From 43eeeecc8ed5fa05652d68032a8bfb1308ee9baa Mon Sep 17 00:00:00 2001
From: Alex Williamson <alex.williamson@redhat.com>
Date: Tue, 24 Mar 2020 09:28:27 -0600
Subject: vfio: Introduce VFIO_DEVICE_FEATURE ioctl and first user

The VFIO_DEVICE_FEATURE ioctl is meant to be a general purpose, device
agnostic ioctl for setting, retrieving, and probing device features.
This implementation provides a 16-bit field for specifying a feature
index, where the data porition of the ioctl is determined by the
semantics for the given feature.  Additional flag bits indicate the
direction and nature of the operation; SET indicates user data is
provided into the device feature, GET indicates the device feature is
written out into user data.  The PROBE flag augments determining
whether the given feature is supported, and if provided, whether the
given operation on the feature is supported.

The first user of this ioctl is for setting the vfio-pci VF token,
where the user provides a shared secret key (UUID) on a SR-IOV PF
device, which users must provide when opening associated VF devices.

Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
---
 include/uapi/linux/vfio.h | 37 +++++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

(limited to 'include/uapi/linux')

diff --git a/include/uapi/linux/vfio.h b/include/uapi/linux/vfio.h
index 9e843a147ead..015516bcfaa3 100644
--- a/include/uapi/linux/vfio.h
+++ b/include/uapi/linux/vfio.h
@@ -707,6 +707,43 @@ struct vfio_device_ioeventfd {
 
 #define VFIO_DEVICE_IOEVENTFD		_IO(VFIO_TYPE, VFIO_BASE + 16)
 
+/**
+ * VFIO_DEVICE_FEATURE - _IORW(VFIO_TYPE, VFIO_BASE + 17,
+ *			       struct vfio_device_feature)
+ *
+ * Get, set, or probe feature data of the device.  The feature is selected
+ * using the FEATURE_MASK portion of the flags field.  Support for a feature
+ * can be probed by setting both the FEATURE_MASK and PROBE bits.  A probe
+ * may optionally include the GET and/or SET bits to determine read vs write
+ * access of the feature respectively.  Probing a feature will return success
+ * if the feature is supported and all of the optionally indicated GET/SET
+ * methods are supported.  The format of the data portion of the structure is
+ * specific to the given feature.  The data portion is not required for
+ * probing.  GET and SET are mutually exclusive, except for use with PROBE.
+ *
+ * Return 0 on success, -errno on failure.
+ */
+struct vfio_device_feature {
+	__u32	argsz;
+	__u32	flags;
+#define VFIO_DEVICE_FEATURE_MASK	(0xffff) /* 16-bit feature index */
+#define VFIO_DEVICE_FEATURE_GET		(1 << 16) /* Get feature into data[] */
+#define VFIO_DEVICE_FEATURE_SET		(1 << 17) /* Set feature from data[] */
+#define VFIO_DEVICE_FEATURE_PROBE	(1 << 18) /* Probe feature support */
+	__u8	data[];
+};
+
+#define VFIO_DEVICE_FEATURE		_IO(VFIO_TYPE, VFIO_BASE + 17)
+
+/*
+ * Provide support for setting a PCI VF Token, which is used as a shared
+ * secret between PF and VF drivers.  This feature may only be set on a
+ * PCI SR-IOV PF when SR-IOV is enabled on the PF and there are no existing
+ * open VFs.  Data provided when setting this feature is a 16-byte array
+ * (__u8 b[16]), representing a UUID.
+ */
+#define VFIO_DEVICE_FEATURE_PCI_VF_TOKEN	(0)
+
 /* -------- API for Type1 VFIO IOMMU -------- */
 
 /**
-- 
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<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/actions/s700-cubieboard7.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/actions/s700-cubieboard7.dts</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
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<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/airoha/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/airoha/Makefile</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
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<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-lts.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-lts.dts</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts</a></td><td class='right'>40</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts</a></td><td class='right'>54</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi</a></td><td class='right'>202</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.9%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab-early-adopter.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab-early-adopter.dts</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts</a></td><td class='right'>48</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts</a></td><td class='right'>32</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi</a></td><td class='right'>236</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 97.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h313-tanix-tx1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h313-tanix-tx1.dts</a></td><td class='right'>194</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h313-x96q.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h313-x96q.dts</a></td><td class='right'>230</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus-v1.2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus-v1.2.dts</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi</a></td><td class='right'>79</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5.dtsi</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-cc.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-cc.dts</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-it.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-it.dts</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h5-cc.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h5-cc.dts</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts</a></td><td class='right'>46</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts</a></td><td class='right'>203</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts</a></td><td class='right'>41</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi</a></td><td class='right'>62</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi</a></td><td class='right'>117</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi</a></td><td class='right'>87</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts</a></td><td class='right'>65</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts</a></td><td class='right'>61</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6-mini.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6-mini.dts</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts</a></td><td class='right'>102</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 1.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi</a></td><td class='right'>192</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi</a></td><td class='right'>243</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 97.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-manta.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-manta.dts</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi</a></td><td class='right'>148</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-pi.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-pi.dts</a></td><td class='right'>63</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi</a></td><td class='right'>126</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi</a></td><td class='right'>141</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts</a></td><td class='right'>149</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts</a></td><td class='right'>218</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi</a></td><td class='right'>1096</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 11.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 88.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h618-longan-module-3h.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h618-longan-module-3h.dtsi</a></td><td class='right'>85</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h618-longanpi-3h.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h618-longanpi-3h.dts</a></td><td class='right'>145</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts</a></td><td class='right'>191</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts</a></td><td class='right'>105</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h618-transpeed-8k618-t.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h618-transpeed-8k618-t.dts</a></td><td class='right'>200</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h618-yuzukihd-chameleon.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h618-yuzukihd-chameleon.dts</a></td><td class='right'>222</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h64-remix-mini-pc.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h64-remix-mini-pc.dts</a></td><td class='right'>356</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts</a></td><td class='right'>381</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-h.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-h.dts</a></td><td class='right'>138</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-plus.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-plus.dts</a></td><td class='right'>53</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-sp.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-sp.dts</a></td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi</a></td><td class='right'>939</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts</a></td><td class='right'>383</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts</a></td><td class='right'>292</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts</a></td><td class='right'>388</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts</a></td><td class='right'>444</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/altera/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/altera/Makefile</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi</a></td><td class='right'>213</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.9%;'/><td class='none' style='width: 97.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts</a></td><td class='right'>73</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts</a></td><td class='right'>79</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts</a></td><td class='right'>105</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amazon/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amazon/Makefile</a> (renamed from arch/arm64/boot/dts/al/Makefile)</td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amazon/alpine-v2-evp.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amazon/alpine-v2-evp.dts</a> (renamed from arch/arm64/boot/dts/al/alpine-v2-evp.dts)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amazon/alpine-v2.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amazon/alpine-v2.dtsi</a> (renamed from arch/arm64/boot/dts/al/alpine-v2.dtsi)</td><td class='right'>43</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amazon/alpine-v3-evp.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amazon/alpine-v3-evp.dts</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amazon/alpine-v3.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amazon/alpine-v3.dtsi</a></td><td class='right'>412</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amd/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amd/Makefile</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dts</a></td><td class='right'>70</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amd/amd-overdrive.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amd/amd-overdrive.dts</a></td><td class='right'>66</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amd/amd-seattle-clks.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amd/amd-seattle-clks.dtsi</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi</a></td><td class='right'>224</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi</a></td><td class='right'>86</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi</a></td><td class='right'>54</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amd/elba-16core.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amd/elba-16core.dtsi</a></td><td class='right'>197</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amd/elba-asic-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amd/elba-asic-common.dtsi</a></td><td class='right'>70</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amd/elba-asic.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amd/elba-asic.dts</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amd/elba-flash-parts.dtsi</a></td><td class='right'>117</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amd/elba.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amd/elba.dtsi</a></td><td class='right'>191</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amd/husky.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amd/husky.dts</a></td><td class='right'>84</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.9%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/Makefile</a></td><td class='right'>85</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/amlogic-a4-a113l2-ba400.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/amlogic-a4-a113l2-ba400.dts</a></td><td class='right'>42</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/amlogic-a4-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/amlogic-a4-common.dtsi</a></td><td class='right'>80</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/amlogic-a4-reset.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/amlogic-a4-reset.h</a></td><td class='right'>93</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi</a></td><td class='right'>241</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/amlogic-a5-a113x2-av400.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/amlogic-a5-a113x2-av400.dts</a></td><td class='right'>42</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/amlogic-a5-reset.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/amlogic-a5-reset.h</a></td><td class='right'>95</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi</a></td><td class='right'>160</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/amlogic-c3-c302x-aw409.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/amlogic-c3-c302x-aw409.dts</a></td><td class='right'>260</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/amlogic-c3-c308l-aw419.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/amlogic-c3-c308l-aw419.dts</a></td><td class='right'>344</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi</a></td><td class='right'>1123</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 11.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 88.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/amlogic-s6-s905x5-bl209.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/amlogic-s6-s905x5-bl209.dts</a></td><td class='right'>42</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi</a></td><td class='right'>222</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/amlogic-s7-s805x3-bp201.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/amlogic-s7-s805x3-bp201.dts</a></td><td class='right'>41</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi</a></td><td class='right'>244</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/amlogic-s7d-s905x5m-bm202.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/amlogic-s7d-s905x5m-bm202.dts</a></td><td class='right'>41</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/amlogic-s7d.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/amlogic-s7d.dtsi</a></td><td class='right'>217</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-an400.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-an400.dts</a></td><td class='right'>39</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts</a></td><td class='right'>54</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/amlogic-t7-reset.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/amlogic-t7-reset.h</a></td><td class='right'>197</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi</a></td><td class='right'>282</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-a1-ad402.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-a1-ad402.dts</a></td><td class='right'>192</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-a1.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-a1.dtsi</a></td><td class='right'>619</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 93.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts</a></td><td class='right'>40</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j110-rev-2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j110-rev-2.dts</a></td><td class='right'>49</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j110-rev-3.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j110-rev-3.dts</a></td><td class='right'>39</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j1xx.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j1xx.dtsi</a></td><td class='right'>334</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-axg-s400.dts</a></td><td class='right'>42</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-axg.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-axg.dtsi</a></td><td class='right'>332</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.1%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 96.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi</a></td><td class='right'>809</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.3%;'/><td class='rem' style='width: 3.1%;'/><td class='none' style='width: 91.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-g12.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12.dtsi</a></td><td class='right'>77</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am-brcm.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am-brcm.dtso</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am-realtek.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am-realtek.dtso</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am.dts</a></td><td class='right'>458</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts</a></td><td class='right'>399</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts</a></td><td class='right'>40</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts</a></td><td class='right'>369</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.7%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 96.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts</a></td><td class='right'>47</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12a.dtsi</a></td><td class='right'>54</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-bananapi-m2s.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12b-a311d-bananapi-m2s.dts</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dts</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-libretech-cc.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12b-a311d-libretech-cc.dts</a></td><td class='right'>117</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi</a></td><td class='right'>42</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4-cm4io.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4-cm4io.dts</a></td><td class='right'>169</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4-mnt-reform2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4-mnt-reform2.dts</a></td><td class='right'>388</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi</a></td><td class='right'>378</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi</a></td><td class='right'>499</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-g12b-dreambox-one.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12b-dreambox-one.dts</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-g12b-dreambox-two.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12b-dreambox-two.dts</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-g12b-dreambox.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12b-dreambox.dtsi</a></td><td class='right'>164</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-g12b-gsking-x.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12b-gsking-x.dts</a></td><td class='right'>159</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-g12b-gtking-pro.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12b-gtking-pro.dts</a></td><td class='right'>143</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-g12b-gtking.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12b-gtking.dts</a></td><td class='right'>165</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi</a></td><td class='right'>98</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 1.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts</a></td><td class='right'>720</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus.dts</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts</a></td><td class='right'>492</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 5.1%;'/><td class='none' style='width: 94.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi</a></td><td class='right'>318</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2l.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2l.dts</a></td><td class='right'>128</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-g12b-odroid.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12b-odroid.dtsi</a></td><td class='right'>435</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts</a></td><td class='right'>503</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-g12b-s922x-bananapi-m2s.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12b-s922x-bananapi-m2s.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi</a></td><td class='right'>57</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-g12b-ugoos-am6.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12b-ugoos-am6.dts</a></td><td class='right'>397</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 4.0%;'/><td class='none' style='width: 95.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi</a></td><td class='right'>413</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12b.dtsi</a></td><td class='right'>98</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi</a></td><td class='right'>103</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gx-mali450.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gx-mali450.dtsi</a></td><td class='right'>61</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi</a></td><td class='right'>111</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gx.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gx.dtsi</a></td><td class='right'>105</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxbb-kii-pro.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxbb-kii-pro.dts</a></td><td class='right'>91</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts</a></td><td class='right'>62</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts</a></td><td class='right'>57</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts</a></td><td class='right'>85</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts</a></td><td class='right'>67</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts</a></td><td class='right'>43</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi</a></td><td class='right'>77</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts</a></td><td class='right'>43</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts</a></td><td class='right'>71</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi</a></td><td class='right'>149</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi</a></td><td class='right'>46</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts</a></td><td class='right'>86</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts</a></td><td class='right'>101</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxl-s805x.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxl-s805x.dtsi</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxl-s805y-xiaomi-aquaman.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxl-s805y-xiaomi-aquaman.dts</a></td><td class='right'>262</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxl-s805y.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxl-s805y.dtsi</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-mecool-kii-pro.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxl-s905d-mecool-kii-pro.dts</a></td><td class='right'>84</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-sml5442tw.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxl-s905d-sml5442tw.dts</a></td><td class='right'>83</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-vero4k-plus.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxl-s905d-vero4k-plus.dts</a></td><td class='right'>115</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts</a></td><td class='right'>245</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-p281.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxl-s905w-p281.dts</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-tx3-mini.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxl-s905w-tx3-mini.dts</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts</a></td><td class='right'>75</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts</a></td><td class='right'>316</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts</a></td><td class='right'>86</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts</a></td><td class='right'>72</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-vero4k.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxl-s905x-vero4k.dts</a></td><td class='right'>204</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxl.dtsi</a></td><td class='right'>196</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxlx-s905l-p271.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxlx-s905l-p271.dts</a></td><td class='right'>51</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxm-gt1-ultimate.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxm-gt1-ultimate.dts</a></td><td class='right'>91</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts</a></td><td class='right'>88</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxm-mecool-kiii-pro.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxm-mecool-kiii-pro.dts</a></td><td class='right'>111</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxm-minix-neo-u9h.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxm-minix-neo-u9h.dts</a></td><td class='right'>117</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts</a></td><td class='right'>68</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxm-q201.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxm-q201.dts</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts</a></td><td class='right'>73</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxm-s912-libretech-pc.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxm-s912-libretech-pc.dts</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxm-tx9-pro.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxm-tx9-pro.dts</a></td><td class='right'>90</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxm-ugoos-am3.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxm-ugoos-am3.dts</a></td><td class='right'>91</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxm-vega-s96.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxm-vega-s96.dts</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxm-wetek-core2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxm-wetek-core2.dts</a></td><td class='right'>85</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxm.dtsi</a></td><td class='right'>96</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-khadas-vim3-ts050.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-khadas-vim3-ts050.dtso</a></td><td class='right'>108</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi</a></td><td class='right'>204</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-libretech-cottonwood.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-libretech-cottonwood.dtsi</a></td><td class='right'>612</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts</a></td><td class='right'>237</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-s4.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-s4.dtsi</a></td><td class='right'>857</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air-gbit.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air-gbit.dts</a></td><td class='right'>132</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air.dts</a></td><td class='right'>111</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi</a></td><td class='right'>290</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m2-pro.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m2-pro.dts</a></td><td class='right'>101</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m5.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m5.dts</a></td><td class='right'>225</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi</a></td><td class='right'>428</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-sm1-h96-max.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-sm1-h96-max.dts</a></td><td class='right'>148</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts</a></td><td class='right'>58</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts</a></td><td class='right'>142</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi</a></td><td class='right'>464</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-sm1-s905d3-libretech-cc.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-sm1-s905d3-libretech-cc.dts</a></td><td class='right'>85</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts</a></td><td class='right'>71</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air-gbit.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-sm1-x96-air-gbit.dts</a></td><td class='right'>136</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-sm1-x96-air.dts</a></td><td class='right'>115</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-sm1.dtsi</a></td><td class='right'>161</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apm/apm-merlin.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apm/apm-merlin.dts</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apm/apm-mustang.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apm/apm-mustang.dts</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apm/apm-shadowcat.dtsi</a></td><td class='right'>71</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apm/apm-storm.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apm/apm-storm.dtsi</a></td><td class='right'>127</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/Makefile</a></td><td class='right'>93</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/multi-die-cpp.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/multi-die-cpp.h</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/s5l8960x-5s.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/s5l8960x-5s.dtsi</a></td><td class='right'>60</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/s5l8960x-air1.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/s5l8960x-air1.dtsi</a></td><td class='right'>56</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/s5l8960x-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/s5l8960x-common.dtsi</a></td><td class='right'>48</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/s5l8960x-j71.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/s5l8960x-j71.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/s5l8960x-j72.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/s5l8960x-j72.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/s5l8960x-j73.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/s5l8960x-j73.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/s5l8960x-j85.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/s5l8960x-j85.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/s5l8960x-j85m.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/s5l8960x-j85m.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/s5l8960x-j86.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/s5l8960x-j86.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/s5l8960x-j86m.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/s5l8960x-j86m.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/s5l8960x-j87.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/s5l8960x-j87.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/s5l8960x-j87m.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/s5l8960x-j87m.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/s5l8960x-mini2.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/s5l8960x-mini2.dtsi</a></td><td class='right'>56</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/s5l8960x-mini3.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/s5l8960x-mini3.dtsi</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/s5l8960x-n51.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/s5l8960x-n51.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/s5l8960x-n53.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/s5l8960x-n53.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/s5l8960x-opp.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/s5l8960x-opp.dtsi</a></td><td class='right'>45</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/s5l8960x-pmgr.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/s5l8960x-pmgr.dtsi</a></td><td class='right'>610</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/s5l8960x.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/s5l8960x.dtsi</a></td><td class='right'>232</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/s5l8965x-opp.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/s5l8965x-opp.dtsi</a></td><td class='right'>45</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/s800-0-3-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/s800-0-3-common.dtsi</a></td><td class='right'>52</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/s800-0-3-pmgr.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/s800-0-3-pmgr.dtsi</a></td><td class='right'>757</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/s800-0-3.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/s800-0-3.dtsi</a></td><td class='right'>249</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/s8000-j71s.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/s8000-j71s.dts</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/s8000-j72s.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/s8000-j72s.dts</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/s8000-n66.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/s8000-n66.dts</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/s8000-n69u.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/s8000-n69u.dts</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/s8000-n71.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/s8000-n71.dts</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/s8000.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/s8000.dtsi</a></td><td class='right'>68</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/s8001-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/s8001-common.dtsi</a></td><td class='right'>49</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/s8001-j127.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/s8001-j127.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/s8001-j128.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/s8001-j128.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/s8001-j98a-j99a.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/s8001-j98a-j99a.dtsi</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/s8001-j98a.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/s8001-j98a.dts</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/s8001-j99a.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/s8001-j99a.dts</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/s8001-pmgr.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/s8001-pmgr.dtsi</a></td><td class='right'>822</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/s8001-pro.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/s8001-pro.dtsi</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/s8001.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/s8001.dtsi</a></td><td class='right'>303</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/s8003-j71t.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/s8003-j71t.dts</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/s8003-j72t.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/s8003-j72t.dts</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/s8003-n66m.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/s8003-n66m.dts</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/s8003-n69.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/s8003-n69.dts</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/s8003-n71m.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/s8003-n71m.dts</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/s8003.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/s8003.dtsi</a></td><td class='right'>68</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/s800x-6s.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/s800x-6s.dtsi</a></td><td class='right'>53</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/s800x-ipad5.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/s800x-ipad5.dtsi</a></td><td class='right'>47</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/s800x-se.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/s800x-se.dtsi</a></td><td class='right'>53</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/spi1-nvram.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/spi1-nvram.dtsi</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t6000-j314s.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t6000-j314s.dts</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t6000-j316s.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t6000-j316s.dts</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t6000.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t6000.dtsi</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t6001-j314c.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t6001-j314c.dts</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t6001-j316c.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t6001-j316c.dts</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t6001-j375c.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t6001-j375c.dts</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t6001.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t6001.dtsi</a></td><td class='right'>68</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t6002-j375d.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t6002-j375d.dts</a></td><td class='right'>58</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t6002.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t6002.dtsi</a></td><td class='right'>306</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t600x-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t600x-common.dtsi</a></td><td class='right'>415</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t600x-die0.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t600x-die0.dtsi</a></td><td class='right'>522</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t600x-dieX.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t600x-dieX.dtsi</a></td><td class='right'>121</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t600x-gpio-pins.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t600x-gpio-pins.dtsi</a></td><td class='right'>59</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi</a></td><td class='right'>133</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t600x-j375.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t600x-j375.dtsi</a></td><td class='right'>141</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t600x-nvme.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t600x-nvme.dtsi</a></td><td class='right'>42</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t600x-pmgr.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t600x-pmgr.dtsi</a></td><td class='right'>2012</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 20.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 79.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t6020-j414s.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t6020-j414s.dts</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t6020-j416s.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t6020-j416s.dts</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t6020-j474s.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t6020-j474s.dts</a></td><td class='right'>47</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t6020.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t6020.dtsi</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t6021-j414c.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t6021-j414c.dts</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t6021-j416c.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t6021-j416c.dts</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t6021-j475c.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t6021-j475c.dts</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t6021.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t6021.dtsi</a></td><td class='right'>69</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t6022-j180d.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t6022-j180d.dts</a></td><td class='right'>121</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t6022-j475d.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t6022-j475d.dts</a></td><td class='right'>42</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t6022-jxxxd.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t6022-jxxxd.dtsi</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t6022.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t6022.dtsi</a></td><td class='right'>349</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t602x-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t602x-common.dtsi</a></td><td class='right'>465</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t602x-die0.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t602x-die0.dtsi</a></td><td class='right'>575</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t602x-dieX.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t602x-dieX.dtsi</a></td><td class='right'>128</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t602x-gpio-pins.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t602x-gpio-pins.dtsi</a></td><td class='right'>81</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t602x-j414-j416.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t602x-j414-j416.dtsi</a></td><td class='right'>45</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t602x-j474-j475.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t602x-j474-j475.dtsi</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t602x-nvme.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t602x-nvme.dtsi</a></td><td class='right'>42</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t602x-pmgr.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t602x-pmgr.dtsi</a></td><td class='right'>2265</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 23.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 76.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t7000-6.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t7000-6.dtsi</a></td><td class='right'>58</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t7000-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t7000-common.dtsi</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t7000-handheld.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t7000-handheld.dtsi</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t7000-j42d.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t7000-j42d.dts</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t7000-j96.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t7000-j96.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t7000-j97.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t7000-j97.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t7000-mini4.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t7000-mini4.dtsi</a></td><td class='right'>63</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t7000-n102.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t7000-n102.dts</a></td><td class='right'>52</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t7000-n56.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t7000-n56.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t7000-n61.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t7000-n61.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t7000-pmgr.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t7000-pmgr.dtsi</a></td><td class='right'>641</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t7000.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t7000.dtsi</a></td><td class='right'>287</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t7001-air2.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t7001-air2.dtsi</a></td><td class='right'>75</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t7001-j81.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t7001-j81.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t7001-j82.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t7001-j82.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t7001-pmgr.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t7001-pmgr.dtsi</a></td><td class='right'>650</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t7001.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t7001.dtsi</a></td><td class='right'>280</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8010-7.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8010-7.dtsi</a></td><td class='right'>55</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8010-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8010-common.dtsi</a></td><td class='right'>52</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8010-d10.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8010-d10.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8010-d101.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8010-d101.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8010-d11.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8010-d11.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8010-d111.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8010-d111.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8010-ipad6.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8010-ipad6.dtsi</a></td><td class='right'>56</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8010-ipad7.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8010-ipad7.dtsi</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8010-j171.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8010-j171.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8010-j172.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8010-j172.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8010-j71b.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8010-j71b.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8010-j72b.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8010-j72b.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8010-n112.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8010-n112.dts</a></td><td class='right'>51</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8010-pmgr.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8010-pmgr.dtsi</a></td><td class='right'>772</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8010.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8010.dtsi</a></td><td class='right'>337</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8011-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8011-common.dtsi</a></td><td class='right'>47</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8011-j105a.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8011-j105a.dts</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8011-j120.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8011-j120.dts</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8011-j121.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8011-j121.dts</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8011-j207.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8011-j207.dts</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8011-j208.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8011-j208.dts</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8011-pmgr.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8011-pmgr.dtsi</a></td><td class='right'>806</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8011-pro2.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8011-pro2.dtsi</a></td><td class='right'>50</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8011.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8011.dtsi</a></td><td class='right'>334</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8012-j132.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8012-j132.dts</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8012-j137.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8012-j137.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8012-j140a.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8012-j140a.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8012-j140k.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8012-j140k.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8012-j152f.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8012-j152f.dts</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8012-j160.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8012-j160.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8012-j174.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8012-j174.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8012-j185.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8012-j185.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8012-j185f.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8012-j185f.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8012-j213.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8012-j213.dts</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8012-j214k.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8012-j214k.dts</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8012-j215.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8012-j215.dts</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8012-j223.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8012-j223.dts</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8012-j230k.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8012-j230k.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8012-j680.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8012-j680.dts</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8012-j780.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8012-j780.dts</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8012-jxxx.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8012-jxxx.dtsi</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8012-pmgr.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8012-pmgr.dtsi</a></td><td class='right'>837</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8012-touchbar.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8012-touchbar.dtsi</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8012.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8012.dtsi</a></td><td class='right'>302</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8015-8.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8015-8.dtsi</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8015-8plus.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8015-8plus.dtsi</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8015-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8015-common.dtsi</a></td><td class='right'>49</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8015-d20.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8015-d20.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8015-d201.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8015-d201.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8015-d21.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8015-d21.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8015-d211.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8015-d211.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8015-d22.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8015-d22.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8015-d221.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8015-d221.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8015-pmgr.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8015-pmgr.dtsi</a></td><td class='right'>932</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8015-x.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8015-x.dtsi</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8015.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8015.dtsi</a></td><td class='right'>535</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8103-j274.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8103-j274.dts</a></td><td class='right'>63</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8103-j293.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8103-j293.dts</a></td><td class='right'>121</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8103-j313.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8103-j313.dts</a></td><td class='right'>43</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8103-j456.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8103-j456.dts</a></td><td class='right'>77</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8103-j457.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8103-j457.dts</a></td><td class='right'>58</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8103-jxxx.dtsi</a></td><td class='right'>94</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8103-pmgr.dtsi</a></td><td class='right'>1133</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 11.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 88.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8103.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8103.dtsi</a></td><td class='right'>1137</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 11.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 88.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8112-j413.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8112-j413.dts</a></td><td class='right'>80</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8112-j415.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8112-j415.dts</a></td><td class='right'>80</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8112-j473.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8112-j473.dts</a></td><td class='right'>54</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8112-j493.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8112-j493.dts</a></td><td class='right'>135</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8112-jxxx.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8112-jxxx.dtsi</a></td><td class='right'>83</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8112-pmgr.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8112-pmgr.dtsi</a></td><td class='right'>1140</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 11.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 88.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/apple/t8112.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apple/t8112.dtsi</a></td><td class='right'>1176</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 12.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 87.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/arm/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/arm/Makefile</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/arm/corstone1000-fvp.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/arm/corstone1000-fvp.dts</a></td><td class='right'>77</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/arm/corstone1000-mps3.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/arm/corstone1000-mps3.dts</a></td><td class='right'>32</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/arm/corstone1000.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/arm/corstone1000.dtsi</a></td><td class='right'>161</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/arm/foundation-v8-gicv2.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/arm/foundation-v8-gicv2.dtsi</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/arm/foundation-v8-gicv3.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/arm/foundation-v8-gicv3.dtsi</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/arm/foundation-v8.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/arm/foundation-v8.dtsi</a></td><td class='right'>157</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/arm/fvp-base-revc.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/arm/fvp-base-revc.dts</a></td><td class='right'>219</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.9%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/arm/juno-base.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/arm/juno-base.dtsi</a></td><td class='right'>301</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.4%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 96.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/arm/juno-clocks.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/arm/juno-clocks.dtsi</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi</a></td><td class='right'>39</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/arm/juno-motherboard.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/arm/juno-motherboard.dtsi</a></td><td class='right'>217</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 1.0%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/arm/juno-r1-scmi.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/arm/juno-r1-scmi.dts</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/arm/juno-r1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/arm/juno-r1.dts</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/arm/juno-r2-scmi.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/arm/juno-r2-scmi.dts</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/arm/juno-r2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/arm/juno-r2.dts</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/arm/juno-scmi.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/arm/juno-scmi.dts</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/arm/juno-scmi.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/arm/juno-scmi.dtsi</a></td><td class='right'>223</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/arm/juno.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/arm/juno.dts</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/arm/morello-fvp.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/arm/morello-fvp.dts</a></td><td class='right'>77</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/arm/morello-sdp.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/arm/morello-sdp.dts</a></td><td class='right'>157</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/arm/morello.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/arm/morello.dtsi</a></td><td class='right'>323</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi</a></td><td class='right'>176</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.9%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts</a></td><td class='right'>69</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>l---------</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/arm/vexpress-v2m-rs1.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/arm/vexpress-v2m-rs1.dtsi</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/axiado/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/axiado/Makefile</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/axiado/ax3000-evk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/axiado/ax3000-evk.dts</a></td><td class='right'>82</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/axiado/ax3000.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/axiado/ax3000.dtsi</a></td><td class='right'>520</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/bitmain/bm1880.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/bitmain/bm1880.dtsi</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/blaize/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/blaize/Makefile</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts</a></td><td class='right'>119</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi</a></td><td class='right'>217</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/Makefile</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dts</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/bcm2711-rpi-cm4-io.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/bcm2711-rpi-cm4-io.dts</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/bcm2712-d-rpi-5-b.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/bcm2712-d-rpi-5-b.dts</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-ovl-rp1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-ovl-rp1.dts</a></td><td class='right'>254</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts</a></td><td class='right'>68</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/bcm2712.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/bcm2712.dtsi</a></td><td class='right'>671</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/bcm2837-rpi-2-b.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/bcm2837-rpi-2-b.dts</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-a-plus.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-a-plus.dts</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b-plus.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b-plus.dts</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/bcm2837-rpi-cm3-io3.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/bcm2837-rpi-cm3-io3.dts</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/bcm2837-rpi-zero-2-w.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/bcm2837-rpi-zero-2-w.dts</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/bcmbca/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/bcmbca/Makefile</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts</a></td><td class='right'>170</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts</a></td><td class='right'>191</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-zyxel-ex3510b.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-zyxel-ex3510b.dts</a></td><td class='right'>196</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/bcmbca/bcm4906.dtsi</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts</a></td><td class='right'>212</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-netgear-raxe500.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-netgear-raxe500.dts</a></td><td class='right'>50</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi</a></td><td class='right'>757</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912-asus-gt-ax6000.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/bcmbca/bcm4912-asus-gt-ax6000.dts</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi</a></td><td class='right'>164</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi</a></td><td class='right'>145</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi</a></td><td class='right'>292</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi</a></td><td class='right'>164</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi</a></td><td class='right'>265</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi</a></td><td class='right'>291</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts</a></td><td class='right'>43</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/rp1-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/rp1-common.dtsi</a></td><td class='right'>86</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/rp1-nexus.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/rp1-nexus.dtsi</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/rp1.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/rp1.dtso</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi</a></td><td class='right'>66</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/stingray/bcm958802a802x.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/stingray/bcm958802a802x.dts</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/stingray/stingray-board-base.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/stingray/stingray-board-base.dtsi</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/stingray/stingray-pcie.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/stingray/stingray-pcie.dtsi</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi</a></td><td class='right'>52</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/stingray/stingray-sata.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/stingray/stingray-sata.dtsi</a></td><td class='right'>278</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 2.9%;'/><td class='none' style='width: 97.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi</a></td><td class='right'>48</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/bst/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/bst/Makefile</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/bst/bstc1200.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/bst/bstc1200.dtsi</a></td><td class='right'>97</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/cavium/thunder-88xx.dtsi</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/cavium/thunder2-99xx.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/cavium/thunder2-99xx.dts</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/cix/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/cix/Makefile</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/cix/sky1-orion-o6.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/cix/sky1-orion-o6.dts</a></td><td class='right'>91</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/cix/sky1-pinfunc.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/cix/sky1-pinfunc.h</a></td><td class='right'>401</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/cix/sky1.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/cix/sky1.dtsi</a></td><td class='right'>586</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/Makefile</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/axis/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/axis/Makefile</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/axis/artpec-pinctrl.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/axis/artpec-pinctrl.h</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/axis/artpec8-grizzly.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/axis/artpec8-grizzly.dts</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi</a></td><td class='right'>120</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/axis/artpec8.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/axis/artpec8.dtsi</a></td><td class='right'>244</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/exynos-pinctrl.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynos-pinctrl.h</a></td><td class='right'>79</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/exynos2200-g0s.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynos2200-g0s.dts</a></td><td class='right'>169</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/exynos2200-pinctrl.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynos2200-pinctrl.dtsi</a></td><td class='right'>1765</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 18.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 81.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/exynos2200.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynos2200.dtsi</a></td><td class='right'>1923</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 20.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 80.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi</a></td><td class='right'>215</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 1.1%;'/><td class='none' style='width: 97.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi</a></td><td class='right'>383</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.2%;'/><td class='rem' style='width: 1.8%;'/><td class='none' style='width: 96.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynos5433-tm2.dts</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/exynos5433.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynos5433.dtsi</a></td><td class='right'>379</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.7%;'/><td class='rem' style='width: 1.2%;'/><td class='none' style='width: 96.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/exynos7-espresso.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynos7-espresso.dts</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi</a></td><td class='right'>248</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 1.3%;'/><td class='none' style='width: 97.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/exynos7.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynos7.dtsi</a></td><td class='right'>254</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.9%;'/><td class='none' style='width: 97.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/exynos7870-a2corelte.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynos7870-a2corelte.dts</a></td><td class='right'>660</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/exynos7870-j6lte.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynos7870-j6lte.dts</a></td><td class='right'>624</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/exynos7870-on7xelte.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynos7870-on7xelte.dts</a></td><td class='right'>692</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/exynos7870-pinctrl.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynos7870-pinctrl.dtsi</a></td><td class='right'>1021</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 10.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 89.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/exynos7870.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynos7870.dtsi</a></td><td class='right'>797</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts</a></td><td class='right'>113</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi</a></td><td class='right'>855</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/exynos7885.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynos7885.dtsi</a></td><td class='right'>470</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynos850-e850-96.dts</a></td><td class='right'>285</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi</a></td><td class='right'>663</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/exynos850.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynos850.dtsi</a></td><td class='right'>915</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/exynos8895-dreamlte.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynos8895-dreamlte.dts</a></td><td class='right'>198</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/exynos8895-pinctrl.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynos8895-pinctrl.dtsi</a></td><td class='right'>1094</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 11.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 88.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/exynos8895.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynos8895.dtsi</a></td><td class='right'>1374</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 14.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 85.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/exynos9810-pinctrl.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynos9810-pinctrl.dtsi</a></td><td class='right'>503</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/exynos9810-starlte.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynos9810-starlte.dts</a></td><td class='right'>119</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/exynos9810.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynos9810.dtsi</a></td><td class='right'>273</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/exynos990-c1s.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynos990-c1s.dts</a></td><td class='right'>131</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/exynos990-pinctrl.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynos990-pinctrl.dtsi</a></td><td class='right'>2195</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 22.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 77.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/exynos990-r8s.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynos990-r8s.dts</a></td><td class='right'>131</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/exynos990-x1s-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynos990-x1s-common.dtsi</a></td><td class='right'>114</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/exynos990-x1s.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynos990-x1s.dts</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/exynos990-x1slte.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynos990-x1slte.dts</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/exynos990.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynos990.dtsi</a></td><td class='right'>418</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/exynosautov9-pinctrl.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynosautov9-pinctrl.dtsi</a></td><td class='right'>1189</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 12.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 87.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts</a></td><td class='right'>139</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/exynosautov9.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynosautov9.dtsi</a></td><td class='right'>1639</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 17.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 83.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/exynosautov920-pinctrl.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynosautov920-pinctrl.dtsi</a></td><td class='right'>1266</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 13.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 86.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts</a></td><td class='right'>88</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/exynosautov920.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynosautov920.dtsi</a></td><td class='right'>1535</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 15.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 84.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/google/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/google/Makefile</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/google/gs101-oriole.dts</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/google/gs101-pinctrl.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/google/gs101-pinctrl.dtsi</a></td><td class='right'>1249</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 13.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 87.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/google/gs101-pinctrl.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/google/gs101-pinctrl.h</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/google/gs101-pixel-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/google/gs101-pixel-common.dtsi</a></td><td class='right'>397</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/google/gs101-raven.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/google/gs101-raven.dts</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/exynos/google/gs101.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/google/gs101.dtsi</a></td><td class='right'>1823</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 18.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 81.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/Makefile</a></td><td class='right'>412</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls1012a-oxalis.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1012a-oxalis.dts</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts</a></td><td class='right'>66</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls1012a-tqmls1012al-mbls1012al-emmc.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1012a-tqmls1012al-mbls1012al-emmc.dts</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls1012a-tqmls1012al-mbls1012al.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1012a-tqmls1012al-mbls1012al.dts</a></td><td class='right'>366</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls1012a-tqmls1012al.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1012a-tqmls1012al.dtsi</a></td><td class='right'>81</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi</a></td><td class='right'>303</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.9%;'/><td class='rem' style='width: 1.2%;'/><td class='none' style='width: 96.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dts</a></td><td class='right'>43</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts</a></td><td class='right'>61</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var2.dts</a></td><td class='right'>40</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dts</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3.dts</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts</a></td><td class='right'>54</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts</a></td><td class='right'>287</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.3%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 97.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dtso</a></td><td class='right'>91</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dtso</a></td><td class='right'>85</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dtso</a></td><td class='right'>69</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dtso</a></td><td class='right'>85</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dtso</a></td><td class='right'>61</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dtso</a></td><td class='right'>68</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts</a></td><td class='right'>173</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts</a></td><td class='right'>177</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi</a></td><td class='right'>717</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.5%;'/><td class='rem' style='width: 1.9%;'/><td class='none' style='width: 92.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts</a></td><td class='right'>181</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts</a></td><td class='right'>73</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls1043a-tqmls1043a-mbls10xxa.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1043a-tqmls1043a-mbls10xxa.dts</a></td><td class='right'>61</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls1043a-tqmls1043a.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1043a-tqmls1043a.dtsi</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi</a></td><td class='right'>682</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.9%;'/><td class='rem' style='width: 2.2%;'/><td class='none' style='width: 92.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy.dts</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts</a></td><td class='right'>215</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 97.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls1046a-tqmls1046a-mbls10xxa.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1046a-tqmls1046a-mbls10xxa.dts</a></td><td class='right'>76</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls1046a-tqmls1046a.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1046a-tqmls1046a.dtsi</a></td><td class='right'>42</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi</a></td><td class='right'>530</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.9%;'/><td class='rem' style='width: 1.7%;'/><td class='none' style='width: 94.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts</a></td><td class='right'>143</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts</a></td><td class='right'>435</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls1088a-tqmls1088a-mbls10xxa.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1088a-tqmls1088a-mbls10xxa.dts</a></td><td class='right'>72</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls1088a-tqmls1088a.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1088a-tqmls1088a.dtsi</a></td><td class='right'>42</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi</a></td><td class='right'>568</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.4%;'/><td class='rem' style='width: 1.5%;'/><td class='none' style='width: 94.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts</a></td><td class='right'>69</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi</a></td><td class='right'>52</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts</a></td><td class='right'>132</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts</a></td><td class='right'>124</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi</a></td><td class='right'>48</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi</a></td><td class='right'>79</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi</a></td><td class='right'>934</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.3%;'/><td class='rem' style='width: 2.4%;'/><td class='none' style='width: 90.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3-rev-a.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3-rev-a.dts</a></td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3.dts</a></td><td class='right'>662</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi</a></td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi</a></td><td class='right'>88</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts</a></td><td class='right'>217</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts</a></td><td class='right'>163</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi</a></td><td class='right'>169</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a.dts</a></td><td class='right'>338</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_12_x_x.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_12_x_x.dtso</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_14_x_x.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_14_x_x.dtso</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_x_11_x.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_x_11_x.dtso</a></td><td class='right'>49</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_x_7_x.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_x_7_x.dtso</a></td><td class='right'>55</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_x_8_x.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_x_8_x.dtso</a></td><td class='right'>47</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a.dtsi</a></td><td class='right'>97</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi</a></td><td class='right'>912</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.2%;'/><td class='rem' style='width: 1.2%;'/><td class='none' style='width: 90.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts</a></td><td class='right'>377</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts</a></td><td class='right'>357</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi</a></td><td class='right'>82</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx-pcie0-ep.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx-pcie0-ep.dtso</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx-pcie1-ep.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx-pcie1-ep.dtso</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8-apalis-eval-v1.1.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8-apalis-eval-v1.1.dtsi</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8-apalis-eval-v1.2.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8-apalis-eval-v1.2.dtsi</a></td><td class='right'>193</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi</a></td><td class='right'>150</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi</a></td><td class='right'>247</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi</a></td><td class='right'>299</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi</a></td><td class='right'>1649</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 17.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 82.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi</a></td><td class='right'>751</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi</a></td><td class='right'>91</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8-ss-cm41.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8-ss-cm41.dtsi</a></td><td class='right'>68</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi</a></td><td class='right'>386</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi</a></td><td class='right'>566</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8-ss-gpu0.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8-ss-gpu0.dtsi</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi</a></td><td class='right'>143</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi</a></td><td class='right'>426</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi</a></td><td class='right'>387</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi</a></td><td class='right'>63</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8-ss-lvds1.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8-ss-lvds1.dtsi</a></td><td class='right'>114</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8-ss-mipi0.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8-ss-mipi0.dtsi</a></td><td class='right'>129</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8-ss-mipi1.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8-ss-mipi1.dtsi</a></td><td class='right'>138</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8-ss-security.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8-ss-security.dtsi</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi</a></td><td class='right'>74</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8dx-colibri-aster.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8dx-colibri-aster.dts</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8dx-colibri-eval-v3.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8dx-colibri-eval-v3.dts</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8dx-colibri-iris-v2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8dx-colibri-iris-v2.dts</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8dx-colibri-iris.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8dx-colibri-iris.dts</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8dx-colibri.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8dx-colibri.dtsi</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8dx.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8dx.dtsi</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8dxl-evk.dts</a></td><td class='right'>1036</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 10.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 89.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi</a></td><td class='right'>260</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi</a></td><td class='right'>171</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi</a></td><td class='right'>61</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi</a></td><td class='right'>120</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8dxl.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8dxl.dtsi</a></td><td class='right'>263</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8dxp-tqma8xdp-mba8xx.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8dxp-tqma8xdp-mba8xx.dts</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8dxp-tqma8xdp.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8dxp-tqma8xdp.dtsi</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8dxp-tqma8xdps-mb-smarc-2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8dxp-tqma8xdps-mb-smarc-2.dts</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8dxp-tqma8xdps.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8dxp-tqma8xdps.dtsi</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8dxp.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8dxp.dtsi</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi</a></td><td class='right'>503</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-beacon-kit.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-beacon-kit.dts</a></td><td class='right'>151</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi</a></td><td class='right'>481</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts</a></td><td class='right'>1022</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 10.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 89.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts</a></td><td class='right'>56</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dts</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dtsi</a></td><td class='right'>139</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi</a></td><td class='right'>625</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-emtop-baseboard.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-emtop-baseboard.dts</a></td><td class='right'>398</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-emtop-som.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-emtop-som.dtsi</a></td><td class='right'>261</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-evk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-evk.dts</a></td><td class='right'>547</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 5.0%;'/><td class='none' style='width: 94.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi</a></td><td class='right'>861</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-evkb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-evkb.dts</a></td><td class='right'>128</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-ctouch2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-ctouch2.dts</a></td><td class='right'>96</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts</a></td><td class='right'>96</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm.dtsi</a></td><td class='right'>232</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15-evk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15-evk.dts</a></td><td class='right'>146</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi</a></td><td class='right'>477</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-iot-gateway.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-iot-gateway.dts</a></td><td class='right'>218</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-lte.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-lte.dtso</a></td><td class='right'>186</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts</a></td><td class='right'>248</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts</a></td><td class='right'>498</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-kontron-dl.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-kontron-dl.dtso</a></td><td class='right'>200</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi</a></td><td class='right'>891</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi</a></td><td class='right'>314</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts</a></td><td class='right'>335</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts</a></td><td class='right'>701</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-overdrive.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-overdrive.dtsi</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-phg.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-phg.dts</a></td><td class='right'>358</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10-etml1010g3dra.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10-etml1010g3dra.dtso</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10-ph128800t006.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10-ph128800t006.dtso</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10.dtsi</a></td><td class='right'>189</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10.dtso</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-eval-01.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-eval-01.dtso</a></td><td class='right'>71</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts</a></td><td class='right'>526</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-phycore-no-eth.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-phycore-no-eth.dtso</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-phycore-no-spiflash.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-phycore-no-spiflash.dtso</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-phycore-rpmsg.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-phycore-rpmsg.dtso</a></td><td class='right'>58</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi</a></td><td class='right'>459</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l-rs232-rs232.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l-rs232-rs232.dtso</a></td><td class='right'>67</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l-rs232-rs485.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l-rs232-rs485.dtso</a></td><td class='right'>71</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l-rs232-rts-cts.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l-rs232-rts-cts.dtso</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts</a></td><td class='right'>511</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-prt8mm.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-prt8mm.dts</a></td><td class='right'>304</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtso</a></td><td class='right'>45</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts</a></td><td class='right'>302</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi</a></td><td class='right'>352</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-ucm-som.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-ucm-som.dtsi</a></td><td class='right'>679</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts</a></td><td class='right'>254</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi</a></td><td class='right'>556</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi</a></td><td class='right'>551</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx-0x.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx-0x.dts</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi</a></td><td class='right'>233</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-imx219.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-imx219.dtso</a></td><td class='right'>109</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rpidsi.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rpidsi.dtso</a></td><td class='right'>90</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs232-rts.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs232-rts.dtso</a></td><td class='right'>48</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs422.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs422.dtso</a></td><td class='right'>57</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs485.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs485.dtso</a></td><td class='right'>57</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x.dts</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi</a></td><td class='right'>394</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-imx219.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-imx219.dtso</a></td><td class='right'>109</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rpidsi.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rpidsi.dtso</a></td><td class='right'>90</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs232-rts.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs232-rts.dtso</a></td><td class='right'>48</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs422.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs422.dtso</a></td><td class='right'>57</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs485.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs485.dtso</a></td><td class='right'>57</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x.dts</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi</a></td><td class='right'>456</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-venice-gw75xx-0x.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-venice-gw75xx-0x.dts</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-venice-gw75xx.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-venice-gw75xx.dtsi</a></td><td class='right'>319</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts</a></td><td class='right'>1195</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 12.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 87.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts</a></td><td class='right'>1088</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 11.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 88.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts</a></td><td class='right'>876</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts</a></td><td class='right'>929</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi</a></td><td class='right'>191</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi</a></td><td class='right'>165</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-verdin-ivy.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-verdin-ivy.dtsi</a></td><td class='right'>471</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-verdin-mallow.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-verdin-mallow.dtsi</a></td><td class='right'>173</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dahlia.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dahlia.dts</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dev.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dev.dts</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-ivy.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-ivy.dts</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-mallow.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-mallow.dts</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-yavia.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-yavia.dts</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi.dtsi</a></td><td class='right'>75</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dts</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dev.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dev.dts</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-ivy.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-ivy.dts</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-mallow.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-mallow.dts</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-yavia.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-yavia.dts</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi.dtsi</a></td><td class='right'>94</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-verdin-yavia.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-verdin-yavia.dtsi</a></td><td class='right'>174</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi</a></td><td class='right'>1332</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 13.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 86.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mm.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm.dtsi</a></td><td class='right'>913</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.5%;'/><td class='rem' style='width: 2.0%;'/><td class='none' style='width: 90.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi</a></td><td class='right'>442</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mn-beacon-kit.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mn-beacon-kit.dts</a></td><td class='right'>151</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi</a></td><td class='right'>492</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi</a></td><td class='right'>427</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-display.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-display.dtsi</a></td><td class='right'>149</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2.dts</a></td><td class='right'>47</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts</a></td><td class='right'>169</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dts</a></td><td class='right'>130</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts</a></td><td class='right'>69</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mn-dimonoff-gateway-evk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mn-dimonoff-gateway-evk.dts</a></td><td class='right'>160</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mn-evk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mn-evk.dts</a></td><td class='right'>121</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi</a></td><td class='right'>451</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.5%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 95.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mn-overdrive.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mn-overdrive.dtsi</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mn-rve-gateway.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mn-rve-gateway.dts</a></td><td class='right'>285</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtso</a></td><td class='right'>45</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx-usbotg.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx-usbotg.dtso</a></td><td class='right'>89</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts</a></td><td class='right'>246</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi</a></td><td class='right'>338</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts</a></td><td class='right'>237</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi</a></td><td class='right'>570</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts</a></td><td class='right'>1016</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 10.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 89.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mn.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mn.dtsi</a></td><td class='right'>746</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.2%;'/><td class='rem' style='width: 1.5%;'/><td class='none' style='width: 92.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-aipstz.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-aipstz.h</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-adpismarc.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-adpismarc.dts</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-helios-lvds.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-helios-lvds.dtso</a></td><td class='right'>113</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-helios.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-helios.dts</a></td><td class='right'>98</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-proton2s.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-proton2s.dts</a></td><td class='right'>161</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3a-som-v1.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-aristainetos3a-som-v1.dtsi</a></td><td class='right'>1107</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 11.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 88.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts</a></td><td class='right'>837</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi</a></td><td class='right'>497</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-cubox-m.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-cubox-m.dts</a></td><td class='right'>223</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts</a></td><td class='right'>1103</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 11.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 88.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts</a></td><td class='right'>584</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts</a></td><td class='right'>574</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-debix-som-a.dtsi</a></td><td class='right'>307</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-dhcom-drc02.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-dhcom-drc02.dts</a></td><td class='right'>255</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts</a></td><td class='right'>269</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts</a></td><td class='right'>351</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-dhcom-picoitx.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-dhcom-picoitx.dts</a></td><td class='right'>176</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi</a></td><td class='right'>1206</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 12.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 87.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-edm-g-wb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-edm-g-wb.dts</a></td><td class='right'>359</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-edm-g.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-edm-g.dtsi</a></td><td class='right'>786</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-evk-imx-lvds-hdmi-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-evk-imx-lvds-hdmi-common.dtsi</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtso</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi-common.dtsi</a></td><td class='right'>43</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi.dtso</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtso</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi-common.dtsi</a></td><td class='right'>43</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi.dtso</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-evk-mx8-dlvds-lcd1.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-evk-mx8-dlvds-lcd1.dtso</a></td><td class='right'>77</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-evk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-evk.dts</a></td><td class='right'>991</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 10.0%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 89.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-mate.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-hummingboard-mate.dts</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pro.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pro.dts</a></td><td class='right'>76</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-codec.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-codec.dtsi</a></td><td class='right'>59</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-common.dtsi</a></td><td class='right'>384</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-hdmi.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-hdmi.dtsi</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-m2con.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-m2con.dtsi</a></td><td class='right'>60</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-mini-hdmi.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-mini-hdmi.dtsi</a></td><td class='right'>81</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse.dts</a></td><td class='right'>83</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-ripple.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-hummingboard-ripple.dts</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts</a></td><td class='right'>175</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi</a></td><td class='right'>186</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-iota2-lumpy.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-iota2-lumpy.dts</a></td><td class='right'>423</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-kontron-bl-osm-s.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-kontron-bl-osm-s.dts</a></td><td class='right'>332</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-kontron-dl.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-kontron-dl.dtso</a></td><td class='right'>111</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-kontron-osm-s.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-kontron-osm-s.dtsi</a></td><td class='right'>909</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-kontron-smarc-eval-carrier.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-kontron-smarc-eval-carrier.dts</a></td><td class='right'>254</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-kontron-smarc.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-kontron-smarc.dtsi</a></td><td class='right'>280</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtso</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc.dts</a></td><td class='right'>290</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-14N0600E.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-14N0600E.dtsi</a></td><td class='right'>68</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts</a></td><td class='right'>148</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s.dtsi</a></td><td class='right'>838</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-navqp.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-navqp.dts</a></td><td class='right'>471</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-enc-carrier-board.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-nitrogen-enc-carrier-board.dts</a></td><td class='right'>452</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-smarc-som.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-nitrogen-smarc-som.dtsi</a></td><td class='right'>348</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-smarc-universal-board.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-nitrogen-smarc-universal-board.dts</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-som.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-nitrogen-som.dtsi</a></td><td class='right'>409</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-nominal.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-nominal.dtsi</a></td><td class='right'>110</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-etml1010g3dra.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-etml1010g3dra.dtso</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10-etml1010g3dra.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10-etml1010g3dra.dtso</a></td><td class='right'>45</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10-ph128800t006.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10-ph128800t006.dtso</a></td><td class='right'>45</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10.dtsi</a></td><td class='right'>198</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10.dtso</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-ph128800t006.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-ph128800t006.dtso</a></td><td class='right'>45</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts</a></td><td class='right'>540</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-phycore-fpsc.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-phycore-fpsc.dtsi</a></td><td class='right'>796</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-phycore-no-eth.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-phycore-no-eth.dtso</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi</a></td><td class='right'>325</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h</a></td><td class='right'>393</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 2.6%;'/><td class='none' style='width: 95.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-prt8ml.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-prt8ml.dts</a></td><td class='right'>504</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-skov-basic.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-skov-basic.dts</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi</a></td><td class='right'>798</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-hdmi.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-skov-revb-hdmi.dts</a></td><td class='right'>61</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-lt6.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-skov-revb-lt6.dts</a></td><td class='right'>161</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts</a></td><td class='right'>81</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-skov-revc-bd500.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-skov-revc-bd500.dts</a></td><td class='right'>91</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-skov-revc-hdmi.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-skov-revc-hdmi.dts</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-skov-revc-jutouch-jt101tm023.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-skov-revc-jutouch-jt101tm023.dts</a></td><td class='right'>79</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-skov-revc-tian-g07017.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-skov-revc-tian-g07017.dts</a></td><td class='right'>81</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi</a></td><td class='right'>591</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc-dev.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc-dev.dts</a></td><td class='right'>300</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc.dtsi</a></td><td class='right'>1308</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 13.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 86.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314-imx219.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314-imx219.dtso</a></td><td class='right'>107</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts</a></td><td class='right'>907</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtso</a></td><td class='right'>77</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl-lvds-tm070jvhg33.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl-lvds-tm070jvhg33.dtso</a></td><td class='right'>61</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts</a></td><td class='right'>1021</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 10.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 89.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi</a></td><td class='right'>297</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dtso</a></td><td class='right'>94</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av123z7m-n17.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av123z7m-n17.dtso</a></td><td class='right'>139</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106.dts</a></td><td class='right'>525</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi</a></td><td class='right'>548</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-ultra-mach-sbc.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-ultra-mach-sbc.dts</a></td><td class='right'>907</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi</a></td><td class='right'>455</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi</a></td><td class='right'>561</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx-2x.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx-2x.dts</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi</a></td><td class='right'>255</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx-2x.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx-2x.dts</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi</a></td><td class='right'>415</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx-2x.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx-2x.dts</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi</a></td><td class='right'>468</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx-imx219.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx-imx219.dtso</a></td><td class='right'>107</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx-rpidsi.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx-rpidsi.dtso</a></td><td class='right'>87</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts</a></td><td class='right'>1159</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 12.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 88.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-venice-gw75xx-2x.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-venice-gw75xx-2x.dts</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-venice-gw75xx.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-venice-gw75xx.dtsi</a></td><td class='right'>325</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-venice-gw82xx-2x.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-venice-gw82xx-2x.dts</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-venice-gw82xx.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-venice-gw82xx.dtsi</a></td><td class='right'>533</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi</a></td><td class='right'>288</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi</a></td><td class='right'>269</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-verdin-ivy.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-verdin-ivy.dtsi</a></td><td class='right'>512</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-verdin-mallow.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-verdin-mallow.dtsi</a></td><td class='right'>251</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-dahlia.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-dahlia.dts</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-dev.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-dev.dts</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-ivy.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-ivy.dts</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-mallow.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-mallow.dts</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-yavia.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-yavia.dts</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi.dtsi</a></td><td class='right'>53</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-dahlia.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-dahlia.dts</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-dev.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-dev.dts</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-ivy.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-ivy.dts</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-mallow.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-mallow.dts</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-yavia.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-yavia.dts</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi.dtsi</a></td><td class='right'>85</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi</a></td><td class='right'>269</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi</a></td><td class='right'>1493</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 15.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 84.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mp.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp.dtsi</a></td><td class='right'>2120</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 20.7%;'/><td class='rem' style='width: 1.3%;'/><td class='none' style='width: 78.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mq-evk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mq-evk.dts</a></td><td class='right'>257</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.5%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 97.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mq-hummingboard-pulse.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mq-hummingboard-pulse.dts</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts</a></td><td class='right'>611</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts</a></td><td class='right'>233</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 97.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mq-librem5-r2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mq-librem5-r2.dts</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dts</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dtsi</a></td><td class='right'>49</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mq-librem5-r4.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mq-librem5-r4.dts</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi</a></td><td class='right'>1419</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 14.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 85.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts</a></td><td class='right'>353</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mq-nitrogen-som.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mq-nitrogen-som.dtsi</a></td><td class='right'>278</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts</a></td><td class='right'>198</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mq-sr-som.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mq-sr-som.dtsi</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mq-thor96.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mq-thor96.dts</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx-lvds-tm070jvhg33.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx-lvds-tm070jvhg33.dtso</a></td><td class='right'>49</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts</a></td><td class='right'>332</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi</a></td><td class='right'>362</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dts</a></td><td class='right'>95</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-zest.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-zest.dts</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi</a></td><td class='right'>145</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8mq.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mq.dtsi</a></td><td class='right'>874</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.1%;'/><td class='rem' style='width: 1.0%;'/><td class='none' style='width: 90.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8qm-apalis-eval-v1.2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qm-apalis-eval-v1.2.dts</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8qm-apalis-eval.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qm-apalis-eval.dts</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8qm-apalis-ixora-v1.1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qm-apalis-ixora-v1.1.dts</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-eval-v1.2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-eval-v1.2.dts</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-eval.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-eval.dts</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-ixora-v1.1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-ixora-v1.1.dts</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-ixora-v1.2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-ixora-v1.2.dts</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1.dtsi</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi</a></td><td class='right'>333</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8qm-mek-ov5640-csi0.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qm-mek-ov5640-csi0.dtso</a></td><td class='right'>62</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8qm-mek-ov5640-csi1.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qm-mek-ov5640-csi1.dtso</a></td><td class='right'>62</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8qm-mek.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qm-mek.dts</a></td><td class='right'>1337</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 13.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 86.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi</a></td><td class='right'>475</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi</a></td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi</a></td><td class='right'>211</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi</a></td><td class='right'>229</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi</a></td><td class='right'>91</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi</a></td><td class='right'>107</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi</a></td><td class='right'>76</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8qm.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qm.dtsi</a></td><td class='right'>651</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8qxp-colibri-aster.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qxp-colibri-aster.dts</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dts</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi</a></td><td class='right'>62</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8qxp-colibri-iris-v2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qxp-colibri-iris-v2.dts</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8qxp-colibri-iris.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qxp-colibri-iris.dts</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi</a></td><td class='right'>592</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 6.1%;'/><td class='none' style='width: 93.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640-csi.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640-csi.dtso</a></td><td class='right'>61</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qxp-mek.dts</a></td><td class='right'>914</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 90.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8qxp-ss-hsio.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qxp-ss-hsio.dtsi</a></td><td class='right'>47</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi</a></td><td class='right'>97</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi</a></td><td class='right'>94</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8qxp-ss-security.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qxp-ss-security.dtsi</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8qxp-ss-vpu.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qxp-ss-vpu.dtsi</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8qxp-tqma8xqp-mba8xx.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qxp-tqma8xqp-mba8xx.dts</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8qxp-tqma8xqp.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qxp-tqma8xqp.dtsi</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8qxp-tqma8xqps-mb-smarc-2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qxp-tqma8xqps-mb-smarc-2.dts</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8qxp-tqma8xqps.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qxp-tqma8xqps.dtsi</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8qxp.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qxp.dtsi</a></td><td class='right'>535</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 4.2%;'/><td class='none' style='width: 94.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts</a></td><td class='right'>69</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8ulp-evk.dts</a></td><td class='right'>396</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h</a></td><td class='right'>978</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 10.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 89.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8ulp.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8ulp.dtsi</a></td><td class='right'>863</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8x-colibri-aster.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8x-colibri-aster.dtsi</a></td><td class='right'>80</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi</a></td><td class='right'>132</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8x-colibri-iris-v2.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8x-colibri-iris-v2.dtsi</a></td><td class='right'>45</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8x-colibri-iris.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8x-colibri-iris.dtsi</a></td><td class='right'>150</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi</a></td><td class='right'>999</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 10.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 89.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts</a></td><td class='right'>674</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx91-phyboard-segin.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx91-phyboard-segin.dts</a></td><td class='right'>345</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx91-phycore-som.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx91-phycore-som.dtsi</a></td><td class='right'>304</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx91-pinfunc.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx91-pinfunc.h</a></td><td class='right'>770</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx91-tqma9131-mba91xxca.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx91-tqma9131-mba91xxca.dts</a></td><td class='right'>739</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx91-tqma9131.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx91-tqma9131.dtsi</a></td><td class='right'>295</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx91.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx91.dtsi</a></td><td class='right'>71</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx91_93_common.dtsi</a></td><td class='right'>1187</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 12.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 87.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts</a></td><td class='right'>1058</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 11.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 89.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts</a></td><td class='right'>674</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-i3c.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx93-9x9-qsb-i3c.dtso</a></td><td class='right'>72</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts</a></td><td class='right'>772</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx93-kontron-bl-osm-s.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx93-kontron-bl-osm-s.dts</a></td><td class='right'>194</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi</a></td><td class='right'>636</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx93-phyboard-nash-jtag.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx93-phyboard-nash-jtag.dtso</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx93-phyboard-nash-peb-wlbt-07.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx93-phyboard-nash-peb-wlbt-07.dtso</a></td><td class='right'>88</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx93-phyboard-nash-pwm-fan.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx93-phyboard-nash-pwm-fan.dtso</a></td><td class='right'>75</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts</a></td><td class='right'>367</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx93-phyboard-segin-peb-eval-01.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx93-phyboard-segin-peb-eval-01.dtso</a></td><td class='right'>52</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx93-phyboard-segin-peb-wlbt-05.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx93-phyboard-segin-peb-wlbt-05.dtso</a></td><td class='right'>93</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts</a></td><td class='right'>338</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx93-phycore-rpmsg.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx93-phycore-rpmsg.dtso</a></td><td class='right'>60</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi</a></td><td class='right'>299</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx93-pinfunc.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx93-pinfunc.h</a></td><td class='right'>623</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca.dts</a></td><td class='right'>760</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts</a></td><td class='right'>930</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts</a></td><td class='right'>892</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi</a></td><td class='right'>298</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts</a></td><td class='right'>368</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx93-var-som.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx93-var-som.dtsi</a></td><td class='right'>456</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx93.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx93.dtsi</a></td><td class='right'>161</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx94-clock.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx94-clock.h</a></td><td class='right'>193</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx94-pinfunc.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx94-pinfunc.h</a></td><td class='right'>1570</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 16.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 83.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx94-power.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx94-power.h</a></td><td class='right'>41</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx94.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx94.dtsi</a></td><td class='right'>1200</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 12.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 87.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx943-evk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx943-evk.dts</a></td><td class='right'>627</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx943.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx943.dtsi</a></td><td class='right'>148</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts</a></td><td class='right'>1185</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 12.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 87.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx95-19x19-evk-sof.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx95-19x19-evk-sof.dts</a></td><td class='right'>84</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts</a></td><td class='right'>1144</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 11.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 88.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx95-19x19-verdin-evk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx95-19x19-verdin-evk.dts</a></td><td class='right'>695</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx95-clock.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx95-clock.h</a></td><td class='right'>187</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx95-libra-rdk-fpsc.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx95-libra-rdk-fpsc.dts</a></td><td class='right'>318</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx95-phycore-fpsc.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx95-phycore-fpsc.dtsi</a></td><td class='right'>656</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx95-pinfunc.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx95-pinfunc.h</a></td><td class='right'>865</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx95-power.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx95-power.h</a></td><td class='right'>47</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx95-toradex-smarc-dev.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx95-toradex-smarc-dev.dts</a></td><td class='right'>277</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi</a></td><td class='right'>1155</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 12.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 88.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx95-tqma9596sa-mb-smarc-2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx95-tqma9596sa-mb-smarc-2.dts</a></td><td class='right'>269</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx95-tqma9596sa.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx95-tqma9596sa.dtsi</a></td><td class='right'>803</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/imx95.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx95.dtsi</a></td><td class='right'>2185</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 22.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 77.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/mba8mx.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/mba8mx.dtsi</a></td><td class='right'>387</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/mba8xx.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/mba8xx.dtsi</a></td><td class='right'>582</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/s32g2.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/s32g2.dtsi</a></td><td class='right'>798</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/s32g274a-evb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/s32g274a-evb.dts</a></td><td class='right'>61</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts</a></td><td class='right'>95</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/s32g3.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/s32g3.dtsi</a></td><td class='right'>954</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts</a></td><td class='right'>111</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi</a></td><td class='right'>306</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi</a></td><td class='right'>259</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/s32v234.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/s32v234.dtsi</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/tqma8xx.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/tqma8xx.dtsi</a></td><td class='right'>277</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/tqma8xxs-mb-smarc-2.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/tqma8xxs-mb-smarc-2.dtsi</a></td><td class='right'>201</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/tqma8xxs.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/tqma8xxs.dtsi</a></td><td class='right'>768</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/tqmls104xa-mbls10xxa-fman.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/tqmls104xa-mbls10xxa-fman.dtsi</a></td><td class='right'>104</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/tqmls1088a-mbls10xxa-mc.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/tqmls1088a-mbls10xxa-mc.dtsi</a></td><td class='right'>130</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/tqmls10xxa-mbls10xxa.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/tqmls10xxa-mbls10xxa.dtsi</a></td><td class='right'>157</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/freescale/tqmls10xxa.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/tqmls10xxa.dtsi</a></td><td class='right'>66</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts</a></td><td class='right'>115</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/hisilicon/hi3660.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/hisilicon/hi3660.dtsi</a></td><td class='right'>89</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/hisilicon/hi3670.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/hisilicon/hi3670.dtsi</a></td><td class='right'>88</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi</a></td><td class='right'>82</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi</a></td><td class='right'>132</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts</a></td><td class='right'>467</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.4%;'/><td class='rem' style='width: 2.5%;'/><td class='none' style='width: 95.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/hisilicon/hi6220.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/hisilicon/hi6220.dtsi</a></td><td class='right'>73</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi</a></td><td class='right'>134</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi</a></td><td class='right'>130</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi</a></td><td class='right'>664</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.6%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 93.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi</a></td><td class='right'>82</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/hisilicon/hip05-d02.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/hisilicon/hip05-d02.dts</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/hisilicon/hip05.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/hisilicon/hip05.dtsi</a></td><td class='right'>48</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/hisilicon/hip06-d03.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/hisilicon/hip06-d03.dts</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/hisilicon/hip06.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/hisilicon/hip06.dtsi</a></td><td class='right'>124</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/hisilicon/hip07-d05.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/hisilicon/hip07-d05.dts</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/hisilicon/hip07.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/hisilicon/hip07.dtsi</a></td><td class='right'>313</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 1.5%;'/><td class='none' style='width: 96.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/intel/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/intel/Makefile</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/intel/keembay-evm.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/intel/keembay-evm.dts</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/intel/keembay-soc.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/intel/keembay-soc.dtsi</a></td><td class='right'>123</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/intel/socfpga_agilex.dtsi</a></td><td class='right'>356</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.5%;'/><td class='rem' style='width: 1.2%;'/><td class='none' style='width: 96.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts</a></td><td class='right'>132</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi</a></td><td class='right'>937</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts</a></td><td class='right'>112</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts</a></td><td class='right'>126</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts</a></td><td class='right'>107</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts</a></td><td class='right'>66</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts</a></td><td class='right'>45</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts</a></td><td class='right'>128</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/lg/lg1312-ref.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/lg/lg1312-ref.dts</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/lg/lg1312.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/lg/lg1312.dtsi</a></td><td class='right'>322</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 3.3%;'/><td class='none' style='width: 96.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/lg/lg1313-ref.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/lg/lg1313-ref.dts</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/lg/lg1313.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/lg/lg1313.dtsi</a></td><td class='right'>322</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 3.3%;'/><td class='none' style='width: 96.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/lg/lg131x.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/lg/lg131x.dtsi</a></td><td class='right'>333</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/Makefile</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi</a></td><td class='right'>368</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/ac5-98dx35xx-rd.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/ac5-98dx35xx-rd.dts</a></td><td class='right'>105</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/ac5-98dx35xx.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/ac5-98dx35xx.dtsi</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/ac5x-rd-carrier-cn9131.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/ac5x-rd-carrier-cn9131.dts</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/ac5x-rd-carrier.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/ac5x-rd-carrier.dtsi</a></td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/armada-371x.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-371x.dtsi</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/armada-3720-atlas-v5.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-3720-atlas-v5.dts</a></td><td class='right'>110</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/armada-3720-db.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-3720-db.dts</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/armada-3720-eDPU.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-3720-eDPU.dts</a></td><td class='right'>59</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/armada-3720-espressobin-emmc.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-3720-espressobin-emmc.dts</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts</a></td><td class='right'>197</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts</a></td><td class='right'>48</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi</a></td><td class='right'>67</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts</a></td><td class='right'>237</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts</a></td><td class='right'>180</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 98.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts</a></td><td class='right'>156</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 1.5%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-3720-uDPU.dtsi</a></td><td class='right'>164</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/armada-372x.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-372x.dtsi</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/armada-37xx.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-37xx.dtsi</a></td><td class='right'>75</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/armada-7020.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-7020.dtsi</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/armada-7040-db.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-7040-db.dts</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts</a></td><td class='right'>457</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/armada-7040.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-7040.dtsi</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/armada-70x0.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-70x0.dtsi</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/armada-8020.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-8020.dtsi</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts</a></td><td class='right'>178</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/armada-8040-db.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-8040-db.dts</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi</a></td><td class='right'>53</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts</a></td><td class='right'>523</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/armada-8040.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-8040.dtsi</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/armada-8080.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-8080.dtsi</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/armada-80x0.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-80x0.dtsi</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/armada-ap806.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-ap806.dtsi</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/armada-ap807.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-ap807.dtsi</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-ap80x.dtsi</a></td><td class='right'>73</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/armada-ap810-ap0.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-ap810-ap0.dtsi</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/armada-cp110.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-cp110.dtsi</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/armada-cp115.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-cp115.dtsi</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-cp11x.dtsi</a></td><td class='right'>75</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/cn9130-cf-base.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/cn9130-cf-base.dts</a></td><td class='right'>178</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/cn9130-cf-pro.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/cn9130-cf-pro.dts</a></td><td class='right'>375</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/cn9130-cf.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/cn9130-cf.dtsi</a></td><td class='right'>198</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/cn9130-crb-A.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/cn9130-crb-A.dts</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/cn9130-crb-B.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/cn9130-crb-B.dts</a></td><td class='right'>47</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/cn9130-crb.dtsi</a></td><td class='right'>360</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/cn9130-db-B.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/cn9130-db-B.dts</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi</a></td><td class='right'>96</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/cn9130-db.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/cn9130-db.dts</a></td><td class='right'>393</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 4.0%;'/><td class='none' style='width: 95.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/cn9130-db.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/cn9130-db.dtsi</a></td><td class='right'>407</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/cn9130-sr-som.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/cn9130-sr-som.dtsi</a></td><td class='right'>159</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/cn9130.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/cn9130.dtsi</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts</a></td><td class='right'>639</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/cn9131-db-B.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/cn9131-db-B.dts</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi</a></td><td class='right'>108</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/cn9131-db.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/cn9131-db.dts</a></td><td class='right'>192</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 1.9%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/cn9131-db.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/cn9131-db.dtsi</a></td><td class='right'>205</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/cn9132-clearfog.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/cn9132-clearfog.dts</a></td><td class='right'>671</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/cn9132-db-B.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/cn9132-db-B.dts</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/cn9132-db.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/cn9132-db.dts</a></td><td class='right'>211</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 2.1%;'/><td class='none' style='width: 97.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/cn9132-db.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/cn9132-db.dtsi</a></td><td class='right'>228</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/cn9132-sr-cex7.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/cn9132-sr-cex7.dtsi</a></td><td class='right'>720</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/mmp/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/mmp/Makefile</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/mmp/pxa1908-samsung-coreprimevelte.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/mmp/pxa1908-samsung-coreprimevelte.dts</a></td><td class='right'>530</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/marvell/mmp/pxa1908.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/mmp/pxa1908.dtsi</a></td><td class='right'>349</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/Makefile</a></td><td class='right'>114</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt2712-evb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt2712-evb.dts</a></td><td class='right'>97</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt2712e.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt2712e.dtsi</a></td><td class='right'>315</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.3%;'/><td class='rem' style='width: 1.0%;'/><td class='none' style='width: 96.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt6331.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt6331.dtsi</a></td><td class='right'>284</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt6357.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt6357.dtsi</a></td><td class='right'>277</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt6358.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt6358.dtsi</a></td><td class='right'>356</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt6359.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt6359.dtsi</a></td><td class='right'>307</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt6755-evb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt6755-evb.dts</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt6755.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt6755.dtsi</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt6779-evb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt6779-evb.dts</a></td><td class='right'>32</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt6779.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt6779.dtsi</a></td><td class='right'>288</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt6795-evb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt6795-evb.dts</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts</a></td><td class='right'>494</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt6795.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt6795.dtsi</a></td><td class='right'>958</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.3%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 90.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt6797-evb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt6797-evb.dts</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts</a></td><td class='right'>50</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt6797.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt6797.dtsi</a></td><td class='right'>241</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 97.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt6878-pinfunc.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt6878-pinfunc.h</a></td><td class='right'>1201</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 12.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 87.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt6893-pinfunc.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt6893-pinfunc.h</a></td><td class='right'>1356</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 14.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 85.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts</a></td><td class='right'>178</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts</a></td><td class='right'>133</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt7622.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt7622.dtsi</a></td><td class='right'>237</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.9%;'/><td class='none' style='width: 97.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt7981b-cudy-wr3000-v1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt7981b-cudy-wr3000-v1.dts</a></td><td class='right'>74</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts</a></td><td class='right'>165</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt7981b-xiaomi-ax3000t.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt7981b-xiaomi-ax3000t.dts</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt7981b.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt7981b.dtsi</a></td><td class='right'>302</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt7986a-acelink-ew-7886cax.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt7986a-acelink-ew-7886cax.dts</a></td><td class='right'>171</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-mini.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-mini.dts</a></td><td class='right'>493</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso</a></td><td class='right'>53</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso</a></td><td class='right'>61</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sata.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sata.dtso</a></td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts</a></td><td class='right'>497</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts</a></td><td class='right'>355</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt7986a.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt7986a.dtsi</a></td><td class='right'>665</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts</a></td><td class='right'>213</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt7986b.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt7986b.dtsi</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-emmc.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-emmc.dtso</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-4e.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-4e.dts</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-8x.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-8x.dts</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-cn15.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-cn15.dtso</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-cn18.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-cn18.dtso</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-emmc.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-emmc.dtso</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-sd.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-sd.dtso</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi</a></td><td class='right'>534</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-sd.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-sd.dtso</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi</a></td><td class='right'>471</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt7988a.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt7988a.dtsi</a></td><td class='right'>1039</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 10.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 89.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8167-pinfunc.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8167-pinfunc.h</a></td><td class='right'>744</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8167.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8167.dtsi</a></td><td class='right'>180</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi</a></td><td class='right'>98</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8173-elm.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8173-elm.dts</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi</a></td><td class='right'>1168</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 12.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 87.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8173-evb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8173-evb.dts</a></td><td class='right'>71</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8173.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8173.dtsi</a></td><td class='right'>415</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.7%;'/><td class='rem' style='width: 1.6%;'/><td class='none' style='width: 95.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8183-evb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-evb.dts</a></td><td class='right'>297</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.8%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 96.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219-max98357a.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219-max98357a.dtsi</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219-rt1015p.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219-rt1015p.dtsi</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219.dtsi</a></td><td class='right'>53</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-max98357a.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-max98357a.dtsi</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-rt1015p.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-rt1015p.dtsi</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e-max98357a.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e-max98357a.dtsi</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e-rt1015p.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e-rt1015p.dtsi</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e.dtsi</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dts</a></td><td class='right'>39</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts</a></td><td class='right'>41</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel.dtsi</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14-sku2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14-sku2.dts</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper.dtsi</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dts</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku0.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku0.dts</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku1.dts</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico.dts</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico6.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico6.dts</a></td><td class='right'>109</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow.dtsi</a></td><td class='right'>41</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi</a></td><td class='right'>483</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi</a></td><td class='right'>406</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8183-kukui-katsu-sku32.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-kukui-katsu-sku32.dts</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8183-kukui-katsu-sku38.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-kukui-katsu-sku38.dts</a></td><td class='right'>40</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku32.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku32.dts</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi</a></td><td class='right'>385</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi</a></td><td class='right'>389</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi</a></td><td class='right'>982</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 10.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 89.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h</a></td><td class='right'>1120</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 11.6%;'/><td class='none' style='width: 88.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts</a></td><td class='right'>538</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8183.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183.dtsi</a></td><td class='right'>1817</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 18.7%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 81.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou-sku0.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou-sku0.dts</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou-sku1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou-sku1.dts</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou-sku16.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou-sku16.dts</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou.dtsi</a></td><td class='right'>321</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8186-corsola-krabby.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8186-corsola-krabby.dtsi</a></td><td class='right'>129</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8186-corsola-magneton-sku393216.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8186-corsola-magneton-sku393216.dts</a></td><td class='right'>39</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8186-corsola-magneton-sku393217.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8186-corsola-magneton-sku393217.dts</a></td><td class='right'>39</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8186-corsola-magneton-sku393218.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8186-corsola-magneton-sku393218.dts</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8186-corsola-ponyta-sku0.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8186-corsola-ponyta-sku0.dts</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8186-corsola-ponyta-sku1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8186-corsola-ponyta-sku1.dts</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8186-corsola-ponyta.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8186-corsola-ponyta.dtsi</a></td><td class='right'>49</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8186-corsola-rusty-sku196608.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8186-corsola-rusty-sku196608.dts</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8186-corsola-squirtle.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8186-corsola-squirtle.dts</a></td><td class='right'>107</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8186-corsola-starmie-sku0.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8186-corsola-starmie-sku0.dts</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8186-corsola-starmie-sku1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8186-corsola-starmie-sku1.dts</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8186-corsola-starmie.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8186-corsola-starmie.dtsi</a></td><td class='right'>427</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8186-corsola-steelix-sku131072.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8186-corsola-steelix-sku131072.dts</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8186-corsola-steelix-sku131073.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8186-corsola-steelix-sku131073.dts</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8186-corsola-steelix.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8186-corsola-steelix.dtsi</a></td><td class='right'>206</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacool-sku327681.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacool-sku327681.dts</a></td><td class='right'>57</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacool-sku327683.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacool-sku327683.dts</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacruel-sku262144.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacruel-sku262144.dts</a></td><td class='right'>48</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacruel-sku262148.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacruel-sku262148.dts</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb.dts</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb.dtsi</a></td><td class='right'>92</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi</a></td><td class='right'>1725</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 17.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 82.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8186-evb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8186-evb.dts</a></td><td class='right'>221</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8186.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8186.dtsi</a></td><td class='right'>2521</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 26.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 73.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8188-evb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8188-evb.dts</a></td><td class='right'>389</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku0.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku0.dts</a></td><td class='right'>32</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku1.dts</a></td><td class='right'>59</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku2.dts</a></td><td class='right'>59</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku3.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku3.dts</a></td><td class='right'>32</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku4.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku4.dts</a></td><td class='right'>48</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku5.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku5.dts</a></td><td class='right'>72</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku6.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku6.dts</a></td><td class='right'>72</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku7.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku7.dts</a></td><td class='right'>48</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri.dtsi</a></td><td class='right'>316</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi</a></td><td class='right'>1340</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 13.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 86.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8188.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8188.dtsi</a></td><td class='right'>3555</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 36.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 63.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts</a></td><td class='right'>147</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts</a></td><td class='right'>99</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi</a></td><td class='right'>1484</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 15.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 84.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8192-evb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8192-evb.dts</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8192.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8192.dtsi</a></td><td class='right'>2377</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 24.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 75.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8195-cherry-dojo-r1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8195-cherry-dojo-r1.dts</a></td><td class='right'>119</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts</a></td><td class='right'>55</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r3.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r3.dts</a></td><td class='right'>55</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi</a></td><td class='right'>1625</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 16.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 83.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8195-demo.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8195-demo.dts</a></td><td class='right'>555</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8195-evb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8195-evb.dts</a></td><td class='right'>191</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8195.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8195.dtsi</a></td><td class='right'>4177</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 43.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 56.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8196-gce.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8196-gce.h</a></td><td class='right'>612</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8196-pinfunc.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8196-pinfunc.h</a></td><td class='right'>1574</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 16.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 83.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8365-evk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8365-evk.dts</a></td><td class='right'>797</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8365.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8365.dtsi</a></td><td class='right'>1256</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 13.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 87.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8370-genio-510-evk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8370-genio-510-evk.dts</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8370-grinn-genio-510-sbc.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8370-grinn-genio-510-sbc.dts</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8370.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8370.dtsi</a></td><td class='right'>80</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi</a></td><td class='right'>1370</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 14.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 85.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-700-sbc.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-700-sbc.dts</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-sbc.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-sbc.dtsi</a></td><td class='right'>538</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-som.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-som.dtsi</a></td><td class='right'>210</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk-ufs.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk-ufs.dts</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi</a></td><td class='right'>1230</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 12.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 87.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8395-kontron-3-5-sbc-i1200.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8395-kontron-3-5-sbc-i1200.dts</a></td><td class='right'>1129</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 11.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 88.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l-8-hd-panel.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l-8-hd-panel.dtso</a></td><td class='right'>84</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts</a></td><td class='right'>1079</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 11.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 88.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8516-pumpkin.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8516-pumpkin.dts</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/mt8516.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8516.dtsi</a></td><td class='right'>146</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi</a></td><td class='right'>88</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/microchip/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/microchip/Makefile</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/microchip/sparx5.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/microchip/sparx5.dtsi</a></td><td class='right'>484</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/microchip/sparx5_nand.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/microchip/sparx5_nand.dtsi</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/microchip/sparx5_pcb125.dts</a></td><td class='right'>79</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/microchip/sparx5_pcb134.dts</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi</a></td><td class='right'>914</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts</a></td><td class='right'>40</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/microchip/sparx5_pcb135.dts</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi</a></td><td class='right'>742</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts</a></td><td class='right'>40</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nuvoton/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nuvoton/Makefile</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts</a></td><td class='right'>128</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts</a></td><td class='right'>131</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nuvoton/ma35d1.dtsi</a></td><td class='right'>383</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi</a></td><td class='right'>884</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi</a></td><td class='right'>78</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/Makefile</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra132-norrin.dts</a></td><td class='right'>438</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.6%;'/><td class='rem' style='width: 2.0%;'/><td class='none' style='width: 95.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/tegra132-peripherals-opp.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra132-peripherals-opp.dtsi</a></td><td class='right'>426</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/tegra132.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra132.dtsi</a></td><td class='right'>495</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.4%;'/><td class='rem' style='width: 1.8%;'/><td class='none' style='width: 94.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts</a></td><td class='right'>2493</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 25.1%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 74.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi</a></td><td class='right'>187</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 1.0%;'/><td class='none' style='width: 98.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts</a></td><td class='right'>1229</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 12.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 87.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/tegra186.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra186.dtsi</a></td><td class='right'>987</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.9%;'/><td class='rem' style='width: 1.4%;'/><td class='none' style='width: 89.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi</a></td><td class='right'>250</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 1.0%;'/><td class='none' style='width: 97.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts</a></td><td class='right'>2298</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 23.2%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 76.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0000.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0000.dts</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0001.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0001.dts</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi</a></td><td class='right'>2486</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 25.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 74.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/tegra194-p3668-0000.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra194-p3668-0000.dtsi</a></td><td class='right'>32</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/tegra194-p3668-0001.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra194-p3668-0001.dtsi</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi</a></td><td class='right'>313</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/tegra194.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra194.dtsi</a></td><td class='right'>2190</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 17.4%;'/><td class='rem' style='width: 5.3%;'/><td class='none' style='width: 77.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi</a></td><td class='right'>197</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts</a></td><td class='right'>1293</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 13.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 86.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/tegra210-p2595.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra210-p2595.dtsi</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi</a></td><td class='right'>499</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.5%;'/><td class='rem' style='width: 1.7%;'/><td class='none' style='width: 94.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi</a></td><td class='right'>496</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.4%;'/><td class='rem' style='width: 2.7%;'/><td class='none' style='width: 94.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts</a></td><td class='right'>1625</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 14.6%;'/><td class='rem' style='width: 2.3%;'/><td class='none' style='width: 83.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/tegra210-p3541-0000.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra210-p3541-0000.dts</a></td><td class='right'>59</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/tegra210-peripherals-opp.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra210-peripherals-opp.dtsi</a></td><td class='right'>135</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra210-smaug.dts</a></td><td class='right'>402</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.7%;'/><td class='rem' style='width: 1.4%;'/><td class='none' style='width: 95.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/tegra210.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra210.dtsi</a></td><td class='right'>983</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.5%;'/><td class='rem' style='width: 1.7%;'/><td class='none' style='width: 89.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/tegra234-p3701-0008.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra234-p3701-0008.dtsi</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/tegra234-p3701.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra234-p3701.dtsi</a></td><td class='right'>237</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0008.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0008.dts</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701.dtsi</a></td><td class='right'>547</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts</a></td><td class='right'>476</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi</a></td><td class='right'>258</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0000.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0000.dts</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0005.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0005.dts</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767.dtsi</a></td><td class='right'>289</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts</a></td><td class='right'>40</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/tegra234.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra234.dtsi</a></td><td class='right'>6344</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 65.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 34.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/tegra264-p3834-0008.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra264-p3834-0008.dtsi</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/tegra264-p3971-0089+p3834-0008.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra264-p3971-0089+p3834-0008.dts</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/tegra264-p3971-0089+p3834.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra264-p3971-0089+p3834.dtsi</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/tegra264-p3971-0089.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra264-p3971-0089.dtsi</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/tegra264-p3971.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra264-p3971.dtsi</a></td><td class='right'>112</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/nvidia/tegra264.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra264.dtsi</a></td><td class='right'>3827</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 39.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 60.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/Makefile</a></td><td class='right'>354</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.6%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 96.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/agatti.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/agatti.dtsi</a></td><td class='right'>2750</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 28.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 71.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/apq8016-sbc-d3-camera-mezzanine.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/apq8016-sbc-d3-camera-mezzanine.dtso</a></td><td class='right'>89</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi</a></td><td class='right'>74</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi</a></td><td class='right'>89</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.9%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/apq8016-sbc-usb-host.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/apq8016-sbc-usb-host.dtso</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/apq8016-sbc.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/apq8016-sbc.dts</a></td><td class='right'>739</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi</a></td><td class='right'>682</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 7.1%;'/><td class='none' style='width: 92.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/apq8016-schneider-hmibsc.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/apq8016-schneider-hmibsc.dts</a></td><td class='right'>524</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/apq8039-t2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/apq8039-t2.dts</a></td><td class='right'>413</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/apq8094-sony-xperia-kitakami-karin_windy.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/apq8094-sony-xperia-kitakami-karin_windy.dts</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/apq8096-db820c.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/apq8096-db820c.dts</a></td><td class='right'>1127</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 11.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 88.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi</a></td><td class='right'>1056</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 11.0%;'/><td class='none' style='width: 89.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts</a></td><td class='right'>99</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts</a></td><td class='right'>1242</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 12.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 87.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi</a></td><td class='right'>618</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi</a></td><td class='right'>569</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/hamoa.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/hamoa.dtsi</a></td><td class='right'>9629</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 100.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 0.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts</a></td><td class='right'>125</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts</a></td><td class='right'>129</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/ipq5018.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/ipq5018.dtsi</a></td><td class='right'>994</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 10.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 89.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi</a></td><td class='right'>81</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts</a></td><td class='right'>141</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts</a></td><td class='right'>93</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts</a></td><td class='right'>104</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/ipq5332-rdp474.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/ipq5332-rdp474.dts</a></td><td class='right'>67</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/ipq5332.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/ipq5332.dtsi</a></td><td class='right'>874</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts</a></td><td class='right'>296</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/ipq5424.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/ipq5424.dtsi</a></td><td class='right'>1429</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 14.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 85.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts</a></td><td class='right'>48</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/ipq6018.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/ipq6018.dtsi</a></td><td class='right'>858</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.9%;'/><td class='rem' style='width: 1.1%;'/><td class='none' style='width: 91.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/ipq8074-hk01.dts</a></td><td class='right'>157</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi</a></td><td class='right'>72</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/ipq8074.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/ipq8074.dtsi</a></td><td class='right'>1191</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.8%;'/><td class='rem' style='width: 2.6%;'/><td class='none' style='width: 87.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi</a></td><td class='right'>240</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts</a></td><td class='right'>63</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts</a></td><td class='right'>131</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/ipq9574-rdp449.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/ipq9574-rdp449.dts</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/ipq9574.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/ipq9574.dtsi</a></td><td class='right'>1509</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 15.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 84.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/kodiak.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/kodiak.dtsi</a></td><td class='right'>7750</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 80.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 19.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/lemans-auto.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/lemans-auto.dtsi</a></td><td class='right'>104</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/lemans-evk-camera-csi1-imx577.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/lemans-evk-camera-csi1-imx577.dtso</a></td><td class='right'>97</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/lemans-evk-camera.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/lemans-evk-camera.dtso</a></td><td class='right'>105</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/lemans-evk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/lemans-evk.dts</a></td><td class='right'>804</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/lemans-pmics.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/lemans-pmics.dtsi</a></td><td class='right'>239</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi</a></td><td class='right'>1061</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 11.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 89.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/lemans-ride-ethernet-88ea1512.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/lemans-ride-ethernet-88ea1512.dtsi</a></td><td class='right'>205</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/lemans-ride-ethernet-aqr115c.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/lemans-ride-ethernet-aqr115c.dtsi</a></td><td class='right'>205</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/lemans.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/lemans.dtsi</a></td><td class='right'>8617</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 89.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 10.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/monaco-evk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/monaco-evk.dts</a></td><td class='right'>509</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/monaco-pmics.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/monaco-pmics.dtsi</a></td><td class='right'>50</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/monaco.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/monaco.dtsi</a></td><td class='right'>6230</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 64.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 35.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8216-samsung-fortuna3g.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8216-samsung-fortuna3g.dts</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts</a></td><td class='right'>278</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts</a></td><td class='right'>483</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts</a></td><td class='right'>272</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts</a></td><td class='right'>274</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts</a></td><td class='right'>434</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916-lg-c50.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-lg-c50.dts</a></td><td class='right'>143</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916-lg-m216.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-lg-m216.dts</a></td><td class='right'>254</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts</a></td><td class='right'>506</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.3%;'/><td class='rem' style='width: 2.0%;'/><td class='none' style='width: 94.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts</a></td><td class='right'>394</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916-modem-qdsp6.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-modem-qdsp6.dtsi</a></td><td class='right'>148</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916-motorola-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-motorola-common.dtsi</a></td><td class='right'>156</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916-motorola-harpia.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-motorola-harpia.dts</a></td><td class='right'>147</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916-motorola-osprey.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-motorola-osprey.dts</a></td><td class='right'>105</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916-motorola-surnia.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-motorola-surnia.dts</a></td><td class='right'>83</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916-mtp.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-mtp.dts</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-pins.dtsi</a></td><td class='right'>760</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 7.9%;'/><td class='none' style='width: 92.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi</a></td><td class='right'>157</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi</a></td><td class='right'>642</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.7%;'/><td class='rem' style='width: 2.0%;'/><td class='none' style='width: 93.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts</a></td><td class='right'>147</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts</a></td><td class='right'>82</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi</a></td><td class='right'>108</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916-samsung-e5.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-samsung-e5.dts</a></td><td class='right'>50</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916-samsung-e7.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-samsung-e7.dts</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi</a></td><td class='right'>488</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916-samsung-gprimeltecan.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-samsung-gprimeltecan.dts</a></td><td class='right'>97</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916-samsung-grandmax.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-samsung-grandmax.dts</a></td><td class='right'>96</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916-samsung-grandprimelte.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-samsung-grandprimelte.dts</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi</a></td><td class='right'>273</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916-samsung-gt510.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-samsung-gt510.dts</a></td><td class='right'>225</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916-samsung-gt58.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-samsung-gt58.dts</a></td><td class='right'>186</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916-samsung-j3-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-samsung-j3-common.dtsi</a></td><td class='right'>62</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916-samsung-j3ltetw.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-samsung-j3ltetw.dts</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi</a></td><td class='right'>265</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts</a></td><td class='right'>32</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916-samsung-j5x.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-samsung-j5x.dts</a></td><td class='right'>60</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi</a></td><td class='right'>66</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-samsung-rossa.dts</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts</a></td><td class='right'>585</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916-thwc-uf896.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-thwc-uf896.dts</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916-thwc-ufi001c.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-thwc-ufi001c.dts</a></td><td class='right'>66</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi</a></td><td class='right'>150</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt86518.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-wingtech-wt86518.dts</a></td><td class='right'>87</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt86528.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-wingtech-wt86528.dts</a></td><td class='right'>158</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt865x8.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-wingtech-wt865x8.dtsi</a></td><td class='right'>218</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts</a></td><td class='right'>339</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916-yiming-uz801v3.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-yiming-uz801v3.dts</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8916.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916.dtsi</a></td><td class='right'>3200</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 21.9%;'/><td class='rem' style='width: 11.3%;'/><td class='none' style='width: 66.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8917-xiaomi-riva.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8917-xiaomi-riva.dts</a></td><td class='right'>358</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8917.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8917.dtsi</a></td><td class='right'>1955</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 20.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 79.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8929-pm8916.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8929-pm8916.dtsi</a></td><td class='right'>162</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8929-wingtech-wt82918hd.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8929-wingtech-wt82918hd.dts</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8929.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8929.dtsi</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8937-xiaomi-land.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8937-xiaomi-land.dts</a></td><td class='right'>381</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8937.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8937.dtsi</a></td><td class='right'>2133</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 22.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 77.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8939-asus-z00t.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8939-asus-z00t.dts</a></td><td class='right'>256</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8939-huawei-kiwi.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8939-huawei-kiwi.dts</a></td><td class='right'>245</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8939-longcheer-l9100.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8939-longcheer-l9100.dts</a></td><td class='right'>420</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi</a></td><td class='right'>161</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts</a></td><td class='right'>632</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts</a></td><td class='right'>97</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8939-wingtech-wt82918.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8939-wingtech-wt82918.dts</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8939-wingtech-wt82918.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8939-wingtech-wt82918.dtsi</a></td><td class='right'>255</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8939-wingtech-wt82918hd.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8939-wingtech-wt82918hd.dts</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8939.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8939.dtsi</a></td><td class='right'>2553</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 26.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 73.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts</a></td><td class='right'>255</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8953-motorola-potter.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8953-motorola-potter.dts</a></td><td class='right'>306</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts</a></td><td class='right'>326</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8953-xiaomi-mido.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8953-xiaomi-mido.dts</a></td><td class='right'>331</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8953-xiaomi-tissot.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8953-xiaomi-tissot.dts</a></td><td class='right'>327</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8953-xiaomi-vince.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8953-xiaomi-vince.dts</a></td><td class='right'>362</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8953.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8953.dtsi</a></td><td class='right'>2427</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 25.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 74.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire-kugo.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire-kugo.dts</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire-suzu.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire-suzu.dts</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire.dtsi</a></td><td class='right'>286</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8956.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8956.dtsi</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8976-longcheer-l9360.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8976-longcheer-l9360.dts</a></td><td class='right'>496</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8976.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8976.dtsi</a></td><td class='right'>1932</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 20.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 79.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts</a></td><td class='right'>50</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead-rev-10.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8992-lg-bullhead-rev-10.dts</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead-rev-101.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8992-lg-bullhead-rev-101.dts</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi</a></td><td class='right'>302</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8992-lg-h815.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8992-lg-h815.dts</a></td><td class='right'>237</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8992-msft-lumia-octagon-talkman.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8992-msft-lumia-octagon-talkman.dts</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8992-pins.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8992-pins.dtsi</a></td><td class='right'>90</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.9%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts</a></td><td class='right'>430</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8992.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8992.dtsi</a></td><td class='right'>334</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 3.1%;'/><td class='none' style='width: 96.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dts</a></td><td class='right'>32</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts</a></td><td class='right'>84</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon-cityman.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon-cityman.dts</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi</a></td><td class='right'>904</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8994-pins.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8994-pins.dtsi</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8994-smd-rpm.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8994-smd-rpm.dtsi</a></td><td class='right'>268</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 2.8%;'/><td class='none' style='width: 97.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-ivy.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-ivy.dts</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-karin.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-karin.dts</a></td><td class='right'>46</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-satsuki.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-satsuki.dts</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-sumire.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-sumire.dts</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-suzuran.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-suzuran.dts</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi</a></td><td class='right'>493</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8994.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8994.dtsi</a></td><td class='right'>1064</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 10.3%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 89.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8996-mtp.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8996-mtp.dts</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8996-mtp.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8996-mtp.dtsi</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi</a></td><td class='right'>806</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8996-oneplus3.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8996-oneplus3.dts</a></td><td class='right'>52</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8996-oneplus3t.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8996-oneplus3t.dts</a></td><td class='right'>53</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8996-pins.dtsi</a></td><td class='right'>653</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 6.8%;'/><td class='none' style='width: 93.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-dora.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-dora.dts</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-kagura.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-kagura.dts</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-keyaki.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-keyaki.dts</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi</a></td><td class='right'>978</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 10.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 89.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8996-v3.0.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8996-v3.0.dtsi</a></td><td class='right'>63</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi</a></td><td class='right'>753</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts</a></td><td class='right'>469</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8996.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8996.dtsi</a></td><td class='right'>2546</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 21.6%;'/><td class='rem' style='width: 4.8%;'/><td class='none' style='width: 73.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-natrium.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-natrium.dts</a></td><td class='right'>413</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-scorpio.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-scorpio.dts</a></td><td class='right'>497</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8996pro.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8996pro.dtsi</a></td><td class='right'>342</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8998-asus-novago-tp370ql.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8998-asus-novago-tp370ql.dts</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi</a></td><td class='right'>198</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts</a> (renamed from arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi)</td><td class='right'>421</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.8%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 95.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8998-hp-envy-x2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8998-hp-envy-x2.dts</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8998-lenovo-miix-630.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8998-lenovo-miix-630.dts</a></td><td class='right'>89</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8998-mtp.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8998-mtp.dts</a></td><td class='right'>441</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts</a></td><td class='right'>41</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi</a></td><td class='right'>575</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8998-oneplus-dumpling.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8998-oneplus-dumpling.dts</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8998-pins.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8998-pins.dtsi</a></td><td class='right'>108</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 1.1%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-lilac.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-lilac.dts</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts</a></td><td class='right'>230</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-poplar.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-poplar.dts</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi</a></td><td class='right'>968</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 10.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 89.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8998-xiaomi-sagit.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8998-xiaomi-sagit.dts</a></td><td class='right'>707</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/msm8998.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8998.dtsi</a></td><td class='right'>1966</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 16.9%;'/><td class='rem' style='width: 3.5%;'/><td class='none' style='width: 79.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pm4125.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pm4125.dtsi</a></td><td class='right'>93</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pm6125.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pm6125.dtsi</a></td><td class='right'>159</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pm6150.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pm6150.dtsi</a></td><td class='right'>112</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pm6150l.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pm6150l.dtsi</a></td><td class='right'>114</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pm6350.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pm6350.dtsi</a></td><td class='right'>93</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pm660.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pm660.dtsi</a></td><td class='right'>229</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pm660l.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pm660l.dtsi</a></td><td class='right'>95</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pm7250b.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pm7250b.dtsi</a></td><td class='right'>213</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pm7325.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pm7325.dtsi</a></td><td class='right'>55</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pm7550ba.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pm7550ba.dtsi</a></td><td class='right'>69</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pm8004.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pm8004.dtsi</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pm8005.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pm8005.dtsi</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pm8009.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pm8009.dtsi</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pm8010.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pm8010.dtsi</a></td><td class='right'>82</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pm8150.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pm8150.dtsi</a></td><td class='right'>94</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pm8150b.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pm8150b.dtsi</a></td><td class='right'>136</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pm8150l.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pm8150l.dtsi</a></td><td class='right'>105</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pm8350.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pm8350.dtsi</a></td><td class='right'>57</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pm8350b.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pm8350b.dtsi</a></td><td class='right'>57</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pm8350c.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pm8350c.dtsi</a></td><td class='right'>69</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pm8450.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pm8450.dtsi</a></td><td class='right'>58</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pm8550.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pm8550.dtsi</a></td><td class='right'>71</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pm8550b.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pm8550b.dtsi</a></td><td class='right'>64</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pm8550ve.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pm8550ve.dtsi</a></td><td class='right'>58</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pm8550vs.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pm8550vs.dtsi</a></td><td class='right'>190</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pm8916.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pm8916.dtsi</a></td><td class='right'>184</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 98.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pm8937.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pm8937.dtsi</a></td><td class='right'>158</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pm8950.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pm8950.dtsi</a></td><td class='right'>186</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pm8953.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pm8953.dtsi</a></td><td class='right'>128</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pm8994.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pm8994.dtsi</a></td><td class='right'>130</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pm8998.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pm8998.dtsi</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pmd8028.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pmd8028.dtsi</a></td><td class='right'>62</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pmi632.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pmi632.dtsi</a></td><td class='right'>209</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pmi8950.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pmi8950.dtsi</a></td><td class='right'>130</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pmi8994.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pmi8994.dtsi</a></td><td class='right'>40</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pmi8996.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pmi8996.dtsi</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pmi8998.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pmi8998.dtsi</a></td><td class='right'>73</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pmih0108.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pmih0108.dtsi</a></td><td class='right'>68</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pmk8350.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pmk8350.dtsi</a></td><td class='right'>174</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pmk8550.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pmk8550.dtsi</a></td><td class='right'>77</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi</a></td><td class='right'>134</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi</a></td><td class='right'>107</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pmp8074.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pmp8074.dtsi</a></td><td class='right'>134</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pmr735a.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pmr735a.dtsi</a></td><td class='right'>57</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pmr735b.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pmr735b.dtsi</a></td><td class='right'>57</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pmr735d_a.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pmr735d_a.dtsi</a></td><td class='right'>58</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pmr735d_b.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pmr735d_b.dtsi</a></td><td class='right'>58</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pms405.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pms405.dtsi</a></td><td class='right'>51</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/pmx75.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/pmx75.dtsi</a></td><td class='right'>63</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/purwa.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/purwa.dtsi</a></td><td class='right'>754</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts</a></td><td class='right'>1478</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 15.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 84.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/qcm6490-idp.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/qcm6490-idp.dts</a></td><td class='right'>991</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 10.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 89.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts</a></td><td class='right'>864</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts</a></td><td class='right'>999</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 10.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 89.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/qcs404-evb-1000.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/qcs404-evb-1000.dts</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/qcs404-evb.dtsi</a></td><td class='right'>137</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/qcs404.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/qcs404.dtsi</a></td><td class='right'>850</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.0%;'/><td class='rem' style='width: 2.8%;'/><td class='none' style='width: 91.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/qcs615-ride.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/qcs615-ride.dts</a></td><td class='right'>670</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/qcs6490-audioreach.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/qcs6490-audioreach.dtsi</a></td><td class='right'>119</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts</a></td><td class='right'>1095</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 11.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 88.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dtso</a></td><td class='right'>89</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts</a></td><td class='right'>1311</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 13.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 86.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/qcs8300-ride.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/qcs8300-ride.dts</a></td><td class='right'>434</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts</a></td><td class='right'>315</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi</a></td><td class='right'>405</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/qcs8550.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/qcs8550.dtsi</a></td><td class='right'>162</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/qcs9100-ride-r3.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/qcs9100-ride-r3.dts</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/qcs9100-ride.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/qcs9100-ride.dts</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/qdu1000-idp.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/qdu1000-idp.dts</a></td><td class='right'>516</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/qdu1000.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/qdu1000.dtsi</a></td><td class='right'>1647</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 17.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 82.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/qrb2210-rb1.dts</a></td><td class='right'>773</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/qrb4210-rb2.dts</a></td><td class='right'>759</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/qrb5165-rb5-vision-mezzanine.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/qrb5165-rb5-vision-mezzanine.dtso</a></td><td class='right'>62</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/qrb5165-rb5.dts</a></td><td class='right'>1580</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 16.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 83.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/qru1000-idp.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/qru1000-idp.dts</a></td><td class='right'>483</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/qru1000.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/qru1000.dtsi</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sa8155p-adp.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sa8155p-adp.dts</a></td><td class='right'>601</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sa8155p.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sa8155p.dtsi</a></td><td class='right'>48</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sa8295p-adp.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sa8295p-adp.dts</a></td><td class='right'>838</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sa8540p-pmics.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sa8540p-pmics.dtsi</a></td><td class='right'>95</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sa8540p-ride.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sa8540p-ride.dts</a></td><td class='right'>654</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sa8540p.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sa8540p.dtsi</a></td><td class='right'>242</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sa8775p-ride.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sa8775p-ride.dts</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts</a></td><td class='right'>558</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sar2130p.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sar2130p.dtsi</a></td><td class='right'>3587</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 37.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 62.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts</a></td><td class='right'>1050</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 10.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 89.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-el2.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-el2.dtso</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-firmware-tfa.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-firmware-tfa.dtsi</a></td><td class='right'>107</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-idp.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-idp.dts</a></td><td class='right'>508</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.2%;'/><td class='rem' style='width: 1.1%;'/><td class='none' style='width: 94.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-lite.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-lite.dtsi</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-clamshell.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-clamshell.dtsi</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1-lte.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1-lte.dts</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1.dts</a></td><td class='right'>171</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r3-lte.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r3-lte.dts</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r3.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r3.dts</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi</a></td><td class='right'>325</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-detachable.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-detachable.dtsi</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r2.dts</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r3.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r3.dts</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r4.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r4.dts</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi</a></td><td class='right'>345</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dts</a></td><td class='right'>217</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r10.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r10.dts</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r4.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r4.dts</a></td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r5.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r5.dts</a></td><td class='right'>32</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r9.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r9.dts</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-r10.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-r10.dts</a></td><td class='right'>45</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-r4.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-r4.dts</a></td><td class='right'>48</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-r9.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-r9.dts</a></td><td class='right'>45</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-kb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-kb.dts</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r10-kb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r10-kb.dts</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r10-lte.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r10-lte.dts</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r10.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r10.dts</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-kb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-kb.dts</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dts</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-kb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-kb.dts</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-lte.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-lte.dts</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9.dts</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi</a></td><td class='right'>213</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-parade-ps8640.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-parade-ps8640.dtsi</a></td><td class='right'>119</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-lte-parade.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-lte-parade.dts</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-lte-ti.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-lte-ti.dts</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-parade.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-parade.dts</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-ti.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-ti.dts</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi</a></td><td class='right'>217</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360-lte.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360-lte.dts</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360-wifi.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360-wifi.dts</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360.dtsi</a></td><td class='right'>63</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r1-lte.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r1-lte.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r1.dts</a></td><td class='right'>43</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2-lte.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2-lte.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2.dts</a></td><td class='right'>32</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r3-lte.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r3-lte.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r3.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r3.dts</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi</a></td><td class='right'>319</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick-r0-lte.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick-r0-lte.dts</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick-r0.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick-r0.dts</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi</a></td><td class='right'>291</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1-lte.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-r1-lte.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts</a></td><td class='right'>195</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-rt5682i-sku.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-rt5682i-sku.dtsi</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-rt5682s-sku.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-rt5682s-sku.dtsi</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi</a></td><td class='right'>105</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-boe-rt5682s.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-boe-rt5682s.dts</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-boe.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-boe.dts</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-inx-rt5682s.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-inx-rt5682s.dts</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-inx.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-inx.dts</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi</a></td><td class='right'>371</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi</a></td><td class='right'>1543</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 16.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 84.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7180.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7180.dtsi</a></td><td class='right'>3352</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 28.2%;'/><td class='rem' style='width: 6.6%;'/><td class='none' style='width: 65.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi</a></td><td class='right'>179</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts</a></td><td class='right'>149</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682-3mic.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682-3mic.dtsi</a></td><td class='right'>190</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682.dtsi</a></td><td class='right'>141</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-wcd9385.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-wcd9385.dtsi</a></td><td class='right'>218</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd-pro.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7280-herobrine-crd-pro.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts</a></td><td class='right'>377</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker-lte.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker-lte.dts</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker.dts</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker.dtsi</a></td><td class='right'>326</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts</a></td><td class='right'>359</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7280-herobrine-lte-sku.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7280-herobrine-lte-sku.dtsi</a></td><td class='right'>61</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7280-herobrine-nvme-sku.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7280-herobrine-nvme-sku.dtsi</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7280-herobrine-pro-sku.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7280-herobrine-pro-sku.dtsi</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r0.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r0.dts</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r1-lte.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r1-lte.dts</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r1.dts</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r1.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r1.dtsi</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi</a></td><td class='right'>316</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7280-herobrine-wifi-sku.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7280-herobrine-wifi-sku.dtsi</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7280-herobrine-zombie-lte.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7280-herobrine-zombie-lte.dts</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7280-herobrine-zombie-nvme-lte.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7280-herobrine-zombie-nvme-lte.dts</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7280-herobrine-zombie-nvme.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7280-herobrine-zombie-nvme.dts</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7280-herobrine-zombie.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7280-herobrine-zombie.dts</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7280-herobrine-zombie.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7280-herobrine-zombie.dtsi</a></td><td class='right'>302</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi</a></td><td class='right'>943</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi</a></td><td class='right'>106</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7280-idp.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7280-idp.dts</a></td><td class='right'>95</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7280-idp.dtsi</a></td><td class='right'>853</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7280-idp2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7280-idp2.dts</a></td><td class='right'>40</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi</a></td><td class='right'>679</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts</a></td><td class='right'>822</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi</a></td><td class='right'>336</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc8180x-primus.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc8180x-primus.dts</a></td><td class='right'>953</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc8180x.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc8180x.dtsi</a></td><td class='right'>4404</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 45.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 54.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc8280xp-crd.dts</a></td><td class='right'>1231</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 12.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 87.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc8280xp-el2.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc8280xp-el2.dtso</a></td><td class='right'>42</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts</a></td><td class='right'>1487</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 15.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 84.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts</a></td><td class='right'>1835</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 19.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 80.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts</a></td><td class='right'>1038</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 10.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 89.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts</a></td><td class='right'>1326</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 13.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 86.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi</a></td><td class='right'>304</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sc8280xp.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sc8280xp.dtsi</a></td><td class='right'>6652</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 69.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 30.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts</a></td><td class='right'>515</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdm450-lenovo-tbx605f.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdm450-lenovo-tbx605f.dts</a></td><td class='right'>373</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdm450-motorola-ali.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdm450-motorola-ali.dts</a></td><td class='right'>253</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdm450.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdm450.dtsi</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-ganges-kirin.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdm630-sony-xperia-ganges-kirin.dts</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-discovery.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-discovery.dts</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-pioneer.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-pioneer.dts</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-voyager.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-voyager.dts</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi</a></td><td class='right'>692</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdm630.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdm630.dtsi</a></td><td class='right'>2652</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 27.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 72.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts</a></td><td class='right'>389</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdm632-motorola-ocean.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdm632-motorola-ocean.dts</a></td><td class='right'>292</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdm632.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdm632.dtsi</a></td><td class='right'>89</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdm636.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdm636.dtsi</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts</a></td><td class='right'>431</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdm660.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdm660.dtsi</a></td><td class='right'>256</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts</a></td><td class='right'>620</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdm670.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdm670.dtsi</a></td><td class='right'>2277</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 23.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 76.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdm845-cheza-r1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdm845-cheza-r1.dts</a></td><td class='right'>238</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 2.5%;'/><td class='none' style='width: 97.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdm845-cheza-r2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdm845-cheza-r2.dts</a></td><td class='right'>238</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 2.5%;'/><td class='none' style='width: 97.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdm845-cheza-r3.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdm845-cheza-r3.dts</a></td><td class='right'>174</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 1.8%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi</a></td><td class='right'>1309</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 13.6%;'/><td class='none' style='width: 86.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdm845-db845c-navigation-mezzanine.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdm845-db845c-navigation-mezzanine.dtso</a></td><td class='right'>71</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdm845-db845c.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdm845-db845c.dts</a></td><td class='right'>584</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.7%;'/><td class='rem' style='width: 1.4%;'/><td class='none' style='width: 93.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi</a></td><td class='right'>582</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts</a></td><td class='right'>66</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdm845-lg-judyp.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdm845-lg-judyp.dts</a></td><td class='right'>42</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdm845-mtp.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdm845-mtp.dts</a></td><td class='right'>391</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.0%;'/><td class='rem' style='width: 1.0%;'/><td class='none' style='width: 95.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi</a></td><td class='right'>933</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts</a></td><td class='right'>112</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts</a></td><td class='right'>76</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts</a></td><td class='right'>1069</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 11.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 88.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts</a></td><td class='right'>744</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akari.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akari.dts</a></td><td class='right'>187</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akatsuki.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akatsuki.dts</a></td><td class='right'>243</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-apollo.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-apollo.dts</a></td><td class='right'>189</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi</a></td><td class='right'>793</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdm845-wcd9340.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdm845-wcd9340.dtsi</a></td><td class='right'>86</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi</a></td><td class='right'>639</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-ebbg.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-ebbg.dts</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-tianma.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-tianma.dts</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts</a></td><td class='right'>711</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdm845.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdm845.dtsi</a></td><td class='right'>3787</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 27.4%;'/><td class='rem' style='width: 11.9%;'/><td class='none' style='width: 60.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdm850-huawei-matebook-e-2019.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdm850-huawei-matebook-e-2019.dts</a></td><td class='right'>971</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 10.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 89.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts</a></td><td class='right'>596</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.3%;'/><td class='rem' style='width: 0.9%;'/><td class='none' style='width: 93.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts</a></td><td class='right'>689</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdm850.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdm850.dtsi</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdx75-idp.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdx75-idp.dts</a></td><td class='right'>359</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sdx75.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sdx75.dtsi</a></td><td class='right'>1588</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 16.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 83.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts</a></td><td class='right'>260</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm4250.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm4250.dtsi</a></td><td class='right'>77</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm4450-qrd.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm4450-qrd.dts</a></td><td class='right'>32</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm4450.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm4450.dtsi</a></td><td class='right'>686</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts</a></td><td class='right'>576</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm6115.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm6115.dtsi</a></td><td class='right'>3464</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 36.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 64.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts</a></td><td class='right'>388</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts</a></td><td class='right'>536</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo.dts</a></td><td class='right'>295</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts</a></td><td class='right'>413</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm6125.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm6125.dtsi</a></td><td class='right'>1601</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 16.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 83.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts</a></td><td class='right'>396</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm6350.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm6350.dtsi</a></td><td class='right'>3514</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 36.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 63.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts</a></td><td class='right'>460</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm6375.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm6375.dtsi</a></td><td class='right'>2477</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 25.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 74.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm7125-xiaomi-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm7125-xiaomi-common.dtsi</a></td><td class='right'>451</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm7125-xiaomi-curtana.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm7125-xiaomi-curtana.dts</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm7125-xiaomi-joyeuse.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm7125-xiaomi-joyeuse.dts</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm7125.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm7125.dtsi</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts</a></td><td class='right'>1196</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 12.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 87.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm7225.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm7225.dtsi</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts</a></td><td class='right'>1461</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 15.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 84.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm7325.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm7325.dtsi</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8150-hdk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8150-hdk.dts</a></td><td class='right'>716</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts</a></td><td class='right'>542</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8150-mtp.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8150-mtp.dts</a></td><td class='right'>80</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano-bahamut.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano-bahamut.dts</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano-griffin.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano-griffin.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi</a></td><td class='right'>874</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8150.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8150.dtsi</a></td><td class='right'>4755</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 48.3%;'/><td class='rem' style='width: 1.1%;'/><td class='none' style='width: 50.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8250-hdk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8250-hdk.dts</a></td><td class='right'>465</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8250-mtp.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8250-mtp.dts</a></td><td class='right'>875</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8250-samsung-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8250-samsung-common.dtsi</a></td><td class='right'>205</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8250-samsung-r8q.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8250-samsung-r8q.dts</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8250-samsung-x1q.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8250-samsung-x1q.dts</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dts</a></td><td class='right'>382</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dts</a></td><td class='right'>279</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi</a></td><td class='right'>725</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-boe.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-boe.dts</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi</a></td><td class='right'>871</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-csot.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-csot.dts</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8250-xiaomi-pipa.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8250-xiaomi-pipa.dts</a></td><td class='right'>541</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8250.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8250.dtsi</a></td><td class='right'>6803</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 69.6%;'/><td class='rem' style='width: 1.0%;'/><td class='none' style='width: 29.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8350-hdk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8350-hdk.dts</a></td><td class='right'>930</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts</a></td><td class='right'>382</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8350-mtp.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8350-mtp.dts</a></td><td class='right'>384</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx214.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx214.dts</a></td><td class='right'>42</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx215.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx215.dts</a></td><td class='right'>306</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi</a></td><td class='right'>922</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8350.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8350.dtsi</a></td><td class='right'>4531</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 47.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 52.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8450-hdk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8450-hdk.dts</a></td><td class='right'>1308</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 13.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 86.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8450-qrd.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8450-qrd.dts</a></td><td class='right'>536</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8450-samsung-r0q.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8450-samsung-r0q.dts</a></td><td class='right'>145</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx223.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx223.dts</a></td><td class='right'>288</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx224.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx224.dts</a></td><td class='right'>268</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi</a></td><td class='right'>799</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8450.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8450.dtsi</a></td><td class='right'>6336</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 65.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 34.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8550-hdk-rear-camera-card.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8550-hdk-rear-camera-card.dtso</a></td><td class='right'>91</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8550-hdk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8550-hdk.dts</a></td><td class='right'>1373</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 14.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 85.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8550-mtp.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8550-mtp.dts</a></td><td class='right'>977</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 10.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 89.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8550-qrd.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8550-qrd.dts</a></td><td class='right'>1281</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 13.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 86.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts</a></td><td class='right'>593</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts</a></td><td class='right'>765</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8550.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8550.dtsi</a></td><td class='right'>6768</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 70.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 29.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8650-hdk-display-card.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8650-hdk-display-card.dtso</a></td><td class='right'>132</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8650-hdk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8650-hdk.dts</a></td><td class='right'>1337</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 13.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 86.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8650-mtp.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8650-mtp.dts</a></td><td class='right'>892</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8650-qrd.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8650-qrd.dts</a></td><td class='right'>1320</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 13.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 86.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8650.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8650.dtsi</a></td><td class='right'>8294</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 86.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 13.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8750-mtp.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8750-mtp.dts</a></td><td class='right'>1275</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 13.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 86.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8750-pmics.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8750-pmics.dtsi</a></td><td class='right'>188</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8750-qrd.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8750-qrd.dts</a></td><td class='right'>1129</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 11.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 88.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/sm8750.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/sm8750.dtsi</a></td><td class='right'>4242</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 44.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 55.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/talos.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/talos.dtsi</a></td><td class='right'>4792</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 49.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 50.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi</a></td><td class='right'>1486</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 15.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 84.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/x1-crd.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/x1-crd.dtsi</a></td><td class='right'>1818</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 18.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 81.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi</a></td><td class='right'>1667</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 17.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 82.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/x1-el2.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/x1-el2.dtso</a></td><td class='right'>57</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi</a></td><td class='right'>1544</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 16.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 84.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/x1e001de-devkit.dts</a></td><td class='right'>1500</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 15.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 84.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s-oled.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s-oled.dts</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dts</a></td><td class='right'>60</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi</a></td><td class='right'>1602</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 16.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 83.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts</a></td><td class='right'>1003</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 10.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 89.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/x1e80100-asus-zenbook-a14.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/x1e80100-asus-zenbook-a14.dts</a></td><td class='right'>139</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/x1e80100-crd.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/x1e80100-crd.dts</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/x1e80100-dell-inspiron-14-plus-7441.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/x1e80100-dell-inspiron-14-plus-7441.dts</a></td><td class='right'>57</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/x1e80100-dell-latitude-7455.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/x1e80100-dell-latitude-7455.dts</a></td><td class='right'>58</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts</a></td><td class='right'>1373</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 14.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 85.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/x1e80100-hp-elitebook-ultra-g1q.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/x1e80100-hp-elitebook-ultra-g1q.dts</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts</a></td><td class='right'>1649</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 17.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 82.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi</a></td><td class='right'>1577</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 16.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 83.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus13.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus13.dts</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus15.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus15.dts</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/x1e80100-qcp.dts</a></td><td class='right'>1536</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 16.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 84.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/x1p42100-asus-zenbook-a14-lcd.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/x1p42100-asus-zenbook-a14-lcd.dts</a></td><td class='right'>62</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/x1p42100-asus-zenbook-a14.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/x1p42100-asus-zenbook-a14.dts</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/x1p42100-asus-zenbook-a14.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/x1p42100-asus-zenbook-a14.dtsi</a></td><td class='right'>138</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/x1p42100-crd.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/x1p42100-crd.dts</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/x1p42100-hp-omnibook-x14.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/x1p42100-hp-omnibook-x14.dts</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts</a></td><td class='right'>1625</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 16.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 83.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/realtek/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/realtek/Makefile</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/realtek/rtd1293-ds418j.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/realtek/rtd1293-ds418j.dts</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/realtek/rtd1293.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/realtek/rtd1293.dtsi</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/realtek/rtd1295-mele-v9.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/realtek/rtd1295-mele-v9.dts</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/realtek/rtd1295-probox2-ava.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/realtek/rtd1295-probox2-ava.dts</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/realtek/rtd1295-xnano-x5.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/realtek/rtd1295-xnano-x5.dts</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/realtek/rtd1295-zidoo-x9s.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/realtek/rtd1295-zidoo-x9s.dts</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/realtek/rtd1295.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/realtek/rtd1295.dtsi</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/realtek/rtd1296-ds418.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/realtek/rtd1296-ds418.dts</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/realtek/rtd1296.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/realtek/rtd1296.dtsi</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/realtek/rtd129x.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/realtek/rtd129x.dtsi</a></td><td class='right'>223</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/realtek/rtd1395-bpi-m4.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/realtek/rtd1395-bpi-m4.dts</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/realtek/rtd1395-lionskin.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/realtek/rtd1395-lionskin.dts</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/realtek/rtd1395.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/realtek/rtd1395.dtsi</a></td><td class='right'>67</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/realtek/rtd139x.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/realtek/rtd139x.dtsi</a></td><td class='right'>193</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/realtek/rtd1619-mjolnir.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/realtek/rtd1619-mjolnir.dts</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/realtek/rtd1619.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/realtek/rtd1619.dtsi</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/realtek/rtd16xx.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/realtek/rtd16xx.dtsi</a></td><td class='right'>233</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/Makefile</a></td><td class='right'>213</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 97.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/aistarvision-mipi-adapter-2.1.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/aistarvision-mipi-adapter-2.1.dtsi</a></td><td class='right'>94</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi</a></td><td class='right'>816</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi</a></td><td class='right'>334</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/cat875.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/cat875.dtsi</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/condor-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/condor-common.dtsi</a></td><td class='right'>556</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/draak-ebisu-panel-aa104xd12.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/draak-ebisu-panel-aa104xd12.dtso</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/draak.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/draak.dtsi</a></td><td class='right'>754</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/ebisu.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/ebisu.dtsi</a></td><td class='right'>892</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/gmsl-cameras.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/gmsl-cameras.dtsi</a></td><td class='right'>332</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/gray-hawk-single.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/gray-hawk-single.dtsi</a></td><td class='right'>866</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/hihope-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/hihope-common.dtsi</a></td><td class='right'>96</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/hihope-rev2.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/hihope-rev2.dtsi</a></td><td class='right'>83</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/hihope-rev4.dtsi</a></td><td class='right'>125</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi</a></td><td class='right'>107</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/hihope-rzg2-ex-lvds.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/hihope-rzg2-ex-lvds.dtsi</a></td><td class='right'>52</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi</a></td><td class='right'>48</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/panel-aa104xd12.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/panel-aa104xd12.dtsi</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a774a1-beacon-rzg2m-kit.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a774a1-beacon-rzg2m-kit.dts</a></td><td class='right'>60</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex-idk-1110wr.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex-idk-1110wr.dts</a></td><td class='right'>43</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex-mipi-2.1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex-mipi-2.1.dts</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex.dts</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-rev2-ex-idk-1110wr.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-rev2-ex-idk-1110wr.dts</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-rev2-ex.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-rev2-ex.dts</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-rev2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-rev2.dts</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m.dts</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a774a1.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a774a1.dtsi</a></td><td class='right'>230</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 97.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a774b1-beacon-rzg2n-kit.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a774b1-beacon-rzg2n-kit.dts</a></td><td class='right'>56</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex-idk-1110wr.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex-idk-1110wr.dts</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex-mipi-2.1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex-mipi-2.1.dts</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex.dts</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-rev2-ex-idk-1110wr.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-rev2-ex-idk-1110wr.dts</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-rev2-ex.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-rev2-ex.dts</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-rev2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-rev2.dts</a></td><td class='right'>41</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n.dts</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a774b1.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a774b1.dtsi</a></td><td class='right'>218</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts</a></td><td class='right'>87</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a774c0-ek874-idk-2121wr.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a774c0-ek874-idk-2121wr.dts</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a774c0-ek874-mipi-2.1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a774c0-ek874-mipi-2.1.dts</a></td><td class='right'>73</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a774c0.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a774c0.dtsi</a></td><td class='right'>170</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a774e1-beacon-rzg2h-kit.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a774e1-beacon-rzg2h-kit.dts</a></td><td class='right'>61</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex-idk-1110wr.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex-idk-1110wr.dts</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex-mipi-2.1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex-mipi-2.1.dts</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex.dts</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h.dts</a></td><td class='right'>41</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a774e1.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a774e1.dtsi</a></td><td class='right'>3019</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 31.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 68.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a77950-salvator-x.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a77950-salvator-x.dts</a></td><td class='right'>157</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 1.6%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a77950-ulcb-kf.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a77950-ulcb-kf.dts</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a77950.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a77950.dtsi</a></td><td class='right'>319</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 3.3%;'/><td class='none' style='width: 96.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a77951-salvator-x.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a77951-salvator-x.dts</a></td><td class='right'>108</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 1.1%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a77951-salvator-xs.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a77951-salvator-xs.dts</a></td><td class='right'>157</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 1.6%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a77951-ulcb-kf.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a77951-ulcb-kf.dts</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a77951-ulcb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a77951-ulcb.dts</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a77951.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a77951.dtsi</a></td><td class='right'>318</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.5%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 96.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a77960-salvator-x.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a77960-salvator-x.dts</a></td><td class='right'>46</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a77960-salvator-xs.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a77960-salvator-xs.dts</a></td><td class='right'>46</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a77960-ulcb-kf.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a77960-ulcb-kf.dts</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a77960-ulcb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a77960-ulcb.dts</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a77960.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a77960.dtsi</a></td><td class='right'>285</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.2%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 97.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dts</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a77961-ulcb-kf.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a77961-ulcb-kf.dts</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a77961-ulcb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a77961-ulcb.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a77961.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a77961.dtsi</a></td><td class='right'>1908</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 19.1%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 80.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts</a></td><td class='right'>45</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts</a></td><td class='right'>59</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a77965-ulcb-kf.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a77965-ulcb-kf.dts</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a77965-ulcb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a77965-ulcb.dts</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a77965.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a77965.dtsi</a></td><td class='right'>406</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.6%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 95.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a77970-eagle-function-expansion.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a77970-eagle-function-expansion.dtso</a></td><td class='right'>230</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a77970-eagle.dts</a></td><td class='right'>232</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 97.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts</a></td><td class='right'>103</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a77970.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a77970.dtsi</a></td><td class='right'>95</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a77980-condor.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a77980-condor.dts</a></td><td class='right'>280</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 2.9%;'/><td class='none' style='width: 97.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts</a></td><td class='right'>88</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a77980.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a77980.dtsi</a></td><td class='right'>141</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a77980a-condor-i.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a77980a-condor-i.dts</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a77980a.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a77980a.dtsi</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts</a></td><td class='right'>742</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 7.7%;'/><td class='none' style='width: 92.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a77990.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a77990.dtsi</a></td><td class='right'>368</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.1%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 96.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a77995-draak.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a77995-draak.dts</a></td><td class='right'>516</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 5.3%;'/><td class='none' style='width: 94.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a77995.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a77995.dtsi</a></td><td class='right'>395</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.8%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 95.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi</a></td><td class='right'>359</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779a0-falcon-csi-dsi.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779a0-falcon-csi-dsi.dtsi</a></td><td class='right'>270</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779a0-falcon-ethernet.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779a0-falcon-ethernet.dtsi</a></td><td class='right'>257</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts</a></td><td class='right'>100</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779a0.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779a0.dtsi</a></td><td class='right'>3124</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 32.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 67.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi</a></td><td class='right'>241</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi</a></td><td class='right'>110</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779f0-spider.dts</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779f0.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779f0.dtsi</a></td><td class='right'>1368</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 14.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 85.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts</a></td><td class='right'>239</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779f4.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779f4.dtsi</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dts</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779g0.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779g0.dtsi</a></td><td class='right'>2622</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 27.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 72.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779g2-white-hawk-single.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779g2-white-hawk-single.dts</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779g2.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779g2.dtsi</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j1-imx219.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j1-imx219.dtso</a></td><td class='right'>116</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j1-imx462.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j1-imx462.dtso</a></td><td class='right'>117</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j2-imx219.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j2-imx219.dtso</a></td><td class='right'>116</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j2-imx462.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j2-imx462.dtso</a></td><td class='right'>117</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-fan-argon40.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-fan-argon40.dtso</a></td><td class='right'>51</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-fan-pwm.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-fan-pwm.dtso</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-rpi-display-2-5in.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-rpi-display-2-5in.dtso</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-rpi-display-2-7in.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-rpi-display-2-7in.dtso</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-rpi-display-2.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-rpi-display-2.dtsi</a></td><td class='right'>90</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts</a></td><td class='right'>944</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779g3-white-hawk-single.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779g3-white-hawk-single.dts</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779g3.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779g3.dtsi</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779h0.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779h0.dtsi</a></td><td class='right'>2233</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 23.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 76.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779h2-gray-hawk-single.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779h2-gray-hawk-single.dts</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779h2.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779h2.dtsi</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779m0.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779m0.dtsi</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779m1-salvator-xs.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779m1-salvator-xs.dts</a></td><td class='right'>53</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779m1-ulcb-kf.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779m1-ulcb-kf.dts</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779m1-ulcb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779m1-ulcb.dts</a> (renamed from arch/arm64/boot/dts/renesas/r8a77950-ulcb.dts)</td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779m1.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779m1.dtsi</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779m2.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779m2.dtsi</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779m3-salvator-xs.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779m3-salvator-xs.dts</a></td><td class='right'>46</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779m3-ulcb-kf.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779m3-ulcb-kf.dts</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779m3-ulcb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779m3-ulcb.dts</a></td><td class='right'>45</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779m3.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779m3.dtsi</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779m4.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779m4.dtsi</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779m5-salvator-xs.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779m5-salvator-xs.dts</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779m5.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779m5.dtsi</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779m6.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779m6.dtsi</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779m7.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779m7.dtsi</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779m8.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779m8.dtsi</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a779mb.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a779mb.dtsi</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts</a></td><td class='right'>85</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r8a78000.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r8a78000.dtsi</a></td><td class='right'>787</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r9a07g043-smarc-pmod.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r9a07g043-smarc-pmod.dtso</a></td><td class='right'>45</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r9a07g043.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r9a07g043.dtsi</a></td><td class='right'>916</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r9a07g043u.dtsi</a></td><td class='right'>275</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc-cru-csi-ov5645.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r9a07g043u11-smarc-cru-csi-ov5645.dtso</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc-du-adv7513.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r9a07g043u11-smarc-du-adv7513.dtso</a></td><td class='right'>62</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r9a07g044.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r9a07g044.dtsi</a></td><td class='right'>1461</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 15.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 84.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc-cru-csi-ov5645.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r9a07g044c2-smarc-cru-csi-ov5645.dtso</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts</a></td><td class='right'>60</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r9a07g044c2.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r9a07g044c2.dtsi</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r9a07g044l2-remi-pi.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r9a07g044l2-remi-pi.dts</a></td><td class='right'>339</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc-cru-csi-ov5645.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r9a07g044l2-smarc-cru-csi-ov5645.dtso</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts</a></td><td class='right'>46</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r9a07g044l2.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r9a07g044l2.dtsi</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r9a07g054.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r9a07g054.dtsi</a></td><td class='right'>1469</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 15.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 84.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>l---------</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc-cru-csi-ov5645.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r9a07g054l2-smarc-cru-csi-ov5645.dtso</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts</a></td><td class='right'>45</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r9a07g054l2.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r9a07g054l2.dtsi</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r9a08g045.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r9a08g045.dtsi</a></td><td class='right'>927</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r9a08g045s33-smarc-pmod1-type-3a.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r9a08g045s33-smarc-pmod1-type-3a.dtso</a></td><td class='right'>48</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r9a08g045s33-smarc.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r9a08g045s33-smarc.dts</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r9a08g045s33.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r9a08g045s33.dtsi</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts</a></td><td class='right'>310</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r9a09g011.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r9a09g011.dtsi</a></td><td class='right'>377</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r9a09g047.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r9a09g047.dtsi</a></td><td class='right'>1233</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 12.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 87.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc-cru-csi-ov5645.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r9a09g047e57-smarc-cru-csi-ov5645.dtso</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts</a></td><td class='right'>181</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r9a09g047e57.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r9a09g047e57.dtsi</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r9a09g056.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r9a09g056.dtsi</a></td><td class='right'>976</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 10.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 89.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts</a></td><td class='right'>440</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r9a09g057.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r9a09g057.dtsi</a></td><td class='right'>1414</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 14.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 85.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts</a></td><td class='right'>498</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dts</a></td><td class='right'>136</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r9a09g077.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r9a09g077.dtsi</a></td><td class='right'>952</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts</a></td><td class='right'>282</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r9a09g087.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r9a09g087.dtsi</a></td><td class='right'>955</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts</a></td><td class='right'>371</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/r9a09g087m44.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/r9a09g087m44.dtsi</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi</a></td><td class='right'>108</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi</a></td><td class='right'>175</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/rz-smarc-cru-csi-ov5645.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/rz-smarc-cru-csi-ov5645.dtsi</a></td><td class='right'>79</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/rz-smarc-du-adv7513.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/rz-smarc-du-adv7513.dtsi</a></td><td class='right'>76</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi</a></td><td class='right'>168</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi</a></td><td class='right'>399</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi</a></td><td class='right'>212</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi</a></td><td class='right'>143</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi</a></td><td class='right'>318</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi</a></td><td class='right'>227</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi</a></td><td class='right'>132</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi</a></td><td class='right'>330</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi</a></td><td class='right'>153</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi</a></td><td class='right'>404</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi</a></td><td class='right'>380</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h</a></td><td class='right'>40</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi</a></td><td class='right'>301</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi</a></td><td class='right'>395</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/rzv2-evk-cn15-emmc.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/rzv2-evk-cn15-emmc.dtso</a></td><td class='right'>50</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/rzv2-evk-cn15-sd.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/rzv2-evk-cn15-sd.dtso</a></td><td class='right'>69</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/salvator-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/salvator-common.dtsi</a></td><td class='right'>276</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.4%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 97.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/salvator-panel-aa104xd12.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/salvator-panel-aa104xd12.dtso</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/salvator-x.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/salvator-x.dtsi</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/salvator-xs.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/salvator-xs.dtsi</a></td><td class='right'>58</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/ulcb-audio-graph-card-mix+split.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/ulcb-audio-graph-card-mix+split.dtsi</a></td><td class='right'>95</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/ulcb-audio-graph-card.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/ulcb-audio-graph-card.dtsi</a></td><td class='right'>90</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/ulcb-audio-graph-card2-mix+split.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/ulcb-audio-graph-card2-mix+split.dtsi</a></td><td class='right'>112</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/ulcb-audio-graph-card2.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/ulcb-audio-graph-card2.dtsi</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card-mix+split.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card-mix+split.dtsi</a></td><td class='right'>223</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card.dtsi</a></td><td class='right'>93</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card2-mix+split.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card2-mix+split.dtsi</a></td><td class='right'>230</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card2.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card2.dtsi</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/ulcb-kf-simple-audio-card-mix+split.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/ulcb-kf-simple-audio-card-mix+split.dtsi</a></td><td class='right'>200</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/ulcb-kf-simple-audio-card.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/ulcb-kf-simple-audio-card.dtsi</a></td><td class='right'>90</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/ulcb-kf.dtsi</a></td><td class='right'>296</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.1%;'/><td class='rem' style='width: 1.0%;'/><td class='none' style='width: 96.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/ulcb-simple-audio-card-mix+split.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/ulcb-simple-audio-card-mix+split.dtsi</a></td><td class='right'>96</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/ulcb-simple-audio-card.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/ulcb-simple-audio-card.dtsi</a></td><td class='right'>93</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/ulcb.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/ulcb.dtsi</a></td><td class='right'>172</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/white-hawk-ard-audio-da7212.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/white-hawk-ard-audio-da7212.dtso</a></td><td class='right'>183</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/white-hawk-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/white-hawk-common.dtsi</a></td><td class='right'>65</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi</a></td><td class='right'>410</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/white-hawk-csi-dsi.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/white-hawk-csi-dsi.dtsi</a></td><td class='right'>193</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/white-hawk-ethernet.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/white-hawk-ethernet.dtsi</a></td><td class='right'>117</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/renesas/white-hawk-single.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/renesas/white-hawk-single.dtsi</a></td><td class='right'>77</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/Makefile</a></td><td class='right'>249</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3146w-a2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3146w-a2.dts</a></td><td class='right'>41</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3146w.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3146w.dts</a></td><td class='right'>41</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3148w.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3148w.dts</a></td><td class='right'>41</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/px30-cobra-ltk500hd1829.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/px30-cobra-ltk500hd1829.dts</a></td><td class='right'>75</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/px30-cobra.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/px30-cobra.dtsi</a></td><td class='right'>566</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi</a></td><td class='right'>129</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/px30-engicam-edimm2.2.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/px30-engicam-edimm2.2.dtsi</a></td><td class='right'>66</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2-of10.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2-of10.dts</a></td><td class='right'>77</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2.dts</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts</a></td><td class='right'>43</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi</a></td><td class='right'>241</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/px30-evb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/px30-evb.dts</a></td><td class='right'>90</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/px30-firefly-jd4-core-mb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/px30-firefly-jd4-core-mb.dts</a></td><td class='right'>179</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/px30-firefly-jd4-core.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/px30-firefly-jd4-core.dtsi</a></td><td class='right'>320</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/px30-pp1516-ltk050h3146w-a2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/px30-pp1516-ltk050h3146w-a2.dts</a></td><td class='right'>41</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/px30-pp1516-ltk050h3148w.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/px30-pp1516-ltk050h3148w.dts</a></td><td class='right'>41</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/px30-pp1516.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/px30-pp1516.dtsi</a></td><td class='right'>601</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou-lvds-9904379.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/px30-ringneck-haikou-lvds-9904379.dtso</a></td><td class='right'>130</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou-video-demo.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/px30-ringneck-haikou-video-demo.dtso</a></td><td class='right'>243</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts</a></td><td class='right'>249</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi</a></td><td class='right'>451</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/px30.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/px30.dtsi</a></td><td class='right'>380</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.1%;'/><td class='rem' style='width: 0.9%;'/><td class='none' style='width: 96.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3308-bpi-p2-pro.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3308-bpi-p2-pro.dts</a></td><td class='right'>362</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3308-evb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3308-evb.dts</a></td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3308-roc-cc.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3308-roc-cc.dts</a></td><td class='right'>40</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts</a></td><td class='right'>388</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3308-rock-s0.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3308-rock-s0.dts</a></td><td class='right'>316</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3308-sakurapi-rk3308b.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3308-sakurapi-rk3308b.dts</a></td><td class='right'>265</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3308.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3308.dtsi</a></td><td class='right'>310</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.8%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 96.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts</a></td><td class='right'>383</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3326-anbernic-rg351m.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3326-anbernic-rg351m.dts</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3326-anbernic-rg351m.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3326-anbernic-rg351m.dtsi</a></td><td class='right'>480</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3326-anbernic-rg351v.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3326-anbernic-rg351v.dts</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3326-gameforce-chi.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3326-gameforce-chi.dts</a></td><td class='right'>811</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3326-odroid-go.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3326-odroid-go.dtsi</a></td><td class='right'>617</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2-v11.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3326-odroid-go2-v11.dts</a></td><td class='right'>158</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts</a></td><td class='right'>68</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3326-odroid-go3.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3326-odroid-go3.dts</a></td><td class='right'>188</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3326.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3326.dtsi</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3328-a1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3328-a1.dts</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3328-evb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3328-evb.dts</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2.dtsi</a></td><td class='right'>393</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts</a></td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dtsi</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s-plus.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s-plus.dts</a></td><td class='right'>48</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dtsi</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts</a></td><td class='right'>41</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dtsi</a></td><td class='right'>356</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts</a></td><td class='right'>349</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 3.5%;'/><td class='none' style='width: 96.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts</a></td><td class='right'>105</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi</a></td><td class='right'>394</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts</a></td><td class='right'>450</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3328-rock64.dts</a></td><td class='right'>105</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3328.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3328.dtsi</a></td><td class='right'>317</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.3%;'/><td class='rem' style='width: 1.0%;'/><td class='none' style='width: 96.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3368-lba3368.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3368-lba3368.dts</a></td><td class='right'>659</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi</a></td><td class='right'>67</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts</a></td><td class='right'>39</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3368-r88.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3368-r88.dts</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3368.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3368.dtsi</a></td><td class='right'>351</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.1%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 96.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-base.dtsi</a></td><td class='right'>3015</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 31.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 68.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-eaidk-610.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-eaidk-610.dts</a></td><td class='right'>939</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-evb-ind.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-evb-ind.dts</a></td><td class='right'>494</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-evb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-evb.dts</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-ficus.dts</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-firefly.dts</a></td><td class='right'>212</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 97.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi</a></td><td class='right'>243</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.2%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 97.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-dumo.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-dumo.dts</a></td><td class='right'>41</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-inx.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-inx.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi</a></td><td class='right'>328</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.1%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 96.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi</a></td><td class='right'>112</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-hugsun-x99.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-hugsun-x99.dts</a></td><td class='right'>48</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge-captain.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-khadas-edge-captain.dts</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge-v.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-khadas-edge-v.dts</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi</a></td><td class='right'>67</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts</a></td><td class='right'>619</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts</a></td><td class='right'>39</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-nanopi-m4.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-nanopi-m4.dts</a></td><td class='right'>47</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-nanopi-m4.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-nanopi-m4.dtsi</a></td><td class='right'>60</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-nanopi-m4b.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-nanopi-m4b.dts</a></td><td class='right'>53</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-nanopi-neo4.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-nanopi-neo4.dts</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s-enterprise.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s-enterprise.dts</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dtsi</a></td><td class='right'>131</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-op1.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-op1.dtsi</a></td><td class='right'>168</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts</a></td><td class='right'>105</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts</a></td><td class='right'>227</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 1.0%;'/><td class='none' style='width: 97.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts</a></td><td class='right'>832</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou-video-demo.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-puma-haikou-video-demo.dtso</a></td><td class='right'>166</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts</a></td><td class='right'>116</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi</a></td><td class='right'>282</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.9%;'/><td class='rem' style='width: 1.0%;'/><td class='none' style='width: 97.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-mezzanine.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-roc-pc-mezzanine.dts</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts</a></td><td class='right'>216</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi</a></td><td class='right'>96</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts</a></td><td class='right'>752</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-rock-4se.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-rock-4se.dts</a></td><td class='right'>50</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi</a> (renamed from arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts)</td><td class='right'>289</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 1.2%;'/><td class='none' style='width: 97.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a-plus.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a-plus.dts</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a.dts</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts</a></td><td class='right'>61</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts</a></td><td class='right'>60</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts</a></td><td class='right'>80</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-rock960.dts</a></td><td class='right'>82</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi</a></td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-rockpro64-screen.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-rockpro64-screen.dtso</a></td><td class='right'>78</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi</a></td><td class='right'>173</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-s.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-s.dtsi</a> (renamed from arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi)</td><td class='right'>56</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399-t.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399-t.dtsi</a> (renamed from arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi)</td><td class='right'>71</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399.dtsi</a></td><td class='right'>2708</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 27.2%;'/><td class='none' style='width: 71.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399pro-rock-pi-n10.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399pro-rock-pi-n10.dts</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi</a></td><td class='right'>224</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.9%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3399pro.dtsi</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3528-armsom-sige1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3528-armsom-sige1.dts</a></td><td class='right'>464</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3528-nanopi-zero2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3528-nanopi-zero2.dts</a></td><td class='right'>340</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3528-pinctrl.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3528-pinctrl.dtsi</a></td><td class='right'>1397</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 14.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 85.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts</a></td><td class='right'>322</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi</a></td><td class='right'>293</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3528-rock-2a.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3528-rock-2a.dts</a></td><td class='right'>81</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3528-rock-2f.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3528-rock-2f.dts</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3528.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3528.dtsi</a></td><td class='right'>1232</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 12.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 87.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3562-evb2-v10.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3562-evb2-v10.dts</a></td><td class='right'>456</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3562-pinctrl.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3562-pinctrl.dtsi</a></td><td class='right'>2352</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 24.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 75.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3562.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3562.dtsi</a></td><td class='right'>1186</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 12.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 87.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg-arc-d.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg-arc-d.dts</a></td><td class='right'>60</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg-arc-s.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg-arc-s.dts</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg-arc.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg-arc.dtsi</a></td><td class='right'>237</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353p.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353p.dts</a></td><td class='right'>146</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353ps.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353ps.dts</a></td><td class='right'>116</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353v.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353v.dts</a></td><td class='right'>126</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353vs.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353vs.dts</a></td><td class='right'>87</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353x.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353x.dtsi</a></td><td class='right'>194</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts</a></td><td class='right'>297</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi</a></td><td class='right'>719</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-base.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-base.dtsi</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2-manta.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2-manta.dts</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi</a></td><td class='right'>904</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-pi2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-pi2.dts</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts</a></td><td class='right'>534</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-lckfb-tspi.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-lckfb-tspi.dts</a></td><td class='right'>725</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-lubancat-1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-lubancat-1.dts</a></td><td class='right'>589</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts</a></td><td class='right'>554</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-odroid-m1s.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-odroid-m1s.dts</a></td><td class='right'>663</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dts</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v2.1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v2.1.dts</a></td><td class='right'>70</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b.dtsi</a></td><td class='right'>683</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-pinenote-v1.1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-pinenote-v1.1.dts</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-pinenote-v1.2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-pinenote-v1.2.dts</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi</a></td><td class='right'>720</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-pinetab2-v0.1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-pinetab2-v0.1.dts</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-pinetab2-v2.0.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-pinetab2-v2.0.dts</a></td><td class='right'>48</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-pinetab2.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-pinetab2.dtsi</a></td><td class='right'>944</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rgb10max3.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rgb10max3.dts</a></td><td class='right'>87</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rgb20sx.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rgb20sx.dts</a></td><td class='right'>89</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rgb30.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rgb30.dts</a></td><td class='right'>57</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rk2023.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rk2023.dts</a></td><td class='right'>56</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rk2023.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rk2023.dtsi</a></td><td class='right'>861</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-x55.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-powkiddy-x55.dts</a></td><td class='right'>927</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts</a></td><td class='right'>844</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts</a></td><td class='right'>745</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts</a></td><td class='right'>281</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi</a></td><td class='right'>425</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi</a></td><td class='right'>530</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3e.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3e.dts</a></td><td class='right'>52</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3w.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3w.dts</a></td><td class='right'>92</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts</a></td><td class='right'>700</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts</a></td><td class='right'>728</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-soquartz-blade.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-soquartz-blade.dts</a></td><td class='right'>198</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts</a></td><td class='right'>196</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-soquartz-model-a.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-soquartz-model-a.dts</a></td><td class='right'>236</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi</a></td><td class='right'>685</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-tinker-board-3.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-tinker-board-3.dts</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-tinker-board-3.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-tinker-board-3.dtsi</a></td><td class='right'>278</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566-tinker-board-3s.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566-tinker-board-3s.dts</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566.dtsi</a></td><td class='right'>107</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3566t.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3566t.dtsi</a></td><td class='right'>90</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3568-9tripod-x3568-v4.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3568-9tripod-x3568-v4.dts</a></td><td class='right'>880</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts</a></td><td class='right'>854</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3568-easepi-r1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3568-easepi-r1.dts</a></td><td class='right'>623</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts</a></td><td class='right'>751</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dts</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi</a></td><td class='right'>460</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts</a></td><td class='right'>110</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3568-hinlink-h66k.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3568-hinlink-h66k.dts</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3568-hinlink-h68k.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3568-hinlink-h68k.dts</a></td><td class='right'>83</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3568-hinlink-opc.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3568-hinlink-opc.dtsi</a></td><td class='right'>666</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3568-lubancat-2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3568-lubancat-2.dts</a></td><td class='right'>728</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3568-mecsbc.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3568-mecsbc.dts</a></td><td class='right'>425</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts</a></td><td class='right'>112</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts</a></td><td class='right'>163</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi</a></td><td class='right'>605</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts</a></td><td class='right'>743</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts</a></td><td class='right'>588</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi</a></td><td class='right'>3214</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 33.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 66.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts233.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3568-qnap-ts233.dts</a></td><td class='right'>131</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts</a></td><td class='right'>189</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3568-qnap-tsx33.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3568-qnap-tsx33.dtsi</a></td><td class='right'>608</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi</a></td><td class='right'>408</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts</a></td><td class='right'>245</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3568-roc-pc.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3568-roc-pc.dts</a></td><td class='right'>640</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts</a></td><td class='right'>855</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts</a></td><td class='right'>781</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3568-wolfvision-pf5-display-vz.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3568-wolfvision-pf5-display-vz.dtso</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3568-wolfvision-pf5-display.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3568-wolfvision-pf5-display.dtsi</a></td><td class='right'>121</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3568-wolfvision-pf5-io-expander.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3568-wolfvision-pf5-io-expander.dtso</a></td><td class='right'>136</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3568-wolfvision-pf5.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3568-wolfvision-pf5.dts</a></td><td class='right'>536</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3568.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3568.dtsi</a></td><td class='right'>412</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk356x-base.dtsi</a></td><td class='right'>1921</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 20.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 80.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3576-100ask-dshanpi-a1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3576-100ask-dshanpi-a1.dts</a></td><td class='right'>838</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5-v1.2-wifibt.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5-v1.2-wifibt.dtso</a></td><td class='right'>49</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts</a></td><td class='right'>1041</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 10.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 89.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts</a></td><td class='right'>943</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3576-luckfox-core3576.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3576-luckfox-core3576.dtsi</a></td><td class='right'>749</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3576-luckfox-omni3576.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3576-luckfox-omni3576.dts</a></td><td class='right'>51</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts</a></td><td class='right'>941</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3576-nanopi-r76s.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3576-nanopi-r76s.dts</a></td><td class='right'>860</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3576-pinctrl.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3576-pinctrl.dtsi</a></td><td class='right'>5775</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 60.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 40.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3576-roc-pc.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3576-roc-pc.dts</a></td><td class='right'>799</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts</a></td><td class='right'>847</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3576.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3576.dtsi</a></td><td class='right'>2693</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 28.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 72.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3582-radxa-e52c.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3582-radxa-e52c.dts</a></td><td class='right'>734</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-armsom-lm7.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-armsom-lm7.dtsi</a></td><td class='right'>459</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts</a></td><td class='right'>836</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-armsom-w3.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-armsom-w3.dts</a></td><td class='right'>509</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi</a></td><td class='right'>3622</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 37.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 62.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-base.dtsi</a></td><td class='right'>3323</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 34.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 65.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts</a></td><td class='right'>319</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-genbook.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-genbook.dts</a></td><td class='right'>445</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi</a></td><td class='right'>660</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi</a></td><td class='right'>476</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dts</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi</a></td><td class='right'>324</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-wifi.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-wifi.dtso</a></td><td class='right'>56</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a.dtsi</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b-io.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b-io.dts</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b.dtsi</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts</a></td><td class='right'>1446</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 15.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 85.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts</a></td><td class='right'>979</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 10.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 89.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-extra-pinctrl.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-extra-pinctrl.dtsi</a></td><td class='right'>517</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi</a></td><td class='right'>695</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-fet3588-c.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-fet3588-c.dtsi</a></td><td class='right'>562</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-firefly-core-3588j.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-firefly-core-3588j.dtsi</a></td><td class='right'>447</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-firefly-icore-3588q.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-firefly-icore-3588q.dtsi</a></td><td class='right'>443</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-firefly-itx-3588j.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-firefly-itx-3588j.dts</a></td><td class='right'>702</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts</a></td><td class='right'>842</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi</a></td><td class='right'>661</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-h96-max-v58.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-h96-max-v58.dts</a></td><td class='right'>830</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-jaguar-ethernet-switch.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-jaguar-ethernet-switch.dtso</a></td><td class='right'>195</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-jaguar-pre-ict-tester.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-jaguar-pre-ict-tester.dtso</a></td><td class='right'>171</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts</a></td><td class='right'>1160</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 12.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 88.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-mnt-reform2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-mnt-reform2.dts</a></td><td class='right'>336</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6-lts.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6-lts.dts</a></td><td class='right'>60</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts</a></td><td class='right'>40</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi</a></td><td class='right'>1201</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 12.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 87.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts</a></td><td class='right'>415</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi</a></td><td class='right'>190</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-compact.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-compact.dtsi</a></td><td class='right'>178</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max.dts</a></td><td class='right'>125</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts</a></td><td class='right'>415</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-ultra.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-ultra.dts</a></td><td class='right'>83</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-orangepi-5.dtsi</a></td><td class='right'>867</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts</a></td><td class='right'>1197</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 12.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 87.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-roc-rt.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-roc-rt.dts</a></td><td class='right'>1132</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 11.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 88.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts</a></td><td class='right'>1339</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 13.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 86.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi</a></td><td class='right'>1075</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 11.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 88.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-srns.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-srns.dtso</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts</a></td><td class='right'>130</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts</a></td><td class='right'>68</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dtsi</a></td><td class='right'>86</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts</a></td><td class='right'>156</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou-video-demo.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou-video-demo.dtso</a></td><td class='right'>153</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts</a></td><td class='right'>386</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi</a></td><td class='right'>741</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts</a></td><td class='right'>695</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dts</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi</a></td><td class='right'>745</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588.dtsi</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588j.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588j.dtsi</a></td><td class='right'>129</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts</a></td><td class='right'>929</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588s-evb1-v10.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588s-evb1-v10.dts</a></td><td class='right'>1228</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 12.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 87.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts</a></td><td class='right'>1461</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 15.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 84.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts</a></td><td class='right'>1086</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 11.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 88.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts</a></td><td class='right'>815</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi</a></td><td class='right'>877</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6s.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6s.dts</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dts</a></td><td class='right'>954</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts</a></td><td class='right'>32</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi</a></td><td class='right'>911</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5b.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5b.dts</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588s-roc-pc.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588s-roc-pc.dts</a></td><td class='right'>840</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts</a></td><td class='right'>867</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts</a></td><td class='right'>965</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 10.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk3588s.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk3588s.dtsi</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rk8xx.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rk8xx.h</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi</a></td><td class='right'>379</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/socionext/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/socionext/Makefile</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi</a></td><td class='right'>104</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/socionext/uniphier-ld20-akebi96.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/socionext/uniphier-ld20-akebi96.dts</a></td><td class='right'>189</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi</a></td><td class='right'>150</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/socionext/uniphier-pinctrl.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/socionext/uniphier-pinctrl.dtsi</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref-gadget0.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/socionext/uniphier-pxs3-ref-gadget0.dts</a></td><td class='right'>41</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref-gadget1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/socionext/uniphier-pxs3-ref-gadget1.dts</a></td><td class='right'>40</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts</a></td><td class='right'>40</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi</a></td><td class='right'>223</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/socionext/uniphier-ref-daughter.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/socionext/uniphier-ref-daughter.dtsi</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/socionext/uniphier-support-card.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/socionext/uniphier-support-card.dtsi</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/sophgo/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/sophgo/Makefile</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/sophgo/sg2000-milkv-duo-module-01-evb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/sophgo/sg2000-milkv-duo-module-01-evb.dts</a></td><td class='right'>76</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/sophgo/sg2000-milkv-duo-module-01.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/sophgo/sg2000-milkv-duo-module-01.dtsi</a></td><td class='right'>40</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/sophgo/sg2000.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/sophgo/sg2000.dtsi</a></td><td class='right'>86</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/sprd/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/sprd/Makefile</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/sprd/sc2731.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/sprd/sc2731.dtsi</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/sprd/sc9836-openphone.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/sprd/sc9836-openphone.dts</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/sprd/sc9836.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/sprd/sc9836.dtsi</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/sprd/sc9860.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/sprd/sc9860.dtsi</a></td><td class='right'>119</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 1.1%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/sprd/sc9863a.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/sprd/sc9863a.dtsi</a></td><td class='right'>70</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/sprd/sharkl3.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/sprd/sharkl3.dtsi</a></td><td class='right'>164</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/sprd/sharkl64.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/sprd/sharkl64.dtsi</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/sprd/sp9860g-1h10.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/sprd/sp9860g-1h10.dts</a></td><td class='right'>42</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/sprd/ums512-1h10.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/sprd/ums512-1h10.dts</a></td><td class='right'>61</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/sprd/ums512.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/sprd/ums512.dtsi</a></td><td class='right'>918</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/sprd/ums9620-2h10.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/sprd/ums9620-2h10.dts</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/sprd/ums9620.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/sprd/ums9620.dtsi</a></td><td class='right'>251</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/sprd/whale2.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/sprd/whale2.dtsi</a></td><td class='right'>105</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/st/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/st/Makefile</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/st/stm32mp211.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/st/stm32mp211.dtsi</a></td><td class='right'>130</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/st/stm32mp213.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/st/stm32mp213.dtsi</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/st/stm32mp215.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/st/stm32mp215.dtsi</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/st/stm32mp215f-dk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/st/stm32mp215f-dk.dts</a></td><td class='right'>49</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/st/stm32mp21xc.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/st/stm32mp21xc.dtsi</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/st/stm32mp21xf.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/st/stm32mp21xf.dtsi</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/st/stm32mp231.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/st/stm32mp231.dtsi</a></td><td class='right'>1191</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 12.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 87.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/st/stm32mp233.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/st/stm32mp233.dtsi</a></td><td class='right'>94</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/st/stm32mp235.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/st/stm32mp235.dtsi</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/st/stm32mp235f-dk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/st/stm32mp235f-dk.dts</a></td><td class='right'>136</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/st/stm32mp23xc.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/st/stm32mp23xc.dtsi</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/st/stm32mp23xf.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/st/stm32mp23xf.dtsi</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi</a></td><td class='right'>536</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/st/stm32mp251.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/st/stm32mp251.dtsi</a></td><td class='right'>2188</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 22.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 77.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/st/stm32mp253.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/st/stm32mp253.dtsi</a></td><td class='right'>94</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/st/stm32mp255.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/st/stm32mp255.dtsi</a></td><td class='right'>43</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/st/stm32mp257.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/st/stm32mp257.dtsi</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/st/stm32mp257f-dk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/st/stm32mp257f-dk.dts</a></td><td class='right'>136</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/st/stm32mp257f-ev1.dts</a></td><td class='right'>493</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/st/stm32mp25xc.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/st/stm32mp25xc.dtsi</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/st/stm32mp25xf.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/st/stm32mp25xf.dtsi</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/st/stm32mp25xxai-pinctrl.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/st/stm32mp25xxai-pinctrl.dtsi</a></td><td class='right'>83</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/st/stm32mp25xxak-pinctrl.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/st/stm32mp25xxak-pinctrl.dtsi</a></td><td class='right'>71</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/st/stm32mp25xxal-pinctrl.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/st/stm32mp25xxal-pinctrl.dtsi</a></td><td class='right'>71</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/synaptics/as370.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/synaptics/as370.dtsi</a></td><td class='right'>173</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 1.8%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/synaptics/berlin4ct.dtsi</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/tesla/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/tesla/Makefile</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/tesla/fsd-evb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/tesla/fsd-evb.dts</a></td><td class='right'>132</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi</a></td><td class='right'>503</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/tesla/fsd-pinctrl.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/tesla/fsd-pinctrl.h</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/tesla/fsd.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/tesla/fsd.dtsi</a></td><td class='right'>1064</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 11.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 89.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/Makefile</a></td><td class='right'>339</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62-lp-sk-nand.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62-lp-sk-nand.dtso</a></td><td class='right'>116</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts</a></td><td class='right'>342</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62-main.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62-main.dtsi</a></td><td class='right'>1268</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 13.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 86.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi</a></td><td class='right'>190</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi</a></td><td class='right'>370</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts</a></td><td class='right'>503</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62-thermal.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62-thermal.dtsi</a></td><td class='right'>70</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62-ti-ipc-firmware.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62-ti-ipc-firmware.dtsi</a></td><td class='right'>52</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi</a></td><td class='right'>223</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi</a></td><td class='right'>246</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62-verdin-ivy.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62-verdin-ivy.dtsi</a></td><td class='right'>655</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62-verdin-mallow.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62-verdin-mallow.dtsi</a></td><td class='right'>212</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62-verdin-nonwifi.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62-verdin-nonwifi.dtsi</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62-verdin-wifi.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62-verdin-wifi.dtsi</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62-verdin-yavia.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62-verdin-yavia.dtsi</a></td><td class='right'>217</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi</a></td><td class='right'>1509</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 15.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 84.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi</a></td><td class='right'>142</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62.dtsi</a></td><td class='right'>150</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am625-beagleplay-csi2-ov5640.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am625-beagleplay-csi2-ov5640.dtso</a></td><td class='right'>108</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am625-beagleplay-csi2-tevi-ov5640.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am625-beagleplay-csi2-tevi-ov5640.dtso</a></td><td class='right'>108</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts</a></td><td class='right'>949</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am625-sk-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am625-sk-common.dtsi</a></td><td class='right'>296</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am625-sk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am625-sk.dts</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-dahlia.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-dahlia.dts</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-dev.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-dev.dts</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-ivy.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-ivy.dts</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-mallow.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-mallow.dts</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-yavia.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-yavia.dts</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-dahlia.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-dahlia.dts</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-dev.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-dev.dts</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-ivy.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-ivy.dts</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-mallow.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-mallow.dts</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-yavia.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-yavia.dts</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am625.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am625.dtsi</a></td><td class='right'>159</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am6254atl-sk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am6254atl-sk.dts</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am6254atl.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am6254atl.dtsi</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62a-main.dtsi</a></td><td class='right'>1175</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 12.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 87.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi</a></td><td class='right'>203</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi</a></td><td class='right'>361</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62a-thermal.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62a-thermal.dtsi</a></td><td class='right'>101</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62a-ti-ipc-firmware.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62a-ti-ipc-firmware.dtsi</a></td><td class='right'>98</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi</a></td><td class='right'>141</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62a.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62a.dtsi</a></td><td class='right'>154</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62a7-phyboard-lyra-rdk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62a7-phyboard-lyra-rdk.dts</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62a7-sk.dts</a></td><td class='right'>924</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62a7.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62a7.dtsi</a></td><td class='right'>159</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62d2-evm.dts</a></td><td class='right'>740</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62d2.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62d2.dtsi</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62l-main.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62l-main.dtsi</a></td><td class='right'>580</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi</a></td><td class='right'>141</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62l.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62l.dtsi</a></td><td class='right'>118</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62l3-evm.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62l3-evm.dts</a></td><td class='right'>361</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62l3.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62l3.dtsi</a></td><td class='right'>67</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi</a></td><td class='right'>1120</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 11.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 88.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi</a></td><td class='right'>211</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-thermal.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62p-j722s-common-thermal.dtsi</a></td><td class='right'>101</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi</a></td><td class='right'>142</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62p-main.dtsi</a></td><td class='right'>62</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62p-ti-ipc-firmware.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62p-ti-ipc-firmware.dtsi</a></td><td class='right'>60</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62p-verdin-dahlia.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62p-verdin-dahlia.dtsi</a></td><td class='right'>228</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62p-verdin-dev.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62p-verdin-dev.dtsi</a></td><td class='right'>245</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62p-verdin-ivy.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62p-verdin-ivy.dtsi</a></td><td class='right'>629</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62p-verdin-mallow.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62p-verdin-mallow.dtsi</a></td><td class='right'>213</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62p-verdin-nonwifi.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62p-verdin-nonwifi.dtsi</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62p-verdin-wifi.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62p-verdin-wifi.dtsi</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62p-verdin-yavia.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62p-verdin-yavia.dtsi</a></td><td class='right'>219</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi</a></td><td class='right'>1418</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 14.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 85.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62p.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62p.dtsi</a></td><td class='right'>155</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62p5-sk.dts</a></td><td class='right'>835</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts</a></td><td class='right'>500</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi</a></td><td class='right'>435</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62p5-verdin-nonwifi-dahlia.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62p5-verdin-nonwifi-dahlia.dts</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62p5-verdin-nonwifi-dev.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62p5-verdin-nonwifi-dev.dts</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62p5-verdin-nonwifi-ivy.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62p5-verdin-nonwifi-ivy.dts</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62p5-verdin-nonwifi-mallow.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62p5-verdin-nonwifi-mallow.dts</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62p5-verdin-nonwifi-yavia.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62p5-verdin-nonwifi-yavia.dts</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62p5-verdin-wifi-dahlia.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62p5-verdin-wifi-dahlia.dts</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62p5-verdin-wifi-dev.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62p5-verdin-wifi-dev.dts</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62p5-verdin-wifi-ivy.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62p5-verdin-wifi-ivy.dts</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62p5-verdin-wifi-mallow.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62p5-verdin-wifi-mallow.dts</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62p5-verdin-wifi-yavia.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62p5-verdin-wifi-yavia.dts</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62p5.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62p5.dtsi</a></td><td class='right'>158</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra-gpio-fan.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra-gpio-fan.dtso</a></td><td class='right'>60</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi</a></td><td class='right'>506</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi</a></td><td class='right'>557</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-imx219.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-imx219.dtso</a></td><td class='right'>114</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-ov5640.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-ov5640.dtso</a></td><td class='right'>114</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-tevi-ov5640.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-tevi-ov5640.dtso</a></td><td class='right'>114</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am62x-sk-hdmi-audio.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am62x-sk-hdmi-audio.dtso</a></td><td class='right'>40</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am64-main.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am64-main.dtsi</a></td><td class='right'>1678</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 17.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 82.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi</a></td><td class='right'>177</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi</a></td><td class='right'>297</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am64-thermal.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am64-thermal.dtsi</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am64-ti-ipc-firmware.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am64-ti-ipc-firmware.dtsi</a></td><td class='right'>162</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am64-tqma64xxl-mbax4xxl-sdcard.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am64-tqma64xxl-mbax4xxl-sdcard.dtso</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am64-tqma64xxl-mbax4xxl-wlan.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am64-tqma64xxl-mbax4xxl-wlan.dtso</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am64.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am64.dtsi</a></td><td class='right'>102</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am642-evm-icssg1-dualemac-mii.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am642-evm-icssg1-dualemac-mii.dtso</a></td><td class='right'>101</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am642-evm-icssg1-dualemac.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am642-evm-icssg1-dualemac.dtso</a></td><td class='right'>79</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am642-evm-nand.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am642-evm-nand.dtso</a></td><td class='right'>148</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso</a></td><td class='right'>52</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am642-evm.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am642-evm.dts</a></td><td class='right'>743</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am642-hummingboard-t-pcie.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am642-hummingboard-t-pcie.dts</a></td><td class='right'>47</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am642-hummingboard-t-usb3.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am642-hummingboard-t-usb3.dts</a></td><td class='right'>47</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am642-hummingboard-t.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am642-hummingboard-t.dts</a></td><td class='right'>291</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-gpio-fan.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-gpio-fan.dtso</a></td><td class='right'>50</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-pcie-usb2.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-pcie-usb2.dtso</a></td><td class='right'>87</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-peb-c-010.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-peb-c-010.dtso</a></td><td class='right'>158</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts</a></td><td class='right'>467</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtso</a></td><td class='right'>63</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am642-sk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am642-sk.dts</a></td><td class='right'>605</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi</a></td><td class='right'>506</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts</a></td><td class='right'>1056</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 11.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 89.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi</a></td><td class='right'>176</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am642.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am642.dtsi</a></td><td class='right'>66</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am65-iot2050-arduino-connector.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am65-iot2050-arduino-connector.dtsi</a></td><td class='right'>768</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg1.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg1.dtsi</a></td><td class='right'>87</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg2.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg2.dtsi</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi</a></td><td class='right'>640</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am65-iot2050-dp.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am65-iot2050-dp.dtsi</a></td><td class='right'>98</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am65-iot2050-usb3.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am65-iot2050-usb3.dtsi</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am65-main.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am65-main.dtsi</a></td><td class='right'>1101</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 10.2%;'/><td class='rem' style='width: 1.2%;'/><td class='none' style='width: 88.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi</a></td><td class='right'>289</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.6%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 97.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am65-ti-ipc-firmware.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am65-ti-ipc-firmware.dtsi</a></td><td class='right'>64</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi</a></td><td class='right'>62</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am65.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am65.dtsi</a></td><td class='right'>43</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am652.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am652.dtsi</a></td><td class='right'>74</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi</a></td><td class='right'>43</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-pg2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-pg2.dts</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic.dts</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am654-base-board-rocktech-rk101-panel.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am654-base-board-rocktech-rk101-panel.dtso</a></td><td class='right'>83</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am654-base-board.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am654-base-board.dts</a></td><td class='right'>427</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.9%;'/><td class='rem' style='width: 1.5%;'/><td class='none' style='width: 95.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso</a></td><td class='right'>146</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am654-idk.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am654-idk.dtso</a></td><td class='right'>355</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am654-industrial-thermal.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am654-industrial-thermal.dtsi</a></td><td class='right'>48</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am654-pcie-usb2.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am654-pcie-usb2.dtso</a></td><td class='right'>60</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am654-pcie-usb3.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am654-pcie-usb3.dtso</a></td><td class='right'>62</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am654.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am654.dtsi</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi</a></td><td class='right'>53</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie.dtso</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2-bkey-usb3.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2-bkey-usb3.dtso</a></td><td class='right'>47</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts</a></td><td class='right'>95</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-pg2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-pg2.dts</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-sm.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-sm.dts</a></td><td class='right'>189</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced.dts</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts</a></td><td class='right'>402</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-ads2.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-ads2.dtso</a></td><td class='right'>146</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts</a></td><td class='right'>1091</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 11.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 88.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-gbe1.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-gbe1.dtso</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-gpios.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-gpios.dtso</a></td><td class='right'>61</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-rtc-rv8263.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-rtc-rv8263.dtso</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am68-phyboard-izar.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am68-phyboard-izar.dts</a></td><td class='right'>576</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi</a></td><td class='right'>370</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am68-sk-base-board-pcie1-ep.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am68-sk-base-board-pcie1-ep.dtso</a></td><td class='right'>53</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts</a></td><td class='right'>868</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi</a></td><td class='right'>148</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am69-aquila-clover.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am69-aquila-clover.dts</a></td><td class='right'>451</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am69-aquila-dev.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am69-aquila-dev.dts</a></td><td class='right'>576</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am69-aquila.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am69-aquila.dtsi</a></td><td class='right'>1840</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 19.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 80.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am69-sk-pcie0-ep.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am69-sk-pcie0-ep.dtso</a></td><td class='right'>53</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am69-sk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am69-sk.dts</a></td><td class='right'>1063</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 11.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 89.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-eth-phy.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-eth-phy.dtso</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-rtc.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-rtc.dtso</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-spi-nor.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-spi-nor.dtso</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-am6xx-phycore-qspi-nor.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-am6xx-phycore-qspi-nor.dtso</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts</a></td><td class='right'>491</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso</a></td><td class='right'>53</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso</a></td><td class='right'>101</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j7200-main.dtsi</a></td><td class='right'>1560</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 16.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 83.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi</a></td><td class='right'>716</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi</a></td><td class='right'>428</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi</a></td><td class='right'>50</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j7200-ti-ipc-firmware.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j7200-ti-ipc-firmware.dtsi</a></td><td class='right'>130</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j7200.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j7200.dtsi</a></td><td class='right'>164</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts</a></td><td class='right'>767</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board-infotainment.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j721e-common-proc-board-infotainment.dtso</a></td><td class='right'>173</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts</a></td><td class='right'>855</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.2%;'/><td class='rem' style='width: 1.7%;'/><td class='none' style='width: 91.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j721e-evm-gesi-exp-board.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j721e-evm-gesi-exp-board.dtso</a></td><td class='right'>196</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso</a></td><td class='right'>53</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie1-ep.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j721e-evm-pcie1-ep.dtso</a></td><td class='right'>53</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso</a></td><td class='right'>133</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j721e-main.dtsi</a></td><td class='right'>2163</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 21.4%;'/><td class='rem' style='width: 1.0%;'/><td class='none' style='width: 77.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi</a></td><td class='right'>463</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.3%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 95.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j721e-sk-csi2-dual-imx219.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j721e-sk-csi2-dual-imx219.dtso</a></td><td class='right'>196</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j721e-sk.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j721e-sk.dts</a></td><td class='right'>1181</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 12.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 87.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi</a></td><td class='right'>329</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 96.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j721e-thermal.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j721e-thermal.dtsi</a></td><td class='right'>78</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j721e-ti-ipc-firmware.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j721e-ti-ipc-firmware.dtsi</a></td><td class='right'>288</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j721e.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j721e.dtsi</a></td><td class='right'>59</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts</a></td><td class='right'>659</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso</a></td><td class='right'>85</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso</a></td><td class='right'>53</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j721s2-evm-usb0-type-a.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j721s2-evm-usb0-type-a.dtso</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi</a></td><td class='right'>2212</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 23.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 77.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi</a></td><td class='right'>769</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi</a></td><td class='right'>456</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j721s2-thermal.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j721s2-thermal.dtsi</a></td><td class='right'>104</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j721s2-ti-ipc-firmware.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j721s2-ti-ipc-firmware.dtsi</a></td><td class='right'>253</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j721s2.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j721s2.dtsi</a></td><td class='right'>174</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtso</a></td><td class='right'>329</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j722s-evm-csi2-quad-tevi-ov5640.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j722s-evm-csi2-quad-tevi-ov5640.dtso</a></td><td class='right'>323</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j722s-evm.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j722s-evm.dts</a></td><td class='right'>857</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j722s-main.dtsi</a></td><td class='right'>469</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j722s-ti-ipc-firmware.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j722s-ti-ipc-firmware.dtsi</a></td><td class='right'>163</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j722s.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j722s.dtsi</a></td><td class='right'>238</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j742s2-evm.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j742s2-evm.dts</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j742s2-main.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j742s2-main.dtsi</a></td><td class='right'>45</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j742s2-mcu-wakeup.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j742s2-mcu-wakeup.dtsi</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j742s2.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j742s2.dtsi</a></td><td class='right'>99</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso</a></td><td class='right'>80</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso</a></td><td class='right'>140</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso</a></td><td class='right'>80</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j784s4-evm.dts</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi</a></td><td class='right'>148</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi</a></td><td class='right'>1291</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 13.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 86.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-usb0-type-a.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-usb0-type-a.dtso</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi</a></td><td class='right'>2751</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 28.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 71.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi</a></td><td class='right'>765</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-thermal-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j784s4-j742s2-thermal-common.dtsi</a></td><td class='right'>104</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-ti-ipc-firmware-common.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j784s4-j742s2-ti-ipc-firmware-common.dtsi</a></td><td class='right'>350</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi</a></td><td class='right'>128</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j784s4-ti-ipc-firmware.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j784s4-ti-ipc-firmware.dtsi</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-j784s4.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-j784s4.dtsi</a></td><td class='right'>172</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-pinctrl.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-pinctrl.h</a></td><td class='right'>149</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/ti/k3-serdes.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/ti/k3-serdes.h</a></td><td class='right'>212</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/toshiba/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/toshiba/Makefile</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts</a></td><td class='right'>75</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrb.dts</a></td><td class='right'>55</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi</a></td><td class='right'>40</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/toshiba/tmpv7708.dtsi</a></td><td class='right'>517</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi</a></td><td class='right'>98</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/xilinx/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/xilinx/Makefile</a></td><td class='right'>42</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/xilinx/versal-net-clk.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/xilinx/versal-net-clk.dtsi</a></td><td class='right'>231</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/xilinx/versal-net-vn-x-b2197-01-revA.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/xilinx/versal-net-vn-x-b2197-01-revA.dts</a></td><td class='right'>116</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/xilinx/versal-net.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/xilinx/versal-net.dtsi</a></td><td class='right'>1160</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 12.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 88.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/xilinx/xlnx-zynqmp-clk.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/xilinx/xlnx-zynqmp-clk.h</a></td><td class='right'>126</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi</a></td><td class='right'>116</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso</a></td><td class='right'>390</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso</a></td><td class='right'>455</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso</a></td><td class='right'>456</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso</a></td><td class='right'>411</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso</a></td><td class='right'>402</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/xilinx/zynqmp-sm-k24-revA.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/xilinx/zynqmp-sm-k24-revA.dts</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts</a></td><td class='right'>463</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/xilinx/zynqmp-smk-k24-revA.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/xilinx/zynqmp-smk-k24-revA.dts</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts</a></td><td class='right'>42</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts</a></td><td class='right'>315</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts</a></td><td class='right'>361</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.6%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 96.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts</a></td><td class='right'>58</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts</a></td><td class='right'>56</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts</a></td><td class='right'>342</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.5%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 96.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts</a></td><td class='right'>352</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.6%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 96.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.1.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.1.dts</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts</a></td><td class='right'>479</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.7%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 95.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts</a></td><td class='right'>384</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.8%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 96.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts</a></td><td class='right'>561</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts</a></td><td class='right'>446</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.5%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 95.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts</a></td><td class='right'>387</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.8%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 96.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts</a></td><td class='right'>58</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/xilinx/zynqmp.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/xilinx/zynqmp.dtsi</a></td><td class='right'>941</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.1%;'/><td class='rem' style='width: 1.7%;'/><td class='none' style='width: 90.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/zte/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/zte/Makefile</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/zte/zx296718-evb.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/zte/zx296718-evb.dts</a></td><td class='right'>144</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 1.5%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/zte/zx296718-pcbox.dts?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/zte/zx296718-pcbox.dts</a></td><td class='right'>143</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 1.5%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/dts/zte/zx296718.dtsi?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/zte/zx296718.dtsi</a></td><td class='right'>627</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 6.5%;'/><td class='none' style='width: 93.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rwxr-xr-x<span class='modechange'>[-rw-r--r--]</span></td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/boot/install.sh?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/install.sh</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/configs/defconfig?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/configs/defconfig</a></td><td class='right'>1149</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 10.6%;'/><td class='rem' style='width: 1.4%;'/><td class='none' style='width: 88.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/configs/hardening.config?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/configs/hardening.config</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/configs/virt.config?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/configs/virt.config</a></td><td class='right'>65</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/Kconfig?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/Kconfig</a></td><td class='right'>260</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.9%;'/><td class='none' style='width: 97.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/Makefile</a></td><td class='right'>65</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/aes-ce-ccm-core.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/aes-ce-ccm-core.S</a></td><td class='right'>265</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 1.8%;'/><td class='none' style='width: 97.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/aes-ce-ccm-glue.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/aes-ce-ccm-glue.c</a></td><td class='right'>272</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 1.6%;'/><td class='none' style='width: 97.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/aes-ce-glue.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/aes-ce-glue.c</a></td><td class='right'>91</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/aes-ce.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/aes-ce.S</a></td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/aes-cipher-glue.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/aes-cipher-glue.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/aes-glue-ce.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/aes-glue-ce.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/aes-glue-neon.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/aes-glue-neon.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/aes-glue.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/aes-glue.c</a></td><td class='right'>458</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 2.7%;'/><td class='none' style='width: 95.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/aes-modes.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/aes-modes.S</a></td><td class='right'>435</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.2%;'/><td class='rem' style='width: 1.3%;'/><td class='none' style='width: 95.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/aes-neon.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/aes-neon.S</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/aes-neonbs-core.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/aes-neonbs-core.S</a></td><td class='right'>275</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 2.1%;'/><td class='none' style='width: 97.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/aes-neonbs-glue.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/aes-neonbs-glue.c</a></td><td class='right'>314</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 2.1%;'/><td class='none' style='width: 96.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/chacha-neon-core.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/chacha-neon-core.S</a></td><td class='right'>860</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 8.9%;'/><td class='none' style='width: 91.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/chacha-neon-glue.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/chacha-neon-glue.c</a></td><td class='right'>235</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 2.4%;'/><td class='none' style='width: 97.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/crct10dif-ce-core.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/crct10dif-ce-core.S</a></td><td class='right'>536</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 5.6%;'/><td class='none' style='width: 94.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/crct10dif-ce-glue.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/crct10dif-ce-glue.c</a></td><td class='right'>125</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 1.3%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/ghash-ce-core.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/ghash-ce-core.S</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/ghash-ce-glue.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/ghash-ce-glue.c</a></td><td class='right'>670</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.8%;'/><td class='rem' style='width: 4.2%;'/><td class='none' style='width: 93.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/nh-neon-core.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/nh-neon-core.S</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/nhpoly1305-neon-glue.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/nhpoly1305-neon-glue.c</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/poly1305-armv8.pl?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/poly1305-armv8.pl</a></td><td class='right'>913</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 9.5%;'/><td class='none' style='width: 90.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/poly1305-core.S_shipped?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/poly1305-core.S_shipped</a></td><td class='right'>835</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 8.7%;'/><td class='none' style='width: 91.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/poly1305-glue.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/poly1305-glue.c</a></td><td class='right'>224</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 2.3%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/sha1-ce-core.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/sha1-ce-core.S</a></td><td class='right'>163</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 1.7%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/sha1-ce-glue.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/sha1-ce-glue.c</a></td><td class='right'>141</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 1.5%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/sha2-ce-core.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/sha2-ce-core.S</a></td><td class='right'>169</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 1.8%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/sha2-ce-glue.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/sha2-ce-glue.c</a></td><td class='right'>176</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 1.8%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/sha256-core.S_shipped?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/sha256-core.S_shipped</a></td><td class='right'>2069</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 21.5%;'/><td class='none' style='width: 78.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/sha256-glue.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/sha256-glue.c</a></td><td class='right'>196</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 2.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/sha3-ce-core.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/sha3-ce-core.S</a></td><td class='right'>233</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 2.4%;'/><td class='none' style='width: 97.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/sha3-ce-glue.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/sha3-ce-glue.c</a></td><td class='right'>158</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 1.6%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/sha512-armv8.pl?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/sha512-armv8.pl</a></td><td class='right'>786</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 8.2%;'/><td class='none' style='width: 91.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/sha512-ce-core.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/sha512-ce-core.S</a></td><td class='right'>219</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 2.3%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/sha512-ce-glue.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/sha512-ce-glue.c</a></td><td class='right'>120</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 1.2%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/sha512-core.S_shipped?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/sha512-core.S_shipped</a></td><td class='right'>1093</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 11.4%;'/><td class='none' style='width: 88.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/sha512-glue.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/sha512-glue.c</a></td><td class='right'>93</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 1.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/sm3-ce-core.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/sm3-ce-core.S</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/sm3-ce-glue.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/sm3-ce-glue.c</a></td><td class='right'>51</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/sm3-neon-core.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/sm3-neon-core.S</a></td><td class='right'>601</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/sm3-neon-glue.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/sm3-neon-glue.c</a></td><td class='right'>67</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/sm4-ce-asm.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/sm4-ce-asm.h</a></td><td class='right'>209</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/sm4-ce-ccm-core.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/sm4-ce-ccm-core.S</a></td><td class='right'>329</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/sm4-ce-ccm-glue.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/sm4-ce-ccm-glue.c</a></td><td class='right'>285</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/sm4-ce-cipher-core.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/sm4-ce-cipher-core.S</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/sm4-ce-cipher-glue.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/sm4-ce-cipher-glue.c</a></td><td class='right'>80</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/sm4-ce-core.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/sm4-ce-core.S</a></td><td class='right'>963</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.7%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 90.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/sm4-ce-gcm-core.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/sm4-ce-gcm-core.S</a></td><td class='right'>742</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/sm4-ce-gcm-glue.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/sm4-ce-gcm-glue.c</a></td><td class='right'>262</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/sm4-ce-glue.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/sm4-ce-glue.c</a></td><td class='right'>741</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.2%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 92.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/sm4-ce.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/sm4-ce.h</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/sm4-neon-core.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/sm4-neon-core.S</a></td><td class='right'>566</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/crypto/sm4-neon-glue.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/crypto/sm4-neon-glue.c</a></td><td class='right'>248</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/hyperv/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/hyperv/Makefile</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/hyperv/hv_core.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/hyperv/hv_core.c</a></td><td class='right'>197</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/hyperv/mshyperv.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/hyperv/mshyperv.c</a></td><td class='right'>136</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/Kbuild?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/Kbuild</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/acpi.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/acpi.h</a></td><td class='right'>56</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/alternative-macros.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/alternative-macros.h</a></td><td class='right'>268</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/alternative.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/alternative.h</a></td><td class='right'>281</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 2.8%;'/><td class='none' style='width: 97.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/apple_m1_pmu.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/apple_m1_pmu.h</a></td><td class='right'>65</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/arch_gicv3.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/arch_gicv3.h</a></td><td class='right'>62</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/arch_timer.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/arch_timer.h</a></td><td class='right'>110</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/archrandom.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/archrandom.h</a></td><td class='right'>117</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/arm_pmuv3.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/arm_pmuv3.h</a></td><td class='right'>191</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/asm-bug.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/asm-bug.h</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/asm-extable.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/asm-extable.h</a></td><td class='right'>137</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/asm-prototypes.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/asm-prototypes.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/asm-uaccess.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/asm-uaccess.h</a></td><td class='right'>48</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/asm_pointer_auth.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/asm_pointer_auth.h</a></td><td class='right'>91</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/assembler.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/assembler.h</a></td><td class='right'>518</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.4%;'/><td class='rem' style='width: 2.0%;'/><td class='none' style='width: 94.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/atomic.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/atomic.h</a></td><td class='right'>46</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/atomic_ll_sc.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/atomic_ll_sc.h</a></td><td class='right'>184</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 1.0%;'/><td class='none' style='width: 98.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/atomic_lse.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/atomic_lse.h</a></td><td class='right'>362</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 2.4%;'/><td class='none' style='width: 96.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/barrier.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/barrier.h</a></td><td class='right'>104</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/bitops.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/bitops.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/boot.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/boot.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/brk-imm.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/brk-imm.h</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/bug.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/bug.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/cache.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/cache.h</a></td><td class='right'>88</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/cacheflush.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/cacheflush.h</a></td><td class='right'>142</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.9%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/cfi.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/cfi.h</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/checksum.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/checksum.h</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/cmpxchg.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/cmpxchg.h</a></td><td class='right'>57</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/compat.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/compat.h</a></td><td class='right'>120</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 1.1%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/compiler.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/compiler.h</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/cpu.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/cpu.h</a></td><td class='right'>59</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/cpu_ops.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/cpu_ops.h</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/cpucaps.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/cpucaps.h</a></td><td class='right'>135</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/cpufeature.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/cpufeature.h</a></td><td class='right'>589</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.8%;'/><td class='rem' style='width: 1.3%;'/><td class='none' style='width: 93.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/cpuidle.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/cpuidle.h</a></td><td class='right'>42</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/cputype.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/cputype.h</a></td><td class='right'>178</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/crash_reserve.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/crash_reserve.h</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/current.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/current.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/daifflags.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/daifflags.h</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/debug-monitors.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/debug-monitors.h</a></td><td class='right'>59</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/device.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/device.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/efi.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/efi.h</a></td><td class='right'>105</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/el2_setup.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/el2_setup.h</a></td><td class='right'>593</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/elf.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/elf.h</a></td><td class='right'>93</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/entry-common.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/entry-common.h</a></td><td class='right'>57</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/esr.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/esr.h</a></td><td class='right'>315</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.7%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 96.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/exception.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/exception.h</a></td><td class='right'>83</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/exec.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/exec.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/extable.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/extable.h</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/fb.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/fb.h</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/fixmap.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/fixmap.h</a></td><td class='right'>49</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/fpsimd.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/fpsimd.h</a></td><td class='right'>375</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.5%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 96.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/fpsimdmacros.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/fpsimdmacros.h</a></td><td class='right'>167</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/fpu.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/fpu.h</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/ftrace.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/ftrace.h</a></td><td class='right'>161</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/futex.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/futex.h</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/gcs.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/gcs.h</a></td><td class='right'>196</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/gpr-num.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/gpr-num.h</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/hardirq.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/hardirq.h</a></td><td class='right'>94</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/hugetlb.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/hugetlb.h</a></td><td class='right'>87</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/hw_breakpoint.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/hw_breakpoint.h</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/hwcap.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/hwcap.h</a></td><td class='right'>93</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/hyp_image.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/hyp_image.h</a></td><td class='right'>68</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/hypervisor.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/hypervisor.h</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/image.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/image.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/insn-def.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/insn-def.h</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/insn.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/insn.h</a></td><td class='right'>361</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.2%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 96.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/io.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/io.h</a></td><td class='right'>247</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.9%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 97.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/irq.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/irq.h</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/irq_work.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/irq_work.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/irqflags.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/irqflags.h</a></td><td class='right'>199</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/jump_label.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/jump_label.h</a></td><td class='right'>53</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/kasan.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/kasan.h</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/kernel-pgtable.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/kernel-pgtable.h</a></td><td class='right'>167</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 1.2%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/kexec.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/kexec.h</a></td><td class='right'>39</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/kfence.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/kfence.h</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/kgdb.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/kgdb.h</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/kprobes.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/kprobes.h</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/kvm_arm.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/kvm_arm.h</a></td><td class='right'>223</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.9%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/kvm_asm.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/kvm_asm.h</a></td><td class='right'>361</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.2%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 96.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/kvm_coproc.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/kvm_coproc.h</a></td><td class='right'>46</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/kvm_emulate.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/kvm_emulate.h</a></td><td class='right'>499</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.4%;'/><td class='rem' style='width: 1.7%;'/><td class='none' style='width: 94.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/kvm_host.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/kvm_host.h</a></td><td class='right'>1667</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 13.7%;'/><td class='rem' style='width: 3.6%;'/><td class='none' style='width: 82.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/kvm_hyp.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/kvm_hyp.h</a></td><td class='right'>130</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/kvm_mmu.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/kvm_mmu.h</a></td><td class='right'>600</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 4.2%;'/><td class='none' style='width: 93.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/kvm_mte.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/kvm_mte.h</a></td><td class='right'>66</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/kvm_nested.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/kvm_nested.h</a></td><td class='right'>409</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/kvm_pgtable.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/kvm_pgtable.h</a></td><td class='right'>881</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/kvm_pkvm.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/kvm_pkvm.h</a></td><td class='right'>203</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/kvm_ptrauth.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/kvm_ptrauth.h</a></td><td class='right'>65</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/kvm_ras.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/kvm_ras.h</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/kvm_types.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/kvm_types.h</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/linkage.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/linkage.h</a></td><td class='right'>49</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/lse.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/lse.h</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/mem_encrypt.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/mem_encrypt.h</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/memory.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/memory.h</a></td><td class='right'>233</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 97.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/mman.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/mman.h</a></td><td class='right'>98</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/mmu.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/mmu.h</a></td><td class='right'>132</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/mmu_context.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/mmu_context.h</a></td><td class='right'>230</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 97.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/mmzone.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/mmzone.h</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/module.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/module.h</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/module.lds.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/module.lds.h</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/mshyperv.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/mshyperv.h</a></td><td class='right'>66</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/mte-def.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/mte-def.h</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/mte-kasan.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/mte-kasan.h</a></td><td class='right'>264</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/mte.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/mte.h</a></td><td class='right'>286</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/neon.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/neon.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/numa.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/numa.h</a></td><td class='right'>45</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/page-def.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/page-def.h</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/page.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/page.h</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/paravirt.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/paravirt.h</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/paravirt_api_clock.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/paravirt_api_clock.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/pci.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/pci.h</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/percpu.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/percpu.h</a></td><td class='right'>80</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/perf_event.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/perf_event.h</a></td><td class='right'>204</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 2.1%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/pgalloc.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/pgalloc.h</a></td><td class='right'>91</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/pgtable-hwdef.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/pgtable-hwdef.h</a></td><td class='right'>283</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 1.6%;'/><td class='none' style='width: 97.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/pgtable-prot.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/pgtable-prot.h</a></td><td class='right'>207</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/pgtable-types.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/pgtable-types.h</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/pgtable.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/pgtable.h</a></td><td class='right'>1508</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 13.4%;'/><td class='rem' style='width: 2.2%;'/><td class='none' style='width: 84.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/pkeys.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/pkeys.h</a></td><td class='right'>106</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/pointer_auth.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/pointer_auth.h</a></td><td class='right'>113</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/por.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/por.h</a></td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/preempt.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/preempt.h</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/probes.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/probes.h</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/proc-fns.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/proc-fns.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/processor.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/processor.h</a></td><td class='right'>266</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.9%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 97.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/ptdump.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/ptdump.h</a></td><td class='right'>69</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/ptrace.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/ptrace.h</a></td><td class='right'>77</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/rqspinlock.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/rqspinlock.h</a></td><td class='right'>93</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/rsi.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/rsi.h</a></td><td class='right'>70</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/rsi_cmds.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/rsi_cmds.h</a></td><td class='right'>162</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/rsi_smc.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/rsi_smc.h</a></td><td class='right'>193</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/runtime-const.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/runtime-const.h</a></td><td class='right'>88</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/rwonce.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/rwonce.h</a></td><td class='right'>69</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/scs.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/scs.h</a></td><td class='right'>60</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/sdei.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/sdei.h</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/seccomp.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/seccomp.h</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/sections.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/sections.h</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/semihost.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/semihost.h</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/set_memory.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/set_memory.h</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/setup.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/setup.h</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/signal.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/signal.h</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/simd.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/simd.h</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/smp.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/smp.h</a></td><td class='right'>88</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/smp_plat.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/smp_plat.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/sparsemem.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/sparsemem.h</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/spectre.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/spectre.h</a></td><td class='right'>123</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/spinlock.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/spinlock.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/spinlock_types.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/spinlock_types.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/stackprotector.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/stackprotector.h</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/stacktrace.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/stacktrace.h</a></td><td class='right'>203</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 1.4%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/stacktrace/common.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/stacktrace/common.h</a></td><td class='right'>171</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/stacktrace/frame.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/stacktrace/frame.h</a></td><td class='right'>48</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/stacktrace/nvhe.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/stacktrace/nvhe.h</a></td><td class='right'>55</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/stage2_pgtable.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/stage2_pgtable.h</a></td><td class='right'>206</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 2.1%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/string.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/string.h</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/suspend.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/suspend.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/syscall.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/syscall.h</a></td><td class='right'>57</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/syscall_wrapper.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/syscall_wrapper.h</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/sysreg.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/sysreg.h</a></td><td class='right'>1265</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.5%;'/><td class='rem' style='width: 4.7%;'/><td class='none' style='width: 86.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/system_misc.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/system_misc.h</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/text-patching.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/text-patching.h</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/thread_info.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/thread_info.h</a></td><td class='right'>54</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/tlb.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/tlb.h</a></td><td class='right'>73</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/tlbbatch.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/tlbbatch.h</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/tlbflush.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/tlbflush.h</a></td><td class='right'>430</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.1%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 95.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/topology.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/topology.h</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/trans_pgd.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/trans_pgd.h</a></td><td class='right'>41</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/traps.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/traps.h</a></td><td class='right'>101</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/uaccess.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/uaccess.h</a></td><td class='right'>450</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.6%;'/><td class='rem' style='width: 2.0%;'/><td class='none' style='width: 95.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/unistd.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/unistd.h</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/unistd32.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/unistd32.h</a></td><td class='right'>891</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 9.2%;'/><td class='none' style='width: 90.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/uprobes.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/uprobes.h</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/vdso.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/vdso.h</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/vdso/clocksource.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/vdso/clocksource.h</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/vdso/compat_barrier.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/vdso/compat_barrier.h</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/vdso/compat_gettimeofday.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/vdso/compat_gettimeofday.h</a></td><td class='right'>53</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/vdso/getrandom.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/vdso/getrandom.h</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/vdso/gettimeofday.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/vdso/gettimeofday.h</a></td><td class='right'>48</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/vdso/processor.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/vdso/processor.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/vdso/vsyscall.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/vdso/vsyscall.h</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/vectors.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/vectors.h</a></td><td class='right'>73</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/virt.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/virt.h</a></td><td class='right'>89</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/vmalloc.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/vmalloc.h</a></td><td class='right'>70</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/vmap_stack.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/vmap_stack.h</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/vncr_mapping.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/vncr_mapping.h</a></td><td class='right'>112</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/word-at-a-time.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/word-at-a-time.h</a></td><td class='right'>39</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/xen/events.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/xen/events.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/xen/page.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/xen/page.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/xen/swiotlb-xen.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/xen/swiotlb-xen.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/xen/xen-ops.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/xen/xen-ops.h</a> (renamed from arch/arm64/include/asm/xen/page-coherent.h)</td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/asm/xor.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/asm/xor.h</a></td><td class='right'>43</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/uapi/asm/Kbuild?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/uapi/asm/Kbuild</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/uapi/asm/bitsperlong.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/uapi/asm/bitsperlong.h</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/uapi/asm/hwcap.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/uapi/asm/hwcap.h</a></td><td class='right'>73</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/uapi/asm/kvm.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/uapi/asm/kvm.h</a></td><td class='right'>200</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/uapi/asm/mman.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/uapi/asm/mman.h</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/uapi/asm/perf_regs.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/uapi/asm/perf_regs.h</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/uapi/asm/ptrace.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/uapi/asm/ptrace.h</a></td><td class='right'>94</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/uapi/asm/sigcontext.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/uapi/asm/sigcontext.h</a></td><td class='right'>118</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/uapi/asm/sve_context.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/uapi/asm/sve_context.h</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/include/uapi/asm/unistd.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/include/uapi/asm/unistd.h</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/Makefile</a></td><td class='right'>65</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/Makefile.syscalls?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/Makefile.syscalls</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/acpi.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/acpi.c</a></td><td class='right'>224</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/acpi_numa.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/acpi_numa.c</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/acpi_parking_protocol.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/acpi_parking_protocol.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/alternative.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/alternative.c</a></td><td class='right'>158</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/armv8_deprecated.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/armv8_deprecated.c</a></td><td class='right'>583</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.9%;'/><td class='rem' style='width: 3.1%;'/><td class='none' style='width: 93.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/asm-offsets.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/asm-offsets.c</a></td><td class='right'>119</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/cacheinfo.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/cacheinfo.c</a></td><td class='right'>57</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/compat_alignment.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/compat_alignment.c</a></td><td class='right'>385</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/cpu-reset.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/cpu-reset.S</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/cpu-reset.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/cpu-reset.h</a></td><td class='right'>32</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/cpu_errata.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/cpu_errata.c</a></td><td class='right'>968</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.7%;'/><td class='rem' style='width: 5.4%;'/><td class='none' style='width: 89.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/cpufeature.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/cpufeature.c</a></td><td class='right'>3308</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 26.0%;'/><td class='rem' style='width: 8.4%;'/><td class='none' style='width: 65.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/cpuidle.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/cpuidle.c</a></td><td class='right'>105</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 1.1%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/cpuinfo.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/cpuinfo.c</a></td><td class='right'>462</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.1%;'/><td class='rem' style='width: 1.7%;'/><td class='none' style='width: 95.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/crash_core.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/crash_core.c</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/crash_dump.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/crash_dump.c</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/debug-monitors.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/debug-monitors.c</a></td><td class='right'>305</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 1.8%;'/><td class='none' style='width: 96.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/efi-entry.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/efi-entry.S</a></td><td class='right'>68</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/efi-header.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/efi-header.S</a></td><td class='right'>155</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/efi-rt-wrapper.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/efi-rt-wrapper.S</a></td><td class='right'>59</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/efi.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/efi.c</a></td><td class='right'>194</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/elfcore.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/elfcore.c</a></td><td class='right'>139</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/entry-common.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/entry-common.c</a></td><td class='right'>850</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.9%;'/><td class='rem' style='width: 0.9%;'/><td class='none' style='width: 91.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/entry-fpsimd.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/entry-fpsimd.S</a></td><td class='right'>109</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/entry-ftrace.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/entry-ftrace.S</a></td><td class='right'>311</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 1.5%;'/><td class='none' style='width: 96.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/entry.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/entry.S</a></td><td class='right'>1099</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.7%;'/><td class='rem' style='width: 5.7%;'/><td class='none' style='width: 88.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/fpsimd.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/fpsimd.c</a></td><td class='right'>1611</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 12.0%;'/><td class='rem' style='width: 4.7%;'/><td class='none' style='width: 83.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/ftrace.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/ftrace.c</a></td><td class='right'>481</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.0%;'/><td class='rem' style='width: 1.0%;'/><td class='none' style='width: 95.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/head.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/head.S</a></td><td class='right'>983</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.7%;'/><td class='rem' style='width: 7.5%;'/><td class='none' style='width: 89.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/hibernate-asm.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/hibernate-asm.S</a></td><td class='right'>83</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/hibernate.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/hibernate.c</a></td><td class='right'>427</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 2.7%;'/><td class='none' style='width: 95.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/hw_breakpoint.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/hw_breakpoint.c</a></td><td class='right'>123</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/hyp-stub.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/hyp-stub.S</a></td><td class='right'>171</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/idle.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/idle.c</a></td><td class='right'>45</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/image-vars.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/image-vars.h</a></td><td class='right'>154</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/image.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/image.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/io.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/io.c</a></td><td class='right'>113</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/irq.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/irq.c</a></td><td class='right'>105</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/jump_label.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/jump_label.c</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/kaslr.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/kaslr.c</a></td><td class='right'>215</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 2.0%;'/><td class='none' style='width: 97.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/kexec_image.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/kexec_image.c</a></td><td class='right'>60</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/kgdb.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/kgdb.c</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/kuser32.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/kuser32.S</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/machine_kexec.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/machine_kexec.c</a></td><td class='right'>279</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 1.7%;'/><td class='none' style='width: 97.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/machine_kexec_file.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/machine_kexec_file.c</a></td><td class='right'>247</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 2.0%;'/><td class='none' style='width: 97.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/module-plts.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/module-plts.c</a></td><td class='right'>91</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/module.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/module.c</a></td><td class='right'>223</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 1.2%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/module.lds?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/module.lds</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/mte.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/mte.c</a></td><td class='right'>655</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/paravirt.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/paravirt.c</a></td><td class='right'>68</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/patching.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/patching.c</a></td><td class='right'>239</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/pci.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/pci.c</a></td><td class='right'>178</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 1.8%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/perf_callchain.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/perf_callchain.c</a></td><td class='right'>162</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 1.6%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/perf_event.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/perf_event.c</a></td><td class='right'>1192</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 12.4%;'/><td class='none' style='width: 87.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/perf_regs.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/perf_regs.c</a></td><td class='right'>58</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/pi/.gitignore?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/pi/.gitignore</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/pi/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/pi/Makefile</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/pi/idreg-override.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/pi/idreg-override.c</a></td><td class='right'>427</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/pi/kaslr_early.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/pi/kaslr_early.c</a></td><td class='right'>62</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/pi/map_kernel.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/pi/map_kernel.c</a></td><td class='right'>289</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/pi/map_range.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/pi/map_range.c</a></td><td class='right'>109</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/pi/patch-scs.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/pi/patch-scs.c</a></td><td class='right'>293</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/pi/pi.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/pi/pi.h</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/pi/relacheck.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/pi/relacheck.c</a></td><td class='right'>130</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/pi/relocate.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/pi/relocate.c</a></td><td class='right'>64</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/pointer_auth.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/pointer_auth.c</a></td><td class='right'>69</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/probes/decode-insn.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/probes/decode-insn.c</a></td><td class='right'>58</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/probes/decode-insn.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/probes/decode-insn.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/probes/kprobes.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/probes/kprobes.c</a></td><td class='right'>408</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 2.9%;'/><td class='none' style='width: 95.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/probes/kprobes_trampoline.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/probes/kprobes_trampoline.S</a></td><td class='right'>78</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/probes/simulate-insn.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/probes/simulate-insn.c</a></td><td class='right'>75</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/probes/simulate-insn.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/probes/simulate-insn.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/probes/uprobes.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/probes/uprobes.c</a></td><td class='right'>83</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/process.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/process.c</a></td><td class='right'>700</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.3%;'/><td class='rem' style='width: 2.0%;'/><td class='none' style='width: 92.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/proton-pack.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/proton-pack.c</a></td><td class='right'>1204</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 12.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 87.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/psci.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/psci.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/ptrace.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/ptrace.c</a></td><td class='right'>1215</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.2%;'/><td class='rem' style='width: 3.4%;'/><td class='none' style='width: 87.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/reloc_test_core.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/reloc_test_core.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/reloc_test_syms.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/reloc_test_syms.S</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/relocate_kernel.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/relocate_kernel.S</a></td><td class='right'>125</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/return_address.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/return_address.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/rsi.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/rsi.c</a></td><td class='right'>175</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/sdei.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/sdei.c</a></td><td class='right'>145</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/setup.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/setup.c</a></td><td class='right'>163</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/signal.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/signal.c</a></td><td class='right'>1079</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.5%;'/><td class='rem' style='width: 1.7%;'/><td class='none' style='width: 88.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/signal32.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/signal32.c</a></td><td class='right'>88</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/sigreturn32.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/sigreturn32.S</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/sleep.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/sleep.S</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/smccc-call.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/smccc-call.S</a></td><td class='right'>67</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/smp.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/smp.c</a></td><td class='right'>680</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.6%;'/><td class='rem' style='width: 2.4%;'/><td class='none' style='width: 92.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/smp_spin_table.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/smp_spin_table.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/ssbd.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/ssbd.c</a></td><td class='right'>129</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 1.3%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/stacktrace.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/stacktrace.c</a></td><td class='right'>670</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.6%;'/><td class='rem' style='width: 1.4%;'/><td class='none' style='width: 93.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/suspend.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/suspend.c</a></td><td class='right'>55</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/sys.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/sys.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/sys32.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/sys32.c</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/sys_compat.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/sys_compat.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/syscall.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/syscall.c</a></td><td class='right'>141</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/time.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/time.c</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/topology.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/topology.c</a></td><td class='right'>518</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.2%;'/><td class='rem' style='width: 2.1%;'/><td class='none' style='width: 94.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/trace-events-emulation.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/trace-events-emulation.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/traps.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/traps.c</a></td><td class='right'>776</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.3%;'/><td class='rem' style='width: 3.8%;'/><td class='none' style='width: 91.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/vdso-wrap.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/vdso-wrap.S</a> (renamed from arch/arm64/kernel/vdso/vdso.S)</td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/vdso.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/vdso.c</a></td><td class='right'>302</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 2.0%;'/><td class='none' style='width: 96.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/vdso/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/vdso/Makefile</a></td><td class='right'>75</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rwxr-xr-x</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/vdso/gen_vdso_offsets.sh?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/vdso/gen_vdso_offsets.sh</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/vdso/note.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/vdso/note.S</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/vdso/sigreturn.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/vdso/sigreturn.S</a></td><td class='right'>74</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/vdso/vdso.lds.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/vdso/vdso.lds.S</a></td><td class='right'>41</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/vdso/vgetrandom-chacha.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/vdso/vgetrandom-chacha.S</a></td><td class='right'>172</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/vdso/vgetrandom.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/vdso/vgetrandom.c</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/vdso/vgettimeofday.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/vdso/vgettimeofday.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/vdso32-wrap.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/vdso32-wrap.S</a> (renamed from arch/arm64/kernel/vdso32/vdso.S)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/vdso32/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/vdso32/Makefile</a></td><td class='right'>125</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.9%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/vdso32/sigreturn.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/vdso32/sigreturn.S</a></td><td class='right'>55</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/vdso32/vdso.lds.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/vdso32/vdso.lds.S</a></td><td class='right'>45</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/vdso32/vgettimeofday.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/vdso32/vgettimeofday.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/vmcore_info.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/vmcore_info.c</a></td><td class='right'>39</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/vmlinux.lds.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/vmlinux.lds.S</a></td><td class='right'>266</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.1%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 97.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kernel/watchdog_hld.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kernel/watchdog_hld.c</a></td><td class='right'>94</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/.gitignore?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/.gitignore</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/Kconfig?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/Kconfig</a></td><td class='right'>81</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/Makefile</a></td><td class='right'>76</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/arch_timer.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/arch_timer.c</a></td><td class='right'>1712</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 17.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 82.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/arm.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/arm.c</a></td><td class='right'>3012</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 31.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 68.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/at.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/at.c</a></td><td class='right'>1795</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 18.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 81.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/config.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/config.c</a></td><td class='right'>1520</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 15.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 84.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/debug.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/debug.c</a></td><td class='right'>389</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.3%;'/><td class='rem' style='width: 1.7%;'/><td class='none' style='width: 96.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/emulate-nested.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/emulate-nested.c</a></td><td class='right'>2854</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 29.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 70.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/fpsimd.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/fpsimd.c</a></td><td class='right'>138</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/guest.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/guest.c</a></td><td class='right'>489</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.4%;'/><td class='rem' style='width: 1.7%;'/><td class='none' style='width: 94.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/handle_exit.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/handle_exit.c</a></td><td class='right'>449</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.6%;'/><td class='rem' style='width: 1.1%;'/><td class='none' style='width: 95.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp-init.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp-init.S</a></td><td class='right'>163</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 1.7%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp.S</a></td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/Makefile</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/aarch32.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/aarch32.c</a></td><td class='right'>154</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/debug-sr.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/debug-sr.c</a></td><td class='right'>224</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 2.3%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/entry.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/entry.S</a></td><td class='right'>133</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/exception.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/exception.c</a></td><td class='right'>377</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/fpsimd.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/fpsimd.S</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/hyp-constants.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/hyp-constants.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/hyp-entry.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/hyp-entry.S</a></td><td class='right'>282</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 1.8%;'/><td class='none' style='width: 97.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/include/hyp/adjust_pc.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/include/hyp/adjust_pc.h</a></td><td class='right'>53</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/include/hyp/debug-sr.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/include/hyp/debug-sr.h</a></td><td class='right'>172</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/include/hyp/fault.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/include/hyp/fault.h</a></td><td class='right'>104</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/include/hyp/switch.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/include/hyp/switch.h</a></td><td class='right'>952</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h</a></td><td class='right'>377</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/include/nvhe/early_alloc.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/include/nvhe/early_alloc.h</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/include/nvhe/ffa.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/include/nvhe/ffa.h</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/include/nvhe/gfp.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/include/nvhe/gfp.h</a></td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/include/nvhe/mem_protect.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/include/nvhe/mem_protect.h</a></td><td class='right'>76</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/include/nvhe/memory.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/include/nvhe/memory.h</a></td><td class='right'>153</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/include/nvhe/mm.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/include/nvhe/mm.h</a></td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/include/nvhe/pkvm.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/include/nvhe/pkvm.h</a></td><td class='right'>92</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/include/nvhe/spinlock.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/include/nvhe/spinlock.h</a></td><td class='right'>125</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/include/nvhe/trap_handler.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/include/nvhe/trap_handler.h</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/nvhe/.gitignore?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/nvhe/.gitignore</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/nvhe/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/nvhe/Makefile</a></td><td class='right'>108</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/nvhe/cache.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/nvhe/cache.S</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/nvhe/debug-sr.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/nvhe/debug-sr.c</a></td><td class='right'>153</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/nvhe/early_alloc.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/nvhe/early_alloc.c</a></td><td class='right'>59</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/nvhe/ffa.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/nvhe/ffa.c</a></td><td class='right'>993</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 10.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 89.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/nvhe/gen-hyprel.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/nvhe/gen-hyprel.c</a></td><td class='right'>462</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/nvhe/host.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/nvhe/host.S</a></td><td class='right'>303</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/nvhe/hyp-init.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/nvhe/hyp-init.S</a></td><td class='right'>313</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/nvhe/hyp-main.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/nvhe/hyp-main.c</a></td><td class='right'>708</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/nvhe/hyp-smp.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/nvhe/hyp-smp.c</a></td><td class='right'>40</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/nvhe/hyp.lds.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/nvhe/hyp.lds.S</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/nvhe/list_debug.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/nvhe/list_debug.c</a></td><td class='right'>56</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/nvhe/mem_protect.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/nvhe/mem_protect.c</a></td><td class='right'>1396</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 14.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 85.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/nvhe/mm.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/nvhe/mm.c</a></td><td class='right'>504</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/nvhe/page_alloc.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/nvhe/page_alloc.c</a></td><td class='right'>248</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/nvhe/pkvm.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/nvhe/pkvm.c</a></td><td class='right'>894</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/nvhe/psci-relay.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/nvhe/psci-relay.c</a></td><td class='right'>308</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/nvhe/setup.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/nvhe/setup.c</a></td><td class='right'>376</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/nvhe/stacktrace.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/nvhe/stacktrace.c</a></td><td class='right'>158</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/nvhe/switch.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/nvhe/switch.c</a></td><td class='right'>390</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/nvhe/sys_regs.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/nvhe/sys_regs.c</a></td><td class='right'>576</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/nvhe/sysreg-sr.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/nvhe/sysreg-sr.c</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/nvhe/timer-sr.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/nvhe/timer-sr.c</a></td><td class='right'>70</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/nvhe/tlb.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/nvhe/tlb.c</a></td><td class='right'>270</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/pgtable.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/pgtable.c</a></td><td class='right'>1679</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 17.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 82.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/switch.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/switch.c</a></td><td class='right'>875</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 9.1%;'/><td class='none' style='width: 90.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/sysreg-sr.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/sysreg-sr.c</a></td><td class='right'>342</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 3.6%;'/><td class='none' style='width: 96.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/tlb.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/tlb.c</a></td><td class='right'>241</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 2.5%;'/><td class='none' style='width: 97.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/vgic-v2-cpuif-proxy.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/vgic-v2-cpuif-proxy.c</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/vgic-v3-sr.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/vgic-v3-sr.c</a></td><td class='right'>1308</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 13.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 86.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/vhe/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/vhe/Makefile</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/vhe/debug-sr.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/vhe/debug-sr.c</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/vhe/switch.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/vhe/switch.c</a></td><td class='right'>688</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/vhe/sysreg-sr.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/vhe/sysreg-sr.c</a></td><td class='right'>277</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/vhe/timer-sr.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/vhe/timer-sr.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hyp/vhe/tlb.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hyp/vhe/tlb.c</a></td><td class='right'>368</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/hypercalls.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/hypercalls.c</a></td><td class='right'>679</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/inject_fault.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/inject_fault.c</a></td><td class='right'>383</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.6%;'/><td class='rem' style='width: 1.3%;'/><td class='none' style='width: 96.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/irq.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/irq.h</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/mmio.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/mmio.c</a></td><td class='right'>234</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/mmu.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/mmu.c</a></td><td class='right'>2575</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 26.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 73.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/nested.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/nested.c</a></td><td class='right'>1919</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 19.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 80.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/pauth.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/pauth.c</a></td><td class='right'>206</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/pkvm.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/pkvm.c</a></td><td class='right'>487</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/pmu-emul.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/pmu-emul.c</a></td><td class='right'>1335</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 13.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 86.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/pmu.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/pmu.c</a></td><td class='right'>188</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.9%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/psci.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/psci.c</a></td><td class='right'>507</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/ptdump.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/ptdump.c</a></td><td class='right'>287</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/pvtime.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/pvtime.c</a></td><td class='right'>133</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/regmap.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/regmap.c</a></td><td class='right'>195</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 2.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/reset.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/reset.c</a></td><td class='right'>354</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 2.5%;'/><td class='none' style='width: 96.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/stacktrace.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/stacktrace.c</a></td><td class='right'>246</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/sys_regs.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/sys_regs.c</a></td><td class='right'>5285</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 41.9%;'/><td class='rem' style='width: 13.0%;'/><td class='none' style='width: 45.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/sys_regs.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/sys_regs.h</a></td><td class='right'>152</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/sys_regs_generic_v8.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/sys_regs_generic_v8.c</a></td><td class='right'>86</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.9%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/trace.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/trace.h</a></td><td class='right'>216</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 2.2%;'/><td class='none' style='width: 97.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/trace_arm.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/trace_arm.h</a></td><td class='right'>426</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/trace_handle_exit.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/trace_handle_exit.h</a></td><td class='right'>144</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/trng.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/trng.c</a></td><td class='right'>85</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/va_layout.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/va_layout.c</a></td><td class='right'>137</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/vgic-sys-reg-v3.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/vgic-sys-reg-v3.c</a></td><td class='right'>587</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.0%;'/><td class='rem' style='width: 2.1%;'/><td class='none' style='width: 93.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/vgic/trace.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/vgic/trace.h</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/vgic/vgic-debug.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/vgic/vgic-debug.c</a></td><td class='right'>557</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/vgic/vgic-init.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/vgic/vgic-init.c</a></td><td class='right'>754</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/vgic/vgic-irqfd.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/vgic/vgic-irqfd.c</a></td><td class='right'>156</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/vgic/vgic-its.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/vgic/vgic-its.c</a></td><td class='right'>2815</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 29.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 70.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/vgic/vgic-kvm-device.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/vgic/vgic-kvm-device.c</a></td><td class='right'>717</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/vgic/vgic-mmio-v2.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/vgic/vgic-mmio-v2.c</a></td><td class='right'>585</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/vgic/vgic-mmio-v3.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/vgic/vgic-mmio-v3.c</a></td><td class='right'>1172</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 12.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 87.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/vgic/vgic-mmio.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/vgic/vgic-mmio.c</a></td><td class='right'>1103</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 11.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 88.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/vgic/vgic-mmio.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/vgic/vgic-mmio.h</a></td><td class='right'>231</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/vgic/vgic-v2.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/vgic/vgic-v2.c</a></td><td class='right'>622</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/vgic/vgic-v3-nested.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/vgic/vgic-v3-nested.c</a></td><td class='right'>407</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/vgic/vgic-v3.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/vgic/vgic-v3.c</a></td><td class='right'>1009</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 10.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 89.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/vgic/vgic-v4.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/vgic/vgic-v4.c</a></td><td class='right'>555</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/vgic/vgic-v5.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/vgic/vgic-v5.c</a></td><td class='right'>52</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/vgic/vgic.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/vgic/vgic.c</a></td><td class='right'>1222</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 12.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 87.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/vgic/vgic.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/vgic/vgic.h</a></td><td class='right'>470</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/kvm/vmid.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/kvm/vmid.c</a></td><td class='right'>195</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/lib/.gitignore?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/lib/.gitignore</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/lib/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/lib/Makefile</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/lib/clear_page.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/lib/clear_page.S</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/lib/clear_user.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/lib/clear_user.S</a></td><td class='right'>74</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/lib/copy_from_user.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/lib/copy_from_user.S</a></td><td class='right'>57</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/lib/copy_in_user.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/lib/copy_in_user.S</a></td><td class='right'>70</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/lib/copy_page.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/lib/copy_page.S</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/lib/copy_template.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/lib/copy_template.S</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/lib/copy_to_user.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/lib/copy_to_user.S</a></td><td class='right'>58</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/lib/crc32.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/lib/crc32.S</a></td><td class='right'>101</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 1.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/lib/csum.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/lib/csum.c</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/lib/delay.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/lib/delay.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/arch/arm64/lib/insn.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/lib/insn.c</a> (renamed from arch/arm64/kernel/insn.c)</td><td class='right'>723</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.1%;'/><td class='rem' style='width: 4.4%;'/><td class='none' style='width: 92.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/lib/kasan_sw_tags.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/lib/kasan_sw_tags.S</a></td><td class='right'>74</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/lib/memchr.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/lib/memchr.S</a></td><td class='right'>70</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/lib/memcmp.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/lib/memcmp.S</a></td><td class='right'>354</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 2.4%;'/><td class='none' style='width: 96.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/lib/memcpy.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/lib/memcpy.S</a></td><td class='right'>313</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.7%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 96.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/lib/memmove.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/lib/memmove.S</a></td><td class='right'>190</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 2.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/lib/memset.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/lib/memset.S</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/lib/mte.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/lib/mte.S</a></td><td class='right'>177</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/lib/strchr.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/lib/strchr.S</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/lib/strcmp.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/lib/strcmp.S</a></td><td class='right'>375</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 2.1%;'/><td class='none' style='width: 96.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/lib/strlen.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/lib/strlen.S</a></td><td class='right'>274</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.9%;'/><td class='rem' style='width: 0.9%;'/><td class='none' style='width: 97.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/lib/strncmp.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/lib/strncmp.S</a></td><td class='right'>483</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.6%;'/><td class='rem' style='width: 2.5%;'/><td class='none' style='width: 95.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/lib/strnlen.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/lib/strnlen.S</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/lib/strrchr.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/lib/strrchr.S</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/lib/uaccess_flushcache.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/lib/uaccess_flushcache.c</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/lib/xor-neon.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/lib/xor-neon.c</a></td><td class='right'>177</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/mm/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/mm/Makefile</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/mm/cache.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/mm/cache.S</a></td><td class='right'>205</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 1.3%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/mm/context.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/mm/context.c</a></td><td class='right'>151</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/mm/contpte.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/mm/contpte.c</a></td><td class='right'>633</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/mm/copypage.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/mm/copypage.c</a></td><td class='right'>62</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/mm/dma-mapping.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/mm/dma-mapping.c</a></td><td class='right'>39</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/mm/extable.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/mm/extable.c</a></td><td class='right'>110</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/mm/fault.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/mm/fault.c</a></td><td class='right'>703</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.2%;'/><td class='rem' style='width: 3.1%;'/><td class='none' style='width: 92.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/mm/fixmap.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/mm/fixmap.c</a></td><td class='right'>175</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/mm/flush.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/mm/flush.c</a></td><td class='right'>46</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/mm/gcs.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/mm/gcs.c</a></td><td class='right'>248</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/mm/hugetlbpage.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/mm/hugetlbpage.c</a></td><td class='right'>442</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.6%;'/><td class='rem' style='width: 2.0%;'/><td class='none' style='width: 95.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/mm/init.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/mm/init.c</a></td><td class='right'>678</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.1%;'/><td class='rem' style='width: 4.0%;'/><td class='none' style='width: 93.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/mm/ioremap.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/mm/ioremap.c</a></td><td class='right'>107</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/mm/kasan_init.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/mm/kasan_init.c</a></td><td class='right'>255</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.1%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 97.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/mm/mem_encrypt.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/mm/mem_encrypt.c</a></td><td class='right'>50</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/mm/mmap.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/mm/mmap.c</a></td><td class='right'>105</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/mm/mmu.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/mm/mmu.c</a></td><td class='right'>1922</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 14.2%;'/><td class='rem' style='width: 5.8%;'/><td class='none' style='width: 80.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/mm/mteswap.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/mm/mteswap.c</a></td><td class='right'>130</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/arch/arm64/mm/numa.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/mm/numa.c</a></td><td class='right'>470</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 4.9%;'/><td class='none' style='width: 95.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/mm/pageattr.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/mm/pageattr.c</a></td><td class='right'>288</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.5%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 97.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/mm/pgd.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/mm/pgd.c</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/mm/physaddr.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/mm/physaddr.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/mm/proc.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/mm/proc.S</a></td><td class='right'>492</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.9%;'/><td class='rem' style='width: 2.2%;'/><td class='none' style='width: 94.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/arch/arm64/mm/ptdump.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/mm/ptdump.c</a> (renamed from arch/arm64/mm/dump.c)</td><td class='right'>236</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 1.1%;'/><td class='none' style='width: 97.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/mm/ptdump_debugfs.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/mm/ptdump_debugfs.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/mm/trans_pgd-asm.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/mm/trans_pgd-asm.S</a></td><td class='right'>65</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/mm/trans_pgd.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/mm/trans_pgd.c</a></td><td class='right'>301</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/net/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/net/Makefile</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/net/bpf_jit.h?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/net/bpf_jit.h</a></td><td class='right'>147</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/net/bpf_jit_comp.c?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/net/bpf_jit_comp.c</a></td><td class='right'>2592</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 24.8%;'/><td class='rem' style='width: 2.1%;'/><td class='none' style='width: 73.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/net/bpf_timed_may_goto.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/net/bpf_timed_may_goto.S</a></td><td class='right'>40</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/tools/Makefile?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/tools/Makefile</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/tools/cpucaps?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/tools/cpucaps</a></td><td class='right'>125</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rwxr-xr-x</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/tools/gen-cpucaps.awk?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/tools/gen-cpucaps.awk</a></td><td class='right'>40</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rwxr-xr-x</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/tools/gen-sysreg.awk?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/tools/gen-sysreg.awk</a></td><td class='right'>411</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/tools/syscall_32.tbl?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/tools/syscall_32.tbl</a></td><td class='right'>484</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.0%;'/></tr></table></td></tr>
<tr><td class='mode'>l---------</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/tools/syscall_64.tbl?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/tools/syscall_64.tbl</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/arch/arm64/tools/sysreg?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/tools/sysreg</a></td><td class='right'>5157</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 53.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 46.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/arch/arm64/xen/hypercall.S?id2=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/xen/hypercall.S</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
</table><div class='diffstat-summary'>3453 files changed, 999708 insertions, 77989 deletions</div><table summary='diff' class='diff'><tr><td><div class='head'>diff --git a/arch/arm64/Kbuild b/arch/arm64/Kbuild<br/>index d6465823b281..5bfbf7d79c99 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/Kbuild?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/Kbuild</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/Kbuild?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/Kbuild</a></div><div class='hunk'>@@ -1,6 +1,9 @@</div><div class='ctx'> # SPDX-License-Identifier: GPL-2.0-only</div><div class='del'>-obj-y			+= kernel/ mm/</div><div class='del'>-obj-$(CONFIG_NET)	+= net/</div><div class='add'>+obj-y			+= kernel/ mm/ net/</div><div class='ctx'> obj-$(CONFIG_KVM)	+= kvm/</div><div class='ctx'> obj-$(CONFIG_XEN)	+= xen/</div><div class='add'>+obj-$(subst m,y,$(CONFIG_HYPERV))	+= hyperv/</div><div class='ctx'> obj-$(CONFIG_CRYPTO)	+= crypto/</div><div class='add'>+</div><div class='add'>+# for cleaning</div><div class='add'>+subdir- += boot</div><div class='head'>diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig<br/>index 40fb05d96c60..93173f0a09c7 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/Kconfig?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/Kconfig</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/Kconfig?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/Kconfig</a></div><div class='hunk'>@@ -1,16 +1,31 @@</div><div class='ctx'> # SPDX-License-Identifier: GPL-2.0-only</div><div class='ctx'> config ARM64</div><div class='ctx'> 	def_bool y</div><div class='add'>+	select ACPI_APMT if ACPI</div><div class='ctx'> 	select ACPI_CCA_REQUIRED if ACPI</div><div class='ctx'> 	select ACPI_GENERIC_GSI if ACPI</div><div class='ctx'> 	select ACPI_GTDT if ACPI</div><div class='add'>+	select ACPI_HOTPLUG_CPU if ACPI_PROCESSOR &amp;&amp; HOTPLUG_CPU</div><div class='ctx'> 	select ACPI_IORT if ACPI</div><div class='ctx'> 	select ACPI_REDUCED_HARDWARE_ONLY if ACPI</div><div class='ctx'> 	select ACPI_MCFG if (ACPI &amp;&amp; PCI)</div><div class='ctx'> 	select ACPI_SPCR_TABLE if ACPI</div><div class='ctx'> 	select ACPI_PPTT if ACPI</div><div class='add'>+	select ARCH_HAS_DEBUG_WX</div><div class='add'>+	select ARCH_BINFMT_ELF_EXTRA_PHDRS</div><div class='add'>+	select ARCH_BINFMT_ELF_STATE</div><div class='add'>+	select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE &amp;&amp; MIGRATION</div><div class='add'>+	select ARCH_ENABLE_MEMORY_HOTPLUG</div><div class='add'>+	select ARCH_ENABLE_MEMORY_HOTREMOVE</div><div class='add'>+	select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS &gt; 2</div><div class='add'>+	select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE</div><div class='add'>+	select ARCH_HAS_CACHE_LINE_SIZE</div><div class='add'>+	select ARCH_HAS_CC_PLATFORM</div><div class='add'>+	select ARCH_HAS_CPU_CACHE_INVALIDATE_MEMREGION</div><div class='add'>+	select ARCH_HAS_CURRENT_STACK_POINTER</div><div class='ctx'> 	select ARCH_HAS_DEBUG_VIRTUAL</div><div class='del'>-	select ARCH_HAS_DEVMEM_IS_ALLOWED</div><div class='add'>+	select ARCH_HAS_DEBUG_VM_PGTABLE</div><div class='add'>+	select ARCH_HAS_DMA_OPS if XEN</div><div class='ctx'> 	select ARCH_HAS_DMA_PREP_COHERENT</div><div class='ctx'> 	select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI</div><div class='ctx'> 	select ARCH_HAS_FAST_MULTIPLIER</div><div class='hunk'>@@ -18,21 +33,33 @@ config ARM64</div><div class='ctx'> 	select ARCH_HAS_GCOV_PROFILE_ALL</div><div class='ctx'> 	select ARCH_HAS_GIGANTIC_PAGE</div><div class='ctx'> 	select ARCH_HAS_KCOV</div><div class='add'>+	select ARCH_HAS_KERNEL_FPU_SUPPORT if KERNEL_MODE_NEON</div><div class='ctx'> 	select ARCH_HAS_KEEPINITRD</div><div class='ctx'> 	select ARCH_HAS_MEMBARRIER_SYNC_CORE</div><div class='del'>-	select ARCH_HAS_PTE_DEVMAP</div><div class='add'>+	select ARCH_HAS_MEM_ENCRYPT</div><div class='add'>+	select ARCH_SUPPORTS_MSEAL_SYSTEM_MAPPINGS</div><div class='add'>+	select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS</div><div class='add'>+	select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE</div><div class='add'>+	select ARCH_HAS_NONLEAF_PMD_YOUNG if ARM64_HAFT</div><div class='add'>+	select ARCH_HAS_PREEMPT_LAZY</div><div class='add'>+	select ARCH_HAS_PTDUMP</div><div class='ctx'> 	select ARCH_HAS_PTE_SPECIAL</div><div class='add'>+	select ARCH_HAS_HW_PTE_YOUNG</div><div class='ctx'> 	select ARCH_HAS_SETUP_DMA_OPS</div><div class='ctx'> 	select ARCH_HAS_SET_DIRECT_MAP</div><div class='ctx'> 	select ARCH_HAS_SET_MEMORY</div><div class='add'>+	select ARCH_HAS_FORCE_DMA_UNENCRYPTED</div><div class='add'>+	select ARCH_STACKWALK</div><div class='ctx'> 	select ARCH_HAS_STRICT_KERNEL_RWX</div><div class='ctx'> 	select ARCH_HAS_STRICT_MODULE_RWX</div><div class='ctx'> 	select ARCH_HAS_SYNC_DMA_FOR_DEVICE</div><div class='ctx'> 	select ARCH_HAS_SYNC_DMA_FOR_CPU</div><div class='ctx'> 	select ARCH_HAS_SYSCALL_WRAPPER</div><div class='del'>-	select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT</div><div class='ctx'> 	select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST</div><div class='add'>+	select ARCH_HAS_ZONE_DMA_SET if EXPERT</div><div class='add'>+	select ARCH_HAVE_ELF_PROT</div><div class='ctx'> 	select ARCH_HAVE_NMI_SAFE_CMPXCHG</div><div class='add'>+	select ARCH_HAVE_TRACE_MMIO_ACCESS</div><div class='ctx'> 	select ARCH_INLINE_READ_LOCK if !PREEMPTION</div><div class='ctx'> 	select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION</div><div class='ctx'> 	select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION</div><div class='hunk'>@@ -60,19 +87,41 @@ config ARM64</div><div class='ctx'> 	select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION</div><div class='ctx'> 	select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION</div><div class='ctx'> 	select ARCH_KEEP_MEMBLOCK</div><div class='add'>+	select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE</div><div class='ctx'> 	select ARCH_USE_CMPXCHG_LOCKREF</div><div class='add'>+	select ARCH_USE_GNU_PROPERTY</div><div class='add'>+	select ARCH_USE_MEMTEST</div><div class='ctx'> 	select ARCH_USE_QUEUED_RWLOCKS</div><div class='ctx'> 	select ARCH_USE_QUEUED_SPINLOCKS</div><div class='add'>+	select ARCH_USE_SYM_ANNOTATIONS</div><div class='add'>+	select ARCH_SUPPORTS_DEBUG_PAGEALLOC</div><div class='add'>+	select ARCH_SUPPORTS_HUGETLBFS</div><div class='ctx'> 	select ARCH_SUPPORTS_MEMORY_FAILURE</div><div class='add'>+	select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK</div><div class='add'>+	select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN</div><div class='add'>+	select ARCH_SUPPORTS_LTO_CLANG_THIN</div><div class='add'>+	select ARCH_SUPPORTS_CFI</div><div class='ctx'> 	select ARCH_SUPPORTS_ATOMIC_RMW</div><div class='del'>-	select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 &amp;&amp; (GCC_VERSION &gt;= 50000 || CC_IS_CLANG)</div><div class='add'>+	select ARCH_SUPPORTS_INT128 if CC_HAS_INT128</div><div class='ctx'> 	select ARCH_SUPPORTS_NUMA_BALANCING</div><div class='add'>+	select ARCH_SUPPORTS_PAGE_TABLE_CHECK</div><div class='add'>+	select ARCH_SUPPORTS_PER_VMA_LOCK</div><div class='add'>+	select ARCH_SUPPORTS_HUGE_PFNMAP if TRANSPARENT_HUGEPAGE</div><div class='add'>+	select ARCH_SUPPORTS_RT</div><div class='add'>+	select ARCH_SUPPORTS_SCHED_SMT</div><div class='add'>+	select ARCH_SUPPORTS_SCHED_CLUSTER</div><div class='add'>+	select ARCH_SUPPORTS_SCHED_MC</div><div class='add'>+	select ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH</div><div class='ctx'> 	select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT</div><div class='ctx'> 	select ARCH_WANT_DEFAULT_BPF_JIT</div><div class='ctx'> 	select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT</div><div class='ctx'> 	select ARCH_WANT_FRAME_POINTERS</div><div class='ctx'> 	select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES &amp;&amp; !ARM64_VA_BITS_36)</div><div class='del'>-	select ARCH_HAS_UBSAN_SANITIZE_ALL</div><div class='add'>+	select ARCH_WANT_LD_ORPHAN_WARN</div><div class='add'>+	select ARCH_WANTS_EXECMEM_LATE</div><div class='add'>+	select ARCH_WANTS_NO_INSTR</div><div class='add'>+	select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES</div><div class='add'>+	select ARCH_HAS_UBSAN</div><div class='ctx'> 	select ARM_AMBA</div><div class='ctx'> 	select ARM_ARCH_TIMER</div><div class='ctx'> 	select ARM_GIC</div><div class='hunk'>@@ -80,55 +129,72 @@ config ARM64</div><div class='ctx'> 	select ARM_GIC_V2M if PCI</div><div class='ctx'> 	select ARM_GIC_V3</div><div class='ctx'> 	select ARM_GIC_V3_ITS if PCI</div><div class='add'>+	select ARM_GIC_V5</div><div class='ctx'> 	select ARM_PSCI_FW</div><div class='ctx'> 	select BUILDTIME_TABLE_SORT</div><div class='ctx'> 	select CLONE_BACKWARDS</div><div class='ctx'> 	select COMMON_CLK</div><div class='ctx'> 	select CPU_PM if (SUSPEND || CPU_IDLE)</div><div class='del'>-	select CRC32</div><div class='add'>+	select CPUMASK_OFFSTACK if NR_CPUS &gt; 256</div><div class='ctx'> 	select DCACHE_WORD_ACCESS</div><div class='add'>+	select HAVE_EXTRA_IPI_TRACEPOINTS</div><div class='add'>+	select DYNAMIC_FTRACE if FUNCTION_TRACER</div><div class='add'>+	select DMA_BOUNCE_UNALIGNED_KMALLOC</div><div class='ctx'> 	select DMA_DIRECT_REMAP</div><div class='ctx'> 	select EDAC_SUPPORT</div><div class='ctx'> 	select FRAME_POINTER</div><div class='add'>+	select FUNCTION_ALIGNMENT_4B</div><div class='add'>+	select FUNCTION_ALIGNMENT_8B if DYNAMIC_FTRACE_WITH_CALL_OPS</div><div class='ctx'> 	select GENERIC_ALLOCATOR</div><div class='ctx'> 	select GENERIC_ARCH_TOPOLOGY</div><div class='del'>-	select GENERIC_CLOCKEVENTS</div><div class='ctx'> 	select GENERIC_CLOCKEVENTS_BROADCAST</div><div class='ctx'> 	select GENERIC_CPU_AUTOPROBE</div><div class='add'>+	select GENERIC_CPU_CACHE_MAINTENANCE</div><div class='add'>+	select GENERIC_CPU_DEVICES</div><div class='ctx'> 	select GENERIC_CPU_VULNERABILITIES</div><div class='ctx'> 	select GENERIC_EARLY_IOREMAP</div><div class='ctx'> 	select GENERIC_IDLE_POLL_SETUP</div><div class='del'>-	select GENERIC_IRQ_MULTI_HANDLER</div><div class='add'>+	select GENERIC_IOREMAP</div><div class='add'>+	select GENERIC_IRQ_ENTRY</div><div class='add'>+	select GENERIC_IRQ_IPI</div><div class='add'>+	select GENERIC_IRQ_KEXEC_CLEAR_VM_FORWARD</div><div class='ctx'> 	select GENERIC_IRQ_PROBE</div><div class='ctx'> 	select GENERIC_IRQ_SHOW</div><div class='ctx'> 	select GENERIC_IRQ_SHOW_LEVEL</div><div class='add'>+	select GENERIC_LIB_DEVMEM_IS_ALLOWED</div><div class='ctx'> 	select GENERIC_PCI_IOMAP</div><div class='del'>-	select GENERIC_PTDUMP</div><div class='ctx'> 	select GENERIC_SCHED_CLOCK</div><div class='ctx'> 	select GENERIC_SMP_IDLE_THREAD</div><div class='del'>-	select GENERIC_STRNCPY_FROM_USER</div><div class='del'>-	select GENERIC_STRNLEN_USER</div><div class='ctx'> 	select GENERIC_TIME_VSYSCALL</div><div class='ctx'> 	select GENERIC_GETTIMEOFDAY</div><div class='del'>-	select HANDLE_DOMAIN_IRQ</div><div class='ctx'> 	select HARDIRQS_SW_RESEND</div><div class='add'>+	select HAS_IOPORT</div><div class='add'>+	select HAVE_MOVE_PMD</div><div class='add'>+	select HAVE_MOVE_PUD</div><div class='ctx'> 	select HAVE_PCI</div><div class='ctx'> 	select HAVE_ACPI_APEI if (ACPI &amp;&amp; EFI)</div><div class='del'>-	select HAVE_ALIGNED_STRUCT_PAGE if SLUB</div><div class='add'>+	select HAVE_ALIGNED_STRUCT_PAGE</div><div class='ctx'> 	select HAVE_ARCH_AUDITSYSCALL</div><div class='ctx'> 	select HAVE_ARCH_BITREVERSE</div><div class='ctx'> 	select HAVE_ARCH_COMPILER_H</div><div class='add'>+	select HAVE_ARCH_HUGE_VMALLOC</div><div class='ctx'> 	select HAVE_ARCH_HUGE_VMAP</div><div class='ctx'> 	select HAVE_ARCH_JUMP_LABEL</div><div class='ctx'> 	select HAVE_ARCH_JUMP_LABEL_RELATIVE</div><div class='del'>-	select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES &amp;&amp; ARM64_VA_BITS_48)</div><div class='del'>-	select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN</div><div class='add'>+	select HAVE_ARCH_KASAN</div><div class='add'>+	select HAVE_ARCH_KASAN_VMALLOC</div><div class='add'>+	select HAVE_ARCH_KASAN_SW_TAGS</div><div class='add'>+	select HAVE_ARCH_KASAN_HW_TAGS if ARM64_MTE</div><div class='add'>+	# Some instrumentation may be unsound, hence EXPERT</div><div class='add'>+	select HAVE_ARCH_KCSAN if EXPERT</div><div class='add'>+	select HAVE_ARCH_KFENCE</div><div class='ctx'> 	select HAVE_ARCH_KGDB</div><div class='add'>+	select HAVE_ARCH_KSTACK_ERASE</div><div class='ctx'> 	select HAVE_ARCH_MMAP_RND_BITS</div><div class='ctx'> 	select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT</div><div class='ctx'> 	select HAVE_ARCH_PREL32_RELOCATIONS</div><div class='add'>+	select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET</div><div class='ctx'> 	select HAVE_ARCH_SECCOMP_FILTER</div><div class='del'>-	select HAVE_ARCH_STACKLEAK</div><div class='ctx'> 	select HAVE_ARCH_THREAD_STRUCT_WHITELIST</div><div class='ctx'> 	select HAVE_ARCH_TRACEHOOK</div><div class='ctx'> 	select HAVE_ARCH_TRANSPARENT_HUGEPAGE</div><div class='hunk'>@@ -139,42 +205,63 @@ config ARM64</div><div class='ctx'> 	select HAVE_C_RECORDMCOUNT</div><div class='ctx'> 	select HAVE_CMPXCHG_DOUBLE</div><div class='ctx'> 	select HAVE_CMPXCHG_LOCAL</div><div class='del'>-	select HAVE_CONTEXT_TRACKING</div><div class='del'>-	select HAVE_COPY_THREAD_TLS</div><div class='del'>-	select HAVE_DEBUG_BUGVERBOSE</div><div class='add'>+	select HAVE_CONTEXT_TRACKING_USER</div><div class='ctx'> 	select HAVE_DEBUG_KMEMLEAK</div><div class='ctx'> 	select HAVE_DMA_CONTIGUOUS</div><div class='ctx'> 	select HAVE_DYNAMIC_FTRACE</div><div class='del'>-	select HAVE_DYNAMIC_FTRACE_WITH_REGS \</div><div class='del'>-		if $(cc-option,-fpatchable-function-entry=2)</div><div class='add'>+	select HAVE_DYNAMIC_FTRACE_WITH_ARGS \</div><div class='add'>+		if (GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS || \</div><div class='add'>+		    CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS)</div><div class='add'>+	select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS \</div><div class='add'>+		if DYNAMIC_FTRACE_WITH_ARGS &amp;&amp; DYNAMIC_FTRACE_WITH_CALL_OPS</div><div class='add'>+	select HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS \</div><div class='add'>+		if (DYNAMIC_FTRACE_WITH_ARGS &amp;&amp; !CFI &amp;&amp; \</div><div class='add'>+		    (CC_IS_CLANG || !CC_OPTIMIZE_FOR_SIZE))</div><div class='add'>+	select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \</div><div class='add'>+		if DYNAMIC_FTRACE_WITH_ARGS</div><div class='add'>+	select HAVE_SAMPLE_FTRACE_DIRECT</div><div class='add'>+	select HAVE_SAMPLE_FTRACE_DIRECT_MULTI</div><div class='add'>+	select HAVE_BUILDTIME_MCOUNT_SORT</div><div class='ctx'> 	select HAVE_EFFICIENT_UNALIGNED_ACCESS</div><div class='del'>-	select HAVE_FAST_GUP</div><div class='del'>-	select HAVE_FTRACE_MCOUNT_RECORD</div><div class='add'>+	select HAVE_GUP_FAST</div><div class='add'>+	select HAVE_FTRACE_GRAPH_FUNC</div><div class='ctx'> 	select HAVE_FUNCTION_TRACER</div><div class='ctx'> 	select HAVE_FUNCTION_ERROR_INJECTION</div><div class='add'>+	select HAVE_FUNCTION_GRAPH_FREGS</div><div class='ctx'> 	select HAVE_FUNCTION_GRAPH_TRACER</div><div class='ctx'> 	select HAVE_GCC_PLUGINS</div><div class='add'>+	select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS &amp;&amp; \</div><div class='add'>+		HW_PERF_EVENTS &amp;&amp; HAVE_PERF_EVENTS_NMI</div><div class='ctx'> 	select HAVE_HW_BREAKPOINT if PERF_EVENTS</div><div class='add'>+	select HAVE_IOREMAP_PROT</div><div class='ctx'> 	select HAVE_IRQ_TIME_ACCOUNTING</div><div class='del'>-	select HAVE_MEMBLOCK_NODE_MAP if NUMA</div><div class='add'>+	select HAVE_LIVEPATCH</div><div class='add'>+	select HAVE_MOD_ARCH_SPECIFIC</div><div class='ctx'> 	select HAVE_NMI</div><div class='del'>-	select HAVE_PATA_PLATFORM</div><div class='ctx'> 	select HAVE_PERF_EVENTS</div><div class='add'>+	select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI</div><div class='ctx'> 	select HAVE_PERF_REGS</div><div class='ctx'> 	select HAVE_PERF_USER_STACK_DUMP</div><div class='add'>+	select HAVE_PREEMPT_DYNAMIC_KEY</div><div class='ctx'> 	select HAVE_REGS_AND_STACK_ACCESS_API</div><div class='add'>+	select HAVE_RELIABLE_STACKTRACE</div><div class='add'>+	select HAVE_POSIX_CPU_TIMERS_TASK_WORK</div><div class='ctx'> 	select HAVE_FUNCTION_ARG_ACCESS_API</div><div class='del'>-	select HAVE_FUTEX_CMPXCHG if FUTEX</div><div class='ctx'> 	select MMU_GATHER_RCU_TABLE_FREE</div><div class='ctx'> 	select HAVE_RSEQ</div><div class='add'>+	select HAVE_RUST if RUSTC_SUPPORTS_ARM64</div><div class='ctx'> 	select HAVE_STACKPROTECTOR</div><div class='ctx'> 	select HAVE_SYSCALL_TRACEPOINTS</div><div class='ctx'> 	select HAVE_KPROBES</div><div class='ctx'> 	select HAVE_KRETPROBES</div><div class='ctx'> 	select HAVE_GENERIC_VDSO</div><div class='del'>-	select IOMMU_DMA if IOMMU_SUPPORT</div><div class='add'>+	select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU</div><div class='add'>+	select HOTPLUG_SMT if HOTPLUG_CPU</div><div class='ctx'> 	select IRQ_DOMAIN</div><div class='ctx'> 	select IRQ_FORCED_THREADING</div><div class='add'>+	select JUMP_LABEL</div><div class='add'>+	select KASAN_VMALLOC if KASAN</div><div class='add'>+	select LOCK_MM_AND_FIND_VMA</div><div class='ctx'> 	select MODULES_USE_ELF_RELA</div><div class='ctx'> 	select NEED_DMA_MAP_STATE</div><div class='ctx'> 	select NEED_SG_DMA_LENGTH</div><div class='hunk'>@@ -189,53 +276,82 @@ config ARM64</div><div class='ctx'> 	select SWIOTLB</div><div class='ctx'> 	select SYSCTL_EXCEPTION_TRACE</div><div class='ctx'> 	select THREAD_INFO_IN_TASK</div><div class='add'>+	select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD</div><div class='add'>+	select HAVE_ARCH_USERFAULTFD_WP if USERFAULTFD</div><div class='add'>+	select TRACE_IRQFLAGS_SUPPORT</div><div class='add'>+	select TRACE_IRQFLAGS_NMI_SUPPORT</div><div class='add'>+	select HAVE_SOFTIRQ_ON_OWN_STACK</div><div class='add'>+	select USER_STACKTRACE_SUPPORT</div><div class='add'>+	select VDSO_GETRANDOM</div><div class='add'>+	select VMAP_STACK</div><div class='ctx'> 	help</div><div class='ctx'> 	  ARM 64-bit (AArch64) Linux support.</div><div class='ctx'> </div><div class='add'>+config RUSTC_SUPPORTS_ARM64</div><div class='add'>+	def_bool y</div><div class='add'>+	depends on CPU_LITTLE_ENDIAN</div><div class='add'>+	# Shadow call stack is only supported on certain rustc versions.</div><div class='add'>+	#</div><div class='add'>+	# When using the UNWIND_PATCH_PAC_INTO_SCS option, rustc version 1.80+ is</div><div class='add'>+	# required due to use of the -Zfixed-x18 flag.</div><div class='add'>+	#</div><div class='add'>+	# Otherwise, rustc version 1.82+ is required due to use of the</div><div class='add'>+	# -Zsanitizer=shadow-call-stack flag.</div><div class='add'>+	depends on !SHADOW_CALL_STACK || RUSTC_VERSION &gt;= 108200 || RUSTC_VERSION &gt;= 108000 &amp;&amp; UNWIND_PATCH_PAC_INTO_SCS</div><div class='add'>+</div><div class='add'>+config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS</div><div class='add'>+	def_bool CC_IS_CLANG</div><div class='add'>+	# https://github.com/ClangBuiltLinux/linux/issues/1507</div><div class='add'>+	depends on AS_IS_GNU || (AS_IS_LLVM &amp;&amp; (LD_IS_LLD || LD_VERSION &gt;= 23600))</div><div class='add'>+</div><div class='add'>+config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS</div><div class='add'>+	def_bool CC_IS_GCC</div><div class='add'>+	depends on $(cc-option,-fpatchable-function-entry=2)</div><div class='add'>+</div><div class='ctx'> config 64BIT</div><div class='ctx'> 	def_bool y</div><div class='ctx'> </div><div class='ctx'> config MMU</div><div class='ctx'> 	def_bool y</div><div class='ctx'> </div><div class='del'>-config ARM64_PAGE_SHIFT</div><div class='add'>+config ARM64_CONT_PTE_SHIFT</div><div class='ctx'> 	int</div><div class='del'>-	default 16 if ARM64_64K_PAGES</div><div class='del'>-	default 14 if ARM64_16K_PAGES</div><div class='del'>-	default 12</div><div class='add'>+	default 5 if PAGE_SIZE_64KB</div><div class='add'>+	default 7 if PAGE_SIZE_16KB</div><div class='add'>+	default 4</div><div class='ctx'> </div><div class='del'>-config ARM64_CONT_SHIFT</div><div class='add'>+config ARM64_CONT_PMD_SHIFT</div><div class='ctx'> 	int</div><div class='del'>-	default 5 if ARM64_64K_PAGES</div><div class='del'>-	default 7 if ARM64_16K_PAGES</div><div class='add'>+	default 5 if PAGE_SIZE_64KB</div><div class='add'>+	default 5 if PAGE_SIZE_16KB</div><div class='ctx'> 	default 4</div><div class='ctx'> </div><div class='ctx'> config ARCH_MMAP_RND_BITS_MIN</div><div class='del'>-       default 14 if ARM64_64K_PAGES</div><div class='del'>-       default 16 if ARM64_16K_PAGES</div><div class='del'>-       default 18</div><div class='add'>+	default 14 if PAGE_SIZE_64KB</div><div class='add'>+	default 16 if PAGE_SIZE_16KB</div><div class='add'>+	default 18</div><div class='ctx'> </div><div class='ctx'> # max bits determined by the following formula:</div><div class='del'>-#  VA_BITS - PAGE_SHIFT - 3</div><div class='add'>+#  VA_BITS - PTDESC_TABLE_SHIFT</div><div class='ctx'> config ARCH_MMAP_RND_BITS_MAX</div><div class='del'>-       default 19 if ARM64_VA_BITS=36</div><div class='del'>-       default 24 if ARM64_VA_BITS=39</div><div class='del'>-       default 27 if ARM64_VA_BITS=42</div><div class='del'>-       default 30 if ARM64_VA_BITS=47</div><div class='del'>-       default 29 if ARM64_VA_BITS=48 &amp;&amp; ARM64_64K_PAGES</div><div class='del'>-       default 31 if ARM64_VA_BITS=48 &amp;&amp; ARM64_16K_PAGES</div><div class='del'>-       default 33 if ARM64_VA_BITS=48</div><div class='del'>-       default 14 if ARM64_64K_PAGES</div><div class='del'>-       default 16 if ARM64_16K_PAGES</div><div class='del'>-       default 18</div><div class='add'>+	default 19 if ARM64_VA_BITS=36</div><div class='add'>+	default 24 if ARM64_VA_BITS=39</div><div class='add'>+	default 27 if ARM64_VA_BITS=42</div><div class='add'>+	default 30 if ARM64_VA_BITS=47</div><div class='add'>+	default 29 if (ARM64_VA_BITS=48 || ARM64_VA_BITS=52) &amp;&amp; ARM64_64K_PAGES</div><div class='add'>+	default 31 if (ARM64_VA_BITS=48 || ARM64_VA_BITS=52) &amp;&amp; ARM64_16K_PAGES</div><div class='add'>+	default 33 if (ARM64_VA_BITS=48 || ARM64_VA_BITS=52)</div><div class='add'>+	default 14 if ARM64_64K_PAGES</div><div class='add'>+	default 16 if ARM64_16K_PAGES</div><div class='add'>+	default 18</div><div class='ctx'> </div><div class='ctx'> config ARCH_MMAP_RND_COMPAT_BITS_MIN</div><div class='del'>-       default 7 if ARM64_64K_PAGES</div><div class='del'>-       default 9 if ARM64_16K_PAGES</div><div class='del'>-       default 11</div><div class='add'>+	default 7 if ARM64_64K_PAGES</div><div class='add'>+	default 9 if ARM64_16K_PAGES</div><div class='add'>+	default 11</div><div class='ctx'> </div><div class='ctx'> config ARCH_MMAP_RND_COMPAT_BITS_MAX</div><div class='del'>-       default 16</div><div class='add'>+	default 16</div><div class='ctx'> </div><div class='ctx'> config NO_IOPORT_MAP</div><div class='ctx'> 	def_bool y if !PCI</div><div class='hunk'>@@ -250,9 +366,6 @@ config ILLEGAL_POINTER_VALUE</div><div class='ctx'> config LOCKDEP_SUPPORT</div><div class='ctx'> 	def_bool y</div><div class='ctx'> </div><div class='del'>-config TRACE_IRQFLAGS_SUPPORT</div><div class='del'>-	def_bool y</div><div class='del'>-</div><div class='ctx'> config GENERIC_BUG</div><div class='ctx'> 	def_bool y</div><div class='ctx'> 	depends on BUG</div><div class='hunk'>@@ -265,23 +378,9 @@ config GENERIC_HWEIGHT</div><div class='ctx'> 	def_bool y</div><div class='ctx'> </div><div class='ctx'> config GENERIC_CSUM</div><div class='del'>-        def_bool y</div><div class='del'>-</div><div class='del'>-config GENERIC_CALIBRATE_DELAY</div><div class='ctx'> 	def_bool y</div><div class='ctx'> </div><div class='del'>-config ZONE_DMA</div><div class='del'>-	bool "Support DMA zone" if EXPERT</div><div class='del'>-	default y</div><div class='del'>-</div><div class='del'>-config ZONE_DMA32</div><div class='del'>-	bool "Support DMA32 zone" if EXPERT</div><div class='del'>-	default y</div><div class='del'>-</div><div class='del'>-config ARCH_ENABLE_MEMORY_HOTPLUG</div><div class='del'>-	def_bool y</div><div class='del'>-</div><div class='del'>-config ARCH_ENABLE_MEMORY_HOTREMOVE</div><div class='add'>+config GENERIC_CALIBRATE_DELAY</div><div class='ctx'> 	def_bool y</div><div class='ctx'> </div><div class='ctx'> config SMP</div><div class='hunk'>@@ -300,7 +399,9 @@ config PGTABLE_LEVELS</div><div class='ctx'> 	default 3 if ARM64_64K_PAGES &amp;&amp; (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)</div><div class='ctx'> 	default 3 if ARM64_4K_PAGES &amp;&amp; ARM64_VA_BITS_39</div><div class='ctx'> 	default 3 if ARM64_16K_PAGES &amp;&amp; ARM64_VA_BITS_47</div><div class='add'>+	default 4 if ARM64_16K_PAGES &amp;&amp; (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)</div><div class='ctx'> 	default 4 if !ARM64_64K_PAGES &amp;&amp; ARM64_VA_BITS_48</div><div class='add'>+	default 5 if ARM64_4K_PAGES &amp;&amp; ARM64_VA_BITS_52</div><div class='ctx'> </div><div class='ctx'> config ARCH_SUPPORTS_UPROBES</div><div class='ctx'> 	def_bool y</div><div class='hunk'>@@ -311,27 +412,80 @@ config ARCH_PROC_KCORE_TEXT</div><div class='ctx'> config BROKEN_GAS_INST</div><div class='ctx'> 	def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)</div><div class='ctx'> </div><div class='add'>+config BUILTIN_RETURN_ADDRESS_STRIPS_PAC</div><div class='add'>+	bool</div><div class='add'>+	# Clang's __builtin_return_address() strips the PAC since 12.0.0</div><div class='add'>+	# https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2</div><div class='add'>+	default y if CC_IS_CLANG</div><div class='add'>+	# GCC's __builtin_return_address() strips the PAC since 11.1.0,</div><div class='add'>+	# and this was backported to 10.2.0, 9.4.0, 8.5.0, but not earlier</div><div class='add'>+	# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94891</div><div class='add'>+	default y if CC_IS_GCC &amp;&amp; (GCC_VERSION &gt;= 110100)</div><div class='add'>+	default y if CC_IS_GCC &amp;&amp; (GCC_VERSION &gt;= 100200) &amp;&amp; (GCC_VERSION &lt; 110000)</div><div class='add'>+	default y if CC_IS_GCC &amp;&amp; (GCC_VERSION &gt;=  90400) &amp;&amp; (GCC_VERSION &lt; 100000)</div><div class='add'>+	default y if CC_IS_GCC &amp;&amp; (GCC_VERSION &gt;=  80500) &amp;&amp; (GCC_VERSION &lt;  90000)</div><div class='add'>+	default n</div><div class='add'>+</div><div class='ctx'> config KASAN_SHADOW_OFFSET</div><div class='ctx'> 	hex</div><div class='del'>-	depends on KASAN</div><div class='del'>-	default 0xdfffa00000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) &amp;&amp; !KASAN_SW_TAGS</div><div class='del'>-	default 0xdfffd00000000000 if ARM64_VA_BITS_47 &amp;&amp; !KASAN_SW_TAGS</div><div class='del'>-	default 0xdffffe8000000000 if ARM64_VA_BITS_42 &amp;&amp; !KASAN_SW_TAGS</div><div class='del'>-	default 0xdfffffd000000000 if ARM64_VA_BITS_39 &amp;&amp; !KASAN_SW_TAGS</div><div class='del'>-	default 0xdffffffa00000000 if ARM64_VA_BITS_36 &amp;&amp; !KASAN_SW_TAGS</div><div class='del'>-	default 0xefff900000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) &amp;&amp; KASAN_SW_TAGS</div><div class='del'>-	default 0xefffc80000000000 if ARM64_VA_BITS_47 &amp;&amp; KASAN_SW_TAGS</div><div class='del'>-	default 0xeffffe4000000000 if ARM64_VA_BITS_42 &amp;&amp; KASAN_SW_TAGS</div><div class='del'>-	default 0xefffffc800000000 if ARM64_VA_BITS_39 &amp;&amp; KASAN_SW_TAGS</div><div class='del'>-	default 0xeffffff900000000 if ARM64_VA_BITS_36 &amp;&amp; KASAN_SW_TAGS</div><div class='add'>+	depends on KASAN_GENERIC || KASAN_SW_TAGS</div><div class='add'>+	default 0xdfff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 &amp;&amp; !ARM64_16K_PAGES)) &amp;&amp; !KASAN_SW_TAGS</div><div class='add'>+	default 0xdfffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) &amp;&amp; ARM64_16K_PAGES &amp;&amp; !KASAN_SW_TAGS</div><div class='add'>+	default 0xdffffe0000000000 if ARM64_VA_BITS_42 &amp;&amp; !KASAN_SW_TAGS</div><div class='add'>+	default 0xdfffffc000000000 if ARM64_VA_BITS_39 &amp;&amp; !KASAN_SW_TAGS</div><div class='add'>+	default 0xdffffff800000000 if ARM64_VA_BITS_36 &amp;&amp; !KASAN_SW_TAGS</div><div class='add'>+	default 0xefff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 &amp;&amp; !ARM64_16K_PAGES)) &amp;&amp; KASAN_SW_TAGS</div><div class='add'>+	default 0xefffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) &amp;&amp; ARM64_16K_PAGES &amp;&amp; KASAN_SW_TAGS</div><div class='add'>+	default 0xeffffe0000000000 if ARM64_VA_BITS_42 &amp;&amp; KASAN_SW_TAGS</div><div class='add'>+	default 0xefffffc000000000 if ARM64_VA_BITS_39 &amp;&amp; KASAN_SW_TAGS</div><div class='add'>+	default 0xeffffff800000000 if ARM64_VA_BITS_36 &amp;&amp; KASAN_SW_TAGS</div><div class='ctx'> 	default 0xffffffffffffffff</div><div class='ctx'> </div><div class='add'>+config UNWIND_TABLES</div><div class='add'>+	bool</div><div class='add'>+</div><div class='ctx'> source "arch/arm64/Kconfig.platforms"</div><div class='ctx'> </div><div class='ctx'> menu "Kernel Features"</div><div class='ctx'> </div><div class='ctx'> menu "ARM errata workarounds via the alternatives framework"</div><div class='ctx'> </div><div class='add'>+config AMPERE_ERRATUM_AC03_CPU_38</div><div class='add'>+        bool "AmpereOne: AC03_CPU_38: Certain bits in the Virtualization Translation Control Register and Translation Control Registers do not follow RES0 semantics"</div><div class='add'>+	default y</div><div class='add'>+	help</div><div class='add'>+	  This option adds an alternative code sequence to work around Ampere</div><div class='add'>+	  errata AC03_CPU_38 and AC04_CPU_10 on AmpereOne.</div><div class='add'>+</div><div class='add'>+	  The affected design reports FEAT_HAFDBS as not implemented in</div><div class='add'>+	  ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ELx.{HA,HD} are not RES0</div><div class='add'>+	  as required by the architecture. The unadvertised HAFDBS</div><div class='add'>+	  implementation suffers from an additional erratum where hardware</div><div class='add'>+	  A/D updates can occur after a PTE has been marked invalid.</div><div class='add'>+</div><div class='add'>+	  The workaround forces KVM to explicitly set VTCR_EL2.HA to 0,</div><div class='add'>+	  which avoids enabling unadvertised hardware Access Flag management</div><div class='add'>+	  at stage-2.</div><div class='add'>+</div><div class='add'>+	  If unsure, say Y.</div><div class='add'>+</div><div class='add'>+config AMPERE_ERRATUM_AC04_CPU_23</div><div class='add'>+        bool "AmpereOne: AC04_CPU_23:  Failure to synchronize writes to HCR_EL2 may corrupt address translations."</div><div class='add'>+	default y</div><div class='add'>+	help</div><div class='add'>+	  This option adds an alternative code sequence to work around Ampere</div><div class='add'>+	  errata AC04_CPU_23 on AmpereOne.</div><div class='add'>+</div><div class='add'>+	  Updates to HCR_EL2 can rarely corrupt simultaneous translations for</div><div class='add'>+	  data addresses initiated by load/store instructions. Only</div><div class='add'>+	  instruction initiated translations are vulnerable, not translations</div><div class='add'>+	  from prefetches for example. A DSB before the store to HCR_EL2 is</div><div class='add'>+	  sufficient to prevent older instructions from hitting the window</div><div class='add'>+	  for corruption, and an ISB after is sufficient to prevent younger</div><div class='add'>+	  instructions from hitting the window for corruption.</div><div class='add'>+</div><div class='add'>+	  If unsure, say Y.</div><div class='add'>+</div><div class='ctx'> config ARM64_WORKAROUND_CLEAN_CACHE</div><div class='ctx'> 	bool</div><div class='ctx'> </div><div class='hunk'>@@ -443,9 +597,8 @@ config ARM64_ERRATUM_832075</div><div class='ctx'> 	  If unsure, say Y.</div><div class='ctx'> </div><div class='ctx'> config ARM64_ERRATUM_834220</div><div class='del'>-	bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"</div><div class='add'>+	bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault (rare)"</div><div class='ctx'> 	depends on KVM</div><div class='del'>-	default y</div><div class='ctx'> 	help</div><div class='ctx'> 	  This option adds an alternative code sequence to work around ARM</div><div class='ctx'> 	  erratum 834220 on Cortex-A57 parts up to r1p2.</div><div class='hunk'>@@ -461,6 +614,22 @@ config ARM64_ERRATUM_834220</div><div class='ctx'> 	  as it depends on the alternative framework, which will only patch</div><div class='ctx'> 	  the kernel if an affected CPU is detected.</div><div class='ctx'> </div><div class='add'>+	  If unsure, say N.</div><div class='add'>+</div><div class='add'>+config ARM64_ERRATUM_1742098</div><div class='add'>+	bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence"</div><div class='add'>+	depends on COMPAT</div><div class='add'>+	default y</div><div class='add'>+	help</div><div class='add'>+	  This option removes the AES hwcap for aarch32 user-space to</div><div class='add'>+	  workaround erratum 1742098 on Cortex-A57 and Cortex-A72.</div><div class='add'>+</div><div class='add'>+	  Affected parts may corrupt the AES state if an interrupt is</div><div class='add'>+	  taken between a pair of AES instructions. These instructions</div><div class='add'>+	  are only present if the cryptography extensions are present.</div><div class='add'>+	  All software should have a fallback implementation for CPUs</div><div class='add'>+	  that don't implement the cryptography extensions.</div><div class='add'>+</div><div class='ctx'> 	  If unsure, say Y.</div><div class='ctx'> </div><div class='ctx'> config ARM64_ERRATUM_845719</div><div class='hunk'>@@ -487,7 +656,6 @@ config ARM64_ERRATUM_845719</div><div class='ctx'> config ARM64_ERRATUM_843419</div><div class='ctx'> 	bool "Cortex-A53: 843419: A load or store might access an incorrect address"</div><div class='ctx'> 	default y</div><div class='del'>-	select ARM64_MODULE_PLTS if MODULES</div><div class='ctx'> 	help</div><div class='ctx'> 	  This option links the kernel with '--fix-cortex-a53-843419' and</div><div class='ctx'> 	  enables PLT support to replace certain ADRP instructions, which can</div><div class='hunk'>@@ -502,7 +670,7 @@ config ARM64_ERRATUM_1024718</div><div class='ctx'> 	help</div><div class='ctx'> 	  This option adds a workaround for ARM Cortex-A55 Erratum 1024718.</div><div class='ctx'> </div><div class='del'>-	  Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect</div><div class='add'>+	  Affected Cortex-A55 cores (all revisions) could cause incorrect</div><div class='ctx'> 	  update of the hardware dirty bit when the DBM/AP bits are updated</div><div class='ctx'> 	  without a break-before-make. The workaround is to disable the usage</div><div class='ctx'> 	  of hardware DBM locally on the affected cores. CPUs not affected by</div><div class='hunk'>@@ -524,13 +692,13 @@ config ARM64_ERRATUM_1418040</div><div class='ctx'> </div><div class='ctx'> 	  If unsure, say Y.</div><div class='ctx'> </div><div class='del'>-config ARM64_WORKAROUND_SPECULATIVE_AT_VHE</div><div class='add'>+config ARM64_WORKAROUND_SPECULATIVE_AT</div><div class='ctx'> 	bool</div><div class='ctx'> </div><div class='ctx'> config ARM64_ERRATUM_1165522</div><div class='del'>-	bool "Cortex-A76: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"</div><div class='add'>+	bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"</div><div class='ctx'> 	default y</div><div class='del'>-	select ARM64_WORKAROUND_SPECULATIVE_AT_VHE</div><div class='add'>+	select ARM64_WORKAROUND_SPECULATIVE_AT</div><div class='ctx'> 	help</div><div class='ctx'> 	  This option adds a workaround for ARM Cortex-A76 erratum 1165522.</div><div class='ctx'> </div><div class='hunk'>@@ -540,10 +708,23 @@ config ARM64_ERRATUM_1165522</div><div class='ctx'> </div><div class='ctx'> 	  If unsure, say Y.</div><div class='ctx'> </div><div class='add'>+config ARM64_ERRATUM_1319367</div><div class='add'>+	bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"</div><div class='add'>+	default y</div><div class='add'>+	select ARM64_WORKAROUND_SPECULATIVE_AT</div><div class='add'>+	help</div><div class='add'>+	  This option adds work arounds for ARM Cortex-A57 erratum 1319537</div><div class='add'>+	  and A72 erratum 1319367</div><div class='add'>+</div><div class='add'>+	  Cortex-A57 and A72 cores could end-up with corrupted TLBs by</div><div class='add'>+	  speculating an AT instruction during a guest context switch.</div><div class='add'>+</div><div class='add'>+	  If unsure, say Y.</div><div class='add'>+</div><div class='ctx'> config ARM64_ERRATUM_1530923</div><div class='del'>-	bool "Cortex-A55: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"</div><div class='add'>+	bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"</div><div class='ctx'> 	default y</div><div class='del'>-	select ARM64_WORKAROUND_SPECULATIVE_AT_VHE</div><div class='add'>+	select ARM64_WORKAROUND_SPECULATIVE_AT</div><div class='ctx'> 	help</div><div class='ctx'> 	  This option adds a workaround for ARM Cortex-A55 erratum 1530923.</div><div class='ctx'> </div><div class='hunk'>@@ -553,9 +734,27 @@ config ARM64_ERRATUM_1530923</div><div class='ctx'> </div><div class='ctx'> 	  If unsure, say Y.</div><div class='ctx'> </div><div class='add'>+config ARM64_WORKAROUND_REPEAT_TLBI</div><div class='add'>+	bool</div><div class='add'>+</div><div class='add'>+config ARM64_ERRATUM_2441007</div><div class='add'>+	bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)"</div><div class='add'>+	select ARM64_WORKAROUND_REPEAT_TLBI</div><div class='add'>+	help</div><div class='add'>+	  This option adds a workaround for ARM Cortex-A55 erratum #2441007.</div><div class='add'>+</div><div class='add'>+	  Under very rare circumstances, affected Cortex-A55 CPUs</div><div class='add'>+	  may not handle a race between a break-before-make sequence on one</div><div class='add'>+	  CPU, and another CPU accessing the same page. This could allow a</div><div class='add'>+	  store to a page that has been unmapped.</div><div class='add'>+</div><div class='add'>+	  Work around this by adding the affected CPUs to the list that needs</div><div class='add'>+	  TLB sequences to be done twice.</div><div class='add'>+</div><div class='add'>+	  If unsure, say N.</div><div class='add'>+</div><div class='ctx'> config ARM64_ERRATUM_1286807</div><div class='del'>-	bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"</div><div class='del'>-	default y</div><div class='add'>+	bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation (rare)"</div><div class='ctx'> 	select ARM64_WORKAROUND_REPEAT_TLBI</div><div class='ctx'> 	help</div><div class='ctx'> 	  This option adds a workaround for ARM Cortex-A76 erratum 1286807.</div><div class='hunk'>@@ -569,21 +768,7 @@ config ARM64_ERRATUM_1286807</div><div class='ctx'> 	  invalidated has been observed by other observers. The</div><div class='ctx'> 	  workaround repeats the TLBI+DSB operation.</div><div class='ctx'> </div><div class='del'>-config ARM64_WORKAROUND_SPECULATIVE_AT_NVHE</div><div class='del'>-	bool</div><div class='del'>-</div><div class='del'>-config ARM64_ERRATUM_1319367</div><div class='del'>-	bool "Cortex-A57/A72: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"</div><div class='del'>-	default y</div><div class='del'>-	select ARM64_WORKAROUND_SPECULATIVE_AT_NVHE</div><div class='del'>-	help</div><div class='del'>-	  This option adds work arounds for ARM Cortex-A57 erratum 1319537</div><div class='del'>-	  and A72 erratum 1319367</div><div class='del'>-</div><div class='del'>-	  Cortex-A57 and A72 cores could end-up with corrupted TLBs by</div><div class='del'>-	  speculating an AT instruction during a guest context switch.</div><div class='del'>-</div><div class='del'>-	  If unsure, say Y.</div><div class='add'>+	  If unsure, say N.</div><div class='ctx'> </div><div class='ctx'> config ARM64_ERRATUM_1463225</div><div class='ctx'> 	bool "Cortex-A76: Software Step might prevent interrupt recognition"</div><div class='hunk'>@@ -604,8 +789,7 @@ config ARM64_ERRATUM_1463225</div><div class='ctx'> 	  If unsure, say Y.</div><div class='ctx'> </div><div class='ctx'> config ARM64_ERRATUM_1542419</div><div class='del'>-	bool "Neoverse-N1: workaround mis-ordering of instruction fetches"</div><div class='del'>-	default y</div><div class='add'>+	bool "Neoverse-N1: workaround mis-ordering of instruction fetches (rare)"</div><div class='ctx'> 	help</div><div class='ctx'> 	  This option adds a workaround for ARM Neoverse-N1 erratum</div><div class='ctx'> 	  1542419.</div><div class='hunk'>@@ -617,6 +801,358 @@ config ARM64_ERRATUM_1542419</div><div class='ctx'> 	  Workaround the issue by hiding the DIC feature from EL0. This</div><div class='ctx'> 	  forces user-space to perform cache maintenance.</div><div class='ctx'> </div><div class='add'>+	  If unsure, say N.</div><div class='add'>+</div><div class='add'>+config ARM64_ERRATUM_1508412</div><div class='add'>+	bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"</div><div class='add'>+	default y</div><div class='add'>+	help</div><div class='add'>+	  This option adds a workaround for Arm Cortex-A77 erratum 1508412.</div><div class='add'>+</div><div class='add'>+	  Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence</div><div class='add'>+	  of a store-exclusive or read of PAR_EL1 and a load with device or</div><div class='add'>+	  non-cacheable memory attributes. The workaround depends on a firmware</div><div class='add'>+	  counterpart.</div><div class='add'>+</div><div class='add'>+	  KVM guests must also have the workaround implemented or they can</div><div class='add'>+	  deadlock the system.</div><div class='add'>+</div><div class='add'>+	  Work around the issue by inserting DMB SY barriers around PAR_EL1</div><div class='add'>+	  register reads and warning KVM users. The DMB barrier is sufficient</div><div class='add'>+	  to prevent a speculative PAR_EL1 read.</div><div class='add'>+</div><div class='add'>+	  If unsure, say Y.</div><div class='add'>+</div><div class='add'>+config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE</div><div class='add'>+	bool</div><div class='add'>+</div><div class='add'>+config ARM64_ERRATUM_2051678</div><div class='add'>+	bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"</div><div class='add'>+	default y</div><div class='add'>+	help</div><div class='add'>+	  This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.</div><div class='add'>+	  Affected Cortex-A510 might not respect the ordering rules for</div><div class='add'>+	  hardware update of the page table's dirty bit. The workaround</div><div class='add'>+	  is to not enable the feature on affected CPUs.</div><div class='add'>+</div><div class='add'>+	  If unsure, say Y.</div><div class='add'>+</div><div class='add'>+config ARM64_ERRATUM_2077057</div><div class='add'>+	bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"</div><div class='add'>+	default y</div><div class='add'>+	help</div><div class='add'>+	  This option adds the workaround for ARM Cortex-A510 erratum 2077057.</div><div class='add'>+	  Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is</div><div class='add'>+	  expected, but a Pointer Authentication trap is taken instead. The</div><div class='add'>+	  erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow</div><div class='add'>+	  EL1 to cause a return to EL2 with a guest controlled ELR_EL2.</div><div class='add'>+</div><div class='add'>+	  This can only happen when EL2 is stepping EL1.</div><div class='add'>+</div><div class='add'>+	  When these conditions occur, the SPSR_EL2 value is unchanged from the</div><div class='add'>+	  previous guest entry, and can be restored from the in-memory copy.</div><div class='add'>+</div><div class='add'>+	  If unsure, say Y.</div><div class='add'>+</div><div class='add'>+config ARM64_ERRATUM_2658417</div><div class='add'>+	bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result"</div><div class='add'>+	default y</div><div class='add'>+	help</div><div class='add'>+	  This option adds the workaround for ARM Cortex-A510 erratum 2658417.</div><div class='add'>+	  Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for</div><div class='add'>+	  BFMMLA or VMMLA instructions in rare circumstances when a pair of</div><div class='add'>+	  A510 CPUs are using shared neon hardware. As the sharing is not</div><div class='add'>+	  discoverable by the kernel, hide the BF16 HWCAP to indicate that</div><div class='add'>+	  user-space should not be using these instructions.</div><div class='add'>+</div><div class='add'>+	  If unsure, say Y.</div><div class='add'>+</div><div class='add'>+config ARM64_ERRATUM_2119858</div><div class='add'>+	bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"</div><div class='add'>+	default y</div><div class='add'>+	depends on CORESIGHT_TRBE</div><div class='add'>+	select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE</div><div class='add'>+	help</div><div class='add'>+	  This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.</div><div class='add'>+</div><div class='add'>+	  Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace</div><div class='add'>+	  data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in</div><div class='add'>+	  the event of a WRAP event.</div><div class='add'>+</div><div class='add'>+	  Work around the issue by always making sure we move the TRBPTR_EL1 by</div><div class='add'>+	  256 bytes before enabling the buffer and filling the first 256 bytes of</div><div class='add'>+	  the buffer with ETM ignore packets upon disabling.</div><div class='add'>+</div><div class='add'>+	  If unsure, say Y.</div><div class='add'>+</div><div class='add'>+config ARM64_ERRATUM_2139208</div><div class='add'>+	bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"</div><div class='add'>+	default y</div><div class='add'>+	depends on CORESIGHT_TRBE</div><div class='add'>+	select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE</div><div class='add'>+	help</div><div class='add'>+	  This option adds the workaround for ARM Neoverse-N2 erratum 2139208.</div><div class='add'>+</div><div class='add'>+	  Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace</div><div class='add'>+	  data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in</div><div class='add'>+	  the event of a WRAP event.</div><div class='add'>+</div><div class='add'>+	  Work around the issue by always making sure we move the TRBPTR_EL1 by</div><div class='add'>+	  256 bytes before enabling the buffer and filling the first 256 bytes of</div><div class='add'>+	  the buffer with ETM ignore packets upon disabling.</div><div class='add'>+</div><div class='add'>+	  If unsure, say Y.</div><div class='add'>+</div><div class='add'>+config ARM64_WORKAROUND_TSB_FLUSH_FAILURE</div><div class='add'>+	bool</div><div class='add'>+</div><div class='add'>+config ARM64_ERRATUM_2054223</div><div class='add'>+	bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"</div><div class='add'>+	default y</div><div class='add'>+	select ARM64_WORKAROUND_TSB_FLUSH_FAILURE</div><div class='add'>+	help</div><div class='add'>+	  Enable workaround for ARM Cortex-A710 erratum 2054223</div><div class='add'>+</div><div class='add'>+	  Affected cores may fail to flush the trace data on a TSB instruction, when</div><div class='add'>+	  the PE is in trace prohibited state. This will cause losing a few bytes</div><div class='add'>+	  of the trace cached.</div><div class='add'>+</div><div class='add'>+	  Workaround is to issue two TSB consecutively on affected cores.</div><div class='add'>+</div><div class='add'>+	  If unsure, say Y.</div><div class='add'>+</div><div class='add'>+config ARM64_ERRATUM_2067961</div><div class='add'>+	bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"</div><div class='add'>+	default y</div><div class='add'>+	select ARM64_WORKAROUND_TSB_FLUSH_FAILURE</div><div class='add'>+	help</div><div class='add'>+	  Enable workaround for ARM Neoverse-N2 erratum 2067961</div><div class='add'>+</div><div class='add'>+	  Affected cores may fail to flush the trace data on a TSB instruction, when</div><div class='add'>+	  the PE is in trace prohibited state. This will cause losing a few bytes</div><div class='add'>+	  of the trace cached.</div><div class='add'>+</div><div class='add'>+	  Workaround is to issue two TSB consecutively on affected cores.</div><div class='add'>+</div><div class='add'>+	  If unsure, say Y.</div><div class='add'>+</div><div class='add'>+config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE</div><div class='add'>+	bool</div><div class='add'>+</div><div class='add'>+config ARM64_ERRATUM_2253138</div><div class='add'>+	bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"</div><div class='add'>+	depends on CORESIGHT_TRBE</div><div class='add'>+	default y</div><div class='add'>+	select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE</div><div class='add'>+	help</div><div class='add'>+	  This option adds the workaround for ARM Neoverse-N2 erratum 2253138.</div><div class='add'>+</div><div class='add'>+	  Affected Neoverse-N2 cores might write to an out-of-range address, not reserved</div><div class='add'>+	  for TRBE. Under some conditions, the TRBE might generate a write to the next</div><div class='add'>+	  virtually addressed page following the last page of the TRBE address space</div><div class='add'>+	  (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.</div><div class='add'>+</div><div class='add'>+	  Work around this in the driver by always making sure that there is a</div><div class='add'>+	  page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.</div><div class='add'>+</div><div class='add'>+	  If unsure, say Y.</div><div class='add'>+</div><div class='add'>+config ARM64_ERRATUM_2224489</div><div class='add'>+	bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"</div><div class='add'>+	depends on CORESIGHT_TRBE</div><div class='add'>+	default y</div><div class='add'>+	select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE</div><div class='add'>+	help</div><div class='add'>+	  This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.</div><div class='add'>+</div><div class='add'>+	  Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved</div><div class='add'>+	  for TRBE. Under some conditions, the TRBE might generate a write to the next</div><div class='add'>+	  virtually addressed page following the last page of the TRBE address space</div><div class='add'>+	  (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.</div><div class='add'>+</div><div class='add'>+	  Work around this in the driver by always making sure that there is a</div><div class='add'>+	  page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.</div><div class='add'>+</div><div class='add'>+	  If unsure, say Y.</div><div class='add'>+</div><div class='add'>+config ARM64_ERRATUM_2441009</div><div class='add'>+	bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)"</div><div class='add'>+	select ARM64_WORKAROUND_REPEAT_TLBI</div><div class='add'>+	help</div><div class='add'>+	  This option adds a workaround for ARM Cortex-A510 erratum #2441009.</div><div class='add'>+</div><div class='add'>+	  Under very rare circumstances, affected Cortex-A510 CPUs</div><div class='add'>+	  may not handle a race between a break-before-make sequence on one</div><div class='add'>+	  CPU, and another CPU accessing the same page. This could allow a</div><div class='add'>+	  store to a page that has been unmapped.</div><div class='add'>+</div><div class='add'>+	  Work around this by adding the affected CPUs to the list that needs</div><div class='add'>+	  TLB sequences to be done twice.</div><div class='add'>+</div><div class='add'>+	  If unsure, say N.</div><div class='add'>+</div><div class='add'>+config ARM64_ERRATUM_2064142</div><div class='add'>+	bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"</div><div class='add'>+	depends on CORESIGHT_TRBE</div><div class='add'>+	default y</div><div class='add'>+	help</div><div class='add'>+	  This option adds the workaround for ARM Cortex-A510 erratum 2064142.</div><div class='add'>+</div><div class='add'>+	  Affected Cortex-A510 core might fail to write into system registers after the</div><div class='add'>+	  TRBE has been disabled. Under some conditions after the TRBE has been disabled</div><div class='add'>+	  writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1,</div><div class='add'>+	  and TRBTRG_EL1 will be ignored and will not be effected.</div><div class='add'>+</div><div class='add'>+	  Work around this in the driver by executing TSB CSYNC and DSB after collection</div><div class='add'>+	  is stopped and before performing a system register write to one of the affected</div><div class='add'>+	  registers.</div><div class='add'>+</div><div class='add'>+	  If unsure, say Y.</div><div class='add'>+</div><div class='add'>+config ARM64_ERRATUM_2038923</div><div class='add'>+	bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"</div><div class='add'>+	depends on CORESIGHT_TRBE</div><div class='add'>+	default y</div><div class='add'>+	help</div><div class='add'>+	  This option adds the workaround for ARM Cortex-A510 erratum 2038923.</div><div class='add'>+</div><div class='add'>+	  Affected Cortex-A510 core might cause an inconsistent view on whether trace is</div><div class='add'>+	  prohibited within the CPU. As a result, the trace buffer or trace buffer state</div><div class='add'>+	  might be corrupted. This happens after TRBE buffer has been enabled by setting</div><div class='add'>+	  TRBLIMITR_EL1.E, followed by just a single context synchronization event before</div><div class='add'>+	  execution changes from a context, in which trace is prohibited to one where it</div><div class='add'>+	  isn't, or vice versa. In these mentioned conditions, the view of whether trace</div><div class='add'>+	  is prohibited is inconsistent between parts of the CPU, and the trace buffer or</div><div class='add'>+	  the trace buffer state might be corrupted.</div><div class='add'>+</div><div class='add'>+	  Work around this in the driver by preventing an inconsistent view of whether the</div><div class='add'>+	  trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a</div><div class='add'>+	  change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or</div><div class='add'>+	  two ISB instructions if no ERET is to take place.</div><div class='add'>+</div><div class='add'>+	  If unsure, say Y.</div><div class='add'>+</div><div class='add'>+config ARM64_ERRATUM_1902691</div><div class='add'>+	bool "Cortex-A510: 1902691: workaround TRBE trace corruption"</div><div class='add'>+	depends on CORESIGHT_TRBE</div><div class='add'>+	default y</div><div class='add'>+	help</div><div class='add'>+	  This option adds the workaround for ARM Cortex-A510 erratum 1902691.</div><div class='add'>+</div><div class='add'>+	  Affected Cortex-A510 core might cause trace data corruption, when being written</div><div class='add'>+	  into the memory. Effectively TRBE is broken and hence cannot be used to capture</div><div class='add'>+	  trace data.</div><div class='add'>+</div><div class='add'>+	  Work around this problem in the driver by just preventing TRBE initialization on</div><div class='add'>+	  affected cpus. The firmware must have disabled the access to TRBE for the kernel</div><div class='add'>+	  on such implementations. This will cover the kernel for any firmware that doesn't</div><div class='add'>+	  do this already.</div><div class='add'>+</div><div class='add'>+	  If unsure, say Y.</div><div class='add'>+</div><div class='add'>+config ARM64_ERRATUM_2457168</div><div class='add'>+	bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"</div><div class='add'>+	depends on ARM64_AMU_EXTN</div><div class='add'>+	default y</div><div class='add'>+	help</div><div class='add'>+	  This option adds the workaround for ARM Cortex-A510 erratum 2457168.</div><div class='add'>+</div><div class='add'>+	  The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate</div><div class='add'>+	  as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments</div><div class='add'>+	  incorrectly giving a significantly higher output value.</div><div class='add'>+</div><div class='add'>+	  Work around this problem by returning 0 when reading the affected counter in</div><div class='add'>+	  key locations that results in disabling all users of this counter. This effect</div><div class='add'>+	  is the same to firmware disabling affected counters.</div><div class='add'>+</div><div class='add'>+	  If unsure, say Y.</div><div class='add'>+</div><div class='add'>+config ARM64_ERRATUM_2645198</div><div class='add'>+	bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption"</div><div class='add'>+	default y</div><div class='add'>+	help</div><div class='add'>+	  This option adds the workaround for ARM Cortex-A715 erratum 2645198.</div><div class='add'>+</div><div class='add'>+	  If a Cortex-A715 cpu sees a page mapping permissions change from executable</div><div class='add'>+	  to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the</div><div class='add'>+	  next instruction abort caused by permission fault.</div><div class='add'>+</div><div class='add'>+	  Only user-space does executable to non-executable permission transition via</div><div class='add'>+	  mprotect() system call. Workaround the problem by doing a break-before-make</div><div class='add'>+	  TLB invalidation, for all changes to executable user space mappings.</div><div class='add'>+</div><div class='add'>+	  If unsure, say Y.</div><div class='add'>+</div><div class='add'>+config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD</div><div class='add'>+	bool</div><div class='add'>+</div><div class='add'>+config ARM64_ERRATUM_2966298</div><div class='add'>+	bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load"</div><div class='add'>+	select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD</div><div class='add'>+	default y</div><div class='add'>+	help</div><div class='add'>+	  This option adds the workaround for ARM Cortex-A520 erratum 2966298.</div><div class='add'>+</div><div class='add'>+	  On an affected Cortex-A520 core, a speculatively executed unprivileged</div><div class='add'>+	  load might leak data from a privileged level via a cache side channel.</div><div class='add'>+</div><div class='add'>+	  Work around this problem by executing a TLBI before returning to EL0.</div><div class='add'>+</div><div class='add'>+	  If unsure, say Y.</div><div class='add'>+</div><div class='add'>+config ARM64_ERRATUM_3117295</div><div class='add'>+	bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load"</div><div class='add'>+	select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD</div><div class='add'>+	default y</div><div class='add'>+	help</div><div class='add'>+	  This option adds the workaround for ARM Cortex-A510 erratum 3117295.</div><div class='add'>+</div><div class='add'>+	  On an affected Cortex-A510 core, a speculatively executed unprivileged</div><div class='add'>+	  load might leak data from a privileged level via a cache side channel.</div><div class='add'>+</div><div class='add'>+	  Work around this problem by executing a TLBI before returning to EL0.</div><div class='add'>+</div><div class='add'>+	  If unsure, say Y.</div><div class='add'>+</div><div class='add'>+config ARM64_ERRATUM_3194386</div><div class='add'>+	bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing"</div><div class='add'>+	default y</div><div class='add'>+	help</div><div class='add'>+	  This option adds the workaround for the following errata:</div><div class='add'>+</div><div class='add'>+	  * ARM Cortex-A76 erratum 3324349</div><div class='add'>+	  * ARM Cortex-A77 erratum 3324348</div><div class='add'>+	  * ARM Cortex-A78 erratum 3324344</div><div class='add'>+	  * ARM Cortex-A78C erratum 3324346</div><div class='add'>+	  * ARM Cortex-A78C erratum 3324347</div><div class='add'>+	  * ARM Cortex-A710 erratam 3324338</div><div class='add'>+	  * ARM Cortex-A715 errartum 3456084</div><div class='add'>+	  * ARM Cortex-A720 erratum 3456091</div><div class='add'>+	  * ARM Cortex-A725 erratum 3456106</div><div class='add'>+	  * ARM Cortex-X1 erratum 3324344</div><div class='add'>+	  * ARM Cortex-X1C erratum 3324346</div><div class='add'>+	  * ARM Cortex-X2 erratum 3324338</div><div class='add'>+	  * ARM Cortex-X3 erratum 3324335</div><div class='add'>+	  * ARM Cortex-X4 erratum 3194386</div><div class='add'>+	  * ARM Cortex-X925 erratum 3324334</div><div class='add'>+	  * ARM Neoverse-N1 erratum 3324349</div><div class='add'>+	  * ARM Neoverse N2 erratum 3324339</div><div class='add'>+	  * ARM Neoverse-N3 erratum 3456111</div><div class='add'>+	  * ARM Neoverse-V1 erratum 3324341</div><div class='add'>+	  * ARM Neoverse V2 erratum 3324336</div><div class='add'>+	  * ARM Neoverse-V3 erratum 3312417</div><div class='add'>+	  * ARM Neoverse-V3AE erratum 3312417</div><div class='add'>+</div><div class='add'>+	  On affected cores "MSR SSBS, #0" instructions may not affect</div><div class='add'>+	  subsequent speculative instructions, which may permit unexepected</div><div class='add'>+	  speculative store bypassing.</div><div class='add'>+</div><div class='add'>+	  Work around this problem by placing a Speculation Barrier (SB) or</div><div class='add'>+	  Instruction Synchronization Barrier (ISB) after kernel changes to</div><div class='add'>+	  SSBS. The presence of the SSBS special-purpose register is hidden</div><div class='add'>+	  from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such that userspace</div><div class='add'>+	  will use the PR_SPEC_STORE_BYPASS prctl to change SSBS.</div><div class='add'>+</div><div class='ctx'> 	  If unsure, say Y.</div><div class='ctx'> </div><div class='ctx'> config CAVIUM_ERRATUM_22375</div><div class='hunk'>@@ -646,13 +1182,17 @@ config CAVIUM_ERRATUM_23144</div><div class='ctx'> 	  If unsure, say Y.</div><div class='ctx'> </div><div class='ctx'> config CAVIUM_ERRATUM_23154</div><div class='del'>-	bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"</div><div class='add'>+	bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation"</div><div class='ctx'> 	default y</div><div class='ctx'> 	help</div><div class='del'>-	  The gicv3 of ThunderX requires a modified version for</div><div class='add'>+	  The ThunderX GICv3 implementation requires a modified version for</div><div class='ctx'> 	  reading the IAR status to ensure data synchronization</div><div class='ctx'> 	  (access to icc_iar1_el1 is not sync'ed before and after).</div><div class='ctx'> </div><div class='add'>+	  It also suffers from erratum 38545 (also present on Marvell's</div><div class='add'>+	  OcteonTX and OcteonTX2), resulting in deactivated interrupts being</div><div class='add'>+	  spuriously presented to the CPU interface.</div><div class='add'>+</div><div class='ctx'> 	  If unsure, say Y.</div><div class='ctx'> </div><div class='ctx'> config CAVIUM_ERRATUM_27456</div><div class='hunk'>@@ -694,6 +1234,46 @@ config CAVIUM_TX2_ERRATUM_219</div><div class='ctx'> </div><div class='ctx'> 	  If unsure, say Y.</div><div class='ctx'> </div><div class='add'>+config FUJITSU_ERRATUM_010001</div><div class='add'>+	bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"</div><div class='add'>+	default y</div><div class='add'>+	help</div><div class='add'>+	  This option adds a workaround for Fujitsu-A64FX erratum E#010001.</div><div class='add'>+	  On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory</div><div class='add'>+	  accesses may cause undefined fault (Data abort, DFSC=0b111111).</div><div class='add'>+	  This fault occurs under a specific hardware condition when a</div><div class='add'>+	  load/store instruction performs an address translation using:</div><div class='add'>+	  case-1  TTBR0_EL1 with TCR_EL1.NFD0 == 1.</div><div class='add'>+	  case-2  TTBR0_EL2 with TCR_EL2.NFD0 == 1.</div><div class='add'>+	  case-3  TTBR1_EL1 with TCR_EL1.NFD1 == 1.</div><div class='add'>+	  case-4  TTBR1_EL2 with TCR_EL2.NFD1 == 1.</div><div class='add'>+</div><div class='add'>+	  The workaround is to ensure these bits are clear in TCR_ELx.</div><div class='add'>+	  The workaround only affects the Fujitsu-A64FX.</div><div class='add'>+</div><div class='add'>+	  If unsure, say Y.</div><div class='add'>+</div><div class='add'>+config HISILICON_ERRATUM_161600802</div><div class='add'>+	bool "Hip07 161600802: Erroneous redistributor VLPI base"</div><div class='add'>+	default y</div><div class='add'>+	help</div><div class='add'>+	  The HiSilicon Hip07 SoC uses the wrong redistributor base</div><div class='add'>+	  when issued ITS commands such as VMOVP and VMAPP, and requires</div><div class='add'>+	  a 128kB offset to be applied to the target address in this commands.</div><div class='add'>+</div><div class='add'>+	  If unsure, say Y.</div><div class='add'>+</div><div class='add'>+config HISILICON_ERRATUM_162100801</div><div class='add'>+	bool "Hip09 162100801 erratum support"</div><div class='add'>+	default y</div><div class='add'>+	help</div><div class='add'>+	  When enabling GICv4.1 in hip09, VMAPP will fail to clear some caches</div><div class='add'>+	  during unmapping operation, which will cause some vSGIs lost.</div><div class='add'>+	  To fix the issue, invalidate related vPE cache through GICR_INVALLR</div><div class='add'>+	  after VMOVP.</div><div class='add'>+</div><div class='add'>+	  If unsure, say Y.</div><div class='add'>+</div><div class='ctx'> config QCOM_FALKOR_ERRATUM_1003</div><div class='ctx'> 	bool "Falkor E1003: Incorrect translation due to ASID change"</div><div class='ctx'> 	default y</div><div class='hunk'>@@ -705,9 +1285,6 @@ config QCOM_FALKOR_ERRATUM_1003</div><div class='ctx'> 	  is unchanged. Work around the erratum by invalidating the walk cache</div><div class='ctx'> 	  entries for the trampoline before entering the kernel proper.</div><div class='ctx'> </div><div class='del'>-config ARM64_WORKAROUND_REPEAT_TLBI</div><div class='del'>-	bool</div><div class='del'>-</div><div class='ctx'> config QCOM_FALKOR_ERRATUM_1009</div><div class='ctx'> 	bool "Falkor E1009: Prematurely complete a DSB after a TLBI"</div><div class='ctx'> 	default y</div><div class='hunk'>@@ -729,56 +1306,55 @@ config QCOM_QDF2400_ERRATUM_0065</div><div class='ctx'> </div><div class='ctx'> 	  If unsure, say Y.</div><div class='ctx'> </div><div class='del'>-config SOCIONEXT_SYNQUACER_PREITS</div><div class='del'>-	bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"</div><div class='add'>+config QCOM_FALKOR_ERRATUM_E1041</div><div class='add'>+	bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"</div><div class='ctx'> 	default y</div><div class='ctx'> 	help</div><div class='del'>-	  Socionext Synquacer SoCs implement a separate h/w block to generate</div><div class='del'>-	  MSI doorbell writes with non-zero values for the device ID.</div><div class='add'>+	  Falkor CPU may speculatively fetch instructions from an improper</div><div class='add'>+	  memory location when MMU translation is changed from SCTLR_ELn[M]=1</div><div class='add'>+	  to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.</div><div class='ctx'> </div><div class='ctx'> 	  If unsure, say Y.</div><div class='ctx'> </div><div class='del'>-config HISILICON_ERRATUM_161600802</div><div class='del'>-	bool "Hip07 161600802: Erroneous redistributor VLPI base"</div><div class='add'>+config NVIDIA_CARMEL_CNP_ERRATUM</div><div class='add'>+	bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores"</div><div class='ctx'> 	default y</div><div class='ctx'> 	help</div><div class='del'>-	  The HiSilicon Hip07 SoC uses the wrong redistributor base</div><div class='del'>-	  when issued ITS commands such as VMOVP and VMAPP, and requires</div><div class='del'>-	  a 128kB offset to be applied to the target address in this commands.</div><div class='add'>+	  If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not</div><div class='add'>+	  invalidate shared TLB entries installed by a different core, as it would</div><div class='add'>+	  on standard ARM cores.</div><div class='ctx'> </div><div class='ctx'> 	  If unsure, say Y.</div><div class='ctx'> </div><div class='del'>-config QCOM_FALKOR_ERRATUM_E1041</div><div class='del'>-	bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"</div><div class='add'>+config ROCKCHIP_ERRATUM_3568002</div><div class='add'>+	bool "Rockchip 3568002: GIC600 can not access physical addresses higher than 4GB"</div><div class='ctx'> 	default y</div><div class='ctx'> 	help</div><div class='del'>-	  Falkor CPU may speculatively fetch instructions from an improper</div><div class='del'>-	  memory location when MMU translation is changed from SCTLR_ELn[M]=1</div><div class='del'>-	  to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.</div><div class='add'>+	  The Rockchip RK3566 and RK3568 GIC600 SoC integrations have AXI</div><div class='add'>+	  addressing limited to the first 32bit of physical address space.</div><div class='ctx'> </div><div class='ctx'> 	  If unsure, say Y.</div><div class='ctx'> </div><div class='del'>-config FUJITSU_ERRATUM_010001</div><div class='del'>-	bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"</div><div class='add'>+config ROCKCHIP_ERRATUM_3588001</div><div class='add'>+	bool "Rockchip 3588001: GIC600 can not support shareability attributes"</div><div class='ctx'> 	default y</div><div class='ctx'> 	help</div><div class='del'>-	  This option adds a workaround for Fujitsu-A64FX erratum E#010001.</div><div class='del'>-	  On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory</div><div class='del'>-	  accesses may cause undefined fault (Data abort, DFSC=0b111111).</div><div class='del'>-	  This fault occurs under a specific hardware condition when a</div><div class='del'>-	  load/store instruction performs an address translation using:</div><div class='del'>-	  case-1  TTBR0_EL1 with TCR_EL1.NFD0 == 1.</div><div class='del'>-	  case-2  TTBR0_EL2 with TCR_EL2.NFD0 == 1.</div><div class='del'>-	  case-3  TTBR1_EL1 with TCR_EL1.NFD1 == 1.</div><div class='del'>-	  case-4  TTBR1_EL2 with TCR_EL2.NFD1 == 1.</div><div class='del'>-</div><div class='del'>-	  The workaround is to ensure these bits are clear in TCR_ELx.</div><div class='del'>-	  The workaround only affects the Fujitsu-A64FX.</div><div class='add'>+	  The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite.</div><div class='add'>+	  This means, that its sharability feature may not be used, even though it</div><div class='add'>+	  is supported by the IP itself.</div><div class='ctx'> </div><div class='ctx'> 	  If unsure, say Y.</div><div class='ctx'> </div><div class='del'>-endmenu</div><div class='add'>+config SOCIONEXT_SYNQUACER_PREITS</div><div class='add'>+	bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"</div><div class='add'>+	default y</div><div class='add'>+	help</div><div class='add'>+	  Socionext Synquacer SoCs implement a separate h/w block to generate</div><div class='add'>+	  MSI doorbell writes with non-zero values for the device ID.</div><div class='add'>+</div><div class='add'>+	  If unsure, say Y.</div><div class='ctx'> </div><div class='add'>+endmenu # "ARM errata workarounds via the alternatives framework"</div><div class='ctx'> </div><div class='ctx'> choice</div><div class='ctx'> 	prompt "Page size"</div><div class='hunk'>@@ -788,11 +1364,13 @@ choice</div><div class='ctx'> </div><div class='ctx'> config ARM64_4K_PAGES</div><div class='ctx'> 	bool "4KB"</div><div class='add'>+	select HAVE_PAGE_SIZE_4KB</div><div class='ctx'> 	help</div><div class='ctx'> 	  This feature enables 4KB pages support.</div><div class='ctx'> </div><div class='ctx'> config ARM64_16K_PAGES</div><div class='ctx'> 	bool "16KB"</div><div class='add'>+	select HAVE_PAGE_SIZE_16KB</div><div class='ctx'> 	help</div><div class='ctx'> 	  The system will use 16KB pages support. AArch32 emulation</div><div class='ctx'> 	  requires applications compiled with 16K (or a multiple of 16K)</div><div class='hunk'>@@ -800,6 +1378,7 @@ config ARM64_16K_PAGES</div><div class='ctx'> </div><div class='ctx'> config ARM64_64K_PAGES</div><div class='ctx'> 	bool "64KB"</div><div class='add'>+	select HAVE_PAGE_SIZE_64KB</div><div class='ctx'> 	help</div><div class='ctx'> 	  This feature enables 64KB pages support (4KB by default)</div><div class='ctx'> 	  allowing only two levels of page tables and faster TLB</div><div class='hunk'>@@ -810,9 +1389,7 @@ endchoice</div><div class='ctx'> </div><div class='ctx'> choice</div><div class='ctx'> 	prompt "Virtual address space size"</div><div class='del'>-	default ARM64_VA_BITS_39 if ARM64_4K_PAGES</div><div class='del'>-	default ARM64_VA_BITS_47 if ARM64_16K_PAGES</div><div class='del'>-	default ARM64_VA_BITS_42 if ARM64_64K_PAGES</div><div class='add'>+	default ARM64_VA_BITS_52</div><div class='ctx'> 	help</div><div class='ctx'> 	  Allows choosing one of multiple possible virtual address</div><div class='ctx'> 	  space sizes. The level of translation table is determined by</div><div class='hunk'>@@ -820,26 +1397,25 @@ choice</div><div class='ctx'> </div><div class='ctx'> config ARM64_VA_BITS_36</div><div class='ctx'> 	bool "36-bit" if EXPERT</div><div class='del'>-	depends on ARM64_16K_PAGES</div><div class='add'>+	depends on PAGE_SIZE_16KB</div><div class='ctx'> </div><div class='ctx'> config ARM64_VA_BITS_39</div><div class='ctx'> 	bool "39-bit"</div><div class='del'>-	depends on ARM64_4K_PAGES</div><div class='add'>+	depends on PAGE_SIZE_4KB</div><div class='ctx'> </div><div class='ctx'> config ARM64_VA_BITS_42</div><div class='ctx'> 	bool "42-bit"</div><div class='del'>-	depends on ARM64_64K_PAGES</div><div class='add'>+	depends on PAGE_SIZE_64KB</div><div class='ctx'> </div><div class='ctx'> config ARM64_VA_BITS_47</div><div class='ctx'> 	bool "47-bit"</div><div class='del'>-	depends on ARM64_16K_PAGES</div><div class='add'>+	depends on PAGE_SIZE_16KB</div><div class='ctx'> </div><div class='ctx'> config ARM64_VA_BITS_48</div><div class='ctx'> 	bool "48-bit"</div><div class='ctx'> </div><div class='ctx'> config ARM64_VA_BITS_52</div><div class='ctx'> 	bool "52-bit"</div><div class='del'>-	depends on ARM64_64K_PAGES &amp;&amp; (ARM64_PAN || !ARM64_SW_TTBR0_PAN)</div><div class='ctx'> 	help</div><div class='ctx'> 	  Enable 52-bit virtual addressing for userspace when explicitly</div><div class='ctx'> 	  requested via a hint to mmap(). The kernel will also use 52-bit</div><div class='hunk'>@@ -886,11 +1462,11 @@ choice</div><div class='ctx'> </div><div class='ctx'> config ARM64_PA_BITS_48</div><div class='ctx'> 	bool "48-bit"</div><div class='add'>+	depends on ARM64_64K_PAGES || !ARM64_VA_BITS_52</div><div class='ctx'> </div><div class='ctx'> config ARM64_PA_BITS_52</div><div class='del'>-	bool "52-bit (ARMv8.2)"</div><div class='del'>-	depends on ARM64_64K_PAGES</div><div class='del'>-	depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN</div><div class='add'>+	bool "52-bit"</div><div class='add'>+	depends on ARM64_64K_PAGES || ARM64_VA_BITS_52</div><div class='ctx'> 	help</div><div class='ctx'> 	  Enable support for a 52-bit physical address space, introduced as</div><div class='ctx'> 	  part of the ARMv8.2-LPA extension.</div><div class='hunk'>@@ -906,6 +1482,10 @@ config ARM64_PA_BITS</div><div class='ctx'> 	default 48 if ARM64_PA_BITS_48</div><div class='ctx'> 	default 52 if ARM64_PA_BITS_52</div><div class='ctx'> </div><div class='add'>+config ARM64_LPA2</div><div class='add'>+	def_bool y</div><div class='add'>+	depends on ARM64_PA_BITS_52 &amp;&amp; !ARM64_64K_PAGES</div><div class='add'>+</div><div class='ctx'> choice</div><div class='ctx'> 	prompt "Endianness"</div><div class='ctx'> 	default CPU_LITTLE_ENDIAN</div><div class='hunk'>@@ -915,8 +1495,9 @@ choice</div><div class='ctx'> 	  that is selected here.</div><div class='ctx'> </div><div class='ctx'> config CPU_BIG_ENDIAN</div><div class='del'>-       bool "Build big-endian kernel"</div><div class='del'>-       help</div><div class='add'>+	bool "Build big-endian kernel"</div><div class='add'>+	depends on BROKEN</div><div class='add'>+	help</div><div class='ctx'> 	  Say Y if you plan on running a kernel with a big-endian userspace.</div><div class='ctx'> </div><div class='ctx'> config CPU_LITTLE_ENDIAN</div><div class='hunk'>@@ -927,24 +1508,10 @@ config CPU_LITTLE_ENDIAN</div><div class='ctx'> </div><div class='ctx'> endchoice</div><div class='ctx'> </div><div class='del'>-config SCHED_MC</div><div class='del'>-	bool "Multi-core scheduler support"</div><div class='del'>-	help</div><div class='del'>-	  Multi-core scheduler support improves the CPU scheduler's decision</div><div class='del'>-	  making when dealing with multi-core CPU chips at a cost of slightly</div><div class='del'>-	  increased overhead in some places. If unsure say N here.</div><div class='del'>-</div><div class='del'>-config SCHED_SMT</div><div class='del'>-	bool "SMT scheduler support"</div><div class='del'>-	help</div><div class='del'>-	  Improves the CPU scheduler's decision making when dealing with</div><div class='del'>-	  MultiThreading at a cost of slightly increased overhead in some</div><div class='del'>-	  places. If unsure say N here.</div><div class='del'>-</div><div class='ctx'> config NR_CPUS</div><div class='ctx'> 	int "Maximum number of CPUs (2-4096)"</div><div class='ctx'> 	range 2 4096</div><div class='del'>-	default "256"</div><div class='add'>+	default "512"</div><div class='ctx'> </div><div class='ctx'> config HOTPLUG_CPU</div><div class='ctx'> 	bool "Support for hot-pluggable CPUs"</div><div class='hunk'>@@ -956,8 +1523,12 @@ config HOTPLUG_CPU</div><div class='ctx'> # Common NUMA Features</div><div class='ctx'> config NUMA</div><div class='ctx'> 	bool "NUMA Memory Allocation and Scheduler Support"</div><div class='del'>-	select ACPI_NUMA if ACPI</div><div class='add'>+	select GENERIC_ARCH_NUMA</div><div class='ctx'> 	select OF_NUMA</div><div class='add'>+	select HAVE_SETUP_PER_CPU_AREA</div><div class='add'>+	select NEED_PER_CPU_EMBED_FIRST_CHUNK</div><div class='add'>+	select NEED_PER_CPU_PAGE_FIRST_CHUNK</div><div class='add'>+	select USE_PERCPU_NUMA_NODE_ID</div><div class='ctx'> 	help</div><div class='ctx'> 	  Enable NUMA (Non-Uniform Memory Access) support.</div><div class='ctx'> </div><div class='hunk'>@@ -968,75 +1539,25 @@ config NUMA</div><div class='ctx'> config NODES_SHIFT</div><div class='ctx'> 	int "Maximum NUMA Nodes (as a power of 2)"</div><div class='ctx'> 	range 1 10</div><div class='del'>-	default "2"</div><div class='del'>-	depends on NEED_MULTIPLE_NODES</div><div class='add'>+	default "4"</div><div class='add'>+	depends on NUMA</div><div class='ctx'> 	help</div><div class='ctx'> 	  Specify the maximum number of NUMA Nodes available on the target</div><div class='ctx'> 	  system.  Increases memory reserved to accommodate various tables.</div><div class='ctx'> </div><div class='del'>-config USE_PERCPU_NUMA_NODE_ID</div><div class='del'>-	def_bool y</div><div class='del'>-	depends on NUMA</div><div class='del'>-</div><div class='del'>-config HAVE_SETUP_PER_CPU_AREA</div><div class='del'>-	def_bool y</div><div class='del'>-	depends on NUMA</div><div class='del'>-</div><div class='del'>-config NEED_PER_CPU_EMBED_FIRST_CHUNK</div><div class='del'>-	def_bool y</div><div class='del'>-	depends on NUMA</div><div class='del'>-</div><div class='del'>-config HOLES_IN_ZONE</div><div class='del'>-	def_bool y</div><div class='del'>-</div><div class='ctx'> source "kernel/Kconfig.hz"</div><div class='ctx'> </div><div class='del'>-config ARCH_SUPPORTS_DEBUG_PAGEALLOC</div><div class='del'>-	def_bool y</div><div class='del'>-</div><div class='ctx'> config ARCH_SPARSEMEM_ENABLE</div><div class='ctx'> 	def_bool y</div><div class='ctx'> 	select SPARSEMEM_VMEMMAP_ENABLE</div><div class='ctx'> </div><div class='del'>-config ARCH_SPARSEMEM_DEFAULT</div><div class='del'>-	def_bool ARCH_SPARSEMEM_ENABLE</div><div class='del'>-</div><div class='del'>-config ARCH_SELECT_MEMORY_MODEL</div><div class='del'>-	def_bool ARCH_SPARSEMEM_ENABLE</div><div class='del'>-</div><div class='del'>-config ARCH_FLATMEM_ENABLE</div><div class='del'>-	def_bool !NUMA</div><div class='del'>-</div><div class='del'>-config HAVE_ARCH_PFN_VALID</div><div class='del'>-	def_bool y</div><div class='del'>-</div><div class='ctx'> config HW_PERF_EVENTS</div><div class='ctx'> 	def_bool y</div><div class='ctx'> 	depends on ARM_PMU</div><div class='ctx'> </div><div class='del'>-config SYS_SUPPORTS_HUGETLBFS</div><div class='del'>-	def_bool y</div><div class='del'>-</div><div class='del'>-config ARCH_WANT_HUGE_PMD_SHARE</div><div class='del'>-</div><div class='del'>-config ARCH_HAS_CACHE_LINE_SIZE</div><div class='del'>-	def_bool y</div><div class='del'>-</div><div class='del'>-config ARCH_ENABLE_SPLIT_PMD_PTLOCK</div><div class='del'>-	def_bool y if PGTABLE_LEVELS &gt; 2</div><div class='del'>-</div><div class='del'>-config SECCOMP</div><div class='del'>-	bool "Enable seccomp to safely compute untrusted bytecode"</div><div class='del'>-	---help---</div><div class='del'>-	  This kernel feature is useful for number crunching applications</div><div class='del'>-	  that may need to compute untrusted bytecode during their</div><div class='del'>-	  execution. By using pipes or other transports made available to</div><div class='del'>-	  the process as file descriptors supporting the read/write</div><div class='del'>-	  syscalls, it's possible to isolate those applications in</div><div class='del'>-	  their own address space using seccomp. Once seccomp is</div><div class='del'>-	  enabled via prctl(PR_SET_SECCOMP), it cannot be disabled</div><div class='del'>-	  and the task is only allowed to execute a few safe syscalls</div><div class='del'>-	  defined by each seccomp mode.</div><div class='add'>+# Supported by clang &gt;= 7.0 or GCC &gt;= 12.0.0</div><div class='add'>+config CC_HAVE_SHADOW_CALL_STACK</div><div class='add'>+	def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)</div><div class='ctx'> </div><div class='ctx'> config PARAVIRT</div><div class='ctx'> 	bool "Enable paravirtualization code"</div><div class='hunk'>@@ -1056,59 +1577,41 @@ config PARAVIRT_TIME_ACCOUNTING</div><div class='ctx'> </div><div class='ctx'> 	  If in doubt, say N here.</div><div class='ctx'> </div><div class='del'>-config KEXEC</div><div class='del'>-	depends on PM_SLEEP_SMP</div><div class='del'>-	select KEXEC_CORE</div><div class='del'>-	bool "kexec system call"</div><div class='del'>-	---help---</div><div class='del'>-	  kexec is a system call that implements the ability to shutdown your</div><div class='del'>-	  current kernel, and to start another kernel.  It is like a reboot</div><div class='del'>-	  but it is independent of the system firmware.   And like a reboot</div><div class='del'>-	  you can start any kernel with it, not just Linux.</div><div class='del'>-</div><div class='del'>-config KEXEC_FILE</div><div class='del'>-	bool "kexec file based system call"</div><div class='del'>-	select KEXEC_CORE</div><div class='del'>-	help</div><div class='del'>-	  This is new version of kexec system call. This system call is</div><div class='del'>-	  file based and takes file descriptors as system call argument</div><div class='del'>-	  for kernel and initramfs as opposed to list of segments as</div><div class='del'>-	  accepted by previous system call.</div><div class='del'>-</div><div class='del'>-config KEXEC_SIG</div><div class='del'>-	bool "Verify kernel signature during kexec_file_load() syscall"</div><div class='add'>+config ARCH_SUPPORTS_KEXEC</div><div class='add'>+	def_bool PM_SLEEP_SMP</div><div class='add'>+</div><div class='add'>+config ARCH_SUPPORTS_KEXEC_FILE</div><div class='add'>+	def_bool y</div><div class='add'>+</div><div class='add'>+config ARCH_SELECTS_KEXEC_FILE</div><div class='add'>+	def_bool y</div><div class='ctx'> 	depends on KEXEC_FILE</div><div class='del'>-	help</div><div class='del'>-	  Select this option to verify a signature with loaded kernel</div><div class='del'>-	  image. If configured, any attempt of loading a image without</div><div class='del'>-	  valid signature will fail.</div><div class='add'>+	select HAVE_IMA_KEXEC if IMA</div><div class='ctx'> </div><div class='del'>-	  In addition to that option, you need to enable signature</div><div class='del'>-	  verification for the corresponding kernel image type being</div><div class='del'>-	  loaded in order for this to work.</div><div class='add'>+config ARCH_SUPPORTS_KEXEC_SIG</div><div class='add'>+	def_bool y</div><div class='ctx'> </div><div class='del'>-config KEXEC_IMAGE_VERIFY_SIG</div><div class='del'>-	bool "Enable Image signature verification support"</div><div class='del'>-	default y</div><div class='del'>-	depends on KEXEC_SIG</div><div class='del'>-	depends on EFI &amp;&amp; SIGNED_PE_FILE_VERIFICATION</div><div class='del'>-	help</div><div class='del'>-	  Enable Image signature verification support.</div><div class='add'>+config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG</div><div class='add'>+	def_bool y</div><div class='ctx'> </div><div class='del'>-comment "Support for PE file signature verification disabled"</div><div class='del'>-	depends on KEXEC_SIG</div><div class='del'>-	depends on !EFI || !SIGNED_PE_FILE_VERIFICATION</div><div class='add'>+config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG</div><div class='add'>+	def_bool y</div><div class='ctx'> </div><div class='del'>-config CRASH_DUMP</div><div class='del'>-	bool "Build kdump crash kernel"</div><div class='del'>-	help</div><div class='del'>-	  Generate crash dump after being started by kexec. This should</div><div class='del'>-	  be normally only set in special crash dump kernels which are</div><div class='del'>-	  loaded in the main kernel with kexec-tools into a specially</div><div class='del'>-	  reserved region and then later executed after a crash by</div><div class='del'>-	  kdump/kexec.</div><div class='add'>+config ARCH_SUPPORTS_KEXEC_HANDOVER</div><div class='add'>+	def_bool y</div><div class='ctx'> </div><div class='del'>-	  For more details see Documentation/admin-guide/kdump/kdump.rst</div><div class='add'>+config ARCH_SUPPORTS_CRASH_DUMP</div><div class='add'>+	def_bool y</div><div class='add'>+</div><div class='add'>+config ARCH_DEFAULT_CRASH_DUMP</div><div class='add'>+	def_bool y</div><div class='add'>+</div><div class='add'>+config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION</div><div class='add'>+	def_bool CRASH_RESERVE</div><div class='add'>+</div><div class='add'>+config TRANS_TABLE</div><div class='add'>+	def_bool y</div><div class='add'>+	depends on HIBERNATION || KEXEC_CORE</div><div class='ctx'> </div><div class='ctx'> config XEN_DOM0</div><div class='ctx'> 	def_bool y</div><div class='hunk'>@@ -1122,31 +1625,39 @@ config XEN</div><div class='ctx'> 	help</div><div class='ctx'> 	  Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.</div><div class='ctx'> </div><div class='del'>-config FORCE_MAX_ZONEORDER</div><div class='add'>+# include/linux/mmzone.h requires the following to be true:</div><div class='add'>+#</div><div class='add'>+#   MAX_PAGE_ORDER + PAGE_SHIFT &lt;= SECTION_SIZE_BITS</div><div class='add'>+#</div><div class='add'>+# so the maximum value of MAX_PAGE_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT:</div><div class='add'>+#</div><div class='add'>+#     | SECTION_SIZE_BITS |  PAGE_SHIFT  |  max MAX_PAGE_ORDER  |  default MAX_PAGE_ORDER |</div><div class='add'>+# ----+-------------------+--------------+----------------------+-------------------------+</div><div class='add'>+# 4K  |       27          |      12      |       15             |         10              |</div><div class='add'>+# 16K |       27          |      14      |       13             |         11              |</div><div class='add'>+# 64K |       29          |      16      |       13             |         13              |</div><div class='add'>+config ARCH_FORCE_MAX_ORDER</div><div class='ctx'> 	int</div><div class='del'>-	default "14" if (ARM64_64K_PAGES &amp;&amp; TRANSPARENT_HUGEPAGE)</div><div class='del'>-	default "12" if (ARM64_16K_PAGES &amp;&amp; TRANSPARENT_HUGEPAGE)</div><div class='del'>-	default "11"</div><div class='add'>+	default "13" if ARM64_64K_PAGES</div><div class='add'>+	default "11" if ARM64_16K_PAGES</div><div class='add'>+	default "10"</div><div class='ctx'> 	help</div><div class='del'>-	  The kernel memory allocator divides physically contiguous memory</div><div class='del'>-	  blocks into "zones", where each zone is a power of two number of</div><div class='del'>-	  pages.  This option selects the largest power of two that the kernel</div><div class='del'>-	  keeps in the memory allocator.  If you need to allocate very large</div><div class='del'>-	  blocks of physically contiguous memory, then you may need to</div><div class='del'>-	  increase this value.</div><div class='add'>+	  The kernel page allocator limits the size of maximal physically</div><div class='add'>+	  contiguous allocations. The limit is called MAX_PAGE_ORDER and it</div><div class='add'>+	  defines the maximal power of two of number of pages that can be</div><div class='add'>+	  allocated as a single contiguous block. This option allows</div><div class='add'>+	  overriding the default setting when ability to allocate very</div><div class='add'>+	  large blocks of physically contiguous memory is required.</div><div class='ctx'> </div><div class='del'>-	  This config option is actually maximum order plus one. For example,</div><div class='del'>-	  a value of 11 means that the largest free memory block is 2^10 pages.</div><div class='add'>+	  The maximal size of allocation cannot exceed the size of the</div><div class='add'>+	  section, so the value of MAX_PAGE_ORDER should satisfy</div><div class='ctx'> </div><div class='del'>-	  We make sure that we can allocate upto a HugePage size for each configuration.</div><div class='del'>-	  Hence we have :</div><div class='del'>-		MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 =&gt; PAGE_SHIFT - 2</div><div class='add'>+	    MAX_PAGE_ORDER + PAGE_SHIFT &lt;= SECTION_SIZE_BITS</div><div class='ctx'> </div><div class='del'>-	  However for 4K, we choose a higher default value, 11 as opposed to 10, giving us</div><div class='del'>-	  4M allocations matching the default size used by generic code.</div><div class='add'>+	  Don't change if unsure.</div><div class='ctx'> </div><div class='ctx'> config UNMAP_KERNEL_AT_EL0</div><div class='del'>-	bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT</div><div class='add'>+	bool "Unmap kernel when running in userspace (KPTI)" if EXPERT</div><div class='ctx'> 	default y</div><div class='ctx'> 	help</div><div class='ctx'> 	  Speculation attacks against some high-performance processors can</div><div class='hunk'>@@ -1157,64 +1668,19 @@ config UNMAP_KERNEL_AT_EL0</div><div class='ctx'> </div><div class='ctx'> 	  If unsure, say Y.</div><div class='ctx'> </div><div class='del'>-config HARDEN_BRANCH_PREDICTOR</div><div class='del'>-	bool "Harden the branch predictor against aliasing attacks" if EXPERT</div><div class='del'>-	default y</div><div class='del'>-	help</div><div class='del'>-	  Speculation attacks against some high-performance processors rely on</div><div class='del'>-	  being able to manipulate the branch predictor for a victim context by</div><div class='del'>-	  executing aliasing branches in the attacker context.  Such attacks</div><div class='del'>-	  can be partially mitigated against by clearing internal branch</div><div class='del'>-	  predictor state and limiting the prediction logic in some situations.</div><div class='del'>-</div><div class='del'>-	  This config option will take CPU-specific actions to harden the</div><div class='del'>-	  branch predictor against aliasing attacks and may rely on specific</div><div class='del'>-	  instruction sequences or control bits being set by the system</div><div class='del'>-	  firmware.</div><div class='del'>-</div><div class='del'>-	  If unsure, say Y.</div><div class='del'>-</div><div class='del'>-config HARDEN_EL2_VECTORS</div><div class='del'>-	bool "Harden EL2 vector mapping against system register leak" if EXPERT</div><div class='add'>+config MITIGATE_SPECTRE_BRANCH_HISTORY</div><div class='add'>+	bool "Mitigate Spectre style attacks against branch history" if EXPERT</div><div class='ctx'> 	default y</div><div class='ctx'> 	help</div><div class='ctx'> 	  Speculation attacks against some high-performance processors can</div><div class='del'>-	  be used to leak privileged information such as the vector base</div><div class='del'>-	  register, resulting in a potential defeat of the EL2 layout</div><div class='del'>-	  randomization.</div><div class='del'>-</div><div class='del'>-	  This config option will map the vectors to a fixed location,</div><div class='del'>-	  independent of the EL2 code mapping, so that revealing VBAR_EL2</div><div class='del'>-	  to an attacker does not give away any extra information. This</div><div class='del'>-	  only gets enabled on affected CPUs.</div><div class='del'>-</div><div class='del'>-	  If unsure, say Y.</div><div class='del'>-</div><div class='del'>-config ARM64_SSBD</div><div class='del'>-	bool "Speculative Store Bypass Disable" if EXPERT</div><div class='del'>-	default y</div><div class='del'>-	help</div><div class='del'>-	  This enables mitigation of the bypassing of previous stores</div><div class='del'>-	  by speculative loads.</div><div class='del'>-</div><div class='del'>-	  If unsure, say Y.</div><div class='del'>-</div><div class='del'>-config RODATA_FULL_DEFAULT_ENABLED</div><div class='del'>-	bool "Apply r/o permissions of VM areas also to their linear aliases"</div><div class='del'>-	default y</div><div class='del'>-	help</div><div class='del'>-	  Apply read-only attributes of VM areas to the linear alias of</div><div class='del'>-	  the backing pages as well. This prevents code or read-only data</div><div class='del'>-	  from being modified (inadvertently or intentionally) via another</div><div class='del'>-	  mapping of the same memory page. This additional enhancement can</div><div class='del'>-	  be turned off at runtime by passing rodata=[off|on] (and turned on</div><div class='del'>-	  with rodata=full if this option is set to 'n')</div><div class='del'>-</div><div class='del'>-	  This requires the linear region to be mapped down to pages,</div><div class='del'>-	  which may adversely affect performance in some cases.</div><div class='add'>+	  make use of branch history to influence future speculation.</div><div class='add'>+	  When taking an exception from user-space, a sequence of branches</div><div class='add'>+	  or a firmware call overwrites the branch history.</div><div class='ctx'> </div><div class='ctx'> config ARM64_SW_TTBR0_PAN</div><div class='ctx'> 	bool "Emulate Privileged Access Never using TTBR0_EL1 switching"</div><div class='add'>+	depends on !KCSAN</div><div class='add'>+	select ARM64_PAN</div><div class='ctx'> 	help</div><div class='ctx'> 	  Enabling this option prevents the kernel from accessing</div><div class='ctx'> 	  user-space memory directly by pointing TTBR0_EL1 to a reserved</div><div class='hunk'>@@ -1228,12 +1694,11 @@ config ARM64_TAGGED_ADDR_ABI</div><div class='ctx'> 	  When this option is enabled, user applications can opt in to a</div><div class='ctx'> 	  relaxed ABI via prctl() allowing tagged addresses to be passed</div><div class='ctx'> 	  to system calls as pointer arguments. For details, see</div><div class='del'>-	  Documentation/arm64/tagged-address-abi.rst.</div><div class='add'>+	  Documentation/arch/arm64/tagged-address-abi.rst.</div><div class='ctx'> </div><div class='ctx'> menuconfig COMPAT</div><div class='ctx'> 	bool "Kernel support for 32-bit EL0"</div><div class='ctx'> 	depends on ARM64_4K_PAGES || EXPERT</div><div class='del'>-	select COMPAT_BINFMT_ELF if BINFMT_ELF</div><div class='ctx'> 	select HAVE_UID16</div><div class='ctx'> 	select OLD_SIGSUSPEND3</div><div class='ctx'> 	select COMPAT_OLD_SIGACTION</div><div class='hunk'>@@ -1263,7 +1728,7 @@ config KUSER_HELPERS</div><div class='ctx'> 	  the system. This permits binaries to be run on ARMv4 through</div><div class='ctx'> 	  to ARMv8 without modification.</div><div class='ctx'> </div><div class='del'>-	  See Documentation/arm/kernel_user_helpers.rst for details.</div><div class='add'>+	  See Documentation/arch/arm/kernel_user_helpers.rst for details.</div><div class='ctx'> </div><div class='ctx'> 	  However, the fixed address nature of these helpers can be used</div><div class='ctx'> 	  by ROP (return orientated programming) authors when creating</div><div class='hunk'>@@ -1280,8 +1745,8 @@ config KUSER_HELPERS</div><div class='ctx'> </div><div class='ctx'> config COMPAT_VDSO</div><div class='ctx'> 	bool "Enable vDSO for 32-bit applications"</div><div class='del'>-	depends on !CPU_BIG_ENDIAN &amp;&amp; "$(CROSS_COMPILE_COMPAT)" != ""</div><div class='del'>-	select GENERIC_COMPAT_VDSO</div><div class='add'>+	depends on !CPU_BIG_ENDIAN</div><div class='add'>+	depends on (CC_IS_CLANG &amp;&amp; LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != ""</div><div class='ctx'> 	default y</div><div class='ctx'> 	help</div><div class='ctx'> 	  Place in the process address space of 32-bit applications an</div><div class='hunk'>@@ -1291,6 +1756,17 @@ config COMPAT_VDSO</div><div class='ctx'> 	  You must have a 32-bit build of glibc 2.22 or later for programs</div><div class='ctx'> 	  to seamlessly take advantage of this.</div><div class='ctx'> </div><div class='add'>+config THUMB2_COMPAT_VDSO</div><div class='add'>+	bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT</div><div class='add'>+	depends on COMPAT_VDSO</div><div class='add'>+	default y</div><div class='add'>+	help</div><div class='add'>+	  Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,</div><div class='add'>+	  otherwise with '-marm'.</div><div class='add'>+</div><div class='add'>+config COMPAT_ALIGNMENT_FIXUPS</div><div class='add'>+	bool "Fix up misaligned multi-word loads and stores in user space"</div><div class='add'>+</div><div class='ctx'> menuconfig ARMV8_DEPRECATED</div><div class='ctx'> 	bool "Emulate deprecated/obsolete ARMv8 instructions"</div><div class='ctx'> 	depends on SYSCTL</div><div class='hunk'>@@ -1311,6 +1787,8 @@ config SWP_EMULATION</div><div class='ctx'> 	  ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that</div><div class='ctx'> 	  they are always undefined. Say Y here to enable software</div><div class='ctx'> 	  emulation of these instructions for userspace using LDXR/STXR.</div><div class='add'>+	  This feature can be controlled at runtime with the abi.swp</div><div class='add'>+	  sysctl which is disabled by default.</div><div class='ctx'> </div><div class='ctx'> 	  In some older versions of glibc [&lt;=2.8] SWP is used during futex</div><div class='ctx'> 	  trylock() operations with the assumption that the code will not</div><div class='hunk'>@@ -1337,7 +1815,8 @@ config CP15_BARRIER_EMULATION</div><div class='ctx'> 	  Say Y here to enable software emulation of these</div><div class='ctx'> 	  instructions for AArch32 userspace code. When this option is</div><div class='ctx'> 	  enabled, CP15 barrier usage is traced which can help</div><div class='del'>-	  identify software that needs updating.</div><div class='add'>+	  identify software that needs updating. This feature can be</div><div class='add'>+	  controlled at runtime with the abi.cp15_barrier sysctl.</div><div class='ctx'> </div><div class='ctx'> 	  If unsure, say Y</div><div class='ctx'> </div><div class='hunk'>@@ -1348,7 +1827,8 @@ config SETEND_EMULATION</div><div class='ctx'> 	  AArch32 EL0, and is deprecated in ARMv8.</div><div class='ctx'> </div><div class='ctx'> 	  Say Y here to enable software emulation of the instruction</div><div class='del'>-	  for AArch32 userspace code.</div><div class='add'>+	  for AArch32 userspace code. This feature can be controlled</div><div class='add'>+	  at runtime with the abi.setend sysctl.</div><div class='ctx'> </div><div class='ctx'> 	  Note: All the cpus on the system must have mixed endian support at EL0</div><div class='ctx'> 	  for this feature to be enabled. If a new CPU - which doesn't support mixed</div><div class='hunk'>@@ -1356,9 +1836,9 @@ config SETEND_EMULATION</div><div class='ctx'> 	  be unexpected results in the applications.</div><div class='ctx'> </div><div class='ctx'> 	  If unsure, say Y</div><div class='del'>-endif</div><div class='add'>+endif # ARMV8_DEPRECATED</div><div class='ctx'> </div><div class='del'>-endif</div><div class='add'>+endif # COMPAT</div><div class='ctx'> </div><div class='ctx'> menu "ARMv8.1 architectural features"</div><div class='ctx'> </div><div class='hunk'>@@ -1383,24 +1863,22 @@ config ARM64_PAN</div><div class='ctx'> 	bool "Enable support for Privileged Access Never (PAN)"</div><div class='ctx'> 	default y</div><div class='ctx'> 	help</div><div class='del'>-	 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)</div><div class='del'>-	 prevents the kernel or hypervisor from accessing user-space (EL0)</div><div class='del'>-	 memory directly.</div><div class='add'>+	  Privileged Access Never (PAN; part of the ARMv8.1 Extensions)</div><div class='add'>+	  prevents the kernel or hypervisor from accessing user-space (EL0)</div><div class='add'>+	  memory directly.</div><div class='ctx'> </div><div class='del'>-	 Choosing this option will cause any unprotected (not using</div><div class='del'>-	 copy_to_user et al) memory access to fail with a permission fault.</div><div class='add'>+	  Choosing this option will cause any unprotected (not using</div><div class='add'>+	  copy_to_user et al) memory access to fail with a permission fault.</div><div class='ctx'> </div><div class='del'>-	 The feature is detected at runtime, and will remain as a 'nop'</div><div class='del'>-	 instruction if the cpu does not implement the feature.</div><div class='add'>+	  The feature is detected at runtime, and will remain as a 'nop'</div><div class='add'>+	  instruction if the cpu does not implement the feature.</div><div class='ctx'> </div><div class='ctx'> config ARM64_LSE_ATOMICS</div><div class='ctx'> 	bool</div><div class='ctx'> 	default ARM64_USE_LSE_ATOMICS</div><div class='del'>-	depends on $(as-instr,.arch_extension lse)</div><div class='ctx'> </div><div class='ctx'> config ARM64_USE_LSE_ATOMICS</div><div class='ctx'> 	bool "Atomic instructions"</div><div class='del'>-	depends on JUMP_LABEL</div><div class='ctx'> 	default y</div><div class='ctx'> 	help</div><div class='ctx'> 	  As part of the Large System Extensions, ARMv8.1 introduces new</div><div class='hunk'>@@ -1409,48 +1887,12 @@ config ARM64_USE_LSE_ATOMICS</div><div class='ctx'> </div><div class='ctx'> 	  Say Y here to make use of these instructions for the in-kernel</div><div class='ctx'> 	  atomic routines. This incurs a small overhead on CPUs that do</div><div class='del'>-	  not support these instructions and requires the kernel to be</div><div class='del'>-	  built with binutils &gt;= 2.25 in order for the new instructions</div><div class='del'>-	  to be used.</div><div class='del'>-</div><div class='del'>-config ARM64_VHE</div><div class='del'>-	bool "Enable support for Virtualization Host Extensions (VHE)"</div><div class='del'>-	default y</div><div class='del'>-	help</div><div class='del'>-	  Virtualization Host Extensions (VHE) allow the kernel to run</div><div class='del'>-	  directly at EL2 (instead of EL1) on processors that support</div><div class='del'>-	  it. This leads to better performance for KVM, as they reduce</div><div class='del'>-	  the cost of the world switch.</div><div class='add'>+	  not support these instructions.</div><div class='ctx'> </div><div class='del'>-	  Selecting this option allows the VHE feature to be detected</div><div class='del'>-	  at runtime, and does not affect processors that do not</div><div class='del'>-	  implement this feature.</div><div class='del'>-</div><div class='del'>-endmenu</div><div class='add'>+endmenu # "ARMv8.1 architectural features"</div><div class='ctx'> </div><div class='ctx'> menu "ARMv8.2 architectural features"</div><div class='ctx'> </div><div class='del'>-config ARM64_UAO</div><div class='del'>-	bool "Enable support for User Access Override (UAO)"</div><div class='del'>-	default y</div><div class='del'>-	help</div><div class='del'>-	  User Access Override (UAO; part of the ARMv8.2 Extensions)</div><div class='del'>-	  causes the 'unprivileged' variant of the load/store instructions to</div><div class='del'>-	  be overridden to be privileged.</div><div class='del'>-</div><div class='del'>-	  This option changes get_user() and friends to use the 'unprivileged'</div><div class='del'>-	  variant of the load/store instructions. This ensures that user-space</div><div class='del'>-	  really did have access to the supplied memory. When addr_limit is</div><div class='del'>-	  set to kernel memory the UAO bit will be set, allowing privileged</div><div class='del'>-	  access to kernel memory.</div><div class='del'>-</div><div class='del'>-	  Choosing this option will cause copy_to_user() et al to use user-space</div><div class='del'>-	  memory permissions.</div><div class='del'>-</div><div class='del'>-	  The feature is detected at runtime, the kernel will use the</div><div class='del'>-	  regular load/store instructions if the cpu does not implement the</div><div class='del'>-	  feature.</div><div class='del'>-</div><div class='ctx'> config ARM64_PMEM</div><div class='ctx'> 	bool "Enable support for persistent memory"</div><div class='ctx'> 	select ARCH_HAS_PMEM_API</div><div class='hunk'>@@ -1482,7 +1924,6 @@ config ARM64_RAS_EXTN</div><div class='ctx'> config ARM64_CNP</div><div class='ctx'> 	bool "Enable support for Common Not Private (CNP) translations"</div><div class='ctx'> 	default y</div><div class='del'>-	depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN</div><div class='ctx'> 	help</div><div class='ctx'> 	  Common Not Private (CNP) allows translation table entries to</div><div class='ctx'> 	  be shared between different PEs in the same inner shareable</div><div class='hunk'>@@ -1493,20 +1934,13 @@ config ARM64_CNP</div><div class='ctx'> 	  at runtime, and does not affect PEs that do not implement</div><div class='ctx'> 	  this feature.</div><div class='ctx'> </div><div class='del'>-endmenu</div><div class='add'>+endmenu # "ARMv8.2 architectural features"</div><div class='ctx'> </div><div class='ctx'> menu "ARMv8.3 architectural features"</div><div class='ctx'> </div><div class='ctx'> config ARM64_PTR_AUTH</div><div class='ctx'> 	bool "Enable support for pointer authentication"</div><div class='ctx'> 	default y</div><div class='del'>-	depends on !KVM || ARM64_VHE</div><div class='del'>-	depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) &amp;&amp; AS_HAS_PAC</div><div class='del'>-	# GCC 9.1 and later inserts a .note.gnu.property section note for PAC</div><div class='del'>-	# which is only understood by binutils starting with version 2.33.1.</div><div class='del'>-	depends on !CC_IS_GCC || GCC_VERSION &lt; 90100 || LD_VERSION &gt;= 233010000</div><div class='del'>-	depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE</div><div class='del'>-	depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)</div><div class='ctx'> 	help</div><div class='ctx'> 	  Pointer authentication (part of the ARMv8.3 Extensions) provides</div><div class='ctx'> 	  instructions for signing and authenticating pointers against secret</div><div class='hunk'>@@ -1518,17 +1952,9 @@ config ARM64_PTR_AUTH</div><div class='ctx'> 	  for each process at exec() time, with these keys being</div><div class='ctx'> 	  context-switched along with the process.</div><div class='ctx'> </div><div class='del'>-	  If the compiler supports the -mbranch-protection or</div><div class='del'>-	  -msign-return-address flag (e.g. GCC 7 or later), then this option</div><div class='del'>-	  will also cause the kernel itself to be compiled with return address</div><div class='del'>-	  protection. In this case, and if the target hardware is known to</div><div class='del'>-	  support pointer authentication, then CONFIG_STACKPROTECTOR can be</div><div class='del'>-	  disabled with minimal loss of protection.</div><div class='del'>-</div><div class='ctx'> 	  The feature is detected at runtime. If the feature is not present in</div><div class='ctx'> 	  hardware it will not be advertised to userspace/KVM guest nor will it</div><div class='del'>-	  be enabled. However, KVM guest also require VHE mode and hence</div><div class='del'>-	  CONFIG_ARM64_VHE=y option to use this feature.</div><div class='add'>+	  be enabled.</div><div class='ctx'> </div><div class='ctx'> 	  If the feature is present on the boot CPU but not on a late CPU, then</div><div class='ctx'> 	  the late CPU will be parked. Also, if the boot CPU does not have</div><div class='hunk'>@@ -1536,24 +1962,35 @@ config ARM64_PTR_AUTH</div><div class='ctx'> 	  but with the feature disabled. On such a system, this option should</div><div class='ctx'> 	  not be selected.</div><div class='ctx'> </div><div class='add'>+config ARM64_PTR_AUTH_KERNEL</div><div class='add'>+	bool "Use pointer authentication for kernel"</div><div class='add'>+	default y</div><div class='add'>+	depends on ARM64_PTR_AUTH</div><div class='add'>+	# Modern compilers insert a .note.gnu.property section note for PAC</div><div class='add'>+	# which is only understood by binutils starting with version 2.33.1.</div><div class='add'>+	depends on LD_IS_LLD || LD_VERSION &gt;= 23301 || (CC_IS_GCC &amp;&amp; GCC_VERSION &lt; 90100)</div><div class='add'>+	depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE</div><div class='add'>+	depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS)</div><div class='add'>+	help</div><div class='add'>+	  If the compiler supports the -mbranch-protection or</div><div class='add'>+	  -msign-return-address flag (e.g. GCC 7 or later), then this option</div><div class='add'>+	  will cause the kernel itself to be compiled with return address</div><div class='add'>+	  protection. In this case, and if the target hardware is known to</div><div class='add'>+	  support pointer authentication, then CONFIG_STACKPROTECTOR can be</div><div class='add'>+	  disabled with minimal loss of protection.</div><div class='add'>+</div><div class='ctx'> 	  This feature works with FUNCTION_GRAPH_TRACER option only if</div><div class='del'>-	  DYNAMIC_FTRACE_WITH_REGS is enabled.</div><div class='add'>+	  DYNAMIC_FTRACE_WITH_ARGS is enabled.</div><div class='ctx'> </div><div class='ctx'> config CC_HAS_BRANCH_PROT_PAC_RET</div><div class='ctx'> 	# GCC 9 or later, clang 8 or later</div><div class='ctx'> 	def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)</div><div class='ctx'> </div><div class='del'>-config CC_HAS_SIGN_RETURN_ADDRESS</div><div class='del'>-	# GCC 7, 8</div><div class='del'>-	def_bool $(cc-option,-msign-return-address=all)</div><div class='del'>-</div><div class='del'>-config AS_HAS_PAC</div><div class='del'>-	def_bool $(as-option,-Wa$(comma)-march=armv8.3-a)</div><div class='del'>-</div><div class='ctx'> config AS_HAS_CFI_NEGATE_RA_STATE</div><div class='add'>+	# binutils 2.34+</div><div class='ctx'> 	def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)</div><div class='ctx'> </div><div class='del'>-endmenu</div><div class='add'>+endmenu # "ARMv8.3 architectural features"</div><div class='ctx'> </div><div class='ctx'> menu "ARMv8.4 architectural features"</div><div class='ctx'> </div><div class='hunk'>@@ -1580,10 +2017,88 @@ config ARM64_AMU_EXTN</div><div class='ctx'> 	  correctly reflect reality. Most commonly, the value read will be 0,</div><div class='ctx'> 	  indicating that the counter is not enabled.</div><div class='ctx'> </div><div class='del'>-endmenu</div><div class='add'>+config ARM64_TLB_RANGE</div><div class='add'>+	bool "Enable support for tlbi range feature"</div><div class='add'>+	default y</div><div class='add'>+	help</div><div class='add'>+	  ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a</div><div class='add'>+	  range of input addresses.</div><div class='add'>+</div><div class='add'>+config ARM64_MPAM</div><div class='add'>+	bool "Enable support for MPAM"</div><div class='add'>+	select ARM64_MPAM_DRIVER if EXPERT	# does nothing yet</div><div class='add'>+	select ACPI_MPAM if ACPI</div><div class='add'>+	help</div><div class='add'>+	  Memory System Resource Partitioning and Monitoring (MPAM) is an</div><div class='add'>+	  optional extension to the Arm architecture that allows each</div><div class='add'>+	  transaction issued to the memory system to be labelled with a</div><div class='add'>+	  Partition identifier (PARTID) and Performance Monitoring Group</div><div class='add'>+	  identifier (PMG).</div><div class='add'>+</div><div class='add'>+	  Memory system components, such as the caches, can be configured with</div><div class='add'>+	  policies to control how much of various physical resources (such as</div><div class='add'>+	  memory bandwidth or cache memory) the transactions labelled with each</div><div class='add'>+	  PARTID can consume.  Depending on the capabilities of the hardware,</div><div class='add'>+	  the PARTID and PMG can also be used as filtering criteria to measure</div><div class='add'>+	  the memory system resource consumption of different parts of a</div><div class='add'>+	  workload.</div><div class='add'>+</div><div class='add'>+	  Use of this extension requires CPU support, support in the</div><div class='add'>+	  Memory System Components (MSC), and a description from firmware</div><div class='add'>+	  of where the MSCs are in the address space.</div><div class='add'>+</div><div class='add'>+	  MPAM is exposed to user-space via the resctrl pseudo filesystem.</div><div class='add'>+</div><div class='add'>+endmenu # "ARMv8.4 architectural features"</div><div class='ctx'> </div><div class='ctx'> menu "ARMv8.5 architectural features"</div><div class='ctx'> </div><div class='add'>+config AS_HAS_ARMV8_5</div><div class='add'>+	def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)</div><div class='add'>+</div><div class='add'>+config ARM64_BTI</div><div class='add'>+	bool "Branch Target Identification support"</div><div class='add'>+	default y</div><div class='add'>+	help</div><div class='add'>+	  Branch Target Identification (part of the ARMv8.5 Extensions)</div><div class='add'>+	  provides a mechanism to limit the set of locations to which computed</div><div class='add'>+	  branch instructions such as BR or BLR can jump.</div><div class='add'>+</div><div class='add'>+	  To make use of BTI on CPUs that support it, say Y.</div><div class='add'>+</div><div class='add'>+	  BTI is intended to provide complementary protection to other control</div><div class='add'>+	  flow integrity protection mechanisms, such as the Pointer</div><div class='add'>+	  authentication mechanism provided as part of the ARMv8.3 Extensions.</div><div class='add'>+	  For this reason, it does not make sense to enable this option without</div><div class='add'>+	  also enabling support for pointer authentication.  Thus, when</div><div class='add'>+	  enabling this option you should also select ARM64_PTR_AUTH=y.</div><div class='add'>+</div><div class='add'>+	  Userspace binaries must also be specifically compiled to make use of</div><div class='add'>+	  this mechanism.  If you say N here or the hardware does not support</div><div class='add'>+	  BTI, such binaries can still run, but you get no additional</div><div class='add'>+	  enforcement of branch destinations.</div><div class='add'>+</div><div class='add'>+config ARM64_BTI_KERNEL</div><div class='add'>+	bool "Use Branch Target Identification for kernel"</div><div class='add'>+	default y</div><div class='add'>+	depends on ARM64_BTI</div><div class='add'>+	depends on ARM64_PTR_AUTH_KERNEL</div><div class='add'>+	depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI</div><div class='add'>+	# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697</div><div class='add'>+	depends on !CC_IS_GCC || GCC_VERSION &gt;= 100100</div><div class='add'>+	# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671</div><div class='add'>+	depends on !CC_IS_GCC</div><div class='add'>+	depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS)</div><div class='add'>+	help</div><div class='add'>+	  Build the kernel with Branch Target Identification annotations</div><div class='add'>+	  and enable enforcement of this for kernel code. When this option</div><div class='add'>+	  is enabled and the system supports BTI all kernel code including</div><div class='add'>+	  modular code must have BTI enabled.</div><div class='add'>+</div><div class='add'>+config CC_HAS_BRANCH_PROT_PAC_RET_BTI</div><div class='add'>+	# GCC 9 or later, clang 8 or later</div><div class='add'>+	def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)</div><div class='add'>+</div><div class='ctx'> config ARM64_E0PD</div><div class='ctx'> 	bool "Enable support for E0PD"</div><div class='ctx'> 	default y</div><div class='hunk'>@@ -1596,20 +2111,125 @@ config ARM64_E0PD</div><div class='ctx'> </div><div class='ctx'> 	  This option enables E0PD for TTBR1 where available.</div><div class='ctx'> </div><div class='del'>-config ARCH_RANDOM</div><div class='del'>-	bool "Enable support for random number generation"</div><div class='add'>+config ARM64_AS_HAS_MTE</div><div class='add'>+	# Initial support for MTE went in binutils 2.32.0, checked with</div><div class='add'>+	# ".arch armv8.5-a+memtag" below. However, this was incomplete</div><div class='add'>+	# as a late addition to the final architecture spec (LDGM/STGM)</div><div class='add'>+	# is only supported in the newer 2.32.x and 2.33 binutils</div><div class='add'>+	# versions, hence the extra "stgm" instruction check below.</div><div class='add'>+	def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])</div><div class='add'>+</div><div class='add'>+config ARM64_MTE</div><div class='add'>+	bool "Memory Tagging Extension support"</div><div class='add'>+	default y</div><div class='add'>+	depends on ARM64_AS_HAS_MTE &amp;&amp; ARM64_TAGGED_ADDR_ABI</div><div class='add'>+	depends on AS_HAS_ARMV8_5</div><div class='add'>+	# Required for tag checking in the uaccess routines</div><div class='add'>+	select ARM64_PAN</div><div class='add'>+	select ARCH_HAS_SUBPAGE_FAULTS</div><div class='add'>+	select ARCH_USES_HIGH_VMA_FLAGS</div><div class='add'>+	select ARCH_USES_PG_ARCH_2</div><div class='add'>+	select ARCH_USES_PG_ARCH_3</div><div class='add'>+	help</div><div class='add'>+	  Memory Tagging (part of the ARMv8.5 Extensions) provides</div><div class='add'>+	  architectural support for run-time, always-on detection of</div><div class='add'>+	  various classes of memory error to aid with software debugging</div><div class='add'>+	  to eliminate vulnerabilities arising from memory-unsafe</div><div class='add'>+	  languages.</div><div class='add'>+</div><div class='add'>+	  This option enables the support for the Memory Tagging</div><div class='add'>+	  Extension at EL0 (i.e. for userspace).</div><div class='add'>+</div><div class='add'>+	  Selecting this option allows the feature to be detected at</div><div class='add'>+	  runtime. Any secondary CPU not implementing this feature will</div><div class='add'>+	  not be allowed a late bring-up.</div><div class='add'>+</div><div class='add'>+	  Userspace binaries that want to use this feature must</div><div class='add'>+	  explicitly opt in. The mechanism for the userspace is</div><div class='add'>+	  described in:</div><div class='add'>+</div><div class='add'>+	  Documentation/arch/arm64/memory-tagging-extension.rst.</div><div class='add'>+</div><div class='add'>+endmenu # "ARMv8.5 architectural features"</div><div class='add'>+</div><div class='add'>+menu "ARMv8.7 architectural features"</div><div class='add'>+</div><div class='add'>+config ARM64_EPAN</div><div class='add'>+	bool "Enable support for Enhanced Privileged Access Never (EPAN)"</div><div class='add'>+	default y</div><div class='add'>+	depends on ARM64_PAN</div><div class='add'>+	help</div><div class='add'>+	  Enhanced Privileged Access Never (EPAN) allows Privileged</div><div class='add'>+	  Access Never to be used with Execute-only mappings.</div><div class='add'>+</div><div class='add'>+	  The feature is detected at runtime, and will remain disabled</div><div class='add'>+	  if the cpu does not implement the feature.</div><div class='add'>+endmenu # "ARMv8.7 architectural features"</div><div class='add'>+</div><div class='add'>+config AS_HAS_MOPS</div><div class='add'>+	def_bool $(as-instr,.arch_extension mops)</div><div class='add'>+</div><div class='add'>+menu "ARMv8.9 architectural features"</div><div class='add'>+</div><div class='add'>+config ARM64_POE</div><div class='add'>+	prompt "Permission Overlay Extension"</div><div class='add'>+	def_bool y</div><div class='add'>+	select ARCH_USES_HIGH_VMA_FLAGS</div><div class='add'>+	select ARCH_HAS_PKEYS</div><div class='add'>+	help</div><div class='add'>+	  The Permission Overlay Extension is used to implement Memory</div><div class='add'>+	  Protection Keys. Memory Protection Keys provides a mechanism for</div><div class='add'>+	  enforcing page-based protections, but without requiring modification</div><div class='add'>+	  of the page tables when an application changes protection domains.</div><div class='add'>+</div><div class='add'>+	  For details, see Documentation/core-api/protection-keys.rst</div><div class='add'>+</div><div class='add'>+	  If unsure, say y.</div><div class='add'>+</div><div class='add'>+config ARCH_PKEY_BITS</div><div class='add'>+	int</div><div class='add'>+	default 3</div><div class='add'>+</div><div class='add'>+config ARM64_HAFT</div><div class='add'>+	bool "Support for Hardware managed Access Flag for Table Descriptors"</div><div class='add'>+	depends on ARM64_HW_AFDBM</div><div class='add'>+	default y</div><div class='add'>+	help</div><div class='add'>+	  The ARMv8.9/ARMv9.5 introduces the feature Hardware managed Access</div><div class='add'>+	  Flag for Table descriptors. When enabled an architectural executed</div><div class='add'>+	  memory access will update the Access Flag in each Table descriptor</div><div class='add'>+	  which is accessed during the translation table walk and for which</div><div class='add'>+	  the Access Flag is 0. The Access Flag of the Table descriptor use</div><div class='add'>+	  the same bit of PTE_AF.</div><div class='add'>+</div><div class='add'>+	  The feature will only be enabled if all the CPUs in the system</div><div class='add'>+	  support this feature. If unsure, say Y.</div><div class='add'>+</div><div class='add'>+endmenu # "ARMv8.9 architectural features"</div><div class='add'>+</div><div class='add'>+menu "ARMv9.4 architectural features"</div><div class='add'>+</div><div class='add'>+config ARM64_GCS</div><div class='add'>+	bool "Enable support for Guarded Control Stack (GCS)"</div><div class='ctx'> 	default y</div><div class='add'>+	select ARCH_HAS_USER_SHADOW_STACK</div><div class='add'>+	select ARCH_USES_HIGH_VMA_FLAGS</div><div class='ctx'> 	help</div><div class='del'>-	  Random number generation (part of the ARMv8.5 Extensions)</div><div class='del'>-	  provides a high bandwidth, cryptographically secure</div><div class='del'>-	  hardware random number generator.</div><div class='add'>+	  Guarded Control Stack (GCS) provides support for a separate</div><div class='add'>+	  stack with restricted access which contains only return</div><div class='add'>+	  addresses.  This can be used to harden against some attacks</div><div class='add'>+	  by comparing return address used by the program with what is</div><div class='add'>+	  stored in the GCS, and may also be used to efficiently obtain</div><div class='add'>+	  the call stack for applications such as profiling.</div><div class='add'>+</div><div class='add'>+	  The feature is detected at runtime, and will remain disabled</div><div class='add'>+	  if the system does not implement the feature.</div><div class='ctx'> </div><div class='del'>-endmenu</div><div class='add'>+endmenu # "ARMv9.4 architectural features"</div><div class='ctx'> </div><div class='ctx'> config ARM64_SVE</div><div class='ctx'> 	bool "ARM Scalable Vector Extension support"</div><div class='ctx'> 	default y</div><div class='del'>-	depends on !KVM || ARM64_VHE</div><div class='ctx'> 	help</div><div class='ctx'> 	  The Scalable Vector Extension (SVE) is an extension to the AArch64</div><div class='ctx'> 	  execution state which complements and extends the SIMD functionality</div><div class='hunk'>@@ -1638,31 +2258,16 @@ config ARM64_SVE</div><div class='ctx'> 	  booting the kernel.  If unsure and you are not observing these</div><div class='ctx'> 	  symptoms, you should assume that it is safe to say Y.</div><div class='ctx'> </div><div class='del'>-	  CPUs that support SVE are architecturally required to support the</div><div class='del'>-	  Virtualization Host Extensions (VHE), so the kernel makes no</div><div class='del'>-	  provision for supporting SVE alongside KVM without VHE enabled.</div><div class='del'>-	  Thus, you will need to enable CONFIG_ARM64_VHE if you want to support</div><div class='del'>-	  KVM in the same kernel image.</div><div class='del'>-</div><div class='del'>-config ARM64_MODULE_PLTS</div><div class='del'>-	bool "Use PLTs to allow module memory to spill over into vmalloc area"</div><div class='del'>-	depends on MODULES</div><div class='del'>-	select HAVE_MOD_ARCH_SPECIFIC</div><div class='add'>+config ARM64_SME</div><div class='add'>+	bool "ARM Scalable Matrix Extension support"</div><div class='add'>+	default y</div><div class='add'>+	depends on ARM64_SVE</div><div class='ctx'> 	help</div><div class='del'>-	  Allocate PLTs when loading modules so that jumps and calls whose</div><div class='del'>-	  targets are too far away for their relative offsets to be encoded</div><div class='del'>-	  in the instructions themselves can be bounced via veneers in the</div><div class='del'>-	  module's PLT. This allows modules to be allocated in the generic</div><div class='del'>-	  vmalloc area after the dedicated module memory area has been</div><div class='del'>-	  exhausted.</div><div class='del'>-</div><div class='del'>-	  When running with address space randomization (KASLR), the module</div><div class='del'>-	  region itself may be too far away for ordinary relative jumps and</div><div class='del'>-	  calls, and so in that case, module PLTs are required and cannot be</div><div class='del'>-	  disabled.</div><div class='del'>-</div><div class='del'>-	  Specific errata workaround(s) might also force module PLTs to be</div><div class='del'>-	  enabled (ARM64_ERRATUM_843419).</div><div class='add'>+	  The Scalable Matrix Extension (SME) is an extension to the AArch64</div><div class='add'>+	  execution state which utilises a substantial subset of the SVE</div><div class='add'>+	  instruction set, together with the addition of new architectural</div><div class='add'>+	  register state capable of holding two dimensional matrix tiles to</div><div class='add'>+	  enable various matrix operations.</div><div class='ctx'> </div><div class='ctx'> config ARM64_PSEUDO_NMI</div><div class='ctx'> 	bool "Support for NMI-like interrupts"</div><div class='hunk'>@@ -1687,11 +2292,12 @@ config ARM64_DEBUG_PRIORITY_MASKING</div><div class='ctx'> 	  the validity of ICC_PMR_EL1 when calling concerned functions.</div><div class='ctx'> </div><div class='ctx'> 	  If unsure, say N</div><div class='del'>-endif</div><div class='add'>+endif # ARM64_PSEUDO_NMI</div><div class='ctx'> </div><div class='ctx'> config RELOCATABLE</div><div class='del'>-	bool</div><div class='add'>+	bool "Build a relocatable kernel image" if EXPERT</div><div class='ctx'> 	select ARCH_HAS_RELR</div><div class='add'>+	default y</div><div class='ctx'> 	help</div><div class='ctx'> 	  This builds the kernel as a Position Independent Executable (PIE),</div><div class='ctx'> 	  which retains all relocation metadata required to relocate the</div><div class='hunk'>@@ -1703,7 +2309,6 @@ config RELOCATABLE</div><div class='ctx'> </div><div class='ctx'> config RANDOMIZE_BASE</div><div class='ctx'> 	bool "Randomize the address of the kernel image"</div><div class='del'>-	select ARM64_MODULE_PLTS if MODULES</div><div class='ctx'> 	select RELOCATABLE</div><div class='ctx'> 	help</div><div class='ctx'> 	  Randomizes the virtual address at which the kernel image is</div><div class='hunk'>@@ -1721,11 +2326,11 @@ config RANDOMIZE_BASE</div><div class='ctx'> 	  If unsure, say N.</div><div class='ctx'> </div><div class='ctx'> config RANDOMIZE_MODULE_REGION_FULL</div><div class='del'>-	bool "Randomize the module region over a 4 GB range"</div><div class='add'>+	bool "Randomize the module region over a 2 GB range"</div><div class='ctx'> 	depends on RANDOMIZE_BASE</div><div class='ctx'> 	default y</div><div class='ctx'> 	help</div><div class='del'>-	  Randomizes the location of the module region inside a 4 GB window</div><div class='add'>+	  Randomizes the location of the module region inside a 2 GB window</div><div class='ctx'> 	  covering the core kernel. This way, it is less likely for modules</div><div class='ctx'> 	  to leak information about the location of core kernel data structures</div><div class='ctx'> 	  but it does imply that function calls between modules and the core</div><div class='hunk'>@@ -1733,7 +2338,9 @@ config RANDOMIZE_MODULE_REGION_FULL</div><div class='ctx'> </div><div class='ctx'> 	  When this option is not set, the module region will be randomized over</div><div class='ctx'> 	  a limited range that contains the [_stext, _etext] interval of the</div><div class='del'>-	  core kernel, so branch relocations are always in range.</div><div class='add'>+	  core kernel, so branch relocations are almost always in range unless</div><div class='add'>+	  the region is exhausted. In this particular case of region</div><div class='add'>+	  exhaustion, modules might be able to fall back to a larger 2GB area.</div><div class='ctx'> </div><div class='ctx'> config CC_HAVE_STACKPROTECTOR_SYSREG</div><div class='ctx'> 	def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)</div><div class='hunk'>@@ -1742,7 +2349,24 @@ config STACKPROTECTOR_PER_TASK</div><div class='ctx'> 	def_bool y</div><div class='ctx'> 	depends on STACKPROTECTOR &amp;&amp; CC_HAVE_STACKPROTECTOR_SYSREG</div><div class='ctx'> </div><div class='del'>-endmenu</div><div class='add'>+config UNWIND_PATCH_PAC_INTO_SCS</div><div class='add'>+	bool "Enable shadow call stack dynamically using code patching"</div><div class='add'>+	depends on CC_IS_CLANG</div><div class='add'>+	depends on ARM64_PTR_AUTH_KERNEL &amp;&amp; CC_HAS_BRANCH_PROT_PAC_RET</div><div class='add'>+	depends on SHADOW_CALL_STACK</div><div class='add'>+	select UNWIND_TABLES</div><div class='add'>+	select DYNAMIC_SCS</div><div class='add'>+</div><div class='add'>+config ARM64_CONTPTE</div><div class='add'>+	bool "Contiguous PTE mappings for user memory" if EXPERT</div><div class='add'>+	depends on TRANSPARENT_HUGEPAGE</div><div class='add'>+	default y</div><div class='add'>+	help</div><div class='add'>+	  When enabled, user mappings are configured using the PTE contiguous</div><div class='add'>+	  bit, for any mappings that meet the size and alignment requirements.</div><div class='add'>+	  This reduces TLB pressure and improves performance.</div><div class='add'>+</div><div class='add'>+endmenu # "Kernel Features"</div><div class='ctx'> </div><div class='ctx'> menu "Boot options"</div><div class='ctx'> </div><div class='hunk'>@@ -1763,15 +2387,31 @@ config CMDLINE</div><div class='ctx'> 	  entering them here. As a minimum, you should specify the the</div><div class='ctx'> 	  root device (e.g. root=/dev/nfs).</div><div class='ctx'> </div><div class='add'>+choice</div><div class='add'>+	prompt "Kernel command line type"</div><div class='add'>+	depends on CMDLINE != ""</div><div class='add'>+	default CMDLINE_FROM_BOOTLOADER</div><div class='add'>+	help</div><div class='add'>+	  Choose how the kernel will handle the provided default kernel</div><div class='add'>+	  command line string.</div><div class='add'>+</div><div class='add'>+config CMDLINE_FROM_BOOTLOADER</div><div class='add'>+	bool "Use bootloader kernel arguments if available"</div><div class='add'>+	help</div><div class='add'>+	  Uses the command-line options passed by the boot loader. If</div><div class='add'>+	  the boot loader doesn't provide any, the default kernel command</div><div class='add'>+	  string provided in CMDLINE will be used.</div><div class='add'>+</div><div class='ctx'> config CMDLINE_FORCE</div><div class='ctx'> 	bool "Always use the default kernel command string"</div><div class='del'>-	depends on CMDLINE != ""</div><div class='ctx'> 	help</div><div class='ctx'> 	  Always use the default kernel command string, even if the boot</div><div class='ctx'> 	  loader passes other arguments to the kernel.</div><div class='ctx'> 	  This is useful if you cannot or don't want to change the</div><div class='ctx'> 	  command-line options your boot loader passes to the kernel.</div><div class='ctx'> </div><div class='add'>+endchoice</div><div class='add'>+</div><div class='ctx'> config EFI_STUB</div><div class='ctx'> 	bool</div><div class='ctx'> </div><div class='hunk'>@@ -1785,15 +2425,27 @@ config EFI</div><div class='ctx'> 	select EFI_PARAMS_FROM_FDT</div><div class='ctx'> 	select EFI_RUNTIME_WRAPPERS</div><div class='ctx'> 	select EFI_STUB</div><div class='del'>-	select EFI_ARMSTUB</div><div class='add'>+	select EFI_GENERIC_STUB</div><div class='add'>+	imply IMA_SECURE_AND_OR_TRUSTED_BOOT</div><div class='ctx'> 	default y</div><div class='ctx'> 	help</div><div class='ctx'> 	  This option provides support for runtime services provided</div><div class='ctx'> 	  by UEFI firmware (such as non-volatile variables, realtime</div><div class='del'>-          clock, and platform reset). A UEFI stub is also provided to</div><div class='add'>+	  clock, and platform reset). A UEFI stub is also provided to</div><div class='ctx'> 	  allow the kernel to be booted as an EFI application. This</div><div class='ctx'> 	  is only useful on systems that have UEFI firmware.</div><div class='ctx'> </div><div class='add'>+config COMPRESSED_INSTALL</div><div class='add'>+	bool "Install compressed image by default"</div><div class='add'>+	help</div><div class='add'>+	  This makes the regular "make install" install the compressed</div><div class='add'>+	  image we built, not the legacy uncompressed one.</div><div class='add'>+</div><div class='add'>+	  You can check that a compressed image works for you by doing</div><div class='add'>+	  "make zinstall" first, and verifying that everything is fine</div><div class='add'>+	  in your environment before making "make install" do this for</div><div class='add'>+	  you.</div><div class='add'>+</div><div class='ctx'> config DMI</div><div class='ctx'> 	bool "Enable support for SMBIOS (DMI) tables"</div><div class='ctx'> 	depends on EFI</div><div class='hunk'>@@ -1805,15 +2457,7 @@ config DMI</div><div class='ctx'> 	  However, even with this option, the resultant kernel should</div><div class='ctx'> 	  continue to boot on existing non-UEFI platforms.</div><div class='ctx'> </div><div class='del'>-endmenu</div><div class='del'>-</div><div class='del'>-config SYSVIPC_COMPAT</div><div class='del'>-	def_bool y</div><div class='del'>-	depends on COMPAT &amp;&amp; SYSVIPC</div><div class='del'>-</div><div class='del'>-config ARCH_ENABLE_HUGEPAGE_MIGRATION</div><div class='del'>-	def_bool y</div><div class='del'>-	depends on HUGETLB_PAGE &amp;&amp; MIGRATION</div><div class='add'>+endmenu # "Boot options"</div><div class='ctx'> </div><div class='ctx'> menu "Power management options"</div><div class='ctx'> </div><div class='hunk'>@@ -1830,7 +2474,7 @@ config ARCH_HIBERNATION_HEADER</div><div class='ctx'> config ARCH_SUSPEND_POSSIBLE</div><div class='ctx'> 	def_bool y</div><div class='ctx'> </div><div class='del'>-endmenu</div><div class='add'>+endmenu # "Power management options"</div><div class='ctx'> </div><div class='ctx'> menu "CPU Power Management"</div><div class='ctx'> </div><div class='hunk'>@@ -1838,14 +2482,10 @@ source "drivers/cpuidle/Kconfig"</div><div class='ctx'> </div><div class='ctx'> source "drivers/cpufreq/Kconfig"</div><div class='ctx'> </div><div class='del'>-endmenu</div><div class='del'>-</div><div class='del'>-source "drivers/firmware/Kconfig"</div><div class='add'>+endmenu # "CPU Power Management"</div><div class='ctx'> </div><div class='ctx'> source "drivers/acpi/Kconfig"</div><div class='ctx'> </div><div class='ctx'> source "arch/arm64/kvm/Kconfig"</div><div class='ctx'> </div><div class='del'>-if CRYPTO</div><div class='del'>-source "arch/arm64/crypto/Kconfig"</div><div class='del'>-endif</div><div class='add'>+source "kernel/livepatch/Kconfig"</div><div class='head'>diff --git a/arch/arm64/Kconfig.debug b/arch/arm64/Kconfig.debug<br/>index a1efa246c9ed..265c4461031f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/Kconfig.debug?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/Kconfig.debug</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/Kconfig.debug?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/Kconfig.debug</a></div><div class='hunk'>@@ -8,50 +8,6 @@ config PID_IN_CONTEXTIDR</div><div class='ctx'> 	  instructions during context switch. Say Y here only if you are</div><div class='ctx'> 	  planning to use hardware trace tools with this kernel.</div><div class='ctx'> </div><div class='del'>-config ARM64_RANDOMIZE_TEXT_OFFSET</div><div class='del'>-	bool "Randomize TEXT_OFFSET at build time"</div><div class='del'>-	help</div><div class='del'>-	  Say Y here if you want the image load offset (AKA TEXT_OFFSET)</div><div class='del'>-	  of the kernel to be randomized at build-time. When selected,</div><div class='del'>-	  this option will cause TEXT_OFFSET to be randomized upon any</div><div class='del'>-	  build of the kernel, and the offset will be reflected in the</div><div class='del'>-	  text_offset field of the resulting Image. This can be used to</div><div class='del'>-	  fuzz-test bootloaders which respect text_offset.</div><div class='del'>-</div><div class='del'>-	  This option is intended for bootloader and/or kernel testing</div><div class='del'>-	  only. Bootloaders must make no assumptions regarding the value</div><div class='del'>-	  of TEXT_OFFSET and platforms must not require a specific</div><div class='del'>-	  value.</div><div class='del'>-</div><div class='del'>-config DEBUG_WX</div><div class='del'>-	bool "Warn on W+X mappings at boot"</div><div class='del'>-	select PTDUMP_CORE</div><div class='del'>-	---help---</div><div class='del'>-	  Generate a warning if any W+X mappings are found at boot.</div><div class='del'>-</div><div class='del'>-	  This is useful for discovering cases where the kernel is leaving</div><div class='del'>-	  W+X mappings after applying NX, as such mappings are a security risk.</div><div class='del'>-	  This check also includes UXN, which should be set on all kernel</div><div class='del'>-	  mappings.</div><div class='del'>-</div><div class='del'>-	  Look for a message in dmesg output like this:</div><div class='del'>-</div><div class='del'>-	    arm64/mm: Checked W+X mappings: passed, no W+X pages found.</div><div class='del'>-</div><div class='del'>-	  or like this, if the check failed:</div><div class='del'>-</div><div class='del'>-	    arm64/mm: Checked W+X mappings: FAILED, &lt;N&gt; W+X pages found.</div><div class='del'>-</div><div class='del'>-	  Note that even if the check fails, your kernel is possibly</div><div class='del'>-	  still fine, as W+X mappings are not a security hole in</div><div class='del'>-	  themselves, what they do is that they make the exploitation</div><div class='del'>-	  of other unfixed kernel bugs easier.</div><div class='del'>-</div><div class='del'>-	  There is no runtime or memory usage effect of this option</div><div class='del'>-	  once the kernel has booted up - it's a one time check.</div><div class='del'>-</div><div class='del'>-	  If in doubt, say "Y".</div><div class='del'>-</div><div class='ctx'> config DEBUG_EFI</div><div class='ctx'> 	depends on EFI &amp;&amp; DEBUG_INFO</div><div class='ctx'> 	bool "UEFI debugging"</div><div class='head'>diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms<br/>index 55d70cfe0f9e..fff14807c965 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/Kconfig.platforms?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/Kconfig.platforms</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/Kconfig.platforms?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/Kconfig.platforms</a></div><div class='hunk'>@@ -8,17 +8,21 @@ config ARCH_ACTIONS</div><div class='ctx'> 	help</div><div class='ctx'> 	  This enables support for the Actions Semiconductor S900 SoC family.</div><div class='ctx'> </div><div class='del'>-config ARCH_AGILEX</div><div class='del'>-	bool "Intel's Agilex SoCFPGA Family"</div><div class='add'>+config ARCH_AIROHA</div><div class='add'>+	bool "Airoha SoC Support"</div><div class='add'>+	select ARM_PSCI</div><div class='add'>+	select HAVE_ARM_ARCH_TIMER</div><div class='ctx'> 	help</div><div class='del'>-	  This enables support for Intel's Agilex SoCFPGA Family.</div><div class='add'>+	  This enables support for the ARM64 based Airoha SoCs.</div><div class='ctx'> </div><div class='ctx'> config ARCH_SUNXI</div><div class='ctx'> 	bool "Allwinner sunxi 64-bit SoC Family"</div><div class='ctx'> 	select ARCH_HAS_RESET_CONTROLLER</div><div class='del'>-	select GENERIC_IRQ_CHIP</div><div class='ctx'> 	select PINCTRL</div><div class='ctx'> 	select RESET_CONTROLLER</div><div class='add'>+	select SUN4I_TIMER</div><div class='add'>+	select SUN6I_R_INTC</div><div class='add'>+	select SUNXI_NMI_INTC</div><div class='ctx'> 	help</div><div class='ctx'> 	  This enables support for Allwinner sunxi based SoCs like the A64.</div><div class='ctx'> </div><div class='hunk'>@@ -29,6 +33,31 @@ config ARCH_ALPINE</div><div class='ctx'> 	  This enables support for the Annapurna Labs Alpine</div><div class='ctx'> 	  Soc family.</div><div class='ctx'> </div><div class='add'>+config ARCH_APPLE</div><div class='add'>+	bool "Apple Silicon SoC family"</div><div class='add'>+	select APPLE_AIC</div><div class='add'>+	help</div><div class='add'>+	  This enables support for Apple's in-house ARM SoC family, such</div><div class='add'>+	  as the Apple M1.</div><div class='add'>+</div><div class='add'>+config ARCH_ARTPEC</div><div class='add'>+	bool "Axis Communications ARTPEC SoC Family"</div><div class='add'>+	depends on ARCH_EXYNOS</div><div class='add'>+	select ARM_GIC</div><div class='add'>+	help</div><div class='add'>+	   This enables support for the ARMv8 based ARTPEC SoC Family.</div><div class='add'>+</div><div class='add'>+config ARCH_AXIADO</div><div class='add'>+	bool "Axiado SoC Family"</div><div class='add'>+	select GPIOLIB</div><div class='add'>+	help</div><div class='add'>+	  This enables support for Axiado SoC family like AX3000</div><div class='add'>+</div><div class='add'>+menuconfig ARCH_BCM</div><div class='add'>+	bool "Broadcom SoC Support"</div><div class='add'>+</div><div class='add'>+if ARCH_BCM</div><div class='add'>+</div><div class='ctx'> config ARCH_BCM2835</div><div class='ctx'> 	bool "Broadcom BCM2835 family"</div><div class='ctx'> 	select TIMER_OF</div><div class='hunk'>@@ -51,9 +80,30 @@ config ARCH_BCM_IPROC</div><div class='ctx'> 	help</div><div class='ctx'> 	  This enables support for Broadcom iProc based SoCs</div><div class='ctx'> </div><div class='add'>+config ARCH_BCMBCA</div><div class='add'>+	bool "Broadcom Broadband Carrier Access (BCA) origin SoC"</div><div class='add'>+	select GPIOLIB</div><div class='add'>+	help</div><div class='add'>+	  Say Y if you intend to run the kernel on a Broadcom Broadband ARM-based</div><div class='add'>+	  BCA chipset.</div><div class='add'>+</div><div class='add'>+	  This enables support for Broadcom BCA ARM-based broadband chipsets,</div><div class='add'>+	  including the DSL, PON and Wireless family of chips.</div><div class='add'>+</div><div class='add'>+config ARCH_BRCMSTB</div><div class='add'>+	bool "Broadcom Set-Top-Box SoCs"</div><div class='add'>+	select ARCH_HAS_RESET_CONTROLLER</div><div class='add'>+	select GENERIC_IRQ_CHIP</div><div class='add'>+	select PINCTRL</div><div class='add'>+	help</div><div class='add'>+	  This enables support for Broadcom's ARMv8 Set Top Box SoCs</div><div class='add'>+</div><div class='add'>+endif</div><div class='add'>+</div><div class='ctx'> config ARCH_BERLIN</div><div class='ctx'> 	bool "Marvell Berlin SoC Family"</div><div class='ctx'> 	select DW_APB_ICTL</div><div class='add'>+	select DW_APB_TIMER_OF</div><div class='ctx'> 	select GPIOLIB</div><div class='ctx'> 	select PINCTRL</div><div class='ctx'> 	help</div><div class='hunk'>@@ -64,24 +114,31 @@ config ARCH_BITMAIN</div><div class='ctx'> 	help</div><div class='ctx'> 	  This enables support for the Bitmain SoC Family.</div><div class='ctx'> </div><div class='del'>-config ARCH_BRCMSTB</div><div class='del'>-	bool "Broadcom Set-Top-Box SoCs"</div><div class='del'>-	select ARCH_HAS_RESET_CONTROLLER</div><div class='del'>-	select BCM7038_L1_IRQ</div><div class='del'>-	select BRCMSTB_L2_IRQ</div><div class='del'>-	select GENERIC_IRQ_CHIP</div><div class='del'>-	select PINCTRL</div><div class='add'>+config ARCH_BLAIZE</div><div class='add'>+	bool "Blaize SoC Platforms"</div><div class='ctx'> 	help</div><div class='del'>-	  This enables support for Broadcom's ARMv8 Set Top Box SoCs</div><div class='add'>+	  This enables support for the Blaize SoC family</div><div class='add'>+</div><div class='add'>+config ARCH_BST</div><div class='add'>+	bool "Black Sesame Technologies SoC Family"</div><div class='add'>+	help</div><div class='add'>+	  This enables support for Black Sesame Technologies (BST) SoC family.</div><div class='add'>+	  BST produces automotive-grade system-on-chips for intelligent driving,</div><div class='add'>+	  focusing on computer vision and AI capabilities. The BST C1200 family</div><div class='add'>+	  includes SoCs for ADAS and autonomous driving applications.</div><div class='add'>+</div><div class='add'>+config ARCH_CIX</div><div class='add'>+	bool "Cixtech SoC family"</div><div class='add'>+	help</div><div class='add'>+	  This enables support for the Cixtech SoC family,</div><div class='add'>+	  like P1(sky1).</div><div class='ctx'> </div><div class='ctx'> config ARCH_EXYNOS</div><div class='del'>-	bool "ARMv8 based Samsung Exynos SoC family"</div><div class='add'>+	bool "Samsung Exynos SoC family"</div><div class='ctx'> 	select COMMON_CLK_SAMSUNG</div><div class='del'>-	select EXYNOS_CHIPID</div><div class='add'>+	select CLKSRC_EXYNOS_MCT</div><div class='ctx'> 	select EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS</div><div class='ctx'> 	select EXYNOS_PMU</div><div class='del'>-	select HAVE_S3C2410_WATCHDOG if WATCHDOG</div><div class='del'>-	select HAVE_S3C_RTC if RTC_CLASS</div><div class='ctx'> 	select PINCTRL</div><div class='ctx'> 	select PINCTRL_EXYNOS</div><div class='ctx'> 	select PM_GENERIC_DOMAINS if PM</div><div class='hunk'>@@ -91,23 +148,12 @@ config ARCH_EXYNOS</div><div class='ctx'> </div><div class='ctx'> config ARCH_K3</div><div class='ctx'> 	bool "Texas Instruments Inc. K3 multicore SoC architecture"</div><div class='del'>-	select PM_GENERIC_DOMAINS if PM</div><div class='del'>-	select MAILBOX</div><div class='ctx'> 	select SOC_TI</div><div class='del'>-	select TI_MESSAGE_MANAGER</div><div class='del'>-	select TI_SCI_PROTOCOL</div><div class='del'>-	select TI_SCI_INTR_IRQCHIP</div><div class='del'>-	select TI_SCI_INTA_IRQCHIP</div><div class='add'>+	select TI_K3_SOCINFO</div><div class='ctx'> 	help</div><div class='ctx'> 	  This enables support for Texas Instruments' K3 multicore SoC</div><div class='ctx'> 	  architecture.</div><div class='ctx'> </div><div class='del'>-config ARCH_LAYERSCAPE</div><div class='del'>-	bool "ARMv8 based Freescale Layerscape SoC family"</div><div class='del'>-	select EDAC_SUPPORT</div><div class='del'>-	help</div><div class='del'>-	  This enables support for the Freescale Layerscape SoC family.</div><div class='del'>-</div><div class='ctx'> config ARCH_LG1K</div><div class='ctx'> 	bool "LG Electronics LG1K SoC Family"</div><div class='ctx'> 	help</div><div class='hunk'>@@ -121,6 +167,11 @@ config ARCH_HISI</div><div class='ctx'> 	help</div><div class='ctx'> 	  This enables support for Hisilicon ARMv8 SoC family</div><div class='ctx'> </div><div class='add'>+config ARCH_KEEMBAY</div><div class='add'>+	bool "Keem Bay SoC"</div><div class='add'>+	help</div><div class='add'>+	  This enables support for Intel Movidius SoC code-named Keem Bay.</div><div class='add'>+</div><div class='ctx'> config ARCH_MEDIATEK</div><div class='ctx'> 	bool "MediaTek SoC Family"</div><div class='ctx'> 	select ARM_GIC</div><div class='hunk'>@@ -132,16 +183,55 @@ config ARCH_MEDIATEK</div><div class='ctx'> </div><div class='ctx'> config ARCH_MESON</div><div class='ctx'> 	bool "Amlogic Platforms"</div><div class='del'>-	select PINCTRL</div><div class='del'>-	select PINCTRL_MESON</div><div class='del'>-	select COMMON_CLK_GXBB</div><div class='del'>-	select COMMON_CLK_AXG</div><div class='del'>-	select COMMON_CLK_G12A</div><div class='del'>-	select MESON_IRQ_GPIO</div><div class='ctx'> 	help</div><div class='ctx'> 	  This enables support for the arm64 based Amlogic SoCs</div><div class='ctx'> 	  such as the s905, S905X/D, S912, A113X/D or S905X/D2</div><div class='ctx'> </div><div class='add'>+menu "Microchip SoC support"</div><div class='add'>+</div><div class='add'>+config ARCH_MICROCHIP</div><div class='add'>+	bool</div><div class='add'>+</div><div class='add'>+config ARCH_LAN969X</div><div class='add'>+	bool "Microchip LAN969X SoC family"</div><div class='add'>+	select PINCTRL</div><div class='add'>+	select DW_APB_TIMER_OF</div><div class='add'>+	select ARCH_MICROCHIP</div><div class='add'>+	help</div><div class='add'>+	  This enables support for the Microchip LAN969X ARMv8-based</div><div class='add'>+	  SoC family of TSN-capable gigabit switches.</div><div class='add'>+</div><div class='add'>+	  The LAN969X Ethernet switch family provides a rich set of</div><div class='add'>+	  switching features such as advanced TCAM-based VLAN and QoS</div><div class='add'>+	  processing enabling delivery of differentiated services, and</div><div class='add'>+	  security through TCAM-based frame processing using versatile</div><div class='add'>+	  content aware processor (VCAP).</div><div class='add'>+</div><div class='add'>+config ARCH_SPARX5</div><div class='add'>+	bool "Microchip Sparx5 SoC family"</div><div class='add'>+	select PINCTRL</div><div class='add'>+	select DW_APB_TIMER_OF</div><div class='add'>+	select ARCH_MICROCHIP</div><div class='add'>+	help</div><div class='add'>+	  This enables support for the Microchip Sparx5 ARMv8-based</div><div class='add'>+	  SoC family of TSN-capable gigabit switches.</div><div class='add'>+</div><div class='add'>+	  The SparX-5 Ethernet switch family provides a rich set of</div><div class='add'>+	  switching features such as advanced TCAM-based VLAN and QoS</div><div class='add'>+	  processing enabling delivery of differentiated services, and</div><div class='add'>+	  security through TCAM-based frame processing using versatile</div><div class='add'>+	  content aware processor (VCAP).</div><div class='add'>+</div><div class='add'>+endmenu</div><div class='add'>+</div><div class='add'>+config ARCH_MMP</div><div class='add'>+	bool "Marvell MMP SoC Family"</div><div class='add'>+	select PINCTRL</div><div class='add'>+	select PINCTRL_SINGLE</div><div class='add'>+	help</div><div class='add'>+	  This enables support for Marvell MMP SoC family, currently</div><div class='add'>+	  supporting PXA1908 aka IAP140.</div><div class='add'>+</div><div class='ctx'> config ARCH_MVEBU</div><div class='ctx'> 	bool "Marvell EBU SoC Family"</div><div class='ctx'> 	select ARMADA_AP806_SYSCON</div><div class='hunk'>@@ -159,14 +249,26 @@ config ARCH_MVEBU</div><div class='ctx'> 	select PINCTRL_ARMADA_37XX</div><div class='ctx'> 	select PINCTRL_ARMADA_AP806</div><div class='ctx'> 	select PINCTRL_ARMADA_CP110</div><div class='add'>+	select PINCTRL_AC5</div><div class='ctx'> 	help</div><div class='del'>-	  This enables support for Marvell EBU familly, including:</div><div class='add'>+	  This enables support for Marvell EBU family, including:</div><div class='ctx'> 	   - Armada 3700 SoC Family</div><div class='ctx'> 	   - Armada 7K SoC Family</div><div class='ctx'> 	   - Armada 8K SoC Family</div><div class='add'>+	   - 98DX2530 SoC Family</div><div class='add'>+</div><div class='add'>+menuconfig ARCH_NXP</div><div class='add'>+	bool "NXP SoC support"</div><div class='add'>+</div><div class='add'>+if ARCH_NXP</div><div class='add'>+</div><div class='add'>+config ARCH_LAYERSCAPE</div><div class='add'>+	bool "Freescale Layerscape SoC family"</div><div class='add'>+	help</div><div class='add'>+	  This enables support for the Freescale Layerscape SoC family.</div><div class='ctx'> </div><div class='ctx'> config ARCH_MXC</div><div class='del'>-	bool "ARMv8 based NXP i.MX SoC family"</div><div class='add'>+	bool "NXP i.MX SoC family"</div><div class='ctx'> 	select ARM64_ERRATUM_843419</div><div class='ctx'> 	select ARM64_ERRATUM_845719 if COMPAT</div><div class='ctx'> 	select IMX_GPCV2</div><div class='hunk'>@@ -179,10 +281,50 @@ config ARCH_MXC</div><div class='ctx'> 	  This enables support for the ARMv8 based SoCs in the</div><div class='ctx'> 	  NXP i.MX family.</div><div class='ctx'> </div><div class='add'>+config ARCH_S32</div><div class='add'>+	bool "NXP S32 SoC Family"</div><div class='add'>+	help</div><div class='add'>+	  This enables support for the NXP S32 family of processors.</div><div class='add'>+</div><div class='add'>+endif</div><div class='add'>+</div><div class='add'>+config ARCH_MA35</div><div class='add'>+	bool "Nuvoton MA35 Architecture"</div><div class='add'>+	select GPIOLIB</div><div class='add'>+	select PINCTRL</div><div class='add'>+	select RESET_CONTROLLER</div><div class='add'>+	help</div><div class='add'>+	  This enables support for the ARMv8 based Nuvoton MA35 series SoCs.</div><div class='add'>+</div><div class='add'>+config ARCH_NPCM</div><div class='add'>+	bool "Nuvoton NPCM Architecture"</div><div class='add'>+	select PINCTRL</div><div class='add'>+	select GPIOLIB</div><div class='add'>+	select NPCM7XX_TIMER</div><div class='add'>+	select RESET_CONTROLLER</div><div class='add'>+	select MFD_SYSCON</div><div class='add'>+	help</div><div class='add'>+	  General support for NPCM8xx BMC (Arbel).</div><div class='add'>+	  Nuvoton NPCM8xx BMC based on the Cortex A35.</div><div class='add'>+</div><div class='add'>+config ARCH_PENSANDO</div><div class='add'>+	bool "AMD Pensando Platforms"</div><div class='add'>+	help</div><div class='add'>+	  This enables support for the ARMv8 based AMD Pensando SoC</div><div class='add'>+	  family to include the Elba SoC.</div><div class='add'>+</div><div class='add'>+	  AMD Pensando SoCs support a range of Distributed Services</div><div class='add'>+	  Cards in PCIe format installed into servers.  The Elba</div><div class='add'>+	  SoC includes 16 Cortex A-72 CPU cores, 144 P4-programmable</div><div class='add'>+	  cores for a minimal latency/jitter datapath, and network</div><div class='add'>+	  interfaces up to 200 Gb/s.</div><div class='add'>+</div><div class='ctx'> config ARCH_QCOM</div><div class='ctx'> 	bool "Qualcomm Platforms"</div><div class='ctx'> 	select GPIOLIB</div><div class='ctx'> 	select PINCTRL</div><div class='add'>+	select HAVE_PWRCTRL if PCI</div><div class='add'>+	select HAVE_SHARED_GPIOS</div><div class='ctx'> 	help</div><div class='ctx'> 	  This enables support for the ARMv8 based Qualcomm chipsets.</div><div class='ctx'> </div><div class='hunk'>@@ -195,50 +337,67 @@ config ARCH_REALTEK</div><div class='ctx'> </div><div class='ctx'> config ARCH_RENESAS</div><div class='ctx'> 	bool "Renesas SoC Platforms"</div><div class='del'>-	select GPIOLIB</div><div class='del'>-	select PINCTRL</div><div class='del'>-	select SOC_BUS</div><div class='ctx'> 	help</div><div class='ctx'> 	  This enables support for the ARMv8 based Renesas SoCs.</div><div class='ctx'> </div><div class='ctx'> config ARCH_ROCKCHIP</div><div class='ctx'> 	bool "Rockchip Platforms"</div><div class='ctx'> 	select ARCH_HAS_RESET_CONTROLLER</div><div class='del'>-	select GPIOLIB</div><div class='ctx'> 	select PINCTRL</div><div class='del'>-	select PINCTRL_ROCKCHIP</div><div class='ctx'> 	select PM</div><div class='ctx'> 	select ROCKCHIP_TIMER</div><div class='ctx'> 	help</div><div class='ctx'> 	  This enables support for the ARMv8 based Rockchip chipsets,</div><div class='ctx'> 	  like the RK3368.</div><div class='ctx'> </div><div class='del'>-config ARCH_S32</div><div class='del'>-	bool "NXP S32 SoC Family"</div><div class='del'>-	help</div><div class='del'>-	  This enables support for the NXP S32 family of processors.</div><div class='del'>-</div><div class='ctx'> config ARCH_SEATTLE</div><div class='ctx'> 	bool "AMD Seattle SoC Family"</div><div class='ctx'> 	help</div><div class='ctx'> 	  This enables support for AMD Seattle SOC Family</div><div class='ctx'> </div><div class='del'>-config ARCH_STRATIX10</div><div class='del'>-	bool "Altera's Stratix 10 SoCFPGA Family"</div><div class='add'>+config ARCH_INTEL_SOCFPGA</div><div class='add'>+	bool "Intel's SoCFPGA ARMv8 Families"</div><div class='add'>+	help</div><div class='add'>+	  This enables support for Intel's SoCFPGA ARMv8 families:</div><div class='add'>+	  Stratix 10 (ex. Altera), Stratix10 Software Virtual Platform,</div><div class='add'>+	  Agilex and eASIC N5X.</div><div class='add'>+</div><div class='add'>+config ARCH_SOPHGO</div><div class='add'>+	bool "Sophgo SoCs"</div><div class='add'>+	select ARCH_HAS_RESET_CONTROLLER</div><div class='ctx'> 	help</div><div class='del'>-	  This enables support for Altera's Stratix 10 SoCFPGA Family.</div><div class='add'>+	  This enables support for Sophgo SoC platform hardware.</div><div class='add'>+</div><div class='add'>+config ARCH_STM32</div><div class='add'>+	bool "STMicroelectronics STM32 SoC Family"</div><div class='add'>+	select GPIOLIB</div><div class='add'>+	select PINCTRL</div><div class='add'>+	select ARM_SMC_MBOX</div><div class='add'>+	select ARM_SCMI_PROTOCOL</div><div class='add'>+	select REGULATOR</div><div class='add'>+	select REGULATOR_ARM_SCMI</div><div class='add'>+	select COMMON_CLK_SCMI</div><div class='add'>+	select STM32_FIREWALL</div><div class='add'>+	help</div><div class='add'>+	  This enables support for ARMv8 based STMicroelectronics</div><div class='add'>+	  STM32 family, including:</div><div class='add'>+		- STM32MP21:</div><div class='add'>+			- STM32MP211, STM32MP213, STM32MP215.</div><div class='add'>+		- STM32MP23:</div><div class='add'>+			- STM32MP231, STM32MP233, STM32MP235.</div><div class='add'>+		- STM32MP25:</div><div class='add'>+			- STM32MP251, STM32MP253, STM32MP255 and STM32MP257.</div><div class='ctx'> </div><div class='ctx'> config ARCH_SYNQUACER</div><div class='ctx'> 	bool "Socionext SynQuacer SoC Family"</div><div class='add'>+	select IRQ_FASTEOI_HIERARCHY_HANDLERS</div><div class='ctx'> </div><div class='ctx'> config ARCH_TEGRA</div><div class='ctx'> 	bool "NVIDIA Tegra SoC Family"</div><div class='ctx'> 	select ARCH_HAS_RESET_CONTROLLER</div><div class='ctx'> 	select ARM_GIC_PM</div><div class='del'>-	select CLKDEV_LOOKUP</div><div class='ctx'> 	select CLKSRC_MMIO</div><div class='ctx'> 	select TIMER_OF</div><div class='del'>-	select GENERIC_CLOCKEVENTS</div><div class='ctx'> 	select GPIOLIB</div><div class='ctx'> 	select PINCTRL</div><div class='ctx'> 	select PM</div><div class='hunk'>@@ -247,8 +406,14 @@ config ARCH_TEGRA</div><div class='ctx'> 	help</div><div class='ctx'> 	  This enables support for the NVIDIA Tegra SoC family.</div><div class='ctx'> </div><div class='add'>+config ARCH_TESLA_FSD</div><div class='add'>+	bool "Tesla platform"</div><div class='add'>+	depends on ARCH_EXYNOS</div><div class='add'>+	help</div><div class='add'>+	  Support for ARMv8 based Tesla platforms.</div><div class='add'>+</div><div class='ctx'> config ARCH_SPRD</div><div class='del'>-	tristate "Spreadtrum SoC platform"</div><div class='add'>+	bool "Spreadtrum SoC platform"</div><div class='ctx'> 	help</div><div class='ctx'> 	  Support for Spreadtrum ARM based SoCs</div><div class='ctx'> </div><div class='hunk'>@@ -273,34 +438,28 @@ config ARCH_UNIPHIER</div><div class='ctx'> 	  This enables support for Socionext UniPhier SoC family.</div><div class='ctx'> </div><div class='ctx'> config ARCH_VEXPRESS</div><div class='del'>-	bool "ARMv8 software model (Versatile Express)"</div><div class='del'>-	select COMMON_CLK_VERSATILE</div><div class='add'>+	bool "ARM Ltd Platforms"</div><div class='ctx'> 	select GPIOLIB</div><div class='ctx'> 	select PM</div><div class='ctx'> 	select PM_GENERIC_DOMAINS</div><div class='del'>-	select POWER_RESET_VEXPRESS</div><div class='del'>-	select VEXPRESS_CONFIG</div><div class='ctx'> 	help</div><div class='del'>-	  This enables support for the ARMv8 software model (Versatile</div><div class='del'>-	  Express).</div><div class='add'>+	  This enables support for the ARM Ltd Platforms.</div><div class='ctx'> </div><div class='del'>-config ARCH_VULCAN</div><div class='del'>-	def_bool n</div><div class='add'>+config ARCH_VISCONTI</div><div class='add'>+	bool "Toshiba Visconti SoC Family"</div><div class='add'>+	select PINCTRL</div><div class='add'>+	select PINCTRL_VISCONTI</div><div class='add'>+	help</div><div class='add'>+	  This enables support for Toshiba Visconti SoCs Family.</div><div class='ctx'> </div><div class='ctx'> config ARCH_XGENE</div><div class='ctx'> 	bool "AppliedMicro X-Gene SOC Family"</div><div class='ctx'> 	help</div><div class='ctx'> 	  This enables support for AppliedMicro X-Gene SOC Family</div><div class='ctx'> </div><div class='del'>-config ARCH_ZX</div><div class='del'>-	bool "ZTE ZX SoC Family"</div><div class='del'>-	select PINCTRL</div><div class='del'>-	help</div><div class='del'>-	  This enables support for ZTE ZX SoC Family</div><div class='del'>-</div><div class='ctx'> config ARCH_ZYNQMP</div><div class='ctx'> 	bool "Xilinx ZynqMP Family"</div><div class='ctx'> 	help</div><div class='ctx'> 	  This enables support for Xilinx ZynqMP Family</div><div class='ctx'> </div><div class='del'>-endmenu</div><div class='add'>+endmenu # "Platform selection"</div><div class='head'>diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile<br/>index 85e4149cc5d5..73a10f65ce8b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/Makefile?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/Makefile</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/Makefile</a></div><div class='hunk'>@@ -10,30 +10,17 @@</div><div class='ctx'> #</div><div class='ctx'> # Copyright (C) 1995-2001 by Russell King</div><div class='ctx'> </div><div class='del'>-LDFLAGS_vmlinux	:=--no-undefined -X</div><div class='del'>-CPPFLAGS_vmlinux.lds = -DTEXT_OFFSET=$(TEXT_OFFSET)</div><div class='del'>-GZFLAGS		:=-9</div><div class='add'>+LDFLAGS_vmlinux	:=--no-undefined -X --pic-veneer</div><div class='ctx'> </div><div class='ctx'> ifeq ($(CONFIG_RELOCATABLE), y)</div><div class='ctx'> # Pass --no-apply-dynamic-relocs to restore pre-binutils-2.27 behaviour</div><div class='ctx'> # for relative relocs, since this leads to better Image compression</div><div class='ctx'> # with the relocation offsets always being zero.</div><div class='del'>-LDFLAGS_vmlinux		+= -shared -Bsymbolic -z notext -z norelro \</div><div class='del'>-			$(call ld-option, --no-apply-dynamic-relocs)</div><div class='add'>+LDFLAGS_vmlinux	+= -shared -Bsymbolic -z notext --no-apply-dynamic-relocs</div><div class='ctx'> endif</div><div class='ctx'> </div><div class='ctx'> ifeq ($(CONFIG_ARM64_ERRATUM_843419),y)</div><div class='del'>-  ifeq ($(call ld-option, --fix-cortex-a53-843419),)</div><div class='del'>-$(warning ld does not support --fix-cortex-a53-843419; kernel may be susceptible to erratum)</div><div class='del'>-  else</div><div class='ctx'> LDFLAGS_vmlinux	+= --fix-cortex-a53-843419</div><div class='del'>-  endif</div><div class='del'>-endif</div><div class='del'>-</div><div class='del'>-ifeq ($(CONFIG_ARM64_USE_LSE_ATOMICS), y)</div><div class='del'>-  ifneq ($(CONFIG_ARM64_LSE_ATOMICS), y)</div><div class='del'>-$(warning LSE atomics not supported by binutils)</div><div class='del'>-  endif</div><div class='ctx'> endif</div><div class='ctx'> </div><div class='ctx'> cc_has_k_constraint := $(call try-run,echo				\</div><div class='hunk'>@@ -46,15 +33,38 @@ ifeq ($(CONFIG_BROKEN_GAS_INST),y)</div><div class='ctx'> $(warning Detected assembler with broken .inst; disassembly will be unreliable)</div><div class='ctx'> endif</div><div class='ctx'> </div><div class='del'>-KBUILD_CFLAGS	+= -mgeneral-regs-only	\</div><div class='add'>+# The GCC option -ffreestanding is required in order to compile code containing</div><div class='add'>+# ARM/NEON intrinsics in a non C99-compliant environment (such as the kernel)</div><div class='add'>+CC_FLAGS_FPU	:= -ffreestanding</div><div class='add'>+# Enable &lt;arm_neon.h&gt;</div><div class='add'>+CC_FLAGS_FPU	+= -isystem $(shell $(CC) -print-file-name=include)</div><div class='add'>+CC_FLAGS_NO_FPU	:= -mgeneral-regs-only</div><div class='add'>+</div><div class='add'>+KBUILD_CFLAGS	+= $(CC_FLAGS_NO_FPU) \</div><div class='ctx'> 		   $(compat_vdso) $(cc_has_k_constraint)</div><div class='del'>-KBUILD_CFLAGS	+= -fno-asynchronous-unwind-tables</div><div class='ctx'> KBUILD_CFLAGS	+= $(call cc-disable-warning, psabi)</div><div class='ctx'> KBUILD_AFLAGS	+= $(compat_vdso)</div><div class='ctx'> </div><div class='add'>+ifeq ($(call rustc-min-version, 108500),y)</div><div class='add'>+KBUILD_RUSTFLAGS += --target=aarch64-unknown-none-softfloat</div><div class='add'>+else</div><div class='add'>+KBUILD_RUSTFLAGS += --target=aarch64-unknown-none -Ctarget-feature="-neon"</div><div class='add'>+endif</div><div class='add'>+</div><div class='ctx'> KBUILD_CFLAGS	+= $(call cc-option,-mabi=lp64)</div><div class='ctx'> KBUILD_AFLAGS	+= $(call cc-option,-mabi=lp64)</div><div class='ctx'> </div><div class='add'>+# Avoid generating .eh_frame* sections.</div><div class='add'>+ifneq ($(CONFIG_UNWIND_TABLES),y)</div><div class='add'>+KBUILD_CFLAGS	+= -fno-asynchronous-unwind-tables -fno-unwind-tables</div><div class='add'>+KBUILD_AFLAGS	+= -fno-asynchronous-unwind-tables -fno-unwind-tables</div><div class='add'>+KBUILD_RUSTFLAGS += -Cforce-unwind-tables=n</div><div class='add'>+else</div><div class='add'>+KBUILD_CFLAGS	+= -fasynchronous-unwind-tables</div><div class='add'>+KBUILD_AFLAGS	+= -fasynchronous-unwind-tables</div><div class='add'>+KBUILD_RUSTFLAGS += -Cforce-unwind-tables=y -Zuse-sync-unwind=n</div><div class='add'>+endif</div><div class='add'>+</div><div class='ctx'> ifeq ($(CONFIG_STACKPROTECTOR_PER_TASK),y)</div><div class='ctx'> prepare: stack_protector_prepare</div><div class='ctx'> stack_protector_prepare: prepare0</div><div class='hunk'>@@ -62,68 +72,82 @@ stack_protector_prepare: prepare0</div><div class='ctx'> 				-mstack-protector-guard-reg=sp_el0	  \</div><div class='ctx'> 				-mstack-protector-guard-offset=$(shell	  \</div><div class='ctx'> 			awk '{if ($$2 == "TSK_STACK_CANARY") print $$3;}' \</div><div class='del'>-					include/generated/asm-offsets.h))</div><div class='add'>+				$(objtree)/include/generated/asm-offsets.h))</div><div class='ctx'> endif</div><div class='ctx'> </div><div class='del'>-# Ensure that if the compiler supports branch protection we default it</div><div class='del'>-# off, this will be overridden if we are using branch protection.</div><div class='del'>-branch-prot-flags-y += $(call cc-option,-mbranch-protection=none)</div><div class='add'>+ifeq ($(CONFIG_ARM64_BTI_KERNEL),y)</div><div class='add'>+  KBUILD_CFLAGS += -mbranch-protection=pac-ret+bti</div><div class='add'>+  KBUILD_RUSTFLAGS += -Zbranch-protection=bti,pac-ret</div><div class='add'>+else ifeq ($(CONFIG_ARM64_PTR_AUTH_KERNEL),y)</div><div class='add'>+  KBUILD_RUSTFLAGS += -Zbranch-protection=pac-ret</div><div class='add'>+  ifeq ($(CONFIG_CC_HAS_BRANCH_PROT_PAC_RET),y)</div><div class='add'>+    KBUILD_CFLAGS += -mbranch-protection=pac-ret</div><div class='add'>+  else</div><div class='add'>+    KBUILD_CFLAGS += -msign-return-address=non-leaf</div><div class='add'>+  endif</div><div class='add'>+else</div><div class='add'>+  KBUILD_CFLAGS += $(call cc-option,-mbranch-protection=none)</div><div class='add'>+endif</div><div class='ctx'> </div><div class='del'>-ifeq ($(CONFIG_ARM64_PTR_AUTH),y)</div><div class='del'>-branch-prot-flags-$(CONFIG_CC_HAS_SIGN_RETURN_ADDRESS) := -msign-return-address=all</div><div class='del'>-branch-prot-flags-$(CONFIG_CC_HAS_BRANCH_PROT_PAC_RET) := -mbranch-protection=pac-ret+leaf</div><div class='del'>-# -march=armv8.3-a enables the non-nops instructions for PAC, to avoid the</div><div class='del'>-# compiler to generate them and consequently to break the single image contract</div><div class='del'>-# we pass it only to the assembler. This option is utilized only in case of non</div><div class='del'>-# integrated assemblers.</div><div class='del'>-branch-prot-flags-$(CONFIG_AS_HAS_PAC) += -Wa,-march=armv8.3-a</div><div class='add'>+# Tell the assembler to support instructions from the latest target</div><div class='add'>+# architecture.</div><div class='add'>+#</div><div class='add'>+# For non-integrated assemblers we'll pass this on the command line, and for</div><div class='add'>+# integrated assemblers we'll define ARM64_ASM_ARCH and ARM64_ASM_PREAMBLE for</div><div class='add'>+# inline usage.</div><div class='add'>+#</div><div class='add'>+# We cannot pass the same arch flag to the compiler as this would allow it to</div><div class='add'>+# freely generate instructions which are not supported by earlier architecture</div><div class='add'>+# versions, which would prevent a single kernel image from working on earlier</div><div class='add'>+# hardware.</div><div class='add'>+ifeq ($(CONFIG_AS_HAS_ARMV8_5), y)</div><div class='add'>+  asm-arch := armv8.5-a</div><div class='add'>+else</div><div class='add'>+  asm-arch := armv8.4-a</div><div class='ctx'> endif</div><div class='ctx'> </div><div class='del'>-KBUILD_CFLAGS += $(branch-prot-flags-y)</div><div class='add'>+ifdef asm-arch</div><div class='add'>+KBUILD_CFLAGS	+= -Wa,-march=$(asm-arch) \</div><div class='add'>+		   -DARM64_ASM_ARCH='"$(asm-arch)"'</div><div class='add'>+endif</div><div class='add'>+</div><div class='add'>+ifeq ($(CONFIG_SHADOW_CALL_STACK), y)</div><div class='add'>+KBUILD_CFLAGS	+= -ffixed-x18</div><div class='add'>+KBUILD_RUSTFLAGS += -Zfixed-x18</div><div class='add'>+endif</div><div class='ctx'> </div><div class='ctx'> ifeq ($(CONFIG_CPU_BIG_ENDIAN), y)</div><div class='ctx'> KBUILD_CPPFLAGS	+= -mbig-endian</div><div class='ctx'> CHECKFLAGS	+= -D__AARCH64EB__</div><div class='del'>-AS		+= -EB</div><div class='ctx'> # Prefer the baremetal ELF build target, but not all toolchains include</div><div class='ctx'> # it so fall back to the standard linux version if needed.</div><div class='del'>-KBUILD_LDFLAGS	+= -EB $(call ld-option, -maarch64elfb, -maarch64linuxb)</div><div class='add'>+KBUILD_LDFLAGS	+= -EB $(call ld-option, -maarch64elfb, -maarch64linuxb -z norelro)</div><div class='ctx'> UTS_MACHINE	:= aarch64_be</div><div class='ctx'> else</div><div class='ctx'> KBUILD_CPPFLAGS	+= -mlittle-endian</div><div class='ctx'> CHECKFLAGS	+= -D__AARCH64EL__</div><div class='del'>-AS		+= -EL</div><div class='ctx'> # Same as above, prefer ELF but fall back to linux target if needed.</div><div class='del'>-KBUILD_LDFLAGS	+= -EL $(call ld-option, -maarch64elf, -maarch64linux)</div><div class='add'>+KBUILD_LDFLAGS	+= -EL $(call ld-option, -maarch64elf, -maarch64linux -z norelro)</div><div class='ctx'> UTS_MACHINE	:= aarch64</div><div class='ctx'> endif</div><div class='ctx'> </div><div class='del'>-CHECKFLAGS	+= -D__aarch64__</div><div class='del'>-</div><div class='del'>-ifeq ($(CONFIG_ARM64_MODULE_PLTS),y)</div><div class='del'>-KBUILD_LDS_MODULE	+= $(srctree)/arch/arm64/kernel/module.lds</div><div class='add'>+ifeq ($(CONFIG_LD_IS_LLD), y)</div><div class='add'>+KBUILD_LDFLAGS	+= -z norelro</div><div class='ctx'> endif</div><div class='ctx'> </div><div class='del'>-ifeq ($(CONFIG_DYNAMIC_FTRACE_WITH_REGS),y)</div><div class='add'>+CHECKFLAGS	+= -D__aarch64__</div><div class='add'>+</div><div class='add'>+ifeq ($(CONFIG_DYNAMIC_FTRACE_WITH_CALL_OPS),y)</div><div class='add'>+  KBUILD_CPPFLAGS += -DCC_USING_PATCHABLE_FUNCTION_ENTRY</div><div class='add'>+  CC_FLAGS_FTRACE := -fpatchable-function-entry=4,2</div><div class='add'>+else ifeq ($(CONFIG_DYNAMIC_FTRACE_WITH_ARGS),y)</div><div class='ctx'>   KBUILD_CPPFLAGS += -DCC_USING_PATCHABLE_FUNCTION_ENTRY</div><div class='ctx'>   CC_FLAGS_FTRACE := -fpatchable-function-entry=2</div><div class='ctx'> endif</div><div class='ctx'> </div><div class='del'>-# Default value</div><div class='del'>-head-y		:= arch/arm64/kernel/head.o</div><div class='del'>-</div><div class='del'>-# The byte offset of the kernel image in RAM from the start of RAM.</div><div class='del'>-ifeq ($(CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET), y)</div><div class='del'>-TEXT_OFFSET := $(shell awk "BEGIN {srand(); printf \"0x%06x\n\", \</div><div class='del'>-		 int(2 * 1024 * 1024 / (2 ^ $(CONFIG_ARM64_PAGE_SHIFT)) * \</div><div class='del'>-		 rand()) * (2 ^ $(CONFIG_ARM64_PAGE_SHIFT))}")</div><div class='del'>-else</div><div class='del'>-TEXT_OFFSET := 0x00080000</div><div class='del'>-endif</div><div class='del'>-</div><div class='ctx'> ifeq ($(CONFIG_KASAN_SW_TAGS), y)</div><div class='ctx'> KASAN_SHADOW_SCALE_SHIFT := 4</div><div class='del'>-else</div><div class='add'>+else ifeq ($(CONFIG_KASAN_GENERIC), y)</div><div class='ctx'> KASAN_SHADOW_SCALE_SHIFT := 3</div><div class='ctx'> endif</div><div class='ctx'> </div><div class='hunk'>@@ -131,35 +155,45 @@ KBUILD_CFLAGS += -DKASAN_SHADOW_SCALE_SHIFT=$(KASAN_SHADOW_SCALE_SHIFT)</div><div class='ctx'> KBUILD_CPPFLAGS += -DKASAN_SHADOW_SCALE_SHIFT=$(KASAN_SHADOW_SCALE_SHIFT)</div><div class='ctx'> KBUILD_AFLAGS += -DKASAN_SHADOW_SCALE_SHIFT=$(KASAN_SHADOW_SCALE_SHIFT)</div><div class='ctx'> </div><div class='del'>-export	TEXT_OFFSET GZFLAGS</div><div class='del'>-</div><div class='del'>-core-y		+= arch/arm64/</div><div class='ctx'> libs-y		:= arch/arm64/lib/ $(libs-y)</div><div class='del'>-core-$(CONFIG_EFI_STUB) += $(objtree)/drivers/firmware/efi/libstub/lib.a</div><div class='add'>+libs-$(CONFIG_EFI_STUB) += $(objtree)/drivers/firmware/efi/libstub/lib.a</div><div class='ctx'> </div><div class='ctx'> # Default target when executing plain make</div><div class='ctx'> boot		:= arch/arm64/boot</div><div class='add'>+</div><div class='add'>+BOOT_TARGETS	:= Image vmlinuz.efi image.fit</div><div class='add'>+</div><div class='add'>+PHONY += $(BOOT_TARGETS)</div><div class='add'>+</div><div class='add'>+ifeq ($(CONFIG_EFI_ZBOOT),)</div><div class='ctx'> KBUILD_IMAGE	:= $(boot)/Image.gz</div><div class='add'>+else</div><div class='add'>+KBUILD_IMAGE	:= $(boot)/vmlinuz.efi</div><div class='add'>+endif</div><div class='ctx'> </div><div class='del'>-all:	Image.gz</div><div class='add'>+all:	$(notdir $(KBUILD_IMAGE))</div><div class='ctx'> </div><div class='add'>+image.fit: dtbs</div><div class='ctx'> </div><div class='del'>-Image: vmlinux</div><div class='add'>+vmlinuz.efi image.fit: Image</div><div class='add'>+$(BOOT_TARGETS): vmlinux</div><div class='ctx'> 	$(Q)$(MAKE) $(build)=$(boot) $(boot)/$@</div><div class='ctx'> </div><div class='ctx'> Image.%: Image</div><div class='ctx'> 	$(Q)$(MAKE) $(build)=$(boot) $(boot)/$@</div><div class='ctx'> </div><div class='del'>-zinstall install:</div><div class='del'>-	$(Q)$(MAKE) $(build)=$(boot) $@</div><div class='add'>+ifeq ($(CONFIG_COMPRESSED_INSTALL),y)</div><div class='add'>+ DEFAULT_KBUILD_IMAGE = $(KBUILD_IMAGE)</div><div class='add'>+else</div><div class='add'>+ DEFAULT_KBUILD_IMAGE = $(boot)/Image</div><div class='add'>+endif</div><div class='ctx'> </div><div class='del'>-PHONY += vdso_install</div><div class='del'>-vdso_install:</div><div class='del'>-	$(Q)$(MAKE) $(build)=arch/arm64/kernel/vdso $@</div><div class='add'>+install: KBUILD_IMAGE := $(DEFAULT_KBUILD_IMAGE)</div><div class='add'>+install zinstall:</div><div class='add'>+	$(call cmd,install)</div><div class='ctx'> </div><div class='del'>-# We use MRPROPER_FILES and CLEAN_FILES now</div><div class='del'>-archclean:</div><div class='del'>-	$(Q)$(MAKE) $(clean)=$(boot)</div><div class='add'>+archprepare:</div><div class='add'>+	$(Q)$(MAKE) $(build)=arch/arm64/tools kapi</div><div class='ctx'> </div><div class='ctx'> ifeq ($(KBUILD_EXTMOD),)</div><div class='ctx'> # We need to generate vdso-offsets.h before compiling certain files in kernel/.</div><div class='hunk'>@@ -170,16 +204,28 @@ ifeq ($(KBUILD_EXTMOD),)</div><div class='ctx'> # this hack.</div><div class='ctx'> prepare: vdso_prepare</div><div class='ctx'> vdso_prepare: prepare0</div><div class='del'>-	$(Q)$(MAKE) $(build)=arch/arm64/kernel/vdso include/generated/vdso-offsets.h</div><div class='del'>-	$(if $(CONFIG_COMPAT_VDSO),$(Q)$(MAKE) \</div><div class='del'>-		$(build)=arch/arm64/kernel/vdso32  \</div><div class='del'>-		include/generated/vdso32-offsets.h)</div><div class='add'>+	$(Q)$(MAKE) $(build)=arch/arm64/kernel/vdso \</div><div class='add'>+	include/generated/vdso-offsets.h arch/arm64/kernel/vdso/vdso.so</div><div class='add'>+ifdef CONFIG_COMPAT_VDSO</div><div class='add'>+	$(Q)$(MAKE) $(build)=arch/arm64/kernel/vdso32 \</div><div class='add'>+	arch/arm64/kernel/vdso32/vdso.so</div><div class='add'>+endif</div><div class='ctx'> endif</div><div class='ctx'> </div><div class='add'>+vdso-install-y				+= arch/arm64/kernel/vdso/vdso.so.dbg</div><div class='add'>+vdso-install-$(CONFIG_COMPAT_VDSO)	+= arch/arm64/kernel/vdso32/vdso32.so.dbg</div><div class='add'>+</div><div class='add'>+include $(srctree)/scripts/Makefile.defconf</div><div class='add'>+</div><div class='add'>+PHONY += virtconfig</div><div class='add'>+virtconfig:</div><div class='add'>+	$(call merge_into_defconfig_override,defconfig,virt)</div><div class='add'>+</div><div class='ctx'> define archhelp</div><div class='ctx'>   echo  '* Image.gz      - Compressed kernel image (arch/$(ARCH)/boot/Image.gz)'</div><div class='ctx'>   echo  '  Image         - Uncompressed kernel image (arch/$(ARCH)/boot/Image)'</div><div class='del'>-  echo  '  install       - Install uncompressed kernel'</div><div class='add'>+  echo  '  image.fit     - Flat Image Tree (arch/$(ARCH)/boot/image.fit)'</div><div class='add'>+  echo  '  install       - Install kernel (compressed if COMPRESSED_INSTALL set)'</div><div class='ctx'>   echo  '  zinstall      - Install compressed kernel'</div><div class='ctx'>   echo  '                  Install using (your) ~/bin/installkernel or'</div><div class='ctx'>   echo  '                  (distribution) /sbin/installkernel or'</div><div class='head'>diff --git a/arch/arm64/boot/.gitignore b/arch/arm64/boot/.gitignore<br/>index 9a7a9009d43a..abaae9de1bdd 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/.gitignore?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/.gitignore</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/.gitignore?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/.gitignore</a></div><div class='hunk'>@@ -1,3 +1,5 @@</div><div class='ctx'> # SPDX-License-Identifier: GPL-2.0-only</div><div class='ctx'> Image</div><div class='ctx'> Image.gz</div><div class='add'>+vmlinuz*</div><div class='add'>+image.fit</div><div class='head'>diff --git a/arch/arm64/boot/Makefile b/arch/arm64/boot/Makefile<br/>index cd3414898d10..b5a08333bc57 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/Makefile?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/Makefile</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/Makefile</a></div><div class='hunk'>@@ -16,7 +16,8 @@</div><div class='ctx'> </div><div class='ctx'> OBJCOPYFLAGS_Image :=-O binary -R .note -R .note.gnu.build-id -R .comment -S</div><div class='ctx'> </div><div class='del'>-targets := Image Image.bz2 Image.gz Image.lz4 Image.lzma Image.lzo</div><div class='add'>+targets := Image Image.bz2 Image.gz Image.lz4 Image.lzma Image.lzo \</div><div class='add'>+	Image.zst Image.xz image.fit</div><div class='ctx'> </div><div class='ctx'> $(obj)/Image: vmlinux FORCE</div><div class='ctx'> 	$(call if_changed,objcopy)</div><div class='hunk'>@@ -36,10 +37,21 @@ $(obj)/Image.lzma: $(obj)/Image FORCE</div><div class='ctx'> $(obj)/Image.lzo: $(obj)/Image FORCE</div><div class='ctx'> 	$(call if_changed,lzo)</div><div class='ctx'> </div><div class='del'>-install:</div><div class='del'>-	$(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \</div><div class='del'>-	$(obj)/Image System.map "$(INSTALL_PATH)"</div><div class='add'>+$(obj)/Image.zst: $(obj)/Image FORCE</div><div class='add'>+	$(call if_changed,zstd)</div><div class='ctx'> </div><div class='del'>-zinstall:</div><div class='del'>-	$(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \</div><div class='del'>-	$(obj)/Image.gz System.map "$(INSTALL_PATH)"</div><div class='add'>+$(obj)/Image.xz: $(obj)/Image FORCE</div><div class='add'>+	$(call if_changed,xzkern)</div><div class='add'>+</div><div class='add'>+$(obj)/image.fit: $(obj)/Image $(obj)/dts/dtbs-list FORCE</div><div class='add'>+	$(call if_changed,fit)</div><div class='add'>+</div><div class='add'>+EFI_ZBOOT_PAYLOAD	:= Image</div><div class='add'>+EFI_ZBOOT_BFD_TARGET	:= elf64-littleaarch64</div><div class='add'>+EFI_ZBOOT_MACH_TYPE	:= ARM64</div><div class='add'>+EFI_ZBOOT_FORWARD_CFI	:= $(CONFIG_ARM64_BTI_KERNEL)</div><div class='add'>+</div><div class='add'>+EFI_ZBOOT_OBJCOPY_FLAGS	= --add-symbol zboot_code_size=0x$$( \</div><div class='add'>+				$(NM) vmlinux|grep _kernel_codesize|cut -d' ' -f1)</div><div class='add'>+</div><div class='add'>+include $(srctree)/drivers/firmware/efi/libstub/Makefile.zboot</div><div class='head'>diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile<br/>index f19b762c008d..98ec8f1b76e4 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/Makefile?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/Makefile</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/Makefile</a></div><div class='hunk'>@@ -1,15 +1,21 @@</div><div class='ctx'> # SPDX-License-Identifier: GPL-2.0</div><div class='ctx'> subdir-y += actions</div><div class='del'>-subdir-y += al</div><div class='add'>+subdir-y += airoha</div><div class='ctx'> subdir-y += allwinner</div><div class='ctx'> subdir-y += altera</div><div class='add'>+subdir-y += amazon</div><div class='ctx'> subdir-y += amd</div><div class='ctx'> subdir-y += amlogic</div><div class='ctx'> subdir-y += apm</div><div class='add'>+subdir-y += apple</div><div class='ctx'> subdir-y += arm</div><div class='add'>+subdir-y += axiado</div><div class='ctx'> subdir-y += bitmain</div><div class='add'>+subdir-y += blaize</div><div class='ctx'> subdir-y += broadcom</div><div class='add'>+subdir-y += bst</div><div class='ctx'> subdir-y += cavium</div><div class='add'>+subdir-y += cix</div><div class='ctx'> subdir-y += exynos</div><div class='ctx'> subdir-y += freescale</div><div class='ctx'> subdir-y += hisilicon</div><div class='hunk'>@@ -17,14 +23,19 @@ subdir-y += intel</div><div class='ctx'> subdir-y += lg</div><div class='ctx'> subdir-y += marvell</div><div class='ctx'> subdir-y += mediatek</div><div class='add'>+subdir-y += microchip</div><div class='add'>+subdir-y += nuvoton</div><div class='ctx'> subdir-y += nvidia</div><div class='ctx'> subdir-y += qcom</div><div class='ctx'> subdir-y += realtek</div><div class='ctx'> subdir-y += renesas</div><div class='ctx'> subdir-y += rockchip</div><div class='ctx'> subdir-y += socionext</div><div class='add'>+subdir-y += sophgo</div><div class='ctx'> subdir-y += sprd</div><div class='add'>+subdir-y += st</div><div class='ctx'> subdir-y += synaptics</div><div class='add'>+subdir-y += tesla</div><div class='ctx'> subdir-y += ti</div><div class='add'>+subdir-y += toshiba</div><div class='ctx'> subdir-y += xilinx</div><div class='del'>-subdir-y += zte</div><div class='head'>diff --git a/arch/arm64/boot/dts/actions/s700-cubieboard7.dts b/arch/arm64/boot/dts/actions/s700-cubieboard7.dts<br/>index 63e375cd9eb4..bd54b5165129 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/actions/s700-cubieboard7.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/actions/s700-cubieboard7.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/actions/s700-cubieboard7.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/actions/s700-cubieboard7.dts</a></div><div class='hunk'>@@ -24,7 +24,7 @@</div><div class='ctx'> 		reg = &lt;0x0 0x0 0x0 0x80000000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	memory@1,e0000000 {</div><div class='add'>+	memory@1e0000000 {</div><div class='ctx'> 		device_type = "memory";</div><div class='ctx'> 		reg = &lt;0x1 0xe0000000 0x0 0x0&gt;;</div><div class='ctx'> 	};</div><div class='head'>diff --git a/arch/arm64/boot/dts/actions/s700.dtsi b/arch/arm64/boot/dts/actions/s700.dtsi<br/>index 2006ad5424fa..2c78caebf515 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/actions/s700.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/actions/s700.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/actions/s700.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/actions/s700.dtsi</a></div><div class='hunk'>@@ -5,6 +5,7 @@</div><div class='ctx'> </div><div class='ctx'> #include &lt;dt-bindings/clock/actions,s700-cmu.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/power/owl-s700-powergate.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/reset/actions,s700-reset.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='hunk'>@@ -231,7 +232,7 @@</div><div class='ctx'> </div><div class='ctx'> 		pinctrl: pinctrl@e01b0000 {</div><div class='ctx'> 			compatible = "actions,s700-pinctrl";</div><div class='del'>-			reg = &lt;0x0 0xe01b0000 0x0 0x1000&gt;;</div><div class='add'>+			reg = &lt;0x0 0xe01b0000 0x0 0x100&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;cmu CLK_GPIO&gt;;</div><div class='ctx'> 			gpio-controller;</div><div class='ctx'> 			gpio-ranges = &lt;&amp;pinctrl 0 0 136&gt;;</div><div class='hunk'>@@ -244,5 +245,19 @@</div><div class='ctx'> 				     &lt;GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 				     &lt;GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		};</div><div class='add'>+</div><div class='add'>+		dma: dma-controller@e0230000 {</div><div class='add'>+			compatible = "actions,s700-dma";</div><div class='add'>+			reg = &lt;0x0 0xe0230000 0x0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+			dma-channels = &lt;10&gt;;</div><div class='add'>+			dma-requests = &lt;44&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu CLK_DMAC&gt;;</div><div class='add'>+			power-domains = &lt;&amp;sps S700_PD_DMA&gt;;</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/airoha/Makefile b/arch/arm64/boot/dts/airoha/Makefile<br/>new file mode 100644<br/>index 000000000000..ebea112ce1d7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/airoha/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/airoha/Makefile</a></div><div class='hunk'>@@ -0,0 +1,2 @@</div><div class='add'>+# SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+dtb-$(CONFIG_ARCH_AIROHA) += en7581-evb.dtb</div><div class='head'>diff --git a/arch/arm64/boot/dts/airoha/en7581-evb.dts b/arch/arm64/boot/dts/airoha/en7581-evb.dts<br/>new file mode 100644<br/>index 000000000000..dae9968a4ff6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/airoha/en7581-evb.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/airoha/en7581-evb.dts</a></div><div class='hunk'>@@ -0,0 +1,108 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+/* Bootloader installs ATF here */</div><div class='add'>+/memreserve/ 0x80000000 0x200000;</div><div class='add'>+</div><div class='add'>+#include "en7581.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Airoha EN7581 Evaluation Board";</div><div class='add'>+	compatible = "airoha,en7581-evb", "airoha,en7581";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+		linux,usable-memory-range = &lt;0x0 0x80200000 0x0 0x1fe00000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@80000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x80000000 0x2 0x00000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi_nand {</div><div class='add'>+	partitions {</div><div class='add'>+		compatible = "fixed-partitions";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		bootloader@0 {</div><div class='add'>+			label = "bootloader";</div><div class='add'>+			reg = &lt;0x00000000 0x00080000&gt;;</div><div class='add'>+			read-only;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		art@200000 {</div><div class='add'>+			label = "art";</div><div class='add'>+			reg = &lt;0x00200000 0x00400000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tclinux@600000 {</div><div class='add'>+			label = "tclinux";</div><div class='add'>+			reg = &lt;0x00600000 0x03200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tclinux_slave@3800000 {</div><div class='add'>+			label = "tclinux_alt";</div><div class='add'>+			reg = &lt;0x03800000 0x03200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rootfs_data@6a00000 {</div><div class='add'>+			label = "rootfs_data";</div><div class='add'>+			reg = &lt;0x06a00000 0x01400000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		reserved_bmt@7e00000 {</div><div class='add'>+			label = "reserved_bmt";</div><div class='add'>+			reg = &lt;0x07e00000 0x00200000&gt;;</div><div class='add'>+			read-only;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;en7581_pinctrl {</div><div class='add'>+	gpio-ranges = &lt;&amp;en7581_pinctrl 0 13 47&gt;;</div><div class='add'>+</div><div class='add'>+	pcie0_rst_pins: pcie0-rst-pins {</div><div class='add'>+		conf {</div><div class='add'>+			pins = "pcie_reset0";</div><div class='add'>+			drive-open-drain = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie1_rst_pins: pcie1-rst-pins {</div><div class='add'>+		conf {</div><div class='add'>+			pins = "pcie_reset1";</div><div class='add'>+			drive-open-drain = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pcie0_rst_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pcie1_rst_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eth {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gdm1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi<br/>new file mode 100644<br/>index 000000000000..ff6908a76e8e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/airoha/en7581.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/airoha/en7581.dtsi</a></div><div class='hunk'>@@ -0,0 +1,399 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/en7523-clk.h&gt;</div><div class='add'>+#include &lt;dt-bindings/reset/airoha,en7581-reset.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		npu-binary@84000000 {</div><div class='add'>+			no-map;</div><div class='add'>+			reg = &lt;0x0 0x84000000 0x0 0xa00000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		npu-flag@84b0000 {</div><div class='add'>+			no-map;</div><div class='add'>+			reg = &lt;0x0 0x84b00000 0x0 0x100000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		npu-pkt@85000000 {</div><div class='add'>+			no-map;</div><div class='add'>+			reg = &lt;0x0 0x85000000 0x0 0x1a00000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		npu-phyaddr@86b00000 {</div><div class='add'>+			no-map;</div><div class='add'>+			reg = &lt;0x0 0x86b00000 0x0 0x100000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		npu-rxdesc@86d00000 {</div><div class='add'>+			no-map;</div><div class='add'>+			reg = &lt;0x0 0x86d00000 0x0 0x100000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-1.0";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu-map {</div><div class='add'>+			cluster0 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu2&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu3&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clock-frequency = &lt;80000000&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@1 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x1&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clock-frequency = &lt;80000000&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@2 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x2&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clock-frequency = &lt;80000000&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@3 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x3&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clock-frequency = &lt;80000000&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2: l2-cache {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-size = &lt;0x80000&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk20m: clock-20000000 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;20000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@9000000 {</div><div class='add'>+			compatible = "arm,gic-v3";</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			reg = &lt;0x0 0x09000000 0x0 0x20000&gt;,</div><div class='add'>+			      &lt;0x0 0x09080000 0x0 0x80000&gt;,</div><div class='add'>+			      &lt;0x0 0x09400000 0x0 0x2000&gt;,</div><div class='add'>+			      &lt;0x0 0x09500000 0x0 0x2000&gt;,</div><div class='add'>+			      &lt;0x0 0x09600000 0x0 0x20000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi@1fa10000 {</div><div class='add'>+			compatible = "airoha,en7581-snand";</div><div class='add'>+			reg = &lt;0x0 0x1fa10000 0x0 0x140&gt;,</div><div class='add'>+			      &lt;0x0 0x1fa11000 0x0 0x160&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;scuclk EN7523_CLK_SPI&gt;;</div><div class='add'>+			clock-names = "spi";</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			spi_nand: nand@0 {</div><div class='add'>+				compatible = "spi-nand";</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				spi-max-frequency = &lt;50000000&gt;;</div><div class='add'>+				spi-tx-bus-width = &lt;1&gt;;</div><div class='add'>+				spi-rx-bus-width = &lt;2&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		scuclk: clock-controller@1fb00000 {</div><div class='add'>+			compatible = "airoha,en7581-scu";</div><div class='add'>+			reg = &lt;0x0 0x1fb00000 0x0 0x970&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pbus_csr: syscon@1fbe3400 {</div><div class='add'>+			compatible = "airoha,en7581-pbus-csr", "syscon";</div><div class='add'>+			reg = &lt;0x0 0x1fbe3400 0x0 0xff&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pciephy: phy@1fa5a000 {</div><div class='add'>+			compatible = "airoha,en7581-pcie-phy";</div><div class='add'>+			reg = &lt;0x0 0x1fa5a000 0x0 0xfff&gt;,</div><div class='add'>+			      &lt;0x0 0x1fa5b000 0x0 0xfff&gt;,</div><div class='add'>+			      &lt;0x0 0x1fa5c000 0x0 0xfff&gt;,</div><div class='add'>+			      &lt;0x0 0x1fc10044 0x0 0x4&gt;,</div><div class='add'>+			      &lt;0x0 0x1fc30044 0x0 0x4&gt;,</div><div class='add'>+			      &lt;0x0 0x1fc15030 0x0 0x104&gt;;</div><div class='add'>+			reg-names = "csr-2l", "pma0", "pma1",</div><div class='add'>+				    "p0-xr-dtime", "p1-xr-dtime",</div><div class='add'>+				    "rx-aeq";</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie0: pcie@1fc00000 {</div><div class='add'>+			compatible = "airoha,en7581-pcie";</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			linux,pci-domain = &lt;0&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			reg = &lt;0x0 0x1fc00000 0x0 0x1670&gt;;</div><div class='add'>+			reg-names = "pcie-mac";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;scuclk EN7523_CLK_PCIE&gt;;</div><div class='add'>+			clock-names = "sys-ck";</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;pciephy&gt;;</div><div class='add'>+			phy-names = "pcie-phy";</div><div class='add'>+</div><div class='add'>+			ranges = &lt;0x02000000 0 0x20000000 0x0 0x20000000 0 0x4000000&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;scuclk EN7581_PCIE0_RST&gt;,</div><div class='add'>+				 &lt;&amp;scuclk EN7581_PCIE1_RST&gt;,</div><div class='add'>+				 &lt;&amp;scuclk EN7581_PCIE2_RST&gt;;</div><div class='add'>+			reset-names = "phy-lane0", "phy-lane1", "phy-lane2";</div><div class='add'>+</div><div class='add'>+			mediatek,pbus-csr = &lt;&amp;pbus_csr 0x0 0x4&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			bus-range = &lt;0x00 0xff&gt;;</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;pcie_intc0 0&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;pcie_intc0 1&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;pcie_intc0 2&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;pcie_intc0 3&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcie_intc0: interrupt-controller {</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#address-cells = &lt;0&gt;;</div><div class='add'>+				#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie1: pcie@1fc20000 {</div><div class='add'>+			compatible = "airoha,en7581-pcie";</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			linux,pci-domain = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			reg = &lt;0x0 0x1fc20000 0x0 0x1670&gt;;</div><div class='add'>+			reg-names = "pcie-mac";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;scuclk EN7523_CLK_PCIE&gt;;</div><div class='add'>+			clock-names = "sys-ck";</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;pciephy&gt;;</div><div class='add'>+			phy-names = "pcie-phy";</div><div class='add'>+</div><div class='add'>+			ranges = &lt;0x02000000 0 0x24000000 0x0 0x24000000 0 0x4000000&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;scuclk EN7581_PCIE0_RST&gt;,</div><div class='add'>+				 &lt;&amp;scuclk EN7581_PCIE1_RST&gt;,</div><div class='add'>+				 &lt;&amp;scuclk EN7581_PCIE2_RST&gt;;</div><div class='add'>+			reset-names = "phy-lane0", "phy-lane1", "phy-lane2";</div><div class='add'>+</div><div class='add'>+			mediatek,pbus-csr = &lt;&amp;pbus_csr 0x8 0xc&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			bus-range = &lt;0x00 0xff&gt;;</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;pcie_intc1 0&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;pcie_intc1 1&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;pcie_intc1 2&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;pcie_intc1 3&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcie_intc1: interrupt-controller {</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#address-cells = &lt;0&gt;;</div><div class='add'>+				#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart1: serial@1fbf0000 {</div><div class='add'>+			compatible = "ns16550";</div><div class='add'>+			reg = &lt;0x0 0x1fbf0000 0x0 0x30&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+			reg-shift = &lt;2&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clock-frequency = &lt;1843200&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rng@1faa1000 {</div><div class='add'>+			compatible = "airoha,en7581-trng";</div><div class='add'>+			reg = &lt;0x0 0x1faa1000 0x0 0xc04&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		system-controller@1fbf0200 {</div><div class='add'>+			compatible = "airoha,en7581-gpio-sysctl", "syscon",</div><div class='add'>+				     "simple-mfd";</div><div class='add'>+			reg = &lt;0x0 0x1fbf0200 0x0 0xc0&gt;;</div><div class='add'>+</div><div class='add'>+			en7581_pinctrl: pinctrl {</div><div class='add'>+				compatible = "airoha,en7581-pinctrl";</div><div class='add'>+</div><div class='add'>+				interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				gpio-controller;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c0: i2c@1fbf8000 {</div><div class='add'>+			compatible = "mediatek,mt7621-i2c";</div><div class='add'>+			reg = &lt;0x0 0x1fbf8000 0x0 0x100&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;scuclk EN7581_I2C2_RST&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;clk20m&gt;;</div><div class='add'>+			clock-frequency = &lt;100000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c1: i2c@1fbf8100 {</div><div class='add'>+			compatible = "mediatek,mt7621-i2c";</div><div class='add'>+			reg = &lt;0x0 0x1fbf8100 0x0 0x100&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;scuclk EN7581_I2C_MASTER_RST&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;clk20m&gt;;</div><div class='add'>+			clock-frequency = &lt;100000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		eth: ethernet@1fb50000 {</div><div class='add'>+			compatible = "airoha,en7581-eth";</div><div class='add'>+			reg = &lt;0 0x1fb50000 0 0x2600&gt;,</div><div class='add'>+			      &lt;0 0x1fb54000 0 0x2000&gt;,</div><div class='add'>+			      &lt;0 0x1fb56000 0 0x2000&gt;;</div><div class='add'>+			reg-names = "fe", "qdma0", "qdma1";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;scuclk EN7581_FE_RST&gt;,</div><div class='add'>+				 &lt;&amp;scuclk EN7581_FE_PDMA_RST&gt;,</div><div class='add'>+				 &lt;&amp;scuclk EN7581_FE_QDMA_RST&gt;,</div><div class='add'>+				 &lt;&amp;scuclk EN7581_XSI_MAC_RST&gt;,</div><div class='add'>+				 &lt;&amp;scuclk EN7581_DUAL_HSI0_MAC_RST&gt;,</div><div class='add'>+				 &lt;&amp;scuclk EN7581_DUAL_HSI1_MAC_RST&gt;,</div><div class='add'>+				 &lt;&amp;scuclk EN7581_HSI_MAC_RST&gt;,</div><div class='add'>+				 &lt;&amp;scuclk EN7581_XFP_MAC_RST&gt;;</div><div class='add'>+			reset-names = "fe", "pdma", "qdma",</div><div class='add'>+				      "xsi-mac", "hsi0-mac", "hsi1-mac",</div><div class='add'>+				      "hsi-mac", "xfp-mac";</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			gdm1: ethernet@1 {</div><div class='add'>+				compatible = "airoha,eth-mac";</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				phy-mode = "internal";</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				fixed-link {</div><div class='add'>+					speed = &lt;10000&gt;;</div><div class='add'>+					full-duplex;</div><div class='add'>+					pause;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile<br/>index e4d3cd0ac5bb..2edfa7bf4ab3 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/Makefile?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/Makefile</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/Makefile</a></div><div class='hunk'>@@ -11,9 +11,14 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinebook.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinephone-1.0.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinephone-1.1.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinephone-1.2.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinetab.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinetab-early-adopter.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-teres-i.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h64-remix-mini-pc.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a100-allwinner-perf1.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a133-liontron-h-a133l.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-bananapi-m2-plus.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-bananapi-m2-plus-v1.2.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-emlid-neutis-n5-devboard.dtb</div><div class='hunk'>@@ -22,6 +27,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-libretech-all-h3-it.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-libretech-all-h5-cc.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo2.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-plus2.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-r1s-h5.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-prime.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus.dtb</div><div class='hunk'>@@ -33,3 +39,23 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-one-plus.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64-model-b.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6-mini.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h313-tanix-tx1.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h313-x96q.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-cb1-manta.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-pi.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-x96-mate.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-longanpi-3h.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-orangepi-zero2w.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-orangepi-zero3.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-transpeed-8k618-t.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-yuzukihd-chameleon.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h700-anbernic-rg35xx-2024.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h700-anbernic-rg35xx-h.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h700-anbernic-rg35xx-plus.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h700-anbernic-rg35xx-sp.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_SUNXI) += sun55i-a527-cubie-a5e.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_SUNXI) += sun55i-h728-x96qpro+.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_SUNXI) += sun55i-t527-avaota-a1.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_SUNXI) += sun55i-t527-orangepi-4a.dtb</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/axp803.dtsi b/arch/arm64/boot/dts/allwinner/axp803.dtsi<br/>index 10e9186a76bf..a6b4b87f185d 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/axp803.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/axp803.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/axp803.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/axp803.dtsi</a></div><div class='hunk'>@@ -10,7 +10,7 @@</div><div class='ctx'> 	interrupt-controller;</div><div class='ctx'> 	#interrupt-cells = &lt;1&gt;;</div><div class='ctx'> </div><div class='del'>-	ac_power_supply: ac-power-supply {</div><div class='add'>+	ac_power_supply: ac-power {</div><div class='ctx'> 		compatible = "x-powers,axp803-ac-power-supply",</div><div class='ctx'> 			     "x-powers,axp813-ac-power-supply";</div><div class='ctx'> 		status = "disabled";</div><div class='hunk'>@@ -25,19 +25,9 @@</div><div class='ctx'> 		compatible = "x-powers,axp803-gpio", "x-powers,axp813-gpio";</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='del'>-</div><div class='del'>-		gpio0_ldo: gpio0-ldo {</div><div class='del'>-			pins = "GPIO0";</div><div class='del'>-			function = "ldo";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		gpio1_ldo: gpio1-ldo {</div><div class='del'>-			pins = "GPIO1";</div><div class='del'>-			function = "ldo";</div><div class='del'>-		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	battery_power_supply: battery-power-supply {</div><div class='add'>+	battery_power_supply: battery-power {</div><div class='ctx'> 		compatible = "x-powers,axp803-battery-power-supply",</div><div class='ctx'> 			     "x-powers,axp813-battery-power-supply";</div><div class='ctx'> 		status = "disabled";</div><div class='hunk'>@@ -147,7 +137,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	usb_power_supply: usb-power-supply {</div><div class='add'>+	usb_power_supply: usb-power {</div><div class='ctx'> 		compatible = "x-powers,axp803-usb-power-supply",</div><div class='ctx'> 			     "x-powers,axp813-usb-power-supply";</div><div class='ctx'> 		status = "disabled";</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts<br/>new file mode 100644<br/>index 000000000000..a7e3be0155a8<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts</a></div><div class='hunk'>@@ -0,0 +1,203 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2020 Yangtao Li &lt;frank@allwinnertech.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "sun50i-a100.dtsi"</div><div class='add'>+#include "sun50i-a100-cpu-opp.dtsi"</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+</div><div class='add'>+/{</div><div class='add'>+	model = "Allwinner A100 Perf1";</div><div class='add'>+	compatible = "allwinner,a100-perf1", "allwinner,sun50i-a100";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc0 {</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_dcdc1&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;pio 5 6 GPIO_ACTIVE_LOW&gt;; /* PF6 */</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc2 {</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_dcdc1&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_aldo1&gt;;</div><div class='add'>+	cap-mmc-hw-reset;</div><div class='add'>+	non-removable;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_dcdc2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	vcc-pb-supply = &lt;&amp;reg_dcdc1&gt;;</div><div class='add'>+	vcc-pc-supply = &lt;&amp;reg_eldo1&gt;;</div><div class='add'>+	vcc-pd-supply = &lt;&amp;reg_dcdc1&gt;;</div><div class='add'>+	vcc-pe-supply = &lt;&amp;reg_dldo2&gt;;</div><div class='add'>+	vcc-pf-supply = &lt;&amp;reg_dcdc1&gt;;</div><div class='add'>+	vcc-pg-supply = &lt;&amp;reg_dldo1&gt;;</div><div class='add'>+	vcc-ph-supply = &lt;&amp;reg_dcdc1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;r_pio {</div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: We can't add that supply for now since it would</div><div class='add'>+	 * create a circular dependency between pinctrl, the regulator</div><div class='add'>+	 * and the RSB Bus.</div><div class='add'>+	 *</div><div class='add'>+	 * vcc-pl-supply = &lt;&amp;reg_aldo3&gt;;</div><div class='add'>+	 */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;r_i2c0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	axp803: pmic@34 {</div><div class='add'>+		compatible = "x-powers,axp803";</div><div class='add'>+		reg = &lt;0x34&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;r_intc&gt;;</div><div class='add'>+		interrupts = &lt;0 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include "axp803.dtsi"</div><div class='add'>+</div><div class='add'>+&amp;ac_power_supply {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_aldo1 {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+	regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	regulator-name = "vcc-pll-avcc";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_aldo2 {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+	regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	regulator-name = "vcc-dram-1";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_aldo3 {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+	regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	regulator-name = "vcc-usb-pl";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_dcdc1 {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+	regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	regulator-name = "vcc-io-usb-pd-emmc-nand-card";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_dcdc2 {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: update min and max before support dvfs.</div><div class='add'>+	 */</div><div class='add'>+	regulator-min-microvolt = &lt;500000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+	regulator-name = "vdd-cpux";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* DCDC3 is polyphased with DCDC2 */</div><div class='add'>+</div><div class='add'>+&amp;reg_dcdc4 {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+	regulator-min-microvolt = &lt;950000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;950000&gt;;</div><div class='add'>+	regulator-name = "vdd-sys-usb-dram";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_dcdc5 {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+	regulator-min-microvolt = &lt;1500000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;1500000&gt;;</div><div class='add'>+	regulator-name = "vcc-dram-2";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_dldo1 {</div><div class='add'>+	regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	regulator-name = "vcc-pg-dcxo-wifi";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_dldo2 {</div><div class='add'>+	regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+	regulator-name = "vcc-pe-csi";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_dldo3 {</div><div class='add'>+	regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	regulator-name = "ldo-avdd-csi";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_dldo4 {</div><div class='add'>+	regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+	regulator-name = "avcc-csi";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_eldo1 {</div><div class='add'>+	regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	regulator-name = "vcc-pc-lvds-csi-efuse-emmc-nand";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_eldo2 {</div><div class='add'>+	regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	regulator-name = "dvdd-csi";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_eldo3 {</div><div class='add'>+	regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	regulator-name = "vcc-mipi-lcd";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_fldo1 {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+	regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;900000&gt;;</div><div class='add'>+	regulator-name = "vdd-cpus-usb";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_ldo_io0 {</div><div class='add'>+	regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	regulator-name = "vcc-ctp";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_drivevbus {</div><div class='add'>+	regulator-name = "usb0-vbus";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart0_pb_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi<br/>new file mode 100644<br/>index 000000000000..c6a2efa037dc<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi</a></div><div class='hunk'>@@ -0,0 +1,90 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+// Copyright (c) 2020 Yangtao Li &lt;frank@allwinnertech.com&gt;</div><div class='add'>+// Copyright (c) 2020 ShuoSheng Huang &lt;huangshuosheng@allwinnertech.com&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	cpu_opp_table: opp-table-cpu {</div><div class='add'>+		compatible = "allwinner,sun50i-a100-operating-points";</div><div class='add'>+		nvmem-cells = &lt;&amp;cpu_speed_grade&gt;;</div><div class='add'>+		opp-shared;</div><div class='add'>+</div><div class='add'>+		opp-408000000 {</div><div class='add'>+			clock-latency-ns = &lt;244144&gt;; /* 8 32k periods */</div><div class='add'>+			opp-hz = /bits/ 64 &lt;408000000&gt;;</div><div class='add'>+</div><div class='add'>+			opp-microvolt-speed0 = &lt;900000&gt;;</div><div class='add'>+			opp-microvolt-speed1 = &lt;900000&gt;;</div><div class='add'>+			opp-microvolt-speed2 = &lt;900000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-600000000 {</div><div class='add'>+			clock-latency-ns = &lt;244144&gt;; /* 8 32k periods */</div><div class='add'>+			opp-hz = /bits/ 64 &lt;600000000&gt;;</div><div class='add'>+</div><div class='add'>+			opp-microvolt-speed0 = &lt;900000&gt;;</div><div class='add'>+			opp-microvolt-speed1 = &lt;900000&gt;;</div><div class='add'>+			opp-microvolt-speed2 = &lt;900000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-816000000 {</div><div class='add'>+			clock-latency-ns = &lt;244144&gt;; /* 8 32k periods */</div><div class='add'>+			opp-hz = /bits/ 64 &lt;816000000&gt;;</div><div class='add'>+</div><div class='add'>+			opp-microvolt-speed0 = &lt;940000&gt;;</div><div class='add'>+			opp-microvolt-speed1 = &lt;900000&gt;;</div><div class='add'>+			opp-microvolt-speed2 = &lt;900000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1080000000 {</div><div class='add'>+			clock-latency-ns = &lt;244144&gt;; /* 8 32k periods */</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1080000000&gt;;</div><div class='add'>+</div><div class='add'>+			opp-microvolt-speed0 = &lt;1020000&gt;;</div><div class='add'>+			opp-microvolt-speed1 = &lt;980000&gt;;</div><div class='add'>+			opp-microvolt-speed2 = &lt;950000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1200000000 {</div><div class='add'>+			clock-latency-ns = &lt;244144&gt;; /* 8 32k periods */</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1200000000&gt;;</div><div class='add'>+</div><div class='add'>+			opp-microvolt-speed0 = &lt;1100000&gt;;</div><div class='add'>+			opp-microvolt-speed1 = &lt;1020000&gt;;</div><div class='add'>+			opp-microvolt-speed2 = &lt;1000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1320000000 {</div><div class='add'>+			clock-latency-ns = &lt;244144&gt;; /* 8 32k periods */</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1320000000&gt;;</div><div class='add'>+</div><div class='add'>+			opp-microvolt-speed0 = &lt;1160000&gt;;</div><div class='add'>+			opp-microvolt-speed1 = &lt;1060000&gt;;</div><div class='add'>+			opp-microvolt-speed2 = &lt;1030000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1464000000 {</div><div class='add'>+			clock-latency-ns = &lt;244144&gt;; /* 8 32k periods */</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1464000000&gt;;</div><div class='add'>+</div><div class='add'>+			opp-microvolt-speed0 = &lt;1180000&gt;;</div><div class='add'>+			opp-microvolt-speed1 = &lt;1180000&gt;;</div><div class='add'>+			opp-microvolt-speed2 = &lt;1130000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu1 {</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu2 {</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu3 {</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi<br/>new file mode 100644<br/>index 000000000000..bb5f9e4f3d42<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi</a></div><div class='hunk'>@@ -0,0 +1,652 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2020 Yangtao Li &lt;frank@allwinnertech.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/sun50i-a100-ccu.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/sun50i-a100-r-ccu.h&gt;</div><div class='add'>+#include &lt;dt-bindings/reset/sun50i-a100-ccu.h&gt;</div><div class='add'>+#include &lt;dt-bindings/reset/sun50i-a100-r-ccu.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_CPUX&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@1 {</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x1&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_CPUX&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@2 {</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x2&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_CPUX&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@3 {</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x3&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_CPUX&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu {</div><div class='add'>+		compatible = "arm,cortex-a53-pmu";</div><div class='add'>+		interrupts = &lt;GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-affinity = &lt;&amp;cpu0&gt;, &lt;&amp;cpu1&gt;, &lt;&amp;cpu2&gt;, &lt;&amp;cpu3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-1.0";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dcxo24M: dcxo24M-clk {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+		clock-output-names = "dcxo24M";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	iosc: internal-osc-clk {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		clock-frequency = &lt;16000000&gt;;</div><div class='add'>+		clock-accuracy = &lt;300000000&gt;;</div><div class='add'>+		clock-output-names = "iosc";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	osc32k: osc32k-clk {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		clock-frequency = &lt;32768&gt;;</div><div class='add'>+		clock-output-names = "osc32k";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13</div><div class='add'>+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14</div><div class='add'>+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11</div><div class='add'>+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10</div><div class='add'>+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges = &lt;0 0 0 0x3fffffff&gt;;</div><div class='add'>+</div><div class='add'>+		syscon: syscon@3000000 {</div><div class='add'>+			compatible = "allwinner,sun50i-a100-system-control",</div><div class='add'>+				     "allwinner,sun50i-a64-system-control";</div><div class='add'>+			reg = &lt;0x03000000 0x1000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			sram_a1: sram@20000 {</div><div class='add'>+				compatible = "mmio-sram";</div><div class='add'>+				reg = &lt;0x00020000 0x4000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;1&gt;;</div><div class='add'>+				ranges = &lt;0 0x00020000 0x4000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sram_c: sram@24000 {</div><div class='add'>+				compatible = "mmio-sram";</div><div class='add'>+				reg = &lt;0x024000 0x21000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;1&gt;;</div><div class='add'>+				ranges = &lt;0 0x024000 0x21000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sram_a2: sram@100000 {</div><div class='add'>+				compatible = "mmio-sram";</div><div class='add'>+				reg = &lt;0x0100000 0x14000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;1&gt;;</div><div class='add'>+				ranges = &lt;0 0x0100000 0x14000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ccu: clock@3001000 {</div><div class='add'>+			compatible = "allwinner,sun50i-a100-ccu";</div><div class='add'>+			reg = &lt;0x03001000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;dcxo24M&gt;, &lt;&amp;osc32k&gt;, &lt;&amp;iosc&gt;;</div><div class='add'>+			clock-names = "hosc", "losc", "iosc";</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dma: dma-controller@3002000 {</div><div class='add'>+			compatible = "allwinner,sun50i-a100-dma";</div><div class='add'>+			reg = &lt;0x03002000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_DMA&gt;, &lt;&amp;ccu CLK_MBUS_DMA&gt;;</div><div class='add'>+			clock-names = "bus", "mbus";</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_DMA&gt;;</div><div class='add'>+			dma-channels = &lt;8&gt;;</div><div class='add'>+			dma-requests = &lt;52&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@3021000 {</div><div class='add'>+			compatible = "arm,gic-400";</div><div class='add'>+			reg = &lt;0x03021000 0x1000&gt;, &lt;0x03022000 0x2000&gt;,</div><div class='add'>+			      &lt;0x03024000 0x2000&gt;, &lt;0x03026000 0x2000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |</div><div class='add'>+						 IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		efuse@3006000 {</div><div class='add'>+			compatible = "allwinner,sun50i-a100-sid",</div><div class='add'>+				     "allwinner,sun50i-a64-sid";</div><div class='add'>+			reg = &lt;0x03006000 0x1000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			ths_calibration: calib@14 {</div><div class='add'>+				reg = &lt;0x14 8&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cpu_speed_grade: cpu-speed-grade@1c {</div><div class='add'>+				reg = &lt;0x1c 0x2&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		watchdog@30090a0 {</div><div class='add'>+			compatible = "allwinner,sun50i-a100-wdt",</div><div class='add'>+				     "allwinner,sun6i-a31-wdt";</div><div class='add'>+			reg = &lt;0x030090a0 0x20&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;dcxo24M&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pio: pinctrl@300b000 {</div><div class='add'>+			compatible = "allwinner,sun50i-a100-pinctrl";</div><div class='add'>+			reg = &lt;0x0300b000 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_APB1&gt;, &lt;&amp;dcxo24M&gt;, &lt;&amp;osc32k&gt;;</div><div class='add'>+			clock-names = "apb", "hosc", "losc";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;3&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+			mmc0_pins: mmc0-pins {</div><div class='add'>+				pins = "PF0", "PF1", "PF2", "PF3",</div><div class='add'>+				       "PF4", "PF5";</div><div class='add'>+				function = "mmc0";</div><div class='add'>+				drive-strength = &lt;30&gt;;</div><div class='add'>+				bias-pull-up;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/omit-if-no-ref/</div><div class='add'>+			mmc1_pins: mmc1-pins {</div><div class='add'>+				pins = "PG0", "PG1", "PG2", "PG3",</div><div class='add'>+				       "PG4", "PG5";</div><div class='add'>+				function = "mmc1";</div><div class='add'>+				drive-strength = &lt;30&gt;;</div><div class='add'>+				bias-pull-up;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mmc2_pins: mmc2-pins {</div><div class='add'>+				pins = "PC0", "PC1", "PC5", "PC6",</div><div class='add'>+				       "PC8", "PC9", "PC10", "PC11",</div><div class='add'>+				       "PC13", "PC14", "PC15", "PC16";</div><div class='add'>+				function = "mmc2";</div><div class='add'>+				drive-strength = &lt;30&gt;;</div><div class='add'>+				bias-pull-up;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			rgmii0_pins: rgmii0-pins {</div><div class='add'>+				pins = "PH0", "PH1", "PH2", "PH3", "PH4",</div><div class='add'>+				       "PH5", "PH6", "PH7", "PH9", "PH10",</div><div class='add'>+				       "PH14", "PH15", "PH16", "PH17", "PH18";</div><div class='add'>+				function = "emac0";</div><div class='add'>+				drive-strength = &lt;40&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			rmii0_pins: rmii0-pins {</div><div class='add'>+				pins = "PH0", "PH1", "PH2", "PH3", "PH4",</div><div class='add'>+				       "PH5", "PH6", "PH7", "PH9", "PH10";</div><div class='add'>+				function = "emac0";</div><div class='add'>+				drive-strength = &lt;40&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart0_pb_pins: uart0-pb-pins {</div><div class='add'>+				pins = "PB9", "PB10";</div><div class='add'>+				function = "uart0";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmc0: mmc@4020000 {</div><div class='add'>+			compatible = "allwinner,sun50i-a100-mmc";</div><div class='add'>+			reg = &lt;0x04020000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_MMC0&gt;, &lt;&amp;ccu CLK_MMC0&gt;;</div><div class='add'>+			clock-names = "ahb", "mmc";</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_MMC0&gt;;</div><div class='add'>+			reset-names = "ahb";</div><div class='add'>+			interrupts = &lt;GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;mmc0_pins&gt;;</div><div class='add'>+			max-frequency = &lt;150000000&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmc1: mmc@4021000 {</div><div class='add'>+			compatible = "allwinner,sun50i-a100-mmc";</div><div class='add'>+			reg = &lt;0x04021000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_MMC1&gt;, &lt;&amp;ccu CLK_MMC1&gt;;</div><div class='add'>+			clock-names = "ahb", "mmc";</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_MMC1&gt;;</div><div class='add'>+			reset-names = "ahb";</div><div class='add'>+			interrupts = &lt;GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;mmc1_pins&gt;;</div><div class='add'>+			max-frequency = &lt;150000000&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmc2: mmc@4022000 {</div><div class='add'>+			compatible = "allwinner,sun50i-a100-emmc";</div><div class='add'>+			reg = &lt;0x04022000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_MMC2&gt;, &lt;&amp;ccu CLK_MMC2&gt;;</div><div class='add'>+			clock-names = "ahb", "mmc";</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_MMC2&gt;;</div><div class='add'>+			reset-names = "ahb";</div><div class='add'>+			interrupts = &lt;GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;mmc2_pins&gt;;</div><div class='add'>+			max-frequency = &lt;150000000&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart0: serial@5000000 {</div><div class='add'>+			compatible = "snps,dw-apb-uart";</div><div class='add'>+			reg = &lt;0x05000000 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			reg-shift = &lt;2&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_UART0&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_UART0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart1: serial@5000400 {</div><div class='add'>+			compatible = "snps,dw-apb-uart";</div><div class='add'>+			reg = &lt;0x05000400 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			reg-shift = &lt;2&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_UART1&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_UART1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart2: serial@5000800 {</div><div class='add'>+			compatible = "snps,dw-apb-uart";</div><div class='add'>+			reg = &lt;0x05000800 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			reg-shift = &lt;2&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_UART2&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_UART2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart3: serial@5000c00 {</div><div class='add'>+			compatible = "snps,dw-apb-uart";</div><div class='add'>+			reg = &lt;0x05000c00 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			reg-shift = &lt;2&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_UART3&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_UART3&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart4: serial@5001000 {</div><div class='add'>+			compatible = "snps,dw-apb-uart";</div><div class='add'>+			reg = &lt;0x05001000 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			reg-shift = &lt;2&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_UART4&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_UART4&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c0: i2c@5002000 {</div><div class='add'>+			compatible = "allwinner,sun50i-a100-i2c",</div><div class='add'>+				     "allwinner,sun8i-v536-i2c",</div><div class='add'>+				     "allwinner,sun6i-a31-i2c";</div><div class='add'>+			reg = &lt;0x05002000 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_I2C0&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_I2C0&gt;;</div><div class='add'>+			dmas = &lt;&amp;dma 43&gt;, &lt;&amp;dma 43&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c1: i2c@5002400 {</div><div class='add'>+			compatible = "allwinner,sun50i-a100-i2c",</div><div class='add'>+				     "allwinner,sun8i-v536-i2c",</div><div class='add'>+				     "allwinner,sun6i-a31-i2c";</div><div class='add'>+			reg = &lt;0x05002400 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_I2C1&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_I2C1&gt;;</div><div class='add'>+			dmas = &lt;&amp;dma 44&gt;, &lt;&amp;dma 44&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c2: i2c@5002800 {</div><div class='add'>+			compatible = "allwinner,sun50i-a100-i2c",</div><div class='add'>+				     "allwinner,sun8i-v536-i2c",</div><div class='add'>+				     "allwinner,sun6i-a31-i2c";</div><div class='add'>+			reg = &lt;0x05002800 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_I2C2&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_I2C2&gt;;</div><div class='add'>+			dmas = &lt;&amp;dma 45&gt;, &lt;&amp;dma 45&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c3: i2c@5002c00 {</div><div class='add'>+			compatible = "allwinner,sun50i-a100-i2c",</div><div class='add'>+				     "allwinner,sun8i-v536-i2c",</div><div class='add'>+				     "allwinner,sun6i-a31-i2c";</div><div class='add'>+			reg = &lt;0x05002c00 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_I2C3&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_I2C3&gt;;</div><div class='add'>+			dmas = &lt;&amp;dma 46&gt;, &lt;&amp;dma 46&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		emac0: ethernet@5020000 {</div><div class='add'>+			compatible = "allwinner,sun50i-a100-emac",</div><div class='add'>+				     "allwinner,sun50i-a64-emac";</div><div class='add'>+			reg = &lt;0x5020000 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "macirq";</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_EMAC&gt;;</div><div class='add'>+			clock-names = "stmmaceth";</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_EMAC&gt;;</div><div class='add'>+			reset-names = "stmmaceth";</div><div class='add'>+			syscon = &lt;&amp;syscon&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			mdio0: mdio {</div><div class='add'>+				compatible = "snps,dwmac-mdio";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ths: thermal-sensor@5070400 {</div><div class='add'>+			compatible = "allwinner,sun50i-a100-ths";</div><div class='add'>+			reg = &lt;0x05070400 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_THS&gt;;</div><div class='add'>+			clock-names = "bus";</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_THS&gt;;</div><div class='add'>+			nvmem-cells = &lt;&amp;ths_calibration&gt;;</div><div class='add'>+			nvmem-cell-names = "calibration";</div><div class='add'>+			#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_otg: usb@5100000 {</div><div class='add'>+			compatible = "allwinner,sun50i-a100-musb",</div><div class='add'>+				     "allwinner,sun8i-a33-musb";</div><div class='add'>+			reg = &lt;0x05100000 0x0400&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_OTG&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_OTG&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "mc";</div><div class='add'>+			phys = &lt;&amp;usbphy 0&gt;;</div><div class='add'>+			phy-names = "usb";</div><div class='add'>+			extcon = &lt;&amp;usbphy 0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usbphy: phy@5100400 {</div><div class='add'>+			compatible = "allwinner,sun50i-a100-usb-phy",</div><div class='add'>+				     "allwinner,sun20i-d1-usb-phy";</div><div class='add'>+			reg = &lt;0x05100400 0x100&gt;,</div><div class='add'>+			      &lt;0x05101800 0x100&gt;,</div><div class='add'>+			      &lt;0x05200800 0x100&gt;;</div><div class='add'>+			reg-names = "phy_ctrl",</div><div class='add'>+				    "pmu0",</div><div class='add'>+				    "pmu1";</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_USB_PHY0&gt;,</div><div class='add'>+				 &lt;&amp;ccu CLK_USB_PHY1&gt;;</div><div class='add'>+			clock-names = "usb0_phy",</div><div class='add'>+				      "usb1_phy";</div><div class='add'>+			resets = &lt;&amp;ccu RST_USB_PHY0&gt;,</div><div class='add'>+				 &lt;&amp;ccu RST_USB_PHY1&gt;;</div><div class='add'>+			reset-names = "usb0_reset",</div><div class='add'>+				      "usb1_reset";</div><div class='add'>+			status = "disabled";</div><div class='add'>+			#phy-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ehci0: usb@5101000 {</div><div class='add'>+			compatible = "allwinner,sun50i-a100-ehci",</div><div class='add'>+				     "generic-ehci";</div><div class='add'>+			reg = &lt;0x05101000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_OHCI0&gt;,</div><div class='add'>+				 &lt;&amp;ccu CLK_BUS_EHCI0&gt;,</div><div class='add'>+				 &lt;&amp;ccu CLK_USB_OHCI0&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_OHCI0&gt;,</div><div class='add'>+				 &lt;&amp;ccu RST_BUS_EHCI0&gt;;</div><div class='add'>+			phys = &lt;&amp;usbphy 0&gt;;</div><div class='add'>+			phy-names = "usb";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ohci0: usb@5101400 {</div><div class='add'>+			compatible = "allwinner,sun50i-a100-ohci",</div><div class='add'>+				     "generic-ohci";</div><div class='add'>+			reg = &lt;0x05101400 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_OHCI0&gt;,</div><div class='add'>+				 &lt;&amp;ccu CLK_USB_OHCI0&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_OHCI0&gt;;</div><div class='add'>+			phys = &lt;&amp;usbphy 0&gt;;</div><div class='add'>+			phy-names = "usb";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ehci1: usb@5200000 {</div><div class='add'>+			compatible = "allwinner,sun50i-a100-ehci",</div><div class='add'>+				     "generic-ehci";</div><div class='add'>+			reg = &lt;0x05200000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_OHCI1&gt;,</div><div class='add'>+				 &lt;&amp;ccu CLK_BUS_EHCI1&gt;,</div><div class='add'>+				 &lt;&amp;ccu CLK_USB_OHCI1&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_OHCI1&gt;,</div><div class='add'>+				 &lt;&amp;ccu RST_BUS_EHCI1&gt;;</div><div class='add'>+			phys = &lt;&amp;usbphy 1&gt;;</div><div class='add'>+			phy-names = "usb";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ohci1: usb@5200400 {</div><div class='add'>+			compatible = "allwinner,sun50i-a100-ohci",</div><div class='add'>+				     "generic-ohci";</div><div class='add'>+			reg = &lt;0x05200400 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_OHCI1&gt;,</div><div class='add'>+				 &lt;&amp;ccu CLK_USB_OHCI1&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_OHCI1&gt;;</div><div class='add'>+			phys = &lt;&amp;usbphy 1&gt;;</div><div class='add'>+			phy-names = "usb";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		r_ccu: clock@7010000 {</div><div class='add'>+			compatible = "allwinner,sun50i-a100-r-ccu";</div><div class='add'>+			reg = &lt;0x07010000 0x300&gt;;</div><div class='add'>+			clocks = &lt;&amp;dcxo24M&gt;, &lt;&amp;osc32k&gt;, &lt;&amp;iosc&gt;,</div><div class='add'>+				 &lt;&amp;ccu CLK_PLL_PERIPH0&gt;;</div><div class='add'>+			clock-names = "hosc", "losc", "iosc", "pll-periph";</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		r_intc: interrupt-controller@7010320 {</div><div class='add'>+			compatible = "allwinner,sun50i-a100-nmi",</div><div class='add'>+				     "allwinner,sun9i-a80-nmi";</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			reg = &lt;0x07010320 0xc&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		r_pio: pinctrl@7022000 {</div><div class='add'>+			compatible = "allwinner,sun50i-a100-r-pinctrl";</div><div class='add'>+			reg = &lt;0x07022000 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;r_ccu CLK_R_APB1&gt;, &lt;&amp;dcxo24M&gt;, &lt;&amp;osc32k&gt;;</div><div class='add'>+			clock-names = "apb", "hosc", "losc";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;3&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+			r_i2c0_pins: r-i2c0-pins {</div><div class='add'>+				pins = "PL0", "PL1";</div><div class='add'>+				function = "s_i2c0";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			r_i2c1_pins: r-i2c1-pins {</div><div class='add'>+				pins = "PL8", "PL9";</div><div class='add'>+				function = "s_i2c1";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		r_uart: serial@7080000 {</div><div class='add'>+			compatible = "snps,dw-apb-uart";</div><div class='add'>+			reg = &lt;0x07080000 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			reg-shift = &lt;2&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+			clocks = &lt;&amp;r_ccu CLK_R_APB2_UART&gt;;</div><div class='add'>+			resets = &lt;&amp;r_ccu RST_R_APB2_UART&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		r_i2c0: i2c@7081400 {</div><div class='add'>+			compatible = "allwinner,sun50i-a100-i2c",</div><div class='add'>+				     "allwinner,sun8i-v536-i2c",</div><div class='add'>+				     "allwinner,sun6i-a31-i2c";</div><div class='add'>+			reg = &lt;0x07081400 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;r_ccu CLK_R_APB2_I2C0&gt;;</div><div class='add'>+			resets = &lt;&amp;r_ccu RST_R_APB2_I2C0&gt;;</div><div class='add'>+			dmas = &lt;&amp;dma 50&gt;, &lt;&amp;dma 50&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;r_i2c0_pins&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		r_i2c1: i2c@7081800 {</div><div class='add'>+			compatible = "allwinner,sun50i-a100-i2c",</div><div class='add'>+				     "allwinner,sun8i-v536-i2c",</div><div class='add'>+				     "allwinner,sun6i-a31-i2c";</div><div class='add'>+			reg = &lt;0x07081800 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;r_ccu CLK_R_APB2_I2C1&gt;;</div><div class='add'>+			resets = &lt;&amp;r_ccu RST_R_APB2_I2C1&gt;;</div><div class='add'>+			dmas = &lt;&amp;dma 51&gt;, &lt;&amp;dma 51&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;r_i2c1_pins&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	thermal-zones {</div><div class='add'>+		cpu-thermal {</div><div class='add'>+			polling-delay-passive = &lt;0&gt;;</div><div class='add'>+			polling-delay = &lt;0&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;ths 0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ddr-thermal {</div><div class='add'>+			polling-delay-passive = &lt;0&gt;;</div><div class='add'>+			polling-delay = &lt;0&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;ths 2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu-thermal {</div><div class='add'>+			polling-delay-passive = &lt;0&gt;;</div><div class='add'>+			polling-delay = &lt;0&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;ths 1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a133-liontron-h-a133l.dts b/arch/arm64/boot/dts/allwinner/sun50i-a133-liontron-h-a133l.dts<br/>new file mode 100644<br/>index 000000000000..90a50910f07b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-a133-liontron-h-a133l.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-a133-liontron-h-a133l.dts</a></div><div class='hunk'>@@ -0,0 +1,230 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2025 Arm Ltd.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "sun50i-a100.dtsi"</div><div class='add'>+#include "sun50i-a100-cpu-opp.dtsi"</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+/{</div><div class='add'>+	model = "Liontron H-A133L";</div><div class='add'>+	compatible = "liontron,h-a133l", "allwinner,sun50i-a100";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led {</div><div class='add'>+			function = LED_FUNCTION_POWER;</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			gpios = &lt;&amp;pio 7 16 GPIO_ACTIVE_LOW&gt;; /* PH16 */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc5v: vcc5v {</div><div class='add'>+		/* board wide 5V supply from a 12V-&gt;5V regulator */</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vcc-5v";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb1_vbus: regulator-usb1-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "usb1-vbus";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;r_pio 0 8 GPIO_ACTIVE_HIGH&gt;; /* PL8 */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_dcdc2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ehci0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ehci1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;emac0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;rmii0_pins&gt;;</div><div class='add'>+	phy-handle = &lt;&amp;rmii_phy&gt;;</div><div class='add'>+	phy-mode = "rmii";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdio0 {</div><div class='add'>+	reset-gpios = &lt;&amp;pio 7 12 GPIO_ACTIVE_LOW&gt;; /* PH12 */</div><div class='add'>+	reset-delay-us = &lt;2000&gt;;</div><div class='add'>+	reset-post-delay-us = &lt;2000&gt;;</div><div class='add'>+</div><div class='add'>+	rmii_phy: ethernet-phy@1 {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc0 {</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_dcdc1&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;pio 5 6 GPIO_ACTIVE_LOW&gt;; /* PF6 */</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc2 {</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_dcdc1&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_eldo1&gt;;</div><div class='add'>+	cap-mmc-hw-reset;</div><div class='add'>+	non-removable;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	mmc-ddr-1_8v;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ohci0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ohci1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	vcc-pb-supply = &lt;&amp;reg_dcdc1&gt;;</div><div class='add'>+	vcc-pc-supply = &lt;&amp;reg_eldo1&gt;;</div><div class='add'>+	vcc-pf-supply = &lt;&amp;reg_dcdc1&gt;;</div><div class='add'>+	vcc-ph-supply = &lt;&amp;reg_dcdc1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;r_i2c0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	axp803: pmic@34 {</div><div class='add'>+		compatible = "x-powers,axp803";</div><div class='add'>+		reg = &lt;0x34&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;r_intc&gt;;</div><div class='add'>+		interrupts = &lt;0 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include "axp803.dtsi"</div><div class='add'>+</div><div class='add'>+&amp;ac_power_supply {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_aldo1 {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+	regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	regulator-name = "vcc-codec-avcc";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_aldo2 {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+	regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	regulator-name = "vcc-dram-1";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_aldo3 {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+	regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	regulator-name = "vcc-usb-pl";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_dcdc1 {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+	regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	regulator-name = "vcc-io-usb-pd-emmc";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_dcdc2 {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+	regulator-min-microvolt = &lt;810000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+	regulator-name = "vdd-cpux";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_dcdc3 {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+	regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;900000&gt;;</div><div class='add'>+	regulator-name = "vdd-usb-cpus";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_dcdc4 {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+	regulator-min-microvolt = &lt;950000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;950000&gt;;</div><div class='add'>+	regulator-name = "vdd-sys";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_dcdc5 {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+	regulator-min-microvolt = &lt;1100000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+	regulator-name = "vcc-dram";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* DCDC6 unused */</div><div class='add'>+/* DLDO3 unused */</div><div class='add'>+/* DLDO4 unused */</div><div class='add'>+</div><div class='add'>+&amp;reg_eldo1 {</div><div class='add'>+	regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	regulator-name = "vcc-pc-emmc";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* ELDO2 unused */</div><div class='add'>+/* ELDO3 unused */</div><div class='add'>+</div><div class='add'>+&amp;reg_fldo1 {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+	regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;900000&gt;;</div><div class='add'>+	regulator-name = "vdd-cpus-usb";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* reg_drivevbus unused */</div><div class='add'>+/* dc1sw unused */</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart0_pb_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_otg {</div><div class='add'>+	dr_mode = "host";       /* USB A type receptacle, always powered */</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbphy {</div><div class='add'>+	usb1_vbus-supply = &lt;&amp;reg_usb1_vbus&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts<br/>index c7bd73f35ed8..8233582f6288 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts</a></div><div class='hunk'>@@ -58,7 +58,7 @@</div><div class='ctx'> </div><div class='ctx'> 	wifi_pwrseq: wifi-pwrseq {</div><div class='ctx'> 		compatible = "mmc-pwrseq-simple";</div><div class='del'>-		clocks = &lt;&amp;rtc 1&gt;;</div><div class='add'>+		clocks = &lt;&amp;rtc CLK_OSC32K_FANOUT&gt;;</div><div class='ctx'> 		clock-names = "ext_clock";</div><div class='ctx'> 		reset-gpios = &lt;&amp;r_pio 0 2 GPIO_ACTIVE_LOW&gt;; /* WL-PMU-EN: PL2 */</div><div class='ctx'> 	};</div><div class='hunk'>@@ -173,7 +173,7 @@</div><div class='ctx'> 		compatible = "x-powers,axp803";</div><div class='ctx'> 		reg = &lt;0x3a3&gt;;</div><div class='ctx'> 		interrupt-parent = &lt;&amp;r_intc&gt;;</div><div class='del'>-		interrupts = &lt;0 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 		x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts<br/>index 883f217efb81..d1f415acd7b5 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts</a></div><div class='hunk'>@@ -36,27 +36,27 @@</div><div class='ctx'> 	leds {</div><div class='ctx'> 		compatible = "gpio-leds";</div><div class='ctx'> </div><div class='del'>-		pwr-led {</div><div class='add'>+		led-0 {</div><div class='ctx'> 			label = "bananapi-m64:red:pwr";</div><div class='ctx'> 			gpios = &lt;&amp;pio 3 24 GPIO_ACTIVE_HIGH&gt;; /* PD24 */</div><div class='ctx'> 			default-state = "on";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		green {</div><div class='add'>+		led-1 {</div><div class='ctx'> 			label = "bananapi-m64:green:user";</div><div class='ctx'> 			gpios = &lt;&amp;pio 4 14 GPIO_ACTIVE_HIGH&gt;; /* PE14 */</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		blue {</div><div class='add'>+		led-2 {</div><div class='ctx'> 			label = "bananapi-m64:blue:user";</div><div class='ctx'> 			gpios = &lt;&amp;pio 4 15 GPIO_ACTIVE_HIGH&gt;; /* PE15 */</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	wifi_pwrseq: wifi_pwrseq {</div><div class='add'>+	wifi_pwrseq: pwrseq {</div><div class='ctx'> 		compatible = "mmc-pwrseq-simple";</div><div class='ctx'> 		reset-gpios = &lt;&amp;r_pio 0 2 GPIO_ACTIVE_LOW&gt;; /* PL2 */</div><div class='del'>-		clocks = &lt;&amp;rtc 1&gt;;</div><div class='add'>+		clocks = &lt;&amp;rtc CLK_OSC32K_FANOUT&gt;;</div><div class='ctx'> 		clock-names = "ext_clock";</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='hunk'>@@ -105,7 +105,7 @@</div><div class='ctx'> &amp;emac {</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;rgmii_pins&gt;;</div><div class='del'>-	phy-mode = "rgmii";</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='ctx'> 	phy-handle = &lt;&amp;ext_rgmii_phy&gt;;</div><div class='ctx'> 	phy-supply = &lt;&amp;reg_dc1sw&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='hunk'>@@ -191,7 +191,7 @@</div><div class='ctx'> 		compatible = "x-powers,axp803";</div><div class='ctx'> 		reg = &lt;0x3a3&gt;;</div><div class='ctx'> 		interrupt-parent = &lt;&amp;r_intc&gt;;</div><div class='del'>-		interrupts = &lt;0 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 		x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='hunk'>@@ -331,10 +331,10 @@</div><div class='ctx'> 				    "Microphone", "Microphone Jack",</div><div class='ctx'> 				    "Microphone", "Onboard Microphone";</div><div class='ctx'> 	simple-audio-card,routing =</div><div class='del'>-			"Left DAC", "AIF1 Slot 0 Left",</div><div class='del'>-			"Right DAC", "AIF1 Slot 0 Right",</div><div class='del'>-			"AIF1 Slot 0 Left ADC", "Left ADC",</div><div class='del'>-			"AIF1 Slot 0 Right ADC", "Right ADC",</div><div class='add'>+			"Left DAC", "DACL",</div><div class='add'>+			"Right DAC", "DACR",</div><div class='add'>+			"ADCL", "Left ADC",</div><div class='add'>+			"ADCR", "Right ADC",</div><div class='ctx'> 			"Headphone Jack", "HP",</div><div class='ctx'> 			"MIC2", "Microphone Jack",</div><div class='ctx'> 			"Onboard Microphone", "MBIAS",</div><div class='hunk'>@@ -355,7 +355,7 @@</div><div class='ctx'> </div><div class='ctx'> 	bluetooth {</div><div class='ctx'> 		compatible = "brcm,bcm43438-bt";</div><div class='del'>-		clocks = &lt;&amp;rtc 1&gt;;</div><div class='add'>+		clocks = &lt;&amp;rtc CLK_OSC32K_FANOUT&gt;;</div><div class='ctx'> 		clock-names = "lpo";</div><div class='ctx'> 		vbat-supply = &lt;&amp;reg_dldo2&gt;;</div><div class='ctx'> 		vddio-supply = &lt;&amp;reg_dldo4&gt;;</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-cpu-opp.dtsi<br/>index 578c37490d90..e39db51eb448 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-a64-cpu-opp.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-a64-cpu-opp.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-a64-cpu-opp.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-a64-cpu-opp.dtsi</a></div><div class='hunk'>@@ -4,7 +4,7 @@</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='del'>-	cpu0_opp_table: opp_table0 {</div><div class='add'>+	cpu0_opp_table: opp-table-cpu {</div><div class='ctx'> 		compatible = "operating-points-v2";</div><div class='ctx'> 		opp-shared;</div><div class='ctx'> </div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts<br/>index e58db8a6cab6..dec9960a7440 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts</a></div><div class='hunk'>@@ -35,15 +35,15 @@</div><div class='ctx'> 	leds {</div><div class='ctx'> 		compatible = "gpio-leds";</div><div class='ctx'> </div><div class='del'>-		blue {</div><div class='add'>+		led {</div><div class='ctx'> 			label = "nanopi-a64:blue:status";</div><div class='ctx'> 			gpios = &lt;&amp;pio 3 24 GPIO_ACTIVE_LOW&gt;; /* PD24 */</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	wifi_pwrseq: wifi_pwrseq {</div><div class='add'>+	wifi_pwrseq: pwrseq {</div><div class='ctx'> 		compatible = "mmc-pwrseq-simple";</div><div class='del'>-		clocks = &lt;&amp;rtc 1&gt;;</div><div class='add'>+		clocks = &lt;&amp;rtc CLK_OSC32K_FANOUT&gt;;</div><div class='ctx'> 		clock-names = "ext_clock";</div><div class='ctx'> 		reset-gpios = &lt;&amp;r_pio 0 2 GPIO_ACTIVE_LOW&gt;; /* PL2 */</div><div class='ctx'> 	};</div><div class='hunk'>@@ -152,7 +152,7 @@</div><div class='ctx'> 		compatible = "x-powers,axp803";</div><div class='ctx'> 		reg = &lt;0x3a3&gt;;</div><div class='ctx'> 		interrupt-parent = &lt;&amp;r_intc&gt;;</div><div class='del'>-		interrupts = &lt;0 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts<br/>index 5fa9ca0191a8..fd3794678c33 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts</a></div><div class='hunk'>@@ -32,6 +32,15 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			label = "a64-olinuxino:red:user";</div><div class='add'>+			gpios = &lt;&amp;pio 4 17 GPIO_ACTIVE_HIGH&gt;; /* PE17 */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	reg_usb1_vbus: usb1-vbus {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "usb1-vbus";</div><div class='hunk'>@@ -43,12 +52,21 @@</div><div class='ctx'> 		status = "okay";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	wifi_pwrseq: wifi_pwrseq {</div><div class='add'>+	wifi_pwrseq: pwrseq {</div><div class='ctx'> 		compatible = "mmc-pwrseq-simple";</div><div class='ctx'> 		reset-gpios = &lt;&amp;r_pio 0 2 GPIO_ACTIVE_LOW&gt;; /* PL2 */</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;codec {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;codec_analog {</div><div class='add'>+	cpvdd-supply = &lt;&amp;reg_eldo1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;cpu0 {</div><div class='ctx'> 	cpu-supply = &lt;&amp;reg_dcdc2&gt;;</div><div class='ctx'> };</div><div class='hunk'>@@ -65,6 +83,10 @@</div><div class='ctx'> 	cpu-supply = &lt;&amp;reg_dcdc2&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;dai {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;de {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='hunk'>@@ -176,7 +198,7 @@</div><div class='ctx'> 		compatible = "x-powers,axp803";</div><div class='ctx'> 		reg = &lt;0x3a3&gt;;</div><div class='ctx'> 		interrupt-parent = &lt;&amp;r_intc&gt;;</div><div class='del'>-		interrupts = &lt;0 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 		x-powers,drive-vbus-en;	/* set N_VBUSEN as output pin */</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='hunk'>@@ -319,6 +341,23 @@</div><div class='ctx'> 	vcc-hdmi-supply = &lt;&amp;reg_dldo1&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;sound {</div><div class='add'>+	simple-audio-card,aux-devs = &lt;&amp;codec_analog&gt;;</div><div class='add'>+	simple-audio-card,widgets = "Microphone", "Microphone Jack Left",</div><div class='add'>+		    "Microphone", "Microphone Jack Right",</div><div class='add'>+		    "Headphone", "Headphone Jack";</div><div class='add'>+	simple-audio-card,routing = "Left DAC", "DACL",</div><div class='add'>+		    "Right DAC", "DACR",</div><div class='add'>+		    "Headphone Jack", "HP",</div><div class='add'>+		    "ADCL", "Left ADC",</div><div class='add'>+		    "ADCR", "Right ADC",</div><div class='add'>+		    "Microphone Jack Left", "MBIAS",</div><div class='add'>+		    "MIC1", "Microphone Jack Left",</div><div class='add'>+		    "Microphone Jack Right", "MBIAS",</div><div class='add'>+		    "MIC2", "Microphone Jack Right";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;uart0 {</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;uart0_pb_pins&gt;;</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts<br/>index fde9c7a99b17..c8303a66438d 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts</a></div><div class='hunk'>@@ -40,7 +40,7 @@</div><div class='ctx'> 	leds {</div><div class='ctx'> 		compatible = "gpio-leds";</div><div class='ctx'> </div><div class='del'>-		status {</div><div class='add'>+		led-0 {</div><div class='ctx'> 			label = "orangepi:green:status";</div><div class='ctx'> 			gpios = &lt;&amp;pio 7 11 GPIO_ACTIVE_HIGH&gt;; /* PH11 */</div><div class='ctx'> 		};</div><div class='hunk'>@@ -68,10 +68,10 @@</div><div class='ctx'> 		status = "okay";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	wifi_pwrseq: wifi_pwrseq {</div><div class='add'>+	wifi_pwrseq: pwrseq {</div><div class='ctx'> 		compatible = "mmc-pwrseq-simple";</div><div class='ctx'> 		reset-gpios = &lt;&amp;r_pio 0 8 GPIO_ACTIVE_LOW&gt;; /* PL8 */</div><div class='del'>-		clocks = &lt;&amp;rtc 1&gt;;</div><div class='add'>+		clocks = &lt;&amp;rtc CLK_OSC32K_FANOUT&gt;;</div><div class='ctx'> 		clock-names = "ext_clock";</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='hunk'>@@ -120,7 +120,7 @@</div><div class='ctx'> &amp;emac {</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;rgmii_pins&gt;;</div><div class='del'>-	phy-mode = "rgmii";</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='ctx'> 	phy-handle = &lt;&amp;ext_rgmii_phy&gt;;</div><div class='ctx'> 	phy-supply = &lt;&amp;reg_gmac_3v3&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='hunk'>@@ -192,7 +192,7 @@</div><div class='ctx'> 		compatible = "x-powers,axp803";</div><div class='ctx'> 		reg = &lt;0x3a3&gt;;</div><div class='ctx'> 		interrupt-parent = &lt;&amp;r_intc&gt;;</div><div class='del'>-		interrupts = &lt;0 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 		x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='hunk'>@@ -330,10 +330,10 @@</div><div class='ctx'> 				    "Microphone", "Microphone Jack",</div><div class='ctx'> 				    "Microphone", "Onboard Microphone";</div><div class='ctx'> 	simple-audio-card,routing =</div><div class='del'>-			"Left DAC", "AIF1 Slot 0 Left",</div><div class='del'>-			"Right DAC", "AIF1 Slot 0 Right",</div><div class='del'>-			"AIF1 Slot 0 Left ADC", "Left ADC",</div><div class='del'>-			"AIF1 Slot 0 Right ADC", "Right ADC",</div><div class='add'>+			"Left DAC", "DACL",</div><div class='add'>+			"Right DAC", "DACR",</div><div class='add'>+			"ADCL", "Left ADC",</div><div class='add'>+			"ADCR", "Right ADC",</div><div class='ctx'> 			"Headphone Jack", "HP",</div><div class='ctx'> 			"MIC2", "Microphone Jack",</div><div class='ctx'> 			"Onboard Microphone", "MBIAS",</div><div class='hunk'>@@ -343,7 +343,7 @@</div><div class='ctx'> &amp;spi0 {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='del'>-	spi-flash@0 {</div><div class='add'>+	flash@0 {</div><div class='ctx'> 		compatible = "mxicy,mx25l1606e", "jedec,spi-nor";</div><div class='ctx'> 		reg = &lt;0&gt;;</div><div class='ctx'> 		spi-max-frequency = &lt;80000000&gt;;</div><div class='hunk'>@@ -369,7 +369,7 @@</div><div class='ctx'> 	bluetooth {</div><div class='ctx'> 		compatible = "brcm,bcm43438-bt";</div><div class='ctx'> 		max-speed = &lt;1500000&gt;;</div><div class='del'>-		clocks = &lt;&amp;rtc 1&gt;;</div><div class='add'>+		clocks = &lt;&amp;rtc CLK_OSC32K_FANOUT&gt;;</div><div class='ctx'> 		clock-names = "lpo";</div><div class='ctx'> 		vbat-supply = &lt;&amp;reg_dldo2&gt;;</div><div class='ctx'> 		vddio-supply = &lt;&amp;reg_dldo4&gt;;</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-lts.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-lts.dts<br/>index 302e24be0a31..709fe650a360 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-lts.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-lts.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-lts.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-lts.dts</a></div><div class='hunk'>@@ -1,10 +1,25 @@</div><div class='ctx'> // SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='ctx'> // Copyright (c) 2018 ARM Ltd.</div><div class='ctx'> </div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='ctx'> #include "sun50i-a64-sopine-baseboard.dts"</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='del'>-	model = "Pine64 LTS";</div><div class='add'>+	model = "Pine64 PINE A64 LTS";</div><div class='ctx'> 	compatible = "pine64,pine64-lts", "allwinner,sun50i-r18",</div><div class='ctx'> 		     "allwinner,sun50i-a64";</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			gpios = &lt;&amp;r_pio 0 7 GPIO_ACTIVE_LOW&gt;; /* PL7 */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc0 {</div><div class='add'>+	broken-cd;		/* card detect is broken on *some* boards */</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts<br/>index b26181cf9095..026d843cd7e0 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts</a></div><div class='hunk'>@@ -4,7 +4,7 @@</div><div class='ctx'> #include "sun50i-a64-pine64.dts"</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='del'>-	model = "Pine64+";</div><div class='add'>+	model = "Pine64 PINE A64+";</div><div class='ctx'> 	compatible = "pine64,pine64-plus", "allwinner,sun50i-a64";</div><div class='ctx'> </div><div class='ctx'> 	/* TODO: Camera, touchscreen, etc. */</div><div class='hunk'>@@ -13,7 +13,7 @@</div><div class='ctx'> &amp;emac {</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;rgmii_pins&gt;;</div><div class='del'>-	phy-mode = "rgmii";</div><div class='add'>+	phy-mode = "rgmii-txid";</div><div class='ctx'> 	phy-handle = &lt;&amp;ext_rgmii_phy&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts<br/>index 2165f238af13..3256acec1ff9 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts</a></div><div class='hunk'>@@ -9,7 +9,7 @@</div><div class='ctx'> #include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='del'>-	model = "Pine64";</div><div class='add'>+	model = "Pine64 PINE A64";</div><div class='ctx'> 	compatible = "pine64,pine64", "allwinner,sun50i-a64";</div><div class='ctx'> </div><div class='ctx'> 	aliases {</div><div class='hunk'>@@ -124,6 +124,17 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+/* On Wifi/BT connector */</div><div class='add'>+&amp;mmc1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc1_pins&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_dldo4&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_eldo1&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;ohci0 {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='hunk'>@@ -139,7 +150,7 @@</div><div class='ctx'> 		compatible = "x-powers,axp803";</div><div class='ctx'> 		reg = &lt;0x3a3&gt;;</div><div class='ctx'> 		interrupt-parent = &lt;&amp;r_intc&gt;;</div><div class='del'>-		interrupts = &lt;0 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -261,11 +272,11 @@</div><div class='ctx'> 	simple-audio-card,widgets = "Microphone", "Microphone Jack",</div><div class='ctx'> 				    "Headphone", "Headphone Jack";</div><div class='ctx'> 	simple-audio-card,routing =</div><div class='del'>-			"Left DAC", "AIF1 Slot 0 Left",</div><div class='del'>-			"Right DAC", "AIF1 Slot 0 Right",</div><div class='add'>+			"Left DAC", "DACL",</div><div class='add'>+			"Right DAC", "DACR",</div><div class='ctx'> 			"Headphone Jack", "HP",</div><div class='del'>-			"AIF1 Slot 0 Left ADC", "Left ADC",</div><div class='del'>-			"AIF1 Slot 0 Right ADC", "Right ADC",</div><div class='add'>+			"ADCL", "Left ADC",</div><div class='add'>+			"ADCR", "Right ADC",</div><div class='ctx'> 			"MIC2", "Microphone Jack";</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='hunk'>@@ -286,6 +297,7 @@</div><div class='ctx'> &amp;uart1 {</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;uart1_pins&gt;, &lt;&amp;uart1_rts_cts_pins&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='ctx'> 	status = "disabled";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts<br/>index 64b1c54f87c0..86d44349e095 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts</a></div><div class='hunk'>@@ -13,8 +13,9 @@</div><div class='ctx'> #include &lt;dt-bindings/pwm/pwm.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='del'>-	model = "Pinebook";</div><div class='add'>+	model = "Pine64 Pinebook";</div><div class='ctx'> 	compatible = "pine64,pinebook", "allwinner,sun50i-a64";</div><div class='add'>+	chassis-type = "laptop";</div><div class='ctx'> </div><div class='ctx'> 	aliases {</div><div class='ctx'> 		serial0 = &amp;uart0;</div><div class='hunk'>@@ -34,10 +35,10 @@</div><div class='ctx'> 		stdout-path = "serial0:115200n8";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpio_keys {</div><div class='add'>+	gpio-keys {</div><div class='ctx'> 		compatible = "gpio-keys";</div><div class='ctx'> </div><div class='del'>-		lid_switch {</div><div class='add'>+		lid-switch {</div><div class='ctx'> 			label = "Lid Switch";</div><div class='ctx'> 			gpios = &lt;&amp;r_pio 0 12 GPIO_ACTIVE_LOW&gt;; /* PL12 */</div><div class='ctx'> 			linux,input-type = &lt;EV_SW&gt;;</div><div class='hunk'>@@ -78,7 +79,7 @@</div><div class='ctx'> 		enable-active-high;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	wifi_pwrseq: wifi_pwrseq {</div><div class='add'>+	wifi_pwrseq: pwrseq {</div><div class='ctx'> 		compatible = "mmc-pwrseq-simple";</div><div class='ctx'> 		reset-gpios = &lt;&amp;r_pio 0 2 GPIO_ACTIVE_LOW&gt;; /* PL2 */</div><div class='ctx'> 	};</div><div class='hunk'>@@ -126,8 +127,6 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;ehci0 {</div><div class='del'>-	phys = &lt;&amp;usbphy 0&gt;;</div><div class='del'>-	phy-names = "usb";</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -169,6 +168,7 @@</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;mmc2_pins&gt;, &lt;&amp;mmc2_ds_pin&gt;;</div><div class='ctx'> 	vmmc-supply = &lt;&amp;reg_dcdc1&gt;;</div><div class='ctx'> 	vqmmc-supply = &lt;&amp;reg_eldo1&gt;;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='ctx'> 	bus-width = &lt;8&gt;;</div><div class='ctx'> 	non-removable;</div><div class='ctx'> 	cap-mmc-hw-reset;</div><div class='hunk'>@@ -177,8 +177,6 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;ohci0 {</div><div class='del'>-	phys = &lt;&amp;usbphy 0&gt;;</div><div class='del'>-	phy-names = "usb";</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -248,7 +246,7 @@</div><div class='ctx'> 		compatible = "x-powers,axp803";</div><div class='ctx'> 		reg = &lt;0x3a3&gt;;</div><div class='ctx'> 		interrupt-parent = &lt;&amp;r_intc&gt;;</div><div class='del'>-		interrupts = &lt;0 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -374,15 +372,15 @@</div><div class='ctx'> 				    "Headphone", "Headphone Jack",</div><div class='ctx'> 				    "Speaker", "Internal Speaker";</div><div class='ctx'> 	simple-audio-card,routing =</div><div class='del'>-			"Left DAC", "AIF1 Slot 0 Left",</div><div class='del'>-			"Right DAC", "AIF1 Slot 0 Right",</div><div class='add'>+			"Left DAC", "DACL",</div><div class='add'>+			"Right DAC", "DACR",</div><div class='ctx'> 			"Speaker Amp INL", "LINEOUT",</div><div class='ctx'> 			"Speaker Amp INR", "LINEOUT",</div><div class='ctx'> 			"Internal Speaker", "Speaker Amp OUTL",</div><div class='ctx'> 			"Internal Speaker", "Speaker Amp OUTR",</div><div class='ctx'> 			"Headphone Jack", "HP",</div><div class='del'>-			"AIF1 Slot 0 Left ADC", "Left ADC",</div><div class='del'>-			"AIF1 Slot 0 Right ADC", "Right ADC",</div><div class='add'>+			"ADCL", "Left ADC",</div><div class='add'>+			"ADCR", "Right ADC",</div><div class='ctx'> 			"Internal Microphone Left", "MBIAS",</div><div class='ctx'> 			"MIC1", "Internal Microphone Left",</div><div class='ctx'> 			"Internal Microphone Right", "HBIAS",</div><div class='hunk'>@@ -392,6 +390,8 @@</div><div class='ctx'> &amp;tcon0 {</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;lcd_rgb666_pins&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;ccu CLK_TCON0&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;ccu CLK_PLL_VIDEO0_2X&gt;;</div><div class='ctx'> </div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='hunk'>@@ -408,6 +408,20 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart1_pins&gt;, &lt;&amp;uart1_rts_cts_pins&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "realtek,rtl8723cs-bt";</div><div class='add'>+		device-wake-gpios = &lt;&amp;r_pio 0 5 GPIO_ACTIVE_LOW&gt;; /* PL5 */</div><div class='add'>+		enable-gpios = &lt;&amp;r_pio 0 4 GPIO_ACTIVE_HIGH&gt;; /* PL4 */</div><div class='add'>+		host-wake-gpios = &lt;&amp;r_pio 0 6 GPIO_ACTIVE_HIGH&gt;; /* PL6 */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;usb_otg {</div><div class='ctx'> 	dr_mode = "host";</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts<br/>index 0c42272106af..219f720b8b7d 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts</a></div><div class='hunk'>@@ -7,5 +7,14 @@</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	model = "Pine64 PinePhone Developer Batch (1.0)";</div><div class='del'>-	compatible = "pine64,pinephone-1.0", "allwinner,sun50i-a64";</div><div class='add'>+	compatible = "pine64,pinephone-1.0", "pine64,pinephone", "allwinner,sun50i-a64";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;codec_analog {</div><div class='add'>+	allwinner,internal-bias-resistor;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sgm3140 {</div><div class='add'>+	enable-gpios = &lt;&amp;pio 2 3 GPIO_ACTIVE_HIGH&gt;; /* PC3 */</div><div class='add'>+	flash-gpios = &lt;&amp;pio 3 24 GPIO_ACTIVE_HIGH&gt;; /* PD24 */</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts<br/>index 06a775c41664..723af64a9cee 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts</a></div><div class='hunk'>@@ -7,5 +7,33 @@</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	model = "Pine64 PinePhone Braveheart (1.1)";</div><div class='del'>-	compatible = "pine64,pinephone-1.1", "allwinner,sun50i-a64";</div><div class='add'>+	compatible = "pine64,pinephone-1.1", "pine64,pinephone", "allwinner,sun50i-a64";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;backlight {</div><div class='add'>+	power-supply = &lt;&amp;reg_ldo_io0&gt;;</div><div class='add'>+	/*</div><div class='add'>+	 * PWM backlight circuit on this PinePhone revision was changed since</div><div class='add'>+	 * 1.0, and the lowest PWM duty cycle that doesn't lead to backlight</div><div class='add'>+	 * being off is around 20%. Duty cycle for the lowest brightness level</div><div class='add'>+	 * also varries quite a bit between individual boards, so the lowest</div><div class='add'>+	 * value here was chosen as a safe default.</div><div class='add'>+	 */</div><div class='add'>+	brightness-levels = &lt;</div><div class='add'>+		774  793  814  842</div><div class='add'>+		882  935  1003 1088</div><div class='add'>+		1192 1316 1462 1633</div><div class='add'>+		1830 2054 2309 2596</div><div class='add'>+		2916 3271 3664 4096&gt;;</div><div class='add'>+	num-interpolated-steps = &lt;50&gt;;</div><div class='add'>+	default-brightness-level = &lt;400&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;codec_analog {</div><div class='add'>+	allwinner,internal-bias-resistor;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sgm3140 {</div><div class='add'>+	enable-gpios = &lt;&amp;pio 3 24 GPIO_ACTIVE_HIGH&gt;; /* PD24 */</div><div class='add'>+	flash-gpios = &lt;&amp;pio 2 3 GPIO_ACTIVE_HIGH&gt;; /* PC3 */</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts<br/>new file mode 100644<br/>index 000000000000..4e7e237cb46a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts</a></div><div class='hunk'>@@ -0,0 +1,54 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+// Copyright (C) 2020 Ondrej Jirman &lt;megous@megous.com&gt;</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "sun50i-a64-pinephone.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Pine64 PinePhone (1.2)";</div><div class='add'>+	compatible = "pine64,pinephone-1.2", "pine64,pinephone", "allwinner,sun50i-a64";</div><div class='add'>+</div><div class='add'>+	wifi_pwrseq: wifi-pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-simple";</div><div class='add'>+		reset-gpios = &lt;&amp;r_pio 0 2 GPIO_ACTIVE_LOW&gt;; /* PL2 */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;backlight {</div><div class='add'>+	power-supply = &lt;&amp;reg_ldo_io0&gt;;</div><div class='add'>+	/*</div><div class='add'>+	 * PWM backlight circuit on this PinePhone revision was changed since 1.0,</div><div class='add'>+	 * and the lowest PWM duty cycle that doesn't lead to backlight being off</div><div class='add'>+	 * is around 10%. Duty cycle for the lowest brightness level also varries</div><div class='add'>+	 * quite a bit between individual boards, so the lowest value here was</div><div class='add'>+	 * chosen as a safe default.</div><div class='add'>+	 */</div><div class='add'>+	brightness-levels = &lt;</div><div class='add'>+		5000 5248 5506 5858 6345</div><div class='add'>+		6987 7805 8823 10062 11543</div><div class='add'>+		13287 15317 17654 20319 23336</div><div class='add'>+		26724 30505 34702 39335 44427</div><div class='add'>+		50000</div><div class='add'>+	&gt;;</div><div class='add'>+	num-interpolated-steps = &lt;50&gt;;</div><div class='add'>+	default-brightness-level = &lt;500&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lis3mdl {</div><div class='add'>+	/*</div><div class='add'>+	 * Board revision 1.2 fixed routing of the interrupt to DRDY pin,</div><div class='add'>+	 * enable interrupts.</div><div class='add'>+	 */</div><div class='add'>+	interrupt-parent = &lt;&amp;pio&gt;;</div><div class='add'>+	interrupts = &lt;1 1 IRQ_TYPE_EDGE_RISING&gt;; /* PB1 */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc1 {</div><div class='add'>+	mmc-pwrseq = &lt;&amp;wifi_pwrseq&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sgm3140 {</div><div class='add'>+	enable-gpios = &lt;&amp;pio 3 24 GPIO_ACTIVE_HIGH&gt;; /* PD24 */</div><div class='add'>+	flash-gpios = &lt;&amp;pio 2 3 GPIO_ACTIVE_HIGH&gt;; /* PC3 */</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi<br/>index cefda145c3c9..4bc6c1ef2cde 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi</a></div><div class='hunk'>@@ -12,10 +12,26 @@</div><div class='ctx'> #include &lt;dt-bindings/pwm/pwm.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='add'>+	chassis-type = "handset";</div><div class='add'>+</div><div class='ctx'> 	aliases {</div><div class='add'>+		ethernet0 = &amp;rtl8723cs;</div><div class='ctx'> 		serial0 = &amp;uart0;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	backlight: backlight {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		pwms = &lt;&amp;r_pwm 0 50000 PWM_POLARITY_INVERTED&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;pio 7 10 GPIO_ACTIVE_HIGH&gt;; /* PH10 */</div><div class='add'>+		power-supply = &lt;&amp;reg_ps&gt;;</div><div class='add'>+		/* Backlight configuration differs per PinePhone revision. */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bt_sco_codec: bt-sco-codec {</div><div class='add'>+		#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+		compatible = "linux,bt-sco";</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	chosen {</div><div class='ctx'> 		stdout-path = "serial0:115200n8";</div><div class='ctx'> 	};</div><div class='hunk'>@@ -23,22 +39,58 @@</div><div class='ctx'> 	leds {</div><div class='ctx'> 		compatible = "gpio-leds";</div><div class='ctx'> </div><div class='del'>-		blue {</div><div class='add'>+		led0: led-0 {</div><div class='ctx'> 			function = LED_FUNCTION_INDICATOR;</div><div class='ctx'> 			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='ctx'> 			gpios = &lt;&amp;pio 3 20 GPIO_ACTIVE_HIGH&gt;; /* PD20 */</div><div class='add'>+			retain-state-suspended;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		green {</div><div class='add'>+		led1: led-1 {</div><div class='ctx'> 			function = LED_FUNCTION_INDICATOR;</div><div class='ctx'> 			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='ctx'> 			gpios = &lt;&amp;pio 3 18 GPIO_ACTIVE_HIGH&gt;; /* PD18 */</div><div class='add'>+			retain-state-suspended;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		red {</div><div class='add'>+		led2: led-2 {</div><div class='ctx'> 			function = LED_FUNCTION_INDICATOR;</div><div class='ctx'> 			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='ctx'> 			gpios = &lt;&amp;pio 3 19 GPIO_ACTIVE_HIGH&gt;; /* PD19 */</div><div class='add'>+			retain-state-suspended;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	multi-led {</div><div class='add'>+		compatible = "leds-group-multicolor";</div><div class='add'>+		color = &lt;LED_COLOR_ID_RGB&gt;;</div><div class='add'>+		function = LED_FUNCTION_INDICATOR;</div><div class='add'>+		leds = &lt;&amp;led0&gt;, &lt;&amp;led1&gt;, &lt;&amp;led2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_ps: ps-regulator {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "ps";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vbat_wifi: vbat-wifi {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "vbat-wifi";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sgm3140: led-controller {</div><div class='add'>+		compatible = "sgmicro,sgm3140";</div><div class='add'>+		vin-supply = &lt;&amp;reg_dcdc1&gt;;</div><div class='add'>+</div><div class='add'>+		sgm3140_flash: led {</div><div class='add'>+			function = LED_FUNCTION_FLASH;</div><div class='add'>+			color = &lt;LED_COLOR_ID_WHITE&gt;;</div><div class='add'>+			flash-max-timeout-us = &lt;250000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -56,6 +108,8 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;codec {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;aif3_pins&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -84,6 +138,28 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;de {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dphy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsi {</div><div class='add'>+	vcc-dsi-supply = &lt;&amp;reg_dldo1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	panel@0 {</div><div class='add'>+		compatible = "xingbangda,xbd599";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pio 3 23 GPIO_ACTIVE_LOW&gt;; /* PD23 */</div><div class='add'>+		iovcc-supply = &lt;&amp;reg_dldo2&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_ldo_io0&gt;;</div><div class='add'>+		backlight = &lt;&amp;backlight&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;ehci0 {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='hunk'>@@ -92,25 +168,71 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	touchscreen@5d {</div><div class='add'>+		compatible = "goodix,gt917s";</div><div class='add'>+		reg = &lt;0x5d&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;pio&gt;;</div><div class='add'>+		interrupts = &lt;7 4 IRQ_TYPE_LEVEL_HIGH&gt;; /* PH4 */</div><div class='add'>+		irq-gpios = &lt;&amp;pio 7 4 GPIO_ACTIVE_HIGH&gt;; /* PH4 */</div><div class='add'>+		reset-gpios = &lt;&amp;pio 7 11 GPIO_ACTIVE_HIGH&gt;; /* PH11 */</div><div class='add'>+		AVDD28-supply = &lt;&amp;reg_ldo_io0&gt;;</div><div class='add'>+		VDDIO-supply = &lt;&amp;reg_ldo_io0&gt;;</div><div class='add'>+		touchscreen-size-x = &lt;720&gt;;</div><div class='add'>+		touchscreen-size-y = &lt;1440&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;i2c1 {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='add'>+	/* Alternative magnetometer */</div><div class='add'>+	af8133j: magnetometer@1c {</div><div class='add'>+		compatible = "voltafield,af8133j";</div><div class='add'>+		reg = &lt;0x1c&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pio 1 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		avdd-supply = &lt;&amp;reg_dldo1&gt;;</div><div class='add'>+		dvdd-supply = &lt;&amp;reg_dldo1&gt;;</div><div class='add'>+		mount-matrix = "0", "-1", "0",</div><div class='add'>+				"-1", "0", "0",</div><div class='add'>+				"0", "0", "-1";</div><div class='add'>+</div><div class='add'>+		/* status will be fixed up in firmware */</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	/* Magnetometer */</div><div class='del'>-	lis3mdl@1e {</div><div class='add'>+	lis3mdl: magnetometer@1e {</div><div class='ctx'> 		compatible = "st,lis3mdl-magn";</div><div class='ctx'> 		reg = &lt;0x1e&gt;;</div><div class='ctx'> 		vdd-supply = &lt;&amp;reg_dldo1&gt;;</div><div class='ctx'> 		vddio-supply = &lt;&amp;reg_dldo1&gt;;</div><div class='add'>+		mount-matrix = "0", "1", "0",</div><div class='add'>+				"-1", "0", "0",</div><div class='add'>+				"0", "0", "1";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Light/proximity sensor */</div><div class='add'>+	light-sensor@48 {</div><div class='add'>+		compatible = "sensortek,stk3311";</div><div class='add'>+		reg = &lt;0x48&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;pio&gt;;</div><div class='add'>+		interrupts = &lt;1 0 IRQ_TYPE_EDGE_FALLING&gt;; /* PB0 */</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	/* Accelerometer/gyroscope */</div><div class='del'>-	mpu6050@68 {</div><div class='add'>+	accelerometer@68 {</div><div class='ctx'> 		compatible = "invensense,mpu6050";</div><div class='ctx'> 		reg = &lt;0x68&gt;;</div><div class='ctx'> 		interrupt-parent = &lt;&amp;pio&gt;;</div><div class='ctx'> 		interrupts = &lt;7 5 IRQ_TYPE_EDGE_RISING&gt;; /* PH5 */</div><div class='ctx'> 		vdd-supply = &lt;&amp;reg_dldo1&gt;;</div><div class='ctx'> 		vddio-supply = &lt;&amp;reg_dldo1&gt;;</div><div class='add'>+		mount-matrix = "0", "1", "0",</div><div class='add'>+			       "-1", "0", "0",</div><div class='add'>+			       "0", "0", "1";</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -121,6 +243,7 @@</div><div class='ctx'> </div><div class='ctx'> &amp;lradc {</div><div class='ctx'> 	vref-supply = &lt;&amp;reg_aldo3&gt;;</div><div class='add'>+	wakeup-source;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='ctx'> 	button-200 {</div><div class='hunk'>@@ -149,6 +272,20 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;mmc1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc1_pins&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_vbat_wifi&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_dldo4&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	rtl8723cs: wifi@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;mmc2 {</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;mmc2_pins&gt;;</div><div class='hunk'>@@ -188,6 +325,10 @@</div><div class='ctx'> 	 */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;r_pwm {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;r_rsb {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='hunk'>@@ -195,16 +336,12 @@</div><div class='ctx'> 		compatible = "x-powers,axp803";</div><div class='ctx'> 		reg = &lt;0x3a3&gt;;</div><div class='ctx'> 		interrupt-parent = &lt;&amp;r_intc&gt;;</div><div class='del'>-		interrupts = &lt;0 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #include "axp803.dtsi"</div><div class='ctx'> </div><div class='del'>-&amp;ac_power_supply {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> &amp;battery_power_supply {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='hunk'>@@ -224,8 +361,8 @@</div><div class='ctx'> </div><div class='ctx'> &amp;reg_aldo3 {</div><div class='ctx'> 	regulator-always-on;</div><div class='del'>-	regulator-min-microvolt = &lt;2700000&gt;;</div><div class='del'>-	regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	regulator-min-microvolt = &lt;3000000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;3000000&gt;;</div><div class='ctx'> 	regulator-name = "vcc-pll-avcc";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -279,7 +416,7 @@</div><div class='ctx'> </div><div class='ctx'> &amp;reg_dldo4 {</div><div class='ctx'> 	regulator-min-microvolt = &lt;1800000&gt;;</div><div class='del'>-	regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 	regulator-name = "vcc-wifi-io";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -329,6 +466,7 @@</div><div class='ctx'> </div><div class='ctx'> &amp;sound {</div><div class='ctx'> 	status = "okay";</div><div class='add'>+	simple-audio-card,name = "PinePhone";</div><div class='ctx'> 	simple-audio-card,aux-devs = &lt;&amp;codec_analog&gt;, &lt;&amp;speaker_amp&gt;;</div><div class='ctx'> 	simple-audio-card,widgets = "Microphone", "Headset Microphone",</div><div class='ctx'> 				    "Microphone", "Internal Microphone",</div><div class='hunk'>@@ -342,14 +480,31 @@</div><div class='ctx'> 			"Internal Speaker", "Speaker Amp OUTR",</div><div class='ctx'> 			"Speaker Amp INL", "LINEOUT",</div><div class='ctx'> 			"Speaker Amp INR", "LINEOUT",</div><div class='del'>-			"Left DAC", "AIF1 Slot 0 Left",</div><div class='del'>-			"Right DAC", "AIF1 Slot 0 Right",</div><div class='del'>-			"AIF1 Slot 0 Left ADC", "Left ADC",</div><div class='del'>-			"AIF1 Slot 0 Right ADC", "Right ADC",</div><div class='add'>+			"Left DAC", "DACL",</div><div class='add'>+			"Right DAC", "DACR",</div><div class='add'>+			"ADCL", "Left ADC",</div><div class='add'>+			"ADCR", "Right ADC",</div><div class='ctx'> 			"Internal Microphone", "MBIAS",</div><div class='ctx'> 			"MIC1", "Internal Microphone",</div><div class='ctx'> 			"Headset Microphone", "HBIAS",</div><div class='ctx'> 			"MIC2", "Headset Microphone";</div><div class='add'>+</div><div class='add'>+	simple-audio-card,dai-link@2 {</div><div class='add'>+		format = "dsp_a";</div><div class='add'>+		frame-master = &lt;&amp;link2_codec&gt;;</div><div class='add'>+		bitclock-master = &lt;&amp;link2_codec&gt;;</div><div class='add'>+		bitclock-inversion;</div><div class='add'>+</div><div class='add'>+		link2_cpu: cpu {</div><div class='add'>+			sound-dai = &lt;&amp;bt_sco_codec 0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		link2_codec: codec {</div><div class='add'>+			sound-dai = &lt;&amp;codec 2&gt;;</div><div class='add'>+			dai-tdm-slot-num = &lt;1&gt;;</div><div class='add'>+			dai-tdm-slot-width = &lt;32&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;uart0 {</div><div class='hunk'>@@ -358,6 +513,19 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart1_pins&gt;, &lt;&amp;uart1_rts_cts_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "realtek,rtl8723cs-bt";</div><div class='add'>+		device-wake-gpios = &lt;&amp;pio 7 6 GPIO_ACTIVE_LOW&gt;; /* PH6 */</div><div class='add'>+		enable-gpios = &lt;&amp;r_pio 0 4 GPIO_ACTIVE_HIGH&gt;; /* PL4 */</div><div class='add'>+		host-wake-gpios = &lt;&amp;r_pio 0 5 GPIO_ACTIVE_HIGH&gt;; /* PL5 */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /* Connected to the modem (hardware flow control can't be used) */</div><div class='ctx'> &amp;uart3 {</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab-early-adopter.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab-early-adopter.dts<br/>new file mode 100644<br/>index 000000000000..86cc85eb3d48<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab-early-adopter.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab-early-adopter.dts</a></div><div class='hunk'>@@ -0,0 +1,26 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2020 Icenowy Zheng &lt;icenowy@aosc.io&gt;</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "sun50i-a64-pinetab.dts"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Pine64 PineTab Early Adopter";</div><div class='add'>+	compatible = "pine64,pinetab-early-adopter", "allwinner,sun50i-a64";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsi {</div><div class='add'>+	/delete-node/ panel@0;</div><div class='add'>+</div><div class='add'>+	panel@0 {</div><div class='add'>+		compatible = "feixin,k101-im2byl02", "ilitek,ili9881c";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		power-supply = &lt;&amp;reg_dc1sw&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pio 3 24 GPIO_ACTIVE_LOW&gt;; /* PD24 */</div><div class='add'>+		backlight = &lt;&amp;backlight&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts<br/>index 316e8a443913..f5fb1ee32dad 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts</a></div><div class='hunk'>@@ -14,8 +14,9 @@</div><div class='ctx'> #include &lt;dt-bindings/pwm/pwm.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='del'>-	model = "PineTab";</div><div class='add'>+	model = "Pine64 PineTab Developer Sample";</div><div class='ctx'> 	compatible = "pine64,pinetab", "allwinner,sun50i-a64";</div><div class='add'>+	chassis-type = "tablet";</div><div class='ctx'> </div><div class='ctx'> 	aliases {</div><div class='ctx'> 		serial0 = &amp;uart0;</div><div class='hunk'>@@ -35,6 +36,17 @@</div><div class='ctx'> 		stdout-path = "serial0:115200n8";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	hdmi-connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		type = "c";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			hdmi_con_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_out_con&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	i2c-csi {</div><div class='ctx'> 		compatible = "i2c-gpio";</div><div class='ctx'> 		sda-gpios = &lt;&amp;pio 4 13 GPIO_ACTIVE_HIGH&gt;; /* PE13 */</div><div class='hunk'>@@ -77,7 +89,7 @@</div><div class='ctx'> 		sound-name-prefix = "Speaker Amp";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vdd_bl: regulator@0 {</div><div class='add'>+	vdd_bl: regulator {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "bl-3v3";</div><div class='ctx'> 		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='hunk'>@@ -86,7 +98,7 @@</div><div class='ctx'> 		enable-active-high;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	wifi_pwrseq: wifi_pwrseq {</div><div class='add'>+	wifi_pwrseq: pwrseq {</div><div class='ctx'> 		compatible = "mmc-pwrseq-simple";</div><div class='ctx'> 		reset-gpios = &lt;&amp;r_pio 0 2 GPIO_ACTIVE_LOW&gt;; /* PL2 */</div><div class='ctx'> 		post-power-on-delay-ms = &lt;200&gt;;</div><div class='hunk'>@@ -98,7 +110,7 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;codec_analog {</div><div class='del'>-	hpvcc-supply = &lt;&amp;reg_eldo1&gt;;</div><div class='add'>+	cpvdd-supply = &lt;&amp;reg_eldo1&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -122,9 +134,6 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='ctx'> 	port {</div><div class='del'>-		#address-cells = &lt;1&gt;;</div><div class='del'>-		#size-cells = &lt;0&gt;;</div><div class='del'>-</div><div class='ctx'> 		csi_ep: endpoint {</div><div class='ctx'> 			remote-endpoint = &lt;&amp;ov5640_ep&gt;;</div><div class='ctx'> 			bus-width = &lt;8&gt;;</div><div class='hunk'>@@ -269,7 +278,7 @@</div><div class='ctx'> 		compatible = "x-powers,axp803";</div><div class='ctx'> 		reg = &lt;0x3a3&gt;;</div><div class='ctx'> 		interrupt-parent = &lt;&amp;r_intc&gt;;</div><div class='del'>-		interrupts = &lt;0 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 		x-powers,drive-vbus-en;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='hunk'>@@ -413,6 +422,21 @@</div><div class='ctx'> 	regulator-name = "vcc-rtc";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;simplefb_hdmi {</div><div class='add'>+	vcc-hdmi-supply = &lt;&amp;reg_dldo1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi {</div><div class='add'>+	hvcc-supply = &lt;&amp;reg_dldo1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_out {</div><div class='add'>+	hdmi_out_con: endpoint {</div><div class='add'>+		remote-endpoint = &lt;&amp;hdmi_con_in&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;sound {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> 	simple-audio-card,aux-devs = &lt;&amp;codec_analog&gt;, &lt;&amp;speaker_amp&gt;;</div><div class='hunk'>@@ -421,15 +445,15 @@</div><div class='ctx'> 				    "Headphone", "Headphone Jack",</div><div class='ctx'> 				    "Speaker", "Internal Speaker";</div><div class='ctx'> 	simple-audio-card,routing =</div><div class='del'>-			"Left DAC", "AIF1 Slot 0 Left",</div><div class='del'>-			"Right DAC", "AIF1 Slot 0 Right",</div><div class='add'>+			"Left DAC", "DACL",</div><div class='add'>+			"Right DAC", "DACR",</div><div class='ctx'> 			"Speaker Amp INL", "LINEOUT",</div><div class='ctx'> 			"Speaker Amp INR", "LINEOUT",</div><div class='ctx'> 			"Internal Speaker", "Speaker Amp OUTL",</div><div class='ctx'> 			"Internal Speaker", "Speaker Amp OUTR",</div><div class='ctx'> 			"Headphone Jack", "HP",</div><div class='del'>-			"AIF1 Slot 0 Left ADC", "Left ADC",</div><div class='del'>-			"AIF1 Slot 0 Right ADC", "Right ADC",</div><div class='add'>+			"ADCL", "Left ADC",</div><div class='add'>+			"ADCR", "Right ADC",</div><div class='ctx'> 			"Internal Microphone Left", "MBIAS",</div><div class='ctx'> 			"MIC1", "Internal Microphone Left",</div><div class='ctx'> 			"Internal Microphone Right", "HBIAS",</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts<br/>index 2f6ea9f3f6a2..231e652cab67 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts</a></div><div class='hunk'>@@ -8,7 +8,7 @@</div><div class='ctx'> #include "sun50i-a64-sopine.dtsi"</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='del'>-	model = "SoPine with baseboard";</div><div class='add'>+	model = "Pine64 SOPINE on Baseboard carrier board";</div><div class='ctx'> 	compatible = "pine64,sopine-baseboard", "pine64,sopine",</div><div class='ctx'> 		     "allwinner,sun50i-a64";</div><div class='ctx'> </div><div class='hunk'>@@ -79,7 +79,7 @@</div><div class='ctx'> &amp;emac {</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;rgmii_pins&gt;;</div><div class='del'>-	phy-mode = "rgmii";</div><div class='add'>+	phy-mode = "rgmii-txid";</div><div class='ctx'> 	phy-handle = &lt;&amp;ext_rgmii_phy&gt;;</div><div class='ctx'> 	phy-supply = &lt;&amp;reg_dc1sw&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='hunk'>@@ -103,6 +103,17 @@</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+/* On Wifi/BT connector */</div><div class='add'>+&amp;mmc1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc1_pins&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_dldo4&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_eldo1&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;mmc2 {</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;mmc2_pins&gt;;</div><div class='hunk'>@@ -111,6 +122,7 @@</div><div class='ctx'> 	bus-width = &lt;8&gt;;</div><div class='ctx'> 	non-removable;</div><div class='ctx'> 	cap-mmc-hw-reset;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -159,11 +171,11 @@</div><div class='ctx'> 	simple-audio-card,widgets = "Microphone", "Microphone Jack",</div><div class='ctx'> 				    "Headphone", "Headphone Jack";</div><div class='ctx'> 	simple-audio-card,routing =</div><div class='del'>-			"Left DAC", "AIF1 Slot 0 Left",</div><div class='del'>-			"Right DAC", "AIF1 Slot 0 Right",</div><div class='add'>+			"Left DAC", "DACL",</div><div class='add'>+			"Right DAC", "DACR",</div><div class='ctx'> 			"Headphone Jack", "HP",</div><div class='del'>-			"AIF1 Slot 0 Left ADC", "Left ADC",</div><div class='del'>-			"AIF1 Slot 0 Right ADC", "Right ADC",</div><div class='add'>+			"ADCL", "Left ADC",</div><div class='add'>+			"ADCR", "Right ADC",</div><div class='ctx'> 			"MIC2", "Microphone Jack";</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='hunk'>@@ -174,6 +186,14 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+/* On Wifi/BT connector, with RTS/CTS */</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart1_pins&gt;, &lt;&amp;uart1_rts_cts_pins&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /* On Pi-2 connector */</div><div class='ctx'> &amp;uart2 {</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi<br/>index c48692b06e1f..6d78a1c98f10 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi</a></div><div class='hunk'>@@ -32,10 +32,9 @@</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;mmc0_pins&gt;;</div><div class='ctx'> 	vmmc-supply = &lt;&amp;reg_dcdc1&gt;;</div><div class='del'>-	non-removable;</div><div class='ctx'> 	disable-wp;</div><div class='ctx'> 	bus-width = &lt;4&gt;;</div><div class='del'>-	cd-gpios = &lt;&amp;pio 5 6 GPIO_ACTIVE_LOW&gt;; /* PF6 */</div><div class='add'>+	cd-gpios = &lt;&amp;pio 5 6 GPIO_ACTIVE_HIGH&gt;; /* PF6 push-pull switch */</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -46,7 +45,7 @@</div><div class='ctx'> 		compatible = "x-powers,axp803";</div><div class='ctx'> 		reg = &lt;0x3a3&gt;;</div><div class='ctx'> 		interrupt-parent = &lt;&amp;r_intc&gt;;</div><div class='del'>-		interrupts = &lt;0 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts<br/>index f5df5f705b72..ec055510af8b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts</a></div><div class='hunk'>@@ -14,6 +14,7 @@</div><div class='ctx'> / {</div><div class='ctx'> 	model = "Olimex A64 Teres-I";</div><div class='ctx'> 	compatible = "olimex,a64-teres-i", "allwinner,sun50i-a64";</div><div class='add'>+	chassis-type = "laptop";</div><div class='ctx'> </div><div class='ctx'> 	aliases {</div><div class='ctx'> 		serial0 = &amp;uart0;</div><div class='hunk'>@@ -52,12 +53,12 @@</div><div class='ctx'> 	leds {</div><div class='ctx'> 		compatible = "gpio-leds";</div><div class='ctx'> </div><div class='del'>-		capslock {</div><div class='add'>+		led-0 {</div><div class='ctx'> 			label = "teres-i:green:capslock";</div><div class='ctx'> 			gpios = &lt;&amp;pio 2 7 GPIO_ACTIVE_HIGH&gt;; /* PC7 */</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		numlock {</div><div class='add'>+		led-1 {</div><div class='ctx'> 			label = "teres-i:green:numlock";</div><div class='ctx'> 			gpios = &lt;&amp;pio 2 4 GPIO_ACTIVE_HIGH&gt;; /* PC4 */</div><div class='ctx'> 		};</div><div class='hunk'>@@ -73,7 +74,7 @@</div><div class='ctx'> 		status = "okay";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	wifi_pwrseq: wifi_pwrseq {</div><div class='add'>+	wifi_pwrseq: pwrseq {</div><div class='ctx'> 		compatible = "mmc-pwrseq-simple";</div><div class='ctx'> 		reset-gpios = &lt;&amp;r_pio 0 2 GPIO_ACTIVE_LOW&gt;; /* PL2 */</div><div class='ctx'> 	};</div><div class='hunk'>@@ -139,6 +140,8 @@</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> </div><div class='ctx'> 			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+</div><div class='ctx'> 				anx6345_in: endpoint {</div><div class='ctx'> 					remote-endpoint = &lt;&amp;tcon0_out_anx6345&gt;;</div><div class='ctx'> 				};</div><div class='hunk'>@@ -194,6 +197,14 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;pio {</div><div class='add'>+	vcc-pc-supply = &lt;&amp;reg_dcdc1&gt;;</div><div class='add'>+	vcc-pd-supply = &lt;&amp;reg_dldo2&gt;;</div><div class='add'>+	vcc-pe-supply = &lt;&amp;reg_aldo1&gt;;</div><div class='add'>+	vcc-pf-supply = &lt;&amp;reg_dcdc1&gt;;  /* No dedicated supply-pin for this */</div><div class='add'>+	vcc-pg-supply = &lt;&amp;reg_aldo2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;pwm {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='hunk'>@@ -205,8 +216,7 @@</div><div class='ctx'> 		compatible = "x-powers,axp803";</div><div class='ctx'> 		reg = &lt;0x3a3&gt;;</div><div class='ctx'> 		interrupt-parent = &lt;&amp;r_intc&gt;;</div><div class='del'>-		interrupts = &lt;0 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='del'>-		wakeup-source;</div><div class='add'>+		interrupts = &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -340,10 +350,10 @@</div><div class='ctx'> 				    "Microphone", "Internal Microphone",</div><div class='ctx'> 				    "Speaker", "Internal Speaker";</div><div class='ctx'> 	simple-audio-card,routing =</div><div class='del'>-			"Left DAC", "AIF1 Slot 0 Left",</div><div class='del'>-			"Right DAC", "AIF1 Slot 0 Right",</div><div class='del'>-			"AIF1 Slot 0 Left ADC", "Left ADC",</div><div class='del'>-			"AIF1 Slot 0 Right ADC", "Right ADC",</div><div class='add'>+			"Left DAC", "DACL",</div><div class='add'>+			"Right DAC", "DACR",</div><div class='add'>+			"ADCL", "Left ADC",</div><div class='add'>+			"ADCR", "Right ADC",</div><div class='ctx'> 			"Headphone Jack", "HP",</div><div class='ctx'> 			"Speaker Amp INL", "LINEOUT",</div><div class='ctx'> 			"Speaker Amp INR", "LINEOUT",</div><div class='hunk'>@@ -359,6 +369,8 @@</div><div class='ctx'> &amp;tcon0 {</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;lcd_rgb666_pins&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;ccu CLK_TCON0&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;ccu CLK_PLL_VIDEO0_2X&gt;;</div><div class='ctx'> </div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi<br/>index 31143fe64d91..0fecf0abb204 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi</a></div><div class='hunk'>@@ -4,6 +4,7 @@</div><div class='ctx'> //    Copyright (C) 2015 Jens Kuske &lt;jenskuske@gmail.com&gt;</div><div class='ctx'> </div><div class='ctx'> #include &lt;dt-bindings/clock/sun50i-a64-ccu.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/sun6i-rtc.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/clock/sun8i-de2.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/clock/sun8i-r-ccu.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='hunk'>@@ -50,10 +51,16 @@</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			reg = &lt;0&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='del'>-			next-level-cache = &lt;&amp;L2&gt;;</div><div class='del'>-			clocks = &lt;&amp;ccu 21&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_CPUX&gt;;</div><div class='ctx'> 			clock-names = "cpu";</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu1: cpu@1 {</div><div class='hunk'>@@ -61,10 +68,16 @@</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			reg = &lt;1&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='del'>-			next-level-cache = &lt;&amp;L2&gt;;</div><div class='del'>-			clocks = &lt;&amp;ccu 21&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_CPUX&gt;;</div><div class='ctx'> 			clock-names = "cpu";</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu2: cpu@2 {</div><div class='hunk'>@@ -72,10 +85,16 @@</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			reg = &lt;2&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='del'>-			next-level-cache = &lt;&amp;L2&gt;;</div><div class='del'>-			clocks = &lt;&amp;ccu 21&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_CPUX&gt;;</div><div class='ctx'> 			clock-names = "cpu";</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu3: cpu@3 {</div><div class='hunk'>@@ -83,15 +102,25 @@</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			reg = &lt;3&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='del'>-			next-level-cache = &lt;&amp;L2&gt;;</div><div class='del'>-			clocks = &lt;&amp;ccu 21&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_CPUX&gt;;</div><div class='ctx'> 			clock-names = "cpu";</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		L2: l2-cache {</div><div class='add'>+		l2_cache: l2-cache {</div><div class='ctx'> 			compatible = "cache";</div><div class='ctx'> 			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x80000&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;512&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -102,14 +131,22 @@</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	osc24M: osc24M_clk {</div><div class='add'>+	gpu_opp_table: opp-table-gpu {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		opp-432000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;432000000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	osc24M: osc24M-clk {</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='ctx'> 		compatible = "fixed-clock";</div><div class='ctx'> 		clock-frequency = &lt;24000000&gt;;</div><div class='ctx'> 		clock-output-names = "osc24M";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	osc32k: osc32k_clk {</div><div class='add'>+	osc32k: osc32k-clk {</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='ctx'> 		compatible = "fixed-clock";</div><div class='ctx'> 		clock-frequency = &lt;32768&gt;;</div><div class='hunk'>@@ -131,50 +168,38 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	sound: sound {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='ctx'> 		compatible = "simple-audio-card";</div><div class='ctx'> 		simple-audio-card,name = "sun50i-a64-audio";</div><div class='del'>-		simple-audio-card,format = "i2s";</div><div class='del'>-		simple-audio-card,frame-master = &lt;&amp;cpudai&gt;;</div><div class='del'>-		simple-audio-card,bitclock-master = &lt;&amp;cpudai&gt;;</div><div class='del'>-		simple-audio-card,mclk-fs = &lt;128&gt;;</div><div class='ctx'> 		simple-audio-card,aux-devs = &lt;&amp;codec_analog&gt;;</div><div class='ctx'> 		simple-audio-card,routing =</div><div class='del'>-				"Left DAC", "AIF1 Slot 0 Left",</div><div class='del'>-				"Right DAC", "AIF1 Slot 0 Right",</div><div class='del'>-				"AIF1 Slot 0 Left ADC", "Left ADC",</div><div class='del'>-				"AIF1 Slot 0 Right ADC", "Right ADC";</div><div class='add'>+				"Left DAC", "DACL",</div><div class='add'>+				"Right DAC", "DACR",</div><div class='add'>+				"ADCL", "Left ADC",</div><div class='add'>+				"ADCR", "Right ADC";</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> </div><div class='del'>-		cpudai: simple-audio-card,cpu {</div><div class='del'>-			sound-dai = &lt;&amp;dai&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		link_codec: simple-audio-card,codec {</div><div class='del'>-			sound-dai = &lt;&amp;codec&gt;;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='add'>+		simple-audio-card,dai-link@0 {</div><div class='add'>+			format = "i2s";</div><div class='add'>+			frame-master = &lt;&amp;link0_cpu&gt;;</div><div class='add'>+			bitclock-master = &lt;&amp;link0_cpu&gt;;</div><div class='add'>+			mclk-fs = &lt;128&gt;;</div><div class='ctx'> </div><div class='del'>-	sound_spdif {</div><div class='del'>-		compatible = "simple-audio-card";</div><div class='del'>-		simple-audio-card,name = "On-board SPDIF";</div><div class='del'>-</div><div class='del'>-		simple-audio-card,cpu {</div><div class='del'>-			sound-dai = &lt;&amp;spdif&gt;;</div><div class='del'>-		};</div><div class='add'>+			link0_cpu: cpu {</div><div class='add'>+				sound-dai = &lt;&amp;dai&gt;;</div><div class='add'>+			};</div><div class='ctx'> </div><div class='del'>-		simple-audio-card,codec {</div><div class='del'>-			sound-dai = &lt;&amp;spdif_out&gt;;</div><div class='add'>+			link0_codec: codec {</div><div class='add'>+				sound-dai = &lt;&amp;codec 0&gt;;</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	spdif_out: spdif-out {</div><div class='del'>-		#sound-dai-cells = &lt;0&gt;;</div><div class='del'>-		compatible = "linux,spdif-dit";</div><div class='del'>-	};</div><div class='del'>-</div><div class='ctx'> 	timer {</div><div class='ctx'> 		compatible = "arm,armv8-timer";</div><div class='ctx'> 		allwinner,erratum-unknown1;</div><div class='add'>+		arm,no-tick-in-suspend;</div><div class='ctx'> 		interrupts = &lt;GIC_PPI 13</div><div class='ctx'> 			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)&gt;,</div><div class='ctx'> 			     &lt;GIC_PPI 14</div><div class='hunk'>@@ -210,21 +235,21 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			trips {</div><div class='del'>-				cpu_alert0: cpu_alert0 {</div><div class='add'>+				cpu_alert0: cpu-alert0 {</div><div class='ctx'> 					/* milliCelsius */</div><div class='ctx'> 					temperature = &lt;75000&gt;;</div><div class='ctx'> 					hysteresis = &lt;2000&gt;;</div><div class='ctx'> 					type = "passive";</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				cpu_alert1: cpu_alert1 {</div><div class='add'>+				cpu_alert1: cpu-alert1 {</div><div class='ctx'> 					/* milliCelsius */</div><div class='ctx'> 					temperature = &lt;90000&gt;;</div><div class='ctx'> 					hysteresis = &lt;2000&gt;;</div><div class='ctx'> 					type = "hot";</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				cpu_crit: cpu_crit {</div><div class='add'>+				cpu_crit: cpu-crit {</div><div class='ctx'> 					/* milliCelsius */</div><div class='ctx'> 					temperature = &lt;110000&gt;;</div><div class='ctx'> 					hysteresis = &lt;2000&gt;;</div><div class='hunk'>@@ -238,6 +263,14 @@</div><div class='ctx'> 			polling-delay-passive = &lt;0&gt;;</div><div class='ctx'> 			polling-delay = &lt;0&gt;;</div><div class='ctx'> 			thermal-sensors = &lt;&amp;ths 1&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				gpu0_crit: gpu0-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		gpu1_thermal: gpu1-thermal {</div><div class='hunk'>@@ -245,6 +278,14 @@</div><div class='ctx'> 			polling-delay-passive = &lt;0&gt;;</div><div class='ctx'> 			polling-delay = &lt;0&gt;;</div><div class='ctx'> 			thermal-sensors = &lt;&amp;ths 2&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				gpu1_crit: gpu1-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -402,8 +443,10 @@</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;ccu CLK_BUS_TCON0&gt;, &lt;&amp;ccu CLK_TCON0&gt;;</div><div class='ctx'> 			clock-names = "ahb", "tcon-ch0";</div><div class='del'>-			clock-output-names = "tcon-pixel-clock";</div><div class='add'>+			clock-output-names = "tcon-data-clock";</div><div class='ctx'> 			#clock-cells = &lt;0&gt;;</div><div class='add'>+			assigned-clocks = &lt;&amp;ccu CLK_TCON0&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;ccu CLK_PLL_MIPI&gt;;</div><div class='ctx'> 			resets = &lt;&amp;ccu RST_BUS_TCON0&gt;, &lt;&amp;ccu RST_BUS_LVDS&gt;;</div><div class='ctx'> 			reset-names = "lcd", "lvds";</div><div class='ctx'> </div><div class='hunk'>@@ -531,7 +574,7 @@</div><div class='ctx'> 			resets = &lt;&amp;ccu RST_BUS_MMC2&gt;;</div><div class='ctx'> 			reset-names = "ahb";</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			max-frequency = &lt;200000000&gt;;</div><div class='add'>+			max-frequency = &lt;150000000&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='hunk'>@@ -557,6 +600,16 @@</div><div class='ctx'> 			resets = &lt;&amp;ccu RST_BUS_CE&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		msgbox: mailbox@1c17000 {</div><div class='add'>+			compatible = "allwinner,sun50i-a64-msgbox",</div><div class='add'>+				     "allwinner,sun6i-a31-msgbox";</div><div class='add'>+			reg = &lt;0x01c17000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_MSGBOX&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_MSGBOX&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#mbox-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		usb_otg: usb@1c19000 {</div><div class='ctx'> 			compatible = "allwinner,sun8i-a33-musb";</div><div class='ctx'> 			reg = &lt;0x01c19000 0x0400&gt;;</div><div class='hunk'>@@ -600,6 +653,8 @@</div><div class='ctx'> 				 &lt;&amp;ccu CLK_USB_OHCI0&gt;;</div><div class='ctx'> 			resets = &lt;&amp;ccu RST_BUS_OHCI0&gt;,</div><div class='ctx'> 				 &lt;&amp;ccu RST_BUS_EHCI0&gt;;</div><div class='add'>+			phys = &lt;&amp;usbphy 0&gt;;</div><div class='add'>+			phy-names = "usb";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -610,6 +665,8 @@</div><div class='ctx'> 			clocks = &lt;&amp;ccu CLK_BUS_OHCI0&gt;,</div><div class='ctx'> 				 &lt;&amp;ccu CLK_USB_OHCI0&gt;;</div><div class='ctx'> 			resets = &lt;&amp;ccu RST_BUS_OHCI0&gt;;</div><div class='add'>+			phys = &lt;&amp;usbphy 0&gt;;</div><div class='add'>+			phy-names = "usb";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -642,7 +699,7 @@</div><div class='ctx'> 		ccu: clock@1c20000 {</div><div class='ctx'> 			compatible = "allwinner,sun50i-a64-ccu";</div><div class='ctx'> 			reg = &lt;0x01c20000 0x400&gt;;</div><div class='del'>-			clocks = &lt;&amp;osc24M&gt;, &lt;&amp;rtc 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;osc24M&gt;, &lt;&amp;rtc CLK_OSC32K&gt;;</div><div class='ctx'> 			clock-names = "hosc", "losc";</div><div class='ctx'> 			#clock-cells = &lt;1&gt;;</div><div class='ctx'> 			#reset-cells = &lt;1&gt;;</div><div class='hunk'>@@ -651,16 +708,30 @@</div><div class='ctx'> 		pio: pinctrl@1c20800 {</div><div class='ctx'> 			compatible = "allwinner,sun50i-a64-pinctrl";</div><div class='ctx'> 			reg = &lt;0x01c20800 0x400&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;r_intc&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 				     &lt;GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 				     &lt;GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;ccu CLK_BUS_PIO&gt;, &lt;&amp;osc24M&gt;, &lt;&amp;rtc 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_PIO&gt;, &lt;&amp;osc24M&gt;,</div><div class='add'>+				 &lt;&amp;rtc CLK_OSC32K&gt;;</div><div class='ctx'> 			clock-names = "apb", "hosc", "losc";</div><div class='ctx'> 			gpio-controller;</div><div class='ctx'> 			#gpio-cells = &lt;3&gt;;</div><div class='ctx'> 			interrupt-controller;</div><div class='ctx'> 			#interrupt-cells = &lt;3&gt;;</div><div class='ctx'> </div><div class='add'>+			/omit-if-no-ref/</div><div class='add'>+			aif2_pins: aif2-pins {</div><div class='add'>+				pins = "PB4", "PB5", "PB6", "PB7";</div><div class='add'>+				function = "aif2";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/omit-if-no-ref/</div><div class='add'>+			aif3_pins: aif3-pins {</div><div class='add'>+				pins = "PG10", "PG11", "PG12", "PG13";</div><div class='add'>+				function = "aif3";</div><div class='add'>+			};</div><div class='add'>+</div><div class='ctx'> 			csi_pins: csi-pins {</div><div class='ctx'> 				pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6",</div><div class='ctx'> 				       "PE7", "PE8", "PE9", "PE10", "PE11";</div><div class='hunk'>@@ -801,6 +872,23 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		timer@1c20c00 {</div><div class='add'>+			compatible = "allwinner,sun50i-a64-timer",</div><div class='add'>+				     "allwinner,sun8i-a23-timer";</div><div class='add'>+			reg = &lt;0x01c20c00 0xa0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;osc24M&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wdt0: watchdog@1c20ca0 {</div><div class='add'>+			compatible = "allwinner,sun50i-a64-wdt",</div><div class='add'>+				     "allwinner,sun6i-a31-wdt";</div><div class='add'>+			reg = &lt;0x01c20ca0 0x20&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;osc24M&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		spdif: spdif@1c21000 {</div><div class='ctx'> 			#sound-dai-cells = &lt;0&gt;;</div><div class='ctx'> 			compatible = "allwinner,sun50i-a64-spdif",</div><div class='hunk'>@@ -821,6 +909,7 @@</div><div class='ctx'> 			compatible = "allwinner,sun50i-a64-lradc",</div><div class='ctx'> 				     "allwinner,sun8i-a83t-r-lradc";</div><div class='ctx'> 			reg = &lt;0x01c21800 0x400&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;r_intc&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='hunk'>@@ -853,6 +942,20 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		i2s2: i2s@1c22800 {</div><div class='add'>+			#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+			compatible = "allwinner,sun50i-a64-i2s",</div><div class='add'>+				     "allwinner,sun8i-h3-i2s";</div><div class='add'>+			reg = &lt;0x01c22800 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_I2S2&gt;, &lt;&amp;ccu CLK_I2S2&gt;;</div><div class='add'>+			clock-names = "apb", "mod";</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_I2S2&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+			dmas = &lt;&amp;dma 27&gt;, &lt;&amp;dma 27&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		dai: dai@1c22c00 {</div><div class='ctx'> 			#sound-dai-cells = &lt;0&gt;;</div><div class='ctx'> 			compatible = "allwinner,sun50i-a64-codec-i2s";</div><div class='hunk'>@@ -867,8 +970,9 @@</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		codec: codec@1c22e00 {</div><div class='del'>-			#sound-dai-cells = &lt;0&gt;;</div><div class='del'>-			compatible = "allwinner,sun8i-a33-codec";</div><div class='add'>+			#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+			compatible = "allwinner,sun50i-a64-codec",</div><div class='add'>+				     "allwinner,sun8i-a33-codec";</div><div class='ctx'> 			reg = &lt;0x01c22e00 0x600&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;ccu CLK_BUS_CODEC&gt;, &lt;&amp;ccu CLK_AC_DIG&gt;;</div><div class='hunk'>@@ -1055,6 +1159,7 @@</div><div class='ctx'> 			clocks = &lt;&amp;ccu CLK_BUS_GPU&gt;, &lt;&amp;ccu CLK_GPU&gt;;</div><div class='ctx'> 			clock-names = "bus", "core";</div><div class='ctx'> 			resets = &lt;&amp;ccu RST_BUS_GPU&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;gpu_opp_table&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		gic: interrupt-controller@1c81000 {</div><div class='hunk'>@@ -1081,8 +1186,16 @@</div><div class='ctx'> </div><div class='ctx'> 		mbus: dram-controller@1c62000 {</div><div class='ctx'> 			compatible = "allwinner,sun50i-a64-mbus";</div><div class='del'>-			reg = &lt;0x01c62000 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;ccu 112&gt;;</div><div class='add'>+			reg = &lt;0x01c62000 0x1000&gt;,</div><div class='add'>+			      &lt;0x01c63000 0x1000&gt;;</div><div class='add'>+			reg-names = "mbus", "dram";</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_MBUS&gt;,</div><div class='add'>+				 &lt;&amp;ccu CLK_DRAM&gt;,</div><div class='add'>+				 &lt;&amp;ccu CLK_BUS_DRAM&gt;;</div><div class='add'>+			clock-names = "mbus", "dram", "bus";</div><div class='add'>+			interrupts = &lt;GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='ctx'> 			dma-ranges = &lt;0x00000000 0x40000000 0xc0000000&gt;;</div><div class='ctx'> 			#interconnect-cells = &lt;1&gt;;</div><div class='ctx'> 		};</div><div class='hunk'>@@ -1124,6 +1237,7 @@</div><div class='ctx'> 			compatible = "allwinner,sun50i-a64-mipi-dphy",</div><div class='ctx'> 				     "allwinner,sun6i-a31-mipi-dphy";</div><div class='ctx'> 			reg = &lt;0x01ca1000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;ccu CLK_BUS_MIPI_DSI&gt;,</div><div class='ctx'> 				 &lt;&amp;ccu CLK_DSI_DPHY&gt;;</div><div class='ctx'> 			clock-names = "bus", "mod";</div><div class='hunk'>@@ -1153,8 +1267,8 @@</div><div class='ctx'> 			reg-io-width = &lt;1&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;ccu CLK_BUS_HDMI&gt;, &lt;&amp;ccu CLK_HDMI_DDC&gt;,</div><div class='del'>-				 &lt;&amp;ccu CLK_HDMI&gt;;</div><div class='del'>-			clock-names = "iahb", "isfr", "tmds";</div><div class='add'>+				 &lt;&amp;ccu CLK_HDMI&gt;, &lt;&amp;rtc CLK_OSC32K&gt;;</div><div class='add'>+			clock-names = "iahb", "isfr", "tmds", "cec";</div><div class='ctx'> 			resets = &lt;&amp;ccu RST_BUS_HDMI1&gt;;</div><div class='ctx'> 			reset-names = "ctrl";</div><div class='ctx'> 			phys = &lt;&amp;hdmi_phy&gt;;</div><div class='hunk'>@@ -1194,6 +1308,7 @@</div><div class='ctx'> 			compatible = "allwinner,sun50i-a64-rtc",</div><div class='ctx'> 				     "allwinner,sun8i-h3-rtc";</div><div class='ctx'> 			reg = &lt;0x01f00000 0x400&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;r_intc&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 				     &lt;GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clock-output-names = "osc32k", "osc32k-out", "iosc";</div><div class='hunk'>@@ -1205,7 +1320,7 @@</div><div class='ctx'> 			compatible = "allwinner,sun50i-a64-r-intc",</div><div class='ctx'> 				     "allwinner,sun6i-a31-r-intc";</div><div class='ctx'> 			interrupt-controller;</div><div class='del'>-			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='ctx'> 			reg = &lt;0x01f00c00 0x400&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		};</div><div class='hunk'>@@ -1213,7 +1328,7 @@</div><div class='ctx'> 		r_ccu: clock@1f01400 {</div><div class='ctx'> 			compatible = "allwinner,sun50i-a64-r-ccu";</div><div class='ctx'> 			reg = &lt;0x01f01400 0x100&gt;;</div><div class='del'>-			clocks = &lt;&amp;osc24M&gt;, &lt;&amp;rtc 0&gt;, &lt;&amp;rtc 2&gt;,</div><div class='add'>+			clocks = &lt;&amp;osc24M&gt;, &lt;&amp;rtc CLK_OSC32K&gt;, &lt;&amp;rtc CLK_IOSC&gt;,</div><div class='ctx'> 				 &lt;&amp;ccu CLK_PLL_PERIPH0&gt;;</div><div class='ctx'> 			clock-names = "hosc", "losc", "iosc", "pll-periph";</div><div class='ctx'> 			#clock-cells = &lt;1&gt;;</div><div class='hunk'>@@ -1265,6 +1380,7 @@</div><div class='ctx'> 		r_pio: pinctrl@1f02c00 {</div><div class='ctx'> 			compatible = "allwinner,sun50i-a64-r-pinctrl";</div><div class='ctx'> 			reg = &lt;0x01f02c00 0x400&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;r_intc&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;r_ccu CLK_APB0_PIO&gt;, &lt;&amp;osc24M&gt;, &lt;&amp;osc32k&gt;;</div><div class='ctx'> 			clock-names = "apb", "hosc", "losc";</div><div class='hunk'>@@ -1307,13 +1423,5 @@</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 		};</div><div class='del'>-</div><div class='del'>-		wdt0: watchdog@1c20ca0 {</div><div class='del'>-			compatible = "allwinner,sun50i-a64-wdt",</div><div class='del'>-				     "allwinner,sun6i-a31-wdt";</div><div class='del'>-			reg = &lt;0x01c20ca0 0x20&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;osc24M&gt;;</div><div class='del'>-		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h313-tanix-tx1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h313-tanix-tx1.dts<br/>new file mode 100644<br/>index 000000000000..7906b79c0389<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h313-tanix-tx1.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h313-tanix-tx1.dts</a></div><div class='hunk'>@@ -0,0 +1,194 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2024 Arm Ltd.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "sun50i-h616.dtsi"</div><div class='add'>+#include "sun50i-h616-cpu-opp.dtsi"</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/linux-event-codes.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Tanix TX1";</div><div class='add'>+	compatible = "oranth,tanix-tx1", "allwinner,sun50i-h616";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+		ethernet0 = &amp;sdio_wifi;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		key {</div><div class='add'>+			label = "hidden";</div><div class='add'>+			linux,code = &lt;BTN_0&gt;;</div><div class='add'>+			gpios = &lt;&amp;pio 7 9 GPIO_ACTIVE_LOW&gt;; /* PH9 */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			function = LED_FUNCTION_POWER;</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			gpios = &lt;&amp;pio 7 6 GPIO_ACTIVE_HIGH&gt;; /* PH6 */</div><div class='add'>+			default-state = "on";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wifi_pwrseq: pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-simple";</div><div class='add'>+		clocks = &lt;&amp;rtc CLK_OSC32K_FANOUT&gt;;</div><div class='add'>+		clock-names = "ext_clock";</div><div class='add'>+		pinctrl-0 = &lt;&amp;x32clk_fanout_pin&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		reset-gpios = &lt;&amp;pio 6 18 GPIO_ACTIVE_LOW&gt;; /* PG18 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc5v: vcc5v {</div><div class='add'>+		/* board wide 5V supply directly from the DC input */</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vcc-5v";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;codec {</div><div class='add'>+	allwinner,audio-routing = "Line Out", "LINEOUT";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_dcdc2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ehci0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	mali-supply = &lt;&amp;reg_dcdc1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ir {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc1 {</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_dldo1&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_aldo1&gt;;</div><div class='add'>+	mmc-pwrseq = &lt;&amp;wifi_pwrseq&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	sdio_wifi: wifi@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc2 {</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_dldo1&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_aldo1&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	max-frequency = &lt;100000000&gt;;</div><div class='add'>+	cap-mmc-hw-reset;</div><div class='add'>+	mmc-ddr-1_8v;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ohci0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	vcc-pc-supply = &lt;&amp;reg_aldo1&gt;;</div><div class='add'>+	vcc-pf-supply = &lt;&amp;reg_dldo1&gt;;</div><div class='add'>+	vcc-pg-supply = &lt;&amp;reg_aldo1&gt;;</div><div class='add'>+	vcc-ph-supply = &lt;&amp;reg_dldo1&gt;;</div><div class='add'>+	vcc-pi-supply = &lt;&amp;reg_dldo1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;r_i2c {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	axp313: pmic@36 {</div><div class='add'>+		compatible = "x-powers,axp313a";</div><div class='add'>+		reg = &lt;0x36&gt;;</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+</div><div class='add'>+		vin1-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vin2-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vin3-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			/* Supplies VCC-PLL, so needs to be always on. */</div><div class='add'>+			reg_aldo1: aldo1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "vcc1v8";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* Supplies VCC-IO, so needs to be always on. */</div><div class='add'>+			reg_dldo1: dldo1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "vcc3v3";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_dcdc1: dcdc1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;810000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;990000&gt;;</div><div class='add'>+				regulator-name = "vdd-gpu-sys";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_dcdc2: dcdc2 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;810000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1120000&gt;;</div><div class='add'>+				regulator-name = "vdd-cpu";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_dcdc3: dcdc3 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-name = "vdd-dram";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart0_ph_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg {</div><div class='add'>+	dr_mode = "host";       /* USB A type receptable */</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbphy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h313-x96q.dts b/arch/arm64/boot/dts/allwinner/sun50i-h313-x96q.dts<br/>new file mode 100644<br/>index 000000000000..b2275eb3d55b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h313-x96q.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h313-x96q.dts</a></div><div class='hunk'>@@ -0,0 +1,230 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2025 J. Neuschäfer &lt;j.ne@posteo.net&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "sun50i-h616.dtsi"</div><div class='add'>+#include "sun50i-h616-cpu-opp.dtsi"</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/linux-event-codes.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "X96Q";</div><div class='add'>+	compatible = "amediatech,x96q", "allwinner,sun50i-h616";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc5v: vcc5v {</div><div class='add'>+		/* board wide 5V supply directly from the DC input */</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vcc-5v";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		key-recovery {</div><div class='add'>+			label = "Recovery";</div><div class='add'>+			linux,code = &lt;KEY_VENDOR&gt;;</div><div class='add'>+			gpios = &lt;&amp;pio 7 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			gpios = &lt;&amp;pio 7 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "on";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;codec {</div><div class='add'>+	allwinner,audio-routing = "Line Out", "LINEOUT";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_dcdca&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ehci0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ehci3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* TODO: EMAC1 connected to AC200 PHY */</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	mali-supply = &lt;&amp;reg_dcdcc&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ir {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc0 {</div><div class='add'>+	/* microSD */</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_aldo1&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;pio 5 6 GPIO_ACTIVE_LOW&gt;;	/* PF6 */</div><div class='add'>+	disable-wp;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* TODO: XRadio XR819 WLAN @ mmc1 */</div><div class='add'>+</div><div class='add'>+&amp;mmc2 {</div><div class='add'>+	/* eMMC */</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_aldo1&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_bldo1&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	cap-mmc-hw-reset;</div><div class='add'>+	mmc-ddr-1_8v;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	max-frequency = &lt;100000000&gt;; /* required for stable operation */</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ohci0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ohci3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;r_i2c {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	axp305: pmic@36 {</div><div class='add'>+		compatible = "x-powers,axp305", "x-powers,axp805",</div><div class='add'>+			     "x-powers,axp806";</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		reg = &lt;0x36&gt;;</div><div class='add'>+</div><div class='add'>+		x-powers,self-working-mode;</div><div class='add'>+		vina-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vinb-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vinc-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vind-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vine-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		aldoin-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		bldoin-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		cldoin-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			reg_dcdca: dcdca {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;810000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-name = "vdd-cpu";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			dcdcb {</div><div class='add'>+				/* unused */</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_dcdcc: dcdcc {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;810000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;990000&gt;;</div><div class='add'>+				regulator-name = "vdd-gpu-sys";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			dcdcd {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;1500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1500000&gt;;</div><div class='add'>+				regulator-name = "vdd-dram";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			dcdce {</div><div class='add'>+				/* unused */</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_aldo1: aldo1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "vcc3v3";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			aldo2 {</div><div class='add'>+				/* unused */</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			aldo3 {</div><div class='add'>+				/* unused */</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_bldo1: bldo1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "vcc1v8";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			bldo2 {</div><div class='add'>+				/* unused */</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			bldo3 {</div><div class='add'>+				/* unused */</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			bldo4 {</div><div class='add'>+				/* unused */</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cldo1 {</div><div class='add'>+				/* unused */</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cldo2 {</div><div class='add'>+				/* unused */</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cldo3 {</div><div class='add'>+				/* unused */</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart0_ph_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg {</div><div class='add'>+	dr_mode = "host";	/* USB A type receptacle */</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbphy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus-v1.2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus-v1.2.dts<br/>index 2e2b14c0ae75..6406a29c85f2 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus-v1.2.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus-v1.2.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus-v1.2.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus-v1.2.dts</a></div><div class='hunk'>@@ -3,7 +3,8 @@</div><div class='ctx'> </div><div class='ctx'> /dts-v1/;</div><div class='ctx'> #include "sun50i-h5.dtsi"</div><div class='del'>-#include &lt;arm/sunxi-bananapi-m2-plus-v1.2.dtsi&gt;</div><div class='add'>+#include "sun50i-h5-cpu-opp.dtsi"</div><div class='add'>+#include &lt;arm/allwinner/sunxi-bananapi-m2-plus-v1.2.dtsi&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	model = "Banana Pi BPI-M2-Plus v1.2 H5";</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts<br/>index 77661006dfba..cfb943e9ae85 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts</a></div><div class='hunk'>@@ -3,7 +3,7 @@</div><div class='ctx'> </div><div class='ctx'> /dts-v1/;</div><div class='ctx'> #include "sun50i-h5.dtsi"</div><div class='del'>-#include &lt;arm/sunxi-bananapi-m2-plus.dtsi&gt;</div><div class='add'>+#include &lt;arm/allwinner/sunxi-bananapi-m2-plus.dtsi&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	model = "Banana Pi BPI-M2-Plus H5";</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi<br/>new file mode 100644<br/>index 000000000000..1afad8b437d7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi</a></div><div class='hunk'>@@ -0,0 +1,79 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+// Copyright (C) 2020 Chen-Yu Tsai &lt;wens@csie.org&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	cpu_opp_table: opp-table-cpu {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+		opp-shared;</div><div class='add'>+</div><div class='add'>+		opp-408000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;408000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1000000 1000000 1310000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;244144&gt;; /* 8 32k periods */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-648000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;648000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1040000 1040000 1310000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;244144&gt;; /* 8 32k periods */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-816000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;816000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1080000 1080000 1310000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;244144&gt;; /* 8 32k periods */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-912000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;912000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1120000 1120000 1310000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;244144&gt;; /* 8 32k periods */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-960000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;960000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1160000 1160000 1310000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;244144&gt;; /* 8 32k periods */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1008000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1008000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1200000 1200000 1310000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;244144&gt;; /* 8 32k periods */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1056000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1056000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1240000 1240000 1310000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;244144&gt;; /* 8 32k periods */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1104000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1104000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1260000 1260000 1310000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;244144&gt;; /* 8 32k periods */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1152000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1152000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1300000 1300000 1310000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;244144&gt;; /* 8 32k periods */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu1 {</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu2 {</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu3 {</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5.dtsi<br/>index fc570011495f..2f4b46746f47 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5.dtsi</a></div><div class='hunk'>@@ -8,4 +8,4 @@</div><div class='ctx'> /dts-v1/;</div><div class='ctx'> </div><div class='ctx'> #include "sun50i-h5.dtsi"</div><div class='del'>-#include &lt;arm/sunxi-h3-h5-emlid-neutis.dtsi&gt;</div><div class='add'>+#include &lt;arm/allwinner/sunxi-h3-h5-emlid-neutis.dtsi&gt;</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-cc.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-cc.dts<br/>index 64d35daf2023..b79018c65cae 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-cc.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-cc.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-cc.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-cc.dts</a></div><div class='hunk'>@@ -4,7 +4,8 @@</div><div class='ctx'> </div><div class='ctx'> /dts-v1/;</div><div class='ctx'> #include "sun50i-h5.dtsi"</div><div class='del'>-#include &lt;arm/sunxi-libretech-all-h3-cc.dtsi&gt;</div><div class='add'>+#include "sun50i-h5-cpu-opp.dtsi"</div><div class='add'>+#include &lt;arm/allwinner/sunxi-libretech-all-h3-cc.dtsi&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	model = "Libre Computer Board ALL-H3-CC H5";</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-it.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-it.dts<br/>index e59d68b525fc..dc657de2a1a4 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-it.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-it.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-it.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-it.dts</a></div><div class='hunk'>@@ -3,7 +3,7 @@</div><div class='ctx'> </div><div class='ctx'> /dts-v1/;</div><div class='ctx'> #include "sun50i-h5.dtsi"</div><div class='del'>-#include &lt;arm/sunxi-libretech-all-h3-it.dtsi&gt;</div><div class='add'>+#include &lt;arm/allwinner/sunxi-libretech-all-h3-it.dtsi&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	model = "Libre Computer Board ALL-H3-IT H5";</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h5-cc.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h5-cc.dts<br/>index df1b9263ad0e..6e30a564c87f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h5-cc.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h5-cc.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h5-cc.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h5-cc.dts</a></div><div class='hunk'>@@ -36,7 +36,7 @@</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;emac_rgmii_pins&gt;;</div><div class='ctx'> 	phy-supply = &lt;&amp;reg_gmac_3v3&gt;;</div><div class='ctx'> 	phy-handle = &lt;&amp;ext_rgmii_phy&gt;;</div><div class='del'>-	phy-mode = "rgmii";</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='ctx'> 	/delete-property/ allwinner,leds-active-low;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts<br/>index 4f9ba53ffaae..18fa541795a6 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts</a></div><div class='hunk'>@@ -25,13 +25,13 @@</div><div class='ctx'> 	leds {</div><div class='ctx'> 		compatible = "gpio-leds";</div><div class='ctx'> </div><div class='del'>-		pwr {</div><div class='add'>+		led-0 {</div><div class='ctx'> 			label = "nanopi:green:pwr";</div><div class='ctx'> 			gpios = &lt;&amp;r_pio 0 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 			default-state = "on";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		status {</div><div class='add'>+		led-1 {</div><div class='ctx'> 			label = "nanopi:red:status";</div><div class='ctx'> 			gpios = &lt;&amp;pio 0 20 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 		};</div><div class='hunk'>@@ -45,16 +45,40 @@</div><div class='ctx'> 		startup-delay-us = &lt;100000&gt;;</div><div class='ctx'> 		enable-active-high;</div><div class='ctx'> 		gpio = &lt;&amp;pio 3 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;reg_vcc3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_gmac_2v5: gmac-2v5 {</div><div class='add'>+		/* 2V5 supply for GMAC PHY IO */</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "gmac-2v5";</div><div class='add'>+		regulator-min-microvolt = &lt;2500000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;2500000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		vin-supply = &lt;&amp;reg_vcc3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc5v: regulator-vcc5v {</div><div class='add'>+		/* board 5V supply from micro USB or pin headers */</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vcc-5v";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	reg_vcc3v3: vcc3v3 {</div><div class='add'>+		/* board 3V3 supply by SY8089A */</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "vcc3v3";</div><div class='ctx'> 		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='ctx'> 		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		vin-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	vdd_cpux: gpio-regulator {</div><div class='add'>+		/* cpu voltage regulator MP2143DJ */</div><div class='ctx'> 		compatible = "regulator-gpio";</div><div class='ctx'> 		regulator-name = "vdd-cpux";</div><div class='ctx'> 		regulator-type = "voltage";</div><div class='hunk'>@@ -66,9 +90,10 @@</div><div class='ctx'> 		gpios = &lt;&amp;r_pio 0 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 		gpios-states = &lt;0x1&gt;;</div><div class='ctx'> 		states = &lt;1100000 0&gt;, &lt;1300000 1&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	wifi_pwrseq: wifi_pwrseq {</div><div class='add'>+	wifi_pwrseq: pwrseq {</div><div class='ctx'> 		compatible = "mmc-pwrseq-simple";</div><div class='ctx'> 		reset-gpios = &lt;&amp;r_pio 0 7 GPIO_ACTIVE_LOW&gt;; /* PL7 */</div><div class='ctx'> 		post-power-on-delay-ms = &lt;200&gt;;</div><div class='hunk'>@@ -96,7 +121,7 @@</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;emac_rgmii_pins&gt;;</div><div class='ctx'> 	phy-supply = &lt;&amp;reg_gmac_3v3&gt;;</div><div class='ctx'> 	phy-handle = &lt;&amp;ext_rgmii_phy&gt;;</div><div class='del'>-	phy-mode = "rgmii";</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -111,6 +136,7 @@</div><div class='ctx'> 	vmmc-supply = &lt;&amp;reg_vcc3v3&gt;;</div><div class='ctx'> 	bus-width = &lt;4&gt;;</div><div class='ctx'> 	cd-gpios = &lt;&amp;pio 5 6 GPIO_ACTIVE_LOW&gt;; /* PF6 */</div><div class='add'>+	disable-wp;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -146,6 +172,18 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;pio {</div><div class='add'>+	vcc-pa-supply = &lt;&amp;reg_vcc3v3&gt;;</div><div class='add'>+	vcc-pc-supply = &lt;&amp;reg_vcc3v3&gt;;</div><div class='add'>+	vcc-pd-supply = &lt;&amp;reg_gmac_2v5&gt;;</div><div class='add'>+	vcc-pf-supply = &lt;&amp;reg_vcc3v3&gt;;</div><div class='add'>+	vcc-pg-supply = &lt;&amp;reg_vcc3v3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;r_pio {</div><div class='add'>+	vcc-pl-supply = &lt;&amp;reg_vcc3v3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;uart0 {</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;uart0_pa_pins&gt;;</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts<br/>index b059e20813bd..128295f5a5d6 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts</a></div><div class='hunk'>@@ -22,13 +22,13 @@</div><div class='ctx'> 	leds {</div><div class='ctx'> 		compatible = "gpio-leds";</div><div class='ctx'> </div><div class='del'>-		pwr {</div><div class='add'>+		led-0 {</div><div class='ctx'> 			label = "nanopi:green:pwr";</div><div class='ctx'> 			gpios = &lt;&amp;r_pio 0 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 			default-state = "on";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		status {</div><div class='add'>+		led-1 {</div><div class='ctx'> 			label = "nanopi:blue:status";</div><div class='ctx'> 			gpios = &lt;&amp;pio 0 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 		};</div><div class='hunk'>@@ -75,7 +75,7 @@</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;emac_rgmii_pins&gt;;</div><div class='ctx'> 	phy-supply = &lt;&amp;reg_gmac_3v3&gt;;</div><div class='ctx'> 	phy-handle = &lt;&amp;ext_rgmii_phy&gt;;</div><div class='del'>-	phy-mode = "rgmii";</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -88,6 +88,7 @@</div><div class='ctx'> </div><div class='ctx'> &amp;mmc0 {</div><div class='ctx'> 	vmmc-supply = &lt;&amp;reg_vcc3v3&gt;;</div><div class='add'>+	disable-wp;</div><div class='ctx'> 	bus-width = &lt;4&gt;;</div><div class='ctx'> 	cd-gpios = &lt;&amp;pio 5 6 GPIO_ACTIVE_LOW&gt;; /* PF6 */</div><div class='ctx'> 	status = "okay";</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts<br/>new file mode 100644<br/>index 000000000000..44fdc8b3f79d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts</a></div><div class='hunk'>@@ -0,0 +1,203 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2021 Chukun Pan &lt;amadeus@jmu.edu.cn&gt;</div><div class='add'>+ *</div><div class='add'>+ * Based on sun50i-h5-nanopi-neo-plus2.dts, which is:</div><div class='add'>+ *   Copyright (C) 2017 Antony Antony &lt;antony@phenome.org&gt;</div><div class='add'>+ *   Copyright (C) 2016 ARM Ltd.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "sun50i-h5.dtsi"</div><div class='add'>+#include "sun50i-h5-cpu-opp.dtsi"</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "FriendlyARM NanoPi R1S H5";</div><div class='add'>+	compatible = "friendlyarm,nanopi-r1s-h5", "allwinner,sun50i-h5";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;emac;</div><div class='add'>+		ethernet1 = &amp;rtl8189etv;</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			function = LED_FUNCTION_LAN;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			gpios = &lt;&amp;pio 0 9 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			gpios = &lt;&amp;pio 0 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-2 {</div><div class='add'>+			function = LED_FUNCTION_WAN;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			gpios = &lt;&amp;pio 6 11 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		key-reset {</div><div class='add'>+			label = "reset";</div><div class='add'>+			linux,code = &lt;KEY_RESTART&gt;;</div><div class='add'>+			gpios = &lt;&amp;r_pio 0 3 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_gmac_3v3: gmac-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "gmac-3v3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		startup-delay-us = &lt;100000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;pio 3 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc3v3: vcc3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vcc3v3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb0_vbus: usb0-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "usb0-vbus";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;r_pio 0 2 GPIO_ACTIVE_HIGH&gt;; /* PL2 */</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_cpux: gpio-regulator {</div><div class='add'>+		compatible = "regulator-gpio";</div><div class='add'>+		regulator-name = "vdd-cpux";</div><div class='add'>+		regulator-type = "voltage";</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-min-microvolt = &lt;1100000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+		regulator-ramp-delay = &lt;50&gt;; /* 4ms */</div><div class='add'>+		gpios = &lt;&amp;r_pio 0 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		gpios-states = &lt;0x1&gt;;</div><div class='add'>+		states = &lt;1100000 0x0&gt;, &lt;1300000 0x1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wifi_pwrseq: pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-simple";</div><div class='add'>+		reset-gpios = &lt;&amp;r_pio 0 7 GPIO_ACTIVE_LOW&gt;; /* PL7 */</div><div class='add'>+		post-power-on-delay-ms = &lt;200&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	cpu-supply = &lt;&amp;vdd_cpux&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ehci1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ehci2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;emac {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;emac_rgmii_pins&gt;;</div><div class='add'>+	phy-supply = &lt;&amp;reg_gmac_3v3&gt;;</div><div class='add'>+	phy-handle = &lt;&amp;ext_rgmii_phy&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;external_mdio {</div><div class='add'>+	ext_rgmii_phy: ethernet-phy@7 {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+		reg = &lt;7&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	eeprom@51 {</div><div class='add'>+		compatible = "microchip,24c02", "atmel,24c02";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+		read-only;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		eth_mac1: mac-address@fa {</div><div class='add'>+			reg = &lt;0xfa 0x06&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc0 {</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_vcc3v3&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;pio 5 6 GPIO_ACTIVE_LOW&gt;; /* PF6 */</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc1 {</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_vcc3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_vcc3v3&gt;;</div><div class='add'>+	mmc-pwrseq = &lt;&amp;wifi_pwrseq&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	rtl8189etv: wifi@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ohci1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ohci2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart0_pa_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_otg {</div><div class='add'>+	dr_mode = "peripheral";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbphy {</div><div class='add'>+	/* USB Type-A port's VBUS is always on */</div><div class='add'>+	usb0_id_det-gpios = &lt;&amp;pio 6 12 GPIO_ACTIVE_HIGH&gt;; /* PG12 */</div><div class='add'>+	usb0_vbus-supply = &lt;&amp;reg_usb0_vbus&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts<br/>index 7d7aad18f078..0f29da7d51e6 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts</a></div><div class='hunk'>@@ -3,6 +3,7 @@</div><div class='ctx'> </div><div class='ctx'> /dts-v1/;</div><div class='ctx'> #include "sun50i-h5.dtsi"</div><div class='add'>+#include "sun50i-h5-cpu-opp.dtsi"</div><div class='ctx'> </div><div class='ctx'> #include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/input/input.h&gt;</div><div class='hunk'>@@ -42,22 +43,22 @@</div><div class='ctx'> 	leds {</div><div class='ctx'> 		compatible = "gpio-leds";</div><div class='ctx'> </div><div class='del'>-		pwr {</div><div class='add'>+		led-0 {</div><div class='ctx'> 			label = "orangepi:green:pwr";</div><div class='ctx'> 			gpios = &lt;&amp;r_pio 0 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 			default-state = "on";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		status {</div><div class='add'>+		led-1 {</div><div class='ctx'> 			label = "orangepi:red:status";</div><div class='ctx'> 			gpios = &lt;&amp;pio 0 20 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	r-gpio-keys {</div><div class='add'>+	gpio-keys {</div><div class='ctx'> 		compatible = "gpio-keys";</div><div class='ctx'> </div><div class='del'>-		sw4 {</div><div class='add'>+		key-sw4 {</div><div class='ctx'> 			label = "sw4";</div><div class='ctx'> 			linux,code = &lt;BTN_0&gt;;</div><div class='ctx'> 			gpios = &lt;&amp;r_pio 0 3 GPIO_ACTIVE_LOW&gt;;</div><div class='hunk'>@@ -123,7 +124,7 @@</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;emac_rgmii_pins&gt;;</div><div class='ctx'> 	phy-supply = &lt;&amp;reg_gmac_3v3&gt;;</div><div class='ctx'> 	phy-handle = &lt;&amp;ext_rgmii_phy&gt;;</div><div class='del'>-	phy-mode = "rgmii";</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -152,6 +153,7 @@</div><div class='ctx'> </div><div class='ctx'> &amp;mmc0 {</div><div class='ctx'> 	vmmc-supply = &lt;&amp;reg_vcc3v3&gt;;</div><div class='add'>+	disable-wp;</div><div class='ctx'> 	bus-width = &lt;4&gt;;</div><div class='ctx'> 	cd-gpios = &lt;&amp;pio 5 6 GPIO_ACTIVE_LOW&gt;; /* PF6 */</div><div class='ctx'> 	status = "okay";</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts<br/>index cb44bfa5981f..d4fc4e60e4e7 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts</a></div><div class='hunk'>@@ -36,22 +36,22 @@</div><div class='ctx'> 	leds {</div><div class='ctx'> 		compatible = "gpio-leds";</div><div class='ctx'> </div><div class='del'>-		pwr {</div><div class='add'>+		led-0 {</div><div class='ctx'> 			label = "orangepi:green:pwr";</div><div class='ctx'> 			gpios = &lt;&amp;r_pio 0 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 			default-state = "on";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		status {</div><div class='add'>+		led-1 {</div><div class='ctx'> 			label = "orangepi:red:status";</div><div class='ctx'> 			gpios = &lt;&amp;pio 0 20 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	r-gpio-keys {</div><div class='add'>+	gpio-keys {</div><div class='ctx'> 		compatible = "gpio-keys";</div><div class='ctx'> </div><div class='del'>-		sw4 {</div><div class='add'>+		key-sw4 {</div><div class='ctx'> 			label = "sw4";</div><div class='ctx'> 			linux,code = &lt;BTN_0&gt;;</div><div class='ctx'> 			gpios = &lt;&amp;r_pio 0 3 GPIO_ACTIVE_LOW&gt;;</div><div class='hunk'>@@ -85,7 +85,7 @@</div><div class='ctx'> 		status = "okay";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	wifi_pwrseq: wifi_pwrseq {</div><div class='add'>+	wifi_pwrseq: pwrseq {</div><div class='ctx'> 		compatible = "mmc-pwrseq-simple";</div><div class='ctx'> 		reset-gpios = &lt;&amp;pio 2 14 GPIO_ACTIVE_LOW&gt;; /* PC14 */</div><div class='ctx'> 	};</div><div class='hunk'>@@ -124,7 +124,7 @@</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;emac_rgmii_pins&gt;;</div><div class='ctx'> 	phy-supply = &lt;&amp;reg_gmac_3v3&gt;;</div><div class='ctx'> 	phy-handle = &lt;&amp;ext_rgmii_phy&gt;;</div><div class='del'>-	phy-mode = "rgmii";</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -153,6 +153,7 @@</div><div class='ctx'> </div><div class='ctx'> &amp;mmc0 {</div><div class='ctx'> 	vmmc-supply = &lt;&amp;reg_vcc3v3&gt;;</div><div class='add'>+	disable-wp;</div><div class='ctx'> 	bus-width = &lt;4&gt;;</div><div class='ctx'> 	cd-gpios = &lt;&amp;pio 5 6 GPIO_ACTIVE_LOW&gt;; /* PF6 */</div><div class='ctx'> 	status = "okay";</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts<br/>index ef5ca6444220..3322cc4d9aa4 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts</a></div><div class='hunk'>@@ -33,13 +33,13 @@</div><div class='ctx'> 	leds {</div><div class='ctx'> 		compatible = "gpio-leds";</div><div class='ctx'> </div><div class='del'>-		pwr {</div><div class='add'>+		led-0 {</div><div class='ctx'> 			label = "orangepi:green:pwr";</div><div class='ctx'> 			gpios = &lt;&amp;r_pio 0 10 GPIO_ACTIVE_HIGH&gt;; /* PA10 */</div><div class='ctx'> 			default-state = "on";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		status {</div><div class='add'>+		led-1 {</div><div class='ctx'> 			label = "orangepi:red:status";</div><div class='ctx'> 			gpios = &lt;&amp;pio 0 17 GPIO_ACTIVE_HIGH&gt;; /* PA17 */</div><div class='ctx'> 		};</div><div class='hunk'>@@ -69,7 +69,7 @@</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;emac_rgmii_pins&gt;;</div><div class='ctx'> 	phy-supply = &lt;&amp;reg_gmac_3v3&gt;;</div><div class='ctx'> 	phy-handle = &lt;&amp;ext_rgmii_phy&gt;;</div><div class='del'>-	phy-mode = "rgmii";</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -82,6 +82,7 @@</div><div class='ctx'> </div><div class='ctx'> &amp;mmc0 {</div><div class='ctx'> 	vmmc-supply = &lt;&amp;reg_vcc3v3&gt;;</div><div class='add'>+	disable-wp;</div><div class='ctx'> 	bus-width = &lt;4&gt;;</div><div class='ctx'> 	cd-gpios = &lt;&amp;pio 5 6 GPIO_ACTIVE_LOW&gt;; /* PF6 */</div><div class='ctx'> 	status = "okay";</div><div class='hunk'>@@ -97,7 +98,7 @@</div><div class='ctx'> 	 * Explicitly define the sdio device, so that we can add an ethernet</div><div class='ctx'> 	 * alias for it (which e.g. makes u-boot set a mac-address).</div><div class='ctx'> 	 */</div><div class='del'>-	rtl8189ftv: sdio_wifi@1 {</div><div class='add'>+	rtl8189ftv: wifi@1 {</div><div class='ctx'> 		reg = &lt;1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts<br/>index c95a68541309..3eb986c354a9 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts</a></div><div class='hunk'>@@ -30,6 +30,21 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			label = "orangepi:green:pwr";</div><div class='add'>+			gpios = &lt;&amp;r_pio 0 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "on";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			label = "orangepi:red:status";</div><div class='add'>+			gpios = &lt;&amp;pio 0 17 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	reg_vcc3v3: vcc3v3 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "vcc3v3";</div><div class='hunk'>@@ -37,7 +52,7 @@</div><div class='ctx'> 		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	wifi_pwrseq: wifi_pwrseq {</div><div class='add'>+	wifi_pwrseq: pwrseq {</div><div class='ctx'> 		compatible = "mmc-pwrseq-simple";</div><div class='ctx'> 		reset-gpios = &lt;&amp;pio 0 9 GPIO_ACTIVE_LOW&gt;; /* PA9 */</div><div class='ctx'> 		post-power-on-delay-ms = &lt;200&gt;;</div><div class='hunk'>@@ -48,6 +63,10 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;ehci0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;hdmi {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='hunk'>@@ -60,6 +79,7 @@</div><div class='ctx'> </div><div class='ctx'> &amp;mmc0 {</div><div class='ctx'> 	vmmc-supply = &lt;&amp;reg_vcc3v3&gt;;</div><div class='add'>+	disable-wp;</div><div class='ctx'> 	bus-width = &lt;4&gt;;</div><div class='ctx'> 	cd-gpios = &lt;&amp;pio 5 6 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='hunk'>@@ -92,6 +112,10 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;ohci0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;uart0 {</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;uart0_pa_pins&gt;;</div><div class='hunk'>@@ -103,3 +127,18 @@</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;uart1_pins&gt;, &lt;&amp;uart1_rts_cts_pins&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='add'>+</div><div class='add'>+&amp;usb_otg {</div><div class='add'>+	/*</div><div class='add'>+	 * According to schematics CN1 MicroUSB port can be used to take</div><div class='add'>+	 * external 5V to power up the board VBUS. On the contrary CN1 MicroUSB</div><div class='add'>+	 * port cannot provide power externally even if the board is powered</div><div class='add'>+	 * via GPIO pins. It thus makes sense to force peripheral mode.</div><div class='add'>+	 */</div><div class='add'>+	dr_mode = "peripheral";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbphy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi<br/>index 4462a68c0681..01a29c1988a6 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi</a></div><div class='hunk'>@@ -1,7 +1,9 @@</div><div class='ctx'> // SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='ctx'> // Copyright (C) 2016 ARM Ltd.</div><div class='ctx'> </div><div class='del'>-#include &lt;arm/sunxi-h3-h5.dtsi&gt;</div><div class='add'>+#include &lt;arm/allwinner/sunxi-h3-h5.dtsi&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/thermal/thermal.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	cpus {</div><div class='hunk'>@@ -13,6 +15,8 @@</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			reg = &lt;0&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_CPUX&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu1: cpu@1 {</div><div class='hunk'>@@ -20,6 +24,8 @@</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			reg = &lt;1&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_CPUX&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu2: cpu@2 {</div><div class='hunk'>@@ -27,6 +33,8 @@</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			reg = &lt;2&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_CPUX&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu3: cpu@3 {</div><div class='hunk'>@@ -34,6 +42,8 @@</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			reg = &lt;3&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_CPUX&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -53,6 +63,7 @@</div><div class='ctx'> </div><div class='ctx'> 	timer {</div><div class='ctx'> 		compatible = "arm,armv8-timer";</div><div class='add'>+		arm,no-tick-in-suspend;</div><div class='ctx'> 		interrupts = &lt;GIC_PPI 13</div><div class='ctx'> 				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='ctx'> 			     &lt;GIC_PPI 14</div><div class='hunk'>@@ -106,6 +117,19 @@</div><div class='ctx'> 			resets = &lt;&amp;ccu RST_BUS_CE&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		deinterlace: deinterlace@1e00000 {</div><div class='add'>+			compatible = "allwinner,sun8i-h3-deinterlace";</div><div class='add'>+			reg = &lt;0x01e00000 0x20000&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_DEINTERLACE&gt;,</div><div class='add'>+				 &lt;&amp;ccu CLK_DEINTERLACE&gt;,</div><div class='add'>+				 &lt;&amp;ccu CLK_DRAM_DEINTERLACE&gt;;</div><div class='add'>+			clock-names = "bus", "mod", "ram";</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_DEINTERLACE&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interconnects = &lt;&amp;mbus 9&gt;;</div><div class='add'>+			interconnect-names = "dma-mem";</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		mali: gpu@1e80000 {</div><div class='ctx'> 			compatible = "allwinner,sun50i-h5-mali", "arm,mali-450";</div><div class='ctx'> 			reg = &lt;0x01e80000 0x30000&gt;;</div><div class='hunk'>@@ -125,8 +149,7 @@</div><div class='ctx'> 				     &lt;GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 				     &lt;GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 				     &lt;GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				     &lt;GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				     &lt;GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				     &lt;GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			interrupt-names = "gp",</div><div class='ctx'> 					  "gpmmu",</div><div class='ctx'> 					  "pp",</div><div class='hunk'>@@ -137,8 +160,7 @@</div><div class='ctx'> 					  "pp2",</div><div class='ctx'> 					  "ppmmu2",</div><div class='ctx'> 					  "pp3",</div><div class='del'>-					  "ppmmu3",</div><div class='del'>-					  "pmu";</div><div class='add'>+					  "ppmmu3";</div><div class='ctx'> 			clocks = &lt;&amp;ccu CLK_BUS_GPU&gt;, &lt;&amp;ccu CLK_GPU&gt;;</div><div class='ctx'> 			clock-names = "bus", "core";</div><div class='ctx'> 			resets = &lt;&amp;ccu RST_BUS_GPU&gt;;</div><div class='hunk'>@@ -165,9 +187,33 @@</div><div class='ctx'> 			polling-delay-passive = &lt;0&gt;;</div><div class='ctx'> 			polling-delay = &lt;0&gt;;</div><div class='ctx'> 			thermal-sensors = &lt;&amp;ths 0&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu_hot_trip: cpu-hot {</div><div class='add'>+					temperature = &lt;80000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_very_hot_trip: cpu-very-hot {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu_hot_trip&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		gpu_thermal {</div><div class='add'>+		gpu-thermal {</div><div class='ctx'> 			polling-delay-passive = &lt;0&gt;;</div><div class='ctx'> 			polling-delay = &lt;0&gt;;</div><div class='ctx'> 			thermal-sensors = &lt;&amp;ths 1&gt;;</div><div class='hunk'>@@ -183,6 +229,10 @@</div><div class='ctx'> 	compatible = "allwinner,sun50i-h5-de2-clk";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;mbus {</div><div class='add'>+	compatible = "allwinner,sun50i-h5-mbus";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;mmc0 {</div><div class='ctx'> 	compatible = "allwinner,sun50i-h5-mmc",</div><div class='ctx'> 		     "allwinner,sun50i-a64-mmc";</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts<br/>index 8f09d209359b..2c64d834a2c4 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts</a></div><div class='hunk'>@@ -4,6 +4,8 @@</div><div class='ctx'> /dts-v1/;</div><div class='ctx'> </div><div class='ctx'> #include "sun50i-h6.dtsi"</div><div class='add'>+#include "sun50i-h6-cpu-opp.dtsi"</div><div class='add'>+#include "sun50i-h6-gpu-opp.dtsi"</div><div class='ctx'> </div><div class='ctx'> #include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='ctx'> </div><div class='hunk'>@@ -32,7 +34,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	ext_osc32k: ext_osc32k_clk {</div><div class='add'>+	ext_osc32k: ext-osc32k-clk {</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='ctx'> 		compatible = "fixed-clock";</div><div class='ctx'> 		clock-frequency = &lt;32768&gt;;</div><div class='hunk'>@@ -42,7 +44,7 @@</div><div class='ctx'> 	leds {</div><div class='ctx'> 		compatible = "gpio-leds";</div><div class='ctx'> </div><div class='del'>-		power {</div><div class='add'>+		led {</div><div class='ctx'> 			label = "beelink:white:power";</div><div class='ctx'> 			gpios = &lt;&amp;r_pio 0 4 GPIO_ACTIVE_HIGH&gt;; /* PL4 */</div><div class='ctx'> 			default-state = "on";</div><div class='hunk'>@@ -77,6 +79,10 @@</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_dcdca&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;de {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='hunk'>@@ -92,7 +98,7 @@</div><div class='ctx'> &amp;emac {</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;ext_rgmii_pins&gt;;</div><div class='del'>-	phy-mode = "rgmii";</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='ctx'> 	phy-handle = &lt;&amp;ext_rgmii_phy&gt;;</div><div class='ctx'> 	phy-supply = &lt;&amp;reg_aldo2&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='hunk'>@@ -123,6 +129,7 @@</div><div class='ctx'> &amp;mmc0 {</div><div class='ctx'> 	vmmc-supply = &lt;&amp;reg_cldo1&gt;;</div><div class='ctx'> 	cd-gpios = &lt;&amp;pio 5 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	disable-wp;</div><div class='ctx'> 	bus-width = &lt;4&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='hunk'>@@ -152,7 +159,7 @@</div><div class='ctx'> 		compatible = "x-powers,axp805", "x-powers,axp806";</div><div class='ctx'> 		reg = &lt;0x36&gt;;</div><div class='ctx'> 		interrupt-parent = &lt;&amp;r_intc&gt;;</div><div class='del'>-		interrupts = &lt;0 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 96 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 		interrupt-controller;</div><div class='ctx'> 		#interrupt-cells = &lt;1&gt;;</div><div class='ctx'> 		x-powers,self-working-mode;</div><div class='hunk'>@@ -234,7 +241,8 @@</div><div class='ctx'> 			reg_dcdca: dcdca {</div><div class='ctx'> 				regulator-always-on;</div><div class='ctx'> 				regulator-min-microvolt = &lt;810000&gt;;</div><div class='del'>-				regulator-max-microvolt = &lt;1080000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1160000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;2500&gt;;</div><div class='ctx'> 				regulator-name = "vdd-cpu";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -242,6 +250,7 @@</div><div class='ctx'> 				regulator-enable-ramp-delay = &lt;32000&gt;;</div><div class='ctx'> 				regulator-min-microvolt = &lt;810000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;1080000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;2500&gt;;</div><div class='ctx'> 				regulator-name = "vdd-gpu";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -282,11 +291,9 @@</div><div class='ctx'> 	vcc-pm-supply = &lt;&amp;reg_aldo1&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;rtc {</div><div class='del'>-	clocks = &lt;&amp;ext_osc32k&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> &amp;spdif {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;spdif_tx_pin&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi<br/>new file mode 100644<br/>index 000000000000..0baf0f8e4d27<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi</a></div><div class='hunk'>@@ -0,0 +1,117 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+// Copyright (C) 2020 Ondrej Jirman &lt;megous@megous.com&gt;</div><div class='add'>+// Copyright (C) 2020 Clément Péron &lt;peron.clem@gmail.com&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	cpu_opp_table: opp-table-cpu {</div><div class='add'>+		compatible = "allwinner,sun50i-h6-operating-points";</div><div class='add'>+		nvmem-cells = &lt;&amp;cpu_speed_grade&gt;;</div><div class='add'>+		opp-shared;</div><div class='add'>+</div><div class='add'>+		opp-480000000 {</div><div class='add'>+			clock-latency-ns = &lt;244144&gt;; /* 8 32k periods */</div><div class='add'>+			opp-hz = /bits/ 64 &lt;480000000&gt;;</div><div class='add'>+</div><div class='add'>+			opp-microvolt-speed0 = &lt;880000 880000 1200000&gt;;</div><div class='add'>+			opp-microvolt-speed1 = &lt;820000 820000 1200000&gt;;</div><div class='add'>+			opp-microvolt-speed2 = &lt;820000 820000 1200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-720000000 {</div><div class='add'>+			clock-latency-ns = &lt;244144&gt;; /* 8 32k periods */</div><div class='add'>+			opp-hz = /bits/ 64 &lt;720000000&gt;;</div><div class='add'>+</div><div class='add'>+			opp-microvolt-speed0 = &lt;880000 880000 1200000&gt;;</div><div class='add'>+			opp-microvolt-speed1 = &lt;820000 820000 1200000&gt;;</div><div class='add'>+			opp-microvolt-speed2 = &lt;820000 820000 1200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-816000000 {</div><div class='add'>+			clock-latency-ns = &lt;244144&gt;; /* 8 32k periods */</div><div class='add'>+			opp-hz = /bits/ 64 &lt;816000000&gt;;</div><div class='add'>+</div><div class='add'>+			opp-microvolt-speed0 = &lt;880000 880000 1200000&gt;;</div><div class='add'>+			opp-microvolt-speed1 = &lt;820000 820000 1200000&gt;;</div><div class='add'>+			opp-microvolt-speed2 = &lt;820000 820000 1200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-888000000 {</div><div class='add'>+			clock-latency-ns = &lt;244144&gt;; /* 8 32k periods */</div><div class='add'>+			opp-hz = /bits/ 64 &lt;888000000&gt;;</div><div class='add'>+</div><div class='add'>+			opp-microvolt-speed0 = &lt;880000 880000 1200000&gt;;</div><div class='add'>+			opp-microvolt-speed1 = &lt;820000 820000 1200000&gt;;</div><div class='add'>+			opp-microvolt-speed2 = &lt;820000 820000 1200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1080000000 {</div><div class='add'>+			clock-latency-ns = &lt;244144&gt;; /* 8 32k periods */</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1080000000&gt;;</div><div class='add'>+</div><div class='add'>+			opp-microvolt-speed0 = &lt;940000 940000 1200000&gt;;</div><div class='add'>+			opp-microvolt-speed1 = &lt;880000 880000 1200000&gt;;</div><div class='add'>+			opp-microvolt-speed2 = &lt;880000 880000 1200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1320000000 {</div><div class='add'>+			clock-latency-ns = &lt;244144&gt;; /* 8 32k periods */</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1320000000&gt;;</div><div class='add'>+</div><div class='add'>+			opp-microvolt-speed0 = &lt;1000000 1000000 1200000&gt;;</div><div class='add'>+			opp-microvolt-speed1 = &lt;940000 940000 1200000&gt;;</div><div class='add'>+			opp-microvolt-speed2 = &lt;940000 940000 1200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1488000000 {</div><div class='add'>+			clock-latency-ns = &lt;244144&gt;; /* 8 32k periods */</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1488000000&gt;;</div><div class='add'>+</div><div class='add'>+			opp-microvolt-speed0 = &lt;1060000 1060000 1200000&gt;;</div><div class='add'>+			opp-microvolt-speed1 = &lt;1000000 1000000 1200000&gt;;</div><div class='add'>+			opp-microvolt-speed2 = &lt;1000000 1000000 1200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1608000000 {</div><div class='add'>+			clock-latency-ns = &lt;244144&gt;; /* 8 32k periods */</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1608000000&gt;;</div><div class='add'>+</div><div class='add'>+			opp-microvolt-speed0 = &lt;1090000 1090000 1200000&gt;;</div><div class='add'>+			opp-microvolt-speed1 = &lt;1030000 1030000 1200000&gt;;</div><div class='add'>+			opp-microvolt-speed2 = &lt;1030000 1030000 1200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1704000000 {</div><div class='add'>+			clock-latency-ns = &lt;244144&gt;; /* 8 32k periods */</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1704000000&gt;;</div><div class='add'>+</div><div class='add'>+			opp-microvolt-speed0 = &lt;1120000 1120000 1200000&gt;;</div><div class='add'>+			opp-microvolt-speed1 = &lt;1060000 1060000 1200000&gt;;</div><div class='add'>+			opp-microvolt-speed2 = &lt;1060000 1060000 1200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1800000000 {</div><div class='add'>+			clock-latency-ns = &lt;244144&gt;; /* 8 32k periods */</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1800000000&gt;;</div><div class='add'>+</div><div class='add'>+			opp-microvolt-speed0 = &lt;1160000 1160000 1200000&gt;;</div><div class='add'>+			opp-microvolt-speed1 = &lt;1100000 1100000 1200000&gt;;</div><div class='add'>+			opp-microvolt-speed2 = &lt;1100000 1100000 1200000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu1 {</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu2 {</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu3 {</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi<br/>new file mode 100644<br/>index 000000000000..b48049c4fc85<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi</a></div><div class='hunk'>@@ -0,0 +1,87 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+// Copyright (C) 2022 Clément Péron &lt;peron.clem@gmail.com&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	gpu_opp_table: opp-table-gpu {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		opp-216000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;216000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;810000 810000 1200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-264000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;264000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;810000 810000 1200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-312000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;312000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;810000 810000 1200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-336000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;336000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;810000 810000 1200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-360000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;360000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;820000 820000 1200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-384000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;384000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;830000 830000 1200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-408000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;408000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;840000 840000 1200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-420000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;420000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;850000 850000 1200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-432000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;432000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;860000 860000 1200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-456000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;456000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;870000 870000 1200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-504000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;504000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;890000 890000 1200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-540000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;540000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;910000 910000 1200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-576000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;576000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;930000 930000 1200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-624000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;624000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;950000 950000 1200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-756000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;756000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1040000 1040000 1200000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	operating-points-v2 = &lt;&amp;gpu_opp_table&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts<br/>index 47f579610dcc..dc7381c944c9 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts</a></div><div class='hunk'>@@ -4,6 +4,7 @@</div><div class='ctx'> /dts-v1/;</div><div class='ctx'> </div><div class='ctx'> #include "sun50i-h6.dtsi"</div><div class='add'>+#include "sun50i-h6-cpu-opp.dtsi"</div><div class='ctx'> </div><div class='ctx'> #include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='ctx'> </div><div class='hunk'>@@ -32,7 +33,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	ext_osc32k: ext_osc32k_clk {</div><div class='add'>+	ext_osc32k: ext-osc32k-clk {</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='ctx'> 		compatible = "fixed-clock";</div><div class='ctx'> 		clock-frequency = &lt;32768&gt;;</div><div class='hunk'>@@ -42,13 +43,13 @@</div><div class='ctx'> 	leds {</div><div class='ctx'> 		compatible = "gpio-leds";</div><div class='ctx'> </div><div class='del'>-		power {</div><div class='add'>+		led-0 {</div><div class='ctx'> 			label = "orangepi:red:power";</div><div class='ctx'> 			gpios = &lt;&amp;r_pio 0 4 GPIO_ACTIVE_HIGH&gt;; /* PL4 */</div><div class='ctx'> 			default-state = "on";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		status {</div><div class='add'>+		led-1 {</div><div class='ctx'> 			label = "orangepi:green:status";</div><div class='ctx'> 			gpios = &lt;&amp;r_pio 0 7 GPIO_ACTIVE_HIGH&gt;; /* PL7 */</div><div class='ctx'> 		};</div><div class='hunk'>@@ -85,7 +86,7 @@</div><div class='ctx'> </div><div class='ctx'> 	wifi_pwrseq: wifi-pwrseq {</div><div class='ctx'> 		compatible = "mmc-pwrseq-simple";</div><div class='del'>-		clocks = &lt;&amp;rtc 1&gt;;</div><div class='add'>+		clocks = &lt;&amp;rtc CLK_OSC32K_FANOUT&gt;;</div><div class='ctx'> 		clock-names = "ext_clock";</div><div class='ctx'> 		reset-gpios = &lt;&amp;r_pio 1 3 GPIO_ACTIVE_LOW&gt;; /* PM3 */</div><div class='ctx'> 		post-power-on-delay-ms = &lt;200&gt;;</div><div class='hunk'>@@ -130,6 +131,7 @@</div><div class='ctx'> &amp;mmc0 {</div><div class='ctx'> 	vmmc-supply = &lt;&amp;reg_cldo1&gt;;</div><div class='ctx'> 	cd-gpios = &lt;&amp;pio 5 6 GPIO_ACTIVE_LOW&gt;; /* PF6 */</div><div class='add'>+	disable-wp;</div><div class='ctx'> 	bus-width = &lt;4&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='hunk'>@@ -142,7 +144,7 @@</div><div class='ctx'> 	non-removable;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='del'>-	brcm: sdio-wifi@1 {</div><div class='add'>+	brcm: wifi@1 {</div><div class='ctx'> 		reg = &lt;1&gt;;</div><div class='ctx'> 		compatible = "brcm,bcm4329-fmac";</div><div class='ctx'> 		interrupt-parent = &lt;&amp;r_pio&gt;;</div><div class='hunk'>@@ -181,7 +183,7 @@</div><div class='ctx'> 		compatible = "x-powers,axp805", "x-powers,axp806";</div><div class='ctx'> 		reg = &lt;0x36&gt;;</div><div class='ctx'> 		interrupt-parent = &lt;&amp;r_intc&gt;;</div><div class='del'>-		interrupts = &lt;0 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 96 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 		interrupt-controller;</div><div class='ctx'> 		#interrupt-cells = &lt;1&gt;;</div><div class='ctx'> 		x-powers,self-working-mode;</div><div class='hunk'>@@ -257,6 +259,7 @@</div><div class='ctx'> 				regulator-always-on;</div><div class='ctx'> 				regulator-min-microvolt = &lt;800000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;1160000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;2500&gt;;</div><div class='ctx'> 				regulator-name = "vdd-cpu";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -264,6 +267,7 @@</div><div class='ctx'> 				regulator-enable-ramp-delay = &lt;32000&gt;;</div><div class='ctx'> 				regulator-min-microvolt = &lt;810000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;1080000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;2500&gt;;</div><div class='ctx'> 				regulator-name = "vdd-gpu";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -311,7 +315,7 @@</div><div class='ctx'> </div><div class='ctx'> 	bluetooth {</div><div class='ctx'> 		compatible = "brcm,bcm4345c5";</div><div class='del'>-		clocks = &lt;&amp;rtc 1&gt;;</div><div class='add'>+		clocks = &lt;&amp;rtc CLK_OSC32K_FANOUT&gt;;</div><div class='ctx'> 		clock-names = "lpo";</div><div class='ctx'> 		device-wakeup-gpios = &lt;&amp;r_pio 1 2 GPIO_ACTIVE_HIGH&gt;; /* PM2 */</div><div class='ctx'> 		host-wakeup-gpios = &lt;&amp;r_pio 1 1 GPIO_ACTIVE_HIGH&gt;; /* PM1 */</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts<br/>index e7ca75c0d0f7..0911c537cc6b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts</a></div><div class='hunk'>@@ -6,4 +6,69 @@</div><div class='ctx'> / {</div><div class='ctx'> 	model = "OrangePi Lite2";</div><div class='ctx'> 	compatible = "xunlong,orangepi-lite2", "allwinner,sun50i-h6";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial1 = &amp;uart1; /* BT-UART */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wifi_pwrseq: pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-simple";</div><div class='add'>+		clocks = &lt;&amp;rtc CLK_OSC32K_FANOUT&gt;;</div><div class='add'>+		clock-names = "ext_clock";</div><div class='add'>+		reset-gpios = &lt;&amp;r_pio 1 3 GPIO_ACTIVE_LOW&gt;; /* PM3 */</div><div class='add'>+		post-power-on-delay-ms = &lt;200&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc1 {</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_cldo2&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_bldo3&gt;;</div><div class='add'>+	mmc-pwrseq = &lt;&amp;wifi_pwrseq&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	brcm: wifi@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		compatible = "brcm,bcm4329-fmac";</div><div class='add'>+		interrupt-parent = &lt;&amp;r_pio&gt;;</div><div class='add'>+		interrupts = &lt;1 0 IRQ_TYPE_LEVEL_LOW&gt;;	/* PM0 */</div><div class='add'>+		interrupt-names = "host-wake";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_cldo2 {</div><div class='add'>+	/*</div><div class='add'>+	 * This regulator is connected with CLDO3.</div><div class='add'>+	 * Before the kernel can support synchronized</div><div class='add'>+	 * enable of coupled regulators, keep them</div><div class='add'>+	 * both always on as a ugly hack.</div><div class='add'>+	 */</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_cldo3 {</div><div class='add'>+	/*</div><div class='add'>+	 * This regulator is connected with CLDO2.</div><div class='add'>+	 * See the comments for CLDO2.</div><div class='add'>+	 */</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* There's the BT part of the AP6255 connected to that UART */</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart1_pins&gt;, &lt;&amp;uart1_rts_cts_pins&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "brcm,bcm4345c5";</div><div class='add'>+		clocks = &lt;&amp;rtc CLK_OSC32K_FANOUT&gt;;</div><div class='add'>+		clock-names = "lpo";</div><div class='add'>+		device-wakeup-gpios = &lt;&amp;r_pio 1 2 GPIO_ACTIVE_HIGH&gt;; /* PM2 */</div><div class='add'>+		host-wakeup-gpios = &lt;&amp;r_pio 1 1 GPIO_ACTIVE_HIGH&gt;; /* PM1 */</div><div class='add'>+		shutdown-gpios = &lt;&amp;r_pio 1 4 GPIO_ACTIVE_HIGH&gt;; /* PM4 */</div><div class='add'>+		max-speed = &lt;1500000&gt;;</div><div class='add'>+	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts<br/>index fceb298bfd53..29a081e72a9b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts</a></div><div class='hunk'>@@ -27,7 +27,7 @@</div><div class='ctx'> &amp;emac {</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;ext_rgmii_pins&gt;;</div><div class='del'>-	phy-mode = "rgmii";</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='ctx'> 	phy-handle = &lt;&amp;ext_rgmii_phy&gt;;</div><div class='ctx'> 	phy-supply = &lt;&amp;reg_gmac_3v3&gt;;</div><div class='ctx'> 	allwinner,rx-delay-ps = &lt;200&gt;;</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi<br/>index 9287976c4a50..e34dbb992021 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi</a></div><div class='hunk'>@@ -32,7 +32,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	ext_osc32k: ext_osc32k_clk {</div><div class='add'>+	ext_osc32k: ext-osc32k-clk {</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='ctx'> 		compatible = "fixed-clock";</div><div class='ctx'> 		clock-frequency = &lt;32768&gt;;</div><div class='hunk'>@@ -42,13 +42,13 @@</div><div class='ctx'> 	leds {</div><div class='ctx'> 		compatible = "gpio-leds";</div><div class='ctx'> </div><div class='del'>-		power {</div><div class='add'>+		led-0 {</div><div class='ctx'> 			label = "orangepi:red:power";</div><div class='ctx'> 			gpios = &lt;&amp;r_pio 0 4 GPIO_ACTIVE_HIGH&gt;; /* PL4 */</div><div class='ctx'> 			default-state = "on";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		status {</div><div class='add'>+		led-1 {</div><div class='ctx'> 			label = "orangepi:green:status";</div><div class='ctx'> 			gpios = &lt;&amp;r_pio 0 7 GPIO_ACTIVE_HIGH&gt;; /* PL7 */</div><div class='ctx'> 		};</div><div class='hunk'>@@ -94,6 +94,7 @@</div><div class='ctx'> &amp;mmc0 {</div><div class='ctx'> 	vmmc-supply = &lt;&amp;reg_cldo1&gt;;</div><div class='ctx'> 	cd-gpios = &lt;&amp;pio 5 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	disable-wp;</div><div class='ctx'> 	bus-width = &lt;4&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='hunk'>@@ -106,6 +107,12 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;pio {</div><div class='add'>+	vcc-pc-supply = &lt;&amp;reg_bldo2&gt;;</div><div class='add'>+	vcc-pd-supply = &lt;&amp;reg_cldo1&gt;;</div><div class='add'>+	vcc-pg-supply = &lt;&amp;reg_aldo1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;r_i2c {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='hunk'>@@ -113,7 +120,7 @@</div><div class='ctx'> 		compatible = "x-powers,axp805", "x-powers,axp806";</div><div class='ctx'> 		reg = &lt;0x36&gt;;</div><div class='ctx'> 		interrupt-parent = &lt;&amp;r_intc&gt;;</div><div class='del'>-		interrupts = &lt;0 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 96 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 		interrupt-controller;</div><div class='ctx'> 		#interrupt-cells = &lt;1&gt;;</div><div class='ctx'> 		x-powers,self-working-mode;</div><div class='hunk'>@@ -230,6 +237,10 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;r_pio {</div><div class='add'>+	vcc-pm-supply = &lt;&amp;reg_bldo3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;rtc {</div><div class='ctx'> 	clocks = &lt;&amp;ext_osc32k&gt;;</div><div class='ctx'> };</div><div class='hunk'>@@ -241,7 +252,12 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;usb2otg {</div><div class='del'>-	dr_mode = "otg";</div><div class='add'>+	/*</div><div class='add'>+	 * OrangePi Lite 2 and One Plus, where this DT is used, don't</div><div class='add'>+	 * have a controllable VBUS even though they do have an ID pin.</div><div class='add'>+	 * Using it as anything but a USB host is unsafe.</div><div class='add'>+	 */</div><div class='add'>+	dr_mode = "host";</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts<br/>index f4c8966a6497..066fbeff8bfa 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts</a></div><div class='hunk'>@@ -1,15 +1,21 @@</div><div class='del'>-// SPDX-License-Identifier: (GPL-2.0+ or MIT)</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (C) 2019 Corentin LABBE &lt;clabbe@baylibre.com&gt;</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include "sun50i-h6-pine-h64.dts"</div><div class='ctx'> </div><div class='add'>+/delete-node/ &amp;reg_gmac_3v3;</div><div class='add'>+</div><div class='ctx'> / {</div><div class='del'>-	model = "Pine H64 model B";</div><div class='add'>+	model = "Pine64 PINE H64 Model B";</div><div class='ctx'> 	compatible = "pine64,pine-h64-model-b", "allwinner,sun50i-h6";</div><div class='ctx'> </div><div class='del'>-	/delete-node/ reg_gmac_3v3;</div><div class='add'>+	wifi_pwrseq: pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-simple";</div><div class='add'>+		reset-gpios = &lt;&amp;r_pio 1 3 GPIO_ACTIVE_LOW&gt;; /* PM3 */</div><div class='add'>+		post-power-on-delay-ms = &lt;200&gt;;</div><div class='add'>+	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;hdmi_connector {</div><div class='hunk'>@@ -19,3 +25,27 @@</div><div class='ctx'> &amp;emac {</div><div class='ctx'> 	phy-supply = &lt;&amp;reg_aldo2&gt;;</div><div class='ctx'> };</div><div class='add'>+</div><div class='add'>+&amp;mmc1 {</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_cldo3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_aldo1&gt;;</div><div class='add'>+	mmc-pwrseq = &lt;&amp;wifi_pwrseq&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart1_pins&gt;, &lt;&amp;uart1_rts_cts_pins&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "realtek,rtl8723bs-bt";</div><div class='add'>+		device-wake-gpios = &lt;&amp;r_pio 1 2 GPIO_ACTIVE_HIGH&gt;; /* PM2 */</div><div class='add'>+		host-wake-gpios = &lt;&amp;r_pio 1 1 GPIO_ACTIVE_HIGH&gt;; /* PM1 */</div><div class='add'>+		enable-gpios = &lt;&amp;r_pio 1 4 GPIO_ACTIVE_HIGH&gt;; /* PM4 */</div><div class='add'>+		max-speed = &lt;1500000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts<br/>index b0642d841933..fa7a765ee828 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts</a></div><div class='hunk'>@@ -4,11 +4,12 @@</div><div class='ctx'> /dts-v1/;</div><div class='ctx'> </div><div class='ctx'> #include "sun50i-h6.dtsi"</div><div class='add'>+#include "sun50i-h6-cpu-opp.dtsi"</div><div class='ctx'> </div><div class='ctx'> #include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='del'>-	model = "Pine H64 model A";</div><div class='add'>+	model = "Pine64 PINE H64 Model A";</div><div class='ctx'> 	compatible = "pine64,pine-h64", "allwinner,sun50i-h6";</div><div class='ctx'> </div><div class='ctx'> 	aliases {</div><div class='hunk'>@@ -21,7 +22,7 @@</div><div class='ctx'> 		stdout-path = "serial0:115200n8";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	ext_osc32k: ext_osc32k_clk {</div><div class='add'>+	ext_osc32k: ext-osc32k-clk {</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='ctx'> 		compatible = "fixed-clock";</div><div class='ctx'> 		clock-frequency = &lt;32768&gt;;</div><div class='hunk'>@@ -43,17 +44,17 @@</div><div class='ctx'> 	leds {</div><div class='ctx'> 		compatible = "gpio-leds";</div><div class='ctx'> </div><div class='del'>-		heartbeat {</div><div class='add'>+		led-0 {</div><div class='ctx'> 			label = "pine-h64:green:heartbeat";</div><div class='ctx'> 			gpios = &lt;&amp;r_pio 0 4 GPIO_ACTIVE_HIGH&gt;; /* PL4 */</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		link {</div><div class='add'>+		led-1 {</div><div class='ctx'> 			label = "pine-h64:white:link";</div><div class='ctx'> 			gpios = &lt;&amp;r_pio 0 3 GPIO_ACTIVE_HIGH&gt;; /* PL3 */</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		status {</div><div class='add'>+		led-2 {</div><div class='ctx'> 			label = "pine-h64:blue:status";</div><div class='ctx'> 			gpios = &lt;&amp;r_pio 0 7 GPIO_ACTIVE_HIGH&gt;; /* PL7 */</div><div class='ctx'> 		};</div><div class='hunk'>@@ -80,10 +81,26 @@</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_dcdca&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;de {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ehci0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ehci3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;emac {</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;ext_rgmii_pins&gt;;</div><div class='del'>-	phy-mode = "rgmii";</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='ctx'> 	phy-handle = &lt;&amp;ext_rgmii_phy&gt;;</div><div class='ctx'> 	phy-supply = &lt;&amp;reg_gmac_3v3&gt;;</div><div class='ctx'> 	allwinner,rx-delay-ps = &lt;200&gt;;</div><div class='hunk'>@@ -91,17 +108,6 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;mdio {</div><div class='del'>-	ext_rgmii_phy: ethernet-phy@1 {</div><div class='del'>-		compatible = "ethernet-phy-ieee802.3-c22";</div><div class='del'>-		reg = &lt;1&gt;;</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;de {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> &amp;gpu {</div><div class='ctx'> 	mali-supply = &lt;&amp;reg_dcdcc&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='hunk'>@@ -117,17 +123,17 @@</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;ehci0 {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;ehci3 {</div><div class='del'>-	status = "okay";</div><div class='add'>+&amp;mdio {</div><div class='add'>+	ext_rgmii_phy: ethernet-phy@1 {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;mmc0 {</div><div class='ctx'> 	vmmc-supply = &lt;&amp;reg_cldo1&gt;;</div><div class='ctx'> 	cd-gpios = &lt;&amp;pio 5 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	disable-wp;</div><div class='ctx'> 	bus-width = &lt;4&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='hunk'>@@ -137,6 +143,7 @@</div><div class='ctx'> 	vqmmc-supply = &lt;&amp;reg_bldo2&gt;;</div><div class='ctx'> 	non-removable;</div><div class='ctx'> 	cap-mmc-hw-reset;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='ctx'> 	bus-width = &lt;8&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='hunk'>@@ -162,7 +169,7 @@</div><div class='ctx'> 		compatible = "x-powers,axp805", "x-powers,axp806";</div><div class='ctx'> 		reg = &lt;0x36&gt;;</div><div class='ctx'> 		interrupt-parent = &lt;&amp;r_intc&gt;;</div><div class='del'>-		interrupts = &lt;0 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 96 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 		interrupt-controller;</div><div class='ctx'> 		#interrupt-cells = &lt;1&gt;;</div><div class='ctx'> 		x-powers,self-working-mode;</div><div class='hunk'>@@ -238,7 +245,8 @@</div><div class='ctx'> 			reg_dcdca: dcdca {</div><div class='ctx'> 				regulator-always-on;</div><div class='ctx'> 				regulator-min-microvolt = &lt;810000&gt;;</div><div class='del'>-				regulator-max-microvolt = &lt;1080000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1160000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;2500&gt;;</div><div class='ctx'> 				regulator-name = "vdd-cpu";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -246,6 +254,7 @@</div><div class='ctx'> 				regulator-enable-ramp-delay = &lt;32000&gt;;</div><div class='ctx'> 				regulator-min-microvolt = &lt;810000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;1080000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;2500&gt;;</div><div class='ctx'> 				regulator-name = "vdd-gpu";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -273,7 +282,7 @@</div><div class='ctx'> 		compatible = "nxp,pcf8563";</div><div class='ctx'> 		reg = &lt;0x51&gt;;</div><div class='ctx'> 		interrupt-parent = &lt;&amp;r_intc&gt;;</div><div class='del'>-		interrupts = &lt;0 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 96 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6-mini.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6-mini.dts<br/>new file mode 100644<br/>index 000000000000..08d84160d88f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6-mini.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6-mini.dts</a></div><div class='hunk'>@@ -0,0 +1,15 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+// Copyright (c) 2021 Jernej Skrabec &lt;jernej.skrabec@gmail.com&gt;</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "sun50i-h6-tanix.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Tanix TX6 mini";</div><div class='add'>+	compatible = "oranth,tanix-tx6-mini", "allwinner,sun50i-h6";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;r_ir {</div><div class='add'>+	linux,rc-map-name = "rc-tanix-tx3mini";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts<br/>index 83e6cb0e59ce..9a38ff9b3fc7 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts</a></div><div class='hunk'>@@ -3,109 +3,27 @@</div><div class='ctx'> </div><div class='ctx'> /dts-v1/;</div><div class='ctx'> </div><div class='del'>-#include "sun50i-h6.dtsi"</div><div class='del'>-</div><div class='del'>-#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include "sun50i-h6-tanix.dtsi"</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	model = "Tanix TX6";</div><div class='ctx'> 	compatible = "oranth,tanix-tx6", "allwinner,sun50i-h6";</div><div class='del'>-</div><div class='del'>-	aliases {</div><div class='del'>-		serial0 = &amp;uart0;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	chosen {</div><div class='del'>-		stdout-path = "serial0:115200n8";</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	connector {</div><div class='del'>-		compatible = "hdmi-connector";</div><div class='del'>-		ddc-en-gpios = &lt;&amp;pio 7 2 GPIO_ACTIVE_HIGH&gt;; /* PH2 */</div><div class='del'>-		type = "a";</div><div class='del'>-</div><div class='del'>-		port {</div><div class='del'>-			hdmi_con_in: endpoint {</div><div class='del'>-				remote-endpoint = &lt;&amp;hdmi_out_con&gt;;</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	reg_vcc3v3: vcc3v3 {</div><div class='del'>-		compatible = "regulator-fixed";</div><div class='del'>-		regulator-name = "vcc3v3";</div><div class='del'>-		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;de {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;dwc3 {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;ehci0 {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;ehci3 {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;gpu {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;hdmi {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;hdmi_out {</div><div class='del'>-	hdmi_out_con: endpoint {</div><div class='del'>-		remote-endpoint = &lt;&amp;hdmi_con_in&gt;;</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;mmc0 {</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-	pinctrl-0 = &lt;&amp;mmc0_pins&gt;;</div><div class='del'>-	vmmc-supply = &lt;&amp;reg_vcc3v3&gt;;</div><div class='del'>-	cd-gpios = &lt;&amp;pio 5 6 GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-	bus-width = &lt;4&gt;;</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;ohci0 {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;ohci3 {</div><div class='del'>-	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;r_ir {</div><div class='ctx'> 	linux,rc-map-name = "rc-tanix-tx5max";</div><div class='del'>-	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;uart0 {</div><div class='add'>+&amp;uart1 {</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='del'>-	pinctrl-0 = &lt;&amp;uart0_ph_pins&gt;;</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;usb2otg {</div><div class='del'>-	dr_mode = "host";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart1_pins&gt;, &lt;&amp;uart1_rts_cts_pins&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='ctx'> 	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;usb2phy {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='ctx'> </div><div class='del'>-&amp;usb3phy {</div><div class='del'>-	status = "okay";</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "realtek,rtl8822cs-bt";</div><div class='add'>+		device-wake-gpios = &lt;&amp;r_pio 1 2 GPIO_ACTIVE_HIGH&gt;; /* PM2 */</div><div class='add'>+		host-wake-gpios = &lt;&amp;r_pio 1 1 GPIO_ACTIVE_HIGH&gt;; /* PM1 */</div><div class='add'>+		enable-gpios = &lt;&amp;r_pio 1 4 GPIO_ACTIVE_HIGH&gt;; /* PM4 */</div><div class='add'>+	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi<br/>new file mode 100644<br/>index 000000000000..bb7de37c0d58<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi</a></div><div class='hunk'>@@ -0,0 +1,192 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+// Copyright (c) 2019 Jernej Skrabec &lt;jernej.skrabec@siol.net&gt;</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "sun50i-h6.dtsi"</div><div class='add'>+#include "sun50i-h6-cpu-opp.dtsi"</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		ddc-en-gpios = &lt;&amp;pio 7 2 GPIO_ACTIVE_HIGH&gt;; /* PH2 */</div><div class='add'>+		type = "a";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			hdmi_con_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_out_con&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* used for FD650 LED display driver */</div><div class='add'>+	i2c {</div><div class='add'>+		compatible = "i2c-gpio";</div><div class='add'>+		sda-gpios = &lt;&amp;pio 7 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)&gt;; /* PH6 */</div><div class='add'>+		scl-gpios = &lt;&amp;pio 7 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)&gt;; /* PH5 */</div><div class='add'>+		i2c-gpio,delay-us = &lt;5&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc1v8: regulator-vcc1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vcc1v8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc3v3: regulator-vcc3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vcc3v3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vdd_cpu_gpu: regulator-vdd-cpu-gpu {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vdd-cpu-gpu";</div><div class='add'>+		regulator-min-microvolt = &lt;1135000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1135000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-spdif {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,name = "sun50i-h6-spdif";</div><div class='add'>+</div><div class='add'>+		simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;spdif&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		simple-audio-card,codec {</div><div class='add'>+			sound-dai = &lt;&amp;spdif_out&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spdif_out: spdif-out {</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		compatible = "linux,spdif-dit";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wifi_pwrseq: wifi-pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-simple";</div><div class='add'>+		clocks = &lt;&amp;rtc CLK_OSC32K_FANOUT&gt;;</div><div class='add'>+		clock-names = "ext_clock";</div><div class='add'>+		reset-gpios = &lt;&amp;r_pio 1 3 GPIO_ACTIVE_LOW&gt;; /* PM3 */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_vdd_cpu_gpu&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;de {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dwc3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ehci0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ehci3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	mali-supply = &lt;&amp;reg_vdd_cpu_gpu&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_out {</div><div class='add'>+	hdmi_out_con: endpoint {</div><div class='add'>+		remote-endpoint = &lt;&amp;hdmi_con_in&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc0_pins&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_vcc3v3&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;pio 5 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc1 {</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_vcc3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_vcc1v8&gt;;</div><div class='add'>+	mmc-pwrseq = &lt;&amp;wifi_pwrseq&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc2 {</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_vcc3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_vcc1v8&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	cap-mmc-hw-reset;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ohci0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ohci3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	vcc-pc-supply = &lt;&amp;reg_vcc1v8&gt;;</div><div class='add'>+	vcc-pd-supply = &lt;&amp;reg_vcc3v3&gt;;</div><div class='add'>+	vcc-pg-supply = &lt;&amp;reg_vcc1v8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;r_ir {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spdif {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;spdif_tx_pin&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart0_ph_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb2otg {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb2phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi<br/>index b9ab7d8fa8af..73e8604315c5 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi</a></div><div class='hunk'>@@ -4,6 +4,7 @@</div><div class='ctx'> #include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/clock/sun50i-h6-ccu.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/clock/sun50i-h6-r-ccu.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/sun6i-rtc.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/clock/sun8i-de2.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/clock/sun8i-tcon-top.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/reset/sun50i-h6-ccu.h&gt;</div><div class='hunk'>@@ -25,6 +26,15 @@</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			reg = &lt;0&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_CPUX&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu1: cpu@1 {</div><div class='hunk'>@@ -32,6 +42,15 @@</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			reg = &lt;1&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_CPUX&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu2: cpu@2 {</div><div class='hunk'>@@ -39,6 +58,15 @@</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			reg = &lt;2&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_CPUX&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu3: cpu@3 {</div><div class='hunk'>@@ -46,6 +74,24 @@</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			reg = &lt;3&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_CPUX&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_cache: l2-cache {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x80000&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;512&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -55,7 +101,7 @@</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	osc24M: osc24M_clk {</div><div class='add'>+	osc24M: osc24M-clk {</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='ctx'> 		compatible = "fixed-clock";</div><div class='ctx'> 		clock-frequency = &lt;24000000&gt;;</div><div class='hunk'>@@ -78,6 +124,7 @@</div><div class='ctx'> </div><div class='ctx'> 	timer {</div><div class='ctx'> 		compatible = "arm,armv8-timer";</div><div class='add'>+		arm,no-tick-in-suspend;</div><div class='ctx'> 		interrupts = &lt;GIC_PPI 13</div><div class='ctx'> 			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)&gt;,</div><div class='ctx'> 			     &lt;GIC_PPI 14</div><div class='hunk'>@@ -106,10 +153,10 @@</div><div class='ctx'> 			display_clocks: clock@0 {</div><div class='ctx'> 				compatible = "allwinner,sun50i-h6-de3-clk";</div><div class='ctx'> 				reg = &lt;0x0 0x10000&gt;;</div><div class='del'>-				clocks = &lt;&amp;ccu CLK_DE&gt;,</div><div class='del'>-					 &lt;&amp;ccu CLK_BUS_DE&gt;;</div><div class='del'>-				clock-names = "mod",</div><div class='del'>-					      "bus";</div><div class='add'>+				clocks = &lt;&amp;ccu CLK_BUS_DE&gt;,</div><div class='add'>+					 &lt;&amp;ccu CLK_DE&gt;;</div><div class='add'>+				clock-names = "bus",</div><div class='add'>+					      "mod";</div><div class='ctx'> 				resets = &lt;&amp;ccu RST_BUS_DE&gt;;</div><div class='ctx'> 				#clock-cells = &lt;1&gt;;</div><div class='ctx'> 				#reset-cells = &lt;1&gt;;</div><div class='hunk'>@@ -123,6 +170,7 @@</div><div class='ctx'> 				clock-names = "bus",</div><div class='ctx'> 					      "mod";</div><div class='ctx'> 				resets = &lt;&amp;display_clocks RST_MIXER0&gt;;</div><div class='add'>+				iommus = &lt;&amp;iommu 0&gt;;</div><div class='ctx'> </div><div class='ctx'> 				ports {</div><div class='ctx'> 					#address-cells = &lt;1&gt;;</div><div class='hunk'>@@ -139,6 +187,16 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		video-codec-g2@1c00000 {</div><div class='add'>+			compatible = "allwinner,sun50i-h6-vpu-g2";</div><div class='add'>+			reg = &lt;0x01c00000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_VP9&gt;, &lt;&amp;ccu CLK_VP9&gt;;</div><div class='add'>+			clock-names = "bus", "mod";</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_VP9&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu 5&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		video-codec@1c0e000 {</div><div class='ctx'> 			compatible = "allwinner,sun50i-h6-video-engine";</div><div class='ctx'> 			reg = &lt;0x01c0e000 0x2000&gt;;</div><div class='hunk'>@@ -148,6 +206,7 @@</div><div class='ctx'> 			resets = &lt;&amp;ccu RST_BUS_VE&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			allwinner,sram = &lt;&amp;ve_sram 1&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu 3&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		gpu: gpu@1800000 {</div><div class='hunk'>@@ -161,6 +220,7 @@</div><div class='ctx'> 			clocks = &lt;&amp;ccu CLK_GPU&gt;, &lt;&amp;ccu CLK_BUS_GPU&gt;;</div><div class='ctx'> 			clock-names = "core", "bus";</div><div class='ctx'> 			resets = &lt;&amp;ccu RST_BUS_GPU&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -213,7 +273,7 @@</div><div class='ctx'> 		ccu: clock@3001000 {</div><div class='ctx'> 			compatible = "allwinner,sun50i-h6-ccu";</div><div class='ctx'> 			reg = &lt;0x03001000 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;osc24M&gt;, &lt;&amp;rtc 0&gt;, &lt;&amp;rtc 2&gt;;</div><div class='add'>+			clocks = &lt;&amp;osc24M&gt;, &lt;&amp;rtc CLK_OSC32K&gt;, &lt;&amp;rtc CLK_IOSC&gt;;</div><div class='ctx'> 			clock-names = "hosc", "losc", "iosc";</div><div class='ctx'> 			#clock-cells = &lt;1&gt;;</div><div class='ctx'> 			#reset-cells = &lt;1&gt;;</div><div class='hunk'>@@ -231,6 +291,16 @@</div><div class='ctx'> 			#dma-cells = &lt;1&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		msgbox: mailbox@3003000 {</div><div class='add'>+			compatible = "allwinner,sun50i-h6-msgbox",</div><div class='add'>+				     "allwinner,sun6i-a31-msgbox";</div><div class='add'>+			reg = &lt;0x03003000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_MSGBOX&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_MSGBOX&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#mbox-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		sid: efuse@3006000 {</div><div class='ctx'> 			compatible = "allwinner,sun50i-h6-sid";</div><div class='ctx'> 			reg = &lt;0x03006000 0x400&gt;;</div><div class='hunk'>@@ -240,6 +310,19 @@</div><div class='ctx'> 			ths_calibration: thermal-sensor-calibration@14 {</div><div class='ctx'> 				reg = &lt;0x14 0x8&gt;;</div><div class='ctx'> 			};</div><div class='add'>+</div><div class='add'>+			cpu_speed_grade: cpu-speed-grade@1c {</div><div class='add'>+				reg = &lt;0x1c 0x4&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		timer@3009000 {</div><div class='add'>+			compatible = "allwinner,sun50i-h6-timer",</div><div class='add'>+				     "allwinner,sun8i-a23-timer";</div><div class='add'>+			reg = &lt;0x03009000 0xa0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;osc24M&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		watchdog: watchdog@30090a0 {</div><div class='hunk'>@@ -265,11 +348,12 @@</div><div class='ctx'> 		pio: pinctrl@300b000 {</div><div class='ctx'> 			compatible = "allwinner,sun50i-h6-pinctrl";</div><div class='ctx'> 			reg = &lt;0x0300b000 0x400&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;r_intc&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 				     &lt;GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 				     &lt;GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 				     &lt;GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;ccu CLK_APB1&gt;, &lt;&amp;osc24M&gt;, &lt;&amp;rtc 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_APB1&gt;, &lt;&amp;osc24M&gt;, &lt;&amp;rtc CLK_OSC32K&gt;;</div><div class='ctx'> 			clock-names = "apb", "hosc", "losc";</div><div class='ctx'> 			gpio-controller;</div><div class='ctx'> 			#gpio-cells = &lt;3&gt;;</div><div class='hunk'>@@ -355,6 +439,7 @@</div><div class='ctx'> 				function = "spi1";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='add'>+			/omit-if-no-ref/</div><div class='ctx'> 			spdif_tx_pin: spdif-tx-pin {</div><div class='ctx'> 				pins = "PH7";</div><div class='ctx'> 				function = "spdif";</div><div class='hunk'>@@ -387,6 +472,15 @@</div><div class='ctx'> 			#interrupt-cells = &lt;3&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		iommu: iommu@30f0000 {</div><div class='add'>+			compatible = "allwinner,sun50i-h6-iommu";</div><div class='add'>+			reg = &lt;0x030f0000 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_IOMMU&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_IOMMU&gt;;</div><div class='add'>+			#iommu-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		mmc0: mmc@4020000 {</div><div class='ctx'> 			compatible = "allwinner,sun50i-h6-mmc",</div><div class='ctx'> 				     "allwinner,sun50i-a64-mmc";</div><div class='hunk'>@@ -398,6 +492,7 @@</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			pinctrl-names = "default";</div><div class='ctx'> 			pinctrl-0 = &lt;&amp;mmc0_pins&gt;;</div><div class='add'>+			max-frequency = &lt;150000000&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='hunk'>@@ -414,6 +509,7 @@</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			pinctrl-names = "default";</div><div class='ctx'> 			pinctrl-0 = &lt;&amp;mmc1_pins&gt;;</div><div class='add'>+			max-frequency = &lt;150000000&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='hunk'>@@ -430,6 +526,7 @@</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			pinctrl-names = "default";</div><div class='ctx'> 			pinctrl-0 = &lt;&amp;mmc2_pins&gt;;</div><div class='add'>+			max-frequency = &lt;150000000&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='hunk'>@@ -571,6 +668,19 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		i2s1: i2s@5091000 {</div><div class='add'>+			#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+			compatible = "allwinner,sun50i-h6-i2s";</div><div class='add'>+			reg = &lt;0x05091000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_I2S1&gt;, &lt;&amp;ccu CLK_I2S1&gt;;</div><div class='add'>+			clock-names = "apb", "mod";</div><div class='add'>+			dmas = &lt;&amp;dma 4&gt;, &lt;&amp;dma 4&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_I2S1&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		spdif: spdif@5093000 {</div><div class='ctx'> 			#sound-dai-cells = &lt;0&gt;;</div><div class='ctx'> 			compatible = "allwinner,sun50i-h6-spdif";</div><div class='hunk'>@@ -579,10 +689,8 @@</div><div class='ctx'> 			clocks = &lt;&amp;ccu CLK_BUS_SPDIF&gt;, &lt;&amp;ccu CLK_SPDIF&gt;;</div><div class='ctx'> 			clock-names = "apb", "spdif";</div><div class='ctx'> 			resets = &lt;&amp;ccu RST_BUS_SPDIF&gt;;</div><div class='del'>-			dmas = &lt;&amp;dma 2&gt;;</div><div class='del'>-			dma-names = "tx";</div><div class='del'>-			pinctrl-names = "default";</div><div class='del'>-			pinctrl-0 = &lt;&amp;spdif_tx_pin&gt;;</div><div class='add'>+			dmas = &lt;&amp;dma 2&gt;, &lt;&amp;dma 2&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -629,6 +737,8 @@</div><div class='ctx'> 				 &lt;&amp;ccu CLK_USB_OHCI0&gt;;</div><div class='ctx'> 			resets = &lt;&amp;ccu RST_BUS_OHCI0&gt;,</div><div class='ctx'> 				 &lt;&amp;ccu RST_BUS_EHCI0&gt;;</div><div class='add'>+			phys = &lt;&amp;usb2phy 0&gt;;</div><div class='add'>+			phy-names = "usb";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -639,16 +749,18 @@</div><div class='ctx'> 			clocks = &lt;&amp;ccu CLK_BUS_OHCI0&gt;,</div><div class='ctx'> 				 &lt;&amp;ccu CLK_USB_OHCI0&gt;;</div><div class='ctx'> 			resets = &lt;&amp;ccu RST_BUS_OHCI0&gt;;</div><div class='add'>+			phys = &lt;&amp;usb2phy 0&gt;;</div><div class='add'>+			phy-names = "usb";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		dwc3: dwc3@5200000 {</div><div class='add'>+		dwc3: usb@5200000 {</div><div class='ctx'> 			compatible = "snps,dwc3";</div><div class='ctx'> 			reg = &lt;0x05200000 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;ccu CLK_BUS_XHCI&gt;,</div><div class='ctx'> 				 &lt;&amp;ccu CLK_BUS_XHCI&gt;,</div><div class='del'>-				 &lt;&amp;rtc 0&gt;;</div><div class='add'>+				 &lt;&amp;rtc CLK_OSC32K&gt;;</div><div class='ctx'> 			clock-names = "ref", "bus_early", "suspend";</div><div class='ctx'> 			resets = &lt;&amp;ccu RST_BUS_XHCI&gt;;</div><div class='ctx'> 			/*</div><div class='hunk'>@@ -844,6 +956,7 @@</div><div class='ctx'> 		rtc: rtc@7000000 {</div><div class='ctx'> 			compatible = "allwinner,sun50i-h6-rtc";</div><div class='ctx'> 			reg = &lt;0x07000000 0x400&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;r_intc&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 				     &lt;GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clock-output-names = "osc32k", "osc32k-out", "iosc";</div><div class='hunk'>@@ -853,7 +966,7 @@</div><div class='ctx'> 		r_ccu: clock@7010000 {</div><div class='ctx'> 			compatible = "allwinner,sun50i-h6-r-ccu";</div><div class='ctx'> 			reg = &lt;0x07010000 0x400&gt;;</div><div class='del'>-			clocks = &lt;&amp;osc24M&gt;, &lt;&amp;rtc 0&gt;, &lt;&amp;rtc 2&gt;,</div><div class='add'>+			clocks = &lt;&amp;osc24M&gt;, &lt;&amp;rtc CLK_OSC32K&gt;, &lt;&amp;rtc CLK_IOSC&gt;,</div><div class='ctx'> 				 &lt;&amp;ccu CLK_PLL_PERIPH0&gt;;</div><div class='ctx'> 			clock-names = "hosc", "losc", "iosc", "pll-periph";</div><div class='ctx'> 			#clock-cells = &lt;1&gt;;</div><div class='hunk'>@@ -869,10 +982,9 @@</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		r_intc: interrupt-controller@7021000 {</div><div class='del'>-			compatible = "allwinner,sun50i-h6-r-intc",</div><div class='del'>-				     "allwinner,sun6i-a31-r-intc";</div><div class='add'>+			compatible = "allwinner,sun50i-h6-r-intc";</div><div class='ctx'> 			interrupt-controller;</div><div class='del'>-			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='ctx'> 			reg = &lt;0x07021000 0x400&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		};</div><div class='hunk'>@@ -880,9 +992,11 @@</div><div class='ctx'> 		r_pio: pinctrl@7022000 {</div><div class='ctx'> 			compatible = "allwinner,sun50i-h6-r-pinctrl";</div><div class='ctx'> 			reg = &lt;0x07022000 0x400&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;r_intc&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 				     &lt;GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;r_ccu CLK_R_APB1&gt;, &lt;&amp;osc24M&gt;, &lt;&amp;rtc 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;r_ccu CLK_R_APB1&gt;, &lt;&amp;osc24M&gt;,</div><div class='add'>+				 &lt;&amp;rtc CLK_OSC32K&gt;;</div><div class='ctx'> 			clock-names = "apb", "hosc", "losc";</div><div class='ctx'> 			gpio-controller;</div><div class='ctx'> 			#gpio-cells = &lt;3&gt;;</div><div class='hunk'>@@ -898,6 +1012,11 @@</div><div class='ctx'> 				pins = "PL9";</div><div class='ctx'> 				function = "s_cir_rx";</div><div class='ctx'> 			};</div><div class='add'>+</div><div class='add'>+			r_rsb_pins: r-rsb-pins {</div><div class='add'>+				pins = "PL0", "PL1";</div><div class='add'>+				function = "s_rsb";</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		r_ir: ir@7040000 {</div><div class='hunk'>@@ -928,6 +1047,20 @@</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		r_rsb: rsb@7083000 {</div><div class='add'>+			compatible = "allwinner,sun8i-a23-rsb";</div><div class='add'>+			reg = &lt;0x07083000 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;r_ccu CLK_R_APB2_RSB&gt;;</div><div class='add'>+			clock-frequency = &lt;3000000&gt;;</div><div class='add'>+			resets = &lt;&amp;r_ccu RST_R_APB2_RSB&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;r_rsb_pins&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		ths: thermal-sensor@5070400 {</div><div class='ctx'> 			compatible = "allwinner,sun50i-h6-ths";</div><div class='ctx'> 			reg = &lt;0x05070400 0x100&gt;;</div><div class='hunk'>@@ -946,12 +1079,82 @@</div><div class='ctx'> 			polling-delay-passive = &lt;0&gt;;</div><div class='ctx'> 			polling-delay = &lt;0&gt;;</div><div class='ctx'> 			thermal-sensors = &lt;&amp;ths 0&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu_alert: cpu-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu_alert&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		gpu-thermal {</div><div class='del'>-			polling-delay-passive = &lt;0&gt;;</div><div class='del'>-			polling-delay = &lt;0&gt;;</div><div class='add'>+			polling-delay-passive = &lt;1000&gt;;</div><div class='add'>+			polling-delay = &lt;2000&gt;;</div><div class='ctx'> 			thermal-sensors = &lt;&amp;ths 1&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				gpu_alert0: gpu-alert-0 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpu_alert1: gpu-alert-1 {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpu_alert2: gpu-alert-2 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpu-crit {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				// Forbid the GPU to go over 756MHz</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;gpu_alert0&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;gpu 1 THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				// Forbid the GPU to go over 624MHz</div><div class='add'>+				map1 {</div><div class='add'>+					trip = &lt;&amp;gpu_alert1&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;gpu 2 THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				// Forbid the GPU to go over 576MHz</div><div class='add'>+				map2 {</div><div class='add'>+					trip = &lt;&amp;gpu_alert2&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;gpu 3 THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-manta.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-manta.dts<br/>new file mode 100644<br/>index 000000000000..4bfb52609c94<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-manta.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-manta.dts</a></div><div class='hunk'>@@ -0,0 +1,35 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2023 Martin Botka &lt;martin.botka@somainline.org&gt;.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "sun50i-h616-bigtreetech-cb1.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "BigTreeTech CB1";</div><div class='add'>+	compatible = "bigtreetech,cb1-manta", "bigtreetech,cb1", "allwinner,sun50i-h616";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ehci1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ohci1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart0_ph_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi<br/>new file mode 100644<br/>index 000000000000..bebfeb2a337a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi</a></div><div class='hunk'>@@ -0,0 +1,148 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2023 Martin Botka &lt;martin.botka@somainline.org&gt;.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "sun50i-h616.dtsi"</div><div class='add'>+#include "sun50i-h616-cpu-opp.dtsi"</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;rtl8189ftv;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			gpios = &lt;&amp;pio 7 5 GPIO_ACTIVE_HIGH&gt;; /* PH5 */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc5v: regulator-vcc5v {</div><div class='add'>+		/* board wide 5V supply from carrier boards */</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vcc-5v";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc33_wifi: vcc33-wifi {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vcc33-wifi";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		vin-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc_wifi_io: vcc-wifi-io {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vcc-wifi-io";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		vin-supply = &lt;&amp;reg_vcc33_wifi&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wifi_pwrseq: wifi-pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-simple";</div><div class='add'>+		clocks = &lt;&amp;rtc 1&gt;;</div><div class='add'>+		clock-names = "ext_clock";</div><div class='add'>+		reset-gpios = &lt;&amp;pio 6 18 GPIO_ACTIVE_LOW&gt;; /* PG18 */</div><div class='add'>+		post-power-on-delay-ms = &lt;200&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_dcdc2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	mali-supply = &lt;&amp;reg_dcdc1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc0 {</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_dldo1&gt;;</div><div class='add'>+	/* Card detection pin is not connected */</div><div class='add'>+	broken-cd;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc1 {</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_vcc33_wifi&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_vcc_wifi_io&gt;;</div><div class='add'>+	mmc-pwrseq = &lt;&amp;wifi_pwrseq&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	mmc-ddr-1_8v;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	rtl8189ftv: wifi@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;r_i2c {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	axp313a: pmic@36 {</div><div class='add'>+		compatible = "x-powers,axp313a";</div><div class='add'>+		reg = &lt;0x36&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			reg_dcdc1: dcdc1 {</div><div class='add'>+				regulator-name = "vdd-gpu-sys";</div><div class='add'>+				regulator-min-microvolt = &lt;810000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;990000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_dcdc2: dcdc2 {</div><div class='add'>+				regulator-name = "vdd-cpu";</div><div class='add'>+				regulator-min-microvolt = &lt;810000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;200&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_dcdc3: dcdc3 {</div><div class='add'>+				regulator-name = "vcc-dram";</div><div class='add'>+				regulator-min-microvolt = &lt;1350000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1500000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_aldo1: aldo1 {</div><div class='add'>+				regulator-name = "vcc-1v8-pll";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_dldo1: dldo1 {</div><div class='add'>+				regulator-name = "vcc-3v3-io";</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbphy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-pi.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-pi.dts<br/>new file mode 100644<br/>index 000000000000..ff84a3794470<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-pi.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-pi.dts</a></div><div class='hunk'>@@ -0,0 +1,63 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2023 Martin Botka &lt;martin@biqu3d.com&gt;.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "sun50i-h616-bigtreetech-cb1.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "BigTreeTech Pi";</div><div class='add'>+	compatible = "bigtreetech,pi", "allwinner,sun50i-h616";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ehci0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ehci1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ehci2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ehci3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ir {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ohci0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ohci1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ohci2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ohci3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart0_ph_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi<br/>new file mode 100644<br/>index 000000000000..dd10aaf472b6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi</a></div><div class='hunk'>@@ -0,0 +1,126 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+// Copyright (C) 2023 Martin Botka &lt;martin@somainline.org&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	cpu_opp_table: opp-table-cpu {</div><div class='add'>+		compatible = "allwinner,sun50i-h616-operating-points";</div><div class='add'>+		nvmem-cells = &lt;&amp;cpu_speed_grade&gt;;</div><div class='add'>+		opp-shared;</div><div class='add'>+</div><div class='add'>+		opp-480000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;480000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;900000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;244144&gt;; /* 8 32k periods */</div><div class='add'>+			opp-supported-hw = &lt;0x3f&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-600000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;600000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;900000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;244144&gt;; /* 8 32k periods */</div><div class='add'>+			opp-supported-hw = &lt;0x12&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-720000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;720000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;900000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;244144&gt;; /* 8 32k periods */</div><div class='add'>+			opp-supported-hw = &lt;0x2d&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-792000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;792000000&gt;;</div><div class='add'>+			opp-microvolt-speed1 = &lt;900000&gt;;</div><div class='add'>+			opp-microvolt-speed4 = &lt;940000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;244144&gt;; /* 8 32k periods */</div><div class='add'>+			opp-supported-hw = &lt;0x12&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-936000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;936000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;900000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;244144&gt;; /* 8 32k periods */</div><div class='add'>+			opp-supported-hw = &lt;0x0d&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1008000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1008000000&gt;;</div><div class='add'>+			opp-microvolt-speed0 = &lt;950000&gt;;</div><div class='add'>+			opp-microvolt-speed1 = &lt;940000&gt;;</div><div class='add'>+			opp-microvolt-speed2 = &lt;950000&gt;;</div><div class='add'>+			opp-microvolt-speed3 = &lt;950000&gt;;</div><div class='add'>+			opp-microvolt-speed4 = &lt;1020000&gt;;</div><div class='add'>+			opp-microvolt-speed5 = &lt;900000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;244144&gt;; /* 8 32k periods */</div><div class='add'>+			opp-supported-hw = &lt;0x3f&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1032000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1032000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;900000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;244144&gt;; /* 8 32k periods */</div><div class='add'>+			opp-supported-hw = &lt;0x20&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1104000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1104000000&gt;;</div><div class='add'>+			opp-microvolt-speed0 = &lt;1000000&gt;;</div><div class='add'>+			opp-microvolt-speed2 = &lt;1000000&gt;;</div><div class='add'>+			opp-microvolt-speed3 = &lt;1000000&gt;;</div><div class='add'>+			opp-microvolt-speed5 = &lt;950000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;244144&gt;; /* 8 32k periods */</div><div class='add'>+			opp-supported-hw = &lt;0x2d&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1200000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1200000000&gt;;</div><div class='add'>+			opp-microvolt-speed0 = &lt;1050000&gt;;</div><div class='add'>+			opp-microvolt-speed1 = &lt;1020000&gt;;</div><div class='add'>+			opp-microvolt-speed2 = &lt;1050000&gt;;</div><div class='add'>+			opp-microvolt-speed3 = &lt;1050000&gt;;</div><div class='add'>+			opp-microvolt-speed4 = &lt;1100000&gt;;</div><div class='add'>+			opp-microvolt-speed5 = &lt;1020000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;244144&gt;; /* 8 32k periods */</div><div class='add'>+			opp-supported-hw = &lt;0x3f&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1320000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1320000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1100000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;244144&gt;; /* 8 32k periods */</div><div class='add'>+			opp-supported-hw = &lt;0x1d&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1416000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1416000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1100000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;244144&gt;; /* 8 32k periods */</div><div class='add'>+			opp-supported-hw = &lt;0x2d&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1512000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1512000000&gt;;</div><div class='add'>+			opp-microvolt-speed1 = &lt;1100000&gt;;</div><div class='add'>+			opp-microvolt-speed3 = &lt;1100000&gt;;</div><div class='add'>+			opp-microvolt-speed5 = &lt;1160000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;244144&gt;; /* 8 32k periods */</div><div class='add'>+			opp-supported-hw = &lt;0x2a&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu1 {</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu2 {</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu3 {</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi<br/>new file mode 100644<br/>index 000000000000..a8644fb52b04<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi</a></div><div class='hunk'>@@ -0,0 +1,141 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2020 Arm Ltd.</div><div class='add'>+ *</div><div class='add'>+ * DT nodes common between Orange Pi Zero 2 and Orange Pi Zero 3.</div><div class='add'>+ * Excludes PMIC nodes and properties, since they are different between the two.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "sun50i-h616.dtsi"</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;emac0;</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			function = LED_FUNCTION_POWER;</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			gpios = &lt;&amp;pio 2 12 GPIO_ACTIVE_HIGH&gt;; /* PC12 */</div><div class='add'>+			default-state = "on";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			gpios = &lt;&amp;pio 2 13 GPIO_ACTIVE_HIGH&gt;; /* PC13 */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc5v: vcc5v {</div><div class='add'>+		/* board wide 5V supply directly from the USB-C socket */</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vcc-5v";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb1_vbus: regulator-usb1-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "usb1-vbus";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;pio 2 16 GPIO_ACTIVE_HIGH&gt;; /* PC16 */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;codec {</div><div class='add'>+	allwinner,audio-routing = "Line Out", "LINEOUT";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ehci1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB 2 &amp; 3 are on headers only. */</div><div class='add'>+</div><div class='add'>+&amp;emac0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;ext_rgmii_pins&gt;;</div><div class='add'>+	phy-handle = &lt;&amp;ext_rgmii_phy&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdio0 {</div><div class='add'>+	ext_rgmii_phy: ethernet-phy@1 {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc0 {</div><div class='add'>+	cd-gpios = &lt;&amp;pio 5 6 GPIO_ACTIVE_LOW&gt;;	/* PF6 */</div><div class='add'>+	disable-wp;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ohci1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi0  {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;spi0_pins&gt;, &lt;&amp;spi0_cs0_pin&gt;;</div><div class='add'>+</div><div class='add'>+	flash@0 {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;40000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart0_ph_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg {</div><div class='add'>+	/*</div><div class='add'>+	 * PHY0 pins are connected to a USB-C socket, but a role switch</div><div class='add'>+	 * is not implemented: both CC pins are pulled to GND.</div><div class='add'>+	 * The VBUS pins power the device, so a fixed peripheral mode</div><div class='add'>+	 * is the best choice.</div><div class='add'>+	 * The board can be powered via GPIOs, in this case port0 *can*</div><div class='add'>+	 * act as a host (with a cable/adapter ignoring CC), as VBUS is</div><div class='add'>+	 * then provided by the GPIOs. Any user of this setup would</div><div class='add'>+	 * need to adjust the DT accordingly: dr_mode set to "host",</div><div class='add'>+	 * enabling OHCI0 and EHCI0.</div><div class='add'>+	 */</div><div class='add'>+	dr_mode = "peripheral";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbphy {</div><div class='add'>+	usb1_vbus-supply = &lt;&amp;reg_usb1_vbus&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts<br/>new file mode 100644<br/>index 000000000000..f2e3300e078a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts</a></div><div class='hunk'>@@ -0,0 +1,149 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2020 Arm Ltd.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "sun50i-h616-orangepi-zero.dtsi"</div><div class='add'>+#include "sun50i-h616-cpu-opp.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "OrangePi Zero2";</div><div class='add'>+	compatible = "xunlong,orangepi-zero2", "allwinner,sun50i-h616";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_dcdca&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;emac0 {</div><div class='add'>+	allwinner,rx-delay-ps = &lt;3100&gt;;</div><div class='add'>+	allwinner,tx-delay-ps = &lt;700&gt;;</div><div class='add'>+	phy-mode = "rgmii";</div><div class='add'>+	phy-supply = &lt;&amp;reg_dcdce&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	mali-supply = &lt;&amp;reg_dcdcc&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc0 {</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_dcdce&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;r_rsb {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	axp305: pmic@745 {</div><div class='add'>+		compatible = "x-powers,axp305", "x-powers,axp805",</div><div class='add'>+			     "x-powers,axp806";</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		reg = &lt;0x745&gt;;</div><div class='add'>+</div><div class='add'>+		x-powers,self-working-mode;</div><div class='add'>+		vina-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vinb-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vinc-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vind-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vine-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		aldoin-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		bldoin-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		cldoin-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			reg_aldo1: aldo1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "vcc-sys";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_aldo2: aldo2 {	/* 3.3V on headers */</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "vcc3v3-ext";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_aldo3: aldo3 {	/* 3.3V on headers */</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "vcc3v3-ext2";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_bldo1: bldo1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "vcc1v8";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			bldo2 {</div><div class='add'>+				/* unused */</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			bldo3 {</div><div class='add'>+				/* unused */</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			bldo4 {</div><div class='add'>+				/* unused */</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cldo1 {</div><div class='add'>+				/* reserved */</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cldo2 {</div><div class='add'>+				/* unused */</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cldo3 {</div><div class='add'>+				/* unused */</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_dcdca: dcdca {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;810000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-name = "vdd-cpu";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_dcdcc: dcdcc {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;810000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;990000&gt;;</div><div class='add'>+				regulator-name = "vdd-gpu-sys";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_dcdcd: dcdcd {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;1500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1500000&gt;;</div><div class='add'>+				regulator-name = "vdd-dram";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_dcdce: dcdce {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "vcc-eth-mmc";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sw {</div><div class='add'>+				/* unused */</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	vcc-pc-supply = &lt;&amp;reg_aldo1&gt;;</div><div class='add'>+	vcc-pf-supply = &lt;&amp;reg_aldo1&gt;;</div><div class='add'>+	vcc-pg-supply = &lt;&amp;reg_bldo1&gt;;</div><div class='add'>+	vcc-ph-supply = &lt;&amp;reg_aldo1&gt;;</div><div class='add'>+	vcc-pi-supply = &lt;&amp;reg_aldo1&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts<br/>new file mode 100644<br/>index 000000000000..085f3e4e8eaa<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts</a></div><div class='hunk'>@@ -0,0 +1,218 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2021 Arm Ltd.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "sun50i-h616.dtsi"</div><div class='add'>+#include "sun50i-h616-cpu-opp.dtsi"</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "X96 Mate";</div><div class='add'>+	compatible = "hechuang,x96-mate", "allwinner,sun50i-h616";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc5v: vcc5v {</div><div class='add'>+		/* board wide 5V supply directly from the DC input */</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vcc-5v";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;codec {</div><div class='add'>+	allwinner,audio-routing = "Line Out", "LINEOUT";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_dcdca&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ehci0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ehci2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	mali-supply = &lt;&amp;reg_dcdcc&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ir {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc0 {</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_dcdce&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;pio 5 6 GPIO_ACTIVE_LOW&gt;;	/* PF6 */</div><div class='add'>+	disable-wp;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc2 {</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_dcdce&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_bldo1&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	cap-mmc-hw-reset;</div><div class='add'>+	mmc-ddr-1_8v;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ohci0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ohci2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;r_rsb {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	axp305: pmic@745 {</div><div class='add'>+		compatible = "x-powers,axp305", "x-powers,axp805",</div><div class='add'>+			     "x-powers,axp806";</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		reg = &lt;0x745&gt;;</div><div class='add'>+</div><div class='add'>+		x-powers,self-working-mode;</div><div class='add'>+		vina-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vinb-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vinc-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vind-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vine-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		aldoin-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		bldoin-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		cldoin-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			reg_aldo1: aldo1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "vcc-sys";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* Enabled by the Android BSP */</div><div class='add'>+			reg_aldo2: aldo2 {</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "vcc3v3-ext";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* Enabled by the Android BSP */</div><div class='add'>+			reg_aldo3: aldo3 {</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "vcc3v3-ext2";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_bldo1: bldo1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "vcc1v8";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* Enabled by the Android BSP */</div><div class='add'>+			reg_bldo2: bldo2 {</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "vcc1v8-2";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			bldo3 {</div><div class='add'>+				/* unused */</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			bldo4 {</div><div class='add'>+				/* unused */</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cldo1 {</div><div class='add'>+				regulator-min-microvolt = &lt;2500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2500000&gt;;</div><div class='add'>+				regulator-name = "vcc2v5";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cldo2 {</div><div class='add'>+				/* unused */</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cldo3 {</div><div class='add'>+				/* unused */</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_dcdca: dcdca {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;810000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-name = "vdd-cpu";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_dcdcc: dcdcc {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;810000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;990000&gt;;</div><div class='add'>+				regulator-name = "vdd-gpu-sys";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_dcdcd: dcdcd {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;1360000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1360000&gt;;</div><div class='add'>+				regulator-name = "vdd-dram";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_dcdce: dcdce {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "vcc-eth-mmc";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sw {</div><div class='add'>+				/* unused */</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart0_ph_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg {</div><div class='add'>+	dr_mode = "host";	/* USB A type receptable */</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbphy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi<br/>new file mode 100644<br/>index 000000000000..8d1110c14bad<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi</a></div><div class='hunk'>@@ -0,0 +1,1096 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+// Copyright (C) 2020 Arm Ltd.</div><div class='add'>+// based on the H6 dtsi, which is:</div><div class='add'>+//   Copyright (C) 2017 Icenowy Zheng &lt;icenowy@aosc.io&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/sun50i-h616-ccu.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/sun50i-h6-r-ccu.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/sun6i-rtc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/reset/sun50i-h616-ccu.h&gt;</div><div class='add'>+#include &lt;dt-bindings/reset/sun50i-h6-r-ccu.h&gt;</div><div class='add'>+#include &lt;dt-bindings/thermal/thermal.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_CPUX&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@1 {</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_CPUX&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@2 {</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;2&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_CPUX&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@3 {</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;3&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_CPUX&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_cache: l2-cache {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x40000&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;256&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * 256 KiB reserved for Trusted Firmware-A (BL31).</div><div class='add'>+		 * This is added by BL31 itself, but some bootloaders fail</div><div class='add'>+		 * to propagate this into the DTB handed to kernels.</div><div class='add'>+		 */</div><div class='add'>+		secmon@40000000 {</div><div class='add'>+			reg = &lt;0x0 0x40000000 0x0 0x40000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	osc24M: osc24M-clk {</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+		clock-output-names = "osc24M";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu {</div><div class='add'>+		compatible = "arm,cortex-a53-pmu";</div><div class='add'>+		interrupts = &lt;GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-affinity = &lt;&amp;cpu0&gt;, &lt;&amp;cpu1&gt;, &lt;&amp;cpu2&gt;, &lt;&amp;cpu3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-0.2";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		arm,no-tick-in-suspend;</div><div class='add'>+		interrupts = &lt;GIC_PPI 13</div><div class='add'>+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14</div><div class='add'>+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11</div><div class='add'>+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10</div><div class='add'>+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges = &lt;0x0 0x0 0x0 0x40000000&gt;;</div><div class='add'>+</div><div class='add'>+		gpu: gpu@1800000 {</div><div class='add'>+			compatible = "allwinner,sun50i-h616-mali",</div><div class='add'>+				     "arm,mali-bifrost";</div><div class='add'>+			reg = &lt;0x1800000 0x40000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "job", "mmu", "gpu";</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_GPU0&gt;, &lt;&amp;ccu CLK_BUS_GPU&gt;;</div><div class='add'>+			clock-names = "core", "bus";</div><div class='add'>+			power-domains = &lt;&amp;prcm_ppu 2&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_GPU&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		crypto: crypto@1904000 {</div><div class='add'>+			compatible = "allwinner,sun50i-h616-crypto";</div><div class='add'>+			reg = &lt;0x01904000 0x800&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_CE&gt;, &lt;&amp;ccu CLK_CE&gt;,</div><div class='add'>+				 &lt;&amp;ccu CLK_MBUS_CE&gt;, &lt;&amp;rtc CLK_IOSC&gt;;</div><div class='add'>+			clock-names = "bus", "mod", "ram", "trng";</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_CE&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		syscon: syscon@3000000 {</div><div class='add'>+			compatible = "allwinner,sun50i-h616-system-control";</div><div class='add'>+			reg = &lt;0x03000000 0x1000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			sram_c: sram@28000 {</div><div class='add'>+				compatible = "mmio-sram";</div><div class='add'>+				reg = &lt;0x00028000 0x30000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;1&gt;;</div><div class='add'>+				ranges = &lt;0 0x00028000 0x30000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ccu: clock@3001000 {</div><div class='add'>+			compatible = "allwinner,sun50i-h616-ccu";</div><div class='add'>+			reg = &lt;0x03001000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;osc24M&gt;, &lt;&amp;rtc CLK_OSC32K&gt;, &lt;&amp;rtc CLK_IOSC&gt;;</div><div class='add'>+			clock-names = "hosc", "losc", "iosc";</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dma: dma-controller@3002000 {</div><div class='add'>+			compatible = "allwinner,sun50i-h616-dma",</div><div class='add'>+				     "allwinner,sun50i-a100-dma";</div><div class='add'>+			reg = &lt;0x03002000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_DMA&gt;, &lt;&amp;ccu CLK_MBUS_DMA&gt;;</div><div class='add'>+			clock-names = "bus", "mbus";</div><div class='add'>+			dma-channels = &lt;16&gt;;</div><div class='add'>+			dma-requests = &lt;49&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_DMA&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sid: efuse@3006000 {</div><div class='add'>+			compatible = "allwinner,sun50i-h616-sid", "allwinner,sun50i-a64-sid";</div><div class='add'>+			reg = &lt;0x03006000 0x1000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			ths_calibration: thermal-sensor-calibration@14 {</div><div class='add'>+				reg = &lt;0x14 0x8&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cpu_speed_grade: cpu-speed-grade@0 {</div><div class='add'>+				reg = &lt;0x0 2&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		watchdog: watchdog@30090a0 {</div><div class='add'>+			compatible = "allwinner,sun50i-h616-wdt",</div><div class='add'>+				     "allwinner,sun6i-a31-wdt";</div><div class='add'>+			reg = &lt;0x030090a0 0x20&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;osc24M&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pio: pinctrl@300b000 {</div><div class='add'>+			compatible = "allwinner,sun50i-h616-pinctrl";</div><div class='add'>+			reg = &lt;0x0300b000 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_APB1&gt;, &lt;&amp;osc24M&gt;, &lt;&amp;rtc CLK_OSC32K&gt;;</div><div class='add'>+			clock-names = "apb", "hosc", "losc";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;3&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+			ext_rgmii_pins: rgmii-pins {</div><div class='add'>+				pins = "PI0", "PI1", "PI2", "PI3", "PI4",</div><div class='add'>+				       "PI5", "PI7", "PI8", "PI9", "PI10",</div><div class='add'>+				       "PI11", "PI12", "PI13", "PI14", "PI15",</div><div class='add'>+				       "PI16";</div><div class='add'>+				function = "emac0";</div><div class='add'>+				drive-strength = &lt;40&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c0_pins: i2c0-pins {</div><div class='add'>+				pins = "PI5", "PI6";</div><div class='add'>+				function = "i2c0";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c3_ph_pins: i2c3-ph-pins {</div><div class='add'>+				pins = "PH4", "PH5";</div><div class='add'>+				function = "i2c3";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ir_rx_pin: ir-rx-pin {</div><div class='add'>+				pins = "PH10";</div><div class='add'>+				function = "ir_rx";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mmc0_pins: mmc0-pins {</div><div class='add'>+				pins = "PF0", "PF1", "PF2", "PF3",</div><div class='add'>+				       "PF4", "PF5";</div><div class='add'>+				function = "mmc0";</div><div class='add'>+				drive-strength = &lt;30&gt;;</div><div class='add'>+				bias-pull-up;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/omit-if-no-ref/</div><div class='add'>+			mmc1_pins: mmc1-pins {</div><div class='add'>+				pins = "PG0", "PG1", "PG2", "PG3",</div><div class='add'>+				       "PG4", "PG5";</div><div class='add'>+				function = "mmc1";</div><div class='add'>+				drive-strength = &lt;30&gt;;</div><div class='add'>+				bias-pull-up;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mmc2_pins: mmc2-pins {</div><div class='add'>+				pins = "PC0", "PC1", "PC5", "PC6",</div><div class='add'>+				       "PC8", "PC9", "PC10", "PC11",</div><div class='add'>+				       "PC13", "PC14", "PC15", "PC16";</div><div class='add'>+				function = "mmc2";</div><div class='add'>+				drive-strength = &lt;30&gt;;</div><div class='add'>+				bias-pull-up;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/omit-if-no-ref/</div><div class='add'>+			nand_pins: nand-pins {</div><div class='add'>+				pins = "PC0", "PC1", "PC2", "PC5", "PC8", "PC9",</div><div class='add'>+				       "PC10", "PC11", "PC12", "PC13", "PC14",</div><div class='add'>+				       "PC15", "PC16";</div><div class='add'>+				function = "nand0";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/omit-if-no-ref/</div><div class='add'>+			nand_cs0_pin: nand-cs0-pin {</div><div class='add'>+				pins = "PC4";</div><div class='add'>+				function = "nand0";</div><div class='add'>+				bias-pull-up;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/omit-if-no-ref/</div><div class='add'>+			nand_cs1_pin: nand-cs1-pin {</div><div class='add'>+				pins = "PC3";</div><div class='add'>+				function = "nand0";</div><div class='add'>+				bias-pull-up;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/omit-if-no-ref/</div><div class='add'>+			nand_rb0_pin: nand-rb0-pin {</div><div class='add'>+				pins = "PC6";</div><div class='add'>+				function = "nand0";</div><div class='add'>+				bias-pull-up;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/omit-if-no-ref/</div><div class='add'>+			nand_rb1_pin: nand-rb1-pin {</div><div class='add'>+				pins = "PC7";</div><div class='add'>+				function = "nand0";</div><div class='add'>+				bias-pull-up;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/omit-if-no-ref/</div><div class='add'>+			spi0_pins: spi0-pins {</div><div class='add'>+				pins = "PC0", "PC2", "PC4";</div><div class='add'>+				function = "spi0";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/omit-if-no-ref/</div><div class='add'>+			spi0_cs0_pin: spi0-cs0-pin {</div><div class='add'>+				pins = "PC3";</div><div class='add'>+				function = "spi0";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/omit-if-no-ref/</div><div class='add'>+			spi1_pins: spi1-pins {</div><div class='add'>+				pins = "PH6", "PH7", "PH8";</div><div class='add'>+				function = "spi1";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/omit-if-no-ref/</div><div class='add'>+			spi1_cs0_pin: spi1-cs0-pin {</div><div class='add'>+				pins = "PH5";</div><div class='add'>+				function = "spi1";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spdif_tx_pin: spdif-tx-pin {</div><div class='add'>+				pins = "PH4";</div><div class='add'>+				function = "spdif";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart0_ph_pins: uart0-ph-pins {</div><div class='add'>+				pins = "PH0", "PH1";</div><div class='add'>+				function = "uart0";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/omit-if-no-ref/</div><div class='add'>+			uart1_pins: uart1-pins {</div><div class='add'>+				pins = "PG6", "PG7";</div><div class='add'>+				function = "uart1";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/omit-if-no-ref/</div><div class='add'>+			uart1_rts_cts_pins: uart1-rts-cts-pins {</div><div class='add'>+				pins = "PG8", "PG9";</div><div class='add'>+				function = "uart1";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/omit-if-no-ref/</div><div class='add'>+			x32clk_fanout_pin: x32clk-fanout-pin {</div><div class='add'>+				pins = "PG10";</div><div class='add'>+				function = "clock";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@3021000 {</div><div class='add'>+			compatible = "arm,gic-400";</div><div class='add'>+			reg = &lt;0x03021000 0x1000&gt;,</div><div class='add'>+			      &lt;0x03022000 0x2000&gt;,</div><div class='add'>+			      &lt;0x03024000 0x2000&gt;,</div><div class='add'>+			      &lt;0x03026000 0x2000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		iommu: iommu@30f0000 {</div><div class='add'>+			compatible = "allwinner,sun50i-h616-iommu";</div><div class='add'>+			reg = &lt;0x030f0000 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_IOMMU&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_IOMMU&gt;;</div><div class='add'>+			#iommu-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nfc: nand-controller@4011000 {</div><div class='add'>+			compatible = "allwinner,sun50i-h616-nand-controller";</div><div class='add'>+			reg = &lt;0x04011000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_NAND&gt;, &lt;&amp;ccu CLK_NAND0&gt;,</div><div class='add'>+				 &lt;&amp;ccu CLK_NAND1&gt;, &lt;&amp;ccu CLK_MBUS_NAND&gt;;</div><div class='add'>+			clock-names = "ahb", "mod", "ecc", "mbus";</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_NAND&gt;;</div><div class='add'>+			reset-names = "ahb";</div><div class='add'>+			dmas = &lt;&amp;dma 10&gt;;</div><div class='add'>+			dma-names = "rxtx";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmc0: mmc@4020000 {</div><div class='add'>+			compatible = "allwinner,sun50i-h616-mmc",</div><div class='add'>+				     "allwinner,sun50i-a100-mmc";</div><div class='add'>+			reg = &lt;0x04020000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_MMC0&gt;, &lt;&amp;ccu CLK_MMC0&gt;;</div><div class='add'>+			clock-names = "ahb", "mmc";</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_MMC0&gt;;</div><div class='add'>+			reset-names = "ahb";</div><div class='add'>+			interrupts = &lt;GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;mmc0_pins&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+			max-frequency = &lt;150000000&gt;;</div><div class='add'>+			cap-sd-highspeed;</div><div class='add'>+			cap-mmc-highspeed;</div><div class='add'>+			mmc-ddr-3_3v;</div><div class='add'>+			cap-sdio-irq;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmc1: mmc@4021000 {</div><div class='add'>+			compatible = "allwinner,sun50i-h616-mmc",</div><div class='add'>+				     "allwinner,sun50i-a100-mmc";</div><div class='add'>+			reg = &lt;0x04021000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_MMC1&gt;, &lt;&amp;ccu CLK_MMC1&gt;;</div><div class='add'>+			clock-names = "ahb", "mmc";</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_MMC1&gt;;</div><div class='add'>+			reset-names = "ahb";</div><div class='add'>+			interrupts = &lt;GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;mmc1_pins&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+			max-frequency = &lt;150000000&gt;;</div><div class='add'>+			cap-sd-highspeed;</div><div class='add'>+			cap-mmc-highspeed;</div><div class='add'>+			mmc-ddr-3_3v;</div><div class='add'>+			cap-sdio-irq;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmc2: mmc@4022000 {</div><div class='add'>+			compatible = "allwinner,sun50i-h616-emmc",</div><div class='add'>+				     "allwinner,sun50i-a100-emmc";</div><div class='add'>+			reg = &lt;0x04022000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_MMC2&gt;, &lt;&amp;ccu CLK_MMC2&gt;;</div><div class='add'>+			clock-names = "ahb", "mmc";</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_MMC2&gt;;</div><div class='add'>+			reset-names = "ahb";</div><div class='add'>+			interrupts = &lt;GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;mmc2_pins&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+			max-frequency = &lt;150000000&gt;;</div><div class='add'>+			cap-sd-highspeed;</div><div class='add'>+			cap-mmc-highspeed;</div><div class='add'>+			mmc-ddr-3_3v;</div><div class='add'>+			cap-sdio-irq;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart0: serial@5000000 {</div><div class='add'>+			compatible = "snps,dw-apb-uart";</div><div class='add'>+			reg = &lt;0x05000000 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			reg-shift = &lt;2&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_UART0&gt;;</div><div class='add'>+			dmas = &lt;&amp;dma 14&gt;, &lt;&amp;dma 14&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_UART0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart1: serial@5000400 {</div><div class='add'>+			compatible = "snps,dw-apb-uart";</div><div class='add'>+			reg = &lt;0x05000400 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			reg-shift = &lt;2&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_UART1&gt;;</div><div class='add'>+			dmas = &lt;&amp;dma 15&gt;, &lt;&amp;dma 15&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_UART1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart2: serial@5000800 {</div><div class='add'>+			compatible = "snps,dw-apb-uart";</div><div class='add'>+			reg = &lt;0x05000800 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			reg-shift = &lt;2&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_UART2&gt;;</div><div class='add'>+			dmas = &lt;&amp;dma 16&gt;, &lt;&amp;dma 16&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_UART2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart3: serial@5000c00 {</div><div class='add'>+			compatible = "snps,dw-apb-uart";</div><div class='add'>+			reg = &lt;0x05000c00 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			reg-shift = &lt;2&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_UART3&gt;;</div><div class='add'>+			dmas = &lt;&amp;dma 17&gt;, &lt;&amp;dma 17&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_UART3&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart4: serial@5001000 {</div><div class='add'>+			compatible = "snps,dw-apb-uart";</div><div class='add'>+			reg = &lt;0x05001000 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			reg-shift = &lt;2&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_UART4&gt;;</div><div class='add'>+			dmas = &lt;&amp;dma 18&gt;, &lt;&amp;dma 18&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_UART4&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart5: serial@5001400 {</div><div class='add'>+			compatible = "snps,dw-apb-uart";</div><div class='add'>+			reg = &lt;0x05001400 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			reg-shift = &lt;2&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_UART5&gt;;</div><div class='add'>+			dmas = &lt;&amp;dma 19&gt;, &lt;&amp;dma 19&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_UART5&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c0: i2c@5002000 {</div><div class='add'>+			compatible = "allwinner,sun50i-h616-i2c",</div><div class='add'>+				     "allwinner,sun8i-v536-i2c",</div><div class='add'>+				     "allwinner,sun6i-a31-i2c";</div><div class='add'>+			reg = &lt;0x05002000 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_I2C0&gt;;</div><div class='add'>+			dmas = &lt;&amp;dma 43&gt;, &lt;&amp;dma 43&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_I2C0&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c0_pins&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c1: i2c@5002400 {</div><div class='add'>+			compatible = "allwinner,sun50i-h616-i2c",</div><div class='add'>+				     "allwinner,sun8i-v536-i2c",</div><div class='add'>+				     "allwinner,sun6i-a31-i2c";</div><div class='add'>+			reg = &lt;0x05002400 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_I2C1&gt;;</div><div class='add'>+			dmas = &lt;&amp;dma 44&gt;, &lt;&amp;dma 44&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_I2C1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c2: i2c@5002800 {</div><div class='add'>+			compatible = "allwinner,sun50i-h616-i2c",</div><div class='add'>+				     "allwinner,sun8i-v536-i2c",</div><div class='add'>+				     "allwinner,sun6i-a31-i2c";</div><div class='add'>+			reg = &lt;0x05002800 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_I2C2&gt;;</div><div class='add'>+			dmas = &lt;&amp;dma 45&gt;, &lt;&amp;dma 45&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_I2C2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c3: i2c@5002c00 {</div><div class='add'>+			compatible = "allwinner,sun50i-h616-i2c",</div><div class='add'>+				     "allwinner,sun8i-v536-i2c",</div><div class='add'>+				     "allwinner,sun6i-a31-i2c";</div><div class='add'>+			reg = &lt;0x05002c00 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_I2C3&gt;;</div><div class='add'>+			dmas = &lt;&amp;dma 46&gt;, &lt;&amp;dma 46&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_I2C3&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c4: i2c@5003000 {</div><div class='add'>+			compatible = "allwinner,sun50i-h616-i2c",</div><div class='add'>+				     "allwinner,sun8i-v536-i2c",</div><div class='add'>+				     "allwinner,sun6i-a31-i2c";</div><div class='add'>+			reg = &lt;0x05003000 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_I2C4&gt;;</div><div class='add'>+			dmas = &lt;&amp;dma 47&gt;, &lt;&amp;dma 47&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_I2C4&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi0: spi@5010000 {</div><div class='add'>+			compatible = "allwinner,sun50i-h616-spi",</div><div class='add'>+				     "allwinner,sun8i-h3-spi";</div><div class='add'>+			reg = &lt;0x05010000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_SPI0&gt;, &lt;&amp;ccu CLK_SPI0&gt;;</div><div class='add'>+			clock-names = "ahb", "mod";</div><div class='add'>+			dmas = &lt;&amp;dma 22&gt;, &lt;&amp;dma 22&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_SPI0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi1: spi@5011000 {</div><div class='add'>+			compatible = "allwinner,sun50i-h616-spi",</div><div class='add'>+				     "allwinner,sun8i-h3-spi";</div><div class='add'>+			reg = &lt;0x05011000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_SPI1&gt;, &lt;&amp;ccu CLK_SPI1&gt;;</div><div class='add'>+			clock-names = "ahb", "mod";</div><div class='add'>+			dmas = &lt;&amp;dma 23&gt;, &lt;&amp;dma 23&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_SPI1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		emac0: ethernet@5020000 {</div><div class='add'>+			compatible = "allwinner,sun50i-h616-emac0",</div><div class='add'>+				     "allwinner,sun50i-a64-emac";</div><div class='add'>+			reg = &lt;0x05020000 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "macirq";</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_EMAC0&gt;;</div><div class='add'>+			clock-names = "stmmaceth";</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_EMAC0&gt;;</div><div class='add'>+			reset-names = "stmmaceth";</div><div class='add'>+			syscon = &lt;&amp;syscon&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			mdio0: mdio {</div><div class='add'>+				compatible = "snps,dwmac-mdio";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpadc: adc@5070000 {</div><div class='add'>+			compatible = "allwinner,sun50i-h616-gpadc",</div><div class='add'>+				     "allwinner,sun20i-d1-gpadc";</div><div class='add'>+			reg = &lt;0x05070000 0x400&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_GPADC&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_GPADC&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+			#io-channel-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ths: thermal-sensor@5070400 {</div><div class='add'>+			compatible = "allwinner,sun50i-h616-ths";</div><div class='add'>+			reg = &lt;0x05070400 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_THS&gt;;</div><div class='add'>+			clock-names = "bus";</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_THS&gt;;</div><div class='add'>+			nvmem-cells = &lt;&amp;ths_calibration&gt;;</div><div class='add'>+			nvmem-cell-names = "calibration";</div><div class='add'>+			allwinner,sram = &lt;&amp;syscon&gt;;</div><div class='add'>+			#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		lradc: lradc@5070800 {</div><div class='add'>+			compatible = "allwinner,sun50i-h616-lradc",</div><div class='add'>+				     "allwinner,sun50i-r329-lradc";</div><div class='add'>+			reg = &lt;0x05070800 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_KEYADC&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_KEYADC&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spdif: spdif@5093000 {</div><div class='add'>+			compatible = "allwinner,sun50i-h616-spdif";</div><div class='add'>+			reg = &lt;0x05093000 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_SPDIF&gt;, &lt;&amp;ccu CLK_SPDIF&gt;;</div><div class='add'>+			clock-names = "apb", "spdif";</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_SPDIF&gt;;</div><div class='add'>+			dmas = &lt;&amp;dma 2&gt;;</div><div class='add'>+			dma-names = "tx";</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;spdif_tx_pin&gt;;</div><div class='add'>+			#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		codec: codec@5096000 {</div><div class='add'>+			#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+			compatible = "allwinner,sun50i-h616-codec";</div><div class='add'>+			reg = &lt;0x05096000 0x31c&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_AUDIO_CODEC&gt;,</div><div class='add'>+				 &lt;&amp;ccu CLK_AUDIO_CODEC_1X&gt;;</div><div class='add'>+			clock-names = "apb", "codec";</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_AUDIO_CODEC&gt;;</div><div class='add'>+			dmas = &lt;&amp;dma 6&gt;;</div><div class='add'>+			dma-names = "tx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usbotg: usb@5100000 {</div><div class='add'>+			compatible = "allwinner,sun50i-h616-musb",</div><div class='add'>+				     "allwinner,sun8i-h3-musb";</div><div class='add'>+			reg = &lt;0x05100000 0x0400&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_OTG&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_OTG&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "mc";</div><div class='add'>+			phys = &lt;&amp;usbphy 0&gt;;</div><div class='add'>+			phy-names = "usb";</div><div class='add'>+			extcon = &lt;&amp;usbphy 0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usbphy: phy@5100400 {</div><div class='add'>+			compatible = "allwinner,sun50i-h616-usb-phy";</div><div class='add'>+			reg = &lt;0x05100400 0x24&gt;,</div><div class='add'>+			      &lt;0x05101800 0x14&gt;,</div><div class='add'>+			      &lt;0x05200800 0x14&gt;,</div><div class='add'>+			      &lt;0x05310800 0x14&gt;,</div><div class='add'>+			      &lt;0x05311800 0x14&gt;;</div><div class='add'>+			reg-names = "phy_ctrl",</div><div class='add'>+				    "pmu0",</div><div class='add'>+				    "pmu1",</div><div class='add'>+				    "pmu2",</div><div class='add'>+				    "pmu3";</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_USB_PHY0&gt;,</div><div class='add'>+				 &lt;&amp;ccu CLK_USB_PHY1&gt;,</div><div class='add'>+				 &lt;&amp;ccu CLK_USB_PHY2&gt;,</div><div class='add'>+				 &lt;&amp;ccu CLK_USB_PHY3&gt;,</div><div class='add'>+				 &lt;&amp;ccu CLK_BUS_EHCI2&gt;;</div><div class='add'>+			clock-names = "usb0_phy",</div><div class='add'>+				      "usb1_phy",</div><div class='add'>+				      "usb2_phy",</div><div class='add'>+				      "usb3_phy",</div><div class='add'>+				      "pmu2_clk";</div><div class='add'>+			resets = &lt;&amp;ccu RST_USB_PHY0&gt;,</div><div class='add'>+				 &lt;&amp;ccu RST_USB_PHY1&gt;,</div><div class='add'>+				 &lt;&amp;ccu RST_USB_PHY2&gt;,</div><div class='add'>+				 &lt;&amp;ccu RST_USB_PHY3&gt;;</div><div class='add'>+			reset-names = "usb0_reset",</div><div class='add'>+				      "usb1_reset",</div><div class='add'>+				      "usb2_reset",</div><div class='add'>+				      "usb3_reset";</div><div class='add'>+			status = "disabled";</div><div class='add'>+			#phy-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ehci0: usb@5101000 {</div><div class='add'>+			compatible = "allwinner,sun50i-h616-ehci",</div><div class='add'>+				     "generic-ehci";</div><div class='add'>+			reg = &lt;0x05101000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_OHCI0&gt;,</div><div class='add'>+				 &lt;&amp;ccu CLK_BUS_EHCI0&gt;,</div><div class='add'>+				 &lt;&amp;ccu CLK_USB_OHCI0&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_OHCI0&gt;,</div><div class='add'>+				 &lt;&amp;ccu RST_BUS_EHCI0&gt;;</div><div class='add'>+			phys = &lt;&amp;usbphy 0&gt;;</div><div class='add'>+			phy-names = "usb";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ohci0: usb@5101400 {</div><div class='add'>+			compatible = "allwinner,sun50i-h616-ohci",</div><div class='add'>+				     "generic-ohci";</div><div class='add'>+			reg = &lt;0x05101400 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_OHCI0&gt;,</div><div class='add'>+				 &lt;&amp;ccu CLK_USB_OHCI0&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_OHCI0&gt;;</div><div class='add'>+			phys = &lt;&amp;usbphy 0&gt;;</div><div class='add'>+			phy-names = "usb";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ehci1: usb@5200000 {</div><div class='add'>+			compatible = "allwinner,sun50i-h616-ehci",</div><div class='add'>+				     "generic-ehci";</div><div class='add'>+			reg = &lt;0x05200000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_OHCI1&gt;,</div><div class='add'>+				 &lt;&amp;ccu CLK_BUS_EHCI1&gt;,</div><div class='add'>+				 &lt;&amp;ccu CLK_USB_OHCI1&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_OHCI1&gt;,</div><div class='add'>+				 &lt;&amp;ccu RST_BUS_EHCI1&gt;;</div><div class='add'>+			phys = &lt;&amp;usbphy 1&gt;;</div><div class='add'>+			phy-names = "usb";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ohci1: usb@5200400 {</div><div class='add'>+			compatible = "allwinner,sun50i-h616-ohci",</div><div class='add'>+				     "generic-ohci";</div><div class='add'>+			reg = &lt;0x05200400 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_OHCI1&gt;,</div><div class='add'>+				 &lt;&amp;ccu CLK_USB_OHCI1&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_OHCI1&gt;;</div><div class='add'>+			phys = &lt;&amp;usbphy 1&gt;;</div><div class='add'>+			phy-names = "usb";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ehci2: usb@5310000 {</div><div class='add'>+			compatible = "allwinner,sun50i-h616-ehci",</div><div class='add'>+				     "generic-ehci";</div><div class='add'>+			reg = &lt;0x05310000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_OHCI2&gt;,</div><div class='add'>+				 &lt;&amp;ccu CLK_BUS_EHCI2&gt;,</div><div class='add'>+				 &lt;&amp;ccu CLK_USB_OHCI2&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_OHCI2&gt;,</div><div class='add'>+				 &lt;&amp;ccu RST_BUS_EHCI2&gt;;</div><div class='add'>+			phys = &lt;&amp;usbphy 2&gt;;</div><div class='add'>+			phy-names = "usb";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ohci2: usb@5310400 {</div><div class='add'>+			compatible = "allwinner,sun50i-h616-ohci",</div><div class='add'>+				     "generic-ohci";</div><div class='add'>+			reg = &lt;0x05310400 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_OHCI2&gt;,</div><div class='add'>+				 &lt;&amp;ccu CLK_USB_OHCI2&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_OHCI2&gt;;</div><div class='add'>+			phys = &lt;&amp;usbphy 2&gt;;</div><div class='add'>+			phy-names = "usb";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ehci3: usb@5311000 {</div><div class='add'>+			compatible = "allwinner,sun50i-h616-ehci",</div><div class='add'>+				     "generic-ehci";</div><div class='add'>+			reg = &lt;0x05311000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_OHCI3&gt;,</div><div class='add'>+				 &lt;&amp;ccu CLK_BUS_EHCI3&gt;,</div><div class='add'>+				 &lt;&amp;ccu CLK_USB_OHCI3&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_OHCI3&gt;,</div><div class='add'>+				 &lt;&amp;ccu RST_BUS_EHCI3&gt;;</div><div class='add'>+			phys = &lt;&amp;usbphy 3&gt;;</div><div class='add'>+			phy-names = "usb";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ohci3: usb@5311400 {</div><div class='add'>+			compatible = "allwinner,sun50i-h616-ohci",</div><div class='add'>+				     "generic-ohci";</div><div class='add'>+			reg = &lt;0x05311400 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_OHCI3&gt;,</div><div class='add'>+				 &lt;&amp;ccu CLK_USB_OHCI3&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_OHCI3&gt;;</div><div class='add'>+			phys = &lt;&amp;usbphy 3&gt;;</div><div class='add'>+			phy-names = "usb";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rtc: rtc@7000000 {</div><div class='add'>+			compatible = "allwinner,sun50i-h616-rtc";</div><div class='add'>+			reg = &lt;0x07000000 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;r_ccu CLK_R_APB1_RTC&gt;, &lt;&amp;osc24M&gt;,</div><div class='add'>+				 &lt;&amp;ccu CLK_PLL_SYSTEM_32K&gt;;</div><div class='add'>+			clock-names = "bus", "hosc",</div><div class='add'>+				      "pll-32k";</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		r_ccu: clock@7010000 {</div><div class='add'>+			compatible = "allwinner,sun50i-h616-r-ccu";</div><div class='add'>+			reg = &lt;0x07010000 0x210&gt;;</div><div class='add'>+			clocks = &lt;&amp;osc24M&gt;, &lt;&amp;rtc CLK_OSC32K&gt;, &lt;&amp;rtc CLK_IOSC&gt;,</div><div class='add'>+				 &lt;&amp;ccu CLK_PLL_PERIPH0&gt;;</div><div class='add'>+			clock-names = "hosc", "losc", "iosc", "pll-periph";</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		prcm_ppu: power-controller@7010250 {</div><div class='add'>+			compatible = "allwinner,sun50i-h616-prcm-ppu";</div><div class='add'>+			reg = &lt;0x07010250 0x10&gt;;</div><div class='add'>+			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nmi_intc: interrupt-controller@7010320 {</div><div class='add'>+			compatible = "allwinner,sun50i-h616-nmi",</div><div class='add'>+				     "allwinner,sun9i-a80-nmi";</div><div class='add'>+			reg = &lt;0x07010320 0xc&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		r_pio: pinctrl@7022000 {</div><div class='add'>+			compatible = "allwinner,sun50i-h616-r-pinctrl";</div><div class='add'>+			reg = &lt;0x07022000 0x400&gt;;</div><div class='add'>+			clocks = &lt;&amp;r_ccu CLK_R_APB1&gt;, &lt;&amp;osc24M&gt;,</div><div class='add'>+				 &lt;&amp;rtc CLK_OSC32K&gt;;</div><div class='add'>+			clock-names = "apb", "hosc", "losc";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+			/omit-if-no-ref/</div><div class='add'>+			r_i2c_pins: r-i2c-pins {</div><div class='add'>+				pins = "PL0", "PL1";</div><div class='add'>+				function = "s_i2c";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			r_rsb_pins: r-rsb-pins {</div><div class='add'>+				pins = "PL0", "PL1";</div><div class='add'>+				function = "s_rsb";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ir: ir@7040000 {</div><div class='add'>+			compatible = "allwinner,sun50i-h616-ir",</div><div class='add'>+				     "allwinner,sun6i-a31-ir";</div><div class='add'>+			reg = &lt;0x07040000 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;r_ccu CLK_R_APB1_IR&gt;,</div><div class='add'>+				 &lt;&amp;r_ccu CLK_IR&gt;;</div><div class='add'>+			clock-names = "apb", "ir";</div><div class='add'>+			resets = &lt;&amp;r_ccu RST_R_APB1_IR&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;ir_rx_pin&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		r_i2c: i2c@7081400 {</div><div class='add'>+			compatible = "allwinner,sun50i-h616-i2c",</div><div class='add'>+				     "allwinner,sun8i-v536-i2c",</div><div class='add'>+				     "allwinner,sun6i-a31-i2c";</div><div class='add'>+			reg = &lt;0x07081400 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;r_ccu CLK_R_APB2_I2C&gt;;</div><div class='add'>+			dmas = &lt;&amp;dma 48&gt;, &lt;&amp;dma 48&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+			resets = &lt;&amp;r_ccu RST_R_APB2_I2C&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;r_i2c_pins&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		r_rsb: rsb@7083000 {</div><div class='add'>+			compatible = "allwinner,sun50i-h616-rsb",</div><div class='add'>+				     "allwinner,sun8i-a23-rsb";</div><div class='add'>+			reg = &lt;0x07083000 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;r_ccu CLK_R_APB2_RSB&gt;;</div><div class='add'>+			clock-frequency = &lt;3000000&gt;;</div><div class='add'>+			resets = &lt;&amp;r_ccu RST_R_APB2_RSB&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;r_rsb_pins&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	thermal-zones {</div><div class='add'>+		cpu-thermal {</div><div class='add'>+			polling-delay-passive = &lt;500&gt;;</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;ths 2&gt;;</div><div class='add'>+			sustainable-power = &lt;1000&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu_threshold: cpu-trip-0 {</div><div class='add'>+					temperature = &lt;60000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+				cpu_target: cpu-trip-1 {</div><div class='add'>+					temperature = &lt;70000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+				cpu_critical: cpu-trip-2 {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu-thermal {</div><div class='add'>+			polling-delay-passive = &lt;500&gt;;</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;ths 0&gt;;</div><div class='add'>+			sustainable-power = &lt;1100&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				gpu_temp_critical: gpu-trip-0 {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ve-thermal {</div><div class='add'>+			polling-delay-passive = &lt;0&gt;;</div><div class='add'>+			polling-delay = &lt;0&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;ths 1&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				ve_temp_critical: ve-trip-0 {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ddr-thermal {</div><div class='add'>+			polling-delay-passive = &lt;0&gt;;</div><div class='add'>+			polling-delay = &lt;0&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;ths 3&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				ddr_temp_critical: ddr-trip-0 {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-longan-module-3h.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h618-longan-module-3h.dtsi<br/>new file mode 100644<br/>index 000000000000..3f416d129b72<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h618-longan-module-3h.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h618-longan-module-3h.dtsi</a></div><div class='hunk'>@@ -0,0 +1,85 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) Jisheng Zhang &lt;jszhang@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "sun50i-h616.dtsi"</div><div class='add'>+#include "sun50i-h616-cpu-opp.dtsi"</div><div class='add'>+</div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_dcdc2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	mali-supply = &lt;&amp;reg_dcdc1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc2_pins&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_dldo1&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_aldo1&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	cap-mmc-hw-reset;</div><div class='add'>+	mmc-ddr-1_8v;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;r_i2c {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	axp313: pmic@36 {</div><div class='add'>+		compatible = "x-powers,axp313a";</div><div class='add'>+		reg = &lt;0x36&gt;;</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			reg_aldo1: aldo1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "vcc-1v8-pll";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_dldo1: dldo1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "vcc-3v3-io";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_dcdc1: dcdc1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;810000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;990000&gt;;</div><div class='add'>+				regulator-name = "vdd-gpu-sys";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_dcdc2: dcdc2 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;810000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-name = "vdd-cpu";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_dcdc3: dcdc3 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-name = "vdd-dram";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	vcc-pc-supply = &lt;&amp;reg_dldo1&gt;;</div><div class='add'>+	vcc-pf-supply = &lt;&amp;reg_dldo1&gt;;</div><div class='add'>+	vcc-pg-supply = &lt;&amp;reg_aldo1&gt;;</div><div class='add'>+	vcc-ph-supply = &lt;&amp;reg_dldo1&gt;;</div><div class='add'>+	vcc-pi-supply = &lt;&amp;reg_dldo1&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-longanpi-3h.dts b/arch/arm64/boot/dts/allwinner/sun50i-h618-longanpi-3h.dts<br/>new file mode 100644<br/>index 000000000000..16c68177ff69<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h618-longanpi-3h.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h618-longanpi-3h.dts</a></div><div class='hunk'>@@ -0,0 +1,145 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) Jisheng Zhang &lt;jszhang@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "sun50i-h618-longan-module-3h.dtsi"</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Sipeed Longan Pi 3H";</div><div class='add'>+	compatible = "sipeed,longan-pi-3h", "sipeed,longan-module-3h", "allwinner,sun50i-h618";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;emac0;</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_ORANGE&gt;;</div><div class='add'>+			function = LED_FUNCTION_INDICATOR;</div><div class='add'>+			function-enumerator = &lt;0&gt;;</div><div class='add'>+			gpios = &lt;&amp;pio 6 2 GPIO_ACTIVE_LOW&gt;; /* PG2 */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_ORANGE&gt;;</div><div class='add'>+			function = LED_FUNCTION_INDICATOR;</div><div class='add'>+			function-enumerator = &lt;1&gt;;</div><div class='add'>+			gpios = &lt;&amp;pio 6 4 GPIO_ACTIVE_LOW&gt;; /* PG4 */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc5v: regulator-vcc5v {</div><div class='add'>+		/* board wide 5V supply directly from the USB-C socket */</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vcc-5v";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc3v3: regulator-vcc3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vcc-3v3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		vin-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;axp313 {</div><div class='add'>+	vin1-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+	vin2-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+	vin3-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ehci1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ohci1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ehci2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ohci2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* WiFi &amp; BT combo module is connected to this Host */</div><div class='add'>+&amp;ehci3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ohci3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;emac0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;ext_rgmii_pins&gt;;</div><div class='add'>+	phy-mode = "rgmii";</div><div class='add'>+	phy-handle = &lt;&amp;ext_rgmii_phy&gt;;</div><div class='add'>+	allwinner,rx-delay-ps = &lt;3100&gt;;</div><div class='add'>+	allwinner,tx-delay-ps = &lt;700&gt;;</div><div class='add'>+	phy-supply = &lt;&amp;reg_vcc3v3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdio0 {</div><div class='add'>+	ext_rgmii_phy: ethernet-phy@1 {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc0 {</div><div class='add'>+	disable-wp;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;pio 5 6 GPIO_ACTIVE_HIGH&gt;;	/* PF6 */</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_vcc3v3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg {</div><div class='add'>+	/*</div><div class='add'>+	 * PHY0 pins are connected to a USB-C socket, but a role switch</div><div class='add'>+	 * is not implemented: both CC pins are pulled to GND.</div><div class='add'>+	 * The VBUS pins power the device, so a fixed peripheral mode</div><div class='add'>+	 * is the best choice.</div><div class='add'>+	 * The board can be powered via GPIOs, in this case port0 *can*</div><div class='add'>+	 * act as a host (with a cable/adapter ignoring CC), as VBUS is</div><div class='add'>+	 * then provided by the GPIOs. Any user of this setup would</div><div class='add'>+	 * need to adjust the DT accordingly: dr_mode set to "host",</div><div class='add'>+	 * enabling OHCI0 and EHCI0.</div><div class='add'>+	 */</div><div class='add'>+	dr_mode = "peripheral";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbphy {</div><div class='add'>+	usb1_vbus-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+	usb2_vbus-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts<br/>new file mode 100644<br/>index 000000000000..b340bbcb710d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts</a></div><div class='hunk'>@@ -0,0 +1,191 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2023 Arm Ltd.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "sun50i-h616.dtsi"</div><div class='add'>+#include "sun50i-h616-cpu-opp.dtsi"</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "OrangePi Zero 2W";</div><div class='add'>+	compatible = "xunlong,orangepi-zero2w", "allwinner,sun50i-h618";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			gpios = &lt;&amp;pio 2 13 GPIO_ACTIVE_HIGH&gt;; /* PC13 */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc5v: vcc5v {</div><div class='add'>+		/* board wide 5V supply directly from the USB-C socket */</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vcc-5v";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc3v3: vcc3v3 {</div><div class='add'>+		/* SY8089 DC/DC converter */</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vcc-3v3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;codec {</div><div class='add'>+	allwinner,audio-routing = "Line Out", "LINEOUT";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_dcdc2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ehci1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB 2 &amp; 3 are on the FPC connector (or the exansion board) */</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	mali-supply = &lt;&amp;reg_dcdc1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc0 {</div><div class='add'>+	cd-gpios = &lt;&amp;pio 5 6 GPIO_ACTIVE_LOW&gt;;	/* PF6 */</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_vcc3v3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ohci1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	vcc-pc-supply = &lt;&amp;reg_dldo1&gt;;</div><div class='add'>+	vcc-pf-supply = &lt;&amp;reg_dldo1&gt;;	/* internally via VCC-IO */</div><div class='add'>+	vcc-pg-supply = &lt;&amp;reg_aldo1&gt;;</div><div class='add'>+	vcc-ph-supply = &lt;&amp;reg_dldo1&gt;;	/* internally via VCC-IO */</div><div class='add'>+	vcc-pi-supply = &lt;&amp;reg_dldo1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;r_i2c {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	axp313: pmic@36 {</div><div class='add'>+		compatible = "x-powers,axp313a";</div><div class='add'>+		reg = &lt;0x36&gt;;</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		interrupt-parent = &lt;&amp;pio&gt;;</div><div class='add'>+		interrupts = &lt;2 9 IRQ_TYPE_LEVEL_LOW&gt;;	/* PC9 */</div><div class='add'>+</div><div class='add'>+		vin1-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vin2-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vin3-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			/* Supplies VCC-PLL and DRAM */</div><div class='add'>+			reg_aldo1: aldo1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "vcc1v8";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* Supplies VCC-IO, so needs to be always on. */</div><div class='add'>+			reg_dldo1: dldo1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "vcc3v3";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_dcdc1: dcdc1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;810000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;990000&gt;;</div><div class='add'>+				regulator-name = "vdd-gpu-sys";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_dcdc2: dcdc2 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;810000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-name = "vdd-cpu";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_dcdc3: dcdc3 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-name = "vdd-dram";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi0  {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;spi0_pins&gt;, &lt;&amp;spi0_cs0_pin&gt;;</div><div class='add'>+</div><div class='add'>+	flash@0 {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;40000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart0_ph_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg {</div><div class='add'>+	/*</div><div class='add'>+	 * PHY0 pins are connected to a USB-C socket, but a role switch</div><div class='add'>+	 * is not implemented: both CC pins are pulled to GND.</div><div class='add'>+	 * The VBUS pins power the device, so a fixed peripheral mode</div><div class='add'>+	 * is the best choice.</div><div class='add'>+	 * The board can be powered via GPIOs, in this case port0 *can*</div><div class='add'>+	 * act as a host (with a cable/adapter ignoring CC), as VBUS is</div><div class='add'>+	 * then provided by the GPIOs. Any user of this setup would</div><div class='add'>+	 * need to adjust the DT accordingly: dr_mode set to "host",</div><div class='add'>+	 * enabling OHCI0 and EHCI0.</div><div class='add'>+	 */</div><div class='add'>+	dr_mode = "peripheral";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbphy {</div><div class='add'>+	usb1_vbus-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts<br/>new file mode 100644<br/>index 000000000000..c51d4d9120de<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts</a></div><div class='hunk'>@@ -0,0 +1,105 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2023 Arm Ltd.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "sun50i-h616-orangepi-zero.dtsi"</div><div class='add'>+#include "sun50i-h616-cpu-opp.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "OrangePi Zero3";</div><div class='add'>+	compatible = "xunlong,orangepi-zero3", "allwinner,sun50i-h618";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_dcdc2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;emac0 {</div><div class='add'>+	allwinner,tx-delay-ps = &lt;700&gt;;</div><div class='add'>+	phy-mode = "rgmii-rxid";</div><div class='add'>+	phy-supply = &lt;&amp;reg_dldo1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ext_rgmii_phy {</div><div class='add'>+	motorcomm,clk-out-frequency-hz = &lt;125000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	mali-supply = &lt;&amp;reg_dcdc1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc0 {</div><div class='add'>+	/*</div><div class='add'>+	 * The schematic shows the card detect pin wired up to PF6, via an</div><div class='add'>+	 * inverter, but it just doesn't work.</div><div class='add'>+	 */</div><div class='add'>+	broken-cd;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_dldo1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;r_i2c {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	axp313: pmic@36 {</div><div class='add'>+		compatible = "x-powers,axp313a";</div><div class='add'>+		reg = &lt;0x36&gt;;</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		interrupt-parent = &lt;&amp;pio&gt;;</div><div class='add'>+		interrupts = &lt;2 9 IRQ_TYPE_LEVEL_LOW&gt;;	/* PC9 */</div><div class='add'>+</div><div class='add'>+		vin1-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vin2-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vin3-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			/* Supplies VCC-PLL, so needs to be always on. */</div><div class='add'>+			reg_aldo1: aldo1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "vcc1v8";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* Supplies VCC-IO, so needs to be always on. */</div><div class='add'>+			reg_dldo1: dldo1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "vcc3v3";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_dcdc1: dcdc1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;810000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;990000&gt;;</div><div class='add'>+				regulator-name = "vdd-gpu-sys";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_dcdc2: dcdc2 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;810000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-name = "vdd-cpu";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_dcdc3: dcdc3 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-name = "vdd-dram";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	vcc-pc-supply = &lt;&amp;reg_dldo1&gt;;</div><div class='add'>+	vcc-pf-supply = &lt;&amp;reg_dldo1&gt;;</div><div class='add'>+	vcc-pg-supply = &lt;&amp;reg_aldo1&gt;;</div><div class='add'>+	vcc-ph-supply = &lt;&amp;reg_dldo1&gt;;</div><div class='add'>+	vcc-pi-supply = &lt;&amp;reg_dldo1&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-transpeed-8k618-t.dts b/arch/arm64/boot/dts/allwinner/sun50i-h618-transpeed-8k618-t.dts<br/>new file mode 100644<br/>index 000000000000..efe0faa252f5<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h618-transpeed-8k618-t.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h618-transpeed-8k618-t.dts</a></div><div class='hunk'>@@ -0,0 +1,200 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2023 Arm Ltd.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "sun50i-h616.dtsi"</div><div class='add'>+#include "sun50i-h616-cpu-opp.dtsi"</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Transpeed 8K618-T";</div><div class='add'>+	compatible = "transpeed,8k618-t", "allwinner,sun50i-h618";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet1 = &amp;sdio_wifi;</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc5v: vcc5v {</div><div class='add'>+		/* board wide 5V supply directly from the DC input */</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vcc-5v";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc3v3: vcc3v3 {</div><div class='add'>+		/* discrete 3.3V regulator */</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vcc-3v3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wifi_pwrseq: pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-simple";</div><div class='add'>+		clocks = &lt;&amp;rtc CLK_OSC32K_FANOUT&gt;;</div><div class='add'>+		clock-names = "ext_clock";</div><div class='add'>+		pinctrl-0 = &lt;&amp;x32clk_fanout_pin&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		reset-gpios = &lt;&amp;pio 6 18 GPIO_ACTIVE_LOW&gt;; /* PG18 */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;codec {</div><div class='add'>+	allwinner,audio-routing = "Line Out", "LINEOUT";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_dcdc2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ehci0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ehci1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	mali-supply = &lt;&amp;reg_dcdc1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ir {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc0 {</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_dldo1&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;pio 8 16 GPIO_ACTIVE_LOW&gt;;	/* PI16 */</div><div class='add'>+	disable-wp;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc1 {</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_dldo1&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_aldo1&gt;;</div><div class='add'>+	mmc-pwrseq = &lt;&amp;wifi_pwrseq&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	sdio_wifi: wifi@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc2 {</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_dldo1&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_aldo1&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	cap-mmc-hw-reset;</div><div class='add'>+	mmc-ddr-1_8v;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ohci0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ohci1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;r_i2c {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	axp313: pmic@36 {</div><div class='add'>+		compatible = "x-powers,axp313a";</div><div class='add'>+		reg = &lt;0x36&gt;;</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+</div><div class='add'>+		vin1-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vin2-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vin3-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			reg_aldo1: aldo1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "vcc-1v8-pll";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_dldo1: dldo1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "vcc-3v3-io-mmc";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_dcdc1: dcdc1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;810000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;990000&gt;;</div><div class='add'>+				regulator-name = "vdd-gpu-sys";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_dcdc2: dcdc2 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;810000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-name = "vdd-cpu";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_dcdc3: dcdc3 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;1360000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1360000&gt;;</div><div class='add'>+				regulator-name = "vdd-dram";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	vcc-pc-supply = &lt;&amp;reg_aldo1&gt;;</div><div class='add'>+	vcc-pg-supply = &lt;&amp;reg_dldo1&gt;;</div><div class='add'>+	vcc-ph-supply = &lt;&amp;reg_dldo1&gt;;</div><div class='add'>+	vcc-pi-supply = &lt;&amp;reg_dldo1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart0_ph_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart1_pins&gt;, &lt;&amp;uart1_rts_cts_pins&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg {</div><div class='add'>+	dr_mode = "host";	/* USB A type receptable */</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbphy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-yuzukihd-chameleon.dts b/arch/arm64/boot/dts/allwinner/sun50i-h618-yuzukihd-chameleon.dts<br/>new file mode 100644<br/>index 000000000000..eae56908b9b4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h618-yuzukihd-chameleon.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h618-yuzukihd-chameleon.dts</a></div><div class='hunk'>@@ -0,0 +1,222 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2024 Arm Ltd.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "sun50i-h616.dtsi"</div><div class='add'>+#include "sun50i-h616-cpu-opp.dtsi"</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Yuzuki Chameleon";</div><div class='add'>+	compatible = "yuzukihd,chameleon", "allwinner,sun50i-h618";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet1 = &amp;sdio_wifi;</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc5v: vcc5v {</div><div class='add'>+		/* board wide 5V supply directly from the USB-C socket */</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vcc-5v";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wifi_pwrseq: pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-simple";</div><div class='add'>+		clocks = &lt;&amp;rtc CLK_OSC32K_FANOUT&gt;;</div><div class='add'>+		clock-names = "ext_clock";</div><div class='add'>+		pinctrl-0 = &lt;&amp;x32clk_fanout_pin&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		reset-gpios = &lt;&amp;pio 6 11 GPIO_ACTIVE_LOW&gt;; /* PG11 */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;codec {</div><div class='add'>+	allwinner,audio-routing = "Line Out", "LINEOUT";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_dcdc2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ehci0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ehci1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ehci2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ehci3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc0 {</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;pio 5 6 GPIO_ACTIVE_LOW&gt;;	/* PF6 */</div><div class='add'>+	disable-wp;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_dldo1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc1 {</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	mmc-pwrseq = &lt;&amp;wifi_pwrseq&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_dldo1&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_dldo1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	sdio_wifi: wifi@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;pio&gt;;</div><div class='add'>+		interrupts = &lt;6 12 IRQ_TYPE_LEVEL_LOW&gt;;  /* PG12 */</div><div class='add'>+		interrupt-names = "host-wake";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc2 {</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	cap-mmc-hw-reset;</div><div class='add'>+	mmc-ddr-3_3v;</div><div class='add'>+	non-removable;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_dldo1&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_dldo1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ohci0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ohci1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ohci2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ohci3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	vcc-pc-supply = &lt;&amp;reg_dldo1&gt;;</div><div class='add'>+	vcc-pf-supply = &lt;&amp;reg_dldo1&gt;;	/* via VCC_IO */</div><div class='add'>+	vcc-pg-supply = &lt;&amp;reg_dldo1&gt;;</div><div class='add'>+	vcc-ph-supply = &lt;&amp;reg_dldo1&gt;;	/* via VCC_IO */</div><div class='add'>+	vcc-pi-supply = &lt;&amp;reg_dldo1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;r_i2c {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	axp313: pmic@36 {</div><div class='add'>+		compatible = "x-powers,axp313a";</div><div class='add'>+		reg = &lt;0x36&gt;;</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		interrupt-parent = &lt;&amp;pio&gt;;</div><div class='add'>+		interrupts = &lt;2 2 IRQ_TYPE_LEVEL_LOW&gt;;	/* PC2 */</div><div class='add'>+</div><div class='add'>+		vin1-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vin2-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vin3-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			/* Supplies VCC-PLL, so needs to be always on. */</div><div class='add'>+			reg_aldo1: aldo1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "vcc1v8";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* Supplies VCC-IO, so needs to be always on. */</div><div class='add'>+			reg_dldo1: dldo1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "vcc3v3";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_dcdc1: dcdc1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;810000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;990000&gt;;</div><div class='add'>+				regulator-name = "vdd-gpu-sys";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_dcdc2: dcdc2 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;810000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-name = "vdd-cpu";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_dcdc3: dcdc3 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;1500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1500000&gt;;</div><div class='add'>+				regulator-name = "vdd-dram";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart0_ph_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Connected to the Bluetooth UART pins of the XR829 Wifi/BT chip. */</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart1_pins&gt;, &lt;&amp;uart1_rts_cts_pins&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg {</div><div class='add'>+	/*</div><div class='add'>+	 * PHY0 pins are connected to a USB-C socket, but a role switch</div><div class='add'>+	 * is not implemented: both CC pins are pulled to GND.</div><div class='add'>+	 * The VBUS pins power the device, so a fixed peripheral mode</div><div class='add'>+	 * is the best choice.</div><div class='add'>+	 * The board can be powered via GPIOs, in this case port0 *can*</div><div class='add'>+	 * act as a host (with a cable/adapter ignoring CC), as VBUS is</div><div class='add'>+	 * then provided by the GPIOs. Any user of this setup would</div><div class='add'>+	 * need to adjust the DT accordingly: dr_mode set to "host",</div><div class='add'>+	 * enabling OHCI0 and EHCI0.</div><div class='add'>+	 */</div><div class='add'>+	dr_mode = "peripheral";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbphy {</div><div class='add'>+	usb0_id_det-gpios = &lt;&amp;pio 6 18 GPIO_ACTIVE_HIGH&gt;; /* PG18 */</div><div class='add'>+	usb0_vbus-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+	usb1_vbus-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+	usb2_vbus-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+	usb3_vbus-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h64-remix-mini-pc.dts b/arch/arm64/boot/dts/allwinner/sun50i-h64-remix-mini-pc.dts<br/>new file mode 100644<br/>index 000000000000..ce90327e1b2e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h64-remix-mini-pc.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h64-remix-mini-pc.dts</a></div><div class='hunk'>@@ -0,0 +1,356 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+// Copyright (c) 2023 ARM Ltd.</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "sun50i-a64.dtsi"</div><div class='add'>+#include "sun50i-a64-cpu-opp.dtsi"</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Remix Mini PC";</div><div class='add'>+	compatible = "jide,remix-mini-pc", "allwinner,sun50i-h64",</div><div class='add'>+		     "allwinner,sun50i-a64";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet1 = &amp;rtl8723bs;</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdmi-connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		type = "a";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			hdmi_con_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_out_con&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc5v: regulator-5v {</div><div class='add'>+		/* board wide 5V supply directly from the DC input */</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vcc-5v";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wifi_pwrseq: pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-simple";</div><div class='add'>+		reset-gpios = &lt;&amp;r_pio 0 2 GPIO_ACTIVE_LOW&gt;; /* PL2 */</div><div class='add'>+		post-power-on-delay-ms = &lt;200&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;codec {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;codec_analog {</div><div class='add'>+	cpvdd-supply = &lt;&amp;reg_eldo1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_dcdc2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu1 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_dcdc2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu2 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_dcdc2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu3 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_dcdc2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dai {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;de {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ehci0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ehci1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi {</div><div class='add'>+	hvcc-supply = &lt;&amp;reg_dldo1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_out {</div><div class='add'>+	hdmi_out_con: endpoint {</div><div class='add'>+		remote-endpoint = &lt;&amp;hdmi_con_in&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Connects to the AC200 chip */</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c0_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0_pins {</div><div class='add'>+	bias-pull-up;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc0_pins&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_dcdc1&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;pio 5 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc1_pins&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_aldo1&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_dldo4&gt;;</div><div class='add'>+	mmc-pwrseq = &lt;&amp;wifi_pwrseq&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	rtl8723bs: wifi@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;r_pio&gt;;</div><div class='add'>+		interrupts = &lt;0 3 IRQ_TYPE_LEVEL_LOW&gt;; /* PL3 */</div><div class='add'>+		interrupt-names = "host-wake";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc2_pins&gt;, &lt;&amp;mmc2_ds_pin&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_dcdc1&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_eldo1&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	mmc-hs400-1_8v;</div><div class='add'>+	cap-mmc-hw-reset;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ohci0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ohci1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	vcc-pb-supply = &lt;&amp;reg_dcdc1&gt;;</div><div class='add'>+	vcc-pc-supply = &lt;&amp;reg_dcdc1&gt;;</div><div class='add'>+	vcc-pd-supply = &lt;&amp;reg_dcdc1&gt;;</div><div class='add'>+	vcc-pe-supply = &lt;&amp;reg_dcdc1&gt;;</div><div class='add'>+	vcc-pf-supply = &lt;&amp;reg_dcdc1&gt;;</div><div class='add'>+	vcc-pg-supply = &lt;&amp;reg_dldo4&gt;;</div><div class='add'>+	vcc-ph-supply = &lt;&amp;reg_dcdc1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;r_ir {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;r_pio {</div><div class='add'>+	/*</div><div class='add'>+	 * We cannot add that supply for now since it would create a circular</div><div class='add'>+	 * dependency between pinctrl, the regulator and the RSB Bus.</div><div class='add'>+	 *</div><div class='add'>+	 * vcc-pl-supply = &lt;&amp;reg_aldo2&gt;;</div><div class='add'>+	 */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;r_rsb {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	axp803: pmic@3a3 {</div><div class='add'>+		compatible = "x-powers,axp803";</div><div class='add'>+		reg = &lt;0x3a3&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;r_intc&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		x-powers,drive-vbus-en;</div><div class='add'>+</div><div class='add'>+		vin1-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vin2-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vin3-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vin5-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vin6-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		aldoin-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		dldoin-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		eldoin-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		fldoin-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		drivevbus-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		ips-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include "axp803.dtsi"</div><div class='add'>+</div><div class='add'>+&amp;ac_power_supply {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_dcdc1 {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+	regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	regulator-name = "vcc-3v3";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_dcdc2 {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+	regulator-min-microvolt = &lt;1040000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+	regulator-name = "vdd-cpux";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* DCDC3 is polyphased with DCDC2 */</div><div class='add'>+</div><div class='add'>+&amp;reg_dcdc5 {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+	regulator-min-microvolt = &lt;1500000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;1500000&gt;;</div><div class='add'>+	regulator-name = "vcc-dram";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Deviates from the reset default of 1.1V. */</div><div class='add'>+&amp;reg_dcdc6 {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+	regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+	regulator-name = "vdd-sys";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_aldo1 {</div><div class='add'>+	regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	regulator-name = "vcc-wifi";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_aldo2 {</div><div class='add'>+	/* Specifying R_PIO consumer would create circular dependency. */</div><div class='add'>+	regulator-always-on;</div><div class='add'>+	regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	regulator-name = "vcc-pl";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_aldo3 {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+	regulator-min-microvolt = &lt;3000000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;3000000&gt;;</div><div class='add'>+	regulator-name = "vcc-pll-avcc";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* AC200 power supply */</div><div class='add'>+&amp;reg_dldo1 {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+	regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	regulator-name = "vcc-ave-33";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_dldo4 {</div><div class='add'>+	regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	regulator-name = "vcc-wifi-io";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_drivevbus {</div><div class='add'>+	regulator-name = "usb0-vbus";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_eldo1 {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+	regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	regulator-name = "vcc-cpvdd-dram-emmc";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Supplies the arisc management core, needed by TF-A to power off cores. */</div><div class='add'>+&amp;reg_fldo2 {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+	regulator-min-microvolt = &lt;1100000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+	regulator-name = "vdd-cpus";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_rtc_ldo {</div><div class='add'>+	regulator-name = "vcc-rtc";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;simplefb_hdmi {</div><div class='add'>+	vcc-hdmi-supply = &lt;&amp;reg_dcdc1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sound {</div><div class='add'>+	simple-audio-card,aux-devs = &lt;&amp;codec_analog&gt;;</div><div class='add'>+	simple-audio-card,widgets = "Microphone", "Microphone Jack",</div><div class='add'>+				    "Headphone", "Headphone Jack";</div><div class='add'>+	simple-audio-card,routing =</div><div class='add'>+			"Left DAC", "DACL",</div><div class='add'>+			"Right DAC", "DACR",</div><div class='add'>+			"Headphone Jack", "HP",</div><div class='add'>+			"ADCL", "Left ADC",</div><div class='add'>+			"ADCR", "Right ADC",</div><div class='add'>+			"MIC2", "Microphone Jack";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* On the (unpopulated) UART pads. */</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart0_pb_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart1_pins&gt;, &lt;&amp;uart1_rts_cts_pins&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "realtek,rtl8723bs-bt";</div><div class='add'>+		enable-gpios = &lt;&amp;r_pio 0 4 GPIO_ACTIVE_HIGH&gt;; /* PL4 */</div><div class='add'>+		max-speed = &lt;1500000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_otg {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbphy {</div><div class='add'>+	usb0_vbus-supply = &lt;&amp;reg_drivevbus&gt;;</div><div class='add'>+	usb1_vbus-supply = &lt;&amp;reg_drivevbus&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts<br/>new file mode 100644<br/>index 000000000000..1a750c5f6fac<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts</a></div><div class='hunk'>@@ -0,0 +1,381 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2024 Ryan Walklin &lt;ryan@testtoast.com&gt;.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "sun50i-h616.dtsi"</div><div class='add'>+#include "sun50i-h616-cpu-opp.dtsi"</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/linux-event-codes.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Anbernic RG35XX 2024";</div><div class='add'>+	chassis-type = "handset";</div><div class='add'>+	compatible = "anbernic,rg35xx-2024", "allwinner,sun50i-h700";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	battery: battery {</div><div class='add'>+		compatible = "simple-battery";</div><div class='add'>+		constant-charge-current-max-microamp = &lt;1024000&gt;;</div><div class='add'>+		voltage-max-design-microvolt = &lt;4200000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio_keys_gamepad: gpio-keys-gamepad {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		button-a {</div><div class='add'>+			label = "Action-Pad A";</div><div class='add'>+			gpios = &lt;&amp;pio 0 0 GPIO_ACTIVE_LOW&gt;; /* PA0 */</div><div class='add'>+			linux,input-type = &lt;EV_KEY&gt;;</div><div class='add'>+			linux,code = &lt;BTN_EAST&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-b {</div><div class='add'>+			label = "Action-Pad B";</div><div class='add'>+			gpios = &lt;&amp;pio 0 1 GPIO_ACTIVE_LOW&gt;; /* PA1 */</div><div class='add'>+			linux,input-type = &lt;EV_KEY&gt;;</div><div class='add'>+			linux,code = &lt;BTN_SOUTH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-down {</div><div class='add'>+			label = "D-Pad Down";</div><div class='add'>+			gpios = &lt;&amp;pio 4 0 GPIO_ACTIVE_LOW&gt;; /* PE0 */</div><div class='add'>+			linux,input-type = &lt;EV_KEY&gt;;</div><div class='add'>+			linux,code = &lt;BTN_DPAD_DOWN&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-l1 {</div><div class='add'>+			label = "Key L1";</div><div class='add'>+			gpios = &lt;&amp;pio 0 10 GPIO_ACTIVE_LOW&gt;; /* PA10 */</div><div class='add'>+			linux,input-type = &lt;EV_KEY&gt;;</div><div class='add'>+			linux,code = &lt;BTN_TL&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-l2 {</div><div class='add'>+			label = "Key L2";</div><div class='add'>+			gpios = &lt;&amp;pio 0 11 GPIO_ACTIVE_LOW&gt;; /* PA11 */</div><div class='add'>+			linux,input-type = &lt;EV_KEY&gt;;</div><div class='add'>+			linux,code = &lt;BTN_TL2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-left {</div><div class='add'>+			label = "D-Pad left";</div><div class='add'>+			gpios = &lt;&amp;pio 0 8 GPIO_ACTIVE_LOW&gt;; /* PA8 */</div><div class='add'>+			linux,input-type = &lt;EV_KEY&gt;;</div><div class='add'>+			linux,code = &lt;BTN_DPAD_LEFT&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-menu {</div><div class='add'>+			label = "Key Menu";</div><div class='add'>+			gpios = &lt;&amp;pio 4 3 GPIO_ACTIVE_LOW&gt;; /* PE3 */</div><div class='add'>+			linux,input-type = &lt;EV_KEY&gt;;</div><div class='add'>+			linux,code = &lt;BTN_MODE&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-r1 {</div><div class='add'>+			label = "Key R1";</div><div class='add'>+			gpios = &lt;&amp;pio 0 12 GPIO_ACTIVE_LOW&gt;; /* PA12 */</div><div class='add'>+			linux,input-type = &lt;EV_KEY&gt;;</div><div class='add'>+			linux,code = &lt;BTN_TR&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-r2 {</div><div class='add'>+			label = "Key R2";</div><div class='add'>+			gpios = &lt;&amp;pio 0 7 GPIO_ACTIVE_LOW&gt;; /* PA7 */</div><div class='add'>+			linux,input-type = &lt;EV_KEY&gt;;</div><div class='add'>+			linux,code = &lt;BTN_TR2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-right {</div><div class='add'>+			label = "D-Pad Right";</div><div class='add'>+			gpios = &lt;&amp;pio 0 9 GPIO_ACTIVE_LOW&gt;; /* PA9 */</div><div class='add'>+			linux,input-type = &lt;EV_KEY&gt;;</div><div class='add'>+			linux,code = &lt;BTN_DPAD_RIGHT&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-select {</div><div class='add'>+			label = "Key Select";</div><div class='add'>+			gpios = &lt;&amp;pio 0 5 GPIO_ACTIVE_LOW&gt;; /* PA5 */</div><div class='add'>+			linux,input-type = &lt;EV_KEY&gt;;</div><div class='add'>+			linux,code = &lt;BTN_SELECT&gt;;</div><div class='add'>+		};</div><div class='add'>+		button-start {</div><div class='add'>+			label = "Key Start";</div><div class='add'>+			gpios = &lt;&amp;pio 0 4 GPIO_ACTIVE_LOW&gt;; /* PA4 */</div><div class='add'>+			linux,input-type = &lt;EV_KEY&gt;;</div><div class='add'>+			linux,code = &lt;BTN_START&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-up {</div><div class='add'>+			label = "D-Pad Up";</div><div class='add'>+			gpios = &lt;&amp;pio 0 6 GPIO_ACTIVE_LOW&gt;; /* PA6 */</div><div class='add'>+			linux,input-type = &lt;EV_KEY&gt;;</div><div class='add'>+			linux,code = &lt;BTN_DPAD_UP&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-x {</div><div class='add'>+			label = "Action-Pad X";</div><div class='add'>+			gpios = &lt;&amp;pio 0 3 GPIO_ACTIVE_LOW&gt;; /* PA3 */</div><div class='add'>+			linux,input-type = &lt;EV_KEY&gt;;</div><div class='add'>+			linux,code = &lt;BTN_NORTH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-y {</div><div class='add'>+			label = "Action Pad Y";</div><div class='add'>+			gpios = &lt;&amp;pio 0 2 GPIO_ACTIVE_LOW&gt;; /* PA2 */</div><div class='add'>+			linux,input-type = &lt;EV_KEY&gt;;</div><div class='add'>+			linux,code = &lt;BTN_WEST&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys-volume {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		autorepeat;</div><div class='add'>+</div><div class='add'>+		button-vol-up {</div><div class='add'>+			label = "Key Volume Up";</div><div class='add'>+			gpios = &lt;&amp;pio 4 1 GPIO_ACTIVE_LOW&gt;; /* PE1 */</div><div class='add'>+			linux,input-type = &lt;EV_KEY&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-vol-down {</div><div class='add'>+			label = "Key Volume Down";</div><div class='add'>+			gpios = &lt;&amp;pio 4 2 GPIO_ACTIVE_LOW&gt;; /* PE2 */</div><div class='add'>+			linux,input-type = &lt;EV_KEY&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			function = LED_FUNCTION_POWER;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			gpios = &lt;&amp;pio 8 12 GPIO_ACTIVE_HIGH&gt;; /* PI12 */</div><div class='add'>+			default-state = "on";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			gpios = &lt;&amp;pio 8 11 GPIO_ACTIVE_HIGH&gt;; /* PI11 */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc5v: regulator-vcc5v { /* USB-C power input */</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vcc-5v";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;codec {</div><div class='add'>+	/* Both speakers and headphone jack connected to 74HC4052D analog mux*/</div><div class='add'>+	allwinner,audio-routing = "Speaker", "LINEOUT",</div><div class='add'>+				  "Headphone", "LINEOUT";</div><div class='add'>+	allwinner,pa-gpios = &lt;&amp;pio 8 5 GPIO_ACTIVE_HIGH&gt;; // PI5</div><div class='add'>+	hp-det-gpios = &lt;&amp;pio 8 3 GPIO_ACTIVE_HIGH&gt;; // PI3</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_dcdc1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ehci0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	mali-supply = &lt;&amp;reg_dcdc2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc0 {</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_cldo3&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+	cd-gpios = &lt;&amp;pio 5 6 GPIO_ACTIVE_LOW&gt;;  /* PF6 */</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ohci0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	vcc-pa-supply = &lt;&amp;reg_cldo3&gt;;</div><div class='add'>+	vcc-pc-supply = &lt;&amp;reg_cldo3&gt;;</div><div class='add'>+	vcc-pe-supply = &lt;&amp;reg_cldo3&gt;;</div><div class='add'>+	vcc-pf-supply = &lt;&amp;reg_cldo3&gt;;</div><div class='add'>+	vcc-pg-supply = &lt;&amp;reg_aldo4&gt;;</div><div class='add'>+	vcc-ph-supply = &lt;&amp;reg_cldo3&gt;;</div><div class='add'>+	vcc-pi-supply = &lt;&amp;reg_cldo3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;r_i2c {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	axp717: pmic@34 {</div><div class='add'>+		compatible = "x-powers,axp717";</div><div class='add'>+		reg = &lt;0x34&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;nmi_intc&gt;;</div><div class='add'>+		interrupts = &lt;0 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		vin1-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vin2-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vin3-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vin4-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+</div><div class='add'>+		axp_adc: adc {</div><div class='add'>+			compatible = "x-powers,axp717-adc";</div><div class='add'>+			#io-channel-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		battery_power: battery-power {</div><div class='add'>+			compatible = "x-powers,axp717-battery-power-supply";</div><div class='add'>+			monitored-battery = &lt;&amp;battery&gt;;</div><div class='add'>+			x-powers,no-thermistor;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			reg_dcdc1: dcdc1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1160000&gt;;</div><div class='add'>+				regulator-name = "vdd-cpu";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_dcdc2: dcdc2 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;940000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;940000&gt;;</div><div class='add'>+				regulator-name = "vdd-gpu-sys";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_dcdc3: dcdc3 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-name = "vdd-dram";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_aldo1: aldo1 {</div><div class='add'>+				/* 1.8v - unused */</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_aldo2: aldo2 {</div><div class='add'>+				/* 1.8v - unused */</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_aldo3: aldo3 {</div><div class='add'>+				/* 1.8v - unused */</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_aldo4: aldo4 {</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "avcc";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_bldo1: bldo1 {</div><div class='add'>+				/* 1.8v - unused */</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_bldo2: bldo2 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "vcc-pll";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_bldo3: bldo3 {</div><div class='add'>+				/* 2.8v - unused */</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_bldo4: bldo4 {</div><div class='add'>+				/* 1.2v - unused */</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_cldo1: cldo1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "vcc-spkr-amp";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_cldo2: cldo2 {</div><div class='add'>+				/* 3.3v - unused */</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_cldo3: cldo3 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "vcc-io";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_cldo4: cldo4 {</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "vcc-wifi";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_boost: boost {</div><div class='add'>+				regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;5200000&gt;;</div><div class='add'>+				regulator-name = "boost";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/*</div><div class='add'>+			 * Regulator function is unknown, but reading</div><div class='add'>+			 * GPIO values in bootloader is inconsistent</div><div class='add'>+			 * on reboot if this is disabled. Setting to</div><div class='add'>+			 * default value from regulator OTP mem.</div><div class='add'>+			 */</div><div class='add'>+			reg_cpusldo: cpusldo {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;900000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_power: usb-power {</div><div class='add'>+			compatible = "x-powers,axp717-usb-power-supply";</div><div class='add'>+			input-current-limit-microamp = &lt;1500000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart0_ph_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* the AXP717 has USB type-C role switch functionality, not yet described by the binding */</div><div class='add'>+&amp;usbotg {</div><div class='add'>+	dr_mode = "peripheral";   /* USB type-C receptable */</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbphy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-h.dts b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-h.dts<br/>new file mode 100644<br/>index 000000000000..bef4d107482f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-h.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-h.dts</a></div><div class='hunk'>@@ -0,0 +1,138 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2024 Ryan Walklin &lt;ryan@testtoast.com&gt;.</div><div class='add'>+ * Copyright (C) 2024 Chris Morgan &lt;macroalpha82@gmail.com&gt;.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "sun50i-h700-anbernic-rg35xx-plus.dts"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Anbernic RG35XX H";</div><div class='add'>+	compatible = "anbernic,rg35xx-h", "allwinner,sun50i-h700";</div><div class='add'>+</div><div class='add'>+	adc-joystick {</div><div class='add'>+		compatible = "adc-joystick";</div><div class='add'>+		io-channels = &lt;&amp;adc_mux 0&gt;,</div><div class='add'>+			      &lt;&amp;adc_mux 1&gt;,</div><div class='add'>+			      &lt;&amp;adc_mux 2&gt;,</div><div class='add'>+			      &lt;&amp;adc_mux 3&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;joy_mux_pin&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		poll-interval = &lt;60&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		axis@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			abs-flat = &lt;32&gt;;</div><div class='add'>+			abs-fuzz = &lt;32&gt;;</div><div class='add'>+			abs-range = &lt;4096 0&gt;;</div><div class='add'>+			linux,code = &lt;ABS_X&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		axis@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			abs-flat = &lt;32&gt;;</div><div class='add'>+			abs-fuzz = &lt;32&gt;;</div><div class='add'>+			abs-range = &lt;0 4096&gt;;</div><div class='add'>+			linux,code = &lt;ABS_Y&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		axis@2 {</div><div class='add'>+			reg = &lt;2&gt;;</div><div class='add'>+			abs-flat = &lt;32&gt;;</div><div class='add'>+			abs-fuzz = &lt;32&gt;;</div><div class='add'>+			abs-range = &lt;0 4096&gt;;</div><div class='add'>+			linux,code = &lt;ABS_RX&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		axis@3 {</div><div class='add'>+			reg = &lt;3&gt;;</div><div class='add'>+			abs-flat = &lt;32&gt;;</div><div class='add'>+			abs-fuzz = &lt;32&gt;;</div><div class='add'>+			abs-range = &lt;4096 0&gt;;</div><div class='add'>+			linux,code = &lt;ABS_RY&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	adc_mux: adc-mux {</div><div class='add'>+		compatible = "io-channel-mux";</div><div class='add'>+		channels = "left_x", "left_y", "right_x", "right_y";</div><div class='add'>+		#io-channel-cells = &lt;1&gt;;</div><div class='add'>+		io-channels = &lt;&amp;gpadc 0&gt;;</div><div class='add'>+		io-channel-names = "parent";</div><div class='add'>+		mux-controls = &lt;&amp;gpio_mux&gt;;</div><div class='add'>+		settle-time-us = &lt;100&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio_mux: mux-controller {</div><div class='add'>+		compatible = "gpio-mux";</div><div class='add'>+		mux-gpios = &lt;&amp;pio 8 1 GPIO_ACTIVE_LOW&gt;,</div><div class='add'>+			    &lt;&amp;pio 8 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		#mux-control-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc3v8_usb: regulator-vcc3v8-usb {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;pio 4 5 GPIO_ACTIVE_HIGH&gt;; /* PE5 */</div><div class='add'>+		regulator-min-microvolt = &lt;3800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3800000&gt;;</div><div class='add'>+		regulator-name = "vcc3v8-usb";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc5v0_usb: regulator-vcc5v0-usb {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;pio 8 7 GPIO_ACTIVE_HIGH&gt;; /* PI7 */</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-name = "vcc5v0-usb";</div><div class='add'>+		vin-supply = &lt;&amp;reg_vcc3v8_usb&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpadc {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	channel@0 {</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio_keys_gamepad {</div><div class='add'>+	button-thumbl {</div><div class='add'>+		label = "GPIO Thumb Left";</div><div class='add'>+		gpios = &lt;&amp;pio 4 8 GPIO_ACTIVE_LOW&gt;; /* PE8 */</div><div class='add'>+		linux,input-type = &lt;EV_KEY&gt;;</div><div class='add'>+		linux,code = &lt;BTN_THUMBL&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	button-thumbr {</div><div class='add'>+		label = "GPIO Thumb Right";</div><div class='add'>+		gpios = &lt;&amp;pio 4 9 GPIO_ACTIVE_LOW&gt;; /* PE9 */</div><div class='add'>+		linux,input-type = &lt;EV_KEY&gt;;</div><div class='add'>+		linux,code = &lt;BTN_THUMBR&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ehci1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ohci1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	joy_mux_pin: joy-mux-pin {</div><div class='add'>+		pins = "PI0";</div><div class='add'>+		function = "gpio_out";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbphy {</div><div class='add'>+	usb1_vbus-supply = &lt;&amp;reg_vcc5v0_usb&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-plus.dts<br/>new file mode 100644<br/>index 000000000000..60a8e4922103<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-plus.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-plus.dts</a></div><div class='hunk'>@@ -0,0 +1,53 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2024 Ryan Walklin &lt;ryan@testtoast.com&gt;.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "sun50i-h700-anbernic-rg35xx-2024.dts"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Anbernic RG35XX Plus";</div><div class='add'>+	compatible = "anbernic,rg35xx-plus", "allwinner,sun50i-h700";</div><div class='add'>+</div><div class='add'>+	wifi_pwrseq: pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-simple";</div><div class='add'>+		clocks = &lt;&amp;rtc CLK_OSC32K_FANOUT&gt;;</div><div class='add'>+		clock-names = "ext_clock";</div><div class='add'>+		pinctrl-0 = &lt;&amp;x32clk_fanout_pin&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		post-power-on-delay-ms = &lt;200&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pio 6 18 GPIO_ACTIVE_LOW&gt;; /* PG18 */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SDIO WiFi RTL8821CS */</div><div class='add'>+&amp;mmc1 {</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_cldo4&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_aldo4&gt;;</div><div class='add'>+	mmc-pwrseq = &lt;&amp;wifi_pwrseq&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	sdio_wifi: wifi@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;pio&gt;;</div><div class='add'>+		interrupts = &lt;6 15 IRQ_TYPE_LEVEL_LOW&gt;; /* PG15 */</div><div class='add'>+		interrupt-names = "host-wake";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Bluetooth RTL8821CS */</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart1_pins&gt;, &lt;&amp;uart1_rts_cts_pins&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "realtek,rtl8821cs-bt", "realtek,rtl8723bs-bt";</div><div class='add'>+		device-wake-gpios = &lt;&amp;pio 6 17 GPIO_ACTIVE_HIGH&gt;; /* PG17 */</div><div class='add'>+		enable-gpios = &lt;&amp;pio 6 19 GPIO_ACTIVE_HIGH&gt;; /* PG19 */</div><div class='add'>+		host-wake-gpios = &lt;&amp;pio 6 16 GPIO_ACTIVE_HIGH&gt;; /* PG16 */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-sp.dts b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-sp.dts<br/>new file mode 100644<br/>index 000000000000..0cf16dc903cd<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-sp.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-sp.dts</a></div><div class='hunk'>@@ -0,0 +1,34 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2024 Ryan Walklin &lt;ryan@testtoast.com&gt;.</div><div class='add'>+ * Copyright (C) 2024 Chris Morgan &lt;macroalpha82@gmail.com&gt;.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/input/gpio-keys.h&gt;</div><div class='add'>+#include "sun50i-h700-anbernic-rg35xx-plus.dts"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Anbernic RG35XX SP";</div><div class='add'>+	compatible = "anbernic,rg35xx-sp", "allwinner,sun50i-h700";</div><div class='add'>+</div><div class='add'>+	gpio-keys-lid {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		lid-switch {</div><div class='add'>+			label = "Lid Switch";</div><div class='add'>+			gpios = &lt;&amp;pio 4 7 GPIO_ACTIVE_LOW&gt;; /* PE7 */</div><div class='add'>+			linux,can-disable;</div><div class='add'>+			linux,code = &lt;SW_LID&gt;;</div><div class='add'>+			linux,input-type = &lt;EV_SW&gt;;</div><div class='add'>+			wakeup-event-action = &lt;EV_ACT_DEASSERTED&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;r_i2c {</div><div class='add'>+	rtc_ext: rtc@51 {</div><div class='add'>+		compatible = "nxp,pcf8563";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi<br/>new file mode 100644<br/>index 000000000000..42dab01e3f56<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi</a></div><div class='hunk'>@@ -0,0 +1,939 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-only OR MIT)</div><div class='add'>+// Copyright (C) 2023-2024 Arm Ltd.</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/sun6i-rtc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/sun55i-a523-ccu.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/sun55i-a523-mcu-ccu.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/sun55i-a523-r-ccu.h&gt;</div><div class='add'>+#include &lt;dt-bindings/reset/sun55i-a523-ccu.h&gt;</div><div class='add'>+#include &lt;dt-bindings/reset/sun55i-a523-mcu-ccu.h&gt;</div><div class='add'>+#include &lt;dt-bindings/reset/sun55i-a523-r-ccu.h&gt;</div><div class='add'>+#include &lt;dt-bindings/power/allwinner,sun55i-a523-ppu.h&gt;</div><div class='add'>+#include &lt;dt-bindings/power/allwinner,sun55i-a523-pck-600.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x000&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@100 {</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x100&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@200 {</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x200&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@300 {</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x300&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu4: cpu@400 {</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x400&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu5: cpu@500 {</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x500&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu6: cpu@600 {</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x600&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu7: cpu@700 {</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x700&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	osc24M: osc24M-clk {</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+		clock-output-names = "osc24M";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu {</div><div class='add'>+		compatible = "arm,cortex-a55-pmu";</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-0.2";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		arm,no-tick-in-suspend;</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges = &lt;0x0 0x0 0x0 0x40000000&gt;;</div><div class='add'>+</div><div class='add'>+		gpu: gpu@1800000 {</div><div class='add'>+			compatible = "allwinner,sun55i-a523-mali",</div><div class='add'>+				     "arm,mali-valhall-jm";</div><div class='add'>+			reg = &lt;0x1800000 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "job", "mmu", "gpu";</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_GPU&gt;, &lt;&amp;ccu CLK_BUS_GPU&gt;;</div><div class='add'>+			clock-names = "core", "bus";</div><div class='add'>+			power-domains = &lt;&amp;pck600 PD_GPU&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_GPU&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pio: pinctrl@2000000 {</div><div class='add'>+			compatible = "allwinner,sun55i-a523-pinctrl";</div><div class='add'>+			reg = &lt;0x2000000 0x800&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_APB1&gt;, &lt;&amp;osc24M&gt;, &lt;&amp;rtc CLK_OSC32K&gt;;</div><div class='add'>+			clock-names = "apb", "hosc", "losc";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;3&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+			/omit-if-no-ref/</div><div class='add'>+			i2s2_pi_pins: i2s2-pi-pins {</div><div class='add'>+				pins = "PI2", "PI3", "PI4", "PI5";</div><div class='add'>+				allwinner,pinmux = &lt;5&gt;;</div><div class='add'>+				function = "i2s2";</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mmc0_pins: mmc0-pins {</div><div class='add'>+				pins = "PF0" ,"PF1", "PF2", "PF3", "PF4", "PF5";</div><div class='add'>+				allwinner,pinmux = &lt;2&gt;;</div><div class='add'>+				function = "mmc0";</div><div class='add'>+				drive-strength = &lt;30&gt;;</div><div class='add'>+				bias-pull-up;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/omit-if-no-ref/</div><div class='add'>+			mmc1_pins: mmc1-pins {</div><div class='add'>+				pins = "PG0" ,"PG1", "PG2", "PG3", "PG4", "PG5";</div><div class='add'>+				allwinner,pinmux = &lt;2&gt;;</div><div class='add'>+				function = "mmc1";</div><div class='add'>+				drive-strength = &lt;30&gt;;</div><div class='add'>+				bias-pull-up;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mmc2_pins: mmc2-pins {</div><div class='add'>+				pins = "PC0", "PC1" ,"PC5", "PC6", "PC8",</div><div class='add'>+				       "PC9", "PC10", "PC11", "PC13", "PC14",</div><div class='add'>+				       "PC15", "PC16";</div><div class='add'>+				allwinner,pinmux = &lt;3&gt;;</div><div class='add'>+				function = "mmc2";</div><div class='add'>+				drive-strength = &lt;30&gt;;</div><div class='add'>+				bias-pull-up;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			rgmii0_pins: rgmii0-pins {</div><div class='add'>+				pins = "PH0", "PH1", "PH2", "PH3", "PH4",</div><div class='add'>+				       "PH5", "PH6", "PH7", "PH9", "PH10",</div><div class='add'>+				       "PH14", "PH15", "PH16", "PH17", "PH18";</div><div class='add'>+				allwinner,pinmux = &lt;5&gt;;</div><div class='add'>+				function = "gmac0";</div><div class='add'>+				drive-strength = &lt;40&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			rgmii1_pins: rgmii1-pins {</div><div class='add'>+				pins = "PJ0", "PJ1", "PJ2", "PJ3", "PJ4",</div><div class='add'>+				       "PJ5", "PJ6", "PJ7", "PJ8", "PJ9",</div><div class='add'>+				       "PJ11", "PJ12", "PJ13", "PJ14", "PJ15";</div><div class='add'>+				allwinner,pinmux = &lt;5&gt;;</div><div class='add'>+				function = "gmac1";</div><div class='add'>+				drive-strength = &lt;40&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/omit-if-no-ref/</div><div class='add'>+			spdif_out_pb_pin: spdif-pb-pin {</div><div class='add'>+				pins = "PB8";</div><div class='add'>+				function = "spdif";</div><div class='add'>+				allwinner,pinmux = &lt;2&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/omit-if-no-ref/</div><div class='add'>+			spdif_out_pi_pin: spdif-pi-pin {</div><div class='add'>+				pins = "PI10";</div><div class='add'>+				function = "spdif";</div><div class='add'>+				allwinner,pinmux = &lt;2&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart0_pb_pins: uart0-pb-pins {</div><div class='add'>+				pins = "PB9", "PB10";</div><div class='add'>+				allwinner,pinmux = &lt;2&gt;;</div><div class='add'>+				function = "uart0";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/omit-if-no-ref/</div><div class='add'>+			uart1_pins: uart1-pins {</div><div class='add'>+				pins = "PG6", "PG7";</div><div class='add'>+				function = "uart1";</div><div class='add'>+				allwinner,pinmux = &lt;2&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/omit-if-no-ref/</div><div class='add'>+			uart1_rts_cts_pins: uart1-rts-cts-pins {</div><div class='add'>+				pins = "PG8", "PG9";</div><div class='add'>+				function = "uart1";</div><div class='add'>+				allwinner,pinmux = &lt;2&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ccu: clock-controller@2001000 {</div><div class='add'>+			compatible = "allwinner,sun55i-a523-ccu";</div><div class='add'>+			reg = &lt;0x02001000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;osc24M&gt;, &lt;&amp;rtc CLK_OSC32K&gt;,</div><div class='add'>+				 &lt;&amp;rtc CLK_IOSC&gt;, &lt;&amp;rtc CLK_OSC32K_FANOUT&gt;;</div><div class='add'>+			clock-names = "hosc", "losc",</div><div class='add'>+				      "iosc", "losc-fanout";</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wdt: watchdog@2050000 {</div><div class='add'>+			compatible = "allwinner,sun55i-a523-wdt";</div><div class='add'>+			reg = &lt;0x2050000 0x20&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;osc24M&gt;, &lt;&amp;rtc CLK_OSC32K&gt;;</div><div class='add'>+			clock-names = "hosc", "losc";</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart0: serial@2500000 {</div><div class='add'>+			compatible = "snps,dw-apb-uart";</div><div class='add'>+			reg = &lt;0x02500000 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			reg-shift = &lt;2&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_UART0&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_UART0&gt;;</div><div class='add'>+			dmas = &lt;&amp;dma 14&gt;, &lt;&amp;dma 14&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart1: serial@2500400 {</div><div class='add'>+			compatible = "snps,dw-apb-uart";</div><div class='add'>+			reg = &lt;0x02500400 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			reg-shift = &lt;2&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_UART1&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_UART1&gt;;</div><div class='add'>+			dmas = &lt;&amp;dma 15&gt;, &lt;&amp;dma 15&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart2: serial@2500800 {</div><div class='add'>+			compatible = "snps,dw-apb-uart";</div><div class='add'>+			reg = &lt;0x02500800 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			reg-shift = &lt;2&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_UART2&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_UART2&gt;;</div><div class='add'>+			dmas = &lt;&amp;dma 16&gt;, &lt;&amp;dma 16&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart3: serial@2500c00 {</div><div class='add'>+			compatible = "snps,dw-apb-uart";</div><div class='add'>+			reg = &lt;0x02500c00 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			reg-shift = &lt;2&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_UART3&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_UART3&gt;;</div><div class='add'>+			dmas = &lt;&amp;dma 17&gt;, &lt;&amp;dma 17&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart4: serial@2501000 {</div><div class='add'>+			compatible = "snps,dw-apb-uart";</div><div class='add'>+			reg = &lt;0x02501000 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			reg-shift = &lt;2&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_UART4&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_UART4&gt;;</div><div class='add'>+			dmas = &lt;&amp;dma 18&gt;, &lt;&amp;dma 18&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart5: serial@2501400 {</div><div class='add'>+			compatible = "snps,dw-apb-uart";</div><div class='add'>+			reg = &lt;0x02501400 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			reg-shift = &lt;2&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_UART5&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_UART5&gt;;</div><div class='add'>+			dmas = &lt;&amp;dma 19&gt;, &lt;&amp;dma 19&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart6: serial@2501800 {</div><div class='add'>+			compatible = "snps,dw-apb-uart";</div><div class='add'>+			reg = &lt;0x02501800 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			reg-shift = &lt;2&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_UART6&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_UART6&gt;;</div><div class='add'>+			dmas = &lt;&amp;dma 20&gt;, &lt;&amp;dma 20&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart7: serial@2501c00 {</div><div class='add'>+			compatible = "snps,dw-apb-uart";</div><div class='add'>+			reg = &lt;0x02501c00 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			reg-shift = &lt;2&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_UART7&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_UART7&gt;;</div><div class='add'>+			dmas = &lt;&amp;dma 21&gt;, &lt;&amp;dma 21&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c0: i2c@2502000 {</div><div class='add'>+			compatible = "allwinner,sun55i-a523-i2c",</div><div class='add'>+				     "allwinner,sun8i-v536-i2c",</div><div class='add'>+				     "allwinner,sun6i-a31-i2c";</div><div class='add'>+			reg = &lt;0x2502000 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_I2C0&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_I2C0&gt;;</div><div class='add'>+			dmas = &lt;&amp;dma 43&gt;, &lt;&amp;dma 43&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c1: i2c@2502400 {</div><div class='add'>+			compatible = "allwinner,sun55i-a523-i2c",</div><div class='add'>+				     "allwinner,sun8i-v536-i2c",</div><div class='add'>+				     "allwinner,sun6i-a31-i2c";</div><div class='add'>+			reg = &lt;0x2502400 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_I2C1&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_I2C1&gt;;</div><div class='add'>+			dmas = &lt;&amp;dma 44&gt;, &lt;&amp;dma 44&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c2: i2c@2502800 {</div><div class='add'>+			compatible = "allwinner,sun55i-a523-i2c",</div><div class='add'>+				     "allwinner,sun8i-v536-i2c",</div><div class='add'>+				     "allwinner,sun6i-a31-i2c";</div><div class='add'>+			reg = &lt;0x2502800 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_I2C2&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_I2C2&gt;;</div><div class='add'>+			dmas = &lt;&amp;dma 45&gt;, &lt;&amp;dma 45&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c3: i2c@2502c00 {</div><div class='add'>+			compatible = "allwinner,sun55i-a523-i2c",</div><div class='add'>+				     "allwinner,sun8i-v536-i2c",</div><div class='add'>+				     "allwinner,sun6i-a31-i2c";</div><div class='add'>+			reg = &lt;0x2502c00 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_I2C3&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_I2C3&gt;;</div><div class='add'>+			dmas = &lt;&amp;dma 46&gt;, &lt;&amp;dma 46&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c4: i2c@2503000 {</div><div class='add'>+			compatible = "allwinner,sun55i-a523-i2c",</div><div class='add'>+				     "allwinner,sun8i-v536-i2c",</div><div class='add'>+				     "allwinner,sun6i-a31-i2c";</div><div class='add'>+			reg = &lt;0x2503000 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_I2C4&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_I2C4&gt;;</div><div class='add'>+			dmas = &lt;&amp;dma 47&gt;, &lt;&amp;dma 47&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c5: i2c@2503400 {</div><div class='add'>+			compatible = "allwinner,sun55i-a523-i2c",</div><div class='add'>+				     "allwinner,sun8i-v536-i2c",</div><div class='add'>+				     "allwinner,sun6i-a31-i2c";</div><div class='add'>+			reg = &lt;0x2503400 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_I2C5&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_I2C5&gt;;</div><div class='add'>+			dmas = &lt;&amp;dma 48&gt;, &lt;&amp;dma 48&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		syscon: syscon@3000000 {</div><div class='add'>+			compatible = "allwinner,sun55i-a523-system-control",</div><div class='add'>+				     "allwinner,sun50i-a64-system-control";</div><div class='add'>+			reg = &lt;0x03000000 0x1000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dma: dma-controller@3002000 {</div><div class='add'>+			compatible = "allwinner,sun55i-a523-dma",</div><div class='add'>+				     "allwinner,sun50i-a100-dma";</div><div class='add'>+			reg = &lt;0x03002000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_DMA&gt;, &lt;&amp;ccu CLK_MBUS_DMA&gt;;</div><div class='add'>+			clock-names = "bus", "mbus";</div><div class='add'>+			dma-channels = &lt;16&gt;;</div><div class='add'>+			dma-requests = &lt;54&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_DMA&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sid: efuse@3006000 {</div><div class='add'>+			compatible = "allwinner,sun55i-a523-sid",</div><div class='add'>+				     "allwinner,sun50i-a64-sid";</div><div class='add'>+			reg = &lt;0x03006000 0x1000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@3400000 {</div><div class='add'>+			compatible = "arm,gic-v3";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			reg = &lt;0x3400000 0x10000&gt;,</div><div class='add'>+			      &lt;0x3460000 0x100000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			dma-noncoherent;</div><div class='add'>+</div><div class='add'>+			its: msi-controller@3440000 {</div><div class='add'>+				compatible = "arm,gic-v3-its";</div><div class='add'>+				reg = &lt;0x3440000 0x20000&gt;;</div><div class='add'>+				msi-controller;</div><div class='add'>+				#msi-cells = &lt;1&gt;;</div><div class='add'>+				dma-noncoherent;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmc0: mmc@4020000 {</div><div class='add'>+			compatible = "allwinner,sun55i-a523-mmc",</div><div class='add'>+				     "allwinner,sun20i-d1-mmc";</div><div class='add'>+			reg = &lt;0x04020000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_MMC0&gt;, &lt;&amp;ccu CLK_MMC0&gt;;</div><div class='add'>+			clock-names = "ahb", "mmc";</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_MMC0&gt;;</div><div class='add'>+			reset-names = "ahb";</div><div class='add'>+			interrupts = &lt;GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;mmc0_pins&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			max-frequency = &lt;150000000&gt;;</div><div class='add'>+			cap-sd-highspeed;</div><div class='add'>+			cap-mmc-highspeed;</div><div class='add'>+			cap-sdio-irq;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmc1: mmc@4021000 {</div><div class='add'>+			compatible = "allwinner,sun55i-a523-mmc",</div><div class='add'>+				     "allwinner,sun20i-d1-mmc";</div><div class='add'>+			reg = &lt;0x04021000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_MMC1&gt;, &lt;&amp;ccu CLK_MMC1&gt;;</div><div class='add'>+			clock-names = "ahb", "mmc";</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_MMC1&gt;;</div><div class='add'>+			reset-names = "ahb";</div><div class='add'>+			interrupts = &lt;GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;mmc1_pins&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			max-frequency = &lt;150000000&gt;;</div><div class='add'>+			cap-sd-highspeed;</div><div class='add'>+			cap-mmc-highspeed;</div><div class='add'>+			cap-sdio-irq;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmc2: mmc@4022000 {</div><div class='add'>+			compatible = "allwinner,sun55i-a523-mmc",</div><div class='add'>+				     "allwinner,sun20i-d1-mmc";</div><div class='add'>+			reg = &lt;0x04022000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_MMC2&gt;, &lt;&amp;ccu CLK_MMC2&gt;;</div><div class='add'>+			clock-names = "ahb", "mmc";</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_MMC2&gt;;</div><div class='add'>+			reset-names = "ahb";</div><div class='add'>+			interrupts = &lt;GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;mmc2_pins&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			max-frequency = &lt;150000000&gt;;</div><div class='add'>+			cap-sd-highspeed;</div><div class='add'>+			cap-mmc-highspeed;</div><div class='add'>+			cap-sdio-irq;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_otg: usb@4100000 {</div><div class='add'>+			compatible = "allwinner,sun55i-a523-musb",</div><div class='add'>+				     "allwinner,sun8i-a33-musb";</div><div class='add'>+			reg = &lt;0x4100000 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "mc";</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_OTG&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_OTG&gt;;</div><div class='add'>+			extcon = &lt;&amp;usbphy 0&gt;;</div><div class='add'>+			phys = &lt;&amp;usbphy 0&gt;;</div><div class='add'>+			phy-names = "usb";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usbphy: phy@4100400 {</div><div class='add'>+			compatible = "allwinner,sun55i-a523-usb-phy",</div><div class='add'>+				     "allwinner,sun20i-d1-usb-phy";</div><div class='add'>+			reg = &lt;0x4100400 0x100&gt;,</div><div class='add'>+			      &lt;0x4101800 0x100&gt;,</div><div class='add'>+			      &lt;0x4200800 0x100&gt;;</div><div class='add'>+			reg-names = "phy_ctrl",</div><div class='add'>+				    "pmu0",</div><div class='add'>+				    "pmu1";</div><div class='add'>+			clocks = &lt;&amp;osc24M&gt;,</div><div class='add'>+				 &lt;&amp;osc24M&gt;;</div><div class='add'>+			clock-names = "usb0_phy",</div><div class='add'>+				      "usb1_phy";</div><div class='add'>+			resets = &lt;&amp;ccu RST_USB_PHY0&gt;,</div><div class='add'>+				 &lt;&amp;ccu RST_USB_PHY1&gt;;</div><div class='add'>+			reset-names = "usb0_reset",</div><div class='add'>+				      "usb1_reset";</div><div class='add'>+			status = "disabled";</div><div class='add'>+			#phy-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ehci0: usb@4101000 {</div><div class='add'>+			compatible = "allwinner,sun55i-a523-ehci",</div><div class='add'>+				     "generic-ehci";</div><div class='add'>+			reg = &lt;0x4101000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_OHCI0&gt;,</div><div class='add'>+				 &lt;&amp;ccu CLK_BUS_EHCI0&gt;,</div><div class='add'>+				 &lt;&amp;ccu CLK_USB_OHCI0&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_OHCI0&gt;,</div><div class='add'>+				 &lt;&amp;ccu RST_BUS_EHCI0&gt;;</div><div class='add'>+			phys = &lt;&amp;usbphy 0&gt;;</div><div class='add'>+			phy-names = "usb";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ohci0: usb@4101400 {</div><div class='add'>+			compatible = "allwinner,sun55i-a523-ohci",</div><div class='add'>+				     "generic-ohci";</div><div class='add'>+			reg = &lt;0x4101400 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_OHCI0&gt;,</div><div class='add'>+				 &lt;&amp;ccu CLK_USB_OHCI0&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_OHCI0&gt;;</div><div class='add'>+			phys = &lt;&amp;usbphy 0&gt;;</div><div class='add'>+			phy-names = "usb";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ehci1: usb@4200000 {</div><div class='add'>+			compatible = "allwinner,sun55i-a523-ehci",</div><div class='add'>+				     "generic-ehci";</div><div class='add'>+			reg = &lt;0x4200000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_OHCI1&gt;,</div><div class='add'>+				 &lt;&amp;ccu CLK_BUS_EHCI1&gt;,</div><div class='add'>+				 &lt;&amp;ccu CLK_USB_OHCI1&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_OHCI1&gt;,</div><div class='add'>+				 &lt;&amp;ccu RST_BUS_EHCI1&gt;;</div><div class='add'>+			phys = &lt;&amp;usbphy 1&gt;;</div><div class='add'>+			phy-names = "usb";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ohci1: usb@4200400 {</div><div class='add'>+			compatible = "allwinner,sun55i-a523-ohci",</div><div class='add'>+				     "generic-ohci";</div><div class='add'>+			reg = &lt;0x4200400 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_OHCI1&gt;,</div><div class='add'>+				 &lt;&amp;ccu CLK_USB_OHCI1&gt;;</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_OHCI1&gt;;</div><div class='add'>+			phys = &lt;&amp;usbphy 1&gt;;</div><div class='add'>+			phy-names = "usb";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gmac0: ethernet@4500000 {</div><div class='add'>+			compatible = "allwinner,sun55i-a523-gmac0",</div><div class='add'>+				     "allwinner,sun50i-a64-emac";</div><div class='add'>+			reg = &lt;0x04500000 0x10000&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_EMAC0&gt;;</div><div class='add'>+			clock-names = "stmmaceth";</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_EMAC0&gt;;</div><div class='add'>+			reset-names = "stmmaceth";</div><div class='add'>+			interrupts = &lt;GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "macirq";</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;rgmii0_pins&gt;;</div><div class='add'>+			syscon = &lt;&amp;syscon&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			mdio0: mdio {</div><div class='add'>+				compatible = "snps,dwmac-mdio";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gmac1: ethernet@4510000 {</div><div class='add'>+			compatible = "allwinner,sun55i-a523-gmac200",</div><div class='add'>+				     "snps,dwmac-4.20a";</div><div class='add'>+			reg = &lt;0x04510000 0x10000&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccu CLK_BUS_EMAC1&gt;, &lt;&amp;ccu CLK_MBUS_EMAC1&gt;;</div><div class='add'>+			clock-names = "stmmaceth", "mbus";</div><div class='add'>+			resets = &lt;&amp;ccu RST_BUS_EMAC1&gt;;</div><div class='add'>+			reset-names = "stmmaceth";</div><div class='add'>+			interrupts = &lt;GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "macirq";</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;rgmii1_pins&gt;;</div><div class='add'>+			power-domains = &lt;&amp;pck600 PD_VO1&gt;;</div><div class='add'>+			syscon = &lt;&amp;syscon&gt;;</div><div class='add'>+			snps,fixed-burst;</div><div class='add'>+			snps,axi-config = &lt;&amp;gmac1_stmmac_axi_setup&gt;;</div><div class='add'>+			snps,mtl-rx-config = &lt;&amp;gmac1_mtl_rx_setup&gt;;</div><div class='add'>+			snps,mtl-tx-config = &lt;&amp;gmac1_mtl_tx_setup&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			mdio1: mdio {</div><div class='add'>+				compatible = "snps,dwmac-mdio";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gmac1_mtl_rx_setup: rx-queues-config {</div><div class='add'>+				snps,rx-queues-to-use = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				queue0 {};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gmac1_stmmac_axi_setup: stmmac-axi-config {</div><div class='add'>+				snps,wr_osr_lmt = &lt;0xf&gt;;</div><div class='add'>+				snps,rd_osr_lmt = &lt;0xf&gt;;</div><div class='add'>+				snps,blen = &lt;256 128 64 32 16 8 4&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gmac1_mtl_tx_setup: tx-queues-config {</div><div class='add'>+				snps,tx-queues-to-use = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				queue0 {};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ppu: power-controller@7001400 {</div><div class='add'>+			compatible = "allwinner,sun55i-a523-ppu";</div><div class='add'>+			reg = &lt;0x07001400 0x400&gt;;</div><div class='add'>+			clocks = &lt;&amp;r_ccu CLK_BUS_R_PPU1&gt;;</div><div class='add'>+			resets = &lt;&amp;r_ccu RST_BUS_R_PPU1&gt;;</div><div class='add'>+			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		r_ccu: clock-controller@7010000 {</div><div class='add'>+			compatible = "allwinner,sun55i-a523-r-ccu";</div><div class='add'>+			reg = &lt;0x7010000 0x250&gt;;</div><div class='add'>+			clocks = &lt;&amp;osc24M&gt;,</div><div class='add'>+				 &lt;&amp;rtc CLK_OSC32K&gt;,</div><div class='add'>+				 &lt;&amp;rtc CLK_IOSC&gt;,</div><div class='add'>+				 &lt;&amp;ccu CLK_PLL_PERIPH0_200M&gt;,</div><div class='add'>+				 &lt;&amp;ccu CLK_PLL_AUDIO0_4X&gt;;</div><div class='add'>+			clock-names = "hosc",</div><div class='add'>+				      "losc",</div><div class='add'>+				      "iosc",</div><div class='add'>+				      "pll-periph",</div><div class='add'>+				      "pll-audio";</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+			assigned-clocks = &lt;&amp;r_ccu CLK_R_AHB&gt;, &lt;&amp;r_ccu CLK_R_APB0&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;200000000&gt;, &lt;100000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nmi_intc: interrupt-controller@7010320 {</div><div class='add'>+			compatible = "allwinner,sun55i-a523-nmi";</div><div class='add'>+			reg = &lt;0x07010320 0xc&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		r_pio: pinctrl@7022000 {</div><div class='add'>+			compatible = "allwinner,sun55i-a523-r-pinctrl";</div><div class='add'>+			reg = &lt;0x7022000 0x800&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;r_ccu CLK_R_APB0&gt;,</div><div class='add'>+				 &lt;&amp;osc24M&gt;,</div><div class='add'>+				 &lt;&amp;rtc CLK_OSC32K&gt;;</div><div class='add'>+			clock-names = "apb", "hosc", "losc";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;3&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+			r_i2c_pins: r-i2c-pins {</div><div class='add'>+				pins = "PL0" ,"PL1";</div><div class='add'>+				allwinner,pinmux = &lt;2&gt;;</div><div class='add'>+				function = "r_i2c0";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pck600: power-controller@7060000 {</div><div class='add'>+			compatible = "allwinner,sun55i-a523-pck-600";</div><div class='add'>+			reg = &lt;0x07060000 0x8000&gt;;</div><div class='add'>+			clocks = &lt;&amp;r_ccu CLK_BUS_R_PPU0&gt;;</div><div class='add'>+			resets = &lt;&amp;r_ccu RST_BUS_R_PPU0&gt;;</div><div class='add'>+			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		r_i2c0: i2c@7081400 {</div><div class='add'>+			compatible = "allwinner,sun55i-a523-i2c",</div><div class='add'>+				     "allwinner,sun8i-v536-i2c",</div><div class='add'>+				     "allwinner,sun6i-a31-i2c";</div><div class='add'>+			reg = &lt;0x07081400 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;r_ccu CLK_BUS_R_I2C0&gt;;</div><div class='add'>+			dmas = &lt;&amp;dma 49&gt;, &lt;&amp;dma 49&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+			resets = &lt;&amp;r_ccu RST_BUS_R_I2C0&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;r_i2c_pins&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rtc: rtc@7090000 {</div><div class='add'>+			compatible = "allwinner,sun55i-a523-rtc",</div><div class='add'>+				     "allwinner,sun50i-r329-rtc";</div><div class='add'>+			reg = &lt;0x7090000 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;r_ccu CLK_BUS_R_RTC&gt;,</div><div class='add'>+				 &lt;&amp;osc24M&gt;,</div><div class='add'>+				 &lt;&amp;r_ccu CLK_R_AHB&gt;;</div><div class='add'>+			clock-names = "bus", "hosc", "ahb";</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mcu_ccu: clock-controller@7102000 {</div><div class='add'>+			compatible = "allwinner,sun55i-a523-mcu-ccu";</div><div class='add'>+			reg = &lt;0x7102000 0x200&gt;;</div><div class='add'>+			clocks = &lt;&amp;osc24M&gt;,</div><div class='add'>+				 &lt;&amp;rtc CLK_OSC32K&gt;,</div><div class='add'>+				 &lt;&amp;rtc CLK_IOSC&gt;,</div><div class='add'>+				 &lt;&amp;ccu CLK_PLL_AUDIO0_4X&gt;,</div><div class='add'>+				 &lt;&amp;ccu CLK_PLL_PERIPH0_300M&gt;,</div><div class='add'>+				 &lt;&amp;ccu CLK_DSP&gt;,</div><div class='add'>+				 &lt;&amp;ccu CLK_MBUS&gt;,</div><div class='add'>+				 &lt;&amp;r_ccu CLK_R_AHB&gt;,</div><div class='add'>+				 &lt;&amp;r_ccu CLK_R_APB0&gt;;</div><div class='add'>+			clock-names = "hosc",</div><div class='add'>+				      "losc",</div><div class='add'>+				      "iosc",</div><div class='add'>+				      "pll-audio0-4x",</div><div class='add'>+				      "pll-periph0-300m",</div><div class='add'>+				      "dsp",</div><div class='add'>+				      "mbus",</div><div class='add'>+				      "r-ahb",</div><div class='add'>+				      "r-apb0";</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2s0: i2s@7112000 {</div><div class='add'>+			compatible = "allwinner,sun55i-a523-i2s",</div><div class='add'>+				     "allwinner,sun50i-r329-i2s";</div><div class='add'>+			reg = &lt;0x07112000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;mcu_ccu CLK_BUS_MCU_I2S0&gt;, &lt;&amp;mcu_ccu CLK_MCU_I2S0&gt;;</div><div class='add'>+			clock-names = "apb", "mod";</div><div class='add'>+			resets = &lt;&amp;mcu_ccu RST_BUS_MCU_I2S0&gt;;</div><div class='add'>+			dmas = &lt;&amp;mcu_dma 3&gt;, &lt;&amp;mcu_dma 3&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+			#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2s1: i2s@7113000 {</div><div class='add'>+			compatible = "allwinner,sun55i-a523-i2s",</div><div class='add'>+				     "allwinner,sun50i-r329-i2s";</div><div class='add'>+			reg = &lt;0x07113000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;mcu_ccu CLK_BUS_MCU_I2S1&gt;, &lt;&amp;mcu_ccu CLK_MCU_I2S1&gt;;</div><div class='add'>+			clock-names = "apb", "mod";</div><div class='add'>+			resets = &lt;&amp;mcu_ccu RST_BUS_MCU_I2S1&gt;;</div><div class='add'>+			dmas = &lt;&amp;mcu_dma 4&gt;, &lt;&amp;mcu_dma 4&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+			#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2s2: i2s@7114000 {</div><div class='add'>+			compatible = "allwinner,sun55i-a523-i2s",</div><div class='add'>+				     "allwinner,sun50i-r329-i2s";</div><div class='add'>+			reg = &lt;0x07114000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;mcu_ccu CLK_BUS_MCU_I2S2&gt;, &lt;&amp;mcu_ccu CLK_MCU_I2S2&gt;;</div><div class='add'>+			clock-names = "apb", "mod";</div><div class='add'>+			resets = &lt;&amp;mcu_ccu RST_BUS_MCU_I2S2&gt;;</div><div class='add'>+			dmas = &lt;&amp;mcu_dma 5&gt;, &lt;&amp;mcu_dma 5&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+			#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2s3: i2s@7115000 {</div><div class='add'>+			compatible = "allwinner,sun55i-a523-i2s",</div><div class='add'>+				     "allwinner,sun50i-r329-i2s";</div><div class='add'>+			reg = &lt;0x07115000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;mcu_ccu CLK_BUS_MCU_I2S3&gt;, &lt;&amp;mcu_ccu CLK_MCU_I2S3&gt;;</div><div class='add'>+			clock-names = "apb", "mod";</div><div class='add'>+			resets = &lt;&amp;mcu_ccu RST_BUS_MCU_I2S3&gt;;</div><div class='add'>+			dmas = &lt;&amp;mcu_dma 6&gt;, &lt;&amp;mcu_dma 6&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+			#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spdif: spdif@7116000 {</div><div class='add'>+			compatible = "allwinner,sun55i-a523-spdif";</div><div class='add'>+			reg = &lt;0x07116000 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;mcu_ccu CLK_BUS_MCU_SPDIF&gt;,</div><div class='add'>+				 &lt;&amp;mcu_ccu CLK_MCU_SPDIF_TX&gt;,</div><div class='add'>+				 &lt;&amp;mcu_ccu CLK_MCU_SPDIF_RX&gt;;</div><div class='add'>+			clock-names = "apb", "tx", "rx";</div><div class='add'>+			resets = &lt;&amp;mcu_ccu RST_BUS_MCU_SPDIF&gt;;</div><div class='add'>+			dmas = &lt;&amp;mcu_dma 2&gt;, &lt;&amp;mcu_dma 2&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+			#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mcu_dma: dma-controller@7121000 {</div><div class='add'>+			compatible = "allwinner,sun55i-a523-mcu-dma",</div><div class='add'>+				     "allwinner,sun50i-a100-dma";</div><div class='add'>+			reg = &lt;0x07121000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;mcu_ccu CLK_BUS_MCU_DMA&gt;, &lt;&amp;mcu_ccu CLK_MCU_MBUS_DMA&gt;;</div><div class='add'>+			clock-names = "bus", "mbus";</div><div class='add'>+			dma-channels = &lt;16&gt;;</div><div class='add'>+			dma-requests = &lt;15&gt;;</div><div class='add'>+			resets = &lt;&amp;mcu_ccu RST_BUS_MCU_DMA&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		npu: npu@7122000 {</div><div class='add'>+			compatible = "vivante,gc";</div><div class='add'>+			reg = &lt;0x07122000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;mcu_ccu CLK_BUS_MCU_NPU_ACLK&gt;,</div><div class='add'>+				 &lt;&amp;ccu CLK_NPU&gt;,</div><div class='add'>+				 &lt;&amp;mcu_ccu CLK_BUS_MCU_NPU_HCLK&gt;;</div><div class='add'>+			clock-names = "bus", "core", "reg";</div><div class='add'>+			resets = &lt;&amp;mcu_ccu RST_BUS_MCU_NPU&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ppu PD_NPU&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts<br/>new file mode 100644<br/>index 000000000000..bfdf1728cd14<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts</a></div><div class='hunk'>@@ -0,0 +1,383 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-only OR MIT)</div><div class='add'>+// Copyright (C) 2025 Arm Ltd.</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "sun55i-a523.dtsi"</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Radxa Cubie A5E";</div><div class='add'>+	compatible = "radxa,cubie-a5e", "allwinner,sun55i-a527";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;gmac0;</div><div class='add'>+		ethernet1 = &amp;gmac1;</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		power-led {</div><div class='add'>+			function = LED_FUNCTION_POWER;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			gpios = &lt;&amp;r_pio 0 4 GPIO_ACTIVE_LOW&gt;; /* PL4 */</div><div class='add'>+			default-state = "on";</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		use-led {</div><div class='add'>+			function = LED_FUNCTION_ACTIVITY;</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			gpios = &lt;&amp;r_pio 0 5 GPIO_ACTIVE_LOW&gt;; /* PL5 */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	iio-hwmon {</div><div class='add'>+		compatible = "iio-hwmon";</div><div class='add'>+		io-channels = &lt;&amp;axp717_adc 3&gt;, /* vsys_v */</div><div class='add'>+			      &lt;&amp;axp717_adc 4&gt;; /* pmic_temp */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc5v: vcc5v {</div><div class='add'>+		/* board wide 5V supply from the USB-C connector */</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vcc-5v";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb_vbus: vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "usb-vbus";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		gpio = &lt;&amp;r_pio 0 8 GPIO_ACTIVE_HIGH&gt;;	/* PL8 */</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ehci0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ehci1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gmac0 {</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ext_rgmii0_phy&gt;;</div><div class='add'>+	phy-supply = &lt;&amp;reg_cldo3&gt;;</div><div class='add'>+</div><div class='add'>+	allwinner,tx-delay-ps = &lt;300&gt;;</div><div class='add'>+	allwinner,rx-delay-ps = &lt;400&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gmac1 {</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ext_rgmii1_phy&gt;;</div><div class='add'>+	phy-supply = &lt;&amp;reg_cldo4&gt;;</div><div class='add'>+</div><div class='add'>+	tx-internal-delay-ps = &lt;300&gt;;</div><div class='add'>+	rx-internal-delay-ps = &lt;400&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	mali-supply = &lt;&amp;reg_dcdc2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdio0 {</div><div class='add'>+	ext_rgmii0_phy: ethernet-phy@1 {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pio 7 8 GPIO_ACTIVE_LOW&gt;; /* PH8 */</div><div class='add'>+		reset-assert-us = &lt;10000&gt;;</div><div class='add'>+		reset-deassert-us = &lt;150000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdio1 {</div><div class='add'>+	ext_rgmii1_phy: ethernet-phy@1 {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pio 9 16 GPIO_ACTIVE_LOW&gt;; /* PJ16 */</div><div class='add'>+		reset-assert-us = &lt;10000&gt;;</div><div class='add'>+		reset-deassert-us = &lt;150000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc0 {</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_cldo3&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)&gt;; /* PF6 */</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ohci0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ohci1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	vcc-pb-supply = &lt;&amp;reg_cldo3&gt;;	/* via VCC-IO */</div><div class='add'>+	vcc-pc-supply = &lt;&amp;reg_cldo1&gt;;</div><div class='add'>+	vcc-pd-supply = &lt;&amp;reg_cldo3&gt;;</div><div class='add'>+	vcc-pe-supply = &lt;&amp;reg_aldo2&gt;;</div><div class='add'>+	vcc-pf-supply = &lt;&amp;reg_cldo3&gt;;	/* actually switchable */</div><div class='add'>+	vcc-pg-supply = &lt;&amp;reg_bldo1&gt;;</div><div class='add'>+	vcc-ph-supply = &lt;&amp;reg_cldo3&gt;;	/* via VCC-IO */</div><div class='add'>+	vcc-pi-supply = &lt;&amp;reg_cldo3&gt;;</div><div class='add'>+	vcc-pj-supply = &lt;&amp;reg_cldo4&gt;;</div><div class='add'>+	vcc-pk-supply = &lt;&amp;reg_cldo1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;r_i2c0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	axp717: pmic@34 {</div><div class='add'>+		compatible = "x-powers,axp717";</div><div class='add'>+		reg = &lt;0x34&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;nmi_intc&gt;;</div><div class='add'>+		interrupts = &lt;0 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		vin1-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vin2-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vin3-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vin4-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		aldoin-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		bldoin-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		cldoin-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+</div><div class='add'>+		axp717_adc: adc {</div><div class='add'>+			compatible = "x-powers,axp717-adc";</div><div class='add'>+			#io-channel-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		battery-power {</div><div class='add'>+			compatible = "x-powers,axp717-battery-power-supply";</div><div class='add'>+			/* charger mode design but has no battery terminal */</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			/* Supplies the "little" cluster (1.4 GHz cores) */</div><div class='add'>+			reg_dcdc1: dcdc1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1160000&gt;;</div><div class='add'>+				regulator-name = "vdd-cpul";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_dcdc2: dcdc2 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;920000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;920000&gt;;</div><div class='add'>+				regulator-name = "vdd-gpu-sys";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_dcdc3: dcdc3 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-name = "vdd-dram";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_aldo1: aldo1 {</div><div class='add'>+				/* not connected */</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_aldo2: aldo2 {</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "vcc-pe";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_aldo3: aldo3 {</div><div class='add'>+				/* supplies the I2C pins for this PMIC */</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "vcc-pl-usb";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_aldo4: aldo4 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "vcc-pll-dxco-avcc";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_bldo1: bldo1 {</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "vcc-pg-iowifi";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_bldo2: bldo2 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "vcc-pm-lpddr4";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_bldo3: bldo3 {</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "vcc-mipi-cam";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_bldo4: bldo4 {</div><div class='add'>+				/* not connected */</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_cldo1: cldo1 {</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "vcc-pc-and-their-dog";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_cldo2: cldo2 {</div><div class='add'>+				/* not connected */</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_cldo3: cldo3 {</div><div class='add'>+				/* IO, USB-2, 3V3, card, NAND, sensor, PI */</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "vcc-io-mmc-spi-ana";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_cldo4: cldo4 {</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "vcc-pj-phy";</div><div class='add'>+				/* enough time for the PHY to fully power on */</div><div class='add'>+				regulator-enable-ramp-delay = &lt;150000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_cpusldo: cpusldo {</div><div class='add'>+				/* supplies the management core */</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-name = "vdd-cpus";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb-power {</div><div class='add'>+			compatible = "x-powers,axp717-usb-power-supply";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	axp323: pmic@36 {</div><div class='add'>+		compatible = "x-powers,axp323";</div><div class='add'>+		reg = &lt;0x36&gt;;</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		interrupt-parent = &lt;&amp;nmi_intc&gt;;</div><div class='add'>+		interrupts = &lt;0 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+</div><div class='add'>+		vin1-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vin2-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vin3-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			aldo1 {</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "vcc-mipi-dsi";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			dldo1 {</div><div class='add'>+				/* not connected */</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* Supplies the "big" cluster (1.8 GHz cores) */</div><div class='add'>+			reg_dcdc1_323: dcdc1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1160000&gt;;</div><div class='add'>+				regulator-name = "vdd-cpub";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* DCDC2 is polyphased with DCDC1 */</div><div class='add'>+</div><div class='add'>+			/* RISC-V management core supply */</div><div class='add'>+			reg_dcdc3_323: dcdc3 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-name = "vdd-dnr";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;r_pio {</div><div class='add'>+/*</div><div class='add'>+ * Specifying the supply would create a circular dependency.</div><div class='add'>+ *</div><div class='add'>+ *	vcc-pl-supply = &lt;&amp;reg_aldo3&gt;;</div><div class='add'>+ */</div><div class='add'>+	vcc-pm-supply = &lt;&amp;reg_aldo3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart0_pb_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_otg {</div><div class='add'>+	/*</div><div class='add'>+	 * The USB-C port is the primary power supply, so in this configuration</div><div class='add'>+	 * relies on the other end of the USB cable to supply the VBUS power.</div><div class='add'>+	 * So use this port in peripheral mode.</div><div class='add'>+	 * It is possible to supply the board with the 5V pins on the GPIO</div><div class='add'>+	 * header, and since the DCIN_5V line is hardwired to the USB-C VBUS</div><div class='add'>+	 * pins, the port turns into a host port, unconditionally supplying</div><div class='add'>+	 * power. The dr_mode property should be changed to "host" here, if</div><div class='add'>+	 * users choose this setup.</div><div class='add'>+	 */</div><div class='add'>+	dr_mode = "peripheral";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * The schematic describes USB0_ID (PL10), measuring VBUS_5V, which looks to</div><div class='add'>+ * be always on. Also there is USB-VBUSDET (PL2), which is measuring the same</div><div class='add'>+ * VBUS_5V. There is also DCIN_DET, which measures DCIN_5V, so the power</div><div class='add'>+ * input rail.</div><div class='add'>+ * None of them seem to make any sense in relation to detecting USB devices</div><div class='add'>+ * or whether there is power provided via any USB pins: they would always</div><div class='add'>+ * report high, otherwise the system wouldn't be running.</div><div class='add'>+ * The AXP717C provides proper USB-C CC pin functionality, but the PMIC is</div><div class='add'>+ * not connected to those pins of the USB-C connector.</div><div class='add'>+ */</div><div class='add'>+&amp;usbphy {</div><div class='add'>+	usb0_vbus-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+	usb1_vbus-supply = &lt;&amp;reg_usb_vbus&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts b/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts<br/>new file mode 100644<br/>index 000000000000..a96927fbdadd<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts</a></div><div class='hunk'>@@ -0,0 +1,292 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-only OR MIT)</div><div class='add'>+// Copyright (C) 2024 Arm Ltd.</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "sun55i-a523.dtsi"</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "X96Q Pro+";</div><div class='add'>+	compatible = "amediatech,x96q-pro-plus", "allwinner,sun55i-h728";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ext_osc32k: ext-osc32k-clk {</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		clock-frequency = &lt;32768&gt;;</div><div class='add'>+		clock-output-names = "ext_osc32k";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc5v: vcc5v {</div><div class='add'>+		/* board wide 5V supply from the barrel plug */</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vcc-5v";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc3v3: vcc3v3 {</div><div class='add'>+		/* 3.3V dummy supply for the SD card */</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vcc-3v3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ehci0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ehci1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	mali-supply = &lt;&amp;reg_dcdc2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc0 {</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_vcc3v3&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)&gt;; /* PF6 */</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc2 {</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_cldo3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_cldo1&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	cap-mmc-hw-reset;</div><div class='add'>+	mmc-ddr-1_8v;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ohci0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ohci1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	vcc-pb-supply = &lt;&amp;reg_cldo3&gt;;	/* via VCC-IO */</div><div class='add'>+	vcc-pc-supply = &lt;&amp;reg_cldo1&gt;;</div><div class='add'>+	vcc-pd-supply = &lt;&amp;reg_dcdc4&gt;;</div><div class='add'>+	vcc-pe-supply = &lt;&amp;reg_dcdc4&gt;;</div><div class='add'>+	vcc-pf-supply = &lt;&amp;reg_cldo3&gt;;	/* actually switchable */</div><div class='add'>+	vcc-pg-supply = &lt;&amp;reg_bldo1&gt;;</div><div class='add'>+	vcc-ph-supply = &lt;&amp;reg_cldo3&gt;;	/* via VCC-IO */</div><div class='add'>+	vcc-pi-supply = &lt;&amp;reg_dcdc4&gt;;</div><div class='add'>+	vcc-pj-supply = &lt;&amp;reg_dcdc4&gt;;</div><div class='add'>+	vcc-pk-supply = &lt;&amp;reg_bldo3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;r_i2c0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	axp717: pmic@34 {</div><div class='add'>+		compatible = "x-powers,axp717";</div><div class='add'>+		reg = &lt;0x34&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;nmi_intc&gt;;</div><div class='add'>+		interrupts = &lt;0 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		vin1-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vin2-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vin3-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vin4-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		aldoin-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		bldoin-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		cldoin-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			/* Supplies the "little" cluster (1.0(?) GHz cores) */</div><div class='add'>+			reg_dcdc1: dcdc1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1160000&gt;;</div><div class='add'>+				regulator-name = "vdd-cpul";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_dcdc2: dcdc2 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;920000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;920000&gt;;</div><div class='add'>+				regulator-name = "vdd-gpu-sys";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_dcdc3: dcdc3 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;1360000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1360000&gt;;</div><div class='add'>+				regulator-name = "vdd-dram";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_dcdc4: dcdc4 {</div><div class='add'>+				regulator-min-microvolt = &lt;1000000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+				regulator-name = "vdd-dcdc4";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_aldo1: aldo1 {</div><div class='add'>+				/* not connected */</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_aldo2: aldo2 {</div><div class='add'>+				/* not connected */</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_aldo3: aldo3 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "vcc-aldo3";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_aldo4: aldo4 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "vcc-pll-dxco-avcc";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_bldo1: bldo1 {</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "vcc-pg-wifi-lvds";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_bldo2: bldo2 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "vcc-dram-1v8";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_bldo3: bldo3 {</div><div class='add'>+				regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-name = "vcc-bldo3";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_bldo4: bldo4 {</div><div class='add'>+				/* not connected */</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_cldo1: cldo1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "vcc-codec-sd";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_cldo2: cldo2 {</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_cldo3: cldo3 {</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "vcc-codec-eth-sd";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_cldo4: cldo4 {</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "vcc-eth-phy";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_cpusldo: cpusldo {</div><div class='add'>+				/* supplies the management core */</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-name = "vdd-cpus";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	axp323: pmic@36 {</div><div class='add'>+		compatible = "x-powers,axp323";</div><div class='add'>+		reg = &lt;0x36&gt;;</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		interrupt-parent = &lt;&amp;nmi_intc&gt;;</div><div class='add'>+		interrupts = &lt;0 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+</div><div class='add'>+		vin1-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vin2-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vin3-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			aldo1 {</div><div class='add'>+				/* not connected */</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			dldo1 {</div><div class='add'>+				/* not connected */</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* Supplies the "big" cluster (1.8 GHz cores) */</div><div class='add'>+			reg_dcdc1_323: dcdc1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1160000&gt;;</div><div class='add'>+				regulator-name = "vdd-cpub";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* DCDC2 is polyphased with DCDC1 */</div><div class='add'>+</div><div class='add'>+			reg_dcdc3_323: dcdc3 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;1050000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1050000&gt;;</div><div class='add'>+				regulator-name = "vdd-dcdc3";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;r_pio {</div><div class='add'>+/*</div><div class='add'>+ * Specifying the supply would create a circular dependency.</div><div class='add'>+ *</div><div class='add'>+ *	vcc-pl-supply = &lt;&amp;reg_aldo3&gt;;</div><div class='add'>+ */</div><div class='add'>+	vcc-pm-supply = &lt;&amp;reg_aldo3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart0_pb_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_otg {</div><div class='add'>+	/* USB0 is a USB-A receptacle, always powered, so force host mode. */</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbphy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts<br/>new file mode 100644<br/>index 000000000000..054d0357c139<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts</a></div><div class='hunk'>@@ -0,0 +1,388 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-only OR MIT)</div><div class='add'>+// Copyright (C) 2024 Arm Ltd.</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "sun55i-a523.dtsi"</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Avaota A1";</div><div class='add'>+	compatible = "yuzukihd,avaota-a1", "allwinner,sun55i-t527";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;gmac0;</div><div class='add'>+		ethernet1 = &amp;gmac1;</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ext_osc32k: ext-osc32k-clk {</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		clock-frequency = &lt;32768&gt;;</div><div class='add'>+		clock-output-names = "ext_osc32k";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	iio-hwmon {</div><div class='add'>+		compatible = "iio-hwmon";</div><div class='add'>+		io-channels = &lt;&amp;axp717_adc 3&gt;, /* vsys_v */</div><div class='add'>+			      &lt;&amp;axp717_adc 4&gt;; /* pmic_temp */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc12v: vcc12v {</div><div class='add'>+		/* DC input jack */</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vcc-12v";</div><div class='add'>+		regulator-min-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc5v: vcc5v {</div><div class='add'>+		/* board wide 5V supply from the 12V-&gt;5V regulator */</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vcc-5v";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;reg_vcc12v&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb_vbus: vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "usb-vbus";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		gpio = &lt;&amp;pio 8 12 GPIO_ACTIVE_HIGH&gt;;	/* PI12 */</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ehci0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ehci1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gmac0 {</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ext_rgmii0_phy&gt;;</div><div class='add'>+	phy-supply = &lt;&amp;reg_dcdc4&gt;;</div><div class='add'>+</div><div class='add'>+	allwinner,tx-delay-ps = &lt;100&gt;;</div><div class='add'>+	allwinner,rx-delay-ps = &lt;300&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gmac1 {</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ext_rgmii1_phy&gt;;</div><div class='add'>+	phy-supply = &lt;&amp;reg_dcdc4&gt;;</div><div class='add'>+</div><div class='add'>+	tx-internal-delay-ps = &lt;100&gt;;</div><div class='add'>+	rx-internal-delay-ps = &lt;100&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	mali-supply = &lt;&amp;reg_dcdc2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdio0 {</div><div class='add'>+	ext_rgmii0_phy: ethernet-phy@1 {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pio 7 8 GPIO_ACTIVE_LOW&gt;; /* PH8 */</div><div class='add'>+		reset-assert-us = &lt;10000&gt;;</div><div class='add'>+		reset-deassert-us = &lt;150000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdio1 {</div><div class='add'>+	ext_rgmii1_phy: ethernet-phy@1 {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pio 9 16 GPIO_ACTIVE_LOW&gt;; /* PJ16 */</div><div class='add'>+		reset-assert-us = &lt;10000&gt;;</div><div class='add'>+		reset-deassert-us = &lt;150000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc0 {</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_cldo3&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)&gt;; /* PF6 */</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc2 {</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	cap-mmc-hw-reset;</div><div class='add'>+	mmc-ddr-1_8v;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	non-removable;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_cldo3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_cldo1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ohci0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ohci1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	vcc-pb-supply = &lt;&amp;reg_cldo3&gt;;	/* via VCC-IO */</div><div class='add'>+	vcc-pc-supply = &lt;&amp;reg_cldo1&gt;;</div><div class='add'>+	vcc-pd-supply = &lt;&amp;reg_dcdc4&gt;;</div><div class='add'>+	vcc-pe-supply = &lt;&amp;reg_dcdc4&gt;;</div><div class='add'>+	vcc-pf-supply = &lt;&amp;reg_cldo3&gt;;	/* actually switchable */</div><div class='add'>+	vcc-pg-supply = &lt;&amp;reg_bldo1&gt;;</div><div class='add'>+	vcc-ph-supply = &lt;&amp;reg_cldo3&gt;;	/* via VCC-IO */</div><div class='add'>+	vcc-pi-supply = &lt;&amp;reg_dcdc4&gt;;</div><div class='add'>+	vcc-pj-supply = &lt;&amp;reg_dcdc4&gt;;</div><div class='add'>+	vcc-pk-supply = &lt;&amp;reg_bldo3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;r_i2c0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	axp717: pmic@35 {</div><div class='add'>+		compatible = "x-powers,axp717";</div><div class='add'>+		reg = &lt;0x35&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;nmi_intc&gt;;</div><div class='add'>+		interrupts = &lt;0 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		vin1-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vin2-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vin3-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vin4-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		aldoin-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		bldoin-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		cldoin-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+</div><div class='add'>+		axp717_adc: adc {</div><div class='add'>+			compatible = "x-powers,axp717-adc";</div><div class='add'>+			#io-channel-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		battery-power {</div><div class='add'>+			compatible = "x-powers,axp717-battery-power-supply";</div><div class='add'>+			/* no battery; output used for dcdc4 instead */</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			/* Supplies the "little" cluster (1.4 GHz cores) */</div><div class='add'>+			reg_dcdc1: dcdc1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1160000&gt;;</div><div class='add'>+				regulator-name = "vdd-cpul";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_dcdc2: dcdc2 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;920000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;920000&gt;;</div><div class='add'>+				regulator-name = "vdd-gpu-sys";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_dcdc3: dcdc3 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;1160000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1160000&gt;;</div><div class='add'>+				regulator-name = "vdd-dram";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_dcdc4: dcdc4 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "vdd-io";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_aldo1: aldo1 {</div><div class='add'>+				/* not connected */</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_aldo2: aldo2 {</div><div class='add'>+				/* not connected */</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_aldo3: aldo3 {</div><div class='add'>+				/* supplies the I2C pins for this PMIC */</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "vcc-pl-pm";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_aldo4: aldo4 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "vcc-pll-dxco-avcc";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_bldo1: bldo1 {</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "vcc-pg-wifi-lvds";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_bldo2: bldo2 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "vcc-dram-1v8";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_bldo3: bldo3 {</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "vcc-cvp-pk-vid1v8";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_bldo4: bldo4 {</div><div class='add'>+				/* not connected */</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_cldo1: cldo1 {</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "vcc-pc";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_cldo2: cldo2 {</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "vcc-efuse";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_cldo3: cldo3 {</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "vcc-io-mmc-spi-ana";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_cldo4: cldo4 {</div><div class='add'>+				/* not connected */</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_cpusldo: cpusldo {</div><div class='add'>+				/* supplies the management core */</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-name = "vdd-cpus";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb-power {</div><div class='add'>+			compatible = "x-powers,axp717-usb-power-supply";</div><div class='add'>+			/* 12V-5V buck converter can supply up to 5A */</div><div class='add'>+			input-current-limit-microamp = &lt;3250000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	axp323: pmic@36 {</div><div class='add'>+		compatible = "x-powers,axp323";</div><div class='add'>+		reg = &lt;0x36&gt;;</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		interrupt-parent = &lt;&amp;nmi_intc&gt;;</div><div class='add'>+		interrupts = &lt;0 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+</div><div class='add'>+		vin1-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vin2-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vin3-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			aldo1 {</div><div class='add'>+				/* not connected */</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			dldo1 {</div><div class='add'>+				/* not connected */</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* Supplies the "big" cluster (1.8 GHz cores) */</div><div class='add'>+			reg_dcdc1_323: dcdc1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1160000&gt;;</div><div class='add'>+				regulator-name = "vdd-cpub";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* DCDC2 is polyphased with DCDC1 */</div><div class='add'>+</div><div class='add'>+			/* Some RISC-V management core related voltage */</div><div class='add'>+			reg_dcdc3_323: dcdc3 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-name = "vdd-dnr";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;r_pio {</div><div class='add'>+/*</div><div class='add'>+ * Specifying the supply would create a circular dependency.</div><div class='add'>+ *</div><div class='add'>+ *	vcc-pl-supply = &lt;&amp;reg_aldo3&gt;;</div><div class='add'>+ */</div><div class='add'>+	vcc-pm-supply = &lt;&amp;reg_aldo3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;rtc {</div><div class='add'>+	clocks = &lt;&amp;r_ccu CLK_BUS_R_RTC&gt;, &lt;&amp;osc24M&gt;,</div><div class='add'>+		 &lt;&amp;r_ccu CLK_R_AHB&gt;, &lt;&amp;ext_osc32k&gt;;</div><div class='add'>+	clock-names = "bus", "hosc", "ahb", "ext-osc32k";</div><div class='add'>+	assigned-clocks = &lt;&amp;rtc CLK_OSC32K&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;32768&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart0_pb_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_otg {</div><div class='add'>+	 /*</div><div class='add'>+	  * The CC pins of the USB-C port have two pull-down resistors</div><div class='add'>+	  * connected to GND, which fixes this port to a peripheral role.</div><div class='add'>+	  * There is a regulator, controlled by a GPIO, to provide VBUS power</div><div class='add'>+	  * to the port, and a VBUSDET GPIO, to detect externally provided</div><div class='add'>+	  * power, but without the CC pins there is no real way to do a</div><div class='add'>+	  * runtime role detection.</div><div class='add'>+	  */</div><div class='add'>+	dr_mode = "peripheral";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbphy {</div><div class='add'>+	usb0_vbus-supply = &lt;&amp;reg_usb_vbus&gt;;</div><div class='add'>+	usb0_vbus_det-gpios = &lt;&amp;pio 8 13 GPIO_ACTIVE_HIGH&gt;; /* PI13 */</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts<br/>new file mode 100644<br/>index 000000000000..9e6b21cf293e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts</a></div><div class='hunk'>@@ -0,0 +1,444 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-only OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2025 Chen-Yu Tsai &lt;wens@csie.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "sun55i-a523.dtsi"</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "OrangePi 4A";</div><div class='add'>+	compatible = "xunlong,orangepi-4a", "allwinner,sun55i-t527";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;gmac1;</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ext_osc32k: ext-osc32k-clk {</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		clock-frequency = &lt;32768&gt;;</div><div class='add'>+		clock-output-names = "ext_osc32k";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		/* PWM capable pin, but PWM isn't supported yet. */</div><div class='add'>+		led {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			gpios = &lt;&amp;pio 3 20 GPIO_ACTIVE_HIGH&gt;; /* PD20 */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	iio-hwmon {</div><div class='add'>+		compatible = "iio-hwmon";</div><div class='add'>+		io-channels = &lt;&amp;axp717_adc 3&gt;, /* vsys_v */</div><div class='add'>+			      &lt;&amp;axp717_adc 4&gt;, /* pmic_temp */</div><div class='add'>+			      &lt;&amp;axp717_adc 7&gt;; /* bkup_batt_v */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wifi_pwrseq: pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-simple";</div><div class='add'>+		reset-gpios = &lt;&amp;r_pio 1 1 GPIO_ACTIVE_LOW&gt;; /* PM1 */</div><div class='add'>+		clocks = &lt;&amp;rtc CLK_OSC32K_FANOUT&gt;;</div><div class='add'>+		clock-names = "ext_clock";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_otg_vbus: regulator-otg-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "otg-vbus";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		gpio = &lt;&amp;r_pio 0 4 GPIO_ACTIVE_HIGH&gt;;	/* PL4 */</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_pcie_vcc3v3: regulator-pcie-vcc3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vcc-pcie-3v3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		gpio = &lt;&amp;r_pio 0 8 GPIO_ACTIVE_HIGH&gt;;	/* PL8 */</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb_vbus: regulator-usb-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "usb-vbus";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		gpio = &lt;&amp;r_pio 0 12 GPIO_ACTIVE_HIGH&gt;;	/* PL12 */</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc5v: regulator-vcc5v {</div><div class='add'>+		/* board wide 5V supply from USB type-C port */</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vcc-5v";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ehci0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ehci1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gmac1 {</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ext_rgmii_phy&gt;;</div><div class='add'>+	phy-supply = &lt;&amp;reg_cldo4&gt;;</div><div class='add'>+</div><div class='add'>+	tx-internal-delay-ps = &lt;0&gt;;</div><div class='add'>+	rx-internal-delay-ps = &lt;300&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	mali-supply = &lt;&amp;reg_dcdc2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdio1 {</div><div class='add'>+	ext_rgmii_phy: ethernet-phy@1 {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 8 16 IRQ_TYPE_LEVEL_LOW&gt;; /* PI16 */</div><div class='add'>+		reset-gpios = &lt;&amp;pio 8 15 GPIO_ACTIVE_LOW&gt;; /* PI15 */</div><div class='add'>+		reset-assert-us = &lt;10000&gt;;</div><div class='add'>+		reset-deassert-us = &lt;150000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc0 {</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_cldo3&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)&gt;; /* PF6 */</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc1 {</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	mmc-pwrseq = &lt;&amp;wifi_pwrseq&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_dldo1_323&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_bldo1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	brcmf: wifi@1 {</div><div class='add'>+		compatible = "brcm,bcm4329-fmac";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;r_pio&gt;;</div><div class='add'>+		interrupts = &lt;1 0 IRQ_TYPE_LEVEL_LOW&gt;; /* PM0 */</div><div class='add'>+		interrupt-names = "host-wake";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc2 {</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	cap-mmc-hw-reset;</div><div class='add'>+	mmc-ddr-1_8v;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	non-removable;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_cldo3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_cldo1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ohci0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ohci1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	vcc-pb-supply = &lt;&amp;reg_cldo3&gt;;	/* via VCC-IO */</div><div class='add'>+	vcc-pc-supply = &lt;&amp;reg_cldo1&gt;;</div><div class='add'>+	vcc-pd-supply = &lt;&amp;reg_cldo3&gt;;</div><div class='add'>+	vcc-pe-supply = &lt;&amp;reg_aldo2&gt;;</div><div class='add'>+	vcc-pf-supply = &lt;&amp;reg_cldo3&gt;;	/* VCC-IO for 3.3v; VCC-MCSI for 1.8v */</div><div class='add'>+	vcc-pg-supply = &lt;&amp;reg_bldo1&gt;;</div><div class='add'>+	vcc-ph-supply = &lt;&amp;reg_cldo3&gt;;	/* via VCC-IO */</div><div class='add'>+	vcc-pi-supply = &lt;&amp;reg_cldo3&gt;;</div><div class='add'>+	vcc-pj-supply = &lt;&amp;reg_cldo1&gt;;</div><div class='add'>+	vcc-pk-supply = &lt;&amp;reg_cldo1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;r_i2c0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	axp717: pmic@35 {</div><div class='add'>+		compatible = "x-powers,axp717";</div><div class='add'>+		reg = &lt;0x35&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;nmi_intc 0 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		vin1-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vin2-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vin3-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vin4-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		aldoin-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		bldoin-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		cldoin-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+</div><div class='add'>+		axp717_adc: adc {</div><div class='add'>+			compatible = "x-powers,axp717-adc";</div><div class='add'>+			#io-channel-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		battery-power {</div><div class='add'>+			compatible = "x-powers,axp717-battery-power-supply";</div><div class='add'>+			/* no battery; output used for dcdc4 instead */</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			/* Supplies the "little" cluster (1.4 GHz cores) */</div><div class='add'>+			reg_dcdc1: dcdc1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1160000&gt;;</div><div class='add'>+				regulator-name = "vdd-cpul";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_dcdc2: dcdc2 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;920000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;920000&gt;;</div><div class='add'>+				regulator-name = "vdd-gpu-sys";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_dcdc3: dcdc3 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;1160000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1160000&gt;;</div><div class='add'>+				regulator-name = "vcc-dram";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_dcdc4: dcdc4 {</div><div class='add'>+				/* feeds 3.3V pin on GPIO header */</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "vdd-io";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			aldo1 {</div><div class='add'>+				/* not actually connected */</div><div class='add'>+				regulator-name = "avdd-csi";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_aldo2: aldo2 {</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "vcc-pe";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_aldo3: aldo3 {</div><div class='add'>+				/* supplies the I2C pins for this PMIC */</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "vcc-pl-usb";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_aldo4: aldo4 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "vcc-pll-dxco-avcc";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_bldo1: bldo1 {</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "vcc-pg-wifi";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_bldo2: bldo2 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "vcc-pm-lpddr";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			bldo3 {</div><div class='add'>+				/* not actually connected */</div><div class='add'>+				regulator-name = "afvcc-csi";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			bldo4 {</div><div class='add'>+				/* not actually connected */</div><div class='add'>+				regulator-name = "dvdd-csi";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_cldo1: cldo1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "vcc-cvp-pc-lvds-mcsi-pk-efuse-pcie-edp-1v8";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_cldo2: cldo2 {</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "vcc3v3-csi";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_cldo3: cldo3 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "vcc-io-mmc-nand-pd-pi-usb";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_cldo4: cldo4 {</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "vcc-3v3-phy1-lcd";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_cpusldo: cpusldo {</div><div class='add'>+				/* supplies the management core */</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-name = "vdd-cpus-usb-0v9";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb-power {</div><div class='add'>+			compatible = "x-powers,axp717-usb-power-supply";</div><div class='add'>+			input-current-limit-microamp = &lt;3000000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	axp323: pmic@36 {</div><div class='add'>+		compatible = "x-powers,axp323";</div><div class='add'>+		reg = &lt;0x36&gt;;</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		status = "okay";</div><div class='add'>+</div><div class='add'>+		vin1-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vin2-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+		vin3-supply = &lt;&amp;reg_vcc5v&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			reg_aldo1_323: aldo1 {</div><div class='add'>+				/* less capable and shares load with dldo1 */</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "vcc-wifi";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_dldo1_323: dldo1 {</div><div class='add'>+				/* more capable and shares load with aldo1 */</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "vcc-wifi2";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* Supplies the "big" cluster (1.8 GHz cores) */</div><div class='add'>+			reg_dcdc1_323: dcdc1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1150000&gt;;</div><div class='add'>+				regulator-name = "vdd-cpub";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* DCDC2 is polyphased with DCDC1 */</div><div class='add'>+</div><div class='add'>+			/* Some RISC-V management core related voltage */</div><div class='add'>+			reg_dcdc3_323: dcdc3 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-name = "vdd-dnr";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;r_pio {</div><div class='add'>+/*</div><div class='add'>+ * Specifying the supply would create a circular dependency.</div><div class='add'>+ *</div><div class='add'>+ *	vcc-pl-supply = &lt;&amp;reg_aldo3&gt;;</div><div class='add'>+ */</div><div class='add'>+	vcc-pm-supply = &lt;&amp;reg_bldo2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;rtc {</div><div class='add'>+	clocks = &lt;&amp;r_ccu CLK_BUS_R_RTC&gt;, &lt;&amp;osc24M&gt;,</div><div class='add'>+		 &lt;&amp;r_ccu CLK_R_AHB&gt;, &lt;&amp;ext_osc32k&gt;;</div><div class='add'>+	clock-names = "bus", "hosc", "ahb", "ext-osc32k";</div><div class='add'>+	assigned-clocks = &lt;&amp;rtc CLK_OSC32K&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;32768&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart0_pb_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart1_pins&gt;, &lt;&amp;uart1_rts_cts_pins&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "brcm,bcm4345c5";</div><div class='add'>+		clocks = &lt;&amp;rtc CLK_OSC32K_FANOUT&gt;;</div><div class='add'>+		clock-names = "lpo";</div><div class='add'>+		vbat-supply = &lt;&amp;reg_aldo1_323&gt;;</div><div class='add'>+		vddio-supply = &lt;&amp;reg_bldo1&gt;;</div><div class='add'>+		device-wakeup-gpios = &lt;&amp;r_pio 1 3 GPIO_ACTIVE_HIGH&gt;; /* PM3 */</div><div class='add'>+		host-wakeup-gpios = &lt;&amp;r_pio 1 4 GPIO_ACTIVE_HIGH&gt;; /* PM4 */</div><div class='add'>+		shutdown-gpios = &lt;&amp;r_pio 1 2 GPIO_ACTIVE_HIGH&gt;; /* PM2 */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_otg {</div><div class='add'>+	/*</div><div class='add'>+	 * The OTG controller is connected to one of the type-A ports.</div><div class='add'>+	 * There is a regulator, controlled by a GPIO, to provide VBUS power</div><div class='add'>+	 * to the port, and a VBUSDET GPIO, to detect externally provided</div><div class='add'>+	 * power. But without ID or CC pins there is no real way to do a</div><div class='add'>+	 * runtime role detection.</div><div class='add'>+	 */</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbphy {</div><div class='add'>+	usb0_vbus-supply = &lt;&amp;reg_otg_vbus&gt;;</div><div class='add'>+	usb0_vbus_det-gpios = &lt;&amp;r_pio 0 7 GPIO_ACTIVE_HIGH&gt;; /* PL7 */</div><div class='add'>+	usb1_vbus-supply = &lt;&amp;reg_usb_vbus&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/altera/Makefile b/arch/arm64/boot/dts/altera/Makefile<br/>index 10119c7ab437..1bf0c472f6b4 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/altera/Makefile?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/altera/Makefile</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/altera/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/altera/Makefile</a></div><div class='hunk'>@@ -1,3 +1,4 @@</div><div class='ctx'> # SPDX-License-Identifier: GPL-2.0-only</div><div class='del'>-dtb-$(CONFIG_ARCH_STRATIX10) += socfpga_stratix10_socdk.dtb \</div><div class='del'>-				socfpga_stratix10_socdk_nand.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_stratix10_socdk.dtb \</div><div class='add'>+				socfpga_stratix10_socdk_nand.dtb \</div><div class='add'>+				socfpga_stratix10_swvp.dtb</div><div class='head'>diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi<br/>index d1fc9c2055f4..657e986e5dba 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi</a></div><div class='hunk'>@@ -34,6 +34,7 @@</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_shared&gt;;</div><div class='ctx'> 			reg = &lt;0x0&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -41,6 +42,7 @@</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_shared&gt;;</div><div class='ctx'> 			reg = &lt;0x1&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -48,6 +50,7 @@</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_shared&gt;;</div><div class='ctx'> 			reg = &lt;0x2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -55,12 +58,38 @@</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_shared&gt;;</div><div class='ctx'> 			reg = &lt;0x3&gt;;</div><div class='ctx'> 		};</div><div class='add'>+</div><div class='add'>+		l2_shared: cache {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	firmware {</div><div class='add'>+		svc {</div><div class='add'>+			compatible = "intel,stratix10-svc";</div><div class='add'>+			method = "smc";</div><div class='add'>+			memory-region = &lt;&amp;service_reserved&gt;;</div><div class='add'>+</div><div class='add'>+			fpga_mgr: fpga-mgr {</div><div class='add'>+				compatible = "intel,stratix10-soc-fpga-mgr";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fpga-region {</div><div class='add'>+		compatible = "fpga-region";</div><div class='add'>+		#address-cells = &lt;0x2&gt;;</div><div class='add'>+		#size-cells = &lt;0x2&gt;;</div><div class='add'>+		fpga-mgr = &lt;&amp;fpga_mgr&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	pmu {</div><div class='del'>-		compatible = "arm,armv8-pmuv3";</div><div class='add'>+		compatible = "arm,cortex-a53-pmu";</div><div class='ctx'> 		interrupts = &lt;0 170 4&gt;,</div><div class='ctx'> 			     &lt;0 171 4&gt;,</div><div class='ctx'> 			     &lt;0 172 4&gt;,</div><div class='hunk'>@@ -77,7 +106,17 @@</div><div class='ctx'> 		method = "smc";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	intc: intc@fffc1000 {</div><div class='add'>+	/* Local timer */</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;1 13 0xf08&gt;,</div><div class='add'>+			     &lt;1 14 0xf08&gt;,</div><div class='add'>+			     &lt;1 11 0xf08&gt;,</div><div class='add'>+			     &lt;1 10 0xf08&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;intc&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	intc: interrupt-controller@fffc1000 {</div><div class='ctx'> 		compatible = "arm,gic-400", "arm,cortex-a15-gic";</div><div class='ctx'> 		#interrupt-cells = &lt;3&gt;;</div><div class='ctx'> 		interrupt-controller;</div><div class='hunk'>@@ -87,7 +126,38 @@</div><div class='ctx'> 		      &lt;0x0 0xfffc6000 0x0 0x2000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	soc {</div><div class='add'>+	clocks {</div><div class='add'>+		cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			clock-frequency = &lt;150000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cb_intosc_ls_clk: cb-intosc-ls-clk {</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			clock-frequency = &lt;300000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		f2s_free_clk: f2s-free-clk {</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		osc1: osc1 {</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qspi_clk: qspi-clk {</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			clock-frequency = &lt;200000000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc@0 {</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;1&gt;;</div><div class='ctx'> 		compatible = "simple-bus";</div><div class='hunk'>@@ -95,48 +165,12 @@</div><div class='ctx'> 		interrupt-parent = &lt;&amp;intc&gt;;</div><div class='ctx'> 		ranges = &lt;0 0 0 0xffffffff&gt;;</div><div class='ctx'> </div><div class='del'>-		base_fpga_region {</div><div class='del'>-			#address-cells = &lt;0x1&gt;;</div><div class='del'>-			#size-cells = &lt;0x1&gt;;</div><div class='del'>-</div><div class='del'>-			compatible = "fpga-region";</div><div class='del'>-			fpga-mgr = &lt;&amp;fpga_mgr&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='ctx'> 		clkmgr: clock-controller@ffd10000 {</div><div class='ctx'> 			compatible = "intel,stratix10-clkmgr";</div><div class='ctx'> 			reg = &lt;0xffd10000 0x1000&gt;;</div><div class='ctx'> 			#clock-cells = &lt;1&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		clocks {</div><div class='del'>-			cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {</div><div class='del'>-				#clock-cells = &lt;0&gt;;</div><div class='del'>-				compatible = "fixed-clock";</div><div class='del'>-			};</div><div class='del'>-</div><div class='del'>-			cb_intosc_ls_clk: cb-intosc-ls-clk {</div><div class='del'>-				#clock-cells = &lt;0&gt;;</div><div class='del'>-				compatible = "fixed-clock";</div><div class='del'>-			};</div><div class='del'>-</div><div class='del'>-			f2s_free_clk: f2s-free-clk {</div><div class='del'>-				#clock-cells = &lt;0&gt;;</div><div class='del'>-				compatible = "fixed-clock";</div><div class='del'>-			};</div><div class='del'>-</div><div class='del'>-			osc1: osc1 {</div><div class='del'>-				#clock-cells = &lt;0&gt;;</div><div class='del'>-				compatible = "fixed-clock";</div><div class='del'>-			};</div><div class='del'>-</div><div class='del'>-			qspi_clk: qspi-clk {</div><div class='del'>-				#clock-cells = &lt;0&gt;;</div><div class='del'>-				compatible = "fixed-clock";</div><div class='del'>-				clock-frequency = &lt;200000000&gt;;</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-</div><div class='ctx'> 		gmac0: ethernet@ff800000 {</div><div class='ctx'> 			compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";</div><div class='ctx'> 			reg = &lt;0xff800000 0x2000&gt;;</div><div class='hunk'>@@ -144,9 +178,9 @@</div><div class='ctx'> 			interrupt-names = "macirq";</div><div class='ctx'> 			mac-address = [00 00 00 00 00 00];</div><div class='ctx'> 			resets = &lt;&amp;rst EMAC0_RESET&gt;, &lt;&amp;rst EMAC0_OCP_RESET&gt;;</div><div class='del'>-			reset-names = "stmmaceth", "stmmaceth-ocp";</div><div class='del'>-			clocks = &lt;&amp;clkmgr STRATIX10_EMAC0_CLK&gt;;</div><div class='del'>-			clock-names = "stmmaceth";</div><div class='add'>+			reset-names = "stmmaceth", "ahb";</div><div class='add'>+			clocks = &lt;&amp;clkmgr STRATIX10_EMAC0_CLK&gt;, &lt;&amp;clkmgr STRATIX10_EMAC_PTP_CLK&gt;;</div><div class='add'>+			clock-names = "stmmaceth", "ptp_ref";</div><div class='ctx'> 			tx-fifo-depth = &lt;16384&gt;;</div><div class='ctx'> 			rx-fifo-depth = &lt;16384&gt;;</div><div class='ctx'> 			snps,multicast-filter-bins = &lt;256&gt;;</div><div class='hunk'>@@ -162,9 +196,9 @@</div><div class='ctx'> 			interrupt-names = "macirq";</div><div class='ctx'> 			mac-address = [00 00 00 00 00 00];</div><div class='ctx'> 			resets = &lt;&amp;rst EMAC1_RESET&gt;, &lt;&amp;rst EMAC1_OCP_RESET&gt;;</div><div class='del'>-			reset-names = "stmmaceth", "stmmaceth-ocp";</div><div class='del'>-			clocks = &lt;&amp;clkmgr STRATIX10_EMAC1_CLK&gt;;</div><div class='del'>-			clock-names = "stmmaceth";</div><div class='add'>+			reset-names = "stmmaceth", "ahb";</div><div class='add'>+			clocks = &lt;&amp;clkmgr STRATIX10_EMAC1_CLK&gt;, &lt;&amp;clkmgr STRATIX10_EMAC_PTP_CLK&gt;;</div><div class='add'>+			clock-names = "stmmaceth", "ptp_ref";</div><div class='ctx'> 			tx-fifo-depth = &lt;16384&gt;;</div><div class='ctx'> 			rx-fifo-depth = &lt;16384&gt;;</div><div class='ctx'> 			snps,multicast-filter-bins = &lt;256&gt;;</div><div class='hunk'>@@ -180,9 +214,9 @@</div><div class='ctx'> 			interrupt-names = "macirq";</div><div class='ctx'> 			mac-address = [00 00 00 00 00 00];</div><div class='ctx'> 			resets = &lt;&amp;rst EMAC2_RESET&gt;, &lt;&amp;rst EMAC2_OCP_RESET&gt;;</div><div class='del'>-			reset-names = "stmmaceth", "stmmaceth-ocp";</div><div class='del'>-			clocks = &lt;&amp;clkmgr STRATIX10_EMAC2_CLK&gt;;</div><div class='del'>-			clock-names = "stmmaceth";</div><div class='add'>+			reset-names = "stmmaceth", "ahb";</div><div class='add'>+			clocks = &lt;&amp;clkmgr STRATIX10_EMAC2_CLK&gt;, &lt;&amp;clkmgr STRATIX10_EMAC_PTP_CLK&gt;;</div><div class='add'>+			clock-names = "stmmaceth", "ptp_ref";</div><div class='ctx'> 			tx-fifo-depth = &lt;16384&gt;;</div><div class='ctx'> 			rx-fifo-depth = &lt;16384&gt;;</div><div class='ctx'> 			snps,multicast-filter-bins = &lt;256&gt;;</div><div class='hunk'>@@ -203,7 +237,7 @@</div><div class='ctx'> 				compatible = "snps,dw-apb-gpio-port";</div><div class='ctx'> 				gpio-controller;</div><div class='ctx'> 				#gpio-cells = &lt;2&gt;;</div><div class='del'>-				snps,nr-gpios = &lt;24&gt;;</div><div class='add'>+				ngpios = &lt;24&gt;;</div><div class='ctx'> 				reg = &lt;0&gt;;</div><div class='ctx'> 				interrupt-controller;</div><div class='ctx'> 				#interrupt-cells = &lt;2&gt;;</div><div class='hunk'>@@ -223,7 +257,7 @@</div><div class='ctx'> 				compatible = "snps,dw-apb-gpio-port";</div><div class='ctx'> 				gpio-controller;</div><div class='ctx'> 				#gpio-cells = &lt;2&gt;;</div><div class='del'>-				snps,nr-gpios = &lt;24&gt;;</div><div class='add'>+				ngpios = &lt;24&gt;;</div><div class='ctx'> 				reg = &lt;0&gt;;</div><div class='ctx'> 				interrupt-controller;</div><div class='ctx'> 				#interrupt-cells = &lt;2&gt;;</div><div class='hunk'>@@ -286,7 +320,7 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		mmc: dwmmc0@ff808000 {</div><div class='add'>+		mmc: mmc@ff808000 {</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			compatible = "altr,socfpga-dw-mshc";</div><div class='hunk'>@@ -299,10 +333,11 @@</div><div class='ctx'> 				 &lt;&amp;clkmgr STRATIX10_SDMMC_CLK&gt;;</div><div class='ctx'> 			clock-names = "biu", "ciu";</div><div class='ctx'> 			iommus = &lt;&amp;smmu 5&gt;;</div><div class='add'>+			altr,sysmgr-syscon = &lt;&amp;sysmgr 0x28 4&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		nand: nand@ffb90000 {</div><div class='add'>+		nand: nand-controller@ffb90000 {</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			compatible = "altr,socfpga-denali-nand";</div><div class='hunk'>@@ -321,9 +356,12 @@</div><div class='ctx'> 		ocram: sram@ffe00000 {</div><div class='ctx'> 			compatible = "mmio-sram";</div><div class='ctx'> 			reg = &lt;0xffe00000 0x100000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges = &lt;0 0xffe00000 0x100000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		pdma: pdma@ffda0000 {</div><div class='add'>+		pdma: dma-controller@ffda0000 {</div><div class='ctx'> 			compatible = "arm,pl330", "arm,primecell";</div><div class='ctx'> 			reg = &lt;0xffda0000 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;0 81 4&gt;,</div><div class='hunk'>@@ -336,17 +374,31 @@</div><div class='ctx'> 				     &lt;0 88 4&gt;,</div><div class='ctx'> 				     &lt;0 89 4&gt;;</div><div class='ctx'> 			#dma-cells = &lt;1&gt;;</div><div class='del'>-			#dma-channels = &lt;8&gt;;</div><div class='del'>-			#dma-requests = &lt;32&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;clkmgr STRATIX10_L4_MAIN_CLK&gt;;</div><div class='ctx'> 			clock-names = "apb_pclk";</div><div class='ctx'> 			resets = &lt;&amp;rst DMA_RESET&gt;, &lt;&amp;rst DMA_OCP_RESET&gt;;</div><div class='ctx'> 			reset-names = "dma", "dma-ocp";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		pinctrl0: pinctrl@ffd13000 {</div><div class='add'>+			compatible = "pinctrl-single";</div><div class='add'>+			reg = &lt;0xffd13000 0xA0&gt;;</div><div class='add'>+			#pinctrl-cells = &lt;1&gt;;</div><div class='add'>+			pinctrl-single,register-width = &lt;32&gt;;</div><div class='add'>+			pinctrl-single,function-mask = &lt;0x0000000f&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl1: pinctrl@ffd13100 {</div><div class='add'>+			compatible = "pinctrl-single";</div><div class='add'>+			reg = &lt;0xffd13100 0x20&gt;;</div><div class='add'>+			#pinctrl-cells = &lt;1&gt;;</div><div class='add'>+			pinctrl-single,register-width = &lt;32&gt;;</div><div class='add'>+			pinctrl-single,function-mask = &lt;0x0000000f&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		rst: rstmgr@ffd11000 {</div><div class='ctx'> 			#reset-cells = &lt;1&gt;;</div><div class='del'>-			compatible = "altr,stratix10-rst-mgr";</div><div class='add'>+			compatible = "altr,stratix10-rst-mgr", "altr,rst-mgr";</div><div class='ctx'> 			reg = &lt;0xffd11000 0x1000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -380,6 +432,7 @@</div><div class='ctx'> 			reg = &lt;0xffda4000 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;0 99 4&gt;;</div><div class='ctx'> 			resets = &lt;&amp;rst SPIM0_RESET&gt;;</div><div class='add'>+			reset-names = "spi";</div><div class='ctx'> 			reg-io-width = &lt;4&gt;;</div><div class='ctx'> 			num-cs = &lt;4&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;clkmgr STRATIX10_L4_MAIN_CLK&gt;;</div><div class='hunk'>@@ -393,6 +446,7 @@</div><div class='ctx'> 			reg = &lt;0xffda5000 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;0 100 4&gt;;</div><div class='ctx'> 			resets = &lt;&amp;rst SPIM1_RESET&gt;;</div><div class='add'>+			reset-names = "spi";</div><div class='ctx'> 			reg-io-width = &lt;4&gt;;</div><div class='ctx'> 			num-cs = &lt;4&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;clkmgr STRATIX10_L4_MAIN_CLK&gt;;</div><div class='hunk'>@@ -404,15 +458,6 @@</div><div class='ctx'> 			reg = &lt;0xffd12000 0x228&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		/* Local timer */</div><div class='del'>-		timer {</div><div class='del'>-			compatible = "arm,armv8-timer";</div><div class='del'>-			interrupts = &lt;1 13 0xf08&gt;,</div><div class='del'>-				     &lt;1 14 0xf08&gt;,</div><div class='del'>-				     &lt;1 11 0xf08&gt;,</div><div class='del'>-				     &lt;1 10 0xf08&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='ctx'> 		timer0: timer0@ffc03000 {</div><div class='ctx'> 			compatible = "snps,dw-apb-timer";</div><div class='ctx'> 			interrupts = &lt;0 113 4&gt;;</div><div class='hunk'>@@ -445,7 +490,7 @@</div><div class='ctx'> 			clock-names = "timer";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		uart0: serial0@ffc02000 {</div><div class='add'>+		uart0: serial@ffc02000 {</div><div class='ctx'> 			compatible = "snps,dw-apb-uart";</div><div class='ctx'> 			reg = &lt;0xffc02000 0x100&gt;;</div><div class='ctx'> 			interrupts = &lt;0 108 4&gt;;</div><div class='hunk'>@@ -456,7 +501,7 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		uart1: serial1@ffc02100 {</div><div class='add'>+		uart1: serial@ffc02100 {</div><div class='ctx'> 			compatible = "snps,dw-apb-uart";</div><div class='ctx'> 			reg = &lt;0xffc02100 0x100&gt;;</div><div class='ctx'> 			interrupts = &lt;0 109 4&gt;;</div><div class='hunk'>@@ -467,12 +512,6 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		usbphy0: usbphy@0 {</div><div class='del'>-			#phy-cells = &lt;0&gt;;</div><div class='del'>-			compatible = "usb-nop-xceiv";</div><div class='del'>-			status = "okay";</div><div class='del'>-		};</div><div class='del'>-</div><div class='ctx'> 		usb0: usb@ffb00000 {</div><div class='ctx'> 			compatible = "snps,dwc2";</div><div class='ctx'> 			reg = &lt;0xffb00000 0x40000&gt;;</div><div class='hunk'>@@ -482,6 +521,7 @@</div><div class='ctx'> 			resets = &lt;&amp;rst USB0_RESET&gt;, &lt;&amp;rst USB0_OCP_RESET&gt;;</div><div class='ctx'> 			reset-names = "dwc2", "dwc2-ecc";</div><div class='ctx'> 			clocks = &lt;&amp;clkmgr STRATIX10_USB_CLK&gt;;</div><div class='add'>+			clock-names = "otg";</div><div class='ctx'> 			iommus = &lt;&amp;smmu 6&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='hunk'>@@ -495,6 +535,7 @@</div><div class='ctx'> 			resets = &lt;&amp;rst USB1_RESET&gt;, &lt;&amp;rst USB1_OCP_RESET&gt;;</div><div class='ctx'> 			reset-names = "dwc2", "dwc2-ecc";</div><div class='ctx'> 			clocks = &lt;&amp;clkmgr STRATIX10_USB_CLK&gt;;</div><div class='add'>+			clock-names = "otg";</div><div class='ctx'> 			iommus = &lt;&amp;smmu 7&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='hunk'>@@ -589,10 +630,19 @@</div><div class='ctx'> 				interrupts = &lt;5 4&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='add'>+			sdmmca-ecc@ff8c8c00 {</div><div class='add'>+				compatible = "altr,socfpga-s10-sdmmc-ecc",</div><div class='add'>+					     "altr,socfpga-sdmmc-ecc";</div><div class='add'>+				reg = &lt;0xff8c8c00 0x100&gt;;</div><div class='add'>+				altr,ecc-parent = &lt;&amp;mmc&gt;;</div><div class='add'>+				interrupts = &lt;14 4&gt;,</div><div class='add'>+					     &lt;15 4&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		qspi: spi@ff8d2000 {</div><div class='del'>-			compatible = "cdns,qspi-nor";</div><div class='add'>+			compatible = "intel,socfpga-qspi", "cdns,qspi-nor";</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			reg = &lt;0xff8d2000 0x100&gt;,</div><div class='hunk'>@@ -605,17 +655,10 @@</div><div class='ctx'> </div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		firmware {</div><div class='del'>-			svc {</div><div class='del'>-				compatible = "intel,stratix10-svc";</div><div class='del'>-				method = "smc";</div><div class='del'>-				memory-region = &lt;&amp;service_reserved&gt;;</div><div class='del'>-</div><div class='del'>-				fpga_mgr: fpga-mgr {</div><div class='del'>-					compatible = "intel,stratix10-soc-fpga-mgr";</div><div class='del'>-				};</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='add'>+	usbphy0: usbphy0 {</div><div class='add'>+		compatible = "usb-nop-xceiv";</div><div class='add'>+		#phy-cells = &lt;0&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts<br/>index f6c4a15079d3..58f776e411fc 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts</a></div><div class='hunk'>@@ -7,6 +7,7 @@</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	model = "SoCFPGA Stratix 10 SoCDK";</div><div class='add'>+	compatible = "altr,socfpga-stratix10-socdk", "altr,socfpga-stratix10";</div><div class='ctx'> </div><div class='ctx'> 	aliases {</div><div class='ctx'> 		serial0 = &amp;uart0;</div><div class='hunk'>@@ -21,52 +22,49 @@</div><div class='ctx'> </div><div class='ctx'> 	leds {</div><div class='ctx'> 		compatible = "gpio-leds";</div><div class='del'>-		hps0 {</div><div class='add'>+		led-hps0 {</div><div class='ctx'> 			label = "hps_led0";</div><div class='ctx'> 			gpios = &lt;&amp;portb 20 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		hps1 {</div><div class='add'>+		led-hps1 {</div><div class='ctx'> 			label = "hps_led1";</div><div class='ctx'> 			gpios = &lt;&amp;portb 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		hps2 {</div><div class='add'>+		led-hps2 {</div><div class='ctx'> 			label = "hps_led2";</div><div class='ctx'> 			gpios = &lt;&amp;portb 21 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	memory {</div><div class='add'>+	memory@80000000 {</div><div class='ctx'> 		device_type = "memory";</div><div class='ctx'> 		/* We expect the bootloader to fill in the reg */</div><div class='del'>-		reg = &lt;0 0 0 0&gt;;</div><div class='add'>+		reg = &lt;0 0x80000000 0 0&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	ref_033v: 033-v-ref {</div><div class='add'>+	ref_033v: regulator-v-ref {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "0.33V";</div><div class='ctx'> 		regulator-min-microvolt = &lt;330000&gt;;</div><div class='ctx'> 		regulator-max-microvolt = &lt;330000&gt;;</div><div class='ctx'> 	};</div><div class='add'>+};</div><div class='ctx'> </div><div class='del'>-	soc {</div><div class='del'>-		clocks {</div><div class='del'>-			osc1 {</div><div class='del'>-				clock-frequency = &lt;25000000&gt;;</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='add'>+&amp;pinctrl0 {</div><div class='add'>+	i2c1_pmx_func: i2c1-pmx-func-pins {</div><div class='add'>+		pinctrl-single,pins = &lt;</div><div class='add'>+			0x78   0x4   /* I2C1_SDA (IO6-B) PIN30SEL) */</div><div class='add'>+			0x7c   0x4   /* I2C1_SCL (IO7-B) PIN31SEL */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		eccmgr {</div><div class='del'>-			sdmmca-ecc@ff8c8c00 {</div><div class='del'>-				compatible = "altr,socfpga-s10-sdmmc-ecc",</div><div class='del'>-					     "altr,socfpga-sdmmc-ecc";</div><div class='del'>-				reg = &lt;0xff8c8c00 0x100&gt;;</div><div class='del'>-				altr,ecc-parent = &lt;&amp;mmc&gt;;</div><div class='del'>-				interrupts = &lt;14 4&gt;,</div><div class='del'>-					     &lt;15 4&gt;;</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='add'>+	i2c1_pmx_func_gpio: i2c1-pmx-func-gpio-pins {</div><div class='add'>+		pinctrl-single,pins = &lt;</div><div class='add'>+			0x78   0x8   /* I2C1_SDA (IO6-B) PIN30SEL) */</div><div class='add'>+			0x7c   0x8   /* I2C1_SCL (IO7-B) PIN31SEL */</div><div class='add'>+		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -110,6 +108,11 @@</div><div class='ctx'> 	cap-mmc-highspeed;</div><div class='ctx'> 	broken-cd;</div><div class='ctx'> 	bus-width = &lt;4&gt;;</div><div class='add'>+	clk-phase-sd-hs = &lt;0&gt;, &lt;135&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;osc1 {</div><div class='add'>+	clock-frequency = &lt;25000000&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;uart0 {</div><div class='hunk'>@@ -129,7 +132,14 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> 	clock-frequency = &lt;100000&gt;;</div><div class='ctx'> 	i2c-sda-falling-time-ns = &lt;890&gt;;  /* hcnt */</div><div class='del'>-	i2c-sdl-falling-time-ns = &lt;890&gt;;  /* lcnt */</div><div class='add'>+	i2c-scl-falling-time-ns = &lt;890&gt;;  /* lcnt */</div><div class='add'>+</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c1_pmx_func&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;i2c1_pmx_func_gpio&gt;;</div><div class='add'>+</div><div class='add'>+	scl-gpios = &lt;&amp;portb 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;portb 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='ctx'> </div><div class='ctx'> 	adc@14 {</div><div class='ctx'> 		compatible = "lltc,ltc2497";</div><div class='hunk'>@@ -155,21 +165,20 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;qspi {</div><div class='add'>+	status = "okay";</div><div class='ctx'> 	flash@0 {</div><div class='del'>-		#address-cells = &lt;1&gt;;</div><div class='del'>-		#size-cells = &lt;1&gt;;</div><div class='del'>-		compatible = "n25q00a";</div><div class='add'>+		compatible = "micron,mt25qu02g", "jedec,spi-nor";</div><div class='ctx'> 		reg = &lt;0&gt;;</div><div class='ctx'> 		spi-max-frequency = &lt;100000000&gt;;</div><div class='ctx'> </div><div class='ctx'> 		m25p,fast-read;</div><div class='del'>-		cdns,page-size = &lt;256&gt;;</div><div class='del'>-		cdns,block-size = &lt;16&gt;;</div><div class='ctx'> 		cdns,read-delay = &lt;1&gt;;</div><div class='ctx'> 		cdns,tshsl-ns = &lt;50&gt;;</div><div class='ctx'> 		cdns,tsd2d-ns = &lt;50&gt;;</div><div class='ctx'> 		cdns,tchsh-ns = &lt;4&gt;;</div><div class='ctx'> 		cdns,tslch-ns = &lt;4&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;4&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='ctx'> </div><div class='ctx'> 		partitions {</div><div class='ctx'> 			compatible = "fixed-partitions";</div><div class='hunk'>@@ -178,12 +187,12 @@</div><div class='ctx'> </div><div class='ctx'> 			qspi_boot: partition@0 {</div><div class='ctx'> 				label = "Boot and fpga data";</div><div class='del'>-				reg = &lt;0x0 0x03FE0000&gt;;</div><div class='add'>+				reg = &lt;0x0 0x04200000&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			qspi_rootfs: partition@3FE0000 {</div><div class='del'>-				label = "Root Filesystem - JFFS2";</div><div class='del'>-				reg = &lt;0x03FE0000 0x0C020000&gt;;</div><div class='add'>+			root: partition@4200000 {</div><div class='add'>+				label = "Root Filesystem - UBIFS";</div><div class='add'>+				reg = &lt;0x04200000 0x0BE00000&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='head'>diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts<br/>index 9946515b8afd..92954c5beb54 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts</a></div><div class='hunk'>@@ -7,6 +7,7 @@</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	model = "SoCFPGA Stratix 10 SoCDK";</div><div class='add'>+	compatible = "altr,socfpga-stratix10-socdk", "altr,socfpga-stratix10";</div><div class='ctx'> </div><div class='ctx'> 	aliases {</div><div class='ctx'> 		serial0 = &amp;uart0;</div><div class='hunk'>@@ -21,53 +22,34 @@</div><div class='ctx'> </div><div class='ctx'> 	leds {</div><div class='ctx'> 		compatible = "gpio-leds";</div><div class='del'>-		hps0 {</div><div class='add'>+		led-hps0 {</div><div class='ctx'> 			label = "hps_led0";</div><div class='ctx'> 			gpios = &lt;&amp;portb 20 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		hps1 {</div><div class='add'>+		led-hps1 {</div><div class='ctx'> 			label = "hps_led1";</div><div class='ctx'> 			gpios = &lt;&amp;portb 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		hps2 {</div><div class='add'>+		led-hps2 {</div><div class='ctx'> 			label = "hps_led2";</div><div class='ctx'> 			gpios = &lt;&amp;portb 21 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	memory {</div><div class='add'>+	memory@80000000 {</div><div class='ctx'> 		device_type = "memory";</div><div class='ctx'> 		/* We expect the bootloader to fill in the reg */</div><div class='del'>-		reg = &lt;0 0 0 0&gt;;</div><div class='add'>+		reg = &lt;0 0x80000000 0 0&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	ref_033v: 033-v-ref {</div><div class='add'>+	ref_033v: regulator-v-ref {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "0.33V";</div><div class='ctx'> 		regulator-min-microvolt = &lt;330000&gt;;</div><div class='ctx'> 		regulator-max-microvolt = &lt;330000&gt;;</div><div class='ctx'> 	};</div><div class='del'>-</div><div class='del'>-	soc {</div><div class='del'>-		clocks {</div><div class='del'>-			osc1 {</div><div class='del'>-				clock-frequency = &lt;25000000&gt;;</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		eccmgr {</div><div class='del'>-			sdmmca-ecc@ff8c8c00 {</div><div class='del'>-				compatible = "altr,socfpga-s10-sdmmc-ecc",</div><div class='del'>-					     "altr,socfpga-sdmmc-ecc";</div><div class='del'>-				reg = &lt;0xff8c8c00 0x100&gt;;</div><div class='del'>-				altr,ecc-parent = &lt;&amp;mmc&gt;;</div><div class='del'>-				interrupts = &lt;14 4&gt;,</div><div class='del'>-					     &lt;15 4&gt;;</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;gpio1 {</div><div class='hunk'>@@ -107,10 +89,10 @@</div><div class='ctx'> &amp;nand {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='del'>-	flash@0 {</div><div class='add'>+	nand@0 {</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;1&gt;;</div><div class='del'>-		reg = &lt;0&gt;;</div><div class='ctx'> 		nand-bus-width = &lt;16&gt;;</div><div class='ctx'> </div><div class='ctx'> 		partition@0 {</div><div class='hunk'>@@ -119,32 +101,16 @@</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		partition@200000 {</div><div class='del'>-			label = "env";</div><div class='del'>-			reg = &lt;0x200000 0x40000&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		partition@240000 {</div><div class='del'>-			label = "dtb";</div><div class='del'>-			reg = &lt;0x240000 0x40000&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		partition@280000 {</div><div class='del'>-			label = "kernel";</div><div class='del'>-			reg = &lt;0x280000 0x2000000&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		partition@2280000 {</div><div class='del'>-			label = "misc";</div><div class='del'>-			reg = &lt;0x2280000 0x2000000&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		partition@4280000 {</div><div class='del'>-			label = "rootfs";</div><div class='del'>-			reg = &lt;0x4280000 0x3bd80000&gt;;</div><div class='add'>+			label = "root";</div><div class='add'>+			reg = &lt;0x200000 0x3fe00000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;osc1 {</div><div class='add'>+	clock-frequency = &lt;25000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;uart0 {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='hunk'>@@ -162,7 +128,7 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> 	clock-frequency = &lt;100000&gt;;</div><div class='ctx'> 	i2c-sda-falling-time-ns = &lt;890&gt;;  /* hcnt */</div><div class='del'>-	i2c-sdl-falling-time-ns = &lt;890&gt;;  /* lcnt */</div><div class='add'>+	i2c-scl-falling-time-ns = &lt;890&gt;;  /* lcnt */</div><div class='ctx'> </div><div class='ctx'> 	adc@14 {</div><div class='ctx'> 		compatible = "lltc,ltc2497";</div><div class='hunk'>@@ -188,16 +154,13 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;qspi {</div><div class='add'>+	status = "okay";</div><div class='ctx'> 	flash@0 {</div><div class='del'>-		#address-cells = &lt;1&gt;;</div><div class='del'>-		#size-cells = &lt;1&gt;;</div><div class='del'>-		compatible = "n25q00a";</div><div class='add'>+		compatible = "micron,mt25qu02g", "jedec,spi-nor";</div><div class='ctx'> 		reg = &lt;0&gt;;</div><div class='ctx'> 		spi-max-frequency = &lt;100000000&gt;;</div><div class='ctx'> </div><div class='ctx'> 		m25p,fast-read;</div><div class='del'>-		cdns,page-size = &lt;256&gt;;</div><div class='del'>-		cdns,block-size = &lt;16&gt;;</div><div class='ctx'> 		cdns,read-delay = &lt;1&gt;;</div><div class='ctx'> 		cdns,tshsl-ns = &lt;50&gt;;</div><div class='ctx'> 		cdns,tsd2d-ns = &lt;50&gt;;</div><div class='hunk'>@@ -211,12 +174,12 @@</div><div class='ctx'> </div><div class='ctx'> 			qspi_boot: partition@0 {</div><div class='ctx'> 				label = "Boot and fpga data";</div><div class='del'>-				reg = &lt;0x0 0x034B0000&gt;;</div><div class='add'>+				reg = &lt;0x0 0x03FE0000&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			qspi_rootfs: partition@4000000 {</div><div class='add'>+			qspi_rootfs: partition@3fe0000 {</div><div class='ctx'> 				label = "Root Filesystem - JFFS2";</div><div class='del'>-				reg = &lt;0x034B0000 0x0EB50000&gt;;</div><div class='add'>+				reg = &lt;0x03FE0000 0x0C020000&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='head'>diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts<br/>new file mode 100644<br/>index 000000000000..5ba6ca4ef19a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts</a></div><div class='hunk'>@@ -0,0 +1,105 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2022, Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "socfpga_stratix10.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "SOCFPGA Stratix 10 SWVP";</div><div class='add'>+	compatible = "altr,socfpga-stratix10-swvp", "altr,socfpga-stratix10";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+		serial1 = &amp;uart1;</div><div class='add'>+</div><div class='add'>+		timer0 = &amp;timer0;</div><div class='add'>+		timer1 = &amp;timer1;</div><div class='add'>+		timer2 = &amp;timer2;</div><div class='add'>+		timer3 = &amp;timer3;</div><div class='add'>+</div><div class='add'>+		ethernet0 = &amp;gmac0;</div><div class='add'>+		ethernet1 = &amp;gmac1;</div><div class='add'>+		ethernet2 = &amp;gmac2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial1:115200n8";</div><div class='add'>+		linux,initrd-start = &lt;0x10000000&gt;;</div><div class='add'>+		linux,initrd-end = &lt;0x125c8324&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@80000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x0 0x0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	enable-method = "spin-table";</div><div class='add'>+	cpu-release-addr = &lt;0x0 0x0000fff8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu1 {</div><div class='add'>+	enable-method = "spin-table";</div><div class='add'>+	cpu-release-addr = &lt;0x0 0x0000fff8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu2 {</div><div class='add'>+	enable-method = "spin-table";</div><div class='add'>+	cpu-release-addr = &lt;0x0 0x0000fff8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu3 {</div><div class='add'>+	enable-method = "spin-table";</div><div class='add'>+	cpu-release-addr = &lt;0x0 0x0000fff8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;osc1 {</div><div class='add'>+	clock-frequency = &lt;25000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gmac0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	phy-mode = "rgmii";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gmac1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	phy-mode = "rgmii";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gmac2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	phy-mode = "rgmii";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc {</div><div class='add'>+	status = "okay";</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	cap-mmc-highspeed;</div><div class='add'>+	broken-cd;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb0 {</div><div class='add'>+	clocks = &lt;&amp;clkmgr STRATIX10_L4_MP_CLK&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb1 {</div><div class='add'>+	clocks = &lt;&amp;clkmgr STRATIX10_L4_MP_CLK&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sysmgr {</div><div class='add'>+	reg = &lt;0xffd12000 0x1000&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/al/Makefile b/arch/arm64/boot/dts/amazon/Makefile<br/>index d79822dc30cd..ba9e11544905 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/al/Makefile?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/al/Makefile</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amazon/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amazon/Makefile</a></div><div class='hunk'>@@ -1,2 +1,3 @@</div><div class='ctx'> # SPDX-License-Identifier: GPL-2.0-only</div><div class='ctx'> dtb-$(CONFIG_ARCH_ALPINE)	+= alpine-v2-evp.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_ALPINE)	+= alpine-v3-evp.dtb</div><div class='head'>diff --git a/arch/arm64/boot/dts/al/alpine-v2-evp.dts b/arch/arm64/boot/dts/amazon/alpine-v2-evp.dts<br/>index a079d7b3063e..a079d7b3063e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/al/alpine-v2-evp.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/al/alpine-v2-evp.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amazon/alpine-v2-evp.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amazon/alpine-v2-evp.dts</a></div><div class='head'>diff --git a/arch/arm64/boot/dts/al/alpine-v2.dtsi b/arch/arm64/boot/dts/amazon/alpine-v2.dtsi<br/>index d5e7e2bb4e6c..f49209fddbbb 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/al/alpine-v2.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/al/alpine-v2.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amazon/alpine-v2.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amazon/alpine-v2.dtsi</a></div><div class='hunk'>@@ -39,6 +39,7 @@</div><div class='ctx'> / {</div><div class='ctx'> 	model = "Annapurna Labs Alpine v2";</div><div class='ctx'> 	compatible = "al,alpine-v2";</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='ctx'> 	#address-cells = &lt;2&gt;;</div><div class='ctx'> 	#size-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -89,6 +90,22 @@</div><div class='ctx'> 		clock-frequency = &lt;1000000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu {</div><div class='add'>+		compatible = "arm,cortex-a57-pmu";</div><div class='add'>+		interrupts = &lt;GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	soc {</div><div class='ctx'> 		compatible = "simple-bus";</div><div class='ctx'> 		#address-cells = &lt;2&gt;;</div><div class='hunk'>@@ -97,23 +114,7 @@</div><div class='ctx'> 		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='ctx'> 		ranges;</div><div class='ctx'> </div><div class='del'>-		timer {</div><div class='del'>-			compatible = "arm,armv8-timer";</div><div class='del'>-			interrupts = &lt;GIC_PPI 13 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='del'>-				     &lt;GIC_PPI 14 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='del'>-				     &lt;GIC_PPI 11 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='del'>-				     &lt;GIC_PPI 10 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		pmu {</div><div class='del'>-			compatible = "arm,armv8-pmuv3";</div><div class='del'>-			interrupts = &lt;GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				     &lt;GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				     &lt;GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				     &lt;GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		gic: gic@f0100000 {</div><div class='add'>+		gic: interrupt-controller@f0200000 {</div><div class='ctx'> 			compatible = "arm,gic-v3";</div><div class='ctx'> 			reg = &lt;0x0 0xf0200000 0x0 0x10000&gt;,	/* GIC Dist */</div><div class='ctx'> 			      &lt;0x0 0xf0280000 0x0 0x200000&gt;,	/* GICR */</div><div class='hunk'>@@ -122,6 +123,7 @@</div><div class='ctx'> 			      &lt;0x0 0xf0120000 0x0 0x2000&gt;;	/* GICH */</div><div class='ctx'> 			interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			interrupt-controller;</div><div class='add'>+			#address-cells = &lt;0&gt;;</div><div class='ctx'> 			#interrupt-cells = &lt;3&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -145,13 +147,12 @@</div><div class='ctx'> 		msix: msix@fbe00000 {</div><div class='ctx'> 			compatible = "al,alpine-msix";</div><div class='ctx'> 			reg = &lt;0x0 0xfbe00000 0x0 0x100000&gt;;</div><div class='del'>-			interrupt-controller;</div><div class='ctx'> 			msi-controller;</div><div class='ctx'> 			al,msi-base-spi = &lt;160&gt;;</div><div class='ctx'> 			al,msi-num-spis = &lt;160&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		io-fabric {</div><div class='add'>+		io-bus@fc000000 {</div><div class='ctx'> 			compatible = "simple-bus";</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;1&gt;;</div><div class='hunk'>@@ -159,7 +160,6 @@</div><div class='ctx'> </div><div class='ctx'> 			uart0: serial@1883000 {</div><div class='ctx'> 				compatible = "ns16550a";</div><div class='del'>-				device_type = "serial";</div><div class='ctx'> 				reg = &lt;0x1883000 0x1000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				clock-frequency = &lt;500000000&gt;;</div><div class='hunk'>@@ -170,7 +170,6 @@</div><div class='ctx'> </div><div class='ctx'> 			uart1: serial@1884000 {</div><div class='ctx'> 				compatible = "ns16550a";</div><div class='del'>-				device_type = "serial";</div><div class='ctx'> 				reg = &lt;0x1884000 0x1000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				clock-frequency = &lt;500000000&gt;;</div><div class='hunk'>@@ -181,7 +180,6 @@</div><div class='ctx'> </div><div class='ctx'> 			uart2: serial@1885000 {</div><div class='ctx'> 				compatible = "ns16550a";</div><div class='del'>-				device_type = "serial";</div><div class='ctx'> 				reg = &lt;0x1885000 0x1000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				clock-frequency = &lt;500000000&gt;;</div><div class='hunk'>@@ -192,7 +190,6 @@</div><div class='ctx'> </div><div class='ctx'> 			uart3: serial@1886000 {</div><div class='ctx'> 				compatible = "ns16550a";</div><div class='del'>-				device_type = "serial";</div><div class='ctx'> 				reg = &lt;0x1886000 0x1000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				clock-frequency = &lt;500000000&gt;;</div><div class='head'>diff --git a/arch/arm64/boot/dts/amazon/alpine-v3-evp.dts b/arch/arm64/boot/dts/amazon/alpine-v3-evp.dts<br/>new file mode 100644<br/>index 000000000000..48078f5ea545<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amazon/alpine-v3-evp.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amazon/alpine-v3-evp.dts</a></div><div class='hunk'>@@ -0,0 +1,24 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "alpine-v3.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Amazon's Annapurna Labs Alpine v3 Evaluation Platform (EVP)";</div><div class='add'>+	compatible = "amazon,al-alpine-v3-evp", "amazon,al-alpine-v3";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+		serial1 = &amp;uart1;</div><div class='add'>+		serial2 = &amp;uart2;</div><div class='add'>+		serial3 = &amp;uart3;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 { status = "okay"; };</div><div class='head'>diff --git a/arch/arm64/boot/dts/amazon/alpine-v3.dtsi b/arch/arm64/boot/dts/amazon/alpine-v3.dtsi<br/>new file mode 100644<br/>index 000000000000..bd35e0e9d0ab<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amazon/alpine-v3.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amazon/alpine-v3.dtsi</a></div><div class='hunk'>@@ -0,0 +1,412 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2020, Amazon.com, Inc. or its affiliates. All Rights Reserved</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Amazon's Annapurna Labs Alpine v3";</div><div class='add'>+	compatible = "amazon,al-alpine-v3";</div><div class='add'>+</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a72";</div><div class='add'>+			reg = &lt;0x0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			i-cache-size = &lt;0xc000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;cluster0_l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu@1 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a72";</div><div class='add'>+			reg = &lt;0x1&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			i-cache-size = &lt;0xc000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;cluster0_l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu@2 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a72";</div><div class='add'>+			reg = &lt;0x2&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			i-cache-size = &lt;0xc000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;cluster0_l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu@3 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a72";</div><div class='add'>+			reg = &lt;0x3&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			i-cache-size = &lt;0xc000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;cluster0_l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu@100 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a72";</div><div class='add'>+			reg = &lt;0x100&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			i-cache-size = &lt;0xc000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;cluster1_l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu@101 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a72";</div><div class='add'>+			reg = &lt;0x101&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			i-cache-size = &lt;0xc000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;cluster1_l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu@102 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a72";</div><div class='add'>+			reg = &lt;0x102&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			i-cache-size = &lt;0xc000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;cluster1_l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu@103 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a72";</div><div class='add'>+			reg = &lt;0x103&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			i-cache-size = &lt;0xc000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;cluster1_l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu@200 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a72";</div><div class='add'>+			reg = &lt;0x200&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			i-cache-size = &lt;0xc000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;cluster2_l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu@201 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a72";</div><div class='add'>+			reg = &lt;0x201&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			i-cache-size = &lt;0xc000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;cluster2_l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu@202 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a72";</div><div class='add'>+			reg = &lt;0x202&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			i-cache-size = &lt;0xc000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;cluster2_l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu@203 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a72";</div><div class='add'>+			reg = &lt;0x203&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			i-cache-size = &lt;0xc000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;cluster2_l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu@300 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a72";</div><div class='add'>+			reg = &lt;0x300&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			i-cache-size = &lt;0xc000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;cluster3_l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu@301 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a72";</div><div class='add'>+			reg = &lt;0x301&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			i-cache-size = &lt;0xc000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;cluster3_l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu@302 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a72";</div><div class='add'>+			reg = &lt;0x302&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			i-cache-size = &lt;0xc000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;cluster3_l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu@303 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a72";</div><div class='add'>+			reg = &lt;0x303&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			i-cache-size = &lt;0xc000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;cluster3_l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cluster0_l2: cache-0 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-size = &lt;0x200000&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;2048&gt;;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cluster1_l2: cache-100 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-size = &lt;0x200000&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;2048&gt;;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cluster2_l2: cache-200 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-size = &lt;0x200000&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;2048&gt;;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cluster3_l2: cache-300 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-size = &lt;0x200000&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;2048&gt;;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		secmon@0 {</div><div class='add'>+			reg = &lt;0x0 0x0 0x0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-0.2";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu {</div><div class='add'>+		compatible = "arm,cortex-a72-pmu";</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@f0800000 {</div><div class='add'>+			compatible = "arm,gic-v3";</div><div class='add'>+			#address-cells = &lt;0&gt;;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			reg = &lt;0x0 0xf0800000 0 0x10000&gt;,	/* GICD */</div><div class='add'>+			      &lt;0x0 0xf0a00000 0 0x200000&gt;,	/* GICR */</div><div class='add'>+			      &lt;0x0 0xf0000000 0 0x2000&gt;,	/* GICC */</div><div class='add'>+			      &lt;0x0 0xf0010000 0 0x1000&gt;,	/* GICH */</div><div class='add'>+			      &lt;0x0 0xf0020000 0 0x2000&gt;;	/* GICV */</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie@fbd00000 {</div><div class='add'>+			compatible = "pci-host-ecam-generic";</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			reg = &lt;0x0 0xfbd00000 0x0 0x100000&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0xf800 0 0 7&gt;;</div><div class='add'>+			/* 8 x legacy interrupts for SATA only */</div><div class='add'>+			interrupt-map = &lt;0x4000 0 0 1 &amp;gic 0 57 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0x4800 0 0 1 &amp;gic 0 58 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0x5000 0 0 1 &amp;gic 0 59 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0x5800 0 0 1 &amp;gic 0 60 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0x6000 0 0 1 &amp;gic 0 61 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0x6800 0 0 1 &amp;gic 0 62 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0x7000 0 0 1 &amp;gic 0 63 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0x7800 0 0 1 &amp;gic 0 64 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			ranges = &lt;0x02000000 0x0 0xfe000000 0x0 0xfe000000 0x0 0x1000000&gt;;</div><div class='add'>+			bus-range = &lt;0x00 0x00&gt;;</div><div class='add'>+			msi-parent = &lt;&amp;msix&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		msix: msix@fbe00000 {</div><div class='add'>+			compatible = "al,alpine-msix";</div><div class='add'>+			reg = &lt;0x0 0xfbe00000 0x0 0x100000&gt;;</div><div class='add'>+			msi-controller;</div><div class='add'>+			al,msi-base-spi = &lt;336&gt;;</div><div class='add'>+			al,msi-num-spis = &lt;959&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		io-bus@fc000000 {</div><div class='add'>+			compatible = "simple-bus";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges = &lt;0x0 0x0 0xfc000000 0x2000000&gt;;</div><div class='add'>+</div><div class='add'>+			uart0: serial@1883000 {</div><div class='add'>+				compatible = "ns16550a";</div><div class='add'>+				reg = &lt;0x1883000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clock-frequency = &lt;0&gt;; /* Filled by firmware */</div><div class='add'>+				reg-shift = &lt;2&gt;;</div><div class='add'>+				reg-io-width = &lt;4&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart1: serial@1884000 {</div><div class='add'>+				compatible = "ns16550a";</div><div class='add'>+				reg = &lt;0x1884000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clock-frequency = &lt;0&gt;; /* Filled by firmware */</div><div class='add'>+				reg-shift = &lt;2&gt;;</div><div class='add'>+				reg-io-width = &lt;4&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart2: serial@1885000 {</div><div class='add'>+				compatible = "ns16550a";</div><div class='add'>+				reg = &lt;0x1885000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clock-frequency = &lt;0&gt;; /* Filled by firmware */</div><div class='add'>+				reg-shift = &lt;2&gt;;</div><div class='add'>+				reg-io-width = &lt;4&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart3: serial@1886000 {</div><div class='add'>+				compatible = "ns16550a";</div><div class='add'>+				reg = &lt;0x1886000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clock-frequency = &lt;0&gt;; /* Filled by firmware */</div><div class='add'>+				reg-shift = &lt;2&gt;;</div><div class='add'>+				reg-io-width = &lt;4&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amd/Makefile b/arch/arm64/boot/dts/amd/Makefile<br/>index 6a6093064a32..8502cc2afbc5 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amd/Makefile?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amd/Makefile</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amd/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amd/Makefile</a></div><div class='hunk'>@@ -1,4 +1,3 @@</div><div class='ctx'> # SPDX-License-Identifier: GPL-2.0</div><div class='del'>-dtb-$(CONFIG_ARCH_SEATTLE) += amd-overdrive.dtb \</div><div class='del'>-			amd-overdrive-rev-b0.dtb amd-overdrive-rev-b1.dtb \</div><div class='del'>-			husky.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_PENSANDO) += elba-asic.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_SEATTLE) += amd-overdrive-rev-b0.dtb amd-overdrive-rev-b1.dtb</div><div class='head'>diff --git a/arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts b/arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts<br/>index 8e341be9a399..8862adae44e9 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts</a></div><div class='hunk'>@@ -9,6 +9,7 @@</div><div class='ctx'> /dts-v1/;</div><div class='ctx'> </div><div class='ctx'> /include/ "amd-seattle-soc.dtsi"</div><div class='add'>+/include/ "amd-seattle-cpus.dtsi"</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	model = "AMD Seattle (Rev.B0) Development Board (Overdrive)";</div><div class='hunk'>@@ -19,59 +20,49 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	psci {</div><div class='del'>-		compatible   = "arm,psci-0.2";</div><div class='del'>-		method       = "smc";</div><div class='add'>+		compatible = "arm,psci-0.2";</div><div class='add'>+		method = "smc";</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;ccp0 {</div><div class='del'>-	status = "ok";</div><div class='del'>-	amd,zlib-support = &lt;1&gt;;</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * NOTE: In Rev.B, gpio0 is reserved.</div><div class='ctx'>  */</div><div class='ctx'> &amp;gpio1 {</div><div class='del'>-	status = "ok";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;gpio2 {</div><div class='del'>-	status = "ok";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;gpio3 {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;gpio4 {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;i2c0 {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;i2c1 {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;pcie0 {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;spi0 {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;spi1 {</div><div class='del'>-	status = "ok";</div><div class='del'>-	sdcard0: sdcard@0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	sdcard0: mmc@0 {</div><div class='ctx'> 		compatible = "mmc-spi-slot";</div><div class='ctx'> 		reg = &lt;0&gt;;</div><div class='ctx'> 		spi-max-frequency = &lt;20000000&gt;;</div><div class='ctx'> 		voltage-ranges = &lt;3200 3400&gt;;</div><div class='del'>-		pl022,hierarchy = &lt;0&gt;;</div><div class='ctx'> 		pl022,interface = &lt;0&gt;;</div><div class='ctx'> 		pl022,com-mode = &lt;0x0&gt;;</div><div class='ctx'> 		pl022,rx-level-trig = &lt;0&gt;;</div><div class='hunk'>@@ -79,10 +70,6 @@</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;ipmi_kcs {</div><div class='del'>-	status = "ok";</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> &amp;smb0 {</div><div class='ctx'> 	/include/ "amd-seattle-xgbe-b.dtsi"</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dts b/arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dts<br/>index 92cef05c6b74..b34dd8d5d1b1 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dts</a></div><div class='hunk'>@@ -8,85 +8,25 @@</div><div class='ctx'> </div><div class='ctx'> /dts-v1/;</div><div class='ctx'> </div><div class='del'>-/include/ "amd-seattle-soc.dtsi"</div><div class='add'>+/include/ "amd-overdrive-rev-b0.dts"</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	model = "AMD Seattle (Rev.B1) Development Board (Overdrive)";</div><div class='del'>-	compatible = "amd,seattle-overdrive", "amd,seattle";</div><div class='del'>-</div><div class='del'>-	chosen {</div><div class='del'>-		stdout-path = &amp;serial0;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	psci {</div><div class='del'>-		compatible   = "arm,psci-0.2";</div><div class='del'>-		method       = "smc";</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;ccp0 {</div><div class='del'>-	status = "ok";</div><div class='del'>-	amd,zlib-support = &lt;1&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-/**</div><div class='del'>- * NOTE: In Rev.B, gpio0 is reserved.</div><div class='del'>- */</div><div class='del'>-&amp;gpio1 {</div><div class='del'>-	status = "ok";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;gpio2 {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;gpio3 {</div><div class='del'>-	status = "ok";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;gpio4 {</div><div class='del'>-	status = "ok";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;i2c0 {</div><div class='del'>-	status = "ok";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;i2c1 {</div><div class='del'>-	status = "ok";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;pcie0 {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;sata1 {</div><div class='del'>-	status = "ok";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;spi0 {</div><div class='del'>-	status = "ok";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;spi1 {</div><div class='del'>-	status = "ok";</div><div class='del'>-	sdcard0: sdcard@0 {</div><div class='del'>-		compatible = "mmc-spi-slot";</div><div class='del'>-		reg = &lt;0&gt;;</div><div class='del'>-		spi-max-frequency = &lt;20000000&gt;;</div><div class='del'>-		voltage-ranges = &lt;3200 3400&gt;;</div><div class='del'>-		pl022,hierarchy = &lt;0&gt;;</div><div class='del'>-		pl022,interface = &lt;0&gt;;</div><div class='del'>-		pl022,com-mode = &lt;0x0&gt;;</div><div class='del'>-		pl022,rx-level-trig = &lt;0&gt;;</div><div class='del'>-		pl022,tx-level-trig = &lt;0&gt;;</div><div class='del'>-	};</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;ipmi_kcs {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;smb0 {</div><div class='del'>-	/include/ "amd-seattle-xgbe-b.dtsi"</div><div class='del'>-};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amd/amd-overdrive.dts b/arch/arm64/boot/dts/amd/amd-overdrive.dts<br/>deleted file mode 100644<br/>index 41b3a6c0993d..000000000000<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amd/amd-overdrive.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amd/amd-overdrive.dts</a><br/>+++ /dev/null</div><div class='hunk'>@@ -1,66 +0,0 @@</div><div class='del'>-// SPDX-License-Identifier: GPL-2.0</div><div class='del'>-/*</div><div class='del'>- * DTS file for AMD Seattle Overdrive Development Board</div><div class='del'>- *</div><div class='del'>- * Copyright (C) 2014 Advanced Micro Devices, Inc.</div><div class='del'>- */</div><div class='del'>-</div><div class='del'>-/dts-v1/;</div><div class='del'>-</div><div class='del'>-/include/ "amd-seattle-soc.dtsi"</div><div class='del'>-</div><div class='del'>-/ {</div><div class='del'>-	model = "AMD Seattle Development Board (Overdrive)";</div><div class='del'>-	compatible = "amd,seattle-overdrive", "amd,seattle";</div><div class='del'>-</div><div class='del'>-	chosen {</div><div class='del'>-		stdout-path = &amp;serial0;</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;ccp0 {</div><div class='del'>-	status = "ok";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;gpio0 {</div><div class='del'>-	status = "ok";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;gpio1 {</div><div class='del'>-	status = "ok";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;i2c0 {</div><div class='del'>-	status = "ok";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;pcie0 {</div><div class='del'>-	status = "ok";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;spi0 {</div><div class='del'>-	status = "ok";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;spi1 {</div><div class='del'>-	status = "ok";</div><div class='del'>-	sdcard0: sdcard@0 {</div><div class='del'>-		compatible = "mmc-spi-slot";</div><div class='del'>-		reg = &lt;0&gt;;</div><div class='del'>-		spi-max-frequency = &lt;20000000&gt;;</div><div class='del'>-		voltage-ranges = &lt;3200 3400&gt;;</div><div class='del'>-		gpios = &lt;&amp;gpio0 7 0&gt;;</div><div class='del'>-		interrupt-parent = &lt;&amp;gpio0&gt;;</div><div class='del'>-		interrupts = &lt;7 3&gt;;</div><div class='del'>-		pl022,hierarchy = &lt;0&gt;;</div><div class='del'>-		pl022,interface = &lt;0&gt;;</div><div class='del'>-		pl022,com-mode = &lt;0x0&gt;;</div><div class='del'>-		pl022,rx-level-trig = &lt;0&gt;;</div><div class='del'>-		pl022,tx-level-trig = &lt;0&gt;;</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;v2m0 {</div><div class='del'>-	arm,msi-base-spi = &lt;64&gt;;</div><div class='del'>-	arm,msi-num-spis = &lt;256&gt;;</div><div class='del'>-};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amd/amd-seattle-clks.dtsi b/arch/arm64/boot/dts/amd/amd-seattle-clks.dtsi<br/>index 2dd2c28171ee..73f687773ce6 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amd/amd-seattle-clks.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amd/amd-seattle-clks.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amd/amd-seattle-clks.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amd/amd-seattle-clks.dtsi</a></div><div class='hunk'>@@ -5,51 +5,39 @@</div><div class='ctx'>  * Copyright (C) 2014 Advanced Micro Devices, Inc.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-	adl3clk_100mhz: clk100mhz_0 {</div><div class='add'>+	adl3clk_100mhz: uartspiclk_100mhz: clock-100000000 {</div><div class='ctx'> 		compatible = "fixed-clock";</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='ctx'> 		clock-frequency = &lt;100000000&gt;;</div><div class='ctx'> 		clock-output-names = "adl3clk_100mhz";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	ccpclk_375mhz: clk375mhz {</div><div class='add'>+	ccpclk_375mhz: clock-375000000 {</div><div class='ctx'> 		compatible = "fixed-clock";</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='ctx'> 		clock-frequency = &lt;375000000&gt;;</div><div class='ctx'> 		clock-output-names = "ccpclk_375mhz";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sataclk_333mhz: clk333mhz {</div><div class='add'>+	sataclk_333mhz: clock-333000000 {</div><div class='ctx'> 		compatible = "fixed-clock";</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='ctx'> 		clock-frequency = &lt;333000000&gt;;</div><div class='ctx'> 		clock-output-names = "sataclk_333mhz";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pcieclk_500mhz: clk500mhz_0 {</div><div class='add'>+	dmaclk_500mhz: pcieclk_500mhz: clock-500000000 {</div><div class='ctx'> 		compatible = "fixed-clock";</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='ctx'> 		clock-frequency = &lt;500000000&gt;;</div><div class='ctx'> 		clock-output-names = "pcieclk_500mhz";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	dmaclk_500mhz: clk500mhz_1 {</div><div class='del'>-		compatible = "fixed-clock";</div><div class='del'>-		#clock-cells = &lt;0&gt;;</div><div class='del'>-		clock-frequency = &lt;500000000&gt;;</div><div class='del'>-		clock-output-names = "dmaclk_500mhz";</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	miscclk_250mhz: clk250mhz_4 {</div><div class='add'>+	xgmacclk0_dma_250mhz: xgmacclk0_ptp_250mhz: xgmacclk1_dma_250mhz: xgmacclk1_ptp_250mhz:</div><div class='add'>+	miscclk_250mhz: clock-250000000 {</div><div class='ctx'> 		compatible = "fixed-clock";</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='ctx'> 		clock-frequency = &lt;250000000&gt;;</div><div class='ctx'> 		clock-output-names = "miscclk_250mhz";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	uartspiclk_100mhz: clk100mhz_1 {</div><div class='del'>-		compatible = "fixed-clock";</div><div class='del'>-		#clock-cells = &lt;0&gt;;</div><div class='del'>-		clock-frequency = &lt;100000000&gt;;</div><div class='del'>-		clock-output-names = "uartspiclk_100mhz";</div><div class='del'>-	};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi b/arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi<br/>new file mode 100644<br/>index 000000000000..93688a0b6820<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi</a></div><div class='hunk'>@@ -0,0 +1,224 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;0x1&gt;;</div><div class='add'>+		#size-cells = &lt;0x0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu-map {</div><div class='add'>+			cluster0 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;CPU0&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;CPU1&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+			cluster1 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;CPU2&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;CPU3&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+			cluster2 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;CPU4&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;CPU5&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+			cluster3 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;CPU6&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;CPU7&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		CPU0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a57";</div><div class='add'>+			reg = &lt;0x0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+</div><div class='add'>+			i-cache-size = &lt;0xC000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			l2-cache = &lt;&amp;L2_0&gt;;</div><div class='add'>+</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		CPU1: cpu@1 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a57";</div><div class='add'>+			reg = &lt;0x1&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+</div><div class='add'>+			i-cache-size = &lt;0xC000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			l2-cache = &lt;&amp;L2_0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		CPU2: cpu@100 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a57";</div><div class='add'>+			reg = &lt;0x100&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+</div><div class='add'>+			i-cache-size = &lt;0xC000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			l2-cache = &lt;&amp;L2_1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		CPU3: cpu@101 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a57";</div><div class='add'>+			reg = &lt;0x101&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+</div><div class='add'>+			i-cache-size = &lt;0xC000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			l2-cache = &lt;&amp;L2_1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		CPU4: cpu@200 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a57";</div><div class='add'>+			reg = &lt;0x200&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+</div><div class='add'>+			i-cache-size = &lt;0xC000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			l2-cache = &lt;&amp;L2_2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		CPU5: cpu@201 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a57";</div><div class='add'>+			reg = &lt;0x201&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+</div><div class='add'>+			i-cache-size = &lt;0xC000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			l2-cache = &lt;&amp;L2_2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		CPU6: cpu@300 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a57";</div><div class='add'>+			reg = &lt;0x300&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+</div><div class='add'>+			i-cache-size = &lt;0xC000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			l2-cache = &lt;&amp;L2_3&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		CPU7: cpu@301 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a57";</div><div class='add'>+			reg = &lt;0x301&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+</div><div class='add'>+			i-cache-size = &lt;0xC000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			l2-cache = &lt;&amp;L2_3&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	L2_0: l2-cache0 {</div><div class='add'>+		cache-size = &lt;0x100000&gt;;</div><div class='add'>+		cache-line-size = &lt;64&gt;;</div><div class='add'>+		cache-sets = &lt;1024&gt;;</div><div class='add'>+		cache-unified;</div><div class='add'>+		next-level-cache = &lt;&amp;L3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	L2_1: l2-cache1 {</div><div class='add'>+		cache-size = &lt;0x100000&gt;;</div><div class='add'>+		cache-line-size = &lt;64&gt;;</div><div class='add'>+		cache-sets = &lt;1024&gt;;</div><div class='add'>+		cache-unified;</div><div class='add'>+		next-level-cache = &lt;&amp;L3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	L2_2: l2-cache2 {</div><div class='add'>+		cache-size = &lt;0x100000&gt;;</div><div class='add'>+		cache-line-size = &lt;64&gt;;</div><div class='add'>+		cache-sets = &lt;1024&gt;;</div><div class='add'>+		cache-unified;</div><div class='add'>+		next-level-cache = &lt;&amp;L3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	L2_3: l2-cache3 {</div><div class='add'>+		cache-size = &lt;0x100000&gt;;</div><div class='add'>+		cache-line-size = &lt;64&gt;;</div><div class='add'>+		cache-sets = &lt;1024&gt;;</div><div class='add'>+		cache-unified;</div><div class='add'>+		next-level-cache = &lt;&amp;L3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	L3: l3-cache {</div><div class='add'>+		cache-level = &lt;3&gt;;</div><div class='add'>+		cache-size = &lt;0x800000&gt;;</div><div class='add'>+		cache-line-size = &lt;64&gt;;</div><div class='add'>+		cache-sets = &lt;8192&gt;;</div><div class='add'>+		cache-unified;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu {</div><div class='add'>+		compatible = "arm,cortex-a57-pmu";</div><div class='add'>+		interrupts = &lt;0x0 0x7 0x4&gt;,</div><div class='add'>+			     &lt;0x0 0x8 0x4&gt;,</div><div class='add'>+			     &lt;0x0 0x9 0x4&gt;,</div><div class='add'>+			     &lt;0x0 0xa 0x4&gt;,</div><div class='add'>+			     &lt;0x0 0xb 0x4&gt;,</div><div class='add'>+			     &lt;0x0 0xc 0x4&gt;,</div><div class='add'>+			     &lt;0x0 0xd 0x4&gt;,</div><div class='add'>+			     &lt;0x0 0xe 0x4&gt;;</div><div class='add'>+		interrupt-affinity = &lt;&amp;CPU0&gt;,</div><div class='add'>+				     &lt;&amp;CPU1&gt;,</div><div class='add'>+				     &lt;&amp;CPU2&gt;,</div><div class='add'>+				     &lt;&amp;CPU3&gt;,</div><div class='add'>+				     &lt;&amp;CPU4&gt;,</div><div class='add'>+				     &lt;&amp;CPU5&gt;,</div><div class='add'>+				     &lt;&amp;CPU6&gt;,</div><div class='add'>+				     &lt;&amp;CPU7&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi b/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi<br/>index b664e7af74eb..a611f8288b3e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi</a></div><div class='hunk'>@@ -11,6 +11,8 @@</div><div class='ctx'> 	#address-cells = &lt;2&gt;;</div><div class='ctx'> 	#size-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='add'>+	/include/ "amd-seattle-clks.dtsi"</div><div class='add'>+</div><div class='ctx'> 	gic0: interrupt-controller@e1101000 {</div><div class='ctx'> 		compatible = "arm,gic-400", "arm,cortex-a15-gic";</div><div class='ctx'> 		interrupt-controller;</div><div class='hunk'>@@ -38,19 +40,7 @@</div><div class='ctx'> 			     &lt;1 10 0xff04&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pmu {</div><div class='del'>-		compatible = "arm,armv8-pmuv3";</div><div class='del'>-		interrupts = &lt;0 7 4&gt;,</div><div class='del'>-			     &lt;0 8 4&gt;,</div><div class='del'>-			     &lt;0 9 4&gt;,</div><div class='del'>-			     &lt;0 10 4&gt;,</div><div class='del'>-			     &lt;0 11 4&gt;,</div><div class='del'>-			     &lt;0 12 4&gt;,</div><div class='del'>-			     &lt;0 13 4&gt;,</div><div class='del'>-			     &lt;0 14 4&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	smb0: smb {</div><div class='add'>+	smb0: bus {</div><div class='ctx'> 		compatible = "simple-bus";</div><div class='ctx'> 		#address-cells = &lt;2&gt;;</div><div class='ctx'> 		#size-cells = &lt;2&gt;;</div><div class='hunk'>@@ -63,13 +53,12 @@</div><div class='ctx'> 		 */</div><div class='ctx'> 		dma-ranges = &lt;0x0 0x0 0x0 0x0 0x100 0x0&gt;;</div><div class='ctx'> </div><div class='del'>-		/include/ "amd-seattle-clks.dtsi"</div><div class='del'>-</div><div class='ctx'> 		sata0: sata@e0300000 {</div><div class='ctx'> 			compatible = "snps,dwc-ahci";</div><div class='ctx'> 			reg = &lt;0 0xe0300000 0 0xf0000&gt;;</div><div class='ctx'> 			interrupts = &lt;0 355 4&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;sataclk_333mhz&gt;;</div><div class='add'>+			iommus = &lt;&amp;sata0_smmu 0x0 0x1f&gt;;</div><div class='ctx'> 			dma-coherent;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -80,6 +69,27 @@</div><div class='ctx'> 			reg = &lt;0 0xe0d00000 0 0xf0000&gt;;</div><div class='ctx'> 			interrupts = &lt;0 354 4&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;sataclk_333mhz&gt;;</div><div class='add'>+			iommus = &lt;&amp;sata1_smmu 0x0e&gt;,</div><div class='add'>+				 &lt;&amp;sata1_smmu 0x0f&gt;,</div><div class='add'>+				 &lt;&amp;sata1_smmu 0x1e&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sata0_smmu: iommu@e0200000 {</div><div class='add'>+			compatible = "arm,mmu-401";</div><div class='add'>+			reg = &lt;0 0xe0200000 0 0x10000&gt;;</div><div class='add'>+			#global-interrupts = &lt;1&gt;;</div><div class='add'>+			interrupts = &lt;0 332 4&gt;, &lt;0 332 4&gt;;</div><div class='add'>+			#iommu-cells = &lt;2&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sata1_smmu: iommu@e0c00000 {</div><div class='add'>+			compatible = "arm,mmu-401";</div><div class='add'>+			reg = &lt;0 0xe0c00000 0 0x10000&gt;;</div><div class='add'>+			#global-interrupts = &lt;1&gt;;</div><div class='add'>+			interrupts = &lt;0 331 4&gt;, &lt;0 331 4&gt;;</div><div class='add'>+			#iommu-cells = &lt;1&gt;;</div><div class='ctx'> 			dma-coherent;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -111,20 +121,18 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 			compatible = "arm,pl022", "arm,primecell";</div><div class='ctx'> 			reg = &lt;0 0xe1020000 0 0x1000&gt;;</div><div class='del'>-			spi-controller;</div><div class='ctx'> 			interrupts = &lt;0 330 4&gt;;</div><div class='del'>-			clocks = &lt;&amp;uartspiclk_100mhz&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='add'>+			clocks = &lt;&amp;uartspiclk_100mhz&gt;, &lt;&amp;uartspiclk_100mhz&gt;;</div><div class='add'>+			clock-names = "sspclk", "apb_pclk";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		spi1: spi@e1030000 {</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 			compatible = "arm,pl022", "arm,primecell";</div><div class='ctx'> 			reg = &lt;0 0xe1030000 0 0x1000&gt;;</div><div class='del'>-			spi-controller;</div><div class='ctx'> 			interrupts = &lt;0 329 4&gt;;</div><div class='del'>-			clocks = &lt;&amp;uartspiclk_100mhz&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='add'>+			clocks = &lt;&amp;uartspiclk_100mhz&gt;, &lt;&amp;uartspiclk_100mhz&gt;;</div><div class='add'>+			clock-names = "sspclk", "apb_pclk";</div><div class='ctx'> 			num-cs = &lt;1&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='hunk'>@@ -201,6 +209,10 @@</div><div class='ctx'> 			reg = &lt;0 0xe0100000 0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;0 3 4&gt;;</div><div class='ctx'> 			dma-coherent;</div><div class='add'>+			iommus = &lt;&amp;sata1_smmu 0x00&gt;,</div><div class='add'>+				 &lt;&amp;sata1_smmu 0x02&gt;,</div><div class='add'>+				 &lt;&amp;sata1_smmu 0x40&gt;,</div><div class='add'>+				 &lt;&amp;sata1_smmu 0x42&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		pcie0: pcie@f0000000 {</div><div class='hunk'>@@ -213,12 +225,22 @@</div><div class='ctx'> 			msi-parent = &lt;&amp;v2m0&gt;;</div><div class='ctx'> 			reg = &lt;0 0xf0000000 0 0x10000000&gt;;</div><div class='ctx'> </div><div class='del'>-			interrupt-map-mask = &lt;0xf800 0x0 0x0 0x7&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0xff00 0x0 0x0 0x7&gt;;</div><div class='ctx'> 			interrupt-map =</div><div class='del'>-				&lt;0x1000 0x0 0x0 0x1 &amp;gic0 0x0 0x0 0x0 0x120 0x1&gt;,</div><div class='del'>-				&lt;0x1000 0x0 0x0 0x2 &amp;gic0 0x0 0x0 0x0 0x121 0x1&gt;,</div><div class='del'>-				&lt;0x1000 0x0 0x0 0x3 &amp;gic0 0x0 0x0 0x0 0x122 0x1&gt;,</div><div class='del'>-				&lt;0x1000 0x0 0x0 0x4 &amp;gic0 0x0 0x0 0x0 0x123 0x1&gt;;</div><div class='add'>+				&lt;0x1100 0x0 0x0 0x1 &amp;gic0 0x0 0x0 0x0 0x120 0x1&gt;,</div><div class='add'>+				&lt;0x1100 0x0 0x0 0x2 &amp;gic0 0x0 0x0 0x0 0x121 0x1&gt;,</div><div class='add'>+				&lt;0x1100 0x0 0x0 0x3 &amp;gic0 0x0 0x0 0x0 0x122 0x1&gt;,</div><div class='add'>+				&lt;0x1100 0x0 0x0 0x4 &amp;gic0 0x0 0x0 0x0 0x123 0x1&gt;,</div><div class='add'>+</div><div class='add'>+				&lt;0x1200 0x0 0x0 0x1 &amp;gic0 0x0 0x0 0x0 0x124 0x1&gt;,</div><div class='add'>+				&lt;0x1200 0x0 0x0 0x2 &amp;gic0 0x0 0x0 0x0 0x125 0x1&gt;,</div><div class='add'>+				&lt;0x1200 0x0 0x0 0x3 &amp;gic0 0x0 0x0 0x0 0x126 0x1&gt;,</div><div class='add'>+				&lt;0x1200 0x0 0x0 0x4 &amp;gic0 0x0 0x0 0x0 0x127 0x1&gt;,</div><div class='add'>+</div><div class='add'>+				&lt;0x1300 0x0 0x0 0x1 &amp;gic0 0x0 0x0 0x0 0x128 0x1&gt;,</div><div class='add'>+				&lt;0x1300 0x0 0x0 0x2 &amp;gic0 0x0 0x0 0x0 0x129 0x1&gt;,</div><div class='add'>+				&lt;0x1300 0x0 0x0 0x3 &amp;gic0 0x0 0x0 0x0 0x12a 0x1&gt;,</div><div class='add'>+				&lt;0x1300 0x0 0x0 0x4 &amp;gic0 0x0 0x0 0x0 0x12b 0x1&gt;;</div><div class='ctx'> </div><div class='ctx'> 			dma-coherent;</div><div class='ctx'> 			dma-ranges = &lt;0x43000000 0x0 0x0 0x0 0x0 0x100 0x0&gt;;</div><div class='hunk'>@@ -227,8 +249,18 @@</div><div class='ctx'> 				&lt;0x01000000 0x00 0x00000000 0x00 0xefff0000 0x00 0x00010000&gt;,</div><div class='ctx'> 				/* 32-bit MMIO (size=2G) */</div><div class='ctx'> 				&lt;0x02000000 0x00 0x40000000 0x00 0x40000000 0x00 0x80000000&gt;,</div><div class='del'>-				/* 64-bit MMIO (size= 124G) */</div><div class='add'>+				/* 64-bit MMIO (size= 508G) */</div><div class='ctx'> 				&lt;0x03000000 0x01 0x00000000 0x01 0x00000000 0x7f 0x00000000&gt;;</div><div class='add'>+			iommu-map = &lt;0x0 &amp;pcie_smmu 0x0 0x10000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie_smmu: iommu@e0a00000 {</div><div class='add'>+			compatible = "arm,mmu-401";</div><div class='add'>+			reg = &lt;0 0xe0a00000 0 0x10000&gt;;</div><div class='add'>+			#global-interrupts = &lt;1&gt;;</div><div class='add'>+			interrupts = &lt;0 333 4&gt;, &lt;0 333 4&gt;;</div><div class='add'>+			#iommu-cells = &lt;1&gt;;</div><div class='add'>+			dma-coherent;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		/* Perf CCN504 PMU */</div><div class='head'>diff --git a/arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi b/arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi<br/>index d97498361ce3..18b0c2dd1b2d 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi</a></div><div class='hunk'>@@ -5,35 +5,7 @@</div><div class='ctx'>  * Copyright (C) 2015 Advanced Micro Devices, Inc.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-	xgmacclk0_dma_250mhz: clk250mhz_0 {</div><div class='del'>-		compatible = "fixed-clock";</div><div class='del'>-		#clock-cells = &lt;0&gt;;</div><div class='del'>-		clock-frequency = &lt;250000000&gt;;</div><div class='del'>-		clock-output-names = "xgmacclk0_dma_250mhz";</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	xgmacclk0_ptp_250mhz: clk250mhz_1 {</div><div class='del'>-		compatible = "fixed-clock";</div><div class='del'>-		#clock-cells = &lt;0&gt;;</div><div class='del'>-		clock-frequency = &lt;250000000&gt;;</div><div class='del'>-		clock-output-names = "xgmacclk0_ptp_250mhz";</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	xgmacclk1_dma_250mhz: clk250mhz_2 {</div><div class='del'>-		compatible = "fixed-clock";</div><div class='del'>-		#clock-cells = &lt;0&gt;;</div><div class='del'>-		clock-frequency = &lt;250000000&gt;;</div><div class='del'>-		clock-output-names = "xgmacclk1_dma_250mhz";</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	xgmacclk1_ptp_250mhz: clk250mhz_3 {</div><div class='del'>-		compatible = "fixed-clock";</div><div class='del'>-		#clock-cells = &lt;0&gt;;</div><div class='del'>-		clock-frequency = &lt;250000000&gt;;</div><div class='del'>-		clock-output-names = "xgmacclk1_ptp_250mhz";</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	xgmac0: xgmac@e0700000 {</div><div class='add'>+	xgmac0: ethernet@e0700000 {</div><div class='ctx'> 		compatible = "amd,xgbe-seattle-v1a";</div><div class='ctx'> 		reg = &lt;0 0xe0700000 0 0x80000&gt;,</div><div class='ctx'> 		      &lt;0 0xe0780000 0 0x80000&gt;,</div><div class='hunk'>@@ -55,11 +27,11 @@</div><div class='ctx'> 		clocks = &lt;&amp;xgmacclk0_dma_250mhz&gt;, &lt;&amp;xgmacclk0_ptp_250mhz&gt;;</div><div class='ctx'> 		clock-names = "dma_clk", "ptp_clk";</div><div class='ctx'> 		phy-mode = "xgmii";</div><div class='del'>-		#stream-id-cells = &lt;16&gt;;</div><div class='add'>+		iommus = &lt;&amp;xgmac0_smmu 0x00 0x17&gt;; /* 0-7, 16-23 */</div><div class='ctx'> 		dma-coherent;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	xgmac1: xgmac@e0900000 {</div><div class='add'>+	xgmac1: ethernet@e0900000 {</div><div class='ctx'> 		compatible = "amd,xgbe-seattle-v1a";</div><div class='ctx'> 		reg = &lt;0 0xe0900000 0 0x80000&gt;,</div><div class='ctx'> 		      &lt;0 0xe0980000 0 0x80000&gt;,</div><div class='hunk'>@@ -81,11 +53,11 @@</div><div class='ctx'> 		clocks = &lt;&amp;xgmacclk1_dma_250mhz&gt;, &lt;&amp;xgmacclk1_ptp_250mhz&gt;;</div><div class='ctx'> 		clock-names = "dma_clk", "ptp_clk";</div><div class='ctx'> 		phy-mode = "xgmii";</div><div class='del'>-		#stream-id-cells = &lt;16&gt;;</div><div class='add'>+		iommus = &lt;&amp;xgmac1_smmu 0x00 0x17&gt;; /* 0-7, 16-23 */</div><div class='ctx'> 		dma-coherent;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	xgmac0_smmu: smmu@e0600000 {</div><div class='add'>+	xgmac0_smmu: iommu@e0600000 {</div><div class='ctx'> 		 compatible = "arm,mmu-401";</div><div class='ctx'> 		 reg = &lt;0 0xe0600000 0 0x10000&gt;;</div><div class='ctx'> 		 #global-interrupts = &lt;1&gt;;</div><div class='hunk'>@@ -94,14 +66,11 @@</div><div class='ctx'> 			       */</div><div class='ctx'> 			      &lt;0 336 4&gt;,</div><div class='ctx'> 			      &lt;0 336 4&gt;;</div><div class='del'>-</div><div class='del'>-		 mmu-masters = &lt;&amp;xgmac0</div><div class='del'>-			  0  1  2  3  4  5  6  7</div><div class='del'>-			 16 17 18 19 20 21 22 23</div><div class='del'>-		 &gt;;</div><div class='add'>+		#iommu-cells = &lt;2&gt;;</div><div class='add'>+		dma-coherent;</div><div class='ctx'> 	 };</div><div class='ctx'> </div><div class='del'>-	 xgmac1_smmu: smmu@e0800000 {</div><div class='add'>+	 xgmac1_smmu: iommu@e0800000 {</div><div class='ctx'> 		 compatible = "arm,mmu-401";</div><div class='ctx'> 		 reg = &lt;0 0xe0800000 0 0x10000&gt;;</div><div class='ctx'> 		 #global-interrupts = &lt;1&gt;;</div><div class='hunk'>@@ -110,9 +79,6 @@</div><div class='ctx'> 			       */</div><div class='ctx'> 			      &lt;0 335 4&gt;,</div><div class='ctx'> 			      &lt;0 335 4&gt;;</div><div class='del'>-</div><div class='del'>-		 mmu-masters = &lt;&amp;xgmac1</div><div class='del'>-			  0  1  2  3  4  5  6  7</div><div class='del'>-			 16 17 18 19 20 21 22 23</div><div class='del'>-		 &gt;;</div><div class='add'>+		#iommu-cells = &lt;2&gt;;</div><div class='add'>+		dma-coherent;</div><div class='ctx'> 	 };</div><div class='head'>diff --git a/arch/arm64/boot/dts/amd/elba-16core.dtsi b/arch/arm64/boot/dts/amd/elba-16core.dtsi<br/>new file mode 100644<br/>index 000000000000..6c1b7b8fe354<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amd/elba-16core.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amd/elba-16core.dtsi</a></div><div class='hunk'>@@ -0,0 +1,197 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2020-2023 Advanced Micro Devices, Inc.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu-map {</div><div class='add'>+			cluster0 {</div><div class='add'>+				core0 { cpu = &lt;&amp;cpu0&gt;; };</div><div class='add'>+				core1 { cpu = &lt;&amp;cpu1&gt;; };</div><div class='add'>+				core2 { cpu = &lt;&amp;cpu2&gt;; };</div><div class='add'>+				core3 { cpu = &lt;&amp;cpu3&gt;; };</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cluster1 {</div><div class='add'>+				core0 { cpu = &lt;&amp;cpu4&gt;; };</div><div class='add'>+				core1 { cpu = &lt;&amp;cpu5&gt;; };</div><div class='add'>+				core2 { cpu = &lt;&amp;cpu6&gt;; };</div><div class='add'>+				core3 { cpu = &lt;&amp;cpu7&gt;; };</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cluster2 {</div><div class='add'>+				core0 { cpu = &lt;&amp;cpu8&gt;; };</div><div class='add'>+				core1 { cpu = &lt;&amp;cpu9&gt;; };</div><div class='add'>+				core2 { cpu = &lt;&amp;cpu10&gt;; };</div><div class='add'>+				core3 { cpu = &lt;&amp;cpu11&gt;; };</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cluster3 {</div><div class='add'>+				core0 { cpu = &lt;&amp;cpu12&gt;; };</div><div class='add'>+				core1 { cpu = &lt;&amp;cpu13&gt;; };</div><div class='add'>+				core2 { cpu = &lt;&amp;cpu14&gt;; };</div><div class='add'>+				core3 { cpu = &lt;&amp;cpu15&gt;; };</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* CLUSTER 0 */</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a72";</div><div class='add'>+			reg = &lt;0x0&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@1 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a72";</div><div class='add'>+			reg = &lt;0x1&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@2 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a72";</div><div class='add'>+			reg = &lt;0x2&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@3 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a72";</div><div class='add'>+			reg = &lt;0x3&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_0: l2-cache0 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* CLUSTER 1 */</div><div class='add'>+		cpu4: cpu@100 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a72";</div><div class='add'>+			reg = &lt;0x100&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_1&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu5: cpu@101 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a72";</div><div class='add'>+			reg = &lt;0x101&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_1&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu6: cpu@102 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a72";</div><div class='add'>+			reg = &lt;0x102&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_1&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu7: cpu@103 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a72";</div><div class='add'>+			reg = &lt;0x103&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_1&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_1: l2-cache1 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* CLUSTER 2 */</div><div class='add'>+		cpu8: cpu@200 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a72";</div><div class='add'>+			reg = &lt;0x200&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_2&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu9: cpu@201 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a72";</div><div class='add'>+			reg = &lt;0x201&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_2&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu10: cpu@202 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a72";</div><div class='add'>+			reg = &lt;0x202&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_2&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu11: cpu@203 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a72";</div><div class='add'>+			reg = &lt;0x203&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_2&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_2: l2-cache2 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* CLUSTER 3 */</div><div class='add'>+		cpu12: cpu@300 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a72";</div><div class='add'>+			reg = &lt;0x300&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_3&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu13: cpu@301 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a72";</div><div class='add'>+			reg = &lt;0x301&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_3&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu14: cpu@302 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a72";</div><div class='add'>+			reg = &lt;0x302&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_3&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu15: cpu@303 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a72";</div><div class='add'>+			reg = &lt;0x303&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_3&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_3: l2-cache3 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amd/elba-asic-common.dtsi b/arch/arm64/boot/dts/amd/elba-asic-common.dtsi<br/>new file mode 100644<br/>index 000000000000..d12e9a7b5587<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amd/elba-asic-common.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amd/elba-asic-common.dtsi</a></div><div class='hunk'>@@ -0,0 +1,70 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2020-2022 Advanced Micro Devices, Inc.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;ahb_clk {</div><div class='add'>+	clock-frequency = &lt;400000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;emmc_clk {</div><div class='add'>+	clock-frequency = &lt;200000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flash_clk {</div><div class='add'>+	clock-frequency = &lt;400000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ref_clk {</div><div class='add'>+	clock-frequency = &lt;156250000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qspi {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash0: flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;40000000&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;2&gt;;</div><div class='add'>+		m25p,fast-read;</div><div class='add'>+		cdns,read-delay = &lt;0&gt;;</div><div class='add'>+		cdns,tshsl-ns = &lt;0&gt;;</div><div class='add'>+		cdns,tsd2d-ns = &lt;0&gt;;</div><div class='add'>+		cdns,tchsh-ns = &lt;0&gt;;</div><div class='add'>+		cdns,tslch-ns = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;emmc {</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	cap-mmc-hw-reset;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdt0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	rtc@51 {</div><div class='add'>+		compatible = "nxp,pcf85263";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi0 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	num-cs = &lt;4&gt;;</div><div class='add'>+	cs-gpios = &lt;0&gt;, &lt;0&gt;, &lt;&amp;porta 1 GPIO_ACTIVE_LOW&gt;,</div><div class='add'>+		   &lt;&amp;porta 7 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amd/elba-asic.dts b/arch/arm64/boot/dts/amd/elba-asic.dts<br/>new file mode 100644<br/>index 000000000000..20b0fa0807a1<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amd/elba-asic.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amd/elba-asic.dts</a></div><div class='hunk'>@@ -0,0 +1,28 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)</div><div class='add'>+/*</div><div class='add'>+ * Device Tree file for AMD Pensando Elba Board.</div><div class='add'>+ *</div><div class='add'>+ * Copyright 2020-2022 Advanced Micro Devices, Inc.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "elba.dtsi"</div><div class='add'>+#include "elba-16core.dtsi"</div><div class='add'>+#include "elba-asic-common.dtsi"</div><div class='add'>+#include "elba-flash-parts.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "AMD Pensando Elba Board";</div><div class='add'>+	compatible = "amd,pensando-elba-ortano", "amd,pensando-elba";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+		spi0 = &amp;spi0;</div><div class='add'>+		spi1 = &amp;qspi;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi b/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi<br/>new file mode 100644<br/>index 000000000000..6ea2d777c8c9<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amd/elba-flash-parts.dtsi</a></div><div class='hunk'>@@ -0,0 +1,117 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2020-2023 Advanced Micro Devices, Inc.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;flash0 {</div><div class='add'>+	partitions {</div><div class='add'>+		compatible = "fixed-partitions";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		partition@0 {</div><div class='add'>+			label = "rsvd";</div><div class='add'>+			reg = &lt;0x0 0x10000&gt;;</div><div class='add'>+			read-only;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		partition@10000 {</div><div class='add'>+			label = "flash";</div><div class='add'>+			reg = &lt;0x10000 0xfff0000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		partition@f0000 {</div><div class='add'>+			label = "golduenv";</div><div class='add'>+			reg = &lt;0xf0000 0x10000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		partition@100000 {</div><div class='add'>+			label = "boot0";</div><div class='add'>+			reg = &lt;0x100000 0x80000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		partition@180000 {</div><div class='add'>+			label = "golduboot";</div><div class='add'>+			reg = &lt;0x180000 0x200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		partition@380000 {</div><div class='add'>+			label = "brdcfg0";</div><div class='add'>+			reg = &lt;0x380000 0x10000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		partition@390000 {</div><div class='add'>+			label = "brdcfg1";</div><div class='add'>+			reg = &lt;0x390000 0x10000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		partition@400000 {</div><div class='add'>+			label = "goldfw";</div><div class='add'>+			reg = &lt;0x400000 0x3c00000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		partition@4010000 {</div><div class='add'>+			label = "fwmap";</div><div class='add'>+			reg = &lt;0x4010000 0x20000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		partition@4030000 {</div><div class='add'>+			label = "fwsel";</div><div class='add'>+			reg = &lt;0x4030000 0x20000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		partition@4090000 {</div><div class='add'>+			label = "bootlog";</div><div class='add'>+			reg = &lt;0x4090000 0x20000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		partition@40b0000 {</div><div class='add'>+			label = "panicbuf";</div><div class='add'>+			reg = &lt;0x40b0000 0x20000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		partition@40d0000 {</div><div class='add'>+			label = "uservars";</div><div class='add'>+			reg = &lt;0x40d0000 0x20000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		partition@4200000 {</div><div class='add'>+			label = "uboota";</div><div class='add'>+			reg = &lt;0x4200000 0x400000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		partition@4600000 {</div><div class='add'>+			label = "ubootb";</div><div class='add'>+			reg = &lt;0x4600000 0x400000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		partition@4a00000 {</div><div class='add'>+			label = "mainfwa";</div><div class='add'>+			reg = &lt;0x4a00000 0x1000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		partition@5a00000 {</div><div class='add'>+			label = "mainfwb";</div><div class='add'>+			reg = &lt;0x5a00000 0x1000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		partition@6a00000 {</div><div class='add'>+			label = "diaguboot";</div><div class='add'>+			reg = &lt;0x6a00000 0x400000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		partition@6e00000 {</div><div class='add'>+			label = "spare";</div><div class='add'>+			reg = &lt;0x6e00000 0x1200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		partition@8000000 {</div><div class='add'>+			label = "diagfw";</div><div class='add'>+			reg = &lt;0x8000000 0x7fe0000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		partition@ffe0000 {</div><div class='add'>+			label = "ubootenv";</div><div class='add'>+			reg = &lt;0xffe0000 0x10000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amd/elba.dtsi b/arch/arm64/boot/dts/amd/elba.dtsi<br/>new file mode 100644<br/>index 000000000000..758bce0a0b2a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amd/elba.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amd/elba.dtsi</a></div><div class='hunk'>@@ -0,0 +1,191 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2020-2022 Advanced Micro Devices, Inc.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include "dt-bindings/interrupt-controller/arm-gic.h"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Elba ASIC Board";</div><div class='add'>+	compatible = "amd,pensando-elba";</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	dma-coherent;</div><div class='add'>+</div><div class='add'>+	ahb_clk: oscillator0 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	emmc_clk: oscillator2 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	flash_clk: oscillator3 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ref_clk: oscillator4 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-0.2";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu {</div><div class='add'>+		compatible = "arm,cortex-a72-pmu";</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc: soc {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		i2c0: i2c@400 {</div><div class='add'>+			compatible = "snps,designware-i2c";</div><div class='add'>+			reg = &lt;0x0 0x400 0x0 0x100&gt;;</div><div class='add'>+			clocks = &lt;&amp;ahb_clk&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			i2c-sda-hold-time-ns = &lt;480&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wdt0: watchdog@1400 {</div><div class='add'>+			compatible = "snps,dw-wdt";</div><div class='add'>+			reg = &lt;0x0 0x1400 0x0 0x100&gt;;</div><div class='add'>+			clocks = &lt;&amp;ahb_clk&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qspi: spi@2400 {</div><div class='add'>+			compatible = "amd,pensando-elba-qspi", "cdns,qspi-nor";</div><div class='add'>+			reg = &lt;0x0 0x2400 0x0 0x400&gt;,</div><div class='add'>+			      &lt;0x0 0x7fff0000 0x0 0x1000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;flash_clk&gt;;</div><div class='add'>+			cdns,fifo-depth = &lt;1024&gt;;</div><div class='add'>+			cdns,fifo-width = &lt;4&gt;;</div><div class='add'>+			cdns,trigger-address = &lt;0x7fff0000&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi0: spi@2800 {</div><div class='add'>+			compatible = "amd,pensando-elba-spi";</div><div class='add'>+			reg = &lt;0x0 0x2800 0x0 0x100&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			amd,pensando-elba-syscon = &lt;&amp;syscon&gt;;</div><div class='add'>+			clocks = &lt;&amp;ahb_clk&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			num-cs = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpio0: gpio@4000 {</div><div class='add'>+			compatible = "snps,dw-apb-gpio";</div><div class='add'>+			reg = &lt;0x0 0x4000 0x0 0x78&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			porta: gpio-port@0 {</div><div class='add'>+				compatible = "snps,dw-apb-gpio-port";</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+				ngpios = &lt;8&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+				#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			portb: gpio-port@1 {</div><div class='add'>+				compatible = "snps,dw-apb-gpio-port";</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+				ngpios = &lt;8&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart0: serial@4800 {</div><div class='add'>+			compatible = "ns16550a";</div><div class='add'>+			reg = &lt;0x0 0x4800 0x0 0x100&gt;;</div><div class='add'>+			clocks = &lt;&amp;ref_clk&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			reg-shift = &lt;2&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@800000 {</div><div class='add'>+			compatible = "arm,gic-v3";</div><div class='add'>+			reg = &lt;0x0 0x800000 0x0 0x200000&gt;,	/* GICD */</div><div class='add'>+			      &lt;0x0 0xa00000 0x0 0x200000&gt;,	/* GICR */</div><div class='add'>+			      &lt;0x0 0x60000000 0x0 0x2000&gt;,	/* GICC */</div><div class='add'>+			      &lt;0x0 0x60010000 0x0 0x1000&gt;,	/* GICH */</div><div class='add'>+			      &lt;0x0 0x60020000 0x0 0x2000&gt;;	/* GICV */</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			/*</div><div class='add'>+			 * Elba specific pre-ITS is enabled using the</div><div class='add'>+			 * existing property socionext,synquacer-pre-its</div><div class='add'>+			 */</div><div class='add'>+			gic_its: msi-controller@820000 {</div><div class='add'>+				compatible = "arm,gic-v3-its";</div><div class='add'>+				reg = &lt;0x0 0x820000 0x0 0x10000&gt;;</div><div class='add'>+				msi-controller;</div><div class='add'>+				#msi-cells = &lt;1&gt;;</div><div class='add'>+				socionext,synquacer-pre-its =</div><div class='add'>+							&lt;0xc00000 0x1000000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		emmc: mmc@30440000 {</div><div class='add'>+			compatible = "amd,pensando-elba-sd4hc", "cdns,sd4hc";</div><div class='add'>+			reg = &lt;0x0 0x30440000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0x30480044 0x0 0x4&gt;;	/* byte-lane ctrl */</div><div class='add'>+			clocks = &lt;&amp;emmc_clk&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			cdns,phy-input-delay-sd-highspeed = &lt;0x4&gt;;</div><div class='add'>+			cdns,phy-input-delay-legacy = &lt;0x4&gt;;</div><div class='add'>+			cdns,phy-input-delay-sd-uhs-sdr50 = &lt;0x6&gt;;</div><div class='add'>+			cdns,phy-input-delay-sd-uhs-ddr50 = &lt;0x16&gt;;</div><div class='add'>+			mmc-ddr-1_8v;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		syscon: syscon@307c0000 {</div><div class='add'>+			compatible = "amd,pensando-elba-syscon", "syscon";</div><div class='add'>+			reg = &lt;0x0 0x307c0000 0x0 0x3000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amd/husky.dts b/arch/arm64/boot/dts/amd/husky.dts<br/>deleted file mode 100644<br/>index 7acde34772cb..000000000000<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amd/husky.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amd/husky.dts</a><br/>+++ /dev/null</div><div class='hunk'>@@ -1,84 +0,0 @@</div><div class='del'>-// SPDX-License-Identifier: GPL-2.0</div><div class='del'>-/*</div><div class='del'>- * DTS file for AMD/Linaro 96Boards Enterprise Edition Server (Husky) Board</div><div class='del'>- * Note: Based-on AMD Seattle Rev.B0</div><div class='del'>- *</div><div class='del'>- * Copyright (C) 2015 Advanced Micro Devices, Inc.</div><div class='del'>- */</div><div class='del'>-</div><div class='del'>-/dts-v1/;</div><div class='del'>-</div><div class='del'>-/include/ "amd-seattle-soc.dtsi"</div><div class='del'>-</div><div class='del'>-/ {</div><div class='del'>-	model = "Linaro 96Boards Enterprise Edition Server (Husky) Board";</div><div class='del'>-	compatible = "amd,seattle-overdrive", "amd,seattle";</div><div class='del'>-</div><div class='del'>-	chosen {</div><div class='del'>-		stdout-path = &amp;serial0;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	psci {</div><div class='del'>-		compatible   = "arm,psci-0.2";</div><div class='del'>-		method       = "smc";</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;ccp0 {</div><div class='del'>-	status = "ok";</div><div class='del'>-	amd,zlib-support = &lt;1&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-/**</div><div class='del'>- * NOTE: In Rev.B, gpio0 is reserved.</div><div class='del'>- */</div><div class='del'>-&amp;gpio1 {</div><div class='del'>-	status = "ok";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;gpio2 {</div><div class='del'>-	status = "ok";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;gpio3 {</div><div class='del'>-	status = "ok";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;gpio4 {</div><div class='del'>-	status = "ok";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;i2c0 {</div><div class='del'>-	status = "ok";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;i2c1 {</div><div class='del'>-	status = "ok";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;pcie0 {</div><div class='del'>-	status = "ok";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;spi0 {</div><div class='del'>-	status = "ok";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;spi1 {</div><div class='del'>-	status = "ok";</div><div class='del'>-	sdcard0: sdcard@0 {</div><div class='del'>-		compatible = "mmc-spi-slot";</div><div class='del'>-		reg = &lt;0&gt;;</div><div class='del'>-		spi-max-frequency = &lt;20000000&gt;;</div><div class='del'>-		voltage-ranges = &lt;3200 3400&gt;;</div><div class='del'>-		pl022,hierarchy = &lt;0&gt;;</div><div class='del'>-		pl022,interface = &lt;0&gt;;</div><div class='del'>-		pl022,com-mode = &lt;0x0&gt;;</div><div class='del'>-		pl022,rx-level-trig = &lt;0&gt;;</div><div class='del'>-		pl022,tx-level-trig = &lt;0&gt;;</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;smb0 {</div><div class='del'>-	/include/ "amd-seattle-xgbe-b.dtsi"</div><div class='del'>-};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile<br/>index eef0045320f2..219fb088c704 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/Makefile?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/Makefile</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/Makefile</a></div><div class='hunk'>@@ -1,11 +1,43 @@</div><div class='ctx'> # SPDX-License-Identifier: GPL-2.0</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += amlogic-a4-a113l2-ba400.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += amlogic-a5-a113x2-av400.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += amlogic-c3-c302x-aw409.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += amlogic-c3-c308l-aw419.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += amlogic-s6-s905x5-bl209.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += amlogic-s7-s805x3-bp201.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += amlogic-s7d-s905x5m-bm202.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += amlogic-t7-a311d2-an400.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += amlogic-t7-a311d2-khadas-vim4.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-a1-ad401.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-a1-ad402.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-axg-jethome-jethub-j100.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-axg-jethome-jethub-j110-rev-2.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-axg-jethome-jethub-j110-rev-3.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MESON) += meson-axg-s400.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-g12a-fbx8am-brcm.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-g12a-fbx8am-realtek.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-g12a-radxa-zero.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MESON) += meson-g12a-sei510.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MESON) += meson-g12a-u200.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MESON) += meson-g12a-x96-max.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-g12b-a311d-bananapi-m2s.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MESON) += meson-g12b-a311d-khadas-vim3.dtb</div><div class='del'>-dtb-$(CONFIG_ARCH_MESON) += meson-g12b-s922x-khadas-vim3.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-g12b-a311d-khadas-vim3-ts050.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-g12b-bananapi-cm4-cm4io.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-g12b-bananapi-cm4-mnt-reform2.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-g12b-dreambox-one.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-g12b-dreambox-two.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gsking-x.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gtking-pro.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gtking.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-g12b-a311d-libretech-cc.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-go-ultra.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2-plus.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2l.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-g12b-radxa-zero2.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-g12b-s922x-bananapi-m2s.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-g12b-s922x-khadas-vim3.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MESON) += meson-g12b-ugoos-am6.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-kii-pro.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nanopi-k2.dtb</div><div class='hunk'>@@ -13,31 +45,62 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nexbox-a95x.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-odroidc2.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-p200.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-p201.dtb</div><div class='del'>-dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-pro.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-meta.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-pro.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-telos.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-wetek-hub.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-wetek-play2.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s805x-libretech-ac.dtb</div><div class='del'>-dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-hwacom-amazetv.dtb</div><div class='del'>-dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-khadas-vim.dtb</div><div class='del'>-dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-libretech-cc.dtb</div><div class='del'>-dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-nexbox-a95x.dtb</div><div class='del'>-dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s805x-p241.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s805y-xiaomi-aquaman.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-libretech-pc.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-mecool-kii-pro.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p230.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p231.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-phicomm-n1.dtb</div><div class='del'>-dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s805x-p241.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-sml5442tw.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-vero4k-plus.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-jethome-jethub-j80.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-p281.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-tx3-mini.dtb</div><div class='del'>-dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-libretech-pc.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-hwacom-amazetv.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-khadas-vim.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-libretech-cc-v2.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-libretech-cc.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-nexbox-a95x.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-vero4k.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-gxlx-s905l-p271.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-gxm-gt1-ultimate.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MESON) += meson-gxm-khadas-vim2.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-gxm-mecool-kiii-pro.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-gxm-minix-neo-u9h.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MESON) += meson-gxm-nexbox-a1.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q200.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q201.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MESON) += meson-gxm-rbox-pro.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MESON) += meson-gxm-s912-libretech-pc.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-gxm-tx9-pro.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-gxm-ugoos-am3.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MESON) += meson-gxm-vega-s96.dtb</div><div class='del'>-dtb-$(CONFIG_ARCH_MESON) += meson-sm1-sei610.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-gxm-wetek-core2.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-s4-s805x2-aq222.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-sm1-a95xf3-air-gbit.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-sm1-a95xf3-air.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-sm1-bananapi-m2-pro.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-sm1-bananapi-m5.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-sm1-h96-max.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MESON) += meson-sm1-khadas-vim3l.dtb</div><div class='del'>-dtb-$(CONFIG_ARCH_MESON) += meson-a1-ad401.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-sm1-khadas-vim3l-ts050.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-sm1-s905d3-libretech-cc.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-sm1-odroid-c4.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-sm1-odroid-hc4.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-sm1-sei610.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-sm1-x96-air-gbit.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MESON) += meson-sm1-x96-air.dtb</div><div class='add'>+</div><div class='add'>+# Overlays</div><div class='add'>+meson-g12a-fbx8am-brcm-dtbs	:= meson-g12a-fbx8am.dtb meson-g12a-fbx8am-brcm.dtbo</div><div class='add'>+meson-g12a-fbx8am-realtek-dtbs	:= meson-g12a-fbx8am.dtb meson-g12a-fbx8am-realtek.dtbo</div><div class='add'>+meson-g12b-a311d-khadas-vim3-ts050-dtbs := meson-g12b-a311d-khadas-vim3.dtb meson-khadas-vim3-ts050.dtbo</div><div class='add'>+meson-sm1-khadas-vim3l-ts050-dtbs	:= meson-sm1-khadas-vim3l.dtb meson-khadas-vim3-ts050.dtbo</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a4-a113l2-ba400.dts b/arch/arm64/boot/dts/amlogic/amlogic-a4-a113l2-ba400.dts<br/>new file mode 100644<br/>index 000000000000..ad3127e695d9<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/amlogic-a4-a113l2-ba400.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/amlogic-a4-a113l2-ba400.dts</a></div><div class='hunk'>@@ -0,0 +1,42 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2024 Amlogic, Inc. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "amlogic-a4.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Amlogic A113L2 ba400 Development Board";</div><div class='add'>+	compatible = "amlogic,ba400", "amlogic,a4";</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart_b;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x0 0x0 0x40000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		/* 10 MiB reserved for ARM Trusted Firmware */</div><div class='add'>+		secmon_reserved: secmon@5000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0x0 0x05000000 0x0 0xa00000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a4-common.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-a4-common.dtsi<br/>new file mode 100644<br/>index 000000000000..54d7a2d56ef6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/amlogic-a4-common.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/amlogic-a4-common.dtsi</a></div><div class='hunk'>@@ -0,0 +1,80 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2024 Amlogic, Inc. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+/ {</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-1.0";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	xtal: xtal-clk {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+		clock-output-names = "xtal";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@fff01000 {</div><div class='add'>+			compatible = "arm,gic-400";</div><div class='add'>+			reg = &lt;0x0 0xfff01000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0xfff02000 0 0x2000&gt;,</div><div class='add'>+			      &lt;0x0 0xfff04000 0 0x2000&gt;,</div><div class='add'>+			      &lt;0x0 0xfff06000 0 0x2000&gt;;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			#address-cells = &lt;0&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		apb: bus@fe000000 {</div><div class='add'>+			compatible = "simple-bus";</div><div class='add'>+			reg = &lt;0x0 0xfe000000 0x0 0x480000&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges = &lt;0x0 0x0 0x0 0xfe000000 0x0 0x480000&gt;;</div><div class='add'>+</div><div class='add'>+			watchdog@2100 {</div><div class='add'>+				compatible = "amlogic,a4-wdt", "amlogic,t7-wdt";</div><div class='add'>+				reg = &lt;0x0 0x2100 0x0 0x10&gt;;</div><div class='add'>+				clocks = &lt;&amp;xtal&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart_b: serial@7a000 {</div><div class='add'>+				compatible = "amlogic,a4-uart",</div><div class='add'>+					     "amlogic,meson-s4-uart";</div><div class='add'>+				reg = &lt;0x0 0x7a000 0x0 0x18&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 169 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				clocks = &lt;&amp;xtal&gt;, &lt;&amp;xtal&gt;, &lt;&amp;xtal&gt;;</div><div class='add'>+				clock-names = "xtal", "pclk", "baud";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sec_ao: ao-secure@10220 {</div><div class='add'>+				compatible = "amlogic,a4-ao-secure",</div><div class='add'>+					     "amlogic,meson-gx-ao-secure",</div><div class='add'>+					     "syscon";</div><div class='add'>+				reg = &lt;0x0 0x10220 0x0 0x140&gt;;</div><div class='add'>+				amlogic,has-chip-id;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a4-reset.h b/arch/arm64/boot/dts/amlogic/amlogic-a4-reset.h<br/>new file mode 100644<br/>index 000000000000..f6a4c90bab3c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/amlogic-a4-reset.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/amlogic-a4-reset.h</a></div><div class='hunk'>@@ -0,0 +1,93 @@</div><div class='add'>+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2024 Amlogic, Inc. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __DTS_AMLOGIC_A4_RESET_H</div><div class='add'>+#define __DTS_AMLOGIC_A4_RESET_H</div><div class='add'>+</div><div class='add'>+/* RESET0 */</div><div class='add'>+/*						0-3 */</div><div class='add'>+#define RESET_USB				4</div><div class='add'>+/*						5-6*/</div><div class='add'>+#define RESET_U2PHY22				7</div><div class='add'>+#define RESET_USBPHY20				8</div><div class='add'>+#define RESET_U2PHY21				9</div><div class='add'>+#define RESET_USB2DRD				10</div><div class='add'>+#define RESET_U2H				11</div><div class='add'>+#define RESET_LED_CTRL				12</div><div class='add'>+/*						13-31 */</div><div class='add'>+</div><div class='add'>+/* RESET1 */</div><div class='add'>+#define RESET_AUDIO				32</div><div class='add'>+#define RESET_AUDIO_VAD				33</div><div class='add'>+/*						34*/</div><div class='add'>+#define RESET_DDR_APB				35</div><div class='add'>+#define RESET_DDR				36</div><div class='add'>+#define RESET_VOUT_VENC				37</div><div class='add'>+#define RESET_VOUT				38</div><div class='add'>+/*						39-47 */</div><div class='add'>+#define RESET_ETHERNET				48</div><div class='add'>+/*						49-63 */</div><div class='add'>+</div><div class='add'>+/* RESET2 */</div><div class='add'>+#define RESET_DEVICE_MMC_ARB			64</div><div class='add'>+#define RESET_IRCTRL				65</div><div class='add'>+/*						66*/</div><div class='add'>+#define RESET_TS_PLL				67</div><div class='add'>+/*						68-72*/</div><div class='add'>+#define RESET_SPICC_0				73</div><div class='add'>+#define RESET_SPICC_1				74</div><div class='add'>+/*						75-79*/</div><div class='add'>+#define RESET_MSR_CLK				80</div><div class='add'>+/*						81*/</div><div class='add'>+#define RESET_SAR_ADC				82</div><div class='add'>+/*						83-87*/</div><div class='add'>+#define RESET_ACODEC				88</div><div class='add'>+/*						89-90*/</div><div class='add'>+#define RESET_WATCHDOG				91</div><div class='add'>+/*						92-95*/</div><div class='add'>+</div><div class='add'>+/* RESET3 */</div><div class='add'>+/*						96-127 */</div><div class='add'>+</div><div class='add'>+/* RESET4 */</div><div class='add'>+/*						128-131 */</div><div class='add'>+#define RESET_PWM_AB				132</div><div class='add'>+#define RESET_PWM_CD				133</div><div class='add'>+#define RESET_PWM_EF				134</div><div class='add'>+#define RESET_PWM_GH				135</div><div class='add'>+/*						136-137*/</div><div class='add'>+#define RESET_UART_A				138</div><div class='add'>+#define RESET_UART_B				139</div><div class='add'>+/*						140*/</div><div class='add'>+#define RESET_UART_D				141</div><div class='add'>+#define RESET_UART_E				142</div><div class='add'>+/*						143-144*/</div><div class='add'>+#define RESET_I2C_M_A				145</div><div class='add'>+#define RESET_I2C_M_B				146</div><div class='add'>+#define RESET_I2C_M_C				147</div><div class='add'>+#define RESET_I2C_M_D				148</div><div class='add'>+/*						149-151*/</div><div class='add'>+#define RESET_SDEMMC_A				152</div><div class='add'>+/*						153*/</div><div class='add'>+#define RESET_SDEMMC_C				154</div><div class='add'>+/*						155-159*/</div><div class='add'>+</div><div class='add'>+/* RESET5 */</div><div class='add'>+/*						160-175*/</div><div class='add'>+#define RESET_BRG_AO_NIC_SYS			176</div><div class='add'>+/*						177*/</div><div class='add'>+#define RESET_BRG_AO_NIC_MAIN			178</div><div class='add'>+#define RESET_BRG_AO_NIC_AUDIO			179</div><div class='add'>+/*						180-183*/</div><div class='add'>+#define RESET_BRG_AO_NIC_ALL			184</div><div class='add'>+/*						185*/</div><div class='add'>+#define RESET_BRG_NIC_SDIO			186</div><div class='add'>+#define RESET_BRG_NIC_EMMC			187</div><div class='add'>+#define RESET_BRG_NIC_DSU			188</div><div class='add'>+#define RESET_BRG_NIC_CLK81			189</div><div class='add'>+#define RESET_BRG_NIC_MAIN			190</div><div class='add'>+#define RESET_BRG_NIC_ALL			191</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi<br/>new file mode 100644<br/>index 000000000000..fce45933fa28<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi</a></div><div class='hunk'>@@ -0,0 +1,241 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2024 Amlogic, Inc. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "amlogic-a4-common.dtsi"</div><div class='add'>+#include "amlogic-a4-reset.h"</div><div class='add'>+#include &lt;dt-bindings/power/amlogic,a4-pwrc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/amlogic,pinctrl.h&gt;</div><div class='add'>+/ {</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x0 0x0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			d-cache-line-size = &lt;32&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-sets = &lt;32&gt;;</div><div class='add'>+			i-cache-line-size = &lt;32&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-sets = &lt;32&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@1 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x0 0x1&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			d-cache-line-size = &lt;32&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-sets = &lt;32&gt;;</div><div class='add'>+			i-cache-line-size = &lt;32&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-sets = &lt;32&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@2 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x0 0x2&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			d-cache-line-size = &lt;32&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-sets = &lt;32&gt;;</div><div class='add'>+			i-cache-line-size = &lt;32&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-sets = &lt;32&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@3 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x0 0x3&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			d-cache-line-size = &lt;32&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-sets = &lt;32&gt;;</div><div class='add'>+			i-cache-line-size = &lt;32&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-sets = &lt;32&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2: l2-cache0 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x80000&gt;; /* L2. 512 KB */</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;512&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sm: secure-monitor {</div><div class='add'>+		compatible = "amlogic,meson-gxbb-sm";</div><div class='add'>+</div><div class='add'>+		pwrc: power-controller {</div><div class='add'>+			compatible = "amlogic,a4-pwrc";</div><div class='add'>+			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;apb {</div><div class='add'>+	reset: reset-controller@2000 {</div><div class='add'>+		compatible = "amlogic,a4-reset",</div><div class='add'>+			     "amlogic,meson-s4-reset";</div><div class='add'>+		reg = &lt;0x0 0x2000 0x0 0x98&gt;;</div><div class='add'>+		#reset-cells = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	periphs_pinctrl: pinctrl@4000 {</div><div class='add'>+		compatible = "amlogic,pinctrl-a4";</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges = &lt;0x0 0x0 0x0 0x4000 0x0 0x280&gt;;</div><div class='add'>+</div><div class='add'>+		gpiox: gpio@100 {</div><div class='add'>+			reg = &lt;0 0x100 0 0x40&gt;, &lt;0 0xc 0 0xc&gt;;</div><div class='add'>+			reg-names = "gpio", "mux";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;periphs_pinctrl 0 (AMLOGIC_GPIO_X&lt;&lt;8) 18&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpiot: gpio@140 {</div><div class='add'>+			reg = &lt;0 0x140 0 0x40&gt;, &lt;0 0x2c 0 0xc&gt;;</div><div class='add'>+			reg-names = "gpio", "mux";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;periphs_pinctrl 0 (AMLOGIC_GPIO_T&lt;&lt;8) 23&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpiod: gpio@180 {</div><div class='add'>+			reg = &lt;0 0x180 0 0x40&gt;, &lt;0 0x40 0 0x8&gt;;</div><div class='add'>+			reg-names = "gpio", "mux";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;periphs_pinctrl 0 (AMLOGIC_GPIO_D&lt;&lt;8) 16&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpioe: gpio@1c0 {</div><div class='add'>+			reg = &lt;0 0x1c0 0 0x40&gt;, &lt;0 0x48 0 0x4&gt;;</div><div class='add'>+			reg-names = "gpio", "mux";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;periphs_pinctrl 0 (AMLOGIC_GPIO_E&lt;&lt;8) 2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpiob: gpio@240 {</div><div class='add'>+			reg = &lt;0 0x240 0 0x40&gt;, &lt;0 0 0 0x8&gt;;</div><div class='add'>+			reg-names = "gpio", "mux";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;periphs_pinctrl 0 (AMLOGIC_GPIO_B&lt;&lt;8) 14&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		func-uart-a {</div><div class='add'>+			uart_a_default: group-uart-a-pins1 {</div><div class='add'>+				pinmux = &lt;AML_PINMUX(AMLOGIC_GPIO_X, 11, 1)&gt;,</div><div class='add'>+					 &lt;AML_PINMUX(AMLOGIC_GPIO_X, 12, 1)&gt;,</div><div class='add'>+					 &lt;AML_PINMUX(AMLOGIC_GPIO_X, 13, 1)&gt;,</div><div class='add'>+					 &lt;AML_PINMUX(AMLOGIC_GPIO_X, 14, 1)&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			group-uart-a-pins2 {</div><div class='add'>+				pinmux = &lt;AML_PINMUX(AMLOGIC_GPIO_D, 2, 3)&gt;,</div><div class='add'>+					 &lt;AML_PINMUX(AMLOGIC_GPIO_D, 3, 3)&gt;;</div><div class='add'>+				bias-pull-up;</div><div class='add'>+				drive-strength-microamp = &lt;4000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		func-uart-b {</div><div class='add'>+			uart_b_default: group-uart-b-pins {</div><div class='add'>+				pinmux = &lt;AML_PINMUX(AMLOGIC_GPIO_E, 0, 3)&gt;,</div><div class='add'>+					 &lt;AML_PINMUX(AMLOGIC_GPIO_E, 1, 3)&gt;;</div><div class='add'>+				bias-pull-up;</div><div class='add'>+				drive-strength-microamp = &lt;4000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		func-uart-d {</div><div class='add'>+			uart_d_default: group-uart-d-pins1 {</div><div class='add'>+				pinmux = &lt;AML_PINMUX(AMLOGIC_GPIO_T, 18, 4)&gt;,</div><div class='add'>+					 &lt;AML_PINMUX(AMLOGIC_GPIO_T, 19, 4)&gt;;</div><div class='add'>+				bias-pull-up;</div><div class='add'>+				drive-strength-microamp = &lt;4000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			group-uart-d-pins2 {</div><div class='add'>+				pinmux = &lt;AML_PINMUX(AMLOGIC_GPIO_T, 7, 2)&gt;,</div><div class='add'>+					 &lt;AML_PINMUX(AMLOGIC_GPIO_T, 8, 2)&gt;,</div><div class='add'>+					 &lt;AML_PINMUX(AMLOGIC_GPIO_T, 9, 2)&gt;,</div><div class='add'>+					 &lt;AML_PINMUX(AMLOGIC_GPIO_T, 10, 2)&gt;;</div><div class='add'>+				bias-pull-up;</div><div class='add'>+				drive-strength-microamp = &lt;4000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		func-uart-e {</div><div class='add'>+			uart_e_default: group-uart-e-pins {</div><div class='add'>+				pinmux = &lt;AML_PINMUX(AMLOGIC_GPIO_T, 14, 3)&gt;,</div><div class='add'>+					 &lt;AML_PINMUX(AMLOGIC_GPIO_T, 15, 3)&gt;,</div><div class='add'>+					 &lt;AML_PINMUX(AMLOGIC_GPIO_T, 16, 3)&gt;,</div><div class='add'>+					 &lt;AML_PINMUX(AMLOGIC_GPIO_T, 17, 3)&gt;;</div><div class='add'>+				bias-pull-up;</div><div class='add'>+				drive-strength-microamp = &lt;4000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio_intc: interrupt-controller@4080 {</div><div class='add'>+		compatible = "amlogic,a4-gpio-intc",</div><div class='add'>+			     "amlogic,meson-gpio-intc";</div><div class='add'>+		reg = &lt;0x0 0x4080 0x0 0x20&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		amlogic,channel-interrupts =</div><div class='add'>+			&lt;10 11 12 13 14 15 16 17 18 19 20 21&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ao_pinctrl: pinctrl@8e700 {</div><div class='add'>+		compatible = "amlogic,pinctrl-a4";</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges = &lt;0x0 0x0 0x0 0x8e700 0x0 0x80&gt;;</div><div class='add'>+</div><div class='add'>+		gpioao: gpio@4 {</div><div class='add'>+			reg = &lt;0 0x4 0 0x16&gt;, &lt;0 0 0 0x4&gt;;</div><div class='add'>+			reg-names = "gpio", "mux";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;periphs_pinctrl 0 (AMLOGIC_GPIO_AO&lt;&lt;8) 7&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		test_n: gpio@44 {</div><div class='add'>+			reg = &lt;0 0x44 0 0x20&gt;;</div><div class='add'>+			reg-names = "gpio";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;periphs_pinctrl 0 (AMLOGIC_GPIO_TEST_N&lt;&lt;8) 1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio_ao_intc: interrupt-controller@8e72c {</div><div class='add'>+		compatible = "amlogic,a4-gpio-ao-intc",</div><div class='add'>+			     "amlogic,meson-gpio-intc";</div><div class='add'>+		reg = &lt;0x0 0x8e72c 0x0 0x0c&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		amlogic,channel-interrupts = &lt;140 141&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a5-a113x2-av400.dts b/arch/arm64/boot/dts/amlogic/amlogic-a5-a113x2-av400.dts<br/>new file mode 100644<br/>index 000000000000..11d8b88c1ce5<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/amlogic-a5-a113x2-av400.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/amlogic-a5-a113x2-av400.dts</a></div><div class='hunk'>@@ -0,0 +1,42 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2024 Amlogic, Inc. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "amlogic-a5.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Amlogic A113X2 av400 Development Board";</div><div class='add'>+	compatible = "amlogic,av400", "amlogic,a5";</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart_b;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x0 0x0 0x40000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		/* 10 MiB reserved for ARM Trusted Firmware */</div><div class='add'>+		secmon_reserved: secmon@5000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0x0 0x05000000 0x0 0xa00000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a5-reset.h b/arch/arm64/boot/dts/amlogic/amlogic-a5-reset.h<br/>new file mode 100644<br/>index 000000000000..cdf0f5159620<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/amlogic-a5-reset.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/amlogic-a5-reset.h</a></div><div class='hunk'>@@ -0,0 +1,95 @@</div><div class='add'>+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2024 Amlogic, Inc. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __DTS_AMLOGIC_A5_RESET_H</div><div class='add'>+#define __DTS_AMLOGIC_A5_RESET_H</div><div class='add'>+</div><div class='add'>+/* RESET0 */</div><div class='add'>+/*						0-3 */</div><div class='add'>+#define RESET_USB				4</div><div class='add'>+/*						5-7 */</div><div class='add'>+#define RESET_USBPHY20				8</div><div class='add'>+/*						9 */</div><div class='add'>+#define RESET_USB2DRD				10</div><div class='add'>+/*						11-31 */</div><div class='add'>+</div><div class='add'>+/* RESET1 */</div><div class='add'>+#define RESET_AUDIO				32</div><div class='add'>+#define RESET_AUDIO_VAD				33</div><div class='add'>+/*                                              34 */</div><div class='add'>+#define RESET_DDR_APB				35</div><div class='add'>+#define RESET_DDR				36</div><div class='add'>+/*						37-40 */</div><div class='add'>+#define RESET_DSPA_DEBUG			41</div><div class='add'>+/*                                              42 */</div><div class='add'>+#define RESET_DSPA				43</div><div class='add'>+/*						44-46 */</div><div class='add'>+#define RESET_NNA				47</div><div class='add'>+#define RESET_ETHERNET				48</div><div class='add'>+/*						49-63 */</div><div class='add'>+</div><div class='add'>+/* RESET2 */</div><div class='add'>+#define RESET_ABUS_ARB				64</div><div class='add'>+#define RESET_IRCTRL				65</div><div class='add'>+/*						66 */</div><div class='add'>+#define RESET_TS_PLL				67</div><div class='add'>+/*						68-72 */</div><div class='add'>+#define RESET_SPICC_0				73</div><div class='add'>+#define RESET_SPICC_1				74</div><div class='add'>+#define RESET_RSA				75</div><div class='add'>+</div><div class='add'>+/*						76-79 */</div><div class='add'>+#define RESET_MSR_CLK				80</div><div class='add'>+#define RESET_SPIFC				81</div><div class='add'>+#define RESET_SAR_ADC				82</div><div class='add'>+/*						83-90 */</div><div class='add'>+#define RESET_WATCHDOG				91</div><div class='add'>+/*						92-95 */</div><div class='add'>+</div><div class='add'>+/* RESET3 */</div><div class='add'>+/*						96-127 */</div><div class='add'>+</div><div class='add'>+/* RESET4 */</div><div class='add'>+#define RESET_RTC				128</div><div class='add'>+/*						129-131 */</div><div class='add'>+#define RESET_PWM_AB				132</div><div class='add'>+#define RESET_PWM_CD				133</div><div class='add'>+#define RESET_PWM_EF				134</div><div class='add'>+#define RESET_PWM_GH				135</div><div class='add'>+/*						104-105 */</div><div class='add'>+#define RESET_UART_A				138</div><div class='add'>+#define RESET_UART_B				139</div><div class='add'>+#define RESET_UART_C				140</div><div class='add'>+#define RESET_UART_D				141</div><div class='add'>+#define RESET_UART_E				142</div><div class='add'>+/*						143*/</div><div class='add'>+#define RESET_I2C_S_A				144</div><div class='add'>+#define RESET_I2C_M_A				145</div><div class='add'>+#define RESET_I2C_M_B				146</div><div class='add'>+#define RESET_I2C_M_C				147</div><div class='add'>+#define RESET_I2C_M_D				148</div><div class='add'>+/*						149-151 */</div><div class='add'>+#define RESET_SDEMMC_A				152</div><div class='add'>+/*						153 */</div><div class='add'>+#define RESET_SDEMMC_C				154</div><div class='add'>+/*						155-159*/</div><div class='add'>+</div><div class='add'>+/* RESET5 */</div><div class='add'>+/*						160-175 */</div><div class='add'>+#define RESET_BRG_AO_NIC_SYS			176</div><div class='add'>+#define RESET_BRG_AO_NIC_DSPA			177</div><div class='add'>+#define RESET_BRG_AO_NIC_MAIN			178</div><div class='add'>+#define RESET_BRG_AO_NIC_AUDIO			179</div><div class='add'>+/*						180-183 */</div><div class='add'>+#define RESET_BRG_AO_NIC_ALL			184</div><div class='add'>+#define RESET_BRG_NIC_NNA			185</div><div class='add'>+#define RESET_BRG_NIC_SDIO			186</div><div class='add'>+#define RESET_BRG_NIC_EMMC			187</div><div class='add'>+#define RESET_BRG_NIC_DSU			188</div><div class='add'>+#define RESET_BRG_NIC_SYSCLK			189</div><div class='add'>+#define RESET_BRG_NIC_MAIN			190</div><div class='add'>+#define RESET_BRG_NIC_ALL			191</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi<br/>new file mode 100644<br/>index 000000000000..2b12d8284594<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi</a></div><div class='hunk'>@@ -0,0 +1,160 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2024 Amlogic, Inc. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "amlogic-a4-common.dtsi"</div><div class='add'>+#include "amlogic-a5-reset.h"</div><div class='add'>+#include &lt;dt-bindings/pinctrl/amlogic,pinctrl.h&gt;</div><div class='add'>+#include &lt;dt-bindings/power/amlogic,a5-pwrc.h&gt;</div><div class='add'>+/ {</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x0 0x0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@100 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x0 0x100&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@200 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x0 0x200&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@300 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x0 0x300&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sm: secure-monitor {</div><div class='add'>+		compatible = "amlogic,meson-gxbb-sm";</div><div class='add'>+</div><div class='add'>+		pwrc: power-controller {</div><div class='add'>+			compatible = "amlogic,a5-pwrc";</div><div class='add'>+			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;apb {</div><div class='add'>+	reset: reset-controller@2000 {</div><div class='add'>+		compatible = "amlogic,a5-reset",</div><div class='add'>+			     "amlogic,meson-s4-reset";</div><div class='add'>+		reg = &lt;0x0 0x2000 0x0 0x98&gt;;</div><div class='add'>+		#reset-cells = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	periphs_pinctrl: pinctrl@4000 {</div><div class='add'>+		compatible = "amlogic,pinctrl-a5",</div><div class='add'>+			     "amlogic,pinctrl-a4";</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges = &lt;0x0 0x0 0x0 0x4000 0x0 0x300&gt;;</div><div class='add'>+</div><div class='add'>+		gpioz: gpio@c0 {</div><div class='add'>+			reg = &lt;0x0 0xc0 0x0 0x40&gt;,</div><div class='add'>+			      &lt;0x0 0x18 0x0 0x8&gt;;</div><div class='add'>+			reg-names = "gpio", "mux";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;periphs_pinctrl 0 (AMLOGIC_GPIO_Z&lt;&lt;8) 16&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpiox: gpio@100 {</div><div class='add'>+			reg = &lt;0x0 0x100 0x0 0x40&gt;,</div><div class='add'>+			      &lt;0x0 0xc   0x0 0xc&gt;;</div><div class='add'>+			reg-names = "gpio", "mux";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;periphs_pinctrl 0 (AMLOGIC_GPIO_X&lt;&lt;8) 20&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpiot: gpio@140 {</div><div class='add'>+			reg = &lt;0x0 0x140 0x0 0x40&gt;,</div><div class='add'>+			      &lt;0x0 0x2c  0x0 0x8&gt;;</div><div class='add'>+			reg-names = "gpio", "mux";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;periphs_pinctrl 0 (AMLOGIC_GPIO_T&lt;&lt;8) 14&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpiod: gpio@180 {</div><div class='add'>+			reg = &lt;0x0 0x180 0x0 0x40&gt;,</div><div class='add'>+			      &lt;0x0 0x40  0x0 0x8&gt;;</div><div class='add'>+			reg-names = "gpio", "mux";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;periphs_pinctrl 0 (AMLOGIC_GPIO_D&lt;&lt;8) 16&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpioe: gpio@1c0 {</div><div class='add'>+			reg = &lt;0x0 0x1c0 0x0 0x40&gt;,</div><div class='add'>+			      &lt;0x0 0x48  0x0 0x4&gt;;</div><div class='add'>+			reg-names = "gpio", "mux";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;periphs_pinctrl 0 (AMLOGIC_GPIO_E&lt;&lt;8) 2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpioc: gpio@200 {</div><div class='add'>+			reg = &lt;0x0 0x200 0x0 0x40&gt;,</div><div class='add'>+			      &lt;0x0 0x24  0x0 0x8&gt;;</div><div class='add'>+			reg-names = "gpio", "mux";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;periphs_pinctrl 0 (AMLOGIC_GPIO_C&lt;&lt;8) 11&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpiob: gpio@240 {</div><div class='add'>+			reg = &lt;0x0 0x240 0x0 0x40&gt;,</div><div class='add'>+			      &lt;0x0 0x0   0x0 0x8&gt;;</div><div class='add'>+			reg-names = "gpio", "mux";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;periphs_pinctrl 0 (AMLOGIC_GPIO_B&lt;&lt;8) 14&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpioh: gpio@280 {</div><div class='add'>+			reg = &lt;0x0 0x280 0x0 0x40&gt;,</div><div class='add'>+			      &lt;0x0 0x4c  0x0 0x4&gt;;</div><div class='add'>+			reg-names = "gpio", "mux";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;periphs_pinctrl 0 (AMLOGIC_GPIO_H&lt;&lt;8) 5&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpio_test_n: gpio@2c0 {</div><div class='add'>+			reg = &lt;0x0 0x2c0 0x0 0x40&gt;,</div><div class='add'>+			      &lt;0x0 0x3c  0x0 0x4&gt;;</div><div class='add'>+			reg-names = "gpio", "mux";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;periphs_pinctrl 0 (AMLOGIC_GPIO_TEST_N&lt;&lt;8) 1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio_intc: interrupt-controller@4080 {</div><div class='add'>+		compatible = "amlogic,a5-gpio-intc",</div><div class='add'>+			     "amlogic,meson-gpio-intc";</div><div class='add'>+		reg = &lt;0x0 0x4080 0x0 0x20&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		amlogic,channel-interrupts =</div><div class='add'>+			&lt;10 11 12 13 14 15 16 17 18 19 20 21&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/amlogic-c3-c302x-aw409.dts b/arch/arm64/boot/dts/amlogic/amlogic-c3-c302x-aw409.dts<br/>new file mode 100644<br/>index 000000000000..a6736ad2a648<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/amlogic-c3-c302x-aw409.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/amlogic-c3-c302x-aw409.dts</a></div><div class='hunk'>@@ -0,0 +1,260 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2021 Amlogic, Inc. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "amlogic-c3.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Amlogic C302 aw409 Development Board";</div><div class='add'>+	compatible = "amlogic,aw409", "amlogic,c3";</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart_b;</div><div class='add'>+		spi0 = &amp;spifc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x0 0x0 0x10000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		/* 9 MiB reserved for ARM Trusted Firmware */</div><div class='add'>+		secmon_reserved: secmon@7f00000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0x0 0x07f00000 0x0 0x900000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	main_12v: regulator-main-12v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "12V";</div><div class='add'>+		regulator-min-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vcc_5v: regulator-vcc-5v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCC5V";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;main_12v&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddq: regulator-vddq {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDQ";</div><div class='add'>+		regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;main_12v&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddao_3v3: regulator-vddao-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDAO3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;main_12v&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddao_1v8: regulator-vddao-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDAO1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ddr4_2v5: regulator-ddr4-2v5 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "DDR4_2V5";</div><div class='add'>+		regulator-min-microvolt = &lt;2500000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;2500000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vcc_3v3: regulator-vcc-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCC3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vcc_1v8: regulator-vcc-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCC1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vcc_3v3&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_1v8: regulator-vdd-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD1V8_BOOT";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vcc_3v3&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddio_b: regulator-vddio-3v3-b {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDIO_B";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vcc_3v3&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdcard: regulator-sdcard {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "SDCARD_POWER";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio GPIOA_4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;nand {</div><div class='add'>+	status = "okay";</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl-0 = &lt;&amp;nand_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	nand@0 {</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		nand-on-flash-bbt;</div><div class='add'>+</div><div class='add'>+		partition@0 {</div><div class='add'>+			label = "boot";</div><div class='add'>+			reg = &lt;0x0 0x00200000&gt;;</div><div class='add'>+		};</div><div class='add'>+		partition@200000 {</div><div class='add'>+			label = "env";</div><div class='add'>+			reg = &lt;0x00200000 0x00400000&gt;;</div><div class='add'>+		};</div><div class='add'>+		partition@600000 {</div><div class='add'>+			label = "system";</div><div class='add'>+			reg = &lt;0x00600000 0x00a00000&gt;;</div><div class='add'>+		};</div><div class='add'>+		partition@1000000 {</div><div class='add'>+			label = "rootfs";</div><div class='add'>+			reg = &lt;0x01000000 0x03000000&gt;;</div><div class='add'>+		};</div><div class='add'>+		partition@4000000 {</div><div class='add'>+			label = "media";</div><div class='add'>+			reg = &lt;0x04000000 0x8000000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethmac {</div><div class='add'>+	status = "okay";</div><div class='add'>+	phy-handle = &lt;&amp;internal_ephy&gt;;</div><div class='add'>+	phy-mode = "rmii";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spifc {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl-0 = &lt;&amp;spifc_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	nand@0 {</div><div class='add'>+		compatible = "spi-nand";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;83000000&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;4&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+</div><div class='add'>+		partitions {</div><div class='add'>+			compatible = "fixed-partitions";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			partition@0 {</div><div class='add'>+				label = "boot";</div><div class='add'>+				reg = &lt;0 0x200000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			partition@200000 {</div><div class='add'>+				label = "env";</div><div class='add'>+				reg = &lt;0x200000 0x400000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			partition@600000 {</div><div class='add'>+				label = "system";</div><div class='add'>+				reg = &lt;0x600000 0xa00000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			partition@1000000 {</div><div class='add'>+				label = "rootfs";</div><div class='add'>+				reg = &lt;0x1000000 0x3000000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			partition@4000000 {</div><div class='add'>+				label = "data";</div><div class='add'>+				reg = &lt;0x4000000 0x8000000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sd {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdcard_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;sdcard_clk_gate_pins&gt;;</div><div class='add'>+	pinctrl-names = "default","clk-gate";</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	max-frequency = &lt;50000000&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+</div><div class='add'>+	cd-gpios = &lt;&amp;gpio GPIOC_6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;sdcard&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;sdcard&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/amlogic-c3-c308l-aw419.dts b/arch/arm64/boot/dts/amlogic/amlogic-c3-c308l-aw419.dts<br/>new file mode 100644<br/>index 000000000000..e026604c55e6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/amlogic-c3-c308l-aw419.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/amlogic-c3-c308l-aw419.dts</a></div><div class='hunk'>@@ -0,0 +1,344 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2024 Amlogic, Inc. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "amlogic-c3.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Amlogic C308l aw419 Development Board";</div><div class='add'>+	compatible = "amlogic,aw419", "amlogic,c3";</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart_b;</div><div class='add'>+		spi0 = &amp;spifc;</div><div class='add'>+		i2c2 = &amp;i2c2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x0 0x0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		/* 9 MiB reserved for ARM Trusted Firmware */</div><div class='add'>+		secmon_reserved: secmon@7f00000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0x0 0x07f00000 0x0 0x900000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	main_12v: regulator-main-12v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "12V";</div><div class='add'>+		regulator-min-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vcc_5v: regulator-vcc-5v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCC5V";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;main_12v&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddq: regulator-vddq {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDQ";</div><div class='add'>+		regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;main_12v&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddao_3v3: regulator-vddao-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDAO3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;main_12v&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddao_1v8: regulator-vddao-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDAO1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ddr4_2v5: regulator-ddr4-2v5 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "DDR4_2V5";</div><div class='add'>+		regulator-min-microvolt = &lt;2500000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;2500000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vcc_3v3: regulator-vcc-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCC3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vcc_1v8: regulator-vcc-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCC1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vcc_3v3&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_1v8: regulator-vdd-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD1V8_BOOT";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vcc_3v3&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddio_b: regulator-vddio-3v3-b {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDIO_B";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vcc_3v3&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdcard: regulator-sdcard {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "SDCARD_POWER";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio GPIOA_4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	camera_vdddo_1v8: regulator-camera-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "CAMERA_VDDDO";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vcc_3v3&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	camera_vdda_2v9: regulator-camera-2v9 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "CAMERA_VDDA";</div><div class='add'>+		regulator-min-microvolt = &lt;2900000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;2900000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vcc_5v&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	camera_vddd_1v2: regulator-camera-1v2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "CAMERA_VDDD";</div><div class='add'>+		regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vcc_3v3&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;nand {</div><div class='add'>+	status = "okay";</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl-0 = &lt;&amp;nand_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	nand@0 {</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		nand-on-flash-bbt;</div><div class='add'>+</div><div class='add'>+		partition@0 {</div><div class='add'>+			label = "boot";</div><div class='add'>+			reg = &lt;0x0 0x00200000&gt;;</div><div class='add'>+		};</div><div class='add'>+		partition@200000 {</div><div class='add'>+			label = "env";</div><div class='add'>+			reg = &lt;0x00200000 0x00400000&gt;;</div><div class='add'>+		};</div><div class='add'>+		partition@600000 {</div><div class='add'>+			label = "system";</div><div class='add'>+			reg = &lt;0x00600000 0x00a00000&gt;;</div><div class='add'>+		};</div><div class='add'>+		partition@1000000 {</div><div class='add'>+			label = "rootfs";</div><div class='add'>+			reg = &lt;0x01000000 0x03000000&gt;;</div><div class='add'>+		};</div><div class='add'>+		partition@4000000 {</div><div class='add'>+			label = "media";</div><div class='add'>+			reg = &lt;0x04000000 0x8000000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethmac {</div><div class='add'>+	status = "okay";</div><div class='add'>+	phy-handle = &lt;&amp;internal_ephy&gt;;</div><div class='add'>+	phy-mode = "rmii";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spifc {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl-0 = &lt;&amp;spifc_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	nand@0 {</div><div class='add'>+		compatible = "spi-nand";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;83000000&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;4&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+</div><div class='add'>+		partitions {</div><div class='add'>+			compatible = "fixed-partitions";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			partition@0 {</div><div class='add'>+				label = "boot";</div><div class='add'>+				reg = &lt;0 0x200000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			partition@200000 {</div><div class='add'>+				label = "env";</div><div class='add'>+				reg = &lt;0x200000 0x400000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			partition@600000 {</div><div class='add'>+				label = "system";</div><div class='add'>+				reg = &lt;0x600000 0xa00000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			partition@1000000 {</div><div class='add'>+				label = "rootfs";</div><div class='add'>+				reg = &lt;0x1000000 0x3000000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			partition@4000000 {</div><div class='add'>+				label = "data";</div><div class='add'>+				reg = &lt;0x4000000 0x8000000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sd {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdcard_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;sdcard_clk_gate_pins&gt;;</div><div class='add'>+	pinctrl-names = "default","clk-gate";</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	max-frequency = &lt;50000000&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+</div><div class='add'>+	cd-gpios = &lt;&amp;gpio GPIOC_6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;sdcard&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;sdcard&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c2_pins1&gt;;</div><div class='add'>+	clock-frequency = &lt;100000&gt;; /* default 100k */</div><div class='add'>+</div><div class='add'>+	imx290: sensor0@1a {</div><div class='add'>+		compatible = "sony,imx290";</div><div class='add'>+		reg = &lt;0x1a&gt;;</div><div class='add'>+		clocks = &lt;&amp;clkc_pll CLKID_MCLK0&gt;;</div><div class='add'>+		clock-names = "xclk";</div><div class='add'>+		clock-frequency = &lt;37125000&gt;;</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc_pll CLKID_MCLK_PLL&gt;,</div><div class='add'>+				  &lt;&amp;clkc_pll CLKID_MCLK0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;74250000&gt;, &lt;37125000&gt;;</div><div class='add'>+</div><div class='add'>+		vdddo-supply = &lt;&amp;camera_vdddo_1v8&gt;;</div><div class='add'>+		vdda-supply = &lt;&amp;camera_vdda_2v9&gt;;</div><div class='add'>+		vddd-supply = &lt;&amp;camera_vddd_1v2&gt;;</div><div class='add'>+</div><div class='add'>+		reset-gpios = &lt;&amp;gpio GPIOE_4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			imx290_out: endpoint {</div><div class='add'>+				data-lanes = &lt;1 2 3 4&gt;;</div><div class='add'>+				link-frequencies = /bits/ 64 &lt;222750000 148500000&gt;;</div><div class='add'>+				remote-endpoint = &lt;&amp;c3_mipi_csi_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;csi2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@0 {</div><div class='add'>+			c3_mipi_csi_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;imx290_out&gt;;</div><div class='add'>+				data-lanes = &lt;1 2 3 4&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;adap {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;isp {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi<br/>new file mode 100644<br/>index 000000000000..13b7ac03f9b2<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi</a></div><div class='hunk'>@@ -0,0 +1,1123 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2021 Amlogic, Inc. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/reset/amlogic,c3-reset.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/amlogic,c3-pll-clkc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/amlogic,c3-scmi-clkc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/amlogic,c3-peripherals-clkc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/power/amlogic,c3-pwrc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/amlogic-c3-gpio.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a35";</div><div class='add'>+			reg = &lt;0x0 0x0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			d-cache-line-size = &lt;32&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-sets = &lt;32&gt;;</div><div class='add'>+			i-cache-line-size = &lt;32&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-sets = &lt;32&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@1 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a35";</div><div class='add'>+			reg = &lt;0x0 0x1&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			d-cache-line-size = &lt;32&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-sets = &lt;32&gt;;</div><div class='add'>+			i-cache-line-size = &lt;32&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-sets = &lt;32&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2: l2-cache0 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x7d000&gt;; /* L2. 512 KB */</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;512&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-1.0";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	xtal: xtal-clk {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+		clock-output-names = "xtal";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	xtal_32k: xtal-clk-32k {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		clock-frequency = &lt;32768&gt;;</div><div class='add'>+		clock-output-names = "xtal_32k";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sm: secure-monitor {</div><div class='add'>+		compatible = "amlogic,meson-gxbb-sm";</div><div class='add'>+</div><div class='add'>+		pwrc: power-controller {</div><div class='add'>+			compatible = "amlogic,c3-pwrc";</div><div class='add'>+			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sram@7f50e00 {</div><div class='add'>+		compatible = "mmio-sram";</div><div class='add'>+		reg = &lt;0x0 0x07f50e00 0x0 0x100&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges = &lt;0 0x0 0x07f50e00 0x100&gt;;</div><div class='add'>+</div><div class='add'>+		scmi_shmem: sram@0 {</div><div class='add'>+			compatible = "arm,scmi-shmem";</div><div class='add'>+			reg = &lt;0x0 0x100&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	firmware {</div><div class='add'>+		scmi: scmi {</div><div class='add'>+			compatible = "arm,scmi-smc";</div><div class='add'>+			arm,smc-id = &lt;0x820000C1&gt;;</div><div class='add'>+			shmem = &lt;&amp;scmi_shmem&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			scmi_clk: protocol@14 {</div><div class='add'>+				reg = &lt;0x14&gt;;</div><div class='add'>+				#clock-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@fff01000 {</div><div class='add'>+			compatible = "arm,gic-400";</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			#address-cells = &lt;0&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			reg = &lt;0x0 0xfff01000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0xfff02000 0 0x2000&gt;,</div><div class='add'>+			      &lt;0x0 0xfff04000 0 0x2000&gt;,</div><div class='add'>+			      &lt;0x0 0xfff06000 0 0x2000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		apb4: bus@fe000000 {</div><div class='add'>+			compatible = "simple-bus";</div><div class='add'>+			reg = &lt;0x0 0xfe000000 0x0 0x480000&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges = &lt;0x0 0x0 0x0 0xfe000000 0x0 0x480000&gt;;</div><div class='add'>+</div><div class='add'>+			clkc_periphs: clock-controller@0 {</div><div class='add'>+				compatible = "amlogic,c3-peripherals-clkc";</div><div class='add'>+				reg = &lt;0x0 0x0 0x0 0x49c&gt;;</div><div class='add'>+				#clock-cells = &lt;1&gt;;</div><div class='add'>+				clocks = &lt;&amp;xtal&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk CLKID_OSC&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk CLKID_FIXED_PLL_OSC&gt;,</div><div class='add'>+					 &lt;&amp;clkc_pll CLKID_FCLK_DIV2&gt;,</div><div class='add'>+					 &lt;&amp;clkc_pll CLKID_FCLK_DIV2P5&gt;,</div><div class='add'>+					 &lt;&amp;clkc_pll CLKID_FCLK_DIV3&gt;,</div><div class='add'>+					 &lt;&amp;clkc_pll CLKID_FCLK_DIV4&gt;,</div><div class='add'>+					 &lt;&amp;clkc_pll CLKID_FCLK_DIV5&gt;,</div><div class='add'>+					 &lt;&amp;clkc_pll CLKID_FCLK_DIV7&gt;,</div><div class='add'>+					 &lt;&amp;clkc_pll CLKID_GP0_PLL&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk CLKID_GP1_PLL_OSC&gt;,</div><div class='add'>+					 &lt;&amp;clkc_pll CLKID_HIFI_PLL&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk CLKID_SYS_CLK&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk CLKID_AXI_CLK&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk CLKID_SYS_PLL_DIV16&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk CLKID_CPU_CLK_DIV16&gt;;</div><div class='add'>+				clock-names = "xtal_24m",</div><div class='add'>+					      "oscin",</div><div class='add'>+					      "fix",</div><div class='add'>+					      "fdiv2",</div><div class='add'>+					      "fdiv2p5",</div><div class='add'>+					      "fdiv3",</div><div class='add'>+					      "fdiv4",</div><div class='add'>+					      "fdiv5",</div><div class='add'>+					      "fdiv7",</div><div class='add'>+					      "gp0",</div><div class='add'>+					      "gp1",</div><div class='add'>+					      "hifi",</div><div class='add'>+					      "sysclk",</div><div class='add'>+					      "axiclk",</div><div class='add'>+					      "sysplldiv16",</div><div class='add'>+					      "cpudiv16";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reset: reset-controller@2000 {</div><div class='add'>+				compatible = "amlogic,c3-reset";</div><div class='add'>+				reg = &lt;0x0 0x2000 0x0 0x98&gt;;</div><div class='add'>+				#reset-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			watchdog@2100 {</div><div class='add'>+				compatible = "amlogic,c3-wdt", "amlogic,t7-wdt";</div><div class='add'>+				reg = &lt;0x0 0x2100 0x0 0x10&gt;;</div><div class='add'>+				clocks = &lt;&amp;xtal&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			periphs_pinctrl: pinctrl@4000 {</div><div class='add'>+				compatible = "amlogic,c3-periphs-pinctrl";</div><div class='add'>+				#address-cells = &lt;2&gt;;</div><div class='add'>+				#size-cells = &lt;2&gt;;</div><div class='add'>+				ranges = &lt;0x0 0x0 0x0 0x4000 0x0 0x02de&gt;;</div><div class='add'>+</div><div class='add'>+				gpio: bank@0 {</div><div class='add'>+					reg = &lt;0x0 0x0 0x0 0x004c&gt;,</div><div class='add'>+					      &lt;0x0 0x100 0x0 0x01de&gt;;</div><div class='add'>+					reg-names = "mux", "gpio";</div><div class='add'>+					gpio-controller;</div><div class='add'>+					#gpio-cells = &lt;2&gt;;</div><div class='add'>+					gpio-ranges = &lt;&amp;periphs_pinctrl 0 0 55&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				i2c0_pins1: i2c0-pins1 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "i2c0_sda_e",</div><div class='add'>+							 "i2c0_scl_e";</div><div class='add'>+						function = "i2c0";</div><div class='add'>+						bias-disable;</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				i2c0_pins2: i2c0-pins2 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "i2c0_sda_d",</div><div class='add'>+							 "i2c0_scl_d";</div><div class='add'>+						function = "i2c0";</div><div class='add'>+						bias-disable;</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				i2c1_pins1: i2c1-pins1 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "i2c1_sda_x",</div><div class='add'>+							 "i2c1_scl_x";</div><div class='add'>+						function = "i2c1";</div><div class='add'>+						bias-disable;</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				i2c1_pins2: i2c1-pins2 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "i2c1_sda_d",</div><div class='add'>+							 "i2c1_scl_d";</div><div class='add'>+						function = "i2c1";</div><div class='add'>+						bias-disable;</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				i2c1_pins3: i2c1-pins3 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "i2c1_sda_a",</div><div class='add'>+							 "i2c1_scl_a";</div><div class='add'>+						function = "i2c1";</div><div class='add'>+						bias-disable;</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				i2c1_pins4: i2c1-pins4 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "i2c1_sda_b",</div><div class='add'>+							 "i2c1_scl_b";</div><div class='add'>+						function = "i2c1";</div><div class='add'>+						bias-disable;</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				i2c2_pins1: i2c2-pins1 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "i2c2_sda",</div><div class='add'>+							 "i2c2_scl";</div><div class='add'>+						function = "i2c2";</div><div class='add'>+						bias-disable;</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				i2c3_pins1: i2c3-pins1 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "i2c3_sda_c",</div><div class='add'>+							 "i2c3_scl_c";</div><div class='add'>+						function = "i2c3";</div><div class='add'>+						bias-disable;</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				i2c3_pins2: i2c3-pins2 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "i2c3_sda_x",</div><div class='add'>+							 "i2c3_scl_x";</div><div class='add'>+						function = "i2c3";</div><div class='add'>+						bias-disable;</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				i2c3_pins3: i2c3-pins3 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "i2c3_sda_d",</div><div class='add'>+							 "i2c3_scl_d";</div><div class='add'>+						function = "i2c3";</div><div class='add'>+						bias-disable;</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				nand_pins: nand-pins {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "emmc_nand_d0",</div><div class='add'>+							 "emmc_nand_d1",</div><div class='add'>+							 "emmc_nand_d2",</div><div class='add'>+							 "emmc_nand_d3",</div><div class='add'>+							 "emmc_nand_d4",</div><div class='add'>+							 "emmc_nand_d5",</div><div class='add'>+							 "emmc_nand_d6",</div><div class='add'>+							 "emmc_nand_d7",</div><div class='add'>+							 "nand_ce0",</div><div class='add'>+							 "nand_ale",</div><div class='add'>+							 "nand_cle",</div><div class='add'>+							 "nand_wen_clk",</div><div class='add'>+							 "nand_ren_wr";</div><div class='add'>+						function = "nand";</div><div class='add'>+						input-enable;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				sdcard_pins: sdcard-pins {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "sdcard_d0",</div><div class='add'>+							 "sdcard_d1",</div><div class='add'>+							 "sdcard_d2",</div><div class='add'>+							 "sdcard_d3",</div><div class='add'>+							 "sdcard_clk",</div><div class='add'>+							 "sdcard_cmd";</div><div class='add'>+						function = "sdcard";</div><div class='add'>+						bias-pull-up;</div><div class='add'>+						drive-strength-microamp = &lt;4000&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				sdcard_clk_gate_pins: sdcard-clk-cmd-pins {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "GPIOC_4";</div><div class='add'>+						function = "gpio_periphs";</div><div class='add'>+						bias-pull-down;</div><div class='add'>+						drive-strength-microamp = &lt;4000&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				sdio_m_clk_gate_pins: sdio-m-clk-cmd-pins {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "sdio_clk";</div><div class='add'>+						function = "sdio";</div><div class='add'>+						bias-pull-down;</div><div class='add'>+						drive-strength-microamp = &lt;4000&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				sdio_m_pins: sdio-m-all-pins {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "sdio_d0",</div><div class='add'>+							 "sdio_d1",</div><div class='add'>+							 "sdio_d2",</div><div class='add'>+							 "sdio_d3",</div><div class='add'>+							 "sdio_clk",</div><div class='add'>+							 "sdio_cmd";</div><div class='add'>+						function = "sdio";</div><div class='add'>+						input-enable;</div><div class='add'>+						bias-pull-up;</div><div class='add'>+						drive-strength-microamp = &lt;4000&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				spicc0_pins1: spicc0-pins1 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "spi_a_mosi_b",</div><div class='add'>+							 "spi_a_miso_b",</div><div class='add'>+							 "spi_a_clk_b";</div><div class='add'>+						function = "spi_a";</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				spicc0_pins2: spicc0-pins2 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "spi_a_mosi_c",</div><div class='add'>+							 "spi_a_miso_c",</div><div class='add'>+							 "spi_a_clk_c";</div><div class='add'>+						function = "spi_a";</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				spicc0_pins3: spicc0-pins3 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "spi_a_mosi_x",</div><div class='add'>+							 "spi_a_miso_x",</div><div class='add'>+							 "spi_a_clk_x";</div><div class='add'>+						function = "spi_a";</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				spicc1_pins1: spicc1-pins1 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "spi_b_mosi_d",</div><div class='add'>+							 "spi_b_miso_d",</div><div class='add'>+							 "spi_b_clk_d";</div><div class='add'>+						function = "spi_b";</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				spicc1_pins2: spicc1-pins2 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "spi_b_mosi_x",</div><div class='add'>+							 "spi_b_miso_x",</div><div class='add'>+							 "spi_b_clk_x";</div><div class='add'>+						function = "spi_b";</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				spifc_pins: spifc-pins {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "spif_mo",</div><div class='add'>+							 "spif_mi",</div><div class='add'>+							 "spif_clk",</div><div class='add'>+							 "spif_cs",</div><div class='add'>+							 "spif_hold",</div><div class='add'>+							 "spif_wp",</div><div class='add'>+							 "spif_clk_loop";</div><div class='add'>+						function = "spif";</div><div class='add'>+						drive-strength-microamp = &lt;4000&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_a_pins1: pwm-a-pins1 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_a";</div><div class='add'>+						function = "pwm_a";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_b_pins1: pwm-b-pins1 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_b";</div><div class='add'>+						function = "pwm_b";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_c_pins1: pwm-c-pins1 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_c";</div><div class='add'>+						function = "pwm_c";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_d_pins1: pwm-d-pins1 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_d";</div><div class='add'>+						function = "pwm_d";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_e_pins1: pwm-e-pins1 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_e";</div><div class='add'>+						function = "pwm_e";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_f_pins1: pwm-f-pins1 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_f";</div><div class='add'>+						function = "pwm_f";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_g_pins1: pwm-g-pins1 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_g_b";</div><div class='add'>+						function = "pwm_g";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_g_pins2: pwm-g-pins2 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_g_c";</div><div class='add'>+						function = "pwm_g";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_g_pins3: pwm-g-pins3 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_g_d";</div><div class='add'>+						function = "pwm_g";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_g_pins4: pwm-g-pins4 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_g_x0";</div><div class='add'>+						function = "pwm_g";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_g_pins5: pwm-g-pins5 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_g_x8";</div><div class='add'>+						function = "pwm_g";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_h_pins1: pwm-h-pins1 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_h_b";</div><div class='add'>+						function = "pwm_h";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_h_pins2: pwm-h-pins2 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_h_c";</div><div class='add'>+						function = "pwm_h";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_h_pins3: pwm-h-pins3 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_h_d";</div><div class='add'>+						function = "pwm_h";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_h_pins4: pwm-h-pins4 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_h_x1";</div><div class='add'>+						function = "pwm_h";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_h_pins5: pwm-h-pins5 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_h_x9";</div><div class='add'>+						function = "pwm_h";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_i_pins1: pwm-i-pins1 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_i_b";</div><div class='add'>+						function = "pwm_i";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_i_pins2: pwm-i-pins2 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_i_c";</div><div class='add'>+						function = "pwm_i";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_i_pins3: pwm-i-pins3 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_i_d";</div><div class='add'>+						function = "pwm_i";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_i_pins4: pwm-i-pins4 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_i_x2";</div><div class='add'>+						function = "pwm_i";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_i_pins5: pwm-i-pins5 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_i_x10";</div><div class='add'>+						function = "pwm_i";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_j_pins1: pwm-j-pins1 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_j_c";</div><div class='add'>+						function = "pwm_j";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_j_pins2: pwm-j-pins2 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_j_d";</div><div class='add'>+						function = "pwm_j";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_j_pins3: pwm-j-pins3 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_j_b";</div><div class='add'>+						function = "pwm_j";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_j_pins4: pwm-j-pins4 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_j_x3";</div><div class='add'>+						function = "pwm_j";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_j_pins5: pwm-j-pins5 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_j_x12";</div><div class='add'>+						function = "pwm_j";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_k_pins1: pwm-k-pins1 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_k_c";</div><div class='add'>+						function = "pwm_k";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_k_pins2: pwm-k-pins2 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_k_d";</div><div class='add'>+						function = "pwm_k";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_k_pins3: pwm-k-pins3 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_k_b";</div><div class='add'>+						function = "pwm_k";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_k_pins4: pwm-k-pins4 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_k_x4";</div><div class='add'>+						function = "pwm_k";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_k_pins5: pwm-k-pins5 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_k_x13";</div><div class='add'>+						function = "pwm_k";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_l_pins1: pwm-l-pins1 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_l_c";</div><div class='add'>+						function = "pwm_l";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_l_pins2: pwm-l-pins2 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_l_x";</div><div class='add'>+						function = "pwm_l";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_l_pins3: pwm-l-pins3 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_l_b";</div><div class='add'>+						function = "pwm_l";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_l_pins4: pwm-l-pins4 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_l_a";</div><div class='add'>+						function = "pwm_l";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_m_pins1: pwm-m-pins1 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_m_c";</div><div class='add'>+						function = "pwm_m";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_m_pins2: pwm-m-pins2 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_m_x";</div><div class='add'>+						function = "pwm_m";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_m_pins3: pwm-m-pins3 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_m_a";</div><div class='add'>+						function = "pwm_m";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_m_pins4: pwm-m-pins4 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_m_b";</div><div class='add'>+						function = "pwm_m";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_n_pins1: pwm-n-pins1 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_n_x";</div><div class='add'>+						function = "pwm_n";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_n_pins2: pwm-n-pins2 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_n_a";</div><div class='add'>+						function = "pwm_n";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_n_pins3: pwm-n-pins3 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_n_b";</div><div class='add'>+						function = "pwm_n";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gpio_intc: interrupt-controller@4080 {</div><div class='add'>+				compatible = "amlogic,c3-gpio-intc", "amlogic,meson-gpio-intc";</div><div class='add'>+				reg = &lt;0x0 0x4080 0x0 0x0020&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;2&gt;;</div><div class='add'>+				amlogic,channel-interrupts =</div><div class='add'>+					&lt;10 11 12 13 14 15 16 17 18 19 20 21&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			clkc_pll: clock-controller@8000 {</div><div class='add'>+				compatible = "amlogic,c3-pll-clkc";</div><div class='add'>+				reg = &lt;0x0 0x8000 0x0 0x1a4&gt;;</div><div class='add'>+				#clock-cells = &lt;1&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk CLKID_TOP_PLL_OSC&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk CLKID_MCLK_PLL_OSC&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk CLKID_FIXED_PLL_OSC&gt;;</div><div class='add'>+				clock-names = "top",</div><div class='add'>+					      "mclk",</div><div class='add'>+					      "fix";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			eth_phy: mdio-multiplexer@28000 {</div><div class='add'>+				compatible = "amlogic,g12a-mdio-mux";</div><div class='add'>+				reg = &lt;0x0 0x28000 0x0 0xa4&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;clkc_periphs CLKID_SYS_ETH_PHY&gt;,</div><div class='add'>+					 &lt;&amp;xtal&gt;,</div><div class='add'>+					 &lt;&amp;clkc_pll CLKID_FCLK_50M&gt;;</div><div class='add'>+				clock-names = "pclk", "clkin0", "clkin1";</div><div class='add'>+				mdio-parent-bus = &lt;&amp;mdio0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				ext_mdio: mdio@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				int_mdio: mdio@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					internal_ephy: ethernet_phy@8 {</div><div class='add'>+						compatible = "ethernet-phy-id0180.3301",</div><div class='add'>+							     "ethernet-phy-ieee802.3-c22";</div><div class='add'>+						interrupts = &lt;GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+						reg = &lt;8&gt;;</div><div class='add'>+						max-speed = &lt;100&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			clk_msr: clock-measure@48000 {</div><div class='add'>+				compatible = "amlogic,c3-clk-measure";</div><div class='add'>+				reg = &lt;0x0 0x48000 0x0 0x1c&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spicc0: spi@50000 {</div><div class='add'>+				compatible = "amlogic,meson-g12a-spicc";</div><div class='add'>+				reg = &lt;0x0 0x50000 0x0 0x44&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clkc_periphs CLKID_SYS_SPICC_0&gt;,</div><div class='add'>+					 &lt;&amp;clkc_periphs CLKID_SPICC_A&gt;;</div><div class='add'>+				clock-names = "core", "pclk";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spicc1: spi@52000 {</div><div class='add'>+				compatible = "amlogic,meson-g12a-spicc";</div><div class='add'>+				reg = &lt;0x0 0x52000 0x0 0x44&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clkc_periphs CLKID_SYS_SPICC_1&gt;,</div><div class='add'>+					 &lt;&amp;clkc_periphs CLKID_SPICC_B&gt;;</div><div class='add'>+				clock-names = "core", "pclk";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pwm_mn: pwm@54000 {</div><div class='add'>+				compatible = "amlogic,c3-pwm",</div><div class='add'>+					     "amlogic,meson-s4-pwm";</div><div class='add'>+				reg = &lt;0x0 0x54000 0x0 0x24&gt;;</div><div class='add'>+				clocks = &lt;&amp;clkc_periphs CLKID_PWM_M&gt;,</div><div class='add'>+					 &lt;&amp;clkc_periphs CLKID_PWM_N&gt;;</div><div class='add'>+				#pwm-cells = &lt;3&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spifc: spi@56000 {</div><div class='add'>+				compatible = "amlogic,a1-spifc";</div><div class='add'>+				reg = &lt;0x0 0x56000 0x0 0x290&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 182 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				clocks = &lt;&amp;clkc_periphs CLKID_SPIFC&gt;;</div><div class='add'>+				clock-names = "core";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pwm_ab: pwm@58000 {</div><div class='add'>+				compatible = "amlogic,c3-pwm",</div><div class='add'>+					     "amlogic,meson-s4-pwm";</div><div class='add'>+				reg = &lt;0x0 0x58000 0x0 0x24&gt;;</div><div class='add'>+				clocks = &lt;&amp;clkc_periphs CLKID_PWM_A&gt;,</div><div class='add'>+					 &lt;&amp;clkc_periphs CLKID_PWM_B&gt;;</div><div class='add'>+				#pwm-cells = &lt;3&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pwm_cd: pwm@5a000 {</div><div class='add'>+				compatible = "amlogic,c3-pwm",</div><div class='add'>+					     "amlogic,meson-s4-pwm";</div><div class='add'>+				reg = &lt;0x0 0x5a000 0x0 0x24&gt;;</div><div class='add'>+				clocks = &lt;&amp;clkc_periphs CLKID_PWM_C&gt;,</div><div class='add'>+					 &lt;&amp;clkc_periphs CLKID_PWM_D&gt;;</div><div class='add'>+				#pwm-cells = &lt;3&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pwm_ef: pwm@5c000 {</div><div class='add'>+				compatible = "amlogic,c3-pwm",</div><div class='add'>+					     "amlogic,meson-s4-pwm";</div><div class='add'>+				reg = &lt;0x0 0x5c000 0x0 0x24&gt;;</div><div class='add'>+				clocks = &lt;&amp;clkc_periphs CLKID_PWM_E&gt;,</div><div class='add'>+					 &lt;&amp;clkc_periphs CLKID_PWM_F&gt;;</div><div class='add'>+				#pwm-cells = &lt;3&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pwm_gh: pwm@5e000 {</div><div class='add'>+				compatible = "amlogic,c3-pwm",</div><div class='add'>+					     "amlogic,meson-s4-pwm";</div><div class='add'>+				reg = &lt;0x0 0x5e000 0x0 0x24&gt;;</div><div class='add'>+				clocks = &lt;&amp;clkc_periphs CLKID_PWM_G&gt;,</div><div class='add'>+					 &lt;&amp;clkc_periphs CLKID_PWM_H&gt;;</div><div class='add'>+				#pwm-cells = &lt;3&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pwm_ij: pwm@60000 {</div><div class='add'>+				compatible = "amlogic,c3-pwm",</div><div class='add'>+					     "amlogic,meson-s4-pwm";</div><div class='add'>+				reg = &lt;0x0 0x60000 0x0 0x24&gt;;</div><div class='add'>+				clocks = &lt;&amp;clkc_periphs CLKID_PWM_I&gt;,</div><div class='add'>+					 &lt;&amp;clkc_periphs CLKID_PWM_J&gt;;</div><div class='add'>+				#pwm-cells = &lt;3&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pwm_kl: pwm@62000 {</div><div class='add'>+				compatible = "amlogic,c3-pwm",</div><div class='add'>+					     "amlogic,meson-s4-pwm";</div><div class='add'>+				reg = &lt;0x0 0x62000 0x0 0x24&gt;;</div><div class='add'>+				clocks = &lt;&amp;clkc_periphs CLKID_PWM_K&gt;,</div><div class='add'>+					 &lt;&amp;clkc_periphs CLKID_PWM_L&gt;;</div><div class='add'>+				#pwm-cells = &lt;3&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c0: i2c@66000 {</div><div class='add'>+				compatible = "amlogic,meson-axg-i2c";</div><div class='add'>+				reg = &lt;0x0 0x66000 0x0 0x24&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 160 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;clkc_periphs CLKID_SYS_I2C_M_A&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c1: i2c@68000 {</div><div class='add'>+				compatible = "amlogic,meson-axg-i2c";</div><div class='add'>+				reg = &lt;0x0 0x68000 0x0 0x24&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 161 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;clkc_periphs CLKID_SYS_I2C_M_B&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c2: i2c@6a000 {</div><div class='add'>+				compatible = "amlogic,meson-axg-i2c";</div><div class='add'>+				reg = &lt;0x0 0x6a000 0x0 0x24&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 162 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;clkc_periphs CLKID_SYS_I2C_M_C&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c3: i2c@6c000 {</div><div class='add'>+				compatible = "amlogic,meson-axg-i2c";</div><div class='add'>+				reg = &lt;0x0 0x6c000 0x0 0x24&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 163 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;clkc_periphs CLKID_SYS_I2C_M_D&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart_b: serial@7a000 {</div><div class='add'>+				compatible = "amlogic,meson-s4-uart",</div><div class='add'>+					   "amlogic,meson-ao-uart";</div><div class='add'>+				reg = &lt;0x0 0x7a000 0x0 0x18&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 169 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+				clocks = &lt;&amp;xtal&gt;, &lt;&amp;clkc_periphs CLKID_SYS_UART_B&gt;, &lt;&amp;xtal&gt;;</div><div class='add'>+				clock-names = "xtal", "pclk", "baud";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sec_ao: ao-secure@10220 {</div><div class='add'>+				compatible = "amlogic,c3-ao-secure",</div><div class='add'>+					     "amlogic,meson-gx-ao-secure",</div><div class='add'>+					     "syscon";</div><div class='add'>+				reg = &lt;0x0 0x10220 0x0 0x140&gt;;</div><div class='add'>+				amlogic,has-chip-id;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sdio: mmc@88000 {</div><div class='add'>+				compatible = "amlogic,meson-axg-mmc";</div><div class='add'>+				reg = &lt;0x0 0x88000 0x0 0x800&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 176 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				power-domains = &lt;&amp;pwrc PWRC_C3_SDIOA_ID&gt;;</div><div class='add'>+				clocks = &lt;&amp;clkc_periphs CLKID_SYS_SD_EMMC_A&gt;,</div><div class='add'>+					  &lt;&amp;clkc_periphs CLKID_SD_EMMC_A&gt;,</div><div class='add'>+					  &lt;&amp;clkc_pll CLKID_FCLK_DIV2&gt;;</div><div class='add'>+				clock-names = "core","clkin0", "clkin1";</div><div class='add'>+				no-mmc;</div><div class='add'>+				no-sd;</div><div class='add'>+				resets = &lt;&amp;reset RESET_SD_EMMC_A&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sd: mmc@8a000 {</div><div class='add'>+				compatible = "amlogic,meson-axg-mmc";</div><div class='add'>+				reg = &lt;0x0 0x8a000 0x0 0x800&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 177 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				power-domains = &lt;&amp;pwrc PWRC_C3_SDCARD_ID&gt;;</div><div class='add'>+				clocks = &lt;&amp;clkc_periphs CLKID_SYS_SD_EMMC_B&gt;,</div><div class='add'>+					&lt;&amp;clkc_periphs CLKID_SD_EMMC_B&gt;,</div><div class='add'>+					&lt;&amp;clkc_pll CLKID_FCLK_DIV2&gt;;</div><div class='add'>+				clock-names = "core", "clkin0", "clkin1";</div><div class='add'>+				no-mmc;</div><div class='add'>+				no-sdio;</div><div class='add'>+				resets = &lt;&amp;reset RESET_SD_EMMC_B&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			nand: nand-controller@8d000 {</div><div class='add'>+				compatible = "amlogic,meson-axg-nfc";</div><div class='add'>+				reg = &lt;0x0 0x8d000 0x0 0x200&gt;,</div><div class='add'>+					&lt;0x0 0x8C000 0x0 0x4&gt;;</div><div class='add'>+				reg-names = "nfc", "emmc";</div><div class='add'>+				interrupts = &lt;GIC_SPI 87 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				clocks = &lt;&amp;clkc_periphs CLKID_SYS_SD_EMMC_C&gt;,</div><div class='add'>+					&lt;&amp;clkc_pll CLKID_FCLK_DIV2&gt;;</div><div class='add'>+				clock-names = "core", "device";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			rtc@9a000 {</div><div class='add'>+				compatible = "amlogic,c3-rtc",</div><div class='add'>+					     "amlogic,a5-rtc";</div><div class='add'>+				reg = &lt;0x0 0x9a000 0x0 0x38&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 131 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				clocks = &lt;&amp;xtal_32k&gt;, &lt;&amp;clkc_periphs CLKID_SYS_RTC&gt;;</div><div class='add'>+				clock-names = "osc", "sys";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ethmac: ethernet@fdc00000 {</div><div class='add'>+			compatible = "amlogic,meson-g12a-dwmac",</div><div class='add'>+				     "snps,dwmac-3.70a",</div><div class='add'>+				     "snps,dwmac";</div><div class='add'>+			reg = &lt;0x0 0xfdc00000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0xfe024000 0x0 0x8&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "macirq";</div><div class='add'>+			power-domains = &lt;&amp;pwrc PWRC_C3_ETH_ID&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkc_periphs CLKID_SYS_ETH_MAC&gt;,</div><div class='add'>+				 &lt;&amp;clkc_pll CLKID_FCLK_DIV2&gt;,</div><div class='add'>+				 &lt;&amp;clkc_pll CLKID_FCLK_50M&gt;;</div><div class='add'>+			clock-names = "stmmaceth", "clkin0", "clkin1";</div><div class='add'>+			rx-fifo-depth = &lt;4096&gt;;</div><div class='add'>+			tx-fifo-depth = &lt;2048&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			mdio0: mdio {</div><div class='add'>+				compatible = "snps,dwmac-mdio";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		csi2: csi2@ff018000 {</div><div class='add'>+			compatible = "amlogic,c3-mipi-csi2";</div><div class='add'>+			reg = &lt;0x0 0xff018000 0x0 0x100&gt;,</div><div class='add'>+			      &lt;0x0 0xff019000 0x0 0x300&gt;,</div><div class='add'>+			      &lt;0x0 0xff01a000 0x0 0x100&gt;;</div><div class='add'>+			reg-names = "aphy", "dphy", "host";</div><div class='add'>+			power-domains = &lt;&amp;pwrc PWRC_C3_MIPI_ISP_WRAP_ID&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkc_periphs CLKID_VAPB&gt;,</div><div class='add'>+				 &lt;&amp;clkc_periphs CLKID_CSI_PHY0&gt;;</div><div class='add'>+			clock-names = "vapb", "phy0";</div><div class='add'>+			assigned-clocks = &lt;&amp;clkc_periphs CLKID_VAPB&gt;,</div><div class='add'>+					  &lt;&amp;clkc_periphs CLKID_CSI_PHY0&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;0&gt;, &lt;200000000&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					c3_mipi_csi_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;c3_adap_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		adap: adap@ff010000 {</div><div class='add'>+			compatible = "amlogic,c3-mipi-adapter";</div><div class='add'>+			reg = &lt;0x0 0xff010000 0x0 0x100&gt;,</div><div class='add'>+			      &lt;0x0 0xff01b000 0x0 0x100&gt;,</div><div class='add'>+			      &lt;0x0 0xff01d000 0x0 0x200&gt;;</div><div class='add'>+			reg-names = "top", "fd", "rd";</div><div class='add'>+			power-domains = &lt;&amp;pwrc PWRC_C3_ISP_TOP_ID&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkc_periphs CLKID_VAPB&gt;,</div><div class='add'>+				 &lt;&amp;clkc_periphs CLKID_ISP0&gt;;</div><div class='add'>+			clock-names = "vapb", "isp0";</div><div class='add'>+			assigned-clocks = &lt;&amp;clkc_periphs CLKID_VAPB&gt;,</div><div class='add'>+					  &lt;&amp;clkc_periphs CLKID_ISP0&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;0&gt;, &lt;400000000&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					c3_adap_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;c3_mipi_csi_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					c3_adap_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;c3_isp_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		isp: isp@ff000000 {</div><div class='add'>+			compatible = "amlogic,c3-isp";</div><div class='add'>+			reg = &lt;0x0 0xff000000 0x0 0xf000&gt;;</div><div class='add'>+			reg-names = "isp";</div><div class='add'>+			power-domains = &lt;&amp;pwrc PWRC_C3_ISP_TOP_ID&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkc_periphs CLKID_VAPB&gt;,</div><div class='add'>+				 &lt;&amp;clkc_periphs CLKID_ISP0&gt;;</div><div class='add'>+			clock-names = "vapb", "isp0";</div><div class='add'>+			assigned-clocks = &lt;&amp;clkc_periphs CLKID_VAPB&gt;,</div><div class='add'>+					  &lt;&amp;clkc_periphs CLKID_ISP0&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;0&gt;, &lt;400000000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 145 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			port {</div><div class='add'>+				c3_isp_in: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;c3_adap_out&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s6-s905x5-bl209.dts b/arch/arm64/boot/dts/amlogic/amlogic-s6-s905x5-bl209.dts<br/>new file mode 100644<br/>index 000000000000..c45b22651798<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/amlogic-s6-s905x5-bl209.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/amlogic-s6-s905x5-bl209.dts</a></div><div class='hunk'>@@ -0,0 +1,42 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2025 Amlogic, Inc. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "amlogic-s6.dtsi"</div><div class='add'>+/ {</div><div class='add'>+	model = "Amlogic S905X5 BL209 Development Board";</div><div class='add'>+	compatible = "amlogic,bl209", "amlogic,s6";</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart_b;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x000000 0x0 0xe0000000&gt;,</div><div class='add'>+		      &lt;0x1 0x000000 0x0 0x20000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		/* 27 MiB reserved for ARM Trusted Firmware */</div><div class='add'>+		secmon_reserved: secmon@5000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0x0 0x05000000 0x0 0x1b00000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi<br/>new file mode 100644<br/>index 000000000000..8ef631939033<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi</a></div><div class='hunk'>@@ -0,0 +1,222 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2025 Amlogic, Inc. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/amlogic,pinctrl.h&gt;</div><div class='add'>+#include &lt;dt-bindings/power/amlogic,s6-pwrc.h&gt;</div><div class='add'>+/ {</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a510";</div><div class='add'>+			reg = &lt;0x0 0x0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@100 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a510";</div><div class='add'>+			reg = &lt;0x0 0x100&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@200 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a510";</div><div class='add'>+			reg = &lt;0x0 0x200&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@300 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a510";</div><div class='add'>+			reg = &lt;0x0 0x300&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sm: secure-monitor {</div><div class='add'>+		compatible = "amlogic,meson-gxbb-sm";</div><div class='add'>+</div><div class='add'>+		pwrc: power-controller {</div><div class='add'>+			compatible = "amlogic,s6-pwrc";</div><div class='add'>+			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-1.0";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	xtal: xtal-clk {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+		clock-output-names = "xtal";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@ff200000 {</div><div class='add'>+			compatible = "arm,gic-v3";</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			#address-cells = &lt;0&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			reg = &lt;0x0 0xff200000 0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0xff240000 0 0x80000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 0xf04&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		apb: bus@fe000000 {</div><div class='add'>+			compatible = "simple-bus";</div><div class='add'>+			reg = &lt;0x0 0xfe000000 0x0 0x480000&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges = &lt;0x0 0x0 0x0 0xfe000000 0x0 0x480000&gt;;</div><div class='add'>+</div><div class='add'>+			uart_b: serial@7a000 {</div><div class='add'>+				compatible = "amlogic,s6-uart",</div><div class='add'>+					     "amlogic,meson-s4-uart";</div><div class='add'>+				reg = &lt;0x0 0x7a000 0x0 0x18&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 169 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				clocks = &lt;&amp;xtal&gt;, &lt;&amp;xtal&gt;, &lt;&amp;xtal&gt;;</div><div class='add'>+				clock-names = "xtal", "pclk", "baud";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			periphs_pinctrl: pinctrl@4000 {</div><div class='add'>+				compatible = "amlogic,pinctrl-s6";</div><div class='add'>+				#address-cells = &lt;2&gt;;</div><div class='add'>+				#size-cells = &lt;2&gt;;</div><div class='add'>+				ranges = &lt;0x0 0x0 0x0 0x4000 0x0 0x340&gt;;</div><div class='add'>+</div><div class='add'>+				gpioz: gpio@c0 {</div><div class='add'>+					reg = &lt;0 0xc0 0 0x20&gt;, &lt;0 0x18 0 0x8&gt;;</div><div class='add'>+					reg-names = "gpio", "mux";</div><div class='add'>+					gpio-controller;</div><div class='add'>+					#gpio-cells = &lt;2&gt;;</div><div class='add'>+					gpio-ranges = &lt;&amp;periphs_pinctrl 0 (AMLOGIC_GPIO_Z&lt;&lt;8) 16&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpiox: gpio@100 {</div><div class='add'>+					reg = &lt;0 0x100 0 0x30&gt;, &lt;0 0xc 0 0x8&gt;;</div><div class='add'>+					reg-names = "gpio", "mux";</div><div class='add'>+					gpio-controller;</div><div class='add'>+					#gpio-cells = &lt;2&gt;;</div><div class='add'>+					gpio-ranges = &lt;&amp;periphs_pinctrl 0 (AMLOGIC_GPIO_X&lt;&lt;8) 20&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpioh: gpio@140 {</div><div class='add'>+					reg = &lt;0 0x140 0 0x20&gt;, &lt;0 0x2c 0 0x8&gt;;</div><div class='add'>+					reg-names = "gpio", "mux";</div><div class='add'>+					gpio-controller;</div><div class='add'>+					#gpio-cells = &lt;2&gt;;</div><div class='add'>+					gpio-ranges = &lt;&amp;periphs_pinctrl 0 (AMLOGIC_GPIO_H&lt;&lt;8) 9&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpiod: gpio@180 {</div><div class='add'>+					reg = &lt;0 0x180 0 0x20&gt;, &lt;0 0x8 0 0x4&gt;;</div><div class='add'>+					reg-names = "gpio", "mux";</div><div class='add'>+					gpio-controller;</div><div class='add'>+					#gpio-cells = &lt;2&gt;;</div><div class='add'>+					gpio-ranges = &lt;&amp;periphs_pinctrl 0 (AMLOGIC_GPIO_D&lt;&lt;8) 7&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpiof: gpio@1a0 {</div><div class='add'>+					reg = &lt;0 0x1a0 0 0x20&gt;, &lt;0 0x20 0 0x4&gt;;</div><div class='add'>+					reg-names = "gpio", "mux";</div><div class='add'>+					gpio-controller;</div><div class='add'>+					#gpio-cells = &lt;2&gt;;</div><div class='add'>+					gpio-ranges = &lt;&amp;periphs_pinctrl 0 (AMLOGIC_GPIO_F&lt;&lt;8) 5&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpioe: gpio@1c0 {</div><div class='add'>+					reg = &lt;0 0x1c0 0 0x20&gt;, &lt;0 0x48 0 0x4&gt;;</div><div class='add'>+					reg-names = "gpio", "mux";</div><div class='add'>+					gpio-controller;</div><div class='add'>+					#gpio-cells = &lt;2&gt;;</div><div class='add'>+					gpio-ranges = &lt;&amp;periphs_pinctrl 0 (AMLOGIC_GPIO_E&lt;&lt;8) 3&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpioc: gpio@200 {</div><div class='add'>+					reg = &lt;0 0x200 0 0x20&gt;, &lt;0 0x24 0 0x4&gt;;</div><div class='add'>+					reg-names = "gpio", "mux";</div><div class='add'>+					gpio-controller;</div><div class='add'>+					#gpio-cells = &lt;2&gt;;</div><div class='add'>+					gpio-ranges = &lt;&amp;periphs_pinctrl 0 (AMLOGIC_GPIO_C&lt;&lt;8) 8&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpiob: gpio@240 {</div><div class='add'>+					reg = &lt;0 0x240 0 0x20&gt;, &lt;0 0x0 0 0x8&gt;;</div><div class='add'>+					reg-names = "gpio", "mux";</div><div class='add'>+					gpio-controller;</div><div class='add'>+					#gpio-cells = &lt;2&gt;;</div><div class='add'>+					gpio-ranges = &lt;&amp;periphs_pinctrl 0 (AMLOGIC_GPIO_B&lt;&lt;8) 14&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpioa: gpio@280 {</div><div class='add'>+					reg = &lt;0 0x280 0 0x20&gt;, &lt;0 0x40 0 0x8&gt;;</div><div class='add'>+					reg-names = "gpio", "mux";</div><div class='add'>+					gpio-controller;</div><div class='add'>+					#gpio-cells = &lt;2&gt;;</div><div class='add'>+					gpio-ranges = &lt;&amp;periphs_pinctrl 0 (AMLOGIC_GPIO_A&lt;&lt;8) 16&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				test_n: gpio@2c0 {</div><div class='add'>+					reg = &lt;0 0x2c0 0 0x20&gt;;</div><div class='add'>+					reg-names = "gpio";</div><div class='add'>+					gpio-controller;</div><div class='add'>+					#gpio-cells = &lt;2&gt;;</div><div class='add'>+					gpio-ranges =</div><div class='add'>+						&lt;&amp;periphs_pinctrl 0 (AMLOGIC_GPIO_TEST_N&lt;&lt;8) 1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpiocc: gpio@300 {</div><div class='add'>+					reg = &lt;0 0x300 0 0x20&gt;, &lt;0 0x14 0 0x4&gt;;</div><div class='add'>+					reg-names = "gpio", "mux";</div><div class='add'>+					gpio-controller;</div><div class='add'>+					#gpio-cells = &lt;2&gt;;</div><div class='add'>+					gpio-ranges = &lt;&amp;periphs_pinctrl 0 (AMLOGIC_GPIO_CC&lt;&lt;8) 2&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gpio_intc: interrupt-controller@4080 {</div><div class='add'>+				compatible = "amlogic,s6-gpio-intc",</div><div class='add'>+					     "amlogic,meson-gpio-intc";</div><div class='add'>+				reg = &lt;0x0 0x4080 0x0 0x20&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;2&gt;;</div><div class='add'>+				amlogic,channel-interrupts =</div><div class='add'>+					&lt;10 11 12 13 14 15 16 17 18 19 20 21&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ao-secure@10220 {</div><div class='add'>+				compatible = "amlogic,s6-ao-secure",</div><div class='add'>+					     "amlogic,meson-gx-ao-secure",</div><div class='add'>+					     "syscon";</div><div class='add'>+				reg = &lt;0x0 0x10220 0x0 0x140&gt;;</div><div class='add'>+				amlogic,has-chip-id;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s7-s805x3-bp201.dts b/arch/arm64/boot/dts/amlogic/amlogic-s7-s805x3-bp201.dts<br/>new file mode 100644<br/>index 000000000000..7fd4ac9321a6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/amlogic-s7-s805x3-bp201.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/amlogic-s7-s805x3-bp201.dts</a></div><div class='hunk'>@@ -0,0 +1,41 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2025 Amlogic, Inc. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "amlogic-s7.dtsi"</div><div class='add'>+/ {</div><div class='add'>+	model = "Amlogic S805X3 BP201 Development Board";</div><div class='add'>+	compatible = "amlogic,bp201", "amlogic,s7";</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart_b;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x0 0x0 0x40000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		/* 35 MiB reserved for ARM Trusted Firmware */</div><div class='add'>+		secmon_reserved: secmon@5000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0x0 0x05000000 0x0 0x2300000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi<br/>new file mode 100644<br/>index 000000000000..a3faf4d188e1<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi</a></div><div class='hunk'>@@ -0,0 +1,244 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2025 Amlogic, Inc. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/amlogic,pinctrl.h&gt;</div><div class='add'>+#include &lt;dt-bindings/power/amlogic,s7-pwrc.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x0 0x0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			d-cache-line-size = &lt;32&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-sets = &lt;32&gt;;</div><div class='add'>+			i-cache-line-size = &lt;32&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-sets = &lt;32&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@100 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x0 0x100&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			d-cache-line-size = &lt;32&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-sets = &lt;32&gt;;</div><div class='add'>+			i-cache-line-size = &lt;32&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-sets = &lt;32&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@200 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x0 0x200&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			d-cache-line-size = &lt;32&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-sets = &lt;32&gt;;</div><div class='add'>+			i-cache-line-size = &lt;32&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-sets = &lt;32&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@300 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x0 0x300&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			d-cache-line-size = &lt;32&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-sets = &lt;32&gt;;</div><div class='add'>+			i-cache-line-size = &lt;32&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-sets = &lt;32&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2: l2-cache0 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x40000&gt;; /* L2. 256 KB */</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;512&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sm: secure-monitor {</div><div class='add'>+		compatible = "amlogic,meson-gxbb-sm";</div><div class='add'>+</div><div class='add'>+		pwrc: power-controller {</div><div class='add'>+			compatible = "amlogic,s7-pwrc";</div><div class='add'>+			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-1.0";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	xtal: xtal-clk {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+		clock-output-names = "xtal";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@fff01000 {</div><div class='add'>+			compatible = "arm,gic-400";</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			#address-cells = &lt;0&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			reg = &lt;0x0 0xfff01000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0xfff02000 0 0x0100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 0xf04&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		apb: bus@fe000000 {</div><div class='add'>+			compatible = "simple-bus";</div><div class='add'>+			reg = &lt;0x0 0xfe000000 0x0 0x480000&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges = &lt;0x0 0x0 0x0 0xfe000000 0x0 0x480000&gt;;</div><div class='add'>+</div><div class='add'>+			uart_b: serial@7a000 {</div><div class='add'>+				compatible = "amlogic,s7-uart",</div><div class='add'>+					     "amlogic,meson-s4-uart";</div><div class='add'>+				reg = &lt;0x0 0x7a000 0x0 0x18&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 169 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				clocks = &lt;&amp;xtal&gt;, &lt;&amp;xtal&gt;, &lt;&amp;xtal&gt;;</div><div class='add'>+				clock-names = "xtal", "pclk", "baud";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			periphs_pinctrl: pinctrl@4000 {</div><div class='add'>+				compatible = "amlogic,pinctrl-s7";</div><div class='add'>+				#address-cells = &lt;2&gt;;</div><div class='add'>+				#size-cells = &lt;2&gt;;</div><div class='add'>+				ranges = &lt;0x0 0x0 0x0 0x4000 0x0 0x340&gt;;</div><div class='add'>+</div><div class='add'>+				gpioz: gpio@c0 {</div><div class='add'>+					reg = &lt;0 0xc0 0 0x20&gt;, &lt;0 0x18 0 0x8&gt;;</div><div class='add'>+					reg-names = "gpio", "mux";</div><div class='add'>+					gpio-controller;</div><div class='add'>+					#gpio-cells = &lt;2&gt;;</div><div class='add'>+					gpio-ranges = &lt;&amp;periphs_pinctrl 0 (AMLOGIC_GPIO_Z&lt;&lt;8) 13&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpiox: gpio@100 {</div><div class='add'>+					reg = &lt;0 0x100 0 0x30&gt;, &lt;0 0xc 0 0x8&gt;;</div><div class='add'>+					reg-names = "gpio", "mux";</div><div class='add'>+					gpio-controller;</div><div class='add'>+					#gpio-cells = &lt;2&gt;;</div><div class='add'>+					gpio-ranges = &lt;&amp;periphs_pinctrl 0 (AMLOGIC_GPIO_X&lt;&lt;8) 20&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpioh: gpio@140 {</div><div class='add'>+					reg = &lt;0 0x140 0 0x20&gt;, &lt;0 0x2c 0 0x8&gt;;</div><div class='add'>+					reg-names = "gpio", "mux";</div><div class='add'>+					gpio-controller;</div><div class='add'>+					#gpio-cells = &lt;2&gt;;</div><div class='add'>+					gpio-ranges = &lt;&amp;periphs_pinctrl 0 (AMLOGIC_GPIO_H&lt;&lt;8) 12&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpiod: gpio@180 {</div><div class='add'>+					reg = &lt;0 0x180 0 0x20&gt;, &lt;0 0x40 0 0x8&gt;;</div><div class='add'>+					reg-names = "gpio", "mux";</div><div class='add'>+					gpio-controller;</div><div class='add'>+					#gpio-cells = &lt;2&gt;;</div><div class='add'>+					gpio-ranges = &lt;&amp;periphs_pinctrl 0 (AMLOGIC_GPIO_D&lt;&lt;8) 12&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpioe: gpio@1c0 {</div><div class='add'>+					reg = &lt;0 0x1c0 0 0x20&gt;, &lt;0 0x48 0 0x4&gt;;</div><div class='add'>+					reg-names = "gpio", "mux";</div><div class='add'>+					gpio-controller;</div><div class='add'>+					#gpio-cells = &lt;2&gt;;</div><div class='add'>+					gpio-ranges = &lt;&amp;periphs_pinctrl 0 (AMLOGIC_GPIO_E&lt;&lt;8) 2&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpioc: gpio@200 {</div><div class='add'>+					reg = &lt;0 0x200 0 0x20&gt;, &lt;0 0x24 0 0x4&gt;;</div><div class='add'>+					reg-names = "gpio", "mux";</div><div class='add'>+					gpio-controller;</div><div class='add'>+					#gpio-cells = &lt;2&gt;;</div><div class='add'>+					gpio-ranges = &lt;&amp;periphs_pinctrl 0 (AMLOGIC_GPIO_C&lt;&lt;8) 8&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpiob: gpio@240 {</div><div class='add'>+					reg = &lt;0 0x240 0 0x20&gt;, &lt;0 0x0 0 0x8&gt;;</div><div class='add'>+					reg-names = "gpio", "mux";</div><div class='add'>+					gpio-controller;</div><div class='add'>+					#gpio-cells = &lt;2&gt;;</div><div class='add'>+					gpio-ranges = &lt;&amp;periphs_pinctrl 0 (AMLOGIC_GPIO_B&lt;&lt;8) 14&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				test_n: gpio@2c0 {</div><div class='add'>+					reg = &lt;0 0x2c0 0 0x20&gt;;</div><div class='add'>+					reg-names = "gpio";</div><div class='add'>+					gpio-controller;</div><div class='add'>+					#gpio-cells = &lt;2&gt;;</div><div class='add'>+					gpio-ranges =</div><div class='add'>+						&lt;&amp;periphs_pinctrl 0 (AMLOGIC_GPIO_TEST_N&lt;&lt;8) 1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpiocc: gpio@300 {</div><div class='add'>+					reg = &lt;0 0x300 0 0x20&gt;, &lt;0 0x14 0 0x4&gt;;</div><div class='add'>+					reg-names = "gpio", "mux";</div><div class='add'>+					gpio-controller;</div><div class='add'>+					#gpio-cells = &lt;2&gt;;</div><div class='add'>+					gpio-ranges = &lt;&amp;periphs_pinctrl 0 (AMLOGIC_GPIO_CC&lt;&lt;8) 2&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gpio_intc: interrupt-controller@4080 {</div><div class='add'>+				compatible = "amlogic,s7-gpio-intc",</div><div class='add'>+					     "amlogic,meson-gpio-intc";</div><div class='add'>+				reg = &lt;0x0 0x4080 0x0 0x20&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;2&gt;;</div><div class='add'>+				amlogic,channel-interrupts =</div><div class='add'>+					&lt;10 11 12 13 14 15 16 17 18 19 20 21&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ao-secure@10220 {</div><div class='add'>+				compatible = "amlogic,s7-ao-secure",</div><div class='add'>+					     "amlogic,meson-gx-ao-secure",</div><div class='add'>+					     "syscon";</div><div class='add'>+				reg = &lt;0x0 0x10220 0x0 0x140&gt;;</div><div class='add'>+				amlogic,has-chip-id;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s7d-s905x5m-bm202.dts b/arch/arm64/boot/dts/amlogic/amlogic-s7d-s905x5m-bm202.dts<br/>new file mode 100644<br/>index 000000000000..2933fcdbc8ef<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/amlogic-s7d-s905x5m-bm202.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/amlogic-s7d-s905x5m-bm202.dts</a></div><div class='hunk'>@@ -0,0 +1,41 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2025 Amlogic, Inc. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "amlogic-s7d.dtsi"</div><div class='add'>+/ {</div><div class='add'>+	model = "Amlogic S905X5M BM202 Development Board";</div><div class='add'>+	compatible = "amlogic,bm202", "amlogic,s7d";</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart_b;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x0 0x0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		/* 36 MiB reserved for ARM Trusted Firmware */</div><div class='add'>+		secmon_reserved: secmon@5000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0x0 0x05000000 0x0 0x2400000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s7d.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-s7d.dtsi<br/>new file mode 100644<br/>index 000000000000..0c4417bcd682<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/amlogic-s7d.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/amlogic-s7d.dtsi</a></div><div class='hunk'>@@ -0,0 +1,217 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2025 Amlogic, Inc. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/amlogic,pinctrl.h&gt;</div><div class='add'>+#include &lt;dt-bindings/power/amlogic,s7d-pwrc.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x0 0x0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@100 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x0 0x100&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@200 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x0 0x200&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@300 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x0 0x300&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sm: secure-monitor {</div><div class='add'>+		compatible = "amlogic,meson-gxbb-sm";</div><div class='add'>+</div><div class='add'>+		pwrc: power-controller {</div><div class='add'>+			compatible = "amlogic,s7d-pwrc";</div><div class='add'>+			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-1.0";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	xtal: xtal-clk {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+		clock-output-names = "xtal";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@fff01000 {</div><div class='add'>+			compatible = "arm,gic-400";</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			#address-cells = &lt;0&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			reg = &lt;0x0 0xfff01000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0xfff02000 0 0x0100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 0xf04&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		apb: bus@fe000000 {</div><div class='add'>+			compatible = "simple-bus";</div><div class='add'>+			reg = &lt;0x0 0xfe000000 0x0 0x480000&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges = &lt;0x0 0x0 0x0 0xfe000000 0x0 0x480000&gt;;</div><div class='add'>+</div><div class='add'>+			uart_b: serial@7a000 {</div><div class='add'>+				compatible = "amlogic,s7d-uart",</div><div class='add'>+					     "amlogic,meson-s4-uart";</div><div class='add'>+				reg = &lt;0x0 0x7a000 0x0 0x18&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 169 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				clocks = &lt;&amp;xtal&gt;, &lt;&amp;xtal&gt;, &lt;&amp;xtal&gt;;</div><div class='add'>+				clock-names = "xtal", "pclk", "baud";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			periphs_pinctrl: pinctrl@4000 {</div><div class='add'>+				compatible = "amlogic,pinctrl-s7d",</div><div class='add'>+					     "amlogic,pinctrl-s7";</div><div class='add'>+				#address-cells = &lt;2&gt;;</div><div class='add'>+				#size-cells = &lt;2&gt;;</div><div class='add'>+				ranges = &lt;0x0 0x0 0x0 0x4000 0x0 0x340&gt;;</div><div class='add'>+</div><div class='add'>+				gpioz: gpio@c0 {</div><div class='add'>+					reg = &lt;0 0xc0 0 0x20&gt;, &lt;0 0x18 0 0x8&gt;;</div><div class='add'>+					reg-names = "gpio", "mux";</div><div class='add'>+					gpio-controller;</div><div class='add'>+					#gpio-cells = &lt;2&gt;;</div><div class='add'>+					gpio-ranges = &lt;&amp;periphs_pinctrl 0 (AMLOGIC_GPIO_Z&lt;&lt;8) 13&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpiox: gpio@100 {</div><div class='add'>+					reg = &lt;0 0x100 0 0x30&gt;, &lt;0 0xc 0 0x8&gt;;</div><div class='add'>+					reg-names = "gpio", "mux";</div><div class='add'>+					gpio-controller;</div><div class='add'>+					#gpio-cells = &lt;2&gt;;</div><div class='add'>+					gpio-ranges = &lt;&amp;periphs_pinctrl 0 (AMLOGIC_GPIO_X&lt;&lt;8) 20&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpioh: gpio@140 {</div><div class='add'>+					reg = &lt;0 0x140 0 0x20&gt;, &lt;0 0x2c 0 0x8&gt;;</div><div class='add'>+					reg-names = "gpio", "mux";</div><div class='add'>+					gpio-controller;</div><div class='add'>+					#gpio-cells = &lt;2&gt;;</div><div class='add'>+					gpio-ranges = &lt;&amp;periphs_pinctrl 0 (AMLOGIC_GPIO_H&lt;&lt;8) 12&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpiod: gpio@180 {</div><div class='add'>+					reg = &lt;0 0x180 0 0x20&gt;, &lt;0 0x40 0 0x4&gt;;</div><div class='add'>+					reg-names = "gpio", "mux";</div><div class='add'>+					gpio-controller;</div><div class='add'>+					#gpio-cells = &lt;2&gt;;</div><div class='add'>+					gpio-ranges = &lt;&amp;periphs_pinctrl 0 (AMLOGIC_GPIO_D&lt;&lt;8) 5&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpioe: gpio@1c0 {</div><div class='add'>+					reg = &lt;0 0x1c0 0 0x20&gt;, &lt;0 0x48 0 0x4&gt;;</div><div class='add'>+					reg-names = "gpio", "mux";</div><div class='add'>+					gpio-controller;</div><div class='add'>+					#gpio-cells = &lt;2&gt;;</div><div class='add'>+					gpio-ranges = &lt;&amp;periphs_pinctrl 0 (AMLOGIC_GPIO_E&lt;&lt;8) 2&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpioc: gpio@200 {</div><div class='add'>+					reg = &lt;0 0x200 0 0x20&gt;, &lt;0 0x24 0 0x4&gt;;</div><div class='add'>+					reg-names = "gpio", "mux";</div><div class='add'>+					gpio-controller;</div><div class='add'>+					#gpio-cells = &lt;2&gt;;</div><div class='add'>+					gpio-ranges = &lt;&amp;periphs_pinctrl 0 (AMLOGIC_GPIO_C&lt;&lt;8) 8&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpiob: gpio@240 {</div><div class='add'>+					reg = &lt;0 0x240 0 0x20&gt;, &lt;0 0x0 0 0x8&gt;;</div><div class='add'>+					reg-names = "gpio", "mux";</div><div class='add'>+					gpio-controller;</div><div class='add'>+					#gpio-cells = &lt;2&gt;;</div><div class='add'>+					gpio-ranges = &lt;&amp;periphs_pinctrl 0 (AMLOGIC_GPIO_B&lt;&lt;8) 14&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpiodv: gpio@280 {</div><div class='add'>+					reg = &lt;0 0x280 0 0x20&gt;, &lt;0 0x8 0 0x4&gt;;</div><div class='add'>+					reg-names = "gpio", "mux";</div><div class='add'>+					gpio-controller;</div><div class='add'>+					#gpio-cells = &lt;2&gt;;</div><div class='add'>+					gpio-ranges = &lt;&amp;periphs_pinctrl 0 (AMLOGIC_GPIO_DV&lt;&lt;8) 7&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				test_n: gpio@2c0 {</div><div class='add'>+					reg = &lt;0 0x2c0 0 0x20&gt;;</div><div class='add'>+					reg-names = "gpio";</div><div class='add'>+					gpio-controller;</div><div class='add'>+					#gpio-cells = &lt;2&gt;;</div><div class='add'>+					gpio-ranges =</div><div class='add'>+						&lt;&amp;periphs_pinctrl 0 (AMLOGIC_GPIO_TEST_N&lt;&lt;8) 1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpiocc: gpio@300 {</div><div class='add'>+					reg = &lt;0 0x300 0 0x20&gt;, &lt;0 0x14 0 0x4&gt;;</div><div class='add'>+					reg-names = "gpio", "mux";</div><div class='add'>+					gpio-controller;</div><div class='add'>+					#gpio-cells = &lt;2&gt;;</div><div class='add'>+					gpio-ranges = &lt;&amp;periphs_pinctrl 0 (AMLOGIC_GPIO_CC&lt;&lt;8) 2&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gpio_intc: interrupt-controller@4080 {</div><div class='add'>+				compatible = "amlogic,s7d-gpio-intc",</div><div class='add'>+					     "amlogic,meson-gpio-intc";</div><div class='add'>+				reg = &lt;0x0 0x4080 0x0 0x20&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;2&gt;;</div><div class='add'>+				amlogic,channel-interrupts =</div><div class='add'>+					&lt;10 11 12 13 14 15 16 17 18 19 20 21&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ao-secure@10220 {</div><div class='add'>+				compatible = "amlogic,s7d-ao-secure",</div><div class='add'>+					     "amlogic,meson-gx-ao-secure",</div><div class='add'>+					     "syscon";</div><div class='add'>+				reg = &lt;0x0 0x10220 0x0 0x140&gt;;</div><div class='add'>+				amlogic,has-chip-id;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-an400.dts b/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-an400.dts<br/>new file mode 100644<br/>index 000000000000..c05edebb90b5<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-an400.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-an400.dts</a></div><div class='hunk'>@@ -0,0 +1,39 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2023 Amlogic, Inc. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "amlogic-t7.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Amlogic A311D2 AN400 Development Board";</div><div class='add'>+	compatible = "amlogic,an400", "amlogic,a311d2", "amlogic,t7";</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart_a;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x00000000 0x00000000 0x00000000 0xE0000000</div><div class='add'>+			0x00000001 0x00000000 0x00000000 0x20000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	xtal: xtal-clk {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+		clock-output-names = "xtal";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart_a {</div><div class='add'>+	clocks = &lt;&amp;xtal&gt;, &lt;&amp;xtal&gt;, &lt;&amp;xtal&gt;;</div><div class='add'>+	clock-names = "xtal", "pclk", "baud";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts b/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts<br/>new file mode 100644<br/>index 000000000000..fffdab96b12e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts</a></div><div class='hunk'>@@ -0,0 +1,54 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2022 Wesion, Inc. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "amlogic-t7.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Khadas vim4";</div><div class='add'>+	compatible = "khadas,vim4", "amlogic,a311d2", "amlogic,t7";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart_a;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x0 0x2 0x0&gt;; /* 8 GB */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		/* 3 MiB reserved for ARM Trusted Firmware (BL31) */</div><div class='add'>+		secmon_reserved: secmon@5000000 {</div><div class='add'>+			reg = &lt;0x0 0x05000000 0x0 0x300000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* 32 MiB reserved for ARM Trusted Firmware (BL32) */</div><div class='add'>+		secmon_reserved_bl32: secmon@5300000 {</div><div class='add'>+			reg = &lt;0x0 0x05300000 0x0 0x2000000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	xtal: xtal-clk {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+		clock-output-names = "xtal";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+	clocks = &lt;&amp;xtal&gt;, &lt;&amp;xtal&gt;, &lt;&amp;xtal&gt;;</div><div class='add'>+	clock-names = "xtal", "pclk", "baud";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7-reset.h b/arch/arm64/boot/dts/amlogic/amlogic-t7-reset.h<br/>new file mode 100644<br/>index 000000000000..ec90a11df508<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/amlogic-t7-reset.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/amlogic-t7-reset.h</a></div><div class='hunk'>@@ -0,0 +1,197 @@</div><div class='add'>+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2024 Amlogic, Inc. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __DTS_AMLOGIC_T7_RESET_H</div><div class='add'>+#define __DTS_AMLOGIC_T7_RESET_H</div><div class='add'>+</div><div class='add'>+/* RESET0 */</div><div class='add'>+/*					0-3	*/</div><div class='add'>+#define RESET_USB			4</div><div class='add'>+#define RESET_U2DRD			5</div><div class='add'>+#define RESET_U3DRD			6</div><div class='add'>+#define RESET_U3DRD_PIPE0		7</div><div class='add'>+#define RESET_U2PHY20			8</div><div class='add'>+#define RESET_U2PHY21			9</div><div class='add'>+#define RESET_GDC			10</div><div class='add'>+#define RESET_HDMI20_AES		11</div><div class='add'>+#define RESET_HDMIRX			12</div><div class='add'>+#define RESET_HDMIRX_APB		13</div><div class='add'>+#define RESET_DEWARP			14</div><div class='add'>+/*					15	*/</div><div class='add'>+#define RESET_HDMITX_CAPB3		16</div><div class='add'>+#define RESET_BRG_VCBUG_DEC		17</div><div class='add'>+#define RESET_VCBUS			18</div><div class='add'>+#define RESET_VID_PLL_DIV		19</div><div class='add'>+#define RESET_VDI6			20</div><div class='add'>+#define RESET_GE2D			21</div><div class='add'>+#define RESET_HDMITXPHY			22</div><div class='add'>+#define RESET_VID_LOCK			23</div><div class='add'>+#define RESET_VENC0			24</div><div class='add'>+#define RESET_VDAC			25</div><div class='add'>+#define RESET_VENC2			26</div><div class='add'>+#define RESET_VENC1			27</div><div class='add'>+#define RESET_RDMA			28</div><div class='add'>+#define RESET_HDMITX			29</div><div class='add'>+#define RESET_VIU			30</div><div class='add'>+#define RESET_VENC			31</div><div class='add'>+</div><div class='add'>+/* RESET1 */</div><div class='add'>+#define RESET_AUDIO			32</div><div class='add'>+#define RESET_MALI_CAPB3		33</div><div class='add'>+#define RESET_MALI			34</div><div class='add'>+#define RESET_DDR_APB			35</div><div class='add'>+#define RESET_DDR			36</div><div class='add'>+#define RESET_DOS_CAPB3			37</div><div class='add'>+#define RESET_DOS			38</div><div class='add'>+#define RESET_COMBO_DPHY_CHAN2		39</div><div class='add'>+#define RESET_DEBUG_B			40</div><div class='add'>+#define RESET_DEBUG_A			41</div><div class='add'>+#define RESET_DSP_B			42</div><div class='add'>+#define RESET_DSP_A			43</div><div class='add'>+#define RESET_PCIE_A			44</div><div class='add'>+#define RESET_PCIE_PHY			45</div><div class='add'>+#define RESET_PCIE_APB			46</div><div class='add'>+#define RESET_ANAKIN			47</div><div class='add'>+#define RESET_ETH			48</div><div class='add'>+#define RESET_EDP0_CTRL			49</div><div class='add'>+#define RESET_EDP1_CTRL			50</div><div class='add'>+#define RESET_COMBO_DPHY_CHAN0		51</div><div class='add'>+#define RESET_COMBO_DPHY_CHAN1		52</div><div class='add'>+#define RESET_DSI_LVDS_EDP_TOP		53</div><div class='add'>+#define RESET_PCIE1_PHY			54</div><div class='add'>+#define RESET_PCIE1_APB			55</div><div class='add'>+#define RESET_DDR_1			56</div><div class='add'>+/*					57	*/</div><div class='add'>+#define RESET_EDP1_PIPELINE		58</div><div class='add'>+#define RESET_EDP0_PIPELINE		59</div><div class='add'>+#define RESET_MIPI_DSI1_PHY		60</div><div class='add'>+#define RESET_MIPI_DSI0_PHY		61</div><div class='add'>+#define RESET_MIPI_DSI_A_HOST		62</div><div class='add'>+#define RESET_MIPI_DSI_B_HOST		63</div><div class='add'>+</div><div class='add'>+/* RESET2 */</div><div class='add'>+#define RESET_DEVICE_MMC_ARB		64</div><div class='add'>+#define RESET_IR_CTRL			65</div><div class='add'>+#define RESET_TS_A73			66</div><div class='add'>+#define RESET_TS_A53			67</div><div class='add'>+#define RESET_SPICC_2			68</div><div class='add'>+#define RESET_SPICC_3			69</div><div class='add'>+#define RESET_SPICC_4			70</div><div class='add'>+#define RESET_SPICC_5			71</div><div class='add'>+#define RESET_SMART_CARD		72</div><div class='add'>+#define RESET_SPICC_0			73</div><div class='add'>+#define RESET_SPICC_1			74</div><div class='add'>+#define RESET_RSA			75</div><div class='add'>+/*					76-79	*/</div><div class='add'>+#define RESET_MSR_CLK			80</div><div class='add'>+#define RESET_SPIFC			81</div><div class='add'>+#define RESET_SAR_ADC			82</div><div class='add'>+#define RESET_BT			83</div><div class='add'>+/*					84-87	*/</div><div class='add'>+#define RESET_ACODEC			88</div><div class='add'>+#define RESET_CEC			89</div><div class='add'>+#define RESET_AFIFO			90</div><div class='add'>+#define RESET_WATCHDOG			91</div><div class='add'>+/*					92-95	*/</div><div class='add'>+</div><div class='add'>+/* RESET3 */</div><div class='add'>+#define RESET_BRG_NIC1_GPV		96</div><div class='add'>+#define RESET_BRG_NIC2_GPV		97</div><div class='add'>+#define RESET_BRG_NIC3_GPV		98</div><div class='add'>+#define RESET_BRG_NIC4_GPV		99</div><div class='add'>+#define RESET_BRG_NIC5_GPV		100</div><div class='add'>+/*					101-121	*/</div><div class='add'>+#define RESET_MIPI_ISP			122</div><div class='add'>+#define RESET_BRG_ADB_MALI_1		123</div><div class='add'>+#define RESET_BRG_ADB_MALI_0		124</div><div class='add'>+#define RESET_BRG_ADB_A73		125</div><div class='add'>+#define RESET_BRG_ADB_A53		126</div><div class='add'>+#define RESET_BRG_CCI			127</div><div class='add'>+</div><div class='add'>+/* RESET4 */</div><div class='add'>+#define RESET_PWM_AO_AB			128</div><div class='add'>+#define RESET_PWM_AO_CD			129</div><div class='add'>+#define RESET_PWM_AO_EF			130</div><div class='add'>+#define RESET_PWM_AO_GH			131</div><div class='add'>+#define RESET_PWM_AB			132</div><div class='add'>+#define RESET_PWM_CD			133</div><div class='add'>+#define RESET_PWM_EF			134</div><div class='add'>+/*					135-137	*/</div><div class='add'>+#define RESET_UART_A			138</div><div class='add'>+#define RESET_UART_B			139</div><div class='add'>+#define RESET_UART_C			140</div><div class='add'>+#define RESET_UART_D			141</div><div class='add'>+#define RESET_UART_E			142</div><div class='add'>+#define RESET_UART_F			143</div><div class='add'>+#define RESET_I2C_S_A			144</div><div class='add'>+#define RESET_I2C_M_A			145</div><div class='add'>+#define RESET_I2C_M_B			146</div><div class='add'>+#define RESET_I2C_M_C			147</div><div class='add'>+#define RESET_I2C_M_D			148</div><div class='add'>+#define RESET_I2C_M_E			149</div><div class='add'>+#define RESET_I2C_M_F			150</div><div class='add'>+#define RESET_I2C_M_AO_A		151</div><div class='add'>+#define RESET_SD_EMMC_A			152</div><div class='add'>+#define RESET_SD_EMMC_B			153</div><div class='add'>+#define RESET_SD_EMMC_C			154</div><div class='add'>+#define RESET_I2C_M_AO_B		155</div><div class='add'>+#define RESET_TS_GPU			156</div><div class='add'>+#define RESET_TS_NNA			157</div><div class='add'>+#define RESET_TS_VPN			158</div><div class='add'>+#define RESET_TS_HEVC			159</div><div class='add'>+</div><div class='add'>+/* RESET5 */</div><div class='add'>+#define RESET_BRG_NOC_DDR_1		160</div><div class='add'>+#define RESET_BRG_NOC_DDR_0		161</div><div class='add'>+#define RESET_BRG_NOC_MAIN		162</div><div class='add'>+#define RESET_BRG_NOC_ALL		163</div><div class='add'>+/*					164-167	*/</div><div class='add'>+#define RESET_BRG_NIC2_SYS		168</div><div class='add'>+#define RESET_BRG_NIC2_MAIN		169</div><div class='add'>+#define RESET_BRG_NIC2_HDMI		170</div><div class='add'>+#define RESET_BRG_NIC2_ALL		171</div><div class='add'>+#define RESET_BRG_NIC3_WAVE		172</div><div class='add'>+#define RESET_BRG_NIC3_VDEC		173</div><div class='add'>+#define RESET_BRG_NIC3_HEVCF		174</div><div class='add'>+#define RESET_BRG_NIC3_HEVCB		175</div><div class='add'>+#define RESET_BRG_NIC3_HCODEC		176</div><div class='add'>+#define RESET_BRG_NIC3_GE2D		177</div><div class='add'>+#define RESET_BRG_NIC3_GDC		178</div><div class='add'>+#define RESET_BRG_NIC3_AMLOGIC		179</div><div class='add'>+#define RESET_BRG_NIC3_MAIN		180</div><div class='add'>+#define RESET_BRG_NIC3_ALL		181</div><div class='add'>+#define RESET_BRG_NIC5_VPU		182</div><div class='add'>+/*					183-185	*/</div><div class='add'>+#define RESET_BRG_NIC4_DSPB		186</div><div class='add'>+#define RESET_BRG_NIC4_DSPA		187</div><div class='add'>+#define RESET_BRG_NIC4_VAPB		188</div><div class='add'>+#define RESET_BRG_NIC4_CLK81		189</div><div class='add'>+#define RESET_BRG_NIC4_MAIN		190</div><div class='add'>+#define RESET_BRG_NIC4_ALL		191</div><div class='add'>+</div><div class='add'>+/* RESET6 */</div><div class='add'>+#define RESET_BRG_VDEC_PIPEL		192</div><div class='add'>+#define RESET_BRG_HEVCF_DMC_PIPEL	193</div><div class='add'>+#define RESET_BRG_NIC2TONIC4_PIPEL	194</div><div class='add'>+#define RESET_BRG_HDMIRXTONIC2_PIPEL	195</div><div class='add'>+#define RESET_BRG_SECTONIC4_PIPEL	196</div><div class='add'>+#define RESET_BRG_VPUTONOC_PIPEL	197</div><div class='add'>+#define RESET_BRG_NIC4TONOC_PIPEL	198</div><div class='add'>+#define RESET_BRG_NIC3TONOC_PIPEL	199</div><div class='add'>+#define RESET_BRG_NIC2TONOC_PIPEL	200</div><div class='add'>+#define RESET_BRG_NNATONOC_PIPEL	201</div><div class='add'>+#define RESET_BRG_FRISP3_PIPEL		202</div><div class='add'>+#define RESET_BRG_FRISP2_PIPEL		203</div><div class='add'>+#define RESET_BRG_FRISP1_PIPEL		204</div><div class='add'>+#define RESET_BRG_FRISP0_PIPEL		205</div><div class='add'>+/*					206-217	*/</div><div class='add'>+#define RESET_BRG_AMPIPE_NAND		218</div><div class='add'>+#define RESET_BRG_AMPIPE_ETH		219</div><div class='add'>+/*					220	*/</div><div class='add'>+#define RESET_BRG_AM2AXI0		221</div><div class='add'>+#define RESET_BRG_AM2AXI1		222</div><div class='add'>+#define RESET_BRG_AM2AXI2		223</div><div class='add'>+</div><div class='add'>+#endif /* ___DTS_AMLOGIC_T7_RESET_H */</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi<br/>new file mode 100644<br/>index 000000000000..6510068bcff9<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi</a></div><div class='hunk'>@@ -0,0 +1,282 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/power/amlogic,t7-pwrc.h&gt;</div><div class='add'>+#include "amlogic-t7-reset.h"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;0x2&gt;;</div><div class='add'>+		#size-cells = &lt;0x0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu-map {</div><div class='add'>+			cluster0 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu100&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu101&gt;;</div><div class='add'>+				};</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu102&gt;;</div><div class='add'>+				};</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu103&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cluster1 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu0&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu1&gt;;</div><div class='add'>+				};</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu2&gt;;</div><div class='add'>+				};</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu3&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu100: cpu@100 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x0 0x100&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			d-cache-line-size = &lt;32&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-sets = &lt;32&gt;;</div><div class='add'>+			i-cache-line-size = &lt;32&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-sets = &lt;32&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_l&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu101: cpu@101 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x0 0x101&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			d-cache-line-size = &lt;32&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-sets = &lt;32&gt;;</div><div class='add'>+			i-cache-line-size = &lt;32&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-sets = &lt;32&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_l&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu102: cpu@102 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x0 0x102&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			d-cache-line-size = &lt;32&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-sets = &lt;32&gt;;</div><div class='add'>+			i-cache-line-size = &lt;32&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-sets = &lt;32&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_l&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu103: cpu@103 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x0 0x103&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			d-cache-line-size = &lt;32&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-sets = &lt;32&gt;;</div><div class='add'>+			i-cache-line-size = &lt;32&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-sets = &lt;32&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_l&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a73";</div><div class='add'>+			reg = &lt;0x0 0x0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			d-cache-sets = &lt;64&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			i-cache-sets = &lt;64&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_b&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@1 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a73";</div><div class='add'>+			reg = &lt;0x0 0x1&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			d-cache-sets = &lt;64&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			i-cache-sets = &lt;64&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_b&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@2 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a73";</div><div class='add'>+			reg = &lt;0x0 0x2&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			d-cache-sets = &lt;64&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			i-cache-sets = &lt;64&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_b&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@3 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a73";</div><div class='add'>+			reg = &lt;0x0 0x3&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			d-cache-sets = &lt;64&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			i-cache-sets = &lt;64&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_b&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_cache_l: l2-cache-cluster0 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x40000&gt;;  /* L2. 256 KB */</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;512&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_cache_b: l2-cache-cluster1 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x100000&gt;; /* L2. 1 Mb */</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;512&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-1.0";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sm: secure-monitor {</div><div class='add'>+		compatible = "amlogic,meson-gxbb-sm";</div><div class='add'>+</div><div class='add'>+		pwrc: power-controller {</div><div class='add'>+			compatible = "amlogic,t7-pwrc";</div><div class='add'>+			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@fff01000 {</div><div class='add'>+			compatible = "arm,gic-400";</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			#address-cells = &lt;0&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			reg = &lt;0x0 0xfff01000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0xfff02000 0 0x0100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		apb4: bus@fe000000 {</div><div class='add'>+			compatible = "simple-bus";</div><div class='add'>+			reg = &lt;0x0 0xfe000000 0x0 0x480000&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges = &lt;0x0 0x0 0x0 0xfe000000 0x0 0x480000&gt;;</div><div class='add'>+</div><div class='add'>+			reset: reset-controller@2000 {</div><div class='add'>+				compatible = "amlogic,t7-reset";</div><div class='add'>+				reg = &lt;0x0 0x2000 0x0 0x98&gt;;</div><div class='add'>+				#reset-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			watchdog@2100 {</div><div class='add'>+				compatible = "amlogic,t7-wdt";</div><div class='add'>+				reg = &lt;0x0 0x2100 0x0 0x10&gt;;</div><div class='add'>+				clocks = &lt;&amp;xtal&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			periphs_pinctrl: pinctrl@4000 {</div><div class='add'>+				compatible = "amlogic,t7-periphs-pinctrl";</div><div class='add'>+				#address-cells = &lt;2&gt;;</div><div class='add'>+				#size-cells = &lt;2&gt;;</div><div class='add'>+				ranges;</div><div class='add'>+</div><div class='add'>+				gpio: bank@4000 {</div><div class='add'>+					reg = &lt;0x0 0x4000 0x0 0x0064&gt;,</div><div class='add'>+					      &lt;0x0 0x40c0 0x0 0x0220&gt;;</div><div class='add'>+					reg-names = "mux", "gpio";</div><div class='add'>+					gpio-controller;</div><div class='add'>+					#gpio-cells = &lt;2&gt;;</div><div class='add'>+					gpio-ranges = &lt;&amp;periphs_pinctrl 0 0 157&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gpio_intc: interrupt-controller@4080 {</div><div class='add'>+				compatible = "amlogic,t7-gpio-intc",</div><div class='add'>+					     "amlogic,meson-gpio-intc";</div><div class='add'>+				reg = &lt;0x0 0x4080 0x0 0x20&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;2&gt;;</div><div class='add'>+				amlogic,channel-interrupts =</div><div class='add'>+					&lt;10 11 12 13 14 15 16 17 18 19 20 21&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart_a: serial@78000 {</div><div class='add'>+				compatible = "amlogic,t7-uart", "amlogic,meson-s4-uart";</div><div class='add'>+				reg = &lt;0x0 0x78000 0x0 0x18&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 168 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sec_ao: ao-secure@10220 {</div><div class='add'>+				compatible = "amlogic,t7-ao-secure",</div><div class='add'>+					     "amlogic,meson-gx-ao-secure",</div><div class='add'>+					     "syscon";</div><div class='add'>+				reg = &lt;0x0 0x10220 0x0 0x140&gt;;</div><div class='add'>+				amlogic,has-chip-id;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-a1-ad402.dts b/arch/arm64/boot/dts/amlogic/meson-a1-ad402.dts<br/>new file mode 100644<br/>index 000000000000..0d92f5253b64<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-a1-ad402.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-a1-ad402.dts</a></div><div class='hunk'>@@ -0,0 +1,192 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2023 SberDevices</div><div class='add'>+ * Author: Dmitry Rokosov &lt;ddrokosov@sberdevices.ru&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "meson-a1.dtsi"</div><div class='add'>+#include &lt;dt-bindings/thermal/thermal.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "amlogic,ad402", "amlogic,a1";</div><div class='add'>+	model = "Amlogic Meson A1 AD402 Development Board";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart_AO_B;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x0 0x0 0x8000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		/* 3 MiB reserved for Amlogic Trust OS (BL32) */</div><div class='add'>+		secos_reserved: secos@3d00000 {</div><div class='add'>+			reg = &lt;0x0 0x03d00000 0x0 0x300000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	firmware {</div><div class='add'>+		optee {</div><div class='add'>+			compatible = "linaro,optee-tz";</div><div class='add'>+			method = "smc";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	battery_4v2: regulator-battery-4v2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "4V2";</div><div class='add'>+		regulator-min-microvolt = &lt;4200000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;4200000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddq_1v35: regulator-vddq-1v35 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDQ_1V35";</div><div class='add'>+		regulator-min-microvolt = &lt;1350000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1350000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;battery_4v2&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddao_3v3: regulator-vddao-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDAO_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;battery_4v2&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vcc_3v3: regulator-vcc-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCC_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddio_1v8: regulator-vddio-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDIO_1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	thermal-zones {</div><div class='add'>+		soc_thermal: soc-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;100&gt;;</div><div class='add'>+			sustainable-power = &lt;130&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;cpu_temp&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				soc_passive: soc-passive {</div><div class='add'>+					temperature = &lt;70000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				soc_hot: soc-hot {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				soc_critical: soc-critical {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			soc_cooling_maps: cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;soc_passive&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				map1 {</div><div class='add'>+					trip = &lt;&amp;soc_hot&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Bluetooth HCI H4 */</div><div class='add'>+&amp;uart_AO {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart_a_pins&gt;, &lt;&amp;uart_a_cts_rts_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart_AO_B {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;saradc {</div><div class='add'>+	status = "okay";</div><div class='add'>+	vref-supply = &lt;&amp;vddio_1v8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spifc {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;spifc_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	flash@0 {</div><div class='add'>+		compatible = "spi-nand";</div><div class='add'>+		status = "okay";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;96000000&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;4&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb2_phy1 {</div><div class='add'>+	phy-supply = &lt;&amp;vcc_3v3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb {</div><div class='add'>+	status = "okay";</div><div class='add'>+	dr_mode = "peripheral";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sd_emmc {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdio_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;sdio_clk_gate_pins&gt;;</div><div class='add'>+	pinctrl-names = "default", "clk-gate";</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	sd-uhs-sdr104;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	disable-wp;</div><div class='add'>+</div><div class='add'>+	vmmc-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;vddio_1v8&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi<br/>index 755b4ad15184..27b68ed85c4c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-a1.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-a1.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-a1.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-a1.dtsi</a></div><div class='hunk'>@@ -3,9 +3,13 @@</div><div class='ctx'>  * Copyright (c) 2019 Amlogic, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='del'>-#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/amlogic,a1-pll-clkc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/amlogic,a1-peripherals-clkc.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/gpio/meson-a1-gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/power/meson-a1-power.h&gt;</div><div class='add'>+#include &lt;dt-bindings/reset/amlogic,meson-a1-reset.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	compatible = "amlogic,a1";</div><div class='hunk'>@@ -23,7 +27,14 @@</div><div class='ctx'> 			compatible = "arm,cortex-a35";</div><div class='ctx'> 			reg = &lt;0x0 0x0&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			d-cache-line-size = &lt;32&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-sets = &lt;32&gt;;</div><div class='add'>+			i-cache-line-size = &lt;32&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-sets = &lt;32&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;l2&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu1: cpu@1 {</div><div class='hunk'>@@ -31,14 +42,35 @@</div><div class='ctx'> 			compatible = "arm,cortex-a35";</div><div class='ctx'> 			reg = &lt;0x0 0x1&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			d-cache-line-size = &lt;32&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-sets = &lt;32&gt;;</div><div class='add'>+			i-cache-line-size = &lt;32&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-sets = &lt;32&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;l2&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		l2: l2-cache0 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x80000&gt;; /* L2. 512 KB */</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;512&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	efuse: efuse {</div><div class='add'>+		compatible = "amlogic,meson-gxbb-efuse";</div><div class='add'>+		clocks = &lt;&amp;clkc_periphs CLKID_OTP&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		secure-monitor = &lt;&amp;sm&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pwrc PWRC_OTP_ID&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	psci {</div><div class='ctx'> 		compatible = "arm,psci-1.0";</div><div class='ctx'> 		method = "smc";</div><div class='hunk'>@@ -64,7 +96,6 @@</div><div class='ctx'> 		pwrc: power-controller {</div><div class='ctx'> 			compatible = "amlogic,meson-a1-pwrc";</div><div class='ctx'> 			#power-domain-cells = &lt;1&gt;;</div><div class='del'>-			status = "okay";</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -74,6 +105,16 @@</div><div class='ctx'> 		#size-cells = &lt;2&gt;;</div><div class='ctx'> 		ranges;</div><div class='ctx'> </div><div class='add'>+		spifc: spi@fd000400 {</div><div class='add'>+			compatible = "amlogic,a1-spifc";</div><div class='add'>+			reg = &lt;0x0 0xfd000400 0x0 0x290&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkc_periphs CLKID_SPIFC&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;pwrc PWRC_SPIFC_ID&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		apb: bus@fe000000 {</div><div class='ctx'> 			compatible = "simple-bus";</div><div class='ctx'> 			reg = &lt;0x0 0xfe000000 0x0 0x1000000&gt;;</div><div class='hunk'>@@ -81,20 +122,19 @@</div><div class='ctx'> 			#size-cells = &lt;2&gt;;</div><div class='ctx'> 			ranges = &lt;0x0 0x0 0x0 0xfe000000 0x0 0x1000000&gt;;</div><div class='ctx'> </div><div class='del'>-</div><div class='ctx'> 			reset: reset-controller@0 {</div><div class='ctx'> 				compatible = "amlogic,meson-a1-reset";</div><div class='ctx'> 				reg = &lt;0x0 0x0 0x0 0x8c&gt;;</div><div class='ctx'> 				#reset-cells = &lt;1&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			periphs_pinctrl: pinctrl@0400 {</div><div class='add'>+			periphs_pinctrl: pinctrl@400 {</div><div class='ctx'> 				compatible = "amlogic,meson-a1-periphs-pinctrl";</div><div class='ctx'> 				#address-cells = &lt;2&gt;;</div><div class='ctx'> 				#size-cells = &lt;2&gt;;</div><div class='ctx'> 				ranges;</div><div class='ctx'> </div><div class='del'>-				gpio: bank@0400 {</div><div class='add'>+				gpio: bank@400 {</div><div class='ctx'> 					reg = &lt;0x0 0x0400 0x0 0x003c&gt;,</div><div class='ctx'> 					      &lt;0x0 0x0480 0x0 0x0118&gt;;</div><div class='ctx'> 					reg-names = "mux", "gpio";</div><div class='hunk'>@@ -103,10 +143,383 @@</div><div class='ctx'> 					gpio-ranges = &lt;&amp;periphs_pinctrl 0 0 62&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='add'>+				i2c0_f11_pins: i2c0-f11 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "i2c0_sck_f11",</div><div class='add'>+							 "i2c0_sda_f12";</div><div class='add'>+						function = "i2c0";</div><div class='add'>+						bias-pull-up;</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				i2c0_f9_pins: i2c0-f9 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "i2c0_sck_f9",</div><div class='add'>+							 "i2c0_sda_f10";</div><div class='add'>+						function = "i2c0";</div><div class='add'>+						bias-pull-up;</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				i2c1_x_pins: i2c1-x {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "i2c1_sck_x",</div><div class='add'>+							 "i2c1_sda_x";</div><div class='add'>+						function = "i2c1";</div><div class='add'>+						bias-pull-up;</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				i2c1_a_pins: i2c1-a {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "i2c1_sck_a",</div><div class='add'>+							 "i2c1_sda_a";</div><div class='add'>+						function = "i2c1";</div><div class='add'>+						bias-pull-up;</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				i2c2_x0_pins: i2c2-x0 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "i2c2_sck_x0",</div><div class='add'>+							 "i2c2_sda_x1";</div><div class='add'>+						function = "i2c2";</div><div class='add'>+						bias-pull-up;</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				i2c2_x15_pins: i2c2-x15 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "i2c2_sck_x15",</div><div class='add'>+							 "i2c2_sda_x16";</div><div class='add'>+						function = "i2c2";</div><div class='add'>+						bias-pull-up;</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				i2c2_a4_pins: i2c2-a4 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "i2c2_sck_a4",</div><div class='add'>+							 "i2c2_sda_a5";</div><div class='add'>+						function = "i2c2";</div><div class='add'>+						bias-pull-up;</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				i2c2_a8_pins: i2c2-a8 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "i2c2_sck_a8",</div><div class='add'>+							 "i2c2_sda_a9";</div><div class='add'>+						function = "i2c2";</div><div class='add'>+						bias-pull-up;</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				i2c3_x_pins: i2c3-x {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "i2c3_sck_x",</div><div class='add'>+							 "i2c3_sda_x";</div><div class='add'>+						function = "i2c3";</div><div class='add'>+						bias-pull-up;</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				i2c3_f_pins: i2c3-f {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "i2c3_sck_f",</div><div class='add'>+							 "i2c3_sda_f";</div><div class='add'>+						function = "i2c3";</div><div class='add'>+						bias-pull-up;</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				uart_a_pins: uart-a {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "uart_a_tx",</div><div class='add'>+							 "uart_a_rx";</div><div class='add'>+						function = "uart_a";</div><div class='add'>+						bias-pull-up;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				uart_a_cts_rts_pins: uart-a-cts-rts {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "uart_a_cts",</div><div class='add'>+							 "uart_a_rts";</div><div class='add'>+						function = "uart_a";</div><div class='add'>+						bias-pull-down;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_a_pins1: pwm-a-pins1 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_a_x6";</div><div class='add'>+						function = "pwm_a";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_a_pins2: pwm-a-pins2 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_a_x7";</div><div class='add'>+						function = "pwm_a";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_a_pins3: pwm-a-pins3 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_a_f10";</div><div class='add'>+						function = "pwm_a";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_a_pins4: pwm-a-pins4 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_a_f6";</div><div class='add'>+						function = "pwm_a";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_a_pins5: pwm-a-pins5 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_a_a";</div><div class='add'>+						function = "pwm_a";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_b_pins1: pwm-b-pins1 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_b_x";</div><div class='add'>+						function = "pwm_b";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_b_pins2: pwm-b-pins2 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_b_f";</div><div class='add'>+						function = "pwm_b";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_b_pins3: pwm-b-pins3 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_b_a";</div><div class='add'>+						function = "pwm_b";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_c_pins1: pwm-c-pins1 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_c_x";</div><div class='add'>+						function = "pwm_c";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_c_pins2: pwm-c-pins2 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_c_f3";</div><div class='add'>+						function = "pwm_c";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_c_pins3: pwm-c-pins3 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_c_f8";</div><div class='add'>+						function = "pwm_c";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_c_pins4: pwm-c-pins4 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_c_a";</div><div class='add'>+						function = "pwm_c";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_d_pins1: pwm-d-pins1 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_d_x15";</div><div class='add'>+						function = "pwm_d";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_d_pins2: pwm-d-pins2 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_d_x13";</div><div class='add'>+						function = "pwm_d";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_d_pins3: pwm-d-pins3 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_d_x10";</div><div class='add'>+						function = "pwm_d";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_d_pins4: pwm-d-pins4 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_d_f";</div><div class='add'>+						function = "pwm_d";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_e_pins1: pwm-e-pins1 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_e_p";</div><div class='add'>+						function = "pwm_e";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_e_pins2: pwm-e-pins2 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_e_x16";</div><div class='add'>+						function = "pwm_e";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_e_pins3: pwm-e-pins3 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_e_x14";</div><div class='add'>+						function = "pwm_e";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_e_pins4: pwm-e-pins4 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_e_x2";</div><div class='add'>+						function = "pwm_e";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_e_pins5: pwm-e-pins5 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_e_f";</div><div class='add'>+						function = "pwm_e";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_e_pins6: pwm-e-pins6 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_e_a";</div><div class='add'>+						function = "pwm_e";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_f_pins1: pwm-f-pins1 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_f_b";</div><div class='add'>+						function = "pwm_f";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_f_pins2: pwm-f-pins2 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_f_x";</div><div class='add'>+						function = "pwm_f";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_f_pins3: pwm-f-pins3 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_f_f4";</div><div class='add'>+						function = "pwm_f";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_f_pins4: pwm-f-pins4 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_f_f12";</div><div class='add'>+						function = "pwm_f";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				sdio_pins: sdio {</div><div class='add'>+					mux0 {</div><div class='add'>+						groups = "sdcard_d0_x",</div><div class='add'>+							 "sdcard_d1_x",</div><div class='add'>+							 "sdcard_d2_x",</div><div class='add'>+							 "sdcard_d3_x",</div><div class='add'>+							 "sdcard_cmd_x";</div><div class='add'>+						function = "sdcard";</div><div class='add'>+						bias-pull-up;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					mux1 {</div><div class='add'>+						groups = "sdcard_clk_x";</div><div class='add'>+						function = "sdcard";</div><div class='add'>+						bias-disable;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				sdio_clk_gate_pins: sdio-clk-gate {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "sdcard_clk_x";</div><div class='add'>+						function = "sdcard";</div><div class='add'>+						bias-pull-down;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				spifc_pins: spifc {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "spif_mo",</div><div class='add'>+							 "spif_mi",</div><div class='add'>+							 "spif_clk",</div><div class='add'>+							 "spif_cs",</div><div class='add'>+							 "spif_hold_n",</div><div class='add'>+							 "spif_wp_n";</div><div class='add'>+						function = "spif";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gpio_intc: interrupt-controller@440 {</div><div class='add'>+				compatible = "amlogic,meson-a1-gpio-intc",</div><div class='add'>+					     "amlogic,meson-gpio-intc";</div><div class='add'>+				reg = &lt;0x0 0x0440 0x0 0x14&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;2&gt;;</div><div class='add'>+				amlogic,channel-interrupts =</div><div class='add'>+					&lt;49 50 51 52 53 54 55 56&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			clkc_periphs: clock-controller@800 {</div><div class='add'>+				compatible = "amlogic,a1-peripherals-clkc";</div><div class='add'>+				reg = &lt;0 0x800 0 0x104&gt;;</div><div class='add'>+				#clock-cells = &lt;1&gt;;</div><div class='add'>+				clocks = &lt;&amp;clkc_pll CLKID_FCLK_DIV2&gt;,</div><div class='add'>+					 &lt;&amp;clkc_pll CLKID_FCLK_DIV3&gt;,</div><div class='add'>+					 &lt;&amp;clkc_pll CLKID_FCLK_DIV5&gt;,</div><div class='add'>+					 &lt;&amp;clkc_pll CLKID_FCLK_DIV7&gt;,</div><div class='add'>+					 &lt;&amp;clkc_pll CLKID_HIFI_PLL&gt;,</div><div class='add'>+					 &lt;&amp;xtal&gt;;</div><div class='add'>+				clock-names = "fclk_div2", "fclk_div3",</div><div class='add'>+					      "fclk_div5", "fclk_div7",</div><div class='add'>+					      "hifi_pll", "xtal";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c0: i2c@1400 {</div><div class='add'>+				compatible = "amlogic,meson-axg-i2c";</div><div class='add'>+				status = "disabled";</div><div class='add'>+				reg = &lt;0x0 0x1400 0x0 0x20&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 32 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;clkc_periphs CLKID_I2C_M_A&gt;;</div><div class='add'>+				power-domains = &lt;&amp;pwrc PWRC_I2C_ID&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			uart_AO: serial@1c00 {</div><div class='del'>-				compatible = "amlogic,meson-gx-uart",</div><div class='add'>+				compatible = "amlogic,meson-a1-uart",</div><div class='ctx'> 					     "amlogic,meson-ao-uart";</div><div class='ctx'> 				reg = &lt;0x0 0x1c00 0x0 0x18&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 25 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='hunk'>@@ -116,7 +529,7 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			uart_AO_B: serial@2000 {</div><div class='del'>-				compatible = "amlogic,meson-gx-uart",</div><div class='add'>+				compatible = "amlogic,meson-a1-uart",</div><div class='ctx'> 					     "amlogic,meson-ao-uart";</div><div class='ctx'> 				reg = &lt;0x0 0x2000 0x0 0x18&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 26 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='hunk'>@@ -124,6 +537,196 @@</div><div class='ctx'> 				clock-names = "xtal", "pclk", "baud";</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='add'>+</div><div class='add'>+			pwm_ab: pwm@2400 {</div><div class='add'>+				compatible = "amlogic,meson-a1-pwm",</div><div class='add'>+					     "amlogic,meson-s4-pwm";</div><div class='add'>+				reg = &lt;0x0 0x2400 0x0 0x24&gt;;</div><div class='add'>+				#pwm-cells = &lt;3&gt;;</div><div class='add'>+				clocks = &lt;&amp;clkc_periphs CLKID_PWM_A&gt;,</div><div class='add'>+					 &lt;&amp;clkc_periphs CLKID_PWM_B&gt;;</div><div class='add'>+				power-domains = &lt;&amp;pwrc PWRC_I2C_ID&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pwm_cd: pwm@2800 {</div><div class='add'>+				compatible = "amlogic,meson-a1-pwm",</div><div class='add'>+					     "amlogic,meson-s4-pwm";</div><div class='add'>+				reg = &lt;0x0 0x2800 0x0 0x24&gt;;</div><div class='add'>+				#pwm-cells = &lt;3&gt;;</div><div class='add'>+				clocks = &lt;&amp;clkc_periphs CLKID_PWM_C&gt;,</div><div class='add'>+					 &lt;&amp;clkc_periphs CLKID_PWM_D&gt;;</div><div class='add'>+				power-domains = &lt;&amp;pwrc PWRC_I2C_ID&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			saradc: adc@2c00 {</div><div class='add'>+				compatible = "amlogic,meson-g12a-saradc",</div><div class='add'>+					"amlogic,meson-saradc";</div><div class='add'>+				reg = &lt;0x0 0x2c00 0x0 0x48&gt;;</div><div class='add'>+				#io-channel-cells = &lt;1&gt;;</div><div class='add'>+				power-domains = &lt;&amp;pwrc PWRC_I2C_ID&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 35 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				clocks = &lt;&amp;xtal&gt;,</div><div class='add'>+					&lt;&amp;clkc_periphs CLKID_SARADC_EN&gt;,</div><div class='add'>+					&lt;&amp;clkc_periphs CLKID_SARADC&gt;,</div><div class='add'>+					&lt;&amp;clkc_periphs CLKID_SARADC_SEL&gt;;</div><div class='add'>+				clock-names = "clkin", "core",</div><div class='add'>+					"adc_clk", "adc_sel";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c1: i2c@5c00 {</div><div class='add'>+				compatible = "amlogic,meson-axg-i2c";</div><div class='add'>+				status = "disabled";</div><div class='add'>+				reg = &lt;0x0 0x5c00 0x0 0x20&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 68 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;clkc_periphs CLKID_I2C_M_B&gt;;</div><div class='add'>+				power-domains = &lt;&amp;pwrc PWRC_I2C_ID&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c2: i2c@6800 {</div><div class='add'>+				compatible = "amlogic,meson-axg-i2c";</div><div class='add'>+				status = "disabled";</div><div class='add'>+				reg = &lt;0x0 0x6800 0x0 0x20&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 76 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;clkc_periphs CLKID_I2C_M_C&gt;;</div><div class='add'>+				power-domains = &lt;&amp;pwrc PWRC_I2C_ID&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c3: i2c@6c00 {</div><div class='add'>+				compatible = "amlogic,meson-axg-i2c";</div><div class='add'>+				status = "disabled";</div><div class='add'>+				reg = &lt;0x0 0x6c00 0x0 0x20&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 78 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;clkc_periphs CLKID_I2C_M_D&gt;;</div><div class='add'>+				power-domains = &lt;&amp;pwrc PWRC_I2C_ID&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			usb2_phy1: phy@4000 {</div><div class='add'>+				compatible = "amlogic,a1-usb2-phy";</div><div class='add'>+				clocks = &lt;&amp;clkc_periphs CLKID_USB_PHY_IN&gt;;</div><div class='add'>+				clock-names = "xtal";</div><div class='add'>+				reg = &lt;0x0 0x4000 0x0 0x60&gt;;</div><div class='add'>+				resets = &lt;&amp;reset RESET_USBPHY&gt;;</div><div class='add'>+				reset-names = "phy";</div><div class='add'>+				#phy-cells = &lt;0&gt;;</div><div class='add'>+				power-domains = &lt;&amp;pwrc PWRC_USB_ID&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cpu_temp: temperature-sensor@4c00 {</div><div class='add'>+				compatible = "amlogic,a1-cpu-thermal";</div><div class='add'>+				reg = &lt;0x0 0x4c00 0x0 0x50&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clkc_periphs CLKID_TS&gt;;</div><div class='add'>+				assigned-clocks = &lt;&amp;clkc_periphs CLKID_TS&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;500000&gt;;</div><div class='add'>+				#thermal-sensor-cells = &lt;0&gt;;</div><div class='add'>+				amlogic,ao-secure = &lt;&amp;sec_AO&gt;;</div><div class='add'>+				power-domains = &lt;&amp;pwrc PWRC_I2C_ID&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			hwrng: rng@5118 {</div><div class='add'>+				compatible = "amlogic,meson-rng";</div><div class='add'>+				reg = &lt;0x0 0x5118 0x0 0x4&gt;;</div><div class='add'>+				power-domains = &lt;&amp;pwrc PWRC_OTP_ID&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sec_AO: ao-secure@5a20 {</div><div class='add'>+				compatible = "amlogic,meson-gx-ao-secure", "syscon";</div><div class='add'>+				reg = &lt;0x0 0x5a20 0x0 0x140&gt;;</div><div class='add'>+				amlogic,has-chip-id;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pwm_ef: pwm@5400 {</div><div class='add'>+				compatible = "amlogic,meson-a1-pwm",</div><div class='add'>+					     "amlogic,meson-s4-pwm";</div><div class='add'>+				reg = &lt;0x0 0x5400 0x0 0x24&gt;;</div><div class='add'>+				#pwm-cells = &lt;3&gt;;</div><div class='add'>+				clocks = &lt;&amp;clkc_periphs CLKID_PWM_E&gt;,</div><div class='add'>+					 &lt;&amp;clkc_periphs CLKID_PWM_F&gt;;</div><div class='add'>+				power-domains = &lt;&amp;pwrc PWRC_I2C_ID&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			clkc_pll: pll-clock-controller@7c80 {</div><div class='add'>+				compatible = "amlogic,a1-pll-clkc";</div><div class='add'>+				reg = &lt;0 0x7c80 0 0x18c&gt;;</div><div class='add'>+				#clock-cells = &lt;1&gt;;</div><div class='add'>+				clocks = &lt;&amp;clkc_periphs CLKID_FIXPLL_IN&gt;,</div><div class='add'>+					 &lt;&amp;clkc_periphs CLKID_HIFIPLL_IN&gt;;</div><div class='add'>+				clock-names = "fixpll_in", "hifipll_in";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sd_emmc: mmc@10000 {</div><div class='add'>+				compatible = "amlogic,meson-axg-mmc";</div><div class='add'>+				reg = &lt;0x0 0x10000 0x0 0x800&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clkc_periphs CLKID_SD_EMMC_A&gt;,</div><div class='add'>+					 &lt;&amp;clkc_periphs CLKID_SD_EMMC&gt;,</div><div class='add'>+					 &lt;&amp;clkc_pll CLKID_FCLK_DIV2&gt;;</div><div class='add'>+				clock-names = "core",</div><div class='add'>+					      "clkin0",</div><div class='add'>+					      "clkin1";</div><div class='add'>+				assigned-clocks = &lt;&amp;clkc_periphs CLKID_SD_EMMC_SEL2&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;xtal&gt;;</div><div class='add'>+				resets = &lt;&amp;reset RESET_SD_EMMC_A&gt;;</div><div class='add'>+				power-domains = &lt;&amp;pwrc PWRC_SD_EMMC_ID&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb: usb@fe004400 {</div><div class='add'>+			status = "disabled";</div><div class='add'>+			compatible = "amlogic,meson-a1-usb-ctrl";</div><div class='add'>+			reg = &lt;0x0 0xfe004400 0x0 0xa0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;clkc_periphs CLKID_USB_CTRL&gt;,</div><div class='add'>+				 &lt;&amp;clkc_periphs CLKID_USB_BUS&gt;,</div><div class='add'>+				 &lt;&amp;clkc_periphs CLKID_USB_CTRL_IN&gt;;</div><div class='add'>+			clock-names = "usb_ctrl", "usb_bus", "xtal_usb_ctrl";</div><div class='add'>+			assigned-clocks = &lt;&amp;clkc_periphs CLKID_USB_BUS&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;64000000&gt;;</div><div class='add'>+			resets = &lt;&amp;reset RESET_USBCTRL&gt;;</div><div class='add'>+</div><div class='add'>+			dr_mode = "otg";</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;usb2_phy1&gt;;</div><div class='add'>+			phy-names = "usb2-phy1";</div><div class='add'>+</div><div class='add'>+			dwc3: usb@ff400000 {</div><div class='add'>+				compatible = "snps,dwc3";</div><div class='add'>+				reg = &lt;0x0 0xff400000 0x0 0x100000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				dr_mode = "host";</div><div class='add'>+				snps,dis_u2_susphy_quirk;</div><div class='add'>+				snps,quirk-frame-length-adjustment = &lt;0x20&gt;;</div><div class='add'>+				snps,parkmode-disable-ss-quirk;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			dwc2: usb@ff500000 {</div><div class='add'>+				compatible = "amlogic,meson-a1-usb", "snps,dwc2";</div><div class='add'>+				reg = &lt;0x0 0xff500000 0x0 0x40000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				phys = &lt;&amp;usb2_phy1&gt;;</div><div class='add'>+				phy-names = "usb2-phy";</div><div class='add'>+				clocks = &lt;&amp;clkc_periphs CLKID_USB_PHY&gt;;</div><div class='add'>+				clock-names = "otg";</div><div class='add'>+				dr_mode = "peripheral";</div><div class='add'>+				g-rx-fifo-size = &lt;192&gt;;</div><div class='add'>+				g-np-tx-fifo-size = &lt;128&gt;;</div><div class='add'>+				g-tx-fifo-size = &lt;128 128 16 16 16&gt;;</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		gic: interrupt-controller@ff901000 {</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts b/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts<br/>new file mode 100644<br/>index 000000000000..b2d6ba660914<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts</a></div><div class='hunk'>@@ -0,0 +1,40 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2022 Vyacheslav Bocharov &lt;adeep@lexina.in&gt;</div><div class='add'>+ * Copyright (c) 2022 JetHome</div><div class='add'>+ * Author: Vyacheslav Bocharov &lt;adeep@lexina.in&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "meson-axg-jethome-jethub-j1xx.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "jethome,jethub-j100", "amlogic,a113d", "amlogic,meson-axg";</div><div class='add'>+	model = "JetHome JetHub D1 (J100)";</div><div class='add'>+</div><div class='add'>+	/* 1024MB RAM */</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x0 0x0 0x40000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+/* wifi module */</div><div class='add'>+&amp;sd_emmc_b {</div><div class='add'>+	non-removable;</div><div class='add'>+</div><div class='add'>+	brcmf: wifi@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		compatible = "brcm,bcm4329-fmac";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* UART Bluetooth */</div><div class='add'>+&amp;uart_B {</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "brcm,bcm43438-bt";</div><div class='add'>+		shutdown-gpios = &lt;&amp;gpio GPIOZ_7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j110-rev-2.dts b/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j110-rev-2.dts<br/>new file mode 100644<br/>index 000000000000..8a18ce948450<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j110-rev-2.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j110-rev-2.dts</a></div><div class='hunk'>@@ -0,0 +1,49 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2022 Vyacheslav Bocharov &lt;adeep@lexina.in&gt;</div><div class='add'>+ * Copyright (c) 2022 JetHome</div><div class='add'>+ * Author: Vyacheslav Bocharov &lt;adeep@lexina.in&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "meson-axg-jethome-jethub-j1xx.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "jethome,jethub-j110", "amlogic,a113d", "amlogic,meson-axg";</div><div class='add'>+	model = "JetHome JetHub D1p (J110) HW rev.2";</div><div class='add'>+</div><div class='add'>+	/* 2GiB or 4GiB RAM */</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x0 0x0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+/* wifi module */</div><div class='add'>+&amp;sd_emmc_b {</div><div class='add'>+	broken-cd;/* cd-gpios = &lt;&amp;gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW&gt;;*/</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* UART Bluetooth */</div><div class='add'>+&amp;uart_B {</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "realtek,rtl8822cs-bt";</div><div class='add'>+		enable-gpios = &lt;&amp;gpio GPIOZ_7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		host-wake-gpios = &lt;&amp;gpio GPIOZ_8 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		device-wake-gpios = &lt;&amp;gpio GPIOZ_6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c_AO {</div><div class='add'>+	/* EEPROM on base board */</div><div class='add'>+	eeprompd: eeprom@56 {</div><div class='add'>+		compatible = "atmel,24c64";</div><div class='add'>+		reg = &lt;0x56&gt;;</div><div class='add'>+		pagesize = &lt;0x20&gt;;</div><div class='add'>+		label = "eeprompd";</div><div class='add'>+		address-width = &lt;0x10&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j110-rev-3.dts b/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j110-rev-3.dts<br/>new file mode 100644<br/>index 000000000000..c356bd2cc63a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j110-rev-3.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j110-rev-3.dts</a></div><div class='hunk'>@@ -0,0 +1,39 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2022 Vyacheslav Bocharov &lt;adeep@lexina.in&gt;</div><div class='add'>+ * Copyright (c) 2022 JetHome</div><div class='add'>+ * Author: Vyacheslav Bocharov &lt;adeep@lexina.in&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "meson-axg-jethome-jethub-j1xx.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "jethome,jethub-j110", "amlogic,a113d", "amlogic,meson-axg";</div><div class='add'>+	model = "JetHome JetHub D1p (J110) Hw rev.3";</div><div class='add'>+</div><div class='add'>+	/* 2GiB or 4GiB RAM */</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x0 0x0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+/* wifi module */</div><div class='add'>+&amp;sd_emmc_b {</div><div class='add'>+	broken-cd;/* cd-gpios = &lt;&amp;gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW&gt;;*/</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c_AO {</div><div class='add'>+	/* EEPROM on base board */</div><div class='add'>+	eeprompd: eeprom@56 {</div><div class='add'>+		compatible = "atmel,24c64";</div><div class='add'>+		reg = &lt;0x56&gt;;</div><div class='add'>+		pagesize = &lt;0x20&gt;;</div><div class='add'>+		label = "eeprompd";</div><div class='add'>+		address-width = &lt;0x10&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j1xx.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j1xx.dtsi<br/>new file mode 100644<br/>index 000000000000..9b65ae818e2f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j1xx.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j1xx.dtsi</a></div><div class='hunk'>@@ -0,0 +1,334 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2022 Vyacheslav Bocharov &lt;adeep@lexina.in&gt;</div><div class='add'>+ * Copyright (c) 2022 JetHome</div><div class='add'>+ * Author: Vyacheslav Bocharov &lt;adeep@lexina.in&gt;</div><div class='add'>+ * Author: Aleksandr Kazantsev &lt;ak@tvip.ru&gt;</div><div class='add'>+ * Author: Alexey Shevelkin &lt;ash@tvip.ru&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "meson-axg.dtsi"</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/thermal/thermal.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart_AO;   /* Console */</div><div class='add'>+		serial2 = &amp;uart_AO_B; /* External UART (Wireless Module) */</div><div class='add'>+		ethernet0 = &amp;ethmac;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		linux,cma {</div><div class='add'>+			size = &lt;0x0 0x400000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	emmc_pwrseq: emmc-pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-emmc";</div><div class='add'>+		reset-gpios = &lt;&amp;gpio BOOT_9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vcc_3v3: regulator-vcc-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCC_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vcc_5v: regulator-vcc-5v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCC5V";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddao_3v3: regulator-vddao-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDAO_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vcc_5v&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddio_ao18: regulator-vddio-ao18 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDIO_AO18";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddio_boot: regulator-vddio-boot {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDIO_BOOT";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vccq_1v8: regulator-vccq-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCCQ_1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb_pwr: regulator-usb-pwr {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "USB_PWR";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vcc_5v&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdio_pwrseq: sdio-pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-simple";</div><div class='add'>+		reset-gpios = &lt;&amp;gpio GPIOX_7 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		clocks = &lt;&amp;wifi32k&gt;;</div><div class='add'>+		clock-names = "ext_clock";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wifi32k: wifi32k {</div><div class='add'>+		compatible = "pwm-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;32768&gt;;</div><div class='add'>+		pwms = &lt;&amp;pwm_ab 0 30518 0&gt;; /* PWM_A at 32.768KHz */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	thermal-zones {</div><div class='add'>+		cpu_thermal: cpu-thermal {</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;scpi_sensors 0&gt;;</div><div class='add'>+			trips {</div><div class='add'>+				cpu_passive: cpu-passive {</div><div class='add'>+					temperature = &lt;70000&gt;; /* millicelsius */</div><div class='add'>+					hysteresis = &lt;2000&gt;; /* millicelsius */</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_hot: cpu-hot {</div><div class='add'>+					temperature = &lt;80000&gt;; /* millicelsius */</div><div class='add'>+					hysteresis = &lt;2000&gt;; /* millicelsius */</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_critical: cpu-critical {</div><div class='add'>+					temperature = &lt;100000&gt;; /* millicelsius */</div><div class='add'>+					hysteresis = &lt;2000&gt;; /* millicelsius */</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cpu_cooling_maps: cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu_passive&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							&lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							&lt;&amp;cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							&lt;&amp;cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				map1 {</div><div class='add'>+					trip = &lt;&amp;cpu_hot&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							&lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							&lt;&amp;cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							&lt;&amp;cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	onewire {</div><div class='add'>+		compatible = "w1-gpio";</div><div class='add'>+		gpios = &lt;&amp;gpio GPIOA_14 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;efuse {</div><div class='add'>+	sn: sn@32 {</div><div class='add'>+		reg = &lt;0x32 0x20&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eth_mac: eth-mac@0 {</div><div class='add'>+		reg = &lt;0x0 0x6&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bt_mac: bt-mac@6 {</div><div class='add'>+		reg = &lt;0x6 0x6&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wifi_mac: wifi-mac@c {</div><div class='add'>+		reg = &lt;0xc 0x6&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bid: bid@12 {</div><div class='add'>+		reg = &lt;0x12 0x20&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethmac {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;eth_rmii_x_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	phy-handle = &lt;&amp;eth_phy0&gt;;</div><div class='add'>+	phy-mode = "rmii";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		/* ICPlus IP101A/G Ethernet PHY (vendor_id=0x0243, model_id=0x0c54) */</div><div class='add'>+		eth_phy0: ethernet-phy@0 {</div><div class='add'>+			/* compatible = "ethernet-phy-id0243.0c54";*/</div><div class='add'>+			max-speed = &lt;100&gt;;</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			reset-assert-us = &lt;10000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;10000&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio GPIOZ_5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Internal I2C bus (on CPU module) */</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c1_z_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	/* RTC */</div><div class='add'>+	pcf8563: rtc@51 {</div><div class='add'>+		compatible = "nxp,pcf8563";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Peripheral I2C bus (on motherboard) */</div><div class='add'>+&amp;i2c_AO {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c_ao_sck_10_pins&gt;, &lt;&amp;i2c_ao_sda_11_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm_ab {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm_a_x20_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* wifi module */</div><div class='add'>+&amp;sd_emmc_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdio_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;sdio_clk_gate_pins&gt;;</div><div class='add'>+	pinctrl-names = "default", "clk-gate";</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	max-frequency = &lt;50000000&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+</div><div class='add'>+	mmc-pwrseq = &lt;&amp;sdio_pwrseq&gt;;</div><div class='add'>+</div><div class='add'>+	vmmc-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;vddio_boot&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* emmc storage */</div><div class='add'>+&amp;sd_emmc_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;emmc_pins&gt;, &lt;&amp;emmc_ds_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;emmc_clk_gate_pins&gt;;</div><div class='add'>+	pinctrl-names = "default", "clk-gate";</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	cap-mmc-highspeed;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	disable-wp;</div><div class='add'>+	mmc-ddr-1_8v;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+</div><div class='add'>+	mmc-pwrseq = &lt;&amp;emmc_pwrseq&gt;;</div><div class='add'>+</div><div class='add'>+	vmmc-supply = &lt;&amp;vcc_3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;vccq_1v8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* UART Bluetooth */</div><div class='add'>+&amp;uart_B {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart_b_z_pins&gt;, &lt;&amp;uart_b_z_cts_rts_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* UART Console */</div><div class='add'>+&amp;uart_AO {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart_ao_a_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* UART Wireless module */</div><div class='add'>+&amp;uart_AO_B {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart_ao_b_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb {</div><div class='add'>+	status = "okay";</div><div class='add'>+	vbus-supply = &lt;&amp;usb_pwr&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spicc1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;spi1_x_pins&gt;, &lt;&amp;spi1_ss0_x_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"", "", "", "", "", // 0 - 4</div><div class='add'>+		"", "", "", "", "", // 5 - 9</div><div class='add'>+		"UserButton", "", "", "", "", // 10 - 14</div><div class='add'>+		"", "", "", "", "", // 15 - 19</div><div class='add'>+		"", "", "", "", "", // 20 - 24</div><div class='add'>+		"", "LedRed", "LedGreen", "Output3", "Output2", // 25 - 29</div><div class='add'>+		"Output1", "", "", "", "", // 30 - 34</div><div class='add'>+		"", "ZigBeeBOOT", "", "", "", // 35 - 39</div><div class='add'>+		"1Wire", "ZigBeeRESET", "", "Input4", "Input3", // 40 - 44</div><div class='add'>+		"Input2", "Input1", "", "", "", // 45 - 49</div><div class='add'>+		"", "", "", "", "", // 50 - 54</div><div class='add'>+		"", "", "", "", "", // 55 - 59</div><div class='add'>+		"", "", "", "", "", // 60 - 64</div><div class='add'>+		"", "", "", "", "", // 65 - 69</div><div class='add'>+		"", "", "", "", "", // 70 - 74</div><div class='add'>+		"", "", "", "", "", // 75 - 79</div><div class='add'>+		"", "", "", "", "", // 80 - 84</div><div class='add'>+		"", ""; // 85-86</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts<br/>index cb1360ae1211..9611775b81ee 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-axg-s400.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-axg-s400.dts</a></div><div class='hunk'>@@ -12,7 +12,7 @@</div><div class='ctx'> 	compatible = "amlogic,s400", "amlogic,a113d", "amlogic,meson-axg";</div><div class='ctx'> 	model = "Amlogic Meson AXG S400 Development Board";</div><div class='ctx'> </div><div class='del'>-	adc_keys {</div><div class='add'>+	keys {</div><div class='ctx'> 		compatible = "adc-keys";</div><div class='ctx'> 		io-channels = &lt;&amp;saradc 0&gt;;</div><div class='ctx'> 		io-channel-names = "buttons";</div><div class='hunk'>@@ -66,7 +66,6 @@</div><div class='ctx'> 		VDDA-supply = &lt;&amp;vcc_3v3&gt;;</div><div class='ctx'> 		VDDP-supply = &lt;&amp;vcc_3v3&gt;;</div><div class='ctx'> 		VDDD-supply = &lt;&amp;vcc_3v3&gt;;</div><div class='del'>-		status = "okay";</div><div class='ctx'> 		sound-name-prefix = "Linein";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -75,14 +74,12 @@</div><div class='ctx'> 		compatible = "everest,es7154";</div><div class='ctx'> 		VDD-supply = &lt;&amp;vcc_3v3&gt;;</div><div class='ctx'> 		PVDD-supply = &lt;&amp;vcc_5v&gt;;</div><div class='del'>-		status = "okay";</div><div class='ctx'> 		sound-name-prefix = "Lineout";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	spdif_dit: audio-codec-2 {</div><div class='ctx'> 		#sound-dai-cells = &lt;0&gt;;</div><div class='ctx'> 		compatible = "linux,spdif-dit";</div><div class='del'>-		status = "okay";</div><div class='ctx'> 		sound-name-prefix = "DIT";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -91,14 +88,12 @@</div><div class='ctx'> 		compatible = "dmic-codec";</div><div class='ctx'> 		num-channels = &lt;7&gt;;</div><div class='ctx'> 		wakeup-delay-ms = &lt;50&gt;;</div><div class='del'>-		status = "okay";</div><div class='ctx'> 		sound-name-prefix = "MIC";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	spdif_dir: audio-codec-4 {</div><div class='ctx'> 		#sound-dai-cells = &lt;0&gt;;</div><div class='ctx'> 		compatible = "linux,spdif-dir";</div><div class='del'>-		status = "okay";</div><div class='ctx'> 		sound-name-prefix = "DIR";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -116,7 +111,7 @@</div><div class='ctx'> 		reg = &lt;0x0 0x0 0x0 0x40000000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	main_12v: regulator-main_12v {</div><div class='add'>+	main_12v: regulator-main-12v {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "12V";</div><div class='ctx'> 		regulator-min-microvolt = &lt;12000000&gt;;</div><div class='hunk'>@@ -124,7 +119,7 @@</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vcc_3v3: regulator-vcc_3v3 {</div><div class='add'>+	vcc_3v3: regulator-vcc-3v3 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VCC_3V3";</div><div class='ctx'> 		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='hunk'>@@ -133,7 +128,7 @@</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vcc_5v: regulator-vcc_5v {</div><div class='add'>+	vcc_5v: regulator-vcc-5v {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VCC5V";</div><div class='ctx'> 		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='hunk'>@@ -144,7 +139,7 @@</div><div class='ctx'> 		enable-active-high;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vddao_3v3: regulator-vddao_3v3 {</div><div class='add'>+	vddao_3v3: regulator-vddao-3v3 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VDDAO_3V3";</div><div class='ctx'> 		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='hunk'>@@ -153,7 +148,7 @@</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vddio_ao18: regulator-vddio_ao18 {</div><div class='add'>+	vddio_ao18: regulator-vddio-ao18 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VDDIO_AO18";</div><div class='ctx'> 		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='hunk'>@@ -162,7 +157,7 @@</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vddio_boot: regulator-vddio_boot {</div><div class='add'>+	vddio_boot: regulator-vddio-boot {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VDDIO_BOOT";</div><div class='ctx'> 		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='hunk'>@@ -171,7 +166,7 @@</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	usb_pwr: regulator-usb_pwr {</div><div class='add'>+	usb_pwr: regulator-usb-pwr {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "USB_PWR";</div><div class='ctx'> 		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='hunk'>@@ -273,6 +268,10 @@</div><div class='ctx'> 				"Speaker1 Right", "SPK1 OUT_D",</div><div class='ctx'> 				"Linein AINL", "Linein",</div><div class='ctx'> 				"Linein AINR", "Linein";</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_HIFI_PLL&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+</div><div class='ctx'> 		assigned-clocks = &lt;&amp;clkc CLKID_HIFI_PLL&gt;,</div><div class='ctx'> 				  &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='ctx'> 				  &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='hunk'>@@ -280,7 +279,6 @@</div><div class='ctx'> 		assigned-clock-rates = &lt;589824000&gt;,</div><div class='ctx'> 				       &lt;270950400&gt;,</div><div class='ctx'> 				       &lt;393216000&gt;;</div><div class='del'>-		status = "okay";</div><div class='ctx'> </div><div class='ctx'> 		dai-link-0 {</div><div class='ctx'> 			sound-dai = &lt;&amp;frddr_a&gt;;</div><div class='hunk'>@@ -441,6 +439,16 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;pcieA {</div><div class='add'>+	reset-gpios = &lt;&amp;gpio GPIOX_19 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcieB {</div><div class='add'>+	reset-gpios = &lt;&amp;gpio GPIOZ_10 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;pwm_ab {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pwm_a_x20_pins&gt;;</div><div class='hunk'>@@ -584,3 +592,9 @@</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;uart_ao_a_pins&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> };</div><div class='add'>+</div><div class='add'>+&amp;usb {</div><div class='add'>+	status = "okay";</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	vbus-supply = &lt;&amp;usb_pwr&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi<br/>index aace3d32a3df..e95c91894968 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-axg.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-axg.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-axg.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-axg.dtsi</a></div><div class='hunk'>@@ -12,6 +12,7 @@</div><div class='ctx'> #include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/reset/amlogic,meson-axg-audio-arb.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/reset/amlogic,meson-axg-reset.h&gt;</div><div class='add'>+#include &lt;dt-bindings/power/meson-axg-power.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	compatible = "amlogic,meson-axg";</div><div class='hunk'>@@ -24,10 +25,10 @@</div><div class='ctx'> 		compatible = "amlogic,axg-tdm-iface";</div><div class='ctx'> 		#sound-dai-cells = &lt;0&gt;;</div><div class='ctx'> 		sound-name-prefix = "TDM_A";</div><div class='del'>-		clocks = &lt;&amp;clkc_audio AUD_CLKID_MST_A_MCLK&gt;,</div><div class='del'>-			 &lt;&amp;clkc_audio AUD_CLKID_MST_A_SCLK&gt;,</div><div class='del'>-			 &lt;&amp;clkc_audio AUD_CLKID_MST_A_LRCLK&gt;;</div><div class='del'>-		clock-names = "mclk", "sclk", "lrclk";</div><div class='add'>+		clocks = &lt;&amp;clkc_audio AUD_CLKID_MST_A_SCLK&gt;,</div><div class='add'>+			 &lt;&amp;clkc_audio AUD_CLKID_MST_A_LRCLK&gt;,</div><div class='add'>+			 &lt;&amp;clkc_audio AUD_CLKID_MST_A_MCLK&gt;;</div><div class='add'>+		clock-names = "sclk", "lrclk", "mclk";</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -35,10 +36,10 @@</div><div class='ctx'> 		compatible = "amlogic,axg-tdm-iface";</div><div class='ctx'> 		#sound-dai-cells = &lt;0&gt;;</div><div class='ctx'> 		sound-name-prefix = "TDM_B";</div><div class='del'>-		clocks = &lt;&amp;clkc_audio AUD_CLKID_MST_B_MCLK&gt;,</div><div class='del'>-			 &lt;&amp;clkc_audio AUD_CLKID_MST_B_SCLK&gt;,</div><div class='del'>-			 &lt;&amp;clkc_audio AUD_CLKID_MST_B_LRCLK&gt;;</div><div class='del'>-		clock-names = "mclk", "sclk", "lrclk";</div><div class='add'>+		clocks = &lt;&amp;clkc_audio AUD_CLKID_MST_B_SCLK&gt;,</div><div class='add'>+			 &lt;&amp;clkc_audio AUD_CLKID_MST_B_LRCLK&gt;,</div><div class='add'>+			 &lt;&amp;clkc_audio AUD_CLKID_MST_B_MCLK&gt;;</div><div class='add'>+		clock-names = "sclk", "lrclk", "mclk";</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -46,10 +47,10 @@</div><div class='ctx'> 		compatible = "amlogic,axg-tdm-iface";</div><div class='ctx'> 		#sound-dai-cells = &lt;0&gt;;</div><div class='ctx'> 		sound-name-prefix = "TDM_C";</div><div class='del'>-		clocks = &lt;&amp;clkc_audio AUD_CLKID_MST_C_MCLK&gt;,</div><div class='del'>-			 &lt;&amp;clkc_audio AUD_CLKID_MST_C_SCLK&gt;,</div><div class='del'>-			 &lt;&amp;clkc_audio AUD_CLKID_MST_C_LRCLK&gt;;</div><div class='del'>-		clock-names = "mclk", "sclk", "lrclk";</div><div class='add'>+		clocks = &lt;&amp;clkc_audio AUD_CLKID_MST_C_SCLK&gt;,</div><div class='add'>+			 &lt;&amp;clkc_audio AUD_CLKID_MST_C_LRCLK&gt;,</div><div class='add'>+			 &lt;&amp;clkc_audio AUD_CLKID_MST_C_MCLK&gt;;</div><div class='add'>+		clock-names = "sclk", "lrclk", "mclk";</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -73,6 +74,8 @@</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			next-level-cache = &lt;&amp;l2&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;scpi_dvfs 0&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;140&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu1: cpu@1 {</div><div class='hunk'>@@ -80,8 +83,16 @@</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			reg = &lt;0x0 0x1&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			d-cache-line-size = &lt;32&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-sets = &lt;32&gt;;</div><div class='add'>+			i-cache-line-size = &lt;32&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-sets = &lt;32&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;l2&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;scpi_dvfs 0&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;140&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu2: cpu@2 {</div><div class='hunk'>@@ -89,8 +100,16 @@</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			reg = &lt;0x0 0x2&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			d-cache-line-size = &lt;32&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-sets = &lt;32&gt;;</div><div class='add'>+			i-cache-line-size = &lt;32&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-sets = &lt;32&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;l2&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;scpi_dvfs 0&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;140&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu3: cpu@3 {</div><div class='hunk'>@@ -98,12 +117,25 @@</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			reg = &lt;0x0 0x3&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			d-cache-line-size = &lt;32&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-sets = &lt;32&gt;;</div><div class='add'>+			i-cache-line-size = &lt;32&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-sets = &lt;32&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;l2&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;scpi_dvfs 0&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;140&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		l2: l2-cache0 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x80000&gt;; /* L2. 512 KB */</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;512&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -151,7 +183,7 @@</div><div class='ctx'> 		scpi_clocks: clocks {</div><div class='ctx'> 			compatible = "arm,scpi-clocks";</div><div class='ctx'> </div><div class='del'>-			scpi_dvfs: clock-controller {</div><div class='add'>+			scpi_dvfs: clocks-0 {</div><div class='ctx'> 				compatible = "arm,scpi-dvfs-clocks";</div><div class='ctx'> 				#clock-cells = &lt;1&gt;;</div><div class='ctx'> 				clock-indices = &lt;0&gt;;</div><div class='hunk'>@@ -160,7 +192,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		scpi_sensors: sensors {</div><div class='del'>-			compatible = "amlogic,meson-gxbb-scpi-sensors";</div><div class='add'>+			compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors";</div><div class='ctx'> 			#thermal-sensor-cells = &lt;1&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='hunk'>@@ -171,6 +203,98 @@</div><div class='ctx'> 		#size-cells = &lt;2&gt;;</div><div class='ctx'> 		ranges;</div><div class='ctx'> </div><div class='add'>+		pcieA: pcie@f9800000 {</div><div class='add'>+			compatible = "amlogic,axg-pcie", "snps,dw-pcie";</div><div class='add'>+			reg = &lt;0x0 0xf9800000 0x0 0x400000&gt;,</div><div class='add'>+			      &lt;0x0 0xff646000 0x0 0x2000&gt;,</div><div class='add'>+			      &lt;0x0 0xf9f00000 0x0 0x100000&gt;;</div><div class='add'>+			reg-names = "dbi", "cfg", "config";</div><div class='add'>+			interrupts = &lt;GIC_SPI 177 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 0 &amp;gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			bus-range = &lt;0x0 0xff&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			ranges = &lt;0x82000000 0 0xf9c00000 0x0 0xf9c00000 0 0x00300000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;clkc CLKID_USB&gt;, &lt;&amp;clkc CLKID_PCIE_A&gt;, &lt;&amp;clkc CLKID_PCIE_CML_EN0&gt;;</div><div class='add'>+			clock-names = "general", "pclk", "port";</div><div class='add'>+			resets = &lt;&amp;reset RESET_PCIE_A&gt;, &lt;&amp;reset RESET_PCIE_APB&gt;;</div><div class='add'>+			reset-names = "port", "apb";</div><div class='add'>+			num-lanes = &lt;1&gt;;</div><div class='add'>+			phys = &lt;&amp;pcie_phy&gt;;</div><div class='add'>+			phy-names = "pcie";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcieB: pcie@fa000000 {</div><div class='add'>+			compatible = "amlogic,axg-pcie", "snps,dw-pcie";</div><div class='add'>+			reg = &lt;0x0 0xfa000000 0x0 0x400000&gt;,</div><div class='add'>+			      &lt;0x0 0xff648000 0x0 0x2000&gt;,</div><div class='add'>+			      &lt;0x0 0xfa400000 0x0 0x100000&gt;;</div><div class='add'>+			reg-names = "dbi", "cfg", "config";</div><div class='add'>+			interrupts = &lt;GIC_SPI 167 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 0 &amp;gic GIC_SPI 169 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			bus-range = &lt;0x0 0xff&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			ranges = &lt;0x82000000 0 0xfa500000 0x0 0xfa500000 0 0x00300000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;clkc CLKID_USB&gt;, &lt;&amp;clkc CLKID_PCIE_B&gt;, &lt;&amp;clkc CLKID_PCIE_CML_EN1&gt;;</div><div class='add'>+			clock-names = "general", "pclk", "port";</div><div class='add'>+			resets = &lt;&amp;reset RESET_PCIE_B&gt;, &lt;&amp;reset RESET_PCIE_APB&gt;;</div><div class='add'>+			reset-names = "port", "apb";</div><div class='add'>+			num-lanes = &lt;1&gt;;</div><div class='add'>+			phys = &lt;&amp;pcie_phy&gt;;</div><div class='add'>+			phy-names = "pcie";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb: usb@ffe09080 {</div><div class='add'>+			compatible = "amlogic,meson-axg-usb-ctrl";</div><div class='add'>+			reg = &lt;0x0 0xffe09080 0x0 0x20&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;clkc CLKID_USB&gt;, &lt;&amp;clkc CLKID_USB1_DDR_BRIDGE&gt;;</div><div class='add'>+			clock-names = "usb_ctrl", "ddr";</div><div class='add'>+			resets = &lt;&amp;reset RESET_USB_OTG&gt;;</div><div class='add'>+</div><div class='add'>+			dr_mode = "otg";</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;usb2_phy1&gt;;</div><div class='add'>+			phy-names = "usb2-phy1";</div><div class='add'>+</div><div class='add'>+			dwc2: usb@ff400000 {</div><div class='add'>+				compatible = "amlogic,meson-g12a-usb", "snps,dwc2";</div><div class='add'>+				reg = &lt;0x0 0xff400000 0x0 0x40000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clkc CLKID_USB1&gt;;</div><div class='add'>+				clock-names = "otg";</div><div class='add'>+				phys = &lt;&amp;usb2_phy1&gt;;</div><div class='add'>+				dr_mode = "peripheral";</div><div class='add'>+				g-rx-fifo-size = &lt;192&gt;;</div><div class='add'>+				g-np-tx-fifo-size = &lt;128&gt;;</div><div class='add'>+				g-tx-fifo-size = &lt;128 128 16 16 16&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			dwc3: usb@ff500000 {</div><div class='add'>+				compatible = "snps,dwc3";</div><div class='add'>+				reg = &lt;0x0 0xff500000 0x0 0x100000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				dr_mode = "host";</div><div class='add'>+				maximum-speed = "high-speed";</div><div class='add'>+				snps,dis_u2_susphy_quirk;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		ethmac: ethernet@ff3f0000 {</div><div class='ctx'> 			compatible = "amlogic,meson-axg-dwmac",</div><div class='ctx'> 				     "snps,dwmac-3.70a",</div><div class='hunk'>@@ -181,13 +305,25 @@</div><div class='ctx'> 			interrupt-names = "macirq";</div><div class='ctx'> 			clocks = &lt;&amp;clkc CLKID_ETH&gt;,</div><div class='ctx'> 				 &lt;&amp;clkc CLKID_FCLK_DIV2&gt;,</div><div class='del'>-				 &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='del'>-			clock-names = "stmmaceth", "clkin0", "clkin1";</div><div class='add'>+				 &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+				 &lt;&amp;clkc CLKID_FCLK_DIV2&gt;;</div><div class='add'>+			clock-names = "stmmaceth", "clkin0", "clkin1",</div><div class='add'>+				      "timing-adjustment";</div><div class='ctx'> 			rx-fifo-depth = &lt;4096&gt;;</div><div class='ctx'> 			tx-fifo-depth = &lt;2048&gt;;</div><div class='add'>+			power-domains = &lt;&amp;pwrc PWRC_AXG_ETHERNET_MEM_ID&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		pcie_phy: phy@ff644000 {</div><div class='add'>+			compatible = "amlogic,axg-pcie-phy";</div><div class='add'>+			reg = &lt;0x0 0xff644000 0x0 0x1c&gt;;</div><div class='add'>+			resets = &lt;&amp;reset RESET_PCIE_PHY&gt;;</div><div class='add'>+			phys = &lt;&amp;mipi_pcie_analog_dphy&gt;;</div><div class='add'>+			phy-names = "analog";</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		pdm: audio-controller@ff632000 {</div><div class='ctx'> 			compatible = "amlogic,axg-pdm";</div><div class='ctx'> 			reg = &lt;0x0 0xff632000 0x0 0x34&gt;;</div><div class='hunk'>@@ -325,6 +461,27 @@</div><div class='ctx'> 					};</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='add'>+				nand_all_pins: nand-all-pins {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "emmc_nand_d0",</div><div class='add'>+							 "emmc_nand_d1",</div><div class='add'>+							 "emmc_nand_d2",</div><div class='add'>+							 "emmc_nand_d3",</div><div class='add'>+							 "emmc_nand_d4",</div><div class='add'>+							 "emmc_nand_d5",</div><div class='add'>+							 "emmc_nand_d6",</div><div class='add'>+							 "emmc_nand_d7",</div><div class='add'>+							 "nand_ce0",</div><div class='add'>+							 "nand_ale",</div><div class='add'>+							 "nand_cle",</div><div class='add'>+							 "nand_wen_clk",</div><div class='add'>+							 "nand_ren_wr";</div><div class='add'>+						function = "nand";</div><div class='add'>+						input-enable;</div><div class='add'>+						bias-pull-up;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='ctx'> 				emmc_ds_pins: emmc_ds {</div><div class='ctx'> 					mux {</div><div class='ctx'> 						groups = "emmc_ds";</div><div class='hunk'>@@ -1028,7 +1185,7 @@</div><div class='ctx'> 						groups = "uart_tx_a",</div><div class='ctx'> 							 "uart_rx_a";</div><div class='ctx'> 						function = "uart_a";</div><div class='del'>-						bias-disable;</div><div class='add'>+						bias-pull-up;</div><div class='ctx'> 					};</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='hunk'>@@ -1046,7 +1203,7 @@</div><div class='ctx'> 						groups = "uart_tx_b_x",</div><div class='ctx'> 							 "uart_rx_b_x";</div><div class='ctx'> 						function = "uart_b";</div><div class='del'>-						bias-disable;</div><div class='add'>+						bias-pull-up;</div><div class='ctx'> 					};</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='hunk'>@@ -1064,7 +1221,7 @@</div><div class='ctx'> 						groups = "uart_tx_b_z",</div><div class='ctx'> 							 "uart_rx_b_z";</div><div class='ctx'> 						function = "uart_b";</div><div class='del'>-						bias-disable;</div><div class='add'>+						bias-pull-up;</div><div class='ctx'> 					};</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='hunk'>@@ -1082,7 +1239,7 @@</div><div class='ctx'> 						groups = "uart_ao_tx_b_z",</div><div class='ctx'> 							 "uart_ao_rx_b_z";</div><div class='ctx'> 						function = "uart_ao_b_z";</div><div class='del'>-						bias-disable;</div><div class='add'>+						bias-pull-up;</div><div class='ctx'> 					};</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='hunk'>@@ -1115,6 +1272,52 @@</div><div class='ctx'> 					clocks = &lt;&amp;xtal&gt;;</div><div class='ctx'> 					clock-names = "xtal";</div><div class='ctx'> 				};</div><div class='add'>+</div><div class='add'>+				pwrc: power-controller {</div><div class='add'>+					compatible = "amlogic,meson-axg-pwrc";</div><div class='add'>+					#power-domain-cells = &lt;1&gt;;</div><div class='add'>+					amlogic,ao-sysctrl = &lt;&amp;sysctrl_AO&gt;;</div><div class='add'>+					resets = &lt;&amp;reset RESET_VIU&gt;,</div><div class='add'>+						 &lt;&amp;reset RESET_VENC&gt;,</div><div class='add'>+						 &lt;&amp;reset RESET_VCBUS&gt;,</div><div class='add'>+						 &lt;&amp;reset RESET_VENCL&gt;,</div><div class='add'>+						 &lt;&amp;reset RESET_VID_LOCK&gt;;</div><div class='add'>+					reset-names = "viu", "venc", "vcbus",</div><div class='add'>+						      "vencl", "vid_lock";</div><div class='add'>+					clocks = &lt;&amp;clkc CLKID_VPU&gt;,</div><div class='add'>+						 &lt;&amp;clkc CLKID_VAPB&gt;;</div><div class='add'>+					clock-names = "vpu", "vapb";</div><div class='add'>+					/*</div><div class='add'>+					 * VPU clocking is provided by two identical clock paths</div><div class='add'>+					 * VPU_0 and VPU_1 muxed to a single clock by a glitch</div><div class='add'>+					 * free mux to safely change frequency while running.</div><div class='add'>+					 * Same for VAPB but with a final gate after the glitch free mux.</div><div class='add'>+					 */</div><div class='add'>+					assigned-clocks = &lt;&amp;clkc CLKID_VPU_0_SEL&gt;,</div><div class='add'>+							  &lt;&amp;clkc CLKID_VPU_0&gt;,</div><div class='add'>+							  &lt;&amp;clkc CLKID_VPU&gt;, /* Glitch free mux */</div><div class='add'>+							  &lt;&amp;clkc CLKID_VAPB_0_SEL&gt;,</div><div class='add'>+							  &lt;&amp;clkc CLKID_VAPB_0&gt;,</div><div class='add'>+							  &lt;&amp;clkc CLKID_VAPB_SEL&gt;; /* Glitch free mux */</div><div class='add'>+					assigned-clock-parents = &lt;&amp;clkc CLKID_FCLK_DIV4&gt;,</div><div class='add'>+								 &lt;0&gt;, /* Do Nothing */</div><div class='add'>+								 &lt;&amp;clkc CLKID_VPU_0&gt;,</div><div class='add'>+								 &lt;&amp;clkc CLKID_FCLK_DIV4&gt;,</div><div class='add'>+								 &lt;0&gt;, /* Do Nothing */</div><div class='add'>+								 &lt;&amp;clkc CLKID_VAPB_0&gt;;</div><div class='add'>+					assigned-clock-rates = &lt;0&gt;, /* Do Nothing */</div><div class='add'>+							       &lt;250000000&gt;,</div><div class='add'>+							       &lt;0&gt;, /* Do Nothing */</div><div class='add'>+							       &lt;0&gt;, /* Do Nothing */</div><div class='add'>+							       &lt;250000000&gt;,</div><div class='add'>+							       &lt;0&gt;; /* Do Nothing */</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				mipi_pcie_analog_dphy: phy {</div><div class='add'>+					compatible = "amlogic,axg-mipi-pcie-analog-phy";</div><div class='add'>+					#phy-cells = &lt;0&gt;;</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -1127,6 +1330,19 @@</div><div class='ctx'> 			#mbox-cells = &lt;1&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		mipi_dphy: phy@ff640000 {</div><div class='add'>+			compatible = "amlogic,axg-mipi-dphy";</div><div class='add'>+			reg = &lt;0x0 0xff640000 0x0 0x100&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkc CLKID_MIPI_DSI_PHY&gt;;</div><div class='add'>+			clock-names = "pclk";</div><div class='add'>+			resets = &lt;&amp;reset RESET_MIPI_PHY&gt;;</div><div class='add'>+			reset-names = "phy";</div><div class='add'>+			phys = &lt;&amp;mipi_pcie_analog_dphy&gt;;</div><div class='add'>+			phy-names = "analog";</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		audio: bus@ff642000 {</div><div class='ctx'> 			compatible = "simple-bus";</div><div class='ctx'> 			reg = &lt;0x0 0xff642000 0x0 0x2000&gt;;</div><div class='hunk'>@@ -1371,7 +1587,7 @@</div><div class='ctx'> </div><div class='ctx'> 			sysctrl_AO: sys-ctrl@0 {</div><div class='ctx'> 				compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon";</div><div class='del'>-				reg =  &lt;0x0 0x0 0x0 0x100&gt;;</div><div class='add'>+				reg = &lt;0x0 0x0 0x0 0x100&gt;;</div><div class='ctx'> </div><div class='ctx'> 				clkc_AO: clock-controller {</div><div class='ctx'> 					compatible = "amlogic,meson-axg-aoclkc";</div><div class='hunk'>@@ -1459,7 +1675,7 @@</div><div class='ctx'> 						groups = "uart_ao_tx_a",</div><div class='ctx'> 							 "uart_ao_rx_a";</div><div class='ctx'> 						function = "uart_ao_a";</div><div class='del'>-						bias-disable;</div><div class='add'>+						bias-pull-up;</div><div class='ctx'> 					};</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='hunk'>@@ -1477,7 +1693,7 @@</div><div class='ctx'> 						groups = "uart_ao_tx_b",</div><div class='ctx'> 							 "uart_ao_rx_b";</div><div class='ctx'> 						function = "uart_ao_b";</div><div class='del'>-						bias-disable;</div><div class='add'>+						bias-pull-up;</div><div class='ctx'> 					};</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='hunk'>@@ -1498,8 +1714,12 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			pwm_AO_cd: pwm@2000 {</div><div class='del'>-				compatible = "amlogic,meson-axg-ao-pwm";</div><div class='add'>+				compatible = "amlogic,meson-axg-pwm-v2", "amlogic,meson8-pwm-v2";</div><div class='ctx'> 				reg = &lt;0x0 0x02000  0x0 0x20&gt;;</div><div class='add'>+				clocks = &lt;&amp;xtal&gt;,</div><div class='add'>+					 &lt;&amp;clkc_AO CLKID_AO_CLK81&gt;,</div><div class='add'>+					 &lt;&amp;clkc CLKID_FCLK_DIV4&gt;,</div><div class='add'>+					 &lt;&amp;clkc CLKID_FCLK_DIV5&gt;;</div><div class='ctx'> 				#pwm-cells = &lt;3&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='hunk'>@@ -1533,8 +1753,12 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			pwm_AO_ab: pwm@7000 {</div><div class='del'>-				compatible = "amlogic,meson-axg-ao-pwm";</div><div class='add'>+				compatible = "amlogic,meson-axg-pwm-v2", "amlogic,meson8-pwm-v2";</div><div class='ctx'> 				reg = &lt;0x0 0x07000 0x0 0x20&gt;;</div><div class='add'>+				clocks = &lt;&amp;xtal&gt;,</div><div class='add'>+					 &lt;&amp;clkc_AO CLKID_AO_CLK81&gt;,</div><div class='add'>+					 &lt;&amp;clkc CLKID_FCLK_DIV4&gt;,</div><div class='add'>+					 &lt;&amp;clkc CLKID_FCLK_DIV5&gt;;</div><div class='ctx'> 				#pwm-cells = &lt;3&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='hunk'>@@ -1561,6 +1785,14 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		ge2d: ge2d@ff940000 {</div><div class='add'>+			compatible = "amlogic,axg-ge2d";</div><div class='add'>+			reg = &lt;0x0 0xff940000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 150 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkc CLKID_VAPB&gt;;</div><div class='add'>+			resets = &lt;&amp;reset RESET_GE2D&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		gic: interrupt-controller@ffc01000 {</div><div class='ctx'> 			compatible = "arm,gic-400";</div><div class='ctx'> 			reg = &lt;0x0 0xffc01000 0 0x1000&gt;,</div><div class='hunk'>@@ -1603,15 +1835,23 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			pwm_ab: pwm@1b000 {</div><div class='del'>-				compatible = "amlogic,meson-axg-ee-pwm";</div><div class='add'>+				compatible = "amlogic,meson-axg-pwm-v2", "amlogic,meson8-pwm-v2";</div><div class='ctx'> 				reg = &lt;0x0 0x1b000 0x0 0x20&gt;;</div><div class='add'>+				clocks = &lt;&amp;xtal&gt;,</div><div class='add'>+					 &lt;&amp;clkc CLKID_FCLK_DIV5&gt;,</div><div class='add'>+					 &lt;&amp;clkc CLKID_FCLK_DIV4&gt;,</div><div class='add'>+					 &lt;&amp;clkc CLKID_FCLK_DIV3&gt;;</div><div class='ctx'> 				#pwm-cells = &lt;3&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			pwm_cd: pwm@1a000 {</div><div class='del'>-				compatible = "amlogic,meson-axg-ee-pwm";</div><div class='add'>+				compatible = "amlogic,meson-axg-pwm-v2", "amlogic,meson8-pwm-v2";</div><div class='ctx'> 				reg = &lt;0x0 0x1a000 0x0 0x20&gt;;</div><div class='add'>+				clocks = &lt;&amp;xtal&gt;,</div><div class='add'>+					 &lt;&amp;clkc CLKID_FCLK_DIV5&gt;,</div><div class='add'>+					 &lt;&amp;clkc CLKID_FCLK_DIV4&gt;,</div><div class='add'>+					 &lt;&amp;clkc CLKID_FCLK_DIV3&gt;;</div><div class='ctx'> 				#pwm-cells = &lt;3&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='hunk'>@@ -1699,6 +1939,7 @@</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 				clocks = &lt;&amp;xtal&gt;, &lt;&amp;clkc CLKID_UART0&gt;, &lt;&amp;xtal&gt;;</div><div class='ctx'> 				clock-names = "xtal", "pclk", "baud";</div><div class='add'>+				fifo-size = &lt;128&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -1709,10 +1950,10 @@</div><div class='ctx'> 			#size-cells = &lt;2&gt;;</div><div class='ctx'> 			ranges = &lt;0x0 0x0 0x0 0xffe00000 0x0 0x200000&gt;;</div><div class='ctx'> </div><div class='del'>-			sd_emmc_b: sd@5000 {</div><div class='add'>+			sd_emmc_b: mmc@5000 {</div><div class='ctx'> 				compatible = "amlogic,meson-axg-mmc";</div><div class='ctx'> 				reg = &lt;0x0 0x5000 0x0 0x800&gt;;</div><div class='del'>-				interrupts = &lt;GIC_SPI 217 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 				clocks = &lt;&amp;clkc CLKID_SD_EMMC_B&gt;,</div><div class='ctx'> 					&lt;&amp;clkc CLKID_SD_EMMC_B_CLK0&gt;,</div><div class='hunk'>@@ -1724,7 +1965,7 @@</div><div class='ctx'> 			sd_emmc_c: mmc@7000 {</div><div class='ctx'> 				compatible = "amlogic,meson-axg-mmc";</div><div class='ctx'> 				reg = &lt;0x0 0x7000 0x0 0x800&gt;;</div><div class='del'>-				interrupts = &lt;GIC_SPI 218 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 				clocks = &lt;&amp;clkc CLKID_SD_EMMC_C&gt;,</div><div class='ctx'> 					&lt;&amp;clkc CLKID_SD_EMMC_C_CLK0&gt;,</div><div class='hunk'>@@ -1732,21 +1973,46 @@</div><div class='ctx'> 				clock-names = "core", "clkin0", "clkin1";</div><div class='ctx'> 				resets = &lt;&amp;reset RESET_SD_EMMC_C&gt;;</div><div class='ctx'> 			};</div><div class='add'>+</div><div class='add'>+			nfc: nand-controller@7800 {</div><div class='add'>+				compatible = "amlogic,meson-axg-nfc";</div><div class='add'>+				reg = &lt;0x0 0x7800 0x0 0x100&gt;,</div><div class='add'>+				      &lt;0x0 0x7000 0x0 0x800&gt;;</div><div class='add'>+				reg-names = "nfc", "emmc";</div><div class='add'>+				pinctrl-0 = &lt;&amp;nand_all_pins&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 34 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				clocks = &lt;&amp;clkc CLKID_SD_EMMC_C&gt;,</div><div class='add'>+					 &lt;&amp;clkc CLKID_FCLK_DIV2&gt;;</div><div class='add'>+				clock-names = "core", "device";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			usb2_phy1: phy@9020 {</div><div class='add'>+				compatible = "amlogic,meson-gxl-usb2-phy";</div><div class='add'>+				#phy-cells = &lt;0&gt;;</div><div class='add'>+				reg = &lt;0x0 0x9020 0x0 0x20&gt;;</div><div class='add'>+				clocks = &lt;&amp;clkc CLKID_USB&gt;;</div><div class='add'>+				clock-names = "phy";</div><div class='add'>+				resets = &lt;&amp;reset RESET_USB_OTG&gt;;</div><div class='add'>+				reset-names = "phy";</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		sram: sram@fffc0000 {</div><div class='del'>-			compatible = "amlogic,meson-axg-sram", "mmio-sram";</div><div class='add'>+			compatible = "mmio-sram";</div><div class='ctx'> 			reg = &lt;0x0 0xfffc0000 0x0 0x20000&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;1&gt;;</div><div class='ctx'> 			ranges = &lt;0 0x0 0xfffc0000 0x20000&gt;;</div><div class='ctx'> </div><div class='del'>-			cpu_scp_lpri: scp-shmem@13000 {</div><div class='add'>+			cpu_scp_lpri: scp-sram@13000 {</div><div class='ctx'> 				compatible = "amlogic,meson-axg-scp-shmem";</div><div class='ctx'> 				reg = &lt;0x13000 0x400&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			cpu_scp_hpri: scp-shmem@13400 {</div><div class='add'>+			cpu_scp_hpri: scp-sram@13400 {</div><div class='ctx'> 				compatible = "amlogic,meson-axg-scp-shmem";</div><div class='ctx'> 				reg = &lt;0x13400 0x400&gt;;</div><div class='ctx'> 			};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi<br/>index 0882ea215b88..ca455f634834 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi</a></div><div class='hunk'>@@ -9,6 +9,7 @@</div><div class='ctx'> #include &lt;dt-bindings/clock/g12a-aoclkc.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/amlogic,meson-g12a-gpio-intc.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/reset/amlogic,meson-g12a-reset.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/thermal/thermal.h&gt;</div><div class='ctx'> </div><div class='hunk'>@@ -17,6 +18,12 @@</div><div class='ctx'> 	#address-cells = &lt;2&gt;;</div><div class='ctx'> 	#size-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='add'>+	aliases {</div><div class='add'>+		mmc0 = &amp;sd_emmc_b; /* SD card */</div><div class='add'>+		mmc1 = &amp;sd_emmc_c; /* eMMC */</div><div class='add'>+		mmc2 = &amp;sd_emmc_a; /* SDIO */</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	chosen {</div><div class='ctx'> 		#address-cells = &lt;2&gt;;</div><div class='ctx'> 		#size-cells = &lt;2&gt;;</div><div class='hunk'>@@ -52,6 +59,39 @@</div><div class='ctx'> 		secure-monitor = &lt;&amp;sm&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	gpu_opp_table: opp-table-gpu {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		opp-124999998 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;124999998&gt;;</div><div class='add'>+			opp-microvolt = &lt;800000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-249999996 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;249999996&gt;;</div><div class='add'>+			opp-microvolt = &lt;800000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-285714281 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;285714281&gt;;</div><div class='add'>+			opp-microvolt = &lt;800000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-399999994 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;399999994&gt;;</div><div class='add'>+			opp-microvolt = &lt;800000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-499999992 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;499999992&gt;;</div><div class='add'>+			opp-microvolt = &lt;800000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-666666656 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;666666656&gt;;</div><div class='add'>+			opp-microvolt = &lt;800000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-799999987 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;799999987&gt;;</div><div class='add'>+			opp-microvolt = &lt;800000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	psci {</div><div class='ctx'> 		compatible = "arm,psci-1.0";</div><div class='ctx'> 		method = "smc";</div><div class='hunk'>@@ -68,6 +108,12 @@</div><div class='ctx'> 			no-map;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		/* 32 MiB reserved for ARM Trusted Firmware (BL32) */</div><div class='add'>+		secmon_reserved_bl32: secmon@5300000 {</div><div class='add'>+			reg = &lt;0x0 0x05300000 0x0 0x2000000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		linux,cma {</div><div class='ctx'> 			compatible = "shared-dma-pool";</div><div class='ctx'> 			reusable;</div><div class='hunk'>@@ -89,10 +135,10 @@</div><div class='ctx'> </div><div class='ctx'> 		pcie: pcie@fc000000 {</div><div class='ctx'> 			compatible = "amlogic,g12a-pcie", "snps,dw-pcie";</div><div class='del'>-			reg = &lt;0x0 0xfc000000 0x0 0x400000</div><div class='del'>-			       0x0 0xff648000 0x0 0x2000</div><div class='del'>-			       0x0 0xfc400000 0x0 0x200000&gt;;</div><div class='del'>-			reg-names = "elbi", "cfg", "config";</div><div class='add'>+			reg = &lt;0x0 0xfc000000 0x0 0x400000&gt;,</div><div class='add'>+			      &lt;0x0 0xff648000 0x0 0x2000&gt;,</div><div class='add'>+			      &lt;0x0 0xfc400000 0x0 0x200000&gt;;</div><div class='add'>+			reg-names = "dbi", "cfg", "config";</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			#interrupt-cells = &lt;1&gt;;</div><div class='ctx'> 			interrupt-map-mask = &lt;0 0 0 0&gt;;</div><div class='hunk'>@@ -101,8 +147,8 @@</div><div class='ctx'> 			#address-cells = &lt;3&gt;;</div><div class='ctx'> 			#size-cells = &lt;2&gt;;</div><div class='ctx'> 			device_type = "pci";</div><div class='del'>-			ranges = &lt;0x81000000 0 0 0x0 0xfc600000 0 0x00100000</div><div class='del'>-				  0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000&gt;;</div><div class='add'>+			ranges = &lt;0x81000000 0 0 0x0 0xfc600000 0 0x00100000&gt;,</div><div class='add'>+				 &lt;0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000&gt;;</div><div class='ctx'> </div><div class='ctx'> 			clocks = &lt;&amp;clkc CLKID_PCIE_PHY</div><div class='ctx'> 				  &amp;clkc CLKID_PCIE_COMB</div><div class='hunk'>@@ -120,63 +166,8 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		thermal-zones {</div><div class='del'>-			cpu_thermal: cpu-thermal {</div><div class='del'>-				polling-delay = &lt;1000&gt;;</div><div class='del'>-				polling-delay-passive = &lt;100&gt;;</div><div class='del'>-				thermal-sensors = &lt;&amp;cpu_temp&gt;;</div><div class='del'>-</div><div class='del'>-				trips {</div><div class='del'>-					cpu_passive: cpu-passive {</div><div class='del'>-						temperature = &lt;85000&gt;; /* millicelsius */</div><div class='del'>-						hysteresis = &lt;2000&gt;; /* millicelsius */</div><div class='del'>-						type = "passive";</div><div class='del'>-					};</div><div class='del'>-</div><div class='del'>-					cpu_hot: cpu-hot {</div><div class='del'>-						temperature = &lt;95000&gt;; /* millicelsius */</div><div class='del'>-						hysteresis = &lt;2000&gt;; /* millicelsius */</div><div class='del'>-						type = "hot";</div><div class='del'>-					};</div><div class='del'>-</div><div class='del'>-					cpu_critical: cpu-critical {</div><div class='del'>-						temperature = &lt;110000&gt;; /* millicelsius */</div><div class='del'>-						hysteresis = &lt;2000&gt;; /* millicelsius */</div><div class='del'>-						type = "critical";</div><div class='del'>-					};</div><div class='del'>-				};</div><div class='del'>-			};</div><div class='del'>-</div><div class='del'>-			ddr_thermal: ddr-thermal {</div><div class='del'>-				polling-delay = &lt;1000&gt;;</div><div class='del'>-				polling-delay-passive = &lt;100&gt;;</div><div class='del'>-				thermal-sensors = &lt;&amp;ddr_temp&gt;;</div><div class='del'>-</div><div class='del'>-				trips {</div><div class='del'>-					ddr_passive: ddr-passive {</div><div class='del'>-						temperature = &lt;85000&gt;; /* millicelsius */</div><div class='del'>-						hysteresis = &lt;2000&gt;; /* millicelsius */</div><div class='del'>-						type = "passive";</div><div class='del'>-					};</div><div class='del'>-</div><div class='del'>-					ddr_critical: ddr-critical {</div><div class='del'>-						temperature = &lt;110000&gt;; /* millicelsius */</div><div class='del'>-						hysteresis = &lt;2000&gt;; /* millicelsius */</div><div class='del'>-						type = "critical";</div><div class='del'>-					};</div><div class='del'>-				};</div><div class='del'>-</div><div class='del'>-				cooling-maps {</div><div class='del'>-					map {</div><div class='del'>-						trip = &lt;&amp;ddr_passive&gt;;</div><div class='del'>-						cooling-device = &lt;&amp;mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='del'>-					};</div><div class='del'>-				};</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-</div><div class='ctx'> 		ethmac: ethernet@ff3f0000 {</div><div class='del'>-			compatible = "amlogic,meson-axg-dwmac",</div><div class='add'>+			compatible = "amlogic,meson-g12a-dwmac",</div><div class='ctx'> 				     "snps,dwmac-3.70a",</div><div class='ctx'> 				     "snps,dwmac";</div><div class='ctx'> 			reg = &lt;0x0 0xff3f0000 0x0 0x10000&gt;,</div><div class='hunk'>@@ -185,8 +176,10 @@</div><div class='ctx'> 			interrupt-names = "macirq";</div><div class='ctx'> 			clocks = &lt;&amp;clkc CLKID_ETH&gt;,</div><div class='ctx'> 				 &lt;&amp;clkc CLKID_FCLK_DIV2&gt;,</div><div class='del'>-				 &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='del'>-			clock-names = "stmmaceth", "clkin0", "clkin1";</div><div class='add'>+				 &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+				 &lt;&amp;clkc CLKID_FCLK_DIV2&gt;;</div><div class='add'>+			clock-names = "stmmaceth", "clkin0", "clkin1",</div><div class='add'>+				      "timing-adjustment";</div><div class='ctx'> 			rx-fifo-depth = &lt;4096&gt;;</div><div class='ctx'> 			tx-fifo-depth = &lt;2048&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='hunk'>@@ -222,6 +215,11 @@</div><div class='ctx'> 				#sound-dai-cells = &lt;0&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> </div><div class='add'>+				assigned-clocks = &lt;&amp;clkc CLKID_HDMI_SEL&gt;,</div><div class='add'>+						  &lt;&amp;clkc CLKID_HDMI&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;xtal&gt;, &lt;0&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;0&gt;, &lt;24000000&gt;;</div><div class='add'>+</div><div class='ctx'> 				/* VPU VENC Input */</div><div class='ctx'> 				hdmi_tx_venc_port: port@0 {</div><div class='ctx'> 					reg = &lt;0&gt;;</div><div class='hunk'>@@ -247,9 +245,22 @@</div><div class='ctx'> 				hwrng: rng@218 {</div><div class='ctx'> 					compatible = "amlogic,meson-rng";</div><div class='ctx'> 					reg = &lt;0x0 0x218 0x0 0x4&gt;;</div><div class='add'>+					clocks = &lt;&amp;clkc CLKID_RNG0&gt;;</div><div class='add'>+					clock-names = "core";</div><div class='ctx'> 				};</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='add'>+			acodec: audio-controller@32000 {</div><div class='add'>+				compatible = "amlogic,t9015";</div><div class='add'>+				reg = &lt;0x0 0x32000 0x0 0x14&gt;;</div><div class='add'>+				#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+				sound-name-prefix = "ACODEC";</div><div class='add'>+				clocks = &lt;&amp;clkc CLKID_AUDIO_CODEC&gt;;</div><div class='add'>+				clock-names = "pclk";</div><div class='add'>+				resets = &lt;&amp;reset RESET_AUDIO_CODEC&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='ctx'> 			periphs: bus@34400 {</div><div class='ctx'> 				compatible = "simple-bus";</div><div class='ctx'> 				reg = &lt;0x0 0x34400 0x0 0x400&gt;;</div><div class='hunk'>@@ -840,6 +851,22 @@</div><div class='ctx'> 						};</div><div class='ctx'> 					};</div><div class='ctx'> </div><div class='add'>+					pwm_f_z_pins: pwm-f-z {</div><div class='add'>+						mux {</div><div class='add'>+							groups = "pwm_f_z";</div><div class='add'>+							function = "pwm_f";</div><div class='add'>+							bias-disable;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					pwm_f_a_pins: pwm-f-a {</div><div class='add'>+						mux {</div><div class='add'>+							groups = "pwm_f_a";</div><div class='add'>+							function = "pwm_f";</div><div class='add'>+							bias-disable;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='ctx'> 					pwm_f_x_pins: pwm-f-x {</div><div class='ctx'> 						mux {</div><div class='ctx'> 							groups = "pwm_f_x";</div><div class='hunk'>@@ -965,7 +992,7 @@</div><div class='ctx'> 						mux {</div><div class='ctx'> 							groups = "spdif_out_h";</div><div class='ctx'> 							function = "spdif_out";</div><div class='del'>-							drive-strength-microamp = &lt;500&gt;;</div><div class='add'>+							drive-strength-microamp = &lt;3000&gt;;</div><div class='ctx'> 							bias-disable;</div><div class='ctx'> 						};</div><div class='ctx'> 					};</div><div class='hunk'>@@ -974,7 +1001,7 @@</div><div class='ctx'> 						mux {</div><div class='ctx'> 							groups = "spdif_out_a11";</div><div class='ctx'> 							function = "spdif_out";</div><div class='del'>-							drive-strength-microamp = &lt;500&gt;;</div><div class='add'>+							drive-strength-microamp = &lt;3000&gt;;</div><div class='ctx'> 							bias-disable;</div><div class='ctx'> 						};</div><div class='ctx'> 					};</div><div class='hunk'>@@ -983,7 +1010,7 @@</div><div class='ctx'> 						mux {</div><div class='ctx'> 							groups = "spdif_out_a13";</div><div class='ctx'> 							function = "spdif_out";</div><div class='del'>-							drive-strength-microamp = &lt;500&gt;;</div><div class='add'>+							drive-strength-microamp = &lt;3000&gt;;</div><div class='ctx'> 							bias-disable;</div><div class='ctx'> 						};</div><div class='ctx'> 					};</div><div class='hunk'>@@ -1476,7 +1503,7 @@</div><div class='ctx'> 							groups = "uart_a_tx",</div><div class='ctx'> 								 "uart_a_rx";</div><div class='ctx'> 							function = "uart_a";</div><div class='del'>-							bias-disable;</div><div class='add'>+							bias-pull-up;</div><div class='ctx'> 						};</div><div class='ctx'> 					};</div><div class='ctx'> </div><div class='hunk'>@@ -1494,7 +1521,7 @@</div><div class='ctx'> 							groups = "uart_b_tx",</div><div class='ctx'> 								 "uart_b_rx";</div><div class='ctx'> 							function = "uart_b";</div><div class='del'>-							bias-disable;</div><div class='add'>+							bias-pull-up;</div><div class='ctx'> 						};</div><div class='ctx'> 					};</div><div class='ctx'> </div><div class='hunk'>@@ -1550,15 +1577,20 @@</div><div class='ctx'> </div><div class='ctx'> 			dmc: bus@38000 {</div><div class='ctx'> 				compatible = "simple-bus";</div><div class='del'>-				reg = &lt;0x0 0x38000 0x0 0x400&gt;;</div><div class='ctx'> 				#address-cells = &lt;2&gt;;</div><div class='ctx'> 				#size-cells = &lt;2&gt;;</div><div class='del'>-				ranges = &lt;0x0 0x0 0x0 0x38000 0x0 0x400&gt;;</div><div class='add'>+				ranges = &lt;0x0 0x0 0x0 0x38000 0x0 0x2000&gt;;</div><div class='ctx'> </div><div class='ctx'> 				canvas: video-lut@48 {</div><div class='ctx'> 					compatible = "amlogic,canvas";</div><div class='ctx'> 					reg = &lt;0x0 0x48 0x0 0x14&gt;;</div><div class='ctx'> 				};</div><div class='add'>+</div><div class='add'>+				pmu: pmu@80 {</div><div class='add'>+					reg = &lt;0x0 0x80 0x0 0x40&gt;,</div><div class='add'>+					      &lt;0x0 0xc00 0x0 0x40&gt;;</div><div class='add'>+					interrupts = &lt;GIC_SPI 52 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				};</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			usb2_phy1: phy@3a000 {</div><div class='hunk'>@@ -1636,9 +1668,28 @@</div><div class='ctx'> 								       &lt;250000000&gt;,</div><div class='ctx'> 								       &lt;0&gt;; /* Do Nothing */</div><div class='ctx'> 					};</div><div class='add'>+</div><div class='add'>+					mipi_analog_dphy: phy {</div><div class='add'>+						compatible = "amlogic,g12a-mipi-dphy-analog";</div><div class='add'>+						#phy-cells = &lt;0&gt;;</div><div class='add'>+						status = "disabled";</div><div class='add'>+					};</div><div class='ctx'> 				};</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='add'>+			mipi_dphy: phy@44000 {</div><div class='add'>+				compatible = "amlogic,axg-mipi-dphy";</div><div class='add'>+				reg = &lt;0x0 0x44000 0x0 0x2000&gt;;</div><div class='add'>+				clocks = &lt;&amp;clkc CLKID_MIPI_DSI_PHY&gt;;</div><div class='add'>+				clock-names = "pclk";</div><div class='add'>+				resets = &lt;&amp;reset RESET_MIPI_DSI_PHY&gt;;</div><div class='add'>+				reset-names = "phy";</div><div class='add'>+				phys = &lt;&amp;mipi_analog_dphy&gt;;</div><div class='add'>+				phy-names = "analog";</div><div class='add'>+				#phy-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='ctx'> 			usb3_pcie_phy: phy@46000 {</div><div class='ctx'> 				compatible = "amlogic,g12a-usb3-pcie-phy";</div><div class='ctx'> 				reg = &lt;0x0 0x46000 0x0 0x2000&gt;;</div><div class='hunk'>@@ -1673,7 +1724,7 @@</div><div class='ctx'> 					#address-cells = &lt;1&gt;;</div><div class='ctx'> 					#size-cells = &lt;0&gt;;</div><div class='ctx'> </div><div class='del'>-					internal_ephy: ethernet_phy@8 {</div><div class='add'>+					internal_ephy: ethernet-phy@8 {</div><div class='ctx'> 						compatible = "ethernet-phy-id0180.3301",</div><div class='ctx'> 							     "ethernet-phy-ieee802.3-c22";</div><div class='ctx'> 						interrupts = &lt;GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='hunk'>@@ -1695,9 +1746,6 @@</div><div class='ctx'> 				compatible = "amlogic,meson-gx-ao-sysctrl",</div><div class='ctx'> 					     "simple-mfd", "syscon";</div><div class='ctx'> 				reg = &lt;0x0 0x0 0x0 0x100&gt;;</div><div class='del'>-				#address-cells = &lt;2&gt;;</div><div class='del'>-				#size-cells = &lt;2&gt;;</div><div class='del'>-				ranges = &lt;0x0 0x0 0x0 0x0 0x0 0x100&gt;;</div><div class='ctx'> </div><div class='ctx'> 				clkc_AO: clock-controller {</div><div class='ctx'> 					compatible = "amlogic,meson-g12a-aoclkc";</div><div class='hunk'>@@ -1706,256 +1754,283 @@</div><div class='ctx'> 					clocks = &lt;&amp;xtal&gt;, &lt;&amp;clkc CLKID_CLK81&gt;;</div><div class='ctx'> 					clock-names = "xtal", "mpeg-clk";</div><div class='ctx'> 				};</div><div class='add'>+			};</div><div class='ctx'> </div><div class='del'>-				ao_pinctrl: pinctrl@14 {</div><div class='del'>-					compatible = "amlogic,meson-g12a-aobus-pinctrl";</div><div class='del'>-					#address-cells = &lt;2&gt;;</div><div class='del'>-					#size-cells = &lt;2&gt;;</div><div class='del'>-					ranges;</div><div class='add'>+			ao_pinctrl: pinctrl@14 {</div><div class='add'>+				compatible = "amlogic,meson-g12a-aobus-pinctrl";</div><div class='add'>+				#address-cells = &lt;2&gt;;</div><div class='add'>+				#size-cells = &lt;2&gt;;</div><div class='add'>+				ranges;</div><div class='add'>+</div><div class='add'>+				gpio_ao: bank@14 {</div><div class='add'>+					reg = &lt;0x0 0x14 0x0 0x8&gt;,</div><div class='add'>+					      &lt;0x0 0x1c 0x0 0x8&gt;,</div><div class='add'>+					      &lt;0x0 0x24 0x0 0x14&gt;;</div><div class='add'>+					reg-names = "mux",</div><div class='add'>+						    "ds",</div><div class='add'>+						    "gpio";</div><div class='add'>+					gpio-controller;</div><div class='add'>+					#gpio-cells = &lt;2&gt;;</div><div class='add'>+					gpio-ranges = &lt;&amp;ao_pinctrl 0 0 15&gt;;</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-					gpio_ao: bank@14 {</div><div class='del'>-						reg = &lt;0x0 0x14 0x0 0x8&gt;,</div><div class='del'>-						      &lt;0x0 0x1c 0x0 0x8&gt;,</div><div class='del'>-						      &lt;0x0 0x24 0x0 0x14&gt;;</div><div class='del'>-						reg-names = "mux",</div><div class='del'>-							    "ds",</div><div class='del'>-							    "gpio";</div><div class='del'>-						gpio-controller;</div><div class='del'>-						#gpio-cells = &lt;2&gt;;</div><div class='del'>-						gpio-ranges = &lt;&amp;ao_pinctrl 0 0 15&gt;;</div><div class='add'>+				i2c_ao_sck_pins: i2c_ao_sck_pins {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "i2c_ao_sck";</div><div class='add'>+						function = "i2c_ao";</div><div class='add'>+						bias-disable;</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='ctx'> 					};</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-					i2c_ao_sck_pins: i2c_ao_sck_pins {</div><div class='del'>-						mux {</div><div class='del'>-							groups = "i2c_ao_sck";</div><div class='del'>-							function = "i2c_ao";</div><div class='del'>-							bias-disable;</div><div class='del'>-							drive-strength-microamp = &lt;3000&gt;;</div><div class='del'>-						};</div><div class='add'>+				i2c_ao_sda_pins: i2c_ao_sda {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "i2c_ao_sda";</div><div class='add'>+						function = "i2c_ao";</div><div class='add'>+						bias-disable;</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='ctx'> 					};</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-					i2c_ao_sda_pins: i2c_ao_sda {</div><div class='del'>-						mux {</div><div class='del'>-							groups = "i2c_ao_sda";</div><div class='del'>-							function = "i2c_ao";</div><div class='del'>-							bias-disable;</div><div class='del'>-							drive-strength-microamp = &lt;3000&gt;;</div><div class='del'>-						};</div><div class='add'>+				i2c_ao_sck_e_pins: i2c_ao_sck_e {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "i2c_ao_sck_e";</div><div class='add'>+						function = "i2c_ao";</div><div class='add'>+						bias-disable;</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='ctx'> 					};</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-					i2c_ao_sck_e_pins: i2c_ao_sck_e {</div><div class='del'>-						mux {</div><div class='del'>-							groups = "i2c_ao_sck_e";</div><div class='del'>-							function = "i2c_ao";</div><div class='del'>-							bias-disable;</div><div class='del'>-							drive-strength-microamp = &lt;3000&gt;;</div><div class='del'>-						};</div><div class='add'>+				i2c_ao_sda_e_pins: i2c_ao_sda_e {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "i2c_ao_sda_e";</div><div class='add'>+						function = "i2c_ao";</div><div class='add'>+						bias-disable;</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='ctx'> 					};</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-					i2c_ao_sda_e_pins: i2c_ao_sda_e {</div><div class='del'>-						mux {</div><div class='del'>-							groups = "i2c_ao_sda_e";</div><div class='del'>-							function = "i2c_ao";</div><div class='del'>-							bias-disable;</div><div class='del'>-							drive-strength-microamp = &lt;3000&gt;;</div><div class='del'>-						};</div><div class='add'>+				mclk0_ao_pins: mclk0-ao {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "mclk0_ao";</div><div class='add'>+						function = "mclk0_ao";</div><div class='add'>+						bias-disable;</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='ctx'> 					};</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-					mclk0_ao_pins: mclk0-ao {</div><div class='del'>-						mux {</div><div class='del'>-							groups = "mclk0_ao";</div><div class='del'>-							function = "mclk0_ao";</div><div class='del'>-							bias-disable;</div><div class='del'>-							drive-strength-microamp = &lt;3000&gt;;</div><div class='del'>-						};</div><div class='add'>+				tdm_ao_b_din0_pins: tdm-ao-b-din0 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "tdm_ao_b_din0";</div><div class='add'>+						function = "tdm_ao_b";</div><div class='add'>+						bias-disable;</div><div class='ctx'> 					};</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-					tdm_ao_b_din0_pins: tdm-ao-b-din0 {</div><div class='del'>-						mux {</div><div class='del'>-							groups = "tdm_ao_b_din0";</div><div class='del'>-							function = "tdm_ao_b";</div><div class='del'>-							bias-disable;</div><div class='del'>-						};</div><div class='add'>+				spdif_ao_out_pins: spdif-ao-out {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "spdif_ao_out";</div><div class='add'>+						function = "spdif_ao_out";</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='add'>+						bias-disable;</div><div class='ctx'> 					};</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-					spdif_ao_out_pins: spdif-ao-out {</div><div class='del'>-						mux {</div><div class='del'>-							groups = "spdif_ao_out";</div><div class='del'>-							function = "spdif_ao_out";</div><div class='del'>-							drive-strength-microamp = &lt;500&gt;;</div><div class='del'>-							bias-disable;</div><div class='del'>-						};</div><div class='add'>+				tdm_ao_b_din1_pins: tdm-ao-b-din1 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "tdm_ao_b_din1";</div><div class='add'>+						function = "tdm_ao_b";</div><div class='add'>+						bias-disable;</div><div class='ctx'> 					};</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-					tdm_ao_b_din1_pins: tdm-ao-b-din1 {</div><div class='del'>-						mux {</div><div class='del'>-							groups = "tdm_ao_b_din1";</div><div class='del'>-							function = "tdm_ao_b";</div><div class='del'>-							bias-disable;</div><div class='del'>-						};</div><div class='add'>+				tdm_ao_b_din2_pins: tdm-ao-b-din2 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "tdm_ao_b_din2";</div><div class='add'>+						function = "tdm_ao_b";</div><div class='add'>+						bias-disable;</div><div class='ctx'> 					};</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-					tdm_ao_b_din2_pins: tdm-ao-b-din2 {</div><div class='del'>-						mux {</div><div class='del'>-							groups = "tdm_ao_b_din2";</div><div class='del'>-							function = "tdm_ao_b";</div><div class='del'>-							bias-disable;</div><div class='del'>-						};</div><div class='add'>+				tdm_ao_b_dout0_pins: tdm-ao-b-dout0 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "tdm_ao_b_dout0";</div><div class='add'>+						function = "tdm_ao_b";</div><div class='add'>+						bias-disable;</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='ctx'> 					};</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-					tdm_ao_b_dout0_pins: tdm-ao-b-dout0 {</div><div class='del'>-						mux {</div><div class='del'>-							groups = "tdm_ao_b_dout0";</div><div class='del'>-							function = "tdm_ao_b";</div><div class='del'>-							bias-disable;</div><div class='del'>-							drive-strength-microamp = &lt;3000&gt;;</div><div class='del'>-						};</div><div class='add'>+				tdm_ao_b_dout1_pins: tdm-ao-b-dout1 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "tdm_ao_b_dout1";</div><div class='add'>+						function = "tdm_ao_b";</div><div class='add'>+						bias-disable;</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='ctx'> 					};</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-					tdm_ao_b_dout1_pins: tdm-ao-b-dout1 {</div><div class='del'>-						mux {</div><div class='del'>-							groups = "tdm_ao_b_dout1";</div><div class='del'>-							function = "tdm_ao_b";</div><div class='del'>-							bias-disable;</div><div class='del'>-							drive-strength-microamp = &lt;3000&gt;;</div><div class='del'>-						};</div><div class='add'>+				tdm_ao_b_dout2_pins: tdm-ao-b-dout2 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "tdm_ao_b_dout2";</div><div class='add'>+						function = "tdm_ao_b";</div><div class='add'>+						bias-disable;</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='ctx'> 					};</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-					tdm_ao_b_dout2_pins: tdm-ao-b-dout2 {</div><div class='del'>-						mux {</div><div class='del'>-							groups = "tdm_ao_b_dout2";</div><div class='del'>-							function = "tdm_ao_b";</div><div class='del'>-							bias-disable;</div><div class='del'>-							drive-strength-microamp = &lt;3000&gt;;</div><div class='del'>-						};</div><div class='add'>+				tdm_ao_b_fs_pins: tdm-ao-b-fs {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "tdm_ao_b_fs";</div><div class='add'>+						function = "tdm_ao_b";</div><div class='add'>+						bias-disable;</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='ctx'> 					};</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-					tdm_ao_b_fs_pins: tdm-ao-b-fs {</div><div class='del'>-						mux {</div><div class='del'>-							groups = "tdm_ao_b_fs";</div><div class='del'>-							function = "tdm_ao_b";</div><div class='del'>-							bias-disable;</div><div class='del'>-							drive-strength-microamp = &lt;3000&gt;;</div><div class='del'>-						};</div><div class='add'>+				tdm_ao_b_sclk_pins: tdm-ao-b-sclk {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "tdm_ao_b_sclk";</div><div class='add'>+						function = "tdm_ao_b";</div><div class='add'>+						bias-disable;</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='ctx'> 					};</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-					tdm_ao_b_sclk_pins: tdm-ao-b-sclk {</div><div class='del'>-						mux {</div><div class='del'>-							groups = "tdm_ao_b_sclk";</div><div class='del'>-							function = "tdm_ao_b";</div><div class='del'>-							bias-disable;</div><div class='del'>-							drive-strength-microamp = &lt;3000&gt;;</div><div class='del'>-						};</div><div class='add'>+				tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "tdm_ao_b_slv_fs";</div><div class='add'>+						function = "tdm_ao_b";</div><div class='add'>+						bias-disable;</div><div class='ctx'> 					};</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-					tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs {</div><div class='del'>-						mux {</div><div class='del'>-							groups = "tdm_ao_b_slv_fs";</div><div class='del'>-							function = "tdm_ao_b";</div><div class='del'>-							bias-disable;</div><div class='del'>-						};</div><div class='add'>+				tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "tdm_ao_b_slv_sclk";</div><div class='add'>+						function = "tdm_ao_b";</div><div class='add'>+						bias-disable;</div><div class='ctx'> 					};</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-					tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk {</div><div class='del'>-						mux {</div><div class='del'>-							groups = "tdm_ao_b_slv_sclk";</div><div class='del'>-							function = "tdm_ao_b";</div><div class='del'>-							bias-disable;</div><div class='del'>-						};</div><div class='add'>+				uart_ao_a_pins: uart-ao-a {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "uart_ao_a_tx",</div><div class='add'>+							 "uart_ao_a_rx";</div><div class='add'>+						function = "uart_ao_a";</div><div class='add'>+						bias-pull-up;</div><div class='ctx'> 					};</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-					uart_ao_a_pins: uart-a-ao {</div><div class='del'>-						mux {</div><div class='del'>-							groups = "uart_ao_a_tx",</div><div class='del'>-								 "uart_ao_a_rx";</div><div class='del'>-							function = "uart_ao_a";</div><div class='del'>-							bias-disable;</div><div class='del'>-						};</div><div class='add'>+				uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "uart_ao_a_cts",</div><div class='add'>+							 "uart_ao_a_rts";</div><div class='add'>+						function = "uart_ao_a";</div><div class='add'>+						bias-disable;</div><div class='ctx'> 					};</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-					uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts {</div><div class='del'>-						mux {</div><div class='del'>-							groups = "uart_ao_a_cts",</div><div class='del'>-								 "uart_ao_a_rts";</div><div class='del'>-							function = "uart_ao_a";</div><div class='del'>-							bias-disable;</div><div class='del'>-						};</div><div class='add'>+				uart_ao_b_2_3_pins: uart-ao-b-2-3 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "uart_ao_b_tx_2",</div><div class='add'>+							 "uart_ao_b_rx_3";</div><div class='add'>+						function = "uart_ao_b";</div><div class='add'>+						bias-pull-up;</div><div class='ctx'> 					};</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-					pwm_a_e_pins: pwm-a-e {</div><div class='del'>-						mux {</div><div class='del'>-							groups = "pwm_a_e";</div><div class='del'>-							function = "pwm_a_e";</div><div class='del'>-							bias-disable;</div><div class='del'>-						};</div><div class='add'>+				uart_ao_b_8_9_pins: uart-ao-b-8-9 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "uart_ao_b_tx_8",</div><div class='add'>+							 "uart_ao_b_rx_9";</div><div class='add'>+						function = "uart_ao_b";</div><div class='add'>+						bias-pull-up;</div><div class='ctx'> 					};</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-					pwm_ao_a_pins: pwm-ao-a {</div><div class='del'>-						mux {</div><div class='del'>-							groups = "pwm_ao_a";</div><div class='del'>-							function = "pwm_ao_a";</div><div class='del'>-							bias-disable;</div><div class='del'>-						};</div><div class='add'>+				uart_ao_b_cts_rts_pins: uart-ao-b-cts-rts {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "uart_ao_b_cts",</div><div class='add'>+							 "uart_ao_b_rts";</div><div class='add'>+						function = "uart_ao_b";</div><div class='add'>+						bias-disable;</div><div class='ctx'> 					};</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-					pwm_ao_b_pins: pwm-ao-b {</div><div class='del'>-						mux {</div><div class='del'>-							groups = "pwm_ao_b";</div><div class='del'>-							function = "pwm_ao_b";</div><div class='del'>-							bias-disable;</div><div class='del'>-						};</div><div class='add'>+				pwm_a_e_pins: pwm-a-e {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_a_e";</div><div class='add'>+						function = "pwm_a_e";</div><div class='add'>+						bias-disable;</div><div class='ctx'> 					};</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-					pwm_ao_c_4_pins: pwm-ao-c-4 {</div><div class='del'>-						mux {</div><div class='del'>-							groups = "pwm_ao_c_4";</div><div class='del'>-							function = "pwm_ao_c";</div><div class='del'>-							bias-disable;</div><div class='del'>-						};</div><div class='add'>+				pwm_ao_a_pins: pwm-ao-a {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_ao_a";</div><div class='add'>+						function = "pwm_ao_a";</div><div class='add'>+						bias-disable;</div><div class='ctx'> 					};</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-					pwm_ao_c_6_pins: pwm-ao-c-6 {</div><div class='del'>-						mux {</div><div class='del'>-							groups = "pwm_ao_c_6";</div><div class='del'>-							function = "pwm_ao_c";</div><div class='del'>-							bias-disable;</div><div class='del'>-						};</div><div class='add'>+				pwm_ao_b_pins: pwm-ao-b {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_ao_b";</div><div class='add'>+						function = "pwm_ao_b";</div><div class='add'>+						bias-disable;</div><div class='ctx'> 					};</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-					pwm_ao_d_5_pins: pwm-ao-d-5 {</div><div class='del'>-						mux {</div><div class='del'>-							groups = "pwm_ao_d_5";</div><div class='del'>-							function = "pwm_ao_d";</div><div class='del'>-							bias-disable;</div><div class='del'>-						};</div><div class='add'>+				pwm_ao_c_4_pins: pwm-ao-c-4 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_ao_c_4";</div><div class='add'>+						function = "pwm_ao_c";</div><div class='add'>+						bias-disable;</div><div class='ctx'> 					};</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-					pwm_ao_d_10_pins: pwm-ao-d-10 {</div><div class='del'>-						mux {</div><div class='del'>-							groups = "pwm_ao_d_10";</div><div class='del'>-							function = "pwm_ao_d";</div><div class='del'>-							bias-disable;</div><div class='del'>-						};</div><div class='add'>+				pwm_ao_c_6_pins: pwm-ao-c-6 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_ao_c_6";</div><div class='add'>+						function = "pwm_ao_c";</div><div class='add'>+						bias-disable;</div><div class='ctx'> 					};</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-					pwm_ao_d_e_pins: pwm-ao-d-e {</div><div class='del'>-						mux {</div><div class='del'>-							groups = "pwm_ao_d_e";</div><div class='del'>-							function = "pwm_ao_d";</div><div class='del'>-						};</div><div class='add'>+				pwm_ao_d_5_pins: pwm-ao-d-5 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_ao_d_5";</div><div class='add'>+						function = "pwm_ao_d";</div><div class='add'>+						bias-disable;</div><div class='ctx'> 					};</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-					remote_input_ao_pins: remote-input-ao {</div><div class='del'>-						mux {</div><div class='del'>-							groups = "remote_ao_input";</div><div class='del'>-							function = "remote_ao_input";</div><div class='del'>-							bias-disable;</div><div class='del'>-						};</div><div class='add'>+				pwm_ao_d_10_pins: pwm-ao-d-10 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_ao_d_10";</div><div class='add'>+						function = "pwm_ao_d";</div><div class='add'>+						bias-disable;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_ao_d_e_pins: pwm-ao-d-e {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_ao_d_e";</div><div class='add'>+						function = "pwm_ao_d";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				remote_input_ao_pins: remote-input-ao {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "remote_ao_input";</div><div class='add'>+						function = "remote_ao_input";</div><div class='add'>+						bias-disable;</div><div class='ctx'> 					};</div><div class='ctx'> 				};</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			vrtc: rtc@0a8 {</div><div class='add'>+			vrtc: rtc@a8 {</div><div class='ctx'> 				compatible = "amlogic,meson-vrtc";</div><div class='ctx'> 				reg = &lt;0x0 0x000a8 0x0 0x4&gt;;</div><div class='ctx'> 			};</div><div class='hunk'>@@ -1985,14 +2060,18 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			pwm_AO_cd: pwm@2000 {</div><div class='del'>-				compatible = "amlogic,meson-g12a-ao-pwm-cd";</div><div class='add'>+				compatible = "amlogic,meson-g12-pwm-v2",</div><div class='add'>+					     "amlogic,meson8-pwm-v2";</div><div class='ctx'> 				reg = &lt;0x0 0x2000 0x0 0x20&gt;;</div><div class='add'>+				clocks = &lt;&amp;xtal&gt;,</div><div class='add'>+					 &lt;&amp;clkc_AO CLKID_AO_CLK81&gt;;</div><div class='ctx'> 				#pwm-cells = &lt;3&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			uart_AO: serial@3000 {</div><div class='del'>-				compatible = "amlogic,meson-gx-uart",</div><div class='add'>+				compatible = "amlogic,meson-g12a-uart",</div><div class='add'>+					     "amlogic,meson-gx-uart",</div><div class='ctx'> 					     "amlogic,meson-ao-uart";</div><div class='ctx'> 				reg = &lt;0x0 0x3000 0x0 0x18&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 193 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='hunk'>@@ -2002,7 +2081,8 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			uart_AO_B: serial@4000 {</div><div class='del'>-				compatible = "amlogic,meson-gx-uart",</div><div class='add'>+				compatible = "amlogic,meson-g12a-uart",</div><div class='add'>+					     "amlogic,meson-gx-uart",</div><div class='ctx'> 					     "amlogic,meson-ao-uart";</div><div class='ctx'> 				reg = &lt;0x0 0x4000 0x0 0x18&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 197 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='hunk'>@@ -2022,8 +2102,13 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			pwm_AO_ab: pwm@7000 {</div><div class='del'>-				compatible = "amlogic,meson-g12a-ao-pwm-ab";</div><div class='add'>+				compatible = "amlogic,meson-g12-pwm-v2",</div><div class='add'>+					     "amlogic,meson8-pwm-v2";</div><div class='ctx'> 				reg = &lt;0x0 0x7000 0x0 0x20&gt;;</div><div class='add'>+				clocks = &lt;&amp;xtal&gt;,</div><div class='add'>+					 &lt;&amp;clkc_AO CLKID_AO_CLK81&gt;,</div><div class='add'>+					 &lt;&amp;clkc CLKID_FCLK_DIV4&gt;,</div><div class='add'>+					 &lt;&amp;clkc CLKID_FCLK_DIV5&gt;;</div><div class='ctx'> 				#pwm-cells = &lt;3&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='hunk'>@@ -2096,6 +2181,15 @@</div><div class='ctx'> 					remote-endpoint = &lt;&amp;hdmi_tx_in&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> 			};</div><div class='add'>+</div><div class='add'>+			/* DPI output port */</div><div class='add'>+			dpi_port: port@2 {</div><div class='add'>+				reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+				dpi_out: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;mipi_dsi_in&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		gic: interrupt-controller@ffc01000 {</div><div class='hunk'>@@ -2133,6 +2227,54 @@</div><div class='ctx'> 				amlogic,channel-interrupts = &lt;64 65 66 67 68 69 70 71&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='add'>+			mipi_dsi: dsi@7000 {</div><div class='add'>+				compatible = "amlogic,meson-g12a-dw-mipi-dsi";</div><div class='add'>+				reg = &lt;0x0 0x7000 0x0 0x1000&gt;;</div><div class='add'>+				resets = &lt;&amp;reset RESET_MIPI_DSI_HOST&gt;;</div><div class='add'>+				reset-names = "top";</div><div class='add'>+				clocks = &lt;&amp;clkc CLKID_MIPI_DSI_HOST&gt;,</div><div class='add'>+					 &lt;&amp;clkc CLKID_MIPI_DSI_PXCLK&gt;,</div><div class='add'>+					 &lt;&amp;clkc CLKID_CTS_ENCL&gt;;</div><div class='add'>+				clock-names = "pclk", "bit", "px";</div><div class='add'>+				phys = &lt;&amp;mipi_dphy&gt;;</div><div class='add'>+				phy-names = "dphy";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				assigned-clocks = &lt;&amp;clkc CLKID_MIPI_DSI_PXCLK_SEL&gt;,</div><div class='add'>+					 &lt;&amp;clkc CLKID_CTS_ENCL_SEL&gt;,</div><div class='add'>+					 &lt;&amp;clkc CLKID_VCLK2_SEL&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;clkc CLKID_GP0_PLL&gt;,</div><div class='add'>+					 &lt;&amp;clkc CLKID_VCLK2_DIV1&gt;,</div><div class='add'>+					 &lt;&amp;clkc CLKID_GP0_PLL&gt;;</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					/* VPU VENC Input */</div><div class='add'>+					mipi_dsi_venc_port: port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						mipi_dsi_in: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;dpi_out&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					/* DSI Output */</div><div class='add'>+					mipi_dsi_panel_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			watchdog: watchdog@f0d0 {</div><div class='add'>+				compatible = "amlogic,meson-gxbb-wdt";</div><div class='add'>+				reg = &lt;0x0 0xf0d0 0x0 0x10&gt;;</div><div class='add'>+				clocks = &lt;&amp;xtal&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='ctx'> 			spicc0: spi@13000 {</div><div class='ctx'> 				compatible = "amlogic,meson-g12a-spicc";</div><div class='ctx'> 				reg = &lt;0x0 0x13000 0x0 0x44&gt;;</div><div class='hunk'>@@ -2167,22 +2309,37 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			pwm_ef: pwm@19000 {</div><div class='del'>-				compatible = "amlogic,meson-g12a-ee-pwm";</div><div class='add'>+				compatible = "amlogic,meson-g12-pwm-v2",</div><div class='add'>+					     "amlogic,meson8-pwm-v2";</div><div class='ctx'> 				reg = &lt;0x0 0x19000 0x0 0x20&gt;;</div><div class='add'>+				clocks = &lt;&amp;xtal&gt;,</div><div class='add'>+					 &lt;0&gt;, /* unknown/untested, the datasheet calls it "vid_pll" */</div><div class='add'>+					 &lt;&amp;clkc CLKID_FCLK_DIV4&gt;,</div><div class='add'>+					 &lt;&amp;clkc CLKID_FCLK_DIV3&gt;;</div><div class='ctx'> 				#pwm-cells = &lt;3&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			pwm_cd: pwm@1a000 {</div><div class='del'>-				compatible = "amlogic,meson-g12a-ee-pwm";</div><div class='add'>+				compatible = "amlogic,meson-g12-pwm-v2",</div><div class='add'>+					     "amlogic,meson8-pwm-v2";</div><div class='ctx'> 				reg = &lt;0x0 0x1a000 0x0 0x20&gt;;</div><div class='add'>+				clocks = &lt;&amp;xtal&gt;,</div><div class='add'>+					 &lt;0&gt;, /* unknown/untested, the datasheet calls it "vid_pll" */</div><div class='add'>+					 &lt;&amp;clkc CLKID_FCLK_DIV4&gt;,</div><div class='add'>+					 &lt;&amp;clkc CLKID_FCLK_DIV3&gt;;</div><div class='ctx'> 				#pwm-cells = &lt;3&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			pwm_ab: pwm@1b000 {</div><div class='del'>-				compatible = "amlogic,meson-g12a-ee-pwm";</div><div class='add'>+				compatible = "amlogic,meson-g12-pwm-v2",</div><div class='add'>+					     "amlogic,meson8-pwm-v2";</div><div class='ctx'> 				reg = &lt;0x0 0x1b000 0x0 0x20&gt;;</div><div class='add'>+				clocks = &lt;&amp;xtal&gt;,</div><div class='add'>+					 &lt;0&gt;, /* unknown/untested, the datasheet calls it "vid_pll" */</div><div class='add'>+					 &lt;&amp;clkc CLKID_FCLK_DIV4&gt;,</div><div class='add'>+					 &lt;&amp;clkc CLKID_FCLK_DIV3&gt;;</div><div class='ctx'> 				#pwm-cells = &lt;3&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='hunk'>@@ -2233,7 +2390,8 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			uart_C: serial@22000 {</div><div class='del'>-				compatible = "amlogic,meson-gx-uart";</div><div class='add'>+				compatible = "amlogic,meson-g12a-uart",</div><div class='add'>+					     "amlogic,meson-gx-uart";</div><div class='ctx'> 				reg = &lt;0x0 0x22000 0x0 0x18&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 93 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;xtal&gt;, &lt;&amp;clkc CLKID_UART2&gt;, &lt;&amp;xtal&gt;;</div><div class='hunk'>@@ -2242,7 +2400,8 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			uart_B: serial@23000 {</div><div class='del'>-				compatible = "amlogic,meson-gx-uart";</div><div class='add'>+				compatible = "amlogic,meson-g12a-uart",</div><div class='add'>+					     "amlogic,meson-gx-uart";</div><div class='ctx'> 				reg = &lt;0x0 0x23000 0x0 0x18&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 75 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;xtal&gt;, &lt;&amp;clkc CLKID_UART1&gt;, &lt;&amp;xtal&gt;;</div><div class='hunk'>@@ -2251,19 +2410,21 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			uart_A: serial@24000 {</div><div class='del'>-				compatible = "amlogic,meson-gx-uart";</div><div class='add'>+				compatible = "amlogic,meson-g12a-uart",</div><div class='add'>+					     "amlogic,meson-gx-uart";</div><div class='ctx'> 				reg = &lt;0x0 0x24000 0x0 0x18&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 26 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;xtal&gt;, &lt;&amp;clkc CLKID_UART0&gt;, &lt;&amp;xtal&gt;;</div><div class='ctx'> 				clock-names = "xtal", "pclk", "baud";</div><div class='ctx'> 				status = "disabled";</div><div class='add'>+				fifo-size = &lt;128&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		sd_emmc_a: sd@ffe03000 {</div><div class='add'>+		sd_emmc_a: mmc@ffe03000 {</div><div class='ctx'> 			compatible = "amlogic,meson-axg-mmc";</div><div class='ctx'> 			reg = &lt;0x0 0xffe03000 0x0 0x800&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 189 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 			clocks = &lt;&amp;clkc CLKID_SD_EMMC_A&gt;,</div><div class='ctx'> 				 &lt;&amp;clkc CLKID_SD_EMMC_A_CLK0&gt;,</div><div class='hunk'>@@ -2272,10 +2433,10 @@</div><div class='ctx'> 			resets = &lt;&amp;reset RESET_SD_EMMC_A&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		sd_emmc_b: sd@ffe05000 {</div><div class='add'>+		sd_emmc_b: mmc@ffe05000 {</div><div class='ctx'> 			compatible = "amlogic,meson-axg-mmc";</div><div class='ctx'> 			reg = &lt;0x0 0xffe05000 0x0 0x800&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 190 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 			clocks = &lt;&amp;clkc CLKID_SD_EMMC_B&gt;,</div><div class='ctx'> 				 &lt;&amp;clkc CLKID_SD_EMMC_B_CLK0&gt;,</div><div class='hunk'>@@ -2287,7 +2448,7 @@</div><div class='ctx'> 		sd_emmc_c: mmc@ffe07000 {</div><div class='ctx'> 			compatible = "amlogic,meson-axg-mmc";</div><div class='ctx'> 			reg = &lt;0x0 0xffe07000 0x0 0x800&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 191 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 			clocks = &lt;&amp;clkc CLKID_SD_EMMC_C&gt;,</div><div class='ctx'> 				 &lt;&amp;clkc CLKID_SD_EMMC_C_CLK0&gt;,</div><div class='hunk'>@@ -2319,7 +2480,7 @@</div><div class='ctx'> 				reg = &lt;0x0 0xff400000 0x0 0x40000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;clkc CLKID_USB1_DDR_BRIDGE&gt;;</div><div class='del'>-				clock-names = "ddr";</div><div class='add'>+				clock-names = "otg";</div><div class='ctx'> 				phys = &lt;&amp;usb2_phy1&gt;;</div><div class='ctx'> 				phy-names = "usb2-phy";</div><div class='ctx'> 				dr_mode = "peripheral";</div><div class='hunk'>@@ -2334,7 +2495,7 @@</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				dr_mode = "host";</div><div class='ctx'> 				snps,dis_u2_susphy_quirk;</div><div class='del'>-				snps,quirk-frame-length-adjustment;</div><div class='add'>+				snps,quirk-frame-length-adjustment = &lt;0x20&gt;;</div><div class='ctx'> 				snps,parkmode-disable-ss-quirk;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='hunk'>@@ -2349,25 +2510,66 @@</div><div class='ctx'> 			interrupt-names = "job", "mmu", "gpu";</div><div class='ctx'> 			clocks = &lt;&amp;clkc CLKID_MALI&gt;;</div><div class='ctx'> 			resets = &lt;&amp;reset RESET_DVALIN_CAPB3&gt;, &lt;&amp;reset RESET_DVALIN&gt;;</div><div class='del'>-</div><div class='del'>-			/*</div><div class='del'>-			 * Mali clocking is provided by two identical clock paths</div><div class='del'>-			 * MALI_0 and MALI_1 muxed to a single clock by a glitch</div><div class='del'>-			 * free mux to safely change frequency while running.</div><div class='del'>-			 */</div><div class='del'>-			assigned-clocks = &lt;&amp;clkc CLKID_MALI_0_SEL&gt;,</div><div class='del'>-					  &lt;&amp;clkc CLKID_MALI_0&gt;,</div><div class='del'>-					  &lt;&amp;clkc CLKID_MALI&gt;; /* Glitch free mux */</div><div class='del'>-			assigned-clock-parents = &lt;&amp;clkc CLKID_FCLK_DIV2P5&gt;,</div><div class='del'>-						 &lt;0&gt;, /* Do Nothing */</div><div class='del'>-						 &lt;&amp;clkc CLKID_MALI_0&gt;;</div><div class='del'>-			assigned-clock-rates = &lt;0&gt;, /* Do Nothing */</div><div class='del'>-					       &lt;800000000&gt;,</div><div class='del'>-					       &lt;0&gt;; /* Do Nothing */</div><div class='add'>+			operating-points-v2 = &lt;&amp;gpu_opp_table&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	thermal-zones {</div><div class='add'>+		cpu_thermal: cpu-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;100&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;cpu_temp&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu_passive: cpu-passive {</div><div class='add'>+					temperature = &lt;85000&gt;; /* millicelsius */</div><div class='add'>+					hysteresis = &lt;2000&gt;; /* millicelsius */</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_hot: cpu-hot {</div><div class='add'>+					temperature = &lt;95000&gt;; /* millicelsius */</div><div class='add'>+					hysteresis = &lt;2000&gt;; /* millicelsius */</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_critical: cpu-critical {</div><div class='add'>+					temperature = &lt;110000&gt;; /* millicelsius */</div><div class='add'>+					hysteresis = &lt;2000&gt;; /* millicelsius */</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ddr_thermal: ddr-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;100&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;ddr_temp&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				ddr_passive: ddr-passive {</div><div class='add'>+					temperature = &lt;85000&gt;; /* millicelsius */</div><div class='add'>+					hysteresis = &lt;2000&gt;; /* millicelsius */</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				ddr_critical: ddr-critical {</div><div class='add'>+					temperature = &lt;110000&gt;; /* millicelsius */</div><div class='add'>+					hysteresis = &lt;2000&gt;; /* millicelsius */</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map {</div><div class='add'>+					trip = &lt;&amp;ddr_passive&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	timer {</div><div class='ctx'> 		compatible = "arm,armv8-timer";</div><div class='ctx'> 		interrupts = &lt;GIC_PPI 13</div><div class='hunk'>@@ -2388,4 +2590,17 @@</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	npu: npu@ff100000 {</div><div class='add'>+		compatible = "vivante,gc";</div><div class='add'>+		reg = &lt;0x0 0xff100000 0x0 0x20000&gt;;</div><div class='add'>+		interrupts = &lt;0 147 4&gt;;</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_NNA_CORE_CLK&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_NNA_AXI_CLK&gt;;</div><div class='add'>+		clock-names = "core", "bus";</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc CLKID_NNA_CORE_CLK&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_NNA_AXI_CLK&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;800000000&gt;, &lt;800000000&gt;;</div><div class='add'>+		resets = &lt;&amp;reset RESET_NNA&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-g12.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12.dtsi<br/>index 783e5a397f86..664912d1beaa 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-g12.dtsi</a></div><div class='hunk'>@@ -1,4 +1,3 @@</div><div class='del'>-</div><div class='ctx'> // SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2019 BayLibre, SAS</div><div class='hunk'>@@ -16,10 +15,10 @@</div><div class='ctx'> 		compatible = "amlogic,axg-tdm-iface";</div><div class='ctx'> 		#sound-dai-cells = &lt;0&gt;;</div><div class='ctx'> 		sound-name-prefix = "TDM_A";</div><div class='del'>-		clocks = &lt;&amp;clkc_audio AUD_CLKID_MST_A_MCLK&gt;,</div><div class='del'>-			 &lt;&amp;clkc_audio AUD_CLKID_MST_A_SCLK&gt;,</div><div class='del'>-			 &lt;&amp;clkc_audio AUD_CLKID_MST_A_LRCLK&gt;;</div><div class='del'>-		clock-names = "mclk", "sclk", "lrclk";</div><div class='add'>+		clocks = &lt;&amp;clkc_audio AUD_CLKID_MST_A_SCLK&gt;,</div><div class='add'>+			 &lt;&amp;clkc_audio AUD_CLKID_MST_A_LRCLK&gt;,</div><div class='add'>+			 &lt;&amp;clkc_audio AUD_CLKID_MST_A_MCLK&gt;;</div><div class='add'>+		clock-names = "sclk", "lrclk", "mclk";</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -27,10 +26,10 @@</div><div class='ctx'> 		compatible = "amlogic,axg-tdm-iface";</div><div class='ctx'> 		#sound-dai-cells = &lt;0&gt;;</div><div class='ctx'> 		sound-name-prefix = "TDM_B";</div><div class='del'>-		clocks = &lt;&amp;clkc_audio AUD_CLKID_MST_B_MCLK&gt;,</div><div class='del'>-			 &lt;&amp;clkc_audio AUD_CLKID_MST_B_SCLK&gt;,</div><div class='del'>-			 &lt;&amp;clkc_audio AUD_CLKID_MST_B_LRCLK&gt;;</div><div class='del'>-		clock-names = "mclk", "sclk", "lrclk";</div><div class='add'>+		clocks = &lt;&amp;clkc_audio AUD_CLKID_MST_B_SCLK&gt;,</div><div class='add'>+			 &lt;&amp;clkc_audio AUD_CLKID_MST_B_LRCLK&gt;,</div><div class='add'>+			 &lt;&amp;clkc_audio AUD_CLKID_MST_B_MCLK&gt;;</div><div class='add'>+		clock-names = "sclk", "lrclk", "mclk";</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -38,10 +37,10 @@</div><div class='ctx'> 		compatible = "amlogic,axg-tdm-iface";</div><div class='ctx'> 		#sound-dai-cells = &lt;0&gt;;</div><div class='ctx'> 		sound-name-prefix = "TDM_C";</div><div class='del'>-		clocks = &lt;&amp;clkc_audio AUD_CLKID_MST_C_MCLK&gt;,</div><div class='del'>-			 &lt;&amp;clkc_audio AUD_CLKID_MST_C_SCLK&gt;,</div><div class='del'>-			 &lt;&amp;clkc_audio AUD_CLKID_MST_C_LRCLK&gt;;</div><div class='del'>-		clock-names = "mclk", "sclk", "lrclk";</div><div class='add'>+		clocks = &lt;&amp;clkc_audio AUD_CLKID_MST_C_SCLK&gt;,</div><div class='add'>+			 &lt;&amp;clkc_audio AUD_CLKID_MST_C_LRCLK&gt;,</div><div class='add'>+			 &lt;&amp;clkc_audio AUD_CLKID_MST_C_MCLK&gt;;</div><div class='add'>+		clock-names = "sclk", "lrclk", "mclk";</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='hunk'>@@ -196,8 +195,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		tdmin_a: audio-controller@300 {</div><div class='del'>-			compatible = "amlogic,g12a-tdmin",</div><div class='del'>-				     "amlogic,axg-tdmin";</div><div class='add'>+			compatible = "amlogic,g12a-tdmin";</div><div class='ctx'> 			reg = &lt;0x0 0x300 0x0 0x40&gt;;</div><div class='ctx'> 			sound-name-prefix = "TDMIN_A";</div><div class='ctx'> 			resets = &lt;&amp;clkc_audio AUD_RESET_TDMIN_A&gt;;</div><div class='hunk'>@@ -212,8 +210,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		tdmin_b: audio-controller@340 {</div><div class='del'>-			compatible = "amlogic,g12a-tdmin",</div><div class='del'>-				     "amlogic,axg-tdmin";</div><div class='add'>+			compatible = "amlogic,g12a-tdmin";</div><div class='ctx'> 			reg = &lt;0x0 0x340 0x0 0x40&gt;;</div><div class='ctx'> 			sound-name-prefix = "TDMIN_B";</div><div class='ctx'> 			resets = &lt;&amp;clkc_audio AUD_RESET_TDMIN_B&gt;;</div><div class='hunk'>@@ -228,8 +225,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		tdmin_c: audio-controller@380 {</div><div class='del'>-			compatible = "amlogic,g12a-tdmin",</div><div class='del'>-				     "amlogic,axg-tdmin";</div><div class='add'>+			compatible = "amlogic,g12a-tdmin";</div><div class='ctx'> 			reg = &lt;0x0 0x380 0x0 0x40&gt;;</div><div class='ctx'> 			sound-name-prefix = "TDMIN_C";</div><div class='ctx'> 			resets = &lt;&amp;clkc_audio AUD_RESET_TDMIN_C&gt;;</div><div class='hunk'>@@ -244,8 +240,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		tdmin_lb: audio-controller@3c0 {</div><div class='del'>-			compatible = "amlogic,g12a-tdmin",</div><div class='del'>-				     "amlogic,axg-tdmin";</div><div class='add'>+			compatible = "amlogic,g12a-tdmin";</div><div class='ctx'> 			reg = &lt;0x0 0x3c0 0x0 0x40&gt;;</div><div class='ctx'> 			sound-name-prefix = "TDMIN_LB";</div><div class='ctx'> 			resets = &lt;&amp;clkc_audio AUD_RESET_TDMIN_LB&gt;;</div><div class='hunk'>@@ -273,12 +268,12 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		spdifout: audio-controller@480 {</div><div class='add'>+		spdifout_a: audio-controller@480 {</div><div class='ctx'> 			compatible = "amlogic,g12a-spdifout",</div><div class='ctx'> 				     "amlogic,axg-spdifout";</div><div class='ctx'> 			reg = &lt;0x0 0x480 0x0 0x50&gt;;</div><div class='ctx'> 			#sound-dai-cells = &lt;0&gt;;</div><div class='del'>-			sound-name-prefix = "SPDIFOUT";</div><div class='add'>+			sound-name-prefix = "SPDIFOUT_A";</div><div class='ctx'> 			clocks = &lt;&amp;clkc_audio AUD_CLKID_SPDIFOUT&gt;,</div><div class='ctx'> 				 &lt;&amp;clkc_audio AUD_CLKID_SPDIFOUT_CLK&gt;;</div><div class='ctx'> 			clock-names = "pclk", "mclk";</div><div class='hunk'>@@ -344,6 +339,15 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		toacodec: audio-controller@740 {</div><div class='add'>+			compatible = "amlogic,g12a-toacodec";</div><div class='add'>+			reg = &lt;0x0 0x740 0x0 0x4&gt;;</div><div class='add'>+			#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+			sound-name-prefix = "TOACODEC";</div><div class='add'>+			resets = &lt;&amp;clkc_audio AUD_RESET_TOACODEC&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		tohdmitx: audio-controller@744 {</div><div class='ctx'> 			compatible = "amlogic,g12a-tohdmitx";</div><div class='ctx'> 			reg = &lt;0x0 0x744 0x0 0x4&gt;;</div><div class='hunk'>@@ -355,33 +359,14 @@</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;cpu_thermal {</div><div class='del'>-	cooling-maps {</div><div class='del'>-		map0 {</div><div class='del'>-			trip = &lt;&amp;cpu_passive&gt;;</div><div class='del'>-			cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='del'>-					 &lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='del'>-					 &lt;&amp;cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='del'>-					 &lt;&amp;cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='del'>-					 &lt;&amp;cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='del'>-					 &lt;&amp;cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='del'>-		};</div><div class='del'>-		map1 {</div><div class='del'>-			trip = &lt;&amp;cpu_hot&gt;;</div><div class='del'>-			cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='del'>-					 &lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='del'>-					 &lt;&amp;cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='del'>-					 &lt;&amp;cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='del'>-					 &lt;&amp;cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='del'>-					 &lt;&amp;cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> &amp;ethmac {</div><div class='ctx'> 	power-domains = &lt;&amp;pwrc PWRC_G12A_ETH_ID&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	power-domains = &lt;&amp;pwrc PWRC_G12A_VPU_ID&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;vpu {</div><div class='ctx'> 	power-domains = &lt;&amp;pwrc PWRC_G12A_VPU_ID&gt;;</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am-brcm.dtso b/arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am-brcm.dtso<br/>new file mode 100644<br/>index 000000000000..9591fdc31ee0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am-brcm.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am-brcm.dtso</a></div><div class='hunk'>@@ -0,0 +1,31 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+// Copyright (c) 2024 Freebox SAS</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/meson-g12a-gpio.h&gt;</div><div class='add'>+</div><div class='add'>+&amp;uart_A {</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "brcm,bcm43438-bt";</div><div class='add'>+		shutdown-gpios = &lt;&amp;gpio GPIOX_17 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		max-speed = &lt;2000000&gt;;</div><div class='add'>+		clocks = &lt;&amp;wifi32k&gt;;</div><div class='add'>+		clock-names = "lpo";</div><div class='add'>+		vbat-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+		vddio-supply = &lt;&amp;vddio_ao1v8&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sd_emmc_a {</div><div class='add'>+	/* Per mmc-controller.yaml */</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	/* NB: may be either AP6398S or AP6398SR3 wifi module */</div><div class='add'>+	brcmf: wifi@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		compatible = "brcm,bcm4329-fmac";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am-realtek.dtso b/arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am-realtek.dtso<br/>new file mode 100644<br/>index 000000000000..55fff35b09ae<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am-realtek.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am-realtek.dtso</a></div><div class='hunk'>@@ -0,0 +1,21 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+// Copyright (c) 2024 Freebox SAS</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/meson-g12a-gpio.h&gt;</div><div class='add'>+</div><div class='add'>+&amp;uart_A {</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "realtek,rtl8822cs-bt";</div><div class='add'>+		enable-gpios = &lt;&amp;gpio GPIOX_17 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		host-wake-gpios = &lt;&amp;gpio GPIOX_19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		device-wake-gpios = &lt;&amp;gpio GPIOX_18 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sd_emmc_a {</div><div class='add'>+	/* No explicit compatible for rtl8822cs sdio */</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am.dts<br/>new file mode 100644<br/>index 000000000000..d0a3b4b9229c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am.dts</a></div><div class='hunk'>@@ -0,0 +1,458 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+// Copyright (c) 2024 Freebox SAS</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * SEI codename: SEI530FB (based on SEI510)</div><div class='add'>+ * Freebox codename: fbx8am</div><div class='add'>+ * Commercial names: Freebox Pop, Player TV Free 4K</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "meson-g12a.dtsi"</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/meson-g12a-gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/meson-g12a-tohdmitx.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "freebox,fbx8am", "amlogic,g12a";</div><div class='add'>+	model = "Freebox Player Pop";</div><div class='add'>+	chassis-type = "embedded";</div><div class='add'>+</div><div class='add'>+	firmware {</div><div class='add'>+		optee {</div><div class='add'>+			compatible = "linaro,optee-tz";</div><div class='add'>+			method = "smc";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys-polled {</div><div class='add'>+		compatible = "gpio-keys-polled";</div><div class='add'>+		poll-interval = &lt;100&gt;;</div><div class='add'>+</div><div class='add'>+		/* Physical user-accessible reset button near USB port */</div><div class='add'>+		power-button {</div><div class='add'>+			label = "Reset";</div><div class='add'>+			linux,code = &lt;BTN_MISC&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spdif_dit: audio-codec-2 {</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		compatible = "linux,spdif-dit";</div><div class='add'>+		status = "okay";</div><div class='add'>+		sound-name-prefix = "DIT";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart_AO;</div><div class='add'>+		ethernet0 = &amp;ethmac;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	emmc_pwrseq: emmc-pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-emmc";</div><div class='add'>+		reset-gpios = &lt;&amp;gpio BOOT_12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdmi-connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		type = "a";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			hdmi_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_tx_tmds_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x0 0x0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ao_5v: regulator-ao-5v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "AO_5V";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;dc_in&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dc_in: regulator-dc-in {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "DC_IN";</div><div class='add'>+		regulator-min-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	emmc_1v8: regulator-emmc-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "EMMC_1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddao_3v3: regulator-vddao-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDAO_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;ao_5v&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddao_3v3_t: regulator-vddao-3v3-t {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDAO_3V3_T";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio GPIOH_8 GPIO_OPEN_DRAIN&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddcpu: regulator-vddcpu {</div><div class='add'>+		/*</div><div class='add'>+		 * SY8120B1ABC DC/DC Regulator.</div><div class='add'>+		 */</div><div class='add'>+		compatible = "pwm-regulator";</div><div class='add'>+</div><div class='add'>+		regulator-name = "VDDCPU";</div><div class='add'>+		regulator-min-microvolt = &lt;721000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1022000&gt;;</div><div class='add'>+</div><div class='add'>+		pwm-supply = &lt;&amp;ao_5v&gt;;</div><div class='add'>+</div><div class='add'>+		pwms = &lt;&amp;pwm_AO_cd 1 1250 0&gt;;</div><div class='add'>+		pwm-dutycycle-range = &lt;100 0&gt;;</div><div class='add'>+</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddio_ao1v8: regulator-vddio-ao1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDIO_AO1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdio_pwrseq: sdio-pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-simple";</div><div class='add'>+		reset-gpios = &lt;&amp;gpio GPIOX_6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		post-power-on-delay-ms = &lt;10&gt;; /* required for 43752 */</div><div class='add'>+		clocks = &lt;&amp;wifi32k&gt;;</div><div class='add'>+		clock-names = "ext_clock";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wifi32k: wifi32k {</div><div class='add'>+		compatible = "pwm-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;32768&gt;;</div><div class='add'>+		pwms = &lt;&amp;pwm_ef 0 30518 0&gt;; /* PWM_E at 32.768KHz */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "amlogic,axg-sound-card";</div><div class='add'>+		model = "fbx8am";</div><div class='add'>+		audio-aux-devs = &lt;&amp;tdmout_b&gt;;</div><div class='add'>+		audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",</div><div class='add'>+				"TDMOUT_B IN 1", "FRDDR_B OUT 1",</div><div class='add'>+				"TDMOUT_B IN 2", "FRDDR_C OUT 1",</div><div class='add'>+				"TDM_B Playback", "TDMOUT_B OUT",</div><div class='add'>+				"SPDIFOUT_A IN 0", "FRDDR_A OUT 3",</div><div class='add'>+				"SPDIFOUT_A IN 1", "FRDDR_B OUT 3",</div><div class='add'>+				"SPDIFOUT_A IN 2", "FRDDR_C OUT 3";</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;294912000&gt;,</div><div class='add'>+				       &lt;270950400&gt;,</div><div class='add'>+				       &lt;393216000&gt;;</div><div class='add'>+</div><div class='add'>+		dai-link-0 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_a&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-1 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_b&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-2 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_c&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* 8ch hdmi interface */</div><div class='add'>+		dai-link-3 {</div><div class='add'>+			sound-dai = &lt;&amp;tdmif_b&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			dai-tdm-slot-tx-mask-0 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-1 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-2 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-3 = &lt;1 1&gt;;</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_IN_B&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* spdif hdmi or toslink interface */</div><div class='add'>+		dai-link-4 {</div><div class='add'>+			sound-dai = &lt;&amp;spdifout_a&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+			sound-dai = &lt;&amp;spdif_dit&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			codec-1 {</div><div class='add'>+				sound-dai = &lt;&amp;tohdmitx TOHDMITX_SPDIF_IN_A&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* spdif hdmi interface */</div><div class='add'>+		dai-link-5 {</div><div class='add'>+			sound-dai = &lt;&amp;spdifout_b&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;tohdmitx TOHDMITX_SPDIF_IN_B&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* hdmi glue */</div><div class='add'>+		dai-link-6 {</div><div class='add'>+			sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;arb {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cecb_AO {</div><div class='add'>+	pinctrl-0 = &lt;&amp;cec_ao_b_h_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+	hdmi-phandle = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;clkc_audio {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPU_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu1 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPU_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu2 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPU_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu3 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPU_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethmac {</div><div class='add'>+	status = "okay";</div><div class='add'>+	phy-handle = &lt;&amp;internal_ephy&gt;;</div><div class='add'>+	phy-mode = "rmii";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spdifout_a {</div><div class='add'>+	pinctrl-0 = &lt;&amp;spdif_out_h_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spdifout_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;hdmitx_hpd_pins&gt;, &lt;&amp;hdmitx_ddc_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx_tmds_port {</div><div class='add'>+	hdmi_tx_tmds_out: endpoint {</div><div class='add'>+		remote-endpoint = &lt;&amp;hdmi_connector_in&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c3_sda_a_pins&gt;, &lt;&amp;i2c3_sck_a_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ir {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;remote_input_ao_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm_AO_cd {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm_ao_d_e_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm_ef {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm_e_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pdm {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pdm_din0_z_pins&gt;, &lt;&amp;pdm_din1_z_pins&gt;,</div><div class='add'>+		    &lt;&amp;pdm_din2_z_pins&gt;, &lt;&amp;pdm_din3_z_pins&gt;,</div><div class='add'>+		    &lt;&amp;pdm_dclk_z_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;saradc {</div><div class='add'>+	status = "okay";</div><div class='add'>+	vref-supply = &lt;&amp;vddio_ao1v8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SDIO */</div><div class='add'>+&amp;sd_emmc_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdio_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;sdio_clk_gate_pins&gt;;</div><div class='add'>+	pinctrl-names = "default", "clk-gate";</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	sd-uhs-sdr50;</div><div class='add'>+	max-frequency = &lt;100000000&gt;;</div><div class='add'>+</div><div class='add'>+	non-removable;</div><div class='add'>+	disable-wp;</div><div class='add'>+</div><div class='add'>+	/* WiFi firmware requires power to be kept while in suspend */</div><div class='add'>+	keep-power-in-suspend;</div><div class='add'>+</div><div class='add'>+	mmc-pwrseq = &lt;&amp;sdio_pwrseq&gt;;</div><div class='add'>+</div><div class='add'>+	vmmc-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;vddio_ao1v8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SD card */</div><div class='add'>+&amp;sd_emmc_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdcard_c_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;sdcard_clk_gate_c_pins&gt;;</div><div class='add'>+	pinctrl-names = "default", "clk-gate";</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	max-frequency = &lt;50000000&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+</div><div class='add'>+	cd-gpios = &lt;&amp;gpio GPIOC_6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* eMMC */</div><div class='add'>+&amp;sd_emmc_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;emmc_ctrl_pins&gt;, &lt;&amp;emmc_data_8b_pins&gt;, &lt;&amp;emmc_ds_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;emmc_clk_gate_pins&gt;;</div><div class='add'>+	pinctrl-names = "default", "clk-gate";</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	cap-mmc-highspeed;</div><div class='add'>+	mmc-ddr-1_8v;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	disable-wp;</div><div class='add'>+</div><div class='add'>+	mmc-pwrseq = &lt;&amp;emmc_pwrseq&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;emmc_1v8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmif_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmout_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tohdmitx {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart_A {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart_a_pins&gt;, &lt;&amp;uart_a_cts_rts_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart_AO {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart_ao_a_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb {</div><div class='add'>+	status = "okay";</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts<br/>new file mode 100644<br/>index 000000000000..4353485c6f26<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts</a></div><div class='hunk'>@@ -0,0 +1,399 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2018 BayLibre SAS. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "meson-g12a.dtsi"</div><div class='add'>+#include &lt;dt-bindings/gpio/meson-g12a-gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/meson-g12a-tohdmitx.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "radxa,zero", "amlogic,g12a";</div><div class='add'>+	model = "Radxa Zero";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart_AO;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x0 0x0 0x40000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cvbs-connector {</div><div class='add'>+		status = "disabled";</div><div class='add'>+		compatible = "composite-video-connector";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			cvbs_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;cvbs_vdac_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdmi-connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		type = "a";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			hdmi_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_tx_tmds_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	emmc_pwrseq: emmc-pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-emmc";</div><div class='add'>+		reset-gpios = &lt;&amp;gpio BOOT_12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdio_pwrseq: sdio-pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-simple";</div><div class='add'>+		reset-gpios = &lt;&amp;gpio GPIOX_6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		clocks = &lt;&amp;wifi32k&gt;;</div><div class='add'>+		clock-names = "ext_clock";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ao_5v: regulator-ao-5v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "AO_5V";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vcc_1v8: regulator-vcc-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCC_1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vcc_3v3&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vcc_3v3: regulator-vcc-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCC_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdmi_pw: regulator-hdmi-pw {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "HDMI_PW";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;ao_5v&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddao_1v8: regulator-vddao-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDAO_1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddao_3v3: regulator-vddao-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDAO_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;ao_5v&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddcpu: regulator-vddcpu {</div><div class='add'>+		compatible = "pwm-regulator";</div><div class='add'>+</div><div class='add'>+		regulator-name = "VDDCPU";</div><div class='add'>+		regulator-min-microvolt = &lt;721000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1022000&gt;;</div><div class='add'>+</div><div class='add'>+		vin-supply = &lt;&amp;ao_5v&gt;;</div><div class='add'>+</div><div class='add'>+		pwms = &lt;&amp;pwm_AO_cd 1 1250 0&gt;;</div><div class='add'>+		pwm-dutycycle-range = &lt;100 0&gt;;</div><div class='add'>+</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "amlogic,axg-sound-card";</div><div class='add'>+		model = "RADXA-ZERO";</div><div class='add'>+		audio-aux-devs = &lt;&amp;tdmout_b&gt;;</div><div class='add'>+		audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",</div><div class='add'>+				"TDMOUT_B IN 1", "FRDDR_B OUT 1",</div><div class='add'>+				"TDMOUT_B IN 2", "FRDDR_C OUT 1",</div><div class='add'>+				"TDM_B Playback", "TDMOUT_B OUT";</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;294912000&gt;,</div><div class='add'>+				       &lt;270950400&gt;,</div><div class='add'>+				       &lt;393216000&gt;;</div><div class='add'>+</div><div class='add'>+		dai-link-0 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_a&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-1 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_b&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-2 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_c&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* 8ch hdmi interface */</div><div class='add'>+		dai-link-3 {</div><div class='add'>+			sound-dai = &lt;&amp;tdmif_b&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			dai-tdm-slot-tx-mask-0 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-1 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-2 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-3 = &lt;1 1&gt;;</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_IN_B&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-4 {</div><div class='add'>+			sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wifi32k: wifi32k {</div><div class='add'>+		compatible = "pwm-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;32768&gt;;</div><div class='add'>+		pwms = &lt;&amp;pwm_ef 0 30518 0&gt;; /* PWM_E at 32.768KHz */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;arb {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cec_AO {</div><div class='add'>+	pinctrl-0 = &lt;&amp;cec_ao_a_h_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "disabled";</div><div class='add'>+	hdmi-phandle = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cecb_AO {</div><div class='add'>+	pinctrl-0 = &lt;&amp;cec_ao_b_h_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+	hdmi-phandle = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;clkc_audio {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPU_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu1 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPU_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu2 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPU_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu3 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPU_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cvbs_vdac_port {</div><div class='add'>+	cvbs_vdac_out: endpoint {</div><div class='add'>+		remote-endpoint = &lt;&amp;cvbs_connector_in&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;hdmitx_hpd_pins&gt;, &lt;&amp;hdmitx_ddc_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	hdmi-supply = &lt;&amp;hdmi_pw&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx_tmds_port {</div><div class='add'>+	hdmi_tx_tmds_out: endpoint {</div><div class='add'>+		remote-endpoint = &lt;&amp;hdmi_connector_in&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ir {</div><div class='add'>+	status = "disabled";</div><div class='add'>+	pinctrl-0 = &lt;&amp;remote_input_ao_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm_AO_cd {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm_ao_d_e_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm_ef {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm_e_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;saradc {</div><div class='add'>+	status = "okay";</div><div class='add'>+	vref-supply = &lt;&amp;vddao_1v8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SDIO */</div><div class='add'>+&amp;sd_emmc_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdio_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;sdio_clk_gate_pins&gt;;</div><div class='add'>+	pinctrl-names = "default", "clk-gate";</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	sd-uhs-sdr50;</div><div class='add'>+	max-frequency = &lt;100000000&gt;;</div><div class='add'>+</div><div class='add'>+	non-removable;</div><div class='add'>+	disable-wp;</div><div class='add'>+</div><div class='add'>+	/* WiFi firmware requires power to be kept while in suspend */</div><div class='add'>+	keep-power-in-suspend;</div><div class='add'>+</div><div class='add'>+	mmc-pwrseq = &lt;&amp;sdio_pwrseq&gt;;</div><div class='add'>+</div><div class='add'>+	vmmc-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;vddao_1v8&gt;;</div><div class='add'>+</div><div class='add'>+	brcmf: wifi@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		compatible = "brcm,bcm4329-fmac";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SD card */</div><div class='add'>+&amp;sd_emmc_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdcard_c_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;sdcard_clk_gate_c_pins&gt;;</div><div class='add'>+	pinctrl-names = "default", "clk-gate";</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	max-frequency = &lt;100000000&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+</div><div class='add'>+	cd-gpios = &lt;&amp;gpio GPIOC_6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* eMMC */</div><div class='add'>+&amp;sd_emmc_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;emmc_ctrl_pins&gt;, &lt;&amp;emmc_data_8b_pins&gt;, &lt;&amp;emmc_ds_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;emmc_clk_gate_pins&gt;;</div><div class='add'>+	pinctrl-names = "default", "clk-gate";</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	cap-mmc-highspeed;</div><div class='add'>+	mmc-ddr-1_8v;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+</div><div class='add'>+	mmc-pwrseq = &lt;&amp;emmc_pwrseq&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;vcc_3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;vcc_1v8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmif_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmout_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tohdmitx {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart_A {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart_a_pins&gt;, &lt;&amp;uart_a_cts_rts_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "brcm,bcm43438-bt";</div><div class='add'>+		shutdown-gpios = &lt;&amp;gpio GPIOX_17 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		max-speed = &lt;2000000&gt;;</div><div class='add'>+		clocks = &lt;&amp;wifi32k&gt;;</div><div class='add'>+		clock-names = "lpo";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart_AO {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart_ao_a_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts<br/>index b00d0468c753..f39fcabc763f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts</a></div><div class='hunk'>@@ -15,7 +15,7 @@</div><div class='ctx'> 	compatible = "seirobotics,sei510", "amlogic,g12a";</div><div class='ctx'> 	model = "SEI Robotics SEI510";</div><div class='ctx'> </div><div class='del'>-	adc_keys {</div><div class='add'>+	keys {</div><div class='ctx'> 		compatible = "adc-keys";</div><div class='ctx'> 		io-channels = &lt;&amp;saradc 0&gt;;</div><div class='ctx'> 		io-channel-names = "buttons";</div><div class='hunk'>@@ -45,7 +45,6 @@</div><div class='ctx'> 		compatible = "dmic-codec";</div><div class='ctx'> 		num-channels = &lt;2&gt;;</div><div class='ctx'> 		wakeup-delay-ms = &lt;50&gt;;</div><div class='del'>-		status = "okay";</div><div class='ctx'> 		sound-name-prefix = "MIC";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -84,7 +83,7 @@</div><div class='ctx'> 		reg = &lt;0x0 0x0 0x0 0x40000000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	ao_5v: regulator-ao_5v {</div><div class='add'>+	ao_5v: regulator-ao-5v {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "AO_5V";</div><div class='ctx'> 		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='hunk'>@@ -93,7 +92,7 @@</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	dc_in: regulator-dc_in {</div><div class='add'>+	dc_in: regulator-dc-in {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "DC_IN";</div><div class='ctx'> 		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='hunk'>@@ -101,7 +100,7 @@</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	emmc_1v8: regulator-emmc_1v8 {</div><div class='add'>+	emmc_1v8: regulator-emmc-1v8 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "EMMC_1V8";</div><div class='ctx'> 		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='hunk'>@@ -110,7 +109,7 @@</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vddao_3v3: regulator-vddao_3v3 {</div><div class='add'>+	vddao_3v3: regulator-vddao-3v3 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VDDAO_3V3";</div><div class='ctx'> 		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='hunk'>@@ -119,7 +118,7 @@</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vddao_3v3_t: regultor-vddao_3v3_t {</div><div class='add'>+	vddao_3v3_t: regulator-vddao-3v3-t {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VDDAO_3V3_T";</div><div class='ctx'> 		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='hunk'>@@ -139,7 +138,7 @@</div><div class='ctx'> 		regulator-min-microvolt = &lt;721000&gt;;</div><div class='ctx'> 		regulator-max-microvolt = &lt;1022000&gt;;</div><div class='ctx'> </div><div class='del'>-		vin-supply = &lt;&amp;dc_in&gt;;</div><div class='add'>+		pwm-supply = &lt;&amp;dc_in&gt;;</div><div class='ctx'> </div><div class='ctx'> 		pwms = &lt;&amp;pwm_AO_cd 1 1250 0&gt;;</div><div class='ctx'> 		pwm-dutycycle-range = &lt;100 0&gt;;</div><div class='hunk'>@@ -148,7 +147,7 @@</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vddio_ao1v8: regulator-vddio_ao1v8 {</div><div class='add'>+	vddio_ao1v8: regulator-vddio-ao1v8 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VDDIO_AO1V8";</div><div class='ctx'> 		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='hunk'>@@ -157,14 +156,6 @@</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	reserved-memory {</div><div class='del'>-		/* TEE Reserved Memory */</div><div class='del'>-		bl32_reserved: bl32@5000000 {</div><div class='del'>-			reg = &lt;0x0 0x05300000 0x0 0x2000000&gt;;</div><div class='del'>-			no-map;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='ctx'> 	sdio_pwrseq: sdio-pwrseq {</div><div class='ctx'> 		compatible = "mmc-pwrseq-simple";</div><div class='ctx'> 		reset-gpios = &lt;&amp;gpio GPIOX_6 GPIO_ACTIVE_LOW&gt;;</div><div class='hunk'>@@ -181,7 +172,7 @@</div><div class='ctx'> </div><div class='ctx'> 	sound {</div><div class='ctx'> 		compatible = "amlogic,axg-sound-card";</div><div class='del'>-		model = "G12A-SEI510";</div><div class='add'>+		model = "SEI510";</div><div class='ctx'> 		audio-aux-devs = &lt;&amp;tdmout_a&gt;, &lt;&amp;tdmout_b&gt;,</div><div class='ctx'> 				 &lt;&amp;tdmin_a&gt;, &lt;&amp;tdmin_b&gt;;</div><div class='ctx'> 		audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",</div><div class='hunk'>@@ -210,6 +201,10 @@</div><div class='ctx'> 				"TODDR_B IN 1", "TDMIN_B OUT",</div><div class='ctx'> 				"TODDR_C IN 1", "TDMIN_B OUT";</div><div class='ctx'> </div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+</div><div class='ctx'> 		assigned-clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='ctx'> 				  &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='ctx'> 				  &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='hunk'>@@ -217,7 +212,6 @@</div><div class='ctx'> 		assigned-clock-rates = &lt;294912000&gt;,</div><div class='ctx'> 				       &lt;270950400&gt;,</div><div class='ctx'> 				       &lt;393216000&gt;;</div><div class='del'>-		status = "okay";</div><div class='ctx'> </div><div class='ctx'> 		dai-link-0 {</div><div class='ctx'> 			sound-dai = &lt;&amp;frddr_a&gt;;</div><div class='hunk'>@@ -320,28 +314,24 @@</div><div class='ctx'> 	cpu-supply = &lt;&amp;vddcpu&gt;;</div><div class='ctx'> 	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='ctx'> 	clocks = &lt;&amp;clkc CLKID_CPU_CLK&gt;;</div><div class='del'>-	clock-latency = &lt;50000&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cpu1 {</div><div class='ctx'> 	cpu-supply = &lt;&amp;vddcpu&gt;;</div><div class='ctx'> 	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='ctx'> 	clocks = &lt;&amp;clkc CLKID_CPU_CLK&gt;;</div><div class='del'>-	clock-latency = &lt;50000&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cpu2 {</div><div class='ctx'> 	cpu-supply = &lt;&amp;vddcpu&gt;;</div><div class='ctx'> 	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='ctx'> 	clocks = &lt;&amp;clkc CLKID_CPU_CLK&gt;;</div><div class='del'>-	clock-latency = &lt;50000&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cpu3 {</div><div class='ctx'> 	cpu-supply = &lt;&amp;vddcpu&gt;;</div><div class='ctx'> 	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='ctx'> 	clocks = &lt;&amp;clkc CLKID_CPU_CLK&gt;;</div><div class='del'>-	clock-latency = &lt;50000&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cvbs_vdac_port {</div><div class='hunk'>@@ -395,8 +385,6 @@</div><div class='ctx'> &amp;pwm_AO_cd {</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pwm_ao_d_e_pins&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='del'>-	clocks = &lt;&amp;xtal&gt;;</div><div class='del'>-	clock-names = "clkin1";</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -404,8 +392,6 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pwm_e_pins&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='del'>-	clocks = &lt;&amp;xtal&gt;;</div><div class='del'>-	clock-names = "clkin0";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;pdm {</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts<br/>index a26bfe72550f..b5bf8ecc91e6 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts</a></div><div class='hunk'>@@ -8,6 +8,8 @@</div><div class='ctx'> #include "meson-g12a.dtsi"</div><div class='ctx'> #include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/gpio/meson-g12a-gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/meson-g12a-tohdmitx.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/meson-g12a-toacodec.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	compatible = "amlogic,u200", "amlogic,g12a";</div><div class='hunk'>@@ -18,6 +20,25 @@</div><div class='ctx'> 		ethernet0 = &amp;ethmac;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	dioo2133: audio-amplifier-0 {</div><div class='add'>+		compatible = "simple-audio-amplifier";</div><div class='add'>+		enable-gpios = &lt;&amp;gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		VCC-supply = &lt;&amp;vcc_5v&gt;;</div><div class='add'>+		sound-name-prefix = "10U2";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spdif_dir: audio-codec-0 {</div><div class='add'>+		compatible = "linux,spdif-dir";</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		sound-name-prefix = "DIR";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spdif_dit: audio-codec-1 {</div><div class='add'>+		compatible = "linux,spdif-dit";</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		sound-name-prefix = "DIT";</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	chosen {</div><div class='ctx'> 		stdout-path = "serial0:115200n8";</div><div class='ctx'> 	};</div><div class='hunk'>@@ -53,7 +74,7 @@</div><div class='ctx'> 		reg = &lt;0x0 0x0 0x0 0x40000000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	flash_1v8: regulator-flash_1v8 {</div><div class='add'>+	flash_1v8: regulator-flash-1v8 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "FLASH_1V8";</div><div class='ctx'> 		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='hunk'>@@ -62,7 +83,7 @@</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	main_12v: regulator-main_12v {</div><div class='add'>+	main_12v: regulator-main-12v {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "12V";</div><div class='ctx'> 		regulator-min-microvolt = &lt;12000000&gt;;</div><div class='hunk'>@@ -70,7 +91,7 @@</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	usb_pwr_en: regulator-usb_pwr_en {</div><div class='add'>+	usb_pwr_en: regulator-usb-pwr-en {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "USB_PWR_EN";</div><div class='ctx'> 		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='hunk'>@@ -81,7 +102,7 @@</div><div class='ctx'> 		enable-active-high;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vcc_1v8: regulator-vcc_1v8 {</div><div class='add'>+	vcc_1v8: regulator-vcc-1v8 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VCC_1V8";</div><div class='ctx'> 		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='hunk'>@@ -90,7 +111,7 @@</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vcc_3v3: regulator-vcc_3v3 {</div><div class='add'>+	vcc_3v3: regulator-vcc-3v3 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VCC_3V3";</div><div class='ctx'> 		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='hunk'>@@ -100,7 +121,7 @@</div><div class='ctx'> 		/* FIXME: actually controlled by VDDCPU_B_EN */</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vcc_5v: regulator-vcc_5v {</div><div class='add'>+	vcc_5v: regulator-vcc-5v {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VCC_5V";</div><div class='ctx'> 		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='hunk'>@@ -111,7 +132,7 @@</div><div class='ctx'> 		enable-active-high;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vddao_1v8: regulator-vddao_1v8 {</div><div class='add'>+	vddao_1v8: regulator-vddao-1v8 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VDDAO_1V8";</div><div class='ctx'> 		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='hunk'>@@ -120,7 +141,7 @@</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vddao_3v3: regulator-vddao_3v3 {</div><div class='add'>+	vddao_3v3: regulator-vddao-3v3 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VDDAO_3V3";</div><div class='ctx'> 		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='hunk'>@@ -139,7 +160,7 @@</div><div class='ctx'> 		regulator-min-microvolt = &lt;721000&gt;;</div><div class='ctx'> 		regulator-max-microvolt = &lt;1022000&gt;;</div><div class='ctx'> </div><div class='del'>-		vin-supply = &lt;&amp;main_12v&gt;;</div><div class='add'>+		pwm-supply = &lt;&amp;main_12v&gt;;</div><div class='ctx'> </div><div class='ctx'> 		pwms = &lt;&amp;pwm_AO_cd 1 1250 0&gt;;</div><div class='ctx'> 		pwm-dutycycle-range = &lt;100 0&gt;;</div><div class='hunk'>@@ -147,6 +168,221 @@</div><div class='ctx'> 		regulator-boot-on;</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "amlogic,axg-sound-card";</div><div class='add'>+		model = "U200";</div><div class='add'>+		audio-widgets = "Line", "Lineout";</div><div class='add'>+		audio-aux-devs = &lt;&amp;tdmout_a&gt;, &lt;&amp;tdmout_b&gt;, &lt;&amp;tdmout_c&gt;,</div><div class='add'>+				 &lt;&amp;tdmin_a&gt;, &lt;&amp;tdmin_b&gt;, &lt;&amp;tdmin_c&gt;,</div><div class='add'>+				 &lt;&amp;tdmin_lb&gt;, &lt;&amp;dioo2133&gt;;</div><div class='add'>+		audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",</div><div class='add'>+				"TDMOUT_A IN 1", "FRDDR_B OUT 0",</div><div class='add'>+				"TDMOUT_A IN 2", "FRDDR_C OUT 0",</div><div class='add'>+				"TDM_A Playback", "TDMOUT_A OUT",</div><div class='add'>+				"TDMOUT_B IN 0", "FRDDR_A OUT 1",</div><div class='add'>+				"TDMOUT_B IN 1", "FRDDR_B OUT 1",</div><div class='add'>+				"TDMOUT_B IN 2", "FRDDR_C OUT 1",</div><div class='add'>+				"TDM_B Playback", "TDMOUT_B OUT",</div><div class='add'>+				"TDMOUT_C IN 0", "FRDDR_A OUT 2",</div><div class='add'>+				"TDMOUT_C IN 1", "FRDDR_B OUT 2",</div><div class='add'>+				"TDMOUT_C IN 2", "FRDDR_C OUT 2",</div><div class='add'>+				"TDM_C Playback", "TDMOUT_C OUT",</div><div class='add'>+				"SPDIFOUT_A IN 0", "FRDDR_A OUT 3",</div><div class='add'>+				"SPDIFOUT_A IN 1", "FRDDR_B OUT 3",</div><div class='add'>+				"SPDIFOUT_A IN 2", "FRDDR_C OUT 3",</div><div class='add'>+				"SPDIFOUT_B IN 0", "FRDDR_A OUT 4",</div><div class='add'>+				"SPDIFOUT_B IN 1", "FRDDR_B OUT 4",</div><div class='add'>+				"SPDIFOUT_B IN 2", "FRDDR_C OUT 4",</div><div class='add'>+				"TDMIN_A IN 0", "TDM_A Capture",</div><div class='add'>+				"TDMIN_A IN 1", "TDM_B Capture",</div><div class='add'>+				"TDMIN_A IN 2", "TDM_C Capture",</div><div class='add'>+				"TDMIN_A IN 3", "TDM_A Loopback",</div><div class='add'>+				"TDMIN_A IN 4", "TDM_B Loopback",</div><div class='add'>+				"TDMIN_A IN 5", "TDM_C Loopback",</div><div class='add'>+				"TDMIN_B IN 0", "TDM_A Capture",</div><div class='add'>+				"TDMIN_B IN 1", "TDM_B Capture",</div><div class='add'>+				"TDMIN_B IN 2", "TDM_C Capture",</div><div class='add'>+				"TDMIN_B IN 3", "TDM_A Loopback",</div><div class='add'>+				"TDMIN_B IN 4", "TDM_B Loopback",</div><div class='add'>+				"TDMIN_B IN 5", "TDM_C Loopback",</div><div class='add'>+				"TDMIN_C IN 0", "TDM_A Capture",</div><div class='add'>+				"TDMIN_C IN 1", "TDM_B Capture",</div><div class='add'>+				"TDMIN_C IN 2", "TDM_C Capture",</div><div class='add'>+				"TDMIN_C IN 3", "TDM_A Loopback",</div><div class='add'>+				"TDMIN_C IN 4", "TDM_B Loopback",</div><div class='add'>+				"TDMIN_C IN 5", "TDM_C Loopback",</div><div class='add'>+				"TDMIN_LB IN 3", "TDM_A Capture",</div><div class='add'>+				"TDMIN_LB IN 4", "TDM_B Capture",</div><div class='add'>+				"TDMIN_LB IN 5", "TDM_C Capture",</div><div class='add'>+				"TDMIN_LB IN 0", "TDM_A Loopback",</div><div class='add'>+				"TDMIN_LB IN 1", "TDM_B Loopback",</div><div class='add'>+				"TDMIN_LB IN 2", "TDM_C Loopback",</div><div class='add'>+				"TODDR_A IN 0", "TDMIN_A OUT",</div><div class='add'>+				"TODDR_B IN 0", "TDMIN_A OUT",</div><div class='add'>+				"TODDR_C IN 0", "TDMIN_A OUT",</div><div class='add'>+				"TODDR_A IN 1", "TDMIN_B OUT",</div><div class='add'>+				"TODDR_B IN 1", "TDMIN_B OUT",</div><div class='add'>+				"TODDR_C IN 1", "TDMIN_B OUT",</div><div class='add'>+				"TODDR_A IN 2", "TDMIN_C OUT",</div><div class='add'>+				"TODDR_B IN 2", "TDMIN_C OUT",</div><div class='add'>+				"TODDR_C IN 2", "TDMIN_C OUT",</div><div class='add'>+				"TODDR_A IN 3", "SPDIFIN Capture",</div><div class='add'>+				"TODDR_B IN 3", "SPDIFIN Capture",</div><div class='add'>+				"TODDR_C IN 3", "SPDIFIN Capture",</div><div class='add'>+				"TODDR_A IN 6", "TDMIN_LB OUT",</div><div class='add'>+				"TODDR_B IN 6", "TDMIN_LB OUT",</div><div class='add'>+				"TODDR_C IN 6", "TDMIN_LB OUT",</div><div class='add'>+				"10U2 INL", "ACODEC LOLP",</div><div class='add'>+				"10U2 INR", "ACODEC LORP",</div><div class='add'>+				"Lineout", "10U2 OUTL",</div><div class='add'>+				"Lineout", "10U2 OUTR";</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;294912000&gt;,</div><div class='add'>+				       &lt;270950400&gt;,</div><div class='add'>+				       &lt;393216000&gt;;</div><div class='add'>+</div><div class='add'>+		dai-link-0 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_a&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-1 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_b&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-2 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_c&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-3 {</div><div class='add'>+			sound-dai = &lt;&amp;toddr_a&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-4 {</div><div class='add'>+			sound-dai = &lt;&amp;toddr_b&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-5 {</div><div class='add'>+			sound-dai = &lt;&amp;toddr_c&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* Connected to the WIFI/BT chip */</div><div class='add'>+		dai-link-6 {</div><div class='add'>+			sound-dai = &lt;&amp;tdmif_a&gt;;</div><div class='add'>+			dai-format = "dsp_a";</div><div class='add'>+			dai-tdm-slot-tx-mask-0 = &lt;1 1&gt;;</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;toacodec TOACODEC_IN_A&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			codec-1 {</div><div class='add'>+				sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_IN_A&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* Connected to the onboard AD82584F DAC */</div><div class='add'>+		dai-link-7 {</div><div class='add'>+			sound-dai = &lt;&amp;tdmif_b&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			dai-tdm-slot-tx-mask-0 = &lt;1 1&gt;;</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;toacodec TOACODEC_IN_B&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			codec-1 {</div><div class='add'>+				sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_IN_B&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* 8ch HDMI interface */</div><div class='add'>+		dai-link-8 {</div><div class='add'>+			sound-dai = &lt;&amp;tdmif_c&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			dai-tdm-slot-tx-mask-0 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-1 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-2 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-3 = &lt;1 1&gt;;</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;toacodec TOACODEC_IN_C&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			codec-1 {</div><div class='add'>+				sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_IN_C&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* spdif hdmi and coax output */</div><div class='add'>+		dai-link-9 {</div><div class='add'>+			sound-dai = &lt;&amp;spdifout_a&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;spdif_dit&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			codec-1 {</div><div class='add'>+				sound-dai = &lt;&amp;tohdmitx TOHDMITX_SPDIF_IN_A&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* spdif hdmi interface */</div><div class='add'>+		dai-link-10 {</div><div class='add'>+			sound-dai = &lt;&amp;spdifout_b&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;tohdmitx TOHDMITX_SPDIF_IN_B&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* hdmi glue */</div><div class='add'>+		dai-link-11 {</div><div class='add'>+			sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* internal codec glue */</div><div class='add'>+		dai-link-12 {</div><div class='add'>+			sound-dai = &lt;&amp;toacodec TOACODEC_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;acodec&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* spdif coax input */</div><div class='add'>+		dai-link-13 {</div><div class='add'>+			sound-dai = &lt;&amp;spdifin&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;spdif_dir&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;acodec {</div><div class='add'>+	AVDD-supply = &lt;&amp;vddao_1v8&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;arb {</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cec_AO {</div><div class='hunk'>@@ -163,32 +399,36 @@</div><div class='ctx'> 	hdmi-phandle = &lt;&amp;hdmi_tx&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;clkc_audio {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;cpu0 {</div><div class='ctx'> 	cpu-supply = &lt;&amp;vddcpu&gt;;</div><div class='ctx'> 	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='ctx'> 	clocks = &lt;&amp;clkc CLKID_CPU_CLK&gt;;</div><div class='del'>-	clock-latency = &lt;50000&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cpu1 {</div><div class='ctx'> 	cpu-supply = &lt;&amp;vddcpu&gt;;</div><div class='ctx'> 	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='ctx'> 	clocks = &lt;&amp;clkc CLKID_CPU_CLK&gt;;</div><div class='del'>-	clock-latency = &lt;50000&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cpu2 {</div><div class='ctx'> 	cpu-supply = &lt;&amp;vddcpu&gt;;</div><div class='ctx'> 	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='ctx'> 	clocks = &lt;&amp;clkc CLKID_CPU_CLK&gt;;</div><div class='del'>-	clock-latency = &lt;50000&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cpu3 {</div><div class='ctx'> 	cpu-supply = &lt;&amp;vddcpu&gt;;</div><div class='ctx'> 	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='ctx'> 	clocks = &lt;&amp;clkc CLKID_CPU_CLK&gt;;</div><div class='del'>-	clock-latency = &lt;50000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;clkc_audio {</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cvbs_vdac_port {</div><div class='hunk'>@@ -203,6 +443,18 @@</div><div class='ctx'> 	phy-mode = "rmii";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;frddr_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;hdmi_tx {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;hdmitx_hpd_pins&gt;, &lt;&amp;hdmitx_ddc_pins&gt;;</div><div class='hunk'>@@ -246,8 +498,6 @@</div><div class='ctx'> &amp;pwm_AO_cd {</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pwm_ao_d_e_pins&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='del'>-	clocks = &lt;&amp;xtal&gt;;</div><div class='del'>-	clock-names = "clkin1";</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -288,6 +538,95 @@</div><div class='ctx'> 	vqmmc-supply = &lt;&amp;flash_1v8&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;spdifin {</div><div class='add'>+	pinctrl-0 = &lt;&amp;spdif_in_h_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spdifout_a {</div><div class='add'>+	pinctrl-0 = &lt;&amp;spdif_ao_out_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spdifout_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmif_a {</div><div class='add'>+	pinctrl-0 = &lt;&amp;tdm_a_fs_pins&gt;, &lt;&amp;tdm_a_sclk_pins&gt;, &lt;&amp;tdm_a_dout0_pins&gt; ;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmif_b {</div><div class='add'>+	pinctrl-0 = &lt;&amp;mclk0_a_pins&gt;, &lt;&amp;tdm_b_fs_pins&gt;, &lt;&amp;tdm_b_sclk_pins&gt;,</div><div class='add'>+		    &lt;&amp;tdm_b_dout0_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	assigned-clocks = &lt;&amp;clkc_audio AUD_CLKID_TDM_MCLK_PAD0&gt;,</div><div class='add'>+			  &lt;&amp;clkc_audio AUD_CLKID_TDM_SCLK_PAD1&gt;,</div><div class='add'>+			  &lt;&amp;clkc_audio AUD_CLKID_TDM_LRCLK_PAD1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clkc_audio AUD_CLKID_MST_B_MCLK&gt;,</div><div class='add'>+				 &lt;&amp;clkc_audio AUD_CLKID_MST_B_SCLK&gt;,</div><div class='add'>+				 &lt;&amp;clkc_audio AUD_CLKID_MST_B_LRCLK&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmif_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmin_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmin_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmin_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmin_lb {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmout_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmout_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmout_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;toacodec {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;toddr_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;toddr_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;toddr_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tohdmitx {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;uart_AO {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;uart_ao_a_pins&gt;;</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts<br/>index 1b07c8c06eac..5ab460a3e637 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts</a></div><div class='hunk'>@@ -22,7 +22,6 @@</div><div class='ctx'> 	spdif_dit: audio-codec-1 {</div><div class='ctx'> 		#sound-dai-cells = &lt;0&gt;;</div><div class='ctx'> 		compatible = "linux,spdif-dit";</div><div class='del'>-		status = "okay";</div><div class='ctx'> 		sound-name-prefix = "DIT";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -67,7 +66,7 @@</div><div class='ctx'> 		clock-names = "ext_clock";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	flash_1v8: regulator-flash_1v8 {</div><div class='add'>+	flash_1v8: regulator-flash-1v8 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "FLASH_1V8";</div><div class='ctx'> 		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='hunk'>@@ -76,7 +75,7 @@</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	dc_in: regulator-dc_in {</div><div class='add'>+	dc_in: regulator-dc-in {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "DC_IN";</div><div class='ctx'> 		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='hunk'>@@ -84,7 +83,7 @@</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vcc_1v8: regulator-vcc_1v8 {</div><div class='add'>+	vcc_1v8: regulator-vcc-1v8 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VCC_1V8";</div><div class='ctx'> 		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='hunk'>@@ -93,7 +92,7 @@</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vcc_3v3: regulator-vcc_3v3 {</div><div class='add'>+	vcc_3v3: regulator-vcc-3v3 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VCC_3V3";</div><div class='ctx'> 		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='hunk'>@@ -103,7 +102,7 @@</div><div class='ctx'> 		/* FIXME: actually controlled by VDDCPU_B_EN */</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vcc_5v: regulator-vcc_5v {</div><div class='add'>+	vcc_5v: regulator-vcc-5v {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VCC_5V";</div><div class='ctx'> 		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='hunk'>@@ -111,10 +110,9 @@</div><div class='ctx'> 		vin-supply = &lt;&amp;dc_in&gt;;</div><div class='ctx'> </div><div class='ctx'> 		gpio = &lt;&amp;gpio GPIOH_8 GPIO_OPEN_DRAIN&gt;;</div><div class='del'>-		enable-active-low;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vddao_1v8: regulator-vddao_1v8 {</div><div class='add'>+	vddao_1v8: regulator-vddao-1v8 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VDDAO_1V8";</div><div class='ctx'> 		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='hunk'>@@ -123,7 +121,7 @@</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vddao_3v3: regulator-vddao_3v3 {</div><div class='add'>+	vddao_3v3: regulator-vddao-3v3 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VDDAO_3V3";</div><div class='ctx'> 		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='hunk'>@@ -139,7 +137,7 @@</div><div class='ctx'> 		regulator-min-microvolt = &lt;721000&gt;;</div><div class='ctx'> 		regulator-max-microvolt = &lt;1022000&gt;;</div><div class='ctx'> </div><div class='del'>-		vin-supply = &lt;&amp;dc_in&gt;;</div><div class='add'>+		pwm-supply = &lt;&amp;dc_in&gt;;</div><div class='ctx'> </div><div class='ctx'> 		pwms = &lt;&amp;pwm_AO_cd 1 1250 0&gt;;</div><div class='ctx'> 		pwm-dutycycle-range = &lt;100 0&gt;;</div><div class='hunk'>@@ -150,15 +148,19 @@</div><div class='ctx'> </div><div class='ctx'> 	sound {</div><div class='ctx'> 		compatible = "amlogic,axg-sound-card";</div><div class='del'>-		model = "G12A-X96-MAX";</div><div class='add'>+		model = "X96-MAX";</div><div class='ctx'> 		audio-aux-devs = &lt;&amp;tdmout_b&gt;;</div><div class='ctx'> 		audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",</div><div class='ctx'> 				"TDMOUT_B IN 1", "FRDDR_B OUT 1",</div><div class='ctx'> 				"TDMOUT_B IN 2", "FRDDR_C OUT 1",</div><div class='ctx'> 				"TDM_B Playback", "TDMOUT_B OUT",</div><div class='del'>-				"SPDIFOUT IN 0", "FRDDR_A OUT 3",</div><div class='del'>-				"SPDIFOUT IN 1", "FRDDR_B OUT 3",</div><div class='del'>-				"SPDIFOUT IN 2", "FRDDR_C OUT 3";</div><div class='add'>+				"SPDIFOUT_A IN 0", "FRDDR_A OUT 3",</div><div class='add'>+				"SPDIFOUT_A IN 1", "FRDDR_B OUT 3",</div><div class='add'>+				"SPDIFOUT_A IN 2", "FRDDR_C OUT 3";</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='ctx'> </div><div class='ctx'> 		assigned-clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='ctx'> 				  &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='hunk'>@@ -167,7 +169,6 @@</div><div class='ctx'> 		assigned-clock-rates = &lt;294912000&gt;,</div><div class='ctx'> 				       &lt;270950400&gt;,</div><div class='ctx'> 				       &lt;393216000&gt;;</div><div class='del'>-		status = "okay";</div><div class='ctx'> </div><div class='ctx'> 		dai-link-0 {</div><div class='ctx'> 			sound-dai = &lt;&amp;frddr_a&gt;;</div><div class='hunk'>@@ -198,7 +199,7 @@</div><div class='ctx'> </div><div class='ctx'> 		/* spdif hdmi or toslink interface */</div><div class='ctx'> 		dai-link-4 {</div><div class='del'>-			sound-dai = &lt;&amp;spdifout&gt;;</div><div class='add'>+			sound-dai = &lt;&amp;spdifout_a&gt;;</div><div class='ctx'> </div><div class='ctx'> 			codec-0 {</div><div class='ctx'> 				sound-dai = &lt;&amp;spdif_dit&gt;;</div><div class='hunk'>@@ -262,28 +263,24 @@</div><div class='ctx'> 	cpu-supply = &lt;&amp;vddcpu&gt;;</div><div class='ctx'> 	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='ctx'> 	clocks = &lt;&amp;clkc CLKID_CPU_CLK&gt;;</div><div class='del'>-	clock-latency = &lt;50000&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cpu1 {</div><div class='ctx'> 	cpu-supply = &lt;&amp;vddcpu&gt;;</div><div class='ctx'> 	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='ctx'> 	clocks = &lt;&amp;clkc CLKID_CPU_CLK&gt;;</div><div class='del'>-	clock-latency = &lt;50000&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cpu2 {</div><div class='ctx'> 	cpu-supply = &lt;&amp;vddcpu&gt;;</div><div class='ctx'> 	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='ctx'> 	clocks = &lt;&amp;clkc CLKID_CPU_CLK&gt;;</div><div class='del'>-	clock-latency = &lt;50000&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cpu3 {</div><div class='ctx'> 	cpu-supply = &lt;&amp;vddcpu&gt;;</div><div class='ctx'> 	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='ctx'> 	clocks = &lt;&amp;clkc CLKID_CPU_CLK&gt;;</div><div class='del'>-	clock-latency = &lt;50000&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cvbs_vdac_port {</div><div class='hunk'>@@ -327,8 +324,6 @@</div><div class='ctx'> &amp;pwm_AO_cd {</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pwm_ao_d_e_pins&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='del'>-	clocks = &lt;&amp;xtal&gt;;</div><div class='del'>-	clock-names = "clkin1";</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -340,12 +335,12 @@</div><div class='ctx'> 		eee-broken-1000t;</div><div class='ctx'> </div><div class='ctx'> 		reset-assert-us = &lt;10000&gt;;</div><div class='del'>-		reset-deassert-us = &lt;30000&gt;;</div><div class='add'>+		reset-deassert-us = &lt;80000&gt;;</div><div class='ctx'> 		reset-gpios = &lt;&amp;gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)&gt;;</div><div class='ctx'> </div><div class='ctx'> 		interrupt-parent = &lt;&amp;gpio_intc&gt;;</div><div class='ctx'> 		/* MAC_INTR on GPIOZ_14 */</div><div class='del'>-		interrupts = &lt;26 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupts = &lt;IRQID_GPIOZ_14 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -362,8 +357,6 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pwm_e_pins&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='del'>-	clocks = &lt;&amp;xtal&gt;;</div><div class='del'>-	clock-names = "clkin0";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;uart_A {</div><div class='hunk'>@@ -458,7 +451,7 @@</div><div class='ctx'> 	vqmmc-supply = &lt;&amp;flash_1v8&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;spdifout {</div><div class='add'>+&amp;spdifout_a {</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;spdif_out_h_pins&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	status = "okay";</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi<br/>index fb0ab27d1f64..1321ad95923d 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12a.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-g12a.dtsi</a></div><div class='hunk'>@@ -17,6 +17,12 @@</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			reg = &lt;0x0 0x0&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			d-cache-line-size = &lt;32&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-sets = &lt;32&gt;;</div><div class='add'>+			i-cache-line-size = &lt;32&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-sets = &lt;32&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;l2&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='hunk'>@@ -26,6 +32,12 @@</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			reg = &lt;0x0 0x1&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			d-cache-line-size = &lt;32&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-sets = &lt;32&gt;;</div><div class='add'>+			i-cache-line-size = &lt;32&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-sets = &lt;32&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;l2&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='hunk'>@@ -35,6 +47,12 @@</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			reg = &lt;0x0 0x2&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			d-cache-line-size = &lt;32&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-sets = &lt;32&gt;;</div><div class='add'>+			i-cache-line-size = &lt;32&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-sets = &lt;32&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;l2&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='hunk'>@@ -44,12 +62,23 @@</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			reg = &lt;0x0 0x3&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			d-cache-line-size = &lt;32&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-sets = &lt;32&gt;;</div><div class='add'>+			i-cache-line-size = &lt;32&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-sets = &lt;32&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;l2&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		l2: l2-cache0 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x80000&gt;; /* L2. 512 KB */</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;512&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -57,29 +86,10 @@</div><div class='ctx'> 		compatible = "operating-points-v2";</div><div class='ctx'> 		opp-shared;</div><div class='ctx'> </div><div class='del'>-		opp-100000000 {</div><div class='del'>-			opp-hz = /bits/ 64 &lt;100000000&gt;;</div><div class='del'>-			opp-microvolt = &lt;731000&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		opp-250000000 {</div><div class='del'>-			opp-hz = /bits/ 64 &lt;250000000&gt;;</div><div class='del'>-			opp-microvolt = &lt;731000&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		opp-500000000 {</div><div class='del'>-			opp-hz = /bits/ 64 &lt;500000000&gt;;</div><div class='del'>-			opp-microvolt = &lt;731000&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		opp-667000000 {</div><div class='del'>-			opp-hz = /bits/ 64 &lt;666666666&gt;;</div><div class='del'>-			opp-microvolt = &lt;731000&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='ctx'> 		opp-1000000000 {</div><div class='ctx'> 			opp-hz = /bits/ 64 &lt;1000000000&gt;;</div><div class='ctx'> 			opp-microvolt = &lt;731000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;50000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		opp-1200000000 {</div><div class='hunk'>@@ -133,3 +143,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='add'>+</div><div class='add'>+&amp;pmu {</div><div class='add'>+	compatible = "amlogic,g12a-ddr-pmu";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-bananapi-m2s.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-bananapi-m2s.dts<br/>new file mode 100644<br/>index 000000000000..ac6f7ae1d103<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-bananapi-m2s.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-g12b-a311d-bananapi-m2s.dts</a></div><div class='hunk'>@@ -0,0 +1,37 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2023 Christian Hewitt &lt;christianshewitt@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "meson-g12b-a311d.dtsi"</div><div class='add'>+#include "meson-g12b-bananapi.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "bananapi,bpi-m2s", "amlogic,a311d", "amlogic,g12b";</div><div class='add'>+	model = "BananaPi M2S";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		i2c0 = &amp;i2c1;</div><div class='add'>+		i2c1 = &amp;i2c3;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Camera (CSI) bus */</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c1_sda_h6_pins&gt;, &lt;&amp;i2c1_sck_h7_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Display (DSI) bus */</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c3_sda_a_pins&gt;, &lt;&amp;i2c3_sck_a_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;npu {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dts<br/>index 124a80901084..9fd68195be3f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dts</a></div><div class='hunk'>@@ -39,3 +39,7 @@</div><div class='ctx'> 	phy-names = "usb2-phy0", "usb2-phy1";</div><div class='ctx'> };</div><div class='ctx'>  */</div><div class='add'>+</div><div class='add'>+&amp;npu {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-libretech-cc.dts<br/>new file mode 100644<br/>index 000000000000..82546b738977<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-libretech-cc.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-g12b-a311d-libretech-cc.dts</a></div><div class='hunk'>@@ -0,0 +1,117 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2023 BayLibre, SAS.</div><div class='add'>+ * Author: Jerome Brunet &lt;jbrunet@baylibre.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/g12a-clkc.h&gt;</div><div class='add'>+#include "meson-g12b-a311d.dtsi"</div><div class='add'>+#include "meson-libretech-cottonwood.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "libretech,aml-a311d-cc", "amlogic,a311d", "amlogic,g12b";</div><div class='add'>+	model = "Libre Computer AML-A311D-CC Alta";</div><div class='add'>+</div><div class='add'>+	vddcpu_a: regulator-vddcpu-a {</div><div class='add'>+		compatible = "pwm-regulator";</div><div class='add'>+		regulator-name = "VDDCPU_A";</div><div class='add'>+		regulator-min-microvolt = &lt;730000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1011000&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		pwm-supply = &lt;&amp;dc_in&gt;;</div><div class='add'>+		pwms = &lt;&amp;pwm_ab 0 1250 0&gt;;</div><div class='add'>+		pwm-dutycycle-range = &lt;100 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		model = "LC-ALTA";</div><div class='add'>+		audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",</div><div class='add'>+				"TDMOUT_A IN 1", "FRDDR_B OUT 0",</div><div class='add'>+				"TDMOUT_A IN 2", "FRDDR_C OUT 0",</div><div class='add'>+				"TDM_A Playback", "TDMOUT_A OUT",</div><div class='add'>+				"TDMOUT_B IN 0", "FRDDR_A OUT 1",</div><div class='add'>+				"TDMOUT_B IN 1", "FRDDR_B OUT 1",</div><div class='add'>+				"TDMOUT_B IN 2", "FRDDR_C OUT 1",</div><div class='add'>+				"TDM_B Playback", "TDMOUT_B OUT",</div><div class='add'>+				"TDMOUT_C IN 0", "FRDDR_A OUT 2",</div><div class='add'>+				"TDMOUT_C IN 1", "FRDDR_B OUT 2",</div><div class='add'>+				"TDMOUT_C IN 2", "FRDDR_C OUT 2",</div><div class='add'>+				"TDM_C Playback", "TDMOUT_C OUT",</div><div class='add'>+				"TDMIN_A IN 0", "TDM_A Capture",</div><div class='add'>+				"TDMIN_B IN 0", "TDM_A Capture",</div><div class='add'>+				"TDMIN_C IN 0", "TDM_A Capture",</div><div class='add'>+				"TDMIN_A IN 3", "TDM_A Loopback",</div><div class='add'>+				"TDMIN_B IN 3", "TDM_A Loopback",</div><div class='add'>+				"TDMIN_C IN 3", "TDM_A Loopback",</div><div class='add'>+				"TDMIN_A IN 1", "TDM_B Capture",</div><div class='add'>+				"TDMIN_B IN 1", "TDM_B Capture",</div><div class='add'>+				"TDMIN_C IN 1", "TDM_B Capture",</div><div class='add'>+				"TDMIN_A IN 4", "TDM_B Loopback",</div><div class='add'>+				"TDMIN_B IN 4", "TDM_B Loopback",</div><div class='add'>+				"TDMIN_C IN 4", "TDM_B Loopback",</div><div class='add'>+				"TDMIN_A IN 2", "TDM_C Capture",</div><div class='add'>+				"TDMIN_B IN 2", "TDM_C Capture",</div><div class='add'>+				"TDMIN_C IN 2", "TDM_C Capture",</div><div class='add'>+				"TDMIN_A IN 5", "TDM_C Loopback",</div><div class='add'>+				"TDMIN_B IN 5", "TDM_C Loopback",</div><div class='add'>+				"TDMIN_C IN 5", "TDM_C Loopback",</div><div class='add'>+				"TODDR_A IN 0", "TDMIN_A OUT",</div><div class='add'>+				"TODDR_B IN 0", "TDMIN_A OUT",</div><div class='add'>+				"TODDR_C IN 0", "TDMIN_A OUT",</div><div class='add'>+				"TODDR_A IN 1", "TDMIN_B OUT",</div><div class='add'>+				"TODDR_B IN 1", "TDMIN_B OUT",</div><div class='add'>+				"TODDR_C IN 1", "TDMIN_B OUT",</div><div class='add'>+				"TODDR_A IN 2", "TDMIN_C OUT",</div><div class='add'>+				"TODDR_B IN 2", "TDMIN_C OUT",</div><div class='add'>+				"TODDR_C IN 2", "TDMIN_C OUT",</div><div class='add'>+				"Lineout", "ACODEC LOLP",</div><div class='add'>+				"Lineout", "ACODEC LORP";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu_b&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table_0&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPU_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu1 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu_b&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table_0&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPU_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu100 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu_a&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpub_opp_table_1&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPUB_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu101 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu_a&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpub_opp_table_1&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPUB_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu102 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu_a&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpub_opp_table_1&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPUB_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu103 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu_a&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpub_opp_table_1&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPUB_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm_ab {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm_a_e_pins&gt;, &lt;&amp;pwm_b_x7_pins&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;npu {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi<br/>index d61f43052a34..8ecb5bd125c1 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi</a></div><div class='hunk'>@@ -11,29 +11,10 @@</div><div class='ctx'> 		compatible = "operating-points-v2";</div><div class='ctx'> 		opp-shared;</div><div class='ctx'> </div><div class='del'>-		opp-100000000 {</div><div class='del'>-			opp-hz = /bits/ 64 &lt;100000000&gt;;</div><div class='del'>-			opp-microvolt = &lt;731000&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		opp-250000000 {</div><div class='del'>-			opp-hz = /bits/ 64 &lt;250000000&gt;;</div><div class='del'>-			opp-microvolt = &lt;731000&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		opp-500000000 {</div><div class='del'>-			opp-hz = /bits/ 64 &lt;500000000&gt;;</div><div class='del'>-			opp-microvolt = &lt;731000&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		opp-667000000 {</div><div class='del'>-			opp-hz = /bits/ 64 &lt;667000000&gt;;</div><div class='del'>-			opp-microvolt = &lt;731000&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='ctx'> 		opp-1000000000 {</div><div class='ctx'> 			opp-hz = /bits/ 64 &lt;1000000000&gt;;</div><div class='ctx'> 			opp-microvolt = &lt;761000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;50000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		opp-1200000000 {</div><div class='hunk'>@@ -71,29 +52,10 @@</div><div class='ctx'> 		compatible = "operating-points-v2";</div><div class='ctx'> 		opp-shared;</div><div class='ctx'> </div><div class='del'>-		opp-100000000 {</div><div class='del'>-			opp-hz = /bits/ 64 &lt;100000000&gt;;</div><div class='del'>-			opp-microvolt = &lt;731000&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		opp-250000000 {</div><div class='del'>-			opp-hz = /bits/ 64 &lt;250000000&gt;;</div><div class='del'>-			opp-microvolt = &lt;731000&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		opp-500000000 {</div><div class='del'>-			opp-hz = /bits/ 64 &lt;500000000&gt;;</div><div class='del'>-			opp-microvolt = &lt;731000&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		opp-667000000 {</div><div class='del'>-			opp-hz = /bits/ 64 &lt;667000000&gt;;</div><div class='del'>-			opp-microvolt = &lt;731000&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='ctx'> 		opp-1000000000 {</div><div class='ctx'> 			opp-hz = /bits/ 64 &lt;1000000000&gt;;</div><div class='ctx'> 			opp-microvolt = &lt;731000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;50000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		opp-1200000000 {</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4-cm4io.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4-cm4io.dts<br/>new file mode 100644<br/>index 000000000000..2d74456e685d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4-cm4io.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4-cm4io.dts</a></div><div class='hunk'>@@ -0,0 +1,169 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2023 Neil Armstrong &lt;neil.armstrong@linaro.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "meson-g12b-bananapi-cm4.dtsi"</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/meson-g12a-tohdmitx.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "bananapi,bpi-cm4io", "bananapi,bpi-cm4", "amlogic,a311d", "amlogic,g12b";</div><div class='add'>+	model = "BananaPi BPI-CM4IO Baseboard with BPI-CM4 Module";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;ethmac;</div><div class='add'>+		i2c0 = &amp;i2c1;</div><div class='add'>+		i2c1 = &amp;i2c3;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	adc-keys {</div><div class='add'>+		compatible = "adc-keys";</div><div class='add'>+		io-channels = &lt;&amp;saradc 2&gt;;</div><div class='add'>+		io-channel-names = "buttons";</div><div class='add'>+		keyup-threshold-microvolt = &lt;1710000&gt;;</div><div class='add'>+</div><div class='add'>+		button-function {</div><div class='add'>+			label = "Function";</div><div class='add'>+			linux,code = &lt;KEY_FN&gt;;</div><div class='add'>+			press-threshold-microvolt = &lt;10000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdmi_connector: hdmi-connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		type = "a";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			hdmi_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_tx_tmds_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-blue {</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			gpios = &lt;&amp;gpio_ao GPIOAO_7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-green {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			gpios = &lt;&amp;gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "amlogic,axg-sound-card";</div><div class='add'>+		model = "BPI-CM4IO";</div><div class='add'>+		audio-aux-devs = &lt;&amp;tdmout_b&gt;;</div><div class='add'>+		audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",</div><div class='add'>+				"TDMOUT_B IN 1", "FRDDR_B OUT 1",</div><div class='add'>+				"TDMOUT_B IN 2", "FRDDR_C OUT 1",</div><div class='add'>+				"TDM_B Playback", "TDMOUT_B OUT";</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;294912000&gt;,</div><div class='add'>+				       &lt;270950400&gt;,</div><div class='add'>+				       &lt;393216000&gt;;</div><div class='add'>+</div><div class='add'>+		dai-link-0 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_a&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-1 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_b&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-2 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_c&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* 8ch hdmi interface */</div><div class='add'>+		dai-link-3 {</div><div class='add'>+			sound-dai = &lt;&amp;tdmif_b&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			dai-tdm-slot-tx-mask-0 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-1 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-2 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-3 = &lt;1 1&gt;;</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_IN_B&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* hdmi glue */</div><div class='add'>+		dai-link-4 {</div><div class='add'>+			sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cecb_AO {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethmac {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx_tmds_port {</div><div class='add'>+	hdmi_tx_tmds_out: endpoint {</div><div class='add'>+		remote-endpoint = &lt;&amp;hdmi_connector_in&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* CSI port */</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* DSI port for touchscreen */</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* miniPCIe port with USB + SIM slot */</div><div class='add'>+&amp;pcie {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sd_emmc_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tohdmitx {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Peripheral Only USB-C port */</div><div class='add'>+&amp;usb {</div><div class='add'>+	dr_mode = "peripheral";</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4-mnt-reform2.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4-mnt-reform2.dts<br/>new file mode 100644<br/>index 000000000000..0f48c32bec97<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4-mnt-reform2.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4-mnt-reform2.dts</a></div><div class='hunk'>@@ -0,0 +1,388 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2023 Neil Armstrong &lt;neil.armstrong@linaro.org&gt;</div><div class='add'>+ * Copyright 2023 MNT Research GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "meson-g12b-bananapi-cm4.dtsi"</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/meson-g12a-tohdmitx.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "MNT Reform 2 with BPI-CM4 Module";</div><div class='add'>+	compatible = "mntre,reform2-cm4", "bananapi,bpi-cm4", "amlogic,a311d", "amlogic,g12b";</div><div class='add'>+	chassis-type = "laptop";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;ethmac;</div><div class='add'>+		i2c0 = &amp;i2c1;</div><div class='add'>+		i2c1 = &amp;i2c3;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdmi_connector: hdmi-connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		type = "a";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			hdmi_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_tx_tmds_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-blue {</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			gpios = &lt;&amp;gpio_ao GPIOAO_7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-green {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			gpios = &lt;&amp;gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "amlogic,axg-sound-card";</div><div class='add'>+		model = "MNT-REFORM2-BPI-CM4";</div><div class='add'>+		audio-widgets = "Headphone", "Headphone Jack",</div><div class='add'>+				"Speaker", "External Speaker",</div><div class='add'>+				"Microphone", "Mic Jack";</div><div class='add'>+		audio-aux-devs = &lt;&amp;tdmout_a&gt;, &lt;&amp;tdmout_b&gt;, &lt;&amp;tdmin_b&gt;;</div><div class='add'>+		audio-routing =	"TDMOUT_A IN 0", "FRDDR_A OUT 0",</div><div class='add'>+				"TDMOUT_A IN 1", "FRDDR_B OUT 0",</div><div class='add'>+				"TDMOUT_A IN 2", "FRDDR_C OUT 0",</div><div class='add'>+				"TDM_A Playback", "TDMOUT_A OUT",</div><div class='add'>+				"TDMOUT_B IN 0", "FRDDR_A OUT 1",</div><div class='add'>+				"TDMOUT_B IN 1", "FRDDR_B OUT 1",</div><div class='add'>+				"TDMOUT_B IN 2", "FRDDR_C OUT 1",</div><div class='add'>+				"TDM_B Playback", "TDMOUT_B OUT",</div><div class='add'>+				"TDMIN_B IN 1", "TDM_B Capture",</div><div class='add'>+				"TDMIN_B IN 4", "TDM_B Loopback",</div><div class='add'>+				"TODDR_A IN 1", "TDMIN_B OUT",</div><div class='add'>+				"TODDR_B IN 1", "TDMIN_B OUT",</div><div class='add'>+				"TODDR_C IN 1", "TDMIN_B OUT",</div><div class='add'>+				"Headphone Jack", "HP_L",</div><div class='add'>+				"Headphone Jack", "HP_R",</div><div class='add'>+				"External Speaker", "SPK_LP",</div><div class='add'>+				"External Speaker", "SPK_LN",</div><div class='add'>+				"External Speaker", "SPK_RP",</div><div class='add'>+				"External Speaker", "SPK_RN",</div><div class='add'>+				"LINPUT1", "Mic Jack",</div><div class='add'>+				"Mic Jack", "MICB";</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+					&lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+					&lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;294912000&gt;,</div><div class='add'>+				       &lt;270950400&gt;,</div><div class='add'>+				       &lt;393216000&gt;;</div><div class='add'>+</div><div class='add'>+		dai-link-0 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_a&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-1 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_b&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-2 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_c&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-3 {</div><div class='add'>+			sound-dai = &lt;&amp;toddr_a&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-4 {</div><div class='add'>+			sound-dai = &lt;&amp;toddr_b&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-5 {</div><div class='add'>+			sound-dai = &lt;&amp;toddr_c&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* 8ch hdmi interface */</div><div class='add'>+		dai-link-6 {</div><div class='add'>+			sound-dai = &lt;&amp;tdmif_a&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			dai-tdm-slot-tx-mask-0 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-1 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-2 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-3 = &lt;1 1&gt;;</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_IN_A&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* Analog Audio */</div><div class='add'>+		dai-link-7 {</div><div class='add'>+			sound-dai = &lt;&amp;tdmif_b&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			dai-tdm-slot-tx-mask-0 = &lt;1 1&gt;;</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;wm8960&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* hdmi glue */</div><div class='add'>+		dai-link-8 {</div><div class='add'>+			sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_main_1v8: regulator-main-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;reg_main_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_main_1v2: regulator-main-1v2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "1V2";</div><div class='add'>+		regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;reg_main_5v&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_main_3v3: regulator-main-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_main_5v: regulator-main-5v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "5V";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_main_usb: regulator-main-usb {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "USB_PWR";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;reg_main_5v&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	backlight: backlight {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		pwms = &lt;&amp;pwm_AO_ab 0 10000 0&gt;;</div><div class='add'>+		power-supply = &lt;&amp;reg_main_usb&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;gpio 58 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		brightness-levels = &lt;0 32 64 128 160 200 255&gt;;</div><div class='add'>+		default-brightness-level = &lt;6&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	panel {</div><div class='add'>+		compatible = "innolux,n125hce-gn1";</div><div class='add'>+		power-supply = &lt;&amp;reg_main_3v3&gt;;</div><div class='add'>+		backlight = &lt;&amp;backlight&gt;;</div><div class='add'>+		no-hpd;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			panel_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;edp_bridge_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clock_12288: clock_12288 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;12288000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_analog_dphy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_dphy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_dsi {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	assigned-clocks = &lt;&amp;clkc CLKID_GP0_PLL&gt;,</div><div class='add'>+			  &lt;&amp;clkc CLKID_MIPI_DSI_PXCLK_SEL&gt;,</div><div class='add'>+			  &lt;&amp;clkc CLKID_MIPI_DSI_PXCLK&gt;,</div><div class='add'>+			  &lt;&amp;clkc CLKID_CTS_ENCL_SEL&gt;,</div><div class='add'>+			  &lt;&amp;clkc CLKID_VCLK2_SEL&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;0&gt;,</div><div class='add'>+				 &lt;&amp;clkc CLKID_GP0_PLL&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;&amp;clkc CLKID_VCLK2_DIV1&gt;,</div><div class='add'>+				 &lt;&amp;clkc CLKID_GP0_PLL&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;936000000&gt;,</div><div class='add'>+			       &lt;0&gt;,</div><div class='add'>+			       &lt;936000000&gt;,</div><div class='add'>+			       &lt;0&gt;,</div><div class='add'>+			       &lt;0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_dsi_panel_port {</div><div class='add'>+	mipi_dsi_out: endpoint {</div><div class='add'>+		remote-endpoint = &lt;&amp;edp_bridge_in&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cecb_AO {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethmac {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx_tmds_port {</div><div class='add'>+	hdmi_tx_tmds_out: endpoint {</div><div class='add'>+		remote-endpoint = &lt;&amp;hdmi_connector_in&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm_AO_ab {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm_ao_a_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	edp_bridge: bridge@2c {</div><div class='add'>+		compatible = "ti,sn65dsi86";</div><div class='add'>+		reg = &lt;0x2c&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;gpio GPIOX_10 GPIO_ACTIVE_HIGH&gt;; // PIN_24 / GPIO8</div><div class='add'>+		vccio-supply = &lt;&amp;reg_main_1v8&gt;;</div><div class='add'>+		vpll-supply = &lt;&amp;reg_main_1v8&gt;;</div><div class='add'>+		vcca-supply = &lt;&amp;reg_main_1v2&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_main_1v2&gt;;</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				edp_bridge_in: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;mipi_dsi_out&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				edp_bridge_out: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;panel_in&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	wm8960: codec@1a {</div><div class='add'>+		compatible = "wlf,wm8960";</div><div class='add'>+		reg = &lt;0x1a&gt;;</div><div class='add'>+		clocks = &lt;&amp;clock_12288&gt;;</div><div class='add'>+		clock-names = "mclk";</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		wlf,shared-lrclk;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rtc@68 {</div><div class='add'>+		compatible = "nxp,pcf8523";</div><div class='add'>+		reg = &lt;0x68&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sd_emmc_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmif_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmout_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmif_b {</div><div class='add'>+	pinctrl-0 = &lt;&amp;tdm_b_dout0_pins&gt;, &lt;&amp;tdm_b_fs_pins&gt;, &lt;&amp;tdm_b_sclk_pins&gt;, &lt;&amp;tdm_b_din1_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	assigned-clocks = &lt;&amp;clkc_audio AUD_CLKID_TDM_SCLK_PAD1&gt;,</div><div class='add'>+			  &lt;&amp;clkc_audio AUD_CLKID_TDM_LRCLK_PAD1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clkc_audio AUD_CLKID_MST_B_SCLK&gt;,</div><div class='add'>+				 &lt;&amp;clkc_audio AUD_CLKID_MST_B_LRCLK&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmin_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;toddr_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;toddr_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;toddr_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tohdmitx {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi<br/>new file mode 100644<br/>index 000000000000..39011b645128<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi</a></div><div class='hunk'>@@ -0,0 +1,378 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2023 Neil Armstrong &lt;neil.armstrong@linaro.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "meson-g12b-a311d.dtsi"</div><div class='add'>+#include &lt;dt-bindings/gpio/meson-g12a-gpio.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart_AO;</div><div class='add'>+		rtc1 = &amp;vrtc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	emmc_pwrseq: emmc-pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-emmc";</div><div class='add'>+		reset-gpios = &lt;&amp;gpio BOOT_12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x0 0x0 0x40000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdio_pwrseq: sdio-pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-simple";</div><div class='add'>+		reset-gpios = &lt;&amp;gpio GPIOAO_6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		clocks = &lt;&amp;wifi32k&gt;;</div><div class='add'>+		clock-names = "ext_clock";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	emmc_1v8: regulator-emmc-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "EMMC_1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dc_in: regulator-dc-in {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "DC_IN";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddio_c: regulator-vddio-c {</div><div class='add'>+		compatible = "regulator-gpio";</div><div class='add'>+		regulator-name = "VDDIO_C";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+</div><div class='add'>+		enable-gpios = &lt;&amp;gpio_ao GPIOAO_3 GPIO_OPEN_DRAIN&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+</div><div class='add'>+		gpios = &lt;&amp;gpio_ao GPIOAO_9 GPIO_OPEN_DRAIN&gt;;</div><div class='add'>+		gpios-states = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		states = &lt;1800000 0&gt;,</div><div class='add'>+			 &lt;3300000 1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddao_1v8: regulator-vddao-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDAO_1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddao_3v3: regulator-vddao-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDAO_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;dc_in&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddcpu_a: regulator-vddcpu-a {</div><div class='add'>+		/*</div><div class='add'>+		 * MP8756GD DC/DC Regulator.</div><div class='add'>+		 */</div><div class='add'>+		compatible = "pwm-regulator";</div><div class='add'>+</div><div class='add'>+		regulator-name = "VDDCPU_A";</div><div class='add'>+		regulator-min-microvolt = &lt;680000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1040000&gt;;</div><div class='add'>+</div><div class='add'>+		pwm-supply = &lt;&amp;dc_in&gt;;</div><div class='add'>+</div><div class='add'>+		pwms = &lt;&amp;pwm_ab 0 1250 0&gt;;</div><div class='add'>+		pwm-dutycycle-range = &lt;100 0&gt;;</div><div class='add'>+</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddcpu_b: regulator-vddcpu-b {</div><div class='add'>+		/*</div><div class='add'>+		 * SY8120B1ABC DC/DC Regulator.</div><div class='add'>+		 */</div><div class='add'>+		compatible = "pwm-regulator";</div><div class='add'>+</div><div class='add'>+		regulator-name = "VDDCPU_B";</div><div class='add'>+		regulator-min-microvolt = &lt;680000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1040000&gt;;</div><div class='add'>+</div><div class='add'>+		pwm-supply = &lt;&amp;dc_in&gt;;</div><div class='add'>+</div><div class='add'>+		pwms = &lt;&amp;pwm_AO_cd 1 1250 0&gt;;</div><div class='add'>+		pwm-dutycycle-range = &lt;100 0&gt;;</div><div class='add'>+</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wifi32k: wifi32k {</div><div class='add'>+		compatible = "pwm-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;32768&gt;;</div><div class='add'>+		pwms = &lt;&amp;pwm_ef 0 30518 0&gt;; /* PWM_E at 32.768KHz */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;arb {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;clkc_audio {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cec_AO {</div><div class='add'>+	pinctrl-0 = &lt;&amp;cec_ao_a_h_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	hdmi-phandle = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cecb_AO {</div><div class='add'>+	pinctrl-0 = &lt;&amp;cec_ao_b_h_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	hdmi-phandle = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu_b&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table_0&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPU_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu1 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu_b&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table_0&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPU_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu100 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu_a&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpub_opp_table_1&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPUB_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu101 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu_a&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpub_opp_table_1&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPUB_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu102 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu_a&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpub_opp_table_1&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPUB_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu103 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu_a&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpub_opp_table_1&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPUB_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ext_mdio {</div><div class='add'>+	external_phy: ethernet-phy@0 {</div><div class='add'>+		/* Realtek RTL8211F (0x001cc916) */</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		max-speed = &lt;1000&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio_intc&gt;;</div><div class='add'>+		/* MAC_INTR on GPIOZ_14 */</div><div class='add'>+		interrupts = &lt;IRQID_GPIOZ_14 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Ethernet to be enabled in baseboard DT */</div><div class='add'>+&amp;ethmac {</div><div class='add'>+	pinctrl-0 = &lt;&amp;eth_pins&gt;, &lt;&amp;eth_rgmii_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	phy-mode = "rgmii-txid";</div><div class='add'>+	phy-handle = &lt;&amp;external_phy&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* HDMI to be enabled in baseboard DT */</div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	pinctrl-0 = &lt;&amp;hdmitx_hpd_pins&gt;, &lt;&amp;hdmitx_ddc_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	hdmi-supply = &lt;&amp;dc_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* "Camera" I2C bus */</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c1_sda_h6_pins&gt;, &lt;&amp;i2c1_sck_h7_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Main I2C bus */</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c2_sda_x_pins&gt;, &lt;&amp;i2c2_sck_x_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* "ID" I2C bus */</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c3_sda_a_pins&gt;, &lt;&amp;i2c3_sck_a_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie {</div><div class='add'>+	reset-gpios = &lt;&amp;gpio GPIOA_8 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm_ab {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm_a_e_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm_ef {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm_e_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm_AO_cd {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm_ao_d_e_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;saradc {</div><div class='add'>+	vref-supply = &lt;&amp;vddao_1v8&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* on-module SDIO WiFi */</div><div class='add'>+&amp;sd_emmc_a {</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdio_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;sdio_clk_gate_pins&gt;;</div><div class='add'>+	pinctrl-names = "default", "clk-gate";</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	sd-uhs-sdr104;</div><div class='add'>+	max-frequency = &lt;50000000&gt;;</div><div class='add'>+</div><div class='add'>+	non-removable;</div><div class='add'>+	disable-wp;</div><div class='add'>+</div><div class='add'>+	/* WiFi firmware requires power in suspend */</div><div class='add'>+	keep-power-in-suspend;</div><div class='add'>+</div><div class='add'>+	mmc-pwrseq = &lt;&amp;sdio_pwrseq&gt;;</div><div class='add'>+</div><div class='add'>+	vmmc-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	rtl8822cs: wifi@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SD card to be enabled in baseboard DT */</div><div class='add'>+&amp;sd_emmc_b {</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdcard_c_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;sdcard_clk_gate_c_pins&gt;;</div><div class='add'>+	pinctrl-names = "default", "clk-gate";</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	max-frequency = &lt;50000000&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+</div><div class='add'>+	cd-gpios = &lt;&amp;gpio GPIOC_6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;vddio_c&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* on-module eMMC */</div><div class='add'>+&amp;sd_emmc_c {</div><div class='add'>+	pinctrl-0 = &lt;&amp;emmc_ctrl_pins&gt;, &lt;&amp;emmc_data_8b_pins&gt;, &lt;&amp;emmc_ds_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;emmc_clk_gate_pins&gt;;</div><div class='add'>+	pinctrl-names = "default", "clk-gate";</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	cap-mmc-highspeed;</div><div class='add'>+	mmc-ddr-1_8v;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+</div><div class='add'>+	mmc-pwrseq = &lt;&amp;emmc_pwrseq&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;vddao_1v8&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmif_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmout_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* on-module UART BT */</div><div class='add'>+&amp;uart_A {</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart_a_pins&gt;, &lt;&amp;uart_a_cts_rts_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "realtek,rtl8822cs-bt";</div><div class='add'>+		enable-gpios = &lt;&amp;gpio GPIOX_17 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		host-wake-gpios = &lt;&amp;gpio GPIOX_19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		device-wake-gpios = &lt;&amp;gpio GPIOX_18 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart_AO {</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart_ao_a_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb {</div><div class='add'>+	phys = &lt;&amp;usb2_phy0&gt;, &lt;&amp;usb2_phy1&gt;;</div><div class='add'>+	phy-names = "usb2-phy0", "usb2-phy1";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi<br/>new file mode 100644<br/>index 000000000000..1b08303c4282<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi</a></div><div class='hunk'>@@ -0,0 +1,499 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2019 BayLibre, SAS</div><div class='add'>+ * Author: Neil Armstrong &lt;narmstrong@baylibre.com&gt;</div><div class='add'>+ * Copyright (c) 2023 Christian Hewitt &lt;christianshewitt@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/meson-g12a-gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/meson-g12a-tohdmitx.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart_AO;</div><div class='add'>+		ethernet0 = &amp;ethmac;</div><div class='add'>+		rtc1 = &amp;vrtc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x0 0x0 0x80000000&gt;; /* 2 GiB or 4 GiB */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	adc-keys {</div><div class='add'>+		compatible = "adc-keys";</div><div class='add'>+		io-channels = &lt;&amp;saradc 2&gt;;</div><div class='add'>+		io-channel-names = "buttons";</div><div class='add'>+		keyup-threshold-microvolt = &lt;1710000&gt;;</div><div class='add'>+</div><div class='add'>+		button-function {</div><div class='add'>+			label = "RST";</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+			press-threshold-microvolt = &lt;10000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	emmc_pwrseq: emmc-pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-emmc";</div><div class='add'>+		reset-gpios = &lt;&amp;gpio BOOT_12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdmi-connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		type = "a";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			hdmi_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_tx_tmds_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			gpios = &lt;&amp;gpio_ao GPIOAO_7 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			gpios = &lt;&amp;gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdio_pwrseq: sdio-pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-simple";</div><div class='add'>+		reset-gpios = &lt;&amp;gpio GPIOX_6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		clocks = &lt;&amp;wifi32k&gt;;</div><div class='add'>+		clock-names = "ext_clock";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wifi32k: wifi32k {</div><div class='add'>+		compatible = "pwm-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;32768&gt;;</div><div class='add'>+		pwms = &lt;&amp;pwm_ef 0 30518 0&gt;; /* PWM_E at 32.768KHz */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dc_in: regulator-dc-in {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "DC_IN";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vcc_5v: regulator-vcc-5v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCC_5V";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;dc_in&gt;;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;gpio GPIOH_8 GPIO_OPEN_DRAIN&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vcc_3v3: regulator-vcc-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCC_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vsys_3v3&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vcc_1v8: regulator-vcc-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCC_1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vcc_3v3&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddao_1v8: regulator-vddao-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDIO_AO1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vsys_3v3&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddcpu_a: regulator-vddcpu-a {</div><div class='add'>+		compatible = "pwm-regulator";</div><div class='add'>+		regulator-name = "VDDCPU_A";</div><div class='add'>+		regulator-min-microvolt = &lt;690000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1050000&gt;;</div><div class='add'>+		pwm-supply = &lt;&amp;dc_in&gt;;</div><div class='add'>+		pwms = &lt;&amp;pwm_ab 0 1250 0&gt;;</div><div class='add'>+		pwm-dutycycle-range = &lt;100 0&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddcpu_b: regulator-vddcpu-b {</div><div class='add'>+		compatible = "pwm-regulator";</div><div class='add'>+		regulator-name = "VDDCPU_B";</div><div class='add'>+		regulator-min-microvolt = &lt;690000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1050000&gt;;</div><div class='add'>+		pwm-supply = &lt;&amp;vsys_3v3&gt;;</div><div class='add'>+		pwms = &lt;&amp;pwm_AO_cd 1 1250 0&gt;;</div><div class='add'>+		pwm-dutycycle-range = &lt;100 0&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vsys_3v3: regulator-vsys-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VSYS_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;dc_in&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	emmc_1v8: regulator-emmc-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "EMMC_AO1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vcc_3v3&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb_pwr: regulator-usb-pwr {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "USB_PWR";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vcc_5v&gt;;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;gpio GPIOA_6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "amlogic,axg-sound-card";</div><div class='add'>+		model = "BPI-M2S";</div><div class='add'>+		audio-aux-devs = &lt;&amp;tdmout_b&gt;;</div><div class='add'>+		audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",</div><div class='add'>+				"TDMOUT_B IN 1", "FRDDR_B OUT 1",</div><div class='add'>+				"TDMOUT_B IN 2", "FRDDR_C OUT 1",</div><div class='add'>+				"TDM_B Playback", "TDMOUT_B OUT";</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;294912000&gt;,</div><div class='add'>+				       &lt;270950400&gt;,</div><div class='add'>+				       &lt;393216000&gt;;</div><div class='add'>+</div><div class='add'>+		dai-link-0 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_a&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-1 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_b&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-2 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_c&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* 8ch hdmi interface */</div><div class='add'>+		dai-link-3 {</div><div class='add'>+			sound-dai = &lt;&amp;tdmif_b&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			dai-tdm-slot-tx-mask-0 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-1 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-2 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-3 = &lt;1 1&gt;;</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_IN_B&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* hdmi glue */</div><div class='add'>+		dai-link-4 {</div><div class='add'>+			sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;arb {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;clkc_audio {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cecb_AO {</div><div class='add'>+	pinctrl-0 = &lt;&amp;cec_ao_b_h_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+	hdmi-phandle = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu_b&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table_0&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPU_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu1 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu_b&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table_0&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPU_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu100 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu_a&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpub_opp_table_1&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPUB_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu101 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu_a&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpub_opp_table_1&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPUB_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu102 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu_a&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpub_opp_table_1&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPUB_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu103 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu_a&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpub_opp_table_1&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPUB_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethmac {</div><div class='add'>+	pinctrl-0 = &lt;&amp;eth_pins&gt;, &lt;&amp;eth_rgmii_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+	phy-mode = "rgmii";</div><div class='add'>+	phy-handle = &lt;&amp;external_phy&gt;;</div><div class='add'>+	amlogic,tx-delay-ns = &lt;2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ext_mdio {</div><div class='add'>+	external_phy: ethernet-phy@0 {</div><div class='add'>+		/* Realtek RTL8211F (0x001cc916) */</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		max-speed = &lt;1000&gt;;</div><div class='add'>+</div><div class='add'>+		reset-assert-us = &lt;10000&gt;;</div><div class='add'>+		reset-deassert-us = &lt;80000&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio_intc&gt;;</div><div class='add'>+		/* MAC_INTR on GPIOZ_14 */</div><div class='add'>+		interrupts = &lt;IRQID_GPIOZ_14 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;hdmitx_hpd_pins&gt;, &lt;&amp;hdmitx_ddc_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	hdmi-supply = &lt;&amp;vcc_5v&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx_tmds_port {</div><div class='add'>+	hdmi_tx_tmds_out: endpoint {</div><div class='add'>+		remote-endpoint = &lt;&amp;hdmi_connector_in&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Main i2c bus */</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c2_sda_x_pins&gt;, &lt;&amp;i2c2_sck_x_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie {</div><div class='add'>+	status = "okay";</div><div class='add'>+	reset-gpios = &lt;&amp;gpio GPIOA_8 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm_ab {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm_a_e_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm_ef {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm_e_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm_AO_cd {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm_ao_d_e_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;saradc {</div><div class='add'>+	status = "okay";</div><div class='add'>+	vref-supply = &lt;&amp;vddao_1v8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SDIO */</div><div class='add'>+&amp;sd_emmc_a {</div><div class='add'>+	/* enable if WiFi/BT board connected */</div><div class='add'>+	status = "disabled";</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdio_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;sdio_clk_gate_pins&gt;;</div><div class='add'>+	pinctrl-names = "default", "clk-gate";</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	sd-uhs-sdr104;</div><div class='add'>+	max-frequency = &lt;50000000&gt;;</div><div class='add'>+</div><div class='add'>+	non-removable;</div><div class='add'>+	disable-wp;</div><div class='add'>+</div><div class='add'>+	/* WiFi firmware requires power in suspend */</div><div class='add'>+	keep-power-in-suspend;</div><div class='add'>+</div><div class='add'>+	mmc-pwrseq = &lt;&amp;sdio_pwrseq&gt;;</div><div class='add'>+</div><div class='add'>+	vmmc-supply = &lt;&amp;vsys_3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;vddao_1v8&gt;;</div><div class='add'>+</div><div class='add'>+	rtl8822cs: wifi@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SD card */</div><div class='add'>+&amp;sd_emmc_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdcard_c_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;sdcard_clk_gate_c_pins&gt;;</div><div class='add'>+	pinctrl-names = "default", "clk-gate";</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	max-frequency = &lt;50000000&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+</div><div class='add'>+	cd-gpios = &lt;&amp;gpio GPIOC_6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;vsys_3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;vsys_3v3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* eMMC */</div><div class='add'>+&amp;sd_emmc_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;emmc_ctrl_pins&gt;, &lt;&amp;emmc_data_8b_pins&gt;, &lt;&amp;emmc_ds_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;emmc_clk_gate_pins&gt;;</div><div class='add'>+	pinctrl-names = "default", "clk-gate";</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	cap-mmc-highspeed;</div><div class='add'>+	mmc-ddr-1_8v;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+</div><div class='add'>+	mmc-pwrseq = &lt;&amp;emmc_pwrseq&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;vcc_3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;emmc_1v8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmif_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmout_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tohdmitx {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart_A {</div><div class='add'>+	/* enable if WiFi/BT board connected */</div><div class='add'>+	status = "disabled";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart_a_pins&gt;, &lt;&amp;uart_a_cts_rts_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "realtek,rtl8822cs-bt";</div><div class='add'>+		enable-gpios = &lt;&amp;gpio GPIOX_17 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		host-wake-gpios = &lt;&amp;gpio GPIOX_19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		device-wake-gpios = &lt;&amp;gpio GPIOX_18 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart_AO {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart_ao_a_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb2_phy0 {</div><div class='add'>+	phy-supply = &lt;&amp;dc_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb2_phy1 {</div><div class='add'>+	phy-supply = &lt;&amp;usb_pwr&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_pcie_phy {</div><div class='add'>+	phy-supply = &lt;&amp;usb_pwr&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb {</div><div class='add'>+	status = "okay";</div><div class='add'>+	dr_mode = "peripheral";</div><div class='add'>+	phys = &lt;&amp;usb2_phy0&gt;, &lt;&amp;usb2_phy1&gt;;</div><div class='add'>+	phy-names = "usb2-phy0", "usb2-phy1";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-dreambox-one.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-dreambox-one.dts<br/>new file mode 100644<br/>index 000000000000..ecfa1c683dde<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12b-dreambox-one.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-g12b-dreambox-one.dts</a></div><div class='hunk'>@@ -0,0 +1,17 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2019 Christian Hewitt &lt;christianshewitt@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "meson-g12b-dreambox.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "dream,dreambox-one", "amlogic,s922x", "amlogic,g12b";</div><div class='add'>+	model = "Dreambox One";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sd_emmc_a {</div><div class='add'>+	sd-uhs-sdr12;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-dreambox-two.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-dreambox-two.dts<br/>new file mode 100644<br/>index 000000000000..df0d71983c3d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12b-dreambox-two.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-g12b-dreambox-two.dts</a></div><div class='hunk'>@@ -0,0 +1,20 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2019 Christian Hewitt &lt;christianshewitt@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "meson-g12b-dreambox.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "dream,dreambox-two", "amlogic,s922x", "amlogic,g12b";</div><div class='add'>+	model = "Dreambox Two";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sd_emmc_a {</div><div class='add'>+	sd-uhs-sdr12;</div><div class='add'>+	sd-uhs-sdr25;</div><div class='add'>+	sd-uhs-sdr50;</div><div class='add'>+	sd-uhs-sdr104;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-dreambox.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-dreambox.dtsi<br/>new file mode 100644<br/>index 000000000000..8e3e3354ed67<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12b-dreambox.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-g12b-dreambox.dtsi</a></div><div class='hunk'>@@ -0,0 +1,164 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2021 Christian Hewitt &lt;christianshewitt@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "meson-g12b-w400.dtsi"</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/meson-g12a-tohdmitx.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	cvbs-connector {</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdio_pwrseq: sdio-pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-simple";</div><div class='add'>+		reset-gpios = &lt;&amp;gpio GPIOA_11 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		clocks = &lt;&amp;wifi32k&gt;;</div><div class='add'>+		clock-names = "ext_clock";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spdif_dit: audio-codec-1 {</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		compatible = "linux,spdif-dit";</div><div class='add'>+		status = "okay";</div><div class='add'>+		sound-name-prefix = "DIT";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "amlogic,axg-sound-card";</div><div class='add'>+		model = "DREAMBOX";</div><div class='add'>+		audio-aux-devs = &lt;&amp;tdmout_b&gt;;</div><div class='add'>+		audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",</div><div class='add'>+				"TDMOUT_B IN 1", "FRDDR_B OUT 1",</div><div class='add'>+				"TDMOUT_B IN 2", "FRDDR_C OUT 1",</div><div class='add'>+				"TDM_B Playback", "TDMOUT_B OUT",</div><div class='add'>+				"SPDIFOUT_A IN 0", "FRDDR_A OUT 3",</div><div class='add'>+				"SPDIFOUT_A IN 1", "FRDDR_B OUT 3",</div><div class='add'>+				"SPDIFOUT_A IN 2", "FRDDR_C OUT 3";</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;294912000&gt;,</div><div class='add'>+				       &lt;270950400&gt;,</div><div class='add'>+				       &lt;393216000&gt;;</div><div class='add'>+</div><div class='add'>+		dai-link-0 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_a&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-1 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_b&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-2 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_c&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* 8ch hdmi interface */</div><div class='add'>+		dai-link-3 {</div><div class='add'>+			sound-dai = &lt;&amp;tdmif_b&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			dai-tdm-slot-tx-mask-0 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-1 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-2 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-3 = &lt;1 1&gt;;</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_IN_B&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* spdif hdmi or toslink interface */</div><div class='add'>+		dai-link-4 {</div><div class='add'>+			sound-dai = &lt;&amp;spdifout_a&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;spdif_dit&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			codec-1 {</div><div class='add'>+				sound-dai = &lt;&amp;tohdmitx TOHDMITX_SPDIF_IN_A&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* spdif hdmi interface */</div><div class='add'>+		dai-link-5 {</div><div class='add'>+			sound-dai = &lt;&amp;spdifout_b&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;tohdmitx TOHDMITX_SPDIF_IN_B&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* hdmi glue */</div><div class='add'>+		dai-link-6 {</div><div class='add'>+			sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;arb {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;clkc_audio {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ir {</div><div class='add'>+	linux,rc-map-name = "rc-dreambox";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;saradc {</div><div class='add'>+	status = "okay";</div><div class='add'>+	vref-supply = &lt;&amp;vddao_1v8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spdifout_a {</div><div class='add'>+	pinctrl-0 = &lt;&amp;spdif_out_h_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spdifout_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmif_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmout_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tohdmitx {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-gsking-x.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-gsking-x.dts<br/>new file mode 100644<br/>index 000000000000..369c5cf889b6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12b-gsking-x.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-g12b-gsking-x.dts</a></div><div class='hunk'>@@ -0,0 +1,159 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2019 BayLibre, SAS</div><div class='add'>+ * Author: Neil Armstrong &lt;narmstrong@baylibre.com&gt;</div><div class='add'>+ * Copyright (c) 2019 Christian Hewitt &lt;christianshewitt@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "meson-g12b-w400.dtsi"</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/meson-g12a-tohdmitx.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "azw,gsking-x", "amlogic,s922x", "amlogic,g12b";</div><div class='add'>+	model = "Beelink GS-King X";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		rtc0 = &amp;rtc;</div><div class='add'>+		rtc1 = &amp;vrtc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio_fan: gpio-fan {</div><div class='add'>+		compatible = "gpio-fan";</div><div class='add'>+		gpios = &lt;&amp;gpio GPIOH_5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		/* Using Dummy Speed */</div><div class='add'>+		gpio-fan,speed-map = &lt;0 0&gt;, &lt;1 1&gt;;</div><div class='add'>+		#cooling-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys-polled {</div><div class='add'>+		compatible = "gpio-keys-polled";</div><div class='add'>+		poll-interval = &lt;100&gt;;</div><div class='add'>+</div><div class='add'>+		power-button {</div><div class='add'>+			label = "power";</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "amlogic,axg-sound-card";</div><div class='add'>+		model = "GSKING-X";</div><div class='add'>+		audio-aux-devs = &lt;&amp;tdmout_a&gt;;</div><div class='add'>+		audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 1",</div><div class='add'>+				"TDMOUT_A IN 1", "FRDDR_B OUT 1",</div><div class='add'>+				"TDMOUT_A IN 2", "FRDDR_C OUT 1",</div><div class='add'>+				"TDM_A Playback", "TDMOUT_A OUT";</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;294912000&gt;,</div><div class='add'>+				       &lt;270950400&gt;,</div><div class='add'>+				       &lt;393216000&gt;;</div><div class='add'>+</div><div class='add'>+		dai-link-0 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_a&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-1 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_b&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-2 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_c&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* 8ch hdmi interface */</div><div class='add'>+		dai-link-3 {</div><div class='add'>+			sound-dai = &lt;&amp;tdmif_a&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			dai-tdm-slot-tx-mask-0 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-1 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-2 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-3 = &lt;1 1&gt;;</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_IN_A&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-4 {</div><div class='add'>+			sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;arb {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;clkc_audio {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu_thermal {</div><div class='add'>+	trips {</div><div class='add'>+		cpu_active: cpu-active {</div><div class='add'>+			temperature = &lt;70000&gt;; /* millicelsius */</div><div class='add'>+			hysteresis = &lt;2000&gt;; /* millicelsius */</div><div class='add'>+			type = "active";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cooling-maps {</div><div class='add'>+		map {</div><div class='add'>+			trip = &lt;&amp;cpu_active&gt;;</div><div class='add'>+			cooling-device = &lt;&amp;gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c3_sda_a_pins&gt;, &lt;&amp;i2c3_sck_a_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	rtc: rtc@51 {</div><div class='add'>+		compatible = "nxp,pcf8563";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		wakeup-source;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmif_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmout_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tohdmitx {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-gtking-pro.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-gtking-pro.dts<br/>new file mode 100644<br/>index 000000000000..654449afd3a4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12b-gtking-pro.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-g12b-gtking-pro.dts</a></div><div class='hunk'>@@ -0,0 +1,143 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2019 BayLibre, SAS</div><div class='add'>+ * Author: Neil Armstrong &lt;narmstrong@baylibre.com&gt;</div><div class='add'>+ * Copyright (c) 2019 Christian Hewitt &lt;christianshewitt@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "meson-g12b-w400.dtsi"</div><div class='add'>+#include &lt;dt-bindings/sound/meson-g12a-tohdmitx.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "azw,gtking", "amlogic,s922x", "amlogic,g12b";</div><div class='add'>+	model = "Beelink GT-King Pro";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		rtc0 = &amp;rtc;</div><div class='add'>+		rtc1 = &amp;vrtc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys-polled {</div><div class='add'>+		compatible = "gpio-keys-polled";</div><div class='add'>+		poll-interval = &lt;100&gt;;</div><div class='add'>+</div><div class='add'>+		power-button {</div><div class='add'>+			label = "power";</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-white {</div><div class='add'>+			label = "power:white";</div><div class='add'>+			gpios = &lt;&amp;gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "on";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "amlogic,axg-sound-card";</div><div class='add'>+		model = "GTKING-PRO";</div><div class='add'>+		audio-aux-devs = &lt;&amp;tdmout_b&gt;;</div><div class='add'>+		audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",</div><div class='add'>+				"TDMOUT_B IN 1", "FRDDR_B OUT 1",</div><div class='add'>+				"TDMOUT_B IN 2", "FRDDR_C OUT 1",</div><div class='add'>+				"TDM_B Playback", "TDMOUT_B OUT";</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;294912000&gt;,</div><div class='add'>+				       &lt;270950400&gt;,</div><div class='add'>+				       &lt;393216000&gt;;</div><div class='add'>+</div><div class='add'>+		dai-link-0 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_a&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-1 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_b&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-2 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_c&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* 8ch hdmi interface */</div><div class='add'>+		dai-link-3 {</div><div class='add'>+			sound-dai = &lt;&amp;tdmif_b&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			dai-tdm-slot-tx-mask-0 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-1 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-2 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-3 = &lt;1 1&gt;;</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_IN_B&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-4 {</div><div class='add'>+			sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;arb {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;clkc_audio {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c3_sda_a_pins&gt;, &lt;&amp;i2c3_sck_a_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	rtc: rtc@51 {</div><div class='add'>+		compatible = "nxp,pcf8563";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		wakeup-source;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmif_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmout_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tohdmitx {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-gtking.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-gtking.dts<br/>new file mode 100644<br/>index 000000000000..e20311386745<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12b-gtking.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-g12b-gtking.dts</a></div><div class='hunk'>@@ -0,0 +1,165 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2019 BayLibre, SAS</div><div class='add'>+ * Author: Neil Armstrong &lt;narmstrong@baylibre.com&gt;</div><div class='add'>+ * Copyright (c) 2019 Christian Hewitt &lt;christianshewitt@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "meson-g12b-w400.dtsi"</div><div class='add'>+#include &lt;dt-bindings/sound/meson-g12a-tohdmitx.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "azw,gtking", "amlogic,s922x", "amlogic,g12b";</div><div class='add'>+	model = "Beelink GT-King";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		rtc0 = &amp;rtc;</div><div class='add'>+		rtc1 = &amp;vrtc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spdif_dit: audio-codec-1 {</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		compatible = "linux,spdif-dit";</div><div class='add'>+		sound-name-prefix = "DIT";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "amlogic,axg-sound-card";</div><div class='add'>+		model = "GTKING";</div><div class='add'>+		audio-aux-devs = &lt;&amp;tdmout_b&gt;;</div><div class='add'>+		audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",</div><div class='add'>+				"TDMOUT_B IN 1", "FRDDR_B OUT 1",</div><div class='add'>+				"TDMOUT_B IN 2", "FRDDR_C OUT 1",</div><div class='add'>+				"TDM_B Playback", "TDMOUT_B OUT",</div><div class='add'>+				"SPDIFOUT_A IN 0", "FRDDR_A OUT 3",</div><div class='add'>+				"SPDIFOUT_A IN 1", "FRDDR_B OUT 3",</div><div class='add'>+				"SPDIFOUT_A IN 2", "FRDDR_C OUT 3";</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;294912000&gt;,</div><div class='add'>+				       &lt;270950400&gt;,</div><div class='add'>+				       &lt;393216000&gt;;</div><div class='add'>+</div><div class='add'>+		dai-link-0 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_a&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-1 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_b&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-2 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_c&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* 8ch hdmi interface */</div><div class='add'>+		dai-link-3 {</div><div class='add'>+			sound-dai = &lt;&amp;tdmif_b&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			dai-tdm-slot-tx-mask-0 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-1 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-2 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-3 = &lt;1 1&gt;;</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_IN_B&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* spdif hdmi or toslink interface */</div><div class='add'>+		dai-link-4 {</div><div class='add'>+			sound-dai = &lt;&amp;spdifout_a&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;spdif_dit&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			codec-1 {</div><div class='add'>+				sound-dai = &lt;&amp;tohdmitx TOHDMITX_SPDIF_IN_A&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* spdif hdmi interface */</div><div class='add'>+		dai-link-5 {</div><div class='add'>+			sound-dai = &lt;&amp;spdifout_b&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;tohdmitx TOHDMITX_SPDIF_IN_B&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* hdmi glue */</div><div class='add'>+		dai-link-6 {</div><div class='add'>+			sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;arb {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;clkc_audio {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c3_sda_a_pins&gt;, &lt;&amp;i2c3_sck_a_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	rtc: rtc@51 {</div><div class='add'>+		compatible = "nxp,pcf8563";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		wakeup-source;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spdifout_a {</div><div class='add'>+	pinctrl-0 = &lt;&amp;spdif_out_h_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spdifout_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmif_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmout_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tohdmitx {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi<br/>index c33e85fbdaba..fc737499f207 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi</a></div><div class='hunk'>@@ -5,8 +5,6 @@</div><div class='ctx'>  * Copyright (c) 2019 Christian Hewitt &lt;christianshewitt@gmail.com&gt;</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-#include &lt;dt-bindings/sound/meson-g12a-tohdmitx.h&gt;</div><div class='del'>-</div><div class='ctx'> / {</div><div class='ctx'> 	model = "Khadas VIM3";</div><div class='ctx'> </div><div class='hunk'>@@ -20,7 +18,7 @@</div><div class='ctx'> 		regulator-min-microvolt = &lt;690000&gt;;</div><div class='ctx'> 		regulator-max-microvolt = &lt;1050000&gt;;</div><div class='ctx'> </div><div class='del'>-		vin-supply = &lt;&amp;dc_in&gt;;</div><div class='add'>+		pwm-supply = &lt;&amp;dc_in&gt;;</div><div class='ctx'> </div><div class='ctx'> 		pwms = &lt;&amp;pwm_ab 0 1250 0&gt;;</div><div class='ctx'> 		pwm-dutycycle-range = &lt;100 0&gt;;</div><div class='hunk'>@@ -39,7 +37,7 @@</div><div class='ctx'> 		regulator-min-microvolt = &lt;690000&gt;;</div><div class='ctx'> 		regulator-max-microvolt = &lt;1050000&gt;;</div><div class='ctx'> </div><div class='del'>-		vin-supply = &lt;&amp;vsys_3v3&gt;;</div><div class='add'>+		pwm-supply = &lt;&amp;vsys_3v3&gt;;</div><div class='ctx'> </div><div class='ctx'> 		pwms = &lt;&amp;pwm_AO_cd 1 1250 0&gt;;</div><div class='ctx'> 		pwm-dutycycle-range = &lt;100 0&gt;;</div><div class='hunk'>@@ -47,145 +45,53 @@</div><div class='ctx'> 		regulator-boot-on;</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='del'>-</div><div class='del'>-	sound {</div><div class='del'>-		compatible = "amlogic,axg-sound-card";</div><div class='del'>-		model = "G12B-KHADAS-VIM3";</div><div class='del'>-		audio-aux-devs = &lt;&amp;tdmout_b&gt;;</div><div class='del'>-		audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",</div><div class='del'>-				"TDMOUT_B IN 1", "FRDDR_B OUT 1",</div><div class='del'>-				"TDMOUT_B IN 2", "FRDDR_C OUT 1",</div><div class='del'>-				"TDM_B Playback", "TDMOUT_B OUT";</div><div class='del'>-</div><div class='del'>-		assigned-clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='del'>-				  &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='del'>-				  &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='del'>-		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='del'>-		assigned-clock-rates = &lt;294912000&gt;,</div><div class='del'>-				       &lt;270950400&gt;,</div><div class='del'>-				       &lt;393216000&gt;;</div><div class='del'>-		status = "okay";</div><div class='del'>-</div><div class='del'>-		dai-link-0 {</div><div class='del'>-			sound-dai = &lt;&amp;frddr_a&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		dai-link-1 {</div><div class='del'>-			sound-dai = &lt;&amp;frddr_b&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		dai-link-2 {</div><div class='del'>-			sound-dai = &lt;&amp;frddr_c&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		/* 8ch hdmi interface */</div><div class='del'>-		dai-link-3 {</div><div class='del'>-			sound-dai = &lt;&amp;tdmif_b&gt;;</div><div class='del'>-			dai-format = "i2s";</div><div class='del'>-			dai-tdm-slot-tx-mask-0 = &lt;1 1&gt;;</div><div class='del'>-			dai-tdm-slot-tx-mask-1 = &lt;1 1&gt;;</div><div class='del'>-			dai-tdm-slot-tx-mask-2 = &lt;1 1&gt;;</div><div class='del'>-			dai-tdm-slot-tx-mask-3 = &lt;1 1&gt;;</div><div class='del'>-			mclk-fs = &lt;256&gt;;</div><div class='del'>-</div><div class='del'>-			codec {</div><div class='del'>-				sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_IN_B&gt;;</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		/* hdmi glue */</div><div class='del'>-		dai-link-4 {</div><div class='del'>-			sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_OUT&gt;;</div><div class='del'>-</div><div class='del'>-			codec {</div><div class='del'>-				sound-dai = &lt;&amp;hdmi_tx&gt;;</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;arb {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;clkc_audio {</div><div class='del'>-	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cpu0 {</div><div class='ctx'> 	cpu-supply = &lt;&amp;vddcpu_b&gt;;</div><div class='ctx'> 	operating-points-v2 = &lt;&amp;cpu_opp_table_0&gt;;</div><div class='ctx'> 	clocks = &lt;&amp;clkc CLKID_CPU_CLK&gt;;</div><div class='del'>-	clock-latency = &lt;50000&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cpu1 {</div><div class='ctx'> 	cpu-supply = &lt;&amp;vddcpu_b&gt;;</div><div class='ctx'> 	operating-points-v2 = &lt;&amp;cpu_opp_table_0&gt;;</div><div class='ctx'> 	clocks = &lt;&amp;clkc CLKID_CPU_CLK&gt;;</div><div class='del'>-	clock-latency = &lt;50000&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cpu100 {</div><div class='ctx'> 	cpu-supply = &lt;&amp;vddcpu_a&gt;;</div><div class='ctx'> 	operating-points-v2 = &lt;&amp;cpub_opp_table_1&gt;;</div><div class='ctx'> 	clocks = &lt;&amp;clkc CLKID_CPUB_CLK&gt;;</div><div class='del'>-	clock-latency = &lt;50000&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cpu101 {</div><div class='ctx'> 	cpu-supply = &lt;&amp;vddcpu_a&gt;;</div><div class='ctx'> 	operating-points-v2 = &lt;&amp;cpub_opp_table_1&gt;;</div><div class='ctx'> 	clocks = &lt;&amp;clkc CLKID_CPUB_CLK&gt;;</div><div class='del'>-	clock-latency = &lt;50000&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cpu102 {</div><div class='ctx'> 	cpu-supply = &lt;&amp;vddcpu_a&gt;;</div><div class='ctx'> 	operating-points-v2 = &lt;&amp;cpub_opp_table_1&gt;;</div><div class='ctx'> 	clocks = &lt;&amp;clkc CLKID_CPUB_CLK&gt;;</div><div class='del'>-	clock-latency = &lt;50000&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cpu103 {</div><div class='ctx'> 	cpu-supply = &lt;&amp;vddcpu_a&gt;;</div><div class='ctx'> 	operating-points-v2 = &lt;&amp;cpub_opp_table_1&gt;;</div><div class='ctx'> 	clocks = &lt;&amp;clkc CLKID_CPUB_CLK&gt;;</div><div class='del'>-	clock-latency = &lt;50000&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;frddr_b {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;frddr_c {</div><div class='del'>-	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;pwm_ab {</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pwm_a_e_pins&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='del'>-	clocks = &lt;&amp;xtal&gt;;</div><div class='del'>-	clock-names = "clkin0";</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;pwm_AO_cd {</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pwm_ao_d_e_pins&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='del'>-	clocks = &lt;&amp;xtal&gt;;</div><div class='del'>-	clock-names = "clkin1";</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;tdmif_b {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;tdmout_b {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;tohdmitx {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts<br/>new file mode 100644<br/>index 000000000000..d5938a4a6da3<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts</a></div><div class='hunk'>@@ -0,0 +1,720 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2022 Neil Armstrong &lt;neil.armstrong@linaro.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "meson-g12b-s922x.dtsi"</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/meson-g12a-gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/meson-g12a-toacodec.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/meson-g12a-tohdmitx.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "hardkernel,odroid-go-ultra", "amlogic,s922x", "amlogic,g12b";</div><div class='add'>+	model = "Hardkernel ODROID-GO-Ultra";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart_AO;</div><div class='add'>+		rtc0 = &amp;vrtc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	adc-joystick-left {</div><div class='add'>+		compatible = "adc-joystick";</div><div class='add'>+		io-channels = &lt;&amp;saradc 2&gt;, &lt;&amp;saradc 3&gt;;</div><div class='add'>+		poll-interval = &lt;10&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		axis@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			linux,code = &lt;ABS_Y&gt;;</div><div class='add'>+			abs-range = &lt;3150 950&gt;;</div><div class='add'>+			abs-fuzz = &lt;32&gt;;</div><div class='add'>+			abs-flat = &lt;64&gt;;</div><div class='add'>+		};</div><div class='add'>+		axis@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			linux,code = &lt;ABS_X&gt;;</div><div class='add'>+			abs-range = &lt;700 2900&gt;;</div><div class='add'>+			abs-fuzz = &lt;32&gt;;</div><div class='add'>+			abs-flat = &lt;64&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	adc-joystick-right {</div><div class='add'>+		compatible = "adc-joystick";</div><div class='add'>+		io-channels = &lt;&amp;saradc 0&gt;, &lt;&amp;saradc 1&gt;;</div><div class='add'>+		poll-interval = &lt;10&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		axis@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			linux,code = &lt;ABS_RY&gt;;</div><div class='add'>+			abs-range = &lt;3150 950&gt;;</div><div class='add'>+			abs-fuzz = &lt;32&gt;;</div><div class='add'>+			abs-flat = &lt;64&gt;;</div><div class='add'>+		};</div><div class='add'>+		axis@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			linux,code = &lt;ABS_RX&gt;;</div><div class='add'>+			abs-range = &lt;800 3000&gt;;</div><div class='add'>+			abs-fuzz = &lt;32&gt;;</div><div class='add'>+			abs-flat = &lt;64&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	codec_clk: codec-clk {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		clock-frequency = &lt;12288000&gt;;</div><div class='add'>+		clock-output-names = "codec_clk";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys-polled";</div><div class='add'>+		poll-interval = &lt;10&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;keypad_gpio_pins&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		volume-up-button {</div><div class='add'>+			label = "VOLUME-UP";</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio GPIOX_8 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+		volume-down-button {</div><div class='add'>+			label = "VOLUME-DOWN";</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio GPIOX_9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+		dpad-up-button {</div><div class='add'>+			label = "DPAD-UP";</div><div class='add'>+			linux,code = &lt;BTN_DPAD_UP&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio GPIOX_0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+		dpad-down-button {</div><div class='add'>+			label = "DPAD-DOWN";</div><div class='add'>+			linux,code = &lt;BTN_DPAD_DOWN&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio GPIOX_1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+		dpad-left-button {</div><div class='add'>+			label = "DPAD-LEFT";</div><div class='add'>+			linux,code = &lt;BTN_DPAD_LEFT&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio GPIOX_2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+		dpad-right-button {</div><div class='add'>+			label = "DPAD-RIGHT";</div><div class='add'>+			linux,code = &lt;BTN_DPAD_RIGHT&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio GPIOX_3 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+		a-button {</div><div class='add'>+			label = "A";</div><div class='add'>+			linux,code = &lt;BTN_EAST&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio GPIOX_4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+		b-button {</div><div class='add'>+			label = "B";</div><div class='add'>+			linux,code = &lt;BTN_SOUTH&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio GPIOX_5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+		y-button {</div><div class='add'>+			label = "Y";</div><div class='add'>+			linux,code = &lt;BTN_WEST&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio GPIOX_6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+		x-button {</div><div class='add'>+			label = "X";</div><div class='add'>+			linux,code = &lt;BTN_NORTH&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio GPIOX_7 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+		f1-button {</div><div class='add'>+			label = "F1";</div><div class='add'>+			linux,code = &lt;BTN_TRIGGER_HAPPY1&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio GPIOX_17 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+		f2-button {</div><div class='add'>+			label = "F2";</div><div class='add'>+			linux,code = &lt;BTN_TRIGGER_HAPPY2&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio GPIOX_10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+		f3-button {</div><div class='add'>+			label = "F3";</div><div class='add'>+			linux,code = &lt;BTN_TRIGGER_HAPPY3&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio GPIOX_11 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+		f4-button {</div><div class='add'>+			label = "F4";</div><div class='add'>+			linux,code = &lt;BTN_TRIGGER_HAPPY4&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio GPIOX_12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+		f5-button {</div><div class='add'>+			label = "F5";</div><div class='add'>+			linux,code = &lt;BTN_TRIGGER_HAPPY5&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio GPIOX_13 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+		f6-button {</div><div class='add'>+			label = "F6";</div><div class='add'>+			linux,code = &lt;BTN_TRIGGER_HAPPY6&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio GPIOX_16 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+		top-left-button {</div><div class='add'>+			label = "TOP Left";</div><div class='add'>+			linux,code = &lt;BTN_TL&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio GPIOX_14 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+		top-left2-button {</div><div class='add'>+			label = "TOP Left 2";</div><div class='add'>+			linux,code = &lt;BTN_TL2&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio GPIOX_19 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+		top-right-button {</div><div class='add'>+			label = "TOP Right";</div><div class='add'>+			linux,code = &lt;BTN_TR&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio GPIOX_15 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+		top-right2-button {</div><div class='add'>+			label = "TOP Right 2";</div><div class='add'>+			linux,code = &lt;BTN_TR2&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio GPIOX_18 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x0 0x0 0x40000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	emmc_pwrseq: emmc-pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-emmc";</div><div class='add'>+		reset-gpios = &lt;&amp;gpio BOOT_12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-blue {</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_sys: regulator-vdd-sys {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_SYS";</div><div class='add'>+		regulator-min-microvolt = &lt;3800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3800000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "amlogic,axg-sound-card";</div><div class='add'>+		model = "Odroid GO Ultra";</div><div class='add'>+		audio-widgets = "Microphone", "Mic Jack",</div><div class='add'>+				"Headphone", "Headphones",</div><div class='add'>+				"Speaker", "Internal Speakers";</div><div class='add'>+		audio-aux-devs = &lt;&amp;tdmout_b&gt;, &lt;&amp;tdmin_b&gt;, &lt;&amp;speaker_amp&gt;;</div><div class='add'>+		audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",</div><div class='add'>+				"TDM_B Playback", "TDMOUT_B OUT",</div><div class='add'>+				"TDMIN_B IN 1", "TDM_B Capture",</div><div class='add'>+				"TDMIN_B IN 4", "TDM_B Loopback",</div><div class='add'>+				"TODDR_A IN 1", "TDMIN_B OUT",</div><div class='add'>+				"MICL", "Mic Jack",</div><div class='add'>+				"Headphones", "HPOL",</div><div class='add'>+				"Headphones", "HPOR",</div><div class='add'>+				"Speaker Amplifier INL", "HPOL",</div><div class='add'>+				"Speaker Amplifier INR", "HPOR",</div><div class='add'>+				"Internal Speakers", "Speaker Amplifier OUTL",</div><div class='add'>+				"Internal Speakers", "Speaker Amplifier OUTR";</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;294912000&gt;,</div><div class='add'>+				       &lt;270950400&gt;,</div><div class='add'>+				       &lt;393216000&gt;;</div><div class='add'>+</div><div class='add'>+		dai-link-0 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_a&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-1 {</div><div class='add'>+			sound-dai = &lt;&amp;toddr_a&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-2 {</div><div class='add'>+			sound-dai = &lt;&amp;tdmif_b&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			dai-tdm-slot-tx-mask-0 = &lt;1 1&gt;;</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;rk817&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	speaker_amp: speaker-amplifier {</div><div class='add'>+		compatible = "simple-audio-amplifier";</div><div class='add'>+		sound-name-prefix = "Speaker Amplifier";</div><div class='add'>+		VCC-supply = &lt;&amp;hp_5v&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;arb {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu_b&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table_0&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPU_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu1 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu_b&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table_0&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPU_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu100 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu_a&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpub_opp_table_1&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPUB_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu101 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu_a&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpub_opp_table_1&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPUB_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu102 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu_a&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpub_opp_table_1&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPUB_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu103 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu_a&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpub_opp_table_1&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPUB_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* RK817 only supports 12.5mV steps, round up the values */</div><div class='add'>+&amp;cpu_opp_table_0 {</div><div class='add'>+	opp-1000000000 {</div><div class='add'>+		opp-microvolt = &lt;737500&gt;;</div><div class='add'>+	};</div><div class='add'>+	opp-1200000000 {</div><div class='add'>+		opp-microvolt = &lt;737500&gt;;</div><div class='add'>+	};</div><div class='add'>+	opp-1398000000 {</div><div class='add'>+		opp-microvolt = &lt;762500&gt;;</div><div class='add'>+	};</div><div class='add'>+	opp-1512000000 {</div><div class='add'>+		opp-microvolt = &lt;800000&gt;;</div><div class='add'>+	};</div><div class='add'>+	opp-1608000000 {</div><div class='add'>+		opp-microvolt = &lt;837500&gt;;</div><div class='add'>+	};</div><div class='add'>+	opp-1704000000 {</div><div class='add'>+		opp-microvolt = &lt;862500&gt;;</div><div class='add'>+	};</div><div class='add'>+	opp-1896000000 {</div><div class='add'>+		opp-microvolt = &lt;987500&gt;;</div><div class='add'>+	};</div><div class='add'>+	opp-1992000000 {</div><div class='add'>+		opp-microvolt = &lt;1012500&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* RK818 only supports 12.5mV steps, round up the values */</div><div class='add'>+&amp;cpub_opp_table_1 {</div><div class='add'>+	opp-1000000000 {</div><div class='add'>+		opp-microvolt = &lt;775000&gt;;</div><div class='add'>+	};</div><div class='add'>+	opp-1200000000 {</div><div class='add'>+		opp-microvolt = &lt;775000&gt;;</div><div class='add'>+	};</div><div class='add'>+	opp-1398000000 {</div><div class='add'>+		opp-microvolt = &lt;800000&gt;;</div><div class='add'>+	};</div><div class='add'>+	opp-1512000000 {</div><div class='add'>+		opp-microvolt = &lt;825000&gt;;</div><div class='add'>+	};</div><div class='add'>+	opp-1608000000 {</div><div class='add'>+		opp-microvolt = &lt;862500&gt;;</div><div class='add'>+	};</div><div class='add'>+	opp-1704000000 {</div><div class='add'>+		opp-microvolt = &lt;900000&gt;;</div><div class='add'>+	};</div><div class='add'>+	opp-1800000000 {</div><div class='add'>+		opp-microvolt = &lt;987500&gt;;</div><div class='add'>+	};</div><div class='add'>+	opp-1908000000 {</div><div class='add'>+		opp-microvolt = &lt;1025000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c_AO {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c_ao_sck_pins&gt;, &lt;&amp;i2c_ao_sda_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	rk818: pmic@1c {</div><div class='add'>+		compatible = "rockchip,rk818";</div><div class='add'>+		reg = &lt;0x1c&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio_intc&gt;;</div><div class='add'>+		interrupts = &lt;IRQID_GPIOAO_7 IRQ_TYPE_LEVEL_LOW&gt;; /* GPIOAO_7 */</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		vcc1-supply = &lt;&amp;vdd_sys&gt;;</div><div class='add'>+		vcc2-supply = &lt;&amp;vdd_sys&gt;;</div><div class='add'>+		vcc3-supply = &lt;&amp;vdd_sys&gt;;</div><div class='add'>+		vcc4-supply = &lt;&amp;vdd_sys&gt;;</div><div class='add'>+		vcc6-supply = &lt;&amp;vdd_sys&gt;;</div><div class='add'>+		vcc7-supply = &lt;&amp;vcc_2v3&gt;;</div><div class='add'>+		vcc8-supply = &lt;&amp;vcc_2v3&gt;;</div><div class='add'>+		vcc9-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+		boost-supply = &lt;&amp;vdd_sys&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			vddcpu_a: DCDC_REG1 {</div><div class='add'>+				regulator-name = "vddcpu_a";</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-min-microvolt = &lt;775000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1025000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;6001&gt;;</div><div class='add'>+				regulator-state-mem {</div><div class='add'>+					regulator-on-in-suspend;</div><div class='add'>+					regulator-suspend-microvolt = &lt;775000&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_ee: DCDC_REG2 {</div><div class='add'>+				regulator-name = "vdd_ee";</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-min-microvolt = &lt;875000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1250000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;6001&gt;;</div><div class='add'>+				regulator-state-mem {</div><div class='add'>+					regulator-on-in-suspend;</div><div class='add'>+					regulator-suspend-microvolt = &lt;875000&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vddq_1v1: DCDC_REG3 {</div><div class='add'>+				regulator-name = "vddq_1v1";</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-state-mem {</div><div class='add'>+					regulator-on-in-suspend;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vddao_3v3: DCDC_REG4 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "vddao_3v3";</div><div class='add'>+				regulator-state-mem {</div><div class='add'>+					regulator-on-in-suspend;</div><div class='add'>+					regulator-suspend-microvolt = &lt;3300000&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			hp_5v: DCDC_BOOST {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-name = "hp_5v";</div><div class='add'>+				regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+				regulator-state-mem {</div><div class='add'>+					regulator-off-in-suspend;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vddio_ao1v8: LDO_REG5 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "vddio_ao1v8";</div><div class='add'>+				regulator-state-mem {</div><div class='add'>+					regulator-on-in-suspend;</div><div class='add'>+					regulator-suspend-microvolt = &lt;1800000&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vddq_1v8: LDO_REG7 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "vddq_1v8";</div><div class='add'>+				regulator-state-mem {</div><div class='add'>+					regulator-on-in-suspend;</div><div class='add'>+					regulator-suspend-microvolt = &lt;1800000&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vddio_c: LDO_REG9 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "vddio_c";</div><div class='add'>+				regulator-state-mem {</div><div class='add'>+					regulator-on-in-suspend;</div><div class='add'>+					regulator-suspend-microvolt = &lt;3300000&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vcc_sd: SWITCH_REG {</div><div class='add'>+				regulator-name = "vcc_sd";</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-state-mem {</div><div class='add'>+					regulator-on-in-suspend;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			OTG_SWITCH {</div><div class='add'>+				regulator-name = "otg_switch";</div><div class='add'>+				regulator-state-mem {</div><div class='add'>+					regulator-off-in-suspend;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c3_sda_a_pins&gt;, &lt;&amp;i2c3_sck_a_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	rk817: pmic@20 {</div><div class='add'>+		compatible = "rockchip,rk817";</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio_intc&gt;;</div><div class='add'>+</div><div class='add'>+		interrupts = &lt;IRQID_GPIOAO_5 IRQ_TYPE_LEVEL_LOW&gt;; /* GPIOAO_5 */</div><div class='add'>+</div><div class='add'>+		vcc1-supply = &lt;&amp;vdd_sys&gt;;</div><div class='add'>+		vcc2-supply = &lt;&amp;vdd_sys&gt;;</div><div class='add'>+		vcc3-supply = &lt;&amp;vdd_sys&gt;;</div><div class='add'>+		vcc4-supply = &lt;&amp;vdd_sys&gt;;</div><div class='add'>+		vcc5-supply = &lt;&amp;vdd_sys&gt;;</div><div class='add'>+		vcc6-supply = &lt;&amp;vdd_sys&gt;;</div><div class='add'>+		vcc7-supply = &lt;&amp;vdd_sys&gt;;</div><div class='add'>+		vcc8-supply = &lt;&amp;vdd_sys&gt;;</div><div class='add'>+		vcc9-supply = &lt;&amp;rk817_boost&gt;;</div><div class='add'>+</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		clocks = &lt;&amp;codec_clk&gt;;</div><div class='add'>+		clock-names = "mclk";</div><div class='add'>+</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			vddcpu_b: DCDC_REG2 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-min-microvolt = &lt;737500&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1012500&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;6001&gt;;</div><div class='add'>+				regulator-initial-mode = &lt;0x2&gt;;</div><div class='add'>+				regulator-name = "vddcpu_b";</div><div class='add'>+				regulator-state-mem {</div><div class='add'>+					regulator-on-in-suspend;</div><div class='add'>+					regulator-suspend-microvolt = &lt;1000000&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vcc_2v3: DCDC_REG3 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-min-microvolt = &lt;2300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2400000&gt;;</div><div class='add'>+				regulator-initial-mode = &lt;0x2&gt;;</div><div class='add'>+				regulator-name = "vcc_2v3";</div><div class='add'>+				regulator-state-mem {</div><div class='add'>+					regulator-on-in-suspend;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			LDO_REG4 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "vdd_codec";</div><div class='add'>+				regulator-state-mem {</div><div class='add'>+					regulator-off-in-suspend;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vcc_lcd: LDO_REG8 {</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "vcc_lcd";</div><div class='add'>+				regulator-state-mem {</div><div class='add'>+					regulator-off-in-suspend;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			rk817_boost: BOOST {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;5400000&gt;;</div><div class='add'>+				regulator-name = "rk817_boost";</div><div class='add'>+				regulator-state-mem {</div><div class='add'>+					regulator-off-in-suspend;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			usb_host: OTG_SWITCH {</div><div class='add'>+				regulator-name = "usb_host";</div><div class='add'>+				regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+				regulator-state-mem {</div><div class='add'>+					regulator-off-in-suspend;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;clkc_audio {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eth_phy {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;periphs_pinctrl {</div><div class='add'>+	keypad_gpio_pins: keypad-gpio-state {</div><div class='add'>+		mux {</div><div class='add'>+			groups = "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3",</div><div class='add'>+			         "GPIOX_4", "GPIOX_5", "GPIOX_6", "GPIOX_7",</div><div class='add'>+				 "GPIOX_8", "GPIOX_9", "GPIOX_10", "GPIOX_11",</div><div class='add'>+				 "GPIOX_12", "GPIOX_13", "GPIOX_14",  "GPIOX_15",</div><div class='add'>+				 "GPIOX_16", "GPIOX_17", "GPIOX_18",  "GPIOX_19";</div><div class='add'>+			function = "gpio_periphs";</div><div class='add'>+			bias-pull-up;</div><div class='add'>+			output-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;saradc {</div><div class='add'>+	status = "okay";</div><div class='add'>+	vref-supply = &lt;&amp;vddio_ao1v8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SD card */</div><div class='add'>+&amp;sd_emmc_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdcard_c_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;sdcard_clk_gate_c_pins&gt;;</div><div class='add'>+	pinctrl-names = "default", "clk-gate";</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	max-frequency = &lt;50000000&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+</div><div class='add'>+	cd-gpios = &lt;&amp;gpio GPIOC_6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;vcc_sd&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;vddio_c&gt;;</div><div class='add'>+</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* eMMC */</div><div class='add'>+&amp;sd_emmc_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;emmc_ctrl_pins&gt;, &lt;&amp;emmc_data_8b_pins&gt;, &lt;&amp;emmc_ds_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;emmc_clk_gate_pins&gt;;</div><div class='add'>+	pinctrl-names = "default", "clk-gate";</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	cap-mmc-highspeed;</div><div class='add'>+	mmc-ddr-1_8v;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+</div><div class='add'>+	mmc-pwrseq = &lt;&amp;emmc_pwrseq&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;vcc_sd&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;vddio_ao1v8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+&amp;tdmif_b {</div><div class='add'>+	pinctrl-0 = &lt;&amp;tdm_b_dout0_pins&gt;, &lt;&amp;tdm_b_fs_pins&gt;, &lt;&amp;tdm_b_sclk_pins&gt;, &lt;&amp;tdm_b_din1_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	assigned-clocks = &lt;&amp;clkc_audio AUD_CLKID_TDM_SCLK_PAD1&gt;,</div><div class='add'>+			  &lt;&amp;clkc_audio AUD_CLKID_TDM_LRCLK_PAD1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clkc_audio AUD_CLKID_MST_B_SCLK&gt;,</div><div class='add'>+				 &lt;&amp;clkc_audio AUD_CLKID_MST_B_LRCLK&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmin_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmout_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;toddr_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart_AO {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart_ao_a_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb {</div><div class='add'>+	status = "okay";</div><div class='add'>+	dr_mode = "peripheral";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb2_phy0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb2_phy1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	phy-supply = &lt;&amp;usb_host&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus.dts<br/>new file mode 100644<br/>index 000000000000..ce1198ad34e4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus.dts</a></div><div class='hunk'>@@ -0,0 +1,31 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2019 BayLibre, SAS</div><div class='add'>+ * Author: Neil Armstrong &lt;narmstrong@baylibre.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+/* The Amlogic S922X Rev. C supports the same OPPs as the A311D variant */</div><div class='add'>+#include "meson-g12b-a311d.dtsi"</div><div class='add'>+#include "meson-g12b-odroid-n2.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "hardkernel,odroid-n2-plus", "amlogic,s922x", "amlogic,g12b";</div><div class='add'>+	model = "Hardkernel ODROID-N2Plus";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;vddcpu_a {</div><div class='add'>+	regulator-min-microvolt = &lt;680000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;1040000&gt;;</div><div class='add'>+</div><div class='add'>+	pwms = &lt;&amp;pwm_ab 0 1500 0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;vddcpu_b {</div><div class='add'>+	regulator-min-microvolt = &lt;680000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;1040000&gt;;</div><div class='add'>+</div><div class='add'>+	pwms = &lt;&amp;pwm_AO_cd 1 1500 0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts<br/>index 169ea283d4ee..a198a91259ec 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts</a></div><div class='hunk'>@@ -7,499 +7,9 @@</div><div class='ctx'> /dts-v1/;</div><div class='ctx'> </div><div class='ctx'> #include "meson-g12b-s922x.dtsi"</div><div class='del'>-#include &lt;dt-bindings/input/input.h&gt;</div><div class='del'>-#include &lt;dt-bindings/gpio/meson-g12a-gpio.h&gt;</div><div class='del'>-#include &lt;dt-bindings/sound/meson-g12a-tohdmitx.h&gt;</div><div class='add'>+#include "meson-g12b-odroid-n2.dtsi"</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	compatible = "hardkernel,odroid-n2", "amlogic,s922x", "amlogic,g12b";</div><div class='ctx'> 	model = "Hardkernel ODROID-N2";</div><div class='del'>-</div><div class='del'>-	aliases {</div><div class='del'>-		serial0 = &amp;uart_AO;</div><div class='del'>-		ethernet0 = &amp;ethmac;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	chosen {</div><div class='del'>-		stdout-path = "serial0:115200n8";</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	memory@0 {</div><div class='del'>-		device_type = "memory";</div><div class='del'>-		reg = &lt;0x0 0x0 0x0 0x40000000&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	emmc_pwrseq: emmc-pwrseq {</div><div class='del'>-		compatible = "mmc-pwrseq-emmc";</div><div class='del'>-		reset-gpios = &lt;&amp;gpio BOOT_12 GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	leds {</div><div class='del'>-		compatible = "gpio-leds";</div><div class='del'>-</div><div class='del'>-		blue {</div><div class='del'>-			label = "n2:blue";</div><div class='del'>-			gpios = &lt;&amp;gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			linux,default-trigger = "heartbeat";</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	tflash_vdd: regulator-tflash_vdd {</div><div class='del'>-		compatible = "regulator-fixed";</div><div class='del'>-</div><div class='del'>-		regulator-name = "TFLASH_VDD";</div><div class='del'>-		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='del'>-</div><div class='del'>-		gpio = &lt;&amp;gpio_ao GPIOAO_8 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-		enable-active-high;</div><div class='del'>-		regulator-always-on;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	tf_io: gpio-regulator-tf_io {</div><div class='del'>-		compatible = "regulator-gpio";</div><div class='del'>-</div><div class='del'>-		regulator-name = "TF_IO";</div><div class='del'>-		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='del'>-</div><div class='del'>-		gpios = &lt;&amp;gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-		gpios-states = &lt;0&gt;;</div><div class='del'>-</div><div class='del'>-		states = &lt;3300000 0&gt;,</div><div class='del'>-			 &lt;1800000 1&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	flash_1v8: regulator-flash_1v8 {</div><div class='del'>-		compatible = "regulator-fixed";</div><div class='del'>-		regulator-name = "FLASH_1V8";</div><div class='del'>-		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='del'>-		vin-supply = &lt;&amp;vcc_3v3&gt;;</div><div class='del'>-		regulator-always-on;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	main_12v: regulator-main_12v {</div><div class='del'>-		compatible = "regulator-fixed";</div><div class='del'>-		regulator-name = "12V";</div><div class='del'>-		regulator-min-microvolt = &lt;12000000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;12000000&gt;;</div><div class='del'>-		regulator-always-on;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	vcc_5v: regulator-vcc_5v {</div><div class='del'>-		compatible = "regulator-fixed";</div><div class='del'>-		regulator-name = "5V";</div><div class='del'>-		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='del'>-		regulator-always-on;</div><div class='del'>-		vin-supply = &lt;&amp;main_12v&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	vcc_1v8: regulator-vcc_1v8 {</div><div class='del'>-		compatible = "regulator-fixed";</div><div class='del'>-		regulator-name = "VCC_1V8";</div><div class='del'>-		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='del'>-		vin-supply = &lt;&amp;vcc_3v3&gt;;</div><div class='del'>-		regulator-always-on;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	vcc_3v3: regulator-vcc_3v3 {</div><div class='del'>-		compatible = "regulator-fixed";</div><div class='del'>-		regulator-name = "VCC_3V3";</div><div class='del'>-		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='del'>-		vin-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='del'>-		regulator-always-on;</div><div class='del'>-		/* FIXME: actually controlled by VDDCPU_B_EN */</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	vddcpu_a: regulator-vddcpu-a {</div><div class='del'>-		/*</div><div class='del'>-		 * MP8756GD Regulator.</div><div class='del'>-		 */</div><div class='del'>-		compatible = "pwm-regulator";</div><div class='del'>-</div><div class='del'>-		regulator-name = "VDDCPU_A";</div><div class='del'>-		regulator-min-microvolt = &lt;721000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;1022000&gt;;</div><div class='del'>-</div><div class='del'>-		vin-supply = &lt;&amp;main_12v&gt;;</div><div class='del'>-</div><div class='del'>-		pwms = &lt;&amp;pwm_ab 0 1250 0&gt;;</div><div class='del'>-		pwm-dutycycle-range = &lt;100 0&gt;;</div><div class='del'>-</div><div class='del'>-		regulator-boot-on;</div><div class='del'>-		regulator-always-on;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	vddcpu_b: regulator-vddcpu-b {</div><div class='del'>-		/*</div><div class='del'>-		 * Silergy SY8120B1ABC Regulator.</div><div class='del'>-		 */</div><div class='del'>-		compatible = "pwm-regulator";</div><div class='del'>-</div><div class='del'>-		regulator-name = "VDDCPU_B";</div><div class='del'>-		regulator-min-microvolt = &lt;721000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;1022000&gt;;</div><div class='del'>-</div><div class='del'>-		vin-supply = &lt;&amp;main_12v&gt;;</div><div class='del'>-</div><div class='del'>-		pwms = &lt;&amp;pwm_AO_cd 1 1250 0&gt;;</div><div class='del'>-		pwm-dutycycle-range = &lt;100 0&gt;;</div><div class='del'>-</div><div class='del'>-		regulator-boot-on;</div><div class='del'>-		regulator-always-on;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	hub_5v: regulator-hub_5v {</div><div class='del'>-		compatible = "regulator-fixed";</div><div class='del'>-		regulator-name = "HUB_5V";</div><div class='del'>-		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='del'>-		vin-supply = &lt;&amp;vcc_5v&gt;;</div><div class='del'>-</div><div class='del'>-		/* Connected to the Hub CHIPENABLE, LOW sets low power state */</div><div class='del'>-		gpio = &lt;&amp;gpio GPIOH_5 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-		enable-active-high;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	usb_pwr_en: regulator-usb_pwr_en {</div><div class='del'>-		compatible = "regulator-fixed";</div><div class='del'>-		regulator-name = "USB_PWR_EN";</div><div class='del'>-		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='del'>-		vin-supply = &lt;&amp;vcc_5v&gt;;</div><div class='del'>-</div><div class='del'>-		/* Connected to the microUSB port power enable */</div><div class='del'>-		gpio = &lt;&amp;gpio GPIOH_6 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-		enable-active-high;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	vddao_1v8: regulator-vddao_1v8 {</div><div class='del'>-		compatible = "regulator-fixed";</div><div class='del'>-		regulator-name = "VDDAO_1V8";</div><div class='del'>-		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='del'>-		vin-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='del'>-		regulator-always-on;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	vddao_3v3: regulator-vddao_3v3 {</div><div class='del'>-		compatible = "regulator-fixed";</div><div class='del'>-		regulator-name = "VDDAO_3V3";</div><div class='del'>-		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='del'>-		vin-supply = &lt;&amp;main_12v&gt;;</div><div class='del'>-		regulator-always-on;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	hdmi-connector {</div><div class='del'>-		compatible = "hdmi-connector";</div><div class='del'>-		type = "a";</div><div class='del'>-</div><div class='del'>-		port {</div><div class='del'>-			hdmi_connector_in: endpoint {</div><div class='del'>-				remote-endpoint = &lt;&amp;hdmi_tx_tmds_out&gt;;</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	sound {</div><div class='del'>-		compatible = "amlogic,axg-sound-card";</div><div class='del'>-		model = "G12B-ODROID-N2";</div><div class='del'>-		audio-aux-devs = &lt;&amp;tdmout_b&gt;;</div><div class='del'>-		audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",</div><div class='del'>-				"TDMOUT_B IN 1", "FRDDR_B OUT 1",</div><div class='del'>-				"TDMOUT_B IN 2", "FRDDR_C OUT 1",</div><div class='del'>-				"TDM_B Playback", "TDMOUT_B OUT";</div><div class='del'>-</div><div class='del'>-		assigned-clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='del'>-				  &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='del'>-				  &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='del'>-		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='del'>-		assigned-clock-rates = &lt;294912000&gt;,</div><div class='del'>-				       &lt;270950400&gt;,</div><div class='del'>-				       &lt;393216000&gt;;</div><div class='del'>-		status = "okay";</div><div class='del'>-</div><div class='del'>-		dai-link-0 {</div><div class='del'>-			sound-dai = &lt;&amp;frddr_a&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		dai-link-1 {</div><div class='del'>-			sound-dai = &lt;&amp;frddr_b&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		dai-link-2 {</div><div class='del'>-			sound-dai = &lt;&amp;frddr_c&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		/* 8ch hdmi interface */</div><div class='del'>-		dai-link-3 {</div><div class='del'>-			sound-dai = &lt;&amp;tdmif_b&gt;;</div><div class='del'>-			dai-format = "i2s";</div><div class='del'>-			dai-tdm-slot-tx-mask-0 = &lt;1 1&gt;;</div><div class='del'>-			dai-tdm-slot-tx-mask-1 = &lt;1 1&gt;;</div><div class='del'>-			dai-tdm-slot-tx-mask-2 = &lt;1 1&gt;;</div><div class='del'>-			dai-tdm-slot-tx-mask-3 = &lt;1 1&gt;;</div><div class='del'>-			mclk-fs = &lt;256&gt;;</div><div class='del'>-</div><div class='del'>-			codec {</div><div class='del'>-				sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_IN_B&gt;;</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		/* hdmi glue */</div><div class='del'>-		dai-link-4 {</div><div class='del'>-			sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_OUT&gt;;</div><div class='del'>-</div><div class='del'>-			codec {</div><div class='del'>-				sound-dai = &lt;&amp;hdmi_tx&gt;;</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;arb {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;cec_AO {</div><div class='del'>-	pinctrl-0 = &lt;&amp;cec_ao_a_h_pins&gt;;</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-	status = "disabled";</div><div class='del'>-	hdmi-phandle = &lt;&amp;hdmi_tx&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;cecb_AO {</div><div class='del'>-	pinctrl-0 = &lt;&amp;cec_ao_b_h_pins&gt;;</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-	status = "okay";</div><div class='del'>-	hdmi-phandle = &lt;&amp;hdmi_tx&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;clkc_audio {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;cpu0 {</div><div class='del'>-	cpu-supply = &lt;&amp;vddcpu_b&gt;;</div><div class='del'>-	operating-points-v2 = &lt;&amp;cpu_opp_table_0&gt;;</div><div class='del'>-	clocks = &lt;&amp;clkc CLKID_CPU_CLK&gt;;</div><div class='del'>-	clock-latency = &lt;50000&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;cpu1 {</div><div class='del'>-	cpu-supply = &lt;&amp;vddcpu_b&gt;;</div><div class='del'>-	operating-points-v2 = &lt;&amp;cpu_opp_table_0&gt;;</div><div class='del'>-	clocks = &lt;&amp;clkc CLKID_CPU_CLK&gt;;</div><div class='del'>-	clock-latency = &lt;50000&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;cpu100 {</div><div class='del'>-	cpu-supply = &lt;&amp;vddcpu_a&gt;;</div><div class='del'>-	operating-points-v2 = &lt;&amp;cpub_opp_table_1&gt;;</div><div class='del'>-	clocks = &lt;&amp;clkc CLKID_CPUB_CLK&gt;;</div><div class='del'>-	clock-latency = &lt;50000&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;cpu101 {</div><div class='del'>-	cpu-supply = &lt;&amp;vddcpu_a&gt;;</div><div class='del'>-	operating-points-v2 = &lt;&amp;cpub_opp_table_1&gt;;</div><div class='del'>-	clocks = &lt;&amp;clkc CLKID_CPUB_CLK&gt;;</div><div class='del'>-	clock-latency = &lt;50000&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;cpu102 {</div><div class='del'>-	cpu-supply = &lt;&amp;vddcpu_a&gt;;</div><div class='del'>-	operating-points-v2 = &lt;&amp;cpub_opp_table_1&gt;;</div><div class='del'>-	clocks = &lt;&amp;clkc CLKID_CPUB_CLK&gt;;</div><div class='del'>-	clock-latency = &lt;50000&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;cpu103 {</div><div class='del'>-	cpu-supply = &lt;&amp;vddcpu_a&gt;;</div><div class='del'>-	operating-points-v2 = &lt;&amp;cpub_opp_table_1&gt;;</div><div class='del'>-	clocks = &lt;&amp;clkc CLKID_CPUB_CLK&gt;;</div><div class='del'>-	clock-latency = &lt;50000&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;ext_mdio {</div><div class='del'>-	external_phy: ethernet-phy@0 {</div><div class='del'>-		/* Realtek RTL8211F (0x001cc916) */	</div><div class='del'>-		reg = &lt;0&gt;;</div><div class='del'>-		max-speed = &lt;1000&gt;;</div><div class='del'>-</div><div class='del'>-		reset-assert-us = &lt;10000&gt;;</div><div class='del'>-		reset-deassert-us = &lt;30000&gt;;</div><div class='del'>-		reset-gpios = &lt;&amp;gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)&gt;;</div><div class='del'>-</div><div class='del'>-		interrupt-parent = &lt;&amp;gpio_intc&gt;;</div><div class='del'>-		/* MAC_INTR on GPIOZ_14 */</div><div class='del'>-		interrupts = &lt;26 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;ethmac {</div><div class='del'>-	pinctrl-0 = &lt;&amp;eth_pins&gt;, &lt;&amp;eth_rgmii_pins&gt;;</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-	status = "okay";</div><div class='del'>-	phy-mode = "rgmii";</div><div class='del'>-	phy-handle = &lt;&amp;external_phy&gt;;</div><div class='del'>-	amlogic,tx-delay-ns = &lt;2&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;frddr_a {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;frddr_b {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;frddr_c {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;gpio {</div><div class='del'>-	/*</div><div class='del'>-	 * WARNING: The USB Hub on the Odroid-N2 needs a reset signal</div><div class='del'>-	 * to be turned high in order to be detected by the USB Controller</div><div class='del'>-	 * This signal should be handled by a USB specific power sequence</div><div class='del'>-	 * in order to reset the Hub when USB bus is powered down.</div><div class='del'>-	 */</div><div class='del'>-	usb-hub {</div><div class='del'>-		gpio-hog;</div><div class='del'>-		gpios = &lt;GPIOH_4 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-		output-high;</div><div class='del'>-		line-name = "usb-hub-reset";</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;hdmi_tx {</div><div class='del'>-	status = "okay";</div><div class='del'>-	pinctrl-0 = &lt;&amp;hdmitx_hpd_pins&gt;, &lt;&amp;hdmitx_ddc_pins&gt;;</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-	hdmi-supply = &lt;&amp;vcc_5v&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;hdmi_tx_tmds_port {</div><div class='del'>-	hdmi_tx_tmds_out: endpoint {</div><div class='del'>-		remote-endpoint = &lt;&amp;hdmi_connector_in&gt;;</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;ir {</div><div class='del'>-	status = "okay";</div><div class='del'>-	pinctrl-0 = &lt;&amp;remote_input_ao_pins&gt;;</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-	linux,rc-map-name = "rc-odroid";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;pwm_ab {</div><div class='del'>-	pinctrl-0 = &lt;&amp;pwm_a_e_pins&gt;;</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-	clocks = &lt;&amp;xtal&gt;;</div><div class='del'>-	clock-names = "clkin0";</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;pwm_AO_cd {</div><div class='del'>-	pinctrl-0 = &lt;&amp;pwm_ao_d_e_pins&gt;;</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-	clocks = &lt;&amp;xtal&gt;;</div><div class='del'>-	clock-names = "clkin1";</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-/* SD card */</div><div class='del'>-&amp;sd_emmc_b {</div><div class='del'>-	status = "okay";</div><div class='del'>-	pinctrl-0 = &lt;&amp;sdcard_c_pins&gt;;</div><div class='del'>-	pinctrl-1 = &lt;&amp;sdcard_clk_gate_c_pins&gt;;</div><div class='del'>-	pinctrl-names = "default", "clk-gate";</div><div class='del'>-</div><div class='del'>-	bus-width = &lt;4&gt;;</div><div class='del'>-	cap-sd-highspeed;</div><div class='del'>-	max-frequency = &lt;50000000&gt;;</div><div class='del'>-	disable-wp;</div><div class='del'>-</div><div class='del'>-	cd-gpios = &lt;&amp;gpio GPIOC_6 GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-	vmmc-supply = &lt;&amp;tflash_vdd&gt;;</div><div class='del'>-	vqmmc-supply = &lt;&amp;tf_io&gt;;</div><div class='del'>-</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-/* eMMC */</div><div class='del'>-&amp;sd_emmc_c {</div><div class='del'>-	status = "okay";</div><div class='del'>-	pinctrl-0 = &lt;&amp;emmc_ctrl_pins&gt;, &lt;&amp;emmc_data_8b_pins&gt;, &lt;&amp;emmc_ds_pins&gt;;</div><div class='del'>-	pinctrl-1 = &lt;&amp;emmc_clk_gate_pins&gt;;</div><div class='del'>-	pinctrl-names = "default", "clk-gate";</div><div class='del'>-</div><div class='del'>-	bus-width = &lt;8&gt;;</div><div class='del'>-	cap-mmc-highspeed;</div><div class='del'>-	mmc-ddr-1_8v;</div><div class='del'>-	mmc-hs200-1_8v;</div><div class='del'>-	max-frequency = &lt;200000000&gt;;</div><div class='del'>-	disable-wp;</div><div class='del'>-</div><div class='del'>-	mmc-pwrseq = &lt;&amp;emmc_pwrseq&gt;;</div><div class='del'>-	vmmc-supply = &lt;&amp;vcc_3v3&gt;;</div><div class='del'>-	vqmmc-supply = &lt;&amp;flash_1v8&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * EMMC_D4, EMMC_D5, EMMC_D6 and EMMC_D7 pins are shared between SPI NOR pins</div><div class='del'>- * and eMMC Data 4 to 7 pins.</div><div class='del'>- * Replace emmc_data_8b_pins to emmc_data_4b_pins from sd_emmc_c pinctrl-0,</div><div class='del'>- * and change bus-width to 4 then spifc can be enabled.</div><div class='del'>- * The SW1 slide should also be set to the correct position.</div><div class='del'>- */</div><div class='del'>-&amp;spifc {</div><div class='del'>-	status = "disabled";</div><div class='del'>-	pinctrl-0 = &lt;&amp;nor_pins&gt;;</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-</div><div class='del'>-	mx25u64: spi-flash@0 {</div><div class='del'>-		#address-cells = &lt;1&gt;;</div><div class='del'>-		#size-cells = &lt;1&gt;;</div><div class='del'>-		compatible = "mxicy,mx25u6435f", "jedec,spi-nor";</div><div class='del'>-		reg = &lt;0&gt;;</div><div class='del'>-		spi-max-frequency = &lt;104000000&gt;;</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;tdmif_b {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;tdmout_b {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;tohdmitx {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;uart_AO {</div><div class='del'>-	status = "okay";</div><div class='del'>-	pinctrl-0 = &lt;&amp;uart_ao_a_pins&gt;;</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;usb {</div><div class='del'>-	status = "okay";</div><div class='del'>-	vbus-supply = &lt;&amp;usb_pwr_en&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;usb2_phy0 {</div><div class='del'>-	phy-supply = &lt;&amp;vcc_5v&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;usb2_phy1 {</div><div class='del'>-	/* Enable the hub which is connected to this port */</div><div class='del'>-	phy-supply = &lt;&amp;hub_5v&gt;;</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi<br/>new file mode 100644<br/>index 000000000000..3bca8023638d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi</a></div><div class='hunk'>@@ -0,0 +1,318 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2019 BayLibre, SAS</div><div class='add'>+ * Author: Neil Armstrong &lt;narmstrong@baylibre.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "meson-g12b-odroid.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		rtc0 = &amp;rtc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dio2133: audio-amplifier-0 {</div><div class='add'>+		compatible = "simple-audio-amplifier";</div><div class='add'>+		enable-gpios = &lt;&amp;gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		VCC-supply = &lt;&amp;vcc_5v&gt;;</div><div class='add'>+		sound-name-prefix = "U19";</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hub_5v: regulator-hub-5v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "HUB_5V";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vcc_5v&gt;;</div><div class='add'>+</div><div class='add'>+		/* Connected to the Hub CHIPENABLE, LOW sets low power state */</div><div class='add'>+		gpio = &lt;&amp;gpio GPIOH_5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USB hub supports both USB 2.0 and USB 3.0 root hub */</div><div class='add'>+	usb-hub {</div><div class='add'>+		dr_mode = "host";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		/* 2.0 hub on port 1 */</div><div class='add'>+		hub_2_0: hub@1 {</div><div class='add'>+			compatible = "usb5e3,610";</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			peer-hub = &lt;&amp;hub_3_0&gt;;</div><div class='add'>+			vdd-supply = &lt;&amp;usb_pwr_en&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* 3.0 hub on port 4 */</div><div class='add'>+		hub_3_0: hub@2 {</div><div class='add'>+			compatible = "usb5e3,620";</div><div class='add'>+			reg = &lt;2&gt;;</div><div class='add'>+			peer-hub = &lt;&amp;hub_2_0&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio GPIOH_4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			vdd-supply = &lt;&amp;vcc_5v&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "amlogic,axg-sound-card";</div><div class='add'>+		model = "ODROID-N2";</div><div class='add'>+		audio-widgets = "Line", "Lineout";</div><div class='add'>+		audio-aux-devs = &lt;&amp;tdmout_b&gt;, &lt;&amp;tdmout_c&gt;, &lt;&amp;tdmin_a&gt;,</div><div class='add'>+				 &lt;&amp;tdmin_b&gt;, &lt;&amp;tdmin_c&gt;, &lt;&amp;tdmin_lb&gt;,</div><div class='add'>+				 &lt;&amp;dio2133&gt;;</div><div class='add'>+		audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",</div><div class='add'>+				"TDMOUT_B IN 1", "FRDDR_B OUT 1",</div><div class='add'>+				"TDMOUT_B IN 2", "FRDDR_C OUT 1",</div><div class='add'>+				"TDM_B Playback", "TDMOUT_B OUT",</div><div class='add'>+				"TDMOUT_C IN 0", "FRDDR_A OUT 2",</div><div class='add'>+				"TDMOUT_C IN 1", "FRDDR_B OUT 2",</div><div class='add'>+				"TDMOUT_C IN 2", "FRDDR_C OUT 2",</div><div class='add'>+				"TDM_C Playback", "TDMOUT_C OUT",</div><div class='add'>+				"TDMIN_A IN 4", "TDM_B Loopback",</div><div class='add'>+				"TDMIN_B IN 4", "TDM_B Loopback",</div><div class='add'>+				"TDMIN_C IN 4", "TDM_B Loopback",</div><div class='add'>+				"TDMIN_LB IN 1", "TDM_B Loopback",</div><div class='add'>+				"TDMIN_A IN 5", "TDM_C Loopback",</div><div class='add'>+				"TDMIN_B IN 5", "TDM_C Loopback",</div><div class='add'>+				"TDMIN_C IN 5", "TDM_C Loopback",</div><div class='add'>+				"TDMIN_LB IN 2", "TDM_C Loopback",</div><div class='add'>+				"TODDR_A IN 0", "TDMIN_A OUT",</div><div class='add'>+				"TODDR_B IN 0", "TDMIN_A OUT",</div><div class='add'>+				"TODDR_C IN 0", "TDMIN_A OUT",</div><div class='add'>+				"TODDR_A IN 1", "TDMIN_B OUT",</div><div class='add'>+				"TODDR_B IN 1", "TDMIN_B OUT",</div><div class='add'>+				"TODDR_C IN 1", "TDMIN_B OUT",</div><div class='add'>+				"TODDR_A IN 2", "TDMIN_C OUT",</div><div class='add'>+				"TODDR_B IN 2", "TDMIN_C OUT",</div><div class='add'>+				"TODDR_C IN 2", "TDMIN_C OUT",</div><div class='add'>+				"TODDR_A IN 6", "TDMIN_LB OUT",</div><div class='add'>+				"TODDR_B IN 6", "TDMIN_LB OUT",</div><div class='add'>+				"TODDR_C IN 6", "TDMIN_LB OUT",</div><div class='add'>+				"U19 INL", "ACODEC LOLP",</div><div class='add'>+				"U19 INR", "ACODEC LORP",</div><div class='add'>+				"Lineout", "U19 OUTL",</div><div class='add'>+				"Lineout", "U19 OUTR";</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;294912000&gt;,</div><div class='add'>+				       &lt;270950400&gt;,</div><div class='add'>+				       &lt;393216000&gt;;</div><div class='add'>+</div><div class='add'>+		dai-link-0 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_a&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-1 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_b&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-2 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_c&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-3 {</div><div class='add'>+			sound-dai = &lt;&amp;toddr_a&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-4 {</div><div class='add'>+			sound-dai = &lt;&amp;toddr_b&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-5 {</div><div class='add'>+			sound-dai = &lt;&amp;toddr_c&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* 8ch hdmi interface */</div><div class='add'>+		dai-link-6 {</div><div class='add'>+			sound-dai = &lt;&amp;tdmif_b&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			dai-tdm-slot-tx-mask-0 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-1 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-2 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-3 = &lt;1 1&gt;;</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_IN_B&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			codec-1 {</div><div class='add'>+				sound-dai = &lt;&amp;toacodec TOACODEC_IN_B&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* i2s jack output interface */</div><div class='add'>+		dai-link-7 {</div><div class='add'>+			sound-dai = &lt;&amp;tdmif_c&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			dai-tdm-slot-tx-mask-0 = &lt;1 1&gt;;</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_IN_C&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			codec-1 {</div><div class='add'>+				sound-dai = &lt;&amp;toacodec TOACODEC_IN_C&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* hdmi glue */</div><div class='add'>+		dai-link-8 {</div><div class='add'>+			sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* acodec glue */</div><div class='add'>+		dai-link-9 {</div><div class='add'>+			sound-dai = &lt;&amp;toacodec TOACODEC_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;acodec&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;acodec {</div><div class='add'>+	AVDD-supply = &lt;&amp;vddao_1v8&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethmac {</div><div class='add'>+	pinctrl-0 = &lt;&amp;eth_pins&gt;, &lt;&amp;eth_rgmii_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+	phy-mode = "rgmii";</div><div class='add'>+	phy-handle = &lt;&amp;external_phy&gt;;</div><div class='add'>+	amlogic,tx-delay-ns = &lt;2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ext_mdio {</div><div class='add'>+	external_phy: ethernet-phy@0 {</div><div class='add'>+		/* Realtek RTL8211F (0x001cc916) */</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		max-speed = &lt;1000&gt;;</div><div class='add'>+</div><div class='add'>+		reset-assert-us = &lt;10000&gt;;</div><div class='add'>+		reset-deassert-us = &lt;80000&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio_intc&gt;;</div><div class='add'>+		/* MAC_INTR on GPIOZ_14 */</div><div class='add'>+		interrupts = &lt;IRQID_GPIOZ_14 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		/* GPIOZ */</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		/* GPIOH */</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"",</div><div class='add'>+		/* BOOT */</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		/* GPIOC */</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		/* GPIOA */</div><div class='add'>+		"PIN_44", /* GPIOA_0 */</div><div class='add'>+		"PIN_46", /* GPIOA_1 */</div><div class='add'>+		"PIN_45", /* GPIOA_2 */</div><div class='add'>+		"PIN_47", /* GPIOA_3 */</div><div class='add'>+		"PIN_26", /* GPIOA_4 */</div><div class='add'>+		"", "", "", "", "", "",</div><div class='add'>+		"PIN_42", /* GPIOA_11 */</div><div class='add'>+		"PIN_32", /* GPIOA_12 */</div><div class='add'>+		"PIN_7",  /* GPIOA_13 */</div><div class='add'>+		"PIN_27", /* GPIOA_14 */</div><div class='add'>+		"PIN_28", /* GPIOA_15 */</div><div class='add'>+		/* GPIOX */</div><div class='add'>+		"PIN_16", /* GPIOX_0 */</div><div class='add'>+		"PIN_18", /* GPIOX_1 */</div><div class='add'>+		"PIN_22", /* GPIOX_2 */</div><div class='add'>+		"PIN_11", /* GPIOX_3 */</div><div class='add'>+		"PIN_13", /* GPIOX_4 */</div><div class='add'>+		"PIN_33", /* GPIOX_5 */</div><div class='add'>+		"PIN_35", /* GPIOX_6 */</div><div class='add'>+		"PIN_15", /* GPIOX_7 */</div><div class='add'>+		"PIN_19", /* GPIOX_8 */</div><div class='add'>+		"PIN_21", /* GPIOX_9 */</div><div class='add'>+		"PIN_24", /* GPIOX_10 */</div><div class='add'>+		"PIN_23", /* GPIOX_11 */</div><div class='add'>+		"PIN_8",  /* GPIOX_12 */</div><div class='add'>+		"PIN_10", /* GPIOX_13 */</div><div class='add'>+		"PIN_29", /* GPIOX_14 */</div><div class='add'>+		"PIN_31", /* GPIOX_15 */</div><div class='add'>+		"PIN_12", /* GPIOX_16 */</div><div class='add'>+		"PIN_3",  /* GPIOX_17 */</div><div class='add'>+		"PIN_5",  /* GPIOX_18 */</div><div class='add'>+		"PIN_36"; /* GPIOX_19 */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c3_sda_a_pins&gt;, &lt;&amp;i2c3_sck_a_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	rtc: rtc@51 {</div><div class='add'>+		compatible = "nxp,pcf8563";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		wakeup-source;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ir {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;remote_input_ao_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	linux,rc-map-name = "rc-odroid";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * EMMC_D4, EMMC_D5, EMMC_D6 and EMMC_D7 pins are shared between SPI NOR pins</div><div class='add'>+ * and eMMC Data 4 to 7 pins.</div><div class='add'>+ * Replace emmc_data_8b_pins to emmc_data_4b_pins from sd_emmc_c pinctrl-0,</div><div class='add'>+ * and change bus-width to 4 then spifc can be enabled.</div><div class='add'>+ * The SW1 slide should also be set to the correct position.</div><div class='add'>+ */</div><div class='add'>+&amp;spifc {</div><div class='add'>+	status = "disabled";</div><div class='add'>+	pinctrl-0 = &lt;&amp;nor_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	mx25u64: flash@0 {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		compatible = "mxicy,mx25u6435f", "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;104000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;toacodec {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb {</div><div class='add'>+	vbus-supply = &lt;&amp;usb_pwr_en&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb2_phy1 {</div><div class='add'>+	/* Enable the hub which is connected to this port */</div><div class='add'>+	phy-supply = &lt;&amp;hub_5v&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2l.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2l.dts<br/>new file mode 100644<br/>index 000000000000..1b9097a30251<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2l.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2l.dts</a></div><div class='hunk'>@@ -0,0 +1,128 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2022 Dongjin Kim &lt;tobetter@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+/* The Amlogic S922X Rev. C supports the same OPPs as the A311D variant */</div><div class='add'>+#include "meson-g12b-a311d.dtsi"</div><div class='add'>+#include "meson-g12b-odroid.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "hardkernel,odroid-n2l", "amlogic,s922x", "amlogic,g12b";</div><div class='add'>+	model = "Hardkernel ODROID-N2L";</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "amlogic,axg-sound-card";</div><div class='add'>+		model = "ODROID-N2L";</div><div class='add'>+		audio-aux-devs = &lt;&amp;tdmout_b&gt;, &lt;&amp;tdmin_a&gt;, &lt;&amp;tdmin_b&gt;,</div><div class='add'>+				 &lt;&amp;tdmin_c&gt;, &lt;&amp;tdmin_lb&gt;;</div><div class='add'>+		audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",</div><div class='add'>+				"TDMOUT_B IN 1", "FRDDR_B OUT 1",</div><div class='add'>+				"TDMOUT_B IN 2", "FRDDR_C OUT 1",</div><div class='add'>+				"TDM_B Playback", "TDMOUT_B OUT",</div><div class='add'>+				"TDMIN_A IN 4", "TDM_B Loopback",</div><div class='add'>+				"TDMIN_B IN 4", "TDM_B Loopback",</div><div class='add'>+				"TDMIN_C IN 4", "TDM_B Loopback",</div><div class='add'>+				"TDMIN_LB IN 1", "TDM_B Loopback",</div><div class='add'>+				"TODDR_A IN 0", "TDMIN_A OUT",</div><div class='add'>+				"TODDR_B IN 0", "TDMIN_A OUT",</div><div class='add'>+				"TODDR_C IN 0", "TDMIN_A OUT",</div><div class='add'>+				"TODDR_A IN 1", "TDMIN_B OUT",</div><div class='add'>+				"TODDR_B IN 1", "TDMIN_B OUT",</div><div class='add'>+				"TODDR_C IN 1", "TDMIN_B OUT",</div><div class='add'>+				"TODDR_A IN 2", "TDMIN_C OUT",</div><div class='add'>+				"TODDR_B IN 2", "TDMIN_C OUT",</div><div class='add'>+				"TODDR_C IN 2", "TDMIN_C OUT",</div><div class='add'>+				"TODDR_A IN 6", "TDMIN_LB OUT",</div><div class='add'>+				"TODDR_B IN 6", "TDMIN_LB OUT",</div><div class='add'>+				"TODDR_C IN 6", "TDMIN_LB OUT";</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;294912000&gt;,</div><div class='add'>+				       &lt;270950400&gt;,</div><div class='add'>+				       &lt;393216000&gt;;</div><div class='add'>+</div><div class='add'>+		dai-link-0 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_a&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-1 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_b&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-2 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_c&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-3 {</div><div class='add'>+			sound-dai = &lt;&amp;toddr_a&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-4 {</div><div class='add'>+			sound-dai = &lt;&amp;toddr_b&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-5 {</div><div class='add'>+			sound-dai = &lt;&amp;toddr_c&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* 8ch hdmi interface */</div><div class='add'>+		dai-link-6 {</div><div class='add'>+			sound-dai = &lt;&amp;tdmif_b&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			dai-tdm-slot-tx-mask-0 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-1 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-2 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-3 = &lt;1 1&gt;;</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_IN_B&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* hdmi glue */</div><div class='add'>+		dai-link-7 {</div><div class='add'>+			sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eth_phy {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;vddcpu_a {</div><div class='add'>+	regulator-min-microvolt = &lt;680000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;1040000&gt;;</div><div class='add'>+</div><div class='add'>+	pwms = &lt;&amp;pwm_ab 0 1500 0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;vddcpu_b {</div><div class='add'>+	regulator-min-microvolt = &lt;680000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;1040000&gt;;</div><div class='add'>+</div><div class='add'>+	pwms = &lt;&amp;pwm_AO_cd 1 1500 0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb2_phy0 {</div><div class='add'>+	phy-supply = &lt;&amp;usb_pwr_en&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb2_phy1 {</div><div class='add'>+	phy-supply = &lt;&amp;usb_pwr_en&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid.dtsi<br/>new file mode 100644<br/>index 000000000000..3298d59833b6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12b-odroid.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-g12b-odroid.dtsi</a></div><div class='hunk'>@@ -0,0 +1,435 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2019 BayLibre, SAS</div><div class='add'>+ * Author: Neil Armstrong &lt;narmstrong@baylibre.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/meson-g12a-gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/meson-g12a-toacodec.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/meson-g12a-tohdmitx.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart_AO;</div><div class='add'>+		ethernet0 = &amp;ethmac;</div><div class='add'>+		rtc1 = &amp;vrtc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x0 0x0 0x40000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	emmc_pwrseq: emmc-pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-emmc";</div><div class='add'>+		reset-gpios = &lt;&amp;gpio BOOT_12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fan: gpio-fan {</div><div class='add'>+		compatible = "gpio-fan";</div><div class='add'>+		gpios = &lt;&amp;gpio_ao GPIOAO_10 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		/* Using Dummy Speed */</div><div class='add'>+		gpio-fan,speed-map = &lt;0 0&gt;, &lt;1 1&gt;;</div><div class='add'>+		#cooling-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-blue {</div><div class='add'>+			label = "n2:blue";</div><div class='add'>+			gpios = &lt;&amp;gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	tflash_vdd: regulator-tflash-vdd {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+</div><div class='add'>+		regulator-name = "TFLASH_VDD";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;gpio_ao GPIOAO_8 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	tf_io: gpio-regulator-tf-io {</div><div class='add'>+		compatible = "regulator-gpio";</div><div class='add'>+</div><div class='add'>+		regulator-name = "TF_IO";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+</div><div class='add'>+		gpios = &lt;&amp;gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		gpios-states = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		states = &lt;3300000 0&gt;,</div><div class='add'>+			 &lt;1800000 1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	flash_1v8: regulator-flash-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "FLASH_1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vcc_3v3&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	main_12v: regulator-main-12v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "12V";</div><div class='add'>+		regulator-min-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb_pwr_en: regulator-usb-pwr-en {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "USB_PWR_EN";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vcc_5v&gt;;</div><div class='add'>+</div><div class='add'>+		/* Connected to the microUSB port power enable */</div><div class='add'>+		gpio = &lt;&amp;gpio GPIOH_6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vcc_5v: regulator-vcc-5v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "5V";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		vin-supply = &lt;&amp;main_12v&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio GPIOH_8 GPIO_OPEN_DRAIN&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vcc_1v8: regulator-vcc-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCC_1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vcc_3v3&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vcc_3v3: regulator-vcc-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCC_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		/* FIXME: actually controlled by VDDCPU_B_EN */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddcpu_a: regulator-vddcpu-a {</div><div class='add'>+		/*</div><div class='add'>+		 * MP8756GD Regulator.</div><div class='add'>+		 */</div><div class='add'>+		compatible = "pwm-regulator";</div><div class='add'>+</div><div class='add'>+		regulator-name = "VDDCPU_A";</div><div class='add'>+		regulator-min-microvolt = &lt;721000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1022000&gt;;</div><div class='add'>+</div><div class='add'>+		pwm-supply = &lt;&amp;main_12v&gt;;</div><div class='add'>+</div><div class='add'>+		pwms = &lt;&amp;pwm_ab 0 1250 0&gt;;</div><div class='add'>+		pwm-dutycycle-range = &lt;100 0&gt;;</div><div class='add'>+</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddcpu_b: regulator-vddcpu-b {</div><div class='add'>+		/*</div><div class='add'>+		 * Silergy SY8120B1ABC Regulator.</div><div class='add'>+		 */</div><div class='add'>+		compatible = "pwm-regulator";</div><div class='add'>+</div><div class='add'>+		regulator-name = "VDDCPU_B";</div><div class='add'>+		regulator-min-microvolt = &lt;721000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1022000&gt;;</div><div class='add'>+</div><div class='add'>+		pwm-supply = &lt;&amp;main_12v&gt;;</div><div class='add'>+</div><div class='add'>+		pwms = &lt;&amp;pwm_AO_cd 1 1250 0&gt;;</div><div class='add'>+		pwm-dutycycle-range = &lt;100 0&gt;;</div><div class='add'>+</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddao_1v8: regulator-vddao-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDAO_1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddao_3v3: regulator-vddao-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDAO_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;main_12v&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdmi-connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		type = "a";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			hdmi_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_tx_tmds_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;arb {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cec_AO {</div><div class='add'>+	pinctrl-0 = &lt;&amp;cec_ao_a_h_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "disabled";</div><div class='add'>+	hdmi-phandle = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cecb_AO {</div><div class='add'>+	pinctrl-0 = &lt;&amp;cec_ao_b_h_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+	hdmi-phandle = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;clkc_audio {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu_b&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table_0&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPU_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu1 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu_b&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table_0&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPU_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu100 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu_a&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpub_opp_table_1&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPUB_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu101 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu_a&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpub_opp_table_1&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPUB_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu102 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu_a&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpub_opp_table_1&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPUB_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu103 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu_a&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpub_opp_table_1&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPUB_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu_thermal {</div><div class='add'>+	trips {</div><div class='add'>+		cpu_active: cpu-active {</div><div class='add'>+			temperature = &lt;60000&gt;; /* millicelsius */</div><div class='add'>+			hysteresis = &lt;2000&gt;; /* millicelsius */</div><div class='add'>+			type = "active";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cooling-maps {</div><div class='add'>+		map {</div><div class='add'>+			trip = &lt;&amp;cpu_active&gt;;</div><div class='add'>+			cooling-device = &lt;&amp;fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ddr_thermal {</div><div class='add'>+	trips {</div><div class='add'>+		ddr_active: ddr-active {</div><div class='add'>+			temperature = &lt;60000&gt;; /* millicelsius */</div><div class='add'>+			hysteresis = &lt;2000&gt;; /* millicelsius */</div><div class='add'>+			type = "active";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cooling-maps {</div><div class='add'>+		map {</div><div class='add'>+			trip = &lt;&amp;ddr_active&gt;;</div><div class='add'>+			cooling-device = &lt;&amp;fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;hdmitx_hpd_pins&gt;, &lt;&amp;hdmitx_ddc_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	hdmi-supply = &lt;&amp;vcc_5v&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx_tmds_port {</div><div class='add'>+	hdmi_tx_tmds_out: endpoint {</div><div class='add'>+		remote-endpoint = &lt;&amp;hdmi_connector_in&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm_ab {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm_a_e_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm_AO_cd {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm_ao_d_e_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;saradc {</div><div class='add'>+	status = "okay";</div><div class='add'>+	vref-supply = &lt;&amp;vddao_1v8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SD card */</div><div class='add'>+&amp;sd_emmc_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdcard_c_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;sdcard_clk_gate_c_pins&gt;;</div><div class='add'>+	pinctrl-names = "default", "clk-gate";</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	max-frequency = &lt;50000000&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+</div><div class='add'>+	cd-gpios = &lt;&amp;gpio GPIOC_6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;tflash_vdd&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;tf_io&gt;;</div><div class='add'>+</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* eMMC */</div><div class='add'>+&amp;sd_emmc_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;emmc_ctrl_pins&gt;, &lt;&amp;emmc_data_8b_pins&gt;, &lt;&amp;emmc_ds_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;emmc_clk_gate_pins&gt;;</div><div class='add'>+	pinctrl-names = "default", "clk-gate";</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	cap-mmc-highspeed;</div><div class='add'>+	mmc-ddr-1_8v;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+</div><div class='add'>+	mmc-pwrseq = &lt;&amp;emmc_pwrseq&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;vcc_3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;flash_1v8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmif_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmif_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmin_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmin_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmin_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmin_lb {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmout_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmout_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tohdmitx {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;toddr_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;toddr_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;toddr_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart_AO {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart_ao_a_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb2_phy0 {</div><div class='add'>+	phy-supply = &lt;&amp;vcc_5v&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts<br/>new file mode 100644<br/>index 000000000000..1e5c6f984945<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts</a></div><div class='hunk'>@@ -0,0 +1,503 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2019 BayLibre, SAS</div><div class='add'>+ * Author: Neil Armstrong &lt;narmstrong@baylibre.com&gt;</div><div class='add'>+ * Copyright (c) 2019 Christian Hewitt &lt;christianshewitt@gmail.com&gt;</div><div class='add'>+ * Copyright (c) 2022 Radxa Limited</div><div class='add'>+ * Author: Yuntian Zhang &lt;yt@radxa.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "meson-g12b-a311d.dtsi"</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/meson-g12a-gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/meson-g12a-tohdmitx.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "radxa,zero2", "amlogic,a311d", "amlogic,g12b";</div><div class='add'>+	model = "Radxa Zero2";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart_AO;</div><div class='add'>+		serial2 = &amp;uart_A;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x0 0x0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fan0: pwm-fan {</div><div class='add'>+		compatible = "pwm-fan";</div><div class='add'>+		#cooling-cells = &lt;2&gt;;</div><div class='add'>+		cooling-levels = &lt;0 64 128 192 255&gt;;</div><div class='add'>+		pwms = &lt;&amp;pwm_AO_ab 0 40000 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys-polled {</div><div class='add'>+		compatible = "gpio-keys-polled";</div><div class='add'>+		poll-interval = &lt;100&gt;;</div><div class='add'>+		power-button {</div><div class='add'>+			label = "power";</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio_ao GPIOAO_3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-green {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			gpios = &lt;&amp;gpio GPIOA_12 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdmi-connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		type = "a";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			hdmi_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_tx_tmds_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	emmc_pwrseq: emmc-pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-emmc";</div><div class='add'>+		reset-gpios = &lt;&amp;gpio BOOT_12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdio_pwrseq: sdio-pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-simple";</div><div class='add'>+		reset-gpios = &lt;&amp;gpio GPIOX_6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		clocks = &lt;&amp;wifi32k&gt;;</div><div class='add'>+		clock-names = "ext_clock";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ao_5v: regulator-ao-5v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "AO_5V";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vcc_1v8: regulator-vcc-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCC_1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vcc_3v3&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vcc_3v3: regulator-vcc-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCC_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		/* FIXME: actually controlled by VDDCPU_B_EN */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddao_1v8: regulator-vddao-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDIO_AO1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddao_3v3: regulator-vddao-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDAO_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;ao_5v&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddcpu_a: regulator-vddcpu-a {</div><div class='add'>+		/*</div><div class='add'>+		 * MP8756GD Regulator.</div><div class='add'>+		 */</div><div class='add'>+		compatible = "pwm-regulator";</div><div class='add'>+</div><div class='add'>+		regulator-name = "VDDCPU_A";</div><div class='add'>+		regulator-min-microvolt = &lt;730000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1022000&gt;;</div><div class='add'>+</div><div class='add'>+		pwm-supply = &lt;&amp;ao_5v&gt;;</div><div class='add'>+</div><div class='add'>+		pwms = &lt;&amp;pwm_ab 0 1250 0&gt;;</div><div class='add'>+		pwm-dutycycle-range = &lt;100 0&gt;;</div><div class='add'>+</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddcpu_b: regulator-vddcpu-b {</div><div class='add'>+		/*</div><div class='add'>+		 * Silergy SY8120B1ABC Regulator.</div><div class='add'>+		 */</div><div class='add'>+		compatible = "pwm-regulator";</div><div class='add'>+</div><div class='add'>+		regulator-name = "VDDCPU_B";</div><div class='add'>+		regulator-min-microvolt = &lt;730000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1022000&gt;;</div><div class='add'>+</div><div class='add'>+		pwm-supply = &lt;&amp;ao_5v&gt;;</div><div class='add'>+</div><div class='add'>+		pwms = &lt;&amp;pwm_AO_cd 1 1250 0&gt;;</div><div class='add'>+		pwm-dutycycle-range = &lt;100 0&gt;;</div><div class='add'>+</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "amlogic,axg-sound-card";</div><div class='add'>+		model = "RADXA-ZERO2";</div><div class='add'>+		audio-aux-devs = &lt;&amp;tdmout_b&gt;;</div><div class='add'>+		audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",</div><div class='add'>+				"TDMOUT_B IN 1", "FRDDR_B OUT 1",</div><div class='add'>+				"TDMOUT_B IN 2", "FRDDR_C OUT 1",</div><div class='add'>+				"TDM_B Playback", "TDMOUT_B OUT";</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;294912000&gt;,</div><div class='add'>+				       &lt;270950400&gt;,</div><div class='add'>+				       &lt;393216000&gt;;</div><div class='add'>+</div><div class='add'>+		dai-link-0 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_a&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-1 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_b&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-2 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_c&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* 8ch hdmi interface */</div><div class='add'>+		dai-link-3 {</div><div class='add'>+			sound-dai = &lt;&amp;tdmif_b&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			dai-tdm-slot-tx-mask-0 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-1 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-2 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-3 = &lt;1 1&gt;;</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_IN_B&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* hdmi glue */</div><div class='add'>+		dai-link-4 {</div><div class='add'>+			sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wifi32k: clock-0 {</div><div class='add'>+		compatible = "pwm-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;32768&gt;;</div><div class='add'>+		pwms = &lt;&amp;pwm_ef 0 30518 0&gt;; /* PWM_E at 32.768KHz */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;arb {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cec_AO {</div><div class='add'>+	pinctrl-0 = &lt;&amp;cec_ao_a_h_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "disabled";</div><div class='add'>+	hdmi-phandle = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cecb_AO {</div><div class='add'>+	pinctrl-0 = &lt;&amp;cec_ao_b_h_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+	hdmi-phandle = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;clkc_audio {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu_b&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table_0&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPU_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu1 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu_b&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table_0&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPU_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu100 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu_a&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpub_opp_table_1&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPUB_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu101 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu_a&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpub_opp_table_1&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPUB_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu102 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu_a&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpub_opp_table_1&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPUB_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu103 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu_a&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpub_opp_table_1&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPUB_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu_thermal {</div><div class='add'>+	trips {</div><div class='add'>+		cpu_active: cpu-active {</div><div class='add'>+			temperature = &lt;70000&gt;; /* millicelsius */</div><div class='add'>+			hysteresis = &lt;2000&gt;; /* millicelsius */</div><div class='add'>+			type = "active";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cooling-maps {</div><div class='add'>+		map2 {</div><div class='add'>+			trip = &lt;&amp;cpu_active&gt;;</div><div class='add'>+			cooling-device = &lt;&amp;fan0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		/* GPIOZ */</div><div class='add'>+		"PIN_27", "PIN_28", "PIN_7", "PIN_11", "PIN_13", "PIN_15", "PIN_18", "PIN_40",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		/* GPIOH */</div><div class='add'>+		"", "", "", "", "PIN_19", "PIN_21", "PIN_24", "PIN_23",</div><div class='add'>+		"",</div><div class='add'>+		/* BOOT */</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "EMMC_PWRSEQ", "", "", "",</div><div class='add'>+		/* GPIOC */</div><div class='add'>+		"", "", "", "", "", "", "SD_CD", "PIN_36",</div><div class='add'>+		/* GPIOA */</div><div class='add'>+		"PIN_32", "PIN_12", "PIN_35", "", "", "PIN_38", "", "",</div><div class='add'>+		"", "", "", "", "LED_GREEN", "PIN_31", "PIN_3", "PIN_5",</div><div class='add'>+		/* GPIOX */</div><div class='add'>+		"", "", "", "", "", "", "SDIO_PWRSEQ", "",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "BT_SHUTDOWN", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio_ao {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		/* GPIOAO */</div><div class='add'>+		"PIN_8", "PIN_10", "", "BTN_POWER", "", "", "", "PIN_29",</div><div class='add'>+		"PIN_33", "PIN_37", "FAN", "",</div><div class='add'>+		/* GPIOE */</div><div class='add'>+		"", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;hdmitx_hpd_pins&gt;, &lt;&amp;hdmitx_ddc_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	hdmi-supply = &lt;&amp;ao_5v&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx_tmds_port {</div><div class='add'>+	hdmi_tx_tmds_out: endpoint {</div><div class='add'>+		remote-endpoint = &lt;&amp;hdmi_connector_in&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ir {</div><div class='add'>+	status = "disabled";</div><div class='add'>+	pinctrl-0 = &lt;&amp;remote_input_ao_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm_ab {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm_a_e_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm_ef {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm_e_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm_AO_ab {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm_ao_a_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm_AO_cd {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm_ao_d_e_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;saradc {</div><div class='add'>+	status = "okay";</div><div class='add'>+	vref-supply = &lt;&amp;vddao_1v8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SDIO */</div><div class='add'>+&amp;sd_emmc_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdio_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;sdio_clk_gate_pins&gt;;</div><div class='add'>+	pinctrl-names = "default", "clk-gate";</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	max-frequency = &lt;100000000&gt;;</div><div class='add'>+</div><div class='add'>+	non-removable;</div><div class='add'>+	disable-wp;</div><div class='add'>+</div><div class='add'>+	/* WiFi firmware requires power to be kept while in suspend */</div><div class='add'>+	keep-power-in-suspend;</div><div class='add'>+</div><div class='add'>+	mmc-pwrseq = &lt;&amp;sdio_pwrseq&gt;;</div><div class='add'>+</div><div class='add'>+	vmmc-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;vddao_1v8&gt;;</div><div class='add'>+</div><div class='add'>+	brcmf: wifi@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		compatible = "brcm,bcm4329-fmac";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SD card */</div><div class='add'>+&amp;sd_emmc_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdcard_c_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;sdcard_clk_gate_c_pins&gt;;</div><div class='add'>+	pinctrl-names = "default", "clk-gate";</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	max-frequency = &lt;50000000&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+</div><div class='add'>+	cd-gpios = &lt;&amp;gpio GPIOC_6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* eMMC */</div><div class='add'>+&amp;sd_emmc_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;emmc_ctrl_pins&gt;, &lt;&amp;emmc_data_8b_pins&gt;, &lt;&amp;emmc_ds_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;emmc_clk_gate_pins&gt;;</div><div class='add'>+	pinctrl-names = "default", "clk-gate";</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	cap-mmc-highspeed;</div><div class='add'>+	mmc-ddr-1_8v;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+</div><div class='add'>+	mmc-pwrseq = &lt;&amp;emmc_pwrseq&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;vcc_3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;vcc_1v8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmif_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmout_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tohdmitx {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart_A {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart_a_pins&gt;, &lt;&amp;uart_a_cts_rts_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "brcm,bcm43438-bt";</div><div class='add'>+		shutdown-gpios = &lt;&amp;gpio GPIOX_17 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		max-speed = &lt;2000000&gt;;</div><div class='add'>+		clocks = &lt;&amp;wifi32k&gt;;</div><div class='add'>+		clock-names = "lpo";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart_AO {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart_ao_a_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-s922x-bananapi-m2s.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-s922x-bananapi-m2s.dts<br/>new file mode 100644<br/>index 000000000000..7f66f263a2ce<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12b-s922x-bananapi-m2s.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-g12b-s922x-bananapi-m2s.dts</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2023 Christian Hewitt &lt;christianshewitt@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "meson-g12b-s922x.dtsi"</div><div class='add'>+#include "meson-g12b-bananapi.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "bananapi,bpi-m2s", "amlogic,s922x", "amlogic,g12b";</div><div class='add'>+	model = "BananaPi M2S";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi<br/>index 046cc332d07f..19cad93a6889 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi</a></div><div class='hunk'>@@ -11,29 +11,10 @@</div><div class='ctx'> 		compatible = "operating-points-v2";</div><div class='ctx'> 		opp-shared;</div><div class='ctx'> </div><div class='del'>-		opp-100000000 {</div><div class='del'>-			opp-hz = /bits/ 64 &lt;100000000&gt;;</div><div class='del'>-			opp-microvolt = &lt;731000&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		opp-250000000 {</div><div class='del'>-			opp-hz = /bits/ 64 &lt;250000000&gt;;</div><div class='del'>-			opp-microvolt = &lt;731000&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		opp-500000000 {</div><div class='del'>-			opp-hz = /bits/ 64 &lt;500000000&gt;;</div><div class='del'>-			opp-microvolt = &lt;731000&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		opp-667000000 {</div><div class='del'>-			opp-hz = /bits/ 64 &lt;667000000&gt;;</div><div class='del'>-			opp-microvolt = &lt;731000&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='ctx'> 		opp-1000000000 {</div><div class='ctx'> 			opp-hz = /bits/ 64 &lt;1000000000&gt;;</div><div class='ctx'> 			opp-microvolt = &lt;731000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;50000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		opp-1200000000 {</div><div class='hunk'>@@ -65,35 +46,21 @@</div><div class='ctx'> 			opp-hz = /bits/ 64 &lt;1896000000&gt;;</div><div class='ctx'> 			opp-microvolt = &lt;981000&gt;;</div><div class='ctx'> 		};</div><div class='add'>+</div><div class='add'>+		opp-1992000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1992000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1001000&gt;;</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	cpub_opp_table_1: opp-table-1 {</div><div class='ctx'> 		compatible = "operating-points-v2";</div><div class='ctx'> 		opp-shared;</div><div class='ctx'> </div><div class='del'>-		opp-100000000 {</div><div class='del'>-			opp-hz = /bits/ 64 &lt;100000000&gt;;</div><div class='del'>-			opp-microvolt = &lt;751000&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		opp-250000000 {</div><div class='del'>-			opp-hz = /bits/ 64 &lt;250000000&gt;;</div><div class='del'>-			opp-microvolt = &lt;751000&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		opp-500000000 {</div><div class='del'>-			opp-hz = /bits/ 64 &lt;500000000&gt;;</div><div class='del'>-			opp-microvolt = &lt;751000&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		opp-667000000 {</div><div class='del'>-			opp-hz = /bits/ 64 &lt;667000000&gt;;</div><div class='del'>-			opp-microvolt = &lt;751000&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='ctx'> 		opp-1000000000 {</div><div class='ctx'> 			opp-hz = /bits/ 64 &lt;1000000000&gt;;</div><div class='ctx'> 			opp-microvolt = &lt;771000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;50000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		opp-1200000000 {</div><div class='hunk'>@@ -120,5 +87,15 @@</div><div class='ctx'> 			opp-hz = /bits/ 64 &lt;1704000000&gt;;</div><div class='ctx'> 			opp-microvolt = &lt;891000&gt;;</div><div class='ctx'> 		};</div><div class='add'>+</div><div class='add'>+		opp-1800000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1800000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;981000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1908000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1908000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1022000&gt;;</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-ugoos-am6.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-ugoos-am6.dts<br/>index 325e448eb09c..4c1a75b926ee 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12b-ugoos-am6.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12b-ugoos-am6.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12b-ugoos-am6.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-g12b-ugoos-am6.dts</a></div><div class='hunk'>@@ -7,208 +7,34 @@</div><div class='ctx'> </div><div class='ctx'> /dts-v1/;</div><div class='ctx'> </div><div class='del'>-#include "meson-g12b.dtsi"</div><div class='del'>-#include "meson-g12b-s922x.dtsi"</div><div class='del'>-#include &lt;dt-bindings/input/input.h&gt;</div><div class='del'>-#include &lt;dt-bindings/gpio/meson-g12a-gpio.h&gt;</div><div class='add'>+#include "meson-g12b-w400.dtsi"</div><div class='ctx'> #include &lt;dt-bindings/sound/meson-g12a-tohdmitx.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='del'>-	compatible = "ugoos,am6", "amlogic,g12b";</div><div class='add'>+	compatible = "ugoos,am6", "amlogic,s922x", "amlogic,g12b";</div><div class='ctx'> 	model = "Ugoos AM6";</div><div class='ctx'> </div><div class='del'>-	aliases {</div><div class='del'>-		serial0 = &amp;uart_AO;</div><div class='del'>-		ethernet0 = &amp;ethmac;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	chosen {</div><div class='del'>-		stdout-path = "serial0:115200n8";</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	memory@0 {</div><div class='del'>-		device_type = "memory";</div><div class='del'>-		reg = &lt;0x0 0x0 0x0 0x40000000&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	emmc_pwrseq: emmc-pwrseq {</div><div class='del'>-		compatible = "mmc-pwrseq-emmc";</div><div class='del'>-		reset-gpios = &lt;&amp;gpio BOOT_12 GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	sdio_pwrseq: sdio-pwrseq {</div><div class='del'>-		compatible = "mmc-pwrseq-simple";</div><div class='del'>-		reset-gpios = &lt;&amp;gpio GPIOX_6 GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-		clocks = &lt;&amp;wifi32k&gt;;</div><div class='del'>-		clock-names = "ext_clock";</div><div class='del'>-	};</div><div class='del'>-</div><div class='ctx'> 	spdif_dit: audio-codec-1 {</div><div class='ctx'> 		#sound-dai-cells = &lt;0&gt;;</div><div class='ctx'> 		compatible = "linux,spdif-dit";</div><div class='del'>-		status = "okay";</div><div class='ctx'> 		sound-name-prefix = "DIT";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	flash_1v8: regulator-flash_1v8 {</div><div class='del'>-		compatible = "regulator-fixed";</div><div class='del'>-		regulator-name = "FLASH_1V8";</div><div class='del'>-		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='del'>-		vin-supply = &lt;&amp;vcc_3v3&gt;;</div><div class='del'>-		regulator-always-on;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	main_12v: regulator-main_12v {</div><div class='del'>-		compatible = "regulator-fixed";</div><div class='del'>-		regulator-name = "12V";</div><div class='del'>-		regulator-min-microvolt = &lt;12000000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;12000000&gt;;</div><div class='del'>-		regulator-always-on;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	vcc_5v: regulator-vcc_5v {</div><div class='del'>-		compatible = "regulator-fixed";</div><div class='del'>-		regulator-name = "VCC_5V";</div><div class='del'>-		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='del'>-		vin-supply = &lt;&amp;main_12v&gt;;</div><div class='del'>-</div><div class='del'>-		gpio = &lt;&amp;gpio GPIOH_8 GPIO_OPEN_DRAIN&gt;;</div><div class='del'>-		enable-active-high;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	vcc_1v8: regulator-vcc_1v8 {</div><div class='del'>-		compatible = "regulator-fixed";</div><div class='del'>-		regulator-name = "VCC_1V8";</div><div class='del'>-		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='del'>-		vin-supply = &lt;&amp;vcc_3v3&gt;;</div><div class='del'>-		regulator-always-on;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	vcc_3v3: regulator-vcc_3v3 {</div><div class='del'>-		compatible = "regulator-fixed";</div><div class='del'>-		regulator-name = "VCC_3V3";</div><div class='del'>-		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='del'>-		vin-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='del'>-		regulator-always-on;</div><div class='del'>-		/* FIXME: actually controlled by VDDCPU_B_EN */</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	vddcpu_a: regulator-vddcpu-a {</div><div class='del'>-		/*</div><div class='del'>-		 * MP1653 Regulator.</div><div class='del'>-		 */</div><div class='del'>-		compatible = "pwm-regulator";</div><div class='del'>-</div><div class='del'>-		regulator-name = "VDDCPU_A";</div><div class='del'>-		regulator-min-microvolt = &lt;721000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;1022000&gt;;</div><div class='del'>-</div><div class='del'>-		vin-supply = &lt;&amp;main_12v&gt;;</div><div class='del'>-</div><div class='del'>-		pwms = &lt;&amp;pwm_ab 0 1250 0&gt;;</div><div class='del'>-		pwm-dutycycle-range = &lt;100 0&gt;;</div><div class='del'>-</div><div class='del'>-		regulator-boot-on;</div><div class='del'>-		regulator-always-on;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	vddcpu_b: regulator-vddcpu-b {</div><div class='del'>-		/*</div><div class='del'>-		 * MP1652 Regulator.</div><div class='del'>-		 */</div><div class='del'>-		compatible = "pwm-regulator";</div><div class='del'>-</div><div class='del'>-		regulator-name = "VDDCPU_B";</div><div class='del'>-		regulator-min-microvolt = &lt;721000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;1022000&gt;;</div><div class='del'>-</div><div class='del'>-		vin-supply = &lt;&amp;main_12v&gt;;</div><div class='del'>-</div><div class='del'>-		pwms = &lt;&amp;pwm_AO_cd 1 1250 0&gt;;</div><div class='del'>-		pwm-dutycycle-range = &lt;100 0&gt;;</div><div class='del'>-</div><div class='del'>-		regulator-boot-on;</div><div class='del'>-		regulator-always-on;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	usb1_pow: regulator-usb1-pow {</div><div class='del'>-		compatible = "regulator-fixed";</div><div class='del'>-		regulator-name = "USB1_POW";</div><div class='del'>-		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='del'>-		vin-supply = &lt;&amp;vcc_5v&gt;;</div><div class='del'>-</div><div class='del'>-		/* connected to SY6280A Power Switch */</div><div class='del'>-		gpio = &lt;&amp;gpio GPIOA_8 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-		enable-active-high;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	usb_pwr_en: regulator-usb-pwr-en {</div><div class='del'>-		compatible = "regulator-fixed";</div><div class='del'>-		regulator-name = "USB_PWR_EN";</div><div class='del'>-		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='del'>-		vin-supply = &lt;&amp;vcc_5v&gt;;</div><div class='del'>-</div><div class='del'>-		/* Connected to USB3 Type-A Port power enable */</div><div class='del'>-		gpio = &lt;&amp;gpio GPIOAO_7 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-		enable-active-high;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	vddao_1v8: regulator-vddao-1v8 {</div><div class='del'>-		compatible = "regulator-fixed";</div><div class='del'>-		regulator-name = "VDDAO_1V8";</div><div class='del'>-		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='del'>-		vin-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='del'>-		regulator-always-on;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	vddao_3v3: regulator-vddao-3v3 {</div><div class='del'>-		compatible = "regulator-fixed";</div><div class='del'>-		regulator-name = "VDDAO_3V3";</div><div class='del'>-		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='del'>-		vin-supply = &lt;&amp;main_12v&gt;;</div><div class='del'>-		regulator-always-on;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	cvbs-connector {</div><div class='del'>-		compatible = "composite-video-connector";</div><div class='del'>-</div><div class='del'>-		port {</div><div class='del'>-			cvbs_connector_in: endpoint {</div><div class='del'>-				remote-endpoint = &lt;&amp;cvbs_vdac_out&gt;;</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	hdmi-connector {</div><div class='del'>-		compatible = "hdmi-connector";</div><div class='del'>-		type = "a";</div><div class='del'>-</div><div class='del'>-		port {</div><div class='del'>-			hdmi_connector_in: endpoint {</div><div class='del'>-				remote-endpoint = &lt;&amp;hdmi_tx_tmds_out&gt;;</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='ctx'> 	sound {</div><div class='ctx'> 		compatible = "amlogic,axg-sound-card";</div><div class='del'>-		model = "G12B-UGOOS-AM6";</div><div class='add'>+		model = "UGOOS-AM6";</div><div class='ctx'> 		audio-aux-devs = &lt;&amp;tdmout_b&gt;;</div><div class='ctx'> 		audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",</div><div class='ctx'> 				"TDMOUT_B IN 1", "FRDDR_B OUT 1",</div><div class='ctx'> 				"TDMOUT_B IN 2", "FRDDR_C OUT 1",</div><div class='ctx'> 				"TDM_B Playback", "TDMOUT_B OUT",</div><div class='del'>-				"SPDIFOUT IN 0", "FRDDR_A OUT 3",</div><div class='del'>-				"SPDIFOUT IN 1", "FRDDR_B OUT 3",</div><div class='del'>-				"SPDIFOUT IN 2", "FRDDR_C OUT 3";</div><div class='add'>+				"SPDIFOUT_A IN 0", "FRDDR_A OUT 3",</div><div class='add'>+				"SPDIFOUT_A IN 1", "FRDDR_B OUT 3",</div><div class='add'>+				"SPDIFOUT_A IN 2", "FRDDR_C OUT 3";</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='ctx'> </div><div class='ctx'> 		assigned-clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='ctx'> 				  &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='hunk'>@@ -217,7 +43,6 @@</div><div class='ctx'> 		assigned-clock-rates = &lt;294912000&gt;,</div><div class='ctx'> 				       &lt;270950400&gt;,</div><div class='ctx'> 				       &lt;393216000&gt;;</div><div class='del'>-		status = "okay";</div><div class='ctx'> </div><div class='ctx'> 		dai-link-0 {</div><div class='ctx'> 			sound-dai = &lt;&amp;frddr_a&gt;;</div><div class='hunk'>@@ -248,7 +73,7 @@</div><div class='ctx'> </div><div class='ctx'> 		/* spdif hdmi or toslink interface */</div><div class='ctx'> 		dai-link-4 {</div><div class='del'>-			sound-dai = &lt;&amp;spdifout&gt;;</div><div class='add'>+			sound-dai = &lt;&amp;spdifout_a&gt;;</div><div class='ctx'> </div><div class='ctx'> 			codec-0 {</div><div class='ctx'> 				sound-dai = &lt;&amp;spdif_dit&gt;;</div><div class='hunk'>@@ -277,110 +102,16 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='del'>-</div><div class='del'>-	wifi32k: wifi32k {</div><div class='del'>-		compatible = "pwm-clock";</div><div class='del'>-		#clock-cells = &lt;0&gt;;</div><div class='del'>-		clock-frequency = &lt;32768&gt;;</div><div class='del'>-		pwms = &lt;&amp;pwm_ef 0 30518 0&gt;; /* PWM_E at 32.768KHz */</div><div class='del'>-	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;arb {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;cec_AO {</div><div class='del'>-	pinctrl-0 = &lt;&amp;cec_ao_a_h_pins&gt;;</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-	status = "disabled";</div><div class='del'>-	hdmi-phandle = &lt;&amp;hdmi_tx&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;cecb_AO {</div><div class='del'>-	pinctrl-0 = &lt;&amp;cec_ao_b_h_pins&gt;;</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-	status = "okay";</div><div class='del'>-	hdmi-phandle = &lt;&amp;hdmi_tx&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> &amp;clkc_audio {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;cpu0 {</div><div class='del'>-	cpu-supply = &lt;&amp;vddcpu_b&gt;;</div><div class='del'>-	operating-points-v2 = &lt;&amp;cpu_opp_table_0&gt;;</div><div class='del'>-	clocks = &lt;&amp;clkc CLKID_CPU_CLK&gt;;</div><div class='del'>-	clock-latency = &lt;50000&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;cpu1 {</div><div class='del'>-	cpu-supply = &lt;&amp;vddcpu_b&gt;;</div><div class='del'>-	operating-points-v2 = &lt;&amp;cpu_opp_table_0&gt;;</div><div class='del'>-	clocks = &lt;&amp;clkc CLKID_CPU_CLK&gt;;</div><div class='del'>-	clock-latency = &lt;50000&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;cpu100 {</div><div class='del'>-	cpu-supply = &lt;&amp;vddcpu_a&gt;;</div><div class='del'>-	operating-points-v2 = &lt;&amp;cpub_opp_table_1&gt;;</div><div class='del'>-	clocks = &lt;&amp;clkc CLKID_CPUB_CLK&gt;;</div><div class='del'>-	clock-latency = &lt;50000&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;cpu101 {</div><div class='del'>-	cpu-supply = &lt;&amp;vddcpu_a&gt;;</div><div class='del'>-	operating-points-v2 = &lt;&amp;cpub_opp_table_1&gt;;</div><div class='del'>-	clocks = &lt;&amp;clkc CLKID_CPUB_CLK&gt;;</div><div class='del'>-	clock-latency = &lt;50000&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;cpu102 {</div><div class='del'>-	cpu-supply = &lt;&amp;vddcpu_a&gt;;</div><div class='del'>-	operating-points-v2 = &lt;&amp;cpub_opp_table_1&gt;;</div><div class='del'>-	clocks = &lt;&amp;clkc CLKID_CPUB_CLK&gt;;</div><div class='del'>-	clock-latency = &lt;50000&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;cpu103 {</div><div class='del'>-	cpu-supply = &lt;&amp;vddcpu_a&gt;;</div><div class='del'>-	operating-points-v2 = &lt;&amp;cpub_opp_table_1&gt;;</div><div class='del'>-	clocks = &lt;&amp;clkc CLKID_CPUB_CLK&gt;;</div><div class='del'>-	clock-latency = &lt;50000&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;cvbs_vdac_port {</div><div class='del'>-	cvbs_vdac_out: endpoint {</div><div class='del'>-		remote-endpoint = &lt;&amp;cvbs_connector_in&gt;;</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;ext_mdio {</div><div class='del'>-	external_phy: ethernet-phy@0 {</div><div class='del'>-		/* Realtek RTL8211F (0x001cc916) */</div><div class='del'>-		reg = &lt;0&gt;;</div><div class='del'>-		max-speed = &lt;1000&gt;;</div><div class='del'>-</div><div class='del'>-		reset-assert-us = &lt;10000&gt;;</div><div class='del'>-		reset-deassert-us = &lt;30000&gt;;</div><div class='del'>-		reset-gpios = &lt;&amp;gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)&gt;;</div><div class='del'>-</div><div class='del'>-		interrupt-parent = &lt;&amp;gpio_intc&gt;;</div><div class='del'>-		/* MAC_INTR on GPIOZ_14 */</div><div class='del'>-		interrupts = &lt;26 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;ethmac {</div><div class='del'>-	pinctrl-0 = &lt;&amp;eth_pins&gt;, &lt;&amp;eth_rgmii_pins&gt;;</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-	status = "okay";</div><div class='del'>-	phy-mode = "rgmii";</div><div class='del'>-	phy-handle = &lt;&amp;external_phy&gt;;</div><div class='del'>-	amlogic,tx-delay-ns = &lt;2&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> &amp;frddr_a {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='hunk'>@@ -393,113 +124,11 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;hdmi_tx {</div><div class='del'>-	status = "okay";</div><div class='del'>-	pinctrl-0 = &lt;&amp;hdmitx_hpd_pins&gt;, &lt;&amp;hdmitx_ddc_pins&gt;;</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-	hdmi-supply = &lt;&amp;vcc_5v&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;hdmi_tx_tmds_port {</div><div class='del'>-	hdmi_tx_tmds_out: endpoint {</div><div class='del'>-		remote-endpoint = &lt;&amp;hdmi_connector_in&gt;;</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> &amp;ir {</div><div class='del'>-	status = "okay";</div><div class='del'>-	pinctrl-0 = &lt;&amp;remote_input_ao_pins&gt;;</div><div class='del'>-	pinctrl-names = "default";</div><div class='ctx'> 	linux,rc-map-name = "rc-khadas";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;pwm_ab {</div><div class='del'>-	pinctrl-0 = &lt;&amp;pwm_a_e_pins&gt;;</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-	clocks = &lt;&amp;xtal&gt;;</div><div class='del'>-	clock-names = "clkin0";</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;pwm_AO_cd {</div><div class='del'>-	pinctrl-0 = &lt;&amp;pwm_ao_d_e_pins&gt;;</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-	clocks = &lt;&amp;xtal&gt;;</div><div class='del'>-	clock-names = "clkin1";</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;pwm_ef {</div><div class='del'>-	pinctrl-0 = &lt;&amp;pwm_e_pins&gt;;</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-	clocks = &lt;&amp;xtal&gt;;</div><div class='del'>-	clock-names = "clkin0";</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-/* SDIO */</div><div class='del'>-&amp;sd_emmc_a {</div><div class='del'>-	status = "okay";</div><div class='del'>-	pinctrl-0 = &lt;&amp;sdio_pins&gt;;</div><div class='del'>-	pinctrl-1 = &lt;&amp;sdio_clk_gate_pins&gt;;</div><div class='del'>-	pinctrl-names = "default", "clk-gate";</div><div class='del'>-	#address-cells = &lt;1&gt;;</div><div class='del'>-	#size-cells = &lt;0&gt;;</div><div class='del'>-</div><div class='del'>-	bus-width = &lt;4&gt;;</div><div class='del'>-	cap-sd-highspeed;</div><div class='del'>-	sd-uhs-sdr50;</div><div class='del'>-	max-frequency = &lt;100000000&gt;;</div><div class='del'>-</div><div class='del'>-	non-removable;</div><div class='del'>-	disable-wp;</div><div class='del'>-</div><div class='del'>-	mmc-pwrseq = &lt;&amp;sdio_pwrseq&gt;;</div><div class='del'>-</div><div class='del'>-	vmmc-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='del'>-	vqmmc-supply = &lt;&amp;vddao_1v8&gt;;</div><div class='del'>-</div><div class='del'>-	brcmf: wifi@1 {</div><div class='del'>-		reg = &lt;1&gt;;</div><div class='del'>-		compatible = "brcm,bcm4329-fmac";</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-/* SD card */</div><div class='del'>-&amp;sd_emmc_b {</div><div class='del'>-	status = "okay";</div><div class='del'>-	pinctrl-0 = &lt;&amp;sdcard_c_pins&gt;;</div><div class='del'>-	pinctrl-1 = &lt;&amp;sdcard_clk_gate_c_pins&gt;;</div><div class='del'>-	pinctrl-names = "default", "clk-gate";</div><div class='del'>-</div><div class='del'>-	bus-width = &lt;4&gt;;</div><div class='del'>-	cap-sd-highspeed;</div><div class='del'>-	max-frequency = &lt;50000000&gt;;</div><div class='del'>-	disable-wp;</div><div class='del'>-</div><div class='del'>-	cd-gpios = &lt;&amp;gpio GPIOC_6 GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-	vmmc-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='del'>-	vqmmc-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-/* eMMC */</div><div class='del'>-&amp;sd_emmc_c {</div><div class='del'>-	status = "okay";</div><div class='del'>-	pinctrl-0 = &lt;&amp;emmc_ctrl_pins&gt;, &lt;&amp;emmc_data_8b_pins&gt;, &lt;&amp;emmc_ds_pins&gt;;</div><div class='del'>-	pinctrl-1 = &lt;&amp;emmc_clk_gate_pins&gt;;</div><div class='del'>-	pinctrl-names = "default", "clk-gate";</div><div class='del'>-</div><div class='del'>-	bus-width = &lt;8&gt;;</div><div class='del'>-	cap-mmc-highspeed;</div><div class='del'>-	max-frequency = &lt;100000000&gt;;</div><div class='del'>-	disable-wp;</div><div class='del'>-</div><div class='del'>-	mmc-pwrseq = &lt;&amp;emmc_pwrseq&gt;;</div><div class='del'>-	vmmc-supply = &lt;&amp;vcc_3v3&gt;;</div><div class='del'>-	vqmmc-supply = &lt;&amp;flash_1v8&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;spdifout {</div><div class='add'>+&amp;spdifout_a {</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;spdif_out_h_pins&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	status = "okay";</div><div class='hunk'>@@ -545,7 +174,7 @@</div><div class='ctx'> &amp;usb {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> 	dr_mode = "host";</div><div class='del'>-	vbus-regulator = &lt;&amp;usb_pwr_en&gt;;</div><div class='add'>+	vbus-supply = &lt;&amp;usb_pwr_en&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;usb2_phy0 {</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi<br/>new file mode 100644<br/>index 000000000000..9b6d780eada7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi</a></div><div class='hunk'>@@ -0,0 +1,413 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2019 BayLibre, SAS</div><div class='add'>+ * Author: Neil Armstrong &lt;narmstrong@baylibre.com&gt;</div><div class='add'>+ * Copyright (c) 2019 Christian Hewitt &lt;christianshewitt@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "meson-g12b.dtsi"</div><div class='add'>+#include "meson-g12b-s922x.dtsi"</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/meson-g12a-gpio.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart_AO;</div><div class='add'>+		ethernet0 = &amp;ethmac;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x0 0x0 0x40000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	emmc_pwrseq: emmc-pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-emmc";</div><div class='add'>+		reset-gpios = &lt;&amp;gpio BOOT_12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdio_pwrseq: sdio-pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-simple";</div><div class='add'>+		reset-gpios = &lt;&amp;gpio GPIOX_6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		clocks = &lt;&amp;wifi32k&gt;;</div><div class='add'>+		clock-names = "ext_clock";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	flash_1v8: regulator-flash-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "FLASH_1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vcc_3v3&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	main_12v: regulator-main-12v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "12V";</div><div class='add'>+		regulator-min-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vcc_5v: regulator-vcc-5v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCC_5V";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;main_12v&gt;;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;gpio GPIOH_8 GPIO_OPEN_DRAIN&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vcc_1v8: regulator-vcc-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCC_1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vcc_3v3&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vcc_3v3: regulator-vcc-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCC_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		/* FIXME: actually controlled by VDDCPU_B_EN */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddcpu_a: regulator-vddcpu-a {</div><div class='add'>+		/*</div><div class='add'>+		 * MP1653 Regulator.</div><div class='add'>+		 */</div><div class='add'>+		compatible = "pwm-regulator";</div><div class='add'>+</div><div class='add'>+		regulator-name = "VDDCPU_A";</div><div class='add'>+		regulator-min-microvolt = &lt;721000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1022000&gt;;</div><div class='add'>+</div><div class='add'>+		pwm-supply = &lt;&amp;main_12v&gt;;</div><div class='add'>+</div><div class='add'>+		pwms = &lt;&amp;pwm_ab 0 1250 0&gt;;</div><div class='add'>+		pwm-dutycycle-range = &lt;100 0&gt;;</div><div class='add'>+</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddcpu_b: regulator-vddcpu-b {</div><div class='add'>+		/*</div><div class='add'>+		 * MP1652 Regulator.</div><div class='add'>+		 */</div><div class='add'>+		compatible = "pwm-regulator";</div><div class='add'>+</div><div class='add'>+		regulator-name = "VDDCPU_B";</div><div class='add'>+		regulator-min-microvolt = &lt;721000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1022000&gt;;</div><div class='add'>+</div><div class='add'>+		pwm-supply = &lt;&amp;main_12v&gt;;</div><div class='add'>+</div><div class='add'>+		pwms = &lt;&amp;pwm_AO_cd 1 1250 0&gt;;</div><div class='add'>+		pwm-dutycycle-range = &lt;100 0&gt;;</div><div class='add'>+</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb1_pow: regulator-usb1-pow {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "USB1_POW";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vcc_5v&gt;;</div><div class='add'>+</div><div class='add'>+		/* connected to SY6280A Power Switch */</div><div class='add'>+		gpio = &lt;&amp;gpio GPIOA_8 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb_pwr_en: regulator-usb-pwr-en {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "USB_PWR_EN";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vcc_5v&gt;;</div><div class='add'>+</div><div class='add'>+		/* Connected to USB3 Type-A Port power enable */</div><div class='add'>+		gpio = &lt;&amp;gpio GPIOAO_7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddao_1v8: regulator-vddao-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDAO_1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddao_3v3: regulator-vddao-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDAO_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;main_12v&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cvbs-connector {</div><div class='add'>+		compatible = "composite-video-connector";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			cvbs_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;cvbs_vdac_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdmi-connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		type = "a";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			hdmi_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_tx_tmds_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wifi32k: wifi32k {</div><div class='add'>+		compatible = "pwm-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;32768&gt;;</div><div class='add'>+		pwms = &lt;&amp;pwm_ef 0 30518 0&gt;; /* PWM_E at 32.768KHz */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cec_AO {</div><div class='add'>+	pinctrl-0 = &lt;&amp;cec_ao_a_h_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "disabled";</div><div class='add'>+	hdmi-phandle = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cecb_AO {</div><div class='add'>+	pinctrl-0 = &lt;&amp;cec_ao_b_h_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+	hdmi-phandle = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu_b&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table_0&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPU_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu1 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu_b&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table_0&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPU_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu100 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu_a&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpub_opp_table_1&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPUB_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu101 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu_a&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpub_opp_table_1&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPUB_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu102 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu_a&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpub_opp_table_1&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPUB_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu103 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu_a&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpub_opp_table_1&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPUB_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cvbs_vdac_port {</div><div class='add'>+	cvbs_vdac_out: endpoint {</div><div class='add'>+		remote-endpoint = &lt;&amp;cvbs_connector_in&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ext_mdio {</div><div class='add'>+	external_phy: ethernet-phy@0 {</div><div class='add'>+		/* Realtek RTL8211F (0x001cc916) */</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		max-speed = &lt;1000&gt;;</div><div class='add'>+</div><div class='add'>+		reset-assert-us = &lt;10000&gt;;</div><div class='add'>+		reset-deassert-us = &lt;80000&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio_intc&gt;;</div><div class='add'>+		/* MAC_INTR on GPIOZ_14 */</div><div class='add'>+		interrupts = &lt;IRQID_GPIOZ_14 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethmac {</div><div class='add'>+	pinctrl-0 = &lt;&amp;eth_pins&gt;, &lt;&amp;eth_rgmii_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+	phy-mode = "rgmii";</div><div class='add'>+	phy-handle = &lt;&amp;external_phy&gt;;</div><div class='add'>+	amlogic,tx-delay-ns = &lt;2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;hdmitx_hpd_pins&gt;, &lt;&amp;hdmitx_ddc_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	hdmi-supply = &lt;&amp;vcc_5v&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx_tmds_port {</div><div class='add'>+	hdmi_tx_tmds_out: endpoint {</div><div class='add'>+		remote-endpoint = &lt;&amp;hdmi_connector_in&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ir {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;remote_input_ao_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm_ab {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm_a_e_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm_AO_cd {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm_ao_d_e_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm_ef {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm_e_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SDIO */</div><div class='add'>+&amp;sd_emmc_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdio_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;sdio_clk_gate_pins&gt;;</div><div class='add'>+	pinctrl-names = "default", "clk-gate";</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	max-frequency = &lt;100000000&gt;;</div><div class='add'>+</div><div class='add'>+	/* WiFi firmware requires power to be kept while in suspend */</div><div class='add'>+	keep-power-in-suspend;</div><div class='add'>+</div><div class='add'>+	non-removable;</div><div class='add'>+	disable-wp;</div><div class='add'>+</div><div class='add'>+	mmc-pwrseq = &lt;&amp;sdio_pwrseq&gt;;</div><div class='add'>+</div><div class='add'>+	vmmc-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;vddao_1v8&gt;;</div><div class='add'>+</div><div class='add'>+	brcmf: wifi@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		compatible = "brcm,bcm4329-fmac";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SD card */</div><div class='add'>+&amp;sd_emmc_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdcard_c_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;sdcard_clk_gate_c_pins&gt;;</div><div class='add'>+	pinctrl-names = "default", "clk-gate";</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	max-frequency = &lt;50000000&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+</div><div class='add'>+	cd-gpios = &lt;&amp;gpio GPIOC_6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* eMMC */</div><div class='add'>+&amp;sd_emmc_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;emmc_ctrl_pins&gt;, &lt;&amp;emmc_data_8b_pins&gt;, &lt;&amp;emmc_ds_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;emmc_clk_gate_pins&gt;;</div><div class='add'>+	pinctrl-names = "default", "clk-gate";</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	cap-mmc-highspeed;</div><div class='add'>+	max-frequency = &lt;100000000&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+</div><div class='add'>+	mmc-pwrseq = &lt;&amp;emmc_pwrseq&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;vcc_3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;flash_1v8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart_A {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart_a_pins&gt;, &lt;&amp;uart_a_cts_rts_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "brcm,bcm43438-bt";</div><div class='add'>+		shutdown-gpios = &lt;&amp;gpio GPIOX_17 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		max-speed = &lt;2000000&gt;;</div><div class='add'>+		clocks = &lt;&amp;wifi32k&gt;;</div><div class='add'>+		clock-names = "lpo";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart_AO {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart_ao_a_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb {</div><div class='add'>+	status = "okay";</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	vbus-supply = &lt;&amp;usb_pwr_en&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb2_phy0 {</div><div class='add'>+	phy-supply = &lt;&amp;usb1_pow&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb2_phy1 {</div><div class='add'>+	phy-supply = &lt;&amp;usb1_pow&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi<br/>index 6dbc3968045b..23358d94844c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-g12b.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-g12b.dtsi</a></div><div class='hunk'>@@ -49,7 +49,13 @@</div><div class='ctx'> 			reg = &lt;0x0 0x0&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			capacity-dmips-mhz = &lt;592&gt;;</div><div class='del'>-			next-level-cache = &lt;&amp;l2&gt;;</div><div class='add'>+			d-cache-line-size = &lt;32&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-sets = &lt;32&gt;;</div><div class='add'>+			i-cache-line-size = &lt;32&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-sets = &lt;32&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_l&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -59,7 +65,13 @@</div><div class='ctx'> 			reg = &lt;0x0 0x1&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			capacity-dmips-mhz = &lt;592&gt;;</div><div class='del'>-			next-level-cache = &lt;&amp;l2&gt;;</div><div class='add'>+			d-cache-line-size = &lt;32&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-sets = &lt;32&gt;;</div><div class='add'>+			i-cache-line-size = &lt;32&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-sets = &lt;32&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_l&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -69,7 +81,13 @@</div><div class='ctx'> 			reg = &lt;0x0 0x100&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='del'>-			next-level-cache = &lt;&amp;l2&gt;;</div><div class='add'>+			d-cache-line-size = &lt;32&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-sets = &lt;32&gt;;</div><div class='add'>+			i-cache-line-size = &lt;32&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-sets = &lt;32&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_b&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -79,7 +97,13 @@</div><div class='ctx'> 			reg = &lt;0x0 0x101&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='del'>-			next-level-cache = &lt;&amp;l2&gt;;</div><div class='add'>+			d-cache-line-size = &lt;32&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-sets = &lt;32&gt;;</div><div class='add'>+			i-cache-line-size = &lt;32&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-sets = &lt;32&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_b&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -89,7 +113,13 @@</div><div class='ctx'> 			reg = &lt;0x0 0x102&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='del'>-			next-level-cache = &lt;&amp;l2&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			d-cache-sets = &lt;64&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			i-cache-sets = &lt;64&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_b&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -99,12 +129,32 @@</div><div class='ctx'> 			reg = &lt;0x0 0x103&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='del'>-			next-level-cache = &lt;&amp;l2&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			d-cache-sets = &lt;64&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			i-cache-sets = &lt;64&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_b&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		l2: l2-cache0 {</div><div class='add'>+		l2_cache_l: l2-cache-cluster0 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x40000&gt;;  /* L2. 256 KB */</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;512&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_cache_b: l2-cache-cluster1 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x100000&gt;; /* L2. 1MB */</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;512&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='hunk'>@@ -113,3 +163,37 @@</div><div class='ctx'> 	compatible = "amlogic,g12b-clkc";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;cpu_thermal {</div><div class='add'>+	cooling-maps {</div><div class='add'>+		map0 {</div><div class='add'>+			trip = &lt;&amp;cpu_passive&gt;;</div><div class='add'>+			cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+					 &lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+					 &lt;&amp;cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+					 &lt;&amp;cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+					 &lt;&amp;cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+					 &lt;&amp;cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+		};</div><div class='add'>+		map1 {</div><div class='add'>+			trip = &lt;&amp;cpu_hot&gt;;</div><div class='add'>+			cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+					 &lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+					 &lt;&amp;cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+					 &lt;&amp;cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+					 &lt;&amp;cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+					 &lt;&amp;cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mali {</div><div class='add'>+	dma-coherent;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pmu {</div><div class='add'>+	compatible = "amlogic,g12b-ddr-pmu";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;npu {</div><div class='add'>+	power-domains = &lt;&amp;pwrc PWRC_G12A_NNA_ID&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi<br/>index 248b018c83d5..2da49cfbde77 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi</a></div><div class='hunk'>@@ -8,6 +8,7 @@</div><div class='ctx'> </div><div class='ctx'> #include &lt;dt-bindings/input/input.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/meson-aiu.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	adc-keys {</div><div class='hunk'>@@ -16,7 +17,7 @@</div><div class='ctx'> 		io-channel-names = "buttons";</div><div class='ctx'> 		keyup-threshold-microvolt = &lt;1800000&gt;;</div><div class='ctx'> </div><div class='del'>-		update-button {</div><div class='add'>+		button-update {</div><div class='ctx'> 			label = "update";</div><div class='ctx'> 			linux,code = &lt;KEY_VENDOR&gt;;</div><div class='ctx'> 			press-threshold-microvolt = &lt;1300000&gt;;</div><div class='hunk'>@@ -29,6 +30,13 @@</div><div class='ctx'> 		spi0 = &amp;spifc;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	dio2133: analog-amplifier {</div><div class='add'>+		compatible = "simple-audio-amplifier";</div><div class='add'>+		sound-name-prefix = "AU2";</div><div class='add'>+		VCC-supply = &lt;&amp;vcc5v&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;gpio GPIOH_5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	chosen {</div><div class='ctx'> 		stdout-path = "serial0:115200n8";</div><div class='ctx'> 	};</div><div class='hunk'>@@ -76,7 +84,7 @@</div><div class='ctx'> 		reg = &lt;0x0 0x0 0x0 0x80000000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	ao_5v: regulator-ao_5v {</div><div class='add'>+	ao_5v: regulator-ao-5v {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "AO_5V";</div><div class='ctx'> 		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='hunk'>@@ -85,7 +93,7 @@</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	dc_in: regulator-dc_in {</div><div class='add'>+	dc_in: regulator-dc-in {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "DC_IN";</div><div class='ctx'> 		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='hunk'>@@ -96,14 +104,14 @@</div><div class='ctx'> 	leds {</div><div class='ctx'> 		compatible = "gpio-leds";</div><div class='ctx'> </div><div class='del'>-		green {</div><div class='add'>+		led-green {</div><div class='ctx'> 			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='ctx'> 			function = LED_FUNCTION_DISK_ACTIVITY;</div><div class='ctx'> 			gpios = &lt;&amp;gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 			linux,default-trigger = "disk-activity";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		blue {</div><div class='add'>+		led-blue {</div><div class='ctx'> 			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='ctx'> 			function = LED_FUNCTION_STATUS;</div><div class='ctx'> 			gpios = &lt;&amp;gpio GPIODV_28 GPIO_ACTIVE_HIGH&gt;;</div><div class='hunk'>@@ -112,7 +120,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vcc_card: regulator-vcc_card {</div><div class='add'>+	vcc_card: regulator-vcc-card {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VCC_CARD";</div><div class='ctx'> 		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='hunk'>@@ -133,7 +141,7 @@</div><div class='ctx'> 		gpio = &lt;&amp;gpio GPIOH_3 GPIO_OPEN_DRAIN&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vddio_ao18: regulator-vddio_ao18 {</div><div class='add'>+	vddio_ao18: regulator-vddio-ao18 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VDDIO_AO18";</div><div class='ctx'> 		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='hunk'>@@ -142,7 +150,7 @@</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vddio_ao3v3: regulator-vddio_ao3v3 {</div><div class='add'>+	vddio_ao3v3: regulator-vddio-ao3v3 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VDDIO_AO3V3";</div><div class='ctx'> 		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='hunk'>@@ -151,7 +159,7 @@</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vddio_boot: regulator-vddio_boot {</div><div class='add'>+	vddio_boot: regulator-vddio-boot {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VDDIO_BOOT";</div><div class='ctx'> 		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='hunk'>@@ -175,6 +183,72 @@</div><div class='ctx'> 		regulator-settling-time-up-us = &lt;200&gt;;</div><div class='ctx'> 		regulator-settling-time-down-us = &lt;50000&gt;;</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "amlogic,gx-sound-card";</div><div class='add'>+		model = "LIBRETECH-PC";</div><div class='add'>+		audio-aux-devs = &lt;&amp;dio2133&gt;;</div><div class='add'>+		audio-widgets = "Speaker", "7J4-14 LEFT",</div><div class='add'>+				"Speaker", "7J4-11 RIGHT";</div><div class='add'>+		audio-routing = "AU2 INL", "ACODEC LOLN",</div><div class='add'>+				"AU2 INR", "ACODEC LORN",</div><div class='add'>+				"7J4-14 LEFT", "AU2 OUTL",</div><div class='add'>+				"7J4-11 RIGHT", "AU2 OUTR";</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL1&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;294912000&gt;,</div><div class='add'>+				       &lt;270950400&gt;,</div><div class='add'>+				       &lt;393216000&gt;;</div><div class='add'>+</div><div class='add'>+		dai-link-0 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_I2S_FIFO&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-1 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_I2S_ENCODER&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;aiu AIU_HDMI CTRL_I2S&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			codec-1 {</div><div class='add'>+				sound-dai = &lt;&amp;aiu AIU_ACODEC CTRL_I2S&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-2 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_HDMI CTRL_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-3 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_ACODEC CTRL_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;acodec&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;acodec {</div><div class='add'>+	AVDD-supply = &lt;&amp;vddio_ao18&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;aiu {</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cec_AO {</div><div class='hunk'>@@ -271,24 +345,18 @@</div><div class='ctx'> &amp;pwm_AO_ab {</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pwm_ao_a_3_pins&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='del'>-	clocks = &lt;&amp;clkc CLKID_FCLK_DIV4&gt;;</div><div class='del'>-	clock-names = "clkin0";</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;pwm_ab {</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pwm_b_pins&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='del'>-	clocks = &lt;&amp;clkc CLKID_FCLK_DIV4&gt;;</div><div class='del'>-	clock-names = "clkin0";</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;pwm_ef {</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pwm_e_pins&gt;, &lt;&amp;pwm_f_clk_pins&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='del'>-	clocks = &lt;&amp;clkc CLKID_FCLK_DIV4&gt;;</div><div class='del'>-	clock-names = "clkin0";</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -345,7 +413,7 @@</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='del'>-	gd25lq128: spi-flash@0 {</div><div class='add'>+	gd25lq128: flash@0 {</div><div class='ctx'> 		compatible = "jedec,spi-nor";</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;1&gt;;</div><div class='hunk'>@@ -360,8 +428,9 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;usb0 {</div><div class='add'>+&amp;usb {</div><div class='ctx'> 	status = "okay";</div><div class='add'>+	dr_mode = "host";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;usb2_phy0 {</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-mali450.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-mali450.dtsi<br/>new file mode 100644<br/>index 000000000000..f9771b51c852<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gx-mali450.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gx-mali450.dtsi</a></div><div class='hunk'>@@ -0,0 +1,61 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2017 BayLibre SAS</div><div class='add'>+ * Author: Neil Armstrong &lt;narmstrong@baylibre.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	gpu_opp_table: opp-table {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		opp-125000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;125000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;950000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-250000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;250000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;950000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-285714285 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;285714285&gt;;</div><div class='add'>+			opp-microvolt = &lt;950000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-400000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;400000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;950000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-500000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;500000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;950000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-666666666 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;666666666&gt;;</div><div class='add'>+			opp-microvolt = &lt;950000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-744000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;744000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;950000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;apb {</div><div class='add'>+	mali: gpu@c0000 {</div><div class='add'>+		compatible = "arm,mali-450";</div><div class='add'>+		reg = &lt;0x0 0xc0000 0x0 0x40000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-names = "gp", "gpmmu", "pp", "pmu",</div><div class='add'>+			"pp0", "ppmmu0", "pp1", "ppmmu1",</div><div class='add'>+			"pp2", "ppmmu2";</div><div class='add'>+		operating-points-v2 = &lt;&amp;gpu_opp_table&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi<br/>index 12d5e333e5f2..b4f88ed6273b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi</a></div><div class='hunk'>@@ -8,12 +8,27 @@</div><div class='ctx'>  * the pin-compatible S912 (GXM) or S905D (GXL) SoCs.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+#include &lt;dt-bindings/sound/meson-aiu.h&gt;</div><div class='add'>+</div><div class='ctx'> / {</div><div class='ctx'> 	aliases {</div><div class='ctx'> 		serial0 = &amp;uart_AO;</div><div class='ctx'> 		ethernet0 = &amp;ethmac;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	dio2133: analog-amplifier {</div><div class='add'>+		compatible = "simple-audio-amplifier";</div><div class='add'>+		sound-name-prefix = "AU2";</div><div class='add'>+		VCC-supply = &lt;&amp;hdmi_5v&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;gpio GPIOH_5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spdif_dit: audio-codec-0 {</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		compatible = "linux,spdif-dit";</div><div class='add'>+		sound-name-prefix = "DIT";</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	chosen {</div><div class='ctx'> 		stdout-path = "serial0:115200n8";</div><div class='ctx'> 	};</div><div class='hunk'>@@ -35,28 +50,28 @@</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vddio_ao18: regulator-vddio_ao18 {</div><div class='add'>+	vddio_ao18: regulator-vddio-ao18 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VDDIO_AO18";</div><div class='ctx'> 		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vddio_boot: regulator-vddio_boot {</div><div class='add'>+	vddio_boot: regulator-vddio-boot {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VDDIO_BOOT";</div><div class='ctx'> 		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vddao_3v3: regulator-vddao_3v3 {</div><div class='add'>+	vddao_3v3: regulator-vddao-3v3 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VDDAO_3V3";</div><div class='ctx'> 		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='ctx'> 		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vcc_3v3: regulator-vcc_3v3 {</div><div class='add'>+	vcc_3v3: regulator-vcc-3v3 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VCC_3V3";</div><div class='ctx'> 		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='hunk'>@@ -82,7 +97,7 @@</div><div class='ctx'> 		clock-names = "ext_clock";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	cvbs-connector {</div><div class='add'>+	cvbs_connector: cvbs-connector {</div><div class='ctx'> 		compatible = "composite-video-connector";</div><div class='ctx'> </div><div class='ctx'> 		port {</div><div class='hunk'>@@ -102,6 +117,87 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "amlogic,gx-sound-card";</div><div class='add'>+		model = "P230-Q200";</div><div class='add'>+		audio-aux-devs = &lt;&amp;dio2133&gt;;</div><div class='add'>+		audio-widgets = "Line", "Lineout";</div><div class='add'>+		audio-routing = "AU2 INL", "ACODEC LOLP",</div><div class='add'>+				"AU2 INR", "ACODEC LORP",</div><div class='add'>+				"AU2 INL", "ACODEC LOLN",</div><div class='add'>+				"AU2 INR", "ACODEC LORN",</div><div class='add'>+				"Lineout", "AU2 OUTL",</div><div class='add'>+				"Lineout", "AU2 OUTR";</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL1&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;294912000&gt;,</div><div class='add'>+				       &lt;270950400&gt;,</div><div class='add'>+				       &lt;393216000&gt;;</div><div class='add'>+		dai-link-0 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_I2S_FIFO&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-1 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_SPDIF_FIFO&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-2 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_I2S_ENCODER&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;aiu AIU_HDMI CTRL_I2S&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			codec-1 {</div><div class='add'>+				sound-dai = &lt;&amp;aiu AIU_ACODEC CTRL_I2S&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-3 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_SPDIF_ENCODER&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;spdif_dit&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-4 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_HDMI CTRL_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-5 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_ACODEC CTRL_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;acodec&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;acodec {</div><div class='add'>+	AVDD-supply = &lt;&amp;vddio_ao18&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;aiu {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;spdif_out_h_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cec_AO {</div><div class='hunk'>@@ -144,8 +240,6 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pwm_e_pins&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='del'>-	clocks = &lt;&amp;clkc CLKID_FCLK_DIV4&gt;;</div><div class='del'>-	clock-names = "clkin0";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;saradc {</div><div class='hunk'>@@ -223,6 +317,7 @@</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;usb0 {</div><div class='add'>+&amp;usb {</div><div class='ctx'> 	status = "okay";</div><div class='add'>+	dr_mode = "otg";</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi<br/>index 03f79fe045b7..c1d8e81d95cb 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gx.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gx.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gx.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gx.dtsi</a></div><div class='hunk'>@@ -12,6 +12,7 @@</div><div class='ctx'> #include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/power/meson-gxbb-power.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/thermal/thermal.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='hunk'>@@ -19,6 +20,12 @@</div><div class='ctx'> 	#address-cells = &lt;2&gt;;</div><div class='ctx'> 	#size-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='add'>+	aliases {</div><div class='add'>+		mmc0 = &amp;sd_emmc_b; /* SD card */</div><div class='add'>+		mmc1 = &amp;sd_emmc_c; /* eMMC */</div><div class='add'>+		mmc2 = &amp;sd_emmc_a; /* SDIO */</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	reserved-memory {</div><div class='ctx'> 		#address-cells = &lt;2&gt;;</div><div class='ctx'> 		#size-cells = &lt;2&gt;;</div><div class='hunk'>@@ -42,6 +49,12 @@</div><div class='ctx'> 			no-map;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		/* 32 MiB reserved for ARM Trusted Firmware (BL32) */</div><div class='add'>+		secmon_reserved_bl32: secmon@5300000 {</div><div class='add'>+			reg = &lt;0x0 0x05300000 0x0 0x2000000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		linux,cma {</div><div class='ctx'> 			compatible = "shared-dma-pool";</div><div class='ctx'> 			reusable;</div><div class='hunk'>@@ -60,7 +73,7 @@</div><div class='ctx'> 			compatible = "amlogic,simple-framebuffer",</div><div class='ctx'> 				     "simple-framebuffer";</div><div class='ctx'> 			amlogic,pipeline = "vpu-cvbs";</div><div class='del'>-			power-domains = &lt;&amp;pwrc_vpu&gt;;</div><div class='add'>+			power-domains = &lt;&amp;pwrc PWRC_GXBB_VPU_ID&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -68,7 +81,7 @@</div><div class='ctx'> 			compatible = "amlogic,simple-framebuffer",</div><div class='ctx'> 				     "simple-framebuffer";</div><div class='ctx'> 			amlogic,pipeline = "vpu-hdmi";</div><div class='del'>-			power-domains = &lt;&amp;pwrc_vpu&gt;;</div><div class='add'>+			power-domains = &lt;&amp;pwrc PWRC_GXBB_VPU_ID&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='hunk'>@@ -82,6 +95,12 @@</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			reg = &lt;0x0 0x0&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			d-cache-line-size = &lt;32&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-sets = &lt;32&gt;;</div><div class='add'>+			i-cache-line-size = &lt;32&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-sets = &lt;32&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;l2&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;scpi_dvfs 0&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='hunk'>@@ -92,6 +111,12 @@</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			reg = &lt;0x0 0x1&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			d-cache-line-size = &lt;32&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-sets = &lt;32&gt;;</div><div class='add'>+			i-cache-line-size = &lt;32&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-sets = &lt;32&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;l2&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;scpi_dvfs 0&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='hunk'>@@ -102,6 +127,12 @@</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			reg = &lt;0x0 0x2&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			d-cache-line-size = &lt;32&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-sets = &lt;32&gt;;</div><div class='add'>+			i-cache-line-size = &lt;32&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-sets = &lt;32&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;l2&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;scpi_dvfs 0&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='hunk'>@@ -112,6 +143,12 @@</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			reg = &lt;0x0 0x3&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			d-cache-line-size = &lt;32&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-sets = &lt;32&gt;;</div><div class='add'>+			i-cache-line-size = &lt;32&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-sets = &lt;32&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;l2&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;scpi_dvfs 0&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='hunk'>@@ -119,6 +156,11 @@</div><div class='ctx'> </div><div class='ctx'> 		l2: l2-cache0 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x80000&gt;; /* L2. 512 KB */</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;512&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -219,7 +261,7 @@</div><div class='ctx'> 			reg = &lt;0x14 0x10&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		eth_mac: eth_mac@34 {</div><div class='add'>+		eth_mac: eth-mac@34 {</div><div class='ctx'> 			reg = &lt;0x34 0x10&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -236,7 +278,7 @@</div><div class='ctx'> 		scpi_clocks: clocks {</div><div class='ctx'> 			compatible = "arm,scpi-clocks";</div><div class='ctx'> </div><div class='del'>-			scpi_dvfs: scpi_clocks@0 {</div><div class='add'>+			scpi_dvfs: clocks-0 {</div><div class='ctx'> 				compatible = "arm,scpi-dvfs-clocks";</div><div class='ctx'> 				#clock-cells = &lt;1&gt;;</div><div class='ctx'> 				clock-indices = &lt;0&gt;;</div><div class='hunk'>@@ -278,11 +320,23 @@</div><div class='ctx'> 				#reset-cells = &lt;1&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='add'>+			aiu: audio-controller@5400 {</div><div class='add'>+				compatible = "amlogic,aiu";</div><div class='add'>+				#sound-dai-cells = &lt;2&gt;;</div><div class='add'>+				sound-name-prefix = "AIU";</div><div class='add'>+				reg = &lt;0x0 0x5400 0x0 0x2ac&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 48 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					     &lt;GIC_SPI 50 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				interrupt-names = "i2s", "spdif";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='ctx'> 			uart_A: serial@84c0 {</div><div class='ctx'> 				compatible = "amlogic,meson-gx-uart";</div><div class='ctx'> 				reg = &lt;0x0 0x84c0 0x0 0x18&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 26 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='add'>+				fifo-size = &lt;128&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			uart_B: serial@84dc {</div><div class='hunk'>@@ -302,14 +356,14 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			pwm_ab: pwm@8550 {</div><div class='del'>-				compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";</div><div class='add'>+				compatible = "amlogic,meson-gxbb-pwm-v2", "amlogic,meson8-pwm-v2";</div><div class='ctx'> 				reg = &lt;0x0 0x08550 0x0 0x10&gt;;</div><div class='ctx'> 				#pwm-cells = &lt;3&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			pwm_cd: pwm@8650 {</div><div class='del'>-				compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";</div><div class='add'>+				compatible = "amlogic,meson-gxbb-pwm-v2", "amlogic,meson8-pwm-v2";</div><div class='ctx'> 				reg = &lt;0x0 0x08650 0x0 0x10&gt;;</div><div class='ctx'> 				#pwm-cells = &lt;3&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='hunk'>@@ -324,7 +378,7 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			pwm_ef: pwm@86c0 {</div><div class='del'>-				compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";</div><div class='add'>+				compatible = "amlogic,meson-gxbb-pwm-v2", "amlogic,meson8-pwm-v2";</div><div class='ctx'> 				reg = &lt;0x0 0x086c0 0x0 0x10&gt;;</div><div class='ctx'> 				#pwm-cells = &lt;3&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='hunk'>@@ -398,20 +452,20 @@</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		sram: sram@c8000000 {</div><div class='del'>-			compatible = "amlogic,meson-gx-sram", "amlogic,meson-gxbb-sram", "mmio-sram";</div><div class='add'>+			compatible = "mmio-sram";</div><div class='ctx'> 			reg = &lt;0x0 0xc8000000 0x0 0x14000&gt;;</div><div class='ctx'> </div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;1&gt;;</div><div class='ctx'> 			ranges = &lt;0 0x0 0xc8000000 0x14000&gt;;</div><div class='ctx'> </div><div class='del'>-			cpu_scp_lpri: scp-shmem@0 {</div><div class='del'>-				compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem";</div><div class='add'>+			cpu_scp_lpri: scp-sram@0 {</div><div class='add'>+				compatible = "amlogic,meson-gxbb-scp-shmem";</div><div class='ctx'> 				reg = &lt;0x13000 0x400&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			cpu_scp_hpri: scp-shmem@200 {</div><div class='del'>-				compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem";</div><div class='add'>+			cpu_scp_hpri: scp-sram@200 {</div><div class='add'>+				compatible = "amlogic,meson-gxbb-scp-shmem";</div><div class='ctx'> 				reg = &lt;0x13400 0x400&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='hunk'>@@ -425,13 +479,7 @@</div><div class='ctx'> </div><div class='ctx'> 			sysctrl_AO: sys-ctrl@0 {</div><div class='ctx'> 				compatible = "amlogic,meson-gx-ao-sysctrl", "simple-mfd", "syscon";</div><div class='del'>-				reg =  &lt;0x0 0x0 0x0 0x100&gt;;</div><div class='del'>-</div><div class='del'>-				pwrc_vpu: power-controller-vpu {</div><div class='del'>-					compatible = "amlogic,meson-gx-pwrc-vpu";</div><div class='del'>-					#power-domain-cells = &lt;0&gt;;</div><div class='del'>-					amlogic,hhi-sysctrl = &lt;&amp;sysctrl&gt;;</div><div class='del'>-				};</div><div class='add'>+				reg = &lt;0x0 0x0 0x0 0x100&gt;;</div><div class='ctx'> </div><div class='ctx'> 				clkc_AO: clock-controller {</div><div class='ctx'> 					compatible = "amlogic,meson-gx-aoclkc";</div><div class='hunk'>@@ -477,7 +525,7 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			pwm_AO_ab: pwm@550 {</div><div class='del'>-				compatible = "amlogic,meson-gx-ao-pwm", "amlogic,meson-gxbb-ao-pwm";</div><div class='add'>+				compatible = "amlogic,meson-gxbb-pwm-v2", "amlogic,meson8-pwm-v2";</div><div class='ctx'> 				reg = &lt;0x0 0x00550 0x0 0x10&gt;;</div><div class='ctx'> 				#pwm-cells = &lt;3&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='hunk'>@@ -512,7 +560,7 @@</div><div class='ctx'> 			#size-cells = &lt;2&gt;;</div><div class='ctx'> 			ranges = &lt;0x0 0x0 0x0 0xc8834000 0x0 0x2000&gt;;</div><div class='ctx'> </div><div class='del'>-			hwrng: rng {</div><div class='add'>+			hwrng: rng@0 {</div><div class='ctx'> 				compatible = "amlogic,meson-rng";</div><div class='ctx'> 				reg = &lt;0x0 0x0 0x0 0x4&gt;;</div><div class='ctx'> 			};</div><div class='hunk'>@@ -541,6 +589,12 @@</div><div class='ctx'> 			sysctrl: system-controller@0 {</div><div class='ctx'> 				compatible = "amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon";</div><div class='ctx'> 				reg = &lt;0 0 0 0x400&gt;;</div><div class='add'>+</div><div class='add'>+				pwrc: power-controller {</div><div class='add'>+					compatible = "amlogic,meson-gxbb-pwrc";</div><div class='add'>+					#power-domain-cells = &lt;1&gt;;</div><div class='add'>+					amlogic,ao-sysctrl = &lt;&amp;sysctrl_AO&gt;;</div><div class='add'>+				};</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			mailbox: mailbox@404 {</div><div class='hunk'>@@ -563,6 +617,7 @@</div><div class='ctx'> 			interrupt-names = "macirq";</div><div class='ctx'> 			rx-fifo-depth = &lt;4096&gt;;</div><div class='ctx'> 			tx-fifo-depth = &lt;2048&gt;;</div><div class='add'>+			power-domains = &lt;&amp;pwrc PWRC_GXBB_ETHERNET_MEM_ID&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -576,21 +631,21 @@</div><div class='ctx'> 			sd_emmc_a: mmc@70000 {</div><div class='ctx'> 				compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";</div><div class='ctx'> 				reg = &lt;0x0 0x70000 0x0 0x800&gt;;</div><div class='del'>-				interrupts = &lt;GIC_SPI 216 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			sd_emmc_b: mmc@72000 {</div><div class='ctx'> 				compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";</div><div class='ctx'> 				reg = &lt;0x0 0x72000 0x0 0x800&gt;;</div><div class='del'>-				interrupts = &lt;GIC_SPI 217 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			sd_emmc_c: mmc@74000 {</div><div class='ctx'> 				compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";</div><div class='ctx'> 				reg = &lt;0x0 0x74000 0x0 0x800&gt;;</div><div class='del'>-				interrupts = &lt;GIC_SPI 218 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='hunk'>@@ -626,6 +681,8 @@</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 57 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='add'>+			#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+			sound-name-prefix = "HDMITX";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> </div><div class='ctx'> 			/* VPU VENC Input */</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-kii-pro.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-kii-pro.dts<br/>index 6c9cc45fb417..073b47ce8c3c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxbb-kii-pro.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxbb-kii-pro.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxbb-kii-pro.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxbb-kii-pro.dts</a></div><div class='hunk'>@@ -6,28 +6,33 @@</div><div class='ctx'> /dts-v1/;</div><div class='ctx'> </div><div class='ctx'> #include "meson-gxbb-p20x.dtsi"</div><div class='del'>-</div><div class='ctx'> #include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/input/input.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/meson-aiu.h&gt;</div><div class='add'>+</div><div class='ctx'> / {</div><div class='del'>-	compatible = "videostrong,kii-pro", "amlogic,p201", "amlogic,s905", "amlogic,meson-gxbb";</div><div class='add'>+	compatible = "videostrong,kii-pro", "amlogic,meson-gxbb";</div><div class='ctx'> 	model = "Videostrong KII Pro";</div><div class='ctx'> </div><div class='add'>+	spdif_dit: audio-codec-0 {</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		compatible = "linux,spdif-dit";</div><div class='add'>+		sound-name-prefix = "DIT";</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	leds {</div><div class='ctx'> 		compatible = "gpio-leds";</div><div class='del'>-		status {</div><div class='add'>+		led {</div><div class='ctx'> 			gpios = &lt;&amp;gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-			default-state = "off";</div><div class='ctx'> 			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='ctx'> 			function = LED_FUNCTION_STATUS;</div><div class='add'>+			default-state = "off";</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	gpio-keys-polled {</div><div class='ctx'> 		compatible = "gpio-keys-polled";</div><div class='del'>-		#address-cells = &lt;1&gt;;</div><div class='del'>-		#size-cells = &lt;0&gt;;</div><div class='ctx'> 		poll-interval = &lt;20&gt;;</div><div class='ctx'> </div><div class='ctx'> 		button-reset {</div><div class='hunk'>@@ -37,22 +42,62 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-};</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "amlogic,gx-sound-card";</div><div class='add'>+		model = "KII-PRO";</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL1&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;294912000&gt;,</div><div class='add'>+				       &lt;270950400&gt;,</div><div class='add'>+				       &lt;393216000&gt;;</div><div class='add'>+</div><div class='add'>+		dai-link-0 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_I2S_FIFO&gt;;</div><div class='add'>+		};</div><div class='ctx'> </div><div class='add'>+		dai-link-1 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_SPDIF_FIFO&gt;;</div><div class='add'>+		};</div><div class='ctx'> </div><div class='add'>+		dai-link-2 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_I2S_ENCODER&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='ctx'> </div><div class='del'>-&amp;uart_A {</div><div class='del'>-	status = "okay";</div><div class='del'>-	pinctrl-0 = &lt;&amp;uart_a_pins&gt;, &lt;&amp;uart_a_cts_rts_pins&gt;;</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-	uart-has-rtscts;</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;aiu AIU_HDMI CTRL_I2S&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='ctx'> </div><div class='del'>-	bluetooth {</div><div class='del'>-		compatible = "brcm,bcm4335a0";</div><div class='add'>+		dai-link-3 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_SPDIF_ENCODER&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;spdif_dit&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-4 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_HDMI CTRL_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-</div><div class='add'>+&amp;aiu {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;spdif_out_y_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='ctx'> </div><div class='ctx'> &amp;ethmac {</div><div class='ctx'> 	status = "okay";</div><div class='hunk'>@@ -80,3 +125,19 @@</div><div class='ctx'> &amp;ir {</div><div class='ctx'> 	linux,rc-map-name = "rc-videostrong-kii-pro";</div><div class='ctx'> };</div><div class='add'>+</div><div class='add'>+&amp;uart_A {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart_a_pins&gt;, &lt;&amp;uart_a_cts_rts_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "brcm,bcm4335a0";</div><div class='add'>+		shutdown-gpios = &lt;&amp;gpio GPIOX_20 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		host-wakeup-gpios = &lt;&amp;gpio GPIOX_21 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		max-speed = &lt;2000000&gt;;</div><div class='add'>+		clocks = &lt;&amp;wifi32k&gt;;</div><div class='add'>+		clock-names = "lpo";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts<br/>index d6ca684e0e61..2ecc6ebd5a43 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts</a></div><div class='hunk'>@@ -7,6 +7,7 @@</div><div class='ctx'> </div><div class='ctx'> #include "meson-gxbb.dtsi"</div><div class='ctx'> #include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/meson-aiu.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb";</div><div class='hunk'>@@ -29,7 +30,7 @@</div><div class='ctx'> 	leds {</div><div class='ctx'> 		compatible = "gpio-leds";</div><div class='ctx'> </div><div class='del'>-		stat {</div><div class='add'>+		led-stat {</div><div class='ctx'> 			label = "nanopi-k2:blue:stat";</div><div class='ctx'> 			gpios = &lt;&amp;gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 			default-state = "on";</div><div class='hunk'>@@ -130,6 +131,48 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "amlogic,gx-sound-card";</div><div class='add'>+		model = "NANOPI-K2";</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL1&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;294912000&gt;,</div><div class='add'>+				       &lt;270950400&gt;,</div><div class='add'>+				       &lt;393216000&gt;;</div><div class='add'>+</div><div class='add'>+		dai-link-0 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_I2S_FIFO&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-1 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_I2S_ENCODER&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;aiu AIU_HDMI CTRL_I2S&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-2 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_HDMI CTRL_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;aiu {</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cec_AO {</div><div class='hunk'>@@ -165,7 +208,7 @@</div><div class='ctx'> 			reg = &lt;0&gt;;</div><div class='ctx'> </div><div class='ctx'> 			reset-assert-us = &lt;10000&gt;;</div><div class='del'>-			reset-deassert-us = &lt;30000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;80000&gt;;</div><div class='ctx'> 			reset-gpios = &lt;&amp;gpio GPIOZ_14 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> </div><div class='ctx'> 			interrupt-parent = &lt;&amp;gpio_intc&gt;;</div><div class='hunk'>@@ -255,8 +298,6 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pwm_e_pins&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='del'>-	clocks = &lt;&amp;clkc CLKID_FCLK_DIV4&gt;;</div><div class='del'>-	clock-names = "clkin0";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;saradc {</div><div class='hunk'>@@ -345,9 +386,20 @@</div><div class='ctx'> </div><div class='ctx'> /* Bluetooth on AP6212 */</div><div class='ctx'> &amp;uart_A {</div><div class='del'>-	status = "disabled";</div><div class='add'>+	status = "okay";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;uart_a_pins&gt;, &lt;&amp;uart_a_cts_rts_pins&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "brcm,bcm43438-bt";</div><div class='add'>+		clocks = &lt;&amp;wifi_32k&gt;;</div><div class='add'>+		clock-names = "lpo";</div><div class='add'>+		vbat-supply = &lt;&amp;vddio_ao3v3&gt;;</div><div class='add'>+		vddio-supply = &lt;&amp;vddio_ao18&gt;;</div><div class='add'>+		host-wakeup-gpios = &lt;&amp;gpio GPIOX_21 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		shutdown-gpios = &lt;&amp;gpio GPIOX_20 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* 40-pin CON1 */</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts<br/>index 65ec7dea828c..c09da40ff7b0 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts</a></div><div class='hunk'>@@ -10,6 +10,7 @@</div><div class='ctx'> #include "meson-gxbb.dtsi"</div><div class='ctx'> #include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/meson-aiu.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	compatible = "nexbox,a95x", "amlogic,meson-gxbb";</div><div class='hunk'>@@ -31,7 +32,7 @@</div><div class='ctx'> </div><div class='ctx'> 	leds {</div><div class='ctx'> 		compatible = "gpio-leds";</div><div class='del'>-		blue {</div><div class='add'>+		led-blue {</div><div class='ctx'> 			label = "a95x:system-status";</div><div class='ctx'> 			gpios = &lt;&amp;gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 			linux,default-trigger = "heartbeat";</div><div class='hunk'>@@ -41,11 +42,9 @@</div><div class='ctx'> </div><div class='ctx'> 	gpio-keys-polled {</div><div class='ctx'> 		compatible = "gpio-keys-polled";</div><div class='del'>-		#address-cells = &lt;1&gt;;</div><div class='del'>-		#size-cells = &lt;0&gt;;</div><div class='ctx'> 		poll-interval = &lt;100&gt;;</div><div class='ctx'> </div><div class='del'>-		button@0 {</div><div class='add'>+		button {</div><div class='ctx'> 			label = "reset";</div><div class='ctx'> 			linux,code = &lt;KEY_RESTART&gt;;</div><div class='ctx'> 			gpios = &lt;&amp;gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW&gt;;</div><div class='hunk'>@@ -79,21 +78,21 @@</div><div class='ctx'> 			 &lt;3300000 1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vddio_boot: regulator-vddio_boot {</div><div class='add'>+	vddio_boot: regulator-vddio-boot {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VDDIO_BOOT";</div><div class='ctx'> 		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vddao_3v3: regulator-vddao_3v3 {</div><div class='add'>+	vddao_3v3: regulator-vddao-3v3 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VDDAO_3V3";</div><div class='ctx'> 		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='ctx'> 		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vcc_3v3: regulator-vcc_3v3 {</div><div class='add'>+	vcc_3v3: regulator-vcc-3v3 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VCC_3V3";</div><div class='ctx'> 		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='hunk'>@@ -139,6 +138,48 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "amlogic,gx-sound-card";</div><div class='add'>+		model = "NEXBOX-A95X";</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL1&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;294912000&gt;,</div><div class='add'>+				       &lt;270950400&gt;,</div><div class='add'>+				       &lt;393216000&gt;;</div><div class='add'>+</div><div class='add'>+		dai-link-0 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_I2S_FIFO&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-1 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_I2S_ENCODER&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;aiu AIU_HDMI CTRL_I2S&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-2 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_HDMI CTRL_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;aiu {</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cvbs_vdac_port {</div><div class='hunk'>@@ -200,8 +241,6 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pwm_e_pins&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='del'>-	clocks = &lt;&amp;clkc CLKID_FCLK_DIV4&gt;;</div><div class='del'>-	clock-names = "clkin0";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* Wireless SDIO Module */</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts<br/>index b46ef985bb44..12e26f99d4f0 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts</a></div><div class='hunk'>@@ -9,6 +9,7 @@</div><div class='ctx'> </div><div class='ctx'> #include "meson-gxbb.dtsi"</div><div class='ctx'> #include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/meson-aiu.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";</div><div class='hunk'>@@ -49,7 +50,7 @@</div><div class='ctx'> </div><div class='ctx'> 	leds {</div><div class='ctx'> 		compatible = "gpio-leds";</div><div class='del'>-		blue {</div><div class='add'>+		led-blue {</div><div class='ctx'> 			label = "c2:blue:alive";</div><div class='ctx'> 			gpios = &lt;&amp;gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 			linux,default-trigger = "heartbeat";</div><div class='hunk'>@@ -66,7 +67,7 @@</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	hdmi_p5v0: regulator-hdmi_p5v0 {</div><div class='add'>+	hdmi_p5v0: regulator-hdmi-p5v0 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "HDMI_P5V0";</div><div class='ctx'> 		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='hunk'>@@ -75,7 +76,7 @@</div><div class='ctx'> 		vin-supply = &lt;&amp;p5v0&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	tflash_vdd: regulator-tflash_vdd {</div><div class='add'>+	tflash_vdd: regulator-tflash-vdd {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> </div><div class='ctx'> 		regulator-name = "TFLASH_VDD";</div><div class='hunk'>@@ -91,7 +92,7 @@</div><div class='ctx'> 		vin-supply = &lt;&amp;vddio_ao3v3&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	tf_io: gpio-regulator-tf_io {</div><div class='add'>+	tf_io: gpio-regulator-tf-io {</div><div class='ctx'> 		compatible = "regulator-gpio";</div><div class='ctx'> </div><div class='ctx'> 		regulator-name = "TF_IO";</div><div class='hunk'>@@ -147,7 +148,7 @@</div><div class='ctx'> 		vin-supply = &lt;&amp;p5v0&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	ddr3_1v5: regulator-ddr3_1v5 {</div><div class='add'>+	ddr3_1v5: regulator-ddr3-1v5 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "DDR3_1V5";</div><div class='ctx'> 		regulator-min-microvolt = &lt;1500000&gt;;</div><div class='hunk'>@@ -172,6 +173,48 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "amlogic,gx-sound-card";</div><div class='add'>+		model = "ODROID-C2";</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL1&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;294912000&gt;,</div><div class='add'>+				       &lt;270950400&gt;,</div><div class='add'>+				       &lt;393216000&gt;;</div><div class='add'>+</div><div class='add'>+		dai-link-0 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_I2S_FIFO&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-1 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_I2S_ENCODER&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;aiu AIU_HDMI CTRL_I2S&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-2 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_HDMI CTRL_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;aiu {</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cec_AO {</div><div class='hunk'>@@ -200,7 +243,7 @@</div><div class='ctx'> 			reg = &lt;0&gt;;</div><div class='ctx'> </div><div class='ctx'> 			reset-assert-us = &lt;10000&gt;;</div><div class='del'>-			reset-deassert-us = &lt;30000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;80000&gt;;</div><div class='ctx'> 			reset-gpios = &lt;&amp;gpio GPIOZ_14 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> </div><div class='ctx'> 			interrupt-parent = &lt;&amp;gpio_intc&gt;;</div><div class='hunk'>@@ -210,21 +253,6 @@</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;gpio_ao {</div><div class='del'>-	/*</div><div class='del'>-	 * WARNING: The USB Hub on the Odroid-C2 needs a reset signal</div><div class='del'>-	 * to be turned high in order to be detected by the USB Controller</div><div class='del'>-	 * This signal should be handled by a USB specific power sequence</div><div class='del'>-	 * in order to reset the Hub when USB bus is powered down.</div><div class='del'>-	 */</div><div class='del'>-	usb-hub {</div><div class='del'>-		gpio-hog;</div><div class='del'>-		gpios = &lt;GPIOAO_4 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-		output-high;</div><div class='del'>-		line-name = "usb-hub-reset";</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> &amp;hdmi_tx {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;hdmi_hpd_pins&gt;, &lt;&amp;hdmi_i2c_pins&gt;;</div><div class='hunk'>@@ -320,10 +348,6 @@</div><div class='ctx'> </div><div class='ctx'> 	bus-width = &lt;4&gt;;</div><div class='ctx'> 	cap-sd-highspeed;</div><div class='del'>-	sd-uhs-sdr12;</div><div class='del'>-	sd-uhs-sdr25;</div><div class='del'>-	sd-uhs-sdr50;</div><div class='del'>-	sd-uhs-ddr50;</div><div class='ctx'> 	max-frequency = &lt;100000000&gt;;</div><div class='ctx'> 	disable-wp;</div><div class='ctx'> </div><div class='hunk'>@@ -374,5 +398,16 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;usb1 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='add'>+</div><div class='add'>+	hub@1 {</div><div class='add'>+		/* Genesys Logic GL852G USB 2.0 hub */</div><div class='add'>+		compatible = "usb5e3,610";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;p5v0&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts<br/>index 3c93d1898b40..bfac00e76ba3 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts</a></div><div class='hunk'>@@ -9,19 +9,26 @@</div><div class='ctx'> </div><div class='ctx'> #include "meson-gxbb-p20x.dtsi"</div><div class='ctx'> #include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/meson-aiu.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	compatible = "amlogic,p200", "amlogic,meson-gxbb";</div><div class='ctx'> 	model = "Amlogic Meson GXBB P200 Development Board";</div><div class='ctx'> </div><div class='del'>-	avdd18_usb_adc: regulator-avdd18_usb_adc {</div><div class='add'>+	spdif_dit: audio-codec-0 {</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		compatible = "linux,spdif-dit";</div><div class='add'>+		sound-name-prefix = "DIT";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	avdd18_usb_adc: regulator-avdd18-usb-adc {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "AVDD18_USB_ADC";</div><div class='ctx'> 		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	adc_keys {</div><div class='add'>+	keys {</div><div class='ctx'> 		compatible = "adc-keys";</div><div class='ctx'> 		io-channels = &lt;&amp;saradc 0&gt;;</div><div class='ctx'> 		io-channel-names = "buttons";</div><div class='hunk'>@@ -57,6 +64,62 @@</div><div class='ctx'> 			press-threshold-microvolt = &lt;0&gt;; /* 0% */</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "amlogic,gx-sound-card";</div><div class='add'>+		model = "P200";</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL1&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;294912000&gt;,</div><div class='add'>+				       &lt;270950400&gt;,</div><div class='add'>+				       &lt;393216000&gt;;</div><div class='add'>+</div><div class='add'>+		dai-link-0 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_I2S_FIFO&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-1 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_SPDIF_FIFO&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-2 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_I2S_ENCODER&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;aiu AIU_HDMI CTRL_I2S&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-3 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_SPDIF_ENCODER&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;spdif_dit&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-4 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_HDMI CTRL_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;aiu {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;spdif_out_y_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;ethmac {</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts<br/>index 150a82f3b2d7..c10f66031ecd 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts</a></div><div class='hunk'>@@ -8,10 +8,53 @@</div><div class='ctx'> /dts-v1/;</div><div class='ctx'> </div><div class='ctx'> #include "meson-gxbb-p20x.dtsi"</div><div class='add'>+#include &lt;dt-bindings/sound/meson-aiu.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	compatible = "amlogic,p201", "amlogic,meson-gxbb";</div><div class='ctx'> 	model = "Amlogic Meson GXBB P201 Development Board";</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "amlogic,gx-sound-card";</div><div class='add'>+		model = "P201";</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL1&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;294912000&gt;,</div><div class='add'>+				       &lt;270950400&gt;,</div><div class='add'>+				       &lt;393216000&gt;;</div><div class='add'>+</div><div class='add'>+		dai-link-0 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_I2S_FIFO&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-1 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_I2S_ENCODER&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;aiu AIU_HDMI CTRL_I2S&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-2 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_HDMI CTRL_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;aiu {</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;ethmac {</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi<br/>index e803a466fe4e..6f67364fd63f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi</a></div><div class='hunk'>@@ -53,21 +53,21 @@</div><div class='ctx'> 		regulator-settling-time-down-us = &lt;150000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vddio_boot: regulator-vddio_boot {</div><div class='add'>+	vddio_boot: regulator-vddio-boot {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VDDIO_BOOT";</div><div class='ctx'> 		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vddao_3v3: regulator-vddao_3v3 {</div><div class='add'>+	vddao_3v3: regulator-vddao-3v3 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VDDAO_3V3";</div><div class='ctx'> 		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='ctx'> 		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vcc_3v3: regulator-vcc_3v3 {</div><div class='add'>+	vcc_3v3: regulator-vcc-3v3 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VCC_3V3";</div><div class='ctx'> 		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='hunk'>@@ -150,8 +150,6 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pwm_e_pins&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='del'>-	clocks = &lt;&amp;clkc CLKID_FCLK_DIV4&gt;;</div><div class='del'>-	clock-names = "clkin0";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* Wireless SDIO Module */</div><div class='hunk'>@@ -178,9 +176,8 @@</div><div class='ctx'> 	vmmc-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='ctx'> 	vqmmc-supply = &lt;&amp;vddio_boot&gt;;</div><div class='ctx'> </div><div class='del'>-	brcmf: wifi@1 {</div><div class='add'>+	sdio: wifi@1 {</div><div class='ctx'> 		reg = &lt;1&gt;;</div><div class='del'>-		compatible = "brcm,bcm4329-fmac";</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi<br/>index 45cb83625951..6ff567225fee 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi</a></div><div class='hunk'>@@ -4,6 +4,7 @@</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include "meson-gxbb.dtsi"</div><div class='add'>+#include &lt;dt-bindings/sound/meson-aiu.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	compatible = "tronsmart,vega-s95", "amlogic,meson-gxbb";</div><div class='hunk'>@@ -17,10 +18,16 @@</div><div class='ctx'> 		stdout-path = "serial0:115200n8";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	spdif_dit: audio-codec-0 {</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		compatible = "linux,spdif-dit";</div><div class='add'>+		sound-name-prefix = "DIT";</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	leds {</div><div class='ctx'> 		compatible = "gpio-leds";</div><div class='ctx'> </div><div class='del'>-		blue {</div><div class='add'>+		led-blue {</div><div class='ctx'> 			label = "vega-s95:blue:on";</div><div class='ctx'> 			gpios = &lt;&amp;gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 			default-state = "on";</div><div class='hunk'>@@ -40,28 +47,28 @@</div><div class='ctx'> 		enable-active-high;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vddio_boot: regulator-vddio_boot {</div><div class='add'>+	vddio_boot: regulator-vddio-boot {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VDDIO_BOOT";</div><div class='ctx'> 		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vddao_3v3: regulator-vddao_3v3 {</div><div class='add'>+	vddao_3v3: regulator-vddao-3v3 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VDDAO_3V3";</div><div class='ctx'> 		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='ctx'> 		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vddio_ao18: regulator-vddio_ao18 {</div><div class='add'>+	vddio_ao18: regulator-vddio-ao18 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VDDIO_AO18";</div><div class='ctx'> 		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vcc_3v3: regulator-vcc_3v3 {</div><div class='add'>+	vcc_3v3: regulator-vcc-3v3 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VCC_3V3";</div><div class='ctx'> 		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='hunk'>@@ -97,6 +104,62 @@</div><div class='ctx'> 		clocks = &lt;&amp;wifi32k&gt;;</div><div class='ctx'> 		clock-names = "ext_clock";</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "amlogic,gx-sound-card";</div><div class='add'>+		model = "VEGA-S95";</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL1&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;294912000&gt;,</div><div class='add'>+				       &lt;270950400&gt;,</div><div class='add'>+				       &lt;393216000&gt;;</div><div class='add'>+</div><div class='add'>+		dai-link-0 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_I2S_FIFO&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-1 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_SPDIF_FIFO&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-2 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_I2S_ENCODER&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;aiu AIU_HDMI CTRL_I2S&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-3 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_SPDIF_ENCODER&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;spdif_dit&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-4 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_HDMI CTRL_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;aiu {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;spdif_out_y_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cec_AO {</div><div class='hunk'>@@ -126,7 +189,7 @@</div><div class='ctx'> 			reg = &lt;0&gt;;</div><div class='ctx'> </div><div class='ctx'> 			reset-assert-us = &lt;10000&gt;;</div><div class='del'>-			reset-deassert-us = &lt;30000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;80000&gt;;</div><div class='ctx'> 			reset-gpios = &lt;&amp;gpio GPIOZ_14 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> </div><div class='ctx'> 			interrupt-parent = &lt;&amp;gpio_intc&gt;;</div><div class='hunk'>@@ -159,8 +222,6 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pwm_e_pins&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='del'>-	clocks = &lt;&amp;clkc CLKID_FCLK_DIV4&gt;;</div><div class='del'>-	clock-names = "clkin0";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;saradc {</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts<br/>index 83b985bb015e..ec281a9e9e77 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts</a></div><div class='hunk'>@@ -7,10 +7,53 @@</div><div class='ctx'> /dts-v1/;</div><div class='ctx'> </div><div class='ctx'> #include "meson-gxbb-wetek.dtsi"</div><div class='add'>+#include &lt;dt-bindings/sound/meson-aiu.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	compatible = "wetek,hub", "amlogic,meson-gxbb";</div><div class='ctx'> 	model = "WeTek Hub";</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "amlogic,gx-sound-card";</div><div class='add'>+		model = "WETEK-HUB";</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL1&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;294912000&gt;,</div><div class='add'>+				       &lt;270950400&gt;,</div><div class='add'>+				       &lt;393216000&gt;;</div><div class='add'>+</div><div class='add'>+		dai-link-0 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_I2S_FIFO&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-1 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_I2S_ENCODER&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;aiu AIU_HDMI CTRL_I2S&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-2 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_HDMI CTRL_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;aiu {</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;ir {</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts<br/>index 1d32d1f6d032..924414861b72 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts</a></div><div class='hunk'>@@ -8,19 +8,26 @@</div><div class='ctx'> </div><div class='ctx'> #include "meson-gxbb-wetek.dtsi"</div><div class='ctx'> #include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/meson-aiu.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	compatible = "wetek,play2", "amlogic,meson-gxbb";</div><div class='ctx'> 	model = "WeTek Play 2";</div><div class='ctx'> </div><div class='add'>+	spdif_dit: audio-codec-0 {</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		compatible = "linux,spdif-dit";</div><div class='add'>+		sound-name-prefix = "DIT";</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	leds {</div><div class='del'>-		wifi {</div><div class='add'>+		led-wifi {</div><div class='ctx'> 			label = "wetek-play:wifi-status";</div><div class='ctx'> 			gpios = &lt;&amp;gpio GPIODV_26 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 			default-state = "off";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		ethernet {</div><div class='add'>+		led-ethernet {</div><div class='ctx'> 			label = "wetek-play:ethernet-status";</div><div class='ctx'> 			gpios = &lt;&amp;gpio GPIODV_27 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 			default-state = "off";</div><div class='hunk'>@@ -29,16 +36,70 @@</div><div class='ctx'> </div><div class='ctx'> 	gpio-keys-polled {</div><div class='ctx'> 		compatible = "gpio-keys-polled";</div><div class='del'>-		#address-cells = &lt;1&gt;;</div><div class='del'>-		#size-cells = &lt;0&gt;;</div><div class='ctx'> 		poll-interval = &lt;100&gt;;</div><div class='ctx'> </div><div class='del'>-		button@0 {</div><div class='add'>+		button {</div><div class='ctx'> 			label = "reset";</div><div class='ctx'> 			linux,code = &lt;KEY_RESTART&gt;;</div><div class='ctx'> 			gpios = &lt;&amp;gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "amlogic,gx-sound-card";</div><div class='add'>+		model = "WETEK-PLAY2";</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL1&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;294912000&gt;,</div><div class='add'>+				       &lt;270950400&gt;,</div><div class='add'>+				       &lt;393216000&gt;;</div><div class='add'>+</div><div class='add'>+		dai-link-0 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_I2S_FIFO&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-1 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_SPDIF_FIFO&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-2 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_I2S_ENCODER&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;aiu AIU_HDMI CTRL_I2S&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-3 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_SPDIF_ENCODER&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;spdif_dit&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-4 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_HDMI CTRL_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;aiu {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;spdif_out_y_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;i2c_A {</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi<br/>index dee51cf95223..bfedfc1472ec 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi</a></div><div class='hunk'>@@ -6,6 +6,8 @@</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include "meson-gxbb.dtsi"</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	aliases {</div><div class='hunk'>@@ -25,8 +27,10 @@</div><div class='ctx'> 	leds {</div><div class='ctx'> 		compatible = "gpio-leds";</div><div class='ctx'> </div><div class='del'>-		system {</div><div class='del'>-			label = "wetek-play:system-status";</div><div class='add'>+		led-power {</div><div class='add'>+			/* red in suspend or power-off */</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			function = LED_FUNCTION_POWER;</div><div class='ctx'> 			gpios = &lt;&amp;gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 			default-state = "on";</div><div class='ctx'> 			panic-indicator;</div><div class='hunk'>@@ -45,28 +49,29 @@</div><div class='ctx'> 		enable-active-high;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vddio_boot: regulator-vddio_boot {</div><div class='add'>+	vddio_boot: regulator-vddio-boot {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VDDIO_BOOT";</div><div class='ctx'> 		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vddao_3v3: regulator-vddao_3v3 {</div><div class='add'>+	vddao_3v3: regulator-vddao-3v3 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VDDAO_3V3";</div><div class='ctx'> 		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='ctx'> 		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vddio_ao18: regulator-vddio_ao18 {</div><div class='add'>+	vddio_ao18: regulator-vddio-ao18 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VDDIO_AO18";</div><div class='ctx'> 		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vcc_3v3: regulator-vcc_3v3 {</div><div class='add'>+	vcc_3v3: regulator-vcc-3v3 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VCC_3V3";</div><div class='ctx'> 		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='hunk'>@@ -147,8 +152,12 @@</div><div class='ctx'> 			reg = &lt;0&gt;;</div><div class='ctx'> </div><div class='ctx'> 			reset-assert-us = &lt;10000&gt;;</div><div class='del'>-			reset-deassert-us = &lt;30000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;80000&gt;;</div><div class='ctx'> 			reset-gpios = &lt;&amp;gpio GPIOZ_14 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio_intc&gt;;</div><div class='add'>+			/* MAC_INTR on GPIOZ_15 */</div><div class='add'>+			interrupts = &lt;29 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='hunk'>@@ -157,6 +166,7 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;hdmi_hpd_pins&gt;, &lt;&amp;hdmi_i2c_pins&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='add'>+	hdmi-supply = &lt;&amp;vddio_ao18&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;hdmi_tx_tmds_port {</div><div class='hunk'>@@ -175,8 +185,6 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pwm_e_pins&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='del'>-	clocks = &lt;&amp;clkc CLKID_FCLK_DIV4&gt;;</div><div class='del'>-	clock-names = "clkin0";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;saradc {</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi<br/>index 0cb40326b0d3..f69923da07fe 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi</a></div><div class='hunk'>@@ -4,6 +4,7 @@</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include "meson-gx.dtsi"</div><div class='add'>+#include "meson-gx-mali450.dtsi"</div><div class='ctx'> #include &lt;dt-bindings/gpio/meson-gxbb-gpio.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/reset/amlogic,meson-gxbb-reset.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/clock/gxbb-clkc.h&gt;</div><div class='hunk'>@@ -60,6 +61,29 @@</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;aiu {</div><div class='add'>+	compatible = "amlogic,aiu-gxbb", "amlogic,aiu";</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_AIU_GLUE&gt;,</div><div class='add'>+		 &lt;&amp;clkc CLKID_I2S_OUT&gt;,</div><div class='add'>+		 &lt;&amp;clkc CLKID_AOCLK_GATE&gt;,</div><div class='add'>+		 &lt;&amp;clkc CLKID_CTS_AMCLK&gt;,</div><div class='add'>+		 &lt;&amp;clkc CLKID_MIXER_IFACE&gt;,</div><div class='add'>+		 &lt;&amp;clkc CLKID_IEC958&gt;,</div><div class='add'>+		 &lt;&amp;clkc CLKID_IEC958_GATE&gt;,</div><div class='add'>+		 &lt;&amp;clkc CLKID_CTS_MCLK_I958&gt;,</div><div class='add'>+		 &lt;&amp;clkc CLKID_CTS_I958&gt;;</div><div class='add'>+	clock-names = "pclk",</div><div class='add'>+		      "i2s_pclk",</div><div class='add'>+		      "i2s_aoclk",</div><div class='add'>+		      "i2s_mclk",</div><div class='add'>+		      "i2s_mixer",</div><div class='add'>+		      "spdif_pclk",</div><div class='add'>+		      "spdif_aoclk",</div><div class='add'>+		      "spdif_mclk",</div><div class='add'>+		      "spdif_mclk_sel";</div><div class='add'>+	resets = &lt;&amp;reset RESET_AIU&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;aobus {</div><div class='ctx'> 	pinctrl_aobus: pinctrl@14 {</div><div class='ctx'> 		compatible = "amlogic,meson-gxbb-aobus-pinctrl";</div><div class='hunk'>@@ -81,7 +105,7 @@</div><div class='ctx'> 			mux {</div><div class='ctx'> 				groups = "uart_tx_ao_a", "uart_rx_ao_a";</div><div class='ctx'> 				function = "uart_ao";</div><div class='del'>-				bias-disable;</div><div class='add'>+				bias-pull-up;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -98,7 +122,7 @@</div><div class='ctx'> 			mux {</div><div class='ctx'> 				groups = "uart_tx_ao_b", "uart_rx_ao_b";</div><div class='ctx'> 				function = "uart_ao_b";</div><div class='del'>-				bias-disable;</div><div class='add'>+				bias-pull-up;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -241,46 +265,6 @@</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;apb {</div><div class='del'>-	mali: gpu@c0000 {</div><div class='del'>-		compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";</div><div class='del'>-		reg = &lt;0x0 0xc0000 0x0 0x40000&gt;;</div><div class='del'>-		interrupts = &lt;GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-			     &lt;GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-			     &lt;GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-			     &lt;GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-			     &lt;GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-			     &lt;GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-			     &lt;GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-			     &lt;GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-			     &lt;GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-			     &lt;GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-		interrupt-names = "gp", "gpmmu", "pp", "pmu",</div><div class='del'>-			"pp0", "ppmmu0", "pp1", "ppmmu1",</div><div class='del'>-			"pp2", "ppmmu2";</div><div class='del'>-		clocks = &lt;&amp;clkc CLKID_CLK81&gt;, &lt;&amp;clkc CLKID_MALI&gt;;</div><div class='del'>-		clock-names = "bus", "core";</div><div class='del'>-</div><div class='del'>-		/*</div><div class='del'>-		 * Mali clocking is provided by two identical clock paths</div><div class='del'>-		 * MALI_0 and MALI_1 muxed to a single clock by a glitch</div><div class='del'>-		 * free mux to safely change frequency while running.</div><div class='del'>-		 */</div><div class='del'>-		assigned-clocks = &lt;&amp;clkc CLKID_GP0_PLL&gt;,</div><div class='del'>-				  &lt;&amp;clkc CLKID_MALI_0_SEL&gt;,</div><div class='del'>-				  &lt;&amp;clkc CLKID_MALI_0&gt;,</div><div class='del'>-				  &lt;&amp;clkc CLKID_MALI&gt;; /* Glitch free mux */</div><div class='del'>-		assigned-clock-parents = &lt;0&gt;, /* Do Nothing */</div><div class='del'>-					 &lt;&amp;clkc CLKID_GP0_PLL&gt;,</div><div class='del'>-					 &lt;0&gt;, /* Do Nothing */</div><div class='del'>-					 &lt;&amp;clkc CLKID_MALI_0&gt;;</div><div class='del'>-		assigned-clock-rates = &lt;744000000&gt;,</div><div class='del'>-				       &lt;0&gt;, /* Do Nothing */</div><div class='del'>-				       &lt;744000000&gt;,</div><div class='del'>-				       &lt;0&gt;; /* Do Nothing */</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> &amp;cbus {</div><div class='ctx'> 	spifc: spi@8c80 {</div><div class='ctx'> 		compatible = "amlogic,meson-gxbb-spifc";</div><div class='hunk'>@@ -310,13 +294,14 @@</div><div class='ctx'> &amp;ethmac {</div><div class='ctx'> 	clocks = &lt;&amp;clkc CLKID_ETH&gt;,</div><div class='ctx'> 		 &lt;&amp;clkc CLKID_FCLK_DIV2&gt;,</div><div class='del'>-		 &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='del'>-	clock-names = "stmmaceth", "clkin0", "clkin1";</div><div class='add'>+		 &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+		 &lt;&amp;clkc CLKID_FCLK_DIV2&gt;;</div><div class='add'>+	clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;gpio_intc {</div><div class='del'>-	compatible = "amlogic,meson-gpio-intc",</div><div class='del'>-		     "amlogic,meson-gxbb-gpio-intc";</div><div class='add'>+	compatible = "amlogic,meson-gxbb-gpio-intc",</div><div class='add'>+		     "amlogic,meson-gpio-intc";</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -326,10 +311,16 @@</div><div class='ctx'> 		 &lt;&amp;reset RESET_HDMI_SYSTEM_RESET&gt;,</div><div class='ctx'> 		 &lt;&amp;reset RESET_HDMI_TX&gt;;</div><div class='ctx'> 	reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";</div><div class='del'>-	clocks = &lt;&amp;clkc CLKID_HDMI_PCLK&gt;,</div><div class='del'>-		 &lt;&amp;clkc CLKID_CLK81&gt;,</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_HDMI&gt;,</div><div class='add'>+		 &lt;&amp;clkc CLKID_HDMI_PCLK&gt;,</div><div class='ctx'> 		 &lt;&amp;clkc CLKID_GCLK_VENCI_INT0&gt;;</div><div class='ctx'> 	clock-names = "isfr", "iahb", "venci";</div><div class='add'>+	power-domains = &lt;&amp;pwrc PWRC_GXBB_VPU_ID&gt;;</div><div class='add'>+</div><div class='add'>+	assigned-clocks = &lt;&amp;clkc CLKID_HDMI_SEL&gt;,</div><div class='add'>+			  &lt;&amp;clkc CLKID_HDMI&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;xtal&gt;, &lt;0&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;0&gt;, &lt;24000000&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;sysctrl {</div><div class='hunk'>@@ -362,6 +353,16 @@</div><div class='ctx'> 	clocks = &lt;&amp;clkc CLKID_I2C&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;mali {</div><div class='add'>+	compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";</div><div class='add'>+</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CLK81&gt;, &lt;&amp;clkc CLKID_MALI&gt;;</div><div class='add'>+	clock-names = "bus", "core";</div><div class='add'>+</div><div class='add'>+	assigned-clocks = &lt;&amp;clkc CLKID_GP0_PLL&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;744000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;periphs {</div><div class='ctx'> 	pinctrl_periphs: pinctrl@4b0 {</div><div class='ctx'> 		compatible = "amlogic,meson-gxbb-periphs-pinctrl";</div><div class='hunk'>@@ -432,6 +433,20 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		spi_idle_high_pins: spi-idle-high-pins {</div><div class='add'>+			mux {</div><div class='add'>+				groups = "spi_sclk";</div><div class='add'>+				bias-pull-up;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi_idle_low_pins: spi-idle-low-pins {</div><div class='add'>+			mux {</div><div class='add'>+				groups = "spi_sclk";</div><div class='add'>+				bias-pull-down;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		spi_ss0_pins: spi-ss0 {</div><div class='ctx'> 			mux {</div><div class='ctx'> 				groups = "spi_ss0";</div><div class='hunk'>@@ -505,7 +520,7 @@</div><div class='ctx'> 				groups = "uart_tx_a",</div><div class='ctx'> 				       "uart_rx_a";</div><div class='ctx'> 				function = "uart_a";</div><div class='del'>-				bias-disable;</div><div class='add'>+				bias-pull-up;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -523,7 +538,7 @@</div><div class='ctx'> 				groups = "uart_tx_b",</div><div class='ctx'> 				       "uart_rx_b";</div><div class='ctx'> 				function = "uart_b";</div><div class='del'>-				bias-disable;</div><div class='add'>+				bias-pull-up;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -541,7 +556,7 @@</div><div class='ctx'> 				groups = "uart_tx_c",</div><div class='ctx'> 				       "uart_rx_c";</div><div class='ctx'> 				function = "uart_c";</div><div class='del'>-				bias-disable;</div><div class='add'>+				bias-pull-up;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -724,7 +739,32 @@</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;pwrc_vpu {</div><div class='add'>+&amp;pwm_ab {</div><div class='add'>+	clocks = &lt;&amp;xtal&gt;,</div><div class='add'>+		 &lt;0&gt;, /* unknown/untested, the datasheet calls it "vid_pll" */</div><div class='add'>+		 &lt;&amp;clkc CLKID_FCLK_DIV4&gt;,</div><div class='add'>+		 &lt;&amp;clkc CLKID_FCLK_DIV3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm_AO_ab {</div><div class='add'>+	clocks = &lt;&amp;xtal&gt;, &lt;&amp;clkc CLKID_CLK81&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm_cd {</div><div class='add'>+	clocks = &lt;&amp;xtal&gt;,</div><div class='add'>+		 &lt;0&gt;, /* unknown/untested, the datasheet calls it "vid_pll" */</div><div class='add'>+		 &lt;&amp;clkc CLKID_FCLK_DIV4&gt;,</div><div class='add'>+		 &lt;&amp;clkc CLKID_FCLK_DIV3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm_ef {</div><div class='add'>+	clocks = &lt;&amp;xtal&gt;,</div><div class='add'>+		 &lt;0&gt;, /* unknown/untested, the datasheet calls it "vid_pll" */</div><div class='add'>+		 &lt;&amp;clkc CLKID_FCLK_DIV4&gt;,</div><div class='add'>+		 &lt;&amp;clkc CLKID_FCLK_DIV3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwrc {</div><div class='ctx'> 	resets = &lt;&amp;reset RESET_VIU&gt;,</div><div class='ctx'> 		 &lt;&amp;reset RESET_VENC&gt;,</div><div class='ctx'> 		 &lt;&amp;reset RESET_VCBUS&gt;,</div><div class='hunk'>@@ -737,6 +777,9 @@</div><div class='ctx'> 		 &lt;&amp;reset RESET_VDI6&gt;,</div><div class='ctx'> 		 &lt;&amp;reset RESET_VENCL&gt;,</div><div class='ctx'> 		 &lt;&amp;reset RESET_VID_LOCK&gt;;</div><div class='add'>+	reset-names = "viu", "venc", "vcbus", "bt656",</div><div class='add'>+		      "dvin", "rdma", "venci", "vencp",</div><div class='add'>+		      "vdac", "vdi6", "vencl", "vid_lock";</div><div class='ctx'> 	clocks = &lt;&amp;clkc CLKID_VPU&gt;,</div><div class='ctx'> 	         &lt;&amp;clkc CLKID_VAPB&gt;;</div><div class='ctx'> 	clock-names = "vpu", "vapb";</div><div class='hunk'>@@ -843,7 +886,7 @@</div><div class='ctx'> </div><div class='ctx'> &amp;vpu {</div><div class='ctx'> 	compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";</div><div class='del'>-	power-domains = &lt;&amp;pwrc_vpu&gt;;</div><div class='add'>+	power-domains = &lt;&amp;pwrc PWRC_GXBB_VPU_ID&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;vdec {</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi<br/>index 6aaafff674f9..478e755cc87c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi</a></div><div class='hunk'>@@ -4,42 +4,14 @@</div><div class='ctx'>  * Author: Neil Armstrong &lt;narmstrong@baylibre.com&gt;</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-&amp;apb {</div><div class='del'>-	mali: gpu@c0000 {</div><div class='del'>-		compatible = "amlogic,meson-gxl-mali", "arm,mali-450";</div><div class='del'>-		reg = &lt;0x0 0xc0000 0x0 0x40000&gt;;</div><div class='del'>-		interrupts = &lt;GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-			     &lt;GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-			     &lt;GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-			     &lt;GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-			     &lt;GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-			     &lt;GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-			     &lt;GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-			     &lt;GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-			     &lt;GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-			     &lt;GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-		interrupt-names = "gp", "gpmmu", "pp", "pmu",</div><div class='del'>-			"pp0", "ppmmu0", "pp1", "ppmmu1",</div><div class='del'>-			"pp2", "ppmmu2";</div><div class='del'>-		clocks = &lt;&amp;clkc CLKID_CLK81&gt;, &lt;&amp;clkc CLKID_MALI&gt;;</div><div class='del'>-		clock-names = "bus", "core";</div><div class='add'>+#include "meson-gx-mali450.dtsi"</div><div class='ctx'> </div><div class='del'>-		/*</div><div class='del'>-		 * Mali clocking is provided by two identical clock paths</div><div class='del'>-		 * MALI_0 and MALI_1 muxed to a single clock by a glitch</div><div class='del'>-		 * free mux to safely change frequency while running.</div><div class='del'>-		 */</div><div class='del'>-		assigned-clocks = &lt;&amp;clkc CLKID_GP0_PLL&gt;,</div><div class='del'>-				  &lt;&amp;clkc CLKID_MALI_0_SEL&gt;,</div><div class='del'>-				  &lt;&amp;clkc CLKID_MALI_0&gt;,</div><div class='del'>-				  &lt;&amp;clkc CLKID_MALI&gt;; /* Glitch free mux */</div><div class='del'>-		assigned-clock-parents = &lt;0&gt;, /* Do Nothing */</div><div class='del'>-					 &lt;&amp;clkc CLKID_GP0_PLL&gt;,</div><div class='del'>-					 &lt;0&gt;, /* Do Nothing */</div><div class='del'>-					 &lt;&amp;clkc CLKID_MALI_0&gt;;</div><div class='del'>-		assigned-clock-rates = &lt;744000000&gt;,</div><div class='del'>-				       &lt;0&gt;, /* Do Nothing */</div><div class='del'>-				       &lt;744000000&gt;,</div><div class='del'>-				       &lt;0&gt;; /* Do Nothing */</div><div class='del'>-	};</div><div class='add'>+&amp;mali {</div><div class='add'>+	compatible = "amlogic,meson-gxl-mali", "arm,mali-450";</div><div class='add'>+</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CLK81&gt;, &lt;&amp;clkc CLKID_MALI&gt;;</div><div class='add'>+	clock-names = "bus", "core";</div><div class='add'>+</div><div class='add'>+	assigned-clocks = &lt;&amp;clkc CLKID_GP0_PLL&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;744000000&gt;;</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts<br/>index 4d5949496596..c6132fb71dfc 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts</a></div><div class='hunk'>@@ -8,8 +8,9 @@</div><div class='ctx'> /dts-v1/;</div><div class='ctx'> </div><div class='ctx'> #include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/meson-aiu.h&gt;</div><div class='ctx'> </div><div class='del'>-#include "meson-gxl-s905x.dtsi"</div><div class='add'>+#include "meson-gxl-s805x.dtsi"</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	compatible = "libretech,aml-s805x-ac", "amlogic,s805x",</div><div class='hunk'>@@ -41,7 +42,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	dc_5v: regulator-dc_5v {</div><div class='add'>+	dc_5v: regulator-dc-5v {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "DC_5V";</div><div class='ctx'> 		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='hunk'>@@ -88,7 +89,7 @@</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vcc_3v3: regulator-vcc_3v3 {</div><div class='add'>+	vcc_3v3: regulator-vcc-3v3 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VCC_3V3";</div><div class='ctx'> 		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='hunk'>@@ -97,7 +98,16 @@</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vddio_boot: regulator-vddio_boot {</div><div class='add'>+	vddio_ao18: regulator-vddio-ao18 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDIO_AO18";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vcc_3v3&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddio_boot: regulator-vddio-boot {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VDDIO_BOOT";</div><div class='ctx'> 		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='hunk'>@@ -105,6 +115,69 @@</div><div class='ctx'> 		vin-supply = &lt;&amp;vcc_3v3&gt;;</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "amlogic,gx-sound-card";</div><div class='add'>+		model = "LIBRETECH-AC";</div><div class='add'>+		audio-widgets = "Speaker", "9J5-3 LEFT",</div><div class='add'>+				"Speaker", "9J5-2 RIGHT";</div><div class='add'>+		audio-routing = "9J5-3 LEFT", "ACODEC LOLN",</div><div class='add'>+				"9J5-2 RIGHT", "ACODEC LORN";</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL1&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;294912000&gt;,</div><div class='add'>+				       &lt;270950400&gt;,</div><div class='add'>+				       &lt;393216000&gt;;</div><div class='add'>+</div><div class='add'>+		dai-link-0 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_I2S_FIFO&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-1 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_I2S_ENCODER&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;aiu AIU_HDMI CTRL_I2S&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			codec-1 {</div><div class='add'>+				sound-dai = &lt;&amp;aiu AIU_ACODEC CTRL_I2S&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-2 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_HDMI CTRL_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-3 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_ACODEC CTRL_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;acodec&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;acodec {</div><div class='add'>+	AVDD-supply = &lt;&amp;vddio_ao18&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;aiu {</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cec_AO {</div><div class='hunk'>@@ -228,7 +301,7 @@</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;nor_pins&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> </div><div class='del'>-	w25q32: spi-flash@0 {</div><div class='add'>+	w25q32: flash@0 {</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;1&gt;;</div><div class='ctx'> 		compatible = "jedec,spi-nor";</div><div class='hunk'>@@ -243,6 +316,7 @@</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;usb0 {</div><div class='add'>+&amp;usb {</div><div class='ctx'> 	status = "okay";</div><div class='add'>+	dr_mode = "host";</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts<br/>index a1119cfb0280..ca7c4e8e7cac 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts</a></div><div class='hunk'>@@ -8,8 +8,9 @@</div><div class='ctx'> /dts-v1/;</div><div class='ctx'> </div><div class='ctx'> #include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/meson-aiu.h&gt;</div><div class='ctx'> </div><div class='del'>-#include "meson-gxl-s905x.dtsi"</div><div class='add'>+#include "meson-gxl-s805x.dtsi"</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	compatible = "amlogic,p241", "amlogic,s805x", "amlogic,meson-gxl";</div><div class='hunk'>@@ -21,6 +22,13 @@</div><div class='ctx'> 		ethernet0 = &amp;ethmac;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	au2: analog-amplifier {</div><div class='add'>+		compatible = "simple-audio-amplifier";</div><div class='add'>+		sound-name-prefix = "AU2";</div><div class='add'>+		VCC-supply = &lt;&amp;vcc_5v&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;gpio GPIOH_5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	chosen {</div><div class='ctx'> 		stdout-path = "serial0:115200n8";</div><div class='ctx'> 	};</div><div class='hunk'>@@ -56,34 +64,42 @@</div><div class='ctx'> 		reg = &lt;0x0 0x0 0x0 0x20000000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vddio_boot: regulator-vddio_boot {</div><div class='add'>+	vddio_boot: regulator-vddio-boot {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VDDIO_BOOT";</div><div class='ctx'> 		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vddao_3v3: regulator-vddao_3v3 {</div><div class='add'>+	vddao_3v3: regulator-vddao-3v3 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VDDAO_3V3";</div><div class='ctx'> 		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='ctx'> 		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vddio_ao18: regulator-vddio_ao18 {</div><div class='add'>+	vddio_ao18: regulator-vddio-ao18 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VDDIO_AO18";</div><div class='ctx'> 		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vcc_3v3: regulator-vcc_3v3 {</div><div class='add'>+	vcc_3v3: regulator-vcc-3v3 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VCC_3V3";</div><div class='ctx'> 		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='ctx'> 		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	vcc_5v: regulator-vcc-5v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCC_5V";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+</div><div class='ctx'> 	emmc_pwrseq: emmc-pwrseq {</div><div class='ctx'> 		compatible = "mmc-pwrseq-emmc";</div><div class='ctx'> 		reset-gpios = &lt;&amp;gpio BOOT_9 GPIO_ACTIVE_LOW&gt;;</div><div class='hunk'>@@ -102,6 +118,71 @@</div><div class='ctx'> 		clocks = &lt;&amp;wifi32k&gt;;</div><div class='ctx'> 		clock-names = "ext_clock";</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "amlogic,gx-sound-card";</div><div class='add'>+		model = "GXL-P241";</div><div class='add'>+		audio-aux-devs = &lt;&amp;au2&gt;;</div><div class='add'>+		audio-widgets = "Line", "Lineout";</div><div class='add'>+		audio-routing = "AU2 INL", "ACODEC LOLN",</div><div class='add'>+				"AU2 INR", "ACODEC LORN",</div><div class='add'>+				"Lineout", "AU2 OUTL",</div><div class='add'>+				"Lineout", "AU2 OUTR";</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL1&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;294912000&gt;,</div><div class='add'>+				       &lt;270950400&gt;,</div><div class='add'>+				       &lt;393216000&gt;;</div><div class='add'>+</div><div class='add'>+		dai-link-0 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_I2S_FIFO&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-1 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_I2S_ENCODER&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;aiu AIU_HDMI CTRL_I2S&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			codec-1 {</div><div class='add'>+				sound-dai = &lt;&amp;aiu AIU_ACODEC CTRL_I2S&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-2 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_HDMI CTRL_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-3 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_ACODEC CTRL_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;acodec&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;acodec {</div><div class='add'>+	AVDD-supply = &lt;&amp;vddio_ao18&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;aiu {</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cec_AO {</div><div class='hunk'>@@ -136,6 +217,7 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;hdmi_hpd_pins&gt;, &lt;&amp;hdmi_i2c_pins&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='add'>+	hdmi-supply = &lt;&amp;vcc_5v&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;hdmi_tx_tmds_port {</div><div class='hunk'>@@ -198,8 +280,6 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pwm_e_pins&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='del'>-	clocks = &lt;&amp;clkc CLKID_FCLK_DIV4&gt;;</div><div class='del'>-	clock-names = "clkin0";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* This is connected to the Bluetooth module: */</div><div class='hunk'>@@ -216,6 +296,11 @@</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;usb0 {</div><div class='add'>+&amp;usb {</div><div class='ctx'> 	status = "okay";</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb2_phy0 {</div><div class='add'>+	phy-supply = &lt;&amp;vcc_5v&gt;;</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x.dtsi<br/>new file mode 100644<br/>index 000000000000..29975849822c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxl-s805x.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxl-s805x.dtsi</a></div><div class='hunk'>@@ -0,0 +1,23 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2020 BayLibre SAS</div><div class='add'>+ * Author: Neil Armstrong &lt;narmstrong@baylibre.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "meson-gxl-s905x.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "amlogic,s805x", "amlogic,meson-gxl";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* The S805X Package doesn't seem to handle the 744MHz OPP correctly */</div><div class='add'>+&amp;gpu_opp_table {</div><div class='add'>+	opp-744000000 {</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mali {</div><div class='add'>+	/delete-property/ assigned-clocks;</div><div class='add'>+	/delete-property/ assigned-clock-rates;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s805y-xiaomi-aquaman.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s805y-xiaomi-aquaman.dts<br/>new file mode 100644<br/>index 000000000000..cac15b89c573<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxl-s805y-xiaomi-aquaman.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxl-s805y-xiaomi-aquaman.dts</a></div><div class='hunk'>@@ -0,0 +1,262 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2025 Ferass El Hafidi &lt;funderscore@postmarketos.org&gt;</div><div class='add'>+ * Heavily based on meson-gxl-s805x-p241.dtb:</div><div class='add'>+ *  - Copyright (c) 2018 BayLibre, SAS.</div><div class='add'>+ *    Author: Neil Armstrong &lt;narmstrong@baylibre.com&gt;</div><div class='add'>+ *    Author: Jerome Brunet &lt;jbrunet@baylibre.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/meson-aiu.h&gt;</div><div class='add'>+</div><div class='add'>+#include "meson-gxl-s805y.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "xiaomi,aquaman", "amlogic,s805y", "amlogic,meson-gxl";</div><div class='add'>+	model = "Xiaomi Mi TV Stick (aquaman)";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart_AO;</div><div class='add'>+		serial1 = &amp;uart_A;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	emmc_pwrseq: emmc-pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-emmc";</div><div class='add'>+		reset-gpios = &lt;&amp;gpio BOOT_9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdmi-connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		type = "a";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			hdmi_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_tx_tmds_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-white {</div><div class='add'>+			color = &lt;LED_COLOR_ID_WHITE&gt;;</div><div class='add'>+			function = LED_FUNCTION_POWER;</div><div class='add'>+			gpios = &lt;&amp;gpio GPIODV_24 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "on";</div><div class='add'>+			panic-indicator;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x0 0x0 0x40000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddio_boot: regulator-vddio-boot {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDIO_BOOT";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddao_3v3: regulator-vddao-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDAO_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddio_ao18: regulator-vddio-ao18 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDIO_AO18";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vcc_3v3: regulator-vcc-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCC_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vcc_5v: regulator-vcc-5v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCC_5V";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	emmc_pwrseq: emmc-pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-emmc";</div><div class='add'>+		reset-gpios = &lt;&amp;gpio BOOT_9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wifi32k: wifi32k {</div><div class='add'>+		compatible = "pwm-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;32768&gt;;</div><div class='add'>+		pwms = &lt;&amp;pwm_ef 0 30518 0&gt;; /* PWM_E at 32.768KHz */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdio_pwrseq: sdio-pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-simple";</div><div class='add'>+		reset-gpios = &lt;&amp;gpio GPIOX_6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		clocks = &lt;&amp;wifi32k&gt;;</div><div class='add'>+		clock-names = "ext_clock";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "amlogic,gx-sound-card";</div><div class='add'>+		model = "XIAOMI-AQUAMAN";</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL1&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;294912000&gt;,</div><div class='add'>+				       &lt;270950400&gt;,</div><div class='add'>+				       &lt;393216000&gt;;</div><div class='add'>+</div><div class='add'>+		dai-link-0 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_I2S_FIFO&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-1 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_I2S_ENCODER&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;aiu AIU_HDMI CTRL_I2S&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-2 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_HDMI CTRL_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;aiu {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cec_AO {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;ao_cec_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	hdmi-phandle = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;hdmi_hpd_pins&gt;, &lt;&amp;hdmi_i2c_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	hdmi-supply = &lt;&amp;vcc_5v&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx_tmds_port {</div><div class='add'>+	hdmi_tx_tmds_out: endpoint {</div><div class='add'>+		remote-endpoint = &lt;&amp;hdmi_connector_in&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;saradc {</div><div class='add'>+	status = "okay";</div><div class='add'>+	vref-supply = &lt;&amp;vddio_ao18&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Wireless SDIO Module (Amlogic W155S1 / Realtek RTL8821CS) */</div><div class='add'>+&amp;sd_emmc_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdio_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;sdio_clk_gate_pins&gt;;</div><div class='add'>+	pinctrl-names = "default", "clk-gate";</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	max-frequency = &lt;50000000&gt;;</div><div class='add'>+</div><div class='add'>+	non-removable;</div><div class='add'>+	disable-wp;</div><div class='add'>+</div><div class='add'>+	/* WiFi firmware requires power to be kept while in suspend */</div><div class='add'>+	keep-power-in-suspend;</div><div class='add'>+</div><div class='add'>+	mmc-pwrseq = &lt;&amp;sdio_pwrseq&gt;;</div><div class='add'>+</div><div class='add'>+	vmmc-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;vddio_boot&gt;;</div><div class='add'>+</div><div class='add'>+	sdio: wifi@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* eMMC */</div><div class='add'>+&amp;sd_emmc_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;emmc_pins&gt;, &lt;&amp;emmc_ds_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;emmc_clk_gate_pins&gt;;</div><div class='add'>+	pinctrl-names = "default", "clk-gate";</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	cap-mmc-highspeed;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	disable-wp;</div><div class='add'>+	mmc-ddr-1_8v;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+</div><div class='add'>+	mmc-pwrseq = &lt;&amp;emmc_pwrseq&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;vcc_3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;vddio_boot&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm_ef {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm_e_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * This is connected to the Bluetooth module</div><div class='add'>+ * Note: There's no driver for the Bluetooth module of some variants yet.</div><div class='add'>+ */</div><div class='add'>+&amp;uart_A {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart_a_pins&gt;, &lt;&amp;uart_a_cts_rts_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart_AO {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart_ao_a_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb {</div><div class='add'>+	status = "okay";</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	vbus-supply = &lt;&amp;vcc_5v&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s805y.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s805y.dtsi<br/>new file mode 100644<br/>index 000000000000..49b29b71f732<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxl-s805y.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxl-s805y.dtsi</a></div><div class='hunk'>@@ -0,0 +1,10 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2025 Ferass El Hafidi &lt;funderscore@postmarketos.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "meson-gxl-s805x.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "amlogic,s805y", "amlogic,meson-gxl";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-mecool-kii-pro.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-mecool-kii-pro.dts<br/>new file mode 100644<br/>index 000000000000..a4fa186f0458<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-mecool-kii-pro.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxl-s905d-mecool-kii-pro.dts</a></div><div class='hunk'>@@ -0,0 +1,84 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Author: Christian Hewitt &lt;christianshewitt@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "meson-gxl-s905d.dtsi"</div><div class='add'>+#include "meson-gx-p23x-q20x.dtsi"</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "videostrong,gxl-kii-pro", "amlogic,s905d", "amlogic,meson-gxl";</div><div class='add'>+	model = "MeCool KII Pro";</div><div class='add'>+</div><div class='add'>+	adc-keys {</div><div class='add'>+		compatible = "adc-keys";</div><div class='add'>+		io-channels = &lt;&amp;saradc 0&gt;;</div><div class='add'>+		io-channel-names = "buttons";</div><div class='add'>+		keyup-threshold-microvolt = &lt;1710000&gt;;</div><div class='add'>+</div><div class='add'>+		button-function {</div><div class='add'>+			label = "Update";</div><div class='add'>+			linux,code = &lt;KEY_VENDOR&gt;;</div><div class='add'>+			press-threshold-microvolt = &lt;10000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys-polled {</div><div class='add'>+		compatible = "gpio-keys-polled";</div><div class='add'>+		poll-interval = &lt;100&gt;;</div><div class='add'>+</div><div class='add'>+		button {</div><div class='add'>+			label = "power";</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-blue {</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			function = LED_FUNCTION_POWER;</div><div class='add'>+			gpios = &lt;&amp;gpio GPIODV_24 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "on";</div><div class='add'>+			panic-indicator;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethmac {</div><div class='add'>+	phy-mode = "rmii";</div><div class='add'>+	phy-handle = &lt;&amp;internal_phy&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ir {</div><div class='add'>+	linux,rc-map-name = "rc-mecool-kii-pro";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sd_emmc_a {</div><div class='add'>+	brcmf: wifi@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		compatible = "brcm,bcm4329-fmac";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart_A {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart_a_pins&gt;, &lt;&amp;uart_a_cts_rts_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "brcm,bcm43438-bt";</div><div class='add'>+		shutdown-gpios = &lt;&amp;gpio GPIOX_17 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		max-speed = &lt;2000000&gt;;</div><div class='add'>+		clocks = &lt;&amp;wifi32k&gt;;</div><div class='add'>+		clock-names = "lpo";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts<br/>index b08c4537f260..7dffeb5931c9 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts</a></div><div class='hunk'>@@ -30,11 +30,9 @@</div><div class='ctx'> </div><div class='ctx'> 	gpio-keys-polled {</div><div class='ctx'> 		compatible = "gpio-keys-polled";</div><div class='del'>-		#address-cells = &lt;1&gt;;</div><div class='del'>-		#size-cells = &lt;0&gt;;</div><div class='ctx'> 		poll-interval = &lt;100&gt;;</div><div class='ctx'> </div><div class='del'>-		button@0 {</div><div class='add'>+		button {</div><div class='ctx'> 			label = "power";</div><div class='ctx'> 			linux,code = &lt;KEY_POWER&gt;;</div><div class='ctx'> 			gpios = &lt;&amp;gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW&gt;;</div><div class='hunk'>@@ -82,7 +80,7 @@</div><div class='ctx'> </div><div class='ctx'> 		/* External PHY reset is shared with internal PHY Led signal */</div><div class='ctx'> 		reset-assert-us = &lt;10000&gt;;</div><div class='del'>-		reset-deassert-us = &lt;30000&gt;;</div><div class='add'>+		reset-deassert-us = &lt;80000&gt;;</div><div class='ctx'> 		reset-gpios = &lt;&amp;gpio GPIOZ_14 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> </div><div class='ctx'> 		interrupt-parent = &lt;&amp;gpio_intc&gt;;</div><div class='hunk'>@@ -104,8 +102,7 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;sd_emmc_a {</div><div class='del'>-	brcmf: wifi@1 {</div><div class='add'>+	sdio: wifi@1 {</div><div class='ctx'> 		reg = &lt;1&gt;;</div><div class='del'>-		compatible = "brcm,bcm4329-fmac";</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts<br/>index 92c425d0259c..ff9145d49090 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts</a></div><div class='hunk'>@@ -21,8 +21,7 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;sd_emmc_a {</div><div class='del'>-	brcmf: wifi@1 {</div><div class='add'>+	sdio: wifi@1 {</div><div class='ctx'> 		reg = &lt;1&gt;;</div><div class='del'>-		compatible = "brcm,bcm4329-fmac";</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts<br/>index b5667f1fb2c8..393d3cb33b9e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts</a></div><div class='hunk'>@@ -18,7 +18,7 @@</div><div class='ctx'> 	leds {</div><div class='ctx'> 		compatible = "gpio-leds";</div><div class='ctx'> </div><div class='del'>-		status {</div><div class='add'>+		led {</div><div class='ctx'> 			label = "n1:white:status";</div><div class='ctx'> 			gpios = &lt;&amp;gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 			default-state = "on";</div><div class='hunk'>@@ -29,3 +29,7 @@</div><div class='ctx'> &amp;cvbs_vdac_port {</div><div class='ctx'> 	status = "disabled";</div><div class='ctx'> };</div><div class='add'>+</div><div class='add'>+&amp;usb {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-sml5442tw.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-sml5442tw.dts<br/>new file mode 100644<br/>index 000000000000..c490dbbf063b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-sml5442tw.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxl-s905d-sml5442tw.dts</a></div><div class='hunk'>@@ -0,0 +1,83 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) Christian Hewitt &lt;christianshewitt@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "meson-gxl-s905d.dtsi"</div><div class='add'>+#include "meson-gx-p23x-q20x.dtsi"</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "smartlabs,sml5442tw", "amlogic,s905d", "amlogic,meson-gxl";</div><div class='add'>+	model = "SmartLabs SML-5442TW";</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-yellow {</div><div class='add'>+			color = &lt;LED_COLOR_ID_YELLOW&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			gpios = &lt;&amp;gpio_ao GPIOAO_6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-blue {</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			gpios = &lt;&amp;gpio GPIODV_28 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-green {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			gpios = &lt;&amp;gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "on";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-red {</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			gpios = &lt;&amp;gpio GPIODV_27 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethmac {</div><div class='add'>+	status = "okay";</div><div class='add'>+	phy-mode = "rmii";</div><div class='add'>+	phy-handle = &lt;&amp;internal_phy&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c_A {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c_a_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;internal_phy {</div><div class='add'>+	pinctrl-0 = &lt;&amp;eth_link_led_pins&gt;, &lt;&amp;eth_act_led_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ir {</div><div class='add'>+        linux,rc-map-name = "rc-khamsin";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* This is connected to the Bluetooth module: */</div><div class='add'>+&amp;uart_A {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart_a_pins&gt;, &lt;&amp;uart_a_cts_rts_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "qcom,qca9377-bt";</div><div class='add'>+		enable-gpios = &lt;&amp;gpio GPIOX_17 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		max-speed = &lt;2000000&gt;;</div><div class='add'>+		clocks = &lt;&amp;wifi32k&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-vero4k-plus.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-vero4k-plus.dts<br/>new file mode 100644<br/>index 000000000000..595b49085074<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-vero4k-plus.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxl-s905d-vero4k-plus.dts</a></div><div class='hunk'>@@ -0,0 +1,115 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Author: Christian Hewitt &lt;christianshewitt@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "meson-gxl-s905d.dtsi"</div><div class='add'>+#include "meson-gx-p23x-q20x.dtsi"</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "osmc,vero4k-plus", "amlogic,s905d", "amlogic,meson-gxl";</div><div class='add'>+	model = "OSMC Vero 4K Plus";</div><div class='add'>+</div><div class='add'>+	gpio-keys-polled {</div><div class='add'>+		compatible = "gpio-keys-polled";</div><div class='add'>+		poll-interval = &lt;20&gt;;</div><div class='add'>+</div><div class='add'>+		button {</div><div class='add'>+			label = "power";</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-standby {</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			function = LED_FUNCTION_POWER;</div><div class='add'>+			gpios = &lt;&amp;gpio_ao GPIOAO_9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+			panic-indicator;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethmac {</div><div class='add'>+	pinctrl-0 = &lt;&amp;eth_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	phy-mode = "rgmii-txid";</div><div class='add'>+	phy-handle = &lt;&amp;external_phy&gt;;</div><div class='add'>+</div><div class='add'>+	amlogic,tx-delay-ns = &lt;0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;external_mdio {</div><div class='add'>+	external_phy: ethernet-phy@0 {</div><div class='add'>+		/* Realtek RTL8211F (0x001cc916) */</div><div class='add'>+		pinctrl-0 = &lt;&amp;eth_phy_irq_pin&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		max-speed = &lt;1000&gt;;</div><div class='add'>+</div><div class='add'>+		reset-assert-us = &lt;10000&gt;;</div><div class='add'>+		reset-deassert-us = &lt;80000&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio GPIOZ_14 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio_intc&gt;;</div><div class='add'>+		interrupts = &lt;25 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_periphs {</div><div class='add'>+	/* Ensure the phy irq pin is properly configured as input */</div><div class='add'>+	eth_phy_irq_pin: eth-phy-irq {</div><div class='add'>+		mux {</div><div class='add'>+			groups = "GPIOZ_15";</div><div class='add'>+			function = "gpio_periphs";</div><div class='add'>+			bias-disable;</div><div class='add'>+			output-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sd_emmc_a {</div><div class='add'>+	brcmf: wifi@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		compatible = "brcm,bcm4329-fmac";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart_A {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart_a_pins&gt;, &lt;&amp;uart_a_cts_rts_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "brcm,bcm43438-bt";</div><div class='add'>+		shutdown-gpios = &lt;&amp;gpio GPIOX_17 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		max-speed = &lt;2000000&gt;;</div><div class='add'>+		clocks = &lt;&amp;wifi32k&gt;;</div><div class='add'>+		clock-names = "lpo";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb2_phy0 {</div><div class='add'>+	/* HDMI_5V also supplies the USB VBUS */</div><div class='add'>+	phy-supply = &lt;&amp;hdmi_5v&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb2_phy0 {</div><div class='add'>+	/* HDMI_5V also supplies the USB VBUS */</div><div class='add'>+	phy-supply = &lt;&amp;hdmi_5v&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts<br/>new file mode 100644<br/>index 000000000000..4ca90ac947b7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts</a></div><div class='hunk'>@@ -0,0 +1,245 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2021 Vyacheslav Bocharov &lt;adeep@lexina.in&gt;</div><div class='add'>+ * Copyright (c) 2020 JetHome</div><div class='add'>+ * Author: Aleksandr Kazantsev &lt;ak@tvip.ru&gt;</div><div class='add'>+ * Author: Alexey Shevelkin &lt;ash@tvip.ru&gt;</div><div class='add'>+ * Author: Vyacheslav Bocharov &lt;adeep@lexina.in&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "meson-gxl.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "jethome,jethub-j80", "amlogic,s905w", "amlogic,meson-gxl";</div><div class='add'>+	model = "JetHome JetHub J80";</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x0 0x0 0x40000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		linux,cma {</div><div class='add'>+			size = &lt;0x0 0x1000000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart_AO;   /* Console */</div><div class='add'>+		serial1 = &amp;uart_A;    /* Bluetooth */</div><div class='add'>+		serial2 = &amp;uart_AO_B; /* Wireless module 1 */</div><div class='add'>+		serial3 = &amp;uart_C;    /* Wireless module 2 */</div><div class='add'>+		ethernet0 = &amp;ethmac;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddio_ao18: regulator-vddio-ao18 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDIO_AO18";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddio_boot: regulator-vddio-boot {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDIO_BOOT";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddao_3v3: regulator-vddao-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDAO_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vcc_3v3: regulator-vcc-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCC_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	emmc_pwrseq: emmc-pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-emmc";</div><div class='add'>+		reset-gpios = &lt;&amp;gpio BOOT_9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wifi32k: wifi32k {</div><div class='add'>+		compatible = "pwm-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;32768&gt;;</div><div class='add'>+		pwms = &lt;&amp;pwm_ef 0 30518 0&gt;; /* PWM_E at 32.768KHz */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdio_pwrseq: sdio-pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-simple";</div><div class='add'>+		reset-gpios = &lt;&amp;gpio GPIOX_6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		clocks = &lt;&amp;wifi32k&gt;;</div><div class='add'>+		clock-names = "ext_clock";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;efuse {</div><div class='add'>+	bt_mac: bt-mac@6 {</div><div class='add'>+		reg = &lt;0x6 0x6&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wifi_mac: wifi-mac@c {</div><div class='add'>+		reg = &lt;0xc 0x6&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sn {</div><div class='add'>+	reg = &lt;0x32 0x20&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eth_mac {</div><div class='add'>+	reg = &lt;0x0 0x6&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;bid {</div><div class='add'>+	reg = &lt;0x12 0x20&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb {</div><div class='add'>+	status = "okay";</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm_ef {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm_e_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;saradc {</div><div class='add'>+	status = "okay";</div><div class='add'>+	vref-supply = &lt;&amp;vddio_ao18&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Wireless SDIO Module */</div><div class='add'>+&amp;sd_emmc_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdio_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;sdio_clk_gate_pins&gt;;</div><div class='add'>+	pinctrl-names = "default", "clk-gate";</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	max-frequency = &lt;50000000&gt;;</div><div class='add'>+</div><div class='add'>+	non-removable;</div><div class='add'>+	disable-wp;</div><div class='add'>+</div><div class='add'>+	/* WiFi firmware requires power to be kept while in suspend */</div><div class='add'>+	keep-power-in-suspend;</div><div class='add'>+</div><div class='add'>+	mmc-pwrseq = &lt;&amp;sdio_pwrseq&gt;;</div><div class='add'>+</div><div class='add'>+	vmmc-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;vddio_boot&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SD card */</div><div class='add'>+&amp;sd_emmc_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdcard_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;sdcard_clk_gate_pins&gt;;</div><div class='add'>+	pinctrl-names = "default", "clk-gate";</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	max-frequency = &lt;50000000&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+</div><div class='add'>+	cd-gpios = &lt;&amp;gpio CARD_6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+	vmmc-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;vddio_boot&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* eMMC */</div><div class='add'>+&amp;sd_emmc_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;emmc_pins&gt;, &lt;&amp;emmc_ds_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;emmc_clk_gate_pins&gt;;</div><div class='add'>+	pinctrl-names = "default", "clk-gate";</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	cap-mmc-highspeed;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	disable-wp;</div><div class='add'>+	mmc-ddr-1_8v;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+</div><div class='add'>+	mmc-pwrseq = &lt;&amp;emmc_pwrseq&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;vcc_3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;vddio_boot&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Console UART */</div><div class='add'>+&amp;uart_AO {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart_ao_a_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* S905W only has access to its internal PHY */</div><div class='add'>+&amp;ethmac {</div><div class='add'>+	status = "okay";</div><div class='add'>+	phy-mode = "rmii";</div><div class='add'>+	phy-handle = &lt;&amp;internal_phy&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;internal_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;eth_link_led_pins&gt;, &lt;&amp;eth_act_led_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart_A {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart_a_pins&gt;, &lt;&amp;uart_a_cts_rts_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "realtek,rtl8822cs-bt";</div><div class='add'>+		enable-gpios = &lt;&amp;gpio GPIOX_17 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		host-wake-gpios = &lt;&amp;gpio GPIOX_18 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+       };</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart_C {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart_c_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart_AO_B {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart_ao_b_pins&gt;, &lt;&amp;uart_ao_b_cts_rts_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c_B {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c_b_pins&gt;;</div><div class='add'>+</div><div class='add'>+	pcf8563: rtc@51 {</div><div class='add'>+		compatible = "nxp,pcf8563";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-p281.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-p281.dts<br/>index 6509c4950950..ecc9df7ca023 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-p281.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxl-s905w-p281.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-p281.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxl-s905w-p281.dts</a></div><div class='hunk'>@@ -20,3 +20,7 @@</div><div class='ctx'> 		reg = &lt;0x0 0x0 0x0 0x40000000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='add'>+</div><div class='add'>+&amp;usb {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-tx3-mini.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-tx3-mini.dts<br/>index dd729ac2300d..6705c2082a78 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-tx3-mini.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxl-s905w-tx3-mini.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-tx3-mini.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxl-s905w-tx3-mini.dts</a></div><div class='hunk'>@@ -24,3 +24,7 @@</div><div class='ctx'> &amp;ir {</div><div class='ctx'> 	linux,rc-map-name = "rc-tanix-tx3mini";</div><div class='ctx'> };</div><div class='add'>+</div><div class='add'>+&amp;usb {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts<br/>index c8d74e61dec1..62a2da766a00 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts</a></div><div class='hunk'>@@ -42,21 +42,21 @@</div><div class='ctx'> 			 &lt;3300000 1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vddio_boot: regulator-vddio_boot {</div><div class='add'>+	vddio_boot: regulator-vddio-boot {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VDDIO_BOOT";</div><div class='ctx'> 		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vddao_3v3: regulator-vddao_3v3 {</div><div class='add'>+	vddao_3v3: regulator-vddao-3v3 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VDDAO_3V3";</div><div class='ctx'> 		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='ctx'> 		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vcc_3v3: regulator-vcc_3v3 {</div><div class='add'>+	vcc_3v3: regulator-vcc-3v3 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VCC_3V3";</div><div class='ctx'> 		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='hunk'>@@ -115,8 +115,6 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pwm_e_pins&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='del'>-	clocks = &lt;&amp;clkc CLKID_FCLK_DIV4&gt;;</div><div class='del'>-	clock-names = "clkin0";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* SD card */</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts<br/>index 440bc23c7342..4e89d6f6bb57 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts</a></div><div class='hunk'>@@ -5,9 +5,9 @@</div><div class='ctx'> </div><div class='ctx'> /dts-v1/;</div><div class='ctx'> </div><div class='del'>-#include &lt;dt-bindings/input/input.h&gt;</div><div class='del'>-</div><div class='ctx'> #include "meson-gxl-s905x-p212.dtsi"</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/meson-aiu.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	compatible = "khadas,vim", "amlogic,s905x", "amlogic,meson-gxl";</div><div class='hunk'>@@ -42,10 +42,10 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pwmleds {</div><div class='add'>+	led-controller {</div><div class='ctx'> 		compatible = "pwm-leds";</div><div class='ctx'> </div><div class='del'>-		power {</div><div class='add'>+		led-1 {</div><div class='ctx'> 			label = "vim:red:power";</div><div class='ctx'> 			pwms = &lt;&amp;pwm_AO_ab 1 7812500 0&gt;;</div><div class='ctx'> 			max-brightness = &lt;255&gt;;</div><div class='hunk'>@@ -63,6 +63,48 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "amlogic,gx-sound-card";</div><div class='add'>+		model = "KHADAS-VIM";</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL1&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;294912000&gt;,</div><div class='add'>+				       &lt;270950400&gt;,</div><div class='add'>+				       &lt;393216000&gt;;</div><div class='add'>+</div><div class='add'>+		dai-link-0 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_I2S_FIFO&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-1 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_I2S_ENCODER&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;aiu AIU_HDMI CTRL_I2S&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-2 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_HDMI CTRL_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;aiu {</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cec_AO {</div><div class='hunk'>@@ -97,12 +139,10 @@</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> </div><div class='ctx'> 	rtc: rtc@51 {</div><div class='del'>-		/* has to be enabled manually when a battery is connected: */</div><div class='del'>-		status = "disabled";</div><div class='add'>+		status = "okay";</div><div class='ctx'> 		compatible = "haoyu,hym8563";</div><div class='ctx'> 		reg = &lt;0x51&gt;;</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='del'>-		clock-frequency = &lt;32768&gt;;</div><div class='ctx'> 		clock-output-names = "xin32k";</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='hunk'>@@ -171,8 +211,6 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pwm_ao_a_3_pins&gt;, &lt;&amp;pwm_ao_b_pins&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='del'>-	clocks = &lt;&amp;xtal&gt; , &lt;&amp;xtal&gt;;</div><div class='del'>-	clock-names = "clkin0", "clkin1" ;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;pwm_ef {</div><div class='hunk'>@@ -180,20 +218,7 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;sd_emmc_a {</div><div class='del'>-	brcmf: wifi@1 {</div><div class='del'>-		reg = &lt;1&gt;;</div><div class='del'>-		compatible = "brcm,bcm4329-fmac";</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;uart_A {</div><div class='del'>-	bluetooth {</div><div class='del'>-		compatible = "brcm,bcm43438-bt";</div><div class='del'>-		shutdown-gpios = &lt;&amp;gpio GPIOX_17 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-		max-speed = &lt;2000000&gt;;</div><div class='del'>-		clocks = &lt;&amp;wifi32k&gt;;</div><div class='del'>-		clock-names = "lpo";</div><div class='del'>-	};</div><div class='add'>+	max-frequency = &lt;100000000&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* This is brought out on the Linux_RX (18) and Linux_TX (19) pins: */</div><div class='hunk'>@@ -207,3 +232,7 @@</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;uart_ao_b_pins&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> };</div><div class='add'>+</div><div class='add'>+&amp;usb {</div><div class='add'>+	dr_mode = "peripheral";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts<br/>new file mode 100644<br/>index 000000000000..6cbdfde00e12<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts</a></div><div class='hunk'>@@ -0,0 +1,316 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2020 BayLibre, SAS.</div><div class='add'>+ * Author: Jerome Brunet &lt;jbrunet@baylibre.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/meson-aiu.h&gt;</div><div class='add'>+</div><div class='add'>+#include "meson-gxl-s905x.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "libretech,aml-s905x-cc-v2", "amlogic,s905x",</div><div class='add'>+		     "amlogic,meson-gxl";</div><div class='add'>+	model = "Libre Computer AML-S905X-CC V2";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart_AO;</div><div class='add'>+		ethernet0 = &amp;ethmac;</div><div class='add'>+		spi0 = &amp;spifc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	emmc_pwrseq: emmc-pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-emmc";</div><div class='add'>+		reset-gpios = &lt;&amp;gpio BOOT_9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdmi-connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		type = "a";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			hdmi_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_tx_tmds_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-blue {</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			gpios = &lt;&amp;gpio GPIODV_24 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+			panic-indicator;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-green {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_DISK_ACTIVITY;</div><div class='add'>+			gpios = &lt;&amp;gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "disk-activity";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x0 0x0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ao_5v: regulator-ao-5v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "AO_5V";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;dc_in&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dc_in: regulator-dc-in {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "DC_IN";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vcck: regulator-vcck {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCCK";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;ao_5v&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vcc_card: regulator-vcc-card {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCC_CARD";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vddio_ao3v3&gt;;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;gpio GPIOCLK_1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vcc5v: regulator-vcc5v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCC5V";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;ao_5v&gt;;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;gpio GPIOH_3 GPIO_OPEN_DRAIN&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddio_ao3v3: regulator-vddio-ao3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDIO_AO3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;ao_5v&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddio_card: regulator-vddio-card {</div><div class='add'>+		compatible = "regulator-gpio";</div><div class='add'>+		regulator-name = "VDDIO_CARD";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+</div><div class='add'>+		gpios = &lt;&amp;gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		gpios-states = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		states = &lt;3300000 0&gt;,</div><div class='add'>+			 &lt;1800000 1&gt;;</div><div class='add'>+</div><div class='add'>+		regulator-settling-time-up-us = &lt;200&gt;;</div><div class='add'>+		regulator-settling-time-down-us = &lt;50000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddio_ao18: regulator-vddio-ao18 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDIO_AO18";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vddio_ao3v3&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vcc_1v8: regulator-vcc-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCC 1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vddio_ao3v3&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "amlogic,gx-sound-card";</div><div class='add'>+		model = "LIBRETECH-CC-V2";</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL1&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;294912000&gt;,</div><div class='add'>+				       &lt;270950400&gt;,</div><div class='add'>+				       &lt;393216000&gt;;</div><div class='add'>+</div><div class='add'>+		dai-link-0 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_I2S_FIFO&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-1 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_I2S_ENCODER&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;aiu AIU_HDMI CTRL_I2S&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-2 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_HDMI CTRL_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;aiu {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cec_AO {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;ao_cec_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	hdmi-phandle = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethmac {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;internal_phy {</div><div class='add'>+	pinctrl-0 = &lt;&amp;eth_link_led_pins&gt;, &lt;&amp;eth_act_led_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ir {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;remote_input_ao_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;hdmi_hpd_pins&gt;, &lt;&amp;hdmi_i2c_pins&gt;;</div><div class='add'>+	hdmi-supply = &lt;&amp;vcc5v&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx_tmds_port {</div><div class='add'>+	hdmi_tx_tmds_out: endpoint {</div><div class='add'>+		remote-endpoint = &lt;&amp;hdmi_connector_in&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;saradc {</div><div class='add'>+	status = "okay";</div><div class='add'>+	vref-supply = &lt;&amp;vddio_ao18&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SD card */</div><div class='add'>+&amp;sd_emmc_b {</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdcard_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;sdcard_clk_gate_pins&gt;;</div><div class='add'>+	pinctrl-names = "default", "clk-gate";</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	sd-uhs-sdr12;</div><div class='add'>+	sd-uhs-sdr25;</div><div class='add'>+	sd-uhs-sdr50;</div><div class='add'>+	sd-uhs-ddr50;</div><div class='add'>+	max-frequency = &lt;100000000&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+</div><div class='add'>+	cd-gpios = &lt;&amp;gpio CARD_6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+	vmmc-supply = &lt;&amp;vcc_card&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;vddio_card&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* eMMC */</div><div class='add'>+&amp;sd_emmc_c {</div><div class='add'>+	pinctrl-0 = &lt;&amp;emmc_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;emmc_clk_gate_pins&gt;;</div><div class='add'>+	pinctrl-names = "default", "clk-gate";</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	cap-mmc-highspeed;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+</div><div class='add'>+	mmc-pwrseq = &lt;&amp;emmc_pwrseq&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;vddio_ao3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;vcc_1v8&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spifc {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;nor_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	nor_4u1: flash@0 {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;3000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart_AO {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart_ao_a_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb {</div><div class='add'>+	status = "okay";</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb2_phy0 {</div><div class='add'>+	phy-supply = &lt;&amp;vcc5v&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb2_phy1 {</div><div class='add'>+	phy-supply = &lt;&amp;vcc5v&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts<br/>index e8348b2728db..401064b0428d 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts</a></div><div class='hunk'>@@ -8,6 +8,7 @@</div><div class='ctx'> /dts-v1/;</div><div class='ctx'> </div><div class='ctx'> #include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/meson-aiu.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "meson-gxl-s905x.dtsi"</div><div class='ctx'> </div><div class='hunk'>@@ -21,6 +22,13 @@</div><div class='ctx'> 		ethernet0 = &amp;ethmac;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	dio2133: analog-amplifier {</div><div class='add'>+		compatible = "simple-audio-amplifier";</div><div class='add'>+		sound-name-prefix = "AU2";</div><div class='add'>+		VCC-supply = &lt;&amp;hdmi_5v&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;gpio GPIOH_5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	chosen {</div><div class='ctx'> 		stdout-path = "serial0:115200n8";</div><div class='ctx'> 	};</div><div class='hunk'>@@ -54,14 +62,14 @@</div><div class='ctx'> 	leds {</div><div class='ctx'> 		compatible = "gpio-leds";</div><div class='ctx'> </div><div class='del'>-		system {</div><div class='add'>+		led-system {</div><div class='ctx'> 			label = "librecomputer:system-status";</div><div class='ctx'> 			gpios = &lt;&amp;gpio GPIODV_24 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 			default-state = "on";</div><div class='ctx'> 			panic-indicator;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		blue {</div><div class='add'>+		led-blue {</div><div class='ctx'> 			label = "librecomputer:blue";</div><div class='ctx'> 			gpios = &lt;&amp;gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 			linux,default-trigger = "heartbeat";</div><div class='hunk'>@@ -85,7 +93,7 @@</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vcc_3v3: regulator-vcc_3v3 {</div><div class='add'>+	vcc_3v3: regulator-vcc-3v3 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VCC_3V3";</div><div class='ctx'> 		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='hunk'>@@ -109,7 +117,7 @@</div><div class='ctx'> 		regulator-settling-time-down-us = &lt;50000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vddio_ao18: regulator-vddio_ao18 {</div><div class='add'>+	vddio_ao18: regulator-vddio-ao18 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VDDIO_AO18";</div><div class='ctx'> 		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='hunk'>@@ -117,13 +125,78 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	/* This is provided by LDOs on the eMMC daugther card */</div><div class='del'>-	vddio_boot: regulator-vddio_boot {</div><div class='add'>+	vddio_boot: regulator-vddio-boot {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VDDIO_BOOT";</div><div class='ctx'> 		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 		vin-supply = &lt;&amp;vcc_3v3&gt;;</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "amlogic,gx-sound-card";</div><div class='add'>+		model = "LIBRETECH-CC";</div><div class='add'>+		audio-aux-devs = &lt;&amp;dio2133&gt;;</div><div class='add'>+		audio-widgets = "Line", "Lineout";</div><div class='add'>+		audio-routing = "AU2 INL", "ACODEC LOLN",</div><div class='add'>+				"AU2 INR", "ACODEC LORN",</div><div class='add'>+				"Lineout", "AU2 OUTL",</div><div class='add'>+				"Lineout", "AU2 OUTR";</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL1&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;294912000&gt;,</div><div class='add'>+				       &lt;270950400&gt;,</div><div class='add'>+				       &lt;393216000&gt;;</div><div class='add'>+</div><div class='add'>+		dai-link-0 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_I2S_FIFO&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-1 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_I2S_ENCODER&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;aiu AIU_HDMI CTRL_I2S&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			codec-1 {</div><div class='add'>+				sound-dai = &lt;&amp;aiu AIU_ACODEC CTRL_I2S&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-2 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_HDMI CTRL_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-3 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_ACODEC CTRL_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;acodec&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;acodec {</div><div class='add'>+	AVDD-supply = &lt;&amp;vddio_ao18&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;aiu {</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cec_AO {</div><div class='hunk'>@@ -272,8 +345,9 @@</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;usb0 {</div><div class='add'>+&amp;usb {</div><div class='ctx'> 	status = "okay";</div><div class='add'>+	dr_mode = "host";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;usb2_phy0 {</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts<br/>index 62dd87821ce5..236cedec9f19 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts</a></div><div class='hunk'>@@ -42,21 +42,21 @@</div><div class='ctx'> 			 &lt;3300000 1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vddio_boot: regulator-vddio_boot {</div><div class='add'>+	vddio_boot: regulator-vddio-boot {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VDDIO_BOOT";</div><div class='ctx'> 		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vddao_3v3: regulator-vddao_3v3 {</div><div class='add'>+	vddao_3v3: regulator-vddao-3v3 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VDDAO_3V3";</div><div class='ctx'> 		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='ctx'> 		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vcc_3v3: regulator-vcc_3v3 {</div><div class='add'>+	vcc_3v3: regulator-vcc-3v3 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VCC_3V3";</div><div class='ctx'> 		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='hunk'>@@ -145,8 +145,6 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pwm_e_pins&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='del'>-	clocks = &lt;&amp;clkc CLKID_FCLK_DIV4&gt;;</div><div class='del'>-	clock-names = "clkin0";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* Wireless SDIO Module */</div><div class='hunk'>@@ -218,6 +216,7 @@</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;usb0 {</div><div class='add'>+&amp;usb {</div><div class='ctx'> 	status = "okay";</div><div class='add'>+	dr_mode = "host";</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts<br/>index 2602940c2077..8b41e340f919 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts</a></div><div class='hunk'>@@ -7,11 +7,19 @@</div><div class='ctx'> /dts-v1/;</div><div class='ctx'> </div><div class='ctx'> #include "meson-gxl-s905x-p212.dtsi"</div><div class='add'>+#include &lt;dt-bindings/sound/meson-aiu.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	compatible = "amlogic,p212", "amlogic,s905x", "amlogic,meson-gxl";</div><div class='ctx'> 	model = "Amlogic Meson GXL (S905X) P212 Development Board";</div><div class='ctx'> </div><div class='add'>+	dio2133: analog-amplifier {</div><div class='add'>+		compatible = "simple-audio-amplifier";</div><div class='add'>+		sound-name-prefix = "AU2";</div><div class='add'>+		VCC-supply = &lt;&amp;hdmi_5v&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;gpio GPIOH_5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	cvbs-connector {</div><div class='ctx'> 		compatible = "composite-video-connector";</div><div class='ctx'> </div><div class='hunk'>@@ -32,6 +40,70 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "amlogic,gx-sound-card";</div><div class='add'>+		model = "S905X-P212";</div><div class='add'>+		audio-aux-devs = &lt;&amp;dio2133&gt;;</div><div class='add'>+		audio-widgets = "Line", "Lineout";</div><div class='add'>+		audio-routing = "AU2 INL", "ACODEC LOLN",</div><div class='add'>+				"AU2 INR", "ACODEC LORN",</div><div class='add'>+				"Lineout", "AU2 OUTL",</div><div class='add'>+				"Lineout", "AU2 OUTR";</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL1&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;294912000&gt;,</div><div class='add'>+				       &lt;270950400&gt;,</div><div class='add'>+				       &lt;393216000&gt;;</div><div class='add'>+		dai-link-0 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_I2S_FIFO&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-1 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_I2S_ENCODER&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;aiu AIU_HDMI CTRL_I2S&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			codec-1 {</div><div class='add'>+				sound-dai = &lt;&amp;aiu AIU_ACODEC CTRL_I2S&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-2 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_HDMI CTRL_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-3 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_ACODEC CTRL_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;acodec&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;acodec {</div><div class='add'>+	AVDD-supply = &lt;&amp;vddio_ao18&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;aiu {</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cec_AO {</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi<br/>index 6ac678f88bd8..05a0d4de3ad7 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi</a></div><div class='hunk'>@@ -39,28 +39,28 @@</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vddio_boot: regulator-vddio_boot {</div><div class='add'>+	vddio_boot: regulator-vddio-boot {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VDDIO_BOOT";</div><div class='ctx'> 		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vddao_3v3: regulator-vddao_3v3 {</div><div class='add'>+	vddao_3v3: regulator-vddao-3v3 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VDDAO_3V3";</div><div class='ctx'> 		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='ctx'> 		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vddio_ao18: regulator-vddio_ao18 {</div><div class='add'>+	vddio_ao18: regulator-vddio-ao18 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VDDIO_AO18";</div><div class='ctx'> 		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vcc_3v3: regulator-vcc_3v3 {</div><div class='add'>+	vcc_3v3: regulator-vcc-3v3 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VCC_3V3";</div><div class='ctx'> 		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='hunk'>@@ -97,6 +97,12 @@</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;pwm_ef {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm_e_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;saradc {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> 	vref-supply = &lt;&amp;vddio_ao18&gt;;</div><div class='hunk'>@@ -125,6 +131,10 @@</div><div class='ctx'> </div><div class='ctx'> 	vmmc-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='ctx'> 	vqmmc-supply = &lt;&amp;vddio_boot&gt;;</div><div class='add'>+</div><div class='add'>+	sdio: wifi@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* SD card */</div><div class='hunk'>@@ -165,14 +175,6 @@</div><div class='ctx'> 	vqmmc-supply = &lt;&amp;vddio_boot&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;pwm_ef {</div><div class='del'>-	status = "okay";</div><div class='del'>-	pinctrl-0 = &lt;&amp;pwm_e_pins&gt;;</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-	clocks = &lt;&amp;clkc CLKID_FCLK_DIV4&gt;;</div><div class='del'>-	clock-names = "clkin0";</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> /* This is connected to the Bluetooth module: */</div><div class='ctx'> &amp;uart_A {</div><div class='ctx'> 	status = "okay";</div><div class='hunk'>@@ -195,8 +197,9 @@</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;usb0 {</div><div class='add'>+&amp;usb {</div><div class='ctx'> 	status = "okay";</div><div class='add'>+	dr_mode = "host";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;usb2_phy0 {</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-vero4k.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-vero4k.dts<br/>new file mode 100644<br/>index 000000000000..a9c5881c9783<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-vero4k.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxl-s905x-vero4k.dts</a></div><div class='hunk'>@@ -0,0 +1,204 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2024 Christian Hewitt &lt;christianshewitt@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "meson-gxl-s905x-p212.dtsi"</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/meson-aiu.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "osmc,vero4k", "amlogic,s905x", "amlogic,meson-gxl";</div><div class='add'>+	model = "OSMC Vero 4K";</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		/* 32 MiB reserved for ARM Trusted Firmware (BL32) */</div><div class='add'>+		secmon_reserved_bl32: secmon@5300000 {</div><div class='add'>+			reg = &lt;0x0 0x05300000 0x0 0x2000000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys-polled {</div><div class='add'>+		compatible = "gpio-keys-polled";</div><div class='add'>+		poll-interval = &lt;20&gt;;</div><div class='add'>+</div><div class='add'>+		button {</div><div class='add'>+			label = "power";</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-standby {</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			function = LED_FUNCTION_POWER;</div><div class='add'>+			gpios = &lt;&amp;gpio GPIODV_24 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+			panic-indicator;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dio2133: analog-amplifier {</div><div class='add'>+		compatible = "simple-audio-amplifier";</div><div class='add'>+		sound-name-prefix = "AU2";</div><div class='add'>+		VCC-supply = &lt;&amp;hdmi_5v&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;gpio GPIOH_5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spdif_dit: audio-codec-0 {</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		compatible = "linux,spdif-dit";</div><div class='add'>+		sound-name-prefix = "DIT";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cvbs-connector {</div><div class='add'>+		compatible = "composite-video-connector";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			cvbs_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;cvbs_vdac_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdmi-connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		type = "a";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			hdmi_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_tx_tmds_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "amlogic,gx-sound-card";</div><div class='add'>+		model = "VERO4K";</div><div class='add'>+		audio-aux-devs = &lt;&amp;dio2133&gt;;</div><div class='add'>+		audio-widgets = "Line", "Lineout";</div><div class='add'>+		audio-routing = "AU2 INL", "ACODEC LOLP",</div><div class='add'>+				"AU2 INR", "ACODEC LORP",</div><div class='add'>+				"AU2 INL", "ACODEC LOLN",</div><div class='add'>+				"AU2 INR", "ACODEC LORN",</div><div class='add'>+				"Lineout", "AU2 OUTL",</div><div class='add'>+				"Lineout", "AU2 OUTR";</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL1&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;294912000&gt;,</div><div class='add'>+				       &lt;270950400&gt;,</div><div class='add'>+				       &lt;393216000&gt;;</div><div class='add'>+</div><div class='add'>+		dai-link-0 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_I2S_FIFO&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-1 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_SPDIF_FIFO&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-2 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_I2S_ENCODER&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;aiu AIU_HDMI CTRL_I2S&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			codec-1 {</div><div class='add'>+				sound-dai = &lt;&amp;aiu AIU_ACODEC CTRL_I2S&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-3 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_SPDIF_ENCODER&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;spdif_dit&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-4 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_HDMI CTRL_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-5 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_ACODEC CTRL_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;acodec&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;acodec {</div><div class='add'>+	AVDD-supply = &lt;&amp;vddio_ao18&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;aiu {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;spdif_out_h_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cec_AO {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;ao_cec_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	hdmi-phandle = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cvbs_vdac_port {</div><div class='add'>+	cvbs_vdac_out: endpoint {</div><div class='add'>+		remote-endpoint = &lt;&amp;cvbs_connector_in&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethmac {</div><div class='add'>+	phy-mode = "rmii";</div><div class='add'>+	phy-handle = &lt;&amp;internal_phy&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;hdmi_hpd_pins&gt;, &lt;&amp;hdmi_i2c_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	hdmi-supply = &lt;&amp;hdmi_5v&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx_tmds_port {</div><div class='add'>+	hdmi_tx_tmds_out: endpoint {</div><div class='add'>+		remote-endpoint = &lt;&amp;hdmi_connector_in&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;internal_phy {</div><div class='add'>+	pinctrl-0 = &lt;&amp;eth_link_led_pins&gt;, &lt;&amp;eth_act_led_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* This UART is brought out to the DB9 connector */</div><div class='add'>+&amp;uart_AO {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi<br/>index 259d86399390..ba535010a3c9 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxl.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxl.dtsi</a></div><div class='hunk'>@@ -14,29 +14,57 @@</div><div class='ctx'> 	compatible = "amlogic,meson-gxl";</div><div class='ctx'> </div><div class='ctx'> 	soc {</div><div class='del'>-		usb0: usb@c9000000 {</div><div class='del'>-			status = "disabled";</div><div class='del'>-			compatible = "amlogic,meson-gxl-dwc3";</div><div class='add'>+		usb: usb@d0078080 {</div><div class='add'>+			compatible = "amlogic,meson-gxl-usb-ctrl";</div><div class='add'>+			reg = &lt;0x0 0xd0078080 0x0 0x20&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			#address-cells = &lt;2&gt;;</div><div class='ctx'> 			#size-cells = &lt;2&gt;;</div><div class='ctx'> 			ranges;</div><div class='ctx'> </div><div class='del'>-			clocks = &lt;&amp;clkc CLKID_USB&gt;;</div><div class='del'>-			clock-names = "usb_general";</div><div class='add'>+			clocks = &lt;&amp;clkc CLKID_USB&gt;, &lt;&amp;clkc CLKID_USB1_DDR_BRIDGE&gt;;</div><div class='add'>+			clock-names = "usb_ctrl", "ddr";</div><div class='ctx'> 			resets = &lt;&amp;reset RESET_USB_OTG&gt;;</div><div class='del'>-			reset-names = "usb_otg";</div><div class='ctx'> </div><div class='del'>-			dwc3: dwc3@c9000000 {</div><div class='add'>+			dr_mode = "otg";</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;usb2_phy0&gt;, &lt;&amp;usb2_phy1&gt;;</div><div class='add'>+			phy-names = "usb2-phy0", "usb2-phy1";</div><div class='add'>+</div><div class='add'>+			dwc2: usb@c9100000 {</div><div class='add'>+				compatible = "amlogic,meson-g12a-usb", "snps,dwc2";</div><div class='add'>+				reg = &lt;0x0 0xc9100000 0x0 0x40000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clkc CLKID_USB1&gt;;</div><div class='add'>+				clock-names = "otg";</div><div class='add'>+				phys = &lt;&amp;usb2_phy1&gt;;</div><div class='add'>+				dr_mode = "peripheral";</div><div class='add'>+				g-rx-fifo-size = &lt;192&gt;;</div><div class='add'>+				g-np-tx-fifo-size = &lt;128&gt;;</div><div class='add'>+				g-tx-fifo-size = &lt;128 128 16 16 16&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			dwc3: usb@c9000000 {</div><div class='ctx'> 				compatible = "snps,dwc3";</div><div class='ctx'> 				reg = &lt;0x0 0xc9000000 0x0 0x100000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				dr_mode = "host";</div><div class='ctx'> 				maximum-speed = "high-speed";</div><div class='ctx'> 				snps,dis_u2_susphy_quirk;</div><div class='del'>-				phys = &lt;&amp;usb3_phy&gt;, &lt;&amp;usb2_phy0&gt;, &lt;&amp;usb2_phy1&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		acodec: audio-controller@c8832000 {</div><div class='add'>+			compatible = "amlogic,t9015";</div><div class='add'>+			reg = &lt;0x0 0xc8832000 0x0 0x14&gt;;</div><div class='add'>+			#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+			sound-name-prefix = "ACODEC";</div><div class='add'>+			clocks = &lt;&amp;clkc CLKID_ACODEC&gt;;</div><div class='add'>+			clock-names = "pclk";</div><div class='add'>+			resets = &lt;&amp;reset RESET_ACODEC&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		crypto: crypto@c883e000 {</div><div class='ctx'> 			compatible = "amlogic,gxl-crypto";</div><div class='ctx'> 			reg = &lt;0x0 0xc883e000 0x0 0x36&gt;;</div><div class='hunk'>@@ -49,6 +77,29 @@</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;aiu {</div><div class='add'>+	compatible = "amlogic,aiu-gxl", "amlogic,aiu";</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_AIU_GLUE&gt;,</div><div class='add'>+		 &lt;&amp;clkc CLKID_I2S_OUT&gt;,</div><div class='add'>+		 &lt;&amp;clkc CLKID_AOCLK_GATE&gt;,</div><div class='add'>+		 &lt;&amp;clkc CLKID_CTS_AMCLK&gt;,</div><div class='add'>+		 &lt;&amp;clkc CLKID_MIXER_IFACE&gt;,</div><div class='add'>+		 &lt;&amp;clkc CLKID_IEC958&gt;,</div><div class='add'>+		 &lt;&amp;clkc CLKID_IEC958_GATE&gt;,</div><div class='add'>+		 &lt;&amp;clkc CLKID_CTS_MCLK_I958&gt;,</div><div class='add'>+		 &lt;&amp;clkc CLKID_CTS_I958&gt;;</div><div class='add'>+	clock-names = "pclk",</div><div class='add'>+		      "i2s_pclk",</div><div class='add'>+		      "i2s_aoclk",</div><div class='add'>+		      "i2s_mclk",</div><div class='add'>+		      "i2s_mixer",</div><div class='add'>+		      "spdif_pclk",</div><div class='add'>+		      "spdif_aoclk",</div><div class='add'>+		      "spdif_mclk",</div><div class='add'>+		      "spdif_mclk_sel";</div><div class='add'>+	resets = &lt;&amp;reset RESET_AIU&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;apb {</div><div class='ctx'> 	usb2_phy0: phy@78000 {</div><div class='ctx'> 		compatible = "amlogic,meson-gxl-usb2-phy";</div><div class='hunk'>@@ -71,18 +122,6 @@</div><div class='ctx'> 		reset-names = "phy";</div><div class='ctx'> 		status = "okay";</div><div class='ctx'> 	};</div><div class='del'>-</div><div class='del'>-	usb3_phy: phy@78080 {</div><div class='del'>-		compatible = "amlogic,meson-gxl-usb3-phy";</div><div class='del'>-		#phy-cells = &lt;0&gt;;</div><div class='del'>-		reg = &lt;0x0 0x78080 0x0 0x20&gt;;</div><div class='del'>-		interrupts = &lt;GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-		clocks = &lt;&amp;clkc CLKID_USB&gt;, &lt;&amp;clkc_AO CLKID_AO_CEC_32K&gt;;</div><div class='del'>-		clock-names = "phy", "peripheral";</div><div class='del'>-		resets = &lt;&amp;reset RESET_USB_OTG&gt;, &lt;&amp;reset RESET_USB_OTG&gt;;</div><div class='del'>-		reset-names = "phy", "peripheral";</div><div class='del'>-		status = "okay";</div><div class='del'>-	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;efuse {</div><div class='hunk'>@@ -92,8 +131,9 @@</div><div class='ctx'> &amp;ethmac {</div><div class='ctx'> 	clocks = &lt;&amp;clkc CLKID_ETH&gt;,</div><div class='ctx'> 		 &lt;&amp;clkc CLKID_FCLK_DIV2&gt;,</div><div class='del'>-		 &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='del'>-	clock-names = "stmmaceth", "clkin0", "clkin1";</div><div class='add'>+		 &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+		 &lt;&amp;clkc CLKID_FCLK_DIV2&gt;;</div><div class='add'>+	clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";</div><div class='ctx'> </div><div class='ctx'> 	mdio0: mdio {</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='hunk'>@@ -123,7 +163,7 @@</div><div class='ctx'> 			mux {</div><div class='ctx'> 				groups = "uart_tx_ao_a", "uart_rx_ao_a";</div><div class='ctx'> 				function = "uart_ao";</div><div class='del'>-				bias-disable;</div><div class='add'>+				bias-pull-up;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -140,7 +180,7 @@</div><div class='ctx'> 			mux {</div><div class='ctx'> 				groups = "uart_tx_ao_b", "uart_rx_ao_b";</div><div class='ctx'> 				function = "uart_ao_b";</div><div class='del'>-				bias-disable;</div><div class='add'>+				bias-pull-up;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -148,7 +188,7 @@</div><div class='ctx'> 			mux {</div><div class='ctx'> 				groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";</div><div class='ctx'> 				function = "uart_ao_b";</div><div class='del'>-				bias-disable;</div><div class='add'>+				bias-pull-up;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -174,7 +214,7 @@</div><div class='ctx'> 				groups = "i2c_sck_ao",</div><div class='ctx'> 				       "i2c_sda_ao";</div><div class='ctx'> 				function = "i2c_ao";</div><div class='del'>-				bias-disable;</div><div class='add'>+				bias-pull-up;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -272,8 +312,8 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;gpio_intc {</div><div class='del'>-	compatible = "amlogic,meson-gpio-intc",</div><div class='del'>-		     "amlogic,meson-gxl-gpio-intc";</div><div class='add'>+	compatible = "amlogic,meson-gxl-gpio-intc",</div><div class='add'>+		     "amlogic,meson-gpio-intc";</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -283,10 +323,16 @@</div><div class='ctx'> 		 &lt;&amp;reset RESET_HDMI_SYSTEM_RESET&gt;,</div><div class='ctx'> 		 &lt;&amp;reset RESET_HDMI_TX&gt;;</div><div class='ctx'> 	reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";</div><div class='del'>-	clocks = &lt;&amp;clkc CLKID_HDMI_PCLK&gt;,</div><div class='del'>-		 &lt;&amp;clkc CLKID_CLK81&gt;,</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_HDMI&gt;,</div><div class='add'>+		 &lt;&amp;clkc CLKID_HDMI_PCLK&gt;,</div><div class='ctx'> 		 &lt;&amp;clkc CLKID_GCLK_VENCI_INT0&gt;;</div><div class='ctx'> 	clock-names = "isfr", "iahb", "venci";</div><div class='add'>+	power-domains = &lt;&amp;pwrc PWRC_GXBB_VPU_ID&gt;;</div><div class='add'>+</div><div class='add'>+	assigned-clocks = &lt;&amp;clkc CLKID_HDMI_SEL&gt;,</div><div class='add'>+			  &lt;&amp;clkc CLKID_HDMI&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;xtal&gt;, &lt;0&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;0&gt;, &lt;24000000&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;sysctrl {</div><div class='hunk'>@@ -298,6 +344,11 @@</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;hwrng {</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_RNG0&gt;;</div><div class='add'>+	clock-names = "core";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;i2c_A {</div><div class='ctx'> 	clocks = &lt;&amp;clkc CLKID_I2C&gt;;</div><div class='ctx'> };</div><div class='hunk'>@@ -384,6 +435,20 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		spi_idle_high_pins: spi-idle-high-pins {</div><div class='add'>+			mux {</div><div class='add'>+				groups = "spi_sclk";</div><div class='add'>+				bias-pull-up;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi_idle_low_pins: spi-idle-low-pins {</div><div class='add'>+			mux {</div><div class='add'>+				groups = "spi_sclk";</div><div class='add'>+				bias-pull-down;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		spi_ss0_pins: spi-ss0 {</div><div class='ctx'> 			mux {</div><div class='ctx'> 				groups = "spi_ss0";</div><div class='hunk'>@@ -457,7 +522,7 @@</div><div class='ctx'> 				groups = "uart_tx_a",</div><div class='ctx'> 				       "uart_rx_a";</div><div class='ctx'> 				function = "uart_a";</div><div class='del'>-				bias-disable;</div><div class='add'>+				bias-pull-up;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -475,7 +540,7 @@</div><div class='ctx'> 				groups = "uart_tx_b",</div><div class='ctx'> 				       "uart_rx_b";</div><div class='ctx'> 				function = "uart_b";</div><div class='del'>-				bias-disable;</div><div class='add'>+				bias-pull-up;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -493,7 +558,7 @@</div><div class='ctx'> 				groups = "uart_tx_c",</div><div class='ctx'> 				       "uart_rx_c";</div><div class='ctx'> 				function = "uart_c";</div><div class='del'>-				bias-disable;</div><div class='add'>+				bias-pull-up;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -511,7 +576,7 @@</div><div class='ctx'> 				groups = "i2c_sck_a",</div><div class='ctx'> 				     "i2c_sda_a";</div><div class='ctx'> 				function = "i2c_a";</div><div class='del'>-				bias-disable;</div><div class='add'>+				bias-pull-up;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -520,7 +585,7 @@</div><div class='ctx'> 				groups = "i2c_sck_b",</div><div class='ctx'> 				      "i2c_sda_b";</div><div class='ctx'> 				function = "i2c_b";</div><div class='del'>-				bias-disable;</div><div class='add'>+				bias-pull-up;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -529,7 +594,7 @@</div><div class='ctx'> 				groups = "i2c_sck_c",</div><div class='ctx'> 				      "i2c_sda_c";</div><div class='ctx'> 				function = "i2c_c";</div><div class='del'>-				bias-disable;</div><div class='add'>+				bias-pull-up;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -538,7 +603,7 @@</div><div class='ctx'> 				groups = "i2c_sck_c_dv19",</div><div class='ctx'> 				      "i2c_sda_c_dv18";</div><div class='ctx'> 				function = "i2c_c";</div><div class='del'>-				bias-disable;</div><div class='add'>+				bias-pull-up;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -714,16 +779,23 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	eth-phy-mux {</div><div class='del'>-		compatible = "mdio-mux-mmioreg", "mdio-mux";</div><div class='add'>+	eth_phy_mux: mdio@558 {</div><div class='add'>+		reg = &lt;0x0 0x558 0x0 0xc&gt;;</div><div class='add'>+		compatible = "amlogic,gxl-mdio-mux";</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;0&gt;;</div><div class='del'>-		reg = &lt;0x0 0x55c 0x0 0x4&gt;;</div><div class='del'>-		mux-mask = &lt;0xffffffff&gt;;</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_FCLK_DIV4&gt;;</div><div class='add'>+		clock-names = "ref";</div><div class='ctx'> 		mdio-parent-bus = &lt;&amp;mdio0&gt;;</div><div class='ctx'> </div><div class='del'>-		internal_mdio: mdio@e40908ff {</div><div class='del'>-			reg = &lt;0xe40908ff&gt;;</div><div class='add'>+		external_mdio: mdio@0 {</div><div class='add'>+			reg = &lt;0x0&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		internal_mdio: mdio@1 {</div><div class='add'>+			reg = &lt;0x1&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -734,16 +806,35 @@</div><div class='ctx'> 				max-speed = &lt;100&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='del'>-</div><div class='del'>-		external_mdio: mdio@2009087f {</div><div class='del'>-			reg = &lt;0x2009087f&gt;;</div><div class='del'>-			#address-cells = &lt;1&gt;;</div><div class='del'>-			#size-cells = &lt;0&gt;;</div><div class='del'>-		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;pwrc_vpu {</div><div class='add'>+&amp;pwm_ab {</div><div class='add'>+	clocks = &lt;&amp;xtal&gt;,</div><div class='add'>+		 &lt;0&gt;, /* unknown/untested, the datasheet calls it "vid_pll" */</div><div class='add'>+		 &lt;&amp;clkc CLKID_FCLK_DIV4&gt;,</div><div class='add'>+		 &lt;&amp;clkc CLKID_FCLK_DIV3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm_AO_ab {</div><div class='add'>+	clocks = &lt;&amp;xtal&gt;, &lt;&amp;clkc CLKID_CLK81&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm_cd {</div><div class='add'>+	clocks = &lt;&amp;xtal&gt;,</div><div class='add'>+		 &lt;0&gt;, /* unknown/untested, the datasheet calls it "vid_pll" */</div><div class='add'>+		 &lt;&amp;clkc CLKID_FCLK_DIV4&gt;,</div><div class='add'>+		 &lt;&amp;clkc CLKID_FCLK_DIV3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm_ef {</div><div class='add'>+	clocks = &lt;&amp;xtal&gt;,</div><div class='add'>+		 &lt;0&gt;, /* unknown/untested, the datasheet calls it "vid_pll" */</div><div class='add'>+		 &lt;&amp;clkc CLKID_FCLK_DIV4&gt;,</div><div class='add'>+		 &lt;&amp;clkc CLKID_FCLK_DIV3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwrc {</div><div class='ctx'> 	resets = &lt;&amp;reset RESET_VIU&gt;,</div><div class='ctx'> 		 &lt;&amp;reset RESET_VENC&gt;,</div><div class='ctx'> 		 &lt;&amp;reset RESET_VCBUS&gt;,</div><div class='hunk'>@@ -756,6 +847,9 @@</div><div class='ctx'> 		 &lt;&amp;reset RESET_VDI6&gt;,</div><div class='ctx'> 		 &lt;&amp;reset RESET_VENCL&gt;,</div><div class='ctx'> 		 &lt;&amp;reset RESET_VID_LOCK&gt;;</div><div class='add'>+	reset-names = "viu", "venc", "vcbus", "bt656",</div><div class='add'>+		      "dvin", "rdma", "venci", "vencp",</div><div class='add'>+		      "vdac", "vdi6", "vencl", "vid_lock";</div><div class='ctx'> 	clocks = &lt;&amp;clkc CLKID_VPU&gt;,</div><div class='ctx'> 	         &lt;&amp;clkc CLKID_VAPB&gt;;</div><div class='ctx'> 	clock-names = "vpu", "vapb";</div><div class='hunk'>@@ -862,7 +956,7 @@</div><div class='ctx'> </div><div class='ctx'> &amp;vpu {</div><div class='ctx'> 	compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";</div><div class='del'>-	power-domains = &lt;&amp;pwrc_vpu&gt;;</div><div class='add'>+	power-domains = &lt;&amp;pwrc PWRC_GXBB_VPU_ID&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;vdec {</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxlx-s905l-p271.dts b/arch/arm64/boot/dts/amlogic/meson-gxlx-s905l-p271.dts<br/>new file mode 100644<br/>index 000000000000..1221f4545130<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxlx-s905l-p271.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxlx-s905l-p271.dts</a></div><div class='hunk'>@@ -0,0 +1,51 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2024 Christian Hewitt &lt;christianshewitt@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "meson-gxl-s905x.dtsi"</div><div class='add'>+#include "meson-gx-p23x-q20x.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "amlogic,p271", "amlogic,s905l", "amlogic,meson-gxlx";</div><div class='add'>+	model = "Amlogic Meson GXLX (S905L) P271 Development Board";</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x0 0x0 0x40000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		model = "P271";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;apb {</div><div class='add'>+	mali: gpu@c0000 {</div><div class='add'>+		/* Mali 450-MP2 */</div><div class='add'>+		interrupts = &lt;GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			&lt;GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			&lt;GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			&lt;GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			&lt;GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			&lt;GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			&lt;GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			&lt;GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-names = "gp", "gpmmu", "pp", "pmu",</div><div class='add'>+			"pp0", "ppmmu0", "pp1", "ppmmu1";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;saradc {</div><div class='add'>+	compatible = "amlogic,meson-gxlx-saradc", "amlogic,meson-saradc";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;vdec {</div><div class='add'>+	compatible = "amlogic,gxlx-vdec", "amlogic,gx-vdec";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-gt1-ultimate.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-gt1-ultimate.dts<br/>new file mode 100644<br/>index 000000000000..2c267884cc16<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxm-gt1-ultimate.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxm-gt1-ultimate.dts</a></div><div class='hunk'>@@ -0,0 +1,91 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) Christian Hewitt &lt;christianshewitt@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "meson-gxm.dtsi"</div><div class='add'>+#include "meson-gx-p23x-q20x.dtsi"</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "azw,gt1-ultimate", "amlogic,s912", "amlogic,meson-gxm";</div><div class='add'>+	model = "Beelink GT1 Ultimate";</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-white {</div><div class='add'>+			color = &lt;LED_COLOR_ID_WHITE&gt;;</div><div class='add'>+			function = LED_FUNCTION_POWER;</div><div class='add'>+			gpios = &lt;&amp;gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "on";</div><div class='add'>+			panic-indicator;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	adc-keys {</div><div class='add'>+		compatible = "adc-keys";</div><div class='add'>+		io-channels = &lt;&amp;saradc 0&gt;;</div><div class='add'>+		io-channel-names = "buttons";</div><div class='add'>+		keyup-threshold-microvolt = &lt;1710000&gt;;</div><div class='add'>+</div><div class='add'>+		button-function {</div><div class='add'>+			label = "update";</div><div class='add'>+			linux,code = &lt;KEY_VENDOR&gt;;</div><div class='add'>+			press-threshold-microvolt = &lt;10000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethmac {</div><div class='add'>+	pinctrl-0 = &lt;&amp;eth_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	phy-handle = &lt;&amp;external_phy&gt;;</div><div class='add'>+	amlogic,tx-delay-ns = &lt;2&gt;;</div><div class='add'>+	phy-mode = "rgmii";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;external_mdio {</div><div class='add'>+	external_phy: ethernet-phy@0 {</div><div class='add'>+		/* Realtek RTL8211F (0x001cc916) */</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		max-speed = &lt;1000&gt;;</div><div class='add'>+</div><div class='add'>+		reset-assert-us = &lt;10000&gt;;</div><div class='add'>+		reset-deassert-us = &lt;80000&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio GPIOZ_14 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio_intc&gt;;</div><div class='add'>+		/* MAC_INTR on GPIOZ_15 */</div><div class='add'>+		interrupts = &lt;25 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ir {</div><div class='add'>+	linux,rc-map-name = "rc-beelink-gs1";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sd_emmc_a {</div><div class='add'>+	brcmf: wifi@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		compatible = "brcm,bcm4329-fmac";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart_A {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart_a_pins&gt;, &lt;&amp;uart_a_cts_rts_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "brcm,bcm43438-bt";</div><div class='add'>+		shutdown-gpios = &lt;&amp;gpio GPIOX_17 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		max-speed = &lt;2000000&gt;;</div><div class='add'>+		clocks = &lt;&amp;wifi32k&gt;;</div><div class='add'>+		clock-names = "lpo";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts<br/>index 27eeab71ec77..2a09b3d550e2 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts</a></div><div class='hunk'>@@ -7,9 +7,9 @@</div><div class='ctx'> </div><div class='ctx'> /dts-v1/;</div><div class='ctx'> </div><div class='del'>-#include &lt;dt-bindings/input/input.h&gt;</div><div class='del'>-</div><div class='ctx'> #include "meson-gxm.dtsi"</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/meson-aiu.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	compatible = "khadas,vim2", "amlogic,s912", "amlogic,meson-gxm";</div><div class='hunk'>@@ -52,10 +52,11 @@</div><div class='ctx'> 		gpios = &lt;&amp;gpio GPIODV_14 GPIO_ACTIVE_HIGH</div><div class='ctx'> 			 &amp;gpio GPIODV_15 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 		/* Dummy RPM values since fan is optional */</div><div class='del'>-		gpio-fan,speed-map = &lt;0 0</div><div class='del'>-				      1 1</div><div class='del'>-				      2 2</div><div class='del'>-				      3 3&gt;;</div><div class='add'>+		gpio-fan,speed-map =</div><div class='add'>+				&lt;0 0&gt;,</div><div class='add'>+				&lt;1 1&gt;,</div><div class='add'>+				&lt;2 2&gt;,</div><div class='add'>+				&lt;3 3&gt;;</div><div class='ctx'> 		#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -81,10 +82,10 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pwmleds {</div><div class='add'>+	led-controller {</div><div class='ctx'> 		compatible = "pwm-leds";</div><div class='ctx'> </div><div class='del'>-		power {</div><div class='add'>+		led-1 {</div><div class='ctx'> 			label = "vim:red:power";</div><div class='ctx'> 			pwms = &lt;&amp;pwm_AO_ab 1 7812500 0&gt;;</div><div class='ctx'> 			max-brightness = &lt;255&gt;;</div><div class='hunk'>@@ -111,28 +112,28 @@</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vcc_3v3: regulator-vcc_3v3 {</div><div class='add'>+	vcc_3v3: regulator-vcc-3v3 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VCC_3V3";</div><div class='ctx'> 		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='ctx'> 		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vddio_ao18: regulator-vddio_ao18 {</div><div class='add'>+	vddio_ao18: regulator-vddio-ao18 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VDDIO_AO18";</div><div class='ctx'> 		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vddio_boot: regulator-vddio_boot {</div><div class='add'>+	vddio_boot: regulator-vddio-boot {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VDDIO_BOOT";</div><div class='ctx'> 		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vddao_3v3: regulator-vddao_3v3 {</div><div class='add'>+	vddao_3v3: regulator-vddao-3v3 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VDDAO_3V3";</div><div class='ctx'> 		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='hunk'>@@ -145,6 +146,48 @@</div><div class='ctx'> 		clock-frequency = &lt;32768&gt;;</div><div class='ctx'> 		pwms = &lt;&amp;pwm_ef 0 30518 0&gt;; /* PWM_E at 32.768KHz */</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "amlogic,gx-sound-card";</div><div class='add'>+		model = "KHADAS-VIM2";</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL1&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;294912000&gt;,</div><div class='add'>+				       &lt;270950400&gt;,</div><div class='add'>+				       &lt;393216000&gt;;</div><div class='add'>+</div><div class='add'>+		dai-link-0 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_I2S_FIFO&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-1 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_I2S_ENCODER&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;aiu AIU_HDMI CTRL_I2S&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-2 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_HDMI CTRL_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;aiu {</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cec_AO {</div><div class='hunk'>@@ -154,7 +197,6 @@</div><div class='ctx'> 	hdmi-phandle = &lt;&amp;hdmi_tx&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-</div><div class='ctx'> &amp;cpu_cooling_maps {</div><div class='ctx'> 	map0 {</div><div class='ctx'> 		cooling-device = &lt;&amp;gpio_fan THERMAL_NO_LIMIT 1&gt;;</div><div class='hunk'>@@ -194,7 +236,7 @@</div><div class='ctx'> 		reg = &lt;0&gt;;</div><div class='ctx'> </div><div class='ctx'> 		reset-assert-us = &lt;10000&gt;;</div><div class='del'>-		reset-deassert-us = &lt;30000&gt;;</div><div class='add'>+		reset-deassert-us = &lt;80000&gt;;</div><div class='ctx'> 		reset-gpios = &lt;&amp;gpio GPIOZ_14 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> </div><div class='ctx'> 		interrupt-parent = &lt;&amp;gpio_intc&gt;;</div><div class='hunk'>@@ -228,12 +270,10 @@</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> </div><div class='ctx'> 	rtc: rtc@51 {</div><div class='del'>-		/* has to be enabled manually when a battery is connected: */</div><div class='del'>-		status = "disabled";</div><div class='add'>+		status = "okay";</div><div class='ctx'> 		compatible = "haoyu,hym8563";</div><div class='ctx'> 		reg = &lt;0x51&gt;;</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='del'>-		clock-frequency = &lt;32768&gt;;</div><div class='ctx'> 		clock-output-names = "xin32k";</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='hunk'>@@ -249,16 +289,12 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pwm_ao_a_3_pins&gt;, &lt;&amp;pwm_ao_b_pins&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='del'>-	clocks = &lt;&amp;clkc CLKID_FCLK_DIV4&gt;;</div><div class='del'>-	clock-names = "clkin0";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;pwm_ef {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pwm_e_pins&gt;, &lt;&amp;pwm_f_clk_pins&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='del'>-	clocks = &lt;&amp;clkc CLKID_FCLK_DIV4&gt;;</div><div class='del'>-	clock-names = "clkin0";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;sd_emmc_a {</div><div class='hunk'>@@ -270,7 +306,8 @@</div><div class='ctx'> 	#size-cells = &lt;0&gt;;</div><div class='ctx'> </div><div class='ctx'> 	bus-width = &lt;4&gt;;</div><div class='del'>-	max-frequency = &lt;60000000&gt;;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	max-frequency = &lt;100000000&gt;;</div><div class='ctx'> </div><div class='ctx'> 	non-removable;</div><div class='ctx'> 	disable-wp;</div><div class='hunk'>@@ -336,12 +373,12 @@</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;nor_pins&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> </div><div class='del'>-	w25q32: spi-flash@0 {</div><div class='add'>+	w25q32: flash@0 {</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;1&gt;;</div><div class='ctx'> 		compatible = "winbond,w25q16", "jedec,spi-nor";</div><div class='ctx'> 		reg = &lt;0&gt;;</div><div class='del'>-		spi-max-frequency = &lt;3000000&gt;;</div><div class='add'>+		spi-max-frequency = &lt;104000000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -380,6 +417,7 @@</div><div class='ctx'> 	vref-supply = &lt;&amp;vddio_ao18&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;usb0 {</div><div class='add'>+&amp;usb {</div><div class='ctx'> 	status = "okay";</div><div class='add'>+	dr_mode = "peripheral";</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-mecool-kiii-pro.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-mecool-kiii-pro.dts<br/>new file mode 100644<br/>index 000000000000..f5b3424c0f61<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxm-mecool-kiii-pro.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxm-mecool-kiii-pro.dts</a></div><div class='hunk'>@@ -0,0 +1,111 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Author: Christian Hewitt &lt;christianshewitt@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "meson-gxm.dtsi"</div><div class='add'>+#include "meson-gx-p23x-q20x.dtsi"</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "videostrong,gxm-kiii-pro", "amlogic,s912", "amlogic,meson-gxm";</div><div class='add'>+	model = "MeCool KIII Pro";</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x0 0x0 0xC0000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	adc-keys {</div><div class='add'>+		compatible = "adc-keys";</div><div class='add'>+		io-channels = &lt;&amp;saradc 0&gt;;</div><div class='add'>+		io-channel-names = "buttons";</div><div class='add'>+		keyup-threshold-microvolt = &lt;1710000&gt;;</div><div class='add'>+</div><div class='add'>+		button-function {</div><div class='add'>+			label = "Update";</div><div class='add'>+			linux,code = &lt;KEY_VENDOR&gt;;</div><div class='add'>+			press-threshold-microvolt = &lt;10000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys-polled {</div><div class='add'>+		compatible = "gpio-keys-polled";</div><div class='add'>+		poll-interval = &lt;100&gt;;</div><div class='add'>+</div><div class='add'>+		button {</div><div class='add'>+			label = "power";</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-blue {</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			function = LED_FUNCTION_POWER;</div><div class='add'>+			gpios = &lt;&amp;gpio GPIODV_24 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "on";</div><div class='add'>+			panic-indicator;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethmac {</div><div class='add'>+	pinctrl-0 = &lt;&amp;eth_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	phy-handle = &lt;&amp;external_phy&gt;;</div><div class='add'>+</div><div class='add'>+	amlogic,tx-delay-ns = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	phy-mode = "rgmii";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;external_mdio {</div><div class='add'>+	external_phy: ethernet-phy@0 {</div><div class='add'>+		/* Realtek RTL8211F (0x001cc916) */</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		max-speed = &lt;1000&gt;;</div><div class='add'>+</div><div class='add'>+		reset-assert-us = &lt;10000&gt;;</div><div class='add'>+		reset-deassert-us = &lt;80000&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio GPIOZ_14 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio_intc&gt;;</div><div class='add'>+		/* MAC_INTR on GPIOZ_15 */</div><div class='add'>+		interrupts = &lt;25 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ir {</div><div class='add'>+	linux,rc-map-name = "rc-mecool-kiii-pro";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sd_emmc_a {</div><div class='add'>+	brcmf: wifi@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		compatible = "brcm,bcm4329-fmac";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart_A {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart_a_pins&gt;, &lt;&amp;uart_a_cts_rts_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "brcm,bcm43438-bt";</div><div class='add'>+		shutdown-gpios = &lt;&amp;gpio GPIOX_17 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		max-speed = &lt;2000000&gt;;</div><div class='add'>+		clocks = &lt;&amp;wifi32k&gt;;</div><div class='add'>+		clock-names = "lpo";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-minix-neo-u9h.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-minix-neo-u9h.dts<br/>new file mode 100644<br/>index 000000000000..1703da3235ea<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxm-minix-neo-u9h.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxm-minix-neo-u9h.dts</a></div><div class='hunk'>@@ -0,0 +1,117 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) Christian Hewitt &lt;christianshewitt@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "meson-gxm.dtsi"</div><div class='add'>+#include "meson-gx-p23x-q20x.dtsi"</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "minix,neo-u9h", "amlogic,s912", "amlogic,meson-gxm";</div><div class='add'>+	model = "Minix Neo U9-H";</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-white {</div><div class='add'>+			color = &lt;LED_COLOR_ID_WHITE&gt;;</div><div class='add'>+			function = LED_FUNCTION_POWER;</div><div class='add'>+			gpios = &lt;&amp;gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "on";</div><div class='add'>+			panic-indicator;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	adc-keys {</div><div class='add'>+		compatible = "adc-keys";</div><div class='add'>+		io-channels = &lt;&amp;saradc 0&gt;;</div><div class='add'>+		io-channel-names = "buttons";</div><div class='add'>+		keyup-threshold-microvolt = &lt;1710000&gt;;</div><div class='add'>+</div><div class='add'>+		button-function {</div><div class='add'>+			label = "update";</div><div class='add'>+			linux,code = &lt;KEY_VENDOR&gt;;</div><div class='add'>+			press-threshold-microvolt = &lt;10000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys-polled {</div><div class='add'>+		compatible = "gpio-keys-polled";</div><div class='add'>+		poll-interval = &lt;100&gt;;</div><div class='add'>+</div><div class='add'>+		button {</div><div class='add'>+			label = "power";</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethmac {</div><div class='add'>+	pinctrl-0 = &lt;&amp;eth_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	phy-handle = &lt;&amp;external_phy&gt;;</div><div class='add'>+	amlogic,tx-delay-ns = &lt;2&gt;;</div><div class='add'>+	phy-mode = "rgmii";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;external_mdio {</div><div class='add'>+	external_phy: ethernet-phy@0 {</div><div class='add'>+		/* Realtek RTL8211F (0x001cc916) */</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		max-speed = &lt;1000&gt;;</div><div class='add'>+</div><div class='add'>+		reset-assert-us = &lt;10000&gt;;</div><div class='add'>+		reset-deassert-us = &lt;80000&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio GPIOZ_14 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio_intc&gt;;</div><div class='add'>+		/* MAC_INTR on GPIOZ_15 */</div><div class='add'>+		interrupts = &lt;25 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ir {</div><div class='add'>+	linux,rc-map-name = "rc-minix-neo";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c_B {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c_b_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	rtc: rtc@51 {</div><div class='add'>+		status = "okay";</div><div class='add'>+		compatible = "haoyu,hym8563";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-output-names = "xin32k";</div><div class='add'>+		wakeup-source;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sd_emmc_a {</div><div class='add'>+	brcmf: wifi@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		compatible = "brcm,bcm4329-fmac";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart_A {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart_a_pins&gt;, &lt;&amp;uart_a_cts_rts_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "brcm,bcm43438-bt";</div><div class='add'>+		shutdown-gpios = &lt;&amp;gpio GPIOX_17 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		max-speed = &lt;2000000&gt;;</div><div class='add'>+		clocks = &lt;&amp;wifi32k&gt;;</div><div class='add'>+		clock-names = "lpo";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts<br/>index c2bd4dbbf38c..773107cc47dd 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts</a></div><div class='hunk'>@@ -10,6 +10,7 @@</div><div class='ctx'> /dts-v1/;</div><div class='ctx'> </div><div class='ctx'> #include "meson-gxm.dtsi"</div><div class='add'>+#include &lt;dt-bindings/sound/meson-aiu.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	compatible = "nexbox,a1", "amlogic,s912", "amlogic,meson-gxm";</div><div class='hunk'>@@ -24,6 +25,12 @@</div><div class='ctx'> 		stdout-path = "serial0:115200n8";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	spdif_dit: audio-codec-0 {</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		compatible = "linux,spdif-dit";</div><div class='add'>+		sound-name-prefix = "DIT";</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	memory@0 {</div><div class='ctx'> 		device_type = "memory";</div><div class='ctx'> 		reg = &lt;0x0 0x0 0x0 0x80000000&gt;;</div><div class='hunk'>@@ -75,6 +82,62 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "amlogic,gx-sound-card";</div><div class='add'>+		model = "NEXBOX-A1";</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL1&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;294912000&gt;,</div><div class='add'>+				       &lt;270950400&gt;,</div><div class='add'>+				       &lt;393216000&gt;;</div><div class='add'>+</div><div class='add'>+		dai-link-0 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_I2S_FIFO&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-1 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_SPDIF_FIFO&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-2 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_I2S_ENCODER&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;aiu AIU_HDMI CTRL_I2S&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-3 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_SPDIF_ENCODER&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;spdif_dit&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-4 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_HDMI CTRL_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;aiu {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;spdif_out_h_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cec_AO {</div><div class='hunk'>@@ -112,7 +175,7 @@</div><div class='ctx'> 		max-speed = &lt;1000&gt;;</div><div class='ctx'> </div><div class='ctx'> 		reset-assert-us = &lt;10000&gt;;</div><div class='del'>-		reset-deassert-us = &lt;30000&gt;;</div><div class='add'>+		reset-deassert-us = &lt;80000&gt;;</div><div class='ctx'> 		reset-gpios = &lt;&amp;gpio GPIOZ_14 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='hunk'>@@ -179,6 +242,7 @@</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;usb0 {</div><div class='add'>+&amp;usb {</div><div class='ctx'> 	status = "okay";</div><div class='add'>+	dr_mode = "host";</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts<br/>index ea45ae0c71b7..feb31207773f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts</a></div><div class='hunk'>@@ -30,11 +30,9 @@</div><div class='ctx'> </div><div class='ctx'> 	gpio-keys-polled {</div><div class='ctx'> 		compatible = "gpio-keys-polled";</div><div class='del'>-		#address-cells = &lt;1&gt;;</div><div class='del'>-		#size-cells = &lt;0&gt;;</div><div class='ctx'> 		poll-interval = &lt;100&gt;;</div><div class='ctx'> </div><div class='del'>-		button@0 {</div><div class='add'>+		button {</div><div class='ctx'> 			label = "power";</div><div class='ctx'> 			linux,code = &lt;KEY_POWER&gt;;</div><div class='ctx'> 			gpios = &lt;&amp;gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW&gt;;</div><div class='hunk'>@@ -64,7 +62,7 @@</div><div class='ctx'> </div><div class='ctx'> 		/* External PHY reset is shared with internal PHY Led signal */</div><div class='ctx'> 		reset-assert-us = &lt;10000&gt;;</div><div class='del'>-		reset-deassert-us = &lt;30000&gt;;</div><div class='add'>+		reset-deassert-us = &lt;80000&gt;;</div><div class='ctx'> 		reset-gpios = &lt;&amp;gpio GPIOZ_14 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> </div><div class='ctx'> 		interrupt-parent = &lt;&amp;gpio_intc&gt;;</div><div class='hunk'>@@ -74,8 +72,7 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;sd_emmc_a {</div><div class='del'>-	brcmf: wifi@1 {</div><div class='add'>+	sdio: wifi@1 {</div><div class='ctx'> 		reg = &lt;1&gt;;</div><div class='del'>-		compatible = "brcm,bcm4329-fmac";</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-q201.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-q201.dts<br/>index d02b80d77378..6c8bec1853ac 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxm-q201.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxm-q201.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxm-q201.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxm-q201.dts</a></div><div class='hunk'>@@ -21,8 +21,7 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;sd_emmc_a {</div><div class='del'>-	brcmf: wifi@1 {</div><div class='add'>+	sdio: wifi@1 {</div><div class='ctx'> 		reg = &lt;1&gt;;</div><div class='del'>-		compatible = "brcm,bcm4329-fmac";</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts<br/>index 420a88e9a195..9d5a481b309f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts</a></div><div class='hunk'>@@ -14,6 +14,7 @@</div><div class='ctx'> /dts-v1/;</div><div class='ctx'> </div><div class='ctx'> #include "meson-gxm.dtsi"</div><div class='add'>+#include &lt;dt-bindings/sound/meson-aiu.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	compatible = "kingnovel,r-box-pro", "amlogic,s912", "amlogic,meson-gxm";</div><div class='hunk'>@@ -33,16 +34,22 @@</div><div class='ctx'> 		reg = &lt;0x0 0x0 0x0 0x80000000&gt;; /* 2 GiB or 3 GiB */</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	spdif_dit: audio-codec-0 {</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		compatible = "linux,spdif-dit";</div><div class='add'>+		sound-name-prefix = "DIT";</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	leds {</div><div class='ctx'> 		compatible = "gpio-leds";</div><div class='ctx'> </div><div class='del'>-		blue {</div><div class='add'>+		led-blue {</div><div class='ctx'> 			label = "rbox-pro:blue:on";</div><div class='ctx'> 			gpios = &lt;&amp;gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 			default-state = "on";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		red {</div><div class='add'>+		led-red {</div><div class='ctx'> 			label = "rbox-pro:red:standby";</div><div class='ctx'> 			gpios = &lt;&amp;gpio GPIODV_28 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 			default-state = "off";</div><div class='hunk'>@@ -90,6 +97,62 @@</div><div class='ctx'> 		clocks = &lt;&amp;wifi32k&gt;;</div><div class='ctx'> 		clock-names = "ext_clock";</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "amlogic,gx-sound-card";</div><div class='add'>+		model = "RBOX-PRO";</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL1&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL2&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;294912000&gt;,</div><div class='add'>+				       &lt;270950400&gt;,</div><div class='add'>+				       &lt;393216000&gt;;</div><div class='add'>+</div><div class='add'>+		dai-link-0 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_I2S_FIFO&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-1 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_SPDIF_FIFO&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-2 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_I2S_ENCODER&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;aiu AIU_HDMI CTRL_I2S&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-3 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_CPU CPU_SPDIF_ENCODER&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;spdif_dit&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-4 {</div><div class='add'>+			sound-dai = &lt;&amp;aiu AIU_HDMI CTRL_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;aiu {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;spdif_out_h_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;ethmac {</div><div class='hunk'>@@ -114,7 +177,7 @@</div><div class='ctx'> 		max-speed = &lt;1000&gt;;</div><div class='ctx'> </div><div class='ctx'> 		reset-assert-us = &lt;10000&gt;;</div><div class='del'>-		reset-deassert-us = &lt;30000&gt;;</div><div class='add'>+		reset-deassert-us = &lt;80000&gt;;</div><div class='ctx'> 		reset-gpios = &lt;&amp;gpio GPIOZ_14 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='hunk'>@@ -129,8 +192,6 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pwm_e_pins&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='del'>-	clocks = &lt;&amp;clkc CLKID_FCLK_DIV4&gt;;</div><div class='del'>-	clock-names = "clkin0";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* Wireless SDIO Module */</div><div class='hunk'>@@ -156,7 +217,7 @@</div><div class='ctx'> 	vmmc-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='ctx'> 	vqmmc-supply = &lt;&amp;vddio_boot&gt;;</div><div class='ctx'> </div><div class='del'>-	brcmf: brcmf@1 {</div><div class='add'>+	brcmf: wifi@1 {</div><div class='ctx'> 		reg = &lt;1&gt;;</div><div class='ctx'> 		compatible = "brcm,bcm4329-fmac";</div><div class='ctx'> 	};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-s912-libretech-pc.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-s912-libretech-pc.dts<br/>index 444c249863cb..a66f19851ac9 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxm-s912-libretech-pc.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxm-s912-libretech-pc.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxm-s912-libretech-pc.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxm-s912-libretech-pc.dts</a></div><div class='hunk'>@@ -14,7 +14,7 @@</div><div class='ctx'> 		     "amlogic,meson-gxm";</div><div class='ctx'> 	model = "Libre Computer AML-S912-PC";</div><div class='ctx'> </div><div class='del'>-	typec2_vbus: regulator-typec2_vbus {</div><div class='add'>+	typec2_vbus: regulator-typec2-vbus {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "TYPEC2_VBUS";</div><div class='ctx'> 		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='hunk'>@@ -54,6 +54,10 @@</div><div class='ctx'> 		vbus-supply = &lt;&amp;typec2_vbus&gt;;</div><div class='ctx'> </div><div class='ctx'> 		status = "okay";</div><div class='add'>+</div><div class='add'>+		connector {</div><div class='add'>+			compatible = "usb-c-connector";</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-tx9-pro.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-tx9-pro.dts<br/>new file mode 100644<br/>index 000000000000..9a62176cfe5a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxm-tx9-pro.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxm-tx9-pro.dts</a></div><div class='hunk'>@@ -0,0 +1,90 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2016 Endless Computers, Inc.</div><div class='add'>+ * Author: Carlo Caione &lt;carlo@endlessm.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "meson-gxm.dtsi"</div><div class='add'>+#include "meson-gx-p23x-q20x.dtsi"</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "oranth,tx9-pro", "amlogic,s912", "amlogic,meson-gxm";</div><div class='add'>+	model = "Tanix TX9 Pro";</div><div class='add'>+</div><div class='add'>+	adc-keys {</div><div class='add'>+		compatible = "adc-keys";</div><div class='add'>+		io-channels = &lt;&amp;saradc 0&gt;;</div><div class='add'>+		io-channel-names = "buttons";</div><div class='add'>+		keyup-threshold-microvolt = &lt;1710000&gt;;</div><div class='add'>+</div><div class='add'>+		button-function {</div><div class='add'>+			label = "Update";</div><div class='add'>+			linux,code = &lt;KEY_VENDOR&gt;;</div><div class='add'>+			press-threshold-microvolt = &lt;10000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys-polled {</div><div class='add'>+		compatible = "gpio-keys-polled";</div><div class='add'>+		poll-interval = &lt;100&gt;;</div><div class='add'>+</div><div class='add'>+		button {</div><div class='add'>+			label = "power";</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethmac {</div><div class='add'>+	pinctrl-0 = &lt;&amp;eth_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	phy-handle = &lt;&amp;external_phy&gt;;</div><div class='add'>+	amlogic,tx-delay-ns = &lt;2&gt;;</div><div class='add'>+	phy-mode = "rgmii";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;external_mdio {</div><div class='add'>+	external_phy: ethernet-phy@0 {</div><div class='add'>+		/* Realtek RTL8211F (0x001cc916) */</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		max-speed = &lt;1000&gt;;</div><div class='add'>+</div><div class='add'>+		reset-assert-us = &lt;10000&gt;;</div><div class='add'>+		reset-deassert-us = &lt;80000&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio GPIOZ_14 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio_intc&gt;;</div><div class='add'>+		/* MAC_INTR on GPIOZ_15 */</div><div class='add'>+		interrupts = &lt;25 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ir {</div><div class='add'>+	linux,rc-map-name = "rc-tanix-tx3mini";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sd_emmc_a {</div><div class='add'>+	brcmf: wifi@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		compatible = "brcm,bcm4329-fmac";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart_A {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart_a_pins&gt;, &lt;&amp;uart_a_cts_rts_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "brcm,bcm43438-bt";</div><div class='add'>+		shutdown-gpios = &lt;&amp;gpio GPIOX_17 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		max-speed = &lt;2000000&gt;;</div><div class='add'>+		clocks = &lt;&amp;wifi32k&gt;;</div><div class='add'>+		clock-names = "lpo";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-ugoos-am3.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-ugoos-am3.dts<br/>new file mode 100644<br/>index 000000000000..ba871f3f53bb<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxm-ugoos-am3.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxm-ugoos-am3.dts</a></div><div class='hunk'>@@ -0,0 +1,91 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2025 J. Neuschäfer &lt;j.ne@posteo.net&gt;</div><div class='add'>+ *</div><div class='add'>+ * Debug UART (3.3V, 115200 baud) at the corner of the board:</div><div class='add'>+ *   (4) (3) (2) [1]</div><div class='add'>+ *   Vcc RXD TXD GND</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/amlogic,meson-g12a-gpio-intc.h&gt;</div><div class='add'>+</div><div class='add'>+#include "meson-gxm.dtsi"</div><div class='add'>+#include "meson-gx-p23x-q20x.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "ugoos,am3", "amlogic,s912", "amlogic,meson-gxm";</div><div class='add'>+	model = "Ugoos AM3";</div><div class='add'>+</div><div class='add'>+	adc-keys {</div><div class='add'>+		compatible = "adc-keys";</div><div class='add'>+		io-channels = &lt;&amp;saradc 0&gt;;</div><div class='add'>+		io-channel-names = "buttons";</div><div class='add'>+		keyup-threshold-microvolt = &lt;1710000&gt;;</div><div class='add'>+</div><div class='add'>+		button-function {</div><div class='add'>+			label = "Update";</div><div class='add'>+			linux,code = &lt;KEY_VENDOR&gt;;</div><div class='add'>+			press-threshold-microvolt = &lt;10000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cvbs_connector {</div><div class='add'>+	/* Not used on this board */</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethmac {</div><div class='add'>+	pinctrl-0 = &lt;&amp;eth_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	/* Select external PHY by default */</div><div class='add'>+	phy-handle = &lt;&amp;external_phy&gt;;</div><div class='add'>+</div><div class='add'>+	amlogic,tx-delay-ns = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	/* External PHY is in RGMII */</div><div class='add'>+	phy-mode = "rgmii";</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;external_mdio {</div><div class='add'>+	external_phy: ethernet-phy@0 {</div><div class='add'>+		/* Realtek RTL8211F (0x001cc916) */</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		reset-assert-us = &lt;10000&gt;;</div><div class='add'>+		reset-deassert-us = &lt;80000&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio GPIOZ_14 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio_intc&gt;;</div><div class='add'>+		/* MAC_INTR on GPIOZ_15 */</div><div class='add'>+		interrupts = &lt;25 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c_B {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c_b_pins&gt;;</div><div class='add'>+</div><div class='add'>+	rtc: rtc@51 {</div><div class='add'>+		compatible = "haoyu,hym8563";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* WLAN: Atheros 10k (QCA9377) */</div><div class='add'>+&amp;sd_emmc_a {</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* eMMC */</div><div class='add'>+&amp;sd_emmc_c {</div><div class='add'>+	max-frequency = &lt;100000000&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-vega-s96.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-vega-s96.dts<br/>index 0bdf51d041ae..d3fdba4da9a6 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxm-vega-s96.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxm-vega-s96.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxm-vega-s96.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxm-vega-s96.dts</a></div><div class='hunk'>@@ -39,3 +39,7 @@</div><div class='ctx'> &amp;ir {</div><div class='ctx'> 	linux,rc-map-name = "rc-vega-s9x";</div><div class='ctx'> };</div><div class='add'>+</div><div class='add'>+&amp;usb {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-wetek-core2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-wetek-core2.dts<br/>new file mode 100644<br/>index 000000000000..f8c40340b9c5<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxm-wetek-core2.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxm-wetek-core2.dts</a></div><div class='hunk'>@@ -0,0 +1,85 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2020 Christian Hewitt &lt;christianshewitt@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "meson-gxm.dtsi"</div><div class='add'>+#include "meson-gx-p23x-q20x.dtsi"</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "wetek,core2", "amlogic,s912", "amlogic,meson-gxm";</div><div class='add'>+	model = "WeTek Core 2";</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x0 0x0 0x80000000&gt;; /* 2 GiB or 3 GiB */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-blue {</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			gpios = &lt;&amp;gpio GPIODV_24 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "on";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	adc-keys {</div><div class='add'>+		compatible = "adc-keys";</div><div class='add'>+		io-channels = &lt;&amp;saradc 0&gt;;</div><div class='add'>+		io-channel-names = "buttons";</div><div class='add'>+		keyup-threshold-microvolt = &lt;1710000&gt;;</div><div class='add'>+</div><div class='add'>+		button-update {</div><div class='add'>+			label = "update";</div><div class='add'>+			linux,code = &lt;KEY_VENDOR&gt;;</div><div class='add'>+			press-threshold-microvolt = &lt;10000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys-polled {</div><div class='add'>+		compatible = "gpio-keys-polled";</div><div class='add'>+		poll-interval = &lt;100&gt;;</div><div class='add'>+</div><div class='add'>+		button-power {</div><div class='add'>+			label = "power";</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Disabled as Realtek RTL8152 USB provides Ethernet */</div><div class='add'>+&amp;ethmac {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;internal_phy {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ir {</div><div class='add'>+	linux,rc-map-name = "rc-wetek-play2";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* This is connected to the Bluetooth module: */</div><div class='add'>+&amp;uart_A {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart_a_pins&gt;, &lt;&amp;uart_a_cts_rts_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "brcm,bcm43438-bt";</div><div class='add'>+		shutdown-gpios = &lt;&amp;gpio GPIOX_17 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		max-speed = &lt;2000000&gt;;</div><div class='add'>+		clocks = &lt;&amp;wifi32k&gt;;</div><div class='add'>+		clock-names = "lpo";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi<br/>index b6f89f108e28..514c9bea6423 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-gxm.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-gxm.dtsi</a></div><div class='hunk'>@@ -42,11 +42,34 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@1 {</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@2 {</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@3 {</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		cpu4: cpu@100 {</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			reg = &lt;0x0 0x100&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			d-cache-line-size = &lt;32&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-sets = &lt;32&gt;;</div><div class='add'>+			i-cache-line-size = &lt;32&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-sets = &lt;32&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;l2&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;scpi_dvfs 1&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='hunk'>@@ -57,6 +80,13 @@</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			reg = &lt;0x0 0x101&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			d-cache-line-size = &lt;32&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-sets = &lt;32&gt;;</div><div class='add'>+			i-cache-line-size = &lt;32&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-sets = &lt;32&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;l2&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;scpi_dvfs 1&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='hunk'>@@ -67,6 +97,13 @@</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			reg = &lt;0x0 0x102&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			d-cache-line-size = &lt;32&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-sets = &lt;32&gt;;</div><div class='add'>+			i-cache-line-size = &lt;32&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-sets = &lt;32&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;l2&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;scpi_dvfs 1&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='hunk'>@@ -77,11 +114,47 @@</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			reg = &lt;0x0 0x103&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			d-cache-line-size = &lt;32&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-sets = &lt;32&gt;;</div><div class='add'>+			i-cache-line-size = &lt;32&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-sets = &lt;32&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;l2&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;scpi_dvfs 1&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	gpu_opp_table: opp-table {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		opp-125000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;125000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;950000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-250000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;250000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;950000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-285714285 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;285714285&gt;;</div><div class='add'>+			opp-microvolt = &lt;950000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-400000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;400000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;950000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-500000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;500000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;950000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-666666666 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;666666666&gt;;</div><div class='add'>+			opp-microvolt = &lt;950000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;apb {</div><div class='hunk'>@@ -106,21 +179,7 @@</div><div class='ctx'> 		interrupt-names = "job", "mmu", "gpu";</div><div class='ctx'> 		clocks = &lt;&amp;clkc CLKID_MALI&gt;;</div><div class='ctx'> 		resets = &lt;&amp;reset RESET_MALI_CAPB3&gt;, &lt;&amp;reset RESET_MALI&gt;;</div><div class='del'>-</div><div class='del'>-		/*</div><div class='del'>-		 * Mali clocking is provided by two identical clock paths</div><div class='del'>-		 * MALI_0 and MALI_1 muxed to a single clock by a glitch</div><div class='del'>-		 * free mux to safely change frequency while running.</div><div class='del'>-		 */</div><div class='del'>-		assigned-clocks = &lt;&amp;clkc CLKID_MALI_0_SEL&gt;,</div><div class='del'>-				  &lt;&amp;clkc CLKID_MALI_0&gt;,</div><div class='del'>-				  &lt;&amp;clkc CLKID_MALI&gt;; /* Glitch free mux */</div><div class='del'>-		assigned-clock-parents = &lt;&amp;clkc CLKID_FCLK_DIV3&gt;,</div><div class='del'>-					 &lt;0&gt;, /* Do Nothing */</div><div class='del'>-					 &lt;&amp;clkc CLKID_MALI_0&gt;;</div><div class='del'>-		assigned-clock-rates = &lt;0&gt;, /* Do Nothing */</div><div class='del'>-				       &lt;666666666&gt;,</div><div class='del'>-				       &lt;0&gt;; /* Do Nothing */</div><div class='add'>+		operating-points-v2 = &lt;&amp;gpu_opp_table&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -169,8 +228,11 @@</div><div class='ctx'> 	compatible = "amlogic,meson-gxm-dw-hdmi", "amlogic,meson-gx-dw-hdmi";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;dwc3 {</div><div class='del'>-	phys = &lt;&amp;usb3_phy&gt;, &lt;&amp;usb2_phy0&gt;, &lt;&amp;usb2_phy1&gt;, &lt;&amp;usb2_phy2&gt;;</div><div class='add'>+&amp;usb {</div><div class='add'>+	compatible = "amlogic,meson-gxm-usb-ctrl";</div><div class='add'>+</div><div class='add'>+	phy-names = "usb2-phy0", "usb2-phy1", "usb2-phy2";</div><div class='add'>+	phys = &lt;&amp;usb2_phy0&gt;, &lt;&amp;usb2_phy1&gt;, &lt;&amp;usb2_phy2&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;vdec {</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3-ts050.dtso b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3-ts050.dtso<br/>new file mode 100644<br/>index 000000000000..a41b4e619580<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-khadas-vim3-ts050.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-khadas-vim3-ts050.dtso</a></div><div class='hunk'>@@ -0,0 +1,108 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2019 BayLibre, SAS</div><div class='add'>+ * Author: Neil Armstrong &lt;narmstrong@baylibre.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/g12a-clkc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/amlogic,meson-g12a-gpio-intc.h&gt;</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Enable Khadas TS050 DSI Panel + Touch Controller</div><div class='add'>+ * on Khadas VIM3 (A311D) and VIM3L (S905D3)</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;{/} {</div><div class='add'>+	panel_backlight: backlight {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		pwms = &lt;&amp;pwm_AO_cd 0 25000 0&gt;;</div><div class='add'>+		brightness-levels = &lt;0 255&gt;;</div><div class='add'>+		num-interpolated-steps = &lt;255&gt;;</div><div class='add'>+		default-brightness-level = &lt;200&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c3_sda_a_pins&gt;, &lt;&amp;i2c3_sck_a_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	touch-controller@38 {</div><div class='add'>+		compatible = "edt,edt-ft5206";</div><div class='add'>+		reg = &lt;0x38&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio_intc&gt;;</div><div class='add'>+		interrupts = &lt;IRQID_GPIOA_5 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio_expander 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		touchscreen-size-x = &lt;1080&gt;;</div><div class='add'>+		touchscreen-size-y = &lt;1920&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_dsi {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	assigned-clocks = &lt;&amp;clkc CLKID_GP0_PLL&gt;,</div><div class='add'>+			  &lt;&amp;clkc CLKID_MIPI_DSI_PXCLK_SEL&gt;,</div><div class='add'>+			  &lt;&amp;clkc CLKID_MIPI_DSI_PXCLK&gt;,</div><div class='add'>+			  &lt;&amp;clkc CLKID_CTS_ENCL_SEL&gt;,</div><div class='add'>+			  &lt;&amp;clkc CLKID_VCLK2_SEL&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;0&gt;,</div><div class='add'>+				 &lt;&amp;clkc CLKID_GP0_PLL&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;&amp;clkc CLKID_VCLK2_DIV1&gt;,</div><div class='add'>+				 &lt;&amp;clkc CLKID_GP0_PLL&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;960000000&gt;,</div><div class='add'>+			       &lt;0&gt;,</div><div class='add'>+			       &lt;960000000&gt;,</div><div class='add'>+			       &lt;0&gt;,</div><div class='add'>+			       &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	panel@0 {</div><div class='add'>+		compatible = "khadas,ts050";</div><div class='add'>+		reset-gpios = &lt;&amp;gpio_expander 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;gpio_expander 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		power-supply = &lt;&amp;vcc_3v3&gt;;</div><div class='add'>+		backlight = &lt;&amp;panel_backlight&gt;;</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			mipi_in_panel: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;mipi_out_panel&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		port@1 {</div><div class='add'>+			mipi_out_panel: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;mipi_in_panel&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_analog_dphy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_dphy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm_AO_cd {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm_ao_c_6_pins&gt;, &lt;&amp;pwm_ao_d_e_pins&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi<br/>index 094ecf2222bb..7daa9b122d5c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi</a></div><div class='hunk'>@@ -6,12 +6,16 @@</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/gpio/meson-g12a-gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/meson-g12a-tohdmitx.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	aliases {</div><div class='ctx'> 		serial0 = &amp;uart_AO;</div><div class='ctx'> 		ethernet0 = &amp;ethmac;</div><div class='add'>+		rtc0 = &amp;rtc;</div><div class='add'>+		rtc1 = &amp;vrtc;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	chosen {</div><div class='hunk'>@@ -39,15 +43,17 @@</div><div class='ctx'> 	leds {</div><div class='ctx'> 		compatible = "gpio-leds";</div><div class='ctx'> </div><div class='del'>-		white {</div><div class='del'>-			label = "vim3:white:sys";</div><div class='del'>-			gpios = &lt;&amp;gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		led-white {</div><div class='add'>+			color = &lt;LED_COLOR_ID_WHITE&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			gpios = &lt;&amp;gpio_ao GPIOAO_4 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 			linux,default-trigger = "heartbeat";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		red {</div><div class='del'>-			label = "vim3:red";</div><div class='del'>-			gpios = &lt;&amp;gpio_expander 5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		led-red {</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			gpios = &lt;&amp;gpio_expander 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -74,7 +80,7 @@</div><div class='ctx'> 		clock-names = "ext_clock";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	dc_in: regulator-dc_in {</div><div class='add'>+	dc_in: regulator-dc-in {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "DC_IN";</div><div class='ctx'> 		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='hunk'>@@ -82,7 +88,7 @@</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vcc_5v: regulator-vcc_5v {</div><div class='add'>+	vcc_5v: regulator-vcc-5v {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VCC_5V";</div><div class='ctx'> 		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='hunk'>@@ -93,7 +99,7 @@</div><div class='ctx'> 		enable-active-high;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vcc_1v8: regulator-vcc_1v8 {</div><div class='add'>+	vcc_1v8: regulator-vcc-1v8 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VCC_1V8";</div><div class='ctx'> 		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='hunk'>@@ -102,7 +108,7 @@</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vcc_3v3: regulator-vcc_3v3 {</div><div class='add'>+	vcc_3v3: regulator-vcc-3v3 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VCC_3V3";</div><div class='ctx'> 		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='hunk'>@@ -112,7 +118,7 @@</div><div class='ctx'> 		/* FIXME: actually controlled by VDDCPU_B_EN */</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vddao_1v8: regulator-vddao_1v8 {</div><div class='add'>+	vddao_1v8: regulator-vddao-1v8 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VDDIO_AO1V8";</div><div class='ctx'> 		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='hunk'>@@ -121,7 +127,7 @@</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	emmc_1v8: regulator-emmc_1v8 {</div><div class='add'>+	emmc_1v8: regulator-emmc-1v8 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "EMMC_AO1V8";</div><div class='ctx'> 		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='hunk'>@@ -130,7 +136,7 @@</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vsys_3v3: regulator-vsys_3v3 {</div><div class='add'>+	vsys_3v3: regulator-vsys-3v3 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VSYS_3V3";</div><div class='ctx'> 		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='hunk'>@@ -139,7 +145,7 @@</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	usb_pwr: regulator-usb_pwr {</div><div class='add'>+	usb_pwr: regulator-usb-pwr {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "USB_PWR";</div><div class='ctx'> 		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='hunk'>@@ -161,6 +167,82 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "amlogic,axg-sound-card";</div><div class='add'>+		model = "KHADAS-VIM3";</div><div class='add'>+		audio-aux-devs = &lt;&amp;tdmin_a&gt;, &lt;&amp;tdmout_a&gt;;</div><div class='add'>+		audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",</div><div class='add'>+				"TDMOUT_A IN 1", "FRDDR_B OUT 0",</div><div class='add'>+				"TDMOUT_A IN 2", "FRDDR_C OUT 0",</div><div class='add'>+				"TDM_A Playback", "TDMOUT_A OUT",</div><div class='add'>+				"TDMIN_A IN 0", "TDM_A Capture",</div><div class='add'>+				"TDMIN_A IN 3", "TDM_A Loopback",</div><div class='add'>+				"TODDR_A IN 0", "TDMIN_A OUT",</div><div class='add'>+				"TODDR_B IN 0", "TDMIN_A OUT",</div><div class='add'>+				"TODDR_C IN 0", "TDMIN_A OUT";</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;294912000&gt;,</div><div class='add'>+				       &lt;270950400&gt;,</div><div class='add'>+				       &lt;393216000&gt;;</div><div class='add'>+</div><div class='add'>+		dai-link-0 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_a&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-1 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_b&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-2 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_c&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-3 {</div><div class='add'>+			sound-dai = &lt;&amp;toddr_a&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-4 {</div><div class='add'>+			sound-dai = &lt;&amp;toddr_b&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-5 {</div><div class='add'>+			sound-dai = &lt;&amp;toddr_c&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* 8ch hdmi interface */</div><div class='add'>+		dai-link-6 {</div><div class='add'>+			sound-dai = &lt;&amp;tdmif_a&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			dai-tdm-slot-tx-mask-0 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-1 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-2 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-3 = &lt;1 1&gt;;</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_IN_A&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* hdmi glue */</div><div class='add'>+		dai-link-7 {</div><div class='add'>+			sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	wifi32k: wifi32k {</div><div class='ctx'> 		compatible = "pwm-clock";</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='hunk'>@@ -169,6 +251,14 @@</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;arb {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;clkc_audio {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;cec_AO {</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;cec_ao_a_h_pins&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='hunk'>@@ -183,6 +273,23 @@</div><div class='ctx'> 	hdmi-phandle = &lt;&amp;hdmi_tx&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;cpu_thermal {</div><div class='add'>+	trips {</div><div class='add'>+		cpu_active: cpu-active {</div><div class='add'>+			temperature = &lt;80000&gt;; /* millicelsius */</div><div class='add'>+			hysteresis = &lt;2000&gt;; /* millicelsius */</div><div class='add'>+			type = "active";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cooling-maps {</div><div class='add'>+		map {</div><div class='add'>+			trip = &lt;&amp;cpu_active&gt;;</div><div class='add'>+			cooling-device = &lt;&amp;khadas_mcu THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;ext_mdio {</div><div class='ctx'> 	external_phy: ethernet-phy@0 {</div><div class='ctx'> 		/* Realtek RTL8211F (0x001cc916) */</div><div class='hunk'>@@ -196,12 +303,24 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;ethmac {</div><div class='del'>-        pinctrl-0 = &lt;&amp;eth_pins&gt;, &lt;&amp;eth_rgmii_pins&gt;;</div><div class='del'>-        pinctrl-names = "default";</div><div class='del'>-        status = "okay";</div><div class='del'>-        phy-mode = "rgmii";</div><div class='del'>-        phy-handle = &lt;&amp;external_phy&gt;;</div><div class='del'>-        amlogic,tx-delay-ns = &lt;2&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;eth_pins&gt;, &lt;&amp;eth_rgmii_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+	phy-mode = "rgmii";</div><div class='add'>+	phy-handle = &lt;&amp;external_phy&gt;;</div><div class='add'>+	amlogic,tx-delay-ns = &lt;2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_c {</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;hdmi_tx {</div><div class='hunk'>@@ -222,6 +341,12 @@</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;i2c_ao_sck_pins&gt;, &lt;&amp;i2c_ao_sda_pins&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> </div><div class='add'>+	khadas_mcu: system-controller@18 {</div><div class='add'>+		compatible = "khadas,mcu";</div><div class='add'>+		reg = &lt;0x18&gt;;</div><div class='add'>+		#cooling-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	gpio_expander: gpio-controller@20 {</div><div class='ctx'> 		compatible = "ti,tca6408";</div><div class='ctx'> 		reg = &lt;0x20&gt;;</div><div class='hunk'>@@ -230,7 +355,7 @@</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	rtc@51 {</div><div class='add'>+	rtc: rtc@51 {</div><div class='ctx'> 		compatible = "haoyu,hym8563";</div><div class='ctx'> 		reg = &lt;0x51&gt;;</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='hunk'>@@ -249,9 +374,9 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;pwm_ef {</div><div class='del'>-        status = "okay";</div><div class='del'>-        pinctrl-0 = &lt;&amp;pwm_e_pins&gt;;</div><div class='del'>-        pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm_e_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;saradc {</div><div class='hunk'>@@ -270,7 +395,6 @@</div><div class='ctx'> </div><div class='ctx'> 	bus-width = &lt;4&gt;;</div><div class='ctx'> 	cap-sd-highspeed;</div><div class='del'>-	sd-uhs-sdr50;</div><div class='ctx'> 	max-frequency = &lt;100000000&gt;;</div><div class='ctx'> </div><div class='ctx'> 	non-removable;</div><div class='hunk'>@@ -337,7 +461,7 @@</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;nor_pins&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> </div><div class='del'>-	w25q32: spi-flash@0 {</div><div class='add'>+	w25q128: flash@0 {</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;1&gt;;</div><div class='ctx'> 		compatible = "winbond,w25q128fw", "jedec,spi-nor";</div><div class='hunk'>@@ -346,6 +470,34 @@</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;tdmif_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmin_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmout_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;toddr_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;toddr_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;toddr_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tohdmitx {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;uart_A {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;uart_a_pins&gt;, &lt;&amp;uart_a_cts_rts_pins&gt;;</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-libretech-cottonwood.dtsi b/arch/arm64/boot/dts/amlogic/meson-libretech-cottonwood.dtsi<br/>new file mode 100644<br/>index 000000000000..ac9c4c2673b1<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-libretech-cottonwood.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-libretech-cottonwood.dtsi</a></div><div class='hunk'>@@ -0,0 +1,612 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2023 BayLibre, SAS.</div><div class='add'>+ * Author: Jerome Brunet &lt;jbrunet@baylibre.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/g12a-clkc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/meson-g12a-gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/meson-g12a-toacodec.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/meson-g12a-tohdmitx.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart_AO;</div><div class='add'>+		ethernet0 = &amp;ethmac;</div><div class='add'>+		spi0 = &amp;spifc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x0 0x0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dioo2133: audio-amplifier-0 {</div><div class='add'>+		compatible = "simple-audio-amplifier";</div><div class='add'>+		enable-gpios = &lt;&amp;gpio GPIOX_0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		VCC-supply = &lt;&amp;vcc_5v&gt;;</div><div class='add'>+		sound-name-prefix = "10U2";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* TOFIX: handle CVBS_DET on SARADC channel 0 */</div><div class='add'>+	cvbs-connector {</div><div class='add'>+		compatible = "composite-video-connector";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			cvbs_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;cvbs_vdac_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	emmc_pwrseq: emmc-pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-emmc";</div><div class='add'>+		reset-gpios = &lt;&amp;gpio BOOT_12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdmi-connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		type = "a";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			hdmi_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_tx_tmds_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	led-blue {</div><div class='add'>+		compatible = "pwm-leds";</div><div class='add'>+</div><div class='add'>+		led {</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			function = LED_FUNCTION_ACTIVITY;</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+			max-brightness = &lt;255&gt;;</div><div class='add'>+			pwms = &lt;&amp;pwm_ab 1 1250 0&gt;;</div><div class='add'>+			active-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	led-green {</div><div class='add'>+		compatible = "pwm-leds";</div><div class='add'>+</div><div class='add'>+		led {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			linux,default-trigger = "default-on";</div><div class='add'>+			max-brightness = &lt;255&gt;;</div><div class='add'>+			pwms = &lt;&amp;pwm_cd 1 1250 0&gt;;</div><div class='add'>+			active-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	led-orange {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led {</div><div class='add'>+			color = &lt;LED_COLOR_ID_AMBER&gt;;</div><div class='add'>+			function = LED_FUNCTION_STANDBY;</div><div class='add'>+			gpios = &lt;&amp;gpio GPIOX_6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			panic-indicator;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dc_in: regulator-dc-in {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "5V_IN";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	flash_1v8: regulator-flash-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "FLASH_1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		vin-supply = &lt;&amp;vcc_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vcc_card: regulator-vcc-card {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCC_CARD";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio GPIOX_2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio-open-drain;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vcc_3v3: regulator-vcc-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCC_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		vin-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+</div><div class='add'>+		/* FIXME: controlled by TEST_N */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vcc_5v: regulator-vcc-5v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCC_5V";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		vin-supply = &lt;&amp;dc_in&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio GPIOH_8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio-open-drain;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddao_3v3: regulator-vddao-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDAO_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		vin-supply = &lt;&amp;dc_in&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddcpu_b: regulator-vddcpu-b {</div><div class='add'>+		compatible = "pwm-regulator";</div><div class='add'>+		regulator-name = "VDDCPU_B";</div><div class='add'>+		regulator-min-microvolt = &lt;730000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1011000&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		pwm-supply = &lt;&amp;dc_in&gt;;</div><div class='add'>+		pwms = &lt;&amp;pwm_AO_cd 1 1250 0&gt;;</div><div class='add'>+		pwm-dutycycle-range = &lt;100 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddio_ao18: regulator-vddio-ao18 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDIO_AO18";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		vin-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddio_c: regulator-vddio-c {</div><div class='add'>+		compatible = "regulator-gpio";</div><div class='add'>+		regulator-name = "VDDIO_C";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-settling-time-up-us = &lt;200&gt;;</div><div class='add'>+		regulator-settling-time-down-us = &lt;50000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+		gpios = &lt;&amp;gpio GPIOX_4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		states = &lt;3300000 0&gt;,</div><div class='add'>+			 &lt;1800000 1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "amlogic,axg-sound-card";</div><div class='add'>+		audio-widgets = "Line", "Lineout";</div><div class='add'>+		audio-aux-devs = &lt;&amp;tdmout_a&gt;, &lt;&amp;tdmout_b&gt;, &lt;&amp;tdmout_c&gt;,</div><div class='add'>+				 &lt;&amp;tdmin_a&gt;, &lt;&amp;tdmin_b&gt;, &lt;&amp;tdmin_c&gt;,</div><div class='add'>+				 &lt;&amp;dioo2133&gt;;</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;294912000&gt;,</div><div class='add'>+				       &lt;270950400&gt;,</div><div class='add'>+				       &lt;393216000&gt;;</div><div class='add'>+</div><div class='add'>+		dai-link-0 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_a&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-1 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_b&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-2 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_c&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-3 {</div><div class='add'>+			sound-dai = &lt;&amp;toddr_a&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-4 {</div><div class='add'>+			sound-dai = &lt;&amp;toddr_b&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-5 {</div><div class='add'>+			sound-dai = &lt;&amp;toddr_c&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Audio setup: The 40 pins header provides access to 2 TDMs,</div><div class='add'>+		 * SPDIF In/Out and PDM inputs.</div><div class='add'>+		 * - TDM A: 2 lanes</div><div class='add'>+		 *    D0:    40/X9</div><div class='add'>+		 *    D1:    38/X8</div><div class='add'>+		 *    BCLK:  12/X11</div><div class='add'>+		 *    FS:    35/X10</div><div class='add'>+		 * - TDM B: 4 lanes</div><div class='add'>+		 *    D0:    37/A3</div><div class='add'>+		 *    D1:    16/A4</div><div class='add'>+		 *    D2:    18/A5 or 7/AO6</div><div class='add'>+		 *    D3:    22/A6 or 21/H5</div><div class='add'>+		 *    BCLK:  29/A1 or 8/AO8</div><div class='add'>+		 *    FS:    31/A2 or 11/AO7</div><div class='add'>+		 * - 2 Master Clocks:</div><div class='add'>+		 *    MCLK0: 15/A0 or 10/AO9</div><div class='add'>+		 *    MCLK1: 33/X15</div><div class='add'>+		 * - SPDIF:</div><div class='add'>+		 *    OUT:   32/A11</div><div class='add'>+		 *    IN:    21/H5</div><div class='add'>+		 * - PDM Input:</div><div class='add'>+		 *    DO:    13/A8</div><div class='add'>+		 *    D1:    26/A9</div><div class='add'>+		 *    D2:    22/A6</div><div class='add'>+		 *    D3:    18/A5</div><div class='add'>+		 *    DCLK:  36/A7</div><div class='add'>+		 *</div><div class='add'>+		 * TDM C is not usable on the 40 pins connector so it is</div><div class='add'>+		 * setup for the HDMI 4 lanes i2s.</div><div class='add'>+		 *</div><div class='add'>+		 * No pinctrl is enabled by default to preserve the</div><div class='add'>+		 * genericity of the 40 pins header. Many configurations are</div><div class='add'>+		 * possible based on the desired use case. Please adjust TDM</div><div class='add'>+		 * masks, clock setups and pinctrl accordingly.</div><div class='add'>+		 */</div><div class='add'>+</div><div class='add'>+		dai-link-6 {</div><div class='add'>+			sound-dai = &lt;&amp;tdmif_a&gt;;</div><div class='add'>+			dai-format = "dsp_a";</div><div class='add'>+			dai-tdm-slot-tx-mask-0 = &lt;1 1&gt;;</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_IN_A&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			codec-1 {</div><div class='add'>+				sound-dai = &lt;&amp;toacodec TOACODEC_IN_A&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-7 {</div><div class='add'>+			sound-dai = &lt;&amp;tdmif_b&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			dai-tdm-slot-tx-mask-0 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-rx-mask-1 = &lt;1 1&gt;;</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_IN_B&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			codec-1 {</div><div class='add'>+				sound-dai = &lt;&amp;toacodec TOACODEC_IN_B&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-8 {</div><div class='add'>+			sound-dai = &lt;&amp;tdmif_c&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			dai-tdm-slot-tx-mask-0 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-1 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-2 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-3 = &lt;1 1&gt;;</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_IN_C&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			codec-1 {</div><div class='add'>+				sound-dai = &lt;&amp;toacodec TOACODEC_IN_C&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-9 {</div><div class='add'>+			sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-10 {</div><div class='add'>+			sound-dai = &lt;&amp;toacodec TOACODEC_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;acodec&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;acodec {</div><div class='add'>+	status = "okay";</div><div class='add'>+	AVDD-supply = &lt;&amp;vddio_ao18&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;arb {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cecb_AO {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;cec_ao_b_h_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	hdmi-phandle = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;clkc_audio {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cvbs_vdac_port {</div><div class='add'>+	cvbs_vdac_out: endpoint {</div><div class='add'>+		remote-endpoint = &lt;&amp;cvbs_connector_in&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dwc3 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	hub: hub@1 {</div><div class='add'>+		compatible = "usb5e3,626";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio GPIOC_7 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;vcc_5v&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethmac {</div><div class='add'>+	pinctrl-0 = &lt;&amp;eth_pins&gt;, &lt;&amp;eth_rgmii_pins&gt;, &lt;&amp;eth_phy_irq_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+	phy-mode = "rgmii";</div><div class='add'>+	phy-handle = &lt;&amp;external_phy&gt;;</div><div class='add'>+	amlogic,tx-delay-ns = &lt;2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ext_mdio {</div><div class='add'>+	external_phy: ethernet-phy@0 {</div><div class='add'>+		/* Realtek RTL8211F (0x001cc916) */</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		max-speed = &lt;1000&gt;;</div><div class='add'>+</div><div class='add'>+		reset-assert-us = &lt;100000&gt;;</div><div class='add'>+		reset-deassert-us = &lt;100000&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio_intc&gt;;</div><div class='add'>+		/* MAC_INTR on GPIOZ_14 */</div><div class='add'>+		interrupts = &lt;26 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;hdmitx_hpd_pins&gt;, &lt;&amp;hdmitx_ddc_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	hdmi-supply = &lt;&amp;vcc_5v&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx_tmds_port {</div><div class='add'>+	hdmi_tx_tmds_out: endpoint {</div><div class='add'>+		remote-endpoint = &lt;&amp;hdmi_connector_in&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ir {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;remote_input_ao_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;periphs_pinctrl {</div><div class='add'>+	spi_cs_disable_pins: spi-cs-disable {</div><div class='add'>+		mux {</div><div class='add'>+			groups = "BOOT_14";</div><div class='add'>+			function = "gpio_periphs";</div><div class='add'>+			bias-disable;</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eth_phy_irq_pins: eth-phy-irq {</div><div class='add'>+		mux {</div><div class='add'>+			groups = "GPIOZ_14";</div><div class='add'>+			function = "gpio_periphs";</div><div class='add'>+			bias-pull-up;</div><div class='add'>+			output-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm_AO_cd {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm_ao_d_e_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm_ab {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm_b_x7_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm_cd {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm_d_x3_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;saradc {</div><div class='add'>+	status = "okay";</div><div class='add'>+	vref-supply = &lt;&amp;vddio_ao18&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SD card */</div><div class='add'>+&amp;sd_emmc_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdcard_c_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;sdcard_clk_gate_c_pins&gt;;</div><div class='add'>+	pinctrl-names = "default", "clk-gate";</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	sd-uhs-sdr12;</div><div class='add'>+	sd-uhs-sdr25;</div><div class='add'>+	sd-uhs-sdr50;</div><div class='add'>+	sd-uhs-sdr104;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+</div><div class='add'>+	cd-gpios = &lt;&amp;gpio GPIOC_6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;vcc_card&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;vddio_c&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * EMMC_D4, EMMC_D5, EMMC_D6 and EMMC_D7 pins are shared between SPI NOR CS</div><div class='add'>+ * and eMMC Data 4 to 7 pins.</div><div class='add'>+ * Replace emmc_data_8b_pins to emmc_data_4b_pins from sd_emmc_c pinctrl-0,</div><div class='add'>+ * and change bus-width to 4 then spifc can be enabled.</div><div class='add'>+ */</div><div class='add'>+&amp;sd_emmc_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;emmc_ctrl_pins&gt;, &lt;&amp;emmc_data_8b_pins&gt;, &lt;&amp;emmc_ds_pins&gt;,</div><div class='add'>+		    &lt;&amp;spi_cs_disable_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;emmc_clk_gate_pins&gt;;</div><div class='add'>+	pinctrl-names = "default", "clk-gate";</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	cap-mmc-highspeed;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+</div><div class='add'>+	mmc-pwrseq = &lt;&amp;emmc_pwrseq&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;vcc_3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;flash_1v8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spifc {</div><div class='add'>+	status = "disabled";</div><div class='add'>+	pinctrl-0 = &lt;&amp;nor_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	cs-gpios = &lt;&amp;gpio BOOT_14 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+	w25lq128d: flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		spi-max-frequency = &lt;80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmif_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmif_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmif_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmin_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmin_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmin_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmout_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmout_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmout_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;toacodec {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;toddr_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;toddr_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;toddr_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tohdmitx {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart_AO {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart_ao_a_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb2_phy1 {</div><div class='add'>+	phy-supply = &lt;&amp;dc_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_pcie_phy {</div><div class='add'>+	phy-supply = &lt;&amp;vcc_5v&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts b/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts<br/>new file mode 100644<br/>index 000000000000..6730c44642d2<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts</a></div><div class='hunk'>@@ -0,0 +1,237 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2021 Amlogic, Inc. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "meson-s4.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Amlogic Meson S4 AQ222 Development Board";</div><div class='add'>+	compatible = "amlogic,aq222", "amlogic,s4";</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart_b;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x0 0x0 0x40000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		/* 52 MiB reserved for ARM Trusted Firmware */</div><div class='add'>+		secmon_reserved: secmon@5000000 {</div><div class='add'>+			reg = &lt;0x0 0x05000000 0x0 0x3400000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdio_32k: sdio-32k {</div><div class='add'>+		compatible = "pwm-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;32768&gt;;</div><div class='add'>+		pwms = &lt;&amp;pwm_ef 0 30518 0&gt;; /* PWM_E at 32.768KHz */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdio_pwrseq: sdio-pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-simple";</div><div class='add'>+		reset-gpios = &lt;&amp;gpio GPIOX_6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		clocks = &lt;&amp;sdio_32k&gt;;</div><div class='add'>+		clock-names = "ext_clock";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	main_12v: regulator-main-12v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "12V";</div><div class='add'>+		regulator-min-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddao_3v3: regulator-vddao-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDAO_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;main_12v&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddio_ao1v8: regulator-vddio-ao1v8 {</div><div class='add'>+	       compatible = "regulator-fixed";</div><div class='add'>+	       regulator-name = "VDDIO_AO1V8";</div><div class='add'>+	       regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+	       regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	       vin-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+	       regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SY8120B1ABC DC/DC Regulator. */</div><div class='add'>+	vddcpu: regulator-vddcpu {</div><div class='add'>+		compatible = "pwm-regulator";</div><div class='add'>+</div><div class='add'>+		regulator-name = "VDDCPU";</div><div class='add'>+		regulator-min-microvolt = &lt;689000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1049000&gt;;</div><div class='add'>+</div><div class='add'>+		vin-supply = &lt;&amp;main_12v&gt;;</div><div class='add'>+</div><div class='add'>+		pwms = &lt;&amp;pwm_ij 1 1500 0&gt;;</div><div class='add'>+		pwm-dutycycle-range = &lt;100 0&gt;;</div><div class='add'>+</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		/* Voltage Duty-Cycle */</div><div class='add'>+		voltage-table = &lt;1049000 0&gt;,</div><div class='add'>+				&lt;1039000 3&gt;,</div><div class='add'>+				&lt;1029000 6&gt;,</div><div class='add'>+				&lt;1019000 9&gt;,</div><div class='add'>+				&lt;1009000 12&gt;,</div><div class='add'>+				&lt;999000 14&gt;,</div><div class='add'>+				&lt;989000 17&gt;,</div><div class='add'>+				&lt;979000 20&gt;,</div><div class='add'>+				&lt;969000 23&gt;,</div><div class='add'>+				&lt;959000 26&gt;,</div><div class='add'>+				&lt;949000 29&gt;,</div><div class='add'>+				&lt;939000 31&gt;,</div><div class='add'>+				&lt;929000 34&gt;,</div><div class='add'>+				&lt;919000 37&gt;,</div><div class='add'>+				&lt;909000 40&gt;,</div><div class='add'>+				&lt;899000 43&gt;,</div><div class='add'>+				&lt;889000 45&gt;,</div><div class='add'>+				&lt;879000 48&gt;,</div><div class='add'>+				&lt;869000 51&gt;,</div><div class='add'>+				&lt;859000 54&gt;,</div><div class='add'>+				&lt;849000 56&gt;,</div><div class='add'>+				&lt;839000 59&gt;,</div><div class='add'>+				&lt;829000 62&gt;,</div><div class='add'>+				&lt;819000 65&gt;,</div><div class='add'>+				&lt;809000 68&gt;,</div><div class='add'>+				&lt;799000 70&gt;,</div><div class='add'>+				&lt;789000 73&gt;,</div><div class='add'>+				&lt;779000 76&gt;,</div><div class='add'>+				&lt;769000 79&gt;,</div><div class='add'>+				&lt;759000 81&gt;,</div><div class='add'>+				&lt;749000 84&gt;,</div><div class='add'>+				&lt;739000 87&gt;,</div><div class='add'>+				&lt;729000 89&gt;,</div><div class='add'>+				&lt;719000 92&gt;,</div><div class='add'>+				&lt;709000 95&gt;,</div><div class='add'>+				&lt;699000 98&gt;,</div><div class='add'>+				&lt;689000 100&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm_ef {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm_e_pins1&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm_ij {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ir {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;remote_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sdio {</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdio_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;sdio_clk_gate_pins&gt;;</div><div class='add'>+	pinctrl-names = "default", "clk-gate";</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	sd-uhs-sdr50;</div><div class='add'>+	sd-uhs-sdr104;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	disable-wp;</div><div class='add'>+	no-sd;</div><div class='add'>+	no-mmc;</div><div class='add'>+	vmmc-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;vddio_ao1v8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sd {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdcard_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;sdcard_clk_gate_pins&gt;;</div><div class='add'>+	pinctrl-names = "default", "clk-gate";</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+</div><div class='add'>+	cd-gpios = &lt;&amp;gpio GPIOC_6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;nand {</div><div class='add'>+	status = "okay";</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl-0 = &lt;&amp;nand_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	nand@0 {</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		nand-on-flash-bbt;</div><div class='add'>+</div><div class='add'>+		partition@0 {</div><div class='add'>+			label = "boot";</div><div class='add'>+			reg = &lt;0x0 0x00200000&gt;;</div><div class='add'>+		};</div><div class='add'>+		partition@200000 {</div><div class='add'>+			label = "env";</div><div class='add'>+			reg = &lt;0x00200000 0x00400000&gt;;</div><div class='add'>+		};</div><div class='add'>+		partition@600000 {</div><div class='add'>+			label = "system";</div><div class='add'>+			reg = &lt;0x00600000 0x00a00000&gt;;</div><div class='add'>+		};</div><div class='add'>+		partition@1000000 {</div><div class='add'>+			label = "rootfs";</div><div class='add'>+			reg = &lt;0x01000000 0x03000000&gt;;</div><div class='add'>+		};</div><div class='add'>+		partition@4000000 {</div><div class='add'>+			label = "media";</div><div class='add'>+			reg = &lt;0x04000000 0x8000000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spicc0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;spicc0_pins_x&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio GPIOX_10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethmac {</div><div class='add'>+	status = "okay";</div><div class='add'>+	phy-handle = &lt;&amp;internal_ephy&gt;;</div><div class='add'>+	phy-mode = "rmii";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi<br/>new file mode 100644<br/>index 000000000000..9d99ed2994df<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-s4.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-s4.dtsi</a></div><div class='hunk'>@@ -0,0 +1,857 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2021 Amlogic, Inc. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/meson-s4-gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/amlogic,s4-pll-clkc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/amlogic,s4-peripherals-clkc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/power/meson-s4-power.h&gt;</div><div class='add'>+#include &lt;dt-bindings/reset/amlogic,meson-s4-reset.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a35";</div><div class='add'>+			reg = &lt;0x0 0x0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@1 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a35";</div><div class='add'>+			reg = &lt;0x0 0x1&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@2 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a35";</div><div class='add'>+			reg = &lt;0x0 0x2&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@3 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a35";</div><div class='add'>+			reg = &lt;0x0 0x3&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-1.0";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	xtal: xtal-clk {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+		clock-output-names = "xtal";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	firmware {</div><div class='add'>+		sm: secure-monitor {</div><div class='add'>+			compatible = "amlogic,meson-gxbb-sm";</div><div class='add'>+</div><div class='add'>+			pwrc: power-controller {</div><div class='add'>+				compatible = "amlogic,meson-s4-pwrc";</div><div class='add'>+				#power-domain-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@fff01000 {</div><div class='add'>+			compatible = "arm,gic-400";</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			#address-cells = &lt;0&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			reg = &lt;0x0 0xfff01000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0xfff02000 0 0x2000&gt;,</div><div class='add'>+			      &lt;0x0 0xfff04000 0 0x2000&gt;,</div><div class='add'>+			      &lt;0x0 0xfff06000 0 0x2000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		apb4: bus@fe000000 {</div><div class='add'>+			compatible = "simple-bus";</div><div class='add'>+			reg = &lt;0x0 0xfe000000 0x0 0x480000&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges = &lt;0x0 0x0 0x0 0xfe000000 0x0 0x480000&gt;;</div><div class='add'>+</div><div class='add'>+			clkc_periphs: clock-controller@0 {</div><div class='add'>+				compatible = "amlogic,s4-peripherals-clkc";</div><div class='add'>+				reg = &lt;0x0 0x0 0x0 0x49c&gt;;</div><div class='add'>+				clocks = &lt;&amp;clkc_pll CLKID_FCLK_DIV2&gt;,</div><div class='add'>+					&lt;&amp;clkc_pll CLKID_FCLK_DIV2P5&gt;,</div><div class='add'>+					&lt;&amp;clkc_pll CLKID_FCLK_DIV3&gt;,</div><div class='add'>+					&lt;&amp;clkc_pll CLKID_FCLK_DIV4&gt;,</div><div class='add'>+					&lt;&amp;clkc_pll CLKID_FCLK_DIV5&gt;,</div><div class='add'>+					&lt;&amp;clkc_pll CLKID_FCLK_DIV7&gt;,</div><div class='add'>+					&lt;&amp;clkc_pll CLKID_HIFI_PLL&gt;,</div><div class='add'>+					&lt;&amp;clkc_pll CLKID_GP0_PLL&gt;,</div><div class='add'>+					&lt;&amp;clkc_pll CLKID_MPLL0&gt;,</div><div class='add'>+					&lt;&amp;clkc_pll CLKID_MPLL1&gt;,</div><div class='add'>+					&lt;&amp;clkc_pll CLKID_MPLL2&gt;,</div><div class='add'>+					&lt;&amp;clkc_pll CLKID_MPLL3&gt;,</div><div class='add'>+					&lt;&amp;clkc_pll CLKID_HDMI_PLL&gt;,</div><div class='add'>+					&lt;&amp;xtal&gt;;</div><div class='add'>+				clock-names = "fclk_div2", "fclk_div2p5", "fclk_div3",</div><div class='add'>+						"fclk_div4", "fclk_div5", "fclk_div7",</div><div class='add'>+						"hifi_pll", "gp0_pll", "mpll0", "mpll1",</div><div class='add'>+						"mpll2", "mpll3", "hdmi_pll", "xtal";</div><div class='add'>+				#clock-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			clkc_pll: clock-controller@8000 {</div><div class='add'>+				compatible = "amlogic,s4-pll-clkc";</div><div class='add'>+				reg = &lt;0x0 0x8000 0x0 0x1e8&gt;;</div><div class='add'>+				clocks = &lt;&amp;xtal&gt;;</div><div class='add'>+				clock-names = "xtal";</div><div class='add'>+				#clock-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			watchdog@2100 {</div><div class='add'>+				compatible = "amlogic,s4-wdt", "amlogic,t7-wdt";</div><div class='add'>+				reg = &lt;0x0 0x2100 0x0 0x10&gt;;</div><div class='add'>+				clocks = &lt;&amp;xtal&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			periphs_pinctrl: pinctrl@4000 {</div><div class='add'>+				compatible = "amlogic,meson-s4-periphs-pinctrl";</div><div class='add'>+				#address-cells = &lt;2&gt;;</div><div class='add'>+				#size-cells = &lt;2&gt;;</div><div class='add'>+				ranges;</div><div class='add'>+</div><div class='add'>+				gpio: bank@4000 {</div><div class='add'>+					reg = &lt;0x0 0x4000 0x0 0x004c&gt;,</div><div class='add'>+					      &lt;0x0 0x40c0 0x0 0x0220&gt;;</div><div class='add'>+					reg-names = "mux", "gpio";</div><div class='add'>+					gpio-controller;</div><div class='add'>+					#gpio-cells = &lt;2&gt;;</div><div class='add'>+					gpio-ranges = &lt;&amp;periphs_pinctrl 0 0 82&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				remote_pins: remote-pin {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "remote_in";</div><div class='add'>+						function = "remote_in";</div><div class='add'>+						bias-disable;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				i2c0_pins1: i2c0-pins1 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "i2c0_sda",</div><div class='add'>+						       "i2c0_scl";</div><div class='add'>+						function = "i2c0";</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='add'>+						bias-disable;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				i2c1_pins1: i2c1-pins1 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "i2c1_sda_c",</div><div class='add'>+						       "i2c1_scl_c";</div><div class='add'>+						function = "i2c1";</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='add'>+						bias-disable;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				i2c1_pins2: i2c1-pins2 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "i2c1_sda_d",</div><div class='add'>+						       "i2c1_scl_d";</div><div class='add'>+						function = "i2c1";</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='add'>+						bias-disable;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				i2c1_pins3: i2c1-pins3 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "i2c1_sda_h",</div><div class='add'>+						       "i2c1_scl_h";</div><div class='add'>+						function = "i2c1";</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='add'>+						bias-disable;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				i2c1_pins4: i2c1-pins4 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "i2c1_sda_x",</div><div class='add'>+						       "i2c1_scl_x";</div><div class='add'>+						function = "i2c1";</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='add'>+						bias-disable;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				i2c2_pins1: i2c2-pins1 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "i2c2_sda_d",</div><div class='add'>+						       "i2c2_scl_d";</div><div class='add'>+						function = "i2c2";</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='add'>+						bias-disable;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				i2c2_pins2: i2c2-pins2 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "i2c2_sda_h8",</div><div class='add'>+						       "i2c2_scl_h9";</div><div class='add'>+						function = "i2c2";</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='add'>+						bias-disable;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				i2c2_pins3: i2c2-pins3 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "i2c2_sda_h0",</div><div class='add'>+						       "i2c2_scl_h1";</div><div class='add'>+						function = "i2c2";</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='add'>+						bias-disable;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				i2c3_pins1: i2c3-pins1 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "i2c3_sda_x",</div><div class='add'>+						       "i2c3_scl_x";</div><div class='add'>+						function = "i2c3";</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='add'>+						bias-disable;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				i2c3_pins2: i2c3-pins2 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "i2c3_sda_z",</div><div class='add'>+						       "i2c3_scl_z";</div><div class='add'>+						function = "i2c3";</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='add'>+						bias-disable;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				i2c4_pins1: i2c4-pins1 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "i2c4_sda_c",</div><div class='add'>+						       "i2c4_scl_c";</div><div class='add'>+						function = "i2c4";</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='add'>+						bias-disable;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				i2c4_pins2: i2c4-pins2 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "i2c4_sda_d",</div><div class='add'>+						       "i2c4_scl_d";</div><div class='add'>+						function = "i2c4";</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='add'>+						bias-disable;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				i2c4_pins3: i2c4-pins3 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "i2c4_sda_z",</div><div class='add'>+						       "i2c4_scl_z";</div><div class='add'>+						function = "i2c4";</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='add'>+						bias-disable;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				nand_pins: nand-pins {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "emmc_nand_d0",</div><div class='add'>+						       "emmc_nand_d1",</div><div class='add'>+						       "emmc_nand_d2",</div><div class='add'>+						       "emmc_nand_d3",</div><div class='add'>+						       "emmc_nand_d4",</div><div class='add'>+						       "emmc_nand_d5",</div><div class='add'>+						       "emmc_nand_d6",</div><div class='add'>+						       "emmc_nand_d7",</div><div class='add'>+						       "nand_ce0",</div><div class='add'>+						       "nand_ale",</div><div class='add'>+						       "nand_cle",</div><div class='add'>+						       "nand_wen_clk",</div><div class='add'>+						       "nand_ren_wr";</div><div class='add'>+						function = "nand";</div><div class='add'>+						input-enable;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_a_pins1: pwm-a-pins1 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_a_d";</div><div class='add'>+						function = "pwm_a";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_a_pins2: pwm-a-pins2 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_a_x";</div><div class='add'>+						function = "pwm_a";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_b_pins1: pwm-b-pins1 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_b_d";</div><div class='add'>+						function = "pwm_b";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_b_pins2: pwm-b-pins2 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_b_x";</div><div class='add'>+						function = "pwm_b";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_c_pins1: pwm-c-pins1 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_c_d";</div><div class='add'>+						function = "pwm_c";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_c_pins2: pwm-c-pins2 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_c_x";</div><div class='add'>+						function = "pwm_c";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_d_pins1: pwm-d-pins1 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_d_d";</div><div class='add'>+						function = "pwm_d";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_d_pins2: pwm-d-pins2 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_d_h";</div><div class='add'>+						function = "pwm_d";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_e_pins1: pwm-e-pins1 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_e_x";</div><div class='add'>+						function = "pwm_e";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_e_pins2: pwm-e-pins2 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_e_z";</div><div class='add'>+						function = "pwm_e";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_f_pins1: pwm-f-pins1 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_f_x";</div><div class='add'>+						function = "pwm_f";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_f_pins2: pwm-f-pins2 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_f_z";</div><div class='add'>+						function = "pwm_f";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_g_pins1: pwm-g-pins1 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_g_d";</div><div class='add'>+						function = "pwm_g";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_g_pins2: pwm-g-pins2 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_g_z";</div><div class='add'>+						function = "pwm_g";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_h_pins: pwm-h-pins {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_h";</div><div class='add'>+						function = "pwm_h";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_i_pins1: pwm-i-pins1 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_i_d";</div><div class='add'>+						function = "pwm_i";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_i_pins2: pwm-i-pins2 {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_i_h";</div><div class='add'>+						function = "pwm_i";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_j_pins: pwm-j-pins {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_j";</div><div class='add'>+						function = "pwm_j";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_a_hiz_pins: pwm-a-hiz-pins {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_a_hiz";</div><div class='add'>+						function = "pwm_a_hiz";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_b_hiz_pins: pwm-b-hiz-pins {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_b_hiz";</div><div class='add'>+						function = "pwm_b_hiz";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_c_hiz_pins: pwm-c-hiz-pins {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_c_hiz";</div><div class='add'>+						function = "pwm_c_hiz";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pwm_g_hiz_pins: pwm-g-hiz-pins {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "pwm_g_hiz";</div><div class='add'>+						function = "pwm_g_hiz";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				sdcard_pins: sdcard-pins {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "sdcard_d0_c",</div><div class='add'>+							 "sdcard_d1_c",</div><div class='add'>+							 "sdcard_d2_c",</div><div class='add'>+							 "sdcard_d3_c",</div><div class='add'>+							 "sdcard_clk_c",</div><div class='add'>+							 "sdcard_cmd_c";</div><div class='add'>+						function = "sdcard";</div><div class='add'>+						bias-pull-up;</div><div class='add'>+						drive-strength-microamp = &lt;4000&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				sdcard_clk_gate_pins: sdcard-clk-gate-pins {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "GPIOC_4";</div><div class='add'>+						function = "gpio_periphs";</div><div class='add'>+						bias-pull-down;</div><div class='add'>+						drive-strength-microamp = &lt;4000&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				emmc_pins: emmc-pins {</div><div class='add'>+					mux-0 {</div><div class='add'>+						groups = "emmc_nand_d0",</div><div class='add'>+							 "emmc_nand_d1",</div><div class='add'>+							 "emmc_nand_d2",</div><div class='add'>+							 "emmc_nand_d3",</div><div class='add'>+							 "emmc_nand_d4",</div><div class='add'>+							 "emmc_nand_d5",</div><div class='add'>+							 "emmc_nand_d6",</div><div class='add'>+							 "emmc_nand_d7",</div><div class='add'>+							 "emmc_cmd";</div><div class='add'>+						function = "emmc";</div><div class='add'>+						bias-pull-up;</div><div class='add'>+						drive-strength-microamp = &lt;4000&gt;;</div><div class='add'>+					};</div><div class='add'>+					mux-1 {</div><div class='add'>+						groups = "emmc_clk";</div><div class='add'>+						function = "emmc";</div><div class='add'>+						bias-pull-up;</div><div class='add'>+						drive-strength-microamp = &lt;4000&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				emmc_ds_pins: emmc-ds-pins {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "emmc_nand_ds";</div><div class='add'>+						function = "emmc";</div><div class='add'>+						bias-pull-down;</div><div class='add'>+						drive-strength-microamp = &lt;4000&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				emmc_clk_gate_pins: emmc-clk-gate-pins {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "GPIOB_8";</div><div class='add'>+						function = "gpio_periphs";</div><div class='add'>+						bias-pull-down;</div><div class='add'>+						drive-strength-microamp = &lt;4000&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				sdio_pins: sdio-pins {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "sdio_d0",</div><div class='add'>+							 "sdio_d1",</div><div class='add'>+							 "sdio_d2",</div><div class='add'>+							 "sdio_d3",</div><div class='add'>+							 "sdio_clk",</div><div class='add'>+							 "sdio_cmd";</div><div class='add'>+						function = "sdio";</div><div class='add'>+						bias-pull-up;</div><div class='add'>+						drive-strength-microamp = &lt;4000&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				sdio_clk_gate_pins: sdio-clk-gate-pins {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "GPIOX_4";</div><div class='add'>+						function = "gpio_periphs";</div><div class='add'>+						bias-pull-down;</div><div class='add'>+						drive-strength-microamp = &lt;4000&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				spicc0_pins_x: spicc0-pins_x {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "spi_a_mosi_x",</div><div class='add'>+						       "spi_a_miso_x",</div><div class='add'>+						       "spi_a_clk_x";</div><div class='add'>+						function = "spi_a";</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				spicc0_pins_h: spicc0-pins-h {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "spi_a_mosi_h",</div><div class='add'>+						       "spi_a_miso_h",</div><div class='add'>+						       "spi_a_clk_h";</div><div class='add'>+						function = "spi_a";</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				spicc0_pins_z: spicc0-pins-z {</div><div class='add'>+					mux {</div><div class='add'>+						groups = "spi_a_mosi_z",</div><div class='add'>+						       "spi_a_miso_z",</div><div class='add'>+						       "spi_a_clk_z";</div><div class='add'>+						function = "spi_a";</div><div class='add'>+						drive-strength-microamp = &lt;3000&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gpio_intc: interrupt-controller@4080 {</div><div class='add'>+				compatible = "amlogic,meson-s4-gpio-intc",</div><div class='add'>+					     "amlogic,meson-gpio-intc";</div><div class='add'>+				reg = &lt;0x0 0x4080 0x0 0x20&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;2&gt;;</div><div class='add'>+				amlogic,channel-interrupts =</div><div class='add'>+					&lt;10 11 12 13 14 15 16 17 18 19 20 21&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			eth_phy: mdio-multiplexer@28000 {</div><div class='add'>+				compatible = "amlogic,g12a-mdio-mux";</div><div class='add'>+				reg = &lt;0x0 0x28000 0x0 0xa4&gt;;</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;clkc_periphs CLKID_ETHPHY&gt;,</div><div class='add'>+					 &lt;&amp;xtal&gt;,</div><div class='add'>+					 &lt;&amp;clkc_pll CLKID_MPLL_50M&gt;;</div><div class='add'>+				clock-names = "pclk", "clkin0", "clkin1";</div><div class='add'>+				mdio-parent-bus = &lt;&amp;mdio0&gt;;</div><div class='add'>+</div><div class='add'>+				ext_mdio: mdio@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				int_mdio: mdio@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					internal_ephy: ethernet-phy@8 {</div><div class='add'>+						compatible = "ethernet-phy-id0180.3301",</div><div class='add'>+							     "ethernet-phy-ieee802.3-c22";</div><div class='add'>+						interrupts = &lt;GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+						reg = &lt;8&gt;;</div><div class='add'>+						max-speed = &lt;100&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			clk_msr: clock-measure@48000 {</div><div class='add'>+				compatible = "amlogic,s4-clk-measure";</div><div class='add'>+				reg = &lt;0x0 0x48000 0x0 0x1c&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spicc0: spi@50000 {</div><div class='add'>+				compatible = "amlogic,meson-g12a-spicc";</div><div class='add'>+				reg = &lt;0x0 0x50000 0x0 0x44&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clkc_periphs CLKID_SPICC0&gt;,</div><div class='add'>+					 &lt;&amp;clkc_periphs CLKID_SPICC0_EN&gt;;</div><div class='add'>+				clock-names = "core", "pclk";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pwm_ab: pwm@58000 {</div><div class='add'>+				compatible = "amlogic,meson-s4-pwm";</div><div class='add'>+				reg = &lt;0x0 0x58000 0x0 0x24&gt;;</div><div class='add'>+				clocks = &lt;&amp;clkc_periphs CLKID_PWM_A&gt;,</div><div class='add'>+					 &lt;&amp;clkc_periphs CLKID_PWM_B&gt;;</div><div class='add'>+				#pwm-cells = &lt;3&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pwm_cd: pwm@5a000 {</div><div class='add'>+				compatible = "amlogic,meson-s4-pwm";</div><div class='add'>+				reg = &lt;0x0 0x5a000 0x0 0x24&gt;;</div><div class='add'>+				clocks = &lt;&amp;clkc_periphs CLKID_PWM_C&gt;,</div><div class='add'>+					 &lt;&amp;clkc_periphs CLKID_PWM_D&gt;;</div><div class='add'>+				#pwm-cells = &lt;3&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pwm_ef: pwm@5c000 {</div><div class='add'>+				compatible = "amlogic,meson-s4-pwm";</div><div class='add'>+				reg = &lt;0x0 0x5c000 0x0 0x24&gt;;</div><div class='add'>+				clocks = &lt;&amp;clkc_periphs CLKID_PWM_E&gt;,</div><div class='add'>+					 &lt;&amp;clkc_periphs CLKID_PWM_F&gt;;</div><div class='add'>+				#pwm-cells = &lt;3&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pwm_gh: pwm@5e000 {</div><div class='add'>+				compatible = "amlogic,meson-s4-pwm";</div><div class='add'>+				reg = &lt;0x0 0x5e000 0x0 0x24&gt;;</div><div class='add'>+				clocks = &lt;&amp;clkc_periphs CLKID_PWM_G&gt;,</div><div class='add'>+					 &lt;&amp;clkc_periphs CLKID_PWM_H&gt;;</div><div class='add'>+				#pwm-cells = &lt;3&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pwm_ij: pwm@60000 {</div><div class='add'>+				compatible = "amlogic,meson-s4-pwm";</div><div class='add'>+				reg = &lt;0x0 0x60000 0x0 0x24&gt;;</div><div class='add'>+				clocks = &lt;&amp;clkc_periphs CLKID_PWM_I&gt;,</div><div class='add'>+					 &lt;&amp;clkc_periphs CLKID_PWM_J&gt;;</div><div class='add'>+				#pwm-cells = &lt;3&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c0: i2c@66000 {</div><div class='add'>+				compatible = "amlogic,meson-axg-i2c";</div><div class='add'>+				reg = &lt;0x0 0x66000 0x0 0x20&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 160 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				clocks = &lt;&amp;clkc_periphs CLKID_I2C_M_A&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c1: i2c@68000 {</div><div class='add'>+				compatible = "amlogic,meson-axg-i2c";</div><div class='add'>+				reg = &lt;0x0 0x68000 0x0 0x20&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 161 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				clocks = &lt;&amp;clkc_periphs CLKID_I2C_M_B&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c2: i2c@6a000 {</div><div class='add'>+				compatible = "amlogic,meson-axg-i2c";</div><div class='add'>+				reg = &lt;0x0 0x6a000 0x0 0x20&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 162 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				clocks = &lt;&amp;clkc_periphs CLKID_I2C_M_C&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c3: i2c@6c000 {</div><div class='add'>+				compatible = "amlogic,meson-axg-i2c";</div><div class='add'>+				reg = &lt;0x0 0x6c000 0x0 0x20&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 163 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				clocks = &lt;&amp;clkc_periphs CLKID_I2C_M_D&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c4: i2c@6e000 {</div><div class='add'>+				compatible = "amlogic,meson-axg-i2c";</div><div class='add'>+				reg = &lt;0x0 0x6e000 0x0 0x20&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 164 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				clocks = &lt;&amp;clkc_periphs CLKID_I2C_M_E&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			nand: nand-controller@8c800 {</div><div class='add'>+				compatible = "amlogic,meson-axg-nfc";</div><div class='add'>+				reg = &lt;0x0 0x8c800 0x0 0x100&gt;, &lt;0x0 0x8c000 0x0 0x4&gt;;</div><div class='add'>+				reg-names = "nfc", "emmc";</div><div class='add'>+				interrupts = &lt;GIC_SPI 175 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				clocks = &lt;&amp;clkc_periphs CLKID_SD_EMMC_C&gt;,</div><div class='add'>+					&lt;&amp;clkc_pll CLKID_FCLK_DIV2&gt;;</div><div class='add'>+				clock-names = "core", "device";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart_b: serial@7a000 {</div><div class='add'>+				compatible = "amlogic,meson-s4-uart",</div><div class='add'>+					     "amlogic,meson-ao-uart";</div><div class='add'>+				reg = &lt;0x0 0x7a000 0x0 0x18&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 169 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				clocks = &lt;&amp;xtal&gt;, &lt;&amp;clkc_periphs CLKID_UART_B&gt;, &lt;&amp;xtal&gt;;</div><div class='add'>+				clock-names = "xtal", "pclk", "baud";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reset: reset-controller@2000 {</div><div class='add'>+				compatible = "amlogic,meson-s4-reset";</div><div class='add'>+				reg = &lt;0x0 0x2000 0x0 0x98&gt;;</div><div class='add'>+				#reset-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sec_ao: ao-secure@10220 {</div><div class='add'>+				compatible = "amlogic,s4-ao-secure",</div><div class='add'>+					     "amlogic,meson-gx-ao-secure",</div><div class='add'>+					     "syscon";</div><div class='add'>+				reg = &lt;0x0 0x10220 0x0 0x140&gt;;</div><div class='add'>+				amlogic,has-chip-id;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ir: ir@84040 {</div><div class='add'>+				compatible = "amlogic,meson-s4-ir";</div><div class='add'>+				reg = &lt;0x0 0x84040 0x0 0x30&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 22 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			hwrng: rng@440788 {</div><div class='add'>+				compatible = "amlogic,meson-s4-rng";</div><div class='add'>+				reg = &lt;0x0 0x440788 0x0 0x0c&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ethmac: ethernet@fdc00000 {</div><div class='add'>+			compatible = "amlogic,meson-axg-dwmac",</div><div class='add'>+				     "snps,dwmac-3.70a",</div><div class='add'>+				     "snps,dwmac";</div><div class='add'>+			reg = &lt;0x0 0xfdc00000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0xfe024000 0x0 0x8&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "macirq";</div><div class='add'>+			power-domains = &lt;&amp;pwrc PWRC_S4_ETH_ID&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkc_periphs CLKID_ETH&gt;,</div><div class='add'>+				 &lt;&amp;clkc_pll CLKID_FCLK_DIV2&gt;,</div><div class='add'>+				 &lt;&amp;clkc_pll CLKID_MPLL2&gt;;</div><div class='add'>+			clock-names = "stmmaceth", "clkin0", "clkin1";</div><div class='add'>+			rx-fifo-depth = &lt;4096&gt;;</div><div class='add'>+			tx-fifo-depth = &lt;2048&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			mdio0: mdio {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				compatible = "snps,dwmac-mdio";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sdio: mmc@fe088000 {</div><div class='add'>+			compatible = "amlogic,meson-axg-mmc";</div><div class='add'>+			reg = &lt;0x0 0xfe088000 0x0 0x800&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkc_periphs CLKID_SDEMMC_A&gt;,</div><div class='add'>+				 &lt;&amp;xtal&gt;,</div><div class='add'>+				 &lt;&amp;clkc_pll CLKID_FCLK_DIV2&gt;;</div><div class='add'>+			clock-names = "core", "clkin0", "clkin1";</div><div class='add'>+			resets = &lt;&amp;reset RESET_SD_EMMC_A&gt;;</div><div class='add'>+			cap-sdio-irq;</div><div class='add'>+			keep-power-in-suspend;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sd: mmc@fe08a000 {</div><div class='add'>+			compatible = "amlogic,meson-axg-mmc";</div><div class='add'>+			reg = &lt;0x0 0xfe08a000 0x0 0x800&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 177 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkc_periphs CLKID_SDEMMC_B&gt;,</div><div class='add'>+				 &lt;&amp;clkc_periphs CLKID_SD_EMMC_B&gt;,</div><div class='add'>+				 &lt;&amp;clkc_pll CLKID_FCLK_DIV2&gt;;</div><div class='add'>+			clock-names = "core", "clkin0", "clkin1";</div><div class='add'>+			resets = &lt;&amp;reset RESET_SD_EMMC_B&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		emmc: mmc@fe08c000 {</div><div class='add'>+			compatible = "amlogic,meson-axg-mmc";</div><div class='add'>+			reg = &lt;0x0 0xfe08c000 0x0 0x800&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 178 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkc_periphs CLKID_NAND&gt;,</div><div class='add'>+				 &lt;&amp;xtal&gt;,</div><div class='add'>+				 &lt;&amp;clkc_pll CLKID_FCLK_DIV2&gt;;</div><div class='add'>+			clock-names = "core", "clkin0", "clkin1";</div><div class='add'>+			resets = &lt;&amp;reset RESET_NAND_EMMC&gt;;</div><div class='add'>+			no-sdio;</div><div class='add'>+			no-sd;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air-gbit.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air-gbit.dts<br/>new file mode 100644<br/>index 000000000000..3c43d3490e14<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air-gbit.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air-gbit.dts</a></div><div class='hunk'>@@ -0,0 +1,132 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2019 BayLibre SAS. All rights reserved.</div><div class='add'>+ * Copyright (c) 2020 Christian Hewitt &lt;christianshewitt@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "meson-sm1-ac2xx.dtsi"</div><div class='add'>+#include &lt;dt-bindings/sound/meson-g12a-tohdmitx.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "cyx,a95xf3-air-gbit", "amlogic,sm1";</div><div class='add'>+	model = "Shenzhen CYX Industrial Co., Ltd A95XF3-AIR";</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "amlogic,axg-sound-card";</div><div class='add'>+		model = "A95XF3-AIR";</div><div class='add'>+		audio-aux-devs = &lt;&amp;tdmout_b&gt;;</div><div class='add'>+		audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",</div><div class='add'>+				"TDMOUT_B IN 1", "FRDDR_B OUT 1",</div><div class='add'>+				"TDMOUT_B IN 2", "FRDDR_C OUT 1",</div><div class='add'>+				"TDM_B Playback", "TDMOUT_B OUT";</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;294912000&gt;,</div><div class='add'>+				       &lt;270950400&gt;,</div><div class='add'>+				       &lt;393216000&gt;;</div><div class='add'>+</div><div class='add'>+		dai-link-0 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_a&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-1 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_b&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-2 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_c&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* 8ch hdmi interface */</div><div class='add'>+		dai-link-3 {</div><div class='add'>+			sound-dai = &lt;&amp;tdmif_b&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			dai-tdm-slot-tx-mask-0 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-1 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-2 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-3 = &lt;1 1&gt;;</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_IN_B&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* hdmi glue */</div><div class='add'>+		dai-link-4 {</div><div class='add'>+			sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;arb {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;clkc_audio {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethmac {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pinctrl-0 = &lt;&amp;eth_pins&gt;, &lt;&amp;eth_rgmii_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	phy-mode = "rgmii-txid";</div><div class='add'>+	phy-handle = &lt;&amp;external_phy&gt;;</div><div class='add'>+</div><div class='add'>+	rx-internal-delay-ps = &lt;800&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ext_mdio {</div><div class='add'>+	external_phy: ethernet-phy@0 {</div><div class='add'>+		/* Realtek RTL8211F (0x001cc916) */</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		max-speed = &lt;1000&gt;;</div><div class='add'>+</div><div class='add'>+		reset-assert-us = &lt;10000&gt;;</div><div class='add'>+		reset-deassert-us = &lt;80000&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio_intc&gt;;</div><div class='add'>+		/* MAC_INTR on GPIOZ_14 */</div><div class='add'>+		interrupts = &lt;IRQID_GPIOZ_14 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmif_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmout_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tohdmitx {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air.dts<br/>new file mode 100644<br/>index 000000000000..445c1671ede7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air.dts</a></div><div class='hunk'>@@ -0,0 +1,111 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2019 BayLibre SAS. All rights reserved.</div><div class='add'>+ * Copyright (c) 2020 Christian Hewitt &lt;christianshewitt@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "meson-sm1-ac2xx.dtsi"</div><div class='add'>+#include &lt;dt-bindings/sound/meson-g12a-tohdmitx.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "cyx,a95xf3-air", "amlogic,sm1";</div><div class='add'>+	model = "Shenzhen CYX Industrial Co., Ltd A95XF3-AIR";</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "amlogic,axg-sound-card";</div><div class='add'>+		model = "A95XF3-AIR";</div><div class='add'>+		audio-aux-devs = &lt;&amp;tdmout_b&gt;;</div><div class='add'>+		audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",</div><div class='add'>+				"TDMOUT_B IN 1", "FRDDR_B OUT 1",</div><div class='add'>+				"TDMOUT_B IN 2", "FRDDR_C OUT 1",</div><div class='add'>+				"TDM_B Playback", "TDMOUT_B OUT";</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;294912000&gt;,</div><div class='add'>+				       &lt;270950400&gt;,</div><div class='add'>+				       &lt;393216000&gt;;</div><div class='add'>+</div><div class='add'>+		dai-link-0 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_a&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-1 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_b&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-2 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_c&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* 8ch hdmi interface */</div><div class='add'>+		dai-link-3 {</div><div class='add'>+			sound-dai = &lt;&amp;tdmif_b&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			dai-tdm-slot-tx-mask-0 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-1 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-2 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-3 = &lt;1 1&gt;;</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_IN_B&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* hdmi glue */</div><div class='add'>+		dai-link-4 {</div><div class='add'>+			sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;arb {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;clkc_audio {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethmac {</div><div class='add'>+	status = "okay";</div><div class='add'>+	phy-handle = &lt;&amp;internal_ephy&gt;;</div><div class='add'>+	phy-mode = "rmii";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmif_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmout_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tohdmitx {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi<br/>new file mode 100644<br/>index 000000000000..9be3084b090d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi</a></div><div class='hunk'>@@ -0,0 +1,290 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2019 BayLibre SAS. All rights reserved.</div><div class='add'>+ * Copyright (c) 2020 Christian Hewitt &lt;christianshewitt@gmail.com&gt;</div><div class='add'>+ *</div><div class='add'>+ * AC200/AC202 = S905D3</div><div class='add'>+ * AC213/AC214 = S905X3</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "meson-sm1.dtsi"</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/meson-g12a-gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart_AO;</div><div class='add'>+		ethernet0 = &amp;ethmac;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	emmc_pwrseq: emmc-pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-emmc";</div><div class='add'>+		reset-gpios = &lt;&amp;gpio BOOT_12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cvbs-connector {</div><div class='add'>+		compatible = "composite-video-connector";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			cvbs_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;cvbs_vdac_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdmi-connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		type = "a";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			hdmi_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_tx_tmds_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x0 0x0 0x40000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ao_5v: regulator-ao-5v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "AO_5V";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;dc_in&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dc_in: regulator-dc-in {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "DC_IN";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	emmc_1v8: regulator-emmc-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "EMMC_1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddao_3v3: regulator-vddao-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDAO_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;dc_in&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddcpu: regulator-vddcpu {</div><div class='add'>+		compatible = "pwm-regulator";</div><div class='add'>+</div><div class='add'>+		regulator-name = "VDDCPU";</div><div class='add'>+		regulator-min-microvolt = &lt;690000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1050000&gt;;</div><div class='add'>+</div><div class='add'>+		vin-supply = &lt;&amp;dc_in&gt;;</div><div class='add'>+</div><div class='add'>+		pwms = &lt;&amp;pwm_AO_cd 1 1500 0&gt;;</div><div class='add'>+		pwm-dutycycle-range = &lt;100 0&gt;;</div><div class='add'>+</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddio_ao1v8: regulator-vddio-ao1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDIO_AO1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdio_pwrseq: sdio-pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-simple";</div><div class='add'>+		reset-gpios = &lt;&amp;gpio GPIOX_6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		clocks = &lt;&amp;wifi32k&gt;;</div><div class='add'>+		clock-names = "ext_clock";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wifi32k: wifi32k {</div><div class='add'>+		compatible = "pwm-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;32768&gt;;</div><div class='add'>+		pwms = &lt;&amp;pwm_ef 0 30518 0&gt;; /* PWM_E at 32.768KHz */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cec_AO {</div><div class='add'>+	pinctrl-0 = &lt;&amp;cec_ao_a_h_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "disabled";</div><div class='add'>+	hdmi-phandle = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cecb_AO {</div><div class='add'>+	pinctrl-0 = &lt;&amp;cec_ao_b_h_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+	hdmi-phandle = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPU_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu1 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPU1_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu2 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPU2_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu3 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPU3_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cvbs_vdac_port {</div><div class='add'>+	cvbs_vdac_out: endpoint {</div><div class='add'>+		remote-endpoint = &lt;&amp;cvbs_connector_in&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;hdmitx_hpd_pins&gt;, &lt;&amp;hdmitx_ddc_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx_tmds_port {</div><div class='add'>+	hdmi_tx_tmds_out: endpoint {</div><div class='add'>+		remote-endpoint = &lt;&amp;hdmi_connector_in&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ir {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;remote_input_ao_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm_AO_ab {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm_ao_a_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm_AO_cd {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm_ao_d_e_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm_ef {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm_e_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;saradc {</div><div class='add'>+	status = "okay";</div><div class='add'>+	vref-supply = &lt;&amp;vddio_ao1v8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SDIO */</div><div class='add'>+&amp;sd_emmc_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdio_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;sdio_clk_gate_pins&gt;;</div><div class='add'>+	pinctrl-names = "default", "clk-gate";</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	sd-uhs-sdr104;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+</div><div class='add'>+	non-removable;</div><div class='add'>+	disable-wp;</div><div class='add'>+</div><div class='add'>+	/* WiFi firmware requires power to be kept while in suspend */</div><div class='add'>+	keep-power-in-suspend;</div><div class='add'>+</div><div class='add'>+	mmc-pwrseq = &lt;&amp;sdio_pwrseq&gt;;</div><div class='add'>+</div><div class='add'>+	vmmc-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;vddio_ao1v8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SD Card */</div><div class='add'>+&amp;sd_emmc_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdcard_c_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;sdcard_clk_gate_c_pins&gt;;</div><div class='add'>+	pinctrl-names = "default", "clk-gate";</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	/* CRC errors are observed at 50MHz */</div><div class='add'>+	max-frequency = &lt;35000000&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+</div><div class='add'>+	cd-gpios = &lt;&amp;gpio GPIOC_6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* eMMC */</div><div class='add'>+&amp;sd_emmc_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;emmc_ctrl_pins&gt;, &lt;&amp;emmc_data_8b_pins&gt;, &lt;&amp;emmc_ds_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;emmc_clk_gate_pins&gt;;</div><div class='add'>+	pinctrl-names = "default", "clk-gate";</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	cap-mmc-highspeed;</div><div class='add'>+	mmc-ddr-1_8v;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	disable-wp;</div><div class='add'>+</div><div class='add'>+	mmc-pwrseq = &lt;&amp;emmc_pwrseq&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;emmc_1v8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart_AO {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart_ao_a_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb {</div><div class='add'>+	status = "okay";</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m2-pro.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m2-pro.dts<br/>new file mode 100644<br/>index 000000000000..eeaff22edade<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m2-pro.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m2-pro.dts</a></div><div class='hunk'>@@ -0,0 +1,101 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2021 BayLibre SAS</div><div class='add'>+ * Author: Neil Armstrong &lt;narmstrong@baylibre.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "meson-sm1-bananapi.dtsi"</div><div class='add'>+#include &lt;dt-bindings/sound/meson-g12a-tohdmitx.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "bananapi,bpi-m2-pro", "amlogic,sm1";</div><div class='add'>+	model = "Banana Pi BPI-M2-PRO";</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "amlogic,axg-sound-card";</div><div class='add'>+		model = "BPI-M2-PRO";</div><div class='add'>+		audio-aux-devs = &lt;&amp;tdmout_b&gt;;</div><div class='add'>+		audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",</div><div class='add'>+				"TDMOUT_B IN 1", "FRDDR_B OUT 1",</div><div class='add'>+				"TDMOUT_B IN 2", "FRDDR_C OUT 1",</div><div class='add'>+				"TDM_B Playback", "TDMOUT_B OUT";</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;294912000&gt;,</div><div class='add'>+				       &lt;270950400&gt;,</div><div class='add'>+				       &lt;393216000&gt;;</div><div class='add'>+</div><div class='add'>+		dai-link-0 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_a&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-1 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_b&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-2 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_c&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* 8ch hdmi interface */</div><div class='add'>+		dai-link-3 {</div><div class='add'>+			sound-dai = &lt;&amp;tdmif_b&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			dai-tdm-slot-tx-mask-0 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-1 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-2 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-3 = &lt;1 1&gt;;</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_IN_B&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* hdmi glue */</div><div class='add'>+		dai-link-4 {</div><div class='add'>+			sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;clkc_audio {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmif_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmout_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tohdmitx {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m5.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m5.dts<br/>new file mode 100644<br/>index 000000000000..697855fec476<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m5.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m5.dts</a></div><div class='hunk'>@@ -0,0 +1,225 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2021 BayLibre SAS</div><div class='add'>+ * Author: Neil Armstrong &lt;narmstrong@baylibre.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "meson-sm1-bananapi.dtsi"</div><div class='add'>+#include &lt;dt-bindings/sound/meson-g12a-toacodec.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/meson-g12a-tohdmitx.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "bananapi,bpi-m5", "amlogic,sm1";</div><div class='add'>+	model = "Banana Pi BPI-M5";</div><div class='add'>+</div><div class='add'>+	/* TOFIX: handle CVBS_DET on SARADC channel 0 */</div><div class='add'>+	cvbs-connector {</div><div class='add'>+		compatible = "composite-video-connector";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			cvbs_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;cvbs_vdac_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "amlogic,axg-sound-card";</div><div class='add'>+		model = "BPI-M5";</div><div class='add'>+		audio-widgets = "Line", "Lineout";</div><div class='add'>+		audio-aux-devs = &lt;&amp;tdmout_b&gt;, &lt;&amp;tdmout_c&gt;,</div><div class='add'>+				 &lt;&amp;tdmin_a&gt;, &lt;&amp;tdmin_b&gt;, &lt;&amp;tdmin_c&gt;;</div><div class='add'>+		audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",</div><div class='add'>+				"TDMOUT_B IN 1", "FRDDR_B OUT 1",</div><div class='add'>+				"TDMOUT_B IN 2", "FRDDR_C OUT 1",</div><div class='add'>+				"TDM_B Playback", "TDMOUT_B OUT",</div><div class='add'>+				"TDMOUT_C IN 0", "FRDDR_A OUT 2",</div><div class='add'>+				"TDMOUT_C IN 1", "FRDDR_B OUT 2",</div><div class='add'>+				"TDMOUT_C IN 2", "FRDDR_C OUT 2",</div><div class='add'>+				"TDM_C Playback", "TDMOUT_C OUT",</div><div class='add'>+				"TDMIN_A IN 4", "TDM_B Loopback",</div><div class='add'>+				"TDMIN_B IN 4", "TDM_B Loopback",</div><div class='add'>+				"TDMIN_C IN 4", "TDM_B Loopback",</div><div class='add'>+				"TDMIN_A IN 5", "TDM_C Loopback",</div><div class='add'>+				"TDMIN_B IN 5", "TDM_C Loopback",</div><div class='add'>+				"TDMIN_C IN 5", "TDM_C Loopback",</div><div class='add'>+				"TODDR_A IN 0", "TDMIN_A OUT",</div><div class='add'>+				"TODDR_B IN 0", "TDMIN_A OUT",</div><div class='add'>+				"TODDR_C IN 0", "TDMIN_A OUT",</div><div class='add'>+				"TODDR_A IN 1", "TDMIN_B OUT",</div><div class='add'>+				"TODDR_B IN 1", "TDMIN_B OUT",</div><div class='add'>+				"TODDR_C IN 1", "TDMIN_B OUT",</div><div class='add'>+				"TODDR_A IN 2", "TDMIN_C OUT",</div><div class='add'>+				"TODDR_B IN 2", "TDMIN_C OUT",</div><div class='add'>+				"TODDR_C IN 2", "TDMIN_C OUT",</div><div class='add'>+				"Lineout", "ACODEC LOLP",</div><div class='add'>+				"Lineout", "ACODEC LORP";</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;294912000&gt;,</div><div class='add'>+				       &lt;270950400&gt;,</div><div class='add'>+				       &lt;393216000&gt;;</div><div class='add'>+</div><div class='add'>+		dai-link-0 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_a&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-1 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_b&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-2 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_c&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-3 {</div><div class='add'>+			sound-dai = &lt;&amp;toddr_a&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-4 {</div><div class='add'>+			sound-dai = &lt;&amp;toddr_b&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-5 {</div><div class='add'>+			sound-dai = &lt;&amp;toddr_c&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* 8ch hdmi interface */</div><div class='add'>+		dai-link-6 {</div><div class='add'>+			sound-dai = &lt;&amp;tdmif_b&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			dai-tdm-slot-tx-mask-0 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-1 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-2 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-3 = &lt;1 1&gt;;</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_IN_B&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			codec-1 {</div><div class='add'>+				sound-dai = &lt;&amp;toacodec TOACODEC_IN_B&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* i2s jack output interface */</div><div class='add'>+		dai-link-7 {</div><div class='add'>+			sound-dai = &lt;&amp;tdmif_c&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			dai-tdm-slot-tx-mask-0 = &lt;1 1&gt;;</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec-0 {</div><div class='add'>+				sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_IN_C&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			codec-1 {</div><div class='add'>+				sound-dai = &lt;&amp;toacodec TOACODEC_IN_C&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* hdmi glue */</div><div class='add'>+		dai-link-8 {</div><div class='add'>+			sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* acodec glue */</div><div class='add'>+		dai-link-9 {</div><div class='add'>+			sound-dai = &lt;&amp;toacodec TOACODEC_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;acodec&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;acodec {</div><div class='add'>+	AVDD-supply = &lt;&amp;vddao_1v8&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+&amp;clkc_audio {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cvbs_vdac_port {</div><div class='add'>+	cvbs_vdac_out: endpoint {</div><div class='add'>+		remote-endpoint = &lt;&amp;cvbs_connector_in&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmif_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmif_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmin_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmin_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmin_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmout_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmout_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;toacodec {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tohdmitx {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;toddr_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;toddr_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;toddr_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi<br/>new file mode 100644<br/>index 000000000000..5e07f0f9538e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi</a></div><div class='hunk'>@@ -0,0 +1,428 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2021 BayLibre SAS</div><div class='add'>+ * Author: Neil Armstrong &lt;narmstrong@baylibre.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "meson-sm1.dtsi"</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/linux-event-codes.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/meson-g12a-gpio.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	adc-keys {</div><div class='add'>+		compatible = "adc-keys";</div><div class='add'>+		io-channels = &lt;&amp;saradc 2&gt;;</div><div class='add'>+		io-channel-names = "buttons";</div><div class='add'>+		keyup-threshold-microvolt = &lt;1800000&gt;;</div><div class='add'>+</div><div class='add'>+		button-sw3 {</div><div class='add'>+			label = "SW3";</div><div class='add'>+			linux,code = &lt;BTN_3&gt;;</div><div class='add'>+			press-threshold-microvolt = &lt;1700000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart_AO;</div><div class='add'>+		ethernet0 = &amp;ethmac;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	emmc_pwrseq: emmc-pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-emmc";</div><div class='add'>+		reset-gpios = &lt;&amp;gpio BOOT_12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		key {</div><div class='add'>+			label = "SW1";</div><div class='add'>+			linux,code = &lt;BTN_1&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio_intc&gt;;</div><div class='add'>+			interrupts = &lt;IRQID_GPIOAO_3 IRQ_TYPE_EDGE_BOTH&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdmi-connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		type = "a";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			hdmi_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_tx_tmds_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-green {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			gpios = &lt;&amp;gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-blue {</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			gpios = &lt;&amp;gpio_ao GPIOAO_11 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x0 0x0 0x40000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	emmc_1v8: regulator-emmc-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "EMMC_1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dc_in: regulator-dc-in {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "DC_IN";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddio_c: regulator-vddio-c {</div><div class='add'>+		compatible = "regulator-gpio";</div><div class='add'>+		regulator-name = "VDDIO_C";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+</div><div class='add'>+		enable-gpios = &lt;&amp;gpio_ao GPIOE_2 GPIO_OPEN_DRAIN&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+</div><div class='add'>+		gpios = &lt;&amp;gpio_ao GPIOAO_6 GPIO_OPEN_DRAIN&gt;;</div><div class='add'>+		gpios-states = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		states = &lt;1800000 0&gt;,</div><div class='add'>+			 &lt;3300000 1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	tflash_vdd: regulator-tflash-vdd {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "TFLASH_VDD";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;dc_in&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio GPIOH_8 GPIO_OPEN_DRAIN&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddao_1v8: regulator-vddao-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDAO_1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddao_3v3: regulator-vddao-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDAO_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;dc_in&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddcpu: regulator-vddcpu {</div><div class='add'>+		/*</div><div class='add'>+		 * SY8120B1ABC DC/DC Regulator.</div><div class='add'>+		 */</div><div class='add'>+		compatible = "pwm-regulator";</div><div class='add'>+</div><div class='add'>+		regulator-name = "VDDCPU";</div><div class='add'>+		regulator-min-microvolt = &lt;690000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1050000&gt;;</div><div class='add'>+</div><div class='add'>+		pwm-supply = &lt;&amp;dc_in&gt;;</div><div class='add'>+</div><div class='add'>+		pwms = &lt;&amp;pwm_AO_cd 1 1250 0&gt;;</div><div class='add'>+		pwm-dutycycle-range = &lt;100 0&gt;;</div><div class='add'>+</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USB Hub Power Enable */</div><div class='add'>+	vl_pwr_en: regulator-vl-pwr-en {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VL_PWR_EN";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;dc_in&gt;;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;gpio GPIOH_6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;arb {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPU_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu1 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPU1_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu2 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPU2_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu3 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPU3_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ext_mdio {</div><div class='add'>+	external_phy: ethernet-phy@0 {</div><div class='add'>+		/* Realtek RTL8211F (0x001cc916) */</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		max-speed = &lt;1000&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio_intc&gt;;</div><div class='add'>+		/* MAC_INTR on GPIOZ_14 */</div><div class='add'>+		interrupts = &lt;IRQID_GPIOZ_14 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethmac {</div><div class='add'>+	pinctrl-0 = &lt;&amp;eth_pins&gt;, &lt;&amp;eth_rgmii_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+	phy-mode = "rgmii-txid";</div><div class='add'>+	phy-handle = &lt;&amp;external_phy&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		/* GPIOZ */</div><div class='add'>+		"ETH_MDIO", /* GPIOZ_0 */</div><div class='add'>+		"ETH_MDC", /* GPIOZ_1 */</div><div class='add'>+		"ETH_RXCLK", /* GPIOZ_2 */</div><div class='add'>+		"ETH_RX_DV", /* GPIOZ_3 */</div><div class='add'>+		"ETH_RXD0", /* GPIOZ_4 */</div><div class='add'>+		"ETH_RXD1", /* GPIOZ_5 */</div><div class='add'>+		"ETH_RXD2", /* GPIOZ_6 */</div><div class='add'>+		"ETH_RXD3", /* GPIOZ_7 */</div><div class='add'>+		"ETH_TXCLK", /* GPIOZ_8 */</div><div class='add'>+		"ETH_TXEN", /* GPIOZ_9 */</div><div class='add'>+		"ETH_TXD0", /* GPIOZ_10 */</div><div class='add'>+		"ETH_TXD1", /* GPIOZ_11 */</div><div class='add'>+		"ETH_TXD2", /* GPIOZ_12 */</div><div class='add'>+		"ETH_TXD3", /* GPIOZ_13 */</div><div class='add'>+		"ETH_INTR", /* GPIOZ_14 */</div><div class='add'>+		"ETH_NRST", /* GPIOZ_15 */</div><div class='add'>+		/* GPIOH */</div><div class='add'>+		"HDMI_SDA", /* GPIOH_0 */</div><div class='add'>+		"HDMI_SCL", /* GPIOH_1 */</div><div class='add'>+		"HDMI_HPD", /* GPIOH_2 */</div><div class='add'>+		"HDMI_CEC", /* GPIOH_3 */</div><div class='add'>+		"VL-RST_N", /* GPIOH_4 */</div><div class='add'>+		"CON1-P36", /* GPIOH_5 */</div><div class='add'>+		"VL-PWREN", /* GPIOH_6 */</div><div class='add'>+		"WiFi_3V3_1V8", /* GPIOH_7 */</div><div class='add'>+		"TFLASH_VDD_EN", /* GPIOH_8 */</div><div class='add'>+		/* BOOT */</div><div class='add'>+		"eMMC_D0", /* BOOT_0 */</div><div class='add'>+		"eMMC_D1", /* BOOT_1 */</div><div class='add'>+		"eMMC_D2", /* BOOT_2 */</div><div class='add'>+		"eMMC_D3", /* BOOT_3 */</div><div class='add'>+		"eMMC_D4", /* BOOT_4 */</div><div class='add'>+		"eMMC_D5", /* BOOT_5 */</div><div class='add'>+		"eMMC_D6", /* BOOT_6 */</div><div class='add'>+		"eMMC_D7", /* BOOT_7 */</div><div class='add'>+		"eMMC_CLK", /* BOOT_8 */</div><div class='add'>+		"",</div><div class='add'>+		"eMMC_CMD", /* BOOT_10 */</div><div class='add'>+		"",</div><div class='add'>+		"eMMC_RST#", /* BOOT_12 */</div><div class='add'>+		"eMMC_DS", /* BOOT_13 */</div><div class='add'>+		"", "",</div><div class='add'>+		/* GPIOC */</div><div class='add'>+		"SD_D0_B", /* GPIOC_0 */</div><div class='add'>+		"SD_D1_B", /* GPIOC_1 */</div><div class='add'>+		"SD_D2_B", /* GPIOC_2 */</div><div class='add'>+		"SD_D3_B", /* GPIOC_3 */</div><div class='add'>+		"SD_CLK_B", /* GPIOC_4 */</div><div class='add'>+		"SD_CMD_B", /* GPIOC_5 */</div><div class='add'>+		"CARD_EN_DET", /* GPIOC_6 */</div><div class='add'>+		"",</div><div class='add'>+		/* GPIOA */</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "",</div><div class='add'>+		"CON1-P27", /* GPIOA_14 */</div><div class='add'>+		"CON1-P28", /* GPIOA_15 */</div><div class='add'>+		/* GPIOX */</div><div class='add'>+		"CON1-P16", /* GPIOX_0 */</div><div class='add'>+		"CON1-P18", /* GPIOX_1 */</div><div class='add'>+		"CON1-P22", /* GPIOX_2 */</div><div class='add'>+		"CON1-P11", /* GPIOX_3 */</div><div class='add'>+		"CON1-P13", /* GPIOX_4 */</div><div class='add'>+		"CON1-P07", /* GPIOX_5 */</div><div class='add'>+		"CON1-P33", /* GPIOX_6 */</div><div class='add'>+		"CON1-P15", /* GPIOX_7 */</div><div class='add'>+		"CON1-P19", /* GPIOX_8 */</div><div class='add'>+		"CON1-P21", /* GPIOX_9 */</div><div class='add'>+		"CON1-P24", /* GPIOX_10 */</div><div class='add'>+		"CON1-P23", /* GPIOX_11 */</div><div class='add'>+		"CON1-P08", /* GPIOX_12 */</div><div class='add'>+		"CON1-P10", /* GPIOX_13 */</div><div class='add'>+		"CON1-P29", /* GPIOX_14 */</div><div class='add'>+		"CON1-P31", /* GPIOX_15 */</div><div class='add'>+		"CON1-P26", /* GPIOX_16 */</div><div class='add'>+		"CON1-P03", /* GPIOX_17 */</div><div class='add'>+		"CON1-P05", /* GPIOX_18 */</div><div class='add'>+		"CON1-P32"; /* GPIOX_19 */</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * WARNING: The USB Hub needs a reset signal to be turned high in</div><div class='add'>+	 * order to be detected by the USB Controller. This signal should</div><div class='add'>+	 * be handled by a USB specific power sequence to reset the Hub</div><div class='add'>+	 * when the USB bus is powered down.</div><div class='add'>+	 */</div><div class='add'>+	usb-hub-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;GPIOH_4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		output-high;</div><div class='add'>+		line-name = "usb-hub-reset";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio_ao {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		/* GPIOAO */</div><div class='add'>+		"DEBUG TX", /* GPIOAO_0 */</div><div class='add'>+		"DEBUG RX", /* GPIOAO_1 */</div><div class='add'>+		"SYS_LED2", /* GPIOAO_2 */</div><div class='add'>+		"UPDATE_KEY", /* GPIOAO_3 */</div><div class='add'>+		"CON1-P40", /* GPIOAO_4 */</div><div class='add'>+		"IR_IN", /* GPIOAO_5 */</div><div class='add'>+		"TF_3V3N_1V8_EN", /* GPIOAO_6 */</div><div class='add'>+		"CON1-P35", /* GPIOAO_7 */</div><div class='add'>+		"CON1-P12", /* GPIOAO_8 */</div><div class='add'>+		"CON1-P37", /* GPIOAO_9 */</div><div class='add'>+		"CON1-P38", /* GPIOAO_10 */</div><div class='add'>+		"SYS_LED", /* GPIOAO_11 */</div><div class='add'>+		/* GPIOE */</div><div class='add'>+		"VDDEE_PWM", /* GPIOE_0 */</div><div class='add'>+		"VDDCPU_PWM", /* GPIOE_1 */</div><div class='add'>+		"TF_PWR_EN"; /* GPIOE_2 */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;hdmitx_hpd_pins&gt;, &lt;&amp;hdmitx_ddc_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	hdmi-supply = &lt;&amp;dc_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx_tmds_port {</div><div class='add'>+	hdmi_tx_tmds_out: endpoint {</div><div class='add'>+		remote-endpoint = &lt;&amp;hdmi_connector_in&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ir {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;remote_input_ao_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm_AO_cd {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm_ao_d_e_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;saradc {</div><div class='add'>+	status = "okay";</div><div class='add'>+	vref-supply = &lt;&amp;vddao_1v8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SD card */</div><div class='add'>+&amp;sd_emmc_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdcard_c_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;sdcard_clk_gate_c_pins&gt;;</div><div class='add'>+	pinctrl-names = "default", "clk-gate";</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	/* Boot failures are observed at 50MHz */</div><div class='add'>+	max-frequency = &lt;35000000&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+</div><div class='add'>+	cd-gpios = &lt;&amp;gpio GPIOC_6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;tflash_vdd&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;vddio_c&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* eMMC */</div><div class='add'>+&amp;sd_emmc_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;emmc_ctrl_pins&gt;, &lt;&amp;emmc_data_8b_pins&gt;, &lt;&amp;emmc_ds_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;emmc_clk_gate_pins&gt;;</div><div class='add'>+	pinctrl-names = "default", "clk-gate";</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	cap-mmc-highspeed;</div><div class='add'>+	mmc-ddr-1_8v;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+</div><div class='add'>+	mmc-pwrseq = &lt;&amp;emmc_pwrseq&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;emmc_1v8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart_AO {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart_ao_a_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb2_phy0 {</div><div class='add'>+	phy-supply = &lt;&amp;dc_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb2_phy1 {</div><div class='add'>+	/* Enable the hub which is connected to this port */</div><div class='add'>+	phy-supply = &lt;&amp;vl_pwr_en&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-h96-max.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-h96-max.dts<br/>new file mode 100644<br/>index 000000000000..7b3a014d4cde<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-sm1-h96-max.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-sm1-h96-max.dts</a></div><div class='hunk'>@@ -0,0 +1,148 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2019 BayLibre SAS. All rights reserved.</div><div class='add'>+ * Copyright (c) 2020 Christian Hewitt &lt;christianshewitt@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "meson-sm1-ac2xx.dtsi"</div><div class='add'>+#include &lt;dt-bindings/sound/meson-g12a-tohdmitx.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "haochuangyi,h96-max", "amlogic,sm1";</div><div class='add'>+	model = "Shenzhen Haochuangyi Technology Co., Ltd H96 Max";</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "amlogic,axg-sound-card";</div><div class='add'>+		model = "H96-MAX";</div><div class='add'>+		audio-aux-devs = &lt;&amp;tdmout_b&gt;;</div><div class='add'>+		audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",</div><div class='add'>+				"TDMOUT_B IN 1", "FRDDR_B OUT 1",</div><div class='add'>+				"TDMOUT_B IN 2", "FRDDR_C OUT 1",</div><div class='add'>+				"TDM_B Playback", "TDMOUT_B OUT";</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;294912000&gt;,</div><div class='add'>+				       &lt;270950400&gt;,</div><div class='add'>+				       &lt;393216000&gt;;</div><div class='add'>+</div><div class='add'>+		dai-link-0 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_a&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-1 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_b&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-2 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_c&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* 8ch hdmi interface */</div><div class='add'>+		dai-link-3 {</div><div class='add'>+			sound-dai = &lt;&amp;tdmif_b&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			dai-tdm-slot-tx-mask-0 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-1 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-2 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-3 = &lt;1 1&gt;;</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_IN_B&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* hdmi glue */</div><div class='add'>+		dai-link-4 {</div><div class='add'>+			sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;arb {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;clkc_audio {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethmac {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pinctrl-0 = &lt;&amp;eth_pins&gt;, &lt;&amp;eth_rgmii_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	phy-mode = "rgmii-txid";</div><div class='add'>+	phy-handle = &lt;&amp;external_phy&gt;;</div><div class='add'>+</div><div class='add'>+	rx-internal-delay-ps = &lt;800&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ext_mdio {</div><div class='add'>+	external_phy: ethernet-phy@0 {</div><div class='add'>+		/* Realtek RTL8211F (0x001cc916) */</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		max-speed = &lt;1000&gt;;</div><div class='add'>+</div><div class='add'>+		reset-assert-us = &lt;10000&gt;;</div><div class='add'>+		reset-deassert-us = &lt;80000&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio_intc&gt;;</div><div class='add'>+		/* MAC_INTR on GPIOZ_14 */</div><div class='add'>+		interrupts = &lt;IRQID_GPIOZ_14 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmif_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmout_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tohdmitx {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart_A {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart_a_pins&gt;, &lt;&amp;uart_a_cts_rts_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "brcm,bcm43438-bt";</div><div class='add'>+		shutdown-gpios = &lt;&amp;gpio GPIOX_17 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		max-speed = &lt;2000000&gt;;</div><div class='add'>+		clocks = &lt;&amp;wifi32k&gt;;</div><div class='add'>+		clock-names = "lpo";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts<br/>index dbbf29a0dbf6..a3d9b66b6878 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts</a></div><div class='hunk'>@@ -8,6 +8,7 @@</div><div class='ctx'> </div><div class='ctx'> #include "meson-sm1.dtsi"</div><div class='ctx'> #include "meson-khadas-vim3.dtsi"</div><div class='add'>+#include &lt;dt-bindings/sound/meson-g12a-tohdmitx.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	compatible = "khadas,vim3l", "amlogic,sm1";</div><div class='hunk'>@@ -23,7 +24,7 @@</div><div class='ctx'> 		regulator-min-microvolt = &lt;690000&gt;;</div><div class='ctx'> 		regulator-max-microvolt = &lt;1050000&gt;;</div><div class='ctx'> </div><div class='del'>-		vin-supply = &lt;&amp;vsys_3v3&gt;;</div><div class='add'>+		pwm-supply = &lt;&amp;vsys_3v3&gt;;</div><div class='ctx'> </div><div class='ctx'> 		pwms = &lt;&amp;pwm_AO_cd 1 1250 0&gt;;</div><div class='ctx'> 		pwm-dutycycle-range = &lt;100 0&gt;;</div><div class='hunk'>@@ -31,41 +32,48 @@</div><div class='ctx'> 		regulator-boot-on;</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		model = "G12B-KHADAS-VIM3L";</div><div class='add'>+		audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",</div><div class='add'>+				"TDMOUT_A IN 1", "FRDDR_B OUT 0",</div><div class='add'>+				"TDMOUT_A IN 2", "FRDDR_C OUT 0",</div><div class='add'>+				"TDM_A Playback", "TDMOUT_A OUT",</div><div class='add'>+				"TDMIN_A IN 0", "TDM_A Capture",</div><div class='add'>+				"TDMIN_A IN 13", "TDM_A Loopback",</div><div class='add'>+				"TODDR_A IN 0", "TDMIN_A OUT",</div><div class='add'>+				"TODDR_B IN 0", "TDMIN_A OUT",</div><div class='add'>+				"TODDR_C IN 0", "TDMIN_A OUT";</div><div class='add'>+	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cpu0 {</div><div class='ctx'> 	cpu-supply = &lt;&amp;vddcpu&gt;;</div><div class='ctx'> 	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='ctx'> 	clocks = &lt;&amp;clkc CLKID_CPU_CLK&gt;;</div><div class='del'>-	clock-latency = &lt;50000&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cpu1 {</div><div class='ctx'> 	cpu-supply = &lt;&amp;vddcpu&gt;;</div><div class='ctx'> 	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='ctx'> 	clocks = &lt;&amp;clkc CLKID_CPU1_CLK&gt;;</div><div class='del'>-	clock-latency = &lt;50000&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cpu2 {</div><div class='ctx'> 	cpu-supply = &lt;&amp;vddcpu&gt;;</div><div class='ctx'> 	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='ctx'> 	clocks = &lt;&amp;clkc CLKID_CPU2_CLK&gt;;</div><div class='del'>-	clock-latency = &lt;50000&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cpu3 {</div><div class='ctx'> 	cpu-supply = &lt;&amp;vddcpu&gt;;</div><div class='ctx'> 	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='ctx'> 	clocks = &lt;&amp;clkc CLKID_CPU3_CLK&gt;;</div><div class='del'>-	clock-latency = &lt;50000&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;pwm_AO_cd {</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pwm_ao_d_e_pins&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='del'>-	clocks = &lt;&amp;xtal&gt;;</div><div class='del'>-	clock-names = "clkin1";</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -93,3 +101,7 @@</div><div class='ctx'> 	phy-names = "usb2-phy0", "usb2-phy1";</div><div class='ctx'> };</div><div class='ctx'>  */</div><div class='add'>+</div><div class='add'>+&amp;sd_emmc_a {</div><div class='add'>+	sd-uhs-sdr50;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts<br/>new file mode 100644<br/>index 000000000000..d04768a66bfe<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts</a></div><div class='hunk'>@@ -0,0 +1,58 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2020 Dongjin Kim &lt;tobetter@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "meson-sm1-odroid.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "hardkernel,odroid-c4", "amlogic,sm1";</div><div class='add'>+	model = "Hardkernel ODROID-C4";</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-blue {</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			gpios = &lt;&amp;gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+			panic-indicator;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		model = "ODROID-C4";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USB hub supports both USB 2.0 and USB 3.0 root hub */</div><div class='add'>+	usb-hub {</div><div class='add'>+		dr_mode = "host";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		/* 2.0 hub on port 1 */</div><div class='add'>+		hub_2_0: hub@1 {</div><div class='add'>+			compatible = "usb2109,2817";</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			peer-hub = &lt;&amp;hub_3_0&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio GPIOH_4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			vdd-supply = &lt;&amp;vcc_5v&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* 3.1 hub on port 4 */</div><div class='add'>+		hub_3_0: hub@2 {</div><div class='add'>+			compatible = "usb2109,817";</div><div class='add'>+			reg = &lt;2&gt;;</div><div class='add'>+			peer-hub = &lt;&amp;hub_2_0&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio GPIOH_4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			vdd-supply = &lt;&amp;vcc_5v&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ir {</div><div class='add'>+	linux,rc-map-name = "rc-odroid";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts<br/>new file mode 100644<br/>index 000000000000..0170139b8d32<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts</a></div><div class='hunk'>@@ -0,0 +1,142 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2020 Dongjin Kim &lt;tobetter@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "meson-sm1-odroid.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "hardkernel,odroid-hc4", "amlogic,sm1";</div><div class='add'>+	model = "Hardkernel ODROID-HC4";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		rtc0 = &amp;rtc;</div><div class='add'>+		rtc1 = &amp;vrtc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fan0: pwm-fan {</div><div class='add'>+		compatible = "pwm-fan";</div><div class='add'>+		#cooling-cells = &lt;2&gt;;</div><div class='add'>+		cooling-levels = &lt;0 120 170 220&gt;;</div><div class='add'>+		pwms = &lt;&amp;pwm_cd 1 40000 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-blue {</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			gpios = &lt;&amp;gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+			panic-indicator;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-red {</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			function = LED_FUNCTION_POWER;</div><div class='add'>+			gpios = &lt;&amp;gpio_ao GPIOAO_7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "on";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Powers the SATA Disk 0 regulator, which is enabled when a disk load is detected */</div><div class='add'>+	p12v_0: regulator-p12v-0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "P12V_0";</div><div class='add'>+		regulator-min-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;12000000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;main_12v&gt;;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;gpio GPIOH_8 GPIO_OPEN_DRAIN&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Powers the SATA Disk 1 regulator, which is enabled when a disk load is detected */</div><div class='add'>+	p12v_1: regulator-p12v-1 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "P12V_1";</div><div class='add'>+		regulator-min-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;12000000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;main_12v&gt;;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;gpio GPIOH_8 GPIO_OPEN_DRAIN&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		model = "ODROID-HC4";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu_thermal {</div><div class='add'>+	trips {</div><div class='add'>+		cpu_active: cpu-active {</div><div class='add'>+			temperature = &lt;60000&gt;; /* millicelsius */</div><div class='add'>+			hysteresis = &lt;2000&gt;; /* millicelsius */</div><div class='add'>+			type = "active";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cooling-maps {</div><div class='add'>+		map {</div><div class='add'>+			trip = &lt;&amp;cpu_active&gt;;</div><div class='add'>+			cooling-device = &lt;&amp;fan0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ir {</div><div class='add'>+	linux,rc-map-name = "rc-odroid";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c2_sda_x_pins&gt;, &lt;&amp;i2c2_sck_x_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	rtc: rtc@51 {</div><div class='add'>+		status = "okay";</div><div class='add'>+		compatible = "nxp,pcf8563";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		wakeup-source;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie {</div><div class='add'>+	status = "okay";</div><div class='add'>+	reset-gpios = &lt;&amp;gpio GPIOH_4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm_cd {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm_d_x6_pins&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sd_emmc_c {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spifc {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;nor_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	flash@0 {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;104000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb {</div><div class='add'>+	phys = &lt;&amp;usb2_phy0&gt;, &lt;&amp;usb2_phy1&gt;;</div><div class='add'>+	phy-names = "usb2-phy0", "usb2-phy1";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi<br/>new file mode 100644<br/>index 000000000000..c4524eb4f099<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi</a></div><div class='hunk'>@@ -0,0 +1,464 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2020 Dongjin Kim &lt;tobetter@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "meson-sm1.dtsi"</div><div class='add'>+#include &lt;dt-bindings/gpio/meson-g12a-gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/meson-g12a-tohdmitx.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart_AO;</div><div class='add'>+		ethernet0 = &amp;ethmac;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x0 0x0 0x40000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	emmc_pwrseq: emmc-pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-emmc";</div><div class='add'>+		reset-gpios = &lt;&amp;gpio BOOT_12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	tflash_vdd: regulator-tflash-vdd {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+</div><div class='add'>+		regulator-name = "TFLASH_VDD";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;gpio_ao GPIOAO_3 GPIO_OPEN_DRAIN&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	tf_io: gpio-regulator-tf-io {</div><div class='add'>+		compatible = "regulator-gpio";</div><div class='add'>+</div><div class='add'>+		regulator-name = "TF_IO";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vcc_5v&gt;;</div><div class='add'>+</div><div class='add'>+		enable-gpios = &lt;&amp;gpio_ao GPIOE_2 GPIO_OPEN_DRAIN&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+</div><div class='add'>+		gpios = &lt;&amp;gpio_ao GPIOAO_6 GPIO_OPEN_SOURCE&gt;;</div><div class='add'>+		gpios-states = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		states = &lt;3300000 0&gt;,</div><div class='add'>+			 &lt;1800000 1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	flash_1v8: regulator-flash-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "FLASH_1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vcc_3v3&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	main_12v: regulator-main-12v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "12V";</div><div class='add'>+		regulator-min-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vcc_5v: regulator-vcc-5v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "5V";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		vin-supply = &lt;&amp;main_12v&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio GPIOH_8 GPIO_OPEN_DRAIN&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vcc_1v8: regulator-vcc-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCC_1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vcc_3v3&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vcc_3v3: regulator-vcc-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCC_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		/* FIXME: actually controlled by VDDCPU_B_EN */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddcpu: regulator-vddcpu {</div><div class='add'>+		/*</div><div class='add'>+		 * MP8756GD Regulator.</div><div class='add'>+		 */</div><div class='add'>+		compatible = "pwm-regulator";</div><div class='add'>+</div><div class='add'>+		regulator-name = "VDDCPU";</div><div class='add'>+		regulator-min-microvolt = &lt;721000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1022000&gt;;</div><div class='add'>+</div><div class='add'>+		pwm-supply = &lt;&amp;main_12v&gt;;</div><div class='add'>+</div><div class='add'>+		pwms = &lt;&amp;pwm_AO_cd 1 1250 0&gt;;</div><div class='add'>+		pwm-dutycycle-range = &lt;100 0&gt;;</div><div class='add'>+</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb_pwr_en: regulator-usb-pwr-en {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "USB_PWR_EN";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vcc_5v&gt;;</div><div class='add'>+</div><div class='add'>+		/* Connected to the microUSB port power enable */</div><div class='add'>+		gpio = &lt;&amp;gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddao_1v8: regulator-vddao-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDAO_1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vddao_3v3: regulator-vddao-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDAO_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;main_12v&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdmi-connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		type = "a";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			hdmi_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_tx_tmds_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "amlogic,axg-sound-card";</div><div class='add'>+		audio-aux-devs = &lt;&amp;tdmout_b&gt;;</div><div class='add'>+		audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",</div><div class='add'>+				"TDMOUT_B IN 1", "FRDDR_B OUT 1",</div><div class='add'>+				"TDMOUT_B IN 2", "FRDDR_C OUT 1",</div><div class='add'>+				"TDM_B Playback", "TDMOUT_B OUT";</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;294912000&gt;,</div><div class='add'>+				       &lt;270950400&gt;,</div><div class='add'>+				       &lt;393216000&gt;;</div><div class='add'>+</div><div class='add'>+		dai-link-0 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_a&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-1 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_b&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-2 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_c&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* 8ch hdmi interface */</div><div class='add'>+		dai-link-3 {</div><div class='add'>+			sound-dai = &lt;&amp;tdmif_b&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			dai-tdm-slot-tx-mask-0 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-1 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-2 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-3 = &lt;1 1&gt;;</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_IN_B&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* hdmi glue */</div><div class='add'>+		dai-link-4 {</div><div class='add'>+			sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;arb {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cec_AO {</div><div class='add'>+	pinctrl-0 = &lt;&amp;cec_ao_a_h_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "disabled";</div><div class='add'>+	hdmi-phandle = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cecb_AO {</div><div class='add'>+	pinctrl-0 = &lt;&amp;cec_ao_b_h_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+	hdmi-phandle = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;clkc_audio {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPU_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu1 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPU1_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu2 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPU2_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu3 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPU3_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ext_mdio {</div><div class='add'>+	external_phy: ethernet-phy@0 {</div><div class='add'>+		/* Realtek RTL8211F (0x001cc916) */</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		max-speed = &lt;1000&gt;;</div><div class='add'>+</div><div class='add'>+		reset-assert-us = &lt;10000&gt;;</div><div class='add'>+		reset-deassert-us = &lt;80000&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio_intc&gt;;</div><div class='add'>+		/* MAC_INTR on GPIOZ_14 */</div><div class='add'>+		interrupts = &lt;IRQID_GPIOZ_14 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethmac {</div><div class='add'>+	pinctrl-0 = &lt;&amp;eth_pins&gt;, &lt;&amp;eth_rgmii_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+	phy-mode = "rgmii";</div><div class='add'>+	phy-handle = &lt;&amp;external_phy&gt;;</div><div class='add'>+	amlogic,tx-delay-ns = &lt;2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		/* GPIOZ */</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		/* GPIOH */</div><div class='add'>+		"", "", "", "", "",</div><div class='add'>+		"PIN_36", /* GPIOH_5 */</div><div class='add'>+		"PIN_26", /* GPIOH_6 */</div><div class='add'>+		"PIN_32", /* GPIOH_7 */</div><div class='add'>+		"",</div><div class='add'>+		/* BOOT */</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		/* GPIOC */</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		/* GPIOA */</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "",</div><div class='add'>+		"PIN_27", /* GPIOA_14 */</div><div class='add'>+		"PIN_28", /* GPIOA_15 */</div><div class='add'>+		/* GPIOX */</div><div class='add'>+		"PIN_16", /* GPIOX_0 */</div><div class='add'>+		"PIN_18", /* GPIOX_1 */</div><div class='add'>+		"PIN_22", /* GPIOX_2 */</div><div class='add'>+		"PIN_11", /* GPIOX_3 */</div><div class='add'>+		"PIN_13", /* GPIOX_4 */</div><div class='add'>+		"PIN_7",  /* GPIOX_5 */</div><div class='add'>+		"PIN_33", /* GPIOX_6 */</div><div class='add'>+		"PIN_15", /* GPIOX_7 */</div><div class='add'>+		"PIN_19", /* GPIOX_8 */</div><div class='add'>+		"PIN_21", /* GPIOX_9 */</div><div class='add'>+		"PIN_24", /* GPIOX_10 */</div><div class='add'>+		"PIN_23", /* GPIOX_11 */</div><div class='add'>+		"PIN_8",  /* GPIOX_12 */</div><div class='add'>+		"PIN_10", /* GPIOX_13 */</div><div class='add'>+		"PIN_29", /* GPIOX_14 */</div><div class='add'>+		"PIN_31", /* GPIOX_15 */</div><div class='add'>+		"PIN_12", /* GPIOX_16 */</div><div class='add'>+		"PIN_3",  /* GPIOX_17 */</div><div class='add'>+		"PIN_5",  /* GPIOX_18 */</div><div class='add'>+		"PIN_35"; /* GPIOX_19 */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio_ao {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		/* GPIOAO */</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"PIN_47", /* GPIOAO_4 */</div><div class='add'>+		"", "",</div><div class='add'>+		"PIN_45", /* GPIOAO_7 */</div><div class='add'>+		"PIN_46", /* GPIOAO_8 */</div><div class='add'>+		"PIN_44", /* GPIOAO_9 */</div><div class='add'>+		"PIN_42", /* GPIOAO_10 */</div><div class='add'>+		"",</div><div class='add'>+		/* GPIOE */</div><div class='add'>+		"", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;hdmitx_hpd_pins&gt;, &lt;&amp;hdmitx_ddc_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	hdmi-supply = &lt;&amp;vcc_5v&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx_tmds_port {</div><div class='add'>+	hdmi_tx_tmds_out: endpoint {</div><div class='add'>+		remote-endpoint = &lt;&amp;hdmi_connector_in&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ir {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;remote_input_ao_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm_AO_cd {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm_ao_d_e_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;saradc {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SD card */</div><div class='add'>+&amp;sd_emmc_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdcard_c_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;sdcard_clk_gate_c_pins&gt;;</div><div class='add'>+	pinctrl-names = "default", "clk-gate";</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	sd-uhs-sdr12;</div><div class='add'>+	sd-uhs-sdr25;</div><div class='add'>+	sd-uhs-sdr50;</div><div class='add'>+	sd-uhs-sdr104;</div><div class='add'>+	disable-wp;</div><div class='add'>+</div><div class='add'>+	cd-gpios = &lt;&amp;gpio GPIOC_6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;tflash_vdd&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;tf_io&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* eMMC */</div><div class='add'>+&amp;sd_emmc_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;emmc_ctrl_pins&gt;, &lt;&amp;emmc_data_8b_pins&gt;, &lt;&amp;emmc_ds_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;emmc_clk_gate_pins&gt;;</div><div class='add'>+	pinctrl-names = "default", "clk-gate";</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	cap-mmc-highspeed;</div><div class='add'>+	mmc-ddr-1_8v;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+</div><div class='add'>+	mmc-pwrseq = &lt;&amp;emmc_pwrseq&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;vcc_3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;flash_1v8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmif_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmout_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tohdmitx {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart_AO {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart_ao_a_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb {</div><div class='add'>+	status = "okay";</div><div class='add'>+	vbus-supply = &lt;&amp;usb_pwr_en&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb2_phy0 {</div><div class='add'>+	phy-supply = &lt;&amp;vcc_5v&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-s905d3-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-s905d3-libretech-cc.dts<br/>new file mode 100644<br/>index 000000000000..5daadfb170b4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-sm1-s905d3-libretech-cc.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-sm1-s905d3-libretech-cc.dts</a></div><div class='hunk'>@@ -0,0 +1,85 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2023 BayLibre, SAS.</div><div class='add'>+ * Author: Jerome Brunet &lt;jbrunet@baylibre.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/g12a-clkc.h&gt;</div><div class='add'>+#include "meson-sm1.dtsi"</div><div class='add'>+#include "meson-libretech-cottonwood.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "libretech,aml-s905d3-cc", "amlogic,sm1";</div><div class='add'>+	model = "Libre Computer AML-S905D3-CC Solitude";</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		model = "LC-SOLITUDE";</div><div class='add'>+		audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",</div><div class='add'>+				"TDMOUT_A IN 1", "FRDDR_B OUT 0",</div><div class='add'>+				"TDMOUT_A IN 2", "FRDDR_C OUT 0",</div><div class='add'>+				"TDM_A Playback", "TDMOUT_A OUT",</div><div class='add'>+				"TDMOUT_B IN 0", "FRDDR_A OUT 1",</div><div class='add'>+				"TDMOUT_B IN 1", "FRDDR_B OUT 1",</div><div class='add'>+				"TDMOUT_B IN 2", "FRDDR_C OUT 1",</div><div class='add'>+				"TDM_B Playback", "TDMOUT_B OUT",</div><div class='add'>+				"TDMOUT_C IN 0", "FRDDR_A OUT 2",</div><div class='add'>+				"TDMOUT_C IN 1", "FRDDR_B OUT 2",</div><div class='add'>+				"TDMOUT_C IN 2", "FRDDR_C OUT 2",</div><div class='add'>+				"TDM_C Playback", "TDMOUT_C OUT",</div><div class='add'>+				"TDMIN_A IN 0", "TDM_A Capture",</div><div class='add'>+				"TDMIN_B IN 0", "TDM_A Capture",</div><div class='add'>+				"TDMIN_C IN 0", "TDM_A Capture",</div><div class='add'>+				"TDMIN_A IN 13", "TDM_A Loopback",</div><div class='add'>+				"TDMIN_B IN 13", "TDM_A Loopback",</div><div class='add'>+				"TDMIN_C IN 13", "TDM_A Loopback",</div><div class='add'>+				"TDMIN_A IN 1", "TDM_B Capture",</div><div class='add'>+				"TDMIN_B IN 1", "TDM_B Capture",</div><div class='add'>+				"TDMIN_C IN 1", "TDM_B Capture",</div><div class='add'>+				"TDMIN_A IN 14", "TDM_B Loopback",</div><div class='add'>+				"TDMIN_B IN 14", "TDM_B Loopback",</div><div class='add'>+				"TDMIN_C IN 14", "TDM_B Loopback",</div><div class='add'>+				"TDMIN_A IN 2", "TDM_C Capture",</div><div class='add'>+				"TDMIN_B IN 2", "TDM_C Capture",</div><div class='add'>+				"TDMIN_C IN 2", "TDM_C Capture",</div><div class='add'>+				"TDMIN_A IN 15", "TDM_C Loopback",</div><div class='add'>+				"TDMIN_B IN 15", "TDM_C Loopback",</div><div class='add'>+				"TDMIN_C IN 15", "TDM_C Loopback",</div><div class='add'>+				"TODDR_A IN 0", "TDMIN_A OUT",</div><div class='add'>+				"TODDR_B IN 0", "TDMIN_A OUT",</div><div class='add'>+				"TODDR_C IN 0", "TDMIN_A OUT",</div><div class='add'>+				"TODDR_A IN 1", "TDMIN_B OUT",</div><div class='add'>+				"TODDR_B IN 1", "TDMIN_B OUT",</div><div class='add'>+				"TODDR_C IN 1", "TDMIN_B OUT",</div><div class='add'>+				"TODDR_A IN 2", "TDMIN_C OUT",</div><div class='add'>+				"TODDR_B IN 2", "TDMIN_C OUT",</div><div class='add'>+				"TODDR_C IN 2", "TDMIN_C OUT",</div><div class='add'>+				"Lineout", "ACODEC LOLP",</div><div class='add'>+				"Lineout", "ACODEC LORP";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu_b&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPU_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu1 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu_b&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPU1_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu2 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu_b&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPU2_CLK&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu3 {</div><div class='add'>+	cpu-supply = &lt;&amp;vddcpu_b&gt;;</div><div class='add'>+	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+	clocks = &lt;&amp;clkc CLKID_CPU3_CLK&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts<br/>index dfb2438851c0..024d2eb8e6ee 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts</a></div><div class='hunk'>@@ -32,7 +32,6 @@</div><div class='ctx'> 		compatible = "dmic-codec";</div><div class='ctx'> 		num-channels = &lt;2&gt;;</div><div class='ctx'> 		wakeup-delay-ms = &lt;50&gt;;</div><div class='del'>-		status = "okay";</div><div class='ctx'> 		sound-name-prefix = "MIC";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -48,45 +47,45 @@</div><div class='ctx'> 	gpio-keys {</div><div class='ctx'> 		compatible = "gpio-keys";</div><div class='ctx'> </div><div class='del'>-		key1 {</div><div class='add'>+		key-1 {</div><div class='ctx'> 			label = "A";</div><div class='ctx'> 			linux,code = &lt;BTN_0&gt;;</div><div class='ctx'> 			gpios = &lt;&amp;gpio GPIOH_6 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 			interrupt-parent = &lt;&amp;gpio_intc&gt;;</div><div class='del'>-			interrupts = &lt;34 IRQ_TYPE_EDGE_BOTH&gt;;</div><div class='add'>+			interrupts = &lt;IRQID_GPIOH_6 IRQ_TYPE_EDGE_BOTH&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		key2 {</div><div class='add'>+		key-2 {</div><div class='ctx'> 			label = "B";</div><div class='ctx'> 			linux,code = &lt;BTN_1&gt;;</div><div class='ctx'> 			gpios = &lt;&amp;gpio GPIOH_7 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 			interrupt-parent = &lt;&amp;gpio_intc&gt;;</div><div class='del'>-			interrupts = &lt;35 IRQ_TYPE_EDGE_BOTH&gt;;</div><div class='add'>+			interrupts = &lt;IRQID_GPIOH_7 IRQ_TYPE_EDGE_BOTH&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		key3 {</div><div class='add'>+		key-3 {</div><div class='ctx'> 			label = "C";</div><div class='ctx'> 			linux,code = &lt;BTN_2&gt;;</div><div class='ctx'> 			gpios = &lt;&amp;gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 			interrupt-parent = &lt;&amp;gpio_intc&gt;;</div><div class='del'>-			interrupts = &lt;2 IRQ_TYPE_EDGE_BOTH&gt;;</div><div class='add'>+			interrupts = &lt;IRQID_GPIOAO_2 IRQ_TYPE_EDGE_BOTH&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		mic_mute {</div><div class='add'>+		key-mic-mute {</div><div class='ctx'> 			label = "MicMute";</div><div class='ctx'> 			linux,code = &lt;SW_MUTE_DEVICE&gt;;</div><div class='ctx'> 			linux,input-type = &lt;EV_SW&gt;;</div><div class='ctx'> 			gpios = &lt;&amp;gpio_ao GPIOE_2 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 			interrupt-parent = &lt;&amp;gpio_intc&gt;;</div><div class='del'>-			interrupts = &lt;99 IRQ_TYPE_EDGE_BOTH&gt;;</div><div class='add'>+			interrupts = &lt;IRQID_GPIOE_2 IRQ_TYPE_EDGE_BOTH&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		power_key {</div><div class='add'>+		key-power {</div><div class='ctx'> 			label = "PowerKey";</div><div class='ctx'> 			linux,code = &lt;KEY_POWER&gt;;</div><div class='ctx'> 			gpios = &lt;&amp;gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 			interrupt-parent = &lt;&amp;gpio_intc&gt;;</div><div class='del'>-			interrupts = &lt;3 IRQ_TYPE_EDGE_BOTH&gt;;</div><div class='add'>+			interrupts = &lt;IRQID_GPIOAO_3 IRQ_TYPE_EDGE_BOTH&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -101,20 +100,20 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	leds {</div><div class='add'>+	led-controller-1 {</div><div class='ctx'> 		compatible = "gpio-leds";</div><div class='ctx'> </div><div class='del'>-		bluetooth {</div><div class='add'>+		led-1 {</div><div class='ctx'> 			label = "sei610:blue:bt";</div><div class='ctx'> 			gpios = &lt;&amp;gpio GPIOC_7 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)&gt;;</div><div class='ctx'> 			default-state = "off";</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pwmleds {</div><div class='add'>+	led-controller-2 {</div><div class='ctx'> 		compatible = "pwm-leds";</div><div class='ctx'> </div><div class='del'>-		power {</div><div class='add'>+		led-2 {</div><div class='ctx'> 			label = "sei610:red:power";</div><div class='ctx'> 			pwms = &lt;&amp;pwm_AO_ab 0 30518 0&gt;;</div><div class='ctx'> 			max-brightness = &lt;255&gt;;</div><div class='hunk'>@@ -128,7 +127,7 @@</div><div class='ctx'> 		reg = &lt;0x0 0x0 0x0 0x40000000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	ao_5v: regulator-ao_5v {</div><div class='add'>+	ao_5v: regulator-ao-5v {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "AO_5V";</div><div class='ctx'> 		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='hunk'>@@ -137,7 +136,7 @@</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	dc_in: regulator-dc_in {</div><div class='add'>+	dc_in: regulator-dc-in {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "DC_IN";</div><div class='ctx'> 		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='hunk'>@@ -145,7 +144,7 @@</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	emmc_1v8: regulator-emmc_1v8 {</div><div class='add'>+	emmc_1v8: regulator-emmc-1v8 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "EMMC_1V8";</div><div class='ctx'> 		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='hunk'>@@ -154,7 +153,7 @@</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vddao_3v3: regulator-vddao_3v3 {</div><div class='add'>+	vddao_3v3: regulator-vddao-3v3 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VDDAO_3V3";</div><div class='ctx'> 		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='hunk'>@@ -164,14 +163,13 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	/* Used by Tuner, RGB Led &amp; IR Emitter LED array */</div><div class='del'>-	vddao_3v3_t: regulator-vddao_3v3_t {</div><div class='add'>+	vddao_3v3_t: regulator-vddao-3v3-t {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VDDAO_3V3_T";</div><div class='ctx'> 		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='ctx'> 		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='ctx'> 		vin-supply = &lt;&amp;vddao_3v3&gt;;</div><div class='ctx'> 		gpio = &lt;&amp;gpio GPIOH_8 GPIO_OPEN_DRAIN&gt;;</div><div class='del'>-		enable-active-low;</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -185,7 +183,7 @@</div><div class='ctx'> 		regulator-min-microvolt = &lt;690000&gt;;</div><div class='ctx'> 		regulator-max-microvolt = &lt;1050000&gt;;</div><div class='ctx'> </div><div class='del'>-		vin-supply = &lt;&amp;dc_in&gt;;</div><div class='add'>+		pwm-supply = &lt;&amp;dc_in&gt;;</div><div class='ctx'> </div><div class='ctx'> 		pwms = &lt;&amp;pwm_AO_cd 1 1500 0&gt;;</div><div class='ctx'> 		pwm-dutycycle-range = &lt;100 0&gt;;</div><div class='hunk'>@@ -194,7 +192,7 @@</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vddio_ao1v8: regulator-vddio_ao1v8 {</div><div class='add'>+	vddio_ao1v8: regulator-vddio-ao1v8 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VDDIO_AO1V8";</div><div class='ctx'> 		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='hunk'>@@ -203,14 +201,6 @@</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	reserved-memory {</div><div class='del'>-		/* TEE Reserved Memory */</div><div class='del'>-		bl32_reserved: bl32@5000000 {</div><div class='del'>-			reg = &lt;0x0 0x05300000 0x0 0x2000000&gt;;</div><div class='del'>-			no-map;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='ctx'> 	sdio_pwrseq: sdio-pwrseq {</div><div class='ctx'> 		compatible = "mmc-pwrseq-simple";</div><div class='ctx'> 		reset-gpios = &lt;&amp;gpio GPIOX_6 GPIO_ACTIVE_LOW&gt;;</div><div class='hunk'>@@ -220,7 +210,7 @@</div><div class='ctx'> </div><div class='ctx'> 	sound {</div><div class='ctx'> 		compatible = "amlogic,axg-sound-card";</div><div class='del'>-		model = "SM1-SEI610";</div><div class='add'>+		model = "SEI610";</div><div class='ctx'> 		audio-aux-devs = &lt;&amp;tdmout_a&gt;, &lt;&amp;tdmout_b&gt;,</div><div class='ctx'> 				 &lt;&amp;tdmin_a&gt;, &lt;&amp;tdmin_b&gt;;</div><div class='ctx'> 		audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",</div><div class='hunk'>@@ -249,6 +239,10 @@</div><div class='ctx'> 				"TODDR_B IN 1", "TDMIN_B OUT",</div><div class='ctx'> 				"TODDR_C IN 1", "TDMIN_B OUT";</div><div class='ctx'> </div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+</div><div class='ctx'> 		assigned-clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='ctx'> 				  &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='ctx'> 				  &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='hunk'>@@ -256,7 +250,6 @@</div><div class='ctx'> 		assigned-clock-rates = &lt;294912000&gt;,</div><div class='ctx'> 				       &lt;270950400&gt;,</div><div class='ctx'> 				       &lt;393216000&gt;;</div><div class='del'>-		status = "okay";</div><div class='ctx'> </div><div class='ctx'> 		dai-link-0 {</div><div class='ctx'> 			sound-dai = &lt;&amp;frddr_a&gt;;</div><div class='hunk'>@@ -366,28 +359,24 @@</div><div class='ctx'> 	cpu-supply = &lt;&amp;vddcpu&gt;;</div><div class='ctx'> 	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='ctx'> 	clocks = &lt;&amp;clkc CLKID_CPU_CLK&gt;;</div><div class='del'>-	clock-latency = &lt;50000&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cpu1 {</div><div class='ctx'> 	cpu-supply = &lt;&amp;vddcpu&gt;;</div><div class='ctx'> 	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='ctx'> 	clocks = &lt;&amp;clkc CLKID_CPU1_CLK&gt;;</div><div class='del'>-	clock-latency = &lt;50000&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cpu2 {</div><div class='ctx'> 	cpu-supply = &lt;&amp;vddcpu&gt;;</div><div class='ctx'> 	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='ctx'> 	clocks = &lt;&amp;clkc CLKID_CPU2_CLK&gt;;</div><div class='del'>-	clock-latency = &lt;50000&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cpu3 {</div><div class='ctx'> 	cpu-supply = &lt;&amp;vddcpu&gt;;</div><div class='ctx'> 	operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='ctx'> 	clocks = &lt;&amp;clkc CLKID_CPU3_CLK&gt;;</div><div class='del'>-	clock-latency = &lt;50000&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;ethmac {</div><div class='hunk'>@@ -442,15 +431,11 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pwm_ao_a_pins&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='del'>-	clocks = &lt;&amp;xtal&gt;;</div><div class='del'>-	clock-names = "clkin0";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;pwm_AO_cd {</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pwm_ao_d_e_pins&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='del'>-	clocks = &lt;&amp;xtal&gt;;</div><div class='del'>-	clock-names = "clkin1";</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -458,8 +443,6 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pwm_e_pins&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='del'>-	clocks = &lt;&amp;xtal&gt;;</div><div class='del'>-	clock-names = "clkin0";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;saradc {</div><div class='hunk'>@@ -592,7 +575,7 @@</div><div class='ctx'> 	bluetooth {</div><div class='ctx'> 		compatible = "brcm,bcm43438-bt";</div><div class='ctx'> 		interrupt-parent = &lt;&amp;gpio_intc&gt;;</div><div class='del'>-		interrupts = &lt;95 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupts = &lt;IRQID_GPIOX_18 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		interrupt-names = "host-wakeup";</div><div class='ctx'> 		shutdown-gpios = &lt;&amp;gpio GPIOX_17 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 		max-speed = &lt;2000000&gt;;</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air-gbit.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air-gbit.dts<br/>new file mode 100644<br/>index 000000000000..e4a3a2a8ad06<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air-gbit.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-sm1-x96-air-gbit.dts</a></div><div class='hunk'>@@ -0,0 +1,136 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2019 BayLibre SAS. All rights reserved.</div><div class='add'>+ * Copyright (c) 2020 Christian Hewitt &lt;christianshewitt@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "meson-sm1-ac2xx.dtsi"</div><div class='add'>+#include &lt;dt-bindings/sound/meson-g12a-tohdmitx.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "amediatech,x96-air-gbit", "amlogic,sm1";</div><div class='add'>+	model = "Shenzhen Amediatech Technology Co., Ltd X96 Air";</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "amlogic,axg-sound-card";</div><div class='add'>+		model = "X96-AIR";</div><div class='add'>+		audio-aux-devs = &lt;&amp;tdmout_b&gt;;</div><div class='add'>+		audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",</div><div class='add'>+				"TDMOUT_B IN 1", "FRDDR_B OUT 1",</div><div class='add'>+				"TDMOUT_B IN 2", "FRDDR_C OUT 1",</div><div class='add'>+				"TDM_B Playback", "TDMOUT_B OUT";</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;294912000&gt;,</div><div class='add'>+				       &lt;270950400&gt;,</div><div class='add'>+				       &lt;393216000&gt;;</div><div class='add'>+</div><div class='add'>+		dai-link-0 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_a&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-1 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_b&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-2 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_c&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* 8ch hdmi interface */</div><div class='add'>+		dai-link-3 {</div><div class='add'>+			sound-dai = &lt;&amp;tdmif_b&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			dai-tdm-slot-tx-mask-0 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-1 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-2 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-3 = &lt;1 1&gt;;</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_IN_B&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* hdmi glue */</div><div class='add'>+		dai-link-4 {</div><div class='add'>+			sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;arb {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;clkc_audio {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethmac {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pinctrl-0 = &lt;&amp;eth_pins&gt;, &lt;&amp;eth_rgmii_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	phy-mode = "rgmii-txid";</div><div class='add'>+	phy-handle = &lt;&amp;external_phy&gt;;</div><div class='add'>+</div><div class='add'>+	rx-internal-delay-ps = &lt;800&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ext_mdio {</div><div class='add'>+	external_phy: ethernet-phy@0 {</div><div class='add'>+		/* Realtek RTL8211F (0x001cc916) */</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		max-speed = &lt;1000&gt;;</div><div class='add'>+</div><div class='add'>+		reset-assert-us = &lt;10000&gt;;</div><div class='add'>+		reset-deassert-us = &lt;80000&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio_intc&gt;;</div><div class='add'>+		/* MAC_INTR on GPIOZ_14 */</div><div class='add'>+		interrupts = &lt;IRQID_GPIOZ_14 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ir {</div><div class='add'>+	linux,rc-map-name = "rc-x96max";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmif_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmout_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tohdmitx {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air.dts<br/>new file mode 100644<br/>index 000000000000..fff92e0d6dd5<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-sm1-x96-air.dts</a></div><div class='hunk'>@@ -0,0 +1,115 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2019 BayLibre SAS. All rights reserved.</div><div class='add'>+ * Copyright (c) 2020 Christian Hewitt &lt;christianshewitt@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "meson-sm1-ac2xx.dtsi"</div><div class='add'>+#include &lt;dt-bindings/sound/meson-g12a-tohdmitx.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "amediatech,x96-air", "amlogic,sm1";</div><div class='add'>+	model = "Shenzhen Amediatech Technology Co., Ltd X96 Air";</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "amlogic,axg-sound-card";</div><div class='add'>+		model = "X96-AIR";</div><div class='add'>+		audio-aux-devs = &lt;&amp;tdmout_b&gt;;</div><div class='add'>+		audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",</div><div class='add'>+				"TDMOUT_B IN 1", "FRDDR_B OUT 1",</div><div class='add'>+				"TDMOUT_B IN 2", "FRDDR_C OUT 1",</div><div class='add'>+				"TDM_B Playback", "TDMOUT_B OUT";</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+			 &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;clkc CLKID_MPLL2&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL0&gt;,</div><div class='add'>+				  &lt;&amp;clkc CLKID_MPLL1&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;294912000&gt;,</div><div class='add'>+				       &lt;270950400&gt;,</div><div class='add'>+				       &lt;393216000&gt;;</div><div class='add'>+</div><div class='add'>+		dai-link-0 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_a&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-1 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_b&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dai-link-2 {</div><div class='add'>+			sound-dai = &lt;&amp;frddr_c&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* 8ch hdmi interface */</div><div class='add'>+		dai-link-3 {</div><div class='add'>+			sound-dai = &lt;&amp;tdmif_b&gt;;</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			dai-tdm-slot-tx-mask-0 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-1 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-2 = &lt;1 1&gt;;</div><div class='add'>+			dai-tdm-slot-tx-mask-3 = &lt;1 1&gt;;</div><div class='add'>+			mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_IN_B&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* hdmi glue */</div><div class='add'>+		dai-link-4 {</div><div class='add'>+			sound-dai = &lt;&amp;tohdmitx TOHDMITX_I2S_OUT&gt;;</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;hdmi_tx&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;arb {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;clkc_audio {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethmac {</div><div class='add'>+	status = "okay";</div><div class='add'>+	phy-handle = &lt;&amp;internal_ephy&gt;;</div><div class='add'>+	phy-mode = "rmii";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_a {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;frddr_c {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ir {</div><div class='add'>+	linux,rc-map-name = "rc-beelink-gs1";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmif_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tdmout_b {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tohdmitx {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi<br/>index d4ec735fb1a5..e5db8ce94062 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/amlogic/meson-sm1.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/amlogic/meson-sm1.dtsi</a></div><div class='hunk'>@@ -17,10 +17,10 @@</div><div class='ctx'> 		compatible = "amlogic,axg-tdm-iface";</div><div class='ctx'> 		#sound-dai-cells = &lt;0&gt;;</div><div class='ctx'> 		sound-name-prefix = "TDM_A";</div><div class='del'>-		clocks = &lt;&amp;clkc_audio AUD_CLKID_MST_A_MCLK&gt;,</div><div class='del'>-			 &lt;&amp;clkc_audio AUD_CLKID_MST_A_SCLK&gt;,</div><div class='del'>-			 &lt;&amp;clkc_audio AUD_CLKID_MST_A_LRCLK&gt;;</div><div class='del'>-		clock-names = "mclk", "sclk", "lrclk";</div><div class='add'>+		clocks = &lt;&amp;clkc_audio AUD_CLKID_MST_A_SCLK&gt;,</div><div class='add'>+			 &lt;&amp;clkc_audio AUD_CLKID_MST_A_LRCLK&gt;,</div><div class='add'>+			 &lt;&amp;clkc_audio AUD_CLKID_MST_A_MCLK&gt;;</div><div class='add'>+		clock-names = "sclk", "lrclk", "mclk";</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -28,10 +28,10 @@</div><div class='ctx'> 		compatible = "amlogic,axg-tdm-iface";</div><div class='ctx'> 		#sound-dai-cells = &lt;0&gt;;</div><div class='ctx'> 		sound-name-prefix = "TDM_B";</div><div class='del'>-		clocks = &lt;&amp;clkc_audio AUD_CLKID_MST_B_MCLK&gt;,</div><div class='del'>-			 &lt;&amp;clkc_audio AUD_CLKID_MST_B_SCLK&gt;,</div><div class='del'>-			 &lt;&amp;clkc_audio AUD_CLKID_MST_B_LRCLK&gt;;</div><div class='del'>-		clock-names = "mclk", "sclk", "lrclk";</div><div class='add'>+		clocks = &lt;&amp;clkc_audio AUD_CLKID_MST_B_SCLK&gt;,</div><div class='add'>+			 &lt;&amp;clkc_audio AUD_CLKID_MST_B_LRCLK&gt;,</div><div class='add'>+			 &lt;&amp;clkc_audio AUD_CLKID_MST_B_MCLK&gt;;</div><div class='add'>+		clock-names = "sclk", "lrclk", "mclk";</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -39,10 +39,10 @@</div><div class='ctx'> 		compatible = "amlogic,axg-tdm-iface";</div><div class='ctx'> 		#sound-dai-cells = &lt;0&gt;;</div><div class='ctx'> 		sound-name-prefix = "TDM_C";</div><div class='del'>-		clocks = &lt;&amp;clkc_audio AUD_CLKID_MST_C_MCLK&gt;,</div><div class='del'>-			 &lt;&amp;clkc_audio AUD_CLKID_MST_C_SCLK&gt;,</div><div class='del'>-			 &lt;&amp;clkc_audio AUD_CLKID_MST_C_LRCLK&gt;;</div><div class='del'>-		clock-names = "mclk", "sclk", "lrclk";</div><div class='add'>+		clocks = &lt;&amp;clkc_audio AUD_CLKID_MST_C_SCLK&gt;,</div><div class='add'>+			 &lt;&amp;clkc_audio AUD_CLKID_MST_C_LRCLK&gt;,</div><div class='add'>+			 &lt;&amp;clkc_audio AUD_CLKID_MST_C_MCLK&gt;;</div><div class='add'>+		clock-names = "sclk", "lrclk", "mclk";</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -55,7 +55,14 @@</div><div class='ctx'> 			compatible = "arm,cortex-a55";</div><div class='ctx'> 			reg = &lt;0x0 0x0&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			d-cache-line-size = &lt;32&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-sets = &lt;32&gt;;</div><div class='add'>+			i-cache-line-size = &lt;32&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-sets = &lt;32&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;l2&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu1: cpu@1 {</div><div class='hunk'>@@ -63,7 +70,14 @@</div><div class='ctx'> 			compatible = "arm,cortex-a55";</div><div class='ctx'> 			reg = &lt;0x0 0x1&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			d-cache-line-size = &lt;32&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-sets = &lt;32&gt;;</div><div class='add'>+			i-cache-line-size = &lt;32&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-sets = &lt;32&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;l2&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu2: cpu@2 {</div><div class='hunk'>@@ -71,7 +85,14 @@</div><div class='ctx'> 			compatible = "arm,cortex-a55";</div><div class='ctx'> 			reg = &lt;0x0 0x2&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			d-cache-line-size = &lt;32&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-sets = &lt;32&gt;;</div><div class='add'>+			i-cache-line-size = &lt;32&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-sets = &lt;32&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;l2&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu3: cpu@3 {</div><div class='hunk'>@@ -79,11 +100,23 @@</div><div class='ctx'> 			compatible = "arm,cortex-a55";</div><div class='ctx'> 			reg = &lt;0x0 0x3&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			d-cache-line-size = &lt;32&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-sets = &lt;32&gt;;</div><div class='add'>+			i-cache-line-size = &lt;32&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-sets = &lt;32&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;l2&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		l2: l2-cache0 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x40000&gt;; /* L2. 256 KB */</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;256&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -91,29 +124,10 @@</div><div class='ctx'> 		compatible = "operating-points-v2";</div><div class='ctx'> 		opp-shared;</div><div class='ctx'> </div><div class='del'>-		opp-100000000 {</div><div class='del'>-			opp-hz = /bits/ 64 &lt;100000000&gt;;</div><div class='del'>-			opp-microvolt = &lt;730000&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		opp-250000000 {</div><div class='del'>-			opp-hz = /bits/ 64 &lt;250000000&gt;;</div><div class='del'>-			opp-microvolt = &lt;730000&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		opp-500000000 {</div><div class='del'>-			opp-hz = /bits/ 64 &lt;500000000&gt;;</div><div class='del'>-			opp-microvolt = &lt;730000&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		opp-667000000 {</div><div class='del'>-			opp-hz = /bits/ 64 &lt;666666666&gt;;</div><div class='del'>-			opp-microvolt = &lt;750000&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='ctx'> 		opp-1000000000 {</div><div class='ctx'> 			opp-hz = /bits/ 64 &lt;1000000000&gt;;</div><div class='ctx'> 			opp-microvolt = &lt;770000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;50000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		opp-1200000000 {</div><div class='hunk'>@@ -126,7 +140,7 @@</div><div class='ctx'> 			opp-microvolt = &lt;790000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		opp-1512000000 {</div><div class='add'>+		opp-1500000000 {</div><div class='ctx'> 			opp-hz = /bits/ 64 &lt;1500000000&gt;;</div><div class='ctx'> 			opp-microvolt = &lt;800000&gt;;</div><div class='ctx'> 		};</div><div class='hunk'>@@ -289,8 +303,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		tdmin_a: audio-controller@300 {</div><div class='del'>-			compatible = "amlogic,sm1-tdmin",</div><div class='del'>-				     "amlogic,axg-tdmin";</div><div class='add'>+			compatible = "amlogic,sm1-tdmin";</div><div class='ctx'> 			reg = &lt;0x0 0x300 0x0 0x40&gt;;</div><div class='ctx'> 			sound-name-prefix = "TDMIN_A";</div><div class='ctx'> 			resets = &lt;&amp;clkc_audio AUD_RESET_TDMIN_A&gt;;</div><div class='hunk'>@@ -305,8 +318,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		tdmin_b: audio-controller@340 {</div><div class='del'>-			compatible = "amlogic,sm1-tdmin",</div><div class='del'>-				     "amlogic,axg-tdmin";</div><div class='add'>+			compatible = "amlogic,sm1-tdmin";</div><div class='ctx'> 			reg = &lt;0x0 0x340 0x0 0x40&gt;;</div><div class='ctx'> 			sound-name-prefix = "TDMIN_B";</div><div class='ctx'> 			resets = &lt;&amp;clkc_audio AUD_RESET_TDMIN_B&gt;;</div><div class='hunk'>@@ -321,8 +333,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		tdmin_c: audio-controller@380 {</div><div class='del'>-			compatible = "amlogic,sm1-tdmin",</div><div class='del'>-				     "amlogic,axg-tdmin";</div><div class='add'>+			compatible = "amlogic,sm1-tdmin";</div><div class='ctx'> 			reg = &lt;0x0 0x380 0x0 0x40&gt;;</div><div class='ctx'> 			sound-name-prefix = "TDMIN_C";</div><div class='ctx'> 			resets = &lt;&amp;clkc_audio AUD_RESET_TDMIN_C&gt;;</div><div class='hunk'>@@ -337,8 +348,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		tdmin_lb: audio-controller@3c0 {</div><div class='del'>-			compatible = "amlogic,sm1-tdmin",</div><div class='del'>-				     "amlogic,axg-tdmin";</div><div class='add'>+			compatible = "amlogic,sm1-tdmin";</div><div class='ctx'> 			reg = &lt;0x0 0x3c0 0x0 0x40&gt;;</div><div class='ctx'> 			sound-name-prefix = "TDMIN_LB";</div><div class='ctx'> 			resets = &lt;&amp;clkc_audio AUD_RESET_TDMIN_LB&gt;;</div><div class='hunk'>@@ -352,6 +362,33 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		spdifin: audio-controller@400 {</div><div class='add'>+			compatible = "amlogic,sm1-spdifin",</div><div class='add'>+				     "amlogic,axg-spdifin";</div><div class='add'>+			reg = &lt;0x0 0x400 0x0 0x30&gt;;</div><div class='add'>+			#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+			sound-name-prefix = "SPDIFIN";</div><div class='add'>+			interrupts = &lt;GIC_SPI 151 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkc_audio AUD_CLKID_SPDIFIN&gt;,</div><div class='add'>+			&lt;&amp;clkc_audio AUD_CLKID_SPDIFIN_CLK&gt;;</div><div class='add'>+			clock-names = "pclk", "refclk";</div><div class='add'>+			resets = &lt;&amp;clkc_audio AUD_RESET_SPDIFIN&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spdifout_a: audio-controller@480 {</div><div class='add'>+			compatible = "amlogic,sm1-spdifout",</div><div class='add'>+				     "amlogic,axg-spdifout";</div><div class='add'>+			reg = &lt;0x0 0x480 0x0 0x50&gt;;</div><div class='add'>+			#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+			sound-name-prefix = "SPDIFOUT_A";</div><div class='add'>+			clocks = &lt;&amp;clkc_audio AUD_CLKID_SPDIFOUT&gt;,</div><div class='add'>+			&lt;&amp;clkc_audio AUD_CLKID_SPDIFOUT_CLK&gt;;</div><div class='add'>+			clock-names = "pclk", "mclk";</div><div class='add'>+			resets = &lt;&amp;clkc_audio AUD_RESET_SPDIFOUT&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		tdmout_a: audio-controller@500 {</div><div class='ctx'> 			compatible = "amlogic,sm1-tdmout";</div><div class='ctx'> 			reg = &lt;0x0 0x500 0x0 0x40&gt;;</div><div class='hunk'>@@ -397,6 +434,16 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		toacodec: audio-controller@740 {</div><div class='add'>+			compatible = "amlogic,sm1-toacodec",</div><div class='add'>+				     "amlogic,g12a-toacodec";</div><div class='add'>+			reg = &lt;0x0 0x740 0x0 0x4&gt;;</div><div class='add'>+			#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+			sound-name-prefix = "TOACODEC";</div><div class='add'>+			resets = &lt;&amp;clkc_audio AUD_RESET_TOACODEC&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		tohdmitx: audio-controller@744 {</div><div class='ctx'> 			compatible = "amlogic,sm1-tohdmitx",</div><div class='ctx'> 				     "amlogic,g12a-tohdmitx";</div><div class='hunk'>@@ -466,6 +513,26 @@</div><div class='ctx'> 	compatible = "amlogic,sm1-clkc";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;cpu_thermal {</div><div class='add'>+	cooling-maps {</div><div class='add'>+		map0 {</div><div class='add'>+			trip = &lt;&amp;cpu_passive&gt;;</div><div class='add'>+			cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+					&lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+					&lt;&amp;cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+					&lt;&amp;cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		map1 {</div><div class='add'>+			trip = &lt;&amp;cpu_hot&gt;;</div><div class='add'>+			cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+					&lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+					&lt;&amp;cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+					&lt;&amp;cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;ethmac {</div><div class='ctx'> 	power-domains = &lt;&amp;pwrc PWRC_SM1_ETH_ID&gt;;</div><div class='ctx'> };</div><div class='hunk'>@@ -475,10 +542,18 @@</div><div class='ctx'> 		     "amlogic,meson-gpio-intc";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	power-domains = &lt;&amp;pwrc PWRC_SM1_VPU_ID&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;pcie {</div><div class='ctx'> 	power-domains = &lt;&amp;pwrc PWRC_SM1_PCIE_ID&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;pmu {</div><div class='add'>+	compatible = "amlogic,sm1-ddr-pmu";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;pwrc {</div><div class='ctx'> 	compatible = "amlogic,meson-sm1-pwrc";</div><div class='ctx'> };</div><div class='hunk'>@@ -502,3 +577,7 @@</div><div class='ctx'> &amp;usb {</div><div class='ctx'> 	power-domains = &lt;&amp;pwrc PWRC_SM1_USB_ID&gt;;</div><div class='ctx'> };</div><div class='add'>+</div><div class='add'>+&amp;npu {</div><div class='add'>+	power-domains = &lt;&amp;pwrc PWRC_SM1_NNA_ID&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apm/apm-merlin.dts b/arch/arm64/boot/dts/apm/apm-merlin.dts<br/>index 217d7728b63a..b1160780a2a6 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apm/apm-merlin.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apm/apm-merlin.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apm/apm-merlin.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apm/apm-merlin.dts</a></div><div class='hunk'>@@ -15,14 +15,14 @@</div><div class='ctx'> </div><div class='ctx'> 	chosen { };</div><div class='ctx'> </div><div class='del'>-	memory {</div><div class='add'>+	memory@100000000 {</div><div class='ctx'> 		device_type = "memory";</div><div class='ctx'> 		reg = &lt; 0x1 0x00000000 0x0 0x80000000 &gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	gpio-keys {</div><div class='ctx'> 		compatible = "gpio-keys";</div><div class='del'>-		button@1 {</div><div class='add'>+		button {</div><div class='ctx'> 			label = "POWER";</div><div class='ctx'> 			linux,code = &lt;116&gt;;</div><div class='ctx'> 			linux,input-type = &lt;0x1&gt;;</div><div class='hunk'>@@ -32,7 +32,7 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	poweroff_mbox: poweroff_mbox@10548000 {</div><div class='del'>-		compatible = "syscon";</div><div class='add'>+		compatible = "apm,merlin-poweroff-mailbox", "syscon";</div><div class='ctx'> 		reg = &lt;0x0 0x10548000 0x0 0x30&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -45,38 +45,38 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;serial0 {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;sata1 {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;sata2 {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;sata3 {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;sgenet0 {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;xgenet1 {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;mmc0 {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;i2c4 {</div><div class='ctx'> 	rtc68: rtc@68 {</div><div class='ctx'> 		compatible = "dallas,ds1337";</div><div class='ctx'> 		reg = &lt;0x68&gt;;</div><div class='del'>-		status = "ok";</div><div class='add'>+		status = "okay";</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/arch/arm64/boot/dts/apm/apm-mustang.dts b/arch/arm64/boot/dts/apm/apm-mustang.dts<br/>index e927811ade28..2ef658796746 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apm/apm-mustang.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apm/apm-mustang.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apm/apm-mustang.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apm/apm-mustang.dts</a></div><div class='hunk'>@@ -15,14 +15,14 @@</div><div class='ctx'> </div><div class='ctx'> 	chosen { };</div><div class='ctx'> </div><div class='del'>-	memory {</div><div class='add'>+	memory@100000000 {</div><div class='ctx'> 		device_type = "memory";</div><div class='ctx'> 		reg = &lt; 0x1 0x00000000 0x0 0x80000000 &gt;; /* Updated by bootloader */</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	gpio-keys {</div><div class='ctx'> 		compatible = "gpio-keys";</div><div class='del'>-		button@1 {</div><div class='add'>+		button {</div><div class='ctx'> 			label = "POWER";</div><div class='ctx'> 			linux,code = &lt;116&gt;;</div><div class='ctx'> 			linux,input-type = &lt;0x1&gt;;</div><div class='hunk'>@@ -32,7 +32,7 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	poweroff_mbox: poweroff_mbox@10548000 {</div><div class='del'>-		compatible = "syscon";</div><div class='add'>+		compatible = "apm,mustang-poweroff-mailbox", "syscon";</div><div class='ctx'> 		reg = &lt;0x0 0x10548000 0x0 0x30&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -45,36 +45,36 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;pcie0clk {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;pcie0 {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;serial0 {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;menet {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;sgenet0 {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;sgenet1 {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;xgenet {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> 	rxlos-gpios = &lt;&amp;sbgpio 12 1&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;mmc0 {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;mdio {</div><div class='head'>diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi<br/>index 3feb1881bbc2..5bbedb0a7107 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apm/apm-shadowcat.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apm/apm-shadowcat.dtsi</a></div><div class='hunk'>@@ -22,7 +22,6 @@</div><div class='ctx'> 			enable-method = "spin-table";</div><div class='ctx'> 			cpu-release-addr = &lt;0x1 0x0000fff8&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;xgene_L2_0&gt;;</div><div class='del'>-			#clock-cells = &lt;1&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;pmd0clk 0&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 		cpu@1 {</div><div class='hunk'>@@ -32,7 +31,6 @@</div><div class='ctx'> 			enable-method = "spin-table";</div><div class='ctx'> 			cpu-release-addr = &lt;0x1 0x0000fff8&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;xgene_L2_0&gt;;</div><div class='del'>-			#clock-cells = &lt;1&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;pmd0clk 0&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 		cpu@100 {</div><div class='hunk'>@@ -42,7 +40,6 @@</div><div class='ctx'> 			enable-method = "spin-table";</div><div class='ctx'> 			cpu-release-addr = &lt;0x1 0x0000fff8&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;xgene_L2_1&gt;;</div><div class='del'>-			#clock-cells = &lt;1&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;pmd1clk 0&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 		cpu@101 {</div><div class='hunk'>@@ -52,7 +49,6 @@</div><div class='ctx'> 			enable-method = "spin-table";</div><div class='ctx'> 			cpu-release-addr = &lt;0x1 0x0000fff8&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;xgene_L2_1&gt;;</div><div class='del'>-			#clock-cells = &lt;1&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;pmd1clk 0&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 		cpu@200 {</div><div class='hunk'>@@ -62,7 +58,6 @@</div><div class='ctx'> 			enable-method = "spin-table";</div><div class='ctx'> 			cpu-release-addr = &lt;0x1 0x0000fff8&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;xgene_L2_2&gt;;</div><div class='del'>-			#clock-cells = &lt;1&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;pmd2clk 0&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 		cpu@201 {</div><div class='hunk'>@@ -72,7 +67,6 @@</div><div class='ctx'> 			enable-method = "spin-table";</div><div class='ctx'> 			cpu-release-addr = &lt;0x1 0x0000fff8&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;xgene_L2_2&gt;;</div><div class='del'>-			#clock-cells = &lt;1&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;pmd2clk 0&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 		cpu@300 {</div><div class='hunk'>@@ -82,7 +76,6 @@</div><div class='ctx'> 			enable-method = "spin-table";</div><div class='ctx'> 			cpu-release-addr = &lt;0x1 0x0000fff8&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;xgene_L2_3&gt;;</div><div class='del'>-			#clock-cells = &lt;1&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;pmd3clk 0&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 		cpu@301 {</div><div class='hunk'>@@ -92,20 +85,27 @@</div><div class='ctx'> 			enable-method = "spin-table";</div><div class='ctx'> 			cpu-release-addr = &lt;0x1 0x0000fff8&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;xgene_L2_3&gt;;</div><div class='del'>-			#clock-cells = &lt;1&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;pmd3clk 0&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 		xgene_L2_0: l2-cache-0 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> 		xgene_L2_1: l2-cache-1 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> 		xgene_L2_2: l2-cache-2 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> 		xgene_L2_3: l2-cache-3 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -203,6 +203,13 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	refclk: clock-100000000 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;100000000&gt;;</div><div class='add'>+		clock-output-names = "refclk";</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	pmu {</div><div class='ctx'> 		compatible = "arm,armv8-pmuv3";</div><div class='ctx'> 		interrupts = &lt;1 12 0xff04&gt;;</div><div class='hunk'>@@ -217,6 +224,16 @@</div><div class='ctx'> 		clock-frequency = &lt;50000000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	i2cslimpro {</div><div class='add'>+		compatible = "apm,xgene-slimpro-i2c";</div><div class='add'>+		mboxes = &lt;&amp;mailbox 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hwmonslimpro {</div><div class='add'>+		compatible = "apm,xgene-slimpro-hwmon";</div><div class='add'>+		mboxes = &lt;&amp;mailbox 7&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	soc {</div><div class='ctx'> 		compatible = "simple-bus";</div><div class='ctx'> 		#address-cells = &lt;2&gt;;</div><div class='hunk'>@@ -228,17 +245,10 @@</div><div class='ctx'> 			#size-cells = &lt;2&gt;;</div><div class='ctx'> 			ranges;</div><div class='ctx'> </div><div class='del'>-			refclk: refclk {</div><div class='del'>-				compatible = "fixed-clock";</div><div class='del'>-				#clock-cells = &lt;1&gt;;</div><div class='del'>-				clock-frequency = &lt;100000000&gt;;</div><div class='del'>-				clock-output-names = "refclk";</div><div class='del'>-			};</div><div class='del'>-</div><div class='ctx'> 			pmdpll: pmdpll@170000f0 {</div><div class='ctx'> 				compatible = "apm,xgene-pcppll-v2-clock";</div><div class='ctx'> 				#clock-cells = &lt;1&gt;;</div><div class='del'>-				clocks = &lt;&amp;refclk 0&gt;;</div><div class='add'>+				clocks = &lt;&amp;refclk&gt;;</div><div class='ctx'> 				reg = &lt;0x0 0x170000f0 0x0 0x10&gt;;</div><div class='ctx'> 				clock-output-names = "pmdpll";</div><div class='ctx'> 			};</div><div class='hunk'>@@ -278,7 +288,7 @@</div><div class='ctx'> 			socpll: socpll@17000120 {</div><div class='ctx'> 				compatible = "apm,xgene-socpll-v2-clock";</div><div class='ctx'> 				#clock-cells = &lt;1&gt;;</div><div class='del'>-				clocks = &lt;&amp;refclk 0&gt;;</div><div class='add'>+				clocks = &lt;&amp;refclk&gt;;</div><div class='ctx'> 				reg = &lt;0x0 0x17000120 0x0 0x1000&gt;;</div><div class='ctx'> 				clock-output-names = "socpll";</div><div class='ctx'> 			};</div><div class='hunk'>@@ -577,18 +587,7 @@</div><div class='ctx'> 					0x0 0x7 0x4&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		i2cslimpro {</div><div class='del'>-			compatible = "apm,xgene-slimpro-i2c";</div><div class='del'>-			mboxes = &lt;&amp;mailbox 0&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		hwmonslimpro {</div><div class='del'>-			compatible = "apm,xgene-slimpro-hwmon";</div><div class='del'>-			mboxes = &lt;&amp;mailbox 7&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='ctx'> 		serial0: serial@10600000 {</div><div class='del'>-			device_type = "serial";</div><div class='ctx'> 			compatible = "ns16550";</div><div class='ctx'> 			reg = &lt;0 0x10600000 0x0 0x1000&gt;;</div><div class='ctx'> 			reg-shift = &lt;2&gt;;</div><div class='hunk'>@@ -597,11 +596,11 @@</div><div class='ctx'> 			interrupts = &lt;0x0 0x4c 0x4&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		/* Do not change dwusb name, coded for backward compatibility */</div><div class='del'>-		usb0: dwusb@19000000 {</div><div class='add'>+		/* Node-name might need to be coded as dwusb for backward compatibility */</div><div class='add'>+		usb0: usb@19000000 {</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 			compatible = "snps,dwc3";</div><div class='del'>-			reg =  &lt;0x0 0x19000000 0x0 0x100000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x19000000 0x0 0x100000&gt;;</div><div class='ctx'> 			interrupts = &lt;0x0 0x5d 0x4&gt;;</div><div class='ctx'> 			dma-coherent;</div><div class='ctx'> 			dr_mode = "host";</div><div class='hunk'>@@ -610,7 +609,7 @@</div><div class='ctx'> 		pcie0: pcie@1f2b0000 {</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 			device_type = "pci";</div><div class='del'>-			compatible = "apm,xgene-pcie", "apm,xgene2-pcie";</div><div class='add'>+			compatible = "apm,xgene-pcie";</div><div class='ctx'> 			#interrupt-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;2&gt;;</div><div class='ctx'> 			#address-cells = &lt;3&gt;;</div><div class='hunk'>@@ -636,7 +635,7 @@</div><div class='ctx'> 		pcie1: pcie@1f2c0000 {</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 			device_type = "pci";</div><div class='del'>-			compatible = "apm,xgene-pcie", "apm,xgene2-pcie";</div><div class='add'>+			compatible = "apm,xgene-pcie";</div><div class='ctx'> 			#interrupt-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;2&gt;;</div><div class='ctx'> 			#address-cells = &lt;3&gt;;</div><div class='hunk'>@@ -709,19 +708,19 @@</div><div class='ctx'> 		dwgpio: gpio@1c024000 {</div><div class='ctx'> 			compatible = "snps,dw-apb-gpio";</div><div class='ctx'> 			reg = &lt;0x0 0x1c024000 0x0 0x1000&gt;;</div><div class='del'>-			reg-io-width = &lt;4&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> </div><div class='ctx'> 			porta: gpio-controller@0 {</div><div class='ctx'> 				compatible = "snps,dw-apb-gpio-port";</div><div class='ctx'> 				gpio-controller;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='ctx'> 				snps,nr-gpios = &lt;32&gt;;</div><div class='ctx'> 				reg = &lt;0&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		sbgpio: gpio@17001000{</div><div class='add'>+		sbgpio: gpio@17001000 {</div><div class='ctx'> 			compatible = "apm,xgene-gpio-sb";</div><div class='ctx'> 			reg = &lt;0x0 0x17001000 0x0 0x400&gt;;</div><div class='ctx'> 			#gpio-cells = &lt;2&gt;;</div><div class='hunk'>@@ -802,7 +801,6 @@</div><div class='ctx'> 			interrupts = &lt;0 0x45 0x4&gt;;</div><div class='ctx'> 			#clock-cells = &lt;1&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;sbapbclk 0&gt;;</div><div class='del'>-			bus_num = &lt;1&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		i2c4: i2c@10640000 {</div><div class='hunk'>@@ -812,7 +810,6 @@</div><div class='ctx'> 			reg = &lt;0x0 0x10640000 0x0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;0 0x3a 0x4&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;i2c4clk 0&gt;;</div><div class='del'>-			bus_num = &lt;4&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi<br/>index 8c802d87e751..4ca0ead120c1 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apm/apm-storm.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/apm/apm-storm.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apm/apm-storm.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apm/apm-storm.dtsi</a></div><div class='hunk'>@@ -81,20 +81,29 @@</div><div class='ctx'> 		};</div><div class='ctx'> 		xgene_L2_0: l2-cache-0 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> 		xgene_L2_1: l2-cache-1 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> 		xgene_L2_2: l2-cache-2 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> 		xgene_L2_3: l2-cache-3 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	gic: interrupt-controller@78010000 {</div><div class='ctx'> 		compatible = "arm,cortex-a15-gic";</div><div class='add'>+		#address-cells = &lt;0&gt;;</div><div class='ctx'> 		#interrupt-cells = &lt;3&gt;;</div><div class='ctx'> 		interrupt-controller;</div><div class='ctx'> 		reg = &lt;0x0 0x78010000 0x0 0x1000&gt;,	/* GIC Dist */</div><div class='hunk'>@@ -104,6 +113,13 @@</div><div class='ctx'> 		interrupts = &lt;1 9 0xf04&gt;;	/* GIC Maintenence IRQ */</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	refclk: clock-100000000 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;100000000&gt;;</div><div class='add'>+		clock-output-names = "refclk";</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	timer {</div><div class='ctx'> 		compatible = "arm,armv8-timer";</div><div class='ctx'> 		interrupts = &lt;1 0 0xff08&gt;,	/* Secure Phys IRQ */</div><div class='hunk'>@@ -114,10 +130,20 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	pmu {</div><div class='del'>-		compatible = "apm,potenza-pmu", "arm,armv8-pmuv3";</div><div class='add'>+		compatible = "apm,potenza-pmu";</div><div class='ctx'> 		interrupts = &lt;1 12 0xff04&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	i2cslimpro {</div><div class='add'>+		compatible = "apm,xgene-slimpro-i2c";</div><div class='add'>+		mboxes = &lt;&amp;mailbox 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hwmonslimpro {</div><div class='add'>+		compatible = "apm,xgene-slimpro-hwmon";</div><div class='add'>+		mboxes = &lt;&amp;mailbox 7&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	soc {</div><div class='ctx'> 		compatible = "simple-bus";</div><div class='ctx'> 		#address-cells = &lt;2&gt;;</div><div class='hunk'>@@ -129,38 +155,29 @@</div><div class='ctx'> 			#address-cells = &lt;2&gt;;</div><div class='ctx'> 			#size-cells = &lt;2&gt;;</div><div class='ctx'> 			ranges;</div><div class='del'>-			refclk: refclk {</div><div class='del'>-				compatible = "fixed-clock";</div><div class='del'>-				#clock-cells = &lt;1&gt;;</div><div class='del'>-				clock-frequency = &lt;100000000&gt;;</div><div class='del'>-				clock-output-names = "refclk";</div><div class='del'>-			};</div><div class='ctx'> </div><div class='ctx'> 			pcppll: pcppll@17000100 {</div><div class='ctx'> 				compatible = "apm,xgene-pcppll-clock";</div><div class='ctx'> 				#clock-cells = &lt;1&gt;;</div><div class='del'>-				clocks = &lt;&amp;refclk 0&gt;;</div><div class='add'>+				clocks = &lt;&amp;refclk&gt;;</div><div class='ctx'> 				clock-names = "pcppll";</div><div class='ctx'> 				reg = &lt;0x0 0x17000100 0x0 0x1000&gt;;</div><div class='ctx'> 				clock-output-names = "pcppll";</div><div class='del'>-				type = &lt;0&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			socpll: socpll@17000120 {</div><div class='ctx'> 				compatible = "apm,xgene-socpll-clock";</div><div class='ctx'> 				#clock-cells = &lt;1&gt;;</div><div class='del'>-				clocks = &lt;&amp;refclk 0&gt;;</div><div class='add'>+				clocks = &lt;&amp;refclk&gt;;</div><div class='ctx'> 				clock-names = "socpll";</div><div class='ctx'> 				reg = &lt;0x0 0x17000120 0x0 0x1000&gt;;</div><div class='ctx'> 				clock-output-names = "socpll";</div><div class='del'>-				type = &lt;1&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			socplldiv2: socplldiv2  {</div><div class='ctx'> 				compatible = "fixed-factor-clock";</div><div class='del'>-				#clock-cells = &lt;1&gt;;</div><div class='add'>+				#clock-cells = &lt;0&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;socpll 0&gt;;</div><div class='del'>-				clock-names = "socplldiv2";</div><div class='ctx'> 				clock-mult = &lt;1&gt;;</div><div class='ctx'> 				clock-div = &lt;2&gt;;</div><div class='ctx'> 				clock-output-names = "socplldiv2";</div><div class='hunk'>@@ -169,7 +186,7 @@</div><div class='ctx'> 			ahbclk: ahbclk@17000000 {</div><div class='ctx'> 				compatible = "apm,xgene-device-clock";</div><div class='ctx'> 				#clock-cells = &lt;1&gt;;</div><div class='del'>-				clocks = &lt;&amp;socplldiv2 0&gt;;</div><div class='add'>+				clocks = &lt;&amp;socplldiv2&gt;;</div><div class='ctx'> 				reg = &lt;0x0 0x17000000 0x0 0x2000&gt;;</div><div class='ctx'> 				reg-names = "div-reg";</div><div class='ctx'> 				divider-offset = &lt;0x164&gt;;</div><div class='hunk'>@@ -181,7 +198,7 @@</div><div class='ctx'> 			sdioclk: sdioclk@1f2ac000 {</div><div class='ctx'> 				compatible = "apm,xgene-device-clock";</div><div class='ctx'> 				#clock-cells = &lt;1&gt;;</div><div class='del'>-				clocks = &lt;&amp;socplldiv2 0&gt;;</div><div class='add'>+				clocks = &lt;&amp;socplldiv2&gt;;</div><div class='ctx'> 				reg = &lt;0x0 0x1f2ac000 0x0 0x1000</div><div class='ctx'> 					0x0 0x17000000 0x0 0x2000&gt;;</div><div class='ctx'> 				reg-names = "csr-reg", "div-reg";</div><div class='hunk'>@@ -198,7 +215,7 @@</div><div class='ctx'> 			ethclk: ethclk {</div><div class='ctx'> 				compatible = "apm,xgene-device-clock";</div><div class='ctx'> 				#clock-cells = &lt;1&gt;;</div><div class='del'>-				clocks = &lt;&amp;socplldiv2 0&gt;;</div><div class='add'>+				clocks = &lt;&amp;socplldiv2&gt;;</div><div class='ctx'> 				clock-names = "ethclk";</div><div class='ctx'> 				reg = &lt;0x0 0x17000000 0x0 0x1000&gt;;</div><div class='ctx'> 				reg-names = "div-reg";</div><div class='hunk'>@@ -220,7 +237,7 @@</div><div class='ctx'> 			sge0clk: sge0clk@1f21c000 {</div><div class='ctx'> 				compatible = "apm,xgene-device-clock";</div><div class='ctx'> 				#clock-cells = &lt;1&gt;;</div><div class='del'>-				clocks = &lt;&amp;socplldiv2 0&gt;;</div><div class='add'>+				clocks = &lt;&amp;socplldiv2&gt;;</div><div class='ctx'> 				reg = &lt;0x0 0x1f21c000 0x0 0x1000&gt;;</div><div class='ctx'> 				reg-names = "csr-reg";</div><div class='ctx'> 				csr-mask = &lt;0xa&gt;;</div><div class='hunk'>@@ -231,7 +248,7 @@</div><div class='ctx'> 			xge0clk: xge0clk@1f61c000 {</div><div class='ctx'> 				compatible = "apm,xgene-device-clock";</div><div class='ctx'> 				#clock-cells = &lt;1&gt;;</div><div class='del'>-				clocks = &lt;&amp;socplldiv2 0&gt;;</div><div class='add'>+				clocks = &lt;&amp;socplldiv2&gt;;</div><div class='ctx'> 				reg = &lt;0x0 0x1f61c000 0x0 0x1000&gt;;</div><div class='ctx'> 				reg-names = "csr-reg";</div><div class='ctx'> 				csr-mask = &lt;0x3&gt;;</div><div class='hunk'>@@ -242,7 +259,7 @@</div><div class='ctx'> 				compatible = "apm,xgene-device-clock";</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 				#clock-cells = &lt;1&gt;;</div><div class='del'>-				clocks = &lt;&amp;socplldiv2 0&gt;;</div><div class='add'>+				clocks = &lt;&amp;socplldiv2&gt;;</div><div class='ctx'> 				reg = &lt;0x0 0x1f62c000 0x0 0x1000&gt;;</div><div class='ctx'> 				reg-names = "csr-reg";</div><div class='ctx'> 				csr-mask = &lt;0x3&gt;;</div><div class='hunk'>@@ -252,7 +269,7 @@</div><div class='ctx'> 			sataphy1clk: sataphy1clk@1f21c000 {</div><div class='ctx'> 				compatible = "apm,xgene-device-clock";</div><div class='ctx'> 				#clock-cells = &lt;1&gt;;</div><div class='del'>-				clocks = &lt;&amp;socplldiv2 0&gt;;</div><div class='add'>+				clocks = &lt;&amp;socplldiv2&gt;;</div><div class='ctx'> 				reg = &lt;0x0 0x1f21c000 0x0 0x1000&gt;;</div><div class='ctx'> 				reg-names = "csr-reg";</div><div class='ctx'> 				clock-output-names = "sataphy1clk";</div><div class='hunk'>@@ -266,11 +283,11 @@</div><div class='ctx'> 			sataphy2clk: sataphy1clk@1f22c000 {</div><div class='ctx'> 				compatible = "apm,xgene-device-clock";</div><div class='ctx'> 				#clock-cells = &lt;1&gt;;</div><div class='del'>-				clocks = &lt;&amp;socplldiv2 0&gt;;</div><div class='add'>+				clocks = &lt;&amp;socplldiv2&gt;;</div><div class='ctx'> 				reg = &lt;0x0 0x1f22c000 0x0 0x1000&gt;;</div><div class='ctx'> 				reg-names = "csr-reg";</div><div class='ctx'> 				clock-output-names = "sataphy2clk";</div><div class='del'>-				status = "ok";</div><div class='add'>+				status = "okay";</div><div class='ctx'> 				csr-offset = &lt;0x4&gt;;</div><div class='ctx'> 				csr-mask = &lt;0x3a&gt;;</div><div class='ctx'> 				enable-offset = &lt;0x0&gt;;</div><div class='hunk'>@@ -280,11 +297,11 @@</div><div class='ctx'> 			sataphy3clk: sataphy1clk@1f23c000 {</div><div class='ctx'> 				compatible = "apm,xgene-device-clock";</div><div class='ctx'> 				#clock-cells = &lt;1&gt;;</div><div class='del'>-				clocks = &lt;&amp;socplldiv2 0&gt;;</div><div class='add'>+				clocks = &lt;&amp;socplldiv2&gt;;</div><div class='ctx'> 				reg = &lt;0x0 0x1f23c000 0x0 0x1000&gt;;</div><div class='ctx'> 				reg-names = "csr-reg";</div><div class='ctx'> 				clock-output-names = "sataphy3clk";</div><div class='del'>-				status = "ok";</div><div class='add'>+				status = "okay";</div><div class='ctx'> 				csr-offset = &lt;0x4&gt;;</div><div class='ctx'> 				csr-mask = &lt;0x3a&gt;;</div><div class='ctx'> 				enable-offset = &lt;0x0&gt;;</div><div class='hunk'>@@ -294,7 +311,7 @@</div><div class='ctx'> 			sata01clk: sata01clk@1f21c000 {</div><div class='ctx'> 				compatible = "apm,xgene-device-clock";</div><div class='ctx'> 				#clock-cells = &lt;1&gt;;</div><div class='del'>-				clocks = &lt;&amp;socplldiv2 0&gt;;</div><div class='add'>+				clocks = &lt;&amp;socplldiv2&gt;;</div><div class='ctx'> 				reg = &lt;0x0 0x1f21c000 0x0 0x1000&gt;;</div><div class='ctx'> 				reg-names = "csr-reg";</div><div class='ctx'> 				clock-output-names = "sata01clk";</div><div class='hunk'>@@ -307,7 +324,7 @@</div><div class='ctx'> 			sata23clk: sata23clk@1f22c000 {</div><div class='ctx'> 				compatible = "apm,xgene-device-clock";</div><div class='ctx'> 				#clock-cells = &lt;1&gt;;</div><div class='del'>-				clocks = &lt;&amp;socplldiv2 0&gt;;</div><div class='add'>+				clocks = &lt;&amp;socplldiv2&gt;;</div><div class='ctx'> 				reg = &lt;0x0 0x1f22c000 0x0 0x1000&gt;;</div><div class='ctx'> 				reg-names = "csr-reg";</div><div class='ctx'> 				clock-output-names = "sata23clk";</div><div class='hunk'>@@ -320,7 +337,7 @@</div><div class='ctx'> 			sata45clk: sata45clk@1f23c000 {</div><div class='ctx'> 				compatible = "apm,xgene-device-clock";</div><div class='ctx'> 				#clock-cells = &lt;1&gt;;</div><div class='del'>-				clocks = &lt;&amp;socplldiv2 0&gt;;</div><div class='add'>+				clocks = &lt;&amp;socplldiv2&gt;;</div><div class='ctx'> 				reg = &lt;0x0 0x1f23c000 0x0 0x1000&gt;;</div><div class='ctx'> 				reg-names = "csr-reg";</div><div class='ctx'> 				clock-output-names = "sata45clk";</div><div class='hunk'>@@ -333,7 +350,7 @@</div><div class='ctx'> 			rtcclk: rtcclk@17000000 {</div><div class='ctx'> 				compatible = "apm,xgene-device-clock";</div><div class='ctx'> 				#clock-cells = &lt;1&gt;;</div><div class='del'>-				clocks = &lt;&amp;socplldiv2 0&gt;;</div><div class='add'>+				clocks = &lt;&amp;socplldiv2&gt;;</div><div class='ctx'> 				reg = &lt;0x0 0x17000000 0x0 0x2000&gt;;</div><div class='ctx'> 				reg-names = "csr-reg";</div><div class='ctx'> 				csr-offset = &lt;0xc&gt;;</div><div class='hunk'>@@ -346,7 +363,7 @@</div><div class='ctx'> 			rngpkaclk: rngpkaclk@17000000 {</div><div class='ctx'> 				compatible = "apm,xgene-device-clock";</div><div class='ctx'> 				#clock-cells = &lt;1&gt;;</div><div class='del'>-				clocks = &lt;&amp;socplldiv2 0&gt;;</div><div class='add'>+				clocks = &lt;&amp;socplldiv2&gt;;</div><div class='ctx'> 				reg = &lt;0x0 0x17000000 0x0 0x2000&gt;;</div><div class='ctx'> 				reg-names = "csr-reg";</div><div class='ctx'> 				csr-offset = &lt;0xc&gt;;</div><div class='hunk'>@@ -360,7 +377,7 @@</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 				compatible = "apm,xgene-device-clock";</div><div class='ctx'> 				#clock-cells = &lt;1&gt;;</div><div class='del'>-				clocks = &lt;&amp;socplldiv2 0&gt;;</div><div class='add'>+				clocks = &lt;&amp;socplldiv2&gt;;</div><div class='ctx'> 				reg = &lt;0x0 0x1f2bc000 0x0 0x1000&gt;;</div><div class='ctx'> 				reg-names = "csr-reg";</div><div class='ctx'> 				clock-output-names = "pcie0clk";</div><div class='hunk'>@@ -370,7 +387,7 @@</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 				compatible = "apm,xgene-device-clock";</div><div class='ctx'> 				#clock-cells = &lt;1&gt;;</div><div class='del'>-				clocks = &lt;&amp;socplldiv2 0&gt;;</div><div class='add'>+				clocks = &lt;&amp;socplldiv2&gt;;</div><div class='ctx'> 				reg = &lt;0x0 0x1f2cc000 0x0 0x1000&gt;;</div><div class='ctx'> 				reg-names = "csr-reg";</div><div class='ctx'> 				clock-output-names = "pcie1clk";</div><div class='hunk'>@@ -380,7 +397,7 @@</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 				compatible = "apm,xgene-device-clock";</div><div class='ctx'> 				#clock-cells = &lt;1&gt;;</div><div class='del'>-				clocks = &lt;&amp;socplldiv2 0&gt;;</div><div class='add'>+				clocks = &lt;&amp;socplldiv2&gt;;</div><div class='ctx'> 				reg = &lt;0x0 0x1f2dc000 0x0 0x1000&gt;;</div><div class='ctx'> 				reg-names = "csr-reg";</div><div class='ctx'> 				clock-output-names = "pcie2clk";</div><div class='hunk'>@@ -390,7 +407,7 @@</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 				compatible = "apm,xgene-device-clock";</div><div class='ctx'> 				#clock-cells = &lt;1&gt;;</div><div class='del'>-				clocks = &lt;&amp;socplldiv2 0&gt;;</div><div class='add'>+				clocks = &lt;&amp;socplldiv2&gt;;</div><div class='ctx'> 				reg = &lt;0x0 0x1f50c000 0x0 0x1000&gt;;</div><div class='ctx'> 				reg-names = "csr-reg";</div><div class='ctx'> 				clock-output-names = "pcie3clk";</div><div class='hunk'>@@ -400,7 +417,7 @@</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 				compatible = "apm,xgene-device-clock";</div><div class='ctx'> 				#clock-cells = &lt;1&gt;;</div><div class='del'>-				clocks = &lt;&amp;socplldiv2 0&gt;;</div><div class='add'>+				clocks = &lt;&amp;socplldiv2&gt;;</div><div class='ctx'> 				reg = &lt;0x0 0x1f51c000 0x0 0x1000&gt;;</div><div class='ctx'> 				reg-names = "csr-reg";</div><div class='ctx'> 				clock-output-names = "pcie4clk";</div><div class='hunk'>@@ -409,7 +426,7 @@</div><div class='ctx'> 			dmaclk: dmaclk@1f27c000 {</div><div class='ctx'> 				compatible = "apm,xgene-device-clock";</div><div class='ctx'> 				#clock-cells = &lt;1&gt;;</div><div class='del'>-				clocks = &lt;&amp;socplldiv2 0&gt;;</div><div class='add'>+				clocks = &lt;&amp;socplldiv2&gt;;</div><div class='ctx'> 				reg = &lt;0x0 0x1f27c000 0x0 0x1000&gt;;</div><div class='ctx'> 				reg-names = "csr-reg";</div><div class='ctx'> 				clock-output-names = "dmaclk";</div><div class='hunk'>@@ -751,19 +768,8 @@</div><div class='ctx'> 					&lt;0x0 0x7 0x4&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		i2cslimpro {</div><div class='del'>-			compatible = "apm,xgene-slimpro-i2c";</div><div class='del'>-			mboxes = &lt;&amp;mailbox 0&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		hwmonslimpro {</div><div class='del'>-			compatible = "apm,xgene-slimpro-hwmon";</div><div class='del'>-			mboxes = &lt;&amp;mailbox 7&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='ctx'> 		serial0: serial@1c020000 {</div><div class='ctx'> 			status = "disabled";</div><div class='del'>-			device_type = "serial";</div><div class='ctx'> 			compatible = "ns16550a";</div><div class='ctx'> 			reg = &lt;0 0x1c020000 0x0 0x1000&gt;;</div><div class='ctx'> 			reg-shift = &lt;2&gt;;</div><div class='hunk'>@@ -774,7 +780,6 @@</div><div class='ctx'> </div><div class='ctx'> 		serial1: serial@1c021000 {</div><div class='ctx'> 			status = "disabled";</div><div class='del'>-			device_type = "serial";</div><div class='ctx'> 			compatible = "ns16550a";</div><div class='ctx'> 			reg = &lt;0 0x1c021000 0x0 0x1000&gt;;</div><div class='ctx'> 			reg-shift = &lt;2&gt;;</div><div class='hunk'>@@ -785,7 +790,6 @@</div><div class='ctx'> </div><div class='ctx'> 		serial2: serial@1c022000 {</div><div class='ctx'> 			status = "disabled";</div><div class='del'>-			device_type = "serial";</div><div class='ctx'> 			compatible = "ns16550a";</div><div class='ctx'> 			reg = &lt;0 0x1c022000 0x0 0x1000&gt;;</div><div class='ctx'> 			reg-shift = &lt;2&gt;;</div><div class='hunk'>@@ -796,7 +800,6 @@</div><div class='ctx'> </div><div class='ctx'> 		serial3: serial@1c023000 {</div><div class='ctx'> 			status = "disabled";</div><div class='del'>-			device_type = "serial";</div><div class='ctx'> 			compatible = "ns16550a";</div><div class='ctx'> 			reg = &lt;0 0x1c023000 0x0 0x1000&gt;;</div><div class='ctx'> 			reg-shift = &lt;2&gt;;</div><div class='hunk'>@@ -825,13 +828,13 @@</div><div class='ctx'> 		dwgpio: gpio@1c024000 {</div><div class='ctx'> 			compatible = "snps,dw-apb-gpio";</div><div class='ctx'> 			reg = &lt;0x0 0x1c024000 0x0 0x1000&gt;;</div><div class='del'>-			reg-io-width = &lt;4&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> </div><div class='ctx'> 			porta: gpio-controller@0 {</div><div class='ctx'> 				compatible = "snps,dw-apb-gpio-port";</div><div class='ctx'> 				gpio-controller;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='ctx'> 				snps,nr-gpios = &lt;32&gt;;</div><div class='ctx'> 				reg = &lt;0&gt;;</div><div class='ctx'> 			};</div><div class='hunk'>@@ -844,9 +847,7 @@</div><div class='ctx'> 			compatible = "snps,designware-i2c";</div><div class='ctx'> 			reg = &lt;0x0 0x10512000 0x0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;0 0x44 0x4&gt;;</div><div class='del'>-			#clock-cells = &lt;1&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;ahbclk 0&gt;;</div><div class='del'>-			bus_num = &lt;0&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		phy1: phy@1f21a000 {</div><div class='hunk'>@@ -864,7 +865,7 @@</div><div class='ctx'> 			reg = &lt;0x0 0x1f22a000 0x0 0x100&gt;;</div><div class='ctx'> 			#phy-cells = &lt;1&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;sataphy2clk 0&gt;;</div><div class='del'>-			status = "ok";</div><div class='add'>+			status = "okay";</div><div class='ctx'> 			apm,tx-boost-gain = &lt;30 30 30 30 30 30&gt;;</div><div class='ctx'> 			apm,tx-eye-tuning = &lt;1 10 10 2 10 10&gt;;</div><div class='ctx'> 		};</div><div class='hunk'>@@ -874,7 +875,7 @@</div><div class='ctx'> 			reg = &lt;0x0 0x1f23a000 0x0 0x100&gt;;</div><div class='ctx'> 			#phy-cells = &lt;1&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;sataphy3clk 0&gt;;</div><div class='del'>-			status = "ok";</div><div class='add'>+			status = "okay";</div><div class='ctx'> 			apm,tx-boost-gain = &lt;31 31 31 31 31 31&gt;;</div><div class='ctx'> 			apm,tx-eye-tuning = &lt;2 10 10 2 10 10&gt;;</div><div class='ctx'> 		};</div><div class='hunk'>@@ -903,7 +904,7 @@</div><div class='ctx'> 			      &lt;0x0 0x1f227000 0x0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;0x0 0x87 0x4&gt;;</div><div class='ctx'> 			dma-coherent;</div><div class='del'>-			status = "ok";</div><div class='add'>+			status = "okay";</div><div class='ctx'> 			clocks = &lt;&amp;sata23clk 0&gt;;</div><div class='ctx'> 			phys = &lt;&amp;phy2 0&gt;;</div><div class='ctx'> 			phy-names = "sata-phy";</div><div class='hunk'>@@ -917,32 +918,32 @@</div><div class='ctx'> 			      &lt;0x0 0x1f23e000 0x0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;0x0 0x88 0x4&gt;;</div><div class='ctx'> 			dma-coherent;</div><div class='del'>-			status = "ok";</div><div class='add'>+			status = "okay";</div><div class='ctx'> 			clocks = &lt;&amp;sata45clk 0&gt;;</div><div class='ctx'> 			phys = &lt;&amp;phy3 0&gt;;</div><div class='ctx'> 			phy-names = "sata-phy";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		/* Do not change dwusb name, coded for backward compatibility */</div><div class='del'>-		usb0: dwusb@19000000 {</div><div class='add'>+		/* Node-name might need to be coded as dwusb for backward compatibility */</div><div class='add'>+		usb0: usb@19000000 {</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 			compatible = "snps,dwc3";</div><div class='del'>-			reg =  &lt;0x0 0x19000000 0x0 0x100000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x19000000 0x0 0x100000&gt;;</div><div class='ctx'> 			interrupts = &lt;0x0 0x89 0x4&gt;;</div><div class='ctx'> 			dma-coherent;</div><div class='ctx'> 			dr_mode = "host";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		usb1: dwusb@19800000 {</div><div class='add'>+		usb1: usb@19800000 {</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 			compatible = "snps,dwc3";</div><div class='del'>-			reg =  &lt;0x0 0x19800000 0x0 0x100000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x19800000 0x0 0x100000&gt;;</div><div class='ctx'> 			interrupts = &lt;0x0 0x8a 0x4&gt;;</div><div class='ctx'> 			dma-coherent;</div><div class='ctx'> 			dr_mode = "host";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		sbgpio: gpio@17001000{</div><div class='add'>+		sbgpio: gpio@17001000 {</div><div class='ctx'> 			compatible = "apm,xgene-gpio-sb";</div><div class='ctx'> 			reg = &lt;0x0 0x17001000 0x0 0x400&gt;;</div><div class='ctx'> 			#gpio-cells = &lt;2&gt;;</div><div class='hunk'>@@ -992,7 +993,7 @@</div><div class='ctx'> 				compatible = "apm,xgene-mdio";</div><div class='ctx'> 				#address-cells = &lt;1&gt;;</div><div class='ctx'> 				#size-cells = &lt;0&gt;;</div><div class='del'>-				menetphy: menetphy@3 {</div><div class='add'>+				menetphy: ethernet-phy@3 {</div><div class='ctx'> 					compatible = "ethernet-phy-id001c.c915";</div><div class='ctx'> 					reg = &lt;0x3&gt;;</div><div class='ctx'> 				};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/Makefile b/arch/arm64/boot/dts/apple/Makefile<br/>new file mode 100644<br/>index 000000000000..4eebcd85c90f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/Makefile</a></div><div class='hunk'>@@ -0,0 +1,93 @@</div><div class='add'>+# SPDX-License-Identifier: GPL-2.0</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += s5l8960x-j71.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += s5l8960x-j73.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += s5l8960x-j85m.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += s5l8960x-j86m.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += s5l8960x-j87m.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += s5l8960x-n53.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += s5l8960x-j72.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += s5l8960x-j85.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += s5l8960x-j86.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += s5l8960x-j87.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += s5l8960x-n51.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t7000-j42d.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t7000-j96.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t7000-j97.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t7000-n102.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t7000-n56.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t7000-n61.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t7001-j81.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t7001-j82.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += s8000-j71s.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += s8000-j72s.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += s8000-n66.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += s8000-n69u.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += s8000-n71.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += s8003-j71t.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += s8003-j72t.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += s8003-n66m.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += s8003-n69.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += s8003-n71m.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += s8001-j127.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += s8001-j128.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += s8001-j98a.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += s8001-j99a.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t8010-d101.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t8010-d10.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t8010-d111.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t8010-d11.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t8010-j171.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t8010-j172.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t8010-j71b.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t8010-j72b.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t8010-n112.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t8011-j105a.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t8011-j120.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t8011-j121.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t8011-j207.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t8011-j208.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t8012-j132.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t8012-j137.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t8012-j140a.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t8012-j140k.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t8012-j152f.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t8012-j160.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t8012-j174.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t8012-j185.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t8012-j185f.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t8012-j213.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t8012-j215.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t8012-j223.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t8012-j230k.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t8012-j214k.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t8012-j680.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t8012-j780.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t8015-d201.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t8015-d20.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t8015-d211.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t8015-d21.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t8015-d221.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t8015-d22.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t8103-j274.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t8103-j293.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t8103-j313.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t8103-j456.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t8103-j457.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t6000-j314s.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t6001-j314c.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t6000-j316s.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t6001-j316c.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t6001-j375c.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t6002-j375d.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t6022-j180d.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t6020-j414s.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t6021-j414c.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t6020-j416s.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t6021-j416c.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t6020-j474s.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t6021-j475c.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t6022-j475d.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t8112-j413.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t8112-j415.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t8112-j473.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_APPLE) += t8112-j493.dtb</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/multi-die-cpp.h b/arch/arm64/boot/dts/apple/multi-die-cpp.h<br/>new file mode 100644<br/>index 000000000000..39e8953bf809<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/multi-die-cpp.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/multi-die-cpp.h</a></div><div class='hunk'>@@ -0,0 +1,22 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+ *</div><div class='add'>+ * C preprocessor macros for t600x multi die support.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __DTS_APPLE_MULTI_DIE_CPP_H</div><div class='add'>+#define __DTS_APPLE_MULTI_DIE_CPP_H</div><div class='add'>+</div><div class='add'>+#ifndef __stringify</div><div class='add'>+#define __stringify_1(x...)     #x</div><div class='add'>+#define __stringify(x...)       __stringify_1(x)</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+#ifndef __concat</div><div class='add'>+#define __concat_1(x, y...)     x ## y</div><div class='add'>+#define __concat(x, y...)       __concat_1(x, y)</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+#define DIE_NODE(a) __concat(a, DIE)</div><div class='add'>+#define DIE_LABEL(a) __stringify(__concat(a, DIE))</div><div class='add'>+</div><div class='add'>+#endif /* !__DTS_APPLE_MULTI_DIE_CPP_H */</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/s5l8960x-5s.dtsi b/arch/arm64/boot/dts/apple/s5l8960x-5s.dtsi<br/>new file mode 100644<br/>index 000000000000..8868df1538d6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/s5l8960x-5s.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/s5l8960x-5s.dtsi</a></div><div class='hunk'>@@ -0,0 +1,60 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPhone 5s common device tree</div><div class='add'>+ * Based on A7 (APL0698), up to 1.3GHz</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "s5l8960x.dtsi"</div><div class='add'>+#include "s5l8960x-common.dtsi"</div><div class='add'>+#include "s5l8960x-opp.dtsi"</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	chassis-type = "handset";</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		button-home {</div><div class='add'>+			label = "Home Button";</div><div class='add'>+			gpios = &lt;&amp;pinctrl 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_HOMEPAGE&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-power {</div><div class='add'>+			label = "Power Button";</div><div class='add'>+			gpios = &lt;&amp;pinctrl 3 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-voldown {</div><div class='add'>+			label = "Volume Down";</div><div class='add'>+			gpios = &lt;&amp;pinctrl 5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-volup {</div><div class='add'>+			label = "Volume Up";</div><div class='add'>+			gpios = &lt;&amp;pinctrl 4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		switch-mute {</div><div class='add'>+			label = "Mute Switch";</div><div class='add'>+			gpios = &lt;&amp;pinctrl 16 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_MUTE&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dwi_bl {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;framebuffer0 {</div><div class='add'>+	power-domains = &lt;&amp;ps_disp0 &amp;ps_mipi_dsi&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/s5l8960x-air1.dtsi b/arch/arm64/boot/dts/apple/s5l8960x-air1.dtsi<br/>new file mode 100644<br/>index 000000000000..dd57eb1d34c0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/s5l8960x-air1.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/s5l8960x-air1.dtsi</a></div><div class='hunk'>@@ -0,0 +1,56 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPad Air  common device tree</div><div class='add'>+ * Based on A7 (APL5698), up to 1.4GHz</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "s5l8960x.dtsi"</div><div class='add'>+#include "s5l8960x-common.dtsi"</div><div class='add'>+#include "s5l8965x-opp.dtsi"</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	chassis-type = "tablet";</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		button-home {</div><div class='add'>+			label = "Home Button";</div><div class='add'>+			gpios = &lt;&amp;pinctrl 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_HOMEPAGE&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-power {</div><div class='add'>+			label = "Power Button";</div><div class='add'>+			gpios = &lt;&amp;pinctrl 3 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-voldown {</div><div class='add'>+			label = "Volume Down";</div><div class='add'>+			gpios = &lt;&amp;pinctrl 4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-volup {</div><div class='add'>+			label = "Volume Up";</div><div class='add'>+			gpios = &lt;&amp;pinctrl 5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		switch-mute {</div><div class='add'>+			label = "Mute Switch";</div><div class='add'>+			gpios = &lt;&amp;pinctrl 110 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_MUTE&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;framebuffer0 {</div><div class='add'>+	power-domains = &lt;&amp;ps_disp0 &amp;ps_dp&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/s5l8960x-common.dtsi b/arch/arm64/boot/dts/apple/s5l8960x-common.dtsi<br/>new file mode 100644<br/>index 000000000000..243480ca2356<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/s5l8960x-common.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/s5l8960x-common.dtsi</a></div><div class='hunk'>@@ -0,0 +1,48 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPhone 5s, iPad mini 2/3, iPad Air</div><div class='add'>+ *</div><div class='add'>+ * This file contains parts common to all Apple A7 devices.</div><div class='add'>+ *</div><div class='add'>+ * target-type: J71, J72, J73, J85, J85m, J86, J86m, J87, J87m, N51, N53</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2024, Nick Chan &lt;towinchenmi@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;serial0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		stdout-path = "serial0";</div><div class='add'>+</div><div class='add'>+		framebuffer0: framebuffer@0 {</div><div class='add'>+			compatible = "apple,simple-framebuffer", "simple-framebuffer";</div><div class='add'>+			reg = &lt;0 0 0 0&gt;; /* To be filled by loader */</div><div class='add'>+			/* Format properties will be added by loader */</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@800000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x8 0 0 0&gt;; /* To be filled by loader */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		/* To be filled by loader */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;serial0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/s5l8960x-j71.dts b/arch/arm64/boot/dts/apple/s5l8960x-j71.dts<br/>new file mode 100644<br/>index 000000000000..e13036dacb45<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/s5l8960x-j71.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/s5l8960x-j71.dts</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPad Air (Wi-Fi), J71, iPad4,1 (A1474)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "s5l8960x-air1.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j71", "apple,s5l8960x", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPad Air (Wi-Fi)";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/s5l8960x-j72.dts b/arch/arm64/boot/dts/apple/s5l8960x-j72.dts<br/>new file mode 100644<br/>index 000000000000..afb71b8885c6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/s5l8960x-j72.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/s5l8960x-j72.dts</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPad Air (Cellular), J72, iPad4,2 (A1475)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "s5l8960x-air1.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j72", "apple,s5l8960x", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPad Air (Cellular)";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/s5l8960x-j73.dts b/arch/arm64/boot/dts/apple/s5l8960x-j73.dts<br/>new file mode 100644<br/>index 000000000000..c871962df529<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/s5l8960x-j73.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/s5l8960x-j73.dts</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPad Air (Cellular, China), J73, iPad4,2 (A1476)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "s5l8960x-air1.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j73", "apple,s5l8960x", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPad Air (Cellular, China)";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/s5l8960x-j85.dts b/arch/arm64/boot/dts/apple/s5l8960x-j85.dts<br/>new file mode 100644<br/>index 000000000000..aefb7b36d7aa<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/s5l8960x-j85.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/s5l8960x-j85.dts</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPad mini 2 (Wi-Fi), J85, iPad4,4 (A1489)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "s5l8960x-mini2.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j85", "apple,s5l8960x", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPad mini 2 (Wi-Fi)";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/s5l8960x-j85m.dts b/arch/arm64/boot/dts/apple/s5l8960x-j85m.dts<br/>new file mode 100644<br/>index 000000000000..ec2bcaa6d1d5<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/s5l8960x-j85m.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/s5l8960x-j85m.dts</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPad mini 3 (Wi-Fi), J85m, iPad4,7 (A1599)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "s5l8960x-mini3.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j85m", "apple,s5l8960x", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPad mini 3 (Wi-Fi)";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/s5l8960x-j86.dts b/arch/arm64/boot/dts/apple/s5l8960x-j86.dts<br/>new file mode 100644<br/>index 000000000000..470f2f825e70<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/s5l8960x-j86.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/s5l8960x-j86.dts</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPad mini 2 (Cellular), J86, iPad4,5 (A1490)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "s5l8960x-mini2.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j86", "apple,s5l8960x", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPad mini 2 (Cellular)";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/s5l8960x-j86m.dts b/arch/arm64/boot/dts/apple/s5l8960x-j86m.dts<br/>new file mode 100644<br/>index 000000000000..90311d98aaad<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/s5l8960x-j86m.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/s5l8960x-j86m.dts</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPad mini 3 (Cellular), J86m, iPad4,8 (A1600)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "s5l8960x-mini3.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j86m", "apple,s5l8960x", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPad mini 3 (Cellular)";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/s5l8960x-j87.dts b/arch/arm64/boot/dts/apple/s5l8960x-j87.dts<br/>new file mode 100644<br/>index 000000000000..3580fd8e3831<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/s5l8960x-j87.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/s5l8960x-j87.dts</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPad mini 2 (Cellular, China), J87, iPad4,6 (A1491)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "s5l8960x-mini2.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j87", "apple,s5l8960x", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPad mini 2 (Cellular, China)";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/s5l8960x-j87m.dts b/arch/arm64/boot/dts/apple/s5l8960x-j87m.dts<br/>new file mode 100644<br/>index 000000000000..fa0da4fa6727<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/s5l8960x-j87m.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/s5l8960x-j87m.dts</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPad mini 3 (Cellular, China), J87m, iPad4,9 (A1601)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "s5l8960x-mini3.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j87m", "apple,s5l8960x", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPad mini 3 (Cellular, China)";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/s5l8960x-mini2.dtsi b/arch/arm64/boot/dts/apple/s5l8960x-mini2.dtsi<br/>new file mode 100644<br/>index 000000000000..f3696d22e71c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/s5l8960x-mini2.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/s5l8960x-mini2.dtsi</a></div><div class='hunk'>@@ -0,0 +1,56 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPad mini 2 common device tree</div><div class='add'>+ * Based on A7 (APL0698), up to 1.3GHz</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "s5l8960x.dtsi"</div><div class='add'>+#include "s5l8960x-common.dtsi"</div><div class='add'>+#include "s5l8960x-opp.dtsi"</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	chassis-type = "tablet";</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		button-home {</div><div class='add'>+			label = "Home Button";</div><div class='add'>+			gpios = &lt;&amp;pinctrl 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_HOMEPAGE&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-power {</div><div class='add'>+			label = "Power Button";</div><div class='add'>+			gpios = &lt;&amp;pinctrl 3 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-voldown {</div><div class='add'>+			label = "Volume Down";</div><div class='add'>+			gpios = &lt;&amp;pinctrl 5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-volup {</div><div class='add'>+			label = "Volume Up";</div><div class='add'>+			gpios = &lt;&amp;pinctrl 4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		switch-mute {</div><div class='add'>+			label = "Mute Switch";</div><div class='add'>+			gpios = &lt;&amp;pinctrl 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_MUTE&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;framebuffer0 {</div><div class='add'>+	power-domains = &lt;&amp;ps_disp0 &amp;ps_dp&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/s5l8960x-mini3.dtsi b/arch/arm64/boot/dts/apple/s5l8960x-mini3.dtsi<br/>new file mode 100644<br/>index 000000000000..4e397b3d7d7a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/s5l8960x-mini3.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/s5l8960x-mini3.dtsi</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPad mini 3 common device tree</div><div class='add'>+ * Based on A7 (APL0698), up to 1.3GHz</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * The Mini 3 seems to be only an iteration over the Mini 2 with some</div><div class='add'>+ * small changes, like the introduction of Touch ID, hence there is little</div><div class='add'>+ * to no differentiation between these 2 for now.</div><div class='add'>+ */</div><div class='add'>+#include "s5l8960x-mini2.dtsi"</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/s5l8960x-n51.dts b/arch/arm64/boot/dts/apple/s5l8960x-n51.dts<br/>new file mode 100644<br/>index 000000000000..cd52f814fbf2<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/s5l8960x-n51.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/s5l8960x-n51.dts</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPhone 5s (GSM), N51, iPhone6,1 (A1453/A1533)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "s5l8960x-5s.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,n51", "apple,s5l8960x", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPhone 5s (GSM)";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/s5l8960x-n53.dts b/arch/arm64/boot/dts/apple/s5l8960x-n53.dts<br/>new file mode 100644<br/>index 000000000000..4795798a4444<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/s5l8960x-n53.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/s5l8960x-n53.dts</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPhone 5s (LTE), N53, iPhone6,2 (A1457/A1518/A1528/A1530)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "s5l8960x-5s.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,n53", "apple,s5l8960x", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPhone 5s (LTE)";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/s5l8960x-opp.dtsi b/arch/arm64/boot/dts/apple/s5l8960x-opp.dtsi<br/>new file mode 100644<br/>index 000000000000..e4d568c4a119<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/s5l8960x-opp.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/s5l8960x-opp.dtsi</a></div><div class='hunk'>@@ -0,0 +1,45 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Operating points for Apple S5L8960X "A7" SoC, Up to 1296 MHz</div><div class='add'>+ *</div><div class='add'>+ * target-type: N51, N53, J85, J86. J87, J85m, J86m, J87m</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2024, Nick Chan &lt;towinchenmi@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	cyclone_opp: opp-table {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		opp01 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;300000000&gt;;</div><div class='add'>+			opp-level = &lt;1&gt;;</div><div class='add'>+			clock-latency-ns = &lt;15500&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp02 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;396000000&gt;;</div><div class='add'>+			opp-level = &lt;2&gt;;</div><div class='add'>+			clock-latency-ns = &lt;43000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp03 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;600000000&gt;;</div><div class='add'>+			opp-level = &lt;3&gt;;</div><div class='add'>+			clock-latency-ns = &lt;26000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp04 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;840000000&gt;;</div><div class='add'>+			opp-level = &lt;4&gt;;</div><div class='add'>+			clock-latency-ns = &lt;30000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp05 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1128000000&gt;;</div><div class='add'>+			opp-level = &lt;5&gt;;</div><div class='add'>+			clock-latency-ns = &lt;39500&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp06 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1296000000&gt;;</div><div class='add'>+			opp-level = &lt;6&gt;;</div><div class='add'>+			clock-latency-ns = &lt;45500&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/s5l8960x-pmgr.dtsi b/arch/arm64/boot/dts/apple/s5l8960x-pmgr.dtsi<br/>new file mode 100644<br/>index 000000000000..da265f484307<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/s5l8960x-pmgr.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/s5l8960x-pmgr.dtsi</a></div><div class='hunk'>@@ -0,0 +1,610 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * PMGR Power domains for the Apple S5L8960X "A7" SoC</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2024 Nick Chan &lt;towinchenmi@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;pmgr {</div><div class='add'>+	ps_cpu0: power-controller@20000 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20000 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "cpu0";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_cpu1: power-controller@20008 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20008 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "cpu1";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_secuart0: power-controller@200f0 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x200f0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "secuart0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_secuart1: power-controller@200f8 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x200f8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "secuart1";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_cpm: power-controller@20010 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20010 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "cpm";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_lio: power-controller@20018 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20018 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "lio";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_iomux: power-controller@20020 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20020 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "iomux";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_aic: power-controller@20028 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20028 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "aic";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_debug: power-controller@20030 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20030 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "debug";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dwi: power-controller@20038 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20038 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dwi";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_gpio: power-controller@20040 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20040 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "gpio";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca0: power-controller@20048 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20048 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca1: power-controller@20050 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20050 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca1";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca2: power-controller@20058 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20058 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca2";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca3: power-controller@20060 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20060 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca3";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca4: power-controller@20068 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20068 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca4";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pwm0: power-controller@20070 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20070 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pwm0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c0: power-controller@20078 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20078 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c1: power-controller@20080 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20080 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c1";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c2: power-controller@20088 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20088 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c2";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c3: power-controller@20090 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20090 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c3";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi0: power-controller@20098 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20098 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi1: power-controller@200a0 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x200a0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi1";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi2: power-controller@200a8 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x200a8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi2";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi3: power-controller@200b0 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x200b0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi3";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart0: power-controller@200b8 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x200b8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart1: power-controller@200c0 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x200c0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart1";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart2: power-controller@200c8 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x200c8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart2";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart3: power-controller@200d0 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x200d0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart3";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart4: power-controller@200d8 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x200d8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart4";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart5: power-controller@200e0 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x200e0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart5";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart6: power-controller@200e8 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x200e8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart6";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sio_p: power-controller@20110 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20110 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sio_p";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usb: power-controller@20158 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20158 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usb";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usbctrl: power-controller@20160 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20160 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usbctrl";</div><div class='add'>+		power-domains = &lt;&amp;ps_usb&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usb2host0: power-controller@20170 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20170 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usb2host0";</div><div class='add'>+		power-domains = &lt;&amp;ps_usbctrl&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usb2host1: power-controller@20180 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20180 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usb2host1";</div><div class='add'>+		power-domains = &lt;&amp;ps_usbctrl&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_disp_busmux: power-controller@201a8 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x201a8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "disp_busmux";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_media: power-controller@201d8 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x201d8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "media";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_isp: power-controller@201d0 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x201d0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "isp";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_msr: power-controller@201e0 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x201e0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "msr";</div><div class='add'>+		power-domains = &lt;&amp;ps_media&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_jpg: power-controller@201e8 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x201e8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "jpg";</div><div class='add'>+		power-domains = &lt;&amp;ps_media&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_disp0: power-controller@201b0 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x201b0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "disp0";</div><div class='add'>+		power-domains = &lt;&amp;ps_disp_busmux&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_aes0: power-controller@20100 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20100 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "aes0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sio: power-controller@20108 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20108 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sio";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_hsic0_phy: power-controller@20118 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20118 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "hsic0_phy";</div><div class='add'>+		power-domains = &lt;&amp;ps_usb2host0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_hsic1_phy: power-controller@20120 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20120 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "hsic1_phy";</div><div class='add'>+		power-domains = &lt;&amp;ps_usb2host0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_hsic2_phy: power-controller@20128 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20128 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "hsic2_phy";</div><div class='add'>+		power-domains = &lt;&amp;ps_usb2host1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_ispsens0: power-controller@20130 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20130 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "ispsens0";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_ispsens1: power-controller@20138 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20138 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "ispsens1";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mcc: power-controller@20140 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20140 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mcc";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mcu: power-controller@20148 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20148 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mcu";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_amp: power-controller@20150 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20150 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "amp";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usb2host0_ohci: power-controller@20168 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20168 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usb2host0_ohci";</div><div class='add'>+		power-domains = &lt;&amp;ps_usb2host0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usb2host1_ohci: power-controller@20178 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20178 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usb2host1_ohci";</div><div class='add'>+		power-domains = &lt;&amp;ps_usb2host1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usbotg: power-controller@20188 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20188 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usbotg";</div><div class='add'>+		power-domains = &lt;&amp;ps_usbctrl&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_smx: power-controller@20190 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20190 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "smx";</div><div class='add'>+		apple,always-on; /* Apple fabric, critical block */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sf: power-controller@20198 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20198 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sf";</div><div class='add'>+		apple,always-on; /* Apple fabric, critical block */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_cp: power-controller@201a0 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x201a0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "cp";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mipi_dsi: power-controller@201b8 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x201b8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mipi_dsi";</div><div class='add'>+		power-domains = &lt;&amp;ps_disp_busmux&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dp: power-controller@201c0 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x201c0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dp";</div><div class='add'>+		power-domains = &lt;&amp;ps_disp0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_disp1: power-controller@201c8 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x201c8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "disp1";</div><div class='add'>+		power-domains = &lt;&amp;ps_disp_busmux&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_vdec: power-controller@201f0 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x201f0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "vdec";</div><div class='add'>+		power-domains = &lt;&amp;ps_media&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc: power-controller@201f8 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x201f8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc";</div><div class='add'>+		power-domains = &lt;&amp;ps_media&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_ans: power-controller@20200 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20200 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "ans";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_ans_dll: power-controller@20208 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20208 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "ans_dll";</div><div class='add'>+		power-domains = &lt;&amp;ps_ans&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_gfx: power-controller@20218 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20218 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "gfx";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sep: power-controller@20268 {</div><div class='add'>+		compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20268 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sep";</div><div class='add'>+		power-domains = &lt;&amp;ps_secuart1&gt;, &lt;&amp;ps_secuart0&gt;;</div><div class='add'>+		apple,always-on; /* Locked on */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/s5l8960x.dtsi b/arch/arm64/boot/dts/apple/s5l8960x.dtsi<br/>new file mode 100644<br/>index 000000000000..462ffdd348fc<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/s5l8960x.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/s5l8960x.dtsi</a></div><div class='hunk'>@@ -0,0 +1,232 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple S5L8960X "A7" SoC</div><div class='add'>+ *</div><div class='add'>+ * Other Names: H6, "Alcatraz"</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ * Based on Asahi Linux's M1 (t8103.dtsi) and Corellium's A10 efforts.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/apple-aic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/apple.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	clkref: clock-ref {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+		clock-output-names = "clkref";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			compatible = "apple,cyclone";</div><div class='add'>+			reg = &lt;0x0 0x0&gt;;</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			operating-points-v2 = &lt;&amp;cyclone_opp&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache&gt;;</div><div class='add'>+			i-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@1 {</div><div class='add'>+			compatible = "apple,cyclone";</div><div class='add'>+			reg = &lt;0x0 0x1&gt;;</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			operating-points-v2 = &lt;&amp;cyclone_opp&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache&gt;;</div><div class='add'>+			i-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_cache: l2-cache {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x100000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		nonposted-mmio;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		cpufreq: performance-controller@202220000 {</div><div class='add'>+			compatible = "apple,s5l8960x-cluster-cpufreq";</div><div class='add'>+			reg = &lt;0x2 0x02220000 0 0x1000&gt;;</div><div class='add'>+			#performance-domain-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		serial0: serial@20a0a0000 {</div><div class='add'>+			compatible = "apple,s5l-uart";</div><div class='add'>+			reg = &lt;0x2 0x0a0a0000 0x0 0x4000&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 140 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			/* Use the bootloader-enabled clocks for now. */</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;, &lt;&amp;clkref&gt;;</div><div class='add'>+			clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+			power-domains = &lt;&amp;ps_uart0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c0: i2c@20a110000 {</div><div class='add'>+			compatible = "apple,s5l8960x-i2c", "apple,i2c";</div><div class='add'>+			reg = &lt;0x2 0x0a110000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 154 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c0_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			power-domains = &lt;&amp;ps_i2c0&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c1: i2c@20a111000 {</div><div class='add'>+			compatible = "apple,s5l8960x-i2c", "apple,i2c";</div><div class='add'>+			reg = &lt;0x2 0x0a111000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 155 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c1_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			power-domains = &lt;&amp;ps_i2c1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c2: i2c@20a112000 {</div><div class='add'>+			compatible = "apple,s5l8960x-i2c", "apple,i2c";</div><div class='add'>+			reg = &lt;0x2 0x0a112000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 156 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c2_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			power-domains = &lt;&amp;ps_i2c2&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c3: i2c@20a113000 {</div><div class='add'>+			compatible = "apple,s5l8960x-i2c", "apple,i2c";</div><div class='add'>+			reg = &lt;0x2 0x0a113000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 157 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c3_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			power-domains = &lt;&amp;ps_i2c3&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmgr: power-management@20e000000 {</div><div class='add'>+			compatible = "apple,s5l8960x-pmgr", "apple,pmgr", "syscon", "simple-mfd";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			reg = &lt;0x2 0xe000000 0 0x24000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wdt: watchdog@20e027000 {</div><div class='add'>+			compatible = "apple,s5l8960x-wdt", "apple,wdt";</div><div class='add'>+			reg = &lt;0x2 0x0e027000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 4 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aic: interrupt-controller@20e100000 {</div><div class='add'>+			compatible = "apple,s5l8960x-aic", "apple,aic";</div><div class='add'>+			reg = &lt;0x2 0x0e100000 0x0 0x100000&gt;;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			power-domains = &lt;&amp;ps_aic&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dwi_bl: backlight@20e200010 {</div><div class='add'>+			compatible = "apple,s5l8960x-dwi-bl", "apple,dwi-bl";</div><div class='add'>+			reg = &lt;0x2 0x0e200010 0x0 0x8&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_dwi&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl: pinctrl@20e300000 {</div><div class='add'>+			compatible = "apple,s5l8960x-pinctrl", "apple,pinctrl";</div><div class='add'>+			reg = &lt;0x2 0x0e300000 0x0 0x100000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_gpio&gt;;</div><div class='add'>+</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;pinctrl 0 0 200&gt;;</div><div class='add'>+			apple,npins = &lt;200&gt;;</div><div class='add'>+</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 108 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 109 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 110 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 111 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 112 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 113 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 114 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			i2c0_pins: i2c0-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(81, 1)&gt;,</div><div class='add'>+					 &lt;APPLE_PINMUX(80, 1)&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c1_pins: i2c1-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(83, 1)&gt;,</div><div class='add'>+					 &lt;APPLE_PINMUX(82, 1)&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c2_pins: i2c2-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(101, 1)&gt;,</div><div class='add'>+					 &lt;APPLE_PINMUX(100, 1)&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c3_pins: i2c3-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(172, 1)&gt;,</div><div class='add'>+					 &lt;APPLE_PINMUX(171, 1)&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupt-names = "phys", "virt";</div><div class='add'>+		/* Note that A7 doesn't actually have a hypervisor (EL2 is not implemented). */</div><div class='add'>+		interrupts = &lt;AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include "s5l8960x-pmgr.dtsi"</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/s5l8965x-opp.dtsi b/arch/arm64/boot/dts/apple/s5l8965x-opp.dtsi<br/>new file mode 100644<br/>index 000000000000..d34dae74a90c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/s5l8965x-opp.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/s5l8965x-opp.dtsi</a></div><div class='hunk'>@@ -0,0 +1,45 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Operating points for Apple S5L8965X "A7" Rev A SoC, Up to 1392 MHz</div><div class='add'>+ *</div><div class='add'>+ * target-type: J71, J72, J73</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2024, Nick Chan &lt;towinchenmi@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	cyclone_opp: opp-table {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		opp01 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;300000000&gt;;</div><div class='add'>+			opp-level = &lt;1&gt;;</div><div class='add'>+			clock-latency-ns = &lt;10000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp02 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;600000000&gt;;</div><div class='add'>+			opp-level = &lt;2&gt;;</div><div class='add'>+			clock-latency-ns = &lt;49000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp03 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;840000000&gt;;</div><div class='add'>+			opp-level = &lt;3&gt;;</div><div class='add'>+			clock-latency-ns = &lt;30000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp04 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1128000000&gt;;</div><div class='add'>+			opp-level = &lt;4&gt;;</div><div class='add'>+			clock-latency-ns = &lt;39500&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp05 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1296000000&gt;;</div><div class='add'>+			opp-level = &lt;5&gt;;</div><div class='add'>+			clock-latency-ns = &lt;45500&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp06 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1392000000&gt;;</div><div class='add'>+			opp-level = &lt;6&gt;;</div><div class='add'>+			clock-latency-ns = &lt;46500&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/s800-0-3-common.dtsi b/arch/arm64/boot/dts/apple/s800-0-3-common.dtsi<br/>new file mode 100644<br/>index 000000000000..cb42c5f2c1b6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/s800-0-3-common.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/s800-0-3-common.dtsi</a></div><div class='hunk'>@@ -0,0 +1,52 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPhone 6s, iPhone 6s Plus, iPad 5, iPhone SE</div><div class='add'>+ *</div><div class='add'>+ * This file contains parts common to all Apple A9 devices.</div><div class='add'>+ *</div><div class='add'>+ * target-type: J71s, J72s, N66, N69u, N71, J71t, J72t, N66m, N69, N71m</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2024, Nick Chan &lt;towinchenmi@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;serial0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		stdout-path = "serial0";</div><div class='add'>+</div><div class='add'>+		framebuffer0: framebuffer@0 {</div><div class='add'>+			compatible = "apple,simple-framebuffer", "simple-framebuffer";</div><div class='add'>+			reg = &lt;0 0 0 0&gt;; /* To be filled by loader */</div><div class='add'>+			/* Format properties will be added by loader */</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@800000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x8 0 0 0&gt;; /* To be filled by loader */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		/* To be filled by loader */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dwi_bl {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;serial0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/s800-0-3-pmgr.dtsi b/arch/arm64/boot/dts/apple/s800-0-3-pmgr.dtsi<br/>new file mode 100644<br/>index 000000000000..196b8e745a95<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/s800-0-3-pmgr.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/s800-0-3-pmgr.dtsi</a></div><div class='hunk'>@@ -0,0 +1,757 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * PMGR Power domains for the Apple S8000/3 "A9" SoC</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2024 Nick Chan &lt;towinchenmi@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;pmgr {</div><div class='add'>+	ps_cpu0: power-controller@80000 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80000 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "cpu0";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_cpu1: power-controller@80008 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80008 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "cpu1";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_cpm: power-controller@80040 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80040 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "cpm";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sio_busif: power-controller@80150 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80150 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sio_busif";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sio_p: power-controller@80158 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80158 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sio_p";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_busif&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sbr: power-controller@80100 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80100 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sbr";</div><div class='add'>+		apple,always-on; /* Apple fabric, critical block */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_aic: power-controller@80108 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80108 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "aic";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dwi: power-controller@80110 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80110 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dwi";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_gpio: power-controller@80118 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80118 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "gpio";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pms: power-controller@80120 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80120 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pms";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pcie_ref: power-controller@80148 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80148 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pcie_ref";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca0: power-controller@80168 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80168 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca1: power-controller@80170 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80170 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca1";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca2: power-controller@80178 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80178 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca2";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca3: power-controller@80180 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80180 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca3";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca4: power-controller@80188 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80188 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca4";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pwm0: power-controller@80190 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80190 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pwm0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c0: power-controller@80198 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80198 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c1: power-controller@801a0 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801a0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c1";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c2: power-controller@801a8 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801a8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c2";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c3: power-controller@801b0 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801b0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c3";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi0: power-controller@801b8 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801b8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi1: power-controller@801c0 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801c0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi1";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi2: power-controller@801c8 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801c8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi2";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi3: power-controller@801d0 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801d0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi3";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart0: power-controller@801d8 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801d8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart1: power-controller@801e0 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801e0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart1";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart2: power-controller@801e8 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801e8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart2";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart3: power-controller@801f0 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801f0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart3";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart4: power-controller@801f8 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801f8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart4";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sio: power-controller@80160 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80160 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sio";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_hsic0_phy: power-controller@80128 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80128 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "hsic0_phy";</div><div class='add'>+		power-domains = &lt;&amp;ps_usb2host1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_hsic1_phy: power-controller@80130 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80130 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "hsic1_phy";</div><div class='add'>+		power-domains = &lt;&amp;ps_usb2host2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_isp_sens0: power-controller@80138 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80138 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "isp_sens0";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_isp_sens1: power-controller@80140 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80140 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "isp_sens1";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usb: power-controller@80250 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80250 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usb";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usbctrl: power-controller@80258 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80258 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usbctrl";</div><div class='add'>+		power-domains = &lt;&amp;ps_usb&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usb2host0: power-controller@80260 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80260 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usb2host0";</div><div class='add'>+		power-domains = &lt;&amp;ps_usbctrl&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usb2host1: power-controller@80270 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80270 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usb2host1";</div><div class='add'>+		power-domains = &lt;&amp;ps_usbctrl&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usb2host2: power-controller@80280 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80280 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usb2host2";</div><div class='add'>+		power-domains = &lt;&amp;ps_usbctrl&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_rtmux: power-controller@802a8 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802a8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "rtmux";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_media: power-controller@802d0 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802d0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "media";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_isp: power-controller@802c8 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802c8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "isp";</div><div class='add'>+		power-domains = &lt;&amp;ps_rtmux&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_msr: power-controller@802e0 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802e0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "msr";</div><div class='add'>+		power-domains = &lt;&amp;ps_media&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_jpg: power-controller@802d8 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802d8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "jpg";</div><div class='add'>+		power-domains = &lt;&amp;ps_media&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_disp0: power-controller@802b0 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802b0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "disp0";</div><div class='add'>+		power-domains = &lt;&amp;ps_rtmux&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pmp: power-controller@802e8 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802e8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pmp";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pms_sram: power-controller@802f0 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802f0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pms_sram";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart5: power-controller@80200 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80200 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart5";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart6: power-controller@80208 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80208 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart6";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart7: power-controller@80210 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80210 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart7";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart8: power-controller@80218 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80218 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart8";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_aes0: power-controller@80220 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80220 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "aes0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mcc: power-controller@80228 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80228 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mcc";</div><div class='add'>+		apple,always-on; /* Memory cache controller */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs0: power-controller@80230 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80230 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs0";</div><div class='add'>+		apple,always-on; /* LPDDR4 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs1: power-controller@80238 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80238 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs1";</div><div class='add'>+		apple,always-on; /* LPDDR4 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs2: power-controller@80240 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80240 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs2";</div><div class='add'>+		apple,always-on; /* LPDDR4 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs3: power-controller@80248 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80248 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs3";</div><div class='add'>+		apple,always-on; /* LPDDR4 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usb2host0_ohci: power-controller@80268 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80268 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usb2host0_ohci";</div><div class='add'>+		power-domains = &lt;&amp;ps_usb2host0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usb2host1_ohci: power-controller@80278 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80278 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usb2host1_ohci";</div><div class='add'>+		power-domains = &lt;&amp;ps_usb2host1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usb2host2_ohci: power-controller@80288 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80288 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usb2host2_ohci";</div><div class='add'>+		power-domains = &lt;&amp;ps_usb2host2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usbotg: power-controller@80290 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80290 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usbotg";</div><div class='add'>+		power-domains = &lt;&amp;ps_usbctrl&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_smx: power-controller@80298 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80298 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "smx";</div><div class='add'>+		apple,always-on; /* Apple fabric, critical block */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sf: power-controller@802a0 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802a0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sf";</div><div class='add'>+		apple,always-on; /* Apple fabric, critical block */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mipi_dsi: power-controller@802b8 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802b8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mipi_dsi";</div><div class='add'>+		power-domains = &lt;&amp;ps_rtmux&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dp: power-controller@802c0 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802c0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dp";</div><div class='add'>+		power-domains = &lt;&amp;ps_disp0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_vdec: power-controller@802f8 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802f8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "vdec";</div><div class='add'>+		power-domains = &lt;&amp;ps_media&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc: power-controller@80308 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80308 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc";</div><div class='add'>+		power-domains = &lt;&amp;ps_media&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pcie: power-controller@80310 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80310 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pcie";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pcie_aux: power-controller@80318 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80318 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pcie_aux";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pcie_link0: power-controller@80320 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80320 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pcie_link0";</div><div class='add'>+		power-domains = &lt;&amp;ps_pcie&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pcie_link1: power-controller@80328 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80328 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pcie_link1";</div><div class='add'>+		power-domains = &lt;&amp;ps_pcie&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pcie_link2: power-controller@80330 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80330 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pcie_link2";</div><div class='add'>+		power-domains = &lt;&amp;ps_pcie&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pcie_link3: power-controller@80338 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80338 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pcie_link3";</div><div class='add'>+		power-domains = &lt;&amp;ps_pcie&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_gfx: power-controller@80340 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80340 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "gfx";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sep: power-controller@80400 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80400 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sep";</div><div class='add'>+		apple,always-on; /* Locked on */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc_pipe: power-controller@88000 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x88000 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc_pipe";</div><div class='add'>+		power-domains = &lt;&amp;ps_venc&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc_me0: power-controller@88008 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x88008 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc_me0";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc_me1: power-controller@88010 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x88010 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc_me1";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pmgr_mini {</div><div class='add'>+	ps_aop: power-controller@80000 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80000 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "aop";</div><div class='add'>+		power-domains = &lt;&amp;ps_aop_busif &amp;ps_aop_cpu &amp;ps_aop_filter&gt;;</div><div class='add'>+		apple,always-on; /* Always on processor */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_debug: power-controller@80008 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80008 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "debug";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_aop_gpio: power-controller@80010 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80010 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "aop_gpio";</div><div class='add'>+		power-domains = &lt;&amp;ps_aop&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_aop_cpu: power-controller@80040 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80040 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "aop_cpu";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_aop_filter: power-controller@80048 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80048 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "aop_filter";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_aop_busif: power-controller@80050 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80050 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "aop_busif";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/s800-0-3.dtsi b/arch/arm64/boot/dts/apple/s800-0-3.dtsi<br/>new file mode 100644<br/>index 000000000000..bb38662b7d2e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/s800-0-3.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/s800-0-3.dtsi</a></div><div class='hunk'>@@ -0,0 +1,249 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple S8000/S8003 "A9" SoC</div><div class='add'>+ *</div><div class='add'>+ * This file contains parts common to both variants of A9</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/apple-aic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/apple.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	clkref: clock-ref {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+		clock-output-names = "clkref";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			compatible = "apple,twister";</div><div class='add'>+			reg = &lt;0x0 0x0&gt;;</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled in by loader */</div><div class='add'>+			operating-points-v2 = &lt;&amp;twister_opp&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache&gt;;</div><div class='add'>+			i-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@1 {</div><div class='add'>+			compatible = "apple,twister";</div><div class='add'>+			reg = &lt;0x0 0x1&gt;;</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled in by loader */</div><div class='add'>+			operating-points-v2 = &lt;&amp;twister_opp&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache&gt;;</div><div class='add'>+			i-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_cache: l2-cache {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x300000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		nonposted-mmio;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		cpufreq: performance-controller@202220000 {</div><div class='add'>+			compatible = "apple,s8000-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";</div><div class='add'>+			reg = &lt;0x2 0x02220000 0 0x1000&gt;;</div><div class='add'>+			#performance-domain-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		serial0: serial@20a0c0000 {</div><div class='add'>+			compatible = "apple,s5l-uart";</div><div class='add'>+			reg = &lt;0x2 0x0a0c0000 0x0 0x4000&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 192 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			/* Use the bootloader-enabled clocks for now. */</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;, &lt;&amp;clkref&gt;;</div><div class='add'>+			clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+			power-domains = &lt;&amp;ps_uart0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c0: i2c@20a110000 {</div><div class='add'>+			compatible = "apple,s8000-i2c", "apple,i2c";</div><div class='add'>+			reg = &lt;0x2 0x0a110000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 206 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c0_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			power-domains = &lt;&amp;ps_i2c0&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c1: i2c@20a111000 {</div><div class='add'>+			compatible = "apple,s8000-i2c", "apple,i2c";</div><div class='add'>+			reg = &lt;0x2 0x0a111000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 207 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c1_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			power-domains = &lt;&amp;ps_i2c1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c2: i2c@20a112000 {</div><div class='add'>+			compatible = "apple,s8000-i2c", "apple,i2c";</div><div class='add'>+			reg = &lt;0x2 0x0a112000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 208 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c2_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			power-domains = &lt;&amp;ps_i2c2&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmgr: power-management@20e000000 {</div><div class='add'>+			compatible = "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			reg = &lt;0x2 0xe000000 0 0x8c000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aic: interrupt-controller@20e100000 {</div><div class='add'>+			compatible = "apple,s8000-aic", "apple,aic";</div><div class='add'>+			reg = &lt;0x2 0x0e100000 0x0 0x100000&gt;;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			power-domains = &lt;&amp;ps_aic&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dwi_bl: backlight@20e200080 {</div><div class='add'>+			compatible = "apple,s8000-dwi-bl", "apple,dwi-bl";</div><div class='add'>+			reg = &lt;0x2 0x0e200080 0x0 0x8&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_dwi&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_ap: pinctrl@20f100000 {</div><div class='add'>+			compatible = "apple,s8000-pinctrl", "apple,pinctrl";</div><div class='add'>+			reg = &lt;0x2 0x0f100000 0x0 0x100000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_gpio&gt;;</div><div class='add'>+</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;pinctrl_ap 0 0 208&gt;;</div><div class='add'>+			apple,npins = &lt;208&gt;;</div><div class='add'>+</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 42 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 43 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 44 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 45 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 46 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 47 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 48 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			i2c0_pins: i2c0-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(46, 1)&gt;,</div><div class='add'>+					 &lt;APPLE_PINMUX(45, 1)&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c1_pins: i2c1-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(115, 1)&gt;,</div><div class='add'>+					 &lt;APPLE_PINMUX(114, 1)&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c2_pins: i2c2-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(23, 1)&gt;,</div><div class='add'>+					 &lt;APPLE_PINMUX(22, 1)&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_aop: pinctrl@2100f0000 {</div><div class='add'>+			compatible = "apple,s8000-pinctrl", "apple,pinctrl";</div><div class='add'>+			reg = &lt;0x2 0x100f0000 0x0 0x100000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_aop_gpio&gt;;</div><div class='add'>+</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;pinctrl_aop 0 0 42&gt;;</div><div class='add'>+			apple,npins = &lt;42&gt;;</div><div class='add'>+</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 113 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 114 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 115 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 116 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 117 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 118 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 119 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmgr_mini: power-management@210200000 {</div><div class='add'>+			compatible = "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			reg = &lt;0x2 0x10200000 0 0x84000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wdt: watchdog@2102b0000 {</div><div class='add'>+			compatible = "apple,s8000-wdt", "apple,wdt";</div><div class='add'>+			reg = &lt;0x2 0x102b0000 0x0 0x4000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 4 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupt-names = "phys", "virt";</div><div class='add'>+		/* Note that A9 doesn't actually have a hypervisor (EL2 is not implemented). */</div><div class='add'>+		interrupts = &lt;AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include "s800-0-3-pmgr.dtsi"</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * The A9 was made by two separate fabs on two different process</div><div class='add'>+ * nodes: Samsung made the S8000 (APL0898) on 14nm and TSMC made</div><div class='add'>+ * the S8003 (APL1022) on 16nm. There are some minor differences</div><div class='add'>+ * such as timing in cpufreq state transistions.</div><div class='add'>+ */</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/s8000-j71s.dts b/arch/arm64/boot/dts/apple/s8000-j71s.dts<br/>new file mode 100644<br/>index 000000000000..b5a2dfa1121e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/s8000-j71s.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/s8000-j71s.dts</a></div><div class='hunk'>@@ -0,0 +1,15 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPad 5 (Wi-Fi) (Samsung), J71s, iPad6,11 (A1822)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "s8000.dtsi"</div><div class='add'>+#include "s800x-ipad5.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j71s", "apple,s8000", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPad 5 (Wi-Fi) (Samsung)";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/s8000-j72s.dts b/arch/arm64/boot/dts/apple/s8000-j72s.dts<br/>new file mode 100644<br/>index 000000000000..8f3dea5adb09<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/s8000-j72s.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/s8000-j72s.dts</a></div><div class='hunk'>@@ -0,0 +1,15 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPad 5 (Cellular) (Samsung), J72s, iPad6,12 (A1823)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "s8000.dtsi"</div><div class='add'>+#include "s800x-ipad5.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j72s", "apple,s8000", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPad 5 (Cellular) (Samsung)";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/s8000-n66.dts b/arch/arm64/boot/dts/apple/s8000-n66.dts<br/>new file mode 100644<br/>index 000000000000..30b4b6630b60<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/s8000-n66.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/s8000-n66.dts</a></div><div class='hunk'>@@ -0,0 +1,15 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPhone 6s Plus (Samsung), N66, iPhone8,2 (A1634/A1687/A1690/A1699)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "s8000.dtsi"</div><div class='add'>+#include "s800x-6s.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,n66", "apple,s8000", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPhone 6s Plus (Samsung)";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/s8000-n69u.dts b/arch/arm64/boot/dts/apple/s8000-n69u.dts<br/>new file mode 100644<br/>index 000000000000..e63bc2e7f7c1<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/s8000-n69u.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/s8000-n69u.dts</a></div><div class='hunk'>@@ -0,0 +1,15 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPhone SE (Samsung), N69u, iPhone8,4 (A1662/A1723/A1724)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "s8000.dtsi"</div><div class='add'>+#include "s800x-se.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,n69u", "apple,s8000", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPhone SE (Samsung)";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/s8000-n71.dts b/arch/arm64/boot/dts/apple/s8000-n71.dts<br/>new file mode 100644<br/>index 000000000000..f2964a1fc434<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/s8000-n71.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/s8000-n71.dts</a></div><div class='hunk'>@@ -0,0 +1,15 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPhone 6s (Samsung), N71, iPhone8,1 (A1633/A1688/A1691/A1700)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "s8000.dtsi"</div><div class='add'>+#include "s800x-6s.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,n71", "apple,s8000", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPhone 6s (Samsung)";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/s8000.dtsi b/arch/arm64/boot/dts/apple/s8000.dtsi<br/>new file mode 100644<br/>index 000000000000..72322f5677ab<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/s8000.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/s8000.dtsi</a></div><div class='hunk'>@@ -0,0 +1,68 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple S8000 "A9" (Samsung) SoC</div><div class='add'>+ *</div><div class='add'>+ * Other names: H8P, "Maui"</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2024, Nick Chan &lt;towinchenmi@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "s800-0-3.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	twister_opp: opp-table {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		opp01 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;300000000&gt;;</div><div class='add'>+			opp-level = &lt;1&gt;;</div><div class='add'>+			clock-latency-ns = &lt;650&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp02 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;396000000&gt;;</div><div class='add'>+			opp-level = &lt;2&gt;;</div><div class='add'>+			clock-latency-ns = &lt;75000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp03 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;600000000&gt;;</div><div class='add'>+			opp-level = &lt;3&gt;;</div><div class='add'>+			clock-latency-ns = &lt;27000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp04 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;912000000&gt;;</div><div class='add'>+			opp-level = &lt;4&gt;;</div><div class='add'>+			clock-latency-ns = &lt;32000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp05 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1200000000&gt;;</div><div class='add'>+			opp-level = &lt;5&gt;;</div><div class='add'>+			clock-latency-ns = &lt;35000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp06 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1512000000&gt;;</div><div class='add'>+			opp-level = &lt;6&gt;;</div><div class='add'>+			clock-latency-ns = &lt;45000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp07 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1800000000&gt;;</div><div class='add'>+			opp-level = &lt;7&gt;;</div><div class='add'>+			clock-latency-ns = &lt;58000&gt;;</div><div class='add'>+		};</div><div class='add'>+#if 0</div><div class='add'>+		/* Not available until CPU deep sleep is implemented */</div><div class='add'>+		opp08 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1844000000&gt;;</div><div class='add'>+			opp-level = &lt;8&gt;;</div><div class='add'>+			clock-latency-ns = &lt;58000&gt;;</div><div class='add'>+			turbo-mode;</div><div class='add'>+		};</div><div class='add'>+#endif</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * The A9 was made by two separate fabs on two different process</div><div class='add'>+ * nodes: Samsung made the S8000 (APL0898) on 14nm and TSMC made</div><div class='add'>+ * the S8003 (APL1022) on 16nm. There are some minor differences</div><div class='add'>+ * such as timing in cpufreq state transistions.</div><div class='add'>+ */</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/s8001-common.dtsi b/arch/arm64/boot/dts/apple/s8001-common.dtsi<br/>new file mode 100644<br/>index 000000000000..91b06e113894<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/s8001-common.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/s8001-common.dtsi</a></div><div class='hunk'>@@ -0,0 +1,49 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPad Pro (9.7-inch), iPad Pro (12.9-inch)</div><div class='add'>+ *</div><div class='add'>+ * This file contains parts common to all Apple A9X devices.</div><div class='add'>+ *</div><div class='add'>+ * target-type: J127, J128, J98a, J99a</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2024, Nick Chan &lt;towinchenmi@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;serial0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		stdout-path = "serial0";</div><div class='add'>+</div><div class='add'>+		framebuffer0: framebuffer@0 {</div><div class='add'>+			compatible = "apple,simple-framebuffer", "simple-framebuffer";</div><div class='add'>+			reg = &lt;0 0 0 0&gt;; /* To be filled by loader */</div><div class='add'>+			power-domains = &lt;&amp;ps_disp0 &amp;ps_dp0&gt;;</div><div class='add'>+			/* Format properties will be added by loader */</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@800000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x8 0 0 0&gt;; /* To be filled by loader */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		/* To be filled by loader */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;serial0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/s8001-j127.dts b/arch/arm64/boot/dts/apple/s8001-j127.dts<br/>new file mode 100644<br/>index 000000000000..8b522085cb3e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/s8001-j127.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/s8001-j127.dts</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPad Pro (9.7-inch) (Wi-Fi), J127, iPad6,3 (A1673)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "s8001-pro.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j127", "apple,s8001", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPad Pro (9.7-inch) (Wi-Fi)";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/s8001-j128.dts b/arch/arm64/boot/dts/apple/s8001-j128.dts<br/>new file mode 100644<br/>index 000000000000..cdd3d06dcbf1<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/s8001-j128.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/s8001-j128.dts</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPad Pro (9.7-inch) (Cellular), J128, iPad6,4 (A1674/A1675)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "s8001-pro.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j128", "apple,s8001", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPad Pro (9.7-inch) (Cellular)";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/s8001-j98a-j99a.dtsi b/arch/arm64/boot/dts/apple/s8001-j98a-j99a.dtsi<br/>new file mode 100644<br/>index 000000000000..e66a4c1c138f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/s8001-j98a-j99a.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/s8001-j98a-j99a.dtsi</a></div><div class='hunk'>@@ -0,0 +1,26 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPad Pro (12.9-inch)</div><div class='add'>+ *</div><div class='add'>+ * This file contains parts common to iPad Pro (12.9-inch).</div><div class='add'>+ *</div><div class='add'>+ * target-type: J98a, J99a</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2024, Nick Chan &lt;towinchenmi@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;ps_dcs4 {</div><div class='add'>+	apple,always-on; /* LPDDR4 interface */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ps_dcs5 {</div><div class='add'>+	apple,always-on; /* LPDDR4 interface */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ps_dcs6 {</div><div class='add'>+	apple,always-on; /* LPDDR4 interface */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ps_dcs7 {</div><div class='add'>+	apple,always-on; /* LPDDR4 interface */</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/s8001-j98a.dts b/arch/arm64/boot/dts/apple/s8001-j98a.dts<br/>new file mode 100644<br/>index 000000000000..162eca05c2d9<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/s8001-j98a.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/s8001-j98a.dts</a></div><div class='hunk'>@@ -0,0 +1,15 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPad Pro (12.9-inch) (Wi-Fi), J98a, iPad6,7 (A1584)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "s8001-pro.dtsi"</div><div class='add'>+#include "s8001-j98a-j99a.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j98a", "apple,s8001", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPad Pro (12.9-inch) (Wi-Fi)";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/s8001-j99a.dts b/arch/arm64/boot/dts/apple/s8001-j99a.dts<br/>new file mode 100644<br/>index 000000000000..7b765820c69e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/s8001-j99a.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/s8001-j99a.dts</a></div><div class='hunk'>@@ -0,0 +1,15 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPad Pro (12.9-inch) (Cellular), J99a, iPad6,8 (A1652)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "s8001-pro.dtsi"</div><div class='add'>+#include "s8001-j98a-j99a.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j99a", "apple,s8001", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPad Pro (12.9-inch) (Cellular)";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/s8001-pmgr.dtsi b/arch/arm64/boot/dts/apple/s8001-pmgr.dtsi<br/>new file mode 100644<br/>index 000000000000..859ab77ae92b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/s8001-pmgr.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/s8001-pmgr.dtsi</a></div><div class='hunk'>@@ -0,0 +1,822 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * PMGR Power domains for the Apple S8001 "A9X" SoC</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2024 Nick Chan &lt;towinchenmi@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;pmgr {</div><div class='add'>+	ps_cpu0: power-controller@80000 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80000 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "cpu0";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_cpu1: power-controller@80008 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80008 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "cpu1";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_cpm: power-controller@80040 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80040 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "cpm";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sio_busif: power-controller@80148 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80148 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sio_busif";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sio_p: power-controller@80150 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80150 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sio_p";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_busif&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sbr: power-controller@80100 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80100 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sbr";</div><div class='add'>+		apple,always-on; /* Apple fabric, critical block */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_aic: power-controller@80108 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80108 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "aic";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dwi: power-controller@80110 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80110 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dwi";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_gpio: power-controller@80118 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80118 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "gpio";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pcie_ref: power-controller@80140 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80140 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pcie_ref";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca0: power-controller@80160 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80160 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca1: power-controller@80168 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80168 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca1";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca2: power-controller@80170 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80170 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca2";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca3: power-controller@80178 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80178 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca3";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca4: power-controller@80180 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80180 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca4";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pwm0: power-controller@80188 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80188 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pwm0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c0: power-controller@80190 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80190 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c1: power-controller@80198 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80198 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c1";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c2: power-controller@801a0 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801a0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c2";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c3: power-controller@801a8 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801a8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c3";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi0: power-controller@801b0 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801b0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi1: power-controller@801b8 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801b8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi1";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi2: power-controller@801c0 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801c0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi2";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi3: power-controller@801c8 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801c8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi3";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart0: power-controller@801d0 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801d0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart1: power-controller@801d8 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801d8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart1";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart2: power-controller@801e0 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801e0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart2";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart3: power-controller@801e8 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801e8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart3";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart4: power-controller@801f0 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801f0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart4";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart5: power-controller@801f8 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801f8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart5";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sio: power-controller@80158 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80158 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sio";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_hsic0_phy: power-controller@80128 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80128 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "hsic0_phy";</div><div class='add'>+		power-domains = &lt;&amp;ps_usb2host1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_isp_sens0: power-controller@80130 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80130 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "isp_sens0";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_isp_sens1: power-controller@80138 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80138 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "isp_sens1";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pms: power-controller@80120 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80120 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pms";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usb: power-controller@80278 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80278 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usb";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usbctrl: power-controller@80280 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80280 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usbctrl";</div><div class='add'>+		power-domains = &lt;&amp;ps_usb&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usb2host0: power-controller@80288 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80288 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usb2host0";</div><div class='add'>+		power-domains = &lt;&amp;ps_usbctrl&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usb2host1: power-controller@80298 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80298 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usb2host1";</div><div class='add'>+		power-domains = &lt;&amp;ps_usbctrl&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usb2host2: power-controller@802a8 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802a8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usb2host2";</div><div class='add'>+		power-domains = &lt;&amp;ps_usbctrl&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_rtmux: power-controller@802d0 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802d0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "rtmux";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_disp1mux: power-controller@802e8 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802e8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "disp1mux";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_disp0: power-controller@802d8 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802d8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "disp0";</div><div class='add'>+		power-domains = &lt;&amp;ps_rtmux&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_disp1: power-controller@802f0 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802f0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "disp1";</div><div class='add'>+		power-domains = &lt;&amp;ps_disp1mux&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart6: power-controller@80200 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80200 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart6";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart7: power-controller@80208 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80208 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart7";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart8: power-controller@80210 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80210 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart8";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_aes0: power-controller@80218 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80218 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "aes0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mcc: power-controller@80230 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80230 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mcc";</div><div class='add'>+		apple,always-on; /* Memory cache controller */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs0: power-controller@80238 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80238 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs0";</div><div class='add'>+		apple,always-on; /* LPDDR4 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs1: power-controller@80240 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80240 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs1";</div><div class='add'>+		apple,always-on; /* LPDDR4 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs2: power-controller@80248 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80248 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs2";</div><div class='add'>+		apple,always-on; /* LPDDR4 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs3: power-controller@80250 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80250 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs3";</div><div class='add'>+		apple,always-on; /* LPDDR4 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs4: power-controller@80258 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80258 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs4";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs5: power-controller@80260 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80260 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs5";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs6: power-controller@80268 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80268 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs6";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs7: power-controller@80270 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80270 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs7";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usb2host0_ohci: power-controller@80290 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80290 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usb2host0_ohci";</div><div class='add'>+		power-domains = &lt;&amp;ps_usb2host0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usbotg: power-controller@802b8 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802b8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usbotg";</div><div class='add'>+		power-domains = &lt;&amp;ps_usbctrl&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_smx: power-controller@802c0 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802c0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "smx";</div><div class='add'>+		apple,always-on; /* Apple fabric, critical block */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sf: power-controller@802c8 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802c8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sf";</div><div class='add'>+		apple,always-on; /* Apple fabric, critical block */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dp0: power-controller@802e0 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802e0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dp0";</div><div class='add'>+		power-domains = &lt;&amp;ps_disp0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dp1: power-controller@802f8 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802f8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dp1";</div><div class='add'>+		power-domains = &lt;&amp;ps_disp1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dpa0: power-controller@80220 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80220 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dpa0";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dpa1: power-controller@80228 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80228 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dpa1";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_media: power-controller@80308 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80308 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "media";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_isp: power-controller@80300 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80300 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "isp";</div><div class='add'>+		power-domains = &lt;&amp;ps_rtmux&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_msr: power-controller@80318 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80318 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "msr";</div><div class='add'>+		power-domains = &lt;&amp;ps_media&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_jpg: power-controller@80310 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80310 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "jpg";</div><div class='add'>+		power-domains = &lt;&amp;ps_media&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc: power-controller@80340 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80340 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc";</div><div class='add'>+		power-domains = &lt;&amp;ps_media&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pcie: power-controller@80348 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80348 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pcie";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_srs: power-controller@80390 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80390 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "srs";</div><div class='add'>+		power-domains = &lt;&amp;ps_media&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pcie_aux: power-controller@80350 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80350 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pcie_aux";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pcie_link0: power-controller@80358 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80358 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pcie_link0";</div><div class='add'>+		power-domains = &lt;&amp;ps_pcie&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pcie_link1: power-controller@80360 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80360 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pcie_link1";</div><div class='add'>+		power-domains = &lt;&amp;ps_pcie&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pcie_link2: power-controller@80368 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80368 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pcie_link2";</div><div class='add'>+		power-domains = &lt;&amp;ps_pcie&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pcie_link3: power-controller@80370 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80370 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pcie_link3";</div><div class='add'>+		power-domains = &lt;&amp;ps_pcie&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pcie_link4: power-controller@80378 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80378 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pcie_link4";</div><div class='add'>+		power-domains = &lt;&amp;ps_pcie&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pcie_link5: power-controller@80380 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80380 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pcie_link5";</div><div class='add'>+		power-domains = &lt;&amp;ps_pcie&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_vdec: power-controller@80330 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80330 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "vdec";</div><div class='add'>+		power-domains = &lt;&amp;ps_media&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_gfx: power-controller@80388 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80388 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "gfx";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pmp: power-controller@80320 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80320 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pmp";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pms_sram: power-controller@80328 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80328 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pms_sram";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sep: power-controller@80400 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80400 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sep";</div><div class='add'>+		apple,always-on; /* Locked on*/</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc_pipe: power-controller@88000 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x88000 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc_pipe";</div><div class='add'>+		power-domains = &lt;&amp;ps_venc&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc_me0: power-controller@88008 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x88008 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc_me0";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc_me1: power-controller@88010 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x88010 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc_me1";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pmgr_mini {</div><div class='add'>+	ps_aop: power-controller@80000 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80000 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "aop";</div><div class='add'>+		power-domains = &lt;&amp;ps_aop_cpu &amp;ps_aop_filter &amp;ps_aop_busif&gt;;</div><div class='add'>+		apple,always-on; /* Always on processor */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_debug: power-controller@80008 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80008 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "debug";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_aop_gpio: power-controller@80010 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80010 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "aop_gpio";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_aop_cpu: power-controller@80040 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80040 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "aop_cpu";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_aop_filter: power-controller@80048 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80048 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "aop_filter";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_aop_busif: power-controller@80050 {</div><div class='add'>+		compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80050 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "aop_busif";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/s8001-pro.dtsi b/arch/arm64/boot/dts/apple/s8001-pro.dtsi<br/>new file mode 100644<br/>index 000000000000..1fce5a7c4200<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/s8001-pro.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/s8001-pro.dtsi</a></div><div class='hunk'>@@ -0,0 +1,44 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPad Pro (1st generation) common device tree</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "s8001.dtsi"</div><div class='add'>+#include "s8001-common.dtsi"</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	chassis-type = "tablet";</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		button-home {</div><div class='add'>+			label = "Home Button";</div><div class='add'>+			gpios = &lt;&amp;pinctrl_ap 122 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_HOMEPAGE&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-power {</div><div class='add'>+			label = "Power Button";</div><div class='add'>+			gpios = &lt;&amp;pinctrl_ap 123 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-voldown {</div><div class='add'>+			label = "Volume Down";</div><div class='add'>+			gpios = &lt;&amp;pinctrl_ap 15 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-volup {</div><div class='add'>+			label = "Volume Up";</div><div class='add'>+			gpios = &lt;&amp;pinctrl_ap 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/s8001.dtsi b/arch/arm64/boot/dts/apple/s8001.dtsi<br/>new file mode 100644<br/>index 000000000000..b5b00dca6ffa<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/s8001.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/s8001.dtsi</a></div><div class='hunk'>@@ -0,0 +1,303 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple S8001 "A9X" SoC</div><div class='add'>+ *</div><div class='add'>+ * Other names: H8G, "Elba"</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/apple-aic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/apple.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	clkref: clock-ref {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+		clock-output-names = "clkref";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			compatible = "apple,twister";</div><div class='add'>+			reg = &lt;0x0 0x0&gt;;</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled in by loader */</div><div class='add'>+			operating-points-v2 = &lt;&amp;twister_opp&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache&gt;;</div><div class='add'>+			i-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@1 {</div><div class='add'>+			compatible = "apple,twister";</div><div class='add'>+			reg = &lt;0x0 0x1&gt;;</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled in by loader */</div><div class='add'>+			operating-points-v2 = &lt;&amp;twister_opp&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache&gt;;</div><div class='add'>+			i-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_cache: l2-cache {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x300000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	twister_opp: opp-table {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		opp01 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;300000000&gt;;</div><div class='add'>+			opp-level = &lt;1&gt;;</div><div class='add'>+			clock-latency-ns = &lt;800&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp02 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;396000000&gt;;</div><div class='add'>+			opp-level = &lt;2&gt;;</div><div class='add'>+			clock-latency-ns = &lt;53000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp03 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;792000000&gt;;</div><div class='add'>+			opp-level = &lt;3&gt;;</div><div class='add'>+			clock-latency-ns = &lt;18000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp04 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1080000000&gt;;</div><div class='add'>+			opp-level = &lt;4&gt;;</div><div class='add'>+			clock-latency-ns = &lt;21000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp05 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1440000000&gt;;</div><div class='add'>+			opp-level = &lt;5&gt;;</div><div class='add'>+			clock-latency-ns = &lt;25000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp06 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1800000000&gt;;</div><div class='add'>+			opp-level = &lt;6&gt;;</div><div class='add'>+			clock-latency-ns = &lt;33000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp07 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2160000000&gt;;</div><div class='add'>+			opp-level = &lt;7&gt;;</div><div class='add'>+			clock-latency-ns = &lt;45000&gt;;</div><div class='add'>+		};</div><div class='add'>+#if 0</div><div class='add'>+		/* Not available until CPU deep sleep is implemented */</div><div class='add'>+		opp08 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2160000000&gt;;</div><div class='add'>+			opp-level = &lt;8&gt;;</div><div class='add'>+			clock-latency-ns = &lt;45000&gt;;</div><div class='add'>+			turbo-mode;</div><div class='add'>+		};</div><div class='add'>+#endif</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		nonposted-mmio;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		cpufreq: performance-controller@202220000 {</div><div class='add'>+			compatible = "apple,s8000-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";</div><div class='add'>+			reg = &lt;0x2 0x02220000 0 0x1000&gt;;</div><div class='add'>+			#performance-domain-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		serial0: serial@20a0c0000 {</div><div class='add'>+			compatible = "apple,s5l-uart";</div><div class='add'>+			reg = &lt;0x2 0x0a0c0000 0x0 0x4000&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 218 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			/* Use the bootloader-enabled clocks for now. */</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;, &lt;&amp;clkref&gt;;</div><div class='add'>+			clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+			power-domains = &lt;&amp;ps_uart0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c0: i2c@20a110000 {</div><div class='add'>+			compatible = "apple,s8000-i2c", "apple,i2c";</div><div class='add'>+			reg = &lt;0x2 0x0a110000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 232 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c0_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			power-domains = &lt;&amp;ps_i2c0&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c1: i2c@20a111000 {</div><div class='add'>+			compatible = "apple,s8000-i2c", "apple,i2c";</div><div class='add'>+			reg = &lt;0x2 0x0a111000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 233 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c1_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			power-domains = &lt;&amp;ps_i2c1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c2: i2c@20a112000 {</div><div class='add'>+			compatible = "apple,s8000-i2c", "apple,i2c";</div><div class='add'>+			reg = &lt;0x2 0x0a112000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 234 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c2_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			power-domains = &lt;&amp;ps_i2c2&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c3: i2c@20a113000 {</div><div class='add'>+			compatible = "apple,s8000-i2c", "apple,i2c";</div><div class='add'>+			reg = &lt;0x2 0x0a113000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 235 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c3_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			power-domains = &lt;&amp;ps_i2c3&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmgr: power-management@20e000000 {</div><div class='add'>+			compatible = "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			reg = &lt;0x2 0xe000000 0 0x8c000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aic: interrupt-controller@20e100000 {</div><div class='add'>+			compatible = "apple,s8000-aic", "apple,aic";</div><div class='add'>+			reg = &lt;0x2 0x0e100000 0x0 0x100000&gt;;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			power-domains = &lt;&amp;ps_aic&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_ap: pinctrl@20f100000 {</div><div class='add'>+			compatible = "apple,s8000-pinctrl", "apple,pinctrl";</div><div class='add'>+			reg = &lt;0x2 0x0f100000 0x0 0x100000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_gpio&gt;;</div><div class='add'>+</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;pinctrl_ap 0 0 219&gt;;</div><div class='add'>+			apple,npins = &lt;219&gt;;</div><div class='add'>+</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 42 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 43 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 44 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 45 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 46 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 47 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 48 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			i2c0_pins: i2c0-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(165, 1)&gt;,</div><div class='add'>+					 &lt;APPLE_PINMUX(164, 1)&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c1_pins: i2c1-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(178, 1)&gt;,</div><div class='add'>+					 &lt;APPLE_PINMUX(177, 1)&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c2_pins: i2c2-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(132, 1)&gt;,</div><div class='add'>+					 &lt;APPLE_PINMUX(131, 1)&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c3_pins: i2c3-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(115, 1)&gt;,</div><div class='add'>+					 &lt;APPLE_PINMUX(114, 1)&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_aop: pinctrl@2100f0000 {</div><div class='add'>+			compatible = "apple,s8000-pinctrl", "apple,pinctrl";</div><div class='add'>+			reg = &lt;0x2 0x100f0000 0x0 0x100000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_aop_gpio&gt;;</div><div class='add'>+</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;pinctrl_aop 0 0 28&gt;;</div><div class='add'>+			apple,npins = &lt;28&gt;;</div><div class='add'>+</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 128 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 129 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 130 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 131 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 132 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 133 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 134 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmgr_mini: power-management@210200000 {</div><div class='add'>+			compatible = "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			reg = &lt;0x2 0x10200000 0 0x84000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wdt: watchdog@2102b0000 {</div><div class='add'>+			compatible = "apple,s8000-wdt", "apple,wdt";</div><div class='add'>+			reg = &lt;0x2 0x102b0000 0x0 0x4000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 4 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupt-names = "phys", "virt";</div><div class='add'>+		/* Note that A9X doesn't actually have a hypervisor (EL2 is not implemented). */</div><div class='add'>+		interrupts = &lt;AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include "s8001-pmgr.dtsi"</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/s8003-j71t.dts b/arch/arm64/boot/dts/apple/s8003-j71t.dts<br/>new file mode 100644<br/>index 000000000000..0d906ae80b07<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/s8003-j71t.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/s8003-j71t.dts</a></div><div class='hunk'>@@ -0,0 +1,15 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPad 5 (Wi-Fi) (TSMC), J71t, iPad6,11 (A1822)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "s8003.dtsi"</div><div class='add'>+#include "s800x-ipad5.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j71t", "apple,s8003", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPad 5 (Wi-Fi) (TSMC)";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/s8003-j72t.dts b/arch/arm64/boot/dts/apple/s8003-j72t.dts<br/>new file mode 100644<br/>index 000000000000..0cd7d88e9dfb<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/s8003-j72t.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/s8003-j72t.dts</a></div><div class='hunk'>@@ -0,0 +1,15 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPad 5 (Cellular) (TSMC), J72t, iPad6,12 (A1823)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "s8003.dtsi"</div><div class='add'>+#include "s800x-ipad5.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j72t", "apple,s8003", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPad 5 (Cellular) (TSMC)";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/s8003-n66m.dts b/arch/arm64/boot/dts/apple/s8003-n66m.dts<br/>new file mode 100644<br/>index 000000000000..4146cd28160d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/s8003-n66m.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/s8003-n66m.dts</a></div><div class='hunk'>@@ -0,0 +1,15 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPhone 6s Plus (TSMC), N66m, iPhone8,2 (A1634/A1687/A1690/A1699)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "s8003.dtsi"</div><div class='add'>+#include "s800x-6s.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,n66m", "apple,s8003", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPhone 6s Plus (TSMC)";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/s8003-n69.dts b/arch/arm64/boot/dts/apple/s8003-n69.dts<br/>new file mode 100644<br/>index 000000000000..8eed879b155e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/s8003-n69.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/s8003-n69.dts</a></div><div class='hunk'>@@ -0,0 +1,15 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPhone SE (TSMC), N69, iPhone8,4 (A1662/A1723/A1724)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "s8003.dtsi"</div><div class='add'>+#include "s800x-se.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,n69", "apple,s8003", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPhone SE (TSMC)";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/s8003-n71m.dts b/arch/arm64/boot/dts/apple/s8003-n71m.dts<br/>new file mode 100644<br/>index 000000000000..7ec6d2cda0bf<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/s8003-n71m.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/s8003-n71m.dts</a></div><div class='hunk'>@@ -0,0 +1,15 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPhone 6s (TSMC), N71m, iPhone8,1 (A1633/A1688/A1691/A1700)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "s8003.dtsi"</div><div class='add'>+#include "s800x-6s.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,n71m", "apple,s8003", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPhone 6s (TSMC)";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/s8003.dtsi b/arch/arm64/boot/dts/apple/s8003.dtsi<br/>new file mode 100644<br/>index 000000000000..79df5c783260<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/s8003.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/s8003.dtsi</a></div><div class='hunk'>@@ -0,0 +1,68 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple S8003 "A9" (TSMC) SoC</div><div class='add'>+ *</div><div class='add'>+ * Other names: H8P, "Malta"</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2024, Nick Chan &lt;towinchenmi@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "s800-0-3.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	twister_opp: opp-table {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		opp01 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;300000000&gt;;</div><div class='add'>+			opp-level = &lt;1&gt;;</div><div class='add'>+			clock-latency-ns = &lt;500&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp02 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;396000000&gt;;</div><div class='add'>+			opp-level = &lt;2&gt;;</div><div class='add'>+			clock-latency-ns = &lt;45000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp03 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;600000000&gt;;</div><div class='add'>+			opp-level = &lt;3&gt;;</div><div class='add'>+			clock-latency-ns = &lt;22000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp04 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;912000000&gt;;</div><div class='add'>+			opp-level = &lt;4&gt;;</div><div class='add'>+			clock-latency-ns = &lt;25000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp05 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1200000000&gt;;</div><div class='add'>+			opp-level = &lt;5&gt;;</div><div class='add'>+			clock-latency-ns = &lt;28000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp06 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1512000000&gt;;</div><div class='add'>+			opp-level = &lt;6&gt;;</div><div class='add'>+			clock-latency-ns = &lt;35000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp07 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1800000000&gt;;</div><div class='add'>+			opp-level = &lt;7&gt;;</div><div class='add'>+			clock-latency-ns = &lt;38000&gt;;</div><div class='add'>+		};</div><div class='add'>+#if 0</div><div class='add'>+		/* Not available until CPU deep sleep is implemented */</div><div class='add'>+		opp08 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1844000000&gt;;</div><div class='add'>+			opp-level = &lt;8&gt;;</div><div class='add'>+			clock-latency-ns = &lt;38000&gt;;</div><div class='add'>+			turbo-mode;</div><div class='add'>+		};</div><div class='add'>+#endif</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * The A9 was made by two separate fabs on two different process</div><div class='add'>+ * nodes: Samsung made the S8000 (APL0898) on 14nm and TSMC made</div><div class='add'>+ * the S8003 (APL1022) on 16nm. There are some minor differences</div><div class='add'>+ * such as timing in cpufreq state transistions.</div><div class='add'>+ */</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/s800x-6s.dtsi b/arch/arm64/boot/dts/apple/s800x-6s.dtsi<br/>new file mode 100644<br/>index 000000000000..1dcf80cc2920<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/s800x-6s.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/s800x-6s.dtsi</a></div><div class='hunk'>@@ -0,0 +1,53 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPhone 6s / 6S Plus common device tree</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "s800-0-3-common.dtsi"</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	chassis-type = "handset";</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		button-home {</div><div class='add'>+			label = "Home Button";</div><div class='add'>+			gpios = &lt;&amp;pinctrl_ap 96 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_HOMEPAGE&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-power {</div><div class='add'>+			label = "Power Button";</div><div class='add'>+			gpios = &lt;&amp;pinctrl_ap 97 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-voldown {</div><div class='add'>+			label = "Volume Down";</div><div class='add'>+			gpios = &lt;&amp;pinctrl_ap 67 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-volup {</div><div class='add'>+			label = "Volume Up";</div><div class='add'>+			gpios = &lt;&amp;pinctrl_ap 66 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		switch-mute {</div><div class='add'>+			label = "Mute Switch";</div><div class='add'>+			gpios = &lt;&amp;pinctrl_ap 149 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_MUTE&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;framebuffer0 {</div><div class='add'>+	power-domains = &lt;&amp;ps_disp0 &amp;ps_mipi_dsi&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/s800x-ipad5.dtsi b/arch/arm64/boot/dts/apple/s800x-ipad5.dtsi<br/>new file mode 100644<br/>index 000000000000..c1701e81f0c1<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/s800x-ipad5.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/s800x-ipad5.dtsi</a></div><div class='hunk'>@@ -0,0 +1,47 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPad 5 common device tree</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "s800-0-3-common.dtsi"</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	chassis-type = "tablet";</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		button-home {</div><div class='add'>+			label = "Home Button";</div><div class='add'>+			gpios = &lt;&amp;pinctrl_ap 96 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_HOMEPAGE&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-power {</div><div class='add'>+			label = "Power Button";</div><div class='add'>+			gpios = &lt;&amp;pinctrl_ap 97 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-voldown {</div><div class='add'>+			label = "Volume Down";</div><div class='add'>+			gpios = &lt;&amp;pinctrl_ap 143 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-volup {</div><div class='add'>+			label = "Volume Up";</div><div class='add'>+			gpios = &lt;&amp;pinctrl_ap 144 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;framebuffer0 {</div><div class='add'>+	power-domains = &lt;&amp;ps_disp0 &amp;ps_dp&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/s800x-se.dtsi b/arch/arm64/boot/dts/apple/s800x-se.dtsi<br/>new file mode 100644<br/>index 000000000000..deb7c7cc90f6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/s800x-se.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/s800x-se.dtsi</a></div><div class='hunk'>@@ -0,0 +1,53 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPhone SE common device tree</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "s800-0-3-common.dtsi"</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	chassis-type = "handset";</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		button-home {</div><div class='add'>+			label = "Home Button";</div><div class='add'>+			gpios = &lt;&amp;pinctrl_ap 96 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_HOMEPAGE&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-power {</div><div class='add'>+			label = "Power Button";</div><div class='add'>+			gpios = &lt;&amp;pinctrl_ap 97 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-voldown {</div><div class='add'>+			label = "Volume Down";</div><div class='add'>+			gpios = &lt;&amp;pinctrl_ap 67 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-volup {</div><div class='add'>+			label = "Volume Up";</div><div class='add'>+			gpios = &lt;&amp;pinctrl_ap 66 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		switch-mute {</div><div class='add'>+			label = "Mute Switch";</div><div class='add'>+			gpios = &lt;&amp;pinctrl_ap 149 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_MUTE&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;framebuffer0 {</div><div class='add'>+	power-domains = &lt;&amp;ps_disp0 &amp;ps_mipi_dsi&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/spi1-nvram.dtsi b/arch/arm64/boot/dts/apple/spi1-nvram.dtsi<br/>new file mode 100644<br/>index 000000000000..9740fbf200f0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/spi1-nvram.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/spi1-nvram.dtsi</a></div><div class='hunk'>@@ -0,0 +1,37 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+//</div><div class='add'>+// Devicetree include for common spi-nor nvram flash.</div><div class='add'>+//</div><div class='add'>+// Apple uses a consistent configiguration for the nvram on all known M1* and</div><div class='add'>+// M2* devices.</div><div class='add'>+//</div><div class='add'>+// Copyright The Asahi Linux Contributors</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		nvram = &amp;nvram;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0x0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;25000000&gt;;</div><div class='add'>+</div><div class='add'>+		partitions {</div><div class='add'>+			compatible = "fixed-partitions";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			nvram: partition@700000 {</div><div class='add'>+				label = "nvram";</div><div class='add'>+				/* To be filled by the loader */</div><div class='add'>+				reg = &lt;0x0 0x0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t6000-j314s.dts b/arch/arm64/boot/dts/apple/t6000-j314s.dts<br/>new file mode 100644<br/>index 000000000000..1430b91ff1b1<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t6000-j314s.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t6000-j314s.dts</a></div><div class='hunk'>@@ -0,0 +1,26 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * MacBook Pro (14-inch, M1 Pro, 2021)</div><div class='add'>+ *</div><div class='add'>+ * target-type: J314s</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t6000.dtsi"</div><div class='add'>+#include "t600x-j314-j316.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j314s", "apple,t6000", "apple,arm-platform";</div><div class='add'>+	model = "Apple MacBook Pro (14-inch, M1 Pro, 2021)";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wifi0 {</div><div class='add'>+	brcm,board-type = "apple,maldives";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;bluetooth0 {</div><div class='add'>+	brcm,board-type = "apple,maldives";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t6000-j316s.dts b/arch/arm64/boot/dts/apple/t6000-j316s.dts<br/>new file mode 100644<br/>index 000000000000..da0cbe7d9673<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t6000-j316s.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t6000-j316s.dts</a></div><div class='hunk'>@@ -0,0 +1,26 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * MacBook Pro (16-inch, M1 Pro, 2021)</div><div class='add'>+ *</div><div class='add'>+ * target-type: J316s</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t6000.dtsi"</div><div class='add'>+#include "t600x-j314-j316.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j316s", "apple,t6000", "apple,arm-platform";</div><div class='add'>+	model = "Apple MacBook Pro (16-inch, M1 Pro, 2021)";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wifi0 {</div><div class='add'>+	brcm,board-type = "apple,madagascar";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;bluetooth0 {</div><div class='add'>+	brcm,board-type = "apple,madagascar";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t6000.dtsi b/arch/arm64/boot/dts/apple/t6000.dtsi<br/>new file mode 100644<br/>index 000000000000..0ad77c98073f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t6000.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t6000.dtsi</a></div><div class='hunk'>@@ -0,0 +1,22 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple T6000 "M1 Pro" SoC</div><div class='add'>+ *</div><div class='add'>+ * Other names: H13J, "Jade Chop"</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/* This chip is just a cut down version of t6001, so include it and disable the missing parts */</div><div class='add'>+</div><div class='add'>+#include "t6001.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,t6000", "apple,arm-platform";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/delete-node/ &amp;pmgr_south;</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	compatible = "apple,agx-g13s";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t6001-j314c.dts b/arch/arm64/boot/dts/apple/t6001-j314c.dts<br/>new file mode 100644<br/>index 000000000000..c37097dcfdb3<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t6001-j314c.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t6001-j314c.dts</a></div><div class='hunk'>@@ -0,0 +1,26 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * MacBook Pro (14-inch, M1 Max, 2021)</div><div class='add'>+ *</div><div class='add'>+ * target-type: J314c</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t6001.dtsi"</div><div class='add'>+#include "t600x-j314-j316.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j314c", "apple,t6001", "apple,arm-platform";</div><div class='add'>+	model = "Apple MacBook Pro (14-inch, M1 Max, 2021)";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wifi0 {</div><div class='add'>+	brcm,board-type = "apple,maldives";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;bluetooth0 {</div><div class='add'>+	brcm,board-type = "apple,maldives";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t6001-j316c.dts b/arch/arm64/boot/dts/apple/t6001-j316c.dts<br/>new file mode 100644<br/>index 000000000000..3bc6e0c3294c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t6001-j316c.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t6001-j316c.dts</a></div><div class='hunk'>@@ -0,0 +1,26 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * MacBook Pro (16-inch, M1 Max, 2021)</div><div class='add'>+ *</div><div class='add'>+ * target-type: J316c</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t6001.dtsi"</div><div class='add'>+#include "t600x-j314-j316.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j316c", "apple,t6001", "apple,arm-platform";</div><div class='add'>+	model = "Apple MacBook Pro (16-inch, M1 Max, 2021)";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wifi0 {</div><div class='add'>+	brcm,board-type = "apple,madagascar";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;bluetooth0 {</div><div class='add'>+	brcm,board-type = "apple,madagascar";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t6001-j375c.dts b/arch/arm64/boot/dts/apple/t6001-j375c.dts<br/>new file mode 100644<br/>index 000000000000..2e7c23714d4d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t6001-j375c.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t6001-j375c.dts</a></div><div class='hunk'>@@ -0,0 +1,26 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Mac Studio (M1 Max, 2022)</div><div class='add'>+ *</div><div class='add'>+ * target-type: J375c</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t6001.dtsi"</div><div class='add'>+#include "t600x-j375.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j375c", "apple,t6001", "apple,arm-platform";</div><div class='add'>+	model = "Apple Mac Studio (M1 Max, 2022)";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wifi0 {</div><div class='add'>+	brcm,board-type = "apple,okinawa";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;bluetooth0 {</div><div class='add'>+	brcm,board-type = "apple,okinawa";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t6001.dtsi b/arch/arm64/boot/dts/apple/t6001.dtsi<br/>new file mode 100644<br/>index 000000000000..ffbe823b71bc<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t6001.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t6001.dtsi</a></div><div class='hunk'>@@ -0,0 +1,68 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple T6001 "M1 Max" SoC</div><div class='add'>+ *</div><div class='add'>+ * Other names: H13J, "Jade"</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/apple-aic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/apple.h&gt;</div><div class='add'>+#include &lt;dt-bindings/spmi/spmi.h&gt;</div><div class='add'>+</div><div class='add'>+#include "multi-die-cpp.h"</div><div class='add'>+</div><div class='add'>+#include "t600x-common.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,t6001", "apple,arm-platform";</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		ranges;</div><div class='add'>+		nonposted-mmio;</div><div class='add'>+</div><div class='add'>+		// filled via templated includes at the end of the file</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define DIE</div><div class='add'>+#define DIE_NO 0</div><div class='add'>+</div><div class='add'>+&amp;{/soc} {</div><div class='add'>+	#include "t600x-die0.dtsi"</div><div class='add'>+	#include "t600x-dieX.dtsi"</div><div class='add'>+	#include "t600x-nvme.dtsi"</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include "t600x-gpio-pins.dtsi"</div><div class='add'>+#include "t600x-pmgr.dtsi"</div><div class='add'>+</div><div class='add'>+#undef DIE</div><div class='add'>+#undef DIE_NO</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+&amp;aic {</div><div class='add'>+	affinities {</div><div class='add'>+		e-core-pmu-affinity {</div><div class='add'>+			apple,fiq-index = &lt;AIC_CPU_PMU_E&gt;;</div><div class='add'>+			cpus = &lt;&amp;cpu_e00 &amp;cpu_e01&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		p-core-pmu-affinity {</div><div class='add'>+			apple,fiq-index = &lt;AIC_CPU_PMU_P&gt;;</div><div class='add'>+			cpus = &lt;&amp;cpu_p00 &amp;cpu_p01 &amp;cpu_p02 &amp;cpu_p03</div><div class='add'>+				&amp;cpu_p10 &amp;cpu_p11 &amp;cpu_p12 &amp;cpu_p13&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	compatible = "apple,agx-g13c", "apple,agx-g13s";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t6002-j375d.dts b/arch/arm64/boot/dts/apple/t6002-j375d.dts<br/>new file mode 100644<br/>index 000000000000..2b7f80119618<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t6002-j375d.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t6002-j375d.dts</a></div><div class='hunk'>@@ -0,0 +1,58 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Mac Studio (M1 Ultra, 2022)</div><div class='add'>+ *</div><div class='add'>+ * target-type: J375d</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t6002.dtsi"</div><div class='add'>+#include "t600x-j375.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j375d", "apple,t6002", "apple,arm-platform";</div><div class='add'>+	model = "Apple Mac Studio (M1 Ultra, 2022)";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB Type C */</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	/* front-right */</div><div class='add'>+	hpm4: usb-pd@39 {</div><div class='add'>+		compatible = "apple,cd321x";</div><div class='add'>+		reg = &lt;0x39&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;pinctrl_ap&gt;;</div><div class='add'>+		interrupts = &lt;174 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupt-names = "irq";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* front-left */</div><div class='add'>+	hpm5: usb-pd@3a {</div><div class='add'>+		compatible = "apple,cd321x";</div><div class='add'>+		reg = &lt;0x3a&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;pinctrl_ap&gt;;</div><div class='add'>+		interrupts = &lt;174 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupt-names = "irq";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wifi0 {</div><div class='add'>+	brcm,board-type = "apple,okinawa";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;bluetooth0 {</div><div class='add'>+	brcm,board-type = "apple,okinawa";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* delete unused always-on power-domains on die 1 */</div><div class='add'>+</div><div class='add'>+/delete-node/ &amp;ps_atc2_usb_aon_die1;</div><div class='add'>+/delete-node/ &amp;ps_atc2_usb_die1;</div><div class='add'>+</div><div class='add'>+/delete-node/ &amp;ps_atc3_usb_aon_die1;</div><div class='add'>+/delete-node/ &amp;ps_atc3_usb_die1;</div><div class='add'>+</div><div class='add'>+/delete-node/ &amp;ps_disp0_cpu0_die1;</div><div class='add'>+/delete-node/ &amp;ps_disp0_fe_die1;</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t6002.dtsi b/arch/arm64/boot/dts/apple/t6002.dtsi<br/>new file mode 100644<br/>index 000000000000..8fb648836b53<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t6002.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t6002.dtsi</a></div><div class='hunk'>@@ -0,0 +1,306 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple T6002 "M1 Ultra" SoC</div><div class='add'>+ *</div><div class='add'>+ * Other names: H13J, "Jade 2C"</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/apple-aic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/apple.h&gt;</div><div class='add'>+#include &lt;dt-bindings/spmi/spmi.h&gt;</div><div class='add'>+</div><div class='add'>+#include "multi-die-cpp.h"</div><div class='add'>+</div><div class='add'>+#include "t600x-common.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,t6002", "apple,arm-platform";</div><div class='add'>+</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		cpu-map {</div><div class='add'>+			cluster3 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu_e10&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu_e11&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cluster4 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu_p20&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu_p21&gt;;</div><div class='add'>+				};</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu_p22&gt;;</div><div class='add'>+				};</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu_p23&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cluster5 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu_p30&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu_p31&gt;;</div><div class='add'>+				};</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu_p32&gt;;</div><div class='add'>+				};</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu_p33&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_e10: cpu@800 {</div><div class='add'>+			compatible = "apple,icestorm";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x800&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_3&gt;;</div><div class='add'>+			i-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;icestorm_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;714&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_e_die1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_e11: cpu@801 {</div><div class='add'>+			compatible = "apple,icestorm";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x801&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_3&gt;;</div><div class='add'>+			i-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;icestorm_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;714&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_e_die1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_p20: cpu@10900 {</div><div class='add'>+			compatible = "apple,firestorm";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x10900&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_4&gt;;</div><div class='add'>+			i-cache-size = &lt;0x30000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;firestorm_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_p0_die1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_p21: cpu@10901 {</div><div class='add'>+			compatible = "apple,firestorm";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x10901&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_4&gt;;</div><div class='add'>+			i-cache-size = &lt;0x30000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;firestorm_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_p0_die1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_p22: cpu@10902 {</div><div class='add'>+			compatible = "apple,firestorm";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x10902&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_4&gt;;</div><div class='add'>+			i-cache-size = &lt;0x30000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;firestorm_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_p0_die1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_p23: cpu@10903 {</div><div class='add'>+			compatible = "apple,firestorm";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x10903&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_4&gt;;</div><div class='add'>+			i-cache-size = &lt;0x30000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;firestorm_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_p0_die1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_p30: cpu@10a00 {</div><div class='add'>+			compatible = "apple,firestorm";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x10a00&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_5&gt;;</div><div class='add'>+			i-cache-size = &lt;0x30000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;firestorm_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_p1_die1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_p31: cpu@10a01 {</div><div class='add'>+			compatible = "apple,firestorm";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x10a01&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_5&gt;;</div><div class='add'>+			i-cache-size = &lt;0x30000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;firestorm_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_p1_die1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_p32: cpu@10a02 {</div><div class='add'>+			compatible = "apple,firestorm";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x10a02&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_5&gt;;</div><div class='add'>+			i-cache-size = &lt;0x30000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;firestorm_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_p1_die1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_p33: cpu@10a03 {</div><div class='add'>+			compatible = "apple,firestorm";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x10a03&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_5&gt;;</div><div class='add'>+			i-cache-size = &lt;0x30000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;firestorm_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_p1_die1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_cache_3: l2-cache-3 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x400000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_cache_4: l2-cache-4 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0xc00000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_cache_5: l2-cache-5 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0xc00000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	die0: soc@200000000 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges = &lt;0x2 0x0 0x2 0x0 0x4 0x0&gt;,</div><div class='add'>+			 &lt;0x5 0x80000000 0x5 0x80000000 0x1 0x80000000&gt;,</div><div class='add'>+			 &lt;0x7 0x0 0x7 0x0 0xf 0x80000000&gt;;</div><div class='add'>+		nonposted-mmio;</div><div class='add'>+</div><div class='add'>+		// filled via templated includes at the end of the file</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	die1: soc@2200000000 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges = &lt;0x2 0x0 0x22 0x0 0x4 0x0&gt;,</div><div class='add'>+			 &lt;0x7 0x0 0x27 0x0 0xf 0x80000000&gt;;</div><div class='add'>+		nonposted-mmio;</div><div class='add'>+</div><div class='add'>+		// filled via templated includes at the end of the file</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define DIE</div><div class='add'>+#define DIE_NO 0</div><div class='add'>+</div><div class='add'>+&amp;die0 {</div><div class='add'>+	#include "t600x-die0.dtsi"</div><div class='add'>+	#include "t600x-dieX.dtsi"</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include "t600x-pmgr.dtsi"</div><div class='add'>+#include "t600x-gpio-pins.dtsi"</div><div class='add'>+</div><div class='add'>+#undef DIE</div><div class='add'>+#undef DIE_NO</div><div class='add'>+</div><div class='add'>+#define DIE _die1</div><div class='add'>+#define DIE_NO 1</div><div class='add'>+</div><div class='add'>+&amp;die1 {</div><div class='add'>+	#include "t600x-dieX.dtsi"</div><div class='add'>+	#include "t600x-nvme.dtsi"</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include "t600x-pmgr.dtsi"</div><div class='add'>+</div><div class='add'>+#undef DIE</div><div class='add'>+#undef DIE_NO</div><div class='add'>+</div><div class='add'>+&amp;aic {</div><div class='add'>+	affinities {</div><div class='add'>+		e-core-pmu-affinity {</div><div class='add'>+			apple,fiq-index = &lt;AIC_CPU_PMU_E&gt;;</div><div class='add'>+			cpus = &lt;&amp;cpu_e00 &amp;cpu_e01</div><div class='add'>+				&amp;cpu_e10 &amp;cpu_e11&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		p-core-pmu-affinity {</div><div class='add'>+			apple,fiq-index = &lt;AIC_CPU_PMU_P&gt;;</div><div class='add'>+			cpus = &lt;&amp;cpu_p00 &amp;cpu_p01 &amp;cpu_p02 &amp;cpu_p03</div><div class='add'>+				&amp;cpu_p10 &amp;cpu_p11 &amp;cpu_p12 &amp;cpu_p13</div><div class='add'>+				&amp;cpu_p20 &amp;cpu_p21 &amp;cpu_p22 &amp;cpu_p23</div><div class='add'>+				&amp;cpu_p30 &amp;cpu_p31 &amp;cpu_p32 &amp;cpu_p33&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ps_gfx {</div><div class='add'>+	// On t6002, the die0 GPU power domain needs both AFR power domains</div><div class='add'>+	power-domains = &lt;&amp;ps_afr&gt;, &lt;&amp;ps_afr_die1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	compatible = "apple,agx-g13d", "apple,agx-g13s";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t600x-common.dtsi b/arch/arm64/boot/dts/apple/t600x-common.dtsi<br/>new file mode 100644<br/>index 000000000000..e20234ef2135<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t600x-common.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t600x-common.dtsi</a></div><div class='hunk'>@@ -0,0 +1,415 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Common Apple T6000 / T6001 / T6002 "M1 Pro/Max/Ultra" SoC</div><div class='add'>+ *</div><div class='add'>+ * Other names: H13J, "Jade Chop", "Jade", "Jade 2C"</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		gpu = &amp;gpu;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu-map {</div><div class='add'>+			cluster0 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu_e00&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu_e01&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cluster1 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu_p00&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu_p01&gt;;</div><div class='add'>+				};</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu_p02&gt;;</div><div class='add'>+				};</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu_p03&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cluster2 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu_p10&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu_p11&gt;;</div><div class='add'>+				};</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu_p12&gt;;</div><div class='add'>+				};</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu_p13&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_e00: cpu@0 {</div><div class='add'>+			compatible = "apple,icestorm";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x0&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_0&gt;;</div><div class='add'>+			i-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;icestorm_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;714&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_e&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_e01: cpu@1 {</div><div class='add'>+			compatible = "apple,icestorm";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x1&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_0&gt;;</div><div class='add'>+			i-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;icestorm_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;714&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_e&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_p00: cpu@10100 {</div><div class='add'>+			compatible = "apple,firestorm";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x10100&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_1&gt;;</div><div class='add'>+			i-cache-size = &lt;0x30000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;firestorm_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_p0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_p01: cpu@10101 {</div><div class='add'>+			compatible = "apple,firestorm";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x10101&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_1&gt;;</div><div class='add'>+			i-cache-size = &lt;0x30000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;firestorm_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_p0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_p02: cpu@10102 {</div><div class='add'>+			compatible = "apple,firestorm";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x10102&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_1&gt;;</div><div class='add'>+			i-cache-size = &lt;0x30000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;firestorm_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_p0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_p03: cpu@10103 {</div><div class='add'>+			compatible = "apple,firestorm";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x10103&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_1&gt;;</div><div class='add'>+			i-cache-size = &lt;0x30000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;firestorm_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_p0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_p10: cpu@10200 {</div><div class='add'>+			compatible = "apple,firestorm";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x10200&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_2&gt;;</div><div class='add'>+			i-cache-size = &lt;0x30000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;firestorm_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_p1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_p11: cpu@10201 {</div><div class='add'>+			compatible = "apple,firestorm";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x10201&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_2&gt;;</div><div class='add'>+			i-cache-size = &lt;0x30000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;firestorm_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_p1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_p12: cpu@10202 {</div><div class='add'>+			compatible = "apple,firestorm";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x10202&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_2&gt;;</div><div class='add'>+			i-cache-size = &lt;0x30000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;firestorm_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_p1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_p13: cpu@10203 {</div><div class='add'>+			compatible = "apple,firestorm";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x10203&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_2&gt;;</div><div class='add'>+			i-cache-size = &lt;0x30000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;firestorm_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_p1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_cache_0: l2-cache-0 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x400000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_cache_1: l2-cache-1 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0xc00000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_cache_2: l2-cache-2 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0xc00000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	icestorm_opp: opp-table-0 {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		opp01 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;600000000&gt;;</div><div class='add'>+			opp-level = &lt;1&gt;;</div><div class='add'>+			clock-latency-ns = &lt;7500&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp02 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;972000000&gt;;</div><div class='add'>+			opp-level = &lt;2&gt;;</div><div class='add'>+			clock-latency-ns = &lt;23000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp03 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1332000000&gt;;</div><div class='add'>+			opp-level = &lt;3&gt;;</div><div class='add'>+			clock-latency-ns = &lt;29000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp04 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1704000000&gt;;</div><div class='add'>+			opp-level = &lt;4&gt;;</div><div class='add'>+			clock-latency-ns = &lt;40000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp05 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2064000000&gt;;</div><div class='add'>+			opp-level = &lt;5&gt;;</div><div class='add'>+			clock-latency-ns = &lt;50000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	firestorm_opp: opp-table-1 {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		opp01 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;600000000&gt;;</div><div class='add'>+			opp-level = &lt;1&gt;;</div><div class='add'>+			clock-latency-ns = &lt;8000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp02 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;828000000&gt;;</div><div class='add'>+			opp-level = &lt;2&gt;;</div><div class='add'>+			clock-latency-ns = &lt;18000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp03 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1056000000&gt;;</div><div class='add'>+			opp-level = &lt;3&gt;;</div><div class='add'>+			clock-latency-ns = &lt;19000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp04 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1296000000&gt;;</div><div class='add'>+			opp-level = &lt;4&gt;;</div><div class='add'>+			clock-latency-ns = &lt;23000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp05 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1524000000&gt;;</div><div class='add'>+			opp-level = &lt;5&gt;;</div><div class='add'>+			clock-latency-ns = &lt;24000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp06 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1752000000&gt;;</div><div class='add'>+			opp-level = &lt;6&gt;;</div><div class='add'>+			clock-latency-ns = &lt;28000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp07 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1980000000&gt;;</div><div class='add'>+			opp-level = &lt;7&gt;;</div><div class='add'>+			clock-latency-ns = &lt;31000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp08 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2208000000&gt;;</div><div class='add'>+			opp-level = &lt;8&gt;;</div><div class='add'>+			clock-latency-ns = &lt;45000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp09 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2448000000&gt;;</div><div class='add'>+			opp-level = &lt;9&gt;;</div><div class='add'>+			clock-latency-ns = &lt;49000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp10 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2676000000&gt;;</div><div class='add'>+			opp-level = &lt;10&gt;;</div><div class='add'>+			clock-latency-ns = &lt;53000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp11 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2904000000&gt;;</div><div class='add'>+			opp-level = &lt;11&gt;;</div><div class='add'>+			clock-latency-ns = &lt;56000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp12 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;3036000000&gt;;</div><div class='add'>+			opp-level = &lt;12&gt;;</div><div class='add'>+			clock-latency-ns = &lt;56000&gt;;</div><div class='add'>+		};</div><div class='add'>+		/* Not available until CPU deep sleep is implemented</div><div class='add'>+		opp13 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;3132000000&gt;;</div><div class='add'>+			opp-level = &lt;13&gt;;</div><div class='add'>+			clock-latency-ns = &lt;56000&gt;;</div><div class='add'>+			turbo-mode;</div><div class='add'>+		};</div><div class='add'>+		opp14 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;3168000000&gt;;</div><div class='add'>+			opp-level = &lt;14&gt;;</div><div class='add'>+			clock-latency-ns = &lt;56000&gt;;</div><div class='add'>+			turbo-mode;</div><div class='add'>+		};</div><div class='add'>+		opp15 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;3228000000&gt;;</div><div class='add'>+			opp-level = &lt;15&gt;;</div><div class='add'>+			clock-latency-ns = &lt;56000&gt;;</div><div class='add'>+			turbo-mode;</div><div class='add'>+		};</div><div class='add'>+		*/</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu-e {</div><div class='add'>+		compatible = "apple,icestorm-pmu";</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_FIQ 0 AIC_CPU_PMU_E IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu-p {</div><div class='add'>+		compatible = "apple,firestorm-pmu";</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_FIQ 0 AIC_CPU_PMU_P IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt";</div><div class='add'>+		interrupts = &lt;AIC_FIQ 0 AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;AIC_FIQ 0 AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;AIC_FIQ 0 AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;AIC_FIQ 0 AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clkref: clock-ref {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+		clock-output-names = "clkref";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_200m: clock-200m {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;200000000&gt;;</div><div class='add'>+		clock-output-names = "clk_200m";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * This is a fabulated representation of the input clock</div><div class='add'>+	 * to NCO since we don't know the true clock tree.</div><div class='add'>+	 */</div><div class='add'>+	nco_clkref: clock-ref-nco {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-output-names = "nco_ref";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		gpu_globals: globals {</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu_hw_cal_a: hw-cal-a {</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu_hw_cal_b: hw-cal-b {</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uat_handoff: uat-handoff {</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uat_pagetables: uat-pagetables {</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uat_ttbs: uat-ttbs {</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t600x-die0.dtsi b/arch/arm64/boot/dts/apple/t600x-die0.dtsi<br/>new file mode 100644<br/>index 000000000000..3603b276a2ab<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t600x-die0.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t600x-die0.dtsi</a></div><div class='hunk'>@@ -0,0 +1,522 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Devices used on die 0 on the Apple T6002 "M1 Ultra" SoC and present on</div><div class='add'>+ * Apple T6000 / T6001 "M1 Pro" / "M1 Max".</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	nco: clock-controller@28e03c000 {</div><div class='add'>+		compatible = "apple,t6000-nco", "apple,nco";</div><div class='add'>+		reg = &lt;0x2 0x8e03c000 0x0 0x14000&gt;;</div><div class='add'>+		clocks = &lt;&amp;nco_clkref&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aic: interrupt-controller@28e100000 {</div><div class='add'>+		compatible = "apple,t6000-aic", "apple,aic2";</div><div class='add'>+		#interrupt-cells = &lt;4&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		reg = &lt;0x2 0x8e100000 0x0 0xc000&gt;,</div><div class='add'>+			&lt;0x2 0x8e10c000 0x0 0x4&gt;;</div><div class='add'>+		reg-names = "core", "event";</div><div class='add'>+		power-domains = &lt;&amp;ps_aic&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	smc: smc@290400000 {</div><div class='add'>+		compatible = "apple,t6000-smc", "apple,smc";</div><div class='add'>+		reg = &lt;0x2 0x90400000 0x0 0x4000&gt;,</div><div class='add'>+			&lt;0x2 0x91e00000 0x0 0x100000&gt;;</div><div class='add'>+		reg-names = "smc", "sram";</div><div class='add'>+		mboxes = &lt;&amp;smc_mbox&gt;;</div><div class='add'>+</div><div class='add'>+		smc_gpio: gpio {</div><div class='add'>+			compatible = "apple,smc-gpio";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smc_reboot: reboot {</div><div class='add'>+			compatible = "apple,smc-reboot";</div><div class='add'>+			nvmem-cells = &lt;&amp;shutdown_flag&gt;, &lt;&amp;boot_stage&gt;,</div><div class='add'>+				&lt;&amp;boot_error_count&gt;, &lt;&amp;panic_count&gt;;</div><div class='add'>+			nvmem-cell-names = "shutdown_flag", "boot_stage",</div><div class='add'>+				"boot_error_count", "panic_count";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	smc_mbox: mbox@290408000 {</div><div class='add'>+		compatible = "apple,t6000-asc-mailbox", "apple,asc-mailbox-v4";</div><div class='add'>+		reg = &lt;0x2 0x90408000 0x0 0x4000&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ 0 754 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			&lt;AIC_IRQ 0 755 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			&lt;AIC_IRQ 0 756 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			&lt;AIC_IRQ 0 757 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-names = "send-empty", "send-not-empty",</div><div class='add'>+			"recv-empty", "recv-not-empty";</div><div class='add'>+		#mbox-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_smc: pinctrl@290820000 {</div><div class='add'>+		compatible = "apple,t6000-pinctrl", "apple,pinctrl";</div><div class='add'>+		reg = &lt;0x2 0x90820000 0x0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-ranges = &lt;&amp;pinctrl_smc 0 0 30&gt;;</div><div class='add'>+		apple,npins = &lt;30&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ 0 743 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ 0 744 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ 0 745 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ 0 746 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ 0 747 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ 0 748 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ 0 749 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	nub_spmi0: spmi@2920a1300 {</div><div class='add'>+		compatible = "apple,t6000-spmi", "apple,spmi";</div><div class='add'>+		reg = &lt;0x2 0x920a1300 0x0 0x100&gt;;</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		pmic1: pmic@f {</div><div class='add'>+			compatible = "apple,maverick-pmic", "apple,spmi-nvmem";</div><div class='add'>+			reg = &lt;0xf SPMI_USID&gt;;</div><div class='add'>+</div><div class='add'>+			nvmem-layout {</div><div class='add'>+				compatible = "fixed-layout";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				pm_setting: pm-setting@1405 {</div><div class='add'>+					reg = &lt;0x1405 0x1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				rtc_offset: rtc-offset@1411 {</div><div class='add'>+					reg = &lt;0x1411 0x6&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				boot_stage: boot-stage@6001 {</div><div class='add'>+					reg = &lt;0x6001 0x1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				boot_error_count: boot-error-count@6002,0 {</div><div class='add'>+					reg = &lt;0x6002 0x1&gt;;</div><div class='add'>+					bits = &lt;0 4&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				panic_count: panic-count@6002,4 {</div><div class='add'>+					reg = &lt;0x6002 0x1&gt;;</div><div class='add'>+					bits = &lt;4 4&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				boot_error_stage: boot-error-stage@6003 {</div><div class='add'>+					reg = &lt;0x6003 0x1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				shutdown_flag: shutdown-flag@600f,3 {</div><div class='add'>+					reg = &lt;0x600f 0x1&gt;;</div><div class='add'>+					bits = &lt;3 1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				fault_shadow: fault-shadow@867b {</div><div class='add'>+					reg = &lt;0x867b 0x10&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				socd: socd@8b00 {</div><div class='add'>+					reg = &lt;0x8b00 0x400&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wdt: watchdog@2922b0000 {</div><div class='add'>+		compatible = "apple,t6000-wdt", "apple,wdt";</div><div class='add'>+		reg = &lt;0x2 0x922b0000 0x0 0x4000&gt;;</div><div class='add'>+		clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ 0 631 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sio_dart_0: iommu@39b004000 {</div><div class='add'>+		compatible = "apple,t6000-dart";</div><div class='add'>+		reg = &lt;0x3 0x9b004000 0x0 0x4000&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ 0 1130 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		#iommu-cells = &lt;1&gt;;</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_cpu&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sio_dart_1: iommu@39b008000 {</div><div class='add'>+		compatible = "apple,t6000-dart";</div><div class='add'>+		reg = &lt;0x3 0x9b008000 0x0 0x8000&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ 0 1130 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		#iommu-cells = &lt;1&gt;;</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_cpu&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fpwm0: pwm@39b030000 {</div><div class='add'>+		compatible = "apple,t6000-fpwm", "apple,s5l-fpwm";</div><div class='add'>+		reg = &lt;0x3 0x9b030000 0x0 0x4000&gt;;</div><div class='add'>+		power-domains = &lt;&amp;ps_fpwm0&gt;;</div><div class='add'>+		clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+		#pwm-cells = &lt;2&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c0: i2c@39b040000 {</div><div class='add'>+		compatible = "apple,t6000-i2c", "apple,i2c";</div><div class='add'>+		reg = &lt;0x3 0x9b040000 0x0 0x4000&gt;;</div><div class='add'>+		clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ 0 1119 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;i2c0_pins&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		power-domains = &lt;&amp;ps_i2c0&gt;;</div><div class='add'>+		#address-cells = &lt;0x1&gt;;</div><div class='add'>+		#size-cells = &lt;0x0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c1: i2c@39b044000 {</div><div class='add'>+		compatible = "apple,t6000-i2c", "apple,i2c";</div><div class='add'>+		reg = &lt;0x3 0x9b044000 0x0 0x4000&gt;;</div><div class='add'>+		clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ 0 1120 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;i2c1_pins&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		power-domains = &lt;&amp;ps_i2c1&gt;;</div><div class='add'>+		#address-cells = &lt;0x1&gt;;</div><div class='add'>+		#size-cells = &lt;0x0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c2: i2c@39b048000 {</div><div class='add'>+		compatible = "apple,t6000-i2c", "apple,i2c";</div><div class='add'>+		reg = &lt;0x3 0x9b048000 0x0 0x4000&gt;;</div><div class='add'>+		clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ 0 1121 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;i2c2_pins&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		power-domains = &lt;&amp;ps_i2c2&gt;;</div><div class='add'>+		#address-cells = &lt;0x1&gt;;</div><div class='add'>+		#size-cells = &lt;0x0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c3: i2c@39b04c000 {</div><div class='add'>+		compatible = "apple,t6000-i2c", "apple,i2c";</div><div class='add'>+		reg = &lt;0x3 0x9b04c000 0x0 0x4000&gt;;</div><div class='add'>+		clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ 0 1122 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;i2c3_pins&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		power-domains = &lt;&amp;ps_i2c3&gt;;</div><div class='add'>+		#address-cells = &lt;0x1&gt;;</div><div class='add'>+		#size-cells = &lt;0x0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c4: i2c@39b050000 {</div><div class='add'>+		compatible = "apple,t6000-i2c", "apple,i2c";</div><div class='add'>+		reg = &lt;0x3 0x9b050000 0x0 0x4000&gt;;</div><div class='add'>+		clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ 0 1123 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;i2c4_pins&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		power-domains = &lt;&amp;ps_i2c4&gt;;</div><div class='add'>+		#address-cells = &lt;0x1&gt;;</div><div class='add'>+		#size-cells = &lt;0x0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c5: i2c@39b054000 {</div><div class='add'>+		compatible = "apple,t6000-i2c", "apple,i2c";</div><div class='add'>+		reg = &lt;0x3 0x9b054000 0x0 0x4000&gt;;</div><div class='add'>+		clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ 0 1124 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;i2c5_pins&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		power-domains = &lt;&amp;ps_i2c5&gt;;</div><div class='add'>+		#address-cells = &lt;0x1&gt;;</div><div class='add'>+		#size-cells = &lt;0x0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi1: spi@39b104000 {</div><div class='add'>+		compatible = "apple,t6000-spi", "apple,spi";</div><div class='add'>+		reg = &lt;0x3 0x9b104000 0x0 0x4000&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ 0 1107 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk_200m&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;spi1_pins&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		power-domains = &lt;&amp;ps_spi1&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi3: spi@39b10c000 {</div><div class='add'>+		compatible = "apple,t6000-spi", "apple,spi";</div><div class='add'>+		reg = &lt;0x3 0x9b10c000 0x0 0x4000&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ 0 1109 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;spi3_pins&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		power-domains = &lt;&amp;ps_spi3&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	serial0: serial@39b200000 {</div><div class='add'>+		compatible = "apple,s5l-uart";</div><div class='add'>+		reg = &lt;0x3 0x9b200000 0x0 0x1000&gt;;</div><div class='add'>+		reg-io-width = &lt;4&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ 0 1097 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		/*</div><div class='add'>+		 * TODO: figure out the clocking properly, there may</div><div class='add'>+		 * be a third selectable clock.</div><div class='add'>+		 */</div><div class='add'>+		clocks = &lt;&amp;clkref&gt;, &lt;&amp;clkref&gt;;</div><div class='add'>+		clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+		power-domains = &lt;&amp;ps_uart0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	admac: dma-controller@39b400000 {</div><div class='add'>+		compatible = "apple,t6000-admac", "apple,admac";</div><div class='add'>+		reg = &lt;0x3 0x9b400000 0x0 0x34000&gt;;</div><div class='add'>+		#dma-cells = &lt;1&gt;;</div><div class='add'>+		dma-channels = &lt;16&gt;;</div><div class='add'>+		interrupts-extended = &lt;0&gt;,</div><div class='add'>+				      &lt;&amp;aic AIC_IRQ 0 1118 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				      &lt;0&gt;,</div><div class='add'>+				      &lt;0&gt;;</div><div class='add'>+		iommus = &lt;&amp;sio_dart_0 2&gt;, &lt;&amp;sio_dart_1 2&gt;;</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_adma&gt;;</div><div class='add'>+		resets = &lt;&amp;ps_audio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mca: mca@39b600000 {</div><div class='add'>+		compatible = "apple,t6000-mca", "apple,mca";</div><div class='add'>+		reg = &lt;0x3 0x9b600000 0x0 0x10000&gt;,</div><div class='add'>+		      &lt;0x3 0x9b500000 0x0 0x20000&gt;;</div><div class='add'>+		clocks = &lt;&amp;nco 0&gt;, &lt;&amp;nco 1&gt;, &lt;&amp;nco 2&gt;, &lt;&amp;nco 3&gt;;</div><div class='add'>+		dmas = &lt;&amp;admac 0&gt;, &lt;&amp;admac 1&gt;, &lt;&amp;admac 2&gt;, &lt;&amp;admac 3&gt;,</div><div class='add'>+		       &lt;&amp;admac 4&gt;, &lt;&amp;admac 5&gt;, &lt;&amp;admac 6&gt;, &lt;&amp;admac 7&gt;,</div><div class='add'>+		       &lt;&amp;admac 8&gt;, &lt;&amp;admac 9&gt;, &lt;&amp;admac 10&gt;, &lt;&amp;admac 11&gt;,</div><div class='add'>+		       &lt;&amp;admac 12&gt;, &lt;&amp;admac 13&gt;, &lt;&amp;admac 14&gt;, &lt;&amp;admac 15&gt;;</div><div class='add'>+		dma-names = "tx0a", "rx0a", "tx0b", "rx0b",</div><div class='add'>+			    "tx1a", "rx1a", "tx1b", "rx1b",</div><div class='add'>+			    "tx2a", "rx2a", "tx2b", "rx2b",</div><div class='add'>+			    "tx3a", "rx3a", "tx3b", "rx3b";</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ 0 1112 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;AIC_IRQ 0 1113 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;AIC_IRQ 0 1114 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;AIC_IRQ 0 1115 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		power-domains = &lt;&amp;ps_audio_p&gt;, &lt;&amp;ps_mca0&gt;, &lt;&amp;ps_mca1&gt;,</div><div class='add'>+				&lt;&amp;ps_mca2&gt;, &lt;&amp;ps_mca3&gt;;</div><div class='add'>+		resets = &lt;&amp;ps_audio_p&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpu: gpu@406400000 {</div><div class='add'>+		compatible = "apple,agx-g13s";</div><div class='add'>+		reg = &lt;0x4 0x6400000 0 0x40000&gt;,</div><div class='add'>+			&lt;0x4 0x4000000 0 0x1000000&gt;;</div><div class='add'>+		reg-names = "asc", "sgx";</div><div class='add'>+		mboxes = &lt;&amp;agx_mbox&gt;;</div><div class='add'>+		power-domains = &lt;&amp;ps_gfx&gt;;</div><div class='add'>+		memory-region = &lt;&amp;uat_ttbs&gt;, &lt;&amp;uat_pagetables&gt;, &lt;&amp;uat_handoff&gt;,</div><div class='add'>+				&lt;&amp;gpu_hw_cal_a&gt;, &lt;&amp;gpu_hw_cal_b&gt;, &lt;&amp;gpu_globals&gt;;</div><div class='add'>+		memory-region-names = "ttbs", "pagetables", "handoff",</div><div class='add'>+				      "hw-cal-a", "hw-cal-b", "globals";</div><div class='add'>+</div><div class='add'>+		apple,firmware-abi = &lt;0 0 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	agx_mbox: mbox@406408000 {</div><div class='add'>+		compatible = "apple,t6000-asc-mailbox", "apple,asc-mailbox-v4";</div><div class='add'>+		reg = &lt;0x4 0x6408000 0x0 0x4000&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ 0 1059 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			&lt;AIC_IRQ 0 1060 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			&lt;AIC_IRQ 0 1061 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			&lt;AIC_IRQ 0 1062 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-names = "send-empty", "send-not-empty",</div><div class='add'>+			"recv-empty", "recv-not-empty";</div><div class='add'>+		#mbox-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_dart_0: iommu@581008000 {</div><div class='add'>+		compatible = "apple,t6000-dart";</div><div class='add'>+		reg = &lt;0x5 0x81008000 0x0 0x4000&gt;;</div><div class='add'>+		#iommu-cells = &lt;1&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ 0 1271 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		power-domains = &lt;&amp;ps_apcie_gp_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_dart_1: iommu@582008000 {</div><div class='add'>+		compatible = "apple,t6000-dart";</div><div class='add'>+		reg = &lt;0x5 0x82008000 0x0 0x4000&gt;;</div><div class='add'>+		#iommu-cells = &lt;1&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ 0 1274 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		power-domains = &lt;&amp;ps_apcie_gp_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_dart_2: iommu@583008000 {</div><div class='add'>+		compatible = "apple,t6000-dart";</div><div class='add'>+		reg = &lt;0x5 0x83008000 0x0 0x4000&gt;;</div><div class='add'>+		#iommu-cells = &lt;1&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ 0 1277 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		power-domains = &lt;&amp;ps_apcie_gp_sys&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_dart_3: iommu@584008000 {</div><div class='add'>+		compatible = "apple,t6000-dart";</div><div class='add'>+		reg = &lt;0x5 0x84008000 0x0 0x4000&gt;;</div><div class='add'>+		#iommu-cells = &lt;1&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ 0 1280 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		power-domains = &lt;&amp;ps_apcie_gp_sys&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0: pcie@590000000 {</div><div class='add'>+		compatible = "apple,t6000-pcie", "apple,pcie";</div><div class='add'>+		device_type = "pci";</div><div class='add'>+</div><div class='add'>+		reg = &lt;0x5 0x90000000 0x0 0x1000000&gt;,</div><div class='add'>+			&lt;0x5 0x80000000 0x0 0x100000&gt;,</div><div class='add'>+			&lt;0x5 0x81000000 0x0 0x4000&gt;,</div><div class='add'>+			&lt;0x5 0x82000000 0x0 0x4000&gt;,</div><div class='add'>+			&lt;0x5 0x83000000 0x0 0x4000&gt;,</div><div class='add'>+			&lt;0x5 0x84000000 0x0 0x4000&gt;;</div><div class='add'>+		reg-names = "config", "rc", "port0", "port1", "port2", "port3";</div><div class='add'>+</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ 0 1270 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ 0 1273 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ 0 1276 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ 0 1279 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+		msi-controller;</div><div class='add'>+		msi-parent = &lt;&amp;pcie0&gt;;</div><div class='add'>+		msi-ranges = &lt;&amp;aic AIC_IRQ 0 1581 IRQ_TYPE_EDGE_RISING 32&gt;;</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+		iommu-map = &lt;0x100 &amp;pcie0_dart_0 1 1&gt;,</div><div class='add'>+				&lt;0x200 &amp;pcie0_dart_1 1 1&gt;,</div><div class='add'>+				&lt;0x300 &amp;pcie0_dart_2 1 1&gt;,</div><div class='add'>+				&lt;0x400 &amp;pcie0_dart_3 1 1&gt;;</div><div class='add'>+		iommu-map-mask = &lt;0xff00&gt;;</div><div class='add'>+</div><div class='add'>+		bus-range = &lt;0 4&gt;;</div><div class='add'>+		#address-cells = &lt;3&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges = &lt;0x43000000 0x5 0xa0000000 0x5 0xa0000000 0x0 0x20000000&gt;,</div><div class='add'>+				&lt;0x02000000 0x0 0xc0000000 0x5 0xc0000000 0x0 0x40000000&gt;;</div><div class='add'>+</div><div class='add'>+		power-domains = &lt;&amp;ps_apcie_gp_sys&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pcie_pins&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		port00: pci@0,0 {</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			reg = &lt;0x0 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;pinctrl_ap 4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;port00 0 0 0 0&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;port00 0 0 0 1&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;port00 0 0 0 2&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;port00 0 0 0 3&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port01: pci@1,0 {</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			reg = &lt;0x800 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;pinctrl_ap 5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;port01 0 0 0 0&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;port01 0 0 0 1&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;port01 0 0 0 2&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;port01 0 0 0 3&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port02: pci@2,0 {</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			reg = &lt;0x1000 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;pinctrl_ap 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;port02 0 0 0 0&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;port02 0 0 0 1&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;port02 0 0 0 2&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;port02 0 0 0 3&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port03: pci@3,0 {</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			reg = &lt;0x1800 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;pinctrl_ap 7 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;port03 0 0 0 0&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;port03 0 0 0 1&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;port03 0 0 0 2&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;port03 0 0 0 3&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t600x-dieX.dtsi b/arch/arm64/boot/dts/apple/t600x-dieX.dtsi<br/>new file mode 100644<br/>index 000000000000..a32ff0c9d7b0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t600x-dieX.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t600x-dieX.dtsi</a></div><div class='hunk'>@@ -0,0 +1,121 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Devices used on both dies on the Apple T6002 "M1 Ultra" and present on</div><div class='add'>+ * Apple T6000/T6001 "M1 Pro/Max".</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+	DIE_NODE(cpufreq_e): cpufreq@210e20000 {</div><div class='add'>+		compatible = "apple,t6000-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";</div><div class='add'>+		reg = &lt;0x2 0x10e20000 0 0x1000&gt;;</div><div class='add'>+		#performance-domain-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(cpufreq_p0): cpufreq@211e20000 {</div><div class='add'>+		compatible = "apple,t6000-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";</div><div class='add'>+		reg = &lt;0x2 0x11e20000 0 0x1000&gt;;</div><div class='add'>+		#performance-domain-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(cpufreq_p1): cpufreq@212e20000 {</div><div class='add'>+		compatible = "apple,t6000-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";</div><div class='add'>+		reg = &lt;0x2 0x12e20000 0 0x1000&gt;;</div><div class='add'>+		#performance-domain-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(pmgr): power-management@28e080000 {</div><div class='add'>+		compatible = "apple,t6000-pmgr", "apple,pmgr", "syscon", "simple-mfd";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		reg = &lt;0x2 0x8e080000 0 0x4000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(pmgr_east): power-management@28e580000 {</div><div class='add'>+		compatible = "apple,t6000-pmgr", "apple,pmgr", "syscon", "simple-mfd";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		reg = &lt;0x2 0x8e580000 0 0xc000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(pmgr_south): power-management@28e680000 {</div><div class='add'>+		compatible = "apple,t6000-pmgr", "apple,pmgr", "syscon", "simple-mfd";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		reg = &lt;0x2 0x8e680000 0 0xc000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(pinctrl_nub): pinctrl@2921f0000 {</div><div class='add'>+		compatible = "apple,t6000-pinctrl", "apple,pinctrl";</div><div class='add'>+		reg = &lt;0x2 0x921f0000 0x0 0x4000&gt;;</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_nub_gpio)&gt;;</div><div class='add'>+</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-ranges = &lt;&amp;DIE_NODE(pinctrl_nub) 0 0 16&gt;;</div><div class='add'>+		apple,npins = &lt;16&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ DIE_NO 623 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ DIE_NO 624 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ DIE_NO 625 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ DIE_NO 626 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ DIE_NO 627 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ DIE_NO 628 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ DIE_NO 629 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(pmgr_mini): power-management@292280000 {</div><div class='add'>+		compatible = "apple,t6000-pmgr", "apple,pmgr", "syscon", "simple-mfd";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		reg = &lt;0x2 0x92280000 0 0x4000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(pinctrl_aop): pinctrl@293820000 {</div><div class='add'>+		compatible = "apple,t6000-pinctrl", "apple,pinctrl";</div><div class='add'>+		reg = &lt;0x2 0x93820000 0x0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-ranges = &lt;&amp;DIE_NODE(pinctrl_aop) 0 0 63&gt;;</div><div class='add'>+		apple,npins = &lt;63&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ DIE_NO 567 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ DIE_NO 568 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ DIE_NO 569 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ DIE_NO 570 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ DIE_NO 571 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ DIE_NO 572 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ DIE_NO 573 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(pinctrl_ap): pinctrl@39b028000 {</div><div class='add'>+		compatible = "apple,t6000-pinctrl", "apple,pinctrl";</div><div class='add'>+		reg = &lt;0x3 0x9b028000 0x0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ DIE_NO 427 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ DIE_NO 428 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ DIE_NO 429 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ DIE_NO 430 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ DIE_NO 431 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ DIE_NO 432 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ DIE_NO 433 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_gpio)&gt;;</div><div class='add'>+</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-ranges = &lt;&amp;DIE_NODE(pinctrl_ap) 0 0 255&gt;;</div><div class='add'>+		apple,npins = &lt;255&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t600x-gpio-pins.dtsi b/arch/arm64/boot/dts/apple/t600x-gpio-pins.dtsi<br/>new file mode 100644<br/>index 000000000000..1a994c3c1b79<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t600x-gpio-pins.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t600x-gpio-pins.dtsi</a></div><div class='hunk'>@@ -0,0 +1,59 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * GPIO pin mappings for Apple T600x SoCs.</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_ap {</div><div class='add'>+	i2c0_pins: i2c0-pins {</div><div class='add'>+		pinmux = &lt;APPLE_PINMUX(92, 1)&gt;,</div><div class='add'>+			&lt;APPLE_PINMUX(93, 1)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c1_pins: i2c1-pins {</div><div class='add'>+		pinmux = &lt;APPLE_PINMUX(94, 1)&gt;,</div><div class='add'>+			&lt;APPLE_PINMUX(95, 1)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c2_pins: i2c2-pins {</div><div class='add'>+		pinmux = &lt;APPLE_PINMUX(96, 1)&gt;,</div><div class='add'>+			&lt;APPLE_PINMUX(97, 1)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c3_pins: i2c3-pins {</div><div class='add'>+		pinmux = &lt;APPLE_PINMUX(98, 1)&gt;,</div><div class='add'>+			&lt;APPLE_PINMUX(99, 1)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c4_pins: i2c4-pins {</div><div class='add'>+		pinmux = &lt;APPLE_PINMUX(8, 1)&gt;,</div><div class='add'>+			&lt;APPLE_PINMUX(9, 1)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c5_pins: i2c5-pins {</div><div class='add'>+		pinmux = &lt;APPLE_PINMUX(100, 1)&gt;,</div><div class='add'>+			&lt;APPLE_PINMUX(101, 1)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi1_pins: spi1-pins {</div><div class='add'>+		pinmux = &lt;APPLE_PINMUX(10, 1)&gt;,</div><div class='add'>+			&lt;APPLE_PINMUX(11, 1)&gt;,</div><div class='add'>+			&lt;APPLE_PINMUX(32, 1)&gt;,</div><div class='add'>+			&lt;APPLE_PINMUX(33, 1)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi3_pins: spi3-pins {</div><div class='add'>+		pinmux = &lt;APPLE_PINMUX(52, 1)&gt;,</div><div class='add'>+			&lt;APPLE_PINMUX(53, 1)&gt;,</div><div class='add'>+			&lt;APPLE_PINMUX(54, 1)&gt;,</div><div class='add'>+			&lt;APPLE_PINMUX(55, 1)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie_pins: pcie-pins {</div><div class='add'>+		pinmux = &lt;APPLE_PINMUX(0, 1)&gt;,</div><div class='add'>+				&lt;APPLE_PINMUX(1, 1)&gt;,</div><div class='add'>+				&lt;APPLE_PINMUX(2, 1)&gt;,</div><div class='add'>+				&lt;APPLE_PINMUX(3, 1)&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi b/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi<br/>new file mode 100644<br/>index 000000000000..c0aac59a6fae<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi</a></div><div class='hunk'>@@ -0,0 +1,133 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * MacBook Pro (14/16-inch, 2021)</div><div class='add'>+ *</div><div class='add'>+ * This file contains the parts common to J314 and J316 devices with both t6000 and t6001.</div><div class='add'>+ *</div><div class='add'>+ * target-type: J314s / J314c / J316s / J316c</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		bluetooth0 = &amp;bluetooth0;</div><div class='add'>+		serial0 = &amp;serial0;</div><div class='add'>+		wifi0 = &amp;wifi0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		stdout-path = "serial0";</div><div class='add'>+</div><div class='add'>+		framebuffer0: framebuffer@0 {</div><div class='add'>+			compatible = "apple,simple-framebuffer", "simple-framebuffer";</div><div class='add'>+			reg = &lt;0 0 0 0&gt;; /* To be filled by loader */</div><div class='add'>+			/* Format properties will be added by loader */</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@10000000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x100 0 0x2 0&gt;; /* To be filled by loader */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	led-controller {</div><div class='add'>+		compatible = "pwm-leds";</div><div class='add'>+		led-0 {</div><div class='add'>+			pwms = &lt;&amp;fpwm0 0 40000&gt;;</div><div class='add'>+			label = "kbd_backlight";</div><div class='add'>+			function = LED_FUNCTION_KBD_BACKLIGHT;</div><div class='add'>+			color = &lt;LED_COLOR_ID_WHITE&gt;;</div><div class='add'>+			max-brightness = &lt;255&gt;;</div><div class='add'>+			default-state = "keep";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;serial0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB Type C */</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	hpm0: usb-pd@38 {</div><div class='add'>+		compatible = "apple,cd321x";</div><div class='add'>+		reg = &lt;0x38&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;pinctrl_ap&gt;;</div><div class='add'>+		interrupts = &lt;174 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupt-names = "irq";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hpm1: usb-pd@3f {</div><div class='add'>+		compatible = "apple,cd321x";</div><div class='add'>+		reg = &lt;0x3f&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;pinctrl_ap&gt;;</div><div class='add'>+		interrupts = &lt;174 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupt-names = "irq";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hpm2: usb-pd@3b {</div><div class='add'>+		compatible = "apple,cd321x";</div><div class='add'>+		reg = &lt;0x3b&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;pinctrl_ap&gt;;</div><div class='add'>+		interrupts = &lt;174 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupt-names = "irq";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* MagSafe port */</div><div class='add'>+	hpm5: usb-pd@3a {</div><div class='add'>+		compatible = "apple,cd321x";</div><div class='add'>+		reg = &lt;0x3a&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;pinctrl_ap&gt;;</div><div class='add'>+		interrupts = &lt;174 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupt-names = "irq";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;nco_clkref {</div><div class='add'>+	clock-frequency = &lt;1068000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* PCIe devices */</div><div class='add'>+&amp;port00 {</div><div class='add'>+	/* WLAN */</div><div class='add'>+	bus-range = &lt;1 1&gt;;</div><div class='add'>+	wifi0: wifi@0,0 {</div><div class='add'>+		compatible = "pci14e4,4433";</div><div class='add'>+		reg = &lt;0x10000 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+		/* To be filled by the loader */</div><div class='add'>+		local-mac-address = [00 10 18 00 00 10];</div><div class='add'>+		apple,antenna-sku = "XX";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bluetooth0: bluetooth@0,1 {</div><div class='add'>+		compatible = "pci14e4,5f71";</div><div class='add'>+		reg = &lt;0x10100 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+		/* To be filled by the loader */</div><div class='add'>+		local-bd-address = [00 00 00 00 00 00];</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;port01 {</div><div class='add'>+	/* SD card reader */</div><div class='add'>+	bus-range = &lt;2 2&gt;;</div><div class='add'>+	sdhci0: mmc@0,0 {</div><div class='add'>+		compatible = "pci17a0,9755";</div><div class='add'>+		reg = &lt;0x20000 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+		cd-inverted;</div><div class='add'>+		wp-inverted;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fpwm0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include "spi1-nvram.dtsi"</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t600x-j375.dtsi b/arch/arm64/boot/dts/apple/t600x-j375.dtsi<br/>new file mode 100644<br/>index 000000000000..c0fb93ae72f4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t600x-j375.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t600x-j375.dtsi</a></div><div class='hunk'>@@ -0,0 +1,141 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Mac Studio (2022)</div><div class='add'>+ *</div><div class='add'>+ * This file contains the parts common to J375 devices with both t6001 and t6002.</div><div class='add'>+ *</div><div class='add'>+ * target-type: J375c / J375d</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		bluetooth0 = &amp;bluetooth0;</div><div class='add'>+		ethernet0 = &amp;ethernet0;</div><div class='add'>+		serial0 = &amp;serial0;</div><div class='add'>+		wifi0 = &amp;wifi0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		stdout-path = "serial0";</div><div class='add'>+</div><div class='add'>+		framebuffer0: framebuffer@0 {</div><div class='add'>+			compatible = "apple,simple-framebuffer", "simple-framebuffer";</div><div class='add'>+			reg = &lt;0 0 0 0&gt;; /* To be filled by loader */</div><div class='add'>+			/* Format properties will be added by loader */</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@10000000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x100 0 0x2 0&gt;; /* To be filled by loader */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;serial0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB Type C */</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	hpm0: usb-pd@38 {</div><div class='add'>+		compatible = "apple,cd321x";</div><div class='add'>+		reg = &lt;0x38&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;pinctrl_ap&gt;;</div><div class='add'>+		interrupts = &lt;174 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupt-names = "irq";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hpm1: usb-pd@3f {</div><div class='add'>+		compatible = "apple,cd321x";</div><div class='add'>+		reg = &lt;0x3f&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;pinctrl_ap&gt;;</div><div class='add'>+		interrupts = &lt;174 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupt-names = "irq";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hpm2: usb-pd@3b {</div><div class='add'>+		compatible = "apple,cd321x";</div><div class='add'>+		reg = &lt;0x3b&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;pinctrl_ap&gt;;</div><div class='add'>+		interrupts = &lt;174 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupt-names = "irq";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hpm3: usb-pd@3c {</div><div class='add'>+		compatible = "apple,cd321x";</div><div class='add'>+		reg = &lt;0x3c&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;pinctrl_ap&gt;;</div><div class='add'>+		interrupts = &lt;174 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupt-names = "irq";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;nco_clkref {</div><div class='add'>+	clock-frequency = &lt;1068000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* PCIe devices */</div><div class='add'>+&amp;port00 {</div><div class='add'>+	/* WLAN */</div><div class='add'>+	bus-range = &lt;1 1&gt;;</div><div class='add'>+	wifi0: wifi@0,0 {</div><div class='add'>+		compatible = "pci14e4,4433";</div><div class='add'>+		reg = &lt;0x10000 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+		/* To be filled by the loader */</div><div class='add'>+		local-mac-address = [00 10 18 00 00 10];</div><div class='add'>+		apple,antenna-sku = "XX";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bluetooth0: bluetooth@0,1 {</div><div class='add'>+		compatible = "pci14e4,5f71";</div><div class='add'>+		reg = &lt;0x10100 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+		/* To be filled by the loader */</div><div class='add'>+		local-bd-address = [00 00 00 00 00 00];</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;port01 {</div><div class='add'>+	/* SD card reader */</div><div class='add'>+	bus-range = &lt;2 2&gt;;</div><div class='add'>+	sdhci0: mmc@0,0 {</div><div class='add'>+		compatible = "pci17a0,9755";</div><div class='add'>+		reg = &lt;0x20000 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+		cd-inverted;</div><div class='add'>+		wp-inverted;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;port02 {</div><div class='add'>+	/* 10 Gbit Ethernet */</div><div class='add'>+	bus-range = &lt;3 3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+	ethernet0: ethernet@0,0 {</div><div class='add'>+		reg = &lt;0x30000 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+		/* To be filled by the loader */</div><div class='add'>+		local-mac-address = [00 10 18 00 00 00];</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;port03 {</div><div class='add'>+	/* USB xHCI */</div><div class='add'>+	bus-range = &lt;4 4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+&amp;pcie0_dart_2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0_dart_3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include "spi1-nvram.dtsi"</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t600x-nvme.dtsi b/arch/arm64/boot/dts/apple/t600x-nvme.dtsi<br/>new file mode 100644<br/>index 000000000000..7dff738d317e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t600x-nvme.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t600x-nvme.dtsi</a></div><div class='hunk'>@@ -0,0 +1,42 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * NVMe related devices for Apple T600x SoCs.</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ans_mbox): mbox@38f408000 {</div><div class='add'>+		compatible = "apple,t6000-asc-mailbox", "apple,asc-mailbox-v4";</div><div class='add'>+		reg = &lt;0x3 0x8f408000 0x0 0x4000&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ DIE_NO 1069 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			&lt;AIC_IRQ DIE_NO 1070 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			&lt;AIC_IRQ DIE_NO 1071 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			&lt;AIC_IRQ DIE_NO 1072 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-names = "send-empty", "send-not-empty",</div><div class='add'>+			"recv-empty", "recv-not-empty";</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_ans2)&gt;;</div><div class='add'>+		#mbox-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(sart): sart@393c50000 {</div><div class='add'>+		compatible = "apple,t6000-sart";</div><div class='add'>+		reg = &lt;0x3 0x93c50000 0x0 0x10000&gt;;</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_ans2)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(nvme): nvme@393cc0000 {</div><div class='add'>+		compatible = "apple,t6000-nvme-ans2", "apple,nvme-ans2";</div><div class='add'>+		reg = &lt;0x3 0x93cc0000 0x0 0x40000&gt;, &lt;0x3 0x8f400000 0x0 0x4000&gt;;</div><div class='add'>+		reg-names = "nvme", "ans";</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		/* The NVME interrupt is always routed to die */</div><div class='add'>+		interrupts = &lt;AIC_IRQ 0 1613 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		mboxes = &lt;&amp;DIE_NODE(ans_mbox)&gt;;</div><div class='add'>+		apple,sart = &lt;&amp;DIE_NODE(sart)&gt;;</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_ans2)&gt;,</div><div class='add'>+			&lt;&amp;DIE_NODE(ps_apcie_st_sys)&gt;,</div><div class='add'>+			&lt;&amp;DIE_NODE(ps_apcie_st1_sys)&gt;;</div><div class='add'>+		power-domain-names = "ans", "apcie0", "apcie1";</div><div class='add'>+		resets = &lt;&amp;DIE_NODE(ps_ans2)&gt;;</div><div class='add'>+	};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t600x-pmgr.dtsi b/arch/arm64/boot/dts/apple/t600x-pmgr.dtsi<br/>new file mode 100644<br/>index 000000000000..0bd44753b76a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t600x-pmgr.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t600x-pmgr.dtsi</a></div><div class='hunk'>@@ -0,0 +1,2012 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * PMGR Power domains for the Apple T6001 "M1 Max" SoC</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;DIE_NODE(pmgr) {</div><div class='add'>+	DIE_NODE(ps_pms_bridge): power-controller@100 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x100 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(pms_bridge);</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_aic): power-controller@108 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x108 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(aic);</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dwi): power-controller@110 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x110 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dwi);</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_pms): power-controller@118 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x118 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(pms);</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_gpio): power-controller@120 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x120 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(gpio);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_pms)&gt;, &lt;&amp;DIE_NODE(ps_sio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_soc_dpe): power-controller@128 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x128 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(soc_dpe);</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_pmgr_soc_ocla): power-controller@130 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x130 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(pmgr_soc_ocla);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_pms)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_pcie0_ref): power-controller@138 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x138 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(pcie0_ref);</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_pcie1_ref): power-controller@140 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x140 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(pcie1_ref);</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_apcie_st): power-controller@148 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x148 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(apcie_st);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_pcie1_ref)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_apcie_gp): power-controller@150 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x150 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(apcie_gp);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_pcie0_ref)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_devc0_ivdmc): power-controller@180 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x180 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(devc0_ivdmc);</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_amcc0): power-controller@188 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x188 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(amcc0);</div><div class='add'>+		apple,always-on; /* Memory controller */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_amcc2): power-controller@190 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x190 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(amcc2);</div><div class='add'>+		apple,always-on; /* Memory controller */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_00): power-controller@198 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x198 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_00);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_01): power-controller@1a0 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1a0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_01);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_02): power-controller@1a8 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1a8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_02);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_03): power-controller@1b0 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1b0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_03);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_08): power-controller@1b8 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1b8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_08);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_09): power-controller@1c0 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1c0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_09);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_10): power-controller@1c8 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1c8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_10);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_11): power-controller@1d0 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1d0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_11);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afi): power-controller@1d8 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1d8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afi);</div><div class='add'>+		apple,always-on; /* Apple Fabric, CPU interface is here */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afc): power-controller@1e0 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1e0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afc);</div><div class='add'>+		apple,always-on; /* Apple Fabric, CPU interface is here */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afr): power-controller@1e8 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1e8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afr);</div><div class='add'>+		/* Apple Fabric, media stuff: this can power down */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afnc1_ioa): power-controller@1f0 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1f0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afnc1_ioa);</div><div class='add'>+		apple,always-on; /* Apple Fabric */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afi)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afnc0_ioa): power-controller@1f8 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1f8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afnc0_ioa);</div><div class='add'>+		apple,always-on; /* Apple Fabric */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afi)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afnc1_ls): power-controller@200 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x200 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afnc1_ls);</div><div class='add'>+		apple,always-on; /* Apple Fabric */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc1_ioa)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afnc0_ls): power-controller@208 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x208 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afnc0_ls);</div><div class='add'>+		apple,always-on; /* Apple Fabric */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc0_ioa)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afnc1_lw0): power-controller@210 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x210 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afnc1_lw0);</div><div class='add'>+		apple,always-on; /* Apple Fabric */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc1_ls)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afnc1_lw1): power-controller@218 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x218 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afnc1_lw1);</div><div class='add'>+		apple,always-on; /* Apple Fabric */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc1_ls)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afnc1_lw2): power-controller@220 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x220 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afnc1_lw2);</div><div class='add'>+		apple,always-on; /* Apple Fabric */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc1_ls)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afnc0_lw0): power-controller@228 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x228 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afnc0_lw0);</div><div class='add'>+		apple,always-on; /* Apple Fabric */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc0_ls)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_scodec): power-controller@230 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x230 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(scodec);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc1_lw0)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc0_common): power-controller@238 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x238 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc0_common);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc1_lw1)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc1_common): power-controller@240 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x240 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc1_common);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc1_lw1)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_c0_usb31drd): power-controller@248 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x248 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(c0_usb31drd);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_usb)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_c1_usb31drd): power-controller@250 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x250 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(c1_usb31drd);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_usb)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dispext0_fe): power-controller@258 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x258 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dispext0_fe);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afi)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dispext1_fe): power-controller@260 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x260 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dispext1_fe);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afi)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_ane_sys): power-controller@268 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x268 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(ane_sys);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afr)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_avd_sys): power-controller@270 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x270 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(avd_sys);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afr)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dispext0_cpu0): power-controller@280 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x280 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dispext0_cpu0);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_dispext0_fe)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dispext1_cpu0): power-controller@2a8 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2a8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dispext1_cpu0);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_dispext1_fe)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_ane_sys_cpu): power-controller@2c8 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2c8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(ane_sys_cpu);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_ane_sys)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+#if DIE_NO == 0</div><div class='add'>+	/* PMP is only present on die 0 of the M1 Ultra */</div><div class='add'>+	DIE_NODE(ps_pmp): power-controller@2d8 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2d8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(pmp);</div><div class='add'>+	};</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_pms_sram): power-controller@2e0 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2e0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(pms_sram);</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_apcie_st_sys): power-controller@2e8 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2e8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(apcie_st_sys);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_apcie_st)&gt;, &lt;&amp;DIE_NODE(ps_ans2)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_apcie_st1_sys): power-controller@2f0 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2f0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(apcie_st1_sys);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_apcie_st)&gt;, &lt;&amp;DIE_NODE(ps_ans2)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc2_common): power-controller@2f8 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2f8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc2_common);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc1_lw1)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc3_common): power-controller@300 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x300 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc3_common);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc1_lw1)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_usb): power-controller@318 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x318 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(usb);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc1_lw2)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_apcie_gp_sys): power-controller@320 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x320 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(apcie_gp_sys);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc1_lw2)&gt;, &lt;&amp;DIE_NODE(ps_apcie_gp)&gt;;</div><div class='add'>+		apple,always-on; /* Breaks things if shut down */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc0_cio): power-controller@328 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x328 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc0_cio);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_atc0_common)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc0_pcie): power-controller@330 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x330 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc0_pcie);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_atc0_common)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc1_cio): power-controller@338 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x338 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc1_cio);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_atc1_common)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc1_pcie): power-controller@340 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x340 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc1_pcie);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_atc1_common)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc2_cio): power-controller@348 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x348 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc2_cio);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_atc2_common)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc2_pcie): power-controller@350 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x350 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc2_pcie);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_atc2_common)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc3_cio): power-controller@358 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x358 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc3_cio);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_atc3_common)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc3_pcie): power-controller@360 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x360 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc3_pcie);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_atc3_common)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_c0_usbctl): power-controller@368 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x368 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(c0_usbctl);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_usb)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_c1_usbctl): power-controller@370 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x370 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(c1_usbctl);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_usb)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc0_cio_pcie): power-controller@378 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x378 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc0_cio_pcie);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_atc0_cio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc0_cio_usb): power-controller@380 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x380 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc0_cio_usb);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_atc0_cio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc1_cio_pcie): power-controller@388 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x388 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc1_cio_pcie);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_atc1_cio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc1_cio_usb): power-controller@390 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x390 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc1_cio_usb);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_atc1_cio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc2_cio_pcie): power-controller@398 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x398 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc2_cio_pcie);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_atc2_cio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc2_cio_usb): power-controller@3a0 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x3a0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc2_cio_usb);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_atc2_cio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc3_cio_pcie): power-controller@3a8 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x3a8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc3_cio_pcie);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_atc3_cio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc3_cio_usb): power-controller@3b0 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x3b0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc3_cio_usb);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_atc3_cio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_trace_fab): power-controller@3b8 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x3b8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(trace_fab);</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;DIE_NODE(pmgr_east) {</div><div class='add'>+	DIE_NODE(ps_clvr_spmi0): power-controller@100 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x100 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(clvr_spmi0);</div><div class='add'>+		apple,always-on; /* PCPU voltage regulator interface (used by SMC) */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_clvr_spmi1): power-controller@108 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x108 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(clvr_spmi1);</div><div class='add'>+		apple,always-on; /* GPU voltage regulator interface (used by SMC) */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_clvr_spmi2): power-controller@110 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x110 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(clvr_spmi2);</div><div class='add'>+		apple,always-on; /* ANE, fabric, AFR voltage regulator interface (used by SMC) */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_clvr_spmi3): power-controller@118 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x118 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(clvr_spmi3);</div><div class='add'>+		apple,always-on; /* Additional voltage regulator, probably used on T6001 (SMC) */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_clvr_spmi4): power-controller@120 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x120 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(clvr_spmi4);</div><div class='add'>+		apple,always-on; /* Additional voltage regulator, probably used on T6001 (SMC) */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_ispsens0): power-controller@128 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x128 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(ispsens0);</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_ispsens1): power-controller@130 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x130 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(ispsens1);</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_ispsens2): power-controller@138 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x138 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(ispsens2);</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_ispsens3): power-controller@140 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x140 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(ispsens3);</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afnc2_ioa): power-controller@148 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x148 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afnc2_ioa);</div><div class='add'>+		apple,always-on; /* Apple Fabric */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afi)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afnc2_ls): power-controller@150 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x150 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afnc2_ls);</div><div class='add'>+		apple,always-on; /* Apple Fabric */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc2_ioa)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afnc2_lw0): power-controller@158 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x158 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afnc2_lw0);</div><div class='add'>+		apple,always-on; /* Apple Fabric */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc2_ls)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afnc2_lw1): power-controller@160 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x160 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afnc2_lw1);</div><div class='add'>+		apple,always-on; /* Apple Fabric */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc2_ls)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afnc3_ioa): power-controller@168 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x168 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afnc3_ioa);</div><div class='add'>+		apple,always-on; /* Apple Fabric */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afi)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afnc3_ls): power-controller@170 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x170 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afnc3_ls);</div><div class='add'>+		apple,always-on; /* Apple Fabric */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc3_ioa)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afnc3_lw0): power-controller@178 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x178 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afnc3_lw0);</div><div class='add'>+		apple,always-on; /* Apple Fabric */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc3_ls)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_sio): power-controller@180 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x180 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(sio);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc2_lw1)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_sio_cpu): power-controller@188 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x188 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(sio_cpu);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_sio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_fpwm0): power-controller@190 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x190 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(fpwm0);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_sio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_fpwm1): power-controller@198 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x198 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(fpwm1);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_sio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_fpwm2): power-controller@1a0 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1a0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(fpwm2);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_sio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_i2c0): power-controller@1a8 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1a8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(i2c0);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_sio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_i2c1): power-controller@1b0 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1b0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(i2c1);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_sio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_i2c2): power-controller@1b8 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1b8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(i2c2);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_sio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_i2c3): power-controller@1c0 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1c0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(i2c3);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_sio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_i2c4): power-controller@1c8 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1c8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(i2c4);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_sio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_i2c5): power-controller@1d0 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1d0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(i2c5);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_sio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_i2c6): power-controller@1d8 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1d8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(i2c6);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_sio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_i2c7): power-controller@1e0 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1e0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(i2c7);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_sio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_spi_p): power-controller@1e8 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1e8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(spi_p);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_sio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_spi0): power-controller@1f0 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1f0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(spi0);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_spi_p)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_spi1): power-controller@1f8 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1f8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(spi1);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_spi_p)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_spi2): power-controller@200 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x200 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(spi2);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_spi_p)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_spi3): power-controller@208 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x208 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(spi3);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_spi_p)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_spi4): power-controller@210 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x210 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(spi4);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_spi_p)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_sio_spmi0): power-controller@218 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x218 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(sio_spmi0);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_sio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_sio_spmi1): power-controller@220 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x220 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(sio_spmi1);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_sio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_sio_spmi2): power-controller@228 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x228 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(sio_spmi2);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_sio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_uart_p): power-controller@230 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x230 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(uart_p);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_sio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_uart_n): power-controller@238 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x238 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(uart_n);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_uart_p)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_uart0): power-controller@240 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x240 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(uart0);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_uart_p)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_uart1): power-controller@248 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x248 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(uart1);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_uart_p)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_uart2): power-controller@250 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x250 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(uart2);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_uart_p)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_uart3): power-controller@258 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x258 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(uart3);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_uart_p)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_uart4): power-controller@260 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x260 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(uart4);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_uart_p)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_uart6): power-controller@268 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x268 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(uart6);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_uart_p)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_uart7): power-controller@270 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x270 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(uart7);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_uart_p)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_audio_p): power-controller@278 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x278 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(audio_p);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_sio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_sio_adma): power-controller@280 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x280 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(sio_adma);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_audio_p)&gt;, &lt;&amp;DIE_NODE(ps_sio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_mca0): power-controller@288 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x288 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(mca0);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_audio_p)&gt;, &lt;&amp;DIE_NODE(ps_sio_adma)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_mca1): power-controller@290 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x290 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(mca1);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_audio_p)&gt;, &lt;&amp;DIE_NODE(ps_sio_adma)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_mca2): power-controller@298 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x298 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(mca2);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_audio_p)&gt;, &lt;&amp;DIE_NODE(ps_sio_adma)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_mca3): power-controller@2a0 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2a0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(mca3);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_audio_p)&gt;, &lt;&amp;DIE_NODE(ps_sio_adma)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dpa0): power-controller@2a8 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2a8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dpa0);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_audio_p)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dpa1): power-controller@2b0 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2b0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dpa1);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_audio_p)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dpa2): power-controller@2b8 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2b8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dpa2);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_audio_p)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dpa3): power-controller@2c0 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2c0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dpa3);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_audio_p)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dpa4): power-controller@2c8 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2c8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dpa4);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_audio_p)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_aes): power-controller@2d0 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2d0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(aes);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_sio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_amcc1): power-controller@2d8 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2d8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(amcc1);</div><div class='add'>+		apple,always-on; /* Memory controller */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_amcc3): power-controller@2e0 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2e0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(amcc3);</div><div class='add'>+		apple,always-on; /* Memory controller */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_04): power-controller@2e8 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2e8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_04);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_05): power-controller@2f0 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2f0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_05);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_06): power-controller@2f8 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2f8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_06);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_07): power-controller@300 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x300 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_07);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_12): power-controller@308 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x308 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_12);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_13): power-controller@310 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x310 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_13);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_14): power-controller@318 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x318 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_14);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_15): power-controller@320 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x320 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_15);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_disp0_fe): power-controller@328 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x328 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(disp0_fe);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc2_lw0)&gt;;</div><div class='add'>+		apple,always-on; /* TODO: figure out if we can enable PM here */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_disp0_cpu0): power-controller@350 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x350 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(disp0_cpu0);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_disp0_fe)&gt;;</div><div class='add'>+		apple,always-on; /* TODO: figure out if we can enable PM here */</div><div class='add'>+		apple,min-state = &lt;4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dispdfr_fe): power-controller@378 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x378 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dispdfr_fe);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc2_lw1)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dispdfr_be): power-controller@380 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x380 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dispdfr_be);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_dispdfr_fe)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_mipi_dsi): power-controller@388 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x388 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(mipi_dsi);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_dispdfr_be)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_jpg): power-controller@390 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x390 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(jpg);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afr)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_msr0): power-controller@398 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x398 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(msr0);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afr)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_msr0_ase_core): power-controller@3a0 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x3a0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(msr0_ase_core);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_msr0)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_isp_sys): power-controller@3a8 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x3a8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(isp_sys);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc2_lw1)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_venc_sys): power-controller@3b0 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x3b0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(venc_sys);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afr)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_ans2): power-controller@3b8 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x3b8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(ans2);</div><div class='add'>+		/*</div><div class='add'>+		 * The ADT makes ps_apcie_st[1]_sys depend on ps_ans2 instead,</div><div class='add'>+		 * but we'd rather have a single power domain for the downstream</div><div class='add'>+		 * device to depend on, so use this node as the child.</div><div class='add'>+		 * This makes more sense anyway (since ANS2 uses APCIE_ST).</div><div class='add'>+		 */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc2_lw0)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_gfx): power-controller@3c0 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x3c0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(gfx);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afr)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_sep): power-controller@c00 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0xc00 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(sep);</div><div class='add'>+		apple,always-on; /* Locked on */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_venc_dma): power-controller@8000 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x8000 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(venc_dma);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_venc_sys)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_venc_pipe4): power-controller@8008 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x8008 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(venc_pipe4);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_venc_dma)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_venc_pipe5): power-controller@8010 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x8010 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(venc_pipe5);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_venc_dma)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_venc_me0): power-controller@8018 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x8018 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(venc_me0);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_venc_pipe5)&gt;, &lt;&amp;DIE_NODE(ps_venc_pipe4)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_venc_me1): power-controller@8020 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x8020 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(venc_me1);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_venc_me0)&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;DIE_NODE(pmgr_south) {</div><div class='add'>+	DIE_NODE(ps_amcc4): power-controller@100 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x100 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(amcc4);</div><div class='add'>+		apple,always-on; /* Memory controller */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_amcc5): power-controller@108 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x108 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(amcc5);</div><div class='add'>+		apple,always-on; /* Memory controller */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_amcc6): power-controller@110 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x110 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(amcc6);</div><div class='add'>+		apple,always-on; /* Memory controller */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_amcc7): power-controller@118 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x118 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(amcc7);</div><div class='add'>+		apple,always-on; /* Memory controller */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_16): power-controller@120 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x120 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_16);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_17): power-controller@128 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x128 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_17);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_18): power-controller@130 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x130 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_18);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_19): power-controller@138 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x138 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_19);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_20): power-controller@140 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x140 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_20);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_21): power-controller@148 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x148 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_21);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_22): power-controller@150 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x150 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_22);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_23): power-controller@158 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x158 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_23);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_24): power-controller@160 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x160 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_24);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_25): power-controller@168 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x168 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_25);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_26): power-controller@170 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x170 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_26);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_27): power-controller@178 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x178 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_27);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_28): power-controller@180 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x180 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_28);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_29): power-controller@188 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x188 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_29);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_30): power-controller@190 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x190 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_30);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_31): power-controller@198 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x198 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_31);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afnc4_ioa): power-controller@1a0 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1a0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afnc4_ioa);</div><div class='add'>+		apple,always-on; /* Apple Fabric */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afi)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afnc4_ls): power-controller@1a8 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1a8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afnc4_ls);</div><div class='add'>+		apple,always-on; /* Apple Fabric */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc4_ioa)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afnc4_lw0): power-controller@1b0 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1b0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afnc4_lw0);</div><div class='add'>+		apple,always-on; /* Apple Fabric */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc4_ls)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afnc5_ioa): power-controller@1b8 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1b8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afnc5_ioa);</div><div class='add'>+		apple,always-on; /* Apple Fabric */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afi)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afnc5_ls): power-controller@1c0 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1c0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afnc5_ls);</div><div class='add'>+		apple,always-on; /* Apple Fabric */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc5_ioa)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afnc5_lw0): power-controller@1c8 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1c8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afnc5_lw0);</div><div class='add'>+		apple,always-on; /* Apple Fabric */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc5_ls)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dispext2_fe): power-controller@1d0 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1d0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dispext2_fe);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc4_lw0)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dispext2_cpu0): power-controller@1e8 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1e8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dispext2_cpu0);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_dispext2_fe)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dispext3_fe): power-controller@210 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x210 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dispext3_fe);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc4_lw0)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dispext3_cpu0): power-controller@228 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x228 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dispext3_cpu0);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_dispext3_fe)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_msr1): power-controller@250 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x250 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(msr1);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc5_lw0)&gt;, &lt;&amp;DIE_NODE(ps_afr)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_msr1_ase_core): power-controller@258 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x258 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(msr1_ase_core);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_msr1)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_venc1_sys): power-controller@260 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x260 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(venc1_sys);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc5_lw0)&gt;, &lt;&amp;DIE_NODE(ps_afr)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Seems to be disabled on shipping hardware */</div><div class='add'>+#if 0</div><div class='add'>+	DIE_NODE(ps_ane1_sys): power-controller@268 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x268 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(ane1_sys);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc5_lw0)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_ane1_sys_cpu): power-controller@270 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x270 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(ane1_sys_cpu);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_ane1_sys)&gt;;</div><div class='add'>+	};</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_venc1_dma): power-controller@8000 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x8000 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(venc1_dma);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_venc1_sys)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_venc1_pipe4): power-controller@8008 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x8008 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(venc1_pipe4);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_venc1_dma)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_venc1_pipe5): power-controller@8010 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x8010 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(venc1_pipe5);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_venc1_dma)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_venc1_me0): power-controller@8018 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x8018 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(venc1_me0);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_venc1_pipe4)&gt;, &lt;&amp;DIE_NODE(ps_venc1_pipe5)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_venc1_me1): power-controller@8020 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x8020 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(venc1_me1);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_venc1_me0)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_prores): power-controller@c000 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0xc000 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(prores);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc4_lw0)&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;DIE_NODE(pmgr_mini) {</div><div class='add'>+	DIE_NODE(ps_debug): power-controller@58 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x58 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(debug);</div><div class='add'>+		apple,always-on; /* Core AON device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_nub_spmi0): power-controller@60 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x60 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(nub_spmi0);</div><div class='add'>+		apple,always-on; /* Core AON device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_nub_spmi1): power-controller@68 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x68 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(nub_spmi1);</div><div class='add'>+		apple,always-on; /* Core AON device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_nub_aon): power-controller@70 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x70 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(nub_aon);</div><div class='add'>+		apple,always-on; /* Core AON device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_msg): power-controller@78 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x78 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(msg);</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_nub_gpio): power-controller@80 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(nub_gpio);</div><div class='add'>+		apple,always-on; /* Core AON device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc0_usb_aon): power-controller@88 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x88 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc0_usb_aon);</div><div class='add'>+		apple,always-on; /* Needs to stay on for dwc3 to work */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc1_usb_aon): power-controller@90 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x90 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc1_usb_aon);</div><div class='add'>+		apple,always-on; /* Needs to stay on for dwc3 to work */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc2_usb_aon): power-controller@98 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x98 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc2_usb_aon);</div><div class='add'>+		apple,always-on; /* Needs to stay on for dwc3 to work */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc3_usb_aon): power-controller@a0 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0xa0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc3_usb_aon);</div><div class='add'>+		apple,always-on; /* Needs to stay on for dwc3 to work */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_gp_usb_aon): power-controller@a8 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0xa8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(gp_usb_aon);</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_nub_fabric): power-controller@b0 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0xb0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(nub_fabric);</div><div class='add'>+		apple,always-on; /* Core AON device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_nub_sram): power-controller@b8 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0xb8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(nub_sram);</div><div class='add'>+		apple,always-on; /* Core AON device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_debug_usb): power-controller@c0 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0xc0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(debug_usb);</div><div class='add'>+		apple,always-on; /* Core AON device */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_debug)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_debug_auth): power-controller@c8 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0xc8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(debug_auth);</div><div class='add'>+		apple,always-on; /* Core AON device */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_debug)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc0_usb): power-controller@d0 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0xd0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc0_usb);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_atc0_usb_aon)&gt;, &lt;&amp;DIE_NODE(ps_atc0_common)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc1_usb): power-controller@d8 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0xd8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc1_usb);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_atc1_usb_aon)&gt;, &lt;&amp;DIE_NODE(ps_atc1_common)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc2_usb): power-controller@e0 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0xe0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc2_usb);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_atc2_usb_aon)&gt;, &lt;&amp;DIE_NODE(ps_atc2_common)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc3_usb): power-controller@e8 {</div><div class='add'>+		compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0xe8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc3_usb);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_atc3_usb_aon)&gt;, &lt;&amp;DIE_NODE(ps_atc3_common)&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t6020-j414s.dts b/arch/arm64/boot/dts/apple/t6020-j414s.dts<br/>new file mode 100644<br/>index 000000000000..631c54c5f03d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t6020-j414s.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t6020-j414s.dts</a></div><div class='hunk'>@@ -0,0 +1,26 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * MacBook Pro (14-inch, M2 Pro, 2023)</div><div class='add'>+ *</div><div class='add'>+ * target-type: J414s</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t6020.dtsi"</div><div class='add'>+#include "t602x-j414-j416.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j414s", "apple,t6020", "apple,arm-platform";</div><div class='add'>+	model = "Apple MacBook Pro (14-inch, M2 Pro, 2023)";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wifi0 {</div><div class='add'>+	brcm,board-type = "apple,tokara";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;bluetooth0 {</div><div class='add'>+	brcm,board-type = "apple,tokara";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t6020-j416s.dts b/arch/arm64/boot/dts/apple/t6020-j416s.dts<br/>new file mode 100644<br/>index 000000000000..c277ed5889a2<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t6020-j416s.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t6020-j416s.dts</a></div><div class='hunk'>@@ -0,0 +1,26 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * MacBook Pro (16-inch, M2 Pro, 2023)</div><div class='add'>+ *</div><div class='add'>+ * target-type: J416s</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t6020.dtsi"</div><div class='add'>+#include "t602x-j414-j416.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j416s", "apple,t6020", "apple,arm-platform";</div><div class='add'>+	model = "Apple MacBook Pro (16-inch, M2 Pro, 2023)";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wifi0 {</div><div class='add'>+	brcm,board-type = "apple,amami";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;bluetooth0 {</div><div class='add'>+	brcm,board-type = "apple,amami";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t6020-j474s.dts b/arch/arm64/boot/dts/apple/t6020-j474s.dts<br/>new file mode 100644<br/>index 000000000000..7c7ad5b8ad18<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t6020-j474s.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t6020-j474s.dts</a></div><div class='hunk'>@@ -0,0 +1,47 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Mac mini (M2 Pro, 2023)</div><div class='add'>+ *</div><div class='add'>+ * target-type: J474s</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t6020.dtsi"</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * This model is very similar to M1 and M2 Mac Studio models so base it on those</div><div class='add'>+ * and remove the missing SDHCI controller.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "t602x-j474-j475.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j474s", "apple,t6020", "apple,arm-platform";</div><div class='add'>+	model = "Apple Mac mini (M2 Pro, 2023)";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* PCIe devices */</div><div class='add'>+&amp;wifi0 {</div><div class='add'>+	compatible = "pci14e4,4434";</div><div class='add'>+	brcm,board-type = "apple,tasmania";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;bluetooth0 {</div><div class='add'>+	compatible = "pci14e4,5f72";</div><div class='add'>+	brcm,board-type = "apple,tasmania";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * port01 is unused, remove the PCIe sdhci0 node from t600x-j375.dtsi and adjust</div><div class='add'>+ * the iommu-map.</div><div class='add'>+ */</div><div class='add'>+/delete-node/ &amp;sdhci0;</div><div class='add'>+</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	iommu-map = &lt;0x100 &amp;pcie0_dart_0 1 1&gt;,</div><div class='add'>+			&lt;0x200 &amp;pcie0_dart_2 1 1&gt;,</div><div class='add'>+			&lt;0x300 &amp;pcie0_dart_3 1 1&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t6020.dtsi b/arch/arm64/boot/dts/apple/t6020.dtsi<br/>new file mode 100644<br/>index 000000000000..bffa66a3ffff<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t6020.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t6020.dtsi</a></div><div class='hunk'>@@ -0,0 +1,22 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple T6020 "M2 Pro" SoC</div><div class='add'>+ *</div><div class='add'>+ * Other names: H14J, "Rhodes Chop"</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/* This chip is just a cut down version of t6021, so include it and disable the missing parts */</div><div class='add'>+</div><div class='add'>+#include "t6021.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,t6020", "apple,arm-platform";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/delete-node/ &amp;pmgr_south;</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	compatible = "apple,agx-g14s";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t6021-j414c.dts b/arch/arm64/boot/dts/apple/t6021-j414c.dts<br/>new file mode 100644<br/>index 000000000000..cdcf0740714d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t6021-j414c.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t6021-j414c.dts</a></div><div class='hunk'>@@ -0,0 +1,26 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * MacBook Pro (14-inch, M2 Max, 2023)</div><div class='add'>+ *</div><div class='add'>+ * target-type: J414c</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t6021.dtsi"</div><div class='add'>+#include "t602x-j414-j416.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j414c", "apple,t6021", "apple,arm-platform";</div><div class='add'>+	model = "Apple MacBook Pro (14-inch, M2 Max, 2023)";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wifi0 {</div><div class='add'>+	brcm,board-type = "apple,tokara";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;bluetooth0 {</div><div class='add'>+	brcm,board-type = "apple,tokara";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t6021-j416c.dts b/arch/arm64/boot/dts/apple/t6021-j416c.dts<br/>new file mode 100644<br/>index 000000000000..6d8146b94170<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t6021-j416c.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t6021-j416c.dts</a></div><div class='hunk'>@@ -0,0 +1,26 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * MacBook Pro (16-inch, M2 Max, 2022)</div><div class='add'>+ *</div><div class='add'>+ * target-type: J416c</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t6021.dtsi"</div><div class='add'>+#include "t602x-j414-j416.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j416c", "apple,t6021", "apple,arm-platform";</div><div class='add'>+	model = "Apple MacBook Pro (16-inch, M2 Max, 2023)";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wifi0 {</div><div class='add'>+	brcm,board-type = "apple,amami";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;bluetooth0 {</div><div class='add'>+	brcm,board-type = "apple,amami";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t6021-j475c.dts b/arch/arm64/boot/dts/apple/t6021-j475c.dts<br/>new file mode 100644<br/>index 000000000000..533e35774874<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t6021-j475c.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t6021-j475c.dts</a></div><div class='hunk'>@@ -0,0 +1,37 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Mac Studio (M2 Max, 2023)</div><div class='add'>+ *</div><div class='add'>+ * target-type: J475c</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t6021.dtsi"</div><div class='add'>+#include "t602x-j474-j475.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j475c", "apple,t6021", "apple,arm-platform";</div><div class='add'>+	model = "Apple Mac Studio (M2 Max, 2023)";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wifi0 {</div><div class='add'>+	compatible = "pci14e4,4434";</div><div class='add'>+	brcm,board-type = "apple,canary";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;bluetooth0 {</div><div class='add'>+	compatible = "pci14e4,5f72";</div><div class='add'>+	brcm,board-type = "apple,canary";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* enable PCIe port01 with SDHCI */</div><div class='add'>+&amp;port01 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0_dart_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t6021.dtsi b/arch/arm64/boot/dts/apple/t6021.dtsi<br/>new file mode 100644<br/>index 000000000000..62907ad6a546<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t6021.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t6021.dtsi</a></div><div class='hunk'>@@ -0,0 +1,69 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple T6021 "M2 Max" SoC</div><div class='add'>+ *</div><div class='add'>+ * Other names: H14J, "Rhodes"</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/apple-aic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/apple.h&gt;</div><div class='add'>+#include &lt;dt-bindings/phy/phy.h&gt;</div><div class='add'>+#include &lt;dt-bindings/spmi/spmi.h&gt;</div><div class='add'>+</div><div class='add'>+#include "multi-die-cpp.h"</div><div class='add'>+</div><div class='add'>+#include "t602x-common.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,t6021", "apple,arm-platform";</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		ranges;</div><div class='add'>+		nonposted-mmio;</div><div class='add'>+</div><div class='add'>+		// filled via templated includes at the end of the file</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define DIE</div><div class='add'>+#define DIE_NO 0</div><div class='add'>+</div><div class='add'>+&amp;{/soc} {</div><div class='add'>+	#include "t602x-die0.dtsi"</div><div class='add'>+	#include "t602x-dieX.dtsi"</div><div class='add'>+	#include "t602x-nvme.dtsi"</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include "t602x-gpio-pins.dtsi"</div><div class='add'>+#include "t602x-pmgr.dtsi"</div><div class='add'>+</div><div class='add'>+#undef DIE</div><div class='add'>+#undef DIE_NO</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+&amp;aic {</div><div class='add'>+	affinities {</div><div class='add'>+		e-core-pmu-affinity {</div><div class='add'>+			apple,fiq-index = &lt;AIC_CPU_PMU_E&gt;;</div><div class='add'>+			cpus = &lt;&amp;cpu_e00 &amp;cpu_e01 &amp;cpu_e02 &amp;cpu_e03&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		p-core-pmu-affinity {</div><div class='add'>+			apple,fiq-index = &lt;AIC_CPU_PMU_P&gt;;</div><div class='add'>+			cpus = &lt;&amp;cpu_p00 &amp;cpu_p01 &amp;cpu_p02 &amp;cpu_p03</div><div class='add'>+				&amp;cpu_p10 &amp;cpu_p11 &amp;cpu_p12 &amp;cpu_p13&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	compatible = "apple,agx-g14c", "apple,agx-g14s";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t6022-j180d.dts b/arch/arm64/boot/dts/apple/t6022-j180d.dts<br/>new file mode 100644<br/>index 000000000000..dca6bd167c22<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t6022-j180d.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t6022-j180d.dts</a></div><div class='hunk'>@@ -0,0 +1,121 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Mac Pro (M2 Ultra, 2023)</div><div class='add'>+ *</div><div class='add'>+ * target-type: J180d</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t6022.dtsi"</div><div class='add'>+#include "t6022-jxxxd.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j180d", "apple,t6022", "apple,arm-platform";</div><div class='add'>+	model = "Apple Mac Pro (M2 Ultra, 2023)";</div><div class='add'>+	aliases {</div><div class='add'>+		nvram = &amp;nvram;</div><div class='add'>+		serial0 = &amp;serial0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		stdout-path = "serial0";</div><div class='add'>+</div><div class='add'>+		framebuffer0: framebuffer@0 {</div><div class='add'>+			compatible = "apple,simple-framebuffer", "simple-framebuffer";</div><div class='add'>+			reg = &lt;0 0 0 0&gt;; /* To be filled by loader */</div><div class='add'>+			/* Format properties will be added by loader */</div><div class='add'>+			status = "disabled";</div><div class='add'>+			power-domains = &lt;&amp;ps_dispext0_cpu0_die1&gt;, &lt;&amp;ps_dptx_phy_ps_die1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@10000000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x100 0 0x2 0&gt;; /* To be filled by loader */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;serial0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB Type C Rear */</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	hpm2: usb-pd@3b {</div><div class='add'>+		compatible = "apple,cd321x";</div><div class='add'>+		reg = &lt;0x3b&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;pinctrl_ap&gt;;</div><div class='add'>+		interrupts = &lt;44 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupt-names = "irq";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hpm3: usb-pd@3c {</div><div class='add'>+		compatible = "apple,cd321x";</div><div class='add'>+		reg = &lt;0x3c&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;pinctrl_ap&gt;;</div><div class='add'>+		interrupts = &lt;44 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupt-names = "irq";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* hpm4 and hpm5 included from t6022-jxxxd.dtsi */</div><div class='add'>+</div><div class='add'>+	hpm6: usb-pd@3d {</div><div class='add'>+		compatible = "apple,cd321x";</div><div class='add'>+		reg = &lt;0x3d&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;pinctrl_ap&gt;;</div><div class='add'>+		interrupts = &lt;44 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupt-names = "irq";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hpm7: usb-pd@3e {</div><div class='add'>+		compatible = "apple,cd321x";</div><div class='add'>+		reg = &lt;0x3e&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;pinctrl_ap&gt;;</div><div class='add'>+		interrupts = &lt;44 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupt-names = "irq";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB Type C Front */</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	hpm0: usb-pd@38 {</div><div class='add'>+		compatible = "apple,cd321x";</div><div class='add'>+		reg = &lt;0x38&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;pinctrl_ap&gt;;</div><div class='add'>+		interrupts = &lt;60 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupt-names = "irq";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hpm1: usb-pd@3f {</div><div class='add'>+		compatible = "apple,cd321x";</div><div class='add'>+		reg = &lt;0x3f&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;pinctrl_ap&gt;;</div><div class='add'>+		interrupts = &lt;60 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupt-names = "irq";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Delete unused PCIe nodes, the Mac Pro uses slightly different PCIe</div><div class='add'>+ * controllers with a single port connected to a PM40100 PCIe switch</div><div class='add'>+ */</div><div class='add'>+/delete-node/ &amp;pcie0;</div><div class='add'>+/delete-node/ &amp;pcie0_dart_0;</div><div class='add'>+/delete-node/ &amp;pcie0_dart_1;</div><div class='add'>+/delete-node/ &amp;pcie0_dart_2;</div><div class='add'>+/delete-node/ &amp;pcie0_dart_3;</div><div class='add'>+</div><div class='add'>+&amp;nco_clkref {</div><div class='add'>+	clock-frequency = &lt;1068000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include "spi1-nvram.dtsi"</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t6022-j475d.dts b/arch/arm64/boot/dts/apple/t6022-j475d.dts<br/>new file mode 100644<br/>index 000000000000..736594544f79<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t6022-j475d.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t6022-j475d.dts</a></div><div class='hunk'>@@ -0,0 +1,42 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Mac Studio (M2 Ultra, 2023)</div><div class='add'>+ *</div><div class='add'>+ * target-type: J475d</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t6022.dtsi"</div><div class='add'>+#include "t602x-j474-j475.dtsi"</div><div class='add'>+#include "t6022-jxxxd.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j475d", "apple,t6022", "apple,arm-platform";</div><div class='add'>+	model = "Apple Mac Studio (M2 Ultra, 2023)";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;framebuffer0 {</div><div class='add'>+	power-domains = &lt;&amp;ps_dispext0_cpu0_die1&gt;, &lt;&amp;ps_dptx_phy_ps_die1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* enable PCIe port01 with SDHCI */</div><div class='add'>+&amp;port01 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0_dart_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wifi0 {</div><div class='add'>+	compatible = "pci14e4,4434";</div><div class='add'>+	brcm,board-type = "apple,canary";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;bluetooth0 {</div><div class='add'>+	compatible = "pci14e4,5f72";</div><div class='add'>+	brcm,board-type = "apple,canary";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t6022-jxxxd.dtsi b/arch/arm64/boot/dts/apple/t6022-jxxxd.dtsi<br/>new file mode 100644<br/>index 000000000000..4f7bf2ebfe39<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t6022-jxxxd.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t6022-jxxxd.dtsi</a></div><div class='hunk'>@@ -0,0 +1,38 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Mac Pro (M2 Ultra, 2023) and Mac Studio (M2 Ultra, 2023)</div><div class='add'>+ *</div><div class='add'>+ * This file contains the parts common to J180 and J475 devices with t6022.</div><div class='add'>+ *</div><div class='add'>+ * target-type: J180d / J475d</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/* delete power-domains for missing disp0 / disp0_die1 */</div><div class='add'>+/delete-node/ &amp;ps_disp0_cpu0;</div><div class='add'>+/delete-node/ &amp;ps_disp0_fe;</div><div class='add'>+</div><div class='add'>+/delete-node/ &amp;ps_disp0_cpu0_die1;</div><div class='add'>+/delete-node/ &amp;ps_disp0_fe_die1;</div><div class='add'>+</div><div class='add'>+/* USB Type C */</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	/* front-right */</div><div class='add'>+	hpm4: usb-pd@39 {</div><div class='add'>+		compatible = "apple,cd321x";</div><div class='add'>+		reg = &lt;0x39&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;pinctrl_ap&gt;;</div><div class='add'>+		interrupts = &lt;44 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupt-names = "irq";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* front-left */</div><div class='add'>+	hpm5: usb-pd@3a {</div><div class='add'>+		compatible = "apple,cd321x";</div><div class='add'>+		reg = &lt;0x3a&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;pinctrl_ap&gt;;</div><div class='add'>+		interrupts = &lt;44 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupt-names = "irq";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t6022.dtsi b/arch/arm64/boot/dts/apple/t6022.dtsi<br/>new file mode 100644<br/>index 000000000000..e73bf2f7510a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t6022.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t6022.dtsi</a></div><div class='hunk'>@@ -0,0 +1,349 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple T6022 "M2 Ultra" SoC</div><div class='add'>+ *</div><div class='add'>+ * Other names: H14J, "Rhodes 2C"</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/apple-aic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/apple.h&gt;</div><div class='add'>+#include &lt;dt-bindings/phy/phy.h&gt;</div><div class='add'>+#include &lt;dt-bindings/spmi/spmi.h&gt;</div><div class='add'>+</div><div class='add'>+#include "multi-die-cpp.h"</div><div class='add'>+</div><div class='add'>+#include "t602x-common.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,t6022", "apple,arm-platform";</div><div class='add'>+</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		cpu-map {</div><div class='add'>+			cluster3 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu_e10&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu_e11&gt;;</div><div class='add'>+				};</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu_e12&gt;;</div><div class='add'>+				};</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu_e13&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cluster4 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu_p20&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu_p21&gt;;</div><div class='add'>+				};</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu_p22&gt;;</div><div class='add'>+				};</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu_p23&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cluster5 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu_p30&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu_p31&gt;;</div><div class='add'>+				};</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu_p32&gt;;</div><div class='add'>+				};</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu_p33&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_e10: cpu@800 {</div><div class='add'>+			compatible = "apple,blizzard";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x800&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* to be filled by loader */</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_3&gt;;</div><div class='add'>+			i-cache-size  = &lt;0x20000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;blizzard_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;756&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_e_die1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_e11: cpu@801 {</div><div class='add'>+			compatible = "apple,blizzard";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x801&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* to be filled by loader */</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_3&gt;;</div><div class='add'>+			i-cache-size  = &lt;0x20000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;blizzard_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;756&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_e_die1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_e12: cpu@802 {</div><div class='add'>+			compatible = "apple,blizzard";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x802&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* to be filled by loader */</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_3&gt;;</div><div class='add'>+			i-cache-size  = &lt;0x20000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;blizzard_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;756&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_e_die1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_e13: cpu@803 {</div><div class='add'>+			compatible = "apple,blizzard";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x803&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* to be filled by loader */</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_3&gt;;</div><div class='add'>+			i-cache-size  = &lt;0x20000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;blizzard_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;756&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_e_die1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_p20: cpu@10900 {</div><div class='add'>+			compatible = "apple,avalanche";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x10900&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_4&gt;;</div><div class='add'>+			i-cache-size = &lt;0x30000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;avalanche_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_p0_die1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_p21: cpu@10901 {</div><div class='add'>+			compatible = "apple,avalanche";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x10901&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_4&gt;;</div><div class='add'>+			i-cache-size = &lt;0x30000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;avalanche_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_p0_die1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_p22: cpu@10902 {</div><div class='add'>+			compatible = "apple,avalanche";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x10902&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_4&gt;;</div><div class='add'>+			i-cache-size = &lt;0x30000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;avalanche_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_p0_die1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_p23: cpu@10903 {</div><div class='add'>+			compatible = "apple,avalanche";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x10903&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_4&gt;;</div><div class='add'>+			i-cache-size = &lt;0x30000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;avalanche_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_p0_die1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_p30: cpu@10a00 {</div><div class='add'>+			compatible = "apple,avalanche";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x10a00&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_5&gt;;</div><div class='add'>+			i-cache-size = &lt;0x30000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;avalanche_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_p1_die1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_p31: cpu@10a01 {</div><div class='add'>+			compatible = "apple,avalanche";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x10a01&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_5&gt;;</div><div class='add'>+			i-cache-size = &lt;0x30000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;avalanche_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_p1_die1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_p32: cpu@10a02 {</div><div class='add'>+			compatible = "apple,avalanche";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x10a02&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_5&gt;;</div><div class='add'>+			i-cache-size = &lt;0x30000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;avalanche_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_p1_die1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_p33: cpu@10a03 {</div><div class='add'>+			compatible = "apple,avalanche";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x10a03&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_5&gt;;</div><div class='add'>+			i-cache-size = &lt;0x30000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;avalanche_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_p1_die1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_cache_3: l2-cache-3 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x400000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_cache_4: l2-cache-4 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x1000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_cache_5: l2-cache-5 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x1000000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	die0: soc@200000000 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges = &lt;0x02 0x00000000 0x02 0x00000000 0x4 0x00000000&gt;,</div><div class='add'>+			 &lt;0x05 0x80000000 0x05 0x80000000 0x1 0x80000000&gt;,</div><div class='add'>+			 &lt;0x07 0x00000000 0x07 0x00000000 0xf 0x80000000&gt;,</div><div class='add'>+			 &lt;0x16 0x80000000 0x16 0x80000000 0x5 0x80000000&gt;;</div><div class='add'>+		nonposted-mmio;</div><div class='add'>+		/* Required to get &gt;32-bit DMA via DARTs */</div><div class='add'>+		dma-ranges = &lt;0 0 0 0 0xffffffff 0xffffc000&gt;;</div><div class='add'>+</div><div class='add'>+		// filled via templated includes at the end of the file</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	die1: soc@2200000000 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges = &lt;0x02 0x00000000 0x22 0x00000000 0x4 0x00000000&gt;,</div><div class='add'>+			 &lt;0x07 0x00000000 0x27 0x00000000 0xf 0x80000000&gt;,</div><div class='add'>+			 &lt;0x16 0x80000000 0x36 0x80000000 0x5 0x80000000&gt;;</div><div class='add'>+		nonposted-mmio;</div><div class='add'>+		/* Required to get &gt;32-bit DMA via DARTs */</div><div class='add'>+		dma-ranges = &lt;0 0 0 0 0xffffffff 0xffffc000&gt;;</div><div class='add'>+</div><div class='add'>+		// filled via templated includes at the end of the file</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define DIE</div><div class='add'>+#define DIE_NO 0</div><div class='add'>+</div><div class='add'>+&amp;die0 {</div><div class='add'>+	#include "t602x-die0.dtsi"</div><div class='add'>+	#include "t602x-dieX.dtsi"</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include "t602x-pmgr.dtsi"</div><div class='add'>+#include "t602x-gpio-pins.dtsi"</div><div class='add'>+</div><div class='add'>+#undef DIE</div><div class='add'>+#undef DIE_NO</div><div class='add'>+</div><div class='add'>+#define DIE _die1</div><div class='add'>+#define DIE_NO 1</div><div class='add'>+</div><div class='add'>+&amp;die1 {</div><div class='add'>+	#include "t602x-dieX.dtsi"</div><div class='add'>+	#include "t602x-nvme.dtsi"</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include "t602x-pmgr.dtsi"</div><div class='add'>+</div><div class='add'>+/delete-node/ &amp;ps_pmp_die1;</div><div class='add'>+</div><div class='add'>+#undef DIE</div><div class='add'>+#undef DIE_NO</div><div class='add'>+</div><div class='add'>+&amp;aic {</div><div class='add'>+	affinities {</div><div class='add'>+		e-core-pmu-affinity {</div><div class='add'>+			apple,fiq-index = &lt;AIC_CPU_PMU_E&gt;;</div><div class='add'>+			cpus = &lt;&amp;cpu_e00 &amp;cpu_e01 &amp;cpu_e02 &amp;cpu_e03</div><div class='add'>+				&amp;cpu_e10 &amp;cpu_e11 &amp;cpu_e12 &amp;cpu_e13&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		p-core-pmu-affinity {</div><div class='add'>+			apple,fiq-index = &lt;AIC_CPU_PMU_P&gt;;</div><div class='add'>+			cpus = &lt;&amp;cpu_p00 &amp;cpu_p01 &amp;cpu_p02 &amp;cpu_p03</div><div class='add'>+				&amp;cpu_p10 &amp;cpu_p11 &amp;cpu_p12 &amp;cpu_p13</div><div class='add'>+				&amp;cpu_p20 &amp;cpu_p21 &amp;cpu_p22 &amp;cpu_p23</div><div class='add'>+				&amp;cpu_p30 &amp;cpu_p31 &amp;cpu_p32 &amp;cpu_p33&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ps_gfx {</div><div class='add'>+	// On t6022, the die0 GPU power domain needs both AFR power domains</div><div class='add'>+	power-domains = &lt;&amp;ps_afr&gt;, &lt;&amp;ps_afr_die1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	compatible = "apple,agx-g14d", "apple,agx-g14s";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t602x-common.dtsi b/arch/arm64/boot/dts/apple/t602x-common.dtsi<br/>new file mode 100644<br/>index 000000000000..9c800a391e7e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t602x-common.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t602x-common.dtsi</a></div><div class='hunk'>@@ -0,0 +1,465 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Nodes common to all T602x family SoCs (M2 Pro/Max/Ultra)</div><div class='add'>+ *</div><div class='add'>+ * Other names: H14J, "Rhodes Chop", "Rhodes", "Rhodes 2C"</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		gpu = &amp;gpu;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu-map {</div><div class='add'>+			cluster0 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu_e00&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu_e01&gt;;</div><div class='add'>+				};</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu_e02&gt;;</div><div class='add'>+				};</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu_e03&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cluster1 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu_p00&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu_p01&gt;;</div><div class='add'>+				};</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu_p02&gt;;</div><div class='add'>+				};</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu_p03&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cluster2 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu_p10&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu_p11&gt;;</div><div class='add'>+				};</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu_p12&gt;;</div><div class='add'>+				};</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu_p13&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_e00: cpu@0 {</div><div class='add'>+			compatible = "apple,blizzard";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x0&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* to be filled by loader */</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_0&gt;;</div><div class='add'>+			i-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;blizzard_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;756&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_e&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_e01: cpu@1 {</div><div class='add'>+			compatible = "apple,blizzard";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x1&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* to be filled by loader */</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_0&gt;;</div><div class='add'>+			i-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;blizzard_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;756&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_e&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_e02: cpu@2 {</div><div class='add'>+			compatible = "apple,blizzard";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x2&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* to be filled by loader */</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_0&gt;;</div><div class='add'>+			i-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;blizzard_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;756&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_e&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_e03: cpu@3 {</div><div class='add'>+			compatible = "apple,blizzard";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x3&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* to be filled by loader */</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_0&gt;;</div><div class='add'>+			i-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;blizzard_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;756&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_e&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_p00: cpu@10100 {</div><div class='add'>+			compatible = "apple,avalanche";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x10100&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_1&gt;;</div><div class='add'>+			i-cache-size = &lt;0x30000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;avalanche_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_p0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_p01: cpu@10101 {</div><div class='add'>+			compatible = "apple,avalanche";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x10101&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_1&gt;;</div><div class='add'>+			i-cache-size = &lt;0x30000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;avalanche_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_p0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_p02: cpu@10102 {</div><div class='add'>+			compatible = "apple,avalanche";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x10102&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_1&gt;;</div><div class='add'>+			i-cache-size = &lt;0x30000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;avalanche_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_p0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_p03: cpu@10103 {</div><div class='add'>+			compatible = "apple,avalanche";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x10103&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_1&gt;;</div><div class='add'>+			i-cache-size = &lt;0x30000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;avalanche_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_p0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_p10: cpu@10200 {</div><div class='add'>+			compatible = "apple,avalanche";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x10200&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_2&gt;;</div><div class='add'>+			i-cache-size = &lt;0x30000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;avalanche_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_p1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_p11: cpu@10201 {</div><div class='add'>+			compatible = "apple,avalanche";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x10201&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_2&gt;;</div><div class='add'>+			i-cache-size = &lt;0x30000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;avalanche_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_p1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_p12: cpu@10202 {</div><div class='add'>+			compatible = "apple,avalanche";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x10202&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_2&gt;;</div><div class='add'>+			i-cache-size = &lt;0x30000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;avalanche_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_p1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_p13: cpu@10203 {</div><div class='add'>+			compatible = "apple,avalanche";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x10203&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_2&gt;;</div><div class='add'>+			i-cache-size = &lt;0x30000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;avalanche_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_p1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_cache_0: l2-cache-0 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x400000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_cache_1: l2-cache-1 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x1000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_cache_2: l2-cache-2 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x1000000&gt;;</div><div class='add'>+		};</div><div class='add'>+	 };</div><div class='add'>+</div><div class='add'>+	blizzard_opp: opp-table-0 {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+		opp-shared;</div><div class='add'>+</div><div class='add'>+		/* pstate #1 is a dummy clone of #2 */</div><div class='add'>+		opp02 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;912000000&gt;;</div><div class='add'>+			opp-level = &lt;2&gt;;</div><div class='add'>+			clock-latency-ns = &lt;7700&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp03 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1284000000&gt;;</div><div class='add'>+			opp-level = &lt;3&gt;;</div><div class='add'>+			clock-latency-ns = &lt;25000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp04 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1752000000&gt;;</div><div class='add'>+			opp-level = &lt;4&gt;;</div><div class='add'>+			clock-latency-ns = &lt;33000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp05 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2004000000&gt;;</div><div class='add'>+			opp-level = &lt;5&gt;;</div><div class='add'>+			clock-latency-ns = &lt;38000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp06 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2256000000&gt;;</div><div class='add'>+			opp-level = &lt;6&gt;;</div><div class='add'>+			clock-latency-ns = &lt;44000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp07 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2424000000&gt;;</div><div class='add'>+			opp-level = &lt;7&gt;;</div><div class='add'>+			clock-latency-ns = &lt;48000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	avalanche_opp: opp-table-1 {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+		opp-shared;</div><div class='add'>+</div><div class='add'>+		opp01 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;702000000&gt;;</div><div class='add'>+			opp-level = &lt;1&gt;;</div><div class='add'>+			clock-latency-ns = &lt;7400&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp02 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;948000000&gt;;</div><div class='add'>+			opp-level = &lt;2&gt;;</div><div class='add'>+			clock-latency-ns = &lt;18000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp03 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1188000000&gt;;</div><div class='add'>+			opp-level = &lt;3&gt;;</div><div class='add'>+			clock-latency-ns = &lt;21000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp04 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1452000000&gt;;</div><div class='add'>+			opp-level = &lt;4&gt;;</div><div class='add'>+			clock-latency-ns = &lt;24000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp05 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1704000000&gt;;</div><div class='add'>+			opp-level = &lt;5&gt;;</div><div class='add'>+			clock-latency-ns = &lt;28000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp06 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1968000000&gt;;</div><div class='add'>+			opp-level = &lt;6&gt;;</div><div class='add'>+			clock-latency-ns = &lt;31000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp07 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2208000000&gt;;</div><div class='add'>+			opp-level = &lt;7&gt;;</div><div class='add'>+			clock-latency-ns = &lt;33000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp08 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2400000000&gt;;</div><div class='add'>+			opp-level = &lt;8&gt;;</div><div class='add'>+			clock-latency-ns = &lt;45000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp09 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2568000000&gt;;</div><div class='add'>+			opp-level = &lt;9&gt;;</div><div class='add'>+			clock-latency-ns = &lt;47000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp10 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2724000000&gt;;</div><div class='add'>+			opp-level = &lt;10&gt;;</div><div class='add'>+			clock-latency-ns = &lt;50000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp11 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2868000000&gt;;</div><div class='add'>+			opp-level = &lt;11&gt;;</div><div class='add'>+			clock-latency-ns = &lt;52000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp12 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;3000000000&gt;;</div><div class='add'>+			opp-level = &lt;12&gt;;</div><div class='add'>+			clock-latency-ns = &lt;57000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp13 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;3132000000&gt;;</div><div class='add'>+			opp-level = &lt;13&gt;;</div><div class='add'>+			clock-latency-ns = &lt;60000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp14 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;3264000000&gt;;</div><div class='add'>+			opp-level = &lt;14&gt;;</div><div class='add'>+			clock-latency-ns = &lt;64000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp15 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;3360000000&gt;;</div><div class='add'>+			opp-level = &lt;15&gt;;</div><div class='add'>+			clock-latency-ns = &lt;64000&gt;;</div><div class='add'>+			turbo-mode;</div><div class='add'>+		};</div><div class='add'>+		opp16 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;3408000000&gt;;</div><div class='add'>+			opp-level = &lt;16&gt;;</div><div class='add'>+			clock-latency-ns = &lt;64000&gt;;</div><div class='add'>+			turbo-mode;</div><div class='add'>+		};</div><div class='add'>+		opp17 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;3504000000&gt;;</div><div class='add'>+			opp-level = &lt;17&gt;;</div><div class='add'>+			clock-latency-ns = &lt;64000&gt;;</div><div class='add'>+			turbo-mode;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu-e {</div><div class='add'>+		compatible = "apple,blizzard-pmu";</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_FIQ 0 AIC_CPU_PMU_E IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu-p {</div><div class='add'>+		compatible = "apple,avalanche-pmu";</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_FIQ 0 AIC_CPU_PMU_P IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt";</div><div class='add'>+		interrupts = &lt;AIC_FIQ 0 AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;AIC_FIQ 0 AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;AIC_FIQ 0 AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;AIC_FIQ 0 AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clkref: clock-ref {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+		clock-output-names = "clkref";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_200m: clock-200m {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;200000000&gt;;</div><div class='add'>+		clock-output-names = "clk_200m";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * This is a fabulated representation of the input clock</div><div class='add'>+	 * to NCO since we don't know the true clock tree.</div><div class='add'>+	 */</div><div class='add'>+	nco_clkref: clock-ref-nco {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-output-names = "nco_ref";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		gpu_globals: globals {</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu_hw_cal_a: hw-cal-a {</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu_hw_cal_b: hw-cal-b {</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uat_handoff: uat-handoff {</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uat_pagetables: uat-pagetables {</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uat_ttbs: uat-ttbs {</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t602x-die0.dtsi b/arch/arm64/boot/dts/apple/t602x-die0.dtsi<br/>new file mode 100644<br/>index 000000000000..2e7d2bf08ddc<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t602x-die0.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t602x-die0.dtsi</a></div><div class='hunk'>@@ -0,0 +1,575 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Devices used on die 0 on the Apple T6022 "M2 Ultra" SoC and present on</div><div class='add'>+ * Apple T6020 / T6021 "M2 Pro" / "M2 Max".</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+	nco: clock-controller@28e03c000 {</div><div class='add'>+		compatible = "apple,t6020-nco", "apple,t8103-nco";</div><div class='add'>+		reg = &lt;0x2 0x8e03c000 0x0 0x14000&gt;;</div><div class='add'>+		clocks = &lt;&amp;nco_clkref&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aic: interrupt-controller@28e100000 {</div><div class='add'>+		compatible = "apple,t6020-aic", "apple,aic2";</div><div class='add'>+		#interrupt-cells = &lt;4&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		reg = &lt;0x2 0x8e100000 0x0 0xc000&gt;,</div><div class='add'>+			&lt;0x2 0x8e10c000 0x0 0x1000&gt;;</div><div class='add'>+		reg-names = "core", "event";</div><div class='add'>+		power-domains = &lt;&amp;ps_aic&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	nub_spmi0: spmi@29e114000 {</div><div class='add'>+		compatible = "apple,t6020-spmi", "apple,t8103-spmi";</div><div class='add'>+		reg = &lt;0x2 0x9e114000 0x0 0x100&gt;;</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		pmic1: pmic@f {</div><div class='add'>+			compatible = "apple,maverick-pmic", "apple,spmi-nvmem";</div><div class='add'>+			reg = &lt;0xb SPMI_USID&gt;;</div><div class='add'>+</div><div class='add'>+			nvmem-layout {</div><div class='add'>+				compatible = "fixed-layout";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				pm_setting: pm-setting@1405 {</div><div class='add'>+					reg = &lt;0x1405 0x1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				rtc_offset: rtc-offset@1411 {</div><div class='add'>+					reg = &lt;0x1411 0x6&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				boot_stage: boot-stage@6001 {</div><div class='add'>+					reg = &lt;0x6001 0x1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				boot_error_count: boot-error-count@6002,0 {</div><div class='add'>+					reg = &lt;0x6002 0x1&gt;;</div><div class='add'>+					bits = &lt;0 4&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				panic_count: panic-count@6002,4 {</div><div class='add'>+					reg = &lt;0x6002 0x1&gt;;</div><div class='add'>+					bits = &lt;4 4&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				boot_error_stage: boot-error-stage@6003 {</div><div class='add'>+					reg = &lt;0x6003 0x1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				shutdown_flag: shutdown-flag@600f,3 {</div><div class='add'>+					reg = &lt;0x600f 0x1&gt;;</div><div class='add'>+					bits = &lt;3 1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				fault_shadow: fault-shadow@867b {</div><div class='add'>+					reg = &lt;0x867b 0x10&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				socd: socd@8b00 {</div><div class='add'>+					reg = &lt;0x8b00 0x400&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wdt: watchdog@29e2c4000 {</div><div class='add'>+		compatible = "apple,t6020-wdt", "apple,t8103-wdt";</div><div class='add'>+		reg = &lt;0x2 0x9e2c4000 0x0 0x4000&gt;;</div><div class='add'>+		clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ 0 719 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	smc_mbox: mbox@2a2408000 {</div><div class='add'>+		compatible = "apple,t6020-asc-mailbox", "apple,asc-mailbox-v4";</div><div class='add'>+		reg = &lt;0x2 0xa2408000 0x0 0x4000&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ 0 862 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			&lt;AIC_IRQ 0 863 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			&lt;AIC_IRQ 0 864 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			&lt;AIC_IRQ 0 865 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-names = "send-empty", "send-not-empty",</div><div class='add'>+			"recv-empty", "recv-not-empty";</div><div class='add'>+		#mbox-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	smc: smc@2a2400000 {</div><div class='add'>+		compatible = "apple,t6020-smc", "apple,t8103-smc";</div><div class='add'>+		reg = &lt;0x2 0xa2400000 0x0 0x4000&gt;,</div><div class='add'>+			&lt;0x2 0xa3e00000 0x0 0x100000&gt;;</div><div class='add'>+		reg-names = "smc", "sram";</div><div class='add'>+		mboxes = &lt;&amp;smc_mbox&gt;;</div><div class='add'>+</div><div class='add'>+		smc_gpio: gpio {</div><div class='add'>+			compatible = "apple,smc-gpio";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smc_reboot: reboot {</div><div class='add'>+			compatible = "apple,smc-reboot";</div><div class='add'>+			nvmem-cells = &lt;&amp;shutdown_flag&gt;, &lt;&amp;boot_stage&gt;,</div><div class='add'>+				&lt;&amp;boot_error_count&gt;, &lt;&amp;panic_count&gt;;</div><div class='add'>+			nvmem-cell-names = "shutdown_flag", "boot_stage",</div><div class='add'>+				"boot_error_count", "panic_count";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_smc: pinctrl@2a2820000 {</div><div class='add'>+		compatible = "apple,t6020-pinctrl", "apple,t8103-pinctrl";</div><div class='add'>+		reg = &lt;0x2 0xa2820000 0x0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-ranges = &lt;&amp;pinctrl_smc 0 0 30&gt;;</div><div class='add'>+		apple,npins = &lt;30&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ 0 851 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ 0 852 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ 0 853 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ 0 854 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ 0 855 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ 0 856 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ 0 857 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sio_dart: iommu@39b008000 {</div><div class='add'>+		compatible = "apple,t6020-dart", "apple,t8110-dart";</div><div class='add'>+		reg = &lt;0x3 0x9b008000 0x0 0x8000&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ 0 1231 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		#iommu-cells = &lt;1&gt;;</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_cpu&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fpwm0: pwm@39b030000 {</div><div class='add'>+		compatible = "apple,t6020-fpwm", "apple,s5l-fpwm";</div><div class='add'>+		reg = &lt;0x3 0x9b030000 0x0 0x4000&gt;;</div><div class='add'>+		power-domains = &lt;&amp;ps_fpwm0&gt;;</div><div class='add'>+		clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+		#pwm-cells = &lt;2&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c0: i2c@39b040000 {</div><div class='add'>+		compatible = "apple,t6020-i2c", "apple,t8103-i2c";</div><div class='add'>+		reg = &lt;0x3 0x9b040000 0x0 0x4000&gt;;</div><div class='add'>+		clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ 0 1219 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;i2c0_pins&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		power-domains = &lt;&amp;ps_i2c0&gt;;</div><div class='add'>+		#address-cells = &lt;0x1&gt;;</div><div class='add'>+		#size-cells = &lt;0x0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c1: i2c@39b044000 {</div><div class='add'>+		compatible = "apple,t6020-i2c", "apple,t8103-i2c";</div><div class='add'>+		reg = &lt;0x3 0x9b044000 0x0 0x4000&gt;;</div><div class='add'>+		clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ 0 1220 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;i2c1_pins&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		power-domains = &lt;&amp;ps_i2c1&gt;;</div><div class='add'>+		#address-cells = &lt;0x1&gt;;</div><div class='add'>+		#size-cells = &lt;0x0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c2: i2c@39b048000 {</div><div class='add'>+		compatible = "apple,t6020-i2c", "apple,t8103-i2c";</div><div class='add'>+		reg = &lt;0x3 0x9b048000 0x0 0x4000&gt;;</div><div class='add'>+		clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ 0 1221 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;i2c2_pins&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		power-domains = &lt;&amp;ps_i2c2&gt;;</div><div class='add'>+		#address-cells = &lt;0x1&gt;;</div><div class='add'>+		#size-cells = &lt;0x0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c3: i2c@39b04c000 {</div><div class='add'>+		compatible = "apple,t6020-i2c", "apple,t8103-i2c";</div><div class='add'>+		reg = &lt;0x3 0x9b04c000 0x0 0x4000&gt;;</div><div class='add'>+		clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ 0 1222 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;i2c3_pins&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		power-domains = &lt;&amp;ps_i2c3&gt;;</div><div class='add'>+		#address-cells = &lt;0x1&gt;;</div><div class='add'>+		#size-cells = &lt;0x0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c4: i2c@39b050000 {</div><div class='add'>+		compatible = "apple,t6020-i2c", "apple,t8103-i2c";</div><div class='add'>+		reg = &lt;0x3 0x9b050000 0x0 0x4000&gt;;</div><div class='add'>+		clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ 0 1223 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;i2c4_pins&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		power-domains = &lt;&amp;ps_i2c4&gt;;</div><div class='add'>+		#address-cells = &lt;0x1&gt;;</div><div class='add'>+		#size-cells = &lt;0x0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c5: i2c@39b054000 {</div><div class='add'>+		compatible = "apple,t6020-i2c", "apple,t8103-i2c";</div><div class='add'>+		reg = &lt;0x3 0x9b054000 0x0 0x4000&gt;;</div><div class='add'>+		clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ 0 1224 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;i2c5_pins&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		power-domains = &lt;&amp;ps_i2c5&gt;;</div><div class='add'>+		#address-cells = &lt;0x1&gt;;</div><div class='add'>+		#size-cells = &lt;0x0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c6: i2c@39b054000 {</div><div class='add'>+		compatible = "apple,t6020-i2c", "apple,t8103-i2c";</div><div class='add'>+		reg = &lt;0x3 0x9b054000 0x0 0x4000&gt;;</div><div class='add'>+		clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ 0 1225 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;i2c6_pins&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		power-domains = &lt;&amp;ps_i2c6&gt;;</div><div class='add'>+		#address-cells = &lt;0x1&gt;;</div><div class='add'>+		#size-cells = &lt;0x0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c7: i2c@39b054000 {</div><div class='add'>+		compatible = "apple,t6020-i2c", "apple,t8103-i2c";</div><div class='add'>+		reg = &lt;0x3 0x9b054000 0x0 0x4000&gt;;</div><div class='add'>+		clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ 0 1226 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;i2c7_pins&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		power-domains = &lt;&amp;ps_i2c7&gt;;</div><div class='add'>+		#address-cells = &lt;0x1&gt;;</div><div class='add'>+		#size-cells = &lt;0x0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c8: i2c@39b054000 {</div><div class='add'>+		compatible = "apple,t6020-i2c", "apple,t8103-i2c";</div><div class='add'>+		reg = &lt;0x3 0x9b054000 0x0 0x4000&gt;;</div><div class='add'>+		clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ 0 1227 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;i2c8_pins&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		power-domains = &lt;&amp;ps_i2c8&gt;;</div><div class='add'>+		#address-cells = &lt;0x1&gt;;</div><div class='add'>+		#size-cells = &lt;0x0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi1: spi@39b104000 {</div><div class='add'>+		compatible = "apple,t6020-spi", "apple,t8103-spi";</div><div class='add'>+		reg = &lt;0x3 0x9b104000 0x0 0x4000&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ 0 1206 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk_200m&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;spi1_pins&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		power-domains = &lt;&amp;ps_spi1&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi2: spi@39b108000 {</div><div class='add'>+		compatible = "apple,t6020-spi", "apple,t8103-spi";</div><div class='add'>+		reg = &lt;0x3 0x9b108000 0x0 0x4000&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ 0 1207 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;spi2_pins&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		power-domains = &lt;&amp;ps_spi2&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi4: spi@39b110000 {</div><div class='add'>+		compatible = "apple,t6020-spi", "apple,t8103-spi";</div><div class='add'>+		reg = &lt;0x3 0x9b110000 0x0 0x4000&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ 0 1209 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;spi4_pins&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		power-domains = &lt;&amp;ps_spi4&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	serial0: serial@39b200000 {</div><div class='add'>+		compatible = "apple,s5l-uart";</div><div class='add'>+		reg = &lt;0x3 0x9b200000 0x0 0x4000&gt;;</div><div class='add'>+		reg-io-width = &lt;4&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ 0 1198 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		/*</div><div class='add'>+		 * TODO: figure out the clocking properly, there may</div><div class='add'>+		 * be a third selectable clock.</div><div class='add'>+		 */</div><div class='add'>+		clocks = &lt;&amp;clkref&gt;, &lt;&amp;clkref&gt;;</div><div class='add'>+		clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+		power-domains = &lt;&amp;ps_uart0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	admac: dma-controller@39b400000 {</div><div class='add'>+		compatible = "apple,t6020-admac", "apple,t8103-admac";</div><div class='add'>+		reg = &lt;0x3 0x9b400000 0x0 0x34000&gt;;</div><div class='add'>+		#dma-cells = &lt;1&gt;;</div><div class='add'>+		dma-channels = &lt;16&gt;;</div><div class='add'>+		interrupts-extended = &lt;0&gt;,</div><div class='add'>+				      &lt;&amp;aic AIC_IRQ 0 1218 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				      &lt;0&gt;,</div><div class='add'>+				      &lt;0&gt;;</div><div class='add'>+		iommus = &lt;&amp;sio_dart 2&gt;;</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_adma&gt;;</div><div class='add'>+		resets = &lt;&amp;ps_audio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mca: mca@39b600000 {</div><div class='add'>+		compatible = "apple,t6020-mca", "apple,t8103-mca";</div><div class='add'>+		reg = &lt;0x3 0x9b600000 0x0 0x10000&gt;,</div><div class='add'>+		      &lt;0x3 0x9b500000 0x0 0x20000&gt;;</div><div class='add'>+		clocks = &lt;&amp;nco 0&gt;, &lt;&amp;nco 1&gt;, &lt;&amp;nco 2&gt;, &lt;&amp;nco 3&gt;;</div><div class='add'>+		dmas = &lt;&amp;admac 0&gt;, &lt;&amp;admac 1&gt;, &lt;&amp;admac 2&gt;, &lt;&amp;admac 3&gt;,</div><div class='add'>+		       &lt;&amp;admac 4&gt;, &lt;&amp;admac 5&gt;, &lt;&amp;admac 6&gt;, &lt;&amp;admac 7&gt;,</div><div class='add'>+		       &lt;&amp;admac 8&gt;, &lt;&amp;admac 9&gt;, &lt;&amp;admac 10&gt;, &lt;&amp;admac 11&gt;,</div><div class='add'>+		       &lt;&amp;admac 12&gt;, &lt;&amp;admac 13&gt;, &lt;&amp;admac 14&gt;, &lt;&amp;admac 15&gt;;</div><div class='add'>+		dma-names = "tx0a", "rx0a", "tx0b", "rx0b",</div><div class='add'>+			    "tx1a", "rx1a", "tx1b", "rx1b",</div><div class='add'>+			    "tx2a", "rx2a", "tx2b", "rx2b",</div><div class='add'>+			    "tx3a", "rx3a", "tx3b", "rx3b";</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ 0 1211 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;AIC_IRQ 0 1212 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;AIC_IRQ 0 1213 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;AIC_IRQ 0 1214 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		power-domains = &lt;&amp;ps_audio_p&gt;, &lt;&amp;ps_mca0&gt;, &lt;&amp;ps_mca1&gt;,</div><div class='add'>+				&lt;&amp;ps_mca2&gt;, &lt;&amp;ps_mca3&gt;;</div><div class='add'>+		resets = &lt;&amp;ps_audio_p&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpu: gpu@406400000 {</div><div class='add'>+		compatible = "apple,agx-g14s";</div><div class='add'>+		reg = &lt;0x4 0x6400000 0 0x40000&gt;,</div><div class='add'>+			&lt;0x4 0x4000000 0 0x1000000&gt;;</div><div class='add'>+		reg-names = "asc", "sgx";</div><div class='add'>+		mboxes = &lt;&amp;agx_mbox&gt;;</div><div class='add'>+		power-domains = &lt;&amp;ps_gfx&gt;;</div><div class='add'>+		memory-region = &lt;&amp;uat_ttbs&gt;, &lt;&amp;uat_pagetables&gt;, &lt;&amp;uat_handoff&gt;,</div><div class='add'>+				&lt;&amp;gpu_hw_cal_a&gt;, &lt;&amp;gpu_hw_cal_b&gt;, &lt;&amp;gpu_globals&gt;;</div><div class='add'>+		memory-region-names = "ttbs", "pagetables", "handoff",</div><div class='add'>+				      "hw-cal-a", "hw-cal-b", "globals";</div><div class='add'>+</div><div class='add'>+		apple,firmware-abi = &lt;0 0 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	agx_mbox: mbox@406408000 {</div><div class='add'>+		compatible = "apple,t6020-asc-mailbox", "apple,asc-mailbox-v4";</div><div class='add'>+		reg = &lt;0x4 0x6408000 0x0 0x4000&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ 0 1143 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			&lt;AIC_IRQ 0 1144 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			&lt;AIC_IRQ 0 1145 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			&lt;AIC_IRQ 0 1146 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-names = "send-empty", "send-not-empty",</div><div class='add'>+			"recv-empty", "recv-not-empty";</div><div class='add'>+		#mbox-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0: pcie@580000000 {</div><div class='add'>+		compatible = "apple,t6020-pcie";</div><div class='add'>+		device_type = "pci";</div><div class='add'>+</div><div class='add'>+		reg = &lt;0x5 0x80000000 0x0 0x1000000&gt;,	/* config */</div><div class='add'>+			&lt;0x5 0x91000000 0x0 0x4000&gt;,	/* rc */</div><div class='add'>+			&lt;0x5 0x94008000 0x0 0x4000&gt;,	/* port0 */</div><div class='add'>+			&lt;0x5 0x95008000 0x0 0x4000&gt;,	/* port1 */</div><div class='add'>+			&lt;0x5 0x96008000 0x0 0x4000&gt;,	/* port2 */</div><div class='add'>+			&lt;0x5 0x97008000 0x0 0x4000&gt;,	/* port3 */</div><div class='add'>+			&lt;0x5 0x9e00c000 0x0 0x4000&gt;,	/* phy0 */</div><div class='add'>+			&lt;0x5 0x9e010000 0x0 0x4000&gt;,	/* phy1 */</div><div class='add'>+			&lt;0x5 0x9e014000 0x0 0x4000&gt;,	/* phy2 */</div><div class='add'>+			&lt;0x5 0x9e018000 0x0 0x4000&gt;;	/* phy3 */</div><div class='add'>+		reg-names = "config", "rc",</div><div class='add'>+			"port0", "port1", "port2", "port3",</div><div class='add'>+			"phy0", "phy1", "phy2", "phy3";</div><div class='add'>+</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ 0 1340 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ 0 1344 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ 0 1348 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ 0 1352 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+		msi-controller;</div><div class='add'>+		msi-parent = &lt;&amp;pcie0&gt;;</div><div class='add'>+		msi-ranges = &lt;&amp;aic AIC_IRQ 0 1672 IRQ_TYPE_EDGE_RISING 32&gt;;</div><div class='add'>+</div><div class='add'>+		iommu-map = &lt;0x100 &amp;pcie0_dart_0 1 1&gt;,</div><div class='add'>+				&lt;0x200 &amp;pcie0_dart_1 1 1&gt;,</div><div class='add'>+				&lt;0x300 &amp;pcie0_dart_2 1 1&gt;,</div><div class='add'>+				&lt;0x400 &amp;pcie0_dart_3 1 1&gt;;</div><div class='add'>+		iommu-map-mask = &lt;0xff00&gt;;</div><div class='add'>+</div><div class='add'>+		bus-range = &lt;0 4&gt;;</div><div class='add'>+		#address-cells = &lt;3&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges = &lt;0x43000000 0x5 0xa0000000 0x5 0xa0000000 0x0 0x20000000&gt;,</div><div class='add'>+				&lt;0x02000000 0x0 0xc0000000 0x5 0xc0000000 0x0 0x40000000&gt;;</div><div class='add'>+</div><div class='add'>+		power-domains = &lt;&amp;ps_apcie_gp_sys&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pcie_pins&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		port00: pci@0,0 {</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			reg = &lt;0x0 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;pinctrl_ap 4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;port00 0 0 0 0&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;port00 0 0 0 1&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;port00 0 0 0 2&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;port00 0 0 0 3&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port01: pci@1,0 {</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			reg = &lt;0x800 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;pinctrl_ap 5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;port01 0 0 0 0&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;port01 0 0 0 1&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;port01 0 0 0 2&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;port01 0 0 0 3&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port02: pci@2,0 {</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			reg = &lt;0x1000 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;pinctrl_ap 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;port02 0 0 0 0&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;port02 0 0 0 1&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;port02 0 0 0 2&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;port02 0 0 0 3&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port03: pci@3,0 {</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			reg = &lt;0x1800 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;pinctrl_ap 7 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;port03 0 0 0 0&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;port03 0 0 0 1&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;port03 0 0 0 2&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;port03 0 0 0 3&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_dart_0: iommu@594000000 {</div><div class='add'>+		compatible = "apple,t6020-dart", "apple,t8110-dart";</div><div class='add'>+		reg = &lt;0x5 0x94000000 0x0 0x4000&gt;;</div><div class='add'>+		#iommu-cells = &lt;1&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ 0 1341 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		power-domains = &lt;&amp;ps_apcie_gp_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_dart_1: iommu@595000000 {</div><div class='add'>+		compatible = "apple,t6020-dart", "apple,t8110-dart";</div><div class='add'>+		reg = &lt;0x5 0x95000000 0x0 0x4000&gt;;</div><div class='add'>+		#iommu-cells = &lt;1&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ 0 1345 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		power-domains = &lt;&amp;ps_apcie_gp_sys&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_dart_2: iommu@596000000 {</div><div class='add'>+		compatible = "apple,t6020-dart", "apple,t8110-dart";</div><div class='add'>+		reg = &lt;0x5 0x96000000 0x0 0x4000&gt;;</div><div class='add'>+		#iommu-cells = &lt;1&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ 0 1349 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		power-domains = &lt;&amp;ps_apcie_gp_sys&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_dart_3: iommu@597000000 {</div><div class='add'>+		compatible = "apple,t6020-dart", "apple,t8110-dart";</div><div class='add'>+		reg = &lt;0x5 0x97000000 0x0 0x4000&gt;;</div><div class='add'>+		#iommu-cells = &lt;1&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ 0 1353 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		power-domains = &lt;&amp;ps_apcie_gp_sys&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t602x-dieX.dtsi b/arch/arm64/boot/dts/apple/t602x-dieX.dtsi<br/>new file mode 100644<br/>index 000000000000..cb07fd82b32e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t602x-dieX.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t602x-dieX.dtsi</a></div><div class='hunk'>@@ -0,0 +1,128 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Nodes present on both dies of T6022 (M2 Ultra) and present on M2 Pro/Max.</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+	DIE_NODE(cpufreq_e): cpufreq@210e20000 {</div><div class='add'>+		compatible = "apple,t6020-cluster-cpufreq", "apple,t8112-cluster-cpufreq";</div><div class='add'>+		reg = &lt;0x2 0x10e20000 0 0x1000&gt;;</div><div class='add'>+		#performance-domain-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(cpufreq_p0): cpufreq@211e20000 {</div><div class='add'>+		compatible = "apple,t6020-cluster-cpufreq", "apple,t8112-cluster-cpufreq";</div><div class='add'>+		reg = &lt;0x2 0x11e20000 0 0x1000&gt;;</div><div class='add'>+		#performance-domain-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(cpufreq_p1): cpufreq@212e20000 {</div><div class='add'>+		compatible = "apple,t6020-cluster-cpufreq", "apple,t8112-cluster-cpufreq";</div><div class='add'>+		reg = &lt;0x2 0x12e20000 0 0x1000&gt;;</div><div class='add'>+		#performance-domain-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(pmgr): power-management@28e080000 {</div><div class='add'>+		compatible = "apple,t6020-pmgr", "apple,t8103-pmgr", "syscon", "simple-mfd";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		reg = &lt;0x2 0x8e080000 0 0x8000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(pmgr_south): power-management@28e680000 {</div><div class='add'>+		compatible = "apple,t6020-pmgr", "apple,t8103-pmgr", "syscon", "simple-mfd";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		reg = &lt;0x2 0x8e680000 0 0x8000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(pmgr_east): power-management@290280000 {</div><div class='add'>+		compatible = "apple,t6020-pmgr", "apple,t8103-pmgr", "syscon", "simple-mfd";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		reg = &lt;0x2 0x90280000 0 0xc000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(pinctrl_nub): pinctrl@29e1f0000 {</div><div class='add'>+		compatible = "apple,t6020-pinctrl", "apple,t8103-pinctrl";</div><div class='add'>+		reg = &lt;0x2 0x9e1f0000 0x0 0x4000&gt;;</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_nub_gpio)&gt;;</div><div class='add'>+</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-ranges = &lt;&amp;DIE_NODE(pinctrl_nub) 0 0 30&gt;;</div><div class='add'>+		apple,npins = &lt;30&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ DIE_NO 711 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ DIE_NO 712 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ DIE_NO 713 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ DIE_NO 714 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ DIE_NO 715 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ DIE_NO 716 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ DIE_NO 717 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(pmgr_mini): power-management@29e280000 {</div><div class='add'>+		compatible = "apple,t6020-pmgr", "apple,t8103-pmgr", "syscon", "simple-mfd";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		reg = &lt;0x2 0x9e280000 0 0x4000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(pinctrl_aop): pinctrl@2a6820000 {</div><div class='add'>+		compatible = "apple,t6020-pinctrl", "apple,t8103-pinctrl";</div><div class='add'>+		reg = &lt;0x2 0xa6820000 0x0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-ranges = &lt;&amp;DIE_NODE(pinctrl_aop) 0 0 72&gt;;</div><div class='add'>+		apple,npins = &lt;72&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ DIE_NO 598 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ DIE_NO 599 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ DIE_NO 600 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ DIE_NO 601 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ DIE_NO 602 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ DIE_NO 603 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ DIE_NO 604 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(pinctrl_ap): pinctrl@39b028000 {</div><div class='add'>+		compatible = "apple,t6020-pinctrl", "apple,t8103-pinctrl";</div><div class='add'>+		reg = &lt;0x3 0x9b028000 0x0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ DIE_NO 458 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ DIE_NO 459 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ DIE_NO 460 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ DIE_NO 461 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ DIE_NO 462 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ DIE_NO 463 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ DIE_NO 464 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_gpio)&gt;;</div><div class='add'>+</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-ranges = &lt;&amp;DIE_NODE(pinctrl_ap) 0 0 255&gt;;</div><div class='add'>+		apple,npins = &lt;255&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(pmgr_gfx): power-management@404e80000 {</div><div class='add'>+		compatible = "apple,t6020-pmgr", "apple,t8103-pmgr", "syscon", "simple-mfd";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		reg = &lt;0x4 0x4e80000 0 0x4000&gt;;</div><div class='add'>+	};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t602x-gpio-pins.dtsi b/arch/arm64/boot/dts/apple/t602x-gpio-pins.dtsi<br/>new file mode 100644<br/>index 000000000000..e41b6475f792<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t602x-gpio-pins.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t602x-gpio-pins.dtsi</a></div><div class='hunk'>@@ -0,0 +1,81 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * GPIO pin mappings for Apple T602x SoCs.</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_ap {</div><div class='add'>+	i2c0_pins: i2c0-pins {</div><div class='add'>+		pinmux = &lt;APPLE_PINMUX(63, 1)&gt;,</div><div class='add'>+			&lt;APPLE_PINMUX(64, 1)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c1_pins: i2c1-pins {</div><div class='add'>+		pinmux = &lt;APPLE_PINMUX(65, 1)&gt;,</div><div class='add'>+			&lt;APPLE_PINMUX(66, 1)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c2_pins: i2c2-pins {</div><div class='add'>+		pinmux = &lt;APPLE_PINMUX(67, 1)&gt;,</div><div class='add'>+			&lt;APPLE_PINMUX(68, 1)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c3_pins: i2c3-pins {</div><div class='add'>+		pinmux = &lt;APPLE_PINMUX(69, 1)&gt;,</div><div class='add'>+			&lt;APPLE_PINMUX(70, 1)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c4_pins: i2c4-pins {</div><div class='add'>+		pinmux = &lt;APPLE_PINMUX(71, 1)&gt;,</div><div class='add'>+			&lt;APPLE_PINMUX(72, 1)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c5_pins: i2c5-pins {</div><div class='add'>+		pinmux = &lt;APPLE_PINMUX(73, 1)&gt;,</div><div class='add'>+			&lt;APPLE_PINMUX(74, 1)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c6_pins: i2c6-pins {</div><div class='add'>+		pinmux = &lt;APPLE_PINMUX(75, 1)&gt;,</div><div class='add'>+			&lt;APPLE_PINMUX(76, 1)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c7_pins: i2c7-pins {</div><div class='add'>+		pinmux = &lt;APPLE_PINMUX(77, 1)&gt;,</div><div class='add'>+			&lt;APPLE_PINMUX(78, 1)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c8_pins: i2c8-pins {</div><div class='add'>+		pinmux = &lt;APPLE_PINMUX(79, 1)&gt;,</div><div class='add'>+			&lt;APPLE_PINMUX(80, 1)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi1_pins: spi1-pins {</div><div class='add'>+		pinmux = &lt;APPLE_PINMUX(155, 1)&gt;, /* SDI */</div><div class='add'>+			&lt;APPLE_PINMUX(156, 1)&gt;,  /* SDO */</div><div class='add'>+			&lt;APPLE_PINMUX(157, 1)&gt;,  /* SCK */</div><div class='add'>+			&lt;APPLE_PINMUX(158, 1)&gt;;  /* CS */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi2_pins: spi2-pins {</div><div class='add'>+		pinmux = &lt;APPLE_PINMUX(159, 1)&gt;, /* SDI */</div><div class='add'>+			&lt;APPLE_PINMUX(160, 1)&gt;,  /* SDO */</div><div class='add'>+			&lt;APPLE_PINMUX(161, 1)&gt;,  /* SCK */</div><div class='add'>+			&lt;APPLE_PINMUX(162, 1)&gt;;  /* CS */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi4_pins: spi4-pins {</div><div class='add'>+		pinmux = &lt;APPLE_PINMUX(167, 1)&gt;, /* SDI */</div><div class='add'>+			&lt;APPLE_PINMUX(168, 1)&gt;,  /* SDO */</div><div class='add'>+			&lt;APPLE_PINMUX(169, 1)&gt;,  /* SCK */</div><div class='add'>+			&lt;APPLE_PINMUX(170, 1)&gt;;  /* CS */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie_pins: pcie-pins {</div><div class='add'>+		pinmux = &lt;APPLE_PINMUX(0, 1)&gt;,</div><div class='add'>+				&lt;APPLE_PINMUX(1, 1)&gt;,</div><div class='add'>+				&lt;APPLE_PINMUX(2, 1)&gt;,</div><div class='add'>+				&lt;APPLE_PINMUX(3, 1)&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t602x-j414-j416.dtsi b/arch/arm64/boot/dts/apple/t602x-j414-j416.dtsi<br/>new file mode 100644<br/>index 000000000000..0e806d8ddf81<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t602x-j414-j416.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t602x-j414-j416.dtsi</a></div><div class='hunk'>@@ -0,0 +1,45 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * MacBook Pro (14/16-inch, 2022)</div><div class='add'>+ *</div><div class='add'>+ * This file contains the parts common to J414 and J416 devices with both t6020 and t6021.</div><div class='add'>+ *</div><div class='add'>+ * target-type: J414s / J414c / J416s / J416c</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * These models are essentially identical to the previous generation, other than</div><div class='add'>+ * the GPIO indices.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "t600x-j314-j316.dtsi"</div><div class='add'>+</div><div class='add'>+&amp;framebuffer0 {</div><div class='add'>+	power-domains = &lt;&amp;ps_disp0_cpu0&gt;, &lt;&amp;ps_dptx_phy_ps&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hpm0 {</div><div class='add'>+	interrupts = &lt;44 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hpm1 {</div><div class='add'>+	interrupts = &lt;44 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hpm2 {</div><div class='add'>+	interrupts = &lt;44 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hpm5 {</div><div class='add'>+	interrupts = &lt;44 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wifi0 {</div><div class='add'>+	compatible = "pci14e4,4434";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;bluetooth0 {</div><div class='add'>+	compatible = "pci14e4,5f72";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t602x-j474-j475.dtsi b/arch/arm64/boot/dts/apple/t602x-j474-j475.dtsi<br/>new file mode 100644<br/>index 000000000000..ee12fea5b12c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t602x-j474-j475.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t602x-j474-j475.dtsi</a></div><div class='hunk'>@@ -0,0 +1,38 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Mac mini (M2 Pro, 2023) and Mac Studio (2023)</div><div class='add'>+ *</div><div class='add'>+ * This file contains the parts common to J474 and J475 devices with t6020,</div><div class='add'>+ * t6021 and t6022.</div><div class='add'>+ *</div><div class='add'>+ * target-type: J474s / J475c / J475d</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * These models are very similar to the previous generation Mac Studio, other</div><div class='add'>+ * than GPIO indices.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "t600x-j375.dtsi"</div><div class='add'>+</div><div class='add'>+&amp;framebuffer0 {</div><div class='add'>+	power-domains = &lt;&amp;ps_dispext0_cpu0&gt;, &lt;&amp;ps_dptx_phy_ps&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hpm0 {</div><div class='add'>+	interrupts = &lt;44 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hpm1 {</div><div class='add'>+	interrupts = &lt;44 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hpm2 {</div><div class='add'>+	interrupts = &lt;44 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hpm3  {</div><div class='add'>+	interrupts = &lt;44 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t602x-nvme.dtsi b/arch/arm64/boot/dts/apple/t602x-nvme.dtsi<br/>new file mode 100644<br/>index 000000000000..590cec8ac804<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t602x-nvme.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t602x-nvme.dtsi</a></div><div class='hunk'>@@ -0,0 +1,42 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * NVMe related devices for Apple T602x SoCs.</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ans_mbox): mbox@347408000 {</div><div class='add'>+		compatible = "apple,t6020-asc-mailbox", "apple,asc-mailbox-v4";</div><div class='add'>+		reg = &lt;0x3 0x47408000 0x0 0x4000&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_IRQ DIE_NO 1169 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			&lt;AIC_IRQ DIE_NO 1170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			&lt;AIC_IRQ DIE_NO 1171 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			&lt;AIC_IRQ DIE_NO 1172 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-names = "send-empty", "send-not-empty",</div><div class='add'>+			"recv-empty", "recv-not-empty";</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_ans2)&gt;;</div><div class='add'>+		#mbox-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(sart): sart@34bc50000 {</div><div class='add'>+		compatible = "apple,t6020-sart", "apple,t6000-sart";</div><div class='add'>+		reg = &lt;0x3 0x4bc50000 0x0 0x10000&gt;;</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_ans2)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(nvme): nvme@34bcc0000 {</div><div class='add'>+		compatible = "apple,t6020-nvme-ans2", "apple,t8103-nvme-ans2";</div><div class='add'>+		reg = &lt;0x3 0x4bcc0000 0x0 0x40000&gt;, &lt;0x3 0x47400000 0x0 0x4000&gt;;</div><div class='add'>+		reg-names = "nvme", "ans";</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		/* The NVME interrupt is always routed to die 0 */</div><div class='add'>+		interrupts = &lt;AIC_IRQ 0 1832 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		mboxes = &lt;&amp;DIE_NODE(ans_mbox)&gt;;</div><div class='add'>+		apple,sart = &lt;&amp;DIE_NODE(sart)&gt;;</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_ans2)&gt;,</div><div class='add'>+			&lt;&amp;DIE_NODE(ps_apcie_st_sys)&gt;,</div><div class='add'>+			&lt;&amp;DIE_NODE(ps_apcie_st1_sys)&gt;;</div><div class='add'>+		power-domain-names = "ans", "apcie0", "apcie1";</div><div class='add'>+		resets = &lt;&amp;DIE_NODE(ps_ans2)&gt;;</div><div class='add'>+	};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t602x-pmgr.dtsi b/arch/arm64/boot/dts/apple/t602x-pmgr.dtsi<br/>new file mode 100644<br/>index 000000000000..f5382a2faf0b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t602x-pmgr.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t602x-pmgr.dtsi</a></div><div class='hunk'>@@ -0,0 +1,2265 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * PMGR Power domains for Apple T602x "M2 Pro/Max/Ultra" SoC</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;DIE_NODE(pmgr) {</div><div class='add'>+	DIE_NODE(ps_afi): power-controller@100 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x100 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afi);</div><div class='add'>+		apple,always-on; /* Apple Fabric, CPU interface is here */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_aic): power-controller@108 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x108 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(aic);</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dwi): power-controller@110 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x110 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dwi);</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_pms): power-controller@118 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x118 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(pms);</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_gpio): power-controller@120 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x120 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(gpio);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_sio)&gt;, &lt;&amp;DIE_NODE(ps_pms)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_soc_dpe): power-controller@128 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x128 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(soc_dpe);</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_pms_c1ppt): power-controller@130 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x130 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(pms_c1ppt);</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_pmgr_soc_ocla): power-controller@138 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x138 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(pmgr_soc_ocla);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_sio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_amcc0): power-controller@168 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x168 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(amcc0);</div><div class='add'>+		apple,always-on; /* Memory controller */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_amcc2): power-controller@170 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x170 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(amcc2);</div><div class='add'>+		apple,always-on; /* Memory controller */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_00): power-controller@178 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x178 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_00);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_01): power-controller@180 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x180 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_01);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_02): power-controller@188 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x188 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_02);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_03): power-controller@190 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x190 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_03);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_08): power-controller@198 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x198 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_08);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_09): power-controller@1a0 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1a0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_09);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_10): power-controller@1a8 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1a8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_10);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_11): power-controller@1b0 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1b0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_11);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afnc1_ioa): power-controller@1b8 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1b8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afnc1_ioa);</div><div class='add'>+		apple,always-on; /* Apple Fabric */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afi)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afc): power-controller@1d0 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1d0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afc);</div><div class='add'>+		apple,always-on; /* Apple Fabric, CPU interface is here */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afnc0_ioa): power-controller@1e8 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1e8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afnc0_ioa);</div><div class='add'>+		apple,always-on; /* Apple Fabric */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afi)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afnc1_ls): power-controller@1f0 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1f0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afnc1_ls);</div><div class='add'>+		apple,always-on; /* Apple Fabric */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc1_ioa)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afnc0_ls): power-controller@1f8 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1f8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afnc0_ls);</div><div class='add'>+		apple,always-on; /* Apple Fabric */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc0_ioa)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afnc1_lw0): power-controller@200 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x200 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afnc1_lw0);</div><div class='add'>+		apple,always-on; /* Apple Fabric */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc1_ls)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afnc1_lw1): power-controller@208 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x208 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afnc1_lw1);</div><div class='add'>+		apple,always-on; /* Apple Fabric */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc1_ls)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afnc1_lw2): power-controller@210 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x210 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afnc1_lw2);</div><div class='add'>+		apple,always-on; /* Apple Fabric */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc1_ls)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afnc0_lw0): power-controller@218 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x218 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afnc0_lw0);</div><div class='add'>+		apple,always-on; /* Apple Fabric */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc0_ls)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_scodec): power-controller@220 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x220 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(scodec);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc1_lw0)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc0_common): power-controller@228 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x228 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc0_common);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc1_lw1)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc1_common): power-controller@230 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x230 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc1_common);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc1_lw1)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc2_common): power-controller@238 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x238 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc2_common);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc1_lw1)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc3_common): power-controller@240 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x240 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc3_common);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc1_lw1)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dispext1_sys): power-controller@248 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x248 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dispext1_sys);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc1_lw2)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_pms_bridge): power-controller@250 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x250 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(pms_bridge);</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc0_lw0)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dispext0_sys): power-controller@258 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x258 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dispext0_sys);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc0_lw0)&gt;, &lt;&amp;DIE_NODE(ps_afr)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_ane_sys): power-controller@260 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x260 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(ane_sys);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc0_lw0)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_avd_sys): power-controller@268 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x268 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(avd_sys);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc0_lw0)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc0_cio): power-controller@270 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x270 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc0_cio);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_atc0_common)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc0_pcie): power-controller@278 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x278 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc0_pcie);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_atc0_common)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc1_cio): power-controller@280 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x280 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc1_cio);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_atc1_common)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc1_pcie): power-controller@288 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x288 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc1_pcie);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_atc1_common)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc2_cio): power-controller@290 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x290 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc2_cio);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_atc2_common)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc2_pcie): power-controller@298 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x298 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc2_pcie);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_atc2_common)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc3_cio): power-controller@2a0 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2a0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc3_cio);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_atc3_common)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc3_pcie): power-controller@2a8 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2a8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc3_pcie);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_atc3_common)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dispext1_fe): power-controller@2b0 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2b0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dispext1_fe);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_dispext1_sys)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dispext1_cpu0): power-controller@2b8 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2b8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dispext1_cpu0);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_dispext1_fe)&gt;;</div><div class='add'>+		apple,min-state = &lt;4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dispext0_fe): power-controller@2c0 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2c0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dispext0_fe);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_dispext0_sys)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_pmp): power-controller@2c8 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2c8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(pmp);</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_pms_sram): power-controller@2d0 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2d0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(pms_sram);</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dispext0_cpu0): power-controller@2d8 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2d8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dispext0_cpu0);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_dispext0_fe)&gt;;</div><div class='add'>+		apple,min-state = &lt;4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_ane_cpu): power-controller@2e0 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2e0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(ane_cpu);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_ane_sys)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc0_cio_pcie): power-controller@2e8 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2e8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc0_cio_pcie);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_atc0_cio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc0_cio_usb): power-controller@2f0 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2f0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc0_cio_usb);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_atc0_cio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc1_cio_pcie): power-controller@2f8 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2f8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc1_cio_pcie);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_atc1_cio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc1_cio_usb): power-controller@300 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x300 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc1_cio_usb);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_atc1_cio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc2_cio_pcie): power-controller@308 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x308 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc2_cio_pcie);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_atc2_cio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc2_cio_usb): power-controller@310 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x310 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc2_cio_usb);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_atc2_cio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc3_cio_pcie): power-controller@318 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x318 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc3_cio_pcie);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_atc3_cio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc3_cio_usb): power-controller@320 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x320 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc3_cio_usb);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_atc3_cio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_trace_fab): power-controller@390 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x390 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(trace_fab);</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_ane_sys_mpm): power-controller@4000 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x4000 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(ane_sys_mpm);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_ane_sys)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_ane_td): power-controller@4008 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x4008 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(ane_td);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_ane_sys)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_ane_base): power-controller@4010 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x4010 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(ane_base);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_ane_td)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_ane_set1): power-controller@4018 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x4018 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(ane_set1);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_ane_base)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_ane_set2): power-controller@4020 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x4020 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(ane_set2);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_ane_set1)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_ane_set3): power-controller@4028 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x4028 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(ane_set3);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_ane_set2)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_ane_set4): power-controller@4030 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x4030 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(ane_set4);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_ane_set3)&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;DIE_NODE(pmgr_south) {</div><div class='add'>+	DIE_NODE(ps_amcc4): power-controller@100 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x100 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(amcc4);</div><div class='add'>+		apple,always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_amcc5): power-controller@108 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x108 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(amcc5);</div><div class='add'>+		apple,always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_amcc6): power-controller@110 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x110 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(amcc6);</div><div class='add'>+		apple,always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_amcc7): power-controller@118 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x118 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(amcc7);</div><div class='add'>+		apple,always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_16): power-controller@120 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x120 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_16);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_17): power-controller@128 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x128 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_17);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_18): power-controller@130 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x130 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_18);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_19): power-controller@138 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x138 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_19);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_20): power-controller@140 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x140 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_20);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_21): power-controller@148 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x148 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_21);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_22): power-controller@150 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x150 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_22);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_23): power-controller@158 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x158 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_23);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_24): power-controller@160 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x160 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_24);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_25): power-controller@168 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x168 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_25);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_26): power-controller@170 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x170 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_26);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_27): power-controller@178 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x178 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_27);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_28): power-controller@180 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x180 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_28);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_29): power-controller@188 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x188 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_29);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_30): power-controller@190 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x190 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_30);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_31): power-controller@198 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x198 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_31);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afnc4_ioa): power-controller@1a0 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1a0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afnc4_ioa);</div><div class='add'>+		apple,always-on; /* Apple Fabric */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afi)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afnc4_ls): power-controller@1a8 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1a8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afnc4_ls);</div><div class='add'>+		apple,always-on; /* Apple Fabric */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc4_ioa)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afnc4_lw0): power-controller@1b0 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1b0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afnc4_lw0);</div><div class='add'>+		apple,always-on; /* Apple Fabric */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc4_ls)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afnc5_ioa): power-controller@1b8 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1b8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afnc5_ioa);</div><div class='add'>+		apple,always-on; /* Apple Fabric */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afi)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afnc5_ls): power-controller@1c0 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1c0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afnc5_ls);</div><div class='add'>+		apple,always-on; /* Apple Fabric */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc5_ioa)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afnc5_lw0): power-controller@1c8 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1c8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afnc5_lw0);</div><div class='add'>+		apple,always-on; /* Apple Fabric */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc5_ls)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dispext2_sys): power-controller@1d0 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1d0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dispext2_sys);</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_msr1): power-controller@1d8 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1d8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(msr1);</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dispext2_fe): power-controller@1e0 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1e0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dispext2_fe);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_dispext2_sys)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dispext2_cpu0): power-controller@1e8 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1e8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dispext2_cpu0);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_dispext2_fe)&gt;;</div><div class='add'>+		apple,min-state = &lt;4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_msr1_ase_core): power-controller@1f0 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1f0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(msr1_ase_core);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_msr1)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dispext3_sys): power-controller@220 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x220 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dispext3_sys);</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_venc1_sys): power-controller@228 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x228 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(venc1_sys);</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dispext3_fe): power-controller@230 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x230 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dispext3_fe);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_dispext3_sys)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dispext3_cpu0): power-controller@238 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x238 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dispext3_cpu0);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_dispext3_fe)&gt;;</div><div class='add'>+		apple,min-state = &lt;4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_venc1_dma): power-controller@4000 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x4000 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(venc1_dma);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_venc1_sys)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_venc1_pipe4): power-controller@4008 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x4008 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(venc1_pipe4);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_venc1_dma)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_venc1_pipe5): power-controller@4010 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x4010 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(venc1_pipe5);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_venc1_dma)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_venc1_me0): power-controller@4018 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x4018 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(venc1_me0);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_venc1_pipe5)&gt;, &lt;&amp;DIE_NODE(ps_venc1_pipe4)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_venc1_me1): power-controller@4020 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x4020 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(venc1_me1);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_venc1_me0)&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;DIE_NODE(pmgr_east) {</div><div class='add'>+	DIE_NODE(ps_clvr_spmi0): power-controller@100 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x100 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(clvr_spmi0);</div><div class='add'>+		apple,always-on; /* PCPU voltage regulator interface (used by SMC) */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_clvr_spmi1): power-controller@108 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x108 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(clvr_spmi1);</div><div class='add'>+		apple,always-on; /* GPU voltage regulator interface (used by SMC) */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_clvr_spmi2): power-controller@110 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x110 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(clvr_spmi2);</div><div class='add'>+		apple,always-on; /* ANE, fabric, AFR voltage regulator interface (used by SMC) */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_clvr_spmi3): power-controller@118 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x118 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(clvr_spmi3);</div><div class='add'>+		apple,always-on; /* Additional voltage regulator, probably used on T6021 (SMC) */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_clvr_spmi4): power-controller@120 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x120 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(clvr_spmi4);</div><div class='add'>+		apple,always-on; /* Additional voltage regulator, probably used on T6021 (SMC) */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_ispsens0): power-controller@128 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x128 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(ispsens0);</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_ispsens1): power-controller@130 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x130 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(ispsens1);</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_ispsens2): power-controller@138 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x138 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(ispsens2);</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_ispsens3): power-controller@140 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x140 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(ispsens3);</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afnc6_ioa): power-controller@148 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x148 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afnc6_ioa);</div><div class='add'>+		apple,always-on;</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afi)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afnc6_ls): power-controller@150 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x150 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afnc6_ls);</div><div class='add'>+		apple,always-on;</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc6_ioa)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afnc6_lw0): power-controller@158 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x158 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afnc6_lw0);</div><div class='add'>+		apple,always-on;</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc6_ls)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afnc2_ioa): power-controller@160 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x160 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afnc2_ioa);</div><div class='add'>+		apple,always-on;</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_dcs_10)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afnc2_ls): power-controller@168 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x168 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afnc2_ls);</div><div class='add'>+		apple,always-on;</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc2_ioa)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afnc2_lw0): power-controller@170 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x170 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afnc2_lw0);</div><div class='add'>+		apple,always-on;</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc2_ls)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afnc2_lw1): power-controller@178 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x178 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afnc2_lw1);</div><div class='add'>+		apple,always-on;</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc2_ls)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afnc3_ioa): power-controller@180 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x180 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afnc3_ioa);</div><div class='add'>+		apple,always-on;</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afi)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afnc3_ls): power-controller@188 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x188 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afnc3_ls);</div><div class='add'>+		apple,always-on;</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc3_ioa)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afnc3_lw0): power-controller@190 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x190 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afnc3_lw0);</div><div class='add'>+		apple,always-on;</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc3_ls)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_apcie_gp): power-controller@198 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x198 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(apcie_gp);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc6_lw0)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_apcie_st): power-controller@1a0 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1a0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(apcie_st);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc6_lw0)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_ans2): power-controller@1a8 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1a8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(ans2);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc6_lw0)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_disp0_sys): power-controller@1b0 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1b0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(disp0_sys);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc2_lw0)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_jpg): power-controller@1b8 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1b8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(jpg);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc2_lw0)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_sio): power-controller@1c0 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1c0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(sio);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc2_lw1)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_isp_sys): power-controller@1c8 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1c8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(isp_sys);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc2_lw1)&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_disp0_fe): power-controller@1d0 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1d0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(disp0_fe);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_disp0_sys)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_disp0_cpu0): power-controller@1d8 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1d8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(disp0_cpu0);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_disp0_fe)&gt;;</div><div class='add'>+		apple,min-state = &lt;4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_sio_cpu): power-controller@1e0 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1e0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(sio_cpu);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_sio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_fpwm0): power-controller@1e8 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1e8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(fpwm0);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_sio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_fpwm1): power-controller@1f0 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1f0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(fpwm1);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_sio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_fpwm2): power-controller@1f8 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1f8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(fpwm2);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_sio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_i2c0): power-controller@200 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x200 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(i2c0);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_sio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_i2c1): power-controller@208 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x208 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(i2c1);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_sio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_i2c2): power-controller@210 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x210 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(i2c2);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_sio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_i2c3): power-controller@218 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x218 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(i2c3);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_sio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_i2c4): power-controller@220 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x220 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(i2c4);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_sio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_i2c5): power-controller@228 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x228 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(i2c5);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_sio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_i2c6): power-controller@230 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x230 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(i2c6);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_sio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_i2c7): power-controller@238 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x238 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(i2c7);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_sio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_i2c8): power-controller@240 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x240 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(i2c8);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_sio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_spi_p): power-controller@248 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x248 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(spi_p);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_sio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_sio_spmi0): power-controller@250 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x250 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(sio_spmi0);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_sio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_sio_spmi1): power-controller@258 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x258 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(sio_spmi1);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_sio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_sio_spmi2): power-controller@260 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x260 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(sio_spmi2);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_sio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_uart_p): power-controller@268 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x268 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(uart_p);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_sio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_audio_p): power-controller@270 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x270 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(audio_p);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_sio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_sio_adma): power-controller@278 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x278 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(sio_adma);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_audio_p)&gt;, &lt;&amp;DIE_NODE(ps_sio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_aes): power-controller@280 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x280 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(aes);</div><div class='add'>+		apple,always-on;</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_sio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dptx_phy_ps): power-controller@288 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x288 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dptx_phy_ps);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_sio)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_spi0): power-controller@2d8 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2d8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(spi0);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_spi_p)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_spi1): power-controller@2e0 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2e0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(spi1);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_spi_p)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_spi2): power-controller@2e8 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2e8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(spi2);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_spi_p)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_spi3): power-controller@2f0 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2f0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(spi3);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_spi_p)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_spi4): power-controller@2f8 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2f8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(spi4);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_spi_p)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_spi5): power-controller@300 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x300 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(spi5);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_spi_p)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_uart_n): power-controller@308 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x308 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(uart_n);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_uart_p)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_uart0): power-controller@310 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x310 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(uart0);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_uart_p)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_amcc1): power-controller@318 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x318 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(amcc1);</div><div class='add'>+		apple,always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_amcc3): power-controller@320 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x320 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(amcc3);</div><div class='add'>+		apple,always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_04): power-controller@328 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x328 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_04);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_05): power-controller@330 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x330 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_05);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_06): power-controller@338 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x338 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_06);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_07): power-controller@340 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x340 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_07);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_12): power-controller@348 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x348 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_12);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_13): power-controller@350 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x350 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_13);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_14): power-controller@358 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x358 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_14);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dcs_15): power-controller@360 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x360 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dcs_15);</div><div class='add'>+		apple,always-on; /* LPDDR5 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_uart1): power-controller@368 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x368 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(uart1);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_uart_p)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_uart2): power-controller@370 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x370 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(uart2);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_uart_p)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_uart3): power-controller@378 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x378 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(uart3);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_uart_p)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_uart4): power-controller@380 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x380 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(uart4);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_uart_p)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_uart5): power-controller@388 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x388 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(uart5);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_uart_p)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_uart6): power-controller@390 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x390 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(uart6);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_uart_p)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_mca0): power-controller@398 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x398 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(mca0);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_audio_p)&gt;, &lt;&amp;DIE_NODE(ps_sio_adma)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_mca1): power-controller@3a0 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x3a0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(mca1);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_audio_p)&gt;, &lt;&amp;DIE_NODE(ps_sio_adma)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_mca2): power-controller@3a8 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x3a8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(mca2);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_audio_p)&gt;, &lt;&amp;DIE_NODE(ps_sio_adma)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_mca3): power-controller@3b0 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x3b0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(mca3);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_audio_p)&gt;, &lt;&amp;DIE_NODE(ps_sio_adma)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dpa0): power-controller@3b8 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x3b8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dpa0);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_audio_p)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dpa1): power-controller@3c0 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x3c0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dpa1);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_audio_p)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dpa2): power-controller@3c8 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x3c8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dpa2);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_audio_p)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dpa3): power-controller@3d0 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x3d0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dpa3);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_audio_p)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_msr0): power-controller@3d8 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x3d8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(msr0);</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_venc_sys): power-controller@3e0 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x3e0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(venc_sys);</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dpa4): power-controller@3e8 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x3e8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dpa4);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_audio_p)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_msr0_ase_core): power-controller@3f0 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x3f0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(msr0_ase_core);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_msr0)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_apcie_gpshr_sys): power-controller@3f8 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x3f8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(apcie_gpshr_sys);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_apcie_gp)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_apcie_st_sys): power-controller@408 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x408 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(apcie_st_sys);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_apcie_st)&gt;, &lt;&amp;DIE_NODE(ps_ans2)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_apcie_st1_sys): power-controller@410 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x410 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(apcie_st1_sys);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_apcie_st_sys)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_apcie_gp_sys): power-controller@418 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x418 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(apcie_gp_sys);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_apcie_gpshr_sys)&gt;;</div><div class='add'>+		apple,always-on; /* Breaks things if shut down */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_apcie_ge_sys): power-controller@420 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x420 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(apcie_ge_sys);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_apcie_gpshr_sys)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_apcie_phy_sw): power-controller@428 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x428 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(apcie_phy_sw);</div><div class='add'>+		apple,always-on; /* macOS does not turn this off */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_sep): power-controller@c00 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0xc00 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(sep);</div><div class='add'>+		apple,always-on; /* Locked on */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* There is a dependency tree involved with these PDs,</div><div class='add'>+	 * but we do not express it here since the ISP driver</div><div class='add'>+	 * is supposed to sequence them in the right order anyway.</div><div class='add'>+	 *</div><div class='add'>+	 * This also works around spurious parent PD activation</div><div class='add'>+	 * on machines with ISP disabled (desktops), so we don't</div><div class='add'>+	 * have to enable/disable everything in the per-model DTs.</div><div class='add'>+	 */</div><div class='add'>+	DIE_NODE(ps_isp_cpu): power-controller@4000 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x4000 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(isp_cpu);</div><div class='add'>+		/* power-domains = &lt;&amp;DIE_NODE(ps_isp_sys)&gt;; */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_isp_fe): power-controller@4008 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x4008 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(isp_fe);</div><div class='add'>+		/* power-domains = &lt;&amp;DIE_NODE(ps_isp_sys)&gt;; */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_dprx): power-controller@4010 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x4010 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(dprx);</div><div class='add'>+		/* power-domains = &lt;&amp;DIE_NODE(ps_isp_sys)&gt;; */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_isp_vis): power-controller@4018 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x4018 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(isp_vis);</div><div class='add'>+		/* power-domains = &lt;&amp;DIE_NODE(ps_isp_fe)&gt;; */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_isp_be): power-controller@4020 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x4020 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(isp_be);</div><div class='add'>+		/* power-domains = &lt;&amp;DIE_NODE(ps_isp_fe)&gt;; */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_isp_raw): power-controller@4028 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x4028 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(isp_raw);</div><div class='add'>+		/* power-domains = &lt;&amp;DIE_NODE(ps_isp_fe)&gt;; */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_isp_clr): power-controller@4030 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x4030 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(isp_clr);</div><div class='add'>+		/* power-domains = &lt;&amp;DIE_NODE(ps_isp_be)&gt;; */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_venc_dma): power-controller@8000 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x8000 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(venc_dma);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_venc_sys)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_venc_pipe4): power-controller@8008 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x8008 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(venc_pipe4);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_venc_dma)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_venc_pipe5): power-controller@8010 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x8010 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(venc_pipe5);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_venc_dma)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_venc_me0): power-controller@8018 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x8018 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(venc_me0);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_venc_pipe5)&gt;, &lt;&amp;DIE_NODE(ps_venc_pipe4)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_venc_me1): power-controller@8020 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x8020 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(venc_me1);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_venc_me0)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_prores): power-controller@c000 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0xc000 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(prores);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afnc3_lw0)&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;DIE_NODE(pmgr_mini) {</div><div class='add'>+	DIE_NODE(ps_debug): power-controller@58 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x58 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(debug);</div><div class='add'>+		apple,always-on; /* Core AON device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_nub_spmi0): power-controller@60 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x60 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(nub_spmi0);</div><div class='add'>+		apple,always-on; /* Core AON device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_nub_spmi1): power-controller@68 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x68 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(nub_spmi1);</div><div class='add'>+		apple,always-on; /* Core AON device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_nub_aon): power-controller@70 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x70 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(nub_aon);</div><div class='add'>+		apple,always-on; /* Core AON device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_msg): power-controller@78 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x78 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(msg);</div><div class='add'>+		apple,always-on; /* Core AON device? */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_nub_gpio): power-controller@80 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(nub_gpio);</div><div class='add'>+		apple,always-on; /* Core AON device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_nub_fabric): power-controller@88 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x88 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(nub_fabric);</div><div class='add'>+		apple,always-on; /* Core AON device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc0_usb_aon): power-controller@90 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x90 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc0_usb_aon);</div><div class='add'>+		apple,always-on; /* Needs to stay on for dwc3 to work */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc1_usb_aon): power-controller@98 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x98 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc1_usb_aon);</div><div class='add'>+		apple,always-on; /* Needs to stay on for dwc3 to work */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc2_usb_aon): power-controller@a0 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0xa0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc2_usb_aon);</div><div class='add'>+		apple,always-on; /* Needs to stay on for dwc3 to work */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc3_usb_aon): power-controller@a8 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0xa8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc3_usb_aon);</div><div class='add'>+		apple,always-on; /* Needs to stay on for dwc3 to work */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_mtp_fabric): power-controller@b0 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0xb0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(mtp_fabric);</div><div class='add'>+		apple,always-on;</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_nub_fabric)&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_nub_sram): power-controller@b8 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0xb8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(nub_sram);</div><div class='add'>+		apple,always-on; /* Core AON device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_debug_switch): power-controller@c0 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0xc0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(debug_switch);</div><div class='add'>+		apple,always-on; /* Core AON device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc0_usb): power-controller@c8 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0xc8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc0_usb);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_atc0_common)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc1_usb): power-controller@d0 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0xd0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc1_usb);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_atc1_common)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc2_usb): power-controller@d8 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0xd8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc2_usb);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_atc2_common)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_atc3_usb): power-controller@e0 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0xe0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(atc3_usb);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_atc3_common)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+#if 0</div><div class='add'>+	/* MTP stuff is self-managed */</div><div class='add'>+	DIE_NODE(ps_mtp_gpio): power-controller@e8 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0xe8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(mtp_gpio);</div><div class='add'>+		apple,always-on; /* MTP always stays on */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_mtp_fabric)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_mtp_base): power-controller@f0 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0xf0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(mtp_base);</div><div class='add'>+		apple,always-on; /* MTP always stays on */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_mtp_fabric)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_mtp_periph): power-controller@f8 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0xf8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(mtp_periph);</div><div class='add'>+		apple,always-on; /* MTP always stays on */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_mtp_fabric)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_mtp_spi0): power-controller@100 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x100 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(mtp_spi0);</div><div class='add'>+		apple,always-on; /* MTP always stays on */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_mtp_fabric)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_mtp_i2cm0): power-controller@108 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x108 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(mtp_i2cm0);</div><div class='add'>+		apple,always-on; /* MTP always stays on */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_mtp_fabric)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_mtp_uart0): power-controller@110 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x110 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(mtp_uart0);</div><div class='add'>+		apple,always-on; /* MTP always stays on */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_mtp_fabric)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_mtp_cpu): power-controller@118 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x118 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(mtp_cpu);</div><div class='add'>+		apple,always-on; /* MTP always stays on */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_mtp_fabric)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_mtp_scm_fabric): power-controller@120 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x120 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(mtp_scm_fabric);</div><div class='add'>+		apple,always-on; /* MTP always stays on */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_mtp_periph)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_mtp_sram): power-controller@128 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x128 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(mtp_sram);</div><div class='add'>+		apple,always-on; /* MTP always stays on */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_mtp_scm_fabric)&gt;, &lt;&amp;DIE_NODE(ps_mtp_cpu)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_mtp_dma): power-controller@130 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x130 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(mtp_dma);</div><div class='add'>+		apple,always-on; /* MTP always stays on */</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_mtp_sram)&gt;;</div><div class='add'>+	};</div><div class='add'>+#endif</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;DIE_NODE(pmgr_gfx) {</div><div class='add'>+	DIE_NODE(ps_gpx): power-controller@0 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(gpx);</div><div class='add'>+		apple,min-state = &lt;4&gt;;</div><div class='add'>+		apple,always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_afr): power-controller@100 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x100 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(afr);</div><div class='add'>+		/* Apple Fabric, media stuff: this can power down */</div><div class='add'>+		apple,min-state = &lt;4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	DIE_NODE(ps_gfx): power-controller@108 {</div><div class='add'>+		compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x108 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = DIE_LABEL(gfx);</div><div class='add'>+		power-domains = &lt;&amp;DIE_NODE(ps_afr)&gt;, &lt;&amp;DIE_NODE(ps_gpx)&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t7000-6.dtsi b/arch/arm64/boot/dts/apple/t7000-6.dtsi<br/>new file mode 100644<br/>index 000000000000..7048d7383982<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t7000-6.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t7000-6.dtsi</a></div><div class='hunk'>@@ -0,0 +1,58 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPhone 6 / 6 Plus common device tree</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include "t7000.dtsi"</div><div class='add'>+#include "t7000-common.dtsi"</div><div class='add'>+#include "t7000-handheld.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	chassis-type = "handset";</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		button-home {</div><div class='add'>+			label = "Home Button";</div><div class='add'>+			gpios = &lt;&amp;pinctrl 32 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_HOMEPAGE&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-power {</div><div class='add'>+			label = "Power Button";</div><div class='add'>+			gpios = &lt;&amp;pinctrl 33 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-volup {</div><div class='add'>+			label = "Volume Up";</div><div class='add'>+			gpios = &lt;&amp;pinctrl 45 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-voldown {</div><div class='add'>+			label = "Volume Down";</div><div class='add'>+			gpios = &lt;&amp;pinctrl 46 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		switch-mute {</div><div class='add'>+			label = "Mute Switch";</div><div class='add'>+			gpios = &lt;&amp;pinctrl 131 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_MUTE&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;framebuffer0 {</div><div class='add'>+	power-domains = &lt;&amp;ps_disp0 &amp;ps_mipi_dsi&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;typhoon_opp06 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t7000-common.dtsi b/arch/arm64/boot/dts/apple/t7000-common.dtsi<br/>new file mode 100644<br/>index 000000000000..87146e6daae7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t7000-common.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t7000-common.dtsi</a></div><div class='hunk'>@@ -0,0 +1,36 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple TV HD, iPhone 6, iPhone 6 Plus, iPad mini 4, iPod touch 6</div><div class='add'>+ *</div><div class='add'>+ * This file contains parts common to all Apple A8 devices.</div><div class='add'>+ *</div><div class='add'>+ * target-type: J42d, J96, J97, N56, N61, N102</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2024, Nick Chan &lt;towinchenmi@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;serial0;</div><div class='add'>+		serial6 = &amp;serial6;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@800000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x8 0 0 0&gt;; /* To be filled by loader */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		/* To be filled by loader */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t7000-handheld.dtsi b/arch/arm64/boot/dts/apple/t7000-handheld.dtsi<br/>new file mode 100644<br/>index 000000000000..7b58aa648b53<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t7000-handheld.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t7000-handheld.dtsi</a></div><div class='hunk'>@@ -0,0 +1,31 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPhone 6, iPhone 6 Plus, iPad mini 4, iPod touch 6</div><div class='add'>+ *</div><div class='add'>+ * This file contains the parts common to handheld devices with t7000</div><div class='add'>+ *</div><div class='add'>+ * target-type: J96, J97, N56, N61, N102</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2024, Nick Chan &lt;towinchenmi@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0";</div><div class='add'>+</div><div class='add'>+		framebuffer0: framebuffer@0 {</div><div class='add'>+			compatible = "apple,simple-framebuffer", "simple-framebuffer";</div><div class='add'>+			reg = &lt;0 0 0 0&gt;; /* To be filled by loader */</div><div class='add'>+			/* Format properties will be added by loader */</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dwi_bl {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;serial0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t7000-j42d.dts b/arch/arm64/boot/dts/apple/t7000-j42d.dts<br/>new file mode 100644<br/>index 000000000000..2ec9e06cc63f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t7000-j42d.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t7000-j42d.dts</a></div><div class='hunk'>@@ -0,0 +1,36 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple TV HD, J42d, AppleTV5,3 (A1625)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t7000.dtsi"</div><div class='add'>+#include "t7000-common.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j42d", "apple,t7000", "apple,arm-platform";</div><div class='add'>+	model = "Apple TV HD";</div><div class='add'>+	chassis-type = "television";</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial6";</div><div class='add'>+</div><div class='add'>+		framebuffer0: framebuffer@0 {</div><div class='add'>+			compatible = "apple,simple-framebuffer", "simple-framebuffer";</div><div class='add'>+			reg = &lt;0 0 0 0&gt;; /* To be filled by loader */</div><div class='add'>+			power-domains = &lt;&amp;ps_disp0 &amp;ps_dp&gt;;</div><div class='add'>+			/* Format properties will be added by loader */</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;serial6 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;typhoon_opp06 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t7000-j96.dts b/arch/arm64/boot/dts/apple/t7000-j96.dts<br/>new file mode 100644<br/>index 000000000000..8a32a50cc2df<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t7000-j96.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t7000-j96.dts</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPad mini 4 (Wi-Fi), J96, iPad5,1 (A1538)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t7000-mini4.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j96", "apple,t7000", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPad mini 4 (Wi-Fi)";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t7000-j97.dts b/arch/arm64/boot/dts/apple/t7000-j97.dts<br/>new file mode 100644<br/>index 000000000000..ac7d501f88d2<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t7000-j97.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t7000-j97.dts</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPad mini 4 (Cellular), J97, iPad5,2 (A1550)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t7000-mini4.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j97", "apple,t7000", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPad mini 4 (Cellular)";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t7000-mini4.dtsi b/arch/arm64/boot/dts/apple/t7000-mini4.dtsi<br/>new file mode 100644<br/>index 000000000000..cc235c5a0c43<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t7000-mini4.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t7000-mini4.dtsi</a></div><div class='hunk'>@@ -0,0 +1,63 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPad mini 4 common device tree</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "t7000.dtsi"</div><div class='add'>+#include "t7000-common.dtsi"</div><div class='add'>+#include "t7000-handheld.dtsi"</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	chassis-type = "tablet";</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		button-home {</div><div class='add'>+			label = "Home Button";</div><div class='add'>+			gpios = &lt;&amp;pinctrl 32 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_HOMEPAGE&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-power {</div><div class='add'>+			label = "Power Button";</div><div class='add'>+			gpios = &lt;&amp;pinctrl 33 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-volup {</div><div class='add'>+			label = "Volume Up";</div><div class='add'>+			gpios = &lt;&amp;pinctrl 45 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-voldown {</div><div class='add'>+			label = "Volume Down";</div><div class='add'>+			gpios = &lt;&amp;pinctrl 46 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		switch-mute {</div><div class='add'>+			label = "Mute Switch";</div><div class='add'>+			gpios = &lt;&amp;pinctrl 36 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_MUTE&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;framebuffer0 {</div><div class='add'>+	power-domains = &lt;&amp;ps_disp0 &amp;ps_dp&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;typhoon_opp06 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;typhoon_opp07 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t7000-n102.dts b/arch/arm64/boot/dts/apple/t7000-n102.dts<br/>new file mode 100644<br/>index 000000000000..99eb8a2b8c73<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t7000-n102.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t7000-n102.dts</a></div><div class='hunk'>@@ -0,0 +1,52 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPod touch 6, N102, iPod7,1 (A1574)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t7000.dtsi"</div><div class='add'>+#include "t7000-common.dtsi"</div><div class='add'>+#include "t7000-handheld.dtsi"</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,n102", "apple,t7000", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPod touch 6";</div><div class='add'>+	chassis-type = "handset";</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		button-home {</div><div class='add'>+			label = "Home Button";</div><div class='add'>+			gpios = &lt;&amp;pinctrl 32 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_HOMEPAGE&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-power {</div><div class='add'>+			label = "Power Button";</div><div class='add'>+			gpios = &lt;&amp;pinctrl 33 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-voldown {</div><div class='add'>+			label = "Volume Down";</div><div class='add'>+			gpios = &lt;&amp;pinctrl 46 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-volup {</div><div class='add'>+			label = "Volume Up";</div><div class='add'>+			gpios = &lt;&amp;pinctrl 45 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;framebuffer0 {</div><div class='add'>+	power-domains = &lt;&amp;ps_disp0 &amp;ps_mipi_dsi&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t7000-n56.dts b/arch/arm64/boot/dts/apple/t7000-n56.dts<br/>new file mode 100644<br/>index 000000000000..2c358df14458<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t7000-n56.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t7000-n56.dts</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPhone 6 Plus, N56, iPhone7,2 (A1549/A1586/A1589)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t7000-6.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,n56", "apple,t7000", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPhone 6 Plus";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t7000-n61.dts b/arch/arm64/boot/dts/apple/t7000-n61.dts<br/>new file mode 100644<br/>index 000000000000..10b4ca8babf7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t7000-n61.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t7000-n61.dts</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPhone 6, N61, iPhone7,2 (A1549/A1586/A1589)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t7000-6.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,n61", "apple,t7000", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPhone 6";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t7000-pmgr.dtsi b/arch/arm64/boot/dts/apple/t7000-pmgr.dtsi<br/>new file mode 100644<br/>index 000000000000..5948fa7afffc<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t7000-pmgr.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t7000-pmgr.dtsi</a></div><div class='hunk'>@@ -0,0 +1,641 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * PMGR Power domains for the Apple T7000 "A8" SoC</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2024, Nick Chan &lt;towinchenmi@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+&amp;pmgr {</div><div class='add'>+	ps_cpu0: power-controller@20000 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20000 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "cpu0";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_cpu1: power-controller@20008 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20008 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "cpu1";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_cpm: power-controller@20040 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20040 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "cpm";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sio_p: power-controller@201f8 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x201f8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sio_p";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_lio: power-controller@20100 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20100 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "lio";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_iomux: power-controller@20108 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20108 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "iomux";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_aic: power-controller@20110 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20110 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "aic";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_debug: power-controller@20118 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20118 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "debug";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dwi: power-controller@20120 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20120 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dwi";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_gpio: power-controller@20128 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20128 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "gpio";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca0: power-controller@20130 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20130 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca1: power-controller@20138 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20138 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca1";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca2: power-controller@20140 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20140 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca2";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca3: power-controller@20148 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20148 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca3";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca4: power-controller@20150 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20150 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca4";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pwm0: power-controller@20158 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20158 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pwm0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c0: power-controller@20160 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20160 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c1: power-controller@20168 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20168 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c1";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c2: power-controller@20170 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20170 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c2";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c3: power-controller@20178 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20178 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c3";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi0: power-controller@20180 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20180 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi1: power-controller@20188 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20188 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi1";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi2: power-controller@20190 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20190 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi2";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi3: power-controller@20198 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20198 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi3";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart0: power-controller@201a0 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x201a0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart1: power-controller@201a8 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x201a8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart1";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart2: power-controller@201b0 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x201b0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart2";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart3: power-controller@201b8 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x201b8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart3";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart4: power-controller@201c0 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x201c0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart4";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart5: power-controller@201c8 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x201c8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart5";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart6: power-controller@201d0 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x201d0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart6";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart7: power-controller@201d8 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x201d8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart7";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart8: power-controller@201e0 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x201e0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart8";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_aes0: power-controller@201e8 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x201e8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "aes0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sio: power-controller@201f0 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x201f0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sio";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usb: power-controller@20248 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20248 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usb";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usbctrl: power-controller@20250 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20250 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usbctrl";</div><div class='add'>+		power-domains = &lt;&amp;ps_usb&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usb2host0: power-controller@20258 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20258 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usb2host0";</div><div class='add'>+		power-domains = &lt;&amp;ps_usbctrl&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usb2host1: power-controller@20268 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20268 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usb2host1";</div><div class='add'>+		power-domains = &lt;&amp;ps_usbctrl&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usb2host2: power-controller@20278 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20278 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usb2host2";</div><div class='add'>+		power-domains = &lt;&amp;ps_usbctrl&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_disp_busmux: power-controller@202a8 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x202a8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "disp_busmux";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_media: power-controller@202d8 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x202d8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "media";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_isp: power-controller@202d0 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x202d0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "isp";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_msr: power-controller@202e0 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x202e0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "msr";</div><div class='add'>+		power-domains = &lt;&amp;ps_media&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_jpg: power-controller@202e8 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x202e8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "jpg";</div><div class='add'>+		power-domains = &lt;&amp;ps_media&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_disp0: power-controller@202b0 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x202b0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "disp0";</div><div class='add'>+		power-domains = &lt;&amp;ps_disp_busmux&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_disp1: power-controller@202c8 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x202c8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "disp1";</div><div class='add'>+		power-domains = &lt;&amp;ps_disp_busmux&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pcie_ref: power-controller@20220 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20220 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pcie_ref";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_hsic0_phy: power-controller@20200 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20200 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "hsic0_phy";</div><div class='add'>+		power-domains = &lt;&amp;ps_usb2host1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_hsic1_phy: power-controller@20208 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20208 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "hsic1_phy";</div><div class='add'>+		power-domains = &lt;&amp;ps_usb2host2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_ispsens0: power-controller@20210 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20210 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "ispsens0";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_ispsens1: power-controller@20218 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20218 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "ispsens1";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mcc: power-controller@20230 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20230 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mcc";</div><div class='add'>+		apple,always-on; /* Memory cache controller */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mcu: power-controller@20238 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20238 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mcu";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_amp: power-controller@20240 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20240 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "amp";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usb2host0_ohci: power-controller@20260 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20260 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usb2host0_ohci";</div><div class='add'>+		power-domains = &lt;&amp;ps_usb2host0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usbotg: power-controller@20288 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20288 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usbotg";</div><div class='add'>+		power-domains = &lt;&amp;ps_usbctrl&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_smx: power-controller@20290 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20290 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "smx";</div><div class='add'>+		apple,always-on; /* Apple Fabric, critical block */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sf: power-controller@20298 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20298 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sf";</div><div class='add'>+		apple,always-on; /* Apple Fabric, critical block */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_cp: power-controller@202a0 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x202a0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "cp";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mipi_dsi: power-controller@202b8 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x202b8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mipi_dsi";</div><div class='add'>+		power-domains = &lt;&amp;ps_disp_busmux&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dp: power-controller@202c0 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x202c0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dp";</div><div class='add'>+		power-domains = &lt;&amp;ps_disp0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_vdec: power-controller@202f0 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x202f0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "vdec";</div><div class='add'>+		power-domains = &lt;&amp;ps_media&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_ans: power-controller@20318 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20318 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "ans";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc: power-controller@20300 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20300 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc";</div><div class='add'>+		power-domains = &lt;&amp;ps_media&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pcie: power-controller@20308 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20308 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pcie";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pcie_aux: power-controller@20310 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20310 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pcie_aux";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_gfx: power-controller@20320 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20320 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "gfx";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sep: power-controller@20400 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20400 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sep";</div><div class='add'>+		apple,always-on; /* Locked on */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc_pipe: power-controller@21000 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x21000 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc_pipe";</div><div class='add'>+		power-domains = &lt;&amp;ps_venc&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc_me0: power-controller@21008 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x21008 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc_me0";</div><div class='add'>+		power-domains = &lt;&amp;ps_venc&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc_me1: power-controller@21010 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x21010 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc_me1";</div><div class='add'>+		power-domains = &lt;&amp;ps_venc&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t7000.dtsi b/arch/arm64/boot/dts/apple/t7000.dtsi<br/>new file mode 100644<br/>index 000000000000..0342455d3444<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t7000.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t7000.dtsi</a></div><div class='hunk'>@@ -0,0 +1,287 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple T7000 "A8" SoC</div><div class='add'>+ *</div><div class='add'>+ * Other names: H7P, "Fiji"</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ * Based on Asahi Linux's M1 (t8103.dtsi) and Corellium's A10 efforts.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/apple-aic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/apple.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	clkref: clock-ref {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+		clock-output-names = "clkref";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			compatible = "apple,typhoon";</div><div class='add'>+			reg = &lt;0x0 0x0&gt;;</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled in by loader */</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;typhoon_opp&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache&gt;;</div><div class='add'>+			i-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@1 {</div><div class='add'>+			compatible = "apple,typhoon";</div><div class='add'>+			reg = &lt;0x0 0x1&gt;;</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled in by loader */</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;typhoon_opp&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache&gt;;</div><div class='add'>+			i-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_cache: l2-cache {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x100000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	typhoon_opp: opp-table {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		opp01 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;300000000&gt;;</div><div class='add'>+			opp-level = &lt;1&gt;;</div><div class='add'>+			clock-latency-ns = &lt;300&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp02 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;396000000&gt;;</div><div class='add'>+			opp-level = &lt;2&gt;;</div><div class='add'>+			clock-latency-ns = &lt;50000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp03 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;600000000&gt;;</div><div class='add'>+			opp-level = &lt;3&gt;;</div><div class='add'>+			clock-latency-ns = &lt;29000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp04 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;840000000&gt;;</div><div class='add'>+			opp-level = &lt;4&gt;;</div><div class='add'>+			clock-latency-ns = &lt;29000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp05 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1128000000&gt;;</div><div class='add'>+			opp-level = &lt;5&gt;;</div><div class='add'>+			clock-latency-ns = &lt;36000&gt;;</div><div class='add'>+		};</div><div class='add'>+		typhoon_opp06: opp06 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1392000000&gt;;</div><div class='add'>+			opp-level = &lt;6&gt;;</div><div class='add'>+			clock-latency-ns = &lt;42000&gt;;</div><div class='add'>+			status = "disabled"; /* Not available on N102 */</div><div class='add'>+		};</div><div class='add'>+		typhoon_opp07: opp07 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1512000000&gt;;</div><div class='add'>+			opp-level = &lt;7&gt;;</div><div class='add'>+			clock-latency-ns = &lt;49000&gt;;</div><div class='add'>+			status = "disabled"; /* J96 and J97 only */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		nonposted-mmio;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		cpufreq: performance-controller@202220000 {</div><div class='add'>+			compatible = "apple,t7000-cluster-cpufreq", "apple,s5l8960x-cluster-cpufreq";</div><div class='add'>+			reg = &lt;0x2 0x02220000 0 0x1000&gt;;</div><div class='add'>+			#performance-domain-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		serial0: serial@20a0c0000 {</div><div class='add'>+			compatible = "apple,s5l-uart";</div><div class='add'>+			reg = &lt;0x2 0x0a0c0000 0x0 0x4000&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 158 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			/* Use the bootloader-enabled clocks for now. */</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;, &lt;&amp;clkref&gt;;</div><div class='add'>+			clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+			power-domains = &lt;&amp;ps_uart0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		serial6: serial@20a0d8000 {</div><div class='add'>+			compatible = "apple,s5l-uart";</div><div class='add'>+			reg = &lt;0x2 0x0a0d8000 0x0 0x4000&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 164 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			/* Use the bootloader-enabled clocks for now. */</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;, &lt;&amp;clkref&gt;;</div><div class='add'>+			clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+			power-domains = &lt;&amp;ps_uart6&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c0: i2c@20a110000 {</div><div class='add'>+			compatible = "apple,t7000-i2c", "apple,i2c";</div><div class='add'>+			reg = &lt;0x2 0x0a110000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 174 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c0_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			power-domains = &lt;&amp;ps_i2c0&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c1: i2c@20a111000 {</div><div class='add'>+			compatible = "apple,t7000-i2c", "apple,i2c";</div><div class='add'>+			reg = &lt;0x2 0x0a111000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 175 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c1_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			power-domains = &lt;&amp;ps_i2c1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c2: i2c@20a112000 {</div><div class='add'>+			compatible = "apple,t7000-i2c", "apple,i2c";</div><div class='add'>+			reg = &lt;0x2 0x0a112000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 176 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c2_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			power-domains = &lt;&amp;ps_i2c2&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c3: i2c@20a113000 {</div><div class='add'>+			compatible = "apple,t7000-i2c", "apple,i2c";</div><div class='add'>+			reg = &lt;0x2 0x0a113000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 177 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c3_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			power-domains = &lt;&amp;ps_i2c3&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmgr: power-management@20e000000 {</div><div class='add'>+			compatible = "apple,t7000-pmgr", "apple,pmgr", "syscon", "simple-mfd";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			reg = &lt;0x2 0xe000000 0 0x24000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wdt: watchdog@20e027000 {</div><div class='add'>+			compatible = "apple,t7000-wdt", "apple,wdt";</div><div class='add'>+			reg = &lt;0x2 0x0e027000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 4 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aic: interrupt-controller@20e100000 {</div><div class='add'>+			compatible = "apple,t7000-aic", "apple,aic";</div><div class='add'>+			reg = &lt;0x2 0x0e100000 0x0 0x100000&gt;;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			power-domains = &lt;&amp;ps_aic&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dwi_bl: backlight@20e200010 {</div><div class='add'>+			compatible = "apple,t7000-dwi-bl", "apple,dwi-bl";</div><div class='add'>+			reg = &lt;0x2 0x0e200010 0x0 0x8&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_dwi&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl: pinctrl@20e300000 {</div><div class='add'>+			compatible = "apple,t7000-pinctrl", "apple,pinctrl";</div><div class='add'>+			reg = &lt;0x2 0x0e300000 0x0 0x100000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_gpio&gt;;</div><div class='add'>+</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;pinctrl 0 0 208&gt;;</div><div class='add'>+			apple,npins = &lt;208&gt;;</div><div class='add'>+</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 62 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 63 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 64 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 65 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 66 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 67 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 68 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			i2c0_pins: i2c0-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(97, 1)&gt;,</div><div class='add'>+					 &lt;APPLE_PINMUX(96, 1)&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c1_pins: i2c1-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(139, 1)&gt;,</div><div class='add'>+					 &lt;APPLE_PINMUX(138, 1)&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c2_pins: i2c2-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(65, 1)&gt;,</div><div class='add'>+					 &lt;APPLE_PINMUX(64, 1)&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c3_pins: i2c3-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(87, 1)&gt;,</div><div class='add'>+					 &lt;APPLE_PINMUX(86, 1)&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupt-names = "phys", "virt";</div><div class='add'>+		/* Note that A8 doesn't actually have a hypervisor (EL2 is not implemented). */</div><div class='add'>+		interrupts = &lt;AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include "t7000-pmgr.dtsi"</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t7001-air2.dtsi b/arch/arm64/boot/dts/apple/t7001-air2.dtsi<br/>new file mode 100644<br/>index 000000000000..e4ec8c1977de<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t7001-air2.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t7001-air2.dtsi</a></div><div class='hunk'>@@ -0,0 +1,75 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPad Air 2 common device tree</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "t7001.dtsi"</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	chassis-type = "tablet";</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		stdout-path = "serial0";</div><div class='add'>+</div><div class='add'>+		framebuffer0: framebuffer@0 {</div><div class='add'>+			compatible = "apple,simple-framebuffer", "simple-framebuffer";</div><div class='add'>+			reg = &lt;0 0 0 0&gt;; /* To be filled by loader */</div><div class='add'>+			power-domains = &lt;&amp;ps_disp0 &amp;ps_dp&gt;;</div><div class='add'>+			/* Format properties will be added by loader */</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		button-home {</div><div class='add'>+			label = "Home Button";</div><div class='add'>+			gpios = &lt;&amp;pinctrl 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_HOMEPAGE&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-power {</div><div class='add'>+			label = "Power Button";</div><div class='add'>+			gpios = &lt;&amp;pinctrl 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-volup {</div><div class='add'>+			label = "Volume Up";</div><div class='add'>+			gpios = &lt;&amp;pinctrl 92 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-voldown {</div><div class='add'>+			label = "Volume Down";</div><div class='add'>+			gpios = &lt;&amp;pinctrl 93 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@800000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x8 0 0 0&gt;; /* To be filled by loader */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		/* To be filled by loader */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;serial0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t7001-j81.dts b/arch/arm64/boot/dts/apple/t7001-j81.dts<br/>new file mode 100644<br/>index 000000000000..ca90dc0c872c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t7001-j81.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t7001-j81.dts</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPad Air 2 (Wi-Fi), J81, iPad5,3 (A1566)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t7001-air2.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j81", "apple,t7001", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPad Air 2 (Wi-Fi)";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t7001-j82.dts b/arch/arm64/boot/dts/apple/t7001-j82.dts<br/>new file mode 100644<br/>index 000000000000..d9fd16f48db7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t7001-j82.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t7001-j82.dts</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPad Air 2 (Cellular), J82, iPad5,4 (A1567)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t7001-air2.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j82", "apple,t7001", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPad Air 2 (Cellular)";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t7001-pmgr.dtsi b/arch/arm64/boot/dts/apple/t7001-pmgr.dtsi<br/>new file mode 100644<br/>index 000000000000..7321cfdcd189<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t7001-pmgr.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t7001-pmgr.dtsi</a></div><div class='hunk'>@@ -0,0 +1,650 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * PMGR Power domains for the Apple T7001 "A8X" SoC</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2024, Nick Chan &lt;towinchenmi@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;pmgr {</div><div class='add'>+	ps_cpu0: power-controller@20000 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20000 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "cpu0";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_cpu1: power-controller@20008 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20008 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "cpu1";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_cpu2: power-controller@20010 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20010 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "cpu2";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_cpm: power-controller@20040 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20040 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "cpm";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sio_p: power-controller@201f8 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x201f8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sio_p";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_lio: power-controller@20100 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20100 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "lio";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_iomux: power-controller@20108 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20108 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "iomux";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_aic: power-controller@20110 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20110 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "aic";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_debug: power-controller@20118 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20118 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "debug";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dwi: power-controller@20120 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20120 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dwi";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_gpio: power-controller@20128 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20128 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "gpio";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca0: power-controller@20130 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20130 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca1: power-controller@20138 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20138 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca1";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca2: power-controller@20140 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20140 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca2";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca3: power-controller@20148 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20148 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca3";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca4: power-controller@20150 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20150 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca4";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pwm0: power-controller@20158 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20158 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pwm0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c0: power-controller@20160 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20160 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c1: power-controller@20168 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20168 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c1";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c2: power-controller@20170 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20170 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c2";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c3: power-controller@20178 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20178 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c3";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi0: power-controller@20180 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20180 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi1: power-controller@20188 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20188 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi1";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi2: power-controller@20190 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20190 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi2";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi3: power-controller@20198 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20198 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi3";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart0: power-controller@201a0 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x201a0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart1: power-controller@201a8 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x201a8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart1";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart2: power-controller@201b0 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x201b0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart2";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart3: power-controller@201b8 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x201b8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart3";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart4: power-controller@201c0 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x201c0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart4";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart5: power-controller@201c8 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x201c8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart5";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart6: power-controller@201d0 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x201d0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart6";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart7: power-controller@201d8 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x201d8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart7";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart8: power-controller@201e0 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x201e0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart8";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_aes0: power-controller@201e8 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x201e8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "aes0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sio: power-controller@201f0 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x201f0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sio";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usb: power-controller@20248 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20248 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usb";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usbctrl: power-controller@20250 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20250 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usbctrl";</div><div class='add'>+		power-domains = &lt;&amp;ps_usb&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usb2host0: power-controller@20258 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20258 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usb2host0";</div><div class='add'>+		power-domains = &lt;&amp;ps_usbctrl&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usb2host1: power-controller@20268 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20268 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usb2host1";</div><div class='add'>+		power-domains = &lt;&amp;ps_usbctrl&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usb2host2: power-controller@20278 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20278 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usb2host2";</div><div class='add'>+		power-domains = &lt;&amp;ps_usbctrl&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_disp_busmux: power-controller@202a8 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x202a8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "disp_busmux";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_disp1_busmux: power-controller@202c0 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x202c0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "disp1_busmux";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_media: power-controller@202d8 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x202d8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "media";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_isp: power-controller@202d0 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x202d0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "isp";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_msr: power-controller@202e0 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x202e0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "msr";</div><div class='add'>+		power-domains = &lt;&amp;ps_media&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_jpg: power-controller@202e8 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x202e8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "jpg";</div><div class='add'>+		power-domains = &lt;&amp;ps_media&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_disp0: power-controller@202b0 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x202b0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "disp0";</div><div class='add'>+		power-domains = &lt;&amp;ps_disp_busmux&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_disp1: power-controller@202c8 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x202c8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "disp1";</div><div class='add'>+		power-domains = &lt;&amp;ps_disp1_busmux&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pcie_ref: power-controller@20220 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20220 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pcie_ref";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_hsic0_phy: power-controller@20200 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20200 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "hsic0_phy";</div><div class='add'>+		power-domains = &lt;&amp;ps_usb2host1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_hsic1_phy: power-controller@20208 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20208 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "hsic1_phy";</div><div class='add'>+		power-domains = &lt;&amp;ps_usb2host2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_ispsens0: power-controller@20210 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20210 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "ispsens0";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_ispsens1: power-controller@20218 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20218 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "ispsens1";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mcc: power-controller@20230 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20230 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mcc";</div><div class='add'>+		apple,always-on; /* Memory cache controller */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mcu: power-controller@20238 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20238 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mcu";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_amp: power-controller@20240 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20240 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "amp";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usb2host0_ohci: power-controller@20260 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20260 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usb2host0_ohci";</div><div class='add'>+		power-domains = &lt;&amp;ps_usb2host0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usbotg: power-controller@20288 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20288 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usbotg";</div><div class='add'>+		power-domains = &lt;&amp;ps_usbctrl&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_smx: power-controller@20290 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20290 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "smx";</div><div class='add'>+		apple,always-on; /* Apple fabric, critical block */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sf: power-controller@20298 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20298 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sf";</div><div class='add'>+		apple,always-on; /* Apple fabric, critical block */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_cp: power-controller@202a0 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x202a0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "cp";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dp: power-controller@202b8 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x202b8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dp";</div><div class='add'>+		power-domains = &lt;&amp;ps_disp0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_vdec: power-controller@202f0 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x202f0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "vdec";</div><div class='add'>+		power-domains = &lt;&amp;ps_media&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_ans: power-controller@20318 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20318 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "ans";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc: power-controller@20300 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20300 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc";</div><div class='add'>+		power-domains = &lt;&amp;ps_media&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pcie: power-controller@20308 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20308 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pcie";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pcie_aux: power-controller@20310 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20310 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pcie_aux";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_gfx: power-controller@20320 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20320 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "gfx";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sep: power-controller@20400 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x20400 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sep";</div><div class='add'>+		apple,always-on; /* Locked on */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc_pipe: power-controller@21000 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x21000 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc_pipe";</div><div class='add'>+		power-domains = &lt;&amp;ps_venc&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc_me0: power-controller@21008 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x21008 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc_me0";</div><div class='add'>+		power-domains = &lt;&amp;ps_venc&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc_me1: power-controller@21010 {</div><div class='add'>+		compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x21010 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc_me1";</div><div class='add'>+		power-domains = &lt;&amp;ps_venc&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t7001.dtsi b/arch/arm64/boot/dts/apple/t7001.dtsi<br/>new file mode 100644<br/>index 000000000000..e1afb0542369<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t7001.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t7001.dtsi</a></div><div class='hunk'>@@ -0,0 +1,280 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple T7001 "A8X" SoC</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ * Based on Asahi Linux's M1 (t8103.dtsi) and Corellium's A10 efforts.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/apple-aic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/apple.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;serial0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clkref: clock-ref {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+		clock-output-names = "clkref";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			compatible = "apple,typhoon";</div><div class='add'>+			reg = &lt;0x0 0x0&gt;;</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled in by loader */</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;typhoon_opp&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache&gt;;</div><div class='add'>+			i-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@1 {</div><div class='add'>+			compatible = "apple,typhoon";</div><div class='add'>+			reg = &lt;0x0 0x1&gt;;</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled in by loader */</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;typhoon_opp&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache&gt;;</div><div class='add'>+			i-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@2 {</div><div class='add'>+			compatible = "apple,typhoon";</div><div class='add'>+			reg = &lt;0x0 0x2&gt;;</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;typhoon_opp&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache&gt;;</div><div class='add'>+			i-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_cache: l2-cache {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x200000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	typhoon_opp: opp-table {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		opp01 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;300000000&gt;;</div><div class='add'>+			opp-level = &lt;1&gt;;</div><div class='add'>+			clock-latency-ns = &lt;300&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp02 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;396000000&gt;;</div><div class='add'>+			opp-level = &lt;2&gt;;</div><div class='add'>+			clock-latency-ns = &lt;49000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp03 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;600000000&gt;;</div><div class='add'>+			opp-level = &lt;3&gt;;</div><div class='add'>+			clock-latency-ns = &lt;31000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp04 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;840000000&gt;;</div><div class='add'>+			opp-level = &lt;4&gt;;</div><div class='add'>+			clock-latency-ns = &lt;32000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp05 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1128000000&gt;;</div><div class='add'>+			opp-level = &lt;5&gt;;</div><div class='add'>+			clock-latency-ns = &lt;32000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp06 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1392000000&gt;;</div><div class='add'>+			opp-level = &lt;6&gt;;</div><div class='add'>+			clock-latency-ns = &lt;37000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp07 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1512000000&gt;;</div><div class='add'>+			opp-level = &lt;7&gt;;</div><div class='add'>+			clock-latency-ns = &lt;41000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		nonposted-mmio;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		cpufreq: performance-controller@202220000 {</div><div class='add'>+			compatible = "apple,t7000-cluster-cpufreq", "apple,s5l8960x-cluster-cpufreq";</div><div class='add'>+			reg = &lt;0x2 0x02220000 0 0x1000&gt;;</div><div class='add'>+			#performance-domain-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		serial0: serial@20a0c0000 {</div><div class='add'>+			compatible = "apple,s5l-uart";</div><div class='add'>+			reg = &lt;0x2 0x0a0c0000 0x0 0x4000&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 158 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			/* Use the bootloader-enabled clocks for now. */</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;, &lt;&amp;clkref&gt;;</div><div class='add'>+			clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+			power-domains = &lt;&amp;ps_uart0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c0: i2c@20a110000 {</div><div class='add'>+			compatible = "apple,t7000-i2c", "apple,i2c";</div><div class='add'>+			reg = &lt;0x2 0x0a110000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 174 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c0_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			power-domains = &lt;&amp;ps_i2c0&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c1: i2c@20a111000 {</div><div class='add'>+			compatible = "apple,t7000-i2c", "apple,i2c";</div><div class='add'>+			reg = &lt;0x2 0x0a111000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 175 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c1_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			power-domains = &lt;&amp;ps_i2c1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c2: i2c@20a112000 {</div><div class='add'>+			compatible = "apple,t7000-i2c", "apple,i2c";</div><div class='add'>+			reg = &lt;0x2 0x0a112000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 176 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c2_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			power-domains = &lt;&amp;ps_i2c2&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c3: i2c@20a113000 {</div><div class='add'>+			compatible = "apple,t7000-i2c", "apple,i2c";</div><div class='add'>+			reg = &lt;0x2 0x0a113000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 177 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c3_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			power-domains = &lt;&amp;ps_i2c3&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmgr: power-management@20e000000 {</div><div class='add'>+			compatible = "apple,t7000-pmgr", "apple,pmgr", "syscon", "simple-mfd";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			reg = &lt;0x2 0xe000000 0 0x24000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wdt: watchdog@20e027000 {</div><div class='add'>+			compatible = "apple,t7000-wdt", "apple,wdt";</div><div class='add'>+			reg = &lt;0x2 0x0e027000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 4 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aic: interrupt-controller@20e100000 {</div><div class='add'>+			compatible = "apple,t7000-aic", "apple,aic";</div><div class='add'>+			reg = &lt;0x2 0x0e100000 0x0 0x100000&gt;;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			power-domains = &lt;&amp;ps_aic&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl: pinctrl@20e300000 {</div><div class='add'>+			compatible = "apple,t7000-pinctrl", "apple,pinctrl";</div><div class='add'>+			reg = &lt;0x2 0x0e300000 0x0 0x100000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_gpio&gt;;</div><div class='add'>+</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;pinctrl 0 0 184&gt;;</div><div class='add'>+			apple,npins = &lt;184&gt;;</div><div class='add'>+</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 62 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 63 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 64 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 65 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 66 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 67 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 68 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			i2c0_pins: i2c0-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(38, 1)&gt;,</div><div class='add'>+					 &lt;APPLE_PINMUX(37, 1)&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c1_pins: i2c1-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(66, 1)&gt;,</div><div class='add'>+					 &lt;APPLE_PINMUX(65, 1)&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c2_pins: i2c2-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(133, 1)&gt;,</div><div class='add'>+					 &lt;APPLE_PINMUX(132, 1)&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c3_pins: i2c3-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(135, 1)&gt;,</div><div class='add'>+					 &lt;APPLE_PINMUX(134, 1)&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupt-names = "phys", "virt";</div><div class='add'>+		/* Note that A8X doesn't actually have a hypervisor (EL2 is not implemented). */</div><div class='add'>+		interrupts = &lt;AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include "t7001-pmgr.dtsi"</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8010-7.dtsi b/arch/arm64/boot/dts/apple/t8010-7.dtsi<br/>new file mode 100644<br/>index 000000000000..1913b7b2c1fe<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8010-7.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8010-7.dtsi</a></div><div class='hunk'>@@ -0,0 +1,55 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPhone 7 / 7 Plus common device tree</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "t8010.dtsi"</div><div class='add'>+#include "t8010-common.dtsi"</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	chassis-type = "handset";</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		button-power {</div><div class='add'>+			label = "Power Button";</div><div class='add'>+			gpios = &lt;&amp;pinctrl_ap 179 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-voldown {</div><div class='add'>+			label = "Volume Down";</div><div class='add'>+			gpios = &lt;&amp;pinctrl_ap 180 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-volup {</div><div class='add'>+			label = "Volume Up";</div><div class='add'>+			gpios = &lt;&amp;pinctrl_ap 23 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		switch-mute {</div><div class='add'>+			label = "Mute Switch";</div><div class='add'>+			gpios = &lt;&amp;pinctrl_ap 86 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_MUTE&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;framebuffer0 {</div><div class='add'>+	power-domains = &lt;&amp;ps_disp0_fe &amp;ps_disp0_be &amp;ps_mipi_dsi&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hurricane_opp09 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hurricane_opp10 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8010-common.dtsi b/arch/arm64/boot/dts/apple/t8010-common.dtsi<br/>new file mode 100644<br/>index 000000000000..44dc968638b1<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8010-common.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8010-common.dtsi</a></div><div class='hunk'>@@ -0,0 +1,52 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0 OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPhone 7, iPhone 7 Plus, iPad 6, iPad 7, iPod touch 7</div><div class='add'>+ *</div><div class='add'>+ * This file contains parts common to all Apple A10 devices.</div><div class='add'>+ *</div><div class='add'>+ * target-type: D10, D11, D101, D111, J71b, J72b, J171, J172, N112</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2024, Nick Chan &lt;towinchenmi@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;serial0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		stdout-path = "serial0";</div><div class='add'>+</div><div class='add'>+		framebuffer0: framebuffer@0 {</div><div class='add'>+			compatible = "apple,simple-framebuffer", "simple-framebuffer";</div><div class='add'>+			reg = &lt;0 0 0 0&gt;; /* To be filled by loader */</div><div class='add'>+			/* Format properties will be added by loader */</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@800000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x8 0 0 0&gt;; /* To be filled by loader */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		/* To be filled by loader */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dwi_bl {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;serial0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8010-d10.dts b/arch/arm64/boot/dts/apple/t8010-d10.dts<br/>new file mode 100644<br/>index 000000000000..39cdd12db6bf<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8010-d10.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8010-d10.dts</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPhone 7 (Qualcomm), D10, iPhone9,1 (A1660/A1778/A1779/A1780)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t8010-7.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,d10", "apple,t8010", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPhone 7 (Qualcomm)";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8010-d101.dts b/arch/arm64/boot/dts/apple/t8010-d101.dts<br/>new file mode 100644<br/>index 000000000000..6a9f0856f930<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8010-d101.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8010-d101.dts</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPhone 7 (Intel), D101, iPhone9,3 (A1660/A1778/A1779/A1780)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t8010-7.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,d101", "apple,t8010", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPhone 7 (Intel)";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8010-d11.dts b/arch/arm64/boot/dts/apple/t8010-d11.dts<br/>new file mode 100644<br/>index 000000000000..57e41c2cfbe2<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8010-d11.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8010-d11.dts</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPhone 7 Plus (Qualcomm), D11, iPhone9,2 (A1661/A1784/A1785/A1786)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t8010-7.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,d11", "apple,t8010", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPhone 7 Plus (Qualcomm)";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8010-d111.dts b/arch/arm64/boot/dts/apple/t8010-d111.dts<br/>new file mode 100644<br/>index 000000000000..37e395a48c1d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8010-d111.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8010-d111.dts</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPhone 7 Plus (Intel), D111, iPhone9,4 (A1661/A1784/A1785/A1786)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t8010-7.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,d111", "apple,t8010", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPhone 7 Plus (Intel)";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8010-ipad6.dtsi b/arch/arm64/boot/dts/apple/t8010-ipad6.dtsi<br/>new file mode 100644<br/>index 000000000000..1e46e4a3a7f4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8010-ipad6.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8010-ipad6.dtsi</a></div><div class='hunk'>@@ -0,0 +1,56 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPad 6 common device tree</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "t8010.dtsi"</div><div class='add'>+#include "t8010-common.dtsi"</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	chassis-type = "tablet";</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		button-home {</div><div class='add'>+			label = "Home Button";</div><div class='add'>+			gpios = &lt;&amp;pinctrl_ap 180 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_HOMEPAGE&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-power {</div><div class='add'>+			label = "Power Button";</div><div class='add'>+			gpios = &lt;&amp;pinctrl_ap 179 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-voldown {</div><div class='add'>+			label = "Volume Down";</div><div class='add'>+			gpios = &lt;&amp;pinctrl_ap 89 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-volup {</div><div class='add'>+			label = "Volume Up";</div><div class='add'>+			gpios = &lt;&amp;pinctrl_ap 90 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;framebuffer0 {</div><div class='add'>+	power-domains = &lt;&amp;ps_disp0_fe &amp;ps_disp0_be &amp;ps_dp&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hurricane_opp09 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hurricane_opp10 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8010-ipad7.dtsi b/arch/arm64/boot/dts/apple/t8010-ipad7.dtsi<br/>new file mode 100644<br/>index 000000000000..bd0e9c0b5696<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8010-ipad7.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8010-ipad7.dtsi</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPad 7 common device tree</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * The iPad 7 seems to be only an iteration over the iPad 6 with some</div><div class='add'>+ * small changes, like the a bigger screen and 1 GiB of RAM more, hence</div><div class='add'>+ * there is little to no differentiation between these 2 generations for</div><div class='add'>+ * now.</div><div class='add'>+ */</div><div class='add'>+#include "t8010-ipad6.dtsi"</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8010-j171.dts b/arch/arm64/boot/dts/apple/t8010-j171.dts<br/>new file mode 100644<br/>index 000000000000..6751bf3a4afd<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8010-j171.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8010-j171.dts</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPad 7 (Wi-Fi), J171, iPad7,11 (A2197)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t8010-ipad7.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j171", "apple,t8010", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPad 7 (Wi-Fi)";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8010-j172.dts b/arch/arm64/boot/dts/apple/t8010-j172.dts<br/>new file mode 100644<br/>index 000000000000..51aaa950acd9<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8010-j172.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8010-j172.dts</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPad 7 (Cellular), J172, iPad7,12 (A2198/A2200)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t8010-ipad7.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j172", "apple,t8010", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPad 7 (Cellular)";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8010-j71b.dts b/arch/arm64/boot/dts/apple/t8010-j71b.dts<br/>new file mode 100644<br/>index 000000000000..534eb8413e08<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8010-j71b.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8010-j71b.dts</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPad 6 (Wi-Fi), J71b, iPad7,5 (A1893)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t8010-ipad6.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j71b", "apple,t8010", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPad 6 (Wi-Fi)";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8010-j72b.dts b/arch/arm64/boot/dts/apple/t8010-j72b.dts<br/>new file mode 100644<br/>index 000000000000..264924e41f42<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8010-j72b.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8010-j72b.dts</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPad 6 (Cellular), J72b, iPad7,6 (A1954)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t8010-ipad6.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j72b", "apple,t8010", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPad 6 (Cellular)";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8010-n112.dts b/arch/arm64/boot/dts/apple/t8010-n112.dts<br/>new file mode 100644<br/>index 000000000000..48fdbedf74da<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8010-n112.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8010-n112.dts</a></div><div class='hunk'>@@ -0,0 +1,51 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPod touch 7, N112, iPod9,1 (A2178)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t8010.dtsi"</div><div class='add'>+#include "t8010-common.dtsi"</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,n112", "apple,t8010", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPod touch 7";</div><div class='add'>+	chassis-type = "handset";</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		button-home {</div><div class='add'>+			label = "Home Button";</div><div class='add'>+			gpios = &lt;&amp;pinctrl_ap 86 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_HOMEPAGE&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-power {</div><div class='add'>+			label = "Power Button";</div><div class='add'>+			gpios = &lt;&amp;pinctrl_ap 179 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-voldown {</div><div class='add'>+			label = "Volume Down";</div><div class='add'>+			gpios = &lt;&amp;pinctrl_ap 180 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-volup {</div><div class='add'>+			label = "Volume Up";</div><div class='add'>+			gpios = &lt;&amp;pinctrl_ap 23 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;framebuffer0 {</div><div class='add'>+	power-domains = &lt;&amp;ps_disp0_fe &amp;ps_disp0_be &amp;ps_mipi_dsi&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8010-pmgr.dtsi b/arch/arm64/boot/dts/apple/t8010-pmgr.dtsi<br/>new file mode 100644<br/>index 000000000000..6d451088616a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8010-pmgr.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8010-pmgr.dtsi</a></div><div class='hunk'>@@ -0,0 +1,772 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * PMGR Power domains for the Apple T8010 "A10" SoC</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2024 Nick Chan &lt;towinchenmi@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;pmgr {</div><div class='add'>+	ps_cpu0: power-controller@80000 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80000 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "cpu0";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_cpu1: power-controller@80008 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80008 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "cpu1";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_cpm: power-controller@80040 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80040 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "cpm";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sio_busif: power-controller@80160 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80160 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sio_busif";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sio_p: power-controller@80168 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80168 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sio_p";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_busif&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sbr: power-controller@80100 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80100 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sbr";</div><div class='add'>+		apple,always-on; /* Apple fabric, critical block */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_aic: power-controller@80108 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80108 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "aic";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dwi: power-controller@80110 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80110 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dwi";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_gpio: power-controller@80118 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80118 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "gpio";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pms: power-controller@80120 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80120 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pms";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pcie_ref: power-controller@80148 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80148 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pcie_ref";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_socuvd: power-controller@80150 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80150 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "socuvd";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca0: power-controller@80178 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80178 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca1: power-controller@80180 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80180 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca1";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca2: power-controller@80188 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80188 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca2";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca3: power-controller@80190 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80190 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca3";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca4: power-controller@80198 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80198 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca4";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pwm0: power-controller@801a0 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801a0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pwm0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c0: power-controller@801a8 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801a8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c1: power-controller@801b0 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801b0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c1";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c2: power-controller@801b8 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801b8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c2";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c3: power-controller@801c0 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801c0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c3";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi0: power-controller@801c8 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801c8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi1: power-controller@801d0 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801d0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi1";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi2: power-controller@801d8 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801d8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi2";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi3: power-controller@801e0 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801e0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi3";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart0: power-controller@801e8 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801e8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart1: power-controller@801f0 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801f0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart1";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart2: power-controller@801f8 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801f8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart2";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sio: power-controller@80170 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80170 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sio";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_hsic0_phy: power-controller@80128 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80128 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "hsic0_phy";</div><div class='add'>+		power-domains = &lt;&amp;ps_usb2host1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_isp_sens0: power-controller@80130 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80130 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "isp_sens0";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_isp_sens1: power-controller@80138 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80138 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "isp_sens1";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_isp_sens2: power-controller@80140 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80140 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "isp_sens2";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usb: power-controller@80268 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80268 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usb";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usbctrl: power-controller@80270 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80270 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usbctrl";</div><div class='add'>+		power-domains = &lt;&amp;ps_usb&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usb2host0: power-controller@80278 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80278 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usb2host0";</div><div class='add'>+		power-domains = &lt;&amp;ps_usbctrl&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usb2host1: power-controller@80288 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80288 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usb2host1";</div><div class='add'>+		power-domains = &lt;&amp;ps_usbctrl&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_rtmux: power-controller@802a8 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802a8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "rtmux";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_media: power-controller@802d8 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802d8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "media";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_isp_sys: power-controller@802d0 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802d0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "isp_sys";</div><div class='add'>+		power-domains = &lt;&amp;ps_rtmux&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_msr: power-controller@802e8 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802e8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "msr";</div><div class='add'>+		power-domains = &lt;&amp;ps_media&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_jpg: power-controller@802e0 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802e0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "jpg";</div><div class='add'>+		power-domains = &lt;&amp;ps_media&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_disp0_fe: power-controller@802b0 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802b0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "disp0_fe";</div><div class='add'>+		power-domains = &lt;&amp;ps_rtmux&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_disp0_be: power-controller@802b8 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802b8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "disp0_be";</div><div class='add'>+		power-domains = &lt;&amp;ps_disp0_fe&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pmp: power-controller@802f0 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802f0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pmp";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pms_sram: power-controller@802f8 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802f8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pms_sram";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart3: power-controller@80200 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80200 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart3";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart4: power-controller@80208 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80208 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart4";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart5: power-controller@80210 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80210 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart5";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart6: power-controller@80218 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80218 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart6";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart7: power-controller@80220 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80220 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart7";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart8: power-controller@80228 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80228 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart8";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_hfd0: power-controller@80238 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80238 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "hfd0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mcc: power-controller@80240 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80240 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mcc";</div><div class='add'>+		apple,always-on; /* Memory cache controller */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs0: power-controller@80248 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80248 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs0";</div><div class='add'>+		apple,always-on; /* LPDDR4 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs1: power-controller@80250 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80250 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs1";</div><div class='add'>+		apple,always-on; /* LPDDR4 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs2: power-controller@80258 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80258 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs2";</div><div class='add'>+		apple,always-on; /* LPDDR4 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs3: power-controller@80260 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80260 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs3";</div><div class='add'>+		apple,always-on; /* LPDDR4 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usb2host0_ohci: power-controller@80280 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80280 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usb2host0_ohci";</div><div class='add'>+		power-domains = &lt;&amp;ps_usb2host0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usbotg: power-controller@80290 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80290 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usbotg";</div><div class='add'>+		power-domains = &lt;&amp;ps_usbctrl&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_smx: power-controller@80298 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80298 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "smx";</div><div class='add'>+		apple,always-on; /* Apple fabric, critical block */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sf: power-controller@802a0 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802a0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sf";</div><div class='add'>+		apple,always-on; /* Apple fabric, critical block */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mipi_dsi: power-controller@802c0 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802c0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mipi_dsi";</div><div class='add'>+		power-domains = &lt;&amp;ps_disp0_be&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dp: power-controller@802c8 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802c8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dp";</div><div class='add'>+		power-domains = &lt;&amp;ps_disp0_be&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc_sys: power-controller@80310 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80310 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc_sys";</div><div class='add'>+		power-domains = &lt;&amp;ps_media&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pcie: power-controller@80318 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80318 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pcie";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pcie_aux: power-controller@80320 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80320 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pcie_aux";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_vdec0: power-controller@80300 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80300 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "vdec0";</div><div class='add'>+		power-domains = &lt;&amp;ps_media&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_gfx: power-controller@80328 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80328 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "gfx";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sep: power-controller@80400 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80400 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sep";</div><div class='add'>+		apple,always-on; /* Locked on */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_isp_rsts0: power-controller@84000 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x84000 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "isp_rsts0";</div><div class='add'>+		power-domains = &lt;&amp;ps_isp_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_isp_rsts1: power-controller@84008 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x84008 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "isp_rsts1";</div><div class='add'>+		power-domains = &lt;&amp;ps_isp_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_isp_vis: power-controller@84010 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x84010 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "isp_vis";</div><div class='add'>+		power-domains = &lt;&amp;ps_isp_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_isp_be: power-controller@84018 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x84018 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "isp_be";</div><div class='add'>+		power-domains = &lt;&amp;ps_isp_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_isp_pearl: power-controller@84020 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x84020 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "isp_pearl";</div><div class='add'>+		power-domains = &lt;&amp;ps_isp_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dprx: power-controller@84028 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x84028 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dprx";</div><div class='add'>+		power-domains = &lt;&amp;ps_isp_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc_pipe4: power-controller@88000 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x88000 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc_pipe4";</div><div class='add'>+		power-domains = &lt;&amp;ps_venc_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc_pipe5: power-controller@88008 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x88008 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc_pipe5";</div><div class='add'>+		power-domains = &lt;&amp;ps_venc_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc_me0: power-controller@88010 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x88010 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc_me0";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc_me1: power-controller@88018 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x88018 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc_me1";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pmgr_mini {</div><div class='add'>+	ps_aop: power-controller@80000 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80000 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "aop";</div><div class='add'>+		power-domains = &lt;&amp;ps_aop_cpu &amp;ps_aop_busif &amp;ps_aop_filter&gt;;</div><div class='add'>+		apple,always-on; /* Always on processor */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_debug: power-controller@80008 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80008 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "debug";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_aop_gpio: power-controller@80010 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80010 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "aop_gpio";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_aop_cpu: power-controller@80048 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80048 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "aop_cpu";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_aop_filter: power-controller@80050 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80050 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "aop_filter";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_aop_busif: power-controller@80058 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80058 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "aop_busif";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8010.dtsi b/arch/arm64/boot/dts/apple/t8010.dtsi<br/>new file mode 100644<br/>index 000000000000..522b3896aa87<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8010.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8010.dtsi</a></div><div class='hunk'>@@ -0,0 +1,337 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0 OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple T8010 "A10" SoC</div><div class='add'>+ *</div><div class='add'>+ * Other names: H9P, "Cayman"</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/apple-aic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/apple.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	clkref: clock-ref {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+		clock-output-names = "clkref";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			compatible = "apple,hurricane-zephyr";</div><div class='add'>+			reg = &lt;0x0 0x0&gt;;</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			operating-points-v2 = &lt;&amp;fusion_opp&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache&gt;;</div><div class='add'>+			i-cache-size = &lt;0x10000&gt;; /* P-core */</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;; /* P-core */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@1 {</div><div class='add'>+			compatible = "apple,hurricane-zephyr";</div><div class='add'>+			reg = &lt;0x0 0x1&gt;;</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			operating-points-v2 = &lt;&amp;fusion_opp&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache&gt;;</div><div class='add'>+			i-cache-size = &lt;0x10000&gt;; /* P-core */</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;; /* P-core */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_cache: l2-cache {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x300000&gt;; /* P-cluster */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fusion_opp: opp-table {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Apple Fusion Architecture: Hardware big.LITTLE switcher</div><div class='add'>+		 * that use p-state transitions to switch between cores.</div><div class='add'>+		 * Only one type of core can be active at a given time.</div><div class='add'>+		 *</div><div class='add'>+		 * The E-core frequencies are adjusted so performance scales</div><div class='add'>+		 * linearly with reported clock speed.</div><div class='add'>+		 */</div><div class='add'>+</div><div class='add'>+		opp01 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;172000000&gt;; /* 300 MHz, E-core */</div><div class='add'>+			opp-level = &lt;1&gt;;</div><div class='add'>+			clock-latency-ns = &lt;11000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp02 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;230000000&gt;; /* 396 MHz, E-core */</div><div class='add'>+			opp-level = &lt;2&gt;;</div><div class='add'>+			clock-latency-ns = &lt;49000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp03 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;425000000&gt;; /* 732 MHz, E-core */</div><div class='add'>+			opp-level = &lt;3&gt;;</div><div class='add'>+			clock-latency-ns = &lt;13000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp04 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;637000000&gt;; /* 1092 MHz, E-core */</div><div class='add'>+			opp-level = &lt;4&gt;;</div><div class='add'>+			clock-latency-ns = &lt;18000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp05 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;756000000&gt;;</div><div class='add'>+			opp-level = &lt;5&gt;;</div><div class='add'>+			clock-latency-ns = &lt;35000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp06 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1056000000&gt;;</div><div class='add'>+			opp-level = &lt;6&gt;;</div><div class='add'>+			clock-latency-ns = &lt;31000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp07 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1356000000&gt;;</div><div class='add'>+			opp-level = &lt;7&gt;;</div><div class='add'>+			clock-latency-ns = &lt;37000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp08 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1644000000&gt;;</div><div class='add'>+			opp-level = &lt;8&gt;;</div><div class='add'>+			clock-latency-ns = &lt;39500&gt;;</div><div class='add'>+		};</div><div class='add'>+		hurricane_opp09: opp09 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1944000000&gt;;</div><div class='add'>+			opp-level = &lt;9&gt;;</div><div class='add'>+			clock-latency-ns = &lt;46000&gt;;</div><div class='add'>+			status = "disabled"; /* Not available on N112 */</div><div class='add'>+		};</div><div class='add'>+		hurricane_opp10: opp10 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2244000000&gt;;</div><div class='add'>+			opp-level = &lt;10&gt;;</div><div class='add'>+			clock-latency-ns = &lt;56000&gt;;</div><div class='add'>+			status = "disabled"; /* Not available on N112 */</div><div class='add'>+		};</div><div class='add'>+#if 0</div><div class='add'>+		/* Not available until CPU deep sleep is implemented */</div><div class='add'>+		hurricane_opp11: opp11 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2340000000&gt;;</div><div class='add'>+			opp-level = &lt;11&gt;;</div><div class='add'>+			clock-latency-ns = &lt;56000&gt;;</div><div class='add'>+			turbo-mode;</div><div class='add'>+			status = "disabled"; /* Not available on N112 */</div><div class='add'>+		};</div><div class='add'>+#endif</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		nonposted-mmio;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		cpufreq: performance-controller@202f20000 {</div><div class='add'>+			compatible = "apple,t8010-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";</div><div class='add'>+			reg = &lt;0x2 0x02f20000 0 0x1000&gt;;</div><div class='add'>+			#performance-domain-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		serial0: serial@20a0c0000 {</div><div class='add'>+			compatible = "apple,s5l-uart";</div><div class='add'>+			reg = &lt;0x2 0x0a0c0000 0x0 0x4000&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 218 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			/* Use the bootloader-enabled clocks for now. */</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;, &lt;&amp;clkref&gt;;</div><div class='add'>+			clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+			power-domains = &lt;&amp;ps_uart0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c0: i2c@20a110000 {</div><div class='add'>+			compatible = "apple,t8010-i2c", "apple,i2c";</div><div class='add'>+			reg = &lt;0x2 0x0a110000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 232 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c0_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			power-domains = &lt;&amp;ps_i2c0&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c1: i2c@20a111000 {</div><div class='add'>+			compatible = "apple,t8010-i2c", "apple,i2c";</div><div class='add'>+			reg = &lt;0x2 0x0a111000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 233 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c1_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			power-domains = &lt;&amp;ps_i2c1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c2: i2c@20a112000 {</div><div class='add'>+			compatible = "apple,t8010-i2c", "apple,i2c";</div><div class='add'>+			reg = &lt;0x2 0x0a112000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 234 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c2_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			power-domains = &lt;&amp;ps_i2c2&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c3: i2c@20a113000 {</div><div class='add'>+			compatible = "apple,t8010-i2c", "apple,i2c";</div><div class='add'>+			reg = &lt;0x2 0x0a113000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 235 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c3_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			power-domains = &lt;&amp;ps_i2c3&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmgr: power-management@20e000000 {</div><div class='add'>+			compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			reg = &lt;0x2 0xe000000 0 0x8c000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aic: interrupt-controller@20e100000 {</div><div class='add'>+			compatible = "apple,t8010-aic", "apple,aic";</div><div class='add'>+			reg = &lt;0x2 0x0e100000 0x0 0x100000&gt;;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			power-domains = &lt;&amp;ps_aic&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dwi_bl: backlight@20e200080 {</div><div class='add'>+			compatible = "apple,t8010-dwi-bl", "apple,dwi-bl";</div><div class='add'>+			reg = &lt;0x2 0x0e200080 0x0 0x8&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_dwi&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_ap: pinctrl@20f100000 {</div><div class='add'>+			compatible = "apple,t8010-pinctrl", "apple,pinctrl";</div><div class='add'>+			reg = &lt;0x2 0x0f100000 0x0 0x100000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_gpio&gt;;</div><div class='add'>+</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;pinctrl_ap 0 0 208&gt;;</div><div class='add'>+			apple,npins = &lt;208&gt;;</div><div class='add'>+</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 42 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 43 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 44 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 45 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 46 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 47 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 48 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			i2c0_pins: i2c0-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(197, 1)&gt;,</div><div class='add'>+					 &lt;APPLE_PINMUX(196, 1)&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c1_pins: i2c1-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(40, 1)&gt;,</div><div class='add'>+					 &lt;APPLE_PINMUX(39, 1)&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c2_pins: i2c2-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(132, 1)&gt;,</div><div class='add'>+					 &lt;APPLE_PINMUX(133, 1)&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c3_pins: i2c3-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(41, 1)&gt;,</div><div class='add'>+					 &lt;APPLE_PINMUX(42, 1)&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_aop: pinctrl@2100f0000 {</div><div class='add'>+			compatible = "apple,t8010-pinctrl", "apple,pinctrl";</div><div class='add'>+			reg = &lt;0x2 0x100f0000 0x0 0x100000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_aop_gpio&gt;;</div><div class='add'>+</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;pinctrl_aop 0 0 42&gt;;</div><div class='add'>+			apple,npins = &lt;42&gt;;</div><div class='add'>+</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 128 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 129 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 130 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 131 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 132 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 133 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 134 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmgr_mini: power-management@210200000 {</div><div class='add'>+			compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			reg = &lt;0x2 0x10200000 0 0x84000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wdt: watchdog@2102b0000 {</div><div class='add'>+			compatible = "apple,t8010-wdt", "apple,wdt";</div><div class='add'>+			reg = &lt;0x2 0x102b0000 0x0 0x4000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 4 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupt-names = "phys", "virt";</div><div class='add'>+		/* Note that A10 doesn't actually have a hypervisor (EL2 is not implemented). */</div><div class='add'>+		interrupts = &lt;AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include "t8010-pmgr.dtsi"</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8011-common.dtsi b/arch/arm64/boot/dts/apple/t8011-common.dtsi<br/>new file mode 100644<br/>index 000000000000..2010b56246f1<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8011-common.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8011-common.dtsi</a></div><div class='hunk'>@@ -0,0 +1,47 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple TV 4K, Apple iPad Pro 2</div><div class='add'>+ *</div><div class='add'>+ * This file contains parts common to all Apple A10X devices.</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2024, Nick Chan &lt;towinchenmi@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;serial0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		stdout-path = "serial0";</div><div class='add'>+</div><div class='add'>+		framebuffer0: framebuffer@0 {</div><div class='add'>+			compatible = "apple,simple-framebuffer", "simple-framebuffer";</div><div class='add'>+			reg = &lt;0 0 0 0&gt;; /* To be filled by loader */</div><div class='add'>+			power-domains = &lt;&amp;ps_disp0_fe &amp;ps_disp0_be &amp;ps_dp&gt;;</div><div class='add'>+			/* Format properties will be added by loader */</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@800000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x8 0 0 0&gt;; /* To be filled by loader */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		/* To be filled by loader */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;serial0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8011-j105a.dts b/arch/arm64/boot/dts/apple/t8011-j105a.dts<br/>new file mode 100644<br/>index 000000000000..d3e5b69c67aa<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8011-j105a.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8011-j105a.dts</a></div><div class='hunk'>@@ -0,0 +1,16 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple TV 4K (1st Generation), J105a, AppleTV6,2 (A1482)</div><div class='add'>+ * Copyright (c) 2024, Nick Chan &lt;towinchenmi@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t8011.dtsi"</div><div class='add'>+#include "t8011-common.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j105a", "apple,t8011", "apple,arm-platform";</div><div class='add'>+	model = "Apple TV 4K (1st Generation)";</div><div class='add'>+	chassis-type = "television";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8011-j120.dts b/arch/arm64/boot/dts/apple/t8011-j120.dts<br/>new file mode 100644<br/>index 000000000000..1b49bb5c97c3<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8011-j120.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8011-j120.dts</a></div><div class='hunk'>@@ -0,0 +1,16 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPad Pro 2 (12.9-inch) (Wi-Fi), J120, iPad7,1 (A1670)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t8011.dtsi"</div><div class='add'>+#include "t8011-common.dtsi"</div><div class='add'>+#include "t8011-pro2.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j120", "apple,t8011", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPad Pro 2 (12.9-inch) (Wi-Fi)";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8011-j121.dts b/arch/arm64/boot/dts/apple/t8011-j121.dts<br/>new file mode 100644<br/>index 000000000000..22f4aa1ecbda<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8011-j121.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8011-j121.dts</a></div><div class='hunk'>@@ -0,0 +1,16 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPad Pro 2 (12.9-inch) (Cellular), J121, iPad7,2 (A1671)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t8011.dtsi"</div><div class='add'>+#include "t8011-common.dtsi"</div><div class='add'>+#include "t8011-pro2.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j121", "apple,t8011", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPad Pro 2 (12.9-inch) (Cellular)";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8011-j207.dts b/arch/arm64/boot/dts/apple/t8011-j207.dts<br/>new file mode 100644<br/>index 000000000000..c3384e2cad44<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8011-j207.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8011-j207.dts</a></div><div class='hunk'>@@ -0,0 +1,16 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPad Pro 2 (10.5-inch) (Wi-Fi), J207, iPad7,3 (A1701)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t8011.dtsi"</div><div class='add'>+#include "t8011-common.dtsi"</div><div class='add'>+#include "t8011-pro2.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j207", "apple,t8011", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPad Pro 2 (10.5-inch) (Wi-Fi)";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8011-j208.dts b/arch/arm64/boot/dts/apple/t8011-j208.dts<br/>new file mode 100644<br/>index 000000000000..251fa76efb6b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8011-j208.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8011-j208.dts</a></div><div class='hunk'>@@ -0,0 +1,16 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPad Pro 2 (10.5-inch) (Cellular), J208, iPad7,4 (A1709)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t8011.dtsi"</div><div class='add'>+#include "t8011-common.dtsi"</div><div class='add'>+#include "t8011-pro2.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j208", "apple,t8011", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPad Pro 2 (10.5-inch) (Cellular)";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8011-pmgr.dtsi b/arch/arm64/boot/dts/apple/t8011-pmgr.dtsi<br/>new file mode 100644<br/>index 000000000000..c44e3f9d7087<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8011-pmgr.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8011-pmgr.dtsi</a></div><div class='hunk'>@@ -0,0 +1,806 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * PMGR Power domains for the Apple T8011 "A10X" SoC</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2024 Nick Chan &lt;towinchenmi@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;pmgr {</div><div class='add'>+	ps_cpu0: power-controller@80000 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80000 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "cpu0";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_cpu1: power-controller@80008 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80008 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "cpu1";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_cpu2: power-controller@80010 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80010 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "cpu2";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_cpm: power-controller@80040 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80040 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "cpm";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sio_busif: power-controller@80158 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80158 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sio_busif";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sio_p: power-controller@80160 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80160 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sio_p";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_busif&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sbr: power-controller@80100 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80100 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sbr";</div><div class='add'>+		apple,always-on; /* Apple fabric, critical block */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_aic: power-controller@80108 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80108 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "aic";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dwi: power-controller@80110 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80110 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dwi";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_gpio: power-controller@80118 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80118 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "gpio";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pms: power-controller@80120 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80120 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pms";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pcie_ref: power-controller@80148 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80148 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pcie_ref";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca0: power-controller@80170 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80170 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca1: power-controller@80178 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80178 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca1";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca2: power-controller@80180 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80180 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca2";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca3: power-controller@80188 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80188 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca3";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca4: power-controller@80190 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80190 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca4";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pwm0: power-controller@80198 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80198 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pwm0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c0: power-controller@801a0 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801a0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c1: power-controller@801a8 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801a8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c1";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c2: power-controller@801b0 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801b0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c2";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c3: power-controller@801b8 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801b8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c3";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi0: power-controller@801c0 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801c0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi1: power-controller@801c8 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801c8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi1";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi2: power-controller@801d0 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801d0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi2";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi3: power-controller@801d8 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801d8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi3";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart0: power-controller@801e0 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801e0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart1: power-controller@801e8 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801e8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart1";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart2: power-controller@801f0 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801f0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart2";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart3: power-controller@801f8 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801f8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart3";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sio: power-controller@80168 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80168 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sio";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_hsic0_phy: power-controller@80128 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80128 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "hsic0_phy";</div><div class='add'>+		power-domains = &lt;&amp;ps_usb3host&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_isp_sens0: power-controller@80130 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80130 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "isp_sens0";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_isp_sens1: power-controller@80138 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80138 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "isp_sens1";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_isp_sens2: power-controller@80140 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80140 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "isp_sens2";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usb: power-controller@80288 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80288 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usb";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usbctrl: power-controller@80290 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80290 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usbctrl";</div><div class='add'>+		power-domains = &lt;&amp;ps_usb&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usb2host: power-controller@80298 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80298 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usb2host";</div><div class='add'>+		power-domains = &lt;&amp;ps_usbctrl&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usb2dev: power-controller@802a0 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802a0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usb2dev";</div><div class='add'>+		power-domains = &lt;&amp;ps_usbctrl&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usb3host: power-controller@802a8 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802a8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usb3host";</div><div class='add'>+		power-domains = &lt;&amp;ps_usbctrl&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usb3dev: power-controller@802b0 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802b0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usb3dev";</div><div class='add'>+		power-domains = &lt;&amp;ps_usbctrl&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_media: power-controller@802e8 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802e8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "media";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_isp_sys: power-controller@802e0 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802e0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "isp_sys";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_msr: power-controller@802f8 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802f8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "msr";</div><div class='add'>+		power-domains = &lt;&amp;ps_media&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_jpg: power-controller@802f0 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802f0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "jpg";</div><div class='add'>+		power-domains = &lt;&amp;ps_media&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_disp0_fe: power-controller@802c8 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802c8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "disp0_fe";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_disp0_be: power-controller@802d0 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802d0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "disp0_be";</div><div class='add'>+		power-domains = &lt;&amp;ps_disp0_fe&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dpa: power-controller@80230 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80230 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dpa";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart4: power-controller@80200 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80200 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart4";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart5: power-controller@80208 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80208 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart5";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart6: power-controller@80210 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80210 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart6";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart7: power-controller@80218 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80218 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart7";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart8: power-controller@80220 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80220 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart8";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_hfd0: power-controller@80238 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80238 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "hfd0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mcc: power-controller@80240 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80240 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mcc";</div><div class='add'>+		apple,always-on; /* Memory cache controller */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs0: power-controller@80248 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80248 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs0";</div><div class='add'>+		apple,always-on; /* LPDDR4 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs1: power-controller@80250 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80250 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs1";</div><div class='add'>+		apple,always-on; /* LPDDR4 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs2: power-controller@80258 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80258 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs2";</div><div class='add'>+		apple,always-on; /* LPDDR4 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs3: power-controller@80260 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80260 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs3";</div><div class='add'>+		apple,always-on; /* LPDDR4 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs4: power-controller@80268 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80268 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs4";</div><div class='add'>+		apple,always-on; /* LPDDR4 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs5: power-controller@80270 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80270 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs5";</div><div class='add'>+		apple,always-on; /* LPDDR4 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs6: power-controller@80278 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80278 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs6";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs7: power-controller@80280 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80280 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs7";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_smx: power-controller@802b8 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802b8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "smx";</div><div class='add'>+		apple,always-on; /* Apple fabric, critical block */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sf: power-controller@802c0 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802c0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sf";</div><div class='add'>+		apple,always-on; /* Apple fabric, critical block */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dp: power-controller@802d8 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802d8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dp";</div><div class='add'>+		power-domains = &lt;&amp;ps_disp0_be&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc_sys: power-controller@80320 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80320 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc_sys";</div><div class='add'>+		power-domains = &lt;&amp;ps_media&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_srs: power-controller@80390 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80390 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "srs";</div><div class='add'>+		power-domains = &lt;&amp;ps_media&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pms_sram: power-controller@80308 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80308 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pms_sram";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pmp: power-controller@80300 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80300 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pmp";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pcie: power-controller@80328 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80328 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pcie";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pcie_aux: power-controller@80330 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80330 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pcie_aux";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_vdec0: power-controller@80310 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80310 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "vdec0";</div><div class='add'>+		power-domains = &lt;&amp;ps_media&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_gfx: power-controller@80338 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80338 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "gfx";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sep: power-controller@80400 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80400 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sep";</div><div class='add'>+		apple,always-on; /* Locked on */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_isp_rsts0: power-controller@84000 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x84000 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "isp_rsts0";</div><div class='add'>+		power-domains = &lt;&amp;ps_isp_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_isp_rsts1: power-controller@84008 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x84008 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "isp_rsts1";</div><div class='add'>+		power-domains = &lt;&amp;ps_isp_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_isp_vis: power-controller@84010 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x84010 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "isp_vis";</div><div class='add'>+		power-domains = &lt;&amp;ps_isp_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_isp_be: power-controller@84018 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x84018 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "isp_be";</div><div class='add'>+		power-domains = &lt;&amp;ps_isp_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_isp_pearl: power-controller@84020 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x84020 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "isp_pearl";</div><div class='add'>+		power-domains = &lt;&amp;ps_isp_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dprx: power-controller@84028 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x84028 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dprx";</div><div class='add'>+		power-domains = &lt;&amp;ps_isp_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc_pipe4: power-controller@88000 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x88000 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc_pipe4";</div><div class='add'>+		power-domains = &lt;&amp;ps_venc_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc_pipe5: power-controller@88008 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x88008 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc_pipe5";</div><div class='add'>+		power-domains = &lt;&amp;ps_venc_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc_me0: power-controller@88010 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x88010 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc_me0";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc_me1: power-controller@88018 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x88018 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc_me1";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pmgr_mini {</div><div class='add'>+	ps_aop: power-controller@80000 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80000 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "aop";</div><div class='add'>+		power-domains = &lt;&amp;ps_aop_cpu &amp;ps_aop_filter &amp;ps_aop_busif&gt;;</div><div class='add'>+		apple,always-on; /* Always on processor */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_debug: power-controller@80008 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80008 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "debug";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_aop_gpio: power-controller@80010 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80010 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "aop_gpio";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_aop_cpu: power-controller@80048 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80048 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "aop_cpu";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_aop_filter: power-controller@80050 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80050 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "aop_filter";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_aop_busif: power-controller@80058 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80058 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "aop_busif";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8011-pro2.dtsi b/arch/arm64/boot/dts/apple/t8011-pro2.dtsi<br/>new file mode 100644<br/>index 000000000000..5eaa0a73350f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8011-pro2.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8011-pro2.dtsi</a></div><div class='hunk'>@@ -0,0 +1,50 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPad Pro 2 common device tree</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	chassis-type = "tablet";</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		button-home {</div><div class='add'>+			label = "Home Button";</div><div class='add'>+			gpios = &lt;&amp;pinctrl_ap 139 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_HOMEPAGE&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-power {</div><div class='add'>+			label = "Power Button";</div><div class='add'>+			gpios = &lt;&amp;pinctrl_ap 138 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-voldown {</div><div class='add'>+			label = "Volume Down";</div><div class='add'>+			gpios = &lt;&amp;pinctrl_ap 43 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-volup {</div><div class='add'>+			label = "Volume Up";</div><div class='add'>+			gpios = &lt;&amp;pinctrl_ap 40 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ps_dcs6 {</div><div class='add'>+	apple,always-on; /* LPDDR4 interface */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ps_dcs7 {</div><div class='add'>+	apple,always-on; /* LPDDR4 interface */</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8011.dtsi b/arch/arm64/boot/dts/apple/t8011.dtsi<br/>new file mode 100644<br/>index 000000000000..039aa4d1e887<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8011.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8011.dtsi</a></div><div class='hunk'>@@ -0,0 +1,334 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple T8011 "A10X" SoC</div><div class='add'>+ *</div><div class='add'>+ * Other names: H9G, "Myst"</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/apple-aic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/apple.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	clkref: clock-ref {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+		clock-output-names = "clkref";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			compatible = "apple,hurricane-zephyr";</div><div class='add'>+			reg = &lt;0x0 0x0&gt;;</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			operating-points-v2 = &lt;&amp;fusion_opp&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache&gt;;</div><div class='add'>+			i-cache-size = &lt;0x10000&gt;; /* P-core */</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;; /* P-core */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@1 {</div><div class='add'>+			compatible = "apple,hurricane-zephyr";</div><div class='add'>+			reg = &lt;0x0 0x1&gt;;</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			operating-points-v2 = &lt;&amp;fusion_opp&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache&gt;;</div><div class='add'>+			i-cache-size = &lt;0x10000&gt;; /* P-core */</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;; /* P-core */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@2 {</div><div class='add'>+			compatible = "apple,hurricane-zephyr";</div><div class='add'>+			reg = &lt;0x0 0x2&gt;;</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			operating-points-v2 = &lt;&amp;fusion_opp&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache&gt;;</div><div class='add'>+			i-cache-size = &lt;0x10000&gt;; /* P-core */</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;; /* P-core */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_cache: l2-cache {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x800000&gt;; /* P-cluster */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fusion_opp: opp-table {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Apple Fusion Architecture: Hardwired big.LITTLE switcher</div><div class='add'>+		 * that use p-state transitions to switch between cores.</div><div class='add'>+		 *</div><div class='add'>+		 * The E-core frequencies are adjusted so performance scales</div><div class='add'>+		 * linearly with reported clock speed.</div><div class='add'>+		 */</div><div class='add'>+</div><div class='add'>+		opp01 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;172000000&gt;; /* 300 MHz, E-core */</div><div class='add'>+			opp-level = &lt;1&gt;;</div><div class='add'>+			clock-latency-ns = &lt;12000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp02 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;230000000&gt;; /* 396 MHz, E-core */</div><div class='add'>+			opp-level = &lt;2&gt;;</div><div class='add'>+			clock-latency-ns = &lt;135000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp03 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;448000000&gt;; /* 768 MHz, E-core */</div><div class='add'>+			opp-level = &lt;3&gt;;</div><div class='add'>+			clock-latency-ns = &lt;105000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp04 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;662000000&gt;; /* 1152 MHz, E-core */</div><div class='add'>+			opp-level = &lt;4&gt;;</div><div class='add'>+			clock-latency-ns = &lt;115000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp05 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;804000000&gt;;</div><div class='add'>+			opp-level = &lt;5&gt;;</div><div class='add'>+			clock-latency-ns = &lt;122000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp06 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1140000000&gt;;</div><div class='add'>+			opp-level = &lt;6&gt;;</div><div class='add'>+			clock-latency-ns = &lt;120000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp07 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1548000000&gt;;</div><div class='add'>+			opp-level = &lt;7&gt;;</div><div class='add'>+			clock-latency-ns = &lt;125000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp08 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1956000000&gt;;</div><div class='add'>+			opp-level = &lt;8&gt;;</div><div class='add'>+			clock-latency-ns = &lt;135000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp09 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2316000000&gt;;</div><div class='add'>+			opp-level = &lt;9&gt;;</div><div class='add'>+			clock-latency-ns = &lt;140000&gt;;</div><div class='add'>+		};</div><div class='add'>+#if 0</div><div class='add'>+		/* Not available until CPU deep sleep is implemented */</div><div class='add'>+		opp10 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2400000000&gt;;</div><div class='add'>+			opp-level = &lt;10&gt;;</div><div class='add'>+			clock-latency-ns = &lt;140000&gt;;</div><div class='add'>+			turbo-mode;</div><div class='add'>+		};</div><div class='add'>+#endif</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		nonposted-mmio;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		cpufreq: performance-controller@202f20000 {</div><div class='add'>+			compatible = "apple,t8010-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";</div><div class='add'>+			reg = &lt;0x2 0x02f20000 0 0x1000&gt;;</div><div class='add'>+			#performance-domain-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		serial0: serial@20a0c0000 {</div><div class='add'>+			compatible = "apple,s5l-uart";</div><div class='add'>+			reg = &lt;0x2 0x0a0c0000 0x0 0x4000&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 216 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			/* Use the bootloader-enabled clocks for now. */</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;, &lt;&amp;clkref&gt;;</div><div class='add'>+			clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+			power-domains = &lt;&amp;ps_uart0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c0: i2c@20a110000 {</div><div class='add'>+			compatible = "apple,t8010-i2c", "apple,i2c";</div><div class='add'>+			reg = &lt;0x2 0x0a110000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 230 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c0_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			power-domains = &lt;&amp;ps_i2c0&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c1: i2c@20a111000 {</div><div class='add'>+			compatible = "apple,t8010-i2c", "apple,i2c";</div><div class='add'>+			reg = &lt;0x2 0x0a111000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 231 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c1_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			power-domains = &lt;&amp;ps_i2c1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c2: i2c@20a112000 {</div><div class='add'>+			compatible = "apple,t8010-i2c", "apple,i2c";</div><div class='add'>+			reg = &lt;0x2 0x0a112000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 232 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c2_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			power-domains = &lt;&amp;ps_i2c2&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c3: i2c@20a113000 {</div><div class='add'>+			compatible = "apple,t8010-i2c", "apple,i2c";</div><div class='add'>+			reg = &lt;0x2 0x0a113000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 233 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c3_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			power-domains = &lt;&amp;ps_i2c3&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmgr: power-management@20e000000 {</div><div class='add'>+			compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			reg = &lt;0x2 0xe000000 0 0x8c000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aic: interrupt-controller@20e100000 {</div><div class='add'>+			compatible = "apple,t8010-aic", "apple,aic";</div><div class='add'>+			reg = &lt;0x2 0x0e100000 0x0 0x100000&gt;;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			power-domains = &lt;&amp;ps_aic&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_ap: pinctrl@20f100000 {</div><div class='add'>+			compatible = "apple,t8010-pinctrl", "apple,pinctrl";</div><div class='add'>+			reg = &lt;0x2 0x0f100000 0x0 0x100000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_gpio&gt;;</div><div class='add'>+</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;pinctrl_ap 0 0 219&gt;;</div><div class='add'>+			apple,npins = &lt;219&gt;;</div><div class='add'>+</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 42 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 43 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 44 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 45 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 46 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 47 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 48 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			i2c0_pins: i2c0-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(211, 1)&gt;,</div><div class='add'>+					 &lt;APPLE_PINMUX(210, 1)&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c1_pins: i2c1-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(156, 1)&gt;,</div><div class='add'>+					 &lt;APPLE_PINMUX(155, 1)&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c2_pins: i2c2-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(58, 1)&gt;,</div><div class='add'>+					 &lt;APPLE_PINMUX(57, 1)&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c3_pins: i2c3-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(158, 1)&gt;,</div><div class='add'>+					 &lt;APPLE_PINMUX(157, 1)&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_aop: pinctrl@2100f0000 {</div><div class='add'>+			compatible = "apple,t8010-pinctrl", "apple,pinctrl";</div><div class='add'>+			reg = &lt;0x2 0x100f0000 0x0 0x100000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_aop_gpio&gt;;</div><div class='add'>+</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;pinctrl_aop 0 0 42&gt;;</div><div class='add'>+			apple,npins = &lt;42&gt;;</div><div class='add'>+</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 125 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 126 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 127 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 128 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 129 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 130 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 131 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmgr_mini: power-management@210200000 {</div><div class='add'>+			compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			reg = &lt;0x2 0x10200000 0 0x84000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wdt: watchdog@2102b0000 {</div><div class='add'>+			compatible = "apple,t8010-wdt", "apple,wdt";</div><div class='add'>+			reg = &lt;0x2 0x102b0000 0x0 0x4000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 4 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupt-names = "phys", "virt";</div><div class='add'>+		/* Note that A10X doesn't actually have a hypervisor (EL2 is not implemented). */</div><div class='add'>+		interrupts = &lt;AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include "t8011-pmgr.dtsi"</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8012-j132.dts b/arch/arm64/boot/dts/apple/t8012-j132.dts<br/>new file mode 100644<br/>index 000000000000..7dcac51703ff<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8012-j132.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8012-j132.dts</a></div><div class='hunk'>@@ -0,0 +1,15 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple T2 MacBookPro15,2 (j132), J132, iBridge2,4</div><div class='add'>+ * Copyright (c) 2024, Nick Chan &lt;towinchenmi@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t8012-jxxx.dtsi"</div><div class='add'>+#include "t8012-touchbar.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Apple T2 MacBookPro15,2 (j132)";</div><div class='add'>+	compatible = "apple,j132", "apple,t8012", "apple,arm-platform";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8012-j137.dts b/arch/arm64/boot/dts/apple/t8012-j137.dts<br/>new file mode 100644<br/>index 000000000000..dbde1ad7ce14<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8012-j137.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8012-j137.dts</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple T2 iMacPro1,1 (j137), J137, iBridge2,1</div><div class='add'>+ * Copyright (c) 2024, Nick Chan &lt;towinchenmi@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t8012-jxxx.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Apple T2 iMacPro1,1 (j137)";</div><div class='add'>+	compatible = "apple,j137", "apple,t8012", "apple,arm-platform";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8012-j140a.dts b/arch/arm64/boot/dts/apple/t8012-j140a.dts<br/>new file mode 100644<br/>index 000000000000..5df1ff74d2df<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8012-j140a.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8012-j140a.dts</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple T2 MacBookAir8,2 (j140a), J140a, iBridge2,12</div><div class='add'>+ * Copyright (c) 2024, Nick Chan &lt;towinchenmi@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t8012-jxxx.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Apple T2 MacBookAir8,2 (j140a)";</div><div class='add'>+	compatible = "apple,j140a", "apple,t8012", "apple,arm-platform";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8012-j140k.dts b/arch/arm64/boot/dts/apple/t8012-j140k.dts<br/>new file mode 100644<br/>index 000000000000..a0ef1585e5c2<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8012-j140k.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8012-j140k.dts</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple T2 MacBookAir8,1 (j140k), J140k, iBridge2,8</div><div class='add'>+ * Copyright (c) 2024, Nick Chan &lt;towinchenmi@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t8012-jxxx.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Apple T2 MacBookAir8,1 (j140k)";</div><div class='add'>+	compatible = "apple,j140k", "apple,t8012", "apple,arm-platform";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8012-j152f.dts b/arch/arm64/boot/dts/apple/t8012-j152f.dts<br/>new file mode 100644<br/>index 000000000000..261416eaf97e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8012-j152f.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8012-j152f.dts</a></div><div class='hunk'>@@ -0,0 +1,15 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple T2 MacBookPro16,1 (j152f), J152f, iBridge2,14</div><div class='add'>+ * Copyright (c) 2024, Nick Chan &lt;towinchenmi@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t8012-jxxx.dtsi"</div><div class='add'>+#include "t8012-touchbar.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Apple T2 MacBookPro16,1 (j152f)";</div><div class='add'>+	compatible = "apple,j152f", "apple,t8012", "apple,arm-platform";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8012-j160.dts b/arch/arm64/boot/dts/apple/t8012-j160.dts<br/>new file mode 100644<br/>index 000000000000..fbcc0604f4a0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8012-j160.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8012-j160.dts</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple T2 MacPro7,1 (j160), J160, iBridge2,6</div><div class='add'>+ * Copyright (c) 2024, Nick Chan &lt;towinchenmi@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t8012-jxxx.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Apple T2 MacPro7,1 (j160)";</div><div class='add'>+	compatible = "apple,j160", "apple,t8012", "apple,arm-platform";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8012-j174.dts b/arch/arm64/boot/dts/apple/t8012-j174.dts<br/>new file mode 100644<br/>index 000000000000..d11c70f84a71<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8012-j174.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8012-j174.dts</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple T2 Macmini8,1 (j174), J174, iBridge2,5</div><div class='add'>+ * Copyright (c) 2024, Nick Chan &lt;towinchenmi@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t8012-jxxx.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Apple T2 Macmini8,1 (j174)";</div><div class='add'>+	compatible = "apple,j174", "apple,t8012", "apple,arm-platform";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8012-j185.dts b/arch/arm64/boot/dts/apple/t8012-j185.dts<br/>new file mode 100644<br/>index 000000000000..33492f5db46d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8012-j185.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8012-j185.dts</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple T2 iMac20,1 (j185), J185, iBridge2,19</div><div class='add'>+ * Copyright (c) 2024, Nick Chan &lt;towinchenmi@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t8012-jxxx.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Apple T2 iMac20,1 (j185)";</div><div class='add'>+	compatible = "apple,j185", "apple,t8012", "apple,arm-platform";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8012-j185f.dts b/arch/arm64/boot/dts/apple/t8012-j185f.dts<br/>new file mode 100644<br/>index 000000000000..3a4abdd8f7d7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8012-j185f.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8012-j185f.dts</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple T2 iMac20,2 (j185f), J185f, iBridge2,20</div><div class='add'>+ * Copyright (c) 2024, Nick Chan &lt;towinchenmi@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t8012-jxxx.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Apple T2 iMac20,2 (j185f)";</div><div class='add'>+	compatible = "apple,j185f", "apple,t8012", "apple,arm-platform";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8012-j213.dts b/arch/arm64/boot/dts/apple/t8012-j213.dts<br/>new file mode 100644<br/>index 000000000000..8270812b9a68<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8012-j213.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8012-j213.dts</a></div><div class='hunk'>@@ -0,0 +1,15 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple T2 MacBookPro15,4 (j213), J213, iBridge2,10</div><div class='add'>+ * Copyright (c) 2024, Nick Chan &lt;towinchenmi@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t8012-jxxx.dtsi"</div><div class='add'>+#include "t8012-touchbar.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Apple T2 MacBookPro15,4 (j213)";</div><div class='add'>+	compatible = "apple,j213", "apple,t8012", "apple,arm-platform";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8012-j214k.dts b/arch/arm64/boot/dts/apple/t8012-j214k.dts<br/>new file mode 100644<br/>index 000000000000..5b8e42512060<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8012-j214k.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8012-j214k.dts</a></div><div class='hunk'>@@ -0,0 +1,15 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple T2 MacBookPro16,2 (j214k), J214k, iBridge2,16</div><div class='add'>+ * Copyright (c) 2024, Nick Chan &lt;towinchenmi@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t8012-jxxx.dtsi"</div><div class='add'>+#include "t8012-touchbar.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Apple T2 MacBookPro16,2 (j214k)";</div><div class='add'>+	compatible = "apple,j214k", "apple,t8012", "apple,arm-platform";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8012-j215.dts b/arch/arm64/boot/dts/apple/t8012-j215.dts<br/>new file mode 100644<br/>index 000000000000..ad574fbf7f92<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8012-j215.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8012-j215.dts</a></div><div class='hunk'>@@ -0,0 +1,15 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple T2 MacBookPro16,4 (j215), J215, iBridge2,22</div><div class='add'>+ * Copyright (c) 2024, Nick Chan &lt;towinchenmi@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t8012-jxxx.dtsi"</div><div class='add'>+#include "t8012-touchbar.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Apple T2 MacBookPro16,4 (j215)";</div><div class='add'>+	compatible = "apple,j215", "apple,t8012", "apple,arm-platform";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8012-j223.dts b/arch/arm64/boot/dts/apple/t8012-j223.dts<br/>new file mode 100644<br/>index 000000000000..de75d775aac5<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8012-j223.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8012-j223.dts</a></div><div class='hunk'>@@ -0,0 +1,15 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple T2 MacBookPro16,3 (j223), J223, iBridge2,21</div><div class='add'>+ * Copyright (c) 2024, Nick Chan &lt;towinchenmi@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t8012-jxxx.dtsi"</div><div class='add'>+#include "t8012-touchbar.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Apple T2 MacBookPro16,3 (j223)";</div><div class='add'>+	compatible = "apple,j223", "apple,t8012", "apple,arm-platform";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8012-j230k.dts b/arch/arm64/boot/dts/apple/t8012-j230k.dts<br/>new file mode 100644<br/>index 000000000000..4b19bc70ab0f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8012-j230k.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8012-j230k.dts</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple T2 MacBookAir9,1 (j230k), J230k, iBridge2,15</div><div class='add'>+ * Copyright (c) 2024, Nick Chan &lt;towinchenmi@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t8012-jxxx.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Apple T2 MacBookAir9,1 (j230k)";</div><div class='add'>+	compatible = "apple,j230k", "apple,t8012", "apple,arm-platform";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8012-j680.dts b/arch/arm64/boot/dts/apple/t8012-j680.dts<br/>new file mode 100644<br/>index 000000000000..aa5a72e07d3f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8012-j680.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8012-j680.dts</a></div><div class='hunk'>@@ -0,0 +1,15 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple T2 MacBookPro15,1 (j680), J680, iBridge2,3</div><div class='add'>+ * Copyright (c) 2024, Nick Chan &lt;towinchenmi@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t8012-jxxx.dtsi"</div><div class='add'>+#include "t8012-touchbar.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Apple T2 MacBookPro15,1 (j680)";</div><div class='add'>+	compatible = "apple,j680", "apple,t8012", "apple,arm-platform";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8012-j780.dts b/arch/arm64/boot/dts/apple/t8012-j780.dts<br/>new file mode 100644<br/>index 000000000000..9cee891cb16d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8012-j780.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8012-j780.dts</a></div><div class='hunk'>@@ -0,0 +1,15 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple T2 MacBookPro15,3 (j780), J780, iBridge2,7</div><div class='add'>+ * Copyright (c) 2024, Nick Chan &lt;towinchenmi@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t8012-jxxx.dtsi"</div><div class='add'>+#include "t8012-touchbar.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Apple T2 MacBookPro15,3 (j780)";</div><div class='add'>+	compatible = "apple,j780", "apple,t8012", "apple,arm-platform";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8012-jxxx.dtsi b/arch/arm64/boot/dts/apple/t8012-jxxx.dtsi<br/>new file mode 100644<br/>index 000000000000..36e82633bc52<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8012-jxxx.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8012-jxxx.dtsi</a></div><div class='hunk'>@@ -0,0 +1,44 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Common Device Tree for all T2 devices</div><div class='add'>+ *</div><div class='add'>+ * target-type: J132, J137, J140a, J140k, J152f, J160, J174, J185, J185f</div><div class='add'>+ * J213, J214k, J215, J223, J230k, J680, J780</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2024, Nick Chan &lt;towinchenmi@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "t8012.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	chassis-type = "embedded";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;serial0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		stdout-path = "serial0";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@800000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x8 0 0 0&gt;; /* To be filled by loader */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		/* To be filled by loader */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;serial0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8012-pmgr.dtsi b/arch/arm64/boot/dts/apple/t8012-pmgr.dtsi<br/>new file mode 100644<br/>index 000000000000..35a462edd4af<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8012-pmgr.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8012-pmgr.dtsi</a></div><div class='hunk'>@@ -0,0 +1,837 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * PMGR Power domains for the Apple T8012 "T2" SoC</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2024 Nick Chan &lt;towinchenmi@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;pmgr {</div><div class='add'>+	ps_cpu0: power-controller@80000 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80000 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "cpu0";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_cpu1: power-controller@80008 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80008 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "cpu1";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_cpm: power-controller@80040 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80040 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "cpm";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sio_busif: power-controller@80158 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80158 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sio_busif";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sio_p: power-controller@80160 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80160 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sio_p";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_busif&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_iomux: power-controller@80150 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80150 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "iomux";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sbr: power-controller@80100 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80100 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sbr";</div><div class='add'>+		apple,always-on; /* Apple fabric, critical block */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_aic: power-controller@80108 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80108 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "aic";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_gpio: power-controller@80110 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80110 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "gpio";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pcie_down_ref: power-controller@80138 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80138 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pcie_down_ref";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pcie_stg0_ref: power-controller@80140 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80140 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pcie_stg0_ref";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pcie_stg1_ref: power-controller@80148 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80148 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pcie_stg1_ref";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca0: power-controller@80170 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80170 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca1: power-controller@80178 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80178 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca1";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca2: power-controller@80180 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80180 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca2";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca3: power-controller@80188 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80188 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca3";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca4: power-controller@80190 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80190 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca4";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca5: power-controller@80198 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80198 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca5";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c0: power-controller@801a8 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801a8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c1: power-controller@801b0 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801b0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c1";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c2: power-controller@801b8 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801b8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c2";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c3: power-controller@801c0 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801c0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c3";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi0: power-controller@801e0 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801e0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi1: power-controller@801e8 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801e8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi1";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi2: power-controller@801f0 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801f0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi2";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi3: power-controller@801f8 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801f8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi3";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pwm0: power-controller@801a0 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801a0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pwm0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sio: power-controller@80168 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80168 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sio";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_isp_sens0: power-controller@80120 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80120 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "isp_sens0";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_isp_sens1: power-controller@80128 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80128 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "isp_sens1";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_isp_sens2: power-controller@80130 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80130 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "isp_sens2";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pms: power-controller@80118 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80118 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pms";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c4: power-controller@801c8 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801c8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c4";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c5: power-controller@801d0 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801d0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c5";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c6: power-controller@801d8 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801d8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c6";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usb: power-controller@80268 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80268 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usb";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usbctrl: power-controller@80270 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80270 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usbctrl";</div><div class='add'>+		power-domains = &lt;&amp;ps_usb&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usb2host0: power-controller@80278 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80278 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usb2host0";</div><div class='add'>+		power-domains = &lt;&amp;ps_usbctrl&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usb2host1: power-controller@80288 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80288 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usb2host1";</div><div class='add'>+		power-domains = &lt;&amp;ps_usbctrl&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_rtmux: power-controller@802a8 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802a8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "rtmux";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_media: power-controller@802d8 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802d8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "media";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_isp_sys: power-controller@802d0 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802d0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "isp_sys";</div><div class='add'>+		power-domains = &lt;&amp;ps_rtmux&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_msr: power-controller@802e8 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802e8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "msr";</div><div class='add'>+		power-domains = &lt;&amp;ps_media&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_jpg: power-controller@802e0 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802e0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "jpg";</div><div class='add'>+		power-domains = &lt;&amp;ps_media&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_disp0_fe: power-controller@802b0 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802b0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "disp0_fe";</div><div class='add'>+		power-domains = &lt;&amp;ps_rtmux&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_disp0_be: power-controller@802b8 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802b8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "disp0_be";</div><div class='add'>+		power-domains = &lt;&amp;ps_disp0_fe&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart0: power-controller@80200 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80200 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart1: power-controller@80208 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80208 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart1";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart2: power-controller@80210 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80210 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart2";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart3: power-controller@80218 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80218 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart3";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart4: power-controller@80220 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80220 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart4";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dpa: power-controller@80228 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80228 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dpa";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_hfd0: power-controller@80230 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80230 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "hfd0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mcc: power-controller@80240 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80240 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mcc";</div><div class='add'>+		apple,always-on; /* Memory cache controller */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs0: power-controller@80248 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80248 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs0";</div><div class='add'>+		apple,always-on; /* LPDDR4 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs1: power-controller@80250 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80250 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs1";</div><div class='add'>+		apple,always-on; /* LPDDR4 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs2: power-controller@80258 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80258 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs2";</div><div class='add'>+		/* Not used on some devicecs, to be disabled by loader */</div><div class='add'>+		apple,always-on; /* LPDDR4 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs3: power-controller@80260 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80260 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs3";</div><div class='add'>+		/* Not used on some devicecs, to be disabled by loader */</div><div class='add'>+		apple,always-on; /* LPDDR4 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usb2host0_ohci: power-controller@80280 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80280 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usb2host0_ohci";</div><div class='add'>+		power-domains = &lt;&amp;ps_usb2host0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usbotg: power-controller@80290 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80290 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usbotg";</div><div class='add'>+		power-domains = &lt;&amp;ps_usbctrl&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_smx: power-controller@80298 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80298 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "smx";</div><div class='add'>+		apple,always-on; /* Apple fabric, critical block */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sf: power-controller@802a0 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802a0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sf";</div><div class='add'>+		apple,always-on; /* Apple fabric, critical block */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mipi_dsi: power-controller@802c8 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802c8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mipi_dsi";</div><div class='add'>+		power-domains = &lt;&amp;ps_disp0_be&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pmp: power-controller@802f0 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802f0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pmp";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pms_sram: power-controller@802f8 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802f8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pms_sram";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pcie_up_af: power-controller@80320 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80320 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pcie_up_af";</div><div class='add'>+		power-domains = &lt;&amp;ps_iomux&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pcie_up: power-controller@80328 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80328 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pcie_up";</div><div class='add'>+		power-domains = &lt;&amp;ps_pcie_up_af&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc_sys: power-controller@80300 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80300 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc_sys";</div><div class='add'>+		power-domains = &lt;&amp;ps_media&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_ans2: power-controller@80308 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80308 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "ans2";</div><div class='add'>+		power-domains = &lt;&amp;ps_iomux&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pcie_down: power-controller@80310 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80310 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pcie_down";</div><div class='add'>+		power-domains = &lt;&amp;ps_iomux&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pcie_down_aux: power-controller@80318 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80318 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pcie_down_aux";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pcie_up_aux: power-controller@80330 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80330 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pcie_up_aux";</div><div class='add'>+		power-domains = &lt;&amp;ps_pcie_up&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pcie_stg0: power-controller@80338 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80338 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pcie_stg0";</div><div class='add'>+		power-domains = &lt;&amp;ps_ans2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pcie_stg0_aux: power-controller@80340 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80340 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pcie_stg0_aux";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pcie_stg1: power-controller@80348 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80348 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pcie_stg1";</div><div class='add'>+		power-domains = &lt;&amp;ps_ans2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pcie_stg1_aux: power-controller@80350 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80350 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pcie_stg1_aux";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sep: power-controller@80400 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80400 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sep";</div><div class='add'>+		apple,always-on; /* Locked on */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_isp_rsts0: power-controller@84000 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x84000 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "isp_rsts0";</div><div class='add'>+		power-domains = &lt;&amp;ps_isp_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_isp_rsts1: power-controller@84008 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x84008 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "isp_rsts1";</div><div class='add'>+		power-domains = &lt;&amp;ps_isp_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_isp_vis: power-controller@84010 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x84010 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "isp_vis";</div><div class='add'>+		power-domains = &lt;&amp;ps_isp_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_isp_be: power-controller@84018 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x84018 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "isp_be";</div><div class='add'>+		power-domains = &lt;&amp;ps_isp_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_isp_pearl: power-controller@84020 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x84020 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "isp_pearl";</div><div class='add'>+		power-domains = &lt;&amp;ps_isp_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc_pipe4: power-controller@88000 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x88000 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc_pipe4";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc_pipe5: power-controller@88008 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x88008 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc_pipe5";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc_me0: power-controller@88010 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x88010 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc_me0";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc_me1: power-controller@88018 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x88018 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc_me1";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pmgr_mini {</div><div class='add'>+	ps_spmi: power-controller@80058 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80058 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spmi";</div><div class='add'>+		apple,always-on; /* Core AON device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_nub_aon: power-controller@80060 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80060 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "nub_aon";</div><div class='add'>+		apple,always-on; /* Core AON device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_smc_fabric: power-controller@80030 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80030 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "smc_fabric";</div><div class='add'>+		apple,always-on; /* Core AON device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_smc_aon: power-controller@80088 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80088 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "smc_aon";</div><div class='add'>+		apple,always-on; /* Core AON device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_debug: power-controller@80050 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80050 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "debug";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_nub_sram: power-controller@801a0 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801a0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "nub_sram";</div><div class='add'>+		apple,always-on; /* Core AON device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_nub_fabric: power-controller@80198 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80198 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "nub_fabric";</div><div class='add'>+		apple,always-on; /* Core AON device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_smc_cpu: power-controller@801a8 {</div><div class='add'>+		compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801a8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "smc_cpu";</div><div class='add'>+		power-domains = &lt;&amp;ps_smc_fabric &amp;ps_smc_aon&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8012-touchbar.dtsi b/arch/arm64/boot/dts/apple/t8012-touchbar.dtsi<br/>new file mode 100644<br/>index 000000000000..fc4a80d0c787<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8012-touchbar.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8012-touchbar.dtsi</a></div><div class='hunk'>@@ -0,0 +1,20 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Common Device Tree for T2 devices with a Touch Bar</div><div class='add'>+ *</div><div class='add'>+ * target-type: J152f, J213, J214k, J215, J223, J680, J780</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2024, Nick Chan &lt;towinchenmi@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	chosen {</div><div class='add'>+		framebuffer0: framebuffer@0 {</div><div class='add'>+			compatible = "apple,simple-framebuffer", "simple-framebuffer";</div><div class='add'>+			reg = &lt;0 0 0 0&gt;; /* To be filled by loader */</div><div class='add'>+			power-domains = &lt;&amp;ps_disp0_fe &amp;ps_disp0_be &amp;ps_mipi_dsi&gt;;</div><div class='add'>+			/* Format properties will be added by loader */</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8012.dtsi b/arch/arm64/boot/dts/apple/t8012.dtsi<br/>new file mode 100644<br/>index 000000000000..e7923814169b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8012.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8012.dtsi</a></div><div class='hunk'>@@ -0,0 +1,302 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple T8012 "T2" SoC</div><div class='add'>+ *</div><div class='add'>+ * Other names: H9M, "Gibraltar"</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2024, Nick Chan &lt;towinchenmi@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/apple-aic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/apple.h&gt;</div><div class='add'>+#include &lt;dt-bindings/spmi/spmi.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	clkref: clock-ref {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+		clock-output-names = "clkref";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@10000 {</div><div class='add'>+			compatible = "apple,hurricane-zephyr";</div><div class='add'>+			reg = &lt;0x0 0x10000&gt;;</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			operating-points-v2 = &lt;&amp;fusion_opp&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache&gt;;</div><div class='add'>+			i-cache-size = &lt;0x10000&gt;; /* P-core */</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;; /* P-core */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@10001 {</div><div class='add'>+			compatible = "apple,hurricane-zephyr";</div><div class='add'>+			reg = &lt;0x0 0x10001&gt;;</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			operating-points-v2 = &lt;&amp;fusion_opp&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache&gt;;</div><div class='add'>+			i-cache-size = &lt;0x10000&gt;; /* P-core */</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;; /* P-core */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_cache: l2-cache {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x300000&gt;; /* P-cluster */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fusion_opp: opp-table {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Apple Fusion Architecture: Hardware big.LITTLE switcher</div><div class='add'>+		 * that use p-state transitions to switch between cores.</div><div class='add'>+		 * Only one type of core can be active at a given time.</div><div class='add'>+		 *</div><div class='add'>+		 * The E-core frequencies are adjusted so performance scales</div><div class='add'>+		 * linearly with reported clock speed.</div><div class='add'>+		 */</div><div class='add'>+</div><div class='add'>+		opp01 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;172000000&gt;; /* 300 MHz, E-core */</div><div class='add'>+			opp-level = &lt;1&gt;;</div><div class='add'>+			clock-latency-ns = &lt;11000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp02 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;230000000&gt;; /* 396 MHz, E-core */</div><div class='add'>+			opp-level = &lt;2&gt;;</div><div class='add'>+			clock-latency-ns = &lt;140000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp03 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;425000000&gt;; /* 732 MHz, E-core */</div><div class='add'>+			opp-level = &lt;3&gt;;</div><div class='add'>+			clock-latency-ns = &lt;110000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp04 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;637000000&gt;; /* 1092 MHz, E-core */</div><div class='add'>+			opp-level = &lt;4&gt;;</div><div class='add'>+			clock-latency-ns = &lt;130000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp05 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;756000000&gt;;</div><div class='add'>+			opp-level = &lt;5&gt;;</div><div class='add'>+			clock-latency-ns = &lt;130000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp06 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1056000000&gt;;</div><div class='add'>+			opp-level = &lt;6&gt;;</div><div class='add'>+			clock-latency-ns = &lt;130000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp07 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1356000000&gt;;</div><div class='add'>+			opp-level = &lt;7&gt;;</div><div class='add'>+			clock-latency-ns = &lt;130000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp08 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1644000000&gt;;</div><div class='add'>+			opp-level = &lt;8&gt;;</div><div class='add'>+			clock-latency-ns = &lt;135000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp09 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1944000000&gt;;</div><div class='add'>+			opp-level = &lt;9&gt;;</div><div class='add'>+			clock-latency-ns = &lt;140000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp10 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2244000000&gt;;</div><div class='add'>+			opp-level = &lt;10&gt;;</div><div class='add'>+			clock-latency-ns = &lt;150000&gt;;</div><div class='add'>+		};</div><div class='add'>+#if 0</div><div class='add'>+		/* Not available until CPU deep sleep is implemented */</div><div class='add'>+		opp11 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2340000000&gt;;</div><div class='add'>+			opp-level = &lt;11&gt;;</div><div class='add'>+			clock-latency-ns = &lt;150000&gt;;</div><div class='add'>+			turbo-mode;</div><div class='add'>+		};</div><div class='add'>+#endif</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		nonposted-mmio;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		cpufreq: performance-controller@202f20000 {</div><div class='add'>+			compatible = "apple,t8010-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";</div><div class='add'>+			reg = &lt;0x2 0x02f20000 0 0x1000&gt;;</div><div class='add'>+			#performance-domain-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		serial0: serial@20a600000 {</div><div class='add'>+			compatible = "apple,s5l-uart";</div><div class='add'>+			reg = &lt;0x2 0x0a600000 0x0 0x4000&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 271 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			/* Use the bootloader-enabled clocks for now. */</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;, &lt;&amp;clkref&gt;;</div><div class='add'>+			clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+			power-domains = &lt;&amp;ps_uart0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmgr: power-management@20e000000 {</div><div class='add'>+			compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			reg = &lt;0x2 0xe000000 0 0x8c000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aic: interrupt-controller@20e100000 {</div><div class='add'>+			compatible = "apple,t8010-aic", "apple,aic";</div><div class='add'>+			reg = &lt;0x2 0x0e100000 0x0 0x100000&gt;;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			power-domains = &lt;&amp;ps_aic&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_ap: pinctrl@20f100000 {</div><div class='add'>+			compatible = "apple,t8010-pinctrl", "apple,pinctrl";</div><div class='add'>+			reg = &lt;0x2 0x0f100000 0x0 0x100000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_gpio&gt;;</div><div class='add'>+</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;pinctrl_ap 0 0 221&gt;;</div><div class='add'>+			apple,npins = &lt;221&gt;;</div><div class='add'>+</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 45 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 46 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 47 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 48 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 49 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 50 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 51 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_aop: pinctrl@2100f0000 {</div><div class='add'>+			compatible = "apple,t8010-pinctrl", "apple,pinctrl";</div><div class='add'>+			reg = &lt;0x2 0x0100f0000 0x0 0x10000&gt;;</div><div class='add'>+</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;pinctrl_aop 0 0 41&gt;;</div><div class='add'>+			apple,npins = &lt;41&gt;;</div><div class='add'>+</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 131 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 132 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 133 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 134 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 135 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 136 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 137 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spmi: spmi@211180700 {</div><div class='add'>+			compatible = "apple,t8012-spmi", "apple,t8103-spmi";</div><div class='add'>+			reg = &lt;0x2 0x11180700 0x0 0x100&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_nub: pinctrl@2111f0000 {</div><div class='add'>+			compatible = "apple,t8010-pinctrl", "apple,pinctrl";</div><div class='add'>+			reg = &lt;0x2 0x111f0000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;pinctrl_nub 0 0 19&gt;;</div><div class='add'>+			apple,npins = &lt;19&gt;;</div><div class='add'>+</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 164 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 165 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 166 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmgr_mini: power-management@211200000 {</div><div class='add'>+			compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			reg = &lt;0x2 0x11200000 0 0x84000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wdt: watchdog@2112b0000 {</div><div class='add'>+			compatible = "apple,t8010-wdt", "apple,wdt";</div><div class='add'>+			reg = &lt;0x2 0x112b0000 0x0 0x4000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 168 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_smc: pinctrl@212024000 {</div><div class='add'>+			compatible = "apple,t8010-pinctrl", "apple,pinctrl";</div><div class='add'>+			reg = &lt;0x2 0x12024000 0x0 0x1000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_smc_cpu&gt;;</div><div class='add'>+</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;pinctrl_smc 0 0 81&gt;;</div><div class='add'>+			apple,npins = &lt;81&gt;;</div><div class='add'>+</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 195 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 196 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 197 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 198 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 199 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 200 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 201 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			/*</div><div class='add'>+			 * SMC is not yet supported and accessing this pinctrl while SMC is</div><div class='add'>+			 * suspended results in a hang.</div><div class='add'>+			 */</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupt-names = "phys", "virt";</div><div class='add'>+		/* Note that T2 doesn't actually have a hypervisor (EL2 is not implemented). */</div><div class='add'>+		interrupts = &lt;AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include "t8012-pmgr.dtsi"</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8015-8.dtsi b/arch/arm64/boot/dts/apple/t8015-8.dtsi<br/>new file mode 100644<br/>index 000000000000..0300ee1a2ffb<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8015-8.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8015-8.dtsi</a></div><div class='hunk'>@@ -0,0 +1,17 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPhone 8 common device tree</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "t8015.dtsi"</div><div class='add'>+#include "t8015-common.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	chassis-type = "handset";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dwi_bl {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8015-8plus.dtsi b/arch/arm64/boot/dts/apple/t8015-8plus.dtsi<br/>new file mode 100644<br/>index 000000000000..ea291a95f028<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8015-8plus.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8015-8plus.dtsi</a></div><div class='hunk'>@@ -0,0 +1,9 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPhone 8 Plus common device tree</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/* The 8 Plus has minor differences like 1 more camera, 1 GiB of RAM more and a bigger display. */</div><div class='add'>+#include "t8015-8.dtsi"</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8015-common.dtsi b/arch/arm64/boot/dts/apple/t8015-common.dtsi<br/>new file mode 100644<br/>index 000000000000..498f58fb9715<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8015-common.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8015-common.dtsi</a></div><div class='hunk'>@@ -0,0 +1,49 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPhone 8, iPhone 8 Plus, iPhone X</div><div class='add'>+ *</div><div class='add'>+ * This file contains parts common to all Apple A11 devices.</div><div class='add'>+ *</div><div class='add'>+ * target-type: D20, D21, D22, D201, D211, D221</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2024, Nick Chan &lt;towinchenmi@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;serial0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		stdout-path = "serial0";</div><div class='add'>+</div><div class='add'>+		framebuffer0: framebuffer@0 {</div><div class='add'>+			compatible = "apple,simple-framebuffer", "simple-framebuffer";</div><div class='add'>+			reg = &lt;0 0 0 0&gt;; /* To be filled by loader */</div><div class='add'>+			power-domains = &lt;&amp;ps_disp0_be &amp;ps_mipi_dsi &amp;ps_disp0_hilo &amp;ps_disp0_ppp&gt;;</div><div class='add'>+			/* Format properties will be added by loader */</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@800000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x8 0 0 0&gt;; /* To be filled by loader */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		/* To be filled by loader */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;serial0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8015-d20.dts b/arch/arm64/boot/dts/apple/t8015-d20.dts<br/>new file mode 100644<br/>index 000000000000..35d79e2ceebc<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8015-d20.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8015-d20.dts</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPhone 8 (Global), D20 iPhone10,1 (A1863/A1906/A1907)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t8015-8.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,d20", "apple,t8015", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPhone 8 (Global)";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8015-d201.dts b/arch/arm64/boot/dts/apple/t8015-d201.dts<br/>new file mode 100644<br/>index 000000000000..31e0947fee70<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8015-d201.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8015-d201.dts</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPhone 8 (GSM), D20 iPhone10,4 (A1905)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t8015-8.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,d201", "apple,t8015", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPhone 8 (GSM)";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8015-d21.dts b/arch/arm64/boot/dts/apple/t8015-d21.dts<br/>new file mode 100644<br/>index 000000000000..a902ba7f1133<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8015-d21.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8015-d21.dts</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPhone 8 Plus (Global), D21 iPhone10,2 (A1864/A1897/A1898)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t8015-8plus.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,d21", "apple,t8015", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPhone 8 Plus (Global)";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8015-d211.dts b/arch/arm64/boot/dts/apple/t8015-d211.dts<br/>new file mode 100644<br/>index 000000000000..3b3f886c0c09<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8015-d211.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8015-d211.dts</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPhone 8 Plus (GSM), D211 iPhone10,5 (A1899)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t8015-8plus.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,d211", "apple,t8015", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPhone 8 Plus (GSM)";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8015-d22.dts b/arch/arm64/boot/dts/apple/t8015-d22.dts<br/>new file mode 100644<br/>index 000000000000..5a7a6092c2d0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8015-d22.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8015-d22.dts</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPhone X (Global), D22, iPhone10,3 (A1865)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t8015-x.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,d22", "apple,t8015", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPhone X (Global)";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8015-d221.dts b/arch/arm64/boot/dts/apple/t8015-d221.dts<br/>new file mode 100644<br/>index 000000000000..dd920c945bd6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8015-d221.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8015-d221.dts</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPhone X (GSM), D221, iPhone10,6 (A1901)</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t8015-x.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,d221", "apple,t8015", "apple,arm-platform";</div><div class='add'>+	model = "Apple iPhone X (GSM)";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8015-pmgr.dtsi b/arch/arm64/boot/dts/apple/t8015-pmgr.dtsi<br/>new file mode 100644<br/>index 000000000000..1d8da9c7863e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8015-pmgr.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8015-pmgr.dtsi</a></div><div class='hunk'>@@ -0,0 +1,932 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * PMGR Power domains for the Apple T8015 "A11" SoC</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2024, Nick Chan &lt;towinchenmi@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;pmgr {</div><div class='add'>+	ps_cpu0: power-controller@80000 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80000 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "cpu0";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_cpu1: power-controller@80008 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80008 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "cpu1";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_cpu2: power-controller@80010 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80010 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "cpu2";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_cpu3: power-controller@80018 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80018 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "cpu3";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_cpu4: power-controller@80020 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80020 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "cpu4";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_cpu5: power-controller@80028 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80028 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "cpu5";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_cpm: power-controller@80040 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80040 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "cpm";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sio_busif: power-controller@80158 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80158 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sio_busif";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sio_p: power-controller@80160 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80160 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sio_p";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_busif&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sbr: power-controller@80100 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80100 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sbr";</div><div class='add'>+		apple,always-on; /* Apple fabric, critical block */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_aic: power-controller@80108 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80108 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "aic";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dwi: power-controller@80110 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80110 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dwi";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_gpio: power-controller@80118 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80118 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "gpio";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pms: power-controller@80120 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80120 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pms";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pcie_ref: power-controller@80148 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80148 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pcie_ref";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca0: power-controller@80170 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80170 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca1: power-controller@80178 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80178 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca1";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca2: power-controller@80180 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80180 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca2";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca3: power-controller@80188 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80188 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca3";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca4: power-controller@80190 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80190 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca4";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pwm0: power-controller@801a0 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801a0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pwm0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c0: power-controller@801a8 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801a8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c1: power-controller@801b0 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801b0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c1";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c2: power-controller@801b8 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801b8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c2";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c3: power-controller@801c0 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801c0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c3";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi0: power-controller@801c8 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801c8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi1: power-controller@801d0 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801d0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi1";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi2: power-controller@801d8 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801d8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi2";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi3: power-controller@801e0 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801e0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi3";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart0: power-controller@801e8 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801e8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart1: power-controller@801f0 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801f0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart1";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart2: power-controller@801f8 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x801f8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart2";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sio: power-controller@80168 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80168 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sio";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_hsicphy: power-controller@80128 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80128 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "hsicphy";</div><div class='add'>+		power-domains = &lt;&amp;ps_usb2host1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_ispsens0: power-controller@80130 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80130 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "ispsens0";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_ispsens1: power-controller@80138 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80138 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "ispsens1";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_ispsens2: power-controller@80140 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80140 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "ispsens2";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca5: power-controller@80198 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80198 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca5";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usb: power-controller@80270 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80270 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usb";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usbctlreg: power-controller@80278 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80278 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usbctlreg";</div><div class='add'>+		power-domains = &lt;&amp;ps_usb&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usb2host0: power-controller@80280 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80280 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usb2host0";</div><div class='add'>+		power-domains = &lt;&amp;ps_usbctlreg&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usb2host1: power-controller@80290 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80290 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usb2host1";</div><div class='add'>+		power-domains = &lt;&amp;ps_usbctlreg&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_rtmux: power-controller@802b0 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802b0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "rtmux";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_media: power-controller@802f0 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802f0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "media";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_jpg: power-controller@802f8 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802f8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "jpg";</div><div class='add'>+		power-domains = &lt;&amp;ps_media&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_disp0_fe: power-controller@802b8 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802b8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "disp0_fe";</div><div class='add'>+		power-domains = &lt;&amp;ps_rtmux&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_disp0_be: power-controller@802c0 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802c0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "disp0_be";</div><div class='add'>+		power-domains = &lt;&amp;ps_disp0_fe&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_disp0_gp: power-controller@802c8 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802c8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "disp0_gp";</div><div class='add'>+		power-domains = &lt;&amp;ps_disp0_be&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart3: power-controller@80200 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80200 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart3";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart4: power-controller@80208 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80208 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart4";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart5: power-controller@80210 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80210 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart5";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart6: power-controller@80218 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80218 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart6";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart7: power-controller@80220 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80220 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart7";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart8: power-controller@80228 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80228 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart8";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_hfd0: power-controller@80238 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80238 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "hfd0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mcc: power-controller@80248 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80248 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mcc";</div><div class='add'>+		apple,always-on; /* Memory cache controller */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs0: power-controller@80250 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80250 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs0";</div><div class='add'>+		apple,always-on; /* LPDDR4X interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs1: power-controller@80258 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80258 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs1";</div><div class='add'>+		apple,always-on; /* LPDDR4X interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs2: power-controller@80260 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80260 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs2";</div><div class='add'>+		apple,always-on; /* LPDDR4X interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs3: power-controller@80268 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80268 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs3";</div><div class='add'>+		apple,always-on; /* LPDDR4X interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usb2host0_ohci: power-controller@80288 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80288 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usb2host0_ohci";</div><div class='add'>+		power-domains = &lt;&amp;ps_usb2host0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_usb2dev: power-controller@80298 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80298 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "usb2dev";</div><div class='add'>+		power-domains = &lt;&amp;ps_usbctlreg&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_smx: power-controller@802a0 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802a0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "smx";</div><div class='add'>+		apple,always-on; /* Apple fabric, critical block */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sf: power-controller@802a8 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802a8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sf";</div><div class='add'>+		apple,always-on; /* Apple fabric, critical block */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mipi_dsi: power-controller@802d8 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802d8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mipi_dsi";</div><div class='add'>+		power-domains = &lt;&amp;ps_rtmux&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dp: power-controller@802e0 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802e0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dp";</div><div class='add'>+		power-domains = &lt;&amp;ps_disp0_be&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dpa: power-controller@80230 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80230 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dpa";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_disp0_be_2x: power-controller@802d0 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x802d0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "disp0_be_2x";</div><div class='add'>+		power-domains = &lt;&amp;ps_disp0_be&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_isp_sys: power-controller@80350 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80350 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "isp_sys";</div><div class='add'>+		power-domains = &lt;&amp;ps_rtmux&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_msr: power-controller@80300 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80300 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "msr";</div><div class='add'>+		power-domains = &lt;&amp;ps_media&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc_sys: power-controller@80398 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80398 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc_sys";</div><div class='add'>+		power-domains = &lt;&amp;ps_media&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pmp: power-controller@80308 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80308 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pmp";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pms_sram: power-controller@80310 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80310 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pms_sram";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pcie: power-controller@80318 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80318 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pcie";</div><div class='add'>+		power-domains = &lt;&amp;ps_pcie_aux&gt;, &lt;&amp;ps_pcie_direct&gt;, &lt;&amp;ps_pcie_ref&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pcie_aux: power-controller@80320 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80320 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pcie_aux";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_vdec0: power-controller@80388 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80388 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "vdec0";</div><div class='add'>+		power-domains = &lt;&amp;ps_media&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_gfx: power-controller@80338 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80338 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "gfx";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_ans2: power-controller@80328 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80328 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "ans2";</div><div class='add'>+		apple,always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pcie_direct: power-controller@80330 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80330 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pcie_direct";</div><div class='add'>+		apple,always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_avd_sys: power-controller@803a8 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x803a8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "avd_sys";</div><div class='add'>+		power-domains = &lt;&amp;ps_media&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sep: power-controller@80400 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80400 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sep";</div><div class='add'>+		apple,always-on; /* Locked on */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_disp0_gp0: power-controller@80830 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80830 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "disp0_gp0";</div><div class='add'>+		power-domains = &lt;&amp;ps_disp0_gp&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_disp0_gp1: power-controller@80838 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80838 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "disp0_gp1";</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_disp0_ppp: power-controller@80840 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80840 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "disp0_ppp";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_disp0_hilo: power-controller@80848 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80848 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "disp0_hilo";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_isp_rsts0: power-controller@84000 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x84000 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "isp_rsts0";</div><div class='add'>+		power-domains = &lt;&amp;ps_isp_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_isp_rsts1: power-controller@84008 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x84008 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "isp_rsts1";</div><div class='add'>+		power-domains = &lt;&amp;ps_isp_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_isp_vis: power-controller@84010 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x84010 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "isp_vis";</div><div class='add'>+		power-domains = &lt;&amp;ps_isp_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_isp_be: power-controller@84018 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x84018 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "isp_be";</div><div class='add'>+		power-domains = &lt;&amp;ps_isp_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_isp_pearl: power-controller@84020 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x84020 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "isp_pearl";</div><div class='add'>+		power-domains = &lt;&amp;ps_isp_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dprx: power-controller@84028 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x84028 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dprx";</div><div class='add'>+		power-domains = &lt;&amp;ps_isp_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_isp_cnv: power-controller@84030 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x84030 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "isp_cnv";</div><div class='add'>+		power-domains = &lt;&amp;ps_isp_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc_dma: power-controller@88000 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x88000 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc_dma";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc_pipe4: power-controller@88010 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x88010 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc_pipe4";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc_pipe5: power-controller@88018 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x88018 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc_pipe5";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc_me0: power-controller@88020 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x88020 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc_me0";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc_me1: power-controller@88028 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x88028 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc_me1";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pmgr_mini {</div><div class='add'>+	ps_aop_base: power-controller@80008 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80008 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "aop_base";</div><div class='add'>+		power-domains = &lt;&amp;ps_aop_cpu &amp;ps_aop_filter&gt;;</div><div class='add'>+		apple,always-on; /* Always on processor */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_debug: power-controller@80050 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80050 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "debug";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_aop_cpu: power-controller@80020 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80020 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "aop_cpu";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_aop_filter: power-controller@80000 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80000 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "aop_filter";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spmi: power-controller@80058 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80058 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spmi";</div><div class='add'>+		apple,always-on; /* System Power Management Interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_smc_i2cm1: power-controller@800a8 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x800a8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "smc_i2cm1";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_smc_fabric: power-controller@80030 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80030 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "smc_fabric";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_smc_cpu: power-controller@80140 {</div><div class='add'>+		compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80140 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "smc_cpu";</div><div class='add'>+		power-domains = &lt;&amp;ps_smc_fabric &amp;ps_smc_i2cm1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8015-x.dtsi b/arch/arm64/boot/dts/apple/t8015-x.dtsi<br/>new file mode 100644<br/>index 000000000000..41134ed40b89<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8015-x.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8015-x.dtsi</a></div><div class='hunk'>@@ -0,0 +1,13 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iPhone X common device tree</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "t8015.dtsi"</div><div class='add'>+#include "t8015-common.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	chassis-type = "handset";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8015.dtsi b/arch/arm64/boot/dts/apple/t8015.dtsi<br/>new file mode 100644<br/>index 000000000000..586d3cf1f375<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8015.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8015.dtsi</a></div><div class='hunk'>@@ -0,0 +1,535 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple T8015 "A11" SoC</div><div class='add'>+ *</div><div class='add'>+ * Other names: H10, "Skye"</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2022, Konrad Dybcio &lt;konradybcio@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/apple-aic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/apple.h&gt;</div><div class='add'>+#include &lt;dt-bindings/spmi/spmi.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	clkref: clock-ref {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+		clock-output-names = "clkref";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu-map {</div><div class='add'>+			cluster0 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu_e0&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu_e1&gt;;</div><div class='add'>+				};</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu_e2&gt;;</div><div class='add'>+				};</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu_e3&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cluster1 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu_p0&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu_p1&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_e0: cpu@0 {</div><div class='add'>+			compatible = "apple,mistral";</div><div class='add'>+			reg = &lt;0x0 0x0&gt;;</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_e&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;mistral_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;633&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_0&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_e1: cpu@1 {</div><div class='add'>+			compatible = "apple,mistral";</div><div class='add'>+			reg = &lt;0x0 0x1&gt;;</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_e&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;mistral_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;633&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_0&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_e2: cpu@2 {</div><div class='add'>+			compatible = "apple,mistral";</div><div class='add'>+			reg = &lt;0x0 0x2&gt;;</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_e&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;mistral_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;633&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_0&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_e3: cpu@3 {</div><div class='add'>+			compatible = "apple,mistral";</div><div class='add'>+			reg = &lt;0x0 0x3&gt;;</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_e&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;mistral_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;633&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_0&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_p0: cpu@10004 {</div><div class='add'>+			compatible = "apple,monsoon";</div><div class='add'>+			reg = &lt;0x0 0x10004&gt;;</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_p&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;monsoon_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_1&gt;;</div><div class='add'>+			i-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_p1: cpu@10005 {</div><div class='add'>+			compatible = "apple,monsoon";</div><div class='add'>+			reg = &lt;0x0 0x10005&gt;;</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_p&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;monsoon_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_1&gt;;</div><div class='add'>+			i-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_cache_0: l2-cache-0 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x100000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_cache_1: l2-cache-1 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x800000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mistral_opp: opp-table-0 {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		opp01 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;300000000&gt;;</div><div class='add'>+			opp-level = &lt;1&gt;;</div><div class='add'>+			clock-latency-ns = &lt;1800&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp02 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;453000000&gt;;</div><div class='add'>+			opp-level = &lt;2&gt;;</div><div class='add'>+			clock-latency-ns = &lt;140000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp03 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;672000000&gt;;</div><div class='add'>+			opp-level = &lt;3&gt;;</div><div class='add'>+			clock-latency-ns = &lt;105000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp04 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;972000000&gt;;</div><div class='add'>+			opp-level = &lt;4&gt;;</div><div class='add'>+			clock-latency-ns = &lt;115000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp05 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1272000000&gt;;</div><div class='add'>+			opp-level = &lt;5&gt;;</div><div class='add'>+			clock-latency-ns = &lt;125000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp06 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1572000000&gt;;</div><div class='add'>+			opp-level = &lt;6&gt;;</div><div class='add'>+			clock-latency-ns = &lt;135000&gt;;</div><div class='add'>+		};</div><div class='add'>+#if 0</div><div class='add'>+		/* Not available until CPU deep sleep is implemented */</div><div class='add'>+		opp07 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1680000000&gt;;</div><div class='add'>+			opp-level = &lt;7&gt;;</div><div class='add'>+			clock-latency-ns = &lt;135000&gt;;</div><div class='add'>+			turbo-mode;</div><div class='add'>+		};</div><div class='add'>+#endif</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	monsoon_opp: opp-table-1 {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		opp01 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;300000000&gt;;</div><div class='add'>+			opp-level = &lt;1&gt;;</div><div class='add'>+			clock-latency-ns = &lt;1400&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp02 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;453000000&gt;;</div><div class='add'>+			opp-level = &lt;2&gt;;</div><div class='add'>+			clock-latency-ns = &lt;140000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp03 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;853000000&gt;;</div><div class='add'>+			opp-level = &lt;3&gt;;</div><div class='add'>+			clock-latency-ns = &lt;110000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp04 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1332000000&gt;;</div><div class='add'>+			opp-level = &lt;4&gt;;</div><div class='add'>+			clock-latency-ns = &lt;110000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp05 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1812000000&gt;;</div><div class='add'>+			opp-level = &lt;5&gt;;</div><div class='add'>+			clock-latency-ns = &lt;125000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp06 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2064000000&gt;;</div><div class='add'>+			opp-level = &lt;6&gt;;</div><div class='add'>+			clock-latency-ns = &lt;130000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp07 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2304000000&gt;;</div><div class='add'>+			opp-level = &lt;7&gt;;</div><div class='add'>+			clock-latency-ns = &lt;140000&gt;;</div><div class='add'>+		};</div><div class='add'>+#if 0</div><div class='add'>+		/* Not available until CPU deep sleep is implemented */</div><div class='add'>+		opp08 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2376000000&gt;;</div><div class='add'>+			opp-level = &lt;8&gt;;</div><div class='add'>+			clock-latency-ns = &lt;140000&gt;;</div><div class='add'>+			turbo-mode;</div><div class='add'>+		};</div><div class='add'>+#endif</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		nonposted-mmio;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		cpufreq_e: performance-controller@208e20000 {</div><div class='add'>+			compatible = "apple,t8015-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";</div><div class='add'>+			reg = &lt;0x2 0x08e20000 0 0x1000&gt;;</div><div class='add'>+			#performance-domain-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpufreq_p: performance-controller@208ea0000 {</div><div class='add'>+			compatible = "apple,t8015-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";</div><div class='add'>+			reg = &lt;0x2 0x08ea0000 0 0x1000&gt;;</div><div class='add'>+			#performance-domain-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c0: i2c@22e200000 {</div><div class='add'>+			compatible = "apple,t8015-i2c", "apple,i2c";</div><div class='add'>+			reg = &lt;0x2 0x2e200000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 304 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c0_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			power-domains = &lt;&amp;ps_i2c0&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c1: i2c@22e204000 {</div><div class='add'>+			compatible = "apple,t8015-i2c", "apple,i2c";</div><div class='add'>+			reg = &lt;0x2 0x2e204000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 305 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c1_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			power-domains = &lt;&amp;ps_i2c1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c2: i2c@22e208000 {</div><div class='add'>+			compatible = "apple,t8015-i2c", "apple,i2c";</div><div class='add'>+			reg = &lt;0x2 0x2e208000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 306 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c2_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			power-domains = &lt;&amp;ps_i2c2&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c3: i2c@22e20c000 {</div><div class='add'>+			compatible = "apple,t8015-i2c", "apple,i2c";</div><div class='add'>+			reg = &lt;0x2 0x2e20c000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 307 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c3_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			power-domains = &lt;&amp;ps_i2c3&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		serial0: serial@22e600000 {</div><div class='add'>+			compatible = "apple,s5l-uart";</div><div class='add'>+			reg = &lt;0x2 0x2e600000 0x0 0x4000&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 282 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			/* Use the bootloader-enabled clocks for now. */</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;, &lt;&amp;clkref&gt;;</div><div class='add'>+			clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+			power-domains = &lt;&amp;ps_uart0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aic: interrupt-controller@232100000 {</div><div class='add'>+			compatible = "apple,t8015-aic", "apple,aic";</div><div class='add'>+			reg = &lt;0x2 0x32100000 0x0 0x8000&gt;;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			power-domains = &lt;&amp;ps_aic&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmgr: power-management@232000000 {</div><div class='add'>+			compatible = "apple,t8015-pmgr", "apple,pmgr", "syscon", "simple-mfd";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			reg = &lt;0x2 0x32000000 0 0x8c000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dwi_bl: backlight@232200080 {</div><div class='add'>+			compatible = "apple,t8015-dwi-bl", "apple,dwi-bl";</div><div class='add'>+			reg = &lt;0x2 0x32200080 0x0 0x8&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_dwi&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_ap: pinctrl@233100000 {</div><div class='add'>+			compatible = "apple,t8015-pinctrl", "apple,pinctrl";</div><div class='add'>+			reg = &lt;0x2 0x33100000 0x0 0x1000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_gpio&gt;;</div><div class='add'>+</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;pinctrl_ap 0 0 223&gt;;</div><div class='add'>+			apple,npins = &lt;223&gt;;</div><div class='add'>+</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 50 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 51 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 52 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 53 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 54 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 55 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 56 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			i2c0_pins: i2c0-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(73, 1)&gt;,</div><div class='add'>+					 &lt;APPLE_PINMUX(72, 1)&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c1_pins: i2c1-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(182, 1)&gt;,</div><div class='add'>+					 &lt;APPLE_PINMUX(181, 1)&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c2_pins: i2c2-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(4, 1)&gt;,</div><div class='add'>+					 &lt;APPLE_PINMUX(3, 1)&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c3_pins: i2c3-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(184, 1)&gt;,</div><div class='add'>+					 &lt;APPLE_PINMUX(183, 1)&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_aop: pinctrl@2340f0000 {</div><div class='add'>+			compatible = "apple,t8015-pinctrl", "apple,pinctrl";</div><div class='add'>+			reg = &lt;0x2 0x340f0000 0x0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;pinctrl_aop 0 0 49&gt;;</div><div class='add'>+			apple,npins = &lt;49&gt;;</div><div class='add'>+</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 135 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 136 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 137 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 138 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 139 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 140 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 141 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spmi: spmi@235180700 {</div><div class='add'>+			compatible = "apple,t8015-spmi", "apple,t8103-spmi";</div><div class='add'>+			reg = &lt;0x2 0x35180700 0x0 0x100&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_nub: pinctrl@2351f0000 {</div><div class='add'>+			compatible = "apple,t8015-pinctrl", "apple,pinctrl";</div><div class='add'>+			reg = &lt;0x2 0x351f0000 0x0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;pinctrl_nub 0 0 8&gt;;</div><div class='add'>+			apple,npins = &lt;8&gt;;</div><div class='add'>+</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 168 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 169 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 170 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmgr_mini: power-management@235200000 {</div><div class='add'>+			compatible = "apple,t8015-pmgr", "apple,pmgr", "syscon", "simple-mfd";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			reg = &lt;0x2 0x35200000 0 0x84000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wdt: watchdog@2352b0000 {</div><div class='add'>+			compatible = "apple,t8015-wdt", "apple,wdt";</div><div class='add'>+			reg = &lt;0x2 0x352b0000 0x0 0x4000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 172 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_smc: pinctrl@236024000 {</div><div class='add'>+			compatible = "apple,t8015-pinctrl", "apple,pinctrl";</div><div class='add'>+			reg = &lt;0x2 0x36024000 0x0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;pinctrl_smc 0 0 6&gt;;</div><div class='add'>+			apple,npins = &lt;6&gt;;</div><div class='add'>+</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 199 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 200 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 201 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 202 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 203 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 204 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 205 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			/*</div><div class='add'>+			 * SMC is not yet supported and accessing this pinctrl while SMC is</div><div class='add'>+			 * suspended results in a hang.</div><div class='add'>+			 */</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ans_mbox: mbox@257008000 {</div><div class='add'>+			compatible = "apple,t8015-asc-mailbox";</div><div class='add'>+			reg = &lt;0x2 0x57008000 0x0 0x4000&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 265 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ 266 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ 267 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ 268 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "send-empty", "send-not-empty",</div><div class='add'>+				"recv-empty", "recv-not-empty";</div><div class='add'>+			#mbox-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_ans2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sart: iommu@259c50000 {</div><div class='add'>+			compatible = "apple,t8015-sart";</div><div class='add'>+			reg = &lt;0x2 0x59c50000 0x0 0x10000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_ans2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nvme@259cc0000 {</div><div class='add'>+			compatible = "apple,t8015-nvme-ans2";</div><div class='add'>+			reg = &lt;0x2 0x59cc0000 0x0 0x40000&gt;,</div><div class='add'>+				&lt;0x2 0x59d20000 0x0 0x2000&gt;;</div><div class='add'>+			reg-names = "nvme", "ans";</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 270 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			mboxes = &lt;&amp;ans_mbox&gt;;</div><div class='add'>+			apple,sart = &lt;&amp;sart&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_ans2&gt;, &lt;&amp;ps_pcie&gt;;</div><div class='add'>+			power-domain-names = "ans", "apcie0";</div><div class='add'>+			resets = &lt;&amp;ps_ans2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupt-names = "phys", "virt";</div><div class='add'>+		/* Note that A11 doesn't actually have a hypervisor (EL2 is not implemented). */</div><div class='add'>+		interrupts = &lt;AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include "t8015-pmgr.dtsi"</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8103-j274.dts b/arch/arm64/boot/dts/apple/t8103-j274.dts<br/>new file mode 100644<br/>index 000000000000..1c3e37f86d46<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8103-j274.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8103-j274.dts</a></div><div class='hunk'>@@ -0,0 +1,63 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple Mac mini (M1, 2020)</div><div class='add'>+ *</div><div class='add'>+ * target-type: J274</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t8103.dtsi"</div><div class='add'>+#include "t8103-jxxx.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j274", "apple,t8103", "apple,arm-platform";</div><div class='add'>+	model = "Apple Mac mini (M1, 2020)";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;ethernet0;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;bluetooth0 {</div><div class='add'>+	brcm,board-type = "apple,atlantisb";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wifi0 {</div><div class='add'>+	brcm,board-type = "apple,atlantisb";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Force the bus number assignments so that we can declare some of the</div><div class='add'>+ * on-board devices and properties that are populated by the bootloader</div><div class='add'>+ * (such as MAC addresses).</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;port01 {</div><div class='add'>+	bus-range = &lt;2 2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;port02 {</div><div class='add'>+	bus-range = &lt;3 3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+	ethernet0: ethernet@0,0 {</div><div class='add'>+		reg = &lt;0x30000 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+		/* To be filled by the loader */</div><div class='add'>+		local-mac-address = [00 10 18 00 00 00];</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0_dart_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0_dart_2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8103-j293.dts b/arch/arm64/boot/dts/apple/t8103-j293.dts<br/>new file mode 100644<br/>index 000000000000..5b3c42e9f0e6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8103-j293.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8103-j293.dts</a></div><div class='hunk'>@@ -0,0 +1,121 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple MacBook Pro (13-inch, M1, 2020)</div><div class='add'>+ *</div><div class='add'>+ * target-type: J293</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t8103.dtsi"</div><div class='add'>+#include "t8103-jxxx.dtsi"</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j293", "apple,t8103", "apple,arm-platform";</div><div class='add'>+	model = "Apple MacBook Pro (13-inch, M1, 2020)";</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * All of those are used by the bootloader to pass calibration</div><div class='add'>+	 * blobs and other device-specific properties</div><div class='add'>+	 */</div><div class='add'>+	aliases {</div><div class='add'>+		touchbar0 = &amp;touchbar0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	led-controller {</div><div class='add'>+		compatible = "pwm-leds";</div><div class='add'>+		led-0 {</div><div class='add'>+			pwms = &lt;&amp;fpwm1 0 40000&gt;;</div><div class='add'>+			label = "kbd_backlight";</div><div class='add'>+			function = LED_FUNCTION_KBD_BACKLIGHT;</div><div class='add'>+			color = &lt;LED_COLOR_ID_WHITE&gt;;</div><div class='add'>+			max-brightness = &lt;255&gt;;</div><div class='add'>+			default-state = "keep";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;bluetooth0 {</div><div class='add'>+	brcm,board-type = "apple,honshu";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wifi0 {</div><div class='add'>+	brcm,board-type = "apple,honshu";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fpwm1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi0 {</div><div class='add'>+	cs-gpios = &lt;&amp;pinctrl_ap 109 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	touchbar0: touchbar@0 {</div><div class='add'>+		compatible = "apple,j293-touchbar";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;11500000&gt;;</div><div class='add'>+		spi-cs-setup-delay-ns = &lt;2000&gt;;</div><div class='add'>+		spi-cs-hold-delay-ns = &lt;2000&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pinctrl_ap 139 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pinctrl_ap 194 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		firmware-name = "apple/dfrmtfw-j293.bin";</div><div class='add'>+		touchscreen-size-x = &lt;23045&gt;;</div><div class='add'>+		touchscreen-size-y = &lt;640&gt;;</div><div class='add'>+		touchscreen-inverted-y;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * The driver depends on boot loader initialized state which resets when this</div><div class='add'>+ * power-domain is powered off. This happens on suspend or when the driver is</div><div class='add'>+ * missing during boot. Mark the domain as always on until the driver can</div><div class='add'>+ * handle this.</div><div class='add'>+ */</div><div class='add'>+&amp;ps_dispdfr_be {</div><div class='add'>+	apple,always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;display_dfr {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dfr_mipi_out {</div><div class='add'>+	dfr_mipi_out_panel: endpoint@0 {</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		remote-endpoint = &lt;&amp;dfr_panel_in&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;displaydfr_mipi {</div><div class='add'>+	status = "okay";</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	dfr_panel: panel@0 {</div><div class='add'>+		compatible = "apple,j293-summit", "apple,summit";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		max-brightness = &lt;255&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			dfr_panel_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;dfr_mipi_out_panel&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;displaydfr_dart {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8103-j313.dts b/arch/arm64/boot/dts/apple/t8103-j313.dts<br/>new file mode 100644<br/>index 000000000000..97a4344d8dca<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8103-j313.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8103-j313.dts</a></div><div class='hunk'>@@ -0,0 +1,43 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple MacBook Air (M1, 2020)</div><div class='add'>+ *</div><div class='add'>+ * target-type: J313</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t8103.dtsi"</div><div class='add'>+#include "t8103-jxxx.dtsi"</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j313", "apple,t8103", "apple,arm-platform";</div><div class='add'>+	model = "Apple MacBook Air (M1, 2020)";</div><div class='add'>+</div><div class='add'>+	led-controller {</div><div class='add'>+		compatible = "pwm-leds";</div><div class='add'>+		led-0 {</div><div class='add'>+			pwms = &lt;&amp;fpwm1 0 40000&gt;;</div><div class='add'>+			label = "kbd_backlight";</div><div class='add'>+			function = LED_FUNCTION_KBD_BACKLIGHT;</div><div class='add'>+			color = &lt;LED_COLOR_ID_WHITE&gt;;</div><div class='add'>+			max-brightness = &lt;255&gt;;</div><div class='add'>+			default-state = "keep";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;bluetooth0 {</div><div class='add'>+	brcm,board-type = "apple,shikoku";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wifi0 {</div><div class='add'>+	brcm,board-type = "apple,shikoku";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fpwm1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8103-j456.dts b/arch/arm64/boot/dts/apple/t8103-j456.dts<br/>new file mode 100644<br/>index 000000000000..58c8e43789b4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8103-j456.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8103-j456.dts</a></div><div class='hunk'>@@ -0,0 +1,77 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iMac (24-inch, 4x USB-C, M1, 2020)</div><div class='add'>+ *</div><div class='add'>+ * target-type: J456</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t8103.dtsi"</div><div class='add'>+#include "t8103-jxxx.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j456", "apple,t8103", "apple,arm-platform";</div><div class='add'>+	model = "Apple iMac (24-inch, 4x USB-C, M1, 2021)";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;ethernet0;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;bluetooth0 {</div><div class='add'>+	brcm,board-type = "apple,capri";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wifi0 {</div><div class='add'>+	brcm,board-type = "apple,capri";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	hpm2: usb-pd@3b {</div><div class='add'>+		compatible = "apple,cd321x";</div><div class='add'>+		reg = &lt;0x3b&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;pinctrl_ap&gt;;</div><div class='add'>+		interrupts = &lt;106 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupt-names = "irq";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hpm3: usb-pd@3c {</div><div class='add'>+		compatible = "apple,cd321x";</div><div class='add'>+		reg = &lt;0x3c&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;pinctrl_ap&gt;;</div><div class='add'>+		interrupts = &lt;106 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupt-names = "irq";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Force the bus number assignments so that we can declare some of the</div><div class='add'>+ * on-board devices and properties that are populated by the bootloader</div><div class='add'>+ * (such as MAC addresses).</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;port01 {</div><div class='add'>+	bus-range = &lt;2 2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;port02 {</div><div class='add'>+	bus-range = &lt;3 3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+	ethernet0: ethernet@0,0 {</div><div class='add'>+		reg = &lt;0x30000 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+		/* To be filled by the loader */</div><div class='add'>+		local-mac-address = [00 10 18 00 00 00];</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0_dart_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0_dart_2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8103-j457.dts b/arch/arm64/boot/dts/apple/t8103-j457.dts<br/>new file mode 100644<br/>index 000000000000..7089ccf3ce55<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8103-j457.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8103-j457.dts</a></div><div class='hunk'>@@ -0,0 +1,58 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple iMac (24-inch, 2x USB-C, M1, 2020)</div><div class='add'>+ *</div><div class='add'>+ * target-type: J457</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t8103.dtsi"</div><div class='add'>+#include "t8103-jxxx.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j457", "apple,t8103", "apple,arm-platform";</div><div class='add'>+	model = "Apple iMac (24-inch, 2x USB-C, M1, 2021)";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;ethernet0;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Adjust pcie0's iommu-map to account for the disabled port01.</div><div class='add'>+ */</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	iommu-map = &lt;0x100 &amp;pcie0_dart_0 1 1&gt;,</div><div class='add'>+			&lt;0x200 &amp;pcie0_dart_2 1 1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;bluetooth0 {</div><div class='add'>+	brcm,board-type = "apple,santorini";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wifi0 {</div><div class='add'>+	brcm,board-type = "apple,santorini";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Force the bus number assignments so that we can declare some of the</div><div class='add'>+ * on-board devices and properties that are populated by the bootloader</div><div class='add'>+ * (such as MAC addresses).</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;port02 {</div><div class='add'>+	bus-range = &lt;2 2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+	ethernet0: ethernet@0,0 {</div><div class='add'>+		reg = &lt;0x20000 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+		/* To be filled by the loader */</div><div class='add'>+		local-mac-address = [00 10 18 00 00 00];</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0_dart_2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi b/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi<br/>new file mode 100644<br/>index 000000000000..0c8206156bfe<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8103-jxxx.dtsi</a></div><div class='hunk'>@@ -0,0 +1,94 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple M1 Mac mini, MacBook Air/Pro, iMac 24" (M1, 2020/2021)</div><div class='add'>+ *</div><div class='add'>+ * This file contains parts common to all Apple M1 devices using the t8103.</div><div class='add'>+ *</div><div class='add'>+ * target-type: J274, J293, J313, J456, J457</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		bluetooth0 = &amp;bluetooth0;</div><div class='add'>+		serial0 = &amp;serial0;</div><div class='add'>+		serial2 = &amp;serial2;</div><div class='add'>+		wifi0 = &amp;wifi0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		stdout-path = "serial0";</div><div class='add'>+</div><div class='add'>+		framebuffer0: framebuffer@0 {</div><div class='add'>+			compatible = "apple,simple-framebuffer", "simple-framebuffer";</div><div class='add'>+			reg = &lt;0 0 0 0&gt;; /* To be filled by loader */</div><div class='add'>+			/* Format properties will be added by loader */</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@800000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x8 0 0x2 0&gt;; /* To be filled by loader */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;serial0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;serial2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	hpm0: usb-pd@38 {</div><div class='add'>+		compatible = "apple,cd321x";</div><div class='add'>+		reg = &lt;0x38&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;pinctrl_ap&gt;;</div><div class='add'>+		interrupts = &lt;106 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupt-names = "irq";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hpm1: usb-pd@3f {</div><div class='add'>+		compatible = "apple,cd321x";</div><div class='add'>+		reg = &lt;0x3f&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;pinctrl_ap&gt;;</div><div class='add'>+		interrupts = &lt;106 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupt-names = "irq";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Force the bus number assignments so that we can declare some of the</div><div class='add'>+ * on-board devices and properties that are populated by the bootloader</div><div class='add'>+ * (such as MAC addresses).</div><div class='add'>+ */</div><div class='add'>+&amp;port00 {</div><div class='add'>+	bus-range = &lt;1 1&gt;;</div><div class='add'>+	wifi0: wifi@0,0 {</div><div class='add'>+		compatible = "pci14e4,4425";</div><div class='add'>+		reg = &lt;0x10000 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+		/* To be filled by the loader */</div><div class='add'>+		local-mac-address = [00 00 00 00 00 00];</div><div class='add'>+		apple,antenna-sku = "XX";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bluetooth0: bluetooth@0,1 {</div><div class='add'>+		compatible = "pci14e4,5f69";</div><div class='add'>+		reg = &lt;0x10100 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+		/* To be filled by the loader */</div><div class='add'>+		local-bd-address = [00 00 00 00 00 00];</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;nco_clkref {</div><div class='add'>+	clock-frequency = &lt;900000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include "spi1-nvram.dtsi"</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi b/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi<br/>new file mode 100644<br/>index 000000000000..c41c57d63997<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8103-pmgr.dtsi</a></div><div class='hunk'>@@ -0,0 +1,1133 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * PMGR Power domains for the Apple T8103 "M1" SoC</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+&amp;pmgr {</div><div class='add'>+	ps_sbr: power-controller@100 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x100 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sbr";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_aic: power-controller@108 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x108 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "aic";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dwi: power-controller@110 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x110 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dwi";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_soc_spmi0: power-controller@118 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x118 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "soc_spmi0";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_soc_spmi1: power-controller@120 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x120 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "soc_spmi1";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_soc_spmi2: power-controller@128 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x128 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "soc_spmi2";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_gpio: power-controller@130 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x130 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "gpio";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pms_busif: power-controller@138 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x138 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pms_busif";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pms: power-controller@140 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x140 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pms";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pms_fpwm0: power-controller@148 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x148 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pms_fpwm0";</div><div class='add'>+		power-domains = &lt;&amp;ps_pms&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pms_fpwm1: power-controller@150 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x150 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pms_fpwm1";</div><div class='add'>+		power-domains = &lt;&amp;ps_pms&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pms_fpwm2: power-controller@158 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x158 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pms_fpwm2";</div><div class='add'>+		power-domains = &lt;&amp;ps_pms&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pms_fpwm3: power-controller@160 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x160 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pms_fpwm3";</div><div class='add'>+		power-domains = &lt;&amp;ps_pms&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pms_fpwm4: power-controller@168 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x168 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pms_fpwm4";</div><div class='add'>+		power-domains = &lt;&amp;ps_pms&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_soc_dpe: power-controller@170 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x170 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "soc_dpe";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pmgr_soc_ocla: power-controller@178 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x178 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pmgr_soc_ocla";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_ispsens0: power-controller@180 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x180 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "ispsens0";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_ispsens1: power-controller@188 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x188 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "ispsens1";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_ispsens2: power-controller@190 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x190 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "ispsens2";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_ispsens3: power-controller@198 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x198 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "ispsens3";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pcie_ref: power-controller@1a0 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1a0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pcie_ref";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_aft0: power-controller@1a8 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1a8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "aft0";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_devc0_ivdmc: power-controller@1b0 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1b0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "devc0_ivdmc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_imx: power-controller@1b8 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1b8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "imx";</div><div class='add'>+		apple,always-on; /* Apple fabric, critical block */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sio_busif: power-controller@1c0 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1c0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sio_busif";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sio: power-controller@1c8 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1c8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sio";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_busif&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sio_cpu: power-controller@1d0 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1d0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sio_cpu";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_fpwm0: power-controller@1d8 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1d8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "fpwm0";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_fpwm1: power-controller@1e0 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1e0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "fpwm1";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_fpwm2: power-controller@1e8 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1e8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "fpwm2";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c0: power-controller@1f0 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1f0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c1: power-controller@1f8 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1f8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c1";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c2: power-controller@200 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x200 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c2";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c3: power-controller@208 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x208 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c3";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c4: power-controller@210 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x210 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c4";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi_p: power-controller@218 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x218 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi_p";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart_p: power-controller@220 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x220 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart_p";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_audio_p: power-controller@228 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x228 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "audio_p";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sio_adma: power-controller@230 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x230 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sio_adma";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio&gt;, &lt;&amp;ps_pms&gt;, &lt;&amp;ps_audio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_aes: power-controller@238 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x238 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "aes";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi0: power-controller@240 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x240 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio&gt;, &lt;&amp;ps_spi_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi1: power-controller@248 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x248 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi1";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio&gt;, &lt;&amp;ps_spi_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi2: power-controller@250 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x250 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi2";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio&gt;, &lt;&amp;ps_spi_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi3: power-controller@258 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x258 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi3";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio&gt;, &lt;&amp;ps_spi_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi4: power-controller@260 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x260 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi4";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio&gt;, &lt;&amp;ps_spi_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart_n: power-controller@268 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x268 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart_n";</div><div class='add'>+		power-domains = &lt;&amp;ps_uart_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart0: power-controller@270 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x270 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart0";</div><div class='add'>+		power-domains = &lt;&amp;ps_uart_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart1: power-controller@278 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x278 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart1";</div><div class='add'>+		power-domains = &lt;&amp;ps_uart_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart2: power-controller@280 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x280 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart2";</div><div class='add'>+		power-domains = &lt;&amp;ps_uart_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart3: power-controller@288 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x288 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart3";</div><div class='add'>+		power-domains = &lt;&amp;ps_uart_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart4: power-controller@290 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x290 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart4";</div><div class='add'>+		power-domains = &lt;&amp;ps_uart_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart5: power-controller@298 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x298 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart5";</div><div class='add'>+		power-domains = &lt;&amp;ps_uart_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart6: power-controller@2a0 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2a0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart6";</div><div class='add'>+		power-domains = &lt;&amp;ps_uart_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart7: power-controller@2a8 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2a8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart7";</div><div class='add'>+		power-domains = &lt;&amp;ps_uart_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart8: power-controller@2b0 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2b0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart8";</div><div class='add'>+		power-domains = &lt;&amp;ps_uart_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca0: power-controller@2b8 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2b8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca0";</div><div class='add'>+		power-domains = &lt;&amp;ps_audio_p&gt;, &lt;&amp;ps_sio_adma&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca1: power-controller@2c0 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2c0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca1";</div><div class='add'>+		power-domains = &lt;&amp;ps_audio_p&gt;, &lt;&amp;ps_sio_adma&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca2: power-controller@2c8 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2c8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca2";</div><div class='add'>+		power-domains = &lt;&amp;ps_audio_p&gt;, &lt;&amp;ps_sio_adma&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca3: power-controller@2d0 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2d0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca3";</div><div class='add'>+		power-domains = &lt;&amp;ps_audio_p&gt;, &lt;&amp;ps_sio_adma&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca4: power-controller@2d8 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2d8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca4";</div><div class='add'>+		power-domains = &lt;&amp;ps_audio_p&gt;, &lt;&amp;ps_sio_adma&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca5: power-controller@2e0 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2e0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca5";</div><div class='add'>+		power-domains = &lt;&amp;ps_audio_p&gt;, &lt;&amp;ps_sio_adma&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dpa0: power-controller@2e8 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2e8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dpa0";</div><div class='add'>+		power-domains = &lt;&amp;ps_audio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dpa1: power-controller@2f0 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2f0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dpa1";</div><div class='add'>+		power-domains = &lt;&amp;ps_audio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mcc: power-controller@2f8 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2f8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mcc";</div><div class='add'>+		apple,always-on; /* Memory controller */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs0: power-controller@300 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x300 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs0";</div><div class='add'>+		apple,always-on; /* LPDDR4 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs1: power-controller@310 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x310 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs1";</div><div class='add'>+		apple,always-on; /* LPDDR4 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs2: power-controller@308 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x308 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs2";</div><div class='add'>+		apple,always-on; /* LPDDR4 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs3: power-controller@318 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x318 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs3";</div><div class='add'>+		apple,always-on; /* LPDDR4 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_smx: power-controller@340 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x340 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "smx";</div><div class='add'>+		apple,always-on; /* Apple fabric, critical block */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_apcie: power-controller@348 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x348 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "apcie";</div><div class='add'>+		power-domains = &lt;&amp;ps_imx&gt;, &lt;&amp;ps_pcie_ref&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_rmx: power-controller@350 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x350 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "rmx";</div><div class='add'>+		/* Apple Fabric, display/image stuff: this can power down */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mmx: power-controller@358 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x358 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mmx";</div><div class='add'>+		/* Apple Fabric, media stuff: this can power down */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_disp0_fe: power-controller@360 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x360 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "disp0_fe";</div><div class='add'>+		power-domains = &lt;&amp;ps_rmx&gt;;</div><div class='add'>+		apple,always-on; /* TODO: figure out if we can enable PM here */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dispext_fe: power-controller@368 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x368 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dispext_fe";</div><div class='add'>+		power-domains = &lt;&amp;ps_rmx&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dispext_cpu0: power-controller@378 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x378 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dispext_cpu0";</div><div class='add'>+		power-domains = &lt;&amp;ps_dispext_fe&gt;;</div><div class='add'>+		apple,min-state = &lt;4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_jpg: power-controller@3c0 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x3c0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "jpg";</div><div class='add'>+		power-domains = &lt;&amp;ps_mmx&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_msr: power-controller@3c8 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x3c8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "msr";</div><div class='add'>+		power-domains = &lt;&amp;ps_mmx&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_msr_ase_core: power-controller@3d0 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x3d0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "msr_ase_core";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pmp: power-controller@3d8 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x3d8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pmp";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pms_sram: power-controller@3e0 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x3e0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pms_sram";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_apcie_gp: power-controller@3e8 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x3e8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "apcie_gp";</div><div class='add'>+		power-domains = &lt;&amp;ps_apcie&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_ans2: power-controller@3f0 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x3f0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "ans2";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_gfx: power-controller@3f8 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x3f8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "gfx";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs4: power-controller@320 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x320 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs4";</div><div class='add'>+		apple,always-on; /* LPDDR4 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs5: power-controller@330 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x330 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs5";</div><div class='add'>+		apple,always-on; /* LPDDR4 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs6: power-controller@328 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x328 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs6";</div><div class='add'>+		apple,always-on; /* LPDDR4 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs7: power-controller@338 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x338 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs7";</div><div class='add'>+		apple,always-on; /* LPDDR4 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dispdfr_fe: power-controller@3a8 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x3a8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dispdfr_fe";</div><div class='add'>+		power-domains = &lt;&amp;ps_rmx&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dispdfr_be: power-controller@3b0 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x3b0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dispdfr_be";</div><div class='add'>+		power-domains = &lt;&amp;ps_dispdfr_fe&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mipi_dsi: power-controller@3b8 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x3b8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mipi_dsi";</div><div class='add'>+		power-domains = &lt;&amp;ps_dispdfr_be&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_isp_sys: power-controller@400 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x400 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "isp_sys";</div><div class='add'>+		power-domains = &lt;&amp;ps_rmx&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc_sys: power-controller@408 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x408 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc_sys";</div><div class='add'>+		power-domains = &lt;&amp;ps_mmx&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_avd_sys: power-controller@410 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x410 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "avd_sys";</div><div class='add'>+		power-domains = &lt;&amp;ps_mmx&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_apcie_st: power-controller@418 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x418 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "apcie_st";</div><div class='add'>+		power-domains = &lt;&amp;ps_apcie&gt;, &lt;&amp;ps_ans2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_ane_sys: power-controller@470 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x470 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "ane_sys";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_atc0_common: power-controller@420 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x420 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "atc0_common";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_atc0_pcie: power-controller@428 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x428 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "atc0_pcie";</div><div class='add'>+		power-domains = &lt;&amp;ps_atc0_common&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_atc0_cio: power-controller@430 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x430 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "atc0_cio";</div><div class='add'>+		power-domains = &lt;&amp;ps_atc0_common&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_atc0_cio_pcie: power-controller@438 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x438 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "atc0_cio_pcie";</div><div class='add'>+		power-domains = &lt;&amp;ps_atc0_cio&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_atc0_cio_usb: power-controller@440 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x440 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "atc0_cio_usb";</div><div class='add'>+		power-domains = &lt;&amp;ps_atc0_cio&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_atc1_common: power-controller@448 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x448 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "atc1_common";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_atc1_pcie: power-controller@450 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x450 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "atc1_pcie";</div><div class='add'>+		power-domains = &lt;&amp;ps_atc1_common&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_atc1_cio: power-controller@458 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x458 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "atc1_cio";</div><div class='add'>+		power-domains = &lt;&amp;ps_atc1_common&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_atc1_cio_pcie: power-controller@460 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x460 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "atc1_cio_pcie";</div><div class='add'>+		power-domains = &lt;&amp;ps_atc1_cio&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_atc1_cio_usb: power-controller@468 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x468 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "atc1_cio_usb";</div><div class='add'>+		power-domains = &lt;&amp;ps_atc1_cio&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sep: power-controller@c00 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0xc00 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sep";</div><div class='add'>+		apple,always-on; /* Locked on */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc_dma: power-controller@8000 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x8000 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc_dma";</div><div class='add'>+		power-domains = &lt;&amp;ps_venc_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc_pipe4: power-controller@8008 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x8008 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc_pipe4";</div><div class='add'>+		power-domains = &lt;&amp;ps_venc_dma&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc_pipe5: power-controller@8010 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x8010 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc_pipe5";</div><div class='add'>+		power-domains = &lt;&amp;ps_venc_dma&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc_me0: power-controller@8018 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x8018 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc_me0";</div><div class='add'>+		power-domains = &lt;&amp;ps_venc_pipe4&gt;, &lt;&amp;ps_venc_pipe5&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc_me1: power-controller@8020 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x8020 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc_me1";</div><div class='add'>+		power-domains = &lt;&amp;ps_venc_pipe4&gt;, &lt;&amp;ps_venc_pipe5&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_ane_sys_cpu: power-controller@c000 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0xc000 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "ane_sys_cpu";</div><div class='add'>+		power-domains = &lt;&amp;ps_ane_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_disp0_cpu0: power-controller@10018 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x10018 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "disp0_cpu0";</div><div class='add'>+		power-domains = &lt;&amp;ps_disp0_fe&gt;;</div><div class='add'>+		apple,always-on; /* TODO: figure out if we can enable PM here */</div><div class='add'>+		apple,min-state = &lt;4&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pmgr_mini {</div><div class='add'>+	ps_debug: power-controller@58 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x58 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "debug";</div><div class='add'>+		apple,always-on; /* Core AON device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_nub_spmi0: power-controller@60 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x60 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "nub_spmi0";</div><div class='add'>+		apple,always-on; /* Core AON device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_nub_aon: power-controller@70 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x70 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "nub_aon";</div><div class='add'>+		apple,always-on; /* Core AON device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_nub_gpio: power-controller@80 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "nub_gpio";</div><div class='add'>+		apple,always-on; /* Core AON device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_nub_fabric: power-controller@a8 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0xa8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "nub_fabric";</div><div class='add'>+		apple,always-on; /* Core AON device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_nub_sram: power-controller@b0 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0xb0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "nub_sram";</div><div class='add'>+		apple,always-on; /* Core AON device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_debug_usb: power-controller@b8 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0xb8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "debug_usb";</div><div class='add'>+		apple,always-on; /* Core AON device */</div><div class='add'>+		power-domains = &lt;&amp;ps_debug&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_debug_auth: power-controller@c0 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0xc0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "debug_auth";</div><div class='add'>+		apple,always-on; /* Core AON device */</div><div class='add'>+		power-domains = &lt;&amp;ps_debug&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_nub_spmi1: power-controller@68 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x68 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "nub_spmi1";</div><div class='add'>+		apple,always-on; /* Core AON device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_msg: power-controller@78 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x78 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "msg";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_atc0_usb_aon: power-controller@88 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x88 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "atc0_usb_aon";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_atc1_usb_aon: power-controller@90 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x90 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "atc1_usb_aon";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_atc0_usb: power-controller@98 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x98 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "atc0_usb";</div><div class='add'>+		power-domains = &lt;&amp;ps_atc0_usb_aon&gt;, &lt;&amp;ps_atc0_common&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_atc1_usb: power-controller@a0 {</div><div class='add'>+		compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0xa0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "atc1_usb";</div><div class='add'>+		power-domains = &lt;&amp;ps_atc1_usb_aon&gt;, &lt;&amp;ps_atc1_common&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/apple/t8103.dtsi<br/>new file mode 100644<br/>index 000000000000..8b7b27887968<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8103.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8103.dtsi</a></div><div class='hunk'>@@ -0,0 +1,1137 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple T8103 "M1" SoC</div><div class='add'>+ *</div><div class='add'>+ * Other names: H13G, "Tonga"</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/apple-aic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/apple.h&gt;</div><div class='add'>+#include &lt;dt-bindings/spmi/spmi.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,t8103", "apple,arm-platform";</div><div class='add'>+</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		gpu = &amp;gpu;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu-map {</div><div class='add'>+			cluster0 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu_e0&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu_e1&gt;;</div><div class='add'>+				};</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu_e2&gt;;</div><div class='add'>+				};</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu_e3&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cluster1 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu_p0&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu_p1&gt;;</div><div class='add'>+				};</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu_p2&gt;;</div><div class='add'>+				};</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu_p3&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_e0: cpu@0 {</div><div class='add'>+			compatible = "apple,icestorm";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x0&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			operating-points-v2 = &lt;&amp;ecluster_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;714&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_e&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_0&gt;;</div><div class='add'>+			i-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_e1: cpu@1 {</div><div class='add'>+			compatible = "apple,icestorm";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x1&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			operating-points-v2 = &lt;&amp;ecluster_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;714&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_e&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_0&gt;;</div><div class='add'>+			i-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_e2: cpu@2 {</div><div class='add'>+			compatible = "apple,icestorm";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x2&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			operating-points-v2 = &lt;&amp;ecluster_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;714&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_e&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_0&gt;;</div><div class='add'>+			i-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_e3: cpu@3 {</div><div class='add'>+			compatible = "apple,icestorm";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x3&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			operating-points-v2 = &lt;&amp;ecluster_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;714&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_e&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_0&gt;;</div><div class='add'>+			i-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_p0: cpu@10100 {</div><div class='add'>+			compatible = "apple,firestorm";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x10100&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			operating-points-v2 = &lt;&amp;pcluster_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_p&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_1&gt;;</div><div class='add'>+			i-cache-size = &lt;0x30000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x20000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_p1: cpu@10101 {</div><div class='add'>+			compatible = "apple,firestorm";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x10101&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			operating-points-v2 = &lt;&amp;pcluster_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_p&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_1&gt;;</div><div class='add'>+			i-cache-size = &lt;0x30000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x20000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_p2: cpu@10102 {</div><div class='add'>+			compatible = "apple,firestorm";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x10102&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			operating-points-v2 = &lt;&amp;pcluster_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_p&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_1&gt;;</div><div class='add'>+			i-cache-size = &lt;0x30000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x20000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_p3: cpu@10103 {</div><div class='add'>+			compatible = "apple,firestorm";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x10103&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			operating-points-v2 = &lt;&amp;pcluster_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_p&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_1&gt;;</div><div class='add'>+			i-cache-size = &lt;0x30000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x20000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_cache_0: l2-cache-0 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x400000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_cache_1: l2-cache-1 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0xc00000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ecluster_opp: opp-table-0 {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		opp01 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;600000000&gt;;</div><div class='add'>+			opp-level = &lt;1&gt;;</div><div class='add'>+			clock-latency-ns = &lt;7500&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp02 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;972000000&gt;;</div><div class='add'>+			opp-level = &lt;2&gt;;</div><div class='add'>+			clock-latency-ns = &lt;22000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp03 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1332000000&gt;;</div><div class='add'>+			opp-level = &lt;3&gt;;</div><div class='add'>+			clock-latency-ns = &lt;27000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp04 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1704000000&gt;;</div><div class='add'>+			opp-level = &lt;4&gt;;</div><div class='add'>+			clock-latency-ns = &lt;33000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp05 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2064000000&gt;;</div><div class='add'>+			opp-level = &lt;5&gt;;</div><div class='add'>+			clock-latency-ns = &lt;50000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcluster_opp: opp-table-1 {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		opp01 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;600000000&gt;;</div><div class='add'>+			opp-level = &lt;1&gt;;</div><div class='add'>+			clock-latency-ns = &lt;8000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp02 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;828000000&gt;;</div><div class='add'>+			opp-level = &lt;2&gt;;</div><div class='add'>+			clock-latency-ns = &lt;19000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp03 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1056000000&gt;;</div><div class='add'>+			opp-level = &lt;3&gt;;</div><div class='add'>+			clock-latency-ns = &lt;21000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp04 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1284000000&gt;;</div><div class='add'>+			opp-level = &lt;4&gt;;</div><div class='add'>+			clock-latency-ns = &lt;23000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp05 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1500000000&gt;;</div><div class='add'>+			opp-level = &lt;5&gt;;</div><div class='add'>+			clock-latency-ns = &lt;24000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp06 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1728000000&gt;;</div><div class='add'>+			opp-level = &lt;6&gt;;</div><div class='add'>+			clock-latency-ns = &lt;29000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp07 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1956000000&gt;;</div><div class='add'>+			opp-level = &lt;7&gt;;</div><div class='add'>+			clock-latency-ns = &lt;31000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp08 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2184000000&gt;;</div><div class='add'>+			opp-level = &lt;8&gt;;</div><div class='add'>+			clock-latency-ns = &lt;34000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp09 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2388000000&gt;;</div><div class='add'>+			opp-level = &lt;9&gt;;</div><div class='add'>+			clock-latency-ns = &lt;36000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp10 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2592000000&gt;;</div><div class='add'>+			opp-level = &lt;10&gt;;</div><div class='add'>+			clock-latency-ns = &lt;51000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp11 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2772000000&gt;;</div><div class='add'>+			opp-level = &lt;11&gt;;</div><div class='add'>+			clock-latency-ns = &lt;54000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp12 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2988000000&gt;;</div><div class='add'>+			opp-level = &lt;12&gt;;</div><div class='add'>+			clock-latency-ns = &lt;55000&gt;;</div><div class='add'>+		};</div><div class='add'>+#if 0</div><div class='add'>+		/* Not available until CPU deep sleep is implemented */</div><div class='add'>+		opp13 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;3096000000&gt;;</div><div class='add'>+			opp-level = &lt;13&gt;;</div><div class='add'>+			clock-latency-ns = &lt;55000&gt;;</div><div class='add'>+			turbo-mode;</div><div class='add'>+		};</div><div class='add'>+		opp14 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;3144000000&gt;;</div><div class='add'>+			opp-level = &lt;14&gt;;</div><div class='add'>+			clock-latency-ns = &lt;56000&gt;;</div><div class='add'>+			turbo-mode;</div><div class='add'>+		};</div><div class='add'>+		opp15 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;3204000000&gt;;</div><div class='add'>+			opp-level = &lt;15&gt;;</div><div class='add'>+			clock-latency-ns = &lt;56000&gt;;</div><div class='add'>+			turbo-mode;</div><div class='add'>+		};</div><div class='add'>+#endif</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt";</div><div class='add'>+		interrupts = &lt;AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;AIC_FIQ AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;AIC_FIQ AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu-e {</div><div class='add'>+		compatible = "apple,icestorm-pmu";</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_FIQ AIC_CPU_PMU_E IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu-p {</div><div class='add'>+		compatible = "apple,firestorm-pmu";</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_FIQ AIC_CPU_PMU_P IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clkref: clock-ref {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+		clock-output-names = "clkref";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_120m: clock-120m {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;120000000&gt;;</div><div class='add'>+		clock-output-names = "clk_120m";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_200m: clock-200m {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;200000000&gt;;</div><div class='add'>+		clock-output-names = "clk_200m";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * This is a fabulated representation of the input clock</div><div class='add'>+	 * to NCO since we don't know the true clock tree.</div><div class='add'>+	 */</div><div class='add'>+	nco_clkref: clock-ref-nco {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-output-names = "nco_ref";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		gpu_globals: globals {</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu_hw_cal_a: hw-cal-a {</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu_hw_cal_b: hw-cal-b {</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uat_handoff: uat-handoff {</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uat_pagetables: uat-pagetables {</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uat_ttbs: uat-ttbs {</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		ranges;</div><div class='add'>+		nonposted-mmio;</div><div class='add'>+</div><div class='add'>+		gpu: gpu@206400000 {</div><div class='add'>+			compatible = "apple,agx-g13g";</div><div class='add'>+			reg = &lt;0x2 0x6400000 0 0x40000&gt;,</div><div class='add'>+				&lt;0x2 0x4000000 0 0x1000000&gt;;</div><div class='add'>+			reg-names = "asc", "sgx";</div><div class='add'>+			mboxes = &lt;&amp;agx_mbox&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_gfx&gt;;</div><div class='add'>+			memory-region = &lt;&amp;uat_ttbs&gt;, &lt;&amp;uat_pagetables&gt;, &lt;&amp;uat_handoff&gt;,</div><div class='add'>+					&lt;&amp;gpu_hw_cal_a&gt;, &lt;&amp;gpu_hw_cal_b&gt;, &lt;&amp;gpu_globals&gt;;</div><div class='add'>+			memory-region-names = "ttbs", "pagetables", "handoff",</div><div class='add'>+					      "hw-cal-a", "hw-cal-b", "globals";</div><div class='add'>+</div><div class='add'>+			apple,firmware-abi = &lt;0 0 0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		agx_mbox: mbox@206408000 {</div><div class='add'>+			compatible = "apple,t8103-asc-mailbox", "apple,asc-mailbox-v4";</div><div class='add'>+			reg = &lt;0x2 0x6408000 0x0 0x4000&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 575 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ 576 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ 577 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ 578 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "send-empty", "send-not-empty",</div><div class='add'>+				"recv-empty", "recv-not-empty";</div><div class='add'>+			#mbox-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpufreq_e: performance-controller@210e20000 {</div><div class='add'>+			compatible = "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";</div><div class='add'>+			reg = &lt;0x2 0x10e20000 0 0x1000&gt;;</div><div class='add'>+			#performance-domain-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpufreq_p: performance-controller@211e20000 {</div><div class='add'>+			compatible = "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";</div><div class='add'>+			reg = &lt;0x2 0x11e20000 0 0x1000&gt;;</div><div class='add'>+			#performance-domain-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display_dfr: display-pipe@228200000 {</div><div class='add'>+			compatible = "apple,t8103-display-pipe", "apple,h7-display-pipe";</div><div class='add'>+			reg = &lt;0x2 0x28200000 0x0 0xc000&gt;,</div><div class='add'>+			      &lt;0x2 0x28400000 0x0 0x4000&gt;;</div><div class='add'>+			reg-names = "be", "fe";</div><div class='add'>+			power-domains = &lt;&amp;ps_dispdfr_fe&gt;, &lt;&amp;ps_dispdfr_be&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 502 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 506 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "be", "fe";</div><div class='add'>+			iommus = &lt;&amp;displaydfr_dart 0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			port {</div><div class='add'>+				dfr_adp_out_mipi: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;dfr_mipi_in_adp&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		displaydfr_dart: iommu@228304000 {</div><div class='add'>+			compatible = "apple,t8103-dart";</div><div class='add'>+			reg = &lt;0x2 0x28304000 0x0 0x4000&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 504 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#iommu-cells = &lt;1&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_dispdfr_fe&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		displaydfr_mipi: dsi@228600000 {</div><div class='add'>+			compatible = "apple,t8103-display-pipe-mipi", "apple,h7-display-pipe-mipi";</div><div class='add'>+			reg = &lt;0x2 0x28600000 0x0 0x100000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_mipi_dsi&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				dfr_mipi_in: port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					dfr_mipi_in_adp: endpoint@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+						remote-endpoint = &lt;&amp;dfr_adp_out_mipi&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				dfr_mipi_out: port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sio_dart: iommu@235004000 {</div><div class='add'>+			compatible = "apple,t8103-dart";</div><div class='add'>+			reg = &lt;0x2 0x35004000 0x0 0x4000&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 635 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#iommu-cells = &lt;1&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_sio_cpu&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c0: i2c@235010000 {</div><div class='add'>+			compatible = "apple,t8103-i2c", "apple,i2c";</div><div class='add'>+			reg = &lt;0x2 0x35010000 0x0 0x4000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 627 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c0_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			#address-cells = &lt;0x1&gt;;</div><div class='add'>+			#size-cells = &lt;0x0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_i2c0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c1: i2c@235014000 {</div><div class='add'>+			compatible = "apple,t8103-i2c", "apple,i2c";</div><div class='add'>+			reg = &lt;0x2 0x35014000 0x0 0x4000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 628 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c1_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			#address-cells = &lt;0x1&gt;;</div><div class='add'>+			#size-cells = &lt;0x0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_i2c1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c2: i2c@235018000 {</div><div class='add'>+			compatible = "apple,t8103-i2c", "apple,i2c";</div><div class='add'>+			reg = &lt;0x2 0x35018000 0x0 0x4000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 629 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c2_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			#address-cells = &lt;0x1&gt;;</div><div class='add'>+			#size-cells = &lt;0x0&gt;;</div><div class='add'>+			status = "disabled"; /* not used in all devices */</div><div class='add'>+			power-domains = &lt;&amp;ps_i2c2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c3: i2c@23501c000 {</div><div class='add'>+			compatible = "apple,t8103-i2c", "apple,i2c";</div><div class='add'>+			reg = &lt;0x2 0x3501c000 0x0 0x4000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 630 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c3_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			#address-cells = &lt;0x1&gt;;</div><div class='add'>+			#size-cells = &lt;0x0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_i2c3&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c4: i2c@235020000 {</div><div class='add'>+			compatible = "apple,t8103-i2c", "apple,i2c";</div><div class='add'>+			reg = &lt;0x2 0x35020000 0x0 0x4000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 631 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c4_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			#address-cells = &lt;0x1&gt;;</div><div class='add'>+			#size-cells = &lt;0x0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_i2c4&gt;;</div><div class='add'>+			status = "disabled"; /* only used in J293 */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		fpwm1: pwm@235044000 {</div><div class='add'>+			compatible = "apple,t8103-fpwm", "apple,s5l-fpwm";</div><div class='add'>+			reg = &lt;0x2 0x35044000 0x0 0x4000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_fpwm1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			#pwm-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi0: spi@235100000 {</div><div class='add'>+			compatible = "apple,t8103-spi", "apple,spi";</div><div class='add'>+			reg = &lt;0x2 0x35100000 0x0 0x4000&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 614 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk_200m&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;spi0_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			power-domains = &lt;&amp;ps_spi0&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi1: spi@235104000 {</div><div class='add'>+			compatible = "apple,t8103-spi", "apple,spi";</div><div class='add'>+			reg = &lt;0x2 0x35104000 0x0 0x4000&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 615 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk_200m&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;spi1_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			power-domains = &lt;&amp;ps_spi1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi3: spi@23510c000 {</div><div class='add'>+			compatible = "apple,t8103-spi", "apple,spi";</div><div class='add'>+			reg = &lt;0x2 0x3510c000 0x0 0x4000&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 617 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk_120m&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;spi3_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			power-domains = &lt;&amp;ps_spi3&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		serial0: serial@235200000 {</div><div class='add'>+			compatible = "apple,s5l-uart";</div><div class='add'>+			reg = &lt;0x2 0x35200000 0x0 0x1000&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 605 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			/*</div><div class='add'>+			 * TODO: figure out the clocking properly, there may</div><div class='add'>+			 * be a third selectable clock.</div><div class='add'>+			 */</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;, &lt;&amp;clkref&gt;;</div><div class='add'>+			clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+			power-domains = &lt;&amp;ps_uart0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		serial2: serial@235208000 {</div><div class='add'>+			compatible = "apple,s5l-uart";</div><div class='add'>+			reg = &lt;0x2 0x35208000 0x0 0x1000&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 607 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;, &lt;&amp;clkref&gt;;</div><div class='add'>+			clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+			power-domains = &lt;&amp;ps_uart2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		admac: dma-controller@238200000 {</div><div class='add'>+			compatible = "apple,t8103-admac", "apple,admac";</div><div class='add'>+			reg = &lt;0x2 0x38200000 0x0 0x34000&gt;;</div><div class='add'>+			dma-channels = &lt;24&gt;;</div><div class='add'>+			interrupts-extended = &lt;0&gt;,</div><div class='add'>+					      &lt;&amp;aic AIC_IRQ 626 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;0&gt;,</div><div class='add'>+					      &lt;0&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+			iommus = &lt;&amp;sio_dart 2&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_sio_adma&gt;;</div><div class='add'>+			resets = &lt;&amp;ps_audio_p&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mca: i2s@238400000 {</div><div class='add'>+			compatible = "apple,t8103-mca", "apple,mca";</div><div class='add'>+			reg = &lt;0x2 0x38400000 0x0 0x18000&gt;,</div><div class='add'>+			      &lt;0x2 0x38300000 0x0 0x30000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 619 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 620 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 621 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 622 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 623 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 624 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;ps_audio_p&gt;;</div><div class='add'>+			clocks = &lt;&amp;nco 0&gt;, &lt;&amp;nco 1&gt;, &lt;&amp;nco 2&gt;,</div><div class='add'>+				 &lt;&amp;nco 3&gt;, &lt;&amp;nco 4&gt;, &lt;&amp;nco 4&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_audio_p&gt;, &lt;&amp;ps_mca0&gt;, &lt;&amp;ps_mca1&gt;,</div><div class='add'>+					&lt;&amp;ps_mca2&gt;, &lt;&amp;ps_mca3&gt;, &lt;&amp;ps_mca4&gt;, &lt;&amp;ps_mca5&gt;;</div><div class='add'>+			dmas = &lt;&amp;admac 0&gt;, &lt;&amp;admac 1&gt;, &lt;&amp;admac 2&gt;, &lt;&amp;admac 3&gt;,</div><div class='add'>+			       &lt;&amp;admac 4&gt;, &lt;&amp;admac 5&gt;, &lt;&amp;admac 6&gt;, &lt;&amp;admac 7&gt;,</div><div class='add'>+			       &lt;&amp;admac 8&gt;, &lt;&amp;admac 9&gt;, &lt;&amp;admac 10&gt;, &lt;&amp;admac 11&gt;,</div><div class='add'>+			       &lt;&amp;admac 12&gt;, &lt;&amp;admac 13&gt;, &lt;&amp;admac 14&gt;, &lt;&amp;admac 15&gt;,</div><div class='add'>+			       &lt;&amp;admac 16&gt;, &lt;&amp;admac 17&gt;, &lt;&amp;admac 18&gt;, &lt;&amp;admac 19&gt;,</div><div class='add'>+			       &lt;&amp;admac 20&gt;, &lt;&amp;admac 21&gt;, &lt;&amp;admac 22&gt;, &lt;&amp;admac 23&gt;;</div><div class='add'>+			dma-names = "tx0a", "rx0a", "tx0b", "rx0b",</div><div class='add'>+				"tx1a", "rx1a", "tx1b", "rx1b",</div><div class='add'>+				"tx2a", "rx2a", "tx2b", "rx2b",</div><div class='add'>+				"tx3a", "rx3a", "tx3b", "rx3b",</div><div class='add'>+				"tx4a", "rx4a", "tx4b", "rx4b",</div><div class='add'>+				"tx5a", "rx5a", "tx5b", "rx5b";</div><div class='add'>+</div><div class='add'>+			#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nco: clock-controller@23b044000 {</div><div class='add'>+			compatible = "apple,t8103-nco", "apple,nco";</div><div class='add'>+			reg = &lt;0x2 0x3b044000 0x0 0x14000&gt;;</div><div class='add'>+			clocks = &lt;&amp;nco_clkref&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aic: interrupt-controller@23b100000 {</div><div class='add'>+			compatible = "apple,t8103-aic", "apple,aic";</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			reg = &lt;0x2 0x3b100000 0x0 0x8000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_aic&gt;;</div><div class='add'>+</div><div class='add'>+			affinities {</div><div class='add'>+				e-core-pmu-affinity {</div><div class='add'>+					apple,fiq-index = &lt;AIC_CPU_PMU_E&gt;;</div><div class='add'>+					cpus = &lt;&amp;cpu_e0 &amp;cpu_e1 &amp;cpu_e2 &amp;cpu_e3&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				p-core-pmu-affinity {</div><div class='add'>+					apple,fiq-index = &lt;AIC_CPU_PMU_P&gt;;</div><div class='add'>+					cpus = &lt;&amp;cpu_p0 &amp;cpu_p1 &amp;cpu_p2 &amp;cpu_p3&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmgr: power-management@23b700000 {</div><div class='add'>+			compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			reg = &lt;0x2 0x3b700000 0 0x14000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_ap: pinctrl@23c100000 {</div><div class='add'>+			compatible = "apple,t8103-pinctrl", "apple,pinctrl";</div><div class='add'>+			reg = &lt;0x2 0x3c100000 0x0 0x100000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_gpio&gt;;</div><div class='add'>+</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;pinctrl_ap 0 0 212&gt;;</div><div class='add'>+			apple,npins = &lt;212&gt;;</div><div class='add'>+</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 190 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 191 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 192 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 193 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 194 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 195 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 196 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			i2c0_pins: i2c0-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(192, 1)&gt;,</div><div class='add'>+					 &lt;APPLE_PINMUX(188, 1)&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c1_pins: i2c1-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(201, 1)&gt;,</div><div class='add'>+					 &lt;APPLE_PINMUX(199, 1)&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c2_pins: i2c2-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(163, 1)&gt;,</div><div class='add'>+					 &lt;APPLE_PINMUX(162, 1)&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c3_pins: i2c3-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(73, 1)&gt;,</div><div class='add'>+					 &lt;APPLE_PINMUX(72, 1)&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c4_pins: i2c4-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(135, 1)&gt;,</div><div class='add'>+					 &lt;APPLE_PINMUX(134, 1)&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi0_pins: spi0-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(67, 1)&gt;, /* CLK */</div><div class='add'>+					&lt;APPLE_PINMUX(68, 1)&gt;,  /* MOSI */</div><div class='add'>+					&lt;APPLE_PINMUX(69, 1)&gt;;  /* MISO */</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi1_pins: spi1-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(42, 1)&gt;,</div><div class='add'>+					&lt;APPLE_PINMUX(43, 1)&gt;,</div><div class='add'>+					&lt;APPLE_PINMUX(44, 1)&gt;,</div><div class='add'>+					&lt;APPLE_PINMUX(45, 1)&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi3_pins: spi3-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(46, 1)&gt;,</div><div class='add'>+					&lt;APPLE_PINMUX(47, 1)&gt;,</div><div class='add'>+					&lt;APPLE_PINMUX(48, 1)&gt;,</div><div class='add'>+					&lt;APPLE_PINMUX(49, 1)&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pcie_pins: pcie-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(150, 1)&gt;,</div><div class='add'>+					 &lt;APPLE_PINMUX(151, 1)&gt;,</div><div class='add'>+					 &lt;APPLE_PINMUX(32, 1)&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nub_spmi: spmi@23d0d9300 {</div><div class='add'>+			compatible = "apple,t8103-spmi", "apple,spmi";</div><div class='add'>+			reg = &lt;0x2 0x3d0d9300 0x0 0x100&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			pmic1: pmic@f {</div><div class='add'>+				compatible = "apple,sera-pmic", "apple,spmi-nvmem";</div><div class='add'>+				reg = &lt;0xf SPMI_USID&gt;;</div><div class='add'>+</div><div class='add'>+				nvmem-layout {</div><div class='add'>+					compatible = "fixed-layout";</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					boot_stage: boot-stage@9f01 {</div><div class='add'>+						reg = &lt;0x9f01 0x1&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					boot_error_count: boot-error-count@9f02,0 {</div><div class='add'>+						reg = &lt;0x9f02 0x1&gt;;</div><div class='add'>+						bits = &lt;0 4&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					panic_count: panic-count@9f02,4 {</div><div class='add'>+						reg = &lt;0x9f02 0x1&gt;;</div><div class='add'>+						bits = &lt;4 4&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					boot_error_stage: boot-error-stage@9f03 {</div><div class='add'>+						reg = &lt;0x9f03 0x1&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					shutdown_flag: shutdown-flag@9f0f,3 {</div><div class='add'>+						reg = &lt;0x9f0f 0x1&gt;;</div><div class='add'>+						bits = &lt;3 1&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					fault_shadow: fault-shadow@a67b {</div><div class='add'>+						reg = &lt;0xa67b 0x10&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					socd: socd@ab00 {</div><div class='add'>+						reg = &lt;0xab00 0x400&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					pm_setting: pm-setting@d001 {</div><div class='add'>+						reg = &lt;0xd001 0x1&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					rtc_offset: rtc-offset@d100 {</div><div class='add'>+						reg = &lt;0xd100 0x6&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_nub: pinctrl@23d1f0000 {</div><div class='add'>+			compatible = "apple,t8103-pinctrl", "apple,pinctrl";</div><div class='add'>+			reg = &lt;0x2 0x3d1f0000 0x0 0x4000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_nub_gpio&gt;;</div><div class='add'>+</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;pinctrl_nub 0 0 23&gt;;</div><div class='add'>+			apple,npins = &lt;23&gt;;</div><div class='add'>+</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 330 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 331 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 332 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 333 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 334 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 335 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 336 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmgr_mini: power-management@23d280000 {</div><div class='add'>+			compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			reg = &lt;0x2 0x3d280000 0 0x4000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wdt: watchdog@23d2b0000 {</div><div class='add'>+			compatible = "apple,t8103-wdt", "apple,wdt";</div><div class='add'>+			reg = &lt;0x2 0x3d2b0000 0x0 0x4000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 338 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smc: smc@23e400000 {</div><div class='add'>+			compatible = "apple,t8103-smc", "apple,smc";</div><div class='add'>+			reg = &lt;0x2 0x3e400000 0x0 0x4000&gt;,</div><div class='add'>+				&lt;0x2 0x3fe00000 0x0 0x100000&gt;;</div><div class='add'>+			reg-names = "smc", "sram";</div><div class='add'>+			mboxes = &lt;&amp;smc_mbox&gt;;</div><div class='add'>+</div><div class='add'>+			smc_gpio: gpio {</div><div class='add'>+				compatible = "apple,smc-gpio";</div><div class='add'>+				gpio-controller;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			smc_reboot: reboot {</div><div class='add'>+				compatible = "apple,smc-reboot";</div><div class='add'>+				nvmem-cells = &lt;&amp;shutdown_flag&gt;, &lt;&amp;boot_stage&gt;,</div><div class='add'>+					&lt;&amp;boot_error_count&gt;, &lt;&amp;panic_count&gt;;</div><div class='add'>+				nvmem-cell-names = "shutdown_flag", "boot_stage",</div><div class='add'>+					"boot_error_count", "panic_count";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smc_mbox: mbox@23e408000 {</div><div class='add'>+			compatible = "apple,t8103-asc-mailbox", "apple,asc-mailbox-v4";</div><div class='add'>+			reg = &lt;0x2 0x3e408000 0x0 0x4000&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 400 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ 401 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ 402 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ 403 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "send-empty", "send-not-empty",</div><div class='add'>+				"recv-empty", "recv-not-empty";</div><div class='add'>+			#mbox-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_smc: pinctrl@23e820000 {</div><div class='add'>+			compatible = "apple,t8103-pinctrl", "apple,pinctrl";</div><div class='add'>+			reg = &lt;0x2 0x3e820000 0x0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;pinctrl_smc 0 0 16&gt;;</div><div class='add'>+			apple,npins = &lt;16&gt;;</div><div class='add'>+</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 391 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 392 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 393 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 394 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 395 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 396 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 397 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_aop: pinctrl@24a820000 {</div><div class='add'>+			compatible = "apple,t8103-pinctrl", "apple,pinctrl";</div><div class='add'>+			reg = &lt;0x2 0x4a820000 0x0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;pinctrl_aop 0 0 42&gt;;</div><div class='add'>+			apple,npins = &lt;42&gt;;</div><div class='add'>+</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 268 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 269 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 270 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 271 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 272 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 273 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 274 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ans_mbox: mbox@277408000 {</div><div class='add'>+			compatible = "apple,t8103-asc-mailbox", "apple,asc-mailbox-v4";</div><div class='add'>+			reg = &lt;0x2 0x77408000 0x0 0x4000&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 583 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ 584 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ 585 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ 586 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "send-empty", "send-not-empty",</div><div class='add'>+				"recv-empty", "recv-not-empty";</div><div class='add'>+			#mbox-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_ans2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sart: iommu@27bc50000 {</div><div class='add'>+			compatible = "apple,t8103-sart";</div><div class='add'>+			reg = &lt;0x2 0x7bc50000 0x0 0x10000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_ans2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nvme@27bcc0000 {</div><div class='add'>+			compatible = "apple,t8103-nvme-ans2", "apple,nvme-ans2";</div><div class='add'>+			reg = &lt;0x2 0x7bcc0000 0x0 0x40000&gt;,</div><div class='add'>+				&lt;0x2 0x77400000 0x0 0x4000&gt;;</div><div class='add'>+			reg-names = "nvme", "ans";</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 590 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			mboxes = &lt;&amp;ans_mbox&gt;;</div><div class='add'>+			apple,sart = &lt;&amp;sart&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_ans2&gt;, &lt;&amp;ps_apcie_st&gt;;</div><div class='add'>+			power-domain-names = "ans", "apcie0";</div><div class='add'>+			resets = &lt;&amp;ps_ans2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie0_dart_0: iommu@681008000 {</div><div class='add'>+			compatible = "apple,t8103-dart";</div><div class='add'>+			reg = &lt;0x6 0x81008000 0x0 0x4000&gt;;</div><div class='add'>+			#iommu-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 696 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_apcie_gp&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie0_dart_1: iommu@682008000 {</div><div class='add'>+			compatible = "apple,t8103-dart";</div><div class='add'>+			reg = &lt;0x6 0x82008000 0x0 0x4000&gt;;</div><div class='add'>+			#iommu-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 699 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_apcie_gp&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie0_dart_2: iommu@683008000 {</div><div class='add'>+			compatible = "apple,t8103-dart";</div><div class='add'>+			reg = &lt;0x6 0x83008000 0x0 0x4000&gt;;</div><div class='add'>+			#iommu-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 702 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_apcie_gp&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie0: pcie@690000000 {</div><div class='add'>+			compatible = "apple,t8103-pcie", "apple,pcie";</div><div class='add'>+			device_type = "pci";</div><div class='add'>+</div><div class='add'>+			reg = &lt;0x6 0x90000000 0x0 0x1000000&gt;,</div><div class='add'>+			      &lt;0x6 0x80000000 0x0 0x100000&gt;,</div><div class='add'>+			      &lt;0x6 0x81000000 0x0 0x4000&gt;,</div><div class='add'>+			      &lt;0x6 0x82000000 0x0 0x4000&gt;,</div><div class='add'>+			      &lt;0x6 0x83000000 0x0 0x4000&gt;;</div><div class='add'>+			reg-names = "config", "rc", "port0", "port1", "port2";</div><div class='add'>+</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 695 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 698 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 701 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			msi-controller;</div><div class='add'>+			msi-parent = &lt;&amp;pcie0&gt;;</div><div class='add'>+			msi-ranges = &lt;&amp;aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32&gt;;</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+			iommu-map = &lt;0x100 &amp;pcie0_dart_0 1 1&gt;,</div><div class='add'>+				    &lt;0x200 &amp;pcie0_dart_1 1 1&gt;,</div><div class='add'>+				    &lt;0x300 &amp;pcie0_dart_2 1 1&gt;;</div><div class='add'>+			iommu-map-mask = &lt;0xff00&gt;;</div><div class='add'>+</div><div class='add'>+			bus-range = &lt;0 3&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges = &lt;0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000&gt;,</div><div class='add'>+				 &lt;0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000&gt;;</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;ps_apcie_gp&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;pcie_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+			port00: pci@0,0 {</div><div class='add'>+				device_type = "pci";</div><div class='add'>+				reg = &lt;0x0 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+				reset-gpios = &lt;&amp;pinctrl_ap 152 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;3&gt;;</div><div class='add'>+				#size-cells = &lt;2&gt;;</div><div class='add'>+				ranges;</div><div class='add'>+</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='add'>+				interrupt-map = &lt;0 0 0 1 &amp;port00 0 0 0 0&gt;,</div><div class='add'>+						&lt;0 0 0 2 &amp;port00 0 0 0 1&gt;,</div><div class='add'>+						&lt;0 0 0 3 &amp;port00 0 0 0 2&gt;,</div><div class='add'>+						&lt;0 0 0 4 &amp;port00 0 0 0 3&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port01: pci@1,0 {</div><div class='add'>+				device_type = "pci";</div><div class='add'>+				reg = &lt;0x800 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+				reset-gpios = &lt;&amp;pinctrl_ap 153 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;3&gt;;</div><div class='add'>+				#size-cells = &lt;2&gt;;</div><div class='add'>+				ranges;</div><div class='add'>+</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='add'>+				interrupt-map = &lt;0 0 0 1 &amp;port01 0 0 0 0&gt;,</div><div class='add'>+						&lt;0 0 0 2 &amp;port01 0 0 0 1&gt;,</div><div class='add'>+						&lt;0 0 0 3 &amp;port01 0 0 0 2&gt;,</div><div class='add'>+						&lt;0 0 0 4 &amp;port01 0 0 0 3&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port02: pci@2,0 {</div><div class='add'>+				device_type = "pci";</div><div class='add'>+				reg = &lt;0x1000 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+				reset-gpios = &lt;&amp;pinctrl_ap 33 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;3&gt;;</div><div class='add'>+				#size-cells = &lt;2&gt;;</div><div class='add'>+				ranges;</div><div class='add'>+</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='add'>+				interrupt-map = &lt;0 0 0 1 &amp;port02 0 0 0 0&gt;,</div><div class='add'>+						&lt;0 0 0 2 &amp;port02 0 0 0 1&gt;,</div><div class='add'>+						&lt;0 0 0 3 &amp;port02 0 0 0 2&gt;,</div><div class='add'>+						&lt;0 0 0 4 &amp;port02 0 0 0 3&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include "t8103-pmgr.dtsi"</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8112-j413.dts b/arch/arm64/boot/dts/apple/t8112-j413.dts<br/>new file mode 100644<br/>index 000000000000..6f69658623bf<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8112-j413.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8112-j413.dts</a></div><div class='hunk'>@@ -0,0 +1,80 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple MacBook Air (M2, 2022)</div><div class='add'>+ *</div><div class='add'>+ * target-type: J413</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t8112.dtsi"</div><div class='add'>+#include "t8112-jxxx.dtsi"</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j413", "apple,t8112", "apple,arm-platform";</div><div class='add'>+	model = "Apple MacBook Air (13-inch, M2, 2022)";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		bluetooth0 = &amp;bluetooth0;</div><div class='add'>+		wifi0 = &amp;wifi0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	led-controller {</div><div class='add'>+		compatible = "pwm-leds";</div><div class='add'>+		led-0 {</div><div class='add'>+			pwms = &lt;&amp;fpwm1 0 40000&gt;;</div><div class='add'>+			label = "kbd_backlight";</div><div class='add'>+			function = LED_FUNCTION_KBD_BACKLIGHT;</div><div class='add'>+			color = &lt;LED_COLOR_ID_WHITE&gt;;</div><div class='add'>+			max-brightness = &lt;255&gt;;</div><div class='add'>+			default-state = "keep";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Force the bus number assignments so that we can declare some of the</div><div class='add'>+ * on-board devices and properties that are populated by the bootloader</div><div class='add'>+ * (such as MAC addresses).</div><div class='add'>+ */</div><div class='add'>+&amp;port00 {</div><div class='add'>+	bus-range = &lt;1 1&gt;;</div><div class='add'>+	wifi0: wifi@0,0 {</div><div class='add'>+		compatible = "pci14e4,4433";</div><div class='add'>+		reg = &lt;0x10000 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+		/* To be filled by the loader */</div><div class='add'>+		local-mac-address = [00 10 18 00 00 10];</div><div class='add'>+		apple,antenna-sku = "XX";</div><div class='add'>+		brcm,board-type = "apple,hokkaido";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bluetooth0: bluetooth@0,1 {</div><div class='add'>+		compatible = "pci14e4,5f71";</div><div class='add'>+		reg = &lt;0x10100 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+		/* To be filled by the loader */</div><div class='add'>+		local-bd-address = [00 00 00 00 00 00];</div><div class='add'>+		brcm,board-type = "apple,hokkaido";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	/* MagSafe port */</div><div class='add'>+	hpm5: usb-pd@3a {</div><div class='add'>+		compatible = "apple,cd321x";</div><div class='add'>+		reg = &lt;0x3a&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;pinctrl_ap&gt;;</div><div class='add'>+		interrupts = &lt;8 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupt-names = "irq";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fpwm1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8112-j415.dts b/arch/arm64/boot/dts/apple/t8112-j415.dts<br/>new file mode 100644<br/>index 000000000000..b54e218e5384<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8112-j415.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8112-j415.dts</a></div><div class='hunk'>@@ -0,0 +1,80 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple MacBook Air (15-inch, M2, 2023)</div><div class='add'>+ *</div><div class='add'>+ * target-type: J415</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t8112.dtsi"</div><div class='add'>+#include "t8112-jxxx.dtsi"</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j415", "apple,t8112", "apple,arm-platform";</div><div class='add'>+	model = "Apple MacBook Air (15-inch, M2, 2023)";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		bluetooth0 = &amp;bluetooth0;</div><div class='add'>+		wifi0 = &amp;wifi0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	led-controller {</div><div class='add'>+		compatible = "pwm-leds";</div><div class='add'>+		led-0 {</div><div class='add'>+			pwms = &lt;&amp;fpwm1 0 40000&gt;;</div><div class='add'>+			label = "kbd_backlight";</div><div class='add'>+			function = LED_FUNCTION_KBD_BACKLIGHT;</div><div class='add'>+			color = &lt;LED_COLOR_ID_WHITE&gt;;</div><div class='add'>+			max-brightness = &lt;255&gt;;</div><div class='add'>+			default-state = "keep";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Force the bus number assignments so that we can declare some of the</div><div class='add'>+ * on-board devices and properties that are populated by the bootloader</div><div class='add'>+ * (such as MAC addresses).</div><div class='add'>+ */</div><div class='add'>+&amp;port00 {</div><div class='add'>+	bus-range = &lt;1 1&gt;;</div><div class='add'>+	wifi0: wifi@0,0 {</div><div class='add'>+		compatible = "pci14e4,4433";</div><div class='add'>+		reg = &lt;0x10000 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+		/* To be filled by the loader */</div><div class='add'>+		local-mac-address = [00 10 18 00 00 10];</div><div class='add'>+		apple,antenna-sku = "XX";</div><div class='add'>+		brcm,board-type = "apple,snake";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bluetooth0: bluetooth@0,1 {</div><div class='add'>+		compatible = "pci14e4,5f71";</div><div class='add'>+		reg = &lt;0x10100 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+		/* To be filled by the loader */</div><div class='add'>+		local-bd-address = [00 00 00 00 00 00];</div><div class='add'>+		brcm,board-type = "apple,snake";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	/* MagSafe port */</div><div class='add'>+	hpm5: usb-pd@3a {</div><div class='add'>+		compatible = "apple,cd321x";</div><div class='add'>+		reg = &lt;0x3a&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;pinctrl_ap&gt;;</div><div class='add'>+		interrupts = &lt;8 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupt-names = "irq";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fpwm1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8112-j473.dts b/arch/arm64/boot/dts/apple/t8112-j473.dts<br/>new file mode 100644<br/>index 000000000000..06fe257f08be<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8112-j473.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8112-j473.dts</a></div><div class='hunk'>@@ -0,0 +1,54 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple Mac mini (M2, 2023)</div><div class='add'>+ *</div><div class='add'>+ * target-type: J473</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t8112.dtsi"</div><div class='add'>+#include "t8112-jxxx.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j473", "apple,t8112", "apple,arm-platform";</div><div class='add'>+	model = "Apple Mac mini (M2, 2023)";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;ethernet0;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Force the bus number assignments so that we can declare some of the</div><div class='add'>+ * on-board devices and properties that are populated by the bootloader</div><div class='add'>+ * (such as MAC addresses).</div><div class='add'>+ */</div><div class='add'>+&amp;port00 {</div><div class='add'>+	bus-range = &lt;1 1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;port01 {</div><div class='add'>+	bus-range = &lt;2 2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;port02 {</div><div class='add'>+	bus-range = &lt;3 3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+	ethernet0: ethernet@0,0 {</div><div class='add'>+		reg = &lt;0x30000 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+		/* To be filled by the loader */</div><div class='add'>+		local-mac-address = [00 10 18 00 00 00];</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie1_dart {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie2_dart {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8112-j493.dts b/arch/arm64/boot/dts/apple/t8112-j493.dts<br/>new file mode 100644<br/>index 000000000000..fb8ad7d4c65a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8112-j493.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8112-j493.dts</a></div><div class='hunk'>@@ -0,0 +1,135 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple MacBook Pro (13-inch, M1, 2022)</div><div class='add'>+ *</div><div class='add'>+ * target-type: J493</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "t8112.dtsi"</div><div class='add'>+#include "t8112-jxxx.dtsi"</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,j493", "apple,t8112", "apple,arm-platform";</div><div class='add'>+	model = "Apple MacBook Pro (13-inch, M2, 2022)";</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * All of those are used by the bootloader to pass calibration</div><div class='add'>+	 * blobs and other device-specific properties</div><div class='add'>+	 */</div><div class='add'>+	aliases {</div><div class='add'>+		bluetooth0 = &amp;bluetooth0;</div><div class='add'>+		touchbar0 = &amp;touchbar0;</div><div class='add'>+		wifi0 = &amp;wifi0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	led-controller {</div><div class='add'>+		compatible = "pwm-leds";</div><div class='add'>+		led-0 {</div><div class='add'>+			pwms = &lt;&amp;fpwm1 0 40000&gt;;</div><div class='add'>+			label = "kbd_backlight";</div><div class='add'>+			function = LED_FUNCTION_KBD_BACKLIGHT;</div><div class='add'>+			color = &lt;LED_COLOR_ID_WHITE&gt;;</div><div class='add'>+			max-brightness = &lt;255&gt;;</div><div class='add'>+			default-state = "keep";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * The driver depends on boot loader initialized state which resets when this</div><div class='add'>+ * power-domain is powered off. This happens on suspend or when the driver is</div><div class='add'>+ * missing during boot. Mark the domain as always on until the driver can</div><div class='add'>+ * handle this.</div><div class='add'>+ */</div><div class='add'>+&amp;ps_dispdfr_be {</div><div class='add'>+	apple,always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;display_dfr {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dfr_mipi_out {</div><div class='add'>+	dfr_mipi_out_panel: endpoint@0 {</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		remote-endpoint = &lt;&amp;dfr_panel_in&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;displaydfr_mipi {</div><div class='add'>+	status = "okay";</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	dfr_panel: panel@0 {</div><div class='add'>+		compatible = "apple,j493-summit", "apple,summit";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		max-brightness = &lt;255&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			dfr_panel_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;dfr_mipi_out_panel&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;displaydfr_dart {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Force the bus number assignments so that we can declare some of the</div><div class='add'>+ * on-board devices and properties that are populated by the bootloader</div><div class='add'>+ * (such as MAC addresses).</div><div class='add'>+ */</div><div class='add'>+&amp;port00 {</div><div class='add'>+	bus-range = &lt;1 1&gt;;</div><div class='add'>+	wifi0: wifi@0,0 {</div><div class='add'>+		compatible = "pci14e4,4425";</div><div class='add'>+		reg = &lt;0x10000 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+		/* To be filled by the loader */</div><div class='add'>+		local-mac-address = [00 00 00 00 00 00];</div><div class='add'>+		apple,antenna-sku = "XX";</div><div class='add'>+		brcm,board-type = "apple,kyushu";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bluetooth0: bluetooth@0,1 {</div><div class='add'>+		compatible = "pci14e4,5f69";</div><div class='add'>+		reg = &lt;0x10100 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+		/* To be filled by the loader */</div><div class='add'>+		local-bd-address = [00 00 00 00 00 00];</div><div class='add'>+		brcm,board-type = "apple,kyushu";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fpwm1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	touchbar0: touchbar@0 {</div><div class='add'>+		compatible = "apple,j493-touchbar";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;8000000&gt;;</div><div class='add'>+		spi-cs-setup-delay-ns = &lt;2000&gt;;</div><div class='add'>+		spi-cs-hold-delay-ns = &lt;2000&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pinctrl_ap 170 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pinctrl_ap 174 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		firmware-name = "apple/dfrmtfw-j493.bin";</div><div class='add'>+		touchscreen-size-x = &lt;23045&gt;;</div><div class='add'>+		touchscreen-size-y = &lt;640&gt;;</div><div class='add'>+		touchscreen-inverted-y;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8112-jxxx.dtsi b/arch/arm64/boot/dts/apple/t8112-jxxx.dtsi<br/>new file mode 100644<br/>index 000000000000..6da35496a4c8<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8112-jxxx.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8112-jxxx.dtsi</a></div><div class='hunk'>@@ -0,0 +1,83 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple M2 MacBook Air/Pro (M2, 2022)</div><div class='add'>+ *</div><div class='add'>+ * This file contains parts common to all Apple M2 devices using the t8112.</div><div class='add'>+ *</div><div class='add'>+ * target-type: J493, J413</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;serial0;</div><div class='add'>+		serial2 = &amp;serial2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		stdout-path = "serial0";</div><div class='add'>+</div><div class='add'>+		framebuffer0: framebuffer@0 {</div><div class='add'>+			compatible = "apple,simple-framebuffer", "simple-framebuffer";</div><div class='add'>+			reg = &lt;0 0 0 0&gt;; /* To be filled by loader */</div><div class='add'>+			/* Format properties will be added by loader */</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@800000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x8 0 0x2 0&gt;; /* To be filled by loader */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;serial0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;serial2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	hpm0: usb-pd@38 {</div><div class='add'>+		compatible = "apple,cd321x";</div><div class='add'>+		reg = &lt;0x38&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;pinctrl_ap&gt;;</div><div class='add'>+		interrupts = &lt;8 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupt-names = "irq";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hpm1: usb-pd@3f {</div><div class='add'>+		compatible = "apple,cd321x";</div><div class='add'>+		reg = &lt;0x3f&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;pinctrl_ap&gt;;</div><div class='add'>+		interrupts = &lt;8 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupt-names = "irq";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;nco_clkref {</div><div class='add'>+	clock-frequency = &lt;900000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include "spi1-nvram.dtsi"</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8112-pmgr.dtsi b/arch/arm64/boot/dts/apple/t8112-pmgr.dtsi<br/>new file mode 100644<br/>index 000000000000..7c050c6f2707<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8112-pmgr.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8112-pmgr.dtsi</a></div><div class='hunk'>@@ -0,0 +1,1140 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * PMGR Power domains for the Apple T8112 "M2" SoC</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+&amp;pmgr {</div><div class='add'>+	ps_sbr: power-controller@100 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x100 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sbr";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_aic: power-controller@108 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x108 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "aic";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dwi: power-controller@110 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x110 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dwi";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_soc_spmi0: power-controller@118 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x118 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "soc_spmi0";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_gpio: power-controller@120 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x120 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "gpio";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pms_busif: power-controller@128 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x128 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pms_busif";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pms: power-controller@130 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x130 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pms";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pms_c1ppt: power-controller@160 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x160 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pms_c1ppt";</div><div class='add'>+		power-domains = &lt;&amp;ps_pms&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_soc_dpe: power-controller@168 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x168 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "soc_dpe";</div><div class='add'>+		apple,always-on; /* Core device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pmgr_soc_ocla: power-controller@170 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x170 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pmgr_soc_ocla";</div><div class='add'>+		power-domains = &lt;&amp;ps_pms&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_ispsens0: power-controller@178 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x178 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "ispsens0";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_ispsens1: power-controller@180 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x180 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "ispsens1";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_ispsens2: power-controller@188 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x188 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "ispsens2";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_ispsens3: power-controller@190 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x190 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "ispsens3";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pcie_ref: power-controller@198 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x198 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pcie_ref";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_aft0: power-controller@1a0 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1a0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "aft0";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_imx: power-controller@1a8 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1a8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "imx";</div><div class='add'>+		apple,always-on; /* Apple fabric, critical block */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sio_busif: power-controller@1b0 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1b0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sio_busif";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sio: power-controller@1b8 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1b8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sio";</div><div class='add'>+		apple,always-on;</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_busif&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sio_cpu: power-controller@1c0 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1c0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sio_cpu";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_fpwm0: power-controller@1c8 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1c8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "fpwm0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_fpwm1: power-controller@1d0 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1d0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "fpwm1";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_fpwm2: power-controller@1d8 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1d8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "fpwm2";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c0: power-controller@1e0 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1e0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c1: power-controller@1e8 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1e8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c1";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c2: power-controller@1f0 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1f0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c2";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c3: power-controller@1f8 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x1f8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c3";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_i2c4: power-controller@200 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x200 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "i2c4";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi_p: power-controller@208 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x208 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi_p";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart_p: power-controller@210 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x210 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart_p";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_audio_p: power-controller@218 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x218 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "audio_p";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_aes: power-controller@220 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x220 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "aes";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi0: power-controller@228 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x228 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi0";</div><div class='add'>+		power-domains = &lt;&amp;ps_spi_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi1: power-controller@230 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x230 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi1";</div><div class='add'>+		power-domains = &lt;&amp;ps_spi_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi2: power-controller@238 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x238 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi2";</div><div class='add'>+		power-domains = &lt;&amp;ps_spi_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi3: power-controller@240 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x240 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi3";</div><div class='add'>+		power-domains = &lt;&amp;ps_spi_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi4: power-controller@248 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x248 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi4";</div><div class='add'>+		power-domains = &lt;&amp;ps_spi_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_spi5: power-controller@250 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x250 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "spi5";</div><div class='add'>+		power-domains = &lt;&amp;ps_spi_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart_n: power-controller@258 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x258 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart_n";</div><div class='add'>+		power-domains = &lt;&amp;ps_uart_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart0: power-controller@260 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x260 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart0";</div><div class='add'>+		power-domains = &lt;&amp;ps_uart_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart1: power-controller@268 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x268 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart1";</div><div class='add'>+		power-domains = &lt;&amp;ps_uart_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart2: power-controller@270 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x270 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart2";</div><div class='add'>+		power-domains = &lt;&amp;ps_uart_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart3: power-controller@278 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x278 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart3";</div><div class='add'>+		power-domains = &lt;&amp;ps_uart_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart4: power-controller@280 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x280 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart4";</div><div class='add'>+		power-domains = &lt;&amp;ps_uart_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart5: power-controller@288 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x288 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart5";</div><div class='add'>+		power-domains = &lt;&amp;ps_uart_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart6: power-controller@290 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x290 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart6";</div><div class='add'>+		power-domains = &lt;&amp;ps_uart_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart7: power-controller@298 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x298 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart7";</div><div class='add'>+		power-domains = &lt;&amp;ps_uart_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_uart8: power-controller@2a0 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2a0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "uart8";</div><div class='add'>+		power-domains = &lt;&amp;ps_uart_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sio_adma: power-controller@2a8 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2a8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sio_adma";</div><div class='add'>+		power-domains = &lt;&amp;ps_spi_p&gt;, &lt;&amp;ps_audio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dpa0: power-controller@2b0 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2b0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dpa0";</div><div class='add'>+		power-domains = &lt;&amp;ps_audio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dpa1: power-controller@2b8 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2b8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dpa1";</div><div class='add'>+		power-domains = &lt;&amp;ps_audio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca0: power-controller@2c0 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2c0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca0";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_adma&gt;, &lt;&amp;ps_audio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca1: power-controller@2c8 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2c8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca1";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_adma&gt;, &lt;&amp;ps_audio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca2: power-controller@2d0 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2d0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca2";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_adma&gt;, &lt;&amp;ps_audio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca3: power-controller@2d8 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2d8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca3";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_adma&gt;, &lt;&amp;ps_audio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca4: power-controller@2e0 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2e0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca4";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_adma&gt;, &lt;&amp;ps_audio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mca5: power-controller@2e8 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2e8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mca5";</div><div class='add'>+		power-domains = &lt;&amp;ps_sio_adma&gt;, &lt;&amp;ps_audio_p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mcc: power-controller@2f0 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2f0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mcc";</div><div class='add'>+		apple,always-on; /* Memory controller */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs0: power-controller@2f8 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x2f8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs0";</div><div class='add'>+		apple,always-on; /* LPDDR4 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs2: power-controller@300 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x300 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs2";</div><div class='add'>+		apple,always-on; /* LPDDR4 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs1: power-controller@308 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x308 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs1";</div><div class='add'>+		apple,always-on; /* LPDDR4 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs3: power-controller@310 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x310 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs3";</div><div class='add'>+		apple,always-on; /* LPDDR4 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs4: power-controller@318 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x318 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs4";</div><div class='add'>+		apple,always-on; /* LPDDR4 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs5: power-controller@320 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x320 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs5";</div><div class='add'>+		apple,always-on; /* LPDDR4 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs6: power-controller@328 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x328 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs6";</div><div class='add'>+		apple,always-on; /* LPDDR4 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dcs7: power-controller@330 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x330 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dcs7";</div><div class='add'>+		apple,always-on; /* LPDDR4 interface */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_smx0: power-controller@338 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x338 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "smx0";</div><div class='add'>+		apple,always-on; /* Apple fabric, critical block */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_smx1: power-controller@340 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x340 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "smx1";</div><div class='add'>+		apple,always-on; /* Apple fabric, critical block */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_apcie: power-controller@348 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x348 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "apcie";</div><div class='add'>+		power-domains = &lt;&amp;ps_imx&gt;, &lt;&amp;ps_pcie_ref&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_rmx0: power-controller@350 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x350 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "rmx0";</div><div class='add'>+		/* Apple Fabric, display/image stuff: this can power down */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_rmx1: power-controller@358 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x358 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "rmx1";</div><div class='add'>+		/* Apple Fabric, display/image stuff: this can power down */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_cmx: power-controller@360 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x360 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "cmx";</div><div class='add'>+		apple,always-on; /* Apple fabric, critical block */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mmx: power-controller@368 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x368 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mmx";</div><div class='add'>+		/* Apple Fabric, media stuff: this can power down */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_disp0_sys: power-controller@370 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x370 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "disp0_sys";</div><div class='add'>+		power-domains = &lt;&amp;ps_rmx1&gt;;</div><div class='add'>+		apple,always-on; /* TODO: figure out if we can enable PM here */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_disp0_fe: power-controller@378 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x378 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "disp0_fe";</div><div class='add'>+		power-domains = &lt;&amp;ps_disp0_sys&gt;;</div><div class='add'>+		apple,always-on; /* TODO: figure out if we can enable PM here */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dispext_sys: power-controller@380 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x380 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dispext_sys";</div><div class='add'>+		power-domains = &lt;&amp;ps_rmx0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dispext_fe: power-controller@388 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x388 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dispext_fe";</div><div class='add'>+		power-domains = &lt;&amp;ps_dispext_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dispext_cpu0: power-controller@3c8 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x3c8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dispext_cpu0";</div><div class='add'>+		power-domains = &lt;&amp;ps_dispext_fe&gt;;</div><div class='add'>+		apple,min-state = &lt;4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dptx_ext_phy: power-controller@3d8 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x3d8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dptx_ext_phy";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dispdfr_fe: power-controller@3e0 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x3e0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dispdfr_fe";</div><div class='add'>+		power-domains = &lt;&amp;ps_rmx0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_dispdfr_be: power-controller@3e8 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x3e8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "dispdfr_be";</div><div class='add'>+		power-domains = &lt;&amp;ps_dispdfr_fe&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_mipi_dsi: power-controller@3f0 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x3f0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "mipi_dsi";</div><div class='add'>+		power-domains = &lt;&amp;ps_dispdfr_be&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_jpg: power-controller@3f8 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x3f8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "jpg";</div><div class='add'>+		power-domains = &lt;&amp;ps_cmx&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_apcie_gp: power-controller@400 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x400 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "apcie_gp";</div><div class='add'>+		power-domains = &lt;&amp;ps_apcie&gt;;</div><div class='add'>+		apple,always-on; /* Breaks things if shut down */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_msr: power-controller@408 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x408 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "msr";</div><div class='add'>+		power-domains = &lt;&amp;ps_imx&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pmp: power-controller@410 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x410 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pmp";</div><div class='add'>+		apple,always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_pms_sram: power-controller@418 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x418 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "pms_sram";</div><div class='add'>+		apple,always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_msr_ase_core: power-controller@420 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x420 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "msr_ase_core";</div><div class='add'>+		power-domains = &lt;&amp;ps_msr&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_ans: power-controller@428 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x428 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "ans";</div><div class='add'>+		power-domains = &lt;&amp;ps_imx&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_gfx: power-controller@430 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x430 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "gfx";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_isp_sys: power-controller@438 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x438 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "isp_sys";</div><div class='add'>+		power-domains = &lt;&amp;ps_rmx1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc_sys: power-controller@440 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x440 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc_sys";</div><div class='add'>+		power-domains = &lt;&amp;ps_rmx1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_avd_sys: power-controller@448 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x448 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "avd_sys";</div><div class='add'>+		power-domains = &lt;&amp;ps_mmx&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_apcie_st: power-controller@450 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x450 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "apcie_st";</div><div class='add'>+		power-domains = &lt;&amp;ps_apcie&gt;, &lt;&amp;ps_ans&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_atc0_common: power-controller@458 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x458 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "atc0_common";</div><div class='add'>+		power-domains = &lt;&amp;ps_imx&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_atc0_pcie: power-controller@460 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x460 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "atc0_pcie";</div><div class='add'>+		power-domains = &lt;&amp;ps_atc0_common&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_atc0_cio: power-controller@468 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x468 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "atc0_cio";</div><div class='add'>+		power-domains = &lt;&amp;ps_atc0_common&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_atc0_cio_pcie: power-controller@470 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x470 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "atc0_cio_pcie";</div><div class='add'>+		power-domains = &lt;&amp;ps_atc0_cio&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_atc0_cio_usb: power-controller@478 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x478 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "atc0_cio_usb";</div><div class='add'>+		power-domains = &lt;&amp;ps_atc0_cio&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_atc1_common: power-controller@480 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x480 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "atc1_common";</div><div class='add'>+		power-domains = &lt;&amp;ps_rmx0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_atc1_pcie: power-controller@488 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x488 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "atc1_pcie";</div><div class='add'>+		power-domains = &lt;&amp;ps_atc1_common&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_atc1_cio: power-controller@490 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x490 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "atc1_cio";</div><div class='add'>+		power-domains = &lt;&amp;ps_atc1_common&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_atc1_cio_pcie: power-controller@498 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x498 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "atc1_cio_pcie";</div><div class='add'>+		power-domains = &lt;&amp;ps_atc1_cio&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_atc1_cio_usb: power-controller@4a0 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x4a0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "atc1_cio_usb";</div><div class='add'>+		power-domains = &lt;&amp;ps_atc1_cio&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_ane_sys: power-controller@4a8 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x4a8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "ane_sys";</div><div class='add'>+		power-domains = &lt;&amp;ps_mmx&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_scodec: power-controller@4b0 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x4b0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "scodec";</div><div class='add'>+		power-domains = &lt;&amp;ps_rmx0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_sep: power-controller@c00 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0xc00 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "sep";</div><div class='add'>+		apple,always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc_dma: power-controller@8000 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x8000 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc_dma";</div><div class='add'>+		power-domains = &lt;&amp;ps_venc_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc_pipe4: power-controller@8008 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x8008 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc_pipe4";</div><div class='add'>+		power-domains = &lt;&amp;ps_venc_dma&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc_pipe5: power-controller@8010 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x8010 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc_pipe5";</div><div class='add'>+		power-domains = &lt;&amp;ps_venc_dma&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc_me0: power-controller@8018 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x8018 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc_me0";</div><div class='add'>+		power-domains = &lt;&amp;ps_venc_pipe5&gt;, &lt;&amp;ps_venc_pipe4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_venc_me1: power-controller@8020 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x8020 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "venc_me1";</div><div class='add'>+		power-domains = &lt;&amp;ps_venc_pipe5&gt;, &lt;&amp;ps_venc_pipe4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_disp0_cpu0: power-controller@10000 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x10000 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "disp0_cpu0";</div><div class='add'>+		power-domains = &lt;&amp;ps_disp0_fe&gt;;</div><div class='add'>+		apple,min-state = &lt;4&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pmgr_mini {</div><div class='add'>+</div><div class='add'>+	ps_debug_gated: power-controller@58 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x58 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "debug_gated";</div><div class='add'>+		apple,always-on; /* Core AON device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_nub_spmi0: power-controller@60 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x60 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "nub_spmi0";</div><div class='add'>+		apple,always-on; /* Core AON device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_nub_spmi1: power-controller@68 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x68 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "nub_spmi1";</div><div class='add'>+		apple,always-on; /* Core AON device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_nub_aon: power-controller@70 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x70 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "nub_aon";</div><div class='add'>+		apple,always-on; /* Core AON device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_msg: power-controller@78 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x78 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "msg";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_nub_gpio: power-controller@80 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x80 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "nub_gpio";</div><div class='add'>+		apple,always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_atc0_usb_aon: power-controller@88 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x88 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "atc0_usb_aon";</div><div class='add'>+		apple,always-on; /* Needs to stay on for dwc3 to work */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_atc1_usb_aon: power-controller@90 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x90 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "atc1_usb_aon";</div><div class='add'>+		apple,always-on; /* Needs to stay on for dwc3 to work */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_atc0_usb: power-controller@98 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0x98 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "atc0_usb";</div><div class='add'>+		power-domains = &lt;&amp;ps_atc0_usb_aon&gt;, &lt;&amp;ps_atc0_common&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_atc1_usb: power-controller@a0 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0xa0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "atc1_usb";</div><div class='add'>+		power-domains = &lt;&amp;ps_atc1_usb_aon&gt;, &lt;&amp;ps_atc1_common&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_nub_fabric: power-controller@a8 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0xa8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "nub_fabric";</div><div class='add'>+		apple,always-on; /* Core AON device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_nub_sram: power-controller@b0 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0xb0 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "nub_sram";</div><div class='add'>+		apple,always-on; /* Core AON device */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps_debug_switch: power-controller@b8 {</div><div class='add'>+		compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";</div><div class='add'>+		reg = &lt;0xb8 4&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+		#reset-cells = &lt;0&gt;;</div><div class='add'>+		label = "debug_switch";</div><div class='add'>+		apple,always-on; /* Core AON device */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/apple/t8112.dtsi b/arch/arm64/boot/dts/apple/t8112.dtsi<br/>new file mode 100644<br/>index 000000000000..3f79878b25af<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/apple/t8112.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/apple/t8112.dtsi</a></div><div class='hunk'>@@ -0,0 +1,1176 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Apple T8112 "M2" SoC</div><div class='add'>+ *</div><div class='add'>+ * Other names: H14G</div><div class='add'>+ *</div><div class='add'>+ * Copyright The Asahi Linux Contributors</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/apple-aic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/apple.h&gt;</div><div class='add'>+#include &lt;dt-bindings/spmi/spmi.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "apple,t8112", "apple,arm-platform";</div><div class='add'>+</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		gpu = &amp;gpu;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu-map {</div><div class='add'>+			cluster0 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu_e0&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu_e1&gt;;</div><div class='add'>+				};</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu_e2&gt;;</div><div class='add'>+				};</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu_e3&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cluster1 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu_p0&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu_p1&gt;;</div><div class='add'>+				};</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu_p2&gt;;</div><div class='add'>+				};</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu_p3&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_e0: cpu@0 {</div><div class='add'>+			compatible = "apple,blizzard";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x0&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			operating-points-v2 = &lt;&amp;ecluster_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;756&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_e&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_0&gt;;</div><div class='add'>+			i-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_e1: cpu@1 {</div><div class='add'>+			compatible = "apple,blizzard";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x1&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			operating-points-v2 = &lt;&amp;ecluster_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;756&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_e&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_0&gt;;</div><div class='add'>+			i-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_e2: cpu@2 {</div><div class='add'>+			compatible = "apple,blizzard";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x2&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			operating-points-v2 = &lt;&amp;ecluster_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;756&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_e&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_0&gt;;</div><div class='add'>+			i-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_e3: cpu@3 {</div><div class='add'>+			compatible = "apple,blizzard";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x3&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			operating-points-v2 = &lt;&amp;ecluster_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;756&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_e&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_0&gt;;</div><div class='add'>+			i-cache-size = &lt;0x20000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_p0: cpu@10100 {</div><div class='add'>+			compatible = "apple,avalanche";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x10100&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			operating-points-v2 = &lt;&amp;pcluster_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_p&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_1&gt;;</div><div class='add'>+			i-cache-size = &lt;0x30000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x20000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_p1: cpu@10101 {</div><div class='add'>+			compatible = "apple,avalanche";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x10101&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			operating-points-v2 = &lt;&amp;pcluster_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_p&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_1&gt;;</div><div class='add'>+			i-cache-size = &lt;0x30000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x20000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_p2: cpu@10102 {</div><div class='add'>+			compatible = "apple,avalanche";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x10102&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			operating-points-v2 = &lt;&amp;pcluster_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_p&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_1&gt;;</div><div class='add'>+			i-cache-size = &lt;0x30000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x20000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_p3: cpu@10103 {</div><div class='add'>+			compatible = "apple,avalanche";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x10103&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0 0&gt;; /* To be filled by loader */</div><div class='add'>+			operating-points-v2 = &lt;&amp;pcluster_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;cpufreq_p&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_1&gt;;</div><div class='add'>+			i-cache-size = &lt;0x30000&gt;;</div><div class='add'>+			d-cache-size = &lt;0x20000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_cache_0: l2-cache-0 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x400000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_cache_1: l2-cache-1 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x1000000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ecluster_opp: opp-table-0 {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+		opp-shared;</div><div class='add'>+</div><div class='add'>+		opp01 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;600000000&gt;;</div><div class='add'>+			opp-level = &lt;1&gt;;</div><div class='add'>+			clock-latency-ns = &lt;7500&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp02 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;912000000&gt;;</div><div class='add'>+			opp-level = &lt;2&gt;;</div><div class='add'>+			clock-latency-ns = &lt;20000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp03 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1284000000&gt;;</div><div class='add'>+			opp-level = &lt;3&gt;;</div><div class='add'>+			clock-latency-ns = &lt;22000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp04 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1752000000&gt;;</div><div class='add'>+			opp-level = &lt;4&gt;;</div><div class='add'>+			clock-latency-ns = &lt;30000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp05 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2004000000&gt;;</div><div class='add'>+			opp-level = &lt;5&gt;;</div><div class='add'>+			clock-latency-ns = &lt;35000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp06 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2256000000&gt;;</div><div class='add'>+			opp-level = &lt;6&gt;;</div><div class='add'>+			clock-latency-ns = &lt;39000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp07 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2424000000&gt;;</div><div class='add'>+			opp-level = &lt;7&gt;;</div><div class='add'>+			clock-latency-ns = &lt;53000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcluster_opp: opp-table-1 {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+		opp-shared;</div><div class='add'>+</div><div class='add'>+		opp01 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;660000000&gt;;</div><div class='add'>+			opp-level = &lt;1&gt;;</div><div class='add'>+			clock-latency-ns = &lt;9000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp02 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;924000000&gt;;</div><div class='add'>+			opp-level = &lt;2&gt;;</div><div class='add'>+			clock-latency-ns = &lt;19000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp03 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1188000000&gt;;</div><div class='add'>+			opp-level = &lt;3&gt;;</div><div class='add'>+			clock-latency-ns = &lt;22000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp04 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1452000000&gt;;</div><div class='add'>+			opp-level = &lt;4&gt;;</div><div class='add'>+			clock-latency-ns = &lt;24000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp05 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1704000000&gt;;</div><div class='add'>+			opp-level = &lt;5&gt;;</div><div class='add'>+			clock-latency-ns = &lt;26000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp06 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1968000000&gt;;</div><div class='add'>+			opp-level = &lt;6&gt;;</div><div class='add'>+			clock-latency-ns = &lt;28000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp07 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2208000000&gt;;</div><div class='add'>+			opp-level = &lt;7&gt;;</div><div class='add'>+			clock-latency-ns = &lt;30000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp08 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2400000000&gt;;</div><div class='add'>+			opp-level = &lt;8&gt;;</div><div class='add'>+			clock-latency-ns = &lt;33000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp09 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2568000000&gt;;</div><div class='add'>+			opp-level = &lt;9&gt;;</div><div class='add'>+			clock-latency-ns = &lt;34000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp10 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2724000000&gt;;</div><div class='add'>+			opp-level = &lt;10&gt;;</div><div class='add'>+			clock-latency-ns = &lt;36000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp11 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2868000000&gt;;</div><div class='add'>+			opp-level = &lt;11&gt;;</div><div class='add'>+			clock-latency-ns = &lt;41000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp12 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2988000000&gt;;</div><div class='add'>+			opp-level = &lt;12&gt;;</div><div class='add'>+			clock-latency-ns = &lt;42000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp13 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;3096000000&gt;;</div><div class='add'>+			opp-level = &lt;13&gt;;</div><div class='add'>+			clock-latency-ns = &lt;44000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp14 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;3204000000&gt;;</div><div class='add'>+			opp-level = &lt;14&gt;;</div><div class='add'>+			clock-latency-ns = &lt;46000&gt;;</div><div class='add'>+		};</div><div class='add'>+		/* Not available until CPU deep sleep is implemented */</div><div class='add'>+#if 0</div><div class='add'>+		opp15 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;3324000000&gt;;</div><div class='add'>+			opp-level = &lt;15&gt;;</div><div class='add'>+			clock-latency-ns = &lt;62000&gt;;</div><div class='add'>+			turbo-mode;</div><div class='add'>+		};</div><div class='add'>+		opp16 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;3408000000&gt;;</div><div class='add'>+			opp-level = &lt;16&gt;;</div><div class='add'>+			clock-latency-ns = &lt;62000&gt;;</div><div class='add'>+			turbo-mode;</div><div class='add'>+		};</div><div class='add'>+		opp17 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;3504000000&gt;;</div><div class='add'>+			opp-level = &lt;17&gt;;</div><div class='add'>+			clock-latency-ns = &lt;62000&gt;;</div><div class='add'>+			turbo-mode;</div><div class='add'>+		};</div><div class='add'>+#endif</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt";</div><div class='add'>+		interrupts = &lt;AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;AIC_FIQ AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;AIC_FIQ AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu-e {</div><div class='add'>+		compatible = "apple,blizzard-pmu";</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_FIQ AIC_CPU_PMU_E IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu-p {</div><div class='add'>+		compatible = "apple,avalanche-pmu";</div><div class='add'>+		interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+		interrupts = &lt;AIC_FIQ AIC_CPU_PMU_P IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clkref: clock-ref {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+		clock-output-names = "clkref";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_200m: clock-200m {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;200000000&gt;;</div><div class='add'>+		clock-output-names = "clk_200m";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * This is a fabulated representation of the input clock</div><div class='add'>+	 * to NCO since we don't know the true clock tree.</div><div class='add'>+	 */</div><div class='add'>+	nco_clkref: clock-ref-nco {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-output-names = "nco_ref";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		gpu_globals: globals {</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu_hw_cal_a: hw-cal-a {</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu_hw_cal_b: hw-cal-b {</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uat_handoff: uat-handoff {</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uat_pagetables: uat-pagetables {</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uat_ttbs: uat-ttbs {</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		ranges;</div><div class='add'>+		nonposted-mmio;</div><div class='add'>+</div><div class='add'>+		gpu: gpu@206400000 {</div><div class='add'>+			compatible = "apple,agx-g14g";</div><div class='add'>+			reg = &lt;0x2 0x6400000 0 0x40000&gt;,</div><div class='add'>+				&lt;0x2 0x4000000 0 0x1000000&gt;;</div><div class='add'>+			reg-names = "asc", "sgx";</div><div class='add'>+			mboxes = &lt;&amp;agx_mbox&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_gfx&gt;;</div><div class='add'>+			memory-region = &lt;&amp;uat_ttbs&gt;, &lt;&amp;uat_pagetables&gt;, &lt;&amp;uat_handoff&gt;,</div><div class='add'>+					&lt;&amp;gpu_hw_cal_a&gt;, &lt;&amp;gpu_hw_cal_b&gt;, &lt;&amp;gpu_globals&gt;;</div><div class='add'>+			memory-region-names = "ttbs", "pagetables", "handoff",</div><div class='add'>+					      "hw-cal-a", "hw-cal-b", "globals";</div><div class='add'>+</div><div class='add'>+			apple,firmware-abi = &lt;0 0 0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		agx_mbox: mbox@206408000 {</div><div class='add'>+			compatible = "apple,t8103-asc-mailbox", "apple,asc-mailbox-v4";</div><div class='add'>+			reg = &lt;0x2 0x6408000 0x0 0x4000&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 709 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ 710 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ 711 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ 712 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "send-empty", "send-not-empty",</div><div class='add'>+				"recv-empty", "recv-not-empty";</div><div class='add'>+			#mbox-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpufreq_e: cpufreq@210e20000 {</div><div class='add'>+			compatible = "apple,t8112-cluster-cpufreq", "apple,cluster-cpufreq";</div><div class='add'>+			reg = &lt;0x2 0x10e20000 0 0x1000&gt;;</div><div class='add'>+			#performance-domain-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpufreq_p: cpufreq@211e20000 {</div><div class='add'>+			compatible = "apple,t8112-cluster-cpufreq", "apple,cluster-cpufreq";</div><div class='add'>+			reg = &lt;0x2 0x11e20000 0 0x1000&gt;;</div><div class='add'>+			#performance-domain-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display_dfr: display-pipe@228200000 {</div><div class='add'>+			compatible = "apple,t8112-display-pipe", "apple,h7-display-pipe";</div><div class='add'>+			reg = &lt;0x2 0x28200000 0x0 0xc000&gt;,</div><div class='add'>+			      &lt;0x2 0x28400000 0x0 0x4000&gt;;</div><div class='add'>+			reg-names = "be", "fe";</div><div class='add'>+			power-domains = &lt;&amp;ps_dispdfr_fe&gt;, &lt;&amp;ps_dispdfr_be&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 614 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 618 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "be", "fe";</div><div class='add'>+			iommus = &lt;&amp;displaydfr_dart 0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			port {</div><div class='add'>+				dfr_adp_out_mipi: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;dfr_mipi_in_adp&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		displaydfr_dart: iommu@228304000 {</div><div class='add'>+			compatible = "apple,t8110-dart";</div><div class='add'>+			reg = &lt;0x2 0x28304000 0x0 0x4000&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 616 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#iommu-cells = &lt;1&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_dispdfr_fe&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		displaydfr_mipi: dsi@228600000 {</div><div class='add'>+			compatible = "apple,t8112-display-pipe-mipi", "apple,h7-display-pipe-mipi";</div><div class='add'>+			reg = &lt;0x2 0x28600000 0x0 0x100000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_mipi_dsi&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				dfr_mipi_in: port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					dfr_mipi_in_adp: endpoint@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+						remote-endpoint = &lt;&amp;dfr_adp_out_mipi&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				dfr_mipi_out: port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sio_dart: iommu@235004000 {</div><div class='add'>+			compatible = "apple,t8110-dart";</div><div class='add'>+			reg = &lt;0x2 0x35004000 0x0 0x4000&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 769 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#iommu-cells = &lt;1&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_sio_cpu&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c0: i2c@235010000 {</div><div class='add'>+			compatible = "apple,t8112-i2c", "apple,i2c";</div><div class='add'>+			reg = &lt;0x2 0x35010000 0x0 0x4000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 761 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c0_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			#address-cells = &lt;0x1&gt;;</div><div class='add'>+			#size-cells = &lt;0x0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_i2c0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c1: i2c@235014000 {</div><div class='add'>+			compatible = "apple,t8112-i2c", "apple,i2c";</div><div class='add'>+			reg = &lt;0x2 0x35014000 0x0 0x4000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 762 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c1_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			#address-cells = &lt;0x1&gt;;</div><div class='add'>+			#size-cells = &lt;0x0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_i2c1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c2: i2c@235018000 {</div><div class='add'>+			compatible = "apple,t8112-i2c", "apple,i2c";</div><div class='add'>+			reg = &lt;0x2 0x35018000 0x0 0x4000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 763 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c2_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			#address-cells = &lt;0x1&gt;;</div><div class='add'>+			#size-cells = &lt;0x0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_i2c2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c3: i2c@23501c000 {</div><div class='add'>+			compatible = "apple,t8112-i2c", "apple,i2c";</div><div class='add'>+			reg = &lt;0x2 0x3501c000 0x0 0x4000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 764 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c3_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			#address-cells = &lt;0x1&gt;;</div><div class='add'>+			#size-cells = &lt;0x0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_i2c3&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c4: i2c@235020000 {</div><div class='add'>+			compatible = "apple,t8112-i2c", "apple,i2c";</div><div class='add'>+			reg = &lt;0x2 0x35020000 0x0 0x4000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 765 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c4_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			#address-cells = &lt;0x1&gt;;</div><div class='add'>+			#size-cells = &lt;0x0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_i2c4&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		fpwm1: pwm@235044000 {</div><div class='add'>+			compatible = "apple,t8112-fpwm", "apple,s5l-fpwm";</div><div class='add'>+			reg = &lt;0x2 0x35044000 0x0 0x4000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_fpwm1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			#pwm-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi1: spi@235104000 {</div><div class='add'>+			compatible = "apple,t8112-spi", "apple,spi";</div><div class='add'>+			reg = &lt;0x2 0x35104000 0x0 0x4000&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 749 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk_200m&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;spi1_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			power-domains = &lt;&amp;ps_spi1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi3: spi@23510c000 {</div><div class='add'>+			compatible = "apple,t8112-spi", "apple,spi";</div><div class='add'>+			reg = &lt;0x2 0x3510c000 0x0 0x4000&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 751 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;spi3_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			power-domains = &lt;&amp;ps_spi3&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled"; /* only used in J493 */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		serial0: serial@235200000 {</div><div class='add'>+			compatible = "apple,s5l-uart";</div><div class='add'>+			reg = &lt;0x2 0x35200000 0x0 0x1000&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 739 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			/*</div><div class='add'>+			 * TODO: figure out the clocking properly, there may</div><div class='add'>+			 * be a third selectable clock.</div><div class='add'>+			 */</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;, &lt;&amp;clkref&gt;;</div><div class='add'>+			clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+			power-domains = &lt;&amp;ps_uart0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		serial2: serial@235208000 {</div><div class='add'>+			compatible = "apple,s5l-uart";</div><div class='add'>+			reg = &lt;0x2 0x35208000 0x0 0x1000&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 741 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;, &lt;&amp;clkref&gt;;</div><div class='add'>+			clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+			power-domains = &lt;&amp;ps_uart2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		admac: dma-controller@238200000 {</div><div class='add'>+			compatible = "apple,t8112-admac", "apple,admac";</div><div class='add'>+			reg = &lt;0x2 0x38200000 0x0 0x34000&gt;;</div><div class='add'>+			dma-channels = &lt;24&gt;;</div><div class='add'>+			interrupts-extended = &lt;0&gt;,</div><div class='add'>+					      &lt;&amp;aic AIC_IRQ 760 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;0&gt;,</div><div class='add'>+					      &lt;0&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+			iommus = &lt;&amp;sio_dart 2&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_sio_adma&gt;;</div><div class='add'>+			resets = &lt;&amp;ps_audio_p&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mca: i2s@238400000 {</div><div class='add'>+			compatible = "apple,t8112-mca", "apple,mca";</div><div class='add'>+			reg = &lt;0x2 0x38400000 0x0 0x18000&gt;,</div><div class='add'>+			      &lt;0x2 0x38300000 0x0 0x30000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 753 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 754 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 755 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 756 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 757 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 758 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;ps_audio_p&gt;;</div><div class='add'>+			clocks = &lt;&amp;nco 0&gt;, &lt;&amp;nco 1&gt;, &lt;&amp;nco 2&gt;,</div><div class='add'>+				 &lt;&amp;nco 3&gt;, &lt;&amp;nco 4&gt;, &lt;&amp;nco 4&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_audio_p&gt;, &lt;&amp;ps_mca0&gt;, &lt;&amp;ps_mca1&gt;,</div><div class='add'>+					&lt;&amp;ps_mca2&gt;, &lt;&amp;ps_mca3&gt;, &lt;&amp;ps_mca4&gt;, &lt;&amp;ps_mca5&gt;;</div><div class='add'>+			dmas = &lt;&amp;admac 0&gt;, &lt;&amp;admac 1&gt;, &lt;&amp;admac 2&gt;, &lt;&amp;admac 3&gt;,</div><div class='add'>+			       &lt;&amp;admac 4&gt;, &lt;&amp;admac 5&gt;, &lt;&amp;admac 6&gt;, &lt;&amp;admac 7&gt;,</div><div class='add'>+			       &lt;&amp;admac 8&gt;, &lt;&amp;admac 9&gt;, &lt;&amp;admac 10&gt;, &lt;&amp;admac 11&gt;,</div><div class='add'>+			       &lt;&amp;admac 12&gt;, &lt;&amp;admac 13&gt;, &lt;&amp;admac 14&gt;, &lt;&amp;admac 15&gt;,</div><div class='add'>+			       &lt;&amp;admac 16&gt;, &lt;&amp;admac 17&gt;, &lt;&amp;admac 18&gt;, &lt;&amp;admac 19&gt;,</div><div class='add'>+			       &lt;&amp;admac 20&gt;, &lt;&amp;admac 21&gt;, &lt;&amp;admac 22&gt;, &lt;&amp;admac 23&gt;;</div><div class='add'>+			dma-names = "tx0a", "rx0a", "tx0b", "rx0b",</div><div class='add'>+				    "tx1a", "rx1a", "tx1b", "rx1b",</div><div class='add'>+				    "tx2a", "rx2a", "tx2b", "rx2b",</div><div class='add'>+				    "tx3a", "rx3a", "tx3b", "rx3b",</div><div class='add'>+				    "tx4a", "rx4a", "tx4b", "rx4b",</div><div class='add'>+				    "tx5a", "rx5a", "tx5b", "rx5b";</div><div class='add'>+</div><div class='add'>+			#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nco: clock-controller@23b044000 {</div><div class='add'>+			compatible = "apple,t8112-nco", "apple,nco";</div><div class='add'>+			reg = &lt;0x2 0x3b044000 0x0 0x14000&gt;;</div><div class='add'>+			clocks = &lt;&amp;nco_clkref&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aic: interrupt-controller@23b0c0000 {</div><div class='add'>+			compatible = "apple,t8112-aic", "apple,aic2";</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			reg = &lt;0x2 0x3b0c0000 0x0 0x8000&gt;,</div><div class='add'>+				&lt;0x2 0x3b0c8000 0x0 0x4&gt;;</div><div class='add'>+			reg-names = "core", "event";</div><div class='add'>+			power-domains = &lt;&amp;ps_aic&gt;;</div><div class='add'>+</div><div class='add'>+			affinities {</div><div class='add'>+				e-core-pmu-affinity {</div><div class='add'>+					apple,fiq-index = &lt;AIC_CPU_PMU_E&gt;;</div><div class='add'>+					cpus = &lt;&amp;cpu_e0 &amp;cpu_e1 &amp;cpu_e2 &amp;cpu_e3&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				p-core-pmu-affinity {</div><div class='add'>+					apple,fiq-index = &lt;AIC_CPU_PMU_P&gt;;</div><div class='add'>+					cpus = &lt;&amp;cpu_p0 &amp;cpu_p1 &amp;cpu_p2 &amp;cpu_p3&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmgr: power-management@23b700000 {</div><div class='add'>+			compatible = "apple,t8112-pmgr", "apple,pmgr", "syscon", "simple-mfd";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			reg = &lt;0x2 0x3b700000 0 0x14000&gt;;</div><div class='add'>+			/* child nodes are added in t8103-pmgr.dtsi */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_ap: pinctrl@23c100000 {</div><div class='add'>+			compatible = "apple,t8112-pinctrl", "apple,pinctrl";</div><div class='add'>+			reg = &lt;0x2 0x3c100000 0x0 0x100000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_gpio&gt;;</div><div class='add'>+</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;pinctrl_ap 0 0 213&gt;;</div><div class='add'>+			apple,npins = &lt;213&gt;;</div><div class='add'>+</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 199 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 200 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 201 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 202 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 203 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 204 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 205 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			i2c0_pins: i2c0-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(111, 1)&gt;,</div><div class='add'>+					 &lt;APPLE_PINMUX(110, 1)&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c1_pins: i2c1-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(113, 1)&gt;,</div><div class='add'>+					 &lt;APPLE_PINMUX(112, 1)&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c2_pins: i2c2-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(87, 1)&gt;,</div><div class='add'>+					 &lt;APPLE_PINMUX(86, 1)&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c3_pins: i2c3-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(54, 1)&gt;,</div><div class='add'>+					 &lt;APPLE_PINMUX(53, 1)&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c4_pins: i2c4-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(131, 1)&gt;,</div><div class='add'>+					 &lt;APPLE_PINMUX(130, 1)&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi1_pins: spi1-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(46, 1)&gt;,</div><div class='add'>+					&lt;APPLE_PINMUX(47, 1)&gt;,</div><div class='add'>+					&lt;APPLE_PINMUX(48, 1)&gt;,</div><div class='add'>+					&lt;APPLE_PINMUX(49, 1)&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi3_pins: spi3-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(93, 1)&gt;,</div><div class='add'>+					&lt;APPLE_PINMUX(94, 1)&gt;,</div><div class='add'>+					&lt;APPLE_PINMUX(95, 1)&gt;,</div><div class='add'>+					&lt;APPLE_PINMUX(96, 1)&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pcie_pins: pcie-pins {</div><div class='add'>+				pinmux = &lt;APPLE_PINMUX(162, 1)&gt;,</div><div class='add'>+					 &lt;APPLE_PINMUX(163, 1)&gt;,</div><div class='add'>+					 &lt;APPLE_PINMUX(164, 1)&gt;;</div><div class='add'>+				// TODO: 1 more CLKREQs</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_nub: pinctrl@23d1f0000 {</div><div class='add'>+			compatible = "apple,t8112-pinctrl", "apple,pinctrl";</div><div class='add'>+			reg = &lt;0x2 0x3d1f0000 0x0 0x4000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_nub_gpio&gt;;</div><div class='add'>+</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;pinctrl_nub 0 0 24&gt;;</div><div class='add'>+			apple,npins = &lt;24&gt;;</div><div class='add'>+</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 371 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 372 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 373 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 374 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 375 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 376 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 377 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmgr_mini: power-management@23d280000 {</div><div class='add'>+			compatible = "apple,t8112-pmgr", "apple,pmgr", "syscon", "simple-mfd";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			reg = &lt;0x2 0x3d280000 0 0x4000&gt;;</div><div class='add'>+			/* child nodes are added in t8103-pmgr.dtsi */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wdt: watchdog@23d2b0000 {</div><div class='add'>+			compatible = "apple,t8112-wdt", "apple,wdt";</div><div class='add'>+			reg = &lt;0x2 0x3d2b0000 0x0 0x4000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkref&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 379 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nub_spmi: spmi@23d714000 {</div><div class='add'>+			compatible = "apple,t8112-spmi", "apple,spmi";</div><div class='add'>+			reg = &lt;0x2 0x3d714000 0x0 0x100&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			pmic1: pmic@e {</div><div class='add'>+				compatible = "apple,stowe-pmic", "apple,spmi-nvmem";</div><div class='add'>+				reg = &lt;0xe SPMI_USID&gt;;</div><div class='add'>+</div><div class='add'>+				nvmem-layout {</div><div class='add'>+					compatible = "fixed-layout";</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					fault_shadow: fault-shadow@867b {</div><div class='add'>+						reg = &lt;0x867b 0x10&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					socd: socd@8b00 {</div><div class='add'>+						reg = &lt;0x8b00 0x400&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					boot_stage: boot-stage@f701 {</div><div class='add'>+						reg = &lt;0xf701 0x1&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					boot_error_count: boot-error-count@f702,0 {</div><div class='add'>+						reg = &lt;0xf702 0x1&gt;;</div><div class='add'>+						bits = &lt;0 4&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					panic_count: panic-count@f702,4 {</div><div class='add'>+						reg = &lt;0xf702 0x1&gt;;</div><div class='add'>+						bits = &lt;4 4&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					boot_error_stage: boot-error-stage@f703 {</div><div class='add'>+						reg = &lt;0xf703 0x1&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					shutdown_flag: shutdown-flag@f70f,3 {</div><div class='add'>+						reg = &lt;0xf70f 0x1&gt;;</div><div class='add'>+						bits = &lt;3 1&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					pm_setting: pm-setting@f801 {</div><div class='add'>+						reg = &lt;0xf801 0x1&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					rtc_offset: rtc-offset@f900 {</div><div class='add'>+						reg = &lt;0xf900 0x6&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smc: smc@23e400000 {</div><div class='add'>+			compatible = "apple,t8112-smc", "apple,smc";</div><div class='add'>+			reg = &lt;0x2 0x3e400000 0x0 0x4000&gt;,</div><div class='add'>+				&lt;0x2 0x3fe00000 0x0 0x100000&gt;;</div><div class='add'>+			reg-names = "smc", "sram";</div><div class='add'>+			mboxes = &lt;&amp;smc_mbox&gt;;</div><div class='add'>+</div><div class='add'>+			smc_gpio: gpio {</div><div class='add'>+				compatible = "apple,smc-gpio";</div><div class='add'>+				gpio-controller;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			smc_reboot: reboot {</div><div class='add'>+				compatible = "apple,smc-reboot";</div><div class='add'>+				nvmem-cells = &lt;&amp;shutdown_flag&gt;, &lt;&amp;boot_stage&gt;,</div><div class='add'>+					&lt;&amp;boot_error_count&gt;, &lt;&amp;panic_count&gt;;</div><div class='add'>+				nvmem-cell-names = "shutdown_flag", "boot_stage",</div><div class='add'>+					"boot_error_count", "panic_count";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smc_mbox: mbox@23e408000 {</div><div class='add'>+			compatible = "apple,t8112-asc-mailbox", "apple,asc-mailbox-v4";</div><div class='add'>+			reg = &lt;0x2 0x3e408000 0x0 0x4000&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 499 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ 500 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ 501 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ 502 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "send-empty", "send-not-empty",</div><div class='add'>+				"recv-empty", "recv-not-empty";</div><div class='add'>+			#mbox-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_smc: pinctrl@23e820000 {</div><div class='add'>+			compatible = "apple,t8112-pinctrl", "apple,pinctrl";</div><div class='add'>+			reg = &lt;0x2 0x3e820000 0x0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;pinctrl_smc 0 0 18&gt;;</div><div class='add'>+			apple,npins = &lt;18&gt;;</div><div class='add'>+</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 490 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 491 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 492 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 493 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 494 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 495 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 496 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_aop: pinctrl@24a820000 {</div><div class='add'>+			compatible = "apple,t8112-pinctrl", "apple,pinctrl";</div><div class='add'>+			reg = &lt;0x2 0x4a820000 0x0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;pinctrl_aop 0 0 54&gt;;</div><div class='add'>+			apple,npins = &lt;54&gt;;</div><div class='add'>+</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 301 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 302 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 303 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 304 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 305 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 306 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 307 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ans_mbox: mbox@277408000 {</div><div class='add'>+			compatible = "apple,t8112-asc-mailbox", "apple,asc-mailbox-v4";</div><div class='add'>+			reg = &lt;0x2 0x77408000 0x0 0x4000&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 717 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ 718 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ 719 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;AIC_IRQ 720 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "send-empty", "send-not-empty",</div><div class='add'>+				"recv-empty", "recv-not-empty";</div><div class='add'>+			#mbox-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_ans&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sart: sart@27bc50000 {</div><div class='add'>+			compatible = "apple,t8112-sart", "apple,t6000-sart";</div><div class='add'>+			reg = &lt;0x2 0x7bc50000 0x0 0x10000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_ans&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nvme@27bcc0000 {</div><div class='add'>+			compatible = "apple,t8112-nvme-ans2", "apple,nvme-ans2";</div><div class='add'>+			reg = &lt;0x2 0x7bcc0000 0x0 0x40000&gt;,</div><div class='add'>+				&lt;0x2 0x77400000 0x0 0x4000&gt;;</div><div class='add'>+			reg-names = "nvme", "ans";</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 724 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			mboxes = &lt;&amp;ans_mbox&gt;;</div><div class='add'>+			apple,sart = &lt;&amp;sart&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_ans&gt;, &lt;&amp;ps_apcie_st&gt;;</div><div class='add'>+			power-domain-names = "ans", "apcie0";</div><div class='add'>+			resets = &lt;&amp;ps_ans&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie0_dart: iommu@681008000 {</div><div class='add'>+			compatible = "apple,t8110-dart";</div><div class='add'>+			reg = &lt;0x6 0x81008000 0x0 0x4000&gt;;</div><div class='add'>+			#iommu-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 782 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_apcie_gp&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie1_dart: iommu@682008000 {</div><div class='add'>+			compatible = "apple,t8110-dart";</div><div class='add'>+			reg = &lt;0x6 0x82008000 0x0 0x4000&gt;;</div><div class='add'>+			#iommu-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 785 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_apcie_gp&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie2_dart: iommu@683008000 {</div><div class='add'>+			compatible = "apple,t8110-dart";</div><div class='add'>+			reg = &lt;0x6 0x83008000 0x0 0x4000&gt;;</div><div class='add'>+			#iommu-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 788 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_apcie_gp&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie3_dart: iommu@684008000 {</div><div class='add'>+			compatible = "apple,t8110-dart";</div><div class='add'>+			reg = &lt;0x6 0x84008000 0x0 0x4000&gt;;</div><div class='add'>+			#iommu-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 791 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			power-domains = &lt;&amp;ps_apcie_gp&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie0: pcie@690000000 {</div><div class='add'>+			compatible = "apple,t8112-pcie", "apple,pcie";</div><div class='add'>+			device_type = "pci";</div><div class='add'>+</div><div class='add'>+			reg = &lt;0x6 0x90000000 0x0 0x1000000&gt;,</div><div class='add'>+			      &lt;0x6 0x80000000 0x0 0x100000&gt;,</div><div class='add'>+			      &lt;0x6 0x81000000 0x0 0x4000&gt;,</div><div class='add'>+			      &lt;0x6 0x82000000 0x0 0x4000&gt;,</div><div class='add'>+			      &lt;0x6 0x83000000 0x0 0x4000&gt;,</div><div class='add'>+			      &lt;0x6 0x84000000 0x0 0x4000&gt;;</div><div class='add'>+			reg-names = "config", "rc", "port0", "port1", "port2", "port3";</div><div class='add'>+</div><div class='add'>+			interrupt-parent = &lt;&amp;aic&gt;;</div><div class='add'>+			interrupts = &lt;AIC_IRQ 781 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 784 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 787 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;AIC_IRQ 790 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			msi-controller;</div><div class='add'>+			msi-parent = &lt;&amp;pcie0&gt;;</div><div class='add'>+			msi-ranges = &lt;&amp;aic AIC_IRQ 793 IRQ_TYPE_EDGE_RISING 32&gt;;</div><div class='add'>+</div><div class='add'>+			iommu-map = &lt;0x100 &amp;pcie0_dart 0 1&gt;,</div><div class='add'>+				    &lt;0x200 &amp;pcie1_dart 1 1&gt;,</div><div class='add'>+				    &lt;0x300 &amp;pcie2_dart 2 1&gt;,</div><div class='add'>+				    &lt;0x400 &amp;pcie3_dart 3 1&gt;;</div><div class='add'>+			iommu-map-mask = &lt;0xff00&gt;;</div><div class='add'>+</div><div class='add'>+			bus-range = &lt;0 4&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges = &lt;0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000&gt;,</div><div class='add'>+				 &lt;0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000&gt;;</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;ps_apcie_gp&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;pcie_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+			port00: pci@0,0 {</div><div class='add'>+				device_type = "pci";</div><div class='add'>+				reg = &lt;0x0 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+				reset-gpios = &lt;&amp;pinctrl_ap 166 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;3&gt;;</div><div class='add'>+				#size-cells = &lt;2&gt;;</div><div class='add'>+				ranges;</div><div class='add'>+</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='add'>+				interrupt-map = &lt;0 0 0 1 &amp;port00 0 0 0 0&gt;,</div><div class='add'>+						&lt;0 0 0 2 &amp;port00 0 0 0 1&gt;,</div><div class='add'>+						&lt;0 0 0 3 &amp;port00 0 0 0 2&gt;,</div><div class='add'>+						&lt;0 0 0 4 &amp;port00 0 0 0 3&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port01: pci@1,0 {</div><div class='add'>+				device_type = "pci";</div><div class='add'>+				reg = &lt;0x800 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+				reset-gpios = &lt;&amp;pinctrl_ap 167 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;3&gt;;</div><div class='add'>+				#size-cells = &lt;2&gt;;</div><div class='add'>+				ranges;</div><div class='add'>+</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='add'>+				interrupt-map = &lt;0 0 0 1 &amp;port01 0 0 0 0&gt;,</div><div class='add'>+						&lt;0 0 0 2 &amp;port01 0 0 0 1&gt;,</div><div class='add'>+						&lt;0 0 0 3 &amp;port01 0 0 0 2&gt;,</div><div class='add'>+						&lt;0 0 0 4 &amp;port01 0 0 0 3&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port02: pci@2,0 {</div><div class='add'>+				device_type = "pci";</div><div class='add'>+				reg = &lt;0x1000 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+				reset-gpios = &lt;&amp;pinctrl_ap 168 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;3&gt;;</div><div class='add'>+				#size-cells = &lt;2&gt;;</div><div class='add'>+				ranges;</div><div class='add'>+</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='add'>+				interrupt-map = &lt;0 0 0 1 &amp;port02 0 0 0 0&gt;,</div><div class='add'>+						&lt;0 0 0 2 &amp;port02 0 0 0 1&gt;,</div><div class='add'>+						&lt;0 0 0 3 &amp;port02 0 0 0 2&gt;,</div><div class='add'>+						&lt;0 0 0 4 &amp;port02 0 0 0 3&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* TODO: GPIO unknown */</div><div class='add'>+			port03: pci@3,0 {</div><div class='add'>+				device_type = "pci";</div><div class='add'>+				reg = &lt;0x1800 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+				//reset-gpios = &lt;&amp;pinctrl_ap 33 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;3&gt;;</div><div class='add'>+				#size-cells = &lt;2&gt;;</div><div class='add'>+				ranges;</div><div class='add'>+</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='add'>+				interrupt-map = &lt;0 0 0 1 &amp;port03 0 0 0 0&gt;,</div><div class='add'>+						&lt;0 0 0 2 &amp;port03 0 0 0 1&gt;,</div><div class='add'>+						&lt;0 0 0 3 &amp;port03 0 0 0 2&gt;,</div><div class='add'>+						&lt;0 0 0 4 &amp;port03 0 0 0 3&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include "t8112-pmgr.dtsi"</div><div class='head'>diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile<br/>index 800da2e84f3f..f30ee045dc95 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/arm/Makefile?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/arm/Makefile</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/arm/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/arm/Makefile</a></div><div class='hunk'>@@ -2,7 +2,9 @@</div><div class='ctx'> dtb-$(CONFIG_ARCH_VEXPRESS) += \</div><div class='ctx'> 	foundation-v8.dtb foundation-v8-psci.dtb \</div><div class='ctx'> 	foundation-v8-gicv3.dtb foundation-v8-gicv3-psci.dtb</div><div class='del'>-dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb juno-r2.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb juno-r2.dtb juno-scmi.dtb juno-r1-scmi.dtb juno-r2-scmi.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-revc.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_VEXPRESS) += corstone1000-fvp.dtb corstone1000-mps3.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_VEXPRESS) += morello-sdp.dtb morello-fvp.dtb</div><div class='head'>diff --git a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts<br/>new file mode 100644<br/>index 000000000000..66ba6b027193<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/arm/corstone1000-fvp.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/arm/corstone1000-fvp.dts</a></div><div class='hunk'>@@ -0,0 +1,77 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0 OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2022, Arm Limited. All rights reserved.</div><div class='add'>+ * Copyright (c) 2022, Linaro Limited. All rights reserved.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "corstone1000.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "ARM Corstone1000 FVP (Fixed Virtual Platform)";</div><div class='add'>+	compatible = "arm,corstone1000-fvp";</div><div class='add'>+</div><div class='add'>+	smsc: ethernet@4010000 {</div><div class='add'>+		compatible = "smsc,lan91c111";</div><div class='add'>+		reg = &lt;0x40100000 0x10000&gt;;</div><div class='add'>+		phy-mode = "mii";</div><div class='add'>+		interrupts = &lt;GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		reg-io-width = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vmmc_v3_3d: regulator-vmmc {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vmmc_supply";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdmmc0: mmc@40300000 {</div><div class='add'>+		compatible = "arm,pl18x", "arm,primecell";</div><div class='add'>+		reg = &lt;0x40300000 0x1000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		max-frequency = &lt;12000000&gt;;</div><div class='add'>+		vmmc-supply = &lt;&amp;vmmc_v3_3d&gt;;</div><div class='add'>+		clocks = &lt;&amp;smbclk&gt;, &lt;&amp;refclk100mhz&gt;;</div><div class='add'>+		clock-names = "smclk", "apb_pclk";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdmmc1: mmc@50000000 {</div><div class='add'>+		compatible = "arm,pl18x", "arm,primecell";</div><div class='add'>+		reg = &lt;0x50000000 0x10000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		max-frequency = &lt;12000000&gt;;</div><div class='add'>+		vmmc-supply = &lt;&amp;vmmc_v3_3d&gt;;</div><div class='add'>+		clocks = &lt;&amp;smbclk&gt;, &lt;&amp;refclk100mhz&gt;;</div><div class='add'>+		clock-names = "smclk", "apb_pclk";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpus {</div><div class='add'>+	cpu1: cpu@1 {</div><div class='add'>+		device_type = "cpu";</div><div class='add'>+		compatible = "arm,cortex-a35";</div><div class='add'>+		reg = &lt;0x1&gt;;</div><div class='add'>+		enable-method = "psci";</div><div class='add'>+		next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpu2: cpu@2 {</div><div class='add'>+		device_type = "cpu";</div><div class='add'>+		compatible = "arm,cortex-a35";</div><div class='add'>+		reg = &lt;0x2&gt;;</div><div class='add'>+		enable-method = "psci";</div><div class='add'>+		next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpu3: cpu@3 {</div><div class='add'>+		device_type = "cpu";</div><div class='add'>+		compatible = "arm,cortex-a35";</div><div class='add'>+		reg = &lt;0x3&gt;;</div><div class='add'>+		enable-method = "psci";</div><div class='add'>+		next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/arm/corstone1000-mps3.dts b/arch/arm64/boot/dts/arm/corstone1000-mps3.dts<br/>new file mode 100644<br/>index 000000000000..10d265be0c02<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/arm/corstone1000-mps3.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/arm/corstone1000-mps3.dts</a></div><div class='hunk'>@@ -0,0 +1,32 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0 OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2022, Arm Limited. All rights reserved.</div><div class='add'>+ * Copyright (c) 2022, Linaro Limited. All rights reserved.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "corstone1000.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "ARM Corstone1000 FPGA MPS3 board";</div><div class='add'>+	compatible = "arm,corstone1000-mps3";</div><div class='add'>+</div><div class='add'>+	smsc: ethernet@4010000 {</div><div class='add'>+		compatible = "smsc,lan9220", "smsc,lan9115";</div><div class='add'>+		reg = &lt;0x40100000 0x10000&gt;;</div><div class='add'>+		phy-mode = "mii";</div><div class='add'>+		interrupts = &lt;GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		reg-io-width = &lt;2&gt;;</div><div class='add'>+		smsc,irq-push-pull;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb_host: usb@40200000 {</div><div class='add'>+		compatible = "nxp,usb-isp1763";</div><div class='add'>+		reg = &lt;0x40200000 0x100000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		bus-width = &lt;16&gt;;</div><div class='add'>+		dr_mode = "host";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/arm/corstone1000.dtsi b/arch/arm64/boot/dts/arm/corstone1000.dtsi<br/>new file mode 100644<br/>index 000000000000..f35a5c96f3da<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/arm/corstone1000.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/arm/corstone1000.dtsi</a></div><div class='hunk'>@@ -0,0 +1,161 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0 OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2022, Arm Limited. All rights reserved.</div><div class='add'>+ * Copyright (c) 2022, Linaro Limited. All rights reserved.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+		serial1 = &amp;uart1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus: cpus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a35";</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@88200000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x88200000 0x77e00000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gic: interrupt-controller@1c000000 {</div><div class='add'>+		compatible = "arm,gic-400";</div><div class='add'>+		#interrupt-cells = &lt;3&gt;;</div><div class='add'>+		#address-cells = &lt;0&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		reg = &lt;0x1c010000 0x1000&gt;,</div><div class='add'>+		      &lt;0x1c02f000 0x2000&gt;,</div><div class='add'>+		      &lt;0x1c04f000 0x1000&gt;,</div><div class='add'>+		      &lt;0x1c06f000 0x2000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |</div><div class='add'>+			      IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	L2_0: l2-cache0 {</div><div class='add'>+		compatible = "cache";</div><div class='add'>+		cache-unified;</div><div class='add'>+		cache-level = &lt;2&gt;;</div><div class='add'>+		cache-size = &lt;0x80000&gt;;</div><div class='add'>+		cache-line-size = &lt;64&gt;;</div><div class='add'>+		cache-sets = &lt;1024&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	refclk100mhz: clock-100000000 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;100000000&gt;;</div><div class='add'>+		clock-output-names = "apb_pclk";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	smbclk: clock-48000000 {</div><div class='add'>+		/* Reference 24MHz clock x 2 */</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;48000000&gt;;</div><div class='add'>+		clock-output-names = "smclk";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uartclk: clock-50000000 {</div><div class='add'>+		/* UART clock - 50MHz */</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;50000000&gt;;</div><div class='add'>+		clock-output-names = "uartclk";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-1.0", "arm,psci-0.2";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		timer@1a220000 {</div><div class='add'>+			compatible = "arm,armv7-timer-mem";</div><div class='add'>+			reg = &lt;0x1a220000 0x1000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			frame@1a230000 {</div><div class='add'>+				frame-number = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				reg = &lt;0x1a230000 0x1000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart0: serial@1a510000 {</div><div class='add'>+			compatible = "arm,pl011", "arm,primecell";</div><div class='add'>+			reg = &lt;0x1a510000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;uartclk&gt;, &lt;&amp;refclk100mhz&gt;;</div><div class='add'>+			clock-names = "uartclk", "apb_pclk";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart1: serial@1a520000 {</div><div class='add'>+			compatible = "arm,pl011", "arm,primecell";</div><div class='add'>+			reg = &lt;0x1a520000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;uartclk&gt;, &lt;&amp;refclk100mhz&gt;;</div><div class='add'>+			clock-names = "uartclk", "apb_pclk";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mhu_hse1: mailbox@1b820000 {</div><div class='add'>+			compatible = "arm,mhuv2-tx", "arm,primecell";</div><div class='add'>+			reg = &lt;0x1b820000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;refclk100mhz&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			interrupts = &lt;GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#mbox-cells = &lt;2&gt;;</div><div class='add'>+			arm,mhuv2-protocols = &lt;0 0&gt;;</div><div class='add'>+			secure-status = "okay";     /* secure-world-only */</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mhu_seh1: mailbox@1b830000 {</div><div class='add'>+			compatible = "arm,mhuv2-rx", "arm,primecell";</div><div class='add'>+			reg = &lt;0x1b830000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;refclk100mhz&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			interrupts = &lt;GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#mbox-cells = &lt;2&gt;;</div><div class='add'>+			arm,mhuv2-protocols = &lt;0 0&gt;;</div><div class='add'>+			secure-status = "okay";     /* secure-world-only */</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/arm/foundation-v8-gicv2.dtsi b/arch/arm64/boot/dts/arm/foundation-v8-gicv2.dtsi<br/>index 15fe81738e94..655fdcce1561 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/arm/foundation-v8-gicv2.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/arm/foundation-v8-gicv2.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/arm/foundation-v8-gicv2.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/arm/foundation-v8-gicv2.dtsi</a></div><div class='hunk'>@@ -6,9 +6,9 @@</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	gic: interrupt-controller@2c001000 {</div><div class='del'>-		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";</div><div class='add'>+		compatible = "arm,gic-400", "arm,cortex-a15-gic";</div><div class='ctx'> 		#interrupt-cells = &lt;3&gt;;</div><div class='del'>-		#address-cells = &lt;2&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		interrupt-controller;</div><div class='ctx'> 		reg = &lt;0x0 0x2c001000 0 0x1000&gt;,</div><div class='ctx'> 		      &lt;0x0 0x2c002000 0 0x2000&gt;,</div><div class='head'>diff --git a/arch/arm64/boot/dts/arm/foundation-v8-gicv3.dtsi b/arch/arm64/boot/dts/arm/foundation-v8-gicv3.dtsi<br/>index f2c75c756039..17fba3bc99cd 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/arm/foundation-v8-gicv3.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/arm/foundation-v8-gicv3.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/arm/foundation-v8-gicv3.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/arm/foundation-v8-gicv3.dtsi</a></div><div class='hunk'>@@ -8,21 +8,22 @@</div><div class='ctx'> 	gic: interrupt-controller@2f000000 {</div><div class='ctx'> 		compatible = "arm,gic-v3";</div><div class='ctx'> 		#interrupt-cells = &lt;3&gt;;</div><div class='del'>-		#address-cells = &lt;2&gt;;</div><div class='del'>-		#size-cells = &lt;2&gt;;</div><div class='del'>-		ranges;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges = &lt;0x0 0x0 0x2f000000 0x100000&gt;;</div><div class='ctx'> 		interrupt-controller;</div><div class='del'>-		reg =	&lt;0x0 0x2f000000 0x0 0x10000&gt;,</div><div class='del'>-			&lt;0x0 0x2f100000 0x0 0x200000&gt;,</div><div class='del'>-			&lt;0x0 0x2c000000 0x0 0x2000&gt;,</div><div class='del'>-			&lt;0x0 0x2c010000 0x0 0x2000&gt;,</div><div class='del'>-			&lt;0x0 0x2c02f000 0x0 0x2000&gt;;</div><div class='add'>+		reg = &lt;0x0 0x2f000000 0x0 0x10000&gt;,</div><div class='add'>+		      &lt;0x0 0x2f100000 0x0 0x200000&gt;,</div><div class='add'>+		      &lt;0x0 0x2c000000 0x0 0x2000&gt;,</div><div class='add'>+		      &lt;0x0 0x2c010000 0x0 0x2000&gt;,</div><div class='add'>+		      &lt;0x0 0x2c02f000 0x0 0x2000&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> </div><div class='del'>-		its: its@2f020000 {</div><div class='add'>+		its: msi-controller@2f020000 {</div><div class='ctx'> 			compatible = "arm,gic-v3-its";</div><div class='ctx'> 			msi-controller;</div><div class='del'>-			reg = &lt;0x0 0x2f020000 0x0 0x20000&gt;;</div><div class='add'>+			#msi-cells = &lt;1&gt;;</div><div class='add'>+			reg = &lt;0x20000 0x20000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dtsi b/arch/arm64/boot/dts/arm/foundation-v8.dtsi<br/>index 12f039fa3dad..a4b2b78d4df3 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/arm/foundation-v8.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/arm/foundation-v8.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/arm/foundation-v8.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/arm/foundation-v8.dtsi</a></div><div class='hunk'>@@ -18,7 +18,9 @@</div><div class='ctx'> 	#address-cells = &lt;2&gt;;</div><div class='ctx'> 	#size-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='del'>-	chosen { };</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='ctx'> </div><div class='ctx'> 	aliases {</div><div class='ctx'> 		serial0 = &amp;v2m_serial0;</div><div class='hunk'>@@ -58,6 +60,8 @@</div><div class='ctx'> </div><div class='ctx'> 		L2_0: l2-cache0 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -73,7 +77,6 @@</div><div class='ctx'> 			     &lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='ctx'> 			     &lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='ctx'> 			     &lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='del'>-		clock-frequency = &lt;100000000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	pmu {</div><div class='hunk'>@@ -84,6 +87,11 @@</div><div class='ctx'> 			     &lt;GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	spe-pmu {</div><div class='add'>+		compatible = "arm,statistical-profiling-extension-v1";</div><div class='add'>+		interrupts = &lt;GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	watchdog@2a440000 {</div><div class='ctx'> 		compatible = "arm,sbsa-gwdt";</div><div class='ctx'> 		reg = &lt;0x0 0x2a440000 0 0x1000&gt;,</div><div class='hunk'>@@ -92,9 +100,29 @@</div><div class='ctx'> 		timeout-sec = &lt;30&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	v2m_clk24mhz: clock-24000000 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+		clock-output-names = "v2m:clk24mhz";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	v2m_refclk1mhz: clock-1000000 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;1000000&gt;;</div><div class='add'>+		clock-output-names = "v2m:refclk1mhz";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	v2m_refclk32khz: clock-32768 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;32768&gt;;</div><div class='add'>+		clock-output-names = "v2m:refclk32khz";</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	bus@8000000 {</div><div class='ctx'> 		compatible = "arm,vexpress,v2m-p1", "simple-bus";</div><div class='del'>-		arm,v2m-memory-map = "rs1";</div><div class='ctx'> 		#address-cells = &lt;2&gt;; /* SMB chipselect number and offset */</div><div class='ctx'> 		#size-cells = &lt;1&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -107,78 +135,57 @@</div><div class='ctx'> </div><div class='ctx'> 		#interrupt-cells = &lt;1&gt;;</div><div class='ctx'> 		interrupt-map-mask = &lt;0 0 63&gt;;</div><div class='del'>-		interrupt-map = &lt;0 0  0 &amp;gic 0 0 GIC_SPI  0 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0  1 &amp;gic 0 0 GIC_SPI  1 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0  2 &amp;gic 0 0 GIC_SPI  2 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0  3 &amp;gic 0 0 GIC_SPI  3 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0  4 &amp;gic 0 0 GIC_SPI  4 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0  5 &amp;gic 0 0 GIC_SPI  5 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0  6 &amp;gic 0 0 GIC_SPI  6 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0  7 &amp;gic 0 0 GIC_SPI  7 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0  8 &amp;gic 0 0 GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0  9 &amp;gic 0 0 GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 10 &amp;gic 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 11 &amp;gic 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 12 &amp;gic 0 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 13 &amp;gic 0 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 14 &amp;gic 0 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 15 &amp;gic 0 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 16 &amp;gic 0 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 17 &amp;gic 0 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 18 &amp;gic 0 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 19 &amp;gic 0 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 20 &amp;gic 0 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 21 &amp;gic 0 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 22 &amp;gic 0 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 23 &amp;gic 0 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 24 &amp;gic 0 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 25 &amp;gic 0 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 26 &amp;gic 0 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 27 &amp;gic 0 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 28 &amp;gic 0 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 29 &amp;gic 0 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 30 &amp;gic 0 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 31 &amp;gic 0 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 32 &amp;gic 0 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 33 &amp;gic 0 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 34 &amp;gic 0 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 35 &amp;gic 0 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 36 &amp;gic 0 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 37 &amp;gic 0 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 38 &amp;gic 0 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 39 &amp;gic 0 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 40 &amp;gic 0 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 41 &amp;gic 0 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 42 &amp;gic 0 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-</div><div class='del'>-		ethernet@2,02000000 {</div><div class='add'>+		interrupt-map = &lt;0 0  0 &amp;gic 0 GIC_SPI  0 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0  1 &amp;gic 0 GIC_SPI  1 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0  2 &amp;gic 0 GIC_SPI  2 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0  3 &amp;gic 0 GIC_SPI  3 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0  4 &amp;gic 0 GIC_SPI  4 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0  5 &amp;gic 0 GIC_SPI  5 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0  6 &amp;gic 0 GIC_SPI  6 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0  7 &amp;gic 0 GIC_SPI  7 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0  8 &amp;gic 0 GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0  9 &amp;gic 0 GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 10 &amp;gic 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 11 &amp;gic 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 12 &amp;gic 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 13 &amp;gic 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 14 &amp;gic 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 15 &amp;gic 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 16 &amp;gic 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 17 &amp;gic 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 18 &amp;gic 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 19 &amp;gic 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 20 &amp;gic 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 21 &amp;gic 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 22 &amp;gic 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 23 &amp;gic 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 24 &amp;gic 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 25 &amp;gic 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 26 &amp;gic 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 27 &amp;gic 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 28 &amp;gic 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 29 &amp;gic 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 30 &amp;gic 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 31 &amp;gic 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 32 &amp;gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 33 &amp;gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 34 &amp;gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 35 &amp;gic 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 36 &amp;gic 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 37 &amp;gic 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 38 &amp;gic 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 39 &amp;gic 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 40 &amp;gic 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 41 &amp;gic 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 42 &amp;gic 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+		ethernet@202000000 {</div><div class='ctx'> 			compatible = "smsc,lan91c111";</div><div class='ctx'> 			reg = &lt;2 0x02000000 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;15&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		v2m_clk24mhz: clk24mhz {</div><div class='del'>-			compatible = "fixed-clock";</div><div class='del'>-			#clock-cells = &lt;0&gt;;</div><div class='del'>-			clock-frequency = &lt;24000000&gt;;</div><div class='del'>-			clock-output-names = "v2m:clk24mhz";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		v2m_refclk1mhz: refclk1mhz {</div><div class='del'>-			compatible = "fixed-clock";</div><div class='del'>-			#clock-cells = &lt;0&gt;;</div><div class='del'>-			clock-frequency = &lt;1000000&gt;;</div><div class='del'>-			clock-output-names = "v2m:refclk1mhz";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		v2m_refclk32khz: refclk32khz {</div><div class='del'>-			compatible = "fixed-clock";</div><div class='del'>-			#clock-cells = &lt;0&gt;;</div><div class='del'>-			clock-frequency = &lt;32768&gt;;</div><div class='del'>-			clock-output-names = "v2m:refclk32khz";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		iofpga@3,00000000 {</div><div class='add'>+		iofpga-bus@300000000 {</div><div class='ctx'> 			compatible = "simple-bus";</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;1&gt;;</div><div class='hunk'>@@ -189,7 +196,7 @@</div><div class='ctx'> 				reg = &lt;0x010000 0x1000&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			v2m_serial0: uart@90000 {</div><div class='add'>+			v2m_serial0: serial@90000 {</div><div class='ctx'> 				compatible = "arm,pl011", "arm,primecell";</div><div class='ctx'> 				reg = &lt;0x090000 0x1000&gt;;</div><div class='ctx'> 				interrupts = &lt;5&gt;;</div><div class='hunk'>@@ -197,7 +204,7 @@</div><div class='ctx'> 				clock-names = "uartclk", "apb_pclk";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			v2m_serial1: uart@a0000 {</div><div class='add'>+			v2m_serial1: serial@a0000 {</div><div class='ctx'> 				compatible = "arm,pl011", "arm,primecell";</div><div class='ctx'> 				reg = &lt;0x0a0000 0x1000&gt;;</div><div class='ctx'> 				interrupts = &lt;6&gt;;</div><div class='hunk'>@@ -205,7 +212,7 @@</div><div class='ctx'> 				clock-names = "uartclk", "apb_pclk";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			v2m_serial2: uart@b0000 {</div><div class='add'>+			v2m_serial2: serial@b0000 {</div><div class='ctx'> 				compatible = "arm,pl011", "arm,primecell";</div><div class='ctx'> 				reg = &lt;0x0b0000 0x1000&gt;;</div><div class='ctx'> 				interrupts = &lt;7&gt;;</div><div class='hunk'>@@ -213,7 +220,7 @@</div><div class='ctx'> 				clock-names = "uartclk", "apb_pclk";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			v2m_serial3: uart@c0000 {</div><div class='add'>+			v2m_serial3: serial@c0000 {</div><div class='ctx'> 				compatible = "arm,pl011", "arm,primecell";</div><div class='ctx'> 				reg = &lt;0x0c0000 0x1000&gt;;</div><div class='ctx'> 				interrupts = &lt;8&gt;;</div><div class='hunk'>@@ -221,7 +228,7 @@</div><div class='ctx'> 				clock-names = "uartclk", "apb_pclk";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			virtio-block@130000 {</div><div class='add'>+			virtio@130000 {</div><div class='ctx'> 				compatible = "virtio,mmio";</div><div class='ctx'> 				reg = &lt;0x130000 0x200&gt;;</div><div class='ctx'> 				interrupts = &lt;42&gt;;</div><div class='head'>diff --git a/arch/arm64/boot/dts/arm/fvp-base-revc.dts b/arch/arm64/boot/dts/arm/fvp-base-revc.dts<br/>index 66381d89c1ce..68a69f17e93d 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/arm/fvp-base-revc.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/arm/fvp-base-revc.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/arm/fvp-base-revc.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/arm/fvp-base-revc.dts</a></div><div class='hunk'>@@ -24,7 +24,9 @@</div><div class='ctx'> 	#address-cells = &lt;2&gt;;</div><div class='ctx'> 	#size-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='del'>-	chosen { };</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='ctx'> </div><div class='ctx'> 	aliases {</div><div class='ctx'> 		serial0 = &amp;v2m_serial0;</div><div class='hunk'>@@ -42,59 +44,164 @@</div><div class='ctx'> 		#address-cells = &lt;2&gt;;</div><div class='ctx'> 		#size-cells = &lt;0&gt;;</div><div class='ctx'> </div><div class='add'>+		idle-states {</div><div class='add'>+			entry-method = "psci";</div><div class='add'>+</div><div class='add'>+			CPU_SLEEP_0: cpu-sleep-0 {</div><div class='add'>+				compatible = "arm,idle-state";</div><div class='add'>+				local-timer-stop;</div><div class='add'>+				arm,psci-suspend-param = &lt;0x0010000&gt;;</div><div class='add'>+				entry-latency-us = &lt;40&gt;;</div><div class='add'>+				exit-latency-us = &lt;100&gt;;</div><div class='add'>+				min-residency-us = &lt;150&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			CLUSTER_SLEEP_0: cluster-sleep-0 {</div><div class='add'>+				compatible = "arm,idle-state";</div><div class='add'>+				local-timer-stop;</div><div class='add'>+				arm,psci-suspend-param = &lt;0x1010000&gt;;</div><div class='add'>+				entry-latency-us = &lt;500&gt;;</div><div class='add'>+				exit-latency-us = &lt;1000&gt;;</div><div class='add'>+				min-residency-us = &lt;2500&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		cpu0: cpu@0 {</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			compatible = "arm,armv8";</div><div class='ctx'> 			reg = &lt;0x0 0x000&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;C0_L2&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;CPU_SLEEP_0 &amp;CLUSTER_SLEEP_0&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 		cpu1: cpu@100 {</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			compatible = "arm,armv8";</div><div class='ctx'> 			reg = &lt;0x0 0x100&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;C0_L2&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;CPU_SLEEP_0 &amp;CLUSTER_SLEEP_0&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 		cpu2: cpu@200 {</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			compatible = "arm,armv8";</div><div class='ctx'> 			reg = &lt;0x0 0x200&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;C0_L2&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;CPU_SLEEP_0 &amp;CLUSTER_SLEEP_0&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 		cpu3: cpu@300 {</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			compatible = "arm,armv8";</div><div class='ctx'> 			reg = &lt;0x0 0x300&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;C0_L2&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;CPU_SLEEP_0 &amp;CLUSTER_SLEEP_0&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 		cpu4: cpu@10000 {</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			compatible = "arm,armv8";</div><div class='ctx'> 			reg = &lt;0x0 0x10000&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;C1_L2&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;CPU_SLEEP_0 &amp;CLUSTER_SLEEP_0&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 		cpu5: cpu@10100 {</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			compatible = "arm,armv8";</div><div class='ctx'> 			reg = &lt;0x0 0x10100&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;C1_L2&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;CPU_SLEEP_0 &amp;CLUSTER_SLEEP_0&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 		cpu6: cpu@10200 {</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			compatible = "arm,armv8";</div><div class='ctx'> 			reg = &lt;0x0 0x10200&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;C1_L2&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;CPU_SLEEP_0 &amp;CLUSTER_SLEEP_0&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 		cpu7: cpu@10300 {</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			compatible = "arm,armv8";</div><div class='ctx'> 			reg = &lt;0x0 0x10300&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;C1_L2&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;CPU_SLEEP_0 &amp;CLUSTER_SLEEP_0&gt;;</div><div class='add'>+		};</div><div class='add'>+		C0_L2: l2-cache0 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-size = &lt;0x80000&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;512&gt;;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		C1_L2: l2-cache1 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-size = &lt;0x80000&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;512&gt;;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	memory@80000000 {</div><div class='ctx'> 		device_type = "memory";</div><div class='del'>-		reg = &lt;0x00000000 0x80000000 0 0x80000000&gt;,</div><div class='add'>+		reg = &lt;0x00000000 0x80000000 0 0x7c000000&gt;,</div><div class='ctx'> 		      &lt;0x00000008 0x80000000 0 0x80000000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -126,7 +233,7 @@</div><div class='ctx'> 		      &lt;0x0 0x2c02f000 0 0x2000&gt;;	// GICV</div><div class='ctx'> 		interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> </div><div class='del'>-		its: its@2f020000 {</div><div class='add'>+		its: msi-controller@2f020000 {</div><div class='ctx'> 			#msi-cells = &lt;1&gt;;</div><div class='ctx'> 			compatible = "arm,gic-v3-its";</div><div class='ctx'> 			reg = &lt;0x0 0x2f020000 0x0 0x20000&gt;; // GITS</div><div class='hunk'>@@ -142,6 +249,19 @@</div><div class='ctx'> 			     &lt;GIC_PPI 10 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	timer@2a810000 {</div><div class='add'>+		compatible = "arm,armv7-timer-mem";</div><div class='add'>+		reg = &lt;0x0 0x2a810000 0x0 0x10000&gt;;</div><div class='add'>+		ranges = &lt;0 0x0 0x2a820000 0x20000&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		frame@2a830000 {</div><div class='add'>+			frame-number = &lt;1&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			reg = &lt;0x10000 0x10000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	pmu {</div><div class='ctx'> 		compatible = "arm,armv8-pmuv3";</div><div class='ctx'> 		interrupts = &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='hunk'>@@ -152,13 +272,67 @@</div><div class='ctx'> 		interrupts = &lt;GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	ete-0 {</div><div class='add'>+		compatible = "arm,embedded-trace-extension";</div><div class='add'>+		cpu = &lt;&amp;cpu0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ete-1 {</div><div class='add'>+		compatible = "arm,embedded-trace-extension";</div><div class='add'>+		cpu = &lt;&amp;cpu1&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ete-2 {</div><div class='add'>+		compatible = "arm,embedded-trace-extension";</div><div class='add'>+		cpu = &lt;&amp;cpu2&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ete-3 {</div><div class='add'>+		compatible = "arm,embedded-trace-extension";</div><div class='add'>+		cpu = &lt;&amp;cpu3&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ete-4 {</div><div class='add'>+		compatible = "arm,embedded-trace-extension";</div><div class='add'>+		cpu = &lt;&amp;cpu4&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ete-5 {</div><div class='add'>+		compatible = "arm,embedded-trace-extension";</div><div class='add'>+		cpu = &lt;&amp;cpu5&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ete-6 {</div><div class='add'>+		compatible = "arm,embedded-trace-extension";</div><div class='add'>+		cpu = &lt;&amp;cpu6&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ete-7 {</div><div class='add'>+		compatible = "arm,embedded-trace-extension";</div><div class='add'>+		cpu = &lt;&amp;cpu7&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	trbe {</div><div class='add'>+		compatible = "arm,trace-buffer-extension";</div><div class='add'>+		interrupts = &lt;GIC_PPI 15 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	pci: pci@40000000 {</div><div class='ctx'> 		#address-cells = &lt;0x3&gt;;</div><div class='ctx'> 		#size-cells = &lt;0x2&gt;;</div><div class='ctx'> 		#interrupt-cells = &lt;0x1&gt;;</div><div class='ctx'> 		compatible = "pci-host-ecam-generic";</div><div class='ctx'> 		device_type = "pci";</div><div class='del'>-		bus-range = &lt;0x0 0x1&gt;;</div><div class='add'>+		bus-range = &lt;0x0 0xff&gt;;</div><div class='ctx'> 		reg = &lt;0x0 0x40000000 0x0 0x10000000&gt;;</div><div class='ctx'> 		ranges = &lt;0x2000000 0x0 0x50000000 0x0 0x50000000 0x0 0x10000000&gt;;</div><div class='ctx'> 		interrupt-map = &lt;0 0 0 1 &amp;gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='hunk'>@@ -170,54 +344,32 @@</div><div class='ctx'> 		iommu-map = &lt;0x0 &amp;smmu 0x0 0x10000&gt;;</div><div class='ctx'> </div><div class='ctx'> 		dma-coherent;</div><div class='add'>+		ats-supported;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	smmu: smmu@2b400000 {</div><div class='add'>+	smmu: iommu@2b400000 {</div><div class='ctx'> 		compatible = "arm,smmu-v3";</div><div class='ctx'> 		reg = &lt;0x0 0x2b400000 0x0 0x100000&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 74 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+			     &lt;GIC_SPI 79 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='ctx'> 			     &lt;GIC_SPI 75 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='del'>-			     &lt;GIC_SPI 77 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='del'>-			     &lt;GIC_SPI 79 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='del'>-		interrupt-names = "eventq", "priq", "cmdq-sync", "gerror";</div><div class='add'>+			     &lt;GIC_SPI 77 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+		interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";</div><div class='ctx'> 		dma-coherent;</div><div class='ctx'> 		#iommu-cells = &lt;1&gt;;</div><div class='ctx'> 		msi-parent = &lt;&amp;its 0x10000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	panel {</div><div class='del'>-		compatible = "arm,rtsm-display", "panel-dpi";</div><div class='add'>+		compatible = "arm,rtsm-display";</div><div class='ctx'> 		port {</div><div class='ctx'> 			panel_in: endpoint {</div><div class='ctx'> 				remote-endpoint = &lt;&amp;clcd_pads&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='del'>-</div><div class='del'>-	       panel-timing {</div><div class='del'>-		       clock-frequency = &lt;63500127&gt;;</div><div class='del'>-		       hactive = &lt;1024&gt;;</div><div class='del'>-		       hback-porch = &lt;152&gt;;</div><div class='del'>-		       hfront-porch = &lt;48&gt;;</div><div class='del'>-		       hsync-len = &lt;104&gt;;</div><div class='del'>-		       vactive = &lt;768&gt;;</div><div class='del'>-		       vback-porch = &lt;23&gt;;</div><div class='del'>-		       vfront-porch = &lt;3&gt;;</div><div class='del'>-		       vsync-len = &lt;4&gt;;</div><div class='del'>-	       };</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	bus@8000000 {</div><div class='del'>-		compatible = "simple-bus";</div><div class='del'>-</div><div class='del'>-		#address-cells = &lt;2&gt;;</div><div class='del'>-		#size-cells = &lt;1&gt;;</div><div class='del'>-		ranges = &lt;0 0 0 0x08000000 0x04000000&gt;,</div><div class='del'>-			 &lt;1 0 0 0x14000000 0x04000000&gt;,</div><div class='del'>-			 &lt;2 0 0 0x18000000 0x04000000&gt;,</div><div class='del'>-			 &lt;3 0 0 0x1c000000 0x04000000&gt;,</div><div class='del'>-			 &lt;4 0 0 0x0c000000 0x04000000&gt;,</div><div class='del'>-			 &lt;5 0 0 0x10000000 0x04000000&gt;;</div><div class='del'>-</div><div class='ctx'> 		#interrupt-cells = &lt;1&gt;;</div><div class='ctx'> 		interrupt-map-mask = &lt;0 0 63&gt;;</div><div class='ctx'> 		interrupt-map = &lt;0 0  0 &amp;gic 0 0 GIC_SPI  0 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='hunk'>@@ -264,6 +416,7 @@</div><div class='ctx'> 				&lt;0 0 41 &amp;gic 0 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 				&lt;0 0 42 &amp;gic 0 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 				&lt;0 0 43 &amp;gic 0 0 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 44 &amp;gic 0 0 GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				&lt;0 0 44 &amp;gic 0 0 GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 46 &amp;gic 0 0 GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi<br/>index f5889281545f..9ccb80821bdb 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/arm/juno-base.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/arm/juno-base.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/arm/juno-base.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/arm/juno-base.dtsi</a></div><div class='hunk'>@@ -10,15 +10,14 @@</div><div class='ctx'> 	memtimer: timer@2a810000 {</div><div class='ctx'> 		compatible = "arm,armv7-timer-mem";</div><div class='ctx'> 		reg = &lt;0x0 0x2a810000 0x0 0x10000&gt;;</div><div class='del'>-		clock-frequency = &lt;50000000&gt;;</div><div class='del'>-		#address-cells = &lt;2&gt;;</div><div class='del'>-		#size-cells = &lt;2&gt;;</div><div class='del'>-		ranges;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges = &lt;0 0x0 0x2a820000 0x20000&gt;;</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 		frame@2a830000 {</div><div class='ctx'> 			frame-number = &lt;1&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			reg = &lt;0x0 0x2a830000 0x0 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x10000 0x10000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -26,9 +25,8 @@</div><div class='ctx'> 		compatible = "arm,mhu", "arm,primecell";</div><div class='ctx'> 		reg = &lt;0x0 0x2b1f0000 0x0 0x1000&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-			     &lt;GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-		interrupt-names = "mhu_lpri_rx",</div><div class='del'>-				  "mhu_hpri_rx";</div><div class='add'>+			     &lt;GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		#mbox-cells = &lt;1&gt;;</div><div class='ctx'> 		clocks = &lt;&amp;soc_refclk100mhz&gt;;</div><div class='ctx'> 		clock-names = "apb_pclk";</div><div class='hunk'>@@ -74,35 +72,35 @@</div><div class='ctx'> 		      &lt;0x0 0x2c02f000 0 0x2000&gt;,</div><div class='ctx'> 		      &lt;0x0 0x2c04f000 0 0x2000&gt;,</div><div class='ctx'> 		      &lt;0x0 0x2c06f000 0 0x2000&gt;;</div><div class='del'>-		#address-cells = &lt;2&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#interrupt-cells = &lt;3&gt;;</div><div class='del'>-		#size-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='ctx'> 		interrupt-controller;</div><div class='ctx'> 		interrupts = &lt;GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='del'>-		ranges = &lt;0 0 0 0x2c1c0000 0 0x40000&gt;;</div><div class='add'>+		ranges = &lt;0 0 0x2c1c0000 0x40000&gt;;</div><div class='ctx'> </div><div class='ctx'> 		v2m_0: v2m@0 {</div><div class='ctx'> 			compatible = "arm,gic-v2m-frame";</div><div class='ctx'> 			msi-controller;</div><div class='del'>-			reg = &lt;0 0 0 0x10000&gt;;</div><div class='add'>+			reg = &lt;0 0x10000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		v2m@10000 {</div><div class='ctx'> 			compatible = "arm,gic-v2m-frame";</div><div class='ctx'> 			msi-controller;</div><div class='del'>-			reg = &lt;0 0x10000 0 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x10000 0x10000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		v2m@20000 {</div><div class='ctx'> 			compatible = "arm,gic-v2m-frame";</div><div class='ctx'> 			msi-controller;</div><div class='del'>-			reg = &lt;0 0x20000 0 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x20000 0x10000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		v2m@30000 {</div><div class='ctx'> 			compatible = "arm,gic-v2m-frame";</div><div class='ctx'> 			msi-controller;</div><div class='del'>-			reg = &lt;0 0x30000 0 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x30000 0x10000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -119,7 +117,7 @@</div><div class='ctx'> 	 * The actual size is just 4K though 64K is reserved. Access to the</div><div class='ctx'> 	 * unmapped reserved region results in a DECERR response.</div><div class='ctx'> 	 */</div><div class='del'>-	etf@20010000 { /* etf0 */</div><div class='add'>+	etf_sys0: etf@20010000 { /* etf0 */</div><div class='ctx'> 		compatible = "arm,coresight-tmc", "arm,primecell";</div><div class='ctx'> 		reg = &lt;0 0x20010000 0 0x1000&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -143,7 +141,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	tpiu@20030000 {</div><div class='add'>+	tpiu_sys: tpiu@20030000 {</div><div class='ctx'> 		compatible = "arm,coresight-tpiu", "arm,primecell";</div><div class='ctx'> 		reg = &lt;0 0x20030000 0 0x1000&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -196,7 +194,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	etr@20070000 {</div><div class='add'>+	etr_sys: etr@20070000 {</div><div class='ctx'> 		compatible = "arm,coresight-tmc", "arm,primecell";</div><div class='ctx'> 		reg = &lt;0 0x20070000 0 0x1000&gt;;</div><div class='ctx'> 		iommus = &lt;&amp;smmu_etr 0&gt;;</div><div class='hunk'>@@ -214,7 +212,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	stm@20100000 {</div><div class='add'>+	stm_sys: stm@20100000 {</div><div class='ctx'> 		compatible = "arm,coresight-stm", "arm,primecell";</div><div class='ctx'> 		reg = &lt;0 0x20100000 0 0x1000&gt;,</div><div class='ctx'> 		      &lt;0 0x28000000 0 0x1000000&gt;;</div><div class='hunk'>@@ -291,6 +289,18 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	cti0: cti@22020000 {</div><div class='add'>+		compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",</div><div class='add'>+			     "arm,primecell";</div><div class='add'>+		reg = &lt;0 0x22020000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;soc_smc50mhz&gt;;</div><div class='add'>+		clock-names = "apb_pclk";</div><div class='add'>+		power-domains = &lt;&amp;scpi_devpd 0&gt;;</div><div class='add'>+</div><div class='add'>+		arm,cs-dev-assoc = &lt;&amp;etm0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	funnel@220c0000 { /* cluster0 funnel */</div><div class='ctx'> 		compatible = "arm,coresight-dynamic-funnel", "arm,primecell";</div><div class='ctx'> 		reg = &lt;0 0x220c0000 0 0x1000&gt;;</div><div class='hunk'>@@ -351,6 +361,18 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	cti1: cti@22120000 {</div><div class='add'>+		compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",</div><div class='add'>+			     "arm,primecell";</div><div class='add'>+		reg = &lt;0 0x22120000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;soc_smc50mhz&gt;;</div><div class='add'>+		clock-names = "apb_pclk";</div><div class='add'>+		power-domains = &lt;&amp;scpi_devpd 0&gt;;</div><div class='add'>+</div><div class='add'>+		arm,cs-dev-assoc = &lt;&amp;etm1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	cpu_debug2: cpu-debug@23010000 {</div><div class='ctx'> 		compatible = "arm,coresight-cpu-debug", "arm,primecell";</div><div class='ctx'> 		reg = &lt;0x0 0x23010000 0x0 0x1000&gt;;</div><div class='hunk'>@@ -376,6 +398,18 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	cti2: cti@23020000 {</div><div class='add'>+		compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",</div><div class='add'>+			     "arm,primecell";</div><div class='add'>+		reg = &lt;0 0x23020000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;soc_smc50mhz&gt;;</div><div class='add'>+		clock-names = "apb_pclk";</div><div class='add'>+		power-domains = &lt;&amp;scpi_devpd 0&gt;;</div><div class='add'>+</div><div class='add'>+		arm,cs-dev-assoc = &lt;&amp;etm2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	funnel@230c0000 { /* cluster1 funnel */</div><div class='ctx'> 		compatible = "arm,coresight-dynamic-funnel", "arm,primecell";</div><div class='ctx'> 		reg = &lt;0 0x230c0000 0 0x1000&gt;;</div><div class='hunk'>@@ -448,6 +482,18 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	cti3: cti@23120000 {</div><div class='add'>+		compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",</div><div class='add'>+			     "arm,primecell";</div><div class='add'>+		reg = &lt;0 0x23120000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;soc_smc50mhz&gt;;</div><div class='add'>+		clock-names = "apb_pclk";</div><div class='add'>+		power-domains = &lt;&amp;scpi_devpd 0&gt;;</div><div class='add'>+</div><div class='add'>+		arm,cs-dev-assoc = &lt;&amp;etm3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	cpu_debug4: cpu-debug@23210000 {</div><div class='ctx'> 		compatible = "arm,coresight-cpu-debug", "arm,primecell";</div><div class='ctx'> 		reg = &lt;0x0 0x23210000 0x0 0x1000&gt;;</div><div class='hunk'>@@ -473,6 +519,18 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	cti4: cti@23220000 {</div><div class='add'>+		compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",</div><div class='add'>+			     "arm,primecell";</div><div class='add'>+		reg = &lt;0 0x23220000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;soc_smc50mhz&gt;;</div><div class='add'>+		clock-names = "apb_pclk";</div><div class='add'>+		power-domains = &lt;&amp;scpi_devpd 0&gt;;</div><div class='add'>+</div><div class='add'>+		arm,cs-dev-assoc = &lt;&amp;etm4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	cpu_debug5: cpu-debug@23310000 {</div><div class='ctx'> 		compatible = "arm,coresight-cpu-debug", "arm,primecell";</div><div class='ctx'> 		reg = &lt;0x0 0x23310000 0x0 0x1000&gt;;</div><div class='hunk'>@@ -498,19 +556,112 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	cti5: cti@23320000 {</div><div class='add'>+		compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",</div><div class='add'>+			     "arm,primecell";</div><div class='add'>+		reg = &lt;0 0x23320000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;soc_smc50mhz&gt;;</div><div class='add'>+		clock-names = "apb_pclk";</div><div class='add'>+		power-domains = &lt;&amp;scpi_devpd 0&gt;;</div><div class='add'>+</div><div class='add'>+		arm,cs-dev-assoc = &lt;&amp;etm5&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cti_sys0: cti@20020000 { /* sys_cti_0 */</div><div class='add'>+		compatible = "arm,coresight-cti", "arm,primecell";</div><div class='add'>+		reg = &lt;0 0x20020000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;soc_smc50mhz&gt;;</div><div class='add'>+		clock-names = "apb_pclk";</div><div class='add'>+		power-domains = &lt;&amp;scpi_devpd 0&gt;;</div><div class='add'>+</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		trig-conns@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			arm,trig-in-sigs = &lt;2 3&gt;;</div><div class='add'>+			arm,trig-in-types = &lt;SNK_FULL SNK_ACQCOMP&gt;;</div><div class='add'>+			arm,trig-out-sigs = &lt;0 1&gt;;</div><div class='add'>+			arm,trig-out-types = &lt;SNK_FLUSHIN SNK_TRIGIN&gt;;</div><div class='add'>+			arm,cs-dev-assoc = &lt;&amp;etr_sys&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		trig-conns@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			arm,trig-in-sigs = &lt;0 1&gt;;</div><div class='add'>+			arm,trig-in-types = &lt;SNK_FULL SNK_ACQCOMP&gt;;</div><div class='add'>+			arm,trig-out-sigs = &lt;7 6&gt;;</div><div class='add'>+			arm,trig-out-types = &lt;SNK_FLUSHIN SNK_TRIGIN&gt;;</div><div class='add'>+			arm,cs-dev-assoc = &lt;&amp;etf_sys0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		trig-conns@2 {</div><div class='add'>+			reg = &lt;2&gt;;</div><div class='add'>+			arm,trig-in-sigs = &lt;4 5 6 7&gt;;</div><div class='add'>+			arm,trig-in-types = &lt;STM_TOUT_SPTE STM_TOUT_SW</div><div class='add'>+					   STM_TOUT_HETE STM_ASYNCOUT&gt;;</div><div class='add'>+			arm,trig-out-sigs = &lt;4 5&gt;;</div><div class='add'>+			arm,trig-out-types = &lt;STM_HWEVENT STM_HWEVENT&gt;;</div><div class='add'>+			arm,cs-dev-assoc = &lt;&amp;stm_sys&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		trig-conns@3 {</div><div class='add'>+			reg = &lt;3&gt;;</div><div class='add'>+			arm,trig-out-sigs = &lt;2 3&gt;;</div><div class='add'>+			arm,trig-out-types = &lt;SNK_FLUSHIN SNK_TRIGIN&gt;;</div><div class='add'>+			arm,cs-dev-assoc = &lt;&amp;tpiu_sys&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cti_sys1: cti@20110000 { /* sys_cti_1 */</div><div class='add'>+		compatible = "arm,coresight-cti", "arm,primecell";</div><div class='add'>+		reg = &lt;0 0x20110000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;soc_smc50mhz&gt;;</div><div class='add'>+		clock-names = "apb_pclk";</div><div class='add'>+		power-domains = &lt;&amp;scpi_devpd 0&gt;;</div><div class='add'>+</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		trig-conns@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			arm,trig-in-sigs = &lt;0&gt;;</div><div class='add'>+			arm,trig-in-types = &lt;GEN_INTREQ&gt;;</div><div class='add'>+			arm,trig-out-sigs = &lt;0&gt;;</div><div class='add'>+			arm,trig-out-types = &lt;GEN_HALTREQ&gt;;</div><div class='add'>+			arm,trig-conn-name = "sys_profiler";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		trig-conns@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			arm,trig-out-sigs = &lt;2 3&gt;;</div><div class='add'>+			arm,trig-out-types = &lt;GEN_HALTREQ GEN_RESTARTREQ&gt;;</div><div class='add'>+			arm,trig-conn-name = "watchdog";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		trig-conns@2 {</div><div class='add'>+			reg = &lt;2&gt;;</div><div class='add'>+			arm,trig-out-sigs = &lt;1 6&gt;;</div><div class='add'>+			arm,trig-out-types = &lt;GEN_HALTREQ GEN_RESTARTREQ&gt;;</div><div class='add'>+			arm,trig-conn-name = "g_counter";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	gpu: gpu@2d000000 {</div><div class='ctx'> 		compatible = "arm,juno-mali", "arm,mali-t624";</div><div class='ctx'> 		reg = &lt;0 0x2d000000 0 0x10000&gt;;</div><div class='del'>-		interrupts = &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-			     &lt;GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-			     &lt;GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-		interrupt-names = "gpu", "job", "mmu";</div><div class='add'>+		interrupts = &lt;GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-names = "job", "mmu", "gpu";</div><div class='ctx'> 		clocks = &lt;&amp;scpi_dvfs 2&gt;;</div><div class='ctx'> 		power-domains = &lt;&amp;scpi_devpd 1&gt;;</div><div class='ctx'> 		dma-coherent;</div><div class='ctx'> 		/* The SMMU is only really of interest to bare-metal hypervisors */</div><div class='ctx'> 		/* iommus = &lt;&amp;smmu_gpu 0&gt;; */</div><div class='del'>-		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	sram: sram@2e000000 {</div><div class='hunk'>@@ -521,12 +672,12 @@</div><div class='ctx'> 		#size-cells = &lt;1&gt;;</div><div class='ctx'> 		ranges = &lt;0 0x0 0x2e000000 0x8000&gt;;</div><div class='ctx'> </div><div class='del'>-		cpu_scp_lpri: scp-shmem@0 {</div><div class='add'>+		cpu_scp_lpri: scp-sram@0 {</div><div class='ctx'> 			compatible = "arm,juno-scp-shmem";</div><div class='ctx'> 			reg = &lt;0x0 0x200&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		cpu_scp_hpri: scp-shmem@200 {</div><div class='add'>+		cpu_scp_hpri: scp-sram@200 {</div><div class='ctx'> 			compatible = "arm,juno-scp-shmem";</div><div class='ctx'> 			reg = &lt;0x200 0x200&gt;;</div><div class='ctx'> 		};</div><div class='hunk'>@@ -544,12 +695,15 @@</div><div class='ctx'> 		ranges = &lt;0x01000000 0x00 0x00000000 0x00 0x5f800000 0x0 0x00800000&gt;,</div><div class='ctx'> 			 &lt;0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000&gt;,</div><div class='ctx'> 			 &lt;0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000&gt;;</div><div class='add'>+		/* Standard AXI Translation entries as programmed by EDK2 */</div><div class='add'>+		dma-ranges = &lt;0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x80000000&gt;,</div><div class='add'>+			     &lt;0x43000000 0x8 0x00000000 0x8 0x00000000 0x2 0x00000000&gt;;</div><div class='ctx'> 		#interrupt-cells = &lt;1&gt;;</div><div class='ctx'> 		interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='del'>-		interrupt-map = &lt;0 0 0 1 &amp;gic 0 0 GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 0 2 &amp;gic 0 0 GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 0 3 &amp;gic 0 0 GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 0 4 &amp;gic 0 0 GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-map = &lt;0 0 0 1 &amp;gic 0 GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 0 2 &amp;gic 0 GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 0 3 &amp;gic 0 GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 0 4 &amp;gic 0 GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		msi-parent = &lt;&amp;v2m_0&gt;;</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 		iommu-map-mask = &lt;0x0&gt;;	/* RC has no means to output PCI RID */</div><div class='hunk'>@@ -564,13 +718,13 @@</div><div class='ctx'> 		clocks {</div><div class='ctx'> 			compatible = "arm,scpi-clocks";</div><div class='ctx'> </div><div class='del'>-			scpi_dvfs: scpi-dvfs {</div><div class='add'>+			scpi_dvfs: clocks-0 {</div><div class='ctx'> 				compatible = "arm,scpi-dvfs-clocks";</div><div class='ctx'> 				#clock-cells = &lt;1&gt;;</div><div class='ctx'> 				clock-indices = &lt;0&gt;, &lt;1&gt;, &lt;2&gt;;</div><div class='ctx'> 				clock-output-names = "atlclk", "aplclk","gpuclk";</div><div class='ctx'> 			};</div><div class='del'>-			scpi_clk: scpi-clk {</div><div class='add'>+			scpi_clk: clocks-1 {</div><div class='ctx'> 				compatible = "arm,scpi-variable-clocks";</div><div class='ctx'> 				#clock-cells = &lt;1&gt;;</div><div class='ctx'> 				clock-indices = &lt;3&gt;;</div><div class='hunk'>@@ -578,7 +732,7 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		scpi_devpd: scpi-power-domains {</div><div class='add'>+		scpi_devpd: power-controller {</div><div class='ctx'> 			compatible = "arm,scpi-power-domains";</div><div class='ctx'> 			num-domains = &lt;2&gt;;</div><div class='ctx'> 			#power-domain-cells = &lt;1&gt;;</div><div class='hunk'>@@ -591,40 +745,54 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	thermal-zones {</div><div class='del'>-		pmic {</div><div class='add'>+		pmic-thermal {</div><div class='ctx'> 			polling-delay = &lt;1000&gt;;</div><div class='ctx'> 			polling-delay-passive = &lt;100&gt;;</div><div class='ctx'> 			thermal-sensors = &lt;&amp;scpi_sensors0 0&gt;;</div><div class='add'>+			trips {</div><div class='add'>+				pmic_crit0: trip0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		soc {</div><div class='add'>+		soc-thermal {</div><div class='ctx'> 			polling-delay = &lt;1000&gt;;</div><div class='ctx'> 			polling-delay-passive = &lt;100&gt;;</div><div class='ctx'> 			thermal-sensors = &lt;&amp;scpi_sensors0 3&gt;;</div><div class='add'>+			trips {</div><div class='add'>+				soc_crit0: trip0 {</div><div class='add'>+					temperature = &lt;80000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		big_cluster_thermal_zone: big-cluster {</div><div class='add'>+		big_cluster_thermal_zone: big-cl-thermal {</div><div class='ctx'> 			polling-delay = &lt;1000&gt;;</div><div class='ctx'> 			polling-delay-passive = &lt;100&gt;;</div><div class='ctx'> 			thermal-sensors = &lt;&amp;scpi_sensors0 21&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		little_cluster_thermal_zone: little-cluster {</div><div class='add'>+		little_cluster_thermal_zone: little-cl-thermal {</div><div class='ctx'> 			polling-delay = &lt;1000&gt;;</div><div class='ctx'> 			polling-delay-passive = &lt;100&gt;;</div><div class='ctx'> 			thermal-sensors = &lt;&amp;scpi_sensors0 22&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		gpu0_thermal_zone: gpu0 {</div><div class='add'>+		gpu0_thermal_zone: gpu0-thermal {</div><div class='ctx'> 			polling-delay = &lt;1000&gt;;</div><div class='ctx'> 			polling-delay-passive = &lt;100&gt;;</div><div class='ctx'> 			thermal-sensors = &lt;&amp;scpi_sensors0 23&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		gpu1_thermal_zone: gpu1 {</div><div class='add'>+		gpu1_thermal_zone: gpu1-thermal {</div><div class='ctx'> 			polling-delay = &lt;1000&gt;;</div><div class='ctx'> 			polling-delay-passive = &lt;100&gt;;</div><div class='ctx'> 			thermal-sensors = &lt;&amp;scpi_sensors0 24&gt;;</div><div class='hunk'>@@ -640,7 +808,6 @@</div><div class='ctx'> 		#iommu-cells = &lt;1&gt;;</div><div class='ctx'> 		#global-interrupts = &lt;1&gt;;</div><div class='ctx'> 		dma-coherent;</div><div class='del'>-		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	smmu_hdlcd1: iommu@7fb10000 {</div><div class='hunk'>@@ -671,12 +838,10 @@</div><div class='ctx'> 		dma-coherent;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	dma@7ff00000 {</div><div class='add'>+	dma-controller@7ff00000 {</div><div class='ctx'> 		compatible = "arm,pl330", "arm,primecell";</div><div class='ctx'> 		reg = &lt;0x0 0x7ff00000 0 0x1000&gt;;</div><div class='ctx'> 		#dma-cells = &lt;1&gt;;</div><div class='del'>-		#dma-channels = &lt;8&gt;;</div><div class='del'>-		#dma-requests = &lt;32&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 			     &lt;GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 			     &lt;GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='hunk'>@@ -729,7 +894,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	soc_uart0: uart@7ff80000 {</div><div class='add'>+	soc_uart0: serial@7ff80000 {</div><div class='ctx'> 		compatible = "arm,pl011", "arm,primecell";</div><div class='ctx'> 		reg = &lt;0x0 0x7ff80000 0x0 0x1000&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='hunk'>@@ -768,7 +933,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	ohci@7ffb0000 {</div><div class='add'>+	usb@7ffb0000 {</div><div class='ctx'> 		compatible = "generic-ohci";</div><div class='ctx'> 		reg = &lt;0x0 0x7ffb0000 0x0 0x10000&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='hunk'>@@ -776,7 +941,7 @@</div><div class='ctx'> 		clocks = &lt;&amp;soc_usb48mhz&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	ehci@7ffc0000 {</div><div class='add'>+	usb@7ffc0000 {</div><div class='ctx'> 		compatible = "generic-ehci";</div><div class='ctx'> 		reg = &lt;0x0 0x7ffc0000 0x0 0x10000&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='hunk'>@@ -801,40 +966,30 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	bus@8000000 {</div><div class='del'>-		compatible = "simple-bus";</div><div class='del'>-		#address-cells = &lt;2&gt;;</div><div class='del'>-		#size-cells = &lt;1&gt;;</div><div class='del'>-		ranges = &lt;0 0 0 0x08000000 0x04000000&gt;,</div><div class='del'>-			 &lt;1 0 0 0x14000000 0x04000000&gt;,</div><div class='del'>-			 &lt;2 0 0 0x18000000 0x04000000&gt;,</div><div class='del'>-			 &lt;3 0 0 0x1c000000 0x04000000&gt;,</div><div class='del'>-			 &lt;4 0 0 0x0c000000 0x04000000&gt;,</div><div class='del'>-			 &lt;5 0 0 0x10000000 0x04000000&gt;;</div><div class='del'>-</div><div class='ctx'> 		#interrupt-cells = &lt;1&gt;;</div><div class='ctx'> 		interrupt-map-mask = &lt;0 0 15&gt;;</div><div class='del'>-		interrupt-map = &lt;0 0  0 &amp;gic 0 0 GIC_SPI  68 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0  1 &amp;gic 0 0 GIC_SPI  69 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0  2 &amp;gic 0 0 GIC_SPI  70 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0  3 &amp;gic 0 0 GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0  4 &amp;gic 0 0 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0  5 &amp;gic 0 0 GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0  6 &amp;gic 0 0 GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0  7 &amp;gic 0 0 GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0  8 &amp;gic 0 0 GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0  9 &amp;gic 0 0 GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 10 &amp;gic 0 0 GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 11 &amp;gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 12 &amp;gic 0 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	site2: tlx@60000000 {</div><div class='add'>+		interrupt-map = &lt;0 0  0 &amp;gic 0 GIC_SPI  68 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0  1 &amp;gic 0 GIC_SPI  69 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0  2 &amp;gic 0 GIC_SPI  70 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0  3 &amp;gic 0 GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0  4 &amp;gic 0 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0  5 &amp;gic 0 GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0  6 &amp;gic 0 GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0  7 &amp;gic 0 GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0  8 &amp;gic 0 GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0  9 &amp;gic 0 GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 10 &amp;gic 0 GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 11 &amp;gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 12 &amp;gic 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	site2: tlx-bus@60000000 {</div><div class='ctx'> 		compatible = "simple-bus";</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;1&gt;;</div><div class='ctx'> 		ranges = &lt;0 0 0x60000000 0x10000000&gt;;</div><div class='ctx'> 		#interrupt-cells = &lt;1&gt;;</div><div class='ctx'> 		interrupt-map-mask = &lt;0 0&gt;;</div><div class='del'>-		interrupt-map = &lt;0 0 &amp;gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-map = &lt;0 0 &amp;gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/arm/juno-clocks.dtsi b/arch/arm64/boot/dts/arm/juno-clocks.dtsi<br/>index 2870b5eeb198..6d7d88e9591a 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/arm/juno-clocks.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/arm/juno-clocks.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/arm/juno-clocks.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/arm/juno-clocks.dtsi</a></div><div class='hunk'>@@ -8,35 +8,35 @@</div><div class='ctx'>  */</div><div class='ctx'> / {</div><div class='ctx'> 	/* SoC fixed clocks */</div><div class='del'>-	soc_uartclk: refclk7372800hz {</div><div class='add'>+	soc_uartclk: clock-7372800 {</div><div class='ctx'> 		compatible = "fixed-clock";</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='ctx'> 		clock-frequency = &lt;7372800&gt;;</div><div class='ctx'> 		clock-output-names = "juno:uartclk";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	soc_usb48mhz: clk48mhz {</div><div class='add'>+	soc_usb48mhz: clock-48000000 {</div><div class='ctx'> 		compatible = "fixed-clock";</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='ctx'> 		clock-frequency = &lt;48000000&gt;;</div><div class='ctx'> 		clock-output-names = "clk48mhz";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	soc_smc50mhz: clk50mhz {</div><div class='add'>+	soc_smc50mhz: clock-50000000 {</div><div class='ctx'> 		compatible = "fixed-clock";</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='ctx'> 		clock-frequency = &lt;50000000&gt;;</div><div class='ctx'> 		clock-output-names = "smc_clk";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	soc_refclk100mhz: refclk100mhz {</div><div class='add'>+	soc_refclk100mhz: clock-100000000 {</div><div class='ctx'> 		compatible = "fixed-clock";</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='ctx'> 		clock-frequency = &lt;100000000&gt;;</div><div class='ctx'> 		clock-output-names = "apb_pclk";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	soc_faxiclk: refclk400mhz {</div><div class='add'>+	soc_faxiclk: clock-400000000 {</div><div class='ctx'> 		compatible = "fixed-clock";</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='ctx'> 		clock-frequency = &lt;400000000&gt;;</div><div class='head'>diff --git a/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi b/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi<br/>index eda3d9e18af6..09d2b692e9e1 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi</a></div><div class='hunk'>@@ -23,7 +23,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	etf@20140000 { /* etf1 */</div><div class='add'>+	etf_sys1: etf@20140000 { /* etf1 */</div><div class='ctx'> 		compatible = "arm,coresight-tmc", "arm,primecell";</div><div class='ctx'> 		reg = &lt;0 0x20140000 0 0x1000&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -67,7 +67,6 @@</div><div class='ctx'> 			port@0 {</div><div class='ctx'> 				reg = &lt;0&gt;;</div><div class='ctx'> 				csys2_funnel_in_port0: endpoint {</div><div class='del'>-					slave-mode;</div><div class='ctx'> 					remote-endpoint = &lt;&amp;etf0_out_port&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> 			};</div><div class='hunk'>@@ -75,11 +74,45 @@</div><div class='ctx'> 			port@1 {</div><div class='ctx'> 				reg = &lt;1&gt;;</div><div class='ctx'> 				csys2_funnel_in_port1: endpoint {</div><div class='del'>-					slave-mode;</div><div class='ctx'> 					remote-endpoint = &lt;&amp;etf1_out_port&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	cti_sys2: cti@20160000 { /* sys_cti_2 */</div><div class='add'>+		compatible = "arm,coresight-cti", "arm,primecell";</div><div class='add'>+		reg = &lt;0 0x20160000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;soc_smc50mhz&gt;;</div><div class='add'>+		clock-names = "apb_pclk";</div><div class='add'>+		power-domains = &lt;&amp;scpi_devpd 0&gt;;</div><div class='add'>+</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		trig-conns@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			arm,trig-in-sigs = &lt;0 1&gt;;</div><div class='add'>+			arm,trig-in-types = &lt;SNK_FULL SNK_ACQCOMP&gt;;</div><div class='add'>+			arm,trig-out-sigs = &lt;0 1&gt;;</div><div class='add'>+			arm,trig-out-types = &lt;SNK_FLUSHIN SNK_TRIGIN&gt;;</div><div class='add'>+			arm,cs-dev-assoc = &lt;&amp;etf_sys1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		trig-conns@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			arm,trig-in-sigs = &lt;2 3 4&gt;;</div><div class='add'>+			arm,trig-in-types = &lt;ELA_DBGREQ ELA_TSTART ELA_TSTOP&gt;;</div><div class='add'>+			arm,trig-conn-name = "ela_clus_0";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		trig-conns@2 {</div><div class='add'>+			reg = &lt;2&gt;;</div><div class='add'>+			arm,trig-in-sigs = &lt;5 6 7&gt;;</div><div class='add'>+			arm,trig-in-types = &lt;ELA_DBGREQ ELA_TSTART ELA_TSTOP&gt;;</div><div class='add'>+			arm,trig-conn-name = "ela_clus_1";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/arm/juno-motherboard.dtsi b/arch/arm64/boot/dts/arm/juno-motherboard.dtsi<br/>index e3983ded3c3c..ffa4ba4f1fbc 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/arm/juno-motherboard.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/arm/juno-motherboard.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/arm/juno-motherboard.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/arm/juno-motherboard.dtsi</a></div><div class='hunk'>@@ -8,102 +8,109 @@</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='del'>-	bus@8000000 {</div><div class='del'>-		mb_clk24mhz: clk24mhz {</div><div class='del'>-			compatible = "fixed-clock";</div><div class='del'>-			#clock-cells = &lt;0&gt;;</div><div class='del'>-			clock-frequency = &lt;24000000&gt;;</div><div class='del'>-			clock-output-names = "juno_mb:clk24mhz";</div><div class='del'>-		};</div><div class='add'>+	mb_clk24mhz: clock-24000000 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+		clock-output-names = "juno_mb:clk24mhz";</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		mb_clk25mhz: clk25mhz {</div><div class='del'>-			compatible = "fixed-clock";</div><div class='del'>-			#clock-cells = &lt;0&gt;;</div><div class='del'>-			clock-frequency = &lt;25000000&gt;;</div><div class='del'>-			clock-output-names = "juno_mb:clk25mhz";</div><div class='del'>-		};</div><div class='add'>+	mb_clk25mhz: clock-25000000 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;25000000&gt;;</div><div class='add'>+		clock-output-names = "juno_mb:clk25mhz";</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		v2m_refclk1mhz: refclk1mhz {</div><div class='del'>-			compatible = "fixed-clock";</div><div class='del'>-			#clock-cells = &lt;0&gt;;</div><div class='del'>-			clock-frequency = &lt;1000000&gt;;</div><div class='del'>-			clock-output-names = "juno_mb:refclk1mhz";</div><div class='del'>-		};</div><div class='add'>+	v2m_refclk1mhz: clock-1000000 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;1000000&gt;;</div><div class='add'>+		clock-output-names = "juno_mb:refclk1mhz";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	v2m_refclk32khz: clock-32768 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;32768&gt;;</div><div class='add'>+		clock-output-names = "juno_mb:refclk32khz";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mb_fixed_3v3: regulator-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "MCC_SB_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='ctx'> </div><div class='del'>-		v2m_refclk32khz: refclk32khz {</div><div class='del'>-			compatible = "fixed-clock";</div><div class='del'>-			#clock-cells = &lt;0&gt;;</div><div class='del'>-			clock-frequency = &lt;32768&gt;;</div><div class='del'>-			clock-output-names = "juno_mb:refclk32khz";</div><div class='add'>+		power-button {</div><div class='add'>+			debounce-interval = &lt;50&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+			linux,code = &lt;116&gt;;</div><div class='add'>+			label = "POWER";</div><div class='add'>+			gpios = &lt;&amp;iofpga_gpio0 0 0x4&gt;;</div><div class='add'>+		};</div><div class='add'>+		home-button {</div><div class='add'>+			debounce-interval = &lt;50&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+			linux,code = &lt;102&gt;;</div><div class='add'>+			label = "HOME";</div><div class='add'>+			gpios = &lt;&amp;iofpga_gpio0 1 0x4&gt;;</div><div class='add'>+		};</div><div class='add'>+		rlock-button {</div><div class='add'>+			debounce-interval = &lt;50&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+			linux,code = &lt;152&gt;;</div><div class='add'>+			label = "RLOCK";</div><div class='add'>+			gpios = &lt;&amp;iofpga_gpio0 2 0x4&gt;;</div><div class='add'>+		};</div><div class='add'>+		vol-up-button {</div><div class='add'>+			debounce-interval = &lt;50&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+			linux,code = &lt;115&gt;;</div><div class='add'>+			label = "VOL+";</div><div class='add'>+			gpios = &lt;&amp;iofpga_gpio0 3 0x4&gt;;</div><div class='add'>+		};</div><div class='add'>+		vol-down-button {</div><div class='add'>+			debounce-interval = &lt;50&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+			linux,code = &lt;114&gt;;</div><div class='add'>+			label = "VOL-";</div><div class='add'>+			gpios = &lt;&amp;iofpga_gpio0 4 0x4&gt;;</div><div class='ctx'> 		};</div><div class='add'>+		nmi-button {</div><div class='add'>+			debounce-interval = &lt;50&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+			linux,code = &lt;99&gt;;</div><div class='add'>+			label = "NMI";</div><div class='add'>+			gpios = &lt;&amp;iofpga_gpio0 5 0x4&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bus@8000000 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges = &lt;0 0x8000000 0 0x8000000 0x18000000&gt;;</div><div class='ctx'> </div><div class='del'>-		motherboard {</div><div class='add'>+		motherboard-bus@8000000 {</div><div class='ctx'> 			compatible = "arm,vexpress,v2p-p1", "simple-bus";</div><div class='ctx'> 			#address-cells = &lt;2&gt;;  /* SMB chipselect number and offset */</div><div class='ctx'> 			#size-cells = &lt;1&gt;;</div><div class='del'>-			#interrupt-cells = &lt;1&gt;;</div><div class='del'>-			ranges;</div><div class='del'>-			model = "V2M-Juno";</div><div class='add'>+			ranges = &lt;0 0 0 0x08000000 0x04000000&gt;,</div><div class='add'>+				 &lt;1 0 0 0x14000000 0x04000000&gt;,</div><div class='add'>+				 &lt;2 0 0 0x18000000 0x04000000&gt;,</div><div class='add'>+				 &lt;3 0 0 0x1c000000 0x04000000&gt;,</div><div class='add'>+				 &lt;4 0 0 0x0c000000 0x04000000&gt;,</div><div class='add'>+				 &lt;5 0 0 0x10000000 0x04000000&gt;;</div><div class='ctx'> 			arm,hbi = &lt;0x252&gt;;</div><div class='ctx'> 			arm,vexpress,site = &lt;0&gt;;</div><div class='del'>-			arm,v2m-memory-map = "rs1";</div><div class='del'>-</div><div class='del'>-			mb_fixed_3v3: mcc-sb-3v3 {</div><div class='del'>-				compatible = "regulator-fixed";</div><div class='del'>-				regulator-name = "MCC_SB_3V3";</div><div class='del'>-				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='del'>-				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='del'>-				regulator-always-on;</div><div class='del'>-			};</div><div class='del'>-</div><div class='del'>-			gpio-keys {</div><div class='del'>-				compatible = "gpio-keys";</div><div class='del'>-</div><div class='del'>-				power-button {</div><div class='del'>-					debounce-interval = &lt;50&gt;;</div><div class='del'>-					wakeup-source;</div><div class='del'>-					linux,code = &lt;116&gt;;</div><div class='del'>-					label = "POWER";</div><div class='del'>-					gpios = &lt;&amp;iofpga_gpio0 0 0x4&gt;;</div><div class='del'>-				};</div><div class='del'>-				home-button {</div><div class='del'>-					debounce-interval = &lt;50&gt;;</div><div class='del'>-					wakeup-source;</div><div class='del'>-					linux,code = &lt;102&gt;;</div><div class='del'>-					label = "HOME";</div><div class='del'>-					gpios = &lt;&amp;iofpga_gpio0 1 0x4&gt;;</div><div class='del'>-				};</div><div class='del'>-				rlock-button {</div><div class='del'>-					debounce-interval = &lt;50&gt;;</div><div class='del'>-					wakeup-source;</div><div class='del'>-					linux,code = &lt;152&gt;;</div><div class='del'>-					label = "RLOCK";</div><div class='del'>-					gpios = &lt;&amp;iofpga_gpio0 2 0x4&gt;;</div><div class='del'>-				};</div><div class='del'>-				vol-up-button {</div><div class='del'>-					debounce-interval = &lt;50&gt;;</div><div class='del'>-					wakeup-source;</div><div class='del'>-					linux,code = &lt;115&gt;;</div><div class='del'>-					label = "VOL+";</div><div class='del'>-					gpios = &lt;&amp;iofpga_gpio0 3 0x4&gt;;</div><div class='del'>-				};</div><div class='del'>-				vol-down-button {</div><div class='del'>-					debounce-interval = &lt;50&gt;;</div><div class='del'>-					wakeup-source;</div><div class='del'>-					linux,code = &lt;114&gt;;</div><div class='del'>-					label = "VOL-";</div><div class='del'>-					gpios = &lt;&amp;iofpga_gpio0 4 0x4&gt;;</div><div class='del'>-				};</div><div class='del'>-				nmi-button {</div><div class='del'>-					debounce-interval = &lt;50&gt;;</div><div class='del'>-					wakeup-source;</div><div class='del'>-					linux,code = &lt;99&gt;;</div><div class='del'>-					label = "NMI";</div><div class='del'>-					gpios = &lt;&amp;iofpga_gpio0 5 0x4&gt;;</div><div class='del'>-				};</div><div class='del'>-			};</div><div class='ctx'> </div><div class='del'>-			flash@0,00000000 {</div><div class='add'>+			flash@0 {</div><div class='ctx'> 				/* 2 * 32MiB NOR Flash memory mounted on CS0 */</div><div class='ctx'> 				compatible = "arm,vexpress-flash", "cfi-flash";</div><div class='ctx'> 				reg = &lt;0 0x00000000 0x04000000&gt;;</div><div class='hunk'>@@ -120,7 +127,7 @@</div><div class='ctx'> 				};</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			ethernet@2,00000000 {</div><div class='add'>+			ethernet@200000000 {</div><div class='ctx'> 				compatible = "smsc,lan9118", "smsc,lan9115";</div><div class='ctx'> 				reg = &lt;2 0x00000000 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;3&gt;;</div><div class='hunk'>@@ -133,7 +140,7 @@</div><div class='ctx'> 				vddvario-supply = &lt;&amp;mb_fixed_3v3&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			iofpga@3,00000000 {</div><div class='add'>+			iofpga-bus@300000000 {</div><div class='ctx'> 				compatible = "simple-bus";</div><div class='ctx'> 				#address-cells = &lt;1&gt;;</div><div class='ctx'> 				#size-cells = &lt;1&gt;;</div><div class='hunk'>@@ -151,66 +158,78 @@</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='ctx'> 				apbregs@10000 {</div><div class='del'>-					compatible = "syscon", "simple-mfd";</div><div class='add'>+					compatible = "arm,juno-fpga-apb-regs",</div><div class='add'>+						     "syscon", "simple-mfd";</div><div class='ctx'> 					reg = &lt;0x010000 0x1000&gt;;</div><div class='add'>+					ranges = &lt;0x0 0x10000 0x1000&gt;;</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;1&gt;;</div><div class='ctx'> </div><div class='del'>-					led0 {</div><div class='add'>+					led@8,0 {</div><div class='ctx'> 						compatible = "register-bit-led";</div><div class='add'>+						reg = &lt;0x08 0x04&gt;;</div><div class='ctx'> 						offset = &lt;0x08&gt;;</div><div class='ctx'> 						mask = &lt;0x01&gt;;</div><div class='ctx'> 						label = "vexpress:0";</div><div class='ctx'> 						linux,default-trigger = "heartbeat";</div><div class='ctx'> 						default-state = "on";</div><div class='ctx'> 					};</div><div class='del'>-					led1 {</div><div class='add'>+					led@8,1 {</div><div class='ctx'> 						compatible = "register-bit-led";</div><div class='add'>+						reg = &lt;0x08 0x04&gt;;</div><div class='ctx'> 						offset = &lt;0x08&gt;;</div><div class='ctx'> 						mask = &lt;0x02&gt;;</div><div class='ctx'> 						label = "vexpress:1";</div><div class='ctx'> 						linux,default-trigger = "mmc0";</div><div class='ctx'> 						default-state = "off";</div><div class='ctx'> 					};</div><div class='del'>-					led2 {</div><div class='add'>+					led@8,2 {</div><div class='ctx'> 						compatible = "register-bit-led";</div><div class='add'>+						reg = &lt;0x08 0x04&gt;;</div><div class='ctx'> 						offset = &lt;0x08&gt;;</div><div class='ctx'> 						mask = &lt;0x04&gt;;</div><div class='ctx'> 						label = "vexpress:2";</div><div class='ctx'> 						linux,default-trigger = "cpu0";</div><div class='ctx'> 						default-state = "off";</div><div class='ctx'> 					};</div><div class='del'>-					led3 {</div><div class='add'>+					led@8,3 {</div><div class='ctx'> 						compatible = "register-bit-led";</div><div class='add'>+						reg = &lt;0x08 0x04&gt;;</div><div class='ctx'> 						offset = &lt;0x08&gt;;</div><div class='ctx'> 						mask = &lt;0x08&gt;;</div><div class='ctx'> 						label = "vexpress:3";</div><div class='ctx'> 						linux,default-trigger = "cpu1";</div><div class='ctx'> 						default-state = "off";</div><div class='ctx'> 					};</div><div class='del'>-					led4 {</div><div class='add'>+					led@8,4 {</div><div class='ctx'> 						compatible = "register-bit-led";</div><div class='add'>+						reg = &lt;0x08 0x04&gt;;</div><div class='ctx'> 						offset = &lt;0x08&gt;;</div><div class='ctx'> 						mask = &lt;0x10&gt;;</div><div class='ctx'> 						label = "vexpress:4";</div><div class='ctx'> 						linux,default-trigger = "cpu2";</div><div class='ctx'> 						default-state = "off";</div><div class='ctx'> 					};</div><div class='del'>-					led5 {</div><div class='add'>+					led@8,5 {</div><div class='ctx'> 						compatible = "register-bit-led";</div><div class='add'>+						reg = &lt;0x08 0x04&gt;;</div><div class='ctx'> 						offset = &lt;0x08&gt;;</div><div class='ctx'> 						mask = &lt;0x20&gt;;</div><div class='ctx'> 						label = "vexpress:5";</div><div class='ctx'> 						linux,default-trigger = "cpu3";</div><div class='ctx'> 						default-state = "off";</div><div class='ctx'> 					};</div><div class='del'>-					led6 {</div><div class='add'>+					led@8,6 {</div><div class='ctx'> 						compatible = "register-bit-led";</div><div class='add'>+						reg = &lt;0x08 0x04&gt;;</div><div class='ctx'> 						offset = &lt;0x08&gt;;</div><div class='ctx'> 						mask = &lt;0x40&gt;;</div><div class='ctx'> 						label = "vexpress:6";</div><div class='ctx'> 						default-state = "off";</div><div class='ctx'> 					};</div><div class='del'>-					led7 {</div><div class='add'>+					led@8,7 {</div><div class='ctx'> 						compatible = "register-bit-led";</div><div class='add'>+						reg = &lt;0x08 0x04&gt;;</div><div class='ctx'> 						offset = &lt;0x08&gt;;</div><div class='ctx'> 						mask = &lt;0x80&gt;;</div><div class='ctx'> 						label = "vexpress:7";</div><div class='hunk'>@@ -218,7 +237,7 @@</div><div class='ctx'> 					};</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				mmci@50000 {</div><div class='add'>+				mmc@50000 {</div><div class='ctx'> 					compatible = "arm,pl180", "arm,primecell";</div><div class='ctx'> 					reg = &lt;0x050000 0x1000&gt;;</div><div class='ctx'> 					interrupts = &lt;5&gt;;</div><div class='hunk'>@@ -246,12 +265,12 @@</div><div class='ctx'> 					clock-names = "KMIREFCLK", "apb_pclk";</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				wdt@f0000 {</div><div class='add'>+				watchdog@f0000 {</div><div class='ctx'> 					compatible = "arm,sp805", "arm,primecell";</div><div class='ctx'> 					reg = &lt;0x0f0000 0x10000&gt;;</div><div class='ctx'> 					interrupts = &lt;7&gt;;</div><div class='ctx'> 					clocks = &lt;&amp;mb_clk24mhz&gt;, &lt;&amp;soc_smc50mhz&gt;;</div><div class='del'>-					clock-names = "wdogclk", "apb_pclk";</div><div class='add'>+					clock-names = "wdog_clk", "apb_pclk";</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='ctx'> 				v2m_timer01: timer@110000 {</div><div class='head'>diff --git a/arch/arm64/boot/dts/arm/juno-r1-scmi.dts b/arch/arm64/boot/dts/arm/juno-r1-scmi.dts<br/>new file mode 100644<br/>index 000000000000..dd9ea69f086f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/arm/juno-r1-scmi.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/arm/juno-r1-scmi.dts</a></div><div class='hunk'>@@ -0,0 +1,27 @@</div><div class='add'>+#include "juno-r1.dts"</div><div class='add'>+#include "juno-scmi.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	funnel@20130000 {</div><div class='add'>+		power-domains = &lt;&amp;scmi_devpd 8&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	etf@20140000 {</div><div class='add'>+		power-domains = &lt;&amp;scmi_devpd 8&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	funnel@20150000 {</div><div class='add'>+		power-domains = &lt;&amp;scmi_devpd 8&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cti_sys2 {</div><div class='add'>+	power-domains = &lt;&amp;scmi_devpd 8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A57_0 {</div><div class='add'>+	clocks = &lt;&amp;scmi_dvfs 0&gt;;</div><div class='add'>+};</div><div class='add'>+&amp;A57_1 {</div><div class='add'>+	clocks = &lt;&amp;scmi_dvfs 0&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts<br/>index 5f290090b0cf..1d90eeebb37d 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/arm/juno-r1.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/arm/juno-r1.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/arm/juno-r1.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/arm/juno-r1.dts</a></div><div class='hunk'>@@ -9,6 +9,7 @@</div><div class='ctx'> /dts-v1/;</div><div class='ctx'> </div><div class='ctx'> #include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/arm/coresight-cti-dt.h&gt;</div><div class='ctx'> #include "juno-base.dtsi"</div><div class='ctx'> #include "juno-cs-r1r2.dtsi"</div><div class='ctx'> </div><div class='hunk'>@@ -188,16 +189,20 @@</div><div class='ctx'> </div><div class='ctx'> 		A57_L2: l2-cache0 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-unified;</div><div class='ctx'> 			cache-size = &lt;0x200000&gt;;</div><div class='ctx'> 			cache-line-size = &lt;64&gt;;</div><div class='ctx'> 			cache-sets = &lt;2048&gt;;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		A53_L2: l2-cache1 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-unified;</div><div class='ctx'> 			cache-size = &lt;0x100000&gt;;</div><div class='ctx'> 			cache-line-size = &lt;64&gt;;</div><div class='ctx'> 			cache-sets = &lt;1024&gt;;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -230,6 +235,10 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;smmu_pcie {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;etm0 {</div><div class='ctx'> 	cpu = &lt;&amp;A57_0&gt;;</div><div class='ctx'> };</div><div class='hunk'>@@ -309,3 +318,27 @@</div><div class='ctx'> &amp;cpu_debug5 {</div><div class='ctx'> 	cpu = &lt;&amp;A53_3&gt;;</div><div class='ctx'> };</div><div class='add'>+</div><div class='add'>+&amp;cti0 {</div><div class='add'>+	cpu = &lt;&amp;A57_0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cti1 {</div><div class='add'>+	cpu = &lt;&amp;A57_1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cti2 {</div><div class='add'>+	cpu = &lt;&amp;A53_0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cti3 {</div><div class='add'>+	cpu = &lt;&amp;A53_1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cti4 {</div><div class='add'>+	cpu = &lt;&amp;A53_2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cti5 {</div><div class='add'>+	cpu = &lt;&amp;A53_3&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/arm/juno-r2-scmi.dts b/arch/arm64/boot/dts/arm/juno-r2-scmi.dts<br/>new file mode 100644<br/>index 000000000000..de2cbac1d1c3<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/arm/juno-r2-scmi.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/arm/juno-r2-scmi.dts</a></div><div class='hunk'>@@ -0,0 +1,27 @@</div><div class='add'>+#include "juno-r2.dts"</div><div class='add'>+#include "juno-scmi.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	funnel@20130000 {</div><div class='add'>+		power-domains = &lt;&amp;scmi_devpd 8&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	etf@20140000 {</div><div class='add'>+		power-domains = &lt;&amp;scmi_devpd 8&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	funnel@20150000 {</div><div class='add'>+		power-domains = &lt;&amp;scmi_devpd 8&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cti_sys2 {</div><div class='add'>+	power-domains = &lt;&amp;scmi_devpd 8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A72_0 {</div><div class='add'>+	clocks = &lt;&amp;scmi_dvfs 0&gt;;</div><div class='add'>+};</div><div class='add'>+&amp;A72_1 {</div><div class='add'>+	clocks = &lt;&amp;scmi_dvfs 0&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/arm/juno-r2.dts b/arch/arm64/boot/dts/arm/juno-r2.dts<br/>index 305300dd521c..d2ada69b0a43 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/arm/juno-r2.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/arm/juno-r2.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/arm/juno-r2.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/arm/juno-r2.dts</a></div><div class='hunk'>@@ -9,6 +9,7 @@</div><div class='ctx'> /dts-v1/;</div><div class='ctx'> </div><div class='ctx'> #include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/arm/coresight-cti-dt.h&gt;</div><div class='ctx'> #include "juno-base.dtsi"</div><div class='ctx'> #include "juno-cs-r1r2.dtsi"</div><div class='ctx'> </div><div class='hunk'>@@ -194,16 +195,20 @@</div><div class='ctx'> </div><div class='ctx'> 		A72_L2: l2-cache0 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-unified;</div><div class='ctx'> 			cache-size = &lt;0x200000&gt;;</div><div class='ctx'> 			cache-line-size = &lt;64&gt;;</div><div class='ctx'> 			cache-sets = &lt;2048&gt;;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		A53_L2: l2-cache1 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-unified;</div><div class='ctx'> 			cache-size = &lt;0x100000&gt;;</div><div class='ctx'> 			cache-line-size = &lt;64&gt;;</div><div class='ctx'> 			cache-sets = &lt;1024&gt;;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -236,6 +241,10 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;smmu_pcie {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;etm0 {</div><div class='ctx'> 	cpu = &lt;&amp;A72_0&gt;;</div><div class='ctx'> };</div><div class='hunk'>@@ -315,3 +324,27 @@</div><div class='ctx'> &amp;cpu_debug5 {</div><div class='ctx'> 	cpu = &lt;&amp;A53_3&gt;;</div><div class='ctx'> };</div><div class='add'>+</div><div class='add'>+&amp;cti0 {</div><div class='add'>+	cpu = &lt;&amp;A72_0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cti1 {</div><div class='add'>+	cpu = &lt;&amp;A72_1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cti2 {</div><div class='add'>+	cpu = &lt;&amp;A53_0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cti3 {</div><div class='add'>+	cpu = &lt;&amp;A53_1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cti4 {</div><div class='add'>+	cpu = &lt;&amp;A53_2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cti5 {</div><div class='add'>+	cpu = &lt;&amp;A53_3&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/arm/juno-scmi.dts b/arch/arm64/boot/dts/arm/juno-scmi.dts<br/>new file mode 100644<br/>index 000000000000..41588fa46d31<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/arm/juno-scmi.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/arm/juno-scmi.dts</a></div><div class='hunk'>@@ -0,0 +1,9 @@</div><div class='add'>+#include "juno.dts"</div><div class='add'>+#include "juno-scmi.dtsi"</div><div class='add'>+</div><div class='add'>+&amp;A57_0 {</div><div class='add'>+	clocks = &lt;&amp;scmi_dvfs 0&gt;;</div><div class='add'>+};</div><div class='add'>+&amp;A57_1 {</div><div class='add'>+	clocks = &lt;&amp;scmi_dvfs 0&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/arm/juno-scmi.dtsi b/arch/arm64/boot/dts/arm/juno-scmi.dtsi<br/>new file mode 100644<br/>index 000000000000..f38c5b6ef657<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/arm/juno-scmi.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/arm/juno-scmi.dtsi</a></div><div class='hunk'>@@ -0,0 +1,223 @@</div><div class='add'>+/ {</div><div class='add'>+	etf@20010000 {</div><div class='add'>+		power-domains = &lt;&amp;scmi_devpd 8&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	tpiu@20030000 {</div><div class='add'>+		power-domains = &lt;&amp;scmi_devpd 8&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	funnel@20040000 {</div><div class='add'>+		power-domains = &lt;&amp;scmi_devpd 8&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	etr@20070000 {</div><div class='add'>+		power-domains = &lt;&amp;scmi_devpd 8&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	stm@20100000 {</div><div class='add'>+		power-domains = &lt;&amp;scmi_devpd 8&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	replicator@20120000 {</div><div class='add'>+		power-domains = &lt;&amp;scmi_devpd 8&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	funnel@220c0000 {</div><div class='add'>+		power-domains = &lt;&amp;scmi_devpd 8&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	funnel@230c0000 {</div><div class='add'>+		power-domains = &lt;&amp;scmi_devpd 8&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdlcd@7ff50000 {</div><div class='add'>+		clocks = &lt;&amp;scmi_clk 3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdlcd@7ff60000 {</div><div class='add'>+		clocks = &lt;&amp;scmi_clk 3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/delete-node/ scpi;</div><div class='add'>+</div><div class='add'>+	firmware {</div><div class='add'>+		scmi {</div><div class='add'>+			compatible = "arm,scmi";</div><div class='add'>+			mbox-names = "tx", "rx";</div><div class='add'>+			mboxes = &lt;&amp;mailbox 0 0 &amp;mailbox 0 1&gt;;</div><div class='add'>+			shmem = &lt;&amp;cpu_scp_lpri0 &amp;cpu_scp_lpri1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			scmi_devpd: protocol@11 {</div><div class='add'>+				reg = &lt;0x11&gt;;</div><div class='add'>+				#power-domain-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			scmi_dvfs: protocol@13 {</div><div class='add'>+				reg = &lt;0x13&gt;;</div><div class='add'>+				#clock-cells = &lt;1&gt;;</div><div class='add'>+				mbox-names = "tx", "rx";</div><div class='add'>+				mboxes = &lt;&amp;mailbox 1 0 &amp;mailbox 1 1&gt;;</div><div class='add'>+				shmem = &lt;&amp;cpu_scp_hpri0 &amp;cpu_scp_hpri1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			scmi_clk: protocol@14 {</div><div class='add'>+				reg = &lt;0x14&gt;;</div><div class='add'>+				#clock-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			scmi_sensors0: protocol@15 {</div><div class='add'>+				reg = &lt;0x15&gt;;</div><div class='add'>+				#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	thermal-zones {</div><div class='add'>+		pmic-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;scmi_sensors0 0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		soc-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;scmi_sensors0 3&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		big-cl-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;scmi_sensors0 21&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		little-cl-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;scmi_sensors0 22&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu0-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;scmi_sensors0 23&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu1-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;scmi_sensors0 24&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	clocks = &lt;&amp;scmi_dvfs 1&gt;;</div><div class='add'>+};</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	clocks = &lt;&amp;scmi_dvfs 1&gt;;</div><div class='add'>+};</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	clocks = &lt;&amp;scmi_dvfs 1&gt;;</div><div class='add'>+};</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	clocks = &lt;&amp;scmi_dvfs 1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu_debug0 {</div><div class='add'>+	power-domains = &lt;&amp;scmi_devpd 8&gt;;</div><div class='add'>+};</div><div class='add'>+&amp;cpu_debug1 {</div><div class='add'>+	power-domains = &lt;&amp;scmi_devpd 8&gt;;</div><div class='add'>+};</div><div class='add'>+&amp;cpu_debug2 {</div><div class='add'>+	power-domains = &lt;&amp;scmi_devpd 8&gt;;</div><div class='add'>+};</div><div class='add'>+&amp;cpu_debug3 {</div><div class='add'>+	power-domains = &lt;&amp;scmi_devpd 8&gt;;</div><div class='add'>+};</div><div class='add'>+&amp;cpu_debug4 {</div><div class='add'>+	power-domains = &lt;&amp;scmi_devpd 8&gt;;</div><div class='add'>+};</div><div class='add'>+&amp;cpu_debug5 {</div><div class='add'>+	power-domains = &lt;&amp;scmi_devpd 8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;etm0 {</div><div class='add'>+	power-domains = &lt;&amp;scmi_devpd 8&gt;;</div><div class='add'>+};</div><div class='add'>+&amp;etm1 {</div><div class='add'>+	power-domains = &lt;&amp;scmi_devpd 8&gt;;</div><div class='add'>+};</div><div class='add'>+&amp;etm2 {</div><div class='add'>+	power-domains = &lt;&amp;scmi_devpd 8&gt;;</div><div class='add'>+};</div><div class='add'>+&amp;etm3 {</div><div class='add'>+	power-domains = &lt;&amp;scmi_devpd 8&gt;;</div><div class='add'>+};</div><div class='add'>+&amp;etm4 {</div><div class='add'>+	power-domains = &lt;&amp;scmi_devpd 8&gt;;</div><div class='add'>+};</div><div class='add'>+&amp;etm5 {</div><div class='add'>+	power-domains = &lt;&amp;scmi_devpd 8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cti0 {</div><div class='add'>+	power-domains = &lt;&amp;scmi_devpd 8&gt;;</div><div class='add'>+};</div><div class='add'>+&amp;cti1 {</div><div class='add'>+	power-domains = &lt;&amp;scmi_devpd 8&gt;;</div><div class='add'>+};</div><div class='add'>+&amp;cti2 {</div><div class='add'>+	power-domains = &lt;&amp;scmi_devpd 8&gt;;</div><div class='add'>+};</div><div class='add'>+&amp;cti3 {</div><div class='add'>+	power-domains = &lt;&amp;scmi_devpd 8&gt;;</div><div class='add'>+};</div><div class='add'>+&amp;cti4 {</div><div class='add'>+	power-domains = &lt;&amp;scmi_devpd 8&gt;;</div><div class='add'>+};</div><div class='add'>+&amp;cti5 {</div><div class='add'>+	power-domains = &lt;&amp;scmi_devpd 8&gt;;</div><div class='add'>+};</div><div class='add'>+&amp;cti_sys0 {</div><div class='add'>+	power-domains = &lt;&amp;scmi_devpd 8&gt;;</div><div class='add'>+};</div><div class='add'>+&amp;cti_sys1 {</div><div class='add'>+	power-domains = &lt;&amp;scmi_devpd 8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	clocks = &lt;&amp;scmi_dvfs 2&gt;;</div><div class='add'>+	power-domains = &lt;&amp;scmi_devpd 9&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mailbox {</div><div class='add'>+	compatible = "arm,mhu-doorbell", "arm,primecell";</div><div class='add'>+	#mbox-cells = &lt;2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;smmu_etr {</div><div class='add'>+	power-domains = &lt;&amp;scmi_devpd 8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;smmu_gpu {</div><div class='add'>+	power-domains = &lt;&amp;scmi_devpd 9&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sram {</div><div class='add'>+	/delete-node/ scp-sram@0;</div><div class='add'>+	/delete-node/ scp-sram@200;</div><div class='add'>+</div><div class='add'>+	cpu_scp_lpri0: scp-sram@0 {</div><div class='add'>+		compatible = "arm,scmi-shmem";</div><div class='add'>+		reg = &lt;0x0 0x80&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpu_scp_lpri1: scp-sram@80 {</div><div class='add'>+		compatible = "arm,scmi-shmem";</div><div class='add'>+		reg = &lt;0x80 0x80&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpu_scp_hpri0: scp-sram@100 {</div><div class='add'>+		compatible = "arm,scmi-shmem";</div><div class='add'>+		reg = &lt;0x100 0x80&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpu_scp_hpri1: scp-sram@180 {</div><div class='add'>+		compatible = "arm,scmi-shmem";</div><div class='add'>+		reg = &lt;0x180 0x80&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts<br/>index f00cffbd032c..5e48a01a5b9f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/arm/juno.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/arm/juno.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/arm/juno.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/arm/juno.dts</a></div><div class='hunk'>@@ -9,6 +9,7 @@</div><div class='ctx'> /dts-v1/;</div><div class='ctx'> </div><div class='ctx'> #include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/arm/coresight-cti-dt.h&gt;</div><div class='ctx'> #include "juno-base.dtsi"</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='hunk'>@@ -193,16 +194,20 @@</div><div class='ctx'> </div><div class='ctx'> 		A57_L2: l2-cache0 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-unified;</div><div class='ctx'> 			cache-size = &lt;0x200000&gt;;</div><div class='ctx'> 			cache-line-size = &lt;64&gt;;</div><div class='ctx'> 			cache-sets = &lt;2048&gt;;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		A53_L2: l2-cache1 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-unified;</div><div class='ctx'> 			cache-size = &lt;0x100000&gt;;</div><div class='ctx'> 			cache-line-size = &lt;64&gt;;</div><div class='ctx'> 			cache-sets = &lt;1024&gt;;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -295,3 +300,27 @@</div><div class='ctx'> &amp;cpu_debug5 {</div><div class='ctx'> 	cpu = &lt;&amp;A53_3&gt;;</div><div class='ctx'> };</div><div class='add'>+</div><div class='add'>+&amp;cti0 {</div><div class='add'>+	cpu = &lt;&amp;A57_0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cti1 {</div><div class='add'>+	cpu = &lt;&amp;A57_1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cti2 {</div><div class='add'>+	cpu = &lt;&amp;A53_0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cti3 {</div><div class='add'>+	cpu = &lt;&amp;A53_1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cti4 {</div><div class='add'>+	cpu = &lt;&amp;A53_2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cti5 {</div><div class='add'>+	cpu = &lt;&amp;A53_3&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/arm/morello-fvp.dts b/arch/arm64/boot/dts/arm/morello-fvp.dts<br/>new file mode 100644<br/>index 000000000000..2072c0b72325<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/arm/morello-fvp.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/arm/morello-fvp.dts</a></div><div class='hunk'>@@ -0,0 +1,77 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2021-2024, Arm Limited. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "morello.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Arm Morello Fixed Virtual Platform";</div><div class='add'>+	compatible = "arm,morello-fvp", "arm,morello";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bp_refclock24mhz: clock-24000000 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+		clock-output-names = "bp:clock24mhz";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	block_0: virtio_block@1c170000 {</div><div class='add'>+		compatible = "virtio,mmio";</div><div class='add'>+		reg = &lt;0x0 0x1c170000 0x0 0x200&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	net_0: virtio_net@1c180000 {</div><div class='add'>+		compatible = "virtio,mmio";</div><div class='add'>+		reg = &lt;0x0 0x1c180000 0x0 0x200&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rng_0: virtio_rng@1c190000 {</div><div class='add'>+		compatible = "virtio,mmio";</div><div class='add'>+		reg = &lt;0x0 0x1c190000 0x0 0x200&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	p9_0: virtio_p9@1c1a0000 {</div><div class='add'>+		compatible = "virtio,mmio";</div><div class='add'>+		reg = &lt;0x0 0x1c1a0000 0x0 0x200&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	kmi_0: kmi@1c150000 {</div><div class='add'>+		compatible = "arm,pl050", "arm,primecell";</div><div class='add'>+		reg = &lt;0x0 0x1c150000 0x0 0x1000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;bp_refclock24mhz&gt;, &lt;&amp;bp_refclock24mhz&gt;;</div><div class='add'>+		clock-names = "KMIREFCLK", "apb_pclk";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	kmi_1: kmi@1c160000 {</div><div class='add'>+		compatible = "arm,pl050", "arm,primecell";</div><div class='add'>+		reg = &lt;0x0 0x1c160000 0x0 0x1000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;bp_refclock24mhz&gt;, &lt;&amp;bp_refclock24mhz&gt;;</div><div class='add'>+		clock-names = "KMIREFCLK", "apb_pclk";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eth_0: ethernet@1d100000 {</div><div class='add'>+		compatible = "smsc,lan91c111";</div><div class='add'>+		reg = &lt;0x0 0x1d100000 0x0 0x10000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/arm/morello-sdp.dts b/arch/arm64/boot/dts/arm/morello-sdp.dts<br/>new file mode 100644<br/>index 000000000000..cee49dee7571<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/arm/morello-sdp.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/arm/morello-sdp.dts</a></div><div class='hunk'>@@ -0,0 +1,157 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2021-2024, Arm Limited. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "morello.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Arm Morello System Development Platform";</div><div class='add'>+	compatible = "arm,morello-sdp", "arm,morello";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dpu_aclk: clock-350000000 {</div><div class='add'>+		/* 77.1 MHz derived from 24 MHz reference clock */</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;350000000&gt;;</div><div class='add'>+		clock-output-names = "aclk";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dpu_pixel_clk: clock-148500000 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;148500000&gt;;</div><div class='add'>+		clock-output-names = "pxclk";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c0: i2c@1c0f0000 {</div><div class='add'>+		compatible = "cdns,i2c-r1p14";</div><div class='add'>+		reg = &lt;0x0 0x1c0f0000 0x0 0x1000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;dpu_aclk&gt;;</div><div class='add'>+</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		clock-frequency = &lt;100000&gt;;</div><div class='add'>+</div><div class='add'>+		hdmi_tx: hdmi-transmitter@70 {</div><div class='add'>+			compatible = "nxp,tda998x";</div><div class='add'>+			reg = &lt;0x70&gt;;</div><div class='add'>+			video-ports = &lt;0x234501&gt;;</div><div class='add'>+			port {</div><div class='add'>+				tda998x_0_input: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;dp_pl0_out0&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dp0: display@2cc00000 {</div><div class='add'>+		compatible = "arm,mali-d32", "arm,mali-d71";</div><div class='add'>+		reg = &lt;0x0 0x2cc00000 0x0 0x20000&gt;;</div><div class='add'>+		interrupts = &lt;0 69 4&gt;;</div><div class='add'>+		clocks = &lt;&amp;dpu_aclk&gt;;</div><div class='add'>+		clock-names = "aclk";</div><div class='add'>+		iommus = &lt;&amp;smmu_dp 0&gt;, &lt;&amp;smmu_dp 1&gt;, &lt;&amp;smmu_dp 2&gt;, &lt;&amp;smmu_dp 3&gt;,</div><div class='add'>+			 &lt;&amp;smmu_dp 8&gt;;</div><div class='add'>+</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		pl0: pipeline@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			clocks = &lt;&amp;dpu_pixel_clk&gt;;</div><div class='add'>+			clock-names = "pxclk";</div><div class='add'>+			port {</div><div class='add'>+				dp_pl0_out0: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;tda998x_0_input&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	smmu_ccix: iommu@4f000000 {</div><div class='add'>+		compatible = "arm,smmu-v3";</div><div class='add'>+		reg = &lt;0x0 0x4f000000 0x0 0x40000&gt;;</div><div class='add'>+</div><div class='add'>+		interrupts = &lt;GIC_SPI 228 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					&lt;GIC_SPI 230 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					&lt;GIC_SPI 41 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					&lt;GIC_SPI 229 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+		interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";</div><div class='add'>+		msi-parent = &lt;&amp;its1 0&gt;;</div><div class='add'>+		#iommu-cells = &lt;1&gt;;</div><div class='add'>+		dma-coherent;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	smmu_pcie: iommu@4f400000 {</div><div class='add'>+		compatible = "arm,smmu-v3";</div><div class='add'>+		reg = &lt;0x0 0x4f400000 0x0 0x40000&gt;;</div><div class='add'>+</div><div class='add'>+		interrupts = &lt;GIC_SPI 235 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					&lt;GIC_SPI 237 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					&lt;GIC_SPI 40 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					&lt;GIC_SPI 236 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+		interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";</div><div class='add'>+		msi-parent = &lt;&amp;its2 0&gt;;</div><div class='add'>+		#iommu-cells = &lt;1&gt;;</div><div class='add'>+		dma-coherent;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie_ctlr: pcie@28c0000000 {</div><div class='add'>+		device_type = "pci";</div><div class='add'>+		compatible = "pci-host-ecam-generic";</div><div class='add'>+		reg = &lt;0x28 0xC0000000 0 0x10000000&gt;;</div><div class='add'>+		ranges = &lt;0x01000000 0x00 0x00000000 0x00 0x6f000000 0x00 0x00800000&gt;,</div><div class='add'>+				&lt;0x02000000 0x00 0x60000000 0x00 0x60000000 0x00 0x0f000000&gt;,</div><div class='add'>+				&lt;0x42000000 0x09 0x00000000 0x09 0x00000000 0x1f 0xc0000000&gt;;</div><div class='add'>+		bus-range = &lt;0 255&gt;;</div><div class='add'>+		linux,pci-domain = &lt;0&gt;;</div><div class='add'>+		#address-cells = &lt;3&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		dma-coherent;</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='add'>+		interrupt-map = &lt;0 0 0 1 &amp;gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 0 2 &amp;gic 0 0 0 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 0 3 &amp;gic 0 0 0 171 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 0 4 &amp;gic 0 0 0 172 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		msi-map = &lt;0 &amp;its_pcie 0 0x10000&gt;;</div><div class='add'>+		iommu-map = &lt;0 &amp;smmu_pcie 0 0x10000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ccix_pcie_ctlr: pcie@4fc0000000 {</div><div class='add'>+		device_type = "pci";</div><div class='add'>+		compatible = "pci-host-ecam-generic";</div><div class='add'>+		reg = &lt;0x4f 0xC0000000 0 0x10000000&gt;;</div><div class='add'>+		ranges = &lt;0x01000000 0x00 0x00000000 0x00 0x7f000000 0x00 0x00800000&gt;,</div><div class='add'>+				&lt;0x02000000 0x00 0x70000000 0x00 0x70000000 0x00 0x0f000000&gt;,</div><div class='add'>+				&lt;0x42000000 0x30 0x00000000 0x30 0x00000000 0x1f 0xc0000000&gt;;</div><div class='add'>+		linux,pci-domain = &lt;1&gt;;</div><div class='add'>+		#address-cells = &lt;3&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		dma-coherent;</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='add'>+		interrupt-map = &lt;0 0 0 1 &amp;gic 0 0 0 201 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 0 2 &amp;gic 0 0 0 202 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 0 3 &amp;gic 0 0 0 203 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 0 4 &amp;gic 0 0 0 204 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		msi-map = &lt;0 &amp;its_ccix 0 0x10000&gt;;</div><div class='add'>+		iommu-map = &lt;0 &amp;smmu_ccix 0 0x10000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/arm/morello.dtsi b/arch/arm64/boot/dts/arm/morello.dtsi<br/>new file mode 100644<br/>index 000000000000..5bc1c725dc86<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/arm/morello.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/arm/morello.dtsi</a></div><div class='hunk'>@@ -0,0 +1,323 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2020-2024, Arm Limited. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	soc_refclk50mhz: clock-50000000 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;50000000&gt;;</div><div class='add'>+		clock-output-names = "apb_pclk";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc_refclk85mhz: clock-85000000 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;85000000&gt;;</div><div class='add'>+		clock-output-names = "iofpga:aclk";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			compatible = "arm,rainier";</div><div class='add'>+			reg = &lt;0x0 0x0&gt;;</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			/* 4 ways set associative */</div><div class='add'>+			i-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;512&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;512&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_dvfs 0&gt;;</div><div class='add'>+</div><div class='add'>+			l2_0: l2-cache {</div><div class='add'>+				compatible = "cache";</div><div class='add'>+				cache-level = &lt;2&gt;;</div><div class='add'>+				/* 8 ways set associative */</div><div class='add'>+				cache-size = &lt;0x100000&gt;;</div><div class='add'>+				cache-line-size = &lt;64&gt;;</div><div class='add'>+				cache-sets = &lt;2048&gt;;</div><div class='add'>+				cache-unified;</div><div class='add'>+				next-level-cache = &lt;&amp;l3_0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@100 {</div><div class='add'>+			compatible = "arm,rainier";</div><div class='add'>+			reg = &lt;0x0 0x100&gt;;</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			/* 4 ways set associative */</div><div class='add'>+			i-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;512&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;512&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_1&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_dvfs 0&gt;;</div><div class='add'>+</div><div class='add'>+			l2_1: l2-cache {</div><div class='add'>+				compatible = "cache";</div><div class='add'>+				cache-level = &lt;2&gt;;</div><div class='add'>+				/* 8 ways set associative */</div><div class='add'>+				cache-size = &lt;0x100000&gt;;</div><div class='add'>+				cache-line-size = &lt;64&gt;;</div><div class='add'>+				cache-sets = &lt;2048&gt;;</div><div class='add'>+				cache-unified;</div><div class='add'>+				next-level-cache = &lt;&amp;l3_0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@10000 {</div><div class='add'>+			compatible = "arm,rainier";</div><div class='add'>+			reg = &lt;0x0 0x10000&gt;;</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			/* 4 ways set associative */</div><div class='add'>+			i-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;512&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;512&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_2&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_dvfs 1&gt;;</div><div class='add'>+</div><div class='add'>+			l2_2: l2-cache {</div><div class='add'>+				compatible = "cache";</div><div class='add'>+				cache-level = &lt;2&gt;;</div><div class='add'>+				/* 8 ways set associative */</div><div class='add'>+				cache-size = &lt;0x100000&gt;;</div><div class='add'>+				cache-line-size = &lt;64&gt;;</div><div class='add'>+				cache-sets = &lt;2048&gt;;</div><div class='add'>+				cache-unified;</div><div class='add'>+				next-level-cache = &lt;&amp;l3_0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@10100 {</div><div class='add'>+			compatible = "arm,rainier";</div><div class='add'>+			reg = &lt;0x0 0x10100&gt;;</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			/* 4 ways set associative */</div><div class='add'>+			i-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;512&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;512&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_3&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_dvfs 1&gt;;</div><div class='add'>+</div><div class='add'>+			l2_3: l2-cache {</div><div class='add'>+				compatible = "cache";</div><div class='add'>+				cache-level = &lt;2&gt;;</div><div class='add'>+				/* 8 ways set associative */</div><div class='add'>+				cache-size = &lt;0x100000&gt;;</div><div class='add'>+				cache-line-size = &lt;64&gt;;</div><div class='add'>+				cache-sets = &lt;2048&gt;;</div><div class='add'>+				cache-unified;</div><div class='add'>+				next-level-cache = &lt;&amp;l3_0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l3_0: l3-cache {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;3&gt;;</div><div class='add'>+			cache-size = &lt;0x100000&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	firmware {</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+</div><div class='add'>+		scmi {</div><div class='add'>+			compatible = "arm,scmi";</div><div class='add'>+			mbox-names = "tx", "rx";</div><div class='add'>+			mboxes = &lt;&amp;mailbox 1 0&gt;, &lt;&amp;mailbox 1 1&gt;;</div><div class='add'>+			shmem = &lt;&amp;cpu_scp_hpri0&gt;, &lt;&amp;cpu_scp_hpri1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			scmi_dvfs: protocol@13 {</div><div class='add'>+				reg = &lt;0x13&gt;;</div><div class='add'>+				#clock-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			scmi_clk: protocol@14 {</div><div class='add'>+				reg = &lt;0x14&gt;;</div><div class='add'>+				#clock-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* The first bank of memory, memory map is actually provided by UEFI. */</div><div class='add'>+	memory@80000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		/* [0x80000000-0xffffffff] */</div><div class='add'>+		reg = &lt;0x00000000 0x80000000 0x0 0x7f000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@8080000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		/* [0x8080000000-0x83f7ffffff] */</div><div class='add'>+		reg = &lt;0x00000080 0x80000000 0x3 0x78000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu {</div><div class='add'>+		compatible = "arm,rainier-pmu";</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-0.2";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		secure-firmware@ff000000 {</div><div class='add'>+			reg = &lt;0x0 0xff000000 0x0 0x01000000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spe-pmu {</div><div class='add'>+		compatible = "arm,statistical-profiling-extension-v1";</div><div class='add'>+		interrupts = &lt;GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc: soc {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		uart0: serial@2a400000 {</div><div class='add'>+			compatible = "arm,pl011", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x2a400000 0x0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;soc_refclk50mhz&gt;, &lt;&amp;soc_refclk50mhz&gt;;</div><div class='add'>+			clock-names = "uartclk", "apb_pclk";</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@30000000 {</div><div class='add'>+			compatible = "arm,gic-v3";</div><div class='add'>+			reg = &lt;0x0 0x30000000 0x0 0x10000&gt;,	/* GICD */</div><div class='add'>+			      &lt;0x0 0x300c0000 0x0 0x80000&gt;;	/* GICR */</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			its1: msi-controller@30040000 {</div><div class='add'>+				compatible = "arm,gic-v3-its";</div><div class='add'>+				reg = &lt;0x0 0x30040000 0x0 0x20000&gt;;</div><div class='add'>+</div><div class='add'>+				msi-controller;</div><div class='add'>+				#msi-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			its2: msi-controller@30060000 {</div><div class='add'>+				compatible = "arm,gic-v3-its";</div><div class='add'>+				reg = &lt;0x0 0x30060000 0x0 0x20000&gt;;</div><div class='add'>+</div><div class='add'>+				msi-controller;</div><div class='add'>+				#msi-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			its_ccix: msi-controller@30080000 {</div><div class='add'>+				compatible = "arm,gic-v3-its";</div><div class='add'>+				reg = &lt;0x0 0x30080000 0x0 0x20000&gt;;</div><div class='add'>+</div><div class='add'>+				msi-controller;</div><div class='add'>+				#msi-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			its_pcie: msi-controller@300a0000 {</div><div class='add'>+				compatible = "arm,gic-v3-its";</div><div class='add'>+				reg = &lt;0x0 0x300a0000 0x0 0x20000&gt;;</div><div class='add'>+</div><div class='add'>+				msi-controller;</div><div class='add'>+				#msi-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smmu_dp: iommu@2ce00000 {</div><div class='add'>+			compatible = "arm,smmu-v3";</div><div class='add'>+			reg = &lt;0x0 0x2ce00000 0x0 0x40000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 76 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 80 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 78 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			interrupt-names = "eventq", "gerror", "cmdq-sync";</div><div class='add'>+			#iommu-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mailbox: mhu@45000000 {</div><div class='add'>+			compatible = "arm,mhu-doorbell", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x45000000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#mbox-cells = &lt;2&gt;;</div><div class='add'>+			clocks = &lt;&amp;soc_refclk50mhz&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sram: sram@6000000 {</div><div class='add'>+			compatible = "mmio-sram";</div><div class='add'>+			reg = &lt;0x0 0x06000000 0x0 0x8000&gt;;</div><div class='add'>+			ranges = &lt;0 0x0 0x06000000 0x8000&gt;;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			cpu_scp_hpri0: scp-sram@0 {</div><div class='add'>+				compatible = "arm,scmi-shmem";</div><div class='add'>+				reg = &lt;0x0 0x80&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cpu_scp_hpri1: scp-sram@80 {</div><div class='add'>+				compatible = "arm,scmi-shmem";</div><div class='add'>+				reg = &lt;0x80 0x80&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts<br/>index c5d15cbd8cf6..a4a29193d4eb 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts</a></div><div class='hunk'>@@ -23,7 +23,9 @@</div><div class='ctx'> 	#address-cells = &lt;2&gt;;</div><div class='ctx'> 	#size-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='del'>-	chosen { };</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='ctx'> </div><div class='ctx'> 	aliases {</div><div class='ctx'> 		serial0 = &amp;v2m_serial0;</div><div class='hunk'>@@ -71,6 +73,8 @@</div><div class='ctx'> </div><div class='ctx'> 		L2_0: l2-cache0 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -95,7 +99,7 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	gic: interrupt-controller@2c001000 {</div><div class='del'>-		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";</div><div class='add'>+		compatible = "arm,gic-400", "arm,cortex-a15-gic";</div><div class='ctx'> 		#interrupt-cells = &lt;3&gt;;</div><div class='ctx'> 		#address-cells = &lt;0&gt;;</div><div class='ctx'> 		interrupt-controller;</div><div class='hunk'>@@ -112,7 +116,6 @@</div><div class='ctx'> 			     &lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='ctx'> 			     &lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='ctx'> 			     &lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='del'>-		clock-frequency = &lt;100000000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	pmu {</div><div class='hunk'>@@ -133,17 +136,6 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	bus@8000000 {</div><div class='del'>-		compatible = "simple-bus";</div><div class='del'>-</div><div class='del'>-		#address-cells = &lt;2&gt;;</div><div class='del'>-		#size-cells = &lt;1&gt;;</div><div class='del'>-		ranges = &lt;0 0 0 0x08000000 0x04000000&gt;,</div><div class='del'>-			 &lt;1 0 0 0x14000000 0x04000000&gt;,</div><div class='del'>-			 &lt;2 0 0 0x18000000 0x04000000&gt;,</div><div class='del'>-			 &lt;3 0 0 0x1c000000 0x04000000&gt;,</div><div class='del'>-			 &lt;4 0 0 0x0c000000 0x04000000&gt;,</div><div class='del'>-			 &lt;5 0 0 0x10000000 0x04000000&gt;;</div><div class='del'>-</div><div class='ctx'> 		#interrupt-cells = &lt;1&gt;;</div><div class='ctx'> 		interrupt-map-mask = &lt;0 0 63&gt;;</div><div class='ctx'> 		interrupt-map = &lt;0 0  0 &amp;gic GIC_SPI  0 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='head'>diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi<br/>index 60703b5763c6..ec2d5280a30b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi</a></div><div class='hunk'>@@ -6,21 +6,28 @@</div><div class='ctx'>  */</div><div class='ctx'> / {</div><div class='ctx'> 	bus@8000000 {</div><div class='del'>-		motherboard {</div><div class='add'>+		motherboard-bus@8000000 {</div><div class='ctx'> 			arm,v2m-memory-map = "rs2";</div><div class='ctx'> </div><div class='del'>-			iofpga@3,00000000 {</div><div class='del'>-				virtio-p9@140000 {</div><div class='add'>+			iofpga-bus@300000000 {</div><div class='add'>+				virtio@140000 {</div><div class='ctx'> 					compatible = "virtio,mmio";</div><div class='ctx'> 					reg = &lt;0x140000 0x200&gt;;</div><div class='ctx'> 					interrupts = &lt;43&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				virtio-net@150000 {</div><div class='add'>+				virtio@150000 {</div><div class='ctx'> 					compatible = "virtio,mmio";</div><div class='ctx'> 					reg = &lt;0x150000 0x200&gt;;</div><div class='ctx'> 					interrupts = &lt;44&gt;;</div><div class='ctx'> 				};</div><div class='add'>+</div><div class='add'>+				virtio@200000 {</div><div class='add'>+					compatible = "virtio,mmio";</div><div class='add'>+					reg = &lt;0x200000 0x200&gt;;</div><div class='add'>+					interrupts = &lt;46&gt;;</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='head'>diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi<br/>index e333c8d2d0e4..66b1b74d27dc 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi</a></div><div class='hunk'>@@ -8,54 +8,109 @@</div><div class='ctx'>  * VEMotherBoard.lisa</div><div class='ctx'>  */</div><div class='ctx'> / {</div><div class='add'>+	v2m_clk24mhz: clock-24000000 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+		clock-output-names = "v2m:clk24mhz";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	v2m_refclk1mhz: clock-1000000 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;1000000&gt;;</div><div class='add'>+		clock-output-names = "v2m:refclk1mhz";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	v2m_refclk32khz: clock-32768 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;32768&gt;;</div><div class='add'>+		clock-output-names = "v2m:refclk32khz";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	v2m_fixed_3v3: regulator-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mcc {</div><div class='add'>+		compatible = "arm,vexpress,config-bus";</div><div class='add'>+		arm,vexpress,config-bridge = &lt;&amp;v2m_sysreg&gt;;</div><div class='add'>+</div><div class='add'>+		v2m_oscclk1: clock-controller {</div><div class='add'>+			/* CLCD clock */</div><div class='add'>+			compatible = "arm,vexpress-osc";</div><div class='add'>+			arm,vexpress-sysreg,func = &lt;1 1&gt;;</div><div class='add'>+			freq-range = &lt;23750000 63500000&gt;;</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-output-names = "v2m:oscclk1";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		reset {</div><div class='add'>+			compatible = "arm,vexpress-reset";</div><div class='add'>+			arm,vexpress-sysreg,func = &lt;5 0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		muxfpga {</div><div class='add'>+			compatible = "arm,vexpress-muxfpga";</div><div class='add'>+			arm,vexpress-sysreg,func = &lt;7 0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		shutdown {</div><div class='add'>+			compatible = "arm,vexpress-shutdown";</div><div class='add'>+			arm,vexpress-sysreg,func = &lt;8 0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		reboot {</div><div class='add'>+			compatible = "arm,vexpress-reboot";</div><div class='add'>+			arm,vexpress-sysreg,func = &lt;9 0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dvimode {</div><div class='add'>+			compatible = "arm,vexpress-dvimode";</div><div class='add'>+			arm,vexpress-sysreg,func = &lt;11 0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	bus@8000000 {</div><div class='del'>-		motherboard {</div><div class='del'>-			arm,v2m-memory-map = "rs1";</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges = &lt;0 0x8000000 0 0x8000000 0x18000000&gt;;</div><div class='add'>+</div><div class='add'>+		motherboard-bus@8000000 {</div><div class='ctx'> 			compatible = "arm,vexpress,v2m-p1", "simple-bus";</div><div class='ctx'> 			#address-cells = &lt;2&gt;; /* SMB chipselect number and offset */</div><div class='ctx'> 			#size-cells = &lt;1&gt;;</div><div class='del'>-			#interrupt-cells = &lt;1&gt;;</div><div class='del'>-			ranges;</div><div class='add'>+			ranges = &lt;0 0 0 0x08000000 0x04000000&gt;,</div><div class='add'>+				 &lt;1 0 0 0x14000000 0x04000000&gt;,</div><div class='add'>+				 &lt;2 0 0 0x18000000 0x04000000&gt;,</div><div class='add'>+				 &lt;3 0 0 0x1c000000 0x04000000&gt;,</div><div class='add'>+				 &lt;4 0 0 0x0c000000 0x04000000&gt;,</div><div class='add'>+				 &lt;5 0 0 0x10000000 0x04000000&gt;;</div><div class='ctx'> </div><div class='del'>-			flash@0,00000000 {</div><div class='add'>+			flash@0 {</div><div class='ctx'> 				compatible = "arm,vexpress-flash", "cfi-flash";</div><div class='ctx'> 				reg = &lt;0 0x00000000 0x04000000&gt;,</div><div class='ctx'> 				      &lt;4 0x00000000 0x04000000&gt;;</div><div class='ctx'> 				bank-width = &lt;4&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			ethernet@2,02000000 {</div><div class='add'>+			ethernet@202000000 {</div><div class='ctx'> 				compatible = "smsc,lan91c111";</div><div class='ctx'> 				reg = &lt;2 0x02000000 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;15&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			v2m_clk24mhz: clk24mhz {</div><div class='del'>-				compatible = "fixed-clock";</div><div class='del'>-				#clock-cells = &lt;0&gt;;</div><div class='del'>-				clock-frequency = &lt;24000000&gt;;</div><div class='del'>-				clock-output-names = "v2m:clk24mhz";</div><div class='del'>-			};</div><div class='del'>-</div><div class='del'>-			v2m_refclk1mhz: refclk1mhz {</div><div class='del'>-				compatible = "fixed-clock";</div><div class='del'>-				#clock-cells = &lt;0&gt;;</div><div class='del'>-				clock-frequency = &lt;1000000&gt;;</div><div class='del'>-				clock-output-names = "v2m:refclk1mhz";</div><div class='del'>-			};</div><div class='del'>-</div><div class='del'>-			v2m_refclk32khz: refclk32khz {</div><div class='del'>-				compatible = "fixed-clock";</div><div class='del'>-				#clock-cells = &lt;0&gt;;</div><div class='del'>-				clock-frequency = &lt;32768&gt;;</div><div class='del'>-				clock-output-names = "v2m:refclk32khz";</div><div class='del'>-			};</div><div class='del'>-</div><div class='del'>-			iofpga@3,00000000 {</div><div class='add'>+			iofpga-bus@300000000 {</div><div class='ctx'> 				compatible = "simple-bus";</div><div class='ctx'> 				#address-cells = &lt;1&gt;;</div><div class='ctx'> 				#size-cells = &lt;1&gt;;</div><div class='del'>-				ranges = &lt;0 3 0 0x200000&gt;;</div><div class='add'>+				ranges = &lt;0 3 0 0x210000&gt;;</div><div class='ctx'> </div><div class='ctx'> 				v2m_sysreg: sysreg@10000 {</div><div class='ctx'> 					compatible = "arm,vexpress-sysreg";</div><div class='hunk'>@@ -83,7 +138,7 @@</div><div class='ctx'> 					clock-names = "apb_pclk";</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				mmci@50000 {</div><div class='add'>+				mmc@50000 {</div><div class='ctx'> 					compatible = "arm,pl180", "arm,primecell";</div><div class='ctx'> 					reg = &lt;0x050000 0x1000&gt;;</div><div class='ctx'> 					interrupts = &lt;9&gt;, &lt;10&gt;;</div><div class='hunk'>@@ -111,7 +166,7 @@</div><div class='ctx'> 					clock-names = "KMIREFCLK", "apb_pclk";</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				v2m_serial0: uart@90000 {</div><div class='add'>+				v2m_serial0: serial@90000 {</div><div class='ctx'> 					compatible = "arm,pl011", "arm,primecell";</div><div class='ctx'> 					reg = &lt;0x090000 0x1000&gt;;</div><div class='ctx'> 					interrupts = &lt;5&gt;;</div><div class='hunk'>@@ -119,7 +174,7 @@</div><div class='ctx'> 					clock-names = "uartclk", "apb_pclk";</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				v2m_serial1: uart@a0000 {</div><div class='add'>+				v2m_serial1: serial@a0000 {</div><div class='ctx'> 					compatible = "arm,pl011", "arm,primecell";</div><div class='ctx'> 					reg = &lt;0x0a0000 0x1000&gt;;</div><div class='ctx'> 					interrupts = &lt;6&gt;;</div><div class='hunk'>@@ -127,7 +182,7 @@</div><div class='ctx'> 					clock-names = "uartclk", "apb_pclk";</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				v2m_serial2: uart@b0000 {</div><div class='add'>+				v2m_serial2: serial@b0000 {</div><div class='ctx'> 					compatible = "arm,pl011", "arm,primecell";</div><div class='ctx'> 					reg = &lt;0x0b0000 0x1000&gt;;</div><div class='ctx'> 					interrupts = &lt;7&gt;;</div><div class='hunk'>@@ -135,7 +190,7 @@</div><div class='ctx'> 					clock-names = "uartclk", "apb_pclk";</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				v2m_serial3: uart@c0000 {</div><div class='add'>+				v2m_serial3: serial@c0000 {</div><div class='ctx'> 					compatible = "arm,pl011", "arm,primecell";</div><div class='ctx'> 					reg = &lt;0x0c0000 0x1000&gt;;</div><div class='ctx'> 					interrupts = &lt;8&gt;;</div><div class='hunk'>@@ -143,12 +198,12 @@</div><div class='ctx'> 					clock-names = "uartclk", "apb_pclk";</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				wdt@f0000 {</div><div class='add'>+				watchdog@f0000 {</div><div class='ctx'> 					compatible = "arm,sp805", "arm,primecell";</div><div class='ctx'> 					reg = &lt;0x0f0000 0x1000&gt;;</div><div class='ctx'> 					interrupts = &lt;0&gt;;</div><div class='ctx'> 					clocks = &lt;&amp;v2m_refclk32khz&gt;, &lt;&amp;v2m_clk24mhz&gt;;</div><div class='del'>-					clock-names = "wdogclk", "apb_pclk";</div><div class='add'>+					clock-names = "wdog_clk", "apb_pclk";</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='ctx'> 				v2m_timer01: timer@110000 {</div><div class='hunk'>@@ -167,7 +222,7 @@</div><div class='ctx'> 					clock-names = "timclken1", "timclken2", "apb_pclk";</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				virtio-block@130000 {</div><div class='add'>+				virtio@130000 {</div><div class='ctx'> 					compatible = "virtio,mmio";</div><div class='ctx'> 					reg = &lt;0x130000 0x200&gt;;</div><div class='ctx'> 					interrupts = &lt;42&gt;;</div><div class='hunk'>@@ -198,53 +253,6 @@</div><div class='ctx'> 					};</div><div class='ctx'> 				};</div><div class='ctx'> 			};</div><div class='del'>-</div><div class='del'>-			v2m_fixed_3v3: v2m-3v3 {</div><div class='del'>-				compatible = "regulator-fixed";</div><div class='del'>-				regulator-name = "3V3";</div><div class='del'>-				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='del'>-				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='del'>-				regulator-always-on;</div><div class='del'>-			};</div><div class='del'>-</div><div class='del'>-			mcc {</div><div class='del'>-				compatible = "arm,vexpress,config-bus";</div><div class='del'>-				arm,vexpress,config-bridge = &lt;&amp;v2m_sysreg&gt;;</div><div class='del'>-</div><div class='del'>-				v2m_oscclk1: oscclk1 {</div><div class='del'>-					/* CLCD clock */</div><div class='del'>-					compatible = "arm,vexpress-osc";</div><div class='del'>-					arm,vexpress-sysreg,func = &lt;1 1&gt;;</div><div class='del'>-					freq-range = &lt;23750000 63500000&gt;;</div><div class='del'>-					#clock-cells = &lt;0&gt;;</div><div class='del'>-					clock-output-names = "v2m:oscclk1";</div><div class='del'>-				};</div><div class='del'>-</div><div class='del'>-				reset {</div><div class='del'>-					compatible = "arm,vexpress-reset";</div><div class='del'>-					arm,vexpress-sysreg,func = &lt;5 0&gt;;</div><div class='del'>-				};</div><div class='del'>-</div><div class='del'>-				muxfpga {</div><div class='del'>-					compatible = "arm,vexpress-muxfpga";</div><div class='del'>-					arm,vexpress-sysreg,func = &lt;7 0&gt;;</div><div class='del'>-				};</div><div class='del'>-</div><div class='del'>-				shutdown {</div><div class='del'>-					compatible = "arm,vexpress-shutdown";</div><div class='del'>-					arm,vexpress-sysreg,func = &lt;8 0&gt;;</div><div class='del'>-				};</div><div class='del'>-</div><div class='del'>-				reboot {</div><div class='del'>-					compatible = "arm,vexpress-reboot";</div><div class='del'>-					arm,vexpress-sysreg,func = &lt;9 0&gt;;</div><div class='del'>-				};</div><div class='del'>-</div><div class='del'>-				dvimode {</div><div class='del'>-					compatible = "arm,vexpress-dvimode";</div><div class='del'>-					arm,vexpress-sysreg,func = &lt;11 0&gt;;</div><div class='del'>-				};</div><div class='del'>-			};</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts<br/>index d859914500a7..a0e1fa83eafa 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts</a></div><div class='hunk'>@@ -13,7 +13,7 @@</div><div class='ctx'> /dts-v1/;</div><div class='ctx'> </div><div class='ctx'> #include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='del'>-#include "vexpress-v2m-rs1.dtsi"</div><div class='add'>+#include "arm/arm/vexpress-v2m-rs1.dtsi"</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	model = "V2F-1XV7 Cortex-A53x2 SMM";</div><div class='hunk'>@@ -57,6 +57,8 @@</div><div class='ctx'> </div><div class='ctx'> 		L2_0: l2-cache0 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -100,7 +102,7 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	pmu {</div><div class='del'>-		compatible = "arm,armv8-pmuv3";</div><div class='add'>+		compatible = "arm,cortex-a53-pmu";</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 			     &lt;GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 	};</div><div class='hunk'>@@ -109,7 +111,7 @@</div><div class='ctx'> 		compatible = "arm,vexpress,config-bus";</div><div class='ctx'> 		arm,vexpress,config-bridge = &lt;&amp;v2m_sysreg&gt;;</div><div class='ctx'> </div><div class='del'>-		smbclk: smclk {</div><div class='add'>+		smbclk: clock-controller {</div><div class='ctx'> 			/* SMC clock */</div><div class='ctx'> 			compatible = "arm,vexpress-osc";</div><div class='ctx'> 			arm,vexpress-sysreg,func = &lt;1 4&gt;;</div><div class='hunk'>@@ -118,7 +120,7 @@</div><div class='ctx'> 			clock-output-names = "smclk";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		volt-vio {</div><div class='add'>+		regulator-vio {</div><div class='ctx'> 			/* VIO to expansion board above */</div><div class='ctx'> 			compatible = "arm,vexpress-volt";</div><div class='ctx'> 			arm,vexpress-sysreg,func = &lt;2 0&gt;;</div><div class='hunk'>@@ -128,7 +130,7 @@</div><div class='ctx'> 			regulator-always-on;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		volt-12v {</div><div class='add'>+		regulator-12v {</div><div class='ctx'> 			/* 12V from power connector J6 */</div><div class='ctx'> 			compatible = "arm,vexpress-volt";</div><div class='ctx'> 			arm,vexpress-sysreg,func = &lt;2 1&gt;;</div><div class='hunk'>@@ -145,61 +147,6 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	smb: bus@8000000 {</div><div class='del'>-		compatible = "simple-bus";</div><div class='del'>-</div><div class='del'>-		#address-cells = &lt;2&gt;;</div><div class='del'>-		#size-cells = &lt;1&gt;;</div><div class='del'>-		ranges = &lt;0 0 0 0x08000000 0x04000000&gt;,</div><div class='del'>-			 &lt;1 0 0 0x14000000 0x04000000&gt;,</div><div class='del'>-			 &lt;2 0 0 0x18000000 0x04000000&gt;,</div><div class='del'>-			 &lt;3 0 0 0x1c000000 0x04000000&gt;,</div><div class='del'>-			 &lt;4 0 0 0x0c000000 0x04000000&gt;,</div><div class='del'>-			 &lt;5 0 0 0x10000000 0x04000000&gt;;</div><div class='del'>-</div><div class='del'>-		#interrupt-cells = &lt;1&gt;;</div><div class='del'>-		interrupt-map-mask = &lt;0 0 63&gt;;</div><div class='del'>-		interrupt-map = &lt;0 0  0 &amp;gic GIC_SPI  0 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0  1 &amp;gic GIC_SPI  1 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0  2 &amp;gic GIC_SPI  2 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0  3 &amp;gic GIC_SPI  3 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0  4 &amp;gic GIC_SPI  4 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0  5 &amp;gic GIC_SPI  5 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0  6 &amp;gic GIC_SPI  6 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0  7 &amp;gic GIC_SPI  7 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0  8 &amp;gic GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0  9 &amp;gic GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 10 &amp;gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 11 &amp;gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 12 &amp;gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 13 &amp;gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 14 &amp;gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 15 &amp;gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 16 &amp;gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 17 &amp;gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 18 &amp;gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 19 &amp;gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 20 &amp;gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 21 &amp;gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 22 &amp;gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 23 &amp;gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 24 &amp;gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 25 &amp;gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 26 &amp;gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 27 &amp;gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 28 &amp;gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 29 &amp;gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 30 &amp;gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 31 &amp;gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 32 &amp;gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 33 &amp;gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 34 &amp;gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 35 &amp;gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 36 &amp;gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 37 &amp;gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 38 &amp;gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 39 &amp;gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 40 &amp;gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 41 &amp;gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;0 0 42 &amp;gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		ranges = &lt;0x8000000 0 0x8000000 0x18000000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/arm/vexpress-v2m-rs1.dtsi b/arch/arm64/boot/dts/arm/vexpress-v2m-rs1.dtsi<br/>deleted file mode 120000<br/>index 68fd0f8f1dee..000000000000<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/arm/vexpress-v2m-rs1.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/arm/vexpress-v2m-rs1.dtsi</a><br/>+++ /dev/null</div><div class='hunk'>@@ -1 +0,0 @@</div><div class='del'>-../../../../arm/boot/dts/vexpress-v2m-rs1.dtsi
\ No newline at end of file</div><div class='head'>diff --git a/arch/arm64/boot/dts/axiado/Makefile b/arch/arm64/boot/dts/axiado/Makefile<br/>new file mode 100644<br/>index 000000000000..6676ad07db61<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/axiado/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/axiado/Makefile</a></div><div class='hunk'>@@ -0,0 +1,2 @@</div><div class='add'>+# SPDX-License-Identifier: GPL-2.0</div><div class='add'>+dtb-$(CONFIG_ARCH_AXIADO) += ax3000-evk.dtb</div><div class='head'>diff --git a/arch/arm64/boot/dts/axiado/ax3000-evk.dts b/arch/arm64/boot/dts/axiado/ax3000-evk.dts<br/>new file mode 100644<br/>index 000000000000..b86e96962557<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/axiado/ax3000-evk.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/axiado/ax3000-evk.dts</a></div><div class='hunk'>@@ -0,0 +1,82 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2021-25 Axiado Corporation (or its affiliates). All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "ax3000.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Axiado AX3000 EVK";</div><div class='add'>+	compatible = "axiado,ax3000-evk", "axiado,ax3000";</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+		serial1 = &amp;uart1;</div><div class='add'>+		serial2 = &amp;uart2;</div><div class='add'>+		serial3 = &amp;uart3;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial3:115200";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		/* Cortex-A53 will use following memory map */</div><div class='add'>+		reg = &lt;0x00000000 0x3d000000 0x00000000 0x23000000&gt;,</div><div class='add'>+		      &lt;0x00000004 0x00000000 0x00000000 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* GPIO bank 0 - 7 */</div><div class='add'>+&amp;gpio0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio5 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio6 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio7 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/axiado/ax3000.dtsi b/arch/arm64/boot/dts/axiado/ax3000.dtsi<br/>new file mode 100644<br/>index 000000000000..792f52e0c7dd<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/axiado/ax3000.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/axiado/ax3000.dtsi</a></div><div class='hunk'>@@ -0,0 +1,520 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2021-25 Axiado Corporation (or its affiliates). All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+</div><div class='add'>+/memreserve/ 0x3c0013a0 0x00000008;	/* cpu-release-addr */</div><div class='add'>+/ {</div><div class='add'>+	model = "Axiado AX3000";</div><div class='add'>+	interrupt-parent = &lt;&amp;gic500&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x0 0x0&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0x0 0x3c0013a0&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@1 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x0 0x1&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0x0 0x3c0013a0&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@2 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x0 0x2&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0x0 0x3c0013a0&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@3 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x0 0x3&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0x0 0x3c0013a0&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2: l2-cache0 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-size = &lt;0x100000&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;1024&gt;;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clocks {</div><div class='add'>+		clk_xin: clock-200000000 {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-frequency = &lt;200000000&gt;;</div><div class='add'>+			clock-output-names = "clk_xin";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		refclk: clock-125000000 {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-frequency = &lt;125000000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		ranges;</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic500&gt;;</div><div class='add'>+</div><div class='add'>+		gic500: interrupt-controller@80300000 {</div><div class='add'>+			compatible = "arm,gic-v3";</div><div class='add'>+			reg = &lt;0x00 0x80300000 0x00 0x10000&gt;,</div><div class='add'>+			      &lt;0x00 0x80380000 0x00 0x80000&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#redistributor-regions = &lt;1&gt;;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* GPIO Controller banks 0 - 7 */</div><div class='add'>+		gpio0: gpio-controller@80500000 {</div><div class='add'>+			compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";</div><div class='add'>+			reg = &lt;0x00 0x80500000 0x00 0x400&gt;;</div><div class='add'>+			clocks = &lt;&amp;refclk&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gic500&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpio1: gpio-controller@80580000 {</div><div class='add'>+			compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";</div><div class='add'>+			reg = &lt;0x00 0x80580000 0x00 0x400&gt;;</div><div class='add'>+			clocks = &lt;&amp;refclk&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gic500&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpio2: gpio-controller@80600000 {</div><div class='add'>+			compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";</div><div class='add'>+			reg = &lt;0x00 0x80600000 0x00 0x400&gt;;</div><div class='add'>+			clocks = &lt;&amp;refclk&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gic500&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpio3: gpio-controller@80680000 {</div><div class='add'>+			compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";</div><div class='add'>+			reg = &lt;0x00 0x80680000 0x00 0x400&gt;;</div><div class='add'>+			clocks = &lt;&amp;refclk&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gic500&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpio4: gpio-controller@80700000 {</div><div class='add'>+			compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";</div><div class='add'>+			reg = &lt;0x00 0x80700000 0x00 0x400&gt;;</div><div class='add'>+			clocks = &lt;&amp;refclk&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gic500&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpio5: gpio-controller@80780000 {</div><div class='add'>+			compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";</div><div class='add'>+			reg = &lt;0x00 0x80780000 0x00 0x400&gt;;</div><div class='add'>+			clocks = &lt;&amp;refclk&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gic500&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpio6: gpio-controller@80800000 {</div><div class='add'>+			compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";</div><div class='add'>+			reg = &lt;0x00 0x80800000 0x00 0x400&gt;;</div><div class='add'>+			clocks = &lt;&amp;refclk&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gic500&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpio7: gpio-controller@80880000 {</div><div class='add'>+			compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";</div><div class='add'>+			reg = &lt;0x00 0x80880000 0x00 0x400&gt;;</div><div class='add'>+			clocks = &lt;&amp;refclk&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gic500&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* I3C Controller 0 - 16 */</div><div class='add'>+		i3c0: i3c@80500400 {</div><div class='add'>+			compatible = "axiado,ax3000-i3c", "cdns,i3c-master";</div><div class='add'>+			reg = &lt;0x00 0x80500400 0x00 0x400&gt;;</div><div class='add'>+			clocks = &lt;&amp;refclk &amp;clk_xin&gt;;</div><div class='add'>+			clock-names = "pclk", "sysclk";</div><div class='add'>+			interrupt-parent = &lt;&amp;gic500&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			i2c-scl-hz = &lt;100000&gt;;</div><div class='add'>+			i3c-scl-hz = &lt;400000&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i3c1: i3c@80500800 {</div><div class='add'>+			compatible = "axiado,ax3000-i3c", "cdns,i3c-master";</div><div class='add'>+			reg = &lt;0x00 0x80500800 0x00 0x400&gt;;</div><div class='add'>+			clocks = &lt;&amp;refclk &amp;clk_xin&gt;;</div><div class='add'>+			clock-names = "pclk", "sysclk";</div><div class='add'>+			interrupt-parent = &lt;&amp;gic500&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			i2c-scl-hz = &lt;100000&gt;;</div><div class='add'>+			i3c-scl-hz = &lt;400000&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i3c2: i3c@80580400 {</div><div class='add'>+			compatible = "axiado,ax3000-i3c", "cdns,i3c-master";</div><div class='add'>+			reg = &lt;0x00 0x80580400 0x00 0x400&gt;;</div><div class='add'>+			clocks = &lt;&amp;refclk &amp;clk_xin&gt;;</div><div class='add'>+			clock-names = "pclk", "sysclk";</div><div class='add'>+			interrupt-parent = &lt;&amp;gic500&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			i2c-scl-hz = &lt;100000&gt;;</div><div class='add'>+			i3c-scl-hz = &lt;400000&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i3c3: i3c@80580800 {</div><div class='add'>+			compatible = "axiado,ax3000-i3c", "cdns,i3c-master";</div><div class='add'>+			reg = &lt;0x00 0x80580800 0x00 0x400&gt;;</div><div class='add'>+			clocks = &lt;&amp;refclk &amp;clk_xin&gt;;</div><div class='add'>+			clock-names = "pclk", "sysclk";</div><div class='add'>+			interrupt-parent = &lt;&amp;gic500&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			i2c-scl-hz = &lt;100000&gt;;</div><div class='add'>+			i3c-scl-hz = &lt;400000&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i3c4: i3c@80600400 {</div><div class='add'>+			compatible = "axiado,ax3000-i3c", "cdns,i3c-master";</div><div class='add'>+			reg = &lt;0x00 0x80600400 0x00 0x400&gt;;</div><div class='add'>+			clocks = &lt;&amp;refclk &amp;clk_xin&gt;;</div><div class='add'>+			clock-names = "pclk", "sysclk";</div><div class='add'>+			interrupt-parent = &lt;&amp;gic500&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			i2c-scl-hz = &lt;100000&gt;;</div><div class='add'>+			i3c-scl-hz = &lt;400000&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i3c5: i3c@80600800 {</div><div class='add'>+			compatible = "axiado,ax3000-i3c", "cdns,i3c-master";</div><div class='add'>+			reg = &lt;0x00 0x80600800 0x00 0x400&gt;;</div><div class='add'>+			clocks = &lt;&amp;refclk &amp;clk_xin&gt;;</div><div class='add'>+			clock-names = "pclk", "sysclk";</div><div class='add'>+			interrupt-parent = &lt;&amp;gic500&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			i2c-scl-hz = &lt;100000&gt;;</div><div class='add'>+			i3c-scl-hz = &lt;400000&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i3c6: i3c@80680400 {</div><div class='add'>+			compatible = "axiado,ax3000-i3c", "cdns,i3c-master";</div><div class='add'>+			reg = &lt;0x00 0x80680400 0x00 0x400&gt;;</div><div class='add'>+			clocks = &lt;&amp;refclk &amp;clk_xin&gt;;</div><div class='add'>+			clock-names = "pclk", "sysclk";</div><div class='add'>+			interrupt-parent = &lt;&amp;gic500&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			i2c-scl-hz = &lt;100000&gt;;</div><div class='add'>+			i3c-scl-hz = &lt;400000&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i3c7: i3c@80680800 {</div><div class='add'>+			compatible = "axiado,ax3000-i3c", "cdns,i3c-master";</div><div class='add'>+			reg = &lt;0x00 0x80680800 0x00 0x400&gt;;</div><div class='add'>+			clocks = &lt;&amp;refclk &amp;clk_xin&gt;;</div><div class='add'>+			clock-names = "pclk", "sysclk";</div><div class='add'>+			interrupt-parent = &lt;&amp;gic500&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			i2c-scl-hz = &lt;100000&gt;;</div><div class='add'>+			i3c-scl-hz = &lt;400000&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i3c8: i3c@80700400 {</div><div class='add'>+			compatible = "axiado,ax3000-i3c", "cdns,i3c-master";</div><div class='add'>+			reg = &lt;0x00 0x80700400 0x00 0x400&gt;;</div><div class='add'>+			clocks = &lt;&amp;refclk &amp;clk_xin&gt;;</div><div class='add'>+			clock-names = "pclk", "sysclk";</div><div class='add'>+			interrupt-parent = &lt;&amp;gic500&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			i2c-scl-hz = &lt;100000&gt;;</div><div class='add'>+			i3c-scl-hz = &lt;400000&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i3c9: i3c@80700800 {</div><div class='add'>+			compatible = "axiado,ax3000-i3c", "cdns,i3c-master";</div><div class='add'>+			reg = &lt;0x00 0x80700800 0x00 0x400&gt;;</div><div class='add'>+			clocks = &lt;&amp;refclk &amp;clk_xin&gt;;</div><div class='add'>+			clock-names = "pclk", "sysclk";</div><div class='add'>+			interrupt-parent = &lt;&amp;gic500&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			i2c-scl-hz = &lt;100000&gt;;</div><div class='add'>+			i3c-scl-hz = &lt;400000&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i3c10: i3c@80780400 {</div><div class='add'>+			compatible = "axiado,ax3000-i3c", "cdns,i3c-master";</div><div class='add'>+			reg = &lt;0x00 0x80780400 0x00 0x400&gt;;</div><div class='add'>+			clocks = &lt;&amp;refclk &amp;clk_xin&gt;;</div><div class='add'>+			clock-names = "pclk", "sysclk";</div><div class='add'>+			interrupt-parent = &lt;&amp;gic500&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			i2c-scl-hz = &lt;100000&gt;;</div><div class='add'>+			i3c-scl-hz = &lt;400000&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i3c11: i3c@80780800 {</div><div class='add'>+			compatible = "axiado,ax3000-i3c", "cdns,i3c-master";</div><div class='add'>+			reg = &lt;0x00 0x80780800 0x00 0x400&gt;;</div><div class='add'>+			clocks = &lt;&amp;refclk &amp;clk_xin&gt;;</div><div class='add'>+			clock-names = "pclk", "sysclk";</div><div class='add'>+			interrupt-parent = &lt;&amp;gic500&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			i2c-scl-hz = &lt;100000&gt;;</div><div class='add'>+			i3c-scl-hz = &lt;400000&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i3c12: i3c@80800400 {</div><div class='add'>+			compatible = "axiado,ax3000-i3c", "cdns,i3c-master";</div><div class='add'>+			reg = &lt;0x00 0x80800400 0x00 0x400&gt;;</div><div class='add'>+			clocks = &lt;&amp;refclk &amp;clk_xin&gt;;</div><div class='add'>+			clock-names = "pclk", "sysclk";</div><div class='add'>+			interrupt-parent = &lt;&amp;gic500&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			i2c-scl-hz = &lt;100000&gt;;</div><div class='add'>+			i3c-scl-hz = &lt;400000&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i3c13: i3c@80800800 {</div><div class='add'>+			compatible = "axiado,ax3000-i3c", "cdns,i3c-master";</div><div class='add'>+			reg = &lt;0x00 0x80800800 0x00 0x400&gt;;</div><div class='add'>+			clocks = &lt;&amp;refclk &amp;clk_xin&gt;;</div><div class='add'>+			clock-names = "pclk", "sysclk";</div><div class='add'>+			interrupt-parent = &lt;&amp;gic500&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			i2c-scl-hz = &lt;100000&gt;;</div><div class='add'>+			i3c-scl-hz = &lt;400000&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i3c14: i3c@80880400 {</div><div class='add'>+			compatible = "axiado,ax3000-i3c", "cdns,i3c-master";</div><div class='add'>+			reg = &lt;0x00 0x80880400 0x00 0x400&gt;;</div><div class='add'>+			clocks = &lt;&amp;refclk &amp;clk_xin&gt;;</div><div class='add'>+			clock-names = "pclk", "sysclk";</div><div class='add'>+			interrupt-parent = &lt;&amp;gic500&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			i2c-scl-hz = &lt;100000&gt;;</div><div class='add'>+			i3c-scl-hz = &lt;400000&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i3c15: i3c@80880800 {</div><div class='add'>+			compatible = "axiado,ax3000-i3c", "cdns,i3c-master";</div><div class='add'>+			reg = &lt;0x00 0x80880800 0x00 0x400&gt;;</div><div class='add'>+			clocks = &lt;&amp;refclk &amp;clk_xin&gt;;</div><div class='add'>+			clock-names = "pclk", "sysclk";</div><div class='add'>+			interrupt-parent = &lt;&amp;gic500&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			i2c-scl-hz = &lt;100000&gt;;</div><div class='add'>+			i3c-scl-hz = &lt;400000&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i3c16: i3c@80620400 {</div><div class='add'>+			compatible = "axiado,ax3000-i3c", "cdns,i3c-master";</div><div class='add'>+			reg = &lt;0x00 0x80620400 0x00 0x400&gt;;</div><div class='add'>+			clocks = &lt;&amp;refclk &amp;clk_xin&gt;;</div><div class='add'>+			clock-names = "pclk", "sysclk";</div><div class='add'>+			interrupt-parent = &lt;&amp;gic500&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			i2c-scl-hz = &lt;100000&gt;;</div><div class='add'>+			i3c-scl-hz = &lt;400000&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart0: serial@80520000 {</div><div class='add'>+			compatible = "axiado,ax3000-uart", "cdns,uart-r1p12";</div><div class='add'>+			reg = &lt;0x00 0x80520000 0x00 0x100&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gic500&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clock-names = "uart_clk", "pclk";</div><div class='add'>+			clocks = &lt;&amp;refclk &amp;refclk&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart1: serial@805a0000 {</div><div class='add'>+			compatible = "axiado,ax3000-uart", "cdns,uart-r1p12";</div><div class='add'>+			reg = &lt;0x00 0x805A0000 0x00 0x100&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gic500&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clock-names = "uart_clk", "pclk";</div><div class='add'>+			clocks = &lt;&amp;refclk &amp;refclk&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart2: serial@80620000 {</div><div class='add'>+			compatible = "axiado,ax3000-uart", "cdns,uart-r1p12";</div><div class='add'>+			reg = &lt;0x00 0x80620000 0x00 0x100&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gic500&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clock-names = "uart_clk", "pclk";</div><div class='add'>+			clocks = &lt;&amp;refclk &amp;refclk&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart3: serial@80520800 {</div><div class='add'>+			compatible = "axiado,ax3000-uart", "cdns,uart-r1p12";</div><div class='add'>+			reg = &lt;0x00 0x80520800 0x00 0x100&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gic500&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clock-names = "uart_clk", "pclk";</div><div class='add'>+			clocks = &lt;&amp;refclk &amp;refclk&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupt-parent = &lt;&amp;gic500&gt;;</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			   &lt;GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			   &lt;GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			   &lt;GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/bitmain/bm1880.dtsi b/arch/arm64/boot/dts/bitmain/bm1880.dtsi<br/>index fa6e6905f588..22a200fb07d2 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/bitmain/bm1880.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/bitmain/bm1880.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/bitmain/bm1880.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/bitmain/bm1880.dtsi</a></div><div class='hunk'>@@ -127,7 +127,7 @@</div><div class='ctx'> 				compatible = "snps,dw-apb-gpio-port";</div><div class='ctx'> 				gpio-controller;</div><div class='ctx'> 				#gpio-cells = &lt;2&gt;;</div><div class='del'>-				snps,nr-gpios = &lt;32&gt;;</div><div class='add'>+				ngpios = &lt;32&gt;;</div><div class='ctx'> 				reg = &lt;0&gt;;</div><div class='ctx'> 				interrupt-controller;</div><div class='ctx'> 				#interrupt-cells = &lt;2&gt;;</div><div class='hunk'>@@ -145,7 +145,7 @@</div><div class='ctx'> 				compatible = "snps,dw-apb-gpio-port";</div><div class='ctx'> 				gpio-controller;</div><div class='ctx'> 				#gpio-cells = &lt;2&gt;;</div><div class='del'>-				snps,nr-gpios = &lt;32&gt;;</div><div class='add'>+				ngpios = &lt;32&gt;;</div><div class='ctx'> 				reg = &lt;0&gt;;</div><div class='ctx'> 				interrupt-controller;</div><div class='ctx'> 				#interrupt-cells = &lt;2&gt;;</div><div class='hunk'>@@ -163,7 +163,7 @@</div><div class='ctx'> 				compatible = "snps,dw-apb-gpio-port";</div><div class='ctx'> 				gpio-controller;</div><div class='ctx'> 				#gpio-cells = &lt;2&gt;;</div><div class='del'>-				snps,nr-gpios = &lt;8&gt;;</div><div class='add'>+				ngpios = &lt;8&gt;;</div><div class='ctx'> 				reg = &lt;0&gt;;</div><div class='ctx'> 				interrupt-controller;</div><div class='ctx'> 				#interrupt-cells = &lt;2&gt;;</div><div class='hunk'>@@ -184,7 +184,7 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		uart1: serial@5801A000 {</div><div class='add'>+		uart1: serial@5801a000 {</div><div class='ctx'> 			compatible = "snps,dw-apb-uart";</div><div class='ctx'> 			reg = &lt;0x0 0x5801a000 0x0 0x2000&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;clk BM1880_CLK_UART_500M&gt;,</div><div class='hunk'>@@ -197,7 +197,7 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		uart2: serial@5801C000 {</div><div class='add'>+		uart2: serial@5801c000 {</div><div class='ctx'> 			compatible = "snps,dw-apb-uart";</div><div class='ctx'> 			reg = &lt;0x0 0x5801c000 0x0 0x2000&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;clk BM1880_CLK_UART_500M&gt;,</div><div class='hunk'>@@ -210,7 +210,7 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		uart3: serial@5801E000 {</div><div class='add'>+		uart3: serial@5801e000 {</div><div class='ctx'> 			compatible = "snps,dw-apb-uart";</div><div class='ctx'> 			reg = &lt;0x0 0x5801e000 0x0 0x2000&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;clk BM1880_CLK_UART_500M&gt;,</div><div class='head'>diff --git a/arch/arm64/boot/dts/blaize/Makefile b/arch/arm64/boot/dts/blaize/Makefile<br/>new file mode 100644<br/>index 000000000000..7e10b3199e6c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/blaize/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/blaize/Makefile</a></div><div class='hunk'>@@ -0,0 +1,2 @@</div><div class='add'>+# SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+dtb-$(CONFIG_ARCH_BLAIZE) += blaize-blzp1600-cb2.dtb</div><div class='head'>diff --git a/arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts b/arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts<br/>new file mode 100644<br/>index 000000000000..fb5415eb347a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts</a></div><div class='hunk'>@@ -0,0 +1,119 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2024 Blaize, Inc. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "blaize-blzp1600-som.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Blaize BLZP1600 SoM1600P CB2 Development Board";</div><div class='add'>+</div><div class='add'>+	compatible = "blaize,blzp1600-cb2", "blaize,blzp1600";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	gpio_expander: gpio@74 {</div><div class='add'>+		compatible = "ti,tca9539";</div><div class='add'>+		reg = &lt;0x74&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-line-names = "RSP_PIN_7",	/* GPIO_0 */</div><div class='add'>+				  "RSP_PIN_11",	/* GPIO_1 */</div><div class='add'>+				  "RSP_PIN_13",	/* GPIO_2 */</div><div class='add'>+				  "RSP_PIN_15",	/* GPIO_3 */</div><div class='add'>+				  "RSP_PIN_27",	/* GPIO_4 */</div><div class='add'>+				  "RSP_PIN_29",	/* GPIO_5 */</div><div class='add'>+				  "RSP_PIN_31",	/* GPIO_6 */</div><div class='add'>+				  "RSP_PIN_33",	/* GPIO_7 */</div><div class='add'>+				  "RSP_PIN_37",	/* GPIO_8 */</div><div class='add'>+				  "RSP_PIN_16",	/* GPIO_9 */</div><div class='add'>+				  "RSP_PIN_18",	/* GPIO_10 */</div><div class='add'>+				  "RSP_PIN_22",	/* GPIO_11 */</div><div class='add'>+				  "RSP_PIN_28",	/* GPIO_12 */</div><div class='add'>+				  "RSP_PIN_32",	/* GPIO_13 */</div><div class='add'>+				  "RSP_PIN_36",	/* GPIO_14 */</div><div class='add'>+				  "TP31";	/* GPIO_15 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio_expander_m2: gpio@75 {</div><div class='add'>+		compatible = "ti,tca9539";</div><div class='add'>+		reg = &lt;0x75&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-line-names = "M2_W_DIS1_N",	/* GPIO_0 */</div><div class='add'>+				  "M2_W_DIS2_N",	/* GPIO_1 */</div><div class='add'>+				  "M2_UART_WAKE_N",	/* GPIO_2 */</div><div class='add'>+				  "M2_COEX3",		/* GPIO_3 */</div><div class='add'>+				  "M2_COEX_RXD",	/* GPIO_4 */</div><div class='add'>+				  "M2_COEX_TXD",	/* GPIO_5 */</div><div class='add'>+				  "M2_VENDOR_PIN40",	/* GPIO_6 */</div><div class='add'>+				  "M2_VENDOR_PIN42",	/* GPIO_7 */</div><div class='add'>+				  "M2_VENDOR_PIN38",	/* GPIO_8 */</div><div class='add'>+				  "M2_SDIO_RST_N",	/* GPIO_9 */</div><div class='add'>+				  "M2_SDIO_WAKE_N",	/* GPIO_10 */</div><div class='add'>+				  "M2_PETN1",		/* GPIO_11 */</div><div class='add'>+				  "M2_PERP1",		/* GPIO_12 */</div><div class='add'>+				  "M2_PERN1",		/* GPIO_13 */</div><div class='add'>+				  "UIM_SWP",		/* GPIO_14 */</div><div class='add'>+				  "UART1_TO_RSP";	/* GPIO_15 */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	gpio-line-names = "PERST_N",		/* GPIO_0 */</div><div class='add'>+			  "LM96063_ALERT_N",	/* GPIO_1 */</div><div class='add'>+			  "INA3221_PV",		/* GPIO_2 */</div><div class='add'>+			  "INA3221_CRIT",	/* GPIO_3 */</div><div class='add'>+			  "INA3221_WARN",	/* GPIO_4 */</div><div class='add'>+			  "INA3221_TC",		/* GPIO_5 */</div><div class='add'>+			  "QSPI0_RST_N",	/* GPIO_6 */</div><div class='add'>+			  "LM96063_TCRIT_N",	/* GPIO_7 */</div><div class='add'>+			  "DSI_TCH_INT",	/* GPIO_8 */</div><div class='add'>+			  "DSI_RST",		/* GPIO_9 */</div><div class='add'>+			  "DSI_BL",		/* GPIO_10 */</div><div class='add'>+			  "DSI_INT",		/* GPIO_11 */</div><div class='add'>+			  "ETH_RST",		/* GPIO_12 */</div><div class='add'>+			  "CSI0_RST",		/* GPIO_13 */</div><div class='add'>+			  "CSI0_PWDN",		/* GPIO_14 */</div><div class='add'>+			  "CSI1_RST",		/* GPIO_15 */</div><div class='add'>+			  "CSI1_PWDN",		/* GPIO_16 */</div><div class='add'>+			  "CSI2_RST",		/* GPIO_17 */</div><div class='add'>+			  "CSI2_PWDN",		/* GPIO_18 */</div><div class='add'>+			  "CSI3_RST",		/* GPIO_19 */</div><div class='add'>+			  "CSI3_PWDN",		/* GPIO_20 */</div><div class='add'>+			  "ADAC_RST",		/* GPIO_21 */</div><div class='add'>+			  "SD_SW_VDD",		/* GPIO_22 */</div><div class='add'>+			  "SD_PON_VDD",		/* GPIO_23 */</div><div class='add'>+			  "GPIO_EXP_INT",	/* GPIO_24 */</div><div class='add'>+			  "BOARD_ID_0",		/* GPIO_25 */</div><div class='add'>+			  "SDIO1_SW_VDD",	/* GPIO_26 */</div><div class='add'>+			  "SDIO1_PON_VDD",	/* GPIO_27 */</div><div class='add'>+			  "SDIO2_SW_VDD",	/* GPIO_28 */</div><div class='add'>+			  "SDIO2_PON_VDD",	/* GPIO_29 */</div><div class='add'>+			  "BOARD_ID_1",		/* GPIO_30 */</div><div class='add'>+			  "BOARD_ID_2";		/* GPIO_31 */</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi b/arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi<br/>new file mode 100644<br/>index 000000000000..bfdff5953edd<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi</a></div><div class='hunk'>@@ -0,0 +1,23 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2024 Blaize, Inc. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "blaize-blzp1600.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x0 0x1 0x0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* i2c4 bus is available only on the SoM, not on the board */</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi b/arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi<br/>new file mode 100644<br/>index 000000000000..5a6c882b2f57<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi</a></div><div class='hunk'>@@ -0,0 +1,217 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2024 Blaize, Inc. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x0 0x0&gt;;</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@1 {</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x0 0x1&gt;;</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2: l2-cache0 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	firmware {</div><div class='add'>+		scmi {</div><div class='add'>+			compatible = "arm,scmi-smc";</div><div class='add'>+			arm,smc-id = &lt;0x82002000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			shmem = &lt;&amp;scmi0_shm&gt;;</div><div class='add'>+</div><div class='add'>+			scmi_clk: protocol@14 {</div><div class='add'>+				reg = &lt;0x14&gt;;</div><div class='add'>+				#clock-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			scmi_rst: protocol@16 {</div><div class='add'>+				reg = &lt;0x16&gt;;</div><div class='add'>+				#reset-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu {</div><div class='add'>+		compatible = "arm,cortex-a53-pmu";</div><div class='add'>+		interrupts = &lt;GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-affinity = &lt;&amp;cpu0&gt;, &lt;&amp;cpu1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-1.0", "arm,psci-0.2";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		/* SCMI reserved buffer space on DDR space */</div><div class='add'>+		scmi0_shm: scmi-shmem@800 {</div><div class='add'>+			compatible = "arm,scmi-shmem";</div><div class='add'>+			reg = &lt;0x0 0x800 0x0 0x80&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = /* Physical Secure PPI */</div><div class='add'>+			     &lt;GIC_PPI 13 (GIC_CPU_MASK_RAW(0x3) |</div><div class='add'>+					  IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     /* Physical Non-Secure PPI */</div><div class='add'>+			     &lt;GIC_PPI 14 (GIC_CPU_MASK_RAW(0x3) |</div><div class='add'>+					  IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     /* Hypervisor PPI */</div><div class='add'>+			     &lt;GIC_PPI 10 (GIC_CPU_MASK_RAW(0x3) |</div><div class='add'>+					  IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     /* Virtual PPI */</div><div class='add'>+			     &lt;GIC_PPI 11 (GIC_CPU_MASK_RAW(0x3) |</div><div class='add'>+					  IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc@200000000 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges = &lt;0x0 0x2 0x0 0x850000&gt;;</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@410000 {</div><div class='add'>+			compatible = "arm,gic-400";</div><div class='add'>+			reg = &lt;0x410000 0x20000&gt;,</div><div class='add'>+			      &lt;0x420000 0x20000&gt;,</div><div class='add'>+			      &lt;0x440000 0x20000&gt;,</div><div class='add'>+			      &lt;0x460000 0x20000&gt;;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			#address-cells = &lt;0&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 (GIC_CPU_MASK_RAW(0x3) |</div><div class='add'>+						 IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpio0: gpio@4c0000 {</div><div class='add'>+			compatible = "blaize,blzp1600-gpio";</div><div class='add'>+			reg = &lt;0x4c0000 0x1000&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			ngpios = &lt;32&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart0: serial@4d0000 {</div><div class='add'>+			compatible = "ns16550a";</div><div class='add'>+			reg = &lt;0x4d0000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_clk 59&gt;;</div><div class='add'>+			resets = &lt;&amp;scmi_rst 59&gt;;</div><div class='add'>+			reg-shift = &lt;2&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart1: serial@4e0000 {</div><div class='add'>+			compatible = "ns16550a";</div><div class='add'>+			reg = &lt;0x4e0000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_clk 60&gt;;</div><div class='add'>+			resets = &lt;&amp;scmi_rst 60&gt;;</div><div class='add'>+			reg-shift = &lt;2&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c0: i2c@4f0000 {</div><div class='add'>+			compatible = "snps,designware-i2c";</div><div class='add'>+			reg = &lt;0x4f0000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_clk 54&gt;;</div><div class='add'>+			resets = &lt;&amp;scmi_rst 54&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c1: i2c@500000 {</div><div class='add'>+			compatible = "snps,designware-i2c";</div><div class='add'>+			reg = &lt;0x500000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_clk 55&gt;;</div><div class='add'>+			resets = &lt;&amp;scmi_rst 55&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c2: i2c@510000 {</div><div class='add'>+			compatible = "snps,designware-i2c";</div><div class='add'>+			reg = &lt;0x510000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_clk 56&gt;;</div><div class='add'>+			resets = &lt;&amp;scmi_rst 56&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c3: i2c@520000 {</div><div class='add'>+			compatible = "snps,designware-i2c";</div><div class='add'>+			reg = &lt;0x520000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_clk 57&gt;;</div><div class='add'>+			resets = &lt;&amp;scmi_rst 57&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c4: i2c@530000 {</div><div class='add'>+			compatible = "snps,designware-i2c";</div><div class='add'>+			reg = &lt;0x530000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_clk 58&gt;;</div><div class='add'>+			resets = &lt;&amp;scmi_rst 58&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		arm_cc712: crypto@550000 {</div><div class='add'>+			compatible = "arm,cryptocell-712-ree";</div><div class='add'>+			reg = &lt;0x550000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_clk 7&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile<br/>index cb7de8d99223..83d45afc6588 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/Makefile?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/Makefile</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/Makefile</a></div><div class='hunk'>@@ -1,9 +1,22 @@</div><div class='ctx'> # SPDX-License-Identifier: GPL-2.0</div><div class='del'>-dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-4-b.dtb \</div><div class='add'>+</div><div class='add'>+# Enables support for device-tree overlays</div><div class='add'>+DTC_FLAGS := -@</div><div class='add'>+</div><div class='add'>+dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-400.dtb \</div><div class='add'>+			      bcm2711-rpi-4-b.dtb \</div><div class='add'>+			      bcm2711-rpi-cm4-io.dtb \</div><div class='add'>+			      bcm2712-rpi-5-b.dtb \</div><div class='add'>+			      bcm2712-rpi-5-b-ovl-rp1.dtb \</div><div class='add'>+			      bcm2712-d-rpi-5-b.dtb \</div><div class='add'>+			      bcm2837-rpi-2-b.dtb \</div><div class='ctx'> 			      bcm2837-rpi-3-a-plus.dtb \</div><div class='ctx'> 			      bcm2837-rpi-3-b.dtb \</div><div class='ctx'> 			      bcm2837-rpi-3-b-plus.dtb \</div><div class='del'>-			      bcm2837-rpi-cm3-io3.dtb</div><div class='add'>+			      bcm2837-rpi-cm3-io3.dtb \</div><div class='add'>+			      bcm2837-rpi-zero-2-w.dtb \</div><div class='add'>+			      rp1.dtbo</div><div class='ctx'> </div><div class='add'>+subdir-y	+= bcmbca</div><div class='ctx'> subdir-y	+= northstar2</div><div class='ctx'> subdir-y	+= stingray</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts<br/>index d24c53682e44..c7280bdefa8d 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts</a></div><div class='hunk'>@@ -1,2 +1,2 @@</div><div class='ctx'> // SPDX-License-Identifier: GPL-2.0</div><div class='del'>-#include "arm/bcm2711-rpi-4-b.dts"</div><div class='add'>+#include "arm/broadcom/bcm2711-rpi-4-b.dts"</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dts b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dts<br/>new file mode 100644<br/>index 000000000000..d9d2852b794f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dts</a></div><div class='hunk'>@@ -0,0 +1,2 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+#include "arm/broadcom/bcm2711-rpi-400.dts"</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/bcm2711-rpi-cm4-io.dts b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-cm4-io.dts<br/>new file mode 100644<br/>index 000000000000..8810322aa66a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/bcm2711-rpi-cm4-io.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/bcm2711-rpi-cm4-io.dts</a></div><div class='hunk'>@@ -0,0 +1,2 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+#include "arm/broadcom/bcm2711-rpi-cm4-io.dts"</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-d-rpi-5-b.dts b/arch/arm64/boot/dts/broadcom/bcm2712-d-rpi-5-b.dts<br/>new file mode 100644<br/>index 000000000000..7de24d60bcd1<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/bcm2712-d-rpi-5-b.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/bcm2712-d-rpi-5-b.dts</a></div><div class='hunk'>@@ -0,0 +1,37 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "bcm2712-rpi-5-b.dts"</div><div class='add'>+</div><div class='add'>+&amp;gio_aon {</div><div class='add'>+	brcm,gpio-bank-widths = &lt;15 6&gt;;</div><div class='add'>+</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"RP1_SDA", // AON_GPIO_00</div><div class='add'>+		"RP1_SCL", // AON_GPIO_01</div><div class='add'>+		"RP1_RUN", // AON_GPIO_02</div><div class='add'>+		"SD_IOVDD_SEL", // AON_GPIO_03</div><div class='add'>+		"SD_PWR_ON", // AON_GPIO_04</div><div class='add'>+		"SD_CDET_N", // AON_GPIO_05</div><div class='add'>+		"SD_FLG_N", // AON_GPIO_06</div><div class='add'>+		"", // AON_GPIO_07</div><div class='add'>+		"2712_WAKE", // AON_GPIO_08</div><div class='add'>+		"2712_STAT_LED", // AON_GPIO_09</div><div class='add'>+		"", // AON_GPIO_10</div><div class='add'>+		"", // AON_GPIO_11</div><div class='add'>+		"PMIC_INT", // AON_GPIO_12</div><div class='add'>+		"UART_TX_FS", // AON_GPIO_13</div><div class='add'>+		"UART_RX_FS", // AON_GPIO_14</div><div class='add'>+		"", // AON_GPIO_15</div><div class='add'>+		"", // AON_GPIO_16</div><div class='add'>+</div><div class='add'>+		// Pad bank0 out to 32 entries</div><div class='add'>+		"", "", "", "", "", "", "", "", "", "", "", "", "", "", "",</div><div class='add'>+</div><div class='add'>+		"HDMI0_SCL", // AON_SGPIO_00</div><div class='add'>+		"HDMI0_SDA", // AON_SGPIO_01</div><div class='add'>+		"HDMI1_SCL", // AON_SGPIO_02</div><div class='add'>+		"HDMI1_SDA", // AON_SGPIO_03</div><div class='add'>+		"PMIC_SCL", // AON_SGPIO_04</div><div class='add'>+		"PMIC_SDA"; // AON_SGPIO_05</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-ovl-rp1.dts b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-ovl-rp1.dts<br/>new file mode 100644<br/>index 000000000000..04738bf281eb<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-ovl-rp1.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-ovl-rp1.dts</a></div><div class='hunk'>@@ -0,0 +1,254 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include "bcm2712.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "raspberrypi,5-model-b", "brcm,bcm2712";</div><div class='add'>+	model = "Raspberry Pi 5";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial10 = &amp;uart10;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen: chosen {</div><div class='add'>+		stdout-path = "serial10:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_rp1_xosc: clock-50000000 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-output-names = "rp1-xosc";</div><div class='add'>+		clock-frequency = &lt;50000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Will be filled by the bootloader */</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0 0 0 0x28000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pwr_button_default&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+</div><div class='add'>+		power_button: power-button {</div><div class='add'>+			label = "pwr_button";</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+			gpios = &lt;&amp;gio 20 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			debounce-interval = &lt;50&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd_io_1v8_reg: sd-io-1v8-reg {</div><div class='add'>+		compatible = "regulator-gpio";</div><div class='add'>+		regulator-name = "vdd-sd-io";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-settling-time-us = &lt;5000&gt;;</div><div class='add'>+		gpios = &lt;&amp;gio_aon 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		states = &lt;1800000 1&gt;,</div><div class='add'>+			 &lt;3300000 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd_vcc_reg: sd-vcc-reg {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vcc-sd";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpios = &lt;&amp;gio_aon 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wl_on_reg: wl-on-reg {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "wl-on-regulator";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;wl_on_default&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		gpio = &lt;&amp;gio 28 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		startup-delay-us = &lt;150000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl {</div><div class='add'>+	bt_shutdown_default: bt-shutdown-default-state {</div><div class='add'>+		function = "gpio";</div><div class='add'>+		pins = "gpio29";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	emmc_sd_default: emmc-sd-default-state {</div><div class='add'>+		pins = "emmc_cmd", "emmc_dat0", "emmc_dat1", "emmc_dat2", "emmc_dat3";</div><div class='add'>+		bias-pull-up;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pwr_button_default: pwr-button-default-state {</div><div class='add'>+		function = "gpio";</div><div class='add'>+		pins = "gpio20";</div><div class='add'>+		bias-pull-up;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdio2_30_default: sdio2-30-default-state {</div><div class='add'>+		clk-pins {</div><div class='add'>+			function = "sd2";</div><div class='add'>+			pins = "gpio30";</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+		cmd-pins {</div><div class='add'>+			function = "sd2";</div><div class='add'>+			pins = "gpio31";</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+		dat-pins {</div><div class='add'>+			function = "sd2";</div><div class='add'>+			pins = "gpio32", "gpio33", "gpio34", "gpio35";</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uarta_24_default: uarta-24-default-state {</div><div class='add'>+		rts-pins {</div><div class='add'>+			function = "uart0";</div><div class='add'>+			pins = "gpio24";</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+		cts-pins {</div><div class='add'>+			function = "uart0";</div><div class='add'>+			pins = "gpio25";</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+		txd-pins {</div><div class='add'>+			function = "uart0";</div><div class='add'>+			pins = "gpio26";</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+		rxd-pins {</div><div class='add'>+			function = "uart0";</div><div class='add'>+			pins = "gpio27";</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wl_on_default: wl-on-default-state {</div><div class='add'>+		function = "gpio";</div><div class='add'>+		pins = "gpio28";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_aon {</div><div class='add'>+	emmc_aon_cd_default: emmc-aon-cd-default-state {</div><div class='add'>+		function = "sd_card_g";</div><div class='add'>+		pins = "aon_gpio5";</div><div class='add'>+		bias-pull-up;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* The Debug UART, on Rpi5 it's on JST-SH 1.0mm 3-pin connector</div><div class='add'>+ * labeled "UART", i.e. the interface with the system console.</div><div class='add'>+ */</div><div class='add'>+&amp;uart10 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SDIO1 is used to drive the SD card */</div><div class='add'>+&amp;sdio1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;emmc_sd_default&gt;, &lt;&amp;emmc_aon_cd_default&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	vqmmc-supply = &lt;&amp;sd_io_1v8_reg&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;sd_vcc_reg&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	sd-uhs-sdr50;</div><div class='add'>+	sd-uhs-ddr50;</div><div class='add'>+	sd-uhs-sdr104;</div><div class='add'>+	cd-gpios = &lt;&amp;gio_aon 5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sdio2 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdio2_30_default&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;wl_on_reg&gt;;</div><div class='add'>+	sd-uhs-ddr50;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	wifi: wifi@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		compatible = "brcm,bcm4329-fmac";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;soc {</div><div class='add'>+	firmware: firmware {</div><div class='add'>+		compatible = "raspberrypi,bcm2835-firmware", "simple-mfd";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		mboxes = &lt;&amp;mailbox&gt;;</div><div class='add'>+		dma-ranges;</div><div class='add'>+</div><div class='add'>+		firmware_clocks: clocks {</div><div class='add'>+			compatible = "raspberrypi,firmware-clocks";</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		reset: reset {</div><div class='add'>+			compatible = "raspberrypi,firmware-reset";</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	power: power {</div><div class='add'>+		compatible = "raspberrypi,bcm2835-power";</div><div class='add'>+		firmware = &lt;&amp;firmware&gt;;</div><div class='add'>+		#power-domain-cells = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* uarta communicates with the BT module */</div><div class='add'>+&amp;uarta {</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	pinctrl-0 = &lt;&amp;uarta_24_default &amp;bt_shutdown_default&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bluetooth: bluetooth {</div><div class='add'>+		compatible = "brcm,bcm43438-bt";</div><div class='add'>+		max-speed = &lt;3000000&gt;;</div><div class='add'>+		shutdown-gpios = &lt;&amp;gio 29 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hvs {</div><div class='add'>+	clocks = &lt;&amp;firmware_clocks 4&gt;, &lt;&amp;firmware_clocks 16&gt;;</div><div class='add'>+	clock-names = "core", "disp";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi0 {</div><div class='add'>+	clocks = &lt;&amp;firmware_clocks 13&gt;, &lt;&amp;firmware_clocks 14&gt;, &lt;&amp;dvp 0&gt;, &lt;&amp;clk_27MHz&gt;;</div><div class='add'>+	clock-names = "hdmi", "bvb", "audio", "cec";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi1 {</div><div class='add'>+	clocks = &lt;&amp;firmware_clocks 13&gt;, &lt;&amp;firmware_clocks 14&gt;, &lt;&amp;dvp 1&gt;, &lt;&amp;clk_27MHz&gt;;</div><div class='add'>+	clock-names = "hdmi", "bvb", "audio", "cec";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts<br/>new file mode 100644<br/>index 000000000000..3e0319fdb93f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts</a></div><div class='hunk'>@@ -0,0 +1,68 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * bcm2712-rpi-5-b-ovl-rp1.dts is the overlay-ready DT which will make</div><div class='add'>+ * the RP1 driver to load the RP1 dtb overlay at runtime, while</div><div class='add'>+ * bcm2712-rpi-5-b.dts (this file) is the fully defined one (i.e. it</div><div class='add'>+ * already contains RP1 node, so no overlay is loaded nor needed).</div><div class='add'>+ * This file is intended to host the override nodes for the RP1 peripherals,</div><div class='add'>+ * e.g. to declare the phy of the ethernet interface or the custom pin setup</div><div class='add'>+ * for several RP1 peripherals.</div><div class='add'>+ * This in turn is due to the fact that there's no current generic</div><div class='add'>+ * infrastructure to reference nodes (i.e. the nodes in rp1-common.dtsi) that</div><div class='add'>+ * are not yet defined in the DT since they are loaded at runtime via overlay.</div><div class='add'>+ * All other nodes that do not have anything to do with RP1 should be added</div><div class='add'>+ * to the included bcm2712-rpi-5-b-ovl-rp1.dts instead.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "bcm2712-rpi-5-b-ovl-rp1.dts"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;rp1_eth;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie2 {</div><div class='add'>+	#include "rp1-nexus.dtsi"</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;rp1_eth {</div><div class='add'>+	assigned-clocks = &lt;&amp;rp1_clocks RP1_CLK_ETH_TSU&gt;,</div><div class='add'>+			  &lt;&amp;rp1_clocks RP1_CLK_ETH&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;50000000&gt;,</div><div class='add'>+			       &lt;125000000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;phy1&gt;;</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		reg = &lt;0x1&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;rp1_gpio 32 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		reset-delay-us = &lt;5000&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		phy1: ethernet-phy@1 {</div><div class='add'>+			reg = &lt;0x1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;rp1_gpio {</div><div class='add'>+	usb_vbus_default_state: usb-vbus-default-state {</div><div class='add'>+		function = "vbus1";</div><div class='add'>+		groups = "vbus1";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;rp1_usb0 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;usb_vbus_default_state&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;rp1_usb1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi<br/>new file mode 100644<br/>index 000000000000..205b87f557d6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/bcm2712.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/bcm2712.dtsi</a></div><div class='hunk'>@@ -0,0 +1,671 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "brcm,bcm2712";</div><div class='add'>+</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	interrupt-parent = &lt;&amp;gicv2&gt;;</div><div class='add'>+</div><div class='add'>+	clocks {</div><div class='add'>+		/* The oscillator is the root of the clock tree. */</div><div class='add'>+		clk_osc: clk-osc {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-output-names = "osc";</div><div class='add'>+			clock-frequency = &lt;54000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		clk_vpu: clk-vpu {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-frequency = &lt;750000000&gt;;</div><div class='add'>+			clock-output-names = "vpu-clock";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		clk_uart: clk-uart {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-frequency = &lt;9216000&gt;;</div><div class='add'>+			clock-output-names = "uart-clock";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		clk_emmc2: clk-emmc2 {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-frequency = &lt;200000000&gt;;</div><div class='add'>+			clock-output-names = "emmc2-clock";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		clk_sw_baud: clk-sw-baud {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-frequency = &lt;96000000&gt;;</div><div class='add'>+			clock-output-names = "sw-baud";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus: cpus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		/* Source for L1 d/i cache-line-size, cache-sets, cache-size</div><div class='add'>+		 * https://developer.arm.com/documentation/100798/0401/L1-memory-system/About-the-L1-memory-system?lang=en</div><div class='add'>+		 * Source for L2 cache-line-size and cache-sets:</div><div class='add'>+		 * https://developer.arm.com/documentation/100798/0401/L2-memory-system/About-the-L2-memory-system?lang=en</div><div class='add'>+		 * and for cache-size:</div><div class='add'>+		 * https://www.raspberrypi.com/documentation/computers/processors.html#bcm2712</div><div class='add'>+		 */</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a76";</div><div class='add'>+			reg = &lt;0x000&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;; // 64KiB(size)/64(line-size)=1024ways/4-way set</div><div class='add'>+			i-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;; // 64KiB(size)/64(line-size)=1024ways/4-way set</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_l0&gt;;</div><div class='add'>+</div><div class='add'>+			l2_cache_l0: l2-cache {</div><div class='add'>+				compatible = "cache";</div><div class='add'>+				cache-size = &lt;0x80000&gt;;</div><div class='add'>+				cache-line-size = &lt;64&gt;;</div><div class='add'>+				cache-sets = &lt;1024&gt;; //512KiB(size)/64(line-size)=8192ways/8-way set</div><div class='add'>+				cache-level = &lt;2&gt;;</div><div class='add'>+				cache-unified;</div><div class='add'>+				next-level-cache = &lt;&amp;l3_cache&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@1 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a76";</div><div class='add'>+			reg = &lt;0x100&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;; // 64KiB(size)/64(line-size)=1024ways/4-way set</div><div class='add'>+			i-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;; // 64KiB(size)/64(line-size)=1024ways/4-way set</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_l1&gt;;</div><div class='add'>+</div><div class='add'>+			l2_cache_l1: l2-cache {</div><div class='add'>+				compatible = "cache";</div><div class='add'>+				cache-size = &lt;0x80000&gt;;</div><div class='add'>+				cache-line-size = &lt;64&gt;;</div><div class='add'>+				cache-sets = &lt;1024&gt;; //512KiB(size)/64(line-size)=8192ways/8-way set</div><div class='add'>+				cache-level = &lt;2&gt;;</div><div class='add'>+				cache-unified;</div><div class='add'>+				next-level-cache = &lt;&amp;l3_cache&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@2 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a76";</div><div class='add'>+			reg = &lt;0x200&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;; // 64KiB(size)/64(line-size)=1024ways/4-way set</div><div class='add'>+			i-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;; // 64KiB(size)/64(line-size)=1024ways/4-way set</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_l2&gt;;</div><div class='add'>+</div><div class='add'>+			l2_cache_l2: l2-cache {</div><div class='add'>+				compatible = "cache";</div><div class='add'>+				cache-size = &lt;0x80000&gt;;</div><div class='add'>+				cache-line-size = &lt;64&gt;;</div><div class='add'>+				cache-sets = &lt;1024&gt;; //512KiB(size)/64(line-size)=8192ways/8-way set</div><div class='add'>+				cache-level = &lt;2&gt;;</div><div class='add'>+				cache-unified;</div><div class='add'>+				next-level-cache = &lt;&amp;l3_cache&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@3 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a76";</div><div class='add'>+			reg = &lt;0x300&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;; // 64KiB(size)/64(line-size)=1024ways/4-way set</div><div class='add'>+			i-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;; // 64KiB(size)/64(line-size)=1024ways/4-way set</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_l3&gt;;</div><div class='add'>+</div><div class='add'>+			l2_cache_l3: l2-cache {</div><div class='add'>+				compatible = "cache";</div><div class='add'>+				cache-size = &lt;0x80000&gt;;</div><div class='add'>+				cache-line-size = &lt;64&gt;;</div><div class='add'>+				cache-sets = &lt;1024&gt;; //512KiB(size)/64(line-size)=8192ways/8-way set</div><div class='add'>+				cache-level = &lt;2&gt;;</div><div class='add'>+				cache-unified;</div><div class='add'>+				next-level-cache = &lt;&amp;l3_cache&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* Source for cache-line-size and cache-sets:</div><div class='add'>+		 * https://developer.arm.com/documentation/100453/0401/L3-cache?lang=en</div><div class='add'>+		 * Source for cache-size:</div><div class='add'>+		 * https://www.raspberrypi.com/documentation/computers/processors.html#bcm2712</div><div class='add'>+		 */</div><div class='add'>+		l3_cache: l3-cache {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-size = &lt;0x200000&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;2048&gt;; // 2MiB(size)/64(line-size)=32768ways/16-way set</div><div class='add'>+			cache-level = &lt;3&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		method = "smc";</div><div class='add'>+		compatible = "arm,psci-1.0", "arm,psci-0.2";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rmem: reserved-memory {</div><div class='add'>+		ranges;</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		atf@0 {</div><div class='add'>+			reg = &lt;0x0 0x0 0x0 0x80000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cma: linux,cma {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			size = &lt;0x0 0x4000000&gt;; /* 64MB */</div><div class='add'>+			reusable;</div><div class='add'>+			linux,cma-default;</div><div class='add'>+			alloc-ranges = &lt;0x0 0x00000000 0x0 0x40000000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc: soc@107c000000 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		ranges = &lt;0x00000000  0x10 0x00000000  0x80000000&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		pcie_rescal: reset-controller@119500 {</div><div class='add'>+			compatible = "brcm,bcm7216-pcie-sata-rescal";</div><div class='add'>+			reg = &lt;0x00119500 0x10&gt;;</div><div class='add'>+			#reset-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sdio1: mmc@fff000 {</div><div class='add'>+			compatible = "brcm,bcm2712-sdhci",</div><div class='add'>+				     "brcm,sdhci-brcmstb";</div><div class='add'>+			reg = &lt;0x00fff000 0x260&gt;,</div><div class='add'>+			      &lt;0x00fff400 0x200&gt;;</div><div class='add'>+			reg-names = "host", "cfg";</div><div class='add'>+			interrupts = &lt;GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk_emmc2&gt;;</div><div class='add'>+			clock-names = "sw_sdio";</div><div class='add'>+			mmc-ddr-3_3v;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		bcm_reset: reset-controller@1504318 {</div><div class='add'>+			compatible = "brcm,brcmstb-reset";</div><div class='add'>+			reg = &lt;0x01504318 0x30&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		system_timer: timer@7c003000 {</div><div class='add'>+			compatible = "brcm,bcm2835-system-timer";</div><div class='add'>+			reg = &lt;0x7c003000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clock-frequency = &lt;1000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mailbox: mailbox@7c013880 {</div><div class='add'>+			compatible = "brcm,bcm2835-mbox";</div><div class='add'>+			reg = &lt;0x7c013880 0x40&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#mbox-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart10: serial@7d001000 {</div><div class='add'>+			compatible = "arm,pl011", "arm,primecell";</div><div class='add'>+			reg = &lt;0x7d001000 0x200&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk_uart&gt;, &lt;&amp;clk_vpu&gt;;</div><div class='add'>+			clock-names = "uartclk", "apb_pclk";</div><div class='add'>+			arm,primecell-periphid = &lt;0x00341011&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl: pinctrl@7d504100 {</div><div class='add'>+			compatible = "brcm,bcm2712c0-pinctrl";</div><div class='add'>+			reg = &lt;0x7d504100 0x30&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gio: gpio@7d508500 {</div><div class='add'>+			compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";</div><div class='add'>+			reg = &lt;0x7d508500 0x40&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;main_irq&gt;;</div><div class='add'>+			interrupts = &lt;0&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			brcm,gpio-bank-widths = &lt;32 22&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uarta: serial@7d50c000 {</div><div class='add'>+			compatible = "brcm,bcm7271-uart";</div><div class='add'>+			reg = &lt;0x7d50c000 0x20&gt;;</div><div class='add'>+			reg-names = "uart";</div><div class='add'>+			clocks = &lt;&amp;clk_sw_baud&gt;;</div><div class='add'>+			clock-names = "sw_baud";</div><div class='add'>+			interrupts = &lt;GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "uart";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_aon: pinctrl@7d510700 {</div><div class='add'>+			compatible = "brcm,bcm2712c0-aon-pinctrl";</div><div class='add'>+			reg = &lt;0x7d510700 0x20&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		interrupt-controller@7d517000 {</div><div class='add'>+			compatible = "brcm,bcm7271-l2-intc";</div><div class='add'>+			reg = &lt;0x7d517000 0x10&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gio_aon: gpio@7d517c00 {</div><div class='add'>+			compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";</div><div class='add'>+			reg = &lt;0x7d517c00 0x40&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			brcm,gpio-bank-widths = &lt;17 6&gt;;</div><div class='add'>+			/* The lack of 'interrupt-controller' property here is intended:</div><div class='add'>+			 * don't use GIO_AON as an interrupt controller because it will</div><div class='add'>+			 * clash with the firmware monitoring the PMIC interrupt via the VPU.</div><div class='add'>+			 */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sdio2: mmc@1100000 {</div><div class='add'>+			compatible = "brcm,bcm2712-sdhci",</div><div class='add'>+				     "brcm,sdhci-brcmstb";</div><div class='add'>+			reg = &lt;0x01100000  0x260&gt;,</div><div class='add'>+			      &lt;0x01100400  0x200&gt;;</div><div class='add'>+			reg-names = "host", "cfg";</div><div class='add'>+			interrupts = &lt;GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk_emmc2&gt;;</div><div class='add'>+			clock-names = "sw_sdio";</div><div class='add'>+			sdhci-caps-mask = &lt;0x0000C000 0x0&gt;;</div><div class='add'>+			sdhci-caps = &lt;0x0 0x0&gt;;</div><div class='add'>+			mmc-ddr-3_3v;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gicv2: interrupt-controller@7fff9000 {</div><div class='add'>+			compatible = "arm,gic-400";</div><div class='add'>+			reg = &lt;0x7fff9000 0x1000&gt;,</div><div class='add'>+			      &lt;0x7fffa000 0x2000&gt;,</div><div class='add'>+			      &lt;0x7fffc000 0x2000&gt;,</div><div class='add'>+			      &lt;0x7fffe000 0x2000&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#address-cells = &lt;0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |</div><div class='add'>+					IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aon_intr: interrupt-controller@7d510600 {</div><div class='add'>+			compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc";</div><div class='add'>+			reg = &lt;0x7d510600 0x30&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pixelvalve0: pixelvalve@7c410000 {</div><div class='add'>+			compatible = "brcm,bcm2712-pixelvalve0";</div><div class='add'>+			reg = &lt;0x7c410000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pixelvalve1: pixelvalve@7c411000 {</div><div class='add'>+			compatible = "brcm,bcm2712-pixelvalve1";</div><div class='add'>+			reg = &lt;0x7c411000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mop: mop@7c500000 {</div><div class='add'>+			compatible = "brcm,bcm2712-mop";</div><div class='add'>+			reg = &lt;0x7c500000 0x28&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;disp_intr&gt;;</div><div class='add'>+			interrupts = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		moplet: moplet@7c501000 {</div><div class='add'>+			compatible = "brcm,bcm2712-moplet";</div><div class='add'>+			reg = &lt;0x7c501000 0x20&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;disp_intr&gt;;</div><div class='add'>+			interrupts = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		disp_intr: interrupt-controller@7c502000 {</div><div class='add'>+			compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc";</div><div class='add'>+			reg = &lt;0x7c502000 0x30&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dvp: clock@7c700000 {</div><div class='add'>+			compatible = "brcm,brcm2711-dvp";</div><div class='add'>+			reg = &lt;0x7c700000 0x10&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk_108MHz&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ddc0: i2c@7d508200 {</div><div class='add'>+			compatible = "brcm,brcmstb-i2c";</div><div class='add'>+			reg = &lt;0x7d508200 0x58&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;bsc_irq&gt;;</div><div class='add'>+			interrupts = &lt;1&gt;;</div><div class='add'>+			clock-frequency = &lt;97500&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ddc1: i2c@7d508280 {</div><div class='add'>+			compatible = "brcm,brcmstb-i2c";</div><div class='add'>+			reg = &lt;0x7d508280 0x58&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;bsc_irq&gt;;</div><div class='add'>+			interrupts = &lt;2&gt;;</div><div class='add'>+			clock-frequency = &lt;97500&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		bsc_irq: interrupt-controller@7d508380 {</div><div class='add'>+			compatible = "brcm,bcm7271-l2-intc";</div><div class='add'>+			reg = &lt;0x7d508380 0x10&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		main_irq: interrupt-controller@7d508400 {</div><div class='add'>+			compatible = "brcm,bcm7271-l2-intc";</div><div class='add'>+			reg = &lt;0x7d508400 0x10&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		hdmi0: hdmi@7c701400 {</div><div class='add'>+			compatible = "brcm,bcm2712-hdmi0";</div><div class='add'>+			reg = &lt;0x7c701400 0x300&gt;,</div><div class='add'>+			      &lt;0x7c701000 0x200&gt;,</div><div class='add'>+			      &lt;0x7c701d00 0x300&gt;,</div><div class='add'>+			      &lt;0x7c702000 0x80&gt;,</div><div class='add'>+			      &lt;0x7c703800 0x200&gt;,</div><div class='add'>+			      &lt;0x7c704000 0x800&gt;,</div><div class='add'>+			      &lt;0x7c700100 0x80&gt;,</div><div class='add'>+			      &lt;0x7d510800 0x100&gt;,</div><div class='add'>+			      &lt;0x7c720000 0x100&gt;;</div><div class='add'>+			reg-names = "hdmi",</div><div class='add'>+				    "dvp",</div><div class='add'>+				    "phy",</div><div class='add'>+				    "rm",</div><div class='add'>+				    "packet",</div><div class='add'>+				    "metadata",</div><div class='add'>+				    "csc",</div><div class='add'>+				    "cec",</div><div class='add'>+				    "hd";</div><div class='add'>+			resets = &lt;&amp;dvp 1&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aon_intr&gt;;</div><div class='add'>+			interrupts = &lt;1&gt;, &lt;2&gt;, &lt;3&gt;,</div><div class='add'>+				     &lt;7&gt;, &lt;8&gt;;</div><div class='add'>+			interrupt-names = "cec-tx", "cec-rx", "cec-low",</div><div class='add'>+					  "hpd-connected", "hpd-removed";</div><div class='add'>+			ddc = &lt;&amp;ddc0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		hdmi1: hdmi@7c706400 {</div><div class='add'>+			compatible = "brcm,bcm2712-hdmi1";</div><div class='add'>+			reg = &lt;0x7c706400 0x300&gt;,</div><div class='add'>+			      &lt;0x7c706000 0x200&gt;,</div><div class='add'>+			      &lt;0x7c706d00 0x300&gt;,</div><div class='add'>+			      &lt;0x7c707000 0x80&gt;,</div><div class='add'>+			      &lt;0x7c708800 0x200&gt;,</div><div class='add'>+			      &lt;0x7c709000 0x800&gt;,</div><div class='add'>+			      &lt;0x7c700180 0x80&gt;,</div><div class='add'>+			      &lt;0x7d511000 0x100&gt;,</div><div class='add'>+			      &lt;0x7c720000 0x100&gt;;</div><div class='add'>+			reg-names = "hdmi",</div><div class='add'>+				    "dvp",</div><div class='add'>+				    "phy",</div><div class='add'>+				    "rm",</div><div class='add'>+				    "packet",</div><div class='add'>+				    "metadata",</div><div class='add'>+				    "csc",</div><div class='add'>+				    "cec",</div><div class='add'>+				    "hd";</div><div class='add'>+			resets = &lt;&amp;dvp 2&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;aon_intr&gt;;</div><div class='add'>+			interrupts = &lt;11&gt;, &lt;12&gt;, &lt;13&gt;,</div><div class='add'>+				     &lt;14&gt;, &lt;15&gt;;</div><div class='add'>+			interrupt-names = "cec-tx", "cec-rx", "cec-low",</div><div class='add'>+					  "hpd-connected", "hpd-removed";</div><div class='add'>+			ddc = &lt;&amp;ddc1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	axi: axi {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		ranges = &lt;0x00 0x00000000  0x00 0x00000000  0x10 0x00000000&gt;,</div><div class='add'>+			 &lt;0x10 0x00000000  0x10 0x00000000  0x01 0x00000000&gt;,</div><div class='add'>+			 &lt;0x14 0x00000000  0x14 0x00000000  0x04 0x00000000&gt;,</div><div class='add'>+			 &lt;0x18 0x00000000  0x18 0x00000000  0x04 0x00000000&gt;,</div><div class='add'>+			 &lt;0x1c 0x00000000  0x1c 0x00000000  0x04 0x00000000&gt;;</div><div class='add'>+</div><div class='add'>+		dma-ranges = &lt;0x00 0x00000000  0x00 0x00000000  0x10 0x00000000&gt;,</div><div class='add'>+			     &lt;0x10 0x00000000  0x10 0x00000000  0x01 0x00000000&gt;,</div><div class='add'>+			     &lt;0x14 0x00000000  0x14 0x00000000  0x04 0x00000000&gt;,</div><div class='add'>+			     &lt;0x18 0x00000000  0x18 0x00000000  0x04 0x00000000&gt;,</div><div class='add'>+			     &lt;0x1c 0x00000000  0x1c 0x00000000  0x04 0x00000000&gt;;</div><div class='add'>+</div><div class='add'>+		vc4: gpu {</div><div class='add'>+			compatible = "brcm,bcm2712-vc6";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie0: pcie@1000100000 {</div><div class='add'>+			compatible = "brcm,bcm2712-pcie";</div><div class='add'>+			reg = &lt;0x10 0x00100000 0x00 0x9310&gt;;</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			linux,pci-domain = &lt;0&gt;;</div><div class='add'>+			max-link-speed = &lt;2&gt;;</div><div class='add'>+			num-lanes = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gicv2&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "pcie", "msi";</div><div class='add'>+			interrupt-map-mask = &lt;0x0 0x0 0x0 0x7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;gicv2 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;gicv2 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;gicv2 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;gicv2 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			resets = &lt;&amp;pcie_rescal&gt;, &lt;&amp;bcm_reset 42&gt;;</div><div class='add'>+			reset-names = "rescal", "bridge";</div><div class='add'>+			msi-controller;</div><div class='add'>+			msi-parent = &lt;&amp;pcie0&gt;;</div><div class='add'>+</div><div class='add'>+			ranges =</div><div class='add'>+				/* ~4GiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */</div><div class='add'>+				&lt;0x02000000 0x00 0x00000000 0x17 0x00000000 0x00 0xfffffffc&gt;,</div><div class='add'>+				/* 12GiB, 64-bit, prefetchable at PCIe 04_0000_0000 */</div><div class='add'>+				&lt;0x43000000 0x04 0x00000000 0x14 0x00000000 0x03 0x00000000&gt;;</div><div class='add'>+</div><div class='add'>+			dma-ranges =</div><div class='add'>+				/* 64GiB, 64-bit, prefetchable at PCIe 10_0000_0000 */</div><div class='add'>+				&lt;0x43000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie1: pcie@1000110000 {</div><div class='add'>+			compatible = "brcm,bcm2712-pcie";</div><div class='add'>+			reg = &lt;0x10 0x00110000 0x00 0x9310&gt;;</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			linux,pci-domain = &lt;1&gt;;</div><div class='add'>+			max-link-speed = &lt;2&gt;;</div><div class='add'>+			num-lanes = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gicv2&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "pcie", "msi";</div><div class='add'>+			interrupt-map-mask = &lt;0x0 0x0 0x0 0x7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;gicv2 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;gicv2 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;gicv2 GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;gicv2 GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			resets = &lt;&amp;pcie_rescal&gt;, &lt;&amp;bcm_reset 43&gt;;</div><div class='add'>+			reset-names = "rescal", "bridge";</div><div class='add'>+			msi-controller;</div><div class='add'>+			msi-parent = &lt;&amp;mip1&gt;;</div><div class='add'>+</div><div class='add'>+			ranges =</div><div class='add'>+				/* ~4GiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */</div><div class='add'>+				&lt;0x02000000 0x00 0x00000000 0x1b 0x00000000 0x00 0xfffffffc&gt;,</div><div class='add'>+				/* 12GiB, 64-bit, prefetchable at PCIe 04_0000_0000 */</div><div class='add'>+				&lt;0x43000000 0x04 0x00000000 0x18 0x00000000 0x03 0x00000000&gt;;</div><div class='add'>+</div><div class='add'>+			dma-ranges =</div><div class='add'>+				/* 64GiB, 64-bit, non-prefetchable at PCIe 10_0000_0000 */</div><div class='add'>+				&lt;0x03000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000&gt;,</div><div class='add'>+				/* 4KiB, 64-bit, non-prefetchable at PCIe ff_ffff_f000 MIP1 */</div><div class='add'>+				&lt;0x03000000 0xff 0xfffff000 0x10 0x00131000 0x00 0x00001000&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie2: pcie@1000120000 {</div><div class='add'>+			compatible = "brcm,bcm2712-pcie";</div><div class='add'>+			reg = &lt;0x10 0x00120000 0x00 0x9310&gt;;</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			linux,pci-domain = &lt;2&gt;;</div><div class='add'>+			max-link-speed = &lt;2&gt;;</div><div class='add'>+			num-lanes = &lt;4&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gicv2&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "pcie", "msi";</div><div class='add'>+			interrupt-map-mask = &lt;0x0 0x0 0x0 0x7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;gicv2 GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;gicv2 GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;gicv2 GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;gicv2 GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			resets = &lt;&amp;pcie_rescal&gt;, &lt;&amp;bcm_reset 44&gt;;</div><div class='add'>+			reset-names = "rescal", "bridge";</div><div class='add'>+			msi-controller;</div><div class='add'>+			msi-parent = &lt;&amp;mip0&gt;;</div><div class='add'>+</div><div class='add'>+			ranges =</div><div class='add'>+				/* ~4GiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */</div><div class='add'>+				&lt;0x02000000 0x00 0x00000000 0x1f 0x00000000 0x00 0xfffffffc&gt;,</div><div class='add'>+				/* 12GiB, 64-bit, prefetchable at PCIe 04_0000_0000 */</div><div class='add'>+				&lt;0x43000000 0x04 0x00000000 0x1c 0x00000000 0x03 0x00000000&gt;;</div><div class='add'>+</div><div class='add'>+			dma-ranges =</div><div class='add'>+				/* 4MiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */</div><div class='add'>+				&lt;0x02000000 0x00 0x00000000 0x1f 0x00000000 0x00 0x00400000&gt;,</div><div class='add'>+				/* 64GiB, 64-bit, prefetchable at PCIe 10_0000_0000 */</div><div class='add'>+				&lt;0x43000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000&gt;,</div><div class='add'>+				/* 4KiB, 64-bit, non-prefetchable at PCIe ff_ffff_f000 MIP0 */</div><div class='add'>+				&lt;0x03000000 0xff 0xfffff000 0x10 0x00130000 0x00 0x00001000&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mip0: msi-controller@1000130000 {</div><div class='add'>+			compatible = "brcm,bcm2712-mip";</div><div class='add'>+			reg = &lt;0x10 0x00130000 0x00 0xc0&gt;,</div><div class='add'>+			      &lt;0xff 0xfffff000 0x00 0x1000&gt;;</div><div class='add'>+			msi-controller;</div><div class='add'>+			msi-ranges = &lt;&amp;gicv2 GIC_SPI 128 IRQ_TYPE_EDGE_RISING 64&gt;;</div><div class='add'>+			brcm,msi-offset = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mip1: msi-controller@1000131000 {</div><div class='add'>+			compatible = "brcm,bcm2712-mip";</div><div class='add'>+			reg = &lt;0x10 0x00131000 0x00 0xc0&gt;,</div><div class='add'>+			      &lt;0xff 0xfffff000 0x00 0x1000&gt;;</div><div class='add'>+			msi-controller;</div><div class='add'>+			msi-ranges = &lt;&amp;gicv2 GIC_SPI 247 IRQ_TYPE_EDGE_RISING 8&gt;;</div><div class='add'>+			brcm,msi-offset = &lt;8&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |</div><div class='add'>+					  IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |</div><div class='add'>+					  IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |</div><div class='add'>+					  IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |</div><div class='add'>+					  IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) |</div><div class='add'>+					  IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_27MHz: clk-27M {</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		clock-frequency = &lt;27000000&gt;;</div><div class='add'>+		clock-output-names = "27MHz-clock";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_108MHz: clk-108M {</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		clock-frequency = &lt;108000000&gt;;</div><div class='add'>+		clock-output-names = "108MHz-clock";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hvs: hvs@107c580000 {</div><div class='add'>+		compatible = "brcm,bcm2712-hvs";</div><div class='add'>+		reg = &lt;0x10 0x7c580000 0x0 0x1a000&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;disp_intr&gt;;</div><div class='add'>+		interrupts = &lt;2&gt;, &lt;9&gt;, &lt;16&gt;;</div><div class='add'>+		interrupt-names = "ch0-eof", "ch1-eof", "ch2-eof";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-2-b.dts b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-2-b.dts<br/>new file mode 100644<br/>index 000000000000..57742ed40049<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/bcm2837-rpi-2-b.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/bcm2837-rpi-2-b.dts</a></div><div class='hunk'>@@ -0,0 +1,2 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+#include "arm/broadcom/bcm2837-rpi-2-b.dts"</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-a-plus.dts b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-a-plus.dts<br/>index f0ec56a1c4d7..17d778a7e0c9 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-a-plus.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-a-plus.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-a-plus.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-a-plus.dts</a></div><div class='hunk'>@@ -1,2 +1,2 @@</div><div class='ctx'> // SPDX-License-Identifier: GPL-2.0</div><div class='del'>-#include "arm/bcm2837-rpi-3-a-plus.dts"</div><div class='add'>+#include "arm/broadcom/bcm2837-rpi-3-a-plus.dts"</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b-plus.dts b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b-plus.dts<br/>index 46ad2023cccf..0cf6240b6bf0 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b-plus.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b-plus.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b-plus.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b-plus.dts</a></div><div class='hunk'>@@ -1,2 +1,2 @@</div><div class='ctx'> // SPDX-License-Identifier: GPL-2.0</div><div class='del'>-#include "arm/bcm2837-rpi-3-b-plus.dts"</div><div class='add'>+#include "arm/broadcom/bcm2837-rpi-3-b-plus.dts"</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts<br/>index 89b78d6c19bf..f429468fd86e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts</a></div><div class='hunk'>@@ -1,2 +1,2 @@</div><div class='ctx'> // SPDX-License-Identifier: GPL-2.0</div><div class='del'>-#include "arm/bcm2837-rpi-3-b.dts"</div><div class='add'>+#include "arm/broadcom/bcm2837-rpi-3-b.dts"</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-cm3-io3.dts b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-cm3-io3.dts<br/>index b1c4ab212c64..3fa21bd16b49 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/bcm2837-rpi-cm3-io3.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/bcm2837-rpi-cm3-io3.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/bcm2837-rpi-cm3-io3.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/bcm2837-rpi-cm3-io3.dts</a></div><div class='hunk'>@@ -1,2 +1,2 @@</div><div class='ctx'> // SPDX-License-Identifier: GPL-2.0</div><div class='del'>-#include "arm/bcm2837-rpi-cm3-io3.dts"</div><div class='add'>+#include "arm/broadcom/bcm2837-rpi-cm3-io3.dts"</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-zero-2-w.dts b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-zero-2-w.dts<br/>new file mode 100644<br/>index 000000000000..363381a0cfb5<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/bcm2837-rpi-zero-2-w.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/bcm2837-rpi-zero-2-w.dts</a></div><div class='hunk'>@@ -0,0 +1,2 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+#include "arm/broadcom/bcm2837-rpi-zero-2-w.dts"</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile<br/>new file mode 100644<br/>index 000000000000..9a8461d91c8c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/bcmbca/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/bcmbca/Makefile</a></div><div class='hunk'>@@ -0,0 +1,15 @@</div><div class='add'>+# SPDX-License-Identifier: GPL-2.0</div><div class='add'>+dtb-$(CONFIG_ARCH_BCMBCA) += \</div><div class='add'>+				bcm4906-netgear-r8000p.dtb \</div><div class='add'>+				bcm4906-tplink-archer-c2300-v1.dtb \</div><div class='add'>+				bcm4906-zyxel-ex3510b.dtb \</div><div class='add'>+				bcm4908-asus-gt-ac5300.dtb \</div><div class='add'>+				bcm4908-netgear-raxe500.dtb \</div><div class='add'>+				bcm94908.dtb \</div><div class='add'>+				bcm4912-asus-gt-ax6000.dtb \</div><div class='add'>+				bcm94912.dtb \</div><div class='add'>+				bcm963158.dtb \</div><div class='add'>+				bcm96858.dtb \</div><div class='add'>+				bcm963146.dtb \</div><div class='add'>+				bcm96856.dtb \</div><div class='add'>+				bcm96813.dtb</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts<br/>new file mode 100644<br/>index 000000000000..a5f9ec92bd5e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts</a></div><div class='hunk'>@@ -0,0 +1,170 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+#include "bcm4906.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "netgear,r8000p", "brcm,bcm4906", "brcm,bcm4908", "brcm,bcmbca";</div><div class='add'>+	model = "Netgear R8000P";</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x00 0x00 0x00 0x20000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-power-white {</div><div class='add'>+			function = LED_FUNCTION_POWER;</div><div class='add'>+			color = &lt;LED_COLOR_ID_WHITE&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio0 8 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-power-amber {</div><div class='add'>+			function = LED_FUNCTION_POWER;</div><div class='add'>+			color = &lt;LED_COLOR_ID_AMBER&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio0 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-wps {</div><div class='add'>+			function = LED_FUNCTION_WPS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_WHITE&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio0 10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-2ghz {</div><div class='add'>+			function = "2ghz";</div><div class='add'>+			color = &lt;LED_COLOR_ID_WHITE&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio0 14 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-5ghz-1 {</div><div class='add'>+			function = "5ghz-1";</div><div class='add'>+			color = &lt;LED_COLOR_ID_WHITE&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio0 15 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-5ghz-2 {</div><div class='add'>+			function = "5ghz-2";</div><div class='add'>+			color = &lt;LED_COLOR_ID_WHITE&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio0 16 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-usb2 {</div><div class='add'>+			function = "usb2";</div><div class='add'>+			color = &lt;LED_COLOR_ID_WHITE&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio0 17 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			trigger-sources = &lt;&amp;ohci_port1&gt;, &lt;&amp;ehci_port1&gt;;</div><div class='add'>+			linux,default-trigger = "usbport";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-usb3 {</div><div class='add'>+			function = "usb3";</div><div class='add'>+			color = &lt;LED_COLOR_ID_WHITE&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio0 18 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			trigger-sources = &lt;&amp;ohci_port2&gt;, &lt;&amp;ehci_port2&gt;, &lt;&amp;xhci_port2&gt;;</div><div class='add'>+			linux,default-trigger = "usbport";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-wifi {</div><div class='add'>+			function = "wifi";</div><div class='add'>+			color = &lt;LED_COLOR_ID_WHITE&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio0 56 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;enet {</div><div class='add'>+	nvmem-cells = &lt;&amp;base_mac_addr&gt;;</div><div class='add'>+	nvmem-cell-names = "mac-address";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_phy {</div><div class='add'>+	brcm,ioc = &lt;1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ehci {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ohci {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xhci {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ports {</div><div class='add'>+	port@0 {</div><div class='add'>+		label = "lan4";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	port@1 {</div><div class='add'>+		label = "lan3";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	port@2 {</div><div class='add'>+		label = "lan2";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	port@3 {</div><div class='add'>+		label = "lan1";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	port@7 {</div><div class='add'>+		reg = &lt;7&gt;;</div><div class='add'>+		phy-mode = "internal";</div><div class='add'>+		phy-handle = &lt;&amp;phy12&gt;;</div><div class='add'>+		label = "wan";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;nand_controller {</div><div class='add'>+	brcm,wp-not-connected;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;nandcs {</div><div class='add'>+	nand-ecc-strength = &lt;4&gt;;</div><div class='add'>+	nand-ecc-step-size = &lt;512&gt;;</div><div class='add'>+	nand-on-flash-bbt;</div><div class='add'>+</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	partitions {</div><div class='add'>+		compatible = "fixed-partitions";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		partition@0 {</div><div class='add'>+			label = "cferom";</div><div class='add'>+			reg = &lt;0x0 0x100000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges = &lt;0 0x0 0x100000&gt;;</div><div class='add'>+</div><div class='add'>+			nvmem-layout {</div><div class='add'>+				compatible = "fixed-layout";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				base_mac_addr: mac@106a0 {</div><div class='add'>+					reg = &lt;0x106a0 0x6&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		partition@100000 {</div><div class='add'>+			compatible = "brcm,bcm4908-firmware";</div><div class='add'>+			label = "firmware";</div><div class='add'>+			reg = &lt;0x100000 0x4400000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts<br/>new file mode 100644<br/>index 000000000000..19fc03ef47a0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts</a></div><div class='hunk'>@@ -0,0 +1,191 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+#include "bcm4906.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "tplink,archer-c2300-v1", "brcm,bcm4906", "brcm,bcm4908", "brcm,bcmbca";</div><div class='add'>+	model = "TP-Link Archer C2300 V1";</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x00 0x00 0x00 0x20000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-power {</div><div class='add'>+			function = LED_FUNCTION_POWER;</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio0 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-2ghz {</div><div class='add'>+			function = "2ghz";</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio0 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-5ghz {</div><div class='add'>+			function = "5ghz";</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio0 3 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-wan-amber {</div><div class='add'>+			function = LED_FUNCTION_WAN;</div><div class='add'>+			color = &lt;LED_COLOR_ID_AMBER&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio0 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-wan-blue {</div><div class='add'>+			function = LED_FUNCTION_WAN;</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio0 10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-lan {</div><div class='add'>+			function = LED_FUNCTION_LAN;</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio0 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-wps {</div><div class='add'>+			function = LED_FUNCTION_WPS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio0 14 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-usb2 {</div><div class='add'>+			function = "usb2";</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio0 15 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			trigger-sources = &lt;&amp;ohci_port1&gt;, &lt;&amp;ehci_port1&gt;;</div><div class='add'>+			linux,default-trigger = "usbport";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-usb3 {</div><div class='add'>+			function = "usb3";</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio0 17 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			trigger-sources = &lt;&amp;ohci_port2&gt;, &lt;&amp;ehci_port2&gt;, &lt;&amp;xhci_port2&gt;;</div><div class='add'>+			linux,default-trigger = "usbport";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-brightness {</div><div class='add'>+			function = LED_FUNCTION_BACKLIGHT;</div><div class='add'>+			color = &lt;LED_COLOR_ID_WHITE&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio0 19 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys-polled {</div><div class='add'>+		compatible = "gpio-keys-polled";</div><div class='add'>+		poll-interval = &lt;100&gt;;</div><div class='add'>+</div><div class='add'>+		key-brightness {</div><div class='add'>+			label = "LEDs";</div><div class='add'>+			linux,code = &lt;KEY_BRIGHTNESS_ZERO&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio0 18 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-wps {</div><div class='add'>+			label = "WPS";</div><div class='add'>+			linux,code = &lt;KEY_WPS_BUTTON&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio0 21 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-wifi {</div><div class='add'>+			label = "WiFi";</div><div class='add'>+			linux,code = &lt;KEY_RFKILL&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio0 22 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-restart {</div><div class='add'>+			label = "Reset";</div><div class='add'>+			linux,code = &lt;KEY_RESTART&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio0 23 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_phy {</div><div class='add'>+	brcm,ioc = &lt;1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ehci {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ohci {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xhci {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ports {</div><div class='add'>+	port@0 {</div><div class='add'>+		label = "lan4";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	port@1 {</div><div class='add'>+		label = "lan3";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	port@2 {</div><div class='add'>+		label = "lan2";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	port@3 {</div><div class='add'>+		label = "lan1";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	port@7 {</div><div class='add'>+		reg = &lt;7&gt;;</div><div class='add'>+		phy-mode = "internal";</div><div class='add'>+		phy-handle = &lt;&amp;phy12&gt;;</div><div class='add'>+		label = "wan";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;nand_controller {</div><div class='add'>+	brcm,wp-not-connected;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;nandcs {</div><div class='add'>+	nand-ecc-strength = &lt;4&gt;;</div><div class='add'>+	nand-ecc-step-size = &lt;512&gt;;</div><div class='add'>+	nand-on-flash-bbt;</div><div class='add'>+</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	partitions {</div><div class='add'>+		compatible = "brcm,bcm4908-partitions";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		partition@0 {</div><div class='add'>+			label = "cferom";</div><div class='add'>+			reg = &lt;0x0 0x100000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		partition@100000 {</div><div class='add'>+			compatible = "brcm,bcm4908-firmware";</div><div class='add'>+			reg = &lt;0x100000 0x3900000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		partition@5800000 {</div><div class='add'>+			compatible = "brcm,bcm4908-firmware";</div><div class='add'>+			reg = &lt;0x3a00000 0x3900000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-zyxel-ex3510b.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-zyxel-ex3510b.dts<br/>new file mode 100644<br/>index 000000000000..54e453bd09f7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-zyxel-ex3510b.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-zyxel-ex3510b.dts</a></div><div class='hunk'>@@ -0,0 +1,196 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+#include "bcm4906.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "zyxel,ex3510b", "brcm,bcm4906", "brcm,bcm4908", "brcm,bcmbca";</div><div class='add'>+	model = "Zyxel EX3510-B";</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x0 0x0 0x20000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys-polled {</div><div class='add'>+		compatible = "gpio-keys-polled";</div><div class='add'>+		poll-interval = &lt;100&gt;;</div><div class='add'>+</div><div class='add'>+		key-wps {</div><div class='add'>+			label = "WPS";</div><div class='add'>+			linux,code = &lt;KEY_WPS_BUTTON&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio0 22 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-reset {</div><div class='add'>+			label = "Reset";</div><div class='add'>+			linux,code = &lt;KEY_RESTART&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio0 23 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;leds {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pins_led_0_a&gt;, &lt;&amp;pins_led_2_a&gt;, &lt;&amp;pins_led_3_a&gt;,</div><div class='add'>+		    &lt;&amp;pins_led_4_a&gt;, &lt;&amp;pins_led_10_a&gt;, &lt;&amp;pins_led_12_a&gt;,</div><div class='add'>+		    &lt;&amp;pins_led_14_a&gt;, &lt;&amp;pins_led_15_a&gt;, &lt;&amp;pins_led_21_a&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	led@0 {</div><div class='add'>+		reg = &lt;0x0&gt;;</div><div class='add'>+		function = LED_FUNCTION_POWER;</div><div class='add'>+		color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	led@2 {</div><div class='add'>+		reg = &lt;0x2&gt;;</div><div class='add'>+		function = LED_FUNCTION_WAN_ONLINE;</div><div class='add'>+		color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	led@3 {</div><div class='add'>+		reg = &lt;0x3&gt;;</div><div class='add'>+		function = LED_FUNCTION_WAN_ONLINE;</div><div class='add'>+		color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	led@4 {</div><div class='add'>+		reg = &lt;0x4&gt;;</div><div class='add'>+		function = LED_FUNCTION_USB;</div><div class='add'>+		color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+		trigger-sources = &lt;&amp;ohci_port1&gt;, &lt;&amp;ohci_port2&gt;,</div><div class='add'>+				  &lt;&amp;ehci_port1&gt;, &lt;&amp;ehci_port2&gt;,</div><div class='add'>+				  &lt;&amp;xhci_port1&gt;, &lt;&amp;xhci_port2&gt;;</div><div class='add'>+		linux,default-trigger = "usbport";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	led@a {</div><div class='add'>+		reg = &lt;0xa&gt;;</div><div class='add'>+		function = LED_FUNCTION_POWER;</div><div class='add'>+		color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+		linux,default-trigger = "default-on";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	led@c {</div><div class='add'>+		reg = &lt;0xc&gt;;</div><div class='add'>+		function = LED_FUNCTION_LAN;</div><div class='add'>+		color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+		active-low;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	led@e {</div><div class='add'>+		reg = &lt;0xe&gt;;</div><div class='add'>+		function = LED_FUNCTION_WPS;</div><div class='add'>+		color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+		active-low;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	led@f {</div><div class='add'>+		reg = &lt;0xf&gt;;</div><div class='add'>+		function = LED_FUNCTION_WPS;</div><div class='add'>+		color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+		active-low;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	led@15 {</div><div class='add'>+		reg = &lt;0x15&gt;;</div><div class='add'>+		function = LED_FUNCTION_WAN;</div><div class='add'>+		color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+		active-low;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;enet {</div><div class='add'>+	nvmem-cells = &lt;&amp;base_mac_addr&gt;;</div><div class='add'>+	nvmem-cell-names = "mac-address";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_phy {</div><div class='add'>+	brcm,ioc = &lt;1&gt;;</div><div class='add'>+	brcm,ipp = &lt;1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ehci {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ohci {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xhci {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ports {</div><div class='add'>+	port@0 {</div><div class='add'>+		label = "lan1";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	port@1 {</div><div class='add'>+		label = "lan2";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	port@2 {</div><div class='add'>+		label = "lan3";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	port@3 {</div><div class='add'>+		label = "lan4";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	port@7 {</div><div class='add'>+		reg = &lt;7&gt;;</div><div class='add'>+		phy-mode = "internal";</div><div class='add'>+		phy-handle = &lt;&amp;phy12&gt;;</div><div class='add'>+		label = "wan";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;nand_controller {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;nandcs {</div><div class='add'>+	brcm,nand-oob-sector-size = &lt;27&gt;;</div><div class='add'>+	nand-ecc-strength = &lt;8&gt;;</div><div class='add'>+	nand-ecc-step-size = &lt;512&gt;;</div><div class='add'>+	nand-on-flash-bbt;</div><div class='add'>+</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	partitions {</div><div class='add'>+		compatible = "brcm,bcm4908-partitions";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		partition@0 {</div><div class='add'>+			compatible = "nvmem-cells";</div><div class='add'>+			label = "cferom";</div><div class='add'>+			reg = &lt;0x0 0x100000&gt;;</div><div class='add'>+			read-only;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			base_mac_addr: mac@106a0 {</div><div class='add'>+				reg = &lt;0x106a0 0x6&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		partition@100000 {</div><div class='add'>+			compatible = "brcm,bcm4908-firmware";</div><div class='add'>+			reg = &lt;0x100000 0x5f80000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		partition@6080000 {</div><div class='add'>+			compatible = "brcm,bcm4908-firmware";</div><div class='add'>+			reg = &lt;0x6080000 0x5f80000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906.dtsi<br/>new file mode 100644<br/>index 000000000000..d084c33d5ca8<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/bcmbca/bcm4906.dtsi</a></div><div class='hunk'>@@ -0,0 +1,26 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+</div><div class='add'>+#include "bcm4908.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	cpus {</div><div class='add'>+		/delete-node/ cpu@2;</div><div class='add'>+</div><div class='add'>+		/delete-node/ cpu@3;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu {</div><div class='add'>+		compatible = "arm,cortex-a53-pmu";</div><div class='add'>+		interrupts = &lt;GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-affinity = &lt;&amp;cpu0&gt;, &lt;&amp;cpu1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts<br/>new file mode 100644<br/>index 000000000000..2a0d4ee3bd79<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts</a></div><div class='hunk'>@@ -0,0 +1,212 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+#include "bcm4908.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "asus,gt-ac5300", "brcm,bcm4908", "brcm,bcmbca";</div><div class='add'>+	model = "Asus GT-AC5300";</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x00 0x00 0x00 0x40000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys-polled {</div><div class='add'>+		compatible = "gpio-keys-polled";</div><div class='add'>+		poll-interval = &lt;100&gt;;</div><div class='add'>+</div><div class='add'>+		key-wifi {</div><div class='add'>+			label = "WiFi";</div><div class='add'>+			linux,code = &lt;KEY_RFKILL&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio0 28 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-wps {</div><div class='add'>+			label = "WPS";</div><div class='add'>+			linux,code = &lt;KEY_WPS_BUTTON&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio0 29 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-restart {</div><div class='add'>+			label = "Reset";</div><div class='add'>+			linux,code = &lt;KEY_RESTART&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio0 30 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-brightness {</div><div class='add'>+			label = "LEDs";</div><div class='add'>+			linux,code = &lt;KEY_BRIGHTNESS_ZERO&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio0 31 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;enet {</div><div class='add'>+	nvmem-cells = &lt;&amp;base_mac_addr&gt;;</div><div class='add'>+	nvmem-cell-names = "mac-address";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_phy {</div><div class='add'>+	brcm,ioc = &lt;1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ehci {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ohci {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xhci {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ports {</div><div class='add'>+	port@0 {</div><div class='add'>+		label = "lan2";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	port@1 {</div><div class='add'>+		label = "lan1";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	port@2 {</div><div class='add'>+		label = "lan6";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	port@3 {</div><div class='add'>+		label = "lan5";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* External BCM53134S switch */</div><div class='add'>+	port@7 {</div><div class='add'>+		label = "sw";</div><div class='add'>+		reg = &lt;7&gt;;</div><div class='add'>+		phy-mode = "rgmii";</div><div class='add'>+</div><div class='add'>+		fixed-link {</div><div class='add'>+			speed = &lt;1000&gt;;</div><div class='add'>+			full-duplex;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdio {</div><div class='add'>+	/* lan8 */</div><div class='add'>+	ethernet-phy@0 {</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* lan7 */</div><div class='add'>+	ethernet-phy@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* lan4 */</div><div class='add'>+	ethernet-phy@2 {</div><div class='add'>+		reg = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* lan3 */</div><div class='add'>+	ethernet-phy@3 {</div><div class='add'>+		reg = &lt;3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;leds {</div><div class='add'>+	led@11 {</div><div class='add'>+		reg = &lt;0x11&gt;;</div><div class='add'>+		function = LED_FUNCTION_POWER;</div><div class='add'>+		color = &lt;LED_COLOR_ID_WHITE&gt;;</div><div class='add'>+		default-state = "on";</div><div class='add'>+		active-low;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pins_led_17_a&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	led@12 {</div><div class='add'>+		reg = &lt;0x12&gt;;</div><div class='add'>+		function = LED_FUNCTION_WAN;</div><div class='add'>+		color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+		active-low;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pins_led_18_a&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	led@14 {</div><div class='add'>+		reg = &lt;0x14&gt;;</div><div class='add'>+		function = LED_FUNCTION_WPS;</div><div class='add'>+		color = &lt;LED_COLOR_ID_WHITE&gt;;</div><div class='add'>+		active-low;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pins_led_20_a&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	led@15 {</div><div class='add'>+		reg = &lt;0x15&gt;;</div><div class='add'>+		function = LED_FUNCTION_WAN;</div><div class='add'>+		color = &lt;LED_COLOR_ID_WHITE&gt;;</div><div class='add'>+		active-low;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pins_led_21_a&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	led@19 {</div><div class='add'>+		reg = &lt;0x19&gt;;</div><div class='add'>+		function = LED_FUNCTION_LAN;</div><div class='add'>+		color = &lt;LED_COLOR_ID_WHITE&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pins_led_25_a&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;nand_controller {</div><div class='add'>+	brcm,wp-not-connected;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;nandcs {</div><div class='add'>+	nand-ecc-strength = &lt;4&gt;;</div><div class='add'>+	nand-ecc-step-size = &lt;512&gt;;</div><div class='add'>+	nand-on-flash-bbt;</div><div class='add'>+</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	partitions {</div><div class='add'>+		compatible = "brcm,bcm4908-partitions";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		partition@0 {</div><div class='add'>+			label = "cferom";</div><div class='add'>+			reg = &lt;0x0 0x100000&gt;;</div><div class='add'>+</div><div class='add'>+			nvmem-layout {</div><div class='add'>+				compatible = "fixed-layout";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				base_mac_addr: mac@106a0 {</div><div class='add'>+					reg = &lt;0x106a0 0x6&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		partition@100000 {</div><div class='add'>+			compatible = "brcm,bcm4908-firmware";</div><div class='add'>+			reg = &lt;0x100000 0x5700000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		partition@5800000 {</div><div class='add'>+			compatible = "brcm,bcm4908-firmware";</div><div class='add'>+			reg = &lt;0x5800000 0x5700000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-netgear-raxe500.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-netgear-raxe500.dts<br/>new file mode 100644<br/>index 000000000000..23b96c663239<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-netgear-raxe500.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-netgear-raxe500.dts</a></div><div class='hunk'>@@ -0,0 +1,50 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+</div><div class='add'>+#include "bcm4908.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "netgear,raxe500", "brcm,bcm4908", "brcm,bcmbca";</div><div class='add'>+	model = "Netgear RAXE500";</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x00 0x00 0x00 0x40000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ehci {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ohci {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xhci {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ports {</div><div class='add'>+	port@0 {</div><div class='add'>+		label = "lan4";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	port@1 {</div><div class='add'>+		label = "lan3";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	port@2 {</div><div class='add'>+		label = "lan2";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	port@3 {</div><div class='add'>+		label = "lan1";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	port@7 {</div><div class='add'>+		reg = &lt;7&gt;;</div><div class='add'>+		phy-mode = "internal";</div><div class='add'>+		phy-handle = &lt;&amp;phy12&gt;;</div><div class='add'>+		label = "wan";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi<br/>new file mode 100644<br/>index 000000000000..3b7595fd4e81<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi</a></div><div class='hunk'>@@ -0,0 +1,757 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/phy/phy.h&gt;</div><div class='add'>+#include &lt;dt-bindings/soc/bcm-pmb.h&gt;</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "brcm,brahma-b53";</div><div class='add'>+			reg = &lt;0x0&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0x0 0xff8&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@1 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "brcm,brahma-b53";</div><div class='add'>+			reg = &lt;0x1&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0x0 0xff8&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@2 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "brcm,brahma-b53";</div><div class='add'>+			reg = &lt;0x2&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0x0 0xff8&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@3 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "brcm,brahma-b53";</div><div class='add'>+			reg = &lt;0x3&gt;;</div><div class='add'>+			enable-method = "spin-table";</div><div class='add'>+			cpu-release-addr = &lt;0x0 0xff8&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2: l2-cache0 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		cfe-stub@0 {</div><div class='add'>+			reg = &lt;0x0 0x0 0x0 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	axi@81000000 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges = &lt;0x00 0x00 0x81000000 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@1000 {</div><div class='add'>+			compatible = "arm,gic-400";</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			#address-cells = &lt;0&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			reg = &lt;0x1000 0x1000&gt;,</div><div class='add'>+			      &lt;0x2000 0x2000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu {</div><div class='add'>+		compatible = "arm,cortex-a53-pmu";</div><div class='add'>+		interrupts = &lt;GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-affinity = &lt;&amp;cpu0&gt;, &lt;&amp;cpu1&gt;, &lt;&amp;cpu2&gt;, &lt;&amp;cpu3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clocks {</div><div class='add'>+		periph_clk: periph_clk {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-frequency = &lt;50000000&gt;;</div><div class='add'>+			clock-output-names = "periph";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		hsspi_pll: hsspi-pll {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-frequency = &lt;400000000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges = &lt;0x00 0x00 0x80000000 0x281000&gt;;</div><div class='add'>+</div><div class='add'>+		enet: ethernet@2000 {</div><div class='add'>+			compatible = "brcm,bcm4908-enet";</div><div class='add'>+			reg = &lt;0x2000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "rx", "tx";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_phy: usb-phy@c200 {</div><div class='add'>+			compatible = "brcm,bcm4908-usb-phy";</div><div class='add'>+			reg = &lt;0xc200 0x100&gt;;</div><div class='add'>+			reg-names = "ctrl";</div><div class='add'>+			power-domains = &lt;&amp;pmb BCM_PMB_HOST_USB&gt;;</div><div class='add'>+			dr_mode = "host";</div><div class='add'>+			brcm,has-xhci;</div><div class='add'>+			brcm,has-eohci;</div><div class='add'>+			#phy-cells = &lt;1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ehci: usb@c300 {</div><div class='add'>+			compatible = "generic-ehci";</div><div class='add'>+			reg = &lt;0xc300 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			phys = &lt;&amp;usb_phy PHY_TYPE_USB2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			ehci_port1: port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				#trigger-source-cells = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ehci_port2: port@2 {</div><div class='add'>+				reg = &lt;2&gt;;</div><div class='add'>+				#trigger-source-cells = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ohci: usb@c400 {</div><div class='add'>+			compatible = "generic-ohci";</div><div class='add'>+			reg = &lt;0xc400 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			phys = &lt;&amp;usb_phy PHY_TYPE_USB2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			ohci_port1: port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				#trigger-source-cells = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ohci_port2: port@2 {</div><div class='add'>+				reg = &lt;2&gt;;</div><div class='add'>+				#trigger-source-cells = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		xhci: usb@d000 {</div><div class='add'>+			compatible = "generic-xhci";</div><div class='add'>+			reg = &lt;0xd000 0x8c8&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			phys = &lt;&amp;usb_phy PHY_TYPE_USB3&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			xhci_port1: port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				#trigger-source-cells = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			xhci_port2: port@2 {</div><div class='add'>+				reg = &lt;2&gt;;</div><div class='add'>+				#trigger-source-cells = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		bus@80000 {</div><div class='add'>+			compatible = "simple-bus";</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			ranges = &lt;0 0x80000 0x50000&gt;;</div><div class='add'>+</div><div class='add'>+			ethernet-switch@0 {</div><div class='add'>+				compatible = "brcm,bcm4908-switch";</div><div class='add'>+				reg = &lt;0x0 0x40000&gt;,</div><div class='add'>+				      &lt;0x40000 0x110&gt;,</div><div class='add'>+				      &lt;0x40340 0x30&gt;,</div><div class='add'>+				      &lt;0x40380 0x30&gt;,</div><div class='add'>+				      &lt;0x40600 0x34&gt;,</div><div class='add'>+				      &lt;0x40800 0x208&gt;;</div><div class='add'>+				reg-names = "core", "reg", "intrl2_0",</div><div class='add'>+					    "intrl2_1", "fcb", "acb";</div><div class='add'>+				interrupts = &lt;GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				brcm,num-gphy = &lt;5&gt;;</div><div class='add'>+				brcm,num-rgmii-ports = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+				ports: ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+						phy-mode = "internal";</div><div class='add'>+						phy-handle = &lt;&amp;phy8&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+						phy-mode = "internal";</div><div class='add'>+						phy-handle = &lt;&amp;phy9&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@2 {</div><div class='add'>+						reg = &lt;2&gt;;</div><div class='add'>+						phy-mode = "internal";</div><div class='add'>+						phy-handle = &lt;&amp;phy10&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@3 {</div><div class='add'>+						reg = &lt;3&gt;;</div><div class='add'>+						phy-mode = "internal";</div><div class='add'>+						phy-handle = &lt;&amp;phy11&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@8 {</div><div class='add'>+						reg = &lt;8&gt;;</div><div class='add'>+						phy-mode = "internal";</div><div class='add'>+						ethernet = &lt;&amp;enet&gt;;</div><div class='add'>+</div><div class='add'>+						fixed-link {</div><div class='add'>+							speed = &lt;1000&gt;;</div><div class='add'>+							full-duplex;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mdio: mdio@405c0 {</div><div class='add'>+				compatible = "brcm,unimac-mdio";</div><div class='add'>+				reg = &lt;0x405c0 0x8&gt;;</div><div class='add'>+				reg-names = "mdio";</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				phy8: ethernet-phy@8 {</div><div class='add'>+					reg = &lt;8&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				phy9: ethernet-phy@9 {</div><div class='add'>+					reg = &lt;9&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				phy10: ethernet-phy@a {</div><div class='add'>+					reg = &lt;10&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				phy11: ethernet-phy@b {</div><div class='add'>+					reg = &lt;11&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				phy12: ethernet-phy@c {</div><div class='add'>+					reg = &lt;12&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		procmon: bus@280000 {</div><div class='add'>+			compatible = "simple-bus";</div><div class='add'>+			reg = &lt;0x280000 0x1000&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			pmb: power-controller@2800c0 {</div><div class='add'>+				compatible = "brcm,bcm4908-pmb";</div><div class='add'>+				reg = &lt;0x2800c0 0x40&gt;;</div><div class='add'>+				#power-domain-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PERF Peripherals */</div><div class='add'>+	bus@ff800000 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges = &lt;0x00 0x00 0xff800000 0x400000&gt;;</div><div class='add'>+</div><div class='add'>+		twd: timer-mfd@400 {</div><div class='add'>+			compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon";</div><div class='add'>+			reg = &lt;0x400 0x4c&gt;;</div><div class='add'>+			ranges = &lt;0x0 0x400 0x4c&gt;;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			timer@0 {</div><div class='add'>+				compatible = "brcm,bcm63138-timer";</div><div class='add'>+				reg = &lt;0x0 0x28&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			watchdog@28 {</div><div class='add'>+				compatible = "brcm,bcm6345-wdt";</div><div class='add'>+				reg = &lt;0x28 0x8&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* GPIOs 0 .. 31 */</div><div class='add'>+		gpio0: gpio@500 {</div><div class='add'>+			compatible = "brcm,bcm6345-gpio";</div><div class='add'>+			reg = &lt;0x500 0x04&gt;, &lt;0x528 0x04&gt;;</div><div class='add'>+			reg-names = "dirout", "dat";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* GPIOs 32 .. 63 */</div><div class='add'>+		gpio1: gpio@504 {</div><div class='add'>+			compatible = "brcm,bcm6345-gpio";</div><div class='add'>+			reg = &lt;0x504 0x04&gt;, &lt;0x52c 0x04&gt;;</div><div class='add'>+			reg-names = "dirout", "dat";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* GPIOs 64 .. 95 */</div><div class='add'>+		gpio2: gpio@508 {</div><div class='add'>+			compatible = "brcm,bcm6345-gpio";</div><div class='add'>+			reg = &lt;0x508 0x04&gt;, &lt;0x530 0x04&gt;;</div><div class='add'>+			reg-names = "dirout", "dat";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* GPIOs 96 .. 127 */</div><div class='add'>+		gpio3: gpio@50c {</div><div class='add'>+			compatible = "brcm,bcm6345-gpio";</div><div class='add'>+			reg = &lt;0x50c 0x04&gt;, &lt;0x534 0x04&gt;;</div><div class='add'>+			reg-names = "dirout", "dat";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* GPIOs 128 .. 159 */</div><div class='add'>+		gpio4: gpio@510 {</div><div class='add'>+			compatible = "brcm,bcm6345-gpio";</div><div class='add'>+			reg = &lt;0x510 0x04&gt;, &lt;0x538 0x04&gt;;</div><div class='add'>+			reg-names = "dirout", "dat";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* GPIOs 160 .. 191 */</div><div class='add'>+		gpio5: gpio@514 {</div><div class='add'>+			compatible = "brcm,bcm6345-gpio";</div><div class='add'>+			reg = &lt;0x514 0x04&gt;, &lt;0x53c 0x04&gt;;</div><div class='add'>+			reg-names = "dirout", "dat";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* GPIOs 192 .. 223 */</div><div class='add'>+		gpio6: gpio@518 {</div><div class='add'>+			compatible = "brcm,bcm6345-gpio";</div><div class='add'>+			reg = &lt;0x518 0x04&gt;, &lt;0x540 0x04&gt;;</div><div class='add'>+			reg-names = "dirout", "dat";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* GPIOs 224 .. 255 */</div><div class='add'>+		gpio7: gpio@51c {</div><div class='add'>+			compatible = "brcm,bcm6345-gpio";</div><div class='add'>+			reg = &lt;0x51c 0x04&gt;, &lt;0x544 0x04&gt;;</div><div class='add'>+			reg-names = "dirout", "dat";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* GPIOs 256 .. 287 */</div><div class='add'>+		gpio8: gpio@520 {</div><div class='add'>+			compatible = "brcm,bcm6345-gpio";</div><div class='add'>+			reg = &lt;0x520 0x04&gt;, &lt;0x548 0x04&gt;;</div><div class='add'>+			reg-names = "dirout", "dat";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* GPIOs 288 .. 319 */</div><div class='add'>+		gpio9: gpio@524 {</div><div class='add'>+			compatible = "brcm,bcm6345-gpio";</div><div class='add'>+			reg = &lt;0x524 0x04&gt;, &lt;0x54c 0x04&gt;;</div><div class='add'>+			reg-names = "dirout", "dat";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl@560 {</div><div class='add'>+			compatible = "brcm,bcm4908-pinctrl";</div><div class='add'>+			reg = &lt;0x560 0x10&gt;;</div><div class='add'>+</div><div class='add'>+			pins_led_0_a: led_0-a-pins {</div><div class='add'>+				function = "led_0";</div><div class='add'>+				groups = "led_0_grp_a";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pins_led_1_a: led_1-a-pins {</div><div class='add'>+				function = "led_1";</div><div class='add'>+				groups = "led_1_grp_a";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pins_led_2_a: led_2-a-pins {</div><div class='add'>+				function = "led_2";</div><div class='add'>+				groups = "led_2_grp_a";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pins_led_3_a: led_3-a-pins {</div><div class='add'>+				function = "led_3";</div><div class='add'>+				groups = "led_3_grp_a";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pins_led_4_a: led_4-a-pins {</div><div class='add'>+				function = "led_4";</div><div class='add'>+				groups = "led_4_grp_a";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pins_led_5_a: led_5-a-pins {</div><div class='add'>+				function = "led_5";</div><div class='add'>+				groups = "led_5_grp_a";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pins_led_6_a: led_6-a-pins {</div><div class='add'>+				function = "led_6";</div><div class='add'>+				groups = "led_6_grp_a";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pins_led_7_a: led_7-a-pins {</div><div class='add'>+				function = "led_7";</div><div class='add'>+				groups = "led_7_grp_a";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pins_led_8_a: led_8-a-pins {</div><div class='add'>+				function = "led_8";</div><div class='add'>+				groups = "led_8_grp_a";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pins_led_9_a: led_9-a-pins {</div><div class='add'>+				function = "led_9";</div><div class='add'>+				groups = "led_9_grp_a";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pins_led_10_a: led_10-a-pins {</div><div class='add'>+				function = "led_10";</div><div class='add'>+				groups = "led_10_grp_a";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pins_led_11_a: led_11-a-pins {</div><div class='add'>+				function = "led_11";</div><div class='add'>+				groups = "led_11_grp_a";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pins_led_12_a: led_12-a-pins {</div><div class='add'>+				function = "led_12";</div><div class='add'>+				groups = "led_12_grp_a";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pins_led_13_a: led_13-a-pins {</div><div class='add'>+				function = "led_13";</div><div class='add'>+				groups = "led_13_grp_a";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pins_led_14_a: led_14-a-pins {</div><div class='add'>+				function = "led_14";</div><div class='add'>+				groups = "led_14_grp_a";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pins_led_15_a: led_15-a-pins {</div><div class='add'>+				function = "led_15";</div><div class='add'>+				groups = "led_15_grp_a";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pins_led_16_a: led_16-a-pins {</div><div class='add'>+				function = "led_16";</div><div class='add'>+				groups = "led_16_grp_a";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pins_led_17_a: led_17-a-pins {</div><div class='add'>+				function = "led_17";</div><div class='add'>+				groups = "led_17_grp_a";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pins_led_18_a: led_18-a-pins {</div><div class='add'>+				function = "led_18";</div><div class='add'>+				groups = "led_18_grp_a";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pins_led_19_a: led_19-a-pins {</div><div class='add'>+				function = "led_19";</div><div class='add'>+				groups = "led_19_grp_a";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pins_led_20_a: led_20-a-pins {</div><div class='add'>+				function = "led_20";</div><div class='add'>+				groups = "led_20_grp_a";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pins_led_21_a: led_21-a-pins {</div><div class='add'>+				function = "led_21";</div><div class='add'>+				groups = "led_21_grp_a";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pins_led_22_a: led_22-a-pins {</div><div class='add'>+				function = "led_22";</div><div class='add'>+				groups = "led_22_grp_a";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pins_led_23_a: led_23-a-pins {</div><div class='add'>+				function = "led_23";</div><div class='add'>+				groups = "led_23_grp_a";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pins_led_24_a: led_24-a-pins {</div><div class='add'>+				function = "led_24";</div><div class='add'>+				groups = "led_24_grp_a";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pins_led_25_a: led_25-a-pins {</div><div class='add'>+				function = "led_25";</div><div class='add'>+				groups = "led_25_grp_a";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pins_led_26_a: led_26-a-pins {</div><div class='add'>+				function = "led_26";</div><div class='add'>+				groups = "led_26_grp_a";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pins_led_27_a: led_27-a-pins {</div><div class='add'>+				function = "led_27";</div><div class='add'>+				groups = "led_27_grp_a";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pins_led_28_a: led_28-a-pins {</div><div class='add'>+				function = "led_28";</div><div class='add'>+				groups = "led_28_grp_a";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pins_led_29_a: led_29-a-pins {</div><div class='add'>+				function = "led_29";</div><div class='add'>+				groups = "led_29_grp_a";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pins_led_30_a: led_30-a-pins {</div><div class='add'>+				function = "led_30";</div><div class='add'>+				groups = "led_30_grp_a";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pins_led_31_a: led_31-a-pins {</div><div class='add'>+				function = "led_31";</div><div class='add'>+				groups = "led_31_grp_a";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pins_hs_uart: hs_uart-pins {</div><div class='add'>+				function = "hs_uart";</div><div class='add'>+				groups = "hs_uart_grp";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pins_i2c_a: i2c-a-pins {</div><div class='add'>+				function = "i2c";</div><div class='add'>+				groups = "i2c_grp_a";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pins_i2c_b: i2c-b-pins {</div><div class='add'>+				function = "i2c";</div><div class='add'>+				groups = "i2c_grp_b";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pins_i2s: i2s-pins {</div><div class='add'>+				function = "i2s";</div><div class='add'>+				groups = "i2s_grp";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pins_nand_ctrl: nand_ctrl-pins {</div><div class='add'>+				function = "nand_ctrl";</div><div class='add'>+				groups = "nand_ctrl_grp";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pins_nand_data: nand_data-pins {</div><div class='add'>+				function = "nand_data";</div><div class='add'>+				groups = "nand_data_grp";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pins_emmc_ctrl: emmc_ctrl-pins {</div><div class='add'>+				function = "emmc_ctrl";</div><div class='add'>+				groups = "emmc_ctrl_grp";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pins_usb0_pwr: usb0_pwr-pins {</div><div class='add'>+				function = "usb0_pwr";</div><div class='add'>+				groups = "usb0_pwr_grp";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pins_usb1_pwr: usb1_pwr-pins {</div><div class='add'>+				function = "usb1_pwr";</div><div class='add'>+				groups = "usb1_pwr_grp";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart0: serial@640 {</div><div class='add'>+			compatible = "brcm,bcm6345-uart";</div><div class='add'>+			reg = &lt;0x640 0x18&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;periph_clk&gt;;</div><div class='add'>+			clock-names = "refclk";</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		leds: leds@800 {</div><div class='add'>+			compatible = "brcm,bcm4908-leds", "brcm,bcm63138-leds";</div><div class='add'>+			reg = &lt;0x800 0xdc&gt;;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rng@b80 {</div><div class='add'>+			compatible = "brcm,iproc-rng200";</div><div class='add'>+			reg = &lt;0xb80 0x28&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		hsspi: spi@1000 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			compatible = "brcm,bcm4908-hsspi", "brcm,bcmbca-hsspi-v1.0";</div><div class='add'>+			reg = &lt;0x1000 0x600&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;hsspi_pll &amp;hsspi_pll&gt;;</div><div class='add'>+			clock-names = "hsspi", "pll";</div><div class='add'>+			num-cs = &lt;8&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nand_controller: nand-controller@1800 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";</div><div class='add'>+			reg = &lt;0x1800 0x600&gt;, &lt;0x2000 0x10&gt;;</div><div class='add'>+			reg-names = "nand", "nand-int-base";</div><div class='add'>+			interrupts = &lt;GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "nand_ctlrdy";</div><div class='add'>+			brcm,wp-not-connected;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			nandcs: nand@0 {</div><div class='add'>+				compatible = "brcm,nandcs";</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@2100 {</div><div class='add'>+			compatible = "brcm,brcmper-i2c";</div><div class='add'>+			reg = &lt;0x2100 0x58&gt;;</div><div class='add'>+			clock-frequency = &lt;97500&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;pins_i2c_a&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		misc@2600 {</div><div class='add'>+			compatible = "brcm,misc", "simple-mfd";</div><div class='add'>+			reg = &lt;0x2600 0xe4&gt;;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges = &lt;0x00 0x2600 0xe4&gt;;</div><div class='add'>+</div><div class='add'>+			reset-controller@2644 {</div><div class='add'>+				compatible = "brcm,bcm4908-misc-pcie-reset";</div><div class='add'>+				reg = &lt;0x44 0x04&gt;;</div><div class='add'>+				#reset-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pl081_dma: dma-controller@59000 {</div><div class='add'>+			compatible = "arm,pl081", "arm,primecell";</div><div class='add'>+			// The magic B105F00D info is missing</div><div class='add'>+			arm,primecell-periphid = &lt;0x00041081&gt;;</div><div class='add'>+			reg = &lt;0x59000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			memcpy-burst-size = &lt;256&gt;;</div><div class='add'>+			memcpy-bus-width = &lt;32&gt;;</div><div class='add'>+			clocks = &lt;&amp;periph_clk&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			#dma-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reboot {</div><div class='add'>+		compatible = "syscon-reboot";</div><div class='add'>+		regmap = &lt;&amp;twd&gt;;</div><div class='add'>+		offset = &lt;0x34&gt;;</div><div class='add'>+		mask = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912-asus-gt-ax6000.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912-asus-gt-ax6000.dts<br/>new file mode 100644<br/>index 000000000000..ed554666e95e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912-asus-gt-ax6000.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/bcmbca/bcm4912-asus-gt-ax6000.dts</a></div><div class='hunk'>@@ -0,0 +1,19 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "bcm4912.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "asus,gt-ax6000", "brcm,bcm4912", "brcm,bcmbca";</div><div class='add'>+	model = "Asus GT-AX6000";</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x00 0x00 0x00 0x40000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi<br/>new file mode 100644<br/>index 000000000000..14b2adfb817c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi</a></div><div class='hunk'>@@ -0,0 +1,164 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Broadcom Ltd.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "brcm,bcm4912", "brcm,bcmbca";</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		B53_0: cpu@0 {</div><div class='add'>+			compatible = "brcm,brahma-b53";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x0&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		B53_1: cpu@1 {</div><div class='add'>+			compatible = "brcm,brahma-b53";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x1&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		B53_2: cpu@2 {</div><div class='add'>+			compatible = "brcm,brahma-b53";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x2&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		B53_3: cpu@3 {</div><div class='add'>+			compatible = "brcm,brahma-b53";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x3&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		L2_0: l2-cache0 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			&lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			&lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			&lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu: pmu {</div><div class='add'>+		compatible = "arm,cortex-a53-pmu";</div><div class='add'>+		interrupts = &lt;GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			&lt;GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			&lt;GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			&lt;GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-affinity = &lt;&amp;B53_0&gt;, &lt;&amp;B53_1&gt;,</div><div class='add'>+			&lt;&amp;B53_2&gt;, &lt;&amp;B53_3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clocks: clocks {</div><div class='add'>+		periph_clk: periph-clk {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-frequency = &lt;200000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart_clk: uart-clk {</div><div class='add'>+			compatible = "fixed-factor-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clocks = &lt;&amp;periph_clk&gt;;</div><div class='add'>+			clock-div = &lt;4&gt;;</div><div class='add'>+			clock-mult = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		hsspi_pll: hsspi-pll {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-frequency = &lt;200000000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-0.2";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	axi@81000000 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges = &lt;0x0 0x0 0x81000000 0x8000&gt;;</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@1000 {</div><div class='add'>+			compatible = "arm,gic-400";</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='add'>+			reg = &lt;0x1000 0x1000&gt;,</div><div class='add'>+				&lt;0x2000 0x2000&gt;,</div><div class='add'>+				&lt;0x4000 0x2000&gt;,</div><div class='add'>+				&lt;0x6000 0x2000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bus@ff800000 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges = &lt;0x0 0x0 0xff800000 0x800000&gt;;</div><div class='add'>+</div><div class='add'>+		hsspi: spi@1000 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			compatible = "brcm,bcm4912-hsspi", "brcm,bcmbca-hsspi-v1.1";</div><div class='add'>+			reg = &lt;0x1000 0x600&gt;, &lt;0x2610 0x4&gt;;</div><div class='add'>+			reg-names = "hsspi", "spim-ctrl";</div><div class='add'>+			interrupts = &lt;GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;hsspi_pll &amp;hsspi_pll&gt;;</div><div class='add'>+			clock-names = "hsspi", "pll";</div><div class='add'>+			num-cs = &lt;8&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nand_controller: nand-controller@1800 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";</div><div class='add'>+			reg = &lt;0x1800 0x600&gt;, &lt;0x2000 0x10&gt;;</div><div class='add'>+			reg-names = "nand", "nand-int-base";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			nandcs: nand@0 {</div><div class='add'>+				compatible = "brcm,nandcs";</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart0: serial@12000 {</div><div class='add'>+			compatible = "arm,pl011", "arm,primecell";</div><div class='add'>+			reg = &lt;0x12000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;uart_clk&gt;, &lt;&amp;uart_clk&gt;;</div><div class='add'>+			clock-names = "uartclk", "apb_pclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi<br/>new file mode 100644<br/>index 000000000000..589b8a1efc72<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi</a></div><div class='hunk'>@@ -0,0 +1,145 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Broadcom Ltd.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "brcm,bcm63146", "brcm,bcmbca";</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		B53_0: cpu@0 {</div><div class='add'>+			compatible = "brcm,brahma-b53";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x0&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		B53_1: cpu@1 {</div><div class='add'>+			compatible = "brcm,brahma-b53";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x1&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		L2_0: l2-cache0 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			&lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			&lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			&lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu: pmu {</div><div class='add'>+		compatible = "arm,cortex-a53-pmu";</div><div class='add'>+		interrupts = &lt;GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			&lt;GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-affinity = &lt;&amp;B53_0&gt;, &lt;&amp;B53_1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clocks: clocks {</div><div class='add'>+		periph_clk: periph-clk {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-frequency = &lt;200000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart_clk: uart-clk {</div><div class='add'>+			compatible = "fixed-factor-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clocks = &lt;&amp;periph_clk&gt;;</div><div class='add'>+			clock-div = &lt;4&gt;;</div><div class='add'>+			clock-mult = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		hsspi_pll: hsspi-pll {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-frequency = &lt;200000000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-0.2";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	axi@81000000 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges = &lt;0x0 0x0 0x81000000 0x8000&gt;;</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@1000 {</div><div class='add'>+			compatible = "arm,gic-400";</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			reg = &lt;0x1000 0x1000&gt;,</div><div class='add'>+				&lt;0x2000 0x2000&gt;,</div><div class='add'>+				&lt;0x4000 0x2000&gt;,</div><div class='add'>+				&lt;0x6000 0x2000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |</div><div class='add'>+					IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bus@ff800000 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges = &lt;0x0 0x0 0xff800000 0x800000&gt;;</div><div class='add'>+</div><div class='add'>+		hsspi: spi@1000 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			compatible = "brcm,bcm63146-hsspi", "brcm,bcmbca-hsspi-v1.0";</div><div class='add'>+			reg = &lt;0x1000 0x600&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;hsspi_pll &amp;hsspi_pll&gt;;</div><div class='add'>+			clock-names = "hsspi", "pll";</div><div class='add'>+			num-cs = &lt;8&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nand_controller: nand-controller@1800 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";</div><div class='add'>+			reg = &lt;0x1800 0x600&gt;, &lt;0x2000 0x10&gt;;</div><div class='add'>+			reg-names = "nand", "nand-int-base";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			nandcs: nand@0 {</div><div class='add'>+				compatible = "brcm,nandcs";</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart0: serial@12000 {</div><div class='add'>+			compatible = "arm,pl011", "arm,primecell";</div><div class='add'>+			reg = &lt;0x12000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;uart_clk&gt;, &lt;&amp;uart_clk&gt;;</div><div class='add'>+			clock-names = "uartclk", "apb_pclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi<br/>new file mode 100644<br/>index 000000000000..a441388c0cd2<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi</a></div><div class='hunk'>@@ -0,0 +1,292 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Broadcom Ltd.</div><div class='add'>+ * This DTSI is for the B0 and later revision of the SoC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "brcm,bcm63158", "brcm,bcmbca";</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		B53_0: cpu@0 {</div><div class='add'>+			compatible = "brcm,brahma-b53";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x0&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		B53_1: cpu@1 {</div><div class='add'>+			compatible = "brcm,brahma-b53";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x1&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		B53_2: cpu@2 {</div><div class='add'>+			compatible = "brcm,brahma-b53";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x2&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		B53_3: cpu@3 {</div><div class='add'>+			compatible = "brcm,brahma-b53";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x3&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		L2_0: l2-cache0 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			&lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			&lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			&lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu: pmu {</div><div class='add'>+		compatible = "arm,cortex-a53-pmu";</div><div class='add'>+		interrupts = &lt;GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			&lt;GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			&lt;GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			&lt;GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-affinity = &lt;&amp;B53_0&gt;, &lt;&amp;B53_1&gt;,</div><div class='add'>+			&lt;&amp;B53_2&gt;, &lt;&amp;B53_3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clocks: clocks {</div><div class='add'>+		periph_clk: periph-clk {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-frequency = &lt;200000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart_clk: uart-clk {</div><div class='add'>+			compatible = "fixed-factor-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clocks = &lt;&amp;periph_clk&gt;;</div><div class='add'>+			clock-div = &lt;4&gt;;</div><div class='add'>+			clock-mult = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		hsspi_pll: hsspi-pll {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-frequency = &lt;400000000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-0.2";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	axi@81000000 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges = &lt;0x0 0x0 0x81000000 0x8000&gt;;</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@1000 {</div><div class='add'>+			compatible = "arm,gic-400";</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='add'>+			reg = &lt;0x1000 0x1000&gt;,</div><div class='add'>+				&lt;0x2000 0x2000&gt;,</div><div class='add'>+				&lt;0x4000 0x2000&gt;,</div><div class='add'>+				&lt;0x6000 0x2000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bus@ff800000 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges = &lt;0x0 0x0 0xff800000 0x800000&gt;;</div><div class='add'>+</div><div class='add'>+		/* GPIOs 0 .. 31 */</div><div class='add'>+		gpio0: gpio@500 {</div><div class='add'>+			compatible = "brcm,bcm6345-gpio";</div><div class='add'>+			reg = &lt;0x500 0x04&gt;, &lt;0x520 0x04&gt;;</div><div class='add'>+			reg-names = "dirout", "dat";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* GPIOs 32 .. 63 */</div><div class='add'>+		gpio1: gpio@504 {</div><div class='add'>+			compatible = "brcm,bcm6345-gpio";</div><div class='add'>+			reg = &lt;0x504 0x04&gt;, &lt;0x524 0x04&gt;;</div><div class='add'>+			reg-names = "dirout", "dat";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* GPIOs 64 .. 95 */</div><div class='add'>+		gpio2: gpio@508 {</div><div class='add'>+			compatible = "brcm,bcm6345-gpio";</div><div class='add'>+			reg = &lt;0x508 0x04&gt;, &lt;0x528 0x04&gt;;</div><div class='add'>+			reg-names = "dirout", "dat";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* GPIOs 96 .. 127 */</div><div class='add'>+		gpio3: gpio@50c {</div><div class='add'>+			compatible = "brcm,bcm6345-gpio";</div><div class='add'>+			reg = &lt;0x50c 0x04&gt;, &lt;0x52c 0x04&gt;;</div><div class='add'>+			reg-names = "dirout", "dat";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* GPIOs 128 .. 159 */</div><div class='add'>+		gpio4: gpio@510 {</div><div class='add'>+			compatible = "brcm,bcm6345-gpio";</div><div class='add'>+			reg = &lt;0x510 0x04&gt;, &lt;0x530 0x04&gt;;</div><div class='add'>+			reg-names = "dirout", "dat";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* GPIOs 160 .. 191 */</div><div class='add'>+		gpio5: gpio@514 {</div><div class='add'>+			compatible = "brcm,bcm6345-gpio";</div><div class='add'>+			reg = &lt;0x514 0x04&gt;, &lt;0x534 0x04&gt;;</div><div class='add'>+			reg-names = "dirout", "dat";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* GPIOs 192 .. 223 */</div><div class='add'>+		gpio6: gpio@518 {</div><div class='add'>+			compatible = "brcm,bcm6345-gpio";</div><div class='add'>+			reg = &lt;0x518 0x04&gt;, &lt;0x538 0x04&gt;;</div><div class='add'>+			reg-names = "dirout", "dat";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* GPIOs 224 .. 255 */</div><div class='add'>+		gpio7: gpio@51c {</div><div class='add'>+			compatible = "brcm,bcm6345-gpio";</div><div class='add'>+			reg = &lt;0x51c 0x04&gt;, &lt;0x53c 0x04&gt;;</div><div class='add'>+			reg-names = "dirout", "dat";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+		leds: led-controller@800 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			compatible = "brcm,bcm63138-leds";</div><div class='add'>+			reg = &lt;0x800 0xdc&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rng@b80 {</div><div class='add'>+			compatible = "brcm,iproc-rng200";</div><div class='add'>+			reg = &lt;0xb80 0x28&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		hsspi: spi@1000 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			compatible = "brcm,bcm63158-hsspi", "brcm,bcmbca-hsspi-v1.0";</div><div class='add'>+			reg = &lt;0x1000 0x600&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;hsspi_pll &amp;hsspi_pll&gt;;</div><div class='add'>+			clock-names = "hsspi", "pll";</div><div class='add'>+			num-cs = &lt;8&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nand_controller: nand-controller@1800 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";</div><div class='add'>+			reg = &lt;0x1800 0x600&gt;, &lt;0x2000 0x10&gt;;</div><div class='add'>+			reg-names = "nand", "nand-int-base";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			nandcs: nand@0 {</div><div class='add'>+				compatible = "brcm,nandcs";</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* B0 AHB Peripherals */</div><div class='add'>+		pl081_dma: dma-controller@11000 {</div><div class='add'>+			compatible = "arm,pl081", "arm,primecell";</div><div class='add'>+			// The magic B105F00D info is missing</div><div class='add'>+			arm,primecell-periphid = &lt;0x00041081&gt;;</div><div class='add'>+			reg = &lt;0x11000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			memcpy-burst-size = &lt;256&gt;;</div><div class='add'>+			memcpy-bus-width = &lt;32&gt;;</div><div class='add'>+			clocks = &lt;&amp;periph_clk&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			#dma-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* B0 ARM UART Peripheral block */</div><div class='add'>+		uart0: serial@12000 {</div><div class='add'>+			compatible = "arm,pl011", "arm,primecell";</div><div class='add'>+			reg = &lt;0x12000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;uart_clk&gt;, &lt;&amp;uart_clk&gt;;</div><div class='add'>+			clock-names = "uartclk", "apb_pclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart1: serial@13000 {</div><div class='add'>+			compatible = "arm,pl011", "arm,primecell";</div><div class='add'>+			reg = &lt;0x13000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;uart_clk&gt;, &lt;&amp;uart_clk&gt;;</div><div class='add'>+			clock-names = "uartclk", "apb_pclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart2: serial@14000 {</div><div class='add'>+			compatible = "arm,pl011", "arm,primecell";</div><div class='add'>+			reg = &lt;0x14000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;uart_clk&gt;, &lt;&amp;uart_clk&gt;;</div><div class='add'>+			clock-names = "uartclk", "apb_pclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi<br/>new file mode 100644<br/>index 000000000000..1d1303cf90f3<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi</a></div><div class='hunk'>@@ -0,0 +1,164 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Broadcom Ltd.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "brcm,bcm6813", "brcm,bcmbca";</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		B53_0: cpu@0 {</div><div class='add'>+			compatible = "brcm,brahma-b53";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x0&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		B53_1: cpu@1 {</div><div class='add'>+			compatible = "brcm,brahma-b53";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x1&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		B53_2: cpu@2 {</div><div class='add'>+			compatible = "brcm,brahma-b53";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x2&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		B53_3: cpu@3 {</div><div class='add'>+			compatible = "brcm,brahma-b53";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x3&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		L2_0: l2-cache0 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			&lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			&lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			&lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu: pmu {</div><div class='add'>+		compatible = "arm,cortex-a53-pmu";</div><div class='add'>+		interrupts = &lt;GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			&lt;GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			&lt;GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			&lt;GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-affinity = &lt;&amp;B53_0&gt;, &lt;&amp;B53_1&gt;,</div><div class='add'>+			&lt;&amp;B53_2&gt;, &lt;&amp;B53_3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clocks: clocks {</div><div class='add'>+		periph_clk: periph-clk {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-frequency = &lt;200000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart_clk: uart-clk {</div><div class='add'>+			compatible = "fixed-factor-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clocks = &lt;&amp;periph_clk&gt;;</div><div class='add'>+			clock-div = &lt;4&gt;;</div><div class='add'>+			clock-mult = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		hsspi_pll: hsspi-pll {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-frequency = &lt;200000000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-0.2";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	axi@81000000 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges = &lt;0x0 0x0 0x81000000 0x8000&gt;;</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@1000 {</div><div class='add'>+			compatible = "arm,gic-400";</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='add'>+			reg = &lt;0x1000 0x1000&gt;,</div><div class='add'>+				&lt;0x2000 0x2000&gt;,</div><div class='add'>+				&lt;0x4000 0x2000&gt;,</div><div class='add'>+				&lt;0x6000 0x2000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bus@ff800000 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges = &lt;0x0 0x0 0xff800000 0x800000&gt;;</div><div class='add'>+</div><div class='add'>+		hsspi: spi@1000 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			compatible = "brcm,bcm6813-hsspi", "brcm,bcmbca-hsspi-v1.1";</div><div class='add'>+			reg = &lt;0x1000 0x600&gt;, &lt;0x2610 0x4&gt;;</div><div class='add'>+			reg-names = "hsspi", "spim-ctrl";</div><div class='add'>+			interrupts = &lt;GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;hsspi_pll &amp;hsspi_pll&gt;;</div><div class='add'>+			clock-names = "hsspi", "pll";</div><div class='add'>+			num-cs = &lt;8&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nand_controller: nand-controller@1800 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";</div><div class='add'>+			reg = &lt;0x1800 0x600&gt;, &lt;0x2000 0x10&gt;;</div><div class='add'>+			reg-names = "nand", "nand-int-base";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			nandcs: nand@0 {</div><div class='add'>+				compatible = "brcm,nandcs";</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart0: serial@12000 {</div><div class='add'>+			compatible = "arm,pl011", "arm,primecell";</div><div class='add'>+			reg = &lt;0x12000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;uart_clk&gt;, &lt;&amp;uart_clk&gt;;</div><div class='add'>+			clock-names = "uartclk", "apb_pclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi<br/>new file mode 100644<br/>index 000000000000..dcbd0fdd33d2<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi</a></div><div class='hunk'>@@ -0,0 +1,265 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Broadcom Ltd.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "brcm,bcm6856", "brcm,bcmbca";</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		B53_0: cpu@0 {</div><div class='add'>+			compatible = "brcm,brahma-b53";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x0&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		B53_1: cpu@1 {</div><div class='add'>+			compatible = "brcm,brahma-b53";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x1&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		L2_0: l2-cache0 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			&lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			&lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			&lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu: pmu {</div><div class='add'>+		compatible = "arm,cortex-a53-pmu";</div><div class='add'>+		interrupts = &lt;GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			&lt;GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-affinity = &lt;&amp;B53_0&gt;, &lt;&amp;B53_1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clocks: clocks {</div><div class='add'>+		periph_clk:periph-clk {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-frequency = &lt;200000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		hsspi_pll: hsspi-pll {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-frequency = &lt;400000000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-0.2";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	axi@81000000 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges = &lt;0x0 0x0 0x81000000 0x8000&gt;;</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@1000 {</div><div class='add'>+			compatible = "arm,gic-400";</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			reg = &lt;0x1000 0x1000&gt;, /* GICD */</div><div class='add'>+				&lt;0x2000 0x2000&gt;, /* GICC */</div><div class='add'>+				&lt;0x4000 0x2000&gt;, /* GICH */</div><div class='add'>+				&lt;0x6000 0x2000&gt;; /* GICV */</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |</div><div class='add'>+					IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PERF Peripherals */</div><div class='add'>+	bus@ff800000 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges = &lt;0x0 0x0 0xff800000 0x400000&gt;;</div><div class='add'>+</div><div class='add'>+		watchdog@480 {</div><div class='add'>+			compatible = "brcm,bcm6345-wdt";</div><div class='add'>+			reg = &lt;0x480 0x10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		watchdog@4c0 {</div><div class='add'>+			compatible = "brcm,bcm6345-wdt";</div><div class='add'>+			reg = &lt;0x4c0 0x10&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* GPIOs 0 .. 31 */</div><div class='add'>+		gpio0: gpio@500 {</div><div class='add'>+			compatible = "brcm,bcm6345-gpio";</div><div class='add'>+			reg = &lt;0x500 0x04&gt;, &lt;0x520 0x04&gt;;</div><div class='add'>+			reg-names = "dirout", "dat";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* GPIOs 32 .. 63 */</div><div class='add'>+		gpio1: gpio@504 {</div><div class='add'>+			compatible = "brcm,bcm6345-gpio";</div><div class='add'>+			reg = &lt;0x504 0x04&gt;, &lt;0x524 0x04&gt;;</div><div class='add'>+			reg-names = "dirout", "dat";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* GPIOs 64 .. 95 */</div><div class='add'>+		gpio2: gpio@508 {</div><div class='add'>+			compatible = "brcm,bcm6345-gpio";</div><div class='add'>+			reg = &lt;0x508 0x04&gt;, &lt;0x528 0x04&gt;;</div><div class='add'>+			reg-names = "dirout", "dat";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* GPIOs 96 .. 127 */</div><div class='add'>+		gpio3: gpio@50c {</div><div class='add'>+			compatible = "brcm,bcm6345-gpio";</div><div class='add'>+			reg = &lt;0x50c 0x04&gt;, &lt;0x52c 0x04&gt;;</div><div class='add'>+			reg-names = "dirout", "dat";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* GPIOs 128 .. 159 */</div><div class='add'>+		gpio4: gpio@510 {</div><div class='add'>+			compatible = "brcm,bcm6345-gpio";</div><div class='add'>+			reg = &lt;0x510 0x04&gt;, &lt;0x530 0x04&gt;;</div><div class='add'>+			reg-names = "dirout", "dat";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* GPIOs 160 .. 191 */</div><div class='add'>+		gpio5: gpio@514 {</div><div class='add'>+			compatible = "brcm,bcm6345-gpio";</div><div class='add'>+			reg = &lt;0x514 0x04&gt;, &lt;0x534 0x04&gt;;</div><div class='add'>+			reg-names = "dirout", "dat";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* GPIOs 192 .. 223 */</div><div class='add'>+		gpio6: gpio@518 {</div><div class='add'>+			compatible = "brcm,bcm6345-gpio";</div><div class='add'>+			reg = &lt;0x518 0x04&gt;, &lt;0x538 0x04&gt;;</div><div class='add'>+			reg-names = "dirout", "dat";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* GPIOs 224 .. 255 */</div><div class='add'>+		gpio7: gpio@51c {</div><div class='add'>+			compatible = "brcm,bcm6345-gpio";</div><div class='add'>+			reg = &lt;0x51c 0x04&gt;, &lt;0x53c 0x04&gt;;</div><div class='add'>+			reg-names = "dirout", "dat";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart0: serial@640 {</div><div class='add'>+			compatible = "brcm,bcm6345-uart";</div><div class='add'>+			reg = &lt;0x640 0x18&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;periph_clk&gt;;</div><div class='add'>+			clock-names = "refclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart1: serial@660 {</div><div class='add'>+			compatible = "brcm,bcm6345-uart";</div><div class='add'>+			reg = &lt;0x660 0x18&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;periph_clk&gt;;</div><div class='add'>+			clock-names = "refclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		leds: led-controller@800 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			compatible = "brcm,bcm63138-leds";</div><div class='add'>+			reg = &lt;0x800 0xdc&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rng@b80 {</div><div class='add'>+			compatible = "brcm,iproc-rng200";</div><div class='add'>+			reg = &lt;0xb80 0x28&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		hsspi: spi@1000 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			compatible = "brcm,bcm6856-hsspi", "brcm,bcmbca-hsspi-v1.0";</div><div class='add'>+			reg = &lt;0x1000 0x600&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;hsspi_pll &amp;hsspi_pll&gt;;</div><div class='add'>+			clock-names = "hsspi", "pll";</div><div class='add'>+			num-cs = &lt;8&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nand_controller: nand-controller@1800 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";</div><div class='add'>+			reg = &lt;0x1800 0x600&gt;, &lt;0x2000 0x10&gt;;</div><div class='add'>+			reg-names = "nand", "nand-int-base";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			nandcs: nand@0 {</div><div class='add'>+				compatible = "brcm,nandcs";</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pl081_dma: dma-controller@59000 {</div><div class='add'>+			compatible = "arm,pl081", "arm,primecell";</div><div class='add'>+			// The magic B105F00D info is missing</div><div class='add'>+			arm,primecell-periphid = &lt;0x00041081&gt;;</div><div class='add'>+			reg = &lt;0x59000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			memcpy-burst-size = &lt;256&gt;;</div><div class='add'>+			memcpy-bus-width = &lt;32&gt;;</div><div class='add'>+			clocks = &lt;&amp;periph_clk&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			#dma-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi<br/>new file mode 100644<br/>index 000000000000..c105a734a648<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi</a></div><div class='hunk'>@@ -0,0 +1,291 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Broadcom Ltd.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "brcm,bcm6858", "brcm,bcmbca";</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		B53_0: cpu@0 {</div><div class='add'>+			compatible = "brcm,brahma-b53";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x0&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		B53_1: cpu@1 {</div><div class='add'>+			compatible = "brcm,brahma-b53";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x1&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		B53_2: cpu@2 {</div><div class='add'>+			compatible = "brcm,brahma-b53";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x2&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		B53_3: cpu@3 {</div><div class='add'>+			compatible = "brcm,brahma-b53";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0 0x3&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+		L2_0: l2-cache0 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			&lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			&lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			&lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu: pmu {</div><div class='add'>+		compatible = "arm,armv8-pmuv3";</div><div class='add'>+		interrupts = &lt;GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			&lt;GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			&lt;GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			&lt;GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-affinity = &lt;&amp;B53_0&gt;, &lt;&amp;B53_1&gt;,</div><div class='add'>+			&lt;&amp;B53_2&gt;, &lt;&amp;B53_3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clocks: clocks {</div><div class='add'>+		periph_clk:periph-clk {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-frequency = &lt;200000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		hsspi_pll: hsspi-pll {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-frequency = &lt;400000000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-0.2";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	axi@81000000 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges = &lt;0x0 0x0 0x81000000 0x8000&gt;;</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@1000 {</div><div class='add'>+			compatible = "arm,gic-400";</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			reg = &lt;0x1000 0x1000&gt;, /* GICD */</div><div class='add'>+				&lt;0x2000 0x2000&gt;, /* GICC */</div><div class='add'>+				&lt;0x4000 0x2000&gt;, /* GICH */</div><div class='add'>+				&lt;0x6000 0x2000&gt;; /* GICV */</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |</div><div class='add'>+					IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PERF Peripherals */</div><div class='add'>+	bus@ff800000 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges = &lt;0x0 0x0 0xff800000 0x400000&gt;;</div><div class='add'>+</div><div class='add'>+		twd: timer-mfd@400 {</div><div class='add'>+			compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon";</div><div class='add'>+			reg = &lt;0x400 0x4c&gt;;</div><div class='add'>+			ranges = &lt;0x0 0x400 0x4c&gt;;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			timer@0 {</div><div class='add'>+				compatible = "brcm,bcm63138-timer";</div><div class='add'>+				reg = &lt;0x0 0x28&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			watchdog@28 {</div><div class='add'>+				compatible = "brcm,bcm6345-wdt";</div><div class='add'>+				reg = &lt;0x28 0x8&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* GPIOs 0 .. 31 */</div><div class='add'>+		gpio0: gpio@500 {</div><div class='add'>+			compatible = "brcm,bcm6345-gpio";</div><div class='add'>+			reg = &lt;0x500 0x04&gt;, &lt;0x520 0x04&gt;;</div><div class='add'>+			reg-names = "dirout", "dat";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* GPIOs 32 .. 63 */</div><div class='add'>+		gpio1: gpio@504 {</div><div class='add'>+			compatible = "brcm,bcm6345-gpio";</div><div class='add'>+			reg = &lt;0x504 0x04&gt;, &lt;0x524 0x04&gt;;</div><div class='add'>+			reg-names = "dirout", "dat";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* GPIOs 64 .. 95 */</div><div class='add'>+		gpio2: gpio@508 {</div><div class='add'>+			compatible = "brcm,bcm6345-gpio";</div><div class='add'>+			reg = &lt;0x508 0x04&gt;, &lt;0x528 0x04&gt;;</div><div class='add'>+			reg-names = "dirout", "dat";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* GPIOs 96 .. 127 */</div><div class='add'>+		gpio3: gpio@50c {</div><div class='add'>+			compatible = "brcm,bcm6345-gpio";</div><div class='add'>+			reg = &lt;0x50c 0x04&gt;, &lt;0x52c 0x04&gt;;</div><div class='add'>+			reg-names = "dirout", "dat";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* GPIOs 128 .. 159 */</div><div class='add'>+		gpio4: gpio@510 {</div><div class='add'>+			compatible = "brcm,bcm6345-gpio";</div><div class='add'>+			reg = &lt;0x510 0x04&gt;, &lt;0x530 0x04&gt;;</div><div class='add'>+			reg-names = "dirout", "dat";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* GPIOs 160 .. 191 */</div><div class='add'>+		gpio5: gpio@514 {</div><div class='add'>+			compatible = "brcm,bcm6345-gpio";</div><div class='add'>+			reg = &lt;0x514 0x04&gt;, &lt;0x534 0x04&gt;;</div><div class='add'>+			reg-names = "dirout", "dat";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* GPIOs 192 .. 223 */</div><div class='add'>+		gpio6: gpio@518 {</div><div class='add'>+			compatible = "brcm,bcm6345-gpio";</div><div class='add'>+			reg = &lt;0x518 0x04&gt;, &lt;0x538 0x04&gt;;</div><div class='add'>+			reg-names = "dirout", "dat";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* GPIOs 224 .. 255 */</div><div class='add'>+		gpio7: gpio@51c {</div><div class='add'>+			compatible = "brcm,bcm6345-gpio";</div><div class='add'>+			reg = &lt;0x51c 0x04&gt;, &lt;0x53c 0x04&gt;;</div><div class='add'>+			reg-names = "dirout", "dat";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart0: serial@640 {</div><div class='add'>+			compatible = "brcm,bcm6345-uart";</div><div class='add'>+			reg = &lt;0x640 0x18&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;periph_clk&gt;;</div><div class='add'>+			clock-names = "refclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart1: serial@660 {</div><div class='add'>+			compatible = "brcm,bcm6345-uart";</div><div class='add'>+			reg = &lt;0x660 0x18&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;periph_clk&gt;;</div><div class='add'>+			clock-names = "refclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		leds: led-controller@800 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			compatible = "brcm,bcm63138-leds";</div><div class='add'>+			reg = &lt;0x800 0xdc&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rng@b80 {</div><div class='add'>+			compatible = "brcm,iproc-rng200";</div><div class='add'>+			reg = &lt;0xb80 0x28&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		hsspi: spi@1000 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			compatible = "brcm,bcm6858-hsspi", "brcm,bcmbca-hsspi-v1.0";</div><div class='add'>+			reg = &lt;0x1000 0x600&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;hsspi_pll &amp;hsspi_pll&gt;;</div><div class='add'>+			clock-names = "hsspi", "pll";</div><div class='add'>+			num-cs = &lt;8&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nand_controller: nand-controller@1800 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";</div><div class='add'>+			reg = &lt;0x1800 0x600&gt;, &lt;0x2000 0x10&gt;;</div><div class='add'>+			reg-names = "nand", "nand-int-base";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			nandcs: nand@0 {</div><div class='add'>+				compatible = "brcm,nandcs";</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pl081_dma: dma-controller@59000 {</div><div class='add'>+			compatible = "arm,pl081", "arm,primecell";</div><div class='add'>+			// The magic B105F00D info is missing</div><div class='add'>+			arm,primecell-periphid = &lt;0x00041081&gt;;</div><div class='add'>+			reg = &lt;0x59000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			memcpy-burst-size = &lt;256&gt;;</div><div class='add'>+			memcpy-bus-width = &lt;32&gt;;</div><div class='add'>+			clocks = &lt;&amp;periph_clk&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			#dma-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts<br/>new file mode 100644<br/>index 000000000000..e5b37643296b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts</a></div><div class='hunk'>@@ -0,0 +1,43 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Broadcom Ltd.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "bcm4908.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Broadcom BCM94908 Reference Board";</div><div class='add'>+	compatible = "brcm,bcm94908", "brcm,bcm4908", "brcm,bcmbca";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x0 0x0 0x08000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hsspi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;nand_controller {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;nandcs {</div><div class='add'>+	nand-on-flash-bbt;</div><div class='add'>+	brcm,nand-ecc-use-strap;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts<br/>new file mode 100644<br/>index 000000000000..4b779e6c22e1<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts</a></div><div class='hunk'>@@ -0,0 +1,44 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Broadcom Ltd.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "bcm4912.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Broadcom BCM94912 Reference Board";</div><div class='add'>+	compatible = "brcm,bcm94912", "brcm,bcm4912", "brcm,bcmbca";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x0 0x0 0x08000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hsspi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;nand_controller {</div><div class='add'>+	brcm,wp-not-connected;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;nandcs {</div><div class='add'>+	nand-on-flash-bbt;</div><div class='add'>+	brcm,nand-ecc-use-strap;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts<br/>new file mode 100644<br/>index 000000000000..2851e8e41bf4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts</a></div><div class='hunk'>@@ -0,0 +1,44 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Broadcom Ltd.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "bcm63146.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Broadcom BCM963146 Reference Board";</div><div class='add'>+	compatible = "brcm,bcm963146", "brcm,bcm63146", "brcm,bcmbca";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x0 0x0 0x08000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hsspi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;nand_controller {</div><div class='add'>+	brcm,wp-not-connected;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;nandcs {</div><div class='add'>+	nand-on-flash-bbt;</div><div class='add'>+	brcm,nand-ecc-use-strap;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts<br/>new file mode 100644<br/>index 000000000000..17dc594fe83f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts</a></div><div class='hunk'>@@ -0,0 +1,44 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Broadcom Ltd.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "bcm63158.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Broadcom BCM963158 Reference Board";</div><div class='add'>+	compatible = "brcm,bcm963158", "brcm,bcm63158", "brcm,bcmbca";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x0 0x0 0x08000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hsspi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;nand_controller {</div><div class='add'>+	brcm,wp-not-connected;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;nandcs {</div><div class='add'>+	nand-on-flash-bbt;</div><div class='add'>+	brcm,nand-ecc-use-strap;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts<br/>new file mode 100644<br/>index 000000000000..34832a734734<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts</a></div><div class='hunk'>@@ -0,0 +1,44 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Broadcom Ltd.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "bcm6813.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Broadcom BCM96813 Reference Board";</div><div class='add'>+	compatible = "brcm,bcm96813", "brcm,bcm6813", "brcm,bcmbca";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x0 0x0 0x08000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hsspi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;nand_controller {</div><div class='add'>+	brcm,wp-not-connected;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;nandcs {</div><div class='add'>+	nand-on-flash-bbt;</div><div class='add'>+	brcm,nand-ecc-use-strap;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts<br/>new file mode 100644<br/>index 000000000000..e1396b5544b7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts</a></div><div class='hunk'>@@ -0,0 +1,44 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Broadcom Ltd.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "bcm6856.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Broadcom BCM96856 Reference Board";</div><div class='add'>+	compatible = "brcm,bcm96856", "brcm,bcm6856", "brcm,bcmbca";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x0 0x0 0x08000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hsspi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;nand_controller {</div><div class='add'>+	brcm,wp-not-connected;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;nandcs {</div><div class='add'>+	nand-on-flash-bbt;</div><div class='add'>+	brcm,nand-ecc-use-strap;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts<br/>new file mode 100644<br/>index 000000000000..30bbf6f2917e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts</a></div><div class='hunk'>@@ -0,0 +1,44 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Broadcom Ltd.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "bcm6858.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Broadcom BCM96858 Reference Board";</div><div class='add'>+	compatible = "brcm,bcm96858", "brcm,bcm6858", "brcm,bcmbca";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x0 0x0 0x08000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hsspi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;nand_controller {</div><div class='add'>+	brcm,wp-not-connected;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;nandcs {</div><div class='add'>+	nand-on-flash-bbt;</div><div class='add'>+	brcm,nand-ecc-use-strap;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts<br/>index ec19fbf928a1..5939d342aec7 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts</a></div><div class='hunk'>@@ -50,9 +50,9 @@</div><div class='ctx'> 		bootargs = "earlycon=uart8250,mmio32,0x66130000";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	memory {</div><div class='add'>+	memory@80000000 {</div><div class='ctx'> 		device_type = "memory";</div><div class='del'>-		reg = &lt;0x000000000 0x80000000 0x00000000 0x40000000&gt;;</div><div class='add'>+		reg = &lt;0x00000000 0x80000000 0x00000000 0x40000000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -111,9 +111,8 @@</div><div class='ctx'> 		compatible = "silabs,si3226x";</div><div class='ctx'> 		reg = &lt;0&gt;;</div><div class='ctx'> 		spi-max-frequency = &lt;5000000&gt;;</div><div class='del'>-		spi-cpha = &lt;1&gt;;</div><div class='del'>-		spi-cpol = &lt;1&gt;;</div><div class='del'>-		pl022,hierarchy = &lt;0&gt;;</div><div class='add'>+		spi-cpha;</div><div class='add'>+		spi-cpol;</div><div class='ctx'> 		pl022,interface = &lt;0&gt;;</div><div class='ctx'> 		pl022,slave-tx-disable = &lt;0&gt;;</div><div class='ctx'> 		pl022,com-mode = &lt;0&gt;;</div><div class='hunk'>@@ -135,11 +134,9 @@</div><div class='ctx'> 		at25,byte-len = &lt;0x8000&gt;;</div><div class='ctx'> 		at25,addr-mode = &lt;2&gt;;</div><div class='ctx'> 		at25,page-size = &lt;64&gt;;</div><div class='del'>-		spi-cpha = &lt;1&gt;;</div><div class='del'>-		spi-cpol = &lt;1&gt;;</div><div class='del'>-		pl022,hierarchy = &lt;0&gt;;</div><div class='add'>+		spi-cpha;</div><div class='add'>+		spi-cpol;</div><div class='ctx'> 		pl022,interface = &lt;0&gt;;</div><div class='del'>-		pl022,slave-tx-disable = &lt;0&gt;;</div><div class='ctx'> 		pl022,com-mode = &lt;0&gt;;</div><div class='ctx'> 		pl022,rx-level-trig = &lt;1&gt;;</div><div class='ctx'> 		pl022,tx-level-trig = &lt;1&gt;;</div><div class='hunk'>@@ -202,8 +199,7 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;qspi {</div><div class='del'>-	bspi-sel = &lt;0&gt;;</div><div class='del'>-	flash: m25p80@0 {</div><div class='add'>+	flash: flash@0 {</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;1&gt;;</div><div class='ctx'> 		compatible = "m25p80";</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts b/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts<br/>index f00c21e0767e..0e134a94e142 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts</a></div><div class='hunk'>@@ -47,9 +47,9 @@</div><div class='ctx'> 		bootargs = "earlycon=uart8250,mmio32,0x66130000";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	memory {</div><div class='add'>+	memory@80000000 {</div><div class='ctx'> 		device_type = "memory";</div><div class='del'>-		reg = &lt;0x000000000 0x80000000 0x00000001 0x00000000&gt;;</div><div class='add'>+		reg = &lt;0x00000000 0x80000000 0x00000001 0x00000000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -114,7 +114,7 @@</div><div class='ctx'> 			reg = &lt;0x04000000 0x06400000&gt;; /*  100MB */</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		partition@a400000{</div><div class='add'>+		partition@a400000 {</div><div class='ctx'> 			label = "ncustfs";</div><div class='ctx'> 			reg = &lt;0x0a400000 0x35c00000&gt;; /*  860MB */</div><div class='ctx'> 		};</div><div class='hunk'>@@ -146,12 +146,11 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;qspi {</div><div class='del'>-	flash: m25p80@0 {</div><div class='add'>+	flash: flash@0 {</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;1&gt;;</div><div class='ctx'> 		compatible = "m25p80";</div><div class='ctx'> 		spi-max-frequency = &lt;62500000&gt;;</div><div class='del'>-		m25p,default-addr-width = &lt;3&gt;;</div><div class='ctx'> 		reg = &lt;0x0 0x0&gt;;</div><div class='ctx'> </div><div class='ctx'> 		partition@0 {</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi<br/>index 15f7b0ed3836..9888a1fabd5c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi</a></div><div class='hunk'>@@ -79,6 +79,8 @@</div><div class='ctx'> </div><div class='ctx'> 		CLUSTER0_L2: l2-cache@0 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -100,7 +102,7 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	pmu {</div><div class='del'>-		compatible = "arm,armv8-pmuv3";</div><div class='add'>+		compatible = "arm,cortex-a57-pmu";</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 			     &lt;GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 			     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='hunk'>@@ -132,7 +134,6 @@</div><div class='ctx'> 		brcm,pcie-ob;</div><div class='ctx'> 		brcm,pcie-ob-oarr-size;</div><div class='ctx'> 		brcm,pcie-ob-axi-offset = &lt;0x00000000&gt;;</div><div class='del'>-		brcm,pcie-ob-window-size = &lt;256&gt;;</div><div class='ctx'> </div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> </div><div class='hunk'>@@ -163,7 +164,6 @@</div><div class='ctx'> 		brcm,pcie-ob;</div><div class='ctx'> 		brcm,pcie-ob-oarr-size;</div><div class='ctx'> 		brcm,pcie-ob-axi-offset = &lt;0x30000000&gt;;</div><div class='del'>-		brcm,pcie-ob-window-size = &lt;256&gt;;</div><div class='ctx'> </div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> </div><div class='hunk'>@@ -276,7 +276,7 @@</div><div class='ctx'> 			mboxes = &lt;&amp;pdc3 0&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		dma0: dma@61360000 {</div><div class='add'>+		dma0: dma-controller@61360000 {</div><div class='ctx'> 			compatible = "arm,pl330", "arm,primecell";</div><div class='ctx'> 			reg = &lt;0x61360000 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='hunk'>@@ -289,13 +289,11 @@</div><div class='ctx'> 				     &lt;GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 				     &lt;GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			#dma-cells = &lt;1&gt;;</div><div class='del'>-			#dma-channels = &lt;8&gt;;</div><div class='del'>-			#dma-requests = &lt;32&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;iprocslow&gt;;</div><div class='ctx'> 			clock-names = "apb_pclk";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		smmu: mmu@64000000 {</div><div class='add'>+		smmu: iommu@64000000 {</div><div class='ctx'> 			compatible = "arm,mmu-500";</div><div class='ctx'> 			reg = &lt;0x64000000 0x40000&gt;;</div><div class='ctx'> 			#global-interrupts = &lt;2&gt;;</div><div class='hunk'>@@ -369,7 +367,6 @@</div><div class='ctx'> </div><div class='ctx'> 			v2m0: v2m@0 {</div><div class='ctx'> 				compatible = "arm,gic-v2m-frame";</div><div class='del'>-				interrupt-parent = &lt;&amp;gic&gt;;</div><div class='ctx'> 				msi-controller;</div><div class='ctx'> 				reg = &lt;0x00000 0x1000&gt;;</div><div class='ctx'> 				arm,msi-base-spi = &lt;72&gt;;</div><div class='hunk'>@@ -378,7 +375,6 @@</div><div class='ctx'> </div><div class='ctx'> 			v2m1: v2m@10000 {</div><div class='ctx'> 				compatible = "arm,gic-v2m-frame";</div><div class='del'>-				interrupt-parent = &lt;&amp;gic&gt;;</div><div class='ctx'> 				msi-controller;</div><div class='ctx'> 				reg = &lt;0x10000 0x1000&gt;;</div><div class='ctx'> 				arm,msi-base-spi = &lt;88&gt;;</div><div class='hunk'>@@ -387,7 +383,6 @@</div><div class='ctx'> </div><div class='ctx'> 			v2m2: v2m@20000 {</div><div class='ctx'> 				compatible = "arm,gic-v2m-frame";</div><div class='del'>-				interrupt-parent = &lt;&amp;gic&gt;;</div><div class='ctx'> 				msi-controller;</div><div class='ctx'> 				reg = &lt;0x20000 0x1000&gt;;</div><div class='ctx'> 				arm,msi-base-spi = &lt;104&gt;;</div><div class='hunk'>@@ -396,7 +391,6 @@</div><div class='ctx'> </div><div class='ctx'> 			v2m3: v2m@30000 {</div><div class='ctx'> 				compatible = "arm,gic-v2m-frame";</div><div class='del'>-				interrupt-parent = &lt;&amp;gic&gt;;</div><div class='ctx'> 				msi-controller;</div><div class='ctx'> 				reg = &lt;0x30000 0x1000&gt;;</div><div class='ctx'> 				arm,msi-base-spi = &lt;120&gt;;</div><div class='hunk'>@@ -405,7 +399,6 @@</div><div class='ctx'> </div><div class='ctx'> 			v2m4: v2m@40000 {</div><div class='ctx'> 				compatible = "arm,gic-v2m-frame";</div><div class='del'>-				interrupt-parent = &lt;&amp;gic&gt;;</div><div class='ctx'> 				msi-controller;</div><div class='ctx'> 				reg = &lt;0x40000 0x1000&gt;;</div><div class='ctx'> 				arm,msi-base-spi = &lt;136&gt;;</div><div class='hunk'>@@ -414,7 +407,6 @@</div><div class='ctx'> </div><div class='ctx'> 			v2m5: v2m@50000 {</div><div class='ctx'> 				compatible = "arm,gic-v2m-frame";</div><div class='del'>-				interrupt-parent = &lt;&amp;gic&gt;;</div><div class='ctx'> 				msi-controller;</div><div class='ctx'> 				reg = &lt;0x50000 0x1000&gt;;</div><div class='ctx'> 				arm,msi-base-spi = &lt;152&gt;;</div><div class='hunk'>@@ -423,7 +415,6 @@</div><div class='ctx'> </div><div class='ctx'> 			v2m6: v2m@60000 {</div><div class='ctx'> 				compatible = "arm,gic-v2m-frame";</div><div class='del'>-				interrupt-parent = &lt;&amp;gic&gt;;</div><div class='ctx'> 				msi-controller;</div><div class='ctx'> 				reg = &lt;0x60000 0x1000&gt;;</div><div class='ctx'> 				arm,msi-base-spi = &lt;168&gt;;</div><div class='hunk'>@@ -432,7 +423,6 @@</div><div class='ctx'> </div><div class='ctx'> 			v2m7: v2m@70000 {</div><div class='ctx'> 				compatible = "arm,gic-v2m-frame";</div><div class='del'>-				interrupt-parent = &lt;&amp;gic&gt;;</div><div class='ctx'> 				msi-controller;</div><div class='ctx'> 				reg = &lt;0x70000 0x1000&gt;;</div><div class='ctx'> 				arm,msi-base-spi = &lt;184&gt;;</div><div class='hunk'>@@ -576,7 +566,7 @@</div><div class='ctx'> 			reg = &lt;0x66090000 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;iprocslow&gt;, &lt;&amp;iprocslow&gt;;</div><div class='del'>-			clock-names = "wdogclk", "apb_pclk";</div><div class='add'>+			clock-names = "wdog_clk", "apb_pclk";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		gpio_g: gpio@660a0000 {</div><div class='hunk'>@@ -586,6 +576,7 @@</div><div class='ctx'> 			#gpio-cells = &lt;2&gt;;</div><div class='ctx'> 			gpio-controller;</div><div class='ctx'> 			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -644,7 +635,7 @@</div><div class='ctx'> 			reg = &lt;0x66180000 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;iprocslow&gt;, &lt;&amp;iprocslow&gt;;</div><div class='del'>-			clock-names = "spiclk", "apb_pclk";</div><div class='add'>+			clock-names = "sspclk", "apb_pclk";</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='hunk'>@@ -655,7 +646,7 @@</div><div class='ctx'> 			reg = &lt;0x66190000 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;iprocslow&gt;, &lt;&amp;iprocslow&gt;;</div><div class='del'>-			clock-names = "spiclk", "apb_pclk";</div><div class='add'>+			clock-names = "sspclk", "apb_pclk";</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='hunk'>@@ -687,7 +678,7 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		sata: ahci@663f2000 {</div><div class='add'>+		sata: sata@663f2000 {</div><div class='ctx'> 			compatible = "brcm,iproc-ahci", "generic-ahci";</div><div class='ctx'> 			reg = &lt;0x663f2000 0x1000&gt;;</div><div class='ctx'> 			dma-coherent;</div><div class='hunk'>@@ -745,7 +736,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		qspi: spi@66470200 {</div><div class='del'>-			compatible = "brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi";</div><div class='add'>+			compatible = "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi";</div><div class='ctx'> 			reg = &lt;0x66470200 0x184&gt;,</div><div class='ctx'> 				&lt;0x66470000 0x124&gt;,</div><div class='ctx'> 				&lt;0x67017408 0x004&gt;,</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/rp1-common.dtsi b/arch/arm64/boot/dts/broadcom/rp1-common.dtsi<br/>new file mode 100644<br/>index 000000000000..5a815c379794<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/rp1-common.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/rp1-common.dtsi</a></div><div class='hunk'>@@ -0,0 +1,86 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/raspberrypi,rp1-clocks.h&gt;</div><div class='add'>+</div><div class='add'>+pci_ep_bus: pci-ep-bus@1 {</div><div class='add'>+	compatible = "simple-bus";</div><div class='add'>+	ranges = &lt;0x00 0x40000000  0x01 0x00 0x00000000  0x00 0x00400000&gt;;</div><div class='add'>+	dma-ranges = &lt;0x10 0x00000000  0x43000000 0x10 0x00000000  0x10 0x00000000&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	rp1_clocks: clocks@40018000 {</div><div class='add'>+		compatible = "raspberrypi,rp1-clocks";</div><div class='add'>+		reg = &lt;0x00 0x40018000 0x0 0x10038&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk_rp1_xosc&gt;;</div><div class='add'>+		assigned-clocks = &lt;&amp;rp1_clocks RP1_PLL_SYS_CORE&gt;,</div><div class='add'>+				  &lt;&amp;rp1_clocks RP1_PLL_SYS&gt;,</div><div class='add'>+				  &lt;&amp;rp1_clocks RP1_PLL_SYS_SEC&gt;,</div><div class='add'>+				  &lt;&amp;rp1_clocks RP1_CLK_SYS&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;1000000000&gt;, // RP1_PLL_SYS_CORE</div><div class='add'>+				       &lt;200000000&gt;,  // RP1_PLL_SYS</div><div class='add'>+				       &lt;125000000&gt;,  // RP1_PLL_SYS_SEC</div><div class='add'>+				       &lt;200000000&gt;;  // RP1_CLK_SYS</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rp1_gpio: pinctrl@400d0000 {</div><div class='add'>+		compatible = "raspberrypi,rp1-gpio";</div><div class='add'>+		reg = &lt;0x00 0x400d0000  0x0 0xc000&gt;,</div><div class='add'>+		      &lt;0x00 0x400e0000  0x0 0xc000&gt;,</div><div class='add'>+		      &lt;0x00 0x400f0000  0x0 0xc000&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupts = &lt;0 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;1 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;2 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rp1_eth: ethernet@40100000 {</div><div class='add'>+		compatible = "raspberrypi,rp1-gem";</div><div class='add'>+		reg = &lt;0x00 0x40100000  0x0 0x4000&gt;;</div><div class='add'>+		interrupts = &lt;6 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;rp1_clocks RP1_CLK_SYS&gt;,</div><div class='add'>+			 &lt;&amp;rp1_clocks RP1_CLK_SYS&gt;,</div><div class='add'>+			 &lt;&amp;rp1_clocks RP1_CLK_ETH&gt;,</div><div class='add'>+			 &lt;&amp;rp1_clocks RP1_CLK_ETH_TSU&gt;;</div><div class='add'>+		clock-names = "pclk", "hclk", "tx_clk", "tsu_clk";</div><div class='add'>+		local-mac-address = [00 00 00 00 00 00];</div><div class='add'>+		status = "disabled";</div><div class='add'>+</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rp1_usb0: usb@40200000 {</div><div class='add'>+		compatible = "snps,dwc3";</div><div class='add'>+		reg = &lt;0x00 0x40200000  0x0 0x100000&gt;;</div><div class='add'>+		interrupts = &lt;31 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+		dr_mode = "host";</div><div class='add'>+		usb3-lpm-capable;</div><div class='add'>+		snps,dis_rxdet_inp3_quirk;</div><div class='add'>+		snps,parkmode-disable-hs-quirk;</div><div class='add'>+		snps,parkmode-disable-ss-quirk;</div><div class='add'>+		snps,tx-max-burst = /bits/ 8 &lt;8&gt;;</div><div class='add'>+		snps,tx-thr-num-pkt = /bits/ 8 &lt;2&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rp1_usb1: usb@40300000 {</div><div class='add'>+		compatible = "snps,dwc3";</div><div class='add'>+		reg = &lt;0x00 0x40300000  0x0 0x100000&gt;;</div><div class='add'>+		interrupts = &lt;36 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+		dr_mode = "host";</div><div class='add'>+		usb3-lpm-capable;</div><div class='add'>+		snps,dis_rxdet_inp3_quirk;</div><div class='add'>+		snps,parkmode-disable-hs-quirk;</div><div class='add'>+		snps,parkmode-disable-ss-quirk;</div><div class='add'>+		snps,tx-max-burst = /bits/ 8 &lt;8&gt;;</div><div class='add'>+		snps,tx-thr-num-pkt = /bits/ 8 &lt;2&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/rp1-nexus.dtsi b/arch/arm64/boot/dts/broadcom/rp1-nexus.dtsi<br/>new file mode 100644<br/>index 000000000000..0ef30d7f1c35<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/rp1-nexus.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/rp1-nexus.dtsi</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+</div><div class='add'>+rp1_nexus {</div><div class='add'>+	compatible = "pci1de4,1";</div><div class='add'>+	#address-cells = &lt;3&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+	ranges = &lt;0x01 0x00 0x00000000</div><div class='add'>+		  0x02000000 0x00 0x00000000</div><div class='add'>+		  0x0 0x400000&gt;;</div><div class='add'>+	interrupt-controller;</div><div class='add'>+	#interrupt-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	#include "rp1-common.dtsi"</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/rp1.dtso b/arch/arm64/boot/dts/broadcom/rp1.dtso<br/>new file mode 100644<br/>index 000000000000..ab4f146d22c0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/rp1.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/rp1.dtso</a></div><div class='hunk'>@@ -0,0 +1,11 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+&amp;pcie2 {</div><div class='add'>+	#address-cells = &lt;3&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	#include "rp1-nexus.dtsi"</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi b/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi<br/>index a9b92e52d50e..8fe7325cfbb2 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi</a></div><div class='hunk'>@@ -56,70 +56,6 @@</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;sata0 {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;sata_phy0{</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;sata1 {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;sata_phy1{</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;sata2 {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;sata_phy2{</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;sata3 {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;sata_phy3{</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;sata4 {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;sata_phy4{</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;sata5 {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;sata_phy5{</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;sata6 {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;sata_phy6{</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;sata7 {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;sata_phy7{</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> &amp;pwm {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='hunk'>@@ -151,7 +87,7 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;nand {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> 	nandcs@0 {</div><div class='ctx'> 		compatible = "brcm,nandcs";</div><div class='ctx'> 		reg = &lt;0&gt;;</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts b/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts<br/>index 77efa28c4dd5..dfac910a45d6 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts</a></div><div class='hunk'>@@ -61,7 +61,7 @@</div><div class='ctx'> 	cs-gpios = &lt;&amp;gpio_hsls 34 0&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='del'>-	spi-flash@0 {</div><div class='add'>+	flash@0 {</div><div class='ctx'> 		compatible = "jedec,spi-nor";</div><div class='ctx'> 		reg = &lt;0&gt;;</div><div class='ctx'> 		spi-max-frequency = &lt;20000000&gt;;</div><div class='hunk'>@@ -76,7 +76,7 @@</div><div class='ctx'> 	cs-gpios = &lt;&amp;gpio_hsls 96 0&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='del'>-	spi-flash@0 {</div><div class='add'>+	flash@0 {</div><div class='ctx'> 		compatible = "jedec,spi-nor";</div><div class='ctx'> 		reg = &lt;0&gt;;</div><div class='ctx'> 		spi-max-frequency = &lt;20000000&gt;;</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/stingray/bcm958802a802x.dts b/arch/arm64/boot/dts/broadcom/stingray/bcm958802a802x.dts<br/>index a41facd7d79b..66471a25e4ac 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/stingray/bcm958802a802x.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/stingray/bcm958802a802x.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/stingray/bcm958802a802x.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/stingray/bcm958802a802x.dts</a></div><div class='hunk'>@@ -1,4 +1,4 @@</div><div class='del'>-// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause)</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)</div><div class='ctx'> /*</div><div class='ctx'>  *Copyright(c) 2018 Broadcom</div><div class='ctx'>  */</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-board-base.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-board-base.dtsi<br/>index 82a24711d0d8..cdd709491f01 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/stingray/stingray-board-base.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/stingray/stingray-board-base.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/stingray/stingray-board-base.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/stingray/stingray-board-base.dtsi</a></div><div class='hunk'>@@ -1,4 +1,4 @@</div><div class='del'>-// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause)</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)</div><div class='ctx'> /*</div><div class='ctx'>  *  Copyright(c) 2016-2018 Broadcom</div><div class='ctx'>  */</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-pcie.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-pcie.dtsi<br/>index 33a472ab17e8..663e51756746 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/stingray/stingray-pcie.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/stingray/stingray-pcie.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/stingray/stingray-pcie.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/stingray/stingray-pcie.dtsi</a></div><div class='hunk'>@@ -1,4 +1,4 @@</div><div class='del'>-// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause)</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)</div><div class='ctx'> /*</div><div class='ctx'>  *Copyright(c) 2018 Broadcom</div><div class='ctx'>  */</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi<br/>index 56789ccf9454..46a827521921 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi</a></div><div class='hunk'>@@ -44,7 +44,7 @@</div><div class='ctx'> 			compatible = "pinctrl-single";</div><div class='ctx'> 			reg = &lt;0x0014029c 0x26c&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='del'>-			#size-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			pinctrl-single,register-width = &lt;32&gt;;</div><div class='ctx'> 			pinctrl-single,function-mask = &lt;0xf&gt;;</div><div class='ctx'> 			pinctrl-single,gpio-range = &lt;</div><div class='hunk'>@@ -56,14 +56,14 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			/* pinctrl functions */</div><div class='del'>-			tsio_pins: pinmux_gpio_14 {</div><div class='add'>+			tsio_pins: gpio-14-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x038 MODE_NITRO /* tsio_0 */</div><div class='ctx'> 					0x03c MODE_NITRO /* tsio_1 */</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			nor_pins: pinmux_pnor_adv_n {</div><div class='add'>+			nor_pins: pnor-adv-n-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x0ac MODE_PNOR /* nand_ce1_n */</div><div class='ctx'> 					0x0b0 MODE_PNOR /* nand_ce0_n */</div><div class='hunk'>@@ -119,7 +119,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			nand_pins: pinmux_nand_ce1_n {</div><div class='add'>+			nand_pins: nand-ce1-n-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x0ac MODE_NAND /* nand_ce1_n */</div><div class='ctx'> 					0x0b0 MODE_NAND /* nand_ce0_n */</div><div class='hunk'>@@ -148,59 +148,59 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			pwm0_pins: pinmux_pwm_0 {</div><div class='add'>+			pwm0_pins: pwm-0-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x10c MODE_NITRO</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			pwm1_pins: pinmux_pwm_1 {</div><div class='add'>+			pwm1_pins: pwm-1-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x110 MODE_NITRO</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			pwm2_pins: pinmux_pwm_2 {</div><div class='add'>+			pwm2_pins: pwm-2-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x114 MODE_NITRO</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			pwm3_pins: pinmux_pwm_3 {</div><div class='add'>+			pwm3_pins: pwm-3-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x118 MODE_NITRO</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			dbu_rxd_pins: pinmux_uart1_sin_nitro {</div><div class='add'>+			dbu_rxd_pins: uart1-sin-nitro-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x11c MODE_NITRO /* dbu_rxd */</div><div class='ctx'> 					0x120 MODE_NITRO /* dbu_txd */</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			uart1_pins: pinmux_uart1_sin_nand {</div><div class='add'>+			uart1_pins: uart1-sin-nand-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x11c MODE_NAND /* uart1_sin */</div><div class='ctx'> 					0x120 MODE_NAND /* uart1_out */</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			uart2_pins: pinmux_uart2_sin {</div><div class='add'>+			uart2_pins: uart2-sin-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x124 MODE_NITRO /* uart2_sin */</div><div class='ctx'> 					0x128 MODE_NITRO /* uart2_out */</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			uart3_pins: pinmux_uart3_sin {</div><div class='add'>+			uart3_pins: uart3-sin-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x12c MODE_NITRO /* uart3_sin */</div><div class='ctx'> 					0x130 MODE_NITRO /* uart3_out */</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			i2s_pins: pinmux_i2s_bitclk {</div><div class='add'>+			i2s_pins: i2s-bitclk-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x134 MODE_NITRO /* i2s_bitclk */</div><div class='ctx'> 					0x138 MODE_NITRO /* i2s_sdout */</div><div class='hunk'>@@ -211,7 +211,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			qspi_pins: pinumx_qspi_hold_n {</div><div class='add'>+			qspi_pins: qspi-hold-n-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x14c MODE_NAND /* qspi_hold_n */</div><div class='ctx'> 					0x150 MODE_NAND /* qspi_wp_n */</div><div class='hunk'>@@ -222,28 +222,28 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			mdio_pins: pinumx_ext_mdio {</div><div class='add'>+			mdio_pins: ext-mdio-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x164 MODE_NITRO /* ext_mdio */</div><div class='ctx'> 					0x168 MODE_NITRO /* ext_mdc */</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			i2c0_pins: pinmux_i2c0_sda {</div><div class='add'>+			i2c0_pins: i2c0-sda-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x16c MODE_NITRO /* i2c0_sda */</div><div class='ctx'> 					0x170 MODE_NITRO /* i2c0_scl */</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			i2c1_pins: pinmux_i2c1_sda {</div><div class='add'>+			i2c1_pins: i2c1-sda-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x174 MODE_NITRO /* i2c1_sda */</div><div class='ctx'> 					0x178 MODE_NITRO /* i2c1_scl */</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			sdio0_pins: pinmux_sdio0_cd_l {</div><div class='add'>+			sdio0_pins: sdio0-cd-l-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x17c MODE_NITRO /* sdio0_cd_l */</div><div class='ctx'> 					0x180 MODE_NITRO /* sdio0_clk_sdcard */</div><div class='hunk'>@@ -262,7 +262,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			sdio1_pins: pinmux_sdio1_cd_l {</div><div class='add'>+			sdio1_pins: sdio1-cd-l-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x1b4 MODE_NITRO /* sdio1_cd_l */</div><div class='ctx'> 					0x1b8 MODE_NITRO /* sdio1_clk_sdcard */</div><div class='hunk'>@@ -281,7 +281,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			spi0_pins: pinmux_spi0_sck_nand {</div><div class='add'>+			spi0_pins: spi0-sck-nand-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x1ec MODE_NITRO /* spi0_sck */</div><div class='ctx'> 					0x1f0 MODE_NITRO /* spi0_rxd */</div><div class='hunk'>@@ -290,7 +290,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			spi1_pins: pinmux_spi1_sck_nand {</div><div class='add'>+			spi1_pins: spi1-sck-nand-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x1fc MODE_NITRO /* spi1_sck */</div><div class='ctx'> 					0x200 MODE_NITRO /* spi1_rxd */</div><div class='hunk'>@@ -299,14 +299,14 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			nuart_pins: pinmux_uart0_sin_nitro {</div><div class='add'>+			nuart_pins: uart0-sin-nitro-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x20c MODE_NITRO /* nuart_rxd */</div><div class='ctx'> 					0x210 MODE_NITRO /* nuart_txd */</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			uart0_pins: pinumux_uart0_sin_nand {</div><div class='add'>+			uart0_pins: uart0-sin-nand-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x20c MODE_NAND /* uart0_sin */</div><div class='ctx'> 					0x210 MODE_NAND /* uart0_out */</div><div class='hunk'>@@ -319,7 +319,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			drdu2_pins: pinmux_drdu2_overcurrent {</div><div class='add'>+			drdu2_pins: drdu2-overcurrent-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x22c MODE_NITRO /* drdu2_overcurrent */</div><div class='ctx'> 					0x230 MODE_NITRO /* drdu2_vbus_ppc */</div><div class='hunk'>@@ -328,7 +328,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			drdu3_pins: pinmux_drdu3_overcurrent {</div><div class='add'>+			drdu3_pins: drdu3-overcurrent-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x23c MODE_NITRO /* drdu3_overcurrent */</div><div class='ctx'> 					0x240 MODE_NITRO /* drdu3_vbus_ppc */</div><div class='hunk'>@@ -337,7 +337,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			usb3h_pins: pinmux_usb3h_overcurrent {</div><div class='add'>+			usb3h_pins: usb3h-overcurrent-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x24c MODE_NITRO /* usb3h_overcurrent */</div><div class='ctx'> 					0x250 MODE_NITRO /* usb3h_vbus_ppc */</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-sata.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-sata.dtsi<br/>deleted file mode 100644<br/>index 8c68e0c26f1b..000000000000<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/stingray/stingray-sata.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/stingray/stingray-sata.dtsi</a><br/>+++ /dev/null</div><div class='hunk'>@@ -1,278 +0,0 @@</div><div class='del'>-/*</div><div class='del'>- *  BSD LICENSE</div><div class='del'>- *</div><div class='del'>- *  Copyright(c) 2016-2017 Broadcom.  All rights reserved.</div><div class='del'>- *</div><div class='del'>- *  Redistribution and use in source and binary forms, with or without</div><div class='del'>- *  modification, are permitted provided that the following conditions</div><div class='del'>- *  are met:</div><div class='del'>- *</div><div class='del'>- *    * Redistributions of source code must retain the above copyright</div><div class='del'>- *      notice, this list of conditions and the following disclaimer.</div><div class='del'>- *    * Redistributions in binary form must reproduce the above copyright</div><div class='del'>- *      notice, this list of conditions and the following disclaimer in</div><div class='del'>- *      the documentation and/or other materials provided with the</div><div class='del'>- *      distribution.</div><div class='del'>- *    * Neither the name of Broadcom nor the names of its</div><div class='del'>- *      contributors may be used to endorse or promote products derived</div><div class='del'>- *      from this software without specific prior written permission.</div><div class='del'>- *</div><div class='del'>- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS</div><div class='del'>- *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT</div><div class='del'>- *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR</div><div class='del'>- *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT</div><div class='del'>- *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,</div><div class='del'>- *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT</div><div class='del'>- *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,</div><div class='del'>- *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY</div><div class='del'>- *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT</div><div class='del'>- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE</div><div class='del'>- *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.</div><div class='del'>- */</div><div class='del'>-</div><div class='del'>-	sata {</div><div class='del'>-		compatible = "simple-bus";</div><div class='del'>-		#address-cells = &lt;1&gt;;</div><div class='del'>-		#size-cells = &lt;1&gt;;</div><div class='del'>-		ranges = &lt;0x0 0x0 0x67d00000 0x00800000&gt;;</div><div class='del'>-</div><div class='del'>-		sata0: ahci@0 {</div><div class='del'>-			compatible = "brcm,iproc-ahci", "generic-ahci";</div><div class='del'>-			reg = &lt;0x00000000 0x1000&gt;;</div><div class='del'>-			reg-names = "ahci";</div><div class='del'>-			interrupts = &lt;GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			#address-cells = &lt;1&gt;;</div><div class='del'>-			#size-cells = &lt;0&gt;;</div><div class='del'>-			status = "disabled";</div><div class='del'>-</div><div class='del'>-			sata0_port0: sata-port@0 {</div><div class='del'>-				reg = &lt;0&gt;;</div><div class='del'>-				phys = &lt;&amp;sata0_phy0&gt;;</div><div class='del'>-				phy-names = "sata-phy";</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		sata_phy0: sata_phy@2100 {</div><div class='del'>-			compatible = "brcm,iproc-sr-sata-phy";</div><div class='del'>-			reg = &lt;0x00002100 0x1000&gt;;</div><div class='del'>-			reg-names = "phy";</div><div class='del'>-			#address-cells = &lt;1&gt;;</div><div class='del'>-			#size-cells = &lt;0&gt;;</div><div class='del'>-			status = "disabled";</div><div class='del'>-</div><div class='del'>-			sata0_phy0: sata-phy@0 {</div><div class='del'>-				reg = &lt;0&gt;;</div><div class='del'>-				#phy-cells = &lt;0&gt;;</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		sata1: ahci@10000 {</div><div class='del'>-			compatible = "brcm,iproc-ahci", "generic-ahci";</div><div class='del'>-			reg = &lt;0x00010000 0x1000&gt;;</div><div class='del'>-			reg-names = "ahci";</div><div class='del'>-			interrupts = &lt;GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			#address-cells = &lt;1&gt;;</div><div class='del'>-			#size-cells = &lt;0&gt;;</div><div class='del'>-			status = "disabled";</div><div class='del'>-</div><div class='del'>-			sata1_port0: sata-port@0 {</div><div class='del'>-				reg = &lt;0&gt;;</div><div class='del'>-				phys = &lt;&amp;sata1_phy0&gt;;</div><div class='del'>-				phy-names = "sata-phy";</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		sata_phy1: sata_phy@12100 {</div><div class='del'>-			compatible = "brcm,iproc-sr-sata-phy";</div><div class='del'>-			reg = &lt;0x00012100 0x1000&gt;;</div><div class='del'>-			reg-names = "phy";</div><div class='del'>-			#address-cells = &lt;1&gt;;</div><div class='del'>-			#size-cells = &lt;0&gt;;</div><div class='del'>-			status = "disabled";</div><div class='del'>-</div><div class='del'>-			sata1_phy0: sata-phy@0 {</div><div class='del'>-				reg = &lt;0&gt;;</div><div class='del'>-				#phy-cells = &lt;0&gt;;</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		sata2: ahci@20000 {</div><div class='del'>-			compatible = "brcm,iproc-ahci", "generic-ahci";</div><div class='del'>-			reg = &lt;0x00020000 0x1000&gt;;</div><div class='del'>-			reg-names = "ahci";</div><div class='del'>-			interrupts = &lt;GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			#address-cells = &lt;1&gt;;</div><div class='del'>-			#size-cells = &lt;0&gt;;</div><div class='del'>-			status = "disabled";</div><div class='del'>-</div><div class='del'>-			sata2_port0: sata-port@0 {</div><div class='del'>-				reg = &lt;0&gt;;</div><div class='del'>-				phys = &lt;&amp;sata2_phy0&gt;;</div><div class='del'>-				phy-names = "sata-phy";</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		sata_phy2: sata_phy@22100 {</div><div class='del'>-			compatible = "brcm,iproc-sr-sata-phy";</div><div class='del'>-			reg = &lt;0x00022100 0x1000&gt;;</div><div class='del'>-			reg-names = "phy";</div><div class='del'>-			#address-cells = &lt;1&gt;;</div><div class='del'>-			#size-cells = &lt;0&gt;;</div><div class='del'>-			status = "disabled";</div><div class='del'>-</div><div class='del'>-			sata2_phy0: sata-phy@0 {</div><div class='del'>-				reg = &lt;0&gt;;</div><div class='del'>-				#phy-cells = &lt;0&gt;;</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		sata3: ahci@30000 {</div><div class='del'>-			compatible = "brcm,iproc-ahci", "generic-ahci";</div><div class='del'>-			reg = &lt;0x00030000 0x1000&gt;;</div><div class='del'>-			reg-names = "ahci";</div><div class='del'>-			interrupts = &lt;GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			#address-cells = &lt;1&gt;;</div><div class='del'>-			#size-cells = &lt;0&gt;;</div><div class='del'>-			status = "disabled";</div><div class='del'>-</div><div class='del'>-			sata3_port0: sata-port@0 {</div><div class='del'>-				reg = &lt;0&gt;;</div><div class='del'>-				phys = &lt;&amp;sata3_phy0&gt;;</div><div class='del'>-				phy-names = "sata-phy";</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		sata_phy3: sata_phy@32100 {</div><div class='del'>-			compatible = "brcm,iproc-sr-sata-phy";</div><div class='del'>-			reg = &lt;0x00032100 0x1000&gt;;</div><div class='del'>-			reg-names = "phy";</div><div class='del'>-			#address-cells = &lt;1&gt;;</div><div class='del'>-			#size-cells = &lt;0&gt;;</div><div class='del'>-			status = "disabled";</div><div class='del'>-</div><div class='del'>-			sata3_phy0: sata-phy@0 {</div><div class='del'>-				reg = &lt;0&gt;;</div><div class='del'>-				#phy-cells = &lt;0&gt;;</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		sata4: ahci@100000 {</div><div class='del'>-			compatible = "brcm,iproc-ahci", "generic-ahci";</div><div class='del'>-			reg = &lt;0x00100000 0x1000&gt;;</div><div class='del'>-			reg-names = "ahci";</div><div class='del'>-			interrupts = &lt;GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			#address-cells = &lt;1&gt;;</div><div class='del'>-			#size-cells = &lt;0&gt;;</div><div class='del'>-			status = "disabled";</div><div class='del'>-</div><div class='del'>-			sata4_port0: sata-port@0 {</div><div class='del'>-				reg = &lt;0&gt;;</div><div class='del'>-				phys = &lt;&amp;sata4_phy0&gt;;</div><div class='del'>-				phy-names = "sata-phy";</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		sata_phy4: sata_phy@102100 {</div><div class='del'>-			compatible = "brcm,iproc-sr-sata-phy";</div><div class='del'>-			reg = &lt;0x00102100 0x1000&gt;;</div><div class='del'>-			reg-names = "phy";</div><div class='del'>-			#address-cells = &lt;1&gt;;</div><div class='del'>-			#size-cells = &lt;0&gt;;</div><div class='del'>-			status = "disabled";</div><div class='del'>-</div><div class='del'>-			sata4_phy0: sata-phy@0 {</div><div class='del'>-				reg = &lt;0&gt;;</div><div class='del'>-				#phy-cells = &lt;0&gt;;</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		sata5: ahci@110000 {</div><div class='del'>-			compatible = "brcm,iproc-ahci", "generic-ahci";</div><div class='del'>-			reg = &lt;0x00110000 0x1000&gt;;</div><div class='del'>-			reg-names = "ahci";</div><div class='del'>-			interrupts = &lt;GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			#address-cells = &lt;1&gt;;</div><div class='del'>-			#size-cells = &lt;0&gt;;</div><div class='del'>-			status = "disabled";</div><div class='del'>-</div><div class='del'>-			sata5_port0: sata-port@0 {</div><div class='del'>-				reg = &lt;0&gt;;</div><div class='del'>-				phys = &lt;&amp;sata5_phy0&gt;;</div><div class='del'>-				phy-names = "sata-phy";</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		sata_phy5: sata_phy@112100 {</div><div class='del'>-			compatible = "brcm,iproc-sr-sata-phy";</div><div class='del'>-			reg = &lt;0x00112100 0x1000&gt;;</div><div class='del'>-			reg-names = "phy";</div><div class='del'>-			#address-cells = &lt;1&gt;;</div><div class='del'>-			#size-cells = &lt;0&gt;;</div><div class='del'>-			status = "disabled";</div><div class='del'>-</div><div class='del'>-			sata5_phy0: sata-phy@0 {</div><div class='del'>-				reg = &lt;0&gt;;</div><div class='del'>-				#phy-cells = &lt;0&gt;;</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		sata6: ahci@120000 {</div><div class='del'>-			compatible = "brcm,iproc-ahci", "generic-ahci";</div><div class='del'>-			reg = &lt;0x00120000 0x1000&gt;;</div><div class='del'>-			reg-names = "ahci";</div><div class='del'>-			interrupts = &lt;GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			#address-cells = &lt;1&gt;;</div><div class='del'>-			#size-cells = &lt;0&gt;;</div><div class='del'>-			status = "disabled";</div><div class='del'>-</div><div class='del'>-			sata6_port0: sata-port@0 {</div><div class='del'>-				reg = &lt;0&gt;;</div><div class='del'>-				phys = &lt;&amp;sata6_phy0&gt;;</div><div class='del'>-				phy-names = "sata-phy";</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		sata_phy6: sata_phy@122100 {</div><div class='del'>-			compatible = "brcm,iproc-sr-sata-phy";</div><div class='del'>-			reg = &lt;0x00122100 0x1000&gt;;</div><div class='del'>-			reg-names = "phy";</div><div class='del'>-			#address-cells = &lt;1&gt;;</div><div class='del'>-			#size-cells = &lt;0&gt;;</div><div class='del'>-			status = "disabled";</div><div class='del'>-</div><div class='del'>-			sata6_phy0: sata-phy@0 {</div><div class='del'>-				reg = &lt;0&gt;;</div><div class='del'>-				#phy-cells = &lt;0&gt;;</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		sata7: ahci@130000 {</div><div class='del'>-			compatible = "brcm,iproc-ahci", "generic-ahci";</div><div class='del'>-			reg = &lt;0x00130000 0x1000&gt;;</div><div class='del'>-			reg-names = "ahci";</div><div class='del'>-			interrupts = &lt;GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			#address-cells = &lt;1&gt;;</div><div class='del'>-			#size-cells = &lt;0&gt;;</div><div class='del'>-			status = "disabled";</div><div class='del'>-</div><div class='del'>-			sata7_port0: sata-port@0 {</div><div class='del'>-				reg = &lt;0&gt;;</div><div class='del'>-				phys = &lt;&amp;sata7_phy0&gt;;</div><div class='del'>-				phy-names = "sata-phy";</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		sata_phy7: sata_phy@132100 {</div><div class='del'>-			compatible = "brcm,iproc-sr-sata-phy";</div><div class='del'>-			reg = &lt;0x00132100 0x1000&gt;;</div><div class='del'>-			reg-names = "phy";</div><div class='del'>-			#address-cells = &lt;1&gt;;</div><div class='del'>-			#size-cells = &lt;0&gt;;</div><div class='del'>-			status = "disabled";</div><div class='del'>-</div><div class='del'>-			sata7_phy0: sata-phy@0 {</div><div class='del'>-				reg = &lt;0&gt;;</div><div class='del'>-				#phy-cells = &lt;0&gt;;</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi<br/>index 55259f973b5a..ac4f7b8f9273 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi</a></div><div class='hunk'>@@ -1,24 +1,29 @@</div><div class='del'>-// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause)</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)</div><div class='ctx'> /*</div><div class='ctx'>  *Copyright(c) 2018 Broadcom</div><div class='ctx'>  */</div><div class='ctx'> 	usb {</div><div class='ctx'> 		compatible = "simple-bus";</div><div class='del'>-		dma-ranges;</div><div class='del'>-		#address-cells = &lt;1&gt;;</div><div class='del'>-		#size-cells = &lt;1&gt;;</div><div class='del'>-		ranges = &lt;0x0 0x0 0x68500000 0x00400000&gt;;</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges = &lt;0x0 0x0 0x0 0x68500000 0x0 0x00400000&gt;;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Internally, USB bus to the interconnect can only address up</div><div class='add'>+		 * to 40-bit</div><div class='add'>+		 */</div><div class='add'>+		dma-ranges = &lt;0 0 0 0 0x100 0x0&gt;;</div><div class='ctx'> </div><div class='ctx'> 		usbphy0: usb-phy@0 {</div><div class='ctx'> 			compatible = "brcm,sr-usb-combo-phy";</div><div class='del'>-			reg = &lt;0x00000000 0x100&gt;;</div><div class='add'>+			reg = &lt;0x0 0x00000000 0x0 0x100&gt;;</div><div class='ctx'> 			#phy-cells = &lt;1&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		xhci0: usb@1000 {</div><div class='ctx'> 			compatible = "generic-xhci";</div><div class='del'>-			reg = &lt;0x00001000 0x1000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x00001000 0x0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			phys = &lt;&amp;usbphy0 1&gt;, &lt;&amp;usbphy0 0&gt;;</div><div class='ctx'> 			phy-names = "phy0", "phy1";</div><div class='hunk'>@@ -28,7 +33,7 @@</div><div class='ctx'> </div><div class='ctx'> 		bdc0: usb@2000 {</div><div class='ctx'> 			compatible = "brcm,bdc-v0.16";</div><div class='del'>-			reg = &lt;0x00002000 0x1000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x00002000 0x0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			phys = &lt;&amp;usbphy0 0&gt;, &lt;&amp;usbphy0 1&gt;;</div><div class='ctx'> 			phy-names = "phy0", "phy1";</div><div class='hunk'>@@ -38,21 +43,21 @@</div><div class='ctx'> </div><div class='ctx'> 		usbphy1: usb-phy@10000 {</div><div class='ctx'> 			compatible = "brcm,sr-usb-combo-phy";</div><div class='del'>-			reg = &lt;0x00010000 0x100&gt;;</div><div class='add'>+			reg = &lt;0x0 0x00010000 0x0 0x100&gt;;</div><div class='ctx'> 			#phy-cells = &lt;1&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		usbphy2: usb-phy@20000 {</div><div class='ctx'> 			compatible = "brcm,sr-usb-hs-phy";</div><div class='del'>-			reg = &lt;0x00020000 0x100&gt;;</div><div class='add'>+			reg = &lt;0x0 0x00020000 0x0 0x100&gt;;</div><div class='ctx'> 			#phy-cells = &lt;0&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		xhci1: usb@11000 {</div><div class='ctx'> 			compatible = "generic-xhci";</div><div class='del'>-			reg = &lt;0x00011000 0x1000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x00011000 0x0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			phys = &lt;&amp;usbphy1 1&gt;, &lt;&amp;usbphy2&gt;, &lt;&amp;usbphy1 0&gt;;</div><div class='ctx'> 			phy-names = "phy0", "phy1", "phy2";</div><div class='hunk'>@@ -62,7 +67,7 @@</div><div class='ctx'> </div><div class='ctx'> 		bdc1: usb@21000 {</div><div class='ctx'> 			compatible = "brcm,bdc-v0.16";</div><div class='del'>-			reg = &lt;0x00021000 0x1000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x00021000 0x0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			phys = &lt;&amp;usbphy2&gt;;</div><div class='ctx'> 			phy-names = "phy0";</div><div class='head'>diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi<br/>index 0098dfdef96c..857fa427e195 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi</a></div><div class='hunk'>@@ -108,18 +108,26 @@</div><div class='ctx'> </div><div class='ctx'> 		CLUSTER0_L2: l2-cache@0 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		CLUSTER1_L2: l2-cache@100 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		CLUSTER2_L2: l2-cache@200 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		CLUSTER3_L2: l2-cache@300 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -134,7 +142,7 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	pmu {</div><div class='del'>-		compatible = "arm,armv8-pmuv3";</div><div class='add'>+		compatible = "arm,cortex-a72-pmu";</div><div class='ctx'> 		interrupts = &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -174,7 +182,7 @@</div><div class='ctx'> 			      &lt;0x02e00000 0x600000&gt;; /* GICR */</div><div class='ctx'> 			interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> </div><div class='del'>-			gic_its: gic-its@63c20000 {</div><div class='add'>+			gic_its: msi-controller@63c20000 {</div><div class='ctx'> 				compatible = "arm,gic-v3-its";</div><div class='ctx'> 				msi-controller;</div><div class='ctx'> 				#msi-cells = &lt;1&gt;;</div><div class='hunk'>@@ -182,7 +190,7 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		smmu: mmu@3000000 {</div><div class='add'>+		smmu: iommu@3000000 {</div><div class='ctx'> 			compatible = "arm,mmu-500";</div><div class='ctx'> 			reg = &lt;0x03000000 0x80000&gt;;</div><div class='ctx'> 			#global-interrupts = &lt;1&gt;;</div><div class='hunk'>@@ -285,7 +293,6 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	#include "stingray-fs4.dtsi"</div><div class='del'>-	#include "stingray-sata.dtsi"</div><div class='ctx'> 	#include "stingray-pcie.dtsi"</div><div class='ctx'> 	#include "stingray-usb.dtsi"</div><div class='ctx'> </div><div class='hunk'>@@ -309,12 +316,6 @@</div><div class='ctx'> 				#size-cells = &lt;0&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			mdio@2 { /* SATA */</div><div class='del'>-				reg = &lt;0x2&gt;;</div><div class='del'>-				#address-cells = &lt;1&gt;;</div><div class='del'>-				#size-cells = &lt;0&gt;;</div><div class='del'>-			};</div><div class='del'>-</div><div class='ctx'> 			mdio@3 { /* USB */</div><div class='ctx'> 				reg = &lt;0x3&gt;;</div><div class='ctx'> 				#address-cells = &lt;1&gt;;</div><div class='hunk'>@@ -438,7 +439,7 @@</div><div class='ctx'> 			reg = &lt;0x000c0000 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;hsls_25m_div2_clk&gt;, &lt;&amp;hsls_div4_clk&gt;;</div><div class='del'>-			clock-names = "wdogclk", "apb_pclk";</div><div class='add'>+			clock-names = "wdog_clk", "apb_pclk";</div><div class='ctx'> 			timeout-sec = &lt;60&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -449,6 +450,7 @@</div><div class='ctx'> 			#gpio-cells = &lt;2&gt;;</div><div class='ctx'> 			gpio-controller;</div><div class='ctx'> 			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			gpio-ranges = &lt;&amp;pinmux 0 0 16&gt;,</div><div class='ctx'> 					&lt;&amp;pinmux 16 71 2&gt;,</div><div class='hunk'>@@ -477,8 +479,7 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		uart0: uart@100000 {</div><div class='del'>-			device_type = "serial";</div><div class='add'>+		uart0: serial@100000 {</div><div class='ctx'> 			compatible = "snps,dw-apb-uart";</div><div class='ctx'> 			reg = &lt;0x00100000 0x1000&gt;;</div><div class='ctx'> 			reg-shift = &lt;2&gt;;</div><div class='hunk'>@@ -488,8 +489,7 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		uart1: uart@110000 {</div><div class='del'>-			device_type = "serial";</div><div class='add'>+		uart1: serial@110000 {</div><div class='ctx'> 			compatible = "snps,dw-apb-uart";</div><div class='ctx'> 			reg = &lt;0x00110000 0x1000&gt;;</div><div class='ctx'> 			reg-shift = &lt;2&gt;;</div><div class='hunk'>@@ -499,8 +499,7 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		uart2: uart@120000 {</div><div class='del'>-			device_type = "serial";</div><div class='add'>+		uart2: serial@120000 {</div><div class='ctx'> 			compatible = "snps,dw-apb-uart";</div><div class='ctx'> 			reg = &lt;0x00120000 0x1000&gt;;</div><div class='ctx'> 			reg-shift = &lt;2&gt;;</div><div class='hunk'>@@ -510,8 +509,7 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		uart3: uart@130000 {</div><div class='del'>-			device_type = "serial";</div><div class='add'>+		uart3: serial@130000 {</div><div class='ctx'> 			compatible = "snps,dw-apb-uart";</div><div class='ctx'> 			reg = &lt;0x00130000 0x1000&gt;;</div><div class='ctx'> 			reg-shift = &lt;2&gt;;</div><div class='hunk'>@@ -526,7 +524,7 @@</div><div class='ctx'> 			reg = &lt;0x00180000 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;hsls_div2_clk&gt;, &lt;&amp;hsls_div2_clk&gt;;</div><div class='del'>-			clock-names = "spiclk", "apb_pclk";</div><div class='add'>+			clock-names = "sspclk", "apb_pclk";</div><div class='ctx'> 			num-cs = &lt;1&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='hunk'>@@ -538,7 +536,7 @@</div><div class='ctx'> 			reg = &lt;0x00190000 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;hsls_div2_clk&gt;, &lt;&amp;hsls_div2_clk&gt;;</div><div class='del'>-			clock-names = "spiclk", "apb_pclk";</div><div class='add'>+			clock-names = "sspclk", "apb_pclk";</div><div class='ctx'> 			num-cs = &lt;1&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='hunk'>@@ -550,7 +548,7 @@</div><div class='ctx'> 			reg = &lt;0x00220000 0x28&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		dma0: dma@310000 {</div><div class='add'>+		dma0: dma-controller@310000 {</div><div class='ctx'> 			compatible = "arm,pl330", "arm,primecell";</div><div class='ctx'> 			reg = &lt;0x00310000 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='hunk'>@@ -563,20 +561,18 @@</div><div class='ctx'> 				     &lt;GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 				     &lt;GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			#dma-cells = &lt;1&gt;;</div><div class='del'>-			#dma-channels = &lt;8&gt;;</div><div class='del'>-			#dma-requests = &lt;32&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;hsls_div2_clk&gt;;</div><div class='ctx'> 			clock-names = "apb_pclk";</div><div class='ctx'> 			iommus = &lt;&amp;smmu 0x6000 0x0000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		enet: ethernet@340000{</div><div class='add'>+		enet: ethernet@340000 {</div><div class='ctx'> 			compatible = "brcm,amac";</div><div class='ctx'> 			reg = &lt;0x00340000 0x1000&gt;;</div><div class='ctx'> 			reg-names = "amac_base";</div><div class='ctx'> 			dma-coherent;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			status= "disabled";</div><div class='add'>+			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		nand: nand@360000 {</div><div class='head'>diff --git a/arch/arm64/boot/dts/bst/Makefile b/arch/arm64/boot/dts/bst/Makefile<br/>new file mode 100644<br/>index 000000000000..4c1b8b4cdad8<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/bst/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/bst/Makefile</a></div><div class='hunk'>@@ -0,0 +1,2 @@</div><div class='add'>+# SPDX-License-Identifier: GPL-2.0</div><div class='add'>+dtb-$(CONFIG_ARCH_BST) += bstc1200-cdcu1.0-adas_4c2g.dtb</div><div class='head'>diff --git a/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts b/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts<br/>new file mode 100644<br/>index 000000000000..5eb9ef369d8c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts</a></div><div class='hunk'>@@ -0,0 +1,24 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "bstc1200.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "BST C1200-96 CDCU1.0 4C2G";</div><div class='add'>+	compatible = "bst,c1200-cdcu1.0-adas-4c2g", "bst,c1200";</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@810000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x8 0x10000000 0x0 0x30000000&gt;,</div><div class='add'>+		      &lt;0x8 0xc0000000 0x1 0x0&gt;,</div><div class='add'>+		      &lt;0xc 0x00000000 0x0 0x40000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/bst/bstc1200.dtsi b/arch/arm64/boot/dts/bst/bstc1200.dtsi<br/>new file mode 100644<br/>index 000000000000..dd13c6bfc3c8<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/bst/bstc1200.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/bst/bstc1200.dtsi</a></div><div class='hunk'>@@ -0,0 +1,97 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "bst,c1200";</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a78";</div><div class='add'>+			reg = &lt;0x0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu@1 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a78";</div><div class='add'>+			reg = &lt;0x100&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu@2 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a78";</div><div class='add'>+			reg = &lt;0x200&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu@3 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a78";</div><div class='add'>+			reg = &lt;0x300&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_cache: l2-cache {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-1.0";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		ranges;</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+</div><div class='add'>+		uart0: serial@20008000 {</div><div class='add'>+			compatible = "snps,dw-apb-uart";</div><div class='add'>+			reg = &lt;0x0 0x20008000 0x0 0x1000&gt;;</div><div class='add'>+			clock-frequency = &lt;25000000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			reg-shift = &lt;2&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@32800000 {</div><div class='add'>+			compatible = "arm,gic-v3";</div><div class='add'>+			reg = &lt;0x0 0x32800000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0x32880000 0x0 0x100000&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		always-on;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi<br/>index e0a71795261b..cc860a80af51 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/cavium/thunder-88xx.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/cavium/thunder-88xx.dtsi</a></div><div class='hunk'>@@ -361,24 +361,24 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	pmu {</div><div class='del'>-		compatible = "cavium,thunder-pmu", "arm,armv8-pmuv3";</div><div class='add'>+		compatible = "cavium,thunder-pmu";</div><div class='ctx'> 		interrupts = &lt;1 7 4&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	refclk50mhz: refclk50mhz {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;50000000&gt;;</div><div class='add'>+		clock-output-names = "refclk50mhz";</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	soc {</div><div class='ctx'> 		compatible = "simple-bus";</div><div class='ctx'> 		#address-cells = &lt;2&gt;;</div><div class='ctx'> 		#size-cells = &lt;2&gt;;</div><div class='ctx'> 		ranges;</div><div class='ctx'> </div><div class='del'>-		refclk50mhz: refclk50mhz {</div><div class='del'>-			compatible = "fixed-clock";</div><div class='del'>-			#clock-cells = &lt;0&gt;;</div><div class='del'>-			clock-frequency = &lt;50000000&gt;;</div><div class='del'>-			clock-output-names = "refclk50mhz";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		gic0: interrupt-controller@8010,00000000 {</div><div class='add'>+		gic0: interrupt-controller@801000000000 {</div><div class='ctx'> 			compatible = "arm,gic-v3";</div><div class='ctx'> 			#interrupt-cells = &lt;3&gt;;</div><div class='ctx'> 			#address-cells = &lt;2&gt;;</div><div class='hunk'>@@ -389,14 +389,15 @@</div><div class='ctx'> 			      &lt;0x8010 0x80000000 0x0 0x600000&gt;; /* GICR */</div><div class='ctx'> 			interrupts = &lt;1 9 0xf04&gt;;</div><div class='ctx'> </div><div class='del'>-			its: gic-its@8010,00020000 {</div><div class='add'>+			its: msi-controller@801000020000 {</div><div class='ctx'> 				compatible = "arm,gic-v3-its";</div><div class='ctx'> 				msi-controller;</div><div class='add'>+				#msi-cells = &lt;1&gt;;</div><div class='ctx'> 				reg = &lt;0x8010 0x20000 0x0 0x200000&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		uaa0: serial@87e0,24000000 {</div><div class='add'>+		uaa0: serial@87e024000000 {</div><div class='ctx'> 			compatible = "arm,pl011", "arm,primecell";</div><div class='ctx'> 			reg = &lt;0x87e0 0x24000000 0x0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;1 21 4&gt;;</div><div class='hunk'>@@ -404,7 +405,7 @@</div><div class='ctx'> 			clock-names = "apb_pclk";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		uaa1: serial@87e0,25000000 {</div><div class='add'>+		uaa1: serial@87e025000000 {</div><div class='ctx'> 			compatible = "arm,pl011", "arm,primecell";</div><div class='ctx'> 			reg = &lt;0x87e0 0x25000000 0x0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;1 22 4&gt;;</div><div class='head'>diff --git a/arch/arm64/boot/dts/cavium/thunder2-99xx.dts b/arch/arm64/boot/dts/cavium/thunder2-99xx.dts<br/>index d005e1e79c3d..89fc4107a0c4 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/cavium/thunder2-99xx.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/cavium/thunder2-99xx.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/cavium/thunder2-99xx.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/cavium/thunder2-99xx.dts</a></div><div class='hunk'>@@ -14,7 +14,7 @@</div><div class='ctx'> 	model = "Cavium ThunderX2 CN99XX";</div><div class='ctx'> 	compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc";</div><div class='ctx'> </div><div class='del'>-	memory {</div><div class='add'>+	memory@80000000 {</div><div class='ctx'> 		device_type = "memory";</div><div class='ctx'> 		reg = &lt;0x00000000 0x80000000 0x0 0x80000000&gt;,  /* 2G @ 2G  */</div><div class='ctx'> 		      &lt;0x00000008 0x80000000 0x0 0x80000000&gt;;  /* 2G @ 34G */</div><div class='head'>diff --git a/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi<br/>index dfb41705a9a9..966fb57280f3 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi</a></div><div class='hunk'>@@ -55,7 +55,7 @@</div><div class='ctx'> 		method = "smc";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gic: interrupt-controller@400080000 {</div><div class='add'>+	gic: interrupt-controller@4000080000 {</div><div class='ctx'> 		compatible = "arm,gic-v3";</div><div class='ctx'> 		#interrupt-cells = &lt;3&gt;;</div><div class='ctx'> 		#address-cells = &lt;2&gt;;</div><div class='hunk'>@@ -67,7 +67,7 @@</div><div class='ctx'> 		      &lt;0x04 0x01000000 0x0 0x1000000&gt;;	/* GICR */</div><div class='ctx'> 		interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> </div><div class='del'>-		gicits: gic-its@40010000 {</div><div class='add'>+		gicits: msi-controller@4000100000 {</div><div class='ctx'> 			compatible = "arm,gic-v3-its";</div><div class='ctx'> 			msi-controller;</div><div class='ctx'> 			reg = &lt;0x04 0x00100000 0x0 0x20000&gt;;	/* GIC ITS */</div><div class='hunk'>@@ -83,7 +83,7 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	pmu {</div><div class='del'>-		compatible = "brcm,vulcan-pmu", "arm,armv8-pmuv3";</div><div class='add'>+		compatible = "brcm,vulcan-pmu";</div><div class='ctx'> 		interrupts = &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH&gt;; /* PMU overflow */</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -103,7 +103,6 @@</div><div class='ctx'> </div><div class='ctx'> 		/* ECAM at 0x3000_0000 - 0x4000_0000 */</div><div class='ctx'> 		reg = &lt;0x0 0x30000000  0x0 0x10000000&gt;;</div><div class='del'>-		reg-names = "PCI ECAM";</div><div class='ctx'> </div><div class='ctx'> 		/*</div><div class='ctx'> 		 * PCI ranges:</div><div class='hunk'>@@ -137,8 +136,8 @@</div><div class='ctx'> 			reg = &lt;0x04 0x02020000 0x0 0x1000&gt;;</div><div class='ctx'> 			interrupt-parent = &lt;&amp;gic&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk125mhz&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='add'>+			clocks = &lt;&amp;clk125mhz&gt;, &lt;&amp;clk125mhz&gt;;</div><div class='add'>+			clock-names = "uartclk", "apb_pclk";</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='head'>diff --git a/arch/arm64/boot/dts/cix/Makefile b/arch/arm64/boot/dts/cix/Makefile<br/>new file mode 100644<br/>index 000000000000..ed3713982012<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/cix/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/cix/Makefile</a></div><div class='hunk'>@@ -0,0 +1,2 @@</div><div class='add'>+# SPDX-License-Identifier: GPL-2.0</div><div class='add'>+dtb-$(CONFIG_ARCH_CIX) += sky1-orion-o6.dtb</div><div class='head'>diff --git a/arch/arm64/boot/dts/cix/sky1-orion-o6.dts b/arch/arm64/boot/dts/cix/sky1-orion-o6.dts<br/>new file mode 100644<br/>index 000000000000..4dee8cd0b86d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/cix/sky1-orion-o6.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/cix/sky1-orion-o6.dts</a></div><div class='hunk'>@@ -0,0 +1,91 @@</div><div class='add'>+// SPDX-License-Identifier: BSD-3-Clause</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2025 Cix Technology Group Co., Ltd.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "sky1.dtsi"</div><div class='add'>+#include "sky1-pinfunc.h"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Radxa Orion O6";</div><div class='add'>+	compatible = "radxa,orion-o6", "cix,sky1";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial2 = &amp;uart2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		linux,cma {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reusable;</div><div class='add'>+			size = &lt;0x0 0x28000000&gt;;</div><div class='add'>+			linux,cma-default;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hog&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl_hog: hog-cfg {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;CIX_PAD_GPIO144_FUNC_GPIO144&gt;,</div><div class='add'>+				&lt;CIX_PAD_GPIO145_FUNC_GPIO145&gt;,</div><div class='add'>+				&lt;CIX_PAD_GPIO146_FUNC_GPIO146&gt;,</div><div class='add'>+				&lt;CIX_PAD_GPIO147_FUNC_GPIO147&gt;;</div><div class='add'>+			bias-pull-down;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc_s5 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hog_s5&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl_hog_s5: hog-s5-cfg {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;CIX_PAD_GPIO014_FUNC_GPIO014&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_x8_rc {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_x4_rc {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_x2_rc {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_x1_0_rc {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_x1_1_rc {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/cix/sky1-pinfunc.h b/arch/arm64/boot/dts/cix/sky1-pinfunc.h<br/>new file mode 100644<br/>index 000000000000..ebe9f6fef403<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/cix/sky1-pinfunc.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/cix/sky1-pinfunc.h</a></div><div class='hunk'>@@ -0,0 +1,401 @@</div><div class='add'>+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024-2025 Cix Technology Group Co., Ltd.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __CIX_SKY1_H</div><div class='add'>+#define __CIX_SKY1_H</div><div class='add'>+</div><div class='add'>+/* s5 pads */</div><div class='add'>+#define CIX_PAD_GPIO001_FUNC_GPIO001				   (0 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO002_FUNC_GPIO002				   (1 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO003_FUNC_GPIO003				   (2 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO004_FUNC_GPIO004				   (3 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO005_FUNC_GPIO005				   (4 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO006_FUNC_GPIO006				   (5 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO007_FUNC_GPIO007				   (6 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO008_FUNC_GPIO008				   (7 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO009_FUNC_GPIO009				   (8 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO010_FUNC_GPIO010				   (9 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO011_FUNC_GPIO011				   (10 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO012_FUNC_GPIO012				   (11 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO013_FUNC_GPIO013				   (12 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO014_FUNC_GPIO014				   (13 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_SFI_I2C0_SCL_FUNC_SFI_I2C0_SCL			   (28 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_SFI_I2C0_SCL_FUNC_SFI_I3C0_SCL			   (28 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_SFI_I2C0_SDA_FUNC_SFI_I2C0_SDA			   (29 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_SFI_I2C0_SDA_FUNC_SFI_I3C0_SDA			   (29 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_SFI_I2C1_SCL_FUNC_SFI_I2C1_SCL			   (30 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_SFI_I2C1_SCL_FUNC_SFI_I3C1_SCL			   (30 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_SFI_I2C1_SCL_FUNC_SFI_SPI_CS0			   (30 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_SFI_I2C1_SDA_FUNC_SFI_I2C1_SDA			   (31 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_SFI_I2C1_SDA_FUNC_SFI_I3C1_SDA			   (31 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_SFI_I2C1_SDA_FUNC_SFI_SPI_CS1			   (31 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_SFI_GPIO0_FUNC_GPIO015				   (32 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_SFI_GPIO0_FUNC_SFI_SPI_SCK			   (32 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_SFI_GPIO0_FUNC_SFI_GPIO0			   (32 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_SFI_GPIO1_FUNC_GPIO016				   (33 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_SFI_GPIO1_FUNC_SFI_SPI_MOSI			   (33 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_SFI_GPIO1_FUNC_SFI_GPIO1			   (33 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_SFI_GPIO2_FUNC_GPIO017				   (34 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_SFI_GPIO2_FUNC_SFI_SPI_MISO			   (34 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_SFI_GPIO2_FUNC_SFI_GPIO2			   (34 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_GPIO018_FUNC_SFI_GPIO3				   (35 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO018_FUNC_GPIO018				   (35 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO019_FUNC_SFI_GPIO4				   (36 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO019_FUNC_GPIO019				   (36 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO020_FUNC_SFI_GPIO5				   (37 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO020_FUNC_GPIO020				   (37 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO021_FUNC_SFI_GPIO6				   (38 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO021_FUNC_GPIO021				   (38 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO022_FUNC_SFI_GPIO7				   (39 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO022_FUNC_GPIO022				   (39 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO023_FUNC_SFI_GPIO8				   (40 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO023_FUNC_GPIO023				   (40 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO023_FUNC_SFI_I3C0_PUR_EN_L			   (40 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_GPIO024_FUNC_SFI_GPIO9				   (41 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO024_FUNC_GPIO024				   (41 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO024_FUNC_SFI_I3C1_PUR_EN_L			   (41 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_SPI1_MISO_FUNC_SPI1_MISO			   (42 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_SPI1_MISO_FUNC_GPIO025				   (42 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_SPI1_CS0_FUNC_SPI1_CS0				   (43 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_SPI1_CS0_FUNC_GPIO026				   (43 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_SPI1_CS1_FUNC_SPI1_CS1				   (44 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_SPI1_CS1_FUNC_GPIO027				   (44 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_SPI1_MOSI_FUNC_SPI1_MOSI			   (45 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_SPI1_MOSI_FUNC_GPIO028				   (45 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_SPI1_CLK_FUNC_SPI1_CLK				   (46 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_SPI1_CLK_FUNC_GPIO029				   (46 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO030_FUNC_GPIO030				   (47 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO030_FUNC_USB_OC0_L				   (47 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO031_FUNC_GPIO031				   (48 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO031_FUNC_USB_OC1_L				   (48 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO032_FUNC_GPIO032				   (49 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO032_FUNC_USB_OC2_L				   (49 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO033_FUNC_GPIO033				   (50 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO033_FUNC_USB_OC3_L				   (50 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO034_FUNC_GPIO034				   (51 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO034_FUNC_USB_OC4_L				   (51 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO035_FUNC_GPIO035				   (52 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO035_FUNC_USB_OC5_L				   (52 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO036_FUNC_GPIO036				   (53 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO036_FUNC_USB_OC6_L				   (53 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO037_FUNC_GPIO037				   (54 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO037_FUNC_USB_OC7_L				   (54 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO038_FUNC_GPIO038				   (55 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO038_FUNC_USB_OC8_L				   (55 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO039_FUNC_GPIO039				   (56 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO039_FUNC_USB_OC9_L				   (56 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO040_FUNC_GPIO040				   (57 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO040_FUNC_USB_DRIVE_VBUS0			   (57 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO041_FUNC_GPIO041				   (58 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO041_FUNC_USB_DRIVE_VBUS4			   (58 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO042_FUNC_GPIO042				   (59 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO042_FUNC_USB_DRIVE_VBUS5			   (59 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_SE_QSPI_CLK_FUNC_SE_QSPI_CLK			   (60 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_SE_QSPI_CLK_FUNC_QSPI_CLK			   (60 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_SE_QSPI_CS_L_FUNC_SE_QSPI_CS_L			   (61 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_SE_QSPI_CS_L_FUNC_QSPI_CS_L			   (61 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_SE_QSPI_DATA0_FUNC_SE_QSPI_DATA0		   (62 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_SE_QSPI_DATA0_FUNC_QSPI_DATA0			   (62 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_SE_QSPI_DATA1_FUNC_SE_QSPI_DATA1		   (63 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_SE_QSPI_DATA1_FUNC_QSPI_DATA1			   (63 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_SE_QSPI_DATA2_FUNC_SE_QSPI_DATA2		   (64 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_SE_QSPI_DATA2_FUNC_QSPI_DATA2			   (64 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_SE_QSPI_DATA3_FUNC_SE_QSPI_DATA3		   (65 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_SE_QSPI_DATA3_FUNC_QSPI_DATA3			   (65 &lt;&lt; 8 | 0x1)</div><div class='add'>+/* s0 pads */</div><div class='add'>+#define CIX_PAD_GPIO043_FUNC_GPIO043				   (0 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO044_FUNC_GPIO044				   (1 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO045_FUNC_GPIO045				   (2 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO046_FUNC_GPIO046				   (3 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_DP2_DIGON_FUNC_DP2_DIGON			   (18 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_DP2_BLON_FUNC_DP2_BLON				   (19 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_DP2_VARY_BL_FUNC_DP2_VARY_BL			   (20 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_I2C7_SCL_FUNC_I2C7_SCL				   (21 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_I2C7_SDA_FUNC_I2C7_SDA				   (22 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_I2C5_SCL_FUNC_I2C5_SCL				   (26 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_I2C5_SCL_FUNC_GPIO047				   (26 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_I2C5_SDA_FUNC_I2C5_SDA				   (27 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_I2C5_SDA_FUNC_GPIO048				   (27 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_I2C6_SCL_FUNC_I2C6_SCL				   (28 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_I2C6_SCL_FUNC_GPIO049				   (28 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_I2C6_SDA_FUNC_I2C6_SDA				   (29 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_I2C6_SDA_FUNC_GPIO050				   (29 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_I2C0_CLK_FUNC_I2C0_CLK				   (30 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_I2C0_CLK_FUNC_GPIO051				   (30 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_I2C0_SDA_FUNC_I2C0_SDA				   (31 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_I2C0_SDA_FUNC_GPIO052				   (31 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_I2C1_CLK_FUNC_I2C1_CLK				   (32 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_I2C1_CLK_FUNC_GPIO053				   (32 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_I2C1_SDA_FUNC_I2C1_SDA				   (33 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_I2C1_SDA_FUNC_GPIO054				   (33 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_I2C2_SCL_FUNC_I2C2_SCL				   (34 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_I2C2_SCL_FUNC_I3C0_SCL				   (34 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_I2C2_SCL_FUNC_GPIO055				   (34 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_I2C2_SDA_FUNC_I2C2_SDA				   (35 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_I2C2_SDA_FUNC_I3C0_SDA				   (35 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_I2C2_SDA_FUNC_GPIO056				   (35 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_GPIO057_FUNC_GPIO057				   (36 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO057_FUNC_I3C0_PUR_EN_L			   (36 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_I2C3_CLK_FUNC_I2C3_CLK				   (37 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_I2C3_CLK_FUNC_I3C1_CLK				   (37 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_I2C3_CLK_FUNC_GPIO058				   (37 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_I2C3_SDA_FUNC_I2C3_SDA				   (38 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_I2C3_SDA_FUNC_I3C1_SDA				   (38 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_I2C3_SDA_FUNC_GPIO059				   (38 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_GPIO060_FUNC_GPIO060				   (39 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO060_FUNC_I3C1_PUR_EN_L			   (39 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_I2C4_CLK_FUNC_I2C4_CLK				   (40 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_I2C4_CLK_FUNC_GPIO061				   (40 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_I2C4_SDA_FUNC_I2C4_SDA				   (41 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_I2C4_SDA_FUNC_GPIO062				   (41 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_HDA_BITCLK_FUNC_HDA_BITCLK			   (42 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_HDA_BITCLK_FUNC_I2S0_SCK			   (42 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_HDA_BITCLK_FUNC_I2S9_RSCK_DBG			   (42 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_HDA_RST_L_FUNC_HDA_RST_L			   (43 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_HDA_RST_L_FUNC_I2S0_DATA_IN			   (43 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_HDA_RST_L_FUNC_I2S9_DATA_IN0_DBG		   (43 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_HDA_SDIN0_FUNC_HDA_SDIN0			   (44 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_HDA_SDIN0_FUNC_I2S0_MCLK			   (44 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_HDA_SDIN0_FUNC_I2S9_TSCK_DBG			   (44 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_HDA_SDOUT0_FUNC_HDA_SDOUT0			   (45 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_HDA_SDOUT0_FUNC_I2S0_DATA_OUT			   (45 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_HDA_SDOUT0_FUNC_I2S9_TWS_DBG		           (45 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_HDA_SYNC_FUNC_HDA_SYNC				   (46 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_HDA_SYNC_FUNC_I2S0_WS				   (46 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_HDA_SYNC_FUNC_I2S9_RWS_DBG			   (46 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_HDA_SDIN1_FUNC_HDA_SDIN1			   (47 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_HDA_SDIN1_FUNC_GPIO063				   (47 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_HDA_SDIN1_FUNC_I2S9_DATA_IN1_DBG		   (47 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_HDA_SDOUT1_FUNC_HDA_SDOUT1			   (48 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_HDA_SDOUT1_FUNC_GPIO064				   (48 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_HDA_SDOUT1_FUNC_I2S9_DATA_OUT0_DBG		   (48 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_I2S1_MCLK_FUNC_I2S1_MCLK			   (49 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_I2S1_MCLK_FUNC_GPIO065				   (49 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_I2S1_SCK_FUNC_I2S1_SCK				   (50 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_I2S1_SCK_FUNC_GPIO066				   (50 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_I2S1_WS_FUNC_I2S1_WS				   (51 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_I2S1_WS_FUNC_GPIO067				   (51 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_I2S1_DATA_IN_FUNC_I2S1_DATA_IN			   (52 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_I2S1_DATA_IN_FUNC_GPIO068			   (52 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_I2S1_DATA_OUT_FUNC_I2S1_DATA_OUT		   (53 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_I2S1_DATA_OUT_FUNC_GPIO069			   (53 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_I2S2_MCLK_FUNC_I2S2_MCLK			   (54 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_I2S2_MCLK_FUNC_GPIO070				   (54 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_I2S2_RSCK_FUNC_I2S2_RSCK			   (55 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_I2S2_RSCK_FUNC_GPIO071				   (55 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_I2S2_RSCK_FUNC_I2S5_RSCK_DBG			   (55 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_I2S2_RSCK_FUNC_I2S6_RSCK_DBG			   (55 &lt;&lt; 8 | 0x3)</div><div class='add'>+#define CIX_PAD_I2S2_RWS_FUNC_I2S2_RWS				   (56 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_I2S2_RWS_FUNC_GPIO072				   (56 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_I2S2_RWS_FUNC_I2S5_RWS_DBG			   (56 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_I2S2_RWS_FUNC_I2S6_RWS_DBG			   (56 &lt;&lt; 8 | 0x3)</div><div class='add'>+#define CIX_PAD_I2S2_TSCK_FUNC_I2S2_TSCK			   (57 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_I2S2_TSCK_FUNC_GPIO073				   (57 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_I2S2_TSCK_FUNC_I2S5_TSCK_DBG			   (57 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_I2S2_TSCK_FUNC_I2S6_TSCK_DBG			   (57 &lt;&lt; 8 | 0x3)</div><div class='add'>+#define CIX_PAD_I2S2_TWS_FUNC_I2S2_TWS				   (58 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_I2S2_TWS_FUNC_GPIO074				   (58 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_I2S2_TWS_FUNC_I2S5_TWS_DBG			   (58 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_I2S2_TWS_FUNC_I2S6_TWS_DBG			   (58 &lt;&lt; 8 | 0x3)</div><div class='add'>+#define CIX_PAD_I2S2_DATA_IN0_FUNC_I2S2_DATA_IN0		   (59 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_I2S2_DATA_IN0_FUNC_GPIO075			   (59 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_I2S2_DATA_IN0_FUNC_I2S5_DATA_IN0_DBG		   (59 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_I2S2_DATA_IN0_FUNC_I2S6_DATA_IN0_DBG		   (59 &lt;&lt; 8 | 0x3)</div><div class='add'>+#define CIX_PAD_I2S2_DATA_IN1_FUNC_I2S2_DATA_IN1		   (60 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_I2S2_DATA_IN1_FUNC_GPIO076			   (60 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_I2S2_DATA_IN1_FUNC_I2S5_DATA_IN1_DBG		   (60 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_I2S2_DATA_IN1_FUNC_I2S6_DATA_IN1_DBG		   (60 &lt;&lt; 8 | 0x3)</div><div class='add'>+#define CIX_PAD_I2S2_DATA_OUT0_FUNC_I2S2_DATA_OUT0		   (61 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_I2S2_DATA_OUT0_FUNC_GPIO077			   (61 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_I2S2_DATA_OUT0_FUNC_I2S5_DATA_OUT0_DBG		   (61 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_I2S2_DATA_OUT0_FUNC_I2S6_DATA_OUT0_DBG		   (61 &lt;&lt; 8 | 0x3)</div><div class='add'>+#define CIX_PAD_I2S2_DATA_OUT1_FUNC_I2S2_DATA_OUT1		   (62 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_I2S2_DATA_OUT1_FUNC_GPIO078			   (62 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_I2S2_DATA_OUT1_FUNC_I2S5_DATA_OUT1_DBG		   (62 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_I2S2_DATA_OUT1_FUNC_I2S6_DATA_OUT1_DBG		   (62 &lt;&lt; 8 | 0x3)</div><div class='add'>+#define CIX_PAD_I2S2_DATA_OUT2_FUNC_I2S2_DATA_OUT2		   (63 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_I2S2_DATA_OUT2_FUNC_GPIO079			   (63 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_I2S2_DATA_OUT3_FUNC_I2S2_DATA_OUT3		   (64 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_I2S2_DATA_OUT3_FUNC_GPIO080			   (64 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_I2S2_DATA_OUT3_FUNC_I2S9_DATA_OUT1_DBG		   (64 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_I2S3_MCLK_FUNC_I2S3_MCLK			   (65 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_I2S3_MCLK_FUNC_GPIO081				   (65 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_I2S3_RSCK_FUNC_I2S3_RSCK			   (66 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_I2S3_RSCK_FUNC_GPIO082				   (66 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_I2S3_RSCK_FUNC_I2S7_RSCK_DBG			   (66 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_I2S3_RSCK_FUNC_I2S8_RSCK_DBG			   (66 &lt;&lt; 8 | 0x3)</div><div class='add'>+#define CIX_PAD_I2S3_RWS_FUNC_I2S3_RWS				   (67 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_I2S3_RWS_FUNC_GPIO083				   (67 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_I2S3_RWS_FUNC_I2S7_RWS_DBG			   (67 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_I2S3_RWS_FUNC_I2S8_RWS_DBG			   (67 &lt;&lt; 8 | 0x3)</div><div class='add'>+#define CIX_PAD_I2S3_TSCK_FUNC_I2S3_TSCK			   (68 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_I2S3_TSCK_FUNC_GPIO084				   (68 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_I2S3_TSCK_FUNC_I2S7_TSCK_DBG			   (68 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_I2S3_TSCK_FUNC_I2S8_TSCK_DBG			   (68 &lt;&lt; 8 | 0x3)</div><div class='add'>+#define CIX_PAD_I2S3_TWS_FUNC_I2S3_TWS				   (69 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_I2S3_TWS_FUNC_GPIO085				   (69 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_I2S3_TWS_FUNC_I2S7_TWS_DBG			   (69 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_I2S3_TWS_FUNC_I2S8_TWS_DBG			   (69 &lt;&lt; 8 | 0x3)</div><div class='add'>+#define CIX_PAD_I2S3_DATA_IN0_FUNC_I2S3_DATA_IN0		   (70 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_I2S3_DATA_IN0_FUNC_GPIO086			   (70 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_I2S3_DATA_IN0_FUNC_I2S7_DATA_IN0_DBG		   (70 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_I2S3_DATA_IN0_FUNC_I2S8_DATA_IN0_DBG		   (70 &lt;&lt; 8 | 0x3)</div><div class='add'>+#define CIX_PAD_I2S3_DATA_IN1_FUNC_I2S3_DATA_IN1		   (71 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_I2S3_DATA_IN1_FUNC_GPIO087			   (71 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_I2S3_DATA_IN1_FUNC_I2S7_DATA_IN1_DBG		   (71 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_I2S3_DATA_IN1_FUNC_I2S8_DATA_IN1_DBG		   (71 &lt;&lt; 8 | 0x3)</div><div class='add'>+#define CIX_PAD_I2S3_DATA_OUT0_FUNC_I2S3_DATA_OUT0		   (72 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_I2S3_DATA_OUT0_FUNC_GPIO088			   (72 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_I2S3_DATA_OUT0_FUNC_I2S7_DATA_OUT0_DBG		   (72 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_I2S3_DATA_OUT0_FUNC_I2S8_DATA_OUT0_DBG		   (72 &lt;&lt; 8 | 0x3)</div><div class='add'>+#define CIX_PAD_I2S3_DATA_OUT1_FUNC_I2S3_DATA_OUT1		   (73 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_I2S3_DATA_OUT1_FUNC_GPIO089			   (73 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_I2S3_DATA_OUT1_FUNC_I2S7_DATA_OUT1_DBG		   (73 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_I2S3_DATA_OUT1_FUNC_I2S8_DATA_OUT1_DBG		   (73 &lt;&lt; 8 | 0x3)</div><div class='add'>+#define CIX_PAD_GPIO090_FUNC_GPIO090				   (74 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO090_FUNC_I2S4_MCLK_LB			   (74 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO091_FUNC_GPIO091				   (75 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO091_FUNC_I2S4_SCK_LB			   (75 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO092_FUNC_GPIO092				   (76 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO092_FUNC_I2S4_WS_LB				   (76 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO093_FUNC_GPIO093				   (77 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO093_FUNC_I2S4_DATA_IN_LB			   (77 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO094_FUNC_GPIO094				   (78 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO094_FUNC_I2S4_DATA_OUT_LB			   (78 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_UART0_TXD_FUNC_UART0_TXD			   (79 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_UART0_TXD_FUNC_PWM0				   (79 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_UART0_TXD_FUNC_GPIO095				   (79 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_UART0_RXD_FUNC_UART0_RXD			   (80 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_UART0_RXD_FUNC_PWM1				   (80 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_UART0_RXD_FUNC_GPIO096				   (80 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_UART0_CTS_FUNC_UART0_CTS			   (81 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_UART0_CTS_FUNC_FAN_OUT2				   (81 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_UART0_CTS_FUNC_GPIO097				   (81 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_UART0_RTS_FUNC_UART0_RTS			   (82 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_UART0_RTS_FUNC_FAN_TACH2			   (82 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_UART0_RTS_FUNC_GPIO098				   (82 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_UART1_TXD_FUNC_UART1_TXD			   (83 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_UART1_TXD_FUNC_FAN_OUT0				   (83 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_UART1_TXD_FUNC_GPIO099				   (83 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_UART1_RXD_FUNC_UART1_RXD			   (84 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_UART1_RXD_FUNC_FAN_TACH0			   (84 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_UART1_RXD_FUNC_GPIO100				   (84 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_UART1_CTS_FUNC_UART1_CTS			   (85 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_UART1_CTS_FUNC_FAN_OUT1				   (85 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_UART1_CTS_FUNC_GPIO101				   (85 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_UART1_RTS_FUNC_UART1_RTS			   (86 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_UART1_RTS_FUNC_FAN_TACH1			   (86 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_UART1_RTS_FUNC_GPIO102				   (86 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_UART2_TXD_FUNC_UART2_TXD			   (87 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_UART2_TXD_FUNC_GPIO103				   (87 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_UART2_RXD_FUNC_UART2_RXD			   (88 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_UART2_RXD_FUNC_GPIO104				   (88 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_UART3_TXD_FUNC_UART3_TXD			   (89 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_UART3_TXD_FUNC_GPIO105				   (89 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_UART3_RXD_FUNC_UART3_RXD			   (90 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_UART3_RXD_FUNC_GPIO106				   (90 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_UART3_CTS_FUNC_UART3_CTS			   (91 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_UART3_CTS_FUNC_GPIO107				   (91 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_UART3_CTS_FUNC_TRIGIN0				   (91 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_UART3_RTS_FUNC_UART3_RTS			   (92 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_UART3_RTS_FUNC_GPIO108				   (92 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_UART3_RTS_FUNC_TRIGIN1				   (92 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_UART4_CSU_PM_TXD_FUNC_UART4_CSU_PM_TXD		   (93 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_UART4_CSU_PM_TXD_FUNC_GPIO109			   (93 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_UART4_CSU_PM_RXD_FUNC_UART4_CSU_PM_RXD		   (94 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_UART4_CSU_PM_RXD_FUNC_GPIO110			   (94 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_UART5_CSU_SE_TXD_FUNC_UART5_CSU_SE_TXD		   (95 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_UART5_CSU_SE_TXD_FUNC_GPIO111			   (95 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_UART5_CSU_SE_RXD_FUNC_UART5_CSU_SE_RXD		   (96 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_UART5_CSU_SE_RXD_FUNC_GPIO112			   (96 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_UART6_CSU_SE_RXD_FUNC_UART6_CSU_SE_RXD		   (97 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_UART6_CSU_SE_RXD_FUNC_GPIO113			   (97 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_CLK_REQ0_L_FUNC_CLK_REQ0_L			   (98 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_CLK_REQ0_L_FUNC_GPIO114				   (98 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_CLK_REQ2_L_FUNC_CLK_REQ2_L			   (99 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_CLK_REQ2_L_FUNC_GPIO115				   (99 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_CLK_REQ4_L_FUNC_CLK_REQ4_L			   (100 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_CLK_REQ4_L_FUNC_GPIO116				   (100 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_CSI0_MCLK0_FUNC_CSI0_MCLK0			   (101 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_CSI0_MCLK0_FUNC_GPIO117				   (101 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_CSI0_MCLK1_FUNC_CSI0_MCLK1			   (102 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_CSI0_MCLK1_FUNC_GPIO118				   (102 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_CSI1_MCLK0_FUNC_CSI1_MCLK0			   (103 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_CSI1_MCLK0_FUNC_GPIO119				   (103 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_CSI1_MCLK1_FUNC_CSI1_MCLK1			   (104 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_CSI1_MCLK1_FUNC_GPIO120				   (104 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO121_FUNC_GPIO121				   (105 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO121_FUNC_GMAC0_REFCLK_25M			   (105 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO122_FUNC_GPIO122				   (106 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO122_FUNC_GMAC0_TX_CTL			   (106 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO123_FUNC_GPIO123				   (107 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO123_FUNC_GMAC0_TXD0				   (107 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO124_FUNC_GPIO124				   (108 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO124_FUNC_GMAC0_TXD1				   (108 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO125_FUNC_GPIO125				   (109 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO125_FUNC_GMAC0_TXD2				   (109 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO126_FUNC_GPIO126				   (110 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO126_FUNC_GMAC0_TXD3				   (110 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO127_FUNC_GPIO127				   (111 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO127_FUNC_GMAC0_TX_CLK			   (111 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO128_FUNC_GPIO128				   (112 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO128_FUNC_GMAC0_RX_CTL			   (112 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO129_FUNC_GPIO129				   (113 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO129_FUNC_GMAC0_RXD0				   (113 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO130_FUNC_GPIO130				   (114 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO130_FUNC_GMAC0_RXD1				   (114 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO131_FUNC_GPIO131				   (115 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO131_FUNC_GMAC0_RXD2				   (115 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO132_FUNC_GPIO132				   (116 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO132_FUNC_GMAC0_RXD3				   (116 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO133_FUNC_GPIO133				   (117 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO133_FUNC_GMAC0_RX_CLK			   (117 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO134_FUNC_GPIO134				   (118 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO134_FUNC_GMAC0_MDC				   (118 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO135_FUNC_GPIO135				   (119 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO135_FUNC_GMAC0_MDIO				   (119 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO136_FUNC_GPIO136				   (120 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO136_FUNC_GMAC1_REFCLK_25M			   (120 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO137_FUNC_GPIO137				   (121 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO137_FUNC_GMAC1_TX_CTL			   (121 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO138_FUNC_GPIO138				   (122 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO138_FUNC_GMAC1_TXD0				   (122 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO138_FUNC_SPI2_MISO				   (122 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_GPIO139_FUNC_GPIO139				   (123 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO139_FUNC_GMAC1_TXD1				   (123 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO139_FUNC_SPI2_CS0				   (123 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_GPIO140_FUNC_GPIO140				   (124 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO140_FUNC_GMAC1_TXD2				   (124 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO140_FUNC_SPI2_CS1				   (124 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_GPIO141_FUNC_GPIO141				   (125 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO141_FUNC_GMAC1_TXD3				   (125 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO141_FUNC_SPI2_MOSI				   (125 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_GPIO142_FUNC_GPIO142				   (126 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO142_FUNC_GMAC1_TX_CLK			   (126 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO142_FUNC_SPI2_CLK				   (126 &lt;&lt; 8 | 0x2)</div><div class='add'>+#define CIX_PAD_GPIO143_FUNC_GPIO143				   (127 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO143_FUNC_GMAC1_RX_CTL			   (127 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO144_FUNC_GPIO144				   (128 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO144_FUNC_GMAC1_RXD0				   (128 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO145_FUNC_GPIO145				   (129 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO145_FUNC_GMAC1_RXD1				   (129 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO146_FUNC_GPIO146				   (130 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO146_FUNC_GMAC1_RXD2				   (130 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO147_FUNC_GPIO147				   (131 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO147_FUNC_GMAC1_RXD3				   (131 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO148_FUNC_GPIO148				   (132 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO148_FUNC_GMAC1_RX_CLK			   (132 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO149_FUNC_GPIO149				   (133 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO149_FUNC_GMAC1_MDC				   (133 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO150_FUNC_GPIO150				   (134 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO150_FUNC_GMAC1_MDIO				   (134 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO151_FUNC_GPIO151				   (135 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO151_FUNC_PM_GPIO0				   (135 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO152_FUNC_GPIO152				   (136 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO152_FUNC_PM_GPIO1				   (136 &lt;&lt; 8 | 0x1)</div><div class='add'>+#define CIX_PAD_GPIO153_FUNC_GPIO153				   (137 &lt;&lt; 8 | 0x0)</div><div class='add'>+#define CIX_PAD_GPIO153_FUNC_PM_GPIO2				   (137 &lt;&lt; 8 | 0x1)</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi<br/>new file mode 100644<br/>index 000000000000..64b76905cbff<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/cix/sky1.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/cix/sky1.dtsi</a></div><div class='hunk'>@@ -0,0 +1,586 @@</div><div class='add'>+// SPDX-License-Identifier: BSD-3-Clause</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2025 Cix Technology Group Co., Ltd.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/cix,sky1.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			compatible = "arm,cortex-a520";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			reg = &lt;0x0 0x0&gt;;</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			capacity-dmips-mhz = &lt;403&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@100 {</div><div class='add'>+			compatible = "arm,cortex-a520";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			reg = &lt;0x0 0x100&gt;;</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			capacity-dmips-mhz = &lt;403&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@200 {</div><div class='add'>+			compatible = "arm,cortex-a520";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			reg = &lt;0x0 0x200&gt;;</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			capacity-dmips-mhz = &lt;403&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@300 {</div><div class='add'>+			compatible = "arm,cortex-a520";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			reg = &lt;0x0 0x300&gt;;</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			capacity-dmips-mhz = &lt;403&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu4: cpu@400 {</div><div class='add'>+			compatible = "arm,cortex-a720";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			reg = &lt;0x0 0x400&gt;;</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu5: cpu@500 {</div><div class='add'>+			compatible = "arm,cortex-a720";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			reg = &lt;0x0 0x500&gt;;</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu6: cpu@600 {</div><div class='add'>+			compatible = "arm,cortex-a720";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			reg = &lt;0x0 0x600&gt;;</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu7: cpu@700 {</div><div class='add'>+			compatible = "arm,cortex-a720";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			reg = &lt;0x0 0x700&gt;;</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu8: cpu@800 {</div><div class='add'>+			compatible = "arm,cortex-a720";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			reg = &lt;0x0 0x800&gt;;</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu9: cpu@900 {</div><div class='add'>+			compatible = "arm,cortex-a720";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			reg = &lt;0x0 0x900&gt;;</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu10: cpu@a00 {</div><div class='add'>+			compatible = "arm,cortex-a720";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			reg = &lt;0x0 0xa00&gt;;</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu11: cpu@b00 {</div><div class='add'>+			compatible = "arm,cortex-a720";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			reg = &lt;0x0 0xb00&gt;;</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu-map {</div><div class='add'>+			cluster0 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu0&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu1&gt;;</div><div class='add'>+				};</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu2&gt;;</div><div class='add'>+				};</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu3&gt;;</div><div class='add'>+				};</div><div class='add'>+				core4 {</div><div class='add'>+					cpu = &lt;&amp;cpu4&gt;;</div><div class='add'>+				};</div><div class='add'>+				core5 {</div><div class='add'>+					cpu = &lt;&amp;cpu5&gt;;</div><div class='add'>+				};</div><div class='add'>+				core6 {</div><div class='add'>+					cpu = &lt;&amp;cpu6&gt;;</div><div class='add'>+				};</div><div class='add'>+				core7 {</div><div class='add'>+					cpu = &lt;&amp;cpu7&gt;;</div><div class='add'>+				};</div><div class='add'>+				core8 {</div><div class='add'>+					cpu = &lt;&amp;cpu8&gt;;</div><div class='add'>+				};</div><div class='add'>+				core9 {</div><div class='add'>+					cpu = &lt;&amp;cpu9&gt;;</div><div class='add'>+				};</div><div class='add'>+				core10 {</div><div class='add'>+					cpu = &lt;&amp;cpu10&gt;;</div><div class='add'>+				};</div><div class='add'>+				core11 {</div><div class='add'>+					cpu = &lt;&amp;cpu11&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	firmware {</div><div class='add'>+		ap_to_pm_scmi: scmi {</div><div class='add'>+			compatible = "arm,scmi";</div><div class='add'>+			mbox-names = "tx", "rx";</div><div class='add'>+			mboxes = &lt;&amp;mbox_ap2pm 8&gt;, &lt;&amp;mbox_pm2ap 8&gt;;</div><div class='add'>+			shmem = &lt;&amp;ap2pm_scmi_mem&gt;, &lt;&amp;pm2ap_scmi_mem&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			scmi_clk: protocol@14 {</div><div class='add'>+				reg = &lt;0x14&gt;;</div><div class='add'>+				#clock-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu-a520 {</div><div class='add'>+		compatible = "arm,cortex-a520-pmu";</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &amp;ppi_partition0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu-a720 {</div><div class='add'>+		compatible = "arm,cortex-a720-pmu";</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &amp;ppi_partition1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-1.0";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc@0 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		ranges = &lt;0 0 0 0 0x20 0&gt;;</div><div class='add'>+		dma-ranges;</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		i2c0: i2c@4010000 {</div><div class='add'>+			compatible = "cdns,i2c-r1p14";</div><div class='add'>+			reg = &lt;0x0 0x04010000 0x0 0x10000&gt;;</div><div class='add'>+			clock-frequency = &lt;400000&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_clk CLK_TREE_FCH_I2C0_APB&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c1: i2c@4020000 {</div><div class='add'>+			compatible = "cdns,i2c-r1p14";</div><div class='add'>+			reg = &lt;0x0 0x04020000 0x0 0x10000&gt;;</div><div class='add'>+			clock-frequency = &lt;400000&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_clk CLK_TREE_FCH_I2C1_APB&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c2: i2c@4030000 {</div><div class='add'>+			compatible = "cdns,i2c-r1p14";</div><div class='add'>+			reg = &lt;0x0 0x04030000 0x0 0x10000&gt;;</div><div class='add'>+			clock-frequency = &lt;400000&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_clk CLK_TREE_FCH_I2C2_APB&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c3: i2c@4040000 {</div><div class='add'>+			compatible = "cdns,i2c-r1p14";</div><div class='add'>+			reg = &lt;0x0 0x04040000 0x0 0x10000&gt;;</div><div class='add'>+			clock-frequency = &lt;400000&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_clk CLK_TREE_FCH_I2C3_APB&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c4: i2c@4050000 {</div><div class='add'>+			compatible = "cdns,i2c-r1p14";</div><div class='add'>+			reg = &lt;0x0 0x04050000 0x0 0x10000&gt;;</div><div class='add'>+			clock-frequency = &lt;400000&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_clk CLK_TREE_FCH_I2C4_APB&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c5: i2c@4060000 {</div><div class='add'>+			compatible = "cdns,i2c-r1p14";</div><div class='add'>+			reg = &lt;0x0 0x04060000 0x0 0x10000&gt;;</div><div class='add'>+			clock-frequency = &lt;400000&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_clk CLK_TREE_FCH_I2C5_APB&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c6: i2c@4070000 {</div><div class='add'>+			compatible = "cdns,i2c-r1p14";</div><div class='add'>+			reg = &lt;0x0 0x04070000 0x0 0x10000&gt;;</div><div class='add'>+			clock-frequency = &lt;400000&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_clk CLK_TREE_FCH_I2C6_APB&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c7: i2c@4080000 {</div><div class='add'>+			compatible = "cdns,i2c-r1p14";</div><div class='add'>+			reg = &lt;0x0 0x04080000 0x0 0x10000&gt;;</div><div class='add'>+			clock-frequency = &lt;400000&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_clk CLK_TREE_FCH_I2C7_APB&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi0: spi@4090000 {</div><div class='add'>+			compatible = "cix,sky1-spi-r1p6", "cdns,spi-r1p6";</div><div class='add'>+			reg = &lt;0x0 0x04090000 0x0 0x10000&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_clk CLK_TREE_FCH_SPI0_APB&gt;,</div><div class='add'>+				 &lt;&amp;scmi_clk CLK_TREE_FCH_SPI0_APB&gt;;</div><div class='add'>+			clock-names = "ref_clk", "pclk";</div><div class='add'>+			interrupts = &lt;GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi1: spi@40a0000 {</div><div class='add'>+			compatible = "cix,sky1-spi-r1p6", "cdns,spi-r1p6";</div><div class='add'>+			reg = &lt;0x0 0x040a0000 0x0 0x10000&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_clk CLK_TREE_FCH_SPI1_APB&gt;,</div><div class='add'>+				 &lt;&amp;scmi_clk CLK_TREE_FCH_SPI1_APB&gt;;</div><div class='add'>+			clock-names = "ref_clk", "pclk";</div><div class='add'>+			interrupts = &lt;GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart0: serial@40b0000 {</div><div class='add'>+			compatible = "arm,pl011", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x040b0000 0x0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_clk CLK_TREE_FCH_UART0_FUNC&gt;, &lt;&amp;scmi_clk CLK_TREE_FCH_UART0_APB&gt;;</div><div class='add'>+			clock-names = "uartclk", "apb_pclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart1: serial@40c0000 {</div><div class='add'>+			compatible = "arm,pl011", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x040c0000 0x0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_clk CLK_TREE_FCH_UART1_FUNC&gt;, &lt;&amp;scmi_clk CLK_TREE_FCH_UART1_APB&gt;;</div><div class='add'>+			clock-names = "uartclk", "apb_pclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart2: serial@40d0000 {</div><div class='add'>+			compatible = "arm,pl011", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x040d0000 0x0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_clk CLK_TREE_FCH_UART2_FUNC&gt;, &lt;&amp;scmi_clk CLK_TREE_FCH_UART2_APB&gt;;</div><div class='add'>+			clock-names = "uartclk", "apb_pclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart3: serial@40e0000 {</div><div class='add'>+			compatible = "arm,pl011", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x040e0000 0x0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_clk CLK_TREE_FCH_UART3_FUNC&gt;, &lt;&amp;scmi_clk CLK_TREE_FCH_UART3_APB&gt;;</div><div class='add'>+			clock-names = "uartclk", "apb_pclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i3c0: i3c@40f0000 {</div><div class='add'>+			compatible = "cdns,i3c-master";</div><div class='add'>+			reg = &lt;0x0 0x040f0000 0x0 0x10000&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_clk CLK_TREE_FCH_I3C0_APB&gt;,</div><div class='add'>+				 &lt;&amp;scmi_clk CLK_TREE_FCH_I3C0_FUNC&gt;;</div><div class='add'>+			clock-names = "pclk", "sysclk";</div><div class='add'>+			i3c-scl-hz = &lt;400000&gt;;</div><div class='add'>+			i2c-scl-hz = &lt;100000&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i3c1: i3c@4100000 {</div><div class='add'>+			compatible = "cdns,i3c-master";</div><div class='add'>+			reg = &lt;0x0 0x04100000 0x0 0x10000&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_clk CLK_TREE_FCH_I3C1_APB&gt;,</div><div class='add'>+				 &lt;&amp;scmi_clk CLK_TREE_FCH_I3C1_FUNC&gt;;</div><div class='add'>+			clock-names = "pclk", "sysclk";</div><div class='add'>+			i3c-scl-hz = &lt;400000&gt;;</div><div class='add'>+			i2c-scl-hz = &lt;100000&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		iomuxc: pinctrl@4170000 {</div><div class='add'>+			compatible = "cix,sky1-pinctrl";</div><div class='add'>+			reg = &lt;0x0 0x04170000 0x0 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mbox_ap2se: mailbox@5060000 {</div><div class='add'>+			compatible = "cix,sky1-mbox";</div><div class='add'>+			reg = &lt;0x0 0x05060000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			#mbox-cells = &lt;1&gt;;</div><div class='add'>+			cix,mbox-dir = "tx";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mbox_se2ap: mailbox@5070000 {</div><div class='add'>+			compatible = "cix,sky1-mbox";</div><div class='add'>+			reg = &lt;0x0 0x05070000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			#mbox-cells = &lt;1&gt;;</div><div class='add'>+			cix,mbox-dir = "rx";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ap2pm_scmi_mem: shmem@6590000 {</div><div class='add'>+			compatible = "arm,scmi-shmem";</div><div class='add'>+			reg = &lt;0x0 0x06590000 0x0 0x80&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mbox_ap2pm: mailbox@6590080 {</div><div class='add'>+			compatible = "cix,sky1-mbox";</div><div class='add'>+			reg = &lt;0x0 0x06590080 0x0 0xff80&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			#mbox-cells = &lt;1&gt;;</div><div class='add'>+			cix,mbox-dir = "tx";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pm2ap_scmi_mem: shmem@65a0000 {</div><div class='add'>+			compatible = "arm,scmi-shmem";</div><div class='add'>+			reg = &lt;0x0 0x065a0000 0x0 0x80&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mbox_pm2ap: mailbox@65a0080 {</div><div class='add'>+			compatible = "cix,sky1-mbox";</div><div class='add'>+			reg = &lt;0x0 0x065a0080 0x0 0xff80&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			#mbox-cells = &lt;1&gt;;</div><div class='add'>+			cix,mbox-dir = "rx";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mbox_sfh2ap: mailbox@8090000 {</div><div class='add'>+			compatible = "cix,sky1-mbox";</div><div class='add'>+			reg = &lt;0x0 0x08090000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			#mbox-cells = &lt;1&gt;;</div><div class='add'>+			cix,mbox-dir = "rx";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mbox_ap2sfh: mailbox@80a0000 {</div><div class='add'>+			compatible = "cix,sky1-mbox";</div><div class='add'>+			reg = &lt;0x0 0x080a0000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			#mbox-cells = &lt;1&gt;;</div><div class='add'>+			cix,mbox-dir = "tx";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie_x8_rc: pcie@a010000 {</div><div class='add'>+			compatible = "cix,sky1-pcie-host";</div><div class='add'>+			reg = &lt;0x00 0x0a010000 0x00 0x10000&gt;,</div><div class='add'>+			      &lt;0x00 0x2c000000 0x00 0x4000000&gt;,</div><div class='add'>+			      &lt;0x00 0x0a000300 0x00 0x100&gt;,</div><div class='add'>+			      &lt;0x00 0x0a000400 0x00 0x100&gt;,</div><div class='add'>+			      &lt;0x00 0x60000000 0x00 0x00100000&gt;;</div><div class='add'>+			reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg";</div><div class='add'>+			ranges = &lt;0x01000000 0x0 0x60100000 0x0 0x60100000 0x0 0x00100000&gt;,</div><div class='add'>+				 &lt;0x02000000 0x0 0x60200000 0x0 0x60200000 0x0 0x1fe00000&gt;,</div><div class='add'>+				 &lt;0x43000000 0x18 0x00000000 0x18 0x00000000 0x04 0x00000000&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			bus-range = &lt;0xc0 0xff&gt;;</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0x7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;gic 0 0 GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;gic 0 0 GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;gic 0 0 GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;gic 0 0 GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			msi-map = &lt;0xc000 &amp;gic_its 0xc000 0x4000&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie_x4_rc: pcie@a070000 {</div><div class='add'>+			compatible = "cix,sky1-pcie-host";</div><div class='add'>+			reg = &lt;0x00 0x0a070000 0x00 0x10000&gt;,</div><div class='add'>+			      &lt;0x00 0x29000000 0x00 0x3000000&gt;,</div><div class='add'>+			      &lt;0x00 0x0a060300 0x00 0x40&gt;,</div><div class='add'>+			      &lt;0x00 0x0a060400 0x00 0x40&gt;,</div><div class='add'>+			      &lt;0x00 0x50000000 0x00 0x00100000&gt;;</div><div class='add'>+			reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg";</div><div class='add'>+			ranges = &lt;0x01000000 0x00 0x50100000 0x00 0x50100000 0x00 0x00100000&gt;,</div><div class='add'>+				 &lt;0x02000000 0x00 0x50200000 0x00 0x50200000 0x00 0x0fe00000&gt;,</div><div class='add'>+				 &lt;0x43000000 0x14 0x00000000 0x14 0x00000000 0x04 0x00000000&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			bus-range = &lt;0x90 0xbf&gt;;</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0x7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;gic 0 0 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;gic 0 0 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;gic 0 0 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;gic 0 0 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			msi-map = &lt;0x9000 &amp;gic_its 0x9000 0x3000&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie_x2_rc: pcie@a0c0000 {</div><div class='add'>+			compatible = "cix,sky1-pcie-host";</div><div class='add'>+			reg = &lt;0x00 0x0a0c0000 0x00 0x10000&gt;,</div><div class='add'>+			      &lt;0x00 0x26000000 0x00 0x3000000&gt;,</div><div class='add'>+			      &lt;0x00 0x0a0600340 0x00 0x20&gt;,</div><div class='add'>+			      &lt;0x00 0x0a0600440 0x00 0x20&gt;,</div><div class='add'>+			      &lt;0x00 0x40000000 0x00 0x00100000&gt;;</div><div class='add'>+			reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg";</div><div class='add'>+			ranges = &lt;0x01000000 0x0 0x40100000 0x0 0x40100000 0x0 0x00100000&gt;,</div><div class='add'>+				 &lt;0x02000000 0x0 0x40200000 0x0 0x40200000 0x0 0x0fe00000&gt;,</div><div class='add'>+				 &lt;0x43000000 0x10 0x00000000 0x10 0x00000000 0x04 0x00000000&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			bus-range = &lt;0x60 0x8f&gt;;</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0x7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;gic 0 0 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;gic 0 0 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;gic 0 0 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;gic 0 0 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			msi-map = &lt;0x6000 &amp;gic_its 0x6000 0x3000&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie_x1_0_rc: pcie@a0d0000 {</div><div class='add'>+			compatible = "cix,sky1-pcie-host";</div><div class='add'>+			reg = &lt;0x00 0x0a0d0000 0x00 0x10000&gt;,</div><div class='add'>+			      &lt;0x00 0x20000000 0x00 0x3000000&gt;,</div><div class='add'>+			      &lt;0x00 0x0a060360 0x00 0x20&gt;,</div><div class='add'>+			      &lt;0x00 0x0a060460 0x00 0x20&gt;,</div><div class='add'>+			      &lt;0x00 0x30000000 0x00 0x00100000&gt;;</div><div class='add'>+			reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg";</div><div class='add'>+			ranges = &lt;0x01000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000&gt;,</div><div class='add'>+				 &lt;0x02000000 0x0 0x30200000 0x0 0x30200000 0x0 0x07e00000&gt;,</div><div class='add'>+				 &lt;0x43000000 0x08 0x00000000 0x08 0x00000000 0x04 0x00000000&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			bus-range = &lt;0x00 0x2f&gt;;</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0x7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;gic 0 0 GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;gic 0 0 GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;gic 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;gic 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			msi-map = &lt;0x0000 &amp;gic_its 0x0000 0x3000&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie_x1_1_rc: pcie@a0e0000 {</div><div class='add'>+			compatible = "cix,sky1-pcie-host";</div><div class='add'>+			reg = &lt;0x00 0x0a0e0000 0x00 0x10000&gt;,</div><div class='add'>+			      &lt;0x00 0x23000000 0x00 0x3000000&gt;,</div><div class='add'>+			      &lt;0x00 0x0a060380 0x00 0x20&gt;,</div><div class='add'>+			      &lt;0x00 0x0a060480 0x00 0x20&gt;,</div><div class='add'>+			      &lt;0x00 0x38000000 0x00 0x00100000&gt;;</div><div class='add'>+			reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg";</div><div class='add'>+			ranges = &lt;0x01000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000&gt;,</div><div class='add'>+				 &lt;0x02000000 0x0 0x38200000 0x0 0x38200000 0x0 0x07e00000&gt;,</div><div class='add'>+				 &lt;0x43000000 0x0C 0x00000000 0x0C 0x00000000 0x04 0x00000000&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			bus-range = &lt;0x30 0x5f&gt;;</div><div class='add'>+			device_type = "pci";</div><div class='add'>+</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0x7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;gic 0 0 GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;gic 0 0 GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;gic 0 0 GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;gic 0 0 GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			msi-map = &lt;0x3000 &amp;gic_its 0x3000 0x3000&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@e010000 {</div><div class='add'>+			compatible = "arm,gic-v3";</div><div class='add'>+			reg = &lt;0x0 0x0e010000 0 0x10000&gt;,	/* GICD */</div><div class='add'>+			      &lt;0x0 0x0e090000 0 0x300000&gt;;       /* GICR * 12 */</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_LOW 0&gt;;</div><div class='add'>+			#interrupt-cells = &lt;4&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			gic_its: msi-controller@e050000 {</div><div class='add'>+				compatible = "arm,gic-v3-its";</div><div class='add'>+				reg = &lt;0x0 0x0e050000 0x0 0x30000&gt;;</div><div class='add'>+				msi-controller;</div><div class='add'>+				#msi-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ppi-partitions {</div><div class='add'>+				ppi_partition0: interrupt-partition-0 {</div><div class='add'>+					affinity = &lt;&amp;cpu0 &amp;cpu1 &amp;cpu2 &amp;cpu3&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				ppi_partition1: interrupt-partition-1 {</div><div class='add'>+					affinity = &lt;&amp;cpu4 &amp;cpu5 &amp;cpu6 &amp;cpu7 &amp;cpu8 &amp;cpu9 &amp;cpu10 &amp;cpu11&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		iomuxc_s5: pinctrl@16007000 {</div><div class='add'>+			compatible = "cix,sky1-pinctrl-s5";</div><div class='add'>+			reg = &lt;0x0 0x16007000 0x0 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0&gt;,</div><div class='add'>+			     &lt;GIC_PPI 12 IRQ_TYPE_LEVEL_LOW 0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/Makefile b/arch/arm64/boot/dts/exynos/Makefile<br/>index e0a2facde6a2..bcca63136557 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/Makefile?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/Makefile</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/Makefile</a></div><div class='hunk'>@@ -1,5 +1,22 @@</div><div class='ctx'> # SPDX-License-Identifier: GPL-2.0</div><div class='add'>+subdir-y += axis</div><div class='add'>+subdir-y += google</div><div class='add'>+</div><div class='ctx'> dtb-$(CONFIG_ARCH_EXYNOS) += \</div><div class='del'>-	exynos5433-tm2.dtb	\</div><div class='del'>-	exynos5433-tm2e.dtb	\</div><div class='del'>-	exynos7-espresso.dtb</div><div class='add'>+	exynos2200-g0s.dtb		\</div><div class='add'>+	exynos5433-tm2.dtb		\</div><div class='add'>+	exynos5433-tm2e.dtb		\</div><div class='add'>+	exynos7-espresso.dtb		\</div><div class='add'>+	exynos7870-a2corelte.dtb	\</div><div class='add'>+	exynos7870-j6lte.dtb		\</div><div class='add'>+	exynos7870-on7xelte.dtb		\</div><div class='add'>+	exynos7885-jackpotlte.dtb	\</div><div class='add'>+	exynos850-e850-96.dtb		\</div><div class='add'>+	exynos8895-dreamlte.dtb		\</div><div class='add'>+	exynos9810-starlte.dtb		\</div><div class='add'>+	exynos990-c1s.dtb		\</div><div class='add'>+	exynos990-r8s.dtb               \</div><div class='add'>+	exynos990-x1s.dtb		\</div><div class='add'>+	exynos990-x1slte.dtb		\</div><div class='add'>+	exynosautov9-sadk.dtb		\</div><div class='add'>+	exynosautov920-sadk.dtb</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/axis/Makefile b/arch/arm64/boot/dts/exynos/axis/Makefile<br/>new file mode 100644<br/>index 000000000000..ccf00de64016<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/axis/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/axis/Makefile</a></div><div class='hunk'>@@ -0,0 +1,4 @@</div><div class='add'>+# SPDX-License-Identifier: GPL-2.0</div><div class='add'>+</div><div class='add'>+dtb-$(CONFIG_ARCH_ARTPEC) += \</div><div class='add'>+	artpec8-grizzly.dtb</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/axis/artpec-pinctrl.h b/arch/arm64/boot/dts/exynos/axis/artpec-pinctrl.h<br/>new file mode 100644<br/>index 000000000000..2c151aa98c96<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/axis/artpec-pinctrl.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/axis/artpec-pinctrl.h</a></div><div class='hunk'>@@ -0,0 +1,36 @@</div><div class='add'>+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */</div><div class='add'>+/*</div><div class='add'>+ * Axis ARTPEC-8 SoC device tree pinctrl constants</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2025 Samsung Electronics Co., Ltd.</div><div class='add'>+ *             https://www.samsung.com</div><div class='add'>+ * Copyright (c) 2025  Axis Communications AB.</div><div class='add'>+ *             https://www.axis.com</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__</div><div class='add'>+#define __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__</div><div class='add'>+</div><div class='add'>+#define ARTPEC_PIN_PULL_NONE		0</div><div class='add'>+#define ARTPEC_PIN_PULL_DOWN		1</div><div class='add'>+#define ARTPEC_PIN_PULL_UP		3</div><div class='add'>+</div><div class='add'>+#define ARTPEC_PIN_FUNC_INPUT		0</div><div class='add'>+#define ARTPEC_PIN_FUNC_OUTPUT		1</div><div class='add'>+#define ARTPEC_PIN_FUNC_2		2</div><div class='add'>+#define ARTPEC_PIN_FUNC_3		3</div><div class='add'>+#define ARTPEC_PIN_FUNC_4		4</div><div class='add'>+#define ARTPEC_PIN_FUNC_5		5</div><div class='add'>+#define ARTPEC_PIN_FUNC_6		6</div><div class='add'>+#define ARTPEC_PIN_FUNC_EINT		0xf</div><div class='add'>+#define ARTPEC_PIN_FUNC_F		ARTPEC_PIN_FUNC_EINT</div><div class='add'>+</div><div class='add'>+/* Drive strength for ARTPEC */</div><div class='add'>+#define ARTPEC_PIN_DRV_SR1		0x8</div><div class='add'>+#define ARTPEC_PIN_DRV_SR2		0x9</div><div class='add'>+#define ARTPEC_PIN_DRV_SR3		0xa</div><div class='add'>+#define ARTPEC_PIN_DRV_SR4		0xb</div><div class='add'>+#define ARTPEC_PIN_DRV_SR5		0xc</div><div class='add'>+#define ARTPEC_PIN_DRV_SR6		0xd</div><div class='add'>+</div><div class='add'>+#endif /* __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__ */</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/axis/artpec8-grizzly.dts b/arch/arm64/boot/dts/exynos/axis/artpec8-grizzly.dts<br/>new file mode 100644<br/>index 000000000000..5ae864ec3193<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/axis/artpec8-grizzly.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/axis/artpec8-grizzly.dts</a></div><div class='hunk'>@@ -0,0 +1,35 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Axis ARTPEC-8 Grizzly board device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2025 Samsung Electronics Co., Ltd.</div><div class='add'>+ *             https://www.samsung.com</div><div class='add'>+ * Copyright (c) 2025  Axis Communications AB.</div><div class='add'>+ *             https://www.axis.com</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "artpec8.dtsi"</div><div class='add'>+#include "artpec8-pinctrl.dtsi"</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+/ {</div><div class='add'>+	model = "ARTPEC-8 grizzly board";</div><div class='add'>+	compatible = "axis,artpec8-grizzly", "axis,artpec8";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;serial_0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;serial_0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@80000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x80000000 0x0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;osc_clk {</div><div class='add'>+	clock-frequency = &lt;50000000&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi<br/>new file mode 100644<br/>index 000000000000..8d239a70f1b4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi</a></div><div class='hunk'>@@ -0,0 +1,120 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Axis ARTPEC-8 SoC pin-mux and pin-config device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2025 Samsung Electronics Co., Ltd.</div><div class='add'>+ *             https://www.samsung.com</div><div class='add'>+ * Copyright (c) 2025  Axis Communications AB.</div><div class='add'>+ *             https://www.axis.com</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "artpec-pinctrl.h"</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_fsys {</div><div class='add'>+	gpe0: gpe0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpe1: gpe1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpe2: gpe2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpf0: gpf0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpf1: gpf1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpf2: gpf2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpf3: gpf3-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpf4: gpf4-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gps0: gps0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gps1: gps1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	serial0_bus: serial0-bus-pins {</div><div class='add'>+		samsung,pins = "gpf4-4", "gpf4-5";</div><div class='add'>+		samsung,pin-function = &lt;ARTPEC_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;ARTPEC_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;ARTPEC_PIN_DRV_SR3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_peric {</div><div class='add'>+	gpa0: gpa0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpa1: gpa1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpa2: gpa2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpk0: gpk0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/axis/artpec8.dtsi b/arch/arm64/boot/dts/exynos/axis/artpec8.dtsi<br/>new file mode 100644<br/>index 000000000000..db9833297982<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/axis/artpec8.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/axis/artpec8.dtsi</a></div><div class='hunk'>@@ -0,0 +1,244 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Axis ARTPEC-8 SoC device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2025 Samsung Electronics Co., Ltd.</div><div class='add'>+ *             https://www.samsung.com</div><div class='add'>+ * Copyright (c) 2025  Axis Communications AB.</div><div class='add'>+ *             https://www.axis.com</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/axis,artpec8-clk.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "axis,artpec8";</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		pinctrl0 = &amp;pinctrl_fsys;</div><div class='add'>+		pinctrl1 = &amp;pinctrl_peric;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_sleep&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_cpucl CLK_GOUT_CPUCL_CLUSTER_CPU&gt;;</div><div class='add'>+			clock-names = "cpu";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@1 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x1&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_sleep&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@2 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x2&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_sleep&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@3 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x3&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_sleep&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		idle-states {</div><div class='add'>+			entry-method = "psci";</div><div class='add'>+</div><div class='add'>+			cpu_sleep: cpu-sleep {</div><div class='add'>+				compatible = "arm,idle-state";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x0010000&gt;;</div><div class='add'>+				local-timer-stop;</div><div class='add'>+				entry-latency-us = &lt;300&gt;;</div><div class='add'>+				exit-latency-us = &lt;1200&gt;;</div><div class='add'>+				min-residency-us = &lt;2000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fin_pll: clock-finpll {</div><div class='add'>+		compatible = "fixed-factor-clock";</div><div class='add'>+		clocks = &lt;&amp;osc_clk&gt;;</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-div = &lt;2&gt;;</div><div class='add'>+		clock-mult = &lt;1&gt;;</div><div class='add'>+		clock-output-names = "fin_pll";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	osc_clk: clock-osc {</div><div class='add'>+		/* XXTI */</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-output-names = "osc_clk";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu {</div><div class='add'>+		compatible = "arm,cortex-a53-pmu";</div><div class='add'>+		interrupts = &lt;GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-affinity = &lt;&amp;cpu0&gt;, &lt;&amp;cpu1&gt;, &lt;&amp;cpu2&gt;, &lt;&amp;cpu3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-0.2";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc: soc@0 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		ranges = &lt;0x0 0x0 0x0 0x17000000&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		cmu_imem: clock-controller@10010000 {</div><div class='add'>+			compatible = "axis,artpec8-cmu-imem";</div><div class='add'>+			reg = &lt;0x10010000 0x4000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;fin_pll&gt;,</div><div class='add'>+				 &lt;&amp;cmu_cmu CLK_DOUT_CMU_IMEM_ACLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_cmu CLK_DOUT_CMU_IMEM_JPEG&gt;;</div><div class='add'>+			clock-names = "fin_pll", "aclk", "jpeg";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		timer@10040000 {</div><div class='add'>+			compatible = "axis,artpec8-mct", "samsung,exynos4210-mct";</div><div class='add'>+			reg = &lt;0x10040000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;fin_pll&gt;, &lt;&amp;cmu_imem CLK_GOUT_IMEM_MCT_PCLK&gt;;</div><div class='add'>+			clock-names = "fin_pll", "mct";</div><div class='add'>+			interrupts = &lt;GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@10201000 {</div><div class='add'>+			compatible = "arm,gic-400";</div><div class='add'>+			reg = &lt;0x10201000 0x1000&gt;,</div><div class='add'>+			      &lt;0x10202000 0x2000&gt;,</div><div class='add'>+			      &lt;0x10204000 0x2000&gt;,</div><div class='add'>+			      &lt;0x10206000 0x2000&gt;;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_cpucl: clock-controller@11410000 {</div><div class='add'>+			compatible = "axis,artpec8-cmu-cpucl";</div><div class='add'>+			reg = &lt;0x11410000 0x4000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;fin_pll&gt;,</div><div class='add'>+				 &lt;&amp;cmu_cmu CLK_DOUT_CMU_CPUCL_SWITCH&gt;;</div><div class='add'>+			clock-names = "fin_pll", "switch";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_cmu: clock-controller@12400000 {</div><div class='add'>+			compatible = "axis,artpec8-cmu-cmu";</div><div class='add'>+			reg = &lt;0x12400000 0x4000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;fin_pll&gt;;</div><div class='add'>+			clock-names = "fin_pll";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_core: clock-controller@12410000 {</div><div class='add'>+			compatible = "axis,artpec8-cmu-core";</div><div class='add'>+			reg = &lt;0x12410000 0x4000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;fin_pll&gt;,</div><div class='add'>+				 &lt;&amp;cmu_cmu CLK_DOUT_CMU_CORE_MAIN&gt;,</div><div class='add'>+				 &lt;&amp;cmu_cmu CLK_DOUT_CMU_CORE_DLP&gt;;</div><div class='add'>+			clock-names = "fin_pll", "main", "dlp";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_bus: clock-controller@12c10000 {</div><div class='add'>+			compatible = "axis,artpec8-cmu-bus";</div><div class='add'>+			reg = &lt;0x12c10000 0x4000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;fin_pll&gt;,</div><div class='add'>+				 &lt;&amp;cmu_cmu CLK_DOUT_CMU_BUS&gt;,</div><div class='add'>+				 &lt;&amp;cmu_cmu CLK_DOUT_CMU_BUS_DLP&gt;;</div><div class='add'>+			clock-names = "fin_pll", "bus", "dlp";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_peri: clock-controller@16410000 {</div><div class='add'>+			compatible = "axis,artpec8-cmu-peri";</div><div class='add'>+			reg = &lt;0x16410000 0x4000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;fin_pll&gt;,</div><div class='add'>+				 &lt;&amp;cmu_cmu CLK_DOUT_CMU_PERI_IP&gt;,</div><div class='add'>+				 &lt;&amp;cmu_cmu CLK_DOUT_CMU_PERI_AUDIO&gt;,</div><div class='add'>+				 &lt;&amp;cmu_cmu CLK_DOUT_CMU_PERI_DISP&gt;;</div><div class='add'>+			clock-names = "fin_pll", "ip", "audio", "disp";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_peric: pinctrl@165f0000 {</div><div class='add'>+			compatible = "axis,artpec8-pinctrl";</div><div class='add'>+			reg = &lt;0x165f0000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_fsys: clock-controller@16c10000 {</div><div class='add'>+			compatible = "axis,artpec8-cmu-fsys";</div><div class='add'>+			reg = &lt;0x16c10000 0x4000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;fin_pll&gt;,</div><div class='add'>+				 &lt;&amp;cmu_cmu CLK_DOUT_CMU_FSYS_SCAN0&gt;,</div><div class='add'>+				 &lt;&amp;cmu_cmu CLK_DOUT_CMU_FSYS_SCAN1&gt;,</div><div class='add'>+				 &lt;&amp;cmu_cmu CLK_DOUT_CMU_FSYS_BUS&gt;,</div><div class='add'>+				 &lt;&amp;cmu_cmu CLK_DOUT_CMU_FSYS_IP&gt;;</div><div class='add'>+			clock-names = "fin_pll", "scan0", "scan1", "bus", "ip";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_fsys: pinctrl@16c30000 {</div><div class='add'>+			compatible = "axis,artpec8-pinctrl";</div><div class='add'>+			reg = &lt;0x16c30000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		serial_0: serial@16cc0000 {</div><div class='add'>+			compatible = "axis,artpec8-uart";</div><div class='add'>+			reg = &lt;0x16cc0000 0x100&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_fsys CLK_GOUT_FSYS_UART0_PCLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_fsys CLK_GOUT_FSYS_UART0_SCLK_UART&gt;;</div><div class='add'>+			clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+			interrupts = &lt;GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;serial0_bus&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/exynos-pinctrl.h b/arch/arm64/boot/dts/exynos/exynos-pinctrl.h<br/>new file mode 100644<br/>index 000000000000..7dd94a9b3652<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynos-pinctrl.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/exynos-pinctrl.h</a></div><div class='hunk'>@@ -0,0 +1,79 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0 */</div><div class='add'>+/*</div><div class='add'>+ * Samsung Exynos DTS pinctrl constants</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2016 Samsung Electronics Co., Ltd.</div><div class='add'>+ *		http://www.samsung.com</div><div class='add'>+ * Copyright (c) 2022 Linaro Ltd</div><div class='add'>+ * Author: Krzysztof Kozlowski &lt;krzk@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__</div><div class='add'>+#define __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__</div><div class='add'>+</div><div class='add'>+#define EXYNOS_PIN_PULL_NONE		0</div><div class='add'>+#define EXYNOS_PIN_PULL_DOWN		1</div><div class='add'>+#define EXYNOS_PIN_PULL_UP		3</div><div class='add'>+</div><div class='add'>+/* Pin function in power down mode */</div><div class='add'>+#define EXYNOS_PIN_PDN_OUT0		0</div><div class='add'>+#define EXYNOS_PIN_PDN_OUT1		1</div><div class='add'>+#define EXYNOS_PIN_PDN_INPUT		2</div><div class='add'>+#define EXYNOS_PIN_PDN_PREV		3</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Drive strengths for Exynos5410, Exynos542x, Exynos5800, Exynos7885, Exynos850</div><div class='add'>+ * (except GPIO_HSI block), ExynosAutov9 (FSI0, PERIC1)</div><div class='add'>+ */</div><div class='add'>+#define EXYNOS5420_PIN_DRV_LV1		0</div><div class='add'>+#define EXYNOS5420_PIN_DRV_LV2		1</div><div class='add'>+#define EXYNOS5420_PIN_DRV_LV3		2</div><div class='add'>+#define EXYNOS5420_PIN_DRV_LV4		3</div><div class='add'>+</div><div class='add'>+/* Drive strengths for Exynos5433 */</div><div class='add'>+#define EXYNOS5433_PIN_DRV_FAST_SR1	0</div><div class='add'>+#define EXYNOS5433_PIN_DRV_FAST_SR2	1</div><div class='add'>+#define EXYNOS5433_PIN_DRV_FAST_SR3	2</div><div class='add'>+#define EXYNOS5433_PIN_DRV_FAST_SR4	3</div><div class='add'>+#define EXYNOS5433_PIN_DRV_FAST_SR5	4</div><div class='add'>+#define EXYNOS5433_PIN_DRV_FAST_SR6	5</div><div class='add'>+#define EXYNOS5433_PIN_DRV_SLOW_SR1	8</div><div class='add'>+#define EXYNOS5433_PIN_DRV_SLOW_SR2	9</div><div class='add'>+#define EXYNOS5433_PIN_DRV_SLOW_SR3	0xa</div><div class='add'>+#define EXYNOS5433_PIN_DRV_SLOW_SR4	0xb</div><div class='add'>+#define EXYNOS5433_PIN_DRV_SLOW_SR5	0xc</div><div class='add'>+#define EXYNOS5433_PIN_DRV_SLOW_SR6	0xf</div><div class='add'>+</div><div class='add'>+/* Drive strengths for Exynos7 (except FSYS1) */</div><div class='add'>+#define EXYNOS7_PIN_DRV_LV1		0</div><div class='add'>+#define EXYNOS7_PIN_DRV_LV2		2</div><div class='add'>+#define EXYNOS7_PIN_DRV_LV3		1</div><div class='add'>+#define EXYNOS7_PIN_DRV_LV4		3</div><div class='add'>+</div><div class='add'>+/* Drive strengths for Exynos7 FSYS1 block */</div><div class='add'>+#define EXYNOS7_FSYS1_PIN_DRV_LV1	0</div><div class='add'>+#define EXYNOS7_FSYS1_PIN_DRV_LV2	4</div><div class='add'>+#define EXYNOS7_FSYS1_PIN_DRV_LV3	2</div><div class='add'>+#define EXYNOS7_FSYS1_PIN_DRV_LV4	6</div><div class='add'>+#define EXYNOS7_FSYS1_PIN_DRV_LV5	1</div><div class='add'>+#define EXYNOS7_FSYS1_PIN_DRV_LV6	5</div><div class='add'>+</div><div class='add'>+/* Drive strengths for Exynos850 GPIO_HSI block */</div><div class='add'>+#define EXYNOS850_HSI_PIN_DRV_LV1	0	/* 1x   */</div><div class='add'>+#define EXYNOS850_HSI_PIN_DRV_LV1_5	1	/* 1.5x */</div><div class='add'>+#define EXYNOS850_HSI_PIN_DRV_LV2	2	/* 2x   */</div><div class='add'>+#define EXYNOS850_HSI_PIN_DRV_LV2_5	3	/* 2.5x */</div><div class='add'>+#define EXYNOS850_HSI_PIN_DRV_LV3	4	/* 3x   */</div><div class='add'>+#define EXYNOS850_HSI_PIN_DRV_LV4	5	/* 4x   */</div><div class='add'>+</div><div class='add'>+#define EXYNOS_PIN_FUNC_INPUT		0</div><div class='add'>+#define EXYNOS_PIN_FUNC_OUTPUT		1</div><div class='add'>+#define EXYNOS_PIN_FUNC_2		2</div><div class='add'>+#define EXYNOS_PIN_FUNC_3		3</div><div class='add'>+#define EXYNOS_PIN_FUNC_4		4</div><div class='add'>+#define EXYNOS_PIN_FUNC_5		5</div><div class='add'>+#define EXYNOS_PIN_FUNC_6		6</div><div class='add'>+#define EXYNOS_PIN_FUNC_EINT		0xf</div><div class='add'>+#define EXYNOS_PIN_FUNC_F		EXYNOS_PIN_FUNC_EINT</div><div class='add'>+</div><div class='add'>+#endif /* __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__ */</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/exynos2200-g0s.dts b/arch/arm64/boot/dts/exynos/exynos2200-g0s.dts<br/>new file mode 100644<br/>index 000000000000..0e348c5cf7df<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynos2200-g0s.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/exynos2200-g0s.dts</a></div><div class='hunk'>@@ -0,0 +1,169 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause</div><div class='add'>+/*</div><div class='add'>+ * Samsung Galaxy S22+ (g0s/SM-S906B) device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2025, Ivaylo Ivanov &lt;ivo.ivanov.ivanov1@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "exynos2200.dtsi"</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Samsung Galaxy S22+ (SM-S906B)";</div><div class='add'>+	compatible = "samsung,g0s", "samsung,exynos2200";</div><div class='add'>+	chassis-type = "handset";</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		framebuffer: framebuffer {</div><div class='add'>+			compatible = "simple-framebuffer";</div><div class='add'>+			memory-region = &lt;&amp;cont_splash_mem&gt;;</div><div class='add'>+			width = &lt;1080&gt;;</div><div class='add'>+			height = &lt;2340&gt;;</div><div class='add'>+			stride = &lt;(1080 * 4)&gt;;</div><div class='add'>+			format = "a8r8g8b8";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * RTC clock (XrtcXTI); external, must be 32.768 kHz.</div><div class='add'>+	 *</div><div class='add'>+	 * TODO: Remove this once RTC clock is implemented properly as part of</div><div class='add'>+	 *       PMIC driver.</div><div class='add'>+	 */</div><div class='add'>+	rtcclk: clock-rtcclk {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		clock-output-names = "rtcclk";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;32768&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;key_volup&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		volup-key {</div><div class='add'>+			label = "Volume Up";</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpa3 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@80000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x80000000 0x0 0x80000000&gt;,</div><div class='add'>+		      &lt;0x8 0x80000000 0x1 0x7e000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* TODO: Remove this once PMIC is implemented  */</div><div class='add'>+	reg_dummy: regulator-0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "dummy_reg";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		cont_splash_mem: framebuffer@f6200000 {</div><div class='add'>+			reg = &lt;0x0 0xf6200000 0x0 (1080 * 2340 * 4)&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		debug_kinfo_reserved: debug-kinfo-reserved@fcfff000 {</div><div class='add'>+			reg = &lt;0x0 0xfcfff000 0x0 0x1000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		log_itmon: log-itmon@fffe0000 {</div><div class='add'>+			reg = &lt;0x0 0xfffe0000 0x0 0x20000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cmu_hsi0 {</div><div class='add'>+	clocks = &lt;&amp;xtcxo&gt;,</div><div class='add'>+		 &lt;&amp;rtcclk&gt;,</div><div class='add'>+		 &lt;&amp;cmu_top CLK_DOUT_CMU_HSI0_NOC&gt;,</div><div class='add'>+		 &lt;&amp;cmu_top CLK_DOUT_CMU_HSI0_DPGTC&gt;,</div><div class='add'>+		 &lt;&amp;cmu_top CLK_DOUT_CMU_HSI0_DPOSC&gt;,</div><div class='add'>+		 &lt;&amp;cmu_top CLK_DOUT_CMU_HSI0_USB32DRD&gt;;</div><div class='add'>+	clock-names = "oscclk", "rtcclk", "noc", "dpgtc", "dposc", "usb";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * cpu2 and cpu3 fail to come up consistently, which leads to a hang later</div><div class='add'>+ * in the boot process. Disable them until the issue is figured out.</div><div class='add'>+ */</div><div class='add'>+&amp;cpu2 {</div><div class='add'>+	status = "fail";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu3 {</div><div class='add'>+	status = "fail";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ext_26m {</div><div class='add'>+	clock-frequency = &lt;26000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ext_200m {</div><div class='add'>+	clock-frequency = &lt;200000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mct_peris {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_alive {</div><div class='add'>+	key_volup: key-volup-pins {</div><div class='add'>+		samsung,pins = "gpa3-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_F&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV4&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ppi_cluster0 {</div><div class='add'>+	affinity = &lt;&amp;cpu0 &amp;cpu1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb {</div><div class='add'>+	/* TODO: Replace these once PMIC is implemented  */</div><div class='add'>+	vdd10-supply = &lt;&amp;reg_dummy&gt;;</div><div class='add'>+	vdd33-supply = &lt;&amp;reg_dummy&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb32drd {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3 {</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	role-switch-default-mode = "peripheral";</div><div class='add'>+	maximum-speed = "high-speed";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_hsphy {</div><div class='add'>+	/* TODO: Replace these once PMIC is implemented  */</div><div class='add'>+	vdda12-supply = &lt;&amp;reg_dummy&gt;;</div><div class='add'>+	vdd-supply = &lt;&amp;reg_dummy&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xtcxo {</div><div class='add'>+	clock-frequency = &lt;76800000&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/exynos2200-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos2200-pinctrl.dtsi<br/>new file mode 100644<br/>index 000000000000..5877da7baf5c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynos2200-pinctrl.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/exynos2200-pinctrl.dtsi</a></div><div class='hunk'>@@ -0,0 +1,1765 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause</div><div class='add'>+/*</div><div class='add'>+ * Samsung's Exynos 2200 SoC pin-mux and pin-config device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2025, Ivaylo Ivanov &lt;ivo.ivanov.ivanov1@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include "exynos-pinctrl.h"</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_alive {</div><div class='add'>+	gpa0: gpa0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpa1: gpa1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpa2: gpa2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpa3: gpa3-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpa4: gpa4-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpq0: gpq0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpq1: gpq1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpq2: gpq2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bt_hostwake: bt-hostwake-pins {</div><div class='add'>+		samsung,pins = "gpa0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_F&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart1_bus: uart1-bus-pins {</div><div class='add'>+		samsung,pins = "gpq0-3", "gpq0-2", "gpq0-1", "gpq0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wlan_host_wake: wlan-host-wake-pins {</div><div class='add'>+		samsung,pins = "gpa0-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_F&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_cmgp {</div><div class='add'>+	gpm0: gpm0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm1: gpm1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm2: gpm2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm3: gpm3-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm4: gpm4-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm5: gpm5-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm6: gpm6-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm7: gpm7-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm8: gpm8-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm9: gpm9-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm10: gpm10-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm11: gpm11-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm12: gpm12-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm13: gpm13-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm14: gpm14-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm15: gpm15-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm16: gpm16-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm17: gpm17-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm20: gpm20-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm21: gpm21-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm22: gpm22-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm23: gpm23-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm24: gpm24-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c24_bus: hsi2c24-bus-pins {</div><div class='add'>+		samsung,pins = "gpm0-0", "gpm0-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c25_bus: hsi2c25-bus-pins {</div><div class='add'>+		samsung,pins = "gpm1-0", "gpm1-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c26_bus: hsi2c26-bus-pins {</div><div class='add'>+		samsung,pins = "gpm2-0", "gpm2-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c27_bus: hsi2c27-bus-pins {</div><div class='add'>+		samsung,pins = "gpm3-0", "gpm3-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c28_bus: hsi2c28-bus-pins {</div><div class='add'>+		samsung,pins = "gpm4-0", "gpm4-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c29_bus: hsi2c29-bus-pins {</div><div class='add'>+		samsung,pins = "gpm5-0", "gpm5-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c30_bus: hsi2c30-bus-pins {</div><div class='add'>+		samsung,pins = "gpm6-0", "gpm6-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c31_bus: hsi2c31-bus-pins {</div><div class='add'>+		samsung,pins = "gpm7-0", "gpm7-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c32_bus: hsi2c32-bus-pins {</div><div class='add'>+		samsung,pins = "gpm8-0", "gpm8-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c33_bus: hsi2c33-bus-pins {</div><div class='add'>+		samsung,pins = "gpm9-0", "gpm9-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c34_bus: hsi2c34-bus-pins {</div><div class='add'>+		samsung,pins = "gpm10-0", "gpm10-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c35_bus: hsi2c35-bus-pins {</div><div class='add'>+		samsung,pins = "gpm11-0", "gpm11-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c36_bus: hsi2c36-bus-pins {</div><div class='add'>+		samsung,pins = "gpm12-0", "gpm12-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c37_bus: hsi2c37-bus-pins {</div><div class='add'>+		samsung,pins = "gpm13-0", "gpm13-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c38_bus: hsi2c38-bus-pins {</div><div class='add'>+		samsung,pins = "gpm23-0", "gpm24-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi12_bus: spi12-bus-pins {</div><div class='add'>+		samsung,pins = "gpm0-0", "gpm0-1", "gpm1-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi12_cs: spi12-cs-pins {</div><div class='add'>+		samsung,pins = "gpm1-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi12_cs_func: spi12-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpm1-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi13_bus: spi13-bus-pins {</div><div class='add'>+		samsung,pins = "gpm2-0", "gpm2-1", "gpm3-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi13_cs: spi13-cs-pins {</div><div class='add'>+		samsung,pins = "gpm3-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi13_cs_func: spi13-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpm3-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi14_bus: spi14-bus-pins {</div><div class='add'>+		samsung,pins = "gpm4-0", "gpm4-1", "gpm5-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi14_cs: spi14-cs-pins {</div><div class='add'>+		samsung,pins = "gpm5-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi14_cs_func: spi14-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpm5-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi15_bus: spi15-bus-pins {</div><div class='add'>+		samsung,pins = "gpm6-0", "gpm6-1", "gpm7-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi15_cs: spi15-cs-pins {</div><div class='add'>+		samsung,pins = "gpm7-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi15_cs_func: spi15-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpm7-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi16_bus: spi16-bus-pins {</div><div class='add'>+		samsung,pins = "gpm8-0", "gpm8-1", "gpm9-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi16_cs: spi16-cs-pins {</div><div class='add'>+		samsung,pins = "gpm9-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi16_cs_func: spi16-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpm9-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi17_bus: spi17-bus-pins {</div><div class='add'>+		samsung,pins = "gpm10-0", "gpm10-1", "gpm11-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi17_cs: spi17-cs-pins {</div><div class='add'>+		samsung,pins = "gpm11-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi17_cs_func: spi17-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpm11-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi18_bus: spi18-bus-pins {</div><div class='add'>+		samsung,pins = "gpm12-0", "gpm12-1", "gpm13-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi18_cs: spi18-cs-pins {</div><div class='add'>+		samsung,pins = "gpm13-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi18_cs_func: spi18-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpm13-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart14_bus_single: uart14-bus-single-pins {</div><div class='add'>+		samsung,pins = "gpm0-0", "gpm0-1", "gpm2-0", "gpm2-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart14_bus_dual: uart14-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpm0-0", "gpm0-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart15_bus_single: uart15-bus-single-pins {</div><div class='add'>+		samsung,pins = "gpm3-0", "gpm3-1", "gpm4-0", "gpm4-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart15_bus_dual: uart15-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpm3-0", "gpm3-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart16_bus_single: uart16-bus-single-pins {</div><div class='add'>+		samsung,pins = "gpm5-0", "gpm5-1", "gpm6-0", "gpm6-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart16_bus_dual: uart16-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpm5-0", "gpm5-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart17_bus_single: uart17-bus-single-pins {</div><div class='add'>+		samsung,pins = "gpm7-0", "gpm7-1", "gpm8-0", "gpm8-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart17_bus_dual: uart17-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpm7-0", "gpm7-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart18_bus_single: uart18-bus-single-pins {</div><div class='add'>+		samsung,pins = "gpm8-0", "gpm8-1", "gpm9-0", "gpm9-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart18_bus_dual: uart18-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpm8-0", "gpm8-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart19_bus_single: uart19-bus-single-pins {</div><div class='add'>+		samsung,pins = "gpm10-0", "gpm10-1", "gpm11-0", "gpm11-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart19_bus_dual: uart19-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpm12-0", "gpm12-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart20_bus_single: uart20-bus-single-pins {</div><div class='add'>+		samsung,pins = "gpm13-0", "gpm13-1", "gpm14-0", "gpm14-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart20_bus_dual: uart20-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpm13-0", "gpm13-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_hsi1 {</div><div class='add'>+	gpf0: gpf0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_clkreq: pcie0-clkreq-pins {</div><div class='add'>+		samsung,pins = "gpf0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV4&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_perst: pcie0-perst-pins {</div><div class='add'>+		samsung,pins = "gpf0-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV4&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie1_clkreq: pcie1-clkreq-pins {</div><div class='add'>+		samsung,pins = "gpf0-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV4&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie1_perst: pcie1-perst-pins {</div><div class='add'>+		samsung,pins = "gpf0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV4&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_hsi1ufs {</div><div class='add'>+	gpf2: gpf2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ufs_rst_n: ufs-rst-n-pins {</div><div class='add'>+		samsung,pins = "gpf2-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ufs_refclk_out: ufs-refclk-out-pins {</div><div class='add'>+		samsung,pins = "gpf2-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV3&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_peric0 {</div><div class='add'>+	gpb0: gpb0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpb1: gpb1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpb2: gpb2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpb3: gpb3-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpc0: gpc0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpc1: gpc1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpc2: gpc2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpg1: gpg1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpg2: gpg2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp4: gpp4-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_i2s0_bus: aud-i2s0-bus-pins {</div><div class='add'>+		samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_i2s1_bus: aud-i2s1-bus-pins {</div><div class='add'>+		samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_i2s2_bus: aud-i2s2-bus-pins {</div><div class='add'>+		samsung,pins = "gpb2-0", "gpb2-1", "gpb2-2", "gpb2-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_i2s3_bus: aud-i2s3-bus-pins {</div><div class='add'>+		samsung,pins = "gpb3-0", "gpb3-1", "gpb3-2", "gpb3-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_i2s3_pci: aud-i2s3-pci-pins {</div><div class='add'>+		samsung,pins = "gpb3-0", "gpb3-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_dsd_bus: aud-dsd-bus-pins {</div><div class='add'>+		samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	decon_0_te: decon-0-te-pins {</div><div class='add'>+		samsung,pins = "gpg2-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_F&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c8_bus: hsi2c8-bus-pins {</div><div class='add'>+		samsung,pins = "gpp4-0", "gpp4-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c9_bus: hsi2c9-bus-pins {</div><div class='add'>+		samsung,pins = "gpp4-2", "gpp4-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i3c0_bus: i3c0-bus-pins {</div><div class='add'>+		samsung,pins = "gpc0-0", "gpc0-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i3c1_bus: i3c1-bus-pins {</div><div class='add'>+		samsung,pins = "gpc1-0", "gpc1-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i3c2_bus: i3c2-bus-pins {</div><div class='add'>+		samsung,pins = "gpc2-0", "gpc2-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi4_bus: spi4-bus-pins {</div><div class='add'>+		samsung,pins = "gpp4-2", "gpp4-1", "gpp4-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi4_cs: spi4-cs-pins {</div><div class='add'>+		samsung,pins = "gpp4-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi4_cs_func: spi4-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp4-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart6_bus_single: uart6-bus-single-pins {</div><div class='add'>+		samsung,pins = "gpp4-0", "gpp4-1", "gpp4-2", "gpp4-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart6_bus_dual: uart6-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp4-0", "gpp4-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_peric1 {</div><div class='add'>+	gpp7: gpp7-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp8: gpp8-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp9: gpp9-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp10: gpp10-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c14_bus: hsi2c14-bus-pins {</div><div class='add'>+		samsung,pins = "gpp7-0", "gpp7-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c15_bus: hsi2c15-bus-pins {</div><div class='add'>+		samsung,pins = "gpp7-2", "gpp7-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c16_bus: hsi2c16-bus-pins {</div><div class='add'>+		samsung,pins = "gpp8-0", "gpp8-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c17_bus: hsi2c17-bus-pins {</div><div class='add'>+		samsung,pins = "gpp8-2", "gpp8-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c18_bus: hsi2c18-bus-pins {</div><div class='add'>+		samsung,pins = "gpp9-0", "gpp9-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c19_bus: hsi2c19-bus-pins {</div><div class='add'>+		samsung,pins = "gpp9-2", "gpp9-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c20_bus: hsi2c20-bus-pins {</div><div class='add'>+		samsung,pins = "gpp10-0", "gpp10-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c21_bus: hsi2c21-bus-pins {</div><div class='add'>+		samsung,pins = "gpp10-2", "gpp10-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi7_bus: spi7-bus-pins {</div><div class='add'>+		samsung,pins = "gpp7-2", "gpp7-1", "gpp7-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi7_cs: spi7-cs-pins {</div><div class='add'>+		samsung,pins = "gpp7-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi7_cs_func: spi7-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp7-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi8_bus: spi8-bus-pins {</div><div class='add'>+		samsung,pins = "gpp8-2", "gpp8-1", "gpp8-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi8_cs: spi8-cs-pins {</div><div class='add'>+		samsung,pins = "gpp8-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi8_cs_func: spi8-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp8-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi9_bus: spi9-bus-pins {</div><div class='add'>+		samsung,pins = "gpp9-2", "gpp9-1", "gpp9-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi9_cs: spi9-cs-pins {</div><div class='add'>+		samsung,pins = "gpp9-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi9_cs_func: spi9-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp9-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi10_bus: spi10-bus-pins {</div><div class='add'>+		samsung,pins = "gpp10-2", "gpp10-1", "gpp10-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi10_cs: spi10-cs-pins {</div><div class='add'>+		samsung,pins = "gpp10-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi10_cs_func: spi10-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp10-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart9_bus_single: uart9-bus-single-pins {</div><div class='add'>+		samsung,pins = "gpp7-3", "gpp7-2", "gpp7-1", "gpp7-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart9_bus_dual: uart9-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp7-0", "gpp7-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart10_bus_single: uart10-bus-single-pins {</div><div class='add'>+		samsung,pins = "gpp8-3", "gpp8-2", "gpp8-1", "gpp8-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart10_bus_dual: uart10-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp8-0", "gpp8-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart11_bus_single: uart11-bus-single-pins {</div><div class='add'>+		samsung,pins = "gpp9-3", "gpp9-2", "gpp9-1", "gpp9-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart11_bus_dual: uart11-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp9-0", "gpp9-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart12_bus_single: uart12-bus-single-pins {</div><div class='add'>+		samsung,pins = "gpp10-3", "gpp10-2", "gpp10-1", "gpp10-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart12_bus_dual: uart12-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp10-0", "gpp10-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_peric2 {</div><div class='add'>+	gpc3: gpc3-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpc4: gpc4-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpc5: gpc5-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpc6: gpc6-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpc7: gpc7-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpc8: gpc8-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpc9: gpc9-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpg0: gpg0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp0: gpp0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp1: gpp1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp2: gpp2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp3: gpp3-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp5: gpp5-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp6: gpp6-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp11: gpp11-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c0_bus: hsi2c0-bus-pins {</div><div class='add'>+		samsung,pins = "gpp0-0", "gpp0-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c1_bus: hsi2c1-bus-pins {</div><div class='add'>+		samsung,pins = "gpp0-2", "gpp0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c2_bus: hsi2c2-bus-pins {</div><div class='add'>+		samsung,pins = "gpp1-0", "gpp1-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c3_bus: hsi2c3-bus-pins {</div><div class='add'>+		samsung,pins = "gpp1-2", "gpp1-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c4_bus: hsi2c4-bus-pins {</div><div class='add'>+		samsung,pins = "gpp2-0", "gpp2-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c5_bus: hsi2c5-bus-pins {</div><div class='add'>+		samsung,pins = "gpp2-2", "gpp2-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c6_bus: hsi2c6-bus-pins {</div><div class='add'>+		samsung,pins = "gpp3-0", "gpp3-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c7_bus: hsi2c7-bus-pins {</div><div class='add'>+		samsung,pins = "gpp3-2", "gpp3-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c10_bus: hsi2c10-bus-pins {</div><div class='add'>+		samsung,pins = "gpp5-0", "gpp5-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c11_bus: hsi2c11-bus-pins {</div><div class='add'>+		samsung,pins = "gpp5-2", "gpp5-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c12_bus: hsi2c12-bus-pins {</div><div class='add'>+		samsung,pins = "gpp6-0", "gpp6-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c13_bus: hsi2c13-bus-pins {</div><div class='add'>+		samsung,pins = "gpp6-2", "gpp6-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c22_bus: hsi2c22-bus-pins {</div><div class='add'>+		samsung,pins = "gpp11-0", "gpp11-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i3c3_bus: i3c3-bus-pins {</div><div class='add'>+		samsung,pins = "gpc3-0", "gpc3-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i3c4_bus: i3c4-bus-pins {</div><div class='add'>+		samsung,pins = "gpc4-0", "gpc4-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i3c5_bus: i3c5-bus-pins {</div><div class='add'>+		samsung,pins = "gpc5-0", "gpc5-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i3c6_bus: i3c6-bus-pins {</div><div class='add'>+		samsung,pins = "gpc6-0", "gpc6-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i3c7_bus: i3c7-bus-pins {</div><div class='add'>+		samsung,pins = "gpc7-0", "gpc7-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i3c8_bus: i3c8-bus-pins {</div><div class='add'>+		samsung,pins = "gpc8-0", "gpc8-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i3c9_bus: i3c9-bus-pins {</div><div class='add'>+		samsung,pins = "gpc9-0", "gpc9-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i3c10_bus: i3c10-bus-pins {</div><div class='add'>+		samsung,pins = "gpp2-2", "gpp2-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_4&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i3c11_bus: i3c11-bus-pins {</div><div class='add'>+		samsung,pins = "gpp3-2", "gpp3-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_4&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c23_bus: hsi2c23-bus-pins {</div><div class='add'>+		samsung,pins = "gpp11-2", "gpp11-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi0_bus: spi0-bus-pins {</div><div class='add'>+		samsung,pins = "gpp0-2", "gpp0-1", "gpp0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi0_cs: spi0-cs-pins {</div><div class='add'>+		samsung,pins = "gpp0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi0_cs_func: spi0-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi1_bus: spi1-bus-pins {</div><div class='add'>+		samsung,pins = "gpp1-2", "gpp1-1", "gpp1-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi1_cs: spi1-cs-pins {</div><div class='add'>+		samsung,pins = "gpp1-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi1_cs_func: spi1-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp1-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi2_bus: spi2-bus-pins {</div><div class='add'>+		samsung,pins = "gpp2-2", "gpp2-1", "gpp2-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi2_cs: spi2-cs-pins {</div><div class='add'>+		samsung,pins = "gpp2-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi2_cs_func: spi2-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp2-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi3_bus: spi3-bus-pins {</div><div class='add'>+		samsung,pins = "gpp3-2", "gpp3-1", "gpp3-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi3_cs: spi3-cs-pins {</div><div class='add'>+		samsung,pins = "gpp3-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi3_cs_func: spi3-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp3-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi5_bus: spi5-bus-pins {</div><div class='add'>+		samsung,pins = "gpp5-2", "gpp5-1", "gpp5-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi5_cs: spi5-cs-pins {</div><div class='add'>+		samsung,pins = "gpp5-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi5_cs_func: spi5-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp5-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi6_bus: spi6-bus-pins {</div><div class='add'>+		samsung,pins = "gpp6-2", "gpp6-1", "gpp6-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi6_cs: spi6-cs-pins {</div><div class='add'>+		samsung,pins = "gpp6-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi6_cs_func: spi6-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp6-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi11_bus: spi11-bus-pins {</div><div class='add'>+		samsung,pins = "gpp11-2", "gpp11-1", "gpp11-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi11_cs: spi11-cs-pins {</div><div class='add'>+		samsung,pins = "gpp11-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi11_cs_func: spi11-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp11-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart0_bus_single: uart0-bus-single-pins {</div><div class='add'>+		samsung,pins = "gpg0-2", "gpg0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart2_bus_single: uart2-bus-single-pins {</div><div class='add'>+		samsung,pins = "gpp0-0", "gpp0-1", "gpp0-2", "gpp0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart2_bus_dual: uart2-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp0-0", "gpp0-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart3_bus_single: uart3-bus-single-pins {</div><div class='add'>+		samsung,pins = "gpp1-0", "gpp1-1", "gpp1-2", "gpp1-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart3_bus_dual: uart3-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp1-0", "gpp1-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart4_bus_single: uart4-bus-single-pins {</div><div class='add'>+		samsung,pins = "gpp2-0", "gpp2-1", "gpp2-2", "gpp2-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart4_bus_dual: uart4-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp2-0", "gpp2-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart5_bus_single: uart5-bus-single-pins {</div><div class='add'>+		samsung,pins = "gpp3-0", "gpp3-1", "gpp3-2", "gpp3-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart5_bus_dual: uart5-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp3-0", "gpp3-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart7_bus_single: uart7-bus-single-pins {</div><div class='add'>+		samsung,pins = "gpp5-0", "gpp5-1", "gpp5-2", "gpp5-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart7_bus_dual: uart7-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp5-0", "gpp5-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart8_bus_single: uart8-bus-single-pins {</div><div class='add'>+		samsung,pins = "gpp6-3", "gpp6-2", "gpp6-1", "gpp6-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart8_bus_dual: uart8-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp6-0", "gpp6-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart13_bus_single: uart13-bus-single-pins {</div><div class='add'>+		samsung,pins = "gpp11-3", "gpp11-2", "gpp11-1", "gpp11-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart13_bus_dual: uart13-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp11-0", "gpp11-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_ufs {</div><div class='add'>+	gpf1: gpf1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_vts {</div><div class='add'>+	gpv0: gpv0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	amic_pdm0_bus: amic-pdm0-bus-pins {</div><div class='add'>+		samsung,pins = "gpv0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_INPUT&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	amic_pdm1_bus: amic-pdm1-bus-pins {</div><div class='add'>+		samsung,pins = "gpv0-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_INPUT&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	amic_pdm2_bus: amic-pdm2-bus-pins {</div><div class='add'>+		samsung,pins = "gpv0-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_INPUT&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dmic_bus_clk0: dmic-bus-clk0-pins {</div><div class='add'>+		samsung,pins = "gpv0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_INPUT&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dmic_bus_clk1: dmic-bus-clk1-pins {</div><div class='add'>+		samsung,pins = "gpv0-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_INPUT&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dmic_bus_clk2: dmic-bus-clk2-pins {</div><div class='add'>+		samsung,pins = "gpv0-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_INPUT&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dmic_pdm0_bus: dmic-pdm0-bus-pins {</div><div class='add'>+		samsung,pins = "gpv0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_INPUT&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dmic_pdm1_bus: dmic-pdm1-bus-pins {</div><div class='add'>+		samsung,pins = "gpv0-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_INPUT&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dmic_pdm2_bus: dmic-pdm2-bus-pins {</div><div class='add'>+		samsung,pins = "gpv0-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_INPUT&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/exynos2200.dtsi b/arch/arm64/boot/dts/exynos/exynos2200.dtsi<br/>new file mode 100644<br/>index 000000000000..6487ccb58ae7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynos2200.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/exynos2200.dtsi</a></div><div class='hunk'>@@ -0,0 +1,1923 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause</div><div class='add'>+/*</div><div class='add'>+ * Samsung's Exynos 2200 SoC device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2025, Ivaylo Ivanov &lt;ivo.ivanov.ivanov1@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/samsung,exynos2200-cmu.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/soc/samsung,exynos-usi.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "samsung,exynos2200";</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		pinctrl0 = &amp;pinctrl_alive;</div><div class='add'>+		pinctrl1 = &amp;pinctrl_cmgp;</div><div class='add'>+		pinctrl2 = &amp;pinctrl_hsi1;</div><div class='add'>+		pinctrl3 = &amp;pinctrl_ufs;</div><div class='add'>+		pinctrl4 = &amp;pinctrl_hsi1ufs;</div><div class='add'>+		pinctrl5 = &amp;pinctrl_peric0;</div><div class='add'>+		pinctrl6 = &amp;pinctrl_peric1;</div><div class='add'>+		pinctrl7 = &amp;pinctrl_peric2;</div><div class='add'>+		pinctrl8 = &amp;pinctrl_vts;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	xtcxo: clock-1 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-output-names = "oscclk";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ext_26m: clock-2 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-output-names = "ext-26m";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ext_200m: clock-3 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-output-names = "ext-200m";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu-map {</div><div class='add'>+			cluster0 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu2&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu3&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cluster1 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu4&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu5&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu6&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cluster2 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu7&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a510";</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;260&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;189&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			cpu-idle-states = &lt;&amp;little_cpu_sleep&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@100 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a510";</div><div class='add'>+			reg = &lt;0x100&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;260&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;189&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			cpu-idle-states = &lt;&amp;little_cpu_sleep&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@200 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a510";</div><div class='add'>+			reg = &lt;0x200&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;260&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;189&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			cpu-idle-states = &lt;&amp;little_cpu_sleep&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@300 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a510";</div><div class='add'>+			reg = &lt;0x300&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;260&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;189&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			cpu-idle-states = &lt;&amp;little_cpu_sleep&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu4: cpu@400 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a710";</div><div class='add'>+			reg = &lt;0x400&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;380&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;560&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			cpu-idle-states = &lt;&amp;big_cpu_sleep&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu5: cpu@500 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a710";</div><div class='add'>+			reg = &lt;0x500&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;380&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;560&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			cpu-idle-states = &lt;&amp;big_cpu_sleep&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu6: cpu@600 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a710";</div><div class='add'>+			reg = &lt;0x600&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;380&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;560&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			cpu-idle-states = &lt;&amp;big_cpu_sleep&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu7: cpu@700 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-x2";</div><div class='add'>+			reg = &lt;0x700&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;488&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;765&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			cpu-idle-states = &lt;&amp;prime_cpu_sleep&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		idle-states {</div><div class='add'>+			entry-method = "psci";</div><div class='add'>+</div><div class='add'>+			little_cpu_sleep: cpu-sleep-0 {</div><div class='add'>+				compatible = "arm,idle-state";</div><div class='add'>+				idle-state-name = "c2";</div><div class='add'>+				entry-latency-us = &lt;70&gt;;</div><div class='add'>+				exit-latency-us = &lt;170&gt;;</div><div class='add'>+				min-residency-us = &lt;2000&gt;;</div><div class='add'>+				arm,psci-suspend-param = &lt;0x10000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			big_cpu_sleep: cpu-sleep-1 {</div><div class='add'>+				compatible = "arm,idle-state";</div><div class='add'>+				idle-state-name = "c2";</div><div class='add'>+				entry-latency-us = &lt;235&gt;;</div><div class='add'>+				exit-latency-us = &lt;220&gt;;</div><div class='add'>+				min-residency-us = &lt;3500&gt;;</div><div class='add'>+				arm,psci-suspend-param = &lt;0x10000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			prime_cpu_sleep: cpu-sleep-2 {</div><div class='add'>+				compatible = "arm,idle-state";</div><div class='add'>+				idle-state-name = "c2";</div><div class='add'>+				entry-latency-us = &lt;150&gt;;</div><div class='add'>+				exit-latency-us = &lt;190&gt;;</div><div class='add'>+				min-residency-us = &lt;2500&gt;;</div><div class='add'>+				arm,psci-suspend-param = &lt;0x10000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu-a510 {</div><div class='add'>+		compatible = "arm,cortex-a510-pmu";</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &amp;ppi_cluster0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu-a710 {</div><div class='add'>+		compatible = "arm,cortex-a710-pmu";</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &amp;ppi_cluster1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu-x2 {</div><div class='add'>+		compatible = "arm,cortex-x2-pmu";</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &amp;ppi_cluster2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-1.0";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc@0 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		ranges = &lt;0x0 0x0 0x0 0x20000000&gt;;</div><div class='add'>+</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		chipid@10000000 {</div><div class='add'>+			compatible = "samsung,exynos2200-chipid",</div><div class='add'>+				     "samsung,exynos850-chipid";</div><div class='add'>+			reg = &lt;0x10000000 0x24&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_peris: clock-controller@10020000 {</div><div class='add'>+			compatible = "samsung,exynos2200-cmu-peris";</div><div class='add'>+			reg = &lt;0x10020000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;cmu_top CLK_DOUT_TCXO_DIV3&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_PERIS_NOC&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_PERIS_GIC&gt;;</div><div class='add'>+			clock-names = "tcxo_div3",</div><div class='add'>+				      "noc",</div><div class='add'>+				      "gic";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mct_peris: timer@10040000 {</div><div class='add'>+			compatible = "samsung,exynos2200-mct-peris",</div><div class='add'>+				     "samsung,exynos4210-mct";</div><div class='add'>+			reg = &lt;0x10040000 0x800&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_top CLK_DOUT_TCXO_DIV3&gt;, &lt;&amp;cmu_peris CLK_MOUT_PERIS_GIC&gt;;</div><div class='add'>+			clock-names = "fin_pll", "mct";</div><div class='add'>+			interrupts = &lt;GIC_SPI 943 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+				     &lt;GIC_SPI 944 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+				     &lt;GIC_SPI 945 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+				     &lt;GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+				     &lt;GIC_SPI 947 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+				     &lt;GIC_SPI 948 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+				     &lt;GIC_SPI 949 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+				     &lt;GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+				     &lt;GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+				     &lt;GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+				     &lt;GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+				     &lt;GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@10200000 {</div><div class='add'>+			compatible = "arm,gic-v3";</div><div class='add'>+			reg = &lt;0x10200000 0x10000&gt;,     /* GICD */</div><div class='add'>+			      &lt;0x10240000 0x200000&gt;;    /* GICR * 8 */</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;0&gt;;</div><div class='add'>+			#interrupt-cells = &lt;4&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+</div><div class='add'>+			ppi-partitions {</div><div class='add'>+				ppi_cluster0: interrupt-partition-0 {</div><div class='add'>+					affinity = &lt;&amp;cpu0 &amp;cpu1 &amp;cpu2 &amp;cpu3&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				ppi_cluster1: interrupt-partition-1 {</div><div class='add'>+					affinity = &lt;&amp;cpu4 &amp;cpu5 &amp;cpu6&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				ppi_cluster2: interrupt-partition-2 {</div><div class='add'>+					affinity = &lt;&amp;cpu7&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_peric0: clock-controller@10400000 {</div><div class='add'>+			compatible = "samsung,exynos2200-cmu-peric0";</div><div class='add'>+			reg = &lt;0x10400000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;xtcxo&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_PERIC0_NOC&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_PERIC0_IP0&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_PERIC0_IP1&gt;;</div><div class='add'>+			clock-names = "oscclk", "noc", "ip0", "ip1";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		syscon_peric0: syscon@10420000 {</div><div class='add'>+			compatible = "samsung,exynos2200-peric0-sysreg", "syscon";</div><div class='add'>+			reg = &lt;0x10420000 0x10000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_peric0: pinctrl@10430000 {</div><div class='add'>+			compatible = "samsung,exynos2200-pinctrl";</div><div class='add'>+			reg = &lt;0x10430000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi4: usi@105000c0 {</div><div class='add'>+			compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x105000c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric0 CLK_MOUT_PERIC0_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric0 CLK_DOUT_PERIC0_USI04&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric0 0x1024&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_8: i2c@10500000 {</div><div class='add'>+				compatible = "samsung,exynos2200-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x10500000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_DOUT_PERIC0_USI04&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_MOUT_PERIC0_NOC_USER&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c8_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_6: serial@10500000 {</div><div class='add'>+				compatible = "samsung,exynos2200-uart", "google,gs101-uart";</div><div class='add'>+				reg = &lt;0x10500000 0xc0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_MOUT_PERIC0_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_DOUT_PERIC0_USI04&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart6_bus_single&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi4_i2c: usi@105100c0 {</div><div class='add'>+			compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x105100c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric0 CLK_MOUT_PERIC0_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric0 CLK_DOUT_PERIC0_I2C&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,mode = &lt;USI_MODE_I2C&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric0 0x1024&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_9: i2c@10510000 {</div><div class='add'>+				compatible = "samsung,exynos2200-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x10510000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_DOUT_PERIC0_I2C&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_MOUT_PERIC0_NOC_USER&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c9_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_peric1: clock-controller@10700000 {</div><div class='add'>+			compatible = "samsung,exynos2200-cmu-peric1";</div><div class='add'>+			reg = &lt;0x10700000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;xtcxo&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_PERIC1_NOC&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_PERIC1_IP0&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_PERIC1_IP1&gt;;</div><div class='add'>+			clock-names = "oscclk", "noc", "ip0", "ip1";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		syscon_peric1: syscon@10720000 {</div><div class='add'>+			compatible = "samsung,exynos2200-peric1-sysreg", "syscon";</div><div class='add'>+			reg = &lt;0x10720000 0x10000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_peric1: pinctrl@10730000 {</div><div class='add'>+			compatible = "samsung,exynos2200-pinctrl";</div><div class='add'>+			reg = &lt;0x10730000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi7: usi@109000c0 {</div><div class='add'>+			compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x109000c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_MOUT_PERIC1_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI07&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric1 0x2030&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_14: i2c@10900000 {</div><div class='add'>+				compatible = "samsung,exynos2200-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x10900000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI07&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_MOUT_PERIC1_NOC_USER&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c14_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_9: serial@10900000 {</div><div class='add'>+				compatible = "samsung,exynos2200-uart", "google,gs101-uart";</div><div class='add'>+				reg = &lt;0x10900000 0xc0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_MOUT_PERIC1_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI07&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart9_bus_single&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi7_i2c: usi@109100c0 {</div><div class='add'>+			compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x109100c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_MOUT_PERIC0_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI07_SPI_I2C&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,mode = &lt;USI_MODE_I2C&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric1 0x2034&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_15: i2c@10910000 {</div><div class='add'>+				compatible = "samsung,exynos2200-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x10910000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI07_SPI_I2C&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_MOUT_PERIC0_NOC_USER&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c15_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi8: usi@109200c0 {</div><div class='add'>+			compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x109200c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_MOUT_PERIC1_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI08&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric1 0x2038&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_16: i2c@10920000 {</div><div class='add'>+				compatible = "samsung,exynos2200-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x10920000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI08&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_MOUT_PERIC1_NOC_USER&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c16_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_10: serial@10920000 {</div><div class='add'>+				compatible = "samsung,exynos2200-uart", "google,gs101-uart";</div><div class='add'>+				reg = &lt;0x10920000 0xc0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_MOUT_PERIC1_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI08&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart10_bus_single&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi8_i2c: usi@109300c0 {</div><div class='add'>+			compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x109300c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_MOUT_PERIC0_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI08_SPI_I2C&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,mode = &lt;USI_MODE_I2C&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric1 0x203c&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_17: i2c@10930000 {</div><div class='add'>+				compatible = "samsung,exynos2200-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x10930000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI08_SPI_I2C&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_MOUT_PERIC0_NOC_USER&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c17_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi9: usi@109400c0 {</div><div class='add'>+			compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x109400c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_MOUT_PERIC1_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI09&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric1 0x2040&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_18: i2c@10940000 {</div><div class='add'>+				compatible = "samsung,exynos2200-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x10940000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI09&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_MOUT_PERIC1_NOC_USER&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c18_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_11: serial@10940000 {</div><div class='add'>+				compatible = "samsung,exynos2200-uart", "google,gs101-uart";</div><div class='add'>+				reg = &lt;0x10940000 0xc0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_MOUT_PERIC1_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI09&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart11_bus_single&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi9_i2c: usi@109500c0 {</div><div class='add'>+			compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x109500c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_MOUT_PERIC0_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_I2C&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,mode = &lt;USI_MODE_I2C&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric1 0x2044&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_19: i2c@10950000 {</div><div class='add'>+				compatible = "samsung,exynos2200-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x10950000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_I2C&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_MOUT_PERIC0_NOC_USER&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c19_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi10: usi@109600c0 {</div><div class='add'>+			compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x109600c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_MOUT_PERIC1_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI10&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric1 0x2048&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_20: i2c@10960000 {</div><div class='add'>+				compatible = "samsung,exynos2200-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x10960000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI10&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_MOUT_PERIC1_NOC_USER&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c20_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_12: serial@10960000 {</div><div class='add'>+				compatible = "samsung,exynos2200-uart", "google,gs101-uart";</div><div class='add'>+				reg = &lt;0x10960000 0xc0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_MOUT_PERIC1_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI10&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart12_bus_single&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi10_i2c: usi@109700c0 {</div><div class='add'>+			compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x109700c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_MOUT_PERIC0_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_I2C&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,mode = &lt;USI_MODE_I2C&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric1 0x204c&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_21: i2c@10970000 {</div><div class='add'>+				compatible = "samsung,exynos2200-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x10970000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_I2C&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_MOUT_PERIC0_NOC_USER&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c21_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_hsi0: clock-controller@10a00000 {</div><div class='add'>+			compatible = "samsung,exynos2200-cmu-hsi0";</div><div class='add'>+			reg = &lt;0x10a00000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb32drd: phy@10aa0000 {</div><div class='add'>+			compatible = "samsung,exynos2200-usb32drd-phy";</div><div class='add'>+			reg = &lt;0x10aa0000 0x10000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;cmu_hsi0 CLK_MOUT_HSI0_NOC&gt;;</div><div class='add'>+			clock-names = "phy";</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;1&gt;;</div><div class='add'>+			phys = &lt;&amp;usb_hsphy&gt;;</div><div class='add'>+			phy-names = "hs";</div><div class='add'>+</div><div class='add'>+			samsung,pmu-syscon = &lt;&amp;pmu_system_controller&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_hsphy: phy@10ab0000 {</div><div class='add'>+			compatible = "samsung,exynos2200-eusb2-phy";</div><div class='add'>+			reg = &lt;0x10ab0000 0x10000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;cmu_hsi0 CLK_MOUT_HSI0_USB32DRD&gt;,</div><div class='add'>+				 &lt;&amp;cmu_hsi0 CLK_MOUT_HSI0_NOC&gt;,</div><div class='add'>+				 &lt;&amp;cmu_hsi0 CLK_DOUT_DIV_CLK_HSI0_EUSB&gt;;</div><div class='add'>+			clock-names = "ref", "bus", "ctrl";</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb: usb@10b00000 {</div><div class='add'>+			compatible = "samsung,exynos2200-dwusb3";</div><div class='add'>+			ranges = &lt;0x0 0x10b00000 0x10000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;cmu_hsi0 CLK_MOUT_HSI0_NOC&gt;;</div><div class='add'>+			clock-names = "link_aclk";</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			usb_dwc3: usb@0 {</div><div class='add'>+				compatible = "snps,dwc3";</div><div class='add'>+				reg = &lt;0x0 0x10000&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;cmu_hsi0 CLK_MOUT_HSI0_USB32DRD&gt;;</div><div class='add'>+				clock-names = "ref";</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 485 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+</div><div class='add'>+				phys = &lt;&amp;usb32drd 0&gt;;</div><div class='add'>+				phy-names = "usb2-phy";</div><div class='add'>+</div><div class='add'>+				snps,dis-u2-freeclk-exists-quirk;</div><div class='add'>+				snps,gfladj-refclk-lpm-sel-quirk;</div><div class='add'>+				snps,has-lpm-erratum;</div><div class='add'>+				snps,quirk-frame-length-adjustment = &lt;0x20&gt;;</div><div class='add'>+				snps,usb3_lpm_capable;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_ufs: clock-controller@11000000 {</div><div class='add'>+			compatible = "samsung,exynos2200-cmu-ufs";</div><div class='add'>+			reg = &lt;0x11000000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;xtcxo&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_UFS_NOC&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_MOUT_CMU_UFS_MMC_CARD&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_UFS_UFS_EMBD&gt;;</div><div class='add'>+			clock-names = "oscclk", "noc", "mmc", "ufs";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		syscon_ufs: syscon@11020000 {</div><div class='add'>+			compatible = "samsung,exynos2200-ufs-sysreg", "syscon";</div><div class='add'>+			reg = &lt;0x11020000 0x10000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_ufs: pinctrl@11040000 {</div><div class='add'>+			compatible = "samsung,exynos2200-pinctrl";</div><div class='add'>+			reg = &lt;0x11040000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_hsi1ufs: pinctrl@11060000 {</div><div class='add'>+			compatible = "samsung,exynos2200-pinctrl";</div><div class='add'>+			reg = &lt;0x11060000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_hsi1: pinctrl@11240000 {</div><div class='add'>+			compatible = "samsung,exynos2200-pinctrl";</div><div class='add'>+			reg = &lt;0x11240000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_peric2: clock-controller@11c00000 {</div><div class='add'>+			compatible = "samsung,exynos2200-cmu-peric2";</div><div class='add'>+			reg = &lt;0x11c00000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;xtcxo&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_PERIC2_NOC&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_PERIC2_IP0&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_PERIC2_IP1&gt;;</div><div class='add'>+			clock-names = "oscclk", "noc", "ip0", "ip1";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		syscon_peric2: syscon@11c20000 {</div><div class='add'>+			compatible = "samsung,exynos2200-peric2-sysreg", "syscon";</div><div class='add'>+			reg = &lt;0x11c20000 0x10000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_peric2: pinctrl@11c30000 {</div><div class='add'>+			compatible = "samsung,exynos2200-pinctrl";</div><div class='add'>+			reg = &lt;0x11c30000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi0: usi@11d000c0 {</div><div class='add'>+			compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x11d000c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric2 CLK_MOUT_PERIC2_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric2 CLK_DOUT_PERIC2_USI00&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric2 0x2000&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_0: i2c@11d00000 {</div><div class='add'>+				compatible = "samsung,exynos2200-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x11d00000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric2 CLK_DOUT_PERIC2_USI00&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric2 CLK_MOUT_PERIC2_NOC_USER&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c0_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_2: serial@11d00000 {</div><div class='add'>+				compatible = "samsung,exynos2200-uart", "google,gs101-uart";</div><div class='add'>+				reg = &lt;0x11d00000 0xc0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric2 CLK_MOUT_PERIC2_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric2 CLK_DOUT_PERIC2_USI00&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart2_bus_single&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi0_i2c: usi@11d100c0 {</div><div class='add'>+			compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x11d100c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric2 CLK_MOUT_PERIC2_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric2 CLK_DOUT_PERIC2_USI00_SPI_I2C&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,mode = &lt;USI_MODE_I2C&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric2 0x2004&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_1: i2c@11d10000 {</div><div class='add'>+				compatible = "samsung,exynos2200-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x11d10000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric2 CLK_DOUT_PERIC2_USI00_SPI_I2C&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric2 CLK_MOUT_PERIC2_NOC_USER&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c1_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi1: usi@11d200c0 {</div><div class='add'>+			compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x11d200c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric2 CLK_MOUT_PERIC2_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric2 CLK_DOUT_PERIC2_USI01&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric2 0x2008&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_2: i2c@11d20000 {</div><div class='add'>+				compatible = "samsung,exynos2200-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x11d20000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric2 CLK_DOUT_PERIC2_USI01&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric2 CLK_MOUT_PERIC2_NOC_USER&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c2_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_3: serial@11d20000 {</div><div class='add'>+				compatible = "samsung,exynos2200-uart", "google,gs101-uart";</div><div class='add'>+				reg = &lt;0x11d20000 0xc0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric2 CLK_MOUT_PERIC2_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric2 CLK_DOUT_PERIC2_USI01&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart3_bus_single&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi1_i2c: usi@11d300c0 {</div><div class='add'>+			compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x11d300c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric2 CLK_MOUT_PERIC2_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric2 CLK_DOUT_PERIC2_USI01_SPI_I2C&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,mode = &lt;USI_MODE_I2C&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric2 0x200c&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_3: i2c@11d30000 {</div><div class='add'>+				compatible = "samsung,exynos2200-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x11d30000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric2 CLK_DOUT_PERIC2_USI01_SPI_I2C&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric2 CLK_MOUT_PERIC2_NOC_USER&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 705 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c3_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi2: usi@11d400c0 {</div><div class='add'>+			compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x11d400c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric2 CLK_MOUT_PERIC2_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric2 CLK_DOUT_PERIC2_USI02&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric2 0x2010&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_4: i2c@11d40000 {</div><div class='add'>+				compatible = "samsung,exynos2200-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x11d40000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric2 CLK_DOUT_PERIC2_USI02&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric2 CLK_MOUT_PERIC2_NOC_USER&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c4_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_4: serial@11d40000 {</div><div class='add'>+				compatible = "samsung,exynos2200-uart", "google,gs101-uart";</div><div class='add'>+				reg = &lt;0x11d40000 0xc0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric2 CLK_MOUT_PERIC2_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric2 CLK_DOUT_PERIC2_USI02&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart4_bus_single&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;256&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi2_i2c: usi@11d500c0 {</div><div class='add'>+			compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x11d500c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric2 CLK_MOUT_PERIC2_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric2 CLK_DOUT_PERIC2_I2C&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,mode = &lt;USI_MODE_I2C&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric2 0x2014&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_5: i2c@11d50000 {</div><div class='add'>+				compatible = "samsung,exynos2200-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x11d50000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric2 CLK_DOUT_PERIC2_I2C&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric2 CLK_MOUT_PERIC2_NOC_USER&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c5_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi3: usi@11d600c0 {</div><div class='add'>+			compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x11d600c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric2 CLK_MOUT_PERIC2_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric2 CLK_DOUT_PERIC2_USI03&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric2 0x2018&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_6: i2c@11d60000 {</div><div class='add'>+				compatible = "samsung,exynos2200-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x11d60000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric2 CLK_DOUT_PERIC2_USI03&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric2 CLK_MOUT_PERIC2_NOC_USER&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c6_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_5: serial@11d60000 {</div><div class='add'>+				compatible = "samsung,exynos2200-uart", "google,gs101-uart";</div><div class='add'>+				reg = &lt;0x11d60000 0xc0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric2 CLK_MOUT_PERIC2_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric2 CLK_DOUT_PERIC2_USI03&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart5_bus_single&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;256&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi3_i2c: usi@11d700c0 {</div><div class='add'>+			compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x11d700c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric2 CLK_MOUT_PERIC2_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric2 CLK_DOUT_PERIC2_I2C&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,mode = &lt;USI_MODE_I2C&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric2 0x201c&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_7: i2c@11d70000 {</div><div class='add'>+				compatible = "samsung,exynos2200-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x11d70000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric2 CLK_DOUT_PERIC2_I2C&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric2 CLK_MOUT_PERIC2_NOC_USER&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c7_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi5_i2c: usi@11d800c0 {</div><div class='add'>+			compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x11d800c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric2 CLK_MOUT_PERIC2_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric2 CLK_DOUT_PERIC2_I2C&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,mode = &lt;USI_MODE_I2C&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric2 0x102c&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_11: i2c@11d80000 {</div><div class='add'>+				compatible = "samsung,exynos2200-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x11d80000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric2 CLK_DOUT_PERIC2_I2C&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric2 CLK_MOUT_PERIC2_NOC_USER&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c11_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi6_i2c: usi@11d900c0 {</div><div class='add'>+			compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x11d900c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric2 CLK_MOUT_PERIC2_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric2 CLK_DOUT_PERIC2_I2C&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,mode = &lt;USI_MODE_I2C&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric2 0x1004&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_13: i2c@11d90000 {</div><div class='add'>+				compatible = "samsung,exynos2200-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x11d90000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric2 CLK_DOUT_PERIC2_I2C&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric2 CLK_MOUT_PERIC2_NOC_USER&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c13_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi11: usi@11da00c0 {</div><div class='add'>+			compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x11da00c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric2 CLK_MOUT_PERIC2_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric2 CLK_DOUT_PERIC2_USI11&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric2 0x1058&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_22: i2c@11da0000 {</div><div class='add'>+				compatible = "samsung,exynos2200-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x11da0000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric2 CLK_DOUT_PERIC2_USI11&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric2 CLK_MOUT_PERIC2_NOC_USER&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c22_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_13: serial@11da0000 {</div><div class='add'>+				compatible = "samsung,exynos2200-uart", "google,gs101-uart";</div><div class='add'>+				reg = &lt;0x11da0000 0xc0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric2 CLK_MOUT_PERIC2_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric2 CLK_DOUT_PERIC2_USI11&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart13_bus_single&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi11_i2c: usi@11db00c0 {</div><div class='add'>+			compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x11db00c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric2 CLK_MOUT_PERIC2_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric2 CLK_DOUT_PERIC2_I2C&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,mode = &lt;USI_MODE_I2C&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric2 0x105c&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_23: i2c@11db0000 {</div><div class='add'>+				compatible = "samsung,exynos2200-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x11db0000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric2 CLK_DOUT_PERIC2_I2C&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric2 CLK_MOUT_PERIC2_NOC_USER&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c23_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi5: usi@11dd00c0 {</div><div class='add'>+			compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x11dd00c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric2 CLK_MOUT_PERIC2_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric2 CLK_DOUT_PERIC2_USI05&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric2 0x117c&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_10: i2c@11dd0000 {</div><div class='add'>+				compatible = "samsung,exynos2200-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x11dd0000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric2 CLK_DOUT_PERIC2_USI05&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric2 CLK_MOUT_PERIC2_NOC_USER&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 538 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c10_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_7: serial@11dd0000 {</div><div class='add'>+				compatible = "samsung,exynos2200-uart", "google,gs101-uart";</div><div class='add'>+				reg = &lt;0x11dd0000 0xc0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric2 CLK_MOUT_PERIC2_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric2 CLK_DOUT_PERIC2_USI05&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 538 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart7_bus_single&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;256&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi6: usi@11de00c0 {</div><div class='add'>+			compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x11de00c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric2 CLK_MOUT_PERIC2_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric2 CLK_DOUT_PERIC2_USI06&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric2 0x1180&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_12: i2c@11de0000 {</div><div class='add'>+				compatible = "samsung,exynos2200-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x11de0000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric2 CLK_DOUT_PERIC2_USI06&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric2 CLK_MOUT_PERIC2_NOC_USER&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c12_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_8: serial@11de0000 {</div><div class='add'>+				compatible = "samsung,exynos2200-uart", "google,gs101-uart";</div><div class='add'>+				reg = &lt;0x11de0000 0xc0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric2 CLK_MOUT_PERIC2_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric2 CLK_DOUT_PERIC2_USI06&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart8_bus_single&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_cmgp: clock-controller@14e00000 {</div><div class='add'>+			compatible = "samsung,exynos2200-cmu-cmgp";</div><div class='add'>+			reg = &lt;0x14e00000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;xtcxo&gt;,</div><div class='add'>+				 &lt;&amp;cmu_alive CLK_DOUT_ALIVE_CMGP_NOC&gt;,</div><div class='add'>+				 &lt;&amp;cmu_alive CLK_DOUT_ALIVE_CMGP_PERI&gt;;</div><div class='add'>+			clock-names = "oscclk", "noc", "peri";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		syscon_cmgp: syscon@14e20000 {</div><div class='add'>+			compatible = "samsung,exynos2200-cmgp-sysreg", "syscon";</div><div class='add'>+			reg = &lt;0x14e20000 0x10000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_cmgp: pinctrl@14e30000 {</div><div class='add'>+			compatible = "samsung,exynos2200-pinctrl";</div><div class='add'>+			reg = &lt;0x14e30000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			wakeup-interrupt-controller {</div><div class='add'>+				compatible = "samsung,exynos2200-wakeup-eint",</div><div class='add'>+					     "samsung,exynos850-wakeup-eint",</div><div class='add'>+					     "samsung,exynos7-wakeup-eint";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_cmgp0: usi@14f000c0 {</div><div class='add'>+			compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x14f000c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_cmgp CLK_DOUT_CMGP_USI0&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_cmgp 0x2000&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_24: i2c@14f00000 {</div><div class='add'>+				compatible = "samsung,exynos2200-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x14f00000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_cmgp CLK_DOUT_CMGP_USI0&gt;,</div><div class='add'>+					 &lt;&amp;cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c24_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_14: serial@14f00000 {</div><div class='add'>+				compatible = "samsung,exynos2200-uart", "google,gs101-uart";</div><div class='add'>+				reg = &lt;0x14f00000 0xc0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_cmgp CLK_DOUT_CMGP_USI0&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart14_bus_single&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_i2c_cmgp0: usi@14f100c0 {</div><div class='add'>+			compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x14f100c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_cmgp CLK_DOUT_CMGP_SPI_I2C0&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,mode = &lt;USI_MODE_I2C&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_cmgp 0x2070&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_25: i2c@14f10000 {</div><div class='add'>+				compatible = "samsung,exynos2200-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x14f10000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_cmgp CLK_DOUT_CMGP_SPI_I2C0&gt;,</div><div class='add'>+					 &lt;&amp;cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c25_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_cmgp1: usi@14f200c0 {</div><div class='add'>+			compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x14f200c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_cmgp CLK_DOUT_CMGP_USI1&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_cmgp 0x2010&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_26: i2c@14f20000 {</div><div class='add'>+				compatible = "samsung,exynos2200-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x14f20000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_cmgp CLK_DOUT_CMGP_USI1&gt;,</div><div class='add'>+					 &lt;&amp;cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c26_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_15: serial@14f20000 {</div><div class='add'>+				compatible = "samsung,exynos2200-uart", "google,gs101-uart";</div><div class='add'>+				reg = &lt;0x14f20000 0xc0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_cmgp CLK_DOUT_CMGP_USI1&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart15_bus_single&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_i2c_cmgp1: usi@14f300c0 {</div><div class='add'>+			compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x14f300c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_cmgp CLK_DOUT_CMGP_SPI_I2C1&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,mode = &lt;USI_MODE_I2C&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_cmgp 0x2074&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_27: i2c@14f30000 {</div><div class='add'>+				compatible = "samsung,exynos2200-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x14f30000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_cmgp CLK_DOUT_CMGP_SPI_I2C1&gt;,</div><div class='add'>+					 &lt;&amp;cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c27_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_cmgp2: usi@14f400c0 {</div><div class='add'>+			compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x14f400c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_cmgp CLK_DOUT_CMGP_USI2&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_cmgp 0x2020&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_28: i2c@14f40000 {</div><div class='add'>+				compatible = "samsung,exynos2200-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x14f40000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_cmgp CLK_DOUT_CMGP_USI2&gt;,</div><div class='add'>+					 &lt;&amp;cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c28_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_16: serial@14f40000 {</div><div class='add'>+				compatible = "samsung,exynos2200-uart", "google,gs101-uart";</div><div class='add'>+				reg = &lt;0x14f40000 0xc0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_cmgp CLK_DOUT_CMGP_USI2&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart16_bus_single&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_i2c_cmgp2: usi@14f500c0 {</div><div class='add'>+			compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x14f500c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_cmgp CLK_DOUT_CMGP_I2C&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,mode = &lt;USI_MODE_I2C&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_cmgp 0x2024&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_29: i2c@14f50000 {</div><div class='add'>+				compatible = "samsung,exynos2200-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x14f50000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_cmgp CLK_DOUT_CMGP_I2C&gt;,</div><div class='add'>+					 &lt;&amp;cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c29_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_cmgp3: usi@14f600c0 {</div><div class='add'>+			compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x14f600c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_cmgp CLK_DOUT_CMGP_USI3&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_cmgp 0x2030&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_30: i2c@14f60000 {</div><div class='add'>+				compatible = "samsung,exynos2200-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x14f60000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_cmgp CLK_DOUT_CMGP_USI3&gt;,</div><div class='add'>+					 &lt;&amp;cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c30_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_17: serial@14f60000 {</div><div class='add'>+				compatible = "samsung,exynos2200-uart", "google,gs101-uart";</div><div class='add'>+				reg = &lt;0x14f60000 0xc0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_cmgp CLK_DOUT_CMGP_USI3&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart17_bus_single&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_i2c_cmgp3: usi@14f700c0 {</div><div class='add'>+			compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x14f700c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_cmgp CLK_DOUT_CMGP_I2C&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,mode = &lt;USI_MODE_I2C&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_cmgp 0x2034&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_31: i2c@14f70000 {</div><div class='add'>+				compatible = "samsung,exynos2200-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x14f70000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_cmgp CLK_DOUT_CMGP_I2C&gt;,</div><div class='add'>+					 &lt;&amp;cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c31_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_cmgp4: usi@14f800c0 {</div><div class='add'>+			compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x14f800c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_cmgp CLK_DOUT_CMGP_USI4&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_cmgp 0x2040&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_32: i2c@14f80000 {</div><div class='add'>+				compatible = "samsung,exynos2200-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x14f80000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_cmgp CLK_DOUT_CMGP_USI4&gt;,</div><div class='add'>+					 &lt;&amp;cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c32_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_18: serial@14f80000 {</div><div class='add'>+				compatible = "samsung,exynos2200-uart", "google,gs101-uart";</div><div class='add'>+				reg = &lt;0x14f80000 0xc0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_cmgp CLK_DOUT_CMGP_USI4&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart18_bus_single&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_i2c_cmgp4: usi@14f900c0 {</div><div class='add'>+			compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x14f900c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_cmgp CLK_DOUT_CMGP_I2C&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,mode = &lt;USI_MODE_I2C&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_cmgp 0x2044&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_33: i2c@14f90000 {</div><div class='add'>+				compatible = "samsung,exynos2200-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x14f90000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_cmgp CLK_DOUT_CMGP_I2C&gt;,</div><div class='add'>+					 &lt;&amp;cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c33_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_cmgp5: usi@14fa00c0 {</div><div class='add'>+			compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x14fa00c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_cmgp CLK_DOUT_CMGP_USI5&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_cmgp 0x2050&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_34: i2c@14fa0000 {</div><div class='add'>+				compatible = "samsung,exynos2200-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x14fa0000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_cmgp CLK_DOUT_CMGP_USI5&gt;,</div><div class='add'>+					 &lt;&amp;cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c34_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_19: serial@14fa0000 {</div><div class='add'>+				compatible = "samsung,exynos2200-uart", "google,gs101-uart";</div><div class='add'>+				reg = &lt;0x14fa0000 0xc0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_cmgp CLK_DOUT_CMGP_USI5&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart19_bus_single&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_i2c_cmgp5: usi@14fb00c0 {</div><div class='add'>+			compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x14fb00c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_cmgp CLK_DOUT_CMGP_I2C&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,mode = &lt;USI_MODE_I2C&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_cmgp 0x2054&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_35: i2c@14fb0000 {</div><div class='add'>+				compatible = "samsung,exynos2200-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x14fb0000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_cmgp CLK_DOUT_CMGP_I2C&gt;,</div><div class='add'>+					 &lt;&amp;cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c35_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_cmgp6: usi@14fc00c0 {</div><div class='add'>+			compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x14fc00c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_cmgp CLK_DOUT_CMGP_USI6&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_cmgp 0x2060&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_36: i2c@14fc0000 {</div><div class='add'>+				compatible = "samsung,exynos2200-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x14fc0000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_cmgp CLK_DOUT_CMGP_USI6&gt;,</div><div class='add'>+					 &lt;&amp;cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c36_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_20: serial@14fc0000 {</div><div class='add'>+				compatible = "samsung,exynos2200-uart", "google,gs101-uart";</div><div class='add'>+				reg = &lt;0x14fc0000 0xc0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_cmgp CLK_DOUT_CMGP_USI6&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart20_bus_single&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_i2c_cmgp6: usi@14fd00c0 {</div><div class='add'>+			compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x14fd00c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_cmgp CLK_DOUT_CMGP_I2C&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,mode = &lt;USI_MODE_I2C&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_cmgp 0x2064&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_37: i2c@14fd0000 {</div><div class='add'>+				compatible = "samsung,exynos2200-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x14fd0000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_cmgp CLK_DOUT_CMGP_I2C&gt;,</div><div class='add'>+					 &lt;&amp;cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c37_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_i2c_cmgp7: usi@14fe00c0 {</div><div class='add'>+			compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x14fe00c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_cmgp CLK_DOUT_CMGP_I2C&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,mode = &lt;USI_MODE_I2C&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_cmgp 0x2080&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_38: i2c@14fe0000 {</div><div class='add'>+				compatible = "samsung,exynos2200-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x14fe0000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_cmgp CLK_DOUT_CMGP_I2C&gt;,</div><div class='add'>+					 &lt;&amp;cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c38_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_vts: clock-controller@15300000 {</div><div class='add'>+			compatible = "samsung,exynos2200-cmu-vts";</div><div class='add'>+			reg = &lt;0x15300000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;xtcxo&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_VTS_DMIC&gt;;</div><div class='add'>+			clock-names = "oscclk", "dmic";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_vts: pinctrl@15320000 {</div><div class='add'>+			compatible = "samsung,exynos2200-pinctrl";</div><div class='add'>+			reg = &lt;0x15320000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_alive: clock-controller@15800000 {</div><div class='add'>+			compatible = "samsung,exynos2200-cmu-alive";</div><div class='add'>+			reg = &lt;0x15800000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;xtcxo&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_ALIVE_NOC&gt;;</div><div class='add'>+			clock-names = "oscclk", "noc";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_alive: pinctrl@15850000 {</div><div class='add'>+			compatible = "samsung,exynos2200-pinctrl";</div><div class='add'>+			reg = &lt;0x15850000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			wakeup-interrupt-controller {</div><div class='add'>+				compatible = "samsung,exynos2200-wakeup-eint",</div><div class='add'>+					     "samsung,exynos850-wakeup-eint",</div><div class='add'>+					     "samsung,exynos7-wakeup-eint";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmu_system_controller: system-controller@15860000 {</div><div class='add'>+			compatible = "samsung,exynos2200-pmu",</div><div class='add'>+				     "samsung,exynos7-pmu", "syscon";</div><div class='add'>+			reg = &lt;0x15860000 0x10000&gt;;</div><div class='add'>+</div><div class='add'>+			reboot: syscon-reboot {</div><div class='add'>+				compatible = "syscon-reboot";</div><div class='add'>+				offset = &lt;0x3c00&gt;; /* SYSTEM_CONFIGURATION */</div><div class='add'>+				mask = &lt;0x2&gt;; /* SWRESET_SYSTEM */</div><div class='add'>+				value = &lt;0x2&gt;; /* reset value */</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_top: clock-controller@1a320000 {</div><div class='add'>+			compatible = "samsung,exynos2200-cmu-top";</div><div class='add'>+			reg = &lt;0x1a320000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;xtcxo&gt;;</div><div class='add'>+			clock-names = "oscclk";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0&gt;;</div><div class='add'>+		/*</div><div class='add'>+		 * Non-updatable, broken stock Samsung bootloader does not</div><div class='add'>+		 * configure CNTFRQ_EL0</div><div class='add'>+		 */</div><div class='add'>+		clock-frequency = &lt;25600000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include "exynos2200-pinctrl.dtsi"</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi<br/>index d77b88af9582..540b4d6c9067 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi</a></div><div class='hunk'>@@ -6,7 +6,7 @@</div><div class='ctx'>  * Chanwoo Choi &lt;cw00.choi@samsung.com&gt;</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-&amp;soc {</div><div class='add'>+/ {</div><div class='ctx'> 	bus_g2d_400: bus0 {</div><div class='ctx'> 		compatible = "samsung,exynos-bus";</div><div class='ctx'> 		clocks = &lt;&amp;cmu_top CLK_ACLK_G2D_400&gt;;</div><div class='hunk'>@@ -87,7 +87,7 @@</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	bus_g2d_400_opp_table: opp_table2 {</div><div class='add'>+	bus_g2d_400_opp_table: opp-table-2 {</div><div class='ctx'> 		compatible = "operating-points-v2";</div><div class='ctx'> 		opp-shared;</div><div class='ctx'> </div><div class='hunk'>@@ -117,7 +117,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	bus_g2d_266_opp_table: opp_table3 {</div><div class='add'>+	bus_g2d_266_opp_table: opp-table-3 {</div><div class='ctx'> 		compatible = "operating-points-v2";</div><div class='ctx'> </div><div class='ctx'> 		opp-267000000 {</div><div class='hunk'>@@ -137,7 +137,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	bus_gscl_opp_table: opp_table4 {</div><div class='add'>+	bus_gscl_opp_table: opp-table-4 {</div><div class='ctx'> 		compatible = "operating-points-v2";</div><div class='ctx'> </div><div class='ctx'> 		opp-333000000 {</div><div class='hunk'>@@ -151,7 +151,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	bus_hevc_opp_table: opp_table5 {</div><div class='add'>+	bus_hevc_opp_table: opp-table-5 {</div><div class='ctx'> 		compatible = "operating-points-v2";</div><div class='ctx'> 		opp-shared;</div><div class='ctx'> </div><div class='hunk'>@@ -175,7 +175,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	bus_noc2_opp_table: opp_table6 {</div><div class='add'>+	bus_noc2_opp_table: opp-table-6 {</div><div class='ctx'> 		compatible = "operating-points-v2";</div><div class='ctx'> </div><div class='ctx'> 		opp-400000000 {</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi<br/>index 9df7c65593a1..681553577ebc 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi</a></div><div class='hunk'>@@ -9,18 +9,27 @@</div><div class='ctx'>  * tree nodes are listed in this file.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-#include &lt;dt-bindings/pinctrl/samsung.h&gt;</div><div class='add'>+#include "exynos-pinctrl.h"</div><div class='ctx'> </div><div class='del'>-#define PIN(_func, _pin, _pull, _drv)					\</div><div class='del'>-	_pin {								\</div><div class='add'>+#define PIN(_pin, _func, _pull, _drv)					\</div><div class='add'>+	pin- ## _pin {							\</div><div class='ctx'> 		samsung,pins = #_pin;					\</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_ ##_func&gt;;	\</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_ ##_pull&gt;;		\</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_ ##_drv&gt;;		\</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+#define PIN_IN(_pin, _pull, _drv)					\</div><div class='add'>+	PIN(_pin, INPUT, _pull, _drv)</div><div class='add'>+</div><div class='add'>+#define PIN_OT(_pin, _pull, _drv)					\</div><div class='add'>+	PIN(_pin, OUTPUT, _pull, _drv)</div><div class='add'>+</div><div class='add'>+#define PIN_F2(_pin, _pull, _drv)					\</div><div class='add'>+	PIN(_pin, 2, _pull, _drv)</div><div class='add'>+</div><div class='ctx'> &amp;pinctrl_alive {</div><div class='del'>-	gpa0: gpa0 {</div><div class='add'>+	gpa0: gpa0-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -37,7 +46,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpa1: gpa1 {</div><div class='add'>+	gpa1: gpa1-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -54,7 +63,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpa2: gpa2 {</div><div class='add'>+	gpa2: gpa2-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -62,7 +71,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpa3: gpa3 {</div><div class='add'>+	gpa3: gpa3-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -70,7 +79,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpf1: gpf1 {</div><div class='add'>+	gpf1: gpf1-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -78,7 +87,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpf2: gpf2 {</div><div class='add'>+	gpf2: gpf2-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -86,7 +95,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpf3: gpf3 {</div><div class='add'>+	gpf3: gpf3-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -94,7 +103,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpf4: gpf4 {</div><div class='add'>+	gpf4: gpf4-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -102,7 +111,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpf5: gpf5 {</div><div class='add'>+	gpf5: gpf5-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -112,7 +121,7 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;pinctrl_aud {</div><div class='del'>-	gpz0: gpz0 {</div><div class='add'>+	gpz0: gpz0-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -120,7 +129,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpz1: gpz1 {</div><div class='add'>+	gpz1: gpz1-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -128,7 +137,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	i2s0_bus: i2s0-bus {</div><div class='add'>+	i2s0_bus: i2s0-bus-pins {</div><div class='ctx'> 		samsung,pins = "gpz0-0", "gpz0-1", "gpz0-2", "gpz0-3",</div><div class='ctx'> 				"gpz0-4", "gpz0-5", "gpz0-6";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='hunk'>@@ -136,14 +145,14 @@</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pcm0_bus: pcm0-bus {</div><div class='add'>+	pcm0_bus: pcm0-bus-pins {</div><div class='ctx'> 		samsung,pins = "gpz1-0", "gpz1-1", "gpz1-2", "gpz1-3";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	uart_aud_bus: uart-aud-bus {</div><div class='add'>+	uart_aud_bus: uart-aud-bus-pins {</div><div class='ctx'> 		samsung,pins = "gpz1-3", "gpz1-2", "gpz1-1", "gpz1-0";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='hunk'>@@ -152,7 +161,7 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;pinctrl_cpif {</div><div class='del'>-	gpv6: gpv6 {</div><div class='add'>+	gpv6: gpv6-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -162,7 +171,7 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;pinctrl_ese {</div><div class='del'>-	gpj2: gpj2 {</div><div class='add'>+	gpj2: gpj2-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -172,7 +181,7 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;pinctrl_finger {</div><div class='del'>-	gpd5: gpd5 {</div><div class='add'>+	gpd5: gpd5-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -180,14 +189,14 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	spi2_bus: spi2-bus {</div><div class='add'>+	spi2_bus: spi2-bus-pins {</div><div class='ctx'> 		samsung,pins = "gpd5-0", "gpd5-2", "gpd5-3";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	hs_i2c6_bus: hs-i2c6-bus {</div><div class='add'>+	hs_i2c6_bus: hs-i2c6-bus-pins {</div><div class='ctx'> 		samsung,pins = "gpd5-3", "gpd5-2";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_4&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='hunk'>@@ -196,7 +205,7 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;pinctrl_fsys {</div><div class='del'>-	gph1: gph1 {</div><div class='add'>+	gph1: gph1-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -204,7 +213,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpr4: gpr4 {</div><div class='add'>+	gpr4: gpr4-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -212,7 +221,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpr0: gpr0 {</div><div class='add'>+	gpr0: gpr0-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -220,7 +229,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpr1: gpr1 {</div><div class='add'>+	gpr1: gpr1-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -228,7 +237,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpr2: gpr2 {</div><div class='add'>+	gpr2: gpr2-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -236,7 +245,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpr3: gpr3 {</div><div class='add'>+	gpr3: gpr3-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -244,139 +253,139 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sd0_clk: sd0-clk {</div><div class='add'>+	sd0_clk: sd0-clk-pins {</div><div class='ctx'> 		samsung,pins = "gpr0-0";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR4&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sd0_cmd: sd0-cmd {</div><div class='add'>+	sd0_cmd: sd0-cmd-pins {</div><div class='ctx'> 		samsung,pins = "gpr0-1";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR4&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sd0_rdqs: sd0-rdqs {</div><div class='add'>+	sd0_rdqs: sd0-rdqs-pins {</div><div class='ctx'> 		samsung,pins = "gpr0-2";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR4&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sd0_qrdy: sd0-qrdy {</div><div class='add'>+	sd0_qrdy: sd0-qrdy-pins {</div><div class='ctx'> 		samsung,pins = "gpr0-3";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR4&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sd0_bus1: sd0-bus-width1 {</div><div class='add'>+	sd0_bus1: sd0-bus-width1-pins {</div><div class='ctx'> 		samsung,pins = "gpr1-0";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR4&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sd0_bus4: sd0-bus-width4 {</div><div class='add'>+	sd0_bus4: sd0-bus-width4-pins {</div><div class='ctx'> 		samsung,pins = "gpr1-1", "gpr1-2", "gpr1-3";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR4&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sd0_bus8: sd0-bus-width8 {</div><div class='add'>+	sd0_bus8: sd0-bus-width8-pins {</div><div class='ctx'> 		samsung,pins = "gpr1-4", "gpr1-5", "gpr1-6", "gpr1-7";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR4&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sd1_clk: sd1-clk {</div><div class='add'>+	sd1_clk: sd1-clk-pins {</div><div class='ctx'> 		samsung,pins = "gpr2-0";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR4&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sd1_cmd: sd1-cmd {</div><div class='add'>+	sd1_cmd: sd1-cmd-pins {</div><div class='ctx'> 		samsung,pins = "gpr2-1";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR4&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sd1_bus1: sd1-bus-width1 {</div><div class='add'>+	sd1_bus1: sd1-bus-width1-pins {</div><div class='ctx'> 		samsung,pins = "gpr3-0";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR4&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sd1_bus4: sd1-bus-width4 {</div><div class='add'>+	sd1_bus4: sd1-bus-width4-pins {</div><div class='ctx'> 		samsung,pins = "gpr3-1", "gpr3-2", "gpr3-3";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR4&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sd1_bus8: sd1-bus-width8 {</div><div class='add'>+	sd1_bus8: sd1-bus-width8-pins {</div><div class='ctx'> 		samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR4&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pcie_bus: pcie_bus {</div><div class='del'>-		samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7";</div><div class='add'>+	pcie_bus: pcie-bus-pins {</div><div class='add'>+		samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sd2_clk: sd2-clk {</div><div class='add'>+	sd2_clk: sd2-clk-pins {</div><div class='ctx'> 		samsung,pins = "gpr4-0";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR4&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sd2_cmd: sd2-cmd {</div><div class='add'>+	sd2_cmd: sd2-cmd-pins {</div><div class='ctx'> 		samsung,pins = "gpr4-1";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR4&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sd2_cd: sd2-cd {</div><div class='add'>+	sd2_cd: sd2-cd-pins {</div><div class='ctx'> 		samsung,pins = "gpr4-2";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR4&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sd2_bus1: sd2-bus-width1 {</div><div class='add'>+	sd2_bus1: sd2-bus-width1-pins {</div><div class='ctx'> 		samsung,pins = "gpr4-3";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR4&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sd2_bus4: sd2-bus-width4 {</div><div class='add'>+	sd2_bus4: sd2-bus-width4-pins {</div><div class='ctx'> 		samsung,pins = "gpr4-4", "gpr4-5", "gpr4-6";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR4&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sd2_clk_output: sd2-clk-output {</div><div class='add'>+	sd2_clk_output: sd2-clk-output-pins {</div><div class='ctx'> 		samsung,pins = "gpr4-0";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR3&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sd2_cmd_output: sd2-cmd-output {</div><div class='add'>+	sd2_cmd_output: sd2-cmd-output-pins {</div><div class='ctx'> 		samsung,pins = "gpr4-1";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='hunk'>@@ -385,7 +394,7 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;pinctrl_imem {</div><div class='del'>-	gpf0: gpf0 {</div><div class='add'>+	gpf0: gpf0-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -395,7 +404,7 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;pinctrl_nfc {</div><div class='del'>-	gpj0: gpj0 {</div><div class='add'>+	gpj0: gpj0-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -403,7 +412,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	hs_i2c4_bus: hs-i2c4-bus {</div><div class='add'>+	hs_i2c4_bus: hs-i2c4-bus-pins {</div><div class='ctx'> 		samsung,pins = "gpj0-1", "gpj0-0";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_4&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='hunk'>@@ -412,7 +421,7 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;pinctrl_peric {</div><div class='del'>-	gpv7: gpv7 {</div><div class='add'>+	gpv7: gpv7-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -420,7 +429,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpb0: gpb0 {</div><div class='add'>+	gpb0: gpb0-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -428,7 +437,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpc0: gpc0 {</div><div class='add'>+	gpc0: gpc0-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -436,7 +445,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpc1: gpc1 {</div><div class='add'>+	gpc1: gpc1-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -444,7 +453,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpc2: gpc2 {</div><div class='add'>+	gpc2: gpc2-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -452,7 +461,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpc3: gpc3 {</div><div class='add'>+	gpc3: gpc3-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -460,7 +469,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpg0: gpg0 {</div><div class='add'>+	gpg0: gpg0-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -468,7 +477,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpd0: gpd0 {</div><div class='add'>+	gpd0: gpd0-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -476,7 +485,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpd1: gpd1 {</div><div class='add'>+	gpd1: gpd1-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -484,7 +493,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpd2: gpd2 {</div><div class='add'>+	gpd2: gpd2-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -492,7 +501,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpd4: gpd4 {</div><div class='add'>+	gpd4: gpd4-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -500,7 +509,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpd8: gpd8 {</div><div class='add'>+	gpd8: gpd8-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -508,7 +517,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpd6: gpd6 {</div><div class='add'>+	gpd6: gpd6-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -516,7 +525,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpd7: gpd7 {</div><div class='add'>+	gpd7: gpd7-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -524,7 +533,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpg1: gpg1 {</div><div class='add'>+	gpg1: gpg1-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -532,7 +541,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpg2: gpg2 {</div><div class='add'>+	gpg2: gpg2-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -540,7 +549,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpg3: gpg3 {</div><div class='add'>+	gpg3: gpg3-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -548,21 +557,21 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	hs_i2c8_bus: hs-i2c8-bus {</div><div class='add'>+	hs_i2c8_bus: hs-i2c8-bus-pins {</div><div class='ctx'> 		samsung,pins = "gpb0-1", "gpb0-0";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_4&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	hs_i2c9_bus: hs-i2c9-bus {</div><div class='add'>+	hs_i2c9_bus: hs-i2c9-bus-pins {</div><div class='ctx'> 		samsung,pins = "gpb0-3", "gpb0-2";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_4&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	i2s1_bus: i2s1-bus {</div><div class='add'>+	i2s1_bus: i2s1-bus-pins {</div><div class='ctx'> 		samsung,pins = "gpd4-0", "gpd4-1", "gpd4-2",</div><div class='ctx'> 				"gpd4-3", "gpd4-4";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='hunk'>@@ -570,7 +579,7 @@</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pcm1_bus: pcm1-bus {</div><div class='add'>+	pcm1_bus: pcm1-bus-pins {</div><div class='ctx'> 		samsung,pins = "gpd4-0", "gpd4-1", "gpd4-2",</div><div class='ctx'> 				"gpd4-3", "gpd4-4";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='hunk'>@@ -578,193 +587,193 @@</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	spdif_bus: spdif-bus {</div><div class='add'>+	spdif_bus: spdif-bus-pins {</div><div class='ctx'> 		samsung,pins = "gpd4-3", "gpd4-4";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_4&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	fimc_is_spi_pin0: fimc-is-spi-pin0 {</div><div class='add'>+	fimc_is_spi_pin0: fimc-is-spi-pin0-pins {</div><div class='ctx'> 		samsung,pins = "gpc3-3", "gpc3-2", "gpc3-1", "gpc3-0";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	fimc_is_spi_pin1: fimc-is-spi-pin1 {</div><div class='add'>+	fimc_is_spi_pin1: fimc-is-spi-pin1-pins {</div><div class='ctx'> 		samsung,pins = "gpc3-7", "gpc3-6", "gpc3-5", "gpc3-4";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	uart0_bus: uart0-bus {</div><div class='add'>+	uart0_bus: uart0-bus-pins {</div><div class='ctx'> 		samsung,pins = "gpd0-3", "gpd0-2", "gpd0-1", "gpd0-0";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	hs_i2c2_bus: hs-i2c2-bus {</div><div class='add'>+	hs_i2c2_bus: hs-i2c2-bus-pins {</div><div class='ctx'> 		samsung,pins = "gpd0-3", "gpd0-2";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	uart2_bus: uart2-bus {</div><div class='add'>+	uart2_bus: uart2-bus-pins {</div><div class='ctx'> 		samsung,pins = "gpd1-5", "gpd1-4";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	uart1_bus: uart1-bus {</div><div class='add'>+	uart1_bus: uart1-bus-pins {</div><div class='ctx'> 		samsung,pins = "gpd1-3", "gpd1-2", "gpd1-1", "gpd1-0";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	hs_i2c3_bus: hs-i2c3-bus {</div><div class='add'>+	hs_i2c3_bus: hs-i2c3-bus-pins {</div><div class='ctx'> 		samsung,pins = "gpd1-3", "gpd1-2";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	hs_i2c0_bus: hs-i2c0-bus {</div><div class='add'>+	hs_i2c0_bus: hs-i2c0-bus-pins {</div><div class='ctx'> 		samsung,pins = "gpd2-1", "gpd2-0";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	hs_i2c1_bus: hs-i2c1-bus {</div><div class='add'>+	hs_i2c1_bus: hs-i2c1-bus-pins {</div><div class='ctx'> 		samsung,pins = "gpd2-3", "gpd2-2";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pwm0_out: pwm0-out {</div><div class='add'>+	pwm0_out: pwm0-out-pins {</div><div class='ctx'> 		samsung,pins = "gpd2-4";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pwm1_out: pwm1-out {</div><div class='add'>+	pwm1_out: pwm1-out-pins {</div><div class='ctx'> 		samsung,pins = "gpd2-5";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pwm2_out: pwm2-out {</div><div class='add'>+	pwm2_out: pwm2-out-pins {</div><div class='ctx'> 		samsung,pins = "gpd2-6";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pwm3_out: pwm3-out {</div><div class='add'>+	pwm3_out: pwm3-out-pins {</div><div class='ctx'> 		samsung,pins = "gpd2-7";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	spi1_bus: spi1-bus {</div><div class='add'>+	spi1_bus: spi1-bus-pins {</div><div class='ctx'> 		samsung,pins = "gpd6-2", "gpd6-4", "gpd6-5";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	hs_i2c7_bus: hs-i2c7-bus {</div><div class='add'>+	hs_i2c7_bus: hs-i2c7-bus-pins {</div><div class='ctx'> 		samsung,pins = "gpd2-7", "gpd2-6";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_4&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	spi0_bus: spi0-bus {</div><div class='add'>+	spi0_bus: spi0-bus-pins {</div><div class='ctx'> 		samsung,pins = "gpd8-0", "gpd6-0", "gpd6-1";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	hs_i2c10_bus: hs-i2c10-bus {</div><div class='add'>+	hs_i2c10_bus: hs-i2c10-bus-pins {</div><div class='ctx'> 		samsung,pins = "gpg3-1", "gpg3-0";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_4&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	hs_i2c11_bus: hs-i2c11-bus {</div><div class='add'>+	hs_i2c11_bus: hs-i2c11-bus-pins {</div><div class='ctx'> 		samsung,pins = "gpg3-3", "gpg3-2";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_4&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	spi3_bus: spi3-bus {</div><div class='add'>+	spi3_bus: spi3-bus-pins {</div><div class='ctx'> 		samsung,pins = "gpg3-4", "gpg3-6", "gpg3-7";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	spi4_bus: spi4-bus {</div><div class='add'>+	spi4_bus: spi4-bus-pins {</div><div class='ctx'> 		samsung,pins = "gpv7-1", "gpv7-3", "gpv7-4";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	fimc_is_uart: fimc-is-uart {</div><div class='add'>+	fimc_is_uart: fimc-is-uart-pins {</div><div class='ctx'> 		samsung,pins = "gpc1-1", "gpc0-7";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	fimc_is_ch0_i2c: fimc-is-ch0_i2c {</div><div class='add'>+	fimc_is_ch0_i2c: fimc-is-ch0-i2c-pins {</div><div class='ctx'> 		samsung,pins = "gpc2-1", "gpc2-0";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	fimc_is_ch0_mclk: fimc-is-ch0_mclk {</div><div class='add'>+	fimc_is_ch0_mclk: fimc-is-ch0-mclk-pins {</div><div class='ctx'> 		samsung,pins = "gpd7-0";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	fimc_is_ch1_i2c: fimc-is-ch1-i2c {</div><div class='add'>+	fimc_is_ch1_i2c: fimc-is-ch1-i2c-pins {</div><div class='ctx'> 		samsung,pins = "gpc2-3", "gpc2-2";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	fimc_is_ch1_mclk: fimc-is-ch1-mclk {</div><div class='add'>+	fimc_is_ch1_mclk: fimc-is-ch1-mclk-pins {</div><div class='ctx'> 		samsung,pins = "gpd7-1";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	fimc_is_ch2_i2c: fimc-is-ch2-i2c {</div><div class='add'>+	fimc_is_ch2_i2c: fimc-is-ch2-i2c-pins {</div><div class='ctx'> 		samsung,pins = "gpc2-5", "gpc2-4";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	fimc_is_ch2_mclk: fimc-is-ch2-mclk {</div><div class='add'>+	fimc_is_ch2_mclk: fimc-is-ch2-mclk-pins {</div><div class='ctx'> 		samsung,pins = "gpd7-2";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='hunk'>@@ -773,7 +782,7 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;pinctrl_touch {</div><div class='del'>-	gpj1: gpj1 {</div><div class='add'>+	gpj1: gpj1-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -781,7 +790,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	hs_i2c5_bus: hs-i2c5-bus {</div><div class='add'>+	hs_i2c5_bus: hs-i2c5-bus-pins {</div><div class='ctx'> 		samsung,pins = "gpj1-1", "gpj1-0";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_4&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi<br/>index 250fc01de78d..a1fb354dea9f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi</a></div><div class='hunk'>@@ -21,6 +21,8 @@</div><div class='ctx'> 		gsc0 = &amp;gsc_0;</div><div class='ctx'> 		gsc1 = &amp;gsc_1;</div><div class='ctx'> 		gsc2 = &amp;gsc_2;</div><div class='add'>+		mmc0 = &amp;mshc_0;</div><div class='add'>+		mmc2 = &amp;mshc_2;</div><div class='ctx'> 		pinctrl0 = &amp;pinctrl_alive;</div><div class='ctx'> 		pinctrl1 = &amp;pinctrl_aud;</div><div class='ctx'> 		pinctrl2 = &amp;pinctrl_cpif;</div><div class='hunk'>@@ -40,8 +42,6 @@</div><div class='ctx'> 		spi2 = &amp;spi_2;</div><div class='ctx'> 		spi3 = &amp;spi_3;</div><div class='ctx'> 		spi4 = &amp;spi_4;</div><div class='del'>-		mshc0 = &amp;mshc_0;</div><div class='del'>-		mshc2 = &amp;mshc_2;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	chosen {</div><div class='hunk'>@@ -85,26 +85,32 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	i2c_max98504: i2c-gpio-0 {</div><div class='add'>+	i2c_max98504: i2c-13 {</div><div class='ctx'> 		compatible = "i2c-gpio";</div><div class='del'>-		gpios = &lt;&amp;gpd0 1 GPIO_ACTIVE_HIGH /* SPK_AMP_SDA */</div><div class='del'>-			 &amp;gpd0 0 GPIO_ACTIVE_HIGH /* SPK_AMP_SCL */ &gt;;</div><div class='add'>+		sda-gpios = &lt;&amp;gpd0 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		scl-gpios = &lt;&amp;gpd0 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 		i2c-gpio,delay-us = &lt;2&gt;;</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;0&gt;;</div><div class='del'>-		status = "okay";</div><div class='ctx'> </div><div class='del'>-		max98504: max98504@31 {</div><div class='add'>+		max98504: amplifier@31 {</div><div class='ctx'> 			compatible = "maxim,max98504";</div><div class='ctx'> 			reg = &lt;0x31&gt;;</div><div class='del'>-			maxim,rx-path = &lt;1&gt;;</div><div class='del'>-			maxim,tx-path = &lt;1&gt;;</div><div class='del'>-			maxim,tx-channel-mask = &lt;3&gt;;</div><div class='del'>-			maxim,tx-channel-source = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			DIOVDD-supply = &lt;&amp;ldo3_reg&gt;;</div><div class='add'>+			DVDD-supply = &lt;&amp;ldo3_reg&gt;;</div><div class='add'>+			PVDD-supply = &lt;&amp;vph_pwr_regulator&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	irda_regulator: irda-regulator {</div><div class='add'>+	vph_pwr_regulator: regulator-vph-pwr {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VPH_PWR";</div><div class='add'>+		regulator-min-microvolt = &lt;4200000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;4200000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	irda_regulator: regulator-irda {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		enable-active-high;</div><div class='ctx'> 		gpio = &lt;&amp;gpr3 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='hunk'>@@ -118,20 +124,18 @@</div><div class='ctx'> 		audio-amplifier = &lt;&amp;max98504&gt;;</div><div class='ctx'> 		mic-bias-gpios = &lt;&amp;gpr3 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 		model = "wm5110";</div><div class='del'>-		samsung,audio-routing =</div><div class='del'>-			/* Headphone */</div><div class='del'>-			"HP", "HPOUT1L",</div><div class='del'>-			"HP", "HPOUT1R",</div><div class='del'>-</div><div class='del'>-			/* Speaker */</div><div class='del'>-			"SPK", "SPKOUT",</div><div class='del'>-			"SPKOUT", "HPOUT2L",</div><div class='del'>-			"SPKOUT", "HPOUT2R",</div><div class='del'>-</div><div class='del'>-			/* Receiver */</div><div class='del'>-			"RCV", "HPOUT3L",</div><div class='del'>-			"RCV", "HPOUT3R";</div><div class='del'>-		status = "okay";</div><div class='add'>+		audio-routing = /* Headphone */</div><div class='add'>+				"HP", "HPOUT1L",</div><div class='add'>+				"HP", "HPOUT1R",</div><div class='add'>+</div><div class='add'>+				/* Speaker */</div><div class='add'>+				"SPK", "SPKOUT",</div><div class='add'>+				"SPKOUT", "HPOUT2L",</div><div class='add'>+				"SPKOUT", "HPOUT2R",</div><div class='add'>+</div><div class='add'>+				/* Receiver */</div><div class='add'>+				"RCV", "HPOUT3L",</div><div class='add'>+				"RCV", "HPOUT3R";</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -386,12 +390,13 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> 	clock-frequency = &lt;2500000&gt;;</div><div class='ctx'> </div><div class='del'>-	s2mps13-pmic@66 {</div><div class='add'>+	pmic@66 {</div><div class='ctx'> 		compatible = "samsung,s2mps13-pmic";</div><div class='ctx'> 		interrupt-parent = &lt;&amp;gpa0&gt;;</div><div class='del'>-		interrupts = &lt;7 IRQ_TYPE_NONE&gt;;</div><div class='add'>+		interrupts = &lt;7 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 		reg = &lt;0x66&gt;;</div><div class='ctx'> 		samsung,s2mps11-wrstbi-ground;</div><div class='add'>+		wakeup-source;</div><div class='ctx'> </div><div class='ctx'> 		s2mps13_osc: clocks {</div><div class='ctx'> 			compatible = "samsung,s2mps13-clk";</div><div class='hunk'>@@ -794,9 +799,9 @@</div><div class='ctx'> 		compatible = "samsung,s3fwrn5-i2c";</div><div class='ctx'> 		reg = &lt;0x27&gt;;</div><div class='ctx'> 		interrupt-parent = &lt;&amp;gpa1&gt;;</div><div class='del'>-		interrupts = &lt;3 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-		s3fwrn5,en-gpios = &lt;&amp;gpf1 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-		s3fwrn5,fw-gpios = &lt;&amp;gpj0 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		interrupts = &lt;3 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+		en-gpios = &lt;&amp;gpf1 4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		wake-gpios = &lt;&amp;gpj0 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -817,7 +822,7 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> 	clock-frequency = &lt;1000000&gt;;</div><div class='ctx'> </div><div class='del'>-	sii8620@39 {</div><div class='add'>+	bridge@39 {</div><div class='ctx'> 		reg = &lt;0x39&gt;;</div><div class='ctx'> 		compatible = "sil,sii8620";</div><div class='ctx'> 		cvcc10-supply = &lt;&amp;ldo36_reg&gt;;</div><div class='hunk'>@@ -852,16 +857,16 @@</div><div class='ctx'> &amp;hsi2c_8 {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='del'>-	max77843@66 {</div><div class='add'>+	pmic@66 {</div><div class='ctx'> 		compatible = "maxim,max77843";</div><div class='ctx'> 		interrupt-parent = &lt;&amp;gpa1&gt;;</div><div class='ctx'> 		interrupts = &lt;5 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='ctx'> 		reg = &lt;0x66&gt;;</div><div class='ctx'> </div><div class='del'>-		muic: max77843-muic {</div><div class='add'>+		muic: extcon {</div><div class='ctx'> 			compatible = "maxim,max77843-muic";</div><div class='ctx'> </div><div class='del'>-			musb_con: musb_connector {</div><div class='add'>+			musb_con: connector {</div><div class='ctx'> 				compatible = "samsung,usb-connector-11pin",</div><div class='ctx'> 					     "usb-b-connector";</div><div class='ctx'> 				label = "micro-USB";</div><div class='hunk'>@@ -871,6 +876,17 @@</div><div class='ctx'> 					#address-cells = &lt;1&gt;;</div><div class='ctx'> 					#size-cells = &lt;0&gt;;</div><div class='ctx'> </div><div class='add'>+					port@0 {</div><div class='add'>+						/*</div><div class='add'>+						 * TODO: The DTS this is based on does not have</div><div class='add'>+						 * port@0 which is a required property. The ports</div><div class='add'>+						 * look incomplete and need fixing.</div><div class='add'>+						 * Add a disabled port just to satisfy dtschema.</div><div class='add'>+						 */</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+						status = "disabled";</div><div class='add'>+					};</div><div class='add'>+</div><div class='ctx'> 					port@3 {</div><div class='ctx'> 						reg = &lt;3&gt;;</div><div class='ctx'> 						musb_con_to_mhl: endpoint {</div><div class='hunk'>@@ -910,11 +926,10 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		haptic: max77843-haptic {</div><div class='add'>+		haptic: motor-driver {</div><div class='ctx'> 			compatible = "maxim,max77843-haptic";</div><div class='ctx'> 			haptic-supply = &lt;&amp;ldo38_reg&gt;;</div><div class='ctx'> 			pwms = &lt;&amp;pwm 0 33670 0&gt;;</div><div class='del'>-			pwm-names = "haptic";</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='hunk'>@@ -935,6 +950,7 @@</div><div class='ctx'> </div><div class='ctx'> &amp;mshc_0 {</div><div class='ctx'> 	status = "okay";</div><div class='add'>+	mmc-ddr-1_8v;</div><div class='ctx'> 	mmc-hs200-1_8v;</div><div class='ctx'> 	mmc-hs400-1_8v;</div><div class='ctx'> 	cap-mmc-highspeed;</div><div class='hunk'>@@ -969,6 +985,25 @@</div><div class='ctx'> 	bus-width = &lt;4&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;pcie {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pcie_bus &amp;pcie_wlanen&gt;;</div><div class='add'>+	vdd10-supply = &lt;&amp;ldo6_reg&gt;;</div><div class='add'>+	vdd18-supply = &lt;&amp;ldo7_reg&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;cmu_fsys CLK_MOUT_SCLK_PCIE_100_USER&gt;,</div><div class='add'>+			  &lt;&amp;cmu_top CLK_MOUT_SCLK_PCIE_100&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;cmu_top CLK_SCLK_PCIE_100_FSYS&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_MOUT_BUS_PLL_USER&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;0&gt;, &lt;100000000&gt;;</div><div class='add'>+	interrupt-map-mask = &lt;0 0 0 0&gt;;</div><div class='add'>+	interrupt-map = &lt;0 0 0 0 &amp;gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;ppmu_d0_general {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> 	events {</div><div class='hunk'>@@ -984,7 +1019,7 @@</div><div class='ctx'> 		ppmu_event0_d1_general: ppmu-event0-d1-general {</div><div class='ctx'> 		       event-name = "ppmu-event0-d1-general";</div><div class='ctx'> 	       };</div><div class='del'>-       };</div><div class='add'>+	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;pinctrl_alive {</div><div class='hunk'>@@ -992,82 +1027,82 @@</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;initial_alive&gt;;</div><div class='ctx'> </div><div class='ctx'> 	initial_alive: initial-state {</div><div class='del'>-		PIN(INPUT, gpa0-0, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpa0-1, NONE, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpa0-2, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpa0-3, NONE, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpa0-4, NONE, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpa0-5, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpa0-6, NONE, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpa0-7, NONE, FAST_SR1);</div><div class='del'>-</div><div class='del'>-		PIN(INPUT, gpa1-0, UP, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpa1-1, UP, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpa1-2, NONE, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpa1-3, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpa1-4, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpa1-5, NONE, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpa1-6, NONE, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpa1-7, NONE, FAST_SR1);</div><div class='del'>-</div><div class='del'>-		PIN(INPUT, gpa2-0, NONE, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpa2-1, NONE, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpa2-2, NONE, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpa2-3, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpa2-4, NONE, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpa2-5, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpa2-6, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpa2-7, NONE, FAST_SR1);</div><div class='del'>-</div><div class='del'>-		PIN(INPUT, gpa3-0, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpa3-1, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpa3-2, NONE, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpa3-3, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpa3-4, NONE, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpa3-5, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpa3-6, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpa3-7, DOWN, FAST_SR1);</div><div class='del'>-</div><div class='del'>-		PIN(INPUT, gpf1-0, NONE, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpf1-1, NONE, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpf1-2, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpf1-4, UP, FAST_SR1);</div><div class='del'>-		PIN(OUTPUT, gpf1-5, NONE, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpf1-6, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpf1-7, DOWN, FAST_SR1);</div><div class='del'>-</div><div class='del'>-		PIN(INPUT, gpf2-0, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpf2-1, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpf2-2, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpf2-3, DOWN, FAST_SR1);</div><div class='del'>-</div><div class='del'>-		PIN(INPUT, gpf3-0, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpf3-1, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpf3-2, NONE, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpf3-3, DOWN, FAST_SR1);</div><div class='del'>-</div><div class='del'>-		PIN(INPUT, gpf4-0, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpf4-1, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpf4-2, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpf4-3, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpf4-4, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpf4-5, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpf4-6, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpf4-7, DOWN, FAST_SR1);</div><div class='del'>-</div><div class='del'>-		PIN(INPUT, gpf5-0, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpf5-1, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpf5-2, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpf5-3, DOWN, FAST_SR1);</div><div class='del'>-		PIN(OUTPUT, gpf5-4, NONE, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpf5-5, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpf5-6, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpf5-7, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpa0-0, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpa0-1, NONE, FAST_SR1);</div><div class='add'>+		PIN_IN(gpa0-2, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpa0-3, NONE, FAST_SR1);</div><div class='add'>+		PIN_IN(gpa0-4, NONE, FAST_SR1);</div><div class='add'>+		PIN_IN(gpa0-5, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpa0-6, NONE, FAST_SR1);</div><div class='add'>+		PIN_IN(gpa0-7, NONE, FAST_SR1);</div><div class='add'>+</div><div class='add'>+		PIN_IN(gpa1-0, UP, FAST_SR1);</div><div class='add'>+		PIN_IN(gpa1-1, UP, FAST_SR1);</div><div class='add'>+		PIN_IN(gpa1-2, NONE, FAST_SR1);</div><div class='add'>+		PIN_IN(gpa1-3, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpa1-4, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpa1-5, NONE, FAST_SR1);</div><div class='add'>+		PIN_IN(gpa1-6, NONE, FAST_SR1);</div><div class='add'>+		PIN_IN(gpa1-7, NONE, FAST_SR1);</div><div class='add'>+</div><div class='add'>+		PIN_IN(gpa2-0, NONE, FAST_SR1);</div><div class='add'>+		PIN_IN(gpa2-1, NONE, FAST_SR1);</div><div class='add'>+		PIN_IN(gpa2-2, NONE, FAST_SR1);</div><div class='add'>+		PIN_IN(gpa2-3, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpa2-4, NONE, FAST_SR1);</div><div class='add'>+		PIN_IN(gpa2-5, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpa2-6, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpa2-7, NONE, FAST_SR1);</div><div class='add'>+</div><div class='add'>+		PIN_IN(gpa3-0, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpa3-1, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpa3-2, NONE, FAST_SR1);</div><div class='add'>+		PIN_IN(gpa3-3, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpa3-4, NONE, FAST_SR1);</div><div class='add'>+		PIN_IN(gpa3-5, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpa3-6, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpa3-7, DOWN, FAST_SR1);</div><div class='add'>+</div><div class='add'>+		PIN_IN(gpf1-0, NONE, FAST_SR1);</div><div class='add'>+		PIN_IN(gpf1-1, NONE, FAST_SR1);</div><div class='add'>+		PIN_IN(gpf1-2, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpf1-4, UP, FAST_SR1);</div><div class='add'>+		PIN_OT(gpf1-5, NONE, FAST_SR1);</div><div class='add'>+		PIN_IN(gpf1-6, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpf1-7, DOWN, FAST_SR1);</div><div class='add'>+</div><div class='add'>+		PIN_IN(gpf2-0, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpf2-1, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpf2-2, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpf2-3, DOWN, FAST_SR1);</div><div class='add'>+</div><div class='add'>+		PIN_IN(gpf3-0, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpf3-1, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpf3-2, NONE, FAST_SR1);</div><div class='add'>+		PIN_IN(gpf3-3, DOWN, FAST_SR1);</div><div class='add'>+</div><div class='add'>+		PIN_IN(gpf4-0, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpf4-1, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpf4-2, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpf4-3, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpf4-4, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpf4-5, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpf4-6, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpf4-7, DOWN, FAST_SR1);</div><div class='add'>+</div><div class='add'>+		PIN_IN(gpf5-0, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpf5-1, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpf5-2, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpf5-3, DOWN, FAST_SR1);</div><div class='add'>+		PIN_OT(gpf5-4, NONE, FAST_SR1);</div><div class='add'>+		PIN_IN(gpf5-5, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpf5-6, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpf5-7, DOWN, FAST_SR1);</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	te_irq: te_irq {</div><div class='add'>+	te_irq: te-irq-pins {</div><div class='ctx'> 		samsung,pins = "gpf1-3";</div><div class='del'>-		samsung,pin-function = &lt;0xf&gt;;</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -1076,8 +1111,8 @@</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;initial_cpif&gt;;</div><div class='ctx'> </div><div class='ctx'> 	initial_cpif: initial-state {</div><div class='del'>-		PIN(INPUT, gpv6-0, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpv6-1, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpv6-0, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpv6-1, DOWN, FAST_SR1);</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -1085,10 +1120,16 @@</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;initial_ese&gt;;</div><div class='ctx'> </div><div class='add'>+	pcie_wlanen: pcie-wlanen-pins {</div><div class='add'>+		samsung,pins = "gpj2-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	initial_ese: initial-state {</div><div class='del'>-		PIN(INPUT, gpj2-0, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpj2-1, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpj2-2, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpj2-1, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpj2-2, DOWN, FAST_SR1);</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -1097,11 +1138,11 @@</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;initial_fsys&gt;;</div><div class='ctx'> </div><div class='ctx'> 	initial_fsys: initial-state {</div><div class='del'>-		PIN(INPUT, gpr3-0, NONE, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpr3-1, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpr3-2, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpr3-3, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpr3-7, NONE, FAST_SR1);</div><div class='add'>+		PIN_IN(gpr3-0, NONE, FAST_SR1);</div><div class='add'>+		PIN_IN(gpr3-1, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpr3-2, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpr3-3, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpr3-7, NONE, FAST_SR1);</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -1110,14 +1151,14 @@</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;initial_imem&gt;;</div><div class='ctx'> </div><div class='ctx'> 	initial_imem: initial-state {</div><div class='del'>-		PIN(INPUT, gpf0-0, UP, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpf0-1, UP, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpf0-2, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpf0-3, UP, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpf0-4, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpf0-5, NONE, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpf0-6, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpf0-7, UP, FAST_SR1);</div><div class='add'>+		PIN_IN(gpf0-0, UP, FAST_SR1);</div><div class='add'>+		PIN_IN(gpf0-1, UP, FAST_SR1);</div><div class='add'>+		PIN_IN(gpf0-2, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpf0-3, UP, FAST_SR1);</div><div class='add'>+		PIN_IN(gpf0-4, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpf0-5, NONE, FAST_SR1);</div><div class='add'>+		PIN_IN(gpf0-6, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpf0-7, UP, FAST_SR1);</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -1126,7 +1167,7 @@</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;initial_nfc&gt;;</div><div class='ctx'> </div><div class='ctx'> 	initial_nfc: initial-state {</div><div class='del'>-		PIN(INPUT, gpj0-2, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpj0-2, DOWN, FAST_SR1);</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -1135,53 +1176,53 @@</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;initial_peric&gt;;</div><div class='ctx'> </div><div class='ctx'> 	initial_peric: initial-state {</div><div class='del'>-		PIN(INPUT, gpv7-0, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpv7-1, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpv7-2, NONE, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpv7-3, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpv7-4, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpv7-5, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpv7-0, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpv7-1, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpv7-2, NONE, FAST_SR1);</div><div class='add'>+		PIN_IN(gpv7-3, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpv7-4, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpv7-5, DOWN, FAST_SR1);</div><div class='ctx'> </div><div class='del'>-		PIN(INPUT, gpb0-4, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpb0-4, DOWN, FAST_SR1);</div><div class='ctx'> </div><div class='del'>-		PIN(INPUT, gpc0-2, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpc0-5, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpc0-7, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpc0-2, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpc0-5, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpc0-7, DOWN, FAST_SR1);</div><div class='ctx'> </div><div class='del'>-		PIN(INPUT, gpc1-1, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpc1-1, DOWN, FAST_SR1);</div><div class='ctx'> </div><div class='del'>-		PIN(INPUT, gpc3-4, NONE, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpc3-5, NONE, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpc3-6, NONE, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpc3-7, NONE, FAST_SR1);</div><div class='add'>+		PIN_IN(gpc3-4, NONE, FAST_SR1);</div><div class='add'>+		PIN_IN(gpc3-5, NONE, FAST_SR1);</div><div class='add'>+		PIN_IN(gpc3-6, NONE, FAST_SR1);</div><div class='add'>+		PIN_IN(gpc3-7, NONE, FAST_SR1);</div><div class='ctx'> </div><div class='del'>-		PIN(OUTPUT, gpg0-0, NONE, FAST_SR1);</div><div class='del'>-		PIN(2, gpg0-1, DOWN, FAST_SR1);</div><div class='add'>+		PIN_OT(gpg0-0, NONE, FAST_SR1);</div><div class='add'>+		PIN_F2(gpg0-1, DOWN, FAST_SR1);</div><div class='ctx'> </div><div class='del'>-		PIN(INPUT, gpd2-5, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpd2-5, DOWN, FAST_SR1);</div><div class='ctx'> </div><div class='del'>-		PIN(INPUT, gpd4-0, NONE, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpd4-1, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpd4-2, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpd4-3, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpd4-4, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpd4-0, NONE, FAST_SR1);</div><div class='add'>+		PIN_IN(gpd4-1, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpd4-2, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpd4-3, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpd4-4, DOWN, FAST_SR1);</div><div class='ctx'> </div><div class='del'>-		PIN(INPUT, gpd6-3, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpd6-3, DOWN, FAST_SR1);</div><div class='ctx'> </div><div class='del'>-		PIN(INPUT, gpd8-1, UP, FAST_SR1);</div><div class='add'>+		PIN_IN(gpd8-1, UP, FAST_SR1);</div><div class='ctx'> </div><div class='del'>-		PIN(INPUT, gpg1-0, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpg1-1, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpg1-2, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpg1-3, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpg1-4, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpg1-0, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpg1-1, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpg1-2, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpg1-3, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpg1-4, DOWN, FAST_SR1);</div><div class='ctx'> </div><div class='del'>-		PIN(INPUT, gpg2-0, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpg2-1, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpg2-0, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpg2-1, DOWN, FAST_SR1);</div><div class='ctx'> </div><div class='del'>-		PIN(INPUT, gpg3-0, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpg3-1, DOWN, FAST_SR1);</div><div class='del'>-		PIN(INPUT, gpg3-5, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpg3-0, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpg3-1, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpg3-5, DOWN, FAST_SR1);</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -1190,7 +1231,7 @@</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;initial_touch&gt;;</div><div class='ctx'> </div><div class='ctx'> 	initial_touch: initial-state {</div><div class='del'>-		PIN(INPUT, gpj1-2, DOWN, FAST_SR1);</div><div class='add'>+		PIN_IN(gpj1-2, DOWN, FAST_SR1);</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -1231,7 +1272,7 @@</div><div class='ctx'> 	cs-gpios = &lt;&amp;gpd6 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='del'>-	wm5110: wm5110-codec@0 {</div><div class='add'>+	wm5110: audio-codec@0 {</div><div class='ctx'> 		compatible = "wlf,wm5110";</div><div class='ctx'> 		reg = &lt;0x0&gt;;</div><div class='ctx'> 		spi-max-frequency = &lt;20000000&gt;;</div><div class='hunk'>@@ -1243,11 +1284,13 @@</div><div class='ctx'> </div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='ctx'> 		wlf,micd-detect-debounce = &lt;300&gt;;</div><div class='ctx'> 		wlf,micd-bias-start-time = &lt;0x1&gt;;</div><div class='ctx'> 		wlf,micd-rate = &lt;0x7&gt;;</div><div class='del'>-		wlf,micd-dbtime = &lt;0x1&gt;;</div><div class='add'>+		wlf,micd-dbtime = &lt;0x2&gt;;</div><div class='ctx'> 		wlf,micd-force-micbias;</div><div class='ctx'> 		wlf,micd-configs = &lt;0x0 1 0&gt;;</div><div class='ctx'> 		wlf,hpdet-channel = &lt;1&gt;;</div><div class='hunk'>@@ -1263,6 +1306,8 @@</div><div class='ctx'> 		CPVDD-supply = &lt;&amp;ldo18_reg&gt;;</div><div class='ctx'> 		DBVDD2-supply = &lt;&amp;ldo18_reg&gt;;</div><div class='ctx'> 		DBVDD3-supply = &lt;&amp;ldo18_reg&gt;;</div><div class='add'>+		SPKVDDL-supply = &lt;&amp;vph_pwr_regulator&gt;;</div><div class='add'>+		SPKVDDR-supply = &lt;&amp;vph_pwr_regulator&gt;;</div><div class='ctx'> </div><div class='ctx'> 		controller-data {</div><div class='ctx'> 			samsung,spi-feedback-delay = &lt;0&gt;;</div><div class='hunk'>@@ -1279,7 +1324,7 @@</div><div class='ctx'> 		reg = &lt;0x0&gt;;</div><div class='ctx'> 		spi-max-frequency = &lt;5000000&gt;;</div><div class='ctx'> 		power-supply = &lt;&amp;irda_regulator&gt;;</div><div class='del'>-		duty-cycle = &lt;60&gt;;</div><div class='add'>+		duty-cycle = /bits/ 8 &lt;60&gt;;</div><div class='ctx'> 		led-active-low;</div><div class='ctx'> </div><div class='ctx'> 		controller-data {</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts<br/>index fdd0796b29d4..aca01709fd29 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynos5433-tm2.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/exynos5433-tm2.dts</a></div><div class='hunk'>@@ -13,6 +13,7 @@</div><div class='ctx'> / {</div><div class='ctx'> 	model = "Samsung TM2 board";</div><div class='ctx'> 	compatible = "samsung,tm2", "samsung,exynos5433";</div><div class='add'>+	chassis-type = "handset";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cmu_disp {</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts<br/>index 089fc7a1af67..22d26460f3dd 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts</a></div><div class='hunk'>@@ -13,6 +13,7 @@</div><div class='ctx'> / {</div><div class='ctx'> 	model = "Samsung TM2E board";</div><div class='ctx'> 	compatible = "samsung,tm2e", "samsung,exynos5433";</div><div class='add'>+	chassis-type = "handset";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cmu_disp {</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi<br/>index 6721966140f4..fa2029e280a5 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynos5433.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynos5433.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynos5433.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/exynos5433.dtsi</a></div><div class='hunk'>@@ -23,8 +23,8 @@</div><div class='ctx'> </div><div class='ctx'> 	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='ctx'> </div><div class='del'>-	arm_a53_pmu {</div><div class='del'>-		compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3";</div><div class='add'>+	arm-a53-pmu {</div><div class='add'>+		compatible = "arm,cortex-a53-pmu";</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 			     &lt;GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 			     &lt;GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='hunk'>@@ -32,8 +32,8 @@</div><div class='ctx'> 		interrupt-affinity = &lt;&amp;cpu0&gt;, &lt;&amp;cpu1&gt;, &lt;&amp;cpu2&gt;, &lt;&amp;cpu3&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	arm_a57_pmu {</div><div class='del'>-		compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3";</div><div class='add'>+	arm-a57-pmu {</div><div class='add'>+		compatible = "arm,cortex-a57-pmu";</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 			     &lt;GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 			     &lt;GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='hunk'>@@ -52,16 +52,54 @@</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;0&gt;;</div><div class='ctx'> </div><div class='add'>+		cpu-map {</div><div class='add'>+			cluster0 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu0&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu1&gt;;</div><div class='add'>+				};</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu2&gt;;</div><div class='add'>+				};</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu3&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cluster1 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu4&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu5&gt;;</div><div class='add'>+				};</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu6&gt;;</div><div class='add'>+				};</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu7&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		cpu0: cpu@100 {</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			reg = &lt;0x100&gt;;</div><div class='del'>-			clock-frequency = &lt;1300000000&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;cmu_apollo CLK_SCLK_APOLLO&gt;;</div><div class='ctx'> 			clock-names = "apolloclk";</div><div class='ctx'> 			operating-points-v2 = &lt;&amp;cluster_a53_opp_table&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;cluster_a53_l2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu1: cpu@101 {</div><div class='hunk'>@@ -69,9 +107,15 @@</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			reg = &lt;0x101&gt;;</div><div class='del'>-			clock-frequency = &lt;1300000000&gt;;</div><div class='ctx'> 			operating-points-v2 = &lt;&amp;cluster_a53_opp_table&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;cluster_a53_l2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu2: cpu@102 {</div><div class='hunk'>@@ -79,9 +123,15 @@</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			reg = &lt;0x102&gt;;</div><div class='del'>-			clock-frequency = &lt;1300000000&gt;;</div><div class='ctx'> 			operating-points-v2 = &lt;&amp;cluster_a53_opp_table&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;cluster_a53_l2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu3: cpu@103 {</div><div class='hunk'>@@ -89,9 +139,15 @@</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			reg = &lt;0x103&gt;;</div><div class='del'>-			clock-frequency = &lt;1300000000&gt;;</div><div class='ctx'> 			operating-points-v2 = &lt;&amp;cluster_a53_opp_table&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;cluster_a53_l2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu4: cpu@0 {</div><div class='hunk'>@@ -99,11 +155,17 @@</div><div class='ctx'> 			compatible = "arm,cortex-a57";</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			reg = &lt;0x0&gt;;</div><div class='del'>-			clock-frequency = &lt;1900000000&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;cmu_atlas CLK_SCLK_ATLAS&gt;;</div><div class='ctx'> 			clock-names = "atlasclk";</div><div class='ctx'> 			operating-points-v2 = &lt;&amp;cluster_a57_opp_table&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			i-cache-size = &lt;0xc000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;cluster_a57_l2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu5: cpu@1 {</div><div class='hunk'>@@ -111,9 +173,15 @@</div><div class='ctx'> 			compatible = "arm,cortex-a57";</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			reg = &lt;0x1&gt;;</div><div class='del'>-			clock-frequency = &lt;1900000000&gt;;</div><div class='ctx'> 			operating-points-v2 = &lt;&amp;cluster_a57_opp_table&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			i-cache-size = &lt;0xc000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;cluster_a57_l2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu6: cpu@2 {</div><div class='hunk'>@@ -121,9 +189,15 @@</div><div class='ctx'> 			compatible = "arm,cortex-a57";</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			reg = &lt;0x2&gt;;</div><div class='del'>-			clock-frequency = &lt;1900000000&gt;;</div><div class='ctx'> 			operating-points-v2 = &lt;&amp;cluster_a57_opp_table&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			i-cache-size = &lt;0xc000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;cluster_a57_l2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu7: cpu@3 {</div><div class='hunk'>@@ -131,13 +205,37 @@</div><div class='ctx'> 			compatible = "arm,cortex-a57";</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			reg = &lt;0x3&gt;;</div><div class='del'>-			clock-frequency = &lt;1900000000&gt;;</div><div class='ctx'> 			operating-points-v2 = &lt;&amp;cluster_a57_opp_table&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			i-cache-size = &lt;0xc000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;cluster_a57_l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cluster_a57_l2: l2-cache0 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x200000&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;2048&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cluster_a53_l2: l2-cache1 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x40000&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;256&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	cluster_a53_opp_table: opp_table0 {</div><div class='add'>+	cluster_a53_opp_table: opp-table-0 {</div><div class='ctx'> 		compatible = "operating-points-v2";</div><div class='ctx'> 		opp-shared;</div><div class='ctx'> </div><div class='hunk'>@@ -183,7 +281,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	cluster_a57_opp_table: opp_table1 {</div><div class='add'>+	cluster_a57_opp_table: opp-table-1 {</div><div class='ctx'> 		compatible = "operating-points-v2";</div><div class='ctx'> 		opp-shared;</div><div class='ctx'> </div><div class='hunk'>@@ -253,17 +351,18 @@</div><div class='ctx'> 		compatible = "arm,psci";</div><div class='ctx'> 		method = "smc";</div><div class='ctx'> 		cpu_off = &lt;0x84000002&gt;;</div><div class='del'>-		cpu_on = &lt;0xC4000003&gt;;</div><div class='add'>+		cpu_on = &lt;0xc4000003&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	soc: soc {</div><div class='add'>+	soc: soc@0 {</div><div class='ctx'> 		compatible = "simple-bus";</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;1&gt;;</div><div class='ctx'> 		ranges = &lt;0x0 0x0 0x0 0x18000000&gt;;</div><div class='ctx'> </div><div class='ctx'> 		chipid@10000000 {</div><div class='del'>-			compatible = "samsung,exynos4210-chipid";</div><div class='add'>+			compatible = "samsung,exynos5433-chipid",</div><div class='add'>+				     "samsung,exynos4210-chipid";</div><div class='ctx'> 			reg = &lt;0x10000000 0x100&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -564,9 +663,9 @@</div><div class='ctx'> 			compatible = "samsung,exynos5433-slim-sss";</div><div class='ctx'> 			reg = &lt;0x11140000 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clock-names = "aclk", "pclk";</div><div class='del'>-			clocks = &lt;&amp;cmu_imem CLK_ACLK_SLIMSSS&gt;,</div><div class='del'>-				 &lt;&amp;cmu_imem CLK_PCLK_SLIMSSS&gt;;</div><div class='add'>+			clock-names = "pclk", "aclk";</div><div class='add'>+			clocks = &lt;&amp;cmu_imem CLK_PCLK_SLIMSSS&gt;,</div><div class='add'>+				 &lt;&amp;cmu_imem CLK_ACLK_SLIMSSS&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		pd_gscl: power-domain@105c4000 {</div><div class='hunk'>@@ -704,7 +803,8 @@</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		timer@101c0000 {</div><div class='del'>-			compatible = "samsung,exynos4210-mct";</div><div class='add'>+			compatible = "samsung,exynos5433-mct",</div><div class='add'>+				     "samsung,exynos4210-mct";</div><div class='ctx'> 			reg = &lt;0x101c0000 0x800&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 				&lt;GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='hunk'>@@ -751,7 +851,8 @@</div><div class='ctx'> 			reg = &lt;0x10580000 0x1a20&gt;, &lt;0x11090000 0x100&gt;;</div><div class='ctx'> </div><div class='ctx'> 			wakeup-interrupt-controller {</div><div class='del'>-				compatible = "samsung,exynos7-wakeup-eint";</div><div class='add'>+				compatible = "samsung,exynos5433-wakeup-eint",</div><div class='add'>+					     "samsung,exynos7-wakeup-eint";</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='hunk'>@@ -812,12 +913,20 @@</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		pmu_system_controller: system-controller@105c0000 {</div><div class='del'>-			compatible = "samsung,exynos5433-pmu", "syscon";</div><div class='add'>+			compatible = "samsung,exynos5433-pmu", "simple-mfd", "syscon";</div><div class='ctx'> 			reg = &lt;0x105c0000 0x5008&gt;;</div><div class='ctx'> 			#clock-cells = &lt;1&gt;;</div><div class='ctx'> 			clock-names = "clkout16";</div><div class='ctx'> 			clocks = &lt;&amp;xxti&gt;;</div><div class='ctx'> </div><div class='add'>+			mipi_phy: mipi-phy {</div><div class='add'>+				compatible = "samsung,exynos5433-mipi-video-phy";</div><div class='add'>+				#phy-cells = &lt;1&gt;;</div><div class='add'>+				samsung,cam0-sysreg = &lt;&amp;syscon_cam0&gt;;</div><div class='add'>+				samsung,cam1-sysreg = &lt;&amp;syscon_cam1&gt;;</div><div class='add'>+				samsung,disp-sysreg = &lt;&amp;syscon_disp&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='ctx'> 			reboot: syscon-reboot {</div><div class='ctx'> 				compatible = "syscon-reboot";</div><div class='ctx'> 				regmap = &lt;&amp;pmu_system_controller&gt;;</div><div class='hunk'>@@ -828,6 +937,7 @@</div><div class='ctx'> </div><div class='ctx'> 		gic: interrupt-controller@11001000 {</div><div class='ctx'> 			compatible = "arm,gic-400";</div><div class='add'>+			#address-cells = &lt;0&gt;;</div><div class='ctx'> 			#interrupt-cells = &lt;3&gt;;</div><div class='ctx'> 			interrupt-controller;</div><div class='ctx'> 			reg = &lt;0x11001000 0x1000&gt;,</div><div class='hunk'>@@ -837,15 +947,6 @@</div><div class='ctx'> 			interrupts = &lt;GIC_PPI 9 0xf04&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		mipi_phy: video-phy {</div><div class='del'>-			compatible = "samsung,exynos5433-mipi-video-phy";</div><div class='del'>-			#phy-cells = &lt;1&gt;;</div><div class='del'>-			samsung,pmu-syscon = &lt;&amp;pmu_system_controller&gt;;</div><div class='del'>-			samsung,cam0-sysreg = &lt;&amp;syscon_cam0&gt;;</div><div class='del'>-			samsung,cam1-sysreg = &lt;&amp;syscon_cam1&gt;;</div><div class='del'>-			samsung,disp-sysreg = &lt;&amp;syscon_disp&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='ctx'> 		decon: decon@13800000 {</div><div class='ctx'> 			compatible = "samsung,exynos5433-decon";</div><div class='ctx'> 			reg = &lt;0x13800000 0x2104&gt;;</div><div class='hunk'>@@ -921,7 +1022,7 @@</div><div class='ctx'> </div><div class='ctx'> 		dsi: dsi@13900000 {</div><div class='ctx'> 			compatible = "samsung,exynos5433-mipi-dsi";</div><div class='del'>-			reg = &lt;0x13900000 0xC0&gt;;</div><div class='add'>+			reg = &lt;0x13900000 0xc0&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			phys = &lt;&amp;mipi_phy 1&gt;;</div><div class='ctx'> 			phy-names = "dsim";</div><div class='hunk'>@@ -1015,20 +1116,29 @@</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		syscon_disp: syscon@13b80000 {</div><div class='del'>-			compatible = "syscon";</div><div class='add'>+			compatible = "samsung,exynos5433-disp-sysreg",</div><div class='add'>+				     "samsung,exynos5433-sysreg", "syscon";</div><div class='ctx'> 			reg = &lt;0x13b80000 0x1010&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		syscon_cam0: syscon@120f0000 {</div><div class='del'>-			compatible = "syscon";</div><div class='add'>+			compatible = "samsung,exynos5433-cam0-sysreg",</div><div class='add'>+				     "samsung,exynos5433-sysreg", "syscon";</div><div class='ctx'> 			reg = &lt;0x120f0000 0x1020&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		syscon_cam1: syscon@145f0000 {</div><div class='del'>-			compatible = "syscon";</div><div class='add'>+			compatible = "samsung,exynos5433-cam1-sysreg",</div><div class='add'>+				     "samsung,exynos5433-sysreg", "syscon";</div><div class='ctx'> 			reg = &lt;0x145f0000 0x1038&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		syscon_fsys: syscon@156f0000 {</div><div class='add'>+			compatible = "samsung,exynos5433-fsys-sysreg",</div><div class='add'>+				     "samsung,exynos5433-sysreg", "syscon";</div><div class='add'>+			reg = &lt;0x156f0000 0x1044&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		gsc_0: video-scaler@13c00000 {</div><div class='ctx'> 			compatible = "samsung,exynos5433-gsc";</div><div class='ctx'> 			reg = &lt;0x13c00000 0x1000&gt;;</div><div class='hunk'>@@ -1087,7 +1197,7 @@</div><div class='ctx'> 			operating-points-v2 = &lt;&amp;gpu_opp_table&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> </div><div class='del'>-			gpu_opp_table: opp_table {</div><div class='add'>+			gpu_opp_table: opp-table {</div><div class='ctx'> 				compatible = "operating-points-v2";</div><div class='ctx'> </div><div class='ctx'> 				opp-160000000 {</div><div class='hunk'>@@ -1164,7 +1274,7 @@</div><div class='ctx'> </div><div class='ctx'> 		mfc: codec@152e0000 {</div><div class='ctx'> 			compatible = "samsung,exynos5433-mfc";</div><div class='del'>-			reg = &lt;0x152E0000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x152e0000 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clock-names = "pclk", "aclk", "aclk_xiu";</div><div class='ctx'> 			clocks = &lt;&amp;cmu_mfc CLK_PCLK_MFC&gt;,</div><div class='hunk'>@@ -1221,7 +1331,7 @@</div><div class='ctx'> </div><div class='ctx'> 		sysmmu_gscl0: sysmmu@13c80000 {</div><div class='ctx'> 			compatible = "samsung,exynos-sysmmu";</div><div class='del'>-			reg = &lt;0x13C80000 0x1000&gt;;</div><div class='add'>+			reg = &lt;0x13c80000 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clock-names = "aclk", "pclk";</div><div class='ctx'> 			clocks = &lt;&amp;cmu_gscl CLK_ACLK_SMMU_GSCL0&gt;,</div><div class='hunk'>@@ -1232,7 +1342,7 @@</div><div class='ctx'> </div><div class='ctx'> 		sysmmu_gscl1: sysmmu@13c90000 {</div><div class='ctx'> 			compatible = "samsung,exynos-sysmmu";</div><div class='del'>-			reg = &lt;0x13C90000 0x1000&gt;;</div><div class='add'>+			reg = &lt;0x13c90000 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clock-names = "aclk", "pclk";</div><div class='ctx'> 			clocks = &lt;&amp;cmu_gscl CLK_ACLK_SMMU_GSCL1&gt;,</div><div class='hunk'>@@ -1243,7 +1353,7 @@</div><div class='ctx'> </div><div class='ctx'> 		sysmmu_gscl2: sysmmu@13ca0000 {</div><div class='ctx'> 			compatible = "samsung,exynos-sysmmu";</div><div class='del'>-			reg = &lt;0x13CA0000 0x1000&gt;;</div><div class='add'>+			reg = &lt;0x13ca0000 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clock-names = "aclk", "pclk";</div><div class='ctx'> 			clocks = &lt;&amp;cmu_gscl CLK_ACLK_SMMU_GSCL2&gt;,</div><div class='hunk'>@@ -1359,6 +1469,7 @@</div><div class='ctx'> 			pinctrl-names = "default";</div><div class='ctx'> 			pinctrl-0 = &lt;&amp;spi0_bus&gt;;</div><div class='ctx'> 			num-cs = &lt;1&gt;;</div><div class='add'>+			fifo-depth = &lt;256&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -1378,6 +1489,7 @@</div><div class='ctx'> 			pinctrl-names = "default";</div><div class='ctx'> 			pinctrl-0 = &lt;&amp;spi1_bus&gt;;</div><div class='ctx'> 			num-cs = &lt;1&gt;;</div><div class='add'>+			fifo-depth = &lt;64&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -1397,6 +1509,7 @@</div><div class='ctx'> 			pinctrl-names = "default";</div><div class='ctx'> 			pinctrl-0 = &lt;&amp;spi2_bus&gt;;</div><div class='ctx'> 			num-cs = &lt;1&gt;;</div><div class='add'>+			fifo-depth = &lt;64&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -1416,6 +1529,7 @@</div><div class='ctx'> 			pinctrl-names = "default";</div><div class='ctx'> 			pinctrl-0 = &lt;&amp;spi3_bus&gt;;</div><div class='ctx'> 			num-cs = &lt;1&gt;;</div><div class='add'>+			fifo-depth = &lt;64&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -1435,22 +1549,22 @@</div><div class='ctx'> 			pinctrl-names = "default";</div><div class='ctx'> 			pinctrl-0 = &lt;&amp;spi4_bus&gt;;</div><div class='ctx'> 			num-cs = &lt;1&gt;;</div><div class='add'>+			fifo-depth = &lt;64&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		adc: adc@14d10000 {</div><div class='del'>-			compatible = "samsung,exynos7-adc";</div><div class='add'>+			compatible = "samsung,exynos5433-adc", "samsung,exynos7-adc";</div><div class='ctx'> 			reg = &lt;0x14d10000 0x100&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clock-names = "adc";</div><div class='ctx'> 			clocks = &lt;&amp;cmu_peric CLK_PCLK_ADCIF&gt;;</div><div class='ctx'> 			#io-channel-cells = &lt;1&gt;;</div><div class='del'>-			io-channel-ranges;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		i2s1: i2s@14d60000 {</div><div class='del'>-			compatible = "samsung,exynos7-i2s";</div><div class='add'>+			compatible = "samsung,exynos5433-i2s", "samsung,exynos7-i2s";</div><div class='ctx'> 			reg = &lt;0x14d60000 0x100&gt;;</div><div class='ctx'> 			dmas = &lt;&amp;pdma0 31&gt;, &lt;&amp;pdma0 30&gt;;</div><div class='ctx'> 			dma-names = "tx", "rx";</div><div class='hunk'>@@ -1460,16 +1574,12 @@</div><div class='ctx'> 				 &lt;&amp;cmu_peric CLK_SCLK_I2S1&gt;;</div><div class='ctx'> 			clock-names = "iis", "i2s_opclk0", "i2s_opclk1";</div><div class='ctx'> 			#clock-cells = &lt;1&gt;;</div><div class='del'>-			samsung,supports-6ch;</div><div class='del'>-			samsung,supports-rstclr;</div><div class='del'>-			samsung,supports-tdm;</div><div class='del'>-			samsung,supports-low-rfs;</div><div class='ctx'> 			#sound-dai-cells = &lt;1&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		pwm: pwm@14dd0000 {</div><div class='del'>-			compatible = "samsung,exynos4210-pwm";</div><div class='add'>+			compatible = "samsung,exynos5433-pwm", "samsung,exynos4210-pwm";</div><div class='ctx'> 			reg = &lt;0x14dd0000 0x100&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 				     &lt;GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='hunk'>@@ -1483,8 +1593,9 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		hsi2c_0: hsi2c@14e40000 {</div><div class='del'>-			compatible = "samsung,exynos7-hsi2c";</div><div class='add'>+		hsi2c_0: i2c@14e40000 {</div><div class='add'>+			compatible = "samsung,exynos5433-hsi2c",</div><div class='add'>+				     "samsung,exynos7-hsi2c";</div><div class='ctx'> 			reg = &lt;0x14e40000 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='hunk'>@@ -1496,8 +1607,9 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		hsi2c_1: hsi2c@14e50000 {</div><div class='del'>-			compatible = "samsung,exynos7-hsi2c";</div><div class='add'>+		hsi2c_1: i2c@14e50000 {</div><div class='add'>+			compatible = "samsung,exynos5433-hsi2c",</div><div class='add'>+				     "samsung,exynos7-hsi2c";</div><div class='ctx'> 			reg = &lt;0x14e50000 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='hunk'>@@ -1509,8 +1621,9 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		hsi2c_2: hsi2c@14e60000 {</div><div class='del'>-			compatible = "samsung,exynos7-hsi2c";</div><div class='add'>+		hsi2c_2: i2c@14e60000 {</div><div class='add'>+			compatible = "samsung,exynos5433-hsi2c",</div><div class='add'>+				     "samsung,exynos7-hsi2c";</div><div class='ctx'> 			reg = &lt;0x14e60000 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='hunk'>@@ -1522,8 +1635,9 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		hsi2c_3: hsi2c@14e70000 {</div><div class='del'>-			compatible = "samsung,exynos7-hsi2c";</div><div class='add'>+		hsi2c_3: i2c@14e70000 {</div><div class='add'>+			compatible = "samsung,exynos5433-hsi2c",</div><div class='add'>+				     "samsung,exynos7-hsi2c";</div><div class='ctx'> 			reg = &lt;0x14e70000 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='hunk'>@@ -1535,8 +1649,9 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		hsi2c_4: hsi2c@14ec0000 {</div><div class='del'>-			compatible = "samsung,exynos7-hsi2c";</div><div class='add'>+		hsi2c_4: i2c@14ec0000 {</div><div class='add'>+			compatible = "samsung,exynos5433-hsi2c",</div><div class='add'>+				     "samsung,exynos7-hsi2c";</div><div class='ctx'> 			reg = &lt;0x14ec0000 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='hunk'>@@ -1548,8 +1663,9 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		hsi2c_5: hsi2c@14ed0000 {</div><div class='del'>-			compatible = "samsung,exynos7-hsi2c";</div><div class='add'>+		hsi2c_5: i2c@14ed0000 {</div><div class='add'>+			compatible = "samsung,exynos5433-hsi2c",</div><div class='add'>+				     "samsung,exynos7-hsi2c";</div><div class='ctx'> 			reg = &lt;0x14ed0000 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='hunk'>@@ -1561,8 +1677,9 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		hsi2c_6: hsi2c@14ee0000 {</div><div class='del'>-			compatible = "samsung,exynos7-hsi2c";</div><div class='add'>+		hsi2c_6: i2c@14ee0000 {</div><div class='add'>+			compatible = "samsung,exynos5433-hsi2c",</div><div class='add'>+				     "samsung,exynos7-hsi2c";</div><div class='ctx'> 			reg = &lt;0x14ee0000 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='hunk'>@@ -1574,8 +1691,9 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		hsi2c_7: hsi2c@14ef0000 {</div><div class='del'>-			compatible = "samsung,exynos7-hsi2c";</div><div class='add'>+		hsi2c_7: i2c@14ef0000 {</div><div class='add'>+			compatible = "samsung,exynos5433-hsi2c",</div><div class='add'>+				     "samsung,exynos7-hsi2c";</div><div class='ctx'> 			reg = &lt;0x14ef0000 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='hunk'>@@ -1587,8 +1705,9 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		hsi2c_8: hsi2c@14d90000 {</div><div class='del'>-			compatible = "samsung,exynos7-hsi2c";</div><div class='add'>+		hsi2c_8: i2c@14d90000 {</div><div class='add'>+			compatible = "samsung,exynos5433-hsi2c",</div><div class='add'>+				     "samsung,exynos7-hsi2c";</div><div class='ctx'> 			reg = &lt;0x14d90000 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='hunk'>@@ -1600,8 +1719,9 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		hsi2c_9: hsi2c@14da0000 {</div><div class='del'>-			compatible = "samsung,exynos7-hsi2c";</div><div class='add'>+		hsi2c_9: i2c@14da0000 {</div><div class='add'>+			compatible = "samsung,exynos5433-hsi2c",</div><div class='add'>+				     "samsung,exynos7-hsi2c";</div><div class='ctx'> 			reg = &lt;0x14da0000 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='hunk'>@@ -1613,8 +1733,9 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		hsi2c_10: hsi2c@14de0000 {</div><div class='del'>-			compatible = "samsung,exynos7-hsi2c";</div><div class='add'>+		hsi2c_10: i2c@14de0000 {</div><div class='add'>+			compatible = "samsung,exynos5433-hsi2c",</div><div class='add'>+				     "samsung,exynos7-hsi2c";</div><div class='ctx'> 			reg = &lt;0x14de0000 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='hunk'>@@ -1626,8 +1747,9 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		hsi2c_11: hsi2c@14df0000 {</div><div class='del'>-			compatible = "samsung,exynos7-hsi2c";</div><div class='add'>+		hsi2c_11: i2c@14df0000 {</div><div class='add'>+			compatible = "samsung,exynos5433-hsi2c",</div><div class='add'>+				     "samsung,exynos7-hsi2c";</div><div class='ctx'> 			reg = &lt;0x14df0000 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='hunk'>@@ -1639,7 +1761,7 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		usbdrd30: usbdrd {</div><div class='add'>+		usbdrd30: usb@15400000 {</div><div class='ctx'> 			compatible = "samsung,exynos5433-dwusb3";</div><div class='ctx'> 			clocks = &lt;&amp;cmu_fsys CLK_ACLK_USBDRD30&gt;,</div><div class='ctx'> 				&lt;&amp;cmu_fsys CLK_SCLK_USBDRD30&gt;,</div><div class='hunk'>@@ -1648,16 +1770,16 @@</div><div class='ctx'> 			clock-names = "aclk", "susp_clk", "phyclk", "pipe_pclk";</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;1&gt;;</div><div class='del'>-			ranges;</div><div class='add'>+			ranges = &lt;0x0 0x15400000 0x10000&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> </div><div class='del'>-			usbdrd_dwc3: dwc3@15400000 {</div><div class='add'>+			usbdrd_dwc3: usb@0 {</div><div class='ctx'> 				compatible = "snps,dwc3";</div><div class='ctx'> 				clocks = &lt;&amp;cmu_fsys CLK_SCLK_USBDRD30&gt;,</div><div class='ctx'> 					&lt;&amp;cmu_fsys CLK_ACLK_USBDRD30&gt;,</div><div class='ctx'> 					&lt;&amp;cmu_fsys CLK_SCLK_USBDRD30&gt;;</div><div class='ctx'> 				clock-names = "ref", "bus_early", "suspend";</div><div class='del'>-				reg = &lt;0x15400000 0x10000&gt;;</div><div class='add'>+				reg = &lt;0x0 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				phys = &lt;&amp;usbdrd30_phy 0&gt;, &lt;&amp;usbdrd30_phy 1&gt;;</div><div class='ctx'> 				phy-names = "usb2-phy", "usb3-phy";</div><div class='hunk'>@@ -1692,7 +1814,7 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		usbhost30: usbhost {</div><div class='add'>+		usbhost30: usb@15a00000 {</div><div class='ctx'> 			compatible = "samsung,exynos5433-dwusb3";</div><div class='ctx'> 			clocks = &lt;&amp;cmu_fsys CLK_ACLK_USBHOST30&gt;,</div><div class='ctx'> 				&lt;&amp;cmu_fsys CLK_SCLK_USBHOST30&gt;,</div><div class='hunk'>@@ -1701,24 +1823,25 @@</div><div class='ctx'> 			clock-names = "aclk", "susp_clk", "phyclk", "pipe_pclk";</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;1&gt;;</div><div class='del'>-			ranges;</div><div class='add'>+			ranges = &lt;0x0 0x15a00000 0x10000&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> </div><div class='del'>-			usbhost_dwc3: dwc3@15a00000 {</div><div class='add'>+			usbhost_dwc3: usb@0 {</div><div class='ctx'> 				compatible = "snps,dwc3";</div><div class='ctx'> 				clocks = &lt;&amp;cmu_fsys CLK_SCLK_USBHOST30&gt;,</div><div class='ctx'> 					&lt;&amp;cmu_fsys CLK_ACLK_USBHOST30&gt;,</div><div class='ctx'> 					&lt;&amp;cmu_fsys CLK_SCLK_USBHOST30&gt;;</div><div class='ctx'> 				clock-names = "ref", "bus_early", "suspend";</div><div class='del'>-				reg = &lt;0x15a00000 0x10000&gt;;</div><div class='add'>+				reg = &lt;0x0 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				phys = &lt;&amp;usbhost30_phy 0&gt;, &lt;&amp;usbhost30_phy 1&gt;;</div><div class='ctx'> 				phy-names = "usb2-phy", "usb3-phy";</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		mshc_0: mshc@15540000 {</div><div class='del'>-			compatible = "samsung,exynos7-dw-mshc-smu";</div><div class='add'>+		mshc_0: mmc@15540000 {</div><div class='add'>+			compatible = "samsung,exynos5433-dw-mshc-smu",</div><div class='add'>+				     "samsung,exynos7-dw-mshc-smu";</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='hunk'>@@ -1730,8 +1853,9 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		mshc_1: mshc@15550000 {</div><div class='del'>-			compatible = "samsung,exynos7-dw-mshc-smu";</div><div class='add'>+		mshc_1: mmc@15550000 {</div><div class='add'>+			compatible = "samsung,exynos5433-dw-mshc-smu",</div><div class='add'>+				     "samsung,exynos7-dw-mshc-smu";</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='hunk'>@@ -1743,8 +1867,9 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		mshc_2: mshc@15560000 {</div><div class='del'>-			compatible = "samsung,exynos7-dw-mshc-smu";</div><div class='add'>+		mshc_2: mmc@15560000 {</div><div class='add'>+			compatible = "samsung,exynos5433-dw-mshc-smu",</div><div class='add'>+				     "samsung,exynos7-dw-mshc-smu";</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='hunk'>@@ -1756,33 +1881,22 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		amba {</div><div class='del'>-			compatible = "simple-bus";</div><div class='del'>-			#address-cells = &lt;1&gt;;</div><div class='del'>-			#size-cells = &lt;1&gt;;</div><div class='del'>-			ranges;</div><div class='del'>-</div><div class='del'>-			pdma0: pdma@15610000 {</div><div class='del'>-				compatible = "arm,pl330", "arm,primecell";</div><div class='del'>-				reg = &lt;0x15610000 0x1000&gt;;</div><div class='del'>-				interrupts = &lt;GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-				clocks = &lt;&amp;cmu_fsys CLK_PDMA0&gt;;</div><div class='del'>-				clock-names = "apb_pclk";</div><div class='del'>-				#dma-cells = &lt;1&gt;;</div><div class='del'>-				#dma-channels = &lt;8&gt;;</div><div class='del'>-				#dma-requests = &lt;32&gt;;</div><div class='del'>-			};</div><div class='add'>+		pdma0: dma-controller@15610000 {</div><div class='add'>+			compatible = "arm,pl330", "arm,primecell";</div><div class='add'>+			reg = &lt;0x15610000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_fsys CLK_PDMA0&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='ctx'> </div><div class='del'>-			pdma1: pdma@15600000 {</div><div class='del'>-				compatible = "arm,pl330", "arm,primecell";</div><div class='del'>-				reg = &lt;0x15600000 0x1000&gt;;</div><div class='del'>-				interrupts = &lt;GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-				clocks = &lt;&amp;cmu_fsys CLK_PDMA1&gt;;</div><div class='del'>-				clock-names = "apb_pclk";</div><div class='del'>-				#dma-cells = &lt;1&gt;;</div><div class='del'>-				#dma-channels = &lt;8&gt;;</div><div class='del'>-				#dma-requests = &lt;32&gt;;</div><div class='del'>-			};</div><div class='add'>+		pdma1: dma-controller@15600000 {</div><div class='add'>+			compatible = "arm,pl330", "arm,primecell";</div><div class='add'>+			reg = &lt;0x15600000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_fsys CLK_PDMA1&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		audio-subsystem@11400000 {</div><div class='hunk'>@@ -1790,26 +1904,24 @@</div><div class='ctx'> 			reg = &lt;0x11400000 0x100&gt;, &lt;0x11500000 0x08&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;cmu_aud CLK_PCLK_SFR0_CTRL&gt;;</div><div class='ctx'> 			clock-names = "sfr0_ctrl";</div><div class='del'>-			samsung,pmu-syscon = &lt;&amp;pmu_system_controller&gt;;</div><div class='ctx'> 			power-domains = &lt;&amp;pd_aud&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;1&gt;;</div><div class='ctx'> 			ranges;</div><div class='ctx'> </div><div class='del'>-			adma: adma@11420000 {</div><div class='add'>+			adma: dma-controller@11420000 {</div><div class='ctx'> 				compatible = "arm,pl330", "arm,primecell";</div><div class='ctx'> 				reg = &lt;0x11420000 0x1000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;cmu_aud CLK_ACLK_DMAC&gt;;</div><div class='ctx'> 				clock-names = "apb_pclk";</div><div class='ctx'> 				#dma-cells = &lt;1&gt;;</div><div class='del'>-				#dma-channels = &lt;8&gt;;</div><div class='del'>-				#dma-requests = &lt;32&gt;;</div><div class='ctx'> 				power-domains = &lt;&amp;pd_aud&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			i2s0: i2s@11440000 {</div><div class='del'>-				compatible = "samsung,exynos7-i2s";</div><div class='add'>+				compatible = "samsung,exynos5433-i2s",</div><div class='add'>+					     "samsung,exynos7-i2s";</div><div class='ctx'> 				reg = &lt;0x11440000 0x100&gt;;</div><div class='ctx'> 				dmas = &lt;&amp;adma 0&gt;, &lt;&amp;adma 2&gt;;</div><div class='ctx'> 				dma-names = "tx", "rx";</div><div class='hunk'>@@ -1841,6 +1953,37 @@</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='add'>+</div><div class='add'>+		pcie_phy: pcie-phy@15680000 {</div><div class='add'>+			compatible = "samsung,exynos5433-pcie-phy";</div><div class='add'>+			reg = &lt;0x15680000 0x1000&gt;;</div><div class='add'>+			samsung,pmu-syscon = &lt;&amp;pmu_system_controller&gt;;</div><div class='add'>+			samsung,fsys-sysreg = &lt;&amp;syscon_fsys&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie: pcie@15700000 {</div><div class='add'>+			compatible = "samsung,exynos5433-pcie";</div><div class='add'>+			reg = &lt;0x15700000 0x1000&gt;, &lt;0x156b0000 0x1000&gt;,</div><div class='add'>+			      &lt;0x0c000000 0x1000&gt;;</div><div class='add'>+			reg-names = "dbi", "elbi", "config";</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			interrupts = &lt;GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_fsys CLK_PCIE&gt;,</div><div class='add'>+				 &lt;&amp;cmu_fsys CLK_PCLK_PCIE_PHY&gt;;</div><div class='add'>+			clock-names = "pcie", "pcie_bus";</div><div class='add'>+			num-lanes = &lt;1&gt;;</div><div class='add'>+			num-viewport = &lt;3&gt;;</div><div class='add'>+			bus-range = &lt;0x00 0xff&gt;;</div><div class='add'>+			phys = &lt;&amp;pcie_phy&gt;;</div><div class='add'>+			ranges = &lt;0x81000000 0 0	  0x0c001000 0 0x00010000&gt;,</div><div class='add'>+				 &lt;0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	timer: timer {</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts<br/>index 7af288fa9475..1f2eddcebdd9 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynos7-espresso.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynos7-espresso.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynos7-espresso.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/exynos7-espresso.dts</a></div><div class='hunk'>@@ -17,9 +17,9 @@</div><div class='ctx'> 	compatible = "samsung,exynos7-espresso", "samsung,exynos7";</div><div class='ctx'> </div><div class='ctx'> 	aliases {</div><div class='add'>+		mmc0 = &amp;mmc_0;</div><div class='add'>+		mmc2 = &amp;mmc_2;</div><div class='ctx'> 		serial0 = &amp;serial_2;</div><div class='del'>-		mshc0 = &amp;mmc_0;</div><div class='del'>-		mshc2 = &amp;mmc_2;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	chosen {</div><div class='hunk'>@@ -28,7 +28,7 @@</div><div class='ctx'> </div><div class='ctx'> 	memory@40000000 {</div><div class='ctx'> 		device_type = "memory";</div><div class='del'>-		reg = &lt;0x0 0x40000000 0x0 0xC0000000&gt;;</div><div class='add'>+		reg = &lt;0x0 0x40000000 0x0 0xc0000000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	usb30_vbus_reg: regulator-usb30 {</div><div class='hunk'>@@ -61,7 +61,6 @@</div><div class='ctx'> </div><div class='ctx'> &amp;gpu {</div><div class='ctx'> 	mali-supply = &lt;&amp;buck6_reg&gt;;</div><div class='del'>-	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;serial_2 {</div><div class='hunk'>@@ -79,18 +78,17 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;adc {</div><div class='add'>+	vdd-supply = &lt;&amp;ldo3_reg&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;hsi2c_4 {</div><div class='del'>-	samsung,i2c-sda-delay = &lt;100&gt;;</div><div class='del'>-	samsung,i2c-max-bus-freq = &lt;200000&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='del'>-	s2mps15_pmic@66 {</div><div class='add'>+	pmic@66 {</div><div class='ctx'> 		compatible = "samsung,s2mps15-pmic";</div><div class='ctx'> 		reg = &lt;0x66&gt;;</div><div class='del'>-		interrupts = &lt;2 IRQ_TYPE_NONE&gt;;</div><div class='add'>+		interrupts = &lt;2 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 		interrupt-parent = &lt;&amp;gpa0&gt;;</div><div class='ctx'> 		pinctrl-names = "default";</div><div class='ctx'> 		pinctrl-0 = &lt;&amp;pmic_irq&gt;;</div><div class='hunk'>@@ -157,6 +155,7 @@</div><div class='ctx'> 				regulator-min-microvolt = &lt;700000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;1150000&gt;;</div><div class='ctx'> 				regulator-enable-ramp-delay = &lt;125&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			ldo8_reg: LDO8 {</div><div class='hunk'>@@ -193,6 +192,7 @@</div><div class='ctx'> 				regulator-min-microvolt = &lt;1000000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='ctx'> 				regulator-enable-ramp-delay = &lt;125&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			ldo13_reg: LDO13 {</div><div class='hunk'>@@ -352,16 +352,17 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;pinctrl_alive {</div><div class='del'>-	pmic_irq: pmic-irq {</div><div class='add'>+	pmic_irq: pmic-irq-pins {</div><div class='ctx'> 		samsung,pins = "gpa0-2";</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='del'>-		samsung,pin-drv = &lt;EXYNOS4_PIN_DRV_LV4&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV4&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;mmc_0 {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> 	cap-mmc-highspeed;</div><div class='add'>+	mmc-ddr-1_8v;</div><div class='ctx'> 	mmc-hs200-1_8v;</div><div class='ctx'> 	non-removable;</div><div class='ctx'> 	card-detect-delay = &lt;200&gt;;</div><div class='hunk'>@@ -391,21 +392,30 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;pinctrl_bus1 {</div><div class='del'>-	usb30_vbus_en: usb30-vbus-en {</div><div class='add'>+	usb30_vbus_en: usb30-vbus-en-pins {</div><div class='ctx'> 		samsung,pins = "gph1-1";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='del'>-		samsung,pin-drv = &lt;EXYNOS4_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	usb3drd_boost_en: usb3drd-boost-en {</div><div class='add'>+	usb3drd_boost_en: usb3drd-boost-en-pins {</div><div class='ctx'> 		samsung,pins = "gpf4-1";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='del'>-		samsung,pin-drv = &lt;EXYNOS4_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;ufs {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbdrd {</div><div class='add'>+	vdd10-supply = &lt;&amp;ldo4_reg&gt;;</div><div class='add'>+	vdd33-supply = &lt;&amp;ldo6_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;usbdrd_phy {</div><div class='ctx'> 	vbus-supply = &lt;&amp;usb30_vbus_reg&gt;;</div><div class='ctx'> 	vbus-boost-supply = &lt;&amp;usb3drd_boost_5v&gt;;</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi<br/>index 472dd649aa7e..ee9c24a226f3 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi</a></div><div class='hunk'>@@ -9,10 +9,10 @@</div><div class='ctx'>  * device tree nodes in this file.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-#include &lt;dt-bindings/pinctrl/samsung.h&gt;</div><div class='add'>+#include "exynos-pinctrl.h"</div><div class='ctx'> </div><div class='ctx'> &amp;pinctrl_alive {</div><div class='del'>-	gpa0: gpa0 {</div><div class='add'>+	gpa0: gpa0-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -29,7 +29,7 @@</div><div class='ctx'> 			     &lt;GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpa1: gpa1 {</div><div class='add'>+	gpa1: gpa1-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -46,7 +46,7 @@</div><div class='ctx'> 			     &lt;GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpa2: gpa2 {</div><div class='add'>+	gpa2: gpa2-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -54,7 +54,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpa3: gpa3 {</div><div class='add'>+	gpa3: gpa3-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -64,7 +64,7 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;pinctrl_bus0 {</div><div class='del'>-	gpb0: gpb0 {</div><div class='add'>+	gpb0: gpb0-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -72,7 +72,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpc0: gpc0 {</div><div class='add'>+	gpc0: gpc0-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -80,7 +80,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpc1: gpc1 {</div><div class='add'>+	gpc1: gpc1-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -88,7 +88,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpc2: gpc2 {</div><div class='add'>+	gpc2: gpc2-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -96,7 +96,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpc3: gpc3 {</div><div class='add'>+	gpc3: gpc3-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -104,7 +104,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpd0: gpd0 {</div><div class='add'>+	gpd0: gpd0-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -112,7 +112,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpd1: gpd1 {</div><div class='add'>+	gpd1: gpd1-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -120,7 +120,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpd2: gpd2 {</div><div class='add'>+	gpd2: gpd2-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -128,7 +128,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpd4: gpd4 {</div><div class='add'>+	gpd4: gpd4-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -136,7 +136,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpd5: gpd5 {</div><div class='add'>+	gpd5: gpd5-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -144,7 +144,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpd6: gpd6 {</div><div class='add'>+	gpd6: gpd6-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -152,7 +152,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpd7: gpd7 {</div><div class='add'>+	gpd7: gpd7-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -160,7 +160,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpd8: gpd8 {</div><div class='add'>+	gpd8: gpd8-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -168,7 +168,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpg0: gpg0 {</div><div class='add'>+	gpg0: gpg0-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -176,7 +176,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpg3: gpg3 {</div><div class='add'>+	gpg3: gpg3-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -184,170 +184,170 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	hs_i2c10_bus: hs-i2c10-bus {</div><div class='add'>+	hs_i2c10_bus: hs-i2c10-bus-pins {</div><div class='ctx'> 		samsung,pins = "gpb0-1", "gpb0-0";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='del'>-		samsung,pin-drv = &lt;EXYNOS4_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	hs_i2c11_bus: hs-i2c11-bus {</div><div class='add'>+	hs_i2c11_bus: hs-i2c11-bus-pins {</div><div class='ctx'> 		samsung,pins = "gpb0-3", "gpb0-2";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='del'>-		samsung,pin-drv = &lt;EXYNOS4_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	hs_i2c2_bus: hs-i2c2-bus {</div><div class='add'>+	hs_i2c2_bus: hs-i2c2-bus-pins {</div><div class='ctx'> 		samsung,pins = "gpd0-3", "gpd0-2";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='del'>-		samsung,pin-drv = &lt;EXYNOS4_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	uart0_data: uart0-data {</div><div class='add'>+	uart0_data: uart0-data-pins {</div><div class='ctx'> 		samsung,pins = "gpd0-0", "gpd0-1";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='del'>-		samsung,pin-drv = &lt;EXYNOS4_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	uart0_fctl: uart0-fctl {</div><div class='add'>+	uart0_fctl: uart0-fctl-pins {</div><div class='ctx'> 		samsung,pins = "gpd0-2", "gpd0-3";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='del'>-		samsung,pin-drv = &lt;EXYNOS4_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	uart2_data: uart2-data {</div><div class='add'>+	uart2_data: uart2-data-pins {</div><div class='ctx'> 		samsung,pins = "gpd1-4", "gpd1-5";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='del'>-		samsung,pin-drv = &lt;EXYNOS4_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	hs_i2c3_bus: hs-i2c3-bus {</div><div class='add'>+	hs_i2c3_bus: hs-i2c3-bus-pins {</div><div class='ctx'> 		samsung,pins = "gpd1-3", "gpd1-2";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='del'>-		samsung,pin-drv = &lt;EXYNOS4_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	uart1_data: uart1-data {</div><div class='add'>+	uart1_data: uart1-data-pins {</div><div class='ctx'> 		samsung,pins = "gpd1-0", "gpd1-1";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='del'>-		samsung,pin-drv = &lt;EXYNOS4_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	uart1_fctl: uart1-fctl {</div><div class='add'>+	uart1_fctl: uart1-fctl-pins {</div><div class='ctx'> 		samsung,pins = "gpd1-2", "gpd1-3";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='del'>-		samsung,pin-drv = &lt;EXYNOS4_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	hs_i2c0_bus: hs-i2c0-bus {</div><div class='add'>+	hs_i2c0_bus: hs-i2c0-bus-pins {</div><div class='ctx'> 		samsung,pins = "gpd2-1", "gpd2-0";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='del'>-		samsung,pin-drv = &lt;EXYNOS4_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	hs_i2c1_bus: hs-i2c1-bus {</div><div class='add'>+	hs_i2c1_bus: hs-i2c1-bus-pins {</div><div class='ctx'> 		samsung,pins = "gpd2-3", "gpd2-2";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='del'>-		samsung,pin-drv = &lt;EXYNOS4_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	hs_i2c9_bus: hs-i2c9-bus {</div><div class='add'>+	hs_i2c9_bus: hs-i2c9-bus-pins {</div><div class='ctx'> 		samsung,pins = "gpd2-7", "gpd2-6";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='del'>-		samsung,pin-drv = &lt;EXYNOS4_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pwm0_out: pwm0-out {</div><div class='add'>+	pwm0_out: pwm0-out-pins {</div><div class='ctx'> 		samsung,pins = "gpd2-4";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='del'>-		samsung,pin-drv = &lt;EXYNOS4_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pwm1_out: pwm1-out {</div><div class='add'>+	pwm1_out: pwm1-out-pins {</div><div class='ctx'> 		samsung,pins = "gpd2-5";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='del'>-		samsung,pin-drv = &lt;EXYNOS4_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pwm2_out: pwm2-out {</div><div class='add'>+	pwm2_out: pwm2-out-pins {</div><div class='ctx'> 		samsung,pins = "gpd2-6";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='del'>-		samsung,pin-drv = &lt;EXYNOS4_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pwm3_out: pwm3-out {</div><div class='add'>+	pwm3_out: pwm3-out-pins {</div><div class='ctx'> 		samsung,pins = "gpd2-7";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='del'>-		samsung,pin-drv = &lt;EXYNOS4_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	hs_i2c8_bus: hs-i2c8-bus {</div><div class='add'>+	hs_i2c8_bus: hs-i2c8-bus-pins {</div><div class='ctx'> 		samsung,pins = "gpd5-3", "gpd5-2";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='del'>-		samsung,pin-drv = &lt;EXYNOS4_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	uart3_data: uart3-data {</div><div class='add'>+	uart3_data: uart3-data-pins {</div><div class='ctx'> 		samsung,pins = "gpd5-0", "gpd5-1";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='del'>-		samsung,pin-drv = &lt;EXYNOS4_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	spi2_bus: spi2-bus {</div><div class='add'>+	spi2_bus: spi2-bus-pins {</div><div class='ctx'> 		samsung,pins = "gpd5-0", "gpd5-1", "gpd5-2", "gpd5-3";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='del'>-		samsung,pin-drv = &lt;EXYNOS4_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	spi1_bus: spi1-bus {</div><div class='add'>+	spi1_bus: spi1-bus-pins {</div><div class='ctx'> 		samsung,pins = "gpd6-2", "gpd6-3", "gpd6-4", "gpd6-5";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='del'>-		samsung,pin-drv = &lt;EXYNOS4_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	spi0_bus: spi0-bus {</div><div class='add'>+	spi0_bus: spi0-bus-pins {</div><div class='ctx'> 		samsung,pins = "gpd8-0", "gpd8-1", "gpd6-0", "gpd6-1";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='del'>-		samsung,pin-drv = &lt;EXYNOS4_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	hs_i2c4_bus: hs-i2c4-bus {</div><div class='add'>+	hs_i2c4_bus: hs-i2c4-bus-pins {</div><div class='ctx'> 		samsung,pins = "gpg3-1", "gpg3-0";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='del'>-		samsung,pin-drv = &lt;EXYNOS4_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	hs_i2c5_bus: hs-i2c5-bus {</div><div class='add'>+	hs_i2c5_bus: hs-i2c5-bus-pins {</div><div class='ctx'> 		samsung,pins = "gpg3-3", "gpg3-2";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='del'>-		samsung,pin-drv = &lt;EXYNOS4_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;pinctrl_nfc {</div><div class='del'>-	gpj0: gpj0 {</div><div class='add'>+	gpj0: gpj0-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -355,16 +355,16 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	hs_i2c6_bus: hs-i2c6-bus {</div><div class='add'>+	hs_i2c6_bus: hs-i2c6-bus-pins {</div><div class='ctx'> 		samsung,pins = "gpj0-1", "gpj0-0";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='del'>-		samsung,pin-drv = &lt;EXYNOS4_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;pinctrl_touch {</div><div class='del'>-	gpj1: gpj1 {</div><div class='add'>+	gpj1: gpj1-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -372,16 +372,16 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	hs_i2c7_bus: hs-i2c7-bus {</div><div class='add'>+	hs_i2c7_bus: hs-i2c7-bus-pins {</div><div class='ctx'> 		samsung,pins = "gpj1-1", "gpj1-0";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='del'>-		samsung,pin-drv = &lt;EXYNOS4_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;pinctrl_ff {</div><div class='del'>-	gpg4: gpg4 {</div><div class='add'>+	gpg4: gpg4-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -389,16 +389,16 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	spi3_bus: spi3-bus {</div><div class='add'>+	spi3_bus: spi3-bus-pins {</div><div class='ctx'> 		samsung,pins = "gpg4-0", "gpg4-1", "gpg4-2", "gpg4-3";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='del'>-		samsung,pin-drv = &lt;EXYNOS4_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;pinctrl_ese {</div><div class='del'>-	gpv7: gpv7 {</div><div class='add'>+	gpv7: gpv7-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -406,16 +406,16 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	spi4_bus: spi4-bus {</div><div class='add'>+	spi4_bus: spi4-bus-pins {</div><div class='ctx'> 		samsung,pins = "gpv7-0", "gpv7-1", "gpv7-2", "gpv7-3";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='del'>-		samsung,pin-drv = &lt;EXYNOS4_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;pinctrl_fsys0 {</div><div class='del'>-	gpr4: gpr4 {</div><div class='add'>+	gpr4: gpr4-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -423,44 +423,44 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sd2_clk: sd2-clk {</div><div class='add'>+	sd2_clk: sd2-clk-pins {</div><div class='ctx'> 		samsung,pins = "gpr4-0";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='del'>-		samsung,pin-drv = &lt;EXYNOS4_PIN_DRV_LV4&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV4&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sd2_cmd: sd2-cmd {</div><div class='add'>+	sd2_cmd: sd2-cmd-pins {</div><div class='ctx'> 		samsung,pins = "gpr4-1";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='del'>-		samsung,pin-drv = &lt;EXYNOS4_PIN_DRV_LV4&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV4&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sd2_cd: sd2-cd {</div><div class='add'>+	sd2_cd: sd2-cd-pins {</div><div class='ctx'> 		samsung,pins = "gpr4-2";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='del'>-		samsung,pin-drv = &lt;EXYNOS4_PIN_DRV_LV4&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV4&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sd2_bus1: sd2-bus-width1 {</div><div class='add'>+	sd2_bus1: sd2-bus-width1-pins {</div><div class='ctx'> 		samsung,pins = "gpr4-3";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='del'>-		samsung,pin-drv = &lt;EXYNOS4_PIN_DRV_LV4&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV4&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sd2_bus4: sd2-bus-width4 {</div><div class='add'>+	sd2_bus4: sd2-bus-width4-pins {</div><div class='ctx'> 		samsung,pins = "gpr4-4", "gpr4-5", "gpr4-6";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='del'>-		samsung,pin-drv = &lt;EXYNOS4_PIN_DRV_LV4&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV4&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;pinctrl_fsys1 {</div><div class='del'>-	gpr0: gpr0 {</div><div class='add'>+	gpr0: gpr0-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -468,7 +468,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpr1: gpr1 {</div><div class='add'>+	gpr1: gpr1-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -476,7 +476,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpr2: gpr2 {</div><div class='add'>+	gpr2: gpr2-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -484,7 +484,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpr3: gpr3 {</div><div class='add'>+	gpr3: gpr3-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -492,105 +492,105 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sd0_clk: sd0-clk {</div><div class='add'>+	sd0_clk: sd0-clk-pins {</div><div class='ctx'> 		samsung,pins = "gpr0-0";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS7_FSYS1_PIN_DRV_LV2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sd0_cmd: sd0-cmd {</div><div class='add'>+	sd0_cmd: sd0-cmd-pins {</div><div class='ctx'> 		samsung,pins = "gpr0-1";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS7_FSYS1_PIN_DRV_LV2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sd0_ds: sd0-ds {</div><div class='add'>+	sd0_ds: sd0-ds-pins {</div><div class='ctx'> 		samsung,pins = "gpr0-2";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS7_FSYS1_PIN_DRV_LV2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sd0_qrdy: sd0-qrdy {</div><div class='add'>+	sd0_qrdy: sd0-qrdy-pins {</div><div class='ctx'> 		samsung,pins = "gpr0-3";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS7_FSYS1_PIN_DRV_LV2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sd0_bus1: sd0-bus-width1 {</div><div class='add'>+	sd0_bus1: sd0-bus-width1-pins {</div><div class='ctx'> 		samsung,pins = "gpr1-0";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS7_FSYS1_PIN_DRV_LV2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sd0_bus4: sd0-bus-width4 {</div><div class='add'>+	sd0_bus4: sd0-bus-width4-pins {</div><div class='ctx'> 		samsung,pins = "gpr1-1", "gpr1-2", "gpr1-3";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS7_FSYS1_PIN_DRV_LV2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sd0_bus8: sd0-bus-width8 {</div><div class='add'>+	sd0_bus8: sd0-bus-width8-pins {</div><div class='ctx'> 		samsung,pins = "gpr1-4", "gpr1-5", "gpr1-6", "gpr1-7";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS7_FSYS1_PIN_DRV_LV2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sd1_clk: sd1-clk {</div><div class='add'>+	sd1_clk: sd1-clk-pins {</div><div class='ctx'> 		samsung,pins = "gpr2-0";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS7_FSYS1_PIN_DRV_LV3&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sd1_cmd: sd1-cmd {</div><div class='add'>+	sd1_cmd: sd1-cmd-pins {</div><div class='ctx'> 		samsung,pins = "gpr2-1";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS7_FSYS1_PIN_DRV_LV3&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sd1_ds: sd1-ds {</div><div class='add'>+	sd1_ds: sd1-ds-pins {</div><div class='ctx'> 		samsung,pins = "gpr2-2";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS7_FSYS1_PIN_DRV_LV4&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sd1_qrdy: sd1-qrdy {</div><div class='add'>+	sd1_qrdy: sd1-qrdy-pins {</div><div class='ctx'> 		samsung,pins = "gpr2-3";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS7_FSYS1_PIN_DRV_LV4&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sd1_int: sd1-int {</div><div class='add'>+	sd1_int: sd1-int-pins {</div><div class='ctx'> 		samsung,pins = "gpr2-4";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS7_FSYS1_PIN_DRV_LV4&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sd1_bus1: sd1-bus-width1 {</div><div class='add'>+	sd1_bus1: sd1-bus-width1-pins {</div><div class='ctx'> 		samsung,pins = "gpr3-0";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS7_FSYS1_PIN_DRV_LV3&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sd1_bus4: sd1-bus-width4 {</div><div class='add'>+	sd1_bus4: sd1-bus-width4-pins {</div><div class='ctx'> 		samsung,pins = "gpr3-1", "gpr3-2", "gpr3-3";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='ctx'> 		samsung,pin-drv = &lt;EXYNOS7_FSYS1_PIN_DRV_LV3&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sd1_bus8: sd1-bus-width8 {</div><div class='add'>+	sd1_bus8: sd1-bus-width8-pins {</div><div class='ctx'> 		samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='hunk'>@@ -599,7 +599,7 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;pinctrl_bus1 {</div><div class='del'>-	gpf0: gpf0 {</div><div class='add'>+	gpf0: gpf0-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -607,7 +607,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpf1: gpf1 {</div><div class='add'>+	gpf1: gpf1-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -615,7 +615,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpf2: gpf2 {</div><div class='add'>+	gpf2: gpf2-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -623,7 +623,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpf3: gpf3 {</div><div class='add'>+	gpf3: gpf3-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -631,7 +631,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpf4: gpf4 {</div><div class='add'>+	gpf4: gpf4-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -639,7 +639,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpf5: gpf5 {</div><div class='add'>+	gpf5: gpf5-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -647,7 +647,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpg1: gpg1 {</div><div class='add'>+	gpg1: gpg1-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -655,7 +655,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpg2: gpg2 {</div><div class='add'>+	gpg2: gpg2-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -663,7 +663,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gph1: gph1 {</div><div class='add'>+	gph1: gph1-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -671,7 +671,7 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpv6: gpv6 {</div><div class='add'>+	gpv6: gpv6-gpio-bank {</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -679,24 +679,24 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	spi5_bus: spi5-bus {</div><div class='add'>+	spi5_bus: spi5-bus-pins {</div><div class='ctx'> 		samsung,pins = "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='del'>-		samsung,pin-drv = &lt;EXYNOS4_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	ufs_refclk_out: ufs-refclk-out {</div><div class='add'>+	ufs_refclk_out: ufs-refclk-out-pins {</div><div class='ctx'> 		samsung,pins = "gpg2-4";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='del'>-		samsung,pin-drv = &lt;EXYNOS4_PIN_DRV_LV2&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	ufs_rst_n: ufs-rst-n {</div><div class='add'>+	ufs_rst_n: ufs-rst-n-pins {</div><div class='ctx'> 		samsung,pins = "gph1-5";</div><div class='ctx'> 		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='ctx'> 		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='del'>-		samsung,pin-drv = &lt;EXYNOS4_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi<br/>index 5558045637ac..9cb6bd61262e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynos7.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/exynos/exynos7.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynos7.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/exynos7.dtsi</a></div><div class='hunk'>@@ -25,11 +25,10 @@</div><div class='ctx'> 		pinctrl6 = &amp;pinctrl_fsys0;</div><div class='ctx'> 		pinctrl7 = &amp;pinctrl_fsys1;</div><div class='ctx'> 		pinctrl8 = &amp;pinctrl_bus1;</div><div class='del'>-		tmuctrl0 = &amp;tmuctrl_0;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	arm-pmu {</div><div class='del'>-		compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3";</div><div class='add'>+		compatible = "arm,cortex-a57-pmu";</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 			     &lt;GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 			     &lt;GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='hunk'>@@ -54,6 +53,13 @@</div><div class='ctx'> 			compatible = "arm,cortex-a57";</div><div class='ctx'> 			reg = &lt;0x0&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			i-cache-size = &lt;0xc000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;atlas_l2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu_atlas1: cpu@1 {</div><div class='hunk'>@@ -61,6 +67,13 @@</div><div class='ctx'> 			compatible = "arm,cortex-a57";</div><div class='ctx'> 			reg = &lt;0x1&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			i-cache-size = &lt;0xc000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;atlas_l2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu_atlas2: cpu@2 {</div><div class='hunk'>@@ -68,6 +81,13 @@</div><div class='ctx'> 			compatible = "arm,cortex-a57";</div><div class='ctx'> 			reg = &lt;0x2&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			i-cache-size = &lt;0xc000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;atlas_l2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu_atlas3: cpu@3 {</div><div class='hunk'>@@ -75,22 +95,41 @@</div><div class='ctx'> 			compatible = "arm,cortex-a57";</div><div class='ctx'> 			reg = &lt;0x3&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			i-cache-size = &lt;0xc000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;atlas_l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		atlas_l2: l2-cache0 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x200000&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;2048&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	psci {</div><div class='del'>-		compatible = "arm,psci-0.2";</div><div class='add'>+		compatible = "arm,psci";</div><div class='ctx'> 		method = "smc";</div><div class='add'>+		cpu_off = &lt;0x84000002&gt;;</div><div class='add'>+		cpu_on = &lt;0xc4000003&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	soc: soc {</div><div class='add'>+	soc: soc@0 {</div><div class='ctx'> 		compatible = "simple-bus";</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;1&gt;;</div><div class='ctx'> 		ranges = &lt;0 0 0 0x18000000&gt;;</div><div class='ctx'> </div><div class='ctx'> 		chipid@10000000 {</div><div class='del'>-			compatible = "samsung,exynos4210-chipid";</div><div class='add'>+			compatible = "samsung,exynos7-chipid",</div><div class='add'>+				     "samsung,exynos4210-chipid";</div><div class='ctx'> 			reg = &lt;0x10000000 0x100&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -99,39 +138,28 @@</div><div class='ctx'> 			#interrupt-cells = &lt;3&gt;;</div><div class='ctx'> 			#address-cells = &lt;0&gt;;</div><div class='ctx'> 			interrupt-controller;</div><div class='del'>-			reg =	&lt;0x11001000 0x1000&gt;,</div><div class='del'>-				&lt;0x11002000 0x1000&gt;,</div><div class='del'>-				&lt;0x11004000 0x2000&gt;,</div><div class='del'>-				&lt;0x11006000 0x2000&gt;;</div><div class='add'>+			reg = &lt;0x11001000 0x1000&gt;,</div><div class='add'>+			      &lt;0x11002000 0x2000&gt;,</div><div class='add'>+			      &lt;0x11004000 0x2000&gt;,</div><div class='add'>+			      &lt;0x11006000 0x2000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		amba {</div><div class='del'>-			compatible = "simple-bus";</div><div class='del'>-			#address-cells = &lt;1&gt;;</div><div class='del'>-			#size-cells = &lt;1&gt;;</div><div class='del'>-			ranges;</div><div class='del'>-</div><div class='del'>-			pdma0: pdma@10e10000 {</div><div class='del'>-				compatible = "arm,pl330", "arm,primecell";</div><div class='del'>-				reg = &lt;0x10E10000 0x1000&gt;;</div><div class='del'>-				interrupts = &lt;GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-				clocks = &lt;&amp;clock_fsys0 ACLK_PDMA0&gt;;</div><div class='del'>-				clock-names = "apb_pclk";</div><div class='del'>-				#dma-cells = &lt;1&gt;;</div><div class='del'>-				#dma-channels = &lt;8&gt;;</div><div class='del'>-				#dma-requests = &lt;32&gt;;</div><div class='del'>-			};</div><div class='add'>+		pdma0: dma-controller@10e10000 {</div><div class='add'>+			compatible = "arm,pl330", "arm,primecell";</div><div class='add'>+			reg = &lt;0x10e10000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clock_fsys0 ACLK_PDMA0&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='ctx'> </div><div class='del'>-			pdma1: pdma@10eb0000 {</div><div class='del'>-				compatible = "arm,pl330", "arm,primecell";</div><div class='del'>-				reg = &lt;0x10EB0000 0x1000&gt;;</div><div class='del'>-				interrupts = &lt;GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-				clocks = &lt;&amp;clock_fsys0 ACLK_PDMA1&gt;;</div><div class='del'>-				clock-names = "apb_pclk";</div><div class='del'>-				#dma-cells = &lt;1&gt;;</div><div class='del'>-				#dma-channels = &lt;8&gt;;</div><div class='del'>-				#dma-requests = &lt;32&gt;;</div><div class='del'>-			};</div><div class='add'>+		pdma1: dma-controller@10eb0000 {</div><div class='add'>+			compatible = "arm,pl330", "arm,primecell";</div><div class='add'>+			reg = &lt;0x10eb0000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clock_fsys0 ACLK_PDMA1&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		clock_topc: clock-controller@10570000 {</div><div class='hunk'>@@ -147,10 +175,11 @@</div><div class='ctx'> 			clocks = &lt;&amp;fin_pll&gt;, &lt;&amp;clock_topc DOUT_SCLK_BUS0_PLL&gt;,</div><div class='ctx'> 				 &lt;&amp;clock_topc DOUT_SCLK_BUS1_PLL&gt;,</div><div class='ctx'> 				 &lt;&amp;clock_topc DOUT_SCLK_CC_PLL&gt;,</div><div class='del'>-				 &lt;&amp;clock_topc DOUT_SCLK_MFC_PLL&gt;;</div><div class='add'>+				 &lt;&amp;clock_topc DOUT_SCLK_MFC_PLL&gt;,</div><div class='add'>+				 &lt;&amp;clock_topc DOUT_SCLK_AUD_PLL&gt;;</div><div class='ctx'> 			clock-names = "fin_pll", "dout_sclk_bus0_pll",</div><div class='ctx'> 				      "dout_sclk_bus1_pll", "dout_sclk_cc_pll",</div><div class='del'>-				      "dout_sclk_mfc_pll";</div><div class='add'>+				      "dout_sclk_mfc_pll", "dout_sclk_aud_pll";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		clock_top1: clock-controller@105e0000 {</div><div class='hunk'>@@ -188,12 +217,32 @@</div><div class='ctx'> 			compatible = "samsung,exynos7-clock-peric1";</div><div class='ctx'> 			reg = &lt;0x14c80000 0xd00&gt;;</div><div class='ctx'> 			#clock-cells = &lt;1&gt;;</div><div class='del'>-			clocks = &lt;&amp;fin_pll&gt;, &lt;&amp;clock_top0 DOUT_ACLK_PERIC1&gt;,</div><div class='add'>+			clocks = &lt;&amp;fin_pll&gt;,</div><div class='add'>+				 &lt;&amp;clock_top0 DOUT_ACLK_PERIC1&gt;,</div><div class='ctx'> 				 &lt;&amp;clock_top0 CLK_SCLK_UART1&gt;,</div><div class='ctx'> 				 &lt;&amp;clock_top0 CLK_SCLK_UART2&gt;,</div><div class='del'>-				 &lt;&amp;clock_top0 CLK_SCLK_UART3&gt;;</div><div class='del'>-			clock-names = "fin_pll", "dout_aclk_peric1_66",</div><div class='del'>-				      "sclk_uart1", "sclk_uart2", "sclk_uart3";</div><div class='add'>+				 &lt;&amp;clock_top0 CLK_SCLK_UART3&gt;,</div><div class='add'>+				 &lt;&amp;clock_top0 CLK_SCLK_SPI0&gt;,</div><div class='add'>+				 &lt;&amp;clock_top0 CLK_SCLK_SPI1&gt;,</div><div class='add'>+				 &lt;&amp;clock_top0 CLK_SCLK_SPI2&gt;,</div><div class='add'>+				 &lt;&amp;clock_top0 CLK_SCLK_SPI3&gt;,</div><div class='add'>+				 &lt;&amp;clock_top0 CLK_SCLK_SPI4&gt;,</div><div class='add'>+				 &lt;&amp;clock_top0 CLK_SCLK_I2S1&gt;,</div><div class='add'>+				 &lt;&amp;clock_top0 CLK_SCLK_PCM1&gt;,</div><div class='add'>+				 &lt;&amp;clock_top0 CLK_SCLK_SPDIF&gt;;</div><div class='add'>+			clock-names = "fin_pll",</div><div class='add'>+				      "dout_aclk_peric1_66",</div><div class='add'>+				      "sclk_uart1",</div><div class='add'>+				      "sclk_uart2",</div><div class='add'>+				      "sclk_uart3",</div><div class='add'>+				      "sclk_spi0",</div><div class='add'>+				      "sclk_spi1",</div><div class='add'>+				      "sclk_spi2",</div><div class='add'>+				      "sclk_spi3",</div><div class='add'>+				      "sclk_spi4",</div><div class='add'>+				      "sclk_i2s1",</div><div class='add'>+				      "sclk_pcm1",</div><div class='add'>+				      "sclk_spdif";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		clock_peris: clock-controller@10040000 {</div><div class='hunk'>@@ -220,13 +269,18 @@</div><div class='ctx'> 			#clock-cells = &lt;1&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;fin_pll&gt;, &lt;&amp;clock_top1 DOUT_ACLK_FSYS1_200&gt;,</div><div class='ctx'> 				 &lt;&amp;clock_top1 DOUT_SCLK_MMC0&gt;,</div><div class='del'>-				 &lt;&amp;clock_top1 DOUT_SCLK_MMC1&gt;;</div><div class='add'>+				 &lt;&amp;clock_top1 DOUT_SCLK_MMC1&gt;,</div><div class='add'>+				 &lt;&amp;clock_top1 DOUT_SCLK_UFSUNIPRO20&gt;,</div><div class='add'>+				 &lt;&amp;clock_top1 DOUT_SCLK_PHY_FSYS1&gt;,</div><div class='add'>+				 &lt;&amp;clock_top1 DOUT_SCLK_PHY_FSYS1_26M&gt;;</div><div class='ctx'> 			clock-names = "fin_pll", "dout_aclk_fsys1_200",</div><div class='del'>-				      "dout_sclk_mmc0", "dout_sclk_mmc1";</div><div class='add'>+				      "dout_sclk_mmc0", "dout_sclk_mmc1",</div><div class='add'>+				      "dout_sclk_ufsunipro20", "dout_sclk_phy_fsys1",</div><div class='add'>+				      "dout_sclk_phy_fsys1_26m";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		serial_0: serial@13630000 {</div><div class='del'>-			compatible = "samsung,exynos4210-uart";</div><div class='add'>+			compatible = "samsung,exynos7-uart", "samsung,exynos4210-uart";</div><div class='ctx'> 			reg = &lt;0x13630000 0x100&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;clock_peric0 PCLK_UART0&gt;,</div><div class='hunk'>@@ -236,7 +290,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		serial_1: serial@14c20000 {</div><div class='del'>-			compatible = "samsung,exynos4210-uart";</div><div class='add'>+			compatible = "samsung,exynos7-uart", "samsung,exynos4210-uart";</div><div class='ctx'> 			reg = &lt;0x14c20000 0x100&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;clock_peric1 PCLK_UART1&gt;,</div><div class='hunk'>@@ -246,7 +300,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		serial_2: serial@14c30000 {</div><div class='del'>-			compatible = "samsung,exynos4210-uart";</div><div class='add'>+			compatible = "samsung,exynos7-uart", "samsung,exynos4210-uart";</div><div class='ctx'> 			reg = &lt;0x14c30000 0x100&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;clock_peric1 PCLK_UART2&gt;,</div><div class='hunk'>@@ -256,7 +310,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		serial_3: serial@14c40000 {</div><div class='del'>-			compatible = "samsung,exynos4210-uart";</div><div class='add'>+			compatible = "samsung,exynos7-uart", "samsung,exynos4210-uart";</div><div class='ctx'> 			reg = &lt;0x14c40000 0x100&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;clock_peric1 PCLK_UART3&gt;,</div><div class='hunk'>@@ -324,7 +378,7 @@</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		hsi2c_0: hsi2c@13640000 {</div><div class='add'>+		hsi2c_0: i2c@13640000 {</div><div class='ctx'> 			compatible = "samsung,exynos7-hsi2c";</div><div class='ctx'> 			reg = &lt;0x13640000 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='hunk'>@@ -337,7 +391,7 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		hsi2c_1: hsi2c@13650000 {</div><div class='add'>+		hsi2c_1: i2c@13650000 {</div><div class='ctx'> 			compatible = "samsung,exynos7-hsi2c";</div><div class='ctx'> 			reg = &lt;0x13650000 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='hunk'>@@ -350,7 +404,7 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		hsi2c_2: hsi2c@14e60000 {</div><div class='add'>+		hsi2c_2: i2c@14e60000 {</div><div class='ctx'> 			compatible = "samsung,exynos7-hsi2c";</div><div class='ctx'> 			reg = &lt;0x14e60000 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='hunk'>@@ -363,7 +417,7 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		hsi2c_3: hsi2c@14e70000 {</div><div class='add'>+		hsi2c_3: i2c@14e70000 {</div><div class='ctx'> 			compatible = "samsung,exynos7-hsi2c";</div><div class='ctx'> 			reg = &lt;0x14e70000 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='hunk'>@@ -376,7 +430,7 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		hsi2c_4: hsi2c@13660000 {</div><div class='add'>+		hsi2c_4: i2c@13660000 {</div><div class='ctx'> 			compatible = "samsung,exynos7-hsi2c";</div><div class='ctx'> 			reg = &lt;0x13660000 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='hunk'>@@ -389,7 +443,7 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		hsi2c_5: hsi2c@13670000 {</div><div class='add'>+		hsi2c_5: i2c@13670000 {</div><div class='ctx'> 			compatible = "samsung,exynos7-hsi2c";</div><div class='ctx'> 			reg = &lt;0x13670000 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='hunk'>@@ -402,7 +456,7 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		hsi2c_6: hsi2c@14e00000 {</div><div class='add'>+		hsi2c_6: i2c@14e00000 {</div><div class='ctx'> 			compatible = "samsung,exynos7-hsi2c";</div><div class='ctx'> 			reg = &lt;0x14e00000 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='hunk'>@@ -415,7 +469,7 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		hsi2c_7: hsi2c@13e10000 {</div><div class='add'>+		hsi2c_7: i2c@13e10000 {</div><div class='ctx'> 			compatible = "samsung,exynos7-hsi2c";</div><div class='ctx'> 			reg = &lt;0x13e10000 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='hunk'>@@ -428,7 +482,7 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		hsi2c_8: hsi2c@14e20000 {</div><div class='add'>+		hsi2c_8: i2c@14e20000 {</div><div class='ctx'> 			compatible = "samsung,exynos7-hsi2c";</div><div class='ctx'> 			reg = &lt;0x14e20000 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='hunk'>@@ -441,7 +495,7 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		hsi2c_9: hsi2c@13680000 {</div><div class='add'>+		hsi2c_9: i2c@13680000 {</div><div class='ctx'> 			compatible = "samsung,exynos7-hsi2c";</div><div class='ctx'> 			reg = &lt;0x13680000 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='hunk'>@@ -454,7 +508,7 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		hsi2c_10: hsi2c@13690000 {</div><div class='add'>+		hsi2c_10: i2c@13690000 {</div><div class='ctx'> 			compatible = "samsung,exynos7-hsi2c";</div><div class='ctx'> 			reg = &lt;0x13690000 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='hunk'>@@ -467,7 +521,7 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		hsi2c_11: hsi2c@136a0000 {</div><div class='add'>+		hsi2c_11: i2c@136a0000 {</div><div class='ctx'> 			compatible = "samsung,exynos7-hsi2c";</div><div class='ctx'> 			reg = &lt;0x136a0000 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='hunk'>@@ -483,17 +537,10 @@</div><div class='ctx'> 		pmu_system_controller: system-controller@105c0000 {</div><div class='ctx'> 			compatible = "samsung,exynos7-pmu", "syscon";</div><div class='ctx'> 			reg = &lt;0x105c0000 0x5000&gt;;</div><div class='del'>-</div><div class='del'>-			reboot: syscon-reboot {</div><div class='del'>-				compatible = "syscon-reboot";</div><div class='del'>-				regmap = &lt;&amp;pmu_system_controller&gt;;</div><div class='del'>-				offset = &lt;0x0400&gt;;</div><div class='del'>-				mask = &lt;0x1&gt;;</div><div class='del'>-			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		rtc: rtc@10590000 {</div><div class='del'>-			compatible = "samsung,s3c6410-rtc";</div><div class='add'>+			compatible = "samsung,exynos7-rtc", "samsung,s3c6410-rtc";</div><div class='ctx'> 			reg = &lt;0x10590000 0x100&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 				     &lt;GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='hunk'>@@ -513,7 +560,8 @@</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		gpu: gpu@14ac0000 {</div><div class='del'>-			compatible = "samsung,exynos5433-mali", "arm,mali-t760";</div><div class='add'>+			compatible = "samsung,exynos7-mali",</div><div class='add'>+				     "samsung,exynos5433-mali", "arm,mali-t760";</div><div class='ctx'> 			reg = &lt;0x14ac0000 0x5000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 				     &lt;GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='hunk'>@@ -569,13 +617,17 @@</div><div class='ctx'> 			clocks = &lt;&amp;clock_peric0 PCLK_ADCIF&gt;;</div><div class='ctx'> 			clock-names = "adc";</div><div class='ctx'> 			#io-channel-cells = &lt;1&gt;;</div><div class='del'>-			io-channel-ranges;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		pwm: pwm@136c0000 {</div><div class='del'>-			compatible = "samsung,exynos4210-pwm";</div><div class='add'>+			compatible = "samsung,exynos7-pwm", "samsung,exynos4210-pwm";</div><div class='ctx'> 			reg = &lt;0x136c0000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			samsung,pwm-outputs = &lt;0&gt;, &lt;1&gt;, &lt;2&gt;, &lt;3&gt;;</div><div class='ctx'> 			#pwm-cells = &lt;3&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;clock_peric0 PCLK_PWM&gt;;</div><div class='hunk'>@@ -592,13 +644,38 @@</div><div class='ctx'> 			#thermal-sensor-cells = &lt;0&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		thermal-zones {</div><div class='del'>-			atlas_thermal: cluster0-thermal {</div><div class='del'>-				polling-delay-passive = &lt;0&gt;; /* milliseconds */</div><div class='del'>-				polling-delay = &lt;0&gt;; /* milliseconds */</div><div class='del'>-				thermal-sensors = &lt;&amp;tmuctrl_0&gt;;</div><div class='del'>-				#include "exynos7-trip-points.dtsi"</div><div class='del'>-			};</div><div class='add'>+		ufs: ufs@15570000 {</div><div class='add'>+			compatible = "samsung,exynos7-ufs";</div><div class='add'>+			reg = &lt;0x15570000 0x100&gt;,  /* 0: HCI standard */</div><div class='add'>+				&lt;0x15570100 0x100&gt;,  /* 1: Vendor specificed */</div><div class='add'>+				&lt;0x15571000 0x200&gt;,  /* 2: UNIPRO */</div><div class='add'>+				&lt;0x15572000 0x300&gt;;  /* 3: UFS protector */</div><div class='add'>+			reg-names = "hci", "vs_hci", "unipro", "ufsp";</div><div class='add'>+			interrupts = &lt;GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clock_fsys1 ACLK_UFS20_LINK&gt;,</div><div class='add'>+				&lt;&amp;clock_fsys1 SCLK_UFSUNIPRO20_USER&gt;;</div><div class='add'>+			clock-names = "core_clk", "sclk_unipro_main";</div><div class='add'>+			freq-table-hz = &lt;0 0&gt;, &lt;0 0&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;ufs_rst_n &amp;ufs_refclk_out&gt;;</div><div class='add'>+			phys = &lt;&amp;ufs_phy&gt;;</div><div class='add'>+			phy-names = "ufs-phy";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ufs_phy: ufs-phy@15571800 {</div><div class='add'>+			compatible = "samsung,exynos7-ufs-phy";</div><div class='add'>+			reg = &lt;0x15571800 0x240&gt;;</div><div class='add'>+			reg-names = "phy-pma";</div><div class='add'>+			samsung,pmu-syscon = &lt;&amp;pmu_system_controller&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clock_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M&gt;,</div><div class='add'>+				 &lt;&amp;clock_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER&gt;,</div><div class='add'>+				 &lt;&amp;clock_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER&gt;,</div><div class='add'>+				 &lt;&amp;clock_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER&gt;;</div><div class='add'>+			clock-names = "ref_clk", "rx1_symbol_clk",</div><div class='add'>+				      "rx0_symbol_clk",</div><div class='add'>+				      "tx0_symbol_clk";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		usbdrd_phy: phy@15500000 {</div><div class='hunk'>@@ -606,16 +683,15 @@</div><div class='ctx'> 			reg = &lt;0x15500000 0x100&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;clock_fsys0 ACLK_USBDRD300&gt;,</div><div class='ctx'> 			       &lt;&amp;clock_fsys0 OSCCLK_PHY_CLKOUT_USB30_PHY&gt;,</div><div class='del'>-			       &lt;&amp;clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER&gt;,</div><div class='ctx'> 			       &lt;&amp;clock_fsys0 PHYCLK_USBDRD300_UDRD30_PHYCLK_USER&gt;,</div><div class='add'>+			       &lt;&amp;clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER&gt;,</div><div class='ctx'> 			       &lt;&amp;clock_fsys0 SCLK_USBDRD300_REFCLK&gt;;</div><div class='del'>-			clock-names = "phy", "ref", "phy_pipe",</div><div class='del'>-				"phy_utmi", "itp";</div><div class='add'>+			clock-names = "phy", "ref", "phy_utmi", "phy_pipe", "itp";</div><div class='ctx'> 			samsung,pmu-syscon = &lt;&amp;pmu_system_controller&gt;;</div><div class='ctx'> 			#phy-cells = &lt;1&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		usbdrd3 {</div><div class='add'>+		usbdrd: usb@15400000 {</div><div class='ctx'> 			compatible = "samsung,exynos7-dwusb3";</div><div class='ctx'> 			clocks = &lt;&amp;clock_fsys0 ACLK_USBDRD300&gt;,</div><div class='ctx'> 			       &lt;&amp;clock_fsys0 SCLK_USBDRD300_SUSPENDCLK&gt;,</div><div class='hunk'>@@ -624,11 +700,11 @@</div><div class='ctx'> 				"usbdrd30_axius_clk";</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;1&gt;;</div><div class='del'>-			ranges;</div><div class='add'>+			ranges = &lt;0x0 0x15400000 0x10000&gt;;</div><div class='ctx'> </div><div class='del'>-			dwc3@15400000 {</div><div class='add'>+			usb@0 {</div><div class='ctx'> 				compatible = "snps,dwc3";</div><div class='del'>-				reg = &lt;0x15400000 0x10000&gt;;</div><div class='add'>+				reg = &lt;0x0 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				phys = &lt;&amp;usbdrd_phy 0&gt;, &lt;&amp;usbdrd_phy 1&gt;;</div><div class='ctx'> 				phy-names = "usb2-phy", "usb3-phy";</div><div class='hunk'>@@ -636,6 +712,15 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	thermal-zones {</div><div class='add'>+		atlas_thermal: cluster0-thermal {</div><div class='add'>+			polling-delay-passive = &lt;0&gt;; /* milliseconds */</div><div class='add'>+			polling-delay = &lt;0&gt;; /* milliseconds */</div><div class='add'>+			thermal-sensors = &lt;&amp;tmuctrl_0&gt;;</div><div class='add'>+			#include "exynos7-trip-points.dtsi"</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	timer {</div><div class='ctx'> 		compatible = "arm,armv8-timer";</div><div class='ctx'> 		interrupts = &lt;GIC_PPI 13</div><div class='hunk'>@@ -650,3 +735,4 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #include "exynos7-pinctrl.dtsi"</div><div class='add'>+#include "arm/samsung/exynos-syscon-restart.dtsi"</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/exynos7870-a2corelte.dts b/arch/arm64/boot/dts/exynos/exynos7870-a2corelte.dts<br/>new file mode 100644<br/>index 000000000000..6f40ca4350ed<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynos7870-a2corelte.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/exynos7870-a2corelte.dts</a></div><div class='hunk'>@@ -0,0 +1,660 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Samsung Galaxy A2 Core (a2corelte) device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2018 Samsung Electronics Co., Ltd.</div><div class='add'>+ * Copyright (c) 2025 Kaustabh Chakraborty &lt;kauschluss@disroot.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "exynos7870.dtsi"</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Samsung Galaxy A2 Core";</div><div class='add'>+	compatible = "samsung,a2corelte", "samsung,exynos7870";</div><div class='add'>+	chassis-type = "handset";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		mmc0 = &amp;mmc0;</div><div class='add'>+		mmc1 = &amp;mmc1;</div><div class='add'>+		mmc2 = &amp;mmc2;</div><div class='add'>+		serial0 = &amp;serial0;</div><div class='add'>+		serial1 = &amp;serial1;</div><div class='add'>+		serial2 = &amp;serial2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;serial2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		label = "GPIO Keys";</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;key_power &amp;key_voldown &amp;key_volup&gt;;</div><div class='add'>+</div><div class='add'>+		key-power {</div><div class='add'>+			label = "Power Key";</div><div class='add'>+			gpios = &lt;&amp;gpa0 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-voldown {</div><div class='add'>+			label = "Volume Down Key";</div><div class='add'>+			gpios = &lt;&amp;gpa2 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-volup {</div><div class='add'>+			label = "Volume Up Key";</div><div class='add'>+			gpios = &lt;&amp;gpa2 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x40000000 0x3f200000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pwrseq_mmc1: pwrseq-mmc1 {</div><div class='add'>+		compatible = "mmc-pwrseq-simple";</div><div class='add'>+		reset-gpios = &lt;&amp;gpd3 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* mmc2: vmmc */</div><div class='add'>+	vdd_fixed_mmc2: regulator-fixed-mmc2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vdd_fixed_mmc2";</div><div class='add'>+		regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpc0 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_fixed_proxled: regulator-fixed-proxled {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vdd_fixed_proxled";</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		gpio = &lt;&amp;gpd4 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		ramoops@46800000 {</div><div class='add'>+			compatible = "ramoops";</div><div class='add'>+			reg = &lt;0x0 0x46800000 0x8000&gt;;</div><div class='add'>+			console-size = &lt;0x4000&gt;;</div><div class='add'>+			pmsg-size = &lt;0x4000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cont_splash_mem: framebuffer@67000000 {</div><div class='add'>+			reg = &lt;0x0 0x67000000 (540 * 960 * 4)&gt;;</div><div class='add'>+			iommu-addresses = &lt;&amp;decon 0x67000000 (540 * 960 * 4)&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vibrator {</div><div class='add'>+		compatible = "regulator-haptic";</div><div class='add'>+		haptic-supply = &lt;&amp;vdd_ldo32&gt;;</div><div class='add'>+		min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;decon {</div><div class='add'>+	memory-region = &lt;&amp;cont_splash_mem&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsi {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	samsung,burst-clock-frequency = &lt;836000000&gt;;</div><div class='add'>+	samsung,esc-clock-frequency = &lt;16000000&gt;;</div><div class='add'>+	samsung,pll-clock-frequency = &lt;26000000&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	panel@0 {</div><div class='add'>+		compatible = "syna,td4101-panel";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		backlight-gpios = &lt;&amp;gpd3 7 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		width-mm = &lt;62&gt;;</div><div class='add'>+		height-mm = &lt;110&gt;;</div><div class='add'>+</div><div class='add'>+		panel-timing {</div><div class='add'>+			clock-frequency = &lt;69336720&gt;;</div><div class='add'>+</div><div class='add'>+			hactive = &lt;540&gt;;</div><div class='add'>+			hsync-len = &lt;4&gt;;</div><div class='add'>+			hfront-porch = &lt;364&gt;;</div><div class='add'>+			hback-porch = &lt;40&gt;;</div><div class='add'>+</div><div class='add'>+			vactive = &lt;960&gt;;</div><div class='add'>+			vsync-len = &lt;2&gt;;</div><div class='add'>+			vfront-porch = &lt;244&gt;;</div><div class='add'>+			vback-porch = &lt;13&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hsi2c0 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pmic@66 {</div><div class='add'>+		compatible = "samsung,s2mpu05-pmic";</div><div class='add'>+		reg = &lt;0x66&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpa0&gt;;</div><div class='add'>+		interrupts = &lt;2 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pmic_irq&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			vdd_buck1: buck1 {</div><div class='add'>+				regulator-name = "vdd_buck1";</div><div class='add'>+				regulator-min-microvolt = &lt;500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_buck2: buck2 {</div><div class='add'>+				regulator-name = "vdd_buck2";</div><div class='add'>+				regulator-min-microvolt = &lt;500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_buck3: buck3 {</div><div class='add'>+				regulator-name = "vdd_buck3";</div><div class='add'>+				regulator-min-microvolt = &lt;500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_buck4: buck4 {</div><div class='add'>+				regulator-name = "vdd_buck4";</div><div class='add'>+				regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1500000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_buck5: buck5 {</div><div class='add'>+				regulator-name = "vdd_buck5";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2100000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_ldo1: ldo1 {</div><div class='add'>+				regulator-name = "vdd_ldo1";</div><div class='add'>+				regulator-min-microvolt = &lt;650000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* mmc2: vqmmc */</div><div class='add'>+			vdd_ldo2: ldo2 {</div><div class='add'>+				regulator-name = "vdd_ldo2";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_ldo3: ldo3 {</div><div class='add'>+				regulator-name = "vdd_ldo3";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2375000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_ldo4: ldo4 {</div><div class='add'>+				regulator-name = "vdd_ldo4";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_ldo5: ldo5 {</div><div class='add'>+				regulator-name = "vdd_ldo5";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_ldo6: ldo6 {</div><div class='add'>+				regulator-name = "vdd_ldo6";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_ldo7: ldo7 {</div><div class='add'>+				regulator-name = "vdd_ldo7";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2375000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* usbdrd: vdd33 */</div><div class='add'>+			vdd_ldo8: ldo8 {</div><div class='add'>+				regulator-name = "vdd_ldo8";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3375000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_ldo9: ldo9 {</div><div class='add'>+				regulator-name = "vdd_ldo9";</div><div class='add'>+				regulator-min-microvolt = &lt;650000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_ldo10: ldo10 {</div><div class='add'>+				regulator-name = "vdd_ldo10";</div><div class='add'>+				regulator-min-microvolt = &lt;650000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_ldo25: ldo25 {</div><div class='add'>+				regulator-name = "vdd_ldo25";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2375000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* mmc0: vmmc */</div><div class='add'>+			vdd_ldo26: ldo26 {</div><div class='add'>+				regulator-name = "vdd_ldo26";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3375000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* mmc0: vqmmc */</div><div class='add'>+			vdd_ldo27: ldo27 {</div><div class='add'>+				regulator-name = "vdd_ldo27";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2375000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_ldo29: ldo29 {</div><div class='add'>+				regulator-name = "vdd_ldo29";</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_ldo30: ldo30 {</div><div class='add'>+				regulator-name = "vdd_ldo30";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_ldo31: ldo31 {</div><div class='add'>+				regulator-name = "vdd_ldo31";</div><div class='add'>+				regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* vibrator: haptic */</div><div class='add'>+			vdd_ldo32: ldo32 {</div><div class='add'>+				regulator-name = "vdd_ldo32";</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_ldo33: ldo33 {</div><div class='add'>+				regulator-name = "vdd_ldo33";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_ldo34: ldo34 {</div><div class='add'>+				regulator-name = "vdd_ldo34";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* touchscreen: vdd */</div><div class='add'>+			vdd_ldo35: ldo35 {</div><div class='add'>+				regulator-name = "vdd_ldo35";</div><div class='add'>+				regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c5 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	samsung,i2c-sda-delay = &lt;100&gt;;</div><div class='add'>+	samsung,i2c-max-bus-freq = &lt;400000&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	accelerometer@1d {</div><div class='add'>+		compatible = "st,lis2ds12";</div><div class='add'>+		reg = &lt;0x1d&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpa2&gt;;</div><div class='add'>+		interrupts = &lt;3 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;accel_irq&gt;;</div><div class='add'>+</div><div class='add'>+		st,drdy-int-pin = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	proximity@48 {</div><div class='add'>+		compatible = "sensortek,stk3013", "sensortek,stk3310";</div><div class='add'>+		reg = &lt;0x48&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpa0&gt;;</div><div class='add'>+		interrupts = &lt;5 IRQ_TYPE_EDGE_BOTH&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;proxm_irq&gt;;</div><div class='add'>+</div><div class='add'>+		proximity-near-level = &lt;25&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c6 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	samsung,i2c-sda-delay = &lt;100&gt;;</div><div class='add'>+	samsung,i2c-max-bus-freq = &lt;400000&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	touchscreen@4b {</div><div class='add'>+		compatible = "syna,rmi4-i2c";</div><div class='add'>+		reg = &lt;0x4b&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpa0&gt;;</div><div class='add'>+		interrupts = &lt;6 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;touch_irq&gt;;</div><div class='add'>+</div><div class='add'>+		vdd-supply = &lt;&amp;vdd_ldo35&gt;;</div><div class='add'>+</div><div class='add'>+		syna,reset-delay-ms = &lt;200&gt;;</div><div class='add'>+		syna,startup-delay-ms = &lt;200&gt;;</div><div class='add'>+</div><div class='add'>+		rmi4-f01@1 {</div><div class='add'>+			reg = &lt;0x01&gt;;</div><div class='add'>+			syna,nosleep-mode = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rmi4-f12@12 {</div><div class='add'>+			reg = &lt;0x12&gt;;</div><div class='add'>+			syna,sensor-type = &lt;1&gt;;</div><div class='add'>+			syna,rezero-wait-ms = &lt;200&gt;;</div><div class='add'>+			syna,clip-x-high = &lt;539&gt;;</div><div class='add'>+			syna,clip-y-high = &lt;959&gt;;</div><div class='add'>+			touchscreen-x-mm = &lt;62&gt;;</div><div class='add'>+			touchscreen-y-mm = &lt;110&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;sd0_clk &amp;sd0_cmd &amp;sd0_rdqs &amp;sd0_bus1 &amp;sd0_bus4 &amp;sd0_bus8&gt;;</div><div class='add'>+</div><div class='add'>+	vmmc-supply = &lt;&amp;vdd_ldo26&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;vdd_ldo27&gt;;</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	fifo-depth = &lt;64&gt;;</div><div class='add'>+	samsung,dw-mshc-ciu-div = &lt;3&gt;;</div><div class='add'>+	samsung,dw-mshc-sdr-timing = &lt;0 4&gt;;</div><div class='add'>+	samsung,dw-mshc-ddr-timing = &lt;2 4&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc1 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;sd1_clk &amp;sd1_cmd &amp;sd1_bus1 &amp;sd1_bus4&gt;;</div><div class='add'>+</div><div class='add'>+	mmc-pwrseq = &lt;&amp;pwrseq_mmc1&gt;;</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	fifo-depth = &lt;64&gt;;</div><div class='add'>+	samsung,dw-mshc-ciu-div = &lt;3&gt;;</div><div class='add'>+	samsung,dw-mshc-sdr-timing = &lt;0 3&gt;;</div><div class='add'>+	samsung,dw-mshc-ddr-timing = &lt;1 2&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	cap-sdio-irq;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	wifi@1 {</div><div class='add'>+		compatible = "brcm,bcm43430a1-fmac", "brcm,bcm4329-fmac";</div><div class='add'>+		reg = &lt;0x1&gt;;</div><div class='add'>+		interrupt-names = "host-wake";</div><div class='add'>+		interrupt-parent = &lt;&amp;gpa2&gt;;</div><div class='add'>+		interrupts = &lt;2 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		reset-gpios = &lt;&amp;gpd3 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;sd2_clk &amp;sd2_cmd &amp;sd2_bus1 &amp;sd2_bus4 &amp;dwmmc2_irq&gt;;</div><div class='add'>+</div><div class='add'>+	vmmc-supply = &lt;&amp;vdd_fixed_mmc2&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;vdd_ldo2&gt;;</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	card-detect-delay = &lt;200&gt;;</div><div class='add'>+	fifo-depth = &lt;64&gt;;</div><div class='add'>+	samsung,dw-mshc-ciu-div = &lt;3&gt;;</div><div class='add'>+	samsung,dw-mshc-sdr-timing = &lt;0 3&gt;;</div><div class='add'>+	samsung,dw-mshc-ddr-timing = &lt;1 2&gt;;</div><div class='add'>+	sd-uhs-sdr50;</div><div class='add'>+	sd-uhs-sdr104;</div><div class='add'>+	broken-cd;</div><div class='add'>+	disable-wp;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;oscclk {</div><div class='add'>+	clock-frequency = &lt;26000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_alive {</div><div class='add'>+	accel_irq: accel-irq-pins {</div><div class='add'>+		samsung,pins = "gpa2-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dwmmc2_irq: dwmmc2-irq-pins {</div><div class='add'>+		samsung,pins = "gpa0-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fuel_irq: fuel-irq-pins {</div><div class='add'>+		samsung,pins = "gpa0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	key_power: key-power-pins {</div><div class='add'>+		samsung,pins = "gpa0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	key_voldown: key-voldown-pins {</div><div class='add'>+		samsung,pins = "gpa2-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	key_volup: key-volup-pins {</div><div class='add'>+		samsung,pins = "gpa2-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmic_irq: pmic-irq-pins {</div><div class='add'>+		samsung,pins = "gpa0-2";</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	proxm_irq: proxm-irq-pins {</div><div class='add'>+		samsung,pins = "gpa0-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	touch_irq: touch-irq-pins {</div><div class='add'>+		samsung,pins = "gpa0-6";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wlan_hostwake: wlan-hostwake-pins {</div><div class='add'>+		samsung,pins = "gpa2-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_top {</div><div class='add'>+	bt_enable: bt-enable-pins {</div><div class='add'>+		samsung,pins = "gpd4-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wlan_enable: wlan-enable-pins {</div><div class='add'>+		samsung,pins = "gpd3-6";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR4&gt;;</div><div class='add'>+		samsung,pin-val = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;serial1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "brcm,bcm43430a1-bt";</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;bt_btwake &amp;bt_hostwake &amp;bt_enable&gt;;</div><div class='add'>+</div><div class='add'>+		device-wakeup-gpios = &lt;&amp;gpa1 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		host-wakeup-gpios = &lt;&amp;gpa1 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		shutdown-gpios = &lt;&amp;gpd4 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+		max-speed = &lt;3000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;serial2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbdrd {</div><div class='add'>+	vdd33-supply = &lt;&amp;vdd_ldo8&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/exynos7870-j6lte.dts b/arch/arm64/boot/dts/exynos/exynos7870-j6lte.dts<br/>new file mode 100644<br/>index 000000000000..09f2367cfec9<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynos7870-j6lte.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/exynos7870-j6lte.dts</a></div><div class='hunk'>@@ -0,0 +1,624 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Samsung Galaxy J6 (j6lte) device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2018 Samsung Electronics Co., Ltd.</div><div class='add'>+ * Copyright (c) 2025 Kaustabh Chakraborty &lt;kauschluss@disroot.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "exynos7870.dtsi"</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Samsung Galaxy J6";</div><div class='add'>+	compatible = "samsung,j6lte", "samsung,exynos7870";</div><div class='add'>+	chassis-type = "handset";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		mmc0 = &amp;mmc0;</div><div class='add'>+		mmc1 = &amp;mmc1;</div><div class='add'>+		mmc2 = &amp;mmc2;</div><div class='add'>+		serial0 = &amp;serial0;</div><div class='add'>+		serial1 = &amp;serial1;</div><div class='add'>+		serial2 = &amp;serial2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;serial2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-hall-effect-sensor {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		label = "GPIO Hall Effect Sensor";</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;hall_irq&gt;;</div><div class='add'>+</div><div class='add'>+		event-hall-effect-sensor {</div><div class='add'>+			label = "Hall Effect Sensor";</div><div class='add'>+			gpios = &lt;&amp;gpa1 3 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,input-type = &lt;EV_SW&gt;;</div><div class='add'>+			linux,code = &lt;SW_LID&gt;;</div><div class='add'>+			linux,can-disable;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		label = "GPIO Keys";</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;key_power &amp;key_voldown &amp;key_volup&gt;;</div><div class='add'>+</div><div class='add'>+		key-power {</div><div class='add'>+			label = "Power Key";</div><div class='add'>+			gpios = &lt;&amp;gpa0 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-voldown {</div><div class='add'>+			label = "Volume Down Key";</div><div class='add'>+			gpios = &lt;&amp;gpa2 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-volup {</div><div class='add'>+			label = "Volume Up Key";</div><div class='add'>+			gpios = &lt;&amp;gpa2 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x40000000 0x3d800000&gt;,</div><div class='add'>+		      &lt;0x0 0x80000000 0x40000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pwrseq_mmc1: pwrseq-mmc1 {</div><div class='add'>+		compatible = "mmc-pwrseq-simple";</div><div class='add'>+		reset-gpios = &lt;&amp;gpd3 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* mmc2: vmmc */</div><div class='add'>+	vdd_fixed_mmc2: regulator-fixed-mmc2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vdd_fixed_mmc2";</div><div class='add'>+		regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpc0 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		ramoops@46e00000 {</div><div class='add'>+			compatible = "ramoops";</div><div class='add'>+			reg = &lt;0x0 0x46e00000 0x8000&gt;;</div><div class='add'>+			console-size = &lt;0x4000&gt;;</div><div class='add'>+			pmsg-size = &lt;0x4000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cont_splash_mem: framebuffer@67000000 {</div><div class='add'>+			reg = &lt;0x0 0x67000000 (720 * 1480 * 4)&gt;;</div><div class='add'>+			iommu-addresses = &lt;&amp;decon 0x67000000 (720 * 1480 * 4)&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vibrator {</div><div class='add'>+		compatible = "regulator-haptic";</div><div class='add'>+		haptic-supply = &lt;&amp;vdd_ldo32&gt;;</div><div class='add'>+		min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;decon {</div><div class='add'>+	memory-region = &lt;&amp;cont_splash_mem&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsi {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	samsung,burst-clock-frequency = &lt;500000000&gt;;</div><div class='add'>+	samsung,esc-clock-frequency = &lt;16000000&gt;;</div><div class='add'>+	samsung,pll-clock-frequency = &lt;26000000&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	panel@0 {</div><div class='add'>+		compatible = "samsung,s6e8aa5x01-ams561ra01";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hsi2c0 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pmic@66 {</div><div class='add'>+		compatible = "samsung,s2mpu05-pmic";</div><div class='add'>+		reg = &lt;0x66&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpa0&gt;;</div><div class='add'>+		interrupts = &lt;2 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pmic_irq&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			vdd_buck1: buck1 {</div><div class='add'>+				regulator-name = "vdd_buck1";</div><div class='add'>+				regulator-min-microvolt = &lt;500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_buck2: buck2 {</div><div class='add'>+				regulator-name = "vdd_buck2";</div><div class='add'>+				regulator-min-microvolt = &lt;500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_buck3: buck3 {</div><div class='add'>+				regulator-name = "vdd_buck3";</div><div class='add'>+				regulator-min-microvolt = &lt;500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_buck4: buck4 {</div><div class='add'>+				regulator-name = "vdd_buck4";</div><div class='add'>+				regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1500000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_buck5: buck5 {</div><div class='add'>+				regulator-name = "vdd_buck5";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2100000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_ldo1: ldo1 {</div><div class='add'>+				regulator-name = "vdd_ldo1";</div><div class='add'>+				regulator-min-microvolt = &lt;650000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* mmc2: vqmmc */</div><div class='add'>+			vdd_ldo2: ldo2 {</div><div class='add'>+				regulator-name = "vdd_ldo2";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_ldo3: ldo3 {</div><div class='add'>+				regulator-name = "vdd_ldo3";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2375000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_ldo4: ldo4 {</div><div class='add'>+				regulator-name = "vdd_ldo4";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_ldo5: ldo5 {</div><div class='add'>+				regulator-name = "vdd_ldo5";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_ldo6: ldo6 {</div><div class='add'>+				regulator-name = "vdd_ldo6";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_ldo7: ldo7 {</div><div class='add'>+				regulator-name = "vdd_ldo7";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2375000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* usbdrd: vdd33 */</div><div class='add'>+			vdd_ldo8: ldo8 {</div><div class='add'>+				regulator-name = "vdd_ldo8";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3375000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_ldo9: ldo9 {</div><div class='add'>+				regulator-name = "vdd_ldo9";</div><div class='add'>+				regulator-min-microvolt = &lt;650000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_ldo10: ldo10 {</div><div class='add'>+				regulator-name = "vdd_ldo10";</div><div class='add'>+				regulator-min-microvolt = &lt;650000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_ldo25: ldo25 {</div><div class='add'>+				regulator-name = "vdd_ldo25";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2375000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* mmc0: vmmc */</div><div class='add'>+			vdd_ldo26: ldo26 {</div><div class='add'>+				regulator-name = "vdd_ldo26";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3375000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* mmc0: vqmmc */</div><div class='add'>+			vdd_ldo27: ldo27 {</div><div class='add'>+				regulator-name = "vdd_ldo27";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2375000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_ldo29: ldo29 {</div><div class='add'>+				regulator-name = "vdd_ldo29";</div><div class='add'>+				regulator-min-microvolt = &lt;3000000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3000000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_ldo30: ldo30 {</div><div class='add'>+				regulator-name = "vdd_ldo30";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_ldo31: ldo31 {</div><div class='add'>+				regulator-name = "vdd_ldo31";</div><div class='add'>+				regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* vibrator: haptic */</div><div class='add'>+			vdd_ldo32: ldo32 {</div><div class='add'>+				regulator-name = "vdd_ldo32";</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_ldo33: ldo33 {</div><div class='add'>+				regulator-name = "vdd_ldo33";</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* touchscreen: vdd */</div><div class='add'>+			vdd_ldo34: ldo34 {</div><div class='add'>+				regulator-name = "vdd_ldo34";</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_ldo35: ldo35 {</div><div class='add'>+				regulator-name = "vdd_ldo35";</div><div class='add'>+				regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c5 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	samsung,i2c-sda-delay = &lt;100&gt;;</div><div class='add'>+	samsung,i2c-max-bus-freq = &lt;400000&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	accelerometer@1d {</div><div class='add'>+		compatible = "st,lis2ds12";</div><div class='add'>+		reg = &lt;0x1d&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpa2&gt;;</div><div class='add'>+		interrupts = &lt;3 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;accel_irq&gt;;</div><div class='add'>+</div><div class='add'>+		mount-matrix = "-1", "0",  "0",</div><div class='add'>+				"0", "1",  "0",</div><div class='add'>+				"0", "0", "-1";</div><div class='add'>+</div><div class='add'>+		st,drdy-int-pin = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c6 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	samsung,i2c-sda-delay = &lt;100&gt;;</div><div class='add'>+	samsung,i2c-max-bus-freq = &lt;400000&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	touchscreen@20 {</div><div class='add'>+		compatible = "zinitix,bt532";</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpa0&gt;;</div><div class='add'>+		interrupts = &lt;6 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;touch_irq&gt;;</div><div class='add'>+</div><div class='add'>+		touchscreen-size-x = &lt;720&gt;;</div><div class='add'>+		touchscreen-size-y = &lt;1480&gt;;</div><div class='add'>+</div><div class='add'>+		vdd-supply = &lt;&amp;vdd_ldo34&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;sd0_clk &amp;sd0_cmd &amp;sd0_rdqs &amp;sd0_bus1 &amp;sd0_bus4 &amp;sd0_bus8&gt;;</div><div class='add'>+</div><div class='add'>+	vmmc-supply = &lt;&amp;vdd_ldo26&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;vdd_ldo27&gt;;</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	fifo-depth = &lt;64&gt;;</div><div class='add'>+	samsung,dw-mshc-ciu-div = &lt;3&gt;;</div><div class='add'>+	samsung,dw-mshc-sdr-timing = &lt;0 4&gt;;</div><div class='add'>+	samsung,dw-mshc-ddr-timing = &lt;2 4&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc1 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;sd1_clk &amp;sd1_cmd &amp;sd1_bus1 &amp;sd1_bus4&gt;;</div><div class='add'>+</div><div class='add'>+	mmc-pwrseq = &lt;&amp;pwrseq_mmc1&gt;;</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	fifo-depth = &lt;64&gt;;</div><div class='add'>+	samsung,dw-mshc-ciu-div = &lt;3&gt;;</div><div class='add'>+	samsung,dw-mshc-sdr-timing = &lt;0 3&gt;;</div><div class='add'>+	samsung,dw-mshc-ddr-timing = &lt;1 2&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	cap-sdio-irq;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	wifi@1 {</div><div class='add'>+		compatible = "brcm,bcm43430a1-fmac", "brcm,bcm4329-fmac";</div><div class='add'>+		reg = &lt;0x1&gt;;</div><div class='add'>+		interrupt-names = "host-wake";</div><div class='add'>+		interrupt-parent = &lt;&amp;gpa2&gt;;</div><div class='add'>+		interrupts = &lt;2 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		reset-gpios = &lt;&amp;gpd3 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;sd2_clk &amp;sd2_cmd &amp;sd2_bus1 &amp;sd2_bus4 &amp;dwmmc2_irq&gt;;</div><div class='add'>+</div><div class='add'>+	vmmc-supply = &lt;&amp;vdd_fixed_mmc2&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;vdd_ldo2&gt;;</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	card-detect-delay = &lt;200&gt;;</div><div class='add'>+	fifo-depth = &lt;64&gt;;</div><div class='add'>+	samsung,dw-mshc-ciu-div = &lt;3&gt;;</div><div class='add'>+	samsung,dw-mshc-sdr-timing = &lt;0 3&gt;;</div><div class='add'>+	samsung,dw-mshc-ddr-timing = &lt;1 2&gt;;</div><div class='add'>+	sd-uhs-sdr50;</div><div class='add'>+	sd-uhs-sdr104;</div><div class='add'>+	broken-cd;</div><div class='add'>+	disable-wp;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;oscclk {</div><div class='add'>+	clock-frequency = &lt;26000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_alive {</div><div class='add'>+	accel_irq: accel-irq-pins {</div><div class='add'>+		samsung,pins = "gpa2-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dwmmc2_irq: dwmmc2-irq-pins {</div><div class='add'>+		samsung,pins = "gpa0-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fuel_irq: fuel-irq-pins {</div><div class='add'>+		samsung,pins = "gpa0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hall_irq: hall-irq-pins {</div><div class='add'>+		samsung,pins = "gpa1-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	key_power: key-power-pins {</div><div class='add'>+		samsung,pins = "gpa0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	key_voldown: key-voldown-pins {</div><div class='add'>+		samsung,pins = "gpa2-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	key_volup: key-volup-pins {</div><div class='add'>+		samsung,pins = "gpa2-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmic_irq: pmic-irq-pins {</div><div class='add'>+		samsung,pins = "gpa0-2";</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	touch_irq: touch-irq-pins {</div><div class='add'>+		samsung,pins = "gpa0-6";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wlan_hostwake: wlan-hostwake-pins {</div><div class='add'>+		samsung,pins = "gpa2-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_top {</div><div class='add'>+	bt_enable: bt-enable-pins {</div><div class='add'>+		samsung,pins = "gpd4-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wlan_enable: wlan-enable-pins {</div><div class='add'>+		samsung,pins = "gpd3-6";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR4&gt;;</div><div class='add'>+		samsung,pin-val = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;serial1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "brcm,bcm43430a1-bt";</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;bt_btwake &amp;bt_hostwake &amp;bt_enable&gt;;</div><div class='add'>+</div><div class='add'>+		device-wakeup-gpios = &lt;&amp;gpa1 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		host-wakeup-gpios = &lt;&amp;gpa1 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		shutdown-gpios = &lt;&amp;gpd4 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+		max-speed = &lt;3000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;serial2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbdrd {</div><div class='add'>+	vdd33-supply = &lt;&amp;vdd_ldo8&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/exynos7870-on7xelte.dts b/arch/arm64/boot/dts/exynos/exynos7870-on7xelte.dts<br/>new file mode 100644<br/>index 000000000000..29e124c72e9d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynos7870-on7xelte.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/exynos7870-on7xelte.dts</a></div><div class='hunk'>@@ -0,0 +1,692 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Samsung Galaxy J7 Prime (on7xelte) device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2015 Samsung Electronics Co., Ltd.</div><div class='add'>+ * Copyright (c) 2025 Kaustabh Chakraborty &lt;kauschluss@disroot.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "exynos7870.dtsi"</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Samsung Galaxy J7 Prime";</div><div class='add'>+	compatible = "samsung,on7xelte", "samsung,exynos7870";</div><div class='add'>+	chassis-type = "handset";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		mmc0 = &amp;mmc0;</div><div class='add'>+		mmc1 = &amp;mmc1;</div><div class='add'>+		mmc2 = &amp;mmc2;</div><div class='add'>+		serial0 = &amp;serial0;</div><div class='add'>+		serial1 = &amp;serial1;</div><div class='add'>+		serial2 = &amp;serial2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;serial2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		label = "GPIO Keys";</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;key_home &amp;key_power &amp;key_voldown &amp;key_volup&gt;;</div><div class='add'>+</div><div class='add'>+		key-home {</div><div class='add'>+			label = "Home Key";</div><div class='add'>+			gpios = &lt;&amp;gpa1 7 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_HOMEPAGE&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-power {</div><div class='add'>+			label = "Power Key";</div><div class='add'>+			gpios = &lt;&amp;gpa0 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-voldown {</div><div class='add'>+			label = "Volume Down Key";</div><div class='add'>+			gpios = &lt;&amp;gpa2 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-volup {</div><div class='add'>+			label = "Volume Up Key";</div><div class='add'>+			gpios = &lt;&amp;gpa2 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x40000000 0x3e400000&gt;,</div><div class='add'>+		      &lt;0x0 0x80000000 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pwrseq_mmc1: pwrseq-mmc1 {</div><div class='add'>+		compatible = "mmc-pwrseq-simple";</div><div class='add'>+		reset-gpios = &lt;&amp;gpd3 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* mmc2: vmmc */</div><div class='add'>+	vdd_fixed_mmc2: regulator-fixed-mmc2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vdd_fixed_mmc2";</div><div class='add'>+		regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpc0 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		ramoops@46e00000 {</div><div class='add'>+			compatible = "ramoops";</div><div class='add'>+			reg = &lt;0x0 0x46e00000 0x8000&gt;;</div><div class='add'>+			console-size = &lt;0x4000&gt;;</div><div class='add'>+			pmsg-size = &lt;0x4000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cont_splash_mem: framebuffer@67000000 {</div><div class='add'>+			reg = &lt;0x0 0x67000000 (1080 * 1920 * 4)&gt;;</div><div class='add'>+			iommu-addresses = &lt;&amp;decon 0x67000000 (1080 * 1920 * 4)&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vibrator {</div><div class='add'>+		compatible = "regulator-haptic";</div><div class='add'>+		haptic-supply = &lt;&amp;vdd_ldo32&gt;;</div><div class='add'>+		min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;decon {</div><div class='add'>+	memory-region = &lt;&amp;cont_splash_mem&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsi {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	samsung,burst-clock-frequency = &lt;1001000000&gt;;</div><div class='add'>+	samsung,esc-clock-frequency = &lt;16000000&gt;;</div><div class='add'>+	samsung,pll-clock-frequency = &lt;26000000&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	panel@0 {</div><div class='add'>+		compatible = "syna,td4300-panel";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		backlight-gpios = &lt;&amp;gpd3 5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		width-mm = &lt;68&gt;;</div><div class='add'>+		height-mm = &lt;121&gt;;</div><div class='add'>+</div><div class='add'>+		panel-timing {</div><div class='add'>+			clock-frequency = &lt;144389520&gt;;</div><div class='add'>+</div><div class='add'>+			hactive = &lt;1080&gt;;</div><div class='add'>+			hsync-len = &lt;4&gt;;</div><div class='add'>+			hfront-porch = &lt;120&gt;;</div><div class='add'>+			hback-porch = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			vactive = &lt;1920&gt;;</div><div class='add'>+			vsync-len = &lt;2&gt;;</div><div class='add'>+			vfront-porch = &lt;21&gt;;</div><div class='add'>+			vback-porch = &lt;4&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hsi2c0 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pmic@66 {</div><div class='add'>+		compatible = "samsung,s2mpu05-pmic";</div><div class='add'>+		reg = &lt;0x66&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-parent = &lt;&amp;gpa0&gt;;</div><div class='add'>+		interrupts = &lt;2 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pmic_irq&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			vdd_buck1: buck1 {</div><div class='add'>+				regulator-name = "vdd_buck1";</div><div class='add'>+				regulator-min-microvolt = &lt;500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_buck2: buck2 {</div><div class='add'>+				regulator-name = "vdd_buck2";</div><div class='add'>+				regulator-min-microvolt = &lt;500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_buck3: buck3 {</div><div class='add'>+				regulator-name = "vdd_buck3";</div><div class='add'>+				regulator-min-microvolt = &lt;500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_buck4: buck4 {</div><div class='add'>+				regulator-name = "vdd_buck4";</div><div class='add'>+				regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1500000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_buck5: buck5 {</div><div class='add'>+				regulator-name = "vdd_buck5";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2100000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_ldo1: ldo1 {</div><div class='add'>+				regulator-name = "vdd_ldo1";</div><div class='add'>+				regulator-min-microvolt = &lt;650000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* mmc2: vqmmc */</div><div class='add'>+			vdd_ldo2: ldo2 {</div><div class='add'>+				regulator-name = "vdd_ldo2";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_ldo3: ldo3 {</div><div class='add'>+				regulator-name = "vdd_ldo3";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2375000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_ldo4: ldo4 {</div><div class='add'>+				regulator-name = "vdd_ldo4";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_ldo5: ldo5 {</div><div class='add'>+				regulator-name = "vdd_ldo5";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_ldo6: ldo6 {</div><div class='add'>+				regulator-name = "vdd_ldo6";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_ldo7: ldo7 {</div><div class='add'>+				regulator-name = "vdd_ldo7";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2375000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* usbdrd: vdd33 */</div><div class='add'>+			vdd_ldo8: ldo8 {</div><div class='add'>+				regulator-name = "vdd_ldo8";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3375000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_ldo9: ldo9 {</div><div class='add'>+				regulator-name = "vdd_ldo9";</div><div class='add'>+				regulator-min-microvolt = &lt;650000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_ldo10: ldo10 {</div><div class='add'>+				regulator-name = "vdd_ldo10";</div><div class='add'>+				regulator-min-microvolt = &lt;650000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_ldo25: ldo25 {</div><div class='add'>+				regulator-name = "vdd_ldo25";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2375000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* mmc0: vmmc */</div><div class='add'>+			vdd_ldo26: ldo26 {</div><div class='add'>+				regulator-name = "vdd_ldo26";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3375000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* mmc0: vqmmc */</div><div class='add'>+			vdd_ldo27: ldo27 {</div><div class='add'>+				regulator-name = "vdd_ldo27";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2375000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_ldo29: ldo29 {</div><div class='add'>+				regulator-name = "vdd_ldo29";</div><div class='add'>+				regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_ldo30: ldo30 {</div><div class='add'>+				regulator-name = "vdd_ldo30";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_ldo31: ldo31 {</div><div class='add'>+				regulator-name = "vdd_ldo31";</div><div class='add'>+				regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* vibrator: haptic */</div><div class='add'>+			vdd_ldo32: ldo32 {</div><div class='add'>+				regulator-name = "vdd_ldo32";</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_ldo33: ldo33 {</div><div class='add'>+				regulator-name = "vdd_ldo33";</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_ldo34: ldo34 {</div><div class='add'>+				regulator-name = "vdd_ldo34";</div><div class='add'>+				regulator-min-microvolt = &lt;3000000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3000000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdd_ldo35: ldo35 {</div><div class='add'>+				regulator-name = "vdd_ldo35";</div><div class='add'>+				regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	samsung,i2c-sda-delay = &lt;100&gt;;</div><div class='add'>+	samsung,i2c-max-bus-freq = &lt;400000&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	touchscreen@70 {</div><div class='add'>+		compatible = "syna,rmi4-i2c";</div><div class='add'>+		reg = &lt;0x70&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpc3&gt;;</div><div class='add'>+		interrupts = &lt;2 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;touch_irq&gt;;</div><div class='add'>+</div><div class='add'>+		syna,reset-delay-ms = &lt;200&gt;;</div><div class='add'>+		syna,startup-delay-ms = &lt;200&gt;;</div><div class='add'>+</div><div class='add'>+		rmi4-f01@1 {</div><div class='add'>+			reg = &lt;0x01&gt;;</div><div class='add'>+			syna,nosleep-mode = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rmi4-f12@12 {</div><div class='add'>+			reg = &lt;0x12&gt;;</div><div class='add'>+			syna,sensor-type = &lt;1&gt;;</div><div class='add'>+			syna,rezero-wait-ms = &lt;200&gt;;</div><div class='add'>+			syna,clip-x-high = &lt;1079&gt;;</div><div class='add'>+			syna,clip-y-high = &lt;1919&gt;;</div><div class='add'>+			touchscreen-x-mm = &lt;68&gt;;</div><div class='add'>+			touchscreen-y-mm = &lt;121&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c7 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	samsung,i2c-sda-delay = &lt;100&gt;;</div><div class='add'>+	samsung,i2c-max-bus-freq = &lt;400000&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	accelerometer@1d {</div><div class='add'>+		compatible = "st,lis2hh12";</div><div class='add'>+		reg = &lt;0x1d&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpa2&gt;;</div><div class='add'>+		interrupts = &lt;3 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;accel_irq&gt;;</div><div class='add'>+</div><div class='add'>+		mount-matrix = "1",  "0",  "0",</div><div class='add'>+			       "0", "-1",  "0",</div><div class='add'>+			       "0",  "0", "-1";</div><div class='add'>+</div><div class='add'>+		st,drdy-int-pin = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c8 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	samsung,i2c-sda-delay = &lt;100&gt;;</div><div class='add'>+	samsung,i2c-max-bus-freq = &lt;400000&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	proximity@48 {</div><div class='add'>+		compatible = "sensortek,stk3013", "sensortek,stk3310";</div><div class='add'>+		reg = &lt;0x48&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpa0&gt;;</div><div class='add'>+		interrupts = &lt;5 IRQ_TYPE_EDGE_BOTH&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;proxm_irq&gt;;</div><div class='add'>+</div><div class='add'>+		proximity-near-level = &lt;25&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;sd0_clk &amp;sd0_cmd &amp;sd0_rdqs &amp;sd0_bus1 &amp;sd0_bus4 &amp;sd0_bus8&gt;;</div><div class='add'>+</div><div class='add'>+	vmmc-supply = &lt;&amp;vdd_ldo26&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;vdd_ldo27&gt;;</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	fifo-depth = &lt;64&gt;;</div><div class='add'>+	samsung,dw-mshc-ciu-div = &lt;3&gt;;</div><div class='add'>+	samsung,dw-mshc-sdr-timing = &lt;0 4&gt;;</div><div class='add'>+	samsung,dw-mshc-ddr-timing = &lt;2 4&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc1 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;sd1_clk &amp;sd1_cmd &amp;sd1_bus1 &amp;sd1_bus4&gt;;</div><div class='add'>+</div><div class='add'>+	mmc-pwrseq = &lt;&amp;pwrseq_mmc1&gt;;</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	fifo-depth = &lt;64&gt;;</div><div class='add'>+	samsung,dw-mshc-ciu-div = &lt;3&gt;;</div><div class='add'>+	samsung,dw-mshc-sdr-timing = &lt;0 3&gt;;</div><div class='add'>+	samsung,dw-mshc-ddr-timing = &lt;1 2&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	cap-sdio-irq;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	wifi@1 {</div><div class='add'>+		compatible = "brcm,bcm43430a1-fmac", "brcm,bcm4329-fmac";</div><div class='add'>+		reg = &lt;0x1&gt;;</div><div class='add'>+		interrupt-names = "host-wake";</div><div class='add'>+		interrupt-parent = &lt;&amp;gpa2&gt;;</div><div class='add'>+		interrupts = &lt;2 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		reset-gpios = &lt;&amp;gpd3 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;sd2_clk &amp;sd2_cmd &amp;sd2_bus1 &amp;sd2_bus4 &amp;dwmmc2_irq&gt;;</div><div class='add'>+</div><div class='add'>+	vmmc-supply = &lt;&amp;vdd_fixed_mmc2&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;vdd_ldo2&gt;;</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	card-detect-delay = &lt;200&gt;;</div><div class='add'>+	fifo-depth = &lt;64&gt;;</div><div class='add'>+	samsung,dw-mshc-ciu-div = &lt;3&gt;;</div><div class='add'>+	samsung,dw-mshc-sdr-timing = &lt;0 3&gt;;</div><div class='add'>+	samsung,dw-mshc-ddr-timing = &lt;1 2&gt;;</div><div class='add'>+	sd-uhs-sdr50;</div><div class='add'>+	sd-uhs-sdr104;</div><div class='add'>+	broken-cd;</div><div class='add'>+	disable-wp;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;oscclk {</div><div class='add'>+	clock-frequency = &lt;26000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_alive {</div><div class='add'>+	accel_irq: accel-irq-pins {</div><div class='add'>+		samsung,pins = "gpa2-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dwmmc2_irq: dwmmc2-irq-pins {</div><div class='add'>+		samsung,pins = "gpa0-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fuel_irq: fuel-irq-pins {</div><div class='add'>+		samsung,pins = "gpa0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	key_home: key-home-pins {</div><div class='add'>+		samsung,pins = "gpa1-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	key_power: key-power-pins {</div><div class='add'>+		samsung,pins = "gpa0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	key_voldown: key-voldown-pins {</div><div class='add'>+		samsung,pins = "gpa2-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	key_volup: key-volup-pins {</div><div class='add'>+		samsung,pins = "gpa2-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmic_irq: pmic-irq-pins {</div><div class='add'>+		samsung,pins = "gpa0-2";</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	proxm_irq: proxm-irq-pins {</div><div class='add'>+		samsung,pins = "gpa0-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	tkey_irq: tkey-irq-pins {</div><div class='add'>+		samsung,pins = "gpa1-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wlan_hostwake: wlan-hostwake-pins {</div><div class='add'>+		samsung,pins = "gpa2-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_top {</div><div class='add'>+	bt_enable: bt-enable-pins {</div><div class='add'>+		samsung,pins = "gpd4-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wlan_enable: wlan-enable-pins {</div><div class='add'>+		samsung,pins = "gpd3-6";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR4&gt;;</div><div class='add'>+		samsung,pin-val = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_touch {</div><div class='add'>+	touch_irq: touch-irq-pins {</div><div class='add'>+		samsung,pins = "gpc3-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;serial1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "brcm,bcm43430a1-bt";</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;bt_btwake &amp;bt_hostwake &amp;bt_enable&gt;;</div><div class='add'>+</div><div class='add'>+		device-wakeup-gpios = &lt;&amp;gpa1 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		host-wakeup-gpios = &lt;&amp;gpa1 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		shutdown-gpios = &lt;&amp;gpd4 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+		max-speed = &lt;3000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;serial2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbdrd {</div><div class='add'>+	vdd33-supply = &lt;&amp;vdd_ldo8&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/exynos7870-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos7870-pinctrl.dtsi<br/>new file mode 100644<br/>index 000000000000..99a28d06aee7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynos7870-pinctrl.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/exynos7870-pinctrl.dtsi</a></div><div class='hunk'>@@ -0,0 +1,1021 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Samsung Exynos7870 SoC pin-mux and pin-config device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2015 Samsung Electronics Co., Ltd.</div><div class='add'>+ * Copyright (c) 2025 Kaustabh Chakraborty &lt;kauschluss@disroot.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include "exynos-pinctrl.h"</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_alive {</div><div class='add'>+	etc0: etc0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	etc1: etc1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpa0: gpa0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpa1: gpa1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpa2: gpa2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpq0: gpq0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bt_btwake: bt-btwake-pins {</div><div class='add'>+		samsung,pins = "gpa1-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bt_hostwake: bt-hostwake-pins {</div><div class='add'>+		samsung,pins = "gpa1-6";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gnss_sensor_i2c: gnss-sensor-i2c-pins {</div><div class='add'>+		samsung,pins = "gpa2-5", "gpa2-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_6&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gnss_sensor_irq: gnss-sensor-irq-pins {</div><div class='add'>+		samsung,pins = "gpa2-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_6&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	nfc_int: nfc-int-pins {</div><div class='add'>+		samsung,pins = "gpa2-6";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart2_bus: uart2-bus-pins {</div><div class='add'>+		samsung,pins = "gpa1-1", "gpa1-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart2_sleep: uart2-sleep-pins {</div><div class='add'>+		samsung,pins = "gpa1-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_dispaud {</div><div class='add'>+	gpz0: gpz0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpz1: gpz1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpz2: gpz2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2s_amp_bus: i2s-amp-bus-pins {</div><div class='add'>+		samsung,pins = "gpz1-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2s_amp_bus_idle: i2s-amp-bus-idle-pins {</div><div class='add'>+		samsung,pins = "gpz1-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2s_bt_bus: i2s-bt-bus-pins {</div><div class='add'>+		samsung,pins = "gpz0-0", "gpz0-1", "gpz0-2", "gpz0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2s_bt_bus_idle: i2s-bt-bus-idle-pins {</div><div class='add'>+		samsung,pins = "gpz0-0", "gpz0-1", "gpz0-2", "gpz0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2s_pmic_amp_bus: i2s-pmic-amp-bus-pins {</div><div class='add'>+		samsung,pins = "gpz1-0", "gpz1-1", "gpz1-2", "gpz1-3", "gpz1-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR6&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2s_pmic_amp_bus_idle: i2s-pmic-amp-bus-idle-pins {</div><div class='add'>+		samsung,pins = "gpz1-0", "gpz1-1", "gpz1-2", "gpz1-3", "gpz1-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR6&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2s_pmic_bus: i2s-pmic-bus-pins {</div><div class='add'>+		samsung,pins = "gpz1-0", "gpz1-2", "gpz1-3", "gpz1-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR6&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2s_pmic_bus_idle: i2s-pmic-bus-idle-pins {</div><div class='add'>+		samsung,pins = "gpz1-0", "gpz1-2", "gpz1-3", "gpz1-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR6&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2s_fm_bus: i2s-fm-bus-pins {</div><div class='add'>+		samsung,pins = "gpz2-0", "gpz2-1", "gpz2-2", "gpz2-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2s_fm_bus_idle: i2s-fm-bus-idle-pins {</div><div class='add'>+		samsung,pins = "gpz2-0", "gpz2-1", "gpz2-2", "gpz2-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_ese {</div><div class='add'>+	gpc7: gpc7-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi0_bus: spi0-bus-pins {</div><div class='add'>+		samsung,pins = "gpc7-3", "gpc7-2", "gpc7-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi0_cs0: spi0-cs0-pins {</div><div class='add'>+		samsung,pins = "gpc7-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi0_cs1: spi0-cs1-pins {</div><div class='add'>+		samsung,pins = "gpc7-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_fsys {</div><div class='add'>+	gpr0: gpr0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpr1: gpr1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpr2: gpr2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpr3: gpr3-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpr4: gpr4-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd0_bus1: sd0-bus-width1-pins {</div><div class='add'>+		samsung,pins = "gpr1-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd0_bus4: sd0-bus-width4-pins {</div><div class='add'>+		samsung,pins = "gpr1-1", "gpr1-2", "gpr1-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd0_bus8: sd0-bus-width8-pins {</div><div class='add'>+		samsung,pins = "gpr1-4", "gpr1-5", "gpr1-6", "gpr1-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd0_clk: sd0-clk-pins {</div><div class='add'>+		samsung,pins = "gpr0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd0_clk_fast_slew_rate_1x: sd0-clk-fast-slew-rate-1x-pins {</div><div class='add'>+		samsung,pins = "gpr0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd0_clk_fast_slew_rate_2x: sd0-clk-fast-slew-rate-2x-pins {</div><div class='add'>+		samsung,pins = "gpr0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd0_clk_fast_slew_rate_3x: sd0-clk-fast-slew-rate-3x-pins {</div><div class='add'>+		samsung,pins = "gpr0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd0_clk_fast_slew_rate_4x: sd0-clk-fast-slew-rate-4x-pins {</div><div class='add'>+		samsung,pins = "gpr0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd0_clk_fast_slew_rate_5x: sd0-clk-fast-slew-rate-5x-pins {</div><div class='add'>+		samsung,pins = "gpr0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR5&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd0_clk_fast_slew_rate_6x: sd0-clk-fast-slew-rate-6x-pins {</div><div class='add'>+		samsung,pins = "gpr0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR6&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd0_cmd: sd0-cmd-pins {</div><div class='add'>+		samsung,pins = "gpr0-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd0_rdqs: sd0-rdqs-pins {</div><div class='add'>+		samsung,pins = "gpr0-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd1_bus1: sd1-bus-width1-pins {</div><div class='add'>+		samsung,pins = "gpr3-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd1_bus4: sd1-bus-width4-pins {</div><div class='add'>+		samsung,pins = "gpr3-1", "gpr3-2", "gpr3-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd1_clk: sd1-clk-pins {</div><div class='add'>+		samsung,pins = "gpr2-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd1_cmd: sd1-cmd-pins {</div><div class='add'>+		samsung,pins = "gpr2-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_bus1: sd2-bus-width1-pins {</div><div class='add'>+		samsung,pins = "gpr4-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_bus4: sd2-bus-width4-pins {</div><div class='add'>+		samsung,pins = "gpr4-3", "gpr4-4", "gpr4-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_clk: sd2-clk-pins {</div><div class='add'>+		samsung,pins = "gpr4-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_clk_fast_slew_rate_1x: sd2-clk-fast-slew-rate-1x-pins {</div><div class='add'>+		samsung,pins = "gpr4-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_clk_fast_slew_rate_2x: sd2-clk-fast-slew-rate-2x-pins {</div><div class='add'>+		samsung,pins = "gpr4-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_clk_fast_slew_rate_3x: sd2-clk-fast-slew-rate-3x-pins {</div><div class='add'>+		samsung,pins = "gpr4-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_clk_fast_slew_rate_4x: sd2-clk-fast-slew-rate-4x-pins {</div><div class='add'>+		samsung,pins = "gpr4-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_cmd: sd2-cmd-pins {</div><div class='add'>+		samsung,pins = "gpr4-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_mif {</div><div class='add'>+	gpm0: gpm0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c0_bus: hsi2c0-bus-pins {</div><div class='add'>+		samsung,pins = "gpm0-1", "gpm0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_nfc {</div><div class='add'>+	gpc2: gpc2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c6_bus: i2c6-bus-pins {</div><div class='add'>+		samsung,pins = "gpc2-1", "gpc2-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	nfc_en: nfc-en-pins {</div><div class='add'>+		samsung,pins = "gpc2-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+		samsung,pin-val = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	nfc_n5_clk_req: nfc-n5-clk-req-pins {</div><div class='add'>+		samsung,pins = "gpc2-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	nfc_pd: nfc-pd-pins {</div><div class='add'>+		samsung,pins = "gpc2-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_top {</div><div class='add'>+	gpb0: gpb0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpc0: gpc0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpc1: gpc1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpc4: gpc4-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpc5: gpc5-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpc6: gpc6-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpc8: gpc8-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpc9: gpc9-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpd1: gpd1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpd2: gpd2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpd3: gpd3-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpd4: gpd4-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpe0: gpe0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpf0: gpf0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpf1: gpf1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpf2: gpf2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpf3: gpf3-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpf4: gpf4-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	decon_te_off: decon-te-off-pins {</div><div class='add'>+		samsung,pins = "gpe0-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	decon_te_on: decon-te-on-pins {</div><div class='add'>+		samsung,pins = "gpe0-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ese_pvdd_en: ese-pvdd-en-pins {</div><div class='add'>+		samsung,pins = "gpf4-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fimc_is_flash: fimc-is-flash-pins {</div><div class='add'>+		samsung,pins = "gpd3-2", "gpd3-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fimc_is_mclk0_fn: fimc-is-mclk0-fn-pins {</div><div class='add'>+		samsung,pins = "gpe0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fimc_is_mclk0_in: fimc-is-mclk0-in-pins {</div><div class='add'>+		samsung,pins = "gpe0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fimc_is_mclk0_out: fimc-is-mclk0-out-pins {</div><div class='add'>+		samsung,pins = "gpe0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fimc_is_mclk1_fn: fimc-is-mclk1-fn-pins {</div><div class='add'>+		samsung,pins = "gpe0-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fimc_is_mclk1_in: fimc-is-mclk1-in-pins {</div><div class='add'>+		samsung,pins = "gpe0-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fimc_is_mclk1_out: fimc-is-mclk1-out-pins {</div><div class='add'>+		samsung,pins = "gpe0-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fimc_is_mclk2_fn: fimc-is-mclk2-fn-pins {</div><div class='add'>+		samsung,pins = "gpf4-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fimc_is_mclk2_out: fimc-is-mclk2-out-pins {</div><div class='add'>+		samsung,pins = "gpf4-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR3&gt;;</div><div class='add'>+		samsung,pin-val = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c1_bus: hsi2c1-bus-pins {</div><div class='add'>+		samsung,pins = "gpf0-1", "gpf0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c2_bus: hsi2c2-bus-pins {</div><div class='add'>+		samsung,pins = "gpf1-1", "gpf1-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c3_bus: hsi2c3-bus-pins {</div><div class='add'>+		samsung,pins = "gpf0-3", "gpf0-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c4_bus: hsi2c4-bus-pins {</div><div class='add'>+		samsung,pins = "gpf2-1", "gpf2-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c5_bus: hsi2c5-bus-pins {</div><div class='add'>+		samsung,pins = "gpf3-0", "gpf3-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c6_bus: hsi2c6-bus-pins {</div><div class='add'>+		samsung,pins = "gpf3-2", "gpf3-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c0_bus: i2c0-bus-pins {</div><div class='add'>+		samsung,pins = "gpc4-1", "gpc4-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c2_bus: i2c2-bus-pins {</div><div class='add'>+		samsung,pins = "gpc8-1", "gpc8-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c3_bus: i2c3-bus-pins {</div><div class='add'>+		samsung,pins = "gpc9-1", "gpc9-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c4_bus: i2c4-bus-pins {</div><div class='add'>+		samsung,pins = "gpc1-1", "gpc1-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c5_bus: i2c5-bus-pins {</div><div class='add'>+		samsung,pins = "gpc1-3", "gpc1-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c7_bus: i2c7-bus-pins {</div><div class='add'>+		samsung,pins = "gpc4-3", "gpc4-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c8_bus: i2c8-bus-pins {</div><div class='add'>+		samsung,pins = "gpc5-1", "gpc5-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	nfc_n5_firm: nfc-n5-firm-pins {</div><div class='add'>+		samsung,pins = "gpd4-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+		samsung,pin-val = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	nfc_pvdd_en: nfc-pvdd-en-pins {</div><div class='add'>+		samsung,pins = "gpd2-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pwm_tout0: pwm-tout0-pins {</div><div class='add'>+		samsung,pins = "gpc0-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pwm_tout1: pwm-tout1-pins {</div><div class='add'>+		samsung,pins = "gpc0-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi1_bus: spi1-bus-pins {</div><div class='add'>+		samsung,pins = "gpf3-3", "gpf3-2", "gpf3-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi1_cs0: spi1-cs0-pins {</div><div class='add'>+		samsung,pins = "gpf3-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi1_cs1: spi1-cs1-pins {</div><div class='add'>+		samsung,pins = "gpd1-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi2_bus: spi2-bus-pins {</div><div class='add'>+		samsung,pins = "gpf4-3", "gpf4-2", "gpf4-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi2_cs0: spi2-cs0-pins {</div><div class='add'>+		samsung,pins = "gpf4-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi2_cs1: spi2-cs1-pins {</div><div class='add'>+		samsung,pins = "gpd1-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi3_bus: spi3-bus-pins {</div><div class='add'>+		samsung,pins = "gpc6-0", "gpc6-2", "gpc6-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi3_bus_suspend: spi3-bus-suspend-pins {</div><div class='add'>+		samsung,pins = "gpc6-0", "gpc6-2", "gpc6-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi3_cs: spi3-cs-pins {</div><div class='add'>+		samsung,pins = "gpc6-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi4_bus: spi4-bus-pins {</div><div class='add'>+		samsung,pins = "gpc4-2", "gpc5-0", "gpc5-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi4_cs: spi4-cs-pins {</div><div class='add'>+		samsung,pins = "gpc4-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi4_cs_func: spi4-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpc4-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi4_miso: spi4-miso-pins {</div><div class='add'>+		samsung,pins = "gpc5-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi4_mosi_sck_ssn: spi4-mosi-sck-ssn-pins {</div><div class='add'>+		samsung,pins = "gpc5-1", "gpc4-2", "gpc4-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart0_bus: uart0-bus-pins {</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pins = "gpd2-3", "gpd2-2", "gpd2-1", "gpd2-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart1_bus: uart1-bus-pins {</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pins = "gpb0-3", "gpb0-2", "gpb0-1", "gpb0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_touch {</div><div class='add'>+	gpc3: gpc3-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c1_bus: i2c1-bus-pins {</div><div class='add'>+		samsung,pins = "gpc3-1", "gpc3-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ese_cs_func: ese-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpc3-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+		samsung,pin-val = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ese_cs_func_suspend: ese-cs-func-suspend-pins {</div><div class='add'>+		samsung,pins = "gpc3-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5433_PIN_DRV_FAST_SR1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/exynos7870.dtsi b/arch/arm64/boot/dts/exynos/exynos7870.dtsi<br/>new file mode 100644<br/>index 000000000000..2827e10d6962<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynos7870.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/exynos7870.dtsi</a></div><div class='hunk'>@@ -0,0 +1,797 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Samsung Exynos7870 SoC device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2015 Samsung Electronics Co., Ltd.</div><div class='add'>+ * Copyright (c) 2025 Kaustabh Chakraborty &lt;kauschluss@disroot.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/samsung,exynos7870-cmu.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "samsung,exynos7870";</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		pinctrl0 = &amp;pinctrl_alive;</div><div class='add'>+		pinctrl1 = &amp;pinctrl_dispaud;</div><div class='add'>+		pinctrl2 = &amp;pinctrl_ese;</div><div class='add'>+		pinctrl3 = &amp;pinctrl_fsys;</div><div class='add'>+		pinctrl4 = &amp;pinctrl_mif;</div><div class='add'>+		pinctrl5 = &amp;pinctrl_nfc;</div><div class='add'>+		pinctrl6 = &amp;pinctrl_top;</div><div class='add'>+		pinctrl7 = &amp;pinctrl_touch;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu-map {</div><div class='add'>+			cluster0 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu0&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu1&gt;;</div><div class='add'>+				};</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu2&gt;;</div><div class='add'>+				};</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu3&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cluster1 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu4&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu5&gt;;</div><div class='add'>+				};</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu6&gt;;</div><div class='add'>+				};</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu7&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@1 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x1&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@2 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x2&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@3 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x3&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu4: cpu@100 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x100&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu5: cpu@101 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x101&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu6: cpu@102 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x102&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu7: cpu@103 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x103&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	oscclk: oscclk {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci";</div><div class='add'>+		method = "smc";</div><div class='add'>+		cpu_suspend = &lt;0xc4000001&gt;;</div><div class='add'>+		cpu_off = &lt;0x84000002&gt;;</div><div class='add'>+		cpu_on = &lt;0xc4000003&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc: soc@0 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		ranges = &lt;0x0 0x0 0x0 0x20000000&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		chipid@10100000 {</div><div class='add'>+			compatible = "samsung,exynos7870-chipid",</div><div class='add'>+				     "samsung,exynos4210-chipid";</div><div class='add'>+			reg = &lt;0x10100000 0x100&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_peri: clock-controller@101f0000 {</div><div class='add'>+			compatible = "samsung,exynos7870-cmu-peri";</div><div class='add'>+			reg = &lt;0x101f0000 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clock-names = "oscclk", "bus", "spi0", "spi1", "spi2",</div><div class='add'>+				      "spi3", "spi4", "uart0", "uart1", "uart2";</div><div class='add'>+			clocks = &lt;&amp;oscclk&gt;,</div><div class='add'>+				 &lt;&amp;cmu_mif CLK_GOUT_MIF_CMU_PERI_BUS&gt;,</div><div class='add'>+				 &lt;&amp;cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI0&gt;,</div><div class='add'>+				 &lt;&amp;cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI1&gt;,</div><div class='add'>+				 &lt;&amp;cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI2&gt;,</div><div class='add'>+				 &lt;&amp;cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI3&gt;,</div><div class='add'>+				 &lt;&amp;cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI4&gt;,</div><div class='add'>+				 &lt;&amp;cmu_mif CLK_GOUT_MIF_CMU_PERI_UART0&gt;,</div><div class='add'>+				 &lt;&amp;cmu_mif CLK_GOUT_MIF_CMU_PERI_UART1&gt;,</div><div class='add'>+				 &lt;&amp;cmu_mif CLK_GOUT_MIF_CMU_PERI_UART2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_mif: clock-controller@10460000 {</div><div class='add'>+			compatible = "samsung,exynos7870-cmu-mif";</div><div class='add'>+			reg = &lt;0x10460000 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clock-names = "oscclk";</div><div class='add'>+			clocks = &lt;&amp;oscclk&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmu_system_controller: system-controller@10480000 {</div><div class='add'>+			compatible = "samsung,exynos7870-pmu",</div><div class='add'>+				     "samsung,exynos7-pmu", "syscon";</div><div class='add'>+			reg = &lt;0x10480000 0x10000&gt;;</div><div class='add'>+</div><div class='add'>+			mipi_phy: mipi-phy {</div><div class='add'>+				compatible = "samsung,exynos7870-mipi-video-phy";</div><div class='add'>+				#phy-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				samsung,cam0-sysreg = &lt;&amp;syscon_cam0&gt;;</div><div class='add'>+				samsung,disp-sysreg = &lt;&amp;syscon_disp&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reboot-mode {</div><div class='add'>+				compatible = "syscon-reboot-mode";</div><div class='add'>+				offset = &lt;0x080c&gt;;</div><div class='add'>+				mode-bootloader = &lt;0x1234567d&gt;;</div><div class='add'>+				mode-download = &lt;0x12345671&gt;;</div><div class='add'>+				mode-recovery = &lt;0x12345674&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@104e1000 {</div><div class='add'>+			compatible = "arm,cortex-a15-gic";</div><div class='add'>+			reg = &lt;0x104e1000 0x1000&gt;,</div><div class='add'>+			      &lt;0x104e2000 0x1000&gt;,</div><div class='add'>+			      &lt;0x104e4000 0x2000&gt;,</div><div class='add'>+			      &lt;0x104e6000 0x2000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |</div><div class='add'>+						 IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#address-cells = &lt;0&gt;;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		hsi2c0: i2c@10510000 {</div><div class='add'>+			compatible = "samsung,exynos7870-hsi2c",</div><div class='add'>+				     "samsung,exynos7-hsi2c";</div><div class='add'>+			reg = &lt;0x10510000 0x2000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;hsi2c0_bus&gt;;</div><div class='add'>+</div><div class='add'>+			clock-names = "hsi2c";</div><div class='add'>+			clocks = &lt;&amp;cmu_mif CLK_GOUT_MIF_HSI2C_IPCLK&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_mif: pinctrl@10530000 {</div><div class='add'>+			compatible = "samsung,exynos7870-pinctrl";</div><div class='add'>+			reg = &lt;0x10530000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu: gpu@11400000 {</div><div class='add'>+			compatible = "samsung,exynos7870-mali", "arm,mali-t830";</div><div class='add'>+			reg = &lt;0x11400000 0x5000&gt;;</div><div class='add'>+			interrupt-names = "job", "mmu", "gpu";</div><div class='add'>+			interrupts = &lt;GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			clock-names = "core", "bus";</div><div class='add'>+			clocks = &lt;&amp;cmu_g3d CLK_GOUT_G3D_CLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_g3d CLK_GOUT_G3D_ASYNCS_D0_CLK&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_g3d: clock-controller@11460000 {</div><div class='add'>+			compatible = "samsung,exynos7870-cmu-g3d";</div><div class='add'>+			reg = &lt;0x11460000 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clock-names = "oscclk", "switch";</div><div class='add'>+			clocks = &lt;&amp;oscclk&gt;,</div><div class='add'>+				 &lt;&amp;cmu_mif CLK_GOUT_MIF_CMU_G3D_SWITCH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_mfcmscl: clock-controller@12cb0000 {</div><div class='add'>+			compatible = "samsung,exynos7870-cmu-mfcmscl";</div><div class='add'>+			reg = &lt;0x12cb0000 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clock-names = "oscclk", "mfc", "mscl";</div><div class='add'>+			clocks = &lt;&amp;oscclk&gt;,</div><div class='add'>+				 &lt;&amp;cmu_mif CLK_GOUT_MIF_CMU_MFCMSCL_MFC&gt;,</div><div class='add'>+				 &lt;&amp;cmu_mif CLK_GOUT_MIF_CMU_MFCMSCL_MSCL&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmc0: mmc@13540000 {</div><div class='add'>+			compatible = "samsung,exynos7870-dw-mshc-smu";</div><div class='add'>+			reg = &lt;0x13540000 0x2000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			clock-names = "biu", "ciu";</div><div class='add'>+			clocks = &lt;&amp;cmu_fsys CLK_GOUT_FSYS_MMC0_ACLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_mif CLK_GOUT_MIF_CMU_FSYS_MMC0&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmc1: mmc@13550000 {</div><div class='add'>+			compatible = "samsung,exynos7870-dw-mshc-smu";</div><div class='add'>+			reg = &lt;0x13550000 0x2000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			clock-names = "biu", "ciu";</div><div class='add'>+			clocks = &lt;&amp;cmu_fsys CLK_GOUT_FSYS_MMC1_ACLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_mif CLK_GOUT_MIF_CMU_FSYS_MMC1&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmc2: mmc@13560000 {</div><div class='add'>+			compatible = "samsung,exynos7870-dw-mshc-smu";</div><div class='add'>+			reg = &lt;0x13560000 0x2000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			clock-names = "biu", "ciu";</div><div class='add'>+			clocks = &lt;&amp;cmu_fsys CLK_GOUT_FSYS_MMC2_ACLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_mif CLK_GOUT_MIF_CMU_FSYS_MMC2&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usbdrd_phy: phy@135c0000 {</div><div class='add'>+			compatible = "samsung,exynos7870-usbdrd-phy";</div><div class='add'>+			reg = &lt;0x135c0000 0x100&gt;;</div><div class='add'>+			#phy-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clock-names = "phy", "ref";</div><div class='add'>+			clocks = &lt;&amp;cmu_fsys CLK_GOUT_FSYS_MUX_USB20DRD_PHYCLOCK_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_fsys CLK_GOUT_FSYS_MUX_USB_PLL&gt;;</div><div class='add'>+</div><div class='add'>+			samsung,pmu-syscon = &lt;&amp;pmu_system_controller&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usbdrd: usb@13600000 {</div><div class='add'>+			compatible = "samsung,exynos7870-dwusb3";</div><div class='add'>+			ranges = &lt;0x0 0x13600000 0x10000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clock-names = "bus_early", "ref", "ctrl";</div><div class='add'>+			clocks = &lt;&amp;cmu_fsys CLK_GOUT_FSYS_USB20DRD_ACLK_HSDRD&gt;,</div><div class='add'>+				 &lt;&amp;cmu_fsys CLK_GOUT_FSYS_USB20DRD_HSDRD_REF_CLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_fsys CLK_GOUT_FSYS_USB20DRD_HCLK_USB20_CTRL&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			usb@0 {</div><div class='add'>+				compatible = "snps,dwc3";</div><div class='add'>+				reg = &lt;0x0 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				phy-names = "usb2-phy";</div><div class='add'>+				phys = &lt;&amp;usbdrd_phy 0&gt;;</div><div class='add'>+</div><div class='add'>+				usb-role-switch;</div><div class='add'>+				snps,usb2-gadget-lpm-disable;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_fsys: clock-controller@13730000 {</div><div class='add'>+			compatible = "samsung,exynos7870-cmu-fsys";</div><div class='add'>+			reg = &lt;0x13730000 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clock-names = "oscclk", "bus", "usb20drd";</div><div class='add'>+			clocks = &lt;&amp;oscclk&gt;,</div><div class='add'>+				 &lt;&amp;cmu_mif CLK_GOUT_MIF_CMU_FSYS_BUS&gt;,</div><div class='add'>+				 &lt;&amp;cmu_mif CLK_GOUT_MIF_CMU_FSYS_USB20DRD_REFCLK&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_fsys: pinctrl@13750000 {</div><div class='add'>+			compatible = "samsung,exynos7870-pinctrl";</div><div class='add'>+			reg = &lt;0x13750000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		serial0: serial@13800000 {</div><div class='add'>+			compatible = "samsung,exynos7870-uart",</div><div class='add'>+				     "samsung,exynos8895-uart";</div><div class='add'>+			reg = &lt;0x13800000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;uart0_bus&gt;;</div><div class='add'>+</div><div class='add'>+			clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+			clocks = &lt;&amp;cmu_peri CLK_GOUT_PERI_UART0_PCLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peri CLK_GOUT_PERI_UART0_EXT_UCLK&gt;;</div><div class='add'>+</div><div class='add'>+			samsung,uart-fifosize = &lt;16&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		serial1: serial@13810000 {</div><div class='add'>+			compatible = "samsung,exynos7870-uart",</div><div class='add'>+				     "samsung,exynos8895-uart";</div><div class='add'>+			reg = &lt;0x13810000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;uart1_bus&gt;;</div><div class='add'>+</div><div class='add'>+			clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+			clocks = &lt;&amp;cmu_peri CLK_GOUT_PERI_UART1_PCLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peri CLK_GOUT_PERI_UART1_EXT_UCLK&gt;;</div><div class='add'>+</div><div class='add'>+			samsung,uart-fifosize = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		serial2: serial@13820000 {</div><div class='add'>+			compatible = "samsung,exynos7870-uart",</div><div class='add'>+				     "samsung,exynos8895-uart";</div><div class='add'>+			reg = &lt;0x13820000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;uart2_bus&gt;;</div><div class='add'>+</div><div class='add'>+			clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+			clocks = &lt;&amp;cmu_peri CLK_GOUT_PERI_UART2_PCLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peri CLK_GOUT_PERI_UART2_EXT_UCLK&gt;;</div><div class='add'>+</div><div class='add'>+			samsung,uart-fifosize = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c0: i2c@13830000 {</div><div class='add'>+			compatible = "samsung,exynos7870-i2c",</div><div class='add'>+				     "samsung,s3c2440-i2c";</div><div class='add'>+			reg = &lt;0x13830000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c0_bus&gt;;</div><div class='add'>+</div><div class='add'>+			clock-names = "i2c";</div><div class='add'>+			clocks = &lt;&amp;cmu_peri CLK_GOUT_PERI_I2C0_PCLK&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c1: i2c@13840000 {</div><div class='add'>+			compatible = "samsung,exynos7870-i2c",</div><div class='add'>+				     "samsung,s3c2440-i2c";</div><div class='add'>+			reg = &lt;0x13840000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c1_bus&gt;;</div><div class='add'>+</div><div class='add'>+			clock-names = "i2c";</div><div class='add'>+			clocks = &lt;&amp;cmu_peri CLK_GOUT_PERI_I2C1_PCLK&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c2: i2c@13850000 {</div><div class='add'>+			compatible = "samsung,exynos7870-i2c",</div><div class='add'>+				     "samsung,s3c2440-i2c";</div><div class='add'>+			reg = &lt;0x13850000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c2_bus&gt;;</div><div class='add'>+</div><div class='add'>+			clock-names = "i2c";</div><div class='add'>+			clocks = &lt;&amp;cmu_peri CLK_GOUT_PERI_I2C2_PCLK&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c3: i2c@13860000 {</div><div class='add'>+			compatible = "samsung,exynos7870-i2c",</div><div class='add'>+				     "samsung,s3c2440-i2c";</div><div class='add'>+			reg = &lt;0x13860000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c3_bus&gt;;</div><div class='add'>+</div><div class='add'>+			clock-names = "i2c";</div><div class='add'>+			clocks = &lt;&amp;cmu_peri CLK_GOUT_PERI_I2C3_PCLK&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c4: i2c@13870000 {</div><div class='add'>+			compatible = "samsung,exynos7870-i2c",</div><div class='add'>+				     "samsung,s3c2440-i2c";</div><div class='add'>+			reg = &lt;0x13870000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c4_bus&gt;;</div><div class='add'>+</div><div class='add'>+			clock-names = "i2c";</div><div class='add'>+			clocks = &lt;&amp;cmu_peri CLK_GOUT_PERI_I2C4_PCLK&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c5: i2c@13880000 {</div><div class='add'>+			compatible = "samsung,exynos7870-i2c",</div><div class='add'>+				     "samsung,s3c2440-i2c";</div><div class='add'>+			reg = &lt;0x13880000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c5_bus&gt;;</div><div class='add'>+</div><div class='add'>+			clock-names = "i2c";</div><div class='add'>+			clocks = &lt;&amp;cmu_peri CLK_GOUT_PERI_I2C5_PCLK&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c6: i2c@13890000 {</div><div class='add'>+			compatible = "samsung,exynos7870-i2c",</div><div class='add'>+				     "samsung,s3c2440-i2c";</div><div class='add'>+			reg = &lt;0x13890000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c6_bus&gt;;</div><div class='add'>+</div><div class='add'>+			clock-names = "i2c";</div><div class='add'>+			clocks = &lt;&amp;cmu_peri CLK_GOUT_PERI_I2C6_PCLK&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		hsi2c1: i2c@138a0000 {</div><div class='add'>+			compatible = "samsung,exynos7870-hsi2c",</div><div class='add'>+				     "samsung,exynos7-hsi2c";</div><div class='add'>+			reg = &lt;0x138a0000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;hsi2c1_bus&gt;;</div><div class='add'>+</div><div class='add'>+			clock-names = "hsi2c";</div><div class='add'>+			clocks = &lt;&amp;cmu_peri CLK_GOUT_PERI_HSI2C1_IPCLK&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		hsi2c2: i2c@138b0000 {</div><div class='add'>+			compatible = "samsung,exynos7870-hsi2c",</div><div class='add'>+				     "samsung,exynos7-hsi2c";</div><div class='add'>+			reg = &lt;0x138b0000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;hsi2c2_bus&gt;;</div><div class='add'>+</div><div class='add'>+			clock-names = "hsi2c";</div><div class='add'>+			clocks = &lt;&amp;cmu_peri CLK_GOUT_PERI_HSI2C2_IPCLK&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		hsi2c3: i2c@138c0000 {</div><div class='add'>+			compatible = "samsung,exynos7870-hsi2c",</div><div class='add'>+				     "samsung,exynos7-hsi2c";</div><div class='add'>+			reg = &lt;0x138c0000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;hsi2c3_bus&gt;;</div><div class='add'>+</div><div class='add'>+			clock-names = "hsi2c";</div><div class='add'>+			clocks = &lt;&amp;cmu_peri CLK_GOUT_PERI_HSI2C3_IPCLK&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c7: i2c@138d0000 {</div><div class='add'>+			compatible = "samsung,exynos7870-i2c",</div><div class='add'>+				     "samsung,s3c2440-i2c";</div><div class='add'>+			reg = &lt;0x138d0000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c7_bus&gt;;</div><div class='add'>+</div><div class='add'>+			clock-names = "i2c";</div><div class='add'>+			clocks = &lt;&amp;cmu_peri CLK_GOUT_PERI_I2C7_PCLK&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c8: i2c@138e0000 {</div><div class='add'>+			compatible = "samsung,exynos7870-i2c",</div><div class='add'>+				     "samsung,s3c2440-i2c";</div><div class='add'>+			reg = &lt;0x138e0000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c8_bus&gt;;</div><div class='add'>+</div><div class='add'>+			clock-names = "i2c";</div><div class='add'>+			clocks = &lt;&amp;cmu_peri CLK_GOUT_PERI_I2C8_PCLK&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		hsi2c4: i2c@138f0000 {</div><div class='add'>+			compatible = "samsung,exynos7870-hsi2c",</div><div class='add'>+				     "samsung,exynos7-hsi2c";</div><div class='add'>+			reg = &lt;0x138f0000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;hsi2c4_bus&gt;;</div><div class='add'>+</div><div class='add'>+			clock-names = "hsi2c";</div><div class='add'>+			clocks = &lt;&amp;cmu_peri CLK_GOUT_PERI_HSI2C4_IPCLK&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		hsi2c5: i2c@13950000 {</div><div class='add'>+			compatible = "samsung,exynos7870-hsi2c",</div><div class='add'>+				     "samsung,exynos7-hsi2c";</div><div class='add'>+			reg = &lt;0x13950000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;hsi2c5_bus&gt;;</div><div class='add'>+</div><div class='add'>+			clock-names = "hsi2c";</div><div class='add'>+			clocks = &lt;&amp;cmu_peri CLK_GOUT_PERI_HSI2C5_IPCLK&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		hsi2c6: i2c@13960000 {</div><div class='add'>+			compatible = "samsung,exynos7870-hsi2c",</div><div class='add'>+				     "samsung,exynos7-hsi2c";</div><div class='add'>+			reg = &lt;0x13960000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;hsi2c6_bus&gt;;</div><div class='add'>+</div><div class='add'>+			clock-names = "hsi2c";</div><div class='add'>+			clocks = &lt;&amp;cmu_peri CLK_GOUT_PERI_HSI2C6_IPCLK&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_top: pinctrl@139b0000 {</div><div class='add'>+			compatible = "samsung,exynos7870-pinctrl";</div><div class='add'>+			reg = &lt;0x139b0000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_nfc: pinctrl@139c0000 {</div><div class='add'>+			compatible = "samsung,exynos7870-pinctrl";</div><div class='add'>+			reg = &lt;0x139c0000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_touch: pinctrl@139d0000 {</div><div class='add'>+			compatible = "samsung,exynos7870-pinctrl";</div><div class='add'>+			reg = &lt;0x139d0000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_ese: pinctrl@139e0000 {</div><div class='add'>+			compatible = "samsung,exynos7870-pinctrl";</div><div class='add'>+			reg = &lt;0x139e0000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_alive: pinctrl@139f0000 {</div><div class='add'>+			compatible = "samsung,exynos7870-pinctrl";</div><div class='add'>+			reg = &lt;0x139f0000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			wakeup-interrupt-controller {</div><div class='add'>+				compatible = "samsung,exynos7870-wakeup-eint",</div><div class='add'>+					     "samsung,exynos7-wakeup-eint";</div><div class='add'>+				interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_isp: clock-controller@144d0000 {</div><div class='add'>+			compatible = "samsung,exynos7870-cmu-isp";</div><div class='add'>+			reg = &lt;0x144d0000 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clock-names = "oscclk", "cam", "isp", "vra";</div><div class='add'>+			clocks = &lt;&amp;oscclk&gt;,</div><div class='add'>+				 &lt;&amp;cmu_mif CLK_GOUT_MIF_CMU_ISP_CAM&gt;,</div><div class='add'>+				 &lt;&amp;cmu_mif CLK_GOUT_MIF_CMU_ISP_ISP&gt;,</div><div class='add'>+				 &lt;&amp;cmu_mif CLK_GOUT_MIF_CMU_ISP_VRA&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		syscon_cam0: system-controller@144f1040 {</div><div class='add'>+			compatible = "samsung,exynos7870-cam0-sysreg", "syscon";</div><div class='add'>+			reg = &lt;0x144f1040 0x04&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dsi: dsi@14800000 {</div><div class='add'>+			compatible = "samsung,exynos7870-mipi-dsi";</div><div class='add'>+			reg = &lt;0x14800000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;cmu_dispaud CLK_GOUT_DISPAUD_BUS_DISP&gt;,</div><div class='add'>+				 &lt;&amp;cmu_dispaud CLK_GOUT_DISPAUD_APB_DISP&gt;,</div><div class='add'>+				 &lt;&amp;cmu_dispaud CLK_GOUT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_dispaud CLK_GOUT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER&gt;;</div><div class='add'>+			clock-names = "bus", "pll", "byte", "esc";</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;mipi_phy 1&gt;;</div><div class='add'>+			phy-names = "dsim";</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					dsi_to_decon: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;decon_to_dsi&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		decon: display-controller@14830000 {</div><div class='add'>+			compatible = "samsung,exynos7870-decon";</div><div class='add'>+			reg = &lt;0x14830000 0x8000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "fifo", "vsync", "lcd_sys";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;cmu_dispaud CLK_GOUT_DISPAUD_MUX_PLL&gt;,</div><div class='add'>+				 &lt;&amp;cmu_dispaud CLK_GOUT_DISPAUD_MUX_BUS_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_dispaud CLK_GOUT_DISPAUD_MUX_DECON_ECLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_dispaud CLK_GOUT_DISPAUD_MUX_DECON_VCLK&gt;;</div><div class='add'>+			clock-names = "pclk_decon0", "aclk_decon0",</div><div class='add'>+				      "decon0_eclk", "decon0_vclk";</div><div class='add'>+</div><div class='add'>+			iommus = &lt;&amp;sysmmu_decon&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			port {</div><div class='add'>+				decon_to_dsi: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;dsi_to_decon&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sysmmu_decon: iommu@14860000 {</div><div class='add'>+			compatible = "samsung,exynos-sysmmu";</div><div class='add'>+			reg = &lt;0x14860000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#iommu-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;cmu_dispaud CLK_GOUT_DISPAUD_MUX_BUS_USER&gt;;</div><div class='add'>+			clock-names = "sysmmu";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_dispaud: pinctrl@148c0000 {</div><div class='add'>+			compatible = "samsung,exynos7870-pinctrl";</div><div class='add'>+			reg = &lt;0x148c0000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_dispaud: clock-controller@148d0000 {</div><div class='add'>+			compatible = "samsung,exynos7870-cmu-dispaud";</div><div class='add'>+			reg = &lt;0x148d0000 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clock-names = "oscclk", "bus", "decon_eclk", "decon_vclk";</div><div class='add'>+			clocks = &lt;&amp;oscclk&gt;,</div><div class='add'>+				 &lt;&amp;cmu_mif CLK_GOUT_MIF_CMU_DISPAUD_BUS&gt;,</div><div class='add'>+				 &lt;&amp;cmu_mif CLK_GOUT_MIF_CMU_DISPAUD_DECON_ECLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_mif CLK_GOUT_MIF_CMU_DISPAUD_DECON_VCLK&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		syscon_disp: system-controller@148f100c {</div><div class='add'>+			compatible = "samsung,exynos7870-disp-sysreg", "syscon";</div><div class='add'>+			reg = &lt;0x148f100c 0x04&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Non-updatable, broken stock Samsung bootloader does not</div><div class='add'>+		 * configure CNTFRQ_EL0</div><div class='add'>+		 */</div><div class='add'>+		clock-frequency = &lt;26000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include "exynos7870-pinctrl.dtsi"</div><div class='add'>+#include "arm/samsung/exynos-syscon-restart.dtsi"</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts b/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts<br/>new file mode 100644<br/>index 000000000000..9d74fa6bfed9<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts</a></div><div class='hunk'>@@ -0,0 +1,113 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Samsung Galaxy A8 2018 (jackpotlte/SM-A530F) device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2021 Samsung Electronics Co., Ltd.</div><div class='add'>+ * Copyright (c) 2021 Dávid Virág</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "exynos7885.dtsi"</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Samsung Galaxy A8 (2018)";</div><div class='add'>+	compatible = "samsung,jackpotlte", "samsung,exynos7885";</div><div class='add'>+	chassis-type = "handset";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		mmc0 = &amp;mmc_0;</div><div class='add'>+		serial0 = &amp;serial_0;</div><div class='add'>+		serial1 = &amp;serial_1;</div><div class='add'>+		serial2 = &amp;serial_2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;serial_2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@80000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x80000000 0x3da00000&gt;,</div><div class='add'>+		      &lt;0x0 0xc0000000 0x40000000&gt;,</div><div class='add'>+		      &lt;0x8 0x80000000 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;key_volup &amp;key_voldown &amp;key_power&gt;;</div><div class='add'>+</div><div class='add'>+		volup-key {</div><div class='add'>+			label = "Volume Up";</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpa1 5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		voldown-key {</div><div class='add'>+			label = "Volume Down";</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpa1 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		power-key {</div><div class='add'>+			label = "Power";</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpa1 7 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	mmc-hs400-1_8v;</div><div class='add'>+	cap-mmc-highspeed;</div><div class='add'>+	non-removable;</div><div class='add'>+	mmc-hs400-enhanced-strobe;</div><div class='add'>+	card-detect-delay = &lt;200&gt;;</div><div class='add'>+	clock-frequency = &lt;800000000&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	samsung,dw-mshc-ciu-div = &lt;3&gt;;</div><div class='add'>+	samsung,dw-mshc-sdr-timing = &lt;0 4&gt;;</div><div class='add'>+	samsung,dw-mshc-ddr-timing = &lt;2 4&gt;;</div><div class='add'>+	samsung,dw-mshc-hs400-timing = &lt;0 2&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;sd0_clk_fast_slew_rate_3x &amp;sd0_cmd &amp;sd0_rdqs</div><div class='add'>+		     &amp;sd0_bus1 &amp;sd0_bus4 &amp;sd0_bus8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;oscclk {</div><div class='add'>+	clock-frequency = &lt;26000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_alive {</div><div class='add'>+	key_volup: key-volup-pins {</div><div class='add'>+		samsung,pins = "gpa1-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_F&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	key_voldown: key-voldown-pins {</div><div class='add'>+		samsung,pins = "gpa1-6";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_F&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	key_power: key-power-pins {</div><div class='add'>+		samsung,pins = "gpa1-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_F&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;serial_2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi<br/>new file mode 100644<br/>index 000000000000..34bb12191955<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi</a></div><div class='hunk'>@@ -0,0 +1,855 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Samsung Exynos7885 SoC pin-mux and pin-config device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2017 Samsung Electronics Co., Ltd.</div><div class='add'>+ * Copyright (c) 2021 Dávid Virág</div><div class='add'>+ *</div><div class='add'>+ * Samsung's Exynos7885 SoC pin-mux and pin-config options are listed as</div><div class='add'>+ * device tree nodes in this file.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include "exynos-pinctrl.h"</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_alive {</div><div class='add'>+	etc0: etc0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	etc1: etc1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpa0: gpa0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpa1: gpa1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpa2: gpa2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpq0: gpq0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sim1_det_gpio: sim1-det-gpio-pins {</div><div class='add'>+		samsung,pins = "gpa2-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_F&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sim0_det_gpio: sim0-det-gpio-pins {</div><div class='add'>+		samsung,pins = "gpa2-6";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_F&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	speedy_bus: speedy-bus-pins {</div><div class='add'>+		samsung,pins = "gpq0-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* UART_DEBUG */</div><div class='add'>+	uart2_bus: uart2-bus-pins {</div><div class='add'>+		samsung,pins = "gpq0-4", "gpq0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_dispaud {</div><div class='add'>+	gpb0: gpb0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpb1: gpb1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpb2: gpb2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_codec_mclk: aud-codec-mclk-pins {</div><div class='add'>+		samsung,pins = "gpb0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_codec_mclk_idle: aud-codec-mclk-idle-pins {</div><div class='add'>+		samsung,pins = "gpb0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_codec_bus: aud-codec-bus-pins {</div><div class='add'>+		samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_codec_bus_idle: aud-codec-bus-idle-pins {</div><div class='add'>+		samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_loopback_bus: aud-loopback-bus-pins {</div><div class='add'>+		samsung,pins = "gpb1-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_loopback_bus_idle: aud-loopback-bus-idle-pins {</div><div class='add'>+		samsung,pins = "gpb1-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_fm_bus: aud-fm-bus-pins {</div><div class='add'>+		samsung,pins = "gpb1-1", "gpb1-2", "gpb1-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_fm_bus_idle: aud-fm-bus-idle-pins {</div><div class='add'>+		samsung,pins = "gpb1-1", "gpb1-2", "gpb1-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_spk_bus: aud-spk-bus-pins {</div><div class='add'>+		samsung,pins = "gpb2-0", "gpb2-1", "gpb2-2", "gpb2-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_spk_bus_idle: aud-spk-bus-idle-pins {</div><div class='add'>+		samsung,pins = "gpb2-0", "gpb2-1", "gpb2-2", "gpb2-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_fsys {</div><div class='add'>+	gpf0: gpf0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpf2: gpf2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpf3: gpf3-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpf4: gpf4-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd0_clk: sd0-clk-pins {</div><div class='add'>+		samsung,pins = "gpf0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd0_clk_fast_slew_rate_1x: sd0-clk-fast-slew-rate-1x-pins {</div><div class='add'>+		samsung,pins = "gpf0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd0_clk_fast_slew_rate_2x: sd0-clk-fast-slew-rate-2x-pins {</div><div class='add'>+		samsung,pins = "gpf0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd0_clk_fast_slew_rate_3x: sd0-clk-fast-slew-rate-3x-pins {</div><div class='add'>+		samsung,pins = "gpf0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd0_clk_fast_slew_rate_4x: sd0-clk-fast-slew-rate-4x-pins {</div><div class='add'>+		samsung,pins = "gpf0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd0_cmd: sd0-cmd-pins {</div><div class='add'>+		samsung,pins = "gpf0-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd0_rdqs: sd0-rdqs-pins {</div><div class='add'>+		samsung,pins = "gpf0-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd0_bus1: sd0-bus-width1-pins {</div><div class='add'>+		samsung,pins = "gpf2-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd0_bus4: sd0-bus-width4-pins {</div><div class='add'>+		samsung,pins = "gpf2-1", "gpf2-2", "gpf2-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd0_bus8: sd0-bus-width8-pins {</div><div class='add'>+		samsung,pins = "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd1_clk: sd1-clk-pins {</div><div class='add'>+		samsung,pins = "gpf3-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd1_clk_fast_slew_rate_1x: sd1-clk-fast-slew-rate-1x-pins {</div><div class='add'>+		samsung,pins = "gpf3-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd1_clk_fast_slew_rate_2x: sd1-clk-fast-slew-rate-2x-pins {</div><div class='add'>+		samsung,pins = "gpf3-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd1_clk_fast_slew_rate_3x: sd1-clk-fast-slew-rate-3x-pins {</div><div class='add'>+		samsung,pins = "gpf3-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd1_clk_fast_slew_rate_4x: sd1-clk-fast-slew-rate-4x-pins {</div><div class='add'>+		samsung,pins = "gpf3-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd1_cmd: sd1-cmd-pins {</div><div class='add'>+		samsung,pins = "gpf3-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd1_bus1: sd1-bus-width1-pins {</div><div class='add'>+		samsung,pins = "gpf3-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd1_bus4: sd1-bus-width4-pins {</div><div class='add'>+		samsung,pins = "gpf3-3", "gpf3-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_clk: sd2-clk-pins {</div><div class='add'>+		samsung,pins = "gpf4-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_clk_fast_slew_rate_1x: sd2-clk-fast-slew-rate-1x-pins {</div><div class='add'>+		samsung,pins = "gpf4-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_clk_fast_slew_rate_2x: sd2-clk-fast-slew-rate-2x-pins {</div><div class='add'>+		samsung,pins = "gpf4-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_clk_fast_slew_rate_3x: sd2-clk-fast-slew-rate-3x-pins {</div><div class='add'>+		samsung,pins = "gpf4-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_clk_fast_slew_rate_4x: sd2-clk-fast-slew-rate-4x-pins {</div><div class='add'>+		samsung,pins = "gpf4-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_cmd: sd2-cmd-pins {</div><div class='add'>+		samsung,pins = "gpf4-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_bus1: sd2-bus-width1-pins {</div><div class='add'>+		samsung,pins = "gpf4-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_bus4: sd2-bus-width4-pins {</div><div class='add'>+		samsung,pins = "gpf4-3", "gpf4-4", "gpf4-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_top {</div><div class='add'>+	gpc0: gpc0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpc1: gpc1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpc2: gpc2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpg0: gpg0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpg1: gpg1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpg2: gpg2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpg3: gpg3-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpg4: gpg4-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp0: gpp0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp1: gpp1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp2: gpp2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp3: gpp3-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp4: gpp4-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp5: gpp5-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp6: gpp6-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp7: gpp7-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp8: gpp8-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hs_i2c0_bus: hs-i2c0-bus-pins {</div><div class='add'>+		samsung,pins = "gpc1-1", "gpc1-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_OUT1&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hs_i2c1_bus: hs-i2c1-bus-pins {</div><div class='add'>+		samsung,pins = "gpc1-3", "gpc1-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_OUT1&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hs_i2c2_bus: hs-i2c2-bus-pins {</div><div class='add'>+		samsung,pins = "gpc1-5", "gpc1-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_OUT1&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hs_i2c3_bus: hs-i2c3-bus-pins {</div><div class='add'>+		samsung,pins = "gpc1-7", "gpc1-6";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_OUT1&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USI0 UART */</div><div class='add'>+	uart3_bus_single: uart3-bus-single-pins {</div><div class='add'>+		samsung,pins = "gpc2-3", "gpc2-2", "gpc2-1", "gpc2-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USI0 UART_HSI2C1 */</div><div class='add'>+	uart3_bus_dual: uart3-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpc2-1", "gpc2-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USI0 HSI2C0 */</div><div class='add'>+	hs_i2c4_bus: hs-i2c4-bus-pins {</div><div class='add'>+		samsung,pins = "gpc2-1", "gpc2-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_OUT1&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USI0 HSI2C1 */</div><div class='add'>+	hs_i2c5_bus: hs-i2c5-bus-pins {</div><div class='add'>+		samsung,pins = "gpc2-3", "gpc2-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_OUT1&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USI0 SPI */</div><div class='add'>+	spi2_bus: spi2-bus-pins {</div><div class='add'>+		samsung,pins = "gpc2-1", "gpc2-0", "gpc2-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi2_cs: spi2-cs-pins {</div><div class='add'>+		samsung,pins = "gpc2-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USI1 UART */</div><div class='add'>+	uart4_bus_single: uart4-bus-single-pins {</div><div class='add'>+		samsung,pins = "gpc2-7", "gpc2-6", "gpc2-5", "gpc2-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USI1 UART_HSI2C1*/</div><div class='add'>+	uart4_bus_dual: uart4-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpc2-5", "gpc2-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USI1 HSI2C0 */</div><div class='add'>+	hs_i2c6_bus: hs-i2c6-bus-pins {</div><div class='add'>+		samsung,pins = "gpc2-5", "gpc2-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_OUT1&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USI1 HSI2C1 */</div><div class='add'>+	hs_i2c7_bus: hs-i2c7-bus-pins {</div><div class='add'>+		samsung,pins = "gpc2-7", "gpc2-6";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_OUT1&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USI1 SPI */</div><div class='add'>+	spi3_bus: spi3-bus-pins {</div><div class='add'>+		samsung,pins = "gpc2-5", "gpc2-4", "gpc2-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi3_cs: spi3-cs-pins {</div><div class='add'>+		samsung,pins = "gpc2-6";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fm_lna_en: fm-lna-en-pins {</div><div class='add'>+		samsung,pins = "gpg0-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-val = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart1_bus: uart1-bus-pins {</div><div class='add'>+		samsung,pins = "gpg1-3", "gpg1-2", "gpg1-1", "gpg1-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c7_bus: i2c7-bus-pins {</div><div class='add'>+		samsung,pins = "gpg1-5", "gpg1-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_dmic_on: aud-dmic-on-pins {</div><div class='add'>+		samsung,pins = "gpg2-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-val = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_dmic_off: aud-dmic-off-pins {</div><div class='add'>+		samsung,pins = "gpg2-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-val = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* UART_HEALTH */</div><div class='add'>+	uart0_bus: uart0-bus-pins {</div><div class='add'>+		samsung,pins = "gpp0-3", "gpp0-2", "gpp0-1", "gpp0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c0_bus: i2c0-bus-pins {</div><div class='add'>+		samsung,pins = "gpp1-1", "gpp1-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c1_bus: i2c1-bus-pins {</div><div class='add'>+		samsung,pins = "gpp1-3", "gpp1-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c2_bus: i2c2-bus-pins {</div><div class='add'>+		samsung,pins = "gpp2-1", "gpp2-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c3_bus: i2c3-bus-pins {</div><div class='add'>+		samsung,pins = "gpp3-1", "gpp3-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c4_bus: i2c4-bus-pins {</div><div class='add'>+		samsung,pins = "gpp4-1", "gpp4-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c5_bus: i2c5-bus-pins {</div><div class='add'>+		samsung,pins = "gpp4-3", "gpp4-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c6_bus: i2c6-bus-pins {</div><div class='add'>+		samsung,pins = "gpp4-5", "gpp4-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SPI_ESE */</div><div class='add'>+	spi0_bus: spi0-bus-pins {</div><div class='add'>+		samsung,pins = "gpp5-3", "gpp5-2", "gpp5-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi0_cs: spi0-cs-pins {</div><div class='add'>+		samsung,pins = "gpp5-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SPI_FP */</div><div class='add'>+	spi1_bus: spi1-bus-pins {</div><div class='add'>+		samsung,pins = "gpp6-3", "gpp6-2", "gpp6-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi1_cs: spi1-cs-pins {</div><div class='add'>+		samsung,pins = "gpp6-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USI2 UART */</div><div class='add'>+	uart5_bus_single: uart5-bus-single-pins {</div><div class='add'>+		samsung,pins = "gpp8-1", "gpp8-0", "gpp7-1", "gpp7-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	  };</div><div class='add'>+</div><div class='add'>+	/* USI2 UART_HSI2C1 */</div><div class='add'>+	uart5_bus_dual: uart5-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp7-1", "gpp7-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USI2 HSI2C0 */</div><div class='add'>+	hs_i2c8_bus: hs-i2c8-bus-pins {</div><div class='add'>+		samsung,pins = "gpp7-1", "gpp7-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_OUT1&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USI2 HSI2C1 */</div><div class='add'>+	hs_i2c9_bus: hs-i2c9-bus-pins {</div><div class='add'>+		samsung,pins = "gpp8-1", "gpp8-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_OUT1&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USI2 SPI */</div><div class='add'>+	spi4_bus: spi4-bus-pins {</div><div class='add'>+		samsung,pins = "gpp7-1", "gpp7-0", "gpp8-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi4_cs: spi4-cs-pins {</div><div class='add'>+		samsung,pins = "gpp8-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/exynos7885.dtsi b/arch/arm64/boot/dts/exynos/exynos7885.dtsi<br/>new file mode 100644<br/>index 000000000000..008228fb319a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynos7885.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/exynos7885.dtsi</a></div><div class='hunk'>@@ -0,0 +1,470 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Samsung Exynos7885 SoC device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2021 Samsung Electronics Co., Ltd.</div><div class='add'>+ * Copyright (c) 2021 Dávid Virág</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/exynos7885.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "samsung,exynos7885";</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		pinctrl0 = &amp;pinctrl_alive;</div><div class='add'>+		pinctrl1 = &amp;pinctrl_dispaud;</div><div class='add'>+		pinctrl2 = &amp;pinctrl_fsys;</div><div class='add'>+		pinctrl3 = &amp;pinctrl_top;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	arm-a53-pmu {</div><div class='add'>+		compatible = "arm,cortex-a53-pmu";</div><div class='add'>+		interrupts = &lt;GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-affinity = &lt;&amp;cpu0&gt;,</div><div class='add'>+				     &lt;&amp;cpu1&gt;,</div><div class='add'>+				     &lt;&amp;cpu2&gt;,</div><div class='add'>+				     &lt;&amp;cpu3&gt;,</div><div class='add'>+				     &lt;&amp;cpu4&gt;,</div><div class='add'>+				     &lt;&amp;cpu5&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	arm-a73-pmu {</div><div class='add'>+		compatible = "arm,cortex-a73-pmu";</div><div class='add'>+		interrupts = &lt;GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-affinity = &lt;&amp;cpu6&gt;,</div><div class='add'>+				     &lt;&amp;cpu7&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu-map {</div><div class='add'>+			cluster0 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu0&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu1&gt;;</div><div class='add'>+				};</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu2&gt;;</div><div class='add'>+				};</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu3&gt;;</div><div class='add'>+				};</div><div class='add'>+				core4 {</div><div class='add'>+					cpu = &lt;&amp;cpu4&gt;;</div><div class='add'>+				};</div><div class='add'>+				core5 {</div><div class='add'>+					cpu = &lt;&amp;cpu5&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cluster1 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu6&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu7&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@100 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x100&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@101 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x101&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@102 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x102&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@103 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x103&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu4: cpu@200 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x200&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu5: cpu@201 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x201&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu6: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a73";</div><div class='add'>+			reg = &lt;0x0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu7: cpu@1 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a73";</div><div class='add'>+			reg = &lt;0x1&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci";</div><div class='add'>+		method = "smc";</div><div class='add'>+		cpu_suspend = &lt;0xc4000001&gt;;</div><div class='add'>+		cpu_off = &lt;0x84000002&gt;;</div><div class='add'>+		cpu_on = &lt;0xc4000003&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		/* Hypervisor Virtual Timer interrupt is not wired to GIC */</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fixed-rate-clocks {</div><div class='add'>+		oscclk: osc-clock {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-output-names = "oscclk";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc: soc@0 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges = &lt;0x0 0x0 0x0 0x20000000&gt;;</div><div class='add'>+</div><div class='add'>+		chipid@10000000 {</div><div class='add'>+			compatible = "samsung,exynos7885-chipid",</div><div class='add'>+				     "samsung,exynos850-chipid";</div><div class='add'>+			reg = &lt;0x10000000 0x24&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@12301000 {</div><div class='add'>+			compatible = "arm,gic-400";</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			#address-cells = &lt;0&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			reg = &lt;0x12301000 0x1000&gt;,</div><div class='add'>+			      &lt;0x12302000 0x2000&gt;,</div><div class='add'>+			      &lt;0x12304000 0x2000&gt;,</div><div class='add'>+			      &lt;0x12306000 0x2000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |</div><div class='add'>+						 IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_peri: clock-controller@10010000 {</div><div class='add'>+			compatible = "samsung,exynos7885-cmu-peri";</div><div class='add'>+			reg = &lt;0x10010000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;oscclk&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_PERI_BUS&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_PERI_SPI0&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_PERI_SPI1&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_PERI_UART0&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_PERI_UART1&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_PERI_UART2&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_PERI_USI0&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_PERI_USI1&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_PERI_USI2&gt;;</div><div class='add'>+			clock-names = "oscclk",</div><div class='add'>+				      "dout_peri_bus",</div><div class='add'>+				      "dout_peri_spi0",</div><div class='add'>+				      "dout_peri_spi1",</div><div class='add'>+				      "dout_peri_uart0",</div><div class='add'>+				      "dout_peri_uart1",</div><div class='add'>+				      "dout_peri_uart2",</div><div class='add'>+				      "dout_peri_usi0",</div><div class='add'>+				      "dout_peri_usi1",</div><div class='add'>+				      "dout_peri_usi2";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_core: clock-controller@12000000 {</div><div class='add'>+			compatible = "samsung,exynos7885-cmu-core";</div><div class='add'>+			reg = &lt;0x12000000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;oscclk&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CORE_BUS&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CORE_CCI&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CORE_G3D&gt;;</div><div class='add'>+			clock-names = "oscclk",</div><div class='add'>+				      "dout_core_bus",</div><div class='add'>+				      "dout_core_cci",</div><div class='add'>+				      "dout_core_g3d";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_top: clock-controller@12060000 {</div><div class='add'>+			compatible = "samsung,exynos7885-cmu-top";</div><div class='add'>+			reg = &lt;0x12060000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;oscclk&gt;;</div><div class='add'>+			clock-names = "oscclk";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_fsys: clock-controller@13400000 {</div><div class='add'>+			compatible = "samsung,exynos7885-cmu-fsys";</div><div class='add'>+			reg = &lt;0x13400000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;oscclk&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_FSYS_BUS&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_FSYS_MMC_CARD&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_FSYS_MMC_EMBD&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_FSYS_MMC_SDIO&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_FSYS_USB30DRD&gt;;</div><div class='add'>+			clock-names = "oscclk",</div><div class='add'>+				      "dout_fsys_bus",</div><div class='add'>+				      "dout_fsys_mmc_card",</div><div class='add'>+				      "dout_fsys_mmc_embd",</div><div class='add'>+				      "dout_fsys_mmc_sdio",</div><div class='add'>+				      "dout_fsys_usb30drd";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_alive: pinctrl@11cb0000 {</div><div class='add'>+			compatible = "samsung,exynos7885-pinctrl";</div><div class='add'>+			reg = &lt;0x11cb0000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			wakeup-interrupt-controller {</div><div class='add'>+				compatible = "samsung,exynos7885-wakeup-eint",</div><div class='add'>+					     "samsung,exynos7-wakeup-eint";</div><div class='add'>+				interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_fsys: pinctrl@13430000 {</div><div class='add'>+			compatible = "samsung,exynos7885-pinctrl";</div><div class='add'>+			reg = &lt;0x13430000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_top: pinctrl@139b0000 {</div><div class='add'>+			compatible = "samsung,exynos7885-pinctrl";</div><div class='add'>+			reg = &lt;0x139b0000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_dispaud: pinctrl@148f0000 {</div><div class='add'>+			compatible = "samsung,exynos7885-pinctrl";</div><div class='add'>+			reg = &lt;0x148f0000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmu_system_controller: system-controller@11c80000 {</div><div class='add'>+			compatible = "samsung,exynos7885-pmu",</div><div class='add'>+				     "samsung,exynos7-pmu", "syscon";</div><div class='add'>+			reg = &lt;0x11c80000 0x10000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmc_0: mmc@13500000 {</div><div class='add'>+			compatible = "samsung,exynos7885-dw-mshc-smu",</div><div class='add'>+				     "samsung,exynos7-dw-mshc-smu";</div><div class='add'>+			reg = &lt;0x13500000 0x2000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_fsys CLK_GOUT_MMC_EMBD_ACLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_fsys CLK_GOUT_MMC_EMBD_SDCLKIN&gt;;</div><div class='add'>+			clock-names = "biu", "ciu";</div><div class='add'>+			fifo-depth = &lt;0x40&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		serial_0: serial@13800000 {</div><div class='add'>+			compatible = "samsung,exynos7885-uart",</div><div class='add'>+				     "samsung,exynos5433-uart";</div><div class='add'>+			reg = &lt;0x13800000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;uart0_bus&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peri CLK_GOUT_UART0_PCLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peri CLK_GOUT_UART0_EXT_UCLK&gt;;</div><div class='add'>+			clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+			samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		serial_1: serial@13810000 {</div><div class='add'>+			compatible = "samsung,exynos7885-uart",</div><div class='add'>+				     "samsung,exynos5433-uart";</div><div class='add'>+			reg = &lt;0x13810000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;uart1_bus&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peri CLK_GOUT_UART1_PCLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peri CLK_GOUT_UART1_EXT_UCLK&gt;;</div><div class='add'>+			clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+			samsung,uart-fifosize = &lt;256&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		serial_2: serial@13820000 {</div><div class='add'>+			compatible = "samsung,exynos7885-uart",</div><div class='add'>+				     "samsung,exynos5433-uart";</div><div class='add'>+			reg = &lt;0x13820000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;uart2_bus&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peri CLK_GOUT_UART2_PCLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peri CLK_GOUT_UART2_EXT_UCLK&gt;;</div><div class='add'>+			clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+			samsung,uart-fifosize = &lt;256&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c_0: i2c@13830000 {</div><div class='add'>+			compatible = "samsung,exynos7885-i2c",</div><div class='add'>+				     "samsung,s3c2440-i2c";</div><div class='add'>+			reg = &lt;0x13830000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c0_bus&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peri CLK_GOUT_I2C0_PCLK&gt;;</div><div class='add'>+			clock-names = "i2c";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c_1: i2c@13840000 {</div><div class='add'>+			compatible = "samsung,exynos7885-i2c",</div><div class='add'>+				     "samsung,s3c2440-i2c";</div><div class='add'>+			reg = &lt;0x13840000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c1_bus&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peri CLK_GOUT_I2C1_PCLK&gt;;</div><div class='add'>+			clock-names = "i2c";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c_2: i2c@13850000 {</div><div class='add'>+			compatible = "samsung,exynos7885-i2c",</div><div class='add'>+				     "samsung,s3c2440-i2c";</div><div class='add'>+			reg = &lt;0x13850000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c2_bus&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peri CLK_GOUT_I2C2_PCLK&gt;;</div><div class='add'>+			clock-names = "i2c";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c_3: i2c@13860000 {</div><div class='add'>+			compatible = "samsung,exynos7885-i2c",</div><div class='add'>+				     "samsung,s3c2440-i2c";</div><div class='add'>+			reg = &lt;0x13860000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c3_bus&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peri CLK_GOUT_I2C3_PCLK&gt;;</div><div class='add'>+			clock-names = "i2c";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c_4: i2c@13870000 {</div><div class='add'>+			compatible = "samsung,exynos7885-i2c",</div><div class='add'>+				     "samsung,s3c2440-i2c";</div><div class='add'>+			reg = &lt;0x13870000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c4_bus&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peri CLK_GOUT_I2C4_PCLK&gt;;</div><div class='add'>+			clock-names = "i2c";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c_5: i2c@13880000 {</div><div class='add'>+			compatible = "samsung,exynos7885-i2c",</div><div class='add'>+				     "samsung,s3c2440-i2c";</div><div class='add'>+			reg = &lt;0x13880000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c5_bus&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peri CLK_GOUT_I2C5_PCLK&gt;;</div><div class='add'>+			clock-names = "i2c";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c_6: i2c@13890000 {</div><div class='add'>+			compatible = "samsung,exynos7885-i2c",</div><div class='add'>+				     "samsung,s3c2440-i2c";</div><div class='add'>+			reg = &lt;0x13890000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c6_bus&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peri CLK_GOUT_I2C6_PCLK&gt;;</div><div class='add'>+			clock-names = "i2c";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c_7: i2c@11cd0000 {</div><div class='add'>+			compatible = "samsung,exynos7885-i2c",</div><div class='add'>+				     "samsung,s3c2440-i2c";</div><div class='add'>+			reg = &lt;0x11cd0000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c7_bus&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peri CLK_GOUT_I2C7_PCLK&gt;;</div><div class='add'>+			clock-names = "i2c";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include "exynos7885-pinctrl.dtsi"</div><div class='add'>+#include "arm/samsung/exynos-syscon-restart.dtsi"</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts b/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts<br/>new file mode 100644<br/>index 000000000000..ab076d326a49<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/exynos850-e850-96.dts</a></div><div class='hunk'>@@ -0,0 +1,285 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * WinLink E850-96 board device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) 2018 Samsung Electronics Co., Ltd.</div><div class='add'>+ * Copyright (C) 2021 Linaro Ltd.</div><div class='add'>+ *</div><div class='add'>+ * Device tree source file for WinLink's E850-96 board which is based on</div><div class='add'>+ * Samsung Exynos850 SoC.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "exynos850.dtsi"</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "WinLink E850-96 board";</div><div class='add'>+	compatible = "winlink,e850-96", "samsung,exynos850";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;ethernet;</div><div class='add'>+		mmc0 = &amp;mmc_0;</div><div class='add'>+		serial0 = &amp;serial_0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;serial_0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	connector {</div><div class='add'>+		compatible = "gpio-usb-b-connector", "usb-b-connector";</div><div class='add'>+		label = "micro-USB";</div><div class='add'>+		type = "micro";</div><div class='add'>+		vbus-supply = &lt;&amp;reg_usb_host_vbus&gt;;</div><div class='add'>+		id-gpios = &lt;&amp;gpa0 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;micro_usb_det_pins&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			usb_dr_connector: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;usb1_drd_sw&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@80000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x80000000 0x80000000&gt;,</div><div class='add'>+		      &lt;0x8 0x80000000 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;key_voldown_pins &amp;key_volup_pins&gt;;</div><div class='add'>+</div><div class='add'>+		volume-down-key {</div><div class='add'>+			label = "Volume Down";</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpa1 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		volume-up-key {</div><div class='add'>+			label = "Volume Up";</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpa0 7 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		/* HEART_BEAT_LED */</div><div class='add'>+		user_led1: led-1 {</div><div class='add'>+			label = "yellow:user1";</div><div class='add'>+			gpios = &lt;&amp;gpg2 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			color = &lt;LED_COLOR_ID_YELLOW&gt;;</div><div class='add'>+			function = LED_FUNCTION_HEARTBEAT;</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* eMMC_LED */</div><div class='add'>+		user_led2: led-2 {</div><div class='add'>+			label = "yellow:user2";</div><div class='add'>+			gpios = &lt;&amp;gpg2 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			color = &lt;LED_COLOR_ID_YELLOW&gt;;</div><div class='add'>+			linux,default-trigger = "mmc0";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* SD_LED */</div><div class='add'>+		user_led3: led-3 {</div><div class='add'>+			label = "white:user3";</div><div class='add'>+			gpios = &lt;&amp;gpg2 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			color = &lt;LED_COLOR_ID_WHITE&gt;;</div><div class='add'>+			function = LED_FUNCTION_SD;</div><div class='add'>+			linux,default-trigger = "mmc2";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* WIFI_LED */</div><div class='add'>+		wlan_active_led: led-4 {</div><div class='add'>+			label = "yellow:wlan";</div><div class='add'>+			gpios = &lt;&amp;gpg2 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			color = &lt;LED_COLOR_ID_YELLOW&gt;;</div><div class='add'>+			function = LED_FUNCTION_WLAN;</div><div class='add'>+			linux,default-trigger = "phy0tx";</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* BLUETOOTH_LED */</div><div class='add'>+		bt_active_led: led-5 {</div><div class='add'>+			label = "blue:bt";</div><div class='add'>+			gpios = &lt;&amp;gpg2 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			function = LED_FUNCTION_BLUETOOTH;</div><div class='add'>+			linux,default-trigger = "hci0-power";</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* TODO: Remove this once PMIC is implemented  */</div><div class='add'>+	reg_dummy: regulator-0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "dummy_reg";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb_host_vbus: regulator-1 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "usb_host_vbus";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpa3 5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		secure_mem: memory@bab00000 {</div><div class='add'>+			reg = &lt;0x0 0xbab00000 0x5500000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ramoops@f0000000 {</div><div class='add'>+			compatible = "ramoops";</div><div class='add'>+			reg = &lt;0x0 0xf0000000 0x200000&gt;;</div><div class='add'>+			record-size = &lt;0x20000&gt;;</div><div class='add'>+			console-size = &lt;0x20000&gt;;</div><div class='add'>+			ftrace-size = &lt;0x100000&gt;;</div><div class='add'>+			pmsg-size = &lt;0x20000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * RTC clock (XrtcXTI); external, must be 32.768 kHz.</div><div class='add'>+	 *</div><div class='add'>+	 * TODO: Remove this once RTC clock is implemented properly as part of</div><div class='add'>+	 *       PMIC driver.</div><div class='add'>+	 */</div><div class='add'>+	rtcclk: clock-rtcclk {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		clock-output-names = "rtcclk";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;32768&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cmu_hsi {</div><div class='add'>+	clocks = &lt;&amp;oscclk&gt;, &lt;&amp;rtcclk&gt;,</div><div class='add'>+		 &lt;&amp;cmu_top CLK_DOUT_HSI_BUS&gt;,</div><div class='add'>+		 &lt;&amp;cmu_top CLK_DOUT_HSI_MMC_CARD&gt;,</div><div class='add'>+		 &lt;&amp;cmu_top CLK_DOUT_HSI_USB20DRD&gt;;</div><div class='add'>+	clock-names = "oscclk", "rtcclk", "dout_hsi_bus",</div><div class='add'>+		      "dout_hsi_mmc_card", "dout_hsi_usb20drd";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	mmc-hs400-1_8v;</div><div class='add'>+	cap-mmc-highspeed;</div><div class='add'>+	non-removable;</div><div class='add'>+	mmc-hs400-enhanced-strobe;</div><div class='add'>+	card-detect-delay = &lt;200&gt;;</div><div class='add'>+	clock-frequency = &lt;800000000&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	samsung,dw-mshc-ciu-div = &lt;3&gt;;</div><div class='add'>+	samsung,dw-mshc-sdr-timing = &lt;0 4&gt;;</div><div class='add'>+	samsung,dw-mshc-ddr-timing = &lt;2 4&gt;;</div><div class='add'>+	samsung,dw-mshc-hs400-timing = &lt;0 2&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;sd0_clk_pins &amp;sd0_cmd_pins &amp;sd0_rdqs_pins &amp;sd0_nreset_pins</div><div class='add'>+		     &amp;sd0_bus1_pins &amp;sd0_bus4_pins &amp;sd0_bus8_pins&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;oscclk {</div><div class='add'>+	clock-frequency = &lt;26000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_alive {</div><div class='add'>+	key_voldown_pins: key-voldown-pins {</div><div class='add'>+		samsung,pins = "gpa1-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	key_volup_pins: key-volup-pins {</div><div class='add'>+		samsung,pins = "gpa0-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	micro_usb_det_pins: micro-usb-det-pins {</div><div class='add'>+		samsung,pins = "gpa0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;rtc {</div><div class='add'>+	status = "okay";</div><div class='add'>+	clocks = &lt;&amp;cmu_apm CLK_GOUT_RTC_PCLK&gt;, &lt;&amp;rtcclk&gt;;</div><div class='add'>+	clock-names = "rtc", "rtc_src";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;serial_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart1_pins&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbdrd {</div><div class='add'>+	status = "okay";</div><div class='add'>+	vdd10-supply = &lt;&amp;reg_dummy&gt;;</div><div class='add'>+	vdd33-supply = &lt;&amp;reg_dummy&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbdrd_dwc3 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	role-switch-default-mode = "host";</div><div class='add'>+</div><div class='add'>+	hub@1 {</div><div class='add'>+		compatible = "usb424,9514";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethernet: ethernet@1 {</div><div class='add'>+			compatible = "usb424,ec00";</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	port {</div><div class='add'>+		usb1_drd_sw: endpoint {</div><div class='add'>+			remote-endpoint = &lt;&amp;usb_dr_connector&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbdrd_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usi_uart {</div><div class='add'>+	samsung,clkreq-on; /* needed for UART mode */</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;watchdog_cl0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;watchdog_cl1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi<br/>new file mode 100644<br/>index 000000000000..424bc80bde68<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi</a></div><div class='hunk'>@@ -0,0 +1,663 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Samsung's Exynos850 SoC pin-mux and pin-config device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) 2017 Samsung Electronics Co., Ltd.</div><div class='add'>+ * Copyright (C) 2021 Linaro Ltd.</div><div class='add'>+ *</div><div class='add'>+ * Samsung's Exynos850 SoC pin-mux and pin-config options are listed as device</div><div class='add'>+ * tree nodes in this file.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include "exynos-pinctrl.h"</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_alive {</div><div class='add'>+	gpa0: gpa0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpa1: gpa1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpa2: gpa2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpa3: gpa3-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpa4: gpa4-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpq0: gpq0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* I2C5 (also called CAM_PMIC_I2C in TRM) */</div><div class='add'>+	i2c5_pins: i2c5-pins {</div><div class='add'>+		samsung,pins = "gpa3-5", "gpa3-6";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* I2C6 (also called MOTOR_I2C in TRM) */</div><div class='add'>+	i2c6_pins: i2c6-pins {</div><div class='add'>+		samsung,pins = "gpa3-7", "gpa4-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USI: UART_DEBUG_0 pins */</div><div class='add'>+	uart0_pins: uart0-pins {</div><div class='add'>+		samsung,pins = "gpq0-0", "gpq0-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USI: UART_DEBUG_1 pins */</div><div class='add'>+	uart1_pins: uart1-pins {</div><div class='add'>+		samsung,pins = "gpa3-7", "gpa4-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_cmgp {</div><div class='add'>+	gpm0: gpm0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm1: gpm1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm2: gpm2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm3: gpm3-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm4: gpm4-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm5: gpm5-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm6: gpm6-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm7: gpm7-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USI_CMGP0: HSI2C function */</div><div class='add'>+	hsi2c3_pins: hsi2c3-pins {</div><div class='add'>+		samsung,pins = "gpm0-0", "gpm1-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USI_CMGP0: UART function (4 pins, Auto Flow Control) */</div><div class='add'>+	uart1_single_pins: uart1-single-pins {</div><div class='add'>+		samsung,pins = "gpm0-0", "gpm1-0", "gpm2-0", "gpm3-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USI_CMGP0: UART function (2 pins, Non-Auto Flow Control) */</div><div class='add'>+	uart1_dual_pins: uart1-dual-pins {</div><div class='add'>+		samsung,pins = "gpm0-0", "gpm1-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USI_CMGP0: SPI function */</div><div class='add'>+	spi1_pins: spi1-pins {</div><div class='add'>+		samsung,pins = "gpm0-0", "gpm1-0", "gpm2-0", "gpm3-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USI_CMGP1: HSI2C function */</div><div class='add'>+	hsi2c4_pins: hsi2c4-pins {</div><div class='add'>+		samsung,pins = "gpm4-0", "gpm5-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USI_CMGP1: UART function (4 pins, Auto Flow Control) */</div><div class='add'>+	uart2_single_pins: uart2-single-pins {</div><div class='add'>+		samsung,pins = "gpm4-0", "gpm5-0", "gpm6-0", "gpm7-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USI_CMGP1: UART function (2 pins, Non-Auto Flow Control) */</div><div class='add'>+	uart2_dual_pins: uart2-dual-pins {</div><div class='add'>+		samsung,pins = "gpm4-0", "gpm5-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USI_CMGP1: SPI function */</div><div class='add'>+	spi2_pins: spi2-pins {</div><div class='add'>+		samsung,pins = "gpm4-0", "gpm5-0", "gpm6-0", "gpm7-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_aud {</div><div class='add'>+	gpb0: gpb0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpb1: gpb1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_codec_mclk_pins: aud-codec-mclk-pins {</div><div class='add'>+		samsung,pins = "gpb0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_codec_mclk_idle_pins: aud-codec-mclk-idle-pins {</div><div class='add'>+		samsung,pins = "gpb0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_i2s0_pins: aud-i2s0-pins {</div><div class='add'>+		samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_i2s0_idle_pins: aud-i2s0-idle-pins {</div><div class='add'>+		samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_i2s1_pins: aud-i2s1-pins {</div><div class='add'>+		samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_i2s1_idle_pins: aud-i2s1-idle-pins {</div><div class='add'>+		samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_fm_pins: aud-fm-pins {</div><div class='add'>+		samsung,pins = "gpb1-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_fm_idle_pins: aud-fm-idle-pins {</div><div class='add'>+		samsung,pins = "gpb1-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_hsi {</div><div class='add'>+	gpf2: gpf2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_clk_pins: sd2-clk-pins {</div><div class='add'>+		samsung,pins = "gpf2-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS850_HSI_PIN_DRV_LV2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_cmd_pins: sd2-cmd-pins {</div><div class='add'>+		samsung,pins = "gpf2-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS850_HSI_PIN_DRV_LV2&gt;;</div><div class='add'>+	 };</div><div class='add'>+</div><div class='add'>+	sd2_bus1_pins: sd2-bus1-pins {</div><div class='add'>+		samsung,pins = "gpf2-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS850_HSI_PIN_DRV_LV2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_bus4_pins: sd2-bus4-pins {</div><div class='add'>+		samsung,pins = "gpf2-3", "gpf2-4", "gpf2-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS850_HSI_PIN_DRV_LV2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_pdn_pins: sd2-pdn-pins {</div><div class='add'>+		samsung,pins = "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",</div><div class='add'>+			       "gpf2-4", "gpf2-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_core {</div><div class='add'>+	gpf0: gpf0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpf1: gpf1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd0_clk_pins: sd0-clk-pins {</div><div class='add'>+		samsung,pins = "gpf0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd0_cmd_pins: sd0-cmd-pins {</div><div class='add'>+		samsung,pins = "gpf0-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd0_rdqs_pins: sd0-rdqs-pins {</div><div class='add'>+		samsung,pins = "gpf0-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd0_nreset_pins: sd0-nreset-pins {</div><div class='add'>+		samsung,pins = "gpf0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd0_bus1_pins: sd0-bus1-pins {</div><div class='add'>+		samsung,pins = "gpf1-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd0_bus4_pins: sd0-bus4-pins {</div><div class='add'>+		samsung,pins = "gpf1-1", "gpf1-2", "gpf1-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd0_bus8_pins: sd0-bus8-pins {</div><div class='add'>+		samsung,pins = "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV4&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_peri {</div><div class='add'>+	gpc0: gpc0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpc1: gpc1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpg0: gpg0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpg1: gpg1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpg2: gpg2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpg3: gpg3-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp0: gpp0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+	gpp1: gpp1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp2: gpp2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sensor_mclk0_in_pins: sensor-mclk0-in-pins {</div><div class='add'>+		samsung,pins = "gpc0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sensor_mclk0_out_pins: sensor-mclk0-out-pins {</div><div class='add'>+		samsung,pins = "gpc0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sensor_mclk0_fn_pins: sensor-mclk0-fn-pins {</div><div class='add'>+		samsung,pins = "gpc0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sensor_mclk1_in_pins: sensor-mclk1-in-pins {</div><div class='add'>+		samsung,pins = "gpc0-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sensor_mclk1_out_pins: sensor-mclk1-out-pins {</div><div class='add'>+		samsung,pins = "gpc0-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sensor_mclk1_fn_pins: sensor-mclk1-fn-pins {</div><div class='add'>+		samsung,pins = "gpc0-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sensor_mclk2_in_pins: sensor-mclk2-in-pins {</div><div class='add'>+		samsung,pins = "gpc0-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sensor_mclk2_out_pins: sensor-mclk2-out-pins {</div><div class='add'>+		samsung,pins = "gpc0-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sensor_mclk2_fn_pins: sensor-mclk2-fn-pins {</div><div class='add'>+		samsung,pins = "gpc0-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USI: HSI2C0 */</div><div class='add'>+	hsi2c0_pins: hsi2c0-pins {</div><div class='add'>+		samsung,pins = "gpc1-0", "gpc1-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USI: HSI2C1 */</div><div class='add'>+	hsi2c1_pins: hsi2c1-pins {</div><div class='add'>+		samsung,pins = "gpc1-2", "gpc1-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USI: HSI2C2 */</div><div class='add'>+	hsi2c2_pins: hsi2c2-pins {</div><div class='add'>+		samsung,pins = "gpc1-4", "gpc1-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USI: SPI */</div><div class='add'>+	spi0_pins: spi0-pins {</div><div class='add'>+		samsung,pins = "gpp2-0", "gpp2-1", "gpp2-2", "gpp2-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c0_pins: i2c0-pins {</div><div class='add'>+		samsung,pins = "gpp0-0", "gpp0-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c1_pins: i2c1-pins {</div><div class='add'>+		samsung,pins = "gpp0-2", "gpp0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c2_pins: i2c2-pins {</div><div class='add'>+		samsung,pins = "gpp0-4", "gpp0-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c3_pins: i2c3-pins {</div><div class='add'>+		samsung,pins = "gpp1-0", "gpp1-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c4_pins: i2c4-pins {</div><div class='add'>+		samsung,pins = "gpp1-2", "gpp1-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	xclkout_pins: xclkout-pins {</div><div class='add'>+		samsung,pins = "gpq0-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi<br/>new file mode 100644<br/>index 000000000000..cb55015c8dce<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynos850.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/exynos850.dtsi</a></div><div class='hunk'>@@ -0,0 +1,915 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Samsung Exynos850 SoC device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) 2018 Samsung Electronics Co., Ltd.</div><div class='add'>+ * Copyright (C) 2021 Linaro Ltd.</div><div class='add'>+ *</div><div class='add'>+ * Samsung Exynos850 SoC device nodes are listed in this file.</div><div class='add'>+ * Exynos850 based board files can include this file and provide</div><div class='add'>+ * values for board specific bindings.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/exynos850.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/soc/samsung,exynos-usi.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	/* Also known under engineering name Exynos3830 */</div><div class='add'>+	compatible = "samsung,exynos850";</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		pinctrl0 = &amp;pinctrl_alive;</div><div class='add'>+		pinctrl1 = &amp;pinctrl_cmgp;</div><div class='add'>+		pinctrl2 = &amp;pinctrl_aud;</div><div class='add'>+		pinctrl3 = &amp;pinctrl_hsi;</div><div class='add'>+		pinctrl4 = &amp;pinctrl_core;</div><div class='add'>+		pinctrl5 = &amp;pinctrl_peri;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	arm-pmu {</div><div class='add'>+		compatible = "arm,cortex-a55-pmu";</div><div class='add'>+		interrupts = &lt;GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-affinity = &lt;&amp;cpu0&gt;, &lt;&amp;cpu1&gt;, &lt;&amp;cpu2&gt;, &lt;&amp;cpu3&gt;,</div><div class='add'>+				     &lt;&amp;cpu4&gt;, &lt;&amp;cpu5&gt;, &lt;&amp;cpu6&gt;, &lt;&amp;cpu7&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Main system clock (XTCXO); external, must be 26 MHz */</div><div class='add'>+	oscclk: clock-oscclk {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		clock-output-names = "oscclk";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu-map {</div><div class='add'>+			cluster0 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu0&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu1&gt;;</div><div class='add'>+				};</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu2&gt;;</div><div class='add'>+				};</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu3&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cluster1 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu4&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu5&gt;;</div><div class='add'>+				};</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu6&gt;;</div><div class='add'>+				};</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu7&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clocks = &lt;&amp;cmu_cpucl0 CLK_CLUSTER0_SCLK&gt;;</div><div class='add'>+			clock-names = "cluster0_clk";</div><div class='add'>+		};</div><div class='add'>+		cpu1: cpu@1 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x1&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+		cpu2: cpu@2 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x2&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+		cpu3: cpu@3 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x3&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+		cpu4: cpu@100 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x100&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clocks = &lt;&amp;cmu_cpucl1 CLK_CLUSTER1_SCLK&gt;;</div><div class='add'>+			clock-names = "cluster1_clk";</div><div class='add'>+		};</div><div class='add'>+		cpu5: cpu@101 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x101&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+		cpu6: cpu@102 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x102&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+		cpu7: cpu@103 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x103&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-1.0";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		/* Hypervisor Virtual Timer interrupt is not wired to GIC */</div><div class='add'>+		interrupts =</div><div class='add'>+		     &lt;GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+		     &lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+		     &lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+		     &lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc: soc@0 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges = &lt;0x0 0x0 0x0 0x20000000&gt;;</div><div class='add'>+</div><div class='add'>+		chipid@10000000 {</div><div class='add'>+			compatible = "samsung,exynos850-chipid";</div><div class='add'>+			reg = &lt;0x10000000 0x100&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		timer@10040000 {</div><div class='add'>+			compatible = "samsung,exynos850-mct",</div><div class='add'>+				     "samsung,exynos4210-mct";</div><div class='add'>+			reg = &lt;0x10040000 0x800&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;oscclk&gt;, &lt;&amp;cmu_peri CLK_GOUT_MCT_PCLK&gt;;</div><div class='add'>+			clock-names = "fin_pll", "mct";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pdma0: dma-controller@120c0000 {</div><div class='add'>+			compatible = "arm,pl330", "arm,primecell";</div><div class='add'>+			reg = &lt;0x120c0000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_core CLK_GOUT_PDMA_CORE_ACLK&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			arm,pl330-broken-no-flushp;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@12a01000 {</div><div class='add'>+			compatible = "arm,gic-400";</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			#address-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0x12a01000 0x1000&gt;,</div><div class='add'>+			      &lt;0x12a02000 0x2000&gt;,</div><div class='add'>+			      &lt;0x12a04000 0x2000&gt;,</div><div class='add'>+			      &lt;0x12a06000 0x2000&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |</div><div class='add'>+						 IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmu_system_controller: system-controller@11860000 {</div><div class='add'>+			compatible = "samsung,exynos850-pmu", "syscon";</div><div class='add'>+			reg = &lt;0x11860000 0x10000&gt;;</div><div class='add'>+</div><div class='add'>+			reboot: syscon-reboot {</div><div class='add'>+				compatible = "syscon-reboot";</div><div class='add'>+				regmap = &lt;&amp;pmu_system_controller&gt;;</div><div class='add'>+				offset = &lt;0x3a00&gt;; /* SYSTEM_CONFIGURATION */</div><div class='add'>+				mask = &lt;0x2&gt;; /* SWRESET_SYSTEM */</div><div class='add'>+				value = &lt;0x2&gt;; /* reset value */</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		watchdog_cl0: watchdog@10050000 {</div><div class='add'>+			compatible = "samsung,exynos850-wdt";</div><div class='add'>+			reg = &lt;0x10050000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peri CLK_GOUT_WDT0_PCLK&gt;, &lt;&amp;oscclk&gt;;</div><div class='add'>+			clock-names = "watchdog", "watchdog_src";</div><div class='add'>+			samsung,syscon-phandle = &lt;&amp;pmu_system_controller&gt;;</div><div class='add'>+			samsung,cluster-index = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		watchdog_cl1: watchdog@10060000 {</div><div class='add'>+			compatible = "samsung,exynos850-wdt";</div><div class='add'>+			reg = &lt;0x10060000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peri CLK_GOUT_WDT1_PCLK&gt;, &lt;&amp;oscclk&gt;;</div><div class='add'>+			clock-names = "watchdog", "watchdog_src";</div><div class='add'>+			samsung,syscon-phandle = &lt;&amp;pmu_system_controller&gt;;</div><div class='add'>+			samsung,cluster-index = &lt;1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_peri: clock-controller@10030000 {</div><div class='add'>+			compatible = "samsung,exynos850-cmu-peri";</div><div class='add'>+			reg = &lt;0x10030000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;oscclk&gt;, &lt;&amp;cmu_top CLK_DOUT_PERI_BUS&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_PERI_UART&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_PERI_IP&gt;;</div><div class='add'>+			clock-names = "oscclk", "dout_peri_bus",</div><div class='add'>+				      "dout_peri_uart", "dout_peri_ip";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_cpucl1: clock-controller@10800000 {</div><div class='add'>+			compatible = "samsung,exynos850-cmu-cpucl1";</div><div class='add'>+			reg = &lt;0x10800000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;oscclk&gt;, &lt;&amp;cmu_top CLK_DOUT_CPUCL1_SWITCH&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CPUCL1_DBG&gt;;</div><div class='add'>+			clock-names = "oscclk", "dout_cpucl1_switch",</div><div class='add'>+				      "dout_cpucl1_dbg";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_cpucl0: clock-controller@10900000 {</div><div class='add'>+			compatible = "samsung,exynos850-cmu-cpucl0";</div><div class='add'>+			reg = &lt;0x10900000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;oscclk&gt;, &lt;&amp;cmu_top CLK_DOUT_CPUCL0_SWITCH&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CPUCL0_DBG&gt;;</div><div class='add'>+			clock-names = "oscclk", "dout_cpucl0_switch",</div><div class='add'>+				      "dout_cpucl0_dbg";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_g3d: clock-controller@11400000 {</div><div class='add'>+			compatible = "samsung,exynos850-cmu-g3d";</div><div class='add'>+			reg = &lt;0x11400000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;oscclk&gt;, &lt;&amp;cmu_top CLK_DOUT_G3D_SWITCH&gt;;</div><div class='add'>+			clock-names = "oscclk", "dout_g3d_switch";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_apm: clock-controller@11800000 {</div><div class='add'>+			compatible = "samsung,exynos850-cmu-apm";</div><div class='add'>+			reg = &lt;0x11800000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;oscclk&gt;, &lt;&amp;cmu_top CLK_DOUT_CLKCMU_APM_BUS&gt;;</div><div class='add'>+			clock-names = "oscclk", "dout_clkcmu_apm_bus";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_cmgp: clock-controller@11c00000 {</div><div class='add'>+			compatible = "samsung,exynos850-cmu-cmgp";</div><div class='add'>+			reg = &lt;0x11c00000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;oscclk&gt;, &lt;&amp;cmu_apm CLK_GOUT_CLKCMU_CMGP_BUS&gt;;</div><div class='add'>+			clock-names = "oscclk", "gout_clkcmu_cmgp_bus";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_core: clock-controller@12000000 {</div><div class='add'>+			compatible = "samsung,exynos850-cmu-core";</div><div class='add'>+			reg = &lt;0x12000000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;oscclk&gt;, &lt;&amp;cmu_top CLK_DOUT_CORE_BUS&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CORE_CCI&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CORE_MMC_EMBD&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CORE_SSS&gt;;</div><div class='add'>+			clock-names = "oscclk", "dout_core_bus",</div><div class='add'>+				      "dout_core_cci", "dout_core_mmc_embd",</div><div class='add'>+				      "dout_core_sss";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_top: clock-controller@120e0000 {</div><div class='add'>+			compatible = "samsung,exynos850-cmu-top";</div><div class='add'>+			reg = &lt;0x120e0000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;oscclk&gt;;</div><div class='add'>+			clock-names = "oscclk";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_mfcmscl: clock-controller@12c00000 {</div><div class='add'>+			compatible = "samsung,exynos850-cmu-mfcmscl";</div><div class='add'>+			reg = &lt;0x12c00000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;oscclk&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_MFCMSCL_MFC&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_MFCMSCL_M2M&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_MFCMSCL_MCSC&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_MFCMSCL_JPEG&gt;;</div><div class='add'>+			clock-names = "oscclk", "dout_mfcmscl_mfc",</div><div class='add'>+				      "dout_mfcmscl_m2m", "dout_mfcmscl_mcsc",</div><div class='add'>+				      "dout_mfcmscl_jpeg";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_dpu: clock-controller@13000000 {</div><div class='add'>+			compatible = "samsung,exynos850-cmu-dpu";</div><div class='add'>+			reg = &lt;0x13000000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;oscclk&gt;, &lt;&amp;cmu_top CLK_DOUT_DPU&gt;;</div><div class='add'>+			clock-names = "oscclk", "dout_dpu";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_hsi: clock-controller@13400000 {</div><div class='add'>+			compatible = "samsung,exynos850-cmu-hsi";</div><div class='add'>+			reg = &lt;0x13400000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;oscclk&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_HSI_BUS&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_HSI_MMC_CARD&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_HSI_USB20DRD&gt;;</div><div class='add'>+			clock-names = "oscclk", "dout_hsi_bus",</div><div class='add'>+				      "dout_hsi_mmc_card", "dout_hsi_usb20drd";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_is: clock-controller@14500000 {</div><div class='add'>+			compatible = "samsung,exynos850-cmu-is";</div><div class='add'>+			reg = &lt;0x14500000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;oscclk&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_IS_BUS&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_IS_ITP&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_IS_VRA&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_IS_GDC&gt;;</div><div class='add'>+			clock-names = "oscclk", "dout_is_bus", "dout_is_itp",</div><div class='add'>+				      "dout_is_vra", "dout_is_gdc";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_aud: clock-controller@14a00000 {</div><div class='add'>+			compatible = "samsung,exynos850-cmu-aud";</div><div class='add'>+			reg = &lt;0x14a00000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;oscclk&gt;, &lt;&amp;cmu_top CLK_DOUT_AUD&gt;;</div><div class='add'>+			clock-names = "oscclk", "dout_aud";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_alive: pinctrl@11850000 {</div><div class='add'>+			compatible = "samsung,exynos850-pinctrl";</div><div class='add'>+			reg = &lt;0x11850000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			wakeup-interrupt-controller {</div><div class='add'>+				compatible = "samsung,exynos850-wakeup-eint",</div><div class='add'>+					     "samsung,exynos7-wakeup-eint";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_cmgp: pinctrl@11c30000 {</div><div class='add'>+			compatible = "samsung,exynos850-pinctrl";</div><div class='add'>+			reg = &lt;0x11c30000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			wakeup-interrupt-controller {</div><div class='add'>+				compatible = "samsung,exynos850-wakeup-eint",</div><div class='add'>+					     "samsung,exynos7-wakeup-eint";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_core: pinctrl@12070000 {</div><div class='add'>+			compatible = "samsung,exynos850-pinctrl";</div><div class='add'>+			reg = &lt;0x12070000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		trng: rng@12081400 {</div><div class='add'>+			compatible = "samsung,exynos850-trng";</div><div class='add'>+			reg = &lt;0x12081400 0x100&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_core CLK_GOUT_SSS_ACLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_core CLK_GOUT_SSS_PCLK&gt;;</div><div class='add'>+			clock-names = "secss", "pclk";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_hsi: pinctrl@13430000 {</div><div class='add'>+			compatible = "samsung,exynos850-pinctrl";</div><div class='add'>+			reg = &lt;0x13430000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_peri: pinctrl@139b0000 {</div><div class='add'>+			compatible = "samsung,exynos850-pinctrl";</div><div class='add'>+			reg = &lt;0x139b0000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_aud: pinctrl@14a60000 {</div><div class='add'>+			compatible = "samsung,exynos850-pinctrl";</div><div class='add'>+			reg = &lt;0x14a60000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rtc: rtc@11a30000 {</div><div class='add'>+			compatible = "samsung,exynos850-rtc", "samsung,s3c6410-rtc";</div><div class='add'>+			reg = &lt;0x11a30000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_apm CLK_GOUT_RTC_PCLK&gt;;</div><div class='add'>+			clock-names = "rtc";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmc_0: mmc@12100000 {</div><div class='add'>+			compatible = "samsung,exynos850-dw-mshc-smu",</div><div class='add'>+				     "samsung,exynos7-dw-mshc-smu";</div><div class='add'>+			reg = &lt;0x12100000 0x2000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_core CLK_GOUT_MMC_EMBD_ACLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_core CLK_GOUT_MMC_EMBD_SDCLKIN&gt;;</div><div class='add'>+			clock-names = "biu", "ciu";</div><div class='add'>+			fifo-depth = &lt;0x40&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c_0: i2c@13830000 {</div><div class='add'>+			compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c";</div><div class='add'>+			reg = &lt;0x13830000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c0_pins&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peri CLK_GOUT_I2C0_PCLK&gt;;</div><div class='add'>+			clock-names = "i2c";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c_1: i2c@13840000 {</div><div class='add'>+			compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c";</div><div class='add'>+			reg = &lt;0x13840000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c1_pins&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peri CLK_GOUT_I2C1_PCLK&gt;;</div><div class='add'>+			clock-names = "i2c";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c_2: i2c@13850000 {</div><div class='add'>+			compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c";</div><div class='add'>+			reg = &lt;0x13850000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c2_pins&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peri CLK_GOUT_I2C2_PCLK&gt;;</div><div class='add'>+			clock-names = "i2c";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c_3: i2c@13860000 {</div><div class='add'>+			compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c";</div><div class='add'>+			reg = &lt;0x13860000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c3_pins&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peri CLK_GOUT_I2C3_PCLK&gt;;</div><div class='add'>+			clock-names = "i2c";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c_4: i2c@13870000 {</div><div class='add'>+			compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c";</div><div class='add'>+			reg = &lt;0x13870000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c4_pins&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peri CLK_GOUT_I2C4_PCLK&gt;;</div><div class='add'>+			clock-names = "i2c";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* I2C_5 (also called CAM_PMIC_I2C in TRM) */</div><div class='add'>+		i2c_5: i2c@13880000 {</div><div class='add'>+			compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c";</div><div class='add'>+			reg = &lt;0x13880000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c5_pins&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peri CLK_GOUT_I2C5_PCLK&gt;;</div><div class='add'>+			clock-names = "i2c";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* I2C_6 (also called MOTOR_I2C in TRM) */</div><div class='add'>+		i2c_6: i2c@13890000 {</div><div class='add'>+			compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c";</div><div class='add'>+			reg = &lt;0x13890000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c6_pins&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peri CLK_GOUT_I2C6_PCLK&gt;;</div><div class='add'>+			clock-names = "i2c";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sysmmu_mfcmscl: sysmmu@12c50000 {</div><div class='add'>+			compatible = "samsung,exynos-sysmmu";</div><div class='add'>+			reg = &lt;0x12c50000 0x9000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clock-names = "sysmmu";</div><div class='add'>+			clocks = &lt;&amp;cmu_mfcmscl CLK_GOUT_MFCMSCL_SYSMMU_CLK&gt;;</div><div class='add'>+			#iommu-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sysmmu_dpu: sysmmu@130c0000 {</div><div class='add'>+			compatible = "samsung,exynos-sysmmu";</div><div class='add'>+			reg = &lt;0x130c0000 0x9000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clock-names = "sysmmu";</div><div class='add'>+			clocks = &lt;&amp;cmu_dpu CLK_GOUT_DPU_SMMU_CLK&gt;;</div><div class='add'>+			#iommu-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sysmmu_is0: sysmmu@14550000 {</div><div class='add'>+			compatible = "samsung,exynos-sysmmu";</div><div class='add'>+			reg = &lt;0x14550000 0x9000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clock-names = "sysmmu";</div><div class='add'>+			clocks = &lt;&amp;cmu_is CLK_GOUT_IS_SYSMMU_IS0_CLK&gt;;</div><div class='add'>+			#iommu-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sysmmu_is1: sysmmu@14570000 {</div><div class='add'>+			compatible = "samsung,exynos-sysmmu";</div><div class='add'>+			reg = &lt;0x14570000 0x9000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clock-names = "sysmmu";</div><div class='add'>+			clocks = &lt;&amp;cmu_is CLK_GOUT_IS_SYSMMU_IS1_CLK&gt;;</div><div class='add'>+			#iommu-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sysmmu_aud: sysmmu@14850000 {</div><div class='add'>+			compatible = "samsung,exynos-sysmmu";</div><div class='add'>+			reg = &lt;0x14850000 0x9000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clock-names = "sysmmu";</div><div class='add'>+			clocks = &lt;&amp;cmu_aud CLK_GOUT_AUD_SYSMMU_CLK&gt;;</div><div class='add'>+			#iommu-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sysreg_peri: syscon@10020000 {</div><div class='add'>+			compatible = "samsung,exynos850-peri-sysreg",</div><div class='add'>+				     "samsung,exynos850-sysreg", "syscon";</div><div class='add'>+			reg = &lt;0x10020000 0x10000&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peri CLK_GOUT_SYSREG_PERI_PCLK&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sysreg_cmgp: syscon@11c20000 {</div><div class='add'>+			compatible = "samsung,exynos850-cmgp-sysreg",</div><div class='add'>+				     "samsung,exynos850-sysreg", "syscon";</div><div class='add'>+			reg = &lt;0x11c20000 0x10000&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_cmgp CLK_GOUT_SYSREG_CMGP_PCLK&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usbdrd: usb@13600000 {</div><div class='add'>+			compatible = "samsung,exynos850-dwusb3";</div><div class='add'>+			ranges = &lt;0x0 0x13600000 0x10000&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_hsi CLK_GOUT_USB_BUS_EARLY_CLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_hsi CLK_GOUT_USB_REF_CLK&gt;;</div><div class='add'>+			clock-names = "bus_early", "ref";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			usbdrd_dwc3: usb@0 {</div><div class='add'>+				compatible = "snps,dwc3";</div><div class='add'>+				reg = &lt;0x0 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				phys = &lt;&amp;usbdrd_phy 0&gt;;</div><div class='add'>+				phy-names = "usb2-phy";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usbdrd_phy: phy@135d0000 {</div><div class='add'>+			compatible = "samsung,exynos850-usbdrd-phy";</div><div class='add'>+			reg = &lt;0x135d0000 0x100&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_hsi CLK_GOUT_USB_PHY_ACLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_hsi CLK_GOUT_USB_PHY_REF_CLK&gt;;</div><div class='add'>+			clock-names = "phy", "ref";</div><div class='add'>+			samsung,pmu-syscon = &lt;&amp;pmu_system_controller&gt;;</div><div class='add'>+			#phy-cells = &lt;1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_uart: usi@138200c0 {</div><div class='add'>+			compatible = "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x138200c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;sysreg_peri 0x1010&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_MODE_UART&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_peri CLK_GOUT_UART_PCLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peri CLK_GOUT_UART_IPCLK&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			serial_0: serial@13820000 {</div><div class='add'>+				compatible = "samsung,exynos850-uart";</div><div class='add'>+				reg = &lt;0x13820000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart0_pins&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peri CLK_GOUT_UART_PCLK&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peri CLK_GOUT_UART_IPCLK&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_hsi2c_0: usi@138a00c0 {</div><div class='add'>+			compatible = "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x138a00c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;sysreg_peri 0x1020&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_MODE_I2C&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_peri CLK_GOUT_HSI2C0_PCLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peri CLK_GOUT_HSI2C0_IPCLK&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_0: i2c@138a0000 {</div><div class='add'>+				compatible = "samsung,exynos850-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x138a0000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c0_pins&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peri CLK_GOUT_HSI2C0_IPCLK&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peri CLK_GOUT_HSI2C0_PCLK&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_hsi2c_1: usi@138b00c0 {</div><div class='add'>+			compatible = "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x138b00c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;sysreg_peri 0x1030&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_MODE_I2C&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_peri CLK_GOUT_HSI2C1_PCLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peri CLK_GOUT_HSI2C1_IPCLK&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_1: i2c@138b0000 {</div><div class='add'>+				compatible = "samsung,exynos850-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x138b0000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c1_pins&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peri CLK_GOUT_HSI2C1_IPCLK&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peri CLK_GOUT_HSI2C1_PCLK&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_hsi2c_2: usi@138c00c0 {</div><div class='add'>+			compatible = "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x138c00c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;sysreg_peri 0x1040&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_MODE_I2C&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_peri CLK_GOUT_HSI2C2_PCLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peri CLK_GOUT_HSI2C2_IPCLK&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_2: i2c@138c0000 {</div><div class='add'>+				compatible = "samsung,exynos850-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x138c0000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c2_pins&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peri CLK_GOUT_HSI2C2_IPCLK&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peri CLK_GOUT_HSI2C2_PCLK&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_spi_0: usi@139400c0 {</div><div class='add'>+			compatible = "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x139400c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;sysreg_peri 0x1050&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_MODE_SPI&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_peri CLK_GOUT_SPI0_PCLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peri CLK_GOUT_SPI0_IPCLK&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			spi_0: spi@13940000 {</div><div class='add'>+				compatible = "samsung,exynos850-spi";</div><div class='add'>+				reg = &lt;0x13940000 0x30&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peri CLK_GOUT_SPI0_PCLK&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peri CLK_GOUT_SPI0_IPCLK&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				dmas = &lt;&amp;pdma0 5&gt;, &lt;&amp;pdma0 4&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				interrupts = &lt;GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi0_pins&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				num-cs = &lt;1&gt;;</div><div class='add'>+				samsung,spi-src-clk = &lt;0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_cmgp0: usi@11d000c0 {</div><div class='add'>+			compatible = "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x11d000c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;sysreg_cmgp 0x2000&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_MODE_I2C&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_3: i2c@11d00000 {</div><div class='add'>+				compatible = "samsung,exynos850-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x11d00000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c3_pins&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK&gt;,</div><div class='add'>+					 &lt;&amp;cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_1: serial@11d00000 {</div><div class='add'>+				compatible = "samsung,exynos850-uart";</div><div class='add'>+				reg = &lt;0x11d00000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart1_single_pins&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK&gt;,</div><div class='add'>+					 &lt;&amp;cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_1: spi@11d00000 {</div><div class='add'>+				compatible = "samsung,exynos850-spi";</div><div class='add'>+				reg = &lt;0x11d00000 0x30&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK&gt;,</div><div class='add'>+					 &lt;&amp;cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				dmas = &lt;&amp;pdma0 12&gt;, &lt;&amp;pdma0 13&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				interrupts = &lt;GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi1_pins&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				num-cs = &lt;1&gt;;</div><div class='add'>+				samsung,spi-src-clk = &lt;0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_cmgp1: usi@11d200c0 {</div><div class='add'>+			compatible = "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x11d200c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;sysreg_cmgp 0x2010&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_MODE_I2C&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_4: i2c@11d20000 {</div><div class='add'>+				compatible = "samsung,exynos850-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x11d20000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c4_pins&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK&gt;,</div><div class='add'>+					 &lt;&amp;cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_2: serial@11d20000 {</div><div class='add'>+				compatible = "samsung,exynos850-uart";</div><div class='add'>+				reg = &lt;0x11d20000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart2_single_pins&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK&gt;,</div><div class='add'>+					 &lt;&amp;cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_2: spi@11d20000 {</div><div class='add'>+				compatible = "samsung,exynos850-spi";</div><div class='add'>+				reg = &lt;0x11d20000 0x30&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK&gt;,</div><div class='add'>+					 &lt;&amp;cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				dmas = &lt;&amp;pdma0 14&gt;, &lt;&amp;pdma0 15&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				interrupts = &lt;GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi2_pins&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				num-cs = &lt;1&gt;;</div><div class='add'>+				samsung,spi-src-clk = &lt;0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include "exynos850-pinctrl.dtsi"</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/exynos8895-dreamlte.dts b/arch/arm64/boot/dts/exynos/exynos8895-dreamlte.dts<br/>new file mode 100644<br/>index 000000000000..61e064af3337<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynos8895-dreamlte.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/exynos8895-dreamlte.dts</a></div><div class='hunk'>@@ -0,0 +1,198 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause</div><div class='add'>+/*</div><div class='add'>+ * Samsung Galaxy S8 (dreamlte/SM-G950F) device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2024, Ivaylo Ivanov &lt;ivo.ivanov.ivanov1@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "exynos8895.dtsi"</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/soc/samsung,exynos-usi.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Samsung Galaxy S8 (SM-G950F)";</div><div class='add'>+	compatible = "samsung,dreamlte", "samsung,exynos8895";</div><div class='add'>+	chassis-type = "handset";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		mmc0 = &amp;mmc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		framebuffer: framebuffer@cc000000 {</div><div class='add'>+			compatible = "simple-framebuffer";</div><div class='add'>+			reg = &lt;0 0xcc000000 (1440 * 2960 * 4)&gt;;</div><div class='add'>+			width = &lt;1440&gt;;</div><div class='add'>+			height = &lt;2960&gt;;</div><div class='add'>+			stride = &lt;(1440 * 4)&gt;;</div><div class='add'>+			format = "a8r8g8b8";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@80000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x80000000 0x3c800000&gt;,</div><div class='add'>+		      &lt;0x0 0xc0000000 0x40000000&gt;,</div><div class='add'>+		      &lt;0x8 0x80000000 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		ramoops@92000000 {</div><div class='add'>+			compatible = "ramoops";</div><div class='add'>+			reg = &lt;0 0x92000000 0x8000&gt;;</div><div class='add'>+			record-size = &lt;0x4000&gt;;</div><div class='add'>+			console-size = &lt;0x4000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cont_splash_mem: framebuffer@cc000000 {</div><div class='add'>+			reg = &lt;0 0xcc000000 (1440 * 2960 * 4)&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;key_power &amp;key_voldown &amp;key_volup &amp;key_wink&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		power-key {</div><div class='add'>+			label = "Power";</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpa2 4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		voldown-key {</div><div class='add'>+			label = "Volume Down";</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpa0 4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		volup-key {</div><div class='add'>+			label = "Volume Up";</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpa0 3 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* Typically used for Bixby. Map it as a camera button for now */</div><div class='add'>+		wink-key {</div><div class='add'>+			label = "Camera";</div><div class='add'>+			linux,code = &lt;KEY_CAMERA&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpa0 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* TODO: Remove once PMIC is implemented  */</div><div class='add'>+	reg_placeholder: regulator-0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "reg-placeholder";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hsi2c_23 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	touchscreen@48 {</div><div class='add'>+		compatible = "samsung,s6sy761";</div><div class='add'>+		reg = &lt;0x48&gt;;</div><div class='add'>+</div><div class='add'>+		/* TODO: Update once PMIC is implemented */</div><div class='add'>+		avdd-supply = &lt;&amp;reg_placeholder&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;reg_placeholder&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-parent = &lt;&amp;gpa1&gt;;</div><div class='add'>+		interrupts = &lt;0 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;ts_int&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;oscclk {</div><div class='add'>+	clock-frequency = &lt;26000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc {</div><div class='add'>+	pinctrl-0 = &lt;&amp;sd2_clk &amp;sd2_cmd &amp;sd2_bus1 &amp;sd2_bus4 &amp;sd2_cd&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	card-detect-delay = &lt;200&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpa1 5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	clock-frequency = &lt;800000000&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+	sd-uhs-sdr50;</div><div class='add'>+	sd-uhs-sdr104;</div><div class='add'>+</div><div class='add'>+	/* TODO: Add regulators once PMIC is implemented */</div><div class='add'>+</div><div class='add'>+	samsung,dw-mshc-ciu-div = &lt;3&gt;;</div><div class='add'>+	samsung,dw-mshc-ddr-timing = &lt;1 2&gt;;</div><div class='add'>+	samsung,dw-mshc-sdr-timing = &lt;0 3&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_alive {</div><div class='add'>+	key_power: key-power-pins {</div><div class='add'>+		samsung,pins = "gpa2-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	key_voldown: key-voldown-pins {</div><div class='add'>+		samsung,pins = "gpa0-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	key_volup: key-volup-pins {</div><div class='add'>+		samsung,pins = "gpa0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	key_wink: key-wink-pins {</div><div class='add'>+		samsung,pins = "gpa0-6";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_cd: sd2-cd-pins {</div><div class='add'>+		samsung,pins = "gpa1-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ts_int: ts-int-pins {</div><div class='add'>+		samsung,pins = "gpa1-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usi9 {</div><div class='add'>+	samsung,mode = &lt;USI_MODE_I2C0_1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/exynos8895-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos8895-pinctrl.dtsi<br/>new file mode 100644<br/>index 000000000000..16903ce63a32<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynos8895-pinctrl.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/exynos8895-pinctrl.dtsi</a></div><div class='hunk'>@@ -0,0 +1,1094 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause</div><div class='add'>+/*</div><div class='add'>+ * Samsung's Exynos 8895 SoC pin-mux and pin-config device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2024, Ivaylo Ivanov &lt;ivo.ivanov.ivanov1@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include "exynos-pinctrl.h"</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_abox {</div><div class='add'>+	gph0: gph0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gph1: gph1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gph3: gph3-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_alive {</div><div class='add'>+	gpa0: gpa0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpa1: gpa1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpa2: gpa2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpa3: gpa3-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpa4: gpa4-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bt_hostwake: bt-hostwake-pins {</div><div class='add'>+		samsung,pins = "gpa2-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie_wake: pcie-wake-pins {</div><div class='add'>+		samsung,pins = "gpa3-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart1_bus: uart1-bus-pins {</div><div class='add'>+		samsung,pins = "gpa4-4", "gpa4-3", "gpa4-2", "gpa4-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wlan_host_wake: wlan-host-wake-pins {</div><div class='add'>+		  samsung,pins = "gpa0-7";</div><div class='add'>+		  samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		  samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+		  samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+		  samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_busc {</div><div class='add'>+	gpb2: gpb2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c0_bus: hsi2c0-bus-pins {</div><div class='add'>+		samsung,pins = "gpb2-1", "gpb2-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	speedy_bus: speedy-bus-pins {</div><div class='add'>+		samsung,pins = "gpb2-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_fsys0 {</div><div class='add'>+	gpi0: gpi0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpi1: gpi1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ufs_rst_n: ufs-rst-n-pins {</div><div class='add'>+		samsung,pins = "gpi0-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ufs_refclk_out: ufs-refclk-out-pins {</div><div class='add'>+		samsung,pins = "gpi0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_fsys1 {</div><div class='add'>+	gpj0: gpj0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpj1: gpj1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bt_btwake: bt-btwake-pins {</div><div class='add'>+		samsung,pins = "gpj1-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bt_en: bt-en-pins {</div><div class='add'>+		samsung,pins = "gpj1-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cfg_wlanen: cfg-wlanen-pins {</div><div class='add'>+		samsung,pins = "gpj1-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV4&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_clk: sd2-clk-pins {</div><div class='add'>+		samsung,pins = "gpj0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_cmd: sd2-cmd-pins {</div><div class='add'>+		samsung,pins = "gpj0-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_bus1: sd2-bus-width1-pins {</div><div class='add'>+		samsung,pins = "gpj0-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_bus4: sd2-bus-width4-pins {</div><div class='add'>+		samsung,pins = "gpj0-3", "gpj0-4", "gpj0-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* For Drive strength swapping */</div><div class='add'>+	sd2_clk_fast_slew_rate_1x: sd2-clk-fast-slew-rate-1x-pins {</div><div class='add'>+		samsung,pins = "gpj0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_clk_fast_slew_rate_2x: sd2-clk-fast-slew-rate-2x-pins {</div><div class='add'>+		samsung,pins = "gpj0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_clk_fast_slew_rate_3x: sd2-clk-fast-slew-rate-3x-pins {</div><div class='add'>+		samsung,pins = "gpj0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_clk_fast_slew_rate_4x: sd2-clk-fast-slew-rate-4x-pins {</div><div class='add'>+		samsung,pins = "gpj0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV4&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_peric0 {</div><div class='add'>+	gpb1: gpb1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpd0: gpd0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpd1: gpd1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpd2: gpd2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpd3: gpd3-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpe7: gpe7-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpf1: gpf1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c5_bus: hsi2c5-bus-pins {</div><div class='add'>+		samsung,pins = "gpd1-1", "gpd1-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c6_bus: hsi2c6-bus-pins {</div><div class='add'>+		samsung,pins = "gpd1-3", "gpd1-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c7_bus: hsi2c7-bus-pins {</div><div class='add'>+		samsung,pins = "gpd1-5", "gpd1-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c8_bus: hsi2c8-bus-pins {</div><div class='add'>+		samsung,pins = "gpd1-7", "gpd1-6";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c9_bus: hsi2c9-bus-pins {</div><div class='add'>+		samsung,pins = "gpd2-1", "gpd2-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c10_bus: hsi2c10-bus-pins {</div><div class='add'>+		samsung,pins = "gpd2-3", "gpd2-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c11_bus: hsi2c11-bus-pins {</div><div class='add'>+		samsung,pins = "gpd3-1", "gpd3-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c12_bus: hsi2c12-bus-pins {</div><div class='add'>+		samsung,pins = "gpd3-3", "gpd3-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hs_i2c14_bus: hs-i2c14-bus-pins {</div><div class='add'>+		samsung,pins = "gpe6-3", "gpe6-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi2_bus: spi2-bus-pins {</div><div class='add'>+		samsung,pins = "gpd1-3", "gpd1-2", "gpd1-1", "gpd1-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi2_cs: spi2-cs-pins {</div><div class='add'>+		samsung,pins = "gpd1-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi3_bus: spi3-bus-pins {</div><div class='add'>+		samsung,pins = "gpd1-7", "gpd1-5", "gpd1-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi3_cs: spi3-cs-pins {</div><div class='add'>+		samsung,pins = "gpd1-6";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi4_bus: spi4-bus-pins {</div><div class='add'>+		samsung,pins = "gpd2-3", "gpd2-1", "gpd2-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi4_cs: spi4-cs-pins {</div><div class='add'>+		samsung,pins = "gpd2-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi5_bus: spi5-bus-pins {</div><div class='add'>+		samsung,pins = "gpd3-3", "gpd3-1", "gpd3-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi5_cs: spi5-cs-pins {</div><div class='add'>+		samsung,pins = "gpd3-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart0_bus: uart0-bus-pins {</div><div class='add'>+		samsung,pins = "gpd0-7", "gpd0-6";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart2_bus: uart2-bus-pins {</div><div class='add'>+		samsung,pins = "gpd1-3", "gpd1-2", "gpd1-1", "gpd1-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart2_bus_dual: uart2-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpd1-1", "gpd1-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart3_bus: uart3-bus-pins {</div><div class='add'>+		samsung,pins = "gpd1-7", "gpd1-6", "gpd1-5", "gpd1-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart3_bus_dual: uart3-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpd1-5", "gpd1-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart4_bus: uart4-bus-pins {</div><div class='add'>+		samsung,pins = "gpd2-3", "gpd2-2", "gpd2-1", "gpd2-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart4_bus_dual: uart4-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpd2-1", "gpd2-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart5_bus: uart5-bus-pins {</div><div class='add'>+		samsung,pins = "gpd3-3", "gpd3-2", "gpd3-1", "gpd3-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart5_bus_dual: uart5-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpd3-1", "gpd3-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_peric1 {</div><div class='add'>+	gpb0: gpb0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpc0: gpc0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpc1: gpc1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpc2: gpc2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpc3: gpc3-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpe1: gpe1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpe2: gpe2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpe3: gpe3-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpe4: gpe4-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpe5: gpe5-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpe6: gpe6-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpf0: gpf0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpg0: gpg0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpk0: gpk0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hrm_irq: hrm-irq-pins {</div><div class='add'>+		samsung,pins = "gpe6-6";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c1_bus: hsi2c1-bus-pins {</div><div class='add'>+		samsung,pins = "gpc2-1", "gpc2-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c2_bus: hsi2c2-bus-pins {</div><div class='add'>+		samsung,pins = "gpc2-3", "gpc2-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c3_bus: hsi2c3-bus-pins {</div><div class='add'>+		samsung,pins = "gpc2-5", "gpc2-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c4_bus: hsi2c4-bus-pins {</div><div class='add'>+		samsung,pins = "gpc2-7", "gpc2-6";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c13_bus: hsi2c13-bus-pins {</div><div class='add'>+		samsung,pins = "gpe5-1", "gpe5-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c14_bus: hsi2c14-bus-pins {</div><div class='add'>+		samsung,pins = "gpe5-3", "gpe5-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c15_bus: hsi2c15-bus-pins {</div><div class='add'>+		samsung,pins = "gpe1-1", "gpe1-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c16_bus: hsi2c16-bus-pins {</div><div class='add'>+		samsung,pins = "gpe1-3", "gpe1-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c17_bus: hsi2c17-bus-pins {</div><div class='add'>+		samsung,pins = "gpe1-5", "gpe1-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c18_bus: hsi2c18-bus-pins {</div><div class='add'>+		samsung,pins = "gpe1-7", "gpe1-6";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c19_bus: hsi2c19-bus-pins {</div><div class='add'>+		samsung,pins = "gpe2-1", "gpe2-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c20_bus: hsi2c20-bus-pins {</div><div class='add'>+		samsung,pins = "gpe2-3", "gpe2-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c21_bus: hsi2c21-bus-pins {</div><div class='add'>+		samsung,pins = "gpe2-5", "gpe2-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c22_bus: hsi2c22-bus-pins {</div><div class='add'>+		samsung,pins = "gpe2-7", "gpe2-6";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c23_bus: hsi2c23-bus-pins {</div><div class='add'>+		samsung,pins = "gpe3-1", "gpe3-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c24_bus: hsi2c24-bus-pins {</div><div class='add'>+		samsung,pins = "gpe3-3", "gpe3-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c25_bus: hsi2c25-bus-pins {</div><div class='add'>+		samsung,pins = "gpe3-5", "gpe3-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c26_bus: hsi2c26-bus-pins {</div><div class='add'>+		samsung,pins = "gpe3-7", "gpe3-6";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c27_bus: hsi2c27-bus-pins {</div><div class='add'>+		samsung,pins = "gpe4-1", "gpe4-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c28_bus: hsi2c28-bus-pins {</div><div class='add'>+		samsung,pins = "gpe4-3", "gpe4-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c29_bus: hsi2c29-bus-pins {</div><div class='add'>+		samsung,pins = "gpe4-5", "gpe4-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c30_bus: hsi2c30-bus-pins {</div><div class='add'>+		samsung,pins = "gpe4-7", "gpe4-6";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c31_bus: hsi2c31-bus-pins {</div><div class='add'>+		samsung,pins = "gpe5-5", "gpe5-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c32_bus: hsi2c32-bus-pins {</div><div class='add'>+		samsung,pins = "gpe5-7", "gpe5-6";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi0_bus: spi0-bus-pins {</div><div class='add'>+		samsung,pins = "gpc3-3", "gpc3-2", "gpc3-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi0_cs: spi0-cs-pins {</div><div class='add'>+		samsung,pins = "gpc3-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi1_bus: spi1-bus-pins {</div><div class='add'>+		samsung,pins = "gpc3-7", "gpc3-6", "gpc3-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi1_cs: spi1-cs-pins {</div><div class='add'>+		samsung,pins = "gpc3-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi6_bus: spi6-bus-pins {</div><div class='add'>+		samsung,pins = "gpe5-3", "gpe5-1", "gpe5-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi6_cs: spi6-cs-pins {</div><div class='add'>+		samsung,pins = "gpe5-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi7_bus: spi7-bus-pins {</div><div class='add'>+		samsung,pins = "gpe1-3", "gpe1-1", "gpe1-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi7_cs: spi7-cs-pins {</div><div class='add'>+		samsung,pins = "gpe1-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi8_bus: spi8-bus-pins {</div><div class='add'>+		samsung,pins = "gpe1-7", "gpe1-5", "gpe1-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi8_cs: spi8-cs-pins {</div><div class='add'>+		samsung,pins = "gpe1-6";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi9_bus: spi9-bus-pins {</div><div class='add'>+		samsung,pins = "gpe2-3", "gpe2-1", "gpe2-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi9_cs: spi9-cs-pins {</div><div class='add'>+		samsung,pins = "gpe2-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi10_bus: spi10-bus-pins {</div><div class='add'>+		samsung,pins = "gpe2-7", "gpe2-5", "gpe2-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi10_cs: spi10-cs-pins {</div><div class='add'>+		samsung,pins = "gpe2-6";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi11_bus: spi11-bus-pins {</div><div class='add'>+		samsung,pins = "gpe3-3", "gpe3-1", "gpe3-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi11_cs: spi11-cs-pins {</div><div class='add'>+		samsung,pins = "gpe3-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi12_bus: spi12-bus-pins {</div><div class='add'>+		samsung,pins = "gpe3-7", "gpe3-5", "gpe3-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi12_cs: spi12-cs-pins {</div><div class='add'>+		samsung,pins = "gpe3-6";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi13_bus: spi13-bus-pins {</div><div class='add'>+		samsung,pins = "gpe4-3", "gpe4-1", "gpe4-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi13_cs: spi13-cs-pins {</div><div class='add'>+		samsung,pins = "gpe4-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi14_bus: spi14-bus-pins {</div><div class='add'>+		samsung,pins = "gpe4-7", "gpe4-5", "gpe4-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi14_cs: spi14-cs-pins {</div><div class='add'>+		samsung,pins = "gpe4-6";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi15_bus: spi15-bus-pins {</div><div class='add'>+		samsung,pins = "gpe5-7", "gpe5-5", "gpe5-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi15_cs: spi15-cs-pins {</div><div class='add'>+		samsung,pins = "gpe5-6";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS7_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart6_bus: uart6-bus-pins {</div><div class='add'>+		samsung,pins = "gpe5-3", "gpe5-2", "gpe5-1", "gpe5-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart6_bus_dual: uart6-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpe5-1", "gpe5-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart7_bus: uart7-bus-pins {</div><div class='add'>+		samsung,pins = "gpe1-3", "gpe1-2", "gpe1-1", "gpe1-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart7_bus_dual: uart7-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpe1-1", "gpe1-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart8_bus: uart8-bus-pins {</div><div class='add'>+		samsung,pins = "gpe1-7", "gpe1-6", "gpe1-5", "gpe1-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart8_bus_dual: uart8-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpe1-5", "gpe1-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart9_bus: uart9-bus-pins {</div><div class='add'>+		samsung,pins = "gpe2-3", "gpe2-2", "gpe2-1", "gpe2-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart9_bus_dual: uart9-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpe2-1", "gpe2-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart10_bus: uart10-bus-pins {</div><div class='add'>+		samsung,pins = "gpe2-7", "gpe2-6", "gpe2-5", "gpe2-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart10_bus_dual: uart10-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpe2-5", "gpe2-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart11_bus: uart11-bus-pins {</div><div class='add'>+		samsung,pins = "gpe3-3", "gpe3-2", "gpe3-1", "gpe3-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart11_bus_dual: uart11-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpe3-1", "gpe3-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart12_bus: uart12-bus-pins {</div><div class='add'>+		samsung,pins = "gpe3-7", "gpe3-6", "gpe3-5", "gpe3-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart12_bus_dual: uart12-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpe3-5", "gpe3-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart13_bus: uart13-bus-pins {</div><div class='add'>+		samsung,pins = "gpe4-3", "gpe4-2", "gpe4-1", "gpe4-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart13_bus_dual: uart13-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpe4-1", "gpe4-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart14_bus: uart14-bus-pins {</div><div class='add'>+		samsung,pins = "gpe4-7", "gpe4-6", "gpe4-5", "gpe4-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart14_bus_dual: uart14-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpe4-5", "gpe4-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart15_bus: uart15-bus-pins {</div><div class='add'>+		samsung,pins = "gpe5-7", "gpe5-6", "gpe5-5", "gpe5-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart15_bus_dual: uart15-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpe5-5", "gpe5-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_vts {</div><div class='add'>+	gph2: gph2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/exynos8895.dtsi b/arch/arm64/boot/dts/exynos/exynos8895.dtsi<br/>new file mode 100644<br/>index 000000000000..f92d2a8a20a2<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynos8895.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/exynos8895.dtsi</a></div><div class='hunk'>@@ -0,0 +1,1374 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause</div><div class='add'>+/*</div><div class='add'>+ * Samsung's Exynos 8895 SoC device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2024, Ivaylo Ivanov &lt;ivo.ivanov.ivanov1@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/samsung,exynos8895.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "samsung,exynos8895";</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		pinctrl0 = &amp;pinctrl_alive;</div><div class='add'>+		pinctrl1 = &amp;pinctrl_abox;</div><div class='add'>+		pinctrl2 = &amp;pinctrl_vts;</div><div class='add'>+		pinctrl3 = &amp;pinctrl_fsys0;</div><div class='add'>+		pinctrl4 = &amp;pinctrl_fsys1;</div><div class='add'>+		pinctrl5 = &amp;pinctrl_busc;</div><div class='add'>+		pinctrl6 = &amp;pinctrl_peric0;</div><div class='add'>+		pinctrl7 = &amp;pinctrl_peric1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu-map {</div><div class='add'>+			cluster0 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu0&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu1&gt;;</div><div class='add'>+				};</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu2&gt;;</div><div class='add'>+				};</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu3&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cluster1 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu4&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu5&gt;;</div><div class='add'>+				};</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu6&gt;;</div><div class='add'>+				};</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu7&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu4: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "samsung,mongoose-m2";</div><div class='add'>+			reg = &lt;0x0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu5: cpu@1 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "samsung,mongoose-m2";</div><div class='add'>+			reg = &lt;0x1&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu6: cpu@2 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "samsung,mongoose-m2";</div><div class='add'>+			reg = &lt;0x2&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu7: cpu@3 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "samsung,mongoose-m2";</div><div class='add'>+			reg = &lt;0x3&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@100 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x100&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@101 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x101&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@102 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x102&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@103 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x103&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	oscclk: osc-clock {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-output-names = "oscclk";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu-a53 {</div><div class='add'>+		compatible = "arm,cortex-a53-pmu";</div><div class='add'>+		interrupts = &lt;GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-affinity = &lt;&amp;cpu0&gt;,</div><div class='add'>+				     &lt;&amp;cpu1&gt;,</div><div class='add'>+				     &lt;&amp;cpu2&gt;,</div><div class='add'>+				     &lt;&amp;cpu3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu-mongoose-m2 {</div><div class='add'>+		compatible = "samsung,mongoose-pmu";</div><div class='add'>+		interrupts = &lt;GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-affinity = &lt;&amp;cpu4&gt;,</div><div class='add'>+				     &lt;&amp;cpu5&gt;,</div><div class='add'>+				     &lt;&amp;cpu6&gt;,</div><div class='add'>+				     &lt;&amp;cpu7&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci";</div><div class='add'>+		method = "smc";</div><div class='add'>+		cpu_off = &lt;0x84000002&gt;;</div><div class='add'>+		cpu_on = &lt;0xc4000003&gt;;</div><div class='add'>+		cpu_suspend = &lt;0xc4000001&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc: soc@0 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		ranges = &lt;0x0 0x0 0x0 0x20000000&gt;;</div><div class='add'>+</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		chipid@10000000 {</div><div class='add'>+			compatible = "samsung,exynos8895-chipid",</div><div class='add'>+				     "samsung,exynos850-chipid";</div><div class='add'>+			reg = &lt;0x10000000 0x24&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_peris: clock-controller@10010000 {</div><div class='add'>+			compatible = "samsung,exynos8895-cmu-peris";</div><div class='add'>+			reg = &lt;0x10010000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;oscclk&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_PERIS_BUS&gt;;</div><div class='add'>+			clock-names = "oscclk", "bus";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		timer@10040000 {</div><div class='add'>+			compatible = "samsung,exynos8895-mct",</div><div class='add'>+				     "samsung,exynos4210-mct";</div><div class='add'>+			reg = &lt;0x10040000 0x800&gt;;</div><div class='add'>+			clocks = &lt;&amp;oscclk&gt;, &lt;&amp;cmu_peris CLK_GOUT_PERIS_MCT_PCLK&gt;;</div><div class='add'>+			clock-names = "fin_pll", "mct";</div><div class='add'>+			interrupts = &lt;GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@10201000 {</div><div class='add'>+			compatible = "arm,gic-400";</div><div class='add'>+			reg = &lt;0x10201000 0x1000&gt;,</div><div class='add'>+			      &lt;0x10202000 0x1000&gt;,</div><div class='add'>+			      &lt;0x10204000 0x2000&gt;,</div><div class='add'>+			      &lt;0x10206000 0x2000&gt;;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |</div><div class='add'>+						 IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='add'>+			#address-cells = &lt;0&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_peric0: clock-controller@10400000 {</div><div class='add'>+			compatible = "samsung,exynos8895-cmu-peric0";</div><div class='add'>+			reg = &lt;0x10400000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;oscclk&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_PERIC0_BUS&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_PERIC0_UART_DBG&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_PERIC0_USI00&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_PERIC0_USI01&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_PERIC0_USI02&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_PERIC0_USI03&gt;;</div><div class='add'>+			clock-names = "oscclk", "bus", "uart", "usi0",</div><div class='add'>+				      "usi1", "usi2", "usi3";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		syscon_peric0: syscon@10420000 {</div><div class='add'>+			compatible = "samsung,exynos8895-peric0-sysreg", "syscon";</div><div class='add'>+			reg = &lt;0x10420000 0x2000&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		serial_0: serial@10430000 {</div><div class='add'>+			compatible = "samsung,exynos8895-uart";</div><div class='add'>+			reg = &lt;0x10430000 0x100&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_UART_DBG_PCLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_UART_DBG_EXT_UCLK&gt;;</div><div class='add'>+			clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+			interrupts = &lt;GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;uart0_bus&gt;;</div><div class='add'>+			samsung,uart-fifosize = &lt;256&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi0: usi@10440000 {</div><div class='add'>+			compatible = "samsung,exynos8895-usi";</div><div class='add'>+			ranges = &lt;0x0 0x10440000 0x11000&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_USI00_I_PCLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_USI00_I_SCLK_USI&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric0 0x1000&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_5: i2c@0 {</div><div class='add'>+				compatible = "samsung,exynos8895-hsi2c";</div><div class='add'>+				reg = &lt;0x0 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_USI00_I_PCLK&gt;;</div><div class='add'>+				clock-names = "hsi2c";</div><div class='add'>+				interrupts = &lt;GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c5_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_2: serial@0 {</div><div class='add'>+				compatible = "samsung,exynos8895-uart";</div><div class='add'>+				reg = &lt;0x0 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_USI00_I_PCLK&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_USI00_I_SCLK_USI&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart2_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_2: spi@0 {</div><div class='add'>+				compatible = "samsung,exynos8895-spi",</div><div class='add'>+					     "samsung,exynos850-spi";</div><div class='add'>+				reg = &lt;0x0 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_USI00_I_PCLK&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_USI00_I_SCLK_USI&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi2_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			hsi2c_6: i2c@10000 {</div><div class='add'>+				compatible = "samsung,exynos8895-hsi2c";</div><div class='add'>+				reg = &lt;0x10000 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_USI00_I_PCLK&gt;;</div><div class='add'>+				clock-names = "hsi2c";</div><div class='add'>+				interrupts = &lt;GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c6_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi1: usi@10460000 {</div><div class='add'>+			compatible = "samsung,exynos8895-usi";</div><div class='add'>+			ranges = &lt;0x0 0x10460000 0x11000&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_USI01_I_PCLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_USI01_I_SCLK_USI&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric0 0x1004&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_7: i2c@0 {</div><div class='add'>+				compatible = "samsung,exynos8895-hsi2c";</div><div class='add'>+				reg = &lt;0x0 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_USI01_I_PCLK&gt;;</div><div class='add'>+				clock-names = "hsi2c";</div><div class='add'>+				interrupts = &lt;GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c5_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_3: serial@0 {</div><div class='add'>+				compatible = "samsung,exynos8895-uart";</div><div class='add'>+				reg = &lt;0x0 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_USI01_I_PCLK&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_USI01_I_SCLK_USI&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart3_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_3: spi@0 {</div><div class='add'>+				compatible = "samsung,exynos8895-spi",</div><div class='add'>+					     "samsung,exynos850-spi";</div><div class='add'>+				reg = &lt;0x0 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_USI01_I_PCLK&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_USI01_I_SCLK_USI&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi3_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			hsi2c_8: i2c@10000 {</div><div class='add'>+				compatible = "samsung,exynos8895-hsi2c";</div><div class='add'>+				reg = &lt;0x10000 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_USI01_I_PCLK&gt;;</div><div class='add'>+				clock-names = "hsi2c";</div><div class='add'>+				interrupts = &lt;GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c8_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi2: usi@10480000 {</div><div class='add'>+			compatible = "samsung,exynos8895-usi";</div><div class='add'>+			ranges = &lt;0x0 0x10480000 0x11000&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_USI02_I_PCLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_USI02_I_SCLK_USI&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric0 0x1008&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_9: i2c@0 {</div><div class='add'>+				compatible = "samsung,exynos8895-hsi2c";</div><div class='add'>+				reg = &lt;0x0 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_USI02_I_PCLK&gt;;</div><div class='add'>+				clock-names = "hsi2c";</div><div class='add'>+				interrupts = &lt;GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c9_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_4: serial@0 {</div><div class='add'>+				compatible = "samsung,exynos8895-uart";</div><div class='add'>+				reg = &lt;0x0 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_USI02_I_PCLK&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_USI02_I_SCLK_USI&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart4_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_4: spi@0 {</div><div class='add'>+				compatible = "samsung,exynos8895-spi",</div><div class='add'>+					     "samsung,exynos850-spi";</div><div class='add'>+				reg = &lt;0x0 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_USI02_I_PCLK&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_USI02_I_SCLK_USI&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi4_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			hsi2c_10: i2c@10000 {</div><div class='add'>+				compatible = "samsung,exynos8895-hsi2c";</div><div class='add'>+				reg = &lt;0x10000 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_USI02_I_PCLK&gt;;</div><div class='add'>+				clock-names = "hsi2c";</div><div class='add'>+				interrupts = &lt;GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c10_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi3: usi@104a0000 {</div><div class='add'>+			compatible = "samsung,exynos8895-usi";</div><div class='add'>+			ranges = &lt;0x0 0x104a0000 0x11000&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_USI03_I_PCLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_USI03_I_SCLK_USI&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric0 0x100c&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_11: i2c@0 {</div><div class='add'>+				compatible = "samsung,exynos8895-hsi2c";</div><div class='add'>+				reg = &lt;0x0 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_USI03_I_PCLK&gt;;</div><div class='add'>+				clock-names = "hsi2c";</div><div class='add'>+				interrupts = &lt;GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c11_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_5: serial@0 {</div><div class='add'>+				compatible = "samsung,exynos8895-uart";</div><div class='add'>+				reg = &lt;0x0 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_USI03_I_PCLK&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_USI03_I_SCLK_USI&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart5_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_5: spi@0 {</div><div class='add'>+				compatible = "samsung,exynos8895-spi",</div><div class='add'>+					     "samsung,exynos850-spi";</div><div class='add'>+				reg = &lt;0x0 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_USI03_I_PCLK&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_USI03_I_SCLK_USI&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi5_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			hsi2c_12: i2c@10000 {</div><div class='add'>+				compatible = "samsung,exynos8895-hsi2c";</div><div class='add'>+				reg = &lt;0x10000 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_USI03_I_PCLK&gt;;</div><div class='add'>+				clock-names = "hsi2c";</div><div class='add'>+				interrupts = &lt;GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c12_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_peric0: pinctrl@104d0000 {</div><div class='add'>+			compatible = "samsung,exynos8895-pinctrl";</div><div class='add'>+			reg = &lt;0x104d0000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_peric1: clock-controller@10800000 {</div><div class='add'>+			compatible = "samsung,exynos8895-cmu-peric1";</div><div class='add'>+			reg = &lt;0x10800000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;oscclk&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_PERIC1_BUS&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_PERIC1_SPEEDY2&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_PERIC1_SPI_CAM0&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_PERIC1_SPI_CAM1&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_PERIC1_UART_BT&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_PERIC1_USI04&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_PERIC1_USI05&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_PERIC1_USI06&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_PERIC1_USI07&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_PERIC1_USI08&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_PERIC1_USI09&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_PERIC1_USI10&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_PERIC1_USI11&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_PERIC1_USI12&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_PERIC1_USI13&gt;;</div><div class='add'>+			clock-names = "oscclk", "bus", "speedy", "cam0",</div><div class='add'>+				      "cam1", "uart", "usi4", "usi5",</div><div class='add'>+				      "usi6", "usi7", "usi8", "usi9",</div><div class='add'>+				      "usi10", "usi11", "usi12", "usi13";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		syscon_peric1: syscon@10820000 {</div><div class='add'>+			compatible = "samsung,exynos8895-peric1-sysreg", "syscon";</div><div class='add'>+			reg = &lt;0x10820000 0x2000&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		serial_1: serial@10830000 {</div><div class='add'>+			compatible = "samsung,exynos8895-uart";</div><div class='add'>+			reg = &lt;0x10830000 0x100&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_UART_BT_PCLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_UART_BT_EXT_UCLK&gt;;</div><div class='add'>+			clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+			interrupts = &lt;GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;uart1_bus&gt;;</div><div class='add'>+			samsung,uart-fifosize = &lt;256&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi4: usi@10840000 {</div><div class='add'>+			compatible = "samsung,exynos8895-usi";</div><div class='add'>+			ranges = &lt;0x0 0x10840000 0x11000&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI04_I_PCLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI04_I_SCLK_USI&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric1 0x1008&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_13: i2c@0 {</div><div class='add'>+				compatible = "samsung,exynos8895-hsi2c";</div><div class='add'>+				reg = &lt;0x0 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI04_I_PCLK&gt;;</div><div class='add'>+				clock-names = "hsi2c";</div><div class='add'>+				interrupts = &lt;GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c13_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_6: serial@0 {</div><div class='add'>+				compatible = "samsung,exynos8895-uart";</div><div class='add'>+				reg = &lt;0x0 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI04_I_PCLK&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI04_I_SCLK_USI&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart6_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_6: spi@0 {</div><div class='add'>+				compatible = "samsung,exynos8895-spi",</div><div class='add'>+					     "samsung,exynos850-spi";</div><div class='add'>+				reg = &lt;0x0 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI04_I_PCLK&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI04_I_SCLK_USI&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi6_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			hsi2c_14: i2c@10000 {</div><div class='add'>+				compatible = "samsung,exynos8895-hsi2c";</div><div class='add'>+				reg = &lt;0x10000 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI04_I_PCLK&gt;;</div><div class='add'>+				clock-names = "hsi2c";</div><div class='add'>+				interrupts = &lt;GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c14_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi5: usi@10860000 {</div><div class='add'>+			compatible = "samsung,exynos8895-usi";</div><div class='add'>+			ranges = &lt;0x0 0x10860000 0x11000&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI05_I_PCLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI05_I_SCLK_USI&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric1 0x100c&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_15: i2c@0 {</div><div class='add'>+				compatible = "samsung,exynos8895-hsi2c";</div><div class='add'>+				reg = &lt;0x0 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI05_I_PCLK&gt;;</div><div class='add'>+				clock-names = "hsi2c";</div><div class='add'>+				interrupts = &lt;GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c15_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_7: serial@0 {</div><div class='add'>+				compatible = "samsung,exynos8895-uart";</div><div class='add'>+				reg = &lt;0x0 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI05_I_PCLK&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI05_I_SCLK_USI&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart7_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_7: spi@0 {</div><div class='add'>+				compatible = "samsung,exynos8895-spi",</div><div class='add'>+					     "samsung,exynos850-spi";</div><div class='add'>+				reg = &lt;0x0 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI05_I_PCLK&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI05_I_SCLK_USI&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi7_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			hsi2c_16: i2c@10000 {</div><div class='add'>+				compatible = "samsung,exynos8895-hsi2c";</div><div class='add'>+				reg = &lt;0x10000 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI05_I_PCLK&gt;;</div><div class='add'>+				clock-names = "hsi2c";</div><div class='add'>+				interrupts = &lt;GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c16_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi6: usi@10880000 {</div><div class='add'>+			compatible = "samsung,exynos8895-usi";</div><div class='add'>+			ranges = &lt;0x0 0x10880000 0x11000&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI06_I_PCLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI06_I_SCLK_USI&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric1 0x1010&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_17: i2c@0 {</div><div class='add'>+				compatible = "samsung,exynos8895-hsi2c";</div><div class='add'>+				reg = &lt;0x0 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI06_I_PCLK&gt;;</div><div class='add'>+				clock-names = "hsi2c";</div><div class='add'>+				interrupts = &lt;GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c17_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_8: serial@0 {</div><div class='add'>+				compatible = "samsung,exynos8895-uart";</div><div class='add'>+				reg = &lt;0x0 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI06_I_PCLK&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI06_I_SCLK_USI&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart8_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_8: spi@0 {</div><div class='add'>+				compatible = "samsung,exynos8895-spi",</div><div class='add'>+					     "samsung,exynos850-spi";</div><div class='add'>+				reg = &lt;0x0 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI06_I_PCLK&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI06_I_SCLK_USI&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi8_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			hsi2c_18: i2c@10000 {</div><div class='add'>+				compatible = "samsung,exynos8895-hsi2c";</div><div class='add'>+				reg = &lt;0x10000 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI06_I_PCLK&gt;;</div><div class='add'>+				clock-names = "hsi2c";</div><div class='add'>+				interrupts = &lt;GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c18_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi7: usi@108a0000 {</div><div class='add'>+			compatible = "samsung,exynos8895-usi";</div><div class='add'>+			ranges = &lt;0x0 0x108a0000 0x11000&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI07_I_PCLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI07_I_SCLK_USI&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric1 0x1014&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_19: i2c@0 {</div><div class='add'>+				compatible = "samsung,exynos8895-hsi2c";</div><div class='add'>+				reg = &lt;0x0 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI07_I_PCLK&gt;;</div><div class='add'>+				clock-names = "hsi2c";</div><div class='add'>+				interrupts = &lt;GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c19_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_9: serial@0 {</div><div class='add'>+				compatible = "samsung,exynos8895-uart";</div><div class='add'>+				reg = &lt;0x0 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI07_I_PCLK&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI07_I_SCLK_USI&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart9_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_9: spi@0 {</div><div class='add'>+				compatible = "samsung,exynos8895-spi",</div><div class='add'>+					     "samsung,exynos850-spi";</div><div class='add'>+				reg = &lt;0x0 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI07_I_PCLK&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI07_I_SCLK_USI&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi9_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			hsi2c_20: i2c@10000 {</div><div class='add'>+				compatible = "samsung,exynos8895-hsi2c";</div><div class='add'>+				reg = &lt;0x10000 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI07_I_PCLK&gt;;</div><div class='add'>+				clock-names = "hsi2c";</div><div class='add'>+				interrupts = &lt;GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c20_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi8: usi@108c0000 {</div><div class='add'>+			compatible = "samsung,exynos8895-usi";</div><div class='add'>+			ranges = &lt;0x0 0x108c0000 0x11000&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI08_I_PCLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI08_I_SCLK_USI&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric1 0x1018&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_21: i2c@0 {</div><div class='add'>+				compatible = "samsung,exynos8895-hsi2c";</div><div class='add'>+				reg = &lt;0x0 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI08_I_PCLK&gt;;</div><div class='add'>+				clock-names = "hsi2c";</div><div class='add'>+				interrupts = &lt;GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c21_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_10: serial@0 {</div><div class='add'>+				compatible = "samsung,exynos8895-uart";</div><div class='add'>+				reg = &lt;0x0 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI08_I_PCLK&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI08_I_SCLK_USI&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart10_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_10: spi@0 {</div><div class='add'>+				compatible = "samsung,exynos8895-spi",</div><div class='add'>+					     "samsung,exynos850-spi";</div><div class='add'>+				reg = &lt;0x0 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI08_I_PCLK&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI08_I_SCLK_USI&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi10_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			hsi2c_22: i2c@10000 {</div><div class='add'>+				compatible = "samsung,exynos8895-hsi2c";</div><div class='add'>+				reg = &lt;0x10000 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI08_I_PCLK&gt;;</div><div class='add'>+				clock-names = "hsi2c";</div><div class='add'>+				interrupts = &lt;GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c22_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi9: usi@108e0000 {</div><div class='add'>+			compatible = "samsung,exynos8895-usi";</div><div class='add'>+			ranges = &lt;0x0 0x108e0000 0x11000&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI09_I_PCLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI09_I_SCLK_USI&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric1 0x101c&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_23: i2c@0 {</div><div class='add'>+				compatible = "samsung,exynos8895-hsi2c";</div><div class='add'>+				reg = &lt;0x0 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI09_I_PCLK&gt;;</div><div class='add'>+				clock-names = "hsi2c";</div><div class='add'>+				interrupts = &lt;GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c23_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_11: serial@0 {</div><div class='add'>+				compatible = "samsung,exynos8895-uart";</div><div class='add'>+				reg = &lt;0 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI09_I_PCLK&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI09_I_SCLK_USI&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart11_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_11: spi@0 {</div><div class='add'>+				compatible = "samsung,exynos8895-spi",</div><div class='add'>+					     "samsung,exynos850-spi";</div><div class='add'>+				reg = &lt;0 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI09_I_PCLK&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI09_I_SCLK_USI&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi11_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			hsi2c_24: i2c@10000 {</div><div class='add'>+				compatible = "samsung,exynos8895-hsi2c";</div><div class='add'>+				reg = &lt;0x10000 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI09_I_PCLK&gt;;</div><div class='add'>+				clock-names = "hsi2c";</div><div class='add'>+				interrupts = &lt;GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c24_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi10: usi@10900000 {</div><div class='add'>+			compatible = "samsung,exynos8895-usi";</div><div class='add'>+			ranges = &lt;0x0 0x10900000 0x11000&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI10_I_PCLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI10_I_SCLK_USI&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric1 0x1020&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_25: i2c@0 {</div><div class='add'>+				compatible = "samsung,exynos8895-hsi2c";</div><div class='add'>+				reg = &lt;0x0 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI10_I_PCLK&gt;;</div><div class='add'>+				clock-names = "hsi2c";</div><div class='add'>+				interrupts = &lt;GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c25_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_12: serial@0 {</div><div class='add'>+				compatible = "samsung,exynos8895-uart";</div><div class='add'>+				reg = &lt;0 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI10_I_PCLK&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI10_I_SCLK_USI&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart12_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_12: spi@0 {</div><div class='add'>+				compatible = "samsung,exynos8895-spi",</div><div class='add'>+					     "samsung,exynos850-spi";</div><div class='add'>+				reg = &lt;0 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI10_I_PCLK&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI10_I_SCLK_USI&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi12_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			hsi2c_26: i2c@10000 {</div><div class='add'>+				compatible = "samsung,exynos8895-hsi2c";</div><div class='add'>+				reg = &lt;0x10000 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI10_I_PCLK&gt;;</div><div class='add'>+				clock-names = "hsi2c";</div><div class='add'>+				interrupts = &lt;GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c26_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi11: usi@10920000 {</div><div class='add'>+			compatible = "samsung,exynos8895-usi";</div><div class='add'>+			ranges = &lt;0x0 0x10920000 0x11000&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI11_I_PCLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI11_I_SCLK_USI&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric1 0x1024&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_27: i2c@0 {</div><div class='add'>+				compatible = "samsung,exynos8895-hsi2c";</div><div class='add'>+				reg = &lt;0x0 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI11_I_PCLK&gt;;</div><div class='add'>+				clock-names = "hsi2c";</div><div class='add'>+				interrupts = &lt;GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c27_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_13: serial@0 {</div><div class='add'>+				compatible = "samsung,exynos8895-uart";</div><div class='add'>+				reg = &lt;0 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI11_I_PCLK&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI11_I_SCLK_USI&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart13_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_13: spi@0 {</div><div class='add'>+				compatible = "samsung,exynos8895-spi",</div><div class='add'>+					     "samsung,exynos850-spi";</div><div class='add'>+				reg = &lt;0 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI11_I_PCLK&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI11_I_SCLK_USI&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi13_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			hsi2c_28: i2c@10000 {</div><div class='add'>+				compatible = "samsung,exynos8895-hsi2c";</div><div class='add'>+				reg = &lt;0x10000 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI11_I_PCLK&gt;;</div><div class='add'>+				clock-names = "hsi2c";</div><div class='add'>+				interrupts = &lt;GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c28_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi12: usi@10940000 {</div><div class='add'>+			compatible = "samsung,exynos8895-usi";</div><div class='add'>+			ranges = &lt;0x0 0x10940000 0x11000&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI12_I_PCLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI12_I_SCLK_USI&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric1 0x1028&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_29: i2c@0 {</div><div class='add'>+				compatible = "samsung,exynos8895-hsi2c";</div><div class='add'>+				reg = &lt;0x0 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI12_I_PCLK&gt;;</div><div class='add'>+				clock-names = "hsi2c";</div><div class='add'>+				interrupts = &lt;GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c29_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_14: serial@0 {</div><div class='add'>+				compatible = "samsung,exynos8895-uart";</div><div class='add'>+				reg = &lt;0 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI12_I_PCLK&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI12_I_SCLK_USI&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart14_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_14: spi@0 {</div><div class='add'>+				compatible = "samsung,exynos8895-spi",</div><div class='add'>+					     "samsung,exynos850-spi";</div><div class='add'>+				reg = &lt;0 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI12_I_PCLK&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI12_I_SCLK_USI&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi14_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			hsi2c_30: i2c@10000 {</div><div class='add'>+				compatible = "samsung,exynos8895-hsi2c";</div><div class='add'>+				reg = &lt;0x10000 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI12_I_PCLK&gt;;</div><div class='add'>+				clock-names = "hsi2c";</div><div class='add'>+				interrupts = &lt;GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c30_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi13: usi@10960000 {</div><div class='add'>+			compatible = "samsung,exynos8895-usi";</div><div class='add'>+			ranges = &lt;0x0 0x10960000 0x11000&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI13_I_PCLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI13_I_SCLK_USI&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric1 0x102c&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_31: i2c@0 {</div><div class='add'>+				compatible = "samsung,exynos8895-hsi2c";</div><div class='add'>+				reg = &lt;0x0 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI13_I_PCLK&gt;;</div><div class='add'>+				clock-names = "hsi2c";</div><div class='add'>+				interrupts = &lt;GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c31_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_15: serial@0 {</div><div class='add'>+				compatible = "samsung,exynos8895-uart";</div><div class='add'>+				reg = &lt;0 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI13_I_PCLK&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI13_I_SCLK_USI&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart15_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_15: spi@0 {</div><div class='add'>+				compatible = "samsung,exynos8895-spi",</div><div class='add'>+					     "samsung,exynos850-spi";</div><div class='add'>+				reg = &lt;0 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI13_I_PCLK&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI13_I_SCLK_USI&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi15_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			hsi2c_32: i2c@10000 {</div><div class='add'>+				compatible = "samsung,exynos8895-hsi2c";</div><div class='add'>+				reg = &lt;0x10000 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_USI13_I_PCLK&gt;;</div><div class='add'>+				clock-names = "hsi2c";</div><div class='add'>+				interrupts = &lt;GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c32_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_peric1: pinctrl@10980000 {</div><div class='add'>+			compatible = "samsung,exynos8895-pinctrl";</div><div class='add'>+			reg = &lt;0x10980000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		hsi2c_1: i2c@10990000 {</div><div class='add'>+			compatible = "samsung,exynos8895-hsi2c";</div><div class='add'>+			reg = &lt;0x10990000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_HSI2C_CAM0_IPCLK&gt;;</div><div class='add'>+			clock-names = "hsi2c";</div><div class='add'>+			interrupts = &lt;GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;hsi2c1_bus&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		hsi2c_2: i2c@109a0000 {</div><div class='add'>+			compatible = "samsung,exynos8895-hsi2c";</div><div class='add'>+			reg = &lt;0x109a0000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_HSI2C_CAM1_IPCLK&gt;;</div><div class='add'>+			clock-names = "hsi2c";</div><div class='add'>+			interrupts = &lt;GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;hsi2c2_bus&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		hsi2c_3: i2c@109b0000 {</div><div class='add'>+			compatible = "samsung,exynos8895-hsi2c";</div><div class='add'>+			reg = &lt;0x109b0000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_HSI2C_CAM2_IPCLK&gt;;</div><div class='add'>+			clock-names = "hsi2c";</div><div class='add'>+			interrupts = &lt;GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;hsi2c3_bus&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		hsi2c_4: i2c@109c0000 {</div><div class='add'>+			compatible = "samsung,exynos8895-hsi2c";</div><div class='add'>+			reg = &lt;0x109c0000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_HSI2C_CAM3_IPCLK&gt;;</div><div class='add'>+			clock-names = "hsi2c";</div><div class='add'>+			interrupts = &lt;GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;hsi2c4_bus&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi_0: spi@109d0000 {</div><div class='add'>+			compatible = "samsung,exynos8895-spi",</div><div class='add'>+				     "samsung,exynos850-spi";</div><div class='add'>+			reg = &lt;0x109d0000 0x100&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_SPI_CAM0_PCLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_SPI_CAM0_SPI_EXT_CLK&gt;;</div><div class='add'>+			clock-names = "spi", "spi_busclk0";</div><div class='add'>+			interrupts = &lt;GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;spi0_bus&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi_1: spi@109e0000 {</div><div class='add'>+			compatible = "samsung,exynos8895-spi",</div><div class='add'>+				     "samsung,exynos850-spi";</div><div class='add'>+			reg = &lt;0x109e0000 0x100&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_SPI_CAM1_PCLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_SPI_CAM1_SPI_EXT_CLK&gt;;</div><div class='add'>+			clock-names = "spi", "spi_busclk0";</div><div class='add'>+			interrupts = &lt;GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;spi1_bus&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_fsys0: clock-controller@11000000 {</div><div class='add'>+			compatible = "samsung,exynos8895-cmu-fsys0";</div><div class='add'>+			reg = &lt;0x11000000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;oscclk&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_FSYS0_BUS&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_FSYS0_DPGTC&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_FSYS0_MMC_EMBD&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_FSYS0_UFS_EMBD&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_FSYS0_USBDRD30&gt;;</div><div class='add'>+			clock-names = "oscclk", "bus", "dpgtc", "mmc",</div><div class='add'>+				      "ufs", "usbdrd30";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		syscon_fsys0: syscon@11020000 {</div><div class='add'>+			compatible = "samsung,exynos8895-fsys0-sysreg", "syscon";</div><div class='add'>+			reg = &lt;0x11020000 0x2000&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_fsys0 CLK_GOUT_FSYS0_SYSREG_FSYS0_PCLK&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_fsys0: pinctrl@11050000 {</div><div class='add'>+			compatible = "samsung,exynos8895-pinctrl";</div><div class='add'>+			reg = &lt;0x11050000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_fsys1: clock-controller@11400000 {</div><div class='add'>+			compatible = "samsung,exynos8895-cmu-fsys1";</div><div class='add'>+			reg = &lt;0x11400000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;oscclk&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_FSYS1_BUS&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_FSYS1_PCIE&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_FSYS1_UFS_CARD&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_FSYS1_MMC_CARD&gt;;</div><div class='add'>+			clock-names = "oscclk", "bus", "pcie", "ufs", "mmc";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		syscon_fsys1: syscon@11420000 {</div><div class='add'>+			compatible = "samsung,exynos8895-fsys1-sysreg", "syscon";</div><div class='add'>+			reg = &lt;0x11420000 0x2000&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_fsys1 CLK_GOUT_FSYS1_SYSREG_FSYS1_PCLK&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_fsys1: pinctrl@11430000 {</div><div class='add'>+			compatible = "samsung,exynos8895-pinctrl";</div><div class='add'>+			reg = &lt;0x11430000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmc: mmc@11500000 {</div><div class='add'>+			compatible = "samsung,exynos8895-dw-mshc-smu",</div><div class='add'>+				     "samsung,exynos7-dw-mshc-smu";</div><div class='add'>+			reg = &lt;0x11500000 0x2000&gt;;</div><div class='add'>+			assigned-clocks = &lt;&amp;cmu_top CLK_MOUT_CMU_FSYS1_MMC_CARD&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;cmu_top CLK_FOUT_SHARED4_PLL&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_fsys1 CLK_GOUT_FSYS1_MMC_CARD_I_ACLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_fsys1 CLK_GOUT_FSYS1_MMC_CARD_SDCLKIN&gt;;</div><div class='add'>+			clock-names = "biu", "ciu";</div><div class='add'>+			fifo-depth = &lt;64&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_abox: pinctrl@13e60000 {</div><div class='add'>+			compatible = "samsung,exynos8895-pinctrl";</div><div class='add'>+			reg = &lt;0x13e60000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_vts: pinctrl@14080000 {</div><div class='add'>+			compatible = "samsung,exynos8895-pinctrl";</div><div class='add'>+			reg = &lt;0x14080000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_busc: pinctrl@15a30000 {</div><div class='add'>+			compatible = "samsung,exynos8895-pinctrl";</div><div class='add'>+			reg = &lt;0x15a30000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_top: clock-controller@15a80000 {</div><div class='add'>+			compatible = "samsung,exynos8895-cmu-top";</div><div class='add'>+			reg = &lt;0x15a80000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;oscclk&gt;;</div><div class='add'>+			clock-names = "oscclk";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmu_system_controller: system-controller@16480000 {</div><div class='add'>+			compatible = "samsung,exynos8895-pmu",</div><div class='add'>+				     "samsung,exynos7-pmu", "syscon";</div><div class='add'>+			reg = &lt;0x16480000 0x10000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_alive: pinctrl@164b0000 {</div><div class='add'>+			compatible = "samsung,exynos8895-pinctrl";</div><div class='add'>+			reg = &lt;0x164b0000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			wakeup-interrupt-controller {</div><div class='add'>+				compatible = "samsung,exynos8895-wakeup-eint",</div><div class='add'>+					     "samsung,exynos7-wakeup-eint";</div><div class='add'>+				interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		/* Hypervisor Virtual Timer interrupt is not wired to GIC */</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+		/*</div><div class='add'>+		 * Non-updatable, broken stock Samsung bootloader does not</div><div class='add'>+		 * configure CNTFRQ_EL0</div><div class='add'>+		 */</div><div class='add'>+		clock-frequency = &lt;26000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include "exynos8895-pinctrl.dtsi"</div><div class='add'>+#include "arm/samsung/exynos-syscon-restart.dtsi"</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/exynos9810-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos9810-pinctrl.dtsi<br/>new file mode 100644<br/>index 000000000000..88091bf09e4e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynos9810-pinctrl.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/exynos9810-pinctrl.dtsi</a></div><div class='hunk'>@@ -0,0 +1,503 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause</div><div class='add'>+/*</div><div class='add'>+ * Samsung's Exynos 9810 SoC pin-mux and pin-config device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2024 Markuss Broks &lt;markuss.broks@gmail.com&gt;</div><div class='add'>+ * Copyright (c) 2024 Maksym Holovach &lt;nergzd@nergzd723.xyz&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "exynos-pinctrl.h"</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_alive {</div><div class='add'>+	etc1: etc1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpa0: gpa0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpa1: gpa1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpa2: gpa2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpa3: gpa3-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpa4: gpa4-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpq0: gpq0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_aud {</div><div class='add'>+	gpb0: gpb0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpb1: gpb1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpb2: gpb2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_chub {</div><div class='add'>+	gph0: gph0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gph1: gph1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_cmgp {</div><div class='add'>+	gpm0: gpm0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupts = &lt;GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm1: gpm1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupts = &lt;GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm2: gpm2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupts = &lt;GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm3: gpm3-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupts = &lt;GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm4: gpm4-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupts = &lt;GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm5: gpm5-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupts = &lt;GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm6: gpm6-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupts = &lt;GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm7: gpm7-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupts = &lt;GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm10: gpm10-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupts = &lt;GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm11: gpm11-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupts = &lt;GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm12: gpm12-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupts = &lt;GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm13: gpm13-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupts = &lt;GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm14: gpm14-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupts = &lt;GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm15: gpm15-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupts = &lt;GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm16: gpm16-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupts = &lt;GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm17: gpm17-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupts = &lt;GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm40: gpm40-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupts = &lt;GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm41: gpm41-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupts = &lt;GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm42: gpm42-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupts = &lt;GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm43: gpm43-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupts = &lt;GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_fsys0 {</div><div class='add'>+	gpf0: gpf0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_fsys1 {</div><div class='add'>+	gpf1: gpf1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpf2: gpf2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_peric0 {</div><div class='add'>+	gpg0: gpg0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpg1: gpg1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpg2: gpg2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp0: gpp0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp1: gpp1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp2: gpp2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp3: gpp3-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_peric1 {</div><div class='add'>+	gpc0: gpc0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpc1: gpc1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpd0: gpd0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpg3: gpg3-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp4: gpp4-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp5: gpp5-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp6: gpp6-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_vts {</div><div class='add'>+	gpt0: gpt0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/exynos9810-starlte.dts b/arch/arm64/boot/dts/exynos/exynos9810-starlte.dts<br/>new file mode 100644<br/>index 000000000000..fc0ddfee4cd6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynos9810-starlte.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/exynos9810-starlte.dts</a></div><div class='hunk'>@@ -0,0 +1,119 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause</div><div class='add'>+/*</div><div class='add'>+ * Samsung Galaxy S9 (starlte/SM-G960F) device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2024 Markuss Broks &lt;markuss.broks@gmail.com&gt;</div><div class='add'>+ * Copyright (c) 2024 Maksym Holovach &lt;nergzd@nergzd723.xyz&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "exynos9810.dtsi"</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Samsung Galaxy S9 (SM-G960F)";</div><div class='add'>+	compatible = "samsung,starlte", "samsung,exynos9810";</div><div class='add'>+	chassis-type = "handset";</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		framebuffer@cc000000 {</div><div class='add'>+			compatible = "simple-framebuffer";</div><div class='add'>+			reg = &lt;0x0 0xcc000000 (1440 * 2960 * 4)&gt;;</div><div class='add'>+			width = &lt;1440&gt;;</div><div class='add'>+			height = &lt;2960&gt;;</div><div class='add'>+			stride = &lt;(1440 * 4)&gt;;</div><div class='add'>+			format = "a8r8g8b8";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;key_power &amp;key_voldown &amp;key_volup &amp;key_wink&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		power-key {</div><div class='add'>+			label = "Power";</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpa2 4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		voldown-key {</div><div class='add'>+			label = "Volume Down";</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpa0 4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		volup-key {</div><div class='add'>+			label = "Volume Up";</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpa0 3 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* In stock firmware used for assistant. Map it as a camera button for now */</div><div class='add'>+		wink-key {</div><div class='add'>+			label = "Camera";</div><div class='add'>+			linux,code = &lt;KEY_CAMERA&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpa0 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@80000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x80000000 0x3c800000&gt;,</div><div class='add'>+		      &lt;0x0 0xc0000000 0x20000000&gt;,</div><div class='add'>+		      &lt;0x0 0xe1900000 0x1e700000&gt;,</div><div class='add'>+		      &lt;0x8 0x80000000 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		framebuffer@cc000000 {</div><div class='add'>+			reg = &lt;0x0 0xcc000000 (1440 * 2960 * 4)&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;oscclk {</div><div class='add'>+	clock-frequency = &lt;26000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_alive {</div><div class='add'>+	key_power: key-power-pins {</div><div class='add'>+		samsung,pins = "gpa2-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	key_voldown: key-voldown-pins {</div><div class='add'>+		samsung,pins = "gpa0-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	key_volup: key-volup-pins {</div><div class='add'>+		samsung,pins = "gpa0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	key_wink: key-wink-pins {</div><div class='add'>+		samsung,pins = "gpa0-6";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/exynos9810.dtsi b/arch/arm64/boot/dts/exynos/exynos9810.dtsi<br/>new file mode 100644<br/>index 000000000000..01eba31f7ca3<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynos9810.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/exynos9810.dtsi</a></div><div class='hunk'>@@ -0,0 +1,273 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause</div><div class='add'>+/*</div><div class='add'>+ * Samsung Exynos 9810 SoC device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2024 Markuss Broks &lt;markuss.broks@gmail.com&gt;</div><div class='add'>+ * Copyright (c) 2024 Maksym Holovach &lt;nergzd@nergzd723.xyz&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "samsung,exynos9810";</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		pinctrl0 = &amp;pinctrl_alive;</div><div class='add'>+		pinctrl1 = &amp;pinctrl_aud;</div><div class='add'>+		pinctrl2 = &amp;pinctrl_chub;</div><div class='add'>+		pinctrl3 = &amp;pinctrl_cmgp;</div><div class='add'>+		pinctrl4 = &amp;pinctrl_fsys0;</div><div class='add'>+		pinctrl5 = &amp;pinctrl_fsys1;</div><div class='add'>+		pinctrl6 = &amp;pinctrl_peric0;</div><div class='add'>+		pinctrl7 = &amp;pinctrl_peric1;</div><div class='add'>+		pinctrl8 = &amp;pinctrl_vts;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu-map {</div><div class='add'>+			cluster0 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu0&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu1&gt;;</div><div class='add'>+				};</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu2&gt;;</div><div class='add'>+				};</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu3&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cluster1 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu4&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu5&gt;;</div><div class='add'>+				};</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu6&gt;;</div><div class='add'>+				};</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu7&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@1 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x1&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@2 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x2&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@3 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x3&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu4: cpu@100 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "samsung,mongoose-m3";</div><div class='add'>+			reg = &lt;0x100&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu5: cpu@101 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "samsung,mongoose-m3";</div><div class='add'>+			reg = &lt;0x101&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu6: cpu@102 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "samsung,mongoose-m3";</div><div class='add'>+			reg = &lt;0x102&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu7: cpu@103 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "samsung,mongoose-m3";</div><div class='add'>+			reg = &lt;0x103&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	oscclk: osc-clock {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-output-names = "oscclk";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu-a55 {</div><div class='add'>+		compatible = "arm,cortex-a55-pmu";</div><div class='add'>+		interrupts = &lt;GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-affinity = &lt;&amp;cpu0&gt;,</div><div class='add'>+				     &lt;&amp;cpu1&gt;,</div><div class='add'>+				     &lt;&amp;cpu2&gt;,</div><div class='add'>+				     &lt;&amp;cpu3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu-mongoose-m3 {</div><div class='add'>+		compatible = "samsung,mongoose-pmu";</div><div class='add'>+		interrupts = &lt;GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-affinity = &lt;&amp;cpu4&gt;,</div><div class='add'>+				     &lt;&amp;cpu5&gt;,</div><div class='add'>+				     &lt;&amp;cpu6&gt;,</div><div class='add'>+				     &lt;&amp;cpu7&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci";</div><div class='add'>+		method = "smc";</div><div class='add'>+		cpu_off = &lt;0x84000002&gt;;</div><div class='add'>+		cpu_on = &lt;0xc4000003&gt;;</div><div class='add'>+		cpu_suspend = &lt;0xc4000001&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc: soc@0 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		ranges = &lt;0x0 0x0 0x0 0x20000000&gt;;</div><div class='add'>+</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		chipid@10000000 {</div><div class='add'>+			compatible = "samsung,exynos9810-chipid",</div><div class='add'>+				     "samsung,exynos850-chipid";</div><div class='add'>+			reg = &lt;0x10000000 0x100&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@10101000 {</div><div class='add'>+			compatible = "arm,gic-400";</div><div class='add'>+			reg = &lt;0x10101000 0x1000&gt;,</div><div class='add'>+			      &lt;0x10102000 0x1000&gt;,</div><div class='add'>+			      &lt;0x10104000 0x2000&gt;,</div><div class='add'>+			      &lt;0x10106000 0x2000&gt;;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |</div><div class='add'>+						 IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='add'>+			#address-cells = &lt;0&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_peric0: pinctrl@10430000 {</div><div class='add'>+			compatible = "samsung,exynos9810-pinctrl";</div><div class='add'>+			reg = &lt;0x10430000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_peric1: pinctrl@10830000 {</div><div class='add'>+			compatible = "samsung,exynos9810-pinctrl";</div><div class='add'>+			reg = &lt;0x10830000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_fsys0: pinctrl@11050000 {</div><div class='add'>+			compatible = "samsung,exynos9810-pinctrl";</div><div class='add'>+			reg = &lt;0x11050000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_fsys1: pinctrl@11430000 {</div><div class='add'>+			compatible = "samsung,exynos9810-pinctrl";</div><div class='add'>+			reg = &lt;0x11430000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_vts: pinctrl@13880000 {</div><div class='add'>+			compatible = "samsung,exynos9810-pinctrl";</div><div class='add'>+			reg = &lt;0x13880000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_chub: pinctrl@13a80000 {</div><div class='add'>+			compatible = "samsung,exynos9810-pinctrl";</div><div class='add'>+			reg = &lt;0x13a80000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_alive: pinctrl@14050000 {</div><div class='add'>+			compatible = "samsung,exynos9810-pinctrl";</div><div class='add'>+			reg = &lt;0x14050000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			wakeup-interrupt-controller {</div><div class='add'>+				compatible = "samsung,exynos9810-wakeup-eint",</div><div class='add'>+					     "samsung,exynos850-wakeup-eint",</div><div class='add'>+					     "samsung,exynos7-wakeup-eint";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmu_system_controller: system-controller@14060000 {</div><div class='add'>+			compatible = "samsung,exynos9810-pmu",</div><div class='add'>+				     "samsung,exynos7-pmu", "syscon";</div><div class='add'>+			reg = &lt;0x14060000 0x10000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_cmgp: pinctrl@14220000 {</div><div class='add'>+			compatible = "samsung,exynos9810-pinctrl";</div><div class='add'>+			reg = &lt;0x14220000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			wakeup-interrupt-controller {</div><div class='add'>+				compatible = "samsung,exynos9810-wakeup-eint",</div><div class='add'>+					     "samsung,exynos850-wakeup-eint",</div><div class='add'>+					     "samsung,exynos7-wakeup-eint";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_aud: pinctrl@17c60000 {</div><div class='add'>+			compatible = "samsung,exynos9810-pinctrl";</div><div class='add'>+			reg = &lt;0x17c60000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		/* Hypervisor Virtual Timer interrupt is not wired to GIC */</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+		/*</div><div class='add'>+		 * Non-updatable, broken stock Samsung bootloader does not</div><div class='add'>+		 * configure CNTFRQ_EL0</div><div class='add'>+		 */</div><div class='add'>+		clock-frequency = &lt;26000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include "exynos9810-pinctrl.dtsi"</div><div class='add'>+#include "arm/samsung/exynos-syscon-restart.dtsi"</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/exynos990-c1s.dts b/arch/arm64/boot/dts/exynos/exynos990-c1s.dts<br/>new file mode 100644<br/>index 000000000000..9f0ad4f9673a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynos990-c1s.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/exynos990-c1s.dts</a></div><div class='hunk'>@@ -0,0 +1,131 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause</div><div class='add'>+/*</div><div class='add'>+ * Samsung Galaxy Note20 5G (c1s/SM-N981B) device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2024, Igor Belwon &lt;igor.belwon@mentallysanemainliners.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "exynos990.dtsi"</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Samsung Galaxy Note20";</div><div class='add'>+	compatible = "samsung,c1s", "samsung,exynos990";</div><div class='add'>+</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		framebuffer0: framebuffer@f1000000 {</div><div class='add'>+			compatible = "simple-framebuffer";</div><div class='add'>+			reg = &lt;0 0xf1000000 0 (1080 * 2400 * 4)&gt;;</div><div class='add'>+			width = &lt;1080&gt;;</div><div class='add'>+			height = &lt;2400&gt;;</div><div class='add'>+			stride = &lt;(1080 * 4)&gt;;</div><div class='add'>+			format = "a8r8g8b8";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@80000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x80000000 0x0 0x3ab00000&gt;,</div><div class='add'>+		      /* Memory hole */</div><div class='add'>+		      &lt;0x0 0xc1200000 0x0 0x1ee00000&gt;,</div><div class='add'>+		      /* Memory hole */</div><div class='add'>+		      &lt;0x0 0xe1900000 0x0 0x1e700000&gt;,</div><div class='add'>+		      /* Memory hole - last block */</div><div class='add'>+		      &lt;0x8 0x80000000 0x1 0x7ec00000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* TODO: Remove this once PMIC is implemented */</div><div class='add'>+	reg_dummy: regulator-0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "dummy_reg";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		cont_splash_mem: framebuffer@f1000000 {</div><div class='add'>+			reg = &lt;0 0xf1000000 0 0x13c6800&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		abox_reserved: audio@f7fb0000 {</div><div class='add'>+			reg = &lt;0 0xf7fb0000 0 0x2a50000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;key_power &amp;key_voldown &amp;key_volup&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		power-key {</div><div class='add'>+			label = "Power";</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpa2 4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		voldown-key {</div><div class='add'>+			label = "Volume Down";</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpa0 4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		volup-key {</div><div class='add'>+			label = "Volume Up";</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpa0 3 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;oscclk {</div><div class='add'>+	clock-frequency = &lt;26000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_alive {</div><div class='add'>+	key_power: key-power-pins {</div><div class='add'>+		samsung,pins = "gpa2-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	key_voldown: key-voldown-pins {</div><div class='add'>+		samsung,pins = "gpa0-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	key_volup: key-volup-pins {</div><div class='add'>+		samsung,pins = "gpa0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbdrd {</div><div class='add'>+	status = "okay";</div><div class='add'>+	vdd10-supply = &lt;&amp;reg_dummy&gt;;</div><div class='add'>+	vdd33-supply = &lt;&amp;reg_dummy&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbdrd_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/exynos990-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos990-pinctrl.dtsi<br/>new file mode 100644<br/>index 000000000000..a03d36458d76<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynos990-pinctrl.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/exynos990-pinctrl.dtsi</a></div><div class='hunk'>@@ -0,0 +1,2195 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause</div><div class='add'>+/*</div><div class='add'>+ * Samsung Exynos 990 pin-mux and pin-config device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2024, Igor Belwon &lt;igor.belwon@mentallysanemainliners.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include "exynos-pinctrl.h"</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_alive {</div><div class='add'>+	gpa0: gpa0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpa1: gpa1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpa2: gpa2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpa3: gpa3-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpa4: gpa4-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpq0: gpq0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	speedy_bus: speedy-bus-pins {</div><div class='add'>+		samsung,pins = "gpq0-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	speedy1_bus: speedy1-bus-pins {</div><div class='add'>+		samsung,pins = "gpq0-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* UART1 is also referred to as UART_BT in downstream. */</div><div class='add'>+	uart1_bus_single: uart1-bus-pins {</div><div class='add'>+		samsung,pins = "gpq0-3", "gpq0-2", "gpq0-1", "gpq0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart1_rxd_pull: uart1-bus-rxd-pins {</div><div class='add'>+		samsung,pins = "gpq0-0";</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart1_bus_rts: uart1-bus-rts-pins {</div><div class='add'>+		samsung,pins = "gpq0-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart1_bus_tx_input: uart1-bus-tx-input-pins {</div><div class='add'>+		samsung,pins = "gpq0-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart1_bus_tx_dat: uart1-bus-tx-dat-pins {</div><div class='add'>+		samsung,pins = "gpq0-1";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart1_bus_tx_con: uart1-bus-tx-con-pins {</div><div class='add'>+		samsung,pins = "gpq0-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wlan_host_wake: wlan-host-wake-pins {</div><div class='add'>+		samsung,pins = "gpa0-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_cmgp {</div><div class='add'>+	gpm0: gpm0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm1: gpm1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm2: gpm2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm3: gpm3-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm4: gpm4-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm5: gpm5-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm6: gpm6-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm7: gpm7-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm8: gpm8-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm9: gpm9-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm10: gpm10-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm11: gpm11-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm12: gpm12-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm13: gpm13-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm14: gpm14-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm15: gpm15-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm16: gpm16-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm17: gpm17-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm18: gpm18-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm19: gpm19-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm20: gpm20-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm21: gpm21-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm22: gpm22-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm23: gpm23-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm24: gpm24-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm25: gpm25-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm26: gpm26-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm27: gpm27-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm28: gpm28-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm29: gpm29-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm30: gpm30-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm31: gpm31-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm32: gpm32-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpm33: gpm33-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c38_bus: hsi2c38-bus-pins {</div><div class='add'>+		samsung,pins = "gpm0-0", "gpm1-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c39_bus: hsi2c39-bus-pins {</div><div class='add'>+		samsung,pins = "gpm2-0", "gpm3-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c40_bus: hsi2c40-bus-pins {</div><div class='add'>+		samsung,pins = "gpm4-0", "gpm5-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c41_bus: hsi2c41-bus-pins {</div><div class='add'>+		samsung,pins = "gpm6-0", "gpm7-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c42_bus: hsi2c42-bus-pins {</div><div class='add'>+		samsung,pins = "gpm8-0", "gpm9-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c43_bus: hsi2c43-bus-pins {</div><div class='add'>+		samsung,pins = "gpm10-0", "gpm11-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c44_bus: hsi2c44-bus-pins {</div><div class='add'>+		samsung,pins = "gpm12-0", "gpm13-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c45_bus: hsi2c45-bus-pins {</div><div class='add'>+		samsung,pins = "gpm14-0", "gpm15-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi19_bus: spi19-bus-pins {</div><div class='add'>+		samsung,pins = "gpm0-0", "gpm1-0", "gpm2-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi19_cs: spi19-cs-pins {</div><div class='add'>+		samsung,pins = "gpm3-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi19_cs_func: spi19-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpm3-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi20_bus: spi20-bus-pins {</div><div class='add'>+		samsung,pins = "gpm4-0", "gpm5-0", "gpm6-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi20_cs: spi20-cs-pins {</div><div class='add'>+		samsung,pins = "gpm7-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi20_cs_func: spi20-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpm7-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi21_bus: spi21-bus-pins {</div><div class='add'>+		samsung,pins = "gpm8-0", "gpm9-0", "gpm10-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi21_cs: spi21-cs-pins {</div><div class='add'>+		samsung,pins = "gpm11-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi21_cs_func: spi21-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpm11-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi22_bus: spi22-bus-pins {</div><div class='add'>+		samsung,pins = "gpm12-0", "gpm13-0", "gpm14-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi22_cs: spi22-cs-pins {</div><div class='add'>+		samsung,pins = "gpm15-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi22_cs_func: spi22-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpm15-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart21_bus_single: uart21-bus-pins {</div><div class='add'>+		samsung,pins = "gpm0-0", "gpm1-0", "gpm2-0", "gpm3-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart21_bus_dual: uart21-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpm0-0", "gpm1-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart22_bus_single: uart22-bus-pins {</div><div class='add'>+		samsung,pins = "gpm4-0", "gpm5-0", "gpm6-0", "gpm7-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart22_bus_dual: uart22-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpm4-0", "gpm5-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart23_bus_single: uart23-bus-pins {</div><div class='add'>+		samsung,pins = "gpm8-0", "gpm9-0", "gpm10-0", "gpm11-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart23_bus_dual: uart23-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpm8-0", "gpm9-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart24_bus_single: uart24-bus-pins {</div><div class='add'>+		samsung,pins = "gpm12-0", "gpm13-0", "gpm14-0", "gpm15-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart24_bus_dual: uart24-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpm12-0", "gpm13-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_hsi1 {</div><div class='add'>+	gpf0: gpf0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpf1: gpf1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpf2: gpf2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_clkreq: pcie0-clkreq-pins {</div><div class='add'>+		samsung,pins = "gpf0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS850_HSI_PIN_DRV_LV2_5&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_perst: pcie0-perst-pins {</div><div class='add'>+		samsung,pins = "gpf0-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS850_HSI_PIN_DRV_LV2_5&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie1_clkreq: pcie1-clkreq-pins {</div><div class='add'>+		samsung,pins = "gpf0-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS850_HSI_PIN_DRV_LV2_5&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie1_perst: pcie1-perst-pins {</div><div class='add'>+		samsung,pins = "gpf0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS850_HSI_PIN_DRV_LV2_5&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ufs_rst_n: ufs-rst-n-pins {</div><div class='add'>+		samsung,pins = "gpf2-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ufs_refclk_out: ufs-refclk-out-pins {</div><div class='add'>+		samsung,pins = "gpf2-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_clk: sd2-clk-pins {</div><div class='add'>+		samsung,pins = "gpf1-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS850_HSI_PIN_DRV_LV3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_cmd: sd2-cmd-pins {</div><div class='add'>+		samsung,pins = "gpf1-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS850_HSI_PIN_DRV_LV2_5&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_bus1: sd2-bus-width1-pins {</div><div class='add'>+		samsung,pins = "gpf1-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS850_HSI_PIN_DRV_LV2_5&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_bus4: sd2-bus-width4-pins {</div><div class='add'>+		samsung,pins = "gpf1-3", "gpf1-4", "gpf1-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS850_HSI_PIN_DRV_LV2_5&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_clk_fast_slew_rate_1x: sd2-clk-fast-slew-rate-1x-pins {</div><div class='add'>+		samsung,pins = "gpf1-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS850_HSI_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_clk_fast_slew_rate_1_5x: sd2-clk-fast-slew-rate-1-5x-pins {</div><div class='add'>+		samsung,pins = "gpf1-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS850_HSI_PIN_DRV_LV1_5&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_clk_fast_slew_rate_2x: sd2-clk-fast-slew-rate-2x-pins {</div><div class='add'>+		samsung,pins = "gpf1-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS850_HSI_PIN_DRV_LV2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_clk_fast_slew_rate_2_5x: sd2-clk-fast-slew-rate-2-5x-pins {</div><div class='add'>+		samsung,pins = "gpf1-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS850_HSI_PIN_DRV_LV2_5&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_clk_fast_slew_rate_3x: sd2-clk-fas-slew-rate-3x-pins {</div><div class='add'>+		samsung,pins = "gpf1-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS850_HSI_PIN_DRV_LV3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_clk_fast_slew_rate_4x: sd2-clk-fast-slew-rate-4x-pins {</div><div class='add'>+		samsung,pins = "gpf1-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS850_HSI_PIN_DRV_LV4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_pins_as_pdn: sd2-pins-as-pdn-pins {</div><div class='add'>+		samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3", "gpf1-4", "gpf1-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_hsi2 {</div><div class='add'>+	gpf3: gpf3-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie2_clkreq: pcie2-clkreq-pins {</div><div class='add'>+		samsung,pins = "gpf3-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV4&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie2_perst: pcie2-perst-pins {</div><div class='add'>+		samsung,pins = "gpf3-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV4&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_peric0 {</div><div class='add'>+	gpg0: gpg0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp0: gpp0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp1: gpp1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp2: gpp2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp3: gpp3-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp4: gpp4-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c0_bus: hsi2c0-bus-pins {</div><div class='add'>+		samsung,pins = "gpp0-0", "gpp0-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c1_bus: hsi2c1-bus-pins {</div><div class='add'>+		samsung,pins = "gpp0-2", "gpp0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c2_bus: hsi2c2-bus-pins {</div><div class='add'>+		samsung,pins = "gpp0-4", "gpp0-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c3_bus: hsi2c3-bus-pins {</div><div class='add'>+		samsung,pins = "gpp0-6", "gpp0-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c4_bus: hsi2c4-bus-pins {</div><div class='add'>+		samsung,pins = "gpp1-0", "gpp1-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c5_bus: hsi2c5-bus-pins {</div><div class='add'>+		samsung,pins = "gpp1-2", "gpp1-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c6_bus: hsi2c6-bus-pins {</div><div class='add'>+		samsung,pins = "gpp1-4", "gpp1-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c7_bus: hsi2c7-bus-pins {</div><div class='add'>+		samsung,pins = "gpp1-6", "gpp1-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c8_bus: hsi2c8-bus-pins {</div><div class='add'>+		samsung,pins = "gpp2-0", "gpp2-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c9_bus: hsi2c9-bus-pins {</div><div class='add'>+		samsung,pins = "gpp2-2", "gpp2-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c10_bus: hsi2c10-bus-pins {</div><div class='add'>+		samsung,pins = "gpp2-4", "gpp2-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c11_bus: hsi2c11-bus-pins {</div><div class='add'>+		samsung,pins = "gpp2-6", "gpp2-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c26_bus: hsi2c26-bus-pins {</div><div class='add'>+		samsung,pins = "gpp3-0", "gpp3-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c27_bus: hsi2c27-bus-pins {</div><div class='add'>+		samsung,pins = "gpp3-2", "gpp3-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c28_bus: hsi2c28-bus-pins {</div><div class='add'>+		samsung,pins = "gpp3-4", "gpp3-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c29_bus: hsi2c29-bus-pins {</div><div class='add'>+		samsung,pins = "gpp3-6", "gpp3-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c30_bus: hsi2c30-bus-pins {</div><div class='add'>+		samsung,pins = "gpp4-0", "gpp4-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c31_bus: hsi2c31-bus-pins {</div><div class='add'>+		samsung,pins = "gpp4-2", "gpp4-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi0_bus: spi0-bus-pins {</div><div class='add'>+		samsung,pins = "gpp0-2", "gpp0-1", "gpp0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi0_cs: spi0-cs-pins {</div><div class='add'>+		samsung,pins = "gpp0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi0_cs_func: spi0-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi1_bus: spi1-bus-pins {</div><div class='add'>+		samsung,pins = "gpp0-6", "gpp0-5", "gpp0-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi1_cs: spi1-cs-pins {</div><div class='add'>+		samsung,pins = "gpp0-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi1_cs_func: spi1-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp0-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi2_bus: spi2-bus-pins {</div><div class='add'>+		samsung,pins = "gpp1-2", "gpp1-1", "gpp1-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi2_cs: spi2-cs-pins {</div><div class='add'>+		samsung,pins = "gpp1-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi2_cs_func: spi2-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp1-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi3_bus: spi3-bus-pins {</div><div class='add'>+		samsung,pins = "gpp1-6", "gpp1-5", "gpp1-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi3_cs: spi3-cs-pins {</div><div class='add'>+		samsung,pins = "gpp1-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi3_cs_func: spi3-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp1-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi4_bus: spi4-bus-pins {</div><div class='add'>+		samsung,pins = "gpp2-2", "gpp2-1", "gpp2-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi4_cs: spi4-cs-pins {</div><div class='add'>+		samsung,pins = "gpp2-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi4_cs_func: spi4-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp2-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi4_fp_inactive: spi4-fp-inactive-pins {</div><div class='add'>+		samsung,pins = "gpp2-3", "gpp2-2", "gpp2-1", "gpp2-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi4_fp_cs_func_high: spi4-fp-cs-func-high-pins {</div><div class='add'>+		samsung,pins = "gpp2-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi5_bus: spi5-bus-pins {</div><div class='add'>+		samsung,pins = "gpp2-6", "gpp2-5", "gpp2-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi5_cs: spi5-cs-pins {</div><div class='add'>+		samsung,pins = "gpp2-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi5_cs_func: spi5-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp2-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi13_bus: spi13-bus-pins {</div><div class='add'>+		samsung,pins = "gpp3-2", "gpp3-1", "gpp3-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi13_cs: spi13-cs-pins {</div><div class='add'>+		samsung,pins = "gpp3-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi13_cs_func: spi13-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp3-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi14_bus: spi14-bus-pins {</div><div class='add'>+		samsung,pins = "gpp3-6", "gpp3-5", "gpp3-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi14_cs: spi14-cs-pins {</div><div class='add'>+		samsung,pins = "gpp3-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi14_cs_func: spi14-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp3-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi15_bus: spi15-bus-pins {</div><div class='add'>+		samsung,pins = "gpp4-2", "gpp4-1", "gpp4-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi15_cs: spi15-cs-pins {</div><div class='add'>+		samsung,pins = "gpp4-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi15_cs_func: spi15-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp4-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart0_bus: uart0-bus-pins {</div><div class='add'>+		samsung,pins = "gpp4-6", "gpp4-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart2_bus_single: uart2-bus-pins {</div><div class='add'>+		samsung,pins = "gpp0-0", "gpp0-1", "gpp0-2", "gpp0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart2_bus_dual: uart2-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp0-0", "gpp0-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart3_bus_single: uart3-bus-pins {</div><div class='add'>+		samsung,pins = "gpp0-4", "gpp0-5", "gpp0-6", "gpp0-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart3_bus_dual: uart3-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp0-4", "gpp0-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart4_bus_single: uart4-bus-pins {</div><div class='add'>+		samsung,pins = "gpp1-0", "gpp1-1", "gpp1-2", "gpp1-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart4_bus_dual: uart4-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp1-0", "gpp1-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart5_bus_single: uart5-bus-pins {</div><div class='add'>+		samsung,pins = "gpp1-4", "gpp1-5", "gpp1-6", "gpp1-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart5_bus_dual: uart5-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp1-4", "gpp1-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart6_bus_single: uart6-bus-pins {</div><div class='add'>+		samsung,pins = "gpp2-0", "gpp2-1", "gpp2-2", "gpp2-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart6_bus_dual: uart6-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp2-0", "gpp2-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart7_bus_single: uart7-bus-pins {</div><div class='add'>+		samsung,pins = "gpp2-4", "gpp2-5", "gpp2-6", "gpp2-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart7_bus_dual: uart7-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp2-4", "gpp2-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart15_bus_single: uart15-bus-pins {</div><div class='add'>+		samsung,pins = "gpp3-0", "gpp3-1", "gpp3-2", "gpp3-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart15_bus_dual: uart15-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp3-0", "gpp3-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart16_bus_single: uart16-bus-pins {</div><div class='add'>+		samsung,pins = "gpp3-4", "gpp3-5", "gpp3-6", "gpp3-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart16_bus_dual: uart16-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp3-4", "gpp3-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart17_bus_single: uart17-bus-pins {</div><div class='add'>+		samsung,pins = "gpp4-0", "gpp4-1", "gpp4-2", "gpp4-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart17_bus_dual: uart17-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp4-0", "gpp4-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_peric1 {</div><div class='add'>+	gpb0: gpb0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpb1: gpb1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpb2: gpb2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpc0: gpc0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpg1: gpg1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp5: gpp5-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp6: gpp6-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp7: gpp7-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp8: gpp8-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp9: gpp9-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_i2s0_bus: aud-i2s0-bus-pins {</div><div class='add'>+		samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_i2s0_idle: aud-i2s0-idle-pins {</div><div class='add'>+		samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_i2s1_bus: aud-i2s1-bus-pins {</div><div class='add'>+		samsung,pins = "gpb0-4", "gpb0-5", "gpb0-6", "gpb0-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_i2s1_idle: aud-i2s1-idle-pins {</div><div class='add'>+		samsung,pins = "gpb0-4", "gpb0-5", "gpb0-6", "gpb0-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_i2s2_bus: aud-i2s2-bus-pins {</div><div class='add'>+		samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_i2s2_idle: aud-i2s2-idle-pins {</div><div class='add'>+		samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_i2s3_bus: aud-i2s3-bus-pins {</div><div class='add'>+		samsung,pins = "gpb1-4", "gpb1-5", "gpb1-6", "gpb1-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_i2s3_idle: aud-i2s3-idle-pins {</div><div class='add'>+		samsung,pins = "gpb1-4", "gpb1-5", "gpb1-6", "gpb1-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_i2s4_bus: aud-i2s4-bus-pins {</div><div class='add'>+		samsung,pins = "gpb2-0", "gpb2-1", "gpb2-2", "gpb2-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_i2s4_pci: aud-i2s4-pci-pins {</div><div class='add'>+		samsung,pins = "gpb2-0", "gpb2-1", "gpb2-2", "gpb2-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_i2s4_idle: aud-i2s4-idle-pins {</div><div class='add'>+		samsung,pins = "gpb2-0", "gpb2-1", "gpb2-2", "gpb2-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_i2s5_bus: aud-i2s5-bus-pins {</div><div class='add'>+		samsung,pins = "gpb2-4", "gpb2-5", "gpb2-6", "gpb2-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_i2s5_idle: aud-i2s5-idle-pins {</div><div class='add'>+		samsung,pins = "gpb2-4", "gpb2-5", "gpb2-6", "gpb2-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_dsd_bus: aud-dsd-bus-pins {</div><div class='add'>+		samsung,pins = "gpb2-4", "gpb2-5", "gpb2-6";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_dsd_idle: aud-dsd-idle-pins {</div><div class='add'>+		samsung,pins = "gpb2-4", "gpb2-5", "gpb2-6";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cfg_wlanen: cfg-wlanen-pins {</div><div class='add'>+		samsung,pins = "gpb0-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV4&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cnss_wlan_en_active: cnss-wlan-en-active-pins {</div><div class='add'>+		samsung,pins = "gpb0-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV4&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cnss_wlan_en_sleep: cnss-wlan-en-sleep-pins {</div><div class='add'>+		samsung,pins = "gpb0-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV2&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	decon_f_te_on: decon-f-te-on-pins {</div><div class='add'>+		samsung,pins = "gpc0-4";</div><div class='add'>+		samsung,pin-function = &lt;0xf&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	decon_f_te_off: decon-f-te-off-pins {</div><div class='add'>+		samsung,pins = "gpc0-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	decon_s_te_on: decon-s-te-on-pins {</div><div class='add'>+		samsung,pins = "gpc0-5";</div><div class='add'>+		samsung,pin-function = &lt;0xf&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	decon_s_te_off: decon-s-te-off-pins {</div><div class='add'>+		samsung,pins = "gpc0-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c12_bus: hsi2c12-bus-pins {</div><div class='add'>+		samsung,pins = "gpp5-0", "gpp5-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c13_bus: hsi2c13-bus-pins {</div><div class='add'>+		samsung,pins = "gpp5-2", "gpp5-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c14_bus: hsi2c14-bus-pins {</div><div class='add'>+		samsung,pins = "gpp5-4", "gpp5-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c15_bus: hsi2c15-bus-pins {</div><div class='add'>+		samsung,pins = "gpp5-6", "gpp5-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c16_bus: hsi2c16-bus-pins {</div><div class='add'>+		samsung,pins = "gpp6-0", "gpp6-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c17_bus: hsi2c17-bus-pins {</div><div class='add'>+		samsung,pins = "gpp6-2", "gpp6-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c18_bus: hsi2c18-bus-pins {</div><div class='add'>+		samsung,pins = "gpp6-4", "gpp6-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c19_bus: hsi2c19-bus-pins {</div><div class='add'>+		samsung,pins = "gpp6-6", "gpp6-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c20_bus: hsi2c20-bus-pins {</div><div class='add'>+		samsung,pins = "gpp7-0", "gpp7-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c21_bus: hsi2c21-bus-pins {</div><div class='add'>+		samsung,pins = "gpp7-2", "gpp7-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c22_bus: hsi2c22-bus-pins {</div><div class='add'>+		samsung,pins = "gpp7-4", "gpp7-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c23_bus: hsi2c23-bus-pins {</div><div class='add'>+		samsung,pins = "gpp7-6", "gpp7-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c24_bus: hsi2c24-bus-pins {</div><div class='add'>+		samsung,pins = "gpp8-0", "gpp8-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c25_bus: hsi2c25-bus-pins {</div><div class='add'>+		samsung,pins = "gpp8-2", "gpp8-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c32_bus: hsi2c32-bus-pins {</div><div class='add'>+		samsung,pins = "gpp8-4", "gpp8-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c33_bus: hsi2c33-bus-pins {</div><div class='add'>+		samsung,pins = "gpp8-6", "gpp8-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c34_bus: hsi2c34-bus-pins {</div><div class='add'>+		samsung,pins = "gpp9-0", "gpp9-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c35_bus: hsi2c35-bus-pins {</div><div class='add'>+		samsung,pins = "gpp9-2", "gpp9-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c36_bus: hsi2c36-bus-pins {</div><div class='add'>+		samsung,pins = "gpp9-4", "gpp9-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c37_bus: hsi2c37-bus-pins {</div><div class='add'>+		samsung,pins = "gpp9-6", "gpp9-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sensor_mclk0_out: sensor-mclk0-out-pins {</div><div class='add'>+		samsung,pins = "gpc0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sensor_mclk1_out: sensor-mclk1-out-pins {</div><div class='add'>+		samsung,pins = "gpg1-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sensor_mclk2_out: sensor-mclk2-out-pins {</div><div class='add'>+		samsung,pins = "gpc0-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sensor_mclk3_out: sensor-mclk3-out-pins {</div><div class='add'>+		samsung,pins = "gpc0-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sensor_mclk4_out: sensor-mclk4-out-pins {</div><div class='add'>+		samsung,pins = "gpc0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sensor_mclk5_out: sensor-mclk5-out-pins {</div><div class='add'>+		samsung,pins = "gpg1-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sensor_mclk0_fn: sensor-mclk0-fn-pins {</div><div class='add'>+		samsung,pins = "gpc0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sensor_mclk1_fn: sensor-mclk1-fn-pins {</div><div class='add'>+		samsung,pins = "gpg1-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sensor_mclk2_fn: sensor-mclk2-fn-pins {</div><div class='add'>+		samsung,pins = "gpc0-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sensor_mclk3_fn: sensor-mclk3-fn-pins {</div><div class='add'>+		samsung,pins = "gpc0-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sensor_mclk4_fn: sensor-mclk4-fn-pins {</div><div class='add'>+		samsung,pins = "gpc0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sensor_mclk5_fn: sensor-mclk5-fn-pins {</div><div class='add'>+		samsung,pins = "gpg1-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi6_bus: spi6-bus-pins {</div><div class='add'>+		samsung,pins = "gpp5-2", "gpp5-1", "gpp5-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi6_cs: spi6-cs-pins {</div><div class='add'>+		samsung,pins = "gpp5-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi6_cs_func: spi6-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp5-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi7_bus: spi7-bus-pins {</div><div class='add'>+		samsung,pins = "gpp5-6", "gpp5-5", "gpp5-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi7_cs: spi7-cs-pins {</div><div class='add'>+		samsung,pins = "gpp5-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi7_cs_func: spi7-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp5-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi8_bus: spi8-bus-pins {</div><div class='add'>+		samsung,pins = "gpp6-2", "gpp6-1", "gpp6-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi8_cs: spi8-cs-pins {</div><div class='add'>+		samsung,pins = "gpp6-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi8_cs_func: spi8-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp6-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi9_bus: spi9-bus-pins {</div><div class='add'>+		samsung,pins = "gpp6-6", "gpp6-5", "gpp6-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi9_cs: spi9-cs-pins {</div><div class='add'>+		samsung,pins = "gpp6-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi9_cs_func: spi9-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp6-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi10_bus: spi10-bus-pins {</div><div class='add'>+		samsung,pins = "gpp7-2", "gpp7-1", "gpp7-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi10_cs: spi10-cs-pins {</div><div class='add'>+		samsung,pins = "gpp7-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi10_cs_func: spi10-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp7-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi11_bus: spi11-bus-pins {</div><div class='add'>+		samsung,pins = "gpp7-6", "gpp7-5", "gpp7-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi11_cs: spi11-cs-pins {</div><div class='add'>+		samsung,pins = "gpp7-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi11_cs_func: spi11-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp7-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi12_bus: spi12-bus-pins {</div><div class='add'>+		samsung,pins = "gpp8-2", "gpp8-1", "gpp8-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi12_cs: spi12-cs-pins {</div><div class='add'>+		samsung,pins = "gpp8-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi12_cs_func: spi12-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp8-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi16_bus: spi16-bus-pins {</div><div class='add'>+		samsung,pins = "gpp8-6", "gpp8-5", "gpp8-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi16_cs: spi16-cs-pins {</div><div class='add'>+		samsung,pins = "gpp8-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi16_cs_func: spi16-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp8-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi17_bus: spi17-bus-pins {</div><div class='add'>+		samsung,pins = "gpp9-2", "gpp9-1", "gpp9-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi17_cs: spi17-cs-pins {</div><div class='add'>+		samsung,pins = "gpp9-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi17_cs_func: spi17-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp9-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi18_bus: spi18-bus-pins {</div><div class='add'>+		samsung,pins = "gpp9-6", "gpp9-5", "gpp9-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi18_cs: spi18-cs-pins {</div><div class='add'>+		samsung,pins = "gpp9-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi18_cs_func: spi18-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp9-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart8_bus_single: uart8-bus-pins {</div><div class='add'>+		samsung,pins = "gpp5-3", "gpp5-2", "gpp5-1", "gpp5-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart8_bus_dual: uart8-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp5-0", "gpp5-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart9_bus_single: uart9-bus-pins {</div><div class='add'>+		samsung,pins = "gpp5-7", "gpp5-6", "gpp5-5", "gpp5-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart9_bus_dual: uart9-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp5-4", "gpp5-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart10_bus_single: uart10-bus-pins {</div><div class='add'>+		samsung,pins = "gpp6-3", "gpp6-2", "gpp6-1", "gpp6-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart10_bus_dual: uart10-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp6-0", "gpp6-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart11_bus_single: uart11-bus-pins {</div><div class='add'>+		samsung,pins = "gpp6-7", "gpp6-6", "gpp6-5", "gpp6-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart11_bus_dual: uart11-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp6-4", "gpp6-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart12_bus_single: uart12-bus-pins {</div><div class='add'>+		samsung,pins = "gpp7-3", "gpp7-2", "gpp7-1", "gpp7-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart12_bus_dual: uart12-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp7-0", "gpp7-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart13_bus_single: uart13-bus-pins {</div><div class='add'>+		samsung,pins = "gpp7-7", "gpp7-6", "gpp7-5", "gpp7-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart13_bus_dual: uart13-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp7-4", "gpp7-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart14_bus_single: uart14-bus-pins {</div><div class='add'>+		samsung,pins = "gpp8-3", "gpp8-2", "gpp8-1", "gpp8-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart14_bus_dual: uart14-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp8-0", "gpp8-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart18_bus_single: uart18-bus-pins {</div><div class='add'>+		samsung,pins = "gpp8-7", "gpp8-6", "gpp8-5", "gpp8-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart18_bus_dual: uart18-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp8-4", "gpp8-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart19_bus_single: uart19-bus-pins {</div><div class='add'>+		samsung,pins = "gpp9-3", "gpp9-2", "gpp9-1", "gpp9-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart19_bus_dual: uart19-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp9-0", "gpp9-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart20_bus_single: uart20-bus-pins {</div><div class='add'>+		samsung,pins = "gpp9-7", "gpp9-6", "gpp9-5", "gpp9-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart20_bus_dual: uart20-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp9-4", "gpp9-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_vts {</div><div class='add'>+	gpv0: gpv0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	amic_pdm: amic-pdm-pins {</div><div class='add'>+		samsung,pins = "gpv0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_INPUT&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dmic_bus_clk: dmic-bus-clk-pins {</div><div class='add'>+		samsung,pins = "gpv0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_INPUT&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dmic_bus_clk_idle: dmic-bus-clk-idle-pins {</div><div class='add'>+		samsung,pins = "gpv0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_INPUT&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dmic_bus_clk1: dmic-bus-clk1-pins {</div><div class='add'>+		samsung,pins = "gpv0-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_INPUT&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dmic_bus_clk1_idle: dmic-bus-clk1-idle-pins {</div><div class='add'>+		samsung,pins = "gpv0-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_INPUT&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dmic_bus_clk2: dmic-bus-clk2-pins {</div><div class='add'>+		samsung,pins = "gpv0-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_INPUT&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dmic_bus_clk2_idle: dmic-bus-clk2-idle-pins {</div><div class='add'>+		samsung,pins = "gpv0-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_INPUT&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dmic_pdm: dmic-pdm-pins {</div><div class='add'>+		samsung,pins = "gpv0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_INPUT&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dmic_pdm_idle: dmic-pdm-idle-pins {</div><div class='add'>+		samsung,pins = "gpv0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_INPUT&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dmic_pdm1_bus: dmic-pdm1-bus-pins {</div><div class='add'>+		samsung,pins = "gpv0-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_INPUT&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dmic_pdm1_idle: dmic-pdm1-idle-pins {</div><div class='add'>+		samsung,pins = "gpv0-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_INPUT&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dmic_pdm2_bus: dmic-pdm2-bus-pins {</div><div class='add'>+		samsung,pins = "gpv0-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_INPUT&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dmic_pdm2_idle: dmic-pdm2-idle-pins {</div><div class='add'>+		samsung,pins = "gpv0-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_INPUT&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/exynos990-r8s.dts b/arch/arm64/boot/dts/exynos/exynos990-r8s.dts<br/>new file mode 100644<br/>index 000000000000..55342db61979<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynos990-r8s.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/exynos990-r8s.dts</a></div><div class='hunk'>@@ -0,0 +1,131 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause</div><div class='add'>+/*</div><div class='add'>+ * Samsung Galaxy S20 FE (r8s/SM-G780F) device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2024, Denzeel Oliva &lt;wachiturroxd150@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "exynos990.dtsi"</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Samsung Galaxy S20 FE";</div><div class='add'>+	compatible = "samsung,r8s", "samsung,exynos990";</div><div class='add'>+</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		framebuffer0: framebuffer@f1000000 {</div><div class='add'>+			compatible = "simple-framebuffer";</div><div class='add'>+			reg = &lt;0 0xf1000000 0 (1080 * 2400 * 4)&gt;;</div><div class='add'>+			width = &lt;1080&gt;;</div><div class='add'>+			height = &lt;2400&gt;;</div><div class='add'>+			stride = &lt;(1080 * 4)&gt;;</div><div class='add'>+			format = "a8r8g8b8";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@80000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x80000000 0x0 0x3ab00000&gt;,</div><div class='add'>+		      /* Memory hole */</div><div class='add'>+		      &lt;0x0 0xc1200000 0x0 0x1ee00000&gt;,</div><div class='add'>+		      /* Memory hole */</div><div class='add'>+		      &lt;0x0 0xe1900000 0x0 0x1e700000&gt;,</div><div class='add'>+		      /* Memory hole - last block */</div><div class='add'>+		      &lt;0x8 0x80000000 0x0 0xc0000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* TODO: Remove this once PMIC is implemented */</div><div class='add'>+	reg_dummy: regulator-0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "dummy_reg";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		cont_splash_mem: framebuffer@f1000000 {</div><div class='add'>+			reg = &lt;0 0xf1000000 0 0x13c6800&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		abox_reserved: audio@f7fb0000 {</div><div class='add'>+			reg = &lt;0 0xf7fb0000 0 0x2a50000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;key_power &amp;key_voldown &amp;key_volup&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		power-key {</div><div class='add'>+			label = "Power";</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpa2 4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		voldown-key {</div><div class='add'>+			label = "Volume Down";</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpa0 4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		volup-key {</div><div class='add'>+			label = "Volume Up";</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpa0 3 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;oscclk {</div><div class='add'>+	clock-frequency = &lt;26000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_alive {</div><div class='add'>+	key_power: key-power-pins {</div><div class='add'>+		samsung,pins = "gpa2-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	key_voldown: key-voldown-pins {</div><div class='add'>+		samsung,pins = "gpa0-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	key_volup: key-volup-pins {</div><div class='add'>+		samsung,pins = "gpa0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbdrd {</div><div class='add'>+	status = "okay";</div><div class='add'>+	vdd10-supply = &lt;&amp;reg_dummy&gt;;</div><div class='add'>+	vdd33-supply = &lt;&amp;reg_dummy&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbdrd_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/exynos990-x1s-common.dtsi b/arch/arm64/boot/dts/exynos/exynos990-x1s-common.dtsi<br/>new file mode 100644<br/>index 000000000000..7b97220cccb7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynos990-x1s-common.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/exynos990-x1s-common.dtsi</a></div><div class='hunk'>@@ -0,0 +1,114 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause</div><div class='add'>+/*</div><div class='add'>+ * Samsung Galaxy S20 Series device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2024, Umer Uddin &lt;umer.uddin@mentallysanemainliners.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "exynos990.dtsi"</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	chosen {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		framebuffer0: framebuffer@f1000000 {</div><div class='add'>+			compatible = "simple-framebuffer";</div><div class='add'>+			reg = &lt;0 0xf1000000 0 (1440 * 3200 * 4)&gt;;</div><div class='add'>+			width = &lt;1440&gt;;</div><div class='add'>+			height = &lt;3200&gt;;</div><div class='add'>+			stride = &lt;(1440 * 4)&gt;;</div><div class='add'>+			format = "a8r8g8b8";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* TODO: Remove this once PMIC is implemented */</div><div class='add'>+	reg_dummy: regulator-0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "dummy_reg";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		cont_splash_mem: framebuffer@f1000000 {</div><div class='add'>+			reg = &lt;0 0xf1000000 0 0x1194000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		abox_reserved: audio@f7fb0000 {</div><div class='add'>+			reg = &lt;0 0xf7fb0000 0 0x2a50000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;key_power &amp;key_voldown &amp;key_volup&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		power-key {</div><div class='add'>+			label = "Power";</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpa2 4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		voldown-key {</div><div class='add'>+			label = "Volume Down";</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpa0 4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		volup-key {</div><div class='add'>+			label = "Volume Up";</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpa0 3 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;oscclk {</div><div class='add'>+	clock-frequency = &lt;26000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_alive {</div><div class='add'>+	key_power: key-power-pins {</div><div class='add'>+		samsung,pins = "gpa2-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	key_voldown: key-voldown-pins {</div><div class='add'>+		samsung,pins = "gpa0-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	key_volup: key-volup-pins {</div><div class='add'>+		samsung,pins = "gpa0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbdrd {</div><div class='add'>+	status = "okay";</div><div class='add'>+	vdd10-supply = &lt;&amp;reg_dummy&gt;;</div><div class='add'>+	vdd33-supply = &lt;&amp;reg_dummy&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbdrd_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/exynos990-x1s.dts b/arch/arm64/boot/dts/exynos/exynos990-x1s.dts<br/>new file mode 100644<br/>index 000000000000..1ae881015e0c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynos990-x1s.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/exynos990-x1s.dts</a></div><div class='hunk'>@@ -0,0 +1,28 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause</div><div class='add'>+/*</div><div class='add'>+ * Samsung Galaxy S20 5G (x1s/SM-G981B) device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2024, Umer Uddin &lt;umer.uddin@mentallysanemainliners.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "exynos990-x1s-common.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	model = "Samsung Galaxy S20 5G";</div><div class='add'>+	compatible = "samsung,x1s", "samsung,exynos990";</div><div class='add'>+</div><div class='add'>+	memory@80000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x80000000 0x0 0x3ab00000&gt;,</div><div class='add'>+		      /* Memory hole */</div><div class='add'>+		      &lt;0x0 0xc1200000 0x0 0x1ee00000&gt;,</div><div class='add'>+		      /* Memory hole */</div><div class='add'>+		      &lt;0x0 0xe1900000 0x0 0x1e700000&gt;,</div><div class='add'>+		      /* Memory hole */</div><div class='add'>+		      &lt;0x8 0x80000000 0x2 0x7e800000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/exynos990-x1slte.dts b/arch/arm64/boot/dts/exynos/exynos990-x1slte.dts<br/>new file mode 100644<br/>index 000000000000..d3720996ba93<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynos990-x1slte.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/exynos990-x1slte.dts</a></div><div class='hunk'>@@ -0,0 +1,28 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause</div><div class='add'>+/*</div><div class='add'>+ * Samsung Galaxy S20 (x1slte/SM-G980F) device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2024, Umer Uddin &lt;umer.uddin@mentallysanemainliners.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "exynos990-x1s-common.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	model = "Samsung Galaxy S20";</div><div class='add'>+	compatible = "samsung,x1slte", "samsung,exynos990";</div><div class='add'>+</div><div class='add'>+	memory@80000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x80000000 0x0 0x3ab00000&gt;,</div><div class='add'>+		      /* Memory hole */</div><div class='add'>+		      &lt;0x0 0xc1200000 0x0 0x1ee00000&gt;,</div><div class='add'>+		      /* Memory hole */</div><div class='add'>+		      &lt;0x0 0xe1900000 0x0 0x1e700000&gt;,</div><div class='add'>+		      /* Memory hole */</div><div class='add'>+		      &lt;0x8 0x80000000 0x1 0x7ec00000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/exynos990.dtsi b/arch/arm64/boot/dts/exynos/exynos990.dtsi<br/>new file mode 100644<br/>index 000000000000..f8e2a31b4b75<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynos990.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/exynos990.dtsi</a></div><div class='hunk'>@@ -0,0 +1,418 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause</div><div class='add'>+/*</div><div class='add'>+ * Samsung Exynos 990 SoC device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2024, Igor Belwon &lt;igor.belwon@mentallysanemainliners.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/samsung,exynos990.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "samsung,exynos990";</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		pinctrl0 = &amp;pinctrl_alive;</div><div class='add'>+		pinctrl1 = &amp;pinctrl_cmgp;</div><div class='add'>+		pinctrl2 = &amp;pinctrl_hsi1;</div><div class='add'>+		pinctrl3 = &amp;pinctrl_hsi2;</div><div class='add'>+		pinctrl4 = &amp;pinctrl_peric0;</div><div class='add'>+		pinctrl5 = &amp;pinctrl_peric1;</div><div class='add'>+		pinctrl6 = &amp;pinctrl_vts;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu-map {</div><div class='add'>+			cluster0 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu2&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu3&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cluster1 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu4&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu5&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cluster2 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu6&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu7&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@1 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x1&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@2 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x2&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@3 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x3&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu4: cpu@100 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a76";</div><div class='add'>+			reg = &lt;0x4&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu5: cpu@101 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a76";</div><div class='add'>+			reg = &lt;0x5&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu6: cpu@200 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "samsung,mongoose-m5";</div><div class='add'>+			reg = &lt;0x6&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu7: cpu@201 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "samsung,mongoose-m5";</div><div class='add'>+			reg = &lt;0x7&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	oscclk: clock-osc {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-output-names = "oscclk";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu-a55 {</div><div class='add'>+		compatible = "arm,cortex-a55-pmu";</div><div class='add'>+		interrupts = &lt;GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-affinity = &lt;&amp;cpu0&gt;,</div><div class='add'>+				     &lt;&amp;cpu1&gt;,</div><div class='add'>+				     &lt;&amp;cpu2&gt;,</div><div class='add'>+				     &lt;&amp;cpu3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu-a76 {</div><div class='add'>+		compatible = "arm,cortex-a76-pmu";</div><div class='add'>+		interrupts = &lt;GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-affinity = &lt;&amp;cpu4&gt;,</div><div class='add'>+				     &lt;&amp;cpu5&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu-mongoose-m5 {</div><div class='add'>+		compatible = "samsung,mongoose-pmu";</div><div class='add'>+		interrupts = &lt;GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-affinity = &lt;&amp;cpu6&gt;,</div><div class='add'>+				     &lt;&amp;cpu7&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-0.2";</div><div class='add'>+		method = "hvc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc: soc@0 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		ranges = &lt;0x0 0x0 0x0 0x20000000&gt;;</div><div class='add'>+</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		chipid@10000000 {</div><div class='add'>+			compatible = "samsung,exynos990-chipid",</div><div class='add'>+				     "samsung,exynos850-chipid";</div><div class='add'>+			reg = &lt;0x10000000 0x100&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_peris: clock-controller@10020000 {</div><div class='add'>+			compatible = "samsung,exynos990-cmu-peris";</div><div class='add'>+			reg = &lt;0x10020000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;oscclk&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_PERIS_BUS&gt;;</div><div class='add'>+			clock-names = "oscclk", "bus";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		timer@10040000 {</div><div class='add'>+			compatible = "samsung,exynos990-mct",</div><div class='add'>+				     "samsung,exynos4210-mct";</div><div class='add'>+			reg = &lt;0x10040000 0x800&gt;;</div><div class='add'>+			clocks = &lt;&amp;oscclk&gt;, &lt;&amp;cmu_peris CLK_GOUT_PERIS_MCT_PCLK&gt;;</div><div class='add'>+			clock-names = "fin_pll", "mct";</div><div class='add'>+			interrupts = &lt;GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		watchdog_cl0: watchdog@10050000 {</div><div class='add'>+			compatible = "samsung,exynos990-wdt";</div><div class='add'>+			reg = &lt;0x10050000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peris CLK_GOUT_PERIS_WDT_CLUSTER0_PCLK&gt;,</div><div class='add'>+				 &lt;&amp;oscclk&gt;;</div><div class='add'>+			clock-names = "watchdog",</div><div class='add'>+				      "watchdog_src";</div><div class='add'>+			samsung,syscon-phandle = &lt;&amp;pmu_system_controller&gt;;</div><div class='add'>+			samsung,cluster-index = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		watchdog_cl2: watchdog@10060000 {</div><div class='add'>+			compatible = "samsung,exynos990-wdt";</div><div class='add'>+			reg = &lt;0x10060000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peris CLK_GOUT_PERIS_WDT_CLUSTER2_PCLK&gt;,</div><div class='add'>+				 &lt;&amp;oscclk&gt;;</div><div class='add'>+			clock-names = "watchdog",</div><div class='add'>+				      "watchdog_src";</div><div class='add'>+			samsung,syscon-phandle = &lt;&amp;pmu_system_controller&gt;;</div><div class='add'>+			samsung,cluster-index = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@10101000 {</div><div class='add'>+			compatible = "arm,gic-400";</div><div class='add'>+			reg = &lt;0x10101000 0x1000&gt;,</div><div class='add'>+			      &lt;0x10102000 0x1000&gt;,</div><div class='add'>+			      &lt;0x10104000 0x2000&gt;,</div><div class='add'>+			      &lt;0x10106000 0x2000&gt;;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |</div><div class='add'>+						 IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='add'>+			#address-cells = &lt;0&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_peric0: clock-controller@10400000 {</div><div class='add'>+			compatible = "samsung,exynos990-cmu-peric0";</div><div class='add'>+			reg = &lt;0x10400000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;oscclk&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_PERIC0_BUS&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_PERIC0_IP&gt;;</div><div class='add'>+			clock-names = "oscclk", "bus", "ip";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sysreg_peric0: syscon@10420000 {</div><div class='add'>+			compatible = "samsung,exynos990-peric0-sysreg", "syscon";</div><div class='add'>+			reg = &lt;0x10420000 0x10000&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_SYSREG_PCLK&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_peric0: pinctrl@10430000 {</div><div class='add'>+			compatible = "samsung,exynos990-pinctrl";</div><div class='add'>+			reg = &lt;0x10430000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_peric1: clock-controller@10700000 {</div><div class='add'>+			compatible = "samsung,exynos990-cmu-peric1";</div><div class='add'>+			reg = &lt;0x10700000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;oscclk&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_PERIC1_BUS&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_PERIC1_IP&gt;;</div><div class='add'>+			clock-names = "oscclk", "bus", "ip";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sysreg_peric1: syscon@10720000 {</div><div class='add'>+			compatible = "samsung,exynos990-peric1-sysreg", "syscon";</div><div class='add'>+			reg = &lt;0x10720000 0x10000&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_SYSREG_PCLK&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_peric1: pinctrl@10730000 {</div><div class='add'>+			compatible = "samsung,exynos990-pinctrl";</div><div class='add'>+			reg = &lt;0x10730000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_hsi0: clock-controller@10a00000 {</div><div class='add'>+			compatible = "samsung,exynos990-cmu-hsi0";</div><div class='add'>+			reg = &lt;0x10a00000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;oscclk&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_HSI0_BUS&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_HSI0_USB31DRD&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_HSI0_USBDP_DEBUG&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_HSI0_DPGTC&gt;;</div><div class='add'>+			clock-names = "oscclk",</div><div class='add'>+				      "bus",</div><div class='add'>+				      "usb31drd",</div><div class='add'>+				      "usbdp_debug",</div><div class='add'>+				      "dpgtc";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usbdrd_phy: phy@10c00000 {</div><div class='add'>+			compatible = "samsung,exynos990-usbdrd-phy";</div><div class='add'>+			reg = &lt;0x10c00000 0x100&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_ACLK_PHYCTRL&gt;,</div><div class='add'>+				 &lt;&amp;oscclk&gt;;</div><div class='add'>+			clock-names = "phy", "ref";</div><div class='add'>+			samsung,pmu-syscon = &lt;&amp;pmu_system_controller&gt;;</div><div class='add'>+			#phy-cells = &lt;1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usbdrd: usb@10e00000 {</div><div class='add'>+			compatible = "samsung,exynos990-dwusb3",</div><div class='add'>+				     "samsung,exynos850-dwusb3";</div><div class='add'>+			ranges = &lt;0x0 0x10e00000 0x10000&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY&gt;,</div><div class='add'>+				 &lt;&amp;cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_USB31DRD_REF_CLK_40&gt;;</div><div class='add'>+			clock-names = "bus_early", "ref";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			usbdrd_dwc3: usb@0 {</div><div class='add'>+				compatible = "snps,dwc3";</div><div class='add'>+				reg = &lt;0x0 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				phys = &lt;&amp;usbdrd_phy 0&gt;;</div><div class='add'>+				phy-names = "usb2-phy";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_hsi1: pinctrl@13040000 {</div><div class='add'>+			compatible = "samsung,exynos990-pinctrl";</div><div class='add'>+			reg = &lt;0x13040000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_hsi2: pinctrl@13c30000 {</div><div class='add'>+			compatible = "samsung,exynos990-pinctrl";</div><div class='add'>+			reg = &lt;0x13c30000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_vts: pinctrl@15580000 {</div><div class='add'>+			compatible = "samsung,exynos990-pinctrl";</div><div class='add'>+			reg = &lt;0x15580000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_alive: pinctrl@15850000 {</div><div class='add'>+			compatible = "samsung,exynos990-pinctrl";</div><div class='add'>+			reg = &lt;0x15850000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			wakeup-interrupt-controller {</div><div class='add'>+				compatible = "samsung,exynos990-wakeup-eint",</div><div class='add'>+					     "samsung,exynos850-wakeup-eint",</div><div class='add'>+					     "samsung,exynos7-wakeup-eint";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmu_system_controller: system-controller@15860000 {</div><div class='add'>+			compatible = "samsung,exynos990-pmu",</div><div class='add'>+				     "samsung,exynos7-pmu", "syscon";</div><div class='add'>+			reg = &lt;0x15860000 0x10000&gt;;</div><div class='add'>+</div><div class='add'>+			reboot: syscon-reboot {</div><div class='add'>+				compatible = "syscon-reboot";</div><div class='add'>+				regmap = &lt;&amp;pmu_system_controller&gt;;</div><div class='add'>+				offset = &lt;0x3a00&gt;; /* SWRESET */</div><div class='add'>+				mask = &lt;0x2&gt;; /* SWRESET_TRIGGER */</div><div class='add'>+				value = &lt;0x2&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_cmgp: pinctrl@15c30000 {</div><div class='add'>+			compatible = "samsung,exynos990-pinctrl";</div><div class='add'>+			reg = &lt;0x15c30000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_top: clock-controller@1a330000 {</div><div class='add'>+			compatible = "samsung,exynos990-cmu-top";</div><div class='add'>+			reg = &lt;0x1a330000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;oscclk&gt;;</div><div class='add'>+			clock-names = "oscclk";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Non-updatable, broken stock Samsung bootloader does not</div><div class='add'>+		 * configure CNTFRQ_EL0</div><div class='add'>+		 */</div><div class='add'>+		clock-frequency = &lt;26000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include "exynos990-pinctrl.dtsi"</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/exynosautov9-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynosautov9-pinctrl.dtsi<br/>new file mode 100644<br/>index 000000000000..e413a51c2d08<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynosautov9-pinctrl.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/exynosautov9-pinctrl.dtsi</a></div><div class='hunk'>@@ -0,0 +1,1189 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Samsung's ExynosAutov9 SoC pin-mux and pin-config device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2021 Samsung Electronics Co., Ltd.</div><div class='add'>+ *</div><div class='add'>+ * Samsung's ExynosAutov9 SoC pin-mux and pin-config options are listed as</div><div class='add'>+ * device tree nodes in this file.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "exynos-pinctrl.h"</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_alive {</div><div class='add'>+	gpa0: gpa0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpa1: gpa1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dp0_hpd: dp0-hpd-pins {</div><div class='add'>+		samsung,pins = "gpa1-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dp1_hpd: dp1-hpd-pins {</div><div class='add'>+		samsung,pins = "gpa1-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpq0: gpq0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	speedy0_bus: speedy0-bus-pins {</div><div class='add'>+		samsung,pins = "gpq0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	speedy1_bus: speedy1-bus-pins {</div><div class='add'>+		samsung,pins = "gpa0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_aud {</div><div class='add'>+	gpb0: gpb0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpb1: gpb1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpb2: gpb2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpb3: gpb3-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_codec_mclk: aud-codec-mclk-pins {</div><div class='add'>+		samsung,pins = "gpb0-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_codec_mclk_idle: aud-codec-mclk-idle-pins {</div><div class='add'>+		samsung,pins = "gpb0-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_i2s0_bus: aud-i2s0-pins {</div><div class='add'>+		samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_i2s0_idle: aud-i2s0-idle-pins {</div><div class='add'>+		samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_i2s1_bus: aud-i2s1-pins {</div><div class='add'>+		samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_i2s1_idle: aud-i2s1-idle-pins {</div><div class='add'>+		samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_i2s2_bus: aud-i2s2-pins {</div><div class='add'>+		samsung,pins = "gpb1-4", "gpb1-5", "gpb1-6", "gpb1-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_i2s2_idle: aud-i2s2-idle-pins {</div><div class='add'>+		samsung,pins = "gpb1-4", "gpb1-5", "gpb1-6", "gpb1-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_i2s3_bus: aud-i2s3-pins {</div><div class='add'>+		samsung,pins = "gpb2-0", "gpb2-1", "gpb2-2", "gpb2-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_i2s3_idle: aud-i2s3-idle-pins {</div><div class='add'>+		samsung,pins = "gpb2-0", "gpb2-1", "gpb2-2", "gpb2-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_i2s4_bus: aud-i2s4-pins {</div><div class='add'>+		samsung,pins = "gpb2-4", "gpb2-5", "gpb2-6", "gpb2-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_i2s4_idle: aud-i2s4-idle-pins {</div><div class='add'>+		samsung,pins = "gpb2-4", "gpb2-5", "gpb2-6", "gpb2-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_i2s5_bus: aud-i2s5-pins {</div><div class='add'>+		samsung,pins = "gpb3-0", "gpb3-1", "gpb3-2", "gpb3-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_i2s5_idle: aaud-i2s5-idle-pins {</div><div class='add'>+		samsung,pins = "gpb3-0", "gpb3-1", "gpb3-2", "gpb3-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_i2s6_bus: aud-i2s6-pins {</div><div class='add'>+		samsung,pins = "gpb3-4", "gpb3-5", "gpb3-6", "gpb3-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_i2s6_idle: aaud-i2s6-idle-pins {</div><div class='add'>+		samsung,pins = "gpb3-4", "gpb3-5", "gpb3-6", "gpb3-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_INPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_fsys0 {</div><div class='add'>+	gpf0: gpf0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpf1: gpf1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie_clkreq0: pcie-clkreq0-pins {</div><div class='add'>+		samsung,pins = "gpf0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV4&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie_perst0_out: pcie-perst0-out-pins {</div><div class='add'>+		samsung,pins = "gpf0-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV4&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie_perst0_in: pcie-perst0-in-pins {</div><div class='add'>+		samsung,pins = "gpf0-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV4&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie_clkreq1: pcie-clkreq1-pins {</div><div class='add'>+		samsung,pins = "gpf0-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV4&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie_perst1_out: pcie-perst1-out-pins {</div><div class='add'>+		samsung,pins = "gpf0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV4&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie_perst1_in: pcie-perst1-in-pins {</div><div class='add'>+		samsung,pins = "gpf0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV4&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie_clkreq2: pcie-clkreq2-pins {</div><div class='add'>+		samsung,pins = "gpf0-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV4&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie_perst2_out: pcie-perst2-out-pins {</div><div class='add'>+		samsung,pins = "gpf0-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV4&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie_perst2_in: pcie-perst2-in-pins {</div><div class='add'>+		samsung,pins = "gpf0-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV4&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie_clkreq3: pcie-clkreq3-pins {</div><div class='add'>+		samsung,pins = "gpf1-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV4&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie_perst3_out: pcie-perst3-out-pins {</div><div class='add'>+		samsung,pins = "gpf1-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV4&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie_perst3_in: pcie-perst3-in-pins {</div><div class='add'>+		samsung,pins = "gpf1-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV4&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie_clkreq4: pcie-clkreq4-pins {</div><div class='add'>+		samsung,pins = "gpf1-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV4&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie_perst4_out: pcie-perst4-out-pins {</div><div class='add'>+		samsung,pins = "gpf1-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV4&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie_perst4_in: pcie-perst4-in-pins {</div><div class='add'>+		samsung,pins = "gpf1-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV4&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie_clkreq5: pcie-clkreq5-pins {</div><div class='add'>+		samsung,pins = "gpf1-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV4&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie_perst5_out: pcie-perst5-out-pins {</div><div class='add'>+		samsung,pins = "gpf1-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV4&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie_perst5_in: pcie-perst5-in-pins {</div><div class='add'>+		samsung,pins = "gpf1-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV4&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_fsys1 {</div><div class='add'>+	gpf8: gpf8-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_clk: sd2-clk-pins {</div><div class='add'>+		samsung,pins = "gpf8-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;2&gt;;	/* 2x drive strength */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_cmd: sd2-cmd-pins {</div><div class='add'>+		samsung,pins = "gpf8-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;2&gt;;	/* 2x drive strength */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_bus1: sd2-bus-width1-pins {</div><div class='add'>+		samsung,pins = "gpf8-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;2&gt;;	/* 2x drive strength */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_bus4: sd2-bus-width4-pins {</div><div class='add'>+		samsung,pins = "gpf8-3", "gpf8-4", "gpf8-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;2&gt;;	/* 2x drive strength */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_fsys2 {</div><div class='add'>+	gpf2: gpf2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpf3: gpf3-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpf4: gpf4-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpf5: gpf5-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpf6: gpf6-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ufs_rst_n: ufs-rst-n-pins {</div><div class='add'>+		samsung,pins = "gpf2-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ufs_refclk_out: ufs-refclk-out-pins {</div><div class='add'>+		samsung,pins = "gpf2-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ufs_rst_n_1: ufs-rst-n-1-pins {</div><div class='add'>+		samsung,pins = "gpf2-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ufs_refclk_out_1: ufs-refclk-out-1-pins {</div><div class='add'>+		samsung,pins = "gpf2-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PDN_PREV&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eth0_mdc_mdio: eth0-mdc-mdio-pins {</div><div class='add'>+		samsung,pins = "gpf4-5", "gpf4-6";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eth0_rgmii: eth0-rgmii-pins {</div><div class='add'>+		samsung,pins = "gpf3-1", "gpf3-2", "gpf3-3", "gpf3-4",</div><div class='add'>+			       "gpf3-5", "gpf3-6", "gpf3-7", "gpf4-0",</div><div class='add'>+			       "gpf4-1", "gpf4-2", "gpf4-3", "gpf4-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eth0_pps_out: eth0-pps-out-pins {</div><div class='add'>+		samsung,pins = "gpf3-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eth1_mdc_mdio: eth1-mdc-mdio-pins {</div><div class='add'>+		samsung,pins = "gpf6-5", "gpf6-6";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eth1_rgmii: eth1-rgmii-pins {</div><div class='add'>+		samsung,pins = "gpf5-1", "gpf5-2", "gpf5-3", "gpf5-4",</div><div class='add'>+			       "gpf5-5", "gpf5-6", "gpf5-7", "gpf6-0",</div><div class='add'>+			       "gpf6-1", "gpf6-2", "gpf6-3", "gpf6-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eth1_pps_out: eth1-pps-out-pins {</div><div class='add'>+		samsung,pins = "gpf5-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_peric0 {</div><div class='add'>+	gpp0: gpp0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp1: gpp1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp2: gpp2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpg0: gpg0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pwm_tout0: pwm-tout0-pins {</div><div class='add'>+		samsung,pins = "gpg0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_4&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pwm_tout1: pwm-tout1-pins {</div><div class='add'>+		samsung,pins = "gpg0-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_4&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pwm_tout2: pwm-tout2-pins {</div><div class='add'>+		samsung,pins = "gpg0-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_4&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pwm_tout3: pwm-tout3-pins {</div><div class='add'>+		samsung,pins = "gpg0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_4&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PERIC0 USI00  */</div><div class='add'>+	hsi2c0_bus: hsi2c0-bus-pins {</div><div class='add'>+		samsung,pins = "gpp0-0", "gpp0-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PERIC0 USI00_I2C */</div><div class='add'>+	hsi2c1_bus: hsi2c1-bus-pins {</div><div class='add'>+		samsung,pins = "gpp0-2", "gpp0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PERIC0 USI01 */</div><div class='add'>+	hsi2c2_bus: hsi2c2-bus-pins {</div><div class='add'>+		samsung,pins = "gpp0-4", "gpp0-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PERIC0 USI01_I2C */</div><div class='add'>+	hsi2c3_bus: hsi2c3-bus-pins {</div><div class='add'>+		samsung,pins = "gpp0-6", "gpp0-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PERIC0 USI02 */</div><div class='add'>+	hsi2c4_bus: hsi2c4-bus-pins {</div><div class='add'>+		samsung,pins = "gpp1-0", "gpp1-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PERIC0 USI02_I2C */</div><div class='add'>+	hsi2c5_bus: hsi2c5-bus-pins {</div><div class='add'>+		samsung,pins = "gpp1-2", "gpp1-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PERIC0 USI03 */</div><div class='add'>+	hsi2c6_bus: hsi2c6-bus-pins {</div><div class='add'>+		samsung,pins = "gpp1-4", "gpp1-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PERIC0 USI03_I2C */</div><div class='add'>+	hsi2c7_bus: hsi2c7-bus-pins {</div><div class='add'>+		samsung,pins = "gpp1-6", "gpp1-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PERIC0 USI04 */</div><div class='add'>+	hsi2c8_bus: hsi2c8-bus-pins {</div><div class='add'>+		samsung,pins = "gpp2-0", "gpp2-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PERIC0 USI04_I2C */</div><div class='add'>+	hsi2c9_bus: hsi2c9-bus-pins {</div><div class='add'>+		samsung,pins = "gpp2-2", "gpp2-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PERIC0 USI05 */</div><div class='add'>+	hsi2c10_bus: hsi2c10-bus-pins {</div><div class='add'>+		samsung,pins = "gpp2-4", "gpp2-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PERIC0 USI05_I2C */</div><div class='add'>+	hsi2c11_bus: hsi2c11-bus-pins {</div><div class='add'>+		samsung,pins = "gpp2-6", "gpp2-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SPI USI_PERIC0_USI00_SPI */</div><div class='add'>+	spi0_bus: spi0-bus-pins {</div><div class='add'>+		samsung,pins = "gpp0-2", "gpp0-1", "gpp0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi0_cs: spi0-cs-pins {</div><div class='add'>+		samsung,pins = "gpp0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi0_cs_func: spi0-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PERIC0 USI01_SPI */</div><div class='add'>+	spi1_bus: spi1-bus-pins {</div><div class='add'>+		samsung,pins = "gpp0-6", "gpp0-5", "gpp0-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi1_cs: spi1-cs-pins {</div><div class='add'>+		samsung,pins = "gpp0-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi1_cs_func: spi1-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp0-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PERIC0 USI02_SPI */</div><div class='add'>+	spi2_bus: spi2-bus-pins {</div><div class='add'>+		samsung,pins = "gpp1-2", "gpp1-1", "gpp1-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi2_cs: spi2-cs-pins {</div><div class='add'>+		samsung,pins = "gpp1-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi2_cs_func: spi2-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp1-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PERIC0 USI03_SPI */</div><div class='add'>+	spi3_bus: spi3-bus-pins {</div><div class='add'>+		samsung,pins = "gpp1-6", "gpp1-5", "gpp1-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi3_cs: spi3-cs-pins {</div><div class='add'>+		samsung,pins = "gpp1-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi3_cs_func: spi3-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp1-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PERIC0 USI04_SPI */</div><div class='add'>+	spi4_bus: spi4-bus-pins {</div><div class='add'>+		samsung,pins = "gpp2-2", "gpp2-1", "gpp2-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi4_cs: spi4-cs-pins {</div><div class='add'>+		samsung,pins = "gpp2-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi4_cs_func: spi4-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp2-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PERIC0 USI05_SPI */</div><div class='add'>+	spi5_bus: spi5-bus-pins {</div><div class='add'>+		samsung,pins = "gpp2-6", "gpp2-5", "gpp2-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi5_cs: spi5-cs-pins {</div><div class='add'>+		samsung,pins = "gpp2-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi5_cs_func: spi5-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp2-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USI_PERIC0_USI00_UART */</div><div class='add'>+	uart0_bus: uart0-bus-pins {</div><div class='add'>+		samsung,pins = "gpp0-0", "gpp0-1", "gpp0-2", "gpp0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart0_bus_dual: uart0-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp0-0", "gpp0-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USI_PERIC0_USI01_UART */</div><div class='add'>+	uart1_bus: uart1-bus-pins {</div><div class='add'>+		samsung,pins = "gpp0-4", "gpp0-5", "gpp0-6", "gpp0-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart1_bus_dual: uart1-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp0-4", "gpp0-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USI_PERIC0_USI02_UART */</div><div class='add'>+	uart2_bus: uart2-bus-pins {</div><div class='add'>+		samsung,pins = "gpp1-0", "gpp1-1", "gpp1-2", "gpp1-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart2_bus_dual: uart2-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp1-0", "gpp1-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USI_PERIC0_USI03_UART */</div><div class='add'>+	uart3_bus: uart3-bus-pins {</div><div class='add'>+		samsung,pins = "gpp1-4", "gpp1-5", "gpp1-6", "gpp1-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart3_bus_dual: uart3-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp1-4", "gpp1-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USI_PERIC0_USI04_UART */</div><div class='add'>+	uart4_bus: uart4-bus-pins {</div><div class='add'>+		samsung,pins = "gpp2-0", "gpp2-1", "gpp2-2", "gpp2-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart4_bus_dual: uart4-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp2-0", "gpp2-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USI_PERIC0_USI05_UART */</div><div class='add'>+	uart5_bus: uart5-bus-pins {</div><div class='add'>+		samsung,pins = "gpp2-4", "gpp2-5", "gpp2-6", "gpp2-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart5_bus_dual: uart5-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp2-4", "gpp2-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_peric1 {</div><div class='add'>+	gpp3: gpp3-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp4: gpp4-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp5: gpp5-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpg1: gpg1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpg2: gpg2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpg3: gpg3-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PERIC1 USI06 */</div><div class='add'>+	hsi2c12_bus: hsi2c12-bus-pins {</div><div class='add'>+		samsung,pins = "gpp3-0", "gpp3-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PERIC1 USI06_I2C */</div><div class='add'>+	hsi2c13_bus: hsi2c13-bus-pins {</div><div class='add'>+		samsung,pins = "gpp3-2", "gpp3-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PERIC1 USI07 */</div><div class='add'>+	hsi2c14_bus: hsi2c14-bus-pins {</div><div class='add'>+		samsung,pins = "gpp3-4", "gpp3-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PERIC1 USI07_I2C */</div><div class='add'>+	hsi2c15_bus: hsi2c15-bus-pins {</div><div class='add'>+		samsung,pins = "gpp3-6", "gpp3-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PERIC1 USI08 */</div><div class='add'>+	hsi2c16_bus: hsi2c16-bus-pins {</div><div class='add'>+		samsung,pins = "gpp4-0", "gpp4-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PERIC1 USI08_I2C */</div><div class='add'>+	hsi2c17_bus: hsi2c17-bus-pins {</div><div class='add'>+		samsung,pins = "gpp4-2", "gpp4-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PERIC1 USI09 */</div><div class='add'>+	hsi2c18_bus: hsi2c18-bus-pins {</div><div class='add'>+		samsung,pins = "gpp4-4", "gpp4-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PERIC1 USI09_I2C */</div><div class='add'>+	hsi2c19_bus: hsi2c19-bus-pins {</div><div class='add'>+		samsung,pins = "gpp4-6", "gpp4-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PERIC1 USI10 */</div><div class='add'>+	hsi2c20_bus: hsi2c20-bus-pins {</div><div class='add'>+		samsung,pins = "gpp5-0", "gpp5-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PERIC1 USI10_I2C */</div><div class='add'>+	hsi2c21_bus: hsi2c21-bus-pins {</div><div class='add'>+		samsung,pins = "gpp5-2", "gpp5-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PERIC1 USI11 */</div><div class='add'>+	hsi2c22_bus: hsi2c22-bus-pins {</div><div class='add'>+		samsung,pins = "gpp5-4", "gpp5-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PERIC1 USI11_I2C */</div><div class='add'>+	hsi2c23_bus: hsi2c23-bus-pins {</div><div class='add'>+		samsung,pins = "gpp5-6", "gpp5-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PERIC1 USI06_SPI */</div><div class='add'>+	spi6_bus: spi6-bus-pins {</div><div class='add'>+		samsung,pins = "gpp3-2", "gpp3-1", "gpp3-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi6_cs: spi6-cs-pins {</div><div class='add'>+		samsung,pins = "gpp3-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi6_cs_func: spi6-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp3-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PERIC1 USI07_SPI */</div><div class='add'>+	spi7_bus: spi7-bus-pins {</div><div class='add'>+		samsung,pins = "gpp3-6", "gpp3-5", "gpp3-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi7_cs: spi7-cs-pins {</div><div class='add'>+		samsung,pins = "gpp3-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi7_cs_func: spi7-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp3-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PERIC1 USI08_SPI */</div><div class='add'>+	spi8_bus: spi8-bus-pins {</div><div class='add'>+		samsung,pins = "gpp4-2", "gpp4-1", "gpp4-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi8_cs: spi8-cs-pins {</div><div class='add'>+		samsung,pins = "gpp4-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi8_cs_func: spi8-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp4-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PERIC1 USI09_SPI */</div><div class='add'>+	spi9_bus: spi9-bus-pins {</div><div class='add'>+		samsung,pins = "gpp4-6", "gpp4-5", "gpp4-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi9_cs: spi9-cs-pins {</div><div class='add'>+		samsung,pins = "gpp4-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi9_cs_func: spi9-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp4-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PERIC1 USI10_SPI */</div><div class='add'>+	spi10_bus: spi10-pins {</div><div class='add'>+		samsung,pins = "gpp5-2", "gpp5-1", "gpp5-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi10_cs: spi10-cs-pins {</div><div class='add'>+		samsung,pins = "gpp5-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi10_cs_func: spi10-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp5-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PERIC1 USI11_SPI */</div><div class='add'>+	spi11_bus: spi11-pins {</div><div class='add'>+		samsung,pins = "gpp5-6", "gpp5-5", "gpp5-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi11_cs: spi11-cs-pins {</div><div class='add'>+		samsung,pins = "gpp5-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi11_cs_func: spi11-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp5-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USI_PERIC1_USI06_UART */</div><div class='add'>+	uart6_bus: uart6-bus-pins {</div><div class='add'>+		samsung,pins = "gpp3-3", "gpp3-2", "gpp3-1", "gpp3-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart6_bus_dual: uart6-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp3-0", "gpp3-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USI_PERIC1_USI07_UART */</div><div class='add'>+	uart7_bus: uart7-bus-pins {</div><div class='add'>+		samsung,pins = "gpp3-7", "gpp3-6", "gpp3-5", "gpp3-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart7_bus_dual: uart7-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp3-4", "gpp3-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USI_PERIC1_USI08_UART */</div><div class='add'>+	uart8_bus: uart8-bus-pins {</div><div class='add'>+		samsung,pins = "gpp4-3", "gpp4-2", "gpp4-1", "gpp4-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart8_bus_dual: uart8-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp4-0", "gpp4-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USI_PERIC1_USI09_UART */</div><div class='add'>+	uart9_bus: uart9-bus-pins {</div><div class='add'>+		samsung,pins = "gpp4-7", "gpp4-6", "gpp4-5", "gpp4-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart9_bus_dual: uart9-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp4-4", "gpp4-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USI_PERIC1_USI10_UART */</div><div class='add'>+	uart10_bus: uart10-bus-pins {</div><div class='add'>+		samsung,pins = "gpp5-3", "gpp5-2", "gpp5-1", "gpp5-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart10_bus_dual: uart10-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp5-0", "gpp5-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USI_PERIC1_USI11_UART */</div><div class='add'>+	uart11_bus: uart11-bus-pins {</div><div class='add'>+		samsung,pins = "gpp5-7", "gpp5-6", "gpp5-5", "gpp5-4";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart11_bus_dual: uart11-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp5-4", "gpp5-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts b/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts<br/>new file mode 100644<br/>index 000000000000..de2c1de51a76<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts</a></div><div class='hunk'>@@ -0,0 +1,139 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Samsung ExynosAutov9 SADK board device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2021 Samsung Electronics Co., Ltd.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "exynosautov9.dtsi"</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Samsung ExynosAuto v9 SADK board";</div><div class='add'>+	compatible = "samsung,exynosautov9-sadk", "samsung,exynosautov9";</div><div class='add'>+</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;serial_0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;serial_0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@80000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x80000000 0x0 0x77000000&gt;,</div><div class='add'>+		      &lt;0x8 0x80000000 0x1 0x7ba00000&gt;,</div><div class='add'>+		      &lt;0xa 0x00000000 0x2 0x00000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;key_wakeup &amp;key_volup &amp;key_voldown&gt;;</div><div class='add'>+</div><div class='add'>+		key-wakeup {</div><div class='add'>+			label = "Wakeup";</div><div class='add'>+			linux,code = &lt;KEY_WAKEUP&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpa0 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-volume-down {</div><div class='add'>+			label = "Volume Down";</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpg2 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-volume-up {</div><div class='add'>+			label = "Volume Up";</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpg1 5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ufs_0_fixed_vcc_reg: regulator-0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "ufs-vcc";</div><div class='add'>+		gpio = &lt;&amp;gpq0 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ufs_1_fixed_vcc_reg: regulator-1 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "ufs-vcc";</div><div class='add'>+		gpio = &lt;&amp;gpg2 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_alive {</div><div class='add'>+	key_wakeup: key-wakeup-pins {</div><div class='add'>+		samsung,pins = "gpa0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_peric1 {</div><div class='add'>+	key_voldown: key-voldown-pins {</div><div class='add'>+		samsung,pins = "gpg2-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	key_volup: key-volup-pins {</div><div class='add'>+		samsung,pins = "gpg1-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;EXYNOS5420_PIN_DRV_LV1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm_tout3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;serial_0 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart0_bus_dual&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ufs_0_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ufs_1_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ufs_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	vcc-supply = &lt;&amp;ufs_0_fixed_vcc_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ufs_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	vcc-supply = &lt;&amp;ufs_1_fixed_vcc_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usi_0 {</div><div class='add'>+	samsung,clkreq-on; /* needed for UART mode */</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xtcxo {</div><div class='add'>+	clock-frequency = &lt;26000000&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi<br/>new file mode 100644<br/>index 000000000000..66628cb32776<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynosautov9.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/exynosautov9.dtsi</a></div><div class='hunk'>@@ -0,0 +1,1639 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Samsung's ExynosAuto v9 SoC device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2021 Samsung Electronics Co., Ltd.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/samsung,exynosautov9.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/soc/samsung,boot-mode.h&gt;</div><div class='add'>+#include &lt;dt-bindings/soc/samsung,exynos-usi.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "samsung,exynosautov9";</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		pinctrl0 = &amp;pinctrl_alive;</div><div class='add'>+		pinctrl1 = &amp;pinctrl_aud;</div><div class='add'>+		pinctrl2 = &amp;pinctrl_fsys0;</div><div class='add'>+		pinctrl3 = &amp;pinctrl_fsys1;</div><div class='add'>+		pinctrl4 = &amp;pinctrl_fsys2;</div><div class='add'>+		pinctrl5 = &amp;pinctrl_peric0;</div><div class='add'>+		pinctrl6 = &amp;pinctrl_peric1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	arm-pmu {</div><div class='add'>+		compatible = "arm,cortex-a76-pmu";</div><div class='add'>+		interrupts = &lt;GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-affinity = &lt;&amp;cpu0&gt;, &lt;&amp;cpu1&gt;, &lt;&amp;cpu2&gt;, &lt;&amp;cpu3&gt;,</div><div class='add'>+				     &lt;&amp;cpu4&gt;, &lt;&amp;cpu5&gt;, &lt;&amp;cpu6&gt;, &lt;&amp;cpu7&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu-map {</div><div class='add'>+			cluster0 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu0&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu1&gt;;</div><div class='add'>+				};</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu2&gt;;</div><div class='add'>+				};</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu3&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cluster1 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu4&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu5&gt;;</div><div class='add'>+				};</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu6&gt;;</div><div class='add'>+				};</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu7&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a76";</div><div class='add'>+			reg = &lt;0x0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@100 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a76";</div><div class='add'>+			reg = &lt;0x100&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@200 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a76";</div><div class='add'>+			reg = &lt;0x200&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@300 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a76";</div><div class='add'>+			reg = &lt;0x300&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu4: cpu@10000 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a76";</div><div class='add'>+			reg = &lt;0x10000&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu5: cpu@10100 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a76";</div><div class='add'>+			reg = &lt;0x10100&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu6: cpu@10200 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a76";</div><div class='add'>+			reg = &lt;0x10200&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu7: cpu@10300 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a76";</div><div class='add'>+			reg = &lt;0x10300&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-1.0";</div><div class='add'>+		method = "smc";</div><div class='add'>+		cpu_suspend = &lt;0xc4000001&gt;;</div><div class='add'>+		cpu_off = &lt;0x84000002&gt;;</div><div class='add'>+		cpu_on = &lt;0xc4000003&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fixed-rate-clocks {</div><div class='add'>+		xtcxo: clock {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-output-names = "oscclk";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc: soc@0 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges = &lt;0x0 0x0 0x0 0x20000000&gt;;</div><div class='add'>+</div><div class='add'>+		chipid@10000000 {</div><div class='add'>+			compatible = "samsung,exynosautov9-chipid",</div><div class='add'>+				     "samsung,exynos850-chipid";</div><div class='add'>+			reg = &lt;0x10000000 0x24&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_peris: clock-controller@10020000 {</div><div class='add'>+			compatible = "samsung,exynosautov9-cmu-peris";</div><div class='add'>+			reg = &lt;0x10020000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;xtcxo&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top DOUT_CLKCMU_PERIS_BUS&gt;;</div><div class='add'>+			clock-names = "oscclk",</div><div class='add'>+				      "dout_clkcmu_peris_bus";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_peric0: clock-controller@10200000 {</div><div class='add'>+			compatible = "samsung,exynosautov9-cmu-peric0";</div><div class='add'>+			reg = &lt;0x10200000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;xtcxo&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top DOUT_CLKCMU_PERIC0_BUS&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top DOUT_CLKCMU_PERIC0_IP&gt;;</div><div class='add'>+			clock-names = "oscclk",</div><div class='add'>+				      "dout_clkcmu_peric0_bus",</div><div class='add'>+				      "dout_clkcmu_peric0_ip";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_peric1: clock-controller@10800000 {</div><div class='add'>+			compatible = "samsung,exynosautov9-cmu-peric1";</div><div class='add'>+			reg = &lt;0x10800000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;xtcxo&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top DOUT_CLKCMU_PERIC1_BUS&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top DOUT_CLKCMU_PERIC1_IP&gt;;</div><div class='add'>+			clock-names = "oscclk",</div><div class='add'>+				      "dout_clkcmu_peric1_bus",</div><div class='add'>+				      "dout_clkcmu_peric1_ip";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_fsys1: clock-controller@17040000 {</div><div class='add'>+			compatible = "samsung,exynosautov9-cmu-fsys1";</div><div class='add'>+			reg = &lt;0x17040000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;xtcxo&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top DOUT_CLKCMU_FSYS1_BUS&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top GOUT_CLKCMU_FSYS1_MMC_CARD&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top DOUT_CLKCMU_FSYS1_USBDRD&gt;;</div><div class='add'>+			clock-names = "oscclk",</div><div class='add'>+				      "dout_clkcmu_fsys1_bus",</div><div class='add'>+				      "gout_clkcmu_fsys1_mmc_card",</div><div class='add'>+				      "dout_clkcmu_fsys1_usbdrd";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_fsys0: clock-controller@17700000 {</div><div class='add'>+			compatible = "samsung,exynosautov9-cmu-fsys0";</div><div class='add'>+			reg = &lt;0x17700000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;xtcxo&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top DOUT_CLKCMU_FSYS0_BUS&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top DOUT_CLKCMU_FSYS0_PCIE&gt;;</div><div class='add'>+			clock-names = "oscclk",</div><div class='add'>+				      "dout_clkcmu_fsys0_bus",</div><div class='add'>+				      "dout_clkcmu_fsys0_pcie";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_fsys2: clock-controller@17c00000 {</div><div class='add'>+			compatible = "samsung,exynosautov9-cmu-fsys2";</div><div class='add'>+			reg = &lt;0x17c00000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;xtcxo&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top DOUT_CLKCMU_FSYS2_BUS&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top DOUT_CLKCMU_FSYS2_UFS_EMBD&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top DOUT_CLKCMU_FSYS2_ETHERNET&gt;;</div><div class='add'>+			clock-names = "oscclk",</div><div class='add'>+				      "dout_clkcmu_fsys2_bus",</div><div class='add'>+				      "dout_fsys2_clkcmu_ufs_embd",</div><div class='add'>+				      "dout_fsys2_clkcmu_ethernet";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_dpum: clock-controller@18c00000 {</div><div class='add'>+			compatible = "samsung,exynosautov9-cmu-dpum";</div><div class='add'>+			reg = &lt;0x18c00000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;xtcxo&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top DOUT_CLKCMU_DPUM_BUS&gt;;</div><div class='add'>+			clock-names = "oscclk", "bus";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sysmmu_dpum_0: sysmmu@18c80000 {</div><div class='add'>+			compatible = "samsung,exynos-sysmmu";</div><div class='add'>+			reg = &lt;0x18c80000 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_dpum CLK_GOUT_DPUM_SYSMMU_D0_CLK&gt;;</div><div class='add'>+			clock-names = "sysmmu";</div><div class='add'>+			#iommu-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sysmmu_dpum_1: sysmmu@18c90000 {</div><div class='add'>+			compatible = "samsung,exynos-sysmmu";</div><div class='add'>+			reg = &lt;0x18c90000 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_dpum CLK_GOUT_DPUM_SYSMMU_D1_CLK&gt;;</div><div class='add'>+			clock-names = "sysmmu";</div><div class='add'>+			#iommu-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sysmmu_dpum_2: sysmmu@18ca0000 {</div><div class='add'>+			compatible = "samsung,exynos-sysmmu";</div><div class='add'>+			reg = &lt;0x18ca0000 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_dpum CLK_GOUT_DPUM_SYSMMU_D2_CLK&gt;;</div><div class='add'>+			clock-names = "sysmmu";</div><div class='add'>+			#iommu-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sysmmu_dpum_3: sysmmu@18cb0000 {</div><div class='add'>+			compatible = "samsung,exynos-sysmmu";</div><div class='add'>+			reg = &lt;0x18cb0000 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_dpum CLK_GOUT_DPUM_SYSMMU_D3_CLK&gt;;</div><div class='add'>+			clock-names = "sysmmu";</div><div class='add'>+			#iommu-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_core: clock-controller@1b030000 {</div><div class='add'>+			compatible = "samsung,exynosautov9-cmu-core";</div><div class='add'>+			reg = &lt;0x1b030000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;xtcxo&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top DOUT_CLKCMU_CORE_BUS&gt;;</div><div class='add'>+			clock-names = "oscclk",</div><div class='add'>+				      "dout_clkcmu_core_bus";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_busmc: clock-controller@1b200000 {</div><div class='add'>+			compatible = "samsung,exynosautov9-cmu-busmc";</div><div class='add'>+			reg = &lt;0x1b200000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;xtcxo&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top DOUT_CLKCMU_BUSMC_BUS&gt;;</div><div class='add'>+			clock-names = "oscclk",</div><div class='add'>+				      "dout_clkcmu_busmc_bus";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_top: clock-controller@1b240000 {</div><div class='add'>+			compatible = "samsung,exynosautov9-cmu-top";</div><div class='add'>+			reg = &lt;0x1b240000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;xtcxo&gt;;</div><div class='add'>+			clock-names = "oscclk";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@10101000 {</div><div class='add'>+			compatible = "arm,gic-400";</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			#address-cells = &lt;0&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			reg = &lt;0x10101000 0x1000&gt;,</div><div class='add'>+			      &lt;0x10102000 0x2000&gt;,</div><div class='add'>+			      &lt;0x10104000 0x2000&gt;,</div><div class='add'>+			      &lt;0x10106000 0x2000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |</div><div class='add'>+						 IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pdma0: dma-controller@1b2e0000 {</div><div class='add'>+			compatible = "arm,pl330", "arm,primecell";</div><div class='add'>+			reg = &lt;0x1b2e0000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_busmc CLK_GOUT_BUSMC_PDMA0_PCLK&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			arm,pl330-broken-no-flushp;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_alive: pinctrl@10450000 {</div><div class='add'>+			compatible = "samsung,exynosautov9-pinctrl";</div><div class='add'>+			reg = &lt;0x10450000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			wakeup-interrupt-controller {</div><div class='add'>+				compatible = "samsung,exynosautov9-wakeup-eint",</div><div class='add'>+					     "samsung,exynos850-wakeup-eint",</div><div class='add'>+					     "samsung,exynos7-wakeup-eint";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_aud: pinctrl@19c60000 {</div><div class='add'>+			compatible = "samsung,exynosautov9-pinctrl";</div><div class='add'>+			reg = &lt;0x19c60000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_fsys0: pinctrl@17740000 {</div><div class='add'>+			compatible = "samsung,exynosautov9-pinctrl";</div><div class='add'>+			reg = &lt;0x17740000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_fsys1: pinctrl@17060000 {</div><div class='add'>+			compatible = "samsung,exynosautov9-pinctrl";</div><div class='add'>+			reg = &lt;0x17060000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_fsys2: pinctrl@17c30000 {</div><div class='add'>+			compatible = "samsung,exynosautov9-pinctrl";</div><div class='add'>+			reg = &lt;0x17c30000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_peric0: pinctrl@10230000 {</div><div class='add'>+			compatible = "samsung,exynosautov9-pinctrl";</div><div class='add'>+			reg = &lt;0x10230000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_peric1: pinctrl@10830000 {</div><div class='add'>+			compatible = "samsung,exynosautov9-pinctrl";</div><div class='add'>+			reg = &lt;0x10830000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmu_system_controller: system-controller@10460000 {</div><div class='add'>+			compatible = "samsung,exynosautov9-pmu",</div><div class='add'>+				     "samsung,exynos7-pmu", "syscon";</div><div class='add'>+			reg = &lt;0x10460000 0x10000&gt;;</div><div class='add'>+</div><div class='add'>+			reboot: syscon-reboot {</div><div class='add'>+				compatible = "syscon-reboot";</div><div class='add'>+				regmap = &lt;&amp;pmu_system_controller&gt;;</div><div class='add'>+				offset = &lt;0x3a00&gt;; /* SYSTEM_CONFIGURATION */</div><div class='add'>+				value = &lt;0x2&gt;;</div><div class='add'>+				mask = &lt;0x2&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reboot-mode {</div><div class='add'>+				compatible = "syscon-reboot-mode";</div><div class='add'>+				offset = &lt;0x810&gt;; /* SYSIP_DAT0 */</div><div class='add'>+				mode-bootloader = &lt;EXYNOSAUTOV9_BOOT_BOOTLOADER&gt;;</div><div class='add'>+				mode-fastboot = &lt;EXYNOSAUTOV9_BOOT_FASTBOOT&gt;;</div><div class='add'>+				mode-recovery = &lt;EXYNOSAUTOV9_BOOT_RECOVERY&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		syscon_fsys2: syscon@17c20000 {</div><div class='add'>+			compatible = "samsung,exynosautov9-fsys2-sysreg",</div><div class='add'>+				     "samsung,exynosautov9-sysreg", "syscon";</div><div class='add'>+			reg = &lt;0x17c20000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		syscon_peric0: syscon@10220000 {</div><div class='add'>+			compatible = "samsung,exynosautov9-peric0-sysreg",</div><div class='add'>+				     "samsung,exynosautov9-sysreg", "syscon";</div><div class='add'>+			reg = &lt;0x10220000 0x2000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		syscon_peric1: syscon@10820000 {</div><div class='add'>+			compatible = "samsung,exynosautov9-peric1-sysreg",</div><div class='add'>+				     "samsung,exynosautov9-sysreg", "syscon";</div><div class='add'>+			reg = &lt;0x10820000 0x2000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_0: usi@103000c0 {</div><div class='add'>+			compatible = "samsung,exynosautov9-usi",</div><div class='add'>+				     "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x103000c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric0 0x1000&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_MODE_UART&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PCLK_0&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			serial_0: serial@10300000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-uart",</div><div class='add'>+					     "samsung,exynos850-uart";</div><div class='add'>+				reg = &lt;0x10300000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart0_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PCLK_0&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				samsung,uart-fifosize = &lt;256&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_0: spi@10300000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-spi";</div><div class='add'>+				reg = &lt;0x10300000 0x30&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi0_bus &amp;spi0_cs_func&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_DOUT_PERIC0_USI00_USI&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PCLK_0&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0", "spi_ioclk";</div><div class='add'>+				samsung,spi-src-clk = &lt;0&gt;;</div><div class='add'>+				dmas = &lt;&amp;pdma0 1&gt;, &lt;&amp;pdma0 0&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				num-cs = &lt;1&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				fifo-depth = &lt;256&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			hsi2c_0: i2c@10300000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x10300000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c0_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PCLK_0&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_i2c_0: usi@103100c0 {</div><div class='add'>+			compatible = "samsung,exynosautov9-usi",</div><div class='add'>+				     "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x103100c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric0 0x1004&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_MODE_I2C&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PCLK_1&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_IPCLK_1&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_1: i2c@10310000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x10310000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c1_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_IPCLK_1&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PCLK_1&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_1: usi@103200c0 {</div><div class='add'>+			compatible = "samsung,exynosautov9-usi",</div><div class='add'>+				     "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x103200c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric0 0x1008&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_MODE_UART&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PCLK_2&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_IPCLK_2&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			serial_1: serial@10320000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-uart",</div><div class='add'>+					     "samsung,exynos850-uart";</div><div class='add'>+				reg = &lt;0x10320000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart1_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PCLK_2&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_IPCLK_2&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				samsung,uart-fifosize = &lt;256&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_1: spi@10320000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-spi";</div><div class='add'>+				reg = &lt;0x10320000 0x30&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi1_bus &amp;spi1_cs_func&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_IPCLK_2&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_DOUT_PERIC0_USI01_USI&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PCLK_2&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0", "spi_ioclk";</div><div class='add'>+				samsung,spi-src-clk = &lt;0&gt;;</div><div class='add'>+				dmas = &lt;&amp;pdma0 3&gt;, &lt;&amp;pdma0 2&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				num-cs = &lt;1&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				fifo-depth = &lt;256&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			hsi2c_2: i2c@10320000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x10320000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c2_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_IPCLK_2&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PCLK_2&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_i2c_1: usi@103300c0 {</div><div class='add'>+			compatible = "samsung,exynosautov9-usi",</div><div class='add'>+				     "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x103300c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric0 0x100c&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_MODE_I2C&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PCLK_3&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_IPCLK_3&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_3: i2c@10330000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x10330000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c3_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_IPCLK_3&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PCLK_3&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_2: usi@103400c0 {</div><div class='add'>+			compatible = "samsung,exynosautov9-usi",</div><div class='add'>+				     "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x103400c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric0 0x1010&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_MODE_UART&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PCLK_4&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_IPCLK_4&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			serial_2: serial@10340000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-uart",</div><div class='add'>+					     "samsung,exynos850-uart";</div><div class='add'>+				reg = &lt;0x10340000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart2_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PCLK_4&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_IPCLK_4&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_2: spi@10340000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-spi";</div><div class='add'>+				reg = &lt;0x10340000 0x30&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi2_bus &amp;spi2_cs_func&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_IPCLK_4&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_DOUT_PERIC0_USI02_USI&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PCLK_4&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0", "spi_ioclk";</div><div class='add'>+				samsung,spi-src-clk = &lt;0&gt;;</div><div class='add'>+				dmas = &lt;&amp;pdma0 5&gt;, &lt;&amp;pdma0 4&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				num-cs = &lt;1&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				fifo-depth = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			hsi2c_4: i2c@10340000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x10340000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c4_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_IPCLK_4&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PCLK_4&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_i2c_2: usi@103500c0 {</div><div class='add'>+			compatible = "samsung,exynosautov9-usi",</div><div class='add'>+				     "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x103500c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric0 0x1014&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_MODE_I2C&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PCLK_5&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_IPCLK_5&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_5: i2c@10350000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x10350000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c5_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_IPCLK_5&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PCLK_5&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_3: usi@103600c0 {</div><div class='add'>+			compatible = "samsung,exynosautov9-usi",</div><div class='add'>+				     "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x103600c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric0 0x1018&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_MODE_UART&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PCLK_6&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_IPCLK_6&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			serial_3: serial@10360000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-uart",</div><div class='add'>+					     "samsung,exynos850-uart";</div><div class='add'>+				reg = &lt;0x10360000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart3_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PCLK_6&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_IPCLK_6&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_3: spi@10360000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-spi";</div><div class='add'>+				reg = &lt;0x10360000 0x30&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi3_bus &amp;spi3_cs_func&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_IPCLK_6&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_DOUT_PERIC0_USI03_USI&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PCLK_6&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0", "spi_ioclk";</div><div class='add'>+				samsung,spi-src-clk = &lt;0&gt;;</div><div class='add'>+				dmas = &lt;&amp;pdma0 7&gt;, &lt;&amp;pdma0 6&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				num-cs = &lt;1&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				fifo-depth = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			hsi2c_6: i2c@10360000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x10360000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c6_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_IPCLK_6&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PCLK_6&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_i2c_3: usi@103700c0 {</div><div class='add'>+			compatible = "samsung,exynosautov9-usi",</div><div class='add'>+				     "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x103700c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric0 0x101c&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_MODE_I2C&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PCLK_7&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_IPCLK_7&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_7: i2c@10370000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x10370000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c7_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_IPCLK_7&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PCLK_7&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_4: usi@103800c0 {</div><div class='add'>+			compatible = "samsung,exynosautov9-usi",</div><div class='add'>+				     "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x103800c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric0 0x1020&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_MODE_UART&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PCLK_8&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_IPCLK_8&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			serial_4: serial@10380000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-uart",</div><div class='add'>+					     "samsung,exynos850-uart";</div><div class='add'>+				reg = &lt;0x10380000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart4_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PCLK_8&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_IPCLK_8&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_4: spi@10380000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-spi";</div><div class='add'>+				reg = &lt;0x10380000 0x30&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi4_bus &amp;spi4_cs_func&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_IPCLK_8&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_DOUT_PERIC0_USI04_USI&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PCLK_8&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0", "spi_ioclk";</div><div class='add'>+				samsung,spi-src-clk = &lt;0&gt;;</div><div class='add'>+				dmas = &lt;&amp;pdma0 9&gt;, &lt;&amp;pdma0 8&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				num-cs = &lt;1&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				fifo-depth = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			hsi2c_8: i2c@10380000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x10380000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c8_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_IPCLK_8&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PCLK_8&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_i2c_4: usi@103900c0 {</div><div class='add'>+			compatible = "samsung,exynosautov9-usi",</div><div class='add'>+				     "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x103900c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric0 0x1024&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_MODE_I2C&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PCLK_9&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_IPCLK_9&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_9: i2c@10390000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x10390000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c9_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_IPCLK_9&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PCLK_9&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_5: usi@103a00c0 {</div><div class='add'>+			compatible = "samsung,exynosautov9-usi",</div><div class='add'>+				     "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x103a00c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric0 0x1028&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_MODE_UART&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PCLK_10&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_IPCLK_10&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			serial_5: serial@103a0000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-uart",</div><div class='add'>+					     "samsung,exynos850-uart";</div><div class='add'>+				reg = &lt;0x103a0000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart5_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PCLK_10&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_IPCLK_10&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_5: spi@103a0000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-spi";</div><div class='add'>+				reg = &lt;0x103a0000 0x30&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi5_bus &amp;spi5_cs_func&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_IPCLK_10&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_DOUT_PERIC0_USI05_USI&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PCLK_10&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0", "spi_ioclk";</div><div class='add'>+				samsung,spi-src-clk = &lt;0&gt;;</div><div class='add'>+				dmas = &lt;&amp;pdma0 11&gt;, &lt;&amp;pdma0 10&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				num-cs = &lt;1&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				fifo-depth = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			hsi2c_10: i2c@103a0000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x103a0000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c10_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_IPCLK_10&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PCLK_10&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_i2c_5: usi@103b00c0 {</div><div class='add'>+			compatible = "samsung,exynosautov9-usi",</div><div class='add'>+				     "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x103b00c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric0 0x102c&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_MODE_I2C&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PCLK_11&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_IPCLK_11&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_11: i2c@103b0000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x103b0000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c11_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_IPCLK_11&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PCLK_11&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_6: usi@109000c0 {</div><div class='add'>+			compatible = "samsung,exynosautov9-usi",</div><div class='add'>+				     "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x109000c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric1 0x1000&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_MODE_UART&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PCLK_0&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_IPCLK_0&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			serial_6: serial@10900000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-uart",</div><div class='add'>+					     "samsung,exynos850-uart";</div><div class='add'>+				reg = &lt;0x10900000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart6_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PCLK_0&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_IPCLK_0&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				samsung,uart-fifosize = &lt;256&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_6: spi@10900000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-spi";</div><div class='add'>+				reg = &lt;0x10900000 0x30&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi6_bus &amp;spi6_cs_func&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_IPCLK_0&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI06_USI&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PCLK_0&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0", "spi_ioclk";</div><div class='add'>+				samsung,spi-src-clk = &lt;0&gt;;</div><div class='add'>+				dmas = &lt;&amp;pdma0 13&gt;, &lt;&amp;pdma0 12&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				num-cs = &lt;1&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				fifo-depth = &lt;256&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			hsi2c_12: i2c@10900000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x10900000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c12_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_IPCLK_0&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PCLK_0&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_i2c_6: usi@109100c0 {</div><div class='add'>+			compatible = "samsung,exynosautov9-usi",</div><div class='add'>+				     "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x109100c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric1 0x1004&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_MODE_I2C&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PCLK_1&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_IPCLK_1&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_13: i2c@10910000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x10910000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c13_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_IPCLK_1&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PCLK_1&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_7: usi@109200c0 {</div><div class='add'>+			compatible = "samsung,exynosautov9-usi",</div><div class='add'>+				     "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x109200c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric1 0x1008&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_MODE_UART&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PCLK_2&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_IPCLK_2&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			serial_7: serial@10920000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-uart",</div><div class='add'>+					     "samsung,exynos850-uart";</div><div class='add'>+				reg = &lt;0x10920000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart7_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PCLK_2&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_IPCLK_2&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_7: spi@10920000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-spi";</div><div class='add'>+				reg = &lt;0x10920000 0x30&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi7_bus &amp;spi7_cs_func&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_IPCLK_2&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI07_USI&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PCLK_2&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0", "spi_ioclk";</div><div class='add'>+				samsung,spi-src-clk = &lt;0&gt;;</div><div class='add'>+				dmas = &lt;&amp;pdma0 15&gt;, &lt;&amp;pdma0 14&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				num-cs = &lt;1&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				fifo-depth = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			hsi2c_14: i2c@10920000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x10920000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c14_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_IPCLK_2&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PCLK_2&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_i2c_7: usi@109300c0 {</div><div class='add'>+			compatible = "samsung,exynosautov9-usi",</div><div class='add'>+				     "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x109300c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric1 0x100c&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_MODE_I2C&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PCLK_3&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_IPCLK_3&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_15: i2c@10930000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x10930000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c15_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_IPCLK_3&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PCLK_3&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_8: usi@109400c0 {</div><div class='add'>+			compatible = "samsung,exynosautov9-usi",</div><div class='add'>+				     "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x109400c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric1 0x1010&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_MODE_UART&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PCLK_4&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_IPCLK_4&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			serial_8: serial@10940000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-uart",</div><div class='add'>+					     "samsung,exynos850-uart";</div><div class='add'>+				reg = &lt;0x10940000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart8_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PCLK_4&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_IPCLK_4&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_8: spi@10940000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-spi";</div><div class='add'>+				reg = &lt;0x10940000 0x30&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi8_bus &amp;spi8_cs_func&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_IPCLK_4&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI08_USI&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PCLK_4&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0", "spi_ioclk";</div><div class='add'>+				samsung,spi-src-clk = &lt;0&gt;;</div><div class='add'>+				dmas = &lt;&amp;pdma0 17&gt;, &lt;&amp;pdma0 16&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				num-cs = &lt;1&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				fifo-depth = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			hsi2c_16: i2c@10940000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x10940000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c16_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_IPCLK_4&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PCLK_4&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_i2c_8: usi@109500c0 {</div><div class='add'>+			compatible = "samsung,exynosautov9-usi",</div><div class='add'>+				     "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x109500c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric1 0x1014&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_MODE_I2C&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PCLK_5&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_IPCLK_5&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_17: i2c@10950000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x10950000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c17_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_IPCLK_5&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PCLK_5&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_9: usi@109600c0 {</div><div class='add'>+			compatible = "samsung,exynosautov9-usi",</div><div class='add'>+				     "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x109600c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric1 0x1018&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_MODE_UART&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PCLK_6&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_IPCLK_6&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			serial_9: serial@10960000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-uart",</div><div class='add'>+					     "samsung,exynos850-uart";</div><div class='add'>+				reg = &lt;0x10960000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart9_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PCLK_6&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_IPCLK_6&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_9: spi@10960000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-spi";</div><div class='add'>+				reg = &lt;0x10960000 0x30&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi9_bus &amp;spi9_cs_func&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_IPCLK_6&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI09_USI&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PCLK_6&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0", "spi_ioclk";</div><div class='add'>+				samsung,spi-src-clk = &lt;0&gt;;</div><div class='add'>+				dmas = &lt;&amp;pdma0 19&gt;, &lt;&amp;pdma0 18&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				num-cs = &lt;1&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				fifo-depth = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			hsi2c_18: i2c@10960000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x10960000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c18_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_IPCLK_6&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PCLK_6&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_i2c_9: usi@109700c0 {</div><div class='add'>+			compatible = "samsung,exynosautov9-usi",</div><div class='add'>+				     "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x109700c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric1 0x101c&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_MODE_I2C&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PCLK_7&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_IPCLK_7&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_19: i2c@10970000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x10970000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c19_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_IPCLK_7&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PCLK_7&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_10: usi@109800c0 {</div><div class='add'>+			compatible = "samsung,exynosautov9-usi",</div><div class='add'>+				     "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x109800c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric1 0x1020&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_MODE_UART&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PCLK_8&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_IPCLK_8&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			serial_10: serial@10980000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-uart",</div><div class='add'>+					     "samsung,exynos850-uart";</div><div class='add'>+				reg = &lt;0x10980000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart10_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PCLK_8&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_IPCLK_8&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_10: spi@10980000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-spi";</div><div class='add'>+				reg = &lt;0x10980000 0x30&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi10_bus &amp;spi10_cs_func&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_IPCLK_8&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI10_USI&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PCLK_8&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0", "spi_ioclk";</div><div class='add'>+				samsung,spi-src-clk = &lt;0&gt;;</div><div class='add'>+				dmas = &lt;&amp;pdma0 21&gt;, &lt;&amp;pdma0 20&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				num-cs = &lt;1&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				fifo-depth = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			hsi2c_20: i2c@10980000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x10980000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c20_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_IPCLK_8&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PCLK_8&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_i2c_10: usi@109900c0 {</div><div class='add'>+			compatible = "samsung,exynosautov9-usi",</div><div class='add'>+				     "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x109900c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric1 0x1024&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_MODE_I2C&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PCLK_9&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_IPCLK_9&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_21: i2c@10990000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x10990000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c21_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_IPCLK_9&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PCLK_9&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_11: usi@109a00c0 {</div><div class='add'>+			compatible = "samsung,exynosautov9-usi",</div><div class='add'>+				     "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x109a00c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric1 0x1028&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_MODE_UART&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PCLK_10&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_IPCLK_10&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			serial_11: serial@109a0000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-uart",</div><div class='add'>+					     "samsung,exynos850-uart";</div><div class='add'>+				reg = &lt;0x109a0000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart11_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PCLK_10&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_IPCLK_10&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_11: spi@109a0000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-spi";</div><div class='add'>+				reg = &lt;0x109a0000 0x30&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi11_bus &amp;spi11_cs_func&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_IPCLK_10&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI11_USI&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PCLK_10&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0", "spi_ioclk";</div><div class='add'>+				samsung,spi-src-clk = &lt;0&gt;;</div><div class='add'>+				num-cs = &lt;1&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				fifo-depth = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			hsi2c_22: i2c@109a0000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x109a0000 0xc0&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c22_bus&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_IPCLK_10&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PCLK_10&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_i2c_11: usi@109b00c0 {</div><div class='add'>+			compatible = "samsung,exynosautov9-usi",</div><div class='add'>+				     "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x109b00c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric1 0x102c&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_MODE_I2C&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PCLK_11&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_IPCLK_11&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_23: i2c@109b0000 {</div><div class='add'>+				compatible = "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x109b0000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c23_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_IPCLK_11&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PCLK_11&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ufs_0_phy: phy@17e04000 {</div><div class='add'>+			compatible = "samsung,exynosautov9-ufs-phy";</div><div class='add'>+			reg = &lt;0x17e04000 0xc00&gt;;</div><div class='add'>+			reg-names = "phy-pma";</div><div class='add'>+			samsung,pmu-syscon = &lt;&amp;pmu_system_controller&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+			clocks = &lt;&amp;xtcxo&gt;;</div><div class='add'>+			clock-names = "ref_clk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ufs_0: ufs@17e00000 {</div><div class='add'>+			compatible = "samsung,exynosautov9-ufs";</div><div class='add'>+</div><div class='add'>+			reg = &lt;0x17e00000 0x100&gt;,</div><div class='add'>+			      &lt;0x17e01100 0x410&gt;,</div><div class='add'>+			      &lt;0x17e80000 0x8000&gt;,</div><div class='add'>+			      &lt;0x17dc0000 0x2200&gt;;</div><div class='add'>+			reg-names = "hci", "vs_hci", "unipro", "ufsp";</div><div class='add'>+			interrupts = &lt;GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD0_ACLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD0_UNIPRO&gt;;</div><div class='add'>+			clock-names = "core_clk", "sclk_unipro_main";</div><div class='add'>+			freq-table-hz = &lt;0 0&gt;, &lt;0 0&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;ufs_rst_n &amp;ufs_refclk_out&gt;;</div><div class='add'>+			phys = &lt;&amp;ufs_0_phy&gt;;</div><div class='add'>+			phy-names = "ufs-phy";</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_fsys2 0x710&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ufs_1_phy: phy@17f04000 {</div><div class='add'>+			compatible = "samsung,exynosautov9-ufs-phy";</div><div class='add'>+			reg = &lt;0x17f04000 0xc00&gt;;</div><div class='add'>+			reg-names = "phy-pma";</div><div class='add'>+			samsung,pmu-syscon = &lt;&amp;pmu_system_controller 0x72c&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+			clocks = &lt;&amp;xtcxo&gt;;</div><div class='add'>+			clock-names = "ref_clk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ufs_1: ufs@17f00000 {</div><div class='add'>+			compatible = "samsung,exynosautov9-ufs";</div><div class='add'>+</div><div class='add'>+			reg = &lt;0x17f00000 0x100&gt;,</div><div class='add'>+			      &lt;0x17f01100 0x410&gt;,</div><div class='add'>+			      &lt;0x17f80000 0x8000&gt;,</div><div class='add'>+			      &lt;0x17de0000 0x2200&gt;;</div><div class='add'>+			reg-names = "hci", "vs_hci", "unipro", "ufsp";</div><div class='add'>+			interrupts = &lt;GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD1_ACLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO&gt;;</div><div class='add'>+			clock-names = "core_clk", "sclk_unipro_main";</div><div class='add'>+			freq-table-hz = &lt;0 0&gt;, &lt;0 0&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;ufs_rst_n_1 &amp;ufs_refclk_out_1&gt;;</div><div class='add'>+			phys = &lt;&amp;ufs_1_phy&gt;;</div><div class='add'>+			phy-names = "ufs-phy";</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_fsys2 0x714&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		watchdog_cl0: watchdog@10050000 {</div><div class='add'>+			compatible = "samsung,exynosautov9-wdt";</div><div class='add'>+			reg = &lt;0x10050000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peris CLK_GOUT_WDT_CLUSTER0&gt;, &lt;&amp;xtcxo&gt;;</div><div class='add'>+			clock-names = "watchdog", "watchdog_src";</div><div class='add'>+			samsung,syscon-phandle = &lt;&amp;pmu_system_controller&gt;;</div><div class='add'>+			samsung,cluster-index = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		watchdog_cl1: watchdog@10060000 {</div><div class='add'>+			compatible = "samsung,exynosautov9-wdt";</div><div class='add'>+			reg = &lt;0x10060000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peris CLK_GOUT_WDT_CLUSTER1&gt;, &lt;&amp;xtcxo&gt;;</div><div class='add'>+			clock-names = "watchdog", "watchdog_src";</div><div class='add'>+			samsung,syscon-phandle = &lt;&amp;pmu_system_controller&gt;;</div><div class='add'>+			samsung,cluster-index = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pwm: pwm@103f0000 {</div><div class='add'>+			compatible = "samsung,exynosautov9-pwm",</div><div class='add'>+				     "samsung,exynos4210-pwm";</div><div class='add'>+			reg = &lt;0x103f0000 0x100&gt;;</div><div class='add'>+			samsung,pwm-outputs = &lt;0&gt;, &lt;1&gt;, &lt;2&gt;, &lt;3&gt;;</div><div class='add'>+			#pwm-cells = &lt;3&gt;;</div><div class='add'>+			clocks = &lt;&amp;xtcxo&gt;;</div><div class='add'>+			clock-names = "timers";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include "exynosautov9-pinctrl.dtsi"</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/exynosautov920-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920-pinctrl.dtsi<br/>new file mode 100644<br/>index 000000000000..663e8265cbf5<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynosautov920-pinctrl.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/exynosautov920-pinctrl.dtsi</a></div><div class='hunk'>@@ -0,0 +1,1266 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Samsung's ExynosAutov920 SoC pin-mux and pin-config device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2023 Samsung Electronics Co., Ltd.</div><div class='add'>+ *</div><div class='add'>+ * Samsung's ExynosAutov920 SoC pin-mux and pin-config options are listed as</div><div class='add'>+ * device tree nodes in this file.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+</div><div class='add'>+#include "exynos-pinctrl.h"</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_alive {</div><div class='add'>+	gpa0: gpa0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpa1: gpa1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpq0: gpq0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_aud {</div><div class='add'>+	gpb0: gpb0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpb1: gpb1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpb2: gpb2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpb3: gpb3-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpb4: gpb4-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpb5: gpb5-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpb6: gpb6-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_hsi0 {</div><div class='add'>+	gph0: gph0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gph1: gph1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_hsi1 {</div><div class='add'>+	gph8: gph8-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_hsi2 {</div><div class='add'>+	gph3: gph3-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gph4: gph4-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gph5: gph5-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gph6: gph6-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_hsi2ufs {</div><div class='add'>+	gph2: gph2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ufs_refclk_out: ufs-refclk-out-pins {</div><div class='add'>+		samsung,pins = "gph2-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ufs_rst_n: ufs-rst-n-pins {</div><div class='add'>+		samsung,pins = "gph2-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ufs_refclk_out_1: ufs-refclk-out-1-pins {</div><div class='add'>+		samsung,pins = "gph2-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ufs_rst_n_1: ufs-rst-n-1-pins {</div><div class='add'>+		samsung,pins = "gph2-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;EXYNOS_PIN_PULL_DOWN&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_peric0 {</div><div class='add'>+	gpg0: gpg0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpg2: gpg2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpg3: gpg3-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpg4: gpg4-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpg5: gpg5-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp0: gpp0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp1: gpp1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp2: gpp2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp3: gpp3-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp4: gpp4-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PWM PERIC0 */</div><div class='add'>+	pwm_tout0: pwm-tout0-pins {</div><div class='add'>+		samsung,pins = "gpg0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_4&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pwm_tout1: pwm-tout1-pins {</div><div class='add'>+		samsung,pins = "gpg0-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_4&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pwm_tout2: pwm-tout2-pins {</div><div class='add'>+		samsung,pins = "gpg0-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_4&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pwm_tout3: pwm-tout3-pins {</div><div class='add'>+		samsung,pins = "gpg0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_4&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* UART PERIC0_USI00 */</div><div class='add'>+	uart0_bus: uart0-bus-pins {</div><div class='add'>+		samsung,pins = "gpp0-0", "gpp0-1", "gpp0-2", "gpp0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart0_bus_dual: uart0-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp0-0", "gpp0-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* UART PERIC0_USI01 */</div><div class='add'>+	uart1_bus: uart1-bus-pins {</div><div class='add'>+		samsung,pins = "gpp0-4", "gpp0-5", "gpp0-6", "gpp0-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart1_bus_dual: uart1-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp0-4", "gpp0-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* UART PERIC0_USI02 */</div><div class='add'>+	uart2_bus: uart2-bus-pins {</div><div class='add'>+		samsung,pins = "gpp1-0", "gpp1-1", "gpp1-2", "gpp1-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart2_bus_dual: uart2-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp1-0", "gpp1-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* UART PERIC0_USI03 */</div><div class='add'>+	uart3_bus: uart3-bus-pins {</div><div class='add'>+		samsung,pins = "gpp1-4", "gpp1-5", "gpp1-6", "gpp1-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart3_bus_dual: uart3-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp1-4", "gpp1-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* UART PERIC0_USI04 */</div><div class='add'>+	uart4_bus: uart4-bus-pins {</div><div class='add'>+		samsung,pins = "gpp2-0", "gpp2-1", "gpp2-2", "gpp2-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart4_bus_dual: uart4-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp2-0", "gpp2-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* UART PERIC0_USI05 */</div><div class='add'>+	uart5_bus: uart5-bus-pins {</div><div class='add'>+		samsung,pins = "gpp2-4", "gpp2-5", "gpp2-6", "gpp2-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart5_bus_dual: uart5-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp2-4", "gpp2-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* UART PERIC0_USI06 */</div><div class='add'>+	uart6_bus: uart6-bus-pins {</div><div class='add'>+		samsung,pins = "gpp3-0", "gpp3-1", "gpp3-2", "gpp3-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart6_bus_dual: uart6-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp3-0", "gpp3-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* UART PERIC0_USI07 */</div><div class='add'>+	uart7_bus: uart7-bus-pins {</div><div class='add'>+		samsung,pins = "gpp3-4", "gpp3-5", "gpp3-6", "gpp3-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart7_bus_dual: uart7-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp3-4", "gpp3-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* UART PERIC0_USI08 */</div><div class='add'>+	uart8_bus: uart8-bus-pins {</div><div class='add'>+		samsung,pins = "gpp4-0", "gpp4-1", "gpp4-2", "gpp4-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart8_bus_dual: uart8-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp4-0", "gpp4-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* I2C PERIC0 USI00  */</div><div class='add'>+	hsi2c0_bus: hsi2c0-bus-pins {</div><div class='add'>+		samsung,pins = "gpp0-0", "gpp0-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* I2C PERIC0 USI00_I2C */</div><div class='add'>+	hsi2c1_bus: hsi2c1-bus-pins {</div><div class='add'>+		samsung,pins = "gpp0-2", "gpp0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* I2C PERIC0 USI01 */</div><div class='add'>+	hsi2c2_bus: hsi2c2-bus-pins {</div><div class='add'>+		samsung,pins = "gpp0-4", "gpp0-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* I2C PERIC0 USI01_I2C */</div><div class='add'>+	hsi2c3_bus: hsi2c3-bus-pins {</div><div class='add'>+		samsung,pins = "gpp0-6", "gpp0-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* I2C PERIC0 USI02 */</div><div class='add'>+	hsi2c4_bus: hsi2c4-bus-pins {</div><div class='add'>+		samsung,pins = "gpp1-0", "gpp1-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* I2C PERIC0 USI02_I2C */</div><div class='add'>+	hsi2c5_bus: hsi2c5-bus-pins {</div><div class='add'>+		samsung,pins = "gpp1-2", "gpp1-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* I2C PERIC0 USI03 */</div><div class='add'>+	hsi2c6_bus: hsi2c6-bus-pins {</div><div class='add'>+		samsung,pins = "gpp1-4", "gpp1-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* I2C PERIC0 USI03_I2C */</div><div class='add'>+	hsi2c7_bus: hsi2c7-bus-pins {</div><div class='add'>+		samsung,pins = "gpp1-6", "gpp1-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* I2C PERIC0 USI04 */</div><div class='add'>+	hsi2c8_bus: hsi2c8-bus-pins {</div><div class='add'>+		samsung,pins = "gpp2-0", "gpp2-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* I2C PERIC0 USI04_I2C */</div><div class='add'>+	hsi2c9_bus: hsi2c9-bus-pins {</div><div class='add'>+		samsung,pins = "gpp2-2", "gpp2-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* I2C PERIC0 USI05 */</div><div class='add'>+	hsi2c10_bus: hsi2c10-bus-pins {</div><div class='add'>+		samsung,pins = "gpp2-4", "gpp2-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* I2C PERIC0 USI05_I2C */</div><div class='add'>+	hsi2c11_bus: hsi2c11-bus-pins {</div><div class='add'>+		samsung,pins = "gpp2-6", "gpp2-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* I2C PERIC0 USI06 */</div><div class='add'>+	hsi2c12_bus: hsi2c12-bus-pins {</div><div class='add'>+		samsung,pins = "gpp3-0", "gpp3-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* I2C PERIC0 USI06_I2C */</div><div class='add'>+	hsi2c13_bus: hsi2c13-bus-pins {</div><div class='add'>+		samsung,pins = "gpp3-2", "gpp3-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* I2C PERIC0 USI07 */</div><div class='add'>+	hsi2c14_bus: hsi2c14-bus-pins {</div><div class='add'>+		samsung,pins = "gpp3-4", "gpp3-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* I2C PERIC0 USI07_I2C */</div><div class='add'>+	hsi2c15_bus: hsi2c15-bus-pins {</div><div class='add'>+		samsung,pins = "gpp3-6", "gpp3-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* I2C PERIC0 USI08 */</div><div class='add'>+	hsi2c16_bus: hsi2c16-bus-pins {</div><div class='add'>+		samsung,pins = "gpp4-0", "gpp4-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* I2C PERIC0 USI08_I2C */</div><div class='add'>+	hsi2c17_bus: hsi2c17-bus-pins {</div><div class='add'>+		samsung,pins = "gpp4-2", "gpp4-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SPI PERIC0 USI00 */</div><div class='add'>+	spi0_bus: spi0-bus-pins {</div><div class='add'>+		samsung,pins = "gpp0-0", "gpp0-1", "gpp0-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi0_cs: spi0-cs-pins {</div><div class='add'>+		samsung,pins = "gpp0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi0_cs_func: spi0-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp0-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SPI PERIC0 USI01 */</div><div class='add'>+	spi1_bus: spi1-bus-pins {</div><div class='add'>+		samsung,pins = "gpp0-4", "gpp0-5", "gpp0-6";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi1_cs: spi1-cs-pins {</div><div class='add'>+		samsung,pins = "gpp0-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi1_cs_func: spi1-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp0-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SPI PERIC0 USI02 */</div><div class='add'>+	spi2_bus: spi2-bus-pins {</div><div class='add'>+		samsung,pins = "gpp1-0", "gpp1-1", "gpp1-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi2_cs: spi2-cs-pins {</div><div class='add'>+		samsung,pins = "gpp1-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi2_cs_func: spi2-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp1-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SPI PERIC0 USI03 */</div><div class='add'>+	spi3_bus: spi3-bus-pins {</div><div class='add'>+		samsung,pins = "gpp1-4", "gpp1-5", "gpp1-6";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi3_cs: spi3-cs-pins {</div><div class='add'>+		samsung,pins = "gpp1-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi3_cs_func: spi3-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp1-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SPI PERIC0 USI04 */</div><div class='add'>+	spi4_bus: spi4-bus-pins {</div><div class='add'>+		samsung,pins = "gpp2-0", "gpp2-1", "gpp2-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi4_cs: spi4-cs-pins {</div><div class='add'>+		samsung,pins = "gpp2-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi4_cs_func: spi4-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp2-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SPI PERIC0 USI05 */</div><div class='add'>+	spi5_bus: spi5-bus-pins {</div><div class='add'>+		samsung,pins = "gpp2-4", "gpp2-5", "gpp2-6";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi5_cs: spi5-cs-pins {</div><div class='add'>+		samsung,pins = "gpp2-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi5_cs_func: spi5-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp2-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SPI PERIC0 USI06 */</div><div class='add'>+	spi6_bus: spi6-bus-pins {</div><div class='add'>+		samsung,pins = "gpp3-0", "gpp3-1", "gpp3-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi6_cs: spi6-cs-pins {</div><div class='add'>+		samsung,pins = "gpp3-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi6_cs_func: spi6-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp3-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SPI PERIC0 USI07 */</div><div class='add'>+	spi7_bus: spi7-bus-pins {</div><div class='add'>+		samsung,pins = "gpp3-4", "gpp3-5", "gpp3-6";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi7_cs: spi7-cs-pins {</div><div class='add'>+		samsung,pins = "gpp3-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi7_cs_func: spi7-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp3-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SPI PERIC0 USI08 */</div><div class='add'>+	spi8_bus: spi8-bus-pins {</div><div class='add'>+		samsung,pins = "gpp4-0", "gpp4-1", "gpp4-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi8_cs: spi8-cs-pins {</div><div class='add'>+		samsung,pins = "gpp4-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi8_cs_func: spi8-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp4-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* I3C PERIC0 */</div><div class='add'>+	i3c0_bus: i3c0-bus-pins {</div><div class='add'>+		samsung,pins = "gpp2-6", "gpp2-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_4&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i3c1_bus: i3c1-bus-pins {</div><div class='add'>+		samsung,pins = "gpp3-2", "gpp3-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_4&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i3c2_bus: i3c2-bus-pins {</div><div class='add'>+		samsung,pins = "gpp3-6", "gpp3-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_4&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i3c3_bus: i3c3-bus-pins {</div><div class='add'>+		samsung,pins = "gpp4-2", "gpp4-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_4&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_peric1 {</div><div class='add'>+	gpg1: gpg1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp5: gpp5-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp6: gpp6-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp7: gpp7-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp8: gpp8-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp9: gpp9-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp10: gpp10-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp11: gpp11-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp12: gpp12-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* UART PERIC1 USI09 */</div><div class='add'>+	uart9_bus: uart9-bus-pins {</div><div class='add'>+		samsung,pins = "gpp5-0", "gpp5-1", "gpp5-2", "gpp5-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart9_bus_dual: uart9-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp5-0", "gpp5-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* UART PERIC1 USI10 */</div><div class='add'>+	uart10_bus: uart10-bus-pins {</div><div class='add'>+		samsung,pins = "gpp5-4", "gpp5-5", "gpp5-6", "gpp5-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart10_bus_dual: uart10-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp5-4", "gpp5-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* UART PERIC1 USI11 */</div><div class='add'>+	uart11_bus: uart11-bus-pins {</div><div class='add'>+		samsung,pins = "gpp10-0", "gpp10-1", "gpp10-2", "gpp10-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart11_bus_dual: uart11-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp10-0", "gpp10-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* UART PERIC1_USI12 */</div><div class='add'>+	uart12_bus: uart12-bus-pins {</div><div class='add'>+		samsung,pins = "gpp7-0", "gpp7-1", "gpp7-2", "gpp7-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart12_bus_dual: uart12-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp7-0", "gpp7-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* UART PERIC1_USI13 */</div><div class='add'>+	uart13_bus: uart13-bus-pins {</div><div class='add'>+		samsung,pins = "gpp7-4", "gpp7-5", "gpp7-6", "gpp7-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart13_bus_dual: uart13-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp7-4", "gpp7-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* UART PERIC1 USI14 */</div><div class='add'>+	uart14_bus: uart14-bus-pins {</div><div class='add'>+		samsung,pins = "gpp8-0", "gpp8-1", "gpp8-2", "gpp8-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart14_bus_dual: uart14-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp8-0", "gpp8-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* UART PERIC1 USI15 */</div><div class='add'>+	uart15_bus: uart15-bus-pins {</div><div class='add'>+		samsung,pins = "gpp11-0", "gpp11-1", "gpp11-2", "gpp11-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart15_bus_dual: uart15-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp11-0", "gpp11-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* UART PERIC1 USI16 */</div><div class='add'>+	uart16_bus: uart16-bus-pins {</div><div class='add'>+		samsung,pins = "gpp9-0", "gpp9-1", "gpp9-2", "gpp9-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart16_bus_dual: uart16-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp9-0", "gpp9-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* UART PERIC1 USI17 */</div><div class='add'>+	uart17_bus: uart17-bus-pins {</div><div class='add'>+		samsung,pins = "gpp12-0", "gpp12-1", "gpp12-2", "gpp12-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart17_bus_dual: uart17-bus-dual-pins {</div><div class='add'>+		samsung,pins = "gpp12-0", "gpp12-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* I2C PERIC1 USI09 */</div><div class='add'>+	hsi2c18_bus: hsi2c18-bus-pins {</div><div class='add'>+		samsung,pins = "gpp5-0", "gpp5-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* I2C PERIC1 USI09_I2C */</div><div class='add'>+	hsi2c19_bus: hsi2c19-bus-pins {</div><div class='add'>+		samsung,pins = "gpp5-2", "gpp5-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* I2C PERIC1 USI10 */</div><div class='add'>+	hsi2c20_bus: hsi2c20-bus-pins {</div><div class='add'>+		samsung,pins = "gpp5-4", "gpp5-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* I2C PERIC1 USI10_I2C */</div><div class='add'>+	hsi2c21_bus: hsi2c21-bus-pins {</div><div class='add'>+		samsung,pins = "gpp5-6", "gpp5-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* I2C PERIC1 USI11 */</div><div class='add'>+	hsi2c22_bus: hsi2c22-bus-pins {</div><div class='add'>+		samsung,pins = "gpp10-0", "gpp10-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* I2C PERIC1 USI11_I2C */</div><div class='add'>+	hsi2c23_bus: hsi2c23-bus-pins {</div><div class='add'>+		samsung,pins = "gpp10-2", "gpp10-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* I2C PERIC1 USI12 */</div><div class='add'>+	hsi2c24_bus: hsi2c24-bus-pins {</div><div class='add'>+		samsung,pins = "gpp7-0", "gpp7-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* I2C PERIC1 USI12_I2C */</div><div class='add'>+	hsi2c25_bus: hsi2c25-bus-pins {</div><div class='add'>+		samsung,pins = "gpp7-2", "gpp7-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* I2C PERIC1 USI13 */</div><div class='add'>+	hsi2c26_bus: hsi2c26-bus-pins {</div><div class='add'>+		samsung,pins = "gpp7-4", "gpp7-5";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* I2C PERIC1 USI13_I2C */</div><div class='add'>+	hsi2c27_bus: hsi2c27-bus-pins {</div><div class='add'>+		samsung,pins = "gpp7-6", "gpp7-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* I2C PERIC1 USI14 */</div><div class='add'>+	hsi2c28_bus: hsi2c28-bus-pins {</div><div class='add'>+		samsung,pins = "gpp8-0", "gpp8-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* I2C PERIC1 USI14_I2C */</div><div class='add'>+	hsi2c29_bus: hsi2c29-bus-pins {</div><div class='add'>+		samsung,pins = "gpp8-2", "gpp8-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* I2C PERIC1 USI15 */</div><div class='add'>+	hsi2c30_bus: hsi2c30-bus-pins {</div><div class='add'>+		samsung,pins = "gpp11-0", "gpp11-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* I2C PERIC1 USI15_I2C */</div><div class='add'>+	hsi2c31_bus: hsi2c31-bus-pins {</div><div class='add'>+		samsung,pins = "gpp11-2", "gpp11-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* I2C PERIC1 USI16 */</div><div class='add'>+	hsi2c32_bus: hsi2c32-bus-pins {</div><div class='add'>+		samsung,pins = "gpp9-0", "gpp9-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* I2C PERIC1 USI16_I2C */</div><div class='add'>+	hsi2c33_bus: hsi2c33-bus-pins {</div><div class='add'>+		samsung,pins = "gpp9-2", "gpp9-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* I2C PERIC1 USI17 */</div><div class='add'>+	hsi2c34_bus: hsi2c34-bus-pins {</div><div class='add'>+		samsung,pins = "gpp12-0", "gpp12-1";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* I2C PERIC1 USI17_I2C */</div><div class='add'>+	hsi2c35_bus: hsi2c35-bus-pins {</div><div class='add'>+		samsung,pins = "gpp12-2", "gpp12-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SPI PERIC1 USI09 */</div><div class='add'>+	spi9_bus: spi9-bus-pins {</div><div class='add'>+		samsung,pins = "gpp5-0", "gpp5-1", "gpp5-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi9_cs: spi9-cs-pins {</div><div class='add'>+		samsung,pins = "gpp5-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi9_cs_func: spi9-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp5-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SPI PERIC1 USI10 */</div><div class='add'>+	spi10_bus: spi10-bus-pins {</div><div class='add'>+		samsung,pins = "gpp5-4", "gpp5-5", "gpp5-6";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi10_cs: spi10-cs-pins {</div><div class='add'>+		samsung,pins = "gpp5-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi10_cs_func: spi10-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp5-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SPI PERIC1 USI11 */</div><div class='add'>+	spi11_bus: spi11-bus-pins {</div><div class='add'>+		samsung,pins = "gpp10-0", "gpp10-1", "gpp10-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi11_cs: spi11-cs-pins {</div><div class='add'>+		samsung,pins = "gpp10-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi11_cs_func: spi11-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp10-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SPI PERIC1 USI12 */</div><div class='add'>+	spi12_bus: spi12-bus-pins {</div><div class='add'>+		samsung,pins = "gpp7-0", "gpp7-1", "gpp7-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi12_cs: spi12-cs-pins {</div><div class='add'>+		samsung,pins = "gpp7-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi12_cs_func: spi12-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp7-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SPI PERIC1 USI13 */</div><div class='add'>+	spi13_bus: spi13-bus-pins {</div><div class='add'>+		samsung,pins = "gpp7-4", "gpp7-5", "gpp7-6";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi13_cs: spi13-cs-pins {</div><div class='add'>+		samsung,pins = "gpp7-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi13_cs_func: spi13-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp7-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SPI PERIC1 USI14 */</div><div class='add'>+	spi14_bus: spi14-bus-pins {</div><div class='add'>+		samsung,pins = "gpp8-0", "gpp8-1", "gpp8-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi14_cs: spi14-cs-pins {</div><div class='add'>+		samsung,pins = "gpp8-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi14_cs_func: spi14-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp8-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SPI PERIC1 USI15 */</div><div class='add'>+	spi15_bus: spi15-bus-pins {</div><div class='add'>+		samsung,pins = "gpp11-0", "gpp11-1", "gpp11-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi15_cs: spi15-cs-pins {</div><div class='add'>+		samsung,pins = "gpp11-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi15_cs_func: spi15-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp11-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SPI PERIC1 USI16 */</div><div class='add'>+	spi16_bus: spi16-bus-pins {</div><div class='add'>+		samsung,pins = "gpp9-0", "gpp9-1", "gpp9-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi16_cs: spi16-cs-pins {</div><div class='add'>+		samsung,pins = "gpp9-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi16_cs_func: spi16-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp9-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SPI PERIC1 USI17 */</div><div class='add'>+	spi17_bus: spi17-bus-pins {</div><div class='add'>+		samsung,pins = "gpp12-0", "gpp12-1", "gpp12-2";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi17_cs: spi17-cs-pins {</div><div class='add'>+		samsung,pins = "gpp12-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi17_cs_func: spi17-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp12-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* I3C PERIC1 */</div><div class='add'>+	i3c4_bus: i3c4-bus-pins {</div><div class='add'>+		samsung,pins = "gpp7-2", "gpp7-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_4&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i3c5_bus: i3c5-bus-pins {</div><div class='add'>+		samsung,pins = "gpp7-6", "gpp7-7";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_4&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i3c6_bus: i3c6-bus-pins {</div><div class='add'>+		samsung,pins = "gpp8-2", "gpp8-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_4&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i3c7_bus: i3c7-bus-pins {</div><div class='add'>+		samsung,pins = "gpp11-2", "gpp11-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_4&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;EXYNOS_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts b/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts<br/>new file mode 100644<br/>index 000000000000..a397f068ed53<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts</a></div><div class='hunk'>@@ -0,0 +1,88 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Samsung's ExynosAutov920 SADK board device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2023 Samsung Electronics Co., Ltd.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "exynosautov920.dtsi"</div><div class='add'>+#include "exynos-pinctrl.h"</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Samsung ExynosAutov920 SADK board";</div><div class='add'>+	compatible = "samsung,exynosautov920-sadk", "samsung,exynosautov920";</div><div class='add'>+</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;serial_0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;serial_0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;key_wakeup &amp;key_back&gt;;</div><div class='add'>+</div><div class='add'>+		key-wakeup {</div><div class='add'>+			label = "KEY_WAKEUP";</div><div class='add'>+			linux,code = &lt;KEY_WAKEUP&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpa0 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-back {</div><div class='add'>+			label = "KEY_BACK";</div><div class='add'>+			linux,code = &lt;KEY_BACK&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpp6 3 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@80000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x80000000 0x0 0x70000000&gt;,</div><div class='add'>+		      &lt;0x8 0x80000000 0x1 0xfba00000&gt;,</div><div class='add'>+		      &lt;0xa 0x00000000 0x2 0x00000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_alive {</div><div class='add'>+	key_wakeup: key-wakeup-pins {</div><div class='add'>+		samsung,pins = "gpa0-0";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_peric1 {</div><div class='add'>+	key_back: key-back-pins {</div><div class='add'>+		samsung,pins = "gpp6-3";</div><div class='add'>+		samsung,pin-function = &lt;EXYNOS_PIN_FUNC_EINT&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm_tout0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;serial_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usi_0 {</div><div class='add'>+	samsung,clkreq-on; /* needed for UART mode */</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xtcxo {</div><div class='add'>+	clock-frequency = &lt;38400000&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi<br/>new file mode 100644<br/>index 000000000000..6ee74d260776<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/exynosautov920.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/exynosautov920.dtsi</a></div><div class='hunk'>@@ -0,0 +1,1535 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Samsung's ExynosAutov920 SoC device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2023 Samsung Electronics Co., Ltd.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/samsung,exynosautov920.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/soc/samsung,exynos-usi.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "samsung,exynosautov920";</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		pinctrl0 = &amp;pinctrl_alive;</div><div class='add'>+		pinctrl1 = &amp;pinctrl_aud;</div><div class='add'>+		pinctrl2 = &amp;pinctrl_hsi0;</div><div class='add'>+		pinctrl3 = &amp;pinctrl_hsi1;</div><div class='add'>+		pinctrl4 = &amp;pinctrl_hsi2;</div><div class='add'>+		pinctrl5 = &amp;pinctrl_hsi2ufs;</div><div class='add'>+		pinctrl6 = &amp;pinctrl_peric0;</div><div class='add'>+		pinctrl7 = &amp;pinctrl_peric1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	arm-pmu {</div><div class='add'>+		compatible = "arm,cortex-a78-pmu";</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	xtcxo: clock {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-output-names = "oscclk";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus: cpus {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu-map {</div><div class='add'>+			cluster0 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu0&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu1&gt;;</div><div class='add'>+				};</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu2&gt;;</div><div class='add'>+				};</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu3&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cluster1 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu4&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu5&gt;;</div><div class='add'>+				};</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu6&gt;;</div><div class='add'>+				};</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu7&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cluster2 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu8&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu9&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a78ae";</div><div class='add'>+			reg = &lt;0x0 0x0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			i-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_cl0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@100 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a78ae";</div><div class='add'>+			reg = &lt;0x0 0x100&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			i-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_cl0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@200 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a78ae";</div><div class='add'>+			reg = &lt;0x0 0x200&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			i-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_cl0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@300 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a78ae";</div><div class='add'>+			reg = &lt;0x0 0x300&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			i-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_cl0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu4: cpu@10000 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a78ae";</div><div class='add'>+			reg = &lt;0x0 0x10000&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			i-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_cl1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu5: cpu@10100 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a78ae";</div><div class='add'>+			reg = &lt;0x0 0x10100&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			i-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_cl1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu6: cpu@10200 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a78ae";</div><div class='add'>+			reg = &lt;0x0 0x10200&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			i-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_cl1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu7: cpu@10300 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a78ae";</div><div class='add'>+			reg = &lt;0x0 0x10300&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			i-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_cl1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu8: cpu@20000 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a78ae";</div><div class='add'>+			reg = &lt;0x0 0x20000&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			i-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_cl2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu9: cpu@20100 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a78ae";</div><div class='add'>+			reg = &lt;0x0 0x20100&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			i-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x10000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_cl2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_cache_cl0: l2-cache0 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x40000&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;512&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l3_cache_cl0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_cache_cl1: l2-cache1 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x40000&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;512&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l3_cache_cl1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_cache_cl2: l2-cache2 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x40000&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;512&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l3_cache_cl2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l3_cache_cl0: l3-cache0 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;3&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x200000&gt;;/* 2MB L3 cache for cpu cluster-0 */</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;2048&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l3_cache_cl1: l3-cache1 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;3&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x200000&gt;;/* 2MB L3 cache for cpu cluster-1 */</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;2048&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l3_cache_cl2: l3-cache2 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;3&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x100000&gt;;/* 1MB L3 cache for cpu cluster-2 */</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;1365&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-1.0";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc: soc@0 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges = &lt;0x0 0x0 0x0 0x20000000&gt;;</div><div class='add'>+</div><div class='add'>+		chipid@10000000 {</div><div class='add'>+			compatible = "samsung,exynosautov920-chipid",</div><div class='add'>+				     "samsung,exynos850-chipid";</div><div class='add'>+			reg = &lt;0x10000000 0x24&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_misc: clock-controller@10020000 {</div><div class='add'>+			compatible = "samsung,exynosautov920-cmu-misc";</div><div class='add'>+			reg = &lt;0x10020000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;xtcxo&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top DOUT_CLKCMU_MISC_NOC&gt;;</div><div class='add'>+			clock-names = "oscclk",</div><div class='add'>+				      "noc";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		watchdog_cl0: watchdog@10060000 {</div><div class='add'>+			compatible = "samsung,exynosautov920-wdt";</div><div class='add'>+			reg = &lt;0x10060000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;xtcxo&gt;, &lt;&amp;xtcxo&gt;;</div><div class='add'>+			clock-names = "watchdog", "watchdog_src";</div><div class='add'>+			samsung,syscon-phandle = &lt;&amp;pmu_system_controller&gt;;</div><div class='add'>+			samsung,cluster-index = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		watchdog_cl1: watchdog@10070000 {</div><div class='add'>+			compatible = "samsung,exynosautov920-wdt";</div><div class='add'>+			reg = &lt;0x10070000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;xtcxo&gt;, &lt;&amp;xtcxo&gt;;</div><div class='add'>+			clock-names = "watchdog", "watchdog_src";</div><div class='add'>+			samsung,syscon-phandle = &lt;&amp;pmu_system_controller&gt;;</div><div class='add'>+			samsung,cluster-index = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@10400000 {</div><div class='add'>+			compatible = "arm,gic-v3";</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			#address-cells = &lt;0&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			reg = &lt;0x10400000 0x10000&gt;,</div><div class='add'>+			      &lt;0x10460000 0x140000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spdma0: dma-controller@10180000 {</div><div class='add'>+			compatible = "arm,pl330", "arm,primecell";</div><div class='add'>+			reg = &lt;0x10180000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 918 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_misc CLK_MOUT_MISC_NOC_USER&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spdma1: dma-controller@10190000 {</div><div class='add'>+			compatible = "arm,pl330", "arm,primecell";</div><div class='add'>+			reg = &lt;0x10190000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 917 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_misc CLK_MOUT_MISC_NOC_USER&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pdma0: dma-controller@101a0000 {</div><div class='add'>+			compatible = "arm,pl330", "arm,primecell";</div><div class='add'>+			reg = &lt;0x101a0000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 916 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_misc CLK_MOUT_MISC_NOC_USER&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pdma1: dma-controller@101b0000 {</div><div class='add'>+			compatible = "arm,pl330", "arm,primecell";</div><div class='add'>+			reg = &lt;0x101b0000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 915 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_misc CLK_MOUT_MISC_NOC_USER&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pdma2: dma-controller@101c0000 {</div><div class='add'>+			compatible = "arm,pl330", "arm,primecell";</div><div class='add'>+			reg = &lt;0x101c0000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 914 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_misc CLK_MOUT_MISC_NOC_USER&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pdma3: dma-controller@101d0000 {</div><div class='add'>+			compatible = "arm,pl330", "arm,primecell";</div><div class='add'>+			reg = &lt;0x101d0000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 913 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_misc CLK_MOUT_MISC_NOC_USER&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pdma4: dma-controller@101e0000 {</div><div class='add'>+			compatible = "arm,pl330", "arm,primecell";</div><div class='add'>+			reg = &lt;0x101e0000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_misc CLK_MOUT_MISC_NOC_USER&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_peric0: clock-controller@10800000 {</div><div class='add'>+			compatible = "samsung,exynosautov920-cmu-peric0";</div><div class='add'>+			reg = &lt;0x10800000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;xtcxo&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top DOUT_CLKCMU_PERIC0_NOC&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top DOUT_CLKCMU_PERIC0_IP&gt;;</div><div class='add'>+			clock-names = "oscclk",</div><div class='add'>+				      "noc",</div><div class='add'>+				      "ip";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		syscon_peric0: syscon@10820000 {</div><div class='add'>+			compatible = "samsung,exynosautov920-peric0-sysreg",</div><div class='add'>+				     "syscon";</div><div class='add'>+			reg = &lt;0x10820000 0x2000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_peric0: pinctrl@10830000 {</div><div class='add'>+			compatible = "samsung,exynosautov920-pinctrl";</div><div class='add'>+			reg = &lt;0x10830000 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_0: usi@108800c0 {</div><div class='add'>+			compatible = "samsung,exynosautov920-usi",</div><div class='add'>+				     "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x108800c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric0 0x1000&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_MODE_UART&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric0 CLK_MOUT_PERIC0_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric0 CLK_DOUT_PERIC0_USI00_USI&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			serial_0: serial@10880000 {</div><div class='add'>+				compatible = "samsung,exynosautov920-uart",</div><div class='add'>+					     "samsung,exynos850-uart";</div><div class='add'>+				reg = &lt;0x10880000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart0_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_MOUT_PERIC0_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_DOUT_PERIC0_USI00_USI&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				samsung,uart-fifosize = &lt;256&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_0: spi@10880000 {</div><div class='add'>+				compatible = "samsung,exynosautov920-spi",</div><div class='add'>+					     "samsung,exynos850-spi";</div><div class='add'>+				reg = &lt;0x10880000 0x30&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi0_bus &amp;spi0_cs_func&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_MOUT_PERIC0_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_DOUT_PERIC0_USI00_USI&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				samsung,spi-src-clk = &lt;0&gt;;</div><div class='add'>+				dmas = &lt;&amp;pdma0 1&gt;, &lt;&amp;pdma0 0&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				num-cs = &lt;1&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				fifo-depth = &lt;256&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_1: usi@108a00c0 {</div><div class='add'>+			compatible = "samsung,exynosautov920-usi",</div><div class='add'>+				     "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x108a00c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric0 0x1008&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_V2_UART&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric0 CLK_MOUT_PERIC0_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric0 CLK_DOUT_PERIC0_USI01_USI&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			serial_1: serial@108a0000 {</div><div class='add'>+				compatible = "samsung,exynosautov920-uart",</div><div class='add'>+					     "samsung,exynos850-uart";</div><div class='add'>+				reg = &lt;0x108a0000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart1_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_MOUT_PERIC0_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_DOUT_PERIC0_USI01_USI&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				samsung,uart-fifosize = &lt;256&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_1: spi@108a0000 {</div><div class='add'>+				compatible = "samsung,exynosautov920-spi",</div><div class='add'>+					     "samsung,exynos850-spi";</div><div class='add'>+				reg = &lt;0x108a0000 0x30&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi1_bus &amp;spi1_cs_func&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_MOUT_PERIC0_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_DOUT_PERIC0_USI01_USI&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				samsung,spi-src-clk = &lt;0&gt;;</div><div class='add'>+				dmas = &lt;&amp;pdma0 3&gt;, &lt;&amp;pdma0 2&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				num-cs = &lt;1&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				fifo-depth = &lt;256&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_2: usi@108c00c0 {</div><div class='add'>+			compatible = "samsung,exynosautov920-usi",</div><div class='add'>+				     "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x108c00c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric0 0x1010&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_V2_UART&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric0 CLK_MOUT_PERIC0_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric0 CLK_DOUT_PERIC0_USI02_USI&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			serial_2: serial@108c0000 {</div><div class='add'>+				compatible = "samsung,exynosautov920-uart",</div><div class='add'>+					     "samsung,exynos850-uart";</div><div class='add'>+				reg = &lt;0x108c0000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart2_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_MOUT_PERIC0_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_DOUT_PERIC0_USI02_USI&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_2: spi@108c0000 {</div><div class='add'>+				compatible = "samsung,exynosautov920-spi",</div><div class='add'>+					     "samsung,exynos850-spi";</div><div class='add'>+				reg = &lt;0x108c0000 0x30&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi2_bus &amp;spi2_cs_func&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_MOUT_PERIC0_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_DOUT_PERIC0_USI02_USI&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				samsung,spi-src-clk = &lt;0&gt;;</div><div class='add'>+				dmas = &lt;&amp;pdma0 5&gt;, &lt;&amp;pdma0 4&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				num-cs = &lt;1&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				fifo-depth = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_3: usi@108e00c0 {</div><div class='add'>+			compatible = "samsung,exynosautov920-usi",</div><div class='add'>+				     "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x108e00c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric0 0x1018&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_V2_UART&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric0 CLK_MOUT_PERIC0_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric0 CLK_DOUT_PERIC0_USI03_USI&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			serial_3: serial@108e0000 {</div><div class='add'>+				compatible = "samsung,exynosautov920-uart",</div><div class='add'>+					     "samsung,exynos850-uart";</div><div class='add'>+				reg = &lt;0x108e0000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart3_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_MOUT_PERIC0_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_DOUT_PERIC0_USI03_USI&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_3: spi@108e0000 {</div><div class='add'>+				compatible = "samsung,exynosautov920-spi",</div><div class='add'>+					     "samsung,exynos850-spi";</div><div class='add'>+				reg = &lt;0x108e0000 0x30&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi3_bus &amp;spi3_cs_func&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_MOUT_PERIC0_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_DOUT_PERIC0_USI03_USI&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				samsung,spi-src-clk = &lt;0&gt;;</div><div class='add'>+				dmas = &lt;&amp;pdma0 7&gt;, &lt;&amp;pdma0 6&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				num-cs = &lt;1&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				fifo-depth = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_4: usi@109000c0 {</div><div class='add'>+			compatible = "samsung,exynosautov920-usi",</div><div class='add'>+				     "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x109000c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric0 0x1020&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_V2_UART&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric0 CLK_MOUT_PERIC0_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric0 CLK_DOUT_PERIC0_USI04_USI&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			serial_4: serial@10900000 {</div><div class='add'>+				compatible = "samsung,exynosautov920-uart",</div><div class='add'>+					     "samsung,exynos850-uart";</div><div class='add'>+				reg = &lt;0x10900000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart4_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_MOUT_PERIC0_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_DOUT_PERIC0_USI04_USI&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_4: spi@10900000 {</div><div class='add'>+				compatible = "samsung,exynosautov920-spi",</div><div class='add'>+					     "samsung,exynos850-spi";</div><div class='add'>+				reg = &lt;0x10900000 0x30&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi4_bus &amp;spi4_cs_func&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_MOUT_PERIC0_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_DOUT_PERIC0_USI04_USI&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				samsung,spi-src-clk = &lt;0&gt;;</div><div class='add'>+				dmas = &lt;&amp;pdma0 9&gt;, &lt;&amp;pdma0 8&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				num-cs = &lt;1&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				fifo-depth = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_5: usi@109200c0 {</div><div class='add'>+			compatible = "samsung,exynosautov920-usi",</div><div class='add'>+				     "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x109200c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric0 0x1028&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_V2_UART&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric0 CLK_MOUT_PERIC0_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric0 CLK_DOUT_PERIC0_USI05_USI&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			serial_5: serial@10920000 {</div><div class='add'>+				compatible = "samsung,exynosautov920-uart",</div><div class='add'>+					     "samsung,exynos850-uart";</div><div class='add'>+				reg = &lt;0x10920000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart5_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_MOUT_PERIC0_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_DOUT_PERIC0_USI05_USI&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_5: spi@10920000 {</div><div class='add'>+				compatible = "samsung,exynosautov920-spi",</div><div class='add'>+					     "samsung,exynos850-spi";</div><div class='add'>+				reg = &lt;0x10920000 0x30&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi5_bus &amp;spi5_cs_func&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_MOUT_PERIC0_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_DOUT_PERIC0_USI05_USI&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				samsung,spi-src-clk = &lt;0&gt;;</div><div class='add'>+				dmas = &lt;&amp;pdma0 11&gt;, &lt;&amp;pdma0 10&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				num-cs = &lt;1&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				fifo-depth = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_6: usi@109400c0 {</div><div class='add'>+			compatible = "samsung,exynosautov920-usi",</div><div class='add'>+				     "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x109400c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric0 0x1030&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_V2_UART&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric0 CLK_MOUT_PERIC0_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric0 CLK_DOUT_PERIC0_USI06_USI&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			serial_6: serial@10940000 {</div><div class='add'>+				compatible = "samsung,exynosautov920-uart",</div><div class='add'>+					     "samsung,exynos850-uart";</div><div class='add'>+				reg = &lt;0x10940000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 776 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart6_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_MOUT_PERIC0_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_DOUT_PERIC0_USI06_USI&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_6: spi@10940000 {</div><div class='add'>+				compatible = "samsung,exynosautov920-spi",</div><div class='add'>+					     "samsung,exynos850-spi";</div><div class='add'>+				reg = &lt;0x10940000 0x30&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 776 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi6_bus &amp;spi6_cs_func&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_MOUT_PERIC0_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_DOUT_PERIC0_USI06_USI&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				samsung,spi-src-clk = &lt;0&gt;;</div><div class='add'>+				dmas = &lt;&amp;pdma0 13&gt;, &lt;&amp;pdma0 12&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				num-cs = &lt;1&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				fifo-depth = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_7: usi@109600c0 {</div><div class='add'>+			compatible = "samsung,exynosautov920-usi",</div><div class='add'>+				     "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x109600c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric0 0x1038&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_V2_UART&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric0 CLK_MOUT_PERIC0_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric0 CLK_DOUT_PERIC0_USI07_USI&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			serial_7: serial@10960000 {</div><div class='add'>+				compatible = "samsung,exynosautov920-uart",</div><div class='add'>+					     "samsung,exynos850-uart";</div><div class='add'>+				reg = &lt;0x10960000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 778 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart7_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_MOUT_PERIC0_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_DOUT_PERIC0_USI07_USI&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_7: spi@10960000 {</div><div class='add'>+				compatible = "samsung,exynosautov920-spi",</div><div class='add'>+					     "samsung,exynos850-spi";</div><div class='add'>+				reg = &lt;0x10960000 0x30&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 778 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi7_bus &amp;spi7_cs_func&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_MOUT_PERIC0_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_DOUT_PERIC0_USI07_USI&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				samsung,spi-src-clk = &lt;0&gt;;</div><div class='add'>+				dmas = &lt;&amp;pdma0 15&gt;, &lt;&amp;pdma0 14&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				num-cs = &lt;1&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				fifo-depth = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_8: usi@109800c0 {</div><div class='add'>+			compatible = "samsung,exynosautov920-usi",</div><div class='add'>+				     "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x109800c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric0 0x1040&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_V2_UART&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric0 CLK_MOUT_PERIC0_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric0 CLK_DOUT_PERIC0_USI08_USI&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			serial_8: serial@10980000 {</div><div class='add'>+				compatible = "samsung,exynosautov920-uart",</div><div class='add'>+					     "samsung,exynos850-uart";</div><div class='add'>+				reg = &lt;0x10980000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart8_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_MOUT_PERIC0_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_DOUT_PERIC0_USI08_USI&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_8: spi@10980000 {</div><div class='add'>+				compatible = "samsung,exynosautov920-spi",</div><div class='add'>+					     "samsung,exynos850-spi";</div><div class='add'>+				reg = &lt;0x10980000 0x30&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi8_bus &amp;spi8_cs_func&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_MOUT_PERIC0_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_DOUT_PERIC0_USI08_USI&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				samsung,spi-src-clk = &lt;0&gt;;</div><div class='add'>+				dmas = &lt;&amp;pdma0 17&gt;, &lt;&amp;pdma0 16&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				num-cs = &lt;1&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				fifo-depth = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pwm: pwm@109b0000 {</div><div class='add'>+			compatible = "samsung,exynosautov920-pwm",</div><div class='add'>+				     "samsung,exynos4210-pwm";</div><div class='add'>+			reg = &lt;0x109b0000 0x100&gt;;</div><div class='add'>+			samsung,pwm-outputs = &lt;0&gt;, &lt;1&gt;, &lt;2&gt;, &lt;3&gt;;</div><div class='add'>+			#pwm-cells = &lt;3&gt;;</div><div class='add'>+			clocks = &lt;&amp;xtcxo&gt;;</div><div class='add'>+			clock-names = "timers";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_peric1: clock-controller@10c00000 {</div><div class='add'>+			compatible = "samsung,exynosautov920-cmu-peric1";</div><div class='add'>+			reg = &lt;0x10c00000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;xtcxo&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top DOUT_CLKCMU_PERIC1_NOC&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top DOUT_CLKCMU_PERIC1_IP&gt;;</div><div class='add'>+			clock-names = "oscclk",</div><div class='add'>+				      "noc",</div><div class='add'>+				      "ip";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		syscon_peric1: syscon@10c20000 {</div><div class='add'>+			compatible = "samsung,exynosautov920-peric1-sysreg",</div><div class='add'>+				     "syscon";</div><div class='add'>+			reg = &lt;0x10c20000 0x2000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_peric1: pinctrl@10c30000 {</div><div class='add'>+			compatible = "samsung,exynosautov920-pinctrl";</div><div class='add'>+			reg = &lt;0x10c30000 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_9: usi@10c800c0 {</div><div class='add'>+			compatible = "samsung,exynosautov920-usi",</div><div class='add'>+				     "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x10c800c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric1 0x1000&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_V2_UART&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_MOUT_PERIC1_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI09_USI&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			serial_9: serial@10c8000 {</div><div class='add'>+				compatible = "samsung,exynosautov920-uart",</div><div class='add'>+					     "samsung,exynos850-uart";</div><div class='add'>+				reg = &lt;0x10c80000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart9_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_MOUT_PERIC1_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI09_USI&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				samsung,uart-fifosize = &lt;256&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_9: spi@10c80000 {</div><div class='add'>+				compatible = "samsung,exynosautov920-spi",</div><div class='add'>+					     "samsung,exynos850-spi";</div><div class='add'>+				reg = &lt;0x10c80000 0x30&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi9_bus &amp;spi9_cs_func&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_MOUT_PERIC1_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI09_USI&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				samsung,spi-src-clk = &lt;0&gt;;</div><div class='add'>+				dmas = &lt;&amp;pdma1 1&gt;, &lt;&amp;pdma1 0&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				num-cs = &lt;1&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				fifo-depth = &lt;256&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_10: usi@10ca00c0 {</div><div class='add'>+			compatible = "samsung,exynosautov920-usi",</div><div class='add'>+				     "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x10ca00c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric1 0x1008&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_V2_UART&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_MOUT_PERIC1_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI10_USI&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			serial_10: serial@10ca0000 {</div><div class='add'>+				compatible = "samsung,exynosautov920-uart",</div><div class='add'>+					     "samsung,exynos850-uart";</div><div class='add'>+				reg = &lt;0x10ca0000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart10_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_MOUT_PERIC1_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI10_USI&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_10: spi@10ca0000 {</div><div class='add'>+				compatible = "samsung,exynosautov920-spi",</div><div class='add'>+					     "samsung,exynos850-spi";</div><div class='add'>+				reg = &lt;0x10ca0000 0x30&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi10_bus &amp;spi10_cs_func&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_MOUT_PERIC1_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI10_USI&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				samsung,spi-src-clk = &lt;0&gt;;</div><div class='add'>+				dmas = &lt;&amp;pdma1 3&gt;, &lt;&amp;pdma1 2&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				num-cs = &lt;1&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				fifo-depth = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_11: usi@10cc00c0 {</div><div class='add'>+			compatible = "samsung,exynosautov920-usi",</div><div class='add'>+				     "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x10cc00c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric1 0x1010&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_V2_UART&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_MOUT_PERIC1_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI11_USI&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			serial_11: serial@10cc0000 {</div><div class='add'>+				compatible = "samsung,exynosautov920-uart",</div><div class='add'>+					     "samsung,exynos850-uart";</div><div class='add'>+				reg = &lt;0x10cc0000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart11_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_MOUT_PERIC1_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI11_USI&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_11: spi@10cc0000 {</div><div class='add'>+				compatible = "samsung,exynosautov920-spi",</div><div class='add'>+					     "samsung,exynos850-spi";</div><div class='add'>+				reg = &lt;0x10cc0000 0x30&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi11_bus &amp;spi11_cs_func&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_MOUT_PERIC1_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI11_USI&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				samsung,spi-src-clk = &lt;0&gt;;</div><div class='add'>+				dmas = &lt;&amp;pdma1 5&gt;, &lt;&amp;pdma1 4&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				num-cs = &lt;1&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				fifo-depth = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_12: usi@10ce00c0 {</div><div class='add'>+			compatible = "samsung,exynosautov920-usi",</div><div class='add'>+				     "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x10ce00c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric1 0x1018&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_V2_UART&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_MOUT_PERIC1_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI12_USI&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			serial_12: serial@10ce0000 {</div><div class='add'>+				compatible = "samsung,exynosautov920-uart",</div><div class='add'>+					     "samsung,exynos850-uart";</div><div class='add'>+				reg = &lt;0x10ce0000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart12_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_MOUT_PERIC1_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI12_USI&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_12: spi@10ce0000 {</div><div class='add'>+				compatible = "samsung,exynosautov920-spi",</div><div class='add'>+					     "samsung,exynos850-spi";</div><div class='add'>+				reg = &lt;0x10ce0000 0x30&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi12_bus &amp;spi12_cs_func&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_MOUT_PERIC1_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI12_USI&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				samsung,spi-src-clk = &lt;0&gt;;</div><div class='add'>+				dmas = &lt;&amp;pdma1 7&gt;, &lt;&amp;pdma1 6&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				num-cs = &lt;1&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				fifo-depth = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_13: usi@10d000c0 {</div><div class='add'>+			compatible = "samsung,exynosautov920-usi",</div><div class='add'>+				     "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x10d000c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric1 0x1020&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_V2_UART&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_MOUT_PERIC1_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI13_USI&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			serial_13: serial@10d00000 {</div><div class='add'>+				compatible = "samsung,exynosautov920-uart",</div><div class='add'>+					     "samsung,exynos850-uart";</div><div class='add'>+				reg = &lt;0x10d00000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart13_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_MOUT_PERIC1_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI13_USI&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_13: spi@10d00000 {</div><div class='add'>+				compatible = "samsung,exynosautov920-spi",</div><div class='add'>+					     "samsung,exynos850-spi";</div><div class='add'>+				reg = &lt;0x10d00000 0x30&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi13_bus &amp;spi13_cs_func&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_MOUT_PERIC1_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI13_USI&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				samsung,spi-src-clk = &lt;0&gt;;</div><div class='add'>+				dmas = &lt;&amp;pdma1 9&gt;, &lt;&amp;pdma1 8&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				num-cs = &lt;1&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				fifo-depth = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_14: usi@10d200c0 {</div><div class='add'>+			compatible = "samsung,exynosautov920-usi",</div><div class='add'>+				     "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x10d200c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric1 0x1028&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_V2_UART&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_MOUT_PERIC1_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI14_USI&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			serial_14: serial@10d20000 {</div><div class='add'>+				compatible = "samsung,exynosautov920-uart",</div><div class='add'>+					     "samsung,exynos850-uart";</div><div class='add'>+				reg = &lt;0x10d20000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart14_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_MOUT_PERIC1_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI14_USI&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_14: spi@10d20000 {</div><div class='add'>+				compatible = "samsung,exynosautov920-spi",</div><div class='add'>+					     "samsung,exynos850-spi";</div><div class='add'>+				reg = &lt;0x10d20000 0x30&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi14_bus &amp;spi14_cs_func&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_MOUT_PERIC1_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI14_USI&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				samsung,spi-src-clk = &lt;0&gt;;</div><div class='add'>+				dmas = &lt;&amp;pdma1 11&gt;, &lt;&amp;pdma1 10&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				num-cs = &lt;1&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				fifo-depth = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_15: usi@10d400c0 {</div><div class='add'>+			compatible = "samsung,exynosautov920-usi",</div><div class='add'>+				     "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x10d400c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric1 0x1030&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_V2_UART&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_MOUT_PERIC1_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI15_USI&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			serial_15: serial@10d40000 {</div><div class='add'>+				compatible = "samsung,exynosautov920-uart",</div><div class='add'>+					     "samsung,exynos850-uart";</div><div class='add'>+				reg = &lt;0x10d40000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart15_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_MOUT_PERIC1_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI15_USI&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_15: spi@10d40000 {</div><div class='add'>+				compatible = "samsung,exynosautov920-spi",</div><div class='add'>+					     "samsung,exynos850-spi";</div><div class='add'>+				reg = &lt;0x10d40000 0x30&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi15_bus &amp;spi15_cs_func&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_MOUT_PERIC1_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI15_USI&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				samsung,spi-src-clk = &lt;0&gt;;</div><div class='add'>+				dmas = &lt;&amp;pdma1 13&gt;, &lt;&amp;pdma1 12&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				num-cs = &lt;1&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				fifo-depth = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_16: usi@10d600c0 {</div><div class='add'>+			compatible = "samsung,exynosautov920-usi",</div><div class='add'>+				     "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x10d600c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric1 0x1038&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_V2_UART&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_MOUT_PERIC1_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI16_USI&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			serial_16: serial@10d60000 {</div><div class='add'>+				compatible = "samsung,exynosautov920-uart",</div><div class='add'>+					     "samsung,exynos850-uart";</div><div class='add'>+				reg = &lt;0x10d60000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart16_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_MOUT_PERIC1_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI16_USI&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_16: spi@10d60000 {</div><div class='add'>+				compatible = "samsung,exynosautov920-spi",</div><div class='add'>+					     "samsung,exynos850-spi";</div><div class='add'>+				reg = &lt;0x10d60000 0x30&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi16_bus &amp;spi16_cs_func&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_MOUT_PERIC1_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI16_USI&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				samsung,spi-src-clk = &lt;0&gt;;</div><div class='add'>+				dmas = &lt;&amp;pdma1 15&gt;, &lt;&amp;pdma1 14&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				num-cs = &lt;1&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				fifo-depth = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_17: usi@10d800c0 {</div><div class='add'>+			compatible = "samsung,exynosautov920-usi",</div><div class='add'>+				     "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x10d800c0 0x20&gt;;</div><div class='add'>+			samsung,sysreg = &lt;&amp;syscon_peric1 0x1040&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_V2_UART&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_MOUT_PERIC1_NOC_USER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI17_USI&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			serial_17: serial@10d80000 {</div><div class='add'>+				compatible = "samsung,exynosautov920-uart",</div><div class='add'>+					     "samsung,exynos850-uart";</div><div class='add'>+				reg = &lt;0x10d80000 0xc0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart17_bus&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_MOUT_PERIC1_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI17_USI&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_17: spi@10d80000 {</div><div class='add'>+				compatible = "samsung,exynosautov920-spi",</div><div class='add'>+					     "samsung,exynos850-spi";</div><div class='add'>+				reg = &lt;0x10d80000 0x30&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi17_bus &amp;spi17_cs_func&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_MOUT_PERIC1_NOC_USER&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_DOUT_PERIC1_USI17_USI&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				samsung,spi-src-clk = &lt;0&gt;;</div><div class='add'>+				dmas = &lt;&amp;pdma1 17&gt;, &lt;&amp;pdma1 16&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				num-cs = &lt;1&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				fifo-depth = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_top: clock-controller@11000000 {</div><div class='add'>+			compatible = "samsung,exynosautov920-cmu-top";</div><div class='add'>+			reg = &lt;0x11000000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;xtcxo&gt;;</div><div class='add'>+			clock-names = "oscclk";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_alive: pinctrl@11850000 {</div><div class='add'>+			compatible = "samsung,exynosautov920-pinctrl";</div><div class='add'>+			reg = &lt;0x11850000 0x10000&gt;;</div><div class='add'>+</div><div class='add'>+			wakeup-interrupt-controller {</div><div class='add'>+				compatible = "samsung,exynosautov920-wakeup-eint";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmu_system_controller: system-controller@11860000 {</div><div class='add'>+			compatible = "samsung,exynosautov920-pmu",</div><div class='add'>+				     "samsung,exynos7-pmu","syscon";</div><div class='add'>+			reg = &lt;0x11860000 0x10000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_hsi0: clock-controller@16000000 {</div><div class='add'>+			compatible = "samsung,exynosautov920-cmu-hsi0";</div><div class='add'>+			reg = &lt;0x16000000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;xtcxo&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top DOUT_CLKCMU_HSI0_NOC&gt;;</div><div class='add'>+			clock-names = "oscclk",</div><div class='add'>+				      "noc";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_hsi0: pinctrl@16040000 {</div><div class='add'>+			compatible = "samsung,exynosautov920-pinctrl";</div><div class='add'>+			reg = &lt;0x16040000 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_hsi1: clock-controller@16400000 {</div><div class='add'>+			compatible = "samsung,exynosautov920-cmu-hsi1";</div><div class='add'>+			reg = &lt;0x16400000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;xtcxo&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top DOUT_CLKCMU_HSI1_NOC&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top DOUT_CLKCMU_HSI1_USBDRD&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top DOUT_CLKCMU_HSI1_MMC_CARD&gt;;</div><div class='add'>+			clock-names = "oscclk",</div><div class='add'>+				      "noc",</div><div class='add'>+				      "usbdrd",</div><div class='add'>+				      "mmc_card";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_hsi1: pinctrl@16450000 {</div><div class='add'>+			compatible = "samsung,exynosautov920-pinctrl";</div><div class='add'>+			reg = &lt;0x16450000 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_hsi2: clock-controller@16b00000 {</div><div class='add'>+			compatible = "samsung,exynosautov920-cmu-hsi2";</div><div class='add'>+			reg = &lt;0x16b00000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;xtcxo&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top DOUT_CLKCMU_HSI2_NOC&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top DOUT_CLKCMU_HSI2_NOC_UFS&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top DOUT_CLKCMU_HSI2_UFS_EMBD&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top DOUT_CLKCMU_HSI2_ETHERNET&gt;;</div><div class='add'>+			clock-names = "oscclk",</div><div class='add'>+				      "noc",</div><div class='add'>+				      "ufs",</div><div class='add'>+				      "embd",</div><div class='add'>+				      "ethernet";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_hsi2: pinctrl@16c10000 {</div><div class='add'>+			compatible = "samsung,exynosautov920-pinctrl";</div><div class='add'>+			reg = &lt;0x16c10000 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_hsi2ufs: pinctrl@16d20000 {</div><div class='add'>+			compatible = "samsung,exynosautov920-pinctrl";</div><div class='add'>+			reg = &lt;0x16d20000 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ufs_0_phy: phy@16e04000 {</div><div class='add'>+			compatible = "samsung,exynosautov920-ufs-phy";</div><div class='add'>+			reg = &lt;0x16e04000 0x4000&gt;;</div><div class='add'>+			reg-names = "phy-pma";</div><div class='add'>+			clocks = &lt;&amp;xtcxo&gt;;</div><div class='add'>+			clock-names = "ref_clk";</div><div class='add'>+			samsung,pmu-syscon = &lt;&amp;pmu_system_controller&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_mfc: clock-controller@19c00000 {</div><div class='add'>+			compatible = "samsung,exynosautov920-cmu-mfc";</div><div class='add'>+			reg = &lt;0x19c00000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;xtcxo&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top DOUT_CLKCMU_MFC_MFC&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top DOUT_CLKCMU_MFC_WFD&gt;;</div><div class='add'>+			clock-names = "oscclk",</div><div class='add'>+				      "mfc",</div><div class='add'>+				      "wfd";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_aud: pinctrl@1a460000 {</div><div class='add'>+			compatible = "samsung,exynosautov920-pinctrl";</div><div class='add'>+			reg = &lt;0x1a460000 0x10000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_m2m: clock-controller@1a800000 {</div><div class='add'>+			compatible = "samsung,exynosautov920-cmu-m2m";</div><div class='add'>+			reg = &lt;0x1a800000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;xtcxo&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top DOUT_CLKCMU_M2M_NOC&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top DOUT_CLKCMU_M2M_JPEG&gt;;</div><div class='add'>+			clock-names = "oscclk",</div><div class='add'>+				      "noc",</div><div class='add'>+				      "jpeg";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_cpucl0: clock-controller@1ec00000 {</div><div class='add'>+			compatible = "samsung,exynosautov920-cmu-cpucl0";</div><div class='add'>+			reg = &lt;0x1ec00000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;xtcxo&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top DOUT_CLKCMU_CPUCL0_SWITCH&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top DOUT_CLKCMU_CPUCL0_CLUSTER&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top DOUT_CLKCMU_CPUCL0_DBG&gt;;</div><div class='add'>+			clock-names = "oscclk",</div><div class='add'>+				      "switch",</div><div class='add'>+				      "cluster",</div><div class='add'>+				      "dbg";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_cpucl1: clock-controller@1ed00000 {</div><div class='add'>+			compatible = "samsung,exynosautov920-cmu-cpucl1";</div><div class='add'>+			reg = &lt;0x1ed00000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;xtcxo&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top DOUT_CLKCMU_CPUCL1_SWITCH&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top DOUT_CLKCMU_CPUCL1_CLUSTER&gt;;</div><div class='add'>+			clock-names = "oscclk",</div><div class='add'>+				      "switch",</div><div class='add'>+				      "cluster";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_cpucl2: clock-controller@1ee00000 {</div><div class='add'>+			compatible = "samsung,exynosautov920-cmu-cpucl2";</div><div class='add'>+			reg = &lt;0x1ee00000 0x8000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;xtcxo&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top DOUT_CLKCMU_CPUCL2_SWITCH&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top DOUT_CLKCMU_CPUCL2_CLUSTER&gt;;</div><div class='add'>+			clock-names = "oscclk",</div><div class='add'>+				      "switch",</div><div class='add'>+				      "cluster";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 12 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include "exynosautov920-pinctrl.dtsi"</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/google/Makefile b/arch/arm64/boot/dts/exynos/google/Makefile<br/>new file mode 100644<br/>index 000000000000..7385f82b03c9<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/google/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/google/Makefile</a></div><div class='hunk'>@@ -0,0 +1,5 @@</div><div class='add'>+# SPDX-License-Identifier: GPL-2.0</div><div class='add'>+</div><div class='add'>+dtb-$(CONFIG_ARCH_EXYNOS) += \</div><div class='add'>+	gs101-oriole.dtb \</div><div class='add'>+	gs101-raven.dtb</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts<br/>new file mode 100644<br/>index 000000000000..8df42bedbc03<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/google/gs101-oriole.dts</a></div><div class='hunk'>@@ -0,0 +1,29 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/*</div><div class='add'>+ * Oriole Device Tree</div><div class='add'>+ *</div><div class='add'>+ * Copyright 2021-2023 Google LLC</div><div class='add'>+ * Copyright 2023 Linaro Ltd - &lt;peter.griffin@linaro.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "gs101-pixel-common.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Oriole";</div><div class='add'>+	compatible = "google,gs101-oriole", "google,gs101";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cont_splash_mem {</div><div class='add'>+	reg = &lt;0x0 0xfac00000 (1080 * 2400 * 4)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;framebuffer0 {</div><div class='add'>+	width = &lt;1080&gt;;</div><div class='add'>+	height = &lt;2400&gt;;</div><div class='add'>+	stride = &lt;(1080 * 4)&gt;;</div><div class='add'>+	format = "a8r8g8b8";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/google/gs101-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/google/gs101-pinctrl.dtsi<br/>new file mode 100644<br/>index 000000000000..a675f822acec<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/google/gs101-pinctrl.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/google/gs101-pinctrl.dtsi</a></div><div class='hunk'>@@ -0,0 +1,1249 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/*</div><div class='add'>+ * GS101 SoC pin-mux and pin-config device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright 2019-2023 Google LLC</div><div class='add'>+ * Copyright 2023 Linaro Ltd - &lt;peter.griffin@linaro.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "gs101-pinctrl.h"</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_gpio_alive {</div><div class='add'>+	gpa0: gpa0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpa1: gpa1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpa2: gpa2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpa3: gpa3-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpa4: gpa4-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpa5: gpa5-gpio-bank  {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpa9: gpa9-gpio-bank  {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpa10: gpa10-gpio-bank  {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart15_bus: uart15-bus-pins {</div><div class='add'>+		samsung,pins = "gpa2-3", "gpa2-4";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart16_bus: uart16-bus-pins {</div><div class='add'>+		samsung,pins = "gpa3-0", "gpa3-1", "gpa3-2", "gpa3-3";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart17_bus: uart17-bus-pins {</div><div class='add'>+		samsung,pins = "gpa4-0", "gpa4-1", "gpa4-2", "gpa4-3";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi15_bus: spi15-bus-pins {</div><div class='add'>+		samsung,pins = "gpa4-0", "gpa4-1", "gpa4-2";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi15_cs: spi15-cs-pins {</div><div class='add'>+		samsung,pins = "gpa4-3";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_far_alive {</div><div class='add'>+	gpa6: gpa6-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpa7: gpa7-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpa8: gpa8-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpa11: gpa11-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_gsacore {</div><div class='add'>+	gps0: gps0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gps1: gps1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gps2: gps2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_gsactrl {</div><div class='add'>+	gps3: gps3-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_hsi1 {</div><div class='add'>+	gph0: gph0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gph1: gph1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_clkreq: pcie0-clkreq-pins {</div><div class='add'>+		samsung,pins = "gph0-1";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_10_MA&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;GS101_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;GS101_PIN_PULL_UP&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_perst: pcie0-perst-pins {</div><div class='add'>+		samsung,pins = "gph0-0";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_10_MA&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;GS101_PIN_PDN_PREV&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_hsi2 {</div><div class='add'>+	gph2: gph2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gph3: gph3-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gph4: gph4-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_clk: sd2-clk-pins {</div><div class='add'>+		samsung,pins = "gph4-0";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_7_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_cmd: sd2-cmd-pins {</div><div class='add'>+		samsung,pins = "gph4-1";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_7_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_bus1: sd2-bus-width1-pins {</div><div class='add'>+		samsung,pins = "gph4-2";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_7_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_bus4: sd2-bus-width4-pins {</div><div class='add'>+		samsung,pins = "gph4-3", "gph4-4", "gph4-5";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_7_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_clk_fast_slew_rate_1x: sd2-clk-fast-slew-rate-1x-pins {</div><div class='add'>+		samsung,pins = "gph4-0";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_clk_fast_slew_rate_2x: sd2-clk-fast-slew-rate-2x-pins {</div><div class='add'>+		samsung,pins = "gph4-0";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_clk_fast_slew_rate_3x: sd2-clk-fast-slew-rate-3x-pins {</div><div class='add'>+		samsung,pins = "gph4-0";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_7_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd2_clk_fast_slew_rate_4x: sd2-clk-fast-slew-rate-4x-pins {</div><div class='add'>+		samsung,pins = "gph4-0";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_10_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ufs_rst_n: ufs-rst-n-pins {</div><div class='add'>+		samsung,pins = "gph3-1";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;GS101_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ufs_refclk_out: ufs-refclk-out-pins {</div><div class='add'>+		samsung,pins = "gph3-0";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;GS101_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie1_clkreq: pcie1-clkreq-pins {</div><div class='add'>+		samsung,pins = "gph2-1";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_10_MA&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;GS101_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;GS101_PIN_PULL_UP&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie1_perst: pcie1-perst-pins {</div><div class='add'>+		samsung,pins = "gph2-0";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_10_MA&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;GS101_PIN_PDN_PREV&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_peric0 {</div><div class='add'>+	gpp0: gpp0-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp1: gpp1-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp2: gpp2-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp3: gpp3-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp4: gpp4-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp5: gpp5-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp6: gpp6-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp7: gpp7-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp8: gpp8-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp9: gpp9-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp10: gpp10-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp11: gpp11-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp12: gpp12-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp13: gpp13-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp14: gpp14-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp15: gpp15-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp16: gpp16-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp17: gpp17-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp18: gpp18-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp19: gpp19-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USI_PERIC0_UART_DBG */</div><div class='add'>+	uart0_bus: uart0-bus-pins {</div><div class='add'>+		samsung,pins = "gpp1-2", "gpp1-3";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	disp_te_pri_on: disp-te-pri-on-pins {</div><div class='add'>+		samsung,pins = "gpp0-3";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_EINT&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	disp_te_pri_off: disp-te-pri-off-pins {</div><div class='add'>+		samsung,pins = "gpp0-3";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_INPUT&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	disp_te_sec_on: disp-te-sec-on-pins {</div><div class='add'>+		samsung,pins = "gpp0-4";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_EINT&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	disp_te_sec_off: disp-te-sec-off-pins {</div><div class='add'>+		samsung,pins = "gpp0-4";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_INPUT&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sensor_mclk1_out: sensor-mclk1-out-pins {</div><div class='add'>+		samsung,pins = "gpp3-0";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_DOWN&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sensor_mclk1_fn: sensor-mclk1-fn-pins {</div><div class='add'>+		samsung,pins = "gpp3-0";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sensor_mclk2_out: sensor-mclk2-out-pins {</div><div class='add'>+		samsung,pins = "gpp5-0";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_DOWN&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sensor_mclk2_fn: sensor-mclk2-fn-pins {</div><div class='add'>+		samsung,pins = "gpp5-0";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sensor_mclk3_out: sensor-mclk3-out-pins {</div><div class='add'>+		samsung,pins = "gpp7-0";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_DOWN&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sensor_mclk3_fn: sensor-mclk3-fn-pins {</div><div class='add'>+		samsung,pins = "gpp7-0";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sensor_mclk4_out: sensor-mclk4-out-pins {</div><div class='add'>+		samsung,pins = "gpp9-0";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_DOWN&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sensor_mclk4_fn: sensor-mclk4-fn-pins {</div><div class='add'>+		samsung,pins = "gpp9-0";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sensor_mclk5_out: sensor-mclk5-out-pins {</div><div class='add'>+		samsung,pins = "gpp11-0";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_DOWN&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sensor_mclk5_fn: sensor-mclk5-fn-pins {</div><div class='add'>+		samsung,pins = "gpp11-0";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sensor_mclk6_out: sensor-mclk6-out-pins {</div><div class='add'>+		samsung,pins = "gpp13-0";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_DOWN&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sensor_mclk6_fn: sensor-mclk6-fn-pins {</div><div class='add'>+		samsung,pins = "gpp13-0";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sensor_mclk7_out: sensor-mclk7-out-pins {</div><div class='add'>+		samsung,pins = "gpp15-0";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_DOWN&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sensor_mclk7_fn: sensor-mclk7-fn-pins {</div><div class='add'>+		samsung,pins = "gpp15-0";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sensor_mclk8_out: sensor-mclk8-out-pins {</div><div class='add'>+		samsung,pins = "gpp17-0";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_DOWN&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sensor_mclk8_fn: sensor-mclk8-fn-pins {</div><div class='add'>+		samsung,pins = "gpp17-0";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c14_bus: hsi2c14-bus-pins {</div><div class='add'>+		samsung,pins = "gpp18-0", "gpp18-1";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart14_bus_single: uart14-bus-pins {</div><div class='add'>+		samsung,pins = "gpp18-0", "gpp18-1",</div><div class='add'>+			       "gpp18-2", "gpp18-3";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi14_bus: spi14-bus-pins {</div><div class='add'>+		samsung,pins = "gpp18-0", "gpp18-1", "gpp18-2";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi14_cs: spi14-cs-pins {</div><div class='add'>+		samsung,pins = "gpp18-3";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi14_cs_func: spi14-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp18-3";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c8_bus: hsi2c8-bus-pins {</div><div class='add'>+		samsung,pins = "gpp16-0", "gpp16-1";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;GS101_PIN_PDN_OUT0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart8_bus_single: uart8-bus-pins {</div><div class='add'>+		samsung,pins = "gpp16-0", "gpp16-1", "gpp16-2",</div><div class='add'>+			       "gpp16-3";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi8_bus: spi8-bus-pins {</div><div class='add'>+		samsung,pins = "gpp16-0", "gpp16-1", "gpp16-2";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi8_cs: spi8-cs-pins {</div><div class='add'>+		samsung,pins = "gpp16-3";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi8_cs_func: spi8-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp16-3";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c7_bus: hsi2c7-bus-pins {</div><div class='add'>+		samsung,pins = "gpp14-0", "gpp14-1";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart7_bus_single: uart7-bus-pins {</div><div class='add'>+		samsung,pins = "gpp14-0", "gpp14-1",</div><div class='add'>+			       "gpp14-2", "gpp14-3";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi7_bus: spi7-bus-pins {</div><div class='add'>+		samsung,pins = "gpp14-0", "gpp14-1", "gpp14-2";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi7_cs: spi7-cs-pins {</div><div class='add'>+		samsung,pins = "gpp14-3";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi7_cs_func: spi7-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp14-3";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c6_bus: hsi2c6-bus-pins {</div><div class='add'>+		samsung,pins = "gpp12-0", "gpp12-1";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart6_bus_single: uart6-bus-pins {</div><div class='add'>+		samsung,pins = "gpp12-0", "gpp12-1",</div><div class='add'>+			       "gpp12-2", "gpp12-3";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi6_bus: spi6-bus-pins {</div><div class='add'>+		samsung,pins = "gpp12-0", "gpp12-1", "gpp12-2";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi6_cs: spi6-cs-pins {</div><div class='add'>+		samsung,pins = "gpp12-3";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi6_cs_func: spi6-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp12-3";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c5_bus: hsi2c5-bus-pins {</div><div class='add'>+		samsung,pins = "gpp10-0", "gpp10-1";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart5_bus_single: uart5-bus-pins {</div><div class='add'>+		samsung,pins = "gpp10-0", "gpp10-1",</div><div class='add'>+			       "gpp10-2", "gpp10-3";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi5_bus: spi5-bus-pins {</div><div class='add'>+		samsung,pins = "gpp10-0", "gpp10-1", "gpp10-2";</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;GS101_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi5_cs_func: spi5-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp10-3";</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-con-pdn = &lt;GS101_PIN_PDN_PREV&gt;;</div><div class='add'>+		samsung,pin-pud-pdn = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c4_bus: hsi2c4-bus-pins {</div><div class='add'>+		samsung,pins = "gpp8-0", "gpp8-1";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart4_bus_single: uart4-bus-pins {</div><div class='add'>+		samsung,pins = "gpp8-0", "gpp8-1",</div><div class='add'>+			       "gpp8-2", "gpp8-3";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi4_bus: spi4-bus-pins {</div><div class='add'>+		samsung,pins = "gpp8-0", "gpp8-1", "gpp8-2";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi4_cs: spi4-cs-pins {</div><div class='add'>+		samsung,pins = "gpp8-3";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi4_cs_func: spi4-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp8-3";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c3_bus: hsi2c3-bus-pins {</div><div class='add'>+		samsung,pins = "gpp6-0", "gpp6-1";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart3_bus_single: uart3-bus-pins {</div><div class='add'>+		samsung,pins = "gpp6-0", "gpp6-1",</div><div class='add'>+			       "gpp6-2", "gpp6-3";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi3_bus: spi3-bus-pins {</div><div class='add'>+		samsung,pins = "gpp6-0", "gpp6-1", "gpp6-2";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi3_cs: spi3-cs-pins {</div><div class='add'>+		samsung,pins = "gpp6-3";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi3_cs_func: spi3-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp6-3";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c2_bus: hsi2c2-bus-pins {</div><div class='add'>+		samsung,pins = "gpp4-0", "gpp4-1";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart2_bus_single: uart2-bus-pins {</div><div class='add'>+		samsung,pins = "gpp4-0", "gpp4-1",</div><div class='add'>+			       "gpp4-2", "gpp4-3";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi2_bus: spi2-bus-pins {</div><div class='add'>+		samsung,pins = "gpp4-0", "gpp4-1", "gpp4-2";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi2_cs: spi2-cs-pins {</div><div class='add'>+		samsung,pins = "gpp4-3";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi2_cs_func: spi2-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp4-3";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c1_bus: hsi2c1-bus-pins {</div><div class='add'>+		samsung,pins = "gpp2-0", "gpp2-1";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart1_bus_single: uart1-bus-pins {</div><div class='add'>+		samsung,pins = "gpp2-0", "gpp2-1",</div><div class='add'>+			       "gpp2-2", "gpp2-3";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi1_bus: spi1-bus-pins {</div><div class='add'>+		samsung,pins = "gpp2-0", "gpp2-1", "gpp2-2";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi1_cs: spi1-cs-pins {</div><div class='add'>+		samsung,pins = "gpp2-3";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi1_cs_func: spi1-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp2-3";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_peric1 {</div><div class='add'>+	gpp20: gpp20-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp21: gpp21-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp22: gpp22-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp23: gpp23-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp24: gpp24-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp25: gpp25-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp26: gpp26-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpp27: gpp27-gpio-bank {</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c13_bus: hsi2c13-bus-pins  {</div><div class='add'>+		samsung,pins = "gpp25-0", "gpp25-1";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart13_bus_single: uart13-bus-pins {</div><div class='add'>+		samsung,pins = "gpp25-0", "gpp25-1",</div><div class='add'>+			       "gpp25-2", "gpp25-3";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi13_bus: spi13-bus-pins {</div><div class='add'>+		samsung,pins = "gpp25-0", "gpp25-1", "gpp25-2";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi13_cs: spi13-cs-pins {</div><div class='add'>+		samsung,pins = "gpp25-3";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi13_cs_func: spi13-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp25-3";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c12_bus: hsi2c12-bus-pins {</div><div class='add'>+		samsung,pins = "gpp23-4", "gpp23-5";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart12_bus_single: uart12-bus-pins {</div><div class='add'>+		samsung,pins = "gpp23-4", "gpp23-5",</div><div class='add'>+			       "gpp23-6", "gpp23-7";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi12_bus: spi12-bus-pins {</div><div class='add'>+		samsung,pins = "gpp23-4", "gpp23-5", "gpp23-6";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi14_cs2: spi14-cs2-pins {</div><div class='add'>+		samsung,pins = "gpp23-6";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi12_cs: spi12-cs-pins {</div><div class='add'>+		samsung,pins = "gpp23-7";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi12_cs_func: spi12-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp23-7";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c11_bus: hsi2c11-bus-pins {</div><div class='add'>+		samsung,pins = "gpp23-0", "gpp23-1";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart11_bus_single: uart11-bus-pins {</div><div class='add'>+		samsung,pins = "gpp23-0", "gpp23-1",</div><div class='add'>+			       "gpp23-2", "gpp23-3";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi11_bus: spi11-bus-pins {</div><div class='add'>+		samsung,pins = "gpp23-0", "gpp23-1", "gpp23-2";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi11_cs: spi11-cs-pins {</div><div class='add'>+		samsung,pins = "gpp23-3";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi11_cs_func: spi11-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp23-3";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c10_bus: hsi2c10-bus-pins {</div><div class='add'>+		samsung,pins = "gpp21-0", "gpp21-1";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart10_bus_single: uart10-bus-pins {</div><div class='add'>+		samsung,pins = "gpp21-0", "gpp21-1",</div><div class='add'>+			       "gpp21-2", "gpp21-3";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi10_bus: spi10-bus-pins {</div><div class='add'>+		samsung,pins = "gpp21-0", "gpp21-1", "gpp21-2";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi10_cs: spi10-cs-pins {</div><div class='add'>+		samsung,pins = "gpp21-3";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi10_cs_func: spi10-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp21-3";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c9_bus: hsi2c9-bus-pins {</div><div class='add'>+		samsung,pins = "gpp20-4", "gpp20-5";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart9_bus_single: uart9-bus-pins {</div><div class='add'>+		samsung,pins = "gpp20-4", "gpp20-5",</div><div class='add'>+			       "gpp20-6", "gpp20-7";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi9_bus: spi9-bus-pins {</div><div class='add'>+		samsung,pins = "gpp20-4", "gpp20-5", "gpp20-6";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi9_cs: spi9-cs-pins {</div><div class='add'>+		samsung,pins = "gpp20-7";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi9_cs_func: spi9-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp20-7";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_2&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsi2c0_bus: hsi2c0-bus-pins {</div><div class='add'>+		samsung,pins = "gpp20-0", "gpp20-1";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart0_bus_single: uart0-bus-pins {</div><div class='add'>+		samsung,pins = "gpp20-0", "gpp20-1",</div><div class='add'>+			       "gpp20-2", "gpp20-3";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi0_bus: spi0-bus-pins {</div><div class='add'>+		samsung,pins = "gpp20-0", "gpp20-1", "gpp20-2";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi0_cs: spi0-cs-pins {</div><div class='add'>+		samsung,pins = "gpp20-3";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_OUTPUT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi0_cs_func: spi0-cs-func-pins {</div><div class='add'>+		samsung,pins = "gpp20-3";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_3&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/google/gs101-pinctrl.h b/arch/arm64/boot/dts/exynos/google/gs101-pinctrl.h<br/>new file mode 100644<br/>index 000000000000..b7d276b1e25a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/google/gs101-pinctrl.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/google/gs101-pinctrl.h</a></div><div class='hunk'>@@ -0,0 +1,33 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0 */</div><div class='add'>+/*</div><div class='add'>+ * Pinctrl binding constants for GS101</div><div class='add'>+ *</div><div class='add'>+ * Copyright 2020-2023 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __DTS_ARM64_SAMSUNG_EXYNOS_GOOGLE_PINCTRL_GS101_H__</div><div class='add'>+#define __DTS_ARM64_SAMSUNG_EXYNOS_GOOGLE_PINCTRL_GS101_H__</div><div class='add'>+</div><div class='add'>+#define GS101_PIN_PULL_NONE		0</div><div class='add'>+#define GS101_PIN_PULL_DOWN		1</div><div class='add'>+#define GS101_PIN_PULL_UP		3</div><div class='add'>+</div><div class='add'>+/* Pin function in power down mode */</div><div class='add'>+#define GS101_PIN_PDN_OUT0		0</div><div class='add'>+#define GS101_PIN_PDN_OUT1		1</div><div class='add'>+#define GS101_PIN_PDN_INPUT		2</div><div class='add'>+#define GS101_PIN_PDN_PREV		3</div><div class='add'>+</div><div class='add'>+/* GS101 drive strengths */</div><div class='add'>+#define GS101_PIN_DRV_2_5_MA		0</div><div class='add'>+#define GS101_PIN_DRV_5_MA		1</div><div class='add'>+#define GS101_PIN_DRV_7_5_MA		2</div><div class='add'>+#define GS101_PIN_DRV_10_MA		3</div><div class='add'>+</div><div class='add'>+#define GS101_PIN_FUNC_INPUT		0</div><div class='add'>+#define GS101_PIN_FUNC_OUTPUT		1</div><div class='add'>+#define GS101_PIN_FUNC_2		2</div><div class='add'>+#define GS101_PIN_FUNC_3		3</div><div class='add'>+#define GS101_PIN_FUNC_EINT		0xf</div><div class='add'>+</div><div class='add'>+#endif /* __DTS_ARM64_SAMSUNG_EXYNOS_GOOGLE_PINCTRL_GS101_H__ */</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/google/gs101-pixel-common.dtsi b/arch/arm64/boot/dts/exynos/google/gs101-pixel-common.dtsi<br/>new file mode 100644<br/>index 000000000000..93892adaa679<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/google/gs101-pixel-common.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/google/gs101-pixel-common.dtsi</a></div><div class='hunk'>@@ -0,0 +1,397 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/*</div><div class='add'>+ * Device Tree nodes common for all GS101-based Pixel</div><div class='add'>+ *</div><div class='add'>+ * Copyright 2021-2023 Google LLC</div><div class='add'>+ * Copyright 2023 Linaro Ltd - &lt;peter.griffin@linaro.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/usb/pd.h&gt;</div><div class='add'>+#include "gs101-pinctrl.h"</div><div class='add'>+#include "gs101.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;serial_0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		/* Bootloader expects bootargs specified otherwise it crashes */</div><div class='add'>+		bootargs = "";</div><div class='add'>+		stdout-path = &amp;serial_0;</div><div class='add'>+</div><div class='add'>+		/* Use display framebuffer as setup by bootloader */</div><div class='add'>+		framebuffer0: framebuffer-0 {</div><div class='add'>+			compatible = "simple-framebuffer";</div><div class='add'>+			memory-region = &lt;&amp;cont_splash_mem&gt;;</div><div class='add'>+			/* format properties to be added by actual board */</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		pinctrl-0 = &lt;&amp;key_voldown&gt;, &lt;&amp;key_volup&gt;, &lt;&amp;key_power&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		button-vol-down {</div><div class='add'>+			label = "KEY_VOLUMEDOWN";</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpa7 3 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-vol-up {</div><div class='add'>+			label = "KEY_VOLUMEUP";</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpa8 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-power {</div><div class='add'>+			label = "KEY_POWER";</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpa10 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reboot-mode {</div><div class='add'>+		compatible = "nvmem-reboot-mode";</div><div class='add'>+		nvmem-cells = &lt;&amp;nvmem_reboot_mode&gt;;</div><div class='add'>+		nvmem-cell-names = "reboot-mode";</div><div class='add'>+		mode-bootloader = &lt;0x800000fc&gt;;</div><div class='add'>+		mode-charge = &lt;0x8000000a&gt;;</div><div class='add'>+		mode-dm-verity-device-corrupted = &lt;0x80000050&gt;;</div><div class='add'>+		mode-fastboot = &lt;0x800000fa&gt;;</div><div class='add'>+		mode-reboot-ab-update = &lt;0x80000052&gt;;</div><div class='add'>+		mode-recovery = &lt;0x800000ff&gt;;</div><div class='add'>+		mode-rescue = &lt;0x800000f9&gt;;</div><div class='add'>+		mode-shutdown-thermal = &lt;0x80000051&gt;;</div><div class='add'>+		mode-shutdown-thermal-battery = &lt;0x80000051&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* TODO: Remove this once PMIC is implemented  */</div><div class='add'>+	reg_placeholder: regulator-0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "placeholder_reg";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* TODO: Remove this once S2MPG11 slave PMIC is implemented  */</div><div class='add'>+	ufs_0_fixed_vcc_reg: regulator-1 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "ufs-vcc";</div><div class='add'>+		gpio = &lt;&amp;gpp0 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		cont_splash_mem: splash@fac00000 {</div><div class='add'>+			/* size to be updated by actual board */</div><div class='add'>+			reg = &lt;0x0 0xfac00000 0x0&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;acpm_ipc {</div><div class='add'>+	pmic {</div><div class='add'>+		compatible = "samsung,s2mpg10-pmic";</div><div class='add'>+		interrupts-extended = &lt;&amp;gpa0 6 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pmic_int&gt;;</div><div class='add'>+		system-power-controller;</div><div class='add'>+		wakeup-source;</div><div class='add'>+</div><div class='add'>+		clocks {</div><div class='add'>+			compatible = "samsung,s2mpg10-clk";</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			clock-output-names = "rtc32k_ap", "peri32k1",</div><div class='add'>+					     "peri32k2";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ext_24_5m {</div><div class='add'>+	clock-frequency = &lt;24576000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ext_200m {</div><div class='add'>+	clock-frequency = &lt;200000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hsi2c_8 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	eeprom: eeprom@50 {</div><div class='add'>+		compatible = "atmel,24c08";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hsi2c_12 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	/* TODO: add the devices once drivers exist */</div><div class='add'>+</div><div class='add'>+	usb-typec@25 {</div><div class='add'>+		compatible = "maxim,max77759-tcpci", "maxim,max33359";</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;gpa8 2 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;typec_int&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		connector {</div><div class='add'>+			compatible = "usb-c-connector";</div><div class='add'>+			label = "USB-C";</div><div class='add'>+			data-role = "dual";</div><div class='add'>+			power-role = "dual";</div><div class='add'>+			self-powered;</div><div class='add'>+			try-power-role = "sink";</div><div class='add'>+			op-sink-microwatt = &lt;2600000&gt;;</div><div class='add'>+			slow-charger-loop;</div><div class='add'>+			/*</div><div class='add'>+			 * max77759 operating in reverse boost mode (0xA) can</div><div class='add'>+			 * source up to 1.5A while extboost can only do ~1A.</div><div class='add'>+			 * Since extboost is the primary path, advertise 900mA.</div><div class='add'>+			 */</div><div class='add'>+			source-pdos = &lt;PDO_FIXED(5000, 900,</div><div class='add'>+						 (PDO_FIXED_SUSPEND</div><div class='add'>+						  | PDO_FIXED_USB_COMM</div><div class='add'>+						  | PDO_FIXED_DATA_SWAP</div><div class='add'>+						  | PDO_FIXED_DUAL_ROLE))&gt;;</div><div class='add'>+			sink-pdos = &lt;PDO_FIXED(5000, 3000,</div><div class='add'>+					       (PDO_FIXED_DATA_SWAP</div><div class='add'>+						| PDO_FIXED_USB_COMM</div><div class='add'>+						| PDO_FIXED_HIGHER_CAP</div><div class='add'>+						| PDO_FIXED_DUAL_ROLE))</div><div class='add'>+				     PDO_FIXED(9000, 2200, 0)</div><div class='add'>+				     PDO_PPS_APDO(5000, 11000, 3000)&gt;;</div><div class='add'>+			sink-vdos = &lt;VDO_IDH(1, 1, IDH_PTYPE_PERIPH, 0,</div><div class='add'>+					     IDH_PTYPE_DFP_HOST, 2, 0x18d1)</div><div class='add'>+				     VDO_CERT(0x0)</div><div class='add'>+				     VDO_PRODUCT(0x4ee1, 0x0)</div><div class='add'>+				     VDO_UFP(UFP_VDO_VER1_2,</div><div class='add'>+					     (DEV_USB2_CAPABLE</div><div class='add'>+					      | DEV_USB3_CAPABLE),</div><div class='add'>+					     UFP_RECEPTACLE, 0,</div><div class='add'>+					     AMA_VCONN_NOT_REQ, 0,</div><div class='add'>+					     UFP_ALTMODE_NOT_SUPP,</div><div class='add'>+					     UFP_USB32_GEN1)</div><div class='add'>+				     /* padding */ 0</div><div class='add'>+				     VDO_DFP(DFP_VDO_VER1_1,</div><div class='add'>+					     (HOST_USB2_CAPABLE</div><div class='add'>+					      | HOST_USB3_CAPABLE),</div><div class='add'>+					     DFP_RECEPTACLE, 0)&gt;;</div><div class='add'>+			sink-vdos-v1 = &lt;VDO_IDH(1, 1, IDH_PTYPE_PERIPH, 0,</div><div class='add'>+						0, 0, 0x18d1)</div><div class='add'>+					VDO_CERT(0x0)</div><div class='add'>+					VDO_PRODUCT(0x4ee1, 0x0)&gt;;</div><div class='add'>+			/*</div><div class='add'>+			 * Until bootloader is updated to set those two when</div><div class='add'>+			 * console is enabled, we disable PD here.</div><div class='add'>+			 */</div><div class='add'>+			pd-disable;</div><div class='add'>+			typec-power-opmode = "default";</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					usbc0_orien_sw: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;usbdrd31_phy_orien_switch&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					usbc0_role_sw: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;usbdrd31_dwc3_role_switch&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmic@66 {</div><div class='add'>+		compatible = "maxim,max77759";</div><div class='add'>+		reg = &lt;0x66&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;if_pmic_int&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		interrupts-extended = &lt;&amp;gpa8 3 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		gpio {</div><div class='add'>+			compatible = "maxim,max77759-gpio";</div><div class='add'>+</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			/*</div><div class='add'>+			 * "Human-readable name [SIGNAL_LABEL]" where the</div><div class='add'>+			 * latter comes from the schematic</div><div class='add'>+			 */</div><div class='add'>+			gpio-line-names = "OTG boost [OTG_BOOST_EN]",</div><div class='add'>+					  "max20339 IRQ [MW_OVP_INT_L]";</div><div class='add'>+</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nvmem-0 {</div><div class='add'>+			compatible = "maxim,max77759-nvmem";</div><div class='add'>+</div><div class='add'>+			nvmem-layout {</div><div class='add'>+				compatible = "fixed-layout";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				nvmem_reboot_mode: reboot-mode@0 {</div><div class='add'>+					reg = &lt;0x0 0x4&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				boot-reason@4 {</div><div class='add'>+					reg = &lt;0x4 0x4&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				shutdown-user-flag@8 {</div><div class='add'>+					reg = &lt;0x8 0x1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				rsoc@a {</div><div class='add'>+					reg = &lt;0xa 0x2&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_far_alive {</div><div class='add'>+	key_voldown: key-voldown-pins {</div><div class='add'>+		samsung,pins = "gpa7-3";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	key_volup: key-volup-pins {</div><div class='add'>+		samsung,pins = "gpa8-1";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	typec_int: typec-int-pins {</div><div class='add'>+		samsung,pins = "gpa8-2";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	if_pmic_int: if-pmic-int-pins {</div><div class='add'>+		samsung,pins = "gpa8-3";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_UP&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_gpio_alive {</div><div class='add'>+	pmic_int: pmic-int-pins {</div><div class='add'>+		samsung,pins = "gpa0-6";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	key_power: key-power-pins {</div><div class='add'>+		samsung,pins = "gpa10-1";</div><div class='add'>+		samsung,pin-function = &lt;GS101_PIN_FUNC_EINT&gt;;</div><div class='add'>+		samsung,pin-pud = &lt;GS101_PIN_PULL_NONE&gt;;</div><div class='add'>+		samsung,pin-drv = &lt;GS101_PIN_DRV_2_5_MA&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;serial_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ufs_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	vcc-supply = &lt;&amp;ufs_0_fixed_vcc_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ufs_0_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbdrd31 {</div><div class='add'>+	vdd10-supply = &lt;&amp;reg_placeholder&gt;;</div><div class='add'>+	vdd33-supply = &lt;&amp;reg_placeholder&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbdrd31_dwc3 {</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	role-switch-default-mode = "peripheral";</div><div class='add'>+	maximum-speed = "super-speed-plus";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	port {</div><div class='add'>+		usbdrd31_dwc3_role_switch: endpoint {</div><div class='add'>+			remote-endpoint = &lt;&amp;usbc0_role_sw&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbdrd31_phy {</div><div class='add'>+	orientation-switch;</div><div class='add'>+	/* TODO: Update these once PMIC is implemented */</div><div class='add'>+	pll-supply = &lt;&amp;reg_placeholder&gt;;</div><div class='add'>+	dvdd-usb20-supply = &lt;&amp;reg_placeholder&gt;;</div><div class='add'>+	vddh-usb20-supply = &lt;&amp;reg_placeholder&gt;;</div><div class='add'>+	vdd33-usb20-supply = &lt;&amp;reg_placeholder&gt;;</div><div class='add'>+	vdda-usbdp-supply = &lt;&amp;reg_placeholder&gt;;</div><div class='add'>+	vddh-usbdp-supply = &lt;&amp;reg_placeholder&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	port {</div><div class='add'>+		usbdrd31_phy_orien_switch: endpoint {</div><div class='add'>+			remote-endpoint = &lt;&amp;usbc0_orien_sw&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usi_uart {</div><div class='add'>+	samsung,clkreq-on; /* needed for UART mode */</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usi8 {</div><div class='add'>+	samsung,mode = &lt;USI_MODE_I2C&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usi12 {</div><div class='add'>+	samsung,mode = &lt;USI_MODE_I2C&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;watchdog_cl0 {</div><div class='add'>+	timeout-sec = &lt;30&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/google/gs101-raven.dts b/arch/arm64/boot/dts/exynos/google/gs101-raven.dts<br/>new file mode 100644<br/>index 000000000000..1e7e6b34b864<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/google/gs101-raven.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/google/gs101-raven.dts</a></div><div class='hunk'>@@ -0,0 +1,29 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/*</div><div class='add'>+ * Raven Device Tree</div><div class='add'>+ *</div><div class='add'>+ * Copyright 2021-2023 Google LLC</div><div class='add'>+ * Copyright 2023-2025 Linaro Ltd</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "gs101-pixel-common.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Raven";</div><div class='add'>+	compatible = "google,gs101-raven", "google,gs101";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cont_splash_mem {</div><div class='add'>+	reg = &lt;0x0 0xfac00000 (1440 * 3120 * 4)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;framebuffer0 {</div><div class='add'>+	width = &lt;1440&gt;;</div><div class='add'>+	height = &lt;3120&gt;;</div><div class='add'>+	stride = &lt;(1440 * 4)&gt;;</div><div class='add'>+	format = "a8r8g8b8";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi<br/>new file mode 100644<br/>index 000000000000..d06d1d05f364<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/exynos/google/gs101.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/exynos/google/gs101.dtsi</a></div><div class='hunk'>@@ -0,0 +1,1823 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/*</div><div class='add'>+ * GS101 SoC</div><div class='add'>+ *</div><div class='add'>+ * Copyright 2019-2023 Google LLC</div><div class='add'>+ * Copyright 2023 Linaro Ltd - &lt;peter.griffin@linaro.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/google,gs101.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/google,gs101-acpm.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/soc/samsung,exynos-usi.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "google,gs101";</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		pinctrl0 = &amp;pinctrl_gpio_alive;</div><div class='add'>+		pinctrl1 = &amp;pinctrl_far_alive;</div><div class='add'>+		pinctrl2 = &amp;pinctrl_gsacore;</div><div class='add'>+		pinctrl3 = &amp;pinctrl_gsactrl;</div><div class='add'>+		pinctrl4 = &amp;pinctrl_peric0;</div><div class='add'>+		pinctrl5 = &amp;pinctrl_peric1;</div><div class='add'>+		pinctrl6 = &amp;pinctrl_hsi1;</div><div class='add'>+		pinctrl7 = &amp;pinctrl_hsi2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu-map {</div><div class='add'>+			cluster0 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu0&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu1&gt;;</div><div class='add'>+				};</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu2&gt;;</div><div class='add'>+				};</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu3&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cluster1 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu4&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu5&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cluster2 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu6&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu7&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x0000&gt;;</div><div class='add'>+			clocks = &lt;&amp;acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			cpu-idle-states = &lt;&amp;ananke_cpu_sleep&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;250&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;70&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpucl0_opp_table&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@100 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x0100&gt;;</div><div class='add'>+			clocks = &lt;&amp;acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			cpu-idle-states = &lt;&amp;ananke_cpu_sleep&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;250&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;70&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpucl0_opp_table&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@200 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x0200&gt;;</div><div class='add'>+			clocks = &lt;&amp;acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			cpu-idle-states = &lt;&amp;ananke_cpu_sleep&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;250&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;70&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpucl0_opp_table&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@300 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x0300&gt;;</div><div class='add'>+			clocks = &lt;&amp;acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			cpu-idle-states = &lt;&amp;ananke_cpu_sleep&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;250&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;70&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpucl0_opp_table&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu4: cpu@400 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a76";</div><div class='add'>+			reg = &lt;0x0400&gt;;</div><div class='add'>+			clocks = &lt;&amp;acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL1&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			cpu-idle-states = &lt;&amp;enyo_cpu_sleep&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;620&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;284&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpucl1_opp_table&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu5: cpu@500 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a76";</div><div class='add'>+			reg = &lt;0x0500&gt;;</div><div class='add'>+			clocks = &lt;&amp;acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL1&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			cpu-idle-states = &lt;&amp;enyo_cpu_sleep&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;620&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;284&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpucl1_opp_table&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu6: cpu@600 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-x1";</div><div class='add'>+			reg = &lt;0x0600&gt;;</div><div class='add'>+			clocks = &lt;&amp;acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL2&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			cpu-idle-states = &lt;&amp;hera_cpu_sleep&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;650&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpucl2_opp_table&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu7: cpu@700 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-x1";</div><div class='add'>+			reg = &lt;0x0700&gt;;</div><div class='add'>+			clocks = &lt;&amp;acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL2&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			cpu-idle-states = &lt;&amp;hera_cpu_sleep&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;650&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpucl2_opp_table&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		idle-states {</div><div class='add'>+			entry-method = "psci";</div><div class='add'>+</div><div class='add'>+			ananke_cpu_sleep: cpu-ananke-sleep {</div><div class='add'>+				idle-state-name = "c2";</div><div class='add'>+				compatible = "arm,idle-state";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x0010000&gt;;</div><div class='add'>+				local-timer-stop;</div><div class='add'>+				entry-latency-us = &lt;70&gt;;</div><div class='add'>+				exit-latency-us = &lt;160&gt;;</div><div class='add'>+				min-residency-us = &lt;2000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			enyo_cpu_sleep: cpu-enyo-sleep {</div><div class='add'>+				idle-state-name = "c2";</div><div class='add'>+				compatible = "arm,idle-state";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x0010000&gt;;</div><div class='add'>+				local-timer-stop;</div><div class='add'>+				entry-latency-us = &lt;150&gt;;</div><div class='add'>+				exit-latency-us = &lt;190&gt;;</div><div class='add'>+				min-residency-us = &lt;2500&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			hera_cpu_sleep: cpu-hera-sleep {</div><div class='add'>+				idle-state-name = "c2";</div><div class='add'>+				compatible = "arm,idle-state";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x0010000&gt;;</div><div class='add'>+				local-timer-stop;</div><div class='add'>+				entry-latency-us = &lt;235&gt;;</div><div class='add'>+				exit-latency-us = &lt;220&gt;;</div><div class='add'>+				min-residency-us = &lt;3500&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpucl0_opp_table: opp-table-0 {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+		opp-shared;</div><div class='add'>+</div><div class='add'>+		opp-300000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;300000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;537500&gt;;</div><div class='add'>+			clock-latency-ns = &lt;500000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-574000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;574000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;600000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;500000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-738000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;738000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;618750&gt;;</div><div class='add'>+			clock-latency-ns = &lt;500000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-930000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;930000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;668750&gt;;</div><div class='add'>+			clock-latency-ns = &lt;500000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1098000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1098000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;712500&gt;;</div><div class='add'>+			clock-latency-ns = &lt;500000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1197000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1197000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;731250&gt;;</div><div class='add'>+			clock-latency-ns = &lt;500000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1328000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1328000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;762500&gt;;</div><div class='add'>+			clock-latency-ns = &lt;500000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1401000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1401000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;781250&gt;;</div><div class='add'>+			clock-latency-ns = &lt;500000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1598000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1598000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;831250&gt;;</div><div class='add'>+			clock-latency-ns = &lt;500000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1704000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1704000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;862500&gt;;</div><div class='add'>+			clock-latency-ns = &lt;500000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1803000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1803000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;906250&gt;;</div><div class='add'>+			clock-latency-ns = &lt;500000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpucl1_opp_table: opp-table-1 {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+		opp-shared;</div><div class='add'>+</div><div class='add'>+		opp-400000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;400000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;506250&gt;;</div><div class='add'>+			clock-latency-ns = &lt;500000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-553000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;553000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;537500&gt;;</div><div class='add'>+			clock-latency-ns = &lt;500000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-696000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;696000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;562500&gt;;</div><div class='add'>+			clock-latency-ns = &lt;500000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-799000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;799000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;581250&gt;;</div><div class='add'>+			clock-latency-ns = &lt;500000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-910000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;910000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;606250&gt;;</div><div class='add'>+			clock-latency-ns = &lt;500000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1024000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1024000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;625000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;500000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1197000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1197000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;662500&gt;;</div><div class='add'>+			clock-latency-ns = &lt;500000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1328000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1328000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;687500&gt;;</div><div class='add'>+			clock-latency-ns = &lt;500000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1491000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1491000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;731250&gt;;</div><div class='add'>+			clock-latency-ns = &lt;500000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1663000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1663000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;775000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;500000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1836000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1836000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;818750&gt;;</div><div class='add'>+			clock-latency-ns = &lt;500000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1999000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1999000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;868750&gt;;</div><div class='add'>+			clock-latency-ns = &lt;500000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-2130000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2130000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;918750&gt;;</div><div class='add'>+			clock-latency-ns = &lt;500000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-2253000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2253000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;968750&gt;;</div><div class='add'>+			clock-latency-ns = &lt;500000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpucl2_opp_table: opp-table-2 {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+		opp-shared;</div><div class='add'>+</div><div class='add'>+		opp-500000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;500000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;500000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;500000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-851000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;851000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;556250&gt;;</div><div class='add'>+			clock-latency-ns = &lt;500000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-984000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;984000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;575000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;500000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1106000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1106000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;606250&gt;;</div><div class='add'>+			clock-latency-ns = &lt;500000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1277000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1277000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;631250&gt;;</div><div class='add'>+			clock-latency-ns = &lt;500000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1426000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1426000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;662500&gt;;</div><div class='add'>+			clock-latency-ns = &lt;500000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1582000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1582000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;693750&gt;;</div><div class='add'>+			clock-latency-ns = &lt;500000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1745000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1745000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;731250&gt;;</div><div class='add'>+			clock-latency-ns = &lt;500000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1826000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1826000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;750000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;500000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-2048000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2048000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;793750&gt;;</div><div class='add'>+			clock-latency-ns = &lt;500000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-2188000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2188000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;831250&gt;;</div><div class='add'>+			clock-latency-ns = &lt;500000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-2252000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2252000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;850000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;500000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-2401000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2401000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;887500&gt;;</div><div class='add'>+			clock-latency-ns = &lt;500000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-2507000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2507000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;925000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;500000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-2630000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2630000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;968750&gt;;</div><div class='add'>+			clock-latency-ns = &lt;500000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-2704000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2704000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1000000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;500000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-2802000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2802000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1056250&gt;;</div><div class='add'>+			clock-latency-ns = &lt;500000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* ect node is required to be present by bootloader */</div><div class='add'>+	ect {</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ext_24_5m: clock-1 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-output-names = "oscclk";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ext_200m: clock-2 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-output-names = "ext-200m";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	firmware {</div><div class='add'>+		acpm_ipc: power-management {</div><div class='add'>+			compatible = "google,gs101-acpm-ipc";</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			mboxes = &lt;&amp;ap2apm_mailbox&gt;;</div><div class='add'>+			shmem = &lt;&amp;apm_sram&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu-0 {</div><div class='add'>+		compatible = "arm,cortex-a55-pmu";</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &amp;ppi_cluster0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu-1 {</div><div class='add'>+		compatible = "arm,cortex-a76-pmu";</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &amp;ppi_cluster1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu-2 {</div><div class='add'>+		compatible = "arm,cortex-x1-pmu";</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &amp;ppi_cluster2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu-3 {</div><div class='add'>+		compatible = "arm,dsu-pmu";</div><div class='add'>+		cpus = &lt;&amp;cpu0&gt;, &lt;&amp;cpu1&gt;, &lt;&amp;cpu2&gt;, &lt;&amp;cpu3&gt;,</div><div class='add'>+		       &lt;&amp;cpu4&gt;, &lt;&amp;cpu5&gt;, &lt;&amp;cpu6&gt;, &lt;&amp;cpu7&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-1.0";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved_memory: reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		gsa_reserved_protected: gsa@90200000 {</div><div class='add'>+			reg = &lt;0x0 0x90200000 0x400000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpu_fw_reserved: tpu-fw@93000000 {</div><div class='add'>+			reg = &lt;0x0 0x93000000 0x1000000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aoc_reserve: aoc@94000000 {</div><div class='add'>+			reg = &lt;0x0 0x94000000 0x03000000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		abl_reserved: abl@f8800000 {</div><div class='add'>+			reg = &lt;0x0 0xf8800000 0x02000000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dss_log_reserved: dss-log-reserved@fd3f0000 {</div><div class='add'>+			reg = &lt;0x0 0xfd3f0000 0x0000e000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		debug_kinfo_reserved: debug-kinfo-reserved@fd3fe000 {</div><div class='add'>+			reg = &lt;0x0 0xfd3fe000 0x00001000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		bldr_log_reserved: bldr-log-reserved@fd800000 {</div><div class='add'>+			reg = &lt;0x0 0xfd800000 0x00100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		bldr_log_hist_reserved: bldr-log-hist-reserved@fd900000 {</div><div class='add'>+			reg = &lt;0x0 0xfd900000 0x00002000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc: soc@0 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges = &lt;0x0 0x0 0x0 0x40000000&gt;;</div><div class='add'>+</div><div class='add'>+		cmu_misc: clock-controller@10010000 {</div><div class='add'>+			compatible = "google,gs101-cmu-misc";</div><div class='add'>+			reg = &lt;0x10010000 0x10000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_top CLK_DOUT_CMU_MISC_BUS&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_MISC_SSS&gt;;</div><div class='add'>+			clock-names = "bus", "sss";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sysreg_misc: syscon@10030000 {</div><div class='add'>+			compatible = "google,gs101-misc-sysreg", "syscon";</div><div class='add'>+			reg = &lt;0x10030000 0x10000&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_misc CLK_GOUT_MISC_SYSREG_MISC_PCLK&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		timer@10050000 {</div><div class='add'>+			compatible = "google,gs101-mct",</div><div class='add'>+				     "samsung,exynos4210-mct";</div><div class='add'>+			reg = &lt;0x10050000 0x800&gt;;</div><div class='add'>+			clocks = &lt;&amp;ext_24_5m&gt;, &lt;&amp;cmu_misc CLK_GOUT_MISC_MCT_PCLK&gt;;</div><div class='add'>+			clock-names = "fin_pll", "mct";</div><div class='add'>+			interrupts = &lt;GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+				     &lt;GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+				     &lt;GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+				     &lt;GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+				     &lt;GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+				     &lt;GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+				     &lt;GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+				     &lt;GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+				     &lt;GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+				     &lt;GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+				     &lt;GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+				     &lt;GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		watchdog_cl0: watchdog@10060000 {</div><div class='add'>+			compatible = "google,gs101-wdt";</div><div class='add'>+			reg = &lt;0x10060000 0x100&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_misc CLK_GOUT_MISC_WDT_CLUSTER0_PCLK&gt;,</div><div class='add'>+				 &lt;&amp;ext_24_5m&gt;;</div><div class='add'>+			clock-names = "watchdog", "watchdog_src";</div><div class='add'>+			interrupts = &lt;GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			samsung,syscon-phandle = &lt;&amp;pmu_system_controller&gt;;</div><div class='add'>+			samsung,cluster-index = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		watchdog_cl1: watchdog@10070000 {</div><div class='add'>+			compatible = "google,gs101-wdt";</div><div class='add'>+			reg = &lt;0x10070000 0x100&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_misc CLK_GOUT_MISC_WDT_CLUSTER1_PCLK&gt;,</div><div class='add'>+				 &lt;&amp;ext_24_5m&gt;;</div><div class='add'>+			clock-names = "watchdog", "watchdog_src";</div><div class='add'>+			interrupts = &lt;GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			samsung,syscon-phandle = &lt;&amp;pmu_system_controller&gt;;</div><div class='add'>+			samsung,cluster-index = &lt;1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@10400000 {</div><div class='add'>+			compatible = "arm,gic-v3";</div><div class='add'>+			#address-cells = &lt;0&gt;;</div><div class='add'>+			#interrupt-cells = &lt;4&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			reg = &lt;0x10400000 0x10000&gt;, /* GICD */</div><div class='add'>+			      &lt;0x10440000 0x100000&gt;;/* GICR * 8 */</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+</div><div class='add'>+			ppi-partitions {</div><div class='add'>+				ppi_cluster0: interrupt-partition-0 {</div><div class='add'>+					affinity = &lt;&amp;cpu0 &amp;cpu1 &amp;cpu2 &amp;cpu3&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				ppi_cluster1: interrupt-partition-1 {</div><div class='add'>+					affinity = &lt;&amp;cpu4 &amp;cpu5&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				ppi_cluster2: interrupt-partition-2 {</div><div class='add'>+					affinity = &lt;&amp;cpu6 &amp;cpu7&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_peric0: clock-controller@10800000 {</div><div class='add'>+			compatible = "google,gs101-cmu-peric0";</div><div class='add'>+			reg = &lt;0x10800000 0x10000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;ext_24_5m&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_PERIC0_BUS&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_PERIC0_IP&gt;;</div><div class='add'>+			clock-names = "oscclk", "bus", "ip";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sysreg_peric0: syscon@10820000 {</div><div class='add'>+			compatible = "google,gs101-peric0-sysreg", "syscon";</div><div class='add'>+			reg = &lt;0x10820000 0x10000&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_peric0: pinctrl@10840000 {</div><div class='add'>+			compatible = "google,gs101-pinctrl";</div><div class='add'>+			reg = &lt;0x10840000 0x00001000&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK&gt;;</div><div class='add'>+			clock-names = "pclk";</div><div class='add'>+			interrupts = &lt;GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi1: usi@109000c0 {</div><div class='add'>+			compatible = "google,gs101-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x109000c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,sysreg = &lt;&amp;sysreg_peric0 0x1000&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_1: i2c@10900000 {</div><div class='add'>+				compatible = "google,gs101-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x10900000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c1_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_1: serial@10900000 {</div><div class='add'>+				compatible = "google,gs101-uart";</div><div class='add'>+				reg = &lt;0x10900000 0xc0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart1_bus_single&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_1: spi@10900000 {</div><div class='add'>+				compatible = "google,gs101-spi";</div><div class='add'>+				reg = &lt;0x10900000 0x30&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi1_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi2: usi@109100c0 {</div><div class='add'>+			compatible = "google,gs101-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x109100c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,sysreg = &lt;&amp;sysreg_peric0 0x1004&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_2: i2c@10910000 {</div><div class='add'>+				compatible = "google,gs101-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x10910000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c2_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_2: serial@10910000 {</div><div class='add'>+				compatible = "google,gs101-uart";</div><div class='add'>+				reg = &lt;0x10910000 0xc0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart2_bus_single&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_2: spi@10910000 {</div><div class='add'>+				compatible = "google,gs101-spi";</div><div class='add'>+				reg = &lt;0x10910000 0x30&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi2_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi3: usi@109200c0 {</div><div class='add'>+			compatible = "google,gs101-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x109200c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,sysreg = &lt;&amp;sysreg_peric0 0x1008&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_3: i2c@10920000 {</div><div class='add'>+				compatible = "google,gs101-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x10920000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c3_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_3: serial@10920000 {</div><div class='add'>+				compatible = "google,gs101-uart";</div><div class='add'>+				reg = &lt;0x10920000 0xc0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart3_bus_single&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_3: spi@10920000 {</div><div class='add'>+				compatible = "google,gs101-spi";</div><div class='add'>+				reg = &lt;0x10920000 0x30&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi3_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi4: usi@109300c0 {</div><div class='add'>+			compatible = "google,gs101-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x109300c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,sysreg = &lt;&amp;sysreg_peric0 0x100c&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_4: i2c@10930000 {</div><div class='add'>+				compatible = "google,gs101-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x10930000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c4_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_4: serial@10930000 {</div><div class='add'>+				compatible = "google,gs101-uart";</div><div class='add'>+				reg = &lt;0x10930000 0xc0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart4_bus_single&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_4: spi@10930000 {</div><div class='add'>+				compatible = "google,gs101-spi";</div><div class='add'>+				reg = &lt;0x10930000 0x30&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi4_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi5: usi@109400c0 {</div><div class='add'>+			compatible = "google,gs101-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x109400c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,sysreg = &lt;&amp;sysreg_peric0 0x1010&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_5: i2c@10940000 {</div><div class='add'>+				compatible = "google,gs101-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x10940000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c5_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_5: serial@10940000 {</div><div class='add'>+				compatible = "google,gs101-uart";</div><div class='add'>+				reg = &lt;0x10940000 0xc0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart5_bus_single&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_5: spi@10940000 {</div><div class='add'>+				compatible = "google,gs101-spi";</div><div class='add'>+				reg = &lt;0x10940000 0x30&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi5_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi6: usi@109500c0 {</div><div class='add'>+			compatible = "google,gs101-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x109500c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,sysreg = &lt;&amp;sysreg_peric0 0x1014&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_6: i2c@10950000 {</div><div class='add'>+				compatible = "google,gs101-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x10950000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c6_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_6: serial@10950000 {</div><div class='add'>+				compatible = "google,gs101-uart";</div><div class='add'>+				reg = &lt;0x10950000 0xc0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart6_bus_single&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_6: spi@10950000 {</div><div class='add'>+				compatible = "google,gs101-spi";</div><div class='add'>+				reg = &lt;0x10950000 0x30&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi6_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi7: usi@109600c0 {</div><div class='add'>+			compatible = "google,gs101-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x109600c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,sysreg = &lt;&amp;sysreg_peric0 0x1018&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_7: i2c@10960000 {</div><div class='add'>+				compatible = "google,gs101-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x10960000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c7_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_7: serial@10960000 {</div><div class='add'>+				compatible = "google,gs101-uart";</div><div class='add'>+				reg = &lt;0x10960000 0xc0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart7_bus_single&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_7: spi@10960000 {</div><div class='add'>+				compatible = "google,gs101-spi";</div><div class='add'>+				reg = &lt;0x10960000 0x30&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi7_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi8: usi@109700c0 {</div><div class='add'>+			compatible = "google,gs101-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x109700c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,sysreg = &lt;&amp;sysreg_peric0 0x101c&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_8: i2c@10970000 {</div><div class='add'>+				compatible = "google,gs101-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x10970000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c8_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_8: serial@10970000 {</div><div class='add'>+				compatible = "google,gs101-uart";</div><div class='add'>+				reg = &lt;0x10970000 0xc0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart8_bus_single&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_8: spi@10970000 {</div><div class='add'>+				compatible = "google,gs101-spi";</div><div class='add'>+				reg = &lt;0x10970000 0x30&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi8_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi_uart: usi@10a000c0 {</div><div class='add'>+			compatible = "google,gs101-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x10a000c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,sysreg = &lt;&amp;sysreg_peric0 0x1020&gt;;</div><div class='add'>+			samsung,mode = &lt;USI_MODE_UART&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			serial_0: serial@10a00000 {</div><div class='add'>+				compatible = "google,gs101-uart";</div><div class='add'>+				reg = &lt;0x10a00000 0xc0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 634 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart0_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;256&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi14: usi@10a200c0 {</div><div class='add'>+			compatible = "google,gs101-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x10a200c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,sysreg = &lt;&amp;sysreg_peric0 0x1028&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_14: i2c@10a20000 {</div><div class='add'>+				compatible = "google,gs101-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x10a20000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c14_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_14: serial@10a20000 {</div><div class='add'>+				compatible = "google,gs101-uart";</div><div class='add'>+				reg = &lt;0x10a20000 0xc0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart14_bus_single&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_14: spi@10a20000 {</div><div class='add'>+				compatible = "google,gs101-spi";</div><div class='add'>+				reg = &lt;0x10a20000 0x30&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi14_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_peric1: clock-controller@10c00000 {</div><div class='add'>+			compatible = "google,gs101-cmu-peric1";</div><div class='add'>+			reg = &lt;0x10c00000 0x10000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;ext_24_5m&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_PERIC1_BUS&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_PERIC1_IP&gt;;</div><div class='add'>+			clock-names = "oscclk", "bus", "ip";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sysreg_peric1: syscon@10c20000 {</div><div class='add'>+			compatible = "google,gs101-peric1-sysreg", "syscon";</div><div class='add'>+			reg = &lt;0x10c20000 0x10000&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_peric1: pinctrl@10c40000 {</div><div class='add'>+			compatible = "google,gs101-pinctrl";</div><div class='add'>+			reg = &lt;0x10c40000 0x00001000&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK&gt;;</div><div class='add'>+			clock-names = "pclk";</div><div class='add'>+			interrupts = &lt;GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi0: usi@10d100c0 {</div><div class='add'>+			compatible = "google,gs101-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x10d100c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,sysreg = &lt;&amp;sysreg_peric1 0x1000&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_0: i2c@10d10000 {</div><div class='add'>+				compatible = "google,gs101-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x10d10000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c0_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_usi0: serial@10d10000 {</div><div class='add'>+				compatible = "google,gs101-uart";</div><div class='add'>+				reg = &lt;0x10d10000 0xc0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart0_bus_single&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_0: spi@10d10000 {</div><div class='add'>+				compatible = "google,gs101-spi";</div><div class='add'>+				reg = &lt;0x10d10000 0x30&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi0_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi9: usi@10d200c0 {</div><div class='add'>+			compatible = "google,gs101-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x10d200c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,sysreg = &lt;&amp;sysreg_peric1 0x1004&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_9: i2c@10d20000 {</div><div class='add'>+				compatible = "google,gs101-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x10d20000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c9_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_9: serial@10d20000 {</div><div class='add'>+				compatible = "google,gs101-uart";</div><div class='add'>+				reg = &lt;0x10d20000 0xc0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart9_bus_single&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_9: spi@10d20000 {</div><div class='add'>+				compatible = "google,gs101-spi";</div><div class='add'>+				reg = &lt;0x10d20000 0x30&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi9_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi10: usi@10d300c0 {</div><div class='add'>+			compatible = "google,gs101-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x10d300c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,sysreg = &lt;&amp;sysreg_peric1 0x1008&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_10: i2c@10d30000 {</div><div class='add'>+				compatible = "google,gs101-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x10d30000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c10_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_10: serial@10d30000 {</div><div class='add'>+				compatible = "google,gs101-uart";</div><div class='add'>+				reg = &lt;0x10d30000 0xc0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart10_bus_single&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_10: spi@10d30000 {</div><div class='add'>+				compatible = "google,gs101-spi";</div><div class='add'>+				reg = &lt;0x10d30000 0x30&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi10_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi11: usi@10d400c0 {</div><div class='add'>+			compatible = "google,gs101-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x10d400c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,sysreg = &lt;&amp;sysreg_peric1 0x100c&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_11: i2c@10d40000 {</div><div class='add'>+				compatible = "google,gs101-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x10d40000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c11_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_11: serial@10d40000 {</div><div class='add'>+				compatible = "google,gs101-uart";</div><div class='add'>+				reg = &lt;0x10d40000 0xc0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart11_bus_single&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_11: spi@10d40000 {</div><div class='add'>+				compatible = "google,gs101-spi";</div><div class='add'>+				reg = &lt;0x10d40000 0x30&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi11_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi12: usi@10d500c0 {</div><div class='add'>+			compatible = "google,gs101-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x10d500c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,sysreg = &lt;&amp;sysreg_peric1 0x1010&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_12: i2c@10d50000 {</div><div class='add'>+				compatible = "google,gs101-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x10d50000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c12_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_12: serial@10d50000 {</div><div class='add'>+				compatible = "google,gs101-uart";</div><div class='add'>+				reg = &lt;0x10d50000 0xc0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart12_bus_single&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_12: spi@10d50000 {</div><div class='add'>+				compatible = "google,gs101-spi";</div><div class='add'>+				reg = &lt;0x10d50000 0x30&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi12_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usi13: usi@10d600c0 {</div><div class='add'>+			compatible = "google,gs101-usi", "samsung,exynos850-usi";</div><div class='add'>+			reg = &lt;0x10d600c0 0x20&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6&gt;,</div><div class='add'>+				 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6&gt;;</div><div class='add'>+			clock-names = "pclk", "ipclk";</div><div class='add'>+			samsung,sysreg = &lt;&amp;sysreg_peric1 0x1014&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			hsi2c_13: i2c@10d60000 {</div><div class='add'>+				compatible = "google,gs101-hsi2c",</div><div class='add'>+					     "samsung,exynosautov9-hsi2c";</div><div class='add'>+				reg = &lt;0x10d60000 0xc0&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6&gt;;</div><div class='add'>+				clock-names = "hsi2c", "hsi2c_pclk";</div><div class='add'>+				interrupts = &lt;GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;hsi2c13_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial_13: serial@10d60000 {</div><div class='add'>+				compatible = "google,gs101-uart";</div><div class='add'>+				reg = &lt;0x10d60000 0xc0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6&gt;;</div><div class='add'>+				clock-names = "uart", "clk_uart_baud0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;uart13_bus_single&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				samsung,uart-fifosize = &lt;64&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi_13: spi@10d60000 {</div><div class='add'>+				compatible = "google,gs101-spi";</div><div class='add'>+				reg = &lt;0x10d60000 0x30&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6&gt;,</div><div class='add'>+					 &lt;&amp;cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6&gt;;</div><div class='add'>+				clock-names = "spi", "spi_busclk0";</div><div class='add'>+				interrupts = &lt;GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;spi13_bus&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_hsi0: clock-controller@11000000 {</div><div class='add'>+			compatible = "google,gs101-cmu-hsi0";</div><div class='add'>+			reg = &lt;0x11000000 0x10000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;ext_24_5m&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_HSI0_BUS&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_HSI0_DPGTC&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_HSI0_USB31DRD&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_HSI0_USBDPDBG&gt;;</div><div class='add'>+			clock-names = "oscclk", "bus", "dpgtc", "usb31drd",</div><div class='add'>+				      "usbdpdbg";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sysreg_hsi0: syscon@11020000 {</div><div class='add'>+			compatible = "google,gs101-hsi0-sysreg", "syscon";</div><div class='add'>+			reg = &lt;0x11020000 0x10000&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_hsi0 CLK_GOUT_HSI0_SYSREG_HSI0_PCLK&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usbdrd31_phy: phy@11100000 {</div><div class='add'>+			compatible = "google,gs101-usb31drd-phy";</div><div class='add'>+			reg = &lt;0x11100000 0x0200&gt;,</div><div class='add'>+			      &lt;0x110f0000 0x0800&gt;,</div><div class='add'>+			      &lt;0x110e0000 0x2800&gt;;</div><div class='add'>+			reg-names = "phy", "pcs", "pma";</div><div class='add'>+			clocks = &lt;&amp;cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_ACLK_PHYCTRL&gt;,</div><div class='add'>+				 &lt;&amp;cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB20_PHY_REFCLK_26&gt;,</div><div class='add'>+				 &lt;&amp;cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_CTRL_ACLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_CTRL_PCLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_SCL_APB_PCLK&gt;;</div><div class='add'>+			clock-names = "phy", "ref", "ctrl_aclk", "ctrl_pclk", "scl_pclk";</div><div class='add'>+			#phy-cells = &lt;1&gt;;</div><div class='add'>+			samsung,pmu-syscon = &lt;&amp;pmu_system_controller&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usbdrd31: usb@11110000 {</div><div class='add'>+			compatible = "google,gs101-dwusb3";</div><div class='add'>+			ranges = &lt;0x0 0x11110000 0x10000&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY&gt;,</div><div class='add'>+				&lt;&amp;cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_SUSPEND_CLK_26&gt;,</div><div class='add'>+				&lt;&amp;cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_LINK_ACLK&gt;,</div><div class='add'>+				&lt;&amp;cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_LINK_PCLK&gt;;</div><div class='add'>+			clock-names = "bus_early", "susp_clk", "link_aclk", "link_pclk";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			usbdrd31_dwc3: usb@0 {</div><div class='add'>+				compatible = "snps,dwc3";</div><div class='add'>+				reg = &lt;0x0 0x10000&gt;;</div><div class='add'>+				clocks = &lt;&amp;cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_REF_CLK_40&gt;;</div><div class='add'>+				clock-names = "ref";</div><div class='add'>+				interrupts = &lt;GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				phys = &lt;&amp;usbdrd31_phy 0&gt;, &lt;&amp;usbdrd31_phy 1&gt;;</div><div class='add'>+				phy-names = "usb2-phy", "usb3-phy";</div><div class='add'>+				snps,has-lpm-erratum;</div><div class='add'>+				snps,dis_u2_susphy_quirk;</div><div class='add'>+				snps,dis_u3_susphy_quirk;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_hsi1: pinctrl@11840000 {</div><div class='add'>+			compatible = "google,gs101-pinctrl";</div><div class='add'>+			reg = &lt;0x11840000 0x00001000&gt;;</div><div class='add'>+			/* TODO: update once support for this CMU exists */</div><div class='add'>+			clocks = &lt;0&gt;;</div><div class='add'>+			clock-names = "pclk";</div><div class='add'>+			interrupts = &lt;GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_hsi2: clock-controller@14400000 {</div><div class='add'>+			compatible = "google,gs101-cmu-hsi2";</div><div class='add'>+			reg = &lt;0x14400000 0x10000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;ext_24_5m&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_HSI2_BUS&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_HSI2_PCIE&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_HSI2_UFS_EMBD&gt;,</div><div class='add'>+				 &lt;&amp;cmu_top CLK_DOUT_CMU_HSI2_MMC_CARD&gt;;</div><div class='add'>+			clock-names = "oscclk", "bus", "pcie", "ufs", "mmc";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sysreg_hsi2: syscon@14420000 {</div><div class='add'>+			compatible = "google,gs101-hsi2-sysreg", "syscon";</div><div class='add'>+			reg = &lt;0x14420000 0x10000&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_hsi2 CLK_GOUT_HSI2_SYSREG_HSI2_PCLK&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_hsi2: pinctrl@14440000 {</div><div class='add'>+			compatible = "google,gs101-pinctrl";</div><div class='add'>+			reg = &lt;0x14440000 0x00001000&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_hsi2 CLK_GOUT_HSI2_GPIO_HSI2_PCLK&gt;;</div><div class='add'>+			clock-names = "pclk";</div><div class='add'>+			interrupts = &lt;GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ufs_0: ufs@14700000 {</div><div class='add'>+			compatible = "google,gs101-ufs";</div><div class='add'>+			reg = &lt;0x14700000 0x200&gt;,</div><div class='add'>+			      &lt;0x14701100 0x200&gt;,</div><div class='add'>+			      &lt;0x14780000 0xa000&gt;,</div><div class='add'>+			      &lt;0x14600000 0x100&gt;;</div><div class='add'>+			reg-names = "hci", "vs_hci", "unipro", "ufsp";</div><div class='add'>+			interrupts = &lt;GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_ACLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO&gt;,</div><div class='add'>+				 &lt;&amp;cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK&gt;,</div><div class='add'>+				 &lt;&amp;cmu_hsi2 CLK_GOUT_HSI2_SYSREG_HSI2_PCLK&gt;;</div><div class='add'>+			clock-names = "core_clk", "sclk_unipro_main", "fmp",</div><div class='add'>+				      "aclk", "pclk", "sysreg";</div><div class='add'>+			dma-coherent;</div><div class='add'>+			freq-table-hz = &lt;0 0&gt;, &lt;0 0&gt;, &lt;0 0&gt;, &lt;0 0&gt;, &lt;0 0&gt;, &lt;0 0&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;ufs_rst_n &amp;ufs_refclk_out&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			phys = &lt;&amp;ufs_0_phy&gt;;</div><div class='add'>+			phy-names = "ufs-phy";</div><div class='add'>+			samsung,sysreg = &lt;&amp;sysreg_hsi2 0x710&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ufs_0_phy: phy@14704000 {</div><div class='add'>+			compatible = "google,gs101-ufs-phy";</div><div class='add'>+			reg = &lt;0x14704000 0x3000&gt;;</div><div class='add'>+			reg-names = "phy-pma";</div><div class='add'>+			samsung,pmu-syscon = &lt;&amp;pmu_system_controller&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+			clocks = &lt;&amp;ext_24_5m&gt;;</div><div class='add'>+			clock-names = "ref_clk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_apm: clock-controller@17400000 {</div><div class='add'>+			compatible = "google,gs101-cmu-apm";</div><div class='add'>+			reg = &lt;0x17400000 0x10000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;ext_24_5m&gt;;</div><div class='add'>+			clock-names = "oscclk";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sysreg_apm: syscon@17420000 {</div><div class='add'>+			compatible = "google,gs101-apm-sysreg", "syscon";</div><div class='add'>+			reg = &lt;0x17420000 0x10000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmu_system_controller: system-controller@17460000 {</div><div class='add'>+			compatible = "google,gs101-pmu", "syscon";</div><div class='add'>+			reg = &lt;0x17460000 0x10000&gt;;</div><div class='add'>+			google,pmu-intr-gen-syscon = &lt;&amp;pmu_intr_gen&gt;;</div><div class='add'>+</div><div class='add'>+			poweroff: syscon-poweroff {</div><div class='add'>+				compatible = "syscon-poweroff";</div><div class='add'>+				offset = &lt;0x3e9c&gt;; /* PAD_CTRL_PWR_HOLD */</div><div class='add'>+				mask = &lt;0x00000100&gt;;</div><div class='add'>+				value = &lt;0x0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reboot: syscon-reboot {</div><div class='add'>+				compatible = "google,gs101-reboot";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reboot-mode {</div><div class='add'>+				compatible = "syscon-reboot-mode";</div><div class='add'>+				offset = &lt;0x0810&gt;; /* EXYNOS_PMU_SYSIP_DAT0 */</div><div class='add'>+				mode-bootloader = &lt;0xfc&gt;;</div><div class='add'>+				mode-charge = &lt;0x0a&gt;;</div><div class='add'>+				mode-dm-verity-device-corrupted = &lt;0x50&gt;;</div><div class='add'>+				mode-fastboot = &lt;0xfa&gt;;</div><div class='add'>+				mode-reboot-ab-update = &lt;0x52&gt;;</div><div class='add'>+				mode-recovery = &lt;0xff&gt;;</div><div class='add'>+				mode-rescue = &lt;0xf9&gt;;</div><div class='add'>+				mode-shutdown-thermal = &lt;0x51&gt;;</div><div class='add'>+				mode-shutdown-thermal-battery = &lt;0x51&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmu_intr_gen: syscon@17470000 {</div><div class='add'>+			compatible = "google,gs101-pmu-intr-gen", "syscon";</div><div class='add'>+			reg = &lt;0x17470000 0x10000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_gpio_alive: pinctrl@174d0000 {</div><div class='add'>+			compatible = "google,gs101-pinctrl";</div><div class='add'>+			reg = &lt;0x174d0000 0x00001000&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_apm CLK_GOUT_APM_APBIF_GPIO_ALIVE_PCLK&gt;;</div><div class='add'>+			clock-names = "pclk";</div><div class='add'>+</div><div class='add'>+			wakeup-interrupt-controller {</div><div class='add'>+				compatible = "google,gs101-wakeup-eint",</div><div class='add'>+					     "samsung,exynos850-wakeup-eint",</div><div class='add'>+					     "samsung,exynos7-wakeup-eint";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_far_alive: pinctrl@174e0000 {</div><div class='add'>+			compatible = "google,gs101-pinctrl";</div><div class='add'>+			reg = &lt;0x174e0000 0x00001000&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_apm CLK_GOUT_APM_APBIF_GPIO_FAR_ALIVE_PCLK&gt;;</div><div class='add'>+			clock-names = "pclk";</div><div class='add'>+</div><div class='add'>+			wakeup-interrupt-controller {</div><div class='add'>+				compatible = "google,gs101-wakeup-eint",</div><div class='add'>+					     "samsung,exynos850-wakeup-eint",</div><div class='add'>+					     "samsung,exynos7-wakeup-eint";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ap2apm_mailbox: mailbox@17610000 {</div><div class='add'>+			compatible = "google,gs101-mbox";</div><div class='add'>+			reg = &lt;0x17610000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmu_apm CLK_GOUT_APM_MAILBOX_APM_AP_PCLK&gt;;</div><div class='add'>+			clock-names = "pclk";</div><div class='add'>+			interrupts = &lt;GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			#mbox-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_gsactrl: pinctrl@17940000 {</div><div class='add'>+			compatible = "google,gs101-pinctrl";</div><div class='add'>+			reg = &lt;0x17940000 0x00001000&gt;;</div><div class='add'>+			/* TODO: update once support for this CMU exists */</div><div class='add'>+			clocks = &lt;0&gt;;</div><div class='add'>+			clock-names = "pclk";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_gsacore: pinctrl@17a80000 {</div><div class='add'>+			compatible = "google,gs101-pinctrl";</div><div class='add'>+			reg = &lt;0x17a80000 0x00001000&gt;;</div><div class='add'>+			/* TODO: update once support for this CMU exists */</div><div class='add'>+			clocks = &lt;0&gt;;</div><div class='add'>+			clock-names = "pclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmu_top: clock-controller@1e080000 {</div><div class='add'>+			compatible = "google,gs101-cmu-top";</div><div class='add'>+			reg = &lt;0x1e080000 0x10000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;ext_24_5m&gt;;</div><div class='add'>+			clock-names = "oscclk";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	apm_sram: sram@2039000 {</div><div class='add'>+		compatible = "mmio-sram";</div><div class='add'>+		reg = &lt;0x0 0x2039000 0x40000&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges = &lt;0x0 0x0 0x2039000 0x40000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts =</div><div class='add'>+		   &lt;GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0&gt;,</div><div class='add'>+		   &lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0&gt;,</div><div class='add'>+		   &lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0&gt;,</div><div class='add'>+		   &lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include "gs101-pinctrl.dtsi"</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile<br/>index a39f0a1723e0..f30d3fd724d0 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/Makefile?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/Makefile</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/Makefile</a></div><div class='hunk'>@@ -1,48 +1,460 @@</div><div class='ctx'> # SPDX-License-Identifier: GPL-2.0</div><div class='add'>+</div><div class='ctx'> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frwy.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-oxalis.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-qds.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-tqmls1012al-mbls1012al.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-tqmls1012al-mbls1012al-emmc.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-kbox-a-230-ls.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var1.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var2.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var3.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var3-ads2.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var4.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-rdb.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-tqmls1043a-mbls10xxa.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-frwy.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-tqmls1046a-mbls10xxa.dtb</div><div class='add'>+DTC_FLAGS_fsl-ls1088a-qds := -Wno-interrupt_map</div><div class='ctx'> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-qds.dtb</div><div class='add'>+DTC_FLAGS_fsl-ls1088a-rdb := -Wno-interrupt_map</div><div class='ctx'> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb</div><div class='add'>+DTC_FLAGS_fsl-ls1088a-ten64 := -Wno-interrupt_map</div><div class='add'>+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-ten64.dtb</div><div class='add'>+DTC_FLAGS_fsl-ls1088a-tqmls1088a-mbls10xxa := -Wno-interrupt_map</div><div class='add'>+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-tqmls1088a-mbls10xxa.dtb</div><div class='add'>+DTC_FLAGS_fsl-ls2080a-qds := -Wno-interrupt_map</div><div class='ctx'> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb</div><div class='add'>+DTC_FLAGS_fsl-ls2080a-rdb := -Wno-interrupt_map</div><div class='ctx'> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb</div><div class='add'>+DTC_FLAGS_fsl-ls2081a-rdb := -Wno-interrupt_map</div><div class='add'>+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2081a-rdb.dtb</div><div class='add'>+DTC_FLAGS_fsl-ls2080a-simu := -Wno-interrupt_map</div><div class='ctx'> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb</div><div class='add'>+DTC_FLAGS_fsl-ls2088a-qds := -Wno-interrupt_map</div><div class='ctx'> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb</div><div class='add'>+DTC_FLAGS_fsl-ls2088a-rdb := -Wno-interrupt_map</div><div class='ctx'> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb</div><div class='add'>+DTC_FLAGS_fsl-lx2160a-bluebox3 := -Wno-interrupt_map</div><div class='add'>+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-bluebox3.dtb</div><div class='add'>+DTC_FLAGS_fsl-lx2160a-bluebox3-rev-a := -Wno-interrupt_map</div><div class='add'>+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-bluebox3-rev-a.dtb</div><div class='add'>+DTC_FLAGS_fsl-lx2160a-clearfog-cx := -Wno-interrupt_map</div><div class='ctx'> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-clearfog-cx.dtb</div><div class='add'>+DTC_FLAGS_fsl-lx2160a-honeycomb := -Wno-interrupt_map</div><div class='ctx'> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-honeycomb.dtb</div><div class='add'>+DTC_FLAGS_fsl-lx2160a-qds := -Wno-interrupt_map</div><div class='ctx'> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb</div><div class='add'>+DTC_FLAGS_fsl-lx2160a-rdb := -Wno-interrupt_map</div><div class='ctx'> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb</div><div class='add'>+DTC_FLAGS_fsl-lx2162a-clearfog := -Wno-interrupt_map</div><div class='add'>+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2162a-clearfog.dtb</div><div class='add'>+DTC_FLAGS_fsl-lx2162a-qds := -Wno-interrupt_map</div><div class='add'>+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2162a-qds.dtb</div><div class='add'>+</div><div class='add'>+fsl-ls1028a-qds-13bb-dtbs := fsl-ls1028a-qds.dtb fsl-ls1028a-qds-13bb.dtbo</div><div class='add'>+fsl-ls1028a-qds-65bb-dtbs := fsl-ls1028a-qds.dtb fsl-ls1028a-qds-65bb.dtbo</div><div class='add'>+fsl-ls1028a-qds-7777-dtbs := fsl-ls1028a-qds.dtb fsl-ls1028a-qds-7777.dtbo</div><div class='add'>+fsl-ls1028a-qds-85bb-dtbs := fsl-ls1028a-qds.dtb fsl-ls1028a-qds-85bb.dtbo</div><div class='add'>+fsl-ls1028a-qds-899b-dtbs := fsl-ls1028a-qds.dtb fsl-ls1028a-qds-899b.dtbo</div><div class='add'>+fsl-ls1028a-qds-9999-dtbs := fsl-ls1028a-qds.dtb fsl-ls1028a-qds-9999.dtbo</div><div class='add'>+</div><div class='add'>+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-13bb.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-65bb.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-7777.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-85bb.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-899b.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-9999.dtb</div><div class='add'>+</div><div class='add'>+DTC_FLAGS_fsl-lx2160a-tqmlx2160a-mblx2160a := -Wno-interrupt_map</div><div class='add'>+fsl-lx2160a-tqmlx2160a-mblx2160a-12-11-x-dtbs := fsl-lx2160a-tqmlx2160a-mblx2160a.dtb \</div><div class='add'>+	fsl-lx2160a-tqmlx2160a-mblx2160a_12_x_x.dtbo \</div><div class='add'>+	fsl-lx2160a-tqmlx2160a-mblx2160a_x_11_x.dtbo</div><div class='add'>+fsl-lx2160a-tqmlx2160a-mblx2160a-12-7-x-dtbs := fsl-lx2160a-tqmlx2160a-mblx2160a.dtb \</div><div class='add'>+	fsl-lx2160a-tqmlx2160a-mblx2160a_12_x_x.dtbo \</div><div class='add'>+	fsl-lx2160a-tqmlx2160a-mblx2160a_x_7_x.dtbo</div><div class='add'>+fsl-lx2160a-tqmlx2160a-mblx2160a-12-8-x-dtbs := fsl-lx2160a-tqmlx2160a-mblx2160a.dtb \</div><div class='add'>+	fsl-lx2160a-tqmlx2160a-mblx2160a_12_x_x.dtbo \</div><div class='add'>+	fsl-lx2160a-tqmlx2160a-mblx2160a_x_8_x.dtbo</div><div class='add'>+fsl-lx2160a-tqmlx2160a-mblx2160a-14-7-x-dtbs := fsl-lx2160a-tqmlx2160a-mblx2160a.dtb \</div><div class='add'>+	fsl-lx2160a-tqmlx2160a-mblx2160a_14_x_x.dtbo \</div><div class='add'>+	fsl-lx2160a-tqmlx2160a-mblx2160a_x_7_x.dtbo</div><div class='add'>+fsl-lx2160a-tqmlx2160a-mblx2160a-14-8-x-dtbs := fsl-lx2160a-tqmlx2160a-mblx2160a.dtb \</div><div class='add'>+	fsl-lx2160a-tqmlx2160a-mblx2160a_14_x_x.dtbo \</div><div class='add'>+	fsl-lx2160a-tqmlx2160a-mblx2160a_x_8_x.dtbo</div><div class='add'>+fsl-lx2160a-tqmlx2160a-mblx2160a-14-11-x-dtbs := fsl-lx2160a-tqmlx2160a-mblx2160a.dtb \</div><div class='add'>+	fsl-lx2160a-tqmlx2160a-mblx2160a_14_x_x.dtbo \</div><div class='add'>+	fsl-lx2160a-tqmlx2160a-mblx2160a_x_11_x.dtbo</div><div class='add'>+</div><div class='add'>+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-tqmlx2160a-mblx2160a-12-11-x.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-tqmlx2160a-mblx2160a-12-8-x.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-tqmlx2160a-mblx2160a-12-7-x.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-tqmlx2160a-mblx2160a-14-11-x.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-tqmlx2160a-mblx2160a-14-8-x.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-tqmlx2160a-mblx2160a-14-7-x.dtb</div><div class='add'>+</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8dx-colibri-aster.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8dx-colibri-eval-v3.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8dx-colibri-iris-v2.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8dx-colibri-iris.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk.dtb</div><div class='ctx'> </div><div class='add'>+imx8dxl-evk-pcie-ep-dtbs += imx8dxl-evk.dtb imx-pcie0-ep.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk-pcie-ep.dtb</div><div class='add'>+</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8dxp-tqma8xdp-mba8xx.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8dxp-tqma8xdps-mb-smarc-2.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-data-modul-edm-sbc.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-emcon-avari.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-emtop-baseboard.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-evkb.dtb</div><div class='add'>+</div><div class='add'>+imx8mm-evk-pcie-ep-dtbs += imx8mm-evk.dtb imx-pcie0-ep.dtbo</div><div class='add'>+imx8mm-evkb-pcie-ep-dtbs += imx8mm-evkb.dtb imx-pcie0-ep.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk-pcie-ep.dtb imx8mm-evkb-pcie-ep.dtb</div><div class='add'>+</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-edimm2.2.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-iot-gateway.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-innocomm-wb15-evk.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-bl.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-bl-osm-s.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-mx8menlo.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-nitrogen-r2.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-phg.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-phyboard-polis-rdk.dtb</div><div class='add'>+</div><div class='add'>+imx8mm-phyboard-polis-peb-av-10-dtbs += imx8mm-phyboard-polis-rdk.dtb imx8mm-phyboard-polis-peb-av-10.dtbo</div><div class='add'>+imx8mm-phyboard-polis-peb-av-10-etml1010g3dra-dtbs += imx8mm-phyboard-polis-rdk.dtb \</div><div class='add'>+	imx8mm-phyboard-polis-peb-av-10-etml1010g3dra.dtbo</div><div class='add'>+imx8mm-phyboard-polis-peb-av-10-ph128800t006-dtbs += imx8mm-phyboard-polis-rdk.dtb \</div><div class='add'>+	imx8mm-phyboard-polis-peb-av-10-ph128800t006.dtbo</div><div class='add'>+imx8mm-phyboard-polis-peb-eval-01-dtbs += imx8mm-phyboard-polis-rdk.dtb imx8mm-phyboard-polis-peb-eval-01.dtbo</div><div class='add'>+imx8mm-phycore-no-eth-dtbs += imx8mm-phyboard-polis-rdk.dtb imx8mm-phycore-no-eth.dtbo</div><div class='add'>+imx8mm-phycore-no-spiflash-dtbs += imx8mm-phyboard-polis-rdk.dtb imx8mm-phycore-no-spiflash.dtbo</div><div class='add'>+imx8mm-phycore-rpmsg-dtbs += imx8mm-phyboard-polis-rdk.dtb imx8mm-phycore-rpmsg.dtbo</div><div class='add'>+</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-phyboard-polis-peb-av-10.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-phyboard-polis-peb-av-10-etml1010g3dra.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-phyboard-polis-peb-av-10-ph128800t006.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-phyboard-polis-peb-eval-01.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-phycore-no-eth.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-phycore-no-spiflash.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-phycore-rpmsg.dtb</div><div class='add'>+</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-phygate-tauri-l.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-prt8mm.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw71xx-0x.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw75xx-0x.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7901.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7902.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7903.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7904.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dahlia.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dev.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-ivy.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-mallow.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-yavia.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dahlia.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-ivy.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-mallow.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-yavia.dtb</div><div class='add'>+</div><div class='add'>+imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33-dtbs += imx8mm-tqma8mqml-mba8mx.dtb imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtb</div><div class='add'>+</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mn-beacon-kit.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mn-bsh-smm-s2.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mn-bsh-smm-s2pro.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mn-dimonoff-gateway-evk.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr3l-evk.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mn-rve-gateway.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mn-venice-gw7902.dtb</div><div class='add'>+</div><div class='add'>+imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33-dtbs += imx8mn-tqma8mqnl-mba8mx.dtb imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtbo</div><div class='add'>+imx8mn-tqma8mqnl-mba8mx-usbotg-dtbs += imx8mn-tqma8mqnl-mba8mx.dtb imx8mn-tqma8mqnl-mba8mx-usbotg.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx-usbotg.dtb</div><div class='add'>+</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-aristainetos3-adpismarc.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-aristainetos3-helios.dtb</div><div class='add'>+imx8mp-aristainetos3-helios-lvds-dtbs += imx8mp-aristainetos3-helios.dtb imx8mp-aristainetos3-helios-lvds.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-aristainetos3-helios-lvds.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-aristainetos3-proton2s.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-beacon-kit.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-cubox-m.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-data-modul-edm-sbc.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-model-a.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-som-a-bmb-08.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-drc02.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk2.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk3.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-picoitx.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-edm-g-wb.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-mate.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-pro.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-pulse.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-ripple.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-icore-mx8mp-edimm2.2.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-iota2-lumpy.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-kontron-bl-osm-s.dtb</div><div class='add'>+</div><div class='add'>+imx8mp-kontron-dl-dtbs += imx8mp-kontron-bl-osm-s.dtb imx8mp-kontron-dl.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-kontron-dl.dtb</div><div class='add'>+</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-kontron-smarc-eval-carrier.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-libra-rdk-fpsc.dtb</div><div class='add'>+imx8mp-libra-rdk-fpsc-lvds-dtbs += imx8mp-libra-rdk-fpsc.dtb imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-libra-rdk-fpsc-lvds.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-msc-sm2s-ep1.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-navqp.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-nitrogen-enc-carrier-board.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-nitrogen-smarc-universal-board.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb</div><div class='add'>+imx8mp-phyboard-pollux-etml1010g3dra-dtbs += imx8mp-phyboard-pollux-rdk.dtb \</div><div class='add'>+	imx8mp-phyboard-pollux-etml1010g3dra.dtbo</div><div class='add'>+imx8mp-phyboard-pollux-peb-av-10-dtbs += imx8mp-phyboard-pollux-rdk.dtb \</div><div class='add'>+	imx8mp-phyboard-pollux-peb-av-10.dtbo</div><div class='add'>+imx8mp-phyboard-pollux-peb-av-10-etml1010g3dra-dtbs += imx8mp-phyboard-pollux-rdk.dtb \</div><div class='add'>+	imx8mp-phyboard-pollux-peb-av-10-etml1010g3dra.dtbo</div><div class='add'>+imx8mp-phyboard-pollux-peb-av-10-ph128800t006-dtbs += imx8mp-phyboard-pollux-rdk.dtb \</div><div class='add'>+	imx8mp-phyboard-pollux-peb-av-10-ph128800t006.dtbo</div><div class='add'>+imx8mp-phyboard-pollux-ph128800t006-dtbs += imx8mp-phyboard-pollux-rdk.dtb \</div><div class='add'>+	imx8mp-phyboard-pollux-ph128800t006.dtbo</div><div class='add'>+imx8mp-phyboard-pollux-rdk-no-eth-dtbs += imx8mp-phyboard-pollux-rdk.dtb imx8mp-phycore-no-eth.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-etml1010g3dra.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-peb-av-10.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-peb-av-10-etml1010g3dra.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-peb-av-10-ph128800t006.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-ph128800t006.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk-no-eth.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-prt8ml.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-basic.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-hdmi.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-lt6.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-mi1010ait-1cp1.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revc-bd500.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revc-hdmi.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revc-tian-g07017.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revc-jutouch-jt101tm023.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-toradex-smarc-dev.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314.dtb</div><div class='add'>+</div><div class='add'>+imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10-dtbs += imx8mp-tx8p-ml81-moduline-display-106.dtb \</div><div class='add'>+	imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dtbo</div><div class='add'>+imx8mp-tx8p-ml81-moduline-display-106-av123z7m-n17-dtbs += imx8mp-tx8p-ml81-moduline-display-106.dtb \</div><div class='add'>+	imx8mp-tx8p-ml81-moduline-display-106-av123z7m-n17.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-tx8p-ml81-moduline-display-106-av123z7m-n17.dtb</div><div class='add'>+</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-ultra-mach-sbc.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-var-som-symphony.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw71xx-2x.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw72xx-2x.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw73xx-2x.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw75xx-2x.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw82xx-2x.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dahlia.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dev.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-ivy.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-mallow.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-yavia.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-dahlia.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-dev.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-ivy.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-mallow.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-yavia.dtb</div><div class='add'>+</div><div class='add'>+imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0-dtbs += imx8mp-evk.dtb imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtbo</div><div class='add'>+imx8mp-evk-lvds0-imx-lvds-hdmi-dtbs += imx8mp-evk.dtb imx8mp-evk-lvds0-imx-lvds-hdmi.dtbo</div><div class='add'>+imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0-dtbs += imx8mp-evk.dtb imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtbo</div><div class='add'>+imx8mp-evk-lvds1-imx-lvds-hdmi-dtbs += imx8mp-evk.dtb imx8mp-evk-lvds1-imx-lvds-hdmi.dtbo</div><div class='add'>+imx8mp-evk-mx8-dlvds-lcd1-dtbs += imx8mp-evk.dtb imx8mp-evk-mx8-dlvds-lcd1.dtbo</div><div class='add'>+imx8mp-evk-pcie-ep-dtbs += imx8mp-evk.dtb imx-pcie0-ep.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-lvds0-imx-lvds-hdmi.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-lvds1-imx-lvds-hdmi.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-mx8-dlvds-lcd1.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-pcie-ep.dtb</div><div class='add'>+</div><div class='add'>+imx8mp-tqma8mpql-mba8mpxl-lvds-tm070jvhg33-dtbs += imx8mp-tqma8mpql-mba8mpxl.dtb imx8mp-tqma8mpql-mba8mpxl-lvds-tm070jvhg33.dtbo</div><div class='add'>+imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01-dtbs += imx8mp-tqma8mpql-mba8mpxl.dtb imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtbo</div><div class='add'>+imx8mp-tqma8mpql-mba8mp-ras314-imx219-dtbs += imx8mp-tqma8mpql-mba8mp-ras314.dtb imx8mp-tqma8mpql-mba8mp-ras314-imx219.dtbo</div><div class='add'>+imx8mp-tqma8mpql-mba8mp-ras314-lvds-tm070jvhg33-dtbs += imx8mp-tqma8mpql-mba8mp-ras314.dtb imx8mp-tqma8mpql-mba8mpxl-lvds-tm070jvhg33.dtbo</div><div class='add'>+imx8mp-tqma8mpql-mba8mp-ras314-lvds-tm070jvhg33-imx219-dtbs += imx8mp-tqma8mpql-mba8mp-ras314.dtb imx8mp-tqma8mpql-mba8mpxl-lvds-tm070jvhg33.dtbo imx8mp-tqma8mpql-mba8mp-ras314-imx219.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl-lvds-tm070jvhg33.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314-imx219.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314-lvds-tm070jvhg33.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314-lvds-tm070jvhg33-imx219.dtb</div><div class='add'>+</div><div class='ctx'> dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb</div><div class='add'>+imx8mq-evk-pcie1-ep-dtbs += imx8mq-evk.dtb imx-pcie1-ep.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-pcie1-ep.dtb</div><div class='add'>+</div><div class='ctx'> dtb-$(CONFIG_ARCH_MXC) += imx8mq-hummingboard-pulse.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mq-kontron-pitx-imx8m.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r2.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r3.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r4.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mq-tqma8mq-mba8mx.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mq-mnt-reform2.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MXC) += imx8mq-nitrogen.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MXC) += imx8mq-phanbell.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MXC) += imx8mq-pico-pi.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MXC) += imx8mq-thor96.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb</div><div class='add'>+</div><div class='add'>+imx8mq-tqma8mq-mba8mx-lvds-tm070jvhg33-dtbs += imx8mq-tqma8mq-mba8mx.dtb imx8mq-tqma8mq-mba8mx-lvds-tm070jvhg33.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mq-tqma8mq-mba8mx-lvds-tm070jvhg33.dtb</div><div class='add'>+</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-eval.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-eval-v1.2.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-ixora-v1.1.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-v1.1-eval.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-v1.1-eval-v1.2.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-v1.1-ixora-v1.1.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-v1.1-ixora-v1.2.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb</div><div class='add'>+</div><div class='add'>+imx8qm-mek-ov5640-csi0-dtbs := imx8qm-mek.dtb imx8qm-mek-ov5640-csi0.dtbo</div><div class='add'>+dtb-${CONFIG_ARCH_MXC} += imx8qm-mek-ov5640-csi0.dtb</div><div class='add'>+imx8qm-mek-ov5640-csi1-dtbs := imx8qm-mek.dtb imx8qm-mek-ov5640-csi1.dtbo</div><div class='add'>+dtb-${CONFIG_ARCH_MXC} += imx8qm-mek-ov5640-csi1.dtb</div><div class='add'>+imx8qm-mek-ov5640-dual-dtbs := imx8qm-mek.dtb imx8qm-mek-ov5640-csi0.dtbo imx8qm-mek-ov5640-csi1.dtbo</div><div class='add'>+dtb-${CONFIG_ARCH_MXC} += imx8qm-mek-ov5640-dual.dtb</div><div class='add'>+</div><div class='ctx'> dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-aster.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-iris.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-iris-v2.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb</div><div class='ctx'> </div><div class='add'>+imx8qxp-mek-pcie-ep-dtbs += imx8qxp-mek.dtb imx-pcie0-ep.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek-pcie-ep.dtb</div><div class='add'>+</div><div class='add'>+imx8qxp-mek-ov5640-csi-dtbs := imx8qxp-mek.dtb imx8qxp-mek-ov5640-csi.dtbo</div><div class='add'>+dtb-${CONFIG_ARCH_MXC} += imx8qxp-mek-ov5640-csi.dtb</div><div class='add'>+</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqp-mba8xx.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqps-mb-smarc-2.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8ulp-9x9-evk.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-evk.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx91-phyboard-segin.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba91xxca.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb.dtb</div><div class='add'>+</div><div class='add'>+imx93-9x9-qsb-i3c-dtbs += imx93-9x9-qsb.dtb imx93-9x9-qsb-i3c.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb-i3c.dtb</div><div class='add'>+</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx93-14x14-evk.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx93-kontron-bl-osm-s.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-nash.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin.dtb</div><div class='add'>+</div><div class='add'>+imx93-phyboard-nash-jtag-dtbs += imx93-phyboard-nash.dtb imx93-phyboard-nash-jtag.dtbo</div><div class='add'>+imx93-phyboard-nash-peb-wlbt-07-dtbs += imx93-phyboard-nash.dtb imx93-phyboard-nash-peb-wlbt-07.dtbo</div><div class='add'>+imx93-phyboard-nash-pwm-fan-dtbs += imx93-phyboard-nash.dtb imx93-phyboard-nash-pwm-fan.dtbo</div><div class='add'>+imx93-phyboard-segin-peb-eval-01-dtbs += imx93-phyboard-segin.dtb imx93-phyboard-segin-peb-eval-01.dtbo</div><div class='add'>+imx93-phyboard-segin-peb-wlbt-05-dtbs += imx93-phyboard-segin.dtb imx93-phyboard-segin-peb-wlbt-05.dtbo</div><div class='add'>+imx93-phycore-rpmsg-dtbs += imx93-phyboard-nash.dtb imx93-phyboard-segin.dtb imx93-phycore-rpmsg.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-nash-jtag.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-nash-peb-wlbt-07.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-nash-pwm-fan.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin-peb-eval-01.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin-peb-wlbt-05.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx93-phycore-rpmsg.dtb</div><div class='add'>+</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba91xxca.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx943-evk.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk-sof.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx95-toradex-smarc-dev.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx95-tqma9596sa-mb-smarc-2.dtb</div><div class='add'>+</div><div class='add'>+imx95-15x15-evk-pcie0-ep-dtbs = imx95-15x15-evk.dtb imx-pcie0-ep.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk-pcie0-ep.dtb</div><div class='add'>+imx95-19x19-evk-pcie0-ep-dtbs += imx95-19x19-evk.dtb imx-pcie0-ep.dtbo</div><div class='add'>+imx95-19x19-evk-pcie1-ep-dtbs += imx95-19x19-evk.dtb imx-pcie1-ep.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk-pcie0-ep.dtb imx95-19x19-evk-pcie1-ep.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx95-libra-rdk-fpsc.dtb</div><div class='add'>+</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-verdin-evk.dtb</div><div class='add'>+</div><div class='add'>+imx8mm-kontron-dl-dtbs			:= imx8mm-kontron-bl.dtb imx8mm-kontron-dl.dtbo</div><div class='add'>+imx8mm-kontron-bl-lte-dtbs		:= imx8mm-kontron-bl.dtb imx8mm-kontron-bl-lte.dtbo</div><div class='add'>+</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-dl.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-bl-lte.dtb</div><div class='add'>+</div><div class='add'>+imx8mm-venice-gw72xx-0x-imx219-dtbs	:= imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-imx219.dtbo</div><div class='add'>+imx8mm-venice-gw72xx-0x-rpidsi-dtbs	:= imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rpidsi.dtbo</div><div class='add'>+imx8mm-venice-gw72xx-0x-rs232-rts-dtbs	:= imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rs232-rts.dtbo</div><div class='add'>+imx8mm-venice-gw72xx-0x-rs422-dtbs	:= imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rs422.dtbo</div><div class='add'>+imx8mm-venice-gw72xx-0x-rs485-dtbs	:= imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rs485.dtbo</div><div class='add'>+imx8mm-venice-gw73xx-0x-imx219-dtbs	:= imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-imx219.dtbo</div><div class='add'>+imx8mm-venice-gw73xx-0x-rpidsi-dtbs	:= imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rpidsi.dtbo</div><div class='add'>+imx8mm-venice-gw73xx-0x-rs232-rts-dtbs	:= imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs232-rts.dtbo</div><div class='add'>+imx8mm-venice-gw73xx-0x-rs422-dtbs	:= imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs422.dtbo</div><div class='add'>+imx8mm-venice-gw73xx-0x-rs485-dtbs	:= imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs485.dtbo</div><div class='add'>+imx8mp-venice-gw74xx-imx219-dtbs	:= imx8mp-venice-gw74xx.dtb imx8mp-venice-gw74xx-imx219.dtbo</div><div class='add'>+imx8mp-venice-gw74xx-rpidsi-dtbs	:= imx8mp-venice-gw74xx.dtb imx8mp-venice-gw74xx-rpidsi.dtbo</div><div class='add'>+</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-imx219.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-rpidsi.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-rs232-rts.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-rs422.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-rs485.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-imx219.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rpidsi.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs232-rts.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs422.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs485.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx-imx219.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx-rpidsi.dtb</div><div class='add'>+</div><div class='add'>+imx8mm-phygate-tauri-l-rs232-rs232-dtbs		:= imx8mm-phygate-tauri-l.dtb imx8mm-phygate-tauri-l-rs232-rs232.dtbo</div><div class='add'>+imx8mm-phygate-tauri-l-rs232-cts-rts-dtbs	:= imx8mm-phygate-tauri-l.dtb imx8mm-phygate-tauri-l-rs232-rts-cts.dtbo</div><div class='add'>+imx8mm-phygate-tauri-l-rs232-rs485-dtbs		:= imx8mm-phygate-tauri-l.dtb imx8mm-phygate-tauri-l-rs232-rs485.dtbo</div><div class='add'>+</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-phygate-tauri-l-rs232-rs232.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-phygate-tauri-l-rs232-cts-rts.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MXC) += imx8mm-phygate-tauri-l-rs232-rs485.dtb</div><div class='add'>+</div><div class='add'>+dtb-$(CONFIG_ARCH_S32) += s32g274a-evb.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_S32) += s32g274a-rdb2.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_S32) += s32g399a-rdb3.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts<br/>index f90c040fd5e8..75081ce3e9a6 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts</a></div><div class='hunk'>@@ -7,6 +7,7 @@</div><div class='ctx'>  */</div><div class='ctx'> /dts-v1/;</div><div class='ctx'> </div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='ctx'> #include "fsl-ls1012a.dtsi"</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='hunk'>@@ -19,6 +20,12 @@</div><div class='ctx'> 		clock-frequency = &lt;25000000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	sc16is7xx_clk: clock-sc16is7xx {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	reg_1p8v: regulator-1p8v {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "1P8V";</div><div class='hunk'>@@ -57,6 +64,20 @@</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;dspi {</div><div class='add'>+	bus-num = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	serial@0 {</div><div class='add'>+		compatible = "nxp,sc16is740";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;4000000&gt;;</div><div class='add'>+		clocks = &lt;&amp;sc16is7xx_clk&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;13 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;duart0 {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='hunk'>@@ -74,6 +95,21 @@</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;qspi {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	s25fs512s0: flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		spi-max-frequency = &lt;50000000&gt;;</div><div class='add'>+		m25p,fast-read;</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;2&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;sai2 {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts<br/>index 8749634c55ee..e8562585d4ac 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts</a></div><div class='hunk'>@@ -23,3 +23,22 @@</div><div class='ctx'> &amp;i2c0 {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='add'>+</div><div class='add'>+&amp;pcie1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qspi {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	w25q16dw0: flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		m25p,fast-read;</div><div class='add'>+		spi-max-frequency = &lt;50000000&gt;;</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;2&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-oxalis.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-oxalis.dts<br/>index 9927b096d343..242f4b0cb344 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1012a-oxalis.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1012a-oxalis.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1012a-oxalis.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls1012a-oxalis.dts</a></div><div class='hunk'>@@ -87,7 +87,7 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;pcie {</div><div class='add'>+&amp;pcie1 {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts<br/>index 2fb1cb1f7d8f..ce59b94d8c22 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts</a></div><div class='hunk'>@@ -13,6 +13,11 @@</div><div class='ctx'> 	model = "LS1012A QDS Board";</div><div class='ctx'> 	compatible = "fsl,ls1012a-qds", "fsl,ls1012a";</div><div class='ctx'> </div><div class='add'>+	aliases {</div><div class='add'>+		mmc0 = &amp;esdhc0;</div><div class='add'>+		mmc1 = &amp;esdhc1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	sys_mclk: clock-mclk {</div><div class='ctx'> 		compatible = "fixed-clock";</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='hunk'>@@ -64,7 +69,7 @@</div><div class='ctx'> 	flash@0 {</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;1&gt;;</div><div class='del'>-		compatible = "n25q128a11", "jedec,spi-nor";</div><div class='add'>+		compatible = "micron,n25q128a11", "jedec,spi-nor";</div><div class='ctx'> 		reg = &lt;0&gt;;</div><div class='ctx'> 		spi-max-frequency = &lt;10000000&gt;;</div><div class='ctx'> 	};</div><div class='hunk'>@@ -82,7 +87,7 @@</div><div class='ctx'> 	flash@2 {</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;1&gt;;</div><div class='del'>-		compatible = "en25s64", "jedec,spi-nor";</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='ctx'> 		spi-cpol;</div><div class='ctx'> 		spi-cpha;</div><div class='ctx'> 		reg = &lt;2&gt;;</div><div class='hunk'>@@ -105,7 +110,7 @@</div><div class='ctx'> &amp;i2c0 {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='del'>-	pca9547@77 {</div><div class='add'>+	i2c-mux@77 {</div><div class='ctx'> 		compatible = "nxp,pca9547";</div><div class='ctx'> 		reg = &lt;0x77&gt;;</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='hunk'>@@ -128,6 +133,21 @@</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;qspi {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	s25fs512s0: flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		spi-max-frequency = &lt;50000000&gt;;</div><div class='add'>+		m25p,fast-read;</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;2&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;sai2 {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts<br/>index 5edb1e137a52..e662677a6e28 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts</a></div><div class='hunk'>@@ -7,11 +7,18 @@</div><div class='ctx'>  */</div><div class='ctx'> /dts-v1/;</div><div class='ctx'> </div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='ctx'> #include "fsl-ls1012a.dtsi"</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	model = "LS1012A RDB Board";</div><div class='ctx'> 	compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;duart0;</div><div class='add'>+		mmc0 = &amp;esdhc0;</div><div class='add'>+		mmc1 = &amp;esdhc1;</div><div class='add'>+	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;duart0 {</div><div class='hunk'>@@ -33,6 +40,65 @@</div><div class='ctx'> </div><div class='ctx'> &amp;i2c0 {</div><div class='ctx'> 	status = "okay";</div><div class='add'>+</div><div class='add'>+	accelerometer@1e {</div><div class='add'>+		compatible = "nxp,fxos8700";</div><div class='add'>+		reg = &lt;0x1e&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio26&gt;;</div><div class='add'>+		interrupts = &lt;13 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+		interrupt-names = "INT1";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gyroscope@20 {</div><div class='add'>+		compatible = "nxp,fxas21002c";</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio@24 {</div><div class='add'>+		compatible = "nxp,pcal9555a";</div><div class='add'>+		reg = &lt;0x24&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio@25 {</div><div class='add'>+		compatible = "nxp,pcal9555a";</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio26: gpio@26 {</div><div class='add'>+		compatible = "nxp,pcal9555a";</div><div class='add'>+		reg = &lt;0x26&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio0&gt;;</div><div class='add'>+		interrupts = &lt;13 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	current-sensor@40 {</div><div class='add'>+		compatible = "ti,ina220";</div><div class='add'>+		reg = &lt;0x40&gt;;</div><div class='add'>+		shunt-resistor = &lt;2000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qspi {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	s25fs512s0: flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		spi-max-frequency = &lt;50000000&gt;;</div><div class='add'>+		m25p,fast-read;</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;2&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;2&gt;;</div><div class='add'>+	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;sata {</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-tqmls1012al-mbls1012al-emmc.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-tqmls1012al-mbls1012al-emmc.dts<br/>new file mode 100644<br/>index 000000000000..07026b067320<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1012a-tqmls1012al-mbls1012al-emmc.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls1012a-tqmls1012al-mbls1012al-emmc.dts</a></div><div class='hunk'>@@ -0,0 +1,23 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2018-2025 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Matthias Schiffer</div><div class='add'>+ * Author: Max Merchel</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "fsl-ls1012a-tqmls1012al-mbls1012al.dts"</div><div class='add'>+</div><div class='add'>+&amp;esdhc0 {</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_1v8&gt;;</div><div class='add'>+	/delete-property/ no-mmc;</div><div class='add'>+	/delete-property/ sd-uhs-sdr12;</div><div class='add'>+	/delete-property/ sd-uhs-sdr25;</div><div class='add'>+	/delete-property/ sd-uhs-sdr50;</div><div class='add'>+	/delete-property/ sd-uhs-sdr104;</div><div class='add'>+	mmc-ddr-1_8v;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	no-sd;</div><div class='add'>+	voltage-ranges = &lt;1800 1800&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-tqmls1012al-mbls1012al.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-tqmls1012al-mbls1012al.dts<br/>new file mode 100644<br/>index 000000000000..e46cc1a07f0c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1012a-tqmls1012al-mbls1012al.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls1012a-tqmls1012al-mbls1012al.dts</a></div><div class='hunk'>@@ -0,0 +1,366 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2018-2025 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Matthias Schiffer</div><div class='add'>+ * Author: Max Merchel</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/net/ti-dp83867.h&gt;</div><div class='add'>+#include "fsl-ls1012a-tqmls1012al.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "TQ-Systems TQMLS1012AL on MBLS1012AL";</div><div class='add'>+	compatible = "tq,ls1012a-tqmls1012al-mbls1012al", "tq,ls1012a-tqmls1012al", "fsl,ls1012a";</div><div class='add'>+	chassis-type = "embedded";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		/* use MAC from U-Boot environment */</div><div class='add'>+		/* TODO: PFE */</div><div class='add'>+		ethernet2 = &amp;swport0;</div><div class='add'>+		ethernet3 = &amp;swport1;</div><div class='add'>+		ethernet4 = &amp;swport2;</div><div class='add'>+		ethernet5 = &amp;swport3;</div><div class='add'>+		serial0 = &amp;duart0;</div><div class='add'>+		spi0 = &amp;qspi;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;duart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		autorepeat;</div><div class='add'>+</div><div class='add'>+		switch-1 {</div><div class='add'>+			label = "S2";</div><div class='add'>+			linux,code = &lt;BTN_0&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio_exp_3p3v 13 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		switch-2 {</div><div class='add'>+			label = "X15";</div><div class='add'>+			linux,code = &lt;BTN_1&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio_exp_1p8v 5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		switch-3 {</div><div class='add'>+			label = "X16";</div><div class='add'>+			linux,code = &lt;BTN_2&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio_exp_1p8v 4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_HEARTBEAT;</div><div class='add'>+			gpios = &lt;&amp;gpio_exp_3p3v 14 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			gpios = &lt;&amp;gpio_exp_3p3v 15 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,default-trigger = "default-on";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		/* global autoconfigured region for contiguous allocations */</div><div class='add'>+		linux,cma {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reusable;</div><div class='add'>+			/* 64 MiB */</div><div class='add'>+			size = &lt;0 0x04000000&gt;;</div><div class='add'>+			/*  512 - 128 MiB, our minimum RAM config will be 512 MiB */</div><div class='add'>+			alloc-ranges = &lt;0 0x80000000 0 0x98000000&gt;;</div><div class='add'>+			linux,cma-default;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_1v5: regulator-1v5 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "V_1V5";</div><div class='add'>+		regulator-min-microvolt = &lt;1500000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1500000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_1p5v_pcie: regulator-1p5v-pcie {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "V_1V5_PCIE";</div><div class='add'>+		regulator-min-microvolt = &lt;1500000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1500000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		gpio = &lt;&amp;gpio_exp_1p8v 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		vin-supply = &lt;&amp;reg_1v5&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_1p5v_wlan: regulator-1p5v-wlan {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "V_1V5_WLAN";</div><div class='add'>+		regulator-min-microvolt = &lt;1500000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1500000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		gpio = &lt;&amp;gpio_exp_1p8v 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		vin-supply = &lt;&amp;reg_1v5&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_1v8: regulator-1p8v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "V_1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3v3: regulator-3p3v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "3P3V";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3v3_pcie: regulator-3v3-pcie {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "V_3V3_PCIE";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		gpio = &lt;&amp;gpio_exp_3p3v 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		vin-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3v3_wlan: regulator-3v3-wlan {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "V_3V3_WLAN";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		gpio = &lt;&amp;gpio_exp_3p3v 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		vin-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;duart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;esdhc0 {</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+	no-mmc;</div><div class='add'>+	no-sdio;</div><div class='add'>+	disable-wp;</div><div class='add'>+	sd-uhs-sdr12;</div><div class='add'>+	sd-uhs-sdr25;</div><div class='add'>+	sd-uhs-sdr50;</div><div class='add'>+	sd-uhs-sdr104;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	gpio_exp_3p3v: gpio@20 {</div><div class='add'>+		compatible = "nxp,pca9555";</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio0&gt;;</div><div class='add'>+		interrupts = &lt;24 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		gpio-line-names = "", "", "GPIO_3V3_3", "",</div><div class='add'>+				  "", "", "", "",</div><div class='add'>+				  "", "GPIO_3V3_1", "GPIO_3V3_2", "",</div><div class='add'>+				  "", "", "", "";</div><div class='add'>+</div><div class='add'>+		wlan-disable-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+			line-name = "WLAN_DISABLE#";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie-rst-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+			line-name = "PCIE_RST#";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wlan-rst-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+			line-name = "WLAN_RST#";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie-dis-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;11 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+			line-name = "PCIE_DIS#";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie-wake-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;12 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			input;</div><div class='add'>+			line-name = "PCIE_WAKE#";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lm75_48: temperature-sensor@48 {</div><div class='add'>+		compatible = "national,lm75a";</div><div class='add'>+		reg = &lt;0x48&gt;;</div><div class='add'>+		vs-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	switch@5f {</div><div class='add'>+		compatible = "microchip,ksz9897";</div><div class='add'>+		reg = &lt;0x5f&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio_exp_3p3v 7 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			swport0: port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				label = "swp0";</div><div class='add'>+				phy-mode = "internal";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			swport1: port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				label = "swp1";</div><div class='add'>+				phy-mode = "internal";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			swport2: port@2 {</div><div class='add'>+				reg = &lt;2&gt;;</div><div class='add'>+				label = "swp2";</div><div class='add'>+				phy-mode = "internal";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			swport3: port@3 {</div><div class='add'>+				reg = &lt;3&gt;;</div><div class='add'>+				label = "swp3";</div><div class='add'>+				phy-mode = "internal";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@6 {</div><div class='add'>+				reg = &lt;6&gt;;</div><div class='add'>+				label = "cpu";</div><div class='add'>+				/* TODO: PFE */</div><div class='add'>+				phy-mode = "rgmii-id";</div><div class='add'>+				rx-internal-delay-ps = &lt;1500&gt;;</div><div class='add'>+				tx-internal-delay-ps = &lt;1500&gt;;</div><div class='add'>+</div><div class='add'>+				fixed-link {</div><div class='add'>+					speed = &lt;1000&gt;;</div><div class='add'>+					full-duplex;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio_exp_1p8v: gpio@70 {</div><div class='add'>+		compatible = "nxp,pca9538";</div><div class='add'>+		reg = &lt;0x70&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_1v8&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio0&gt;;</div><div class='add'>+		interrupts = &lt;27 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		gpio-line-names = "PCIE_CLK_PD#", "PMIC_INT#", "ETH_SW_INT#", "",</div><div class='add'>+				  "", "", "", "",</div><div class='add'>+				  "", "GPIO_3V3_1", "GPIO_3V3_2", "",</div><div class='add'>+				  "", "", "", "";</div><div class='add'>+</div><div class='add'>+		/* do not change PCIE_CLK_PD */</div><div class='add'>+		pcie-clk-pd-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+			line-name = "PCIE_CLK_PD#";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmic-int-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			input;</div><div class='add'>+			line-name = "PMIC_INT#";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		eth-sw-int-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			input;</div><div class='add'>+			line-name = "ETH_SW_INT#";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		eth-link-pwrdwn-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			input;</div><div class='add'>+			line-name = "ETH_LINK_PWRDWN#";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* TODO: PFE */</div><div class='add'>+</div><div class='add'>+&amp;sata {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb0 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	hub_2_0: hub@1 {</div><div class='add'>+		compatible = "usb451,8142";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		peer-hub = &lt;&amp;hub_3_0&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio_exp_3p3v 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;reg_vcc_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hub_3_0: hub@2 {</div><div class='add'>+		compatible = "usb451,8140";</div><div class='add'>+		reg = &lt;2&gt;;</div><div class='add'>+		peer-hub = &lt;&amp;hub_2_0&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio_exp_3p3v 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;reg_vcc_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-tqmls1012al.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a-tqmls1012al.dtsi<br/>new file mode 100644<br/>index 000000000000..7c5a3dee91b9<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1012a-tqmls1012al.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls1012a-tqmls1012al.dtsi</a></div><div class='hunk'>@@ -0,0 +1,81 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2018-2025 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Matthias Schiffer</div><div class='add'>+ * Author: Max Merchel</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "fsl-ls1012a.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "tq,ls1012a-tqmls1012al", "fsl,ls1012a";</div><div class='add'>+</div><div class='add'>+	memory@80000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		/*  our minimum RAM config will be 512 MiB */</div><div class='add'>+		reg = &lt;0x00000000 0x80000000 0 0x20000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc_1v8: regulator-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCC_1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc_3v3: regulator-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCC_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	jc42_19: temperature-sensor@19 {</div><div class='add'>+		compatible = "nxp,se97b", "jedec,jc-42.4-temp";</div><div class='add'>+		reg = &lt;0x19&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	m24c64_50: eeprom@50 {</div><div class='add'>+		compatible = "atmel,24c64";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_vcc_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	m24c02_51: eeprom@51 {</div><div class='add'>+		compatible = "nxp,se97b", "atmel,24c02";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+		read-only;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_vcc_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rtc1: rtc@68 {</div><div class='add'>+		compatible = "dallas,ds1339";</div><div class='add'>+		reg = &lt;0x68&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qspi {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;39000000&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;1&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_vcc_1v8&gt;;</div><div class='add'>+</div><div class='add'>+		partitions {</div><div class='add'>+			compatible = "fixed-partitions";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi<br/>index 337919366dc8..ef80bf6a604f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi</a></div><div class='hunk'>@@ -1,11 +1,13 @@</div><div class='ctx'> // SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='ctx'> /*</div><div class='del'>- * Device Tree Include file for Freescale Layerscape-1012A family SoC.</div><div class='add'>+ * Device Tree Include file for NXP Layerscape-1012A family SoC.</div><div class='ctx'>  *</div><div class='ctx'>  * Copyright 2016 Freescale Semiconductor, Inc.</div><div class='add'>+ * Copyright 2019-2020 NXP</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+#include &lt;dt-bindings/clock/fsl,qoriq-clockgen.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/thermal/thermal.h&gt;</div><div class='ctx'> </div><div class='hunk'>@@ -17,6 +19,7 @@</div><div class='ctx'> </div><div class='ctx'> 	aliases {</div><div class='ctx'> 		crypto = &amp;crypto;</div><div class='add'>+		rtc1 = &amp;ftm_alarm0;</div><div class='ctx'> 		rtic-a = &amp;rtic_a;</div><div class='ctx'> 		rtic-b = &amp;rtic_b;</div><div class='ctx'> 		rtic-c = &amp;rtic_c;</div><div class='hunk'>@@ -32,7 +35,7 @@</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			reg = &lt;0x0&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 1 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 0&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 			cpu-idle-states = &lt;&amp;CPU_PH20&gt;;</div><div class='ctx'> 		};</div><div class='hunk'>@@ -71,26 +74,27 @@</div><div class='ctx'> </div><div class='ctx'> 	timer {</div><div class='ctx'> 		compatible = "arm,armv8-timer";</div><div class='del'>-		interrupts = &lt;1 13 IRQ_TYPE_LEVEL_LOW&gt;,/* Physical Secure PPI */</div><div class='del'>-			     &lt;1 14 IRQ_TYPE_LEVEL_LOW&gt;,/* Physical Non-Secure PPI */</div><div class='del'>-			     &lt;1 11 IRQ_TYPE_LEVEL_LOW&gt;,/* Virtual PPI */</div><div class='del'>-			     &lt;1 10 IRQ_TYPE_LEVEL_LOW&gt;;/* Hypervisor PPI */</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 IRQ_TYPE_LEVEL_LOW&gt;,/* Physical Secure PPI */</div><div class='add'>+			     &lt;GIC_PPI 14 IRQ_TYPE_LEVEL_LOW&gt;,/* Physical Non-Secure PPI */</div><div class='add'>+			     &lt;GIC_PPI 11 IRQ_TYPE_LEVEL_LOW&gt;,/* Virtual PPI */</div><div class='add'>+			     &lt;GIC_PPI 10 IRQ_TYPE_LEVEL_LOW&gt;;/* Hypervisor PPI */</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	pmu {</div><div class='del'>-		compatible = "arm,armv8-pmuv3";</div><div class='del'>-		interrupts = &lt;0 106 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		compatible = "arm,cortex-a53-pmu";</div><div class='add'>+		interrupts = &lt;GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	gic: interrupt-controller@1400000 {</div><div class='ctx'> 		compatible = "arm,gic-400";</div><div class='add'>+		#address-cells = &lt;0&gt;;</div><div class='ctx'> 		#interrupt-cells = &lt;3&gt;;</div><div class='ctx'> 		interrupt-controller;</div><div class='ctx'> 		reg = &lt;0x0 0x1401000 0 0x1000&gt;, /* GICD */</div><div class='ctx'> 		      &lt;0x0 0x1402000 0 0x2000&gt;, /* GICC */</div><div class='ctx'> 		      &lt;0x0 0x1404000 0 0x2000&gt;, /* GICH */</div><div class='ctx'> 		      &lt;0x0 0x1406000 0 0x2000&gt;; /* GICV */</div><div class='del'>-		interrupts = &lt;1 9 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	reboot {</div><div class='hunk'>@@ -137,14 +141,30 @@</div><div class='ctx'> 		#size-cells = &lt;2&gt;;</div><div class='ctx'> 		ranges;</div><div class='ctx'> </div><div class='del'>-		esdhc0: esdhc@1560000 {</div><div class='add'>+		qspi: spi@1550000 {</div><div class='add'>+			compatible = "fsl,ls1021a-qspi";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0x0 0x1550000 0x0 0x10000&gt;,</div><div class='add'>+				&lt;0x0 0x40000000 0x0 0x10000000&gt;;</div><div class='add'>+			reg-names = "QuadSPI", "QuadSPI-memory";</div><div class='add'>+			interrupts = &lt;GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clock-names = "qspi_en", "qspi";</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(1)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(1)&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		esdhc0: mmc@1560000 {</div><div class='ctx'> 			compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";</div><div class='ctx'> 			reg = &lt;0x0 0x1560000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 62 0x4&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(1)&gt;;</div><div class='ctx'> 			voltage-ranges = &lt;1800 1800 3300 3300&gt;;</div><div class='ctx'> 			sdhci,auto-cmd12;</div><div class='del'>-			big-endian;</div><div class='ctx'> 			bus-width = &lt;4&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='hunk'>@@ -155,14 +175,14 @@</div><div class='ctx'> 			big-endian;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		esdhc1: esdhc@1580000 {</div><div class='add'>+		esdhc1: mmc@1580000 {</div><div class='ctx'> 			compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";</div><div class='ctx'> 			reg = &lt;0x0 0x1580000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 65 0x4&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(1)&gt;;</div><div class='ctx'> 			voltage-ranges = &lt;1800 1800 3300 3300&gt;;</div><div class='ctx'> 			sdhci,auto-cmd12;</div><div class='del'>-			big-endian;</div><div class='ctx'> 			broken-cd;</div><div class='ctx'> 			bus-width = &lt;4&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='hunk'>@@ -177,12 +197,13 @@</div><div class='ctx'> 			ranges = &lt;0x0 0x00 0x1700000 0x100000&gt;;</div><div class='ctx'> 			reg = &lt;0x00 0x1700000 0x0 0x100000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			dma-coherent;</div><div class='ctx'> </div><div class='ctx'> 			sec_jr0: jr@10000 {</div><div class='ctx'> 				compatible = "fsl,sec-v5.4-job-ring",</div><div class='ctx'> 					     "fsl,sec-v5.0-job-ring",</div><div class='ctx'> 					     "fsl,sec-v4.0-job-ring";</div><div class='del'>-				reg	   = &lt;0x10000 0x10000&gt;;</div><div class='add'>+				reg = &lt;0x10000 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -190,7 +211,7 @@</div><div class='ctx'> 				compatible = "fsl,sec-v5.4-job-ring",</div><div class='ctx'> 					     "fsl,sec-v5.0-job-ring",</div><div class='ctx'> 					     "fsl,sec-v4.0-job-ring";</div><div class='del'>-				reg	   = &lt;0x20000 0x10000&gt;;</div><div class='add'>+				reg = &lt;0x20000 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -198,7 +219,7 @@</div><div class='ctx'> 				compatible = "fsl,sec-v5.4-job-ring",</div><div class='ctx'> 					     "fsl,sec-v5.0-job-ring",</div><div class='ctx'> 					     "fsl,sec-v4.0-job-ring";</div><div class='del'>-				reg	   = &lt;0x30000 0x10000&gt;;</div><div class='add'>+				reg = &lt;0x30000 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -206,7 +227,7 @@</div><div class='ctx'> 				compatible = "fsl,sec-v5.4-job-ring",</div><div class='ctx'> 					     "fsl,sec-v5.0-job-ring",</div><div class='ctx'> 					     "fsl,sec-v4.0-job-ring";</div><div class='del'>-				reg	   = &lt;0x40000 0x10000&gt;;</div><div class='add'>+				reg = &lt;0x40000 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -216,39 +237,47 @@</div><div class='ctx'> 					     "fsl,sec-v4.0-rtic";</div><div class='ctx'> 				#address-cells = &lt;1&gt;;</div><div class='ctx'> 				#size-cells = &lt;1&gt;;</div><div class='del'>-				reg = &lt;0x60000 0x100 0x60e00 0x18&gt;;</div><div class='add'>+				reg = &lt;0x60000 0x100&gt;, &lt;0x60e00 0x18&gt;;</div><div class='ctx'> 				ranges = &lt;0x0 0x60100 0x500&gt;;</div><div class='ctx'> </div><div class='ctx'> 				rtic_a: rtic-a@0 {</div><div class='ctx'> 					compatible = "fsl,sec-v5.4-rtic-memory",</div><div class='ctx'> 						     "fsl,sec-v5.0-rtic-memory",</div><div class='ctx'> 						     "fsl,sec-v4.0-rtic-memory";</div><div class='del'>-					reg = &lt;0x00 0x20 0x100 0x100&gt;;</div><div class='add'>+					reg = &lt;0x00 0x20&gt;, &lt;0x100 0x100&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='ctx'> 				rtic_b: rtic-b@20 {</div><div class='ctx'> 					compatible = "fsl,sec-v5.4-rtic-memory",</div><div class='ctx'> 						     "fsl,sec-v5.0-rtic-memory",</div><div class='ctx'> 						     "fsl,sec-v4.0-rtic-memory";</div><div class='del'>-					reg = &lt;0x20 0x20 0x200 0x100&gt;;</div><div class='add'>+					reg = &lt;0x20 0x20&gt;, &lt;0x200 0x100&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='ctx'> 				rtic_c: rtic-c@40 {</div><div class='ctx'> 					compatible = "fsl,sec-v5.4-rtic-memory",</div><div class='ctx'> 						     "fsl,sec-v5.0-rtic-memory",</div><div class='ctx'> 						     "fsl,sec-v4.0-rtic-memory";</div><div class='del'>-					reg = &lt;0x40 0x20 0x300 0x100&gt;;</div><div class='add'>+					reg = &lt;0x40 0x20&gt;, &lt;0x300 0x100&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='ctx'> 				rtic_d: rtic-d@60 {</div><div class='ctx'> 					compatible = "fsl,sec-v5.4-rtic-memory",</div><div class='ctx'> 						     "fsl,sec-v5.0-rtic-memory",</div><div class='ctx'> 						     "fsl,sec-v4.0-rtic-memory";</div><div class='del'>-					reg = &lt;0x60 0x20 0x400 0x100&gt;;</div><div class='add'>+					reg = &lt;0x60 0x20&gt;, &lt;0x400 0x100&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		sfp: efuse@1e80000 {</div><div class='add'>+			compatible = "fsl,ls1021a-sfp";</div><div class='add'>+			reg = &lt;0x0 0x1e80000 0x0 0x10000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='add'>+			clock-names = "sfp";</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		sec_mon: sec_mon@1e90000 {</div><div class='ctx'> 			compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon",</div><div class='ctx'> 				     "fsl,sec-v4.0-mon";</div><div class='hunk'>@@ -260,7 +289,7 @@</div><div class='ctx'> 		dcfg: dcfg@1ee0000 {</div><div class='ctx'> 			compatible = "fsl,ls1012a-dcfg",</div><div class='ctx'> 				     "syscon";</div><div class='del'>-			reg = &lt;0x0 0x1ee0000 0x0 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x1ee0000 0x0 0x1000&gt;;</div><div class='ctx'> 			big-endian;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -275,65 +304,72 @@</div><div class='ctx'> 		tmu: tmu@1f00000 {</div><div class='ctx'> 			compatible = "fsl,qoriq-tmu";</div><div class='ctx'> 			reg = &lt;0x0 0x1f00000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 33 0x4&gt;;</div><div class='del'>-			fsl,tmu-range = &lt;0xb0000 0x9002a 0x6004c 0x30062&gt;;</div><div class='del'>-			fsl,tmu-calibration = &lt;0x00000000 0x00000026</div><div class='del'>-					       0x00000001 0x0000002d</div><div class='del'>-					       0x00000002 0x00000032</div><div class='del'>-					       0x00000003 0x00000039</div><div class='del'>-					       0x00000004 0x0000003f</div><div class='del'>-					       0x00000005 0x00000046</div><div class='del'>-					       0x00000006 0x0000004d</div><div class='del'>-					       0x00000007 0x00000054</div><div class='del'>-					       0x00000008 0x0000005a</div><div class='del'>-					       0x00000009 0x00000061</div><div class='del'>-					       0x0000000a 0x0000006a</div><div class='del'>-					       0x0000000b 0x00000071</div><div class='del'>-</div><div class='del'>-					       0x00010000 0x00000025</div><div class='del'>-					       0x00010001 0x0000002c</div><div class='del'>-					       0x00010002 0x00000035</div><div class='del'>-					       0x00010003 0x0000003d</div><div class='del'>-					       0x00010004 0x00000045</div><div class='del'>-					       0x00010005 0x0000004e</div><div class='del'>-					       0x00010006 0x00000057</div><div class='del'>-					       0x00010007 0x00000061</div><div class='del'>-					       0x00010008 0x0000006b</div><div class='del'>-					       0x00010009 0x00000076</div><div class='del'>-</div><div class='del'>-					       0x00020000 0x00000029</div><div class='del'>-					       0x00020001 0x00000033</div><div class='del'>-					       0x00020002 0x0000003d</div><div class='del'>-					       0x00020003 0x00000049</div><div class='del'>-					       0x00020004 0x00000056</div><div class='del'>-					       0x00020005 0x00000061</div><div class='del'>-					       0x00020006 0x0000006d</div><div class='del'>-</div><div class='del'>-					       0x00030000 0x00000021</div><div class='del'>-					       0x00030001 0x0000002a</div><div class='del'>-					       0x00030002 0x0000003c</div><div class='del'>-					       0x00030003 0x0000004e&gt;;</div><div class='del'>-			big-endian;</div><div class='add'>+			interrupts = &lt;GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			fsl,tmu-range = &lt;0xb0000 0x9002a 0x6004c 0x60062&gt;;</div><div class='add'>+			fsl,tmu-calibration =</div><div class='add'>+					&lt;0x00000000 0x00000025&gt;,</div><div class='add'>+					&lt;0x00000001 0x0000002c&gt;,</div><div class='add'>+					&lt;0x00000002 0x00000032&gt;,</div><div class='add'>+					&lt;0x00000003 0x00000039&gt;,</div><div class='add'>+					&lt;0x00000004 0x0000003f&gt;,</div><div class='add'>+					&lt;0x00000005 0x00000046&gt;,</div><div class='add'>+					&lt;0x00000006 0x0000004c&gt;,</div><div class='add'>+					&lt;0x00000007 0x00000053&gt;,</div><div class='add'>+					&lt;0x00000008 0x00000059&gt;,</div><div class='add'>+					&lt;0x00000009 0x0000005f&gt;,</div><div class='add'>+					&lt;0x0000000a 0x00000066&gt;,</div><div class='add'>+					&lt;0x0000000b 0x0000006c&gt;,</div><div class='add'>+</div><div class='add'>+					&lt;0x00010000 0x00000026&gt;,</div><div class='add'>+					&lt;0x00010001 0x0000002d&gt;,</div><div class='add'>+					&lt;0x00010002 0x00000035&gt;,</div><div class='add'>+					&lt;0x00010003 0x0000003d&gt;,</div><div class='add'>+					&lt;0x00010004 0x00000045&gt;,</div><div class='add'>+					&lt;0x00010005 0x0000004d&gt;,</div><div class='add'>+					&lt;0x00010006 0x00000055&gt;,</div><div class='add'>+					&lt;0x00010007 0x0000005d&gt;,</div><div class='add'>+					&lt;0x00010008 0x00000065&gt;,</div><div class='add'>+					&lt;0x00010009 0x0000006d&gt;,</div><div class='add'>+</div><div class='add'>+					&lt;0x00020000 0x00000026&gt;,</div><div class='add'>+					&lt;0x00020001 0x00000030&gt;,</div><div class='add'>+					&lt;0x00020002 0x0000003a&gt;,</div><div class='add'>+					&lt;0x00020003 0x00000044&gt;,</div><div class='add'>+					&lt;0x00020004 0x0000004e&gt;,</div><div class='add'>+					&lt;0x00020005 0x00000059&gt;,</div><div class='add'>+					&lt;0x00020006 0x00000063&gt;,</div><div class='add'>+</div><div class='add'>+					&lt;0x00030000 0x00000014&gt;,</div><div class='add'>+					&lt;0x00030001 0x00000021&gt;,</div><div class='add'>+					&lt;0x00030002 0x0000002e&gt;,</div><div class='add'>+					&lt;0x00030003 0x0000003a&gt;,</div><div class='add'>+					&lt;0x00030004 0x00000047&gt;,</div><div class='add'>+					&lt;0x00030005 0x00000053&gt;,</div><div class='add'>+					&lt;0x00030006 0x00000060&gt;;</div><div class='ctx'> 			#thermal-sensor-cells = &lt;1&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		i2c0: i2c@2180000 {</div><div class='del'>-			compatible = "fsl,vf610-i2c";</div><div class='add'>+			compatible = "fsl,ls1012a-i2c", "fsl,vf610-i2c";</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			reg = &lt;0x0 0x2180000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 56 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='add'>+			scl-gpios = &lt;&amp;gpio0 2 0&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		i2c1: i2c@2190000 {</div><div class='del'>-			compatible = "fsl,vf610-i2c";</div><div class='add'>+			compatible = "fsl,ls1012a-i2c", "fsl,vf610-i2c";</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			reg = &lt;0x0 0x2190000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 57 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='add'>+			scl-gpios = &lt;&amp;gpio0 13 0&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -342,9 +378,10 @@</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			reg = &lt;0x0 0x2100000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 64 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clock-names = "dspi";</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(1)&gt;;</div><div class='ctx'> 			spi-num-chipselects = &lt;5&gt;;</div><div class='ctx'> 			big-endian;</div><div class='ctx'> 			status = "disabled";</div><div class='hunk'>@@ -353,23 +390,25 @@</div><div class='ctx'> 		duart0: serial@21c0500 {</div><div class='ctx'> 			compatible = "fsl,ns16550", "ns16550a";</div><div class='ctx'> 			reg = &lt;0x00 0x21c0500 0x0 0x100&gt;;</div><div class='del'>-			interrupts = &lt;0 54 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(1)&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		duart1: serial@21c0600 {</div><div class='ctx'> 			compatible = "fsl,ns16550", "ns16550a";</div><div class='ctx'> 			reg = &lt;0x00 0x21c0600 0x0 0x100&gt;;</div><div class='del'>-			interrupts = &lt;0 54 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(1)&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		gpio0: gpio@2300000 {</div><div class='del'>-			compatible = "fsl,qoriq-gpio";</div><div class='add'>+			compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";</div><div class='ctx'> 			reg = &lt;0x0 0x2300000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 66 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			gpio-controller;</div><div class='ctx'> 			#gpio-cells = &lt;2&gt;;</div><div class='ctx'> 			interrupt-controller;</div><div class='hunk'>@@ -377,21 +416,21 @@</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		gpio1: gpio@2310000 {</div><div class='del'>-			compatible = "fsl,qoriq-gpio";</div><div class='add'>+			compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";</div><div class='ctx'> 			reg = &lt;0x0 0x2310000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 67 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			gpio-controller;</div><div class='ctx'> 			#gpio-cells = &lt;2&gt;;</div><div class='ctx'> 			interrupt-controller;</div><div class='ctx'> 			#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		wdog0: wdog@2ad0000 {</div><div class='add'>+		wdog0: watchdog@2ad0000 {</div><div class='ctx'> 			compatible = "fsl,ls1012a-wdt",</div><div class='ctx'> 				     "fsl,imx21-wdt";</div><div class='ctx'> 			reg = &lt;0x0 0x2ad0000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 83 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(1)&gt;;</div><div class='ctx'> 			big-endian;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -399,13 +438,19 @@</div><div class='ctx'> 			#sound-dai-cells = &lt;0&gt;;</div><div class='ctx'> 			compatible = "fsl,vf610-sai";</div><div class='ctx'> 			reg = &lt;0x0 0x2b50000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 148 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;, &lt;&amp;clockgen 4 3&gt;,</div><div class='del'>-				 &lt;&amp;clockgen 4 3&gt;, &lt;&amp;clockgen 4 3&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='ctx'> 			clock-names = "bus", "mclk1", "mclk2", "mclk3";</div><div class='del'>-			dma-names = "tx", "rx";</div><div class='del'>-			dmas = &lt;&amp;edma0 1 47&gt;,</div><div class='del'>-			       &lt;&amp;edma0 1 46&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+			dmas = &lt;&amp;edma0 1 46&gt;,</div><div class='add'>+			       &lt;&amp;edma0 1 47&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -413,37 +458,46 @@</div><div class='ctx'> 			#sound-dai-cells = &lt;0&gt;;</div><div class='ctx'> 			compatible = "fsl,vf610-sai";</div><div class='ctx'> 			reg = &lt;0x0 0x2b60000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 149 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;, &lt;&amp;clockgen 4 3&gt;,</div><div class='del'>-				 &lt;&amp;clockgen 4 3&gt;, &lt;&amp;clockgen 4 3&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='ctx'> 			clock-names = "bus", "mclk1", "mclk2", "mclk3";</div><div class='del'>-			dma-names = "tx", "rx";</div><div class='del'>-			dmas = &lt;&amp;edma0 1 45&gt;,</div><div class='del'>-			       &lt;&amp;edma0 1 44&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+			dmas = &lt;&amp;edma0 1 44&gt;,</div><div class='add'>+			       &lt;&amp;edma0 1 45&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		edma0: edma@2c00000 {</div><div class='add'>+		edma0: dma-controller@2c00000 {</div><div class='ctx'> 			#dma-cells = &lt;2&gt;;</div><div class='ctx'> 			compatible = "fsl,vf610-edma";</div><div class='ctx'> 			reg = &lt;0x0 0x2c00000 0x0 0x10000&gt;,</div><div class='ctx'> 			      &lt;0x0 0x2c10000 0x0 0x10000&gt;,</div><div class='ctx'> 			      &lt;0x0 0x2c20000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 103 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				     &lt;0 103 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			interrupt-names = "edma-tx", "edma-err";</div><div class='ctx'> 			dma-channels = &lt;32&gt;;</div><div class='ctx'> 			big-endian;</div><div class='ctx'> 			clock-names = "dmamux0", "dmamux1";</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;,</div><div class='del'>-				 &lt;&amp;clockgen 4 3&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		usb0: usb3@2f00000 {</div><div class='del'>-			compatible = "snps,dwc3";</div><div class='add'>+		usb0: usb@2f00000 {</div><div class='add'>+			compatible = "fsl,ls1012a-dwc3", "fsl,ls1028a-dwc3";</div><div class='ctx'> 			reg = &lt;0x0 0x2f00000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 60 0x4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			dr_mode = "host";</div><div class='add'>+			dma-coherent;</div><div class='ctx'> 			snps,quirk-frame-length-adjustment = &lt;0x20&gt;;</div><div class='ctx'> 			snps,dis_rxdet_inp3_quirk;</div><div class='ctx'> 			snps,incr-burst-type-adjustment = &lt;1&gt;, &lt;4&gt;, &lt;8&gt;, &lt;16&gt;;</div><div class='hunk'>@@ -454,16 +508,17 @@</div><div class='ctx'> 			reg = &lt;0x0 0x3200000 0x0 0x10000&gt;,</div><div class='ctx'> 				&lt;0x0 0x20140520 0x0 0x4&gt;;</div><div class='ctx'> 			reg-names = "ahci", "sata-ecc";</div><div class='del'>-			interrupts = &lt;0 69 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(1)&gt;;</div><div class='ctx'> 			dma-coherent;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		usb1: usb2@8600000 {</div><div class='add'>+		usb1: usb@8600000 {</div><div class='ctx'> 			compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";</div><div class='ctx'> 			reg = &lt;0x0 0x8600000 0x0 0x1000&gt;;</div><div class='del'>-			interrupts = &lt;0 139 0x4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			dr_mode = "host";</div><div class='ctx'> 			phy_type = "ulpi";</div><div class='ctx'> 		};</div><div class='hunk'>@@ -472,21 +527,20 @@</div><div class='ctx'> 			compatible = "fsl,ls1012a-msi";</div><div class='ctx'> 			reg = &lt;0x0 0x1572000 0x0 0x8&gt;;</div><div class='ctx'> 			msi-controller;</div><div class='del'>-			interrupts = &lt;0 126 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		pcie: pcie@3400000 {</div><div class='add'>+		pcie1: pcie@3400000 {</div><div class='ctx'> 			compatible = "fsl,ls1012a-pcie";</div><div class='del'>-			reg = &lt;0x00 0x03400000 0x0 0x00100000   /* controller registers */</div><div class='del'>-			       0x40 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='add'>+			reg = &lt;0x00 0x03400000 0x0 0x00100000&gt;, /* controller registers */</div><div class='add'>+			      &lt;0x40 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='ctx'> 			reg-names = "regs", "config";</div><div class='del'>-			interrupts = &lt;0 118 0x4&gt;, /* controller interrupt */</div><div class='del'>-				     &lt;0 117 0x4&gt;; /* PME interrupt */</div><div class='del'>-			interrupt-names = "aer", "pme";</div><div class='add'>+			interrupts = &lt;GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH&gt;, /* PME interrupt */</div><div class='add'>+				     &lt;GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH&gt;; /* controller interrupt */</div><div class='add'>+			interrupt-names = "pme", "aer";</div><div class='ctx'> 			#address-cells = &lt;3&gt;;</div><div class='ctx'> 			#size-cells = &lt;2&gt;;</div><div class='ctx'> 			device_type = "pci";</div><div class='del'>-			num-viewport = &lt;2&gt;;</div><div class='ctx'> 			bus-range = &lt;0x0 0xff&gt;;</div><div class='ctx'> 			ranges = &lt;0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */</div><div class='ctx'> 				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000&gt;; /* non-prefetchable memory */</div><div class='hunk'>@@ -497,8 +551,23 @@</div><div class='ctx'> 					&lt;0000 0 0 2 &amp;gic 0 111 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 					&lt;0000 0 0 3 &amp;gic 0 112 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 					&lt;0000 0 0 4 &amp;gic 0 113 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			big-endian;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='add'>+</div><div class='add'>+		rcpm: wakeup-controller@1ee2140 {</div><div class='add'>+			compatible = "fsl,ls1012a-rcpm", "fsl,qoriq-rcpm-2.1+";</div><div class='add'>+			reg = &lt;0x0 0x1ee2140 0x0 0x4&gt;;</div><div class='add'>+			#fsl,rcpm-wakeup-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ftm_alarm0: rtc@29d0000 {</div><div class='add'>+			compatible = "fsl,ls1012a-ftm-alarm";</div><div class='add'>+			reg = &lt;0x0 0x29d0000 0x0 0x10000&gt;;</div><div class='add'>+			fsl,rcpm-wakeup = &lt;&amp;rcpm 0x20000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			big-endian;</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	firmware {</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dts<br/>index 4b4cc6a1573d..af9194eca556 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dts</a></div><div class='hunk'>@@ -11,11 +11,29 @@</div><div class='ctx'> </div><div class='ctx'> /dts-v1/;</div><div class='ctx'> #include "fsl-ls1028a-kontron-sl28-var4.dts"</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	model = "Kontron KBox A-230-LS";</div><div class='ctx'> 	compatible = "kontron,kbox-a-230-ls", "kontron,sl28-var4",</div><div class='ctx'> 		     "kontron,sl28", "fsl,ls1028a";</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		alarm-led {</div><div class='add'>+			function = LED_FUNCTION_ALARM;</div><div class='add'>+			color = &lt;LED_COLOR_ID_YELLOW&gt;;</div><div class='add'>+			gpios = &lt;&amp;sl28cpld_gpio0 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		power-led {</div><div class='add'>+			linux,default-trigger = "default-on";</div><div class='add'>+			function = LED_FUNCTION_POWER;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			gpios = &lt;&amp;sl28cpld_gpio1 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;enetc_mdio_pf3 {</div><div class='hunk'>@@ -38,6 +56,14 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;enetc_port2 {</div><div class='add'>+	nvmem-cells = &lt;&amp;base_mac_address 2&gt;;</div><div class='add'>+	nvmem-cell-names = "mac-address";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;enetc_port3 {</div><div class='add'>+	nvmem-cells = &lt;&amp;base_mac_address 3&gt;;</div><div class='add'>+	nvmem-cell-names = "mac-address";</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -58,6 +84,8 @@</div><div class='ctx'> 	managed = "in-band-status";</div><div class='ctx'> 	phy-handle = &lt;&amp;qsgmii_phy0&gt;;</div><div class='ctx'> 	phy-mode = "qsgmii";</div><div class='add'>+	nvmem-cells = &lt;&amp;base_mac_address 4&gt;;</div><div class='add'>+	nvmem-cell-names = "mac-address";</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -66,6 +94,8 @@</div><div class='ctx'> 	managed = "in-band-status";</div><div class='ctx'> 	phy-handle = &lt;&amp;qsgmii_phy1&gt;;</div><div class='ctx'> 	phy-mode = "qsgmii";</div><div class='add'>+	nvmem-cells = &lt;&amp;base_mac_address 5&gt;;</div><div class='add'>+	nvmem-cell-names = "mac-address";</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -74,6 +104,8 @@</div><div class='ctx'> 	managed = "in-band-status";</div><div class='ctx'> 	phy-handle = &lt;&amp;qsgmii_phy2&gt;;</div><div class='ctx'> 	phy-mode = "qsgmii";</div><div class='add'>+	nvmem-cells = &lt;&amp;base_mac_address 6&gt;;</div><div class='add'>+	nvmem-cell-names = "mac-address";</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -82,10 +114,19 @@</div><div class='ctx'> 	managed = "in-band-status";</div><div class='ctx'> 	phy-handle = &lt;&amp;qsgmii_phy3&gt;;</div><div class='ctx'> 	phy-mode = "qsgmii";</div><div class='add'>+	nvmem-cells = &lt;&amp;base_mac_address 7&gt;;</div><div class='add'>+	nvmem-cell-names = "mac-address";</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;mscc_felix_port4 {</div><div class='del'>-	ethernet = &lt;&amp;enetc_port2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mscc_felix_port5 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sata {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts<br/>new file mode 100644<br/>index 000000000000..1f34c7553459<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts</a></div><div class='hunk'>@@ -0,0 +1,61 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Device Tree file for the Kontron SMARC-sAL28 board.</div><div class='add'>+ *</div><div class='add'>+ * This is for the network variant 1 which has one ethernet port. It is</div><div class='add'>+ * different than the base variant, which also has one port, but here the</div><div class='add'>+ * port is connected via RGMII. This port is not TSN aware.</div><div class='add'>+ * None of the  four SerDes lanes are used by the module, instead they are</div><div class='add'>+ * all led out to the carrier for customer use.</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) 2021 Michael Walle &lt;michael@walle.cc&gt;</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "fsl-ls1028a-kontron-sl28.dts"</div><div class='add'>+#include &lt;dt-bindings/net/qca-ar803x.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Kontron SMARC-sAL28 (4 Lanes)";</div><div class='add'>+	compatible = "kontron,sl28-var1", "kontron,sl28", "fsl,ls1028a";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;enetc_mdio_pf3 {</div><div class='add'>+	/* Delete unused phy node */</div><div class='add'>+	/delete-node/ ethernet-phy@5;</div><div class='add'>+</div><div class='add'>+	phy0: ethernet-phy@4 {</div><div class='add'>+		reg = &lt;0x4&gt;;</div><div class='add'>+		eee-broken-1000t;</div><div class='add'>+		eee-broken-100tx;</div><div class='add'>+		qca,clk-out-frequency = &lt;125000000&gt;;</div><div class='add'>+		qca,clk-out-strength = &lt;AR803X_STRENGTH_FULL&gt;;</div><div class='add'>+		qca,keep-pll-enabled;</div><div class='add'>+		vddio-supply = &lt;&amp;vddio&gt;;</div><div class='add'>+</div><div class='add'>+		vddio: vddio-regulator {</div><div class='add'>+			regulator-name = "VDDIO";</div><div class='add'>+			regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vddh: vddh-regulator {</div><div class='add'>+			regulator-name = "VDDH";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;enetc_port0 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+	/* Delete the phy-handle to the old phy0 label */</div><div class='add'>+	/delete-property/ phy-handle;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;enetc_port1 {</div><div class='add'>+	phy-handle = &lt;&amp;phy0&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	nvmem-cells = &lt;&amp;base_mac_address 0&gt;;</div><div class='add'>+	nvmem-cell-names = "mac-address";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var2.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var2.dts<br/>index 901b5b161def..aac41192caa1 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var2.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var2.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var2.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var2.dts</a></div><div class='hunk'>@@ -5,7 +5,7 @@</div><div class='ctx'>  * This is for the network variant 2 which has two ethernet ports. These</div><div class='ctx'>  * ports are connected to the internal switch.</div><div class='ctx'>  *</div><div class='del'>- * Copyright (C) 2020 Michael Walle &lt;michael@walle.cc&gt;</div><div class='add'>+ * Copyright (C) 2021 Michael Walle &lt;michael@walle.cc&gt;</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='hunk'>@@ -18,12 +18,6 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;enetc_mdio_pf3 {</div><div class='del'>-	phy0: ethernet-phy@5 {</div><div class='del'>-		reg = &lt;0x5&gt;;</div><div class='del'>-		eee-broken-1000t;</div><div class='del'>-		eee-broken-100tx;</div><div class='del'>-	};</div><div class='del'>-</div><div class='ctx'> 	phy1: ethernet-phy@4 {</div><div class='ctx'> 		reg = &lt;0x4&gt;;</div><div class='ctx'> 		eee-broken-1000t;</div><div class='hunk'>@@ -34,17 +28,22 @@</div><div class='ctx'> &amp;enetc_port0 {</div><div class='ctx'> 	status = "disabled";</div><div class='ctx'> 	/*</div><div class='del'>-	 * In the base device tree the PHY was registered in the mdio</div><div class='del'>-	 * subnode as it is PHY for this port. On this module this PHY</div><div class='del'>-	 * is connected to a switch port instead and registered above.</div><div class='del'>-	 * Therefore, delete the mdio subnode as well as the phy-handle</div><div class='del'>-	 * property here.</div><div class='add'>+	 * In the base device tree the PHY at address 5 was assigned for</div><div class='add'>+	 * this port. On this module this PHY is connected to a switch</div><div class='add'>+	 * port instead. Therefore, delete the phy-handle property here.</div><div class='ctx'> 	 */</div><div class='ctx'> 	/delete-property/ phy-handle;</div><div class='del'>-	/delete-node/ mdio;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;enetc_port2 {</div><div class='add'>+	nvmem-cells = &lt;&amp;base_mac_address 2&gt;;</div><div class='add'>+	nvmem-cell-names = "mac-address";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;enetc_port3 {</div><div class='add'>+	nvmem-cells = &lt;&amp;base_mac_address 3&gt;;</div><div class='add'>+	nvmem-cell-names = "mac-address";</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -53,20 +52,29 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;mscc_felix_port0 {</div><div class='del'>-	label = "gbe0";</div><div class='add'>+	label = "swp0";</div><div class='add'>+	managed = "in-band-status";</div><div class='ctx'> 	phy-handle = &lt;&amp;phy0&gt;;</div><div class='ctx'> 	phy-mode = "sgmii";</div><div class='add'>+	nvmem-cells = &lt;&amp;base_mac_address 0&gt;;</div><div class='add'>+	nvmem-cell-names = "mac-address";</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;mscc_felix_port1 {</div><div class='del'>-	label = "gbe1";</div><div class='add'>+	label = "swp1";</div><div class='add'>+	managed = "in-band-status";</div><div class='ctx'> 	phy-handle = &lt;&amp;phy1&gt;;</div><div class='ctx'> 	phy-mode = "sgmii";</div><div class='add'>+	nvmem-cells = &lt;&amp;base_mac_address 1&gt;;</div><div class='add'>+	nvmem-cell-names = "mac-address";</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;mscc_felix_port4 {</div><div class='del'>-	ethernet = &lt;&amp;enetc_port2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mscc_felix_port5 {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dts<br/>index 0973a6a45217..1d53b529af88 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dts</a></div><div class='hunk'>@@ -8,13 +8,29 @@</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> /dts-v1/;</div><div class='del'>-#include "fsl-ls1028a-kontron-sl28.dts"</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/fsl,qoriq-clockgen.h&gt;</div><div class='add'>+#include "fsl-ls1028a-kontron-sl28-var3.dts"</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	model = "Kontron SMARC-sAL28 (Single PHY) on SMARC Eval 2.0 carrier";</div><div class='ctx'> 	compatible = "kontron,sl28-var3-ads2", "kontron,sl28-var3",</div><div class='ctx'> 		     "kontron,sl28", "fsl,ls1028a";</div><div class='ctx'> </div><div class='add'>+	pwm-fan {</div><div class='add'>+		compatible = "pwm-fan";</div><div class='add'>+		#cooling-cells = &lt;2&gt;;</div><div class='add'>+		pwms = &lt;&amp;sl28cpld_pwm0 0 4000000&gt;;</div><div class='add'>+		cooling-levels = &lt;1 128 192 255&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3p3v: regulator-3p3v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "3P3V";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	sound {</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;0&gt;;</div><div class='hunk'>@@ -96,6 +112,11 @@</div><div class='ctx'> 		clock-names = "mclk";</div><div class='ctx'> 		assigned-clocks = &lt;&amp;mclk&gt;;</div><div class='ctx'> 		assigned-clock-rates = &lt;1250000&gt;;</div><div class='add'>+		AVDD-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='add'>+		CPVDD-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='add'>+		DBVDD-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='add'>+		DCVDD-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='add'>+		MICVDD-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -111,7 +132,8 @@</div><div class='ctx'> 	mclk: clock-mclk@f130080 {</div><div class='ctx'> 		compatible = "fsl,vf610-sai-clock";</div><div class='ctx'> 		reg = &lt;0x0 0xf130080 0x0 0x80&gt;;</div><div class='del'>-		clocks = &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+				    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3.dts<br/>new file mode 100644<br/>index 000000000000..08851ca407a8<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3.dts</a></div><div class='hunk'>@@ -0,0 +1,18 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Device Tree file for the Kontron SMARC-sAL28 board.</div><div class='add'>+ *</div><div class='add'>+ * This is for the network variant 3 which has one ethernet ports.</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) 2024 Michael Walle &lt;michael@walle.cc&gt;</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "fsl-ls1028a-kontron-sl28.dts"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Kontron SMARC-sAL28 (Single PHY)";</div><div class='add'>+	compatible = "kontron,sl28-var3", "kontron,sl28", "fsl,ls1028a";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts<br/>index df212ed5bb94..a4421db3784e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts</a></div><div class='hunk'>@@ -5,7 +5,7 @@</div><div class='ctx'>  * This is for the network variant 4 which has two ethernet ports. It</div><div class='ctx'>  * extends the base and provides one more port connected via RGMII.</div><div class='ctx'>  *</div><div class='del'>- * Copyright (C) 2019 Michael Walle &lt;michael@walle.cc&gt;</div><div class='add'>+ * Copyright (C) 2021 Michael Walle &lt;michael@walle.cc&gt;</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='hunk'>@@ -18,34 +18,32 @@</div><div class='ctx'> 	compatible = "kontron,sl28-var4", "kontron,sl28", "fsl,ls1028a";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;enetc_port1 {</div><div class='del'>-	phy-handle = &lt;&amp;phy1&gt;;</div><div class='del'>-	phy-connection-type = "rgmii-id";</div><div class='del'>-	status = "okay";</div><div class='del'>-</div><div class='del'>-	mdio {</div><div class='del'>-		#address-cells = &lt;1&gt;;</div><div class='del'>-		#size-cells = &lt;0&gt;;</div><div class='del'>-</div><div class='del'>-		phy1: ethernet-phy@4 {</div><div class='del'>-			reg = &lt;0x4&gt;;</div><div class='del'>-			eee-broken-1000t;</div><div class='del'>-			eee-broken-100tx;</div><div class='del'>-</div><div class='del'>-			qca,clk-out-frequency = &lt;125000000&gt;;</div><div class='del'>-			qca,clk-out-strength = &lt;AR803X_STRENGTH_FULL&gt;;</div><div class='del'>-</div><div class='del'>-			vddio-supply = &lt;&amp;vddh&gt;;</div><div class='del'>-</div><div class='del'>-			vddio: vddio-regulator {</div><div class='del'>-				regulator-name = "VDDIO";</div><div class='del'>-				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='del'>-				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='del'>-			};</div><div class='add'>+&amp;enetc_mdio_pf3 {</div><div class='add'>+	phy1: ethernet-phy@4 {</div><div class='add'>+		reg = &lt;0x4&gt;;</div><div class='add'>+		eee-broken-1000t;</div><div class='add'>+		eee-broken-100tx;</div><div class='add'>+		qca,clk-out-frequency = &lt;125000000&gt;;</div><div class='add'>+		qca,clk-out-strength = &lt;AR803X_STRENGTH_FULL&gt;;</div><div class='add'>+		qca,keep-pll-enabled;</div><div class='add'>+		vddio-supply = &lt;&amp;vddio&gt;;</div><div class='add'>+</div><div class='add'>+		vddio: vddio-regulator {</div><div class='add'>+			regulator-name = "VDDIO";</div><div class='add'>+			regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		};</div><div class='ctx'> </div><div class='del'>-			vddh: vddh-regulator {</div><div class='del'>-				regulator-name = "VDDH";</div><div class='del'>-			};</div><div class='add'>+		vddh: vddh-regulator {</div><div class='add'>+			regulator-name = "VDDH";</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='add'>+</div><div class='add'>+&amp;enetc_port1 {</div><div class='add'>+	phy-handle = &lt;&amp;phy1&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	nvmem-cells = &lt;&amp;base_mac_address 1&gt;;</div><div class='add'>+	nvmem-cell-names = "mac-address";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts<br/>index 1648a04ea79f..8b65af4a7147 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts</a></div><div class='hunk'>@@ -2,12 +2,15 @@</div><div class='ctx'> /*</div><div class='ctx'>  * Device Tree file for the Kontron SMARC-sAL28 board.</div><div class='ctx'>  *</div><div class='del'>- * Copyright (C) 2019 Michael Walle &lt;michael@walle.cc&gt;</div><div class='add'>+ * Copyright (C) 2021 Michael Walle &lt;michael@walle.cc&gt;</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> /dts-v1/;</div><div class='ctx'> #include "fsl-ls1028a.dtsi"</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	model = "Kontron SMARC-sAL28";</div><div class='hunk'>@@ -17,8 +20,43 @@</div><div class='ctx'> 		crypto = &amp;crypto;</div><div class='ctx'> 		serial0 = &amp;duart0;</div><div class='ctx'> 		serial1 = &amp;duart1;</div><div class='add'>+		serial2 = &amp;lpuart1;</div><div class='ctx'> 		spi0 = &amp;fspi;</div><div class='ctx'> 		spi1 = &amp;dspi2;</div><div class='add'>+		mmc0 = &amp;esdhc1;</div><div class='add'>+		mmc1 = &amp;esdhc;</div><div class='add'>+		rtc0 = &amp;rtc;</div><div class='add'>+		rtc1 = &amp;ftm_alarm0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	buttons0 {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		power-button {</div><div class='add'>+			interrupts-extended = &lt;&amp;sl28cpld_intc</div><div class='add'>+					       4 IRQ_TYPE_EDGE_BOTH&gt;;</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+			label = "Power";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sleep-button {</div><div class='add'>+			interrupts-extended = &lt;&amp;sl28cpld_intc</div><div class='add'>+					       5 IRQ_TYPE_EDGE_BOTH&gt;;</div><div class='add'>+			linux,code = &lt;KEY_SLEEP&gt;;</div><div class='add'>+			label = "Sleep";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	buttons1 {</div><div class='add'>+		compatible = "gpio-keys-polled";</div><div class='add'>+		poll-interval = &lt;200&gt;;</div><div class='add'>+</div><div class='add'>+		lid-switch {</div><div class='add'>+			linux,input-type = &lt;EV_SW&gt;;</div><div class='add'>+			linux,code = &lt;SW_LID&gt;;</div><div class='add'>+			gpios = &lt;&amp;sl28cpld_gpio3 4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			label = "Lid";</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	chosen {</div><div class='hunk'>@@ -26,6 +64,10 @@</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;can0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;dspi2 {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='hunk'>@@ -38,21 +80,21 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;enetc_mdio_pf3 {</div><div class='add'>+	phy0: ethernet-phy@5 {</div><div class='add'>+		reg = &lt;0x5&gt;;</div><div class='add'>+		eee-broken-1000t;</div><div class='add'>+		eee-broken-100tx;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;enetc_port0 {</div><div class='ctx'> 	phy-handle = &lt;&amp;phy0&gt;;</div><div class='del'>-	phy-connection-type = "sgmii";</div><div class='add'>+	phy-mode = "sgmii";</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	nvmem-cells = &lt;&amp;base_mac_address 0&gt;;</div><div class='add'>+	nvmem-cell-names = "mac-address";</div><div class='ctx'> 	status = "okay";</div><div class='del'>-</div><div class='del'>-	mdio {</div><div class='del'>-		#address-cells = &lt;1&gt;;</div><div class='del'>-		#size-cells = &lt;0&gt;;</div><div class='del'>-</div><div class='del'>-		phy0: ethernet-phy@5 {</div><div class='del'>-			reg = &lt;0x5&gt;;</div><div class='del'>-			eee-broken-1000t;</div><div class='del'>-			eee-broken-100tx;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;esdhc {</div><div class='hunk'>@@ -74,8 +116,6 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='ctx'> 	flash@0 {</div><div class='del'>-		#address-cells = &lt;1&gt;;</div><div class='del'>-		#size-cells = &lt;1&gt;;</div><div class='ctx'> 		compatible = "jedec,spi-nor";</div><div class='ctx'> 		m25p,fast-read;</div><div class='ctx'> 		spi-max-frequency = &lt;133000000&gt;;</div><div class='hunk'>@@ -84,63 +124,60 @@</div><div class='ctx'> 		spi-rx-bus-width = &lt;2&gt;; /* 2 SPI Rx lines */</div><div class='ctx'> 		spi-tx-bus-width = &lt;1&gt;; /* 1 SPI Tx line */</div><div class='ctx'> </div><div class='del'>-		partition@0 {</div><div class='del'>-			reg = &lt;0x000000 0x010000&gt;;</div><div class='del'>-			label = "rcw";</div><div class='del'>-			read-only;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		partition@10000 {</div><div class='del'>-			reg = &lt;0x010000 0x0f0000&gt;;</div><div class='del'>-			label = "failsafe bootloader";</div><div class='del'>-			read-only;</div><div class='add'>+		partitions {</div><div class='add'>+			compatible = "fixed-partitions";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			partition@0 {</div><div class='add'>+				reg = &lt;0x000000 0x010000&gt;;</div><div class='add'>+				label = "rcw";</div><div class='add'>+				read-only;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			partition@10000 {</div><div class='add'>+				reg = &lt;0x010000 0x1d0000&gt;;</div><div class='add'>+				label = "failsafe bootloader";</div><div class='add'>+				read-only;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			partition@200000 {</div><div class='add'>+				reg = &lt;0x200000 0x010000&gt;;</div><div class='add'>+				label = "configuration store";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			partition@210000 {</div><div class='add'>+				reg = &lt;0x210000 0x1d0000&gt;;</div><div class='add'>+				label = "bootloader";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			partition@3e0000 {</div><div class='add'>+				reg = &lt;0x3e0000 0x020000&gt;;</div><div class='add'>+				label = "bootloader environment";</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		partition@100000 {</div><div class='del'>-			reg = &lt;0x100000 0x040000&gt;;</div><div class='del'>-			label = "failsafe DP firmware";</div><div class='del'>-			read-only;</div><div class='del'>-		};</div><div class='add'>+		otp-1 {</div><div class='add'>+			compatible = "user-otp";</div><div class='ctx'> </div><div class='del'>-		partition@140000 {</div><div class='del'>-			reg = &lt;0x140000 0x0a0000&gt;;</div><div class='del'>-			label = "failsafe trusted firmware";</div><div class='del'>-			read-only;</div><div class='del'>-		};</div><div class='add'>+			nvmem-layout {</div><div class='add'>+				compatible = "kontron,sl28-vpd";</div><div class='ctx'> </div><div class='del'>-		partition@1e0000 {</div><div class='del'>-			reg = &lt;0x1e0000 0x020000&gt;;</div><div class='del'>-			label = "reserved";</div><div class='del'>-			read-only;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		partition@200000 {</div><div class='del'>-			reg = &lt;0x200000 0x010000&gt;;</div><div class='del'>-			label = "configuration store";</div><div class='del'>-		};</div><div class='add'>+				serial_number: serial-number {</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-		partition@210000 {</div><div class='del'>-			reg = &lt;0x210000 0x0f0000&gt;;</div><div class='del'>-			label = "bootloader";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		partition@300000 {</div><div class='del'>-			reg = &lt;0x300000 0x040000&gt;;</div><div class='del'>-			label = "DP firmware";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		partition@340000 {</div><div class='del'>-			reg = &lt;0x340000 0x0a0000&gt;;</div><div class='del'>-			label = "trusted firmware";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		partition@3e0000 {</div><div class='del'>-			reg = &lt;0x3e0000 0x020000&gt;;</div><div class='del'>-			label = "bootloader environment";</div><div class='add'>+				base_mac_address: base-mac-address {</div><div class='add'>+					#nvmem-cell-cells = &lt;1&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;ftm_alarm0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;gpio1 {</div><div class='ctx'> 	gpio-line-names =</div><div class='ctx'> 		"", "", "", "", "", "", "", "",</div><div class='hunk'>@@ -160,11 +197,112 @@</div><div class='ctx'> &amp;i2c0 {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='del'>-	rtc@32 {</div><div class='add'>+	rtc: rtc@32 {</div><div class='ctx'> 		compatible = "microcrystal,rv8803";</div><div class='ctx'> 		reg = &lt;0x32&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	sl28cpld@4a {</div><div class='add'>+		compatible = "kontron,sl28cpld";</div><div class='add'>+		reg = &lt;0x4a&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		watchdog@4 {</div><div class='add'>+			compatible = "kontron,sl28cpld-wdt";</div><div class='add'>+			reg = &lt;0x4&gt;;</div><div class='add'>+			kontron,assert-wdt-timeout-pin;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		hwmon@b {</div><div class='add'>+			compatible = "kontron,sl28cpld-fan";</div><div class='add'>+			reg = &lt;0xb&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sl28cpld_pwm0: pwm@c {</div><div class='add'>+			compatible = "kontron,sl28cpld-pwm";</div><div class='add'>+			reg = &lt;0xc&gt;;</div><div class='add'>+			#pwm-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sl28cpld_pwm1: pwm@e {</div><div class='add'>+			compatible = "kontron,sl28cpld-pwm";</div><div class='add'>+			reg = &lt;0xe&gt;;</div><div class='add'>+			#pwm-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sl28cpld_gpio0: gpio@10 {</div><div class='add'>+			compatible = "kontron,sl28cpld-gpio";</div><div class='add'>+			reg = &lt;0x10&gt;;</div><div class='add'>+			interrupts-extended = &lt;&amp;gpio2 6</div><div class='add'>+					       IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-line-names =</div><div class='add'>+				"GPIO0_CAM0_PWR_N", "GPIO1_CAM1_PWR_N",</div><div class='add'>+				"GPIO2_CAM0_RST_N", "GPIO3_CAM1_RST_N",</div><div class='add'>+				"GPIO4_HDA_RST_N", "GPIO5_PWM_OUT",</div><div class='add'>+				"GPIO6_TACHIN", "GPIO7";</div><div class='add'>+</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sl28cpld_gpio1: gpio@15 {</div><div class='add'>+			compatible = "kontron,sl28cpld-gpio";</div><div class='add'>+			reg = &lt;0x15&gt;;</div><div class='add'>+			interrupts-extended = &lt;&amp;gpio2 6</div><div class='add'>+					       IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-line-names =</div><div class='add'>+				"GPIO8", "GPIO9", "GPIO10", "GPIO11",</div><div class='add'>+				"", "", "", "";</div><div class='add'>+</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sl28cpld_gpio2: gpio@1a {</div><div class='add'>+			compatible = "kontron,sl28cpld-gpo";</div><div class='add'>+			reg = &lt;0x1a&gt;;</div><div class='add'>+</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-line-names =</div><div class='add'>+				"LCD0 voltage enable",</div><div class='add'>+				"LCD0 backlight enable",</div><div class='add'>+				"eMMC reset", "LVDS bridge reset",</div><div class='add'>+				"LVDS bridge power-down",</div><div class='add'>+				"SDIO power enable",</div><div class='add'>+				"", "";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sl28cpld_gpio3: gpio@1b {</div><div class='add'>+			compatible = "kontron,sl28cpld-gpi";</div><div class='add'>+			reg = &lt;0x1b&gt;;</div><div class='add'>+</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-line-names =</div><div class='add'>+				"Power button", "Force recovery", "Sleep",</div><div class='add'>+				"Battery low", "Lid state", "Charging",</div><div class='add'>+				"Charger present", "";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sl28cpld_intc: interrupt-controller@1c {</div><div class='add'>+			compatible = "kontron,sl28cpld-intc";</div><div class='add'>+			reg = &lt;0x1c&gt;;</div><div class='add'>+			interrupts-extended = &lt;&amp;gpio2 6</div><div class='add'>+					       IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	eeprom@50 {</div><div class='ctx'> 		compatible = "atmel,24c32";</div><div class='ctx'> 		reg = &lt;0x50&gt;;</div><div class='hunk'>@@ -185,3 +323,24 @@</div><div class='ctx'> 		pagesize = &lt;32&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='add'>+</div><div class='add'>+&amp;lpuart1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mscc_felix_port4 {</div><div class='add'>+	dsa-tag-protocol = "ocelot-8021q";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mscc_felix_port5 {</div><div class='add'>+	dsa-tag-protocol = "ocelot-8021q";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb1 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dtso b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dtso<br/>new file mode 100644<br/>index 000000000000..f826392c23fa<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dtso</a></div><div class='hunk'>@@ -0,0 +1,91 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Device Tree fragment for LS1028A QDS board, serdes 13bb</div><div class='add'>+ *</div><div class='add'>+ * Copyright 2019-2021 NXP</div><div class='add'>+ *</div><div class='add'>+ * Requires a LS1028A QDS board with lane B rework.</div><div class='add'>+ * Requires a SCH-30841 card with lane A of connector rewired to PHY lane C.</div><div class='add'>+ * Set-up is a SCH-30842 card in slot 1 and SCH-30841 in slot 2.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+&amp;mdio_slot1 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	slot1_sgmii: ethernet-phy@2 {</div><div class='add'>+		/* AQR112 */</div><div class='add'>+		reg = &lt;0x2&gt;;</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;enetc_port0 {</div><div class='add'>+	phy-handle = &lt;&amp;slot1_sgmii&gt;;</div><div class='add'>+	phy-mode = "usxgmii";</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdio_slot2 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	/* 4 ports on AQR412 */</div><div class='add'>+	slot2_qxgmii0: ethernet-phy@0 {</div><div class='add'>+		reg = &lt;0x0&gt;;</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	slot2_qxgmii1: ethernet-phy@1 {</div><div class='add'>+		reg = &lt;0x1&gt;;</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	slot2_qxgmii2: ethernet-phy@2 {</div><div class='add'>+		reg = &lt;0x2&gt;;</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	slot2_qxgmii3: ethernet-phy@3 {</div><div class='add'>+		reg = &lt;0x3&gt;;</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mscc_felix_ports {</div><div class='add'>+	port@0 {</div><div class='add'>+		status = "okay";</div><div class='add'>+		phy-handle = &lt;&amp;slot2_qxgmii0&gt;;</div><div class='add'>+		phy-mode = "usxgmii";</div><div class='add'>+		managed = "in-band-status";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	port@1 {</div><div class='add'>+		status = "okay";</div><div class='add'>+		phy-handle = &lt;&amp;slot2_qxgmii1&gt;;</div><div class='add'>+		phy-mode = "usxgmii";</div><div class='add'>+		managed = "in-band-status";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	port@2 {</div><div class='add'>+		status = "okay";</div><div class='add'>+		phy-handle = &lt;&amp;slot2_qxgmii2&gt;;</div><div class='add'>+		phy-mode = "usxgmii";</div><div class='add'>+		managed = "in-band-status";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	port@3 {</div><div class='add'>+		status = "okay";</div><div class='add'>+		phy-handle = &lt;&amp;slot2_qxgmii3&gt;;</div><div class='add'>+		phy-mode = "usxgmii";</div><div class='add'>+		managed = "in-band-status";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mscc_felix {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dtso b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dtso<br/>new file mode 100644<br/>index 000000000000..b949cac03742<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dtso</a></div><div class='hunk'>@@ -0,0 +1,85 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Device Tree fragment for LS1028A QDS board, serdes 69xx</div><div class='add'>+ *</div><div class='add'>+ * Copyright 2019-2021 NXP</div><div class='add'>+ *</div><div class='add'>+ * Requires a LS1028A QDS board with lane B rework.</div><div class='add'>+ * Requires a SCH-30842 card in slot 1 and a SCH-28021 card in slot 2.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+&amp;mdio_slot1 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	slot1_sgmii: ethernet-phy@2 {</div><div class='add'>+		/* AQR112 */</div><div class='add'>+		reg = &lt;0x2&gt;;</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;enetc_port0 {</div><div class='add'>+	phy-handle = &lt;&amp;slot1_sgmii&gt;;</div><div class='add'>+	phy-mode = "2500base-x";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdio_slot2 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	/* 4 ports on VSC8514 */</div><div class='add'>+	slot2_qsgmii0: ethernet-phy@8 {</div><div class='add'>+		reg = &lt;0x8&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	slot2_qsgmii1: ethernet-phy@9 {</div><div class='add'>+		reg = &lt;0x9&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	slot2_qsgmii2: ethernet-phy@a {</div><div class='add'>+		reg = &lt;0xa&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	slot2_qsgmii3: ethernet-phy@b {</div><div class='add'>+		reg = &lt;0xb&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mscc_felix_ports {</div><div class='add'>+	port@0 {</div><div class='add'>+		status = "okay";</div><div class='add'>+		phy-handle = &lt;&amp;slot2_qsgmii0&gt;;</div><div class='add'>+		phy-mode = "qsgmii";</div><div class='add'>+		managed = "in-band-status";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	port@1 {</div><div class='add'>+		status = "okay";</div><div class='add'>+		phy-handle = &lt;&amp;slot2_qsgmii1&gt;;</div><div class='add'>+		phy-mode = "qsgmii";</div><div class='add'>+		managed = "in-band-status";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	port@2 {</div><div class='add'>+		status = "okay";</div><div class='add'>+		phy-handle = &lt;&amp;slot2_qsgmii2&gt;;</div><div class='add'>+		phy-mode = "qsgmii";</div><div class='add'>+		managed = "in-band-status";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	port@3 {</div><div class='add'>+		status = "okay";</div><div class='add'>+		phy-handle = &lt;&amp;slot2_qsgmii3&gt;;</div><div class='add'>+		phy-mode = "qsgmii";</div><div class='add'>+		managed = "in-band-status";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mscc_felix {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dtso b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dtso<br/>new file mode 100644<br/>index 000000000000..1dff68d7484b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dtso</a></div><div class='hunk'>@@ -0,0 +1,69 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Device Tree fragment for LS1028A QDS board, serdes 7777</div><div class='add'>+ *</div><div class='add'>+ * Copyright 2019-2021 NXP</div><div class='add'>+ *</div><div class='add'>+ * Requires a LS1028A QDS board without lane B rework.</div><div class='add'>+ * Requires a SCH-30841 card without lane A/C rewire and with a FW with muxing</div><div class='add'>+ * disabled, plugged in slot 1.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+&amp;mdio_slot1 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	/* 4 ports on AQR412 */</div><div class='add'>+	slot1_sxgmii0: ethernet-phy@0 {</div><div class='add'>+		reg = &lt;0x0&gt;;</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	slot1_sxgmii1: ethernet-phy@1 {</div><div class='add'>+		reg = &lt;0x1&gt;;</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	slot1_sxgmii2: ethernet-phy@2 {</div><div class='add'>+		reg = &lt;0x2&gt;;</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	slot1_sxgmii3: ethernet-phy@3 {</div><div class='add'>+		reg = &lt;0x3&gt;;</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mscc_felix_ports {</div><div class='add'>+	port@0 {</div><div class='add'>+		status = "okay";</div><div class='add'>+		phy-handle = &lt;&amp;slot1_sxgmii0&gt;;</div><div class='add'>+		phy-mode = "2500base-x";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	port@1 {</div><div class='add'>+		status = "okay";</div><div class='add'>+		phy-handle = &lt;&amp;slot1_sxgmii1&gt;;</div><div class='add'>+		phy-mode = "2500base-x";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	port@2 {</div><div class='add'>+		status = "okay";</div><div class='add'>+		phy-handle = &lt;&amp;slot1_sxgmii2&gt;;</div><div class='add'>+		phy-mode = "2500base-x";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	port@3 {</div><div class='add'>+		status = "okay";</div><div class='add'>+		phy-handle = &lt;&amp;slot1_sxgmii3&gt;;</div><div class='add'>+		phy-mode = "2500base-x";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mscc_felix {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dtso b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dtso<br/>new file mode 100644<br/>index 000000000000..19424d349713<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dtso</a></div><div class='hunk'>@@ -0,0 +1,85 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Device Tree fragment for LS1028A QDS board, serdes 85bb</div><div class='add'>+ *</div><div class='add'>+ * Copyright 2019-2021 NXP</div><div class='add'>+ *</div><div class='add'>+ * Requires a LS1028A QDS board with lane B rework.</div><div class='add'>+ * Requires a SCH-24801 card in slot 1 and a SCH-28021 card in slot 2.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+&amp;mdio_slot1 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	slot1_sgmii: ethernet-phy@1c {</div><div class='add'>+		/* 1st port on VSC8234 */</div><div class='add'>+		reg = &lt;0x1c&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;enetc_port0 {</div><div class='add'>+	phy-handle = &lt;&amp;slot1_sgmii&gt;;</div><div class='add'>+	phy-mode = "sgmii";</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdio_slot2 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	/* 4 ports on VSC8514 */</div><div class='add'>+	slot2_qsgmii0: ethernet-phy@8 {</div><div class='add'>+		reg = &lt;0x8&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	slot2_qsgmii1: ethernet-phy@9 {</div><div class='add'>+		reg = &lt;0x9&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	slot2_qsgmii2: ethernet-phy@a {</div><div class='add'>+		reg = &lt;0xa&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	slot2_qsgmii3: ethernet-phy@b {</div><div class='add'>+		reg = &lt;0xb&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mscc_felix_ports {</div><div class='add'>+	port@0 {</div><div class='add'>+		status = "okay";</div><div class='add'>+		phy-handle = &lt;&amp;slot2_qsgmii0&gt;;</div><div class='add'>+		phy-mode = "qsgmii";</div><div class='add'>+		managed = "in-band-status";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	port@1 {</div><div class='add'>+		status = "okay";</div><div class='add'>+		phy-handle = &lt;&amp;slot2_qsgmii1&gt;;</div><div class='add'>+		phy-mode = "qsgmii";</div><div class='add'>+		managed = "in-band-status";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	port@2 {</div><div class='add'>+		status = "okay";</div><div class='add'>+		phy-handle = &lt;&amp;slot2_qsgmii2&gt;;</div><div class='add'>+		phy-mode = "qsgmii";</div><div class='add'>+		managed = "in-band-status";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	port@3 {</div><div class='add'>+		status = "okay";</div><div class='add'>+		phy-handle = &lt;&amp;slot2_qsgmii3&gt;;</div><div class='add'>+		phy-mode = "qsgmii";</div><div class='add'>+		managed = "in-band-status";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mscc_felix {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dtso b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dtso<br/>new file mode 100644<br/>index 000000000000..fb85847f778f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dtso</a></div><div class='hunk'>@@ -0,0 +1,61 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Device Tree fragment for LS1028A QDS board, serdes 85xx</div><div class='add'>+ *</div><div class='add'>+ * Copyright 2019-2021 NXP</div><div class='add'>+ *</div><div class='add'>+ * Requires a LS1028A QDS board without lane B rework.</div><div class='add'>+ * Requires a SCH-24801 card in slot 1.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+&amp;mdio_slot1 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	/* VSC8234 */</div><div class='add'>+	slot1_sgmii0: ethernet-phy@1c {</div><div class='add'>+		reg = &lt;0x1c&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	slot1_sgmii1: ethernet-phy@1d {</div><div class='add'>+		reg = &lt;0x1d&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	slot1_sgmii2: ethernet-phy@1e {</div><div class='add'>+		reg = &lt;0x1e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	slot1_sgmii3: ethernet-phy@1f {</div><div class='add'>+		reg = &lt;0x1f&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;enetc_port0 {</div><div class='add'>+	phy-handle = &lt;&amp;slot1_sgmii0&gt;;</div><div class='add'>+	phy-mode = "sgmii";</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mscc_felix_ports {</div><div class='add'>+	port@1 {</div><div class='add'>+		status = "okay";</div><div class='add'>+		phy-handle = &lt;&amp;slot1_sgmii1&gt;;</div><div class='add'>+		phy-mode = "sgmii";</div><div class='add'>+		managed = "in-band-status";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	port@2 {</div><div class='add'>+		status = "okay";</div><div class='add'>+		phy-handle = &lt;&amp;slot1_sgmii2&gt;;</div><div class='add'>+		phy-mode = "sgmii";</div><div class='add'>+		managed = "in-band-status";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mscc_felix {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dtso b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dtso<br/>new file mode 100644<br/>index 000000000000..63e46fad22bd<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dtso</a></div><div class='hunk'>@@ -0,0 +1,68 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Device Tree fragment for LS1028A QDS board, serdes 85xx</div><div class='add'>+ *</div><div class='add'>+ * Copyright 2019-2021 NXP</div><div class='add'>+ *</div><div class='add'>+ * Requires a LS1028A QDS board without lane B rework.</div><div class='add'>+ * Requires a SCH-24801 card in slot 1.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+&amp;mdio_slot1 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	/* VSC8234 */</div><div class='add'>+	slot1_sgmii0: ethernet-phy@1c {</div><div class='add'>+		reg = &lt;0x1c&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	slot1_sgmii1: ethernet-phy@1d {</div><div class='add'>+		reg = &lt;0x1d&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	slot1_sgmii2: ethernet-phy@1e {</div><div class='add'>+		reg = &lt;0x1e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	slot1_sgmii3: ethernet-phy@1f {</div><div class='add'>+		reg = &lt;0x1f&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mscc_felix_ports {</div><div class='add'>+	port@0 {</div><div class='add'>+		status = "okay";</div><div class='add'>+		phy-handle = &lt;&amp;slot1_sgmii0&gt;;</div><div class='add'>+		phy-mode = "sgmii";</div><div class='add'>+		managed = "in-band-status";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	port@1 {</div><div class='add'>+		status = "okay";</div><div class='add'>+		phy-handle = &lt;&amp;slot1_sgmii1&gt;;</div><div class='add'>+		phy-mode = "sgmii";</div><div class='add'>+		managed = "in-band-status";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	port@2 {</div><div class='add'>+		status = "okay";</div><div class='add'>+		phy-handle = &lt;&amp;slot1_sgmii2&gt;;</div><div class='add'>+		phy-mode = "sgmii";</div><div class='add'>+		managed = "in-band-status";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	port@3 {</div><div class='add'>+		status = "okay";</div><div class='add'>+		phy-handle = &lt;&amp;slot1_sgmii3&gt;;</div><div class='add'>+		phy-mode = "sgmii";</div><div class='add'>+		managed = "in-band-status";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mscc_felix {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts<br/>index dd69c5b821e9..0bb2f28a0441 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts</a></div><div class='hunk'>@@ -23,6 +23,9 @@</div><div class='ctx'> 		gpio2 = &amp;gpio3;</div><div class='ctx'> 		serial0 = &amp;duart0;</div><div class='ctx'> 		serial1 = &amp;duart1;</div><div class='add'>+		mmc0 = &amp;esdhc;</div><div class='add'>+		mmc1 = &amp;esdhc1;</div><div class='add'>+		rtc1 = &amp;ftm_alarm1;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	chosen {</div><div class='hunk'>@@ -90,7 +93,7 @@</div><div class='ctx'> 		compatible = "mdio-mux-multiplexer";</div><div class='ctx'> 		mux-controls = &lt;&amp;mux 0&gt;;</div><div class='ctx'> 		mdio-parent-bus = &lt;&amp;enetc_mdio_pf3&gt;;</div><div class='del'>-		#address-cells=&lt;1&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;0&gt;;</div><div class='ctx'> </div><div class='ctx'> 		/* on-board RGMII PHY */</div><div class='hunk'>@@ -104,6 +107,123 @@</div><div class='ctx'> 				reg = &lt;5&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='add'>+</div><div class='add'>+		mdio_slot1: mdio@4 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;4&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio_slot2: mdio@5 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;5&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio_slot3: mdio@6 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;6&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio_slot4: mdio@7 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;7&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;can0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;can1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dspi0 {</div><div class='add'>+	bus-num = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash@0 {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		spi-cpol;</div><div class='add'>+		spi-cpha;</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;10000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	flash@1 {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		spi-cpol;</div><div class='add'>+		spi-cpha;</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		spi-max-frequency = &lt;10000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	flash@2 {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		spi-cpol;</div><div class='add'>+		spi-cpha;</div><div class='add'>+		reg = &lt;2&gt;;</div><div class='add'>+		spi-max-frequency = &lt;10000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dspi1 {</div><div class='add'>+	bus-num = &lt;1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash@0 {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		spi-cpol;</div><div class='add'>+		spi-cpha;</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;10000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	flash@1 {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		spi-cpol;</div><div class='add'>+		spi-cpha;</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		spi-max-frequency = &lt;10000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	flash@2 {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		spi-cpol;</div><div class='add'>+		spi-cpha;</div><div class='add'>+		reg = &lt;2&gt;;</div><div class='add'>+		spi-max-frequency = &lt;10000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dspi2 {</div><div class='add'>+	bus-num = &lt;2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash@0 {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		spi-cpol;</div><div class='add'>+		spi-cpha;</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;10000000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -115,6 +235,16 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;enetc_port1 {</div><div class='add'>+	phy-handle = &lt;&amp;qds_phy1&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;enetc_port2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;esdhc {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='hunk'>@@ -138,6 +268,10 @@</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;ftm_alarm1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;i2c0 {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='hunk'>@@ -176,11 +310,6 @@</div><div class='ctx'> 				vcc-supply = &lt;&amp;sb_3v3&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			rtc@51 {</div><div class='del'>-				compatible = "nxp,pcf2129";</div><div class='del'>-				reg = &lt;0x51&gt;;</div><div class='del'>-			};</div><div class='del'>-</div><div class='ctx'> 			eeprom@56 {</div><div class='ctx'> 				compatible = "atmel,24c512";</div><div class='ctx'> 				reg = &lt;0x56&gt;;</div><div class='hunk'>@@ -222,9 +351,25 @@</div><div class='ctx'> </div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;enetc_port1 {</div><div class='del'>-	phy-handle = &lt;&amp;qds_phy1&gt;;</div><div class='del'>-	phy-connection-type = "rgmii-id";</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	rtc@51 {</div><div class='add'>+		compatible = "nxp,pcf2129";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mscc_felix_port4 {</div><div class='add'>+	ethernet = &lt;&amp;enetc_port2&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -235,3 +380,13 @@</div><div class='ctx'> &amp;sata {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='add'>+</div><div class='add'>+&amp;usb0 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb1 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts<br/>index c2dc1232f93f..757a34ba7da3 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts</a></div><div class='hunk'>@@ -2,7 +2,7 @@</div><div class='ctx'> /*</div><div class='ctx'>  * Device Tree file for NXP LS1028A RDB Board.</div><div class='ctx'>  *</div><div class='del'>- * Copyright 2018 NXP</div><div class='add'>+ * Copyright 2018-2021 NXP</div><div class='ctx'>  *</div><div class='ctx'>  * Harninder Rai &lt;harninder.rai@nxp.com&gt;</div><div class='ctx'>  *</div><div class='hunk'>@@ -19,6 +19,19 @@</div><div class='ctx'> 		crypto = &amp;crypto;</div><div class='ctx'> 		serial0 = &amp;duart0;</div><div class='ctx'> 		serial1 = &amp;duart1;</div><div class='add'>+		mmc0 = &amp;esdhc;</div><div class='add'>+		mmc1 = &amp;esdhc1;</div><div class='add'>+		rtc1 = &amp;ftm_alarm1;</div><div class='add'>+		spi0 = &amp;fspi;</div><div class='add'>+		ethernet0 = &amp;enetc_port0;</div><div class='add'>+		ethernet1 = &amp;enetc_port2;</div><div class='add'>+		ethernet2 = &amp;mscc_felix_port0;</div><div class='add'>+		ethernet3 = &amp;mscc_felix_port1;</div><div class='add'>+		ethernet4 = &amp;mscc_felix_port2;</div><div class='add'>+		ethernet5 = &amp;mscc_felix_port3;</div><div class='add'>+		ethernet6 = &amp;mscc_felix_port4;</div><div class='add'>+		ethernet7 = &amp;mscc_felix_port5;</div><div class='add'>+		ethernet8 = &amp;enetc_port3;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	chosen {</div><div class='hunk'>@@ -83,6 +96,68 @@</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;can0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	can-transceiver {</div><div class='add'>+		max-bitrate = &lt;5000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;can1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	can-transceiver {</div><div class='add'>+		max-bitrate = &lt;5000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;duart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;duart1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;enetc_mdio_pf3 {</div><div class='add'>+	sgmii_phy0: ethernet-phy@2 {</div><div class='add'>+		reg = &lt;0x2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* VSC8514 QSGMII quad PHY */</div><div class='add'>+	qsgmii_phy0: ethernet-phy@10 {</div><div class='add'>+		reg = &lt;0x10&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	qsgmii_phy1: ethernet-phy@11 {</div><div class='add'>+		reg = &lt;0x11&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	qsgmii_phy2: ethernet-phy@12 {</div><div class='add'>+		reg = &lt;0x12&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	qsgmii_phy3: ethernet-phy@13 {</div><div class='add'>+		reg = &lt;0x13&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;enetc_port0 {</div><div class='add'>+	phy-handle = &lt;&amp;sgmii_phy0&gt;;</div><div class='add'>+	phy-mode = "sgmii";</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;enetc_port2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;enetc_port3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;esdhc {</div><div class='ctx'> 	sd-uhs-sdr104;</div><div class='ctx'> 	sd-uhs-sdr50;</div><div class='hunk'>@@ -113,6 +188,10 @@</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;ftm_alarm1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;i2c0 {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='hunk'>@@ -122,6 +201,37 @@</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;0&gt;;</div><div class='ctx'> </div><div class='add'>+		i2c@0 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0x0&gt;;</div><div class='add'>+</div><div class='add'>+			/* Atmel AT24C512C-XHD­B: 64 KB EEPROM */</div><div class='add'>+			eeprom@50 {</div><div class='add'>+				compatible = "atmel,24c512";</div><div class='add'>+				reg = &lt;0x50&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* AT24C04C 512-byte DDR4 SPD EEPROM */</div><div class='add'>+			/* Documentation says 0x51, but must be even and i2cdetect says 0x52 */</div><div class='add'>+			eeprom@52 {</div><div class='add'>+				compatible = "atmel,24c04";</div><div class='add'>+				reg = &lt;0x52&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* Atmel AT24C02C-XHM­B: 256-byte EEPROM */</div><div class='add'>+			eeprom@57 {</div><div class='add'>+				compatible = "atmel,24c02";</div><div class='add'>+				reg = &lt;0x57&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		i2c@1 {</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='hunk'>@@ -169,51 +279,6 @@</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;duart0 {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;duart1 {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;enetc_mdio_pf3 {</div><div class='del'>-	/* VSC8514 QSGMII quad PHY */</div><div class='del'>-	qsgmii_phy0: ethernet-phy@10 {</div><div class='del'>-		reg = &lt;0x10&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	qsgmii_phy1: ethernet-phy@11 {</div><div class='del'>-		reg = &lt;0x11&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	qsgmii_phy2: ethernet-phy@12 {</div><div class='del'>-		reg = &lt;0x12&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	qsgmii_phy3: ethernet-phy@13 {</div><div class='del'>-		reg = &lt;0x13&gt;;</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;enetc_port0 {</div><div class='del'>-	phy-handle = &lt;&amp;sgmii_phy0&gt;;</div><div class='del'>-	phy-connection-type = "sgmii";</div><div class='del'>-	status = "okay";</div><div class='del'>-</div><div class='del'>-	mdio {</div><div class='del'>-		#address-cells = &lt;1&gt;;</div><div class='del'>-		#size-cells = &lt;0&gt;;</div><div class='del'>-		sgmii_phy0: ethernet-phy@2 {</div><div class='del'>-			reg = &lt;0x2&gt;;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;enetc_port2 {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> &amp;mscc_felix {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='hunk'>@@ -251,7 +316,18 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;mscc_felix_port4 {</div><div class='del'>-	ethernet = &lt;&amp;enetc_port2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mscc_felix_port5 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;optee {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm0 {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -263,6 +339,11 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;usb0 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;usb1 {</div><div class='del'>-	dr_mode = "otg";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi<br/>index 2a7f70b71149..e7f9c9319319 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi</a></div><div class='hunk'>@@ -2,12 +2,13 @@</div><div class='ctx'> /*</div><div class='ctx'>  * Device Tree Include file for NXP Layerscape-1028A family SoC.</div><div class='ctx'>  *</div><div class='del'>- * Copyright 2018 NXP</div><div class='add'>+ * Copyright 2018-2020 NXP</div><div class='ctx'>  *</div><div class='ctx'>  * Harninder Rai &lt;harninder.rai@nxp.com&gt;</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+#include &lt;dt-bindings/clock/fsl,qoriq-clockgen.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/thermal/thermal.h&gt;</div><div class='ctx'> </div><div class='hunk'>@@ -26,7 +27,13 @@</div><div class='ctx'> 			compatible = "arm,cortex-a72";</div><div class='ctx'> 			reg = &lt;0x0&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='del'>-			clocks = &lt;&amp;clockgen 1 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 0&gt;;</div><div class='add'>+			i-cache-size = &lt;0xc000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;l2&gt;;</div><div class='ctx'> 			cpu-idle-states = &lt;&amp;CPU_PW20&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='hunk'>@@ -37,7 +44,13 @@</div><div class='ctx'> 			compatible = "arm,cortex-a72";</div><div class='ctx'> 			reg = &lt;0x1&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='del'>-			clocks = &lt;&amp;clockgen 1 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 0&gt;;</div><div class='add'>+			i-cache-size = &lt;0xc000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;l2&gt;;</div><div class='ctx'> 			cpu-idle-states = &lt;&amp;CPU_PW20&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='hunk'>@@ -45,6 +58,11 @@</div><div class='ctx'> </div><div class='ctx'> 		l2: l2-cache {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x100000&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;1024&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -65,7 +83,14 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sysclk: clock-sysclk {</div><div class='add'>+	rtc_clk: rtc-clk {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;32768&gt;;</div><div class='add'>+		clock-output-names = "rtc_clk";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sysclk: sysclk {</div><div class='ctx'> 		compatible = "fixed-clock";</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='ctx'> 		clock-frequency = &lt;100000000&gt;;</div><div class='hunk'>@@ -79,18 +104,12 @@</div><div class='ctx'> 		clock-output-names = "phy_27m";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	dpclk: clock-controller@f1f0000 {</div><div class='del'>-		compatible = "fsl,ls1028a-plldig";</div><div class='del'>-		reg = &lt;0x0 0xf1f0000 0x0 0xffff&gt;;</div><div class='del'>-		#clock-cells = &lt;0&gt;;</div><div class='del'>-		clocks = &lt;&amp;osc_27m&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	reboot {</div><div class='del'>-		compatible ="syscon-reboot";</div><div class='del'>-		regmap = &lt;&amp;rst&gt;;</div><div class='del'>-		offset = &lt;0xb0&gt;;</div><div class='del'>-		mask = &lt;0x02&gt;;</div><div class='add'>+	firmware {</div><div class='add'>+		optee: optee  {</div><div class='add'>+			compatible = "linaro,optee-tz";</div><div class='add'>+			method = "smc";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	timer {</div><div class='hunk'>@@ -111,30 +130,51 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	gic: interrupt-controller@6000000 {</div><div class='del'>-		compatible= "arm,gic-v3";</div><div class='add'>+		compatible = "arm,gic-v3";</div><div class='ctx'> 		#address-cells = &lt;2&gt;;</div><div class='ctx'> 		#size-cells = &lt;2&gt;;</div><div class='ctx'> 		ranges;</div><div class='del'>-		reg= &lt;0x0 0x06000000 0 0x10000&gt;, /* GIC Dist */</div><div class='add'>+		reg = &lt;0x0 0x06000000 0 0x10000&gt;, /* GIC Dist */</div><div class='ctx'> 			&lt;0x0 0x06040000 0 0x40000&gt;; /* GIC Redistributor */</div><div class='del'>-		#interrupt-cells= &lt;3&gt;;</div><div class='add'>+		#interrupt-cells = &lt;3&gt;;</div><div class='ctx'> 		interrupt-controller;</div><div class='ctx'> 		interrupts = &lt;GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |</div><div class='ctx'> 					 IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='del'>-		its: gic-its@6020000 {</div><div class='add'>+		its: msi-controller@6020000 {</div><div class='ctx'> 			compatible = "arm,gic-v3-its";</div><div class='ctx'> 			msi-controller;</div><div class='add'>+			#msi-cells = &lt;1&gt;;</div><div class='ctx'> 			reg = &lt;0x0 0x06020000 0 0x20000&gt;;/* GIC Translater */</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	thermal-zones {</div><div class='del'>-		core-cluster {</div><div class='add'>+		ddr-thermal {</div><div class='ctx'> 			polling-delay-passive = &lt;1000&gt;;</div><div class='ctx'> 			polling-delay = &lt;5000&gt;;</div><div class='ctx'> 			thermal-sensors = &lt;&amp;tmu 0&gt;;</div><div class='ctx'> </div><div class='ctx'> 			trips {</div><div class='add'>+				ddr-ctrler-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				ddr-ctrler-crit {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cluster-thermal {</div><div class='add'>+			polling-delay-passive = &lt;1000&gt;;</div><div class='add'>+			polling-delay = &lt;5000&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;tmu 1&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='ctx'> 				core_cluster_alert: core-cluster-alert {</div><div class='ctx'> 					temperature = &lt;85000&gt;;</div><div class='ctx'> 					hysteresis = &lt;2000&gt;;</div><div class='hunk'>@@ -168,20 +208,51 @@</div><div class='ctx'> 		ddr: memory-controller@1080000 {</div><div class='ctx'> 			compatible = "fsl,qoriq-memory-controller";</div><div class='ctx'> 			reg = &lt;0x0 0x1080000 0x0 0x1000&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			big-endian;</div><div class='add'>+			interrupts = &lt;GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			little-endian;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		dcfg: syscon@1e00000 {</div><div class='del'>-			compatible = "fsl,ls1028a-dcfg", "syscon";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			compatible = "fsl,ls1028a-dcfg", "syscon", "simple-mfd";</div><div class='ctx'> 			reg = &lt;0x0 0x1e00000 0x0 0x10000&gt;;</div><div class='add'>+			ranges = &lt;0x0 0x0 0x1e00000 0x10000&gt;;</div><div class='ctx'> 			little-endian;</div><div class='add'>+</div><div class='add'>+			fspi_clk: clock-controller@900 {</div><div class='add'>+				compatible = "fsl,ls1028a-flexspi-clk";</div><div class='add'>+				reg = &lt;0x900 0x4&gt;;</div><div class='add'>+				#clock-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;clockgen QORIQ_CLK_HWACCEL 0&gt;;</div><div class='add'>+				clock-output-names = "fspi_clk";</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		rst: syscon@1e60000 {</div><div class='del'>-			compatible = "syscon";</div><div class='add'>+		syscon@1e60000 {</div><div class='add'>+			compatible = "fsl,ls1028a-reset", "syscon", "simple-mfd";</div><div class='ctx'> 			reg = &lt;0x0 0x1e60000 0x0 0x10000&gt;;</div><div class='ctx'> 			little-endian;</div><div class='add'>+</div><div class='add'>+			reboot {</div><div class='add'>+				compatible = "syscon-reboot";</div><div class='add'>+				offset = &lt;0&gt;;</div><div class='add'>+				mask = &lt;0x02&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sfp: efuse@1e80000 {</div><div class='add'>+			compatible = "fsl,ls1028a-sfp";</div><div class='add'>+			reg = &lt;0x0 0x1e80000 0x0 0x10000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='add'>+			clock-names = "sfp";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			ls1028a_uid: unique-id@1c {</div><div class='add'>+				reg = &lt;0x1c 0x8&gt;;</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		scfg: syscon@1fc0000 {</div><div class='hunk'>@@ -203,7 +274,8 @@</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			reg = &lt;0x0 0x2000000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -213,7 +285,8 @@</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			reg = &lt;0x0 0x2010000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -223,7 +296,8 @@</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			reg = &lt;0x0 0x2020000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -233,7 +307,8 @@</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			reg = &lt;0x0 0x2030000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -243,7 +318,8 @@</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			reg = &lt;0x0 0x2040000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -253,7 +329,8 @@</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			reg = &lt;0x0 0x2050000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -263,7 +340,8 @@</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			reg = &lt;0x0 0x2060000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -273,7 +351,8 @@</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			reg = &lt;0x0 0x2070000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -285,7 +364,7 @@</div><div class='ctx'> 			      &lt;0x0 0x20000000 0x0 0x10000000&gt;;</div><div class='ctx'> 			reg-names = "fspi_base", "fspi_mmap";</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;, &lt;&amp;clockgen 4 3&gt;;</div><div class='add'>+			clocks = &lt;&amp;fspi_clk&gt;, &lt;&amp;fspi_clk&gt;;</div><div class='ctx'> 			clock-names = "fspi_en", "fspi";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='hunk'>@@ -297,9 +376,11 @@</div><div class='ctx'> 			reg = &lt;0x0 0x2100000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clock-names = "dspi";</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='add'>+			dmas = &lt;&amp;edma0 0 62&gt;, &lt;&amp;edma0 0 60&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='ctx'> 			spi-num-chipselects = &lt;4&gt;;</div><div class='del'>-			little-endian;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -310,9 +391,11 @@</div><div class='ctx'> 			reg = &lt;0x0 0x2110000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clock-names = "dspi";</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='add'>+			dmas = &lt;&amp;edma0 0 58&gt;, &lt;&amp;edma0 0 56&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='ctx'> 			spi-num-chipselects = &lt;4&gt;;</div><div class='del'>-			little-endian;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -323,9 +406,11 @@</div><div class='ctx'> 			reg = &lt;0x0 0x2120000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clock-names = "dspi";</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='add'>+			dmas = &lt;&amp;edma0 0 54&gt;, &lt;&amp;edma0 0 2&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='ctx'> 			spi-num-chipselects = &lt;3&gt;;</div><div class='del'>-			little-endian;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -334,7 +419,7 @@</div><div class='ctx'> 			reg = &lt;0x0 0x2140000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clock-frequency = &lt;0&gt;; /* fixed up by bootloader */</div><div class='del'>-			clocks = &lt;&amp;clockgen 2 1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_HWACCEL 1&gt;;</div><div class='ctx'> 			voltage-ranges = &lt;1800 1800 3300 3300&gt;;</div><div class='ctx'> 			sdhci,auto-cmd12;</div><div class='ctx'> 			little-endian;</div><div class='hunk'>@@ -347,20 +432,45 @@</div><div class='ctx'> 			reg = &lt;0x0 0x2150000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clock-frequency = &lt;0&gt;; /* fixed up by bootloader */</div><div class='del'>-			clocks = &lt;&amp;clockgen 2 1&gt;;</div><div class='del'>-			voltage-ranges = &lt;1800 1800 3300 3300&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_HWACCEL 1&gt;;</div><div class='add'>+			voltage-ranges = &lt;1800 1800&gt;;</div><div class='ctx'> 			sdhci,auto-cmd12;</div><div class='del'>-			broken-cd;</div><div class='add'>+			non-removable;</div><div class='ctx'> 			little-endian;</div><div class='ctx'> 			bus-width = &lt;4&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		can0: can@2180000 {</div><div class='add'>+			compatible = "fsl,lx2160ar1-flexcan";</div><div class='add'>+			reg = &lt;0x0 0x2180000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='add'>+			clock-names = "ipg", "per";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		can1: can@2190000 {</div><div class='add'>+			compatible = "fsl,lx2160ar1-flexcan";</div><div class='add'>+			reg = &lt;0x0 0x2190000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='add'>+			clock-names = "ipg", "per";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		duart0: serial@21c0500 {</div><div class='ctx'> 			compatible = "fsl,ns16550", "ns16550a";</div><div class='ctx'> 			reg = &lt;0x00 0x21c0500 0x0 0x100&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -368,7 +478,8 @@</div><div class='ctx'> 			compatible = "fsl,ns16550", "ns16550a";</div><div class='ctx'> 			reg = &lt;0x00 0x21c0600 0x0 0x100&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -377,7 +488,8 @@</div><div class='ctx'> 			compatible = "fsl,ls1028a-lpuart";</div><div class='ctx'> 			reg = &lt;0x0 0x2260000 0x0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='ctx'> 			clock-names = "ipg";</div><div class='ctx'> 			dma-names = "rx","tx";</div><div class='ctx'> 			dmas = &lt;&amp;edma0 1 32&gt;,</div><div class='hunk'>@@ -389,7 +501,8 @@</div><div class='ctx'> 			compatible = "fsl,ls1028a-lpuart";</div><div class='ctx'> 			reg = &lt;0x0 0x2270000 0x0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='ctx'> 			clock-names = "ipg";</div><div class='ctx'> 			dma-names = "rx","tx";</div><div class='ctx'> 			dmas = &lt;&amp;edma0 1 30&gt;,</div><div class='hunk'>@@ -401,7 +514,8 @@</div><div class='ctx'> 			compatible = "fsl,ls1028a-lpuart";</div><div class='ctx'> 			reg = &lt;0x0 0x2280000 0x0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='ctx'> 			clock-names = "ipg";</div><div class='ctx'> 			dma-names = "rx","tx";</div><div class='ctx'> 			dmas = &lt;&amp;edma0 1 28&gt;,</div><div class='hunk'>@@ -413,7 +527,8 @@</div><div class='ctx'> 			compatible = "fsl,ls1028a-lpuart";</div><div class='ctx'> 			reg = &lt;0x0 0x2290000 0x0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='ctx'> 			clock-names = "ipg";</div><div class='ctx'> 			dma-names = "rx","tx";</div><div class='ctx'> 			dmas = &lt;&amp;edma0 1 26&gt;,</div><div class='hunk'>@@ -425,7 +540,8 @@</div><div class='ctx'> 			compatible = "fsl,ls1028a-lpuart";</div><div class='ctx'> 			reg = &lt;0x0 0x22a0000 0x0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='ctx'> 			clock-names = "ipg";</div><div class='ctx'> 			dma-names = "rx","tx";</div><div class='ctx'> 			dmas = &lt;&amp;edma0 1 24&gt;,</div><div class='hunk'>@@ -437,7 +553,8 @@</div><div class='ctx'> 			compatible = "fsl,ls1028a-lpuart";</div><div class='ctx'> 			reg = &lt;0x0 0x22b0000 0x0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='ctx'> 			clock-names = "ipg";</div><div class='ctx'> 			dma-names = "rx","tx";</div><div class='ctx'> 			dmas = &lt;&amp;edma0 1 22&gt;,</div><div class='hunk'>@@ -447,7 +564,7 @@</div><div class='ctx'> </div><div class='ctx'> 		edma0: dma-controller@22c0000 {</div><div class='ctx'> 			#dma-cells = &lt;2&gt;;</div><div class='del'>-			compatible = "fsl,ls1028a-edma";</div><div class='add'>+			compatible = "fsl,ls1028a-edma", "fsl,vf610-edma";</div><div class='ctx'> 			reg = &lt;0x0 0x22c0000 0x0 0x10000&gt;,</div><div class='ctx'> 			      &lt;0x0 0x22d0000 0x0 0x10000&gt;,</div><div class='ctx'> 			      &lt;0x0 0x22e0000 0x0 0x10000&gt;;</div><div class='hunk'>@@ -456,8 +573,10 @@</div><div class='ctx'> 			interrupt-names = "edma-tx", "edma-err";</div><div class='ctx'> 			dma-channels = &lt;32&gt;;</div><div class='ctx'> 			clock-names = "dmamux0", "dmamux1";</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 1&gt;,</div><div class='del'>-				 &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		gpio1: gpio@2300000 {</div><div class='hunk'>@@ -494,23 +613,27 @@</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		usb0: usb@3100000 {</div><div class='del'>-			compatible = "fsl,ls1028a-dwc3", "snps,dwc3";</div><div class='add'>+			compatible = "fsl,ls1028a-dwc3";</div><div class='ctx'> 			reg = &lt;0x0 0x3100000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			dr_mode = "host";</div><div class='add'>+			iommus = &lt;&amp;smmu 1&gt;;</div><div class='add'>+			dma-coherent;</div><div class='ctx'> 			snps,dis_rxdet_inp3_quirk;</div><div class='ctx'> 			snps,quirk-frame-length-adjustment = &lt;0x20&gt;;</div><div class='ctx'> 			snps,incr-burst-type-adjustment = &lt;1&gt;, &lt;4&gt;, &lt;8&gt;, &lt;16&gt;;</div><div class='add'>+			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		usb1: usb@3110000 {</div><div class='del'>-			compatible = "fsl,ls1028a-dwc3", "snps,dwc3";</div><div class='add'>+			compatible = "fsl,ls1028a-dwc3";</div><div class='ctx'> 			reg = &lt;0x0 0x3110000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			dr_mode = "host";</div><div class='add'>+			iommus = &lt;&amp;smmu 2&gt;;</div><div class='add'>+			dma-coherent;</div><div class='ctx'> 			snps,dis_rxdet_inp3_quirk;</div><div class='ctx'> 			snps,quirk-frame-length-adjustment = &lt;0x20&gt;;</div><div class='ctx'> 			snps,incr-burst-type-adjustment = &lt;1&gt;, &lt;4&gt;, &lt;8&gt;, &lt;16&gt;;</div><div class='add'>+			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		sata: sata@3200000 {</div><div class='hunk'>@@ -519,14 +642,15 @@</div><div class='ctx'> 				&lt;0x7 0x100520 0x0 0x4&gt;;</div><div class='ctx'> 			reg-names = "ahci", "sata-ecc";</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		pcie@3400000 {</div><div class='add'>+		pcie1: pcie@3400000 {</div><div class='ctx'> 			compatible = "fsl,ls1028a-pcie";</div><div class='del'>-			reg = &lt;0x00 0x03400000 0x0 0x00100000   /* controller registers */</div><div class='del'>-			       0x80 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='add'>+			reg = &lt;0x00 0x03400000 0x0 0x00100000&gt;, /* controller registers */</div><div class='add'>+			      &lt;0x80 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='ctx'> 			reg-names = "regs", "config";</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH&gt;, /* PME interrupt */</div><div class='ctx'> 				     &lt;GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH&gt;; /* aer interrupt */</div><div class='hunk'>@@ -539,7 +663,7 @@</div><div class='ctx'> 			bus-range = &lt;0x0 0xff&gt;;</div><div class='ctx'> 			ranges = &lt;0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000   /* downstream I/O */</div><div class='ctx'> 				  0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000&gt;; /* non-prefetchable memory */</div><div class='del'>-			msi-parent = &lt;&amp;its&gt;;</div><div class='add'>+			msi-parent = &lt;&amp;its 0&gt;;</div><div class='ctx'> 			#interrupt-cells = &lt;1&gt;;</div><div class='ctx'> 			interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='ctx'> 			interrupt-map = &lt;0000 0 0 1 &amp;gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='hunk'>@@ -550,10 +674,22 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		pcie@3500000 {</div><div class='add'>+		pcie_ep1: pcie-ep@3400000 {</div><div class='add'>+			compatible = "fsl,ls1028a-pcie-ep";</div><div class='add'>+			reg = &lt;0x00 0x03400000 0x0 0x00100000</div><div class='add'>+			       0x80 0x00000000 0x8 0x00000000&gt;;</div><div class='add'>+			reg-names = "regs", "addr_space";</div><div class='add'>+			interrupts = &lt;GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH&gt;; /* PME interrupt */</div><div class='add'>+			interrupt-names = "pme";</div><div class='add'>+			num-ib-windows = &lt;6&gt;;</div><div class='add'>+			num-ob-windows = &lt;8&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie2: pcie@3500000 {</div><div class='ctx'> 			compatible = "fsl,ls1028a-pcie";</div><div class='del'>-			reg = &lt;0x00 0x03500000 0x0 0x00100000   /* controller registers */</div><div class='del'>-			       0x88 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='add'>+			reg = &lt;0x00 0x03500000 0x0 0x00100000&gt;, /* controller registers */</div><div class='add'>+			      &lt;0x88 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='ctx'> 			reg-names = "regs", "config";</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 				     &lt;GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='hunk'>@@ -566,7 +702,7 @@</div><div class='ctx'> 			bus-range = &lt;0x0 0xff&gt;;</div><div class='ctx'> 			ranges = &lt;0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000   /* downstream I/O */</div><div class='ctx'> 				  0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000&gt;; /* non-prefetchable memory */</div><div class='del'>-			msi-parent = &lt;&amp;its&gt;;</div><div class='add'>+			msi-parent = &lt;&amp;its 0&gt;;</div><div class='ctx'> 			#interrupt-cells = &lt;1&gt;;</div><div class='ctx'> 			interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='ctx'> 			interrupt-map = &lt;0000 0 0 1 &amp;gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='hunk'>@@ -577,11 +713,24 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		pcie_ep2: pcie-ep@3500000 {</div><div class='add'>+			compatible = "fsl,ls1028a-pcie-ep";</div><div class='add'>+			reg = &lt;0x00 0x03500000 0x0 0x00100000</div><div class='add'>+			       0x88 0x00000000 0x8 0x00000000&gt;;</div><div class='add'>+			reg-names = "regs", "addr_space";</div><div class='add'>+			interrupts = &lt;GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH&gt;; /* PME interrupt */</div><div class='add'>+			interrupt-names = "pme";</div><div class='add'>+			num-ib-windows = &lt;6&gt;;</div><div class='add'>+			num-ob-windows = &lt;8&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		smmu: iommu@5000000 {</div><div class='ctx'> 			compatible = "arm,mmu-500";</div><div class='ctx'> 			reg = &lt;0 0x5000000 0 0x800000&gt;;</div><div class='ctx'> 			#global-interrupts = &lt;8&gt;;</div><div class='ctx'> 			#iommu-cells = &lt;1&gt;;</div><div class='add'>+			dma-coherent;</div><div class='ctx'> 			stream-match-mask = &lt;0x7c00&gt;;</div><div class='ctx'> 			/* global secure fault */</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='hunk'>@@ -642,28 +791,28 @@</div><div class='ctx'> 			sec_jr0: jr@10000 {</div><div class='ctx'> 				compatible = "fsl,sec-v5.0-job-ring",</div><div class='ctx'> 					     "fsl,sec-v4.0-job-ring";</div><div class='del'>-				reg	= &lt;0x10000 0x10000&gt;;</div><div class='add'>+				reg = &lt;0x10000 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			sec_jr1: jr@20000 {</div><div class='ctx'> 				compatible = "fsl,sec-v5.0-job-ring",</div><div class='ctx'> 					     "fsl,sec-v4.0-job-ring";</div><div class='del'>-				reg	= &lt;0x20000 0x10000&gt;;</div><div class='add'>+				reg = &lt;0x20000 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			sec_jr2: jr@30000 {</div><div class='ctx'> 				compatible = "fsl,sec-v5.0-job-ring",</div><div class='ctx'> 					     "fsl,sec-v4.0-job-ring";</div><div class='del'>-				reg	= &lt;0x30000 0x10000&gt;;</div><div class='add'>+				reg = &lt;0x30000 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			sec_jr3: jr@40000 {</div><div class='ctx'> 				compatible = "fsl,sec-v5.0-job-ring",</div><div class='ctx'> 					     "fsl,sec-v4.0-job-ring";</div><div class='del'>-				reg	= &lt;0x40000 0x10000&gt;;</div><div class='add'>+				reg = &lt;0x40000 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='hunk'>@@ -680,6 +829,7 @@</div><div class='ctx'> 				     &lt;GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			interrupt-names = "qdma-error", "qdma-queue0",</div><div class='ctx'> 				"qdma-queue1", "qdma-queue2", "qdma-queue3";</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='ctx'> 			dma-channels = &lt;8&gt;;</div><div class='ctx'> 			block-number = &lt;1&gt;;</div><div class='ctx'> 			block-offset = &lt;0x10000&gt;;</div><div class='hunk'>@@ -691,15 +841,53 @@</div><div class='ctx'> 		cluster1_core0_watchdog: watchdog@c000000 {</div><div class='ctx'> 			compatible = "arm,sp805", "arm,primecell";</div><div class='ctx'> 			reg = &lt;0x0 0xc000000 0x0 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 15&gt;, &lt;&amp;clockgen 4 15&gt;;</div><div class='del'>-			clock-names = "apb_pclk", "wdog_clk";</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(16)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(16)&gt;;</div><div class='add'>+			clock-names = "wdog_clk", "apb_pclk";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cluster1_core1_watchdog: watchdog@c010000 {</div><div class='ctx'> 			compatible = "arm,sp805", "arm,primecell";</div><div class='ctx'> 			reg = &lt;0x0 0xc010000 0x0 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 15&gt;, &lt;&amp;clockgen 4 15&gt;;</div><div class='del'>-			clock-names = "apb_pclk", "wdog_clk";</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(16)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(16)&gt;;</div><div class='add'>+			clock-names = "wdog_clk", "apb_pclk";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		malidp0: display@f080000 {</div><div class='add'>+			compatible = "arm,mali-dp500";</div><div class='add'>+			reg = &lt;0x0 0xf080000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "DE", "SE";</div><div class='add'>+			clocks = &lt;&amp;dpclk&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_HWACCEL 2&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_HWACCEL 2&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_HWACCEL 2&gt;;</div><div class='add'>+			clock-names = "pxlclk", "mclk", "aclk", "pclk";</div><div class='add'>+			arm,malidp-output-port-lines = /bits/ 8 &lt;8 8 8&gt;;</div><div class='add'>+			arm,malidp-arqos-value = &lt;0xd000d000&gt;;</div><div class='add'>+</div><div class='add'>+			port {</div><div class='add'>+				dpi0_out: endpoint {</div><div class='add'>+</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu: gpu@f0c0000 {</div><div class='add'>+			compatible = "vivante,gc";</div><div class='add'>+			reg = &lt;0x0 0xf0c0000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_HWACCEL 2&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_HWACCEL 2&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_HWACCEL 2&gt;;</div><div class='add'>+			clock-names = "core", "shader", "bus";</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		sai1: audio-controller@f100000 {</div><div class='hunk'>@@ -707,12 +895,18 @@</div><div class='ctx'> 			compatible = "fsl,vf610-sai";</div><div class='ctx'> 			reg = &lt;0x0 0xf100000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 1&gt;, &lt;&amp;clockgen 4 1&gt;,</div><div class='del'>-				 &lt;&amp;clockgen 4 1&gt;, &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='ctx'> 			clock-names = "bus", "mclk1", "mclk2", "mclk3";</div><div class='del'>-			dma-names = "tx", "rx";</div><div class='del'>-			dmas = &lt;&amp;edma0 1 4&gt;,</div><div class='del'>-			       &lt;&amp;edma0 1 3&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+			dmas = &lt;&amp;edma0 1 3&gt;,</div><div class='add'>+			       &lt;&amp;edma0 1 4&gt;;</div><div class='ctx'> 			fsl,sai-asynchronous;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='hunk'>@@ -722,12 +916,18 @@</div><div class='ctx'> 			compatible = "fsl,vf610-sai";</div><div class='ctx'> 			reg = &lt;0x0 0xf110000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 1&gt;, &lt;&amp;clockgen 4 1&gt;,</div><div class='del'>-				 &lt;&amp;clockgen 4 1&gt;, &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='ctx'> 			clock-names = "bus", "mclk1", "mclk2", "mclk3";</div><div class='del'>-			dma-names = "tx", "rx";</div><div class='del'>-			dmas = &lt;&amp;edma0 1 6&gt;,</div><div class='del'>-			       &lt;&amp;edma0 1 5&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+			dmas = &lt;&amp;edma0 1 5&gt;,</div><div class='add'>+			       &lt;&amp;edma0 1 6&gt;;</div><div class='ctx'> 			fsl,sai-asynchronous;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='hunk'>@@ -737,12 +937,18 @@</div><div class='ctx'> 			compatible = "fsl,vf610-sai";</div><div class='ctx'> 			reg = &lt;0x0 0xf120000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 1&gt;, &lt;&amp;clockgen 4 1&gt;,</div><div class='del'>-				 &lt;&amp;clockgen 4 1&gt;, &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='ctx'> 			clock-names = "bus", "mclk1", "mclk2", "mclk3";</div><div class='del'>-			dma-names = "tx", "rx";</div><div class='del'>-			dmas = &lt;&amp;edma0 1 8&gt;,</div><div class='del'>-			       &lt;&amp;edma0 1 7&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+			dmas = &lt;&amp;edma0 1 7&gt;,</div><div class='add'>+			       &lt;&amp;edma0 1 8&gt;;</div><div class='ctx'> 			fsl,sai-asynchronous;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='hunk'>@@ -752,12 +958,18 @@</div><div class='ctx'> 			compatible = "fsl,vf610-sai";</div><div class='ctx'> 			reg = &lt;0x0 0xf130000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 1&gt;, &lt;&amp;clockgen 4 1&gt;,</div><div class='del'>-				 &lt;&amp;clockgen 4 1&gt;, &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='ctx'> 			clock-names = "bus", "mclk1", "mclk2", "mclk3";</div><div class='del'>-			dma-names = "tx", "rx";</div><div class='del'>-			dmas = &lt;&amp;edma0 1 10&gt;,</div><div class='del'>-			       &lt;&amp;edma0 1 9&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+			dmas = &lt;&amp;edma0 1 9&gt;,</div><div class='add'>+			       &lt;&amp;edma0 1 10&gt;;</div><div class='ctx'> 			fsl,sai-asynchronous;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='hunk'>@@ -767,12 +979,18 @@</div><div class='ctx'> 			compatible = "fsl,vf610-sai";</div><div class='ctx'> 			reg = &lt;0x0 0xf140000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 1&gt;, &lt;&amp;clockgen 4 1&gt;,</div><div class='del'>-				 &lt;&amp;clockgen 4 1&gt;, &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='ctx'> 			clock-names = "bus", "mclk1", "mclk2", "mclk3";</div><div class='del'>-			dma-names = "tx", "rx";</div><div class='del'>-			dmas = &lt;&amp;edma0 1 12&gt;,</div><div class='del'>-			       &lt;&amp;edma0 1 11&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+			dmas = &lt;&amp;edma0 1 11&gt;,</div><div class='add'>+			       &lt;&amp;edma0 1 12&gt;;</div><div class='ctx'> 			fsl,sai-asynchronous;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='hunk'>@@ -782,64 +1000,78 @@</div><div class='ctx'> 			compatible = "fsl,vf610-sai";</div><div class='ctx'> 			reg = &lt;0x0 0xf150000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 1&gt;, &lt;&amp;clockgen 4 1&gt;,</div><div class='del'>-				 &lt;&amp;clockgen 4 1&gt;, &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='ctx'> 			clock-names = "bus", "mclk1", "mclk2", "mclk3";</div><div class='del'>-			dma-names = "tx", "rx";</div><div class='del'>-			dmas = &lt;&amp;edma0 1 14&gt;,</div><div class='del'>-			       &lt;&amp;edma0 1 13&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+			dmas = &lt;&amp;edma0 1 13&gt;,</div><div class='add'>+			       &lt;&amp;edma0 1 14&gt;;</div><div class='ctx'> 			fsl,sai-asynchronous;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		dpclk: clock-controller@f1f0000 {</div><div class='add'>+			compatible = "fsl,ls1028a-plldig";</div><div class='add'>+			reg = &lt;0x0 0xf1f0000 0x0 0x10000&gt;;</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clocks = &lt;&amp;osc_27m&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		tmu: tmu@1f80000 {</div><div class='ctx'> 			compatible = "fsl,qoriq-tmu";</div><div class='ctx'> 			reg = &lt;0x0 0x1f80000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 23 0x4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			fsl,tmu-range = &lt;0xb0000 0xa0026 0x80048 0x70061&gt;;</div><div class='del'>-			fsl,tmu-calibration = &lt;0x00000000 0x00000024</div><div class='del'>-					       0x00000001 0x0000002b</div><div class='del'>-					       0x00000002 0x00000031</div><div class='del'>-					       0x00000003 0x00000038</div><div class='del'>-					       0x00000004 0x0000003f</div><div class='del'>-					       0x00000005 0x00000045</div><div class='del'>-					       0x00000006 0x0000004c</div><div class='del'>-					       0x00000007 0x00000053</div><div class='del'>-					       0x00000008 0x00000059</div><div class='del'>-					       0x00000009 0x00000060</div><div class='del'>-					       0x0000000a 0x00000066</div><div class='del'>-					       0x0000000b 0x0000006d</div><div class='del'>-</div><div class='del'>-					       0x00010000 0x0000001c</div><div class='del'>-					       0x00010001 0x00000024</div><div class='del'>-					       0x00010002 0x0000002c</div><div class='del'>-					       0x00010003 0x00000035</div><div class='del'>-					       0x00010004 0x0000003d</div><div class='del'>-					       0x00010005 0x00000045</div><div class='del'>-					       0x00010006 0x0000004d</div><div class='del'>-					       0x00010007 0x00000055</div><div class='del'>-					       0x00010008 0x0000005e</div><div class='del'>-					       0x00010009 0x00000066</div><div class='del'>-					       0x0001000a 0x0000006e</div><div class='del'>-</div><div class='del'>-					       0x00020000 0x00000018</div><div class='del'>-					       0x00020001 0x00000022</div><div class='del'>-					       0x00020002 0x0000002d</div><div class='del'>-					       0x00020003 0x00000038</div><div class='del'>-					       0x00020004 0x00000043</div><div class='del'>-					       0x00020005 0x0000004d</div><div class='del'>-					       0x00020006 0x00000058</div><div class='del'>-					       0x00020007 0x00000063</div><div class='del'>-					       0x00020008 0x0000006e</div><div class='del'>-</div><div class='del'>-					       0x00030000 0x00000010</div><div class='del'>-					       0x00030001 0x0000001c</div><div class='del'>-					       0x00030002 0x00000029</div><div class='del'>-					       0x00030003 0x00000036</div><div class='del'>-					       0x00030004 0x00000042</div><div class='del'>-					       0x00030005 0x0000004f</div><div class='del'>-					       0x00030006 0x0000005b</div><div class='del'>-					       0x00030007 0x00000068&gt;;</div><div class='add'>+			fsl,tmu-calibration =</div><div class='add'>+					&lt;0x00000000 0x00000024&gt;,</div><div class='add'>+					&lt;0x00000001 0x0000002b&gt;,</div><div class='add'>+					&lt;0x00000002 0x00000031&gt;,</div><div class='add'>+					&lt;0x00000003 0x00000038&gt;,</div><div class='add'>+					&lt;0x00000004 0x0000003f&gt;,</div><div class='add'>+					&lt;0x00000005 0x00000045&gt;,</div><div class='add'>+					&lt;0x00000006 0x0000004c&gt;,</div><div class='add'>+					&lt;0x00000007 0x00000053&gt;,</div><div class='add'>+					&lt;0x00000008 0x00000059&gt;,</div><div class='add'>+					&lt;0x00000009 0x00000060&gt;,</div><div class='add'>+					&lt;0x0000000a 0x00000066&gt;,</div><div class='add'>+					&lt;0x0000000b 0x0000006d&gt;,</div><div class='add'>+</div><div class='add'>+					&lt;0x00010000 0x0000001c&gt;,</div><div class='add'>+					&lt;0x00010001 0x00000024&gt;,</div><div class='add'>+					&lt;0x00010002 0x0000002c&gt;,</div><div class='add'>+					&lt;0x00010003 0x00000035&gt;,</div><div class='add'>+					&lt;0x00010004 0x0000003d&gt;,</div><div class='add'>+					&lt;0x00010005 0x00000045&gt;,</div><div class='add'>+					&lt;0x00010006 0x0000004d&gt;,</div><div class='add'>+					&lt;0x00010007 0x00000055&gt;,</div><div class='add'>+					&lt;0x00010008 0x0000005e&gt;,</div><div class='add'>+					&lt;0x00010009 0x00000066&gt;,</div><div class='add'>+					&lt;0x0001000a 0x0000006e&gt;,</div><div class='add'>+</div><div class='add'>+					&lt;0x00020000 0x00000018&gt;,</div><div class='add'>+					&lt;0x00020001 0x00000022&gt;,</div><div class='add'>+					&lt;0x00020002 0x0000002d&gt;,</div><div class='add'>+					&lt;0x00020003 0x00000038&gt;,</div><div class='add'>+					&lt;0x00020004 0x00000043&gt;,</div><div class='add'>+					&lt;0x00020005 0x0000004d&gt;,</div><div class='add'>+					&lt;0x00020006 0x00000058&gt;,</div><div class='add'>+					&lt;0x00020007 0x00000063&gt;,</div><div class='add'>+					&lt;0x00020008 0x0000006e&gt;,</div><div class='add'>+</div><div class='add'>+					&lt;0x00030000 0x00000010&gt;,</div><div class='add'>+					&lt;0x00030001 0x0000001c&gt;,</div><div class='add'>+					&lt;0x00030002 0x00000029&gt;,</div><div class='add'>+					&lt;0x00030003 0x00000036&gt;,</div><div class='add'>+					&lt;0x00030004 0x00000042&gt;,</div><div class='add'>+					&lt;0x00030005 0x0000004f&gt;,</div><div class='add'>+					&lt;0x00030006 0x0000005b&gt;,</div><div class='add'>+					&lt;0x00030007 0x00000068&gt;;</div><div class='ctx'> 			little-endian;</div><div class='ctx'> 			#thermal-sensor-cells = &lt;1&gt;;</div><div class='ctx'> 		};</div><div class='hunk'>@@ -849,62 +1081,67 @@</div><div class='ctx'> 			reg = &lt;0x01 0xf0000000 0x0 0x100000&gt;;</div><div class='ctx'> 			#address-cells = &lt;3&gt;;</div><div class='ctx'> 			#size-cells = &lt;2&gt;;</div><div class='del'>-			msi-parent = &lt;&amp;its&gt;;</div><div class='add'>+			msi-parent = &lt;&amp;its 0&gt;;</div><div class='ctx'> 			device_type = "pci";</div><div class='ctx'> 			bus-range = &lt;0x0 0x0&gt;;</div><div class='ctx'> 			dma-coherent;</div><div class='ctx'> 			msi-map = &lt;0 &amp;its 0x17 0xe&gt;;</div><div class='ctx'> 			iommu-map = &lt;0 &amp;smmu 0x17 0xe&gt;;</div><div class='ctx'> 				  /* PF0-6 BAR0 - non-prefetchable memory */</div><div class='del'>-			ranges = &lt;0x82000000 0x0 0x00000000  0x1 0xf8000000  0x0 0x160000</div><div class='add'>+			ranges = &lt;0x82000000 0x1 0xf8000000  0x1 0xf8000000  0x0 0x160000</div><div class='ctx'> 				  /* PF0-6 BAR2 - prefetchable memory */</div><div class='del'>-				  0xc2000000 0x0 0x00000000  0x1 0xf8160000  0x0 0x070000</div><div class='add'>+				  0xc2000000 0x1 0xf8160000  0x1 0xf8160000  0x0 0x070000</div><div class='ctx'> 				  /* PF0: VF0-1 BAR0 - non-prefetchable memory */</div><div class='del'>-				  0x82000000 0x0 0x00000000  0x1 0xf81d0000  0x0 0x020000</div><div class='add'>+				  0x82000000 0x1 0xf81d0000  0x1 0xf81d0000  0x0 0x020000</div><div class='ctx'> 				  /* PF0: VF0-1 BAR2 - prefetchable memory */</div><div class='del'>-				  0xc2000000 0x0 0x00000000  0x1 0xf81f0000  0x0 0x020000</div><div class='add'>+				  0xc2000000 0x1 0xf81f0000  0x1 0xf81f0000  0x0 0x020000</div><div class='ctx'> 				  /* PF1: VF0-1 BAR0 - non-prefetchable memory */</div><div class='del'>-				  0x82000000 0x0 0x00000000  0x1 0xf8210000  0x0 0x020000</div><div class='add'>+				  0x82000000 0x1 0xf8210000  0x1 0xf8210000  0x0 0x020000</div><div class='ctx'> 				  /* PF1: VF0-1 BAR2 - prefetchable memory */</div><div class='del'>-				  0xc2000000 0x0 0x00000000  0x1 0xf8230000  0x0 0x020000</div><div class='add'>+				  0xc2000000 0x1 0xf8230000  0x1 0xf8230000  0x0 0x020000</div><div class='ctx'> 				  /* BAR4 (PF5) - non-prefetchable memory */</div><div class='del'>-				  0x82000000 0x0 0x00000000  0x1 0xfc000000  0x0 0x400000&gt;;</div><div class='add'>+				  0x82000000 0x1 0xfc000000  0x1 0xfc000000  0x0 0x400000&gt;;</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='add'>+			interrupt-map = &lt;0000 0 0 1 &amp;gic 0 0 GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0000 0 0 2 &amp;gic 0 0 GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> </div><div class='ctx'> 			enetc_port0: ethernet@0,0 {</div><div class='del'>-				compatible = "fsl,enetc";</div><div class='add'>+				compatible = "pci1957,e100", "fsl,enetc";</div><div class='ctx'> 				reg = &lt;0x000000 0 0 0 0&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			enetc_port1: ethernet@0,1 {</div><div class='del'>-				compatible = "fsl,enetc";</div><div class='add'>+				compatible = "pci1957,e100", "fsl,enetc";</div><div class='ctx'> 				reg = &lt;0x000100 0 0 0 0&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			enetc_port2: ethernet@0,2 {</div><div class='del'>-				compatible = "fsl,enetc";</div><div class='add'>+				compatible = "pci1957,e100", "fsl,enetc";</div><div class='ctx'> 				reg = &lt;0x000200 0 0 0 0&gt;;</div><div class='ctx'> 				phy-mode = "internal";</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> </div><div class='ctx'> 				fixed-link {</div><div class='del'>-					speed = &lt;1000&gt;;</div><div class='add'>+					speed = &lt;2500&gt;;</div><div class='ctx'> 					full-duplex;</div><div class='add'>+					pause;</div><div class='ctx'> 				};</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			enetc_mdio_pf3: mdio@0,3 {</div><div class='del'>-				compatible = "fsl,enetc-mdio";</div><div class='add'>+				compatible = "pci1957,ee01", "fsl,enetc-mdio";</div><div class='ctx'> 				reg = &lt;0x000300 0 0 0 0&gt;;</div><div class='ctx'> 				#address-cells = &lt;1&gt;;</div><div class='ctx'> 				#size-cells = &lt;0&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			ethernet@0,4 {</div><div class='del'>-				compatible = "fsl,enetc-ptp";</div><div class='add'>+				compatible = "pci1957,ee02", "fsl,enetc-ptp";</div><div class='ctx'> 				reg = &lt;0x000400 0 0 0 0&gt;;</div><div class='del'>-				clocks = &lt;&amp;clockgen 4 0&gt;;</div><div class='add'>+				clocks = &lt;&amp;clockgen QORIQ_CLK_HWACCEL 3&gt;;</div><div class='ctx'> 				little-endian;</div><div class='ctx'> 				fsl,extts-fifo;</div><div class='ctx'> 			};</div><div class='hunk'>@@ -912,10 +1149,10 @@</div><div class='ctx'> 			mscc_felix: ethernet-switch@0,5 {</div><div class='ctx'> 				reg = &lt;0x000500 0 0 0 0&gt;;</div><div class='ctx'> 				/* IEP INT_B */</div><div class='del'>-				interrupts = &lt;GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				interrupts = &lt;2&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> </div><div class='del'>-				ports {</div><div class='add'>+				mscc_felix_ports: ports {</div><div class='ctx'> 					#address-cells = &lt;1&gt;;</div><div class='ctx'> 					#size-cells = &lt;0&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -944,29 +1181,33 @@</div><div class='ctx'> 					mscc_felix_port4: port@4 {</div><div class='ctx'> 						reg = &lt;4&gt;;</div><div class='ctx'> 						phy-mode = "internal";</div><div class='add'>+						ethernet = &lt;&amp;enetc_port2&gt;;</div><div class='ctx'> 						status = "disabled";</div><div class='ctx'> </div><div class='ctx'> 						fixed-link {</div><div class='ctx'> 							speed = &lt;2500&gt;;</div><div class='ctx'> 							full-duplex;</div><div class='add'>+							pause;</div><div class='ctx'> 						};</div><div class='ctx'> 					};</div><div class='ctx'> </div><div class='ctx'> 					mscc_felix_port5: port@5 {</div><div class='ctx'> 						reg = &lt;5&gt;;</div><div class='ctx'> 						phy-mode = "internal";</div><div class='add'>+						ethernet = &lt;&amp;enetc_port3&gt;;</div><div class='ctx'> 						status = "disabled";</div><div class='ctx'> </div><div class='ctx'> 						fixed-link {</div><div class='ctx'> 							speed = &lt;1000&gt;;</div><div class='ctx'> 							full-duplex;</div><div class='add'>+							pause;</div><div class='ctx'> 						};</div><div class='ctx'> 					};</div><div class='ctx'> 				};</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			enetc_port3: ethernet@0,6 {</div><div class='del'>-				compatible = "fsl,enetc";</div><div class='add'>+				compatible = "pci1957,e100", "fsl,enetc";</div><div class='ctx'> 				reg = &lt;0x000600 0 0 0 0&gt;;</div><div class='ctx'> 				phy-mode = "internal";</div><div class='ctx'> 				status = "disabled";</div><div class='hunk'>@@ -974,27 +1215,133 @@</div><div class='ctx'> 				fixed-link {</div><div class='ctx'> 					speed = &lt;1000&gt;;</div><div class='ctx'> 					full-duplex;</div><div class='add'>+					pause;</div><div class='ctx'> 				};</div><div class='ctx'> 			};</div><div class='add'>+</div><div class='add'>+			rcec@1f,0 {</div><div class='add'>+				reg = &lt;0x00f800 0 0 0 0&gt;;</div><div class='add'>+				/* IEP INT_A */</div><div class='add'>+				interrupts = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* Integrated Endpoint Register Block */</div><div class='add'>+		ierb@1f0800000 {</div><div class='add'>+			compatible = "fsl,ls1028a-enetc-ierb";</div><div class='add'>+			reg = &lt;0x01 0xf0800000 0x0 0x10000&gt;;</div><div class='ctx'> 		};</div><div class='del'>-	};</div><div class='ctx'> </div><div class='del'>-	malidp0: display@f080000 {</div><div class='del'>-		compatible = "arm,mali-dp500";</div><div class='del'>-		reg = &lt;0x0 0xf080000 0x0 0x10000&gt;;</div><div class='del'>-		interrupts = &lt;0 222 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-			     &lt;0 223 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-		interrupt-names = "DE", "SE";</div><div class='del'>-		clocks = &lt;&amp;dpclk&gt;, &lt;&amp;clockgen 2 2&gt;, &lt;&amp;clockgen 2 2&gt;,</div><div class='del'>-			 &lt;&amp;clockgen 2 2&gt;;</div><div class='del'>-		clock-names = "pxlclk", "mclk", "aclk", "pclk";</div><div class='del'>-		arm,malidp-output-port-lines = /bits/ 8 &lt;8 8 8&gt;;</div><div class='del'>-		arm,malidp-arqos-value = &lt;0xd000d000&gt;;</div><div class='del'>-</div><div class='del'>-		port {</div><div class='del'>-			dp0_out: endpoint {</div><div class='add'>+		pwm0: pwm@2800000 {</div><div class='add'>+			compatible = "fsl,vf610-ftm-pwm";</div><div class='add'>+			#pwm-cells = &lt;3&gt;;</div><div class='add'>+			reg = &lt;0x0 0x2800000 0x0 0x10000&gt;;</div><div class='add'>+			clock-names = "ftm_sys", "ftm_ext",</div><div class='add'>+				      "ftm_fix", "ftm_cnt_clk_en";</div><div class='add'>+			clocks = &lt;&amp;clockgen 4 1&gt;, &lt;&amp;clockgen 4 1&gt;,</div><div class='add'>+				 &lt;&amp;rtc_clk&gt;, &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='ctx'> </div><div class='del'>-			};</div><div class='add'>+		pwm1: pwm@2810000 {</div><div class='add'>+			compatible = "fsl,vf610-ftm-pwm";</div><div class='add'>+			#pwm-cells = &lt;3&gt;;</div><div class='add'>+			reg = &lt;0x0 0x2810000 0x0 0x10000&gt;;</div><div class='add'>+			clock-names = "ftm_sys", "ftm_ext",</div><div class='add'>+				      "ftm_fix", "ftm_cnt_clk_en";</div><div class='add'>+			clocks = &lt;&amp;clockgen 4 1&gt;, &lt;&amp;clockgen 4 1&gt;,</div><div class='add'>+				 &lt;&amp;rtc_clk&gt;, &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pwm2: pwm@2820000 {</div><div class='add'>+			compatible = "fsl,vf610-ftm-pwm";</div><div class='add'>+			#pwm-cells = &lt;3&gt;;</div><div class='add'>+			reg = &lt;0x0 0x2820000 0x0 0x10000&gt;;</div><div class='add'>+			clock-names = "ftm_sys", "ftm_ext",</div><div class='add'>+				      "ftm_fix", "ftm_cnt_clk_en";</div><div class='add'>+			clocks = &lt;&amp;clockgen 4 1&gt;, &lt;&amp;clockgen 4 1&gt;,</div><div class='add'>+				 &lt;&amp;rtc_clk&gt;, &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pwm3: pwm@2830000 {</div><div class='add'>+			compatible = "fsl,vf610-ftm-pwm";</div><div class='add'>+			#pwm-cells = &lt;3&gt;;</div><div class='add'>+			reg = &lt;0x0 0x2830000 0x0 0x10000&gt;;</div><div class='add'>+			clock-names = "ftm_sys", "ftm_ext",</div><div class='add'>+				      "ftm_fix", "ftm_cnt_clk_en";</div><div class='add'>+			clocks = &lt;&amp;clockgen 4 1&gt;, &lt;&amp;clockgen 4 1&gt;,</div><div class='add'>+				 &lt;&amp;rtc_clk&gt;, &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pwm4: pwm@2840000 {</div><div class='add'>+			compatible = "fsl,vf610-ftm-pwm";</div><div class='add'>+			#pwm-cells = &lt;3&gt;;</div><div class='add'>+			reg = &lt;0x0 0x2840000 0x0 0x10000&gt;;</div><div class='add'>+			clock-names = "ftm_sys", "ftm_ext",</div><div class='add'>+				      "ftm_fix", "ftm_cnt_clk_en";</div><div class='add'>+			clocks = &lt;&amp;clockgen 4 1&gt;, &lt;&amp;clockgen 4 1&gt;,</div><div class='add'>+				 &lt;&amp;rtc_clk&gt;, &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pwm5: pwm@2850000 {</div><div class='add'>+			compatible = "fsl,vf610-ftm-pwm";</div><div class='add'>+			#pwm-cells = &lt;3&gt;;</div><div class='add'>+			reg = &lt;0x0 0x2850000 0x0 0x10000&gt;;</div><div class='add'>+			clock-names = "ftm_sys", "ftm_ext",</div><div class='add'>+				      "ftm_fix", "ftm_cnt_clk_en";</div><div class='add'>+			clocks = &lt;&amp;clockgen 4 1&gt;, &lt;&amp;clockgen 4 1&gt;,</div><div class='add'>+				 &lt;&amp;rtc_clk&gt;, &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pwm6: pwm@2860000 {</div><div class='add'>+			compatible = "fsl,vf610-ftm-pwm";</div><div class='add'>+			#pwm-cells = &lt;3&gt;;</div><div class='add'>+			reg = &lt;0x0 0x2860000 0x0 0x10000&gt;;</div><div class='add'>+			clock-names = "ftm_sys", "ftm_ext",</div><div class='add'>+				      "ftm_fix", "ftm_cnt_clk_en";</div><div class='add'>+			clocks = &lt;&amp;clockgen 4 1&gt;, &lt;&amp;clockgen 4 1&gt;,</div><div class='add'>+				 &lt;&amp;rtc_clk&gt;, &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pwm7: pwm@2870000 {</div><div class='add'>+			compatible = "fsl,vf610-ftm-pwm";</div><div class='add'>+			#pwm-cells = &lt;3&gt;;</div><div class='add'>+			reg = &lt;0x0 0x2870000 0x0 0x10000&gt;;</div><div class='add'>+			clock-names = "ftm_sys", "ftm_ext",</div><div class='add'>+				      "ftm_fix", "ftm_cnt_clk_en";</div><div class='add'>+			clocks = &lt;&amp;clockgen 4 1&gt;, &lt;&amp;clockgen 4 1&gt;,</div><div class='add'>+				 &lt;&amp;rtc_clk&gt;, &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rcpm: wakeup-controller@1e34040 {</div><div class='add'>+			compatible = "fsl,ls1028a-rcpm", "fsl,qoriq-rcpm-2.1+";</div><div class='add'>+			reg = &lt;0x0 0x1e34040 0x0 0x1c&gt;;</div><div class='add'>+			#fsl,rcpm-wakeup-cells = &lt;7&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ftm_alarm0: rtc@2800000 {</div><div class='add'>+			compatible = "fsl,ls1028a-ftm-alarm";</div><div class='add'>+			reg = &lt;0x0 0x2800000 0x0 0x10000&gt;;</div><div class='add'>+			fsl,rcpm-wakeup = &lt;&amp;rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ftm_alarm1: rtc@2810000 {</div><div class='add'>+			compatible = "fsl,ls1028a-ftm-alarm";</div><div class='add'>+			reg = &lt;0x0 0x2810000 0x0 0x10000&gt;;</div><div class='add'>+			fsl,rcpm-wakeup = &lt;&amp;rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi<br/>index d237162a8744..ca7cd7a33c01 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi</a></div><div class='hunk'>@@ -24,9 +24,13 @@</div><div class='ctx'> </div><div class='ctx'> 	/* these aliases provide the FMan ports mapping */</div><div class='ctx'> 	enet0: ethernet@e0000 {</div><div class='add'>+		pcs-handle-names = "qsgmii";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	enet1: ethernet@e2000 {</div><div class='add'>+		pcsphy-handle = &lt;&amp;pcsphy1&gt;, &lt;&amp;qsgmiib_pcs1&gt;;</div><div class='add'>+		pcs-handle = &lt;&amp;pcsphy1&gt;, &lt;&amp;qsgmiib_pcs1&gt;;</div><div class='add'>+		pcs-handle-names = "sgmii", "qsgmii";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	enet2: ethernet@e4000 {</div><div class='hunk'>@@ -36,11 +40,34 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	enet4: ethernet@e8000 {</div><div class='add'>+		pcsphy-handle = &lt;&amp;pcsphy4&gt;, &lt;&amp;qsgmiib_pcs2&gt;;</div><div class='add'>+		pcs-handle = &lt;&amp;pcsphy4&gt;, &lt;&amp;qsgmiib_pcs2&gt;;</div><div class='add'>+		pcs-handle-names = "sgmii", "qsgmii";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	enet5: ethernet@ea000 {</div><div class='add'>+		pcsphy-handle = &lt;&amp;pcsphy5&gt;, &lt;&amp;qsgmiib_pcs3&gt;;</div><div class='add'>+		pcs-handle = &lt;&amp;pcsphy5&gt;, &lt;&amp;qsgmiib_pcs3&gt;;</div><div class='add'>+		pcs-handle-names = "sgmii", "qsgmii";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	enet6: ethernet@f0000 {</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	mdio@e1000 {</div><div class='add'>+		qsgmiib_pcs1: ethernet-pcs@1 {</div><div class='add'>+			compatible = "fsl,lynx-pcs";</div><div class='add'>+			reg = &lt;0x1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qsgmiib_pcs2: ethernet-pcs@2 {</div><div class='add'>+			compatible = "fsl,lynx-pcs";</div><div class='add'>+			reg = &lt;0x2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qsgmiib_pcs3: ethernet-pcs@3 {</div><div class='add'>+			compatible = "fsl,lynx-pcs";</div><div class='add'>+			reg = &lt;0x3&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts<br/>index 1aac81da7e37..e850551b16ac 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts</a></div><div class='hunk'>@@ -3,7 +3,7 @@</div><div class='ctx'>  * Device Tree Include file for Freescale Layerscape-1043A family SoC.</div><div class='ctx'>  *</div><div class='ctx'>  * Copyright 2014-2015 Freescale Semiconductor, Inc.</div><div class='del'>- * Copyright 2018 NXP</div><div class='add'>+ * Copyright 2018-2021 NXP</div><div class='ctx'>  *</div><div class='ctx'>  * Mingkai Hu &lt;Mingkai.hu@freescale.com&gt;</div><div class='ctx'>  */</div><div class='hunk'>@@ -24,6 +24,22 @@</div><div class='ctx'> 		serial1 = &amp;duart1;</div><div class='ctx'> 		serial2 = &amp;duart2;</div><div class='ctx'> 		serial3 = &amp;duart3;</div><div class='add'>+		sgmii-riser-s1-p1 = &amp;sgmii_phy_s1_p1;</div><div class='add'>+		sgmii-riser-s2-p1 = &amp;sgmii_phy_s2_p1;</div><div class='add'>+		sgmii-riser-s3-p1 = &amp;sgmii_phy_s3_p1;</div><div class='add'>+		sgmii-riser-s4-p1 = &amp;sgmii_phy_s4_p1;</div><div class='add'>+		qsgmii-s1-p1 = &amp;qsgmii_phy_s1_p1;</div><div class='add'>+		qsgmii-s1-p2 = &amp;qsgmii_phy_s1_p2;</div><div class='add'>+		qsgmii-s1-p3 = &amp;qsgmii_phy_s1_p3;</div><div class='add'>+		qsgmii-s1-p4 = &amp;qsgmii_phy_s1_p4;</div><div class='add'>+		qsgmii-s2-p1 = &amp;qsgmii_phy_s2_p1;</div><div class='add'>+		qsgmii-s2-p2 = &amp;qsgmii_phy_s2_p2;</div><div class='add'>+		qsgmii-s2-p3 = &amp;qsgmii_phy_s2_p3;</div><div class='add'>+		qsgmii-s2-p4 = &amp;qsgmii_phy_s2_p4;</div><div class='add'>+		emi1-slot1 = &amp;ls1043mdio_s1;</div><div class='add'>+		emi1-slot2 = &amp;ls1043mdio_s2;</div><div class='add'>+		emi1-slot3 = &amp;ls1043mdio_s3;</div><div class='add'>+		emi1-slot4 = &amp;ls1043mdio_s4;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	chosen {</div><div class='hunk'>@@ -48,7 +64,7 @@</div><div class='ctx'> 		  0x2 0x0 0x0 0x7fb00000 0x00000100&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='del'>-	nor@0,0 {</div><div class='add'>+	flash@0,0 {</div><div class='ctx'> 		compatible = "cfi-flash";</div><div class='ctx'> 		reg = &lt;0x0 0x0 0x8000000&gt;;</div><div class='ctx'> 		big-endian;</div><div class='hunk'>@@ -62,15 +78,18 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	fpga: board-control@2,0 {</div><div class='del'>-		compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis";</div><div class='add'>+		compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis", "simple-mfd";</div><div class='ctx'> 		reg = &lt;0x2 0x0 0x0000100&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges = &lt;0 2 0 0x100&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;i2c0 {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='del'>-	pca9547@77 {</div><div class='add'>+	i2c-mux@77 {</div><div class='ctx'> 		compatible = "nxp,pca9547";</div><div class='ctx'> 		reg = &lt;0x77&gt;;</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='hunk'>@@ -148,4 +167,158 @@</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;usb0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> #include "fsl-ls1043-post.dtsi"</div><div class='add'>+</div><div class='add'>+&amp;fman0 {</div><div class='add'>+	ethernet@e0000 {</div><div class='add'>+		phy-handle = &lt;&amp;qsgmii_phy_s2_p1&gt;;</div><div class='add'>+		phy-connection-type = "sgmii";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ethernet@e2000 {</div><div class='add'>+		phy-handle = &lt;&amp;qsgmii_phy_s2_p2&gt;;</div><div class='add'>+		phy-connection-type = "sgmii";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ethernet@e4000 {</div><div class='add'>+		phy-handle = &lt;&amp;rgmii_phy1&gt;;</div><div class='add'>+		phy-connection-type = "rgmii";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ethernet@e6000 {</div><div class='add'>+		phy-handle = &lt;&amp;rgmii_phy2&gt;;</div><div class='add'>+		phy-connection-type = "rgmii";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ethernet@e8000 {</div><div class='add'>+		phy-handle = &lt;&amp;qsgmii_phy_s2_p3&gt;;</div><div class='add'>+		phy-connection-type = "sgmii";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ethernet@ea000 {</div><div class='add'>+		phy-handle = &lt;&amp;qsgmii_phy_s2_p4&gt;;</div><div class='add'>+		phy-connection-type = "sgmii";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ethernet@f0000 { /* DTSEC9/10GEC1 */</div><div class='add'>+		fixed-link = &lt;1 1 10000 0 0&gt;;</div><div class='add'>+		phy-connection-type = "xgmii";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fpga {</div><div class='add'>+	mdio-mux@54 {</div><div class='add'>+		compatible = "mdio-mux-mmioreg", "mdio-mux";</div><div class='add'>+		mdio-parent-bus = &lt;&amp;mdio0&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		reg = &lt;0x54 1&gt;;    /* BRDCFG4 */</div><div class='add'>+		mux-mask = &lt;0xe0&gt;; /* EMI1 */</div><div class='add'>+</div><div class='add'>+		/* On-board RGMII1 PHY */</div><div class='add'>+		ls1043mdio0: mdio@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			rgmii_phy1: ethernet-phy@1 { /* MAC3 */</div><div class='add'>+				reg = &lt;0x1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* On-board RGMII2 PHY */</div><div class='add'>+		ls1043mdio1: mdio@20 {</div><div class='add'>+			reg = &lt;0x20&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			rgmii_phy2: ethernet-phy@2 { /* MAC4 */</div><div class='add'>+				reg = &lt;0x2&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* Slot 1 */</div><div class='add'>+		ls1043mdio_s1: mdio@40 {</div><div class='add'>+			reg = &lt;0x40&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			qsgmii_phy_s1_p1: ethernet-phy@4 {</div><div class='add'>+				reg = &lt;0x4&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qsgmii_phy_s1_p2: ethernet-phy@5 {</div><div class='add'>+				reg = &lt;0x5&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qsgmii_phy_s1_p3: ethernet-phy@6 {</div><div class='add'>+				reg = &lt;0x6&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qsgmii_phy_s1_p4: ethernet-phy@7 {</div><div class='add'>+				reg = &lt;0x7&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sgmii_phy_s1_p1: ethernet-phy@1c {</div><div class='add'>+				reg = &lt;0x1c&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* Slot 2 */</div><div class='add'>+		ls1043mdio_s2: mdio@60 {</div><div class='add'>+			reg = &lt;0x60&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			qsgmii_phy_s2_p1: ethernet-phy@8 {</div><div class='add'>+				reg = &lt;0x8&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qsgmii_phy_s2_p2: ethernet-phy@9 {</div><div class='add'>+				reg = &lt;0x9&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qsgmii_phy_s2_p3: ethernet-phy@a {</div><div class='add'>+				reg = &lt;0xa&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qsgmii_phy_s2_p4: ethernet-phy@b {</div><div class='add'>+				reg = &lt;0xb&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sgmii_phy_s2_p1: ethernet-phy@1c {</div><div class='add'>+				reg = &lt;0x1c&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* Slot 3 */</div><div class='add'>+		ls1043mdio_s3: mdio@80 {</div><div class='add'>+			reg = &lt;0x80&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			sgmii_phy_s3_p1: ethernet-phy@1c {</div><div class='add'>+				reg = &lt;0x1c&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* Slot 4 */</div><div class='add'>+		ls1043mdio_s4: mdio@a0 {</div><div class='add'>+			reg = &lt;0xa0&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			sgmii_phy_s4_p1: ethernet-phy@1c {</div><div class='add'>+				reg = &lt;0x1c&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts<br/>index dde50c88f5e3..c4532c809f0a 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts</a></div><div class='hunk'>@@ -13,6 +13,7 @@</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	model = "LS1043A RDB Board";</div><div class='add'>+	compatible = "fsl,ls1043a-rdb", "fsl,ls1043a";</div><div class='ctx'> </div><div class='ctx'> 	aliases {</div><div class='ctx'> 		serial0 = &amp;duart0;</div><div class='hunk'>@@ -28,23 +29,33 @@</div><div class='ctx'> </div><div class='ctx'> &amp;i2c0 {</div><div class='ctx'> 	status = "okay";</div><div class='add'>+</div><div class='ctx'> 	ina220@40 {</div><div class='ctx'> 		compatible = "ti,ina220";</div><div class='ctx'> 		reg = &lt;0x40&gt;;</div><div class='ctx'> 		shunt-resistor = &lt;1000&gt;;</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='ctx'> 	adt7461a@4c {</div><div class='ctx'> 		compatible = "adi,adt7461";</div><div class='ctx'> 		reg = &lt;0x4c&gt;;</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	rtc@51 {</div><div class='add'>+		compatible = "nxp,pcf85263";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	eeprom@52 {</div><div class='ctx'> 		compatible = "atmel,24c512";</div><div class='ctx'> 		reg = &lt;0x52&gt;;</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='ctx'> 	eeprom@53 {</div><div class='ctx'> 		compatible = "atmel,24c512";</div><div class='ctx'> 		reg = &lt;0x53&gt;;</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='ctx'> 	rtc@68 {</div><div class='ctx'> 		compatible = "pericom,pt7c4338";</div><div class='ctx'> 		reg = &lt;0x68&gt;;</div><div class='hunk'>@@ -60,7 +71,7 @@</div><div class='ctx'> 		  0x1 0x0 0x0 0x7e800000 0x00010000</div><div class='ctx'> 		  0x2 0x0 0x0 0x7fb00000 0x00000100&gt;;</div><div class='ctx'> </div><div class='del'>-		nor@0,0 {</div><div class='add'>+		flash@0,0 {</div><div class='ctx'> 			compatible = "cfi-flash";</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;1&gt;;</div><div class='hunk'>@@ -93,6 +104,42 @@</div><div class='ctx'> 		compatible = "n25q128a13", "jedec,spi-nor";  /* 16MB */</div><div class='ctx'> 		reg = &lt;0&gt;;</div><div class='ctx'> 		spi-max-frequency = &lt;1000000&gt;; /* input clock */</div><div class='add'>+		/*</div><div class='add'>+		 * Standard CS timing properties replace the deprecated vendor</div><div class='add'>+		 * variants below.</div><div class='add'>+		 */</div><div class='add'>+		spi-cs-setup-delay-ns = &lt;100&gt;;</div><div class='add'>+		spi-cs-hold-delay-ns = &lt;100&gt;;</div><div class='add'>+		fsl,spi-cs-sck-delay = &lt;100&gt;;</div><div class='add'>+		fsl,spi-sck-cs-delay = &lt;100&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	slic@2 {</div><div class='add'>+		compatible = "maxim,ds26522";</div><div class='add'>+		reg = &lt;2&gt;;</div><div class='add'>+		spi-max-frequency = &lt;2000000&gt;;</div><div class='add'>+		/*</div><div class='add'>+		 * Standard CS timing properties replace the deprecated vendor</div><div class='add'>+		 * variants below.</div><div class='add'>+		 */</div><div class='add'>+		spi-cs-setup-delay-ns = &lt;100&gt;;</div><div class='add'>+		spi-cs-hold-delay-ns = &lt;50&gt;;</div><div class='add'>+		fsl,spi-cs-sck-delay = &lt;100&gt;;</div><div class='add'>+		fsl,spi-sck-cs-delay = &lt;50&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	slic@3 {</div><div class='add'>+		compatible = "maxim,ds26522";</div><div class='add'>+		reg = &lt;3&gt;;</div><div class='add'>+		spi-max-frequency = &lt;2000000&gt;;</div><div class='add'>+		/*</div><div class='add'>+		 * Standard CS timing properties replace the deprecated vendor</div><div class='add'>+		 * variants below.</div><div class='add'>+		 */</div><div class='add'>+		spi-cs-setup-delay-ns = &lt;100&gt;;</div><div class='add'>+		spi-cs-hold-delay-ns = &lt;50&gt;;</div><div class='add'>+		fsl,spi-cs-sck-delay = &lt;100&gt;;</div><div class='add'>+		fsl,spi-sck-cs-delay = &lt;50&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -176,3 +223,27 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='add'>+</div><div class='add'>+&amp;uqe {</div><div class='add'>+	ucc_hdlc: ucc@2000 {</div><div class='add'>+		compatible = "fsl,ucc-hdlc";</div><div class='add'>+		rx-clock-name = "clk8";</div><div class='add'>+		tx-clock-name = "clk9";</div><div class='add'>+		fsl,rx-sync-clock = "rsync_pin";</div><div class='add'>+		fsl,tx-sync-clock = "tsync_pin";</div><div class='add'>+		fsl,tx-timeslot-mask = &lt;0xfffffffe&gt;;</div><div class='add'>+		fsl,rx-timeslot-mask = &lt;0xfffffffe&gt;;</div><div class='add'>+		fsl,tdm-framer-type = "e1";</div><div class='add'>+		fsl,tdm-id = &lt;0&gt;;</div><div class='add'>+		fsl,siram-entry-id = &lt;0&gt;;</div><div class='add'>+		fsl,tdm-interface;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-tqmls1043a-mbls10xxa.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-tqmls1043a-mbls10xxa.dts<br/>new file mode 100644<br/>index 000000000000..e04483fdb908<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1043a-tqmls1043a-mbls10xxa.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls1043a-tqmls1043a-mbls10xxa.dts</a></div><div class='hunk'>@@ -0,0 +1,61 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2018-2023 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Gregor Herburger, Timo Herbrecher</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+</div><div class='add'>+#include "fsl-ls1043a-tqmls1043a.dtsi"</div><div class='add'>+#include "tqmls10xxa-mbls10xxa.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "TQ-Systems GmbH LS1043A TQMLS1043A SoM on MBLS10xxA board";</div><div class='add'>+	compatible = "tq,ls1043a-tqmls1043a-mbls10xxa", "tq,ls1043a-tqmls1043a",</div><div class='add'>+		     "fsl,ls1043a";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		qsgmii-s1-p1 = &amp;qsgmii1_phy1;</div><div class='add'>+		qsgmii-s1-p2 = &amp;qsgmii1_phy2;</div><div class='add'>+		qsgmii-s1-p3 = &amp;qsgmii1_phy3;</div><div class='add'>+		qsgmii-s1-p4 = &amp;qsgmii1_phy4;</div><div class='add'>+		qsgmii-s2-p1 = &amp;qsgmii2_phy1;</div><div class='add'>+		qsgmii-s2-p2 = &amp;qsgmii2_phy2;</div><div class='add'>+		qsgmii-s2-p3 = &amp;qsgmii2_phy3;</div><div class='add'>+		qsgmii-s2-p4 = &amp;qsgmii2_phy4;</div><div class='add'>+		serial0 = &amp;duart0;</div><div class='add'>+		serial1 = &amp;duart1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;duart1;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;esdhc {</div><div class='add'>+	cd-gpios = &lt;&amp;gpio3 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	wp-gpios = &lt;&amp;gpio3 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sfp1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sfp1_i2c {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include "fsl-ls1043-post.dtsi"</div><div class='add'>+#include "tqmls104xa-mbls10xxa-fman.dtsi"</div><div class='add'>+</div><div class='add'>+&amp;enet6 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-tqmls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a-tqmls1043a.dtsi<br/>new file mode 100644<br/>index 000000000000..257d90bb9c20<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1043a-tqmls1043a.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls1043a-tqmls1043a.dtsi</a></div><div class='hunk'>@@ -0,0 +1,31 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2018-2023 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Gregor Herburger, Timo Herbrecher</div><div class='add'>+ *</div><div class='add'>+ * Device Tree Include file for LS1043A based SoM of TQ</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "fsl-ls1043a.dtsi"</div><div class='add'>+#include "tqmls10xxa.dtsi"</div><div class='add'>+</div><div class='add'>+&amp;qspi {</div><div class='add'>+	num-cs = &lt;2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	qflash0: flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;62500000&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;4&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_vcc1v8&gt;;</div><div class='add'>+</div><div class='add'>+		partitions {</div><div class='add'>+			compatible = "fixed-partitions";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi<br/>index c084c7a4b6a6..50d9b03a284a 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi</a></div><div class='hunk'>@@ -1,15 +1,17 @@</div><div class='ctx'> // SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='ctx'> /*</div><div class='del'>- * Device Tree Include file for Freescale Layerscape-1043A family SoC.</div><div class='add'>+ * Device Tree Include file for NXP Layerscape-1043A family SoC.</div><div class='ctx'>  *</div><div class='ctx'>  * Copyright 2014-2015 Freescale Semiconductor, Inc.</div><div class='del'>- * Copyright 2018 NXP</div><div class='add'>+ * Copyright 2018, 2020 NXP</div><div class='ctx'>  *</div><div class='ctx'>  * Mingkai Hu &lt;Mingkai.hu@freescale.com&gt;</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+#include &lt;dt-bindings/clock/fsl,qoriq-clockgen.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/thermal/thermal.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	compatible = "fsl,ls1043a";</div><div class='hunk'>@@ -27,6 +29,7 @@</div><div class='ctx'> 		ethernet4 = &amp;enet4;</div><div class='ctx'> 		ethernet5 = &amp;enet5;</div><div class='ctx'> 		ethernet6 = &amp;enet6;</div><div class='add'>+		rtc1 = &amp;ftm_alarm0;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	cpus {</div><div class='hunk'>@@ -43,7 +46,7 @@</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			reg = &lt;0x0&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 1 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 0&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;l2&gt;;</div><div class='ctx'> 			cpu-idle-states = &lt;&amp;CPU_PH20&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='hunk'>@@ -53,7 +56,7 @@</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			reg = &lt;0x1&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 1 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 0&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;l2&gt;;</div><div class='ctx'> 			cpu-idle-states = &lt;&amp;CPU_PH20&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='hunk'>@@ -63,7 +66,7 @@</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			reg = &lt;0x2&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 1 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 0&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;l2&gt;;</div><div class='ctx'> 			cpu-idle-states = &lt;&amp;CPU_PH20&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='hunk'>@@ -73,7 +76,7 @@</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			reg = &lt;0x3&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 1 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 0&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;l2&gt;;</div><div class='ctx'> 			cpu-idle-states = &lt;&amp;CPU_PH20&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='hunk'>@@ -81,6 +84,8 @@</div><div class='ctx'> </div><div class='ctx'> 		l2: l2-cache {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -142,26 +147,86 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	reboot {</div><div class='del'>-		compatible ="syscon-reboot";</div><div class='add'>+		compatible = "syscon-reboot";</div><div class='ctx'> 		regmap = &lt;&amp;dcfg&gt;;</div><div class='ctx'> 		offset = &lt;0xb0&gt;;</div><div class='ctx'> 		mask = &lt;0x02&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	thermal-zones {</div><div class='del'>-		cpu_thermal: cpu-thermal {</div><div class='add'>+		ddr-thermal {</div><div class='ctx'> 			polling-delay-passive = &lt;1000&gt;;</div><div class='ctx'> 			polling-delay = &lt;5000&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;tmu 0&gt;;</div><div class='ctx'> </div><div class='add'>+			trips {</div><div class='add'>+				ddr-ctrler-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				ddr-ctrler-crit {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		serdes-thermal {</div><div class='add'>+			polling-delay-passive = &lt;1000&gt;;</div><div class='add'>+			polling-delay = &lt;5000&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;tmu 1&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				serdes-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				serdes-crit {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		fman-thermal {</div><div class='add'>+			polling-delay-passive = &lt;1000&gt;;</div><div class='add'>+			polling-delay = &lt;5000&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;tmu 2&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				fman-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				fman-crit {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cluster-thermal {</div><div class='add'>+			polling-delay-passive = &lt;1000&gt;;</div><div class='add'>+			polling-delay = &lt;5000&gt;;</div><div class='ctx'> 			thermal-sensors = &lt;&amp;tmu 3&gt;;</div><div class='ctx'> </div><div class='ctx'> 			trips {</div><div class='del'>-				cpu_alert: cpu-alert {</div><div class='add'>+				core_cluster_alert: core-cluster-alert {</div><div class='ctx'> 					temperature = &lt;85000&gt;;</div><div class='ctx'> 					hysteresis = &lt;2000&gt;;</div><div class='ctx'> 					type = "passive";</div><div class='ctx'> 				};</div><div class='del'>-				cpu_crit: cpu-crit {</div><div class='add'>+</div><div class='add'>+				core_cluster_crit: core-cluster-crit {</div><div class='ctx'> 					temperature = &lt;95000&gt;;</div><div class='ctx'> 					hysteresis = &lt;2000&gt;;</div><div class='ctx'> 					type = "critical";</div><div class='hunk'>@@ -170,7 +235,7 @@</div><div class='ctx'> </div><div class='ctx'> 			cooling-maps {</div><div class='ctx'> 				map0 {</div><div class='del'>-					trip = &lt;&amp;cpu_alert&gt;;</div><div class='add'>+					trip = &lt;&amp;core_cluster_alert&gt;;</div><div class='ctx'> 					cooling-device =</div><div class='ctx'> 						&lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='ctx'> 						&lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='hunk'>@@ -179,23 +244,43 @@</div><div class='ctx'> 				};</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='add'>+</div><div class='add'>+		sec-thermal {</div><div class='add'>+			polling-delay-passive = &lt;1000&gt;;</div><div class='add'>+			polling-delay = &lt;5000&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;tmu 4&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				sec-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				sec-crit {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	timer {</div><div class='ctx'> 		compatible = "arm,armv8-timer";</div><div class='del'>-		interrupts = &lt;1 13 0xf08&gt;, /* Physical Secure PPI */</div><div class='del'>-			     &lt;1 14 0xf08&gt;, /* Physical Non-Secure PPI */</div><div class='del'>-			     &lt;1 11 0xf08&gt;, /* Virtual PPI */</div><div class='del'>-			     &lt;1 10 0xf08&gt;; /* Hypervisor PPI */</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='ctx'> 		fsl,erratum-a008585;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	pmu {</div><div class='del'>-		compatible = "arm,armv8-pmuv3";</div><div class='del'>-		interrupts = &lt;0 106 0x4&gt;,</div><div class='del'>-			     &lt;0 107 0x4&gt;,</div><div class='del'>-			     &lt;0 95 0x4&gt;,</div><div class='del'>-			     &lt;0 97 0x4&gt;;</div><div class='add'>+		compatible = "arm,cortex-a53-pmu";</div><div class='add'>+		interrupts = &lt;GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		interrupt-affinity = &lt;&amp;cpu0&gt;,</div><div class='ctx'> 				     &lt;&amp;cpu1&gt;,</div><div class='ctx'> 				     &lt;&amp;cpu2&gt;,</div><div class='hunk'>@@ -204,13 +289,14 @@</div><div class='ctx'> </div><div class='ctx'> 	gic: interrupt-controller@1400000 {</div><div class='ctx'> 		compatible = "arm,gic-400";</div><div class='add'>+		#address-cells = &lt;0&gt;;</div><div class='ctx'> 		#interrupt-cells = &lt;3&gt;;</div><div class='ctx'> 		interrupt-controller;</div><div class='ctx'> 		reg = &lt;0x0 0x1401000 0 0x1000&gt;, /* GICD */</div><div class='ctx'> 		      &lt;0x0 0x1402000 0 0x2000&gt;, /* GICC */</div><div class='ctx'> 		      &lt;0x0 0x1404000 0 0x2000&gt;, /* GICH */</div><div class='ctx'> 		      &lt;0x0 0x1406000 0 0x2000&gt;; /* GICV */</div><div class='del'>-		interrupts = &lt;1 9 0xf08&gt;;</div><div class='add'>+		interrupts = &lt;GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	soc: soc {</div><div class='hunk'>@@ -218,6 +304,8 @@</div><div class='ctx'> 		#address-cells = &lt;2&gt;;</div><div class='ctx'> 		#size-cells = &lt;2&gt;;</div><div class='ctx'> 		ranges;</div><div class='add'>+		dma-ranges = &lt;0x0 0x0 0x0 0x0 0x10000 0x00000000&gt;;</div><div class='add'>+		dma-coherent;</div><div class='ctx'> </div><div class='ctx'> 		clockgen: clocking@1ee1000 {</div><div class='ctx'> 			compatible = "fsl,ls1043a-clockgen";</div><div class='hunk'>@@ -230,6 +318,31 @@</div><div class='ctx'> 			compatible = "fsl,ls1043a-scfg", "syscon";</div><div class='ctx'> 			reg = &lt;0x0 0x1570000 0x0 0x10000&gt;;</div><div class='ctx'> 			big-endian;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges = &lt;0x0 0x0 0x1570000 0x10000&gt;;</div><div class='add'>+</div><div class='add'>+			extirq: interrupt-controller@1ac {</div><div class='add'>+				compatible = "fsl,ls1043a-extirq";</div><div class='add'>+				#interrupt-cells = &lt;2&gt;;</div><div class='add'>+				#address-cells = &lt;0&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				reg = &lt;0x1ac 4&gt;;</div><div class='add'>+				interrupt-map =</div><div class='add'>+					&lt;0 0 &amp;gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;1 0 &amp;gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;2 0 &amp;gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;3 0 &amp;gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;4 0 &amp;gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;5 0 &amp;gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;6 0 &amp;gic GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;7 0 &amp;gic GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;8 0 &amp;gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;9 0 &amp;gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;10 0 &amp;gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;11 0 &amp;gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				interrupt-map-mask = &lt;0xf 0x0&gt;;</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		crypto: crypto@1700000 {</div><div class='hunk'>@@ -240,51 +353,60 @@</div><div class='ctx'> 			#size-cells = &lt;1&gt;;</div><div class='ctx'> 			ranges = &lt;0x0 0x00 0x1700000 0x100000&gt;;</div><div class='ctx'> 			reg = &lt;0x00 0x1700000 0x0 0x100000&gt;;</div><div class='del'>-			interrupts = &lt;0 75 0x4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			dma-coherent;</div><div class='ctx'> </div><div class='ctx'> 			sec_jr0: jr@10000 {</div><div class='ctx'> 				compatible = "fsl,sec-v5.4-job-ring",</div><div class='ctx'> 					     "fsl,sec-v5.0-job-ring",</div><div class='ctx'> 					     "fsl,sec-v4.0-job-ring";</div><div class='del'>-				reg	   = &lt;0x10000 0x10000&gt;;</div><div class='del'>-				interrupts = &lt;0 71 0x4&gt;;</div><div class='add'>+				reg = &lt;0x10000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			sec_jr1: jr@20000 {</div><div class='ctx'> 				compatible = "fsl,sec-v5.4-job-ring",</div><div class='ctx'> 					     "fsl,sec-v5.0-job-ring",</div><div class='ctx'> 					     "fsl,sec-v4.0-job-ring";</div><div class='del'>-				reg	   = &lt;0x20000 0x10000&gt;;</div><div class='del'>-				interrupts = &lt;0 72 0x4&gt;;</div><div class='add'>+				reg = &lt;0x20000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			sec_jr2: jr@30000 {</div><div class='ctx'> 				compatible = "fsl,sec-v5.4-job-ring",</div><div class='ctx'> 					     "fsl,sec-v5.0-job-ring",</div><div class='ctx'> 					     "fsl,sec-v4.0-job-ring";</div><div class='del'>-				reg	   = &lt;0x30000 0x10000&gt;;</div><div class='del'>-				interrupts = &lt;0 73 0x4&gt;;</div><div class='add'>+				reg = &lt;0x30000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			sec_jr3: jr@40000 {</div><div class='ctx'> 				compatible = "fsl,sec-v5.4-job-ring",</div><div class='ctx'> 					     "fsl,sec-v5.0-job-ring",</div><div class='ctx'> 					     "fsl,sec-v4.0-job-ring";</div><div class='del'>-				reg	   = &lt;0x40000 0x10000&gt;;</div><div class='del'>-				interrupts = &lt;0 74 0x4&gt;;</div><div class='add'>+				reg = &lt;0x40000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		sfp: efuse@1e80000 {</div><div class='add'>+			compatible = "fsl,ls1021a-sfp";</div><div class='add'>+			reg = &lt;0x0 0x1e80000 0x0 0x10000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='add'>+			clock-names = "sfp";</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		dcfg: dcfg@1ee0000 {</div><div class='ctx'> 			compatible = "fsl,ls1043a-dcfg", "syscon";</div><div class='del'>-			reg = &lt;0x0 0x1ee0000 0x0 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x1ee0000 0x0 0x1000&gt;;</div><div class='ctx'> 			big-endian;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		ifc: ifc@1530000 {</div><div class='del'>-			compatible = "fsl,ifc", "simple-bus";</div><div class='add'>+		ifc: memory-controller@1530000 {</div><div class='add'>+			compatible = "fsl,ifc";</div><div class='ctx'> 			reg = &lt;0x0 0x1530000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 43 0x4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		qspi: spi@1550000 {</div><div class='hunk'>@@ -294,71 +416,77 @@</div><div class='ctx'> 			reg = &lt;0x0 0x1550000 0x0 0x10000&gt;,</div><div class='ctx'> 				&lt;0x0 0x40000000 0x0 0x4000000&gt;;</div><div class='ctx'> 			reg-names = "QuadSPI", "QuadSPI-memory";</div><div class='del'>-			interrupts = &lt;0 99 0x4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clock-names = "qspi_en", "qspi";</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 0&gt;, &lt;&amp;clockgen 4 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(1)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(1)&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		esdhc: esdhc@1560000 {</div><div class='add'>+		esdhc: mmc@1560000 {</div><div class='ctx'> 			compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";</div><div class='ctx'> 			reg = &lt;0x0 0x1560000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 62 0x4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clock-frequency = &lt;0&gt;;</div><div class='ctx'> 			voltage-ranges = &lt;1800 1800 3300 3300&gt;;</div><div class='ctx'> 			sdhci,auto-cmd12;</div><div class='del'>-			big-endian;</div><div class='ctx'> 			bus-width = &lt;4&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		ddr: memory-controller@1080000 {</div><div class='ctx'> 			compatible = "fsl,qoriq-memory-controller";</div><div class='ctx'> 			reg = &lt;0x0 0x1080000 0x0 0x1000&gt;;</div><div class='del'>-			interrupts = &lt;0 144 0x4&gt;;</div><div class='del'>-			big-endian;</div><div class='add'>+			interrupts = &lt;GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		tmu: tmu@1f00000 {</div><div class='ctx'> 			compatible = "fsl,qoriq-tmu";</div><div class='ctx'> 			reg = &lt;0x0 0x1f00000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 33 0x4&gt;;</div><div class='del'>-			fsl,tmu-range = &lt;0xb0000 0x9002a 0x6004c 0x30062&gt;;</div><div class='del'>-			fsl,tmu-calibration = &lt;0x00000000 0x00000026</div><div class='del'>-					       0x00000001 0x0000002d</div><div class='del'>-					       0x00000002 0x00000032</div><div class='del'>-					       0x00000003 0x00000039</div><div class='del'>-					       0x00000004 0x0000003f</div><div class='del'>-					       0x00000005 0x00000046</div><div class='del'>-					       0x00000006 0x0000004d</div><div class='del'>-					       0x00000007 0x00000054</div><div class='del'>-					       0x00000008 0x0000005a</div><div class='del'>-					       0x00000009 0x00000061</div><div class='del'>-					       0x0000000a 0x0000006a</div><div class='del'>-					       0x0000000b 0x00000071</div><div class='del'>-</div><div class='del'>-					       0x00010000 0x00000025</div><div class='del'>-					       0x00010001 0x0000002c</div><div class='del'>-					       0x00010002 0x00000035</div><div class='del'>-					       0x00010003 0x0000003d</div><div class='del'>-					       0x00010004 0x00000045</div><div class='del'>-					       0x00010005 0x0000004e</div><div class='del'>-					       0x00010006 0x00000057</div><div class='del'>-					       0x00010007 0x00000061</div><div class='del'>-					       0x00010008 0x0000006b</div><div class='del'>-					       0x00010009 0x00000076</div><div class='del'>-</div><div class='del'>-					       0x00020000 0x00000029</div><div class='del'>-					       0x00020001 0x00000033</div><div class='del'>-					       0x00020002 0x0000003d</div><div class='del'>-					       0x00020003 0x00000049</div><div class='del'>-					       0x00020004 0x00000056</div><div class='del'>-					       0x00020005 0x00000061</div><div class='del'>-					       0x00020006 0x0000006d</div><div class='del'>-</div><div class='del'>-					       0x00030000 0x00000021</div><div class='del'>-					       0x00030001 0x0000002a</div><div class='del'>-					       0x00030002 0x0000003c</div><div class='del'>-					       0x00030003 0x0000004e&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			fsl,tmu-range = &lt;0xb0000 0x9002a 0x6004c 0x70062&gt;;</div><div class='add'>+			fsl,tmu-calibration =</div><div class='add'>+					&lt;0x00000000 0x00000023&gt;,</div><div class='add'>+					&lt;0x00000001 0x0000002a&gt;,</div><div class='add'>+					&lt;0x00000002 0x00000031&gt;,</div><div class='add'>+					&lt;0x00000003 0x00000037&gt;,</div><div class='add'>+					&lt;0x00000004 0x0000003e&gt;,</div><div class='add'>+					&lt;0x00000005 0x00000044&gt;,</div><div class='add'>+					&lt;0x00000006 0x0000004b&gt;,</div><div class='add'>+					&lt;0x00000007 0x00000051&gt;,</div><div class='add'>+					&lt;0x00000008 0x00000058&gt;,</div><div class='add'>+					&lt;0x00000009 0x0000005e&gt;,</div><div class='add'>+					&lt;0x0000000a 0x00000065&gt;,</div><div class='add'>+					&lt;0x0000000b 0x0000006b&gt;,</div><div class='add'>+</div><div class='add'>+					&lt;0x00010000 0x00000023&gt;,</div><div class='add'>+					&lt;0x00010001 0x0000002b&gt;,</div><div class='add'>+					&lt;0x00010002 0x00000033&gt;,</div><div class='add'>+					&lt;0x00010003 0x0000003b&gt;,</div><div class='add'>+					&lt;0x00010004 0x00000043&gt;,</div><div class='add'>+					&lt;0x00010005 0x0000004b&gt;,</div><div class='add'>+					&lt;0x00010006 0x00000054&gt;,</div><div class='add'>+					&lt;0x00010007 0x0000005c&gt;,</div><div class='add'>+					&lt;0x00010008 0x00000064&gt;,</div><div class='add'>+					&lt;0x00010009 0x0000006c&gt;,</div><div class='add'>+</div><div class='add'>+					&lt;0x00020000 0x00000021&gt;,</div><div class='add'>+					&lt;0x00020001 0x0000002c&gt;,</div><div class='add'>+					&lt;0x00020002 0x00000036&gt;,</div><div class='add'>+					&lt;0x00020003 0x00000040&gt;,</div><div class='add'>+					&lt;0x00020004 0x0000004b&gt;,</div><div class='add'>+					&lt;0x00020005 0x00000055&gt;,</div><div class='add'>+					&lt;0x00020006 0x0000005f&gt;,</div><div class='add'>+</div><div class='add'>+					&lt;0x00030000 0x00000013&gt;,</div><div class='add'>+					&lt;0x00030001 0x0000001d&gt;,</div><div class='add'>+					&lt;0x00030002 0x00000028&gt;,</div><div class='add'>+					&lt;0x00030003 0x00000032&gt;,</div><div class='add'>+					&lt;0x00030004 0x0000003d&gt;,</div><div class='add'>+					&lt;0x00030005 0x00000047&gt;,</div><div class='add'>+					&lt;0x00030006 0x00000052&gt;,</div><div class='add'>+					&lt;0x00030007 0x0000005c&gt;;</div><div class='ctx'> 			#thermal-sensor-cells = &lt;1&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -376,11 +504,11 @@</div><div class='ctx'> 			memory-region = &lt;&amp;bman_fbpr&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		bportals: bman-portals@508000000 {</div><div class='add'>+		bportals: bman-portals-bus@508000000 {</div><div class='ctx'> 			ranges = &lt;0x0 0x5 0x08000000 0x8000000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		qportals: qman-portals@500000000 {</div><div class='add'>+		qportals: qman-portals-bus@500000000 {</div><div class='ctx'> 			ranges = &lt;0x0 0x5 0x00000000 0x8000000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -389,106 +517,114 @@</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			reg = &lt;0x0 0x2100000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 64 0x4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clock-names = "dspi";</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 0&gt;;</div><div class='del'>-			spi-num-chipselects = &lt;5&gt;;</div><div class='del'>-			big-endian;</div><div class='del'>-			status = "disabled";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		dspi1: spi@2110000 {</div><div class='del'>-			compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";</div><div class='del'>-			#address-cells = &lt;1&gt;;</div><div class='del'>-			#size-cells = &lt;0&gt;;</div><div class='del'>-			reg = &lt;0x0 0x2110000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 65 0x4&gt;;</div><div class='del'>-			clock-names = "dspi";</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(1)&gt;;</div><div class='ctx'> 			spi-num-chipselects = &lt;5&gt;;</div><div class='ctx'> 			big-endian;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		i2c0: i2c@2180000 {</div><div class='del'>-			compatible = "fsl,vf610-i2c";</div><div class='add'>+			compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c";</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			reg = &lt;0x0 0x2180000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 56 0x4&gt;;</div><div class='del'>-			clock-names = "i2c";</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 0&gt;;</div><div class='del'>-			dmas = &lt;&amp;edma0 1 39&gt;,</div><div class='del'>-			       &lt;&amp;edma0 1 38&gt;;</div><div class='del'>-			dma-names = "tx", "rx";</div><div class='add'>+			interrupts = &lt;GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clock-names = "ipg";</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(1)&gt;;</div><div class='add'>+			dmas = &lt;&amp;edma0 1 38&gt;,</div><div class='add'>+			       &lt;&amp;edma0 1 39&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		i2c1: i2c@2190000 {</div><div class='del'>-			compatible = "fsl,vf610-i2c";</div><div class='add'>+			compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c";</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			reg = &lt;0x0 0x2190000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 57 0x4&gt;;</div><div class='del'>-			clock-names = "i2c";</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clock-names = "ipg";</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(1)&gt;;</div><div class='add'>+			scl-gpios = &lt;&amp;gpio4 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+			dmas = &lt;&amp;edma0 1 36&gt;,</div><div class='add'>+			       &lt;&amp;edma0 1 37&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		i2c2: i2c@21a0000 {</div><div class='del'>-			compatible = "fsl,vf610-i2c";</div><div class='add'>+			compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c";</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			reg = &lt;0x0 0x21a0000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 58 0x4&gt;;</div><div class='del'>-			clock-names = "i2c";</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clock-names = "ipg";</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(1)&gt;;</div><div class='add'>+			scl-gpios = &lt;&amp;gpio4 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+			dmas = &lt;&amp;edma0 1 34&gt;,</div><div class='add'>+			       &lt;&amp;edma0 1 35&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		i2c3: i2c@21b0000 {</div><div class='del'>-			compatible = "fsl,vf610-i2c";</div><div class='add'>+			compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c";</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			reg = &lt;0x0 0x21b0000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 59 0x4&gt;;</div><div class='del'>-			clock-names = "i2c";</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clock-names = "ipg";</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(1)&gt;;</div><div class='add'>+			scl-gpios = &lt;&amp;gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+			dmas = &lt;&amp;edma0 1 40&gt;,</div><div class='add'>+			       &lt;&amp;edma0 1 41&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		duart0: serial@21c0500 {</div><div class='ctx'> 			compatible = "fsl,ns16550", "ns16550a";</div><div class='ctx'> 			reg = &lt;0x00 0x21c0500 0x0 0x100&gt;;</div><div class='del'>-			interrupts = &lt;0 54 0x4&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(1)&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		duart1: serial@21c0600 {</div><div class='ctx'> 			compatible = "fsl,ns16550", "ns16550a";</div><div class='ctx'> 			reg = &lt;0x00 0x21c0600 0x0 0x100&gt;;</div><div class='del'>-			interrupts = &lt;0 54 0x4&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(1)&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		duart2: serial@21d0500 {</div><div class='ctx'> 			compatible = "fsl,ns16550", "ns16550a";</div><div class='ctx'> 			reg = &lt;0x0 0x21d0500 0x0 0x100&gt;;</div><div class='del'>-			interrupts = &lt;0 55 0x4&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(1)&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		duart3: serial@21d0600 {</div><div class='ctx'> 			compatible = "fsl,ns16550", "ns16550a";</div><div class='ctx'> 			reg = &lt;0x0 0x21d0600 0x0 0x100&gt;;</div><div class='del'>-			interrupts = &lt;0 55 0x4&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(1)&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		gpio1: gpio@2300000 {</div><div class='ctx'> 			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";</div><div class='ctx'> 			reg = &lt;0x0 0x2300000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 66 0x4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			gpio-controller;</div><div class='ctx'> 			#gpio-cells = &lt;2&gt;;</div><div class='ctx'> 			interrupt-controller;</div><div class='hunk'>@@ -498,7 +634,7 @@</div><div class='ctx'> 		gpio2: gpio@2310000 {</div><div class='ctx'> 			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";</div><div class='ctx'> 			reg = &lt;0x0 0x2310000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 67 0x4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			gpio-controller;</div><div class='ctx'> 			#gpio-cells = &lt;2&gt;;</div><div class='ctx'> 			interrupt-controller;</div><div class='hunk'>@@ -508,7 +644,7 @@</div><div class='ctx'> 		gpio3: gpio@2320000 {</div><div class='ctx'> 			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";</div><div class='ctx'> 			reg = &lt;0x0 0x2320000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 68 0x4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			gpio-controller;</div><div class='ctx'> 			#gpio-cells = &lt;2&gt;;</div><div class='ctx'> 			interrupt-controller;</div><div class='hunk'>@@ -518,165 +654,267 @@</div><div class='ctx'> 		gpio4: gpio@2330000 {</div><div class='ctx'> 			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";</div><div class='ctx'> 			reg = &lt;0x0 0x2330000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 134 0x4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			gpio-controller;</div><div class='ctx'> 			#gpio-cells = &lt;2&gt;;</div><div class='ctx'> 			interrupt-controller;</div><div class='ctx'> 			#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		uqe: uqe-bus@2400000 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			compatible = "fsl,qe", "simple-bus";</div><div class='add'>+			ranges = &lt;0x0 0x0 0x2400000 0x40000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x2400000 0x0 0x480&gt;;</div><div class='add'>+			brg-frequency = &lt;100000000&gt;;</div><div class='add'>+			bus-frequency = &lt;200000000&gt;;</div><div class='add'>+			fsl,qe-num-riscs = &lt;1&gt;;</div><div class='add'>+			fsl,qe-num-snums = &lt;28&gt;;</div><div class='add'>+</div><div class='add'>+			qeic: qeic@80 {</div><div class='add'>+				compatible = "fsl,qe-ic";</div><div class='add'>+				reg = &lt;0x80 0x80&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;1&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			si1: si@700 {</div><div class='add'>+				compatible = "fsl,ls1043-qe-si",</div><div class='add'>+						"fsl,t1040-qe-si";</div><div class='add'>+				reg = &lt;0x700 0x80&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			siram1: siram@1000 {</div><div class='add'>+				compatible = "fsl,ls1043-qe-siram",</div><div class='add'>+						"fsl,t1040-qe-siram";</div><div class='add'>+				reg = &lt;0x1000 0x800&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ucc@2000 {</div><div class='add'>+				cell-index = &lt;1&gt;;</div><div class='add'>+				reg = &lt;0x2000 0x200&gt;;</div><div class='add'>+				interrupts = &lt;32&gt;;</div><div class='add'>+				interrupt-parent = &lt;&amp;qeic&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ucc@2200 {</div><div class='add'>+				cell-index = &lt;3&gt;;</div><div class='add'>+				reg = &lt;0x2200 0x200&gt;;</div><div class='add'>+				interrupts = &lt;34&gt;;</div><div class='add'>+				interrupt-parent = &lt;&amp;qeic&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			muram@10000 {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;1&gt;;</div><div class='add'>+				compatible = "fsl,qe-muram", "fsl,cpm-muram";</div><div class='add'>+				ranges = &lt;0x0 0x10000 0x6000&gt;;</div><div class='add'>+</div><div class='add'>+				data-only@0 {</div><div class='add'>+					compatible = "fsl,qe-muram-data",</div><div class='add'>+					"fsl,cpm-muram-data";</div><div class='add'>+					reg = &lt;0x0 0x6000&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		lpuart0: serial@2950000 {</div><div class='ctx'> 			compatible = "fsl,ls1021a-lpuart";</div><div class='ctx'> 			reg = &lt;0x0 0x2950000 0x0 0x1000&gt;;</div><div class='del'>-			interrupts = &lt;0 48 0x4&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 0 0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_SYSCLK 0&gt;;</div><div class='ctx'> 			clock-names = "ipg";</div><div class='add'>+			dmas = &lt;&amp;edma0 1 32&gt;,</div><div class='add'>+			       &lt;&amp;edma0 1 33&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		lpuart1: serial@2960000 {</div><div class='ctx'> 			compatible = "fsl,ls1021a-lpuart";</div><div class='ctx'> 			reg = &lt;0x0 0x2960000 0x0 0x1000&gt;;</div><div class='del'>-			interrupts = &lt;0 49 0x4&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(1)&gt;;</div><div class='ctx'> 			clock-names = "ipg";</div><div class='add'>+			dmas = &lt;&amp;edma0 1 30&gt;,</div><div class='add'>+			       &lt;&amp;edma0 1 31&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		lpuart2: serial@2970000 {</div><div class='ctx'> 			compatible = "fsl,ls1021a-lpuart";</div><div class='ctx'> 			reg = &lt;0x0 0x2970000 0x0 0x1000&gt;;</div><div class='del'>-			interrupts = &lt;0 50 0x4&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(1)&gt;;</div><div class='ctx'> 			clock-names = "ipg";</div><div class='add'>+			dmas = &lt;&amp;edma0 1 28&gt;,</div><div class='add'>+			       &lt;&amp;edma0 1 29&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		lpuart3: serial@2980000 {</div><div class='ctx'> 			compatible = "fsl,ls1021a-lpuart";</div><div class='ctx'> 			reg = &lt;0x0 0x2980000 0x0 0x1000&gt;;</div><div class='del'>-			interrupts = &lt;0 51 0x4&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(1)&gt;;</div><div class='ctx'> 			clock-names = "ipg";</div><div class='add'>+			dmas = &lt;&amp;edma0 1 26&gt;,</div><div class='add'>+			       &lt;&amp;edma0 1 27&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		lpuart4: serial@2990000 {</div><div class='ctx'> 			compatible = "fsl,ls1021a-lpuart";</div><div class='ctx'> 			reg = &lt;0x0 0x2990000 0x0 0x1000&gt;;</div><div class='del'>-			interrupts = &lt;0 52 0x4&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(1)&gt;;</div><div class='ctx'> 			clock-names = "ipg";</div><div class='add'>+			dmas = &lt;&amp;edma0 1 24&gt;,</div><div class='add'>+			       &lt;&amp;edma0 1 25&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		lpuart5: serial@29a0000 {</div><div class='ctx'> 			compatible = "fsl,ls1021a-lpuart";</div><div class='ctx'> 			reg = &lt;0x0 0x29a0000 0x0 0x1000&gt;;</div><div class='del'>-			interrupts = &lt;0 53 0x4&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(1)&gt;;</div><div class='ctx'> 			clock-names = "ipg";</div><div class='add'>+			dmas = &lt;&amp;edma0 1 22&gt;,</div><div class='add'>+			       &lt;&amp;edma0 1 23&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		wdog0: wdog@2ad0000 {</div><div class='add'>+		wdog0: watchdog@2ad0000 {</div><div class='ctx'> 			compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";</div><div class='ctx'> 			reg = &lt;0x0 0x2ad0000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 83 0x4&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 0&gt;;</div><div class='del'>-			clock-names = "wdog";</div><div class='add'>+			interrupts = &lt;GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(1)&gt;;</div><div class='ctx'> 			big-endian;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		edma0: edma@2c00000 {</div><div class='add'>+		edma0: dma-controller@2c00000 {</div><div class='ctx'> 			#dma-cells = &lt;2&gt;;</div><div class='ctx'> 			compatible = "fsl,vf610-edma";</div><div class='ctx'> 			reg = &lt;0x0 0x2c00000 0x0 0x10000&gt;,</div><div class='ctx'> 			      &lt;0x0 0x2c10000 0x0 0x10000&gt;,</div><div class='ctx'> 			      &lt;0x0 0x2c20000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 103 0x4&gt;,</div><div class='del'>-				     &lt;0 103 0x4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			interrupt-names = "edma-tx", "edma-err";</div><div class='ctx'> 			dma-channels = &lt;32&gt;;</div><div class='ctx'> 			big-endian;</div><div class='ctx'> 			clock-names = "dmamux0", "dmamux1";</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 0&gt;,</div><div class='del'>-				 &lt;&amp;clockgen 4 0&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		usb0: usb3@2f00000 {</div><div class='del'>-			compatible = "snps,dwc3";</div><div class='del'>-			reg = &lt;0x0 0x2f00000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 60 0x4&gt;;</div><div class='del'>-			dr_mode = "host";</div><div class='del'>-			snps,quirk-frame-length-adjustment = &lt;0x20&gt;;</div><div class='del'>-			snps,dis_rxdet_inp3_quirk;</div><div class='del'>-			snps,incr-burst-type-adjustment = &lt;1&gt;, &lt;4&gt;, &lt;8&gt;, &lt;16&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		usb1: usb3@3000000 {</div><div class='del'>-			compatible = "snps,dwc3";</div><div class='del'>-			reg = &lt;0x0 0x3000000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 61 0x4&gt;;</div><div class='del'>-			dr_mode = "host";</div><div class='del'>-			snps,quirk-frame-length-adjustment = &lt;0x20&gt;;</div><div class='del'>-			snps,dis_rxdet_inp3_quirk;</div><div class='del'>-			snps,incr-burst-type-adjustment = &lt;1&gt;, &lt;4&gt;, &lt;8&gt;, &lt;16&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		usb2: usb3@3100000 {</div><div class='del'>-			compatible = "snps,dwc3";</div><div class='del'>-			reg = &lt;0x0 0x3100000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 63 0x4&gt;;</div><div class='del'>-			dr_mode = "host";</div><div class='del'>-			snps,quirk-frame-length-adjustment = &lt;0x20&gt;;</div><div class='del'>-			snps,dis_rxdet_inp3_quirk;</div><div class='del'>-			snps,incr-burst-type-adjustment = &lt;1&gt;, &lt;4&gt;, &lt;8&gt;, &lt;16&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		sata: sata@3200000 {</div><div class='del'>-			compatible = "fsl,ls1043a-ahci";</div><div class='del'>-			reg = &lt;0x0 0x3200000 0x0 0x10000&gt;,</div><div class='del'>-				&lt;0x0 0x20140520 0x0 0x4&gt;;</div><div class='del'>-			reg-names = "ahci", "sata-ecc";</div><div class='del'>-			interrupts = &lt;0 69 0x4&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 0&gt;;</div><div class='del'>-			dma-coherent;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(1)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(1)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aux_bus: bus {</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			compatible = "simple-bus";</div><div class='add'>+			ranges;</div><div class='add'>+			dma-ranges = &lt;0x0 0x0 0x0 0x0 0x100 0x00000000&gt;;</div><div class='add'>+</div><div class='add'>+			usb0: usb@2f00000 {</div><div class='add'>+				compatible = "fsl,ls1043a-dwc3", "fsl,ls1028a-dwc3";</div><div class='add'>+				reg = &lt;0x0 0x2f00000 0x0 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				dr_mode = "host";</div><div class='add'>+				dma-coherent;</div><div class='add'>+				snps,quirk-frame-length-adjustment = &lt;0x20&gt;;</div><div class='add'>+				snps,dis_rxdet_inp3_quirk;</div><div class='add'>+				usb3-lpm-capable;</div><div class='add'>+				snps,incr-burst-type-adjustment = &lt;1&gt;, &lt;4&gt;, &lt;8&gt;, &lt;16&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			usb1: usb@3000000 {</div><div class='add'>+				compatible = "fsl,ls1043a-dwc3", "fsl,ls1028a-dwc3";</div><div class='add'>+				reg = &lt;0x0 0x3000000 0x0 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				dr_mode = "host";</div><div class='add'>+				dma-coherent;</div><div class='add'>+				snps,quirk-frame-length-adjustment = &lt;0x20&gt;;</div><div class='add'>+				snps,dis_rxdet_inp3_quirk;</div><div class='add'>+				usb3-lpm-capable;</div><div class='add'>+				snps,incr-burst-type-adjustment = &lt;1&gt;, &lt;4&gt;, &lt;8&gt;, &lt;16&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			usb2: usb@3100000 {</div><div class='add'>+				compatible = "fsl,ls1043a-dwc3", "fsl,ls1028a-dwc3";</div><div class='add'>+				reg = &lt;0x0 0x3100000 0x0 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				dr_mode = "host";</div><div class='add'>+				dma-coherent;</div><div class='add'>+				snps,quirk-frame-length-adjustment = &lt;0x20&gt;;</div><div class='add'>+				snps,dis_rxdet_inp3_quirk;</div><div class='add'>+				usb3-lpm-capable;</div><div class='add'>+				snps,incr-burst-type-adjustment = &lt;1&gt;, &lt;4&gt;, &lt;8&gt;, &lt;16&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sata: sata@3200000 {</div><div class='add'>+				compatible = "fsl,ls1043a-ahci";</div><div class='add'>+				reg = &lt;0x0 0x3200000 0x0 0x10000&gt;,</div><div class='add'>+					&lt;0x0 0x20140520 0x0 0x4&gt;;</div><div class='add'>+				reg-names = "ahci", "sata-ecc";</div><div class='add'>+				interrupts = &lt;GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+						    QORIQ_CLK_PLL_DIV(1)&gt;;</div><div class='add'>+				dma-coherent;</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		msi1: msi-controller1@1571000 {</div><div class='ctx'> 			compatible = "fsl,ls1043a-msi";</div><div class='ctx'> 			reg = &lt;0x0 0x1571000 0x0 0x8&gt;;</div><div class='ctx'> 			msi-controller;</div><div class='del'>-			interrupts = &lt;0 116 0x4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		msi2: msi-controller2@1572000 {</div><div class='ctx'> 			compatible = "fsl,ls1043a-msi";</div><div class='ctx'> 			reg = &lt;0x0 0x1572000 0x0 0x8&gt;;</div><div class='ctx'> 			msi-controller;</div><div class='del'>-			interrupts = &lt;0 126 0x4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		msi3: msi-controller3@1573000 {</div><div class='ctx'> 			compatible = "fsl,ls1043a-msi";</div><div class='ctx'> 			reg = &lt;0x0 0x1573000 0x0 0x8&gt;;</div><div class='ctx'> 			msi-controller;</div><div class='del'>-			interrupts = &lt;0 160 0x4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		pcie@3400000 {</div><div class='add'>+		pcie1: pcie@3400000 {</div><div class='ctx'> 			compatible = "fsl,ls1043a-pcie";</div><div class='del'>-			reg = &lt;0x00 0x03400000 0x0 0x00100000   /* controller registers */</div><div class='del'>-			       0x40 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='add'>+			reg = &lt;0x00 0x03400000 0x0 0x00100000&gt;, /* controller registers */</div><div class='add'>+			      &lt;0x40 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='ctx'> 			reg-names = "regs", "config";</div><div class='del'>-			interrupts = &lt;0 118 0x4&gt;, /* controller interrupt */</div><div class='del'>-				     &lt;0 117 0x4&gt;; /* PME interrupt */</div><div class='del'>-			interrupt-names = "intr", "pme";</div><div class='add'>+			interrupts = &lt;GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "pme", "aer";</div><div class='ctx'> 			#address-cells = &lt;3&gt;;</div><div class='ctx'> 			#size-cells = &lt;2&gt;;</div><div class='ctx'> 			device_type = "pci";</div><div class='del'>-			dma-coherent;</div><div class='ctx'> 			num-viewport = &lt;6&gt;;</div><div class='ctx'> 			bus-range = &lt;0x0 0xff&gt;;</div><div class='ctx'> 			ranges = &lt;0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */</div><div class='hunk'>@@ -688,21 +926,22 @@</div><div class='ctx'> 					&lt;0000 0 0 2 &amp;gic 0 111 0x4&gt;,</div><div class='ctx'> 					&lt;0000 0 0 3 &amp;gic 0 112 0x4&gt;,</div><div class='ctx'> 					&lt;0000 0 0 4 &amp;gic 0 113 0x4&gt;;</div><div class='add'>+			fsl,pcie-scfg = &lt;&amp;scfg 0&gt;;</div><div class='add'>+			big-endian;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		pcie@3500000 {</div><div class='add'>+		pcie2: pcie@3500000 {</div><div class='ctx'> 			compatible = "fsl,ls1043a-pcie";</div><div class='del'>-			reg = &lt;0x00 0x03500000 0x0 0x00100000   /* controller registers */</div><div class='del'>-			       0x48 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='add'>+			reg = &lt;0x00 0x03500000 0x0 0x00100000&gt;, /* controller registers */</div><div class='add'>+			      &lt;0x48 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='ctx'> 			reg-names = "regs", "config";</div><div class='del'>-			interrupts = &lt;0 128 0x4&gt;,</div><div class='del'>-				     &lt;0 127 0x4&gt;;</div><div class='del'>-			interrupt-names = "intr", "pme";</div><div class='add'>+			interrupts = &lt;GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "pme", "aer";</div><div class='ctx'> 			#address-cells = &lt;3&gt;;</div><div class='ctx'> 			#size-cells = &lt;2&gt;;</div><div class='ctx'> 			device_type = "pci";</div><div class='del'>-			dma-coherent;</div><div class='ctx'> 			num-viewport = &lt;6&gt;;</div><div class='ctx'> 			bus-range = &lt;0x0 0xff&gt;;</div><div class='ctx'> 			ranges = &lt;0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */</div><div class='hunk'>@@ -714,21 +953,22 @@</div><div class='ctx'> 					&lt;0000 0 0 2 &amp;gic 0 121 0x4&gt;,</div><div class='ctx'> 					&lt;0000 0 0 3 &amp;gic 0 122 0x4&gt;,</div><div class='ctx'> 					&lt;0000 0 0 4 &amp;gic 0 123 0x4&gt;;</div><div class='add'>+			fsl,pcie-scfg = &lt;&amp;scfg 1&gt;;</div><div class='add'>+			big-endian;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		pcie@3600000 {</div><div class='add'>+		pcie3: pcie@3600000 {</div><div class='ctx'> 			compatible = "fsl,ls1043a-pcie";</div><div class='del'>-			reg = &lt;0x00 0x03600000 0x0 0x00100000   /* controller registers */</div><div class='del'>-			       0x50 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='add'>+			reg = &lt;0x00 0x03600000 0x0 0x00100000&gt;, /* controller registers */</div><div class='add'>+			      &lt;0x50 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='ctx'> 			reg-names = "regs", "config";</div><div class='del'>-			interrupts = &lt;0 162 0x4&gt;,</div><div class='del'>-				     &lt;0 161 0x4&gt;;</div><div class='del'>-			interrupt-names = "intr", "pme";</div><div class='add'>+			interrupts = &lt;GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "pme", "aer";</div><div class='ctx'> 			#address-cells = &lt;3&gt;;</div><div class='ctx'> 			#size-cells = &lt;2&gt;;</div><div class='ctx'> 			device_type = "pci";</div><div class='del'>-			dma-coherent;</div><div class='ctx'> 			num-viewport = &lt;6&gt;;</div><div class='ctx'> 			bus-range = &lt;0x0 0xff&gt;;</div><div class='ctx'> 			ranges = &lt;0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000   /* downstream I/O */</div><div class='hunk'>@@ -740,11 +980,13 @@</div><div class='ctx'> 					&lt;0000 0 0 2 &amp;gic 0 155 0x4&gt;,</div><div class='ctx'> 					&lt;0000 0 0 3 &amp;gic 0 156 0x4&gt;,</div><div class='ctx'> 					&lt;0000 0 0 4 &amp;gic 0 157 0x4&gt;;</div><div class='add'>+			fsl,pcie-scfg = &lt;&amp;scfg 2&gt;;</div><div class='add'>+			big-endian;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		qdma: dma-controller@8380000 {</div><div class='del'>-			compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma";</div><div class='add'>+			compatible = "fsl,ls1043a-qdma", "fsl,ls1021a-qdma";</div><div class='ctx'> 			reg = &lt;0x0 0x8380000 0x0 0x1000&gt;, /* Controller regs */</div><div class='ctx'> 			      &lt;0x0 0x8390000 0x0 0x10000&gt;, /* Status regs */</div><div class='ctx'> 			      &lt;0x0 0x83a0000 0x0 0x40000&gt;; /* Block regs */</div><div class='hunk'>@@ -755,6 +997,7 @@</div><div class='ctx'> 				     &lt;GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			interrupt-names = "qdma-error", "qdma-queue0",</div><div class='ctx'> 				"qdma-queue1", "qdma-queue2", "qdma-queue3";</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='ctx'> 			dma-channels = &lt;8&gt;;</div><div class='ctx'> 			block-number = &lt;1&gt;;</div><div class='ctx'> 			block-offset = &lt;0x10000&gt;;</div><div class='hunk'>@@ -764,6 +1007,19 @@</div><div class='ctx'> 			big-endian;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		rcpm: wakeup-controller@1ee2140 {</div><div class='add'>+			compatible = "fsl,ls1043a-rcpm", "fsl,qoriq-rcpm-2.1+";</div><div class='add'>+			reg = &lt;0x0 0x1ee2140 0x0 0x4&gt;;</div><div class='add'>+			#fsl,rcpm-wakeup-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ftm_alarm0: rtc@29d0000 {</div><div class='add'>+			compatible = "fsl,ls1043a-ftm-alarm";</div><div class='add'>+			reg = &lt;0x0 0x29d0000 0x0 0x10000&gt;;</div><div class='add'>+			fsl,rcpm-wakeup = &lt;&amp;rcpm 0x20000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			big-endian;</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	firmware {</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi<br/>index d6caaea57d90..15ff7c569d28 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi</a></div><div class='hunk'>@@ -23,6 +23,9 @@</div><div class='ctx'> &amp;fman0 {</div><div class='ctx'> 	/* these aliases provide the FMan ports mapping */</div><div class='ctx'> 	enet0: ethernet@e0000 {</div><div class='add'>+		pcsphy-handle = &lt;&amp;qsgmiib_pcs3&gt;;</div><div class='add'>+		pcs-handle = &lt;&amp;qsgmiib_pcs3&gt;;</div><div class='add'>+		pcs-handle-names = "qsgmii";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	enet1: ethernet@e2000 {</div><div class='hunk'>@@ -35,14 +38,40 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	enet4: ethernet@e8000 {</div><div class='add'>+		pcsphy-handle = &lt;&amp;pcsphy4&gt;, &lt;&amp;qsgmiib_pcs1&gt;;</div><div class='add'>+		pcs-handle = &lt;&amp;pcsphy4&gt;, &lt;&amp;qsgmiib_pcs1&gt;;</div><div class='add'>+		pcs-handle-names = "sgmii", "qsgmii";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	enet5: ethernet@ea000 {</div><div class='add'>+		pcsphy-handle = &lt;&amp;pcsphy5&gt;, &lt;&amp;pcsphy5&gt;;</div><div class='add'>+		pcs-handle = &lt;&amp;pcsphy5&gt;, &lt;&amp;pcsphy5&gt;;</div><div class='add'>+		pcs-handle-names = "sgmii", "qsgmii";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	enet6: ethernet@f0000 {</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	enet7: ethernet@f2000 {</div><div class='add'>+		pcsphy-handle = &lt;&amp;pcsphy7&gt;, &lt;&amp;qsgmiib_pcs2&gt;, &lt;&amp;pcsphy7&gt;;</div><div class='add'>+		pcs-handle = &lt;&amp;pcsphy7&gt;, &lt;&amp;qsgmiib_pcs2&gt;, &lt;&amp;pcsphy7&gt;;</div><div class='add'>+		pcs-handle-names = "sgmii", "qsgmii", "xfi";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mdio@eb000 {</div><div class='add'>+		qsgmiib_pcs1: ethernet-pcs@1 {</div><div class='add'>+			compatible = "fsl,lynx-pcs";</div><div class='add'>+			reg = &lt;0x1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qsgmiib_pcs2: ethernet-pcs@2 {</div><div class='add'>+			compatible = "fsl,lynx-pcs";</div><div class='add'>+			reg = &lt;0x2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qsgmiib_pcs3: ethernet-pcs@3 {</div><div class='add'>+			compatible = "fsl,lynx-pcs";</div><div class='add'>+			reg = &lt;0x3&gt;;</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy.dts<br/>index db3d303093f6..6d22efbd645c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy.dts</a></div><div class='hunk'>@@ -83,15 +83,9 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			eeprom@52 {</div><div class='del'>-				compatible = "atmel,24c512";</div><div class='add'>+				compatible = "onnn,cat24c04", "atmel,24c04";</div><div class='ctx'> 				reg = &lt;0x52&gt;;</div><div class='ctx'> 			};</div><div class='del'>-</div><div class='del'>-			eeprom@53 {</div><div class='del'>-				compatible = "atmel,24c512";</div><div class='del'>-				reg = &lt;0x53&gt;;</div><div class='del'>-			};</div><div class='del'>-</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts<br/>index eec62c63dafe..48a6c08fcea8 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts</a></div><div class='hunk'>@@ -3,7 +3,7 @@</div><div class='ctx'>  * Device Tree Include file for Freescale Layerscape-1046A family SoC.</div><div class='ctx'>  *</div><div class='ctx'>  * Copyright 2016 Freescale Semiconductor, Inc.</div><div class='del'>- * Copyright 2018 NXP</div><div class='add'>+ * Copyright 2018-2019 NXP</div><div class='ctx'>  *</div><div class='ctx'>  * Shaohui Xie &lt;Shaohui.Xie@nxp.com&gt;</div><div class='ctx'>  */</div><div class='hunk'>@@ -17,19 +17,46 @@</div><div class='ctx'> 	compatible = "fsl,ls1046a-qds", "fsl,ls1046a";</div><div class='ctx'> </div><div class='ctx'> 	aliases {</div><div class='add'>+		emi1-slot1 = &amp;ls1046mdio_s1;</div><div class='add'>+		emi1-slot2 = &amp;ls1046mdio_s2;</div><div class='add'>+		emi1-slot4 = &amp;ls1046mdio_s4;</div><div class='ctx'> 		gpio0 = &amp;gpio0;</div><div class='ctx'> 		gpio1 = &amp;gpio1;</div><div class='ctx'> 		gpio2 = &amp;gpio2;</div><div class='ctx'> 		gpio3 = &amp;gpio3;</div><div class='add'>+		qsgmii-s2-p1 = &amp;qsgmii_phy_s2_p1;</div><div class='add'>+		qsgmii-s2-p2 = &amp;qsgmii_phy_s2_p2;</div><div class='add'>+		qsgmii-s2-p3 = &amp;qsgmii_phy_s2_p3;</div><div class='add'>+		qsgmii-s2-p4 = &amp;qsgmii_phy_s2_p4;</div><div class='ctx'> 		serial0 = &amp;duart0;</div><div class='ctx'> 		serial1 = &amp;duart1;</div><div class='ctx'> 		serial2 = &amp;duart2;</div><div class='ctx'> 		serial3 = &amp;duart3;</div><div class='add'>+		sgmii-s1-p1 = &amp;sgmii_phy_s1_p1;</div><div class='add'>+		sgmii-s1-p2 = &amp;sgmii_phy_s1_p2;</div><div class='add'>+		sgmii-s1-p3 = &amp;sgmii_phy_s1_p3;</div><div class='add'>+		sgmii-s1-p4 = &amp;sgmii_phy_s1_p4;</div><div class='add'>+		sgmii-s4-p1 = &amp;sgmii_phy_s4_p1;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	chosen {</div><div class='ctx'> 		stdout-path = "serial0:115200n8";</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	sfp1: sfp-1 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;sfp1_i2c&gt;;</div><div class='add'>+		maximum-power-milliwatt = &lt;2000&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;stat_pres2 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp2: sfp-2 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;sfp2_i2c&gt;;</div><div class='add'>+		maximum-power-milliwatt = &lt;2000&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;stat_pres2 7 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;dspi {</div><div class='hunk'>@@ -57,7 +84,7 @@</div><div class='ctx'> 	flash@2 {</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;1&gt;;</div><div class='del'>-		compatible = "en25s64", "jedec,spi-nor";</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='ctx'> 		spi-cpol;</div><div class='ctx'> 		spi-cpha;</div><div class='ctx'> 		reg = &lt;2&gt;;</div><div class='hunk'>@@ -76,7 +103,7 @@</div><div class='ctx'> &amp;i2c0 {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='del'>-	pca9547@77 {</div><div class='add'>+	i2c-mux@77 {</div><div class='ctx'> 		compatible = "nxp,pca9547";</div><div class='ctx'> 		reg = &lt;0x77&gt;;</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='hunk'>@@ -127,6 +154,31 @@</div><div class='ctx'> 				reg = &lt;0x4c&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='add'>+</div><div class='add'>+		i2c@7 {</div><div class='add'>+			reg = &lt;0x7&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			i2c-mux@76 {</div><div class='add'>+				compatible = "nxp,pca9547";</div><div class='add'>+				reg = &lt;0x76&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				sfp1_i2c: i2c@6 {</div><div class='add'>+					reg = &lt;0x6&gt;;</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				sfp2_i2c: i2c@7 {</div><div class='add'>+					reg = &lt;0x7&gt;;</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -139,7 +191,7 @@</div><div class='ctx'> 		  0x2 0x0 0x0 0x7fb00000 0x00000100&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='del'>-	nor@0,0 {</div><div class='add'>+	flash@0,0 {</div><div class='ctx'> 		compatible = "cfi-flash";</div><div class='ctx'> 		reg = &lt;0x0 0x0 0x8000000&gt;;</div><div class='ctx'> 		big-endian;</div><div class='hunk'>@@ -153,8 +205,21 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	fpga: board-control@2,0 {</div><div class='del'>-		compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis";</div><div class='add'>+		compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis", "simple-mfd";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='ctx'> 		reg = &lt;0x2 0x0 0x0000100&gt;;</div><div class='add'>+		ranges = &lt;0 2 0 0x100&gt;;</div><div class='add'>+</div><div class='add'>+		stat_pres2: gpio@c {</div><div class='add'>+			compatible = "fsl,ls1046aqds-fpga-gpio-stat-pres2";</div><div class='add'>+			reg = &lt;0xc 1&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-line-names =</div><div class='add'>+				"SLOT1", "SLOT2", "SLOT3", "SLOT4", "SLOT5", "SLOT6",</div><div class='add'>+				"SFP1_MOD_DEF", "SFP2_MOD_DEF";</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -169,7 +234,7 @@</div><div class='ctx'> 		compatible = "spansion,m25p80";</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;1&gt;;</div><div class='del'>-		spi-max-frequency = &lt;20000000&gt;;</div><div class='add'>+		spi-max-frequency = &lt;50000000&gt;;</div><div class='ctx'> 		spi-rx-bus-width = &lt;4&gt;;</div><div class='ctx'> 		spi-tx-bus-width = &lt;4&gt;;</div><div class='ctx'> 		reg = &lt;0&gt;;</div><div class='hunk'>@@ -177,3 +242,141 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #include "fsl-ls1046-post.dtsi"</div><div class='add'>+</div><div class='add'>+&amp;fman0 {</div><div class='add'>+	ethernet@e0000 {</div><div class='add'>+		phy-handle = &lt;&amp;qsgmii_phy_s2_p1&gt;;</div><div class='add'>+		phy-connection-type = "sgmii";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ethernet@e2000 {</div><div class='add'>+		phy-handle = &lt;&amp;sgmii_phy_s4_p1&gt;;</div><div class='add'>+		phy-connection-type = "sgmii";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ethernet@e4000 {</div><div class='add'>+		phy-handle = &lt;&amp;rgmii_phy1&gt;;</div><div class='add'>+		phy-connection-type = "rgmii";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ethernet@e6000 {</div><div class='add'>+		phy-handle = &lt;&amp;rgmii_phy2&gt;;</div><div class='add'>+		phy-connection-type = "rgmii";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ethernet@e8000 {</div><div class='add'>+		phy-handle = &lt;&amp;sgmii_phy_s1_p3&gt;;</div><div class='add'>+		phy-connection-type = "sgmii";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ethernet@ea000 {</div><div class='add'>+		phy-handle = &lt;&amp;sgmii_phy_s1_p4&gt;;</div><div class='add'>+		phy-connection-type = "sgmii";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ethernet@f0000 { /* DTSEC9/10GEC1 */</div><div class='add'>+		phy-handle = &lt;&amp;sgmii_phy_s1_p1&gt;;</div><div class='add'>+		phy-connection-type = "xgmii";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ethernet@f2000 { /* DTSEC10/10GEC2 */</div><div class='add'>+		phy-handle = &lt;&amp;sgmii_phy_s1_p2&gt;;</div><div class='add'>+		phy-connection-type = "xgmii";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fpga {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+	mdio-mux@54 {</div><div class='add'>+		compatible = "mdio-mux-mmioreg", "mdio-mux";</div><div class='add'>+		mdio-parent-bus = &lt;&amp;mdio0&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		reg = &lt;0x54 1&gt;;    /* BRDCFG4 */</div><div class='add'>+		mux-mask = &lt;0xe0&gt;; /* EMI1 */</div><div class='add'>+</div><div class='add'>+		/* On-board RGMII1 PHY */</div><div class='add'>+		ls1046mdio0: mdio@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			rgmii_phy1: ethernet-phy@1 { /* MAC3 */</div><div class='add'>+				reg = &lt;0x1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* On-board RGMII2 PHY */</div><div class='add'>+		ls1046mdio1: mdio@1 {</div><div class='add'>+			reg = &lt;0x20&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			rgmii_phy2: ethernet-phy@2 { /* MAC4 */</div><div class='add'>+				reg = &lt;0x2&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* Slot 1 */</div><div class='add'>+		ls1046mdio_s1: mdio@2 {</div><div class='add'>+			reg = &lt;0x40&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			sgmii_phy_s1_p1: ethernet-phy@1c {</div><div class='add'>+				reg = &lt;0x1c&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sgmii_phy_s1_p2: ethernet-phy@1d {</div><div class='add'>+				reg = &lt;0x1d&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sgmii_phy_s1_p3: ethernet-phy@1e {</div><div class='add'>+				reg = &lt;0x1e&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sgmii_phy_s1_p4: ethernet-phy@1f {</div><div class='add'>+				reg = &lt;0x1f&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* Slot 2 */</div><div class='add'>+		ls1046mdio_s2: mdio@3 {</div><div class='add'>+			reg = &lt;0x60&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			qsgmii_phy_s2_p1: ethernet-phy@8 {</div><div class='add'>+				reg = &lt;0x8&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qsgmii_phy_s2_p2: ethernet-phy@9 {</div><div class='add'>+				reg = &lt;0x9&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qsgmii_phy_s2_p3: ethernet-phy@a {</div><div class='add'>+				reg = &lt;0xa&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qsgmii_phy_s2_p4: ethernet-phy@b {</div><div class='add'>+				reg = &lt;0xb&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* Slot 4 */</div><div class='add'>+		ls1046mdio_s4: mdio@5 {</div><div class='add'>+			reg = &lt;0x80&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			sgmii_phy_s4_p1: ethernet-phy@1c {</div><div class='add'>+				reg = &lt;0x1c&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts<br/>index d53ccc56bb63..07f6cc6e354a 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts</a></div><div class='hunk'>@@ -3,6 +3,7 @@</div><div class='ctx'>  * Device Tree Include file for Freescale Layerscape-1046A family SoC.</div><div class='ctx'>  *</div><div class='ctx'>  * Copyright 2016 Freescale Semiconductor, Inc.</div><div class='add'>+ * Copyright 2019-2020 NXP</div><div class='ctx'>  *</div><div class='ctx'>  * Mingkai Hu &lt;mingkai.hu@nxp.com&gt;</div><div class='ctx'>  */</div><div class='hunk'>@@ -58,14 +59,9 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	eeprom@52 {</div><div class='del'>-		compatible = "atmel,24c512";</div><div class='add'>+		compatible = "onnn,cat24c05", "atmel,24c04";</div><div class='ctx'> 		reg = &lt;0x52&gt;;</div><div class='ctx'> 	};</div><div class='del'>-</div><div class='del'>-	eeprom@53 {</div><div class='del'>-		compatible = "atmel,24c512";</div><div class='del'>-		reg = &lt;0x53&gt;;</div><div class='del'>-	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;i2c3 {</div><div class='hunk'>@@ -74,6 +70,8 @@</div><div class='ctx'> 	rtc@51 {</div><div class='ctx'> 		compatible = "nxp,pcf2129";</div><div class='ctx'> 		reg = &lt;0x51&gt;;</div><div class='add'>+		/* IRQ_RTC_B -&gt; IRQ05, active low */</div><div class='add'>+		interrupts-extended = &lt;&amp;extirq 5 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -155,8 +153,8 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	ethernet@f2000 { /* 10GEC2 */</div><div class='del'>-		fixed-link = &lt;0 1 1000 0 0&gt;;</div><div class='del'>-		phy-connection-type = "xgmii";</div><div class='add'>+		phy-connection-type = "10gbase-r";</div><div class='add'>+		managed = "in-band-status";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	mdio@fc000 {</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-tqmls1046a-mbls10xxa.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-tqmls1046a-mbls10xxa.dts<br/>new file mode 100644<br/>index 000000000000..43261cda3fcf<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1046a-tqmls1046a-mbls10xxa.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls1046a-tqmls1046a-mbls10xxa.dts</a></div><div class='hunk'>@@ -0,0 +1,76 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2018-2023 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Gregor Herburger, Timo Herbrecher</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+</div><div class='add'>+#include "fsl-ls1046a-tqmls1046a.dtsi"</div><div class='add'>+#include "tqmls10xxa-mbls10xxa.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "TQ-Systems GmbH LS1046A TQMLS1046A SoM on MBLS10xxA board";</div><div class='add'>+	compatible = "tq,ls1046a-tqmls1046a-mbls10xxa", "tq,ls1046a-tqmls1046a",</div><div class='add'>+		     "fsl,ls1046a";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		qsgmii-s1-p1 = &amp;qsgmii1_phy1;</div><div class='add'>+		qsgmii-s1-p2 = &amp;qsgmii1_phy2;</div><div class='add'>+		qsgmii-s1-p3 = &amp;qsgmii1_phy3;</div><div class='add'>+		qsgmii-s1-p4 = &amp;qsgmii1_phy4;</div><div class='add'>+		qsgmii-s2-p1 = &amp;qsgmii2_phy1;</div><div class='add'>+		qsgmii-s2-p2 = &amp;qsgmii2_phy2;</div><div class='add'>+		qsgmii-s2-p3 = &amp;qsgmii2_phy3;</div><div class='add'>+		qsgmii-s2-p4 = &amp;qsgmii2_phy4;</div><div class='add'>+		serial0 = &amp;duart0;</div><div class='add'>+		serial1 = &amp;duart1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;duart1;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dspi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;esdhc {</div><div class='add'>+	cd-gpios = &lt;&amp;gpio3 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	wp-gpios = &lt;&amp;gpio3 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sfp1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sfp2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sfp1_i2c {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sfp2_i2c {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include "fsl-ls1046-post.dtsi"</div><div class='add'>+#include "tqmls104xa-mbls10xxa-fman.dtsi"</div><div class='add'>+</div><div class='add'>+&amp;enet6 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;enet7 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-tqmls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a-tqmls1046a.dtsi<br/>new file mode 100644<br/>index 000000000000..fa543db99def<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1046a-tqmls1046a.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls1046a-tqmls1046a.dtsi</a></div><div class='hunk'>@@ -0,0 +1,42 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2018-2023 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Gregor Herburger, Timo Herbrecher</div><div class='add'>+ *</div><div class='add'>+ * Device Tree Include file for LS1046A based SoM of TQ</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "fsl-ls1046a.dtsi"</div><div class='add'>+#include "tqmls10xxa.dtsi"</div><div class='add'>+</div><div class='add'>+&amp;qspi {</div><div class='add'>+	num-cs = &lt;2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	qflash0: flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;62500000&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;4&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_vcc1v8&gt;;</div><div class='add'>+</div><div class='add'>+		partitions {</div><div class='add'>+			compatible = "fixed-partitions";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	qflash1: flash@1 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		spi-max-frequency = &lt;62500000&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;4&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_vcc1v8&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi<br/>index d4c1da3d4bde..22173d69713d 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi</a></div><div class='hunk'>@@ -1,15 +1,17 @@</div><div class='ctx'> // SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='ctx'> /*</div><div class='del'>- * Device Tree Include file for Freescale Layerscape-1046A family SoC.</div><div class='add'>+ * Device Tree Include file for NXP Layerscape-1046A family SoC.</div><div class='ctx'>  *</div><div class='ctx'>  * Copyright 2016 Freescale Semiconductor, Inc.</div><div class='del'>- * Copyright 2018 NXP</div><div class='add'>+ * Copyright 2018, 2020 NXP</div><div class='ctx'>  *</div><div class='ctx'>  * Mingkai Hu &lt;mingkai.hu@nxp.com&gt;</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+#include &lt;dt-bindings/clock/fsl,qoriq-clockgen.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/thermal/thermal.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	compatible = "fsl,ls1046a";</div><div class='hunk'>@@ -28,6 +30,7 @@</div><div class='ctx'> 		ethernet5 = &amp;enet5;</div><div class='ctx'> 		ethernet6 = &amp;enet6;</div><div class='ctx'> 		ethernet7 = &amp;enet7;</div><div class='add'>+		rtc1 = &amp;ftm_alarm0;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	cpus {</div><div class='hunk'>@@ -38,7 +41,7 @@</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			compatible = "arm,cortex-a72";</div><div class='ctx'> 			reg = &lt;0x0&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 1 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 0&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;l2&gt;;</div><div class='ctx'> 			cpu-idle-states = &lt;&amp;CPU_PH20&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='hunk'>@@ -48,7 +51,7 @@</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			compatible = "arm,cortex-a72";</div><div class='ctx'> 			reg = &lt;0x1&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 1 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 0&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;l2&gt;;</div><div class='ctx'> 			cpu-idle-states = &lt;&amp;CPU_PH20&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='hunk'>@@ -58,7 +61,7 @@</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			compatible = "arm,cortex-a72";</div><div class='ctx'> 			reg = &lt;0x2&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 1 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 0&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;l2&gt;;</div><div class='ctx'> 			cpu-idle-states = &lt;&amp;CPU_PH20&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='hunk'>@@ -68,7 +71,7 @@</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			compatible = "arm,cortex-a72";</div><div class='ctx'> 			reg = &lt;0x3&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 1 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 0&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;l2&gt;;</div><div class='ctx'> 			cpu-idle-states = &lt;&amp;CPU_PH20&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='hunk'>@@ -76,6 +79,8 @@</div><div class='ctx'> </div><div class='ctx'> 		l2: l2-cache {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -110,26 +115,86 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	reboot {</div><div class='del'>-		compatible ="syscon-reboot";</div><div class='add'>+		compatible = "syscon-reboot";</div><div class='ctx'> 		regmap = &lt;&amp;dcfg&gt;;</div><div class='ctx'> 		offset = &lt;0xb0&gt;;</div><div class='ctx'> 		mask = &lt;0x02&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	thermal-zones {</div><div class='del'>-		cpu_thermal: cpu-thermal {</div><div class='add'>+		ddr-thermal {</div><div class='add'>+			polling-delay-passive = &lt;1000&gt;;</div><div class='add'>+			polling-delay = &lt;5000&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;tmu 0&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				ddr-ctrler-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				ddr-ctrler-crit {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		serdes-thermal {</div><div class='add'>+			polling-delay-passive = &lt;1000&gt;;</div><div class='add'>+			polling-delay = &lt;5000&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;tmu 1&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				serdes-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				serdes-crit {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		fman-thermal {</div><div class='add'>+			polling-delay-passive = &lt;1000&gt;;</div><div class='add'>+			polling-delay = &lt;5000&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;tmu 2&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				fman-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				fman-crit {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cluster-thermal {</div><div class='ctx'> 			polling-delay-passive = &lt;1000&gt;;</div><div class='ctx'> 			polling-delay = &lt;5000&gt;;</div><div class='ctx'> 			thermal-sensors = &lt;&amp;tmu 3&gt;;</div><div class='ctx'> </div><div class='ctx'> 			trips {</div><div class='del'>-				cpu_alert: cpu-alert {</div><div class='add'>+				core_cluster_alert: core-cluster-alert {</div><div class='ctx'> 					temperature = &lt;85000&gt;;</div><div class='ctx'> 					hysteresis = &lt;2000&gt;;</div><div class='ctx'> 					type = "passive";</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				cpu_crit: cpu-crit {</div><div class='add'>+				core_cluster_crit: core-cluster-crit {</div><div class='ctx'> 					temperature = &lt;95000&gt;;</div><div class='ctx'> 					hysteresis = &lt;2000&gt;;</div><div class='ctx'> 					type = "critical";</div><div class='hunk'>@@ -138,7 +203,7 @@</div><div class='ctx'> </div><div class='ctx'> 			cooling-maps {</div><div class='ctx'> 				map0 {</div><div class='del'>-					trip = &lt;&amp;cpu_alert&gt;;</div><div class='add'>+					trip = &lt;&amp;core_cluster_alert&gt;;</div><div class='ctx'> 					cooling-device =</div><div class='ctx'> 						&lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='ctx'> 						&lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='hunk'>@@ -147,6 +212,26 @@</div><div class='ctx'> 				};</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='add'>+</div><div class='add'>+		sec-thermal {</div><div class='add'>+			polling-delay-passive = &lt;1000&gt;;</div><div class='add'>+			polling-delay = &lt;5000&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;tmu 4&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				sec-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				sec-crit {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	timer {</div><div class='hunk'>@@ -175,6 +260,7 @@</div><div class='ctx'> </div><div class='ctx'> 	gic: interrupt-controller@1400000 {</div><div class='ctx'> 		compatible = "arm,gic-400";</div><div class='add'>+		#address-cells = &lt;0&gt;;</div><div class='ctx'> 		#interrupt-cells = &lt;3&gt;;</div><div class='ctx'> 		interrupt-controller;</div><div class='ctx'> 		reg = &lt;0x0 0x1410000 0 0x10000&gt;, /* GICD */</div><div class='hunk'>@@ -190,16 +276,17 @@</div><div class='ctx'> 		#address-cells = &lt;2&gt;;</div><div class='ctx'> 		#size-cells = &lt;2&gt;;</div><div class='ctx'> 		ranges;</div><div class='add'>+		dma-ranges = &lt;0x0 0x0 0x0 0x0 0x10000 0x00000000&gt;;</div><div class='add'>+		dma-coherent;</div><div class='ctx'> </div><div class='ctx'> 		ddr: memory-controller@1080000 {</div><div class='ctx'> 			compatible = "fsl,qoriq-memory-controller";</div><div class='ctx'> 			reg = &lt;0x0 0x1080000 0x0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			big-endian;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		ifc: ifc@1530000 {</div><div class='del'>-			compatible = "fsl,ifc", "simple-bus";</div><div class='add'>+		ifc: memory-controller@1530000 {</div><div class='add'>+			compatible = "fsl,ifc";</div><div class='ctx'> 			reg = &lt;0x0 0x1530000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='hunk'>@@ -214,18 +301,20 @@</div><div class='ctx'> 			reg-names = "QuadSPI", "QuadSPI-memory";</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clock-names = "qspi_en", "qspi";</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 1&gt;, &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		esdhc: esdhc@1560000 {</div><div class='add'>+		esdhc: mmc@1560000 {</div><div class='ctx'> 			compatible = "fsl,ls1046a-esdhc", "fsl,esdhc";</div><div class='ctx'> 			reg = &lt;0x0 0x1560000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 2 1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_HWACCEL 1&gt;;</div><div class='ctx'> 			voltage-ranges = &lt;1800 1800 3300 3300&gt;;</div><div class='ctx'> 			sdhci,auto-cmd12;</div><div class='del'>-			big-endian;</div><div class='ctx'> 			bus-width = &lt;4&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -233,6 +322,31 @@</div><div class='ctx'> 			compatible = "fsl,ls1046a-scfg", "syscon";</div><div class='ctx'> 			reg = &lt;0x0 0x1570000 0x0 0x10000&gt;;</div><div class='ctx'> 			big-endian;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges = &lt;0x0 0x0 0x1570000 0x10000&gt;;</div><div class='add'>+</div><div class='add'>+			extirq: interrupt-controller@1ac {</div><div class='add'>+				compatible = "fsl,ls1046a-extirq", "fsl,ls1043a-extirq";</div><div class='add'>+				#interrupt-cells = &lt;2&gt;;</div><div class='add'>+				#address-cells = &lt;0&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				reg = &lt;0x1ac 4&gt;;</div><div class='add'>+				interrupt-map =</div><div class='add'>+					&lt;0 0 &amp;gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;1 0 &amp;gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;2 0 &amp;gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;3 0 &amp;gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;4 0 &amp;gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;5 0 &amp;gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;6 0 &amp;gic GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;7 0 &amp;gic GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;8 0 &amp;gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;9 0 &amp;gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;10 0 &amp;gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;11 0 &amp;gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				interrupt-map-mask = &lt;0xf 0x0&gt;;</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		crypto: crypto@1700000 {</div><div class='hunk'>@@ -249,7 +363,7 @@</div><div class='ctx'> 				compatible = "fsl,sec-v5.4-job-ring",</div><div class='ctx'> 					     "fsl,sec-v5.0-job-ring",</div><div class='ctx'> 					     "fsl,sec-v4.0-job-ring";</div><div class='del'>-				reg	   = &lt;0x10000 0x10000&gt;;</div><div class='add'>+				reg = &lt;0x10000 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -257,7 +371,7 @@</div><div class='ctx'> 				compatible = "fsl,sec-v5.4-job-ring",</div><div class='ctx'> 					     "fsl,sec-v5.0-job-ring",</div><div class='ctx'> 					     "fsl,sec-v4.0-job-ring";</div><div class='del'>-				reg	   = &lt;0x20000 0x10000&gt;;</div><div class='add'>+				reg = &lt;0x20000 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -265,7 +379,7 @@</div><div class='ctx'> 				compatible = "fsl,sec-v5.4-job-ring",</div><div class='ctx'> 					     "fsl,sec-v5.0-job-ring",</div><div class='ctx'> 					     "fsl,sec-v4.0-job-ring";</div><div class='del'>-				reg	   = &lt;0x30000 0x10000&gt;;</div><div class='add'>+				reg = &lt;0x30000 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -273,7 +387,7 @@</div><div class='ctx'> 				compatible = "fsl,sec-v5.4-job-ring",</div><div class='ctx'> 					     "fsl,sec-v5.0-job-ring",</div><div class='ctx'> 					     "fsl,sec-v4.0-job-ring";</div><div class='del'>-				reg	   = &lt;0x40000 0x10000&gt;;</div><div class='add'>+				reg = &lt;0x40000 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='hunk'>@@ -294,17 +408,25 @@</div><div class='ctx'> </div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		qportals: qman-portals@500000000 {</div><div class='add'>+		qportals: qman-portals-bus@500000000 {</div><div class='ctx'> 			ranges = &lt;0x0 0x5 0x00000000 0x8000000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		bportals: bman-portals@508000000 {</div><div class='add'>+		bportals: bman-portals-bus@508000000 {</div><div class='ctx'> 			ranges = &lt;0x0 0x5 0x08000000 0x8000000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		sfp: efuse@1e80000 {</div><div class='add'>+			compatible = "fsl,ls1021a-sfp";</div><div class='add'>+			reg = &lt;0x0 0x1e80000 0x0 0x10000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='add'>+			clock-names = "sfp";</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		dcfg: dcfg@1ee0000 {</div><div class='ctx'> 			compatible = "fsl,ls1046a-dcfg", "syscon";</div><div class='del'>-			reg = &lt;0x0 0x1ee0000 0x0 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x1ee0000 0x0 0x1000&gt;;</div><div class='ctx'> 			big-endian;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -318,47 +440,50 @@</div><div class='ctx'> 		tmu: tmu@1f00000 {</div><div class='ctx'> 			compatible = "fsl,qoriq-tmu";</div><div class='ctx'> 			reg = &lt;0x0 0x1f00000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 33 0x4&gt;;</div><div class='del'>-			fsl,tmu-range = &lt;0xb0000 0x9002a 0x6004c 0x30062&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			fsl,tmu-range = &lt;0xb0000 0x9002a 0x6004c 0x70062&gt;;</div><div class='ctx'> 			fsl,tmu-calibration =</div><div class='ctx'> 				/* Calibration data group 1 */</div><div class='del'>-				&lt;0x00000000 0x00000026</div><div class='del'>-				0x00000001 0x0000002d</div><div class='del'>-				0x00000002 0x00000032</div><div class='del'>-				0x00000003 0x00000039</div><div class='del'>-				0x00000004 0x0000003f</div><div class='del'>-				0x00000005 0x00000046</div><div class='del'>-				0x00000006 0x0000004d</div><div class='del'>-				0x00000007 0x00000054</div><div class='del'>-				0x00000008 0x0000005a</div><div class='del'>-				0x00000009 0x00000061</div><div class='del'>-				0x0000000a 0x0000006a</div><div class='del'>-				0x0000000b 0x00000071</div><div class='add'>+				&lt;0x00000000 0x00000023&gt;,</div><div class='add'>+				&lt;0x00000001 0x00000029&gt;,</div><div class='add'>+				&lt;0x00000002 0x0000002f&gt;,</div><div class='add'>+				&lt;0x00000003 0x00000036&gt;,</div><div class='add'>+				&lt;0x00000004 0x0000003c&gt;,</div><div class='add'>+				&lt;0x00000005 0x00000042&gt;,</div><div class='add'>+				&lt;0x00000006 0x00000049&gt;,</div><div class='add'>+				&lt;0x00000007 0x0000004f&gt;,</div><div class='add'>+				&lt;0x00000008 0x00000055&gt;,</div><div class='add'>+				&lt;0x00000009 0x0000005c&gt;,</div><div class='add'>+				&lt;0x0000000a 0x00000062&gt;,</div><div class='add'>+				&lt;0x0000000b 0x00000068&gt;,</div><div class='ctx'> 				/* Calibration data group 2 */</div><div class='del'>-				0x00010000 0x00000025</div><div class='del'>-				0x00010001 0x0000002c</div><div class='del'>-				0x00010002 0x00000035</div><div class='del'>-				0x00010003 0x0000003d</div><div class='del'>-				0x00010004 0x00000045</div><div class='del'>-				0x00010005 0x0000004e</div><div class='del'>-				0x00010006 0x00000057</div><div class='del'>-				0x00010007 0x00000061</div><div class='del'>-				0x00010008 0x0000006b</div><div class='del'>-				0x00010009 0x00000076</div><div class='add'>+				&lt;0x00010000 0x00000022&gt;,</div><div class='add'>+				&lt;0x00010001 0x0000002a&gt;,</div><div class='add'>+				&lt;0x00010002 0x00000032&gt;,</div><div class='add'>+				&lt;0x00010003 0x0000003a&gt;,</div><div class='add'>+				&lt;0x00010004 0x00000042&gt;,</div><div class='add'>+				&lt;0x00010005 0x0000004a&gt;,</div><div class='add'>+				&lt;0x00010006 0x00000052&gt;,</div><div class='add'>+				&lt;0x00010007 0x0000005a&gt;,</div><div class='add'>+				&lt;0x00010008 0x00000062&gt;,</div><div class='add'>+				&lt;0x00010009 0x0000006a&gt;,</div><div class='ctx'> 				/* Calibration data group 3 */</div><div class='del'>-				0x00020000 0x00000029</div><div class='del'>-				0x00020001 0x00000033</div><div class='del'>-				0x00020002 0x0000003d</div><div class='del'>-				0x00020003 0x00000049</div><div class='del'>-				0x00020004 0x00000056</div><div class='del'>-				0x00020005 0x00000061</div><div class='del'>-				0x00020006 0x0000006d</div><div class='add'>+				&lt;0x00020000 0x00000021&gt;,</div><div class='add'>+				&lt;0x00020001 0x0000002b&gt;,</div><div class='add'>+				&lt;0x00020002 0x00000035&gt;,</div><div class='add'>+				&lt;0x00020003 0x0000003e&gt;,</div><div class='add'>+				&lt;0x00020004 0x00000048&gt;,</div><div class='add'>+				&lt;0x00020005 0x00000052&gt;,</div><div class='add'>+				&lt;0x00020006 0x0000005c&gt;,</div><div class='ctx'> 				/* Calibration data group 4 */</div><div class='del'>-				0x00030000 0x00000021</div><div class='del'>-				0x00030001 0x0000002a</div><div class='del'>-				0x00030002 0x0000003c</div><div class='del'>-				0x00030003 0x0000004e&gt;;</div><div class='del'>-			big-endian;</div><div class='add'>+				&lt;0x00030000 0x00000011&gt;,</div><div class='add'>+				&lt;0x00030001 0x0000001a&gt;,</div><div class='add'>+				&lt;0x00030002 0x00000024&gt;,</div><div class='add'>+				&lt;0x00030003 0x0000002e&gt;,</div><div class='add'>+				&lt;0x00030004 0x00000038&gt;,</div><div class='add'>+				&lt;0x00030005 0x00000042&gt;,</div><div class='add'>+				&lt;0x00030006 0x0000004c&gt;,</div><div class='add'>+				&lt;0x00030007 0x00000056&gt;;</div><div class='ctx'> 			#thermal-sensor-cells = &lt;1&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -369,52 +494,69 @@</div><div class='ctx'> 			reg = &lt;0x0 0x2100000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clock-names = "dspi";</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='ctx'> 			spi-num-chipselects = &lt;5&gt;;</div><div class='ctx'> 			big-endian;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		i2c0: i2c@2180000 {</div><div class='del'>-			compatible = "fsl,vf610-i2c";</div><div class='add'>+			compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c";</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			reg = &lt;0x0 0x2180000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 1&gt;;</div><div class='del'>-			dmas = &lt;&amp;edma0 1 39&gt;,</div><div class='del'>-			       &lt;&amp;edma0 1 38&gt;;</div><div class='del'>-			dma-names = "tx", "rx";</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='add'>+			dmas = &lt;&amp;edma0 1 38&gt;,</div><div class='add'>+			       &lt;&amp;edma0 1 39&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		i2c1: i2c@2190000 {</div><div class='del'>-			compatible = "fsl,vf610-i2c";</div><div class='add'>+			compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c";</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			reg = &lt;0x0 0x2190000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='add'>+			scl-gpios = &lt;&amp;gpio3 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+			dmas = &lt;&amp;edma0 1 36&gt;,</div><div class='add'>+			       &lt;&amp;edma0 1 37&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		i2c2: i2c@21a0000 {</div><div class='del'>-			compatible = "fsl,vf610-i2c";</div><div class='add'>+			compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c";</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			reg = &lt;0x0 0x21a0000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='add'>+			scl-gpios = &lt;&amp;gpio3 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+			dmas = &lt;&amp;edma0 1 34&gt;,</div><div class='add'>+			       &lt;&amp;edma0 1 35&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		i2c3: i2c@21b0000 {</div><div class='del'>-			compatible = "fsl,vf610-i2c";</div><div class='add'>+			compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c";</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			reg = &lt;0x0 0x21b0000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='add'>+			scl-gpios = &lt;&amp;gpio3 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+			dmas = &lt;&amp;edma0 1 40&gt;,</div><div class='add'>+			       &lt;&amp;edma0 1 41&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -422,7 +564,8 @@</div><div class='ctx'> 			compatible = "fsl,ns16550", "ns16550a";</div><div class='ctx'> 			reg = &lt;0x00 0x21c0500 0x0 0x100&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -430,7 +573,8 @@</div><div class='ctx'> 			compatible = "fsl,ns16550", "ns16550a";</div><div class='ctx'> 			reg = &lt;0x00 0x21c0600 0x0 0x100&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -438,7 +582,8 @@</div><div class='ctx'> 			compatible = "fsl,ns16550", "ns16550a";</div><div class='ctx'> 			reg = &lt;0x0 0x21d0500 0x0 0x100&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -446,12 +591,13 @@</div><div class='ctx'> 			compatible = "fsl,ns16550", "ns16550a";</div><div class='ctx'> 			reg = &lt;0x0 0x21d0600 0x0 0x100&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		gpio0: gpio@2300000 {</div><div class='del'>-			compatible = "fsl,qoriq-gpio";</div><div class='add'>+			compatible = "fsl,ls1046a-gpio", "fsl,qoriq-gpio";</div><div class='ctx'> 			reg = &lt;0x0 0x2300000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			gpio-controller;</div><div class='hunk'>@@ -461,7 +607,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		gpio1: gpio@2310000 {</div><div class='del'>-			compatible = "fsl,qoriq-gpio";</div><div class='add'>+			compatible = "fsl,ls1046a-gpio", "fsl,qoriq-gpio";</div><div class='ctx'> 			reg = &lt;0x0 0x2310000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			gpio-controller;</div><div class='hunk'>@@ -471,7 +617,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		gpio2: gpio@2320000 {</div><div class='del'>-			compatible = "fsl,qoriq-gpio";</div><div class='add'>+			compatible = "fsl,ls1046a-gpio", "fsl,qoriq-gpio";</div><div class='ctx'> 			reg = &lt;0x0 0x2320000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			gpio-controller;</div><div class='hunk'>@@ -481,7 +627,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		gpio3: gpio@2330000 {</div><div class='del'>-			compatible = "fsl,qoriq-gpio";</div><div class='add'>+			compatible = "fsl,ls1046a-gpio", "fsl,qoriq-gpio";</div><div class='ctx'> 			reg = &lt;0x0 0x2330000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			gpio-controller;</div><div class='hunk'>@@ -494,8 +640,12 @@</div><div class='ctx'> 			compatible = "fsl,ls1021a-lpuart";</div><div class='ctx'> 			reg = &lt;0x0 0x2950000 0x0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(1)&gt;;</div><div class='ctx'> 			clock-names = "ipg";</div><div class='add'>+			dmas = &lt;&amp;edma0 1 32&gt;,</div><div class='add'>+			       &lt;&amp;edma0 1 33&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -503,8 +653,12 @@</div><div class='ctx'> 			compatible = "fsl,ls1021a-lpuart";</div><div class='ctx'> 			reg = &lt;0x0 0x2960000 0x0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='ctx'> 			clock-names = "ipg";</div><div class='add'>+			dmas = &lt;&amp;edma0 1 30&gt;,</div><div class='add'>+			       &lt;&amp;edma0 1 31&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -512,8 +666,12 @@</div><div class='ctx'> 			compatible = "fsl,ls1021a-lpuart";</div><div class='ctx'> 			reg = &lt;0x0 0x2970000 0x0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='ctx'> 			clock-names = "ipg";</div><div class='add'>+			dmas = &lt;&amp;edma0 1 28&gt;,</div><div class='add'>+			       &lt;&amp;edma0 1 29&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -521,8 +679,12 @@</div><div class='ctx'> 			compatible = "fsl,ls1021a-lpuart";</div><div class='ctx'> 			reg = &lt;0x0 0x2980000 0x0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='ctx'> 			clock-names = "ipg";</div><div class='add'>+			dmas = &lt;&amp;edma0 1 26&gt;,</div><div class='add'>+			       &lt;&amp;edma0 1 27&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -530,8 +692,12 @@</div><div class='ctx'> 			compatible = "fsl,ls1021a-lpuart";</div><div class='ctx'> 			reg = &lt;0x0 0x2990000 0x0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='ctx'> 			clock-names = "ipg";</div><div class='add'>+			dmas = &lt;&amp;edma0 1 24&gt;,</div><div class='add'>+			       &lt;&amp;edma0 1 25&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -539,20 +705,25 @@</div><div class='ctx'> 			compatible = "fsl,ls1021a-lpuart";</div><div class='ctx'> 			reg = &lt;0x0 0x29a0000 0x0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='ctx'> 			clock-names = "ipg";</div><div class='add'>+			dmas = &lt;&amp;edma0 1 22&gt;,</div><div class='add'>+			       &lt;&amp;edma0 1 23&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		wdog0: watchdog@2ad0000 {</div><div class='del'>-			compatible = "fsl,imx21-wdt";</div><div class='add'>+			compatible = "fsl,ls1046a-wdt", "fsl,imx21-wdt";</div><div class='ctx'> 			reg = &lt;0x0 0x2ad0000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='ctx'> 			big-endian;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		edma0: edma@2c00000 {</div><div class='add'>+		edma0: dma-controller@2c00000 {</div><div class='ctx'> 			#dma-cells = &lt;2&gt;;</div><div class='ctx'> 			compatible = "fsl,vf610-edma";</div><div class='ctx'> 			reg = &lt;0x0 0x2c00000 0x0 0x10000&gt;,</div><div class='hunk'>@@ -564,47 +735,64 @@</div><div class='ctx'> 			dma-channels = &lt;32&gt;;</div><div class='ctx'> 			big-endian;</div><div class='ctx'> 			clock-names = "dmamux0", "dmamux1";</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 1&gt;,</div><div class='del'>-				 &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		usb0: usb@2f00000 {</div><div class='del'>-			compatible = "snps,dwc3";</div><div class='del'>-			reg = &lt;0x0 0x2f00000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			dr_mode = "host";</div><div class='del'>-			snps,quirk-frame-length-adjustment = &lt;0x20&gt;;</div><div class='del'>-			snps,dis_rxdet_inp3_quirk;</div><div class='del'>-			snps,incr-burst-type-adjustment = &lt;1&gt;, &lt;4&gt;, &lt;8&gt;, &lt;16&gt;;</div><div class='del'>-		};</div><div class='add'>+		aux_bus: bus {</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			compatible = "simple-bus";</div><div class='add'>+			ranges;</div><div class='add'>+			dma-ranges = &lt;0x0 0x0 0x0 0x0 0x100 0x00000000&gt;;</div><div class='add'>+</div><div class='add'>+			usb0: usb@2f00000 {</div><div class='add'>+				compatible = "fsl,ls1046a-dwc3", "fsl,ls1028a-dwc3";</div><div class='add'>+				reg = &lt;0x0 0x2f00000 0x0 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				dr_mode = "host";</div><div class='add'>+				dma-coherent;</div><div class='add'>+				snps,quirk-frame-length-adjustment = &lt;0x20&gt;;</div><div class='add'>+				snps,dis_rxdet_inp3_quirk;</div><div class='add'>+				snps,incr-burst-type-adjustment = &lt;1&gt;, &lt;4&gt;, &lt;8&gt;, &lt;16&gt;;</div><div class='add'>+				usb3-lpm-capable;</div><div class='add'>+			};</div><div class='ctx'> </div><div class='del'>-		usb1: usb@3000000 {</div><div class='del'>-			compatible = "snps,dwc3";</div><div class='del'>-			reg = &lt;0x0 0x3000000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			dr_mode = "host";</div><div class='del'>-			snps,quirk-frame-length-adjustment = &lt;0x20&gt;;</div><div class='del'>-			snps,dis_rxdet_inp3_quirk;</div><div class='del'>-			snps,incr-burst-type-adjustment = &lt;1&gt;, &lt;4&gt;, &lt;8&gt;, &lt;16&gt;;</div><div class='del'>-		};</div><div class='add'>+			usb1: usb@3000000 {</div><div class='add'>+				compatible = "fsl,ls1046a-dwc3", "fsl,ls1028a-dwc3";</div><div class='add'>+				reg = &lt;0x0 0x3000000 0x0 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				dr_mode = "host";</div><div class='add'>+				dma-coherent;</div><div class='add'>+				snps,quirk-frame-length-adjustment = &lt;0x20&gt;;</div><div class='add'>+				snps,dis_rxdet_inp3_quirk;</div><div class='add'>+				snps,incr-burst-type-adjustment = &lt;1&gt;, &lt;4&gt;, &lt;8&gt;, &lt;16&gt;;</div><div class='add'>+				usb3-lpm-capable;</div><div class='add'>+			};</div><div class='ctx'> </div><div class='del'>-		usb2: usb@3100000 {</div><div class='del'>-			compatible = "snps,dwc3";</div><div class='del'>-			reg = &lt;0x0 0x3100000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			dr_mode = "host";</div><div class='del'>-			snps,quirk-frame-length-adjustment = &lt;0x20&gt;;</div><div class='del'>-			snps,dis_rxdet_inp3_quirk;</div><div class='del'>-			snps,incr-burst-type-adjustment = &lt;1&gt;, &lt;4&gt;, &lt;8&gt;, &lt;16&gt;;</div><div class='del'>-		};</div><div class='add'>+			usb2: usb@3100000 {</div><div class='add'>+				compatible = "fsl,ls1046a-dwc3", "fsl,ls1028a-dwc3";</div><div class='add'>+				reg = &lt;0x0 0x3100000 0x0 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				dr_mode = "host";</div><div class='add'>+				dma-coherent;</div><div class='add'>+				snps,quirk-frame-length-adjustment = &lt;0x20&gt;;</div><div class='add'>+				snps,dis_rxdet_inp3_quirk;</div><div class='add'>+				snps,incr-burst-type-adjustment = &lt;1&gt;, &lt;4&gt;, &lt;8&gt;, &lt;16&gt;;</div><div class='add'>+				usb3-lpm-capable;</div><div class='add'>+			};</div><div class='ctx'> </div><div class='del'>-		sata: sata@3200000 {</div><div class='del'>-			compatible = "fsl,ls1046a-ahci";</div><div class='del'>-			reg = &lt;0x0 0x3200000 0x0 0x10000&gt;,</div><div class='del'>-				&lt;0x0 0x20140520 0x0 0x4&gt;;</div><div class='del'>-			reg-names = "ahci", "sata-ecc";</div><div class='del'>-			interrupts = &lt;GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			sata: sata@3200000 {</div><div class='add'>+				compatible = "fsl,ls1046a-ahci";</div><div class='add'>+				reg = &lt;0x0 0x3200000 0x0 0x10000&gt;,</div><div class='add'>+					&lt;0x0 0x20140520 0x0 0x4&gt;;</div><div class='add'>+				reg-names = "ahci", "sata-ecc";</div><div class='add'>+				interrupts = &lt;GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+						    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		msi1: msi-controller@1580000 {</div><div class='hunk'>@@ -637,18 +825,17 @@</div><div class='ctx'> 				     &lt;GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		pcie@3400000 {</div><div class='add'>+		pcie1: pcie@3400000 {</div><div class='ctx'> 			compatible = "fsl,ls1046a-pcie";</div><div class='del'>-			reg = &lt;0x00 0x03400000 0x0 0x00100000   /* controller registers */</div><div class='del'>-			       0x40 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='add'>+			reg = &lt;0x00 0x03400000 0x0 0x00100000&gt;, /* controller registers */</div><div class='add'>+			      &lt;0x40 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='ctx'> 			reg-names = "regs", "config";</div><div class='del'>-			interrupts = &lt;GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH&gt;, /* controller interrupt */</div><div class='del'>-				     &lt;GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH&gt;; /* PME interrupt */</div><div class='del'>-			interrupt-names = "aer", "pme";</div><div class='add'>+			interrupts = &lt;GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH&gt;, /* PME interrupt */</div><div class='add'>+				     &lt;GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH&gt;; /* controller interrupt */</div><div class='add'>+			interrupt-names = "pme", "aer";</div><div class='ctx'> 			#address-cells = &lt;3&gt;;</div><div class='ctx'> 			#size-cells = &lt;2&gt;;</div><div class='ctx'> 			device_type = "pci";</div><div class='del'>-			dma-coherent;</div><div class='ctx'> 			num-viewport = &lt;8&gt;;</div><div class='ctx'> 			bus-range = &lt;0x0 0xff&gt;;</div><div class='ctx'> 			ranges = &lt;0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */</div><div class='hunk'>@@ -660,31 +847,34 @@</div><div class='ctx'> 					&lt;0000 0 0 2 &amp;gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 					&lt;0000 0 0 3 &amp;gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 					&lt;0000 0 0 4 &amp;gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			big-endian;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		pcie_ep@3400000 {</div><div class='del'>-			compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep";</div><div class='del'>-			reg = &lt;0x00 0x03400000 0x0 0x00100000</div><div class='del'>-				0x40 0x00000000 0x8 0x00000000&gt;;</div><div class='add'>+		pcie_ep1: pcie_ep@3400000 {</div><div class='add'>+			compatible = "fsl,ls1046a-pcie-ep";</div><div class='add'>+			reg = &lt;0x00 0x03400000 0x0 0x00100000&gt;,</div><div class='add'>+			      &lt;0x40 0x00000000 0x8 0x00000000&gt;;</div><div class='ctx'> 			reg-names = "regs", "addr_space";</div><div class='add'>+			interrupts = &lt;GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "pme";</div><div class='ctx'> 			num-ib-windows = &lt;6&gt;;</div><div class='ctx'> 			num-ob-windows = &lt;8&gt;;</div><div class='add'>+			big-endian;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		pcie@3500000 {</div><div class='add'>+		pcie2: pcie@3500000 {</div><div class='ctx'> 			compatible = "fsl,ls1046a-pcie";</div><div class='del'>-			reg = &lt;0x00 0x03500000 0x0 0x00100000   /* controller registers */</div><div class='del'>-			       0x48 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='add'>+			reg = &lt;0x00 0x03500000 0x0 0x00100000&gt;, /* controller registers */</div><div class='add'>+			      &lt;0x48 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='ctx'> 			reg-names = "regs", "config";</div><div class='del'>-			interrupts = &lt;GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH&gt;, /* controller interrupt */</div><div class='del'>-				     &lt;GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH&gt;; /* PME interrupt */</div><div class='del'>-			interrupt-names = "aer", "pme";</div><div class='add'>+			interrupts = &lt;GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH&gt;, /* PME interrupt */</div><div class='add'>+				     &lt;GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH&gt;; /* controller interrupt */</div><div class='add'>+			interrupt-names = "pme", "aer";</div><div class='ctx'> 			#address-cells = &lt;3&gt;;</div><div class='ctx'> 			#size-cells = &lt;2&gt;;</div><div class='ctx'> 			device_type = "pci";</div><div class='del'>-			dma-coherent;</div><div class='ctx'> 			num-viewport = &lt;8&gt;;</div><div class='ctx'> 			bus-range = &lt;0x0 0xff&gt;;</div><div class='ctx'> 			ranges = &lt;0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */</div><div class='hunk'>@@ -696,31 +886,34 @@</div><div class='ctx'> 					&lt;0000 0 0 2 &amp;gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 					&lt;0000 0 0 3 &amp;gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 					&lt;0000 0 0 4 &amp;gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			big-endian;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		pcie_ep@3500000 {</div><div class='del'>-			compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep";</div><div class='del'>-			reg = &lt;0x00 0x03500000 0x0 0x00100000</div><div class='del'>-				0x48 0x00000000 0x8 0x00000000&gt;;</div><div class='add'>+		pcie_ep2: pcie_ep@3500000 {</div><div class='add'>+			compatible = "fsl,ls1046a-pcie-ep";</div><div class='add'>+			reg = &lt;0x00 0x03500000 0x0 0x00100000&gt;,</div><div class='add'>+			      &lt;0x48 0x00000000 0x8 0x00000000&gt;;</div><div class='ctx'> 			reg-names = "regs", "addr_space";</div><div class='add'>+			interrupts = &lt;GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "pme";</div><div class='ctx'> 			num-ib-windows = &lt;6&gt;;</div><div class='ctx'> 			num-ob-windows = &lt;8&gt;;</div><div class='add'>+			big-endian;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		pcie@3600000 {</div><div class='add'>+		pcie3: pcie@3600000 {</div><div class='ctx'> 			compatible = "fsl,ls1046a-pcie";</div><div class='del'>-			reg = &lt;0x00 0x03600000 0x0 0x00100000   /* controller registers */</div><div class='del'>-			       0x50 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='add'>+			reg = &lt;0x00 0x03600000 0x0 0x00100000&gt;, /* controller registers */</div><div class='add'>+			      &lt;0x50 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='ctx'> 			reg-names = "regs", "config";</div><div class='del'>-			interrupts = &lt;GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH&gt;, /* controller interrupt */</div><div class='del'>-				     &lt;GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH&gt;; /* PME interrupt */</div><div class='del'>-			interrupt-names = "aer", "pme";</div><div class='add'>+			interrupts = &lt;GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH&gt;, /* PME interrupt */</div><div class='add'>+				     &lt;GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH&gt;; /* controller interrupt */</div><div class='add'>+			interrupt-names = "pme", "aer";</div><div class='ctx'> 			#address-cells = &lt;3&gt;;</div><div class='ctx'> 			#size-cells = &lt;2&gt;;</div><div class='ctx'> 			device_type = "pci";</div><div class='del'>-			dma-coherent;</div><div class='ctx'> 			num-viewport = &lt;8&gt;;</div><div class='ctx'> 			bus-range = &lt;0x0 0xff&gt;;</div><div class='ctx'> 			ranges = &lt;0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000   /* downstream I/O */</div><div class='hunk'>@@ -732,16 +925,20 @@</div><div class='ctx'> 					&lt;0000 0 0 2 &amp;gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 					&lt;0000 0 0 3 &amp;gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 					&lt;0000 0 0 4 &amp;gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			big-endian;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		pcie_ep@3600000 {</div><div class='del'>-			compatible = "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep";</div><div class='del'>-			reg = &lt;0x00 0x03600000 0x0 0x00100000</div><div class='del'>-				0x50 0x00000000 0x8 0x00000000&gt;;</div><div class='add'>+		pcie_ep3: pcie_ep@3600000 {</div><div class='add'>+			compatible = "fsl,ls1046a-pcie-ep";</div><div class='add'>+			reg = &lt;0x00 0x03600000 0x0 0x00100000&gt;,</div><div class='add'>+			      &lt;0x50 0x00000000 0x8 0x00000000&gt;;</div><div class='ctx'> 			reg-names = "regs", "addr_space";</div><div class='add'>+			interrupts = &lt;GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "pme";</div><div class='ctx'> 			num-ib-windows = &lt;6&gt;;</div><div class='ctx'> 			num-ob-windows = &lt;8&gt;;</div><div class='add'>+			big-endian;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -757,6 +954,7 @@</div><div class='ctx'> 				     &lt;GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			interrupt-names = "qdma-error", "qdma-queue0",</div><div class='ctx'> 				"qdma-queue1", "qdma-queue2", "qdma-queue3";</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='ctx'> 			dma-channels = &lt;8&gt;;</div><div class='ctx'> 			block-number = &lt;1&gt;;</div><div class='ctx'> 			block-offset = &lt;0x10000&gt;;</div><div class='hunk'>@@ -765,6 +963,20 @@</div><div class='ctx'> 			queue-sizes = &lt;64 64&gt;;</div><div class='ctx'> 			big-endian;</div><div class='ctx'> 		};</div><div class='add'>+</div><div class='add'>+		rcpm: wakeup-controller@1ee2140 {</div><div class='add'>+			compatible = "fsl,ls1046a-rcpm", "fsl,qoriq-rcpm-2.1+";</div><div class='add'>+			reg = &lt;0x0 0x1ee2140 0x0 0x4&gt;;</div><div class='add'>+			#fsl,rcpm-wakeup-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ftm_alarm0: rtc@29d0000 {</div><div class='add'>+			compatible = "fsl,ls1046a-ftm-alarm";</div><div class='add'>+			reg = &lt;0x0 0x29d0000 0x0 0x10000&gt;;</div><div class='add'>+			fsl,rcpm-wakeup = &lt;&amp;rcpm 0x20000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			big-endian;</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	reserved-memory {</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts<br/>index 41d8b15f25a5..d238a8440a81 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts</a></div><div class='hunk'>@@ -53,7 +53,7 @@</div><div class='ctx'> &amp;i2c0 {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='del'>-	i2c-switch@77 {</div><div class='add'>+	i2c-mux@77 {</div><div class='ctx'> 		compatible = "nxp,pca9547";</div><div class='ctx'> 		reg = &lt;0x77&gt;;</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='hunk'>@@ -113,7 +113,7 @@</div><div class='ctx'> 		  3 0 0x5 0x20000000 0x00010000&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='del'>-	nor@0,0 {</div><div class='add'>+	flash@0,0 {</div><div class='ctx'> 		compatible = "cfi-flash";</div><div class='ctx'> 		reg = &lt;0x0 0x0 0x8000000&gt;;</div><div class='ctx'> 		bank-width = &lt;2&gt;;</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts<br/>index 5633e59febc3..2df16bfb901c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts</a></div><div class='hunk'>@@ -2,7 +2,7 @@</div><div class='ctx'> /*</div><div class='ctx'>  * Device Tree file for NXP LS1088A RDB Board.</div><div class='ctx'>  *</div><div class='del'>- * Copyright 2017 NXP</div><div class='add'>+ * Copyright 2017-2020 NXP</div><div class='ctx'>  *</div><div class='ctx'>  * Harninder Rai &lt;harninder.rai@nxp.com&gt;</div><div class='ctx'>  *</div><div class='hunk'>@@ -17,10 +17,126 @@</div><div class='ctx'> 	compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;dpmac2 {</div><div class='add'>+	phy-handle = &lt;&amp;mdio2_aquantia_phy&gt;;</div><div class='add'>+	phy-connection-type = "10gbase-r";</div><div class='add'>+	pcs-handle = &lt;&amp;pcs2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac3 {</div><div class='add'>+	phy-handle = &lt;&amp;mdio1_phy5&gt;;</div><div class='add'>+	phy-connection-type = "qsgmii";</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	pcs-handle = &lt;&amp;pcs3_0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac4 {</div><div class='add'>+	phy-handle = &lt;&amp;mdio1_phy6&gt;;</div><div class='add'>+	phy-connection-type = "qsgmii";</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	pcs-handle = &lt;&amp;pcs3_1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac5 {</div><div class='add'>+	phy-handle = &lt;&amp;mdio1_phy7&gt;;</div><div class='add'>+	phy-connection-type = "qsgmii";</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	pcs-handle = &lt;&amp;pcs3_2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac6 {</div><div class='add'>+	phy-handle = &lt;&amp;mdio1_phy8&gt;;</div><div class='add'>+	phy-connection-type = "qsgmii";</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	pcs-handle = &lt;&amp;pcs3_3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac7 {</div><div class='add'>+	phy-handle = &lt;&amp;mdio1_phy1&gt;;</div><div class='add'>+	phy-connection-type = "qsgmii";</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	pcs-handle = &lt;&amp;pcs7_0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac8 {</div><div class='add'>+	phy-handle = &lt;&amp;mdio1_phy2&gt;;</div><div class='add'>+	phy-connection-type = "qsgmii";</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	pcs-handle = &lt;&amp;pcs7_1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac9 {</div><div class='add'>+	phy-handle = &lt;&amp;mdio1_phy3&gt;;</div><div class='add'>+	phy-connection-type = "qsgmii";</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	pcs-handle = &lt;&amp;pcs7_2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac10 {</div><div class='add'>+	phy-handle = &lt;&amp;mdio1_phy4&gt;;</div><div class='add'>+	phy-connection-type = "qsgmii";</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	pcs-handle = &lt;&amp;pcs7_3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;emdio1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio1_phy5: ethernet-phy@c {</div><div class='add'>+		interrupts-extended = &lt;&amp;extirq 1 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		reg = &lt;0xc&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mdio1_phy6: ethernet-phy@d {</div><div class='add'>+		interrupts-extended = &lt;&amp;extirq 1 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		reg = &lt;0xd&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mdio1_phy7: ethernet-phy@e {</div><div class='add'>+		interrupts-extended = &lt;&amp;extirq 1 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		reg = &lt;0xe&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mdio1_phy8: ethernet-phy@f {</div><div class='add'>+		interrupts-extended = &lt;&amp;extirq 1 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		reg = &lt;0xf&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mdio1_phy1: ethernet-phy@1c {</div><div class='add'>+		interrupts-extended = &lt;&amp;extirq 1 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		reg = &lt;0x1c&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mdio1_phy2: ethernet-phy@1d {</div><div class='add'>+		interrupts-extended = &lt;&amp;extirq 1 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		reg = &lt;0x1d&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mdio1_phy3: ethernet-phy@1e {</div><div class='add'>+		interrupts-extended = &lt;&amp;extirq 1 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		reg = &lt;0x1e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mdio1_phy4: ethernet-phy@1f {</div><div class='add'>+		interrupts-extended = &lt;&amp;extirq 1 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		reg = &lt;0x1f&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;emdio2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio2_aquantia_phy: ethernet-phy@0 {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+		interrupts-extended = &lt;&amp;extirq 2 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		reg = &lt;0x0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;i2c0 {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='del'>-	i2c-switch@77 {</div><div class='add'>+	i2c-mux@77 {</div><div class='ctx'> 		compatible = "nxp,pca9547";</div><div class='ctx'> 		reg = &lt;0x77&gt;;</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='hunk'>@@ -51,8 +167,15 @@</div><div class='ctx'> 			rtc@51 {</div><div class='ctx'> 				compatible = "nxp,pcf2129";</div><div class='ctx'> 				reg = &lt;0x51&gt;;</div><div class='del'>-				/* IRQ10_B */</div><div class='del'>-				interrupts = &lt;0 150 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				/* IRQ_RTC_B -&gt; IRQ0_B(CPLD) -&gt; IRQ00(CPU), active low */</div><div class='add'>+				interrupts-extended = &lt;&amp;extirq 0 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			rtc@53 {</div><div class='add'>+				compatible = "nxp,pcf2131";</div><div class='add'>+				reg = &lt;0x53&gt;;</div><div class='add'>+				/* IRQ_RTC_B -&gt; IRQ0_B(CPLD) -&gt; IRQ00(CPU), active low */</div><div class='add'>+				interrupts-extended = &lt;&amp;extirq 0 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='hunk'>@@ -87,6 +210,18 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;pcs_mdio2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio7 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;qspi {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts<br/>new file mode 100644<br/>index 000000000000..71765ec91745<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts</a></div><div class='hunk'>@@ -0,0 +1,435 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Device Tree file for Travese Ten64 (LS1088) board</div><div class='add'>+ * Based on fsl-ls1088a-rdb.dts</div><div class='add'>+ * Copyright 2017-2020 NXP</div><div class='add'>+ * Copyright 2019-2021 Traverse Technologies</div><div class='add'>+ *</div><div class='add'>+ * Author: Mathew McBride &lt;matt@traverse.com.au&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "fsl-ls1088a.dtsi"</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Traverse Ten64";</div><div class='add'>+	compatible = "traverse,ten64", "fsl,ls1088a";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;duart0;</div><div class='add'>+		serial1 = &amp;duart1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	buttons {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		/* Fired by system controller when</div><div class='add'>+		 * external power off (e.g ATX Power Button)</div><div class='add'>+		 * asserted</div><div class='add'>+		 */</div><div class='add'>+		button-powerdn {</div><div class='add'>+			label = "External Power Down";</div><div class='add'>+			gpios = &lt;&amp;gpio1 17 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* Rear Panel 'ADMIN' button (GPIO_H) */</div><div class='add'>+		button-admin {</div><div class='add'>+			label = "ADMIN button";</div><div class='add'>+			gpios = &lt;&amp;gpio3 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,code = &lt;KEY_WPS_BUTTON&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			label = "ten64:green:sfp1:down";</div><div class='add'>+			gpios = &lt;&amp;gpio3 11 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			label = "ten64:green:sfp2:up";</div><div class='add'>+			gpios = &lt;&amp;gpio3 12 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-2 {</div><div class='add'>+			label = "ten64:admin";</div><div class='add'>+			gpios = &lt;&amp;sfpgpio 12 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp_xg0: dpmac2-sfp {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;sfplower_i2c&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;sfpgpio 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;sfpgpio 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;sfpgpio 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;sfpgpio 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		maximum-power-milliwatt = &lt;2000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp_xg1: dpmac1-sfp {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;sfpupper_i2c&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;sfpgpio 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;sfpgpio 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;sfpgpio 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;sfpgpio 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		maximum-power-milliwatt = &lt;2000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb1v2_supply: regulator-usbhub-1v2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "usbhub_1v2";</div><div class='add'>+		regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	system3v3_supply: regulator-system-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "system_3v3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* XG1 - Upper SFP */</div><div class='add'>+&amp;dpmac1 {</div><div class='add'>+	sfp = &lt;&amp;sfp_xg1&gt;;</div><div class='add'>+	pcs-handle = &lt;&amp;pcs1&gt;;</div><div class='add'>+	phy-connection-type = "10gbase-r";</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* XG0 - Lower SFP */</div><div class='add'>+&amp;dpmac2 {</div><div class='add'>+	sfp = &lt;&amp;sfp_xg0&gt;;</div><div class='add'>+	pcs-handle = &lt;&amp;pcs2&gt;;</div><div class='add'>+	phy-connection-type = "10gbase-r";</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* DPMAC3..6 is GE4 to GE8 */</div><div class='add'>+&amp;dpmac3 {</div><div class='add'>+	phy-handle = &lt;&amp;mdio1_phy5&gt;;</div><div class='add'>+	phy-connection-type = "qsgmii";</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	pcs-handle = &lt;&amp;pcs3_0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac4 {</div><div class='add'>+	phy-handle = &lt;&amp;mdio1_phy6&gt;;</div><div class='add'>+	phy-connection-type = "qsgmii";</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	pcs-handle = &lt;&amp;pcs3_1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac5 {</div><div class='add'>+	phy-handle = &lt;&amp;mdio1_phy7&gt;;</div><div class='add'>+	phy-connection-type = "qsgmii";</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	pcs-handle = &lt;&amp;pcs3_2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac6 {</div><div class='add'>+	phy-handle = &lt;&amp;mdio1_phy8&gt;;</div><div class='add'>+	phy-connection-type = "qsgmii";</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	pcs-handle = &lt;&amp;pcs3_3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* DPMAC7..10 is GE0 to GE3 */</div><div class='add'>+&amp;dpmac7 {</div><div class='add'>+	phy-handle = &lt;&amp;mdio1_phy1&gt;;</div><div class='add'>+	phy-connection-type = "qsgmii";</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	pcs-handle = &lt;&amp;pcs7_0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac8 {</div><div class='add'>+	phy-handle = &lt;&amp;mdio1_phy2&gt;;</div><div class='add'>+	phy-connection-type = "qsgmii";</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	pcs-handle = &lt;&amp;pcs7_1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac9 {</div><div class='add'>+	phy-handle = &lt;&amp;mdio1_phy3&gt;;</div><div class='add'>+	phy-connection-type = "qsgmii";</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	pcs-handle = &lt;&amp;pcs7_2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac10 {</div><div class='add'>+	phy-handle = &lt;&amp;mdio1_phy4&gt;;</div><div class='add'>+	phy-connection-type = "qsgmii";</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	pcs-handle = &lt;&amp;pcs7_3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;duart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;duart1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;emdio1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio1_phy5: ethernet-phy@c {</div><div class='add'>+		reg = &lt;0xc&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mdio1_phy6: ethernet-phy@d {</div><div class='add'>+		reg = &lt;0xd&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mdio1_phy7: ethernet-phy@e {</div><div class='add'>+		reg = &lt;0xe&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mdio1_phy8: ethernet-phy@f {</div><div class='add'>+		reg = &lt;0xf&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mdio1_phy1: ethernet-phy@1c {</div><div class='add'>+		reg = &lt;0x1c&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mdio1_phy2: ethernet-phy@1d {</div><div class='add'>+		reg = &lt;0x1d&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mdio1_phy3: ethernet-phy@1e {</div><div class='add'>+		reg = &lt;0x1e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mdio1_phy4: ethernet-phy@1f {</div><div class='add'>+		reg = &lt;0x1f&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;esdhc {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	sfpgpio: gpio@76 {</div><div class='add'>+		compatible = "ti,tca9539";</div><div class='add'>+		reg = &lt;0x76&gt;;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+</div><div class='add'>+		admin-led-lower-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;13 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	at97sc: tpm@29 {</div><div class='add'>+		compatible = "atmel,at97sc3204t";</div><div class='add'>+		reg = &lt;0x29&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usbhub: usb-hub@2d {</div><div class='add'>+		compatible = "microchip,usb5744";</div><div class='add'>+		reg = &lt;0x2d&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uc: board-controller@7e {</div><div class='add'>+		compatible = "traverse,ten64-controller";</div><div class='add'>+		reg = &lt;0x7e&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	rx8035: rtc@32 {</div><div class='add'>+		compatible = "epson,rx8035";</div><div class='add'>+		reg = &lt;0x32&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	i2c-mux@70 {</div><div class='add'>+		compatible = "nxp,pca9540";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		reg = &lt;0x70&gt;;</div><div class='add'>+</div><div class='add'>+		sfpupper_i2c: i2c@0 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sfplower_i2c: i2c@1 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio7 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qspi {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	en25s64: flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;20000000&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+		partitions {</div><div class='add'>+			compatible = "fixed-partitions";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			partition@0 {</div><div class='add'>+				label = "bl2";</div><div class='add'>+				reg = &lt;0 0x100000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			partition@100000 {</div><div class='add'>+				label = "bl3";</div><div class='add'>+				reg = &lt;0x100000 0x200000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			partition@300000 {</div><div class='add'>+				label = "mcfirmware";</div><div class='add'>+				reg = &lt;0x300000 0x200000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			partition@500000 {</div><div class='add'>+				label = "ubootenv";</div><div class='add'>+				reg = &lt;0x500000 0x80000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			partition@580000 {</div><div class='add'>+				label = "dpl";</div><div class='add'>+				reg = &lt;0x580000 0x40000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			partition@5c0000 {</div><div class='add'>+				label = "dpc";</div><div class='add'>+				reg = &lt;0x5c0000 0x40000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			partition@600000 {</div><div class='add'>+				label = "devicetree";</div><div class='add'>+				reg = &lt;0x600000 0x40000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	nand: flash@1 {</div><div class='add'>+		compatible = "spi-nand";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		spi-max-frequency = &lt;20000000&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+		partitions {</div><div class='add'>+			compatible = "fixed-partitions";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			/* reserved for future boot direct from NAND flash</div><div class='add'>+			 * (this would use the same layout as the 8MiB NOR flash)</div><div class='add'>+			 */</div><div class='add'>+			partition@0 {</div><div class='add'>+				label = "nand-boot-reserved";</div><div class='add'>+				reg = &lt;0 0x800000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* recovery / install environment */</div><div class='add'>+			partition@800000 {</div><div class='add'>+				label = "recovery";</div><div class='add'>+				reg = &lt;0x800000 0x2000000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* ubia (first OpenWrt) - a/b names to prevent confusion with ubi0/1/etc. */</div><div class='add'>+			partition@2800000 {</div><div class='add'>+				label = "ubia";</div><div class='add'>+				reg = &lt;0x2800000 0x6C00000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* ubib (second OpenWrt) */</div><div class='add'>+			partition@9400000 {</div><div class='add'>+				label = "ubib";</div><div class='add'>+				reg = &lt;0x9400000 0x6C00000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* LS1088A USB Port 0 - direct to bottom USB-A port */</div><div class='add'>+&amp;usb0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* LS1088A USB Port 1 - to Microchip USB5744 USB Hub */</div><div class='add'>+&amp;usb1 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	hub_2_0: hub@1 {</div><div class='add'>+		compatible = "usb424,2744";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		peer-hub = &lt;&amp;hub_3_0&gt;;</div><div class='add'>+		i2c-bus = &lt;&amp;usbhub&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;system3v3_supply&gt;;</div><div class='add'>+		vdd2-supply = &lt;&amp;usb1v2_supply&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hub_3_0: hub@2 {</div><div class='add'>+		compatible = "usb424,5744";</div><div class='add'>+		reg = &lt;2&gt;;</div><div class='add'>+		peer-hub = &lt;&amp;hub_2_0&gt;;</div><div class='add'>+		i2c-bus = &lt;&amp;usbhub&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;system3v3_supply&gt;;</div><div class='add'>+		vdd2-supply = &lt;&amp;usb1v2_supply&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-tqmls1088a-mbls10xxa.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-tqmls1088a-mbls10xxa.dts<br/>new file mode 100644<br/>index 000000000000..181eeab55aa0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1088a-tqmls1088a-mbls10xxa.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls1088a-tqmls1088a-mbls10xxa.dts</a></div><div class='hunk'>@@ -0,0 +1,72 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2018-2023 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Gregor Herburger, Timo Herbrecher</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+</div><div class='add'>+#include "fsl-ls1088a-tqmls1088a.dtsi"</div><div class='add'>+#include "tqmls10xxa-mbls10xxa.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "TQ-Systems GmbH LS1088A TQMLS1088A SoM on MBLS10xxA board";</div><div class='add'>+	compatible = "tq,ls1088a-tqmls1088a-mbls10xxa", "tq,ls1088a-tqmls1088a",</div><div class='add'>+		     "fsl,ls1088a";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		dpmac1 = &amp;dpmac1;</div><div class='add'>+		dpmac2 = &amp;dpmac2;</div><div class='add'>+		dpmac3 = &amp;dpmac3;</div><div class='add'>+		dpmac4 = &amp;dpmac4;</div><div class='add'>+		dpmac5 = &amp;dpmac5;</div><div class='add'>+		dpmac6 = &amp;dpmac6;</div><div class='add'>+		dpmac7 = &amp;dpmac7;</div><div class='add'>+		dpmac8 = &amp;dpmac8;</div><div class='add'>+		dpmac9 = &amp;dpmac9;</div><div class='add'>+		dpmac10 = &amp;dpmac10;</div><div class='add'>+		qsgmii-s1-p1 = &amp;qsgmii1_phy1;</div><div class='add'>+		qsgmii-s1-p2 = &amp;qsgmii1_phy2;</div><div class='add'>+		qsgmii-s1-p3 = &amp;qsgmii1_phy3;</div><div class='add'>+		qsgmii-s1-p4 = &amp;qsgmii1_phy4;</div><div class='add'>+		qsgmii-s2-p1 = &amp;qsgmii2_phy1;</div><div class='add'>+		qsgmii-s2-p2 = &amp;qsgmii2_phy2;</div><div class='add'>+		qsgmii-s2-p3 = &amp;qsgmii2_phy3;</div><div class='add'>+		qsgmii-s2-p4 = &amp;qsgmii2_phy4;</div><div class='add'>+		rgmii-s1 = &amp;rgmii_phy1;</div><div class='add'>+		rgmii-s2 = &amp;rgmii_phy2;</div><div class='add'>+		serial0 = &amp;duart0;</div><div class='add'>+		serial1 = &amp;duart1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;duart1;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;esdhc {</div><div class='add'>+	cd-gpios = &lt;&amp;gpio3 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	wp-gpios = &lt;&amp;gpio3 13 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sfp1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sfp2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sfp1_i2c {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sfp2_i2c {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include "tqmls1088a-mbls10xxa-mc.dtsi"</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-tqmls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a-tqmls1088a.dtsi<br/>new file mode 100644<br/>index 000000000000..b8a213df238a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1088a-tqmls1088a.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls1088a-tqmls1088a.dtsi</a></div><div class='hunk'>@@ -0,0 +1,42 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2018-2023 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Gregor Herburger, Timo Herbrecher</div><div class='add'>+ *</div><div class='add'>+ * Device Tree Include file for LS1088A based SoM of TQ</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "fsl-ls1088a.dtsi"</div><div class='add'>+#include "tqmls10xxa.dtsi"</div><div class='add'>+</div><div class='add'>+&amp;qspi {</div><div class='add'>+	num-cs = &lt;2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	qflash0: flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;62500000&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;4&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_vcc1v8&gt;;</div><div class='add'>+</div><div class='add'>+		partitions {</div><div class='add'>+			compatible = "fixed-partitions";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	qflash1: flash@1 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		spi-max-frequency = &lt;62500000&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;4&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_vcc1v8&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi<br/>index 36a799554620..b2f6cd237be0 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi</a></div><div class='hunk'>@@ -2,11 +2,12 @@</div><div class='ctx'> /*</div><div class='ctx'>  * Device Tree Include file for NXP Layerscape-1088A family SoC.</div><div class='ctx'>  *</div><div class='del'>- * Copyright 2017 NXP</div><div class='add'>+ * Copyright 2017-2020 NXP</div><div class='ctx'>  *</div><div class='ctx'>  * Harninder Rai &lt;harninder.rai@nxp.com&gt;</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='add'>+#include &lt;dt-bindings/clock/fsl,qoriq-clockgen.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/thermal/thermal.h&gt;</div><div class='ctx'> </div><div class='hunk'>@@ -18,6 +19,7 @@</div><div class='ctx'> </div><div class='ctx'> 	aliases {</div><div class='ctx'> 		crypto = &amp;crypto;</div><div class='add'>+		rtc1 = &amp;ftm_alarm0;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	cpus {</div><div class='hunk'>@@ -29,7 +31,7 @@</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			reg = &lt;0x0&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 1 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 0&gt;;</div><div class='ctx'> 			cpu-idle-states = &lt;&amp;CPU_PH20&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='hunk'>@@ -38,7 +40,7 @@</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			reg = &lt;0x1&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 1 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 0&gt;;</div><div class='ctx'> 			cpu-idle-states = &lt;&amp;CPU_PH20&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='hunk'>@@ -47,7 +49,7 @@</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			reg = &lt;0x2&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 1 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 0&gt;;</div><div class='ctx'> 			cpu-idle-states = &lt;&amp;CPU_PH20&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='hunk'>@@ -56,7 +58,7 @@</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			reg = &lt;0x3&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 1 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 0&gt;;</div><div class='ctx'> 			cpu-idle-states = &lt;&amp;CPU_PH20&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='hunk'>@@ -65,7 +67,7 @@</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			reg = &lt;0x100&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 1 1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 1&gt;;</div><div class='ctx'> 			cpu-idle-states = &lt;&amp;CPU_PH20&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='hunk'>@@ -74,7 +76,7 @@</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			reg = &lt;0x101&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 1 1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 1&gt;;</div><div class='ctx'> 			cpu-idle-states = &lt;&amp;CPU_PH20&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='hunk'>@@ -83,7 +85,7 @@</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			reg = &lt;0x102&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 1 1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 1&gt;;</div><div class='ctx'> 			cpu-idle-states = &lt;&amp;CPU_PH20&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='hunk'>@@ -92,7 +94,7 @@</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			reg = &lt;0x103&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 1 1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 1&gt;;</div><div class='ctx'> 			cpu-idle-states = &lt;&amp;CPU_PH20&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='hunk'>@@ -116,32 +118,33 @@</div><div class='ctx'> 		      &lt;0x0 0x0c0c0000 0 0x2000&gt;, /* GICC */</div><div class='ctx'> 		      &lt;0x0 0x0c0d0000 0 0x1000&gt;, /* GICH */</div><div class='ctx'> 		      &lt;0x0 0x0c0e0000 0 0x20000&gt;; /* GICV */</div><div class='del'>-		interrupts = &lt;1 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		#address-cells = &lt;2&gt;;</div><div class='ctx'> 		#size-cells = &lt;2&gt;;</div><div class='ctx'> 		ranges;</div><div class='ctx'> </div><div class='del'>-		its: gic-its@6020000 {</div><div class='add'>+		its: msi-controller@6020000 {</div><div class='ctx'> 			compatible = "arm,gic-v3-its";</div><div class='ctx'> 			msi-controller;</div><div class='add'>+			#msi-cells = &lt;1&gt;;</div><div class='ctx'> 			reg = &lt;0x0 0x6020000 0 0x20000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	thermal-zones {</div><div class='del'>-		cpu_thermal: cpu-thermal {</div><div class='add'>+		cluster-thermal {</div><div class='ctx'> 			polling-delay-passive = &lt;1000&gt;;</div><div class='ctx'> 			polling-delay = &lt;5000&gt;;</div><div class='ctx'> 			thermal-sensors = &lt;&amp;tmu 0&gt;;</div><div class='ctx'> </div><div class='ctx'> 			trips {</div><div class='del'>-				cpu_alert: cpu-alert {</div><div class='add'>+				core_cluster_alert: core-cluster-alert {</div><div class='ctx'> 					temperature = &lt;85000&gt;;</div><div class='ctx'> 					hysteresis = &lt;2000&gt;;</div><div class='ctx'> 					type = "passive";</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				cpu_crit: cpu-crit {</div><div class='add'>+				core-cluster-crit {</div><div class='ctx'> 					temperature = &lt;95000&gt;;</div><div class='ctx'> 					hysteresis = &lt;2000&gt;;</div><div class='ctx'> 					type = "critical";</div><div class='hunk'>@@ -150,7 +153,7 @@</div><div class='ctx'> </div><div class='ctx'> 			cooling-maps {</div><div class='ctx'> 				map0 {</div><div class='del'>-					trip = &lt;&amp;cpu_alert&gt;;</div><div class='add'>+					trip = &lt;&amp;core_cluster_alert&gt;;</div><div class='ctx'> 					cooling-device =</div><div class='ctx'> 						&lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='ctx'> 						&lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='hunk'>@@ -163,14 +166,33 @@</div><div class='ctx'> 				};</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='add'>+</div><div class='add'>+		soc-thermal {</div><div class='add'>+			polling-delay-passive = &lt;1000&gt;;</div><div class='add'>+			polling-delay = &lt;5000&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;tmu 1&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				soc-crit {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	timer {</div><div class='ctx'> 		compatible = "arm,armv8-timer";</div><div class='del'>-		interrupts = &lt;1 13 IRQ_TYPE_LEVEL_LOW&gt;,/* Physical Secure PPI */</div><div class='del'>-			     &lt;1 14 IRQ_TYPE_LEVEL_LOW&gt;,/* Physical Non-Secure PPI */</div><div class='del'>-			     &lt;1 11 IRQ_TYPE_LEVEL_LOW&gt;,/* Virtual PPI */</div><div class='del'>-			     &lt;1 10 IRQ_TYPE_LEVEL_LOW&gt;;/* Hypervisor PPI */</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 IRQ_TYPE_LEVEL_LOW&gt;,/* Physical Secure PPI */</div><div class='add'>+			     &lt;GIC_PPI 14 IRQ_TYPE_LEVEL_LOW&gt;,/* Physical Non-Secure PPI */</div><div class='add'>+			     &lt;GIC_PPI 11 IRQ_TYPE_LEVEL_LOW&gt;,/* Virtual PPI */</div><div class='add'>+			     &lt;GIC_PPI 10 IRQ_TYPE_LEVEL_LOW&gt;;/* Hypervisor PPI */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu {</div><div class='add'>+		compatible = "arm,cortex-a53-pmu";</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	psci {</div><div class='hunk'>@@ -185,6 +207,13 @@</div><div class='ctx'> 		clock-output-names = "sysclk";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	reboot {</div><div class='add'>+		compatible = "syscon-reboot";</div><div class='add'>+		regmap = &lt;&amp;reset&gt;;</div><div class='add'>+		offset = &lt;0x0&gt;;</div><div class='add'>+		mask = &lt;0x02&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	soc {</div><div class='ctx'> 		compatible = "simple-bus";</div><div class='ctx'> 		#address-cells = &lt;2&gt;;</div><div class='hunk'>@@ -205,49 +234,97 @@</div><div class='ctx'> 			little-endian;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		reset: syscon@1e60000 {</div><div class='add'>+			compatible = "fsl,ls1088a-reset", "syscon";</div><div class='add'>+			reg = &lt;0x0 0x1e60000 0x0 0x10000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		isc: syscon@1f70000 {</div><div class='add'>+			compatible = "fsl,ls1088a-isc", "syscon";</div><div class='add'>+			reg = &lt;0x0 0x1f70000 0x0 0x10000&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges = &lt;0x0 0x0 0x1f70000 0x10000&gt;;</div><div class='add'>+</div><div class='add'>+			extirq: interrupt-controller@14 {</div><div class='add'>+				compatible = "fsl,ls1088a-extirq";</div><div class='add'>+				#interrupt-cells = &lt;2&gt;;</div><div class='add'>+				#address-cells = &lt;0&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				reg = &lt;0x14 4&gt;;</div><div class='add'>+				interrupt-map =</div><div class='add'>+					&lt;0 0 &amp;gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;1 0 &amp;gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;2 0 &amp;gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;3 0 &amp;gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;4 0 &amp;gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;5 0 &amp;gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;6 0 &amp;gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;7 0 &amp;gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;8 0 &amp;gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;9 0 &amp;gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;10 0 &amp;gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;11 0 &amp;gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				interrupt-map-mask = &lt;0xf 0x0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sfp: efuse@1e80000 {</div><div class='add'>+			compatible = "fsl,ls1028a-sfp";</div><div class='add'>+			reg = &lt;0x0 0x1e80000 0x0 0x10000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='add'>+			clock-names = "sfp";</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		tmu: tmu@1f80000 {</div><div class='ctx'> 			compatible = "fsl,qoriq-tmu";</div><div class='ctx'> 			reg = &lt;0x0 0x1f80000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 23 0x4&gt;;</div><div class='del'>-			fsl,tmu-range = &lt;0xb0000 0x9002a 0x6004c 0x30062&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			fsl,tmu-range = &lt;0xb0000 0x9002a 0x6004c 0x70062&gt;;</div><div class='ctx'> 			fsl,tmu-calibration =</div><div class='ctx'> 				/* Calibration data group 1 */</div><div class='del'>-				&lt;0x00000000 0x00000026</div><div class='del'>-				0x00000001 0x0000002d</div><div class='del'>-				0x00000002 0x00000032</div><div class='del'>-				0x00000003 0x00000039</div><div class='del'>-				0x00000004 0x0000003f</div><div class='del'>-				0x00000005 0x00000046</div><div class='del'>-				0x00000006 0x0000004d</div><div class='del'>-				0x00000007 0x00000054</div><div class='del'>-				0x00000008 0x0000005a</div><div class='del'>-				0x00000009 0x00000061</div><div class='del'>-				0x0000000a 0x0000006a</div><div class='del'>-				0x0000000b 0x00000071</div><div class='add'>+				&lt;0x00000000 0x00000023&gt;,</div><div class='add'>+				&lt;0x00000001 0x0000002a&gt;,</div><div class='add'>+				&lt;0x00000002 0x00000030&gt;,</div><div class='add'>+				&lt;0x00000003 0x00000037&gt;,</div><div class='add'>+				&lt;0x00000004 0x0000003d&gt;,</div><div class='add'>+				&lt;0x00000005 0x00000044&gt;,</div><div class='add'>+				&lt;0x00000006 0x0000004a&gt;,</div><div class='add'>+				&lt;0x00000007 0x00000051&gt;,</div><div class='add'>+				&lt;0x00000008 0x00000057&gt;,</div><div class='add'>+				&lt;0x00000009 0x0000005e&gt;,</div><div class='add'>+				&lt;0x0000000a 0x00000064&gt;,</div><div class='add'>+				&lt;0x0000000b 0x0000006b&gt;,</div><div class='ctx'> 				/* Calibration data group 2 */</div><div class='del'>-				0x00010000 0x00000025</div><div class='del'>-				0x00010001 0x0000002c</div><div class='del'>-				0x00010002 0x00000035</div><div class='del'>-				0x00010003 0x0000003d</div><div class='del'>-				0x00010004 0x00000045</div><div class='del'>-				0x00010005 0x0000004e</div><div class='del'>-				0x00010006 0x00000057</div><div class='del'>-				0x00010007 0x00000061</div><div class='del'>-				0x00010008 0x0000006b</div><div class='del'>-				0x00010009 0x00000076</div><div class='add'>+				&lt;0x00010000 0x00000022&gt;,</div><div class='add'>+				&lt;0x00010001 0x0000002a&gt;,</div><div class='add'>+				&lt;0x00010002 0x00000032&gt;,</div><div class='add'>+				&lt;0x00010003 0x0000003a&gt;,</div><div class='add'>+				&lt;0x00010004 0x00000042&gt;,</div><div class='add'>+				&lt;0x00010005 0x0000004a&gt;,</div><div class='add'>+				&lt;0x00010006 0x00000052&gt;,</div><div class='add'>+				&lt;0x00010007 0x0000005a&gt;,</div><div class='add'>+				&lt;0x00010008 0x00000062&gt;,</div><div class='add'>+				&lt;0x00010009 0x0000006a&gt;,</div><div class='ctx'> 				/* Calibration data group 3 */</div><div class='del'>-				0x00020000 0x00000029</div><div class='del'>-				0x00020001 0x00000033</div><div class='del'>-				0x00020002 0x0000003d</div><div class='del'>-				0x00020003 0x00000049</div><div class='del'>-				0x00020004 0x00000056</div><div class='del'>-				0x00020005 0x00000061</div><div class='del'>-				0x00020006 0x0000006d</div><div class='add'>+				&lt;0x00020000 0x00000021&gt;,</div><div class='add'>+				&lt;0x00020001 0x0000002b&gt;,</div><div class='add'>+				&lt;0x00020002 0x00000035&gt;,</div><div class='add'>+				&lt;0x00020003 0x00000040&gt;,</div><div class='add'>+				&lt;0x00020004 0x0000004a&gt;,</div><div class='add'>+				&lt;0x00020005 0x00000054&gt;,</div><div class='add'>+				&lt;0x00020006 0x0000005e&gt;,</div><div class='ctx'> 				/* Calibration data group 4 */</div><div class='del'>-				0x00030000 0x00000021</div><div class='del'>-				0x00030001 0x0000002a</div><div class='del'>-				0x00030002 0x0000003c</div><div class='del'>-				0x00030003 0x0000004e&gt;;</div><div class='add'>+				&lt;0x00030000 0x00000010&gt;,</div><div class='add'>+				&lt;0x00030001 0x0000001c&gt;,</div><div class='add'>+				&lt;0x00030002 0x00000027&gt;,</div><div class='add'>+				&lt;0x00030003 0x00000032&gt;,</div><div class='add'>+				&lt;0x00030004 0x0000003e&gt;,</div><div class='add'>+				&lt;0x00030005 0x00000049&gt;,</div><div class='add'>+				&lt;0x00030006 0x00000054&gt;,</div><div class='add'>+				&lt;0x00030007 0x00000060&gt;;</div><div class='ctx'> 			little-endian;</div><div class='ctx'> 			#thermal-sensor-cells = &lt;1&gt;;</div><div class='ctx'> 		};</div><div class='hunk'>@@ -260,7 +337,8 @@</div><div class='ctx'> 			reg = &lt;0x0 0x2100000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clock-names = "dspi";</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='ctx'> 			spi-num-chipselects = &lt;6&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='hunk'>@@ -268,23 +346,25 @@</div><div class='ctx'> 		duart0: serial@21c0500 {</div><div class='ctx'> 			compatible = "fsl,ns16550", "ns16550a";</div><div class='ctx'> 			reg = &lt;0x0 0x21c0500 0x0 0x100&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;;</div><div class='del'>-			interrupts = &lt;0 32 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		duart1: serial@21c0600 {</div><div class='ctx'> 			compatible = "fsl,ns16550", "ns16550a";</div><div class='ctx'> 			reg = &lt;0x0 0x21c0600 0x0 0x100&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;;</div><div class='del'>-			interrupts = &lt;0 32 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		gpio0: gpio@2300000 {</div><div class='ctx'> 			compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";</div><div class='ctx'> 			reg = &lt;0x0 0x2300000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 36 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			little-endian;</div><div class='ctx'> 			gpio-controller;</div><div class='ctx'> 			#gpio-cells = &lt;2&gt;;</div><div class='hunk'>@@ -295,7 +375,7 @@</div><div class='ctx'> 		gpio1: gpio@2310000 {</div><div class='ctx'> 			compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";</div><div class='ctx'> 			reg = &lt;0x0 0x2310000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 36 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			little-endian;</div><div class='ctx'> 			gpio-controller;</div><div class='ctx'> 			#gpio-cells = &lt;2&gt;;</div><div class='hunk'>@@ -306,7 +386,7 @@</div><div class='ctx'> 		gpio2: gpio@2320000 {</div><div class='ctx'> 			compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";</div><div class='ctx'> 			reg = &lt;0x0 0x2320000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 37 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			little-endian;</div><div class='ctx'> 			gpio-controller;</div><div class='ctx'> 			#gpio-cells = &lt;2&gt;;</div><div class='hunk'>@@ -317,7 +397,7 @@</div><div class='ctx'> 		gpio3: gpio@2330000 {</div><div class='ctx'> 			compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";</div><div class='ctx'> 			reg = &lt;0x0 0x2330000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 37 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			little-endian;</div><div class='ctx'> 			gpio-controller;</div><div class='ctx'> 			#gpio-cells = &lt;2&gt;;</div><div class='hunk'>@@ -325,10 +405,10 @@</div><div class='ctx'> 			#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		ifc: ifc@2240000 {</div><div class='del'>-			compatible = "fsl,ifc", "simple-bus";</div><div class='add'>+		ifc: memory-controller@2240000 {</div><div class='add'>+			compatible = "fsl,ifc";</div><div class='ctx'> 			reg = &lt;0x0 0x2240000 0x0 0x20000&gt;;</div><div class='del'>-			interrupts = &lt;0 21 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			little-endian;</div><div class='ctx'> 			#address-cells = &lt;2&gt;;</div><div class='ctx'> 			#size-cells = &lt;1&gt;;</div><div class='hunk'>@@ -340,8 +420,9 @@</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			reg = &lt;0x0 0x2000000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 34 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 7&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(8)&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -350,8 +431,9 @@</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			reg = &lt;0x0 0x2010000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 34 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 7&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(8)&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -360,8 +442,9 @@</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			reg = &lt;0x0 0x2020000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 35 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 7&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(8)&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -370,8 +453,9 @@</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			reg = &lt;0x0 0x2030000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 35 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 7&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(8)&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -384,16 +468,19 @@</div><div class='ctx'> 			reg-names = "QuadSPI", "QuadSPI-memory";</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clock-names = "qspi_en", "qspi";</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;, &lt;&amp;clockgen 4 3&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		esdhc: esdhc@2140000 {</div><div class='add'>+		esdhc: mmc@2140000 {</div><div class='ctx'> 			compatible = "fsl,ls1088a-esdhc", "fsl,esdhc";</div><div class='ctx'> 			reg = &lt;0x0 0x2140000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 28 0x4&gt;; /* Level high type */</div><div class='add'>+			interrupts = &lt;GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clock-frequency = &lt;0&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 2 1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_HWACCEL 1&gt;;</div><div class='ctx'> 			voltage-ranges = &lt;1800 1800 3300 3300&gt;;</div><div class='ctx'> 			sdhci,auto-cmd12;</div><div class='ctx'> 			little-endian;</div><div class='hunk'>@@ -401,24 +488,29 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		usb0: usb3@3100000 {</div><div class='del'>-			compatible = "snps,dwc3";</div><div class='add'>+		usb0: usb@3100000 {</div><div class='add'>+			compatible = "fsl,ls1088a-dwc3", "fsl,ls1028a-dwc3";</div><div class='ctx'> 			reg = &lt;0x0 0x3100000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 80 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			dr_mode = "host";</div><div class='add'>+			iommus = &lt;&amp;smmu 1&gt;;</div><div class='add'>+			dma-coherent;</div><div class='ctx'> 			snps,quirk-frame-length-adjustment = &lt;0x20&gt;;</div><div class='ctx'> 			snps,dis_rxdet_inp3_quirk;</div><div class='ctx'> 			snps,incr-burst-type-adjustment = &lt;1&gt;, &lt;4&gt;, &lt;8&gt;, &lt;16&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		usb1: usb3@3110000 {</div><div class='del'>-			compatible = "snps,dwc3";</div><div class='add'>+		usb1: usb@3110000 {</div><div class='add'>+			compatible = "fsl,ls1088a-dwc3", "fsl,ls1028a-dwc3";</div><div class='ctx'> 			reg = &lt;0x0 0x3110000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 81 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			dr_mode = "host";</div><div class='add'>+			iommus = &lt;&amp;smmu 2&gt;;</div><div class='add'>+			dma-coherent;</div><div class='ctx'> 			snps,quirk-frame-length-adjustment = &lt;0x20&gt;;</div><div class='ctx'> 			snps,dis_rxdet_inp3_quirk;</div><div class='add'>+			snps,incr-burst-type-adjustment = &lt;1&gt;, &lt;4&gt;, &lt;8&gt;, &lt;16&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -427,8 +519,9 @@</div><div class='ctx'> 			reg = &lt;0x0 0x3200000 0x0 0x10000&gt;,</div><div class='ctx'> 				&lt;0x7 0x100520 0x0 0x4&gt;;</div><div class='ctx'> 			reg-names = "ahci", "sata-ecc";</div><div class='del'>-			interrupts = &lt;0 133 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='ctx'> 			dma-coherent;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='hunk'>@@ -446,38 +539,38 @@</div><div class='ctx'> 			sec_jr0: jr@10000 {</div><div class='ctx'> 				compatible = "fsl,sec-v5.0-job-ring",</div><div class='ctx'> 					     "fsl,sec-v4.0-job-ring";</div><div class='del'>-				reg	   = &lt;0x10000 0x10000&gt;;</div><div class='add'>+				reg = &lt;0x10000 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			sec_jr1: jr@20000 {</div><div class='ctx'> 				compatible = "fsl,sec-v5.0-job-ring",</div><div class='ctx'> 					     "fsl,sec-v4.0-job-ring";</div><div class='del'>-				reg	   = &lt;0x20000 0x10000&gt;;</div><div class='add'>+				reg = &lt;0x20000 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			sec_jr2: jr@30000 {</div><div class='ctx'> 				compatible = "fsl,sec-v5.0-job-ring",</div><div class='ctx'> 					     "fsl,sec-v4.0-job-ring";</div><div class='del'>-				reg	   = &lt;0x30000 0x10000&gt;;</div><div class='add'>+				reg = &lt;0x30000 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			sec_jr3: jr@40000 {</div><div class='ctx'> 				compatible = "fsl,sec-v5.0-job-ring",</div><div class='ctx'> 					     "fsl,sec-v4.0-job-ring";</div><div class='del'>-				reg	   = &lt;0x40000 0x10000&gt;;</div><div class='add'>+				reg = &lt;0x40000 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		pcie@3400000 {</div><div class='add'>+		pcie1: pcie@3400000 {</div><div class='ctx'> 			compatible = "fsl,ls1088a-pcie";</div><div class='del'>-			reg = &lt;0x00 0x03400000 0x0 0x00100000   /* controller registers */</div><div class='del'>-			       0x20 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='add'>+			reg = &lt;0x00 0x03400000 0x0 0x00100000&gt;, /* controller registers */</div><div class='add'>+			      &lt;0x20 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='ctx'> 			reg-names = "regs", "config";</div><div class='del'>-			interrupts = &lt;0 108 IRQ_TYPE_LEVEL_HIGH&gt;; /* aer interrupt */</div><div class='add'>+			interrupts = &lt;GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH&gt;; /* aer interrupt */</div><div class='ctx'> 			interrupt-names = "aer";</div><div class='ctx'> 			#address-cells = &lt;3&gt;;</div><div class='ctx'> 			#size-cells = &lt;2&gt;;</div><div class='hunk'>@@ -487,7 +580,7 @@</div><div class='ctx'> 			bus-range = &lt;0x0 0xff&gt;;</div><div class='ctx'> 			ranges = &lt;0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000   /* downstream I/O */</div><div class='ctx'> 				  0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000&gt;; /* non-prefetchable memory */</div><div class='del'>-			msi-parent = &lt;&amp;its&gt;;</div><div class='add'>+			msi-parent = &lt;&amp;its 0&gt;;</div><div class='ctx'> 			#interrupt-cells = &lt;1&gt;;</div><div class='ctx'> 			interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='ctx'> 			interrupt-map = &lt;0000 0 0 1 &amp;gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='hunk'>@@ -498,12 +591,25 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		pcie@3500000 {</div><div class='add'>+		pcie_ep1: pcie-ep@3400000 {</div><div class='add'>+			compatible = "fsl,ls1088a-pcie-ep";</div><div class='add'>+			reg = &lt;0x00 0x03400000 0x0 0x00100000&gt;,</div><div class='add'>+			      &lt;0x20 0x00000000 0x8 0x00000000&gt;;</div><div class='add'>+			reg-names = "regs", "addr_space";</div><div class='add'>+			interrupts = &lt;GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH&gt;; /* PME interrupt */</div><div class='add'>+			interrupt-names = "pme";</div><div class='add'>+			num-ib-windows = &lt;24&gt;;</div><div class='add'>+			num-ob-windows = &lt;256&gt;;</div><div class='add'>+			max-functions = /bits/ 8 &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie2: pcie@3500000 {</div><div class='ctx'> 			compatible = "fsl,ls1088a-pcie";</div><div class='del'>-			reg = &lt;0x00 0x03500000 0x0 0x00100000   /* controller registers */</div><div class='del'>-			       0x28 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='add'>+			reg = &lt;0x00 0x03500000 0x0 0x00100000&gt;, /* controller registers */</div><div class='add'>+			      &lt;0x28 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='ctx'> 			reg-names = "regs", "config";</div><div class='del'>-			interrupts = &lt;0 113 IRQ_TYPE_LEVEL_HIGH&gt;; /* aer interrupt */</div><div class='add'>+			interrupts = &lt;GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH&gt;; /* aer interrupt */</div><div class='ctx'> 			interrupt-names = "aer";</div><div class='ctx'> 			#address-cells = &lt;3&gt;;</div><div class='ctx'> 			#size-cells = &lt;2&gt;;</div><div class='hunk'>@@ -513,7 +619,7 @@</div><div class='ctx'> 			bus-range = &lt;0x0 0xff&gt;;</div><div class='ctx'> 			ranges = &lt;0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000   /* downstream I/O */</div><div class='ctx'> 				  0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000&gt;; /* non-prefetchable memory */</div><div class='del'>-			msi-parent = &lt;&amp;its&gt;;</div><div class='add'>+			msi-parent = &lt;&amp;its 0&gt;;</div><div class='ctx'> 			#interrupt-cells = &lt;1&gt;;</div><div class='ctx'> 			interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='ctx'> 			interrupt-map = &lt;0000 0 0 1 &amp;gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='hunk'>@@ -524,12 +630,24 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		pcie@3600000 {</div><div class='add'>+		pcie_ep2: pcie-ep@3500000 {</div><div class='add'>+			compatible = "fsl,ls1088a-pcie-ep";</div><div class='add'>+			reg = &lt;0x00 0x03500000 0x0 0x00100000&gt;,</div><div class='add'>+			      &lt;0x28 0x00000000 0x8 0x00000000&gt;;</div><div class='add'>+			reg-names = "regs", "addr_space";</div><div class='add'>+			interrupts = &lt;GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH&gt;; /* PME interrupt */</div><div class='add'>+			interrupt-names = "pme";</div><div class='add'>+			num-ib-windows = &lt;6&gt;;</div><div class='add'>+			num-ob-windows = &lt;6&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie3: pcie@3600000 {</div><div class='ctx'> 			compatible = "fsl,ls1088a-pcie";</div><div class='del'>-			reg = &lt;0x00 0x03600000 0x0 0x00100000   /* controller registers */</div><div class='del'>-			       0x30 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='add'>+			reg = &lt;0x00 0x03600000 0x0 0x00100000&gt;, /* controller registers */</div><div class='add'>+			      &lt;0x30 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='ctx'> 			reg-names = "regs", "config";</div><div class='del'>-			interrupts = &lt;0 118 IRQ_TYPE_LEVEL_HIGH&gt;; /* aer interrupt */</div><div class='add'>+			interrupts = &lt;GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH&gt;; /* aer interrupt */</div><div class='ctx'> 			interrupt-names = "aer";</div><div class='ctx'> 			#address-cells = &lt;3&gt;;</div><div class='ctx'> 			#size-cells = &lt;2&gt;;</div><div class='hunk'>@@ -539,7 +657,7 @@</div><div class='ctx'> 			bus-range = &lt;0x0 0xff&gt;;</div><div class='ctx'> 			ranges = &lt;0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000   /* downstream I/O */</div><div class='ctx'> 				  0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000&gt;; /* non-prefetchable memory */</div><div class='del'>-			msi-parent = &lt;&amp;its&gt;;</div><div class='add'>+			msi-parent = &lt;&amp;its 0&gt;;</div><div class='ctx'> 			#interrupt-cells = &lt;1&gt;;</div><div class='ctx'> 			interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='ctx'> 			interrupt-map = &lt;0000 0 0 1 &amp;gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='hunk'>@@ -550,11 +668,24 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		pcie_ep3: pcie-ep@3600000 {</div><div class='add'>+			compatible = "fsl,ls1088a-pcie-ep";</div><div class='add'>+			reg = &lt;0x00 0x03600000 0x0 0x00100000&gt;,</div><div class='add'>+			      &lt;0x30 0x00000000 0x8 0x00000000&gt;;</div><div class='add'>+			reg-names = "regs", "addr_space";</div><div class='add'>+			interrupts = &lt;GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH&gt;; /* PME interrupt */</div><div class='add'>+			interrupt-names = "pme";</div><div class='add'>+			num-ib-windows = &lt;6&gt;;</div><div class='add'>+			num-ob-windows = &lt;6&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		smmu: iommu@5000000 {</div><div class='ctx'> 			compatible = "arm,mmu-500";</div><div class='ctx'> 			reg = &lt;0 0x5000000 0 0x800000&gt;;</div><div class='ctx'> 			#iommu-cells = &lt;1&gt;;</div><div class='ctx'> 			stream-match-mask = &lt;0x7C00&gt;;</div><div class='add'>+			dma-coherent;</div><div class='ctx'> 			#global-interrupts = &lt;12&gt;;</div><div class='ctx'> 				     // global secure fault</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='hunk'>@@ -648,72 +779,197 @@</div><div class='ctx'> 		ptp-timer@8b95000 {</div><div class='ctx'> 			compatible = "fsl,dpaa2-ptp";</div><div class='ctx'> 			reg = &lt;0x0 0x8b95000 0x0 0x100&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(1)&gt;;</div><div class='ctx'> 			little-endian;</div><div class='ctx'> 			fsl,extts-fifo;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		cluster1_core0_watchdog: wdt@c000000 {</div><div class='del'>-			compatible = "arm,sp805-wdt", "arm,primecell";</div><div class='add'>+		emdio1: mdio@8b96000 {</div><div class='add'>+			compatible = "fsl,fman-memac-mdio";</div><div class='add'>+			reg = &lt;0x0 0x8b96000 0x0 0x1000&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			clock-frequency = &lt;2500000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(1)&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		emdio2: mdio@8b97000 {</div><div class='add'>+			compatible = "fsl,fman-memac-mdio";</div><div class='add'>+			reg = &lt;0x0 0x8b97000 0x0 0x1000&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			clock-frequency = &lt;2500000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(1)&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcs_mdio1: mdio@8c07000 {</div><div class='add'>+			compatible = "fsl,fman-memac-mdio";</div><div class='add'>+			reg = &lt;0x0 0x8c07000 0x0 0x1000&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcs1: ethernet-phy@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcs_mdio2: mdio@8c0b000 {</div><div class='add'>+			compatible = "fsl,fman-memac-mdio";</div><div class='add'>+			reg = &lt;0x0 0x8c0b000 0x0 0x1000&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcs2: ethernet-phy@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcs_mdio3: mdio@8c0f000 {</div><div class='add'>+			compatible = "fsl,fman-memac-mdio";</div><div class='add'>+			reg = &lt;0x0 0x8c0f000 0x0 0x1000&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcs3_0: ethernet-phy@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pcs3_1: ethernet-phy@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pcs3_2: ethernet-phy@2 {</div><div class='add'>+				reg = &lt;2&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pcs3_3: ethernet-phy@3 {</div><div class='add'>+				reg = &lt;3&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcs_mdio7: mdio@8c1f000 {</div><div class='add'>+			compatible = "fsl,fman-memac-mdio";</div><div class='add'>+			reg = &lt;0x0 0x8c1f000 0x0 0x1000&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcs7_0: ethernet-phy@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pcs7_1: ethernet-phy@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pcs7_2: ethernet-phy@2 {</div><div class='add'>+				reg = &lt;2&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pcs7_3: ethernet-phy@3 {</div><div class='add'>+				reg = &lt;3&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cluster1_core0_watchdog: watchdog@c000000 {</div><div class='add'>+			compatible = "arm,sp805", "arm,primecell";</div><div class='ctx'> 			reg = &lt;0x0 0xc000000 0x0 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;, &lt;&amp;clockgen 4 3&gt;;</div><div class='del'>-			clock-names = "apb_pclk", "wdog_clk";</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(16)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(16)&gt;;</div><div class='add'>+			clock-names = "wdog_clk", "apb_pclk";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		cluster1_core1_watchdog: wdt@c010000 {</div><div class='del'>-			compatible = "arm,sp805-wdt", "arm,primecell";</div><div class='add'>+		cluster1_core1_watchdog: watchdog@c010000 {</div><div class='add'>+			compatible = "arm,sp805", "arm,primecell";</div><div class='ctx'> 			reg = &lt;0x0 0xc010000 0x0 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;, &lt;&amp;clockgen 4 3&gt;;</div><div class='del'>-			clock-names = "apb_pclk", "wdog_clk";</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(16)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(16)&gt;;</div><div class='add'>+			clock-names = "wdog_clk", "apb_pclk";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		cluster1_core2_watchdog: wdt@c020000 {</div><div class='del'>-			compatible = "arm,sp805-wdt", "arm,primecell";</div><div class='add'>+		cluster1_core2_watchdog: watchdog@c020000 {</div><div class='add'>+			compatible = "arm,sp805", "arm,primecell";</div><div class='ctx'> 			reg = &lt;0x0 0xc020000 0x0 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;, &lt;&amp;clockgen 4 3&gt;;</div><div class='del'>-			clock-names = "apb_pclk", "wdog_clk";</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(16)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(16)&gt;;</div><div class='add'>+			clock-names = "wdog_clk", "apb_pclk";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		cluster1_core3_watchdog: wdt@c030000 {</div><div class='del'>-			compatible = "arm,sp805-wdt", "arm,primecell";</div><div class='add'>+		cluster1_core3_watchdog: watchdog@c030000 {</div><div class='add'>+			compatible = "arm,sp805", "arm,primecell";</div><div class='ctx'> 			reg = &lt;0x0 0xc030000 0x0 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;, &lt;&amp;clockgen 4 3&gt;;</div><div class='del'>-			clock-names = "apb_pclk", "wdog_clk";</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(16)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(16)&gt;;</div><div class='add'>+			clock-names = "wdog_clk", "apb_pclk";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		cluster2_core0_watchdog: wdt@c100000 {</div><div class='del'>-			compatible = "arm,sp805-wdt", "arm,primecell";</div><div class='add'>+		cluster2_core0_watchdog: watchdog@c100000 {</div><div class='add'>+			compatible = "arm,sp805", "arm,primecell";</div><div class='ctx'> 			reg = &lt;0x0 0xc100000 0x0 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;, &lt;&amp;clockgen 4 3&gt;;</div><div class='del'>-			clock-names = "apb_pclk", "wdog_clk";</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(16)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(16)&gt;;</div><div class='add'>+			clock-names = "wdog_clk", "apb_pclk";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		cluster2_core1_watchdog: wdt@c110000 {</div><div class='del'>-			compatible = "arm,sp805-wdt", "arm,primecell";</div><div class='add'>+		cluster2_core1_watchdog: watchdog@c110000 {</div><div class='add'>+			compatible = "arm,sp805", "arm,primecell";</div><div class='ctx'> 			reg = &lt;0x0 0xc110000 0x0 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;, &lt;&amp;clockgen 4 3&gt;;</div><div class='del'>-			clock-names = "apb_pclk", "wdog_clk";</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(16)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(16)&gt;;</div><div class='add'>+			clock-names = "wdog_clk", "apb_pclk";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		cluster2_core2_watchdog: wdt@c120000 {</div><div class='del'>-			compatible = "arm,sp805-wdt", "arm,primecell";</div><div class='add'>+		cluster2_core2_watchdog: watchdog@c120000 {</div><div class='add'>+			compatible = "arm,sp805", "arm,primecell";</div><div class='ctx'> 			reg = &lt;0x0 0xc120000 0x0 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;, &lt;&amp;clockgen 4 3&gt;;</div><div class='del'>-			clock-names = "apb_pclk", "wdog_clk";</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(16)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(16)&gt;;</div><div class='add'>+			clock-names = "wdog_clk", "apb_pclk";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		cluster2_core3_watchdog: wdt@c130000 {</div><div class='del'>-			compatible = "arm,sp805-wdt", "arm,primecell";</div><div class='add'>+		cluster2_core3_watchdog: watchdog@c130000 {</div><div class='add'>+			compatible = "arm,sp805", "arm,primecell";</div><div class='ctx'> 			reg = &lt;0x0 0xc130000 0x0 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;, &lt;&amp;clockgen 4 3&gt;;</div><div class='del'>-			clock-names = "apb_pclk", "wdog_clk";</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(16)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(16)&gt;;</div><div class='add'>+			clock-names = "wdog_clk", "apb_pclk";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		fsl_mc: fsl-mc@80c000000 {</div><div class='ctx'> 			compatible = "fsl,qoriq-mc";</div><div class='ctx'> 			reg = &lt;0x00000008 0x0c000000 0 0x40&gt;,	 /* MC portal base */</div><div class='ctx'> 			      &lt;0x00000000 0x08340000 0 0x40000&gt;; /* MC control reg */</div><div class='del'>-			msi-parent = &lt;&amp;its&gt;;</div><div class='add'>+			msi-parent = &lt;&amp;its 0&gt;;</div><div class='ctx'> 			iommu-map = &lt;0 &amp;smmu 0 0&gt;;	/* This is fixed-up by u-boot */</div><div class='ctx'> 			dma-coherent;</div><div class='ctx'> 			#address-cells = &lt;3&gt;;</div><div class='hunk'>@@ -730,57 +986,71 @@</div><div class='ctx'> 				#address-cells = &lt;1&gt;;</div><div class='ctx'> 				#size-cells = &lt;0&gt;;</div><div class='ctx'> </div><div class='del'>-				dpmac1: dpmac@1 {</div><div class='add'>+				dpmac1: ethernet@1 {</div><div class='ctx'> 					compatible = "fsl,qoriq-mc-dpmac";</div><div class='ctx'> 					reg = &lt;1&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				dpmac2: dpmac@2 {</div><div class='add'>+				dpmac2: ethernet@2 {</div><div class='ctx'> 					compatible = "fsl,qoriq-mc-dpmac";</div><div class='ctx'> 					reg = &lt;2&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				dpmac3: dpmac@3 {</div><div class='add'>+				dpmac3: ethernet@3 {</div><div class='ctx'> 					compatible = "fsl,qoriq-mc-dpmac";</div><div class='ctx'> 					reg = &lt;3&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				dpmac4: dpmac@4 {</div><div class='add'>+				dpmac4: ethernet@4 {</div><div class='ctx'> 					compatible = "fsl,qoriq-mc-dpmac";</div><div class='ctx'> 					reg = &lt;4&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				dpmac5: dpmac@5 {</div><div class='add'>+				dpmac5: ethernet@5 {</div><div class='ctx'> 					compatible = "fsl,qoriq-mc-dpmac";</div><div class='ctx'> 					reg = &lt;5&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				dpmac6: dpmac@6 {</div><div class='add'>+				dpmac6: ethernet@6 {</div><div class='ctx'> 					compatible = "fsl,qoriq-mc-dpmac";</div><div class='ctx'> 					reg = &lt;6&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				dpmac7: dpmac@7 {</div><div class='add'>+				dpmac7: ethernet@7 {</div><div class='ctx'> 					compatible = "fsl,qoriq-mc-dpmac";</div><div class='ctx'> 					reg = &lt;7&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				dpmac8: dpmac@8 {</div><div class='add'>+				dpmac8: ethernet@8 {</div><div class='ctx'> 					compatible = "fsl,qoriq-mc-dpmac";</div><div class='ctx'> 					reg = &lt;8&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				dpmac9: dpmac@9 {</div><div class='add'>+				dpmac9: ethernet@9 {</div><div class='ctx'> 					compatible = "fsl,qoriq-mc-dpmac";</div><div class='ctx'> 					reg = &lt;9&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				dpmac10: dpmac@a {</div><div class='add'>+				dpmac10: ethernet@a {</div><div class='ctx'> 					compatible = "fsl,qoriq-mc-dpmac";</div><div class='ctx'> 					reg = &lt;0xa&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='add'>+</div><div class='add'>+		rcpm: wakeup-controller@1e34040 {</div><div class='add'>+			compatible = "fsl,ls1088a-rcpm", "fsl,qoriq-rcpm-2.1+";</div><div class='add'>+			reg = &lt;0x0 0x1e34040 0x0 0x18&gt;;</div><div class='add'>+			#fsl,rcpm-wakeup-cells = &lt;6&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ftm_alarm0: rtc@2800000 {</div><div class='add'>+			compatible = "fsl,ls1088a-ftm-alarm";</div><div class='add'>+			reg = &lt;0x0 0x2800000 0x0 0x10000&gt;;</div><div class='add'>+			fsl,rcpm-wakeup = &lt;&amp;rcpm 0x0 0x0 0x0 0x0 0x4000 0x0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	firmware {</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts<br/>index 44894356059c..8b6915136997 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts</a></div><div class='hunk'>@@ -14,6 +14,7 @@</div><div class='ctx'> </div><div class='ctx'> #include "fsl-ls2080a.dtsi"</div><div class='ctx'> #include "fsl-ls208xa-rdb.dtsi"</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	model = "Freescale Layerscape 2080a RDB Board";</div><div class='hunk'>@@ -23,3 +24,71 @@</div><div class='ctx'> 		stdout-path = "serial1:115200n8";</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='add'>+</div><div class='add'>+&amp;dpmac5 {</div><div class='add'>+	phy-handle = &lt;&amp;mdio2_phy1&gt;;</div><div class='add'>+	phy-connection-type = "10gbase-r";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac6 {</div><div class='add'>+	phy-handle = &lt;&amp;mdio2_phy2&gt;;</div><div class='add'>+	phy-connection-type = "10gbase-r";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac7 {</div><div class='add'>+	phy-handle = &lt;&amp;mdio2_phy3&gt;;</div><div class='add'>+	phy-connection-type = "10gbase-r";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac8 {</div><div class='add'>+	phy-handle = &lt;&amp;mdio2_phy4&gt;;</div><div class='add'>+	phy-connection-type = "10gbase-r";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;emdio1 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+</div><div class='add'>+	/* CS4340 PHYs */</div><div class='add'>+	mdio1_phy1: emdio1-phy@10 {</div><div class='add'>+		reg = &lt;0x10&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mdio1_phy2: emdio1-phy@11 {</div><div class='add'>+		reg = &lt;0x11&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mdio1_phy3: emdio1-phy@12 {</div><div class='add'>+		reg = &lt;0x12&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mdio1_phy4: emdio1-phy@13 {</div><div class='add'>+		reg = &lt;0x13&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;emdio2 {</div><div class='add'>+	/* AQR405 PHYs */</div><div class='add'>+	mdio2_phy1: emdio2-phy@0 {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+		interrupts = &lt;GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		reg = &lt;0x0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mdio2_phy2: emdio2-phy@1 {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+		interrupts = &lt;GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		reg = &lt;0x1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mdio2_phy3: emdio2-phy@2 {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+		interrupts = &lt;GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		reg = &lt;0x2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mdio2_phy4: emdio2-phy@3 {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+		interrupts = &lt;GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		reg = &lt;0x3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi<br/>index f9c1d30cf4a7..e9bc1f4fa13c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi</a></div><div class='hunk'>@@ -9,14 +9,22 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+#include &lt;dt-bindings/clock/fsl,qoriq-clockgen.h&gt;</div><div class='ctx'> #include "fsl-ls208xa.dtsi"</div><div class='ctx'> </div><div class='add'>+/ {</div><div class='add'>+	pmu {</div><div class='add'>+		compatible = "arm,cortex-a57-pmu";</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;cpu {</div><div class='ctx'> 	cpu0: cpu@0 {</div><div class='ctx'> 		device_type = "cpu";</div><div class='ctx'> 		compatible = "arm,cortex-a57";</div><div class='ctx'> 		reg = &lt;0x0&gt;;</div><div class='del'>-		clocks = &lt;&amp;clockgen 1 0&gt;;</div><div class='add'>+		clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 0&gt;;</div><div class='ctx'> 		cpu-idle-states = &lt;&amp;CPU_PW20&gt;;</div><div class='ctx'> 		next-level-cache = &lt;&amp;cluster0_l2&gt;;</div><div class='ctx'> 		#cooling-cells = &lt;2&gt;;</div><div class='hunk'>@@ -26,7 +34,7 @@</div><div class='ctx'> 		device_type = "cpu";</div><div class='ctx'> 		compatible = "arm,cortex-a57";</div><div class='ctx'> 		reg = &lt;0x1&gt;;</div><div class='del'>-		clocks = &lt;&amp;clockgen 1 0&gt;;</div><div class='add'>+		clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 0&gt;;</div><div class='ctx'> 		cpu-idle-states = &lt;&amp;CPU_PW20&gt;;</div><div class='ctx'> 		next-level-cache = &lt;&amp;cluster0_l2&gt;;</div><div class='ctx'> 		#cooling-cells = &lt;2&gt;;</div><div class='hunk'>@@ -36,7 +44,7 @@</div><div class='ctx'> 		device_type = "cpu";</div><div class='ctx'> 		compatible = "arm,cortex-a57";</div><div class='ctx'> 		reg = &lt;0x100&gt;;</div><div class='del'>-		clocks = &lt;&amp;clockgen 1 1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 1&gt;;</div><div class='ctx'> 		cpu-idle-states = &lt;&amp;CPU_PW20&gt;;</div><div class='ctx'> 		next-level-cache = &lt;&amp;cluster1_l2&gt;;</div><div class='ctx'> 		#cooling-cells = &lt;2&gt;;</div><div class='hunk'>@@ -46,7 +54,7 @@</div><div class='ctx'> 		device_type = "cpu";</div><div class='ctx'> 		compatible = "arm,cortex-a57";</div><div class='ctx'> 		reg = &lt;0x101&gt;;</div><div class='del'>-		clocks = &lt;&amp;clockgen 1 1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 1&gt;;</div><div class='ctx'> 		cpu-idle-states = &lt;&amp;CPU_PW20&gt;;</div><div class='ctx'> 		next-level-cache = &lt;&amp;cluster1_l2&gt;;</div><div class='ctx'> 		#cooling-cells = &lt;2&gt;;</div><div class='hunk'>@@ -56,7 +64,7 @@</div><div class='ctx'> 		device_type = "cpu";</div><div class='ctx'> 		compatible = "arm,cortex-a57";</div><div class='ctx'> 		reg = &lt;0x200&gt;;</div><div class='del'>-		clocks = &lt;&amp;clockgen 1 2&gt;;</div><div class='add'>+		clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 2&gt;;</div><div class='ctx'> 		cpu-idle-states = &lt;&amp;CPU_PW20&gt;;</div><div class='ctx'> 		next-level-cache = &lt;&amp;cluster2_l2&gt;;</div><div class='ctx'> 		#cooling-cells = &lt;2&gt;;</div><div class='hunk'>@@ -66,7 +74,7 @@</div><div class='ctx'> 		device_type = "cpu";</div><div class='ctx'> 		compatible = "arm,cortex-a57";</div><div class='ctx'> 		reg = &lt;0x201&gt;;</div><div class='del'>-		clocks = &lt;&amp;clockgen 1 2&gt;;</div><div class='add'>+		clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 2&gt;;</div><div class='ctx'> 		cpu-idle-states = &lt;&amp;CPU_PW20&gt;;</div><div class='ctx'> 		next-level-cache = &lt;&amp;cluster2_l2&gt;;</div><div class='ctx'> 		#cooling-cells = &lt;2&gt;;</div><div class='hunk'>@@ -76,7 +84,7 @@</div><div class='ctx'> 		device_type = "cpu";</div><div class='ctx'> 		compatible = "arm,cortex-a57";</div><div class='ctx'> 		reg = &lt;0x300&gt;;</div><div class='del'>-		clocks = &lt;&amp;clockgen 1 3&gt;;</div><div class='add'>+		clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 3&gt;;</div><div class='ctx'> 		next-level-cache = &lt;&amp;cluster3_l2&gt;;</div><div class='ctx'> 		cpu-idle-states = &lt;&amp;CPU_PW20&gt;;</div><div class='ctx'> 		#cooling-cells = &lt;2&gt;;</div><div class='hunk'>@@ -86,7 +94,7 @@</div><div class='ctx'> 		device_type = "cpu";</div><div class='ctx'> 		compatible = "arm,cortex-a57";</div><div class='ctx'> 		reg = &lt;0x301&gt;;</div><div class='del'>-		clocks = &lt;&amp;clockgen 1 3&gt;;</div><div class='add'>+		clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 3&gt;;</div><div class='ctx'> 		cpu-idle-states = &lt;&amp;CPU_PW20&gt;;</div><div class='ctx'> 		next-level-cache = &lt;&amp;cluster3_l2&gt;;</div><div class='ctx'> 		#cooling-cells = &lt;2&gt;;</div><div class='hunk'>@@ -94,18 +102,26 @@</div><div class='ctx'> </div><div class='ctx'> 	cluster0_l2: l2-cache0 {</div><div class='ctx'> 		compatible = "cache";</div><div class='add'>+		cache-level = &lt;2&gt;;</div><div class='add'>+		cache-unified;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	cluster1_l2: l2-cache1 {</div><div class='ctx'> 		compatible = "cache";</div><div class='add'>+		cache-level = &lt;2&gt;;</div><div class='add'>+		cache-unified;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	cluster2_l2: l2-cache2 {</div><div class='ctx'> 		compatible = "cache";</div><div class='add'>+		cache-level = &lt;2&gt;;</div><div class='add'>+		cache-unified;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	cluster3_l2: l2-cache3 {</div><div class='ctx'> 		compatible = "cache";</div><div class='add'>+		cache-level = &lt;2&gt;;</div><div class='add'>+		cache-unified;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	CPU_PW20: cpu-pw20 {</div><div class='hunk'>@@ -119,33 +135,37 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;pcie1 {</div><div class='del'>-	reg = &lt;0x00 0x03400000 0x0 0x00100000   /* controller registers */</div><div class='del'>-	       0x10 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='add'>+	reg = &lt;0x00 0x03400000 0x0 0x00100000&gt;, /* controller registers */</div><div class='add'>+	      &lt;0x10 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='ctx'> </div><div class='ctx'> 	ranges = &lt;0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000   /* downstream I/O */</div><div class='ctx'> 		  0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000&gt;; /* non-prefetchable memory */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;pcie2 {</div><div class='del'>-	reg = &lt;0x00 0x03500000 0x0 0x00100000   /* controller registers */</div><div class='del'>-	       0x12 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='add'>+	reg = &lt;0x00 0x03500000 0x0 0x00100000&gt;, /* controller registers */</div><div class='add'>+	      &lt;0x12 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='ctx'> </div><div class='ctx'> 	ranges = &lt;0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000   /* downstream I/O */</div><div class='ctx'> 		  0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000&gt;; /* non-prefetchable memory */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;pcie3 {</div><div class='del'>-	reg = &lt;0x00 0x03600000 0x0 0x00100000   /* controller registers */</div><div class='del'>-	       0x14 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='add'>+	reg = &lt;0x00 0x03600000 0x0 0x00100000&gt;, /* controller registers */</div><div class='add'>+	      &lt;0x14 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='ctx'> </div><div class='ctx'> 	ranges = &lt;0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000   /* downstream I/O */</div><div class='ctx'> 		  0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000&gt;; /* non-prefetchable memory */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;pcie4 {</div><div class='del'>-	reg = &lt;0x00 0x03700000 0x0 0x00100000   /* controller registers */</div><div class='del'>-	       0x16 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='add'>+	reg = &lt;0x00 0x03700000 0x0 0x00100000&gt;, /* controller registers */</div><div class='add'>+	      &lt;0x16 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='ctx'> </div><div class='ctx'> 	ranges = &lt;0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000   /* downstream I/O */</div><div class='ctx'> 		  0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000&gt;; /* non-prefetchable memory */</div><div class='ctx'> };</div><div class='add'>+</div><div class='add'>+&amp;timer {</div><div class='add'>+	fsl,erratum-a008585;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts<br/>new file mode 100644<br/>index 000000000000..4461e16fd53a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts</a></div><div class='hunk'>@@ -0,0 +1,132 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Device Tree file for NXP LS2081A RDB Board.</div><div class='add'>+ *</div><div class='add'>+ * Copyright 2017 NXP</div><div class='add'>+ *</div><div class='add'>+ * Priyanka Jain &lt;priyanka.jain@nxp.com&gt;</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "fsl-ls2088a.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "NXP Layerscape 2081A RDB Board";</div><div class='add'>+	compatible = "fsl,ls2081a-rdb", "fsl,ls2081a";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;serial0;</div><div class='add'>+		serial1 = &amp;serial1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial1:115200n8";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dspi {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	n25q512a: flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		spi-max-frequency = &lt;3000000&gt;;</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;esdhc {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pca9547: mux@75 {</div><div class='add'>+		compatible = "nxp,pca9547";</div><div class='add'>+		reg = &lt;0x75&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		i2c@1 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0x1&gt;;</div><div class='add'>+</div><div class='add'>+			rtc@51 {</div><div class='add'>+				compatible = "nxp,pcf2129";</div><div class='add'>+				reg = &lt;0x51&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@2 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0x2&gt;;</div><div class='add'>+</div><div class='add'>+			ina220@40 {</div><div class='add'>+				compatible = "ti,ina220";</div><div class='add'>+				reg = &lt;0x40&gt;;</div><div class='add'>+				shunt-resistor = &lt;500&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@3 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0x3&gt;;</div><div class='add'>+</div><div class='add'>+			adt7481@4c {</div><div class='add'>+				compatible = "adi,adt7461";</div><div class='add'>+				reg = &lt;0x4c&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ifc {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qspi {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	s25fs512s0: flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;4&gt;;</div><div class='add'>+		spi-max-frequency = &lt;20000000&gt;;</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	s25fs512s1: flash@1 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;4&gt;;</div><div class='add'>+		spi-max-frequency = &lt;20000000&gt;;</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sata0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sata1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts<br/>index f6b4d75a258b..3e4e857db13f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts</a></div><div class='hunk'>@@ -22,3 +22,127 @@</div><div class='ctx'> 		stdout-path = "serial1:115200n8";</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='add'>+</div><div class='add'>+&amp;dpmac1 {</div><div class='add'>+	phy-handle = &lt;&amp;mdio1_phy1&gt;;</div><div class='add'>+	phy-connection-type = "10gbase-r";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac2 {</div><div class='add'>+	phy-handle = &lt;&amp;mdio1_phy2&gt;;</div><div class='add'>+	phy-connection-type = "10gbase-r";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac3 {</div><div class='add'>+	phy-handle = &lt;&amp;mdio1_phy3&gt;;</div><div class='add'>+	phy-connection-type = "10gbase-r";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac4 {</div><div class='add'>+	phy-handle = &lt;&amp;mdio1_phy4&gt;;</div><div class='add'>+	phy-connection-type = "10gbase-r";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac5 {</div><div class='add'>+	phy-handle = &lt;&amp;mdio2_phy1&gt;;</div><div class='add'>+	phy-connection-type = "10gbase-r";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac6 {</div><div class='add'>+	phy-handle = &lt;&amp;mdio2_phy2&gt;;</div><div class='add'>+	phy-connection-type = "10gbase-r";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac7 {</div><div class='add'>+	phy-handle = &lt;&amp;mdio2_phy3&gt;;</div><div class='add'>+	phy-connection-type = "10gbase-r";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac8 {</div><div class='add'>+	phy-handle = &lt;&amp;mdio2_phy4&gt;;</div><div class='add'>+	phy-connection-type = "10gbase-r";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;emdio1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio1_phy1: ethernet-phy@10 {</div><div class='add'>+		compatible = "ethernet-phy-id13e5.1002";</div><div class='add'>+		reg = &lt;0x10&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mdio1_phy2: ethernet-phy@11 {</div><div class='add'>+		compatible = "ethernet-phy-id13e5.1002";</div><div class='add'>+		reg = &lt;0x11&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mdio1_phy3: ethernet-phy@12 {</div><div class='add'>+		compatible = "ethernet-phy-id13e5.1002";</div><div class='add'>+		reg = &lt;0x12&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mdio1_phy4: ethernet-phy@13 {</div><div class='add'>+		compatible = "ethernet-phy-id13e5.1002";</div><div class='add'>+		reg = &lt;0x13&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;emdio2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio2_phy1: ethernet-phy@0 {</div><div class='add'>+		compatible = "ethernet-phy-id03a1.b4b0", "ethernet-phy-ieee802.3-c45";</div><div class='add'>+		interrupts-extended = &lt;&amp;extirq 1 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		reg = &lt;0x0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mdio2_phy2: ethernet-phy@1 {</div><div class='add'>+		compatible = "ethernet-phy-id03a1.b4b0", "ethernet-phy-ieee802.3-c45";</div><div class='add'>+		interrupts-extended = &lt;&amp;extirq 2 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		reg = &lt;0x1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mdio2_phy3: ethernet-phy@2 {</div><div class='add'>+		compatible = "ethernet-phy-id03a1.b4b0", "ethernet-phy-ieee802.3-c45";</div><div class='add'>+		interrupts-extended = &lt;&amp;extirq 4 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		reg = &lt;0x2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mdio2_phy4: ethernet-phy@3 {</div><div class='add'>+		compatible = "ethernet-phy-id03a1.b4b0", "ethernet-phy-ieee802.3-c45";</div><div class='add'>+		interrupts-extended = &lt;&amp;extirq 5 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		reg = &lt;0x3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio4 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio5 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio6 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio7 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio8 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi<br/>index a5f668d786b8..60c422560e33 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi</a></div><div class='hunk'>@@ -9,14 +9,22 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+#include &lt;dt-bindings/clock/fsl,qoriq-clockgen.h&gt;</div><div class='ctx'> #include "fsl-ls208xa.dtsi"</div><div class='ctx'> </div><div class='add'>+/ {</div><div class='add'>+	pmu {</div><div class='add'>+		compatible = "arm,cortex-a72-pmu";</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;cpu {</div><div class='ctx'> 	cpu0: cpu@0 {</div><div class='ctx'> 		device_type = "cpu";</div><div class='ctx'> 		compatible = "arm,cortex-a72";</div><div class='ctx'> 		reg = &lt;0x0&gt;;</div><div class='del'>-		clocks = &lt;&amp;clockgen 1 0&gt;;</div><div class='add'>+		clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 0&gt;;</div><div class='ctx'> 		cpu-idle-states = &lt;&amp;CPU_PW20&gt;;</div><div class='ctx'> 		next-level-cache = &lt;&amp;cluster0_l2&gt;;</div><div class='ctx'> 		#cooling-cells = &lt;2&gt;;</div><div class='hunk'>@@ -26,7 +34,7 @@</div><div class='ctx'> 		device_type = "cpu";</div><div class='ctx'> 		compatible = "arm,cortex-a72";</div><div class='ctx'> 		reg = &lt;0x1&gt;;</div><div class='del'>-		clocks = &lt;&amp;clockgen 1 0&gt;;</div><div class='add'>+		clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 0&gt;;</div><div class='ctx'> 		cpu-idle-states = &lt;&amp;CPU_PW20&gt;;</div><div class='ctx'> 		next-level-cache = &lt;&amp;cluster0_l2&gt;;</div><div class='ctx'> 		#cooling-cells = &lt;2&gt;;</div><div class='hunk'>@@ -36,7 +44,7 @@</div><div class='ctx'> 		device_type = "cpu";</div><div class='ctx'> 		compatible = "arm,cortex-a72";</div><div class='ctx'> 		reg = &lt;0x100&gt;;</div><div class='del'>-		clocks = &lt;&amp;clockgen 1 1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 1&gt;;</div><div class='ctx'> 		cpu-idle-states = &lt;&amp;CPU_PW20&gt;;</div><div class='ctx'> 		next-level-cache = &lt;&amp;cluster1_l2&gt;;</div><div class='ctx'> 		#cooling-cells = &lt;2&gt;;</div><div class='hunk'>@@ -46,7 +54,7 @@</div><div class='ctx'> 		device_type = "cpu";</div><div class='ctx'> 		compatible = "arm,cortex-a72";</div><div class='ctx'> 		reg = &lt;0x101&gt;;</div><div class='del'>-		clocks = &lt;&amp;clockgen 1 1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 1&gt;;</div><div class='ctx'> 		cpu-idle-states = &lt;&amp;CPU_PW20&gt;;</div><div class='ctx'> 		next-level-cache = &lt;&amp;cluster1_l2&gt;;</div><div class='ctx'> 		#cooling-cells = &lt;2&gt;;</div><div class='hunk'>@@ -56,7 +64,7 @@</div><div class='ctx'> 		device_type = "cpu";</div><div class='ctx'> 		compatible = "arm,cortex-a72";</div><div class='ctx'> 		reg = &lt;0x200&gt;;</div><div class='del'>-		clocks = &lt;&amp;clockgen 1 2&gt;;</div><div class='add'>+		clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 2&gt;;</div><div class='ctx'> 		next-level-cache = &lt;&amp;cluster2_l2&gt;;</div><div class='ctx'> 		cpu-idle-states = &lt;&amp;CPU_PW20&gt;;</div><div class='ctx'> 		#cooling-cells = &lt;2&gt;;</div><div class='hunk'>@@ -66,7 +74,7 @@</div><div class='ctx'> 		device_type = "cpu";</div><div class='ctx'> 		compatible = "arm,cortex-a72";</div><div class='ctx'> 		reg = &lt;0x201&gt;;</div><div class='del'>-		clocks = &lt;&amp;clockgen 1 2&gt;;</div><div class='add'>+		clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 2&gt;;</div><div class='ctx'> 		cpu-idle-states = &lt;&amp;CPU_PW20&gt;;</div><div class='ctx'> 		next-level-cache = &lt;&amp;cluster2_l2&gt;;</div><div class='ctx'> 		#cooling-cells = &lt;2&gt;;</div><div class='hunk'>@@ -76,7 +84,7 @@</div><div class='ctx'> 		device_type = "cpu";</div><div class='ctx'> 		compatible = "arm,cortex-a72";</div><div class='ctx'> 		reg = &lt;0x300&gt;;</div><div class='del'>-		clocks = &lt;&amp;clockgen 1 3&gt;;</div><div class='add'>+		clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 3&gt;;</div><div class='ctx'> 		cpu-idle-states = &lt;&amp;CPU_PW20&gt;;</div><div class='ctx'> 		next-level-cache = &lt;&amp;cluster3_l2&gt;;</div><div class='ctx'> 		#cooling-cells = &lt;2&gt;;</div><div class='hunk'>@@ -86,7 +94,7 @@</div><div class='ctx'> 		device_type = "cpu";</div><div class='ctx'> 		compatible = "arm,cortex-a72";</div><div class='ctx'> 		reg = &lt;0x301&gt;;</div><div class='del'>-		clocks = &lt;&amp;clockgen 1 3&gt;;</div><div class='add'>+		clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 3&gt;;</div><div class='ctx'> 		cpu-idle-states = &lt;&amp;CPU_PW20&gt;;</div><div class='ctx'> 		next-level-cache = &lt;&amp;cluster3_l2&gt;;</div><div class='ctx'> 		#cooling-cells = &lt;2&gt;;</div><div class='hunk'>@@ -94,18 +102,26 @@</div><div class='ctx'> </div><div class='ctx'> 	cluster0_l2: l2-cache0 {</div><div class='ctx'> 		compatible = "cache";</div><div class='add'>+		cache-level = &lt;2&gt;;</div><div class='add'>+		cache-unified;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	cluster1_l2: l2-cache1 {</div><div class='ctx'> 		compatible = "cache";</div><div class='add'>+		cache-level = &lt;2&gt;;</div><div class='add'>+		cache-unified;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	cluster2_l2: l2-cache2 {</div><div class='ctx'> 		compatible = "cache";</div><div class='add'>+		cache-level = &lt;2&gt;;</div><div class='add'>+		cache-unified;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	cluster3_l2: l2-cache3 {</div><div class='ctx'> 		compatible = "cache";</div><div class='add'>+		cache-level = &lt;2&gt;;</div><div class='add'>+		cache-unified;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	CPU_PW20: cpu-pw20 {</div><div class='hunk'>@@ -120,8 +136,8 @@</div><div class='ctx'> </div><div class='ctx'> &amp;pcie1 {</div><div class='ctx'> 	compatible = "fsl,ls2088a-pcie";</div><div class='del'>-	reg = &lt;0x00 0x03400000 0x0 0x00100000   /* controller registers */</div><div class='del'>-	       0x20 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='add'>+	reg = &lt;0x00 0x03400000 0x0 0x00100000&gt;, /* controller registers */</div><div class='add'>+	      &lt;0x20 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='ctx'> </div><div class='ctx'> 	ranges = &lt;0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000</div><div class='ctx'> 		  0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000&gt;;</div><div class='hunk'>@@ -129,8 +145,8 @@</div><div class='ctx'> </div><div class='ctx'> &amp;pcie2 {</div><div class='ctx'> 	compatible = "fsl,ls2088a-pcie";</div><div class='del'>-	reg = &lt;0x00 0x03500000 0x0 0x00100000   /* controller registers */</div><div class='del'>-	       0x28 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='add'>+	reg = &lt;0x00 0x03500000 0x0 0x00100000&gt;, /* controller registers */</div><div class='add'>+	      &lt;0x28 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='ctx'> </div><div class='ctx'> 	ranges = &lt;0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000</div><div class='ctx'> 		  0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000&gt;;</div><div class='hunk'>@@ -138,8 +154,8 @@</div><div class='ctx'> </div><div class='ctx'> &amp;pcie3 {</div><div class='ctx'> 	compatible = "fsl,ls2088a-pcie";</div><div class='del'>-	reg = &lt;0x00 0x03600000 0x0 0x00100000   /* controller registers */</div><div class='del'>-	       0x30 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='add'>+	reg = &lt;0x00 0x03600000 0x0 0x00100000&gt;, /* controller registers */</div><div class='add'>+	      &lt;0x30 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='ctx'> </div><div class='ctx'> 	ranges = &lt;0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000</div><div class='ctx'> 		  0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000&gt;;</div><div class='hunk'>@@ -147,8 +163,8 @@</div><div class='ctx'> </div><div class='ctx'> &amp;pcie4 {</div><div class='ctx'> 	compatible = "fsl,ls2088a-pcie";</div><div class='del'>-	reg = &lt;0x00 0x03700000 0x0 0x00100000   /* controller registers */</div><div class='del'>-	       0x38 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='add'>+	reg = &lt;0x00 0x03700000 0x0 0x00100000&gt;, /* controller registers */</div><div class='add'>+	      &lt;0x38 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='ctx'> </div><div class='ctx'> 	ranges = &lt;0x81000000 0x0 0x00000000 0x38 0x00010000 0x0 0x00010000</div><div class='ctx'> 		  0x82000000 0x0 0x40000000 0x38 0x40000000 0x0 0x40000000&gt;;</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi<br/>index 10d2fe091965..556d8c5f3180 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi</a></div><div class='hunk'>@@ -9,6 +9,27 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */</div><div class='add'>+&amp;dpmac9 {</div><div class='add'>+	phy-handle = &lt;&amp;mdio0_phy12&gt;;</div><div class='add'>+	phy-connection-type = "sgmii";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac10 {</div><div class='add'>+	phy-handle = &lt;&amp;mdio0_phy13&gt;;</div><div class='add'>+	phy-connection-type = "sgmii";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac11 {</div><div class='add'>+	phy-handle = &lt;&amp;mdio0_phy14&gt;;</div><div class='add'>+	phy-connection-type = "sgmii";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac12 {</div><div class='add'>+	phy-handle = &lt;&amp;mdio0_phy15&gt;;</div><div class='add'>+	phy-connection-type = "sgmii";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;esdhc {</div><div class='ctx'> 	mmc-hs200-1_8v;</div><div class='ctx'> 	status = "okay";</div><div class='hunk'>@@ -22,7 +43,7 @@</div><div class='ctx'> 		  0x2 0x0 0x5 0x30000000 0x00010000</div><div class='ctx'> 		  0x3 0x0 0x5 0x20000000 0x00010000&gt;;</div><div class='ctx'> </div><div class='del'>-	nor@0,0 {</div><div class='add'>+	flash@0,0 {</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;1&gt;;</div><div class='ctx'> 		compatible = "cfi-flash";</div><div class='hunk'>@@ -36,15 +57,53 @@</div><div class='ctx'> 	     reg = &lt;0x2 0x0 0x10000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	cpld@3,0 {</div><div class='del'>-	     reg = &lt;0x3 0x0 0x10000&gt;;</div><div class='del'>-	     compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";</div><div class='add'>+	boardctrl: board-control@3,0 {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		compatible = "fsl,ls208xaqds-fpga", "fsl,fpga-qixis", "simple-mfd";</div><div class='add'>+		reg = &lt;3 0 0x1000&gt;;</div><div class='add'>+		ranges = &lt;0 3 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+		mdio-mux@54 {</div><div class='add'>+			compatible = "mdio-mux-mmioreg", "mdio-mux";</div><div class='add'>+			mdio-parent-bus = &lt;&amp;emdio1&gt;;</div><div class='add'>+			reg = &lt;0x54 1&gt;;		/* BRDCFG4 */</div><div class='add'>+			mux-mask = &lt;0xe0&gt;;	/* EMI1_MDIO */</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			/* Child MDIO buses, one for each riser card:</div><div class='add'>+			 * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.</div><div class='add'>+			 * VSC8234 PHYs on the riser cards.</div><div class='add'>+			 */</div><div class='add'>+			mdio_mux3: mdio@60 {</div><div class='add'>+				reg = &lt;0x60&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				mdio0_phy12: mdio-phy0@1c {</div><div class='add'>+					reg = &lt;0x1c&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				mdio0_phy13: mdio-phy1@1d {</div><div class='add'>+					reg = &lt;0x1d&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				mdio0_phy14: mdio-phy2@1e {</div><div class='add'>+					reg = &lt;0x1e&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				mdio0_phy15: mdio-phy3@1f {</div><div class='add'>+					reg = &lt;0x1f&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;i2c0 {</div><div class='ctx'> 	status = "okay";</div><div class='del'>-	pca9547@77 {</div><div class='add'>+	i2c-mux@77 {</div><div class='ctx'> 		compatible = "nxp,pca9547";</div><div class='ctx'> 		reg = &lt;0x77&gt;;</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='hunk'>@@ -104,21 +163,21 @@</div><div class='ctx'> </div><div class='ctx'> &amp;dspi {</div><div class='ctx'> 	status = "okay";</div><div class='del'>-	dflash0: n25q128a@0 {</div><div class='add'>+	dflash0: flash@0 {</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;1&gt;;</div><div class='ctx'> 		compatible = "st,m25p80";</div><div class='ctx'> 		spi-max-frequency = &lt;3000000&gt;;</div><div class='ctx'> 		reg = &lt;0&gt;;</div><div class='ctx'> 	};</div><div class='del'>-	dflash1: sst25wf040b@1 {</div><div class='add'>+	dflash1: flash@1 {</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;1&gt;;</div><div class='ctx'> 		compatible = "st,m25p80";</div><div class='ctx'> 		spi-max-frequency = &lt;3000000&gt;;</div><div class='ctx'> 		reg = &lt;1&gt;;</div><div class='ctx'> 	};</div><div class='del'>-	dflash2: en25s64@2 {</div><div class='add'>+	dflash2: flash@2 {</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;1&gt;;</div><div class='ctx'> 		compatible = "st,m25p80";</div><div class='hunk'>@@ -129,7 +188,7 @@</div><div class='ctx'> </div><div class='ctx'> &amp;qspi {</div><div class='ctx'> 	status = "okay";</div><div class='del'>-	flash0: s25fl256s1@0 {</div><div class='add'>+	flash0: flash@0 {</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;1&gt;;</div><div class='ctx'> 		compatible = "st,m25p80";</div><div class='hunk'>@@ -138,7 +197,7 @@</div><div class='ctx'> 		spi-tx-bus-width = &lt;4&gt;;</div><div class='ctx'> 		reg = &lt;0&gt;;</div><div class='ctx'> 	};</div><div class='del'>-	flash2: s25fl256s1@2 {</div><div class='add'>+	flash2: flash@2 {</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;1&gt;;</div><div class='ctx'> 		compatible = "st,m25p80";</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi<br/>index d0d670227ae2..69cd05a30b85 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi</a></div><div class='hunk'>@@ -3,7 +3,7 @@</div><div class='ctx'>  * Device Tree file for Freescale LS2080A RDB Board.</div><div class='ctx'>  *</div><div class='ctx'>  * Copyright 2016 Freescale Semiconductor, Inc.</div><div class='del'>- * Copyright 2017 NXP</div><div class='add'>+ * Copyright 2017-2020 NXP</div><div class='ctx'>  *</div><div class='ctx'>  * Abhimanyu Saini &lt;abhimanyu.saini@nxp.com&gt;</div><div class='ctx'>  *</div><div class='hunk'>@@ -21,7 +21,7 @@</div><div class='ctx'> 		  0x2 0x0 0x5 0x30000000 0x00010000</div><div class='ctx'> 		  0x3 0x0 0x5 0x20000000 0x00010000&gt;;</div><div class='ctx'> </div><div class='del'>-	nor@0,0 {</div><div class='add'>+	flash@0,0 {</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;1&gt;;</div><div class='ctx'> 		compatible = "cfi-flash";</div><div class='hunk'>@@ -44,11 +44,13 @@</div><div class='ctx'> </div><div class='ctx'> &amp;i2c0 {</div><div class='ctx'> 	status = "okay";</div><div class='del'>-	pca9547@75 {</div><div class='add'>+	i2c-mux@75 {</div><div class='ctx'> 		compatible = "nxp,pca9547";</div><div class='ctx'> 		reg = &lt;0x75&gt;;</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;0&gt;;</div><div class='add'>+		idle-state = &lt;0&gt;;</div><div class='add'>+</div><div class='ctx'> 		i2c@1 {</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='hunk'>@@ -56,6 +58,8 @@</div><div class='ctx'> 			rtc@68 {</div><div class='ctx'> 				compatible = "dallas,ds3232";</div><div class='ctx'> 				reg = &lt;0x68&gt;;</div><div class='add'>+				/* IRQ_RTC_B -&gt; IRQ06, active low */</div><div class='add'>+				interrupts-extended = &lt;&amp;extirq 6 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -98,7 +102,7 @@</div><div class='ctx'> </div><div class='ctx'> &amp;dspi {</div><div class='ctx'> 	status = "okay";</div><div class='del'>-	dflash0: n25q512a@0 {</div><div class='add'>+	dflash0: flash@0 {</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;1&gt;;</div><div class='ctx'> 		compatible = "st,m25p80";</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi<br/>index 3944ef16ec60..9421fdd7e30e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi</a></div><div class='hunk'>@@ -3,12 +3,13 @@</div><div class='ctx'>  * Device Tree Include file for Freescale Layerscape-2080A family SoC.</div><div class='ctx'>  *</div><div class='ctx'>  * Copyright 2016 Freescale Semiconductor, Inc.</div><div class='del'>- * Copyright 2017 NXP</div><div class='add'>+ * Copyright 2017-2020 NXP</div><div class='ctx'>  *</div><div class='ctx'>  * Abhimanyu Saini &lt;abhimanyu.saini@nxp.com&gt;</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+#include &lt;dt-bindings/clock/fsl,qoriq-clockgen.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/thermal/thermal.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='ctx'> </div><div class='hunk'>@@ -20,6 +21,7 @@</div><div class='ctx'> </div><div class='ctx'> 	aliases {</div><div class='ctx'> 		crypto = &amp;crypto;</div><div class='add'>+		rtc1 = &amp;ftm_alarm0;</div><div class='ctx'> 		serial0 = &amp;serial0;</div><div class='ctx'> 		serial1 = &amp;serial1;</div><div class='ctx'> 		serial2 = &amp;serial2;</div><div class='hunk'>@@ -56,42 +58,84 @@</div><div class='ctx'> 		#size-cells = &lt;2&gt;;</div><div class='ctx'> 		ranges;</div><div class='ctx'> 		interrupt-controller;</div><div class='del'>-		interrupts = &lt;1 9 0x4&gt;;</div><div class='add'>+		interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> </div><div class='del'>-		its: gic-its@6020000 {</div><div class='add'>+		its: msi-controller@6020000 {</div><div class='ctx'> 			compatible = "arm,gic-v3-its";</div><div class='ctx'> 			msi-controller;</div><div class='add'>+			#msi-cells = &lt;1&gt;;</div><div class='ctx'> 			reg = &lt;0x0 0x6020000 0 0x20000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	rstcr: syscon@1e60000 {</div><div class='del'>-		compatible = "fsl,ls2080a-rstcr", "syscon";</div><div class='add'>+		compatible = "fsl,ls1028a-reset", "syscon", "simple-mfd";</div><div class='ctx'> 		reg = &lt;0x0 0x1e60000 0x0 0x4&gt;;</div><div class='del'>-	};</div><div class='ctx'> </div><div class='del'>-	reboot {</div><div class='del'>-		compatible ="syscon-reboot";</div><div class='del'>-		regmap = &lt;&amp;rstcr&gt;;</div><div class='del'>-		offset = &lt;0x0&gt;;</div><div class='del'>-		mask = &lt;0x2&gt;;</div><div class='add'>+		reboot {</div><div class='add'>+			compatible = "syscon-reboot";</div><div class='add'>+			offset = &lt;0x0&gt;;</div><div class='add'>+			mask = &lt;0x2&gt;;</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	thermal-zones {</div><div class='del'>-		cpu_thermal: cpu-thermal {</div><div class='add'>+		ddr-ctrl1-thermal {</div><div class='ctx'> 			polling-delay-passive = &lt;1000&gt;;</div><div class='ctx'> 			polling-delay = &lt;5000&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;tmu 1&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				ddr-ctrler1-crit {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='ctx'> </div><div class='add'>+		ddr-ctrl2-thermal {</div><div class='add'>+			polling-delay-passive = &lt;1000&gt;;</div><div class='add'>+			polling-delay = &lt;5000&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;tmu 2&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				ddr-ctrler2-crit {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ddr-ctrl3-thermal {</div><div class='add'>+			polling-delay-passive = &lt;1000&gt;;</div><div class='add'>+			polling-delay = &lt;5000&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;tmu 3&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				ddr-ctrler3-crit {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cluster1-thermal {</div><div class='add'>+			polling-delay-passive = &lt;1000&gt;;</div><div class='add'>+			polling-delay = &lt;5000&gt;;</div><div class='ctx'> 			thermal-sensors = &lt;&amp;tmu 4&gt;;</div><div class='ctx'> </div><div class='ctx'> 			trips {</div><div class='del'>-				cpu_alert: cpu-alert {</div><div class='del'>-					temperature = &lt;75000&gt;;</div><div class='add'>+				core_cluster1_alert: core-cluster1-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='ctx'> 					hysteresis = &lt;2000&gt;;</div><div class='ctx'> 					type = "passive";</div><div class='ctx'> 				};</div><div class='del'>-				cpu_crit: cpu-crit {</div><div class='del'>-					temperature = &lt;85000&gt;;</div><div class='add'>+</div><div class='add'>+				core-cluster1-crit {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='ctx'> 					hysteresis = &lt;2000&gt;;</div><div class='ctx'> 					type = "critical";</div><div class='ctx'> 				};</div><div class='hunk'>@@ -99,14 +143,95 @@</div><div class='ctx'> </div><div class='ctx'> 			cooling-maps {</div><div class='ctx'> 				map0 {</div><div class='del'>-					trip = &lt;&amp;cpu_alert&gt;;</div><div class='add'>+					trip = &lt;&amp;core_cluster1_alert&gt;;</div><div class='ctx'> 					cooling-device =</div><div class='ctx'> 						&lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='del'>-						&lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+						&lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cluster2-thermal {</div><div class='add'>+			polling-delay-passive = &lt;1000&gt;;</div><div class='add'>+			polling-delay = &lt;5000&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;tmu 5&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				core_cluster2_alert: core-cluster2-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core-cluster2-crit {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;core_cluster2_alert&gt;;</div><div class='add'>+					cooling-device =</div><div class='ctx'> 						&lt;&amp;cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='del'>-						&lt;&amp;cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+						&lt;&amp;cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cluster3-thermal {</div><div class='add'>+			polling-delay-passive = &lt;1000&gt;;</div><div class='add'>+			polling-delay = &lt;5000&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;tmu 6&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				core_cluster3_alert: core-cluster3-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core-cluster3-crit {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;core_cluster3_alert&gt;;</div><div class='add'>+					cooling-device =</div><div class='ctx'> 						&lt;&amp;cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='del'>-						&lt;&amp;cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+						&lt;&amp;cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cluster4-thermal {</div><div class='add'>+			polling-delay-passive = &lt;1000&gt;;</div><div class='add'>+			polling-delay = &lt;5000&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;tmu 7&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				core_cluster4_alert: core-cluster4-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core-cluster4-crit {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;core_cluster4_alert&gt;;</div><div class='add'>+					cooling-device =</div><div class='ctx'> 						&lt;&amp;cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='ctx'> 						&lt;&amp;cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='ctx'> 				};</div><div class='hunk'>@@ -114,18 +239,12 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	timer {</div><div class='add'>+	timer: timer {</div><div class='ctx'> 		compatible = "arm,armv8-timer";</div><div class='del'>-		interrupts = &lt;1 13 4&gt;, /* Physical Secure PPI, active-low */</div><div class='del'>-			     &lt;1 14 4&gt;, /* Physical Non-Secure PPI, active-low */</div><div class='del'>-			     &lt;1 11 4&gt;, /* Virtual PPI, active-low */</div><div class='del'>-			     &lt;1 10 4&gt;; /* Hypervisor PPI, active-low */</div><div class='del'>-		fsl,erratum-a008585;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	pmu {</div><div class='del'>-		compatible = "arm,armv8-pmuv3";</div><div class='del'>-		interrupts = &lt;1 7 0x8&gt;; /* PMU PPI, Level low type */</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH&gt;, /* Physical Secure PPI */</div><div class='add'>+			     &lt;GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH&gt;, /* Physical Non-Secure PPI */</div><div class='add'>+			     &lt;GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH&gt;, /* Virtual PPI */</div><div class='add'>+			     &lt;GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH&gt;; /* Hypervisor PPI */</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	psci {</div><div class='hunk'>@@ -153,47 +272,87 @@</div><div class='ctx'> 			little-endian;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		sfp: efuse@1e80000 {</div><div class='add'>+			compatible = "fsl,ls1028a-sfp";</div><div class='add'>+			reg = &lt;0x0 0x1e80000 0x0 0x10000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='add'>+			clock-names = "sfp";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		isc: syscon@1f70000 {</div><div class='add'>+			compatible = "fsl,ls2080a-isc", "syscon";</div><div class='add'>+			reg = &lt;0x0 0x1f70000 0x0 0x10000&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges = &lt;0x0 0x0 0x1f70000 0x10000&gt;;</div><div class='add'>+</div><div class='add'>+			extirq: interrupt-controller@14 {</div><div class='add'>+				compatible = "fsl,ls2080a-extirq", "fsl,ls1088a-extirq";</div><div class='add'>+				#interrupt-cells = &lt;2&gt;;</div><div class='add'>+				#address-cells = &lt;0&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				reg = &lt;0x14 4&gt;;</div><div class='add'>+				interrupt-map =</div><div class='add'>+					&lt;0 0 &amp;gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;1 0 &amp;gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;2 0 &amp;gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;3 0 &amp;gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;4 0 &amp;gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;5 0 &amp;gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;6 0 &amp;gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;7 0 &amp;gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;8 0 &amp;gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;9 0 &amp;gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;10 0 &amp;gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;11 0 &amp;gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				interrupt-map-mask = &lt;0xf 0x0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		tmu: tmu@1f80000 {</div><div class='ctx'> 			compatible = "fsl,qoriq-tmu";</div><div class='ctx'> 			reg = &lt;0x0 0x1f80000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 23 0x4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			fsl,tmu-range = &lt;0xb0000 0x9002a 0x6004c 0x30062&gt;;</div><div class='del'>-			fsl,tmu-calibration = &lt;0x00000000 0x00000026</div><div class='del'>-					       0x00000001 0x0000002d</div><div class='del'>-					       0x00000002 0x00000032</div><div class='del'>-					       0x00000003 0x00000039</div><div class='del'>-					       0x00000004 0x0000003f</div><div class='del'>-					       0x00000005 0x00000046</div><div class='del'>-					       0x00000006 0x0000004d</div><div class='del'>-					       0x00000007 0x00000054</div><div class='del'>-					       0x00000008 0x0000005a</div><div class='del'>-					       0x00000009 0x00000061</div><div class='del'>-					       0x0000000a 0x0000006a</div><div class='del'>-					       0x0000000b 0x00000071</div><div class='del'>-</div><div class='del'>-					       0x00010000 0x00000025</div><div class='del'>-					       0x00010001 0x0000002c</div><div class='del'>-					       0x00010002 0x00000035</div><div class='del'>-					       0x00010003 0x0000003d</div><div class='del'>-					       0x00010004 0x00000045</div><div class='del'>-					       0x00010005 0x0000004e</div><div class='del'>-					       0x00010006 0x00000057</div><div class='del'>-					       0x00010007 0x00000061</div><div class='del'>-					       0x00010008 0x0000006b</div><div class='del'>-					       0x00010009 0x00000076</div><div class='del'>-</div><div class='del'>-					       0x00020000 0x00000029</div><div class='del'>-					       0x00020001 0x00000033</div><div class='del'>-					       0x00020002 0x0000003d</div><div class='del'>-					       0x00020003 0x00000049</div><div class='del'>-					       0x00020004 0x00000056</div><div class='del'>-					       0x00020005 0x00000061</div><div class='del'>-					       0x00020006 0x0000006d</div><div class='del'>-</div><div class='del'>-					       0x00030000 0x00000021</div><div class='del'>-					       0x00030001 0x0000002a</div><div class='del'>-					       0x00030002 0x0000003c</div><div class='del'>-					       0x00030003 0x0000004e&gt;;</div><div class='add'>+			fsl,tmu-calibration =</div><div class='add'>+					&lt;0x00000000 0x00000026&gt;,</div><div class='add'>+					&lt;0x00000001 0x0000002d&gt;,</div><div class='add'>+					&lt;0x00000002 0x00000032&gt;,</div><div class='add'>+					&lt;0x00000003 0x00000039&gt;,</div><div class='add'>+					&lt;0x00000004 0x0000003f&gt;,</div><div class='add'>+					&lt;0x00000005 0x00000046&gt;,</div><div class='add'>+					&lt;0x00000006 0x0000004d&gt;,</div><div class='add'>+					&lt;0x00000007 0x00000054&gt;,</div><div class='add'>+					&lt;0x00000008 0x0000005a&gt;,</div><div class='add'>+					&lt;0x00000009 0x00000061&gt;,</div><div class='add'>+					&lt;0x0000000a 0x0000006a&gt;,</div><div class='add'>+					&lt;0x0000000b 0x00000071&gt;,</div><div class='add'>+</div><div class='add'>+					&lt;0x00010000 0x00000025&gt;,</div><div class='add'>+					&lt;0x00010001 0x0000002c&gt;,</div><div class='add'>+					&lt;0x00010002 0x00000035&gt;,</div><div class='add'>+					&lt;0x00010003 0x0000003d&gt;,</div><div class='add'>+					&lt;0x00010004 0x00000045&gt;,</div><div class='add'>+					&lt;0x00010005 0x0000004e&gt;,</div><div class='add'>+					&lt;0x00010006 0x00000057&gt;,</div><div class='add'>+					&lt;0x00010007 0x00000061&gt;,</div><div class='add'>+					&lt;0x00010008 0x0000006b&gt;,</div><div class='add'>+					&lt;0x00010009 0x00000076&gt;,</div><div class='add'>+</div><div class='add'>+					&lt;0x00020000 0x00000029&gt;,</div><div class='add'>+					&lt;0x00020001 0x00000033&gt;,</div><div class='add'>+					&lt;0x00020002 0x0000003d&gt;,</div><div class='add'>+					&lt;0x00020003 0x00000049&gt;,</div><div class='add'>+					&lt;0x00020004 0x00000056&gt;,</div><div class='add'>+					&lt;0x00020005 0x00000061&gt;,</div><div class='add'>+					&lt;0x00020006 0x0000006d&gt;,</div><div class='add'>+</div><div class='add'>+					&lt;0x00030000 0x00000021&gt;,</div><div class='add'>+					&lt;0x00030001 0x0000002a&gt;,</div><div class='add'>+					&lt;0x00030002 0x0000003c&gt;,</div><div class='add'>+					&lt;0x00030003 0x0000004e&gt;;</div><div class='ctx'> 			little-endian;</div><div class='ctx'> 			#thermal-sensor-cells = &lt;1&gt;;</div><div class='ctx'> 		};</div><div class='hunk'>@@ -201,85 +360,113 @@</div><div class='ctx'> 		serial0: serial@21c0500 {</div><div class='ctx'> 			compatible = "fsl,ns16550", "ns16550a";</div><div class='ctx'> 			reg = &lt;0x0 0x21c0500 0x0 0x100&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;;</div><div class='del'>-			interrupts = &lt;0 32 0x4&gt;; /* Level high type */</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		serial1: serial@21c0600 {</div><div class='ctx'> 			compatible = "fsl,ns16550", "ns16550a";</div><div class='ctx'> 			reg = &lt;0x0 0x21c0600 0x0 0x100&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;;</div><div class='del'>-			interrupts = &lt;0 32 0x4&gt;; /* Level high type */</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		serial2: serial@21d0500 {</div><div class='ctx'> 			compatible = "fsl,ns16550", "ns16550a";</div><div class='ctx'> 			reg = &lt;0x0 0x21d0500 0x0 0x100&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;;</div><div class='del'>-			interrupts = &lt;0 33 0x4&gt;; /* Level high type */</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		serial3: serial@21d0600 {</div><div class='ctx'> 			compatible = "fsl,ns16550", "ns16550a";</div><div class='ctx'> 			reg = &lt;0x0 0x21d0600 0x0 0x100&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;;</div><div class='del'>-			interrupts = &lt;0 33 0x4&gt;; /* Level high type */</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		cluster1_core0_watchdog: wdt@c000000 {</div><div class='del'>-			compatible = "arm,sp805-wdt", "arm,primecell";</div><div class='add'>+		cluster1_core0_watchdog: watchdog@c000000 {</div><div class='add'>+			compatible = "arm,sp805", "arm,primecell";</div><div class='ctx'> 			reg = &lt;0x0 0xc000000 0x0 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;, &lt;&amp;clockgen 4 3&gt;;</div><div class='del'>-			clock-names = "apb_pclk", "wdog_clk";</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='add'>+			clock-names = "wdog_clk", "apb_pclk";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		cluster1_core1_watchdog: wdt@c010000 {</div><div class='del'>-			compatible = "arm,sp805-wdt", "arm,primecell";</div><div class='add'>+		cluster1_core1_watchdog: watchdog@c010000 {</div><div class='add'>+			compatible = "arm,sp805", "arm,primecell";</div><div class='ctx'> 			reg = &lt;0x0 0xc010000 0x0 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;, &lt;&amp;clockgen 4 3&gt;;</div><div class='del'>-			clock-names = "apb_pclk", "wdog_clk";</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='add'>+			clock-names = "wdog_clk", "apb_pclk";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		cluster2_core0_watchdog: wdt@c100000 {</div><div class='del'>-			compatible = "arm,sp805-wdt", "arm,primecell";</div><div class='add'>+		cluster2_core0_watchdog: watchdog@c100000 {</div><div class='add'>+			compatible = "arm,sp805", "arm,primecell";</div><div class='ctx'> 			reg = &lt;0x0 0xc100000 0x0 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;, &lt;&amp;clockgen 4 3&gt;;</div><div class='del'>-			clock-names = "apb_pclk", "wdog_clk";</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='add'>+			clock-names = "wdog_clk", "apb_pclk";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		cluster2_core1_watchdog: wdt@c110000 {</div><div class='del'>-			compatible = "arm,sp805-wdt", "arm,primecell";</div><div class='add'>+		cluster2_core1_watchdog: watchdog@c110000 {</div><div class='add'>+			compatible = "arm,sp805", "arm,primecell";</div><div class='ctx'> 			reg = &lt;0x0 0xc110000 0x0 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;, &lt;&amp;clockgen 4 3&gt;;</div><div class='del'>-			clock-names = "apb_pclk", "wdog_clk";</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='add'>+			clock-names = "wdog_clk", "apb_pclk";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		cluster3_core0_watchdog: wdt@c200000 {</div><div class='del'>-			compatible = "arm,sp805-wdt", "arm,primecell";</div><div class='add'>+		cluster3_core0_watchdog: watchdog@c200000 {</div><div class='add'>+			compatible = "arm,sp805", "arm,primecell";</div><div class='ctx'> 			reg = &lt;0x0 0xc200000 0x0 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;, &lt;&amp;clockgen 4 3&gt;;</div><div class='del'>-			clock-names = "apb_pclk", "wdog_clk";</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='add'>+			clock-names = "wdog_clk", "apb_pclk";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		cluster3_core1_watchdog: wdt@c210000 {</div><div class='del'>-			compatible = "arm,sp805-wdt", "arm,primecell";</div><div class='add'>+		cluster3_core1_watchdog: watchdog@c210000 {</div><div class='add'>+			compatible = "arm,sp805", "arm,primecell";</div><div class='ctx'> 			reg = &lt;0x0 0xc210000 0x0 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;, &lt;&amp;clockgen 4 3&gt;;</div><div class='del'>-			clock-names = "apb_pclk", "wdog_clk";</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='add'>+			clock-names = "wdog_clk", "apb_pclk";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		cluster4_core0_watchdog: wdt@c300000 {</div><div class='del'>-			compatible = "arm,sp805-wdt", "arm,primecell";</div><div class='add'>+		cluster4_core0_watchdog: watchdog@c300000 {</div><div class='add'>+			compatible = "arm,sp805", "arm,primecell";</div><div class='ctx'> 			reg = &lt;0x0 0xc300000 0x0 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;, &lt;&amp;clockgen 4 3&gt;;</div><div class='del'>-			clock-names = "apb_pclk", "wdog_clk";</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='add'>+			clock-names = "wdog_clk", "apb_pclk";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		cluster4_core1_watchdog: wdt@c310000 {</div><div class='del'>-			compatible = "arm,sp805-wdt", "arm,primecell";</div><div class='add'>+		cluster4_core1_watchdog: watchdog@c310000 {</div><div class='add'>+			compatible = "arm,sp805", "arm,primecell";</div><div class='ctx'> 			reg = &lt;0x0 0xc310000 0x0 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;, &lt;&amp;clockgen 4 3&gt;;</div><div class='del'>-			clock-names = "apb_pclk", "wdog_clk";</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='add'>+			clock-names = "wdog_clk", "apb_pclk";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		crypto: crypto@8000000 {</div><div class='hunk'>@@ -295,28 +482,28 @@</div><div class='ctx'> 			sec_jr0: jr@10000 {</div><div class='ctx'> 				compatible = "fsl,sec-v5.0-job-ring",</div><div class='ctx'> 					     "fsl,sec-v4.0-job-ring";</div><div class='del'>-				reg	   = &lt;0x10000 0x10000&gt;;</div><div class='add'>+				reg = &lt;0x10000 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			sec_jr1: jr@20000 {</div><div class='ctx'> 				compatible = "fsl,sec-v5.0-job-ring",</div><div class='ctx'> 					     "fsl,sec-v4.0-job-ring";</div><div class='del'>-				reg	   = &lt;0x20000 0x10000&gt;;</div><div class='add'>+				reg = &lt;0x20000 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			sec_jr2: jr@30000 {</div><div class='ctx'> 				compatible = "fsl,sec-v5.0-job-ring",</div><div class='ctx'> 					     "fsl,sec-v4.0-job-ring";</div><div class='del'>-				reg	   = &lt;0x30000 0x10000&gt;;</div><div class='add'>+				reg = &lt;0x30000 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			sec_jr3: jr@40000 {</div><div class='ctx'> 				compatible = "fsl,sec-v5.0-job-ring",</div><div class='ctx'> 					     "fsl,sec-v4.0-job-ring";</div><div class='del'>-				reg	   = &lt;0x40000 0x10000&gt;;</div><div class='add'>+				reg = &lt;0x40000 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='hunk'>@@ -329,16 +516,249 @@</div><div class='ctx'> 		ptp-timer@8b95000 {</div><div class='ctx'> 			compatible = "fsl,dpaa2-ptp";</div><div class='ctx'> 			reg = &lt;0x0 0x8b95000 0x0 0x100&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='ctx'> 			little-endian;</div><div class='ctx'> 			fsl,extts-fifo;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		emdio1: mdio@8b96000 {</div><div class='add'>+			compatible = "fsl,fman-memac-mdio";</div><div class='add'>+			reg = &lt;0x0 0x8b96000 0x0 0x1000&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			clock-frequency = &lt;2500000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		emdio2: mdio@8b97000 {</div><div class='add'>+			compatible = "fsl,fman-memac-mdio";</div><div class='add'>+			reg = &lt;0x0 0x8b97000 0x0 0x1000&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			clock-frequency = &lt;2500000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcs_mdio1: mdio@8c07000 {</div><div class='add'>+			compatible = "fsl,fman-memac-mdio";</div><div class='add'>+			reg = &lt;0x0 0x8c07000 0x0 0x1000&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcs1: ethernet-phy@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcs_mdio2: mdio@8c0b000 {</div><div class='add'>+			compatible = "fsl,fman-memac-mdio";</div><div class='add'>+			reg = &lt;0x0 0x8c0b000 0x0 0x1000&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcs2: ethernet-phy@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcs_mdio3: mdio@8c0f000 {</div><div class='add'>+			compatible = "fsl,fman-memac-mdio";</div><div class='add'>+			reg = &lt;0x0 0x8c0f000 0x0 0x1000&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcs3: ethernet-phy@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcs_mdio4: mdio@8c13000 {</div><div class='add'>+			compatible = "fsl,fman-memac-mdio";</div><div class='add'>+			reg = &lt;0x0 0x8c13000 0x0 0x1000&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcs4: ethernet-phy@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcs_mdio5: mdio@8c17000 {</div><div class='add'>+			compatible = "fsl,fman-memac-mdio";</div><div class='add'>+			reg = &lt;0x0 0x8c17000 0x0 0x1000&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcs5: ethernet-phy@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcs_mdio6: mdio@8c1b000 {</div><div class='add'>+			compatible = "fsl,fman-memac-mdio";</div><div class='add'>+			reg = &lt;0x0 0x8c1b000 0x0 0x1000&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcs6: ethernet-phy@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcs_mdio7: mdio@8c1f000 {</div><div class='add'>+			compatible = "fsl,fman-memac-mdio";</div><div class='add'>+			reg = &lt;0x0 0x8c1f000 0x0 0x1000&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcs7: ethernet-phy@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcs_mdio8: mdio@8c23000 {</div><div class='add'>+			compatible = "fsl,fman-memac-mdio";</div><div class='add'>+			reg = &lt;0x0 0x8c23000 0x0 0x1000&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcs8: ethernet-phy@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcs_mdio9: mdio@8c27000 {</div><div class='add'>+			compatible = "fsl,fman-memac-mdio";</div><div class='add'>+			reg = &lt;0x0 0x8c27000 0x0 0x1000&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcs9: ethernet-phy@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcs_mdio10: mdio@8c2b000 {</div><div class='add'>+			compatible = "fsl,fman-memac-mdio";</div><div class='add'>+			reg = &lt;0x0 0x8c2b000 0x0 0x1000&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcs10: ethernet-phy@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcs_mdio11: mdio@8c2f000 {</div><div class='add'>+			compatible = "fsl,fman-memac-mdio";</div><div class='add'>+			reg = &lt;0x0 0x8c2f000 0x0 0x1000&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcs11: ethernet-phy@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcs_mdio12: mdio@8c33000 {</div><div class='add'>+			compatible = "fsl,fman-memac-mdio";</div><div class='add'>+			reg = &lt;0x0 0x8c33000 0x0 0x1000&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcs12: ethernet-phy@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcs_mdio13: mdio@8c37000 {</div><div class='add'>+			compatible = "fsl,fman-memac-mdio";</div><div class='add'>+			reg = &lt;0x0 0x8c37000 0x0 0x1000&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcs13: ethernet-phy@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcs_mdio14: mdio@8c3b000 {</div><div class='add'>+			compatible = "fsl,fman-memac-mdio";</div><div class='add'>+			reg = &lt;0x0 0x8c3b000 0x0 0x1000&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcs14: ethernet-phy@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcs_mdio15: mdio@8c3f000 {</div><div class='add'>+			compatible = "fsl,fman-memac-mdio";</div><div class='add'>+			reg = &lt;0x0 0x8c3f000 0x0 0x1000&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcs15: ethernet-phy@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcs_mdio16: mdio@8c43000 {</div><div class='add'>+			compatible = "fsl,fman-memac-mdio";</div><div class='add'>+			reg = &lt;0x0 0x8c43000 0x0 0x1000&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcs16: ethernet-phy@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		fsl_mc: fsl-mc@80c000000 {</div><div class='ctx'> 			compatible = "fsl,qoriq-mc";</div><div class='ctx'> 			reg = &lt;0x00000008 0x0c000000 0 0x40&gt;,	 /* MC portal base */</div><div class='ctx'> 			      &lt;0x00000000 0x08340000 0 0x40000&gt;; /* MC control reg */</div><div class='del'>-			msi-parent = &lt;&amp;its&gt;;</div><div class='add'>+			msi-parent = &lt;&amp;its 0&gt;;</div><div class='ctx'> 			iommu-map = &lt;0 &amp;smmu 0 0&gt;;	/* This is fixed-up by u-boot */</div><div class='ctx'> 			dma-coherent;</div><div class='ctx'> 			#address-cells = &lt;3&gt;;</div><div class='hunk'>@@ -358,84 +778,100 @@</div><div class='ctx'> 				#address-cells = &lt;1&gt;;</div><div class='ctx'> 				#size-cells = &lt;0&gt;;</div><div class='ctx'> </div><div class='del'>-				dpmac1: dpmac@1 {</div><div class='add'>+				dpmac1: ethernet@1 {</div><div class='ctx'> 					compatible = "fsl,qoriq-mc-dpmac";</div><div class='ctx'> 					reg = &lt;0x1&gt;;</div><div class='add'>+					pcs-handle = &lt;&amp;pcs1&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				dpmac2: dpmac@2 {</div><div class='add'>+				dpmac2: ethernet@2 {</div><div class='ctx'> 					compatible = "fsl,qoriq-mc-dpmac";</div><div class='ctx'> 					reg = &lt;0x2&gt;;</div><div class='add'>+					pcs-handle = &lt;&amp;pcs2&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				dpmac3: dpmac@3 {</div><div class='add'>+				dpmac3: ethernet@3 {</div><div class='ctx'> 					compatible = "fsl,qoriq-mc-dpmac";</div><div class='ctx'> 					reg = &lt;0x3&gt;;</div><div class='add'>+					pcs-handle = &lt;&amp;pcs3&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				dpmac4: dpmac@4 {</div><div class='add'>+				dpmac4: ethernet@4 {</div><div class='ctx'> 					compatible = "fsl,qoriq-mc-dpmac";</div><div class='ctx'> 					reg = &lt;0x4&gt;;</div><div class='add'>+					pcs-handle = &lt;&amp;pcs4&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				dpmac5: dpmac@5 {</div><div class='add'>+				dpmac5: ethernet@5 {</div><div class='ctx'> 					compatible = "fsl,qoriq-mc-dpmac";</div><div class='ctx'> 					reg = &lt;0x5&gt;;</div><div class='add'>+					pcs-handle = &lt;&amp;pcs5&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				dpmac6: dpmac@6 {</div><div class='add'>+				dpmac6: ethernet@6 {</div><div class='ctx'> 					compatible = "fsl,qoriq-mc-dpmac";</div><div class='ctx'> 					reg = &lt;0x6&gt;;</div><div class='add'>+					pcs-handle = &lt;&amp;pcs6&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				dpmac7: dpmac@7 {</div><div class='add'>+				dpmac7: ethernet@7 {</div><div class='ctx'> 					compatible = "fsl,qoriq-mc-dpmac";</div><div class='ctx'> 					reg = &lt;0x7&gt;;</div><div class='add'>+					pcs-handle = &lt;&amp;pcs7&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				dpmac8: dpmac@8 {</div><div class='add'>+				dpmac8: ethernet@8 {</div><div class='ctx'> 					compatible = "fsl,qoriq-mc-dpmac";</div><div class='ctx'> 					reg = &lt;0x8&gt;;</div><div class='add'>+					pcs-handle = &lt;&amp;pcs8&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				dpmac9: dpmac@9 {</div><div class='add'>+				dpmac9: ethernet@9 {</div><div class='ctx'> 					compatible = "fsl,qoriq-mc-dpmac";</div><div class='ctx'> 					reg = &lt;0x9&gt;;</div><div class='add'>+					pcs-handle = &lt;&amp;pcs9&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				dpmac10: dpmac@a {</div><div class='add'>+				dpmac10: ethernet@a {</div><div class='ctx'> 					compatible = "fsl,qoriq-mc-dpmac";</div><div class='ctx'> 					reg = &lt;0xa&gt;;</div><div class='add'>+					pcs-handle = &lt;&amp;pcs10&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				dpmac11: dpmac@b {</div><div class='add'>+				dpmac11: ethernet@b {</div><div class='ctx'> 					compatible = "fsl,qoriq-mc-dpmac";</div><div class='ctx'> 					reg = &lt;0xb&gt;;</div><div class='add'>+					pcs-handle = &lt;&amp;pcs11&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				dpmac12: dpmac@c {</div><div class='add'>+				dpmac12: ethernet@c {</div><div class='ctx'> 					compatible = "fsl,qoriq-mc-dpmac";</div><div class='ctx'> 					reg = &lt;0xc&gt;;</div><div class='add'>+					pcs-handle = &lt;&amp;pcs12&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				dpmac13: dpmac@d {</div><div class='add'>+				dpmac13: ethernet@d {</div><div class='ctx'> 					compatible = "fsl,qoriq-mc-dpmac";</div><div class='ctx'> 					reg = &lt;0xd&gt;;</div><div class='add'>+					pcs-handle = &lt;&amp;pcs13&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				dpmac14: dpmac@e {</div><div class='add'>+				dpmac14: ethernet@e {</div><div class='ctx'> 					compatible = "fsl,qoriq-mc-dpmac";</div><div class='ctx'> 					reg = &lt;0xe&gt;;</div><div class='add'>+					pcs-handle = &lt;&amp;pcs14&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				dpmac15: dpmac@f {</div><div class='add'>+				dpmac15: ethernet@f {</div><div class='ctx'> 					compatible = "fsl,qoriq-mc-dpmac";</div><div class='ctx'> 					reg = &lt;0xf&gt;;</div><div class='add'>+					pcs-handle = &lt;&amp;pcs15&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				dpmac16: dpmac@10 {</div><div class='add'>+				dpmac16: ethernet@10 {</div><div class='ctx'> 					compatible = "fsl,qoriq-mc-dpmac";</div><div class='ctx'> 					reg = &lt;0x10&gt;;</div><div class='add'>+					pcs-handle = &lt;&amp;pcs16&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='hunk'>@@ -447,48 +883,48 @@</div><div class='ctx'> 			#iommu-cells = &lt;1&gt;;</div><div class='ctx'> 			stream-match-mask = &lt;0x7C00&gt;;</div><div class='ctx'> 			dma-coherent;</div><div class='del'>-			interrupts = &lt;0 13 4&gt;, /* global secure fault */</div><div class='del'>-				     &lt;0 14 4&gt;, /* combined secure interrupt */</div><div class='del'>-				     &lt;0 15 4&gt;, /* global non-secure fault */</div><div class='del'>-				     &lt;0 16 4&gt;, /* combined non-secure interrupt */</div><div class='add'>+			interrupts = &lt;GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH&gt;, /* global secure fault */</div><div class='add'>+				     &lt;GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH&gt;, /* combined secure interrupt */</div><div class='add'>+				     &lt;GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH&gt;, /* global non-secure fault */</div><div class='add'>+				     &lt;GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH&gt;, /* combined non-secure interrupt */</div><div class='ctx'> 				/* performance counter interrupts 0-7 */</div><div class='del'>-				     &lt;0 211 4&gt;, &lt;0 212 4&gt;,</div><div class='del'>-				     &lt;0 213 4&gt;, &lt;0 214 4&gt;,</div><div class='del'>-				     &lt;0 215 4&gt;, &lt;0 216 4&gt;,</div><div class='del'>-				     &lt;0 217 4&gt;, &lt;0 218 4&gt;,</div><div class='add'>+				     &lt;GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH&gt;, &lt;GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH&gt;, &lt;GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH&gt;, &lt;GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH&gt;, &lt;GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 				/* per context interrupt, 64 interrupts */</div><div class='del'>-				     &lt;0 146 4&gt;, &lt;0 147 4&gt;,</div><div class='del'>-				     &lt;0 148 4&gt;, &lt;0 149 4&gt;,</div><div class='del'>-				     &lt;0 150 4&gt;, &lt;0 151 4&gt;,</div><div class='del'>-				     &lt;0 152 4&gt;, &lt;0 153 4&gt;,</div><div class='del'>-				     &lt;0 154 4&gt;, &lt;0 155 4&gt;,</div><div class='del'>-				     &lt;0 156 4&gt;, &lt;0 157 4&gt;,</div><div class='del'>-				     &lt;0 158 4&gt;, &lt;0 159 4&gt;,</div><div class='del'>-				     &lt;0 160 4&gt;, &lt;0 161 4&gt;,</div><div class='del'>-				     &lt;0 162 4&gt;, &lt;0 163 4&gt;,</div><div class='del'>-				     &lt;0 164 4&gt;, &lt;0 165 4&gt;,</div><div class='del'>-				     &lt;0 166 4&gt;, &lt;0 167 4&gt;,</div><div class='del'>-				     &lt;0 168 4&gt;, &lt;0 169 4&gt;,</div><div class='del'>-				     &lt;0 170 4&gt;, &lt;0 171 4&gt;,</div><div class='del'>-				     &lt;0 172 4&gt;, &lt;0 173 4&gt;,</div><div class='del'>-				     &lt;0 174 4&gt;, &lt;0 175 4&gt;,</div><div class='del'>-				     &lt;0 176 4&gt;, &lt;0 177 4&gt;,</div><div class='del'>-				     &lt;0 178 4&gt;, &lt;0 179 4&gt;,</div><div class='del'>-				     &lt;0 180 4&gt;, &lt;0 181 4&gt;,</div><div class='del'>-				     &lt;0 182 4&gt;, &lt;0 183 4&gt;,</div><div class='del'>-				     &lt;0 184 4&gt;, &lt;0 185 4&gt;,</div><div class='del'>-				     &lt;0 186 4&gt;, &lt;0 187 4&gt;,</div><div class='del'>-				     &lt;0 188 4&gt;, &lt;0 189 4&gt;,</div><div class='del'>-				     &lt;0 190 4&gt;, &lt;0 191 4&gt;,</div><div class='del'>-				     &lt;0 192 4&gt;, &lt;0 193 4&gt;,</div><div class='del'>-				     &lt;0 194 4&gt;, &lt;0 195 4&gt;,</div><div class='del'>-				     &lt;0 196 4&gt;, &lt;0 197 4&gt;,</div><div class='del'>-				     &lt;0 198 4&gt;, &lt;0 199 4&gt;,</div><div class='del'>-				     &lt;0 200 4&gt;, &lt;0 201 4&gt;,</div><div class='del'>-				     &lt;0 202 4&gt;, &lt;0 203 4&gt;,</div><div class='del'>-				     &lt;0 204 4&gt;, &lt;0 205 4&gt;,</div><div class='del'>-				     &lt;0 206 4&gt;, &lt;0 207 4&gt;,</div><div class='del'>-				     &lt;0 208 4&gt;, &lt;0 209 4&gt;;</div><div class='add'>+				     &lt;GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH&gt;, &lt;GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH&gt;, &lt;GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH&gt;, &lt;GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH&gt;, &lt;GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH&gt;, &lt;GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH&gt;, &lt;GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH&gt;, &lt;GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH&gt;, &lt;GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH&gt;, &lt;GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH&gt;, &lt;GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH&gt;, &lt;GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH&gt;, &lt;GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;, &lt;GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH&gt;, &lt;GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH&gt;, &lt;GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH&gt;, &lt;GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH&gt;, &lt;GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH&gt;, &lt;GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH&gt;, &lt;GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH&gt;, &lt;GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH&gt;, &lt;GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH&gt;, &lt;GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH&gt;, &lt;GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH&gt;, &lt;GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH&gt;, &lt;GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH&gt;, &lt;GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH&gt;, &lt;GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH&gt;, &lt;GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH&gt;, &lt;GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH&gt;, &lt;GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH&gt;, &lt;GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH&gt;, &lt;GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		dspi: spi@2100000 {</div><div class='hunk'>@@ -497,19 +933,20 @@</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			reg = &lt;0x0 0x2100000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 26 0x4&gt;; /* Level high type */</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='ctx'> 			clock-names = "dspi";</div><div class='ctx'> 			spi-num-chipselects = &lt;5&gt;;</div><div class='del'>-			bus-num = &lt;0&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		esdhc: esdhc@2140000 {</div><div class='add'>+		esdhc: mmc@2140000 {</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 			compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";</div><div class='ctx'> 			reg = &lt;0x0 0x2140000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 28 0x4&gt;; /* Level high type */</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='ctx'> 			voltage-ranges = &lt;1800 1800 3300 3300&gt;;</div><div class='ctx'> 			sdhci,auto-cmd12;</div><div class='ctx'> 			little-endian;</div><div class='hunk'>@@ -519,7 +956,7 @@</div><div class='ctx'> 		gpio0: gpio@2300000 {</div><div class='ctx'> 			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";</div><div class='ctx'> 			reg = &lt;0x0 0x2300000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 36 0x4&gt;; /* Level high type */</div><div class='add'>+			interrupts = &lt;GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			gpio-controller;</div><div class='ctx'> 			little-endian;</div><div class='ctx'> 			#gpio-cells = &lt;2&gt;;</div><div class='hunk'>@@ -530,7 +967,7 @@</div><div class='ctx'> 		gpio1: gpio@2310000 {</div><div class='ctx'> 			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";</div><div class='ctx'> 			reg = &lt;0x0 0x2310000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 36 0x4&gt;; /* Level high type */</div><div class='add'>+			interrupts = &lt;GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			gpio-controller;</div><div class='ctx'> 			little-endian;</div><div class='ctx'> 			#gpio-cells = &lt;2&gt;;</div><div class='hunk'>@@ -541,7 +978,7 @@</div><div class='ctx'> 		gpio2: gpio@2320000 {</div><div class='ctx'> 			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";</div><div class='ctx'> 			reg = &lt;0x0 0x2320000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 37 0x4&gt;; /* Level high type */</div><div class='add'>+			interrupts = &lt;GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			gpio-controller;</div><div class='ctx'> 			little-endian;</div><div class='ctx'> 			#gpio-cells = &lt;2&gt;;</div><div class='hunk'>@@ -552,7 +989,7 @@</div><div class='ctx'> 		gpio3: gpio@2330000 {</div><div class='ctx'> 			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";</div><div class='ctx'> 			reg = &lt;0x0 0x2330000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 37 0x4&gt;; /* Level high type */</div><div class='add'>+			interrupts = &lt;GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			gpio-controller;</div><div class='ctx'> 			little-endian;</div><div class='ctx'> 			#gpio-cells = &lt;2&gt;;</div><div class='hunk'>@@ -566,9 +1003,10 @@</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			reg = &lt;0x0 0x2000000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 34 0x4&gt;; /* Level high type */</div><div class='del'>-			clock-names = "i2c";</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clock-names = "ipg";</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		i2c1: i2c@2010000 {</div><div class='hunk'>@@ -577,9 +1015,10 @@</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			reg = &lt;0x0 0x2010000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 34 0x4&gt;; /* Level high type */</div><div class='del'>-			clock-names = "i2c";</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clock-names = "ipg";</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		i2c2: i2c@2020000 {</div><div class='hunk'>@@ -588,9 +1027,10 @@</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			reg = &lt;0x0 0x2020000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 35 0x4&gt;; /* Level high type */</div><div class='del'>-			clock-names = "i2c";</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clock-names = "ipg";</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		i2c3: i2c@2030000 {</div><div class='hunk'>@@ -599,15 +1039,16 @@</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			reg = &lt;0x0 0x2030000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 35 0x4&gt;; /* Level high type */</div><div class='del'>-			clock-names = "i2c";</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clock-names = "ipg";</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		ifc: ifc@2240000 {</div><div class='del'>-			compatible = "fsl,ifc", "simple-bus";</div><div class='add'>+		ifc: memory-controller@2240000 {</div><div class='add'>+			compatible = "fsl,ifc";</div><div class='ctx'> 			reg = &lt;0x0 0x2240000 0x0 0x20000&gt;;</div><div class='del'>-			interrupts = &lt;0 21 0x4&gt;; /* Level high type */</div><div class='add'>+			interrupts = &lt;GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			little-endian;</div><div class='ctx'> 			#address-cells = &lt;2&gt;;</div><div class='ctx'> 			#size-cells = &lt;1&gt;;</div><div class='hunk'>@@ -625,15 +1066,18 @@</div><div class='ctx'> 			      &lt;0x0 0x20000000 0x0 0x10000000&gt;;</div><div class='ctx'> 			reg-names = "QuadSPI", "QuadSPI-memory";</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;, &lt;&amp;clockgen 4 3&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='ctx'> 			clock-names = "qspi_en", "qspi";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		pcie1: pcie@3400000 {</div><div class='del'>-			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";</div><div class='add'>+			compatible = "fsl,ls2080a-pcie";</div><div class='ctx'> 			reg-names = "regs", "config";</div><div class='del'>-			interrupts = &lt;0 108 0x4&gt;; /* Level high type */</div><div class='add'>+			interrupts = &lt;GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			interrupt-names = "intr";</div><div class='ctx'> 			#address-cells = &lt;3&gt;;</div><div class='ctx'> 			#size-cells = &lt;2&gt;;</div><div class='hunk'>@@ -641,7 +1085,7 @@</div><div class='ctx'> 			dma-coherent;</div><div class='ctx'> 			num-viewport = &lt;6&gt;;</div><div class='ctx'> 			bus-range = &lt;0x0 0xff&gt;;</div><div class='del'>-			msi-parent = &lt;&amp;its&gt;;</div><div class='add'>+			msi-parent = &lt;&amp;its 0&gt;;</div><div class='ctx'> 			#interrupt-cells = &lt;1&gt;;</div><div class='ctx'> 			interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='ctx'> 			interrupt-map = &lt;0000 0 0 1 &amp;gic 0 0 0 109 4&gt;,</div><div class='hunk'>@@ -653,9 +1097,9 @@</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		pcie2: pcie@3500000 {</div><div class='del'>-			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";</div><div class='add'>+			compatible = "fsl,ls2080a-pcie";</div><div class='ctx'> 			reg-names = "regs", "config";</div><div class='del'>-			interrupts = &lt;0 113 0x4&gt;; /* Level high type */</div><div class='add'>+			interrupts = &lt;GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			interrupt-names = "intr";</div><div class='ctx'> 			#address-cells = &lt;3&gt;;</div><div class='ctx'> 			#size-cells = &lt;2&gt;;</div><div class='hunk'>@@ -663,7 +1107,7 @@</div><div class='ctx'> 			dma-coherent;</div><div class='ctx'> 			num-viewport = &lt;6&gt;;</div><div class='ctx'> 			bus-range = &lt;0x0 0xff&gt;;</div><div class='del'>-			msi-parent = &lt;&amp;its&gt;;</div><div class='add'>+			msi-parent = &lt;&amp;its 0&gt;;</div><div class='ctx'> 			#interrupt-cells = &lt;1&gt;;</div><div class='ctx'> 			interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='ctx'> 			interrupt-map = &lt;0000 0 0 1 &amp;gic 0 0 0 114 4&gt;,</div><div class='hunk'>@@ -675,9 +1119,9 @@</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		pcie3: pcie@3600000 {</div><div class='del'>-			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";</div><div class='add'>+			compatible = "fsl,ls2080a-pcie";</div><div class='ctx'> 			reg-names = "regs", "config";</div><div class='del'>-			interrupts = &lt;0 118 0x4&gt;; /* Level high type */</div><div class='add'>+			interrupts = &lt;GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			interrupt-names = "intr";</div><div class='ctx'> 			#address-cells = &lt;3&gt;;</div><div class='ctx'> 			#size-cells = &lt;2&gt;;</div><div class='hunk'>@@ -685,7 +1129,7 @@</div><div class='ctx'> 			dma-coherent;</div><div class='ctx'> 			num-viewport = &lt;256&gt;;</div><div class='ctx'> 			bus-range = &lt;0x0 0xff&gt;;</div><div class='del'>-			msi-parent = &lt;&amp;its&gt;;</div><div class='add'>+			msi-parent = &lt;&amp;its 0&gt;;</div><div class='ctx'> 			#interrupt-cells = &lt;1&gt;;</div><div class='ctx'> 			interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='ctx'> 			interrupt-map = &lt;0000 0 0 1 &amp;gic 0 0 0 119 4&gt;,</div><div class='hunk'>@@ -697,9 +1141,9 @@</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		pcie4: pcie@3700000 {</div><div class='del'>-			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";</div><div class='add'>+			compatible = "fsl,ls2080a-pcie";</div><div class='ctx'> 			reg-names = "regs", "config";</div><div class='del'>-			interrupts = &lt;0 123 0x4&gt;; /* Level high type */</div><div class='add'>+			interrupts = &lt;GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			interrupt-names = "intr";</div><div class='ctx'> 			#address-cells = &lt;3&gt;;</div><div class='ctx'> 			#size-cells = &lt;2&gt;;</div><div class='hunk'>@@ -707,7 +1151,7 @@</div><div class='ctx'> 			dma-coherent;</div><div class='ctx'> 			num-viewport = &lt;6&gt;;</div><div class='ctx'> 			bus-range = &lt;0x0 0xff&gt;;</div><div class='del'>-			msi-parent = &lt;&amp;its&gt;;</div><div class='add'>+			msi-parent = &lt;&amp;its 0&gt;;</div><div class='ctx'> 			#interrupt-cells = &lt;1&gt;;</div><div class='ctx'> 			interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='ctx'> 			interrupt-map = &lt;0000 0 0 1 &amp;gic 0 0 0 124 4&gt;,</div><div class='hunk'>@@ -722,8 +1166,9 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 			compatible = "fsl,ls2080a-ahci";</div><div class='ctx'> 			reg = &lt;0x0 0x3200000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 133 0x4&gt;; /* Level high type */</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='ctx'> 			dma-coherent;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -731,51 +1176,74 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 			compatible = "fsl,ls2080a-ahci";</div><div class='ctx'> 			reg = &lt;0x0 0x3210000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 136 0x4&gt;; /* Level high type */</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='ctx'> 			dma-coherent;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		usb0: usb3@3100000 {</div><div class='del'>-			status = "disabled";</div><div class='del'>-			compatible = "snps,dwc3";</div><div class='del'>-			reg = &lt;0x0 0x3100000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 80 0x4&gt;; /* Level high type */</div><div class='del'>-			dr_mode = "host";</div><div class='del'>-			snps,quirk-frame-length-adjustment = &lt;0x20&gt;;</div><div class='del'>-			snps,dis_rxdet_inp3_quirk;</div><div class='del'>-			snps,incr-burst-type-adjustment = &lt;1&gt;, &lt;4&gt;, &lt;8&gt;, &lt;16&gt;;</div><div class='del'>-		};</div><div class='add'>+		bus: bus {</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			compatible = "simple-bus";</div><div class='add'>+			ranges;</div><div class='add'>+			dma-ranges = &lt;0x0 0x0 0x0 0x0 0x100 0x00000000&gt;;</div><div class='add'>+</div><div class='add'>+			usb0: usb@3100000 {</div><div class='add'>+				compatible = "snps,dwc3";</div><div class='add'>+				reg = &lt;0x0 0x3100000 0x0 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				dr_mode = "host";</div><div class='add'>+				snps,quirk-frame-length-adjustment = &lt;0x20&gt;;</div><div class='add'>+				snps,dis_rxdet_inp3_quirk;</div><div class='add'>+				snps,incr-burst-type-adjustment = &lt;1&gt;, &lt;4&gt;, &lt;8&gt;, &lt;16&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='ctx'> </div><div class='del'>-		usb1: usb3@3110000 {</div><div class='del'>-			status = "disabled";</div><div class='del'>-			compatible = "snps,dwc3";</div><div class='del'>-			reg = &lt;0x0 0x3110000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 81 0x4&gt;; /* Level high type */</div><div class='del'>-			dr_mode = "host";</div><div class='del'>-			snps,quirk-frame-length-adjustment = &lt;0x20&gt;;</div><div class='del'>-			snps,dis_rxdet_inp3_quirk;</div><div class='del'>-			snps,incr-burst-type-adjustment = &lt;1&gt;, &lt;4&gt;, &lt;8&gt;, &lt;16&gt;;</div><div class='add'>+			usb1: usb@3110000 {</div><div class='add'>+				compatible = "snps,dwc3";</div><div class='add'>+				reg = &lt;0x0 0x3110000 0x0 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				dr_mode = "host";</div><div class='add'>+				snps,quirk-frame-length-adjustment = &lt;0x20&gt;;</div><div class='add'>+				snps,dis_rxdet_inp3_quirk;</div><div class='add'>+				snps,incr-burst-type-adjustment = &lt;1&gt;, &lt;4&gt;, &lt;8&gt;, &lt;16&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		ccn@4000000 {</div><div class='ctx'> 			compatible = "arm,ccn-504";</div><div class='ctx'> 			reg = &lt;0x0 0x04000000 0x0 0x01000000&gt;;</div><div class='del'>-			interrupts = &lt;0 12 4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rcpm: wakeup-controller@1e34040 {</div><div class='add'>+			compatible = "fsl,ls208xa-rcpm", "fsl,qoriq-rcpm-2.1+";</div><div class='add'>+			reg = &lt;0x0 0x1e34040 0x0 0x18&gt;;</div><div class='add'>+			#fsl,rcpm-wakeup-cells = &lt;6&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ftm_alarm0: rtc@2800000 {</div><div class='add'>+			compatible = "fsl,ls208xa-ftm-alarm";</div><div class='add'>+			reg = &lt;0x0 0x2800000 0x0 0x10000&gt;;</div><div class='add'>+			fsl,rcpm-wakeup = &lt;&amp;rcpm 0x0 0x0 0x0 0x0 0x4000 0x0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	ddr1: memory-controller@1080000 {</div><div class='ctx'> 		compatible = "fsl,qoriq-memory-controller";</div><div class='ctx'> 		reg = &lt;0x0 0x1080000 0x0 0x1000&gt;;</div><div class='del'>-		interrupts = &lt;0 17 0x4&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		little-endian;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	ddr2: memory-controller@1090000 {</div><div class='ctx'> 		compatible = "fsl,qoriq-memory-controller";</div><div class='ctx'> 		reg = &lt;0x0 0x1090000 0x0 0x1000&gt;;</div><div class='del'>-		interrupts = &lt;0 18 0x4&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		little-endian;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3-rev-a.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3-rev-a.dts<br/>new file mode 100644<br/>index 000000000000..15d273c93154<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3-rev-a.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3-rev-a.dts</a></div><div class='hunk'>@@ -0,0 +1,34 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+//</div><div class='add'>+// Device Tree file for LX2160A BLUEBOX3</div><div class='add'>+//</div><div class='add'>+// Copyright 2020-2021 NXP</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "fsl-lx2160a-bluebox3.dts"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "fsl,lx2160a-bluebox3-rev-a", "fsl,lx2160a";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* The RGMII PHYs have a different MDIO address */</div><div class='add'>+&amp;emdio1 {</div><div class='add'>+	/delete-node/ ethernet-phy@5;</div><div class='add'>+</div><div class='add'>+	sw1_mii3_phy: ethernet-phy@1 {</div><div class='add'>+		/* AR8035 */</div><div class='add'>+		compatible = "ethernet-phy-id004d.d072";</div><div class='add'>+		reg = &lt;0x1&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;extirq 6 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/delete-node/ ethernet-phy@6;</div><div class='add'>+</div><div class='add'>+	sw2_mii3_phy: ethernet-phy@2 {</div><div class='add'>+		/* AR8035 */</div><div class='add'>+		compatible = "ethernet-phy-id004d.d072";</div><div class='add'>+		reg = &lt;0x2&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;extirq 7 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3.dts<br/>new file mode 100644<br/>index 000000000000..042c486bdda2<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3.dts</a></div><div class='hunk'>@@ -0,0 +1,662 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+//</div><div class='add'>+// Device Tree file for LX2160A BLUEBOX3</div><div class='add'>+//</div><div class='add'>+// Copyright 2020-2021 NXP</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "fsl-lx2160a.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "NXP Layerscape LX2160ABLUEBOX3";</div><div class='add'>+	compatible = "fsl,lx2160a-bluebox3", "fsl,lx2160a";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		crypto = &amp;crypto;</div><div class='add'>+		mmc0 = &amp;esdhc0;</div><div class='add'>+		mmc1 = &amp;esdhc1;</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sb_3v3: regulator-sb3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "MC34717-3.3VSB";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;can0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	can-transceiver {</div><div class='add'>+		max-bitrate = &lt;5000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;can1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	can-transceiver {</div><div class='add'>+		max-bitrate = &lt;5000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;crypto {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac5 {</div><div class='add'>+	phy-handle = &lt;&amp;aqr113c_phy1&gt;;</div><div class='add'>+	phy-mode = "usxgmii";</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac6 {</div><div class='add'>+	phy-handle = &lt;&amp;aqr113c_phy2&gt;;</div><div class='add'>+	phy-mode = "usxgmii";</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac9 {</div><div class='add'>+	phy-handle = &lt;&amp;aqr113c_phy3&gt;;</div><div class='add'>+	phy-mode = "usxgmii";</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac10 {</div><div class='add'>+	phy-handle = &lt;&amp;aqr113c_phy4&gt;;</div><div class='add'>+	phy-mode = "usxgmii";</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac17 {</div><div class='add'>+	phy-mode = "rgmii";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	fixed-link {</div><div class='add'>+		speed = &lt;1000&gt;;</div><div class='add'>+		full-duplex;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac18 {</div><div class='add'>+	phy-mode = "rgmii";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	fixed-link {</div><div class='add'>+		speed = &lt;1000&gt;;</div><div class='add'>+		full-duplex;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;emdio1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	aqr113c_phy2: ethernet-phy@0 {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+		reg = &lt;0x0&gt;;</div><div class='add'>+		/* IRQ_10G_PHY2 */</div><div class='add'>+		interrupts-extended = &lt;&amp;extirq 3 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aqr113c_phy1: ethernet-phy@8 {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+		reg = &lt;0x8&gt;;</div><div class='add'>+		/* IRQ_10G_PHY1 */</div><div class='add'>+		interrupts-extended = &lt;&amp;extirq 2 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sw1_mii3_phy: ethernet-phy@5 {</div><div class='add'>+		/* AR8035 */</div><div class='add'>+		compatible = "ethernet-phy-id004d.d072";</div><div class='add'>+		reg = &lt;0x5&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;extirq 6 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sw2_mii3_phy: ethernet-phy@6 {</div><div class='add'>+		/* AR8035 */</div><div class='add'>+		compatible = "ethernet-phy-id004d.d072";</div><div class='add'>+		reg = &lt;0x6&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;extirq 7 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;emdio2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	aqr113c_phy4: ethernet-phy@0 {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+		reg = &lt;0x0&gt;;</div><div class='add'>+		/* IRQ_10G_PHY4 */</div><div class='add'>+		interrupts-extended = &lt;&amp;extirq 5 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aqr113c_phy3: ethernet-phy@8 {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+		reg = &lt;0x8&gt;;</div><div class='add'>+		/* IRQ_10G_PHY3 */</div><div class='add'>+		interrupts-extended = &lt;&amp;extirq 4 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;esdhc0 {</div><div class='add'>+	sd-uhs-sdr104;</div><div class='add'>+	sd-uhs-sdr50;</div><div class='add'>+	sd-uhs-sdr25;</div><div class='add'>+	sd-uhs-sdr12;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;esdhc1 {</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	mmc-hs400-1_8v;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fspi {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mt35xu512aba0: flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		m25p,fast-read;</div><div class='add'>+		spi-max-frequency = &lt;50000000&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;8&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;8&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mt35xu512aba1: flash@1 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		m25p,fast-read;</div><div class='add'>+		spi-max-frequency = &lt;50000000&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;8&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;8&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	i2c-mux@77 {</div><div class='add'>+		compatible = "nxp,pca9547";</div><div class='add'>+		reg = &lt;0x77&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		i2c@2 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0x2&gt;;</div><div class='add'>+</div><div class='add'>+			power-monitor@40 {</div><div class='add'>+				compatible = "ti,ina220";</div><div class='add'>+				reg = &lt;0x40&gt;;</div><div class='add'>+				shunt-resistor = &lt;500&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@3 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0x3&gt;;</div><div class='add'>+</div><div class='add'>+			temp2: temperature-sensor@48 {</div><div class='add'>+				compatible = "nxp,sa56004";</div><div class='add'>+				reg = &lt;0x48&gt;;</div><div class='add'>+				vcc-supply = &lt;&amp;sb_3v3&gt;;</div><div class='add'>+				#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			temp1: temperature-sensor@4c {</div><div class='add'>+				compatible = "nxp,sa56004";</div><div class='add'>+				reg = &lt;0x4c&gt;;</div><div class='add'>+				vcc-supply = &lt;&amp;sb_3v3&gt;;</div><div class='add'>+				#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@4 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0x4&gt;;</div><div class='add'>+</div><div class='add'>+			rtc@51 {</div><div class='add'>+				compatible = "nxp,pcf2129";</div><div class='add'>+				reg = &lt;0x51&gt;;</div><div class='add'>+				interrupts-extended = &lt;&amp;extirq 11 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@7 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0x7&gt;;</div><div class='add'>+</div><div class='add'>+			i2c-mux@75 {</div><div class='add'>+				compatible = "nxp,pca9547";</div><div class='add'>+				reg = &lt;0x75&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				i2c@0 {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+					reg = &lt;0x0&gt;;</div><div class='add'>+</div><div class='add'>+					spi_bridge: spi@28 {</div><div class='add'>+						compatible = "nxp,sc18is602b";</div><div class='add'>+						reg = &lt;0x28&gt;;</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c5 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	i2c-mux@77 {</div><div class='add'>+		compatible = "nxp,pca9846";</div><div class='add'>+		reg = &lt;0x77&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		i2c@1 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0x1&gt;;</div><div class='add'>+</div><div class='add'>+			/* The I2C multiplexer and temperature sensors are on</div><div class='add'>+			 * the T6 riser card.</div><div class='add'>+			 */</div><div class='add'>+			i2c-mux@70 {</div><div class='add'>+				compatible = "nxp,pca9548";</div><div class='add'>+				reg = &lt;0x70&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				i2c@6 {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+					reg = &lt;0x6&gt;;</div><div class='add'>+</div><div class='add'>+					q12: temperature-sensor@4c {</div><div class='add'>+						compatible = "nxp,sa56004";</div><div class='add'>+						reg = &lt;0x4c&gt;;</div><div class='add'>+						vcc-supply = &lt;&amp;sb_3v3&gt;;</div><div class='add'>+						#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				i2c@7 {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+					reg = &lt;0x7&gt;;</div><div class='add'>+</div><div class='add'>+					q11: temperature-sensor@4c {</div><div class='add'>+						compatible = "nxp,sa56004";</div><div class='add'>+						reg = &lt;0x4c&gt;;</div><div class='add'>+						vcc-supply = &lt;&amp;sb_3v3&gt;;</div><div class='add'>+						#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					q13: temperature-sensor@48 {</div><div class='add'>+						compatible = "nxp,sa56004";</div><div class='add'>+						reg = &lt;0x48&gt;;</div><div class='add'>+						vcc-supply = &lt;&amp;sb_3v3&gt;;</div><div class='add'>+						#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					q14: temperature-sensor@4a {</div><div class='add'>+						compatible = "nxp,sa56004";</div><div class='add'>+						reg = &lt;0x4a&gt;;</div><div class='add'>+						vcc-supply = &lt;&amp;sb_3v3&gt;;</div><div class='add'>+						#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio5 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio6 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio9 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio10 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi_bridge {</div><div class='add'>+	sw1: ethernet-switch@0 {</div><div class='add'>+		compatible = "nxp,sja1110a";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;4000000&gt;;</div><div class='add'>+		spi-cpol;</div><div class='add'>+		dsa,member = &lt;0 0&gt;;</div><div class='add'>+</div><div class='add'>+		ethernet-ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			/* Microcontroller port */</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* SW1_P1 */</div><div class='add'>+			port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				label = "con_2x20";</div><div class='add'>+				phy-mode = "sgmii";</div><div class='add'>+</div><div class='add'>+				fixed-link {</div><div class='add'>+					speed = &lt;1000&gt;;</div><div class='add'>+					full-duplex;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@2 {</div><div class='add'>+				reg = &lt;2&gt;;</div><div class='add'>+				ethernet = &lt;&amp;dpmac17&gt;;</div><div class='add'>+				phy-mode = "rgmii-id";</div><div class='add'>+				rx-internal-delay-ps = &lt;2000&gt;;</div><div class='add'>+				tx-internal-delay-ps = &lt;2000&gt;;</div><div class='add'>+</div><div class='add'>+				fixed-link {</div><div class='add'>+					speed = &lt;1000&gt;;</div><div class='add'>+					full-duplex;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@3 {</div><div class='add'>+				reg = &lt;3&gt;;</div><div class='add'>+				label = "1ge_p1";</div><div class='add'>+				phy-mode = "rgmii-id";</div><div class='add'>+				phy-handle = &lt;&amp;sw1_mii3_phy&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sw1p4: port@4 {</div><div class='add'>+				reg = &lt;4&gt;;</div><div class='add'>+				link = &lt;&amp;sw2p1&gt;;</div><div class='add'>+				phy-mode = "sgmii";</div><div class='add'>+</div><div class='add'>+				fixed-link {</div><div class='add'>+					speed = &lt;1000&gt;;</div><div class='add'>+					full-duplex;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@5 {</div><div class='add'>+				reg = &lt;5&gt;;</div><div class='add'>+				label = "trx1";</div><div class='add'>+				phy-mode = "internal";</div><div class='add'>+				phy-handle = &lt;&amp;sw1_port5_base_t1_phy&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@6 {</div><div class='add'>+				reg = &lt;6&gt;;</div><div class='add'>+				label = "trx2";</div><div class='add'>+				phy-mode = "internal";</div><div class='add'>+				phy-handle = &lt;&amp;sw1_port6_base_t1_phy&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@7 {</div><div class='add'>+				reg = &lt;7&gt;;</div><div class='add'>+				label = "trx3";</div><div class='add'>+				phy-mode = "internal";</div><div class='add'>+				phy-handle = &lt;&amp;sw1_port7_base_t1_phy&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@8 {</div><div class='add'>+				reg = &lt;8&gt;;</div><div class='add'>+				label = "trx4";</div><div class='add'>+				phy-mode = "internal";</div><div class='add'>+				phy-handle = &lt;&amp;sw1_port8_base_t1_phy&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@9 {</div><div class='add'>+				reg = &lt;9&gt;;</div><div class='add'>+				label = "trx5";</div><div class='add'>+				phy-mode = "internal";</div><div class='add'>+				phy-handle = &lt;&amp;sw1_port9_base_t1_phy&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@a {</div><div class='add'>+				reg = &lt;10&gt;;</div><div class='add'>+				label = "trx6";</div><div class='add'>+				phy-mode = "internal";</div><div class='add'>+				phy-handle = &lt;&amp;sw1_port10_base_t1_phy&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdios {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			mdio@0 {</div><div class='add'>+				compatible = "nxp,sja1110-base-t1-mdio";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				sw1_port5_base_t1_phy: ethernet-phy@1 {</div><div class='add'>+					compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+					reg = &lt;0x1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				sw1_port6_base_t1_phy: ethernet-phy@2 {</div><div class='add'>+					compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+					reg = &lt;0x2&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				sw1_port7_base_t1_phy: ethernet-phy@3 {</div><div class='add'>+					compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+					reg = &lt;0x3&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				sw1_port8_base_t1_phy: ethernet-phy@4 {</div><div class='add'>+					compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+					reg = &lt;0x4&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				sw1_port9_base_t1_phy: ethernet-phy@5 {</div><div class='add'>+					compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+					reg = &lt;0x5&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				sw1_port10_base_t1_phy: ethernet-phy@6 {</div><div class='add'>+					compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+					reg = &lt;0x6&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sw2: ethernet-switch@2 {</div><div class='add'>+		compatible = "nxp,sja1110a";</div><div class='add'>+		reg = &lt;2&gt;;</div><div class='add'>+		spi-max-frequency = &lt;4000000&gt;;</div><div class='add'>+		spi-cpol;</div><div class='add'>+		dsa,member = &lt;0 1&gt;;</div><div class='add'>+</div><div class='add'>+		ethernet-ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			/* Microcontroller port */</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sw2p1: port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				link = &lt;&amp;sw1p4&gt;;</div><div class='add'>+				phy-mode = "sgmii";</div><div class='add'>+</div><div class='add'>+				fixed-link {</div><div class='add'>+					speed = &lt;1000&gt;;</div><div class='add'>+					full-duplex;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@2 {</div><div class='add'>+				reg = &lt;2&gt;;</div><div class='add'>+				ethernet = &lt;&amp;dpmac18&gt;;</div><div class='add'>+				phy-mode = "rgmii-id";</div><div class='add'>+				rx-internal-delay-ps = &lt;2000&gt;;</div><div class='add'>+				tx-internal-delay-ps = &lt;2000&gt;;</div><div class='add'>+</div><div class='add'>+				fixed-link {</div><div class='add'>+					speed = &lt;1000&gt;;</div><div class='add'>+					full-duplex;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@3 {</div><div class='add'>+				reg = &lt;3&gt;;</div><div class='add'>+				label = "1ge_p2";</div><div class='add'>+				phy-mode = "rgmii-id";</div><div class='add'>+				phy-handle = &lt;&amp;sw2_mii3_phy&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@4 {</div><div class='add'>+				reg = &lt;4&gt;;</div><div class='add'>+				label = "to_sw3";</div><div class='add'>+				phy-mode = "2500base-x";</div><div class='add'>+</div><div class='add'>+				fixed-link {</div><div class='add'>+					speed = &lt;2500&gt;;</div><div class='add'>+					full-duplex;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@5 {</div><div class='add'>+				reg = &lt;5&gt;;</div><div class='add'>+				label = "trx7";</div><div class='add'>+				phy-mode = "internal";</div><div class='add'>+				phy-handle = &lt;&amp;sw2_port5_base_t1_phy&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@6 {</div><div class='add'>+				reg = &lt;6&gt;;</div><div class='add'>+				label = "trx8";</div><div class='add'>+				phy-mode = "internal";</div><div class='add'>+				phy-handle = &lt;&amp;sw2_port6_base_t1_phy&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@7 {</div><div class='add'>+				reg = &lt;7&gt;;</div><div class='add'>+				label = "trx9";</div><div class='add'>+				phy-mode = "internal";</div><div class='add'>+				phy-handle = &lt;&amp;sw2_port7_base_t1_phy&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@8 {</div><div class='add'>+				reg = &lt;8&gt;;</div><div class='add'>+				label = "trx10";</div><div class='add'>+				phy-mode = "internal";</div><div class='add'>+				phy-handle = &lt;&amp;sw2_port8_base_t1_phy&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@9 {</div><div class='add'>+				reg = &lt;9&gt;;</div><div class='add'>+				label = "trx11";</div><div class='add'>+				phy-mode = "internal";</div><div class='add'>+				phy-handle = &lt;&amp;sw2_port9_base_t1_phy&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@a {</div><div class='add'>+				reg = &lt;10&gt;;</div><div class='add'>+				label = "trx12";</div><div class='add'>+				phy-mode = "internal";</div><div class='add'>+				phy-handle = &lt;&amp;sw2_port10_base_t1_phy&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdios {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			mdio@0 {</div><div class='add'>+				compatible = "nxp,sja1110-base-t1-mdio";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				sw2_port5_base_t1_phy: ethernet-phy@1 {</div><div class='add'>+					compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+					reg = &lt;0x1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				sw2_port6_base_t1_phy: ethernet-phy@2 {</div><div class='add'>+					compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+					reg = &lt;0x2&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				sw2_port7_base_t1_phy: ethernet-phy@3 {</div><div class='add'>+					compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+					reg = &lt;0x3&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				sw2_port8_base_t1_phy: ethernet-phy@4 {</div><div class='add'>+					compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+					reg = &lt;0x4&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				sw2_port9_base_t1_phy: ethernet-phy@5 {</div><div class='add'>+					compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+					reg = &lt;0x5&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				sw2_port10_base_t1_phy: ethernet-phy@6 {</div><div class='add'>+					compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+					reg = &lt;0x6&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi<br/>index d87d16460875..eec2cd6c6d32 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi</a></div><div class='hunk'>@@ -40,6 +40,8 @@</div><div class='ctx'> </div><div class='ctx'> 	rgmii_phy1: ethernet-phy@1 {</div><div class='ctx'> 		reg = &lt;1&gt;;</div><div class='add'>+		qca,smarteee-tw-us-1g = &lt;24&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;gpio2 4 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -53,7 +55,7 @@</div><div class='ctx'> &amp;i2c0 {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='del'>-	i2c-switch@77 {</div><div class='add'>+	i2c-mux@77 {</div><div class='ctx'> 		compatible = "nxp,pca9547";</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;0&gt;;</div><div class='hunk'>@@ -93,9 +95,6 @@</div><div class='ctx'> 			fan-temperature-ctrlr@18 {</div><div class='ctx'> 				compatible = "ti,amc6821";</div><div class='ctx'> 				reg = &lt;0x18&gt;;</div><div class='del'>-				cooling-min-state = &lt;0&gt;;</div><div class='del'>-				cooling-max-state = &lt;9&gt;;</div><div class='del'>-				#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -121,6 +120,30 @@</div><div class='ctx'> 				vcc-supply = &lt;&amp;sb_3v3&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='add'>+</div><div class='add'>+		sfp0_i2c: i2c@4 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;4&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sfp1_i2c: i2c@5 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;5&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sfp2_i2c: i2c@6 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;6&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sfp3_i2c: i2c@7 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;7&gt;;</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -134,8 +157,7 @@</div><div class='ctx'> 	rtc@51 {</div><div class='ctx'> 		compatible = "nxp,pcf2129";</div><div class='ctx'> 		reg = &lt;0x51&gt;;</div><div class='del'>-		// IRQ10_B</div><div class='del'>-		interrupts = &lt;GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;gpio2 8 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi<br/>index f3741a32e868..af6258b2fe82 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi</a></div><div class='hunk'>@@ -8,6 +8,7 @@</div><div class='ctx'> /dts-v1/;</div><div class='ctx'> </div><div class='ctx'> #include "fsl-lx2160a-cex7.dtsi"</div><div class='add'>+#include &lt;dt-bindings/input/linux-event-codes.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	aliases {</div><div class='hunk'>@@ -18,6 +19,69 @@</div><div class='ctx'> 	chosen {</div><div class='ctx'> 		stdout-path = "serial0:115200n8";</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		key {</div><div class='add'>+			label = "power";</div><div class='add'>+			linux,can-disable;</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio2 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp0: sfp-0 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;sfp0_i2c&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;gpio2 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		maximum-power-milliwatt = &lt;2000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp1: sfp-1 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;sfp1_i2c&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;gpio2 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		maximum-power-milliwatt = &lt;2000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp2: sfp-2 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;sfp2_i2c&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;gpio2 10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		maximum-power-milliwatt = &lt;2000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp3: sfp-3 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;sfp3_i2c&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;gpio2 11 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		maximum-power-milliwatt = &lt;2000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac7 {</div><div class='add'>+	sfp = &lt;&amp;sfp0&gt;;</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	phys = &lt;&amp;serdes_1 3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac8 {</div><div class='add'>+	sfp = &lt;&amp;sfp1&gt;;</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	phys = &lt;&amp;serdes_1 2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac9 {</div><div class='add'>+	sfp = &lt;&amp;sfp2&gt;;</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	phys = &lt;&amp;serdes_1 1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac10 {</div><div class='add'>+	sfp = &lt;&amp;sfp3&gt;;</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	phys = &lt;&amp;serdes_1 0&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;emdio2 {</div><div class='hunk'>@@ -32,6 +96,30 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;pcie3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie5 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio7 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio8 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio9 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio10 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;sata0 {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts<br/>index 3b88e1efe4db..d8ef68ad3bcc 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts</a></div><div class='hunk'>@@ -6,7 +6,7 @@</div><div class='ctx'> </div><div class='ctx'> /dts-v1/;</div><div class='ctx'> </div><div class='del'>-#include "fsl-lx2160a.dtsi"</div><div class='add'>+#include "fsl-lx2160a-rev2.dtsi"</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	model = "NXP Layerscape LX2160AQDS";</div><div class='hunk'>@@ -14,6 +14,8 @@</div><div class='ctx'> </div><div class='ctx'> 	aliases {</div><div class='ctx'> 		crypto = &amp;crypto;</div><div class='add'>+		mmc0 = &amp;esdhc0;</div><div class='add'>+		mmc1 = &amp;esdhc1;</div><div class='ctx'> 		serial0 = &amp;uart0;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -29,12 +31,208 @@</div><div class='ctx'> 		regulator-boot-on;</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	mdio-mux-1 {</div><div class='add'>+		compatible = "mdio-mux-multiplexer";</div><div class='add'>+		mux-controls = &lt;&amp;mux 0&gt;;</div><div class='add'>+		mdio-parent-bus = &lt;&amp;emdio1&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		mdio@0 { /* On-board PHY #1 RGMI1*/</div><div class='add'>+			reg = &lt;0x00&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			rgmii_phy1: ethernet-phy@1 {</div><div class='add'>+				compatible = "ethernet-phy-id001c.c916";</div><div class='add'>+				reg = &lt;0x1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio@8 { /* On-board PHY #2 RGMI2*/</div><div class='add'>+			reg = &lt;0x8&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			rgmii_phy2: ethernet-phy@2 {</div><div class='add'>+				compatible = "ethernet-phy-id001c.c916";</div><div class='add'>+				reg = &lt;0x2&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio@18 { /* Slot #1 */</div><div class='add'>+			reg = &lt;0x18&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio@19 { /* Slot #2 */</div><div class='add'>+			reg = &lt;0x19&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio@1a { /* Slot #3 */</div><div class='add'>+			reg = &lt;0x1a&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio@1b { /* Slot #4 */</div><div class='add'>+			reg = &lt;0x1b&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio@1c { /* Slot #5 */</div><div class='add'>+			reg = &lt;0x1c&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio@1d { /* Slot #6 */</div><div class='add'>+			reg = &lt;0x1d&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio@1e { /* Slot #7 */</div><div class='add'>+			reg = &lt;0x1e&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio@1f { /* Slot #8 */</div><div class='add'>+			reg = &lt;0x1f&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mdio-mux-2 {</div><div class='add'>+		compatible = "mdio-mux-multiplexer";</div><div class='add'>+		mux-controls = &lt;&amp;mux 1&gt;;</div><div class='add'>+		mdio-parent-bus = &lt;&amp;emdio2&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		mdio@0 { /* Slot #1 (secondary EMI) */</div><div class='add'>+			reg = &lt;0x00&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio@1 { /* Slot #2 (secondary EMI) */</div><div class='add'>+			reg = &lt;0x01&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio@2 { /* Slot #3 (secondary EMI) */</div><div class='add'>+			reg = &lt;0x02&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio@3 { /* Slot #4 (secondary EMI) */</div><div class='add'>+			reg = &lt;0x03&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio@4 { /* Slot #5 (secondary EMI) */</div><div class='add'>+			reg = &lt;0x04&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio@5 { /* Slot #6 (secondary EMI) */</div><div class='add'>+			reg = &lt;0x05&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio@6 { /* Slot #7 (secondary EMI) */</div><div class='add'>+			reg = &lt;0x06&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio@7 { /* Slot #8 (secondary EMI) */</div><div class='add'>+			reg = &lt;0x07&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;can0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;can1 {</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;crypto {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;dpmac17 {</div><div class='add'>+	phy-handle = &lt;&amp;rgmii_phy1&gt;;</div><div class='add'>+	phy-connection-type = "rgmii-id";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac18 {</div><div class='add'>+	phy-handle = &lt;&amp;rgmii_phy2&gt;;</div><div class='add'>+	phy-connection-type = "rgmii-id";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dspi0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	dflash0: flash@0 {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;1000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dspi1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	dflash1: flash@0 {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;1000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dspi2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	dflash2: flash@0 {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;1000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;emdio1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;emdio2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;esdhc0 {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='hunk'>@@ -61,6 +259,19 @@</div><div class='ctx'> &amp;i2c0 {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='add'>+	fpga@66 {</div><div class='add'>+		compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c",</div><div class='add'>+			     "simple-mfd";</div><div class='add'>+		reg = &lt;0x66&gt;;</div><div class='add'>+</div><div class='add'>+		mux: mux-controller {</div><div class='add'>+			compatible = "reg-mux";</div><div class='add'>+			#mux-control-cells = &lt;1&gt;;</div><div class='add'>+			mux-reg-masks = &lt;0x54 0xf8&gt;, /* 0: reg 0x54, bits 7:3 */</div><div class='add'>+					&lt;0x54 0x07&gt;; /* 1: reg 0x54, bit 2:0 */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	i2c-mux@77 {</div><div class='ctx'> 		compatible = "nxp,pca9547";</div><div class='ctx'> 		reg = &lt;0x77&gt;;</div><div class='hunk'>@@ -110,6 +321,10 @@</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;optee {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;sata0 {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts<br/>index 22d0308eb13b..935f421475ac 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts</a></div><div class='hunk'>@@ -2,11 +2,11 @@</div><div class='ctx'> //</div><div class='ctx'> // Device Tree file for LX2160ARDB</div><div class='ctx'> //</div><div class='del'>-// Copyright 2018 NXP</div><div class='add'>+// Copyright 2018-2020 NXP</div><div class='ctx'> </div><div class='ctx'> /dts-v1/;</div><div class='ctx'> </div><div class='del'>-#include "fsl-lx2160a.dtsi"</div><div class='add'>+#include "fsl-lx2160a-rev2.dtsi"</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	model = "NXP Layerscape LX2160ARDB";</div><div class='hunk'>@@ -14,6 +14,8 @@</div><div class='ctx'> </div><div class='ctx'> 	aliases {</div><div class='ctx'> 		crypto = &amp;crypto;</div><div class='add'>+		mmc0 = &amp;esdhc0;</div><div class='add'>+		mmc1 = &amp;esdhc1;</div><div class='ctx'> 		serial0 = &amp;uart0;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -29,12 +31,54 @@</div><div class='ctx'> 		regulator-boot-on;</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	sfp2: sfp-2 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;sfp2_i2c&gt;;</div><div class='add'>+		maximum-power-milliwatt = &lt;2000&gt;;</div><div class='add'>+		/* Leave commented out if using DPMAC_LINK_TYPE_FIXED mode */</div><div class='add'>+		/* tx-disable-gpios = &lt;&amp;sfp2_csr 0 GPIO_ACTIVE_HIGH&gt;; */</div><div class='add'>+		los-gpios = &lt;&amp;sfp2_csr 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;sfp2_csr 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;sfp2_csr 7 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp3: sfp-3 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;sfp3_i2c&gt;;</div><div class='add'>+		maximum-power-milliwatt = &lt;2000&gt;;</div><div class='add'>+		/* Leave commented out if using DPMAC_LINK_TYPE_FIXED mode */</div><div class='add'>+		/* tx-disable-gpios = &lt;&amp;sfp3_csr 0 GPIO_ACTIVE_HIGH&gt;; */</div><div class='add'>+		los-gpios = &lt;&amp;sfp3_csr 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;sfp3_csr 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;sfp3_csr 7 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;crypto {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;dpmac3 {</div><div class='add'>+	phy-handle = &lt;&amp;aquantia_phy1&gt;;</div><div class='add'>+	phy-connection-type = "usxgmii";</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac4 {</div><div class='add'>+	phy-handle = &lt;&amp;aquantia_phy2&gt;;</div><div class='add'>+	phy-connection-type = "usxgmii";</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac5 {</div><div class='add'>+	phy-handle = &lt;&amp;inphi_phy&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac6 {</div><div class='add'>+	phy-handle = &lt;&amp;inphi_phy&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;dpmac17 {</div><div class='ctx'> 	phy-handle = &lt;&amp;rgmii_phy1&gt;;</div><div class='ctx'> 	phy-connection-type = "rgmii-id";</div><div class='hunk'>@@ -51,6 +95,7 @@</div><div class='ctx'> 	rgmii_phy1: ethernet-phy@1 {</div><div class='ctx'> 		/* AR8035 PHY */</div><div class='ctx'> 		compatible = "ethernet-phy-id004d.d072";</div><div class='add'>+		interrupts-extended = &lt;&amp;extirq 4 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 		reg = &lt;0x1&gt;;</div><div class='ctx'> 		eee-broken-1000t;</div><div class='ctx'> 	};</div><div class='hunk'>@@ -58,9 +103,49 @@</div><div class='ctx'> 	rgmii_phy2: ethernet-phy@2 {</div><div class='ctx'> 		/* AR8035 PHY */</div><div class='ctx'> 		compatible = "ethernet-phy-id004d.d072";</div><div class='add'>+		interrupts-extended = &lt;&amp;extirq 5 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 		reg = &lt;0x2&gt;;</div><div class='ctx'> 		eee-broken-1000t;</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	aquantia_phy1: ethernet-phy@4 {</div><div class='add'>+		/* AQR107 PHY */</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+		interrupts-extended = &lt;&amp;extirq 2 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		reg = &lt;0x4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aquantia_phy2: ethernet-phy@5 {</div><div class='add'>+		/* AQR107 PHY */</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+		interrupts-extended = &lt;&amp;extirq 3 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		reg = &lt;0x5&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;can0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	can-transceiver {</div><div class='add'>+		max-bitrate = &lt;5000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;can1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	can-transceiver {</div><div class='add'>+		max-bitrate = &lt;5000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;emdio2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	inphi_phy: ethernet-phy@0 {</div><div class='add'>+		compatible = "ethernet-phy-id0210.7440";</div><div class='add'>+		reg = &lt;0x0&gt;;</div><div class='add'>+	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;esdhc0 {</div><div class='hunk'>@@ -107,6 +192,37 @@</div><div class='ctx'> &amp;i2c0 {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='add'>+	cpld@66 {</div><div class='add'>+		compatible = "fsl,lx2160ardb-fpga";</div><div class='add'>+		reg = &lt;0x66&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		sfp2_csr: gpio@19 {</div><div class='add'>+			compatible = "fsl,lx2160ardb-fpga-gpio-sfp";</div><div class='add'>+			reg = &lt;0x19&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-line-names =</div><div class='add'>+				"SFP2_TX_EN", "",</div><div class='add'>+				"", "",</div><div class='add'>+				"SFP2_RX_LOS", "SFP2_TX_FAULT",</div><div class='add'>+				"", "SFP2_MOD_ABS";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sfp3_csr: gpio@1a {</div><div class='add'>+			compatible = "fsl,lx2160ardb-fpga-gpio-sfp";</div><div class='add'>+			reg = &lt;0x1a&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-line-names =</div><div class='add'>+				"SFP3_TX_EN", "",</div><div class='add'>+				"", "",</div><div class='add'>+				"SFP3_RX_LOS", "SFP3_TX_FAULT",</div><div class='add'>+				"", "SFP3_MOD_ABS";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	i2c-mux@77 {</div><div class='ctx'> 		compatible = "nxp,pca9547";</div><div class='ctx'> 		reg = &lt;0x77&gt;;</div><div class='hunk'>@@ -121,7 +237,7 @@</div><div class='ctx'> 			power-monitor@40 {</div><div class='ctx'> 				compatible = "ti,ina220";</div><div class='ctx'> 				reg = &lt;0x40&gt;;</div><div class='del'>-				shunt-resistor = &lt;1000&gt;;</div><div class='add'>+				shunt-resistor = &lt;500&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -142,6 +258,31 @@</div><div class='ctx'> 				vcc-supply = &lt;&amp;sb_3v3&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='add'>+</div><div class='add'>+		i2c@7 {</div><div class='add'>+			reg = &lt;0x7&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			i2c-mux@75 {</div><div class='add'>+				compatible = "nxp,pca9547";</div><div class='add'>+				reg = &lt;0x75&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				sfp2_i2c: i2c@4 {</div><div class='add'>+					reg = &lt;0x4&gt;;</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				sfp3_i2c: i2c@5 {</div><div class='add'>+					reg = &lt;0x5&gt;;</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -151,11 +292,23 @@</div><div class='ctx'> 	rtc@51 {</div><div class='ctx'> 		compatible = "nxp,pcf2129";</div><div class='ctx'> 		reg = &lt;0x51&gt;;</div><div class='del'>-		// IRQ10_B</div><div class='del'>-		interrupts = &lt;0 150 0x4&gt;;</div><div class='add'>+		/* IRQ_RTC_B -&gt; IRQ08, active low */</div><div class='add'>+		interrupts-extended = &lt;&amp;extirq 8 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;optee {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio4 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;sata0 {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi<br/>new file mode 100644<br/>index 000000000000..f54005e37924<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi</a></div><div class='hunk'>@@ -0,0 +1,169 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+//</div><div class='add'>+// Device Tree file for LX2160 REV2</div><div class='add'>+//</div><div class='add'>+// Copyright 2025 NXP</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "fsl-lx2160a.dtsi"</div><div class='add'>+</div><div class='add'>+&amp;pcie1 {</div><div class='add'>+	compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";</div><div class='add'>+	reg = &lt;0x00 0x03400000 0x0 0x00100000   /* controller registers */</div><div class='add'>+	      0x80 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='add'>+	reg-names = "regs", "config";</div><div class='add'>+</div><div class='add'>+	ranges = &lt;0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000</div><div class='add'>+		  0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000&gt;;</div><div class='add'>+</div><div class='add'>+	interrupts = &lt;GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	interrupt-names = "intr";</div><div class='add'>+</div><div class='add'>+	/delete-property/ apio-wins;</div><div class='add'>+	/delete-property/ ppio-wins;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie2 {</div><div class='add'>+	compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";</div><div class='add'>+	reg = &lt;0x00 0x03500000 0x0 0x00100000   /* controller registers */</div><div class='add'>+	       0x88 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='add'>+	reg-names = "regs", "config";</div><div class='add'>+</div><div class='add'>+	ranges = &lt;0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000</div><div class='add'>+		  0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000&gt;;</div><div class='add'>+</div><div class='add'>+	interrupts = &lt;GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	interrupt-names = "intr";</div><div class='add'>+</div><div class='add'>+	/delete-property/ apio-wins;</div><div class='add'>+	/delete-property/ ppio-wins;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie3 {</div><div class='add'>+	compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";</div><div class='add'>+	reg = &lt;0x00 0x03600000 0x0 0x00100000   /* controller registers */</div><div class='add'>+	       0x90 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='add'>+	reg-names = "regs", "config";</div><div class='add'>+</div><div class='add'>+	ranges = &lt;0x81000000 0x0 0x00000000 0x90 0x00010000 0x0 0x00010000</div><div class='add'>+		  0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000&gt;;</div><div class='add'>+</div><div class='add'>+	interrupts = &lt;GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	interrupt-names = "intr";</div><div class='add'>+</div><div class='add'>+	/delete-property/ apio-wins;</div><div class='add'>+	/delete-property/ ppio-wins;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+&amp;pcie4 {</div><div class='add'>+	compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";</div><div class='add'>+	reg = &lt;0x00 0x03700000 0x0 0x00100000   /* controller registers */</div><div class='add'>+	       0x98 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='add'>+	reg-names = "regs", "config";</div><div class='add'>+</div><div class='add'>+	ranges = &lt;0x81000000 0x0 0x00000000 0x98 0x00010000 0x0 0x00010000</div><div class='add'>+		  0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000&gt;;</div><div class='add'>+</div><div class='add'>+	interrupts = &lt;GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	interrupt-names = "intr";</div><div class='add'>+</div><div class='add'>+	/delete-property/ apio-wins;</div><div class='add'>+	/delete-property/ ppio-wins;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie5 {</div><div class='add'>+	compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";</div><div class='add'>+	reg = &lt;0x00 0x03800000 0x0 0x00100000   /* controller registers */</div><div class='add'>+	       0xa0 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='add'>+	reg-names = "regs", "config";</div><div class='add'>+</div><div class='add'>+	ranges = &lt;0x81000000 0x0 0x00000000 0xa0 0x00010000 0x0 0x00010000</div><div class='add'>+		  0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000&gt;;</div><div class='add'>+</div><div class='add'>+	interrupts = &lt;GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	interrupt-names = "intr";</div><div class='add'>+</div><div class='add'>+	/delete-property/ apio-wins;</div><div class='add'>+	/delete-property/ ppio-wins;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie6 {</div><div class='add'>+	compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";</div><div class='add'>+	reg = &lt;0x00 0x03900000 0x0 0x00100000   /* controller registers */</div><div class='add'>+	       0xa8 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='add'>+	reg-names = "regs", "config";</div><div class='add'>+</div><div class='add'>+	ranges = &lt;0x81000000 0x0 0x00000000 0xa8 0x00010000 0x0 0x00010000</div><div class='add'>+		  0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000&gt;;</div><div class='add'>+</div><div class='add'>+	interrupts = &lt;GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	interrupt-names = "intr";</div><div class='add'>+</div><div class='add'>+	/delete-property/ apio-wins;</div><div class='add'>+	/delete-property/ ppio-wins;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;soc {</div><div class='add'>+	pcie_ep1: pcie-ep@3400000 {</div><div class='add'>+		compatible = "fsl,lx2160ar2-pcie-ep";</div><div class='add'>+		reg = &lt;0x00 0x03400000 0x0 0x00100000</div><div class='add'>+		       0x80 0x00000000 0x8 0x00000000&gt;;</div><div class='add'>+		reg-names = "regs", "addr_space";</div><div class='add'>+		num-ob-windows = &lt;8&gt;;</div><div class='add'>+		num-ib-windows = &lt;8&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie_ep2: pcie-ep@3500000 {</div><div class='add'>+		compatible = "fsl,lx2160ar2-pcie-ep";</div><div class='add'>+		reg = &lt;0x00 0x03500000 0x0 0x00100000</div><div class='add'>+		       0x88 0x00000000 0x8 0x00000000&gt;;</div><div class='add'>+		reg-names = "regs", "addr_space";</div><div class='add'>+		num-ob-windows = &lt;8&gt;;</div><div class='add'>+		num-ib-windows = &lt;8&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie_ep3: pcie-ep@3600000 {</div><div class='add'>+		compatible = "fsl,lx2160ar2-pcie-ep";</div><div class='add'>+		reg = &lt;0x00 0x03600000 0x0 0x00100000</div><div class='add'>+		       0x90 0x00000000 0x8 0x00000000&gt;;</div><div class='add'>+		reg-names = "regs", "addr_space";</div><div class='add'>+		num-ob-windows = &lt;256&gt;;</div><div class='add'>+		num-ib-windows = &lt;24&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie_ep4: pcie-ep@3700000 {</div><div class='add'>+		compatible = "fsl,lx2160ar2-pcie-ep";</div><div class='add'>+		reg = &lt;0x00 0x03700000 0x0 0x00100000</div><div class='add'>+		       0x98 0x00000000 0x8 0x00000000&gt;;</div><div class='add'>+		reg-names = "regs", "addr_space";</div><div class='add'>+		num-ob-windows = &lt;8&gt;;</div><div class='add'>+		num-ib-windows = &lt;8&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	pcie_ep5: pcie-ep@3800000 {</div><div class='add'>+		compatible = "fsl,lx2160ar2-pcie-ep";</div><div class='add'>+		reg = &lt;0x00 0x03800000 0x0 0x00100000</div><div class='add'>+		       0xa0 0x00000000 0x8 0x00000000&gt;;</div><div class='add'>+		reg-names = "regs", "addr_space";</div><div class='add'>+		num-ob-windows = &lt;256&gt;;</div><div class='add'>+		num-ib-windows = &lt;24&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie_ep6: pcie-ep@3900000 {</div><div class='add'>+		compatible = "fsl,lx2160ar2-pcie-ep";</div><div class='add'>+		reg = &lt;0x00 0x03900000 0x0 0x00100000</div><div class='add'>+		       0xa8 0x00000000 0x8 0x00000000&gt;;</div><div class='add'>+		reg-names = "regs", "addr_space";</div><div class='add'>+		num-ob-windows = &lt;8&gt;;</div><div class='add'>+		num-ib-windows = &lt;8&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a.dts<br/>new file mode 100644<br/>index 000000000000..f6a4f8d54301<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a.dts</a></div><div class='hunk'>@@ -0,0 +1,338 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2020-2023 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Gregor Herburger</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/net/ti-dp83867.h&gt;</div><div class='add'>+</div><div class='add'>+#include "fsl-lx2160a-tqmlx2160a.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "TQ Systems GmbH MBLX2160A Starterkit";</div><div class='add'>+	compatible = "tq,lx2160a-tqmlx2160a-mblx2160a", "tq,lx2160a-tqmlx2160a",</div><div class='add'>+		     "fsl,lx2160a";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		mmc0 = &amp;esdhc0;</div><div class='add'>+		mmc1 = &amp;esdhc1;</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+		serial1 = &amp;uart1;</div><div class='add'>+		serial2 = &amp;uart2;</div><div class='add'>+		serial3 = &amp;uart3;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		button-user1 {</div><div class='add'>+			label = "button:user1";</div><div class='add'>+			gpios = &lt;&amp;gpio2 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_F1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-user2 {</div><div class='add'>+			label = "button:user2";</div><div class='add'>+			gpios = &lt;&amp;gpio2 10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_F2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-user1 {</div><div class='add'>+			gpios = &lt;&amp;gpioex1 15 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			function = LED_FUNCTION_HEARTBEAT;</div><div class='add'>+			function-enumerator = &lt;0&gt;;</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-user2 {</div><div class='add'>+			gpios = &lt;&amp;gpio2 8 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			function = LED_FUNCTION_HEARTBEAT;</div><div class='add'>+			function-enumerator = &lt;1&gt;;</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp_xfi1: sfp-xfi1 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;xfi1_i2c&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;gpioex2 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;gpioex2 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;gpioex2 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;gpioex2 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp_xfi2: sfp-xfi2 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;xfi2_i2c&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;gpioex2 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;gpioex2 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;gpioex2 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;gpioex2 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;can0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;can1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac17 {</div><div class='add'>+	phy-handle = &lt;&amp;dp83867_2_3&gt;;</div><div class='add'>+	phy-connection-type = "rgmii-id";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac18 {</div><div class='add'>+	phy-handle = &lt;&amp;dp83867_2_4&gt;;</div><div class='add'>+	phy-connection-type = "rgmii-id";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;emdio1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	dp83867_1_1: ethernet-phy@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		ti,clk-output-sel = &lt;DP83867_CLK_O_SEL_OFF&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dp83867_1_2: ethernet-phy@2 {</div><div class='add'>+		reg = &lt;2&gt;;</div><div class='add'>+		ti,clk-output-sel = &lt;DP83867_CLK_O_SEL_OFF&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dp83867_1_3: ethernet-phy@3 {</div><div class='add'>+		reg = &lt;3&gt;;</div><div class='add'>+		ti,clk-output-sel = &lt;DP83867_CLK_O_SEL_OFF&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dp83867_1_4: ethernet-phy@4 {</div><div class='add'>+		reg = &lt;4&gt;;</div><div class='add'>+		ti,clk-output-sel = &lt;DP83867_CLK_O_SEL_OFF&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dp83867_1_5: ethernet-phy@5 {</div><div class='add'>+		reg = &lt;5&gt;;</div><div class='add'>+		ti,clk-output-sel = &lt;DP83867_CLK_O_SEL_OFF&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dp83867_1_6: ethernet-phy@6 {</div><div class='add'>+		reg = &lt;6&gt;;</div><div class='add'>+		ti,clk-output-sel = &lt;DP83867_CLK_O_SEL_OFF&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;emdio2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	dp83867_2_1: ethernet-phy@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		ti,clk-output-sel = &lt;DP83867_CLK_O_SEL_OFF&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dp83867_2_2: ethernet-phy@2 {</div><div class='add'>+		reg = &lt;2&gt;;</div><div class='add'>+		ti,clk-output-sel = &lt;DP83867_CLK_O_SEL_OFF&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dp83867_2_3: ethernet-phy@3 {</div><div class='add'>+		reg = &lt;3&gt;;</div><div class='add'>+		ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_2_25_NS&gt;;</div><div class='add'>+		ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_2_25_NS&gt;;</div><div class='add'>+		ti,clk-output-sel = &lt;DP83867_CLK_O_SEL_OFF&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dp83867_2_4: ethernet-phy@4 {</div><div class='add'>+		reg = &lt;4&gt;;</div><div class='add'>+		ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_2_25_NS&gt;;</div><div class='add'>+		ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_2_25_NS&gt;;</div><div class='add'>+		ti,clk-output-sel = &lt;DP83867_CLK_O_SEL_OFF&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;esdhc0 {</div><div class='add'>+	sd-uhs-sdr104;</div><div class='add'>+	sd-uhs-sdr50;</div><div class='add'>+	sd-uhs-sdr25;</div><div class='add'>+	sd-uhs-sdr12;</div><div class='add'>+	no-mmc;</div><div class='add'>+	no-sdio;</div><div class='add'>+	wp-gpios = &lt;&amp;gpio0 30 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio0 31 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	gpioex3: gpio@20 {</div><div class='add'>+		compatible = "nxp,pca9555";</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_vcc3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mux@70 {</div><div class='add'>+		compatible = "nxp,pca9544";</div><div class='add'>+		reg = &lt;0x70&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;reg_vcc3v3&gt;;</div><div class='add'>+</div><div class='add'>+		i2c@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@2 {</div><div class='add'>+			reg = &lt;2&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			gpioex0: gpio@20 {</div><div class='add'>+				compatible = "nxp,pca9555";</div><div class='add'>+				reg = &lt;0x20&gt;;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+				vcc-supply = &lt;&amp;reg_vcc3v3&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gpioex1: gpio@21 {</div><div class='add'>+				compatible = "nxp,pca9555";</div><div class='add'>+				reg = &lt;0x21&gt;;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+				vcc-supply = &lt;&amp;reg_vcc3v3&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gpioex2: gpio@22 {</div><div class='add'>+				compatible = "nxp,pca9555";</div><div class='add'>+				reg = &lt;0x22&gt;;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+				vcc-supply = &lt;&amp;reg_vcc3v3&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@3 {</div><div class='add'>+			reg = &lt;3&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c5 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mux@70 {</div><div class='add'>+		compatible = "nxp,pca9544";</div><div class='add'>+		reg = &lt;0x70&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;reg_vcc3v3&gt;;</div><div class='add'>+</div><div class='add'>+		i2c@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		xfi1_i2c: i2c@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		xfi2_i2c: i2c@2 {</div><div class='add'>+			reg = &lt;2&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@3 {</div><div class='add'>+			reg = &lt;3&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio17 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio18 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb0 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	hub_2_0: hub@1 {</div><div class='add'>+		compatible = "usb451,8142";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		peer-hub = &lt;&amp;hub_3_0&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpioex1 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;reg_vcc3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hub_3_0: hub@2 {</div><div class='add'>+		compatible = "usb451,8140";</div><div class='add'>+		reg = &lt;2&gt;;</div><div class='add'>+		peer-hub = &lt;&amp;hub_2_0&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpioex1 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;reg_vcc3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb1 {</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_12_x_x.dtso b/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_12_x_x.dtso<br/>new file mode 100644<br/>index 000000000000..8284a564e20d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_12_x_x.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_12_x_x.dtso</a></div><div class='hunk'>@@ -0,0 +1,29 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2020-2023 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Gregor Herburger</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+&amp;dpmac9 {</div><div class='add'>+	phy-handle = &lt;&amp;dp83867_2_1&gt;;</div><div class='add'>+	phy-connection-type = "sgmii";</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac10 {</div><div class='add'>+	phy-handle = &lt;&amp;dp83867_2_2&gt;;</div><div class='add'>+	phy-connection-type = "sgmii";</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio9 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio10 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_14_x_x.dtso b/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_14_x_x.dtso<br/>new file mode 100644<br/>index 000000000000..636b17a383ed<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_14_x_x.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_14_x_x.dtso</a></div><div class='hunk'>@@ -0,0 +1,17 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2020-2023 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Gregor Herburger</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+&amp;dpmac1 {</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_x_11_x.dtso b/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_x_11_x.dtso<br/>new file mode 100644<br/>index 000000000000..6d0c808cd840<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_x_11_x.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_x_11_x.dtso</a></div><div class='hunk'>@@ -0,0 +1,49 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2020-2023 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Gregor Herburger</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+&amp;dpmac12 {</div><div class='add'>+	phy-handle = &lt;&amp;dp83867_1_1&gt;;</div><div class='add'>+	phy-connection-type = "sgmii";</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac13 {</div><div class='add'>+	phy-handle = &lt;&amp;dp83867_1_5&gt;;</div><div class='add'>+	phy-connection-type = "sgmii";</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac14 {</div><div class='add'>+	phy-handle = &lt;&amp;dp83867_1_6&gt;;</div><div class='add'>+	phy-connection-type = "sgmii";</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac16 {</div><div class='add'>+	phy-handle = &lt;&amp;dp83867_1_4&gt;;</div><div class='add'>+	phy-connection-type = "sgmii";</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio12 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio13 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio14 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio16 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_x_7_x.dtso b/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_x_7_x.dtso<br/>new file mode 100644<br/>index 000000000000..db88a86ff69c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_x_7_x.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_x_7_x.dtso</a></div><div class='hunk'>@@ -0,0 +1,55 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2020-2023 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Gregor Herburger</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+&amp;dpmac12 {</div><div class='add'>+	phy-handle = &lt;&amp;dp83867_1_1&gt;;</div><div class='add'>+	phy-connection-type = "sgmii";</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac13 {</div><div class='add'>+	sfp = &lt;&amp;sfp_xfi1&gt;;</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac14 {</div><div class='add'>+	sfp = &lt;&amp;sfp_xfi2&gt;;</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac16 {</div><div class='add'>+	phy-handle = &lt;&amp;dp83867_1_4&gt;;</div><div class='add'>+	phy-connection-type = "sgmii";</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio12 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio13 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio14 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio16 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sfp_xfi1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sfp_xfi2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_x_8_x.dtso b/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_x_8_x.dtso<br/>new file mode 100644<br/>index 000000000000..f6dfa76aa0e7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_x_8_x.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_x_8_x.dtso</a></div><div class='hunk'>@@ -0,0 +1,47 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2020-2023 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Gregor Herburger</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+&amp;dpmac13 {</div><div class='add'>+	sfp = &lt;&amp;sfp_xfi1&gt;;</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac14 {</div><div class='add'>+	sfp = &lt;&amp;sfp_xfi2&gt;;</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio13 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio14 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sata0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sata1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sata2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sfp_xfi1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sfp_xfi2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a.dtsi<br/>new file mode 100644<br/>index 000000000000..89a4765737b4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a.dtsi</a></div><div class='hunk'>@@ -0,0 +1,97 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2020-2023 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Gregor Herburger</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "fsl-lx2160a.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	reg_vcc3v3: regulator-vcc3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCC3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+&amp;emdio1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;emdio2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;esdhc1 {</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	no-sd;</div><div class='add'>+	no-sdio;</div><div class='add'>+	non-removable;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fspi {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash0: flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		spi-max-frequency = &lt;10000000&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;1&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		partitions {</div><div class='add'>+			compatible = "fixed-partitions";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	flash1: flash@1 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		spi-max-frequency = &lt;10000000&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;1&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	scl-gpios = &lt;&amp;gpio2 11 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	sensor0: temperature-sensor@1f {</div><div class='add'>+		compatible = "nxp,se97", "jedec,jc-42.4-temp";</div><div class='add'>+		reg = &lt;0x1f&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom1: eeprom@57 {</div><div class='add'>+		compatible = "atmel,24c02";</div><div class='add'>+		reg = &lt;0x57&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+		read-only;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_vcc3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rtc: rtc@51 {</div><div class='add'>+		compatible = "nxp,pcf85063a";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		quartz-load-femtofarads = &lt;12500&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom2: eeprom@50 {</div><div class='add'>+		compatible = "atmel,24c64";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_vcc3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi<br/>index ae1b113ab162..d899c0355e51 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi</a></div><div class='hunk'>@@ -2,8 +2,9 @@</div><div class='ctx'> //</div><div class='ctx'> // Device Tree Include file for Layerscape-LX2160A family SoC.</div><div class='ctx'> //</div><div class='del'>-// Copyright 2018 NXP</div><div class='add'>+// Copyright 2018-2020 NXP</div><div class='ctx'> </div><div class='add'>+#include &lt;dt-bindings/clock/fsl,qoriq-clockgen.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/thermal/thermal.h&gt;</div><div class='hunk'>@@ -16,6 +17,10 @@</div><div class='ctx'> 	#address-cells = &lt;2&gt;;</div><div class='ctx'> 	#size-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='add'>+	aliases {</div><div class='add'>+		rtc1 = &amp;ftm_alarm0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	cpus {</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;0&gt;;</div><div class='hunk'>@@ -26,7 +31,7 @@</div><div class='ctx'> 			compatible = "arm,cortex-a72";</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			reg = &lt;0x0&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 1 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 0&gt;;</div><div class='ctx'> 			d-cache-size = &lt;0x8000&gt;;</div><div class='ctx'> 			d-cache-line-size = &lt;64&gt;;</div><div class='ctx'> 			d-cache-sets = &lt;128&gt;;</div><div class='hunk'>@@ -43,7 +48,7 @@</div><div class='ctx'> 			compatible = "arm,cortex-a72";</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			reg = &lt;0x1&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 1 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 0&gt;;</div><div class='ctx'> 			d-cache-size = &lt;0x8000&gt;;</div><div class='ctx'> 			d-cache-line-size = &lt;64&gt;;</div><div class='ctx'> 			d-cache-sets = &lt;128&gt;;</div><div class='hunk'>@@ -60,7 +65,7 @@</div><div class='ctx'> 			compatible = "arm,cortex-a72";</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			reg = &lt;0x100&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 1 1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 1&gt;;</div><div class='ctx'> 			d-cache-size = &lt;0x8000&gt;;</div><div class='ctx'> 			d-cache-line-size = &lt;64&gt;;</div><div class='ctx'> 			d-cache-sets = &lt;128&gt;;</div><div class='hunk'>@@ -77,7 +82,7 @@</div><div class='ctx'> 			compatible = "arm,cortex-a72";</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			reg = &lt;0x101&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 1 1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 1&gt;;</div><div class='ctx'> 			d-cache-size = &lt;0x8000&gt;;</div><div class='ctx'> 			d-cache-line-size = &lt;64&gt;;</div><div class='ctx'> 			d-cache-sets = &lt;128&gt;;</div><div class='hunk'>@@ -94,7 +99,7 @@</div><div class='ctx'> 			compatible = "arm,cortex-a72";</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			reg = &lt;0x200&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 1 2&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 2&gt;;</div><div class='ctx'> 			d-cache-size = &lt;0x8000&gt;;</div><div class='ctx'> 			d-cache-line-size = &lt;64&gt;;</div><div class='ctx'> 			d-cache-sets = &lt;128&gt;;</div><div class='hunk'>@@ -111,7 +116,7 @@</div><div class='ctx'> 			compatible = "arm,cortex-a72";</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			reg = &lt;0x201&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 1 2&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 2&gt;;</div><div class='ctx'> 			d-cache-size = &lt;0x8000&gt;;</div><div class='ctx'> 			d-cache-line-size = &lt;64&gt;;</div><div class='ctx'> 			d-cache-sets = &lt;128&gt;;</div><div class='hunk'>@@ -128,7 +133,7 @@</div><div class='ctx'> 			compatible = "arm,cortex-a72";</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			reg = &lt;0x300&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 1 3&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 3&gt;;</div><div class='ctx'> 			d-cache-size = &lt;0x8000&gt;;</div><div class='ctx'> 			d-cache-line-size = &lt;64&gt;;</div><div class='ctx'> 			d-cache-sets = &lt;128&gt;;</div><div class='hunk'>@@ -145,7 +150,7 @@</div><div class='ctx'> 			compatible = "arm,cortex-a72";</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			reg = &lt;0x301&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 1 3&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 3&gt;;</div><div class='ctx'> 			d-cache-size = &lt;0x8000&gt;;</div><div class='ctx'> 			d-cache-line-size = &lt;64&gt;;</div><div class='ctx'> 			d-cache-sets = &lt;128&gt;;</div><div class='hunk'>@@ -162,7 +167,7 @@</div><div class='ctx'> 			compatible = "arm,cortex-a72";</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			reg = &lt;0x400&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 1 4&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 4&gt;;</div><div class='ctx'> 			d-cache-size = &lt;0x8000&gt;;</div><div class='ctx'> 			d-cache-line-size = &lt;64&gt;;</div><div class='ctx'> 			d-cache-sets = &lt;128&gt;;</div><div class='hunk'>@@ -179,7 +184,7 @@</div><div class='ctx'> 			compatible = "arm,cortex-a72";</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			reg = &lt;0x401&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 1 4&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 4&gt;;</div><div class='ctx'> 			d-cache-size = &lt;0x8000&gt;;</div><div class='ctx'> 			d-cache-line-size = &lt;64&gt;;</div><div class='ctx'> 			d-cache-sets = &lt;128&gt;;</div><div class='hunk'>@@ -196,7 +201,7 @@</div><div class='ctx'> 			compatible = "arm,cortex-a72";</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			reg = &lt;0x500&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 1 5&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 5&gt;;</div><div class='ctx'> 			d-cache-size = &lt;0x8000&gt;;</div><div class='ctx'> 			d-cache-line-size = &lt;64&gt;;</div><div class='ctx'> 			d-cache-sets = &lt;128&gt;;</div><div class='hunk'>@@ -213,7 +218,7 @@</div><div class='ctx'> 			compatible = "arm,cortex-a72";</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			reg = &lt;0x501&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 1 5&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 5&gt;;</div><div class='ctx'> 			d-cache-size = &lt;0x8000&gt;;</div><div class='ctx'> 			d-cache-line-size = &lt;64&gt;;</div><div class='ctx'> 			d-cache-sets = &lt;128&gt;;</div><div class='hunk'>@@ -230,7 +235,7 @@</div><div class='ctx'> 			compatible = "arm,cortex-a72";</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			reg = &lt;0x600&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 1 6&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 6&gt;;</div><div class='ctx'> 			d-cache-size = &lt;0x8000&gt;;</div><div class='ctx'> 			d-cache-line-size = &lt;64&gt;;</div><div class='ctx'> 			d-cache-sets = &lt;128&gt;;</div><div class='hunk'>@@ -247,7 +252,7 @@</div><div class='ctx'> 			compatible = "arm,cortex-a72";</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			reg = &lt;0x601&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 1 6&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 6&gt;;</div><div class='ctx'> 			d-cache-size = &lt;0x8000&gt;;</div><div class='ctx'> 			d-cache-line-size = &lt;64&gt;;</div><div class='ctx'> 			d-cache-sets = &lt;128&gt;;</div><div class='hunk'>@@ -264,7 +269,7 @@</div><div class='ctx'> 			compatible = "arm,cortex-a72";</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			reg = &lt;0x700&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 1 7&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 7&gt;;</div><div class='ctx'> 			d-cache-size = &lt;0x8000&gt;;</div><div class='ctx'> 			d-cache-line-size = &lt;64&gt;;</div><div class='ctx'> 			d-cache-sets = &lt;128&gt;;</div><div class='hunk'>@@ -281,7 +286,7 @@</div><div class='ctx'> 			compatible = "arm,cortex-a72";</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			reg = &lt;0x701&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 1 7&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_CMUX 7&gt;;</div><div class='ctx'> 			d-cache-size = &lt;0x8000&gt;;</div><div class='ctx'> 			d-cache-line-size = &lt;64&gt;;</div><div class='ctx'> 			d-cache-sets = &lt;128&gt;;</div><div class='hunk'>@@ -295,6 +300,7 @@</div><div class='ctx'> </div><div class='ctx'> 		cluster0_l2: l2-cache0 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-unified;</div><div class='ctx'> 			cache-size = &lt;0x100000&gt;;</div><div class='ctx'> 			cache-line-size = &lt;64&gt;;</div><div class='ctx'> 			cache-sets = &lt;1024&gt;;</div><div class='hunk'>@@ -303,6 +309,7 @@</div><div class='ctx'> </div><div class='ctx'> 		cluster1_l2: l2-cache1 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-unified;</div><div class='ctx'> 			cache-size = &lt;0x100000&gt;;</div><div class='ctx'> 			cache-line-size = &lt;64&gt;;</div><div class='ctx'> 			cache-sets = &lt;1024&gt;;</div><div class='hunk'>@@ -311,6 +318,7 @@</div><div class='ctx'> </div><div class='ctx'> 		cluster2_l2: l2-cache2 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-unified;</div><div class='ctx'> 			cache-size = &lt;0x100000&gt;;</div><div class='ctx'> 			cache-line-size = &lt;64&gt;;</div><div class='ctx'> 			cache-sets = &lt;1024&gt;;</div><div class='hunk'>@@ -319,6 +327,7 @@</div><div class='ctx'> </div><div class='ctx'> 		cluster3_l2: l2-cache3 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-unified;</div><div class='ctx'> 			cache-size = &lt;0x100000&gt;;</div><div class='ctx'> 			cache-line-size = &lt;64&gt;;</div><div class='ctx'> 			cache-sets = &lt;1024&gt;;</div><div class='hunk'>@@ -327,6 +336,7 @@</div><div class='ctx'> </div><div class='ctx'> 		cluster4_l2: l2-cache4 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-unified;</div><div class='ctx'> 			cache-size = &lt;0x100000&gt;;</div><div class='ctx'> 			cache-line-size = &lt;64&gt;;</div><div class='ctx'> 			cache-sets = &lt;1024&gt;;</div><div class='hunk'>@@ -335,6 +345,7 @@</div><div class='ctx'> </div><div class='ctx'> 		cluster5_l2: l2-cache5 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-unified;</div><div class='ctx'> 			cache-size = &lt;0x100000&gt;;</div><div class='ctx'> 			cache-line-size = &lt;64&gt;;</div><div class='ctx'> 			cache-sets = &lt;1024&gt;;</div><div class='hunk'>@@ -343,6 +354,7 @@</div><div class='ctx'> </div><div class='ctx'> 		cluster6_l2: l2-cache6 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-unified;</div><div class='ctx'> 			cache-size = &lt;0x100000&gt;;</div><div class='ctx'> 			cache-line-size = &lt;64&gt;;</div><div class='ctx'> 			cache-sets = &lt;1024&gt;;</div><div class='hunk'>@@ -351,6 +363,7 @@</div><div class='ctx'> </div><div class='ctx'> 		cluster7_l2: l2-cache7 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-unified;</div><div class='ctx'> 			cache-size = &lt;0x100000&gt;;</div><div class='ctx'> 			cache-line-size = &lt;64&gt;;</div><div class='ctx'> 			cache-sets = &lt;1024&gt;;</div><div class='hunk'>@@ -382,9 +395,10 @@</div><div class='ctx'> 		interrupt-controller;</div><div class='ctx'> 		interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> </div><div class='del'>-		its: gic-its@6020000 {</div><div class='add'>+		its: msi-controller@6020000 {</div><div class='ctx'> 			compatible = "arm,gic-v3-its";</div><div class='ctx'> 			msi-controller;</div><div class='add'>+			#msi-cells = &lt;1&gt;;</div><div class='ctx'> 			reg = &lt;0x0 0x6020000 0 0x20000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='hunk'>@@ -436,19 +450,19 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	thermal-zones {</div><div class='del'>-		core_thermal1: core-thermal1 {</div><div class='add'>+		cluster6-7-thermal {</div><div class='ctx'> 			polling-delay-passive = &lt;1000&gt;;</div><div class='ctx'> 			polling-delay = &lt;5000&gt;;</div><div class='ctx'> 			thermal-sensors = &lt;&amp;tmu 0&gt;;</div><div class='ctx'> </div><div class='ctx'> 			trips {</div><div class='del'>-				core_cluster_alert: core-cluster-alert {</div><div class='add'>+				cluster6_7_alert: cluster6-7-alert {</div><div class='ctx'> 					temperature = &lt;85000&gt;;</div><div class='ctx'> 					hysteresis = &lt;2000&gt;;</div><div class='ctx'> 					type = "passive";</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				core_cluster_crit: core-cluster-crit {</div><div class='add'>+				cluster6_7_crit: cluster6-7-crit {</div><div class='ctx'> 					temperature = &lt;95000&gt;;</div><div class='ctx'> 					hysteresis = &lt;2000&gt;;</div><div class='ctx'> 					type = "critical";</div><div class='hunk'>@@ -457,7 +471,7 @@</div><div class='ctx'> </div><div class='ctx'> 			cooling-maps {</div><div class='ctx'> 				map0 {</div><div class='del'>-					trip = &lt;&amp;core_cluster_alert&gt;;</div><div class='add'>+					trip = &lt;&amp;cluster6_7_alert&gt;;</div><div class='ctx'> 					cooling-device =</div><div class='ctx'> 						&lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='ctx'> 						&lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='hunk'>@@ -478,15 +492,148 @@</div><div class='ctx'> 				};</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='add'>+</div><div class='add'>+		ddr-ctrl5-thermal {</div><div class='add'>+			polling-delay-passive = &lt;1000&gt;;</div><div class='add'>+			polling-delay = &lt;5000&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;tmu 1&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				ddr-cluster5-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				ddr-cluster5-crit {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wriop-thermal {</div><div class='add'>+			polling-delay-passive = &lt;1000&gt;;</div><div class='add'>+			polling-delay = &lt;5000&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;tmu 2&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				wriop-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				wriop-crit {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dce-thermal {</div><div class='add'>+			polling-delay-passive = &lt;1000&gt;;</div><div class='add'>+			polling-delay = &lt;5000&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;tmu 3&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				dce-qbman-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				dce-qbman-crit {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ccn-thermal {</div><div class='add'>+			polling-delay-passive = &lt;1000&gt;;</div><div class='add'>+			polling-delay = &lt;5000&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;tmu 4&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				ccn-dpaa-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				ccn-dpaa-crit {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cluster4-thermal {</div><div class='add'>+			polling-delay-passive = &lt;1000&gt;;</div><div class='add'>+			polling-delay = &lt;5000&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;tmu 5&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				clust4-hsio3-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				clust4-hsio3-crit {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cluster2-3-thermal {</div><div class='add'>+			polling-delay-passive = &lt;1000&gt;;</div><div class='add'>+			polling-delay = &lt;5000&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;tmu 6&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cluster2-3-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cluster2-3-crit {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	soc {</div><div class='add'>+	soc: soc {</div><div class='ctx'> 		compatible = "simple-bus";</div><div class='ctx'> 		#address-cells = &lt;2&gt;;</div><div class='ctx'> 		#size-cells = &lt;2&gt;;</div><div class='ctx'> 		ranges;</div><div class='ctx'> 		dma-ranges = &lt;0x0 0x0 0x0 0x0 0x10000 0x00000000&gt;;</div><div class='ctx'> </div><div class='add'>+		serdes_1: phy@1ea0000 {</div><div class='add'>+			compatible = "fsl,lynx-28g";</div><div class='add'>+			reg = &lt;0x0 0x1ea0000 0x0 0x1e30&gt;;</div><div class='add'>+			#phy-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		serdes_2: phy@1eb0000 {</div><div class='add'>+			compatible = "fsl,lynx-28g";</div><div class='add'>+			reg = &lt;0x0 0x1eb0000 0x0 0x1e30&gt;;</div><div class='add'>+			#phy-cells = &lt;1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		crypto: crypto@8000000 {</div><div class='ctx'> 			compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";</div><div class='ctx'> 			fsl,sec-era = &lt;10&gt;;</div><div class='hunk'>@@ -501,28 +648,28 @@</div><div class='ctx'> 			sec_jr0: jr@10000 {</div><div class='ctx'> 				compatible = "fsl,sec-v5.0-job-ring",</div><div class='ctx'> 					     "fsl,sec-v4.0-job-ring";</div><div class='del'>-				reg        = &lt;0x10000 0x10000&gt;;</div><div class='add'>+				reg = &lt;0x10000 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			sec_jr1: jr@20000 {</div><div class='ctx'> 				compatible = "fsl,sec-v5.0-job-ring",</div><div class='ctx'> 					     "fsl,sec-v4.0-job-ring";</div><div class='del'>-				reg        = &lt;0x20000 0x10000&gt;;</div><div class='add'>+				reg = &lt;0x20000 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			sec_jr2: jr@30000 {</div><div class='ctx'> 				compatible = "fsl,sec-v5.0-job-ring",</div><div class='ctx'> 					     "fsl,sec-v4.0-job-ring";</div><div class='del'>-				reg        = &lt;0x30000 0x10000&gt;;</div><div class='add'>+				reg = &lt;0x30000 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			sec_jr3: jr@40000 {</div><div class='ctx'> 				compatible = "fsl,sec-v5.0-job-ring",</div><div class='ctx'> 					     "fsl,sec-v4.0-job-ring";</div><div class='del'>-				reg        = &lt;0x40000 0x10000&gt;;</div><div class='add'>+				reg = &lt;0x40000 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='hunk'>@@ -540,6 +687,45 @@</div><div class='ctx'> 			little-endian;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		sfp: efuse@1e80000 {</div><div class='add'>+			compatible = "fsl,ls1028a-sfp";</div><div class='add'>+			reg = &lt;0x0 0x1e80000 0x0 0x10000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='add'>+			clock-names = "sfp";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		isc: syscon@1f70000 {</div><div class='add'>+			compatible = "fsl,lx2160a-isc", "syscon";</div><div class='add'>+			reg = &lt;0x0 0x1f70000 0x0 0x10000&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges = &lt;0x0 0x0 0x1f70000 0x10000&gt;;</div><div class='add'>+</div><div class='add'>+			extirq: interrupt-controller@14 {</div><div class='add'>+				compatible = "fsl,lx2160a-extirq", "fsl,ls1088a-extirq";</div><div class='add'>+				#interrupt-cells = &lt;2&gt;;</div><div class='add'>+				#address-cells = &lt;0&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				reg = &lt;0x14 4&gt;;</div><div class='add'>+				interrupt-map =</div><div class='add'>+					&lt;0 0 &amp;gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;1 0 &amp;gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;2 0 &amp;gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;3 0 &amp;gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;4 0 &amp;gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;5 0 &amp;gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;6 0 &amp;gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;7 0 &amp;gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;8 0 &amp;gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;9 0 &amp;gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;10 0 &amp;gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;11 0 &amp;gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				interrupt-map-mask = &lt;0xf 0x0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		tmu: tmu@1f80000 {</div><div class='ctx'> 			compatible = "fsl,qoriq-tmu";</div><div class='ctx'> 			reg = &lt;0x0 0x1f80000 0x0 0x10000&gt;;</div><div class='hunk'>@@ -547,9 +733,9 @@</div><div class='ctx'> 			fsl,tmu-range = &lt;0x800000e6 0x8001017d&gt;;</div><div class='ctx'> 			fsl,tmu-calibration =</div><div class='ctx'> 				/* Calibration data group 1 */</div><div class='del'>-				&lt;0x00000000 0x00000035</div><div class='add'>+				&lt;0x00000000 0x00000035&gt;,</div><div class='ctx'> 				/* Calibration data group 2 */</div><div class='del'>-				0x00010001 0x00000154&gt;;</div><div class='add'>+				&lt;0x00000001 0x00000154&gt;;</div><div class='ctx'> 			little-endian;</div><div class='ctx'> 			#thermal-sensor-cells = &lt;1&gt;;</div><div class='ctx'> 		};</div><div class='hunk'>@@ -560,9 +746,13 @@</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			reg = &lt;0x0 0x2000000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clock-names = "i2c";</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 15&gt;;</div><div class='del'>-			scl-gpio = &lt;&amp;gpio2 15 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			clock-names = "ipg";</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(16)&gt;;</div><div class='add'>+			pinctrl-names = "default", "gpio";</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c0_scl&gt;;</div><div class='add'>+			pinctrl-1 = &lt;&amp;i2c0_scl_gpio&gt;;</div><div class='add'>+			scl-gpios = &lt;&amp;gpio0 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -572,8 +762,13 @@</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			reg = &lt;0x0 0x2010000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clock-names = "i2c";</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 15&gt;;</div><div class='add'>+			clock-names = "ipg";</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(16)&gt;;</div><div class='add'>+			pinctrl-names = "default", "gpio";</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c1_scl&gt;;</div><div class='add'>+			pinctrl-1 = &lt;&amp;i2c1_scl_gpio&gt;;</div><div class='add'>+			scl-gpios = &lt;&amp;gpio0 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -583,8 +778,13 @@</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			reg = &lt;0x0 0x2020000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clock-names = "i2c";</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 15&gt;;</div><div class='add'>+			clock-names = "ipg";</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(16)&gt;;</div><div class='add'>+			pinctrl-names = "default", "gpio";</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c2_scl&gt;;</div><div class='add'>+			pinctrl-1 = &lt;&amp;i2c2_scl_gpio&gt;;</div><div class='add'>+			scl-gpios = &lt;&amp;gpio0 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -594,8 +794,13 @@</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			reg = &lt;0x0 0x2030000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clock-names = "i2c";</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 15&gt;;</div><div class='add'>+			clock-names = "ipg";</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(16)&gt;;</div><div class='add'>+			pinctrl-names = "default", "gpio";</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c3_scl&gt;;</div><div class='add'>+			pinctrl-1 = &lt;&amp;i2c3_scl_gpio&gt;;</div><div class='add'>+			scl-gpios = &lt;&amp;gpio0 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -605,9 +810,13 @@</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			reg = &lt;0x0 0x2040000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clock-names = "i2c";</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 15&gt;;</div><div class='del'>-			scl-gpio = &lt;&amp;gpio2 16 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			clock-names = "ipg";</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(16)&gt;;</div><div class='add'>+			pinctrl-names = "default", "gpio";</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c4_scl&gt;;</div><div class='add'>+			pinctrl-1 = &lt;&amp;i2c4_scl_gpio&gt;;</div><div class='add'>+			scl-gpios = &lt;&amp;gpio0 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -617,8 +826,13 @@</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			reg = &lt;0x0 0x2050000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clock-names = "i2c";</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 15&gt;;</div><div class='add'>+			clock-names = "ipg";</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(16)&gt;;</div><div class='add'>+			pinctrl-names = "default", "gpio";</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c5_scl&gt;;</div><div class='add'>+			pinctrl-1 = &lt;&amp;i2c5_scl_gpio&gt;;</div><div class='add'>+			scl-gpios = &lt;&amp;gpio0 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -628,8 +842,13 @@</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			reg = &lt;0x0 0x2060000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clock-names = "i2c";</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 15&gt;;</div><div class='add'>+			clock-names = "ipg";</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(16)&gt;;</div><div class='add'>+			pinctrl-names = "default", "gpio";</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c6_scl&gt;;</div><div class='add'>+			pinctrl-1 = &lt;&amp;i2c6_scl_gpio&gt;;</div><div class='add'>+			scl-gpios = &lt;&amp;gpio1 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -639,8 +858,13 @@</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			reg = &lt;0x0 0x2070000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clock-names = "i2c";</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 15&gt;;</div><div class='add'>+			clock-names = "ipg";</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(16)&gt;;</div><div class='add'>+			pinctrl-names = "default", "gpio";</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c7_scl&gt;;</div><div class='add'>+			pinctrl-1 = &lt;&amp;i2c7_scl_gpio&gt;;</div><div class='add'>+			scl-gpios = &lt;&amp;gpio1 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -652,16 +876,62 @@</div><div class='ctx'> 			      &lt;0x0 0x20000000 0x0 0x10000000&gt;;</div><div class='ctx'> 			reg-names = "fspi_base", "fspi_mmap";</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;, &lt;&amp;clockgen 4 3&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='ctx'> 			clock-names = "fspi_en", "fspi";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		esdhc0: esdhc@2140000 {</div><div class='del'>-			compatible = "fsl,esdhc";</div><div class='add'>+		dspi0: spi@2100000 {</div><div class='add'>+			compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0x0 0x2100000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(8)&gt;;</div><div class='add'>+			clock-names = "dspi";</div><div class='add'>+			spi-num-chipselects = &lt;5&gt;;</div><div class='add'>+			bus-num = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dspi1: spi@2110000 {</div><div class='add'>+			compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0x0 0x2110000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(8)&gt;;</div><div class='add'>+			clock-names = "dspi";</div><div class='add'>+			spi-num-chipselects = &lt;5&gt;;</div><div class='add'>+			bus-num = &lt;1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dspi2: spi@2120000 {</div><div class='add'>+			compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0x0 0x2120000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(8)&gt;;</div><div class='add'>+			clock-names = "dspi";</div><div class='add'>+			spi-num-chipselects = &lt;5&gt;;</div><div class='add'>+			bus-num = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		esdhc0: mmc@2140000 {</div><div class='add'>+			compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";</div><div class='ctx'> 			reg = &lt;0x0 0x2140000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 28 0x4&gt;; /* Level high type */</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='ctx'> 			dma-coherent;</div><div class='ctx'> 			voltage-ranges = &lt;1800 1800 3300 3300&gt;;</div><div class='ctx'> 			sdhci,auto-cmd12;</div><div class='hunk'>@@ -670,11 +940,12 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		esdhc1: esdhc@2150000 {</div><div class='del'>-			compatible = "fsl,esdhc";</div><div class='add'>+		esdhc1: mmc@2150000 {</div><div class='add'>+			compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";</div><div class='ctx'> 			reg = &lt;0x0 0x2150000 0x0 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;0 63 0x4&gt;; /* Level high type */</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='ctx'> 			dma-coherent;</div><div class='ctx'> 			voltage-ranges = &lt;1800 1800 3300 3300&gt;;</div><div class='ctx'> 			sdhci,auto-cmd12;</div><div class='hunk'>@@ -684,40 +955,80 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		can0: can@2180000 {</div><div class='add'>+			compatible = "fsl,lx2160ar1-flexcan";</div><div class='add'>+			reg = &lt;0x0 0x2180000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(8)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_SYSCLK 0&gt;;</div><div class='add'>+			clock-names = "ipg", "per";</div><div class='add'>+			fsl,clk-source = /bits/ 8 &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		can1: can@2190000 {</div><div class='add'>+			compatible = "fsl,lx2160ar1-flexcan";</div><div class='add'>+			reg = &lt;0x0 0x2190000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(8)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_SYSCLK 0&gt;;</div><div class='add'>+			clock-names = "ipg", "per";</div><div class='add'>+			fsl,clk-source = /bits/ 8 &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		uart0: serial@21c0000 {</div><div class='del'>-			compatible = "arm,sbsa-uart","arm,pl011";</div><div class='add'>+			compatible = "arm,pl011", "arm,primecell";</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(8)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(8)&gt;;</div><div class='add'>+			clock-names = "uartclk", "apb_pclk";</div><div class='ctx'> 			reg = &lt;0x0 0x21c0000 0x0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			current-speed = &lt;115200&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		uart1: serial@21d0000 {</div><div class='del'>-			compatible = "arm,sbsa-uart","arm,pl011";</div><div class='add'>+			compatible = "arm,pl011", "arm,primecell";</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(8)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(8)&gt;;</div><div class='add'>+			clock-names = "uartclk", "apb_pclk";</div><div class='ctx'> 			reg = &lt;0x0 0x21d0000 0x0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			current-speed = &lt;115200&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		uart2: serial@21e0000 {</div><div class='del'>-			compatible = "arm,sbsa-uart","arm,pl011";</div><div class='add'>+			compatible = "arm,pl011", "arm,primecell";</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(8)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(8)&gt;;</div><div class='add'>+			clock-names = "uartclk", "apb_pclk";</div><div class='ctx'> 			reg = &lt;0x0 0x21e0000 0x0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			current-speed = &lt;115200&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		uart3: serial@21f0000 {</div><div class='del'>-			compatible = "arm,sbsa-uart","arm,pl011";</div><div class='add'>+			compatible = "arm,pl011", "arm,primecell";</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(8)&gt;,</div><div class='add'>+				 &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(8)&gt;;</div><div class='add'>+			clock-names = "uartclk", "apb_pclk";</div><div class='ctx'> 			reg = &lt;0x0 0x21f0000 0x0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			current-speed = &lt;115200&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		gpio0: gpio@2300000 {</div><div class='del'>-			compatible = "fsl,qoriq-gpio";</div><div class='add'>+			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";</div><div class='ctx'> 			reg = &lt;0x0 0x2300000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			gpio-controller;</div><div class='hunk'>@@ -728,7 +1039,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		gpio1: gpio@2310000 {</div><div class='del'>-			compatible = "fsl,qoriq-gpio";</div><div class='add'>+			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";</div><div class='ctx'> 			reg = &lt;0x0 0x2310000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			gpio-controller;</div><div class='hunk'>@@ -739,7 +1050,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		gpio2: gpio@2320000 {</div><div class='del'>-			compatible = "fsl,qoriq-gpio";</div><div class='add'>+			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";</div><div class='ctx'> 			reg = &lt;0x0 0x2320000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			gpio-controller;</div><div class='hunk'>@@ -750,7 +1061,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		gpio3: gpio@2330000 {</div><div class='del'>-			compatible = "fsl,qoriq-gpio";</div><div class='add'>+			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";</div><div class='ctx'> 			reg = &lt;0x0 0x2330000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			gpio-controller;</div><div class='hunk'>@@ -768,23 +1079,43 @@</div><div class='ctx'> 			timeout-sec = &lt;30&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		rcpm: wakeup-controller@1e34040 {</div><div class='add'>+			compatible = "fsl,lx2160a-rcpm", "fsl,qoriq-rcpm-2.1+";</div><div class='add'>+			reg = &lt;0x0 0x1e34040 0x0 0x1c&gt;;</div><div class='add'>+			#fsl,rcpm-wakeup-cells = &lt;7&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ftm_alarm0: rtc@2800000 {</div><div class='add'>+			compatible = "fsl,lx2160a-ftm-alarm";</div><div class='add'>+			reg = &lt;0x0 0x2800000 0x0 0x10000&gt;;</div><div class='add'>+			fsl,rcpm-wakeup = &lt;&amp;rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		usb0: usb@3100000 {</div><div class='del'>-			compatible = "snps,dwc3";</div><div class='add'>+			compatible = "fsl,lx2160a-dwc3", "fsl,ls1028a-dwc3";</div><div class='ctx'> 			reg = &lt;0x0 0x3100000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			dr_mode = "host";</div><div class='ctx'> 			snps,quirk-frame-length-adjustment = &lt;0x20&gt;;</div><div class='add'>+			usb3-lpm-capable;</div><div class='add'>+			iommus = &lt;&amp;smmu 1&gt;;</div><div class='add'>+			dma-coherent;</div><div class='ctx'> 			snps,dis_rxdet_inp3_quirk;</div><div class='ctx'> 			snps,incr-burst-type-adjustment = &lt;1&gt;, &lt;4&gt;, &lt;8&gt;, &lt;16&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		usb1: usb@3110000 {</div><div class='del'>-			compatible = "snps,dwc3";</div><div class='add'>+			compatible = "fsl,lx2160a-dwc3", "fsl,ls1028a-dwc3";</div><div class='ctx'> 			reg = &lt;0x0 0x3110000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			dr_mode = "host";</div><div class='ctx'> 			snps,quirk-frame-length-adjustment = &lt;0x20&gt;;</div><div class='add'>+			usb3-lpm-capable;</div><div class='add'>+			iommus = &lt;&amp;smmu 2&gt;;</div><div class='add'>+			dma-coherent;</div><div class='ctx'> 			snps,dis_rxdet_inp3_quirk;</div><div class='ctx'> 			snps,incr-burst-type-adjustment = &lt;1&gt;, &lt;4&gt;, &lt;8&gt;, &lt;16&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='hunk'>@@ -796,7 +1127,8 @@</div><div class='ctx'> 			      &lt;0x7 0x100520 0x0 0x4&gt;;</div><div class='ctx'> 			reg-names = "ahci", "sata-ecc";</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='ctx'> 			dma-coherent;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='hunk'>@@ -807,7 +1139,8 @@</div><div class='ctx'> 			      &lt;0x7 0x100520 0x0 0x4&gt;;</div><div class='ctx'> 			reg-names = "ahci", "sata-ecc";</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='ctx'> 			dma-coherent;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='hunk'>@@ -818,7 +1151,8 @@</div><div class='ctx'> 			      &lt;0x7 0x100520 0x0 0x4&gt;;</div><div class='ctx'> 			reg-names = "ahci", "sata-ecc";</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='ctx'> 			dma-coherent;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='hunk'>@@ -829,15 +1163,16 @@</div><div class='ctx'> 			      &lt;0x7 0x100520 0x0 0x4&gt;;</div><div class='ctx'> 			reg-names = "ahci", "sata-ecc";</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 3&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(4)&gt;;</div><div class='ctx'> 			dma-coherent;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		pcie@3400000 {</div><div class='add'>+		pcie1: pcie@3400000 {</div><div class='ctx'> 			compatible = "fsl,lx2160a-pcie";</div><div class='del'>-			reg = &lt;0x00 0x03400000 0x0 0x00100000   /* controller registers */</div><div class='del'>-			       0x80 0x00000000 0x0 0x00001000&gt;; /* configuration space */</div><div class='add'>+			reg = &lt;0x00 0x03400000 0x0 0x00100000&gt;, /* controller registers */</div><div class='add'>+			      &lt;0x80 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='ctx'> 			reg-names = "csr_axi_slave", "config_axi_slave";</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH&gt;, /* AER interrupt */</div><div class='ctx'> 				     &lt;GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH&gt;, /* PME interrupt */</div><div class='hunk'>@@ -851,7 +1186,7 @@</div><div class='ctx'> 			ppio-wins = &lt;8&gt;;</div><div class='ctx'> 			bus-range = &lt;0x0 0xff&gt;;</div><div class='ctx'> 			ranges = &lt;0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000&gt;; /* non-prefetchable memory */</div><div class='del'>-			msi-parent = &lt;&amp;its&gt;;</div><div class='add'>+			msi-parent = &lt;&amp;its 0&gt;;</div><div class='ctx'> 			#interrupt-cells = &lt;1&gt;;</div><div class='ctx'> 			interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='ctx'> 			interrupt-map = &lt;0000 0 0 1 &amp;gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='hunk'>@@ -862,10 +1197,10 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		pcie@3500000 {</div><div class='add'>+		pcie2: pcie@3500000 {</div><div class='ctx'> 			compatible = "fsl,lx2160a-pcie";</div><div class='del'>-			reg = &lt;0x00 0x03500000 0x0 0x00100000   /* controller registers */</div><div class='del'>-			       0x88 0x00000000 0x0 0x00001000&gt;; /* configuration space */</div><div class='add'>+			reg = &lt;0x00 0x03500000 0x0 0x00100000&gt;, /* controller registers */</div><div class='add'>+			      &lt;0x88 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='ctx'> 			reg-names = "csr_axi_slave", "config_axi_slave";</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH&gt;, /* AER interrupt */</div><div class='ctx'> 				     &lt;GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH&gt;, /* PME interrupt */</div><div class='hunk'>@@ -879,7 +1214,7 @@</div><div class='ctx'> 			ppio-wins = &lt;8&gt;;</div><div class='ctx'> 			bus-range = &lt;0x0 0xff&gt;;</div><div class='ctx'> 			ranges = &lt;0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000&gt;; /* non-prefetchable memory */</div><div class='del'>-			msi-parent = &lt;&amp;its&gt;;</div><div class='add'>+			msi-parent = &lt;&amp;its 0&gt;;</div><div class='ctx'> 			#interrupt-cells = &lt;1&gt;;</div><div class='ctx'> 			interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='ctx'> 			interrupt-map = &lt;0000 0 0 1 &amp;gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='hunk'>@@ -890,10 +1225,10 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		pcie@3600000 {</div><div class='add'>+		pcie3: pcie@3600000 {</div><div class='ctx'> 			compatible = "fsl,lx2160a-pcie";</div><div class='del'>-			reg = &lt;0x00 0x03600000 0x0 0x00100000   /* controller registers */</div><div class='del'>-			       0x90 0x00000000 0x0 0x00001000&gt;; /* configuration space */</div><div class='add'>+			reg = &lt;0x00 0x03600000 0x0 0x00100000&gt;, /* controller registers */</div><div class='add'>+			      &lt;0x90 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='ctx'> 			reg-names = "csr_axi_slave", "config_axi_slave";</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH&gt;, /* AER interrupt */</div><div class='ctx'> 				     &lt;GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH&gt;, /* PME interrupt */</div><div class='hunk'>@@ -907,7 +1242,7 @@</div><div class='ctx'> 			ppio-wins = &lt;24&gt;;</div><div class='ctx'> 			bus-range = &lt;0x0 0xff&gt;;</div><div class='ctx'> 			ranges = &lt;0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000&gt;; /* non-prefetchable memory */</div><div class='del'>-			msi-parent = &lt;&amp;its&gt;;</div><div class='add'>+			msi-parent = &lt;&amp;its 0&gt;;</div><div class='ctx'> 			#interrupt-cells = &lt;1&gt;;</div><div class='ctx'> 			interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='ctx'> 			interrupt-map = &lt;0000 0 0 1 &amp;gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='hunk'>@@ -918,10 +1253,10 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		pcie@3700000 {</div><div class='add'>+		pcie4: pcie@3700000 {</div><div class='ctx'> 			compatible = "fsl,lx2160a-pcie";</div><div class='del'>-			reg = &lt;0x00 0x03700000 0x0 0x00100000   /* controller registers */</div><div class='del'>-			       0x98 0x00000000 0x0 0x00001000&gt;; /* configuration space */</div><div class='add'>+			reg = &lt;0x00 0x03700000 0x0 0x00100000&gt;, /* controller registers */</div><div class='add'>+			      &lt;0x98 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='ctx'> 			reg-names = "csr_axi_slave", "config_axi_slave";</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH&gt;, /* AER interrupt */</div><div class='ctx'> 				     &lt;GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH&gt;, /* PME interrupt */</div><div class='hunk'>@@ -935,7 +1270,7 @@</div><div class='ctx'> 			ppio-wins = &lt;8&gt;;</div><div class='ctx'> 			bus-range = &lt;0x0 0xff&gt;;</div><div class='ctx'> 			ranges = &lt;0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000&gt;; /* non-prefetchable memory */</div><div class='del'>-			msi-parent = &lt;&amp;its&gt;;</div><div class='add'>+			msi-parent = &lt;&amp;its 0&gt;;</div><div class='ctx'> 			#interrupt-cells = &lt;1&gt;;</div><div class='ctx'> 			interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='ctx'> 			interrupt-map = &lt;0000 0 0 1 &amp;gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='hunk'>@@ -946,10 +1281,10 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		pcie@3800000 {</div><div class='add'>+		pcie5: pcie@3800000 {</div><div class='ctx'> 			compatible = "fsl,lx2160a-pcie";</div><div class='del'>-			reg = &lt;0x00 0x03800000 0x0 0x00100000   /* controller registers */</div><div class='del'>-			       0xa0 0x00000000 0x0 0x00001000&gt;; /* configuration space */</div><div class='add'>+			reg = &lt;0x00 0x03800000 0x0 0x00100000&gt;, /* controller registers */</div><div class='add'>+			      &lt;0xa0 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='ctx'> 			reg-names = "csr_axi_slave", "config_axi_slave";</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH&gt;, /* AER interrupt */</div><div class='ctx'> 				     &lt;GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH&gt;, /* PME interrupt */</div><div class='hunk'>@@ -963,7 +1298,7 @@</div><div class='ctx'> 			ppio-wins = &lt;24&gt;;</div><div class='ctx'> 			bus-range = &lt;0x0 0xff&gt;;</div><div class='ctx'> 			ranges = &lt;0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000&gt;; /* non-prefetchable memory */</div><div class='del'>-			msi-parent = &lt;&amp;its&gt;;</div><div class='add'>+			msi-parent = &lt;&amp;its 0&gt;;</div><div class='ctx'> 			#interrupt-cells = &lt;1&gt;;</div><div class='ctx'> 			interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='ctx'> 			interrupt-map = &lt;0000 0 0 1 &amp;gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='hunk'>@@ -974,10 +1309,10 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		pcie@3900000 {</div><div class='add'>+		pcie6: pcie@3900000 {</div><div class='ctx'> 			compatible = "fsl,lx2160a-pcie";</div><div class='del'>-			reg = &lt;0x00 0x03900000 0x0 0x00100000   /* controller registers */</div><div class='del'>-			       0xa8 0x00000000 0x0 0x00001000&gt;; /* configuration space */</div><div class='add'>+			reg = &lt;0x00 0x03900000 0x0 0x00100000&gt;, /* controller registers */</div><div class='add'>+			      &lt;0xa8 0x00000000 0x0 0x00002000&gt;; /* configuration space */</div><div class='ctx'> 			reg-names = "csr_axi_slave", "config_axi_slave";</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH&gt;, /* AER interrupt */</div><div class='ctx'> 				     &lt;GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH&gt;, /* PME interrupt */</div><div class='hunk'>@@ -991,7 +1326,7 @@</div><div class='ctx'> 			ppio-wins = &lt;8&gt;;</div><div class='ctx'> 			bus-range = &lt;0x0 0xff&gt;;</div><div class='ctx'> 			ranges = &lt;0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000&gt;; /* non-prefetchable memory */</div><div class='del'>-			msi-parent = &lt;&amp;its&gt;;</div><div class='add'>+			msi-parent = &lt;&amp;its 0&gt;;</div><div class='ctx'> 			#interrupt-cells = &lt;1&gt;;</div><div class='ctx'> 			interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='ctx'> 			interrupt-map = &lt;0000 0 0 1 &amp;gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='hunk'>@@ -1102,7 +1437,8 @@</div><div class='ctx'> 		ptp-timer@8b95000 {</div><div class='ctx'> 			compatible = "fsl,dpaa2-ptp";</div><div class='ctx'> 			reg = &lt;0x0 0x8b95000 0x0 0x100&gt;;</div><div class='del'>-			clocks = &lt;&amp;clockgen 4 1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='ctx'> 			little-endian;</div><div class='ctx'> 			fsl,extts-fifo;</div><div class='ctx'> 		};</div><div class='hunk'>@@ -1115,6 +1451,9 @@</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			little-endian;</div><div class='add'>+			clock-frequency = &lt;2500000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -1125,14 +1464,325 @@</div><div class='ctx'> 			little-endian;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='add'>+			clock-frequency = &lt;2500000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clockgen QORIQ_CLK_PLATFORM_PLL</div><div class='add'>+					    QORIQ_CLK_PLL_DIV(2)&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcs_mdio1: mdio@8c07000 {</div><div class='add'>+			compatible = "fsl,fman-memac-mdio";</div><div class='add'>+			reg = &lt;0x0 0x8c07000 0x0 0x1000&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcs1: ethernet-phy@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcs_mdio2: mdio@8c0b000 {</div><div class='add'>+			compatible = "fsl,fman-memac-mdio";</div><div class='add'>+			reg = &lt;0x0 0x8c0b000 0x0 0x1000&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcs2: ethernet-phy@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcs_mdio3: mdio@8c0f000 {</div><div class='add'>+			compatible = "fsl,fman-memac-mdio";</div><div class='add'>+			reg = &lt;0x0 0x8c0f000 0x0 0x1000&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcs3: ethernet-phy@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcs_mdio4: mdio@8c13000 {</div><div class='add'>+			compatible = "fsl,fman-memac-mdio";</div><div class='add'>+			reg = &lt;0x0 0x8c13000 0x0 0x1000&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcs4: ethernet-phy@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcs_mdio5: mdio@8c17000 {</div><div class='add'>+			compatible = "fsl,fman-memac-mdio";</div><div class='add'>+			reg = &lt;0x0 0x8c17000 0x0 0x1000&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcs5: ethernet-phy@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcs_mdio6: mdio@8c1b000 {</div><div class='add'>+			compatible = "fsl,fman-memac-mdio";</div><div class='add'>+			reg = &lt;0x0 0x8c1b000 0x0 0x1000&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcs6: ethernet-phy@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcs_mdio7: mdio@8c1f000 {</div><div class='add'>+			compatible = "fsl,fman-memac-mdio";</div><div class='add'>+			reg = &lt;0x0 0x8c1f000 0x0 0x1000&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcs7: ethernet-phy@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcs_mdio8: mdio@8c23000 {</div><div class='add'>+			compatible = "fsl,fman-memac-mdio";</div><div class='add'>+			reg = &lt;0x0 0x8c23000 0x0 0x1000&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcs8: ethernet-phy@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcs_mdio9: mdio@8c27000 {</div><div class='add'>+			compatible = "fsl,fman-memac-mdio";</div><div class='add'>+			reg = &lt;0x0 0x8c27000 0x0 0x1000&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcs9: ethernet-phy@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcs_mdio10: mdio@8c2b000 {</div><div class='add'>+			compatible = "fsl,fman-memac-mdio";</div><div class='add'>+			reg = &lt;0x0 0x8c2b000 0x0 0x1000&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcs10: ethernet-phy@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcs_mdio11: mdio@8c2f000 {</div><div class='add'>+			compatible = "fsl,fman-memac-mdio";</div><div class='add'>+			reg = &lt;0x0 0x8c2f000 0x0 0x1000&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcs11: ethernet-phy@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcs_mdio12: mdio@8c33000 {</div><div class='add'>+			compatible = "fsl,fman-memac-mdio";</div><div class='add'>+			reg = &lt;0x0 0x8c33000 0x0 0x1000&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcs12: ethernet-phy@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcs_mdio13: mdio@8c37000 {</div><div class='add'>+			compatible = "fsl,fman-memac-mdio";</div><div class='add'>+			reg = &lt;0x0 0x8c37000 0x0 0x1000&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcs13: ethernet-phy@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcs_mdio14: mdio@8c3b000 {</div><div class='add'>+			compatible = "fsl,fman-memac-mdio";</div><div class='add'>+			reg = &lt;0x0 0x8c3b000 0x0 0x1000&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcs14: ethernet-phy@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcs_mdio15: mdio@8c3f000 {</div><div class='add'>+			compatible = "fsl,fman-memac-mdio";</div><div class='add'>+			reg = &lt;0x0 0x8c3f000 0x0 0x1000&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcs15: ethernet-phy@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcs_mdio16: mdio@8c43000 {</div><div class='add'>+			compatible = "fsl,fman-memac-mdio";</div><div class='add'>+			reg = &lt;0x0 0x8c43000 0x0 0x1000&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcs16: ethernet-phy@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcs_mdio17: mdio@8c47000 {</div><div class='add'>+			compatible = "fsl,fman-memac-mdio";</div><div class='add'>+			reg = &lt;0x0 0x8c47000 0x0 0x1000&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcs17: ethernet-phy@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcs_mdio18: mdio@8c4b000 {</div><div class='add'>+			compatible = "fsl,fman-memac-mdio";</div><div class='add'>+			reg = &lt;0x0 0x8c4b000 0x0 0x1000&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcs18: ethernet-phy@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinmux_i2crv: pinmux@70010012c {</div><div class='add'>+			compatible = "pinctrl-single";</div><div class='add'>+			reg = &lt;0x00000007 0x0010012c 0x0 0xc&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			pinctrl-single,bit-per-mux;</div><div class='add'>+			pinctrl-single,register-width = &lt;32&gt;;</div><div class='add'>+			pinctrl-single,function-mask = &lt;0x7&gt;;</div><div class='add'>+</div><div class='add'>+			i2c1_scl: i2c1-scl-pins {</div><div class='add'>+				pinctrl-single,bits = &lt;0x0 0 0x7&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c1_scl_gpio: i2c1-scl-gpio-pins {</div><div class='add'>+				pinctrl-single,bits = &lt;0x0 0x1 0x7&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c2_scl: i2c2-scl-pins {</div><div class='add'>+				pinctrl-single,bits = &lt;0x0 0 (0x7 &lt;&lt; 3)&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c2_scl_gpio: i2c2-scl-gpio-pins {</div><div class='add'>+				pinctrl-single,bits = &lt;0x0 (0x1 &lt;&lt; 3) (0x7 &lt;&lt; 3)&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c3_scl: i2c3-scl-pins {</div><div class='add'>+				pinctrl-single,bits = &lt;0x0 0 (0x7 &lt;&lt; 6)&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c3_scl_gpio: i2c3-scl-gpio-pins {</div><div class='add'>+				pinctrl-single,bits = &lt;0x0 (0x1 &lt;&lt; 6) (0x7 &lt;&lt; 6)&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c4_scl: i2c4-scl-pins {</div><div class='add'>+				pinctrl-single,bits = &lt;0x0 0 (0x7 &lt;&lt; 9)&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c4_scl_gpio: i2c4-scl-gpio-pins {</div><div class='add'>+				pinctrl-single,bits = &lt;0x0 (0x1 &lt;&lt; 9) (0x7 &lt;&lt; 9)&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c5_scl: i2c5-scl-pins {</div><div class='add'>+				pinctrl-single,bits = &lt;0x0 0 (0x7 &lt;&lt; 12)&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c5_scl_gpio: i2c5-scl-gpio-pins {</div><div class='add'>+				pinctrl-single,bits = &lt;0x0 (0x1 &lt;&lt; 12) (0x7 &lt;&lt; 12)&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c6_scl: i2c6-scl-pins {</div><div class='add'>+				pinctrl-single,bits = &lt;0x4 0x2 0x7&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c6_scl_gpio: i2c6-scl-gpio-pins {</div><div class='add'>+				pinctrl-single,bits = &lt;0x4 0x1 0x7&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c7_scl: i2c7-scl-pins {</div><div class='add'>+				pinctrl-single,bits = &lt;0x4 0x2 0x7&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c7_scl_gpio: i2c7-scl-gpio-pins {</div><div class='add'>+				pinctrl-single,bits = &lt;0x4 0x1 0x7&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c0_scl: i2c0-scl-pins {</div><div class='add'>+				pinctrl-single,bits = &lt;0x8 0 (0x7 &lt;&lt; 10)&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c0_scl_gpio: i2c0-scl-gpio-pins {</div><div class='add'>+				pinctrl-single,bits = &lt;0x8 (0x1 &lt;&lt; 10) (0x7 &lt;&lt; 10)&gt;;</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		fsl_mc: fsl-mc@80c000000 {</div><div class='ctx'> 			compatible = "fsl,qoriq-mc";</div><div class='ctx'> 			reg = &lt;0x00000008 0x0c000000 0 0x40&gt;,</div><div class='ctx'> 			      &lt;0x00000000 0x08340000 0 0x40000&gt;;</div><div class='del'>-			msi-parent = &lt;&amp;its&gt;;</div><div class='add'>+			msi-parent = &lt;&amp;its 0&gt;;</div><div class='ctx'> 			/* iommu-map property is fixed up by u-boot */</div><div class='ctx'> 			iommu-map = &lt;0 &amp;smmu 0 0&gt;;</div><div class='ctx'> 			dma-coherent;</div><div class='hunk'>@@ -1153,96 +1803,122 @@</div><div class='ctx'> 				#address-cells = &lt;1&gt;;</div><div class='ctx'> 				#size-cells = &lt;0&gt;;</div><div class='ctx'> </div><div class='del'>-				dpmac1: dpmac@1 {</div><div class='add'>+				dpmac1: ethernet@1 {</div><div class='ctx'> 					compatible = "fsl,qoriq-mc-dpmac";</div><div class='ctx'> 					reg = &lt;0x1&gt;;</div><div class='add'>+					pcs-handle = &lt;&amp;pcs1&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				dpmac2: dpmac@2 {</div><div class='add'>+				dpmac2: ethernet@2 {</div><div class='ctx'> 					compatible = "fsl,qoriq-mc-dpmac";</div><div class='ctx'> 					reg = &lt;0x2&gt;;</div><div class='add'>+					pcs-handle = &lt;&amp;pcs2&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				dpmac3: dpmac@3 {</div><div class='add'>+				dpmac3: ethernet@3 {</div><div class='ctx'> 					compatible = "fsl,qoriq-mc-dpmac";</div><div class='ctx'> 					reg = &lt;0x3&gt;;</div><div class='add'>+					pcs-handle = &lt;&amp;pcs3&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				dpmac4: dpmac@4 {</div><div class='add'>+				dpmac4: ethernet@4 {</div><div class='ctx'> 					compatible = "fsl,qoriq-mc-dpmac";</div><div class='ctx'> 					reg = &lt;0x4&gt;;</div><div class='add'>+					pcs-handle = &lt;&amp;pcs4&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				dpmac5: dpmac@5 {</div><div class='add'>+				dpmac5: ethernet@5 {</div><div class='ctx'> 					compatible = "fsl,qoriq-mc-dpmac";</div><div class='ctx'> 					reg = &lt;0x5&gt;;</div><div class='add'>+					pcs-handle = &lt;&amp;pcs5&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				dpmac6: dpmac@6 {</div><div class='add'>+				dpmac6: ethernet@6 {</div><div class='ctx'> 					compatible = "fsl,qoriq-mc-dpmac";</div><div class='ctx'> 					reg = &lt;0x6&gt;;</div><div class='add'>+					pcs-handle = &lt;&amp;pcs6&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				dpmac7: dpmac@7 {</div><div class='add'>+				dpmac7: ethernet@7 {</div><div class='ctx'> 					compatible = "fsl,qoriq-mc-dpmac";</div><div class='ctx'> 					reg = &lt;0x7&gt;;</div><div class='add'>+					pcs-handle = &lt;&amp;pcs7&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				dpmac8: dpmac@8 {</div><div class='add'>+				dpmac8: ethernet@8 {</div><div class='ctx'> 					compatible = "fsl,qoriq-mc-dpmac";</div><div class='ctx'> 					reg = &lt;0x8&gt;;</div><div class='add'>+					pcs-handle = &lt;&amp;pcs8&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				dpmac9: dpmac@9 {</div><div class='add'>+				dpmac9: ethernet@9 {</div><div class='ctx'> 					compatible = "fsl,qoriq-mc-dpmac";</div><div class='ctx'> 					reg = &lt;0x9&gt;;</div><div class='add'>+					pcs-handle = &lt;&amp;pcs9&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				dpmac10: dpmac@a {</div><div class='add'>+				dpmac10: ethernet@a {</div><div class='ctx'> 					compatible = "fsl,qoriq-mc-dpmac";</div><div class='ctx'> 					reg = &lt;0xa&gt;;</div><div class='add'>+					pcs-handle = &lt;&amp;pcs10&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				dpmac11: dpmac@b {</div><div class='add'>+				dpmac11: ethernet@b {</div><div class='ctx'> 					compatible = "fsl,qoriq-mc-dpmac";</div><div class='ctx'> 					reg = &lt;0xb&gt;;</div><div class='add'>+					pcs-handle = &lt;&amp;pcs11&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				dpmac12: dpmac@c {</div><div class='add'>+				dpmac12: ethernet@c {</div><div class='ctx'> 					compatible = "fsl,qoriq-mc-dpmac";</div><div class='ctx'> 					reg = &lt;0xc&gt;;</div><div class='add'>+					pcs-handle = &lt;&amp;pcs12&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				dpmac13: dpmac@d {</div><div class='add'>+				dpmac13: ethernet@d {</div><div class='ctx'> 					compatible = "fsl,qoriq-mc-dpmac";</div><div class='ctx'> 					reg = &lt;0xd&gt;;</div><div class='add'>+					pcs-handle = &lt;&amp;pcs13&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				dpmac14: dpmac@e {</div><div class='add'>+				dpmac14: ethernet@e {</div><div class='ctx'> 					compatible = "fsl,qoriq-mc-dpmac";</div><div class='ctx'> 					reg = &lt;0xe&gt;;</div><div class='add'>+					pcs-handle = &lt;&amp;pcs14&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				dpmac15: dpmac@f {</div><div class='add'>+				dpmac15: ethernet@f {</div><div class='ctx'> 					compatible = "fsl,qoriq-mc-dpmac";</div><div class='ctx'> 					reg = &lt;0xf&gt;;</div><div class='add'>+					pcs-handle = &lt;&amp;pcs15&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				dpmac16: dpmac@10 {</div><div class='add'>+				dpmac16: ethernet@10 {</div><div class='ctx'> 					compatible = "fsl,qoriq-mc-dpmac";</div><div class='ctx'> 					reg = &lt;0x10&gt;;</div><div class='add'>+					pcs-handle = &lt;&amp;pcs16&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				dpmac17: dpmac@11 {</div><div class='add'>+				dpmac17: ethernet@11 {</div><div class='ctx'> 					compatible = "fsl,qoriq-mc-dpmac";</div><div class='ctx'> 					reg = &lt;0x11&gt;;</div><div class='add'>+					pcs-handle = &lt;&amp;pcs17&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				dpmac18: dpmac@12 {</div><div class='add'>+				dpmac18: ethernet@12 {</div><div class='ctx'> 					compatible = "fsl,qoriq-mc-dpmac";</div><div class='ctx'> 					reg = &lt;0x12&gt;;</div><div class='add'>+					pcs-handle = &lt;&amp;pcs18&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	firmware {</div><div class='add'>+		optee: optee {</div><div class='add'>+			compatible = "linaro,optee-tz";</div><div class='add'>+			method = "smc";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts<br/>new file mode 100644<br/>index 000000000000..eafef8718a0f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts</a></div><div class='hunk'>@@ -0,0 +1,377 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+//</div><div class='add'>+// Device Tree file for LX2162A Clearfog</div><div class='add'>+//</div><div class='add'>+// Copyright 2023 Josua Mayer &lt;josua@solid-run.com&gt;</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "fsl-lx2160a.dtsi"</div><div class='add'>+#include "fsl-lx2162a-sr-som.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "SolidRun LX2162A Clearfog";</div><div class='add'>+	compatible = "solidrun,lx2162a-clearfog", "solidrun,lx2162a-som", "fsl,lx2160a";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		crypto = &amp;crypto;</div><div class='add'>+		i2c0 = &amp;i2c0;</div><div class='add'>+		i2c1 = &amp;i2c2;</div><div class='add'>+		i2c2 = &amp;i2c4;</div><div class='add'>+		i2c3 = &amp;sfp_i2c0;</div><div class='add'>+		i2c4 = &amp;sfp_i2c1;</div><div class='add'>+		i2c5 = &amp;sfp_i2c2;</div><div class='add'>+		i2c6 = &amp;sfp_i2c3;</div><div class='add'>+		i2c7 = &amp;mpcie1_i2c;</div><div class='add'>+		i2c8 = &amp;mpcie0_i2c;</div><div class='add'>+		i2c9 = &amp;pcieclk_i2c;</div><div class='add'>+		i2c10 = &amp;i2c5;</div><div class='add'>+		mmc0 = &amp;esdhc0;</div><div class='add'>+		mmc1 = &amp;esdhc1;</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led_sfp_at: led-sfp-at {</div><div class='add'>+			gpios = &lt;&amp;gpio2 5 GPIO_ACTIVE_HIGH&gt;; /* PROC_IRQ5 */</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led_sfp_ab: led-sfp-ab {</div><div class='add'>+			gpios = &lt;&amp;gpio2 11 GPIO_ACTIVE_HIGH&gt;; /* PROC_IRQ11 */</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led_sfp_bt: led-sfp-bt {</div><div class='add'>+			gpios = &lt;&amp;gpio2 13 GPIO_ACTIVE_HIGH&gt;; /* EVT1_B */</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led_sfp_bb: led-sfp-bb {</div><div class='add'>+			gpios = &lt;&amp;gpio2 14 GPIO_ACTIVE_HIGH&gt;; /* EVT2_B */</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp_at: sfp-at {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;sfp_i2c0&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;gpio2 16 GPIO_ACTIVE_LOW&gt;; /* EVT4_B */</div><div class='add'>+		maximum-power-milliwatt = &lt;2000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp_ab: sfp-ab {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;sfp_i2c1&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;gpio2 1 GPIO_ACTIVE_LOW&gt;; /* PROC_IRQ1 */</div><div class='add'>+		maximum-power-milliwatt = &lt;2000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp_bt: sfp-bt {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;sfp_i2c2&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;gpio2 10 GPIO_ACTIVE_LOW&gt;; /* PROC_IRQ10 */</div><div class='add'>+		maximum-power-milliwatt = &lt;2000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp_bb: sfp-bb {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;sfp_i2c3&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;gpio2 15 GPIO_ACTIVE_LOW&gt;; /* EVT3_B */</div><div class='add'>+		maximum-power-milliwatt = &lt;2000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac3 {</div><div class='add'>+	sfp = &lt;&amp;sfp_at&gt;;</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	phys = &lt;&amp;serdes_1 7&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac4 {</div><div class='add'>+	sfp = &lt;&amp;sfp_ab&gt;;</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	phys = &lt;&amp;serdes_1 6&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac5 {</div><div class='add'>+	sfp = &lt;&amp;sfp_bt&gt;;</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	phys = &lt;&amp;serdes_1 5&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac6 {</div><div class='add'>+	sfp = &lt;&amp;sfp_bb&gt;;</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	phys = &lt;&amp;serdes_1 4&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac11 {</div><div class='add'>+	phys = &lt;&amp;serdes_2 0&gt;;</div><div class='add'>+	phy-handle = &lt;&amp;ethernet_phy3&gt;;</div><div class='add'>+	phy-connection-type = "sgmii";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac12 {</div><div class='add'>+	phys = &lt;&amp;serdes_2 1&gt;;</div><div class='add'>+	phy-handle = &lt;&amp;ethernet_phy1&gt;;</div><div class='add'>+	phy-connection-type = "sgmii";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac13 {</div><div class='add'>+	phys = &lt;&amp;serdes_2 6&gt;;</div><div class='add'>+	phy-handle = &lt;&amp;ethernet_phy6&gt;;</div><div class='add'>+	phy-connection-type = "sgmii";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac14 {</div><div class='add'>+	phys = &lt;&amp;serdes_2 7&gt;;</div><div class='add'>+	phy-handle = &lt;&amp;ethernet_phy8&gt;;</div><div class='add'>+	phy-connection-type = "sgmii";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac15 {</div><div class='add'>+	phys = &lt;&amp;serdes_2 4&gt;;</div><div class='add'>+	phy-handle = &lt;&amp;ethernet_phy4&gt;;</div><div class='add'>+	phy-connection-type = "sgmii";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac16 {</div><div class='add'>+	phys = &lt;&amp;serdes_2 5&gt;;</div><div class='add'>+	phy-handle = &lt;&amp;ethernet_phy2&gt;;</div><div class='add'>+	phy-connection-type = "sgmii";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac17 {</div><div class='add'>+	/* override connection to on-SoM phy */</div><div class='add'>+	/delete-property/ phy-handle;</div><div class='add'>+	/delete-property/ phy-connection-type;</div><div class='add'>+</div><div class='add'>+	phys = &lt;&amp;serdes_2 2&gt;;</div><div class='add'>+	phy-handle = &lt;&amp;ethernet_phy5&gt;;</div><div class='add'>+	phy-connection-type = "sgmii";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac18 {</div><div class='add'>+	phys = &lt;&amp;serdes_2 3&gt;;</div><div class='add'>+	phy-handle = &lt;&amp;ethernet_phy7&gt;;</div><div class='add'>+	phy-connection-type = "sgmii";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;emdio1 {</div><div class='add'>+	ethernet_phy1: ethernet-phy@8 {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+		reg = &lt;8&gt;;</div><div class='add'>+		max-speed = &lt;1000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ethernet_phy2: ethernet-phy@9 {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+		reg = &lt;9&gt;;</div><div class='add'>+		max-speed = &lt;1000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ethernet_phy3: ethernet-phy@10 {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+		reg = &lt;10&gt;;</div><div class='add'>+		max-speed = &lt;1000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ethernet_phy4: ethernet-phy@11 {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+		reg = &lt;11&gt;;</div><div class='add'>+		max-speed = &lt;1000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ethernet_phy5: ethernet-phy@12 {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+		reg = &lt;12&gt;;</div><div class='add'>+		max-speed = &lt;1000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ethernet_phy6: ethernet-phy@13 {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+		reg = &lt;13&gt;;</div><div class='add'>+		max-speed = &lt;1000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ethernet_phy7: ethernet-phy@14 {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+		reg = &lt;14&gt;;</div><div class='add'>+		max-speed = &lt;1000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ethernet_phy8: ethernet-phy@15 {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+		reg = &lt;15&gt;;</div><div class='add'>+		max-speed = &lt;1000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;esdhc0 {</div><div class='add'>+	sd-uhs-sdr104;</div><div class='add'>+	sd-uhs-sdr50;</div><div class='add'>+	sd-uhs-sdr25;</div><div class='add'>+	sd-uhs-sdr12;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethernet_phy0 {</div><div class='add'>+	/*</div><div class='add'>+	 * SoM has a phy at address 1 connected to SoC Ethernet Controller 1.</div><div class='add'>+	 * It competes for WRIOP MAC17, and no connector has been wired.</div><div class='add'>+	 */</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* retimer@18 */</div><div class='add'>+</div><div class='add'>+	i2c-mux@70 {</div><div class='add'>+		compatible = "nxp,pca9546";</div><div class='add'>+		reg = &lt;0x70&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		i2c-mux-idle-disconnect;</div><div class='add'>+</div><div class='add'>+		sfp_i2c0: i2c@0 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sfp_i2c1: i2c@1 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sfp_i2c2: i2c@2 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sfp_i2c3: i2c@3 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;3&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c-mux@71 {</div><div class='add'>+		compatible = "nxp,pca9546";</div><div class='add'>+		reg = &lt;0x71&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		i2c-mux-idle-disconnect;</div><div class='add'>+</div><div class='add'>+		mpcie1_i2c: i2c@0 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mpcie0_i2c: i2c@1 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcieclk_i2c: i2c@2 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			/* clock-controller@6b */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie3 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie4 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio4 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio5 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio6 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio11 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio12 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio13 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio14 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio15 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio16 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio17 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio18 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;serdes_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;serdes_2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts<br/>new file mode 100644<br/>index 000000000000..7a595fddc027<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts</a></div><div class='hunk'>@@ -0,0 +1,357 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+//</div><div class='add'>+// Device Tree file for LX2162AQDS</div><div class='add'>+//</div><div class='add'>+// Copyright 2020 NXP</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "fsl-lx2160a-rev2.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "NXP Layerscape LX2162AQDS";</div><div class='add'>+	compatible = "fsl,lx2162a-qds", "fsl,lx2160a";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		crypto = &amp;crypto;</div><div class='add'>+		mmc0 = &amp;esdhc0;</div><div class='add'>+		mmc1 = &amp;esdhc1;</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sb_3v3: regulator-sb3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "LTM4619-3.3VSB";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mdio-mux-1 {</div><div class='add'>+		compatible = "mdio-mux-multiplexer";</div><div class='add'>+		mux-controls = &lt;&amp;mux 0&gt;;</div><div class='add'>+		mdio-parent-bus = &lt;&amp;emdio1&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		mdio@0 { /* On-board RTL8211F PHY #1 RGMII1 */</div><div class='add'>+			reg = &lt;0x00&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			rgmii_phy1: ethernet-phy@1 {</div><div class='add'>+				compatible = "ethernet-phy-id001c.c916";</div><div class='add'>+				reg = &lt;0x1&gt;;</div><div class='add'>+				eee-broken-1000t;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio@8 { /* On-board RTL8211F PHY #2 RGMII2 */</div><div class='add'>+			reg = &lt;0x8&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			rgmii_phy2: ethernet-phy@2 {</div><div class='add'>+				compatible = "ethernet-phy-id001c.c916";</div><div class='add'>+				reg = &lt;0x2&gt;;</div><div class='add'>+				eee-broken-1000t;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio@18 { /* Slot #1 */</div><div class='add'>+			reg = &lt;0x18&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio@19 { /* Slot #2 */</div><div class='add'>+			reg = &lt;0x19&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio@1a { /* Slot #3 */</div><div class='add'>+			reg = &lt;0x1a&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio@1b { /* Slot #4 */</div><div class='add'>+			reg = &lt;0x1b&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio@1c { /* Slot #5 */</div><div class='add'>+			reg = &lt;0x1c&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio@1d { /* Slot #6 */</div><div class='add'>+			reg = &lt;0x1d&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio@1e { /* Slot #7 */</div><div class='add'>+			reg = &lt;0x1e&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio@1f { /* Slot #8 */</div><div class='add'>+			reg = &lt;0x1f&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mdio-mux-2 {</div><div class='add'>+		compatible = "mdio-mux-multiplexer";</div><div class='add'>+		mux-controls = &lt;&amp;mux 1&gt;;</div><div class='add'>+		mdio-parent-bus = &lt;&amp;emdio2&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		mdio@0 { /* Slot #1 (secondary EMI) */</div><div class='add'>+			reg = &lt;0x00&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio@1 { /* Slot #2 (secondary EMI) */</div><div class='add'>+			reg = &lt;0x01&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio@2 { /* Slot #3 (secondary EMI) */</div><div class='add'>+			reg = &lt;0x02&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio@3 { /* Slot #4 (secondary EMI) */</div><div class='add'>+			reg = &lt;0x03&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio@4 { /* Slot #5 (secondary EMI) */</div><div class='add'>+			reg = &lt;0x04&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio@5 { /* Slot #6 (secondary EMI) */</div><div class='add'>+			reg = &lt;0x05&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio@6 { /* Slot #7 (secondary EMI) */</div><div class='add'>+			reg = &lt;0x06&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio@7 { /* Slot #8 (secondary EMI) */</div><div class='add'>+			reg = &lt;0x07&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;can0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;can1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;crypto {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac17 {</div><div class='add'>+	phy-handle = &lt;&amp;rgmii_phy1&gt;;</div><div class='add'>+	phy-connection-type = "rgmii-id";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac18 {</div><div class='add'>+	phy-handle = &lt;&amp;rgmii_phy2&gt;;</div><div class='add'>+	phy-connection-type = "rgmii-id";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dspi0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	dflash0: flash@0 {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;1000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dspi1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	dflash1: flash@0 {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;1000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dspi2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	dflash2: flash@0 {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;1000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;emdio1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;emdio2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;esdhc0 {</div><div class='add'>+	sd-uhs-sdr104;</div><div class='add'>+	sd-uhs-sdr50;</div><div class='add'>+	sd-uhs-sdr25;</div><div class='add'>+	sd-uhs-sdr12;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;esdhc1 {</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	mmc-hs400-1_8v;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fspi {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mt35xu512aba0: flash@0 {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		m25p,fast-read;</div><div class='add'>+		spi-max-frequency = &lt;50000000&gt;;</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;8&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;8&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	fpga@66 {</div><div class='add'>+		compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c",</div><div class='add'>+			     "simple-mfd";</div><div class='add'>+		reg = &lt;0x66&gt;;</div><div class='add'>+</div><div class='add'>+		mux: mux-controller {</div><div class='add'>+			compatible = "reg-mux";</div><div class='add'>+			#mux-control-cells = &lt;1&gt;;</div><div class='add'>+			mux-reg-masks = &lt;0x54 0xf8&gt;, /* 0: reg 0x54, bits 7:3 */</div><div class='add'>+					&lt;0x54 0x07&gt;; /* 1: reg 0x54, bit 2:0 */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c-mux@77 {</div><div class='add'>+		compatible = "nxp,pca9547";</div><div class='add'>+		reg = &lt;0x77&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		i2c@2 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0x2&gt;;</div><div class='add'>+</div><div class='add'>+			power-monitor@40 {</div><div class='add'>+				compatible = "ti,ina220";</div><div class='add'>+				reg = &lt;0x40&gt;;</div><div class='add'>+				shunt-resistor = &lt;500&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			power-monitor@41 {</div><div class='add'>+				compatible = "ti,ina220";</div><div class='add'>+				reg = &lt;0x41&gt;;</div><div class='add'>+				shunt-resistor = &lt;1000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@3 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0x3&gt;;</div><div class='add'>+</div><div class='add'>+			temperature-sensor@4c {</div><div class='add'>+				compatible = "nxp,sa56004";</div><div class='add'>+				reg = &lt;0x4c&gt;;</div><div class='add'>+				vcc-supply = &lt;&amp;sb_3v3&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			rtc@51 {</div><div class='add'>+				compatible = "nxp,pcf2129";</div><div class='add'>+				reg = &lt;0x51&gt;;</div><div class='add'>+				/* IRQ_RTC_B -&gt; IRQ11_B(CPLD) -&gt; IRQ11(CPU), active low */</div><div class='add'>+				interrupts-extended = &lt;&amp;extirq 11 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;optee {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sata0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sata1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sata2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sata3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi<br/>new file mode 100644<br/>index 000000000000..e914291e63a1<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi</a></div><div class='hunk'>@@ -0,0 +1,82 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+//</div><div class='add'>+// Device Tree file for LX2162A-SOM</div><div class='add'>+//</div><div class='add'>+// Copyright 2021 Rabeeh Khoury &lt;rabeeh@solid-run.com&gt;</div><div class='add'>+// Copyright 2023 Josua Mayer &lt;josua@solid-run.com&gt;</div><div class='add'>+</div><div class='add'>+&amp;crypto {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac17 {</div><div class='add'>+	phy-handle = &lt;&amp;ethernet_phy0&gt;;</div><div class='add'>+	phy-connection-type = "rgmii-id";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;emdio1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ethernet_phy0: ethernet-phy@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;esdhc1 {</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	mmc-hs400-1_8v;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fspi {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		m25p,fast-read;</div><div class='add'>+		spi-max-frequency = &lt;50000000&gt;;</div><div class='add'>+		/* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */</div><div class='add'>+		spi-rx-bus-width = &lt;8&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	fan-controller@18 {</div><div class='add'>+		compatible = "ti,amc6821";</div><div class='add'>+		reg = &lt;0x18&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ddr_spd: eeprom@51 {</div><div class='add'>+		compatible = "st,24c02", "atmel,24c02";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		read-only;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	config_eeprom: eeprom@57 {</div><div class='add'>+		compatible = "st,24c02", "atmel,24c02";</div><div class='add'>+		reg = &lt;0x57&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	variable_eeprom: eeprom@54 {</div><div class='add'>+		compatible = "st,24c2048", "atmel,24c2048";</div><div class='add'>+		reg = &lt;0x54&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c5 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	rtc@6f {</div><div class='add'>+		compatible = "microchip,mcp7940x";</div><div class='add'>+		reg = &lt;0x6f&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx-pcie0-ep.dtso b/arch/arm64/boot/dts/freescale/imx-pcie0-ep.dtso<br/>new file mode 100644<br/>index 000000000000..ed73284d9bb6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx-pcie0-ep.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx-pcie0-ep.dtso</a></div><div class='hunk'>@@ -0,0 +1,15 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0_ep {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx-pcie1-ep.dtso b/arch/arm64/boot/dts/freescale/imx-pcie1-ep.dtso<br/>new file mode 100644<br/>index 000000000000..0e7ef7ef8560<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx-pcie1-ep.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx-pcie1-ep.dtso</a></div><div class='hunk'>@@ -0,0 +1,15 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2025 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+&amp;pcie1 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie1_ep {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-eval-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-eval-v1.1.dtsi<br/>new file mode 100644<br/>index 000000000000..0f77f78f4d96<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8-apalis-eval-v1.1.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8-apalis-eval-v1.1.dtsi</a></div><div class='hunk'>@@ -0,0 +1,26 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "imx8-apalis-eval.dtsi"</div><div class='add'>+</div><div class='add'>+/* Apalis CAN1 */</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis CAN2 */</div><div class='add'>+&amp;flexcan2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis MMC1 */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis SD1 */</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-eval-v1.2.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-eval-v1.2.dtsi<br/>new file mode 100644<br/>index 000000000000..5862b24fb764<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8-apalis-eval-v1.2.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8-apalis-eval-v1.2.dtsi</a></div><div class='hunk'>@@ -0,0 +1,193 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "imx8-apalis-eval.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	reg_3v3_mmc: regulator-3v3-mmc {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_enable_3v3_mmc&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;lsio_gpio5 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		off-on-delay-us = &lt;100000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "3.3V_MMC";</div><div class='add'>+		startup-delay-us = &lt;10000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3v3_sd: regulator-3v3-sd {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_enable_3v3_sd&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;lsio_gpio5 20 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		off-on-delay-us = &lt;100000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "3.3V_SD";</div><div class='add'>+		startup-delay-us = &lt;10000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_can1: regulator-can1 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_enable_can1_power&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;lsio_gpio5 22 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		regulator-name = "5V_SW_CAN1";</div><div class='add'>+		startup-delay-us = &lt;10000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_can2: regulator-can2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_enable_can2_power&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;lsio_gpio5 21 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		regulator-name = "5V_SW_CAN2";</div><div class='add'>+		startup-delay-us = &lt;10000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-carrier {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,bitclock-master = &lt;&amp;codec_dai&gt;;</div><div class='add'>+		simple-audio-card,format = "i2s";</div><div class='add'>+		simple-audio-card,frame-master = &lt;&amp;codec_dai&gt;;</div><div class='add'>+		simple-audio-card,name = "apalis-nau8822";</div><div class='add'>+		simple-audio-card,routing =</div><div class='add'>+			"Headphones", "LHP",</div><div class='add'>+			"Headphones", "RHP",</div><div class='add'>+			"Speaker", "LSPK",</div><div class='add'>+			"Speaker", "RSPK",</div><div class='add'>+			"Line Out", "AUXOUT1",</div><div class='add'>+			"Line Out", "AUXOUT2",</div><div class='add'>+			"LAUX", "Line In",</div><div class='add'>+			"RAUX", "Line In",</div><div class='add'>+			"LMICP", "Mic In",</div><div class='add'>+			"RMICP", "Mic In";</div><div class='add'>+		simple-audio-card,widgets =</div><div class='add'>+			"Headphones", "Headphones",</div><div class='add'>+			"Line Out", "Line Out",</div><div class='add'>+			"Speaker", "Speaker",</div><div class='add'>+			"Microphone", "Mic In",</div><div class='add'>+			"Line", "Line In";</div><div class='add'>+</div><div class='add'>+		codec_dai: simple-audio-card,codec {</div><div class='add'>+			sound-dai = &lt;&amp;nau8822_1a&gt;;</div><div class='add'>+			system-clock-frequency = &lt;12288000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;sai0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis CAN1 */</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	xceiver-supply = &lt;&amp;reg_can1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis CAN2 */</div><div class='add'>+&amp;flexcan2 {</div><div class='add'>+	xceiver-supply = &lt;&amp;reg_can2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis I2C1 */</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* Audio Codec */</div><div class='add'>+	nau8822_1a: audio-codec@1a {</div><div class='add'>+		compatible = "nuvoton,nau8822";</div><div class='add'>+		reg = &lt;0x1a&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Power/Current Measurement Sensor */</div><div class='add'>+	hwmon@40 {</div><div class='add'>+		compatible = "ti,ina219";</div><div class='add'>+		reg = &lt;0x40&gt;;</div><div class='add'>+		shunt-resistor = &lt;5000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	temperature-sensor@4f {</div><div class='add'>+		compatible = "ti,tmp75c";</div><div class='add'>+		reg = &lt;0x4f&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@57 {</div><div class='add'>+		compatible = "st,24c02", "atmel,24c02";</div><div class='add'>+		reg = &lt;0x57&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai0 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS&gt;,</div><div class='add'>+			  &lt;&amp;sai0_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;786432000&gt;, &lt;49152000&gt;, &lt;12288000&gt;, &lt;49152000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai0&gt;;</div><div class='add'>+	#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis MMC1 */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2_4bit&gt;, &lt;&amp;pinctrl_mmc1_cd&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_4bit_100mhz&gt;, &lt;&amp;pinctrl_mmc1_cd&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_4bit_200mhz&gt;, &lt;&amp;pinctrl_mmc1_cd&gt;;</div><div class='add'>+	pinctrl-3 = &lt;&amp;pinctrl_usdhc2_4bit_sleep&gt;, &lt;&amp;pinctrl_mmc1_cd_sleep&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_3v3_mmc&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis SD1 */</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_3v3_sd&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_cam1_gpios&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_esai0_gpios&gt;, &lt;&amp;pinctrl_fec2_gpios&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_gpio3&gt;, &lt;&amp;pinctrl_gpio4&gt;, &lt;&amp;pinctrl_gpio_keys&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_gpio_usbh_oc_n&gt;, &lt;&amp;pinctrl_lpuart1ctrl&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_lvds0_i2c0_gpio&gt;, &lt;&amp;pinctrl_lvds1_i2c0_gpios&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_mipi_dsi_0_1_en&gt;, &lt;&amp;pinctrl_mipi_dsi1_gpios&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_mlb_gpios&gt;, &lt;&amp;pinctrl_qspi1a_gpios&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_sata1_act&gt;, &lt;&amp;pinctrl_sim0_gpios&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_usdhc1_gpios&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl_enable_3v3_mmc: enable3v3mmcgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_USDHC1_DATA4_LSIO_GPIO5_IO19	0x00000021&gt;; /* MXM3_148 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_enable_3v3_sd: enable3v3sdgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_USDHC1_DATA5_LSIO_GPIO5_IO20	0x00000021&gt;; /* MXM3_152 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_enable_can1_power: enablecan1powergrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22	0x00000021&gt;; /* MXM3_158 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_enable_can2_power: enablecan2powergrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21	0x00000021&gt;; /* MXM3_156 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai0: sai0grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_SAI1_RXC_AUD_SAI0_TXD	0xc600006c&gt;, /* MXM3_196 */</div><div class='add'>+			   &lt;IMX8QM_SPI0_CS1_AUD_SAI0_TXC	0xc600004c&gt;, /* MXM3_200 */</div><div class='add'>+			   &lt;IMX8QM_SAI1_RXFS_AUD_SAI0_RXD	0xc600004c&gt;, /* MXM3_202 */</div><div class='add'>+			   &lt;IMX8QM_SPI2_CS1_AUD_SAI0_TXFS	0xc600004c&gt;; /* MXM3_204 */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi<br/>new file mode 100644<br/>index 000000000000..06790255a764<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi</a></div><div class='hunk'>@@ -0,0 +1,150 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		rtc0 = &amp;rtc_i2c;</div><div class='add'>+		rtc1 = &amp;rtc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb_host_vbus: regulator-usb-host-vbus {</div><div class='add'>+		regulator-name = "VCC USBH2(ABCD) / USBH(3|4)";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;adc0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;adc1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;amix {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;asrc0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* TODO: Display Controller */</div><div class='add'>+</div><div class='add'>+/* TODO: DPU */</div><div class='add'>+</div><div class='add'>+/* Apalis ETH1 */</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis I2C1 */</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* M41T0M6 real time clock on carrier board */</div><div class='add'>+	rtc_i2c: rtc@68 {</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis I2C3 (CAM) */</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis SPI1 */</div><div class='add'>+&amp;lpspi0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis SPI2 */</div><div class='add'>+&amp;lpspi2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis UART3 */</div><div class='add'>+&amp;lpuart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis UART1 */</div><div class='add'>+&amp;lpuart1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis UART4 */</div><div class='add'>+&amp;lpuart2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis UART2 */</div><div class='add'>+&amp;lpuart3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis PWM3, MXM3 pin 6 */</div><div class='add'>+&amp;lsio_pwm0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis PWM4, MXM3 pin 8 */</div><div class='add'>+&amp;lsio_pwm1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis PWM1, MXM3 pin 2 */</div><div class='add'>+&amp;lsio_pwm2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis PWM2, MXM3 pin 4 */</div><div class='add'>+&amp;lsio_pwm3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis PCIE1 */</div><div class='add'>+&amp;pciea {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis BKL1_PWM */</div><div class='add'>+&amp;pwm_lvds1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis DAP1 */</div><div class='add'>+&amp;sai1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai5 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai5_lpcg {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis SATA1 */</div><div class='add'>+&amp;sata {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis SPDIF1 */</div><div class='add'>+&amp;spdif0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* TODO: Apalis USBH2, Apalis USBH3 and on-module Wi-Fi via on-module HSIC Hub */</div><div class='add'>+</div><div class='add'>+/* Apalis USBO1 */</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis USBH4 SuperSpeed */</div><div class='add'>+&amp;usbotg3_cdns3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi<br/>new file mode 100644<br/>index 000000000000..7022de46b8bf<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi</a></div><div class='hunk'>@@ -0,0 +1,247 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		rtc0 = &amp;rtc_i2c;</div><div class='add'>+		rtc1 = &amp;rtc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_leds_ixora&gt;;</div><div class='add'>+</div><div class='add'>+		/* LED_4_GREEN / MXM3_188 */</div><div class='add'>+		led-1 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			gpios = &lt;&amp;lsio_gpio5 27 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* LED_4_RED / MXM3_178 */</div><div class='add'>+		led-2 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			gpios = &lt;&amp;lsio_gpio5 29 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* LED_5_GREEN / MXM3_152 */</div><div class='add'>+		led-3 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			gpios = &lt;&amp;lsio_gpio5 20 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* LED_5_RED / MXM3_156 */</div><div class='add'>+		led-4 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			gpios = &lt;&amp;lsio_gpio5 21 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb_host_vbus: regulator-usb-host-vbus {</div><div class='add'>+		regulator-name = "VCC_USBH(2|4)";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;adc0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;adc1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;amix {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;asrc0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* TODO: Display Controller */</div><div class='add'>+</div><div class='add'>+/* TODO: DPU */</div><div class='add'>+</div><div class='add'>+/* Apalis ETH1 */</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis CAN1 */</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis CAN2 */</div><div class='add'>+&amp;flexcan2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* TODO: GPU */</div><div class='add'>+</div><div class='add'>+/* Apalis I2C1 */</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* M41T0M6 real time clock on carrier board */</div><div class='add'>+	rtc_i2c: rtc@68 {</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis I2C3 (CAM) */</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_cam1_gpios&gt;, &lt;&amp;pinctrl_dap1_gpios&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_esai0_gpios&gt;, &lt;&amp;pinctrl_fec2_gpios&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_gpio3&gt;, &lt;&amp;pinctrl_gpio4&gt;, &lt;&amp;pinctrl_gpio_usbh_oc_n&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_lpuart1ctrl&gt;, &lt;&amp;pinctrl_lvds0_i2c0_gpio&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_lvds1_i2c0_gpios&gt;, &lt;&amp;pinctrl_mipi_dsi_0_1_en&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_mipi_dsi1_gpios&gt;, &lt;&amp;pinctrl_mlb_gpios&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_qspi1a_gpios&gt;, &lt;&amp;pinctrl_sata1_act&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_sim0_gpios&gt;, &lt;&amp;pinctrl_uart24_forceoff&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_usdhc1_gpios&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl_leds_ixora: ledsixoragrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_USDHC2_DATA1_LSIO_GPIO5_IO27	0x06000061&gt;, /* LED_4_GREEN */</div><div class='add'>+			   &lt;IMX8QM_USDHC2_DATA3_LSIO_GPIO5_IO29	0x06000061&gt;, /* LED_4_RED */</div><div class='add'>+			   &lt;IMX8QM_USDHC1_DATA5_LSIO_GPIO5_IO20	0x06000061&gt;, /* LED_5_GREEN */</div><div class='add'>+			   &lt;IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21	0x06000061&gt;; /* LED_5_RED */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart24_forceoff: uart24forceoffgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_USDHC2_CMD_LSIO_GPIO5_IO25		0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis SPI1 */</div><div class='add'>+&amp;lpspi0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis SPI2 */</div><div class='add'>+&amp;lpspi2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis UART3 */</div><div class='add'>+&amp;lpuart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis UART1 */</div><div class='add'>+&amp;lpuart1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis UART4 */</div><div class='add'>+&amp;lpuart2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis UART2 */</div><div class='add'>+&amp;lpuart3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio5 {</div><div class='add'>+	gpio-line-names = "gpio5-00", "gpio5-01", "gpio5-02", "gpio5-03",</div><div class='add'>+			  "gpio5-04", "gpio5-05", "gpio5-06", "gpio5-07",</div><div class='add'>+			  "gpio5-08", "gpio5-09", "gpio5-10", "gpio5-11",</div><div class='add'>+			  "gpio5-12", "gpio5-13", "gpio5-14", "gpio5-15",</div><div class='add'>+			  "gpio5-16", "gpio5-17", "gpio5-18", "gpio5-19",</div><div class='add'>+			  "LED-5-GREEN", "LED-5-RED", "gpio5-22", "gpio5-23",</div><div class='add'>+			  "gpio5-24", "UART24-FORCEOFF", "gpio5-26",</div><div class='add'>+			  "LED-4-GREEN", "gpio5-28", "LED-4-RED", "gpio5-30",</div><div class='add'>+			  "gpio5-31";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis PWM3, MXM3 pin 6 */</div><div class='add'>+&amp;lsio_pwm0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis PWM4, MXM3 pin 8 */</div><div class='add'>+&amp;lsio_pwm1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis PWM1, MXM3 pin 2 */</div><div class='add'>+&amp;lsio_pwm2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis PWM2, MXM3 pin 4 */</div><div class='add'>+&amp;lsio_pwm3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis PCIE1 */</div><div class='add'>+&amp;pciea {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis BKL1_PWM */</div><div class='add'>+&amp;pwm_lvds1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis DAP1 */</div><div class='add'>+&amp;sai1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai5 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai5_lpcg {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis SATA1 */</div><div class='add'>+&amp;sata {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis SPDIF1 */</div><div class='add'>+&amp;spdif0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* TODO: Apalis USBH2, Apalis USBH3 and on-module Wi-Fi via on-module HSIC Hub */</div><div class='add'>+</div><div class='add'>+/* Apalis USBO1 */</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis USBH4 SuperSpeed */</div><div class='add'>+&amp;usbotg3_cdns3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis MMC1 */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2_4bit&gt;, &lt;&amp;pinctrl_mmc1_cd&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_4bit_100mhz&gt;, &lt;&amp;pinctrl_mmc1_cd&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_4bit_200mhz&gt;, &lt;&amp;pinctrl_mmc1_cd&gt;;</div><div class='add'>+	pinctrl-3 = &lt;&amp;pinctrl_usdhc2_4bit_sleep&gt;, &lt;&amp;pinctrl_mmc1_cd_sleep&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi<br/>new file mode 100644<br/>index 000000000000..12732ed7f811<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi</a></div><div class='hunk'>@@ -0,0 +1,299 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		rtc0 = &amp;rtc_i2c;</div><div class='add'>+		rtc1 = &amp;rtc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_leds_ixora&gt;;</div><div class='add'>+</div><div class='add'>+		/* LED_4_GREEN / MXM3_188 */</div><div class='add'>+		led-1 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			gpios = &lt;&amp;lsio_gpio5 27 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* LED_4_RED / MXM3_178 */</div><div class='add'>+		led-2 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			gpios = &lt;&amp;lsio_gpio5 29 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* LED_5_GREEN / MXM3_152 */</div><div class='add'>+		led-3 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			gpios = &lt;&amp;lsio_gpio5 20 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* LED_5_RED / MXM3_156 */</div><div class='add'>+		led-4 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			gpios = &lt;&amp;lsio_gpio5 21 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3v3_vmmc: regulator-3v3-vmmc {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_enable_3v3_vmmc&gt;;</div><div class='add'>+		/* MMC1_PWR_CTRL */</div><div class='add'>+		gpio = &lt;&amp;lsio_gpio5 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "3v3_vmmc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_can1_supply: regulator-can1-supply {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_enable_can1_power&gt;;</div><div class='add'>+		gpio = &lt;&amp;lsio_gpio5 22 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-name = "can1_supply";</div><div class='add'>+		startup-delay-us = &lt;1000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_can2_supply: regulator-can2-supply {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_sata1_act&gt;;</div><div class='add'>+		gpio = &lt;&amp;lsio_gpio2 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-name = "can2_supply";</div><div class='add'>+		startup-delay-us = &lt;1000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb_host_vbus: regulator-usb-host-vbus {</div><div class='add'>+		regulator-name = "VCC_USBH(2|4)";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;adc0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;adc1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;amix {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;asrc0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* TODO: Display Controller */</div><div class='add'>+</div><div class='add'>+/* TODO: DPU */</div><div class='add'>+</div><div class='add'>+/* Apalis ETH1 */</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis CAN1 */</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	xceiver-supply = &lt;&amp;reg_can1_supply&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis CAN2 */</div><div class='add'>+&amp;flexcan2 {</div><div class='add'>+	xceiver-supply = &lt;&amp;reg_can2_supply&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* TODO: GPU */</div><div class='add'>+</div><div class='add'>+/* Apalis I2C1 */</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	eeprom: eeprom@50 {</div><div class='add'>+		compatible = "atmel,24c02";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* M41T0M6 real time clock on carrier board */</div><div class='add'>+	rtc_i2c: rtc@68 {</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis I2C3 (CAM) */</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_cam1_gpios&gt;, &lt;&amp;pinctrl_dap1_gpios&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_esai0_gpios&gt;, &lt;&amp;pinctrl_fec2_gpios&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_gpio3&gt;, &lt;&amp;pinctrl_gpio4&gt;, &lt;&amp;pinctrl_gpio_usbh_oc_n&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_lpuart1ctrl&gt;, &lt;&amp;pinctrl_lvds0_i2c0_gpio&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_lvds1_i2c0_gpios&gt;, &lt;&amp;pinctrl_mipi_dsi_0_1_en&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_mipi_dsi1_gpios&gt;, &lt;&amp;pinctrl_mlb_gpios&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_qspi1a_gpios&gt;, &lt;&amp;pinctrl_sim0_gpios&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_uart24_forceoff&gt;, &lt;&amp;pinctrl_usdhc1_gpios&gt;;</div><div class='add'>+</div><div class='add'>+	/* PMIC MMC1 power-switch */</div><div class='add'>+	pinctrl_enable_3v3_vmmc: enable3v3vmmcgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_USDHC1_DATA4_LSIO_GPIO5_IO19	0x00000021&gt;; /* MXM3_148, PMIC */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* FlexCAN PMIC */</div><div class='add'>+	pinctrl_enable_can1_power: enablecan1powergrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22	0x00000021&gt;; /* MXM3_158, PMIC */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_leds_ixora: ledsixoragrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_USDHC2_DATA1_LSIO_GPIO5_IO27	0x06000061&gt;, /* LED_4_GREEN */</div><div class='add'>+			   &lt;IMX8QM_USDHC2_DATA3_LSIO_GPIO5_IO29	0x06000061&gt;, /* LED_4_RED */</div><div class='add'>+			   &lt;IMX8QM_USDHC1_DATA5_LSIO_GPIO5_IO20	0x06000061&gt;, /* LED_5_GREEN */</div><div class='add'>+			   &lt;IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21	0x06000061&gt;; /* LED_5_RED */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart24_forceoff: uart24forceoffgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_USDHC2_CMD_LSIO_GPIO5_IO25		0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis SPI1 */</div><div class='add'>+&amp;lpspi0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis SPI2 */</div><div class='add'>+&amp;lpspi2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis UART3 */</div><div class='add'>+&amp;lpuart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis UART1 */</div><div class='add'>+&amp;lpuart1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis UART4 */</div><div class='add'>+&amp;lpuart2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis UART2 */</div><div class='add'>+&amp;lpuart3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio5 {</div><div class='add'>+	gpio-line-names = "gpio5-00", "gpio5-01", "gpio5-02", "gpio5-03",</div><div class='add'>+			  "gpio5-04", "gpio5-05", "gpio5-06", "gpio5-07",</div><div class='add'>+			  "gpio5-08", "gpio5-09", "gpio5-10", "gpio5-11",</div><div class='add'>+			  "gpio5-12", "gpio5-13", "gpio5-14", "gpio5-15",</div><div class='add'>+			  "gpio5-16", "gpio5-17", "gpio5-18", "gpio5-19",</div><div class='add'>+			  "LED-5-GREEN", "LED-5-RED", "gpio5-22", "gpio5-23",</div><div class='add'>+			  "gpio5-24", "UART24-FORCEOFF", "gpio5-26",</div><div class='add'>+			  "LED-4-GREEN", "gpio5-28", "LED-4-RED", "gpio5-30",</div><div class='add'>+			  "gpio5-31";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis PWM3, MXM3 pin 6 */</div><div class='add'>+&amp;lsio_pwm0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis PWM4, MXM3 pin 8 */</div><div class='add'>+&amp;lsio_pwm1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis PWM1, MXM3 pin 2 */</div><div class='add'>+&amp;lsio_pwm2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis PWM2, MXM3 pin 4 */</div><div class='add'>+&amp;lsio_pwm3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis PCIE1 */</div><div class='add'>+&amp;pciea {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis BKL1_PWM */</div><div class='add'>+&amp;pwm_lvds1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis DAP1 */</div><div class='add'>+&amp;sai1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai5 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai5_lpcg {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis SATA1 */</div><div class='add'>+&amp;sata {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis SPDIF1 */</div><div class='add'>+&amp;spdif0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* TODO: Apalis USBH2, Apalis USBH3 and on-module Wi-Fi via on-module HSIC Hub */</div><div class='add'>+</div><div class='add'>+/* Apalis USBO1 */</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis USBH4 SuperSpeed */</div><div class='add'>+&amp;usbotg3_cdns3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis MMC1 */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2_4bit&gt;, &lt;&amp;pinctrl_mmc1_cd&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_4bit_100mhz&gt;, &lt;&amp;pinctrl_mmc1_cd&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_4bit_200mhz&gt;, &lt;&amp;pinctrl_mmc1_cd&gt;;</div><div class='add'>+	pinctrl-3 = &lt;&amp;pinctrl_usdhc2_4bit_sleep&gt;, &lt;&amp;pinctrl_mmc1_cd_sleep&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cap-power-off-card;</div><div class='add'>+	/delete-property/ no-1-8-v;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_3v3_vmmc&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi<br/>new file mode 100644<br/>index 000000000000..9153dddfd3b8<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi</a></div><div class='hunk'>@@ -0,0 +1,1649 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/pwm/pwm.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;lpuart1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis BKL1 */</div><div class='add'>+	backlight: backlight {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_bkl_on&gt;;</div><div class='add'>+		brightness-levels = &lt;0 45 63 88 119 158 203 255&gt;;</div><div class='add'>+		default-brightness-level = &lt;4&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;lsio_gpio1 4 GPIO_ACTIVE_HIGH&gt;; /* Apalis BKL1_ON */</div><div class='add'>+		pwms = &lt;&amp;pwm_lvds1 0 6666667 PWM_POLARITY_INVERTED&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio_fan: gpio-fan {</div><div class='add'>+		compatible = "gpio-fan";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio8&gt;;</div><div class='add'>+		gpios = &lt;&amp;lsio_gpio3 28 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		gpio-fan,speed-map = &lt;	 0 0</div><div class='add'>+				      3000 1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Power management bus used to control LDO1OUT of the</div><div class='add'>+	 * second PMIC PF8100. This is used for controlling voltage levels of</div><div class='add'>+	 * typespecific RGMII signals and Apalis UART2_RTS UART2_CTS.</div><div class='add'>+	 *</div><div class='add'>+	 * IMX_SC_R_BOARD_R1 for 3.3V</div><div class='add'>+	 * IMX_SC_R_BOARD_R2 for 1.8V</div><div class='add'>+	 * IMX_SC_R_BOARD_R3 for 2.5V</div><div class='add'>+	 * Note that for 2.5V operation the pad muxing needs to be changed,</div><div class='add'>+	 * compare with PSW_OVR field of IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD.</div><div class='add'>+	 *</div><div class='add'>+	 * those power domains are mutually exclusive.</div><div class='add'>+	 */</div><div class='add'>+	reg_ext_rgmii: regulator-ext-rgmii {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_BOARD_R1&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "VDD_EXT_RGMII (LDO1)";</div><div class='add'>+</div><div class='add'>+		regulator-state-mem {</div><div class='add'>+			regulator-off-in-suspend;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_module_3v3: regulator-module-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "+V3.3";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_module_3v3_avdd: regulator-module-3v3-avdd {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "+V3.3_AUDIO";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_module_wifi: regulator-module-wifi {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_wifi_pdn&gt;;</div><div class='add'>+		gpio = &lt;&amp;lsio_gpio1 28 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-name = "Wi-Fi_POWER_DOWN"; /* Wi-Fi module PDn */</div><div class='add'>+		startup-delay-us = &lt;100&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_pcie_switch: regulator-pcie-switch {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio7&gt;;</div><div class='add'>+		gpio = &lt;&amp;lsio_gpio3 26 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-name = "pcie_switch";</div><div class='add'>+		startup-delay-us = &lt;100000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb_host_vbus: regulator-usb-host-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usbh_en&gt;;</div><div class='add'>+		/* Apalis USBH_EN */</div><div class='add'>+		gpio = &lt;&amp;lsio_gpio4 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-name = "usb-host-vbus";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb_hsic: regulator-usb-hsic {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;3000000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3000000&gt;;</div><div class='add'>+		regulator-name = "usb-hsic-dummy";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb_phy: regulator-usb-hsic1 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;3000000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3000000&gt;;</div><div class='add'>+		regulator-name = "usb-phy-dummy";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vref_1v8: regulator-vref-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "+V1.8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		decoder_boot: decoder-boot@84000000 {</div><div class='add'>+			reg = &lt;0 0x84000000 0 0x2000000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		encoder1_boot: encoder1-boot@86000000 {</div><div class='add'>+			reg = &lt;0 0x86000000 0 0x200000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		encoder2_boot: encoder2-boot@86200000 {</div><div class='add'>+			reg = &lt;0 0x86200000 0 0x200000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * reserved-memory layout</div><div class='add'>+		 * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4</div><div class='add'>+		 * Shouldn't be used at A core and Linux side.</div><div class='add'>+		 *</div><div class='add'>+		 */</div><div class='add'>+		m4_reserved: m4@88000000 {</div><div class='add'>+			reg = &lt;0 0x88000000 0 0x8000000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rpmsg_reserved: rpmsg@90200000 {</div><div class='add'>+			reg = &lt;0 0x90200000 0 0x200000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdevbuffer: vdevbuffer@90400000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x90400000 0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		decoder_rpc: decoder-rpc@92000000 {</div><div class='add'>+			reg = &lt;0 0x92000000 0 0x200000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dsp_reserved: dsp@92400000 {</div><div class='add'>+			reg = &lt;0 0x92400000 0 0x2000000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		encoder1_rpc: encoder1-rpc@94400000 {</div><div class='add'>+			reg = &lt;0 0x94400000 0 0x700000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		encoder2_rpc: encoder2-rpc@94b00000 {</div><div class='add'>+			reg = &lt;0 0x94b00000 0 0x700000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* global autoconfigured region for contiguous allocations */</div><div class='add'>+		linux,cma {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			alloc-ranges = &lt;0 0xc0000000 0 0x3c000000&gt;;</div><div class='add'>+			linux,cma-default;</div><div class='add'>+			reusable;</div><div class='add'>+			size = &lt;0 0x3c000000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,bitclock-master = &lt;&amp;dailink_master&gt;;</div><div class='add'>+		simple-audio-card,format = "i2s";</div><div class='add'>+		simple-audio-card,frame-master = &lt;&amp;dailink_master&gt;;</div><div class='add'>+		simple-audio-card,name = "apalis-imx8qm";</div><div class='add'>+</div><div class='add'>+		simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;sai1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dailink_master: simple-audio-card,codec {</div><div class='add'>+			sound-dai = &lt;&amp;sgtl5000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* TODO: HDMI Audio */</div><div class='add'>+</div><div class='add'>+	/* Apalis SPDIF1 */</div><div class='add'>+	sound-spdif {</div><div class='add'>+		compatible = "fsl,imx-audio-spdif";</div><div class='add'>+		model = "imx-spdif";</div><div class='add'>+		spdif-controller = &lt;&amp;spdif0&gt;;</div><div class='add'>+		spdif-in;</div><div class='add'>+		spdif-out;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	thermal-zones {</div><div class='add'>+		pmic-thermal {</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			polling-delay = &lt;2000&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens IMX_SC_R_PMIC_0&gt;;</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				cooling_maps_map0: map0 {</div><div class='add'>+					trip = &lt;&amp;pmic_alert0&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				pmic_alert0: trip0 {</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				pmic_crit0: trip1 {</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					temperature = &lt;125000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	touchscreen: touchscreen {</div><div class='add'>+		compatible = "toradex,vf50-touchscreen";</div><div class='add'>+		interrupt-parent = &lt;&amp;lsio_gpio3&gt;;</div><div class='add'>+		interrupts = &lt;22 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "idle", "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_touchctrl_idle&gt;, &lt;&amp;pinctrl_touchctrl_gpios&gt;;</div><div class='add'>+		pinctrl-1 = &lt;&amp;pinctrl_adc1&gt;, &lt;&amp;pinctrl_touchctrl_gpios&gt;;</div><div class='add'>+		io-channels = &lt;&amp;adc1 2&gt;, &lt;&amp;adc1 1&gt;,</div><div class='add'>+			      &lt;&amp;adc1 0&gt;, &lt;&amp;adc1 3&gt;;</div><div class='add'>+		vf50-ts-min-pressure = &lt;200&gt;;</div><div class='add'>+		xp-gpios = &lt;&amp;lsio_gpio2 4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		xm-gpios = &lt;&amp;lsio_gpio2 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		yp-gpios = &lt;&amp;lsio_gpio2 17 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		ym-gpios = &lt;&amp;lsio_gpio2 21 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		/*</div><div class='add'>+		 * NOTE: you must remove the pinctrl-adc1 from the adc1</div><div class='add'>+		 * node below to use the touchscreen</div><div class='add'>+		 */</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;asrc0 {</div><div class='add'>+	fsl,asrc-rate = &lt;48000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;adc0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_adc0&gt;;</div><div class='add'>+	vref-supply = &lt;&amp;reg_vref_1v8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;adc1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_adc1&gt;;</div><div class='add'>+	vref-supply = &lt;&amp;reg_vref_1v8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu_alert0 {</div><div class='add'>+	temperature = &lt;95000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu_alert1 {</div><div class='add'>+	temperature = &lt;95000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu_crit0 {</div><div class='add'>+	temperature = &lt;105000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu_crit1 {</div><div class='add'>+	temperature = &lt;105000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;drc_alert0 {</div><div class='add'>+	temperature = &lt;95000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;drc_crit0 {</div><div class='add'>+	temperature = &lt;105000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis ETH1 */</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_fec1_sleep&gt;;</div><div class='add'>+	fsl,magic-packet;</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@7 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;7&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;lsio_gpio1&gt;;</div><div class='add'>+			interrupts = &lt;29 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			micrel,led-mode = &lt;0&gt;;</div><div class='add'>+			reset-assert-us = &lt;2&gt;;</div><div class='add'>+			reset-deassert-us = &lt;2&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;lsio_gpio1 11 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis CAN1 */</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis CAN2 */</div><div class='add'>+&amp;flexcan2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis CAN3 (optional) */</div><div class='add'>+&amp;flexcan3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hsio_phy {</div><div class='add'>+	fsl,hsio-cfg = "pciea-pcieb-sata";</div><div class='add'>+	fsl,refclk-pad-mode = "input";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hsio_refa_clk {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie_sata_refclk&gt;;</div><div class='add'>+	enable-gpios = &lt;&amp;lsio_gpio4 11 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hsio_refb_clk {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie_wifi_refclk&gt;;</div><div class='add'>+	clocks = &lt;&amp;hsio_refa_clk&gt;;</div><div class='add'>+	enable-gpios = &lt;&amp;lsio_gpio2 11 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* TODO: Apalis HDMI1 */</div><div class='add'>+</div><div class='add'>+&amp;gpu_alert0 {</div><div class='add'>+	temperature = &lt;95000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu_alert1 {</div><div class='add'>+	temperature = &lt;95000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu_crit0 {</div><div class='add'>+	temperature = &lt;105000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu_crit1 {</div><div class='add'>+	temperature = &lt;105000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* On-module I2C */</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c1&gt;;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* USB3503A */</div><div class='add'>+	usb-hub@8 {</div><div class='add'>+		compatible = "smsc,usb3503a";</div><div class='add'>+		reg = &lt;0x08&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usb3503a&gt;;</div><div class='add'>+		connect-gpios = &lt;&amp;lsio_gpio0 31 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		initial-mode = &lt;1&gt;;</div><div class='add'>+		intn-gpios = &lt;&amp;lsio_gpio1 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		refclk-frequency = &lt;25000000&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;lsio_gpio1 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+	</div><div class='add'>+	/* On Module Audio Codec */</div><div class='add'>+	sgtl5000: audio-codec@a {</div><div class='add'>+		compatible = "fsl,sgtl5000";</div><div class='add'>+		reg = &lt;0x0a&gt;;</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL&gt;,</div><div class='add'>+				  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS&gt;,</div><div class='add'>+				  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS&gt;,</div><div class='add'>+				  &lt;&amp;mclkout0_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;786432000&gt;, &lt;49152000&gt;, &lt;12288000&gt;, &lt;12288000&gt;;</div><div class='add'>+		clocks = &lt;&amp;mclkout0_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_sgtl5000&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		VDDA-supply = &lt;&amp;reg_module_3v3_avdd&gt;;</div><div class='add'>+		VDDD-supply = &lt;&amp;reg_vref_1v8&gt;;</div><div class='add'>+		VDDIO-supply = &lt;&amp;reg_module_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis I2C1 */</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c2&gt;;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+</div><div class='add'>+	atmel_mxt_ts: touch@4a {</div><div class='add'>+		compatible = "atmel,maxtouch";</div><div class='add'>+		reg = &lt;0x4a&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;lsio_gpio4&gt;;</div><div class='add'>+		interrupts = &lt;1 IRQ_TYPE_EDGE_FALLING&gt;;		/* Apalis GPIO5 */</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio5&gt;, &lt;&amp;pinctrl_gpio6&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;lsio_gpio4 2 GPIO_ACTIVE_LOW&gt;;	/* Apalis GPIO6 */</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* M41T0M6 real time clock on carrier board */</div><div class='add'>+	rtc_i2c: rtc@68 {</div><div class='add'>+		compatible = "st,m41t0";</div><div class='add'>+		reg = &lt;0x68&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis I2C3 (CAM) */</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c3&gt;;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;jpegdec {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;jpegenc {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* TODO: Apalis LVDS1 */</div><div class='add'>+</div><div class='add'>+/* Apalis SPI1 */</div><div class='add'>+&amp;lpspi0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpspi0&gt;;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;lsio_gpio3 5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis SPI2 */</div><div class='add'>+&amp;lpspi2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpspi2&gt;;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;lsio_gpio3 10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis UART3 */</div><div class='add'>+&amp;lpuart0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpuart0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis UART1 */</div><div class='add'>+&amp;lpuart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpuart1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis UART4 */</div><div class='add'>+&amp;lpuart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpuart2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis UART2 */</div><div class='add'>+&amp;lpuart3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpuart3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio0 {</div><div class='add'>+	gpio-line-names = "MXM3_279",</div><div class='add'>+			  "MXM3_277",</div><div class='add'>+			  "MXM3_135",</div><div class='add'>+			  "MXM3_203",</div><div class='add'>+			  "MXM3_201",</div><div class='add'>+			  "MXM3_275",</div><div class='add'>+			  "MXM3_110",</div><div class='add'>+			  "MXM3_120",</div><div class='add'>+			  "MXM3_1/GPIO1",</div><div class='add'>+			  "MXM3_3/GPIO2",</div><div class='add'>+			  "MXM3_124",</div><div class='add'>+			  "MXM3_122",</div><div class='add'>+			  "MXM3_5/GPIO3",</div><div class='add'>+			  "MXM3_7/GPIO4",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "MXM3_4",</div><div class='add'>+			  "MXM3_211",</div><div class='add'>+			  "MXM3_209",</div><div class='add'>+			  "MXM3_2",</div><div class='add'>+			  "MXM3_136",</div><div class='add'>+			  "MXM3_134",</div><div class='add'>+			  "MXM3_6",</div><div class='add'>+			  "MXM3_8",</div><div class='add'>+			  "MXM3_112",</div><div class='add'>+			  "MXM3_118",</div><div class='add'>+			  "MXM3_114",</div><div class='add'>+			  "MXM3_116",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "MXM3_26";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio1 {</div><div class='add'>+	gpio-line-names = "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "MXM3_286",</div><div class='add'>+			  "",</div><div class='add'>+			  "MXM3_87",</div><div class='add'>+			  "MXM3_99",</div><div class='add'>+			  "MXM3_138",</div><div class='add'>+			  "MXM3_140",</div><div class='add'>+			  "MXM3_239",</div><div class='add'>+			  "",</div><div class='add'>+			  "MXM3_281",</div><div class='add'>+			  "MXM3_283",</div><div class='add'>+			  "MXM3_126",</div><div class='add'>+			  "MXM3_132",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "MXM3_173",</div><div class='add'>+			  "MXM3_175",</div><div class='add'>+			  "MXM3_123";</div><div class='add'>+</div><div class='add'>+	hdmi-ctrl-hog {</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_hdmi_ctrl&gt;;</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;30 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		line-name = "CONNECTOR_IS_HDMI";</div><div class='add'>+		/* Set signals depending on HDP device type, 0 DP, 1 HDMI */</div><div class='add'>+		output-high;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio2 {</div><div class='add'>+	gpio-line-names = "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "MXM3_198",</div><div class='add'>+			  "MXM3_35",</div><div class='add'>+			  "MXM3_164",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "MXM3_217",</div><div class='add'>+			  "MXM3_215",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "MXM3_193",</div><div class='add'>+			  "MXM3_194",</div><div class='add'>+			  "MXM3_37",</div><div class='add'>+			  "",</div><div class='add'>+			  "MXM3_271",</div><div class='add'>+			  "MXM3_273",</div><div class='add'>+			  "MXM3_195",</div><div class='add'>+			  "MXM3_197",</div><div class='add'>+			  "MXM3_177",</div><div class='add'>+			  "MXM3_179",</div><div class='add'>+			  "MXM3_181",</div><div class='add'>+			  "MXM3_183",</div><div class='add'>+			  "MXM3_185",</div><div class='add'>+			  "MXM3_187";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio3 {</div><div class='add'>+	gpio-line-names = "MXM3_191",</div><div class='add'>+			  "",</div><div class='add'>+			  "MXM3_221",</div><div class='add'>+			  "MXM3_225",</div><div class='add'>+			  "MXM3_223",</div><div class='add'>+			  "MXM3_227",</div><div class='add'>+			  "MXM3_200",</div><div class='add'>+			  "MXM3_235",</div><div class='add'>+			  "MXM3_231",</div><div class='add'>+			  "MXM3_229",</div><div class='add'>+			  "MXM3_233",</div><div class='add'>+			  "MXM3_204",</div><div class='add'>+			  "MXM3_196",</div><div class='add'>+			  "",</div><div class='add'>+			  "MXM3_202",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "MXM3_305",</div><div class='add'>+			  "MXM3_307",</div><div class='add'>+			  "MXM3_309",</div><div class='add'>+			  "MXM3_311",</div><div class='add'>+			  "MXM3_315",</div><div class='add'>+			  "MXM3_317",</div><div class='add'>+			  "MXM3_319",</div><div class='add'>+			  "MXM3_321",</div><div class='add'>+			  "MXM3_15/GPIO7",</div><div class='add'>+			  "MXM3_63",</div><div class='add'>+			  "MXM3_17/GPIO8",</div><div class='add'>+			  "MXM3_12",</div><div class='add'>+			  "MXM3_14",</div><div class='add'>+			  "MXM3_16";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio4 {</div><div class='add'>+	gpio-line-names = "MXM3_18",</div><div class='add'>+			  "MXM3_11/GPIO5",</div><div class='add'>+			  "MXM3_13/GPIO6",</div><div class='add'>+			  "MXM3_274",</div><div class='add'>+			  "MXM3_84",</div><div class='add'>+			  "MXM3_262",</div><div class='add'>+			  "MXM3_96",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "MXM3_190",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "MXM3_269",</div><div class='add'>+			  "MXM3_251",</div><div class='add'>+			  "MXM3_253",</div><div class='add'>+			  "MXM3_295",</div><div class='add'>+			  "MXM3_299",</div><div class='add'>+			  "MXM3_301",</div><div class='add'>+			  "MXM3_297",</div><div class='add'>+			  "MXM3_293",</div><div class='add'>+			  "MXM3_291",</div><div class='add'>+			  "MXM3_289",</div><div class='add'>+			  "MXM3_287";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio5 {</div><div class='add'>+	gpio-line-names = "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "MXM3_150",</div><div class='add'>+			  "MXM3_160",</div><div class='add'>+			  "MXM3_162",</div><div class='add'>+			  "MXM3_144",</div><div class='add'>+			  "MXM3_146",</div><div class='add'>+			  "MXM3_148",</div><div class='add'>+			  "MXM3_152",</div><div class='add'>+			  "MXM3_156",</div><div class='add'>+			  "MXM3_158",</div><div class='add'>+			  "MXM3_159",</div><div class='add'>+			  "MXM3_184",</div><div class='add'>+			  "MXM3_180",</div><div class='add'>+			  "MXM3_186",</div><div class='add'>+			  "MXM3_188",</div><div class='add'>+			  "MXM3_176",</div><div class='add'>+			  "MXM3_178";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio6 {</div><div class='add'>+	gpio-line-names = "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "MXM3_261",</div><div class='add'>+			  "MXM3_263",</div><div class='add'>+			  "MXM3_259",</div><div class='add'>+			  "MXM3_257",</div><div class='add'>+			  "MXM3_255",</div><div class='add'>+			  "MXM3_128",</div><div class='add'>+			  "MXM3_130",</div><div class='add'>+			  "MXM3_265",</div><div class='add'>+			  "MXM3_249",</div><div class='add'>+			  "MXM3_247",</div><div class='add'>+			  "MXM3_245",</div><div class='add'>+			  "MXM3_243";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis PWM3, MXM3 pin 6 */</div><div class='add'>+&amp;lsio_pwm0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm0&gt;;</div><div class='add'>+	#pwm-cells = &lt;3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis PWM4, MXM3 pin 8 */</div><div class='add'>+&amp;lsio_pwm1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm1&gt;;</div><div class='add'>+	#pwm-cells = &lt;3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis PWM1, MXM3 pin 2 */</div><div class='add'>+&amp;lsio_pwm2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm2&gt;;</div><div class='add'>+	#pwm-cells = &lt;3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis PWM2, MXM3 pin 4 */</div><div class='add'>+&amp;lsio_pwm3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm3&gt;;</div><div class='add'>+	#pwm-cells = &lt;3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Messaging Units */</div><div class='add'>+&amp;mu_m0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mu1_m0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mu2_m0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis PCIE1 */</div><div class='add'>+&amp;pciea {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_reset_moci&gt;;</div><div class='add'>+	phys = &lt;&amp;hsio_phy 0 PHY_TYPE_PCIE 0&gt;;</div><div class='add'>+	phy-names = "pcie-phy";</div><div class='add'>+	reset-gpio = &lt;&amp;lsio_gpio0 30 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vpcie-supply = &lt;&amp;reg_pcie_switch&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* On-module Wi-Fi */</div><div class='add'>+&amp;pcieb {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcieb&gt;, &lt;&amp;pinctrl_wifi&gt;;</div><div class='add'>+	phys = &lt;&amp;hsio_phy 1 PHY_TYPE_PCIE 1&gt;;</div><div class='add'>+	phy-names = "pcie-phy";</div><div class='add'>+	reset-gpio = &lt;&amp;lsio_gpio5 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;phyx2_lpcg {</div><div class='add'>+	clocks = &lt;&amp;hsio_refa_clk&gt;, &lt;&amp;hsio_refb_clk&gt;,</div><div class='add'>+		 &lt;&amp;hsio_refa_clk&gt;, &lt;&amp;hsio_per_clk&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm_lvds1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm_bkl&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis DAP1 */</div><div class='add'>+&amp;sai1 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS&gt;,</div><div class='add'>+			  &lt;&amp;sai1_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;786432000&gt;, &lt;49152000&gt;, &lt;12288000&gt;, &lt;49152000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai1&gt;;</div><div class='add'>+	#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis HDMI Audio */</div><div class='add'>+&amp;sai5 {</div><div class='add'>+	assigned-clocks = &lt;&amp;acm IMX_ADMA_ACM_SAI5_MCLK_SEL&gt;,</div><div class='add'>+			  &lt;&amp;acm IMX_ADMA_ACM_AUD_CLK1_SEL&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS&gt;,</div><div class='add'>+			  &lt;&amp;sai5_lpcg 0&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;aud_pll_div0_lpcg 0&gt;, &lt;&amp;aud_rec1_lpcg 0&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;0&gt;, &lt;0&gt;, &lt;786432000&gt;, &lt;49152000&gt;, &lt;12288000&gt;,</div><div class='add'>+			       &lt;722534400&gt;, &lt;45158400&gt;, &lt;11289600&gt;, &lt;49152000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis SPDIF1 */</div><div class='add'>+&amp;spdif0 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;786432000&gt;, &lt;49152000&gt;, &lt;12288000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_spdif0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* TODO: Apalis USBH2, Apalis USBH3 and on-module Wi-Fi via on-module HSIC Hub */</div><div class='add'>+</div><div class='add'>+/* Apalis USBH4 */</div><div class='add'>+&amp;usb3_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg3_cdns3 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis USBO1 */</div><div class='add'>+&amp;usbphy1 {</div><div class='add'>+	phy-3p0-supply = &lt;&amp;reg_usb_phy&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usbotg1&gt;;</div><div class='add'>+	adp-disable;</div><div class='add'>+	hnp-disable;</div><div class='add'>+	over-current-active-low;</div><div class='add'>+	power-active-high;</div><div class='add'>+	srp-disable;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* On-module eMMC */</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1_200mhz&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis MMC1 */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2_4bit&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_usdhc2_8bit&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_mmc1_cd&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_4bit_100mhz&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_usdhc2_8bit_100mhz&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_mmc1_cd&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_4bit_200mhz&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_usdhc2_8bit_200mhz&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_mmc1_cd&gt;;</div><div class='add'>+	pinctrl-3 = &lt;&amp;pinctrl_usdhc2_4bit_sleep&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_usdhc2_8bit_sleep&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_mmc1_cd_sleep&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;lsio_gpio2 9 GPIO_ACTIVE_LOW&gt;; /* Apalis MMC1_CD# */</div><div class='add'>+	no-1-8-v;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis SD1 */</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;, &lt;&amp;pinctrl_sd1_cd&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;, &lt;&amp;pinctrl_sd1_cd&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;, &lt;&amp;pinctrl_sd1_cd&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;lsio_gpio4 12 GPIO_ACTIVE_LOW&gt;; /* Apalis SD1_CD# */</div><div class='add'>+	no-1-8-v;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Video Processing Unit */</div><div class='add'>+&amp;vpu {</div><div class='add'>+	compatible = "nxp,imx8qm-vpu";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;vpu_core0 {</div><div class='add'>+	reg = &lt;0x2d080000 0x10000&gt;;</div><div class='add'>+	memory-region = &lt;&amp;decoder_boot&gt;, &lt;&amp;decoder_rpc&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;vpu_core1 {</div><div class='add'>+	reg = &lt;0x2d090000 0x10000&gt;;</div><div class='add'>+	memory-region = &lt;&amp;encoder1_boot&gt;, &lt;&amp;encoder1_rpc&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;vpu_core2 {</div><div class='add'>+	reg = &lt;0x2d0a0000 0x10000&gt;;</div><div class='add'>+	memory-region = &lt;&amp;encoder2_boot&gt;, &lt;&amp;encoder2_rpc&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_cam1_gpios&gt;, &lt;&amp;pinctrl_dap1_gpios&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_esai0_gpios&gt;, &lt;&amp;pinctrl_fec2_gpios&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_gpio3&gt;, &lt;&amp;pinctrl_gpio4&gt;, &lt;&amp;pinctrl_gpio_keys&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_gpio_usbh_oc_n&gt;, &lt;&amp;pinctrl_lpuart1ctrl&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_lvds0_i2c0_gpio&gt;, &lt;&amp;pinctrl_lvds1_i2c0_gpios&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_mipi_dsi_0_1_en&gt;, &lt;&amp;pinctrl_mipi_dsi1_gpios&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_mlb_gpios&gt;, &lt;&amp;pinctrl_qspi1a_gpios&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_sata1_act&gt;, &lt;&amp;pinctrl_sim0_gpios&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_usdhc1_gpios&gt;;</div><div class='add'>+</div><div class='add'>+	/* Apalis AN1_ADC */</div><div class='add'>+	pinctrl_adc0: adc0grp {</div><div class='add'>+		fsl,pins = /* Apalis AN1_ADC0 */</div><div class='add'>+			   &lt;IMX8QM_ADC_IN0_DMA_ADC0_IN0				0xc0000060&gt;,</div><div class='add'>+			   /* Apalis AN1_ADC1 */</div><div class='add'>+			   &lt;IMX8QM_ADC_IN1_DMA_ADC0_IN1				0xc0000060&gt;,</div><div class='add'>+			   /* Apalis AN1_ADC2 */</div><div class='add'>+			   &lt;IMX8QM_ADC_IN2_DMA_ADC0_IN2				0xc0000060&gt;,</div><div class='add'>+			   /* Apalis AN1_TSWIP_ADC3 */</div><div class='add'>+			   &lt;IMX8QM_ADC_IN3_DMA_ADC0_IN3				0xc0000060&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis AN1_TS */</div><div class='add'>+	pinctrl_adc1: adc1grp {</div><div class='add'>+		fsl,pins = /* Apalis AN1_TSPX */</div><div class='add'>+			   &lt;IMX8QM_ADC_IN4_DMA_ADC1_IN0				0xc0000060&gt;,</div><div class='add'>+			   /* Apalis AN1_TSMX */</div><div class='add'>+			   &lt;IMX8QM_ADC_IN5_DMA_ADC1_IN1				0xc0000060&gt;,</div><div class='add'>+			   /* Apalis AN1_TSPY */</div><div class='add'>+			   &lt;IMX8QM_ADC_IN6_DMA_ADC1_IN2				0xc0000060&gt;,</div><div class='add'>+			   /* Apalis AN1_TSMY */</div><div class='add'>+			   &lt;IMX8QM_ADC_IN7_DMA_ADC1_IN3				0xc0000060&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis CAM1 */</div><div class='add'>+	pinctrl_cam1_gpios: cam1gpiosgrp {</div><div class='add'>+		fsl,pins = /* Apalis CAM1_D7 */</div><div class='add'>+			   &lt;IMX8QM_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO20		0x00000021&gt;,</div><div class='add'>+			   /* Apalis CAM1_D6 */</div><div class='add'>+			   &lt;IMX8QM_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO21		0x00000021&gt;,</div><div class='add'>+			   /* Apalis CAM1_D5 */</div><div class='add'>+			   &lt;IMX8QM_ESAI0_TX0_LSIO_GPIO2_IO26			0x00000021&gt;,</div><div class='add'>+			   /* Apalis CAM1_D4 */</div><div class='add'>+			   &lt;IMX8QM_ESAI0_TX1_LSIO_GPIO2_IO27			0x00000021&gt;,</div><div class='add'>+			   /* Apalis CAM1_D3 */</div><div class='add'>+			   &lt;IMX8QM_ESAI0_TX2_RX3_LSIO_GPIO2_IO28		0x00000021&gt;,</div><div class='add'>+			   /* Apalis CAM1_D2 */</div><div class='add'>+			   &lt;IMX8QM_ESAI0_TX3_RX2_LSIO_GPIO2_IO29		0x00000021&gt;,</div><div class='add'>+			   /* Apalis CAM1_D1 */</div><div class='add'>+			   &lt;IMX8QM_ESAI0_TX4_RX1_LSIO_GPIO2_IO30		0x00000021&gt;,</div><div class='add'>+			   /* Apalis CAM1_D0 */</div><div class='add'>+			   &lt;IMX8QM_ESAI0_TX5_RX0_LSIO_GPIO2_IO31		0x00000021&gt;,</div><div class='add'>+			   /* Apalis CAM1_PCLK */</div><div class='add'>+			   &lt;IMX8QM_MCLK_IN0_LSIO_GPIO3_IO00			0x00000021&gt;,</div><div class='add'>+			   /* Apalis CAM1_MCLK */</div><div class='add'>+			   &lt;IMX8QM_SPI3_SDO_LSIO_GPIO2_IO18			0x00000021&gt;,</div><div class='add'>+			   /* Apalis CAM1_VSYNC */</div><div class='add'>+			   &lt;IMX8QM_ESAI0_SCKR_LSIO_GPIO2_IO24			0x00000021&gt;,</div><div class='add'>+			   /* Apalis CAM1_HSYNC */</div><div class='add'>+			   &lt;IMX8QM_ESAI0_SCKT_LSIO_GPIO2_IO25			0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis DAP1 */</div><div class='add'>+	pinctrl_dap1_gpios: dap1gpiosgrp {</div><div class='add'>+		fsl,pins = /* Apalis DAP1_MCLK */</div><div class='add'>+			   &lt;IMX8QM_SPI3_SDI_LSIO_GPIO2_IO19			0x00000021&gt;,</div><div class='add'>+			   /* Apalis DAP1_D_OUT */</div><div class='add'>+			   &lt;IMX8QM_SAI1_RXC_LSIO_GPIO3_IO12			0x00000021&gt;,</div><div class='add'>+			   /* Apalis DAP1_RESET */</div><div class='add'>+			   &lt;IMX8QM_ESAI1_SCKT_LSIO_GPIO2_IO07			0x00000021&gt;,</div><div class='add'>+			   /* Apalis DAP1_BIT_CLK */</div><div class='add'>+			   &lt;IMX8QM_SPI0_CS1_LSIO_GPIO3_IO06			0x00000021&gt;,</div><div class='add'>+			   /* Apalis DAP1_D_IN */</div><div class='add'>+			   &lt;IMX8QM_SAI1_RXFS_LSIO_GPIO3_IO14			0x00000021&gt;,</div><div class='add'>+			   /* Apalis DAP1_SYNC */</div><div class='add'>+			   &lt;IMX8QM_SPI2_CS1_LSIO_GPIO3_IO11			0x00000021&gt;,</div><div class='add'>+			   /* On-module Wi-Fi_I2S_EN# */</div><div class='add'>+			   &lt;IMX8QM_ESAI1_TX5_RX0_LSIO_GPIO2_IO13		0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis LCD1_G1+2 */</div><div class='add'>+	pinctrl_esai0_gpios: esai0gpiosgrp {</div><div class='add'>+		fsl,pins = /* Apalis LCD1_G1 */</div><div class='add'>+			   &lt;IMX8QM_ESAI0_FSR_LSIO_GPIO2_IO22			0x00000021&gt;,</div><div class='add'>+			   /* Apalis LCD1_G2 */</div><div class='add'>+			   &lt;IMX8QM_ESAI0_FST_LSIO_GPIO2_IO23			0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* On-module Gigabit Ethernet PHY Micrel KSZ9031 for Apalis GLAN */</div><div class='add'>+	pinctrl_fec1: fec1grp {</div><div class='add'>+		fsl,pins = /* Use pads in 3.3V mode */</div><div class='add'>+			   &lt;IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD			0x000014a0&gt;,</div><div class='add'>+			   &lt;IMX8QM_ENET0_MDC_CONN_ENET0_MDC				0x06000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO				0x06000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL		0x06000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC			0x06000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0		0x06000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1		0x06000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2		0x06000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3		0x06000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC			0x06000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL		0x06000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0		0x06000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1		0x06000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2		0x06000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3		0x06000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M	0x06000020&gt;,</div><div class='add'>+			   /* On-module ETH_RESET# */</div><div class='add'>+			   &lt;IMX8QM_LVDS1_GPIO01_LSIO_GPIO1_IO11				0x06000020&gt;,</div><div class='add'>+			   /* On-module ETH_INT# */</div><div class='add'>+			   &lt;IMX8QM_MIPI_CSI1_MCLK_OUT_LSIO_GPIO1_IO29			0x04000060&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec1_sleep: fec1-sleepgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD		0x000014a0&gt;,</div><div class='add'>+			   &lt;IMX8QM_ENET0_MDC_LSIO_GPIO4_IO14			0x04000040&gt;,</div><div class='add'>+			   &lt;IMX8QM_ENET0_MDIO_LSIO_GPIO4_IO13			0x04000040&gt;,</div><div class='add'>+			   &lt;IMX8QM_ENET0_RGMII_TX_CTL_LSIO_GPIO5_IO31		0x04000040&gt;,</div><div class='add'>+			   &lt;IMX8QM_ENET0_RGMII_TXC_LSIO_GPIO5_IO30		0x04000040&gt;,</div><div class='add'>+			   &lt;IMX8QM_ENET0_RGMII_TXD0_LSIO_GPIO6_IO00		0x04000040&gt;,</div><div class='add'>+			   &lt;IMX8QM_ENET0_RGMII_TXD1_LSIO_GPIO6_IO01		0x04000040&gt;,</div><div class='add'>+			   &lt;IMX8QM_ENET0_RGMII_TXD2_LSIO_GPIO6_IO02		0x04000040&gt;,</div><div class='add'>+			   &lt;IMX8QM_ENET0_RGMII_TXD3_LSIO_GPIO6_IO03		0x04000040&gt;,</div><div class='add'>+			   &lt;IMX8QM_ENET0_RGMII_RXC_LSIO_GPIO6_IO04		0x04000040&gt;,</div><div class='add'>+			   &lt;IMX8QM_ENET0_RGMII_RX_CTL_LSIO_GPIO6_IO05		0x04000040&gt;,</div><div class='add'>+			   &lt;IMX8QM_ENET0_RGMII_RXD0_LSIO_GPIO6_IO06		0x04000040&gt;,</div><div class='add'>+			   &lt;IMX8QM_ENET0_RGMII_RXD1_LSIO_GPIO6_IO07		0x04000040&gt;,</div><div class='add'>+			   &lt;IMX8QM_ENET0_RGMII_RXD2_LSIO_GPIO6_IO08		0x04000040&gt;,</div><div class='add'>+			   &lt;IMX8QM_ENET0_RGMII_RXD3_LSIO_GPIO6_IO09		0x04000040&gt;,</div><div class='add'>+			   &lt;IMX8QM_ENET0_REFCLK_125M_25M_LSIO_GPIO4_IO15	0x04000040&gt;,</div><div class='add'>+			   &lt;IMX8QM_LVDS1_GPIO01_LSIO_GPIO1_IO11			0x06000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_MIPI_CSI1_MCLK_OUT_LSIO_GPIO1_IO29		0x04000040&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis LCD1_ */</div><div class='add'>+	pinctrl_fec2_gpios: fec2gpiosgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD		0x000014a0&gt;,</div><div class='add'>+			   /* Apalis LCD1_R1 */</div><div class='add'>+			   &lt;IMX8QM_ENET1_MDC_LSIO_GPIO4_IO18			0x00000021&gt;,</div><div class='add'>+			   /* Apalis LCD1_R0 */</div><div class='add'>+			   &lt;IMX8QM_ENET1_MDIO_LSIO_GPIO4_IO17			0x00000021&gt;,</div><div class='add'>+			   /* Apalis LCD1_G0 */</div><div class='add'>+			   &lt;IMX8QM_ENET1_REFCLK_125M_25M_LSIO_GPIO4_IO16	0x00000021&gt;,</div><div class='add'>+			   /* Apalis LCD1_R7 */</div><div class='add'>+			   &lt;IMX8QM_ENET1_RGMII_RX_CTL_LSIO_GPIO6_IO17		0x00000021&gt;,</div><div class='add'>+			   /* Apalis LCD1_DE */</div><div class='add'>+			   &lt;IMX8QM_ENET1_RGMII_RXD0_LSIO_GPIO6_IO18		0x00000021&gt;,</div><div class='add'>+			   /* Apalis LCD1_HSYNC */</div><div class='add'>+			   &lt;IMX8QM_ENET1_RGMII_RXD1_LSIO_GPIO6_IO19		0x00000021&gt;,</div><div class='add'>+			   /* Apalis LCD1_VSYNC */</div><div class='add'>+			   &lt;IMX8QM_ENET1_RGMII_RXD2_LSIO_GPIO6_IO20		0x00000021&gt;,</div><div class='add'>+			   /* Apalis LCD1_PCLK */</div><div class='add'>+			   &lt;IMX8QM_ENET1_RGMII_RXD3_LSIO_GPIO6_IO21		0x00000021&gt;,</div><div class='add'>+			   /* Apalis LCD1_R6 */</div><div class='add'>+			   &lt;IMX8QM_ENET1_RGMII_TX_CTL_LSIO_GPIO6_IO11		0x00000021&gt;,</div><div class='add'>+			   /* Apalis LCD1_R5 */</div><div class='add'>+			   &lt;IMX8QM_ENET1_RGMII_TXC_LSIO_GPIO6_IO10		0x00000021&gt;,</div><div class='add'>+			   /* Apalis LCD1_R4 */</div><div class='add'>+			   &lt;IMX8QM_ENET1_RGMII_TXD0_LSIO_GPIO6_IO12		0x00000021&gt;,</div><div class='add'>+			   /* Apalis LCD1_R3 */</div><div class='add'>+			   &lt;IMX8QM_ENET1_RGMII_TXD1_LSIO_GPIO6_IO13		0x00000021&gt;,</div><div class='add'>+			   /* Apalis LCD1_R2 */</div><div class='add'>+			   &lt;IMX8QM_ENET1_RGMII_TXD2_LSIO_GPIO6_IO14		0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis CAN1 */</div><div class='add'>+	pinctrl_flexcan1: flexcan0grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX			0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX			0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis CAN2 */</div><div class='add'>+	pinctrl_flexcan2: flexcan1grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX			0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX			0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis CAN3 (optional) */</div><div class='add'>+	pinctrl_flexcan3: flexcan2grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX			0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX			0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis GPIO1 */</div><div class='add'>+	pinctrl_gpio1: gpio1grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_M40_GPIO0_00_LSIO_GPIO0_IO08			0x06000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis GPIO2 */</div><div class='add'>+	pinctrl_gpio2: gpio2grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_M40_GPIO0_01_LSIO_GPIO0_IO09			0x06000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis GPIO3 */</div><div class='add'>+	pinctrl_gpio3: gpio3grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_M41_GPIO0_00_LSIO_GPIO0_IO12			0x06000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis GPIO4 */</div><div class='add'>+	pinctrl_gpio4: gpio4grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_M41_GPIO0_01_LSIO_GPIO0_IO13			0x06000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis GPIO5 */</div><div class='add'>+	pinctrl_gpio5: gpio5grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_FLEXCAN2_RX_LSIO_GPIO4_IO01			0x06000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis GPIO6 */</div><div class='add'>+	pinctrl_gpio6: gpio6grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_FLEXCAN2_TX_LSIO_GPIO4_IO02			0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis GPIO7 */</div><div class='add'>+	pinctrl_gpio7: gpio7grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_MLB_SIG_LSIO_GPIO3_IO26			0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis GPIO8 */</div><div class='add'>+	pinctrl_gpio8: gpio8grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_MLB_DATA_LSIO_GPIO3_IO28			0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis BKL1_ON */</div><div class='add'>+	pinctrl_gpio_bkl_on: gpiobklongrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_LVDS0_GPIO00_LSIO_GPIO1_IO04			0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis WAKE1_MICO */</div><div class='add'>+	pinctrl_gpio_keys: gpiokeysgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_SPI3_CS0_LSIO_GPIO2_IO20			0x06700021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis USBH_OC# */</div><div class='add'>+	pinctrl_gpio_usbh_oc_n: gpiousbhocngrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_USB_SS3_TC3_LSIO_GPIO4_IO06			0x04000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* On-module HDMI_CTRL */</div><div class='add'>+	pinctrl_hdmi_ctrl: hdmictrlgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30		0x00000061&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* On-module I2C */</div><div class='add'>+	pinctrl_lpi2c1: lpi2c1grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_GPT0_CLK_DMA_I2C1_SCL			0x04000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA			0x04000020&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis I2C1 */</div><div class='add'>+	pinctrl_lpi2c2: lpi2c2grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_GPT1_CLK_DMA_I2C2_SCL			0x04000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_GPT1_CAPTURE_DMA_I2C2_SDA			0x04000020&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis I2C3 (CAM) */</div><div class='add'>+	pinctrl_lpi2c3: lpi2c3grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_SIM0_PD_DMA_I2C3_SCL				0x04000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_SIM0_POWER_EN_DMA_I2C3_SDA			0x04000020&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis SPI1 */</div><div class='add'>+	pinctrl_lpspi0: lpspi0grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_SPI0_SCK_DMA_SPI0_SCK			0x0600004c&gt;,</div><div class='add'>+			   &lt;IMX8QM_SPI0_SDO_DMA_SPI0_SDO			0x0600004c&gt;,</div><div class='add'>+			   &lt;IMX8QM_SPI0_SDI_DMA_SPI0_SDI			0x0600004c&gt;,</div><div class='add'>+			   &lt;IMX8QM_SPI0_CS0_LSIO_GPIO3_IO05			0x0600004c&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis SPI2 */</div><div class='add'>+	pinctrl_lpspi2: lpspi2grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_SPI2_SCK_DMA_SPI2_SCK			0x0600004c&gt;,</div><div class='add'>+			   &lt;IMX8QM_SPI2_SDO_DMA_SPI2_SDO			0x0600004c&gt;,</div><div class='add'>+			   &lt;IMX8QM_SPI2_SDI_DMA_SPI2_SDI			0x0600004c&gt;,</div><div class='add'>+			   &lt;IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10			0x0600004c&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis UART3 */</div><div class='add'>+	pinctrl_lpuart0: lpuart0grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_UART0_RX_DMA_UART0_RX			0x06000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_UART0_TX_DMA_UART0_TX			0x06000020&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis UART1 */</div><div class='add'>+	pinctrl_lpuart1: lpuart1grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_UART1_RX_DMA_UART1_RX			0x06000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_UART1_TX_DMA_UART1_TX			0x06000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_UART1_CTS_B_DMA_UART1_CTS_B			0x06000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_UART1_RTS_B_DMA_UART1_RTS_B			0x06000020&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis UART1 */</div><div class='add'>+	pinctrl_lpuart1ctrl: lpuart1ctrlgrp {</div><div class='add'>+		fsl,pins = /* Apalis UART1_DTR */</div><div class='add'>+			   &lt;IMX8QM_M40_I2C0_SCL_LSIO_GPIO0_IO06			0x00000021&gt;,</div><div class='add'>+			   /* Apalis UART1_DSR */</div><div class='add'>+			   &lt;IMX8QM_M40_I2C0_SDA_LSIO_GPIO0_IO07			0x00000021&gt;,</div><div class='add'>+			   /* Apalis UART1_DCD */</div><div class='add'>+			   &lt;IMX8QM_M41_I2C0_SCL_LSIO_GPIO0_IO10			0x00000021&gt;,</div><div class='add'>+			   /* Apalis UART1_RI */</div><div class='add'>+			   &lt;IMX8QM_M41_I2C0_SDA_LSIO_GPIO0_IO11			0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis UART4 */</div><div class='add'>+	pinctrl_lpuart2: lpuart2grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_LVDS0_I2C1_SCL_DMA_UART2_TX			0x06000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_LVDS0_I2C1_SDA_DMA_UART2_RX			0x06000020&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis UART2 */</div><div class='add'>+	pinctrl_lpuart3: lpuart3grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_LVDS1_I2C1_SCL_DMA_UART3_TX			0x06000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_LVDS1_I2C1_SDA_DMA_UART3_RX			0x06000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_ENET1_RGMII_TXD3_DMA_UART3_RTS_B		0x06000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_ENET1_RGMII_RXC_DMA_UART3_CTS_B		0x06000020&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis TS_2 */</div><div class='add'>+	pinctrl_lvds0_i2c0_gpio: lvds0i2c0gpiogrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06		0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis LCD1_G6+7 */</div><div class='add'>+	pinctrl_lvds1_i2c0_gpios: lvds1i2c0gpiosgrp {</div><div class='add'>+		fsl,pins = /* Apalis LCD1_G6 */</div><div class='add'>+			   &lt;IMX8QM_LVDS1_I2C0_SCL_LSIO_GPIO1_IO12		0x00000021&gt;,</div><div class='add'>+			   /* Apalis LCD1_G7 */</div><div class='add'>+			   &lt;IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13		0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis TS_3 */</div><div class='add'>+	pinctrl_mipi_dsi_0_1_en: mipidsi0-1engrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07		0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis TS_4 */</div><div class='add'>+	pinctrl_mipi_dsi1_gpios: mipidsi1gpiosgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO22		0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis TS_1 */</div><div class='add'>+	pinctrl_mlb_gpios: mlbgpiosgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_MLB_CLK_LSIO_GPIO3_IO27			0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis MMC1_CD# */</div><div class='add'>+	pinctrl_mmc1_cd: mmc1cdgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_ESAI1_TX1_LSIO_GPIO2_IO09			0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_mmc1_cd_sleep: mmc1cdsleepgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_ESAI1_TX1_LSIO_GPIO2_IO09			0x04000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* On-module PCIe_Wi-Fi */</div><div class='add'>+	pinctrl_pcieb: pciebgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30		0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QM_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31		0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QM_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00		0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* On-module PCIe_CLK_EN1 */</div><div class='add'>+	pinctrl_pcie_sata_refclk: pciesatarefclkgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_USDHC2_WP_LSIO_GPIO4_IO11			0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* On-module PCIe_CLK_EN2 */</div><div class='add'>+	pinctrl_pcie_wifi_refclk: pciewifirefclkgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_ESAI1_TX3_RX2_LSIO_GPIO2_IO11		0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis PWM3 */</div><div class='add'>+	pinctrl_pwm0: pwm0grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_UART0_RTS_B_LSIO_PWM0_OUT			0x00000020&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis PWM4 */</div><div class='add'>+	pinctrl_pwm1: pwm1grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_UART0_CTS_B_LSIO_PWM1_OUT			0x00000020&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis PWM1 */</div><div class='add'>+	pinctrl_pwm2: pwm2grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_GPT1_COMPARE_LSIO_PWM2_OUT			0x00000020&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis PWM2 */</div><div class='add'>+	pinctrl_pwm3: pwm3grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_GPT0_COMPARE_LSIO_PWM3_OUT			0x00000020&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis BKL1_PWM */</div><div class='add'>+	pinctrl_pwm_bkl: pwmbklgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_LVDS1_GPIO00_LVDS1_PWM0_OUT			0x00000020&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis LCD1_ */</div><div class='add'>+	pinctrl_qspi1a_gpios: qspi1agpiosgrp {</div><div class='add'>+		fsl,pins = /* Apalis LCD1_B0 */</div><div class='add'>+			   &lt;IMX8QM_QSPI1A_DATA0_LSIO_GPIO4_IO26			0x00000021&gt;,</div><div class='add'>+			   /* Apalis LCD1_B1 */</div><div class='add'>+			   &lt;IMX8QM_QSPI1A_DATA1_LSIO_GPIO4_IO25			0x00000021&gt;,</div><div class='add'>+			   /* Apalis LCD1_B2 */</div><div class='add'>+			   &lt;IMX8QM_QSPI1A_DATA2_LSIO_GPIO4_IO24			0x00000021&gt;,</div><div class='add'>+			   /* Apalis LCD1_B3 */</div><div class='add'>+			   &lt;IMX8QM_QSPI1A_DATA3_LSIO_GPIO4_IO23			0x00000021&gt;,</div><div class='add'>+			   /* Apalis LCD1_B5 */</div><div class='add'>+			   &lt;IMX8QM_QSPI1A_DQS_LSIO_GPIO4_IO22			0x00000021&gt;,</div><div class='add'>+			   /* Apalis LCD1_B7 */</div><div class='add'>+			   &lt;IMX8QM_QSPI1A_SCLK_LSIO_GPIO4_IO21			0x00000021&gt;,</div><div class='add'>+			   /* Apalis LCD1_B4 */</div><div class='add'>+			   &lt;IMX8QM_QSPI1A_SS0_B_LSIO_GPIO4_IO19			0x00000021&gt;,</div><div class='add'>+			   /* Apalis LCD1_B6 */</div><div class='add'>+			   &lt;IMX8QM_QSPI1A_SS1_B_LSIO_GPIO4_IO20			0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* On-module RESET_MOCI#_DRV */</div><div class='add'>+	pinctrl_reset_moci: resetmocigrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_SCU_GPIO0_02_LSIO_GPIO0_IO30			0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* On-module I2S SGTL5000 for Apalis Analogue Audio */</div><div class='add'>+	pinctrl_sai1: sai1grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_SAI1_TXD_AUD_SAI1_TXD			0xc600006c&gt;,</div><div class='add'>+			   &lt;IMX8QM_SAI1_RXD_AUD_SAI1_RXD			0xc600004c&gt;,</div><div class='add'>+			   &lt;IMX8QM_SAI1_TXC_AUD_SAI1_TXC			0xc600004c&gt;,</div><div class='add'>+			   &lt;IMX8QM_SAI1_TXFS_AUD_SAI1_TXFS			0xc600004c&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis SATA1_ACT# */</div><div class='add'>+	pinctrl_sata1_act: sata1actgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_ESAI1_TX0_LSIO_GPIO2_IO08			0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis SD1_CD# */</div><div class='add'>+	pinctrl_sd1_cd: sd1cdgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_USDHC2_CD_B_LSIO_GPIO4_IO12			0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* On-module I2S SGTL5000 SYS_MCLK */</div><div class='add'>+	pinctrl_sgtl5000: sgtl5000grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0			0xc600004c&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis LCD1_ */</div><div class='add'>+	pinctrl_sim0_gpios: sim0gpiosgrp {</div><div class='add'>+		fsl,pins = /* Apalis LCD1_G5 */</div><div class='add'>+			   &lt;IMX8QM_SIM0_CLK_LSIO_GPIO0_IO00			0x00000021&gt;,</div><div class='add'>+			   /* Apalis LCD1_G3 */</div><div class='add'>+			   &lt;IMX8QM_SIM0_GPIO0_00_LSIO_GPIO0_IO05		0x00000021&gt;,</div><div class='add'>+			   /* Apalis TS_5 */</div><div class='add'>+			   &lt;IMX8QM_SIM0_IO_LSIO_GPIO0_IO02			0x00000021&gt;,</div><div class='add'>+			   /* Apalis LCD1_G4 */</div><div class='add'>+			   &lt;IMX8QM_SIM0_RST_LSIO_GPIO0_IO01			0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis SPDIF */</div><div class='add'>+	pinctrl_spdif0: spdif0grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_SPDIF0_TX_AUD_SPDIF0_TX			0xc6000040&gt;,</div><div class='add'>+			   &lt;IMX8QM_SPDIF0_RX_AUD_SPDIF0_RX			0xc6000040&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_touchctrl_gpios: touchctrlgpiosgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_ESAI1_FSR_LSIO_GPIO2_IO04			0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QM_ESAI1_FST_LSIO_GPIO2_IO05			0x00000041&gt;,</div><div class='add'>+			   &lt;IMX8QM_SPI3_SCK_LSIO_GPIO2_IO17			0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QM_SPI3_CS1_LSIO_GPIO2_IO21			0x00000041&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_touchctrl_idle: touchctrlidlegrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_ADC_IN4_LSIO_GPIO3_IO22			0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QM_ADC_IN5_LSIO_GPIO3_IO23			0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QM_ADC_IN6_LSIO_GPIO3_IO24			0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QM_ADC_IN7_LSIO_GPIO3_IO25			0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* On-module USB HSIC HUB (active) */</div><div class='add'>+	pinctrl_usb_hsic_active: usbh1activegrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_USB_HSIC0_DATA_CONN_USB_HSIC0_DATA		0x000000cf&gt;,</div><div class='add'>+			   &lt;IMX8QM_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE	0x000000ff&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* On-module USB HSIC HUB (idle) */</div><div class='add'>+	pinctrl_usb_hsic_idle: usbh1idlegrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_USB_HSIC0_DATA_CONN_USB_HSIC0_DATA		0x000000cf&gt;,</div><div class='add'>+			   &lt;IMX8QM_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE	0x000000cf&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* On-module USB HSIC HUB */</div><div class='add'>+	pinctrl_usb3503a: usb3503agrp {</div><div class='add'>+		fsl,pins = /* On-module HSIC_HUB_CONNECT */</div><div class='add'>+			   &lt;IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31			0x00000041&gt;,</div><div class='add'>+			   /* On-module HSIC_INT_N */</div><div class='add'>+			   &lt;IMX8QM_SCU_GPIO0_05_LSIO_GPIO1_IO01			0x00000021&gt;,</div><div class='add'>+			   /* On-module HSIC_RESET_N */</div><div class='add'>+			   &lt;IMX8QM_SCU_GPIO0_06_LSIO_GPIO1_IO02			0x00000041&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis USBH_EN */</div><div class='add'>+	pinctrl_usbh_en: usbhengrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_USB_SS3_TC1_LSIO_GPIO4_IO04			0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis USBO1 */</div><div class='add'>+	pinctrl_usbotg1: usbotg1grp {</div><div class='add'>+		fsl,pins = /* Apalis USBO1_EN */</div><div class='add'>+			   &lt;IMX8QM_USB_SS3_TC0_CONN_USB_OTG1_PWR		0x00000021&gt;,</div><div class='add'>+			   /* Apalis USBO1_OC# */</div><div class='add'>+			   &lt;IMX8QM_USB_SS3_TC2_CONN_USB_OTG1_OC			0x04000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* On-module eMMC */</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK			0x06000041&gt;,</div><div class='add'>+			   &lt;IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD			0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0			0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1			0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2			0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3			0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4			0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5			0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6			0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7			0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE		0x06000041&gt;,</div><div class='add'>+			   &lt;IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B		0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK			0x06000040&gt;,</div><div class='add'>+			   &lt;IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD			0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0			0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1			0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2			0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3			0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4			0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5			0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6			0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7			0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE		0x06000040&gt;,</div><div class='add'>+			   &lt;IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B		0x00000020&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK			0x06000040&gt;,</div><div class='add'>+			   &lt;IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD			0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0			0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1			0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2			0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3			0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4			0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5			0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6			0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7			0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE		0x06000040&gt;,</div><div class='add'>+			   &lt;IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B		0x00000020&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis TS_6 */</div><div class='add'>+	pinctrl_usdhc1_gpios: usdhc1gpiosgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_USDHC1_STROBE_LSIO_GPIO5_IO23		0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis MMC1 */</div><div class='add'>+	pinctrl_usdhc2_4bit: usdhc2grp4bitgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK			0x06000041&gt;,</div><div class='add'>+			   &lt;IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD			0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0		0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1		0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2		0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3		0x00000021&gt;,</div><div class='add'>+			   /* On-module PMIC use */</div><div class='add'>+			   &lt;IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_4bit_100mhz: usdhc2-4bit100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK			0x06000040&gt;,</div><div class='add'>+			   &lt;IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD			0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0		0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1		0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2		0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3		0x00000020&gt;,</div><div class='add'>+			   /* On-module PMIC use */</div><div class='add'>+			   &lt;IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_4bit_200mhz: usdhc2-4bit200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK			0x06000040&gt;,</div><div class='add'>+			   &lt;IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD			0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0		0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1		0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2		0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3		0x00000020&gt;,</div><div class='add'>+			   /* On-module PMIC use */</div><div class='add'>+			   &lt;IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_8bit: usdhc2grp8bitgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4		0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5		0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6		0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7		0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_8bit_100mhz: usdhc2-8bit100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4		0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5		0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6		0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7		0x00000020&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_8bit_200mhz: usdhc2-8bit200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4		0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5		0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6		0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7		0x00000020&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_4bit_sleep: usdhc2-4bitsleepgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK			0x04000061&gt;,</div><div class='add'>+			   &lt;IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD			0x04000061&gt;,</div><div class='add'>+			   &lt;IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0		0x04000061&gt;,</div><div class='add'>+			   &lt;IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1		0x04000061&gt;,</div><div class='add'>+			   &lt;IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2		0x04000061&gt;,</div><div class='add'>+			   &lt;IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3		0x04000061&gt;,</div><div class='add'>+			   /* On-module PMIC use */</div><div class='add'>+			   &lt;IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_8bit_sleep: usdhc2-8bitsleepgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4		0x04000061&gt;,</div><div class='add'>+			   &lt;IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5		0x04000061&gt;,</div><div class='add'>+			   &lt;IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6		0x04000061&gt;,</div><div class='add'>+			   &lt;IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7		0x04000061&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Apalis SD1 */</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK			0x06000041&gt;,</div><div class='add'>+			   &lt;IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD			0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0		0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1		0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2		0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3		0x00000021&gt;,</div><div class='add'>+			   /* On-module PMIC use */</div><div class='add'>+			   &lt;IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT		0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK			0x06000041&gt;,</div><div class='add'>+			   &lt;IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD			0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0		0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1		0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2		0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3		0x00000021&gt;,</div><div class='add'>+			   /* On-module PMIC use */</div><div class='add'>+			   &lt;IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT		0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK			0x06000041&gt;,</div><div class='add'>+			   &lt;IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD			0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0		0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1		0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2		0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3		0x00000021&gt;,</div><div class='add'>+			   /* On-module PMIC use */</div><div class='add'>+			   &lt;IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT		0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* On-module Wi-Fi */</div><div class='add'>+	pinctrl_wifi: wifigrp {</div><div class='add'>+		fsl,pins = /* On-module Wi-Fi_SUSCLK_32k */</div><div class='add'>+			   &lt;IMX8QM_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K	0x06000021&gt;,</div><div class='add'>+			   /* On-module Wi-Fi_PCIE_W_DISABLE */</div><div class='add'>+			   &lt;IMX8QM_MIPI_CSI0_MCLK_OUT_LSIO_GPIO1_IO24		0x06000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wifi_pdn: wifipdngrp {</div><div class='add'>+		fsl,pins = /* On-module Wi-Fi_POWER_DOWN */</div><div class='add'>+			   &lt;IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28		0x06000021&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi<br/>new file mode 100644<br/>index 000000000000..9386d1a59e82<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi</a></div><div class='hunk'>@@ -0,0 +1,8 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2018-2020 NXP</div><div class='add'>+ *	Dong Aisheng &lt;aisheng.dong@nxp.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "imx8-ss-audio.dtsi"</div><div class='add'>+#include "imx8-ss-dma.dtsi"</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi<br/>new file mode 100644<br/>index 000000000000..5e4233ccfde4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi</a></div><div class='hunk'>@@ -0,0 +1,751 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2018-2019 NXP</div><div class='add'>+ *	Dong Aisheng &lt;aisheng.dong@nxp.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/imx8-clock.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/imx8-lpcg.h&gt;</div><div class='add'>+#include &lt;dt-bindings/dma/fsl-edma.h&gt;</div><div class='add'>+#include &lt;dt-bindings/firmware/imx/rsrc.h&gt;</div><div class='add'>+</div><div class='add'>+audio_ipg_clk: clock-audio-ipg {</div><div class='add'>+	compatible = "fixed-clock";</div><div class='add'>+	#clock-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;120000000&gt;;</div><div class='add'>+	clock-output-names = "audio_ipg_clk";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+clk_ext_aud_mclk0: clock-ext-aud-mclk0 {</div><div class='add'>+	compatible = "fixed-clock";</div><div class='add'>+	#clock-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;0&gt;;</div><div class='add'>+	clock-output-names = "ext_aud_mclk0";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+clk_ext_aud_mclk1: clock-ext-aud-mclk1 {</div><div class='add'>+	compatible = "fixed-clock";</div><div class='add'>+	#clock-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;0&gt;;</div><div class='add'>+	clock-output-names = "ext_aud_mclk1";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+clk_esai0_rx_clk: clock-esai0-rx {</div><div class='add'>+	compatible = "fixed-clock";</div><div class='add'>+	#clock-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;0&gt;;</div><div class='add'>+	clock-output-names = "esai0_rx_clk";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+clk_esai0_rx_hf_clk: clock-esai0-rx-hf {</div><div class='add'>+	compatible = "fixed-clock";</div><div class='add'>+	#clock-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;0&gt;;</div><div class='add'>+	clock-output-names = "esai0_rx_hf_clk";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+clk_esai0_tx_clk: clock-esai0-tx {</div><div class='add'>+	compatible = "fixed-clock";</div><div class='add'>+	#clock-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;0&gt;;</div><div class='add'>+	clock-output-names = "esai0_tx_clk";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+clk_esai0_tx_hf_clk: clock-esai0-tx-hf {</div><div class='add'>+	compatible = "fixed-clock";</div><div class='add'>+	#clock-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;0&gt;;</div><div class='add'>+	clock-output-names = "esai0_tx_hf_clk";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+clk_spdif0_rx: clock-spdif0-rx {</div><div class='add'>+	compatible = "fixed-clock";</div><div class='add'>+	#clock-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;0&gt;;</div><div class='add'>+	clock-output-names = "spdif0_rx";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+clk_sai0_rx_bclk: clock-sai0-rx-bclk {</div><div class='add'>+	compatible = "fixed-clock";</div><div class='add'>+	#clock-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;0&gt;;</div><div class='add'>+	clock-output-names = "sai0_rx_bclk";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+clk_sai0_tx_bclk: clock-sai0-tx-bclk {</div><div class='add'>+	compatible = "fixed-clock";</div><div class='add'>+	#clock-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;0&gt;;</div><div class='add'>+	clock-output-names = "sai0_tx_bclk";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+clk_sai1_rx_bclk: clock-sai1-rx-bclk {</div><div class='add'>+	compatible = "fixed-clock";</div><div class='add'>+	#clock-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;0&gt;;</div><div class='add'>+	clock-output-names = "sai1_rx_bclk";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+clk_sai1_tx_bclk: clock-sai1-tx-bclk {</div><div class='add'>+	compatible = "fixed-clock";</div><div class='add'>+	#clock-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;0&gt;;</div><div class='add'>+	clock-output-names = "sai1_tx_bclk";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+clk_sai2_rx_bclk: clock-sai2-rx-bclk {</div><div class='add'>+	compatible = "fixed-clock";</div><div class='add'>+	#clock-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;0&gt;;</div><div class='add'>+	clock-output-names = "sai2_rx_bclk";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+clk_sai3_rx_bclk: clock-sai3-rx-bclk {</div><div class='add'>+	compatible = "fixed-clock";</div><div class='add'>+	#clock-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;0&gt;;</div><div class='add'>+	clock-output-names = "sai3_rx_bclk";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+clk_sai4_rx_bclk: clock-sai4-rx-bclk {</div><div class='add'>+	compatible = "fixed-clock";</div><div class='add'>+	#clock-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;0&gt;;</div><div class='add'>+	clock-output-names = "sai4_rx_bclk";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+audio_subsys: bus@59000000 {</div><div class='add'>+	compatible = "simple-bus";</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;1&gt;;</div><div class='add'>+	ranges = &lt;0x59000000 0x0 0x59000000 0x1000000&gt;;</div><div class='add'>+</div><div class='add'>+	asrc0: asrc@59000000 {</div><div class='add'>+		compatible = "fsl,imx8qm-asrc";</div><div class='add'>+		reg = &lt;0x59000000 0x10000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;asrc0_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;asrc0_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;aud_pll_div0_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;aud_pll_div1_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;acm IMX_ADMA_ACM_AUD_CLK0_SEL&gt;,</div><div class='add'>+			 &lt;&amp;acm IMX_ADMA_ACM_AUD_CLK1_SEL&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;;</div><div class='add'>+		clock-names = "mem", "ipg",</div><div class='add'>+			      "asrck_0", "asrck_1", "asrck_2", "asrck_3",</div><div class='add'>+			      "asrck_4", "asrck_5", "asrck_6", "asrck_7",</div><div class='add'>+			      "asrck_8", "asrck_9", "asrck_a", "asrck_b",</div><div class='add'>+			      "asrck_c", "asrck_d", "asrck_e", "asrck_f",</div><div class='add'>+			      "spba";</div><div class='add'>+		dmas = &lt;&amp;edma0 0 0 0&gt;,</div><div class='add'>+		       &lt;&amp;edma0 1 0 0&gt;,</div><div class='add'>+		       &lt;&amp;edma0 2 0 0&gt;,</div><div class='add'>+		       &lt;&amp;edma0 3 0 FSL_EDMA_RX&gt;,</div><div class='add'>+		       &lt;&amp;edma0 4 0 FSL_EDMA_RX&gt;,</div><div class='add'>+		       &lt;&amp;edma0 5 0 FSL_EDMA_RX&gt;;</div><div class='add'>+		/* tx* is output channel of asrc, it is rx channel for eDMA */</div><div class='add'>+		dma-names = "rxa", "rxb", "rxc", "txa", "txb", "txc";</div><div class='add'>+		fsl,asrc-rate = &lt;8000&gt;;</div><div class='add'>+		fsl,asrc-width = &lt;16&gt;;</div><div class='add'>+		fsl,asrc-clk-map = &lt;0&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_ASRC_0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	esai0: esai@59010000 {</div><div class='add'>+		compatible = "fsl,imx8qm-esai", "fsl,imx6ull-esai";</div><div class='add'>+		reg = &lt;0x59010000 0x10000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;esai0_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;esai0_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;esai0_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;;</div><div class='add'>+		clock-names = "core", "extal", "fsys", "spba";</div><div class='add'>+		dmas = &lt;&amp;edma0 6 0 FSL_EDMA_RX&gt;, &lt;&amp;edma0 7 0 0&gt;;</div><div class='add'>+		dma-names = "rx", "tx";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_ESAI_0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spdif0: spdif@59020000 {</div><div class='add'>+		compatible = "fsl,imx8qm-spdif";</div><div class='add'>+		reg = &lt;0x59020000 0x10000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH&gt;, /* rx */</div><div class='add'>+			     &lt;GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH&gt;; /* tx */</div><div class='add'>+		clocks = &lt;&amp;spdif0_lpcg IMX_LPCG_CLK_4&gt;,	/* core */</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,			/* rxtx0 */</div><div class='add'>+			 &lt;&amp;spdif0_lpcg IMX_LPCG_CLK_0&gt;,	/* rxtx1 */</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,			/* rxtx2 */</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,			/* rxtx3 */</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,			/* rxtx4 */</div><div class='add'>+			 &lt;&amp;audio_ipg_clk&gt;,		/* rxtx5 */</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,			/* rxtx6 */</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,			/* rxtx7 */</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;;			/* spba */</div><div class='add'>+		clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", "rxtx4",</div><div class='add'>+			      "rxtx5", "rxtx6", "rxtx7", "spba";</div><div class='add'>+		dmas = &lt;&amp;edma0 8 0 (FSL_EDMA_MULTI_FIFO | FSL_EDMA_RX)&gt;,</div><div class='add'>+		       &lt;&amp;edma0 9 0 FSL_EDMA_MULTI_FIFO&gt;;</div><div class='add'>+		dma-names = "rx", "tx";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SPDIF_0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sai0: sai@59040000 {</div><div class='add'>+		compatible = "fsl,imx8qm-sai";</div><div class='add'>+		reg = &lt;0x59040000 0x10000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;sai0_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+			 &lt;&amp;sai0_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;;</div><div class='add'>+		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";</div><div class='add'>+		dma-names = "rx", "tx";</div><div class='add'>+		dmas = &lt;&amp;edma0 12 0 1&gt;, &lt;&amp;edma0 13 0 0&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SAI_0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sai1: sai@59050000 {</div><div class='add'>+		compatible = "fsl,imx8qm-sai";</div><div class='add'>+		reg = &lt;0x59050000 0x10000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;sai1_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+			 &lt;&amp;sai1_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;;</div><div class='add'>+		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";</div><div class='add'>+		dma-names = "rx", "tx";</div><div class='add'>+		dmas = &lt;&amp;edma0 14 0 1&gt;, &lt;&amp;edma0 15 0 0&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SAI_1&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sai2: sai@59060000 {</div><div class='add'>+		compatible = "fsl,imx8qm-sai";</div><div class='add'>+		reg = &lt;0x59060000 0x10000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;sai2_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+			 &lt;&amp;sai2_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;;</div><div class='add'>+		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";</div><div class='add'>+		dma-names = "rx";</div><div class='add'>+		dmas = &lt;&amp;edma0 16 0 1&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SAI_2&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sai3: sai@59070000 {</div><div class='add'>+		compatible = "fsl,imx8qm-sai";</div><div class='add'>+		reg = &lt;0x59070000 0x10000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;sai3_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+			 &lt;&amp;sai3_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;;</div><div class='add'>+		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";</div><div class='add'>+		dma-names = "rx";</div><div class='add'>+		dmas = &lt;&amp;edma0 17 0 1&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SAI_3&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	edma0: dma-controller@591f0000 {</div><div class='add'>+		compatible = "fsl,imx8qm-edma";</div><div class='add'>+		reg = &lt;0x591f0000 0x190000&gt;;</div><div class='add'>+		#dma-cells = &lt;3&gt;;</div><div class='add'>+		dma-channels = &lt;24&gt;;</div><div class='add'>+		dma-channel-mask = &lt;0x5c0c00&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH&gt;, /* 0 asrc 0 */</div><div class='add'>+			     &lt;GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH&gt;, /* 1 */</div><div class='add'>+			     &lt;GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH&gt;, /* 2 */</div><div class='add'>+			     &lt;GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH&gt;, /* 3 */</div><div class='add'>+			     &lt;GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH&gt;, /* 4 */</div><div class='add'>+			     &lt;GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH&gt;, /* 5 */</div><div class='add'>+			     &lt;GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH&gt;, /* 6 esai0 */</div><div class='add'>+			     &lt;GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH&gt;, /* 7 */</div><div class='add'>+			     &lt;GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH&gt;, /* 8 spdif0 */</div><div class='add'>+			     &lt;GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH&gt;, /* 9 */</div><div class='add'>+			     &lt;GIC_SPI 0   IRQ_TYPE_LEVEL_HIGH&gt;, /* 10 unused */</div><div class='add'>+			     &lt;GIC_SPI 0   IRQ_TYPE_LEVEL_HIGH&gt;, /* 11 unused */</div><div class='add'>+			     &lt;GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH&gt;, /* 12 sai0 */</div><div class='add'>+			     &lt;GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH&gt;, /* 13 */</div><div class='add'>+			     &lt;GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH&gt;, /* 14 sai1 */</div><div class='add'>+			     &lt;GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH&gt;, /* 15 */</div><div class='add'>+			     &lt;GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH&gt;, /* 16 sai2 */</div><div class='add'>+			     &lt;GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH&gt;, /* 17 sai3 */</div><div class='add'>+			     &lt;GIC_SPI 0   IRQ_TYPE_LEVEL_HIGH&gt;, /* 18 unused */</div><div class='add'>+			     &lt;GIC_SPI 0   IRQ_TYPE_LEVEL_HIGH&gt;, /* 19 unused */</div><div class='add'>+			     &lt;GIC_SPI 0   IRQ_TYPE_LEVEL_HIGH&gt;, /* 20 unused */</div><div class='add'>+			     &lt;GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH&gt;, /* 21 */</div><div class='add'>+			     &lt;GIC_SPI 0   IRQ_TYPE_LEVEL_HIGH&gt;, /* 22 unused */</div><div class='add'>+			     &lt;GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH&gt;, /* 23 unused */</div><div class='add'>+			     &lt;GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_DMA_0_CH0&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_0_CH1&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_0_CH2&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_0_CH3&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_0_CH4&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_0_CH5&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_0_CH6&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_0_CH7&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_0_CH8&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_0_CH9&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_0_CH10&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_0_CH11&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_0_CH12&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_0_CH13&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_0_CH14&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_0_CH15&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_0_CH16&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_0_CH17&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_0_CH18&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_0_CH19&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_0_CH20&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_0_CH21&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_0_CH22&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_0_CH23&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	asrc0_lpcg: clock-controller@59400000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x59400000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;audio_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "asrc0_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_ASRC_0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	esai0_lpcg: clock-controller@59410000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x59410000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;acm IMX_ADMA_ACM_ESAI0_MCLK_SEL&gt;,</div><div class='add'>+			 &lt;&amp;audio_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "esai0_lpcg_extal_clk",</div><div class='add'>+				     "esai0_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_ESAI_0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spdif0_lpcg: clock-controller@59420000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x59420000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;acm IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL&gt;,</div><div class='add'>+			 &lt;&amp;audio_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "spdif0_lpcg_tx_clk",</div><div class='add'>+				     "spdif0_lpcg_gclkw";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SPDIF_0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sai0_lpcg: clock-controller@59440000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x59440000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;acm IMX_ADMA_ACM_SAI0_MCLK_SEL&gt;,</div><div class='add'>+			 &lt;&amp;audio_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "sai0_lpcg_mclk",</div><div class='add'>+				     "sai0_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SAI_0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sai1_lpcg: clock-controller@59450000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x59450000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;acm IMX_ADMA_ACM_SAI1_MCLK_SEL&gt;,</div><div class='add'>+			 &lt;&amp;audio_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "sai1_lpcg_mclk",</div><div class='add'>+				     "sai1_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SAI_1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sai2_lpcg: clock-controller@59460000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x59460000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;acm IMX_ADMA_ACM_SAI2_MCLK_SEL&gt;,</div><div class='add'>+			 &lt;&amp;audio_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "sai2_lpcg_mclk",</div><div class='add'>+				     "sai2_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SAI_2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sai3_lpcg: clock-controller@59470000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x59470000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;acm IMX_ADMA_ACM_SAI3_MCLK_SEL&gt;,</div><div class='add'>+			 &lt;&amp;audio_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "sai3_lpcg_mclk",</div><div class='add'>+				     "sai3_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SAI_3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dsp_lpcg: clock-controller@59580000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x59580000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;audio_ipg_clk&gt;,</div><div class='add'>+			 &lt;&amp;audio_ipg_clk&gt;,</div><div class='add'>+			 &lt;&amp;audio_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_4&gt;, &lt;IMX_LPCG_CLK_5&gt;,</div><div class='add'>+				&lt;IMX_LPCG_CLK_7&gt;;</div><div class='add'>+		clock-output-names = "dsp_lpcg_adb_clk",</div><div class='add'>+				     "dsp_lpcg_ipg_clk",</div><div class='add'>+				     "dsp_lpcg_core_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_DSP&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dsp_ram_lpcg: clock-controller@59590000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x59590000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;audio_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "dsp_ram_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_DSP_RAM&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dsp: dsp@596e8000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-hifi4";</div><div class='add'>+		reg = &lt;0x596e8000 0x88000&gt;;</div><div class='add'>+		clocks = &lt;&amp;dsp_lpcg IMX_LPCG_CLK_5&gt;,</div><div class='add'>+			 &lt;&amp;dsp_ram_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;dsp_lpcg IMX_LPCG_CLK_7&gt;;</div><div class='add'>+		clock-names = "ipg", "ocram", "core";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_MU_13B&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_MU_2A&gt;;</div><div class='add'>+		mbox-names = "tx", "rx", "rxdb";</div><div class='add'>+		mboxes = &lt;&amp;lsio_mu13 0 0&gt;,</div><div class='add'>+			 &lt;&amp;lsio_mu13 1 0&gt;,</div><div class='add'>+			 &lt;&amp;lsio_mu13 3 0&gt;;</div><div class='add'>+		firmware-name = "imx/dsp/hifi4.bin";</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	asrc1: asrc@59800000 {</div><div class='add'>+		compatible = "fsl,imx8qm-asrc";</div><div class='add'>+		reg = &lt;0x59800000 0x10000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;asrc1_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;asrc1_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;aud_pll_div0_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;aud_pll_div1_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;acm IMX_ADMA_ACM_AUD_CLK0_SEL&gt;,</div><div class='add'>+			 &lt;&amp;acm IMX_ADMA_ACM_AUD_CLK1_SEL&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;;</div><div class='add'>+		clock-names = "mem", "ipg",</div><div class='add'>+			      "asrck_0", "asrck_1", "asrck_2", "asrck_3",</div><div class='add'>+			      "asrck_4", "asrck_5", "asrck_6", "asrck_7",</div><div class='add'>+			      "asrck_8", "asrck_9", "asrck_a", "asrck_b",</div><div class='add'>+			      "asrck_c", "asrck_d", "asrck_e", "asrck_f",</div><div class='add'>+			      "spba";</div><div class='add'>+		dmas = &lt;&amp;edma1 0 0 0&gt;,</div><div class='add'>+		       &lt;&amp;edma1 1 0 0&gt;,</div><div class='add'>+		       &lt;&amp;edma1 2 0 0&gt;,</div><div class='add'>+		       &lt;&amp;edma1 3 0 FSL_EDMA_RX&gt;,</div><div class='add'>+		       &lt;&amp;edma1 4 0 FSL_EDMA_RX&gt;,</div><div class='add'>+		       &lt;&amp;edma1 5 0 FSL_EDMA_RX&gt;;</div><div class='add'>+		/* tx* is output channel of asrc, it is rx channel for eDMA */</div><div class='add'>+		dma-names = "rxa", "rxb", "rxc", "txa", "txb", "txc";</div><div class='add'>+		fsl,asrc-rate = &lt;8000&gt;;</div><div class='add'>+		fsl,asrc-width = &lt;16&gt;;</div><div class='add'>+		fsl,asrc-clk-map = &lt;1&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_ASRC_1&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sai4: sai@59820000 {</div><div class='add'>+		compatible = "fsl,imx8qm-sai";</div><div class='add'>+		reg = &lt;0x59820000 0x10000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;sai4_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+			 &lt;&amp;sai4_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;;</div><div class='add'>+		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";</div><div class='add'>+		dmas = &lt;&amp;edma1 8 0 FSL_EDMA_RX&gt;, &lt;&amp;edma1 9 0 0&gt;;</div><div class='add'>+		dma-names = "rx", "tx";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SAI_4&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sai5: sai@59830000 {</div><div class='add'>+		compatible = "fsl,imx8qm-sai";</div><div class='add'>+		reg = &lt;0x59830000 0x10000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;sai5_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+			 &lt;&amp;sai5_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;;</div><div class='add'>+		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";</div><div class='add'>+		dmas = &lt;&amp;edma1 10 0 0&gt;;</div><div class='add'>+		dma-names = "tx";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SAI_5&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	amix: amix@59840000 {</div><div class='add'>+		compatible = "fsl,imx8qm-audmix";</div><div class='add'>+		reg = &lt;0x59840000 0x10000&gt;;</div><div class='add'>+		clocks = &lt;&amp;amix_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-names = "ipg";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_AMIX&gt;;</div><div class='add'>+		dais = &lt;&amp;sai4&gt;, &lt;&amp;sai5&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mqs: mqs@59850000 {</div><div class='add'>+		compatible = "fsl,imx8qm-mqs";</div><div class='add'>+		reg = &lt;0x59850000 0x10000&gt;;</div><div class='add'>+		clocks = &lt;&amp;mqs0_lpcg IMX_LPCG_CLK_4&gt;, &lt;&amp;mqs0_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-names = "mclk", "core";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_MQS_0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	edma1: dma-controller@599f0000 {</div><div class='add'>+		compatible = "fsl,imx8qm-edma";</div><div class='add'>+		reg = &lt;0x599f0000 0xc0000&gt;;</div><div class='add'>+		#dma-cells = &lt;3&gt;;</div><div class='add'>+		dma-channels = &lt;11&gt;;</div><div class='add'>+		dma-channel-mask = &lt;0xc0&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH&gt;, /* 0 asrc 1 */</div><div class='add'>+			     &lt;GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH&gt;, /* 1 */</div><div class='add'>+			     &lt;GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH&gt;, /* 2 */</div><div class='add'>+			     &lt;GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH&gt;, /* 3 */</div><div class='add'>+			     &lt;GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH&gt;, /* 4 */</div><div class='add'>+			     &lt;GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH&gt;, /* 5 */</div><div class='add'>+			     &lt;GIC_SPI 0   IRQ_TYPE_LEVEL_HIGH&gt;, /* 6 unused */</div><div class='add'>+			     &lt;GIC_SPI 0   IRQ_TYPE_LEVEL_HIGH&gt;, /* 7 unused */</div><div class='add'>+			     &lt;GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH&gt;, /* sai4 */</div><div class='add'>+			     &lt;GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH&gt;, /* sai5 */</div><div class='add'>+			     &lt;GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_DMA_1_CH0&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_1_CH1&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_1_CH2&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_1_CH3&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_1_CH4&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_1_CH5&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_1_CH6&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_1_CH7&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_1_CH8&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_1_CH9&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_1_CH10&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_rec0_lpcg: clock-controller@59d00000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x59d00000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-output-names = "aud_rec_clk0_lpcg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_AUDIO_PLL_0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_rec1_lpcg: clock-controller@59d10000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x59d10000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-output-names = "aud_rec_clk1_lpcg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_AUDIO_PLL_1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_pll_div0_lpcg: clock-controller@59d20000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x59d20000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-output-names = "aud_pll_div_clk0_lpcg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_AUDIO_PLL_0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_pll_div1_lpcg: clock-controller@59d30000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x59d30000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-output-names = "aud_pll_div_clk1_lpcg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_AUDIO_PLL_1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mclkout0_lpcg: clock-controller@59d50000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x59d50000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;acm IMX_ADMA_ACM_MCLKOUT0_SEL&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-output-names = "mclkout0_lpcg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_MCLK_OUT_0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mclkout1_lpcg: clock-controller@59d60000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x59d60000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;acm IMX_ADMA_ACM_MCLKOUT1_SEL&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-output-names = "mclkout1_lpcg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_MCLK_OUT_1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	acm: acm@59e00000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-acm";</div><div class='add'>+		reg = &lt;0x59e00000 0x1d0000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_AUDIO_CLK_0&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_AUDIO_CLK_1&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_MCLK_OUT_0&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_MCLK_OUT_1&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_AUDIO_PLL_0&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_AUDIO_PLL_1&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_ASRC_0&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_ASRC_1&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_ESAI_0&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_SAI_0&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_SAI_1&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_SAI_2&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_SAI_3&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_SAI_4&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_SAI_5&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_SPDIF_0&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_MQS_0&gt;;</div><div class='add'>+		clocks = &lt;&amp;aud_rec0_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;aud_rec1_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;aud_pll_div0_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;aud_pll_div1_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;clk_ext_aud_mclk0&gt;,</div><div class='add'>+			 &lt;&amp;clk_ext_aud_mclk1&gt;,</div><div class='add'>+			 &lt;&amp;clk_esai0_rx_clk&gt;,</div><div class='add'>+			 &lt;&amp;clk_esai0_rx_hf_clk&gt;,</div><div class='add'>+			 &lt;&amp;clk_esai0_tx_clk&gt;,</div><div class='add'>+			 &lt;&amp;clk_esai0_tx_hf_clk&gt;,</div><div class='add'>+			 &lt;&amp;clk_spdif0_rx&gt;,</div><div class='add'>+			 &lt;&amp;clk_sai0_rx_bclk&gt;,</div><div class='add'>+			 &lt;&amp;clk_sai0_tx_bclk&gt;,</div><div class='add'>+			 &lt;&amp;clk_sai1_rx_bclk&gt;,</div><div class='add'>+			 &lt;&amp;clk_sai1_tx_bclk&gt;,</div><div class='add'>+			 &lt;&amp;clk_sai2_rx_bclk&gt;,</div><div class='add'>+			 &lt;&amp;clk_sai3_rx_bclk&gt;,</div><div class='add'>+			 &lt;&amp;clk_sai4_rx_bclk&gt;;</div><div class='add'>+		clock-names = "aud_rec_clk0_lpcg_clk",</div><div class='add'>+			      "aud_rec_clk1_lpcg_clk",</div><div class='add'>+			      "aud_pll_div_clk0_lpcg_clk",</div><div class='add'>+			      "aud_pll_div_clk1_lpcg_clk",</div><div class='add'>+			      "ext_aud_mclk0",</div><div class='add'>+			      "ext_aud_mclk1",</div><div class='add'>+			      "esai0_rx_clk",</div><div class='add'>+			      "esai0_rx_hf_clk",</div><div class='add'>+			      "esai0_tx_clk",</div><div class='add'>+			      "esai0_tx_hf_clk",</div><div class='add'>+			      "spdif0_rx",</div><div class='add'>+			      "sai0_rx_bclk",</div><div class='add'>+			      "sai0_tx_bclk",</div><div class='add'>+			      "sai1_rx_bclk",</div><div class='add'>+			      "sai1_tx_bclk",</div><div class='add'>+			      "sai2_rx_bclk",</div><div class='add'>+			      "sai3_rx_bclk",</div><div class='add'>+			      "sai4_rx_bclk";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	asrc1_lpcg: clock-controller@59c00000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x59c00000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;audio_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "asrc1_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_ASRC_1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sai4_lpcg: clock-controller@59c20000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x59c20000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;acm IMX_ADMA_ACM_SAI4_MCLK_SEL&gt;,</div><div class='add'>+			 &lt;&amp;audio_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "sai4_lpcg_mclk",</div><div class='add'>+				     "sai4_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SAI_4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sai5_lpcg: clock-controller@59c30000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x59c30000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;acm IMX_ADMA_ACM_SAI5_MCLK_SEL&gt;,</div><div class='add'>+			 &lt;&amp;audio_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "sai5_lpcg_mclk",</div><div class='add'>+				     "sai5_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SAI_5&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	amix_lpcg: clock-controller@59c40000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x59c40000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;audio_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-output-names = "amix_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_AMIX&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mqs0_lpcg: clock-controller@59c50000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x59c50000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;acm IMX_ADMA_ACM_MQS_TX_CLK_SEL&gt;,</div><div class='add'>+			 &lt;&amp;audio_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "mqs0_lpcg_mclk",</div><div class='add'>+				     "mqs0_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_MQS_0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi<br/>new file mode 100644<br/>index 000000000000..92752c0c5eb5<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi</a></div><div class='hunk'>@@ -0,0 +1,91 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 NXP</div><div class='add'>+ *	Dong Aisheng &lt;aisheng.dong@nxp.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/firmware/imx/rsrc.h&gt;</div><div class='add'>+</div><div class='add'>+cm40_ipg_clk: clock-cm40-ipg {</div><div class='add'>+	compatible = "fixed-clock";</div><div class='add'>+	#clock-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;132000000&gt;;</div><div class='add'>+	clock-output-names = "cm40_ipg_clk";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+cm40_subsys: bus@34000000 {</div><div class='add'>+	compatible = "simple-bus";</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;1&gt;;</div><div class='add'>+	ranges = &lt;0x34000000 0x0 0x34000000 0x4000000&gt;;</div><div class='add'>+	interrupt-parent = &lt;&amp;cm40_intmux&gt;;</div><div class='add'>+</div><div class='add'>+	cm40_lpuart: serial@37220000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpuart";</div><div class='add'>+		reg = &lt;0x37220000 0x1000&gt;;</div><div class='add'>+		interrupts = &lt;7 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;cm40_uart_lpcg IMX_LPCG_CLK_1&gt;, &lt;&amp;cm40_uart_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-names = "ipg", "baud";</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_M4_0_UART IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;24000000&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_M4_0_UART&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cm40_i2c: i2c@37230000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+		reg = &lt;0x37230000 0x1000&gt;;</div><div class='add'>+		interrupts = &lt;9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;cm40_i2c_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;cm40_i2c_lpcg IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-names = "per", "ipg";</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;24000000&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_M4_0_I2C&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cm40_intmux: intmux@37400000 {</div><div class='add'>+		compatible = "fsl,imx-intmux";</div><div class='add'>+		reg = &lt;0x37400000 0x1000&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		clocks = &lt;&amp;cm40_ipg_clk&gt;;</div><div class='add'>+		clock-names = "ipg";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_M4_0_INTMUX&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cm40_uart_lpcg: clock-controller@37620000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x37620000 0x1000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_M4_0_UART IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;cm40_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_1&gt;;</div><div class='add'>+		clock-output-names = "cm40_lpcg_uart_clk",</div><div class='add'>+				     "cm40_lpcg_uart_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_M4_0_UART&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cm40_i2c_lpcg: clock-controller@37630000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x37630000 0x1000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;cm40_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "cm40_lpcg_i2c_clk",</div><div class='add'>+				     "cm40_lpcg_i2c_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_M4_0_I2C&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-cm41.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-cm41.dtsi<br/>new file mode 100644<br/>index 000000000000..d715f2a6b037<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8-ss-cm41.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8-ss-cm41.dtsi</a></div><div class='hunk'>@@ -0,0 +1,68 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 NXP</div><div class='add'>+ *	Dong Aisheng &lt;aisheng.dong@nxp.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/firmware/imx/rsrc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/imx8-lpcg.h&gt;</div><div class='add'>+</div><div class='add'>+cm41_ipg_clk: clock-cm41-ipg {</div><div class='add'>+	compatible = "fixed-clock";</div><div class='add'>+	#clock-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;132000000&gt;;</div><div class='add'>+	clock-output-names = "cm41_ipg_clk";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+cm41_subsys: bus@38000000 {</div><div class='add'>+	compatible = "simple-bus";</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;1&gt;;</div><div class='add'>+	ranges = &lt;0x38000000 0x0 0x38000000 0x4000000&gt;;</div><div class='add'>+	interrupt-parent = &lt;&amp;cm41_intmux&gt;;</div><div class='add'>+</div><div class='add'>+	cm41_i2c: i2c@3b230000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+		reg = &lt;0x3b230000 0x1000&gt;;</div><div class='add'>+		interrupts = &lt;9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;cm41_i2c_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;cm41_i2c_lpcg IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-names = "per", "ipg";</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_M4_1_I2C IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;24000000&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_M4_1_I2C&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cm41_intmux: intmux@3b400000 {</div><div class='add'>+		compatible = "fsl,imx-intmux";</div><div class='add'>+		reg = &lt;0x3b400000 0x1000&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		clocks = &lt;&amp;cm41_ipg_clk&gt;;</div><div class='add'>+		clock-names = "ipg";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_M4_1_INTMUX&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cm41_i2c_lpcg: clock-controller@3b630000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x3b630000 0x1000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_M4_1_I2C IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;cm41_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "cm41_lpcg_i2c_clk",</div><div class='add'>+				     "cm41_lpcg_i2c_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_M4_1_I2C&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi<br/>new file mode 100644<br/>index 000000000000..176e2e332f87<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi</a></div><div class='hunk'>@@ -0,0 +1,386 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2018-2019 NXP</div><div class='add'>+ *	Dong Aisheng &lt;aisheng.dong@nxp.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/imx8-lpcg.h&gt;</div><div class='add'>+#include &lt;dt-bindings/firmware/imx/rsrc.h&gt;</div><div class='add'>+</div><div class='add'>+conn_axi_clk: clock-conn-axi {</div><div class='add'>+	compatible = "fixed-clock";</div><div class='add'>+	#clock-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;333333333&gt;;</div><div class='add'>+	clock-output-names = "conn_axi_clk";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+conn_ahb_clk: clock-conn-ahb {</div><div class='add'>+	compatible = "fixed-clock";</div><div class='add'>+	#clock-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;166666666&gt;;</div><div class='add'>+	clock-output-names = "conn_ahb_clk";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+conn_ipg_clk: clock-conn-ipg {</div><div class='add'>+	compatible = "fixed-clock";</div><div class='add'>+	#clock-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;83333333&gt;;</div><div class='add'>+	clock-output-names = "conn_ipg_clk";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+conn_bch_clk: clock-conn-bch {</div><div class='add'>+	compatible = "fixed-clock";</div><div class='add'>+	#clock-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;400000000&gt;;</div><div class='add'>+	clock-output-names = "conn_bch_clk";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+conn_subsys: bus@5b000000 {</div><div class='add'>+	compatible = "simple-bus";</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;1&gt;;</div><div class='add'>+	ranges = &lt;0x5b000000 0x0 0x5b000000 0x1000000&gt;;</div><div class='add'>+</div><div class='add'>+	usbotg1: usb@5b0d0000 {</div><div class='add'>+		compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb", "fsl,imx27-usb";</div><div class='add'>+		reg = &lt;0x5b0d0000 0x200&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		fsl,usbphy = &lt;&amp;usbphy1&gt;;</div><div class='add'>+		fsl,usbmisc = &lt;&amp;usbmisc1 0&gt;;</div><div class='add'>+		clocks = &lt;&amp;usb2_lpcg IMX_LPCG_CLK_6&gt;;</div><div class='add'>+		ahb-burst-config = &lt;0x0&gt;;</div><div class='add'>+		tx-burst-size-dword = &lt;0x10&gt;;</div><div class='add'>+		rx-burst-size-dword = &lt;0x10&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_USB_0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usbmisc1: usbmisc@5b0d0200 {</div><div class='add'>+		#index-cells = &lt;1&gt;;</div><div class='add'>+		compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";</div><div class='add'>+		reg = &lt;0x5b0d0200 0x200&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usbphy1: usbphy@5b100000 {</div><div class='add'>+		compatible = "fsl,imx7ulp-usbphy";</div><div class='add'>+		reg = &lt;0x5b100000 0x1000&gt;;</div><div class='add'>+		clocks = &lt;&amp;usb2_lpcg IMX_LPCG_CLK_7&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_USB_0_PHY&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usdhc1: mmc@5b010000 {</div><div class='add'>+		interrupts = &lt;GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		reg = &lt;0x5b010000 0x10000&gt;;</div><div class='add'>+		clocks = &lt;&amp;sdhc0_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;sdhc0_lpcg IMX_LPCG_CLK_5&gt;,</div><div class='add'>+			 &lt;&amp;sdhc0_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-names = "ipg", "ahb", "per";</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SDHC_0&gt;;</div><div class='add'>+		fsl,tuning-start-tap = &lt;20&gt;;</div><div class='add'>+		fsl,tuning-step = &lt;2&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usdhc2: mmc@5b020000 {</div><div class='add'>+		interrupts = &lt;GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		reg = &lt;0x5b020000 0x10000&gt;;</div><div class='add'>+		clocks = &lt;&amp;sdhc1_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;sdhc1_lpcg IMX_LPCG_CLK_5&gt;,</div><div class='add'>+			 &lt;&amp;sdhc1_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-names = "ipg", "ahb", "per";</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;200000000&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SDHC_1&gt;;</div><div class='add'>+		fsl,tuning-start-tap = &lt;20&gt;;</div><div class='add'>+		fsl,tuning-step = &lt;2&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usdhc3: mmc@5b030000 {</div><div class='add'>+		interrupts = &lt;GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		reg = &lt;0x5b030000 0x10000&gt;;</div><div class='add'>+		clocks = &lt;&amp;sdhc2_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;sdhc2_lpcg IMX_LPCG_CLK_5&gt;,</div><div class='add'>+			 &lt;&amp;sdhc2_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-names = "ipg", "ahb", "per";</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;200000000&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SDHC_2&gt;;</div><div class='add'>+		fsl,tuning-start-tap = &lt;20&gt;;</div><div class='add'>+		fsl,tuning-step = &lt;2&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fec1: ethernet@5b040000 {</div><div class='add'>+		reg = &lt;0x5b040000 0x10000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;enet0_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;enet0_lpcg IMX_LPCG_CLK_2&gt;,</div><div class='add'>+			 &lt;&amp;enet0_lpcg IMX_LPCG_CLK_3&gt;,</div><div class='add'>+			 &lt;&amp;enet0_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;enet0_lpcg IMX_LPCG_CLK_1&gt;;</div><div class='add'>+		clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk";</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+				  &lt;&amp;clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;250000000&gt;, &lt;125000000&gt;;</div><div class='add'>+		fsl,num-tx-queues = &lt;3&gt;;</div><div class='add'>+		fsl,num-rx-queues = &lt;3&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_ENET_0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fec2: ethernet@5b050000 {</div><div class='add'>+		reg = &lt;0x5b050000 0x10000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;enet1_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;enet1_lpcg IMX_LPCG_CLK_2&gt;,</div><div class='add'>+			 &lt;&amp;enet1_lpcg IMX_LPCG_CLK_3&gt;,</div><div class='add'>+			 &lt;&amp;enet1_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;enet0_lpcg IMX_LPCG_CLK_1&gt;;</div><div class='add'>+		clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk";</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+				  &lt;&amp;clk IMX_SC_R_ENET_1 IMX_SC_C_CLKDIV&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;250000000&gt;, &lt;125000000&gt;;</div><div class='add'>+		fsl,num-tx-queues = &lt;3&gt;;</div><div class='add'>+		fsl,num-rx-queues = &lt;3&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_ENET_1&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usbotg3: usb@5b110000 {</div><div class='add'>+		compatible = "fsl,imx8qm-usb3";</div><div class='add'>+		reg = &lt;0x5b110000 0x10000&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+		clocks = &lt;&amp;usb3_lpcg IMX_LPCG_CLK_1&gt;,</div><div class='add'>+			 &lt;&amp;usb3_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;usb3_lpcg IMX_LPCG_CLK_7&gt;,</div><div class='add'>+			 &lt;&amp;usb3_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;usb3_lpcg IMX_LPCG_CLK_5&gt;;</div><div class='add'>+		clock-names = "lpm", "bus", "aclk", "ipg", "core";</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;250000000&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_USB_2&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+</div><div class='add'>+		usbotg3_cdns3: usb@5b120000 {</div><div class='add'>+			compatible = "cdns,usb3";</div><div class='add'>+			reg = &lt;0x5b120000 0x10000&gt;,   /* memory area for OTG/DRD registers */</div><div class='add'>+			      &lt;0x5b130000 0x10000&gt;,   /* memory area for HOST registers */</div><div class='add'>+			      &lt;0x5b140000 0x10000&gt;;   /* memory area for DEVICE registers */</div><div class='add'>+			reg-names = "otg", "xhci", "dev";</div><div class='add'>+			interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "host", "peripheral", "otg", "wakeup";</div><div class='add'>+			phys = &lt;&amp;usb3_phy&gt;;</div><div class='add'>+			phy-names = "cdns3,usb3-phy";</div><div class='add'>+			cdns,on-chip-buff-size = /bits/ 16 &lt;18&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb3_phy: usb-phy@5b160000 {</div><div class='add'>+		compatible = "nxp,salvo-phy";</div><div class='add'>+		reg = &lt;0x5b160000 0x40000&gt;;</div><div class='add'>+		clocks = &lt;&amp;usb3_lpcg IMX_LPCG_CLK_6&gt;;</div><div class='add'>+		clock-names = "salvo_phy_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_USB_2_PHY&gt;;</div><div class='add'>+		#phy-cells = &lt;0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* LPCG clocks */</div><div class='add'>+	sdhc0_lpcg: clock-controller@5b200000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5b200000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;conn_ipg_clk&gt;, &lt;&amp;conn_axi_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_4&gt;,</div><div class='add'>+				&lt;IMX_LPCG_CLK_5&gt;;</div><div class='add'>+		clock-output-names = "sdhc0_lpcg_per_clk",</div><div class='add'>+				     "sdhc0_lpcg_ipg_clk",</div><div class='add'>+				     "sdhc0_lpcg_ahb_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SDHC_0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdhc1_lpcg: clock-controller@5b210000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5b210000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;conn_ipg_clk&gt;, &lt;&amp;conn_axi_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_4&gt;,</div><div class='add'>+				&lt;IMX_LPCG_CLK_5&gt;;</div><div class='add'>+		clock-output-names = "sdhc1_lpcg_per_clk",</div><div class='add'>+				     "sdhc1_lpcg_ipg_clk",</div><div class='add'>+				     "sdhc1_lpcg_ahb_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SDHC_1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdhc2_lpcg: clock-controller@5b220000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5b220000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;conn_ipg_clk&gt;, &lt;&amp;conn_axi_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_4&gt;,</div><div class='add'>+				&lt;IMX_LPCG_CLK_5&gt;;</div><div class='add'>+		clock-output-names = "sdhc2_lpcg_per_clk",</div><div class='add'>+				     "sdhc2_lpcg_ipg_clk",</div><div class='add'>+				     "sdhc2_lpcg_ahb_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SDHC_2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	enet0_lpcg: clock-controller@5b230000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5b230000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;conn_axi_clk&gt;,</div><div class='add'>+			 &lt;&amp;clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK&gt;,</div><div class='add'>+			 &lt;&amp;conn_ipg_clk&gt;,</div><div class='add'>+			 &lt;&amp;conn_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_1&gt;,</div><div class='add'>+				&lt;IMX_LPCG_CLK_2&gt;, &lt;IMX_LPCG_CLK_3&gt;,</div><div class='add'>+				&lt;IMX_LPCG_CLK_4&gt;, &lt;IMX_LPCG_CLK_5&gt;;</div><div class='add'>+		clock-output-names = "enet0_lpcg_timer_clk",</div><div class='add'>+				     "enet0_lpcg_txc_sampling_clk",</div><div class='add'>+				     "enet0_lpcg_ahb_clk",</div><div class='add'>+				     "enet0_lpcg_rgmii_txc_clk",</div><div class='add'>+				     "enet0_lpcg_ipg_clk",</div><div class='add'>+				     "enet0_lpcg_ipg_s_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_ENET_0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	enet1_lpcg: clock-controller@5b240000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5b240000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;conn_axi_clk&gt;,</div><div class='add'>+			 &lt;&amp;clk IMX_SC_R_ENET_1 IMX_SC_C_TXCLK&gt;,</div><div class='add'>+			 &lt;&amp;conn_ipg_clk&gt;,</div><div class='add'>+			 &lt;&amp;conn_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_1&gt;,</div><div class='add'>+				&lt;IMX_LPCG_CLK_2&gt;, &lt;IMX_LPCG_CLK_3&gt;,</div><div class='add'>+				&lt;IMX_LPCG_CLK_4&gt;, &lt;IMX_LPCG_CLK_5&gt;;</div><div class='add'>+		clock-output-names = "enet1_lpcg_timer_clk",</div><div class='add'>+				     "enet1_lpcg_txc_sampling_clk",</div><div class='add'>+				     "enet1_lpcg_ahb_clk",</div><div class='add'>+				     "enet1_lpcg_rgmii_txc_clk",</div><div class='add'>+				     "enet1_lpcg_ipg_clk",</div><div class='add'>+				     "enet1_lpcg_ipg_s_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_ENET_1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb2_lpcg: clock-controller@5b270000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5b270000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;conn_ahb_clk&gt;, &lt;&amp;conn_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_6&gt;, &lt;IMX_LPCG_CLK_7&gt;;</div><div class='add'>+		clock-output-names = "usboh3_ahb_clk", "usboh3_phy_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_USB_0_PHY&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb3_lpcg: clock-controller@5b280000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5b280000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_1&gt;,</div><div class='add'>+				&lt;IMX_LPCG_CLK_4&gt;, &lt;IMX_LPCG_CLK_5&gt;,</div><div class='add'>+				&lt;IMX_LPCG_CLK_6&gt;, &lt;IMX_LPCG_CLK_7&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MISC&gt;,</div><div class='add'>+			 &lt;&amp;conn_ipg_clk&gt;,</div><div class='add'>+			 &lt;&amp;conn_ipg_clk&gt;,</div><div class='add'>+			 &lt;&amp;conn_ipg_clk&gt;,</div><div class='add'>+			 &lt;&amp;clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS&gt;;</div><div class='add'>+		clock-output-names = "usb3_app_clk",</div><div class='add'>+				     "usb3_lpm_clk",</div><div class='add'>+				     "usb3_ipg_clk",</div><div class='add'>+				     "usb3_core_pclk",</div><div class='add'>+				     "usb3_phy_clk",</div><div class='add'>+				     "usb3_aclk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_USB_2_PHY&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rawnand_0_lpcg: clock-controller@5b290000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5b290000 0x4&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_NAND IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;clk IMX_SC_R_NAND IMX_SC_PM_CLK_MST_BUS&gt;,</div><div class='add'>+			 &lt;&amp;conn_axi_clk&gt;,</div><div class='add'>+			 &lt;&amp;conn_axi_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_1&gt;,</div><div class='add'>+				&lt;IMX_LPCG_CLK_4&gt;, &lt;IMX_LPCG_CLK_5&gt;;</div><div class='add'>+		clock-output-names = "gpmi_bch",</div><div class='add'>+				     "gpmi_io",</div><div class='add'>+				     "gpmi_apb",</div><div class='add'>+				     "gpmi_bch_apb";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_NAND&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rawnand_4_lpcg: clock-controller@5b290004 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5b290004 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;conn_axi_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "apbhdma_hclk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_NAND&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dma_apbh: dma-controller@5b810000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-dma-apbh", "fsl,imx28-dma-apbh";</div><div class='add'>+		reg = &lt;0x5b810000 0x2000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		#dma-cells = &lt;1&gt;;</div><div class='add'>+		dma-channels = &lt;4&gt;;</div><div class='add'>+		clocks = &lt;&amp;rawnand_4_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_NAND&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpmi: nand-controller@5b812000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-gpmi-nand";</div><div class='add'>+		reg = &lt;0x5b812000 0x2000&gt;, &lt;0x5b814000 0x2000&gt;;</div><div class='add'>+		reg-names = "gpmi-nand", "bch";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-names = "bch";</div><div class='add'>+		clocks = &lt;&amp;rawnand_0_lpcg IMX_LPCG_CLK_1&gt;,</div><div class='add'>+			 &lt;&amp;rawnand_0_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;rawnand_0_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;rawnand_0_lpcg IMX_LPCG_CLK_5&gt;;</div><div class='add'>+		clock-names = "gpmi_io", "gpmi_apb",</div><div class='add'>+			      "gpmi_bch", "gpmi_bch_apb";</div><div class='add'>+		dmas = &lt;&amp;dma_apbh 0&gt;;</div><div class='add'>+		dma-names = "rx-tx";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_NAND&gt;;</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_NAND IMX_SC_PM_CLK_MST_BUS&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;50000000&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi<br/>new file mode 100644<br/>index 000000000000..7d5183c6c5be<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi</a></div><div class='hunk'>@@ -0,0 +1,18 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2019-2020 NXP</div><div class='add'>+ *	Dong Aisheng &lt;aisheng.dong@nxp.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+ddr_subsys: bus@5c000000 {</div><div class='add'>+	compatible = "simple-bus";</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;1&gt;;</div><div class='add'>+	ranges = &lt;0x5c000000 0x0 0x5c000000 0x1000000&gt;;</div><div class='add'>+</div><div class='add'>+	ddr_pmu0: ddr-pmu@5c020000 {</div><div class='add'>+		compatible = "fsl,imx8-ddr-pmu";</div><div class='add'>+		reg = &lt;0x5c020000 0x10000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi<br/>new file mode 100644<br/>index 000000000000..4de78f870c05<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi</a></div><div class='hunk'>@@ -0,0 +1,566 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2018-2019 NXP</div><div class='add'>+ *	Dong Aisheng &lt;aisheng.dong@nxp.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/imx8-lpcg.h&gt;</div><div class='add'>+#include &lt;dt-bindings/dma/fsl-edma.h&gt;</div><div class='add'>+#include &lt;dt-bindings/firmware/imx/rsrc.h&gt;</div><div class='add'>+</div><div class='add'>+dma_ipg_clk: clock-dma-ipg {</div><div class='add'>+	compatible = "fixed-clock";</div><div class='add'>+	#clock-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;120000000&gt;;</div><div class='add'>+	clock-output-names = "dma_ipg_clk";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+dma_subsys: bus@5a000000 {</div><div class='add'>+	compatible = "simple-bus";</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;1&gt;;</div><div class='add'>+	ranges = &lt;0x5a000000 0x0 0x5a000000 0x1000000&gt;;</div><div class='add'>+</div><div class='add'>+	lpspi0: spi@5a000000 {</div><div class='add'>+		compatible = "fsl,imx7ulp-spi";</div><div class='add'>+		reg = &lt;0x5a000000 0x10000&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		clocks = &lt;&amp;spi0_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;spi0_lpcg IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-names = "per", "ipg";</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;60000000&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SPI_0&gt;;</div><div class='add'>+		dmas = &lt;&amp;edma2 1 0 0&gt;, &lt;&amp;edma2 0 0 FSL_EDMA_RX&gt;;</div><div class='add'>+		dma-names = "tx", "rx";</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lpspi1: spi@5a010000 {</div><div class='add'>+		compatible = "fsl,imx7ulp-spi";</div><div class='add'>+		reg = &lt;0x5a010000 0x10000&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		clocks = &lt;&amp;spi1_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;spi1_lpcg IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-names = "per", "ipg";</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;60000000&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SPI_1&gt;;</div><div class='add'>+		dmas = &lt;&amp;edma2 3 0 0&gt;, &lt;&amp;edma2 2 0 FSL_EDMA_RX&gt;;</div><div class='add'>+		dma-names = "tx", "rx";</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lpspi2: spi@5a020000 {</div><div class='add'>+		compatible = "fsl,imx7ulp-spi";</div><div class='add'>+		reg = &lt;0x5a020000 0x10000&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		clocks = &lt;&amp;spi2_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;spi2_lpcg IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-names = "per", "ipg";</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;60000000&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SPI_2&gt;;</div><div class='add'>+		dmas = &lt;&amp;edma2 5 0 0&gt;, &lt;&amp;edma2 4 0 FSL_EDMA_RX&gt;;</div><div class='add'>+		dma-names = "tx", "rx";</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lpspi3: spi@5a030000 {</div><div class='add'>+		compatible = "fsl,imx7ulp-spi";</div><div class='add'>+		reg = &lt;0x5a030000 0x10000&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		clocks = &lt;&amp;spi3_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;spi3_lpcg IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-names = "per", "ipg";</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;60000000&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SPI_3&gt;;</div><div class='add'>+		dmas = &lt;&amp;edma2 7 0 0&gt;, &lt;&amp;edma2 6 0 FSL_EDMA_RX&gt;;</div><div class='add'>+		dma-names = "tx", "rx";</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lpuart0: serial@5a060000 {</div><div class='add'>+		reg = &lt;0x5a060000 0x1000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;uart0_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;uart0_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-names = "ipg", "baud";</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;80000000&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_UART_0&gt;;</div><div class='add'>+		dma-names = "rx", "tx";</div><div class='add'>+		dmas = &lt;&amp;edma2 8 0 FSL_EDMA_RX&gt;, &lt;&amp;edma2 9 0 0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lpuart1: serial@5a070000 {</div><div class='add'>+		reg = &lt;0x5a070000 0x1000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;uart1_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;uart1_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-names = "ipg", "baud";</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;80000000&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_UART_1&gt;;</div><div class='add'>+		dma-names = "rx", "tx";</div><div class='add'>+		dmas = &lt;&amp;edma2 10 0 FSL_EDMA_RX&gt;, &lt;&amp;edma2 11 0 0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lpuart2: serial@5a080000 {</div><div class='add'>+		reg = &lt;0x5a080000 0x1000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;uart2_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;uart2_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-names = "ipg", "baud";</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;80000000&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_UART_2&gt;;</div><div class='add'>+		dma-names = "rx", "tx";</div><div class='add'>+		dmas = &lt;&amp;edma2 12 0 FSL_EDMA_RX&gt;, &lt;&amp;edma2 13 0 0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lpuart3: serial@5a090000 {</div><div class='add'>+		reg = &lt;0x5a090000 0x1000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;uart3_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;uart3_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-names = "ipg", "baud";</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;80000000&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_UART_3&gt;;</div><div class='add'>+		dma-names = "rx", "tx";</div><div class='add'>+		dmas = &lt;&amp;edma2 14 0 FSL_EDMA_RX&gt;, &lt;&amp;edma2 15 0 0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	adma_pwm: pwm@5a190000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";</div><div class='add'>+		reg = &lt;0x5a190000 0x1000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;adma_pwm_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;adma_pwm_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-names = "ipg", "per";</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;24000000&gt;;</div><div class='add'>+		#pwm-cells = &lt;3&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_LCD_0_PWM_0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	edma2: dma-controller@5a1f0000 {</div><div class='add'>+		compatible = "fsl,imx8qm-edma";</div><div class='add'>+		reg = &lt;0x5a1f0000 0x170000&gt;;</div><div class='add'>+		#dma-cells = &lt;3&gt;;</div><div class='add'>+		dma-channels = &lt;16&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_DMA_2_CH0&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_2_CH1&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_2_CH2&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_2_CH3&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_2_CH4&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_2_CH5&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_2_CH6&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_2_CH7&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_2_CH8&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_2_CH9&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_2_CH10&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_2_CH11&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_2_CH12&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_2_CH13&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_2_CH14&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_2_CH15&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi0_lpcg: clock-controller@5a400000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5a400000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;dma_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "spi0_lpcg_clk",</div><div class='add'>+				     "spi0_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SPI_0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi1_lpcg: clock-controller@5a410000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5a410000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;dma_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "spi1_lpcg_clk",</div><div class='add'>+				     "spi1_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SPI_1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi2_lpcg: clock-controller@5a420000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5a420000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;dma_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "spi2_lpcg_clk",</div><div class='add'>+				     "spi2_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SPI_2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi3_lpcg: clock-controller@5a430000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5a430000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;dma_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "spi3_lpcg_clk",</div><div class='add'>+				     "spi3_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SPI_3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart0_lpcg: clock-controller@5a460000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5a460000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;dma_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "uart0_lpcg_baud_clk",</div><div class='add'>+				     "uart0_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_UART_0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart1_lpcg: clock-controller@5a470000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5a470000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;dma_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "uart1_lpcg_baud_clk",</div><div class='add'>+				     "uart1_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_UART_1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart2_lpcg: clock-controller@5a480000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5a480000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;dma_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "uart2_lpcg_baud_clk",</div><div class='add'>+				     "uart2_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_UART_2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart3_lpcg: clock-controller@5a490000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5a490000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;dma_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "uart3_lpcg_baud_clk",</div><div class='add'>+				     "uart3_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_UART_3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	adma_pwm_lpcg: clock-controller@5a590000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5a590000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;dma_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "adma_pwm_lpcg_clk",</div><div class='add'>+				     "adma_pwm_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_LCD_0_PWM_0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c0: i2c@5a800000 {</div><div class='add'>+		reg = &lt;0x5a800000 0x4000&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;i2c0_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;i2c0_lpcg IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-names = "per", "ipg";</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;24000000&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_I2C_0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c1: i2c@5a810000 {</div><div class='add'>+		reg = &lt;0x5a810000 0x4000&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;i2c1_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;i2c1_lpcg IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-names = "per", "ipg";</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;24000000&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_I2C_1&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c2: i2c@5a820000 {</div><div class='add'>+		reg = &lt;0x5a820000 0x4000&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;i2c2_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;i2c2_lpcg IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-names = "per", "ipg";</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;24000000&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_I2C_2&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c3: i2c@5a830000 {</div><div class='add'>+		reg = &lt;0x5a830000 0x4000&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;i2c3_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;i2c3_lpcg IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-names = "per", "ipg";</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;24000000&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_I2C_3&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	adc0: adc@5a880000 {</div><div class='add'>+		compatible = "nxp,imx8qxp-adc";</div><div class='add'>+		#io-channel-cells = &lt;1&gt;;</div><div class='add'>+		reg = &lt;0x5a880000 0x10000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		clocks = &lt;&amp;adc0_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;adc0_lpcg IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-names = "per", "ipg";</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;24000000&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_ADC_0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	adc1: adc@5a890000 {</div><div class='add'>+		compatible = "nxp,imx8qxp-adc";</div><div class='add'>+		#io-channel-cells = &lt;1&gt;;</div><div class='add'>+		reg = &lt;0x5a890000 0x10000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		clocks = &lt;&amp;adc1_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;adc1_lpcg IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-names = "per", "ipg";</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;24000000&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_ADC_1&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	flexcan1: can@5a8d0000 {</div><div class='add'>+		compatible = "fsl,imx8qm-flexcan";</div><div class='add'>+		reg = &lt;0x5a8d0000 0x10000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		clocks = &lt;&amp;can0_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;can0_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-names = "ipg", "per";</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;40000000&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_CAN_0&gt;;</div><div class='add'>+		/* SLSlice[4] */</div><div class='add'>+		fsl,clk-source = /bits/ 8 &lt;0&gt;;</div><div class='add'>+		fsl,scu-index = /bits/ 8 &lt;0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	flexcan2: can@5a8e0000 {</div><div class='add'>+		compatible = "fsl,imx8qm-flexcan";</div><div class='add'>+		reg = &lt;0x5a8e0000 0x10000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		/* CAN0 clock and PD is shared among all CAN instances as</div><div class='add'>+		 * CAN1 shares CAN0's clock and to enable CAN0's clock it</div><div class='add'>+		 * has to be powered on.</div><div class='add'>+		 */</div><div class='add'>+		clocks = &lt;&amp;can0_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;can0_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-names = "ipg", "per";</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;40000000&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_CAN_1&gt;;</div><div class='add'>+		/* SLSlice[4] */</div><div class='add'>+		fsl,clk-source = /bits/ 8 &lt;0&gt;;</div><div class='add'>+		fsl,scu-index = /bits/ 8 &lt;1&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	flexcan3: can@5a8f0000 {</div><div class='add'>+		compatible = "fsl,imx8qm-flexcan";</div><div class='add'>+		reg = &lt;0x5a8f0000 0x10000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		/* CAN0 clock and PD is shared among all CAN instances as</div><div class='add'>+		 * CAN2 shares CAN0's clock and to enable CAN0's clock it</div><div class='add'>+		 * has to be powered on.</div><div class='add'>+		 */</div><div class='add'>+		clocks = &lt;&amp;can0_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;can0_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-names = "ipg", "per";</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;40000000&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_CAN_2&gt;;</div><div class='add'>+		/* SLSlice[4] */</div><div class='add'>+		fsl,clk-source = /bits/ 8 &lt;0&gt;;</div><div class='add'>+		fsl,scu-index = /bits/ 8 &lt;2&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	edma3: dma-controller@5a9f0000 {</div><div class='add'>+		compatible = "fsl,imx8qm-edma";</div><div class='add'>+		reg = &lt;0x5a9f0000 0x90000&gt;;</div><div class='add'>+		#dma-cells = &lt;3&gt;;</div><div class='add'>+		dma-channels = &lt;8&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_DMA_3_CH0&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_3_CH1&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_3_CH2&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_3_CH3&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_3_CH4&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_3_CH5&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_3_CH6&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_DMA_3_CH7&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c0_lpcg: clock-controller@5ac00000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5ac00000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;dma_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "i2c0_lpcg_clk",</div><div class='add'>+				     "i2c0_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_I2C_0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c1_lpcg: clock-controller@5ac10000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5ac10000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;dma_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "i2c1_lpcg_clk",</div><div class='add'>+				     "i2c1_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_I2C_1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c2_lpcg: clock-controller@5ac20000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5ac20000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;dma_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "i2c2_lpcg_clk",</div><div class='add'>+				     "i2c2_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_I2C_2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c3_lpcg: clock-controller@5ac30000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5ac30000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;dma_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "i2c3_lpcg_clk",</div><div class='add'>+				     "i2c3_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_I2C_3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	adc0_lpcg: clock-controller@5ac80000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5ac80000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;dma_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "adc0_lpcg_clk",</div><div class='add'>+				     "adc0_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_ADC_0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	adc1_lpcg: clock-controller@5ac90000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5ac90000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;dma_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "adc1_lpcg_clk",</div><div class='add'>+				     "adc1_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_ADC_1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	can0_lpcg: clock-controller@5acd0000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5acd0000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;dma_ipg_clk&gt;, &lt;&amp;dma_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_4&gt;, &lt;IMX_LPCG_CLK_5&gt;;</div><div class='add'>+		clock-output-names = "can0_lpcg_pe_clk",</div><div class='add'>+				     "can0_lpcg_ipg_clk",</div><div class='add'>+				     "can0_lpcg_chi_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_CAN_0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-gpu0.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-gpu0.dtsi<br/>new file mode 100644<br/>index 000000000000..9b8a44aa63d6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8-ss-gpu0.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8-ss-gpu0.dtsi</a></div><div class='hunk'>@@ -0,0 +1,27 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2019 NXP</div><div class='add'>+ *	Dong Aisheng &lt;aisheng.dong@nxp.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/firmware/imx/rsrc.h&gt;</div><div class='add'>+</div><div class='add'>+gpu0_subsys: bus@53000000 {</div><div class='add'>+	compatible = "simple-bus";</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;1&gt;;</div><div class='add'>+	ranges = &lt;0x53000000 0x0 0x53000000 0x1000000&gt;;</div><div class='add'>+</div><div class='add'>+	gpu_3d0: gpu@53100000 {</div><div class='add'>+		compatible = "vivante,gc";</div><div class='add'>+		reg = &lt;0x53100000 0x40000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC&gt;;</div><div class='add'>+		clock-names = "core", "shader";</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+				  &lt;&amp;clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;700000000&gt;, &lt;850000000&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_GPU_0_PID0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi<br/>new file mode 100644<br/>index 000000000000..469de8b536b5<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi</a></div><div class='hunk'>@@ -0,0 +1,143 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 NXP</div><div class='add'>+ *</div><div class='add'>+ * Richard Zhu &lt;hongxing.zhu@nxp.com&gt;</div><div class='add'>+ */</div><div class='add'>+#include &lt;dt-bindings/phy/phy.h&gt;</div><div class='add'>+</div><div class='add'>+hsio_axi_clk: clock-hsio-axi {</div><div class='add'>+	compatible = "fixed-clock";</div><div class='add'>+	#clock-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;400000000&gt;;</div><div class='add'>+	clock-output-names = "hsio_axi_clk";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+hsio_per_clk: clock-hsio-per {</div><div class='add'>+	compatible = "fixed-clock";</div><div class='add'>+	#clock-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;133333333&gt;;</div><div class='add'>+	clock-output-names = "hsio_per_clk";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+hsio_refa_clk: clock-hsio-refa {</div><div class='add'>+	compatible = "gpio-gate-clock";</div><div class='add'>+	clocks = &lt;&amp;xtal100m&gt;;</div><div class='add'>+	#clock-cells = &lt;0&gt;;</div><div class='add'>+	enable-gpios = &lt;&amp;lsio_gpio4 27 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+hsio_refb_clk: clock-hsio-refb {</div><div class='add'>+	compatible = "gpio-gate-clock";</div><div class='add'>+	clocks = &lt;&amp;xtal100m&gt;;</div><div class='add'>+	#clock-cells = &lt;0&gt;;</div><div class='add'>+	enable-gpios = &lt;&amp;lsio_gpio4 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+xtal100m: clock-xtal100m {</div><div class='add'>+	compatible = "fixed-clock";</div><div class='add'>+	#clock-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;100000000&gt;;</div><div class='add'>+	clock-output-names = "xtal_100MHz";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+hsio_subsys: bus@5f000000 {</div><div class='add'>+	compatible = "simple-bus";</div><div class='add'>+	ranges = &lt;0x5f000000 0x0 0x5f000000 0x01000000&gt;,</div><div class='add'>+		 &lt;0x80000000 0x0 0x70000000 0x10000000&gt;;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;1&gt;;</div><div class='add'>+	dma-ranges = &lt;0x80000000 0 0x80000000 0x80000000&gt;;</div><div class='add'>+</div><div class='add'>+	pcieb: pcie@5f010000 {</div><div class='add'>+		compatible = "fsl,imx8q-pcie";</div><div class='add'>+		reg = &lt;0x5f010000 0x10000&gt;,</div><div class='add'>+		      &lt;0x8ff00000 0x80000&gt;;</div><div class='add'>+		reg-names = "dbi", "config";</div><div class='add'>+		ranges = &lt;0x81000000 0 0x00000000 0x8ff80000 0 0x00010000&gt;,</div><div class='add'>+			 &lt;0x82000000 0 0x80000000 0x80000000 0 0x0ff00000&gt;;</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-names = "msi", "dma";</div><div class='add'>+		#address-cells = &lt;3&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		clocks = &lt;&amp;pcieb_lpcg IMX_LPCG_CLK_6&gt;,</div><div class='add'>+			 &lt;&amp;pcieb_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;pcieb_lpcg IMX_LPCG_CLK_5&gt;;</div><div class='add'>+		clock-names = "dbi", "mstr", "slv";</div><div class='add'>+		bus-range = &lt;0x00 0xff&gt;;</div><div class='add'>+		device_type = "pci";</div><div class='add'>+		interrupt-map = &lt;0 0 0 1 &amp;gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 0 2 &amp;gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 0 3 &amp;gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 0 4 &amp;gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-map-mask = &lt;0 0 0 0x7&gt;;</div><div class='add'>+		num-lanes = &lt;1&gt;;</div><div class='add'>+		num-viewport = &lt;4&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_PCIE_B&gt;;</div><div class='add'>+		fsl,max-link-speed = &lt;3&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcieb_ep: pcie-ep@5f010000 {</div><div class='add'>+		compatible = "fsl,imx8q-pcie-ep";</div><div class='add'>+		reg = &lt;0x5f010000 0x00010000&gt;,</div><div class='add'>+		      &lt;0x80000000 0x10000000&gt;;</div><div class='add'>+		reg-names = "dbi", "addr_space";</div><div class='add'>+		num-lanes = &lt;1&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-names = "dma";</div><div class='add'>+		clocks = &lt;&amp;pcieb_lpcg IMX_LPCG_CLK_6&gt;,</div><div class='add'>+			 &lt;&amp;pcieb_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;pcieb_lpcg IMX_LPCG_CLK_5&gt;;</div><div class='add'>+		clock-names = "dbi", "mstr", "slv";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_PCIE_B&gt;;</div><div class='add'>+		fsl,max-link-speed = &lt;3&gt;;</div><div class='add'>+		num-ib-windows = &lt;6&gt;;</div><div class='add'>+		num-ob-windows = &lt;6&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcieb_lpcg: clock-controller@5f060000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5f060000 0x10000&gt;;</div><div class='add'>+		clocks = &lt;&amp;hsio_axi_clk&gt;, &lt;&amp;hsio_axi_clk&gt;, &lt;&amp;hsio_axi_clk&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_4&gt;, &lt;IMX_LPCG_CLK_5&gt;, &lt;IMX_LPCG_CLK_6&gt;;</div><div class='add'>+		clock-output-names = "hsio_pcieb_mstr_axi_clk",</div><div class='add'>+				     "hsio_pcieb_slv_axi_clk",</div><div class='add'>+				     "hsio_pcieb_dbi_axi_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_PCIE_B&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	phyx1_crr1_lpcg: clock-controller@5f0b0000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5f0b0000 0x10000&gt;;</div><div class='add'>+		clocks = &lt;&amp;hsio_per_clk&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "hsio_phyx1_per_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SERDES_1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcieb_crr3_lpcg: clock-controller@5f0d0000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5f0d0000 0x10000&gt;;</div><div class='add'>+		clocks = &lt;&amp;hsio_per_clk&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "hsio_pcieb_per_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_PCIE_B&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	misc_crr5_lpcg: clock-controller@5f0f0000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5f0f0000 0x10000&gt;;</div><div class='add'>+		clocks = &lt;&amp;hsio_per_clk&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "hsio_misc_per_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_HSIO_GPIO&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi<br/>new file mode 100644<br/>index 000000000000..a72b2f1c4a1b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi</a></div><div class='hunk'>@@ -0,0 +1,426 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2019-2021 NXP</div><div class='add'>+ * Zhou Guoniu &lt;guoniu.zhou@nxp.com&gt;</div><div class='add'>+ */</div><div class='add'>+img_ipg_clk: clock-img-ipg {</div><div class='add'>+	compatible = "fixed-clock";</div><div class='add'>+	#clock-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;200000000&gt;;</div><div class='add'>+	clock-output-names = "img_ipg_clk";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+img_pxl_clk: clock-img-pxl {</div><div class='add'>+	compatible = "fixed-clock";</div><div class='add'>+	#clock-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;600000000&gt;;</div><div class='add'>+	clock-output-names = "img_pxl_clk";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+img_subsys: bus@58000000 {</div><div class='add'>+	compatible = "simple-bus";</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;1&gt;;</div><div class='add'>+	ranges = &lt;0x58000000 0x0 0x58000000 0x1000000&gt;;</div><div class='add'>+</div><div class='add'>+	isi: isi@58100000 {</div><div class='add'>+		reg = &lt;0x58100000 0x80000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;pdma0_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;pdma1_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;pdma2_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;pdma3_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;pdma4_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;pdma5_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;pdma6_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;pdma7_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-names = "per0", "per1", "per2", "per3",</div><div class='add'>+			      "per4", "per5", "per6", "per7";</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_ISI_CH0&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_ISI_CH1&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_ISI_CH2&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_ISI_CH3&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_ISI_CH4&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_ISI_CH5&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_ISI_CH6&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_ISI_CH7&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	irqsteer_csi0: irqsteer@58220000 {</div><div class='add'>+		compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";</div><div class='add'>+		reg = &lt;0x58220000 0x1000&gt;;</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		interrupts = &lt;GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;img_ipg_clk&gt;;</div><div class='add'>+		clock-names = "ipg";</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_CSI_0&gt;;</div><div class='add'>+		fsl,channel = &lt;0&gt;;</div><div class='add'>+		fsl,num-irqs = &lt;32&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio0_mipi_csi0: gpio@58222000 {</div><div class='add'>+		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";</div><div class='add'>+		reg = &lt;0x58222000 0x1000&gt;;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		interrupts = &lt;0&gt;;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		interrupt-parent = &lt;&amp;irqsteer_csi0&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_CSI_0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	csi0_core_lpcg: clock-controller@58223018 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x58223018 0x4&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_CSI_0 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "csi0_lpcg_core_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_ISI_CH0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	csi0_esc_lpcg: clock-controller@5822301c {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5822301c 0x4&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_CSI_0 IMX_SC_PM_CLK_MISC&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "csi0_lpcg_esc_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_ISI_CH0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c_mipi_csi0: i2c@58226000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+		reg = &lt;0x58226000 0x1000&gt;;</div><div class='add'>+		interrupts = &lt;8&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_CSI_0_I2C_0 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;img_ipg_clk&gt;;</div><div class='add'>+		clock-names = "per", "ipg";</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_CSI_0_I2C_0 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;24000000&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;irqsteer_csi0&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_CSI_0_I2C_0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mipi_csi_0: csi@58227000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-mipi-csi2";</div><div class='add'>+		reg = &lt;0x58227000 0x1000&gt;,</div><div class='add'>+		      &lt;0x58221000 0x1000&gt;;</div><div class='add'>+		clocks = &lt;&amp;csi0_core_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;csi0_esc_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;csi0_pxl_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-names = "core", "esc", "ui";</div><div class='add'>+		assigned-clocks = &lt;&amp;csi0_core_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+				  &lt;&amp;csi0_esc_lpcg IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;360000000&gt;, &lt;72000000&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_ISI_CH0&gt;;</div><div class='add'>+		resets = &lt;&amp;scu_reset IMX_SC_R_CSI_0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	irqsteer_csi1: irqsteer@58240000 {</div><div class='add'>+		compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";</div><div class='add'>+		reg = &lt;0x58240000 0x1000&gt;;</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		interrupts = &lt;GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;img_ipg_clk&gt;;</div><div class='add'>+		clock-names = "ipg";</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_CSI_1&gt;;</div><div class='add'>+		fsl,channel = &lt;0&gt;;</div><div class='add'>+		fsl,num-irqs = &lt;32&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio0_mipi_csi1: gpio@58242000 {</div><div class='add'>+		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";</div><div class='add'>+		reg = &lt;0x58242000 0x1000&gt;;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		interrupts = &lt;0&gt;;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		interrupt-parent = &lt;&amp;irqsteer_csi1&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_CSI_1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	csi1_core_lpcg: clock-controller@58243018 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x58243018 0x4&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_CSI_1 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "csi1_lpcg_core_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_ISI_CH0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	csi1_esc_lpcg: clock-controller@5824301c {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5824301c 0x4&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_CSI_1 IMX_SC_PM_CLK_MISC&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "csi1_lpcg_esc_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_ISI_CH0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c_mipi_csi1: i2c@58246000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+		reg = &lt;0x58246000 0x1000&gt;;</div><div class='add'>+		interrupts = &lt;8&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_CSI_1_I2C_0 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;img_ipg_clk&gt;;</div><div class='add'>+		clock-names = "per", "ipg";</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_CSI_1_I2C_0 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;24000000&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;irqsteer_csi1&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_CSI_1_I2C_0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mipi_csi_1: csi@58247000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-mipi-csi2";</div><div class='add'>+		reg = &lt;0x58247000 0x1000&gt;,</div><div class='add'>+		      &lt;0x58241000 0x1000&gt;;</div><div class='add'>+		clocks = &lt;&amp;csi1_core_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;csi1_esc_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;csi1_pxl_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-names = "core", "esc", "ui";</div><div class='add'>+		assigned-clocks = &lt;&amp;csi1_core_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+				  &lt;&amp;csi1_esc_lpcg IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;360000000&gt;, &lt;72000000&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_ISI_CH0&gt;;</div><div class='add'>+		resets = &lt;&amp;scu_reset IMX_SC_R_CSI_1&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	irqsteer_parallel: irqsteer@58260000 {</div><div class='add'>+		compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";</div><div class='add'>+		reg = &lt;0x58260000 0x1000&gt;;</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		interrupts = &lt;GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk_dummy&gt;;</div><div class='add'>+		clock-names = "ipg";</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_PI_0&gt;;</div><div class='add'>+		fsl,channel = &lt;0&gt;;</div><div class='add'>+		fsl,num-irqs = &lt;32&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pi0_ipg_lpcg: clock-controller@58263004 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x58263004 0x4&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "pi0_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_ISI_CH0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pi0_pxl_lpcg: clock-controller@58263018 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x58263018 0x4&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-output-names = "pi0_lpcg_pxl_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_ISI_CH0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pi0_misc_lpcg: clock-controller@5826301c {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5826301c 0x4&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_MISC0&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-output-names = "pi0_lpcg_misc_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_ISI_CH0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c0_parallel: i2c@58266000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+		reg = &lt;0x58266000 0x1000&gt;;</div><div class='add'>+		interrupts = &lt;8&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_PI_0_I2C_0 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;img_ipg_clk&gt;;</div><div class='add'>+		clock-names = "per", "ipg";</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_PI_0_I2C_0 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;24000000&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;irqsteer_parallel&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_PI_0_I2C_0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	jpegdec: jpegdec@58400000 {</div><div class='add'>+		reg = &lt;0x58400000 0x00050000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;img_jpeg_dec_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;img_jpeg_dec_lpcg IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		assigned-clocks = &lt;&amp;img_jpeg_dec_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+				  &lt;&amp;img_jpeg_dec_lpcg IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;200000000&gt;, &lt;200000000&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_MJPEG_DEC_MP&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_MJPEG_DEC_S0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	jpegenc: jpegenc@58450000 {</div><div class='add'>+		reg = &lt;0x58450000 0x00050000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;img_jpeg_enc_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;img_jpeg_enc_lpcg IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		assigned-clocks = &lt;&amp;img_jpeg_enc_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+				  &lt;&amp;img_jpeg_enc_lpcg IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;200000000&gt;, &lt;200000000&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_MJPEG_ENC_MP&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_MJPEG_ENC_S0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pdma0_lpcg: clock-controller@58500000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x58500000 0x10000&gt;;</div><div class='add'>+		clocks = &lt;&amp;img_pxl_clk&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-output-names = "pdma0_lpcg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_ISI_CH0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pdma1_lpcg: clock-controller@58510000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x58510000 0x10000&gt;;</div><div class='add'>+		clocks = &lt;&amp;img_pxl_clk&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-output-names = "pdma1_lpcg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_ISI_CH1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pdma2_lpcg: clock-controller@58520000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x58520000 0x10000&gt;;</div><div class='add'>+		clocks = &lt;&amp;img_pxl_clk&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-output-names = "pdma2_lpcg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_ISI_CH2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pdma3_lpcg: clock-controller@58530000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x58530000 0x10000&gt;;</div><div class='add'>+		clocks = &lt;&amp;img_pxl_clk&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-output-names = "pdma3_lpcg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_ISI_CH3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pdma4_lpcg: clock-controller@58540000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x58540000 0x10000&gt;;</div><div class='add'>+		clocks = &lt;&amp;img_pxl_clk&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-output-names = "pdma4_lpcg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_ISI_CH4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pdma5_lpcg: clock-controller@58550000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x58550000 0x10000&gt;;</div><div class='add'>+		clocks = &lt;&amp;img_pxl_clk&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-output-names = "pdma5_lpcg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_ISI_CH5&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pdma6_lpcg: clock-controller@58560000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x58560000 0x10000&gt;;</div><div class='add'>+		clocks = &lt;&amp;img_pxl_clk&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-output-names = "pdma6_lpcg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_ISI_CH6&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pdma7_lpcg: clock-controller@58570000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x58570000 0x10000&gt;;</div><div class='add'>+		clocks = &lt;&amp;img_pxl_clk&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-output-names = "pdma7_lpcg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_ISI_CH7&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	csi0_pxl_lpcg: clock-controller@58580000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x58580000 0x10000&gt;;</div><div class='add'>+		clocks = &lt;&amp;img_pxl_clk&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-output-names = "csi0_lpcg_pxl_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_CSI_0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	csi1_pxl_lpcg: clock-controller@58590000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x58590000 0x10000&gt;;</div><div class='add'>+		clocks = &lt;&amp;img_pxl_clk&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-output-names = "csi1_lpcg_pxl_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_CSI_1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdmi_rx_pxl_link_lpcg: clock-controller@585a0000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x585a0000 0x10000&gt;;</div><div class='add'>+		clocks = &lt;&amp;img_pxl_clk&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-output-names = "hdmi_rx_lpcg_pxl_link_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_HDMI_RX&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	img_jpeg_dec_lpcg: clock-controller@585d0000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x585d0000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;img_ipg_clk&gt;, &lt;&amp;img_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;,</div><div class='add'>+				&lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "img_jpeg_dec_lpcg_clk",</div><div class='add'>+				     "img_jpeg_dec_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_MJPEG_DEC_MP&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	img_jpeg_enc_lpcg: clock-controller@585f0000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x585f0000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;img_ipg_clk&gt;, &lt;&amp;img_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;,</div><div class='add'>+				&lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "img_jpeg_enc_lpcg_clk",</div><div class='add'>+				     "img_jpeg_enc_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_MJPEG_ENC_MP&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi<br/>new file mode 100644<br/>index 000000000000..764c1a08e3b1<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi</a></div><div class='hunk'>@@ -0,0 +1,387 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2018-2020 NXP</div><div class='add'>+ *	Dong Aisheng &lt;aisheng.dong@nxp.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/imx8-lpcg.h&gt;</div><div class='add'>+#include &lt;dt-bindings/firmware/imx/rsrc.h&gt;</div><div class='add'>+</div><div class='add'>+lsio_bus_clk: clock-lsio-bus {</div><div class='add'>+	compatible = "fixed-clock";</div><div class='add'>+	#clock-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;100000000&gt;;</div><div class='add'>+	clock-output-names = "lsio_bus_clk";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+lsio_subsys: bus@5d000000 {</div><div class='add'>+	compatible = "simple-bus";</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;1&gt;;</div><div class='add'>+	ranges = &lt;0x5d000000 0x0 0x5d000000 0x1000000&gt;,</div><div class='add'>+		 &lt;0x08000000 0x0 0x08000000 0x10000000&gt;;</div><div class='add'>+</div><div class='add'>+	lsio_pwm0: pwm@5d000000 {</div><div class='add'>+		compatible = "fsl,imx27-pwm";</div><div class='add'>+		reg = &lt;0x5d000000 0x10000&gt;;</div><div class='add'>+		clock-names = "ipg", "per";</div><div class='add'>+		clocks = &lt;&amp;pwm0_lpcg IMX_LPCG_CLK_6&gt;,</div><div class='add'>+			 &lt;&amp;pwm0_lpcg IMX_LPCG_CLK_1&gt;;</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;24000000&gt;;</div><div class='add'>+		#pwm-cells = &lt;3&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lsio_pwm1: pwm@5d010000 {</div><div class='add'>+		compatible = "fsl,imx27-pwm";</div><div class='add'>+		reg = &lt;0x5d010000 0x10000&gt;;</div><div class='add'>+		clock-names = "ipg", "per";</div><div class='add'>+		clocks = &lt;&amp;pwm1_lpcg IMX_LPCG_CLK_6&gt;,</div><div class='add'>+			 &lt;&amp;pwm1_lpcg IMX_LPCG_CLK_1&gt;;</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;24000000&gt;;</div><div class='add'>+		#pwm-cells = &lt;3&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lsio_pwm2: pwm@5d020000 {</div><div class='add'>+		compatible = "fsl,imx27-pwm";</div><div class='add'>+		reg = &lt;0x5d020000 0x10000&gt;;</div><div class='add'>+		clock-names = "ipg", "per";</div><div class='add'>+		clocks = &lt;&amp;pwm2_lpcg IMX_LPCG_CLK_6&gt;,</div><div class='add'>+			 &lt;&amp;pwm2_lpcg IMX_LPCG_CLK_1&gt;;</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;24000000&gt;;</div><div class='add'>+		#pwm-cells = &lt;3&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lsio_pwm3: pwm@5d030000 {</div><div class='add'>+		compatible = "fsl,imx27-pwm";</div><div class='add'>+		reg = &lt;0x5d030000 0x10000&gt;;</div><div class='add'>+		clock-names = "ipg", "per";</div><div class='add'>+		clocks = &lt;&amp;pwm3_lpcg IMX_LPCG_CLK_6&gt;,</div><div class='add'>+			 &lt;&amp;pwm3_lpcg IMX_LPCG_CLK_1&gt;;</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;24000000&gt;;</div><div class='add'>+		#pwm-cells = &lt;3&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lsio_gpio0: gpio@5d080000 {</div><div class='add'>+		reg = &lt;0x5d080000 0x10000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_GPIO_0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lsio_gpio1: gpio@5d090000 {</div><div class='add'>+		reg = &lt;0x5d090000 0x10000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_GPIO_1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lsio_gpio2: gpio@5d0a0000 {</div><div class='add'>+		reg = &lt;0x5d0a0000 0x10000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_GPIO_2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lsio_gpio3: gpio@5d0b0000 {</div><div class='add'>+		reg = &lt;0x5d0b0000 0x10000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_GPIO_3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lsio_gpio4: gpio@5d0c0000 {</div><div class='add'>+		reg = &lt;0x5d0c0000 0x10000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_GPIO_4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lsio_gpio5: gpio@5d0d0000 {</div><div class='add'>+		reg = &lt;0x5d0d0000 0x10000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_GPIO_5&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lsio_gpio6: gpio@5d0e0000 {</div><div class='add'>+		reg = &lt;0x5d0e0000 0x10000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_GPIO_6&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lsio_gpio7: gpio@5d0f0000 {</div><div class='add'>+		reg = &lt;0x5d0f0000 0x10000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_GPIO_7&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	flexspi0: spi@5d120000 {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		compatible = "nxp,imx8qxp-fspi";</div><div class='add'>+		reg = &lt;0x5d120000 0x10000&gt;, &lt;0x08000000 0x10000000&gt;;</div><div class='add'>+		reg-names = "fspi_base", "fspi_mmap";</div><div class='add'>+		interrupts = &lt;GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_FSPI_0 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;clk IMX_SC_R_FSPI_0 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		clock-names = "fspi_en", "fspi";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_FSPI_0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lsio_mu0: mailbox@5d1b0000 {</div><div class='add'>+		reg = &lt;0x5d1b0000 0x10000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		#mbox-cells = &lt;2&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lsio_mu1: mailbox@5d1c0000 {</div><div class='add'>+		reg = &lt;0x5d1c0000 0x10000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		#mbox-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lsio_mu2: mailbox@5d1d0000 {</div><div class='add'>+		reg = &lt;0x5d1d0000 0x10000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		#mbox-cells = &lt;2&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lsio_mu3: mailbox@5d1e0000 {</div><div class='add'>+		reg = &lt;0x5d1e0000 0x10000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		#mbox-cells = &lt;2&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lsio_mu4: mailbox@5d1f0000 {</div><div class='add'>+		reg = &lt;0x5d1f0000 0x10000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		#mbox-cells = &lt;2&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lsio_mu5: mailbox@5d200000 {</div><div class='add'>+		reg = &lt;0x5d200000 0x10000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		#mbox-cells = &lt;2&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_MU_5A&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lsio_mu6: mailbox@5d210000 {</div><div class='add'>+		reg = &lt;0x5d210000 0x10000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		#mbox-cells = &lt;2&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_MU_6A&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lsio_mu13: mailbox@5d280000 {</div><div class='add'>+		reg = &lt;0x5d280000 0x10000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		#mbox-cells = &lt;2&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_MU_13A&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* LPCG clocks */</div><div class='add'>+	pwm0_lpcg: clock-controller@5d400000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5d400000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;lsio_bus_clk&gt;,</div><div class='add'>+			 &lt;&amp;clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_1&gt;,</div><div class='add'>+				&lt;IMX_LPCG_CLK_4&gt;, &lt;IMX_LPCG_CLK_5&gt;,</div><div class='add'>+				&lt;IMX_LPCG_CLK_6&gt;;</div><div class='add'>+		clock-output-names = "pwm0_lpcg_ipg_clk",</div><div class='add'>+				     "pwm0_lpcg_ipg_hf_clk",</div><div class='add'>+				     "pwm0_lpcg_ipg_s_clk",</div><div class='add'>+				     "pwm0_lpcg_ipg_slv_clk",</div><div class='add'>+				     "pwm0_lpcg_ipg_mstr_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_PWM_0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pwm1_lpcg: clock-controller@5d410000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5d410000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;lsio_bus_clk&gt;,</div><div class='add'>+			 &lt;&amp;clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_1&gt;,</div><div class='add'>+				&lt;IMX_LPCG_CLK_4&gt;, &lt;IMX_LPCG_CLK_5&gt;,</div><div class='add'>+				&lt;IMX_LPCG_CLK_6&gt;;</div><div class='add'>+		clock-output-names = "pwm1_lpcg_ipg_clk",</div><div class='add'>+				     "pwm1_lpcg_ipg_hf_clk",</div><div class='add'>+				     "pwm1_lpcg_ipg_s_clk",</div><div class='add'>+				     "pwm1_lpcg_ipg_slv_clk",</div><div class='add'>+				     "pwm1_lpcg_ipg_mstr_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_PWM_1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pwm2_lpcg: clock-controller@5d420000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5d420000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;lsio_bus_clk&gt;,</div><div class='add'>+			 &lt;&amp;clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_1&gt;,</div><div class='add'>+				&lt;IMX_LPCG_CLK_4&gt;, &lt;IMX_LPCG_CLK_5&gt;,</div><div class='add'>+				&lt;IMX_LPCG_CLK_6&gt;;</div><div class='add'>+		clock-output-names = "pwm2_lpcg_ipg_clk",</div><div class='add'>+				     "pwm2_lpcg_ipg_hf_clk",</div><div class='add'>+				     "pwm2_lpcg_ipg_s_clk",</div><div class='add'>+				     "pwm2_lpcg_ipg_slv_clk",</div><div class='add'>+				     "pwm2_lpcg_ipg_mstr_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_PWM_2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pwm3_lpcg: clock-controller@5d430000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5d430000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;lsio_bus_clk&gt;,</div><div class='add'>+			 &lt;&amp;clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_1&gt;,</div><div class='add'>+				&lt;IMX_LPCG_CLK_4&gt;, &lt;IMX_LPCG_CLK_5&gt;,</div><div class='add'>+				&lt;IMX_LPCG_CLK_6&gt;;</div><div class='add'>+		clock-output-names = "pwm3_lpcg_ipg_clk",</div><div class='add'>+				     "pwm3_lpcg_ipg_hf_clk",</div><div class='add'>+				     "pwm3_lpcg_ipg_s_clk",</div><div class='add'>+				     "pwm3_lpcg_ipg_slv_clk",</div><div class='add'>+				     "pwm3_lpcg_ipg_mstr_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_PWM_3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pwm4_lpcg: clock-controller@5d440000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5d440000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;lsio_bus_clk&gt;,</div><div class='add'>+			 &lt;&amp;clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_1&gt;,</div><div class='add'>+				&lt;IMX_LPCG_CLK_4&gt;, &lt;IMX_LPCG_CLK_5&gt;,</div><div class='add'>+				&lt;IMX_LPCG_CLK_6&gt;;</div><div class='add'>+		clock-output-names = "pwm4_lpcg_ipg_clk",</div><div class='add'>+				     "pwm4_lpcg_ipg_hf_clk",</div><div class='add'>+				     "pwm4_lpcg_ipg_s_clk",</div><div class='add'>+				     "pwm4_lpcg_ipg_slv_clk",</div><div class='add'>+				     "pwm4_lpcg_ipg_mstr_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_PWM_4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pwm5_lpcg: clock-controller@5d450000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5d450000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;lsio_bus_clk&gt;,</div><div class='add'>+			 &lt;&amp;clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_1&gt;,</div><div class='add'>+				&lt;IMX_LPCG_CLK_4&gt;, &lt;IMX_LPCG_CLK_5&gt;,</div><div class='add'>+				&lt;IMX_LPCG_CLK_6&gt;;</div><div class='add'>+		clock-output-names = "pwm5_lpcg_ipg_clk",</div><div class='add'>+				     "pwm5_lpcg_ipg_hf_clk",</div><div class='add'>+				     "pwm5_lpcg_ipg_s_clk",</div><div class='add'>+				     "pwm5_lpcg_ipg_slv_clk",</div><div class='add'>+				     "pwm5_lpcg_ipg_mstr_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_PWM_5&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pwm6_lpcg: clock-controller@5d460000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5d460000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;lsio_bus_clk&gt;,</div><div class='add'>+			 &lt;&amp;clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_1&gt;,</div><div class='add'>+				&lt;IMX_LPCG_CLK_4&gt;, &lt;IMX_LPCG_CLK_5&gt;,</div><div class='add'>+				&lt;IMX_LPCG_CLK_6&gt;;</div><div class='add'>+		clock-output-names = "pwm6_lpcg_ipg_clk",</div><div class='add'>+				     "pwm6_lpcg_ipg_hf_clk",</div><div class='add'>+				     "pwm6_lpcg_ipg_s_clk",</div><div class='add'>+				     "pwm6_lpcg_ipg_slv_clk",</div><div class='add'>+				     "pwm6_lpcg_ipg_mstr_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_PWM_6&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pwm7_lpcg: clock-controller@5d470000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5d470000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;lsio_bus_clk&gt;,</div><div class='add'>+			 &lt;&amp;clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_1&gt;,</div><div class='add'>+				&lt;IMX_LPCG_CLK_4&gt;, &lt;IMX_LPCG_CLK_5&gt;,</div><div class='add'>+				&lt;IMX_LPCG_CLK_6&gt;;</div><div class='add'>+		clock-output-names = "pwm7_lpcg_ipg_clk",</div><div class='add'>+				     "pwm7_lpcg_ipg_hf_clk",</div><div class='add'>+				     "pwm7_lpcg_ipg_s_clk",</div><div class='add'>+				     "pwm7_lpcg_ipg_slv_clk",</div><div class='add'>+				     "pwm7_lpcg_ipg_mstr_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_PWM_7&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi<br/>new file mode 100644<br/>index 000000000000..dad0dc8fb431<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi</a></div><div class='hunk'>@@ -0,0 +1,63 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only and MIT</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+lvds0_subsys: bus@56240000 {</div><div class='add'>+	compatible = "simple-bus";</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;1&gt;;</div><div class='add'>+	ranges = &lt;0x56240000 0x0 0x56240000 0x10000&gt;;</div><div class='add'>+</div><div class='add'>+	qm_lvds0_lis_lpcg: qxp_mipi1_lis_lpcg: clock-controller@56243000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x56243000 0x4&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clock-output-names = "lvds0_lis_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_MIPI_1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	qm_lvds0_pwm_lpcg: qxp_mipi1_pwm_lpcg: clock-controller@5624300c {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5624300c 0x4&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clock-output-names = "lvds0_pwm_lpcg_clk",</div><div class='add'>+				     "lvds0_pwm_lpcg_ipg_clk",</div><div class='add'>+				     "lvds0_pwm_lpcg_32k_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_MIPI_1_PWM_0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	qm_lvds0_i2c0_lpcg: qxp_mipi1_i2c0_lpcg: clock-controller@56243010 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x56243010 0x4&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clock-output-names = "lvds0_i2c0_lpcg_clk",</div><div class='add'>+				     "lvds0_i2c0_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_MIPI_1_I2C_0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	qm_pwm_lvds0: qxp_pwm_mipi_lvds1: pwm@56244000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";</div><div class='add'>+		reg = &lt;0x56244000 0x1000&gt;;</div><div class='add'>+		clock-names = "ipg", "per";</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;24000000&gt;;</div><div class='add'>+		#pwm-cells = &lt;3&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_MIPI_1_PWM_0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	qm_i2c0_lvds0: qxp_i2c0_mipi_lvds1: i2c@56246000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+		reg = &lt;0x56246000 0x1000&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		interrupts = &lt;8&gt;;</div><div class='add'>+		clock-names = "per", "ipg";</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;24000000&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_MIPI_1_I2C_0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lvds1.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lvds1.dtsi<br/>new file mode 100644<br/>index 000000000000..12ae4f48e1e1<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8-ss-lvds1.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8-ss-lvds1.dtsi</a></div><div class='hunk'>@@ -0,0 +1,114 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only and MIT</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+lvds1_subsys: bus@57240000 {</div><div class='add'>+	compatible = "simple-bus";</div><div class='add'>+	interrupt-parent = &lt;&amp;irqsteer_lvds1&gt;;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;1&gt;;</div><div class='add'>+	ranges = &lt;0x57240000 0x0 0x57240000 0x10000&gt;;</div><div class='add'>+</div><div class='add'>+	irqsteer_lvds1: interrupt-controller@57240000 {</div><div class='add'>+		compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";</div><div class='add'>+		reg = &lt;0x57240000 0x1000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;lvds1_lis_lpcg IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-names = "ipg";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_LVDS_1&gt;;</div><div class='add'>+		fsl,channel = &lt;0&gt;;</div><div class='add'>+		fsl,num-irqs = &lt;32&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lvds1_lis_lpcg: clock-controller@57243000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x57243000 0x4&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;lvds_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "lvds1_lis_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_LVDS_1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lvds1_pwm_lpcg: clock-controller@5724300c {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5724300c 0x4&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_LVDS_1_PWM_0 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;lvds_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "lvds1_pwm_lpcg_clk",</div><div class='add'>+				     "lvds1_pwm_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_LVDS_1_PWM_0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lvds1_i2c0_lpcg: clock-controller@57243010 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x57243010 0x4&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;lvds_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "lvds1_i2c0_lpcg_clk",</div><div class='add'>+				     "lvds1_i2c0_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_LVDS_1_I2C_0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lvds1_i2c1_lpcg: clock-controller@57243014 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x57243014 0x4&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;lvds_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "lvds1_i2c1_lpcg_clk",</div><div class='add'>+				     "lvds1_i2c1_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_LVDS_1_I2C_0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pwm_lvds1: pwm@57244000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";</div><div class='add'>+		reg = &lt;0x57244000 0x1000&gt;;</div><div class='add'>+		clocks = &lt;&amp;lvds1_pwm_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;lvds1_pwm_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-names = "ipg", "per";</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_LVDS_1_PWM_0 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;24000000&gt;;</div><div class='add'>+		#pwm-cells = &lt;3&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_LVDS_1_PWM_0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c0_lvds1: i2c@57246000 {</div><div class='add'>+		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+		reg = &lt;0x57246000 0x1000&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		interrupts = &lt;8&gt;;</div><div class='add'>+		clocks = &lt;&amp;lvds1_i2c0_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;lvds1_i2c0_lpcg IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-names = "per", "ipg";</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;24000000&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_LVDS_1_I2C_0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c1_lvds1: i2c@57247000 {</div><div class='add'>+		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+		reg = &lt;0x57247000 0x1000&gt;;</div><div class='add'>+		interrupts = &lt;9&gt;;</div><div class='add'>+		clocks = &lt;&amp;lvds1_i2c1_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;lvds1_i2c1_lpcg IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-names = "per", "ipg";</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;24000000&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_LVDS_1_I2C_0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-mipi0.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-mipi0.dtsi<br/>new file mode 100644<br/>index 000000000000..9c5b0cbdfcbd<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8-ss-mipi0.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8-ss-mipi0.dtsi</a></div><div class='hunk'>@@ -0,0 +1,129 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only and MIT</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+mipi0_subsys: bus@56220000 {</div><div class='add'>+	compatible = "simple-bus";</div><div class='add'>+	interrupt-parent = &lt;&amp;irqsteer_mipi0&gt;;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;1&gt;;</div><div class='add'>+	ranges = &lt;0x56220000 0x0 0x56220000 0x10000&gt;;</div><div class='add'>+</div><div class='add'>+	irqsteer_mipi0: interrupt-controller@56220000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-irqsteer", "fsl,imx-irqsteer";</div><div class='add'>+		reg = &lt;0x56220000 0x1000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;mipi0_lis_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-names = "ipg";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_MIPI_0&gt;;</div><div class='add'>+		fsl,channel = &lt;0&gt;;</div><div class='add'>+		fsl,num-irqs = &lt;32&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mipi0_lis_lpcg: clock-controller@56223000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x56223000 0x4&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_MIPI_0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mipi0_pwm_lpcg: clock-controller@5622300c {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5622300c 0x4&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_MIPI_0_PWM_0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mipi0_i2c0_lpcg_ipg_clk: clock-controller@56223014 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x56223014 0x4&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;mipi0_i2c0_lpcg_ipg_s_clk IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-output-names = "mipi0_i2c0_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_MIPI_0_I2C_0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mipi0_i2c0_lpcg_ipg_s_clk: clock-controller@56223018 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x56223018 0x4&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;dsi_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-output-names = "mipi0_i2c0_lpcg_ipg_s_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_MIPI_0_I2C_0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mipi0_i2c0_lpcg_clk: clock-controller@5622301c {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5622301c 0x4&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_MISC2&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-output-names = "mipi0_i2c0_lpcg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_MIPI_0_I2C_0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mipi0_i2c1_lpcg_ipg_clk: clock-controller@56223024 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x56223024 0x4&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;mipi0_i2c1_lpcg_ipg_s_clk IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-output-names = "mipi0_i2c1_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_MIPI_0_I2C_1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mipi0_i2c1_lpcg_ipg_s_clk: clock-controller@56223028 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x56223028 0x4&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;dsi_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-output-names = "mipi0_i2c1_lpcg_ipg_s_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_MIPI_0_I2C_1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mipi0_i2c1_lpcg_clk: clock-controller@5622302c {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5622302c 0x4&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_MIPI_0_I2C_1 IMX_SC_PM_CLK_MISC2&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-output-names = "mipi0_i2c1_lpcg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_MIPI_0_I2C_1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pwm_mipi0: pwm@56224000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";</div><div class='add'>+		reg = &lt;0x56224000 0x1000&gt;;</div><div class='add'>+		clocks = &lt;&amp;mipi0_pwm_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;mipi0_pwm_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-names = "ipg", "per";</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_MIPI_0_PWM_0 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;24000000&gt;;</div><div class='add'>+		#pwm-cells = &lt;3&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_MIPI_0_PWM_0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c0_mipi0: i2c@56226000 {</div><div class='add'>+		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+		reg = &lt;0x56226000 0x1000&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		interrupts = &lt;8&gt;;</div><div class='add'>+		clocks = &lt;&amp;mipi0_i2c0_lpcg_clk IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;mipi0_i2c0_lpcg_ipg_clk IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-names = "per", "ipg";</div><div class='add'>+		assigned-clocks = &lt;&amp;mipi0_i2c0_lpcg_clk IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;24000000&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_MIPI_0_I2C_0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-mipi1.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-mipi1.dtsi<br/>new file mode 100644<br/>index 000000000000..5b1f08e412b2<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8-ss-mipi1.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8-ss-mipi1.dtsi</a></div><div class='hunk'>@@ -0,0 +1,138 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only and MIT</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+mipi1_subsys: bus@57220000 {</div><div class='add'>+	compatible = "simple-bus";</div><div class='add'>+	interrupt-parent = &lt;&amp;irqsteer_mipi1&gt;;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;1&gt;;</div><div class='add'>+	ranges = &lt;0x57220000 0x0 0x57220000 0x10000&gt;;</div><div class='add'>+</div><div class='add'>+	irqsteer_mipi1: interrupt-controller@57220000 {</div><div class='add'>+		compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";</div><div class='add'>+		reg = &lt;0x57220000 0x1000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;mipi1_lis_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-names = "ipg";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_MIPI_1&gt;;</div><div class='add'>+		fsl,channel = &lt;0&gt;;</div><div class='add'>+		fsl,num-irqs = &lt;32&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mipi1_lis_lpcg: clock-controller@57223000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x57223000 0x4&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;dsi_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-output-names = "mipi1_lis_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_MIPI_1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mipi1_pwm_lpcg: clock-controller@5722300c {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5722300c 0x4&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;dsi_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "mipi1_pwm_lpcg_clk",</div><div class='add'>+				     "mipi1_pwm_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_MIPI_1_PWM_0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mipi1_i2c0_lpcg_clk: clock-controller@5722301c {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5722301c 0x4&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_MISC2&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-output-names = "mipi1_i2c0_lpcg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_MIPI_1_I2C_0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mipi1_i2c0_lpcg_ipg_clk: clock-controller@57223014 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x57223014 0x4&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;mipi1_i2c0_lpcg_ipg_s_clk IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-output-names = "mipi1_i2c0_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_MIPI_1_I2C_0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mipi1_i2c0_lpcg_ipg_s_clk: clock-controller@57223018 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x57223018 0x4&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;dsi_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-output-names = "mipi1_i2c0_lpcg_ipg_s_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_MIPI_1_I2C_0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mipi1_i2c1_lpcg_ipg_clk: clock-controller@57223024 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x57223024 0x4&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;mipi1_i2c1_lpcg_ipg_s_clk IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-output-names = "mipi1_i2c1_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_MIPI_1_I2C_1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mipi1_i2c1_lpcg_ipg_s_clk: clock-controller@57223028 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x57223028 0x4&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;dsi_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-output-names = "mipi1_i2c1_lpcg_ipg_s_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_MIPI_1_I2C_1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mipi1_i2c1_lpcg_clk: clock-controller@5722302c {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5722302c 0x4&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_MIPI_1_I2C_1 IMX_SC_PM_CLK_MISC2&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-output-names = "mipi1_i2c1_lpcg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_MIPI_1_I2C_1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pwm_mipi1: pwm@57224000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";</div><div class='add'>+		reg = &lt;0x57224000 0x1000&gt;;</div><div class='add'>+		clocks = &lt;&amp;mipi1_pwm_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;mipi1_pwm_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-names = "ipg", "per";</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;24000000&gt;;</div><div class='add'>+		#pwm-cells = &lt;3&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_MIPI_1_PWM_0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c0_mipi1: i2c@57226000 {</div><div class='add'>+		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+		reg = &lt;0x57226000 0x1000&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		interrupts = &lt;8&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;irqsteer_mipi1&gt;;</div><div class='add'>+		clocks = &lt;&amp;mipi1_i2c0_lpcg_clk IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;mipi1_i2c0_lpcg_ipg_clk IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-names = "per", "ipg";</div><div class='add'>+		assigned-clocks = &lt;&amp;mipi1_i2c0_lpcg_clk IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;24000000&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_MIPI_1_I2C_0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-security.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-security.dtsi<br/>new file mode 100644<br/>index 000000000000..3e04142aca5c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8-ss-security.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8-ss-security.dtsi</a></div><div class='hunk'>@@ -0,0 +1,38 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2019 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/firmware/imx/rsrc.h&gt;</div><div class='add'>+</div><div class='add'>+security_subsys: bus@31400000 {</div><div class='add'>+	compatible = "simple-bus";</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;1&gt;;</div><div class='add'>+	ranges = &lt;0x31400000 0x0 0x31400000 0x90000&gt;;</div><div class='add'>+</div><div class='add'>+	crypto: crypto@31400000 {</div><div class='add'>+		compatible = "fsl,imx8qm-caam", "fsl,sec-v4.0";</div><div class='add'>+		reg = &lt;0x31400000 0x90000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges = &lt;0 0x31400000 0x90000&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_CAAM_JR2&gt;;</div><div class='add'>+		fsl,sec-era = &lt;9&gt;;</div><div class='add'>+</div><div class='add'>+		sec_jr2: jr@30000 {</div><div class='add'>+			compatible = "fsl,imx8qm-job-ring", "fsl,sec-v4.0-job-ring";</div><div class='add'>+			reg = &lt;0x30000 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			power-domains = &lt;&amp;pd IMX_SC_R_CAAM_JR2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sec_jr3: jr@40000 {</div><div class='add'>+			compatible = "fsl,imx8qm-job-ring", "fsl,sec-v4.0-job-ring";</div><div class='add'>+			reg = &lt;0x40000 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			power-domains = &lt;&amp;pd IMX_SC_R_CAAM_JR3&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi<br/>new file mode 100644<br/>index 000000000000..87211c18d65a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi</a></div><div class='hunk'>@@ -0,0 +1,74 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021 NXP</div><div class='add'>+ *	Dong Aisheng &lt;aisheng.dong@nxp.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+vpu: vpu@2c000000 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;1&gt;;</div><div class='add'>+	ranges = &lt;0x2c000000 0x0 0x2c000000 0x2000000&gt;;</div><div class='add'>+	reg = &lt;0 0x2c000000 0 0x1000000&gt;;</div><div class='add'>+	power-domains = &lt;&amp;pd IMX_SC_R_VPU&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+</div><div class='add'>+	mu_m0: mailbox@2d000000 {</div><div class='add'>+		compatible = "fsl,imx6sx-mu";</div><div class='add'>+		reg = &lt;0x2d000000 0x20000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		#mbox-cells = &lt;2&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_VPU_MU_0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mu1_m0: mailbox@2d020000 {</div><div class='add'>+		compatible = "fsl,imx6sx-mu";</div><div class='add'>+		reg = &lt;0x2d020000 0x20000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		#mbox-cells = &lt;2&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_VPU_MU_1&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mu2_m0: mailbox@2d040000 {</div><div class='add'>+		compatible = "fsl,imx6sx-mu";</div><div class='add'>+		reg = &lt;0x2d040000 0x20000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		#mbox-cells = &lt;2&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_VPU_MU_2&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vpu_core0: vpu-core@2d080000 {</div><div class='add'>+		reg = &lt;0x2d080000 0x10000&gt;;</div><div class='add'>+		compatible = "nxp,imx8q-vpu-decoder";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_VPU_DEC_0&gt;;</div><div class='add'>+		mbox-names = "tx0", "tx1", "rx";</div><div class='add'>+		mboxes = &lt;&amp;mu_m0 0 0&gt;,</div><div class='add'>+			&lt;&amp;mu_m0 0 1&gt;,</div><div class='add'>+			&lt;&amp;mu_m0 1 0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vpu_core1: vpu-core@2d090000 {</div><div class='add'>+		reg = &lt;0x2d090000 0x10000&gt;;</div><div class='add'>+		compatible = "nxp,imx8q-vpu-encoder";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_VPU_ENC_0&gt;;</div><div class='add'>+		mbox-names = "tx0", "tx1", "rx";</div><div class='add'>+		mboxes = &lt;&amp;mu1_m0 0 0&gt;,</div><div class='add'>+			&lt;&amp;mu1_m0 0 1&gt;,</div><div class='add'>+			&lt;&amp;mu1_m0 1 0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vpu_core2: vpu-core@2d0a0000 {</div><div class='add'>+		reg = &lt;0x2d0a0000 0x10000&gt;;</div><div class='add'>+		compatible = "nxp,imx8q-vpu-encoder";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_VPU_ENC_1&gt;;</div><div class='add'>+		mbox-names = "tx0", "tx1", "rx";</div><div class='add'>+		mboxes = &lt;&amp;mu2_m0 0 0&gt;,</div><div class='add'>+			&lt;&amp;mu2_m0 0 1&gt;,</div><div class='add'>+			&lt;&amp;mu2_m0 1 0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8dx-colibri-aster.dts b/arch/arm64/boot/dts/freescale/imx8dx-colibri-aster.dts<br/>new file mode 100644<br/>index 000000000000..c974f5dc0283<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8dx-colibri-aster.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8dx-colibri-aster.dts</a></div><div class='hunk'>@@ -0,0 +1,16 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2018-2021 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8dx-colibri.dtsi"</div><div class='add'>+#include "imx8x-colibri-aster.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Toradex Colibri iMX8DX on Aster Board";</div><div class='add'>+	compatible = "toradex,colibri-imx8x-aster",</div><div class='add'>+		     "toradex,colibri-imx8x",</div><div class='add'>+		     "fsl,imx8dx";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8dx-colibri-eval-v3.dts b/arch/arm64/boot/dts/freescale/imx8dx-colibri-eval-v3.dts<br/>new file mode 100644<br/>index 000000000000..f2bf15463ae8<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8dx-colibri-eval-v3.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8dx-colibri-eval-v3.dts</a></div><div class='hunk'>@@ -0,0 +1,16 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2018-2021 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8dx-colibri.dtsi"</div><div class='add'>+#include "imx8x-colibri-eval-v3.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Toradex Colibri iMX8DX on Colibri Evaluation Board V3";</div><div class='add'>+	compatible = "toradex,colibri-imx8x-eval-v3",</div><div class='add'>+		     "toradex,colibri-imx8x",</div><div class='add'>+		     "fsl,imx8dx";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8dx-colibri-iris-v2.dts b/arch/arm64/boot/dts/freescale/imx8dx-colibri-iris-v2.dts<br/>new file mode 100644<br/>index 000000000000..fd425c70cf2b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8dx-colibri-iris-v2.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8dx-colibri-iris-v2.dts</a></div><div class='hunk'>@@ -0,0 +1,16 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2018-2021 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8dx-colibri.dtsi"</div><div class='add'>+#include "imx8x-colibri-iris-v2.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Toradex Colibri iMX8DX on Colibri Iris V2 Board";</div><div class='add'>+	compatible = "toradex,colibri-imx8x-iris-v2",</div><div class='add'>+		     "toradex,colibri-imx8x",</div><div class='add'>+		     "fsl,imx8dx";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8dx-colibri-iris.dts b/arch/arm64/boot/dts/freescale/imx8dx-colibri-iris.dts<br/>new file mode 100644<br/>index 000000000000..e5e2346ce4f1<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8dx-colibri-iris.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8dx-colibri-iris.dts</a></div><div class='hunk'>@@ -0,0 +1,16 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2018-2021 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8dx-colibri.dtsi"</div><div class='add'>+#include "imx8x-colibri-iris.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Toradex Colibri iMX8DX on Colibri Iris Board";</div><div class='add'>+	compatible = "toradex,colibri-imx8x-iris",</div><div class='add'>+		     "toradex,colibri-imx8x",</div><div class='add'>+		     "fsl,imx8dx";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8dx-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8dx-colibri.dtsi<br/>new file mode 100644<br/>index 000000000000..4d1ad052c5b6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8dx-colibri.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8dx-colibri.dtsi</a></div><div class='hunk'>@@ -0,0 +1,22 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2018-2021 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "imx8dx.dtsi"</div><div class='add'>+#include "imx8x-colibri.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Toradex Colibri iMX8DX Module";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;thermal_zones {</div><div class='add'>+	pmic-thermal {</div><div class='add'>+		cooling-maps {</div><div class='add'>+			map0 {</div><div class='add'>+				cooling-device = &lt;&amp;A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+						 &lt;&amp;A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8dx.dtsi b/arch/arm64/boot/dts/freescale/imx8dx.dtsi<br/>new file mode 100644<br/>index 000000000000..ce76efc1a041<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8dx.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8dx.dtsi</a></div><div class='hunk'>@@ -0,0 +1,13 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2016 Freescale Semiconductor, Inc.</div><div class='add'>+ * Copyright 2017-2020 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8dxp.dtsi"</div><div class='add'>+</div><div class='add'>+&amp;gpu_3d0 {</div><div class='add'>+	assigned-clock-rates = &lt;372000000&gt;, &lt;372000000&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts<br/>new file mode 100644<br/>index 000000000000..5c68d33e19f2<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8dxl-evk.dts</a></div><div class='hunk'>@@ -0,0 +1,1036 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2019~2020, 2022 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8dxl.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Freescale i.MX8DXL EVK";</div><div class='add'>+	compatible = "fsl,imx8dxl-evk", "fsl,imx8dxl";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		i2c2 = &amp;i2c2;</div><div class='add'>+		mmc0 = &amp;usdhc1;</div><div class='add'>+		mmc1 = &amp;usdhc2;</div><div class='add'>+		serial0 = &amp;lpuart0;</div><div class='add'>+		serial1 = &amp;lpuart1;</div><div class='add'>+		serial6 = &amp;cm40_lpuart;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;lpuart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	imx8dxl-cm4 {</div><div class='add'>+		compatible = "fsl,imx8qxp-cm4";</div><div class='add'>+		clocks = &lt;&amp;clk_dummy&gt;;</div><div class='add'>+		mbox-names = "tx", "rx", "rxdb";</div><div class='add'>+		mboxes = &lt;&amp;lsio_mu5 0 1 &amp;lsio_mu5 1 1 &amp;lsio_mu5 3 1&gt;;</div><div class='add'>+		memory-region = &lt;&amp;vdevbuffer&gt;, &lt;&amp;vdev0vring0&gt;, &lt;&amp;vdev0vring1&gt;,</div><div class='add'>+				&lt;&amp;vdev1vring0&gt;, &lt;&amp;vdev1vring1&gt;, &lt;&amp;rsc_table&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_M4_0_PID0&gt;, &lt;&amp;pd IMX_SC_R_M4_0_MU_1A&gt;;</div><div class='add'>+		fsl,resource-id = &lt;IMX_SC_R_M4_0_PID0&gt;;</div><div class='add'>+		fsl,entry-address = &lt;0x34fe0000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	memory@80000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x00000000 0x80000000 0 0x40000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Memory reserved for optee usage. Please do not use.</div><div class='add'>+		 * This will be automatically added to dtb if OP-TEE is installed.</div><div class='add'>+		 * optee@96000000 {</div><div class='add'>+		 *     reg = &lt;0 0x96000000 0 0x2000000&gt;;</div><div class='add'>+		 *     no-map;</div><div class='add'>+		 * };</div><div class='add'>+		 */</div><div class='add'>+</div><div class='add'>+		/* global autoconfigured region for contiguous allocations */</div><div class='add'>+		linux,cma {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reusable;</div><div class='add'>+			size = &lt;0 0x14000000&gt;;</div><div class='add'>+			alloc-ranges = &lt;0 0x98000000 0 0x14000000&gt;;</div><div class='add'>+			linux,cma-default;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev0vring0: memory0@90000000 {</div><div class='add'>+			reg = &lt;0 0x90000000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev0vring1: memory@90008000 {</div><div class='add'>+			reg = &lt;0 0x90008000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev1vring0: memory@90010000 {</div><div class='add'>+			reg = &lt;0 0x90010000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev1vring1: memory@90018000 {</div><div class='add'>+			reg = &lt;0 0x90018000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rsc_table: memory-rsc-table@900ff000 {</div><div class='add'>+			reg = &lt;0 0x900ff000 0 0x1000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdevbuffer: memory-vdevbuffer@90400000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x90400000 0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	m2_uart1_sel: regulator-m2uart1sel {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "m2_uart1_sel";</div><div class='add'>+		gpio = &lt;&amp;pca6416_1 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mux3_en: regulator-0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "mux3_en";</div><div class='add'>+		gpio = &lt;&amp;pca6416_2 8 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_fec1_sel: regulator-1 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "fec1_supply";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;pca6416_1 11 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_fec1_io: regulator-2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "fec1_io_supply";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		gpio = &lt;&amp;max7322 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_can0_stby: regulator-4 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "can0-stby";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;pca6416_3 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_can1_stby: regulator-5 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "can1-stby";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;pca6416_3 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "SD1_SPWR";</div><div class='add'>+		regulator-min-microvolt = &lt;3000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;lsio_gpio4 30 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		off-on-delay-us = &lt;3480&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vref_1v8: regulator-adc-vref {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vref_1v8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mii_select: regulator-4 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "mii-select";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;scu_gpio 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_pcieb: regulator-pcieb {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "reg_pcieb";</div><div class='add'>+		gpio = &lt;&amp;pca6416_1 13 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_audio_5v: regulator-audio-pwr {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "audio-5v";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_audio_3v3: regulator-audio-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "audio-3v3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_audio_1v8: regulator-audio-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "audio-1v8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bt_sco_codec: audio-codec-bt {</div><div class='add'>+		compatible = "linux,bt-sco";</div><div class='add'>+		#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-bt-sco {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,name = "bt-sco-audio";</div><div class='add'>+		simple-audio-card,format = "dsp_a";</div><div class='add'>+		simple-audio-card,bitclock-inversion;</div><div class='add'>+		simple-audio-card,frame-master = &lt;&amp;btcpu&gt;;</div><div class='add'>+		simple-audio-card,bitclock-master = &lt;&amp;btcpu&gt;;</div><div class='add'>+</div><div class='add'>+		btcpu: simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;sai0&gt;;</div><div class='add'>+			dai-tdm-slot-num = &lt;2&gt;;</div><div class='add'>+			dai-tdm-slot-width = &lt;16&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		simple-audio-card,codec {</div><div class='add'>+			sound-dai = &lt;&amp;bt_sco_codec 1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-wm8960-1 {</div><div class='add'>+		compatible = "fsl,imx-audio-wm8960";</div><div class='add'>+		model = "wm8960-audio";</div><div class='add'>+		audio-cpu = &lt;&amp;sai1&gt;;</div><div class='add'>+		audio-codec = &lt;&amp;wm8960_1&gt;;</div><div class='add'>+		audio-asrc = &lt;&amp;asrc0&gt;;</div><div class='add'>+		audio-routing = "Headphone Jack", "HP_L",</div><div class='add'>+				"Headphone Jack", "HP_R",</div><div class='add'>+				"Ext Spk", "SPK_LP",</div><div class='add'>+				"Ext Spk", "SPK_LN",</div><div class='add'>+				"Ext Spk", "SPK_RP",</div><div class='add'>+				"Ext Spk", "SPK_RN",</div><div class='add'>+				"LINPUT1", "Mic Jack",</div><div class='add'>+				"Mic Jack", "MICB";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-wm8960-2 {</div><div class='add'>+		compatible = "fsl,imx-audio-wm8960";</div><div class='add'>+		model = "wm8960-audio-2";</div><div class='add'>+		audio-cpu = &lt;&amp;sai2&gt;;</div><div class='add'>+		audio-codec = &lt;&amp;wm8960_2&gt;;</div><div class='add'>+		audio-routing = "Headphone Jack", "HP_L",</div><div class='add'>+				"Headphone Jack", "HP_R",</div><div class='add'>+				"Ext Spk", "SPK_LP",</div><div class='add'>+				"Ext Spk", "SPK_LN",</div><div class='add'>+				"Ext Spk", "SPK_RP",</div><div class='add'>+				"Ext Spk", "SPK_RN",</div><div class='add'>+				"LINPUT1", "Mic Jack",</div><div class='add'>+				"Mic Jack", "MICB";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-wm8960-3 {</div><div class='add'>+		compatible = "fsl,imx-audio-wm8960";</div><div class='add'>+		model = "wm8960-audio-3";</div><div class='add'>+		audio-cpu = &lt;&amp;sai3&gt;;</div><div class='add'>+		audio-codec = &lt;&amp;wm8960_3&gt;;</div><div class='add'>+		audio-routing = "Headphone Jack", "HP_L",</div><div class='add'>+				"Headphone Jack", "HP_R",</div><div class='add'>+				"Ext Spk", "SPK_LP",</div><div class='add'>+				"Ext Spk", "SPK_LN",</div><div class='add'>+				"Ext Spk", "SPK_RP",</div><div class='add'>+				"Ext Spk", "SPK_RN",</div><div class='add'>+				"LINPUT1", "Mic Jack",</div><div class='add'>+				"Mic Jack", "MICB";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;adc0 {</div><div class='add'>+	vref-supply = &lt;&amp;reg_vref_1v8&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;asrc0 {</div><div class='add'>+	fsl,asrc-rate = &lt;48000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eqos {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_eqos&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	nvmem-cells = &lt;&amp;fec_mac1&gt;;</div><div class='add'>+	nvmem-cell-names = "mac-address";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@0 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			eee-broken-1000t;</div><div class='add'>+			qca,disable-smarteee;</div><div class='add'>+			qca,disable-hibernation-mode;</div><div class='add'>+			reset-gpios = &lt;&amp;pca6416_1 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;20&gt;;</div><div class='add'>+			reset-deassert-us = &lt;200000&gt;;</div><div class='add'>+			vddio-supply = &lt;&amp;vddio0&gt;;</div><div class='add'>+</div><div class='add'>+			vddio0: vddio-regulator {</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * fec1 shares the some PINs with usdhc2.</div><div class='add'>+ * by default usdhc2 is enabled in this dts.</div><div class='add'>+ * Please disable usdhc2 to enable fec1</div><div class='add'>+ */</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec1&gt;;</div><div class='add'>+	phy-mode = "rgmii-txid";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy1&gt;;</div><div class='add'>+	fsl,magic-packet;</div><div class='add'>+	rx-internal-delay-ps = &lt;2000&gt;;</div><div class='add'>+	nvmem-cells = &lt;&amp;fec_mac0&gt;;</div><div class='add'>+	nvmem-cell-names = "mac-address";</div><div class='add'>+	status = "disabled";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy1: ethernet-phy@1 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;pca6416_1 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;10000&gt;;</div><div class='add'>+			qca,disable-smarteee;</div><div class='add'>+			vddio-supply = &lt;&amp;vddio1&gt;;</div><div class='add'>+</div><div class='add'>+			vddio1: vddio-regulator {</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexspi0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexspi0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mt35xu512aba0: flash@0 {</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		spi-max-frequency = &lt;133000000&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;8&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;8&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pca6416_1: gpio@20 {</div><div class='add'>+		compatible = "ti,tca6416";</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pca6416_2: gpio@21 {</div><div class='add'>+		compatible = "ti,tca6416";</div><div class='add'>+		reg = &lt;0x21&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pca9548_1: i2c-mux@70 {</div><div class='add'>+		compatible = "nxp,pca9548";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		reg = &lt;0x70&gt;;</div><div class='add'>+</div><div class='add'>+		i2c@0 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0x0&gt;;</div><div class='add'>+</div><div class='add'>+			max7322: gpio@68 {</div><div class='add'>+				compatible = "maxim,max7322";</div><div class='add'>+				reg = &lt;0x68&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@1 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0x1&gt;;</div><div class='add'>+</div><div class='add'>+			wm8960_1: audio-codec@1a {</div><div class='add'>+				compatible = "wlf,wm8960";</div><div class='add'>+				reg = &lt;0x1a&gt;;</div><div class='add'>+				clocks = &lt;&amp;mclkout1_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+				clock-names = "mclk";</div><div class='add'>+				assigned-clocks = &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS&gt;,</div><div class='add'>+						  &lt;&amp;mclkout1_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;786432000&gt;,</div><div class='add'>+						       &lt;49152000&gt;,</div><div class='add'>+						       &lt;12288000&gt;,</div><div class='add'>+						       &lt;12288000&gt;;</div><div class='add'>+				wlf,shared-lrclk;</div><div class='add'>+				wlf,hp-cfg = &lt;2 2 3&gt;;</div><div class='add'>+				wlf,gpio-cfg = &lt;1 3&gt;;</div><div class='add'>+				AVDD-supply = &lt;&amp;reg_audio_3v3&gt;;</div><div class='add'>+				DBVDD-supply = &lt;&amp;reg_audio_1v8&gt;;</div><div class='add'>+				DCVDD-supply = &lt;&amp;reg_audio_1v8&gt;;</div><div class='add'>+				SPKVDD1-supply = &lt;&amp;reg_audio_5v&gt;;</div><div class='add'>+				SPKVDD2-supply = &lt;&amp;reg_audio_5v&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@2 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0x2&gt;;</div><div class='add'>+</div><div class='add'>+			wm8960_2: audio-codec@1a {</div><div class='add'>+				compatible = "wlf,wm8960";</div><div class='add'>+				reg = &lt;0x1a&gt;;</div><div class='add'>+				clocks = &lt;&amp;mclkout1_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+				clock-names = "mclk";</div><div class='add'>+				assigned-clocks = &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS&gt;,</div><div class='add'>+						  &lt;&amp;mclkout1_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;786432000&gt;,</div><div class='add'>+						       &lt;49152000&gt;,</div><div class='add'>+						       &lt;12288000&gt;,</div><div class='add'>+						       &lt;12288000&gt;;</div><div class='add'>+				wlf,shared-lrclk;</div><div class='add'>+				wlf,hp-cfg = &lt;2 2 3&gt;;</div><div class='add'>+				wlf,gpio-cfg = &lt;1 3&gt;;</div><div class='add'>+				AVDD-supply = &lt;&amp;reg_audio_3v3&gt;;</div><div class='add'>+				DBVDD-supply = &lt;&amp;reg_audio_1v8&gt;;</div><div class='add'>+				DCVDD-supply = &lt;&amp;reg_audio_1v8&gt;;</div><div class='add'>+				SPKVDD1-supply = &lt;&amp;reg_audio_5v&gt;;</div><div class='add'>+				SPKVDD2-supply = &lt;&amp;reg_audio_5v&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@3 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0x3&gt;;</div><div class='add'>+</div><div class='add'>+			wm8960_3: audio-codec@1a {</div><div class='add'>+				compatible = "wlf,wm8960";</div><div class='add'>+				reg = &lt;0x1a&gt;;</div><div class='add'>+				clocks = &lt;&amp;mclkout1_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+				clock-names = "mclk";</div><div class='add'>+				assigned-clocks = &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS&gt;,</div><div class='add'>+						  &lt;&amp;mclkout1_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;786432000&gt;,</div><div class='add'>+						       &lt;49152000&gt;,</div><div class='add'>+						       &lt;12288000&gt;,</div><div class='add'>+						       &lt;12288000&gt;;</div><div class='add'>+				wlf,shared-lrclk;</div><div class='add'>+				wlf,hp-cfg = &lt;2 2 3&gt;;</div><div class='add'>+				wlf,gpio-cfg = &lt;1 3&gt;;</div><div class='add'>+				AVDD-supply = &lt;&amp;reg_audio_3v3&gt;;</div><div class='add'>+				DBVDD-supply = &lt;&amp;reg_audio_1v8&gt;;</div><div class='add'>+				DCVDD-supply = &lt;&amp;reg_audio_1v8&gt;;</div><div class='add'>+				SPKVDD1-supply = &lt;&amp;reg_audio_5v&gt;;</div><div class='add'>+				SPKVDD2-supply = &lt;&amp;reg_audio_5v&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@4 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0x4&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@5 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0x5&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@6 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0x6&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pca6416_3: gpio@20 {</div><div class='add'>+		compatible = "ti,tca6416";</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;lsio_gpio2&gt;;</div><div class='add'>+		interrupts = &lt;5 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pca9548_2: i2c-mux@70 {</div><div class='add'>+		compatible = "nxp,pca9548";</div><div class='add'>+		reg = &lt;0x70&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		i2c@0 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0x0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@1 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0x1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@2 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0x2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@3 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0x3&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@4 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0x4&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpuart0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpuart1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "nxp,88w8987-bt";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_mu5 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan2&gt;;</div><div class='add'>+	xceiver-supply = &lt;&amp;reg_can0_stby&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan3&gt;;</div><div class='add'>+	xceiver-supply = &lt;&amp;reg_can1_stby&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hsio_phy {</div><div class='add'>+	fsl,hsio-cfg = "pciea-x2-pcieb";</div><div class='add'>+	fsl,refclk-pad-mode = "output";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cm40_intmux {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cm40_lpuart {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_cm40_lpuart&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio4 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio5 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	phys = &lt;&amp;hsio_phy 0 PHY_TYPE_PCIE 0&gt;;</div><div class='add'>+	phy-names = "pcie-phy";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcieb&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	reset-gpio = &lt;&amp;lsio_gpio4 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vpcie-supply = &lt;&amp;reg_pcieb&gt;;</div><div class='add'>+	vpcie3v3aux-supply = &lt;&amp;reg_pcieb&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0_ep {</div><div class='add'>+	phys = &lt;&amp;hsio_phy 0 PHY_TYPE_PCIE 0&gt;;</div><div class='add'>+	phy-names = "pcie-phy";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcieb&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	reset-gpio = &lt;&amp;lsio_gpio4 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vpcie-supply = &lt;&amp;reg_pcieb&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai0&gt;;</div><div class='add'>+	#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS&gt;,</div><div class='add'>+			  &lt;&amp;sai0_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;786432000&gt;, &lt;49152000&gt;, &lt;12288000&gt;, &lt;49152000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai1 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS&gt;,</div><div class='add'>+			  &lt;&amp;sai1_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;786432000&gt;, &lt;49152000&gt;, &lt;12288000&gt;, &lt;49152000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai2 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS&gt;,</div><div class='add'>+			  &lt;&amp;sai2_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;786432000&gt;, &lt;49152000&gt;, &lt;12288000&gt;, &lt;49152000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai2&gt;;</div><div class='add'>+	fsl,sai-asynchronous;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai3 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS&gt;,</div><div class='add'>+			  &lt;&amp;sai3_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;786432000&gt;, &lt;49152000&gt;, &lt;12288000&gt;, &lt;49152000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai3&gt;;</div><div class='add'>+	fsl,sai-asynchronous;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;thermal_zones {</div><div class='add'>+	pmic-thermal {</div><div class='add'>+		polling-delay-passive = &lt;250&gt;;</div><div class='add'>+		polling-delay = &lt;2000&gt;;</div><div class='add'>+		thermal-sensors = &lt;&amp;tsens IMX_SC_R_PMIC_0&gt;;</div><div class='add'>+</div><div class='add'>+		trips {</div><div class='add'>+			pmic_alert0: trip0 {</div><div class='add'>+				temperature = &lt;110000&gt;;</div><div class='add'>+				hysteresis = &lt;2000&gt;;</div><div class='add'>+				type = "passive";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pmic_crit0: trip1 {</div><div class='add'>+				temperature = &lt;125000&gt;;</div><div class='add'>+				hysteresis = &lt;2000&gt;;</div><div class='add'>+				type = "critical";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cooling-maps {</div><div class='add'>+			map0 {</div><div class='add'>+				trip = &lt;&amp;pmic_alert0&gt;;</div><div class='add'>+				cooling-device =</div><div class='add'>+					&lt;&amp;A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+					&lt;&amp;A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbphy1 {</div><div class='add'>+	/* USB eye diagram tests result */</div><div class='add'>+	fsl,tx-d-cal = &lt;114&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usbotg1&gt;;</div><div class='add'>+	srp-disable;</div><div class='add'>+	hnp-disable;</div><div class='add'>+	adp-disable;</div><div class='add'>+	power-active-high;</div><div class='add'>+	disable-over-current;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbphy2 {</div><div class='add'>+	/* USB eye diagram tests result */</div><div class='add'>+	fsl,tx-d-cal = &lt;111&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usbotg2&gt;;</div><div class='add'>+	srp-disable;</div><div class='add'>+	hnp-disable;</div><div class='add'>+	adp-disable;</div><div class='add'>+	power-active-high;</div><div class='add'>+	disable-over-current;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	no-sd;</div><div class='add'>+	no-sdio;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;lsio_gpio5 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	wp-gpios = &lt;&amp;lsio_gpio5 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	max-frequency = &lt;100000000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpspi3 {</div><div class='add'>+	fsl,spi-only-use-cs1-sel;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpspi3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hog&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl_hog: hoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD	0x000514a0</div><div class='add'>+			IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD	0x000014a0</div><div class='add'>+			IMX8DXL_SPI3_CS0_ADMA_ACM_MCLK_OUT1		0x0600004c</div><div class='add'>+			IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO05_IN	0x0600004c</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usbotg1: usbotg1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8DXL_USB_SS3_TC0_CONN_USB_OTG1_PWR		0x00000021</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usbotg2: usbotg2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8DXL_USB_SS3_TC1_CONN_USB_OTG2_PWR		0x00000021</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_eqos: eqosgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8DXL_ENET0_MDC_CONN_EQOS_MDC				0x06000020</div><div class='add'>+			IMX8DXL_ENET0_MDIO_CONN_EQOS_MDIO			0x06000020</div><div class='add'>+			IMX8DXL_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC		0x06000020</div><div class='add'>+			IMX8DXL_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0		0x06000020</div><div class='add'>+			IMX8DXL_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1		0x06000020</div><div class='add'>+			IMX8DXL_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2		0x06000020</div><div class='add'>+			IMX8DXL_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3		0x06000020</div><div class='add'>+			IMX8DXL_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL	0x06000020</div><div class='add'>+			IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC		0x06000020</div><div class='add'>+			IMX8DXL_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0		0x06000020</div><div class='add'>+			IMX8DXL_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1		0x06000020</div><div class='add'>+			IMX8DXL_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2		0x06000020</div><div class='add'>+			IMX8DXL_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3		0x06000020</div><div class='add'>+			IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL	0x06000020</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexspi0: flexspi0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8DXL_QSPI0A_DATA0_LSIO_QSPI0A_DATA0     0x06000021</div><div class='add'>+			IMX8DXL_QSPI0A_DATA1_LSIO_QSPI0A_DATA1     0x06000021</div><div class='add'>+			IMX8DXL_QSPI0A_DATA2_LSIO_QSPI0A_DATA2     0x06000021</div><div class='add'>+			IMX8DXL_QSPI0A_DATA3_LSIO_QSPI0A_DATA3     0x06000021</div><div class='add'>+			IMX8DXL_QSPI0A_DQS_LSIO_QSPI0A_DQS         0x06000021</div><div class='add'>+			IMX8DXL_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B     0x06000021</div><div class='add'>+			IMX8DXL_QSPI0A_SCLK_LSIO_QSPI0A_SCLK       0x06000021</div><div class='add'>+			IMX8DXL_QSPI0B_SCLK_LSIO_QSPI0B_SCLK       0x06000021</div><div class='add'>+			IMX8DXL_QSPI0B_DATA0_LSIO_QSPI0B_DATA0     0x06000021</div><div class='add'>+			IMX8DXL_QSPI0B_DATA1_LSIO_QSPI0B_DATA1     0x06000021</div><div class='add'>+			IMX8DXL_QSPI0B_DATA2_LSIO_QSPI0B_DATA2     0x06000021</div><div class='add'>+			IMX8DXL_QSPI0B_DATA3_LSIO_QSPI0B_DATA3     0x06000021</div><div class='add'>+			IMX8DXL_QSPI0B_DQS_LSIO_QSPI0B_DQS         0x06000021</div><div class='add'>+			IMX8DXL_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B     0x06000021</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan2: flexcan2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8DXL_UART2_TX_ADMA_FLEXCAN1_TX	0x00000021</div><div class='add'>+			IMX8DXL_UART2_RX_ADMA_FLEXCAN1_RX	0x00000021</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan3: flexcan3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8DXL_FLEXCAN2_TX_ADMA_FLEXCAN2_TX	0x00000021</div><div class='add'>+			IMX8DXL_FLEXCAN2_RX_ADMA_FLEXCAN2_RX	0x00000021</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec1: fec1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD		0x000014a0</div><div class='add'>+			IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD		0x000014a0</div><div class='add'>+			IMX8DXL_ENET0_MDC_CONN_ENET0_MDC			0x06000020</div><div class='add'>+			IMX8DXL_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020</div><div class='add'>+			IMX8DXL_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC		0x00000060</div><div class='add'>+			IMX8DXL_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0		0x00000060</div><div class='add'>+			IMX8DXL_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1		0x00000060</div><div class='add'>+			IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2		0x00000060</div><div class='add'>+			IMX8DXL_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3		0x00000060</div><div class='add'>+			IMX8DXL_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x00000060</div><div class='add'>+			IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC		0x00000060</div><div class='add'>+			IMX8DXL_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0		0x00000060</div><div class='add'>+			IMX8DXL_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1		0x00000060</div><div class='add'>+			IMX8DXL_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2		0x00000060</div><div class='add'>+			IMX8DXL_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3		0x00000060</div><div class='add'>+			IMX8DXL_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x00000060</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpspi3: lpspi3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK		0x6000040</div><div class='add'>+			IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO		0x6000040</div><div class='add'>+			IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI		0x6000040</div><div class='add'>+			IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1		0x6000040</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA		0x06000021</div><div class='add'>+			IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL		0x06000021</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_cm40_lpuart: cm40lpuartgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8DXL_ADC_IN2_M40_UART0_RX		0x06000020</div><div class='add'>+			IMX8DXL_ADC_IN3_M40_UART0_TX		0x06000020</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA		0x06000021</div><div class='add'>+			IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL		0x06000021</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpuart0: lpuart0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8DXL_UART0_RX_ADMA_UART0_RX		0x06000020</div><div class='add'>+			IMX8DXL_UART0_TX_ADMA_UART0_TX		0x06000020</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpuart1: lpuart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8DXL_UART1_TX_ADMA_UART1_TX          0x06000020</div><div class='add'>+			IMX8DXL_UART1_RX_ADMA_UART1_RX          0x06000020</div><div class='add'>+			IMX8DXL_UART1_RTS_B_ADMA_UART1_RTS_B    0x06000020</div><div class='add'>+			IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B    0x06000020</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcieb: pcieagrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8DXL_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00	0x06000021</div><div class='add'>+			IMX8DXL_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01	0x06000021</div><div class='add'>+			IMX8DXL_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02	0x04000021</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai0: sai0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8DXL_SPI0_CS0_ADMA_SAI0_RXD		0x06000060</div><div class='add'>+			IMX8DXL_SPI0_CS1_ADMA_SAI0_RXC		0x06000040</div><div class='add'>+			IMX8DXL_SPI0_SCK_ADMA_SAI0_TXC		0x06000060</div><div class='add'>+			IMX8DXL_SPI0_SDI_ADMA_SAI0_TXD		0x06000060</div><div class='add'>+			IMX8DXL_SPI0_SDO_ADMA_SAI0_TXFS		0x06000040</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai1: sai1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8DXL_FLEXCAN0_RX_ADMA_SAI1_TXC	0x06000040</div><div class='add'>+			IMX8DXL_FLEXCAN0_TX_ADMA_SAI1_TXFS	0x06000040</div><div class='add'>+			IMX8DXL_FLEXCAN1_RX_ADMA_SAI1_TXD	0x06000060</div><div class='add'>+			IMX8DXL_FLEXCAN1_TX_ADMA_SAI1_RXD	0x06000060</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai2: sai2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8DXL_SNVS_TAMPER_OUT3_ADMA_SAI2_RXC	0x06000040</div><div class='add'>+			IMX8DXL_SNVS_TAMPER_IN0_ADMA_SAI2_RXFS	0x06000040</div><div class='add'>+			IMX8DXL_SNVS_TAMPER_OUT4_ADMA_SAI2_RXD	0x06000060</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai3: sai3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8DXL_SNVS_TAMPER_IN1_ADMA_SAI3_RXC	0x06000040</div><div class='add'>+			IMX8DXL_SNVS_TAMPER_IN3_ADMA_SAI3_RXFS	0x06000040</div><div class='add'>+			IMX8DXL_SNVS_TAMPER_IN2_ADMA_SAI3_RXD	0x06000060</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK	0x06000041</div><div class='add'>+			IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD	0x00000021</div><div class='add'>+			IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021</div><div class='add'>+			IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021</div><div class='add'>+			IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021</div><div class='add'>+			IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021</div><div class='add'>+			IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021</div><div class='add'>+			IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021</div><div class='add'>+			IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021</div><div class='add'>+			IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021</div><div class='add'>+			IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8DXL_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30	0x00000040 /* RESET_B */</div><div class='add'>+			IMX8DXL_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00	0x00000021 /* WP */</div><div class='add'>+			IMX8DXL_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01	0x00000021 /* CD */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK		0x06000041</div><div class='add'>+			IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD	0x00000021</div><div class='add'>+			IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0	0x00000021</div><div class='add'>+			IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1	0x00000021</div><div class='add'>+			IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2	0x00000021</div><div class='add'>+			IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3	0x00000021</div><div class='add'>+			IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT	0x00000021</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi<br/>new file mode 100644<br/>index 000000000000..7a191195dbd9<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi</a></div><div class='hunk'>@@ -0,0 +1,260 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2019~2020, 2022 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/delete-node/ &amp;asrc1;</div><div class='add'>+/delete-node/ &amp;asrc1_lpcg;</div><div class='add'>+/delete-node/ &amp;adc1;</div><div class='add'>+/delete-node/ &amp;adc1_lpcg;</div><div class='add'>+/delete-node/ &amp;amix;</div><div class='add'>+/delete-node/ &amp;amix_lpcg;</div><div class='add'>+/delete-node/ &amp;edma1;</div><div class='add'>+/delete-node/ &amp;esai0;</div><div class='add'>+/delete-node/ &amp;esai0_lpcg;</div><div class='add'>+/delete-node/ &amp;sai4;</div><div class='add'>+/delete-node/ &amp;sai4_lpcg;</div><div class='add'>+/delete-node/ &amp;sai5;</div><div class='add'>+/delete-node/ &amp;sai5_lpcg;</div><div class='add'>+</div><div class='add'>+&amp;acm {</div><div class='add'>+	compatible = "fsl,imx8dxl-acm";</div><div class='add'>+	power-domains = &lt;&amp;pd IMX_SC_R_AUDIO_CLK_0&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_AUDIO_CLK_1&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_MCLK_OUT_0&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_MCLK_OUT_1&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_AUDIO_PLL_0&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_AUDIO_PLL_1&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_ASRC_0&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_SAI_0&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_SAI_1&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_SAI_2&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_SAI_3&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_SPDIF_0&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_MQS_0&gt;;</div><div class='add'>+	clocks = &lt;&amp;aud_rec0_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+		 &lt;&amp;aud_rec1_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+		 &lt;&amp;aud_pll_div0_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+		 &lt;&amp;aud_pll_div1_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+		 &lt;&amp;clk_ext_aud_mclk0&gt;,</div><div class='add'>+		 &lt;&amp;clk_ext_aud_mclk1&gt;,</div><div class='add'>+		 &lt;&amp;clk_spdif0_rx&gt;,</div><div class='add'>+		 &lt;&amp;clk_sai0_rx_bclk&gt;,</div><div class='add'>+		 &lt;&amp;clk_sai0_tx_bclk&gt;,</div><div class='add'>+		 &lt;&amp;clk_sai1_rx_bclk&gt;,</div><div class='add'>+		 &lt;&amp;clk_sai1_tx_bclk&gt;,</div><div class='add'>+		 &lt;&amp;clk_sai2_rx_bclk&gt;,</div><div class='add'>+		 &lt;&amp;clk_sai3_rx_bclk&gt;;</div><div class='add'>+	clock-names = "aud_rec_clk0_lpcg_clk",</div><div class='add'>+		      "aud_rec_clk1_lpcg_clk",</div><div class='add'>+		      "aud_pll_div_clk0_lpcg_clk",</div><div class='add'>+		      "aud_pll_div_clk1_lpcg_clk",</div><div class='add'>+		      "ext_aud_mclk0",</div><div class='add'>+		      "ext_aud_mclk1",</div><div class='add'>+		      "spdif0_rx",</div><div class='add'>+		      "sai0_rx_bclk",</div><div class='add'>+		      "sai0_tx_bclk",</div><div class='add'>+		      "sai1_rx_bclk",</div><div class='add'>+		      "sai1_tx_bclk",</div><div class='add'>+		      "sai2_rx_bclk",</div><div class='add'>+		      "sai3_rx_bclk";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;audio_ipg_clk {</div><div class='add'>+	clock-frequency = &lt;160000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dma_ipg_clk {</div><div class='add'>+	clock-frequency = &lt;160000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;adc0 {</div><div class='add'>+	interrupts = &lt;GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;edma0 {</div><div class='add'>+	reg = &lt;0x591f0000 0x1a0000&gt;;</div><div class='add'>+	#dma-cells = &lt;3&gt;;</div><div class='add'>+	dma-channels = &lt;25&gt;;</div><div class='add'>+	dma-channel-mask = &lt;0x1c0cc0&gt;;</div><div class='add'>+	interrupts = &lt;GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH&gt;, /* asrc 0 */</div><div class='add'>+		&lt;GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		&lt;GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		&lt;GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		&lt;GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		&lt;GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		&lt;GIC_SPI 0   IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		&lt;GIC_SPI 0   IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		&lt;GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH&gt;, /* spdif0 */</div><div class='add'>+		&lt;GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		&lt;GIC_SPI 0   IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		&lt;GIC_SPI 0   IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		&lt;GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH&gt;, /* sai0 */</div><div class='add'>+		&lt;GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		&lt;GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH&gt;, /* sai1 */</div><div class='add'>+		&lt;GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		&lt;GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH&gt;, /* sai2 */</div><div class='add'>+		&lt;GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH&gt;, /* sai3 */</div><div class='add'>+		&lt;GIC_SPI 0   IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		&lt;GIC_SPI 0   IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		&lt;GIC_SPI 0   IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		&lt;GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH&gt;, /* gpt0 */</div><div class='add'>+		&lt;GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH&gt;, /* gpt1 */</div><div class='add'>+		&lt;GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH&gt;, /* gpt2 */</div><div class='add'>+		&lt;GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH&gt;, /* gpt3 */</div><div class='add'>+		&lt;GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	power-domains = &lt;&amp;pd IMX_SC_R_DMA_0_CH0&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_0_CH1&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_0_CH2&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_0_CH3&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_0_CH4&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_0_CH5&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_0_CH6&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_0_CH7&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_0_CH8&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_0_CH9&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_0_CH10&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_0_CH11&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_0_CH12&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_0_CH13&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_0_CH14&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_0_CH15&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_0_CH16&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_0_CH17&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_0_CH18&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_0_CH19&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_0_CH20&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_0_CH21&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_0_CH22&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_0_CH23&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_0_CH24&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;edma2 {</div><div class='add'>+	interrupts = &lt;GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;edma3 {</div><div class='add'>+	interrupts = &lt;GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	interrupts = &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan2 {</div><div class='add'>+	interrupts = &lt;GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan3 {</div><div class='add'>+	interrupts = &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+	interrupts = &lt;GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	dma-names = "tx","rx";</div><div class='add'>+	dmas = &lt;&amp;edma3 1 0 0&gt;, &lt;&amp;edma3 0 0 FSL_EDMA_RX&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+	interrupts = &lt;GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	dma-names = "tx","rx";</div><div class='add'>+	dmas = &lt;&amp;edma3 3 0 0&gt;, &lt;&amp;edma3 2 0 FSL_EDMA_RX&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+	interrupts = &lt;GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	dma-names = "tx","rx";</div><div class='add'>+	dmas = &lt;&amp;edma3 5 0 0&gt;, &lt;&amp;edma3 4 0 FSL_EDMA_RX&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+	interrupts = &lt;GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	dma-names = "tx","rx";</div><div class='add'>+	dmas = &lt;&amp;edma3 7 0 0&gt;, &lt;&amp;edma3 6 0 FSL_EDMA_RX&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart0 {</div><div class='add'>+	compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart";</div><div class='add'>+	interrupts = &lt;GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart1 {</div><div class='add'>+	compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart";</div><div class='add'>+	interrupts = &lt;GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart2 {</div><div class='add'>+	compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart";</div><div class='add'>+	interrupts = &lt;GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart3 {</div><div class='add'>+	compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart";</div><div class='add'>+	interrupts = &lt;GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpspi0 {</div><div class='add'>+	interrupts = &lt;GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpspi1 {</div><div class='add'>+	interrupts = &lt;GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpspi2 {</div><div class='add'>+	interrupts = &lt;GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpspi3 {</div><div class='add'>+	interrupts = &lt;GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai0 {</div><div class='add'>+	interrupts = &lt;GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai1 {</div><div class='add'>+	interrupts = &lt;GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai2 {</div><div class='add'>+	interrupts = &lt;GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai3 {</div><div class='add'>+	interrupts = &lt;GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spdif0 {</div><div class='add'>+	interrupts = &lt;GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH&gt;, /* rx */</div><div class='add'>+		     &lt;GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH&gt;; /* tx */</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi<br/>new file mode 100644<br/>index 000000000000..74f9ce493248<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi</a></div><div class='hunk'>@@ -0,0 +1,171 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2019~2020, 2022 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/delete-node/ &amp;enet1_lpcg;</div><div class='add'>+/delete-node/ &amp;fec2;</div><div class='add'>+/delete-node/ &amp;usbotg3;</div><div class='add'>+/delete-node/ &amp;usb3_phy;</div><div class='add'>+/delete-node/ &amp;usb3_lpcg;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	conn_enet0_root_clk: clock-conn-enet0-root {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;250000000&gt;;</div><div class='add'>+		clock-output-names = "conn_enet0_root_clk";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_dummy: clock-dummy {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;0&gt;;</div><div class='add'>+		clock-output-names = "clk_dummy";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;conn_subsys {</div><div class='add'>+	eqos: ethernet@5b050000 {</div><div class='add'>+		compatible = "nxp,imx8dxl-dwmac-eqos", "snps,dwmac-5.10a";</div><div class='add'>+		reg = &lt;0x5b050000 0x10000&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-names = "macirq", "eth_wake_irq";</div><div class='add'>+		clocks = &lt;&amp;eqos_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;eqos_lpcg IMX_LPCG_CLK_6&gt;,</div><div class='add'>+			 &lt;&amp;eqos_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;eqos_lpcg IMX_LPCG_CLK_5&gt;,</div><div class='add'>+			 &lt;&amp;eqos_lpcg IMX_LPCG_CLK_2&gt;;</div><div class='add'>+		clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem";</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;125000000&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_ENET_1&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usbotg2: usb@5b0e0000 {</div><div class='add'>+		compatible = "fsl,imx8dxl-usb", "fsl,imx7ulp-usb", "fsl,imx6ul-usb";</div><div class='add'>+		reg = &lt;0x5b0e0000 0x200&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		fsl,usbphy = &lt;&amp;usbphy2&gt;;</div><div class='add'>+		fsl,usbmisc = &lt;&amp;usbmisc2 0&gt;;</div><div class='add'>+		/*</div><div class='add'>+		 * usbotg1 and usbotg2 share one clcok.</div><div class='add'>+		 * scu firmware disables the access to the clock and keeps</div><div class='add'>+		 * it always on in case other core (M4) uses one of these.</div><div class='add'>+		 */</div><div class='add'>+		clocks = &lt;&amp;clk_dummy&gt;;</div><div class='add'>+		ahb-burst-config = &lt;0x0&gt;;</div><div class='add'>+		tx-burst-size-dword = &lt;0x10&gt;;</div><div class='add'>+		rx-burst-size-dword = &lt;0x10&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_USB_1&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usbmisc2: usbmisc@5b0e0200 {</div><div class='add'>+		#index-cells = &lt;1&gt;;</div><div class='add'>+		compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";</div><div class='add'>+		reg = &lt;0x5b0e0200 0x200&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usbphy2: usbphy@5b110000 {</div><div class='add'>+		compatible = "fsl,imx8dxl-usbphy", "fsl,imx7ulp-usbphy";</div><div class='add'>+		reg = &lt;0x5b110000 0x1000&gt;;</div><div class='add'>+		clocks = &lt;&amp;usb2_2_lpcg IMX_LPCG_CLK_7&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_USB_1_PHY&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eqos_lpcg: clock-controller@5b240000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5b240000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;conn_enet0_root_clk&gt;,</div><div class='add'>+			 &lt;&amp;conn_axi_clk&gt;,</div><div class='add'>+			 &lt;&amp;conn_axi_clk&gt;,</div><div class='add'>+			 &lt;&amp;clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;conn_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_2&gt;,</div><div class='add'>+				&lt;IMX_LPCG_CLK_4&gt;, &lt;IMX_LPCG_CLK_5&gt;,</div><div class='add'>+				&lt;IMX_LPCG_CLK_6&gt;;</div><div class='add'>+		clock-output-names = "eqos_ptp",</div><div class='add'>+				     "eqos_mem_clk",</div><div class='add'>+				     "eqos_aclk",</div><div class='add'>+				     "eqos_clk",</div><div class='add'>+				     "eqos_csr_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_ENET_1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb2_2_lpcg: clock-controller@5b280000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5b280000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_7&gt;;</div><div class='add'>+		clocks = &lt;&amp;conn_ipg_clk&gt;;</div><div class='add'>+		clock-output-names = "usboh3_2_phy_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_USB_1_PHY&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dma_apbh {</div><div class='add'>+	interrupts = &lt;GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;enet0_lpcg {</div><div class='add'>+	clocks = &lt;&amp;conn_enet0_root_clk&gt;,</div><div class='add'>+		 &lt;&amp;conn_enet0_root_clk&gt;,</div><div class='add'>+		 &lt;&amp;conn_axi_clk&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK&gt;,</div><div class='add'>+		 &lt;&amp;conn_ipg_clk&gt;,</div><div class='add'>+		 &lt;&amp;conn_ipg_clk&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	compatible = "fsl,imx8dxl-fec", "fsl,imx8qm-fec", "fsl,imx6sx-fec";</div><div class='add'>+	interrupts = &lt;GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;125000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpmi {</div><div class='add'>+	interrupts = &lt;GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbphy1 {</div><div class='add'>+	compatible = "fsl,imx8dxl-usbphy", "fsl,imx7ulp-usbphy";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";</div><div class='add'>+	interrupts = &lt;GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";</div><div class='add'>+	interrupts = &lt;GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";</div><div class='add'>+	interrupts = &lt;GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	interrupts = &lt;GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	/*</div><div class='add'>+	 * usbotg1 and usbotg2 share one clock</div><div class='add'>+	 * scfw disable clock access and keep it always on</div><div class='add'>+	 * in case other core (M4) use one of these.</div><div class='add'>+	 */</div><div class='add'>+	clocks = &lt;&amp;clk_dummy&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi<br/>new file mode 100644<br/>index 000000000000..3569abb5bb9b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi</a></div><div class='hunk'>@@ -0,0 +1,9 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2020 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;ddr_pmu0 {</div><div class='add'>+	compatible = "fsl,imx8dxl-ddr-pmu", "fsl,imx8-ddr-pmu";</div><div class='add'>+	interrupts = &lt;GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi<br/>new file mode 100644<br/>index 000000000000..5c0d09c5c086<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi</a></div><div class='hunk'>@@ -0,0 +1,61 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;hsio_subsys {</div><div class='add'>+	phyx1_lpcg: clock-controller@5f090000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5f090000 0x10000&gt;;</div><div class='add'>+		clocks = &lt;&amp;hsio_refb_clk&gt;, &lt;&amp;hsio_per_clk&gt;,</div><div class='add'>+			 &lt;&amp;hsio_per_clk&gt;, &lt;&amp;hsio_per_clk&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_1&gt;,</div><div class='add'>+				&lt;IMX_LPCG_CLK_2&gt;, &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "hsio_phyx1_pclk",</div><div class='add'>+				     "hsio_phyx1_epcs_tx_clk",</div><div class='add'>+				     "hsio_phyx1_epcs_rx_clk",</div><div class='add'>+				     "hsio_phyx1_apb_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SERDES_1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsio_phy: phy@5f1a0000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-hsio";</div><div class='add'>+		reg = &lt;0x5f1a0000 0x10000&gt;,</div><div class='add'>+		      &lt;0x5f120000 0x10000&gt;,</div><div class='add'>+		      &lt;0x5f140000 0x10000&gt;,</div><div class='add'>+		      &lt;0x5f160000 0x10000&gt;;</div><div class='add'>+		reg-names = "reg", "phy", "ctrl", "misc";</div><div class='add'>+		clocks = &lt;&amp;phyx1_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;phyx1_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;phyx1_crr1_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;pcieb_crr3_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;misc_crr5_lpcg IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-names = "pclk0", "apb_pclk0", "phy0_crr", "ctl0_crr",</div><div class='add'>+			      "misc_crr";</div><div class='add'>+		#phy-cells = &lt;3&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SERDES_1&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0: pcie@5f010000 {</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-names = "msi";</div><div class='add'>+		interrupt-map = &lt;0 0 0 1 &amp;gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 0 2 &amp;gic GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 0 3 &amp;gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 0 4 &amp;gic GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-map-mask = &lt;0 0 0 0x7&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_ep: pcie-ep@5f010000 {</div><div class='add'>+		interrupts = &lt;GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-names = "dma";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcieb_ep {</div><div class='add'>+	interrupts = &lt;GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	interrupt-names = "dma";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi<br/>new file mode 100644<br/>index 000000000000..5f4f789e4a73<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi</a></div><div class='hunk'>@@ -0,0 +1,120 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2019~2020, 2022 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;flexspi0 {</div><div class='add'>+	compatible = "nxp,imx8dxl-fspi";</div><div class='add'>+	interrupts = &lt;GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio0 {</div><div class='add'>+	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";</div><div class='add'>+	interrupts = &lt;GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	gpio-ranges = &lt;&amp;iomuxc 0 47 13&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 13 61 4&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 19 67 4&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 24 72 1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio1 {</div><div class='add'>+	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";</div><div class='add'>+	interrupts = &lt;GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	gpio-ranges = &lt;&amp;iomuxc 4 74 5&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 9 80 16&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio2 {</div><div class='add'>+	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";</div><div class='add'>+	interrupts = &lt;GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	gpio-ranges = &lt;&amp;iomuxc 1 98 2&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 3 101 1&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 5 107 8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio3 {</div><div class='add'>+	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";</div><div class='add'>+	interrupts = &lt;GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	gpio-ranges = &lt;&amp;iomuxc 0 115 4&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 9 121 1&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 10 120 1&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 11 123 1&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 12 122 1&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 13 125 1&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 14 124 1&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 16 126 1&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 17 128 1&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 18 131 1&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 19 130 1&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 20 133 1&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 21 132 1&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 22 129 1&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 23 134 1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio4 {</div><div class='add'>+	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";</div><div class='add'>+	interrupts = &lt;GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	gpio-ranges = &lt;&amp;iomuxc 0 0 3&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 3 4 4&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 7 9 12&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 19 22 2&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 21 25 2&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 29 29 3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio5 {</div><div class='add'>+	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";</div><div class='add'>+	interrupts = &lt;GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	gpio-ranges = &lt;&amp;iomuxc 0 32 3&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 3 36 6&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 9 43 3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio6 {</div><div class='add'>+	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";</div><div class='add'>+	interrupts = &lt;GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	gpio-ranges = &lt;&amp;iomuxc 0 53 7&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 8 86 10&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 19 107 8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio7 {</div><div class='add'>+	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";</div><div class='add'>+	interrupts = &lt;GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	gpio-ranges = &lt;&amp;iomuxc 0 0 3&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 3 4 4&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 8 22 2&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 10 25 2&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 16 44 2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_mu0 {</div><div class='add'>+	compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";</div><div class='add'>+	interrupts = &lt;GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_mu1 {</div><div class='add'>+	compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";</div><div class='add'>+	interrupts = &lt;GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_mu2 {</div><div class='add'>+	compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";</div><div class='add'>+	interrupts = &lt;GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_mu3 {</div><div class='add'>+	compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";</div><div class='add'>+	interrupts = &lt;GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_mu4 {</div><div class='add'>+	compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";</div><div class='add'>+	interrupts = &lt;GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_mu5 {</div><div class='add'>+	compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";</div><div class='add'>+	interrupts = &lt;GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi<br/>new file mode 100644<br/>index 000000000000..8d60827822ed<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8dxl.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8dxl.dtsi</a></div><div class='hunk'>@@ -0,0 +1,263 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2019~2020, 2022 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/imx8-clock.h&gt;</div><div class='add'>+#include &lt;dt-bindings/dma/fsl-edma.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/imx8-lpcg.h&gt;</div><div class='add'>+#include &lt;dt-bindings/firmware/imx/rsrc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/pads-imx8dxl.h&gt;</div><div class='add'>+#include &lt;dt-bindings/thermal/thermal.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;fec1;</div><div class='add'>+		ethernet1 = &amp;eqos;</div><div class='add'>+		gpio0 = &amp;lsio_gpio0;</div><div class='add'>+		gpio1 = &amp;lsio_gpio1;</div><div class='add'>+		gpio2 = &amp;lsio_gpio2;</div><div class='add'>+		gpio3 = &amp;lsio_gpio3;</div><div class='add'>+		gpio4 = &amp;lsio_gpio4;</div><div class='add'>+		gpio5 = &amp;lsio_gpio5;</div><div class='add'>+		gpio6 = &amp;lsio_gpio6;</div><div class='add'>+		gpio7 = &amp;lsio_gpio7;</div><div class='add'>+		mu1 = &amp;lsio_mu1;</div><div class='add'>+		spi0 = &amp;lpspi0;</div><div class='add'>+		spi1 = &amp;lpspi1;</div><div class='add'>+		spi2 = &amp;lpspi2;</div><div class='add'>+		spi3 = &amp;lpspi3;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus: cpus {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		/* We have 1 clusters with 2 Cortex-A35 cores */</div><div class='add'>+		A35_0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a35";</div><div class='add'>+			reg = &lt;0x0 0x0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;A35_L2&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;a35_opp_table&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		A35_1: cpu@1 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a35";</div><div class='add'>+			reg = &lt;0x0 0x1&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;A35_L2&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;a35_opp_table&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		A35_L2: l2-cache0 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	a35_opp_table: opp-table {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+		opp-shared;</div><div class='add'>+</div><div class='add'>+		opp-900000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;900000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1000000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;150000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1200000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1200000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1100000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;150000&gt;;</div><div class='add'>+			opp-suspend;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gic: interrupt-controller@51a00000 {</div><div class='add'>+		compatible = "arm,gic-v3";</div><div class='add'>+		reg = &lt;0x0 0x51a00000 0 0x10000&gt;, /* GIC Dist */</div><div class='add'>+		      &lt;0x0 0x51b00000 0 0xc0000&gt;; /* GICR (RD_base + SGI_base) */</div><div class='add'>+		#address-cells = &lt;0&gt;;</div><div class='add'>+		#interrupt-cells = &lt;3&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		dsp_reserved: dsp@92400000 {</div><div class='add'>+			reg = &lt;0 0x92400000 0 0x2000000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu {</div><div class='add'>+		compatible = "arm,cortex-a35-pmu";</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-1.0";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	system-controller {</div><div class='add'>+		compatible = "fsl,imx-scu";</div><div class='add'>+		mbox-names = "tx0",</div><div class='add'>+			     "rx0",</div><div class='add'>+			     "gip3";</div><div class='add'>+		mboxes = &lt;&amp;lsio_mu1 0 0</div><div class='add'>+			  &amp;lsio_mu1 1 0</div><div class='add'>+			  &amp;lsio_mu1 3 3&gt;;</div><div class='add'>+</div><div class='add'>+		pd: power-controller {</div><div class='add'>+			compatible = "fsl,imx8dl-scu-pd", "fsl,scu-pd";</div><div class='add'>+			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		clk: clock-controller {</div><div class='add'>+			compatible = "fsl,imx8dxl-clk", "fsl,scu-clk";</div><div class='add'>+			#clock-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		scu_gpio: gpio {</div><div class='add'>+			compatible = "fsl,imx8qxp-sc-gpio";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		iomuxc: pinctrl {</div><div class='add'>+			compatible = "fsl,imx8dxl-iomuxc";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ocotp: ocotp {</div><div class='add'>+			compatible = "fsl,imx8qxp-scu-ocotp";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			fec_mac0: mac@2c4 {</div><div class='add'>+				reg = &lt;0x2c4 6&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			fec_mac1: mac@2c6 {</div><div class='add'>+				reg = &lt;0x2c6 6&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rtc: rtc {</div><div class='add'>+			compatible = "fsl,imx8qxp-sc-rtc";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sc_pwrkey: keys {</div><div class='add'>+			compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";</div><div class='add'>+			linux,keycodes = &lt;KEY_POWER&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		watchdog {</div><div class='add'>+			compatible = "fsl,imx8dxl-sc-wdt", "fsl,imx-sc-wdt";</div><div class='add'>+			timeout-sec = &lt;60&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tsens: thermal-sensor {</div><div class='add'>+			compatible = "fsl,imx8dxl-sc-thermal", "fsl,imx-sc-thermal";</div><div class='add'>+			#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 IRQ_TYPE_LEVEL_LOW&gt;, /* Physical Secure */</div><div class='add'>+			     &lt;GIC_PPI 14 IRQ_TYPE_LEVEL_LOW&gt;, /* Physical Non-Secure */</div><div class='add'>+			     &lt;GIC_PPI 11 IRQ_TYPE_LEVEL_LOW&gt;, /* Virtual */</div><div class='add'>+			     &lt;GIC_PPI 10 IRQ_TYPE_LEVEL_LOW&gt;; /* Hypervisor */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	thermal_zones: thermal-zones {</div><div class='add'>+		cpu-thermal {</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			polling-delay = &lt;2000&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens IMX_SC_R_SYSTEM&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu_alert0: trip0 {</div><div class='add'>+					temperature = &lt;107000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+				cpu_crit0: trip1 {</div><div class='add'>+					temperature = &lt;127000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu_alert0&gt;;</div><div class='add'>+					cooling-device =</div><div class='add'>+					&lt;&amp;A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+					&lt;&amp;A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* The two values below cannot be changed by the board */</div><div class='add'>+	xtal32k: clock-xtal32k {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;32768&gt;;</div><div class='add'>+		clock-output-names = "xtal_32KHz";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	xtal24m: clock-xtal24m {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+		clock-output-names = "xtal_24MHz";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* sorted in register address */</div><div class='add'>+	#include "imx8-ss-cm40.dtsi"</div><div class='add'>+	#include "imx8-ss-adma.dtsi"</div><div class='add'>+	#include "imx8-ss-conn.dtsi"</div><div class='add'>+	#include "imx8-ss-ddr.dtsi"</div><div class='add'>+	#include "imx8-ss-lsio.dtsi"</div><div class='add'>+	#include "imx8-ss-hsio.dtsi"</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include "imx8dxl-ss-adma.dtsi"</div><div class='add'>+#include "imx8dxl-ss-conn.dtsi"</div><div class='add'>+#include "imx8dxl-ss-lsio.dtsi"</div><div class='add'>+#include "imx8dxl-ss-ddr.dtsi"</div><div class='add'>+#include "imx8dxl-ss-hsio.dtsi"</div><div class='add'>+</div><div class='add'>+&amp;cm40_intmux {</div><div class='add'>+	interrupts = &lt;GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8dxp-tqma8xdp-mba8xx.dts b/arch/arm64/boot/dts/freescale/imx8dxp-tqma8xdp-mba8xx.dts<br/>new file mode 100644<br/>index 000000000000..f35514b7b338<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8dxp-tqma8xdp-mba8xx.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8dxp-tqma8xdp-mba8xx.dts</a></div><div class='hunk'>@@ -0,0 +1,16 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR X11)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2018-2023 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Alexander Stein</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8dxp-tqma8xdp.dtsi"</div><div class='add'>+#include "mba8xx.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "TQ-Systems i.MX8DXP TQMa8XDP on MBa8Xx";</div><div class='add'>+	compatible = "tq,imx8dxp-tqma8xdp-mba8xx", "tq,imx8dxp-tqma8xdp", "fsl,imx8dxp";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8dxp-tqma8xdp.dtsi b/arch/arm64/boot/dts/freescale/imx8dxp-tqma8xdp.dtsi<br/>new file mode 100644<br/>index 000000000000..e2de8517aa0e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8dxp-tqma8xdp.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8dxp-tqma8xdp.dtsi</a></div><div class='hunk'>@@ -0,0 +1,24 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR X11)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2018-2023 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Alexander Stein</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "imx8dxp.dtsi"</div><div class='add'>+#include "tqma8xx.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "TQ-Systems i.MX8DXP TQMa8XDP";</div><div class='add'>+	compatible = "tq,imx8dxp-tqma8xdp", "fsl,imx8dxp";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pmic_thermal {</div><div class='add'>+	cooling-maps {</div><div class='add'>+		map0 {</div><div class='add'>+			cooling-device =</div><div class='add'>+				&lt;&amp;A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+				&lt;&amp;A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8dxp-tqma8xdps-mb-smarc-2.dts b/arch/arm64/boot/dts/freescale/imx8dxp-tqma8xdps-mb-smarc-2.dts<br/>new file mode 100644<br/>index 000000000000..331787df2fe4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8dxp-tqma8xdps-mb-smarc-2.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8dxp-tqma8xdps-mb-smarc-2.dts</a></div><div class='hunk'>@@ -0,0 +1,16 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2021-2025 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Alexander Stein</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8dxp-tqma8xdps.dtsi"</div><div class='add'>+#include "tqma8xxs-mb-smarc-2.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "TQ-Systems i.MX8DXP TQMa8XDPS on MB-SMARC-2";</div><div class='add'>+	compatible = "tq,imx8dxp-tqma8xdps-mb-smarc-2", "tq,imx8dxp-tqma8xdps", "fsl,imx8dxp";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8dxp-tqma8xdps.dtsi b/arch/arm64/boot/dts/freescale/imx8dxp-tqma8xdps.dtsi<br/>new file mode 100644<br/>index 000000000000..a97286fe7e0d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8dxp-tqma8xdps.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8dxp-tqma8xdps.dtsi</a></div><div class='hunk'>@@ -0,0 +1,24 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2021-2025 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Alexander Stein</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "imx8dxp.dtsi"</div><div class='add'>+#include "tqma8xxs.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "TQ-Systems i.MX8DXP TQMa8XDPS";</div><div class='add'>+	compatible = "tq,imx8dxp-tqma8xdps", "fsl,imx8dxp";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pmic0_thermal {</div><div class='add'>+	cooling-maps {</div><div class='add'>+		map0 {</div><div class='add'>+			cooling-device =</div><div class='add'>+				&lt;&amp;A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+				&lt;&amp;A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8dxp.dtsi b/arch/arm64/boot/dts/freescale/imx8dxp.dtsi<br/>new file mode 100644<br/>index 000000000000..a8f7352332c0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8dxp.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8dxp.dtsi</a></div><div class='hunk'>@@ -0,0 +1,24 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2016 Freescale Semiconductor, Inc.</div><div class='add'>+ * Copyright 2017-2019 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8qxp.dtsi"</div><div class='add'>+</div><div class='add'>+/delete-node/ &amp;A35_2;</div><div class='add'>+/delete-node/ &amp;A35_3;</div><div class='add'>+</div><div class='add'>+&amp;thermal_zones {</div><div class='add'>+	cpu0-thermal {</div><div class='add'>+		cooling-maps {</div><div class='add'>+			map0 {</div><div class='add'>+				cooling-device =</div><div class='add'>+				&lt;&amp;A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+				&lt;&amp;A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi<br/>new file mode 100644<br/>index 000000000000..ea1d5b9c6bae<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi</a></div><div class='hunk'>@@ -0,0 +1,503 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2020 Compass Electronics Group, LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/phy/phy-imx8-pcie.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+</div><div class='add'>+	dmic_codec: dmic-codec {</div><div class='add'>+		compatible = "dmic-codec";</div><div class='add'>+		num-channels = &lt;1&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led0 {</div><div class='add'>+			label = "gen_led0";</div><div class='add'>+			gpios = &lt;&amp;pca6416_1 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led1 {</div><div class='add'>+			label = "gen_led1";</div><div class='add'>+			gpios = &lt;&amp;pca6416_1 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led2 {</div><div class='add'>+			label = "gen_led2";</div><div class='add'>+			gpios = &lt;&amp;pca6416_1 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led3 {</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_led3&gt;;</div><div class='add'>+			label = "heartbeat";</div><div class='add'>+			gpios = &lt;&amp;gpio4 28 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_refclk: pcie0-refclk {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;100000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_refclk_gated:  pcie0-refclk-gated {</div><div class='add'>+		compatible = "gpio-gate-clock";</div><div class='add'>+		clocks = &lt;&amp;pcie0_refclk&gt;;</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;pca6416_1 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_1v5: regulator-1v5 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "1V5";</div><div class='add'>+		regulator-min-microvolt = &lt;1500000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1500000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_1v8: regulator-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_audio: regulator-audio {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "3v3_aud";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;pca6416_1 11 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usbotg1: regulator-usbotg1 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usb_otg1&gt;;</div><div class='add'>+		regulator-name = "usb_otg_vbus";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio4 29 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_camera: regulator-camera {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "mipi_pwr";</div><div class='add'>+		regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+		gpio = &lt;&amp;pca6416_1 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		startup-delay-us = &lt;100000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_pcie0: regulator-pcie {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "pci_pwr_en";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;pca6416_1 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		startup-delay-us = &lt;100000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VSD_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio2 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-dmic {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,name = "dmic";</div><div class='add'>+		simple-audio-card,format = "pdm";</div><div class='add'>+		simple-audio-card,bitclock-master = &lt;&amp;dailink_master&gt;;</div><div class='add'>+		simple-audio-card,frame-master = &lt;&amp;dailink_master&gt;;</div><div class='add'>+</div><div class='add'>+		dailink_master: simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;micfil&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		simple-audio-card,codec {</div><div class='add'>+			sound-dai = &lt;&amp;dmic_codec&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-wm8962 {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,name = "wm8962";</div><div class='add'>+		simple-audio-card,format = "i2s";</div><div class='add'>+		simple-audio-card,widgets = "Headphone", "Headphones",</div><div class='add'>+					    "Microphone", "Headset Mic",</div><div class='add'>+					    "Speaker", "Speaker";</div><div class='add'>+		simple-audio-card,routing = "Headphones", "HPOUTL",</div><div class='add'>+					    "Headphones", "HPOUTR",</div><div class='add'>+					    "Speaker", "SPKOUTL",</div><div class='add'>+					    "Speaker", "SPKOUTR",</div><div class='add'>+					    "Headset Mic", "MICBIAS",</div><div class='add'>+					    "IN3R", "Headset Mic";</div><div class='add'>+</div><div class='add'>+		simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;sai3&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		simple-audio-card,codec {</div><div class='add'>+			sound-dai = &lt;&amp;wm8962&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MM_CLK_SAI3_ROOT&gt;;</div><div class='add'>+			frame-master;</div><div class='add'>+			bitclock-master;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;csi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_espi2&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 13 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	eeprom@0 {</div><div class='add'>+		compatible = "microchip,at25160bn", "atmel,at25";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;5000000&gt;;</div><div class='add'>+		spi-cpha;</div><div class='add'>+		spi-cpol;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		size = &lt;2048&gt;;</div><div class='add'>+		address-width = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	camera@10 {</div><div class='add'>+		compatible = "ovti,ov5640";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_ov5640&gt;;</div><div class='add'>+		reg = &lt;0x10&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX8MM_CLK_CLKO1&gt;;</div><div class='add'>+		clock-names = "xclk";</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX8MM_CLK_CLKO1&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;&amp;clk IMX8MM_CLK_24M&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;24000000&gt;;</div><div class='add'>+		AVDD-supply = &lt;&amp;reg_camera&gt;;  /* 2.8v */</div><div class='add'>+		DVDD-supply = &lt;&amp;reg_1v5&gt;;</div><div class='add'>+		DOVDD-supply = &lt;&amp;reg_1v8&gt;;</div><div class='add'>+		powerdown-gpios = &lt;&amp;gpio1 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio1 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			/* MIPI CSI-2 bus endpoint */</div><div class='add'>+			ov5640_to_mipi_csi2: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;imx8mm_mipi_csi_in&gt;;</div><div class='add'>+				clock-lanes = &lt;0&gt;;</div><div class='add'>+				data-lanes = &lt;1 2&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	wm8962: audio-codec@1a {</div><div class='add'>+		compatible = "wlf,wm8962";</div><div class='add'>+		reg = &lt;0x1a&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX8MM_CLK_SAI3_ROOT&gt;;</div><div class='add'>+		DCVDD-supply = &lt;&amp;reg_audio&gt;;</div><div class='add'>+		DBVDD-supply = &lt;&amp;reg_audio&gt;;</div><div class='add'>+		AVDD-supply = &lt;&amp;reg_audio&gt;;</div><div class='add'>+		CPVDD-supply = &lt;&amp;reg_audio&gt;;</div><div class='add'>+		MICVDD-supply = &lt;&amp;reg_audio&gt;;</div><div class='add'>+		PLLVDD-supply = &lt;&amp;reg_audio&gt;;</div><div class='add'>+		SPKVDD1-supply = &lt;&amp;reg_audio&gt;;</div><div class='add'>+		SPKVDD2-supply = &lt;&amp;reg_audio&gt;;</div><div class='add'>+		gpio-cfg = &lt;</div><div class='add'>+			0x0000 /* 0:Default */</div><div class='add'>+			0x0000 /* 1:Default */</div><div class='add'>+			0x0000 /* 2:FN_DMICCLK */</div><div class='add'>+			0x0000 /* 3:Default */</div><div class='add'>+			0x0000 /* 4:FN_DMICCDAT */</div><div class='add'>+			0x0000 /* 5:Default */</div><div class='add'>+		&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pca6416_0: gpio@20 {</div><div class='add'>+		compatible = "nxp,pcal6416";</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pcal6414&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;27 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pca6416_1: gpio@21 {</div><div class='add'>+		compatible = "nxp,pcal6416";</div><div class='add'>+		reg = &lt;0x21&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;27 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;micfil {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pdm&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_PDM&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;49152000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_csi {</div><div class='add'>+	status = "okay";</div><div class='add'>+	ports {</div><div class='add'>+		port@0 {</div><div class='add'>+			imx8mm_mipi_csi_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;ov5640_to_mipi_csi2&gt;;</div><div class='add'>+				data-lanes = &lt;1 2&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	fsl,refclk-pad-mode = &lt;IMX8_PCIE_REFCLK_PAD_INPUT&gt;;</div><div class='add'>+	fsl,tx-deemph-gen1 = &lt;0x2d&gt;;</div><div class='add'>+	fsl,tx-deemph-gen2 = &lt;0xf&gt;;</div><div class='add'>+	fsl,clkreq-unsupported;</div><div class='add'>+	clocks = &lt;&amp;pcie0_refclk_gated&gt;;</div><div class='add'>+	clock-names = "ref";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie0&gt;;</div><div class='add'>+	reset-gpio = &lt;&amp;gpio4 21 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	clocks = &lt;&amp;clk IMX8MM_CLK_PCIE1_ROOT&gt;, &lt;&amp;pcie0_refclk_gated&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX8MM_CLK_PCIE1_AUX&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_PCIE1_AUX&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MM_CLK_PCIE1_CTRL&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;10000000&gt;, &lt;250000000&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL2_50M&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MM_SYS_PLL2_250M&gt;;</div><div class='add'>+	vpcie-supply = &lt;&amp;reg_pcie0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai3&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_SAI3&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;24576000&gt;;</div><div class='add'>+	fsl,sai-mclk-direction-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;snvs_pwrkey {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 { /* console */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_UART3&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL1_80M&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usbotg1&gt;;</div><div class='add'>+	disable-over-current;</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg2 {</div><div class='add'>+	disable-over-current;</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbphynop2 {</div><div class='add'>+	reset-gpios = &lt;&amp;pca6416_1 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_espi2: espi2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK		0x82</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI		0x82</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO		0x82</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13              0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4: i2c4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL		0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_led3: led3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ov5640: ov5640grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x19</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6		0x19</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1	0x59</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcal6414: pcal6414-gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27		0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pdm: pdmgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXC_PDM_CLK	0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0	0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usb_otg1: usbotg1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29     0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie0: pcie0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21       0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai3: sai3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0	0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140</div><div class='add'>+			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: uart3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX	0x40</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX	0x40</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B	0x40</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B	0x40</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B	0x41</div><div class='add'>+			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK	0x190</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK	0x194</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK	0x196</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-kit.dts b/arch/arm64/boot/dts/freescale/imx8mm-beacon-kit.dts<br/>new file mode 100644<br/>index 000000000000..734a75198f06<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-beacon-kit.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-beacon-kit.dts</a></div><div class='hunk'>@@ -0,0 +1,151 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2020 Compass Electronics Group, LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mm.dtsi"</div><div class='add'>+#include "imx8mm-beacon-som.dtsi"</div><div class='add'>+#include "imx8mm-beacon-baseboard.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Beacon EmbeddedWorks i.MX8M Mini Development Kit";</div><div class='add'>+	compatible = "beacon,imx8mm-beacon-kit", "fsl,imx8mm";</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		type = "a";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			hdmi_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;adv7535_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_hdmi: regulator-hdmi-dvdd {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_hdmi&gt;;</div><div class='add'>+		regulator-name = "hdmi_pwr_en";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio2 11 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		startup-delay-us = &lt;70000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-hdmi {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,name = "sound-hdmi";</div><div class='add'>+		simple-audio-card,format = "i2s";</div><div class='add'>+</div><div class='add'>+		simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;sai5&gt;;</div><div class='add'>+			system-clock-direction-out;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		simple-audio-card,codec {</div><div class='add'>+			sound-dai = &lt;&amp;adv_bridge&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	adv_bridge: hdmi@3d {</div><div class='add'>+		compatible = "adi,adv7535";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_hdmi_bridge&gt;;</div><div class='add'>+		reg = &lt;0x3d&gt;, &lt;0x3e&gt;, &lt;0x3c&gt;, &lt;0x3f&gt;;</div><div class='add'>+		reg-names = "main", "edid", "cec", "packet";</div><div class='add'>+		adi,dsi-lanes = &lt;4&gt;;</div><div class='add'>+		avdd-supply = &lt;&amp;reg_hdmi&gt;;</div><div class='add'>+		a2vdd-supply = &lt;&amp;reg_hdmi&gt;;</div><div class='add'>+		dvdd-supply = &lt;&amp;reg_hdmi&gt;;</div><div class='add'>+		pvdd-supply = &lt;&amp;reg_hdmi&gt;;</div><div class='add'>+		v1p2-supply = &lt;&amp;reg_hdmi&gt;;</div><div class='add'>+		v3p3-supply = &lt;&amp;reg_hdmi&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;9 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				adv7535_in: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;dsi_out&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				adv7535_out: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;hdmi_connector_in&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_dsi {</div><div class='add'>+	samsung,esc-clock-frequency = &lt;20000000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			dsi_out: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;adv7535_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai5 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai5&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_SAI5&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;24576000&gt;;</div><div class='add'>+	#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	fsl,sai-mclk-direction-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_hdmi_bridge: hdmibridgegrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_hdmi: reghdmigrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11              0x16</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai5: sai5grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0	0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK	0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC	0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi<br/>new file mode 100644<br/>index 000000000000..8287a7f66ed3<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi</a></div><div class='hunk'>@@ -0,0 +1,481 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2020 Compass Electronics Group, LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "imx8mm-overdrive.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		rtc0 = &amp;rtc;</div><div class='add'>+		rtc1 = &amp;snvs_rtc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usdhc1_pwrseq: usdhc1_pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-simple";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usdhc1_gpio&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio2 10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		clocks = &lt;&amp;osc_32k&gt;;</div><div class='add'>+		clock-names = "ext_clock";</div><div class='add'>+		post-power-on-delay-ms = &lt;80&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x40000000 0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ddrc {</div><div class='add'>+	operating-points-v2 = &lt;&amp;ddrc_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+	ddrc_opp_table: opp-table {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		opp-25000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;25000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-100000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;100000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-750000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;750000000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec1&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	fsl,magic-packet;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@0 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio4 22 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+			interrupts = &lt;10 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexspi {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexspi&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash@0 {</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		spi-max-frequency = &lt;80000000&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;1&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pmic@4b {</div><div class='add'>+		compatible = "rohm,bd71847";</div><div class='add'>+		reg = &lt;0x4b&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;3 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		rohm,reset-snvs-powered;</div><div class='add'>+</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clocks = &lt;&amp;osc_32k&gt;;</div><div class='add'>+		clock-output-names = "clk-32k-out";</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			buck1_reg: BUCK1 {</div><div class='add'>+				regulator-name = "buck1";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;1250&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck2_reg: BUCK2 {</div><div class='add'>+				regulator-name = "buck2";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;1250&gt;;</div><div class='add'>+				rohm,dvs-run-voltage = &lt;1000000&gt;;</div><div class='add'>+				rohm,dvs-idle-voltage = &lt;900000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck3_reg: BUCK3 {</div><div class='add'>+				// BUCK5 in datasheet</div><div class='add'>+				regulator-name = "buck3";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck4_reg: BUCK4 {</div><div class='add'>+				// BUCK6 in datasheet</div><div class='add'>+				regulator-name = "buck4";</div><div class='add'>+				regulator-min-microvolt = &lt;3000000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck5_reg: BUCK5 {</div><div class='add'>+				// BUCK7 in datasheet</div><div class='add'>+				regulator-name = "buck5";</div><div class='add'>+				regulator-min-microvolt = &lt;1605000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1995000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck6_reg: BUCK6 {</div><div class='add'>+				// BUCK8 in datasheet</div><div class='add'>+				regulator-name = "buck6";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo1_reg: LDO1 {</div><div class='add'>+				regulator-name = "ldo1";</div><div class='add'>+				regulator-min-microvolt = &lt;1600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo2_reg: LDO2 {</div><div class='add'>+				regulator-name = "ldo2";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo3_reg: LDO3 {</div><div class='add'>+				regulator-name = "ldo3";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo4_reg: LDO4 {</div><div class='add'>+				regulator-name = "ldo4";</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo6_reg: LDO6 {</div><div class='add'>+				regulator-name = "ldo6";</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	eeprom@50 {</div><div class='add'>+		compatible = "microchip,24c64", "atmel,24c64";</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		read-only;	/* Manufacturing EEPROM programmed at factory */</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rtc: rtc@51 {</div><div class='add'>+		compatible = "nxp,pcf85263";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_rtc&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;13 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		quartz-load-femtofarads = &lt;12500&gt;;</div><div class='add'>+		wakeup-source;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_UART1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL1_80M&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "brcm,bcm43438-bt";</div><div class='add'>+		shutdown-gpios = &lt;&amp;gpio2 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		host-wakeup-gpios = &lt;&amp;gpio2 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		device-wakeup-gpios = &lt;&amp;gpio2 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;osc_32k&gt;;</div><div class='add'>+		max-speed = &lt;4000000&gt;;</div><div class='add'>+		clock-names = "extclk";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1_200mhz&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	cap-power-off-card;</div><div class='add'>+	keep-power-in-suspend;</div><div class='add'>+	mmc-pwrseq = &lt;&amp;usdhc1_pwrseq&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	brcmf: wifi@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		compatible = "brcm,bcm4329-fmac";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_wlan&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio2&gt;;</div><div class='add'>+		interrupts = &lt;9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-names = "host-wake";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_USDHC3&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_fec1: fec1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC		0x3</div><div class='add'>+			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO	0x3</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10             0x146</div><div class='add'>+			MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22	0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexspi: flexspigrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK               0x1c2</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B            0x82</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0           0x82</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1           0x82</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2           0x82</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3           0x82</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: pmicirqgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x141</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_rtc: rtcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13	0x146</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140</div><div class='add'>+			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140</div><div class='add'>+			MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B	0x140</div><div class='add'>+			MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B	0x140</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6	0x19</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7	0x19</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8	0x19</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K	0x141</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_gpio: usdhc1gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x190</div><div class='add'>+			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x194</div><div class='add'>+			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x196</div><div class='add'>+			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x190</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x190</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x194</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x194</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x196</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x196</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0x166</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wlan: wlangrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9		0x111</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts<br/>new file mode 100644<br/>index 000000000000..472c584fb3bd<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts</a></div><div class='hunk'>@@ -0,0 +1,1022 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Marek Vasut &lt;marex@denx.de&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/net/qca-ar803x.h&gt;</div><div class='add'>+#include &lt;dt-bindings/phy/phy-imx8-pcie.h&gt;</div><div class='add'>+#include "imx8mm.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Data Modul i.MX8M Mini eDM SBC";</div><div class='add'>+	compatible = "dmo,imx8mm-data-modul-edm-sbc", "fsl,imx8mm";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		rtc0 = &amp;rtc;</div><div class='add'>+		rtc1 = &amp;snvs_rtc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart3;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		/* There are 1/2/4 GiB options, adjusted by bootloader. */</div><div class='add'>+		reg = &lt;0x0 0x40000000 0 0x40000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	backlight: backlight {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_panel_backlight&gt;;</div><div class='add'>+		brightness-levels = &lt;0 1 10 20 30 40 50 60 70 75 80 90 100&gt;;</div><div class='add'>+		default-brightness-level = &lt;7&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;gpio3 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pwms = &lt;&amp;pwm1 0 5000000 0&gt;;</div><div class='add'>+		/* Disabled by default, unless display board plugged in. */</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_xtal25: clk-xtal25 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;25000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_xtal32k: clk-xtal32k {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;32768&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	panel: panel {</div><div class='add'>+		backlight = &lt;&amp;backlight&gt;;</div><div class='add'>+		power-supply = &lt;&amp;reg_panel_vcc&gt;;</div><div class='add'>+		/* Disabled by default, unless display board plugged in. */</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_panel_vcc: regulator-panel-vcc {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_panel_vcc_reg&gt;;</div><div class='add'>+		regulator-name = "PANEL_VCC";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio3 6 0&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		/* Disabled by default, unless display board plugged in. */</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vcc: regulator-usdhc2-vcc {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usdhc2_vcc_reg&gt;;</div><div class='add'>+		regulator-name = "V_3V3_SD";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio2 19 0&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	watchdog {</div><div class='add'>+		/* TPS3813 */</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_watchdog_gpio&gt;;</div><div class='add'>+		compatible = "linux,wdt-gpio";</div><div class='add'>+		always-running;</div><div class='add'>+		gpios = &lt;&amp;gpio1 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		hw_algo = "level";</div><div class='add'>+		/* Reset triggers in 2..3 seconds */</div><div class='add'>+		hw_margin_ms = &lt;1500&gt;;</div><div class='add'>+		/* Disabled by default */</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ddrc {</div><div class='add'>+	operating-points-v2 = &lt;&amp;ddrc_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+	ddrc_opp_table: opp-table {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		opp-25000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;25000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-100000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;100000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-750000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;750000000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi1&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash@0 {	/* W25Q128FVSI */</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		m25p,fast-read;</div><div class='add'>+		spi-max-frequency = &lt;50000000&gt;;</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi2 {	/* Feature connector SPI */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi2&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 13 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	/* Disabled by default, unless feature board plugged in. */</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi3 {	/* Display connector SPI */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi3&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 25 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	/* Disabled by default, unless display board plugged in. */</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec1&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;fec1_phy_bcm&gt;;</div><div class='add'>+	phy-supply = &lt;&amp;buck4_reg&gt;;</div><div class='add'>+	fsl,magic-packet;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		/* Atheros AR8031 PHY */</div><div class='add'>+		fec1_phy_ath: ethernet-phy@0 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			/*</div><div class='add'>+			 * Dedicated ENET_WOL# signal is unused, the PHY</div><div class='add'>+			 * can wake the SoC up via INT signal as well.</div><div class='add'>+			 */</div><div class='add'>+			interrupts-extended = &lt;&amp;gpio1 15 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio1 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;10000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;10000&gt;;</div><div class='add'>+			qca,keep-pll-enabled;</div><div class='add'>+			vddio-supply = &lt;&amp;vddio&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			vddio: vddio-regulator {</div><div class='add'>+				regulator-name = "VDDIO";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vddh: vddh-regulator {</div><div class='add'>+				regulator-name = "VDDH";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* Broadcom BCM54213PE PHY */</div><div class='add'>+		fec1_phy_bcm: ethernet-phy@1 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			/*</div><div class='add'>+			 * Dedicated ENET_INT# and ENET_WOL# signals are</div><div class='add'>+			 * unused, the PHY does not provide cable detect</div><div class='add'>+			 * interrupt.</div><div class='add'>+			 */</div><div class='add'>+			reset-gpios = &lt;&amp;gpio1 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;10000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;10000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"", "ENET_RST#", "WDOG_B#", "PMIC_INT#",</div><div class='add'>+		"", "M2-B_PCIE_RST#", "M2-B_PCIE_WAKE#", "RTC_IRQ#",</div><div class='add'>+		"WDOG_KICK#", "M2-B_PCIE_CLKREQ#",</div><div class='add'>+		"USB1_OTG_ID_3V3", "ENET_WOL#",</div><div class='add'>+		"", "", "", "ENET_INT#",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio2 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"MEMCFG2", "MEMCFG1", "DSI_RESET_1V8#", "DSI_IRQ_1V8#",</div><div class='add'>+		"M2-B_FULL_CARD_PWROFF_1V8#", "EEPROM_WP_1V8#",</div><div class='add'>+		"PCIE_CLK_GEN_CLKPWRGD_PD_1V8#", "GRAPHICS_PRSNT_1V8#",</div><div class='add'>+		"MEMCFG0", "WDOG_EN",</div><div class='add'>+		"M2-B_W_DISABLE1_WWAN_1V8#", "M2-B_W_DISABLE2_GPS_1V8#",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "SD2_RESET#", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio3 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"BL_ENABLE_1V8", "PG_V_IN_VAR#", "", "",</div><div class='add'>+		"", "", "TFT_ENABLE_1V8", "GRAPHICS_GPIO0_1V8",</div><div class='add'>+		"CSI_PD_1V8", "CSI_RESET_1V8#", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "M2-B_WAKE_WWAN_1V8#",</div><div class='add'>+		"M2-B_RESET_1V8#", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"NC0", "NC1", "BOOTCFG0", "BOOTCFG1",</div><div class='add'>+		"BOOTCFG2", "BOOTCFG3", "BOOTCFG4", "BOOTCFG5",</div><div class='add'>+		"BOOTCFG6", "BOOTCFG7", "NC10", "NC11",</div><div class='add'>+		"BOOTCFG8", "BOOTCFG9", "BOOTCFG10", "BOOTCFG11",</div><div class='add'>+		"BOOTCFG12", "BOOTCFG13", "BOOTCFG14", "BOOTCFG15",</div><div class='add'>+		"NC20", "", "", "",</div><div class='add'>+		"", "CAN_INT#", "CAN_RST#", "GPIO4_IO27",</div><div class='add'>+		"DIS_USB_DN2", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio5 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"", "DIS_USB_DN1", "USBHUB_RESET#", "GPIO5_IO03",</div><div class='add'>+		"GPIO5_IO04", "", "", "",</div><div class='add'>+		"", "SPI1_CS#", "", "",</div><div class='add'>+		"", "SPI2_CS#", "I2C1_SCL_3V3", "I2C1_SDA_3V3",</div><div class='add'>+		"I2C2_SCL_3V3", "I2C2_SDA_3V3", "I2C3_SCL_3V3", "I2C3_SDA_3V3",</div><div class='add'>+		"I2C4_SCL_3V3", "I2C4_SDA_3V3", "", "",</div><div class='add'>+		"", "SPI3_CS#", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	/* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c1_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pmic: pmic@4b {</div><div class='add'>+		compatible = "rohm,bd71847";</div><div class='add'>+		reg = &lt;0x4b&gt;;</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk_xtal32k&gt;;</div><div class='add'>+		clock-output-names = "clk-32k-out";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;3 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		rohm,reset-snvs-powered;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * i.MX 8M Mini Data Sheet for Consumer Products</div><div class='add'>+		 * 3.1.3 Operating ranges</div><div class='add'>+		 * MIMX8MM4DVTLZAA</div><div class='add'>+		 */</div><div class='add'>+		regulators {</div><div class='add'>+			/* VDD_SOC */</div><div class='add'>+			buck1_reg: BUCK1 {</div><div class='add'>+				regulator-name = "buck1";</div><div class='add'>+				regulator-min-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;1250&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* VDD_ARM */</div><div class='add'>+			buck2_reg: BUCK2 {</div><div class='add'>+				regulator-name = "buck2";</div><div class='add'>+				regulator-min-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1050000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;1250&gt;;</div><div class='add'>+				rohm,dvs-run-voltage = &lt;1000000&gt;;</div><div class='add'>+				rohm,dvs-idle-voltage = &lt;950000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* VDD_DRAM, BUCK5 */</div><div class='add'>+			buck3_reg: BUCK3 {</div><div class='add'>+				regulator-name = "buck3";</div><div class='add'>+				/* 1.5 GHz DDR bus clock */</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* 3V3_VDD, BUCK6 */</div><div class='add'>+			buck4_reg: BUCK4 {</div><div class='add'>+				regulator-name = "buck4";</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* 1V8_VDD, BUCK7 */</div><div class='add'>+			buck5_reg: BUCK5 {</div><div class='add'>+				regulator-name = "buck5";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* 1V1_NVCC_DRAM, BUCK8 */</div><div class='add'>+			buck6_reg: BUCK6 {</div><div class='add'>+				regulator-name = "buck6";</div><div class='add'>+				regulator-min-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* 1V8_NVCC_SNVS */</div><div class='add'>+			ldo1_reg: LDO1 {</div><div class='add'>+				regulator-name = "ldo1";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* 0V8_VDD_SNVS */</div><div class='add'>+			ldo2_reg: LDO2 {</div><div class='add'>+				regulator-name = "ldo2";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* 1V8_VDDA */</div><div class='add'>+			ldo3_reg: LDO3 {</div><div class='add'>+				regulator-name = "ldo3";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* 0V9_VDD_PHY */</div><div class='add'>+			ldo4_reg: LDO4 {</div><div class='add'>+				regulator-name = "ldo4";</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* 1V2_VDD_PHY */</div><div class='add'>+			ldo6_reg: LDO6 {</div><div class='add'>+				regulator-name = "ldo6";</div><div class='add'>+				regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	/* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c2_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	usb-hub@2c {</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usb_hub&gt;;</div><div class='add'>+		compatible = "microchip,usb2514bi";</div><div class='add'>+		reg = &lt;0x2c&gt;;</div><div class='add'>+		individual-port-switching;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio5 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		self-powered;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom: eeprom@50 {</div><div class='add'>+		compatible = "atmel,24c32";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rtc: rtc@68 {</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_rtc&gt;;</div><div class='add'>+		compatible = "st,m41t62";</div><div class='add'>+		reg = &lt;0x68&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;gpio1 7 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcieclk: clk@6a {</div><div class='add'>+		compatible = "renesas,9fgv0241";</div><div class='add'>+		reg = &lt;0x6a&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk_xtal25&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {	/* Display connector I2C */</div><div class='add'>+	/* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */</div><div class='add'>+	clock-frequency = &lt;320000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c3_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {	/* Feature connector I2C */</div><div class='add'>+	/* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */</div><div class='add'>+	clock-frequency = &lt;320000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c4&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c4_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hog_feature&gt;, &lt;&amp;pinctrl_hog_misc&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_hog_panel&gt;, &lt;&amp;pinctrl_hog_sbc&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_panel_expansion&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi1: ecspi1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK		0x44</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI		0x44</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO		0x44</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9		0x40</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi2: ecspi2-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK		0x44</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI		0x44</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO		0x44</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13		0x40</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi3: ecspi3-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK		0x44</div><div class='add'>+			MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI		0x44</div><div class='add'>+			MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO		0x44</div><div class='add'>+			MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25		0x40</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec1: fec1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3</div><div class='add'>+			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f</div><div class='add'>+			/* ENET_RST# */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1		0x6</div><div class='add'>+			/* ENET_WOL# */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x40000090</div><div class='add'>+			/* ENET_INT# */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15		0x40000090</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_hog_feature: hog-feature-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* GPIO4_IO27 */</div><div class='add'>+			MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27		0x40000006</div><div class='add'>+			/* GPIO5_IO03 */</div><div class='add'>+			MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3			0x40000006</div><div class='add'>+			/* GPIO5_IO04 */</div><div class='add'>+			MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4			0x40000006</div><div class='add'>+</div><div class='add'>+			/* CAN_INT# */</div><div class='add'>+			MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25		0x40000090</div><div class='add'>+			/* CAN_RST# */</div><div class='add'>+			MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26		0x26</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_hog_panel: hog-panel-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* GRAPHICS_GPIO0_1V8 */</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7		0x26</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_hog_misc: hog-misc-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* PG_V_IN_VAR# */</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1		0x40000000</div><div class='add'>+			/* CSI_PD_1V8 */</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8		0x0</div><div class='add'>+			/* CSI_RESET_1V8# */</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9		0x0</div><div class='add'>+</div><div class='add'>+			/* DIS_USB_DN1 */</div><div class='add'>+			MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1			0x0</div><div class='add'>+			/* DIS_USB_DN2 */</div><div class='add'>+			MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28		0x0</div><div class='add'>+</div><div class='add'>+			/* EEPROM_WP_1V8# */</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA3_GPIO2_IO5		0x100</div><div class='add'>+			/* PCIE_CLK_GEN_CLKPWRGD_PD_1V8# */</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6		0x0</div><div class='add'>+			/* GRAPHICS_PRSNT_1V8# */</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7		0x40000000</div><div class='add'>+</div><div class='add'>+			/* CLK_CCM_CLKO1_3V3 */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1	0x10</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_hog_sbc: hog-sbc-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* MEMCFG[0..2] straps */</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8		0x40000140</div><div class='add'>+			MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1			0x40000140</div><div class='add'>+			MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0			0x40000140</div><div class='add'>+</div><div class='add'>+			/* BOOT_CFG[0..15] straps */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2		0x40000000</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3		0x40000000</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4		0x40000000</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5		0x40000000</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6		0x40000000</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7		0x40000000</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8		0x40000000</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9		0x40000000</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12		0x40000000</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13		0x40000000</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14		0x40000000</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15		0x40000000</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16		0x40000000</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17		0x40000000</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18		0x40000000</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19		0x40000000</div><div class='add'>+</div><div class='add'>+			/* Not connected pins */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20		0x0</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10		0x0</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11		0x0</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0		0x0</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1			0x0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL			0x40000084</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA			0x40000084</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1_gpio: i2c1-gpio-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14		0x84</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15		0x84</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL			0x40000084</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA			0x40000084</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2_gpio: i2c2-gpio-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16		0x84</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17		0x84</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL			0x40000084</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA			0x40000084</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3_gpio: i2c3-gpio-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18		0x84</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19		0x84</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4: i2c4-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL			0x40000084</div><div class='add'>+			MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA			0x40000084</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4_gpio: i2c4-gpio-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20		0x84</div><div class='add'>+			MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21		0x84</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_panel_backlight: panel-backlight-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* BL_ENABLE_1V8 */</div><div class='add'>+			MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0			0x104</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_panel_expansion: panel-expansion-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* DSI_RESET_1V8# */</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2		0x2</div><div class='add'>+			/* DSI_IRQ_1V8# */</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3		0x40000090</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_panel_vcc_reg: panel-vcc-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* TFT_ENABLE_1V8 */</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6		0x104</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_panel_pwm: panel-pwm-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* BL_PWM_3V3 */</div><div class='add'>+			MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT		0x12</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie0: pcie-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* M2-B_RESET_1V8# */</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20		0x102</div><div class='add'>+			/* M2-B_PCIE_RST# */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5		0x2</div><div class='add'>+			/* M2-B_FULL_CARD_PWROFF_1V8# */</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA2_GPIO2_IO4		0x102</div><div class='add'>+			/* M2-B_W_DISABLE1_WWAN_1V8# */</div><div class='add'>+			MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10		0x102</div><div class='add'>+			/* M2-B_W_DISABLE2_GPS_1V8# */</div><div class='add'>+			MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11		0x102</div><div class='add'>+			/* CLK_M2_32K768 */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K	0x14</div><div class='add'>+			/* M2-B_WAKE_WWAN_1V8# */</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19		0x40000140</div><div class='add'>+			/* M2-B_PCIE_WAKE# */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6		0x40000140</div><div class='add'>+			/* M2-B_PCIE_CLKREQ# */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x40000140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: pmic-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x40000090</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_rtc: rtc-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* RTC_IRQ# */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x40000090</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai5: sai5-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK		0x100</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0		0x0</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC		0x100</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK		0x100</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0		0x100</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX		0x90</div><div class='add'>+			MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B		0x90</div><div class='add'>+			MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX		0x50</div><div class='add'>+			MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B		0x50</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B		0x50</div><div class='add'>+			MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B		0x90</div><div class='add'>+			MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX		0x50</div><div class='add'>+			MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX		0x90</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: uart3-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX		0x40</div><div class='add'>+			MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX		0x40</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart4: uart4-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX		0x40</div><div class='add'>+			MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX		0x40</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usb_hub: usb-hub-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* USBHUB_RESET# */</div><div class='add'>+			MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2		0x4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usb_otg1: usb-otg1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x40000000</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR		0x4</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC		0x40000090</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_vcc_reg: usdhc2-vcc-reg-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19		0x4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x190</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_WP_USDHC2_WP			0x400000d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B		0x0d6</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x194</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_WP_USDHC2_WP			0x400000d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B		0x0d6</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x196</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_WP_USDHC2_WP			0x400000d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B		0x0d6</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: usdhc3-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x190</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x190</div><div class='add'>+			MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B		0x40</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x194</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x194</div><div class='add'>+			MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B		0x40</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x196</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x196</div><div class='add'>+			MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B		0x40</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_watchdog_gpio: watchdog-gpio-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* WDOG_B# */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO02_GPIO1_IO2		0x26</div><div class='add'>+			/* WDOG_EN -- ungate WDT RESET# signal propagation */</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9		0x6</div><div class='add'>+			/* WDOG_KICK# / WDI */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8		0x26</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	fsl,clkreq-unsupported;	/* CLKREQ_B is not connected to suitable input */</div><div class='add'>+	fsl,refclk-pad-mode = &lt;IMX8_PCIE_REFCLK_PAD_INPUT&gt;;</div><div class='add'>+	fsl,tx-deemph-gen1 = &lt;0x2d&gt;;</div><div class='add'>+	fsl,tx-deemph-gen2 = &lt;0xf&gt;;</div><div class='add'>+	clocks = &lt;&amp;pcieclk 0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie0&gt;;</div><div class='add'>+	reset-gpio = &lt;&amp;gpio1 5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	clocks = &lt;&amp;clk IMX8MM_CLK_PCIE1_ROOT&gt;, &lt;&amp;pcieclk 0&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX8MM_CLK_PCIE1_AUX&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_PCIE1_AUX&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MM_CLK_PCIE1_CTRL&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;10000000&gt;, &lt;250000000&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL2_50M&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MM_SYS_PLL2_250M&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_panel_pwm&gt;;</div><div class='add'>+	/* Disabled by default, unless display board plugged in. */</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai5 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai5&gt;;</div><div class='add'>+	fsl,sai-mclk-direction-output;</div><div class='add'>+	/* Input into codec PLL */</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_SAI5&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_AUDIO_PLL2_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;22579200&gt;;</div><div class='add'>+	/* Disabled by default, unless display board plugged in. */</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;snvs_rtc {</div><div class='add'>+	clocks = &lt;&amp;pmic&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart3 {	/* A53 Debug */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart4 {	/* M4 Debug */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart4&gt;;</div><div class='add'>+	/* UART4 is reserved for CM and RDC blocks CA access to UART4. */</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usb_otg1&gt;;</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg2 {</div><div class='add'>+	disable-over-current;</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {	/* MicroSD */</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_USDHC2_ROOT&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vcc&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc3 {	/* eMMC */</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_USDHC3_ROOT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	vmmc-supply = &lt;&amp;buck4_reg&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;buck5_reg&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts<br/>new file mode 100644<br/>index 000000000000..27848cee1670<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts</a></div><div class='hunk'>@@ -0,0 +1,56 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2020 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mm-evk.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "FSL i.MX8MM DDR4 EVK with CYW43455 WIFI/BT board";</div><div class='add'>+	compatible = "fsl,imx8mm-ddr4-evk", "fsl,imx8mm";</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_led_2&gt;;</div><div class='add'>+</div><div class='add'>+		status {</div><div class='add'>+			gpios = &lt;&amp;gpio3 4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpmi {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpmi_nand&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_gpmi_nand: gpminandgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE		0x00000096</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B		0x00000096</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B		0x00000096</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_RAWNAND_CLE		0x00000096</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA00_RAWNAND_DATA00		0x00000096</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA01_RAWNAND_DATA01		0x00000096</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA02_RAWNAND_DATA02		0x00000096</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA03_RAWNAND_DATA03		0x00000096</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_RAWNAND_DATA04		0x00000096</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_RAWNAND_DATA05		0x00000096</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_RAWNAND_DATA06		0x00000096</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_RAWNAND_DATA07		0x00000096</div><div class='add'>+			MX8MM_IOMUXC_NAND_RE_B_RAWNAND_RE_B		0x00000096</div><div class='add'>+			MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B	0x00000056</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B		0x00000096</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_RAWNAND_WP_B		0x00000096</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio_led_2: gpioled2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4	0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dts b/arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dts<br/>new file mode 100644<br/>index 000000000000..c8ff70212602<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dts</a></div><div class='hunk'>@@ -0,0 +1,23 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+//</div><div class='add'>+// Copyright (c) 2021 emtrion GmbH</div><div class='add'>+// Author: Frank Erdrich &lt;frank.erdrich@emtrion.com&gt;</div><div class='add'>+//</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mm-emcon.dtsi"</div><div class='add'>+#include "imx8mm-emcon-avari.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "emtrion SoM emCON-MX8M mini on Avari";</div><div class='add'>+	compatible = "emtrion,emcon-mx8mm-avari", "fsl,imx8mm";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lvds_backlight {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dtsi<br/>new file mode 100644<br/>index 000000000000..44c2cba41a1f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dtsi</a></div><div class='hunk'>@@ -0,0 +1,139 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+//</div><div class='add'>+// Copyright (C) 2021 emtrion GmbH</div><div class='add'>+// Author: Frank Erdrich &lt;frank.erdrich@emtrion.com&gt;</div><div class='add'>+//</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		boardid = &amp;boardID;</div><div class='add'>+		mmc0 = &amp;usdhc1;</div><div class='add'>+		mmc1 = &amp;usdhc2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_wall_5p0: regulator-wall5p0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "Main-Supply";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_base3p3: regulator-base3p3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		vin-supply = &lt;&amp;reg_wall_5p0&gt;;</div><div class='add'>+		regulator-name = "3V3-avari";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_base1p5: regulator-base1p5 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		vin-supply = &lt;&amp;reg_base3p3&gt;;</div><div class='add'>+		regulator-name = "1V5-avari";</div><div class='add'>+		regulator-min-microvolt = &lt;1500000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1500000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb_otg: regulator-otgvbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		vin-supply = &lt;&amp;reg_wall_5p0&gt;;</div><div class='add'>+		regulator-name = "OTG_VBUS";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio1 8 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_codec: clock-codec {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;12000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,name = "SGTL5000-Card";</div><div class='add'>+		simple-audio-card,format = "i2s";</div><div class='add'>+		simple-audio-card,bitclock-master = &lt;&amp;codec_dai&gt;;</div><div class='add'>+		simple-audio-card,frame-master = &lt;&amp;codec_dai&gt;;</div><div class='add'>+		simple-audio-card,widgets = "Headphone", "Headphone Jack";</div><div class='add'>+		simple-audio-card,routing = "Headphone Jack", "HP_OUT";</div><div class='add'>+</div><div class='add'>+		cpu_dai: simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;sai2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		codec_dai: simple-audio-card,codec {</div><div class='add'>+			sound-dai = &lt;&amp;sgtl5000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	sgtl5000: audio-codec@a {</div><div class='add'>+		compatible = "fsl,sgtl5000";</div><div class='add'>+		reg = &lt;0x0a&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk_codec&gt;;</div><div class='add'>+		VDDA-supply = &lt;&amp;reg_base3p3&gt;;</div><div class='add'>+		VDDIO-supply = &lt;&amp;reg_base3p3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	boardID: gpio@3a {</div><div class='add'>+		compatible = "nxp,pca8574";</div><div class='add'>+		reg = &lt;0x3a&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg2 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi<br/>new file mode 100644<br/>index 000000000000..af7dc8d1f5f1<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi</a></div><div class='hunk'>@@ -0,0 +1,625 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+//</div><div class='add'>+// Copyright 2018 NXP</div><div class='add'>+// Copyright (C) 2021 emtrion GmbH</div><div class='add'>+//</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mm.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	som_leds: leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_led&gt;;</div><div class='add'>+</div><div class='add'>+		led-green {</div><div class='add'>+			label = "som:green";</div><div class='add'>+			gpios = &lt;&amp;gpio3 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "on";</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-red {</div><div class='add'>+			label = "som:red";</div><div class='add'>+			gpios = &lt;&amp;gpio5 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lvds_backlight: lvds-backlight {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		enable-gpios = &lt;&amp;gpio3 23 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pwms = &lt;&amp;pwm1 0 50000 0&gt;;</div><div class='add'>+		brightness-levels = &lt;</div><div class='add'>+			0 4 8 16 32 64 80 96 112</div><div class='add'>+			128 144 160 176 250</div><div class='add'>+		&gt;;</div><div class='add'>+		default-brightness-level = &lt;9&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc1_vmmc: regulator-emmc {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "eMMC";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "sdcard_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi1 &amp;pinctrl_ecspi1_cs&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 9 GPIO_ACTIVE_LOW&gt;,</div><div class='add'>+				&lt;&amp;gpio5 13 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec1&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	fsl,magic-packet;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@0 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio1 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;10000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexspi {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexspi0&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_flexspi1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash0: flash@0 {</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		spi-max-frequency = &lt;40000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_csi_pwn: csi-pwn-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi1: ecspi1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK		0x82</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI		0x82</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO		0x82</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi1_cs: ecspi1cs-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9		0x40000</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13		0x40000</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec1: fec1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC				0x3</div><div class='add'>+			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO			0x3</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9			0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexspi0: flexspi0-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK		0x1c2</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B	0x82</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0	0x82</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1	0x82</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2	0x82</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3	0x82</div><div class='add'>+			MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS		0x82</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexspi1: flexspi1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_QSPI_B_SCLK		0x1c2</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B	0x82</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_QSPI_B_DATA0	0x82</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_QSPI_B_DATA1	0x82</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_QSPI_B_DATA2	0x82</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_QSPI_B_DATA3	0x82</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio_led: gpio-led-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10		0x19</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4		0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL			0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA			0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL			0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA			0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL			0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA			0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lvds: lvds-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25		0x06</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie0: pcie0-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20		0x41</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19		0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: pmicirq-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2		0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm1: pwm1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT		0x06</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai2: sai2-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK		0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI2_RXC_SAI2_RX_BCLK		0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0	0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC		0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK		0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0	0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC		0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_spdif1: spdif1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT		0xd6</div><div class='add'>+			MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN			0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX		0x140</div><div class='add'>+			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX		0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX		0x140</div><div class='add'>+			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX		0x140</div><div class='add'>+</div><div class='add'>+			/* rts and cts */</div><div class='add'>+			MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B	0x140</div><div class='add'>+			MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: uart3-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX		0x140</div><div class='add'>+			MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX		0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart4: uart4-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX		0x140</div><div class='add'>+			MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX		0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: usdhc1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK			0x190</div><div class='add'>+			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD			0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7		0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK			0x194</div><div class='add'>+			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD			0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7		0x1d4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK			0x196</div><div class='add'>+			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD			0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7		0x1d6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_gpio: usdhc1-gpio-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B	0x41</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x1c4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x190</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x194</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x196</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* no reset for sdhc2 interface */</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2-gpio-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x1c4</div><div class='add'>+			MX8MM_IOMUXC_SD2_WP_USDHC2_WP			0x1c4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdog-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bd71847: pmic@4b {</div><div class='add'>+		compatible = "rohm,bd71847";</div><div class='add'>+		reg = &lt;0x4b&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+		interrupts = &lt;2 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		rohm,reset-snvs-powered;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			buck1_reg: BUCK1 {</div><div class='add'>+				regulator-name = "buck1";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;1250&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck2_reg: BUCK2 {</div><div class='add'>+				regulator-name = "buck2";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;1250&gt;;</div><div class='add'>+				rohm,dvs-run-voltage = &lt;1000000&gt;;</div><div class='add'>+				rohm,dvs-idle-voltage = &lt;900000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck3_reg: BUCK3 {</div><div class='add'>+				// BUCK5 in datasheet</div><div class='add'>+				regulator-name = "buck3";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck4_reg: BUCK4 {</div><div class='add'>+				// BUCK6 in datasheet</div><div class='add'>+				regulator-name = "buck4";</div><div class='add'>+				regulator-min-microvolt = &lt;3000000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck5_reg: BUCK5 {</div><div class='add'>+				// BUCK7 in datasheet</div><div class='add'>+				regulator-name = "buck5";</div><div class='add'>+				regulator-min-microvolt = &lt;1605000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1995000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck6_reg: BUCK6 {</div><div class='add'>+				// BUCK8 in datasheet</div><div class='add'>+				regulator-name = "buck6";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo1_reg: LDO1 {</div><div class='add'>+				regulator-name = "ldo1";</div><div class='add'>+				regulator-min-microvolt = &lt;1600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1900000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo2_reg: LDO2 {</div><div class='add'>+				regulator-name = "ldo2";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo3_reg: LDO3 {</div><div class='add'>+				regulator-name = "ldo3";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo4_reg: LDO4 {</div><div class='add'>+				regulator-name = "ldo4";</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo6_reg: LDO6 {</div><div class='add'>+				regulator-name = "ldo6";</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rv1805: rtc@69 {</div><div class='add'>+		compatible = "abracon,ab1805";</div><div class='add'>+		reg = &lt;0x69&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mu {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai2 {</div><div class='add'>+	#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai2&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_SAI2&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;12000000&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spdif1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_spdif1&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_SPDIF1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;24576000&gt;;</div><div class='add'>+	clocks = &lt;&amp;clk IMX8MM_CLK_AUDIO_AHB&gt;, &lt;&amp;clk IMX8MM_CLK_24M&gt;,</div><div class='add'>+		&lt;&amp;clk IMX8MM_CLK_SPDIF1&gt;, &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;,</div><div class='add'>+		&lt;&amp;clk IMX8MM_CLK_DUMMY&gt;, &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;,</div><div class='add'>+		&lt;&amp;clk IMX8MM_CLK_AUDIO_AHB&gt;, &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;,</div><div class='add'>+		&lt;&amp;clk IMX8MM_CLK_DUMMY&gt;, &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;,</div><div class='add'>+		&lt;&amp;clk IMX8MM_AUDIO_PLL1_OUT&gt;, &lt;&amp;clk IMX8MM_AUDIO_PLL2_OUT&gt;;</div><div class='add'>+	clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3",</div><div class='add'>+		"rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k";</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 { /* console */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_UART1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL1_80M&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_UART2&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL1_80M&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_UART3&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL1_80M&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart4&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_UART4&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL1_80M&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	over-current-active-low;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg2 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	disable-over-current;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;, &lt;&amp;pinctrl_usdhc1_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1_100mhz&gt;, &lt;&amp;pinctrl_usdhc1_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1_200mhz&gt;, &lt;&amp;pinctrl_usdhc1_gpio&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc1_vmmc&gt;;</div><div class='add'>+	keep-power-in-suspend;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	wp-gpios = &lt;&amp;gpio2 20 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	no-1-8-v;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-emtop-baseboard.dts b/arch/arm64/boot/dts/freescale/imx8mm-emtop-baseboard.dts<br/>new file mode 100644<br/>index 000000000000..87fe3ebedb8d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-emtop-baseboard.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-emtop-baseboard.dts</a></div><div class='hunk'>@@ -0,0 +1,398 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Emtop Embedded Solutions</div><div class='add'>+ *</div><div class='add'>+ * Author: Himanshu Bhavani &lt;himanshu.bhavani@siliconsignals.io&gt;</div><div class='add'>+ * Author: Tarang Raval &lt;tarang.raval@siliconsignals.io&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mm-emtop-som.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Emtop Embedded Solutions i.MX8M Mini Baseboard V1";</div><div class='add'>+	compatible = "ees,imx8mm-emtop-baseboard", "ees,imx8mm-emtop-som",</div><div class='add'>+		"fsl,imx8mm";</div><div class='add'>+</div><div class='add'>+	connector {</div><div class='add'>+		compatible = "usb-c-connector";</div><div class='add'>+		label = "USB-C";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usb_otg&gt;;</div><div class='add'>+		id-gpios = &lt;&amp;gpio1 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			high_speed_ep: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;usb_hs_ep&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_led&gt;;</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+		        label = "buzzer";</div><div class='add'>+		        gpios = &lt;&amp;gpio4 29 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		        default-state = "off";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	osc_can: clock-osc-can {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;16000000&gt;;</div><div class='add'>+		clock-output-names = "osc-can";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_audio: regulator-audio {</div><div class='add'>+	        compatible = "regulator-fixed";</div><div class='add'>+	        regulator-name = "wm8904_supply";</div><div class='add'>+	        regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+	        regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	        regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_wifi_vmmc: regulator-wifi-vmmc {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vmmc";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio2 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		startup-delay-us = &lt;100&gt;;</div><div class='add'>+		off-on-delay-us = &lt;20000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-wm8904 {</div><div class='add'>+	        compatible = "simple-audio-card";</div><div class='add'>+	        simple-audio-card,bitclock-master = &lt;&amp;dailink_master&gt;;</div><div class='add'>+	        simple-audio-card,format = "i2s";</div><div class='add'>+	        simple-audio-card,frame-master = &lt;&amp;dailink_master&gt;;</div><div class='add'>+	        simple-audio-card,name = "wm8904-audio";</div><div class='add'>+	        simple-audio-card,mclk-fs = &lt;256&gt;;</div><div class='add'>+	        simple-audio-card,routing =</div><div class='add'>+			"Headphone Jack", "HPOUTL",</div><div class='add'>+			"Headphone Jack", "HPOUTR",</div><div class='add'>+			"IN2L", "Line In Jack",</div><div class='add'>+			"IN2R", "Line In Jack",</div><div class='add'>+			"Headphone Jack", "MICBIAS",</div><div class='add'>+			"IN1L", "Headphone Jack";</div><div class='add'>+</div><div class='add'>+	        simple-audio-card,widgets =</div><div class='add'>+	                "Microphone","Headphone Jack",</div><div class='add'>+	                "Headphone", "Headphone Jack",</div><div class='add'>+	                "Line", "Line In Jack";</div><div class='add'>+</div><div class='add'>+	        dailink_master: simple-audio-card,codec {</div><div class='add'>+	                sound-dai = &lt;&amp;wm8904&gt;;</div><div class='add'>+	        };</div><div class='add'>+</div><div class='add'>+	        simple-audio-card,cpu {</div><div class='add'>+	                sound-dai = &lt;&amp;sai3&gt;;</div><div class='add'>+	        };</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-spdif {</div><div class='add'>+	        compatible = "fsl,imx-audio-spdif";</div><div class='add'>+	        model = "imx-spdif";</div><div class='add'>+	        spdif-controller = &lt;&amp;spdif1&gt;;</div><div class='add'>+	        spdif-out;</div><div class='add'>+	        spdif-in;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* CAN BUS */</div><div class='add'>+&amp;ecspi2 {</div><div class='add'>+        pinctrl-names = "default";</div><div class='add'>+        pinctrl-0 = &lt;&amp;pinctrl_ecspi2&gt;;</div><div class='add'>+        status = "okay";</div><div class='add'>+</div><div class='add'>+        can: can@0 {</div><div class='add'>+                compatible = "microchip,mcp2515";</div><div class='add'>+                reg = &lt;0&gt;;</div><div class='add'>+                pinctrl-names = "default";</div><div class='add'>+                pinctrl-0 = &lt;&amp;pinctrl_canbus&gt;;</div><div class='add'>+                clocks = &lt;&amp;osc_can&gt;;</div><div class='add'>+                interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+                interrupts = &lt;14 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+                spi-max-frequency = &lt;10000000&gt;;</div><div class='add'>+        };</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec1&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	fsl,magic-packet;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@4 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;4&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio4 22 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;10000&gt;;</div><div class='add'>+			vddio-supply = &lt;&amp;vddio&gt;;</div><div class='add'>+</div><div class='add'>+			vddio: vddio-regulator {</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	wm8904: audio-codec@1a {</div><div class='add'>+		compatible = "wlf,wm8904";</div><div class='add'>+		reg = &lt;0x1a&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX8MM_CLK_SAI3_ROOT&gt;;</div><div class='add'>+		clock-names = "mclk";</div><div class='add'>+		DCVDD-supply = &lt;&amp;reg_audio&gt;;</div><div class='add'>+		DBVDD-supply = &lt;&amp;reg_audio&gt;;</div><div class='add'>+		AVDD-supply = &lt;&amp;reg_audio&gt;;</div><div class='add'>+		CPVDD-supply = &lt;&amp;reg_audio&gt;;</div><div class='add'>+		MICVDD-supply = &lt;&amp;reg_audio&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rtc@32 {</div><div class='add'>+		compatible = "epson,rx8025";</div><div class='add'>+		reg = &lt;0x32&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* AUDIO */</div><div class='add'>+&amp;sai3 {</div><div class='add'>+        pinctrl-names = "default";</div><div class='add'>+        pinctrl-0 = &lt;&amp;pinctrl_sai3&gt;;</div><div class='add'>+        assigned-clocks = &lt;&amp;clk IMX8MM_CLK_SAI3&gt;;</div><div class='add'>+        assigned-clock-parents = &lt;&amp;clk IMX8MM_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+        assigned-clock-rates = &lt;24576000&gt;;</div><div class='add'>+        status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spdif1 {</div><div class='add'>+        pinctrl-names = "default";</div><div class='add'>+        pinctrl-0 = &lt;&amp;pinctrl_spdif1&gt;;</div><div class='add'>+        assigned-clocks = &lt;&amp;clk IMX8MM_CLK_SPDIF1&gt;;</div><div class='add'>+        assigned-clock-parents = &lt;&amp;clk IMX8MM_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+        assigned-clock-rates = &lt;24576000&gt;;</div><div class='add'>+        clocks = &lt;&amp;clk IMX8MM_CLK_AUDIO_AHB&gt;, &lt;&amp;clk IMX8MM_CLK_24M&gt;,</div><div class='add'>+                &lt;&amp;clk IMX8MM_CLK_SPDIF1&gt;, &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;,</div><div class='add'>+                &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;, &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;,</div><div class='add'>+                &lt;&amp;clk IMX8MM_CLK_AUDIO_AHB&gt;, &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;,</div><div class='add'>+                &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;, &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;,</div><div class='add'>+                &lt;&amp;clk IMX8MM_AUDIO_PLL1_OUT&gt;, &lt;&amp;clk IMX8MM_AUDIO_PLL2_OUT&gt;;</div><div class='add'>+        clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3",</div><div class='add'>+                "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k";</div><div class='add'>+        status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USBOTG */</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	port {</div><div class='add'>+		usb_hs_ep: endpoint {</div><div class='add'>+			remote-endpoint = &lt;&amp;high_speed_ep&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg2 {</div><div class='add'>+        dr_mode = "host";</div><div class='add'>+        status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Wifi */</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;, &lt;&amp;pinctrl_usdhc1_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1_100mhz&gt;, &lt;&amp;pinctrl_usdhc1_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1_200mhz&gt;, &lt;&amp;pinctrl_usdhc1_gpio&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_wifi_vmmc&gt;;</div><div class='add'>+	cap-power-off-card;</div><div class='add'>+	keep-power-in-suspend;</div><div class='add'>+	non-removable;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	wifi: wifi@1 {</div><div class='add'>+		compatible = "brcm,bcm4329-fmac";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio2&gt;;</div><div class='add'>+		interrupts = &lt;9 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupt-names = "host-wake";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SD-card */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+        pinctrl-names = "default";</div><div class='add'>+        pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;;</div><div class='add'>+        pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;;</div><div class='add'>+        pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;;</div><div class='add'>+        cd-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+        bus-width = &lt;4&gt;;</div><div class='add'>+        status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+</div><div class='add'>+	pinctrl_canbus: canbusgrp {</div><div class='add'>+	        fsl,pins = &lt;</div><div class='add'>+		        MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14              0x14</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi2: ecspi2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_SS0_ECSPI2_SS0  		0x82</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI		0x82</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO		0x82</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK		0x82</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usb_otg: usbotggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x140   /* otg_id */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12		0x19    /* otg_vbus */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec1: fec1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC                 0x3</div><div class='add'>+			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO               0x3</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3           0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2           0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1           0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0           0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3           0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2           0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1           0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0           0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC           0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC           0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f</div><div class='add'>+			MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22                0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+	        fsl,pins = &lt;</div><div class='add'>+	                MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL                  0x400001c3</div><div class='add'>+	                MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA                  0x400001c3</div><div class='add'>+	        &gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai3: sai3grp {</div><div class='add'>+	        fsl,pins = &lt;</div><div class='add'>+	                MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC             0xd6</div><div class='add'>+	                MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK              0xd6</div><div class='add'>+	                MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK                0xd6</div><div class='add'>+	                MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0             0xd6</div><div class='add'>+	                MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0             0xd6</div><div class='add'>+	        &gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_spdif1: spdif1grp {</div><div class='add'>+	        fsl,pins = &lt;</div><div class='add'>+	                MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT                0xd6</div><div class='add'>+	        &gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK                 0x190</div><div class='add'>+			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD                 0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0             0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1             0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2             0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3             0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK         	0x194</div><div class='add'>+			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD         	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0     	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1     	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2     	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3     	0x1d4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK         	0x196</div><div class='add'>+			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD         	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0     	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1     	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2     	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3     	0x1d6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_gpio: usdhc1-gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10             0x41    /* wl_reg_on */</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9                0x41    /* wl_host_wake */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K      0x141   /* LP0: 32KHz */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+	        fsl,pins = &lt;</div><div class='add'>+	                MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK         	0x190</div><div class='add'>+	                MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD         	0x1d0</div><div class='add'>+	                MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0     	0x1d0</div><div class='add'>+	                MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1     	0x1d0</div><div class='add'>+	                MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2     	0x1d0</div><div class='add'>+	                MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3     	0x1d0</div><div class='add'>+	        &gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+	        fsl,pins = &lt;</div><div class='add'>+	                MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK         	0x194</div><div class='add'>+	                MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD         	0x1d4</div><div class='add'>+	                MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0     	0x1d4</div><div class='add'>+	                MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1     	0x1d4</div><div class='add'>+	                MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2     	0x1d4</div><div class='add'>+	                MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3     	0x1d4</div><div class='add'>+	        &gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+	        fsl,pins = &lt;</div><div class='add'>+	                MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK         	0x196</div><div class='add'>+	                MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD         	0x1d6</div><div class='add'>+	                MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0     	0x1d6</div><div class='add'>+	                MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1     	0x1d6</div><div class='add'>+	                MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2     	0x1d6</div><div class='add'>+	                MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3     	0x1d6</div><div class='add'>+	        &gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-emtop-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-emtop-som.dtsi<br/>new file mode 100644<br/>index 000000000000..67d22d3768aa<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-emtop-som.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-emtop-som.dtsi</a></div><div class='hunk'>@@ -0,0 +1,261 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Emtop Embedded Solutions</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/usb/pd.h&gt;</div><div class='add'>+</div><div class='add'>+#include "imx8mm.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Emtop Embedded Solutions i.MX8M Mini SOM-IMX8MMLPD4 SoM";</div><div class='add'>+	compatible = "ees,imx8mm-emtop-som", "fsl,imx8mm";</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_led&gt;;</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			function = LED_FUNCTION_POWER;</div><div class='add'>+			gpios = &lt;&amp;gpio3 16 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pmic@25 {</div><div class='add'>+		compatible = "nxp,pca9450c";</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;3 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			buck1: BUCK1 {</div><div class='add'>+				regulator-name = "BUCK1";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck2: BUCK2 {</div><div class='add'>+				regulator-name = "BUCK2";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck3: BUCK3 {</div><div class='add'>+				regulator-name = "BUCK3";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck4: BUCK4 {</div><div class='add'>+				regulator-name = "BUCK4";</div><div class='add'>+				regulator-min-microvolt = &lt;3000000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3600000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck5: BUCK5 {</div><div class='add'>+				regulator-name = "BUCK5";</div><div class='add'>+				regulator-min-microvolt = &lt;1650000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1950000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck6: BUCK6 {</div><div class='add'>+				regulator-name = "BUCK6";</div><div class='add'>+				regulator-min-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo1: LDO1 {</div><div class='add'>+				regulator-name = "LDO1";</div><div class='add'>+				regulator-min-microvolt = &lt;1650000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1950000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo2: LDO2 {</div><div class='add'>+				regulator-name = "LDO2";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;945000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo3: LDO3 {</div><div class='add'>+				regulator-name = "LDO3";</div><div class='add'>+				regulator-min-microvolt = &lt;1710000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1890000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo4: LDO4 {</div><div class='add'>+				regulator-name = "LDO4";</div><div class='add'>+				regulator-min-microvolt = &lt;810000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;945000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo5: LDO5 {</div><div class='add'>+				regulator-name = "LDO5";</div><div class='add'>+				regulator-min-microvolt = &lt;1650000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3600000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_gpio_led: emtop-gpio-led-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16			0x19</div><div class='add'>+			MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29			0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: emtop-i2c1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL				0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA				0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: emtop-pmic-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3			0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: emtop-uart2-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX			0x140</div><div class='add'>+			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX			0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: emtop-usdhc3-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK			0x190</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD			0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0			0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1			0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2			0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3			0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4			0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5			0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6			0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7			0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE			0x190</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: emtop-usdhc3-100mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK			0x194</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD			0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0			0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1			0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2			0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3			0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4			0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5			0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6			0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7			0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE			0x194</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: emtop-usdhc3-200mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK			0x196</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD			0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0			0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1			0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2			0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3			0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4			0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5			0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6			0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7			0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE			0x196</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: emtop-wdog-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B			0xc6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts<br/>index 951e14a3de0e..b68954bcc383 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-evk.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-evk.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-evk.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-evk.dts</a></div><div class='hunk'>@@ -1,85 +1,20 @@</div><div class='ctx'> // SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='ctx'> /*</div><div class='del'>- * Copyright 2019 NXP</div><div class='add'>+ * Copyright 2019-2020 NXP</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> /dts-v1/;</div><div class='ctx'> </div><div class='ctx'> #include &lt;dt-bindings/usb/pd.h&gt;</div><div class='del'>-#include "imx8mm.dtsi"</div><div class='add'>+#include "imx8mm-evk.dtsi"</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	model = "FSL i.MX8MM EVK board";</div><div class='ctx'> 	compatible = "fsl,imx8mm-evk", "fsl,imx8mm";</div><div class='ctx'> </div><div class='del'>-	chosen {</div><div class='del'>-		stdout-path = &amp;uart2;</div><div class='add'>+	aliases {</div><div class='add'>+		spi0 = &amp;flexspi;</div><div class='ctx'> 	};</div><div class='del'>-</div><div class='del'>-	memory@40000000 {</div><div class='del'>-		device_type = "memory";</div><div class='del'>-		reg = &lt;0x0 0x40000000 0 0x80000000&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	leds {</div><div class='del'>-		compatible = "gpio-leds";</div><div class='del'>-		pinctrl-names = "default";</div><div class='del'>-		pinctrl-0 = &lt;&amp;pinctrl_gpio_led&gt;;</div><div class='del'>-</div><div class='del'>-		status {</div><div class='del'>-			label = "status";</div><div class='del'>-			gpios = &lt;&amp;gpio3 16 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			default-state = "on";</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	reg_usdhc2_vmmc: regulator-usdhc2 {</div><div class='del'>-		compatible = "regulator-fixed";</div><div class='del'>-		pinctrl-names = "default";</div><div class='del'>-		pinctrl-0 = &lt;&amp;pinctrl_reg_usdhc2_vmmc&gt;;</div><div class='del'>-		regulator-name = "VSD_3V3";</div><div class='del'>-		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='del'>-		gpio = &lt;&amp;gpio2 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-		enable-active-high;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	wm8524: audio-codec {</div><div class='del'>-		#sound-dai-cells = &lt;0&gt;;</div><div class='del'>-		compatible = "wlf,wm8524";</div><div class='del'>-		pinctrl-names = "default";</div><div class='del'>-		pinctrl-0 = &lt;&amp;pinctrl_gpio_wlf&gt;;</div><div class='del'>-		wlf,mute-gpios = &lt;&amp;gpio5 21 GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	sound-wm8524 {</div><div class='del'>-		compatible = "simple-audio-card";</div><div class='del'>-		simple-audio-card,name = "wm8524-audio";</div><div class='del'>-		simple-audio-card,format = "i2s";</div><div class='del'>-		simple-audio-card,frame-master = &lt;&amp;cpudai&gt;;</div><div class='del'>-		simple-audio-card,bitclock-master = &lt;&amp;cpudai&gt;;</div><div class='del'>-		simple-audio-card,widgets =</div><div class='del'>-			"Line", "Left Line Out Jack",</div><div class='del'>-			"Line", "Right Line Out Jack";</div><div class='del'>-		simple-audio-card,routing =</div><div class='del'>-			"Left Line Out Jack", "LINEVOUTL",</div><div class='del'>-			"Right Line Out Jack", "LINEVOUTR";</div><div class='del'>-</div><div class='del'>-		cpudai: simple-audio-card,cpu {</div><div class='del'>-			sound-dai = &lt;&amp;sai3&gt;;</div><div class='del'>-			dai-tdm-slot-num = &lt;2&gt;;</div><div class='del'>-			dai-tdm-slot-width = &lt;32&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		simple-audio-card,codec {</div><div class='del'>-			sound-dai = &lt;&amp;wm8524&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk IMX8MM_CLK_SAI3_ROOT&gt;;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;A53_0 {</div><div class='del'>-	cpu-supply = &lt;&amp;buck2_reg&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;ddrc {</div><div class='hunk'>@@ -88,252 +23,36 @@</div><div class='ctx'> 	ddrc_opp_table: opp-table {</div><div class='ctx'> 		compatible = "operating-points-v2";</div><div class='ctx'> </div><div class='del'>-		opp-25M {</div><div class='add'>+		opp-25000000 {</div><div class='ctx'> 			opp-hz = /bits/ 64 &lt;25000000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		opp-100M {</div><div class='add'>+		opp-100000000 {</div><div class='ctx'> 			opp-hz = /bits/ 64 &lt;100000000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		opp-750M {</div><div class='add'>+		opp-750000000 {</div><div class='ctx'> 			opp-hz = /bits/ 64 &lt;750000000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;fec1 {</div><div class='add'>+&amp;flexspi {</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='del'>-	pinctrl-0 = &lt;&amp;pinctrl_fec1&gt;;</div><div class='del'>-	phy-mode = "rgmii-id";</div><div class='del'>-	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='del'>-	phy-reset-gpios = &lt;&amp;gpio4 22 GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-	phy-reset-duration = &lt;10&gt;;</div><div class='del'>-	fsl,magic-packet;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexspi&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='del'>-	mdio {</div><div class='add'>+	flash@0 {</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='del'>-		#size-cells = &lt;0&gt;;</div><div class='del'>-</div><div class='del'>-		ethphy0: ethernet-phy@0 {</div><div class='del'>-			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='del'>-			reg = &lt;0&gt;;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;i2c1 {</div><div class='del'>-	clock-frequency = &lt;400000&gt;;</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='del'>-	status = "okay";</div><div class='del'>-</div><div class='del'>-	pmic@4b {</div><div class='del'>-		compatible = "rohm,bd71847";</div><div class='del'>-		reg = &lt;0x4b&gt;;</div><div class='del'>-		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='del'>-		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='del'>-		interrupts = &lt;3 GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-		rohm,reset-snvs-powered;</div><div class='del'>-</div><div class='del'>-		regulators {</div><div class='del'>-			buck1_reg: BUCK1 {</div><div class='del'>-				regulator-name = "BUCK1";</div><div class='del'>-				regulator-min-microvolt = &lt;700000&gt;;</div><div class='del'>-				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='del'>-				regulator-boot-on;</div><div class='del'>-				regulator-always-on;</div><div class='del'>-				regulator-ramp-delay = &lt;1250&gt;;</div><div class='del'>-			};</div><div class='del'>-</div><div class='del'>-			buck2_reg: BUCK2 {</div><div class='del'>-				regulator-name = "BUCK2";</div><div class='del'>-				regulator-min-microvolt = &lt;700000&gt;;</div><div class='del'>-				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='del'>-				regulator-boot-on;</div><div class='del'>-				regulator-always-on;</div><div class='del'>-				regulator-ramp-delay = &lt;1250&gt;;</div><div class='del'>-				rohm,dvs-run-voltage = &lt;1000000&gt;;</div><div class='del'>-				rohm,dvs-idle-voltage = &lt;900000&gt;;</div><div class='del'>-			};</div><div class='del'>-</div><div class='del'>-			buck3_reg: BUCK3 {</div><div class='del'>-				// BUCK5 in datasheet</div><div class='del'>-				regulator-name = "BUCK3";</div><div class='del'>-				regulator-min-microvolt = &lt;700000&gt;;</div><div class='del'>-				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='del'>-				regulator-boot-on;</div><div class='del'>-				regulator-always-on;</div><div class='del'>-			};</div><div class='del'>-</div><div class='del'>-			buck4_reg: BUCK4 {</div><div class='del'>-				// BUCK6 in datasheet</div><div class='del'>-				regulator-name = "BUCK4";</div><div class='del'>-				regulator-min-microvolt = &lt;3000000&gt;;</div><div class='del'>-				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='del'>-				regulator-boot-on;</div><div class='del'>-				regulator-always-on;</div><div class='del'>-			};</div><div class='del'>-</div><div class='del'>-			buck5_reg: BUCK5 {</div><div class='del'>-				// BUCK7 in datasheet</div><div class='del'>-				regulator-name = "BUCK5";</div><div class='del'>-				regulator-min-microvolt = &lt;1605000&gt;;</div><div class='del'>-				regulator-max-microvolt = &lt;1995000&gt;;</div><div class='del'>-				regulator-boot-on;</div><div class='del'>-				regulator-always-on;</div><div class='del'>-			};</div><div class='del'>-</div><div class='del'>-			buck6_reg: BUCK6 {</div><div class='del'>-				// BUCK8 in datasheet</div><div class='del'>-				regulator-name = "BUCK6";</div><div class='del'>-				regulator-min-microvolt = &lt;800000&gt;;</div><div class='del'>-				regulator-max-microvolt = &lt;1400000&gt;;</div><div class='del'>-				regulator-boot-on;</div><div class='del'>-				regulator-always-on;</div><div class='del'>-			};</div><div class='del'>-</div><div class='del'>-			ldo1_reg: LDO1 {</div><div class='del'>-				regulator-name = "LDO1";</div><div class='del'>-				regulator-min-microvolt = &lt;3000000&gt;;</div><div class='del'>-				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='del'>-				regulator-boot-on;</div><div class='del'>-				regulator-always-on;</div><div class='del'>-			};</div><div class='del'>-</div><div class='del'>-			ldo2_reg: LDO2 {</div><div class='del'>-				regulator-name = "LDO2";</div><div class='del'>-				regulator-min-microvolt = &lt;900000&gt;;</div><div class='del'>-				regulator-max-microvolt = &lt;900000&gt;;</div><div class='del'>-				regulator-boot-on;</div><div class='del'>-				regulator-always-on;</div><div class='del'>-			};</div><div class='del'>-</div><div class='del'>-			ldo3_reg: LDO3 {</div><div class='del'>-				regulator-name = "LDO3";</div><div class='del'>-				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='del'>-				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='del'>-				regulator-boot-on;</div><div class='del'>-				regulator-always-on;</div><div class='del'>-			};</div><div class='del'>-</div><div class='del'>-			ldo4_reg: LDO4 {</div><div class='del'>-				regulator-name = "LDO4";</div><div class='del'>-				regulator-min-microvolt = &lt;900000&gt;;</div><div class='del'>-				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='del'>-				regulator-boot-on;</div><div class='del'>-				regulator-always-on;</div><div class='del'>-			};</div><div class='del'>-</div><div class='del'>-			ldo6_reg: LDO6 {</div><div class='del'>-				regulator-name = "LDO6";</div><div class='del'>-				regulator-min-microvolt = &lt;900000&gt;;</div><div class='del'>-				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='del'>-				regulator-boot-on;</div><div class='del'>-				regulator-always-on;</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		spi-max-frequency = &lt;80000000&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;1&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;i2c2 {</div><div class='del'>-	clock-frequency = &lt;400000&gt;;</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='del'>-	status = "okay";</div><div class='del'>-</div><div class='del'>-	ptn5110: tcpc@50 {</div><div class='del'>-		compatible = "nxp,ptn5110";</div><div class='del'>-		pinctrl-names = "default";</div><div class='del'>-		pinctrl-0 = &lt;&amp;pinctrl_typec1&gt;;</div><div class='del'>-		reg = &lt;0x50&gt;;</div><div class='del'>-		interrupt-parent = &lt;&amp;gpio2&gt;;</div><div class='del'>-		interrupts = &lt;11 8&gt;;</div><div class='del'>-		status = "okay";</div><div class='del'>-</div><div class='del'>-		port {</div><div class='del'>-			typec1_dr_sw: endpoint {</div><div class='del'>-				remote-endpoint = &lt;&amp;usb1_drd_sw&gt;;</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		typec1_con: connector {</div><div class='del'>-			compatible = "usb-c-connector";</div><div class='del'>-			label = "USB-C";</div><div class='del'>-			power-role = "dual";</div><div class='del'>-			data-role = "dual";</div><div class='del'>-			try-power-role = "sink";</div><div class='del'>-			source-pdos = &lt;PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)&gt;;</div><div class='del'>-			sink-pdos = &lt;PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)</div><div class='del'>-				     PDO_VAR(5000, 20000, 3000)&gt;;</div><div class='del'>-			op-sink-microwatt = &lt;15000000&gt;;</div><div class='del'>-			self-powered;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;i2c3 {</div><div class='del'>-	clock-frequency = &lt;400000&gt;;</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='del'>-	status = "okay";</div><div class='del'>-</div><div class='del'>-	pca6416: gpio@20 {</div><div class='del'>-		compatible = "ti,tca6416";</div><div class='del'>-		reg = &lt;0x20&gt;;</div><div class='del'>-		gpio-controller;</div><div class='del'>-		#gpio-cells = &lt;2&gt;;</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;sai3 {</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-	pinctrl-0 = &lt;&amp;pinctrl_sai3&gt;;</div><div class='del'>-	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_SAI3&gt;;</div><div class='del'>-	assigned-clock-parents = &lt;&amp;clk IMX8MM_AUDIO_PLL1_OUT&gt;;</div><div class='del'>-	assigned-clock-rates = &lt;24576000&gt;;</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;snvs_pwrkey {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;uart2 { /* console */</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;usbotg1 {</div><div class='del'>-	dr_mode = "otg";</div><div class='del'>-	hnp-disable;</div><div class='del'>-	srp-disable;</div><div class='del'>-	adp-disable;</div><div class='del'>-	usb-role-switch;</div><div class='del'>-	status = "okay";</div><div class='del'>-</div><div class='del'>-	port {</div><div class='del'>-		usb1_drd_sw: endpoint {</div><div class='del'>-			remote-endpoint = &lt;&amp;typec1_dr_sw&gt;;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;usdhc2 {</div><div class='del'>-	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_USDHC2&gt;;</div><div class='del'>-	assigned-clock-rates = &lt;200000000&gt;;</div><div class='del'>-	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='del'>-	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='del'>-	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='del'>-	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='del'>-	cd-gpios = &lt;&amp;gpio1 15 GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-	bus-width = &lt;4&gt;;</div><div class='del'>-	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> &amp;usdhc3 {</div><div class='ctx'> 	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_USDHC3_ROOT&gt;;</div><div class='ctx'> 	assigned-clock-rates = &lt;400000000&gt;;</div><div class='hunk'>@@ -346,196 +65,64 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;wdog1 {</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='del'>-	fsl,ext-reset-output;</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> &amp;iomuxc {</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-</div><div class='del'>-	pinctrl_fec1: fec1grp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3</div><div class='del'>-			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3</div><div class='del'>-			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f</div><div class='del'>-			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f</div><div class='del'>-			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f</div><div class='del'>-			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f</div><div class='del'>-			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91</div><div class='del'>-			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91</div><div class='del'>-			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91</div><div class='del'>-			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91</div><div class='del'>-			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f</div><div class='del'>-			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91</div><div class='del'>-			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91</div><div class='del'>-			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f</div><div class='del'>-			MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22		0x19</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	pinctrl_gpio_led: gpioledgrp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16	0x19</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	pinctrl_gpio_wlf: gpiowlfgrp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21	0xd6</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	pinctrl_i2c1: i2c1grp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL			0x400001c3</div><div class='del'>-			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA			0x400001c3</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	pinctrl_i2c2: i2c2grp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL			0x400001c3</div><div class='del'>-			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA			0x400001c3</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	pinctrl_i2c3: i2c3grp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL			0x400001c3</div><div class='del'>-			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA			0x400001c3</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	pinctrl_pmic: pmicirq {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x41</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	pinctrl_sai3: sai3grp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6</div><div class='del'>-			MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6</div><div class='del'>-			MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6</div><div class='del'>-			MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	pinctrl_typec1: typec1grp {</div><div class='add'>+	pinctrl_flexspi: flexspigrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='del'>-			MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11	0x159</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	pinctrl_uart2: uart2grp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140</div><div class='del'>-			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	pinctrl_usdhc2_gpio: usdhc2grpgpio {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x1c4</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	pinctrl_usdhc2: usdhc2grp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190</div><div class='del'>-			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0</div><div class='del'>-			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0</div><div class='del'>-			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0</div><div class='del'>-			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0</div><div class='del'>-			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0</div><div class='del'>-			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194</div><div class='del'>-			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4</div><div class='del'>-			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4</div><div class='del'>-			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4</div><div class='del'>-			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4</div><div class='del'>-			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4</div><div class='del'>-			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196</div><div class='del'>-			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6</div><div class='del'>-			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6</div><div class='del'>-			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6</div><div class='del'>-			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6</div><div class='del'>-			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6</div><div class='del'>-			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK               0x1c2</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B            0x82</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0           0x82</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1           0x82</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2           0x82</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3           0x82</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	pinctrl_usdhc3: usdhc3grp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='del'>-			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x190</div><div class='del'>-			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0</div><div class='del'>-			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0</div><div class='del'>-			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0</div><div class='del'>-			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0</div><div class='del'>-			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0</div><div class='del'>-			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d0</div><div class='del'>-			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d0</div><div class='del'>-			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d0</div><div class='del'>-			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d0</div><div class='del'>-			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 		0x190</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	pinctrl_usdhc3_100mhz: usdhc3grp100mhz {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x194</div><div class='del'>-			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4</div><div class='del'>-			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d4</div><div class='del'>-			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d4</div><div class='del'>-			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d4</div><div class='del'>-			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d4</div><div class='del'>-			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4</div><div class='del'>-			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d4</div><div class='del'>-			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d4</div><div class='del'>-			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4</div><div class='del'>-			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 		0x194</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	pinctrl_usdhc3_200mhz: usdhc3grp200mhz {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x196</div><div class='del'>-			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6</div><div class='del'>-			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d6</div><div class='del'>-			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d6</div><div class='del'>-			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d6</div><div class='del'>-			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d6</div><div class='del'>-			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d6</div><div class='del'>-			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d6</div><div class='del'>-			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d6</div><div class='del'>-			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d6</div><div class='del'>-			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 		0x196</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	pinctrl_wdog: wdoggrp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x190</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x190</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x194</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x194</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x196</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x196</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi<br/>new file mode 100644<br/>index 000000000000..6eab8a6001db<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi</a></div><div class='hunk'>@@ -0,0 +1,861 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2020 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/phy/phy-imx8-pcie.h&gt;</div><div class='add'>+#include &lt;dt-bindings/usb/pd.h&gt;</div><div class='add'>+#include "imx8mm.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x40000000 0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdmi-connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		label = "hdmi";</div><div class='add'>+		type = "a";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			hdmi_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;adv7535_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_led&gt;;</div><div class='add'>+</div><div class='add'>+		status {</div><div class='add'>+			label = "status";</div><div class='add'>+			gpios = &lt;&amp;gpio3 16 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "on";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_refclk: pcie0-refclk {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;100000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_pcie0: regulator-pcie {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pcie0_reg&gt;;</div><div class='add'>+		regulator-name = "MPCIE_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio1 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usdhc2_vmmc&gt;;</div><div class='add'>+		regulator-name = "VSD_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio2 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		off-on-delay-us = &lt;20000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_1v5: regulator-1v5 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_1V5";</div><div class='add'>+		regulator-min-microvolt = &lt;1500000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1500000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_1v8: regulator-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vddext_3v3: regulator-vddext-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDEXT_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	backlight: backlight {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		pwms = &lt;&amp;pwm1 0 5000000 0&gt;;</div><div class='add'>+		brightness-levels = &lt;0 255&gt;;</div><div class='add'>+		num-interpolated-steps = &lt;255&gt;;</div><div class='add'>+		default-brightness-level = &lt;250&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ir-receiver {</div><div class='add'>+		compatible = "gpio-ir-receiver";</div><div class='add'>+		gpios = &lt;&amp;gpio1 13 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_ir&gt;;</div><div class='add'>+		linux,autosuspend-period = &lt;125&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	audio_codec_bt_sco: audio-codec-bt-sco {</div><div class='add'>+		compatible = "linux,bt-sco";</div><div class='add'>+		#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wm8524: audio-codec {</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		compatible = "wlf,wm8524";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_wlf&gt;;</div><div class='add'>+		wlf,mute-gpios = &lt;&amp;gpio5 21 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-bt-sco {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,name = "bt-sco-audio";</div><div class='add'>+		simple-audio-card,format = "dsp_a";</div><div class='add'>+		simple-audio-card,bitclock-inversion;</div><div class='add'>+		simple-audio-card,frame-master = &lt;&amp;btcpu&gt;;</div><div class='add'>+		simple-audio-card,bitclock-master = &lt;&amp;btcpu&gt;;</div><div class='add'>+</div><div class='add'>+		btcpu: simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;sai2&gt;;</div><div class='add'>+			dai-tdm-slot-num = &lt;2&gt;;</div><div class='add'>+			dai-tdm-slot-width = &lt;16&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		simple-audio-card,codec {</div><div class='add'>+			sound-dai = &lt;&amp;audio_codec_bt_sco 1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-wm8524 {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,name = "wm8524-audio";</div><div class='add'>+		simple-audio-card,format = "i2s";</div><div class='add'>+		simple-audio-card,frame-master = &lt;&amp;cpudai&gt;;</div><div class='add'>+		simple-audio-card,bitclock-master = &lt;&amp;cpudai&gt;;</div><div class='add'>+		simple-audio-card,mclk-fs = &lt;256&gt;;</div><div class='add'>+		simple-audio-card,widgets =</div><div class='add'>+			"Line", "Left Line Out Jack",</div><div class='add'>+			"Line", "Right Line Out Jack";</div><div class='add'>+		simple-audio-card,routing =</div><div class='add'>+			"Left Line Out Jack", "LINEVOUTL",</div><div class='add'>+			"Right Line Out Jack", "LINEVOUTR";</div><div class='add'>+</div><div class='add'>+		cpudai: simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;sai3&gt;;</div><div class='add'>+			dai-tdm-slot-num = &lt;2&gt;;</div><div class='add'>+			dai-tdm-slot-width = &lt;32&gt;;</div><div class='add'>+			system-clock-direction-out;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		simple-audio-card,codec {</div><div class='add'>+			sound-dai = &lt;&amp;wm8524&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-micfil {</div><div class='add'>+		compatible = "fsl,imx-audio-card";</div><div class='add'>+		model = "micfil-audio";</div><div class='add'>+</div><div class='add'>+		pri-dai-link {</div><div class='add'>+			link-name = "micfil hifi";</div><div class='add'>+			format = "i2s";</div><div class='add'>+</div><div class='add'>+			cpu {</div><div class='add'>+				sound-dai = &lt;&amp;micfil&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spdif_out: spdif-out {</div><div class='add'>+		compatible = "linux,spdif-dit";</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spdif_in: spdif-in {</div><div class='add'>+		compatible = "linux,spdif-dir";</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-spdif {</div><div class='add'>+		compatible = "fsl,imx-audio-spdif";</div><div class='add'>+		model = "imx-spdif";</div><div class='add'>+		audio-cpu = &lt;&amp;spdif1&gt;;</div><div class='add'>+		audio-codec = &lt;&amp;spdif_out&gt;, &lt;&amp;spdif_in&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec1&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	fsl,magic-packet;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@0 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio4 22 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;10000&gt;;</div><div class='add'>+			qca,disable-smarteee;</div><div class='add'>+			vddio-supply = &lt;&amp;vddio&gt;;</div><div class='add'>+</div><div class='add'>+			vddio: vddio-regulator {</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pmic@4b {</div><div class='add'>+		compatible = "rohm,bd71847";</div><div class='add'>+		reg = &lt;0x4b&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;3 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		rohm,reset-snvs-powered;</div><div class='add'>+</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clocks = &lt;&amp;osc_32k&gt;;</div><div class='add'>+		clock-output-names = "clk-32k-out";</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			buck1_reg: BUCK1 {</div><div class='add'>+				regulator-name = "buck1";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;1250&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck2_reg: BUCK2 {</div><div class='add'>+				regulator-name = "buck2";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;1250&gt;;</div><div class='add'>+				rohm,dvs-run-voltage = &lt;1000000&gt;;</div><div class='add'>+				rohm,dvs-idle-voltage = &lt;900000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck3_reg: BUCK3 {</div><div class='add'>+				// BUCK5 in datasheet</div><div class='add'>+				regulator-name = "buck3";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck4_reg: BUCK4 {</div><div class='add'>+				// BUCK6 in datasheet</div><div class='add'>+				regulator-name = "buck4";</div><div class='add'>+				regulator-min-microvolt = &lt;3000000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck5_reg: BUCK5 {</div><div class='add'>+				// BUCK7 in datasheet</div><div class='add'>+				regulator-name = "buck5";</div><div class='add'>+				regulator-min-microvolt = &lt;1605000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1995000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck6_reg: BUCK6 {</div><div class='add'>+				// BUCK8 in datasheet</div><div class='add'>+				regulator-name = "buck6";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo1_reg: LDO1 {</div><div class='add'>+				regulator-name = "ldo1";</div><div class='add'>+				regulator-min-microvolt = &lt;1600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo2_reg: LDO2 {</div><div class='add'>+				regulator-name = "ldo2";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo3_reg: LDO3 {</div><div class='add'>+				regulator-name = "ldo3";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo4_reg: LDO4 {</div><div class='add'>+				regulator-name = "ldo4";</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo6_reg: LDO6 {</div><div class='add'>+				regulator-name = "ldo6";</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	hdmi@3d {</div><div class='add'>+		compatible = "adi,adv7535";</div><div class='add'>+		reg = &lt;0x3d&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;9 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		adi,dsi-lanes = &lt;4&gt;;</div><div class='add'>+		avdd-supply = &lt;&amp;buck5_reg&gt;;</div><div class='add'>+		dvdd-supply = &lt;&amp;buck5_reg&gt;;</div><div class='add'>+		pvdd-supply = &lt;&amp;buck5_reg&gt;;</div><div class='add'>+		a2vdd-supply = &lt;&amp;buck5_reg&gt;;</div><div class='add'>+		v3p3-supply = &lt;&amp;reg_vddext_3v3&gt;;</div><div class='add'>+		v1p2-supply = &lt;&amp;buck5_reg&gt;;</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				adv7535_in: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;dsi_out&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				adv7535_out: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;hdmi_connector_in&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ptn5110: tcpc@50 {</div><div class='add'>+		compatible = "nxp,ptn5110", "tcpci";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_typec1&gt;;</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio2&gt;;</div><div class='add'>+		interrupts = &lt;11 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+</div><div class='add'>+		typec1_con: connector {</div><div class='add'>+			compatible = "usb-c-connector";</div><div class='add'>+			label = "USB-C";</div><div class='add'>+			power-role = "dual";</div><div class='add'>+			data-role = "dual";</div><div class='add'>+			try-power-role = "sink";</div><div class='add'>+			source-pdos = &lt;PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)&gt;;</div><div class='add'>+			sink-pdos = &lt;PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)</div><div class='add'>+				     PDO_VAR(5000, 20000, 3000)&gt;;</div><div class='add'>+			op-sink-microwatt = &lt;15000000&gt;;</div><div class='add'>+			self-powered;</div><div class='add'>+</div><div class='add'>+			port {</div><div class='add'>+				typec1_dr_sw: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;usb1_drd_sw&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+&amp;csi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pca6416: gpio@20 {</div><div class='add'>+		compatible = "nxp,pca6416";</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;buck4_reg&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	camera@3c {</div><div class='add'>+		compatible = "ovti,ov5640";</div><div class='add'>+		reg = &lt;0x3c&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_camera&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX8MM_CLK_CLKO1&gt;;</div><div class='add'>+		clock-names = "xclk";</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX8MM_CLK_CLKO1&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;&amp;clk IMX8MM_CLK_24M&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;24000000&gt;;</div><div class='add'>+		powerdown-gpios = &lt;&amp;gpio1 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio1 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		DOVDD-supply = &lt;&amp;buck5_reg&gt;;</div><div class='add'>+		AVDD-supply = &lt;&amp;reg_1v8&gt;;</div><div class='add'>+		DVDD-supply = &lt;&amp;reg_1v5&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			ov5640_to_mipi_csi2: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;imx8mm_mipi_csi_in&gt;;</div><div class='add'>+				clock-lanes = &lt;0&gt;;</div><div class='add'>+				data-lanes = &lt;1 2&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;micfil {</div><div class='add'>+	#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pdm&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_PDM&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;196608000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_csi {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@0 {</div><div class='add'>+			imx8mm_mipi_csi_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;ov5640_to_mipi_csi2&gt;;</div><div class='add'>+				data-lanes = &lt;1 2&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_dsi {</div><div class='add'>+	samsung,esc-clock-frequency = &lt;10000000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			dsi_out: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;adv7535_in&gt;;</div><div class='add'>+				data-lanes = &lt;1 2 3 4&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	fsl,refclk-pad-mode = &lt;IMX8_PCIE_REFCLK_PAD_INPUT&gt;;</div><div class='add'>+	fsl,tx-deemph-gen1 = &lt;0x2d&gt;;</div><div class='add'>+	fsl,tx-deemph-gen2 = &lt;0xf&gt;;</div><div class='add'>+	clocks = &lt;&amp;pcie0_refclk&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie0&gt;;</div><div class='add'>+	reset-gpio = &lt;&amp;gpio4 21 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	clocks = &lt;&amp;clk IMX8MM_CLK_PCIE1_ROOT&gt;, &lt;&amp;pcie0_refclk&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX8MM_CLK_PCIE1_AUX&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_PCIE1_AUX&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MM_CLK_PCIE1_CTRL&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;10000000&gt;, &lt;250000000&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL2_50M&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MM_SYS_PLL2_250M&gt;;</div><div class='add'>+	vpcie-supply = &lt;&amp;reg_pcie0&gt;;</div><div class='add'>+	supports-clkreq;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0_ep {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie0&gt;;</div><div class='add'>+	clocks = &lt;&amp;clk IMX8MM_CLK_PCIE1_ROOT&gt;, &lt;&amp;pcie0_refclk&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX8MM_CLK_PCIE1_AUX&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_PCIE1_AUX&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MM_CLK_PCIE1_CTRL&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;10000000&gt;, &lt;250000000&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL2_50M&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MM_SYS_PLL2_250M&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai2 {</div><div class='add'>+	#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai2&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_SAI2&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;24576000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai3&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_AUDIO_PLL1&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MM_AUDIO_PLL2&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MM_CLK_SAI3&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;&amp;clk IMX8MM_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;393216000&gt;, &lt;361267200&gt;, &lt;24576000&gt;;</div><div class='add'>+	fsl,sai-mclk-direction-output;</div><div class='add'>+	clocks = &lt;&amp;clk IMX8MM_CLK_SAI3_IPG&gt;, &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;,</div><div class='add'>+		&lt;&amp;clk IMX8MM_CLK_SAI3_ROOT&gt;, &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;,</div><div class='add'>+		&lt;&amp;clk IMX8MM_CLK_DUMMY&gt;, &lt;&amp;clk IMX8MM_AUDIO_PLL1_OUT&gt;,</div><div class='add'>+		&lt;&amp;clk IMX8MM_AUDIO_PLL2_OUT&gt;;</div><div class='add'>+	clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;snvs_pwrkey {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spdif1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_spdif1&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_SPDIF1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;24576000&gt;;</div><div class='add'>+	clocks = &lt;&amp;clk IMX8MM_CLK_AUDIO_AHB&gt;, &lt;&amp;clk IMX8MM_CLK_24M&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX8MM_CLK_SPDIF1&gt;, &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;, &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX8MM_CLK_AUDIO_AHB&gt;, &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;, &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX8MM_AUDIO_PLL1_OUT&gt;, &lt;&amp;clk IMX8MM_AUDIO_PLL2_OUT&gt;;</div><div class='add'>+	clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3",</div><div class='add'>+		      "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba",</div><div class='add'>+		      "pll8k", "pll11k";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 { /* console */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbphynop1 {</div><div class='add'>+	wakeup-source;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	hnp-disable;</div><div class='add'>+	srp-disable;</div><div class='add'>+	adp-disable;</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	disable-over-current;</div><div class='add'>+	samsung,picophy-pre-emp-curr-control = &lt;3&gt;;</div><div class='add'>+	samsung,picophy-dc-vol-level-adjust = &lt;7&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	port {</div><div class='add'>+		usb1_drd_sw: endpoint {</div><div class='add'>+			remote-endpoint = &lt;&amp;typec1_dr_sw&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_USDHC2&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;200000000&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio1 15 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_backlight&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_fec1: fec1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3</div><div class='add'>+			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f</div><div class='add'>+			MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22		0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio_led: gpioledgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16	0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ir: irgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13              0x4f</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio_wlf: gpiowlfgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21	0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL			0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA			0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL			0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA			0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL			0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA			0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie0: pcie0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B    0x61</div><div class='add'>+			MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21       0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie0_reg: pcie0reggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5       0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pdm: pdmgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK        0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXC_PDM_CLK           0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC     0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0        0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1        0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2        0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3        0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: pmicirqgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x141</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai2: sai2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK      0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC     0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0    0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0    0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai3: sai3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_spdif1: spdif1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT	0xd6</div><div class='add'>+			MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN		0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_typec1: typec1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11	0x159</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140</div><div class='add'>+			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x1c4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0x166</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_backlight: backlightgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT	0x06</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_camera: cameragrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6		0x19</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x19</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1	0x59</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evkb.dts b/arch/arm64/boot/dts/freescale/imx8mm-evkb.dts<br/>new file mode 100644<br/>index 000000000000..164df627a213<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-evkb.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-evkb.dts</a></div><div class='hunk'>@@ -0,0 +1,128 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2019-2020 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mm-evk.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "FSL i.MX8MM EVKB";</div><div class='add'>+	compatible = "fsl,imx8mm-evkb", "fsl,imx8mm";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	/delete-node/ pmic@4b;</div><div class='add'>+</div><div class='add'>+	pmic@25 {</div><div class='add'>+		compatible = "nxp,pca9450a";</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;3 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			/* VDD_SOC with PCIe */</div><div class='add'>+			buck1_reg: BUCK1 {</div><div class='add'>+				regulator-name = "BUCK1";</div><div class='add'>+				regulator-min-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* VDD_ARM */</div><div class='add'>+			buck2_reg: BUCK2 {</div><div class='add'>+				regulator-name = "BUCK2";</div><div class='add'>+				regulator-min-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+				nxp,dvs-standby-voltage = &lt;850000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* VDD_GPU, VDD_VPU, VDD_DRAM */</div><div class='add'>+			buck3_reg: BUCK3 {</div><div class='add'>+				regulator-name = "BUCK3";</div><div class='add'>+				regulator-min-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* NVCC_3V3 */</div><div class='add'>+			buck4_reg: BUCK4 {</div><div class='add'>+				regulator-name = "BUCK4";</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* VDD_1V8, NVCC_1V8, NVCC_ENET */</div><div class='add'>+			buck5_reg: BUCK5 {</div><div class='add'>+				regulator-name = "BUCK5";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* NVCC_DRAM for LPDDR4 */</div><div class='add'>+			buck6_reg: BUCK6 {</div><div class='add'>+				regulator-name = "BUCK6";</div><div class='add'>+				regulator-min-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* NVCC_SNVS_1P8 */</div><div class='add'>+			ldo1_reg: LDO1 {</div><div class='add'>+				regulator-name = "LDO1";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* VDD_SNVS_0P8 */</div><div class='add'>+			ldo2_reg: LDO2 {</div><div class='add'>+				regulator-name = "LDO2";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* VDD_*_1V8 */</div><div class='add'>+			ldo3_reg: LDO3 {</div><div class='add'>+				regulator-name = "LDO3";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* VDD_PHY_0V9 */</div><div class='add'>+			ldo4_reg: LDO4 {</div><div class='add'>+				regulator-name = "LDO4";</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* NVCC_SD2 */</div><div class='add'>+			ldo5_reg: LDO5 {</div><div class='add'>+				regulator-name = "LDO5";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-ctouch2.dts b/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-ctouch2.dts<br/>new file mode 100644<br/>index 000000000000..502745402847<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-ctouch2.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-ctouch2.dts</a></div><div class='hunk'>@@ -0,0 +1,96 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2019 NXP</div><div class='add'>+ * Copyright (c) 2019 Engicam srl</div><div class='add'>+ * Copyright (c) 2020 Amarula Solutions(India)</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "imx8mm.dtsi"</div><div class='add'>+#include "imx8mm-icore-mx8mm.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Engicam i.Core MX8M Mini C.TOUCH 2.0";</div><div class='add'>+	compatible = "engicam,icore-mx8mm-ctouch2", "engicam,icore-mx8mm",</div><div class='add'>+		     "fsl,imx8mm";</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart2;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4: i2c4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL		0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140</div><div class='add'>+			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_gpio: usdhc1gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x190</div><div class='add'>+			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SD */</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;, &lt;&amp;pinctrl_usdhc1_gpio&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio1 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	max-frequency = &lt;50000000&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	no-1-8-v;</div><div class='add'>+	keep-power-in-suspend;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts b/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts<br/>new file mode 100644<br/>index 000000000000..ddac8bc7ae65<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts</a></div><div class='hunk'>@@ -0,0 +1,96 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2019 NXP</div><div class='add'>+ * Copyright (c) 2019 Engicam srl</div><div class='add'>+ * Copyright (c) 2020 Amarula Solutions(India)</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "imx8mm.dtsi"</div><div class='add'>+#include "imx8mm-icore-mx8mm.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Engicam i.Core MX8M Mini EDIMM2.2 Starter Kit";</div><div class='add'>+	compatible = "engicam,icore-mx8mm-edimm2.2", "engicam,icore-mx8mm",</div><div class='add'>+		     "fsl,imx8mm";</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart2;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4: i2c4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL		0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140</div><div class='add'>+			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_gpio: usdhc1gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x190</div><div class='add'>+			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SD */</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;, &lt;&amp;pinctrl_usdhc1_gpio&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio1 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	max-frequency = &lt;50000000&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	no-1-8-v;</div><div class='add'>+	keep-power-in-suspend;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm.dtsi<br/>new file mode 100644<br/>index 000000000000..def7bb5d37cf<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm.dtsi</a></div><div class='hunk'>@@ -0,0 +1,232 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2018 NXP</div><div class='add'>+ * Copyright (c) 2019 Engicam srl</div><div class='add'>+ * Copyright (c) 2020 Amarula Solutions(India)</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "engicam,icore-mx8mm", "fsl,imx8mm";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_buck4&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_buck4&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_buck4&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_buck4&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec1&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy&gt;;</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy: ethernet-phy@3 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;3&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio3 7 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;10000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pmic@8 {</div><div class='add'>+		compatible = "nxp,pf8121a";</div><div class='add'>+		reg = &lt;0x08&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			reg_ldo1: ldo1 {</div><div class='add'>+				regulator-min-microvolt = &lt;1500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_ldo2: ldo2 {</div><div class='add'>+				regulator-min-microvolt = &lt;1500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_ldo3: ldo3 {</div><div class='add'>+				regulator-min-microvolt = &lt;1500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_ldo4: ldo4 {</div><div class='add'>+				regulator-min-microvolt = &lt;1500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_buck1: buck1 {</div><div class='add'>+				regulator-min-microvolt = &lt;400000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_buck2: buck2 {</div><div class='add'>+				regulator-min-microvolt = &lt;400000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_buck3: buck3 {</div><div class='add'>+				regulator-min-microvolt = &lt;400000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_buck4: buck4 {</div><div class='add'>+				regulator-min-microvolt = &lt;400000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_buck5: buck5 {</div><div class='add'>+				regulator-min-microvolt = &lt;400000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_buck6: buck6 {</div><div class='add'>+				regulator-min-microvolt = &lt;400000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_buck7: buck7 {</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vsnvs: vsnvs {</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_fec1: fec1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3</div><div class='add'>+			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7		0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x190</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x190</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x194</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x194</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x196</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x196</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* eMMC */</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15-evk.dts<br/>new file mode 100644<br/>index 000000000000..055faae79930<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15-evk.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15-evk.dts</a></div><div class='hunk'>@@ -0,0 +1,146 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2018 Bang &amp; Olufsen</div><div class='add'>+ * Copyright 2022 Pengutronix</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mm-innocomm-wb15.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "InnoComm WB15-EVK";</div><div class='add'>+	compatible = "innocomm,wb15-evk", "fsl,imx8mm";</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_leds&gt;;</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			label = "debug";</div><div class='add'>+			gpios = &lt;&amp;gpio4 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vsd_3v3: regulator-vsd-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_vsd_3v3&gt;;</div><div class='add'>+		regulator-name = "VSD_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio2 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_ethphy: regulator-eth-phy {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_fec_phy_reg&gt;;</div><div class='add'>+		regulator-name = "PHY_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio1 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	fsl,magic-packet;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@1 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;0x1&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_fec_phy&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio1 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			phy-supply = &lt;&amp;reg_ethphy&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	samsung,picophy-pre-emp-curr-control = &lt;3&gt;;</div><div class='add'>+	samsung,picophy-dc-vol-level-adjust = &lt;7&gt;;</div><div class='add'>+	disable-over-current;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg2 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	samsung,picophy-pre-emp-curr-control = &lt;3&gt;;</div><div class='add'>+	samsung,picophy-dc-vol-level-adjust = &lt;7&gt;;</div><div class='add'>+	disable-over-current;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	cd-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_vsd_3v3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_fec: fec-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x03</div><div class='add'>+			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x03</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec_phy: fec-phy-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec_phy_reg: fec-phy-reg-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x16</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio_leds: led-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3	0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_vsd_3v3: reg-vsd-3v3-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi<br/>new file mode 100644<br/>index 000000000000..299752aa8277<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi</a></div><div class='hunk'>@@ -0,0 +1,477 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2018 Bang &amp; Olufsen</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "imx8mm.dtsi"</div><div class='add'>+#include &lt;dt-bindings/phy/phy-imx8-pcie.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	reg_modem: regulator-modem {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_modem_regulator&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "epdev_on";</div><div class='add'>+		gpio = &lt;&amp;gpio3 16 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3v3_out: regulator-3v3-out {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "3V3_OUT";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu_alert0 {</div><div class='add'>+	temperature = &lt;95000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu_crit0 {</div><div class='add'>+	temperature = &lt;105000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ddrc {</div><div class='add'>+	operating-points-v2 = &lt;&amp;ddrc_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+	ddrc_opp_table: opp-table {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		opp-25000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;25000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-100000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;100000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-600000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;600000000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c1_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pmic@4b {</div><div class='add'>+		compatible = "rohm,bd71847";</div><div class='add'>+		reg = &lt;0x4b&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;3 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		rohm,reset-snvs-powered;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			buck1_reg: BUCK1 {</div><div class='add'>+				regulator-name = "buck1";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;1250&gt;;</div><div class='add'>+				rohm,dvs-run-voltage = &lt;850000&gt;;</div><div class='add'>+				rohm,dvs-idle-voltage = &lt;850000&gt;;</div><div class='add'>+				rohm,dvs-suspend-voltage = &lt;850000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck2_reg: BUCK2 {</div><div class='add'>+				regulator-name = "buck2";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;1250&gt;;</div><div class='add'>+				rohm,dvs-run-voltage = &lt;1000000&gt;;</div><div class='add'>+				rohm,dvs-idle-voltage = &lt;900000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck3_reg: BUCK3 {</div><div class='add'>+				// buck5 in datasheet</div><div class='add'>+				regulator-name = "buck3";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck4_reg: BUCK4 {</div><div class='add'>+				// buck6 in datasheet</div><div class='add'>+				regulator-name = "buck4";</div><div class='add'>+				regulator-min-microvolt = &lt;3000000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck5_reg: BUCK5 {</div><div class='add'>+				// buck7 in datasheet</div><div class='add'>+				regulator-name = "buck5";</div><div class='add'>+				regulator-min-microvolt = &lt;1605000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1995000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck6_reg: BUCK6 {</div><div class='add'>+				// buck8 in datasheet</div><div class='add'>+				regulator-name = "buck6";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo1_reg: LDO1 {</div><div class='add'>+				regulator-name = "ldo1";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo2_reg: LDO2 {</div><div class='add'>+				regulator-name = "ldo2";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo3_reg: LDO3 {</div><div class='add'>+				regulator-name = "ldo3";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo4_reg: LDO4 {</div><div class='add'>+				regulator-name = "ldo4";</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo5_reg: LDO5 {</div><div class='add'>+				regulator-name = "ldo5";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo6_reg: LDO6 {</div><div class='add'>+				regulator-name = "ldo6";</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c2_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c3_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	fsl,refclk-pad-mode = &lt;IMX8_PCIE_REFCLK_PAD_OUTPUT&gt;;</div><div class='add'>+	fsl,tx-deemph-gen1 = &lt;0x2d&gt;;</div><div class='add'>+	fsl,tx-deemph-gen2 = &lt;0xf&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie0&gt;;</div><div class='add'>+	reset-gpio = &lt;&amp;gpio5 21 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	fsl,max-link-speed = &lt;1&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_PCIE1_AUX&gt;, &lt;&amp;clk IMX8MM_CLK_PCIE1_CTRL&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;10000000&gt;, &lt;250000000&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL2_50M&gt;, &lt;&amp;clk IMX8MM_SYS_PLL2_250M&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 { /* BT */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_UART1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL1_80M&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "brcm,bcm4349-bt";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_modem_bt&gt;;</div><div class='add'>+		device-wakeup-gpios = &lt;&amp;gpio3 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		host-wakeup-gpios = &lt;&amp;gpio3 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		shutdown-gpios = &lt;&amp;gpio3 15 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		vbat-supply = &lt;&amp;reg_3v3_out&gt;;</div><div class='add'>+		vddio-supply = &lt;&amp;reg_3v3_out&gt;;</div><div class='add'>+		clocks = &lt;&amp;osc_32k&gt;;</div><div class='add'>+		max-speed = &lt;3000000&gt;;</div><div class='add'>+		clock-names = "extclk";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 { /* console */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	no-sd;</div><div class='add'>+	no-sdio;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/delete-node/ &amp;sec_jr1; /* Job ring in use by OP-TEE */</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_i2c1: i2c1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL	0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA	0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1_gpio: i2c1-gpio-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14	0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15	0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL	0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA	0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2_gpio: i2c2-gpio-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16	0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17	0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3_gpio: i2c3-gpio-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18	0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19	0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie0: pcie0-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B	0x61</div><div class='add'>+			MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21	0x6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_modem_bt: modem-bt-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5			0x19</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3		0x19</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4		0x19</div><div class='add'>+			MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15		0x19</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K	0x141</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_modem_regulator: modem-reg-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16    0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: pmic-irq-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140</div><div class='add'>+			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140</div><div class='add'>+			MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B	0x140</div><div class='add'>+			MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140</div><div class='add'>+			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: usdhc1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x40000190</div><div class='add'>+			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE	0x190</div><div class='add'>+			MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x40000194</div><div class='add'>+			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE	0x194</div><div class='add'>+			MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B	0x1d4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x40000196</div><div class='add'>+			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE	0x196</div><div class='add'>+			MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B	0x1d6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2-gpio-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdog-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-iot-gateway.dts b/arch/arm64/boot/dts/freescale/imx8mm-iot-gateway.dts<br/>new file mode 100644<br/>index 000000000000..370558a8ba46<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-iot-gateway.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-iot-gateway.dts</a></div><div class='hunk'>@@ -0,0 +1,218 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+//</div><div class='add'>+// Copyright 2020 CompuLab</div><div class='add'>+</div><div class='add'>+#include "imx8mm-ucm-som.dtsi"</div><div class='add'>+#include &lt;dt-bindings/phy/phy-imx8-pcie.h&gt;</div><div class='add'>+/ {</div><div class='add'>+	model = "CompuLab i.MX8MM IoT Gateway";</div><div class='add'>+	compatible = "compulab,imx8mm-iot-gateway", "compulab,imx8mm-ucm-som", "fsl,imx8mm";</div><div class='add'>+</div><div class='add'>+	regulator-usbhub-ena {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "usbhub_ena";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio4 28 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	regulator-usbhub-rst {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "usbhub_rst";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio3 24 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	regulator-uart1-mode {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "uart1_mode";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio4 26 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	regulator-uart1-duplex {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "uart1_duplex";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio4 27 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	regulator-uart1-shdn {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "uart1_shdn";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio5 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	regulator-uart1-trmen {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "uart1_trmen";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio4 25 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	regulator-usdhc2-v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "usdhc2_v";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio1 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	regulator-mpcie2-rst {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "mpcie2_rst";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio3 22 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	regulator-mpcie2lora-dis {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "mpcie2lora_dis";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio3 21 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_refclk: clock-pcie0-refclk {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;100000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	eeprom@54 {</div><div class='add'>+		compatible = "atmel,24c08";</div><div class='add'>+		reg = &lt;0x54&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi1 &amp;pinctrl_ecspi1_cs&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	fsl,refclk-pad-mode = &lt;IMX8_PCIE_REFCLK_PAD_INPUT&gt;;</div><div class='add'>+	fsl,tx-deemph-gen1 = &lt;0x2d&gt;;</div><div class='add'>+	fsl,tx-deemph-gen2 = &lt;0xf&gt;;</div><div class='add'>+	fsl,clkreq-unsupported;</div><div class='add'>+	clocks = &lt;&amp;pcie0_refclk&gt;;</div><div class='add'>+	clock-names = "ref";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie0&gt;;</div><div class='add'>+	reset-gpio = &lt;&amp;gpio3 20 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg2 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	usbhub@1 {</div><div class='add'>+		compatible = "usb424,9514";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usb9514&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethernet: ethernet@1 {</div><div class='add'>+			compatible = "usb424,ec00";</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	mmc-ddr-1_8v;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hog&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl_hog: hoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* mPCIe2 */</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21		0x140</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22		0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi1: ecspi1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK		0x82</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI		0x82</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO		0x82</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi1_cs: ecspi1csgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9		0x40000</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie0: pcie0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20		0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usb9514: usb9514grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28		0x140 /* USB_PS_EN */</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24		0x140 /* HUB_RSTn */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-lte.dtso b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-lte.dtso<br/>new file mode 100644<br/>index 000000000000..324004b0eca3<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-lte.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-lte.dtso</a></div><div class='hunk'>@@ -0,0 +1,186 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2025 Kontron Electronics GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include "imx8mm-pinfunc.h"</div><div class='add'>+</div><div class='add'>+&amp;{/} {</div><div class='add'>+	compatible = "kontron,imx8mm-bl", "kontron,imx8mm-sl", "fsl,imx8mm";</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_keys&gt;;</div><div class='add'>+</div><div class='add'>+		key-user {</div><div class='add'>+			label = "user";</div><div class='add'>+			linux,code = &lt;BTN_0&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio4 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_led_lte&gt;;</div><div class='add'>+</div><div class='add'>+		lte-led1-b {</div><div class='add'>+			label = "lte-led1-blue";</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio3 17 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		lte-led1-g {</div><div class='add'>+			label = "lte-led1-green";</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio3 18 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		lte-led1-r {</div><div class='add'>+			label = "lte-led1-red";</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio5 23 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		lte-led2-b {</div><div class='add'>+			label = "lte-led2-blue";</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio5 25 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		lte-led2-g {</div><div class='add'>+			label = "lte-led2-green";</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio5 22 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		lte-led2-r {</div><div class='add'>+			label = "lte-led2-red";</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio5 24 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi3 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	tpm@2e {</div><div class='add'>+		compatible = "infineon,slb9673", "tcg,tpm-tis-i2c";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_tpm&gt;;</div><div class='add'>+		reg = &lt;0x2e&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+		interrupts = &lt;11 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio3&gt;;</div><div class='add'>+	gpio-line-names = "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "VDD_IO_REF", "TPM_PIRQ#",</div><div class='add'>+			  "TPM_RESET# ", "", "", "",</div><div class='add'>+			  "", "LTE_LED1_B", "LTE_LED1_G", "",</div><div class='add'>+			  "";</div><div class='add'>+</div><div class='add'>+	vdd-io-ref-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;10 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		line-name = "VDD_IO_REF";</div><div class='add'>+		output-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	tpm-reset-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		line-name = "TPM_RESET#";</div><div class='add'>+		output-low;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio4&gt;;</div><div class='add'>+	gpio-line-names = "", "", "LTE_RESET", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "LTE_PWRKEY",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "LTE_PWR_EN";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio5 {</div><div class='add'>+	gpio-line-names = "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "LTE_LED2_G", "LTE_LED1_R",</div><div class='add'>+			  "LTE_LED2_R", "LTE_LED2_B";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_gpio3: gpio3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_GPIO3_IO10		0x19 /* VDD_IO_REF */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio4: gpio4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2		0x19 /* LTE_RESET */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 		0x19 /* LTE_PWRKEY */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20		0x19 /* LTE_PWR_EN */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio_keys: gpiokeysgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12		0x19 /* Pushbutton */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio_led_lte: gpioledltegrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_GPIO3_IO17		0x19 /* LTE_LED1_B */</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_GPIO3_IO18		0x19 /* LTE_LED1_G */</div><div class='add'>+			MX8MM_IOMUXC_UART1_TXD_GPIO5_IO23		0x19 /* LTE_LED1_R */</div><div class='add'>+			MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25		0x19 /* LTE_LED2_B */</div><div class='add'>+			MX8MM_IOMUXC_UART1_RXD_GPIO5_IO22		0x19 /* LTE_LED2_G */</div><div class='add'>+			MX8MM_IOMUXC_UART2_RXD_GPIO5_IO24		0x19 /* LTE_LED2_R */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL			0x40000083 /* I2C_A_SCL */</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA			0x40000083 /* I2C_A_SDA */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_tpm: tpmgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_GPIO3_IO11		0x19 /* TPM_PIRQ# */</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_GPIO3_IO12		0x39 /* TPM_RESET# */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts<br/>new file mode 100644<br/>index 000000000000..3a166cf0afcb<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts</a></div><div class='hunk'>@@ -0,0 +1,248 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2022 Kontron Electronics GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mm-kontron-osm-s.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Kontron BL i.MX8MM OSM-S (N802X S)";</div><div class='add'>+	compatible = "kontron,imx8mm-bl-osm-s", "kontron,imx8mm-osm-s", "fsl,imx8mm";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet1 = &amp;usbnet;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* fixed crystal dedicated to mcp2542fd */</div><div class='add'>+	osc_can: clock-osc-can {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;40000000&gt;;</div><div class='add'>+		clock-output-names = "osc-can";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led1 {</div><div class='add'>+			label = "led1";</div><div class='add'>+			gpios = &lt;&amp;gpio1 5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led2 {</div><div class='add'>+			label = "led2";</div><div class='add'>+			gpios = &lt;&amp;gpio3 8 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led3 {</div><div class='add'>+			label = "led3";</div><div class='add'>+			gpios = &lt;&amp;gpio3 7 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pwm-beeper {</div><div class='add'>+		compatible = "pwm-beeper";</div><div class='add'>+		pwms = &lt;&amp;pwm2 0 5000 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vdd_5v: regulator-5v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-name = "vdd-5v";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	can@0 {</div><div class='add'>+		compatible = "microchip,mcp251xfd";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_can&gt;;</div><div class='add'>+		clocks = &lt;&amp;osc_can&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;gpio5 1 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		/*</div><div class='add'>+		 * Limit the SPI clock to 15 MHz to prevent issues</div><div class='add'>+		 * with corrupted data due to chip errata.</div><div class='add'>+		 */</div><div class='add'>+		spi-max-frequency = &lt;15000000&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;reg_vdd_3v3&gt;;</div><div class='add'>+		xceiver-supply = &lt;&amp;reg_vdd_5v&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	eeram@0 {</div><div class='add'>+		compatible = "microchip,48l640";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;20000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_enet_rgmii&gt;;</div><div class='add'>+	phy-connection-type = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy: ethernet-phy@0 {</div><div class='add'>+			compatible = "ethernet-phy-id4f51.e91b";</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			reset-assert-us = &lt;10000&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio1 3 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Rename SoM signals according to board usage:</div><div class='add'>+ *   GPIO_B_0      -&gt; DIO1_OUT</div><div class='add'>+ *   GPIO_B_1      -&gt; DIO2_OUT</div><div class='add'>+ */</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	gpio-line-names = "", "GPIO_A_0", "", "GPIO_A_1",</div><div class='add'>+			  "", "GPIO_A_2", "GPIO_A_3", "GPIO_A_4",</div><div class='add'>+			  "GPIO_A_5", "GPIO_A_6", "GPIO_A_7", "DIO1_OUT",</div><div class='add'>+			  "DIO2_OUT", "USB_A_OC#", "CAM_MCK", "USB_B_OC#",</div><div class='add'>+			  "ETH_MDC", "ETH_MDIO", "ETH_A_(S)(R)(G)MII_TXD3",</div><div class='add'>+			  "ETH_A_(S)(R)(G)MII_TXD2", "ETH_A_(S)(R)(G)MII_TXD1",</div><div class='add'>+			  "ETH_A_(S)(R)(G)MII_TXD0", "ETH_A_(R)(G)MII_TX_EN(_ER)",</div><div class='add'>+			  "ETH_A_(R)(G)MII_TX_CLK", "ETH_A_(R)(G)MII_RX_DV(_ER)",</div><div class='add'>+			  "ETH_A_(R)(G)MII_RX_CLK", "ETH_A_(S)(R)(G)MII_RXD0",</div><div class='add'>+			  "ETH_A_(S)(R)(G)MII_RXD1", "ETH_A_(R)(G)MII_RXD2",</div><div class='add'>+			  "ETH_A_(R)(G)MII_RXD3";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Rename SoM signals according to board usage:</div><div class='add'>+ *   GPIO_B_2      -&gt; DIO3_OUT</div><div class='add'>+ *   GPIO_B_3      -&gt; DIO4_OUT</div><div class='add'>+ */</div><div class='add'>+&amp;gpio3 {</div><div class='add'>+	gpio-line-names = "GPIO_C_5", "GPIO_C_4", "SDIO_B_CD#", "SDIO_B_D5",</div><div class='add'>+			  "SDIO_B_D6", "SDIO_B_D7", "GPIO_C_0", "GPIO_C_1",</div><div class='add'>+			  "GPIO_C_2", "GPIO_C_3", "SDIO_B_D0", "SDIO_B_D1",</div><div class='add'>+			  "SDIO_B_D2", "SDIO_B_D3", "", "SDIO_B_D4",</div><div class='add'>+			  "CARRIER_PWR_EN", "SDIO_B_CLK", "SDIO_B_CMD", "DIO3_OUT",</div><div class='add'>+			  "USB_B_EN", "DIO4_OUT", "PCIe_CLKREQ#", "PCIe_A_PERST#",</div><div class='add'>+			  "PCIe_WAKE#", "USB_A_EN";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Rename SoM signals according to board usage:</div><div class='add'>+ *   GPIO_B_4      -&gt; DIO1_IN</div><div class='add'>+ *   GPIO_B_5      -&gt; DIO2_IN</div><div class='add'>+ *   GPIO_B_6      -&gt; DIO3_IN</div><div class='add'>+ *   GPIO_B_7      -&gt; DIO4_IN</div><div class='add'>+ */</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	gpio-line-names = "GPIO_C_7", "", "I2S_A_DATA_IN", "I2S_B_DATA_IN",</div><div class='add'>+			  "DIO1_IN", "BOOT_SEL0#", "BOOT_SEL1#", "",</div><div class='add'>+			  "", "", "I2S_LRCLK", "I2S_BITCLK",</div><div class='add'>+			  "I2S_A_DATA_OUT", "I2S_B_DATA_OUT", "DIO2_IN", "DIO3_IN",</div><div class='add'>+			  "DIO4_IN", "SPI_A_/WP_(IO2)", "SPI_A_/HOLD_(IO3)", "GPIO_C_6",</div><div class='add'>+			  "I2S_MCLK", "UART_A_TX", "UART_A_RX", "UART_A_CTS",</div><div class='add'>+			  "UART_A_RTS", "", "", "",</div><div class='add'>+			  "PCIe_SM_ALERT", "UART_B_RTS", "UART_B_CTS", "UART_B_RX";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	usb-hub@2c {</div><div class='add'>+		compatible = "microchip,usb2514b";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usb_hub&gt;;</div><div class='add'>+		reg = &lt;0x2c&gt;;</div><div class='add'>+		non-removable-ports = &lt;0&gt;, &lt;3&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio5 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_usb2_vbus {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_usdhc2_vcc {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_usdhc3_vcc {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	linux,rs485-enabled-at-boot-time;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg2 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	disable-over-current;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* VBUS is controlled by the hub */</div><div class='add'>+	/delete-property/ vbus-supply;</div><div class='add'>+</div><div class='add'>+	usb1@1 {</div><div class='add'>+		compatible = "usb424,2514";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		usbnet: ethernet@1 {</div><div class='add'>+			compatible = "usbb95,772b";</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			local-mac-address = [ 00 00 00 00 00 00 ];</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_vdd_3v3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_can: cangrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1			0x19  /* SDIO_B_PWR_EN */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usb_hub: usbhubgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2		0x19 /* SDIO_B_WP */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts<br/>new file mode 100644<br/>index 000000000000..e756fe5db56b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts</a></div><div class='hunk'>@@ -0,0 +1,498 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2019 Kontron Electronics GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mm-kontron-sl.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Kontron BL i.MX8MM (N801X S)";</div><div class='add'>+	compatible = "kontron,imx8mm-bl", "kontron,imx8mm-sl", "fsl,imx8mm";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet1 = &amp;usbnet;</div><div class='add'>+		rtc0 = &amp;rx8900;</div><div class='add'>+		rtc1 = &amp;snvs_rtc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* fixed crystal dedicated to mcp2515 */</div><div class='add'>+	osc_can: clock-osc-can {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;16000000&gt;;</div><div class='add'>+		clock-output-names = "osc-can";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdmi-out {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		type = "a";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			hdmi_in_conn: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;bridge_out_conn&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_led&gt;;</div><div class='add'>+</div><div class='add'>+		led1 {</div><div class='add'>+			label = "led1";</div><div class='add'>+			gpios = &lt;&amp;gpio4 17 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led2 {</div><div class='add'>+			label = "led2";</div><div class='add'>+			gpios = &lt;&amp;gpio4 19 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led3 {</div><div class='add'>+			label = "led3";</div><div class='add'>+			gpios = &lt;&amp;gpio4 18 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led4 {</div><div class='add'>+			label = "led4";</div><div class='add'>+			gpios = &lt;&amp;gpio4 8 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led5 {</div><div class='add'>+			label = "led5";</div><div class='add'>+			gpios = &lt;&amp;gpio4 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led6 {</div><div class='add'>+			label = "led6";</div><div class='add'>+			gpios = &lt;&amp;gpio4 7 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pwm-beeper {</div><div class='add'>+		compatible = "pwm-beeper";</div><div class='add'>+		pwms = &lt;&amp;pwm2 0 5000 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_rst_eth2: regulator-rst-eth2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "rst-usb-eth2";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usb_eth2&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio3 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vdd_5v: regulator-5v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vdd-5v";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi2&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 13 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	can0: can@0 {</div><div class='add'>+		compatible = "microchip,mcp2515";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_can&gt;;</div><div class='add'>+		clocks = &lt;&amp;osc_can&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;28 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		spi-max-frequency = &lt;10000000&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;reg_vdd_3v3&gt;;</div><div class='add'>+		xceiver-supply = &lt;&amp;reg_vdd_5v&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi3&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 25 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_enet&gt;;</div><div class='add'>+	phy-connection-type = "rgmii-rxid";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy: ethernet-phy@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			reset-assert-us = &lt;1&gt;;</div><div class='add'>+			reset-deassert-us = &lt;15000&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio4 27 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio4&gt;;</div><div class='add'>+</div><div class='add'>+	dsi_mux_sel_hdmi: dsi-mux-sel-hdmi-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;14 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		output-high;</div><div class='add'>+		line-name = "dsi-mux-sel";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dsi_mux_sel_lvds: dsi-mux-sel-lvds-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;14 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		output-low;</div><div class='add'>+		line-name = "dsi-mux-sel";</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dsi-mux-oe-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;15 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		output-high;</div><div class='add'>+		line-name = "dsi-mux-oe";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	lvds: bridge@2c {</div><div class='add'>+		compatible = "ti,sn65dsi84";</div><div class='add'>+		reg = &lt;0x2c&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;gpio4 26 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_sn65dsi84&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdmi: hdmi@39 {</div><div class='add'>+		compatible = "adi,adv7535";</div><div class='add'>+		reg = &lt;0x39&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_adv7535&gt;;</div><div class='add'>+		adi,dsi-lanes = &lt;4&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;16 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		a2vdd-supply = &lt;&amp;reg_vdd_1v8&gt;;</div><div class='add'>+		avdd-supply = &lt;&amp;reg_vdd_1v8&gt;;</div><div class='add'>+		dvdd-supply = &lt;&amp;reg_vdd_1v8&gt;;</div><div class='add'>+		pvdd-supply = &lt;&amp;reg_vdd_1v8&gt;;</div><div class='add'>+		v1p2-supply = &lt;&amp;reg_vdd_1v8&gt;;</div><div class='add'>+		v3p3-supply = &lt;&amp;reg_vdd_3v3&gt;;</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				bridge_in_dsi_hdmi: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;mipi_dsi_out&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				bridge_out_conn: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;hdmi_in_conn&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	rx8900: rtc@32 {</div><div class='add'>+		compatible = "epson,rx8900";</div><div class='add'>+		reg = &lt;0x32&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_dsi {</div><div class='add'>+	samsung,esc-clock-frequency = &lt;54000000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_dsi_out {</div><div class='add'>+	remote-endpoint = &lt;&amp;bridge_in_dsi_hdmi&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_nvcc_sd {</div><div class='add'>+	sd-vsel-gpios = &lt;&amp;gpio1 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	/*</div><div class='add'>+	 * During bootup the CTS needs to stay LOW, which is only possible if this</div><div class='add'>+	 * pin is controlled by a GPIO. The UART IP always sets CTS to HIGH if not</div><div class='add'>+	 * running. So using 'uart-has-rtscts' is not a good choice here! There are</div><div class='add'>+	 * workarounds for this, but they introduce unnecessary complexity and are</div><div class='add'>+	 * therefore avoided here. For more information about this see:</div><div class='add'>+	 * https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit?id=79d0224f6bf296d04cd843cfc49921b19c97bb09</div><div class='add'>+	 */</div><div class='add'>+	rts-gpios = &lt;&amp;gpio4 29 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	linux,rs485-enabled-at-boot-time;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	over-current-active-low;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg2 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	disable-over-current;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	usb1@1 {</div><div class='add'>+		compatible = "usb424,9514";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		usbnet: ethernet@1 {</div><div class='add'>+			compatible = "usb424,ec00";</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			local-mac-address = [ 00 00 00 00 00 00 ];</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_vdd_3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_nvcc_sd&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl_adv7535: adv7535grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16		0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_can: cangrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28		0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi2: ecspi2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO		0x82</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI		0x82</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK		0x82</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13		0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi3: ecspi3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO		0x82</div><div class='add'>+			MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI		0x82</div><div class='add'>+			MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK		0x82</div><div class='add'>+			MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25		0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_enet: enetgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3</div><div class='add'>+			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f</div><div class='add'>+			MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27		0x19 /* PHY RST */</div><div class='add'>+			MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25		0x19 /* ETH IRQ */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio_led: gpioledgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16		0x19</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7		0x19</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8		0x19</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9		0x19</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17		0x19</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18		0x19</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19		0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio: gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x19</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x19</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x19</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x19</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6		0x19</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8		0x19</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x19</div><div class='add'>+			MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2		0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio4: gpio4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14		0x19</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15		0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL			0x40000083</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA			0x40000083</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4: i2c4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL			0x40000083</div><div class='add'>+			MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA			0x40000083</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm2: pwm2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT			0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sn65dsi84: sn65dsi84grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26		0x19</div><div class='add'>+			MX8MM_IOMUXC_SD2_WP_GPIO2_IO20			0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX		0x0</div><div class='add'>+			MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX		0x0</div><div class='add'>+			MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B		0x0</div><div class='add'>+			MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B		0x0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX		0x0</div><div class='add'>+			MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX		0x0</div><div class='add'>+			MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B		0x0</div><div class='add'>+			MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29		0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usb_eth2: usbeth2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2		0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x90</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x19</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x40000d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x94</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x19</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x40000d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x96</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x19</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x40000d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-dl.dtso b/arch/arm64/boot/dts/freescale/imx8mm-kontron-dl.dtso<br/>new file mode 100644<br/>index 000000000000..57d0739fcce3<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-kontron-dl.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-kontron-dl.dtso</a></div><div class='hunk'>@@ -0,0 +1,200 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2024 Kontron Electronics GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include "imx8mm-pinfunc.h"</div><div class='add'>+</div><div class='add'>+&amp;{/} {</div><div class='add'>+	compatible = "kontron,imx8mm-bl", "kontron,imx8mm-sl", "fsl,imx8mm";</div><div class='add'>+</div><div class='add'>+	backlight: backlight {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		pwms = &lt;&amp;pwm1 0 50000 0&gt;;</div><div class='add'>+		brightness-levels = &lt;0 100&gt;;</div><div class='add'>+		num-interpolated-steps = &lt;100&gt;;</div><div class='add'>+		default-brightness-level = &lt;100&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	panel {</div><div class='add'>+		compatible = "jenson,bl-jt60050-01a", "panel-lvds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_panel&gt;;</div><div class='add'>+		backlight = &lt;&amp;backlight&gt;;</div><div class='add'>+		data-mapping = "vesa-24";</div><div class='add'>+		enable-gpios = &lt;&amp;gpio3 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		height-mm = &lt;86&gt;;</div><div class='add'>+		width-mm = &lt;154&gt;;</div><div class='add'>+</div><div class='add'>+		panel-timing {</div><div class='add'>+			clock-frequency = &lt;51200000&gt;;</div><div class='add'>+			hactive = &lt;1024&gt;;</div><div class='add'>+			vactive = &lt;600&gt;;</div><div class='add'>+			hsync-len = &lt;1&gt;;</div><div class='add'>+			hfront-porch = &lt;160&gt;;</div><div class='add'>+			hback-porch = &lt;160&gt;;</div><div class='add'>+			vsync-len = &lt;1&gt;;</div><div class='add'>+			vfront-porch = &lt;12&gt;;</div><div class='add'>+			vback-porch = &lt;23&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			panel_out_bridge: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;bridge_out_panel&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsi_mux_sel_hdmi {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsi_mux_sel_lvds {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_dsi_out {</div><div class='add'>+	remote-endpoint = &lt;&amp;bridge_in_dsi_lvds&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio3&gt;;</div><div class='add'>+</div><div class='add'>+	panel-rst-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;20 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		output-high;</div><div class='add'>+		line-name = "panel-reset";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	panel-stby-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;21 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		output-high;</div><div class='add'>+		line-name = "panel-standby";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	panel-hinv-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;24 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		output-high;</div><div class='add'>+		line-name = "panel-horizontal-invert";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	panel-vinv-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;25 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		output-low;</div><div class='add'>+		line-name = "panel-vertical-invert";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	gt911: touchscreen@5d {</div><div class='add'>+		compatible = "goodix,gt928";</div><div class='add'>+		reg = &lt;0x5d&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_touch&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+		interrupts = &lt;22 8&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio3 23 0&gt;;</div><div class='add'>+		irq-gpios = &lt;&amp;gpio3 22 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	st1633: touchscreen@55 {</div><div class='add'>+		compatible = "sitronix,st1633";</div><div class='add'>+		reg = &lt;0x55&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_touch&gt;;</div><div class='add'>+		interrupts = &lt;22 8&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+		gpios = &lt;&amp;gpio3 22 0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lvds {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		port@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			bridge_in_dsi_lvds: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;mipi_dsi_out&gt;;</div><div class='add'>+				data-lanes = &lt;1 2&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@2 {</div><div class='add'>+			reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			bridge_out_panel: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;panel_out_bridge&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_gpio3: gpio3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24		0x19</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20		0x19</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21		0x19</div><div class='add'>+			MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25		0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL			0x40000083</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA			0x40000083</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_panel: panelgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19		0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm1: pwm1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT		0x6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_touch: touchgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22		0x19</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23		0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi<br/>new file mode 100644<br/>index 000000000000..96987910609f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi</a></div><div class='hunk'>@@ -0,0 +1,891 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2022 Kontron Electronics GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include "imx8mm.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Kontron OSM-S i.MX8MM (N802X SOM)";</div><div class='add'>+	compatible = "kontron,imx8mm-osm-s", "fsl,imx8mm";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		rtc0 = &amp;rv3028;</div><div class='add'>+		rtc1 = &amp;snvs_rtc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		/*</div><div class='add'>+		 * There are multiple SoM flavors with different DDR sizes.</div><div class='add'>+		 * The smallest is 1GB. For larger sizes the bootloader will</div><div class='add'>+		 * update the reg property.</div><div class='add'>+		 */</div><div class='add'>+		reg = &lt;0x0 0x40000000 0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart3;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb1_vbus: regulator-usb1-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usb1_vbus&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;gpio3 25 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-name = "VBUS_USB_A";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb2_vbus: regulator-usb2-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usb2_vbus&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;gpio3 20 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-name = "VBUS_USB_B";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vcc: regulator-usdhc2-vcc {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usdhc2_vcc&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;gpio2 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "VCC_SDIO_A";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc3_vcc: regulator-usdhc3-vcc {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usdhc3_vcc&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;gpio5 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "VCC_SDIO_B";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vdd_carrier: regulator-vdd-carrier {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_vdd_carrier&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio3 16 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-name = "VDD_CARRIER";</div><div class='add'>+</div><div class='add'>+		regulator-state-standby {</div><div class='add'>+			regulator-on-in-suspend;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		regulator-state-mem {</div><div class='add'>+			regulator-off-in-suspend;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		regulator-state-disk {</div><div class='add'>+			regulator-off-in-suspend;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_vdd_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_vdd_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_vdd_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_vdd_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ddrc {</div><div class='add'>+	operating-points-v2 = &lt;&amp;ddrc_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+	ddrc_opp_table: opp-table {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		opp-100000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;100000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-750000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;750000000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi1&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash@0 {</div><div class='add'>+		compatible = "mxicy,mx25r1635f", "jedec,spi-nor";</div><div class='add'>+		spi-max-frequency = &lt;80000000&gt;;</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		partitions {</div><div class='add'>+			compatible = "fixed-partitions";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			partition@0 {</div><div class='add'>+				label = "u-boot";</div><div class='add'>+				reg = &lt;0x0 0x1e0000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			partition@1e0000 {</div><div class='add'>+				label = "env";</div><div class='add'>+				reg = &lt;0x1e0000 0x10000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			partition@1f0000 {</div><div class='add'>+				label = "env_redundant";</div><div class='add'>+				reg = &lt;0x1f0000 0x10000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi2&gt;, &lt;&amp;pinctrl_ecspi2_gpio&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 13 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi3&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 25 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio1&gt;;</div><div class='add'>+	gpio-line-names = "", "GPIO_A_0", "", "GPIO_A_1",</div><div class='add'>+			  "", "GPIO_A_2", "GPIO_A_3", "GPIO_A_4",</div><div class='add'>+			  "GPIO_A_5", "GPIO_A_6", "GPIO_A_7", "GPIO_B_0",</div><div class='add'>+			  "GPIO_B_1", "USB_A_OC#", "CAM_MCK", "USB_B_OC#",</div><div class='add'>+			  "ETH_MDC", "ETH_MDIO", "ETH_A_(S)(R)(G)MII_TXD3",</div><div class='add'>+			  "ETH_A_(S)(R)(G)MII_TXD2", "ETH_A_(S)(R)(G)MII_TXD1",</div><div class='add'>+			  "ETH_A_(S)(R)(G)MII_TXD0", "ETH_A_(R)(G)MII_TX_EN(_ER)",</div><div class='add'>+			  "ETH_A_(R)(G)MII_TX_CLK", "ETH_A_(R)(G)MII_RX_DV(_ER)",</div><div class='add'>+			  "ETH_A_(R)(G)MII_RX_CLK", "ETH_A_(S)(R)(G)MII_RXD0",</div><div class='add'>+			  "ETH_A_(S)(R)(G)MII_RXD1", "ETH_A_(R)(G)MII_RXD2",</div><div class='add'>+			  "ETH_A_(R)(G)MII_RXD3";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio2 {</div><div class='add'>+	gpio-line-names = "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "SDIO_A_CD#", "SDIO_A_CLK", "SDIO_A_CMD", "SDIO_A_D0",</div><div class='add'>+			  "SDIO_A_D1", "SDIO_A_D2", "SDIO_A_D3", "SDIO_A_PWR_EN",</div><div class='add'>+			  "SDIO_A_WP";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio3&gt;;</div><div class='add'>+	gpio-line-names = "GPIO_C_5", "GPIO_C_4", "SDIO_B_CD#", "SDIO_B_D5",</div><div class='add'>+			  "SDIO_B_D6", "SDIO_B_D7", "GPIO_C_0", "GPIO_C_1",</div><div class='add'>+			  "GPIO_C_2", "GPIO_C_3", "SDIO_B_D0", "SDIO_B_D1",</div><div class='add'>+			  "SDIO_B_D2", "SDIO_B_D3", "", "SDIO_B_D4",</div><div class='add'>+			  "CARRIER_PWR_EN", "SDIO_B_CLK", "SDIO_B_CMD", "GPIO_B_2",</div><div class='add'>+			  "USB_B_EN", "GPIO_B_3", "PCIe_CLKREQ#", "PCIe_A_PERST#",</div><div class='add'>+			  "PCIe_WAKE#", "USB_A_EN";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio4&gt;;</div><div class='add'>+	gpio-line-names = "GPIO_C_7", "", "I2S_A_DATA_IN", "I2S_B_DATA_IN",</div><div class='add'>+			  "GPIO_B_4", "BOOT_SEL0#", "BOOT_SEL1#", "",</div><div class='add'>+			  "", "", "I2S_LRCLK", "I2S_BITCLK",</div><div class='add'>+			  "I2S_A_DATA_OUT", "I2S_B_DATA_OUT", "GPIO_B_5", "GPIO_B_6",</div><div class='add'>+			  "GPIO_B_7", "SPI_A_/WP_(IO2)", "SPI_A_/HOLD_(IO3)", "GPIO_C_6",</div><div class='add'>+			  "I2S_MCLK", "UART_A_TX", "UART_A_RX", "UART_A_CTS",</div><div class='add'>+			  "UART_A_RTS", "", "", "",</div><div class='add'>+			  "PCIe_SM_ALERT", "UART_B_RTS", "UART_B_CTS", "UART_B_RX";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio5 {</div><div class='add'>+	gpio-line-names = "UART_B_TX", "SDIO_B_PWR_EN", "SDIO_B_WP", "PWM_2",</div><div class='add'>+			  "PWM_1", "PWM_0", "", "",</div><div class='add'>+			  "", "", "SPI_A_SCK", "SPI_A_SDO_(IO1)",</div><div class='add'>+			  "SPI_A_SCK", "SPI_A_CS0#", "", "",</div><div class='add'>+			  "I2C_A_SCL", "I2C_A_SDA", "I2C_B_SCL", "I2C_B_SDA",</div><div class='add'>+			  "PCIe_SMCLK", "PCIe_SMDAT", "SPI_B_SCK", "SPI_B_SDO",</div><div class='add'>+			  "SPI_B_SDI", "SPI_B_CS0#", "UART_CON_RX", "UART_CON_TX",</div><div class='add'>+			  "UART_C_RX", "UART_C_TX";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pca9450: pmic@25 {</div><div class='add'>+		compatible = "nxp,pca9450a";</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;0 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			reg_vdd_soc: BUCK1 {</div><div class='add'>+				regulator-name = "+0V8_VDD_SOC (BUCK1)";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+				nxp,dvs-run-voltage = &lt;850000&gt;;</div><div class='add'>+				nxp,dvs-standby-voltage = &lt;800000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vdd_arm: BUCK2 {</div><div class='add'>+				regulator-name = "+0V9_VDD_ARM (BUCK2)";</div><div class='add'>+				regulator-min-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;950000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+				nxp,dvs-run-voltage = &lt;950000&gt;;</div><div class='add'>+				nxp,dvs-standby-voltage = &lt;850000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vdd_dram: BUCK3 {</div><div class='add'>+				regulator-name = "+0V9_VDD_DRAM&amp;PU (BUCK3)";</div><div class='add'>+				regulator-min-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;950000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vdd_3v3: BUCK4 {</div><div class='add'>+				regulator-name = "+3V3 (BUCK4)";</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vdd_1v8: BUCK5 {</div><div class='add'>+				regulator-name = "+1V8 (BUCK5)";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_nvcc_dram: BUCK6 {</div><div class='add'>+				regulator-name = "+1V1_NVCC_DRAM (BUCK6)";</div><div class='add'>+				regulator-min-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_nvcc_snvs: LDO1 {</div><div class='add'>+				regulator-name = "+1V8_NVCC_SNVS (LDO1)";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vdd_snvs: LDO2 {</div><div class='add'>+				regulator-name = "+0V8_VDD_SNVS (LDO2)";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vdda: LDO3 {</div><div class='add'>+				regulator-name = "+1V8_VDDA (LDO3)";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vdd_phy: LDO4 {</div><div class='add'>+				regulator-name = "+0V9_VDD_PHY (LDO4)";</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_nvcc_sd: LDO5 {</div><div class='add'>+				regulator-name = "NVCC_SD (LDO5)";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				sd-vsel-gpios = &lt;&amp;gpio1 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom: eeprom@50 {</div><div class='add'>+		compatible = "atmel,24c64";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		address-width = &lt;16&gt;;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		size = &lt;8192&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rv3028: rtc@52 {</div><div class='add'>+		compatible = "microcrystal,rv3028";</div><div class='add'>+		reg = &lt;0x52&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_rtc&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;gpio4 1 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c4&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart3 { /* console */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart4&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usb1&gt;;</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usb1_vbus&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usb2&gt;;</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usb2_vbus&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1_200mhz&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_vdd_3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_vdd_1v8&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vcc&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_nvcc_sd&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;, &lt;&amp;pinctrl_usdhc3_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;, &lt;&amp;pinctrl_usdhc3_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;, &lt;&amp;pinctrl_usdhc3_gpio&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc3_vcc&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_nvcc_sd&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio3 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_csi_mck: csimckgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1	0x59 /* CAM_MCK */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi1: ecspi1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO		0x82</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI		0x82</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK		0x82</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9		0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi2: ecspi2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO		0x82 /* SPI_A_SDI_(IO0) */</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI		0x82 /* SPI_A_SDO_(IO1) */</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK		0x82 /* SPI_A_SCK */</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13		0x19 /* SPI_A_CS0# */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi2_gpio: ecspi2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17		0x19 /* SPI_A_/WP_(IO2) */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18		0x19 /* SPI_A_/HOLD_(IO3) */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi3: ecspi3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO		0x82 /* SPI_B_SDI */</div><div class='add'>+			MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI		0x82 /* SPI_B_SDO */</div><div class='add'>+			MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK		0x82 /* SPI_B_SCK */</div><div class='add'>+			MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25		0x19 /* SPI_B_CS0# */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_enet_rgmii: enetrgmiigrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x03 /* ETH_MDC */</div><div class='add'>+			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x03 /* ETH_MDIO */</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f /* ETH_A_(S)(R)(G)MII_TXD3 */</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f /* ETH_A_(S)(R)(G)MII_TXD2 */</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f /* ETH_A_(S)(R)(G)MII_TXD1 */</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f /* ETH_A_(S)(R)(G)MII_TXD0 */</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91 /* ETH_A_(R)(G)MII_RXD3 */</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91 /* ETH_A_(R)(G)MII_RXD2 */</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91 /* ETH_A_(S)(R)(G)MII_RXD1 */</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91 /* ETH_A_(S)(R)(G)MII_RXD0 */</div><div class='add'>+			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f /* ETH_A_(R)(G)MII_TX_CLK */</div><div class='add'>+			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91 /* ETH_A_(R)(G)MII_RX_CLK */</div><div class='add'>+			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91 /* ETH_A_(R)(G)MII_RX_DV(_ER) */</div><div class='add'>+			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f /* ETH_A_(R)(G)MII_TX_EN(_ER) */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_enet_rmii: enetrmiigrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x03 /* ETH_MDC */</div><div class='add'>+			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x03 /* ETH_MDIO */</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK		0x4000001f /* ETH_A_(S)(R)(G)MII_TXD2 */</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x56 /* ETH_A_(S)(R)(G)MII_TXD1 */</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x56 /* ETH_A_(S)(R)(G)MII_TXD0 */</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x56 /* ETH_A_(S)(R)(G)MII_RXD1 */</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x56 /* ETH_A_(S)(R)(G)MII_RXD0 */</div><div class='add'>+			MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER		0x56 /* ETH_A_(R)(G)MII_RX_CLK */</div><div class='add'>+			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x56 /* ETH_A_(R)(G)MII_RX_DV(_ER) */</div><div class='add'>+			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x56 /* ETH_A_(R)(G)MII_TX_EN(_ER) */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio1: gpio1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1		0x19 /* GPIO_A_0 */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x19 /* GPIO_A_1 */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5		0x19 /* GPIO_A_2 */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6		0x19 /* GPIO_A_3 */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x19 /* GPIO_A_4 */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8		0x19 /* GPIO_A_5 */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x19 /* GPIO_A_6 */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x19 /* GPIO_A_7 */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x19 /* GPIO_B_0 */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12		0x19 /* GPIO_B_1 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio3: gpio3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0			0x19 /* GPIO_C_5 */</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1		0x19 /* GPIO_C_4 */</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6		0x19 /* GPIO_C_0 */</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7		0x19 /* GPIO_C_1 */</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8		0x19 /* GPIO_C_2 */</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9		0x19 /* GPIO_C_3 */</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19		0x19 /* GPIO_B_2 */</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21		0x19 /* GPIO_B_3 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio4: gpio4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0		0x19 /* GPIO_C_7 */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4		0x19 /* GPIO_B_4 */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5		0x19 /* BOOT_SEL0# */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6		0x19 /* BOOT_SEL1# */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14		0x19 /* GPIO_B_5 */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15		0x19 /* GPIO_B_6 */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16		0x19 /* GPIO_B_7 */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19		0x19 /* GPIO_C_6 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL			0x40000083</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA			0x40000083</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL			0x40000083 /* I2C_A_SCL */</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA			0x40000083 /* I2C_A_SDA */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL			0x40000083 /* I2C_B_SCL */</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA			0x40000083 /* I2C_B_SDA */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4: i2c4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL			0x40000083 /* PCIe_SMCLK and I2C_CAM_SCL/CSI_TX_P */</div><div class='add'>+			MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA			0x40000083 /* PCIe_SMDAT and I2C_CAM_SDA/CSI_TX_N */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie: pciegrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22		0x19 /* PCIe_CLKREQ# */</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23		0x19 /* PCIe_A_PERST# */</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24		0x19 /* PCIe_WAKE# */</div><div class='add'>+			MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28		0x19 /* PCIe_SM_ALERT */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: pmicgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0		0x141</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm1: pwm1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT		0x19 /* PWM_0 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm2: pwm2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT			0x19 /* PWM_1 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm3: pwm3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT			0x19 /* PWM_2 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usb1_vbus: regusb1vbusgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25		0x19 /* USB_A_EN */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usb2_vbus: regusb2vbusgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20		0x19 /* USB_B_EN */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usdhc2_vcc: regusdhc2vccgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19		0x19 /* SDIO_A_PWR_EN */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usdhc3_vcc: regusdhc3vccgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1			0x19 /* SDIO_B_PWR_EN */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_vdd_carrier: regvddcarriergrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16		0x19 /* CARRIER_PWR_EN */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_rtc: rtcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1			0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai1: sai1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0		0xd6 /* I2S_A_DATA_IN */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0		0xd6 /* I2S_A_DATA_OUT */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1		0xd6 /* I2S_B_DATA_IN */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1		0xd6 /* I2S_B_DATA_OUT */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK		0xd6 /* I2S_MCLK */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC		0xd6 /* I2S_LRCLK */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK		0xd6 /* I2S_BITCLK */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX		0x0 /* UART_A_RX */</div><div class='add'>+			MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX		0x0 /* UART_A_TX */</div><div class='add'>+			MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B		0x0 /* UART_A_CTS */</div><div class='add'>+			MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B		0x0 /* UART_A_RTS */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX		0x0 /* UART_B_RX */</div><div class='add'>+			MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX		0x0 /* UART_B_TX */</div><div class='add'>+			MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B		0x0 /* UART_B_CTS */</div><div class='add'>+			MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B		0x0 /* UART_B_RTS */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: uart3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX		0x140 /* UART_CON_RX */</div><div class='add'>+			MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX		0x140 /* UART_CON_TX */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart4: uart4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX		0x0 /* UART_C_RX */</div><div class='add'>+			MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX		0x0 /* UART_C_TX */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usb1: usb1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC		0x19 /* USB_A_OC# */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usb2: usb2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC		0x19 /* USB_B_OC# */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK			0x190</div><div class='add'>+			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD			0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0x019</div><div class='add'>+			MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x190</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK			0x194</div><div class='add'>+			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD			0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0x019</div><div class='add'>+			MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x194</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK			0x196</div><div class='add'>+			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD			0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0x019</div><div class='add'>+			MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x196</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x90 /* SDIO_A_CLK */</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d0 /* SDIO_A_CMD */</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d0 /* SDIO_A_D0 */</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d0 /* SDIO_A_D1 */</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d0 /* SDIO_A_D2 */</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d0 /* SDIO_A_D3 */</div><div class='add'>+			MX8MM_IOMUXC_SD2_WP_USDHC2_WP			0x400000d6 /* SDIO_A_WP */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x40000090</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x94 /* SDIO_A_CLK */</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d4 /* SDIO_A_CMD */</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d4 /* SDIO_A_D0 */</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d4 /* SDIO_A_D1 */</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d4 /* SDIO_A_D2 */</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d4 /* SDIO_A_D3 */</div><div class='add'>+			MX8MM_IOMUXC_SD2_WP_USDHC2_WP			0x400000d6 /* SDIO_A_WP */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x40000090</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x96 /* SDIO_A_CLK */</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d6 /* SDIO_A_CMD */</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d6 /* SDIO_A_D0 */</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d6 /* SDIO_A_D1 */</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d6 /* SDIO_A_D2 */</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d6 /* SDIO_A_D3 */</div><div class='add'>+			MX8MM_IOMUXC_SD2_WP_USDHC2_WP			0x400000d6 /* SDIO_A_WP */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x40000090</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x19 /* SDIO_A_CD# */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x90 /* SDIO_B_CLK */</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x90 /* SDIO_B_CMD */</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x90 /* SDIO_B_D0 */</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x90 /* SDIO_B_D1 */</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x90 /* SDIO_B_D2 */</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x90 /* SDIO_B_D3 */</div><div class='add'>+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x90 /* SDIO_B_D4 */</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x90 /* SDIO_B_D5 */</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x90 /* SDIO_B_D6 */</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x90 /* SDIO_B_D7 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x94 /* SDIO_B_CLK */</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x94 /* SDIO_B_CMD */</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x94 /* SDIO_B_D0 */</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x94 /* SDIO_B_D1 */</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x94 /* SDIO_B_D2 */</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x94 /* SDIO_B_D3 */</div><div class='add'>+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x94 /* SDIO_B_D4 */</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x94 /* SDIO_B_D5 */</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x94 /* SDIO_B_D6 */</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x94 /* SDIO_B_D7 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x96 /* SDIO_B_CLK */</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x96 /* SDIO_B_CMD */</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x96 /* SDIO_B_D0 */</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x96 /* SDIO_B_D1 */</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x96 /* SDIO_B_D2 */</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x96 /* SDIO_B_D3 */</div><div class='add'>+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x96 /* SDIO_B_D4 */</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x96 /* SDIO_B_D5 */</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x96 /* SDIO_B_D6 */</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x96 /* SDIO_B_D7 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_gpio: usdhc3gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2		0x19 /* SDIO_B_CD# */</div><div class='add'>+			MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2		0x19 /* SDIO_B_WP */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0xc6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi<br/>new file mode 100644<br/>index 000000000000..2076148e0862<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi</a></div><div class='hunk'>@@ -0,0 +1,314 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2019 Kontron Electronics GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "imx8mm.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Kontron SL i.MX8MM (N801X SOM)";</div><div class='add'>+	compatible = "kontron,imx8mm-sl", "fsl,imx8mm";</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		/*</div><div class='add'>+		 * There are multiple SoM flavors with different DDR sizes.</div><div class='add'>+		 * The smallest is 1GB. For larger sizes the bootloader will</div><div class='add'>+		 * update the reg property.</div><div class='add'>+		 */</div><div class='add'>+		reg = &lt;0x0 0x40000000 0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart3;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_vdd_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_vdd_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_vdd_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_vdd_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ddrc {</div><div class='add'>+	operating-points-v2 = &lt;&amp;ddrc_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+	ddrc_opp_table: opp-table {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		opp-100000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;100000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-750000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;750000000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi1&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash@0 {</div><div class='add'>+		compatible = "mxicy,mx25r1635f", "jedec,spi-nor";</div><div class='add'>+		spi-max-frequency = &lt;80000000&gt;;</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		partitions {</div><div class='add'>+			compatible = "fixed-partitions";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			partition@0 {</div><div class='add'>+				label = "u-boot";</div><div class='add'>+				reg = &lt;0x0 0x1e0000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			partition@1e0000 {</div><div class='add'>+				label = "env";</div><div class='add'>+				reg = &lt;0x1e0000 0x10000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			partition@1f0000 {</div><div class='add'>+				label = "env_redundant";</div><div class='add'>+				reg = &lt;0x1f0000 0x10000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pca9450: pmic@25 {</div><div class='add'>+		compatible = "nxp,pca9450a";</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;0 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			reg_vdd_soc: BUCK1 {</div><div class='add'>+				regulator-name = "+0V8_VDD_SOC (BUCK1)";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+				nxp,dvs-run-voltage = &lt;850000&gt;;</div><div class='add'>+				nxp,dvs-standby-voltage = &lt;800000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vdd_arm: BUCK2 {</div><div class='add'>+				regulator-name = "+0V9_VDD_ARM (BUCK2)";</div><div class='add'>+				regulator-min-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;950000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+				nxp,dvs-run-voltage = &lt;950000&gt;;</div><div class='add'>+				nxp,dvs-standby-voltage = &lt;850000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vdd_dram: BUCK3 {</div><div class='add'>+				regulator-name = "+0V9_VDD_DRAM&amp;PU (BUCK3)";</div><div class='add'>+				regulator-min-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;950000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vdd_3v3: BUCK4 {</div><div class='add'>+				regulator-name = "+3V3 (BUCK4)";</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vdd_1v8: BUCK5 {</div><div class='add'>+				regulator-name = "+1V8 (BUCK5)";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_nvcc_dram: BUCK6 {</div><div class='add'>+				regulator-name = "+1V1_NVCC_DRAM (BUCK6)";</div><div class='add'>+				regulator-min-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_nvcc_snvs: LDO1 {</div><div class='add'>+				regulator-name = "+1V8_NVCC_SNVS (LDO1)";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vdd_snvs: LDO2 {</div><div class='add'>+				regulator-name = "+0V8_VDD_SNVS (LDO2)";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vdda: LDO3 {</div><div class='add'>+				regulator-name = "+1V8_VDDA (LDO3)";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vdd_phy: LDO4 {</div><div class='add'>+				regulator-name = "+0V9_VDD_PHY (LDO4)";</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_nvcc_sd: LDO5 {</div><div class='add'>+				regulator-name = "NVCC_SD (LDO5)";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart3 { /* console */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1_200mhz&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_vdd_3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_vdd_1v8&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_ecspi1: ecspi1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO		0x82</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI		0x82</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK		0x82</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9		0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL			0x40000083</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA			0x40000083</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: pmicgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0		0x141</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: uart3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX		0x140</div><div class='add'>+			MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX		0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK			0x190</div><div class='add'>+			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD			0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0x019</div><div class='add'>+			MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x190</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK			0x194</div><div class='add'>+			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD			0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0x019</div><div class='add'>+			MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x194</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK			0x196</div><div class='add'>+			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD			0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0x019</div><div class='add'>+			MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x196</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0xc6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts b/arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts<br/>new file mode 100644<br/>index 000000000000..0b123a84018b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts</a></div><div class='hunk'>@@ -0,0 +1,335 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021-2022 Marek Vasut &lt;marex@denx.de&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mm-verdin.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "MENLO MX8MM EMBEDDED DEVICE";</div><div class='add'>+	compatible = "menlo,mx8menlo",</div><div class='add'>+		     "toradex,verdin-imx8mm-nonwifi",</div><div class='add'>+		     "toradex,verdin-imx8mm",</div><div class='add'>+		     "fsl,imx8mm";</div><div class='add'>+</div><div class='add'>+	/delete-node/ gpio-keys;</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_led&gt;;</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			label = "TestLed601";</div><div class='add'>+			gpios = &lt;&amp;gpio4 18 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "mmc0";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-2 {</div><div class='add'>+			label = "TestLed602";</div><div class='add'>+			gpios = &lt;&amp;gpio4 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	beeper {</div><div class='add'>+		compatible = "gpio-beeper";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_beeper&gt;;</div><div class='add'>+		gpios = &lt;&amp;gpio5 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Fixed clock dedicated to SPI CAN on carrier board */</div><div class='add'>+	clk_xtal20: clk-xtal20 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;20000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi1 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi1&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* CAN controller on the baseboard */</div><div class='add'>+	canfd: can@0 {</div><div class='add'>+		compatible = "microchip,mcp2518fd";</div><div class='add'>+		clocks = &lt;&amp;clk_xtal20&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;8 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;2000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi2 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi2 &amp;pinctrl_gpio1&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 13 GPIO_ACTIVE_LOW&gt;, &lt;&amp;gpio3 4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	spidev@0 {</div><div class='add'>+		compatible = "menlo,m53cpld";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;25000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spidev@1 {</div><div class='add'>+		compatible = "menlo,m53cpld";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		spi-max-frequency = &lt;25000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethphy0 {</div><div class='add'>+	max-speed = &lt;100&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexspi {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash@0 {</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		spi-max-frequency = &lt;66000000&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;4&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio2 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio3 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "DISP_reset", "KBD_intI",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	/*</div><div class='add'>+	 * CPLD_D[n] is ARM_CPLD[n] in schematic</div><div class='add'>+	 * CPLD_int is SA_INTERRUPT in schematic</div><div class='add'>+	 * CPLD_reset is RESET_SOFT in schematic</div><div class='add'>+	 */</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"CPLD_D[6]", "CPLD_int", "CPLD_reset", "",</div><div class='add'>+		"", "CPLD_D[7]", "", "",</div><div class='add'>+		"", "", "", "CPLD_D[5]",</div><div class='add'>+		"CPLD_D[4]", "CPLD_D[3]", "CPLD_D[2]", "CPLD_D[1]",</div><div class='add'>+		"CPLD_D[0]", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "KBD_intK",</div><div class='add'>+		"", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio5 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio_expander_21 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hwmon {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	/* None of this is present on the SoM. */</div><div class='add'>+	/delete-node/ bridge@2c;</div><div class='add'>+	/delete-node/ hdmi@48;</div><div class='add'>+	/delete-node/ touch@4a;</div><div class='add'>+	/delete-node/ sensor@4f;</div><div class='add'>+	/delete-node/ eeprom@50;</div><div class='add'>+	/delete-node/ eeprom@57;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio7&gt;, &lt;&amp;pinctrl_gpio_hog1&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_gpio_hog2&gt;, &lt;&amp;pinctrl_gpio_hog3&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl_beeper: beepergrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3			0x1c4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi1: ecspi1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK		0x4</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI		0x4</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO		0x1c4</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9		0x1c4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_led: ledgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18		0x1c4</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10		0x1c4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart4_rts: uart4rtsgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* SODIMM 222 */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x184</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_gpio1 {</div><div class='add'>+	fsl,pins = &lt;</div><div class='add'>+		/* SODIMM 206 */</div><div class='add'>+		MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4			0x1c4</div><div class='add'>+	&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_gpio_hog1 {</div><div class='add'>+	fsl,pins = &lt;</div><div class='add'>+		/* SODIMM 88 */</div><div class='add'>+		MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20			0x1c4</div><div class='add'>+		/* CPLD_int */</div><div class='add'>+		MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1				0x1c4</div><div class='add'>+		/* CPLD_reset */</div><div class='add'>+		MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2			0x1c4</div><div class='add'>+		/* SODIMM 94 */</div><div class='add'>+		MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3			0x1c4</div><div class='add'>+		/* SODIMM 96 */</div><div class='add'>+		MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4			0x1c4</div><div class='add'>+		/* CPLD_D[7] */</div><div class='add'>+		MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5			0x184</div><div class='add'>+		/* CPLD_D[6] */</div><div class='add'>+		MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0			0x184</div><div class='add'>+		/* CPLD_D[5] */</div><div class='add'>+		MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11			0x184</div><div class='add'>+		/* CPLD_D[4] */</div><div class='add'>+		MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12			0x184</div><div class='add'>+		/* CPLD_D[3] */</div><div class='add'>+		MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13			0x184</div><div class='add'>+		/* CPLD_D[2] */</div><div class='add'>+		MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14			0x184</div><div class='add'>+		/* CPLD_D[1] */</div><div class='add'>+		MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15			0x184</div><div class='add'>+		/* CPLD_D[0] */</div><div class='add'>+		MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16			0x184</div><div class='add'>+		/* KBD_intK */</div><div class='add'>+		MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27			0x1c4</div><div class='add'>+		/* DISP_reset */</div><div class='add'>+		MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22			0x1c4</div><div class='add'>+		/* KBD_intI */</div><div class='add'>+		MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23			0x1c4</div><div class='add'>+		/* SODIMM 46 */</div><div class='add'>+		MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24			0x1c4</div><div class='add'>+	&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_uart1 {</div><div class='add'>+	fsl,pins = &lt;</div><div class='add'>+		/* SODIMM 149 */</div><div class='add'>+		MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX			0x1c4</div><div class='add'>+		/* SODIMM 147 */</div><div class='add'>+		MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX			0x1c4</div><div class='add'>+		/* SODIMM 210 */</div><div class='add'>+		MX8MM_IOMUXC_UART3_RXD_UART1_DTE_RTS_B			0x1c4</div><div class='add'>+		/* SODIMM 212 */</div><div class='add'>+		MX8MM_IOMUXC_UART3_TXD_UART1_DTE_CTS_B			0x1c4</div><div class='add'>+	&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_usb_otg1_vbus {</div><div class='add'>+	/delete-property/ enable-active-high;</div><div class='add'>+	gpio = &lt;&amp;gpio1 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_usb_otg2_vbus {</div><div class='add'>+	/delete-property/ enable-active-high;</div><div class='add'>+	gpio = &lt;&amp;gpio1 14 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai2 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart4 &amp;pinctrl_uart4_rts&gt;;</div><div class='add'>+	linux,rs485-enabled-at-boot-time;</div><div class='add'>+	rts-gpios = &lt;&amp;gpio1 9 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	dr_mode = "peripheral";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg2 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts b/arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts<br/>new file mode 100644<br/>index 000000000000..12fb79d20b29<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts</a></div><div class='hunk'>@@ -0,0 +1,701 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Device Tree file for Boundary Devices i.MX8MMini Nitrogen8MM Rev2 board.</div><div class='add'>+ * Adrien Grassein &lt;adrien.grassein@gmail.com.com&gt;</div><div class='add'>+ */</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "imx8mm.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Boundary Devices i.MX8MMini Nitrogen8MM Rev2";</div><div class='add'>+	compatible = "boundary,imx8mm-nitrogen8mm", "fsl,imx8mm";</div><div class='add'>+</div><div class='add'>+	reg_vref_1v8: regulator-vref-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vref-1v8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vref_3v3: regulator-vref-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vref-3v3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_wlan_vmmc: regulator-wlan-vmmc {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_wlan_vmmc&gt;;</div><div class='add'>+		regulator-name = "reg_wlan_vmmc";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio3 20 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-wm8960 {</div><div class='add'>+		audio-cpu = &lt;&amp;sai1&gt;;</div><div class='add'>+		audio-codec = &lt;&amp;wm8960&gt;;</div><div class='add'>+		audio-routing =</div><div class='add'>+			"Headphone Jack", "HP_L",</div><div class='add'>+			"Headphone Jack", "HP_R",</div><div class='add'>+			"Ext Spk", "SPK_LP",</div><div class='add'>+			"Ext Spk", "SPK_LN",</div><div class='add'>+			"Ext Spk", "SPK_RP",</div><div class='add'>+			"Ext Spk", "SPK_RN",</div><div class='add'>+			"RINPUT1", "Mic Jack",</div><div class='add'>+			"Mic Jack", "MICB";</div><div class='add'>+		compatible = "fsl,imx-audio-wm8960";</div><div class='add'>+		/* JD2: hp detect high for headphone*/</div><div class='add'>+		hp-det-gpios = &lt;&amp;gpio4 28 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		/* Jack is not stuffed */</div><div class='add'>+		mic-det-gpios = &lt;&amp;gpio1 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		model = "wm8960-audio";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_sound_wm8960&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_buck3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_buck3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_buck3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_buck3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* J15 */</div><div class='add'>+&amp;ecspi2 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_ECSPI2&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL1_40M&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;40000000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi2&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 13 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec1&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	fsl,magic-packet;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@4 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;4&gt;;</div><div class='add'>+			interrupts-extended = &lt;&amp;gpio3 16 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexspi {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexspi&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pmic@8 {</div><div class='add'>+		compatible = "nxp,pf8121a";</div><div class='add'>+		reg = &lt;0x8&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			reg_ldo1: ldo1 {</div><div class='add'>+				regulator-min-microvolt = &lt;1500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_ldo2: ldo2 {</div><div class='add'>+				regulator-min-microvolt = &lt;1500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_ldo3: ldo3 {</div><div class='add'>+				regulator-min-microvolt = &lt;1500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_ldo4: ldo4 {</div><div class='add'>+				regulator-min-microvolt = &lt;1500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_buck1: buck1 {</div><div class='add'>+				regulator-min-microvolt = &lt;400000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_buck2: buck2 {</div><div class='add'>+				regulator-min-microvolt = &lt;400000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_buck3: buck3 {</div><div class='add'>+				regulator-min-microvolt = &lt;400000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_buck4: buck4 {</div><div class='add'>+				regulator-min-microvolt = &lt;400000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_buck5: buck5 {</div><div class='add'>+				regulator-min-microvolt = &lt;400000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_buck6: buck6 {</div><div class='add'>+				regulator-min-microvolt = &lt;400000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_buck7: buck7 {</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vsnvs: vsnvs {</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	i2c-mux@70 {</div><div class='add'>+		compatible = "nxp,pca9540";</div><div class='add'>+		reg = &lt;0x70&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		i2c@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			rtc@68 {</div><div class='add'>+				compatible = "microcrystal,rv4162";</div><div class='add'>+				reg = &lt;0x68&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;pinctrl_i2c3a_rv4162&gt;;</div><div class='add'>+				interrupts-extended = &lt;&amp;gpio4 22 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+				wakeup-source;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	wm8960: codec@1a {</div><div class='add'>+		compatible = "wlf,wm8960";</div><div class='add'>+		reg = &lt;0x1a&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX8MM_CLK_SAI1_ROOT&gt;;</div><div class='add'>+		clock-names = "mclk";</div><div class='add'>+		wlf,shared-lrclk;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm2 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_PWM2&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL1_40M&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;40000000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* BT */</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* console */</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* J15 */</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* J9 */</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* eMMC */</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	sdhci-caps-mask = &lt;0x80000000 0x0&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1_200mhz&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_vref_3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_vref_1v8&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* sdcard */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_ldo2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* wlan */</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	sdhci-caps-mask = &lt;0x2 0x0&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_wlan_vmmc&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_vref_1v8&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB OTG port */</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	over-current-active-low;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usbotg1&gt;;</div><div class='add'>+	power-active-high;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB Host port */</div><div class='add'>+&amp;usbotg2 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	over-current-active-low;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usbotg2&gt;;</div><div class='add'>+	power-active-high;</div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: having USB2 enabled hangs the boot just after:</div><div class='add'>+	 *[    1.655941] ci_hdrc ci_hdrc.1: EHCI Host Controller</div><div class='add'>+	 *[    1.660880] ci_hdrc ci_hdrc.1: new USB bus registered, assigned bus number 2</div><div class='add'>+	 *[    1.681505] ci_hdrc ci_hdrc.1: USB 2.0 started, EHCI 1.00</div><div class='add'>+	 *[    1.687730] hub 2-0:1.0: USB hub found</div><div class='add'>+	 *[    1.691528] hub 2-0:1.0: 1 port detected</div><div class='add'>+	 */</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hog&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi2: ecspi2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13	0x140</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO	0x19</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0x19</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec1: fec1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3</div><div class='add'>+			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f</div><div class='add'>+			MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16		0x159</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexspi: flexspigrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK	0x1c2</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B	0x82</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0	0x82</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1	0x82</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2	0x82</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3	0x82</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_hog: hoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x09</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x09</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4: i2c4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3a_rv4162: i2c3a-rv4162grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1c0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm1: pwm1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x16</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm2: pwm2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x16</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm3: pwm3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x16</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm4: pwm4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI3_MCLK_PWM4_OUT 0x16</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_wlan_vmmc: reg-wlan-vmmcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x16</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai1: sai1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* wm8960 */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK	0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC	0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK	0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0	0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0	0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai2: sai2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* Bluetooth PCM */</div><div class='add'>+			MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC	0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK	0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0	0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0	0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sound_wm8960: sound-wm8960grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10	0x80</div><div class='add'>+			MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28	0x80</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140</div><div class='add'>+			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140</div><div class='add'>+			MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140</div><div class='add'>+			MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140</div><div class='add'>+			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: uart3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart4: uart4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140</div><div class='add'>+			MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usbotg1: usbotg1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR	0x16</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC	0x156</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usbotg2: usbotg2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO14_USB2_OTG_PWR	0x16</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC	0x15</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x190</div><div class='add'>+			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10	0x141</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x194</div><div class='add'>+			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7	0x1d4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x196</div><div class='add'>+			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7	0x1d6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12	0x1c4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x190</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K	0x03</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x194</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x196</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-overdrive.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-overdrive.dtsi<br/>new file mode 100644<br/>index 000000000000..b31436b5e9b7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-overdrive.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-overdrive.dtsi</a></div><div class='hunk'>@@ -0,0 +1,29 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+</div><div class='add'>+&amp;gpu_2d {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_GPU2D_CORE&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MM_GPU_PLL_OUT&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_GPU_PLL_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;0&gt;, &lt;1000000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu_3d {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_GPU3D_CORE&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MM_GPU_PLL_OUT&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_GPU_PLL_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;0&gt;, &lt;1000000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;vpu_blk_ctrl {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_VPU_G1&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MM_CLK_VPU_G2&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MM_CLK_VPU_H1&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MM_VPU_PLL_OUT&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL3_OUT&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MM_VPU_PLL_OUT&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MM_SYS_PLL3_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;750000000&gt;,</div><div class='add'>+			       &lt;700000000&gt;,</div><div class='add'>+			       &lt;750000000&gt;,</div><div class='add'>+			       &lt;700000000&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phg.dts b/arch/arm64/boot/dts/freescale/imx8mm-phg.dts<br/>new file mode 100644<br/>index 000000000000..a134b1833649<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-phg.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-phg.dts</a></div><div class='hunk'>@@ -0,0 +1,358 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Fabio Estevam &lt;festevam@denx.de&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mm-tqma8mqml.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Cloos i.MX8MM PHG board";</div><div class='add'>+	compatible = "cloos,imx8mm-phg", "tq,imx8mm-tqma8mqml", "fsl,imx8mm";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		mmc0 = &amp;usdhc3;</div><div class='add'>+		mmc1 = &amp;usdhc2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	beeper {</div><div class='add'>+		compatible = "gpio-beeper";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_beeper&gt;;</div><div class='add'>+		gpios = &lt;&amp;gpio1 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_led&gt;;</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			label = "status1";</div><div class='add'>+			gpios = &lt;&amp;gpio1 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			label = "status2";</div><div class='add'>+			gpios = &lt;&amp;gpio1 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-2 {</div><div class='add'>+			label = "status3";</div><div class='add'>+			gpios = &lt;&amp;gpio1 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-3 {</div><div class='add'>+			label = "run";</div><div class='add'>+			gpios = &lt;&amp;gpio1 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-4 {</div><div class='add'>+			label = "powerled";</div><div class='add'>+			gpios = &lt;&amp;gpio1 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb_otg_vbus: regulator-usb-otg-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_otg_vbus_ctrl&gt;;</div><div class='add'>+		regulator-name = "usb_otg_vbus";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio2 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-vmmc {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usdhc2_vmmc&gt;;</div><div class='add'>+		regulator-name = "VSD_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio2 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		startup-delay-us = &lt;100&gt;;</div><div class='add'>+		off-on-delay-us = &lt;12000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	panel {</div><div class='add'>+		compatible = "auo,g084sn05", "panel-lvds";</div><div class='add'>+		width-mm = &lt;170&gt;;</div><div class='add'>+		height-mm = &lt;28&gt;;</div><div class='add'>+		data-mapping = "jeida-18";</div><div class='add'>+</div><div class='add'>+		panel-timing {</div><div class='add'>+			clock-frequency = &lt;49500000&gt;;</div><div class='add'>+			hactive = &lt;800&gt;;</div><div class='add'>+			hback-porch = &lt;48&gt;;</div><div class='add'>+			hfront-porch = &lt;312&gt;;</div><div class='add'>+			hsync-len = &lt;40&gt;;</div><div class='add'>+			vactive = &lt;600&gt;;</div><div class='add'>+			vback-porch = &lt;19&gt;;</div><div class='add'>+			vfront-porch = &lt;61&gt;;</div><div class='add'>+			vsync-len = &lt;20&gt;;</div><div class='add'>+			hsync-active = &lt;0&gt;;</div><div class='add'>+			vsync-active = &lt;0&gt;;</div><div class='add'>+			de-active = &lt;1&gt;;</div><div class='add'>+			pixelclk-active = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			panel_out_bridge: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;bridge_out_panel&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* QSPI is not populated on the SoM */</div><div class='add'>+&amp;flexspi {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi1&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec1&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	fsl,magic-packet;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bridge@2c {</div><div class='add'>+		compatible = "ti,sn65dsi83";</div><div class='add'>+		reg = &lt;0x2c&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;gpio2 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_dsi_bridge&gt;;</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				bridge_in_dsi: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;dsi_out_bridge&gt;;</div><div class='add'>+					data-lanes = &lt;1 2 3 4&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@2 {</div><div class='add'>+				reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+				bridge_out_panel: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;panel_out_bridge&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_dsi {</div><div class='add'>+	samsung,esc-clock-frequency = &lt;10000000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			dsi_out_bridge: endpoint {</div><div class='add'>+				data-lanes = &lt;1 2&gt;;</div><div class='add'>+				lane-polarities = &lt;1 0 0 0 0&gt;;</div><div class='add'>+				remote-endpoint = &lt;&amp;bridge_in_dsi&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbphynop1 {</div><div class='add'>+	power-domains = &lt;&amp;pgc_otg1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbphynop2 {</div><div class='add'>+	power-domains = &lt;&amp;pgc_otg2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usb_otg_vbus&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg2 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_USDHC2&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL1_400M&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+	no-mmc;</div><div class='add'>+	no-sdio;</div><div class='add'>+	sd-uhs-sdr104;</div><div class='add'>+	sd-uhs-ddr50;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_beeper: beepergrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0		0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_dsi_bridge: dsibridgeggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3		0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi1: ecspi1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO		0x82</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI		0x82</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK		0x82</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9		0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec1: fec1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC		0x40000002</div><div class='add'>+			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x40000002</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x14</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x14</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x14</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x14</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x90</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x90</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x90</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x90</div><div class='add'>+			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x14</div><div class='add'>+			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x90</div><div class='add'>+			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x90</div><div class='add'>+			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x14</div><div class='add'>+			MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22		0x10</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio_led: gpioledgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x19</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x19</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6		0x19</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x19</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1		0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_otg_vbus_ctrl: otgvbusctrlgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2		0x119</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX		0x140</div><div class='add'>+			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX		0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x1c4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10-etml1010g3dra.dtso b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10-etml1010g3dra.dtso<br/>new file mode 100644<br/>index 000000000000..193fa9dc34d4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10-etml1010g3dra.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10-etml1010g3dra.dtso</a></div><div class='hunk'>@@ -0,0 +1,44 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2025 PHYTEC Messtechnik GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include "imx8mm-phyboard-polis-peb-av-10.dtsi"</div><div class='add'>+</div><div class='add'>+&amp;backlight {</div><div class='add'>+	brightness-levels = &lt;0 4 8 16 32 64 128 255&gt;;</div><div class='add'>+	default-brightness-level = &lt;6&gt;;</div><div class='add'>+	enable-gpios = &lt;&amp;gpio5 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	pwms = &lt;&amp;pwm4 0 50000 0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;bridge_out {</div><div class='add'>+	ti,lvds-vod-swing-clock-microvolt = &lt;200000 600000&gt;;</div><div class='add'>+	ti,lvds-vod-swing-data-microvolt = &lt;200000 600000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_dsi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;panel {</div><div class='add'>+	compatible = "edt,etml1010g3dra";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm4 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sn65dsi83 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10-ph128800t006.dtso b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10-ph128800t006.dtso<br/>new file mode 100644<br/>index 000000000000..fd819bd563b8<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10-ph128800t006.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10-ph128800t006.dtso</a></div><div class='hunk'>@@ -0,0 +1,44 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2025 PHYTEC Messtechnik GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include "imx8mm-phyboard-polis-peb-av-10.dtsi"</div><div class='add'>+</div><div class='add'>+&amp;backlight {</div><div class='add'>+	brightness-levels = &lt;0 4 8 16 32 64 128 255&gt;;</div><div class='add'>+	default-brightness-level = &lt;6&gt;;</div><div class='add'>+	enable-gpios = &lt;&amp;gpio5 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	pwms = &lt;&amp;pwm4 0 50000 0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;bridge_out {</div><div class='add'>+	ti,lvds-vod-swing-clock-microvolt = &lt;200000 600000&gt;;</div><div class='add'>+	ti,lvds-vod-swing-data-microvolt = &lt;200000 600000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_dsi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;panel {</div><div class='add'>+	compatible = "powertip,ph128800t006-zhc01";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm4 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sn65dsi83 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10.dtsi<br/>new file mode 100644<br/>index 000000000000..bd1f255e15ea<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10.dtsi</a></div><div class='hunk'>@@ -0,0 +1,189 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2025 PHYTEC Messtechnik GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/imx8mm-clock.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include "imx8mm-pinfunc.h"</div><div class='add'>+</div><div class='add'>+&amp;{/} {</div><div class='add'>+	backlight: backlight {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_lcd&gt;;</div><div class='add'>+		power-supply = &lt;&amp;reg_vdd_3v3_s&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	panel: panel {</div><div class='add'>+		backlight = &lt;&amp;backlight&gt;;</div><div class='add'>+		power-supply = &lt;&amp;reg_vcc_3v3&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			panel_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;bridge_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_sound_1v8: regulator-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCC_1V8_Audio";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_sound_3v3: regulator-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCC_3V3_Analog";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-peb-av-10 {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,name = "snd-peb-av-10";</div><div class='add'>+		simple-audio-card,format = "i2s";</div><div class='add'>+		simple-audio-card,bitclock-master = &lt;&amp;dailink_master&gt;;</div><div class='add'>+		simple-audio-card,frame-master = &lt;&amp;dailink_master&gt;;</div><div class='add'>+		simple-audio-card,mclk-fs = &lt;32&gt;;</div><div class='add'>+		simple-audio-card,widgets =</div><div class='add'>+			"Line", "Line In",</div><div class='add'>+			"Speaker", "Speaker",</div><div class='add'>+			"Microphone", "Microphone Jack",</div><div class='add'>+			"Headphone", "Headphone Jack";</div><div class='add'>+		simple-audio-card,routing =</div><div class='add'>+			"Speaker", "SPOP",</div><div class='add'>+			"Speaker", "SPOM",</div><div class='add'>+			"Headphone Jack", "HPLOUT",</div><div class='add'>+			"Headphone Jack", "HPROUT",</div><div class='add'>+			"LINE1L", "Line In",</div><div class='add'>+			"LINE1R", "Line In",</div><div class='add'>+			"MIC3R", "Microphone Jack",</div><div class='add'>+			"Microphone Jack", "Mic Bias";</div><div class='add'>+</div><div class='add'>+		simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;sai5&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dailink_master: simple-audio-card,codec {</div><div class='add'>+			sound-dai = &lt;&amp;codec&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MM_CLK_SAI5&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;bridge_out {</div><div class='add'>+	remote-endpoint = &lt;&amp;panel_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c3_gpio&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	codec: codec@18 {</div><div class='add'>+		compatible = "ti,tlv320aic3007";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_tlv320&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		reg = &lt;0x18&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio4 28 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		ai3x-gpio-func = &lt;0xd 0x0&gt;;</div><div class='add'>+		ai3x-micbias-vg = &lt;2&gt;;</div><div class='add'>+		AVDD-supply = &lt;&amp;reg_sound_3v3&gt;;</div><div class='add'>+		IOVDD-supply = &lt;&amp;reg_sound_3v3&gt;;</div><div class='add'>+		DRVDD-supply = &lt;&amp;reg_sound_3v3&gt;;</div><div class='add'>+		DVDD-supply = &lt;&amp;reg_sound_1v8&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@57 {</div><div class='add'>+		compatible = "atmel,24c32";</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		reg = &lt;0x57&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_vdd_3v3_s&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@5f {</div><div class='add'>+		compatible = "atmel,24c32";</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		reg = &lt;0x5f&gt;;</div><div class='add'>+		size = &lt;32&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_vdd_3v3_s&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm4&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai5 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_SAI5&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_AUDIO_PLL2_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;11289600&gt;;</div><div class='add'>+	clocks = &lt;&amp;clk IMX8MM_CLK_SAI5_IPG&gt;, &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;,</div><div class='add'>+		&lt;&amp;clk IMX8MM_CLK_SAI5_ROOT&gt;, &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;,</div><div class='add'>+		&lt;&amp;clk IMX8MM_CLK_DUMMY&gt;, &lt;&amp;clk IMX8MM_AUDIO_PLL1_OUT&gt;,</div><div class='add'>+		&lt;&amp;clk IMX8MM_AUDIO_PLL2_OUT&gt;;</div><div class='add'>+	clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k",</div><div class='add'>+			"pll11k";</div><div class='add'>+	fsl,sai-mclk-direction-output;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai5&gt;;</div><div class='add'>+	#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL          0x400001c2</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA          0x400001c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3_gpio: i2c3gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18        0x1e2</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19        0x1e2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+	pinctrl_lcd: lcd0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1		0x12</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm4: pwm4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI3_MCLK_PWM4_OUT		0x12</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai5: sai5grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK        0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0    0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC     0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK     0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0    0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_tlv320: tlv320grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28       0x116</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20        0x16</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10.dtso b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10.dtso<br/>new file mode 100644<br/>index 000000000000..28e8589f9f95<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10.dtso</a></div><div class='hunk'>@@ -0,0 +1,9 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2025 PHYTEC Messtechnik GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+#include "imx8mm-phyboard-polis-peb-av-10.dtsi"</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-eval-01.dtso b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-eval-01.dtso<br/>new file mode 100644<br/>index 000000000000..1059c26990fe<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-eval-01.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-eval-01.dtso</a></div><div class='hunk'>@@ -0,0 +1,71 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2025 PHYTEC Messtechnik GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/linux-event-codes.h&gt;</div><div class='add'>+#include "imx8mm-pinfunc.h"</div><div class='add'>+</div><div class='add'>+&amp;{/} {</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_keys&gt;;</div><div class='add'>+</div><div class='add'>+		button-0 {</div><div class='add'>+			label = "home";</div><div class='add'>+			linux,code = &lt;KEY_HOME&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio4 17 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-1 {</div><div class='add'>+			label = "menu";</div><div class='add'>+			linux,code = &lt;KEY_MENU&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio5 29 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	user-leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_user_leds&gt;;</div><div class='add'>+</div><div class='add'>+		user-led1 {</div><div class='add'>+			gpios = &lt;&amp;gpio4 14 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "on";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		user-led2 {</div><div class='add'>+			gpios = &lt;&amp;gpio4 15 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "on";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		user-led3 {</div><div class='add'>+			gpios = &lt;&amp;gpio5 28 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "on";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_gpio_keys: gpio_keysgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17	0x16</div><div class='add'>+			MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29	0x16</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_user_leds: user_ledsgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15	0x16</div><div class='add'>+			MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28	0x16</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14	0x16</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts<br/>new file mode 100644<br/>index 000000000000..6043e7d16306<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts</a></div><div class='hunk'>@@ -0,0 +1,526 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2022 PHYTEC Messtechnik GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/phy/phy-imx8-pcie.h&gt;</div><div class='add'>+#include "imx8mm-phycore-som.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "PHYTEC phyBOARD-Polis-i.MX8MM RDK";</div><div class='add'>+	compatible = "phytec,imx8mm-phyboard-polis-rdk",</div><div class='add'>+		     "phytec,imx8mm-phycore-som", "fsl,imx8mm";</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart3;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bt_osc_32k: bt-lp-clock {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		clock-frequency = &lt;32768&gt;;</div><div class='add'>+		clock-output-names = "bt_osc_32k";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	can_osc_40m: can-clock {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		clock-frequency = &lt;40000000&gt;;</div><div class='add'>+		clock-output-names = "can_osc_40m";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fan {</div><div class='add'>+		compatible = "gpio-fan";</div><div class='add'>+		gpios = &lt;&amp;gpio4 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		gpio-fan,speed-map = &lt;0     0</div><div class='add'>+				      13000 1&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_fan&gt;;</div><div class='add'>+		#cooling-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_leds&gt;;</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			function = LED_FUNCTION_DISK;</div><div class='add'>+			gpios = &lt;&amp;gpio1 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "mmc2";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			function = LED_FUNCTION_DISK;</div><div class='add'>+			gpios = &lt;&amp;gpio1 15 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "mmc1";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-2 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_CPU;</div><div class='add'>+			gpios = &lt;&amp;gpio1 14 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usdhc1_pwrseq: pwr-seq {</div><div class='add'>+		compatible = "mmc-pwrseq-simple";</div><div class='add'>+		post-power-on-delay-ms = &lt;100&gt;;</div><div class='add'>+		power-off-delay-us = &lt;60&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio2 7 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_can_en: regulator-can-en {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		gpio = &lt;&amp;gpio1 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_can_en&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "CAN_EN";</div><div class='add'>+		startup-delay-us = &lt;20&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb_otg1_vbus: regulator-usb-otg1 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		gpio = &lt;&amp;gpio1 12 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usbotg1pwrgrp&gt;;</div><div class='add'>+		regulator-name = "usb_otg1_vbus";</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		gpio = &lt;&amp;gpio2 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		off-on-delay-us = &lt;20000&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usdhc2_vmmc&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "VSD_3V3";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc_3v3: regulator-vcc-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "VCC_3V3";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SPI - CAN MCP251XFD */</div><div class='add'>+&amp;ecspi1 {</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	can0: can@0 {</div><div class='add'>+		compatible = "microchip,mcp251xfd";</div><div class='add'>+		clocks = &lt;&amp;can_osc_40m&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;8 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_can_int&gt;;</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;20000000&gt;;</div><div class='add'>+		xceiver-supply = &lt;&amp;reg_can_en&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* TPM */</div><div class='add'>+&amp;ecspi2 {</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 13 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi2&gt;;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	tpm: tpm@0 {</div><div class='add'>+		compatible = "infineon,slb9670", "tcg,tpm_tis-spi";</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio2&gt;;</div><div class='add'>+		interrupts = &lt;11 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_tpm&gt;;</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;43000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	gpio-line-names = "", "LED_RED", "WDOG_INT", "X_RTC_INT",</div><div class='add'>+		"", "", "", "RESET_ETHPHY",</div><div class='add'>+		"CAN_nINT", "CAN_EN", "nENABLE_FLATLINK", "",</div><div class='add'>+		"USB_OTG_VBUS_EN", "", "LED_GREEN", "LED_BLUE";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio2 {</div><div class='add'>+	gpio-line-names = "", "", "", "",</div><div class='add'>+		"", "", "BT_REG_ON", "WL_REG_ON",</div><div class='add'>+		"BT_DEV_WAKE", "BT_HOST_WAKE", "", "",</div><div class='add'>+		"X_SD2_CD_B", "", "", "",</div><div class='add'>+		"", "", "", "SD2_RESET_B";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	gpio-line-names = "", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"FAN", "miniPCIe_nPERST", "", "",</div><div class='add'>+		"COEX1", "COEX2";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio5 {</div><div class='add'>+	gpio-line-names = "", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "ECSPI1_SS0";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c4&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c4_gpio&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* PCIe */</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_PCIE1_AUX&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MM_CLK_PCIE1_CTRL&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL2_50M&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MM_SYS_PLL2_250M&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;10000000&gt;, &lt;250000000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie&gt;;</div><div class='add'>+	reset-gpio = &lt;&amp;gpio4 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	clocks = &lt;&amp;clk IMX8MM_CLK_PCIE1_PHY&gt;;</div><div class='add'>+	fsl,clkreq-unsupported;</div><div class='add'>+	fsl,refclk-pad-mode = &lt;IMX8_PCIE_REFCLK_PAD_OUTPUT&gt;;</div><div class='add'>+	fsl,tx-deemph-gen1 = &lt;0x2d&gt;;</div><div class='add'>+	fsl,tx-deemph-gen2 = &lt;0xf&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* RTC */</div><div class='add'>+&amp;rv3028 {</div><div class='add'>+	interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+	interrupts = &lt;3 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_rtc&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	aux-voltage-chargeable = &lt;1&gt;;</div><div class='add'>+	trickle-resistor-ohms = &lt;3000&gt;;</div><div class='add'>+	wakeup-source;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;snvs_pwrkey {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* UART - RS232/RS485 */</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_UART1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL1_80M&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* UART - Sterling-LWB Bluetooth */</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_UART2&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL1_80M&gt;;</div><div class='add'>+	fsl,dte-mode;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2_bt&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "brcm,bcm43438-bt";</div><div class='add'>+		clocks = &lt;&amp;bt_osc_32k&gt;;</div><div class='add'>+		clock-names = "lpo";</div><div class='add'>+		device-wakeup-gpios = &lt;&amp;gpio2 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		interrupt-names = "host-wakeup";</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio2&gt;;</div><div class='add'>+		interrupts = &lt;9 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		max-speed = &lt;2000000&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_bt&gt;;</div><div class='add'>+		shutdown-gpios = &lt;&amp;gpio2 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		vbat-supply = &lt;&amp;reg_vcc_3v3&gt;;</div><div class='add'>+		vddio-supply = &lt;&amp;reg_vcc_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* UART - console */</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB */</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	adp-disable;</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	over-current-active-low;</div><div class='add'>+	samsung,picophy-pre-emp-curr-control = &lt;3&gt;;</div><div class='add'>+	samsung,picophy-dc-vol-level-adjust = &lt;7&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usbotg1&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	srp-disable;</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usb_otg1_vbus&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg2 {</div><div class='add'>+	disable-over-current;</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	samsung,picophy-pre-emp-curr-control = &lt;3&gt;;</div><div class='add'>+	samsung,picophy-dc-vol-level-adjust = &lt;7&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SDIO - Sterling-LWB Wifi */</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_USDHC1&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;200000000&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	mmc-pwrseq = &lt;&amp;usdhc1_pwrseq&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	no-1-8-v;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;, &lt;&amp;pinctrl_wlan&gt;;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	brcmf: wifi@1 {</div><div class='add'>+		compatible = "brcm,bcm4329-fmac";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SD-Card */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_USDHC2&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;200000000&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_nvcc_sd2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_bt: btgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6	0x00</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8	0x00</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_can_en: can-engrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9	0x00</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_can_int: can-intgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8	0x00</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi1: ecspi1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO	0x80</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI	0x80</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK	0x80</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9	0x00</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi2: ecspi2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO    0x80</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI    0x80</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK    0x80</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13      0x00</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fan: fan0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8	0x16</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4: i2c4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL		0x400001c2</div><div class='add'>+			MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA		0x400001c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4_gpio: i2c4gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20        0x1e2</div><div class='add'>+			MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21        0x1e2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_leds: leds1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1	0x16</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14	0x16</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x16</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie: pciegrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9	0x00</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12	0x12</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19	0x12</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x40</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_rtc: rtcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x1c0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_tpm: tpmgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11      0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX	0x00</div><div class='add'>+			MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B	0x00</div><div class='add'>+			MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX	0x00</div><div class='add'>+			MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B	0x00</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2_bt: uart2btgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B	0x00</div><div class='add'>+			MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B	0x00</div><div class='add'>+			MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX	0x00</div><div class='add'>+			MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX	0x00</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: uart3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX	0x140</div><div class='add'>+			MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usbotg1pwrgrp: usbotg1pwrgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x00</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usbotg1: usbotg1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC	0x00</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x182</div><div class='add'>+			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0xc6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0xc6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0xc6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0xc6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0xc6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12	0x40</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x192</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d2</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d2</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d2</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d2</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wlan: wlangrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7	0x00</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phycore-no-eth.dtso b/arch/arm64/boot/dts/freescale/imx8mm-phycore-no-eth.dtso<br/>new file mode 100644<br/>index 000000000000..0fb4b6da6c10<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-phycore-no-eth.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-phycore-no-eth.dtso</a></div><div class='hunk'>@@ -0,0 +1,12 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2025 PHYTEC Messtechnik GmbH</div><div class='add'>+ * Author: Teresa Remmet &lt;t.remmet@phytec.de&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+&amp;ethphy0 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phycore-no-spiflash.dtso b/arch/arm64/boot/dts/freescale/imx8mm-phycore-no-spiflash.dtso<br/>new file mode 100644<br/>index 000000000000..7bfc366c1689<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-phycore-no-spiflash.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-phycore-no-spiflash.dtso</a></div><div class='hunk'>@@ -0,0 +1,16 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2025 PHYTEC Messtechnik GmbH</div><div class='add'>+ * Author: Teresa Remmet &lt;t.remmet@phytec.de&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+&amp;flexspi {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;som_flash {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phycore-rpmsg.dtso b/arch/arm64/boot/dts/freescale/imx8mm-phycore-rpmsg.dtso<br/>new file mode 100644<br/>index 000000000000..43d5905f3d72<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-phycore-rpmsg.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-phycore-rpmsg.dtso</a></div><div class='hunk'>@@ -0,0 +1,58 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2025 PHYTEC Messtechnik GmbH</div><div class='add'>+ * Author: Dominik Haller &lt;d.haller@phytec.de&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/imx8mm-clock.h&gt;</div><div class='add'>+</div><div class='add'>+&amp;{/} {</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		m4_reserved: m4@80000000 {</div><div class='add'>+			reg = &lt;0 0x80000000 0 0x1000000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev0vring0: vdev0vring0@b8000000 {</div><div class='add'>+			reg = &lt;0 0xb8000000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev0vring1: vdev0vring1@b8008000 {</div><div class='add'>+			reg = &lt;0 0xb8008000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rsc_table: rsc_table@b80ff000 {</div><div class='add'>+			reg = &lt;0 0xb80ff000 0 0x1000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdevbuffer: vdevbuffer@b8400000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0xb8400000 0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	core-m4 {</div><div class='add'>+		compatible = "fsl,imx8mm-cm4";</div><div class='add'>+		clocks = &lt;&amp;clk IMX8MM_CLK_M4_DIV&gt;;</div><div class='add'>+		mboxes = &lt;&amp;mu 0 1</div><div class='add'>+			&amp;mu 1 1</div><div class='add'>+			&amp;mu 3 1&gt;;</div><div class='add'>+		mbox-names = "tx", "rx", "rxdb";</div><div class='add'>+		memory-region = &lt;&amp;vdevbuffer&gt;, &lt;&amp;vdev0vring0&gt;, &lt;&amp;vdev0vring1&gt;, &lt;&amp;rsc_table&gt;;</div><div class='add'>+		syscon = &lt;&amp;src&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi<br/>new file mode 100644<br/>index 000000000000..3d66c6701342<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi</a></div><div class='hunk'>@@ -0,0 +1,459 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2022 PHYTEC Messtechnik GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "imx8mm.dtsi"</div><div class='add'>+#include &lt;dt-bindings/net/ti-dp83867.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "PHYTEC phyCORE-i.MX8MM";</div><div class='add'>+	compatible = "phytec,imx8mm-phycore-som", "fsl,imx8mm";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		rtc0 = &amp;rv3028;</div><div class='add'>+		rtc1 = &amp;snvs_rtc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x40000000 0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vdd_3v3_s: regulator-vdd-3v3-s {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "VDD_3V3_S";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_vdd_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_vdd_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_vdd_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_vdd_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ddrc {</div><div class='add'>+	operating-points-v2 = &lt;&amp;ddrc_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+	ddrc_opp_table: opp-table {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		opp-25000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;25000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-100000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;100000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-750000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;750000000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Ethernet */</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@0 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			enet-phy-lane-no-swap;</div><div class='add'>+			ti,clk-output-sel = &lt;DP83867_CLK_O_SEL_OFF&gt;;</div><div class='add'>+			ti,fifo-depth = &lt;DP83867_PHYCR_FIFO_DEPTH_4_B_NIB&gt;;</div><div class='add'>+			ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_2_00_NS&gt;;</div><div class='add'>+			ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_2_00_NS&gt;;</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio1 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			reset-assert-us = &lt;1000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;1000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SPI Flash */</div><div class='add'>+&amp;flexspi {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexspi0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	som_flash: flash@0 {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;80000000&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	gpio-line-names = "", "", "WDOG_INT", "X_RTC_INT",</div><div class='add'>+		"", "", "", "RESET_ETHPHY",</div><div class='add'>+		"", "", "nENABLE_FLATLINK";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* I2C1 */</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default","gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c1_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pmic@8 {</div><div class='add'>+		compatible = "nxp,pf8121a";</div><div class='add'>+		reg = &lt;0x08&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			reg_nvcc_sd1: ldo1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "NVCC_SD1 (LDO1)";</div><div class='add'>+</div><div class='add'>+				regulator-state-mem {</div><div class='add'>+					regulator-off-in-suspend;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_nvcc_sd2: ldo2 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "NVCC_SD2 (LDO2)";</div><div class='add'>+</div><div class='add'>+				regulator-state-mem {</div><div class='add'>+					regulator-off-in-suspend;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vcc_enet: ldo3 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;2500000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;2500000&gt;;</div><div class='add'>+				regulator-name = "VCC_ENET_2V5 (LDO3)";</div><div class='add'>+</div><div class='add'>+				regulator-state-mem {</div><div class='add'>+					regulator-on-in-suspend;</div><div class='add'>+					regulator-suspend-max-microvolt = &lt;2500000&gt;;</div><div class='add'>+					regulator-suspend-min-microvolt = &lt;2500000&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vdda_1v8: ldo4 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1500000&gt;;</div><div class='add'>+				regulator-name = "VDDA_1V8 (LDO4)";</div><div class='add'>+</div><div class='add'>+				regulator-state-mem {</div><div class='add'>+					regulator-on-in-suspend;</div><div class='add'>+					regulator-suspend-min-microvolt = &lt;1500000&gt;;</div><div class='add'>+					regulator-suspend-max-microvolt = &lt;1500000&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_soc_vdda_phy: buck1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;400000&gt;;</div><div class='add'>+				regulator-name = "VDD_SOC_VDDA_PHY_0P8 (BUCK1)";</div><div class='add'>+</div><div class='add'>+				regulator-state-mem {</div><div class='add'>+					regulator-on-in-suspend;</div><div class='add'>+					regulator-suspend-min-microvolt = &lt;400000&gt;;</div><div class='add'>+					regulator-suspend-max-microvolt = &lt;400000&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vdd_gpu_dram: buck2 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1000000&gt;;</div><div class='add'>+				regulator-name = "VDD_GPU_DRAM (BUCK2)";</div><div class='add'>+</div><div class='add'>+				regulator-state-mem {</div><div class='add'>+					regulator-on-in-suspend;</div><div class='add'>+					regulator-suspend-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+					regulator-suspend-min-microvolt = &lt;1000000&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vdd_vpu: buck3 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;400000&gt;;</div><div class='add'>+				regulator-name = "VDD_VPU (BUCK3)";</div><div class='add'>+</div><div class='add'>+				regulator-state-mem {</div><div class='add'>+					regulator-off-in-suspend;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vdd_mipi: buck4 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1050000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-name = "VDD_MIPI_0P9 (BUCK4)";</div><div class='add'>+</div><div class='add'>+				regulator-state-mem {</div><div class='add'>+					regulator-off-in-suspend;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vdd_arm: buck5 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1050000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;400000&gt;;</div><div class='add'>+				regulator-name = "VDD_ARM (BUCK5)";</div><div class='add'>+</div><div class='add'>+				regulator-state-mem {</div><div class='add'>+					regulator-off-in-suspend;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vdd_1v8: buck6 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "VDD_1V8 (BUCK6)";</div><div class='add'>+</div><div class='add'>+				regulator-state-mem {</div><div class='add'>+					regulator-on-in-suspend;</div><div class='add'>+					regulator-suspend-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+					regulator-suspend-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_nvcc_dram: buck7 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-name = "NVCC_DRAM_1P1V (BUCK7)";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vsnvs: vsnvs {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "NVCC_SNVS_1P8 (VSNVS)";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sn65dsi83: bridge@2d {</div><div class='add'>+		compatible = "ti,sn65dsi83";</div><div class='add'>+		enable-gpios = &lt;&amp;gpio1 10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_sn65dsi83&gt;;</div><div class='add'>+		reg = &lt;0x2d&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_vdd_1v8&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				bridge_in: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;mipi_dsi_out&gt;;</div><div class='add'>+					data-lanes = &lt;1 2 3 4&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@2 {</div><div class='add'>+				reg = &lt;2&gt;;</div><div class='add'>+				bridge_out: endpoint {};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* EEPROM */</div><div class='add'>+	eeprom@51 {</div><div class='add'>+		compatible = "atmel,24c32";</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_vdd_3v3_s&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* RTC */</div><div class='add'>+	rv3028: rtc@52 {</div><div class='add'>+		compatible = "microcrystal,rv3028";</div><div class='add'>+		reg = &lt;0x52&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_dsi {</div><div class='add'>+	samsung,esc-clock-frequency = &lt;10000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_dsi_out {</div><div class='add'>+	remote-endpoint = &lt;&amp;bridge_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* eMMC */</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_USDHC3_ROOT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	keep-power-in-suspend;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Watchdog */</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_fec1: fec1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x2</div><div class='add'>+			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x2</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x90</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x90</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x90</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x90</div><div class='add'>+			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x90</div><div class='add'>+			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x90</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x16</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x16</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x12</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x12</div><div class='add'>+			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x12</div><div class='add'>+			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x12</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x10</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexspi0: flexspi0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK		0x1c2</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B		0x82</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0		0x82</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1		0x82</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2		0x82</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3		0x82</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA			0x400001c0</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL			0x400001c0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1_gpio: i2c1gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15		0x1e0</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14		0x1e0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sn65dsi83: sn65dsi83grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x190</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x190</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x194</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x194</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x196</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x196</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0x26</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l-rs232-rs232.dtso b/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l-rs232-rs232.dtso<br/>new file mode 100644<br/>index 000000000000..78f4e8d5814d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l-rs232-rs232.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l-rs232-rs232.dtso</a></div><div class='hunk'>@@ -0,0 +1,67 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2021 PHYTEC Messtechnik GmbH</div><div class='add'>+ * Author: Jens Lang &lt;j.lang@phytec.de&gt;</div><div class='add'>+ *</div><div class='add'>+ * Tauri-L 2 x RS232:</div><div class='add'>+ *  - GPIO3_20 uart4_rs485_en needs to be driven low (inactive)</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/imx8mm-clock.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include "imx8mm-pinfunc.h"</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+&amp;gpio3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio3_hog&gt;;</div><div class='add'>+</div><div class='add'>+	uart4-rs485-en-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;20 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		output-low;</div><div class='add'>+		line-name = "uart4_rs485_en";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* UART2 - RS232  */</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_UART2&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL1_80M&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* UART4 - RS232  */</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart4&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_UART4&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL1_80M&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_gpio3_hog: gpio3hoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20	0x49</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x00</div><div class='add'>+			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x00</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart4: uart4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX	0x49</div><div class='add'>+			MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX	0x49</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l-rs232-rs485.dtso b/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l-rs232-rs485.dtso<br/>new file mode 100644<br/>index 000000000000..66288948bdd3<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l-rs232-rs485.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l-rs232-rs485.dtso</a></div><div class='hunk'>@@ -0,0 +1,71 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2021 PHYTEC Messtechnik GmbH</div><div class='add'>+ * Author: Jens Lang &lt;j.lang@phytec.de&gt;</div><div class='add'>+ *</div><div class='add'>+ * Tauri-L RS232 + RS485:</div><div class='add'>+ *  - GPIO3_20 uart4_rs485_en needs to be driven high (active)</div><div class='add'>+ *  - GPIO3_25 RS485_DE Driver enable</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/imx8mm-clock.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include "imx8mm-pinfunc.h"</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+&amp;gpio3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio3_hog&gt;;</div><div class='add'>+</div><div class='add'>+	uart4-rs485-en-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;20 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		output-high;</div><div class='add'>+		line-name = "uart4_rs485_en";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* UART2 - RS232  */</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_UART2&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL1_80M&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* UART4 - RS485  */</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart4&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_UART4&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL1_80M&gt;;</div><div class='add'>+	rts-gpios = &lt;&amp;gpio3 25 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	linux,rs485-enabled-at-boot-time;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_gpio3_hog: gpio3hoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20	0x49</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x00</div><div class='add'>+			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x00</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart4: uart4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX	0x49</div><div class='add'>+			MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX	0x49</div><div class='add'>+			MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25	0x49</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l-rs232-rts-cts.dtso b/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l-rs232-rts-cts.dtso<br/>new file mode 100644<br/>index 000000000000..4719f5fbad03<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l-rs232-rts-cts.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l-rs232-rts-cts.dtso</a></div><div class='hunk'>@@ -0,0 +1,35 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2023 PHYTEC Messtechnik GmbH</div><div class='add'>+ * Author: Jens Lang &lt;j.lang@phytec.de&gt;</div><div class='add'>+ *</div><div class='add'>+ * Tauri-L RS232 with RTS/CTS hardware flow control:</div><div class='add'>+ *  - UART4_TX becomes RTS</div><div class='add'>+ *  - UART4_RX becomes CTS</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/imx8mm-clock.h&gt;</div><div class='add'>+#include "imx8mm-pinfunc.h"</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_UART2&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL1_80M&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x00</div><div class='add'>+			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x00</div><div class='add'>+			MX8MM_IOMUXC_UART4_RXD_UART2_DCE_CTS_B	0x00</div><div class='add'>+			MX8MM_IOMUXC_UART4_TXD_UART2_DCE_RTS_B	0x00</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts b/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts<br/>new file mode 100644<br/>index 000000000000..2ecc8b3c67da<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts</a></div><div class='hunk'>@@ -0,0 +1,511 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2023 PHYTEC Messtechnik GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/input/linux-event-codes.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/phy/phy-imx8-pcie.h&gt;</div><div class='add'>+#include "imx8mm-phycore-som.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "PHYTEC phyGATE-Tauri-L-iMX8MM";</div><div class='add'>+	compatible = "phytec,imx8mm-phygate-tauri-l",</div><div class='add'>+		     "phytec,imx8mm-phycore-som", "fsl,imx8mm";</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart3;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	can_osc_40m: clock-can {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		clock-frequency = &lt;40000000&gt;;</div><div class='add'>+		clock-output-names = "can_osc_40m";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpiokeys&gt;;</div><div class='add'>+</div><div class='add'>+		key {</div><div class='add'>+			gpios = &lt;&amp;gpio1 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			label = "KEY-A";</div><div class='add'>+			linux,code = &lt;KEY_A&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_leds&gt;;</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio5 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "none";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-2 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_YELLOW&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio4 30 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "none";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usdhc1_pwrseq: pwr-seq {</div><div class='add'>+		compatible = "mmc-pwrseq-simple";</div><div class='add'>+		post-power-on-delay-ms = &lt;100&gt;;</div><div class='add'>+		power-off-delay-us = &lt;60&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio2 7 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb_hub_vbus: regulator-hub-otg1 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		gpio = &lt;&amp;gpio1 14 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usbhubpwr&gt;;</div><div class='add'>+		regulator-name = "usb_hub_vbus";</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb_otg1_vbus: regulator-usb-otg1 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		gpio = &lt;&amp;gpio1 12 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usbotg1pwr&gt;;</div><div class='add'>+		regulator-name = "usb_otg1_vbus";</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		gpio = &lt;&amp;gpio2 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		off-on-delay-us = &lt;20000&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usdhc2_vmmc&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "VSD_3V3";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi1 {</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 9 GPIO_ACTIVE_LOW&gt;,</div><div class='add'>+		   &lt;&amp;gpio5 13 GPIO_ACTIVE_LOW&gt;,</div><div class='add'>+		   &lt;&amp;gpio5 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi1 &amp;pinctrl_ecspi1_cs&gt;;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* CAN MCP251XFD */</div><div class='add'>+	can0: can@0 {</div><div class='add'>+		compatible = "microchip,mcp251xfd";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		clocks = &lt;&amp;can_osc_40m&gt;;</div><div class='add'>+		interrupts = &lt;8 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_can_int&gt;;</div><div class='add'>+		spi-max-frequency = &lt;10000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	tpm: tpm@1 {</div><div class='add'>+		compatible = "infineon,slb9670", "tcg,tpm_tis-spi";</div><div class='add'>+		interrupts = &lt;11 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio2&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_tpm&gt;;</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		spi-max-frequency = &lt;38000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c2_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	temp_sense0: temperature-sensor@49 {</div><div class='add'>+		compatible = "ti,tmp102";</div><div class='add'>+		reg = &lt;0x49&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;31 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_tempsense&gt;;</div><div class='add'>+		#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c3_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c4&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c4_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* PCIe */</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_PCIE1_AUX&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MM_CLK_PCIE1_PHY&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MM_CLK_PCIE1_CTRL&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL2_50M&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MM_SYS_PLL2_100M&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MM_SYS_PLL2_250M&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;10000000&gt;, &lt;100000000&gt;, &lt;250000000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie&gt;;</div><div class='add'>+	reset-gpio = &lt;&amp;gpio3 22 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	clocks = &lt;&amp;clk IMX8MM_CLK_PCIE1_PHY&gt;;</div><div class='add'>+	fsl,clkreq-unsupported;</div><div class='add'>+	fsl,refclk-pad-mode = &lt;IMX8_PCIE_REFCLK_PAD_OUTPUT&gt;;</div><div class='add'>+	fsl,tx-deemph-gen1 = &lt;0x2d&gt;;</div><div class='add'>+	fsl,tx-deemph-gen2 = &lt;0xf&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* RTC */</div><div class='add'>+&amp;rv3028 {</div><div class='add'>+	interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+	interrupts = &lt;3 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_rtc&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	aux-voltage-chargeable = &lt;1&gt;;</div><div class='add'>+	trickle-resistor-ohms = &lt;3000&gt;;</div><div class='add'>+	wakeup-source;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_UART1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL1_80M&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* UART2 - RS232 */</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_UART2&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL1_80M&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* UART - console */</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB */</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	adp-disable;</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	over-current-active-low;</div><div class='add'>+	samsung,picophy-pre-emp-curr-control = &lt;3&gt;;</div><div class='add'>+	samsung,picophy-dc-vol-level-adjust = &lt;7&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usbotg1&gt;;</div><div class='add'>+	srp-disable;</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usb_otg1_vbus&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg2 {</div><div class='add'>+	disable-over-current;</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	samsung,picophy-pre-emp-curr-control = &lt;3&gt;;</div><div class='add'>+	samsung,picophy-dc-vol-level-adjust = &lt;7&gt;;</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usb_hub_vbus&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SD-Card */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_USDHC2&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;200000000&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_nvcc_sd2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_can_int: can-intgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8	0x00</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi1: ecspi1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO	0x82</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI	0x82</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK	0x82</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi1_cs: ecspi1csgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9	0x00</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13	0x00</div><div class='add'>+			MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2	0x00</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpiokeys: keygrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9	0x00</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL	0x400001c2</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA	0x400001c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2_gpio: i2c2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17		0x1e0</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16		0x1e0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL	0x400001c2</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA	0x400001c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3_gpio: i2c3gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19		0x1e0</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18		0x1e0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4: i2c4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL	0x400001c2</div><div class='add'>+			MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA	0x400001c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4_gpio: i2c4gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21		0x1e0</div><div class='add'>+			MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20		0x1e0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_leds: leds1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30	0x00</div><div class='add'>+			MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5	0x00</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie: pciegrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* COEX2 */</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22	0x00</div><div class='add'>+			/* COEX1 */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12	0x12</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm1: pwm1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT	0x40</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm3: pwm3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT		0x40</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm4: pwm4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT	0x40</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19     0x40</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_rtc: rtcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x1c0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_tempsense: tempsensegrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31	0x00</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_tpm: tpmgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX	0x00</div><div class='add'>+			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX	0x00</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x00</div><div class='add'>+			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x00</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: uart3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX	0x140</div><div class='add'>+			MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usbhubpwr: usbhubpwrgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14	0x00</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usbotg1pwr: usbotg1pwrgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x00</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usbotg1: usbotg1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC	0x00</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x182</div><div class='add'>+			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0xc6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0xc6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0xc6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0xc6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0xc6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12	0x40</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x192</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d2</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d2</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d2</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d2</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h b/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h<br/>index 5ccc4cc91959..b1f11098d248 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h</a></div><div class='hunk'>@@ -124,7 +124,7 @@</div><div class='ctx'> #define MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD                                     0x0A4 0x30C 0x000 0x0 0x0</div><div class='ctx'> #define MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1                                      0x0A4 0x30C 0x000 0x5 0x0</div><div class='ctx'> #define MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0                                 0x0A8 0x310 0x000 0x0 0x0</div><div class='del'>-#define MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2                                    0x0A8 0x31  0x000 0x5 0x0</div><div class='add'>+#define MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2                                    0x0A8 0x310 0x000 0x5 0x0</div><div class='ctx'> #define MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1                                 0x0AC 0x314 0x000 0x0 0x0</div><div class='ctx'> #define MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3                                    0x0AC 0x314 0x000 0x5 0x0</div><div class='ctx'> #define MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2                                 0x0B0 0x318 0x000 0x0 0x0</div><div class='hunk'>@@ -248,6 +248,7 @@</div><div class='ctx'> #define MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15                                   0x130 0x398 0x000 0x5 0x0</div><div class='ctx'> #define MX8MM_IOMUXC_NAND_RE_B_SIM_M_HADDR11                                0x130 0x398 0x000 0x7 0x0</div><div class='ctx'> #define MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B                           0x134 0x39C 0x000 0x0 0x0</div><div class='add'>+#define MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B                               0x134 0x39C 0x000 0x2 0x0</div><div class='ctx'> #define MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16                                0x134 0x39C 0x000 0x5 0x0</div><div class='ctx'> #define MX8MM_IOMUXC_NAND_READY_B_SIM_M_HADDR12                             0x134 0x39C 0x000 0x7 0x0</div><div class='ctx'> #define MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B                                 0x138 0x3A0 0x000 0x0 0x0</div><div class='hunk'>@@ -279,7 +280,7 @@</div><div class='ctx'> #define MX8MM_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4                                0x150 0x3B8 0x000 0x1 0x0</div><div class='ctx'> #define MX8MM_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC                                 0x150 0x3B8 0x4CC 0x2 0x1</div><div class='ctx'> #define MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK                                 0x150 0x3B8 0x4E8 0x3 0x0</div><div class='del'>-#define MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2                                    0x150 0x3B8 0x53c 0x4 0x0</div><div class='add'>+#define MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2                                    0x150 0x3B8 0x53C 0x4 0x0</div><div class='ctx'> #define MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23                                   0x150 0x3B8 0x000 0x5 0x0</div><div class='ctx'> #define MX8MM_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3                                0x154 0x3BC 0x4E0 0x0 0x0</div><div class='ctx'> #define MX8MM_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5                                0x154 0x3BC 0x000 0x1 0x0</div><div class='hunk'>@@ -486,7 +487,7 @@</div><div class='ctx'> #define MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC                                 0x1D8 0x440 0x000 0x0 0x0</div><div class='ctx'> #define MX8MM_IOMUXC_SAI3_TXFS_GPT1_CAPTURE2                                0x1D8 0x440 0x000 0x1 0x0</div><div class='ctx'> #define MX8MM_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1                                0x1D8 0x440 0x4D8 0x2 0x2</div><div class='del'>-#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX                                 0x1D8 0x440 0x4Fc 0x4 0x2</div><div class='add'>+#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX                                 0x1D8 0x440 0x4FC 0x4 0x2</div><div class='ctx'> #define MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX                                 0x1D8 0x440 0x000 0x4 0x0</div><div class='ctx'> #define MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31                                   0x1D8 0x440 0x000 0x5 0x0</div><div class='ctx'> #define MX8MM_IOMUXC_SAI3_TXFS_TPSMP_HDATA1                                 0x1D8 0x440 0x000 0x7 0x0</div><div class='hunk'>@@ -494,7 +495,7 @@</div><div class='ctx'> #define MX8MM_IOMUXC_SAI3_TXC_GPT1_COMPARE2                                 0x1DC 0x444 0x000 0x1 0x0</div><div class='ctx'> #define MX8MM_IOMUXC_SAI3_TXC_SAI5_RX_DATA2                                 0x1DC 0x444 0x4DC 0x2 0x2</div><div class='ctx'> #define MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX                                  0x1DC 0x444 0x000 0x4 0x0</div><div class='del'>-#define MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX                                  0x1DC 0x444 0x4Fc 0x4 0x3</div><div class='add'>+#define MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX                                  0x1DC 0x444 0x4FC 0x4 0x3</div><div class='ctx'> #define MX8MM_IOMUXC_SAI3_TXC_GPIO5_IO0                                     0x1DC 0x444 0x000 0x5 0x0</div><div class='ctx'> #define MX8MM_IOMUXC_SAI3_TXC_TPSMP_HDATA2                                  0x1DC 0x444 0x000 0x7 0x0</div><div class='ctx'> #define MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0                                 0x1E0 0x448 0x000 0x0 0x0</div><div class='hunk'>@@ -601,7 +602,7 @@</div><div class='ctx'> #define MX8MM_IOMUXC_UART1_RXD_GPIO5_IO22                                   0x234 0x49C 0x000 0x5 0x0</div><div class='ctx'> #define MX8MM_IOMUXC_UART1_RXD_TPSMP_HDATA24                                0x234 0x49C 0x000 0x7 0x0</div><div class='ctx'> #define MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX                                 0x238 0x4A0 0x000 0x0 0x0</div><div class='del'>-#define MX8MM_IOMUXC_UART1_TXD_UART1_DTE_RX                                 0x238 0x4A0 0x4F4 0x0 0x0</div><div class='add'>+#define MX8MM_IOMUXC_UART1_TXD_UART1_DTE_RX                                 0x238 0x4A0 0x4F4 0x0 0x1</div><div class='ctx'> #define MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI                                  0x238 0x4A0 0x000 0x1 0x0</div><div class='ctx'> #define MX8MM_IOMUXC_UART1_TXD_GPIO5_IO23                                   0x238 0x4A0 0x000 0x5 0x0</div><div class='ctx'> #define MX8MM_IOMUXC_UART1_TXD_TPSMP_HDATA25                                0x238 0x4A0 0x000 0x7 0x0</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-prt8mm.dts b/arch/arm64/boot/dts/freescale/imx8mm-prt8mm.dts<br/>new file mode 100644<br/>index 000000000000..1eb1fe7ebde8<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-prt8mm.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-prt8mm.dts</a></div><div class='hunk'>@@ -0,0 +1,304 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2020 Protonic Holland</div><div class='add'>+ * Copyright 2019 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/usb/pd.h&gt;</div><div class='add'>+#include "imx8mm.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Protonic PRT8MM";</div><div class='add'>+	compatible = "prt,prt8mm", "fsl,imx8mm";</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart4;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x40000000 0 0x40000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_leds&gt;;</div><div class='add'>+</div><div class='add'>+		debug-led0 {</div><div class='add'>+			label = "DEBUG_LED0";</div><div class='add'>+			gpios = &lt;&amp;gpio3 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		debug-led1 {</div><div class='add'>+			label = "DEBUG_LED1";</div><div class='add'>+			gpios = &lt;&amp;gpio3 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "cpu";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-ssm2518 {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,name = "ssm2518-audio";</div><div class='add'>+		simple-audio-card,format = "i2s";</div><div class='add'>+		simple-audio-card,frame-master = &lt;&amp;cpudai&gt;;</div><div class='add'>+		simple-audio-card,bitclock-master = &lt;&amp;cpudai&gt;;</div><div class='add'>+</div><div class='add'>+		cpudai: simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;sai3&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		simple-audio-card,codec {</div><div class='add'>+			sound-dai = &lt;&amp;ssm2518&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MM_CLK_SAI3_ROOT&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ssm2518: audio-codec@34 {</div><div class='add'>+		compatible = "adi,ssm2518";</div><div class='add'>+		reg = &lt;0x34&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	regulator@60 {</div><div class='add'>+		compatible = "fcs,fan53555";</div><div class='add'>+		reg = &lt;0x60&gt;;</div><div class='add'>+		regulator-name = "0V9_CORE";</div><div class='add'>+		regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;980000&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	rtc@51 {</div><div class='add'>+		compatible = "nxp,pcf85363";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	touchscreeen@5d {</div><div class='add'>+		compatible = "goodix,gt911";</div><div class='add'>+		reg = &lt;0x5d&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_touchscreen&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;8 IRQ_TYPE_NONE&gt;;</div><div class='add'>+		irq-gpios = &lt;&amp;gpio1 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio1 9 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	temp-sense@70 {</div><div class='add'>+		compatible = "ti,tmp103";</div><div class='add'>+		reg = &lt;0x70&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai3&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_SAI3&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;12288000&gt;;</div><div class='add'>+	fsl,sai-mclk-direction-output;</div><div class='add'>+	fsl,sai-asynchronous;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;snvs_pwrkey {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usbotg1&gt;;</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	disable-over-current;</div><div class='add'>+	power-active-high;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_USDHC2&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;100000000&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_USDHC3_ROOT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	no-sdio;</div><div class='add'>+	no-sd;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_gpio_leds: ledsgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0			0x00</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1		0x00</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL			0x400000c3</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA			0x400000c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL			0x400000c3</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA			0x400000c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL			0x400000c3</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA			0x400000c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai3: sai3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC		0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK		0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK		0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0		0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_touchscreen: tsgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8		0x80</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x80</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart4: uart4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX		0x040</div><div class='add'>+			MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX		0x040</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usbotg1: usbotg1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR		0x000</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC		0x000</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x190</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x0d4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x190</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x190</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x194</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x194</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x196</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x196</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0xc6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtso b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtso<br/>new file mode 100644<br/>index 000000000000..e44249c6d8a0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtso</a></div><div class='hunk'>@@ -0,0 +1,45 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2022-2023 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Alexander Stein</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+</div><div class='add'>+&amp;{/} {</div><div class='add'>+	compatible = "tq,imx8mm-tqma8mqml-mba8mx", "tq,imx8mm-tqma8mqml", "fsl,imx8mm";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;backlight_lvds {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsi_lvds_bridge {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;expander0 {</div><div class='add'>+	dsi-mux-oe-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		output-high;</div><div class='add'>+		line-name = "DSI_MUX_OE#";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_dsi {</div><div class='add'>+       status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;panel {</div><div class='add'>+	compatible = "tianma,tm070jvhg33";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts<br/>new file mode 100644<br/>index 000000000000..b941c8c4f7bb<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts</a></div><div class='hunk'>@@ -0,0 +1,302 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2020-2021 TQ-Systems GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/phy/phy-imx8-pcie.h&gt;</div><div class='add'>+</div><div class='add'>+#include "imx8mm-tqma8mqml.dtsi"</div><div class='add'>+#include "mba8mx.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "TQ-Systems GmbH i.MX8MM TQMa8MxML on MBa8Mx";</div><div class='add'>+	compatible = "tq,imx8mm-tqma8mqml-mba8mx", "tq,imx8mm-tqma8mqml", "fsl,imx8mm";</div><div class='add'>+	chassis-type = "embedded";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		eeprom0 = &amp;eeprom3;</div><div class='add'>+		mmc0 = &amp;usdhc3;</div><div class='add'>+		mmc1 = &amp;usdhc2;</div><div class='add'>+		mmc2 = &amp;usdhc1;</div><div class='add'>+		rtc0 = &amp;pcf85063;</div><div class='add'>+		rtc1 = &amp;snvs_rtc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-vmmc {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usdhc2_vmmc&gt;;</div><div class='add'>+		regulator-name = "VSD_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio2 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		startup-delay-us = &lt;100&gt;;</div><div class='add'>+		off-on-delay-us = &lt;12000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	connector {</div><div class='add'>+		compatible = "gpio-usb-b-connector", "usb-b-connector";</div><div class='add'>+		type = "micro";</div><div class='add'>+		label = "X19";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usb1_connector&gt;;</div><div class='add'>+		id-gpios = &lt;&amp;gpio1 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				usb_dr_connector: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;usb1_drd_sw&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	expander2: gpio@27 {</div><div class='add'>+		compatible = "nxp,pca9555";</div><div class='add'>+		reg = &lt;0x27&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_vcc_3v3&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_expander&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;9 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_dsi {</div><div class='add'>+	samsung,burst-clock-frequency = &lt;891000000&gt;;</div><div class='add'>+	samsung,esc-clock-frequency = &lt;20000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	fsl,refclk-pad-mode = &lt;IMX8_PCIE_REFCLK_PAD_INPUT&gt;;</div><div class='add'>+	fsl,clkreq-unsupported;</div><div class='add'>+	clocks = &lt;&amp;pcieclk 2&gt;;</div><div class='add'>+	clock-names = "ref";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* PCIe slot on X36 */</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	reset-gpio = &lt;&amp;expander0 14 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	clocks = &lt;&amp;clk IMX8MM_CLK_PCIE1_ROOT&gt;, &lt;&amp;pcieclk 3&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX8MM_CLK_PCIE1_AUX&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_PCIE1_AUX&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MM_CLK_PCIE1_CTRL&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;10000000&gt;, &lt;250000000&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL2_50M&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MM_SYS_PLL2_250M&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai3 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_SAI3&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";</div><div class='add'>+	clocks = &lt;&amp;clk IMX8MM_CLK_SAI3_IPG&gt;, &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;,</div><div class='add'>+		&lt;&amp;clk IMX8MM_CLK_SAI3_ROOT&gt;, &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;,</div><div class='add'>+		&lt;&amp;clk IMX8MM_CLK_DUMMY&gt;, &lt;&amp;clk IMX8MM_AUDIO_PLL1_OUT&gt;,</div><div class='add'>+		&lt;&amp;clk IMX8MM_AUDIO_PLL2_OUT&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tlv320aic3x04 {</div><div class='add'>+	clock-names = "mclk";</div><div class='add'>+	clocks = &lt;&amp;clk IMX8MM_CLK_SAI3_ROOT&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_UART1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL1_80M&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_UART2&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL1_80M&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usbotg1&gt;;</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	srp-disable;</div><div class='add'>+	hnp-disable;</div><div class='add'>+	adp-disable;</div><div class='add'>+	power-active-high;</div><div class='add'>+	over-current-active-low;</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	port {</div><div class='add'>+		usb1_drd_sw: endpoint {</div><div class='add'>+			remote-endpoint = &lt;&amp;usb_dr_connector&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg2 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	disable-over-current;</div><div class='add'>+	vbus-supply = &lt;&amp;reg_hub_vbus&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_ecspi1: ecspi1grp {</div><div class='add'>+		fsl,pins = &lt;MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK	0x00000006&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI	0x00000006&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO	0x00000006&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9		0x00000006&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi2: ecspi2grp {</div><div class='add'>+		fsl,pins = &lt;MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0x00000006&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0x00000006&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO	0x00000006&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13		0x00000006&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_expander: expandergrp {</div><div class='add'>+		fsl,pins = &lt;MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x94&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec1: fec1grp {</div><div class='add'>+		fsl,pins = &lt;MX8MM_IOMUXC_ENET_MDC_ENET1_MDC		0x40000002&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x40000002&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x14&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x14&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x14&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x14&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x90&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x90&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x90&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x90&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x14&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x90&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x90&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x14&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpiobutton: gpiobuttongrp {</div><div class='add'>+		fsl,pins = &lt;MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5		0x84&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x84&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0		0x84&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpioled: gpioledgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0		0x84&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_NAND_DQS_GPIO3_IO14		0x84&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL		0x40000004&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA		0x40000004&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2_gpio: i2c2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16		0x40000004&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17		0x40000004&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+		fsl,pins = &lt;MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL		0x40000004&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA		0x40000004&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3_gpio: i2c3gpiogrp {</div><div class='add'>+		fsl,pins = &lt;MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18		0x40000004&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19		0x40000004&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm3: pwm3grp {</div><div class='add'>+		fsl,pins = &lt;MX8MM_IOMUXC_GPIO1_IO14_PWM3_OUT		0x14&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm4: pwm4grp {</div><div class='add'>+		fsl,pins = &lt;MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT		0x14&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai3: sai3grp {</div><div class='add'>+		fsl,pins = &lt;MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK		0x94&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK		0x94&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC		0x94&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0		0x94&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC		0x94&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0		0x94&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK		0x94&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX		0x16&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX		0x16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX		0x16&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX		0x16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: uart3grp {</div><div class='add'>+		fsl,pins = &lt;MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX		0x16&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX		0x16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart4: uart4grp {</div><div class='add'>+		fsl,pins = &lt;MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX		0x16&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX		0x16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usbotg1: usbotg1grp {</div><div class='add'>+		fsl,pins = &lt;MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR	0x84&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC		0x84&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usb1_connector: usb1-connectorgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x1c0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {</div><div class='add'>+		fsl,pins = &lt;MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x84&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x84&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x84&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x84&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi<br/>new file mode 100644<br/>index 000000000000..b82e9790ea20<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi</a></div><div class='hunk'>@@ -0,0 +1,352 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2020-2021 TQ-Systems GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/phy/phy-imx8-pcie.h&gt;</div><div class='add'>+#include "imx8mm.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "TQ-Systems GmbH i.MX8MM TQMa8MxML";</div><div class='add'>+	compatible = "tq,imx8mm-tqma8mqml", "fsl,imx8mm";</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		/*  our minimum RAM config will be 1024 MiB */</div><div class='add'>+		reg = &lt;0x00000000 0x40000000 0 0x40000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* e-MMC IO, needed for HS modes */</div><div class='add'>+	reg_vcc1v8: regulator-vcc1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "TQMA8MXML_VCC1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* identical to buck4_reg, but should never change */</div><div class='add'>+	reg_vcc3v3: regulator-vcc3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "TQMA8MXML_VCC3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		/* global autoconfigured region for contiguous allocations */</div><div class='add'>+		linux,cma {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reusable;</div><div class='add'>+			/* 640 MiB */</div><div class='add'>+			size = &lt;0 0x28000000&gt;;</div><div class='add'>+			/*  1024 - 128 MiB, our minimum RAM config will be 1024 MiB */</div><div class='add'>+			alloc-ranges = &lt;0 0x40000000 0 0x78000000&gt;;</div><div class='add'>+			linux,cma-default;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexspi {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexspi&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash0: flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;84000000&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;1&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;buck5_reg&gt;;</div><div class='add'>+</div><div class='add'>+		partitions {</div><div class='add'>+			compatible = "fixed-partitions";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu_2d {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu_3d {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c1_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	sensor0: temperature-sensor@1b {</div><div class='add'>+		compatible = "nxp,se97b", "jedec,jc-42.4-temp";</div><div class='add'>+		reg = &lt;0x1b&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pca9450: pmic@25 {</div><div class='add'>+		compatible = "nxp,pca9450a";</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+</div><div class='add'>+		/* PMIC PCA9450 PMIC_nINT GPIO1_IO08 */</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;8 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			/* V_0V85_SOC: 0.85 */</div><div class='add'>+			buck1_reg: BUCK1 {</div><div class='add'>+				regulator-name = "BUCK1";</div><div class='add'>+				regulator-min-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* VDD_ARM */</div><div class='add'>+			buck2_reg: BUCK2 {</div><div class='add'>+				regulator-name = "BUCK2";</div><div class='add'>+				regulator-min-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				nxp,dvs-run-voltage = &lt;950000&gt;;</div><div class='add'>+				nxp,dvs-standby-voltage = &lt;850000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* V_0V85_GPU / DRAM / VPU */</div><div class='add'>+			buck3_reg: BUCK3 {</div><div class='add'>+				regulator-name = "BUCK3";</div><div class='add'>+				regulator-min-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;950000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* VCC3V3 -&gt; VMMC, ... must not be changed */</div><div class='add'>+			buck4_reg: BUCK4 {</div><div class='add'>+				regulator-name = "BUCK4";</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* V_1V8 -&gt; VQMMC, SPI-NOR, ... must not be changed */</div><div class='add'>+			buck5_reg: BUCK5 {</div><div class='add'>+				regulator-name = "BUCK5";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* V_1V1 -&gt; RAM, ... must not be changed */</div><div class='add'>+			buck6_reg: BUCK6 {</div><div class='add'>+				regulator-name = "BUCK6";</div><div class='add'>+				regulator-min-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* V_1V8_SNVS */</div><div class='add'>+			ldo1_reg: LDO1 {</div><div class='add'>+				regulator-name = "LDO1";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* V_0V8_SNVS */</div><div class='add'>+			ldo2_reg: LDO2 {</div><div class='add'>+				regulator-name = "LDO2";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* V_1V8_ANA */</div><div class='add'>+			ldo3_reg: LDO3 {</div><div class='add'>+				regulator-name = "LDO3";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* V_0V9_MIPI */</div><div class='add'>+			ldo4_reg: LDO4 {</div><div class='add'>+				regulator-name = "LDO4";</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* VCC SD IO - switched using SD2 VSELECT */</div><div class='add'>+			ldo5_reg: LDO5 {</div><div class='add'>+				regulator-name = "LDO5";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	pcf85063: rtc@51 {</div><div class='add'>+		compatible = "nxp,pcf85063a";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		quartz-load-femtofarads = &lt;7000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom1: eeprom@53 {</div><div class='add'>+		compatible = "nxp,se97b", "atmel,24c02";</div><div class='add'>+		read-only;</div><div class='add'>+		reg = &lt;0x53&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_vcc3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom0: eeprom@57 {</div><div class='add'>+		compatible = "atmel,24c64";</div><div class='add'>+		reg = &lt;0x57&gt;;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_vcc3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_dsi {</div><div class='add'>+	vddcore-supply = &lt;&amp;ldo4_reg&gt;;</div><div class='add'>+	vddio-supply = &lt;&amp;ldo3_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	fsl,refclk-pad-mode = &lt;IMX8_PCIE_REFCLK_PAD_INPUT&gt;;</div><div class='add'>+	fsl,clkreq-unsupported;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	no-sd;</div><div class='add'>+	no-sdio;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_vcc3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_vcc1v8&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Attention:</div><div class='add'>+ * wdog reset is routed to PMIC, PMIC must be preconfigured to force POR</div><div class='add'>+ * without LDO for SNVS. GPIO1_IO02 must not be used as GPIO.</div><div class='add'>+ */</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_flexspi: flexspigrp {</div><div class='add'>+		fsl,pins = &lt;MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK		0x82&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B	0x82&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0	0x82&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1	0x82&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2	0x82&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3	0x82&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL		0x40000004&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA		0x40000004&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1_gpio: i2c1gpiogrp {</div><div class='add'>+		fsl,pins = &lt;MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14		0x40000004&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15		0x40000004&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: pmicgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8		0x94&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19		0x84&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d2&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x84&gt;,</div><div class='add'>+			   /* option USDHC3_RESET_B not defined, only in RM */</div><div class='add'>+			   &lt;MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16	0x84&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x1d2&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d2&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x84&gt;,</div><div class='add'>+			   /* option USDHC3_RESET_B not defined, only in RM */</div><div class='add'>+			   &lt;MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16	0x84&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x1d6&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d2&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x84&gt;,</div><div class='add'>+			   /* option USDHC3_RESET_B not defined, only in RM */</div><div class='add'>+			   &lt;MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16	0x84&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0x84&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ucm-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-ucm-som.dtsi<br/>new file mode 100644<br/>index 000000000000..d3b21203c5f4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-ucm-som.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-ucm-som.dtsi</a></div><div class='hunk'>@@ -0,0 +1,679 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+//</div><div class='add'>+// Copyright 2018 CompuLab</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mm.dtsi"</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		rtc0 = &amp;rtc_i2c;</div><div class='add'>+		rtc1 = &amp;snvs_rtc;</div><div class='add'>+		mmc0 = &amp;usdhc3;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart3;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	backlight {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		pwms = &lt;&amp;pwm2 0 3000000 0&gt;;</div><div class='add'>+		brightness-levels = &lt;0 255&gt;;</div><div class='add'>+		num-interpolated-steps = &lt;255&gt;;</div><div class='add'>+		default-brightness-level = &lt;222&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_led&gt;;</div><div class='add'>+</div><div class='add'>+		heartbeat-led {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			gpios = &lt;&amp;gpio1 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmic_osc: clock-pmic {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;32768&gt;;</div><div class='add'>+		clock-output-names = "pmic_osc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wlreg_on: regulator-wlreg-on {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "wlreg_on";</div><div class='add'>+		gpio = &lt;&amp;gpio2 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		startup-delay-us = &lt;100&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VSD_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio2 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		startup-delay-us = &lt;100&gt;;</div><div class='add'>+		off-on-delay-us = &lt;12000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	regulator-usdhc3rst {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "usdhc3_rst";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio3 16 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	regulator-fec1rst {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "fec1_rst";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio1 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		startup-delay-us = &lt;500&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	arm-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu_alert0 {</div><div class='add'>+	temperature = &lt;105000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu_crit0 {</div><div class='add'>+	temperature = &lt;115000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec1&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	fsl,magic-packet;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@0 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pmic@4b {</div><div class='add'>+		reg = &lt;0x4b&gt;;</div><div class='add'>+		compatible = "rohm,bd71837";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clocks = &lt;&amp;pmic_osc&gt;;</div><div class='add'>+		clock-names = "osc";</div><div class='add'>+		clock-output-names = "pmic_clk";</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;3 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		rohm,reset-snvs-powered;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			buck1: BUCK1 {</div><div class='add'>+				regulator-name = "buck1";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;1250&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck2: BUCK2 {</div><div class='add'>+				regulator-name = "buck2";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;1250&gt;;</div><div class='add'>+				rohm,dvs-run-voltage = &lt;1000000&gt;;</div><div class='add'>+				rohm,dvs-idle-voltage = &lt;900000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck3: BUCK3 {</div><div class='add'>+				regulator-name = "buck3";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck4: BUCK4 {</div><div class='add'>+				regulator-name = "buck4";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck5: BUCK5 {</div><div class='add'>+				regulator-name = "buck5";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck6: BUCK6 {</div><div class='add'>+				regulator-name = "buck6";</div><div class='add'>+				regulator-min-microvolt = &lt;3000000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck7: BUCK7 {</div><div class='add'>+				regulator-name = "buck7";</div><div class='add'>+				regulator-min-microvolt = &lt;1605000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1995000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck8: BUCK8 {</div><div class='add'>+				regulator-name = "buck8";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo1: LDO1 {</div><div class='add'>+				regulator-name = "ldo1";</div><div class='add'>+				regulator-min-microvolt = &lt;1600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1900000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo2: LDO2 {</div><div class='add'>+				regulator-name = "ldo2";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo3: LDO3 {</div><div class='add'>+				regulator-name = "ldo3";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo4: LDO4 {</div><div class='add'>+				regulator-name = "ldo4";</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo5: LDO5 {</div><div class='add'>+				regulator-name = "ldo5";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo6: LDO6 {</div><div class='add'>+				regulator-name = "ldo6";</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo7: LDO7 {</div><div class='add'>+				regulator-name = "ldo7";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@50 {</div><div class='add'>+		compatible = "atmel,24c08";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rtc_i2c: rtc@69 {</div><div class='add'>+		compatible = "abracon,ab1805";</div><div class='add'>+		reg = &lt;0x69&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm_backlight&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai2 {</div><div class='add'>+	#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai2&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_SAI2&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;49152000&gt;;</div><div class='add'>+	clocks = &lt;&amp;clk IMX8MM_CLK_SAI2_IPG&gt;, &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;,</div><div class='add'>+		&lt;&amp;clk IMX8MM_CLK_SAI2_ROOT&gt;, &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;,</div><div class='add'>+		&lt;&amp;clk IMX8MM_CLK_DUMMY&gt;, &lt;&amp;clk IMX8MM_AUDIO_PLL1_OUT&gt;,</div><div class='add'>+		&lt;&amp;clk IMX8MM_AUDIO_PLL2_OUT&gt;;</div><div class='add'>+	clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";</div><div class='add'>+	fsl,sai-asynchronous;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;snvs {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;snvs_pwrkey {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_UART1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL1_80M&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_UART2&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL1_80M&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart3 { /* console */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart4 { /* bluetooth */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart4&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_UART4&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL1_80M&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "disabled";</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "brcm,bcm4330-bt";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_bt&gt;;</div><div class='add'>+		max-speed = &lt;3000000&gt;;</div><div class='add'>+		device-wakeup-gpios = &lt;&amp;gpio2 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		host-wakeup-gpios = &lt;&amp;gpio2 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		shutdown-gpios = &lt;&amp;gpio2 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	hnp-disable;</div><div class='add'>+	srp-disable;</div><div class='add'>+	disable-over-current;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg2 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	hnp-disable;</div><div class='add'>+	srp-disable;</div><div class='add'>+	disable-over-current;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;, &lt;&amp;pinctrl_usdhc1_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1_100mhz&gt;, &lt;&amp;pinctrl_usdhc1_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1_200mhz&gt;, &lt;&amp;pinctrl_usdhc1_gpio&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	wp-gpios = &lt;&amp;gpio2 20 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	no-1-8-v;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	no-1-8-v;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hog_1&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl_hog: hoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x19</div><div class='add'>+			MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16		0x190</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_bt: bt0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6		0x19 /* BT_REG_ON */</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7		0x19 /* BT_DEV_WU */</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8		0x19 /* BT_HST_WU */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec1: fec1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3</div><div class='add'>+			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio_led: gpioledgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12		0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL			0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA			0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL			0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA			0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL			0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA			0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4: i2c4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL			0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA			0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: pmicgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm_backlight: pwmbacklightgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO13_PWM2_OUT		0x03</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	pinctrl_sai2: sai2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK		0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC		0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC		0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK		0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0		0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0		0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX		0x140</div><div class='add'>+			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX		0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX		0x140</div><div class='add'>+			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX		0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: uart3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX		0x49</div><div class='add'>+			MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX		0x49</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart4: uart4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B	0x140</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX		0x140</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B		0x140</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX		0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_gpio: usdhc1grpgpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10		0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK			0x190</div><div class='add'>+			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD			0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO03_USDHC1_VSELECT		0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1grp100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK			0x194</div><div class='add'>+			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD			0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO03_USDHC1_VSELECT		0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1grp200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK			0x196</div><div class='add'>+			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD			0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO03_USDHC1_VSELECT		0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19		0x41</div><div class='add'>+			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x41</div><div class='add'>+			MX8MM_IOMUXC_SD2_WP_GPIO2_IO20			0x00</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x190</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2grp100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x194</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2grp200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x196</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x40000190</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x190</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3grp100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x40000194</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x194</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3grp200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x40000196</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x196</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0xc6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts<br/>new file mode 100644<br/>index 000000000000..affbc67c2ef6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts</a></div><div class='hunk'>@@ -0,0 +1,254 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2020 Krzysztof Kozlowski &lt;krzk@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mm-var-som.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Variscite VAR-SOM-MX8MM Symphony evaluation board";</div><div class='add'>+	compatible = "variscite,var-som-mx8mm-symphony", "variscite,var-som-mx8mm", "fsl,imx8mm";</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usdhc2_vmmc&gt;;</div><div class='add'>+		regulator-name = "VSD_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio2 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb_otg2_vbus: regulator-usb-otg2-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usb_otg2_vbus&gt;;</div><div class='add'>+		regulator-name = "usb_otg2_vbus";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio5 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		key-back {</div><div class='add'>+			label = "Back";</div><div class='add'>+			gpios = &lt;&amp;pca9534 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_BACK&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-home {</div><div class='add'>+			label = "Home";</div><div class='add'>+			gpios = &lt;&amp;pca9534 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_HOME&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-menu {</div><div class='add'>+			label = "Menu";</div><div class='add'>+			gpios = &lt;&amp;pca9534 3 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_MENU&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led {</div><div class='add'>+			label = "Heartbeat";</div><div class='add'>+			gpios = &lt;&amp;pca9534 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethphy {</div><div class='add'>+	reset-gpios = &lt;&amp;pca9534 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pca9534: gpio@20 {</div><div class='add'>+		compatible = "nxp,pca9534";</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pca9534&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;7 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		wakeup-source;</div><div class='add'>+</div><div class='add'>+		/* USB 3.0 OTG (usbotg1) / SATA port switch, set to USB 3.0 */</div><div class='add'>+		usb3-sata-sel-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+			line-name = "usb3_sata_sel";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		som-vselect-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+			line-name = "som_vselect";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		enet-sel-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+			line-name = "enet_sel";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	extcon_usbotg1: typec@3d {</div><div class='add'>+		compatible = "nxp,ptn5150";</div><div class='add'>+		reg = &lt;0x3d&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;11 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_ptn5150&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	/* Capacitive touch controller */</div><div class='add'>+	ft5x06_ts: touchscreen@38 {</div><div class='add'>+		compatible = "edt,edt-ft5406";</div><div class='add'>+		reg = &lt;0x38&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_captouch&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio5&gt;;</div><div class='add'>+		interrupts = &lt;4 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+		touchscreen-size-x = &lt;800&gt;;</div><div class='add'>+		touchscreen-size-y = &lt;480&gt;;</div><div class='add'>+		touchscreen-inverted-x;</div><div class='add'>+		touchscreen-inverted-y;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rtc@68 {</div><div class='add'>+		compatible = "dallas,ds1337";</div><div class='add'>+		reg = &lt;0x68&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Header */</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Header */</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	disable-over-current;</div><div class='add'>+	extcon = &lt;&amp;extcon_usbotg1&gt;, &lt;&amp;extcon_usbotg1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg2 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usb_otg2_vbus&gt;;</div><div class='add'>+	srp-disable;</div><div class='add'>+	hnp-disable;</div><div class='add'>+	adp-disable;</div><div class='add'>+	disable-over-current;</div><div class='add'>+	/delete-property/ usb-role-switch;</div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: having USB2 enabled hangs the boot just after:</div><div class='add'>+	 * [    1.943365] ci_hdrc ci_hdrc.1: EHCI Host Controller</div><div class='add'>+	 * [    1.948287] ci_hdrc ci_hdrc.1: new USB bus registered, assigned bus number 1</div><div class='add'>+	 * [    1.971006] ci_hdrc ci_hdrc.1: USB 2.0 started, EHCI 1.00</div><div class='add'>+	 * [    1.977203] hub 1-0:1.0: USB hub found</div><div class='add'>+	 * [    1.980987] hub 1-0:1.0: 1 port detected</div><div class='add'>+	 */</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_fec1 {</div><div class='add'>+	fsl,pins = &lt;</div><div class='add'>+		MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3</div><div class='add'>+		MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3</div><div class='add'>+		MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f</div><div class='add'>+		MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f</div><div class='add'>+		MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f</div><div class='add'>+		MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f</div><div class='add'>+		MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91</div><div class='add'>+		MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91</div><div class='add'>+		MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91</div><div class='add'>+		MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91</div><div class='add'>+		MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f</div><div class='add'>+		MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91</div><div class='add'>+		MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91</div><div class='add'>+		MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f</div><div class='add'>+		/* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */</div><div class='add'>+	&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_captouch: captouchgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4		0x16</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pca9534: pca9534grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7	0x16</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ptn5150: ptn5150grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11	0x16</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usb_otg2_vbus: regusbotg2vbusgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1		0x16</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140</div><div class='add'>+			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: uart3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX	0x140</div><div class='add'>+			MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi<br/>new file mode 100644<br/>index 000000000000..190bde4edcd7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi</a></div><div class='hunk'>@@ -0,0 +1,556 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2019 NXP</div><div class='add'>+ * Copyright (C) 2020 Krzysztof Kozlowski &lt;krzk@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "imx8mm.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Variscite VAR-SOM-MX8MM module";</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart4;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x40000000 0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_eth_phy: regulator-eth-phy {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_eth_phy&gt;;</div><div class='add'>+		regulator-name = "eth_phy_pwr";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio2 9 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ddrc {</div><div class='add'>+	operating-points-v2 = &lt;&amp;ddrc_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+	ddrc_opp_table: opp-table {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		opp-25000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;25000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-100000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;100000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-750000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;750000000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi1&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio1 14 GPIO_ACTIVE_LOW&gt;,</div><div class='add'>+		   &lt;&amp;gpio1  0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	/delete-property/ dmas;</div><div class='add'>+	/delete-property/ dma-names;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* Resistive touch controller */</div><div class='add'>+	touchscreen@0 {</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		compatible = "ti,ads7846";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_restouch&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;3 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+</div><div class='add'>+		spi-max-frequency = &lt;1500000&gt;;</div><div class='add'>+		pendown-gpio = &lt;&amp;gpio1 3 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		ti,x-min = /bits/ 16 &lt;125&gt;;</div><div class='add'>+		touchscreen-size-x = &lt;4008&gt;;</div><div class='add'>+		ti,y-min = /bits/ 16 &lt;282&gt;;</div><div class='add'>+		touchscreen-size-y = &lt;3864&gt;;</div><div class='add'>+		ti,x-plate-ohms = /bits/ 16 &lt;180&gt;;</div><div class='add'>+		touchscreen-max-pressure = &lt;255&gt;;</div><div class='add'>+		touchscreen-average-samples = &lt;10&gt;;</div><div class='add'>+		ti,debounce-tol = /bits/ 16 &lt;3&gt;;</div><div class='add'>+		ti,debounce-rep = /bits/ 16 &lt;1&gt;;</div><div class='add'>+		ti,settle-delay-usec = /bits/ 16 &lt;150&gt;;</div><div class='add'>+		ti,keep-vref-on;</div><div class='add'>+		wakeup-source;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec1&gt;;</div><div class='add'>+	phy-mode = "rgmii";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy&gt;;</div><div class='add'>+	phy-supply = &lt;&amp;reg_eth_phy&gt;;</div><div class='add'>+	fsl,magic-packet;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy: ethernet-phy@4 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;4&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio1 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;10000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;10000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pmic@4b {</div><div class='add'>+		compatible = "rohm,bd71847";</div><div class='add'>+		reg = &lt;0x4b&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio2&gt;;</div><div class='add'>+		interrupts = &lt;8 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		rohm,reset-snvs-powered;</div><div class='add'>+</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clocks = &lt;&amp;osc_32k&gt;;</div><div class='add'>+		clock-output-names = "clk-32k-out";</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			buck1_reg: BUCK1 {</div><div class='add'>+				regulator-name = "buck1";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;1250&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck2_reg: BUCK2 {</div><div class='add'>+				regulator-name = "buck2";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;1250&gt;;</div><div class='add'>+				rohm,dvs-run-voltage = &lt;1000000&gt;;</div><div class='add'>+				rohm,dvs-idle-voltage = &lt;900000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck3_reg: BUCK3 {</div><div class='add'>+				regulator-name = "buck3";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck4_reg: BUCK4 {</div><div class='add'>+				regulator-name = "buck4";</div><div class='add'>+				regulator-min-microvolt = &lt;3000000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck5_reg: BUCK5 {</div><div class='add'>+				regulator-name = "buck5";</div><div class='add'>+				regulator-min-microvolt = &lt;1605000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1995000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck6_reg: BUCK6 {</div><div class='add'>+				regulator-name = "buck6";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo1_reg: LDO1 {</div><div class='add'>+				regulator-name = "ldo1";</div><div class='add'>+				regulator-min-microvolt = &lt;1600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1900000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo2_reg: LDO2 {</div><div class='add'>+				regulator-name = "ldo2";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo3_reg: LDO3 {</div><div class='add'>+				regulator-name = "ldo3";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo4_reg: LDO4 {</div><div class='add'>+				regulator-name = "ldo4";</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo5_reg: LDO5 {</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo6_reg: LDO6 {</div><div class='add'>+				regulator-name = "ldo6";</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* TODO: configure audio, as of now just put a placeholder */</div><div class='add'>+	wm8904: codec@1a {</div><div class='add'>+		compatible = "wlf,wm8904";</div><div class='add'>+		reg = &lt;0x1a&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;snvs_pwrkey {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Bluetooth */</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_UART2&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL1_80M&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Console */</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg2 {</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* WIFI */</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1_200mhz&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	keep-power-in-suspend;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	brcmf: wifi@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		compatible = "brcm,bcm4329-fmac";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SD */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_USDHC2&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;200000000&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio1 10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* eMMC */</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_USDHC3_ROOT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_ecspi1: ecspi1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK		0x13</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI		0x13</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO		0x13</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14		0x13</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0		0x13</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec1: fec1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3</div><div class='add'>+			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: pmicirqgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8	0x141</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_eth_phy: regethphygrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_restouch: restouchgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x1c0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX	0x140</div><div class='add'>+			MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX	0x140</div><div class='add'>+			MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B	0x140</div><div class='add'>+			MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart4: uart4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX	0x140</div><div class='add'>+			MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x190</div><div class='add'>+			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x194</div><div class='add'>+			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x196</div><div class='add'>+			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10	0xc1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x190</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x190</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x194</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x194</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x196</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x196</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0x166</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi<br/>new file mode 100644<br/>index 000000000000..dca213c85cc3<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi</a></div><div class='hunk'>@@ -0,0 +1,551 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2020 Gateworks Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/linux-event-codes.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/net/ti-dp83867.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		rtc0 = &amp;gsc_rtc;</div><div class='add'>+		rtc1 = &amp;snvs_rtc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x40000000 0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		key-user-pb {</div><div class='add'>+			label = "user_pb";</div><div class='add'>+			gpios = &lt;&amp;gpio 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;BTN_0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-user-pb1x {</div><div class='add'>+			label = "user_pb1x";</div><div class='add'>+			linux,code = &lt;BTN_1&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gsc&gt;;</div><div class='add'>+			interrupts = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-erased {</div><div class='add'>+			label = "key_erased";</div><div class='add'>+			linux,code = &lt;BTN_2&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gsc&gt;;</div><div class='add'>+			interrupts = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-eeprom-wp {</div><div class='add'>+			label = "eeprom_wp";</div><div class='add'>+			linux,code = &lt;BTN_3&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gsc&gt;;</div><div class='add'>+			interrupts = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-tamper {</div><div class='add'>+			label = "tamper";</div><div class='add'>+			linux,code = &lt;BTN_4&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gsc&gt;;</div><div class='add'>+			interrupts = &lt;5&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		switch-hold {</div><div class='add'>+			label = "switch_hold";</div><div class='add'>+			linux,code = &lt;BTN_5&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gsc&gt;;</div><div class='add'>+			interrupts = &lt;7&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck3_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck3_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck3_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck3_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ddrc {</div><div class='add'>+	operating-points-v2 = &lt;&amp;ddrc_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+	ddrc_opp_table: opp-table {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		opp-25000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;25000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-100000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;100000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-750000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;750000000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec1&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@0 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			ti,clk-output-sel = &lt;DP83867_CLK_O_SEL_OFF&gt;;</div><div class='add'>+			ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_2_00_NS&gt;;</div><div class='add'>+			ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_2_00_NS&gt;;</div><div class='add'>+			tx-fifo-depth = &lt;DP83867_PHYCR_FIFO_DEPTH_4_B_NIB&gt;;</div><div class='add'>+			rx-fifo-depth = &lt;DP83867_PHYCR_FIFO_DEPTH_4_B_NIB&gt;;</div><div class='add'>+</div><div class='add'>+			leds {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				led@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					color = &lt;LED_COLOR_ID_AMBER&gt;;</div><div class='add'>+					function = LED_FUNCTION_LAN;</div><div class='add'>+					default-state = "keep";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				led@2 {</div><div class='add'>+					reg = &lt;2&gt;;</div><div class='add'>+					color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+					function = LED_FUNCTION_LAN;</div><div class='add'>+					default-state = "keep";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c1_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	gsc: gsc@20 {</div><div class='add'>+		compatible = "gw,gsc";</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gsc&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio2&gt;;</div><div class='add'>+		interrupts = &lt;6 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		adc {</div><div class='add'>+			compatible = "gw,gsc-adc";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			channel@6 {</div><div class='add'>+				gw,mode = &lt;0&gt;;</div><div class='add'>+				reg = &lt;0x06&gt;;</div><div class='add'>+				label = "temp";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@8 {</div><div class='add'>+				gw,mode = &lt;3&gt;;</div><div class='add'>+				reg = &lt;0x08&gt;;</div><div class='add'>+				label = "vdd_bat";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@16 {</div><div class='add'>+				gw,mode = &lt;4&gt;;</div><div class='add'>+				reg = &lt;0x16&gt;;</div><div class='add'>+				label = "fan_tach";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@82 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x82&gt;;</div><div class='add'>+				label = "vdd_vin";</div><div class='add'>+				gw,voltage-divider-ohms = &lt;22100 1000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@84 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x84&gt;;</div><div class='add'>+				label = "vdd_adc1";</div><div class='add'>+				gw,voltage-divider-ohms = &lt;10000 10000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@86 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x86&gt;;</div><div class='add'>+				label = "vdd_adc2";</div><div class='add'>+				gw,voltage-divider-ohms = &lt;10000 10000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@88 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x88&gt;;</div><div class='add'>+				label = "vdd_dram";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@8c {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x8c&gt;;</div><div class='add'>+				label = "vdd_1p2";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@8e {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x8e&gt;;</div><div class='add'>+				label = "vdd_1p0";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@90 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x90&gt;;</div><div class='add'>+				label = "vdd_2p5";</div><div class='add'>+				gw,voltage-divider-ohms = &lt;10000 10000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@92 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x92&gt;;</div><div class='add'>+				label = "vdd_3p3";</div><div class='add'>+				gw,voltage-divider-ohms = &lt;10000 10000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@98 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x98&gt;;</div><div class='add'>+				label = "vdd_0p95";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@9a {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x9a&gt;;</div><div class='add'>+				label = "vdd_1p8";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@a2 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0xa2&gt;;</div><div class='add'>+				label = "vdd_gsc";</div><div class='add'>+				gw,voltage-divider-ohms = &lt;10000 10000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		fan-controller@0 {</div><div class='add'>+			compatible = "gw,gsc-fan";</div><div class='add'>+			reg = &lt;0x0a&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio: gpio@23 {</div><div class='add'>+		compatible = "nxp,pca9555";</div><div class='add'>+		reg = &lt;0x23&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gsc&gt;;</div><div class='add'>+		interrupts = &lt;4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@50 {</div><div class='add'>+		compatible = "atmel,24c02";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@51 {</div><div class='add'>+		compatible = "atmel,24c02";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@52 {</div><div class='add'>+		compatible = "atmel,24c02";</div><div class='add'>+		reg = &lt;0x52&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@53 {</div><div class='add'>+		compatible = "atmel,24c02";</div><div class='add'>+		reg = &lt;0x53&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gsc_rtc: rtc@68 {</div><div class='add'>+		compatible = "dallas,ds1672";</div><div class='add'>+		reg = &lt;0x68&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmic@69 {</div><div class='add'>+		compatible = "mps,mp5416";</div><div class='add'>+		reg = &lt;0x69&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			/* vdd_0p95: DRAM/GPU/VPU */</div><div class='add'>+			buck1 {</div><div class='add'>+				regulator-name = "buck1";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+				regulator-min-microamp = &lt;3800000&gt;;</div><div class='add'>+				regulator-max-microamp = &lt;6800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* vdd_soc */</div><div class='add'>+			buck2 {</div><div class='add'>+				regulator-name = "buck2";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-min-microamp = &lt;2200000&gt;;</div><div class='add'>+				regulator-max-microamp = &lt;5200000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* vdd_arm */</div><div class='add'>+			buck3_reg: buck3 {</div><div class='add'>+				regulator-name = "buck3";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+				regulator-min-microamp = &lt;3800000&gt;;</div><div class='add'>+				regulator-max-microamp = &lt;6800000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* vdd_1p8 */</div><div class='add'>+			buck4 {</div><div class='add'>+				regulator-name = "buck4";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-min-microamp = &lt;2200000&gt;;</div><div class='add'>+				regulator-max-microamp = &lt;5200000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* nvcc_snvs_1p8 */</div><div class='add'>+			ldo1 {</div><div class='add'>+				regulator-name = "ldo1";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* vdd_snvs_0p8 */</div><div class='add'>+			ldo2 {</div><div class='add'>+				regulator-name = "ldo2";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* vdd_0p9 */</div><div class='add'>+			ldo3 {</div><div class='add'>+				regulator-name = "ldo3";</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* vdd_1p8 */</div><div class='add'>+			ldo4 {</div><div class='add'>+				regulator-name = "ldo4";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c2_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	eeprom@52 {</div><div class='add'>+		compatible = "atmel,24c32";</div><div class='add'>+		reg = &lt;0x52&gt;;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* console */</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* eMMC */</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_USDHC3&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_fec1: fec1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3</div><div class='add'>+			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x0</div><div class='add'>+			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f</div><div class='add'>+			MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0			0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gsc: gscgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6	0x159</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1_gpio: i2c1gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14	0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15	0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2_gpio: i2c2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16	0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17	0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140</div><div class='add'>+			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x190</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x190</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x194</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x194</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x196</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x196</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx-0x.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx-0x.dts<br/>new file mode 100644<br/>index 000000000000..3f88c4ad5716<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx-0x.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx-0x.dts</a></div><div class='hunk'>@@ -0,0 +1,19 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2020 Gateworks Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mm.dtsi"</div><div class='add'>+#include "imx8mm-venice-gw700x.dtsi"</div><div class='add'>+#include "imx8mm-venice-gw71xx.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Gateworks Venice GW71xx-0x i.MX8MM Development Kit";</div><div class='add'>+	compatible = "gw,imx8mm-gw71xx-0x", "fsl,imx8mm";</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart2;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi<br/>new file mode 100644<br/>index 000000000000..429be2bab8a2<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi</a></div><div class='hunk'>@@ -0,0 +1,233 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2020 Gateworks Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/phy/phy-imx8-pcie.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		usb0 = &amp;usbotg1;</div><div class='add'>+		usb1 = &amp;usbotg2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	led-controller {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_leds&gt;;</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio5 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "on";</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio5 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_refclk: pcie0-refclk {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;100000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pps {</div><div class='add'>+		compatible = "pps-gpio";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pps&gt;;</div><div class='add'>+		gpios = &lt;&amp;gpio1 15 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_spi2&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 13 GPIO_ACTIVE_LOW&gt;,</div><div class='add'>+		   &lt;&amp;gpio1 10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	tpm@1 {</div><div class='add'>+		compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";</div><div class='add'>+		reg = &lt;0x1&gt;;</div><div class='add'>+		spi-max-frequency = &lt;36000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	gpio-line-names = "", "", "", "", "", "", "pci_usb_sel", "dio0",</div><div class='add'>+		"", "dio1", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	gpio-line-names = "", "", "", "dio2", "dio3", "", "", "pci_wdis#",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	accelerometer@19 {</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_accel&gt;;</div><div class='add'>+		compatible = "st,lis2de12";</div><div class='add'>+		reg = &lt;0x19&gt;;</div><div class='add'>+		st,drdy-int-pin = &lt;1&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;5 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* off-board header */</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	fsl,refclk-pad-mode = &lt;IMX8_PCIE_REFCLK_PAD_INPUT&gt;;</div><div class='add'>+	fsl,clkreq-unsupported;</div><div class='add'>+	clocks = &lt;&amp;pcie0_refclk&gt;;</div><div class='add'>+	clock-names = "ref";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie0&gt;;</div><div class='add'>+	reset-gpio = &lt;&amp;gpio4 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	clocks = &lt;&amp;clk IMX8MM_CLK_PCIE1_ROOT&gt;, &lt;&amp;pcie0_refclk&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX8MM_CLK_PCIE1_AUX&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_PCIE1_AUX&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MM_CLK_PCIE1_CTRL&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;10000000&gt;, &lt;250000000&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL2_50M&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MM_SYS_PLL2_250M&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* GPS */</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* off-board header */</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usbotg1&gt;;</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	over-current-active-low;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg2 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	disable-over-current;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hog&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl_hog: hoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3		0x40000041 /* PLUG_TEST */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6	0x40000041 /* PCI_USBSEL */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7	0x40000041 /* PCIE_WDIS# */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7	0x40000041 /* DIO0 */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9	0x40000041 /* DIO1 */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3	0x40000041 /* DIO2 */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4	0x40000041 /* DIO2 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_accel: accelgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5	0x159</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio_leds: gpioledgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5	0x19</div><div class='add'>+			MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4		0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie0: pcie0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pps: ppsgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_spi2: spi2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0xd6</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0xd6</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO	0xd6</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13	0xd6</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10	0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140</div><div class='add'>+			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: uart3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX	0x140</div><div class='add'>+			MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usbotg1: usbotg1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x141</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-imx219.dtso b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-imx219.dtso<br/>new file mode 100644<br/>index 000000000000..c09aa80d2ba2<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-imx219.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-imx219.dtso</a></div><div class='hunk'>@@ -0,0 +1,109 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Gateworks Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+</div><div class='add'>+#include "imx8mm-pinfunc.h"</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+&amp;{/} {</div><div class='add'>+	compatible = "gw,imx8mm-gw72xx-0x", "fsl,imx8mm";</div><div class='add'>+</div><div class='add'>+	reg_vana: regulator-2p8v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "2P8V";</div><div class='add'>+		regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vddl: regulator-1p2v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "1P2V";</div><div class='add'>+		regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_cam: regulator-cam {</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_cam&gt;;</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "reg_cam";</div><div class='add'>+		gpio = &lt;&amp;gpio1 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cam24m: cam24m {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+		clock-output-names = "cam24m";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;csi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	imx219: sensor@10 {</div><div class='add'>+		compatible = "sony,imx219";</div><div class='add'>+		reg = &lt;0x10&gt;;</div><div class='add'>+		clocks = &lt;&amp;cam24m&gt;;</div><div class='add'>+		VDIG-supply = &lt;&amp;reg_cam&gt;;</div><div class='add'>+		VANA-supply = &lt;&amp;reg_vana&gt;;</div><div class='add'>+		VDDL-supply = &lt;&amp;reg_vddl&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			/* MIPI CSI-2 bus endpoint */</div><div class='add'>+			imx219_to_mipi_csi2: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;imx8mm_mipi_csi_in&gt;;</div><div class='add'>+				clock-lanes = &lt;0&gt;;</div><div class='add'>+				data-lanes = &lt;1 2&gt;;</div><div class='add'>+				link-frequencies = /bits/ 64 &lt;456000000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_csi {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		port@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			imx8mm_mipi_csi_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;imx219_to_mipi_csi2&gt;;</div><div class='add'>+				data-lanes = &lt;1 2&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			imx8mm_mipi_csi_out: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;csi_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_reg_cam: regcamgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rpidsi.dtso b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rpidsi.dtso<br/>new file mode 100644<br/>index 000000000000..e0768d408c3b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rpidsi.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rpidsi.dtso</a></div><div class='hunk'>@@ -0,0 +1,90 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Gateworks Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+</div><div class='add'>+#include "imx8mm-pinfunc.h"</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+&amp;{/} {</div><div class='add'>+	compatible = "gw,imx8mm-gw73xx-0x", "fsl,imx8mm";</div><div class='add'>+</div><div class='add'>+	panel {</div><div class='add'>+		compatible = "powertip,ph800480t013-idf02";</div><div class='add'>+		power-supply = &lt;&amp;attiny&gt;;</div><div class='add'>+		backlight = &lt;&amp;attiny&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			panel_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;bridge_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	attiny: regulator@45 {</div><div class='add'>+		compatible = "raspberrypi,7inch-touchscreen-panel-regulator";</div><div class='add'>+		reg = &lt;0x45&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_dsi {</div><div class='add'>+	samsung,burst-clock-frequency = &lt;891000000&gt;;</div><div class='add'>+	samsung,esc-clock-frequency = &lt;54000000&gt;;</div><div class='add'>+	samsung,pll-clock-frequency = &lt;27000000&gt;;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bridge@0 {</div><div class='add'>+		compatible = "toshiba,tc358762";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		vddc-supply = &lt;&amp;attiny&gt;;</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				bridge_in: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;dsi_out&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				bridge_out: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;panel_in&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			dsi_out: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;bridge_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs232-rts.dtso b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs232-rts.dtso<br/>new file mode 100644<br/>index 000000000000..bb2056746f8c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs232-rts.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs232-rts.dtso</a></div><div class='hunk'>@@ -0,0 +1,48 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Gateworks Corporation</div><div class='add'>+ *</div><div class='add'>+ * GW72xx RS232 with RTS/CTS hardware flow control:</div><div class='add'>+ *  - GPIO4_0 rs485_en needs to be driven low (in-active)</div><div class='add'>+ *  - UART4_TX becomes RTS</div><div class='add'>+ *  - UART4_RX becomes CTS</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+</div><div class='add'>+#include "imx8mm-pinfunc.h"</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	rs485-en-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		output-low;</div><div class='add'>+		line-name = "rs485_en";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	rts-gpios = &lt;&amp;gpio5 29 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	cts-gpios = &lt;&amp;gpio5 28 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX     0x140</div><div class='add'>+			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX     0x140</div><div class='add'>+			MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29	0x140</div><div class='add'>+			MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs422.dtso b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs422.dtso<br/>new file mode 100644<br/>index 000000000000..45ac8bdce869<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs422.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs422.dtso</a></div><div class='hunk'>@@ -0,0 +1,57 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Gateworks Corporation</div><div class='add'>+ *</div><div class='add'>+ * GW72xx RS422 (RS485 full duplex):</div><div class='add'>+ *  - GPIO1_0 rs485_term selects on-chip termination</div><div class='add'>+ *  - GPIO4_0 rs485_en needs to be driven high (active)</div><div class='add'>+ *  - GPIO4_2 rs485_hd needs to be driven low (in-active)</div><div class='add'>+ *  - UART4_TX is DE for RS485 transmitter</div><div class='add'>+ *  - RS485_EN needs to be pulled high</div><div class='add'>+ *  - RS485_HALF needs to be low</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+</div><div class='add'>+#include "imx8mm-pinfunc.h"</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	rs485-en-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		output-high;</div><div class='add'>+		line-name = "rs485_en";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rs485-hd-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		output-low;</div><div class='add'>+		line-name = "rs485_hd";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	rts-gpios = &lt;&amp;gpio5 29 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	linux,rs485-enabled-at-boot-time;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX     0x140</div><div class='add'>+			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX     0x140</div><div class='add'>+			MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs485.dtso b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs485.dtso<br/>new file mode 100644<br/>index 000000000000..30aa620d7004<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs485.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs485.dtso</a></div><div class='hunk'>@@ -0,0 +1,57 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Gateworks Corporation</div><div class='add'>+ *</div><div class='add'>+ * GW72xx RS485 HD:</div><div class='add'>+ *  - GPIO1_0 rs485_term selects on-chip termination</div><div class='add'>+ *  - GPIO4_0 rs485_en needs to be driven high (active)</div><div class='add'>+ *  - GPIO4_2 rs485_hd needs to be driven high (active)</div><div class='add'>+ *  - UART4_TX is DE for RS485 transmitter</div><div class='add'>+ *  - RS485_EN needs to be pulled high</div><div class='add'>+ *  - RS485_HALF needs to be pulled high</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+</div><div class='add'>+#include "imx8mm-pinfunc.h"</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	rs485-en-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		output-high;</div><div class='add'>+		line-name = "rs485_en";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rs485-hd-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		output-high;</div><div class='add'>+		line-name = "rs485_hd";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	rts-gpios = &lt;&amp;gpio5 29 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	linux,rs485-enabled-at-boot-time;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX     0x140</div><div class='add'>+			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX     0x140</div><div class='add'>+			MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x.dts<br/>new file mode 100644<br/>index 000000000000..641be3af989d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x.dts</a></div><div class='hunk'>@@ -0,0 +1,19 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2020 Gateworks Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mm.dtsi"</div><div class='add'>+#include "imx8mm-venice-gw700x.dtsi"</div><div class='add'>+#include "imx8mm-venice-gw72xx.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Gateworks Venice GW72xx-0x i.MX8MM Development Kit";</div><div class='add'>+	compatible = "gw,imx8mm-gw72xx-0x", "fsl,imx8mm";</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart2;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi<br/>new file mode 100644<br/>index 000000000000..266038fbbef9<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi</a></div><div class='hunk'>@@ -0,0 +1,394 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2020 Gateworks Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/phy/phy-imx8-pcie.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet1 = &amp;eth1;</div><div class='add'>+		usb0 = &amp;usbotg1;</div><div class='add'>+		usb1 = &amp;usbotg2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	led-controller {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_leds&gt;;</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio5 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "on";</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio5 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_refclk: pcie0-refclk {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;100000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pps {</div><div class='add'>+		compatible = "pps-gpio";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pps&gt;;</div><div class='add'>+		gpios = &lt;&amp;gpio1 15 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3p3v: regulator-3p3v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "3P3V";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb_otg1_vbus: regulator-usb-otg1 {</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usb1_en&gt;;</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "usb_otg1_vbus";</div><div class='add'>+		gpio = &lt;&amp;gpio1 12 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb_otg2_vbus: regulator-usb-otg2 {</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usb2_en&gt;;</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "usb_otg2_vbus";</div><div class='add'>+		gpio = &lt;&amp;gpio1 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* off-board header */</div><div class='add'>+&amp;ecspi2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_spi2&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 13 GPIO_ACTIVE_LOW&gt;,</div><div class='add'>+		   &lt;&amp;gpio1 10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	tpm@1 {</div><div class='add'>+		compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";</div><div class='add'>+		reg = &lt;0x1&gt;;</div><div class='add'>+		spi-max-frequency = &lt;36000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	gpio-line-names = "rs485_term", "mipi_gpio4", "", "",</div><div class='add'>+		"", "", "pci_usb_sel", "dio0",</div><div class='add'>+		"", "dio1", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	gpio-line-names = "rs485_en", "mipi_gpio3", "rs485_hd", "mipi_gpio2",</div><div class='add'>+		"mipi_gpio1", "", "", "pci_wdis#",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	accelerometer@19 {</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_accel&gt;;</div><div class='add'>+		compatible = "st,lis2de12";</div><div class='add'>+		reg = &lt;0x19&gt;;</div><div class='add'>+		st,drdy-int-pin = &lt;1&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;5 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* off-board header */</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	fsl,refclk-pad-mode = &lt;IMX8_PCIE_REFCLK_PAD_INPUT&gt;;</div><div class='add'>+	fsl,clkreq-unsupported;</div><div class='add'>+	clocks = &lt;&amp;pcie0_refclk&gt;;</div><div class='add'>+	clock-names = "ref";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie0&gt;;</div><div class='add'>+	reset-gpio = &lt;&amp;gpio4 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	clocks = &lt;&amp;clk IMX8MM_CLK_PCIE1_ROOT&gt;, &lt;&amp;pcie0_refclk&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX8MM_CLK_PCIE1_AUX&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_PCIE1_AUX&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MM_CLK_PCIE1_CTRL&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;10000000&gt;, &lt;250000000&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL2_50M&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MM_SYS_PLL2_250M&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pcie@0,0 {</div><div class='add'>+		reg = &lt;0x0000 0 0 0 0&gt;;</div><div class='add'>+		device_type = "pci";</div><div class='add'>+		#address-cells = &lt;3&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		pcie@0,0 {</div><div class='add'>+			reg = &lt;0x0000 0 0 0 0&gt;;</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			pcie@3,0 {</div><div class='add'>+				reg = &lt;0x1800 0 0 0 0&gt;;</div><div class='add'>+				device_type = "pci";</div><div class='add'>+				#address-cells = &lt;3&gt;;</div><div class='add'>+				#size-cells = &lt;2&gt;;</div><div class='add'>+				ranges;</div><div class='add'>+</div><div class='add'>+				eth1: ethernet@0,0 {</div><div class='add'>+					reg = &lt;0x0000 0 0 0 0&gt;;</div><div class='add'>+					#address-cells = &lt;3&gt;;</div><div class='add'>+					#size-cells = &lt;2&gt;;</div><div class='add'>+					ranges;</div><div class='add'>+</div><div class='add'>+					local-mac-address = [00 00 00 00 00 00];</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* off-board header */</div><div class='add'>+&amp;sai3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai3&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_SAI3&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;24576000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* GPS */</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* off-board header */</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* RS232 */</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	over-current-active-low;</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usb_otg1_vbus&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg2 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	disable-over-current;</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usb_otg2_vbus&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* microSD */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hog&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl_hog: hoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3		0x40000041 /* PLUG_TEST */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6	0x40000041 /* PCI_USBSEL */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7	0x40000041 /* PCIE_WDIS# */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7	0x40000041 /* DIO0 */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9	0x40000041 /* DIO1 */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0	0x40000104 /* RS485_TERM */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0	0x40000104 /* RS485 */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2	0x40000104 /* RS485_HALF */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_accel: accelgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5	0x159</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio_leds: gpioledgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5	0x19</div><div class='add'>+			MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4		0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie0: pcie0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pps: ppsgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usb1_en: regusb1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x41</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usb2_en: regusb2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai3: sai3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0	0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_spi2: spi2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0xd6</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0xd6</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO	0xd6</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13	0xd6</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10	0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140</div><div class='add'>+			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: uart3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX	0x140</div><div class='add'>+			MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart4: uart4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX	0x140</div><div class='add'>+			MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12	0x1c4</div><div class='add'>+			MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-imx219.dtso b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-imx219.dtso<br/>new file mode 100644<br/>index 000000000000..cfc014eb038d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-imx219.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-imx219.dtso</a></div><div class='hunk'>@@ -0,0 +1,109 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Gateworks Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+</div><div class='add'>+#include "imx8mm-pinfunc.h"</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+&amp;{/} {</div><div class='add'>+	compatible = "gw,imx8mm-gw73xx-0x", "fsl,imx8mm";</div><div class='add'>+</div><div class='add'>+	reg_vana: regulator-2p8v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "2P8V";</div><div class='add'>+		regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vddl: regulator-1p2v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "1P2V";</div><div class='add'>+		regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_cam: regulator-cam {</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_cam&gt;;</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "reg_cam";</div><div class='add'>+		gpio = &lt;&amp;gpio1 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cam24m: cam24m {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+		clock-output-names = "cam24m";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;csi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	imx219: sensor@10 {</div><div class='add'>+		compatible = "sony,imx219";</div><div class='add'>+		reg = &lt;0x10&gt;;</div><div class='add'>+		clocks = &lt;&amp;cam24m&gt;;</div><div class='add'>+		VDIG-supply = &lt;&amp;reg_cam&gt;;</div><div class='add'>+		VANA-supply = &lt;&amp;reg_vana&gt;;</div><div class='add'>+		VDDL-supply = &lt;&amp;reg_vddl&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			/* MIPI CSI-2 bus endpoint */</div><div class='add'>+			imx219_to_mipi_csi2: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;imx8mm_mipi_csi_in&gt;;</div><div class='add'>+				clock-lanes = &lt;0&gt;;</div><div class='add'>+				data-lanes = &lt;1 2&gt;;</div><div class='add'>+				link-frequencies = /bits/ 64 &lt;456000000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_csi {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		port@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			imx8mm_mipi_csi_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;imx219_to_mipi_csi2&gt;;</div><div class='add'>+				data-lanes = &lt;1 2&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			imx8mm_mipi_csi_out: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;csi_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_reg_cam: regcamgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rpidsi.dtso b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rpidsi.dtso<br/>new file mode 100644<br/>index 000000000000..e0768d408c3b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rpidsi.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rpidsi.dtso</a></div><div class='hunk'>@@ -0,0 +1,90 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Gateworks Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+</div><div class='add'>+#include "imx8mm-pinfunc.h"</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+&amp;{/} {</div><div class='add'>+	compatible = "gw,imx8mm-gw73xx-0x", "fsl,imx8mm";</div><div class='add'>+</div><div class='add'>+	panel {</div><div class='add'>+		compatible = "powertip,ph800480t013-idf02";</div><div class='add'>+		power-supply = &lt;&amp;attiny&gt;;</div><div class='add'>+		backlight = &lt;&amp;attiny&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			panel_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;bridge_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	attiny: regulator@45 {</div><div class='add'>+		compatible = "raspberrypi,7inch-touchscreen-panel-regulator";</div><div class='add'>+		reg = &lt;0x45&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_dsi {</div><div class='add'>+	samsung,burst-clock-frequency = &lt;891000000&gt;;</div><div class='add'>+	samsung,esc-clock-frequency = &lt;54000000&gt;;</div><div class='add'>+	samsung,pll-clock-frequency = &lt;27000000&gt;;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bridge@0 {</div><div class='add'>+		compatible = "toshiba,tc358762";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		vddc-supply = &lt;&amp;attiny&gt;;</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				bridge_in: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;dsi_out&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				bridge_out: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;panel_in&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			dsi_out: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;bridge_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs232-rts.dtso b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs232-rts.dtso<br/>new file mode 100644<br/>index 000000000000..b1a9f35e1dfa<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs232-rts.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs232-rts.dtso</a></div><div class='hunk'>@@ -0,0 +1,48 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Gateworks Corporation</div><div class='add'>+ *</div><div class='add'>+ * GW73xx RS232 with RTS/CTS hardware flow control:</div><div class='add'>+ *  - GPIO4_0 rs485_en needs to be driven low (in-active)</div><div class='add'>+ *  - UART4_TX becomes RTS</div><div class='add'>+ *  - UART4_RX becomes CTS</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+</div><div class='add'>+#include "imx8mm-pinfunc.h"</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	rs485-en-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		output-low;</div><div class='add'>+		line-name = "rs485_en";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	rts-gpios = &lt;&amp;gpio5 29 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	cts-gpios = &lt;&amp;gpio5 28 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX     0x140</div><div class='add'>+			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX     0x140</div><div class='add'>+			MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29	0x140</div><div class='add'>+			MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs422.dtso b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs422.dtso<br/>new file mode 100644<br/>index 000000000000..44ebc0a58c51<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs422.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs422.dtso</a></div><div class='hunk'>@@ -0,0 +1,57 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021 Gateworks Corporation</div><div class='add'>+ *</div><div class='add'>+ * GW73xx RS422 (RS485 full duplex):</div><div class='add'>+ *  - GPIO1_0 rs485_term selects on-chip termination</div><div class='add'>+ *  - GPIO4_0 rs485_en needs to be driven high (active)</div><div class='add'>+ *  - GPIO4_2 rs485_hd needs to be driven low (in-active)</div><div class='add'>+ *  - UART4_TX is DE for RS485 transmitter</div><div class='add'>+ *  - RS485_EN needs to be pulled high</div><div class='add'>+ *  - RS485_HALF needs to be low</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+</div><div class='add'>+#include "imx8mm-pinfunc.h"</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	rs485-en-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		output-high;</div><div class='add'>+		line-name = "rs485_en";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rs485-hd-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		output-low;</div><div class='add'>+		line-name = "rs485_hd";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	rts-gpios = &lt;&amp;gpio5 29 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	linux,rs485-enabled-at-boot-time;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX     0x140</div><div class='add'>+			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX     0x140</div><div class='add'>+			MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs485.dtso b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs485.dtso<br/>new file mode 100644<br/>index 000000000000..2f8a7ac40873<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs485.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs485.dtso</a></div><div class='hunk'>@@ -0,0 +1,57 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021 Gateworks Corporation</div><div class='add'>+ *</div><div class='add'>+ * GW73xx RS485 HD:</div><div class='add'>+ *  - GPIO1_0 rs485_term selects on-chip termination</div><div class='add'>+ *  - GPIO4_0 rs485_en needs to be driven high (active)</div><div class='add'>+ *  - GPIO4_2 rs485_hd needs to be driven high (active)</div><div class='add'>+ *  - UART4_TX is DE for RS485 transmitter</div><div class='add'>+ *  - RS485_EN needs to be pulled high</div><div class='add'>+ *  - RS485_HALF needs to be pulled high</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+</div><div class='add'>+#include "imx8mm-pinfunc.h"</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	rs485-en-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		output-high;</div><div class='add'>+		line-name = "rs485_en";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rs485-hd-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		output-high;</div><div class='add'>+		line-name = "rs485_hd";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	rts-gpios = &lt;&amp;gpio5 29 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	linux,rs485-enabled-at-boot-time;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX     0x140</div><div class='add'>+			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX     0x140</div><div class='add'>+			MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x.dts<br/>new file mode 100644<br/>index 000000000000..6905437ff281<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x.dts</a></div><div class='hunk'>@@ -0,0 +1,19 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2020 Gateworks Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mm.dtsi"</div><div class='add'>+#include "imx8mm-venice-gw700x.dtsi"</div><div class='add'>+#include "imx8mm-venice-gw73xx.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Gateworks Venice GW73xx-0x i.MX8MM Development Kit";</div><div class='add'>+	compatible = "gw,imx8mm-gw73xx-0x", "fsl,imx8mm";</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart2;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi<br/>new file mode 100644<br/>index 000000000000..2aa6c1090fc7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi</a></div><div class='hunk'>@@ -0,0 +1,456 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2020 Gateworks Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/phy/phy-imx8-pcie.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet1 = &amp;eth1;</div><div class='add'>+		usb0 = &amp;usbotg1;</div><div class='add'>+		usb1 = &amp;usbotg2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	led-controller {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_leds&gt;;</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio5 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "on";</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio5 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_refclk: pcie0-refclk {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;100000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pps {</div><div class='add'>+		compatible = "pps-gpio";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pps&gt;;</div><div class='add'>+		gpios = &lt;&amp;gpio1 15 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_1p8v: regulator-1p8v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "1P8V";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3p3v: regulator-3p3v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "3P3V";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb_otg1_vbus: regulator-usb-otg1 {</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usb1_en&gt;;</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "usb_otg1_vbus";</div><div class='add'>+		gpio = &lt;&amp;gpio1 12 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb_otg2_vbus: regulator-usb-otg2 {</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usb2_en&gt;;</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "usb_otg2_vbus";</div><div class='add'>+		gpio = &lt;&amp;gpio1 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_wifi_en: regulator-wifi-en {</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_wl&gt;;</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "wl";</div><div class='add'>+		gpio = &lt;&amp;gpio1 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		startup-delay-us = &lt;100&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* off-board header */</div><div class='add'>+&amp;ecspi2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_spi2&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 13 GPIO_ACTIVE_LOW&gt;,</div><div class='add'>+		   &lt;&amp;gpio1 10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	tpm@1 {</div><div class='add'>+		compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";</div><div class='add'>+		reg = &lt;0x1&gt;;</div><div class='add'>+		spi-max-frequency = &lt;36000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	gpio-line-names = "rs485_term", "mipi_gpio4", "", "",</div><div class='add'>+		"", "", "pci_usb_sel", "dio0",</div><div class='add'>+		"", "dio1", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	gpio-line-names = "rs485_en", "mipi_gpio3", "rs485_hd", "mipi_gpio2",</div><div class='add'>+		"mipi_gpio1", "", "", "pci_wdis#",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	accelerometer@19 {</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_accel&gt;;</div><div class='add'>+		compatible = "st,lis2de12";</div><div class='add'>+		reg = &lt;0x19&gt;;</div><div class='add'>+		st,drdy-int-pin = &lt;1&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;5 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* off-board header */</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	fsl,refclk-pad-mode = &lt;IMX8_PCIE_REFCLK_PAD_INPUT&gt;;</div><div class='add'>+	fsl,clkreq-unsupported;</div><div class='add'>+	clocks = &lt;&amp;pcie0_refclk&gt;;</div><div class='add'>+	clock-names = "ref";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie0&gt;;</div><div class='add'>+	reset-gpio = &lt;&amp;gpio4 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	clocks = &lt;&amp;clk IMX8MM_CLK_PCIE1_ROOT&gt;, &lt;&amp;pcie0_refclk&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX8MM_CLK_PCIE1_AUX&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_PCIE1_AUX&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MM_CLK_PCIE1_CTRL&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;10000000&gt;, &lt;250000000&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL2_50M&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MM_SYS_PLL2_250M&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pcie@0,0 {</div><div class='add'>+		reg = &lt;0x0000 0 0 0 0&gt;;</div><div class='add'>+		device_type = "pci";</div><div class='add'>+		#address-cells = &lt;3&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		pcie@0,0 {</div><div class='add'>+			reg = &lt;0x0000 0 0 0 0&gt;;</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			pcie@4,0 {</div><div class='add'>+				reg = &lt;0x2000 0 0 0 0&gt;;</div><div class='add'>+				device_type = "pci";</div><div class='add'>+				#address-cells = &lt;3&gt;;</div><div class='add'>+				#size-cells = &lt;2&gt;;</div><div class='add'>+				ranges;</div><div class='add'>+</div><div class='add'>+				eth1: ethernet@0,0 {</div><div class='add'>+					reg = &lt;0x0000 0 0 0 0&gt;;</div><div class='add'>+					#address-cells = &lt;3&gt;;</div><div class='add'>+					#size-cells = &lt;2&gt;;</div><div class='add'>+					ranges;</div><div class='add'>+</div><div class='add'>+					local-mac-address = [00 00 00 00 00 00];</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* off-board header */</div><div class='add'>+&amp;sai3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai3&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_SAI3&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;24576000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* GPS */</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* bluetooth HCI */</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;, &lt;&amp;pinctrl_bten&gt;;</div><div class='add'>+	cts-gpios = &lt;&amp;gpio5 8 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	rts-gpios = &lt;&amp;gpio5 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "brcm,bcm4330-bt";</div><div class='add'>+		shutdown-gpios = &lt;&amp;gpio1 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* RS232 */</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	over-current-active-low;</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usb_otg1_vbus&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg2 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	disable-over-current;</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usb_otg2_vbus&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SDIO WiFi */</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_wifi_en&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* microSD */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hog&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl_hog: hoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3		0x40000041 /* PLUG_TEST */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6	0x40000041 /* PCI_USBSEL */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7	0x40000041 /* PCIE_WDIS# */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7	0x40000041 /* DIO0 */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9	0x40000041 /* DIO1 */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0	0x40000104 /* RS485_TERM */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0	0x40000104 /* RS485 */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2	0x40000104 /* RS485_HALF */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_accel: accelgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5	0x159</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_bten: btengrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio_leds: gpioledgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5	0x19</div><div class='add'>+			MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4		0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie0: pcie0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pps: ppsgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_wl: regwlgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usb1_en: regusb1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x41</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usb2_en: regusb2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai3: sai3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0	0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_spi2: spi2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0xd6</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0xd6</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO	0xd6</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13	0xd6</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10	0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140</div><div class='add'>+			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: uart3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX	0x140</div><div class='add'>+			MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX	0x140</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8	0x140</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart4: uart4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX	0x140</div><div class='add'>+			MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x190</div><div class='add'>+			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12	0x1c4</div><div class='add'>+			MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw75xx-0x.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw75xx-0x.dts<br/>new file mode 100644<br/>index 000000000000..04f06a55da5c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-venice-gw75xx-0x.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-venice-gw75xx-0x.dts</a></div><div class='hunk'>@@ -0,0 +1,28 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Gateworks Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mm.dtsi"</div><div class='add'>+#include "imx8mm-venice-gw700x.dtsi"</div><div class='add'>+#include "imx8mm-venice-gw75xx.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Gateworks Venice GW75xx-0x i.MX8MM Development Kit";</div><div class='add'>+	compatible = "gateworks,imx8mm-gw75xx-0x", "fsl,imx8mm";</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart2;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Disable SOM interfaces not used on baseboard */</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw75xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw75xx.dtsi<br/>new file mode 100644<br/>index 000000000000..53004c4a13aa<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-venice-gw75xx.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-venice-gw75xx.dtsi</a></div><div class='hunk'>@@ -0,0 +1,319 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Gateworks Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/phy/phy-imx8-pcie.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	led-controller {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_leds&gt;;</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio4 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "on";</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio4 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_refclk: clock-pcie0 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;100000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pps {</div><div class='add'>+		compatible = "pps-gpio";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pps&gt;;</div><div class='add'>+		gpios = &lt;&amp;gpio4 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb2_vbus: regulator-usb2-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usb2_en&gt;;</div><div class='add'>+		regulator-name = "usb2_vbus";</div><div class='add'>+		gpio = &lt;&amp;gpio1 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usdhc2_vmmc&gt;;</div><div class='add'>+		regulator-name = "SD2_3P3V";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio2 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* off-board header */</div><div class='add'>+&amp;ecspi2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_spi2&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 13 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "gpioa", "gpiob", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"", "", "", "pci_usb_sel",</div><div class='add'>+		"", "", "", "pci_wdis#",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio5 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"gpioc", "gpiod", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	accelerometer@19 {</div><div class='add'>+		compatible = "st,lis2de12";</div><div class='add'>+		reg = &lt;0x19&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_accel&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio5&gt;;</div><div class='add'>+		interrupts = &lt;8 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		st,drdy-int-pin = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@52 {</div><div class='add'>+		compatible = "atmel,24c32";</div><div class='add'>+		reg = &lt;0x52&gt;;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* off-board header */</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	fsl,refclk-pad-mode = &lt;IMX8_PCIE_REFCLK_PAD_INPUT&gt;;</div><div class='add'>+	fsl,clkreq-unsupported;</div><div class='add'>+	clocks = &lt;&amp;pcie0_refclk&gt;;</div><div class='add'>+	clock-names = "ref";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie0&gt;;</div><div class='add'>+	reset-gpio = &lt;&amp;gpio4 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* GPS */</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB1 - Type C front panel SINK port J14 */</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	dr_mode = "peripheral";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB2 4-port USB3.0 HUB:</div><div class='add'>+ *  P1 - USBC connector (host only)</div><div class='add'>+ *  P2 - USB2 test connector</div><div class='add'>+ *  P3 - miniPCIe full card</div><div class='add'>+ *  P4 - miniPCIe half card</div><div class='add'>+ */</div><div class='add'>+&amp;usbotg2 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usb2_vbus&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* microSD */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hog&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl_hog: hoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13	0x40000040 /* GPIOA */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14	0x40000040 /* GPIOB */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3	0x40000106 /* PCI_USBSEL */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7	0x40000106 /* PCIE_WDIS# */</div><div class='add'>+			MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5	0x40000040 /* GPIOD */</div><div class='add'>+			MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4		0x40000040 /* GPIOC */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_accel: accelgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8	0x159</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio_leds: gpioledgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0	0x6	/* LEDG */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2	0x6	/* LEDR */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c2</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c2</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie0: pciegrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6	0x106</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pps: ppsgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5	0x106</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usb2_en: regusb2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8	0x6	/* USBHUB_RST# (ext p/u) */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x40</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_spi2: spi2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0x140</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0x140</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO	0x140</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140</div><div class='add'>+			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0xc0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0xc0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0xc0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12	0x1c4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts<br/>new file mode 100644<br/>index 000000000000..272c2b223d16<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts</a></div><div class='hunk'>@@ -0,0 +1,1195 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2020 Gateworks Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/linux-event-codes.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/phy/phy-imx8-pcie.h&gt;</div><div class='add'>+</div><div class='add'>+#include "imx8mm.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Gateworks Venice GW7901 i.MX8MM board";</div><div class='add'>+	compatible = "gw,imx8mm-gw7901", "fsl,imx8mm";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;fec1;</div><div class='add'>+		ethernet1 = &amp;lan1;</div><div class='add'>+		ethernet2 = &amp;lan2;</div><div class='add'>+		ethernet3 = &amp;lan3;</div><div class='add'>+		ethernet4 = &amp;lan4;</div><div class='add'>+		rtc0 = &amp;gsc_rtc;</div><div class='add'>+		rtc1 = &amp;snvs_rtc;</div><div class='add'>+		usb0 = &amp;usbotg1;</div><div class='add'>+		usb1 = &amp;usbotg2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x40000000 0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		key-user-pb {</div><div class='add'>+			label = "user_pb";</div><div class='add'>+			gpios = &lt;&amp;gpio 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;BTN_0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-user-pb1x {</div><div class='add'>+			label = "user_pb1x";</div><div class='add'>+			linux,code = &lt;BTN_1&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gsc&gt;;</div><div class='add'>+			interrupts = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-erased {</div><div class='add'>+			label = "key_erased";</div><div class='add'>+			linux,code = &lt;BTN_2&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gsc&gt;;</div><div class='add'>+			interrupts = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-eeprom-wp {</div><div class='add'>+			label = "eeprom_wp";</div><div class='add'>+			linux,code = &lt;BTN_3&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gsc&gt;;</div><div class='add'>+			interrupts = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-tamper {</div><div class='add'>+			label = "tamper";</div><div class='add'>+			linux,code = &lt;BTN_4&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gsc&gt;;</div><div class='add'>+			interrupts = &lt;5&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		switch-hold {</div><div class='add'>+			label = "switch_hold";</div><div class='add'>+			linux,code = &lt;BTN_5&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gsc&gt;;</div><div class='add'>+			interrupts = &lt;7&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	led-controller {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			label = "led01_red";</div><div class='add'>+			gpios = &lt;&amp;leds_gpio 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			label = "led01_grn";</div><div class='add'>+			gpios = &lt;&amp;leds_gpio 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-2 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			label = "led02_red";</div><div class='add'>+			gpios = &lt;&amp;leds_gpio 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-3 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			label = "led02_grn";</div><div class='add'>+			gpios = &lt;&amp;leds_gpio 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-4 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			label = "led03_red";</div><div class='add'>+			gpios = &lt;&amp;leds_gpio 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-5 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			label = "led03_grn";</div><div class='add'>+			gpios = &lt;&amp;leds_gpio 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-6 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			label = "led04_red";</div><div class='add'>+			gpios = &lt;&amp;leds_gpio 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-7 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			label = "led04_grn";</div><div class='add'>+			gpios = &lt;&amp;leds_gpio 9 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-8 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			label = "led05_red";</div><div class='add'>+			gpios = &lt;&amp;leds_gpio 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-9 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			label = "led05_grn";</div><div class='add'>+			gpios = &lt;&amp;leds_gpio 11 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-a {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			label = "led06_red";</div><div class='add'>+			gpios = &lt;&amp;leds_gpio 12 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-b {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			label = "led06_grn";</div><div class='add'>+			gpios = &lt;&amp;leds_gpio 13 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_refclk: pcie0-refclk {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;100000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3p3v: regulator-3p3v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "3P3V";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	regulator-ioexp {</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_ioexp&gt;;</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "ioexp";</div><div class='add'>+		gpio = &lt;&amp;gpio4 21 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		startup-delay-us = &lt;100&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	regulator-isouart {</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_isouart&gt;;</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "iso_uart";</div><div class='add'>+		gpio = &lt;&amp;gpio1 13 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		startup-delay-us = &lt;100&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb2_vbus: regulator-usb2 {</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usb2&gt;;</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "usb_usb2_vbus";</div><div class='add'>+		gpio = &lt;&amp;gpio4 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_wifi: regulator-wifi {</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_wl&gt;;</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "wifi";</div><div class='add'>+		gpio = &lt;&amp;gpio3 25 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		startup-delay-us = &lt;100&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ddrc {</div><div class='add'>+	operating-points-v2 = &lt;&amp;ddrc_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+	ddrc_opp_table: opp-table {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		opp-25000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;25000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-100000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;100000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-750000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;750000000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;disp_blk_ctrl {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_spi1&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 9 GPIO_ACTIVE_LOW&gt;,</div><div class='add'>+		   &lt;&amp;gpio4 24 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;40000000&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	tpm@1 {</div><div class='add'>+		compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";</div><div class='add'>+		reg = &lt;0x1&gt;;</div><div class='add'>+		spi-max-frequency = &lt;36000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec1&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	local-mac-address = [00 00 00 00 00 00];</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	fixed-link {</div><div class='add'>+		speed = &lt;1000&gt;;</div><div class='add'>+		full-duplex;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	gpio-line-names = "uart1_rs422#", "", "", "uart1_rs485#",</div><div class='add'>+		"", "uart1_rs232#", "dig1_in", "dig1_out",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	gpio-line-names = "", "", "", "",</div><div class='add'>+		"dig1_ctl", "dig2_ctl", "uart3_rs232#", "uart3_rs422#",</div><div class='add'>+		"uart3_rs485#", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "uart4_rs485#", "", "sim1det#", "sim2det#", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio5 {</div><div class='add'>+	gpio-line-names = "", "", "", "dig2_out", "dig2_in", "sim2sel", "", "",</div><div class='add'>+		"", "", "uart4_rs232#", "", "", "uart4_rs422#", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu_2d {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu_3d {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c1_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	gsc: gsc@20 {</div><div class='add'>+		compatible = "gw,gsc";</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gsc&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;16 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		adc {</div><div class='add'>+			compatible = "gw,gsc-adc";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			channel@6 {</div><div class='add'>+				gw,mode = &lt;0&gt;;</div><div class='add'>+				reg = &lt;0x06&gt;;</div><div class='add'>+				label = "temp";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@8 {</div><div class='add'>+				gw,mode = &lt;3&gt;;</div><div class='add'>+				reg = &lt;0x08&gt;;</div><div class='add'>+				label = "vdd_bat";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@82 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x82&gt;;</div><div class='add'>+				label = "vin_aux1";</div><div class='add'>+				gw,voltage-divider-ohms = &lt;22100 1000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@84 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x84&gt;;</div><div class='add'>+				label = "vin_aux2";</div><div class='add'>+				gw,voltage-divider-ohms = &lt;22100 1000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@86 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x86&gt;;</div><div class='add'>+				label = "vdd_vin";</div><div class='add'>+				gw,voltage-divider-ohms = &lt;22100 1000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@88 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x88&gt;;</div><div class='add'>+				label = "vdd_3p3";</div><div class='add'>+				gw,voltage-divider-ohms = &lt;10000 10000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@8c {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x8c&gt;;</div><div class='add'>+				label = "vdd_2p5";</div><div class='add'>+				gw,voltage-divider-ohms = &lt;10000 10000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@8e {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x8e&gt;;</div><div class='add'>+				label = "vdd_0p95";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@90 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x90&gt;;</div><div class='add'>+				label = "vdd_soc";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@92 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x92&gt;;</div><div class='add'>+				label = "vdd_arm";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@98 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x98&gt;;</div><div class='add'>+				label = "vdd_1p8";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@9a {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x9a&gt;;</div><div class='add'>+				label = "vdd_1p2";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@9c {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x9c&gt;;</div><div class='add'>+				label = "vdd_dram";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@a2 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0xa2&gt;;</div><div class='add'>+				label = "vdd_gsc";</div><div class='add'>+				gw,voltage-divider-ohms = &lt;10000 10000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio: gpio@23 {</div><div class='add'>+		compatible = "nxp,pca9555";</div><div class='add'>+		reg = &lt;0x23&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gsc&gt;;</div><div class='add'>+		interrupts = &lt;4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@50 {</div><div class='add'>+		compatible = "atmel,24c02";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@51 {</div><div class='add'>+		compatible = "atmel,24c02";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@52 {</div><div class='add'>+		compatible = "atmel,24c02";</div><div class='add'>+		reg = &lt;0x52&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@53 {</div><div class='add'>+		compatible = "atmel,24c02";</div><div class='add'>+		reg = &lt;0x53&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gsc_rtc: rtc@68 {</div><div class='add'>+		compatible = "dallas,ds1672";</div><div class='add'>+		reg = &lt;0x68&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c2_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pmic@4b {</div><div class='add'>+		compatible = "rohm,bd71847";</div><div class='add'>+		reg = &lt;0x4b&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+		interrupts = &lt;20 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		rohm,reset-snvs-powered;</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clocks = &lt;&amp;osc_32k&gt;;</div><div class='add'>+		clock-output-names = "clk-32k-out";</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			/* vdd_soc: 0.805-0.900V (typ=0.8V) */</div><div class='add'>+			BUCK1 {</div><div class='add'>+				regulator-name = "buck1";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;1250&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* vdd_arm: 0.805-1.0V (typ=0.9V) */</div><div class='add'>+			buck2: BUCK2 {</div><div class='add'>+				regulator-name = "buck2";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;1250&gt;;</div><div class='add'>+				rohm,dvs-run-voltage = &lt;1000000&gt;;</div><div class='add'>+				rohm,dvs-idle-voltage = &lt;900000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* vdd_0p9: 0.805-1.0V (typ=0.9V) */</div><div class='add'>+			BUCK3 {</div><div class='add'>+				regulator-name = "buck3";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* vdd_3p3 */</div><div class='add'>+			BUCK4 {</div><div class='add'>+				regulator-name = "buck4";</div><div class='add'>+				regulator-min-microvolt = &lt;3000000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* vdd_1p8 */</div><div class='add'>+			BUCK5 {</div><div class='add'>+				regulator-name = "buck5";</div><div class='add'>+				regulator-min-microvolt = &lt;1605000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1995000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* vdd_dram */</div><div class='add'>+			BUCK6 {</div><div class='add'>+				regulator-name = "buck6";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* nvcc_snvs_1p8 */</div><div class='add'>+			LDO1 {</div><div class='add'>+				regulator-name = "ldo1";</div><div class='add'>+				regulator-min-microvolt = &lt;1600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1900000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* vdd_snvs_0p8 */</div><div class='add'>+			LDO2 {</div><div class='add'>+				regulator-name = "ldo2";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* vdda_1p8 */</div><div class='add'>+			LDO3 {</div><div class='add'>+				regulator-name = "ldo3";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			LDO4 {</div><div class='add'>+				regulator-name = "ldo4";</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			LDO6 {</div><div class='add'>+				regulator-name = "ldo6";</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c3_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	leds_gpio: gpio@20 {</div><div class='add'>+		compatible = "nxp,pca9555";</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	switch: switch@5f {</div><div class='add'>+		compatible = "microchip,ksz9897";</div><div class='add'>+		reg = &lt;0x5f&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_ksz&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;18 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			lan1: port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				label = "lan1";</div><div class='add'>+				phy-mode = "internal";</div><div class='add'>+				local-mac-address = [00 00 00 00 00 00];</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lan2: port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				label = "lan2";</div><div class='add'>+				phy-mode = "internal";</div><div class='add'>+				local-mac-address = [00 00 00 00 00 00];</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lan3: port@2 {</div><div class='add'>+				reg = &lt;2&gt;;</div><div class='add'>+				label = "lan3";</div><div class='add'>+				phy-mode = "internal";</div><div class='add'>+				local-mac-address = [00 00 00 00 00 00];</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lan4: port@3 {</div><div class='add'>+				reg = &lt;3&gt;;</div><div class='add'>+				label = "lan4";</div><div class='add'>+				phy-mode = "internal";</div><div class='add'>+				local-mac-address = [00 00 00 00 00 00];</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@5 {</div><div class='add'>+				reg = &lt;5&gt;;</div><div class='add'>+				ethernet = &lt;&amp;fec1&gt;;</div><div class='add'>+				phy-mode = "rgmii-id";</div><div class='add'>+</div><div class='add'>+				fixed-link {</div><div class='add'>+					speed = &lt;1000&gt;;</div><div class='add'>+					full-duplex;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	crypto@60 {</div><div class='add'>+		compatible = "atmel,atecc508a";</div><div class='add'>+		reg = &lt;0x60&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c4&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c4_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	fsl,refclk-pad-mode = &lt;IMX8_PCIE_REFCLK_PAD_INPUT&gt;;</div><div class='add'>+	fsl,clkreq-unsupported;</div><div class='add'>+	clocks = &lt;&amp;pcie0_refclk&gt;;</div><div class='add'>+	clock-names = "ref";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie0&gt;;</div><div class='add'>+	reset-gpio = &lt;&amp;gpio5 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	clocks = &lt;&amp;clk IMX8MM_CLK_PCIE1_ROOT&gt;, &lt;&amp;pcie0_refclk&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX8MM_CLK_PCIE1_AUX&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_PCIE1_AUX&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MM_CLK_PCIE1_CTRL&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;10000000&gt;, &lt;250000000&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL2_50M&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MM_SYS_PLL2_250M&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pgc_gpu {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pgc_gpumix {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pgc_mipi {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;, &lt;&amp;pinctrl_uart1_gpio&gt;;</div><div class='add'>+	rts-gpios = &lt;&amp;gpio1 10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	cts-gpios = &lt;&amp;gpio1 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	dtr-gpios = &lt;&amp;gpio1 14 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	dsr-gpios = &lt;&amp;gpio1 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	dcd-gpios = &lt;&amp;gpio1 11 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* console */</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;, &lt;&amp;pinctrl_uart3_gpio&gt;;</div><div class='add'>+	cts-gpios = &lt;&amp;gpio4 10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	rts-gpios = &lt;&amp;gpio4 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart4&gt;, &lt;&amp;pinctrl_uart4_gpio&gt;;</div><div class='add'>+	cts-gpios = &lt;&amp;gpio5 11 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	rts-gpios = &lt;&amp;gpio5 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	disable-over-current;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg2 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usb2_vbus&gt;;</div><div class='add'>+	over-current-active-low;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SDIO WiFi */</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1_200mhz&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_wifi&gt;;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	wifi@0 {</div><div class='add'>+		compatible = "brcm,bcm43455-fmac", "brcm,bcm4329-fmac";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* microSD */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* eMMC */</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_USDHC3&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hog&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl_hog: hoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4	0x40000041 /* DIG1_CTL */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5	0x40000041 /* DIG2_CTL */</div><div class='add'>+			MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3		0x40000041 /* DIG2_OUT */</div><div class='add'>+			MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4		0x40000041 /* DIG2_IN */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6	0x40000041 /* DIG1_IN */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7	0x40000041 /* DIG1_OUT */</div><div class='add'>+			MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30	0x40000041 /* SIM2DET# */</div><div class='add'>+			MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29	0x40000041 /* SIM1DET# */</div><div class='add'>+			MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5	0x40000041 /* SIM2SEL */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec1: fec1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3</div><div class='add'>+			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18		0x19 /* IRQ# */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19		0x19 /* RST# */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gsc: gscgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16	0x159</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1_gpio: i2c1gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14	0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15	0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2_gpio: i2c2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16	0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17	0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3_gpio: i2c3gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18	0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19	0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4: i2c4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL		0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4_gpio: i2c4gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20	0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21	0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ksz: kszgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18	0x41</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19	0x41 /* RST# */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie0: pciegrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31	0x40000041 /* WDIS# */</div><div class='add'>+			MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: pmicgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_isouart: regisouartgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13	0x40000041</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_ioexp: regioexpgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21	0x40000041</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_wl: regwlgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25	0x40000041</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usb2: regusb1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2	0x41</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17	0x140</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_spi1: spi1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK	0x82</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI	0x82</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO	0x82</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9	0x140</div><div class='add'>+			MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140</div><div class='add'>+			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1	0x140</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10	0x140</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11	0x140</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x140</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1_gpio: uart1gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0	0x40000041 /* RS422# */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x40000041 /* RS485# */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5	0x40000041 /* RS232# */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140</div><div class='add'>+			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: uart3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX	0x140</div><div class='add'>+			MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX	0x140</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9	0x140</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3_gpio: uart3gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6	0x40000110 /* RS232# */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7	0x40000110 /* RS422# */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8	0x40000110 /* RS485# */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart4: uart4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX	0x140</div><div class='add'>+			MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX	0x140</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11	0x140</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart4_gpio: uart4gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10	0x40000041 /* RS232# */</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13	0x40000041 /* RS422# */</div><div class='add'>+			MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27	0x40000041 /* RS485# */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x190</div><div class='add'>+			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x194</div><div class='add'>+			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x196</div><div class='add'>+			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2-gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12	0x1c4</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x190</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x190</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x194</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x194</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x196</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x196</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts<br/>new file mode 100644<br/>index 000000000000..468c7e993c52<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts</a></div><div class='hunk'>@@ -0,0 +1,1088 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021 Gateworks Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/linux-event-codes.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/net/ti-dp83867.h&gt;</div><div class='add'>+#include &lt;dt-bindings/phy/phy-imx8-pcie.h&gt;</div><div class='add'>+</div><div class='add'>+#include "imx8mm.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Gateworks Venice GW7902 i.MX8MM board";</div><div class='add'>+	compatible = "gw,imx8mm-gw7902", "fsl,imx8mm";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet1 = &amp;eth1;</div><div class='add'>+		rtc0 = &amp;gsc_rtc;</div><div class='add'>+		rtc1 = &amp;snvs_rtc;</div><div class='add'>+		usb0 = &amp;usbotg1;</div><div class='add'>+		usb1 = &amp;usbotg2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x40000000 0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	can20m: can20m {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;20000000&gt;;</div><div class='add'>+		clock-output-names = "can20m";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		key-user-pb {</div><div class='add'>+			label = "user_pb";</div><div class='add'>+			gpios = &lt;&amp;gpio 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;BTN_0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-user-pb1x {</div><div class='add'>+			label = "user_pb1x";</div><div class='add'>+			linux,code = &lt;BTN_1&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gsc&gt;;</div><div class='add'>+			interrupts = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-erased {</div><div class='add'>+			label = "key_erased";</div><div class='add'>+			linux,code = &lt;BTN_2&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gsc&gt;;</div><div class='add'>+			interrupts = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-eeprom-wp {</div><div class='add'>+			label = "eeprom_wp";</div><div class='add'>+			linux,code = &lt;BTN_3&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gsc&gt;;</div><div class='add'>+			interrupts = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-tamper {</div><div class='add'>+			label = "tamper";</div><div class='add'>+			linux,code = &lt;BTN_4&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gsc&gt;;</div><div class='add'>+			interrupts = &lt;5&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		switch-hold {</div><div class='add'>+			label = "switch_hold";</div><div class='add'>+			linux,code = &lt;BTN_5&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gsc&gt;;</div><div class='add'>+			interrupts = &lt;7&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	led-controller {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_leds&gt;;</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			label = "panel1";</div><div class='add'>+			gpios = &lt;&amp;gpio3 21 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			label = "panel2";</div><div class='add'>+			gpios = &lt;&amp;gpio3 23 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-2 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			label = "panel3";</div><div class='add'>+			gpios = &lt;&amp;gpio3 22 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-3 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			label = "panel4";</div><div class='add'>+			gpios = &lt;&amp;gpio3 20 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-4 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			label = "panel5";</div><div class='add'>+			gpios = &lt;&amp;gpio3 25 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_refclk: pcie0-refclk {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;100000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pps {</div><div class='add'>+		compatible = "pps-gpio";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pps&gt;;</div><div class='add'>+		gpios = &lt;&amp;gpio3 24 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3p3v: regulator-3p3v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "3P3V";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb1_vbus: regulator-usb1 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usb1&gt;;</div><div class='add'>+		regulator-name = "usb_usb1_vbus";</div><div class='add'>+		gpio = &lt;&amp;gpio2 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_wifi: regulator-wifi {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_wl&gt;;</div><div class='add'>+		regulator-name = "wifi";</div><div class='add'>+		gpio = &lt;&amp;gpio2 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		startup-delay-us = &lt;100&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ddrc {</div><div class='add'>+	operating-points-v2 = &lt;&amp;ddrc_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+	ddrc_opp_table: opp-table {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		opp-25000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;25000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-100000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;100000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-750000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;750000000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_spi1&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	can@0 {</div><div class='add'>+		compatible = "microchip,mcp2515";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		clocks = &lt;&amp;can20m&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio2&gt;;</div><div class='add'>+		interrupts = &lt;3 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		spi-max-frequency = &lt;10000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* off-board header */</div><div class='add'>+&amp;ecspi2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_spi2&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 13 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec1&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	local-mac-address = [00 00 00 00 00 00];</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@0 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			ti,clk-output-sel = &lt;DP83867_CLK_O_SEL_OFF&gt;;</div><div class='add'>+			ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_2_00_NS&gt;;</div><div class='add'>+			ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_2_00_NS&gt;;</div><div class='add'>+			tx-fifo-depth = &lt;DP83867_PHYCR_FIFO_DEPTH_4_B_NIB&gt;;</div><div class='add'>+			rx-fifo-depth = &lt;DP83867_PHYCR_FIFO_DEPTH_4_B_NIB&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	gpio-line-names = "", "", "", "", "", "", "", "",</div><div class='add'>+		"m2_pwr_en", "", "", "", "", "m2_reset", "", "m2_wdis#",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio2 {</div><div class='add'>+	gpio-line-names = "", "", "", "", "", "", "", "",</div><div class='add'>+		"uart2_en#", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio3 {</div><div class='add'>+	gpio-line-names = "", "m2_gdis#", "", "", "", "", "", "m2_off#",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	gpio-line-names = "", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "amp_gpio3", "amp_gpio2", "", "amp_gpio1", "",</div><div class='add'>+		"lte_pwr#", "lte_rst", "lte_int", "",</div><div class='add'>+		"amp_gpio4", "app_gpio1", "vdd_4p0_en", "uart1_rs485",</div><div class='add'>+		"", "uart1_term", "uart1_half", "app_gpio2",</div><div class='add'>+		"mipi_gpio1", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio5 {</div><div class='add'>+	gpio-line-names = "", "", "", "mipi_gpio4",</div><div class='add'>+		"mipi_gpio3", "mipi_gpio2", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c1_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	gsc: gsc@20 {</div><div class='add'>+		compatible = "gw,gsc";</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gsc&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio2&gt;;</div><div class='add'>+		interrupts = &lt;6 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		adc {</div><div class='add'>+			compatible = "gw,gsc-adc";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			channel@6 {</div><div class='add'>+				gw,mode = &lt;0&gt;;</div><div class='add'>+				reg = &lt;0x06&gt;;</div><div class='add'>+				label = "temp";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@8 {</div><div class='add'>+				gw,mode = &lt;3&gt;;</div><div class='add'>+				reg = &lt;0x08&gt;;</div><div class='add'>+				label = "vdd_bat";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@82 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x82&gt;;</div><div class='add'>+				label = "vin";</div><div class='add'>+				gw,voltage-divider-ohms = &lt;22100 1000&gt;;</div><div class='add'>+				gw,voltage-offset-microvolt = &lt;700000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@84 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x84&gt;;</div><div class='add'>+				label = "vin_4p0";</div><div class='add'>+				gw,voltage-divider-ohms = &lt;10000 10000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@86 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x86&gt;;</div><div class='add'>+				label = "vdd_3p3";</div><div class='add'>+				gw,voltage-divider-ohms = &lt;10000 10000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@88 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x88&gt;;</div><div class='add'>+				label = "vdd_0p9";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@8c {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x8c&gt;;</div><div class='add'>+				label = "vdd_soc";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@8e {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x8e&gt;;</div><div class='add'>+				label = "vdd_arm";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@90 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x90&gt;;</div><div class='add'>+				label = "vdd_1p8";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@92 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x92&gt;;</div><div class='add'>+				label = "vdd_dram";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@98 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x98&gt;;</div><div class='add'>+				label = "vdd_1p0";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@9a {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x9a&gt;;</div><div class='add'>+				label = "vdd_2p5";</div><div class='add'>+				gw,voltage-divider-ohms = &lt;10000 10000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@9c {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x9c&gt;;</div><div class='add'>+				label = "vdd_5p0";</div><div class='add'>+				gw,voltage-divider-ohms = &lt;10000 10000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@a2 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0xa2&gt;;</div><div class='add'>+				label = "vdd_gsc";</div><div class='add'>+				gw,voltage-divider-ohms = &lt;10000 10000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio: gpio@23 {</div><div class='add'>+		compatible = "nxp,pca9555";</div><div class='add'>+		reg = &lt;0x23&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gsc&gt;;</div><div class='add'>+		interrupts = &lt;4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmic@4b {</div><div class='add'>+		compatible = "rohm,bd71847";</div><div class='add'>+		reg = &lt;0x4b&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+		interrupts = &lt;8 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		rohm,reset-snvs-powered;</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clocks = &lt;&amp;osc_32k&gt;;</div><div class='add'>+		clock-output-names = "clk-32k-out";</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			/* vdd_soc: 0.805-0.900V (typ=0.8V) */</div><div class='add'>+			BUCK1 {</div><div class='add'>+				regulator-name = "buck1";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;1250&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* vdd_arm: 0.805-1.0V (typ=0.9V) */</div><div class='add'>+			buck2: BUCK2 {</div><div class='add'>+				regulator-name = "buck2";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;1250&gt;;</div><div class='add'>+				rohm,dvs-run-voltage = &lt;1000000&gt;;</div><div class='add'>+				rohm,dvs-idle-voltage = &lt;900000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* vdd_0p9: 0.805-1.0V (typ=0.9V) */</div><div class='add'>+			BUCK3 {</div><div class='add'>+				regulator-name = "buck3";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* vdd_3p3 */</div><div class='add'>+			BUCK4 {</div><div class='add'>+				regulator-name = "buck4";</div><div class='add'>+				regulator-min-microvolt = &lt;3000000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* vdd_1p8 */</div><div class='add'>+			BUCK5 {</div><div class='add'>+				regulator-name = "buck5";</div><div class='add'>+				regulator-min-microvolt = &lt;1605000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1995000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* vdd_dram */</div><div class='add'>+			BUCK6 {</div><div class='add'>+				regulator-name = "buck6";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* nvcc_snvs_1p8 */</div><div class='add'>+			LDO1 {</div><div class='add'>+				regulator-name = "ldo1";</div><div class='add'>+				regulator-min-microvolt = &lt;1600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1900000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* vdd_snvs_0p8 */</div><div class='add'>+			LDO2 {</div><div class='add'>+				regulator-name = "ldo2";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* vdda_1p8 */</div><div class='add'>+			LDO3 {</div><div class='add'>+				regulator-name = "ldo3";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			LDO4 {</div><div class='add'>+				regulator-name = "ldo4";</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			LDO6 {</div><div class='add'>+				regulator-name = "ldo6";</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@50 {</div><div class='add'>+		compatible = "atmel,24c02";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@51 {</div><div class='add'>+		compatible = "atmel,24c02";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@52 {</div><div class='add'>+		compatible = "atmel,24c02";</div><div class='add'>+		reg = &lt;0x52&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@53 {</div><div class='add'>+		compatible = "atmel,24c02";</div><div class='add'>+		reg = &lt;0x53&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gsc_rtc: rtc@68 {</div><div class='add'>+		compatible = "dallas,ds1672";</div><div class='add'>+		reg = &lt;0x68&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c2_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	accelerometer@19 {</div><div class='add'>+		compatible = "st,lis2de12";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_accel&gt;;</div><div class='add'>+		reg = &lt;0x19&gt;;</div><div class='add'>+		st,drdy-int-pin = &lt;1&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;12 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* off-board header */</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c3_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* off-board header */</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c4&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c4_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	fsl,refclk-pad-mode = &lt;IMX8_PCIE_REFCLK_PAD_INPUT&gt;;</div><div class='add'>+	fsl,clkreq-unsupported;</div><div class='add'>+	clocks = &lt;&amp;pcie0_refclk&gt;;</div><div class='add'>+	clock-names = "ref";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie0&gt;;</div><div class='add'>+	reset-gpio = &lt;&amp;gpio4 5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	clocks = &lt;&amp;clk IMX8MM_CLK_PCIE1_ROOT&gt;, &lt;&amp;pcie0_refclk&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX8MM_CLK_PCIE1_AUX&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_PCIE1_AUX&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MM_CLK_PCIE1_CTRL&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;10000000&gt;, &lt;250000000&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL2_50M&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MM_SYS_PLL2_250M&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pcie@0,0 {</div><div class='add'>+		reg = &lt;0x0000 0 0 0 0&gt;;</div><div class='add'>+		device_type = "pci";</div><div class='add'>+		#address-cells = &lt;3&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		eth1: ethernet@0,0 {</div><div class='add'>+			reg = &lt;0x0000 0 0 0 0&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			local-mac-address = [00 00 00 00 00 00];</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* off-board header */</div><div class='add'>+&amp;sai3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai3&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_SAI3&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;24576000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* RS232/RS485/RS422 selectable */</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;, &lt;&amp;pinctrl_uart1_gpio&gt;;</div><div class='add'>+	rts-gpios = &lt;&amp;gpio4 10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	cts-gpios = &lt;&amp;gpio4 24 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* RS232 console */</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* bluetooth HCI */</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;, &lt;&amp;pinctrl_uart3_gpio&gt;;</div><div class='add'>+	rts-gpios = &lt;&amp;gpio2 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	cts-gpios = &lt;&amp;gpio2 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "brcm,bcm4330-bt";</div><div class='add'>+		shutdown-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* LTE Cat M1/NB1/EGPRS modem or GPS (loading option) */</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart4&gt;;</div><div class='add'>+	rts-gpios = &lt;&amp;gpio4 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	cts-gpios = &lt;&amp;gpio4 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	dtr-gpios = &lt;&amp;gpio4 3 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	dsr-gpios = &lt;&amp;gpio4 4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	dcd-gpios = &lt;&amp;gpio4 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usb1_vbus&gt;;</div><div class='add'>+	disable-over-current;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg2 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	disable-over-current;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SDIO WiFi */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_wifi&gt;;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	wifi@0 {</div><div class='add'>+		compatible = "brcm,bcm43455-fmac", "brcm,bcm4329-fmac";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* eMMC */</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_USDHC3&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hog&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl_hog: hoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1	0x40000159 /* M2_GDIS# */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8	0x40000041 /* M2_PWR_EN */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13	0x40000041 /* M2_RESET */</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7	0x40000119 /* M2_OFF# */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x40000159 /* M2_WDIS# */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18       0x40000041 /* LTE_INT */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17       0x40000041 /* LTE_RST# */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16       0x40000041 /* LTE_PWR */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14	0x40000041 /* AMP GPIO1 */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12	0x40000041 /* AMP GPIO2 */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11	0x40000041 /* AMP GPIO3 */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20	0x40000041 /* AMP_GPIO4 */</div><div class='add'>+			MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21	0x40000041 /* APP GPIO1 */</div><div class='add'>+			MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22	0x40000041 /* VDD_4P0_EN */</div><div class='add'>+			MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27	0x40000041 /* APP GPIO2 */</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8	0x40000041 /* UART2_EN# */</div><div class='add'>+			MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28	0x40000041 /* MIPI_GPIO1 */</div><div class='add'>+			MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5	0x40000041 /* MIPI_GPIO2 */</div><div class='add'>+			MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4		0x40000041 /* MIPI_GPIO3/PWM2 */</div><div class='add'>+			MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3		0x40000041 /* MIPI_GPIO4/PWM3 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_accel: accelgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x159</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec1: fec1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3</div><div class='add'>+			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x19 /* RST# */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x19 /* IRQ# */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gsc: gscgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6	0x40</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1_gpio: i2c1gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14	0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15	0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2_gpio: i2c2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16	0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17	0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3_gpio: i2c3gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18	0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19	0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4: i2c4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL		0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4_gpio: i2c4gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20	0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21	0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio_leds: gpioledgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21	0x19</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23	0x19</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22	0x19</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20	0x19</div><div class='add'>+			MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25	0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie0: pciegrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: pmicgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pps: ppsgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24	0x141 /* PPS */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_wl: regwlgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41 /* WLAN_WLON */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usb1: regusb1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai3: sai3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK	0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0	0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK	0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0	0xd6</div><div class='add'>+			MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC	0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_spi1: spi1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK	0x82</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI	0x82</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO	0x82</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9	0x40</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3	0x140 /* CAN_IRQ# */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_spi2: spi2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0x82</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0x82</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO	0x82</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13	0x40 /* SS0 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140</div><div class='add'>+			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140</div><div class='add'>+			MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10	0x140 /* RTS */</div><div class='add'>+			MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24	0x140 /* CTS */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1_gpio: uart1gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26	0x40000110 /* HALF */</div><div class='add'>+			MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25	0x40000110 /* TERM */</div><div class='add'>+			MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23	0x40000110 /* RS485 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140</div><div class='add'>+			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3_gpio: uart3_gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12	0x41 /* BT_EN# */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: uart3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX	0x140</div><div class='add'>+			MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX	0x140</div><div class='add'>+			MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0		0x140 /* CTS */</div><div class='add'>+			MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1		0x140 /* RTS */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart4: uart4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX	0x140</div><div class='add'>+			MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX	0x140</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1		0x140 /* CTS */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2	0x140 /* RTS */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3	0x140 /* DTR */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4	0x140 /* DSR */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6	0x140 /* DCD */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7	0x140 /* RI */</div><div class='add'>+			MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0	0x140 /* GNSS_PPS */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6	0x141 /* GNSS_GASP */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x190</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x190</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x194</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x194</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x196</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x196</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts<br/>new file mode 100644<br/>index 000000000000..636daa3d6ca2<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts</a></div><div class='hunk'>@@ -0,0 +1,876 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Gateworks Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/linux-event-codes.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/phy/phy-imx8-pcie.h&gt;</div><div class='add'>+</div><div class='add'>+#include "imx8mm.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Gateworks Venice GW7903 i.MX8MM board";</div><div class='add'>+	compatible = "gw,imx8mm-gw7903", "fsl,imx8mm";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;fec1;</div><div class='add'>+		rtc0 = &amp;gsc_rtc;</div><div class='add'>+		rtc1 = &amp;snvs_rtc;</div><div class='add'>+		usb0 = &amp;usbotg1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x40000000 0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		key-user-pb {</div><div class='add'>+			label = "user_pb";</div><div class='add'>+			gpios = &lt;&amp;gpio 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;BTN_0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-user-pb1x {</div><div class='add'>+			label = "user_pb1x";</div><div class='add'>+			linux,code = &lt;BTN_1&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gsc&gt;;</div><div class='add'>+			interrupts = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-erased {</div><div class='add'>+			label = "key_erased";</div><div class='add'>+			linux,code = &lt;BTN_2&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gsc&gt;;</div><div class='add'>+			interrupts = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-eeprom-wp {</div><div class='add'>+			label = "eeprom_wp";</div><div class='add'>+			linux,code = &lt;BTN_3&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gsc&gt;;</div><div class='add'>+			interrupts = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		switch-hold {</div><div class='add'>+			label = "switch_hold";</div><div class='add'>+			linux,code = &lt;BTN_5&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gsc&gt;;</div><div class='add'>+			interrupts = &lt;7&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	led-controller {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_leds&gt;;</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			label = "led01_red";</div><div class='add'>+			gpios = &lt;&amp;gpio5 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			label = "led01_grn";</div><div class='add'>+			gpios = &lt;&amp;gpio4 30 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-2 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			label = "led02_red";</div><div class='add'>+			gpios = &lt;&amp;gpio5 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-3 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			label = "led02_grn";</div><div class='add'>+			gpios = &lt;&amp;gpio1 14 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-4 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			label = "led03_red";</div><div class='add'>+			gpios = &lt;&amp;gpio1 9 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-5 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			label = "led03_grn";</div><div class='add'>+			gpios = &lt;&amp;gpio5 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-6 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			label = "led04_red";</div><div class='add'>+			gpios = &lt;&amp;gpio4 29 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-7 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			label = "led04_grn";</div><div class='add'>+			gpios = &lt;&amp;gpio4 28 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-8 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			label = "led05_red";</div><div class='add'>+			gpios = &lt;&amp;gpio1 13 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-9 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			label = "led05_grn";</div><div class='add'>+			gpios = &lt;&amp;gpio4 31 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-a {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			label = "led06_red";</div><div class='add'>+			gpios = &lt;&amp;gpio5 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-b {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			label = "led06_grn";</div><div class='add'>+			gpios = &lt;&amp;gpio1 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_refclk: pcie0-refclk {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;100000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3p3v: regulator-3p3v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "3P3V";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ddrc {</div><div class='add'>+	operating-points-v2 = &lt;&amp;ddrc_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+	ddrc_opp_table: opp-table {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		opp-25000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;25000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-100000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;100000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-750000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;750000000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec1&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	local-mac-address = [00 00 00 00 00 00];</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@0 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			rx-internal-delay-ps = &lt;2000&gt;;</div><div class='add'>+			tx-internal-delay-ps = &lt;2500&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	gpio-line-names = "", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "rs422_en#", "rs485_en#", "rs232_en#", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio2 {</div><div class='add'>+	gpio-line-names = "dig2_in", "dig2_out#", "dig2_ctl", "", "", "", "dig1_ctl", "",</div><div class='add'>+		"dig1_out#", "dig1_in", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio5 {</div><div class='add'>+	gpio-line-names = "", "", "", "", "", "", "", "sim1_det#",</div><div class='add'>+		"sim2_det#", "sim2_sel", "", "", "pci_wdis#", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c1_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	gsc: gsc@20 {</div><div class='add'>+		compatible = "gw,gsc";</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gsc&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;26 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		adc {</div><div class='add'>+			compatible = "gw,gsc-adc";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			channel@6 {</div><div class='add'>+				gw,mode = &lt;0&gt;;</div><div class='add'>+				reg = &lt;0x06&gt;;</div><div class='add'>+				label = "temp";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@8 {</div><div class='add'>+				gw,mode = &lt;3&gt;;</div><div class='add'>+				reg = &lt;0x08&gt;;</div><div class='add'>+				label = "vdd_bat";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@82 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x82&gt;;</div><div class='add'>+				label = "vin";</div><div class='add'>+				gw,voltage-divider-ohms = &lt;22100 1000&gt;;</div><div class='add'>+				gw,voltage-offset-microvolt = &lt;700000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@84 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x84&gt;;</div><div class='add'>+				label = "vdd_5p0";</div><div class='add'>+				gw,voltage-divider-ohms = &lt;10000 10000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@86 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x86&gt;;</div><div class='add'>+				label = "vdd_3p3";</div><div class='add'>+				gw,voltage-divider-ohms = &lt;10000 10000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@88 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x88&gt;;</div><div class='add'>+				label = "vdd_0p9";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@8c {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x8c&gt;;</div><div class='add'>+				label = "vdd_soc";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@8e {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x8e&gt;;</div><div class='add'>+				label = "vdd_arm";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@90 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x90&gt;;</div><div class='add'>+				label = "vdd_1p8";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@92 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x92&gt;;</div><div class='add'>+				label = "vdd_dram";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@a2 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0xa2&gt;;</div><div class='add'>+				label = "vdd_gsc";</div><div class='add'>+				gw,voltage-divider-ohms = &lt;10000 10000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio: gpio@23 {</div><div class='add'>+		compatible = "nxp,pca9555";</div><div class='add'>+		reg = &lt;0x23&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gsc&gt;;</div><div class='add'>+		interrupts = &lt;4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@50 {</div><div class='add'>+		compatible = "atmel,24c02";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@51 {</div><div class='add'>+		compatible = "atmel,24c02";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@52 {</div><div class='add'>+		compatible = "atmel,24c02";</div><div class='add'>+		reg = &lt;0x52&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@53 {</div><div class='add'>+		compatible = "atmel,24c02";</div><div class='add'>+		reg = &lt;0x53&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gsc_rtc: rtc@68 {</div><div class='add'>+		compatible = "dallas,ds1672";</div><div class='add'>+		reg = &lt;0x68&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c2_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pmic@4b {</div><div class='add'>+		compatible = "rohm,bd71847";</div><div class='add'>+		reg = &lt;0x4b&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+		interrupts = &lt;8 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		rohm,reset-snvs-powered;</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clocks = &lt;&amp;osc_32k&gt;;</div><div class='add'>+		clock-output-names = "clk-32k-out";</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			/* vdd_soc: 0.805-0.900V (typ=0.8V) */</div><div class='add'>+			BUCK1 {</div><div class='add'>+				regulator-name = "buck1";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;1250&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* vdd_arm: 0.805-1.0V (typ=0.9V) */</div><div class='add'>+			buck2: BUCK2 {</div><div class='add'>+				regulator-name = "buck2";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;1250&gt;;</div><div class='add'>+				rohm,dvs-run-voltage = &lt;1000000&gt;;</div><div class='add'>+				rohm,dvs-idle-voltage = &lt;900000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* vdd_0p9: 0.805-1.0V (typ=0.9V) */</div><div class='add'>+			BUCK3 {</div><div class='add'>+				regulator-name = "buck3";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* vdd_3p3 */</div><div class='add'>+			BUCK4 {</div><div class='add'>+				regulator-name = "buck4";</div><div class='add'>+				regulator-min-microvolt = &lt;3000000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* vdd_1p8 */</div><div class='add'>+			BUCK5 {</div><div class='add'>+				regulator-name = "buck5";</div><div class='add'>+				regulator-min-microvolt = &lt;1605000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1995000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* vdd_dram */</div><div class='add'>+			BUCK6 {</div><div class='add'>+				regulator-name = "buck6";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* nvcc_snvs_1p8 */</div><div class='add'>+			LDO1 {</div><div class='add'>+				regulator-name = "ldo1";</div><div class='add'>+				regulator-min-microvolt = &lt;1600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1900000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* vdd_snvs_0p8 */</div><div class='add'>+			LDO2 {</div><div class='add'>+				regulator-name = "ldo2";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* vdda_1p8 */</div><div class='add'>+			LDO3 {</div><div class='add'>+				regulator-name = "ldo3";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			LDO4 {</div><div class='add'>+				regulator-name = "ldo4";</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			LDO6 {</div><div class='add'>+				regulator-name = "ldo6";</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c3_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	accelerometer@19 {</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_accel&gt;;</div><div class='add'>+		compatible = "st,lis2de12";</div><div class='add'>+		reg = &lt;0x19&gt;;</div><div class='add'>+		st,drdy-int-pin = &lt;1&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;15 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	fsl,refclk-pad-mode = &lt;IMX8_PCIE_REFCLK_PAD_INPUT&gt;;</div><div class='add'>+	fsl,clkreq-unsupported;</div><div class='add'>+	clocks = &lt;&amp;pcie0_refclk&gt;;</div><div class='add'>+	clock-names = "ref";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie0&gt;;</div><div class='add'>+	reset-gpio = &lt;&amp;gpio5 11 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	clocks = &lt;&amp;clk IMX8MM_CLK_PCIE1_ROOT&gt;, &lt;&amp;pcie0_refclk&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX8MM_CLK_PCIE1_AUX&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_PCIE1_AUX&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MM_CLK_PCIE1_CTRL&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;10000000&gt;, &lt;250000000&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL2_50M&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MM_SYS_PLL2_250M&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;disp_blk_ctrl {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pgc_mipi {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* off-board RS232/RS485/RS422 */</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	cts-gpios = &lt;&amp;gpio1 3 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	rts-gpios = &lt;&amp;gpio1 5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	dtr-gpios = &lt;&amp;gpio1 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	dsr-gpios = &lt;&amp;gpio1 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	dcd-gpios = &lt;&amp;gpio3 24 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* console */</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	disable-over-current;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* microSD */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* eMMC */</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_USDHC3&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hog&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl_hog: hoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10	0x40000041 /* RS422# */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11	0x40000041 /* RS485# */</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x40000041 /* RS232# */</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9	0x40000041 /* DIG1_IN */</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8	0x40000041 /* DIG1_OUT */</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6	0x40000041 /* DIG1_CTL */</div><div class='add'>+			MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2	0x40000041 /* DIG2_CTL */</div><div class='add'>+			MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0		0x40000041 /* DIG2_IN */</div><div class='add'>+			MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1		0x40000041 /* DIG2_OUT */</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_MOSI_GPIO5_IO7	0x40000041 /* SIM1DET# */</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8	0x40000041 /* SIM2DET# */</div><div class='add'>+			MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9	0x40000041 /* SIM2SEL */</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12	0x40000041 /* PCI_WDIS# */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_accel: accelgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x159</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec1: fec1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3</div><div class='add'>+			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f</div><div class='add'>+			MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24		0x19 /* IRQ# */</div><div class='add'>+			MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25		0x19 /* RST# */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gsc: gscgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26	0x159</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1_gpio: i2c1gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14	0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15	0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2_gpio: i2c2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16	0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17	0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3_gpio: i2c3gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18	0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19	0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio_leds: gpioledgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5	0x19</div><div class='add'>+			MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30	0x19</div><div class='add'>+			MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2	0x19</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14	0x19</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9	0x19</div><div class='add'>+			MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3		0x19</div><div class='add'>+			MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29	0x19</div><div class='add'>+			MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28	0x19</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13	0x19</div><div class='add'>+			MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31	0x19</div><div class='add'>+			MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4		0x19</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8	0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie0: pciegrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: pmicgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140</div><div class='add'>+			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0	0x140</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1	0x140</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x140</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5	0x140</div><div class='add'>+			MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140</div><div class='add'>+			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2-gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12	0x1c4</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x190</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x190</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x194</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x194</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x196</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x196</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts<br/>new file mode 100644<br/>index 000000000000..99572961d9e1<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts</a></div><div class='hunk'>@@ -0,0 +1,929 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Gateworks Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/linux-event-codes.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/phy/phy-imx8-pcie.h&gt;</div><div class='add'>+</div><div class='add'>+#include "imx8mm.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Gateworks Venice GW7904 i.MX8MM board";</div><div class='add'>+	compatible = "gateworks,imx8mm-gw7904", "fsl,imx8mm";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		rtc0 = &amp;gsc_rtc;</div><div class='add'>+		rtc1 = &amp;snvs_rtc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x40000000 0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		key-0 {</div><div class='add'>+			label = "user_pb";</div><div class='add'>+			gpios = &lt;&amp;gpio 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;BTN_0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-1 {</div><div class='add'>+			label = "user_pb1x";</div><div class='add'>+			linux,code = &lt;BTN_1&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gsc&gt;;</div><div class='add'>+			interrupts = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-2 {</div><div class='add'>+			label = "key_erased";</div><div class='add'>+			linux,code = &lt;BTN_2&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gsc&gt;;</div><div class='add'>+			interrupts = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-3 {</div><div class='add'>+			label = "eeprom_wp";</div><div class='add'>+			linux,code = &lt;BTN_3&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gsc&gt;;</div><div class='add'>+			interrupts = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-4 {</div><div class='add'>+			label = "switch_hold";</div><div class='add'>+			linux,code = &lt;BTN_5&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gsc&gt;;</div><div class='add'>+			interrupts = &lt;7&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	led-controller {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_leds&gt;;</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			label = "led01_grn";</div><div class='add'>+			gpios = &lt;&amp;gpioled 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_YELLOW&gt;;</div><div class='add'>+			label = "led01_yel";</div><div class='add'>+			gpios = &lt;&amp;gpioled 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-2 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			label = "led02_grn";</div><div class='add'>+			gpios = &lt;&amp;gpioled 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-3 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_YELLOW&gt;;</div><div class='add'>+			label = "led02_yel";</div><div class='add'>+			gpios = &lt;&amp;gpioled 3 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-4 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			label = "led03_grn";</div><div class='add'>+			gpios = &lt;&amp;gpioled 4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-5 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_YELLOW&gt;;</div><div class='add'>+			label = "led03_yel";</div><div class='add'>+			gpios = &lt;&amp;gpioled 5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-6 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			label = "led04_grn";</div><div class='add'>+			gpios = &lt;&amp;gpioled 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-7 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_YELLOW&gt;;</div><div class='add'>+			label = "led04_yel";</div><div class='add'>+			gpios = &lt;&amp;gpioled 7 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-8 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			label = "led05_grn";</div><div class='add'>+			gpios = &lt;&amp;gpioled 8 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-9 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_YELLOW&gt;;</div><div class='add'>+			label = "led05_yel";</div><div class='add'>+			gpios = &lt;&amp;gpioled 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-10 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			label = "led06_grn";</div><div class='add'>+			gpios = &lt;&amp;gpio1 8 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-11 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			label = "led06_red";</div><div class='add'>+			gpios = &lt;&amp;gpio1 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-12 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			label = "led07_grn";</div><div class='add'>+			gpios = &lt;&amp;gpio1 10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-13 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			label = "led07_red";</div><div class='add'>+			gpios = &lt;&amp;gpio1 11 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-14 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			label = "led08_grn";</div><div class='add'>+			gpios = &lt;&amp;gpioled 10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-15 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_YELLOW&gt;;</div><div class='add'>+			label = "led08_yel";</div><div class='add'>+			gpios = &lt;&amp;gpioled 11 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-16 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			label = "led09_grn";</div><div class='add'>+			gpios = &lt;&amp;gpioled 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-17 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_YELLOW&gt;;</div><div class='add'>+			label = "led09_yel";</div><div class='add'>+			gpios = &lt;&amp;gpioled 13 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-18 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			label = "led10_grn";</div><div class='add'>+			gpios = &lt;&amp;gpioled 14 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-19 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_YELLOW&gt;;</div><div class='add'>+			label = "led10_yel";</div><div class='add'>+			gpios = &lt;&amp;gpioled 15 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_refclk: pcie0-refclk {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;100000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3p3v: regulator-3p3v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "3P3V";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ddrc {</div><div class='add'>+	operating-points-v2 = &lt;&amp;ddrc_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+	ddrc_opp_table: opp-table {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		opp-25000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;25000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-100000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;100000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-750000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;750000000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec1&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	local-mac-address = [00 00 00 00 00 00];</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@0 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	gpio-line-names = "", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "rs232_en#", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio5 {</div><div class='add'>+	gpio-line-names = "", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "pci_wdis#", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c1_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	gsc: gsc@20 {</div><div class='add'>+		compatible = "gw,gsc";</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gsc&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;26 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		adc {</div><div class='add'>+			compatible = "gw,gsc-adc";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			channel@6 {</div><div class='add'>+				gw,mode = &lt;0&gt;;</div><div class='add'>+				reg = &lt;0x06&gt;;</div><div class='add'>+				label = "temp";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@82 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x82&gt;;</div><div class='add'>+				label = "vin";</div><div class='add'>+				gw,voltage-divider-ohms = &lt;22100 1000&gt;;</div><div class='add'>+				gw,voltage-offset-microvolt = &lt;700000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@84 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x84&gt;;</div><div class='add'>+				label = "vdd_5p0";</div><div class='add'>+				gw,voltage-divider-ohms = &lt;10000 10000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@86 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x86&gt;;</div><div class='add'>+				label = "vdd_3p3";</div><div class='add'>+				gw,voltage-divider-ohms = &lt;10000 10000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@88 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x88&gt;;</div><div class='add'>+				label = "vdd_0p9";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@8c {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x8c&gt;;</div><div class='add'>+				label = "vdd_soc";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@8e {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x8e&gt;;</div><div class='add'>+				label = "vdd_arm";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@90 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x90&gt;;</div><div class='add'>+				label = "vdd_1p8";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@92 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x92&gt;;</div><div class='add'>+				label = "vdd_dram";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@a2 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0xa2&gt;;</div><div class='add'>+				label = "vdd_gsc";</div><div class='add'>+				gw,voltage-divider-ohms = &lt;10000 10000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio: gpio@23 {</div><div class='add'>+		compatible = "nxp,pca9555";</div><div class='add'>+		reg = &lt;0x23&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gsc&gt;;</div><div class='add'>+		interrupts = &lt;4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@50 {</div><div class='add'>+		compatible = "atmel,24c02";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@51 {</div><div class='add'>+		compatible = "atmel,24c02";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@52 {</div><div class='add'>+		compatible = "atmel,24c02";</div><div class='add'>+		reg = &lt;0x52&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@53 {</div><div class='add'>+		compatible = "atmel,24c02";</div><div class='add'>+		reg = &lt;0x53&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gsc_rtc: rtc@68 {</div><div class='add'>+		compatible = "dallas,ds1672";</div><div class='add'>+		reg = &lt;0x68&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c2_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pmic@4b {</div><div class='add'>+		compatible = "rohm,bd71847";</div><div class='add'>+		reg = &lt;0x4b&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+		interrupts = &lt;8 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		rohm,reset-snvs-powered;</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clocks = &lt;&amp;osc_32k&gt;;</div><div class='add'>+		clock-output-names = "clk-32k-out";</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			/* vdd_soc: 0.805-0.900V (typ=0.8V) */</div><div class='add'>+			BUCK1 {</div><div class='add'>+				regulator-name = "buck1";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;1250&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* vdd_arm: 0.805-1.0V (typ=0.9V) */</div><div class='add'>+			buck2: BUCK2 {</div><div class='add'>+				regulator-name = "buck2";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;1250&gt;;</div><div class='add'>+				rohm,dvs-run-voltage = &lt;1000000&gt;;</div><div class='add'>+				rohm,dvs-idle-voltage = &lt;900000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* vdd_0p9: 0.805-1.0V (typ=0.9V) */</div><div class='add'>+			BUCK3 {</div><div class='add'>+				regulator-name = "buck3";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* vdd_3p3 */</div><div class='add'>+			BUCK4 {</div><div class='add'>+				regulator-name = "buck4";</div><div class='add'>+				regulator-min-microvolt = &lt;3000000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* vdd_1p8 */</div><div class='add'>+			BUCK5 {</div><div class='add'>+				regulator-name = "buck5";</div><div class='add'>+				regulator-min-microvolt = &lt;1605000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1995000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* vdd_dram */</div><div class='add'>+			BUCK6 {</div><div class='add'>+				regulator-name = "buck6";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* nvcc_snvs_1p8 */</div><div class='add'>+			LDO1 {</div><div class='add'>+				regulator-name = "ldo1";</div><div class='add'>+				regulator-min-microvolt = &lt;1600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1900000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* vdd_snvs_0p8 */</div><div class='add'>+			LDO2 {</div><div class='add'>+				regulator-name = "ldo2";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* vdda_1p8 */</div><div class='add'>+			LDO3 {</div><div class='add'>+				regulator-name = "ldo3";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			LDO4 {</div><div class='add'>+				regulator-name = "ldo4";</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			LDO6 {</div><div class='add'>+				regulator-name = "ldo6";</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c3_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	accelerometer@19 {</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_accel&gt;;</div><div class='add'>+		compatible = "st,lis2de12";</div><div class='add'>+		reg = &lt;0x19&gt;;</div><div class='add'>+		st,drdy-int-pin = &lt;1&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;15 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c4&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c4_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	gpioled: gpio@27 {</div><div class='add'>+		compatible = "nxp,pca9555";</div><div class='add'>+		reg = &lt;0x27&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	fsl,refclk-pad-mode = &lt;IMX8_PCIE_REFCLK_PAD_INPUT&gt;;</div><div class='add'>+	fsl,clkreq-unsupported;</div><div class='add'>+	clocks = &lt;&amp;pcie0_refclk&gt;;</div><div class='add'>+	clock-names = "ref";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie0&gt;;</div><div class='add'>+	reset-gpio = &lt;&amp;gpio5 11 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	clocks = &lt;&amp;clk IMX8MM_CLK_PCIE1_ROOT&gt;, &lt;&amp;pcie0_refclk&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX8MM_CLK_PCIE1_AUX&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_PCIE1_AUX&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MM_CLK_PCIE1_CTRL&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;10000000&gt;, &lt;250000000&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL2_50M&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MM_SYS_PLL2_250M&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;disp_blk_ctrl {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pgc_mipi {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* off-board RS232 */</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	cts-gpios = &lt;&amp;gpio5 26 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	rts-gpios = &lt;&amp;gpio5 27 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* console */</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	disable-over-current;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* microSD */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* eMMC */</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_USDHC3&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hog&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl_hog: hoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x40000041 /* RS232# */</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12	0x40000041 /* PCI_WDIS# */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_accel: accelgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x159</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec1: fec1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3</div><div class='add'>+			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f</div><div class='add'>+			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91</div><div class='add'>+			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f</div><div class='add'>+			MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24		0x19 /* IRQ# */</div><div class='add'>+			MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25		0x19 /* RST# */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio_leds: gpioledsgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8	0x40000019</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9	0x40000019</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10	0x40000019</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11	0x40000019</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gsc: gscgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26	0x159</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1_gpio: i2c1gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14	0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15	0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2_gpio: i2c2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16	0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17	0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3_gpio: i2c3gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18	0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19	0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4: i2c4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL		0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4_gpio: i2c4gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20	0x400001c3</div><div class='add'>+			MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21	0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie0: pciegrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: pmicgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140</div><div class='add'>+			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140</div><div class='add'>+			MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26	0x140 /* CTS# in */</div><div class='add'>+			MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27	0x140 /* RTS# out */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140</div><div class='add'>+			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196</div><div class='add'>+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2-gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12	0x1c4</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x190</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d0</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x190</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x194</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d4</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x194</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x196</div><div class='add'>+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d6</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x196</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi<br/>new file mode 100644<br/>index 000000000000..3d0b14968131<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi</a></div><div class='hunk'>@@ -0,0 +1,191 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	sound_card: sound-card {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,bitclock-master = &lt;&amp;dailink_master&gt;;</div><div class='add'>+		simple-audio-card,format = "i2s";</div><div class='add'>+		simple-audio-card,frame-master = &lt;&amp;dailink_master&gt;;</div><div class='add'>+		simple-audio-card,mclk-fs = &lt;256&gt;;</div><div class='add'>+		simple-audio-card,name = "verdin-wm8904";</div><div class='add'>+		simple-audio-card,routing =</div><div class='add'>+			"Headphone Jack", "HPOUTL",</div><div class='add'>+			"Headphone Jack", "HPOUTR",</div><div class='add'>+			"IN2L", "Line In Jack",</div><div class='add'>+			"IN2R", "Line In Jack",</div><div class='add'>+			"Microphone Jack", "MICBIAS",</div><div class='add'>+			"IN1L", "Microphone Jack";</div><div class='add'>+		simple-audio-card,widgets =</div><div class='add'>+			"Microphone", "Microphone Jack",</div><div class='add'>+			"Headphone", "Headphone Jack",</div><div class='add'>+			"Line", "Line In Jack";</div><div class='add'>+</div><div class='add'>+		dailink_master: simple-audio-card,codec {</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MM_CLK_SAI2_ROOT&gt;;</div><div class='add'>+			sound-dai = &lt;&amp;wm8904_1a&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;sai2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb_hub: regulator-usb-hub {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		enable-active-high;</div><div class='add'>+		/* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */</div><div class='add'>+		gpio = &lt;&amp;gpio5 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-name = "HUB_PWR_EN";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_pcie: regulator-pcie {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		enable-active-high;</div><div class='add'>+		/* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */</div><div class='add'>+		gpio = &lt;&amp;gpio5 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-name = "PCIE_1_PWR_EN";</div><div class='add'>+		startup-delay-us = &lt;100000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin SPI_1 */</div><div class='add'>+&amp;ecspi2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* EEPROM on display adapter boards */</div><div class='add'>+&amp;eeprom_display_adapter {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* EEPROM on Verdin Development board */</div><div class='add'>+&amp;eeprom_carrier_board {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin QSPI_1 */</div><div class='add'>+&amp;flexspi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio5 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ctrl_sleep_moci&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Current measurement into module VCC */</div><div class='add'>+&amp;hwmon {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hwmon_temp {</div><div class='add'>+	vs-supply = &lt;&amp;reg_1p8v&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin I2C_1 */</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* Audio Codec */</div><div class='add'>+	wm8904_1a: audio-codec@1a {</div><div class='add'>+		compatible = "wlf,wm8904";</div><div class='add'>+		AVDD-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX8MM_CLK_SAI2_ROOT&gt;;</div><div class='add'>+		clock-names = "mclk";</div><div class='add'>+		CPVDD-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='add'>+		DBVDD-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='add'>+		DCVDD-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='add'>+		MICVDD-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='add'>+		reg = &lt;0x1a&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin PCIE_1 */</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	vpcie-supply = &lt;&amp;reg_pcie&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin PWM_3_DSI */</div><div class='add'>+&amp;pwm1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin PWM_1 */</div><div class='add'>+&amp;pwm2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin PWM_2 */</div><div class='add'>+&amp;pwm3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* We support turning off sleep moci on Dahlia */</div><div class='add'>+&amp;reg_force_sleep_moci {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin I2S_1 */</div><div class='add'>+&amp;sai2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin UART_3 */</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin UART_1 */</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin UART_2 */</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin USB_1 */</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	disable-over-current;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin USB_2 */</div><div class='add'>+&amp;usbotg2 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	disable-over-current;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	usb-hub@1 {</div><div class='add'>+		compatible = "usb424,2744";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;reg_usb_hub&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin SD_1 */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi<br/>new file mode 100644<br/>index 000000000000..1d8d146d9eeb<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi</a></div><div class='hunk'>@@ -0,0 +1,165 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	sound_card: sound-card {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,bitclock-master = &lt;&amp;dailink_master&gt;;</div><div class='add'>+		simple-audio-card,format = "i2s";</div><div class='add'>+		simple-audio-card,frame-master = &lt;&amp;dailink_master&gt;;</div><div class='add'>+		simple-audio-card,mclk-fs = &lt;256&gt;;</div><div class='add'>+		simple-audio-card,name = "verdin-nau8822";</div><div class='add'>+		simple-audio-card,routing =</div><div class='add'>+			"Headphones", "LHP",</div><div class='add'>+			"Headphones", "RHP",</div><div class='add'>+			"Speaker", "LSPK",</div><div class='add'>+			"Speaker", "RSPK",</div><div class='add'>+			"Line Out", "AUXOUT1",</div><div class='add'>+			"Line Out", "AUXOUT2",</div><div class='add'>+			"LAUX", "Line In",</div><div class='add'>+			"RAUX", "Line In",</div><div class='add'>+			"LMICP", "Mic In",</div><div class='add'>+			"RMICP", "Mic In";</div><div class='add'>+		simple-audio-card,widgets =</div><div class='add'>+			"Headphones", "Headphones",</div><div class='add'>+			"Line Out", "Line Out",</div><div class='add'>+			"Speaker", "Speaker",</div><div class='add'>+			"Microphone", "Mic In",</div><div class='add'>+			"Line", "Line In";</div><div class='add'>+</div><div class='add'>+		dailink_master: simple-audio-card,codec {</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MM_CLK_SAI2_ROOT&gt;;</div><div class='add'>+			sound-dai = &lt;&amp;nau8822_1a&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;sai2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin SPI_1 */</div><div class='add'>+&amp;ecspi2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* EEPROM on display adapter boards */</div><div class='add'>+&amp;eeprom_display_adapter {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* EEPROM on Verdin Development board */</div><div class='add'>+&amp;eeprom_carrier_board {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin QSPI_1 */</div><div class='add'>+&amp;flexspi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Current measurement into module VCC */</div><div class='add'>+&amp;hwmon {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hwmon_temp {</div><div class='add'>+	vs-supply = &lt;&amp;reg_1p8v&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio5 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ctrl_sleep_moci&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio_expander_21 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin I2C_1 */</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* Audio Codec */</div><div class='add'>+	nau8822_1a: audio-codec@1a {</div><div class='add'>+		compatible = "nuvoton,nau8822";</div><div class='add'>+		reg = &lt;0x1a&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin PCIE_1 */</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin PWM_3_DSI */</div><div class='add'>+&amp;pwm1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin PWM_1 */</div><div class='add'>+&amp;pwm2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin PWM_2 */</div><div class='add'>+&amp;pwm3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin I2S_1 */</div><div class='add'>+&amp;sai2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin UART_3 */</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin UART_1, connector X50 through RS485 transceiver */</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	linux,rs485-enabled-at-boot-time;</div><div class='add'>+	rs485-rts-active-low;</div><div class='add'>+	rs485-rx-during-tx;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin UART_2 */</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin USB_1 */</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	disable-over-current;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin USB_2 */</div><div class='add'>+&amp;usbotg2 {</div><div class='add'>+	disable-over-current;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Limit frequency on dev board due to long traces and bad signal integrity */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	max-frequency = &lt;100000000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-ivy.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-ivy.dtsi<br/>new file mode 100644<br/>index 000000000000..29075ff5eda6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-verdin-ivy.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-verdin-ivy.dtsi</a></div><div class='hunk'>@@ -0,0 +1,471 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 Toradex</div><div class='add'>+ *</div><div class='add'>+ * Common dtsi for Verdin IMX8MM SoM on Ivy carrier board</div><div class='add'>+ *</div><div class='add'>+ * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-mini-nano</div><div class='add'>+ * https://www.toradex.com/products/carrier-board/ivy-carrier-board</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/mux/mux.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	/* AIN1 Voltage w/o AIN1_MODE gpio control */</div><div class='add'>+	ain1_voltage_unmanaged: voltage-divider-ain1 {</div><div class='add'>+		compatible = "voltage-divider";</div><div class='add'>+		#io-channel-cells = &lt;1&gt;;</div><div class='add'>+		io-channels = &lt;&amp;ivy_adc1 0&gt;;</div><div class='add'>+		full-ohms = &lt;19&gt;;</div><div class='add'>+		output-ohms = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* AIN1 Current w/o AIN1_MODE gpio control */</div><div class='add'>+	ain1_current_unmanaged: current-sense-shunt-ain1 {</div><div class='add'>+		compatible = "current-sense-shunt";</div><div class='add'>+		#io-channel-cells = &lt;0&gt;;</div><div class='add'>+		io-channels = &lt;&amp;ivy_adc1 1&gt;;</div><div class='add'>+		shunt-resistor-micro-ohms = &lt;100000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* AIN1_MODE - SODIMM 216 */</div><div class='add'>+	ain1_mode_mux_ctrl: mux-controller-0 {</div><div class='add'>+		compatible = "gpio-mux";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio5&gt;;</div><div class='add'>+		#mux-control-cells = &lt;0&gt;;</div><div class='add'>+		mux-gpios = &lt;&amp;gpio1 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ain1-voltage {</div><div class='add'>+		compatible = "io-channel-mux";</div><div class='add'>+		channels = "ain1_voltage", "";</div><div class='add'>+		io-channels = &lt;&amp;ain1_voltage_unmanaged 0&gt;;</div><div class='add'>+		io-channel-names = "parent";</div><div class='add'>+		mux-controls = &lt;&amp;ain1_mode_mux_ctrl&gt;;</div><div class='add'>+		settle-time-us = &lt;1000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ain1-current {</div><div class='add'>+		compatible = "io-channel-mux";</div><div class='add'>+		channels = "", "ain1_current";</div><div class='add'>+		io-channels = &lt;&amp;ain1_current_unmanaged&gt;;</div><div class='add'>+		io-channel-names = "parent";</div><div class='add'>+		mux-controls = &lt;&amp;ain1_mode_mux_ctrl&gt;;</div><div class='add'>+		settle-time-us = &lt;1000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* AIN2 Voltage w/o AIN2_MODE gpio control */</div><div class='add'>+	ain2_voltage_unmanaged: voltage-divider-ain2 {</div><div class='add'>+		compatible = "voltage-divider";</div><div class='add'>+		#io-channel-cells = &lt;1&gt;;</div><div class='add'>+		io-channels = &lt;&amp;ivy_adc2 0&gt;;</div><div class='add'>+		full-ohms = &lt;19&gt;;</div><div class='add'>+		output-ohms = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* AIN2 Current w/o AIN2_MODE gpio control */</div><div class='add'>+	ain2_current_unmanaged: current-sense-shunt-ain2 {</div><div class='add'>+		compatible = "current-sense-shunt";</div><div class='add'>+		#io-channel-cells = &lt;0&gt;;</div><div class='add'>+		io-channels = &lt;&amp;ivy_adc2 1&gt;;</div><div class='add'>+		shunt-resistor-micro-ohms = &lt;100000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* AIN2_MODE - SODIMM 218 */</div><div class='add'>+	ain2_mode_mux_ctrl: mux-controller-1 {</div><div class='add'>+		compatible = "gpio-mux";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio6&gt;;</div><div class='add'>+		#mux-control-cells = &lt;0&gt;;</div><div class='add'>+		mux-gpios = &lt;&amp;gpio1 11 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ain2-voltage {</div><div class='add'>+		compatible = "io-channel-mux";</div><div class='add'>+		channels = "ain2_voltage", "";</div><div class='add'>+		io-channels = &lt;&amp;ain2_voltage_unmanaged 0&gt;;</div><div class='add'>+		io-channel-names = "parent";</div><div class='add'>+		mux-controls = &lt;&amp;ain2_mode_mux_ctrl&gt;;</div><div class='add'>+		settle-time-us = &lt;1000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ain2-current {</div><div class='add'>+		compatible = "io-channel-mux";</div><div class='add'>+		channels = "", "ain2_current";</div><div class='add'>+		io-channels = &lt;&amp;ain2_current_unmanaged&gt;;</div><div class='add'>+		io-channel-names = "parent";</div><div class='add'>+		mux-controls = &lt;&amp;ain2_mode_mux_ctrl&gt;;</div><div class='add'>+		settle-time-us = &lt;1000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_ivy_leds&gt;;</div><div class='add'>+</div><div class='add'>+		/* D7 Blue - SODIMM 30 - LEDs.GPIO1 */</div><div class='add'>+		led-0 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			function-enumerator = &lt;1&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio4 25 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* D7 Green - SODIMM 32 - LEDs.GPIO2 */</div><div class='add'>+		led-1 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			function-enumerator = &lt;1&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio4 24 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* D7 Red - SODIMM 34 - LEDs.GPIO3 */</div><div class='add'>+		led-2 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			function-enumerator = &lt;1&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio4 26 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* D8 Blue - SODIMM 36 - LEDs.GPIO4 */</div><div class='add'>+		led-3 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			function-enumerator = &lt;2&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio4 23 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* D8 Green - SODIMM 54 - LEDs.GPIO5 */</div><div class='add'>+		led-4 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			function-enumerator = &lt;2&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio3 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* D8 Red - SODIMM 44 - LEDs.GPIO6 */</div><div class='add'>+		led-5 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			function-enumerator = &lt;2&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio3 22 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* D9 Blue - SODIMM 46 - LEDs.GPIO7 */</div><div class='add'>+		led-6 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			function-enumerator = &lt;3&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio3 24 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* D9 Red - SODIMM 48 - LEDs.GPIO8 */</div><div class='add'>+		led-7 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			function-enumerator = &lt;3&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio3 21 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3v2_ain1: regulator-3v2-ain1 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;3200000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3200000&gt;;</div><div class='add'>+		regulator-name = "+3V2_AIN1";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3v2_ain2: regulator-3v2-ain2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;3200000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3200000&gt;;</div><div class='add'>+		regulator-name = "+3V2_AIN2";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Ivy Power Supply Input Voltage */</div><div class='add'>+	ivy-input-voltage {</div><div class='add'>+		compatible = "voltage-divider";</div><div class='add'>+		/* Verdin ADC_1 */</div><div class='add'>+		io-channels = &lt;&amp;verdin_som_adc 7&gt;;</div><div class='add'>+		full-ohms = &lt;204700&gt;; /* 200k + 4.7k */</div><div class='add'>+		output-ohms = &lt;4700&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ivy-5v-voltage {</div><div class='add'>+		compatible = "voltage-divider";</div><div class='add'>+		/* Verdin ADC_2 */</div><div class='add'>+		io-channels = &lt;&amp;verdin_som_adc 6&gt;;</div><div class='add'>+		full-ohms = &lt;39000&gt;; /* 27k + 12k */</div><div class='add'>+		output-ohms = &lt;12000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ivy-3v3-voltage {</div><div class='add'>+		compatible = "voltage-divider";</div><div class='add'>+		/* Verdin ADC_3 */</div><div class='add'>+		io-channels = &lt;&amp;verdin_som_adc 5&gt;;</div><div class='add'>+		full-ohms = &lt;54000&gt;; /* 27k + 27k */</div><div class='add'>+		output-ohms = &lt;27000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ivy-1v8-voltage {</div><div class='add'>+		compatible = "voltage-divider";</div><div class='add'>+		/* Verdin ADC_4 */</div><div class='add'>+		io-channels = &lt;&amp;verdin_som_adc 4&gt;;</div><div class='add'>+		full-ohms = &lt;39000&gt;; /* 12k + 27k */</div><div class='add'>+		output-ohms = &lt;27000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin SPI_1 */</div><div class='add'>+&amp;ecspi2 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi2&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_gpio1&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_gpio4&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 13 GPIO_ACTIVE_LOW&gt;,</div><div class='add'>+		   &lt;&amp;gpio3 4 GPIO_ACTIVE_LOW&gt;,</div><div class='add'>+		   &lt;&amp;gpio5 27 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	tpm@1 {</div><div class='add'>+		compatible = "infineon,slb9670", "tcg,tpm_tis-spi";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		spi-max-frequency = &lt;18500000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fram@2 {</div><div class='add'>+		compatible = "fujitsu,mb85rs256", "atmel,at25";</div><div class='add'>+		reg = &lt;2&gt;;</div><div class='add'>+		address-width = &lt;16&gt;;</div><div class='add'>+		size = &lt;32768&gt;;</div><div class='add'>+		spi-max-frequency = &lt;33000000&gt;;</div><div class='add'>+		pagesize = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* EEPROM on Ivy */</div><div class='add'>+&amp;eeprom_carrier_board {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin ETH_1 */</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio3 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"", /* 0 */</div><div class='add'>+		"",</div><div class='add'>+		"REL3", /* SODIMM 64 */</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"DIG_1", /* SODIMM 56 */</div><div class='add'>+		"DIG_2", /* SODIMM 58 */</div><div class='add'>+		"REL1",  /* SODIMM 60 */</div><div class='add'>+		"REL2",  /* SODIMM 62 */</div><div class='add'>+		"", /* 10 */</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"REL4",  /* SODIMM 66 */</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"", /* 20 */</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio5 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"", /* 0 */</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"GPIO2", /* Verdin GPIO_2 - SODIMM 208 */</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"", /* 10 */</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"", /* 20 */</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"GPIO3", /* Verdin GPIO_3 - SODIMM 210 */</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Temperature sensor on Ivy */</div><div class='add'>+&amp;hwmon_temp {</div><div class='add'>+	compatible = "ti,tmp1075";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin I2C_4 CSI */</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ivy_adc1: adc@40 {</div><div class='add'>+		compatible = "ti,ads1119";</div><div class='add'>+		reg = &lt;0x40&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio7&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;8 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		avdd-supply = &lt;&amp;reg_3v2_ain1&gt;;</div><div class='add'>+		dvdd-supply = &lt;&amp;reg_3v2_ain1&gt;;</div><div class='add'>+		vref-supply = &lt;&amp;reg_3v2_ain1&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#io-channel-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		/* AIN1 0-33V Voltage Input */</div><div class='add'>+		channel@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			diff-channels = &lt;0 1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* AIN1 0-20mA Current Input */</div><div class='add'>+		channel@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			diff-channels = &lt;2 3&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ivy_adc2: adc@41 {</div><div class='add'>+		compatible = "ti,ads1119";</div><div class='add'>+		reg = &lt;0x41&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio8&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;9 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		avdd-supply = &lt;&amp;reg_3v2_ain2&gt;;</div><div class='add'>+		dvdd-supply = &lt;&amp;reg_3v2_ain2&gt;;</div><div class='add'>+		vref-supply = &lt;&amp;reg_3v2_ain2&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#io-channel-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		/* AIN2 0-33V Voltage Input */</div><div class='add'>+		channel@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			diff-channels = &lt;0 1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* AIN2 0-20mA Current Input */</div><div class='add'>+		channel@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			diff-channels = &lt;2 3&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin I2C_1 */</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin PCIE_1 */</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin UART_3 */</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin UART_1 */</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin UART_2 */</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	linux,rs485-enabled-at-boot-time;</div><div class='add'>+	rs485-rx-during-tx;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin USB_1*/</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin USB_2 */</div><div class='add'>+&amp;usbotg2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin SD_1 */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio2&gt;, &lt;&amp;pinctrl_gpio3&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_ivy_dig_inputs&gt;, &lt;&amp;pinctrl_ivy_relays&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl_ivy_dig_inputs: ivydiginputsgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6	0x96&gt;, /* SODIMM 56 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7	0x96&gt;; /* SODIMM 58 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ivy_leds: ivyledsgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25	0x16&gt;, /* SODIMM 30 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24	0x16&gt;, /* SODIMM 32 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26	0x16&gt;, /* SODIMM 34 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23	0x16&gt;, /* SODIMM 36 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22	0x16&gt;, /* SODIMM 44 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24	0x16&gt;, /* SODIMM 46 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21	0x16&gt;, /* SODIMM 48 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1	0x16&gt;; /* SODIMM 54 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ivy_relays: ivyrelaysgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8	0x16&gt;, /* SODIMM 60 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9	0x16&gt;, /* SODIMM 62 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2	0x16&gt;, /* SODIMM 64 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_NAND_DQS_GPIO3_IO14	0x16&gt;; /* SODIMM 66 */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-mallow.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-mallow.dtsi<br/>new file mode 100644<br/>index 000000000000..4a0799d63446<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-verdin-mallow.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-verdin-mallow.dtsi</a></div><div class='hunk'>@@ -0,0 +1,173 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Toradex</div><div class='add'>+ *</div><div class='add'>+ * Common dtsi for Verdin IMX8MM SoM on Mallow carrier board</div><div class='add'>+ *</div><div class='add'>+ * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-mini-nano</div><div class='add'>+ * https://www.toradex.com/products/carrier-board/mallow-carrier-board</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_leds&gt;;</div><div class='add'>+</div><div class='add'>+		/* SODIMM 52 - USER_LED_1_RED */</div><div class='add'>+		led-0 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			function = LED_FUNCTION_DEBUG;</div><div class='add'>+			function-enumerator = &lt;1&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio3 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* SODIMM 54 - USER_LED_1_GREEN */</div><div class='add'>+		led-1 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_DEBUG;</div><div class='add'>+			function-enumerator = &lt;1&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio3 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* SODIMM 56 - USER_LED_2_RED */</div><div class='add'>+		led-2 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			function = LED_FUNCTION_DEBUG;</div><div class='add'>+			function-enumerator = &lt;2&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio3 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* SODIMM 58 - USER_LED_2_GREEN */</div><div class='add'>+		led-3 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_DEBUG;</div><div class='add'>+			function-enumerator = &lt;2&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio3 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin SPI_1 */</div><div class='add'>+&amp;ecspi2 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi2&gt;, &lt;&amp;pinctrl_tpm_cs&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 13 GPIO_ACTIVE_LOW&gt;, &lt;&amp;gpio3 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	tpm@1 {</div><div class='add'>+		compatible = "infineon,slb9670", "tcg,tpm_tis-spi";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_tpm_irq&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+		interrupts = &lt;14 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		spi-max-frequency = &lt;18500000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* EEPROM on Mallow */</div><div class='add'>+&amp;eeprom_carrier_board {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin ETH_1 */</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Temperature sensor on Mallow */</div><div class='add'>+&amp;hwmon_temp {</div><div class='add'>+	compatible = "ti,tmp1075";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin I2C_2_DSI */</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin I2C_4_CSI */</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin I2C_1 */</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin PCIE_1 */</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin PWM_3_DSI */</div><div class='add'>+&amp;pwm1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin PWM_1 */</div><div class='add'>+&amp;pwm2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin PWM_2 */</div><div class='add'>+&amp;pwm3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin UART_3 */</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin UART_1 */</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin UART_2 */</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin USB_1 */</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin USB_2 */</div><div class='add'>+&amp;usbotg2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin SD_1 */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_leds: ledsgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0	0x106&gt;, /* SODIMM 52 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1	0x106&gt;, /* SODIMM 54 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6	0x106&gt;, /* SODIMM 56 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7	0x106&gt;; /* SODIMM 58 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_tpm_cs: tpmcsgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2	0x146&gt;; /* SODIMM 64 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_tpm_irq: tpmirqgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_NAND_DQS_GPIO3_IO14	0x141&gt;; /* SODIMM 66 */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dahlia.dts b/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dahlia.dts<br/>new file mode 100644<br/>index 000000000000..d64ff378a152<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dahlia.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dahlia.dts</a></div><div class='hunk'>@@ -0,0 +1,18 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mm-verdin.dtsi"</div><div class='add'>+#include "imx8mm-verdin-nonwifi.dtsi"</div><div class='add'>+#include "imx8mm-verdin-dahlia.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Toradex Verdin iMX8M Mini on Dahlia Board";</div><div class='add'>+	compatible = "toradex,verdin-imx8mm-nonwifi-dahlia",</div><div class='add'>+		     "toradex,verdin-imx8mm-nonwifi",</div><div class='add'>+		     "toradex,verdin-imx8mm",</div><div class='add'>+		     "fsl,imx8mm";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dev.dts b/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dev.dts<br/>new file mode 100644<br/>index 000000000000..6ae71ecac8de<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dev.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dev.dts</a></div><div class='hunk'>@@ -0,0 +1,18 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mm-verdin.dtsi"</div><div class='add'>+#include "imx8mm-verdin-nonwifi.dtsi"</div><div class='add'>+#include "imx8mm-verdin-dev.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Toradex Verdin iMX8M Mini on Verdin Development Board";</div><div class='add'>+	compatible = "toradex,verdin-imx8mm-nonwifi-dev",</div><div class='add'>+		     "toradex,verdin-imx8mm-nonwifi",</div><div class='add'>+		     "toradex,verdin-imx8mm",</div><div class='add'>+		     "fsl,imx8mm";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-ivy.dts b/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-ivy.dts<br/>new file mode 100644<br/>index 000000000000..82b34a12ee2b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-ivy.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-ivy.dts</a></div><div class='hunk'>@@ -0,0 +1,18 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mm-verdin.dtsi"</div><div class='add'>+#include "imx8mm-verdin-nonwifi.dtsi"</div><div class='add'>+#include "imx8mm-verdin-ivy.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Toradex Verdin iMX8M Mini on Ivy";</div><div class='add'>+	compatible = "toradex,verdin-imx8mm-nonwifi-ivy",</div><div class='add'>+		     "toradex,verdin-imx8mm-nonwifi",</div><div class='add'>+		     "toradex,verdin-imx8mm",</div><div class='add'>+		     "fsl,imx8mm";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-mallow.dts b/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-mallow.dts<br/>new file mode 100644<br/>index 000000000000..1b1999f3a80e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-mallow.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-mallow.dts</a></div><div class='hunk'>@@ -0,0 +1,18 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mm-verdin.dtsi"</div><div class='add'>+#include "imx8mm-verdin-nonwifi.dtsi"</div><div class='add'>+#include "imx8mm-verdin-mallow.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Toradex Verdin iMX8M Mini on Mallow";</div><div class='add'>+	compatible = "toradex,verdin-imx8mm-nonwifi-mallow",</div><div class='add'>+		     "toradex,verdin-imx8mm-nonwifi",</div><div class='add'>+		     "toradex,verdin-imx8mm",</div><div class='add'>+		     "fsl,imx8mm";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-yavia.dts b/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-yavia.dts<br/>new file mode 100644<br/>index 000000000000..c71825ecf2ea<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-yavia.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-yavia.dts</a></div><div class='hunk'>@@ -0,0 +1,18 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mm-verdin.dtsi"</div><div class='add'>+#include "imx8mm-verdin-nonwifi.dtsi"</div><div class='add'>+#include "imx8mm-verdin-yavia.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Toradex Verdin iMX8M Mini on Yavia Board";</div><div class='add'>+	compatible = "toradex,verdin-imx8mm-nonwifi-yavia",</div><div class='add'>+		     "toradex,verdin-imx8mm-nonwifi",</div><div class='add'>+		     "toradex,verdin-imx8mm",</div><div class='add'>+		     "fsl,imx8mm";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi.dtsi<br/>new file mode 100644<br/>index 000000000000..1e0f87c7a609<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi.dtsi</a></div><div class='hunk'>@@ -0,0 +1,75 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;gpio3 {</div><div class='add'>+	gpio-line-names = "SODIMM_52",</div><div class='add'>+			  "SODIMM_54",</div><div class='add'>+			  "SODIMM_64",</div><div class='add'>+			  "SODIMM_21",</div><div class='add'>+			  "SODIMM_206",</div><div class='add'>+			  "SODIMM_76",</div><div class='add'>+			  "SODIMM_56",</div><div class='add'>+			  "SODIMM_58",</div><div class='add'>+			  "SODIMM_60",</div><div class='add'>+			  "SODIMM_62",</div><div class='add'>+			  "SODIMM_162",</div><div class='add'>+			  "SODIMM_164",</div><div class='add'>+			  "SODIMM_166",</div><div class='add'>+			  "SODIMM_168",</div><div class='add'>+			  "SODIMM_66",</div><div class='add'>+			  "SODIMM_17",</div><div class='add'>+			  "",</div><div class='add'>+			  "SODIMM_156",</div><div class='add'>+			  "SODIMM_160",</div><div class='add'>+			  "SODIMM_244",</div><div class='add'>+			  "",</div><div class='add'>+			  "SODIMM_48",</div><div class='add'>+			  "SODIMM_44",</div><div class='add'>+			  "SODIMM_42",</div><div class='add'>+			  "SODIMM_46";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	gpio-line-names = "SODIMM_102",</div><div class='add'>+			  "SODIMM_90",</div><div class='add'>+			  "SODIMM_92",</div><div class='add'>+			  "SODIMM_94",</div><div class='add'>+			  "SODIMM_96",</div><div class='add'>+			  "SODIMM_100",</div><div class='add'>+			  "SODIMM_148",</div><div class='add'>+			  "SODIMM_152",</div><div class='add'>+			  "SODIMM_154",</div><div class='add'>+			  "SODIMM_174",</div><div class='add'>+			  "SODIMM_120",</div><div class='add'>+			  "SODIMM_104",</div><div class='add'>+			  "SODIMM_106",</div><div class='add'>+			  "SODIMM_108",</div><div class='add'>+			  "SODIMM_112",</div><div class='add'>+			  "SODIMM_114",</div><div class='add'>+			  "SODIMM_116",</div><div class='add'>+			  "SODIMM_150",</div><div class='add'>+			  "SODIMM_118",</div><div class='add'>+			  "",</div><div class='add'>+			  "SODIMM_88",</div><div class='add'>+			  "SODIMM_149",</div><div class='add'>+			  "SODIMM_147",</div><div class='add'>+			  "SODIMM_36",</div><div class='add'>+			  "SODIMM_32",</div><div class='add'>+			  "SODIMM_30",</div><div class='add'>+			  "SODIMM_34",</div><div class='add'>+			  "SODIMM_38",</div><div class='add'>+			  "SODIMM_252",</div><div class='add'>+			  "SODIMM_133",</div><div class='add'>+			  "SODIMM_135",</div><div class='add'>+			  "SODIMM_129";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dts b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dts<br/>new file mode 100644<br/>index 000000000000..d424c475cba1<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dts</a></div><div class='hunk'>@@ -0,0 +1,18 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mm-verdin.dtsi"</div><div class='add'>+#include "imx8mm-verdin-wifi.dtsi"</div><div class='add'>+#include "imx8mm-verdin-dahlia.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Toradex Verdin iMX8M Mini WB on Dahlia Board";</div><div class='add'>+	compatible = "toradex,verdin-imx8mm-wifi-dahlia",</div><div class='add'>+		     "toradex,verdin-imx8mm-wifi",</div><div class='add'>+		     "toradex,verdin-imx8mm",</div><div class='add'>+		     "fsl,imx8mm";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dev.dts b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dev.dts<br/>new file mode 100644<br/>index 000000000000..ef952021832e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dev.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dev.dts</a></div><div class='hunk'>@@ -0,0 +1,18 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mm-verdin.dtsi"</div><div class='add'>+#include "imx8mm-verdin-wifi.dtsi"</div><div class='add'>+#include "imx8mm-verdin-dev.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Toradex Verdin iMX8M Mini WB on Verdin Development Board";</div><div class='add'>+	compatible = "toradex,verdin-imx8mm-wifi-dev",</div><div class='add'>+		     "toradex,verdin-imx8mm-wifi",</div><div class='add'>+		     "toradex,verdin-imx8mm",</div><div class='add'>+		     "fsl,imx8mm";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-ivy.dts b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-ivy.dts<br/>new file mode 100644<br/>index 000000000000..3369ba852b5c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-ivy.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-ivy.dts</a></div><div class='hunk'>@@ -0,0 +1,18 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mm-verdin.dtsi"</div><div class='add'>+#include "imx8mm-verdin-wifi.dtsi"</div><div class='add'>+#include "imx8mm-verdin-ivy.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Toradex Verdin iMX8M Mini WB on Ivy";</div><div class='add'>+	compatible = "toradex,verdin-imx8mm-wifi-ivy",</div><div class='add'>+		     "toradex,verdin-imx8mm-wifi",</div><div class='add'>+		     "toradex,verdin-imx8mm",</div><div class='add'>+		     "fsl,imx8mm";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-mallow.dts b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-mallow.dts<br/>new file mode 100644<br/>index 000000000000..2916145f31bb<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-mallow.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-mallow.dts</a></div><div class='hunk'>@@ -0,0 +1,18 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mm-verdin.dtsi"</div><div class='add'>+#include "imx8mm-verdin-wifi.dtsi"</div><div class='add'>+#include "imx8mm-verdin-mallow.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Toradex Verdin iMX8M Mini WB on Mallow";</div><div class='add'>+	compatible = "toradex,verdin-imx8mm-wifi-mallow",</div><div class='add'>+		     "toradex,verdin-imx8mm-wifi",</div><div class='add'>+		     "toradex,verdin-imx8mm",</div><div class='add'>+		     "fsl,imx8mm";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-yavia.dts b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-yavia.dts<br/>new file mode 100644<br/>index 000000000000..fe39de9310d6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-yavia.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-yavia.dts</a></div><div class='hunk'>@@ -0,0 +1,18 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mm-verdin.dtsi"</div><div class='add'>+#include "imx8mm-verdin-wifi.dtsi"</div><div class='add'>+#include "imx8mm-verdin-yavia.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Toradex Verdin iMX8M Mini WB on Yavia Board";</div><div class='add'>+	compatible = "toradex,verdin-imx8mm-wifi-yavia",</div><div class='add'>+		     "toradex,verdin-imx8mm-wifi",</div><div class='add'>+		     "toradex,verdin-imx8mm",</div><div class='add'>+		     "fsl,imx8mm";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi.dtsi<br/>new file mode 100644<br/>index 000000000000..017db9eab256<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi.dtsi</a></div><div class='hunk'>@@ -0,0 +1,94 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	reg_wifi_en: regulator-wifi-en {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;gpio3 25 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_wifi_pwr_en&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "PDn_AW-CM276NF";</div><div class='add'>+		startup-delay-us = &lt;2000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio3 {</div><div class='add'>+	gpio-line-names = "SODIMM_52",</div><div class='add'>+			  "SODIMM_54",</div><div class='add'>+			  "SODIMM_64",</div><div class='add'>+			  "SODIMM_21",</div><div class='add'>+			  "SODIMM_206",</div><div class='add'>+			  "SODIMM_76",</div><div class='add'>+			  "SODIMM_56",</div><div class='add'>+			  "SODIMM_58",</div><div class='add'>+			  "SODIMM_60",</div><div class='add'>+			  "SODIMM_62",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "SODIMM_66",</div><div class='add'>+			  "SODIMM_17",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "SODIMM_244",</div><div class='add'>+			  "",</div><div class='add'>+			  "SODIMM_48",</div><div class='add'>+			  "SODIMM_44",</div><div class='add'>+			  "SODIMM_42",</div><div class='add'>+			  "SODIMM_46";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	gpio-line-names = "SODIMM_102",</div><div class='add'>+			  "SODIMM_90",</div><div class='add'>+			  "SODIMM_92",</div><div class='add'>+			  "SODIMM_94",</div><div class='add'>+			  "SODIMM_96",</div><div class='add'>+			  "SODIMM_100",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "SODIMM_120",</div><div class='add'>+			  "SODIMM_104",</div><div class='add'>+			  "SODIMM_106",</div><div class='add'>+			  "SODIMM_108",</div><div class='add'>+			  "SODIMM_112",</div><div class='add'>+			  "SODIMM_114",</div><div class='add'>+			  "SODIMM_116",</div><div class='add'>+			  "",</div><div class='add'>+			  "SODIMM_118",</div><div class='add'>+			  "",</div><div class='add'>+			  "SODIMM_88",</div><div class='add'>+			  "SODIMM_149",</div><div class='add'>+			  "SODIMM_147",</div><div class='add'>+			  "SODIMM_36",</div><div class='add'>+			  "SODIMM_32",</div><div class='add'>+			  "SODIMM_30",</div><div class='add'>+			  "SODIMM_34",</div><div class='add'>+			  "SODIMM_38",</div><div class='add'>+			  "SODIMM_252",</div><div class='add'>+			  "SODIMM_133",</div><div class='add'>+			  "SODIMM_135",</div><div class='add'>+			  "SODIMM_129";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* On-module Wi-Fi */</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	keep-power-in-suspend;</div><div class='add'>+	non-removable;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;, &lt;&amp;pinctrl_wifi_ctrl&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;, &lt;&amp;pinctrl_wifi_ctrl&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;, &lt;&amp;pinctrl_wifi_ctrl&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_wifi_en&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-yavia.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-yavia.dtsi<br/>new file mode 100644<br/>index 000000000000..763f069e8405<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-verdin-yavia.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-verdin-yavia.dtsi</a></div><div class='hunk'>@@ -0,0 +1,174 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_leds_yavia&gt;;</div><div class='add'>+</div><div class='add'>+		/* SODIMM 52 - LD1_RED */</div><div class='add'>+		led-0 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			function = LED_FUNCTION_DEBUG;</div><div class='add'>+			function-enumerator = &lt;1&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio3 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+		/* SODIMM 54 - LD1_GREEN */</div><div class='add'>+		led-1 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_DEBUG;</div><div class='add'>+			function-enumerator = &lt;1&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio3 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+		/* SODIMM 56 - LD1_BLUE */</div><div class='add'>+		led-2 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			function = LED_FUNCTION_DEBUG;</div><div class='add'>+			function-enumerator = &lt;1&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio3 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+		/* SODIMM 58 - LD2_RED */</div><div class='add'>+		led-3 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			function = LED_FUNCTION_DEBUG;</div><div class='add'>+			function-enumerator = &lt;2&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio3 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+		/* SODIMM 60 - LD2_GREEN */</div><div class='add'>+		led-4 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_DEBUG;</div><div class='add'>+			function-enumerator = &lt;2&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio3 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+		/* SODIMM 62 - LD2_BLUE */</div><div class='add'>+		led-5 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			function = LED_FUNCTION_DEBUG;</div><div class='add'>+			function-enumerator = &lt;2&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio3 9 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin SPI_1 */</div><div class='add'>+&amp;ecspi2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* EEPROM on display adapter boards */</div><div class='add'>+&amp;eeprom_display_adapter {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* EEPROM on Verdin yavia board */</div><div class='add'>+&amp;eeprom_carrier_board {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpios_ext_yavia&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio5 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ctrl_sleep_moci&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hwmon_temp {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin I2C_1 */</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin PCIE_1 */</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin PWM_3_DSI */</div><div class='add'>+&amp;pwm1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin PWM_1 */</div><div class='add'>+&amp;pwm2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin PWM_2 */</div><div class='add'>+&amp;pwm3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin UART_3 */</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin UART_1 */</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin UART_2 */</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin USB_1 */</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin USB_2 */</div><div class='add'>+&amp;usbotg2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin SD_1 */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_leds_yavia: ledsyaviagrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0		0x106	/* SODIMM 52 */</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1	0x106	/* SODIMM 54 */</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6	0x106	/* SODIMM 56 */</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7	0x106	/* SODIMM 58 */</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8	0x106	/* SODIMM 60 */</div><div class='add'>+			MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9	0x106	/* SODIMM 62 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpios_ext_yavia: gpiosextyaviagrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2	0x106	/* SODIMM 64 */</div><div class='add'>+			MX8MM_IOMUXC_NAND_DQS_GPIO3_IO14	0x106	/* SODIMM 66 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi<br/>new file mode 100644<br/>index 000000000000..1594ce9182a5<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi</a></div><div class='hunk'>@@ -0,0 +1,1332 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/phy/phy-imx8-pcie.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pwm/pwm.h&gt;</div><div class='add'>+#include "imx8mm.dtsi"</div><div class='add'>+#include "imx8mm-overdrive.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		rtc0 = &amp;rtc_i2c;</div><div class='add'>+		rtc1 = &amp;snvs_rtc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Fixed clock dedicated to SPI CAN controller */</div><div class='add'>+	clk40m: oscillator {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;40000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_keys&gt;;</div><div class='add'>+</div><div class='add'>+		key-wakeup {</div><div class='add'>+			debounce-interval = &lt;10&gt;;</div><div class='add'>+			/* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */</div><div class='add'>+			gpios = &lt;&amp;gpio4 28 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			label = "Wake-Up";</div><div class='add'>+			linux,code = &lt;KEY_WAKEUP&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdmi_connector: hdmi-connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		ddc-i2c-bus = &lt;&amp;i2c2&gt;;</div><div class='add'>+		/* Verdin PWM_3_DSI (SODIMM 19) */</div><div class='add'>+		hpd-gpios = &lt;&amp;gpio1 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		label = "hdmi";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pwm_3_dsi_hpd_gpio&gt;;</div><div class='add'>+		type = "a";</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Carrier Board Supplies */</div><div class='add'>+	reg_1p8v: regulator-1p8v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-name = "+V1.8_SW";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3p3v: regulator-3p3v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "+V3.3_SW";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_5p0v: regulator-5p0v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-name = "+V5_SW";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Non PMIC On-module Supplies */</div><div class='add'>+	reg_ethphy: regulator-ethphy {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;gpio2 20 GPIO_ACTIVE_HIGH&gt;; /* PMIC_EN_ETH */</div><div class='add'>+		off-on-delay-us = &lt;500000&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_eth&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "On-module +V3.3_ETH";</div><div class='add'>+		startup-delay-us = &lt;200000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * By default we enable CTRL_SLEEP_MOCI#, this is required to have</div><div class='add'>+	 * peripherals on the carrier board powered.</div><div class='add'>+	 * If more granularity or power saving is required this can be disabled</div><div class='add'>+	 * in the carrier board device tree files.</div><div class='add'>+	 */</div><div class='add'>+	reg_force_sleep_moci: regulator-force-sleep-moci {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		enable-active-high;</div><div class='add'>+		/* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */</div><div class='add'>+		gpio = &lt;&amp;gpio5 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-name = "CTRL_SLEEP_MOCI#";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb_otg1_vbus: regulator-usb-otg1 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		enable-active-high;</div><div class='add'>+		/* Verdin USB_1_EN (SODIMM 155) */</div><div class='add'>+		gpio = &lt;&amp;gpio1 12 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usb1_en&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-name = "USB_1_EN";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb_otg2_vbus: regulator-usb-otg2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		enable-active-high;</div><div class='add'>+		/* Verdin USB_2_EN (SODIMM 185) */</div><div class='add'>+		gpio = &lt;&amp;gpio1 14 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usb2_en&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-name = "USB_2_EN";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		enable-active-high;</div><div class='add'>+		/* Verdin SD_1_PWR_EN (SODIMM 76) */</div><div class='add'>+		gpio = &lt;&amp;gpio3 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		off-on-delay-us = &lt;100000&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usdhc2_pwr_en&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "+V3.3_SD";</div><div class='add'>+		startup-delay-us = &lt;20000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc {</div><div class='add'>+		compatible = "regulator-gpio";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usdhc2_vsel&gt;;</div><div class='add'>+		gpios = &lt;&amp;gpio1 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		states = &lt;1800000 0x1&gt;,</div><div class='add'>+			 &lt;3300000 0x0&gt;;</div><div class='add'>+		regulator-name = "PMIC_USDHC_VSELECT";</div><div class='add'>+		vin-supply = &lt;&amp;reg_nvcc_sd&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		/* Use the kernel configuration settings instead */</div><div class='add'>+		/delete-node/ linux,cma;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_vdd_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_vdd_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_vdd_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_vdd_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu_alert0 {</div><div class='add'>+	temperature = &lt;95000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu_crit0 {</div><div class='add'>+	temperature = &lt;105000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ddrc {</div><div class='add'>+	operating-points-v2 = &lt;&amp;ddrc_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+	ddrc_opp_table: opp-table {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		opp-25000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;25000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-100000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;100000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-750000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;750000000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin SPI_1 */</div><div class='add'>+&amp;ecspi2 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 13 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* On-module SPI */</div><div class='add'>+&amp;ecspi3 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 25 GPIO_ACTIVE_LOW&gt;, &lt;&amp;gpio4 19 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi3&gt;, &lt;&amp;pinctrl_tpm_spi_cs&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* Verdin CAN_1 */</div><div class='add'>+	can1: can@0 {</div><div class='add'>+		compatible = "microchip,mcp251xfd";</div><div class='add'>+		clocks = &lt;&amp;clk40m&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;gpio1 6 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_can1_int&gt;;</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;8500000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	verdin_som_tpm: tpm@1 {</div><div class='add'>+		compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";</div><div class='add'>+		reg = &lt;0x1&gt;;</div><div class='add'>+		spi-max-frequency = &lt;36000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin ETH_1 (On-module PHY) */</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	fsl,magic-packet;</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-supply = &lt;&amp;reg_ethphy&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_fec1_sleep&gt;;</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@7 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+			interrupts = &lt;10 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			micrel,led-mode = &lt;0&gt;;</div><div class='add'>+			reg = &lt;7&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin QSPI_1 */</div><div class='add'>+&amp;flexspi {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexspi0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	gpio-line-names = "SODIMM_216",</div><div class='add'>+			  "SODIMM_19",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "PMIC_USDHC_VSELECT",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "SODIMM_220",</div><div class='add'>+			  "SODIMM_222",</div><div class='add'>+			  "",</div><div class='add'>+			  "SODIMM_218",</div><div class='add'>+			  "SODIMM_155",</div><div class='add'>+			  "SODIMM_157",</div><div class='add'>+			  "SODIMM_185",</div><div class='add'>+			  "SODIMM_187";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio2 {</div><div class='add'>+	gpio-line-names = "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "SODIMM_84",</div><div class='add'>+			  "SODIMM_78",</div><div class='add'>+			  "SODIMM_74",</div><div class='add'>+			  "SODIMM_80",</div><div class='add'>+			  "SODIMM_82",</div><div class='add'>+			  "SODIMM_70",</div><div class='add'>+			  "SODIMM_72";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio5 {</div><div class='add'>+	gpio-line-names = "SODIMM_131",</div><div class='add'>+			  "",</div><div class='add'>+			  "SODIMM_91",</div><div class='add'>+			  "SODIMM_16",</div><div class='add'>+			  "SODIMM_15",</div><div class='add'>+			  "SODIMM_208",</div><div class='add'>+			  "SODIMM_137",</div><div class='add'>+			  "SODIMM_139",</div><div class='add'>+			  "SODIMM_141",</div><div class='add'>+			  "SODIMM_143",</div><div class='add'>+			  "SODIMM_196",</div><div class='add'>+			  "SODIMM_200",</div><div class='add'>+			  "SODIMM_198",</div><div class='add'>+			  "SODIMM_202",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "SODIMM_55",</div><div class='add'>+			  "SODIMM_53",</div><div class='add'>+			  "SODIMM_95",</div><div class='add'>+			  "SODIMM_93",</div><div class='add'>+			  "SODIMM_14",</div><div class='add'>+			  "SODIMM_12",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "SODIMM_210",</div><div class='add'>+			  "SODIMM_212",</div><div class='add'>+			  "SODIMM_151",</div><div class='add'>+			  "SODIMM_153";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* On-module I2C */</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c1_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	single-master;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pca9450: pmic@25 {</div><div class='add'>+		compatible = "nxp,pca9450a";</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		/* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */</div><div class='add'>+		interrupts = &lt;3 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * The bootloader is expected to switch on the I2C level shifter for the TLA2024 ADC</div><div class='add'>+		 * behind this PMIC.</div><div class='add'>+		 */</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			reg_vdd_soc: BUCK1 {</div><div class='add'>+				nxp,dvs-run-voltage = &lt;850000&gt;;</div><div class='add'>+				nxp,dvs-standby-voltage = &lt;800000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-name = "On-module +VDD_SOC (BUCK1)";</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vdd_arm: BUCK2 {</div><div class='add'>+				nxp,dvs-run-voltage = &lt;950000&gt;;</div><div class='add'>+				nxp,dvs-standby-voltage = &lt;850000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1050000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;805000&gt;;</div><div class='add'>+				regulator-name = "On-module +VDD_ARM (BUCK2)";</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vdd_dram: BUCK3 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;805000&gt;;</div><div class='add'>+				regulator-name = "On-module +VDD_GPU_VPU_DDR (BUCK3)";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vdd_3v3: BUCK4 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "On-module +V3.3 (BUCK4)";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vdd_1v8: BUCK5 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "PWR_1V8_MOCI (BUCK5)";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_nvcc_dram: BUCK6 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-name = "On-module +VDD_DDR (BUCK6)";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_nvcc_snvs: LDO1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "On-module +V1.8_SNVS (LDO1)";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vdd_snvs: LDO2 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-name = "On-module +V0.8_SNVS (LDO2)";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vdda: LDO3 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "On-module +V1.8A (LDO3)";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vdd_phy: LDO4 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-name = "On-module +V0.9_MIPI (LDO4)";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_nvcc_sd: LDO5 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "On-module +V3.3_1.8_SD (LDO5)";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rtc_i2c: rtc@32 {</div><div class='add'>+		compatible = "epson,rx8130";</div><div class='add'>+		reg = &lt;0x32&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	verdin_som_adc: adc@49 {</div><div class='add'>+		compatible = "ti,ads1015";</div><div class='add'>+		reg = &lt;0x49&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		#io-channel-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		/* Verdin I2C_1 (ADC_4 - ADC_3) */</div><div class='add'>+		channel@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			ti,datarate = &lt;4&gt;;</div><div class='add'>+			ti,gain = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* Verdin I2C_1 (ADC_4 - ADC_1) */</div><div class='add'>+		channel@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			ti,datarate = &lt;4&gt;;</div><div class='add'>+			ti,gain = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* Verdin I2C_1 (ADC_3 - ADC_1) */</div><div class='add'>+		channel@2 {</div><div class='add'>+			reg = &lt;2&gt;;</div><div class='add'>+			ti,datarate = &lt;4&gt;;</div><div class='add'>+			ti,gain = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* Verdin I2C_1 (ADC_2 - ADC_1) */</div><div class='add'>+		channel@3 {</div><div class='add'>+			reg = &lt;3&gt;;</div><div class='add'>+			ti,datarate = &lt;4&gt;;</div><div class='add'>+			ti,gain = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* Verdin I2C_1 ADC_4 */</div><div class='add'>+		channel@4 {</div><div class='add'>+			reg = &lt;4&gt;;</div><div class='add'>+			ti,datarate = &lt;4&gt;;</div><div class='add'>+			ti,gain = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* Verdin I2C_1 ADC_3 */</div><div class='add'>+		channel@5 {</div><div class='add'>+			reg = &lt;5&gt;;</div><div class='add'>+			ti,datarate = &lt;4&gt;;</div><div class='add'>+			ti,gain = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* Verdin I2C_1 ADC_2 */</div><div class='add'>+		channel@6 {</div><div class='add'>+			reg = &lt;6&gt;;</div><div class='add'>+			ti,datarate = &lt;4&gt;;</div><div class='add'>+			ti,gain = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* Verdin I2C_1 ADC_1 */</div><div class='add'>+		channel@7 {</div><div class='add'>+			reg = &lt;7&gt;;</div><div class='add'>+			ti,datarate = &lt;4&gt;;</div><div class='add'>+			ti,gain = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@50 {</div><div class='add'>+		compatible = "st,24c02", "atmel,24c02";</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin I2C_2_DSI */</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c2_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	single-master;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin I2C_3_HDMI N/A */</div><div class='add'>+</div><div class='add'>+/* Verdin I2C_4_CSI */</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c3_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	single-master;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin I2C_1 */</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c4&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c4_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	single-master;</div><div class='add'>+</div><div class='add'>+	gpio_expander_21: gpio-expander@21 {</div><div class='add'>+		compatible = "nxp,pcal6416";</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		reg = &lt;0x21&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lvds_ti_sn65dsi84: bridge@2c {</div><div class='add'>+		compatible = "ti,sn65dsi84";</div><div class='add'>+		/* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */</div><div class='add'>+		/* Verdin GPIO_10_DSI (SODIMM 21) */</div><div class='add'>+		enable-gpios = &lt;&amp;gpio3 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_10_dsi&gt;;</div><div class='add'>+		reg = &lt;0x2c&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Current measurement into module VCC */</div><div class='add'>+	hwmon: hwmon@40 {</div><div class='add'>+		compatible = "ti,ina219";</div><div class='add'>+		reg = &lt;0x40&gt;;</div><div class='add'>+		shunt-resistor = &lt;10000&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdmi_lontium_lt8912: hdmi@48 {</div><div class='add'>+		compatible = "lontium,lt8912b";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_10_dsi&gt;;</div><div class='add'>+		reg = &lt;0x48&gt;;</div><div class='add'>+		/* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */</div><div class='add'>+		/* Verdin GPIO_10_DSI (SODIMM 21) */</div><div class='add'>+		reset-gpios = &lt;&amp;gpio3 3 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	atmel_mxt_ts: touch@4a {</div><div class='add'>+		compatible = "atmel,maxtouch";</div><div class='add'>+		/*</div><div class='add'>+		 * Verdin GPIO_9_DSI</div><div class='add'>+		 * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI84 IRQ albeit currently unused)</div><div class='add'>+		 */</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+		interrupts = &lt;15 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_9_dsi&gt;, &lt;&amp;pinctrl_i2s_2_bclk_touch_reset&gt;;</div><div class='add'>+		reg = &lt;0x4a&gt;;</div><div class='add'>+		/* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */</div><div class='add'>+		reset-gpios = &lt;&amp;gpio3 23 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Temperature sensor on carrier board */</div><div class='add'>+	hwmon_temp: sensor@4f {</div><div class='add'>+		compatible = "ti,tmp75c";</div><div class='add'>+		reg = &lt;0x4f&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* EEPROM on display adapter (MIPI DSI Display Adapter) */</div><div class='add'>+	eeprom_display_adapter: eeprom@50 {</div><div class='add'>+		compatible = "st,24c02", "atmel,24c02";</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* EEPROM on carrier board */</div><div class='add'>+	eeprom_carrier_board: eeprom@57 {</div><div class='add'>+		compatible = "st,24c02", "atmel,24c02";</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+		reg = &lt;0x57&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin PCIE_1 */</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_PCIE1_AUX&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MM_CLK_PCIE1_CTRL&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL2_50M&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MM_SYS_PLL2_250M&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;10000000&gt;, &lt;250000000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie0&gt;;</div><div class='add'>+	/* PCIE_1_RESET# (SODIMM 244) */</div><div class='add'>+	reset-gpio = &lt;&amp;gpio3 19 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	clocks = &lt;&amp;clk IMX8MM_CLK_PCIE1_PHY&gt;;</div><div class='add'>+	clock-names = "ref";</div><div class='add'>+	fsl,clkreq-unsupported;</div><div class='add'>+	fsl,refclk-pad-mode = &lt;IMX8_PCIE_REFCLK_PAD_OUTPUT&gt;;</div><div class='add'>+	fsl,tx-deemph-gen1 = &lt;0x2d&gt;;</div><div class='add'>+	fsl,tx-deemph-gen2 = &lt;0xf&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin PWM_3_DSI */</div><div class='add'>+&amp;pwm1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm_1&gt;;</div><div class='add'>+	#pwm-cells = &lt;3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin PWM_1 */</div><div class='add'>+&amp;pwm2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm_2&gt;;</div><div class='add'>+	#pwm-cells = &lt;3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin PWM_2 */</div><div class='add'>+&amp;pwm3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm_3&gt;;</div><div class='add'>+	#pwm-cells = &lt;3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin I2S_1 */</div><div class='add'>+&amp;sai2 {</div><div class='add'>+	#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MM_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;24576000&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MM_CLK_SAI2&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;snvs_pwrkey {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin UART_3, used as the Linux console */</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin UART_1 */</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin UART_2 */</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Verdin UART_4</div><div class='add'>+ * Resource allocated to M4 by default, must not be accessed from Cortex-A35 or you get an OOPS</div><div class='add'>+ */</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart4&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin USB_1 */</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	adp-disable;</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	hnp-disable;</div><div class='add'>+	samsung,picophy-dc-vol-level-adjust = &lt;7&gt;;</div><div class='add'>+	samsung,picophy-pre-emp-curr-control = &lt;3&gt;;</div><div class='add'>+	srp-disable;</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usb_otg1_vbus&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin USB_2 */</div><div class='add'>+&amp;usbotg2 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	samsung,picophy-dc-vol-level-adjust = &lt;7&gt;;</div><div class='add'>+	samsung,picophy-pre-emp-curr-control = &lt;3&gt;;</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usb_otg2_vbus&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbphynop1 {</div><div class='add'>+	vcc-supply = &lt;&amp;reg_vdd_3v3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbphynop2 {</div><div class='add'>+	power-domains = &lt;&amp;pgc_otg2&gt;;</div><div class='add'>+	vcc-supply = &lt;&amp;reg_vdd_3v3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* On-module eMMC */</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	keep-power-in-suspend;</div><div class='add'>+	non-removable;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1_200mhz&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin SD_1 */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_cd&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_cd&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_cd&gt;;</div><div class='add'>+	pinctrl-3 = &lt;&amp;pinctrl_usdhc2_sleep&gt;, &lt;&amp;pinctrl_usdhc2_cd_sleep&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_usdhc2_vqmmc&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio1&gt;, &lt;&amp;pinctrl_gpio2&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_gpio3&gt;, &lt;&amp;pinctrl_gpio4&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_gpio7&gt;, &lt;&amp;pinctrl_gpio8&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_gpio_hog1&gt;, &lt;&amp;pinctrl_gpio_hog2&gt;, &lt;&amp;pinctrl_gpio_hog3&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl_can1_int: can1intgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6		0x146&gt;;	/* CAN_1_SPI_INT#_1.8V */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_can2_int: can2intgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x106&gt;;	/* CAN_2_SPI_INT#_1.8V, unused */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1		0x106&gt;;	/* SODIMM 256 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi2: ecspi2grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO		0x6&gt;,	/* SODIMM 198 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI		0x6&gt;,	/* SODIMM 200 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK		0x6&gt;,	/* SODIMM 196 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13		0x6&gt;;	/* SODIMM 202 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi3: ecspi3grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5		0x146&gt;,	/* CAN_2_SPI_CS#_1.8V */</div><div class='add'>+			&lt;MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK		0x6&gt;,	/* CAN_SPI_SCK_1.8V */</div><div class='add'>+			&lt;MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI		0x6&gt;,	/* CAN_SPI_MOSI_1.8V */</div><div class='add'>+			&lt;MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO		0x6&gt;,	/* CAN_SPI_MISO_1.8V */</div><div class='add'>+			&lt;MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25		0x6&gt;;	/* CAN_1_SPI_CS_1.8V# */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec1: fec1grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_ENET_MDC_ENET1_MDC		0x3&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x146&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec1_sleep: fec1-sleepgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_ENET_MDC_ENET1_MDC		0x3&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21		0x1f&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20		0x1f&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19		0x1f&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18		0x1f&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23		0x1f&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22		0x1f&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x106&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexspi0: flexspi0grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK		0x106&gt;,	/* SODIMM 52 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B		0x106&gt;,	/* SODIMM 54 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B		0x106&gt;,	/* SODIMM 64 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0		0x106&gt;,	/* SODIMM 56 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1		0x106&gt;,	/* SODIMM 58 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2		0x106&gt;,	/* SODIMM 60 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3		0x106&gt;,	/* SODIMM 62 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS		0x106&gt;;	/* SODIMM 66 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio1: gpio1grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4		0x106&gt;;	/* SODIMM 206 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio2: gpio2grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5		0x106&gt;;	/* SODIMM 208 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio3: gpio3grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26		0x106&gt;;	/* SODIMM 210 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio4: gpio4grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27		0x106&gt;;	/* SODIMM 212 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio5: gpio5grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0		0x106&gt;;	/* SODIMM 216 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio6: gpio6grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x106&gt;;	/* SODIMM 218 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio7: gpio7grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8		0x106&gt;;	/* SODIMM 220 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio8: gpio8grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x106&gt;;	/* SODIMM 222 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Verdin GPIO_9_DSI (pulled-up as active-low) */</div><div class='add'>+	pinctrl_gpio_9_dsi: gpio9dsigrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15		0x1c6&gt;;	/* SODIMM 17 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Verdin GPIO_10_DSI (pulled-up as active-low) */</div><div class='add'>+	pinctrl_gpio_10_dsi: gpio10dsigrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3		0x146&gt;;	/* SODIMM 21 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio_hog1: gpiohog1grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20		0x106&gt;,	/* SODIMM 88 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1		0x106&gt;,	/* SODIMM 90 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2		0x106&gt;,	/* SODIMM 92 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3		0x106&gt;,	/* SODIMM 94 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4		0x106&gt;,	/* SODIMM 96 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5		0x106&gt;,	/* SODIMM 100 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0		0x106&gt;,	/* SODIMM 102 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11		0x106&gt;,	/* SODIMM 104 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12		0x106&gt;,	/* SODIMM 106 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13		0x106&gt;,	/* SODIMM 108 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14		0x106&gt;,	/* SODIMM 112 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15		0x106&gt;,	/* SODIMM 114 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16		0x106&gt;,	/* SODIMM 116 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18		0x106&gt;,	/* SODIMM 118 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10		0x106&gt;;	/* SODIMM 120 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio_hog2: gpiohog2grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2		0x106&gt;;	/* SODIMM 91 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio_hog3: gpiohog3grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13		0x146&gt;,	/* SODIMM 157 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15		0x146&gt;;	/* SODIMM 187 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio_keys: gpiokeysgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28		0x146&gt;;	/* SODIMM 252 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* On-module I2C */</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL			0x40000146&gt;,	/* PMIC_I2C_SCL */</div><div class='add'>+			&lt;MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA			0x40000146&gt;;	/* PMIC_I2C_SDA */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1_gpio: i2c1gpiogrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14		0x146&gt;,	/* PMIC_I2C_SCL */</div><div class='add'>+			&lt;MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15		0x146&gt;;	/* PMIC_I2C_SDA */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Verdin I2C_4_CSI */</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL			0x40000146&gt;,	/* SODIMM 55 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA			0x40000146&gt;;	/* SODIMM 53 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2_gpio: i2c2gpiogrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16		0x146&gt;,	/* SODIMM 55 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17		0x146&gt;;	/* SODIMM 53 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Verdin I2C_2_DSI */</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL			0x40000146&gt;,	/* SODIMM 95 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA			0x40000146&gt;;	/* SODIMM 93 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3_gpio: i2c3gpiogrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18		0x146&gt;,	/* SODIMM 95 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19		0x146&gt;;	/* SODIMM 93 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Verdin I2C_1 */</div><div class='add'>+	pinctrl_i2c4: i2c4grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL			0x40000146&gt;,	/* SODIMM 14 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA			0x40000146&gt;;	/* SODIMM 12 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4_gpio: i2c4gpiogrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20		0x146&gt;,	/* SODIMM 14 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21		0x146&gt;;	/* SODIMM 12 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Verdin I2S_2_BCLK (TOUCH_RESET#) */</div><div class='add'>+	pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23		0x6&gt;;	/* SODIMM 42 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Verdin I2S_2_D_OUT shared with SAI5 */</div><div class='add'>+	pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24		0x6&gt;;	/* SODIMM 46 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie0: pcie0grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19		0x6&gt;,	/* SODIMM 244 */</div><div class='add'>+			/* PMIC_EN_PCIe_CLK, unused */</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19		0x6&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: pmicirqgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x141&gt;;	/* PMIC_INT# */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Verdin PWM_3_DSI shared with GPIO1_IO1 */</div><div class='add'>+	pinctrl_pwm_1: pwm1grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT		0x6&gt;;	/* SODIMM 19 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm_2: pwm2grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT			0x6&gt;;	/* SODIMM 15 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm_3: pwm3grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT			0x6&gt;;	/* SODIMM 16 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM1_OUT */</div><div class='add'>+	pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsihpdgpiogrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1		0x106&gt;;	/* SODIMM 19 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_eth: regethgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD2_WP_GPIO2_IO20			0x146&gt;;	/* PMIC_EN_ETH */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usb1_en: regusb1engrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12		0x106&gt;;	/* SODIMM 155 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usb2_en: regusb2engrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14		0x106&gt;;	/* SODIMM 185 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai2: sai2grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK		0x6&gt;,	/* SODIMM 38 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK		0x6&gt;,	/* SODIMM 30 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC		0x6&gt;,	/* SODIMM 32 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0		0x6&gt;,	/* SODIMM 36 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0		0x6&gt;;	/* SODIMM 34 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai5: sai5grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0		0x6&gt;,	/* SODIMM 48 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC		0x6&gt;,	/* SODIMM 44 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK		0x6&gt;,	/* SODIMM 42 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0		0x6&gt;;	/* SODIMM 46 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* control signal for optional ATTPM20P or SE050 */</div><div class='add'>+	pinctrl_tpm_spi_cs: tpmspicsgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19		0x106&gt;;	/* PMIC_TPM_ENA */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_tsp: tspgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6		0x6&gt;,	/* SODIMM 148 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7		0x6&gt;,	/* SODIMM 152 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8		0x6&gt;,	/* SODIMM 154 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9		0x146&gt;,	/* SODIMM 174 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17		0x6&gt;;	/* SODIMM 150 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX		0x146&gt;,	/* SODIMM 147 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX		0x146&gt;;	/* SODIMM 149 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B		0x146&gt;,	/* SODIMM 133 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B		0x146&gt;,	/* SODIMM 135 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX		0x146&gt;,	/* SODIMM 131 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX		0x146&gt;;	/* SODIMM 129 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: uart3grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B	0x146&gt;,	/* SODIMM 141 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX		0x146&gt;,	/* SODIMM 139 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX		0x146&gt;,	/* SODIMM 137 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B	0x146&gt;;	/* SODIMM 143 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart4: uart4grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX		0x146&gt;,	/* SODIMM 151 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX		0x146&gt;;	/* SODIMM 153 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x190&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d0&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x1d0&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x1d0&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x1d0&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x1d0&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4		0x1d0&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5		0x1d0&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6		0x1d0&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7		0x1d0&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B	0x1d1&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x190&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x194&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d4&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x1d4&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x1d4&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x1d4&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x1d4&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4		0x1d4&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5		0x1d4&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6		0x1d4&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7		0x1d4&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B	0x1d1&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x194&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x196&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d6&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x1d6&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x1d6&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x1d6&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x1d6&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4		0x1d6&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5		0x1d6&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6		0x1d6&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7		0x1d6&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B	0x1d1&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x196&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_cd: usdhc2cdgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x6&gt;;	/* SODIMM 84 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x0&gt;;	/* SODIMM 84 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5		0x6&gt;;	/* SODIMM 76 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_vsel: usdhc2vselgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4	0x10&gt;; /* PMIC_USDHC_VSELECT */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Note: Due to ERR050080 we use discrete external on-module resistors pulling-up to the</div><div class='add'>+	 * on-module +V3.3_1.8_SD (LDO5) rail and explicitly disable the internal pull-ups here.</div><div class='add'>+	 */</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x90&gt;,	/* SODIMM 78 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x90&gt;,	/* SODIMM 74 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x90&gt;,	/* SODIMM 80 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x90&gt;,	/* SODIMM 82 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x90&gt;,	/* SODIMM 70 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x90&gt;;	/* SODIMM 72 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x94&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x94&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x94&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x94&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x94&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x94&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x96&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x96&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x96&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x96&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x96&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x96&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Avoid backfeeding with removed card power */</div><div class='add'>+	pinctrl_usdhc2_sleep: usdhc2slpgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x0&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x0&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x0&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x0&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x0&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * On-module Wi-Fi/BT or type specific SDHC interface</div><div class='add'>+	 * (e.g. on X52 extension slot of Verdin Development Board)</div><div class='add'>+	 */</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x150&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x150&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x150&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x150&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x150&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x150&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x154&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x154&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x154&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x154&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x154&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x154&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x156&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x156&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x156&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x156&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x156&gt;,</div><div class='add'>+			&lt;MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x156&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0x166&gt;;	/* PMIC_WDI */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wifi_ctrl: wifictrlgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16		0x46&gt;,	/* WIFI_WKUP_BT */</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9		0x146&gt;,	/* WIFI_W_WKUP_HOST */</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20		0x46&gt;;	/* WIFI_WKUP_WLAN */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wifi_i2s: bti2sgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK		0x6&gt;,	/* WIFI_TX_BCLK */</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0		0x6&gt;,	/* WIFI_TX_DATA0 */</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC		0x6&gt;,	/* WIFI_TX_SYNC */</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0		0x6&gt;;	/* WIFI_RX_DATA0 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wifi_pwr_en: wifipwrengrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25		0x6&gt;;	/* PMIC_EN_WIFI */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi<br/>index cc7152ecedd9..fc3cd639310e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mm.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mm.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mm.dtsi</a></div><div class='hunk'>@@ -7,6 +7,8 @@</div><div class='ctx'> #include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/input/input.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/power/imx8mm-power.h&gt;</div><div class='add'>+#include &lt;dt-bindings/reset/imx8mq-reset.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/thermal/thermal.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "imx8mm-pinfunc.h"</div><div class='hunk'>@@ -18,10 +20,18 @@</div><div class='ctx'> </div><div class='ctx'> 	aliases {</div><div class='ctx'> 		ethernet0 = &amp;fec1;</div><div class='add'>+		gpio0 = &amp;gpio1;</div><div class='add'>+		gpio1 = &amp;gpio2;</div><div class='add'>+		gpio2 = &amp;gpio3;</div><div class='add'>+		gpio3 = &amp;gpio4;</div><div class='add'>+		gpio4 = &amp;gpio5;</div><div class='ctx'> 		i2c0 = &amp;i2c1;</div><div class='ctx'> 		i2c1 = &amp;i2c2;</div><div class='ctx'> 		i2c2 = &amp;i2c3;</div><div class='ctx'> 		i2c3 = &amp;i2c4;</div><div class='add'>+		mmc0 = &amp;usdhc1;</div><div class='add'>+		mmc1 = &amp;usdhc2;</div><div class='add'>+		mmc2 = &amp;usdhc3;</div><div class='ctx'> 		serial0 = &amp;uart1;</div><div class='ctx'> 		serial1 = &amp;uart2;</div><div class='ctx'> 		serial2 = &amp;uart3;</div><div class='hunk'>@@ -29,14 +39,6 @@</div><div class='ctx'> 		spi0 = &amp;ecspi1;</div><div class='ctx'> 		spi1 = &amp;ecspi2;</div><div class='ctx'> 		spi2 = &amp;ecspi3;</div><div class='del'>-		mmc0 = &amp;usdhc1;</div><div class='del'>-		mmc1 = &amp;usdhc2;</div><div class='del'>-		mmc2 = &amp;usdhc3;</div><div class='del'>-		gpio0 = &amp;gpio1;</div><div class='del'>-		gpio1 = &amp;gpio2;</div><div class='del'>-		gpio2 = &amp;gpio3;</div><div class='del'>-		gpio3 = &amp;gpio4;</div><div class='del'>-		gpio4 = &amp;gpio5;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	cpus {</div><div class='hunk'>@@ -60,9 +62,14 @@</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			reg = &lt;0x0&gt;;</div><div class='del'>-			clock-latency = &lt;61036&gt;; /* two CLK32 periods */</div><div class='ctx'> 			clocks = &lt;&amp;clk IMX8MM_CLK_ARM&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;A53_L2&gt;;</div><div class='ctx'> 			operating-points-v2 = &lt;&amp;a53_opp_table&gt;;</div><div class='ctx'> 			nvmem-cells = &lt;&amp;cpu_speed_grade&gt;;</div><div class='hunk'>@@ -75,9 +82,14 @@</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			reg = &lt;0x1&gt;;</div><div class='del'>-			clock-latency = &lt;61036&gt;; /* two CLK32 periods */</div><div class='ctx'> 			clocks = &lt;&amp;clk IMX8MM_CLK_ARM&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;A53_L2&gt;;</div><div class='ctx'> 			operating-points-v2 = &lt;&amp;a53_opp_table&gt;;</div><div class='ctx'> 			cpu-idle-states = &lt;&amp;cpu_pd_wait&gt;;</div><div class='hunk'>@@ -88,9 +100,14 @@</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			reg = &lt;0x2&gt;;</div><div class='del'>-			clock-latency = &lt;61036&gt;; /* two CLK32 periods */</div><div class='ctx'> 			clocks = &lt;&amp;clk IMX8MM_CLK_ARM&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;A53_L2&gt;;</div><div class='ctx'> 			operating-points-v2 = &lt;&amp;a53_opp_table&gt;;</div><div class='ctx'> 			cpu-idle-states = &lt;&amp;cpu_pd_wait&gt;;</div><div class='hunk'>@@ -101,9 +118,14 @@</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			reg = &lt;0x3&gt;;</div><div class='del'>-			clock-latency = &lt;61036&gt;; /* two CLK32 periods */</div><div class='ctx'> 			clocks = &lt;&amp;clk IMX8MM_CLK_ARM&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;A53_L2&gt;;</div><div class='ctx'> 			operating-points-v2 = &lt;&amp;a53_opp_table&gt;;</div><div class='ctx'> 			cpu-idle-states = &lt;&amp;cpu_pd_wait&gt;;</div><div class='hunk'>@@ -112,6 +134,11 @@</div><div class='ctx'> </div><div class='ctx'> 		A53_L2: l2-cache0 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x80000&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;512&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -129,7 +156,7 @@</div><div class='ctx'> </div><div class='ctx'> 		opp-1600000000 {</div><div class='ctx'> 			opp-hz = /bits/ 64 &lt;1600000000&gt;;</div><div class='del'>-			opp-microvolt = &lt;900000&gt;;</div><div class='add'>+			opp-microvolt = &lt;950000&gt;;</div><div class='ctx'> 			opp-supported-hw = &lt;0xc&gt;, &lt;0x7&gt;;</div><div class='ctx'> 			clock-latency-ns = &lt;150000&gt;;</div><div class='ctx'> 			opp-suspend;</div><div class='hunk'>@@ -182,7 +209,7 @@</div><div class='ctx'> 	clk_ext4: clock-ext4 {</div><div class='ctx'> 		compatible = "fixed-clock";</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='del'>-		clock-frequency= &lt;133000000&gt;;</div><div class='add'>+		clock-frequency = &lt;133000000&gt;;</div><div class='ctx'> 		clock-output-names = "clk_ext4";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -192,18 +219,17 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	pmu {</div><div class='del'>-		compatible = "arm,armv8-pmuv3";</div><div class='add'>+		compatible = "arm,cortex-a53-pmu";</div><div class='ctx'> 		interrupts = &lt;GIC_PPI 7</div><div class='del'>-			     (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='del'>-		interrupt-affinity = &lt;&amp;A53_0&gt;, &lt;&amp;A53_1&gt;, &lt;&amp;A53_2&gt;, &lt;&amp;A53_3&gt;;</div><div class='add'>+			     (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	timer {</div><div class='ctx'> 		compatible = "arm,armv8-timer";</div><div class='del'>-		interrupts = &lt;GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)&gt;, /* Physical Secure */</div><div class='del'>-			     &lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)&gt;, /* Physical Non-Secure */</div><div class='del'>-			     &lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)&gt;, /* Virtual */</div><div class='del'>-			     &lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)&gt;; /* Hypervisor */</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;, /* Physical Secure */</div><div class='add'>+			     &lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;, /* Physical Non-Secure */</div><div class='add'>+			     &lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;, /* Virtual */</div><div class='add'>+			     &lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;; /* Hypervisor */</div><div class='ctx'> 		clock-frequency = &lt;8000000&gt;;</div><div class='ctx'> 		arm,no-tick-in-suspend;</div><div class='ctx'> 	};</div><div class='hunk'>@@ -241,98 +267,161 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	usbphynop1: usbphynop1 {</div><div class='add'>+		#phy-cells = &lt;0&gt;;</div><div class='ctx'> 		compatible = "usb-nop-xceiv";</div><div class='ctx'> 		clocks = &lt;&amp;clk IMX8MM_CLK_USB_PHY_REF&gt;;</div><div class='ctx'> 		assigned-clocks = &lt;&amp;clk IMX8MM_CLK_USB_PHY_REF&gt;;</div><div class='ctx'> 		assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL1_100M&gt;;</div><div class='ctx'> 		clock-names = "main_clk";</div><div class='add'>+		power-domains = &lt;&amp;pgc_otg1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	usbphynop2: usbphynop2 {</div><div class='add'>+		#phy-cells = &lt;0&gt;;</div><div class='ctx'> 		compatible = "usb-nop-xceiv";</div><div class='ctx'> 		clocks = &lt;&amp;clk IMX8MM_CLK_USB_PHY_REF&gt;;</div><div class='ctx'> 		assigned-clocks = &lt;&amp;clk IMX8MM_CLK_USB_PHY_REF&gt;;</div><div class='ctx'> 		assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL1_100M&gt;;</div><div class='ctx'> 		clock-names = "main_clk";</div><div class='add'>+		power-domains = &lt;&amp;pgc_otg2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	soc@0 {</div><div class='del'>-		compatible = "simple-bus";</div><div class='add'>+	soc: soc@0 {</div><div class='add'>+		compatible = "fsl,imx8mm-soc", "simple-bus";</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;1&gt;;</div><div class='ctx'> 		ranges = &lt;0x0 0x0 0x0 0x3e000000&gt;;</div><div class='add'>+		dma-ranges = &lt;0x40000000 0x0 0x40000000 0xc0000000&gt;;</div><div class='add'>+		nvmem-cells = &lt;&amp;imx8mm_uid&gt;;</div><div class='add'>+		nvmem-cell-names = "soc_unique_id";</div><div class='ctx'> </div><div class='ctx'> 		aips1: bus@30000000 {</div><div class='ctx'> 			compatible = "fsl,aips-bus", "simple-bus";</div><div class='del'>-			reg = &lt;0x301f0000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x30000000 0x400000&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;1&gt;;</div><div class='ctx'> 			ranges = &lt;0x30000000 0x30000000 0x400000&gt;;</div><div class='ctx'> </div><div class='del'>-			sai1: sai@30010000 {</div><div class='del'>-				compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";</div><div class='del'>-				reg = &lt;0x30010000 0x10000&gt;;</div><div class='del'>-				interrupts = &lt;GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-				clocks = &lt;&amp;clk IMX8MM_CLK_SAI1_IPG&gt;,</div><div class='del'>-					 &lt;&amp;clk IMX8MM_CLK_SAI1_ROOT&gt;,</div><div class='del'>-					 &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;, &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;;</div><div class='del'>-				clock-names = "bus", "mclk1", "mclk2", "mclk3";</div><div class='del'>-				dmas = &lt;&amp;sdma2 0 2 0&gt;, &lt;&amp;sdma2 1 2 0&gt;;</div><div class='del'>-				dma-names = "rx", "tx";</div><div class='del'>-				status = "disabled";</div><div class='del'>-			};</div><div class='add'>+			spba2: spba-bus@30000000 {</div><div class='add'>+				compatible = "fsl,spba-bus", "simple-bus";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;1&gt;;</div><div class='add'>+				reg = &lt;0x30000000 0x100000&gt;;</div><div class='add'>+				ranges;</div><div class='add'>+</div><div class='add'>+				sai1: sai@30010000 {</div><div class='add'>+					#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+					compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";</div><div class='add'>+					reg = &lt;0x30010000 0x10000&gt;;</div><div class='add'>+					interrupts = &lt;GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					clocks = &lt;&amp;clk IMX8MM_CLK_SAI1_IPG&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MM_CLK_SAI1_ROOT&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;, &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;;</div><div class='add'>+					clock-names = "bus", "mclk1", "mclk2", "mclk3";</div><div class='add'>+					dmas = &lt;&amp;sdma2 0 2 0&gt;, &lt;&amp;sdma2 1 2 0&gt;;</div><div class='add'>+					dma-names = "rx", "tx";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-			sai2: sai@30020000 {</div><div class='del'>-				compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";</div><div class='del'>-				reg = &lt;0x30020000 0x10000&gt;;</div><div class='del'>-				interrupts = &lt;GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-				clocks = &lt;&amp;clk IMX8MM_CLK_SAI2_IPG&gt;,</div><div class='del'>-					&lt;&amp;clk IMX8MM_CLK_SAI2_ROOT&gt;,</div><div class='del'>-					&lt;&amp;clk IMX8MM_CLK_DUMMY&gt;, &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;;</div><div class='del'>-				clock-names = "bus", "mclk1", "mclk2", "mclk3";</div><div class='del'>-				dmas = &lt;&amp;sdma2 2 2 0&gt;, &lt;&amp;sdma2 3 2 0&gt;;</div><div class='del'>-				dma-names = "rx", "tx";</div><div class='del'>-				status = "disabled";</div><div class='del'>-			};</div><div class='add'>+				sai2: sai@30020000 {</div><div class='add'>+					#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+					compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";</div><div class='add'>+					reg = &lt;0x30020000 0x10000&gt;;</div><div class='add'>+					interrupts = &lt;GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					clocks = &lt;&amp;clk IMX8MM_CLK_SAI2_IPG&gt;,</div><div class='add'>+						&lt;&amp;clk IMX8MM_CLK_SAI2_ROOT&gt;,</div><div class='add'>+						&lt;&amp;clk IMX8MM_CLK_DUMMY&gt;, &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;;</div><div class='add'>+					clock-names = "bus", "mclk1", "mclk2", "mclk3";</div><div class='add'>+					dmas = &lt;&amp;sdma2 2 2 0&gt;, &lt;&amp;sdma2 3 2 0&gt;;</div><div class='add'>+					dma-names = "rx", "tx";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-			sai3: sai@30030000 {</div><div class='del'>-				#sound-dai-cells = &lt;0&gt;;</div><div class='del'>-				compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";</div><div class='del'>-				reg = &lt;0x30030000 0x10000&gt;;</div><div class='del'>-				interrupts = &lt;GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-				clocks = &lt;&amp;clk IMX8MM_CLK_SAI3_IPG&gt;,</div><div class='del'>-					 &lt;&amp;clk IMX8MM_CLK_SAI3_ROOT&gt;,</div><div class='del'>-					 &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;, &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;;</div><div class='del'>-				clock-names = "bus", "mclk1", "mclk2", "mclk3";</div><div class='del'>-				dmas = &lt;&amp;sdma2 4 2 0&gt;, &lt;&amp;sdma2 5 2 0&gt;;</div><div class='del'>-				dma-names = "rx", "tx";</div><div class='del'>-				status = "disabled";</div><div class='del'>-			};</div><div class='add'>+				sai3: sai@30030000 {</div><div class='add'>+					#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+					compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";</div><div class='add'>+					reg = &lt;0x30030000 0x10000&gt;;</div><div class='add'>+					interrupts = &lt;GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					clocks = &lt;&amp;clk IMX8MM_CLK_SAI3_IPG&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MM_CLK_SAI3_ROOT&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;, &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;;</div><div class='add'>+					clock-names = "bus", "mclk1", "mclk2", "mclk3";</div><div class='add'>+					dmas = &lt;&amp;sdma2 4 2 0&gt;, &lt;&amp;sdma2 5 2 0&gt;;</div><div class='add'>+					dma-names = "rx", "tx";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-			sai5: sai@30050000 {</div><div class='del'>-				compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";</div><div class='del'>-				reg = &lt;0x30050000 0x10000&gt;;</div><div class='del'>-				interrupts = &lt;GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-				clocks = &lt;&amp;clk IMX8MM_CLK_SAI5_IPG&gt;,</div><div class='del'>-					 &lt;&amp;clk IMX8MM_CLK_SAI5_ROOT&gt;,</div><div class='del'>-					 &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;, &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;;</div><div class='del'>-				clock-names = "bus", "mclk1", "mclk2", "mclk3";</div><div class='del'>-				dmas = &lt;&amp;sdma2 8 2 0&gt;, &lt;&amp;sdma2 9 2 0&gt;;</div><div class='del'>-				dma-names = "rx", "tx";</div><div class='del'>-				status = "disabled";</div><div class='del'>-			};</div><div class='add'>+				sai5: sai@30050000 {</div><div class='add'>+					#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+					compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";</div><div class='add'>+					reg = &lt;0x30050000 0x10000&gt;;</div><div class='add'>+					interrupts = &lt;GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					clocks = &lt;&amp;clk IMX8MM_CLK_SAI5_IPG&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MM_CLK_SAI5_ROOT&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;, &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;;</div><div class='add'>+					clock-names = "bus", "mclk1", "mclk2", "mclk3";</div><div class='add'>+					dmas = &lt;&amp;sdma2 8 2 0&gt;, &lt;&amp;sdma2 9 2 0&gt;;</div><div class='add'>+					dma-names = "rx", "tx";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-			sai6: sai@30060000 {</div><div class='del'>-				compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";</div><div class='del'>-				reg = &lt;0x30060000 0x10000&gt;;</div><div class='del'>-				interrupts = &lt;GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-				clocks = &lt;&amp;clk IMX8MM_CLK_SAI6_IPG&gt;,</div><div class='del'>-					 &lt;&amp;clk IMX8MM_CLK_SAI6_ROOT&gt;,</div><div class='del'>-					 &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;, &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;;</div><div class='del'>-				clock-names = "bus", "mclk1", "mclk2", "mclk3";</div><div class='del'>-				dmas = &lt;&amp;sdma2 10 2 0&gt;, &lt;&amp;sdma2 11 2 0&gt;;</div><div class='del'>-				dma-names = "rx", "tx";</div><div class='del'>-				status = "disabled";</div><div class='add'>+				sai6: sai@30060000 {</div><div class='add'>+					#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+					compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";</div><div class='add'>+					reg = &lt;0x30060000 0x10000&gt;;</div><div class='add'>+					interrupts = &lt;GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					clocks = &lt;&amp;clk IMX8MM_CLK_SAI6_IPG&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MM_CLK_SAI6_ROOT&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;, &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;;</div><div class='add'>+					clock-names = "bus", "mclk1", "mclk2", "mclk3";</div><div class='add'>+					dmas = &lt;&amp;sdma2 10 2 0&gt;, &lt;&amp;sdma2 11 2 0&gt;;</div><div class='add'>+					dma-names = "rx", "tx";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				micfil: audio-controller@30080000 {</div><div class='add'>+					compatible = "fsl,imx8mm-micfil";</div><div class='add'>+					reg = &lt;0x30080000 0x10000&gt;;</div><div class='add'>+					interrupts = &lt;GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+						     &lt;GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+						     &lt;GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+						     &lt;GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					clocks = &lt;&amp;clk IMX8MM_CLK_PDM_IPG&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MM_CLK_PDM_ROOT&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MM_AUDIO_PLL1_OUT&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MM_AUDIO_PLL2_OUT&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MM_CLK_EXT3&gt;;</div><div class='add'>+					clock-names = "ipg_clk", "ipg_clk_app",</div><div class='add'>+						      "pll8k", "pll11k", "clkext3";</div><div class='add'>+					dmas = &lt;&amp;sdma2 24 25 0x80000000&gt;;</div><div class='add'>+					dma-names = "rx";</div><div class='add'>+					#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				spdif1: spdif@30090000 {</div><div class='add'>+					compatible = "fsl,imx35-spdif";</div><div class='add'>+					reg = &lt;0x30090000 0x10000&gt;;</div><div class='add'>+					interrupts = &lt;GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					clocks = &lt;&amp;clk IMX8MM_CLK_AUDIO_AHB&gt;, /* core */</div><div class='add'>+						 &lt;&amp;clk IMX8MM_CLK_24M&gt;, /* rxtx0 */</div><div class='add'>+						 &lt;&amp;clk IMX8MM_CLK_SPDIF1&gt;, /* rxtx1 */</div><div class='add'>+						 &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;, /* rxtx2 */</div><div class='add'>+						 &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;, /* rxtx3 */</div><div class='add'>+						 &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;, /* rxtx4 */</div><div class='add'>+						 &lt;&amp;clk IMX8MM_CLK_AUDIO_AHB&gt;, /* rxtx5 */</div><div class='add'>+						 &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;, /* rxtx6 */</div><div class='add'>+						 &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;, /* rxtx7 */</div><div class='add'>+						 &lt;&amp;clk IMX8MM_CLK_DUMMY&gt;; /* spba */</div><div class='add'>+					clock-names = "core", "rxtx0",</div><div class='add'>+						      "rxtx1", "rxtx2",</div><div class='add'>+						      "rxtx3", "rxtx4",</div><div class='add'>+						      "rxtx5", "rxtx6",</div><div class='add'>+						      "rxtx7", "spba";</div><div class='add'>+					dmas = &lt;&amp;sdma2 28 18 0&gt;, &lt;&amp;sdma2 29 18 0&gt;;</div><div class='add'>+					dma-names = "rx", "tx";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			gpio1: gpio@30200000 {</div><div class='hunk'>@@ -404,6 +493,8 @@</div><div class='ctx'> 				compatible = "fsl,imx8mm-tmu";</div><div class='ctx'> 				reg = &lt;0x30260000 0x10000&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;clk IMX8MM_CLK_TMU_ROOT&gt;;</div><div class='add'>+				nvmem-cells = &lt;&amp;tmu_calib&gt;;</div><div class='add'>+				nvmem-cell-names = "calib";</div><div class='ctx'> 				#thermal-sensor-cells = &lt;0&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -458,12 +549,12 @@</div><div class='ctx'> 				reg = &lt;0x30330000 0x10000&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			gpr: iomuxc-gpr@30340000 {</div><div class='add'>+			gpr: syscon@30340000 {</div><div class='ctx'> 				compatible = "fsl,imx8mm-iomuxc-gpr", "syscon";</div><div class='ctx'> 				reg = &lt;0x30340000 0x10000&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			ocotp: ocotp-ctrl@30350000 {</div><div class='add'>+			ocotp: efuse@30350000 {</div><div class='ctx'> 				compatible = "fsl,imx8mm-ocotp", "syscon";</div><div class='ctx'> 				reg = &lt;0x30350000 0x10000&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;clk IMX8MM_CLK_OCOTP_ROOT&gt;;</div><div class='hunk'>@@ -471,14 +562,40 @@</div><div class='ctx'> 				#address-cells = &lt;1&gt;;</div><div class='ctx'> 				#size-cells = &lt;1&gt;;</div><div class='ctx'> </div><div class='del'>-				cpu_speed_grade: speed-grade@10 {</div><div class='add'>+				/*</div><div class='add'>+				 * The register address below maps to the MX8M</div><div class='add'>+				 * Fusemap Description Table entries this way.</div><div class='add'>+				 * Assuming</div><div class='add'>+				 *   reg = &lt;ADDR SIZE&gt;;</div><div class='add'>+				 * then</div><div class='add'>+				 *   Fuse Address = (ADDR * 4) + 0x400</div><div class='add'>+				 * Note that if SIZE is greater than 4, then</div><div class='add'>+				 * each subsequent fuse is located at offset</div><div class='add'>+				 * +0x10 in Fusemap Description Table (e.g.</div><div class='add'>+				 * reg = &lt;0x4 0x8&gt; describes fuses 0x410 and</div><div class='add'>+				 * 0x420).</div><div class='add'>+				 */</div><div class='add'>+				imx8mm_uid: unique-id@4 { /* 0x410-0x420 */</div><div class='add'>+					reg = &lt;0x4 0x8&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_speed_grade: speed-grade@10 { /* 0x440 */</div><div class='ctx'> 					reg = &lt;0x10 4&gt;;</div><div class='ctx'> 				};</div><div class='add'>+</div><div class='add'>+				tmu_calib: calib@3c { /* 0x4f0 */</div><div class='add'>+					reg = &lt;0x3c 4&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				fec_mac_address: mac-address@90 { /* 0x640 */</div><div class='add'>+					reg = &lt;0x90 6&gt;;</div><div class='add'>+				};</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			anatop: anatop@30360000 {</div><div class='del'>-				compatible = "fsl,imx8mm-anatop", "syscon";</div><div class='add'>+			anatop: clock-controller@30360000 {</div><div class='add'>+				compatible = "fsl,imx8mm-anatop";</div><div class='ctx'> 				reg = &lt;0x30360000 0x10000&gt;;</div><div class='add'>+				#clock-cells = &lt;1&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			snvs: snvs@30370000 {</div><div class='hunk'>@@ -505,32 +622,39 @@</div><div class='ctx'> 					wakeup-source;</div><div class='ctx'> 					status = "disabled";</div><div class='ctx'> 				};</div><div class='add'>+</div><div class='add'>+				snvs_lpgpr: snvs-lpgpr {</div><div class='add'>+					compatible = "fsl,imx8mm-snvs-lpgpr",</div><div class='add'>+						     "fsl,imx7d-snvs-lpgpr";</div><div class='add'>+				};</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			clk: clock-controller@30380000 {</div><div class='ctx'> 				compatible = "fsl,imx8mm-ccm";</div><div class='ctx'> 				reg = &lt;0x30380000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				#clock-cells = &lt;1&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;osc_32k&gt;, &lt;&amp;osc_24m&gt;, &lt;&amp;clk_ext1&gt;, &lt;&amp;clk_ext2&gt;,</div><div class='ctx'> 					 &lt;&amp;clk_ext3&gt;, &lt;&amp;clk_ext4&gt;;</div><div class='ctx'> 				clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",</div><div class='ctx'> 					      "clk_ext3", "clk_ext4";</div><div class='del'>-				assigned-clocks = &lt;&amp;clk IMX8MM_CLK_NOC&gt;,</div><div class='add'>+				assigned-clocks = &lt;&amp;clk IMX8MM_CLK_A53_SRC&gt;,</div><div class='add'>+						&lt;&amp;clk IMX8MM_CLK_A53_CORE&gt;,</div><div class='add'>+						&lt;&amp;clk IMX8MM_CLK_NOC&gt;,</div><div class='ctx'> 						&lt;&amp;clk IMX8MM_CLK_AUDIO_AHB&gt;,</div><div class='ctx'> 						&lt;&amp;clk IMX8MM_CLK_IPG_AUDIO_ROOT&gt;,</div><div class='ctx'> 						&lt;&amp;clk IMX8MM_SYS_PLL3&gt;,</div><div class='del'>-						&lt;&amp;clk IMX8MM_VIDEO_PLL1&gt;,</div><div class='del'>-						&lt;&amp;clk IMX8MM_AUDIO_PLL1&gt;,</div><div class='del'>-						&lt;&amp;clk IMX8MM_AUDIO_PLL2&gt;;</div><div class='del'>-				assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL3_OUT&gt;,</div><div class='add'>+						&lt;&amp;clk IMX8MM_AUDIO_PLL1&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL1_800M&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MM_ARM_PLL_OUT&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MM_SYS_PLL3_OUT&gt;,</div><div class='ctx'> 							 &lt;&amp;clk IMX8MM_SYS_PLL1_800M&gt;;</div><div class='del'>-				assigned-clock-rates = &lt;0&gt;,</div><div class='add'>+				assigned-clock-rates = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;,</div><div class='ctx'> 							&lt;400000000&gt;,</div><div class='ctx'> 							&lt;400000000&gt;,</div><div class='ctx'> 							&lt;750000000&gt;,</div><div class='del'>-							&lt;594000000&gt;,</div><div class='del'>-							&lt;393216000&gt;,</div><div class='del'>-							&lt;361267200&gt;;</div><div class='add'>+							&lt;393216000&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			src: reset-controller@30390000 {</div><div class='hunk'>@@ -539,11 +663,113 @@</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				#reset-cells = &lt;1&gt;;</div><div class='ctx'> 			};</div><div class='add'>+</div><div class='add'>+			gpc: gpc@303a0000 {</div><div class='add'>+				compatible = "fsl,imx8mm-gpc";</div><div class='add'>+				reg = &lt;0x303a0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+				pgc {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					pgc_hsiomix: power-domain@0 {</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						reg = &lt;IMX8MM_POWER_DOMAIN_HSIOMIX&gt;;</div><div class='add'>+						clocks = &lt;&amp;clk IMX8MM_CLK_USB_BUS&gt;;</div><div class='add'>+						assigned-clocks = &lt;&amp;clk IMX8MM_CLK_USB_BUS&gt;;</div><div class='add'>+						assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL2_500M&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					pgc_pcie: power-domain@1 {</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						reg = &lt;IMX8MM_POWER_DOMAIN_PCIE&gt;;</div><div class='add'>+						power-domains = &lt;&amp;pgc_hsiomix&gt;;</div><div class='add'>+						clocks = &lt;&amp;clk IMX8MM_CLK_PCIE1_ROOT&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					pgc_otg1: power-domain@2 {</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						reg = &lt;IMX8MM_POWER_DOMAIN_OTG1&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					pgc_otg2: power-domain@3 {</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						reg = &lt;IMX8MM_POWER_DOMAIN_OTG2&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					pgc_gpumix: power-domain@4 {</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						reg = &lt;IMX8MM_POWER_DOMAIN_GPUMIX&gt;;</div><div class='add'>+						clocks = &lt;&amp;clk IMX8MM_CLK_GPU_BUS_ROOT&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MM_CLK_GPU_AHB&gt;;</div><div class='add'>+						assigned-clocks = &lt;&amp;clk IMX8MM_CLK_GPU_AXI&gt;,</div><div class='add'>+								  &lt;&amp;clk IMX8MM_CLK_GPU_AHB&gt;;</div><div class='add'>+						assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL1_800M&gt;,</div><div class='add'>+									 &lt;&amp;clk IMX8MM_SYS_PLL1_800M&gt;;</div><div class='add'>+						assigned-clock-rates = &lt;800000000&gt;, &lt;400000000&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					pgc_gpu: power-domain@5 {</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						reg = &lt;IMX8MM_POWER_DOMAIN_GPU&gt;;</div><div class='add'>+						clocks = &lt;&amp;clk IMX8MM_CLK_GPU_AHB&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MM_CLK_GPU_BUS_ROOT&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MM_CLK_GPU2D_ROOT&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MM_CLK_GPU3D_ROOT&gt;;</div><div class='add'>+						resets = &lt;&amp;src IMX8MQ_RESET_GPU_RESET&gt;;</div><div class='add'>+						power-domains = &lt;&amp;pgc_gpumix&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					pgc_vpumix: power-domain@6 {</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						reg = &lt;IMX8MM_POWER_DOMAIN_VPUMIX&gt;;</div><div class='add'>+						clocks = &lt;&amp;clk IMX8MM_CLK_VPU_DEC_ROOT&gt;;</div><div class='add'>+						assigned-clocks = &lt;&amp;clk IMX8MM_CLK_VPU_BUS&gt;;</div><div class='add'>+						assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL1_800M&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					pgc_vpu_g1: power-domain@7 {</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						reg = &lt;IMX8MM_POWER_DOMAIN_VPUG1&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					pgc_vpu_g2: power-domain@8 {</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						reg = &lt;IMX8MM_POWER_DOMAIN_VPUG2&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					pgc_vpu_h1: power-domain@9 {</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						reg = &lt;IMX8MM_POWER_DOMAIN_VPUH1&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					pgc_dispmix: power-domain@10 {</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						reg = &lt;IMX8MM_POWER_DOMAIN_DISPMIX&gt;;</div><div class='add'>+						clocks = &lt;&amp;clk IMX8MM_CLK_DISP_APB_ROOT&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MM_CLK_DISP_AXI_ROOT&gt;;</div><div class='add'>+						assigned-clocks = &lt;&amp;clk IMX8MM_CLK_DISP_AXI&gt;,</div><div class='add'>+								  &lt;&amp;clk IMX8MM_CLK_DISP_APB&gt;;</div><div class='add'>+						assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL2_1000M&gt;,</div><div class='add'>+									 &lt;&amp;clk IMX8MM_SYS_PLL1_800M&gt;;</div><div class='add'>+						assigned-clock-rates = &lt;500000000&gt;, &lt;200000000&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					pgc_mipi: power-domain@11 {</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						reg = &lt;IMX8MM_POWER_DOMAIN_MIPI&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		aips2: bus@30400000 {</div><div class='ctx'> 			compatible = "fsl,aips-bus", "simple-bus";</div><div class='del'>-			reg = &lt;0x305f0000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x30400000 0x400000&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;1&gt;;</div><div class='ctx'> 			ranges = &lt;0x30400000 0x30400000 0x400000&gt;;</div><div class='hunk'>@@ -555,7 +781,7 @@</div><div class='ctx'> 				clocks = &lt;&amp;clk IMX8MM_CLK_PWM1_ROOT&gt;,</div><div class='ctx'> 					&lt;&amp;clk IMX8MM_CLK_PWM1_ROOT&gt;;</div><div class='ctx'> 				clock-names = "ipg", "per";</div><div class='del'>-				#pwm-cells = &lt;2&gt;;</div><div class='add'>+				#pwm-cells = &lt;3&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -566,7 +792,7 @@</div><div class='ctx'> 				clocks = &lt;&amp;clk IMX8MM_CLK_PWM2_ROOT&gt;,</div><div class='ctx'> 					 &lt;&amp;clk IMX8MM_CLK_PWM2_ROOT&gt;;</div><div class='ctx'> 				clock-names = "ipg", "per";</div><div class='del'>-				#pwm-cells = &lt;2&gt;;</div><div class='add'>+				#pwm-cells = &lt;3&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -577,7 +803,7 @@</div><div class='ctx'> 				clocks = &lt;&amp;clk IMX8MM_CLK_PWM3_ROOT&gt;,</div><div class='ctx'> 					 &lt;&amp;clk IMX8MM_CLK_PWM3_ROOT&gt;;</div><div class='ctx'> 				clock-names = "ipg", "per";</div><div class='del'>-				#pwm-cells = &lt;2&gt;;</div><div class='add'>+				#pwm-cells = &lt;3&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -588,7 +814,7 @@</div><div class='ctx'> 				clocks = &lt;&amp;clk IMX8MM_CLK_PWM4_ROOT&gt;,</div><div class='ctx'> 					 &lt;&amp;clk IMX8MM_CLK_PWM4_ROOT&gt;;</div><div class='ctx'> 				clock-names = "ipg", "per";</div><div class='del'>-				#pwm-cells = &lt;2&gt;;</div><div class='add'>+				#pwm-cells = &lt;3&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -603,86 +829,96 @@</div><div class='ctx'> </div><div class='ctx'> 		aips3: bus@30800000 {</div><div class='ctx'> 			compatible = "fsl,aips-bus", "simple-bus";</div><div class='del'>-			reg = &lt;0x309f0000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x30800000 0x400000&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;1&gt;;</div><div class='ctx'> 			ranges = &lt;0x30800000 0x30800000 0x400000&gt;,</div><div class='ctx'> 				 &lt;0x8000000 0x8000000 0x10000000&gt;;</div><div class='ctx'> </div><div class='del'>-			ecspi1: spi@30820000 {</div><div class='del'>-				compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";</div><div class='add'>+			spba1: spba-bus@30800000 {</div><div class='add'>+				compatible = "fsl,spba-bus", "simple-bus";</div><div class='ctx'> 				#address-cells = &lt;1&gt;;</div><div class='del'>-				#size-cells = &lt;0&gt;;</div><div class='del'>-				reg = &lt;0x30820000 0x10000&gt;;</div><div class='del'>-				interrupts = &lt;GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-				clocks = &lt;&amp;clk IMX8MM_CLK_ECSPI1_ROOT&gt;,</div><div class='del'>-					 &lt;&amp;clk IMX8MM_CLK_ECSPI1_ROOT&gt;;</div><div class='del'>-				clock-names = "ipg", "per";</div><div class='del'>-				dmas = &lt;&amp;sdma1 0 7 1&gt;, &lt;&amp;sdma1 1 7 2&gt;;</div><div class='del'>-				dma-names = "rx", "tx";</div><div class='del'>-				status = "disabled";</div><div class='del'>-			};</div><div class='add'>+				#size-cells = &lt;1&gt;;</div><div class='add'>+				reg = &lt;0x30800000 0x100000&gt;;</div><div class='add'>+				ranges;</div><div class='add'>+</div><div class='add'>+				ecspi1: spi@30820000 {</div><div class='add'>+					compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+					reg = &lt;0x30820000 0x10000&gt;;</div><div class='add'>+					interrupts = &lt;GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					clocks = &lt;&amp;clk IMX8MM_CLK_ECSPI1_ROOT&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MM_CLK_ECSPI1_ROOT&gt;;</div><div class='add'>+					clock-names = "ipg", "per";</div><div class='add'>+					dmas = &lt;&amp;sdma1 0 7 1&gt;, &lt;&amp;sdma1 1 7 2&gt;;</div><div class='add'>+					dma-names = "rx", "tx";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-			ecspi2: spi@30830000 {</div><div class='del'>-				compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";</div><div class='del'>-				#address-cells = &lt;1&gt;;</div><div class='del'>-				#size-cells = &lt;0&gt;;</div><div class='del'>-				reg = &lt;0x30830000 0x10000&gt;;</div><div class='del'>-				interrupts = &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-				clocks = &lt;&amp;clk IMX8MM_CLK_ECSPI2_ROOT&gt;,</div><div class='del'>-					 &lt;&amp;clk IMX8MM_CLK_ECSPI2_ROOT&gt;;</div><div class='del'>-				clock-names = "ipg", "per";</div><div class='del'>-				dmas = &lt;&amp;sdma1 2 7 1&gt;, &lt;&amp;sdma1 3 7 2&gt;;</div><div class='del'>-				dma-names = "rx", "tx";</div><div class='del'>-				status = "disabled";</div><div class='del'>-			};</div><div class='add'>+				ecspi2: spi@30830000 {</div><div class='add'>+					compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+					reg = &lt;0x30830000 0x10000&gt;;</div><div class='add'>+					interrupts = &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					clocks = &lt;&amp;clk IMX8MM_CLK_ECSPI2_ROOT&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MM_CLK_ECSPI2_ROOT&gt;;</div><div class='add'>+					clock-names = "ipg", "per";</div><div class='add'>+					dmas = &lt;&amp;sdma1 2 7 1&gt;, &lt;&amp;sdma1 3 7 2&gt;;</div><div class='add'>+					dma-names = "rx", "tx";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-			ecspi3: spi@30840000 {</div><div class='del'>-				compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";</div><div class='del'>-				#address-cells = &lt;1&gt;;</div><div class='del'>-				#size-cells = &lt;0&gt;;</div><div class='del'>-				reg = &lt;0x30840000 0x10000&gt;;</div><div class='del'>-				interrupts = &lt;GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-				clocks = &lt;&amp;clk IMX8MM_CLK_ECSPI3_ROOT&gt;,</div><div class='del'>-					 &lt;&amp;clk IMX8MM_CLK_ECSPI3_ROOT&gt;;</div><div class='del'>-				clock-names = "ipg", "per";</div><div class='del'>-				dmas = &lt;&amp;sdma1 4 7 1&gt;, &lt;&amp;sdma1 5 7 2&gt;;</div><div class='del'>-				dma-names = "rx", "tx";</div><div class='del'>-				status = "disabled";</div><div class='del'>-			};</div><div class='add'>+				ecspi3: spi@30840000 {</div><div class='add'>+					compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+					reg = &lt;0x30840000 0x10000&gt;;</div><div class='add'>+					interrupts = &lt;GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					clocks = &lt;&amp;clk IMX8MM_CLK_ECSPI3_ROOT&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MM_CLK_ECSPI3_ROOT&gt;;</div><div class='add'>+					clock-names = "ipg", "per";</div><div class='add'>+					dmas = &lt;&amp;sdma1 4 7 1&gt;, &lt;&amp;sdma1 5 7 2&gt;;</div><div class='add'>+					dma-names = "rx", "tx";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-			uart1: serial@30860000 {</div><div class='del'>-				compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";</div><div class='del'>-				reg = &lt;0x30860000 0x10000&gt;;</div><div class='del'>-				interrupts = &lt;GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-				clocks = &lt;&amp;clk IMX8MM_CLK_UART1_ROOT&gt;,</div><div class='del'>-					 &lt;&amp;clk IMX8MM_CLK_UART1_ROOT&gt;;</div><div class='del'>-				clock-names = "ipg", "per";</div><div class='del'>-				dmas = &lt;&amp;sdma1 22 4 0&gt;, &lt;&amp;sdma1 23 4 0&gt;;</div><div class='del'>-				dma-names = "rx", "tx";</div><div class='del'>-				status = "disabled";</div><div class='del'>-			};</div><div class='add'>+				uart1: serial@30860000 {</div><div class='add'>+					compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";</div><div class='add'>+					reg = &lt;0x30860000 0x10000&gt;;</div><div class='add'>+					interrupts = &lt;GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					clocks = &lt;&amp;clk IMX8MM_CLK_UART1_ROOT&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MM_CLK_UART1_ROOT&gt;;</div><div class='add'>+					clock-names = "ipg", "per";</div><div class='add'>+					dmas = &lt;&amp;sdma1 22 4 0&gt;, &lt;&amp;sdma1 23 4 0&gt;;</div><div class='add'>+					dma-names = "rx", "tx";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-			uart3: serial@30880000 {</div><div class='del'>-				compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";</div><div class='del'>-				reg = &lt;0x30880000 0x10000&gt;;</div><div class='del'>-				interrupts = &lt;GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-				clocks = &lt;&amp;clk IMX8MM_CLK_UART3_ROOT&gt;,</div><div class='del'>-					 &lt;&amp;clk IMX8MM_CLK_UART3_ROOT&gt;;</div><div class='del'>-				clock-names = "ipg", "per";</div><div class='del'>-				dmas = &lt;&amp;sdma1 26 4 0&gt;, &lt;&amp;sdma1 27 4 0&gt;;</div><div class='del'>-				dma-names = "rx", "tx";</div><div class='del'>-				status = "disabled";</div><div class='del'>-			};</div><div class='add'>+				uart3: serial@30880000 {</div><div class='add'>+					compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";</div><div class='add'>+					reg = &lt;0x30880000 0x10000&gt;;</div><div class='add'>+					interrupts = &lt;GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					clocks = &lt;&amp;clk IMX8MM_CLK_UART3_ROOT&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MM_CLK_UART3_ROOT&gt;;</div><div class='add'>+					clock-names = "ipg", "per";</div><div class='add'>+					dmas = &lt;&amp;sdma1 26 4 0&gt;, &lt;&amp;sdma1 27 4 0&gt;;</div><div class='add'>+					dma-names = "rx", "tx";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-			uart2: serial@30890000 {</div><div class='del'>-				compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";</div><div class='del'>-				reg = &lt;0x30890000 0x10000&gt;;</div><div class='del'>-				interrupts = &lt;GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-				clocks = &lt;&amp;clk IMX8MM_CLK_UART2_ROOT&gt;,</div><div class='del'>-					 &lt;&amp;clk IMX8MM_CLK_UART2_ROOT&gt;;</div><div class='del'>-				clock-names = "ipg", "per";</div><div class='del'>-				status = "disabled";</div><div class='add'>+				uart2: serial@30890000 {</div><div class='add'>+					compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";</div><div class='add'>+					reg = &lt;0x30890000 0x10000&gt;;</div><div class='add'>+					interrupts = &lt;GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					clocks = &lt;&amp;clk IMX8MM_CLK_UART2_ROOT&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MM_CLK_UART2_ROOT&gt;;</div><div class='add'>+					clock-names = "ipg", "per";</div><div class='add'>+					dmas = &lt;&amp;sdma1 24 4 0&gt;, &lt;&amp;sdma1 25 4 0&gt;;</div><div class='add'>+					dma-names = "rx", "tx";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			crypto: crypto@30900000 {</div><div class='hunk'>@@ -700,6 +936,7 @@</div><div class='ctx'> 					compatible = "fsl,sec-v4.0-job-ring";</div><div class='ctx'> 					reg = &lt;0x1000 0x1000&gt;;</div><div class='ctx'> 					interrupts = &lt;GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					status = "disabled";</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='ctx'> 				sec_jr1: jr@2000 {</div><div class='hunk'>@@ -767,6 +1004,14 @@</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='add'>+			mu: mailbox@30aa0000 {</div><div class='add'>+				compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu";</div><div class='add'>+				reg = &lt;0x30aa0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MM_CLK_MU_ROOT&gt;;</div><div class='add'>+				#mbox-cells = &lt;2&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='ctx'> 			usdhc1: mmc@30b40000 {</div><div class='ctx'> 				compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";</div><div class='ctx'> 				reg = &lt;0x30b40000 0x10000&gt;;</div><div class='hunk'>@@ -776,7 +1021,7 @@</div><div class='ctx'> 					 &lt;&amp;clk IMX8MM_CLK_USDHC1_ROOT&gt;;</div><div class='ctx'> 				clock-names = "ipg", "ahb", "per";</div><div class='ctx'> 				fsl,tuning-start-tap = &lt;20&gt;;</div><div class='del'>-				fsl,tuning-step= &lt;2&gt;;</div><div class='add'>+				fsl,tuning-step = &lt;2&gt;;</div><div class='ctx'> 				bus-width = &lt;4&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='hunk'>@@ -790,7 +1035,7 @@</div><div class='ctx'> 					 &lt;&amp;clk IMX8MM_CLK_USDHC2_ROOT&gt;;</div><div class='ctx'> 				clock-names = "ipg", "ahb", "per";</div><div class='ctx'> 				fsl,tuning-start-tap = &lt;20&gt;;</div><div class='del'>-				fsl,tuning-step= &lt;2&gt;;</div><div class='add'>+				fsl,tuning-step = &lt;2&gt;;</div><div class='ctx'> 				bus-width = &lt;4&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='hunk'>@@ -804,7 +1049,7 @@</div><div class='ctx'> 					 &lt;&amp;clk IMX8MM_CLK_USDHC3_ROOT&gt;;</div><div class='ctx'> 				clock-names = "ipg", "ahb", "per";</div><div class='ctx'> 				fsl,tuning-start-tap = &lt;20&gt;;</div><div class='del'>-				fsl,tuning-step= &lt;2&gt;;</div><div class='add'>+				fsl,tuning-step = &lt;2&gt;;</div><div class='ctx'> 				bus-width = &lt;4&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='hunk'>@@ -818,7 +1063,7 @@</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;clk IMX8MM_CLK_QSPI_ROOT&gt;,</div><div class='ctx'> 					 &lt;&amp;clk IMX8MM_CLK_QSPI_ROOT&gt;;</div><div class='del'>-				clock-names = "fspi", "fspi_en";</div><div class='add'>+				clock-names = "fspi_en", "fspi";</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -834,11 +1079,12 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			fec1: ethernet@30be0000 {</div><div class='del'>-				compatible = "fsl,imx8mm-fec", "fsl,imx6sx-fec";</div><div class='add'>+				compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";</div><div class='ctx'> 				reg = &lt;0x30be0000 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 					     &lt;GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-					     &lt;GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					     &lt;GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;clk IMX8MM_CLK_ENET1_ROOT&gt;,</div><div class='ctx'> 					 &lt;&amp;clk IMX8MM_CLK_ENET1_ROOT&gt;,</div><div class='ctx'> 					 &lt;&amp;clk IMX8MM_CLK_ENET_TIMER&gt;,</div><div class='hunk'>@@ -849,13 +1095,17 @@</div><div class='ctx'> 				assigned-clocks = &lt;&amp;clk IMX8MM_CLK_ENET_AXI&gt;,</div><div class='ctx'> 						  &lt;&amp;clk IMX8MM_CLK_ENET_TIMER&gt;,</div><div class='ctx'> 						  &lt;&amp;clk IMX8MM_CLK_ENET_REF&gt;,</div><div class='del'>-						  &lt;&amp;clk IMX8MM_CLK_ENET_TIMER&gt;;</div><div class='add'>+						  &lt;&amp;clk IMX8MM_CLK_ENET_PHY_REF&gt;;</div><div class='ctx'> 				assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL1_266M&gt;,</div><div class='ctx'> 							 &lt;&amp;clk IMX8MM_SYS_PLL2_100M&gt;,</div><div class='del'>-							 &lt;&amp;clk IMX8MM_SYS_PLL2_125M&gt;;</div><div class='del'>-				assigned-clock-rates = &lt;0&gt;, &lt;0&gt;, &lt;125000000&gt;, &lt;100000000&gt;;</div><div class='add'>+							 &lt;&amp;clk IMX8MM_SYS_PLL2_125M&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MM_SYS_PLL2_50M&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;0&gt;, &lt;100000000&gt;, &lt;125000000&gt;, &lt;0&gt;;</div><div class='ctx'> 				fsl,num-tx-queues = &lt;3&gt;;</div><div class='ctx'> 				fsl,num-rx-queues = &lt;3&gt;;</div><div class='add'>+				nvmem-cells = &lt;&amp;fec_mac_address&gt;;</div><div class='add'>+				nvmem-cell-names = "mac-address";</div><div class='add'>+				fsl,stop-mode = &lt;&amp;gpr 0x10 3&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -863,49 +1113,199 @@</div><div class='ctx'> </div><div class='ctx'> 		aips4: bus@32c00000 {</div><div class='ctx'> 			compatible = "fsl,aips-bus", "simple-bus";</div><div class='del'>-			reg = &lt;0x32df0000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x32c00000 0x400000&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;1&gt;;</div><div class='ctx'> 			ranges = &lt;0x32c00000 0x32c00000 0x400000&gt;;</div><div class='ctx'> </div><div class='add'>+			lcdif: lcdif@32e00000 {</div><div class='add'>+				compatible = "fsl,imx8mm-lcdif", "fsl,imx6sx-lcdif";</div><div class='add'>+				reg = &lt;0x32e00000 0x10000&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MM_CLK_LCDIF_PIXEL&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MM_CLK_DISP_APB_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MM_CLK_DISP_AXI_ROOT&gt;;</div><div class='add'>+				clock-names = "pix", "axi", "disp_axi";</div><div class='add'>+				assigned-clocks = &lt;&amp;clk IMX8MM_CLK_LCDIF_PIXEL&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX8MM_CLK_DISP_AXI&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX8MM_CLK_DISP_APB&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;clk IMX8MM_VIDEO_PLL1_OUT&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MM_SYS_PLL2_1000M&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MM_SYS_PLL1_800M&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;24000000&gt;, &lt;500000000&gt;, &lt;200000000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				power-domains = &lt;&amp;disp_blk_ctrl IMX8MM_DISPBLK_PD_LCDIF&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				port {</div><div class='add'>+					lcdif_to_dsim: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dsim_from_lcdif&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mipi_dsi: dsi@32e10000 {</div><div class='add'>+				compatible = "fsl,imx8mm-mipi-dsim";</div><div class='add'>+				reg = &lt;0x32e10000 0x400&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MM_CLK_DSI_CORE&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MM_CLK_DSI_PHY_REF&gt;;</div><div class='add'>+				clock-names = "bus_clk", "sclk_mipi";</div><div class='add'>+				assigned-clocks = &lt;&amp;clk IMX8MM_CLK_DSI_CORE&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL1_266M&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				power-domains = &lt;&amp;disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_DSI&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						dsim_from_lcdif: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;lcdif_to_dsim&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						mipi_dsi_out: endpoint {</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			csi: csi@32e20000 {</div><div class='add'>+				compatible = "fsl,imx8mm-csi", "fsl,imx7-csi";</div><div class='add'>+				reg = &lt;0x32e20000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MM_CLK_CSI1_ROOT&gt;;</div><div class='add'>+				clock-names = "mclk";</div><div class='add'>+				power-domains = &lt;&amp;disp_blk_ctrl IMX8MM_DISPBLK_PD_CSI_BRIDGE&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				port {</div><div class='add'>+					csi_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;imx8mm_mipi_csi_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			disp_blk_ctrl: blk-ctrl@32e28000 {</div><div class='add'>+				compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon";</div><div class='add'>+				reg = &lt;0x32e28000 0x100&gt;;</div><div class='add'>+				power-domains = &lt;&amp;pgc_dispmix&gt;, &lt;&amp;pgc_dispmix&gt;,</div><div class='add'>+						&lt;&amp;pgc_dispmix&gt;, &lt;&amp;pgc_mipi&gt;,</div><div class='add'>+						&lt;&amp;pgc_mipi&gt;;</div><div class='add'>+				power-domain-names = "bus", "csi-bridge",</div><div class='add'>+						     "lcdif", "mipi-dsi",</div><div class='add'>+						     "mipi-csi";</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MM_CLK_DISP_AXI_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MM_CLK_DISP_APB_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MM_CLK_CSI1_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MM_CLK_DISP_AXI_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MM_CLK_DISP_APB_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MM_CLK_DISP_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MM_CLK_DSI_CORE&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MM_CLK_DSI_PHY_REF&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MM_CLK_CSI1_CORE&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MM_CLK_CSI1_PHY_REF&gt;;</div><div class='add'>+				clock-names = "csi-bridge-axi","csi-bridge-apb",</div><div class='add'>+					      "csi-bridge-core", "lcdif-axi",</div><div class='add'>+					      "lcdif-apb", "lcdif-pix",</div><div class='add'>+					      "dsi-pclk", "dsi-ref",</div><div class='add'>+					      "csi-aclk", "csi-pclk";</div><div class='add'>+				#power-domain-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mipi_csi: mipi-csi@32e30000 {</div><div class='add'>+				compatible = "fsl,imx8mm-mipi-csi2";</div><div class='add'>+				reg = &lt;0x32e30000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				assigned-clocks = &lt;&amp;clk IMX8MM_CLK_CSI1_CORE&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL2_1000M&gt;;</div><div class='add'>+</div><div class='add'>+				clock-frequency = &lt;333000000&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MM_CLK_DISP_APB_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MM_CLK_CSI1_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MM_CLK_CSI1_PHY_REF&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MM_CLK_DISP_AXI_ROOT&gt;;</div><div class='add'>+				clock-names = "pclk", "wrap", "phy", "axi";</div><div class='add'>+				power-domains = &lt;&amp;disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_CSI&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						imx8mm_mipi_csi_out: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;csi_in&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='ctx'> 			usbotg1: usb@32e40000 {</div><div class='del'>-				compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";</div><div class='add'>+				compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb", "fsl,imx27-usb";</div><div class='ctx'> 				reg = &lt;0x32e40000 0x200&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;clk IMX8MM_CLK_USB1_CTRL_ROOT&gt;;</div><div class='del'>-				clock-names = "usb1_ctrl_root_clk";</div><div class='ctx'> 				assigned-clocks = &lt;&amp;clk IMX8MM_CLK_USB_BUS&gt;;</div><div class='ctx'> 				assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL2_500M&gt;;</div><div class='del'>-				fsl,usbphy = &lt;&amp;usbphynop1&gt;;</div><div class='add'>+				phys = &lt;&amp;usbphynop1&gt;;</div><div class='ctx'> 				fsl,usbmisc = &lt;&amp;usbmisc1 0&gt;;</div><div class='add'>+				power-domains = &lt;&amp;pgc_hsiomix&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			usbmisc1: usbmisc@32e40200 {</div><div class='del'>-				compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";</div><div class='add'>+				compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc",</div><div class='add'>+					     "fsl,imx6q-usbmisc";</div><div class='ctx'> 				#index-cells = &lt;1&gt;;</div><div class='ctx'> 				reg = &lt;0x32e40200 0x200&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			usbotg2: usb@32e50000 {</div><div class='del'>-				compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";</div><div class='add'>+				compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb", "fsl,imx27-usb";</div><div class='ctx'> 				reg = &lt;0x32e50000 0x200&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;clk IMX8MM_CLK_USB1_CTRL_ROOT&gt;;</div><div class='del'>-				clock-names = "usb1_ctrl_root_clk";</div><div class='ctx'> 				assigned-clocks = &lt;&amp;clk IMX8MM_CLK_USB_BUS&gt;;</div><div class='ctx'> 				assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL2_500M&gt;;</div><div class='del'>-				fsl,usbphy = &lt;&amp;usbphynop2&gt;;</div><div class='add'>+				phys = &lt;&amp;usbphynop2&gt;;</div><div class='ctx'> 				fsl,usbmisc = &lt;&amp;usbmisc2 0&gt;;</div><div class='add'>+				power-domains = &lt;&amp;pgc_hsiomix&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			usbmisc2: usbmisc@32e50200 {</div><div class='del'>-				compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";</div><div class='add'>+				compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc",</div><div class='add'>+					     "fsl,imx6q-usbmisc";</div><div class='ctx'> 				#index-cells = &lt;1&gt;;</div><div class='ctx'> 				reg = &lt;0x32e50200 0x200&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='add'>+			pcie_phy: pcie-phy@32f00000 {</div><div class='add'>+				compatible = "fsl,imx8mm-pcie-phy";</div><div class='add'>+				reg = &lt;0x32f00000 0x10000&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MM_CLK_PCIE1_PHY&gt;;</div><div class='add'>+				clock-names = "ref";</div><div class='add'>+				assigned-clocks = &lt;&amp;clk IMX8MM_CLK_PCIE1_PHY&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;100000000&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;clk IMX8MM_SYS_PLL2_100M&gt;;</div><div class='add'>+				resets = &lt;&amp;src IMX8MQ_RESET_PCIEPHY&gt;;</div><div class='add'>+				reset-names = "pciephy";</div><div class='add'>+				#phy-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		dma_apbh: dma-controller@33000000 {</div><div class='hunk'>@@ -915,16 +1315,15 @@</div><div class='ctx'> 				     &lt;GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 				     &lt;GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 				     &lt;GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";</div><div class='ctx'> 			#dma-cells = &lt;1&gt;;</div><div class='ctx'> 			dma-channels = &lt;4&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		gpmi: nand-controller@33002000{</div><div class='add'>+		gpmi: nand-controller@33002000 {</div><div class='ctx'> 			compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand";</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='del'>-			#size-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			reg = &lt;0x33002000 0x2000&gt;, &lt;0x33004000 0x4000&gt;;</div><div class='ctx'> 			reg-names = "gpmi-nand", "bch";</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='hunk'>@@ -937,10 +1336,138 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		pcie0: pcie@33800000 {</div><div class='add'>+			compatible = "fsl,imx8mm-pcie";</div><div class='add'>+			reg = &lt;0x33800000 0x400000&gt;, &lt;0x1ff00000 0x80000&gt;;</div><div class='add'>+			reg-names = "dbi", "config";</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			bus-range = &lt;0x00 0xff&gt;;</div><div class='add'>+			ranges = &lt;0x81000000 0 0x00000000 0x1ff80000 0 0x00010000&gt;, /* downstream I/O 64KB */</div><div class='add'>+				 &lt;0x82000000 0 0x18000000 0x18000000 0 0x07f00000&gt;; /* non-prefetchable memory */</div><div class='add'>+			num-lanes = &lt;1&gt;;</div><div class='add'>+			num-viewport = &lt;4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "msi";</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0x7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			fsl,max-link-speed = &lt;2&gt;;</div><div class='add'>+			linux,pci-domain = &lt;0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MM_CLK_PCIE1_ROOT&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MM_CLK_PCIE1_PHY&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MM_CLK_PCIE1_AUX&gt;;</div><div class='add'>+			clock-names = "pcie", "pcie_bus", "pcie_aux";</div><div class='add'>+			power-domains = &lt;&amp;pgc_pcie&gt;;</div><div class='add'>+			resets = &lt;&amp;src IMX8MQ_RESET_PCIE_CTRL_APPS_EN&gt;,</div><div class='add'>+				 &lt;&amp;src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF&gt;;</div><div class='add'>+			reset-names = "apps", "turnoff";</div><div class='add'>+			phys = &lt;&amp;pcie_phy&gt;;</div><div class='add'>+			phy-names = "pcie-phy";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie0_ep: pcie-ep@33800000 {</div><div class='add'>+			compatible = "fsl,imx8mm-pcie-ep";</div><div class='add'>+			reg = &lt;0x33800000 0x100000&gt;,</div><div class='add'>+			      &lt;0x18000000 0x8000000&gt;,</div><div class='add'>+			      &lt;0x33900000 0x100000&gt;,</div><div class='add'>+			      &lt;0x33b00000 0x100000&gt;;</div><div class='add'>+			reg-names = "dbi", "addr_space", "dbi2", "atu";</div><div class='add'>+			num-lanes = &lt;1&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "dma";</div><div class='add'>+			fsl,max-link-speed = &lt;2&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MM_CLK_PCIE1_ROOT&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MM_CLK_PCIE1_PHY&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MM_CLK_PCIE1_AUX&gt;;</div><div class='add'>+			clock-names = "pcie", "pcie_bus", "pcie_aux";</div><div class='add'>+			power-domains = &lt;&amp;pgc_pcie&gt;;</div><div class='add'>+			resets = &lt;&amp;src IMX8MQ_RESET_PCIE_CTRL_APPS_EN&gt;,</div><div class='add'>+				 &lt;&amp;src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF&gt;;</div><div class='add'>+			reset-names = "apps", "turnoff";</div><div class='add'>+			phys = &lt;&amp;pcie_phy&gt;;</div><div class='add'>+			phy-names = "pcie-phy";</div><div class='add'>+			num-ib-windows = &lt;4&gt;;</div><div class='add'>+			num-ob-windows = &lt;4&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu_3d: gpu@38000000 {</div><div class='add'>+			compatible = "vivante,gc";</div><div class='add'>+			reg = &lt;0x38000000 0x8000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MM_CLK_GPU_AHB&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MM_CLK_GPU_BUS_ROOT&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MM_CLK_GPU3D_ROOT&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MM_CLK_GPU3D_ROOT&gt;;</div><div class='add'>+			clock-names = "reg", "bus", "core", "shader";</div><div class='add'>+			assigned-clocks = &lt;&amp;clk IMX8MM_CLK_GPU3D_CORE&gt;,</div><div class='add'>+					  &lt;&amp;clk IMX8MM_GPU_PLL_OUT&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;clk IMX8MM_GPU_PLL_OUT&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;0&gt;, &lt;800000000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;pgc_gpu&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu_2d: gpu@38008000 {</div><div class='add'>+			compatible = "vivante,gc";</div><div class='add'>+			reg = &lt;0x38008000 0x8000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MM_CLK_GPU_AHB&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MM_CLK_GPU_BUS_ROOT&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MM_CLK_GPU2D_ROOT&gt;;</div><div class='add'>+			clock-names = "reg", "bus", "core";</div><div class='add'>+			assigned-clocks = &lt;&amp;clk IMX8MM_CLK_GPU2D_CORE&gt;,</div><div class='add'>+					  &lt;&amp;clk IMX8MM_GPU_PLL_OUT&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;clk IMX8MM_GPU_PLL_OUT&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;0&gt;, &lt;800000000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;pgc_gpu&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vpu_g1: video-codec@38300000 {</div><div class='add'>+			compatible = "nxp,imx8mm-vpu-g1";</div><div class='add'>+			reg = &lt;0x38300000 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MM_CLK_VPU_G1_ROOT&gt;;</div><div class='add'>+			power-domains = &lt;&amp;vpu_blk_ctrl IMX8MM_VPUBLK_PD_G1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vpu_g2: video-codec@38310000 {</div><div class='add'>+			compatible = "nxp,imx8mq-vpu-g2";</div><div class='add'>+			reg = &lt;0x38310000 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MM_CLK_VPU_G2_ROOT&gt;;</div><div class='add'>+			power-domains = &lt;&amp;vpu_blk_ctrl IMX8MM_VPUBLK_PD_G2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vpu_blk_ctrl: blk-ctrl@38330000 {</div><div class='add'>+			compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon";</div><div class='add'>+			reg = &lt;0x38330000 0x100&gt;;</div><div class='add'>+			power-domains = &lt;&amp;pgc_vpumix&gt;, &lt;&amp;pgc_vpu_g1&gt;,</div><div class='add'>+					&lt;&amp;pgc_vpu_g2&gt;, &lt;&amp;pgc_vpu_h1&gt;;</div><div class='add'>+			power-domain-names = "bus", "g1", "g2", "h1";</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MM_CLK_VPU_G1_ROOT&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MM_CLK_VPU_G2_ROOT&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MM_CLK_VPU_H1_ROOT&gt;;</div><div class='add'>+			clock-names = "g1", "g2", "h1";</div><div class='add'>+			assigned-clocks = &lt;&amp;clk IMX8MM_CLK_VPU_G1&gt;,</div><div class='add'>+					  &lt;&amp;clk IMX8MM_CLK_VPU_G2&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;clk IMX8MM_VPU_PLL_OUT&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MM_VPU_PLL_OUT&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;600000000&gt;,</div><div class='add'>+					       &lt;600000000&gt;;</div><div class='add'>+			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		gic: interrupt-controller@38800000 {</div><div class='ctx'> 			compatible = "arm,gic-v3";</div><div class='ctx'> 			reg = &lt;0x38800000 0x10000&gt;, /* GIC Dist */</div><div class='ctx'> 			      &lt;0x38880000 0xc0000&gt;; /* GICR (RD_base + SGI_base) */</div><div class='add'>+			#address-cells = &lt;0&gt;;</div><div class='ctx'> 			#interrupt-cells = &lt;3&gt;;</div><div class='ctx'> 			interrupt-controller;</div><div class='ctx'> 			interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi<br/>new file mode 100644<br/>index 000000000000..77d14ea459e5<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi</a></div><div class='hunk'>@@ -0,0 +1,442 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2020 Compass Electronics Group, LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	dmic_codec: dmic-codec {</div><div class='add'>+		compatible = "dmic-codec";</div><div class='add'>+		num-channels = &lt;1&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			label = "gen_led0";</div><div class='add'>+			gpios = &lt;&amp;pca6416_1 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			label = "gen_led1";</div><div class='add'>+			gpios = &lt;&amp;pca6416_1 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-2 {</div><div class='add'>+			label = "gen_led2";</div><div class='add'>+			gpios = &lt;&amp;pca6416_1 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-3 {</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_led3&gt;;</div><div class='add'>+			label = "heartbeat";</div><div class='add'>+			gpios = &lt;&amp;gpio4 28 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_1v5: regulator-1v5 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "1V5";</div><div class='add'>+		regulator-min-microvolt = &lt;1500000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1500000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_1v8: regulator-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_audio: regulator-audio {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "3v3_aud";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;pca6416_1 11 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_camera: regulator-camera {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "mipi_pwr";</div><div class='add'>+		regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+		gpio = &lt;&amp;pca6416_1 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		startup-delay-us = &lt;100000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vsd_3v3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio2 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb_otg_vbus: regulator-usb {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usb_otg&gt;;</div><div class='add'>+		regulator-name = "usb_otg_vbus";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio4 29 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-dmic {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,name = "dmic";</div><div class='add'>+		simple-audio-card,format = "pdm";</div><div class='add'>+		simple-audio-card,bitclock-master = &lt;&amp;dailink_master&gt;;</div><div class='add'>+		simple-audio-card,frame-master = &lt;&amp;dailink_master&gt;;</div><div class='add'>+</div><div class='add'>+		dailink_master: simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;micfil&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		simple-audio-card,codec {</div><div class='add'>+			sound-dai = &lt;&amp;dmic_codec&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-wm8962 {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,name = "wm8962";</div><div class='add'>+		simple-audio-card,format = "i2s";</div><div class='add'>+		simple-audio-card,widgets = "Headphone", "Headphones",</div><div class='add'>+					    "Microphone", "Headset Mic",</div><div class='add'>+					    "Speaker", "Speaker";</div><div class='add'>+		simple-audio-card,routing = "Headphones", "HPOUTL",</div><div class='add'>+					    "Headphones", "HPOUTR",</div><div class='add'>+					    "Speaker", "SPKOUTL",</div><div class='add'>+					    "Speaker", "SPKOUTR",</div><div class='add'>+					    "Headset Mic", "MICBIAS",</div><div class='add'>+					    "IN3R", "Headset Mic";</div><div class='add'>+</div><div class='add'>+		simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;sai3&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		simple-audio-card,codec {</div><div class='add'>+			sound-dai = &lt;&amp;wm8962&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MN_CLK_SAI3_ROOT&gt;;</div><div class='add'>+			frame-master;</div><div class='add'>+			bitclock-master;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_espi2&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 13 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	eeprom@0 {</div><div class='add'>+		compatible = "microchip,at25160bn", "atmel,at25";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;5000000&gt;;</div><div class='add'>+		spi-cpha;</div><div class='add'>+		spi-cpol;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		size = &lt;2048&gt;;</div><div class='add'>+		address-width = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;384000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	camera@10 {</div><div class='add'>+		compatible = "ovti,ov5640";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_ov5640&gt;;</div><div class='add'>+		reg = &lt;0x10&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX8MN_CLK_CLKO1&gt;;</div><div class='add'>+		clock-names = "xclk";</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX8MN_CLK_CLKO1&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;&amp;clk IMX8MN_CLK_24M&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;24000000&gt;;</div><div class='add'>+		AVDD-supply = &lt;&amp;reg_camera&gt;;  /* 2.8v */</div><div class='add'>+		DVDD-supply = &lt;&amp;reg_1v5&gt;;</div><div class='add'>+		DOVDD-supply = &lt;&amp;reg_1v8&gt;;</div><div class='add'>+		powerdown-gpios = &lt;&amp;gpio1 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio1 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			/* MIPI CSI-2 bus endpoint */</div><div class='add'>+			ov5640_to_mipi_csi2: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;mipi_csi_in&gt;;</div><div class='add'>+				clock-lanes = &lt;0&gt;;</div><div class='add'>+				data-lanes = &lt;1 2&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pca6416_0: gpio@20 {</div><div class='add'>+		compatible = "nxp,pcal6416";</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pcal6414&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;27 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pca6416_1: gpio@21 {</div><div class='add'>+		compatible = "nxp,pcal6416";</div><div class='add'>+		reg = &lt;0x21&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;27 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wm8962: audio-codec@1a {</div><div class='add'>+		compatible = "wlf,wm8962";</div><div class='add'>+		reg = &lt;0x1a&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX8MN_CLK_SAI3_ROOT&gt;;</div><div class='add'>+		DCVDD-supply = &lt;&amp;reg_audio&gt;;</div><div class='add'>+		DBVDD-supply = &lt;&amp;reg_audio&gt;;</div><div class='add'>+		AVDD-supply = &lt;&amp;reg_audio&gt;;</div><div class='add'>+		CPVDD-supply = &lt;&amp;reg_audio&gt;;</div><div class='add'>+		MICVDD-supply = &lt;&amp;reg_audio&gt;;</div><div class='add'>+		PLLVDD-supply = &lt;&amp;reg_audio&gt;;</div><div class='add'>+		SPKVDD1-supply = &lt;&amp;reg_audio&gt;;</div><div class='add'>+		SPKVDD2-supply = &lt;&amp;reg_audio&gt;;</div><div class='add'>+		gpio-cfg = &lt;</div><div class='add'>+			0x0000 /* 0:Default */</div><div class='add'>+			0x0000 /* 1:Default */</div><div class='add'>+			0x0000 /* 2:FN_DMICCLK */</div><div class='add'>+			0x0000 /* 3:Default */</div><div class='add'>+			0x0000 /* 4:FN_DMICCDAT */</div><div class='add'>+			0x0000 /* 5:Default */</div><div class='add'>+		&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;isi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;easrc {</div><div class='add'>+	fsl,asrc-rate = &lt;48000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_csi {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@0 {</div><div class='add'>+			mipi_csi_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;ov5640_to_mipi_csi2&gt;;</div><div class='add'>+				data-lanes = &lt;1 2&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;micfil {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pdm&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MN_CLK_PDM&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MN_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;49152000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai3&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MN_CLK_SAI3&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MN_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;24576000&gt;;</div><div class='add'>+	fsl,sai-mclk-direction-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;snvs_pwrkey {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 { /* console */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MN_CLK_UART3&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MN_SYS_PLL1_80M&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usb_otg_vbus&gt;;</div><div class='add'>+	disable-over-current;</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_espi2: espi2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK		0x82</div><div class='add'>+			MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI		0x82</div><div class='add'>+			MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO		0x82</div><div class='add'>+			MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13		0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3</div><div class='add'>+			MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4: i2c4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL		0x400001c3</div><div class='add'>+			MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_led3: led3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ov5640: ov5640grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x19</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6		0x19</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1	0x59</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcal6414: pcal6414-gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27		0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pdm: pdmgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SAI5_RXC_PDM_CLK	0xd6</div><div class='add'>+			MX8MN_IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0	0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usb_otg: reg-otggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SAI3_RXC_GPIO4_IO29     0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai3: sai3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6</div><div class='add'>+			MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6</div><div class='add'>+			MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6</div><div class='add'>+			MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6</div><div class='add'>+			MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0	0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140</div><div class='add'>+			MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: uart3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX	0x40</div><div class='add'>+			MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX	0x40</div><div class='add'>+			MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B	0x40</div><div class='add'>+			MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B	0x40</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SD2_CD_B_USDHC2_CD_B	0x41</div><div class='add'>+			MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK	0x190</div><div class='add'>+			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD	0x1d0</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK	0x194</div><div class='add'>+			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD	0x1d4</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK	0x196</div><div class='add'>+			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD	0x1d6</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-kit.dts b/arch/arm64/boot/dts/freescale/imx8mn-beacon-kit.dts<br/>new file mode 100644<br/>index 000000000000..37fc5ed98d7f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mn-beacon-kit.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mn-beacon-kit.dts</a></div><div class='hunk'>@@ -0,0 +1,151 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2020 Compass Electronics Group, LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mn.dtsi"</div><div class='add'>+#include "imx8mn-beacon-som.dtsi"</div><div class='add'>+#include "imx8mn-beacon-baseboard.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Beacon EmbeddedWorks i.MX8M Nano Development Kit";</div><div class='add'>+	compatible = "beacon,imx8mn-beacon-kit", "fsl,imx8mn";</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		type = "a";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			hdmi_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;adv7535_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_hdmi: regulator-hdmi-dvdd {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_hdmi&gt;;</div><div class='add'>+		regulator-name = "hdmi_pwr_en";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio2 11 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		startup-delay-us = &lt;70000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-hdmi {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,name = "sound-hdmi";</div><div class='add'>+		simple-audio-card,format = "i2s";</div><div class='add'>+</div><div class='add'>+		simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;sai5&gt;;</div><div class='add'>+			system-clock-direction-out;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		simple-audio-card,codec {</div><div class='add'>+			sound-dai = &lt;&amp;adv_bridge&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	adv_bridge: hdmi@3d {</div><div class='add'>+		compatible = "adi,adv7535";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_hdmi_bridge&gt;;</div><div class='add'>+		reg = &lt;0x3d&gt;, &lt;0x3e&gt;, &lt;0x3c&gt;, &lt;0x3f&gt;;</div><div class='add'>+		reg-names = "main", "edid", "cec", "packet";</div><div class='add'>+		adi,dsi-lanes = &lt;4&gt;;</div><div class='add'>+		avdd-supply = &lt;&amp;reg_hdmi&gt;;</div><div class='add'>+		a2vdd-supply = &lt;&amp;reg_hdmi&gt;;</div><div class='add'>+		dvdd-supply = &lt;&amp;reg_hdmi&gt;;</div><div class='add'>+		pvdd-supply = &lt;&amp;reg_hdmi&gt;;</div><div class='add'>+		v1p2-supply = &lt;&amp;reg_hdmi&gt;;</div><div class='add'>+		v3p3-supply = &lt;&amp;reg_hdmi&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;9 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				adv7535_in: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;dsi_out&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				adv7535_out: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;hdmi_connector_in&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_dsi {</div><div class='add'>+	samsung,esc-clock-frequency = &lt;20000000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			dsi_out: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;adv7535_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai5 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai5&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MN_CLK_SAI5&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MN_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;24576000&gt;;</div><div class='add'>+	#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	fsl,sai-mclk-direction-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_hdmi_bridge: hdmibridgegrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_hdmi: reghdmigrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11              0x16</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai5: sai5grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0	0xd6</div><div class='add'>+			MX8MN_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK	0xd6</div><div class='add'>+			MX8MN_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC	0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi<br/>new file mode 100644<br/>index 000000000000..917b7d0007a7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi</a></div><div class='hunk'>@@ -0,0 +1,492 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2020 Compass Electronics Group, LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "imx8mn-overdrive.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		rtc0 = &amp;rtc;</div><div class='add'>+		rtc1 = &amp;snvs_rtc;</div><div class='add'>+		spi0 = &amp;flexspi;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usdhc1_pwrseq: usdhc1_pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-simple";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usdhc1_gpio&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio2 10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		clocks = &lt;&amp;osc_32k&gt;;</div><div class='add'>+		clock-names = "ext_clock";</div><div class='add'>+		post-power-on-delay-ms = &lt;80&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x40000000 0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* DDR controller is running LPDDR at 800MHz which requires 0.95V */</div><div class='add'>+&amp;a53_opp_table {</div><div class='add'>+	opp-1200000000 {</div><div class='add'>+		opp-microvolt = &lt;950000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ddrc {</div><div class='add'>+	operating-points-v2 = &lt;&amp;ddrc_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+	ddrc_opp_table: opp-table {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		opp-25000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;25000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-100000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;100000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-800000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;800000000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec1&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	phy-supply = &lt;&amp;buck6_reg&gt;;</div><div class='add'>+	phy-reset-gpios = &lt;&amp;gpio4 22 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	fsl,magic-packet;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@0 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio4 22 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+			interrupts = &lt;10 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexspi {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexspi&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash@0 {</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		spi-max-frequency = &lt;80000000&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;1&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pmic@4b {</div><div class='add'>+		compatible = "rohm,bd71847";</div><div class='add'>+		reg = &lt;0x4b&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;3 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		rohm,reset-snvs-powered;</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clocks = &lt;&amp;osc_32k&gt;;</div><div class='add'>+		clock-output-names = "clk-32k-out";</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			buck1_reg: BUCK1 {</div><div class='add'>+				regulator-name = "buck1";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;1250&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck2_reg: BUCK2 {</div><div class='add'>+				regulator-name = "buck2";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;1250&gt;;</div><div class='add'>+				rohm,dvs-run-voltage = &lt;1000000&gt;;</div><div class='add'>+				rohm,dvs-idle-voltage = &lt;900000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck3_reg: BUCK3 {</div><div class='add'>+				// BUCK5 in datasheet</div><div class='add'>+				regulator-name = "buck3";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck4_reg: BUCK4 {</div><div class='add'>+				// BUCK6 in datasheet</div><div class='add'>+				regulator-name = "buck4";</div><div class='add'>+				regulator-min-microvolt = &lt;3000000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck5_reg: BUCK5 {</div><div class='add'>+				// BUCK7 in datasheet</div><div class='add'>+				regulator-name = "buck5";</div><div class='add'>+				regulator-min-microvolt = &lt;1605000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1995000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck6_reg: BUCK6 {</div><div class='add'>+				// BUCK8 in datasheet</div><div class='add'>+				regulator-name = "buck6";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo1_reg: LDO1 {</div><div class='add'>+				regulator-name = "ldo1";</div><div class='add'>+				regulator-min-microvolt = &lt;1600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo2_reg: LDO2 {</div><div class='add'>+				regulator-name = "ldo2";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo3_reg: LDO3 {</div><div class='add'>+				regulator-name = "ldo3";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo4_reg: LDO4 {</div><div class='add'>+				regulator-name = "ldo4";</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo6_reg: LDO6 {</div><div class='add'>+				regulator-name = "ldo6";</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	eeprom@50 {</div><div class='add'>+		compatible = "microchip,24c64", "atmel,24c64";</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		read-only;	/* Manufacturing EEPROM programmed at factory */</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rtc: rtc@51 {</div><div class='add'>+		compatible = "nxp,pcf85263";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_rtc&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;13 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		quartz-load-femtofarads = &lt;12500&gt;;</div><div class='add'>+		wakeup-source;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MN_CLK_UART1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MN_SYS_PLL1_80M&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "brcm,bcm43438-bt";</div><div class='add'>+		shutdown-gpios = &lt;&amp;gpio2 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		host-wakeup-gpios = &lt;&amp;gpio2 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		device-wakeup-gpios = &lt;&amp;gpio2 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;osc_32k&gt;;</div><div class='add'>+		max-speed = &lt;4000000&gt;;</div><div class='add'>+		clock-names = "extclk";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1_200mhz&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;buck4_reg&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;buck5_reg&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	cap-power-off-card;</div><div class='add'>+	keep-power-in-suspend;</div><div class='add'>+	mmc-pwrseq = &lt;&amp;usdhc1_pwrseq&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	brcmf: wifi@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		compatible = "brcm,bcm4329-fmac";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_wlan&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio2&gt;;</div><div class='add'>+		interrupts = &lt;9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-names = "host-wake";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MN_CLK_USDHC3&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_fec1: fec1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_ENET_MDC_ENET1_MDC		0x3</div><div class='add'>+			MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO	0x3</div><div class='add'>+			MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x1f</div><div class='add'>+			MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x1f</div><div class='add'>+			MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x1f</div><div class='add'>+			MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x1f</div><div class='add'>+			MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x91</div><div class='add'>+			MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x91</div><div class='add'>+			MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x91</div><div class='add'>+			MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x91</div><div class='add'>+			MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x1f</div><div class='add'>+			MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x91</div><div class='add'>+			MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91</div><div class='add'>+			MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10             0x146</div><div class='add'>+			MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22	0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3</div><div class='add'>+			MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3</div><div class='add'>+			MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexspi: flexspigrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK               0x1c2</div><div class='add'>+			MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B            0x82</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0           0x82</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1           0x82</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2           0x82</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3           0x82</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: pmicirqgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x141</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_rtc: rtcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13	0x146</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140</div><div class='add'>+			MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140</div><div class='add'>+			MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B	0x140</div><div class='add'>+			MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B	0x140</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6	0x19</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7	0x19</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8	0x19</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K	0x141</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_gpio: usdhc1gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK		0x190</div><div class='add'>+			MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d0</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d0</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d0</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d0</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK		0x194</div><div class='add'>+			MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d4</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d4</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d4</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d4</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK		0x196</div><div class='add'>+			MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d6</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d6</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d6</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d6</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x190</div><div class='add'>+			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0</div><div class='add'>+			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d0</div><div class='add'>+			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d0</div><div class='add'>+			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d0</div><div class='add'>+			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d0</div><div class='add'>+			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x190</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x194</div><div class='add'>+			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d4</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d4</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d4</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d4</div><div class='add'>+			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4</div><div class='add'>+			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d4</div><div class='add'>+			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d4</div><div class='add'>+			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4</div><div class='add'>+			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x194</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x196</div><div class='add'>+			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d6</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d6</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d6</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d6</div><div class='add'>+			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d6</div><div class='add'>+			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d6</div><div class='add'>+			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d6</div><div class='add'>+			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d6</div><div class='add'>+			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x196</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0xc6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wlan: wlangrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9		0x111</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi<br/>new file mode 100644<br/>index 000000000000..d20393c2d901<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi</a></div><div class='hunk'>@@ -0,0 +1,427 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021 Collabora Ltd.</div><div class='add'>+ * Copyright 2021 BSH Hausgeraete GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mn.dtsi"</div><div class='add'>+#include "imx8mn-bsh-smm-s2-display.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart4;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fec_supply: fec-supply-en {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		vin-supply = &lt;&amp;buck4_reg&gt;;</div><div class='add'>+		regulator-name = "tja1101_en";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio2 20 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usdhc2_pwrseq: usdhc2-pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-simple";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usdhc2_pwrseq&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio4 27 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_espi2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec1&gt;;</div><div class='add'>+	phy-mode = "rmii";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	phy-supply = &lt;&amp;fec_supply&gt;;</div><div class='add'>+	fsl,magic-packet;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@0 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio1 29 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;20&gt;;</div><div class='add'>+			reset-deassert-us = &lt;2000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bd71847: pmic@4b {</div><div class='add'>+		compatible = "rohm,bd71847";</div><div class='add'>+		reg = &lt;0x4b&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;3 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		rohm,reset-snvs-powered;</div><div class='add'>+</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clocks = &lt;&amp;osc_32k&gt;;</div><div class='add'>+		clock-output-names = "clk-32k-out";</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			buck1_reg: BUCK1 {</div><div class='add'>+				/* PMIC_BUCK1 - VDD_SOC */</div><div class='add'>+				regulator-name = "buck1";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;1250&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck2_reg: BUCK2 {</div><div class='add'>+				/* PMIC_BUCK2 - VDD_ARM */</div><div class='add'>+				regulator-name = "buck2";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;1250&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck3_reg: BUCK3 {</div><div class='add'>+				/* PMIC_BUCK5 - VDD_DRAM_VPU_GPU */</div><div class='add'>+				regulator-name = "buck3";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck4_reg: BUCK4 {</div><div class='add'>+				/* PMIC_BUCK6 - VDD_3V3 */</div><div class='add'>+				regulator-name = "buck4";</div><div class='add'>+				regulator-min-microvolt = &lt;3000000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck5_reg: BUCK5 {</div><div class='add'>+				/* PMIC_BUCK7 - VDD_1V8 */</div><div class='add'>+				regulator-name = "buck5";</div><div class='add'>+				regulator-min-microvolt = &lt;1605000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1995000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck6_reg: BUCK6 {</div><div class='add'>+				/* PMIC_BUCK8 - NVCC_DRAM */</div><div class='add'>+				regulator-name = "buck6";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo1_reg: LDO1 {</div><div class='add'>+				/* PMIC_LDO1 - NVCC_SNVS_1V8 */</div><div class='add'>+				regulator-name = "ldo1";</div><div class='add'>+				regulator-min-microvolt = &lt;1600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1900000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo2_reg: LDO2 {</div><div class='add'>+				/* PMIC_LDO2 - VDD_SNVS_0V8 */</div><div class='add'>+				regulator-name = "ldo2";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo3_reg: LDO3 {</div><div class='add'>+				/* PMIC_LDO3 - VDDA_1V8 */</div><div class='add'>+				regulator-name = "ldo3";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo4_reg: LDO4 {</div><div class='add'>+				/* PMIC_LDO4 - VDD_MIPI_0V9 */</div><div class='add'>+				regulator-name = "ldo4";</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo6_reg: LDO6 {</div><div class='add'>+				/* PMIC_LDO6 - VDD_MIPI_1V2 */</div><div class='add'>+				regulator-name = "ldo6";</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MN_CLK_UART3&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MN_SYS_PLL1_80M&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "brcm,bcm43438-bt";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_bluetooth&gt;;</div><div class='add'>+		shutdown-gpios = &lt;&amp;gpio1 15 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		device-wakeup-gpios = &lt;&amp;gpio1 18 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		host-wakeup-gpios = &lt;&amp;gpio1 28 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		max-speed = &lt;3000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Console */</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	dr_mode = "peripheral";</div><div class='add'>+	disable-over-current;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;;</div><div class='add'>+	mmc-pwrseq = &lt;&amp;usdhc2_pwrseq&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	brcmf: wifi@1 {</div><div class='add'>+		compatible = "brcm,bcm4329-fmac";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_wlan&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;0 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-names = "host-wake";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_bluetooth: bluetoothgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15		0x044	/* BT_REG_ON */</div><div class='add'>+			MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18		0x046	/* BT_DEV_WAKE */</div><div class='add'>+			MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28		0x090	/* BT_HOST_WAKE */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_espi2: espi2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK		0x082</div><div class='add'>+			MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI		0x082</div><div class='add'>+			MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO		0x082</div><div class='add'>+			MX8MN_IOMUXC_ECSPI2_SS0_ECSPI2_SS0		0x040</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec1: fec1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_ENET_MDC_ENET1_MDC			0x002</div><div class='add'>+			MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO		0x002</div><div class='add'>+			MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x090</div><div class='add'>+			MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x090</div><div class='add'>+			MX8MN_IOMUXC_ENET_RXC_ENET1_RX_ER		0x090</div><div class='add'>+			MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x016</div><div class='add'>+			MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x016</div><div class='add'>+			MX8MN_IOMUXC_ENET_TD2_ENET1_TX_CLK		0x016</div><div class='add'>+			MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x016</div><div class='add'>+			MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x090</div><div class='add'>+			MX8MN_IOMUXC_ENET_TXC_ENET1_TX_ER		0x016</div><div class='add'>+			MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12		0x150	/* RMII_INT - ENET_INT */</div><div class='add'>+			MX8MN_IOMUXC_SD2_WP_GPIO2_IO20			0x150	/* RMII_EN - ENET_EN */</div><div class='add'>+			MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19		0x016	/* RMII_WAKE - GPIO_ENET_WAKE */</div><div class='add'>+			MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29		0x016	/* RMII_RESET - GPIO_ENET_RST */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL			0x400000c2</div><div class='add'>+			MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA			0x400000c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL			0x400000c2</div><div class='add'>+			MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA			0x400000c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4: i2c4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL			0x400000c2</div><div class='add'>+			MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA			0x400000c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: pmicirqgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x040</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX		0x040</div><div class='add'>+			MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX		0x040</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: uart3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX		0x040</div><div class='add'>+			MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX		0x040</div><div class='add'>+			MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B	0x040</div><div class='add'>+			MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B		0x040</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart4: uart4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX		0x040</div><div class='add'>+			MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX		0x040</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK			0x090</div><div class='add'>+			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD			0x0d0</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x0d0</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x0d0</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x0d0</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x0d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK			0x094</div><div class='add'>+			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD			0x0d4</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x0d4</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x0d4</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x0d4</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x0d4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK			0x096</div><div class='add'>+			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD			0x0d6</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x0d6</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x0d6</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x0d6</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x0d6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_pwrseq: usdhc2pwrseqgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27		0x040	/* WL_REG_ON */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0x046</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wlan: wlangrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0		0x0d6	/* GPIO_0 - WIFI_GPIO_0 */</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8		0x0d6	/* GPIO_1 - WIFI_GPIO_1 */</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO04_GPIO1_IO4		0x0d6	/* BT_GPIO_5 - WIFI_GPIO_5 */</div><div class='add'>+			MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4			0x0d6	/* I2S_CLK - WIFI_GPIO_6 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-display.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-display.dtsi<br/>new file mode 100644<br/>index 000000000000..98dec3c42060<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-display.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-display.dtsi</a></div><div class='hunk'>@@ -0,0 +1,149 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021 BSH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	chosen {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		framebuffer-panel0 {</div><div class='add'>+			compatible = "simple-framebuffer";</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MN_CLK_DISP_PIXEL_ROOT&gt;, /* lcdif */</div><div class='add'>+				 &lt;&amp;clk IMX8MN_CLK_DISP_APB_ROOT&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MN_CLK_DISP_AXI_ROOT&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MN_VIDEO_PLL1&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MN_CLK_DISP_AXI_ROOT&gt;, /* pgc_dispmix */</div><div class='add'>+				 &lt;&amp;clk IMX8MN_CLK_DISP_APB_ROOT&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MN_CLK_DISP_AXI&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MN_CLK_DISP_APB&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MN_SYS_PLL2_1000M&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MN_SYS_PLL1_800M&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MN_CLK_DSI_CORE&gt;, /* mipi_disi */</div><div class='add'>+				 &lt;&amp;clk IMX8MN_CLK_DSI_PHY_REF&gt;;</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;disp_blk_ctrl IMX8MN_DISPBLK_PD_LCDIF&gt;,</div><div class='add'>+					&lt;&amp;disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_DSI&gt;;</div><div class='add'>+			dvdd-supply = &lt;&amp;reg_3v3_dvdd&gt;;</div><div class='add'>+			avdd-supply = &lt;&amp;reg_v3v3_avdd&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	backlight: backlight {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		pwms = &lt;&amp;pwm1 0 700000 0&gt;;	/* 700000 ns = 1337Hz */</div><div class='add'>+		brightness-levels = &lt;0 100&gt;;</div><div class='add'>+		num-interpolated-steps = &lt;100&gt;;</div><div class='add'>+		default-brightness-level = &lt;50&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3v3_dvdd: regulator-3v3-O3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_dvdd&gt;;</div><div class='add'>+		regulator-name = "3v3-dvdd-supply";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio1 7 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_v3v3_avdd: regulator-3v3-O2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_avdd&gt;;</div><div class='add'>+		regulator-name = "3v3-avdd-supply";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio1 5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_bl&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MN_VIDEO_PLL1&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;594000000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pgc_dispmix {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MN_CLK_DISP_AXI&gt;, &lt;&amp;clk IMX8MN_CLK_DISP_APB&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MN_SYS_PLL2_1000M&gt;, &lt;&amp;clk IMX8MN_SYS_PLL1_800M&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;500000000&gt;, &lt;200000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_dsi {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	samsung,esc-clock-frequency = &lt;20000000&gt;;</div><div class='add'>+	samsung,pll-clock-frequency = &lt;12000000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	panel@0 {</div><div class='add'>+		compatible = "sharp,ls068b3sx02", "syna,r63353";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_panel&gt;;</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		backlight = &lt;&amp;backlight&gt;;</div><div class='add'>+		dvdd-supply = &lt;&amp;reg_3v3_dvdd&gt;;</div><div class='add'>+		avdd-supply = &lt;&amp;reg_v3v3_avdd&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio4 29 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			panel_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;mipi_dsi_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			mipi_dsi_out: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;panel_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_avdd: avddgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5	0x16	/* VDD 3V3_VO2 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* This is for both PWM and voltage regulators for display */</div><div class='add'>+	pinctrl_bl: blgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT	0x16</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_dvdd: dvddgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7	0x16	/* VDD 3V3_VO3 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_panel: panelgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SAI3_RXC_GPIO4_IO29	0x16	/* panel reset */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2.dts b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2.dts<br/>new file mode 100644<br/>index 000000000000..11a1ba5bfdb7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2.dts</a></div><div class='hunk'>@@ -0,0 +1,47 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021 Collabora Ltd.</div><div class='add'>+ * Copyright 2021 BSH Hausgeraete GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mn-bsh-smm-s2-common.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "BSH SMM S2";</div><div class='add'>+	compatible = "bsh,imx8mn-bsh-smm-s2", "fsl,imx8mn";</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x40000000 0x0 0x10000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpmi {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpmi_nand&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_gpmi_nand: gpminandgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_NAND_ALE_RAWNAND_ALE		0x00000096</div><div class='add'>+			MX8MN_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B		0x00000096</div><div class='add'>+			MX8MN_IOMUXC_NAND_CLE_RAWNAND_CLE		0x00000096</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA00_RAWNAND_DATA00		0x00000096</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA01_RAWNAND_DATA01		0x00000096</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA02_RAWNAND_DATA02		0x00000096</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA03_RAWNAND_DATA03		0x00000096</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA04_RAWNAND_DATA04		0x00000096</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA05_RAWNAND_DATA05		0x00000096</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA06_RAWNAND_DATA06		0x00000096</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA07_RAWNAND_DATA07		0x00000096</div><div class='add'>+			MX8MN_IOMUXC_NAND_RE_B_RAWNAND_RE_B		0x00000096</div><div class='add'>+			MX8MN_IOMUXC_NAND_READY_B_RAWNAND_READY_B	0x00000056</div><div class='add'>+			MX8MN_IOMUXC_NAND_WE_B_RAWNAND_WE_B		0x00000096</div><div class='add'>+			MX8MN_IOMUXC_NAND_WP_B_RAWNAND_WP_B		0x00000096</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts<br/>new file mode 100644<br/>index 000000000000..475cbf9e0d1e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts</a></div><div class='hunk'>@@ -0,0 +1,169 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021 Collabora Ltd.</div><div class='add'>+ * Copyright 2021 BSH Hausgeraete GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mn-bsh-smm-s2-common.dtsi"</div><div class='add'>+#include &lt;dt-bindings/sound/tlv320aic31xx.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "BSH SMM S2 PRO";</div><div class='add'>+	compatible = "bsh,imx8mn-bsh-smm-s2pro", "fsl,imx8mn";</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x40000000 0x0 0x20000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-tlv320aic31xx {</div><div class='add'>+		compatible = "fsl,imx-audio-tlv320aic31xx";</div><div class='add'>+		model = "tlv320aic31xx-hifi";</div><div class='add'>+		audio-cpu = &lt;&amp;sai3&gt;;</div><div class='add'>+		audio-codec = &lt;&amp;tlv320dac3101&gt;;</div><div class='add'>+		audio-asrc = &lt;&amp;easrc&gt;;</div><div class='add'>+		audio-routing =</div><div class='add'>+			"Ext Spk", "SPL",</div><div class='add'>+			"Ext Spk", "SPR";</div><div class='add'>+		mclk-id = &lt;PLL_CLKIN_BCLK&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_input: vdd_input {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vdd_input";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;easrc {</div><div class='add'>+	fsl,asrc-rate = &lt;48000&gt;;</div><div class='add'>+	fsl,asrc-format = &lt;10&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	tlv320dac3101: audio-codec@18 {</div><div class='add'>+		compatible = "ti,tlv320dac3101";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_dac_rst&gt;;</div><div class='add'>+		reg = &lt;0x18&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		HPVDD-supply = &lt;&amp;buck4_reg&gt;;</div><div class='add'>+		SPRVDD-supply = &lt;&amp;vdd_input&gt;;</div><div class='add'>+		SPLVDD-supply = &lt;&amp;vdd_input&gt;;</div><div class='add'>+		AVDD-supply = &lt;&amp;buck4_reg&gt;;</div><div class='add'>+		IOVDD-supply = &lt;&amp;buck4_reg&gt;;</div><div class='add'>+		DVDD-supply = &lt;&amp;buck5_reg&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio1 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		ai31xx-micbias-vg = &lt;MICBIAS_AVDDV&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai3&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MN_CLK_SAI3&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MN_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;24576000&gt;;</div><div class='add'>+	fsl,sai-mclk-direction-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* eMMC */</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1_200mhz&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_dac_rst: dacrstgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6		0x19 /* DAC_RST */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_espi2: espi2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK		0x082</div><div class='add'>+			MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI		0x082</div><div class='add'>+			MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO		0x082</div><div class='add'>+			MX8MN_IOMUXC_ECSPI2_SS0_ECSPI2_SS0		0x040</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL			0x400000c3</div><div class='add'>+			MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA			0x400000c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai3: sai3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC		0xd6</div><div class='add'>+			MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK		0xd6</div><div class='add'>+			MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0		0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK			0x40000090</div><div class='add'>+			MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD			0x0d0</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x0d0</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x0d0</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x0d0</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x0d0</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4		0x0d0</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5		0x0d0</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6		0x0d0</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7		0x0d0</div><div class='add'>+			MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x090</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK			0x40000094</div><div class='add'>+			MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD			0x0d4</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x0d4</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x0d4</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x0d4</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x0d4</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4		0x0d4</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5		0x0d4</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6		0x0d4</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7		0x0d4</div><div class='add'>+			MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x094</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK			0x40000096</div><div class='add'>+			MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD			0x0d6</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x0d6</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x0d6</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x0d6</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x0d6</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4		0x0d6</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5		0x0d6</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6		0x0d6</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7		0x0d6</div><div class='add'>+			MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x096</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dts<br/>new file mode 100644<br/>index 000000000000..d25032e3ceab<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dts</a></div><div class='hunk'>@@ -0,0 +1,130 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mn.dtsi"</div><div class='add'>+#include "imx8mn-evk.dtsi"</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "NXP i.MX8MNano DDR3L EVK board";</div><div class='add'>+	compatible = "fsl,imx8mn-ddr3l-evk", "fsl,imx8mn";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	pmic: pmic@25 {</div><div class='add'>+		compatible = "nxp,pca9450b";</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;3 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			buck1: BUCK1 {</div><div class='add'>+				regulator-name = "VDD_SOC_0V9";</div><div class='add'>+				regulator-min-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;950000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck4: BUCK4 {</div><div class='add'>+				regulator-name = "VDD_3V3";</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck5: BUCK5 {</div><div class='add'>+				regulator-name = "VDD_1V8";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck6: BUCK6 {</div><div class='add'>+				regulator-name = "NVCC_DRAM_1V35";</div><div class='add'>+				regulator-min-microvolt = &lt;1350000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo1: LDO1 {</div><div class='add'>+				regulator-name = "NVCC_SNVS_1V8";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo2: LDO2 {</div><div class='add'>+				regulator-name = "VDD_SNVS_0V8";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo3: LDO3 {</div><div class='add'>+				regulator-name = "VDDA_1V8";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo4: LDO4 {</div><div class='add'>+				regulator-name = "VDD_PHY_1V2";</div><div class='add'>+				regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo5: LDO5 {</div><div class='add'>+				regulator-name = "NVCC_SD2";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	hdmi@3d {</div><div class='add'>+		avdd-supply = &lt;&amp;buck5&gt;;</div><div class='add'>+		dvdd-supply = &lt;&amp;buck5&gt;;</div><div class='add'>+		pvdd-supply = &lt;&amp;buck5&gt;;</div><div class='add'>+		a2vdd-supply = &lt;&amp;buck5&gt;;</div><div class='add'>+		v1p2-supply = &lt;&amp;buck5&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	camera@3c {</div><div class='add'>+		DOVDD-supply = &lt;&amp;buck5&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts<br/>index 2497eebb5739..6d85a0b052c9 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts</a></div><div class='hunk'>@@ -17,21 +17,33 @@</div><div class='ctx'> 	cpu-supply = &lt;&amp;buck2_reg&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;ddrc {</div><div class='ctx'> 	operating-points-v2 = &lt;&amp;ddrc_opp_table&gt;;</div><div class='ctx'> </div><div class='ctx'> 	ddrc_opp_table: opp-table {</div><div class='ctx'> 		compatible = "operating-points-v2";</div><div class='ctx'> </div><div class='del'>-		opp-25M {</div><div class='add'>+		opp-25000000 {</div><div class='ctx'> 			opp-hz = /bits/ 64 &lt;25000000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		opp-100M {</div><div class='add'>+		opp-100000000 {</div><div class='ctx'> 			opp-hz = /bits/ 64 &lt;100000000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		opp-600M {</div><div class='add'>+		opp-600000000 {</div><div class='ctx'> 			opp-hz = /bits/ 64 &lt;600000000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='hunk'>@@ -41,14 +53,19 @@</div><div class='ctx'> 	pmic@4b {</div><div class='ctx'> 		compatible = "rohm,bd71847";</div><div class='ctx'> 		reg = &lt;0x4b&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='ctx'> 		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='ctx'> 		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='del'>-		interrupts = &lt;3 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		interrupts = &lt;3 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 		rohm,reset-snvs-powered;</div><div class='ctx'> </div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clocks = &lt;&amp;osc_32k&gt;;</div><div class='add'>+		clock-output-names = "clk-32k-out";</div><div class='add'>+</div><div class='ctx'> 		regulators {</div><div class='ctx'> 			buck1_reg: BUCK1 {</div><div class='del'>-				regulator-name = "BUCK1";</div><div class='add'>+				regulator-name = "buck1";</div><div class='ctx'> 				regulator-min-microvolt = &lt;700000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='ctx'> 				regulator-boot-on;</div><div class='hunk'>@@ -57,7 +74,7 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			buck2_reg: BUCK2 {</div><div class='del'>-				regulator-name = "BUCK2";</div><div class='add'>+				regulator-name = "buck2";</div><div class='ctx'> 				regulator-min-microvolt = &lt;700000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='ctx'> 				regulator-boot-on;</div><div class='hunk'>@@ -67,14 +84,14 @@</div><div class='ctx'> </div><div class='ctx'> 			buck3_reg: BUCK3 {</div><div class='ctx'> 				// BUCK5 in datasheet</div><div class='del'>-				regulator-name = "BUCK3";</div><div class='add'>+				regulator-name = "buck3";</div><div class='ctx'> 				regulator-min-microvolt = &lt;700000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			buck4_reg: BUCK4 {</div><div class='ctx'> 				// BUCK6 in datasheet</div><div class='del'>-				regulator-name = "BUCK4";</div><div class='add'>+				regulator-name = "buck4";</div><div class='ctx'> 				regulator-min-microvolt = &lt;3000000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='ctx'> 				regulator-boot-on;</div><div class='hunk'>@@ -83,7 +100,7 @@</div><div class='ctx'> </div><div class='ctx'> 			buck5_reg: BUCK5 {</div><div class='ctx'> 				// BUCK7 in datasheet</div><div class='del'>-				regulator-name = "BUCK5";</div><div class='add'>+				regulator-name = "buck5";</div><div class='ctx'> 				regulator-min-microvolt = &lt;1605000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;1995000&gt;;</div><div class='ctx'> 				regulator-boot-on;</div><div class='hunk'>@@ -92,7 +109,7 @@</div><div class='ctx'> </div><div class='ctx'> 			buck6_reg: BUCK6 {</div><div class='ctx'> 				// BUCK8 in datasheet</div><div class='del'>-				regulator-name = "BUCK6";</div><div class='add'>+				regulator-name = "buck6";</div><div class='ctx'> 				regulator-min-microvolt = &lt;800000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;1400000&gt;;</div><div class='ctx'> 				regulator-boot-on;</div><div class='hunk'>@@ -100,23 +117,23 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			ldo1_reg: LDO1 {</div><div class='del'>-				regulator-name = "LDO1";</div><div class='del'>-				regulator-min-microvolt = &lt;3000000&gt;;</div><div class='add'>+				regulator-name = "ldo1";</div><div class='add'>+				regulator-min-microvolt = &lt;1600000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='ctx'> 				regulator-boot-on;</div><div class='ctx'> 				regulator-always-on;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			ldo2_reg: LDO2 {</div><div class='del'>-				regulator-name = "LDO2";</div><div class='del'>-				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-name = "ldo2";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;900000&gt;;</div><div class='ctx'> 				regulator-boot-on;</div><div class='ctx'> 				regulator-always-on;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			ldo3_reg: LDO3 {</div><div class='del'>-				regulator-name = "LDO3";</div><div class='add'>+				regulator-name = "ldo3";</div><div class='ctx'> 				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='ctx'> 				regulator-boot-on;</div><div class='hunk'>@@ -124,7 +141,7 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			ldo4_reg: LDO4 {</div><div class='del'>-				regulator-name = "LDO4";</div><div class='add'>+				regulator-name = "ldo4";</div><div class='ctx'> 				regulator-min-microvolt = &lt;900000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 				regulator-boot-on;</div><div class='hunk'>@@ -132,7 +149,7 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			ldo6_reg: LDO6 {</div><div class='del'>-				regulator-name = "LDO6";</div><div class='add'>+				regulator-name = "ldo6";</div><div class='ctx'> 				regulator-min-microvolt = &lt;900000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 				regulator-boot-on;</div><div class='hunk'>@@ -142,10 +159,18 @@</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;iomuxc {</div><div class='del'>-	pinctrl_pmic: pmicirq {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x41</div><div class='del'>-		&gt;;</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	hdmi@3d {</div><div class='add'>+		avdd-supply = &lt;&amp;buck5_reg&gt;;</div><div class='add'>+		dvdd-supply = &lt;&amp;buck5_reg&gt;;</div><div class='add'>+		pvdd-supply = &lt;&amp;buck5_reg&gt;;</div><div class='add'>+		a2vdd-supply = &lt;&amp;buck5_reg&gt;;</div><div class='add'>+		v1p2-supply = &lt;&amp;buck5_reg&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	camera@3c {</div><div class='add'>+		DOVDD-supply = &lt;&amp;buck5_reg&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mn-dimonoff-gateway-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-dimonoff-gateway-evk.dts<br/>new file mode 100644<br/>index 000000000000..6f9b82958b96<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mn-dimonoff-gateway-evk.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mn-dimonoff-gateway-evk.dts</a></div><div class='hunk'>@@ -0,0 +1,160 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 DimOnOff</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/usb/pd.h&gt;</div><div class='add'>+#include "imx8mn-var-som-symphony.dts"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "DimOnOff Gateway EVK board";</div><div class='add'>+	compatible = "dimonoff,gateway-evk", "variscite,var-som-mx8mn",</div><div class='add'>+		     "fsl,imx8mn";</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * U30 FPF2193 regulator.</div><div class='add'>+	 * Source = BASE_PER_3V3 = SOM_3V3 (COM pin 49).</div><div class='add'>+	 */</div><div class='add'>+	reg_disp_3v3: regulator-disp-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "Display 3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_keys&gt;;</div><div class='add'>+</div><div class='add'>+		key-enter {</div><div class='add'>+			label = "enter";</div><div class='add'>+			gpios = &lt;&amp;gpio1 8 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_ENTER&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Bourns PEC12R rotary encoder, 24 steps. */</div><div class='add'>+	rotary: rotary-encoder {</div><div class='add'>+		compatible = "rotary-encoder";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_rotary&gt;;</div><div class='add'>+		gpios = &lt;&amp;gpio5 12 GPIO_ACTIVE_LOW&gt;, /* A */</div><div class='add'>+			&lt;&amp;gpio5 13 GPIO_ACTIVE_LOW&gt;; /* B */</div><div class='add'>+		linux,axis = &lt;0&gt;; /* REL_X */</div><div class='add'>+		rotary-encoder,encoding = "gray";</div><div class='add'>+		rotary-encoder,relative-axis;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Disable Asynchronous Sample Rate Converter (audio) */</div><div class='add'>+&amp;easrc {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi1 {</div><div class='add'>+	/* Resistive touch controller */</div><div class='add'>+	/delete-node/ touchscreen@0;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	adc@48 {</div><div class='add'>+		compatible = "ti,ads7924";</div><div class='add'>+		reg = &lt;0x48&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_adc&gt;;</div><div class='add'>+		vref-supply = &lt;&amp;reg_disp_3v3&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio5 5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		channel@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			label = "Pot0";</div><div class='add'>+		};</div><div class='add'>+		channel@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			label = "Pot1";</div><div class='add'>+		};</div><div class='add'>+		channel@2 {</div><div class='add'>+			reg = &lt;2&gt;;</div><div class='add'>+			label = "Pot2";</div><div class='add'>+		};</div><div class='add'>+		channel@3 {</div><div class='add'>+			reg = &lt;3&gt;;</div><div class='add'>+			label = "Pot3";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rtc@51 {</div><div class='add'>+		compatible = "nxp,pcf2129";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		reset-source; /* For watchdog. */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rtc@53 {</div><div class='add'>+		compatible = "nxp,pcf2131";</div><div class='add'>+		reg = &lt;0x53&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_rtc&gt;;</div><div class='add'>+		reset-source; /* For watchdog. */</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio5&gt;;</div><div class='add'>+		interrupts = &lt;10 IRQ_TYPE_EDGE_FALLING&gt;; /* J17.6 on EVK */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	touchscreen@38 {</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	codec@1a {</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* DS1337 RTC module */</div><div class='add'>+	rtc@68 {</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai5 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_gpio_keys: gpiokeysgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8	0xc6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_rotary: rotarygrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_ECSPI2_MISO_GPIO5_IO12	0x00000156</div><div class='add'>+			MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13	0x00000156</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_adc: adcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5	0x00000156</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_rtc: rtcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_ECSPI2_SCLK_GPIO5_IO10	0x00000156</div><div class='add'>+			MX8MN_IOMUXC_ECSPI2_MOSI_GPIO5_IO11	0x00000156</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts<br/>index 61f351958618..41330210a05f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mn-evk.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mn-evk.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mn-evk.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mn-evk.dts</a></div><div class='hunk'>@@ -7,6 +7,7 @@</div><div class='ctx'> </div><div class='ctx'> #include "imx8mn.dtsi"</div><div class='ctx'> #include "imx8mn-evk.dtsi"</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	model = "NXP i.MX8MNano EVK board";</div><div class='hunk'>@@ -14,17 +15,129 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;A53_0 {</div><div class='del'>-	/delete-property/operating-points-v2;</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;A53_1 {</div><div class='del'>-	/delete-property/operating-points-v2;</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;A53_2 {</div><div class='del'>-	/delete-property/operating-points-v2;</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;A53_3 {</div><div class='del'>-	/delete-property/operating-points-v2;</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	pmic: pmic@25 {</div><div class='add'>+		compatible = "nxp,pca9450b";</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;3 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			buck1: BUCK1 {</div><div class='add'>+				regulator-name = "VDD_SOC";</div><div class='add'>+				regulator-min-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;950000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+				nxp,dvs-standby-voltage = &lt;750000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck2: BUCK2 {</div><div class='add'>+				regulator-name = "VDD_ARM_0V9";</div><div class='add'>+				regulator-min-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck4: BUCK4 {</div><div class='add'>+				regulator-name = "VDD_3V3";</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck5: BUCK5 {</div><div class='add'>+				regulator-name = "VDD_1V8";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck6: BUCK6 {</div><div class='add'>+				regulator-name = "NVCC_DRAM_1V1";</div><div class='add'>+				regulator-min-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo1: LDO1 {</div><div class='add'>+				regulator-name = "NVCC_SNVS_1V8";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo2: LDO2 {</div><div class='add'>+				regulator-name = "VDD_SNVS_0V8";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo3: LDO3 {</div><div class='add'>+				regulator-name = "VDDA_1V8";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo4: LDO4 {</div><div class='add'>+				regulator-name = "VDD_PHY_1V2";</div><div class='add'>+				regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo5: LDO5 {</div><div class='add'>+				regulator-name = "NVCC_SD2";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	hdmi@3d {</div><div class='add'>+		avdd-supply = &lt;&amp;buck5&gt;;</div><div class='add'>+		dvdd-supply = &lt;&amp;buck5&gt;;</div><div class='add'>+		pvdd-supply = &lt;&amp;buck5&gt;;</div><div class='add'>+		a2vdd-supply = &lt;&amp;buck5&gt;;</div><div class='add'>+		v1p2-supply = &lt;&amp;buck5&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	camera@3c {</div><div class='add'>+		DOVDD-supply = &lt;&amp;buck5&gt;;</div><div class='add'>+	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi<br/>index 85fc0aa38c4f..145355ff91b4 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi</a></div><div class='hunk'>@@ -23,6 +23,18 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	hdmi-connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		label = "hdmi";</div><div class='add'>+		type = "a";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			hdmi_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;adv7535_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	memory@40000000 {</div><div class='ctx'> 		device_type = "memory";</div><div class='ctx'> 		reg = &lt;0x0 0x40000000 0 0x80000000&gt;;</div><div class='hunk'>@@ -36,8 +48,117 @@</div><div class='ctx'> 		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='ctx'> 		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='ctx'> 		gpio = &lt;&amp;gpio2 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		off-on-delay-us = &lt;12000&gt;;</div><div class='ctx'> 		enable-active-high;</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	reg_1v5: regulator-1v5 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_1V5";</div><div class='add'>+		regulator-min-microvolt = &lt;1500000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1500000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_1v8: regulator-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vddext_3v3: regulator-vddext-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDEXT_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ir-receiver {</div><div class='add'>+		compatible = "gpio-ir-receiver";</div><div class='add'>+		gpios = &lt;&amp;gpio1 13 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_ir&gt;;</div><div class='add'>+		linux,autosuspend-period = &lt;125&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	audio_codec_bt_sco: audio-codec-bt-sco {</div><div class='add'>+		compatible = "linux,bt-sco";</div><div class='add'>+		#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wm8524: audio-codec {</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		compatible = "wlf,wm8524";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_wlf&gt;;</div><div class='add'>+		wlf,mute-gpios = &lt;&amp;gpio5 21 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-bt-sco {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,name = "bt-sco-audio";</div><div class='add'>+		simple-audio-card,format = "dsp_a";</div><div class='add'>+		simple-audio-card,bitclock-inversion;</div><div class='add'>+		simple-audio-card,frame-master = &lt;&amp;btcpu&gt;;</div><div class='add'>+		simple-audio-card,bitclock-master = &lt;&amp;btcpu&gt;;</div><div class='add'>+</div><div class='add'>+		btcpu: simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;sai2&gt;;</div><div class='add'>+			dai-tdm-slot-num = &lt;2&gt;;</div><div class='add'>+			dai-tdm-slot-width = &lt;16&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		simple-audio-card,codec {</div><div class='add'>+			sound-dai = &lt;&amp;audio_codec_bt_sco 1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-wm8524 {</div><div class='add'>+		compatible = "fsl,imx-audio-wm8524";</div><div class='add'>+		model = "wm8524-audio";</div><div class='add'>+		audio-cpu = &lt;&amp;sai3&gt;;</div><div class='add'>+		audio-codec = &lt;&amp;wm8524&gt;;</div><div class='add'>+		audio-asrc = &lt;&amp;easrc&gt;;</div><div class='add'>+		audio-routing =</div><div class='add'>+			"Line Out Jack", "LINEVOUTL",</div><div class='add'>+			"Line Out Jack", "LINEVOUTR";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spdif_out: spdif-out {</div><div class='add'>+		compatible = "linux,spdif-dit";</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spdif_in: spdif-in {</div><div class='add'>+		compatible = "linux,spdif-dir";</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-spdif {</div><div class='add'>+		compatible = "fsl,imx-audio-spdif";</div><div class='add'>+		model = "imx-spdif";</div><div class='add'>+		audio-cpu = &lt;&amp;spdif1&gt;;</div><div class='add'>+		audio-codec = &lt;&amp;spdif_out&gt;, &lt;&amp;spdif_in&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-micfil {</div><div class='add'>+		compatible = "fsl,imx-audio-card";</div><div class='add'>+		model = "micfil-audio";</div><div class='add'>+</div><div class='add'>+		pri-dai-link {</div><div class='add'>+			link-name = "micfil hifi";</div><div class='add'>+			format = "i2s";</div><div class='add'>+</div><div class='add'>+			cpu {</div><div class='add'>+				sound-dai = &lt;&amp;micfil&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;easrc {</div><div class='add'>+	fsl,asrc-rate = &lt;48000&gt;;</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;fec1 {</div><div class='hunk'>@@ -55,10 +176,35 @@</div><div class='ctx'> 		ethphy0: ethernet-phy@0 {</div><div class='ctx'> 			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='ctx'> 			reg = &lt;0&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio4 22 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;10000&gt;;</div><div class='add'>+			qca,disable-smarteee;</div><div class='add'>+			vddio-supply = &lt;&amp;vddio&gt;;</div><div class='add'>+</div><div class='add'>+			vddio: vddio-regulator {</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;flexspi {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexspi&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash0: flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		spi-max-frequency = &lt;166000000&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;4&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;i2c1 {</div><div class='ctx'> 	clock-frequency = &lt;400000&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='hunk'>@@ -68,12 +214,46 @@</div><div class='ctx'> </div><div class='ctx'> &amp;i2c2 {</div><div class='ctx'> 	clock-frequency = &lt;400000&gt;;</div><div class='del'>-	pinctrl-names = "default";</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c2_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='add'>+	hdmi@3d {</div><div class='add'>+		compatible = "adi,adv7535";</div><div class='add'>+		reg = &lt;0x3d&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;9 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		adi,dsi-lanes = &lt;4&gt;;</div><div class='add'>+		v3p3-supply = &lt;&amp;reg_vddext_3v3&gt;;</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				adv7535_in: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;dsi_out&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				adv7535_out: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;hdmi_connector_in&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	ptn5110: tcpc@50 {</div><div class='del'>-		compatible = "nxp,ptn5110";</div><div class='add'>+		compatible = "nxp,ptn5110", "tcpci";</div><div class='ctx'> 		pinctrl-names = "default";</div><div class='ctx'> 		pinctrl-0 = &lt;&amp;pinctrl_typec1&gt;;</div><div class='ctx'> 		reg = &lt;0x50&gt;;</div><div class='hunk'>@@ -81,12 +261,6 @@</div><div class='ctx'> 		interrupts = &lt;11 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 		status = "okay";</div><div class='ctx'> </div><div class='del'>-		port {</div><div class='del'>-			typec1_dr_sw: endpoint {</div><div class='del'>-				remote-endpoint = &lt;&amp;usb1_drd_sw&gt;;</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-</div><div class='ctx'> 		typec1_con: connector {</div><div class='ctx'> 			compatible = "usb-c-connector";</div><div class='ctx'> 			label = "USB-C";</div><div class='hunk'>@@ -98,14 +272,23 @@</div><div class='ctx'> 				     PDO_VAR(5000, 20000, 3000)&gt;;</div><div class='ctx'> 			op-sink-microwatt = &lt;15000000&gt;;</div><div class='ctx'> 			self-powered;</div><div class='add'>+</div><div class='add'>+			port {</div><div class='add'>+				typec1_dr_sw: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;usb1_drd_sw&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;i2c3 {</div><div class='ctx'> 	clock-frequency = &lt;400000&gt;;</div><div class='del'>-	pinctrl-names = "default";</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c3_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 18 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='ctx'> 	pca6416: gpio@20 {</div><div class='hunk'>@@ -114,24 +297,154 @@</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	camera@3c {</div><div class='add'>+		compatible = "ovti,ov5640";</div><div class='add'>+		reg = &lt;0x3c&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_camera&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX8MN_CLK_CLKO1&gt;;</div><div class='add'>+		clock-names = "xclk";</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX8MN_CLK_CLKO1&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;&amp;clk IMX8MN_CLK_24M&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;24000000&gt;;</div><div class='add'>+		powerdown-gpios = &lt;&amp;gpio1 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio1 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		AVDD-supply = &lt;&amp;reg_1v8&gt;;</div><div class='add'>+		DVDD-supply = &lt;&amp;reg_1v5&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			ov5640_to_mipi_csi2: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;imx8mn_mipi_csi_in&gt;;</div><div class='add'>+				clock-lanes = &lt;0&gt;;</div><div class='add'>+				data-lanes = &lt;1 2&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;isi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;micfil {</div><div class='add'>+	#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pdm&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MN_CLK_PDM&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MN_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;196608000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_csi {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@0 {</div><div class='add'>+			imx8mn_mipi_csi_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;ov5640_to_mipi_csi2&gt;;</div><div class='add'>+				data-lanes = &lt;1 2&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_dsi {</div><div class='add'>+	samsung,esc-clock-frequency = &lt;10000000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			dsi_out: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;adv7535_in&gt;;</div><div class='add'>+				data-lanes = &lt;1 2 3 4&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai2 {</div><div class='add'>+	#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai2&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MN_CLK_SAI2&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MN_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;24576000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai3&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MN_CLK_SAI3&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MN_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;24576000&gt;;</div><div class='add'>+	fsl,sai-mclk-direction-output;</div><div class='add'>+	clocks = &lt;&amp;clk IMX8MN_CLK_SAI3_IPG&gt;, &lt;&amp;clk IMX8MN_CLK_DUMMY&gt;,</div><div class='add'>+		&lt;&amp;clk IMX8MN_CLK_SAI3_ROOT&gt;, &lt;&amp;clk IMX8MN_CLK_DUMMY&gt;,</div><div class='add'>+		&lt;&amp;clk IMX8MN_CLK_DUMMY&gt;, &lt;&amp;clk IMX8MN_AUDIO_PLL1_OUT&gt;,</div><div class='add'>+		&lt;&amp;clk IMX8MN_AUDIO_PLL2_OUT&gt;;</div><div class='add'>+	clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;snvs_pwrkey {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;spdif1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_spdif1&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MN_CLK_SPDIF1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MN_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;24576000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 { /* BT */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MN_CLK_UART1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MN_SYS_PLL1_80M&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;uart2 { /* console */</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;uart3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MN_CLK_UART3&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MN_SYS_PLL1_80M&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbphynop1 {</div><div class='add'>+	wakeup-source;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;usbotg1 {</div><div class='ctx'> 	dr_mode = "otg";</div><div class='ctx'> 	hnp-disable;</div><div class='ctx'> 	srp-disable;</div><div class='ctx'> 	adp-disable;</div><div class='ctx'> 	usb-role-switch;</div><div class='add'>+	disable-over-current;</div><div class='add'>+	samsung,picophy-pre-emp-curr-control = &lt;3&gt;;</div><div class='add'>+	samsung,picophy-dc-vol-level-adjust = &lt;7&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='ctx'> 	port {</div><div class='hunk'>@@ -174,7 +487,13 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;iomuxc {</div><div class='del'>-	pinctrl-names = "default";</div><div class='add'>+	pinctrl_camera: cameragrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6		0x19</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x19</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1	0x59</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='ctx'> 	pinctrl_fec1: fec1grp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='hunk'>@@ -196,12 +515,35 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	pinctrl_flexspi: flexspigrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK               0x1c2</div><div class='add'>+			MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B            0x82</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0           0x82</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1           0x82</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2           0x82</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3           0x82</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	pinctrl_gpio_led: gpioledgrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16	0x19</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	pinctrl_gpio_wlf: gpiowlfgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21	0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ir: irgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13              0x4f</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	pinctrl_i2c1: i2c1grp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3</div><div class='hunk'>@@ -216,6 +558,13 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	pinctrl_i2c2_gpio: i2c2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16	0x1c3</div><div class='add'>+			MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17	0x1c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	pinctrl_i2c3: i2c3grp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3</div><div class='hunk'>@@ -223,18 +572,77 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {</div><div class='add'>+	pinctrl_i2c3_gpio: i2c3gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18	0x1c3</div><div class='add'>+			MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19	0x1c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pdm: pdmgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SAI5_MCLK_SAI5_MCLK	0xd6</div><div class='add'>+			MX8MN_IOMUXC_SAI5_RXC_PDM_CLK		0xd6</div><div class='add'>+			MX8MN_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC	0xd6</div><div class='add'>+			MX8MN_IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0	0xd6</div><div class='add'>+			MX8MN_IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1	0xd6</div><div class='add'>+			MX8MN_IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2	0xd6</div><div class='add'>+			MX8MN_IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3	0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: pmicirqgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x141</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	pinctrl_sai2: sai2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SAI2_TXC_SAI2_TX_BCLK      0xd6</div><div class='add'>+			MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC     0xd6</div><div class='add'>+			MX8MN_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0    0xd6</div><div class='add'>+			MX8MN_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0    0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai3: sai3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6</div><div class='add'>+			MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6</div><div class='add'>+			MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6</div><div class='add'>+			MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_spdif1: spdif1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT	0xd6</div><div class='add'>+			MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN		0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	pinctrl_typec1: typec1grp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11	0x159</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140</div><div class='add'>+			MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140</div><div class='add'>+			MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B	0x140</div><div class='add'>+			MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	pinctrl_uart2: uart2grp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140</div><div class='hunk'>@@ -242,7 +650,16 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pinctrl_usdhc2_gpio: usdhc2grpgpio {</div><div class='add'>+	pinctrl_uart3: uart3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX		0x140</div><div class='add'>+			MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX		0x140</div><div class='add'>+			MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B	0x140</div><div class='add'>+			MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x1c4</div><div class='ctx'> 		&gt;;</div><div class='hunk'>@@ -260,7 +677,7 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x194</div><div class='ctx'> 			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4</div><div class='hunk'>@@ -272,7 +689,7 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x196</div><div class='ctx'> 			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6</div><div class='hunk'>@@ -300,7 +717,7 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pinctrl_usdhc3_100mhz: usdhc3grp100mhz {</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x40000194</div><div class='ctx'> 			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4</div><div class='hunk'>@@ -316,7 +733,7 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pinctrl_usdhc3_200mhz: usdhc3grp200mhz {</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x40000196</div><div class='ctx'> 			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6</div><div class='hunk'>@@ -334,7 +751,7 @@</div><div class='ctx'> </div><div class='ctx'> 	pinctrl_wdog: wdoggrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='del'>-			MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0xc6</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0x166</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mn-overdrive.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-overdrive.dtsi<br/>new file mode 100644<br/>index 000000000000..5d03fb893e90<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mn-overdrive.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mn-overdrive.dtsi</a></div><div class='hunk'>@@ -0,0 +1,18 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MN_CLK_GPU_CORE&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MN_CLK_GPU_SHADER&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MN_CLK_GPU_AXI&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MN_CLK_GPU_AHB&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MN_GPU_PLL&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MN_GPU_PLL_OUT&gt;,</div><div class='add'>+				  &lt;&amp;clk IMX8MN_GPU_PLL_OUT&gt;,</div><div class='add'>+				  &lt;&amp;clk IMX8MN_SYS_PLL1_800M&gt;,</div><div class='add'>+				  &lt;&amp;clk IMX8MN_SYS_PLL1_800M&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;600000000&gt;,</div><div class='add'>+			       &lt;600000000&gt;,</div><div class='add'>+			       &lt;800000000&gt;,</div><div class='add'>+			       &lt;400000000&gt;,</div><div class='add'>+			       &lt;1200000000&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mn-rve-gateway.dts b/arch/arm64/boot/dts/freescale/imx8mn-rve-gateway.dts<br/>new file mode 100644<br/>index 000000000000..ea1855171fb0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mn-rve-gateway.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mn-rve-gateway.dts</a></div><div class='hunk'>@@ -0,0 +1,285 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 DimOnOff</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/usb/pd.h&gt;</div><div class='add'>+#include "imx8mn-var-som.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "RVE gateway";</div><div class='add'>+	compatible = "rve,gateway", "variscite,var-som-mx8mn", "fsl,imx8mn";</div><div class='add'>+</div><div class='add'>+	crystal_duart_24m: crystal-duart-24m {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_keys&gt;;</div><div class='add'>+</div><div class='add'>+		key-enter {</div><div class='add'>+			label = "enter";</div><div class='add'>+			gpios = &lt;&amp;gpio1 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_ENTER&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-exit {</div><div class='add'>+			label = "exit";</div><div class='add'>+			gpios = &lt;&amp;gpio3 23 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_ESC&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lcd {</div><div class='add'>+		compatible = "hit,hd44780";</div><div class='add'>+		display-height-chars = &lt;2&gt;;</div><div class='add'>+		display-width-chars = &lt;20&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_lcd&gt;;</div><div class='add'>+		data-gpios = &lt;&amp;gpio5  1 GPIO_ACTIVE_HIGH&gt;,</div><div class='add'>+			     &lt;&amp;gpio1  6 GPIO_ACTIVE_HIGH&gt;,</div><div class='add'>+			     &lt;&amp;gpio1 14 GPIO_ACTIVE_HIGH&gt;,</div><div class='add'>+			     &lt;&amp;gpio4 28 GPIO_ACTIVE_HIGH&gt;,</div><div class='add'>+			     &lt;&amp;gpio5 24 GPIO_ACTIVE_HIGH&gt;,</div><div class='add'>+			     &lt;&amp;gpio5  2 GPIO_ACTIVE_HIGH&gt;,</div><div class='add'>+			     &lt;&amp;gpio1 12 GPIO_ACTIVE_HIGH&gt;,</div><div class='add'>+			     &lt;&amp;gpio5 25 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;gpio5 23 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		rs-gpios = &lt;&amp;gpio1 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		rw-gpios = &lt;&amp;gpio4 27 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3p3v: regulator-3p3v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "3P3V";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Bourns PEC12R rotary encoder, 24 steps. */</div><div class='add'>+	rotary: rotary-encoder {</div><div class='add'>+		compatible = "rotary-encoder";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_rotary&gt;;</div><div class='add'>+		gpios = &lt;&amp;gpio1  5 GPIO_ACTIVE_LOW&gt;, /* A */</div><div class='add'>+			&lt;&amp;gpio3 21 GPIO_ACTIVE_LOW&gt;; /* B */</div><div class='add'>+		linux,axis = &lt;0&gt;; /* REL_X */</div><div class='add'>+		rotary-encoder,encoding = "gray";</div><div class='add'>+		rotary-encoder,relative-axis;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi1 {</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+	duart1: serial@0 {</div><div class='add'>+		compatible = "nxp,sc16is752";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;1&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;1&gt;;</div><div class='add'>+		spi-max-frequency = &lt;4000000&gt;;</div><div class='add'>+		clocks = &lt;&amp;crystal_duart_24m&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+		interrupts = &lt;22 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-line-names = "RADIO0", "RADIO1", "RADIO2", "RADIO3",</div><div class='add'>+				  "RADIO4", "RADIO_RESET", "TP12", "TP11";</div><div class='add'>+		linux,rs485-enabled-at-boot-time;</div><div class='add'>+		rs485-rts-active-low;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/delete-node/ touchscreen@0;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi2&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 13 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	/delete-property/ dmas;</div><div class='add'>+	/delete-property/ dma-names;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	duart2: serial@0 {</div><div class='add'>+		compatible = "nxp,sc16is752";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;1&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;1&gt;;</div><div class='add'>+		spi-max-frequency = &lt;4000000&gt;;</div><div class='add'>+		clocks = &lt;&amp;crystal_duart_24m&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+		interrupts = &lt;20 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-line-names = "LED_B_USER", "LED_R_USER", "LED_G_USER",</div><div class='add'>+				  "GPIO_EXT3", "GPIO_EXT2", "GPIO_EXT1",</div><div class='add'>+				  "GPIO_EXT0", "TP13";</div><div class='add'>+		linux,rs485-enabled-at-boot-time;</div><div class='add'>+		rs485-rts-active-low;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Configure PWM pins in GPIO mode: */</div><div class='add'>+&amp;gpio5 {</div><div class='add'>+	gpio-line-names = "", "", "", "PWM3", "PWM2", "PWM1";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* Carrier board EEPROM */</div><div class='add'>+	eeprom_cb: eeprom@56 {</div><div class='add'>+		compatible = "atmel,24c04";</div><div class='add'>+		reg = &lt;0x56&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lm75: sensor@48 {</div><div class='add'>+		compatible = "st,stlm75";</div><div class='add'>+		reg = &lt;0x48&gt;;</div><div class='add'>+		vs-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mcp7940: rtc@6f {</div><div class='add'>+		compatible = "microchip,mcp7940x";</div><div class='add'>+		reg = &lt;0x6f&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	codec@1a {</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pcf8574_1: gpio@38 {</div><div class='add'>+		compatible = "nxp,pcf8574";</div><div class='add'>+		reg = &lt;0x38&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-line-names = "LED_B_COMM3", "LED_R_COMM3", "LED_G_COMM3",</div><div class='add'>+				  "TP14", "TP15", "LED_G_COMM4", "LED_R_COMM4",</div><div class='add'>+				  "LED_B_COMM4";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcf8574_2: gpio@39 {</div><div class='add'>+		compatible = "nxp,pcf8574";</div><div class='add'>+		reg = &lt;0x39&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-line-names = "LED_B_COMM2", "LED_G_COMM2", "LED_B_COMM1",</div><div class='add'>+				  "LED_R_COMM2", "LED_R_COMM1", "LED_G_COMM1",</div><div class='add'>+				  "TP16", "TP17";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Bluetooth */</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	disable-over-current;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SD interface on expansion connector. */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio1 13 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_ecspi1: ecspi1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK	0x13</div><div class='add'>+			MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI	0x13</div><div class='add'>+			MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO	0x13</div><div class='add'>+			MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9	0x13 /* SS0 */</div><div class='add'>+			MX8MN_IOMUXC_SAI5_RXD1_GPIO3_IO22	0x13 /* SC16 IRQ */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi2: ecspi2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0x13</div><div class='add'>+			MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0x13</div><div class='add'>+			MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO	0x13</div><div class='add'>+			MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13	0x13 /* SS0 */</div><div class='add'>+			MX8MN_IOMUXC_SAI5_RXC_GPIO3_IO20	0x13 /* SC16 IRQ */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio_keys: gpiokeysgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1	0xc6 /* Enter */</div><div class='add'>+			MX8MN_IOMUXC_SAI5_RXD2_GPIO3_IO23	0xc6 /* Exit */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3</div><div class='add'>+			MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4: i2c4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL		0x400001c3</div><div class='add'>+			MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lcd: lcdgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SAI3_TXD_GPIO5_IO1		0x00000156 /* D0 */</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6	0x00000156 /* D1 */</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO14_GPIO1_IO14	0x00000156 /* D2 */</div><div class='add'>+			MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28	0x00000156 /* D3 */</div><div class='add'>+			MX8MN_IOMUXC_UART2_RXD_GPIO5_IO24	0x00000156 /* D4 */</div><div class='add'>+			MX8MN_IOMUXC_SAI3_MCLK_GPIO5_IO2	0x00000156 /* D5 */</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x00000156 /* D6 */</div><div class='add'>+			MX8MN_IOMUXC_UART2_TXD_GPIO5_IO25	0x00000156 /* D7 */</div><div class='add'>+			MX8MN_IOMUXC_UART1_TXD_GPIO5_IO23	0x00000156 /* E */</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7	0x00000156 /* RS */</div><div class='add'>+			MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27	0x00000156 /* R/W */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_rotary: rotarygrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5	0x00000156 /* A */</div><div class='add'>+			MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21	0x00000156 /* B */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Override Card Detect function GPIO value (GPIO1_IO10) from SOM: */</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtso b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtso<br/>new file mode 100644<br/>index 000000000000..29235e390a5d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtso</a></div><div class='hunk'>@@ -0,0 +1,45 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2022-2023 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Alexander Stein</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+</div><div class='add'>+&amp;{/} {</div><div class='add'>+	compatible = "tq,imx8mn-tqma8mqnl-mba8mx", "tq,imx8mn-tqma8mqnl", "fsl,imx8mn";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;backlight_lvds {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsi_lvds_bridge {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;expander0 {</div><div class='add'>+	dsi-mux-oe-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		output-high;</div><div class='add'>+		line-name = "DSI_MUX_OE#";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_dsi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;panel {</div><div class='add'>+	compatible = "tianma,tm070jvhg33";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx-usbotg.dtso b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx-usbotg.dtso<br/>new file mode 100644<br/>index 000000000000..1f2a0fe70a0a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx-usbotg.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx-usbotg.dtso</a></div><div class='hunk'>@@ -0,0 +1,89 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2022-2024 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Alexander Stein</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+</div><div class='add'>+#include "imx8mn-pinfunc.h"</div><div class='add'>+</div><div class='add'>+&amp;{/} {</div><div class='add'>+	connector {</div><div class='add'>+		compatible = "gpio-usb-b-connector", "usb-b-connector";</div><div class='add'>+		type = "micro";</div><div class='add'>+		label = "X19";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usb1_connector&gt;;</div><div class='add'>+		id-gpios = &lt;&amp;gpio1 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			usb_dr_connector: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;usb1_drd_sw&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * rst_usb_hub_hog and sel_usb_hub_hog have property 'output-high',</div><div class='add'>+ * dt overlay don't support /delete-property/. Both 'output-low' and</div><div class='add'>+ * 'output-high' will be exist under hog nodes if overlay file set</div><div class='add'>+ * 'output-low'. Workaround is disable these hog and create new hog with</div><div class='add'>+ * 'output-low'.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;rst_usb_hub_hog {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;expander0 {</div><div class='add'>+	rst-usb-low-hub-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;13 0&gt;;</div><div class='add'>+		output-low;</div><div class='add'>+		line-name = "RST_USB_HUB#";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sel_usb_hub_hog {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio2 {</div><div class='add'>+	sel-usb-low-hub-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		output-low;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usbotg&gt;;</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	srp-disable;</div><div class='add'>+	hnp-disable;</div><div class='add'>+	adp-disable;</div><div class='add'>+	power-active-high;</div><div class='add'>+	/delete-property/ disable-over-current;</div><div class='add'>+	over-current-active-low;</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	port {</div><div class='add'>+		usb1_drd_sw: endpoint {</div><div class='add'>+			remote-endpoint = &lt;&amp;usb_dr_connector&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_usb1_connector: usb1-connectorgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x1c0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts<br/>new file mode 100644<br/>index 000000000000..d7f7f9aafb7d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts</a></div><div class='hunk'>@@ -0,0 +1,246 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2020-2021 TQ-Systems GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mn-tqma8mqnl.dtsi"</div><div class='add'>+#include "mba8mx.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "TQ-Systems GmbH i.MX8MN TQMa8MxNL on MBa8Mx";</div><div class='add'>+	compatible = "tq,imx8mn-tqma8mqnl-mba8mx", "tq,imx8mn-tqma8mqnl", "fsl,imx8mn";</div><div class='add'>+	chassis-type = "embedded";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		eeprom0 = &amp;eeprom3;</div><div class='add'>+		mmc0 = &amp;usdhc3;</div><div class='add'>+		mmc1 = &amp;usdhc2;</div><div class='add'>+		mmc2 = &amp;usdhc1;</div><div class='add'>+		rtc0 = &amp;pcf85063;</div><div class='add'>+		rtc1 = &amp;snvs_rtc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-vmmc {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usdhc2_vmmc&gt;;</div><div class='add'>+		regulator-name = "VSD_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio2 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		startup-delay-us = &lt;100&gt;;</div><div class='add'>+		off-on-delay-us = &lt;12000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Located on TQMa8MxML-ADAP */</div><div class='add'>+&amp;gpio2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usb0hub_sel&gt;;</div><div class='add'>+</div><div class='add'>+	sel_usb_hub_hog: sel-usb-hub-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		output-high;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	expander2: gpio@27 {</div><div class='add'>+		compatible = "nxp,pca9555";</div><div class='add'>+		reg = &lt;0x27&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_vcc_3v3&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_expander2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;9 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_dsi {</div><div class='add'>+	samsung,burst-clock-frequency = &lt;891000000&gt;;</div><div class='add'>+	samsung,esc-clock-frequency = &lt;20000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai3 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MN_CLK_SAI3&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MN_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";</div><div class='add'>+	clocks = &lt;&amp;clk IMX8MN_CLK_SAI3_IPG&gt;, &lt;&amp;clk IMX8MN_CLK_DUMMY&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX8MN_CLK_SAI3_ROOT&gt;, &lt;&amp;clk IMX8MN_CLK_DUMMY&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX8MN_CLK_DUMMY&gt;, &lt;&amp;clk IMX8MN_AUDIO_PLL1_OUT&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX8MN_AUDIO_PLL2_OUT&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sound {</div><div class='add'>+	audio-asrc = &lt;&amp;easrc&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tlv320aic3x04 {</div><div class='add'>+	clock-names = "mclk";</div><div class='add'>+	clocks = &lt;&amp;clk IMX8MN_CLK_SAI3_ROOT&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	disable-over-current;</div><div class='add'>+	power-active-high;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_ecspi1: ecspi1grp {</div><div class='add'>+		fsl,pins = &lt;MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK	0x00000146&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI	0x00000146&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO	0x00000146&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9		0x00000146&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi2: ecspi2grp {</div><div class='add'>+		fsl,pins = &lt;MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0x00000146&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0x00000146&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO	0x00000146&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13		0x00000146&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_expander2: expander2grp {</div><div class='add'>+		fsl,pins = &lt;MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x94&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec1: fec1grp {</div><div class='add'>+		fsl,pins = &lt;MX8MN_IOMUXC_ENET_MDC_ENET1_MDC		0x40000002&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO		0x40000002&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x14&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x14&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x14&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x14&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x90&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x90&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x90&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x90&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x14&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x90&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x90&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x14&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpiobutton: gpiobuttongrp {</div><div class='add'>+		fsl,pins = &lt;MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5		0x84&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x84&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_SD1_CLK_GPIO2_IO0		0x84&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpioled: gpioledgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0		0x84&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_NAND_DQS_GPIO3_IO14		0x84&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001C4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001C4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2_gpio: i2c2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16		0x400001C4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17		0x400001C4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+		fsl,pins = &lt;MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001C4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001C4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3_gpio: i2c3gpiogrp {</div><div class='add'>+		fsl,pins = &lt;MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18		0x400001C4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19		0x400001C4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm3: pwm3grp {</div><div class='add'>+		fsl,pins = &lt;MX8MN_IOMUXC_GPIO1_IO14_PWM3_OUT		0x14&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm4: pwm4grp {</div><div class='add'>+		fsl,pins = &lt;MX8MN_IOMUXC_GPIO1_IO15_PWM4_OUT		0x14&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai3: sai3grp {</div><div class='add'>+		fsl,pins = &lt;MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK		0x94&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_SAI3_RXC_SAI3_RX_BCLK		0x94&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC		0x94&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0		0x94&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC		0x94&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0		0x94&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK		0x94&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX		0x16&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX		0x16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX		0x16&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX		0x16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: uart3grp {</div><div class='add'>+		fsl,pins = &lt;MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX		0x16&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX		0x16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart4: uart4grp {</div><div class='add'>+		fsl,pins = &lt;MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX		0x16&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX		0x16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usb0hub_sel: usb0hub-selgrp {</div><div class='add'>+		/* SEL_USB_HUB_B */</div><div class='add'>+		fsl,pins = &lt;MX8MN_IOMUXC_SD1_CMD_GPIO2_IO1		0x84&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usbotg: usbotggrp {</div><div class='add'>+		fsl,pins = &lt;MX8MN_IOMUXC_GPIO1_IO12_USB1_OTG_PWR	0x84&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_GPIO1_IO13_USB1_OTG_OC		0x84&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x84&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x84&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x84&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2-gpiogrp {</div><div class='add'>+		fsl,pins = &lt;MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12		0x84&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi<br/>new file mode 100644<br/>index 000000000000..1d23814e11cd<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi</a></div><div class='hunk'>@@ -0,0 +1,338 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2020-2021 TQ-Systems GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "imx8mn.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "TQ-Systems i.MX8MN TQMa8MxNL";</div><div class='add'>+	compatible = "tq,imx8mn-tqma8mqnl", "fsl,imx8mn";</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		/*  our minimum RAM config will be 1024 MiB */</div><div class='add'>+		reg = &lt;0x00000000 0x40000000 0 0x40000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* e-MMC IO, needed for HS modes */</div><div class='add'>+	reg_vcc1v8: regulator-vcc1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "TQMA8MXNL_VCC1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc3v3: regulator-vcc3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "TQMA8MXNL_VCC3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		/* global autoconfigured region for contiguous allocations */</div><div class='add'>+		linux,cma {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reusable;</div><div class='add'>+			/* 640 MiB */</div><div class='add'>+			size = &lt;0 0x28000000&gt;;</div><div class='add'>+			/*  1024 - 128 MiB, our minimum RAM config will be 1024 MiB */</div><div class='add'>+			alloc-ranges = &lt;0 0x40000000 0 0x78000000&gt;;</div><div class='add'>+			linux,cma-default;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;easrc {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexspi {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexspi&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash0: flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;84000000&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;1&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;buck5_reg&gt;;</div><div class='add'>+</div><div class='add'>+		partitions {</div><div class='add'>+			compatible = "fixed-partitions";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c1_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	sensor0: temperature-sensor@1b {</div><div class='add'>+		compatible = "nxp,se97b", "jedec,jc-42.4-temp";</div><div class='add'>+		reg = &lt;0x1b&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pca9450: pmic@25 {</div><div class='add'>+		compatible = "nxp,pca9450a";</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+</div><div class='add'>+		/* PMIC PCA9450 PMIC_nINT GPIO1_IO08 */</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;8 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			/* V_0V85_SOC: 0.85 .. 0.95 */</div><div class='add'>+			buck1_reg: BUCK1 {</div><div class='add'>+				regulator-name = "BUCK1";</div><div class='add'>+				regulator-min-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;950000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* VDD_ARM */</div><div class='add'>+			buck2_reg: BUCK2 {</div><div class='add'>+				regulator-name = "BUCK2";</div><div class='add'>+				regulator-min-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				nxp,dvs-run-voltage = &lt;950000&gt;;</div><div class='add'>+				nxp,dvs-standby-voltage = &lt;850000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* V_0V85_GPU / DRAM: shall be equal to BUCK1 for i.MX8MN */</div><div class='add'>+			buck3_reg: BUCK3 {</div><div class='add'>+				regulator-name = "BUCK3";</div><div class='add'>+				regulator-min-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;950000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* VCC3V3 -&gt; VMMC, ... must not be changed */</div><div class='add'>+			buck4_reg: BUCK4 {</div><div class='add'>+				regulator-name = "BUCK4";</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* V_1V8 -&gt; VQMMC, SPI-NOR, ... must not be changed */</div><div class='add'>+			buck5_reg: BUCK5 {</div><div class='add'>+				regulator-name = "BUCK5";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* V_1V1 -&gt; RAM, ... must not be changed */</div><div class='add'>+			buck6_reg: BUCK6 {</div><div class='add'>+				regulator-name = "BUCK6";</div><div class='add'>+				regulator-min-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* V_1V8_SNVS */</div><div class='add'>+			ldo1_reg: LDO1 {</div><div class='add'>+				regulator-name = "LDO1";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* V_0V8_SNVS */</div><div class='add'>+			ldo2_reg: LDO2 {</div><div class='add'>+				regulator-name = "LDO2";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* V_1V8_ANA */</div><div class='add'>+			ldo3_reg: LDO3 {</div><div class='add'>+				regulator-name = "LDO3";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* V_0V9_MIPI */</div><div class='add'>+			ldo4_reg: LDO4 {</div><div class='add'>+				regulator-name = "LDO4";</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* VCC SD IO - switched using SD2 VSELECT */</div><div class='add'>+			ldo5_reg: LDO5 {</div><div class='add'>+				regulator-name = "LDO5";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcf85063: rtc@51 {</div><div class='add'>+		compatible = "nxp,pcf85063a";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		quartz-load-femtofarads = &lt;7000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom1: eeprom@53 {</div><div class='add'>+		compatible = "nxp,se97b", "atmel,24c02";</div><div class='add'>+		read-only;</div><div class='add'>+		reg = &lt;0x53&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_vcc3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom0: eeprom@57 {</div><div class='add'>+		compatible = "atmel,24c64";</div><div class='add'>+		reg = &lt;0x57&gt;;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_vcc3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_dsi {</div><div class='add'>+	vddcore-supply = &lt;&amp;ldo4_reg&gt;;</div><div class='add'>+	vddio-supply = &lt;&amp;ldo3_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	no-sd;</div><div class='add'>+	no-sdio;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_vcc3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_vcc1v8&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Attention:</div><div class='add'>+ * wdog reset is routed to PMIC, PMIC must be preconfigured to force POR</div><div class='add'>+ * without LDO for SNVS. GPIO1_IO02 must not be used as GPIO.</div><div class='add'>+ */</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_flexspi: flexspigrp {</div><div class='add'>+		fsl,pins = &lt;MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK		0x84&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B	0x84&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0	0x84&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1	0x84&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2	0x84&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3	0x84&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1_gpio: i2c1gpiogrp {</div><div class='add'>+		fsl,pins = &lt;MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14	0x400001c4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15	0x400001c4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: pmicgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8	0x84&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19		0x84&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d2&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x84&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B	0x84&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x1d2&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d2&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x84&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B	0x84&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x1d6&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d2&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x84&gt;,</div><div class='add'>+			   &lt;MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B	0x84&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0x84&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts<br/>new file mode 100644<br/>index 000000000000..3434b189fa58<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts</a></div><div class='hunk'>@@ -0,0 +1,237 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Supports Symphony evaluation board versions &gt;= 1.4a.</div><div class='add'>+ *</div><div class='add'>+ * Copyright 2019-2020 Variscite Ltd.</div><div class='add'>+ * Copyright (C) 2020 Krzysztof Kozlowski &lt;krzk@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/usb/pd.h&gt;</div><div class='add'>+#include "imx8mn-var-som.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Variscite VAR-SOM-MX8MN Symphony evaluation board";</div><div class='add'>+	compatible = "variscite,var-som-mx8mn-symphony", "variscite,var-som-mx8mn", "fsl,imx8mn";</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usdhc2_vmmc&gt;;</div><div class='add'>+		regulator-name = "VSD_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio4 22 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		key-back {</div><div class='add'>+			label = "Back";</div><div class='add'>+			gpios = &lt;&amp;pca9534 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_BACK&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-home {</div><div class='add'>+			label = "Home";</div><div class='add'>+			gpios = &lt;&amp;pca9534 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_HOME&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-menu {</div><div class='add'>+			label = "Menu";</div><div class='add'>+			gpios = &lt;&amp;pca9534 3 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_MENU&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led {</div><div class='add'>+			label = "Heartbeat";</div><div class='add'>+			gpios = &lt;&amp;pca9534 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Peripherals supply, enabled by Q2 after SOM_3V3 rises. */</div><div class='add'>+	reg_per_3v3: regulator-peripheral-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "per_3v3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethphy {</div><div class='add'>+	reset-gpios = &lt;&amp;pca9534 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pca9534: gpio@20 {</div><div class='add'>+		compatible = "nxp,pca9534";</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pca9534&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;7 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		wakeup-source;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_per_3v3&gt;;</div><div class='add'>+</div><div class='add'>+		/* USB 3.0 OTG (usbotg1) / SATA port switch, set to USB 3.0 */</div><div class='add'>+		usb3-sata-sel-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+			line-name = "usb3_sata_sel";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		som-vselect-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+			line-name = "som_vselect";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		enet-sel-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+			line-name = "enet_sel";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * For Symphony board version &lt;= 1.4, the PTN5150 IRQ pin is connected</div><div class='add'>+	 * to GPIO1_IO11 on the SoM (R106 present, R132 absent). From Symphony</div><div class='add'>+	 * board version &gt;= 1.4a, the PTN5150 ID pin is connected to GPIO1_IO11</div><div class='add'>+	 * on the SoM (R106 absent, R132 present).</div><div class='add'>+	 */</div><div class='add'>+	extcon_usbotg1: typec@3d {</div><div class='add'>+		compatible = "nxp,ptn5150";</div><div class='add'>+		reg = &lt;0x3d&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;11 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_ptn5150&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			typec1_dr_sw: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;usb1_drd_sw&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	/* Capacitive touch controller */</div><div class='add'>+	ft5x06_ts: touchscreen@38 {</div><div class='add'>+		compatible = "edt,edt-ft5406";</div><div class='add'>+		reg = &lt;0x38&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_captouch&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio5&gt;;</div><div class='add'>+		interrupts = &lt;4 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+		touchscreen-size-x = &lt;800&gt;;</div><div class='add'>+		touchscreen-size-y = &lt;480&gt;;</div><div class='add'>+		touchscreen-inverted-x;</div><div class='add'>+		touchscreen-inverted-y;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rtc@68 {</div><div class='add'>+		compatible = "dallas,ds1337";</div><div class='add'>+		reg = &lt;0x68&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Header */</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Header */</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	hnp-disable;</div><div class='add'>+	srp-disable;</div><div class='add'>+	adp-disable;</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	disable-over-current;</div><div class='add'>+	samsung,picophy-pre-emp-curr-control = &lt;3&gt;;</div><div class='add'>+	samsung,picophy-dc-vol-level-adjust = &lt;7&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	port {</div><div class='add'>+		usb1_drd_sw: endpoint {</div><div class='add'>+			remote-endpoint = &lt;&amp;typec1_dr_sw&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_captouch: captouchgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4		0x16</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3</div><div class='add'>+			MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pca9534: pca9534grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7	0x16</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ptn5150: ptn5150grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11	0x16</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140</div><div class='add'>+			MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: uart3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX	0x140</div><div class='add'>+			MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi<br/>new file mode 100644<br/>index 000000000000..38ef9e4fdf07<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi</a></div><div class='hunk'>@@ -0,0 +1,570 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2019 NXP</div><div class='add'>+ * Copyright 2019-2020 Variscite Ltd.</div><div class='add'>+ * Copyright (C) 2020 Krzysztof Kozlowski &lt;krzk@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "imx8mn.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Variscite VAR-SOM-MX8MN module";</div><div class='add'>+	compatible = "variscite,var-som-mx8mn", "fsl,imx8mn";</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart4;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x40000000 0 0x40000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_eth_phy: regulator-eth-phy {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_eth_phy&gt;;</div><div class='add'>+		regulator-name = "eth_phy_pwr";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-enable-ramp-delay = &lt;20000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio2 9 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3v3_fixed: regulator-3v3-fixed {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "fixed_3v3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi1&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio1 14 GPIO_ACTIVE_LOW&gt;,</div><div class='add'>+		   &lt;&amp;gpio1  0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	/delete-property/ dmas;</div><div class='add'>+	/delete-property/ dma-names;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* Resistive touch controller */</div><div class='add'>+	touchscreen@0 {</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		compatible = "ti,ads7846";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_restouch&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;3 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+</div><div class='add'>+		spi-max-frequency = &lt;1500000&gt;;</div><div class='add'>+		pendown-gpio = &lt;&amp;gpio1 3 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		ti,x-min = /bits/ 16 &lt;125&gt;;</div><div class='add'>+		touchscreen-size-x = &lt;4008&gt;;</div><div class='add'>+		ti,y-min = /bits/ 16 &lt;282&gt;;</div><div class='add'>+		touchscreen-size-y = &lt;3864&gt;;</div><div class='add'>+		ti,x-plate-ohms = /bits/ 16 &lt;180&gt;;</div><div class='add'>+		touchscreen-max-pressure = &lt;255&gt;;</div><div class='add'>+		touchscreen-average-samples = &lt;10&gt;;</div><div class='add'>+		ti,debounce-tol = /bits/ 16 &lt;3&gt;;</div><div class='add'>+		ti,debounce-rep = /bits/ 16 &lt;1&gt;;</div><div class='add'>+		ti,settle-delay-usec = /bits/ 16 &lt;150&gt;;</div><div class='add'>+		ti,keep-vref-on;</div><div class='add'>+		wakeup-source;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_fec1_sleep&gt;;</div><div class='add'>+	phy-mode = "rgmii";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy&gt;;</div><div class='add'>+	phy-supply = &lt;&amp;reg_eth_phy&gt;;</div><div class='add'>+	fsl,magic-packet;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy: ethernet-phy@4 { /* AR8033 or ADIN1300 */</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;4&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio1 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;10000&gt;;</div><div class='add'>+			/*</div><div class='add'>+			 * Deassert delay:</div><div class='add'>+			 * ADIN1300 requires 5ms.</div><div class='add'>+			 * AR8033   requires 1ms.</div><div class='add'>+			 */</div><div class='add'>+			reset-deassert-us = &lt;20000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pmic@4b {</div><div class='add'>+		compatible = "rohm,bd71847";</div><div class='add'>+		reg = &lt;0x4b&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio2&gt;;</div><div class='add'>+		interrupts = &lt;8 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		rohm,reset-snvs-powered;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			buck1_reg: BUCK1 {</div><div class='add'>+				regulator-name = "buck1";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;1250&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck2_reg: BUCK2 {</div><div class='add'>+				regulator-name = "buck2";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;1250&gt;;</div><div class='add'>+				rohm,dvs-run-voltage = &lt;1000000&gt;;</div><div class='add'>+				rohm,dvs-idle-voltage = &lt;900000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck3_reg: BUCK3 {</div><div class='add'>+				regulator-name = "buck3";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck4_reg: BUCK4 {</div><div class='add'>+				regulator-name = "buck4";</div><div class='add'>+				regulator-min-microvolt = &lt;2600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck5_reg: BUCK5 {</div><div class='add'>+				regulator-name = "buck5";</div><div class='add'>+				regulator-min-microvolt = &lt;1605000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1995000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck6_reg: BUCK6 {</div><div class='add'>+				regulator-name = "buck6";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo1_reg: LDO1 {</div><div class='add'>+				regulator-name = "ldo1";</div><div class='add'>+				regulator-min-microvolt = &lt;1600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1900000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo2_reg: LDO2 {</div><div class='add'>+				regulator-name = "ldo2";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo3_reg: LDO3 {</div><div class='add'>+				regulator-name = "ldo3";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo4_reg: LDO4 {</div><div class='add'>+				regulator-name = "ldo4";</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo5_reg: LDO5 {</div><div class='add'>+				regulator-name = "ldo5";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo6_reg: LDO6 {</div><div class='add'>+				regulator-name = "ldo6";</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom_som: eeprom@52 {</div><div class='add'>+		compatible = "atmel,24c04";</div><div class='add'>+		reg = &lt;0x52&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_3v3_fixed&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* TODO: configure audio, as of now just put a placeholder */</div><div class='add'>+	wm8904: codec@1a {</div><div class='add'>+		compatible = "wlf,wm8904";</div><div class='add'>+		reg = &lt;0x1a&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;snvs_pwrkey {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Bluetooth */</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MN_CLK_UART2&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MN_SYS_PLL1_80M&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Console */</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* WIFI */</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1_200mhz&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	keep-power-in-suspend;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	brcmf: wifi@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		compatible = "brcm,bcm4329-fmac";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SD */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MN_CLK_USDHC2&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;200000000&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio1 10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* eMMC */</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MN_CLK_USDHC3_ROOT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_ecspi1: ecspi1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK		0x13</div><div class='add'>+			MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI		0x13</div><div class='add'>+			MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO		0x13</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO14_GPIO1_IO14		0x13</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0		0x13</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec1: fec1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_ENET_MDC_ENET1_MDC			0x3</div><div class='add'>+			MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3</div><div class='add'>+			MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f</div><div class='add'>+			MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f</div><div class='add'>+			MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f</div><div class='add'>+			MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f</div><div class='add'>+			MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91</div><div class='add'>+			MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91</div><div class='add'>+			MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91</div><div class='add'>+			MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91</div><div class='add'>+			MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f</div><div class='add'>+			MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91</div><div class='add'>+			MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91</div><div class='add'>+			MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x159</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec1_sleep: fec1sleepgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16		0x120</div><div class='add'>+			MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17		0x120</div><div class='add'>+			MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18		0x120</div><div class='add'>+			MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19		0x120</div><div class='add'>+			MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20		0x120</div><div class='add'>+			MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21		0x120</div><div class='add'>+			MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29		0x120</div><div class='add'>+			MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28		0x120</div><div class='add'>+			MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27		0x120</div><div class='add'>+			MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26		0x120</div><div class='add'>+			MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23		0x120</div><div class='add'>+			MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25		0x120</div><div class='add'>+			MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24		0x120</div><div class='add'>+			MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22		0x120</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x120</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3</div><div class='add'>+			MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3</div><div class='add'>+			MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: pmicirqgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8	0x141</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_eth_phy: regethphygrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_restouch: restouchgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x1c0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX	0x140</div><div class='add'>+			MX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX	0x140</div><div class='add'>+			MX8MN_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B	0x140</div><div class='add'>+			MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart4: uart4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX	0x140</div><div class='add'>+			MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK		0x190</div><div class='add'>+			MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d0</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d0</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d0</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d0</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK		0x194</div><div class='add'>+			MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d4</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d4</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d4</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d4</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK		0x196</div><div class='add'>+			MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d6</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d6</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d6</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d6</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x190</div><div class='add'>+			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x194</div><div class='add'>+			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x196</div><div class='add'>+			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK	0x190</div><div class='add'>+			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d0</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d0</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d0</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d0</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d0</div><div class='add'>+			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d0</div><div class='add'>+			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d0</div><div class='add'>+			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d0</div><div class='add'>+			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d0</div><div class='add'>+			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x190</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK	0x194</div><div class='add'>+			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d4</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4</div><div class='add'>+			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d4</div><div class='add'>+			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d4</div><div class='add'>+			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d4</div><div class='add'>+			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d4</div><div class='add'>+			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x194</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK	0x196</div><div class='add'>+			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d6</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d6</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d6</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d6</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d6</div><div class='add'>+			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d6</div><div class='add'>+			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d6</div><div class='add'>+			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d6</div><div class='add'>+			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d6</div><div class='add'>+			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x196</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0x166</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts<br/>new file mode 100644<br/>index 000000000000..5aa0e2cd155e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts</a></div><div class='hunk'>@@ -0,0 +1,1016 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021 Gateworks Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/linux-event-codes.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/net/ti-dp83867.h&gt;</div><div class='add'>+</div><div class='add'>+#include "imx8mn.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Gateworks Venice GW7902 i.MX8MN board";</div><div class='add'>+	compatible = "gw,imx8mn-gw7902", "fsl,imx8mn";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		rtc0 = &amp;gsc_rtc;</div><div class='add'>+		rtc1 = &amp;snvs_rtc;</div><div class='add'>+		usb0 = &amp;usbotg1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x40000000 0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	can20m: can20m {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;20000000&gt;;</div><div class='add'>+		clock-output-names = "can20m";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		key-user-pb {</div><div class='add'>+			label = "user_pb";</div><div class='add'>+			gpios = &lt;&amp;gpio 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;BTN_0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-user-pb1x {</div><div class='add'>+			label = "user_pb1x";</div><div class='add'>+			linux,code = &lt;BTN_1&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gsc&gt;;</div><div class='add'>+			interrupts = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-erased {</div><div class='add'>+			label = "key_erased";</div><div class='add'>+			linux,code = &lt;BTN_2&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gsc&gt;;</div><div class='add'>+			interrupts = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-eeprom-wp {</div><div class='add'>+			label = "eeprom_wp";</div><div class='add'>+			linux,code = &lt;BTN_3&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gsc&gt;;</div><div class='add'>+			interrupts = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-tamper {</div><div class='add'>+			label = "tamper";</div><div class='add'>+			linux,code = &lt;BTN_4&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gsc&gt;;</div><div class='add'>+			interrupts = &lt;5&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		switch-hold {</div><div class='add'>+			label = "switch_hold";</div><div class='add'>+			linux,code = &lt;BTN_5&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gsc&gt;;</div><div class='add'>+			interrupts = &lt;7&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	led-controller {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_leds&gt;;</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			label = "panel1";</div><div class='add'>+			gpios = &lt;&amp;gpio3 21 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			label = "panel2";</div><div class='add'>+			gpios = &lt;&amp;gpio3 23 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-2 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			label = "panel3";</div><div class='add'>+			gpios = &lt;&amp;gpio3 22 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-3 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			label = "panel4";</div><div class='add'>+			gpios = &lt;&amp;gpio3 20 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-4 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			label = "panel5";</div><div class='add'>+			gpios = &lt;&amp;gpio3 25 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pps {</div><div class='add'>+		compatible = "pps-gpio";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pps&gt;;</div><div class='add'>+		gpios = &lt;&amp;gpio3 24 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3p3v: regulator-3p3v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "3P3V";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb1_vbus: regulator-usb1 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usb1&gt;;</div><div class='add'>+		regulator-name = "usb_usb1_vbus";</div><div class='add'>+		gpio = &lt;&amp;gpio2 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_wifi: regulator-wifi {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_wl&gt;;</div><div class='add'>+		regulator-name = "wifi";</div><div class='add'>+		gpio = &lt;&amp;gpio2 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		startup-delay-us = &lt;100&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ddrc {</div><div class='add'>+	operating-points-v2 = &lt;&amp;ddrc_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+	ddrc_opp_table: opp-table {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		opp-25000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;25000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-100000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;100000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-750000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;750000000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_spi1&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	can@0 {</div><div class='add'>+		compatible = "microchip,mcp2515";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		clocks = &lt;&amp;can20m&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio2&gt;;</div><div class='add'>+		interrupts = &lt;3 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		spi-max-frequency = &lt;10000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;disp_blk_ctrl {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* off-board header */</div><div class='add'>+&amp;ecspi2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_spi2&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 13 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec1&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	local-mac-address = [00 00 00 00 00 00];</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@0 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			ti,clk-output-sel = &lt;DP83867_CLK_O_SEL_OFF&gt;;</div><div class='add'>+			ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_2_00_NS&gt;;</div><div class='add'>+			ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_2_00_NS&gt;;</div><div class='add'>+			tx-fifo-depth = &lt;DP83867_PHYCR_FIFO_DEPTH_4_B_NIB&gt;;</div><div class='add'>+			rx-fifo-depth = &lt;DP83867_PHYCR_FIFO_DEPTH_4_B_NIB&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	gpio-line-names = "", "", "", "", "", "", "", "",</div><div class='add'>+		"m2_pwr_en", "", "", "", "", "m2_reset", "", "m2_wdis#",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio2 {</div><div class='add'>+	gpio-line-names = "", "", "", "", "", "", "", "",</div><div class='add'>+		"uart2_en#", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio3 {</div><div class='add'>+	gpio-line-names = "", "m2_gdis#", "", "", "", "", "", "m2_off#",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	gpio-line-names = "", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "app_gpio1", "vdd_4p0_en", "uart1_rs485",</div><div class='add'>+		"", "uart1_term", "uart1_half", "app_gpio2",</div><div class='add'>+		"mipi_gpio1", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio5 {</div><div class='add'>+	gpio-line-names = "", "", "", "mipi_gpio4",</div><div class='add'>+		"mipi_gpio3", "mipi_gpio2", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c1_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	gsc: gsc@20 {</div><div class='add'>+		compatible = "gw,gsc";</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gsc&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio2&gt;;</div><div class='add'>+		interrupts = &lt;6 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		adc {</div><div class='add'>+			compatible = "gw,gsc-adc";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			channel@6 {</div><div class='add'>+				gw,mode = &lt;0&gt;;</div><div class='add'>+				reg = &lt;0x06&gt;;</div><div class='add'>+				label = "temp";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@8 {</div><div class='add'>+				gw,mode = &lt;3&gt;;</div><div class='add'>+				reg = &lt;0x08&gt;;</div><div class='add'>+				label = "vdd_bat";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@82 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x82&gt;;</div><div class='add'>+				label = "vin";</div><div class='add'>+				gw,voltage-divider-ohms = &lt;22100 1000&gt;;</div><div class='add'>+				gw,voltage-offset-microvolt = &lt;700000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@84 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x84&gt;;</div><div class='add'>+				label = "vin_4p0";</div><div class='add'>+				gw,voltage-divider-ohms = &lt;10000 10000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@86 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x86&gt;;</div><div class='add'>+				label = "vdd_3p3";</div><div class='add'>+				gw,voltage-divider-ohms = &lt;10000 10000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@88 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x88&gt;;</div><div class='add'>+				label = "vdd_0p9";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@8c {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x8c&gt;;</div><div class='add'>+				label = "vdd_soc";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@8e {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x8e&gt;;</div><div class='add'>+				label = "vdd_arm";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@90 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x90&gt;;</div><div class='add'>+				label = "vdd_1p8";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@92 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x92&gt;;</div><div class='add'>+				label = "vdd_dram";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@98 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x98&gt;;</div><div class='add'>+				label = "vdd_1p0";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@9a {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x9a&gt;;</div><div class='add'>+				label = "vdd_2p5";</div><div class='add'>+				gw,voltage-divider-ohms = &lt;10000 10000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@9c {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x9c&gt;;</div><div class='add'>+				label = "vdd_5p0";</div><div class='add'>+				gw,voltage-divider-ohms = &lt;10000 10000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@a2 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0xa2&gt;;</div><div class='add'>+				label = "vdd_gsc";</div><div class='add'>+				gw,voltage-divider-ohms = &lt;10000 10000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio: gpio@23 {</div><div class='add'>+		compatible = "nxp,pca9555";</div><div class='add'>+		reg = &lt;0x23&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gsc&gt;;</div><div class='add'>+		interrupts = &lt;4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmic@4b {</div><div class='add'>+		compatible = "rohm,bd71847";</div><div class='add'>+		reg = &lt;0x4b&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+		interrupts = &lt;8 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		rohm,reset-snvs-powered;</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clocks = &lt;&amp;osc_32k&gt;;</div><div class='add'>+		clock-output-names = "clk-32k-out";</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			/* vdd_soc: 0.805-0.900V (typ=0.8V) */</div><div class='add'>+			BUCK1 {</div><div class='add'>+				regulator-name = "buck1";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;1250&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* vdd_arm: 0.805-1.0V (typ=0.9V) */</div><div class='add'>+			buck2: BUCK2 {</div><div class='add'>+				regulator-name = "buck2";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;1250&gt;;</div><div class='add'>+				rohm,dvs-run-voltage = &lt;1000000&gt;;</div><div class='add'>+				rohm,dvs-idle-voltage = &lt;900000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* vdd_0p9: 0.805-1.0V (typ=0.9V) */</div><div class='add'>+			BUCK3 {</div><div class='add'>+				regulator-name = "buck3";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* vdd_3p3 */</div><div class='add'>+			BUCK4 {</div><div class='add'>+				regulator-name = "buck4";</div><div class='add'>+				regulator-min-microvolt = &lt;3000000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* vdd_1p8 */</div><div class='add'>+			BUCK5 {</div><div class='add'>+				regulator-name = "buck5";</div><div class='add'>+				regulator-min-microvolt = &lt;1605000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1995000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* vdd_dram */</div><div class='add'>+			BUCK6 {</div><div class='add'>+				regulator-name = "buck6";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* nvcc_snvs_1p8 */</div><div class='add'>+			LDO1 {</div><div class='add'>+				regulator-name = "ldo1";</div><div class='add'>+				regulator-min-microvolt = &lt;1600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1900000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* vdd_snvs_0p8 */</div><div class='add'>+			LDO2 {</div><div class='add'>+				regulator-name = "ldo2";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* vdda_1p8 */</div><div class='add'>+			LDO3 {</div><div class='add'>+				regulator-name = "ldo3";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			LDO4 {</div><div class='add'>+				regulator-name = "ldo4";</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			LDO6 {</div><div class='add'>+				regulator-name = "ldo6";</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@50 {</div><div class='add'>+		compatible = "atmel,24c02";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@51 {</div><div class='add'>+		compatible = "atmel,24c02";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@52 {</div><div class='add'>+		compatible = "atmel,24c02";</div><div class='add'>+		reg = &lt;0x52&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@53 {</div><div class='add'>+		compatible = "atmel,24c02";</div><div class='add'>+		reg = &lt;0x53&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gsc_rtc: rtc@68 {</div><div class='add'>+		compatible = "dallas,ds1672";</div><div class='add'>+		reg = &lt;0x68&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c2_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	accelerometer@19 {</div><div class='add'>+		compatible = "st,lis2de12";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_accel&gt;;</div><div class='add'>+		reg = &lt;0x19&gt;;</div><div class='add'>+		st,drdy-int-pin = &lt;1&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;12 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* off-board header */</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c3_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* off-board header */</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c4&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c4_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pgc_gpumix {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* off-board header */</div><div class='add'>+&amp;sai3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai3&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MN_CLK_SAI3&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MN_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;24576000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* RS232/RS485/RS422 selectable */</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;, &lt;&amp;pinctrl_uart1_gpio&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* RS232 console */</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* bluetooth HCI */</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;, &lt;&amp;pinctrl_uart3_gpio&gt;;</div><div class='add'>+	rts-gpios = &lt;&amp;gpio2 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	cts-gpios = &lt;&amp;gpio2 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "brcm,bcm4330-bt";</div><div class='add'>+		shutdown-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* LTE Cat M1/NB1/EGPRS modem or GPS (loading option) */</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usb1_vbus&gt;;</div><div class='add'>+	disable-over-current;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SDIO WiFi */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_wifi&gt;;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	wifi@0 {</div><div class='add'>+		compatible = "brcm,bcm43455-fmac", "brcm,bcm4329-fmac";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* eMMC */</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MN_CLK_USDHC3&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hog&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl_hog: hoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1	0x40000159 /* M2_GDIS# */</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8	0x40000041 /* M2_PWR_EN */</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13	0x40000041 /* M2_RESET */</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7	0x40000119 /* M2_OFF# */</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x40000159 /* M2_WDIS# */</div><div class='add'>+			MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21	0x40000041 /* APP GPIO1 */</div><div class='add'>+			MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22	0x40000041 /* VDD_4P0_EN */</div><div class='add'>+			MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27	0x40000041 /* APP GPIO2 */</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8	0x40000041 /* UART2_EN# */</div><div class='add'>+			MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28	0x40000041 /* MIPI_GPIO1 */</div><div class='add'>+			MX8MN_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5	0x40000041 /* MIPI_GPIO2 */</div><div class='add'>+			MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4		0x40000041 /* MIPI_GPIO3/PWM2 */</div><div class='add'>+			MX8MN_IOMUXC_SPDIF_TX_GPIO5_IO3		0x40000041 /* MIPI_GPIO4/PWM3 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_accel: accelgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x159</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec1: fec1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_ENET_MDC_ENET1_MDC			0x3</div><div class='add'>+			MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3</div><div class='add'>+			MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f</div><div class='add'>+			MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f</div><div class='add'>+			MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f</div><div class='add'>+			MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f</div><div class='add'>+			MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91</div><div class='add'>+			MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91</div><div class='add'>+			MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91</div><div class='add'>+			MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91</div><div class='add'>+			MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f</div><div class='add'>+			MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91</div><div class='add'>+			MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91</div><div class='add'>+			MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x19 /* RST# */</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x19 /* IRQ# */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gsc: gscgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6	0x40</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3</div><div class='add'>+			MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1_gpio: i2c1gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14	0x400001c3</div><div class='add'>+			MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15	0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3</div><div class='add'>+			MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2_gpio: i2c2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16	0x400001c3</div><div class='add'>+			MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17	0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3</div><div class='add'>+			MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3_gpio: i2c3gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18	0x400001c3</div><div class='add'>+			MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19	0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4: i2c4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL		0x400001c3</div><div class='add'>+			MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4_gpio: i2c4gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_I2C4_SCL_GPIO5_IO20	0x400001c3</div><div class='add'>+			MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21	0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio_leds: gpioledgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21	0x19</div><div class='add'>+			MX8MN_IOMUXC_SAI5_RXD2_GPIO3_IO23	0x19</div><div class='add'>+			MX8MN_IOMUXC_SAI5_RXD1_GPIO3_IO22	0x19</div><div class='add'>+			MX8MN_IOMUXC_SAI5_RXC_GPIO3_IO20	0x19</div><div class='add'>+			MX8MN_IOMUXC_SAI5_MCLK_GPIO3_IO25	0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: pmicgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA02_GPIO3_IO8	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pps: ppsgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SAI5_RXD3_GPIO3_IO24	0x141 /* PPS */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_wl: regwlgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41 /* WLAN_WLON */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usb1: regusb1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai3: sai3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK	0xd6</div><div class='add'>+			MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0	0xd6</div><div class='add'>+			MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK	0xd6</div><div class='add'>+			MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0	0xd6</div><div class='add'>+			MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC	0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_spi1: spi1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK	0x82</div><div class='add'>+			MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI	0x82</div><div class='add'>+			MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO	0x82</div><div class='add'>+			MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9	0x40</div><div class='add'>+			MX8MN_IOMUXC_SD1_DATA1_GPIO2_IO3	0x140 /* CAN_IRQ# */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_spi2: spi2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0x82</div><div class='add'>+			MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0x82</div><div class='add'>+			MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO	0x82</div><div class='add'>+			MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13	0x40 /* SS0 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140</div><div class='add'>+			MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1_gpio: uart1gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SAI2_TXD0_GPIO4_IO26	0x40000110 /* HALF */</div><div class='add'>+			MX8MN_IOMUXC_SAI2_TXC_GPIO4_IO25	0x40000110 /* TERM */</div><div class='add'>+			MX8MN_IOMUXC_SAI2_RXD0_GPIO4_IO23	0x40000110 /* RS485 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140</div><div class='add'>+			MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3_gpio: uart3_gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12	0x41 /* BT_EN# */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: uart3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX	0x140</div><div class='add'>+			MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX	0x140</div><div class='add'>+			MX8MN_IOMUXC_SD1_CLK_GPIO2_IO0		0x140 /* CTS */</div><div class='add'>+			MX8MN_IOMUXC_SD1_CMD_GPIO2_IO1		0x140 /* RTS */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart4: uart4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX	0x140</div><div class='add'>+			MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX	0x140</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6	0x141 /* GNSS_GASP */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x190</div><div class='add'>+			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x194</div><div class='add'>+			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x196</div><div class='add'>+			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6</div><div class='add'>+			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK	0x190</div><div class='add'>+			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d0</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d0</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d0</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d0</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d0</div><div class='add'>+			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d0</div><div class='add'>+			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d0</div><div class='add'>+			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d0</div><div class='add'>+			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d0</div><div class='add'>+			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x190</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK	0x194</div><div class='add'>+			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d4</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4</div><div class='add'>+			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d4</div><div class='add'>+			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d4</div><div class='add'>+			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d4</div><div class='add'>+			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d4</div><div class='add'>+			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x194</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK	0x196</div><div class='add'>+			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d6</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d6</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d6</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d6</div><div class='add'>+			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d6</div><div class='add'>+			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d6</div><div class='add'>+			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d6</div><div class='add'>+			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d6</div><div class='add'>+			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d6</div><div class='add'>+			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x196</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi<br/>index fa78f0163270..b98b3d0ddf25 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mn.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mn.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mn.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mn.dtsi</a></div><div class='hunk'>@@ -4,6 +4,8 @@</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;dt-bindings/clock/imx8mn-clock.h&gt;</div><div class='add'>+#include &lt;dt-bindings/power/imx8mn-power.h&gt;</div><div class='add'>+#include &lt;dt-bindings/reset/imx8mq-reset.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/input/input.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='hunk'>@@ -60,9 +62,14 @@</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			reg = &lt;0x0&gt;;</div><div class='del'>-			clock-latency = &lt;61036&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;clk IMX8MN_CLK_ARM&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;A53_L2&gt;;</div><div class='ctx'> 			operating-points-v2 = &lt;&amp;a53_opp_table&gt;;</div><div class='ctx'> 			nvmem-cells = &lt;&amp;cpu_speed_grade&gt;;</div><div class='hunk'>@@ -75,9 +82,14 @@</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			reg = &lt;0x1&gt;;</div><div class='del'>-			clock-latency = &lt;61036&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;clk IMX8MN_CLK_ARM&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;A53_L2&gt;;</div><div class='ctx'> 			operating-points-v2 = &lt;&amp;a53_opp_table&gt;;</div><div class='ctx'> 			cpu-idle-states = &lt;&amp;cpu_pd_wait&gt;;</div><div class='hunk'>@@ -88,9 +100,14 @@</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			reg = &lt;0x2&gt;;</div><div class='del'>-			clock-latency = &lt;61036&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;clk IMX8MN_CLK_ARM&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;A53_L2&gt;;</div><div class='ctx'> 			operating-points-v2 = &lt;&amp;a53_opp_table&gt;;</div><div class='ctx'> 			cpu-idle-states = &lt;&amp;cpu_pd_wait&gt;;</div><div class='hunk'>@@ -101,9 +118,14 @@</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			reg = &lt;0x3&gt;;</div><div class='del'>-			clock-latency = &lt;61036&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;clk IMX8MN_CLK_ARM&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;A53_L2&gt;;</div><div class='ctx'> 			operating-points-v2 = &lt;&amp;a53_opp_table&gt;;</div><div class='ctx'> 			cpu-idle-states = &lt;&amp;cpu_pd_wait&gt;;</div><div class='hunk'>@@ -112,6 +134,11 @@</div><div class='ctx'> </div><div class='ctx'> 		A53_L2: l2-cache0 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x80000&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;512&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -121,7 +148,7 @@</div><div class='ctx'> </div><div class='ctx'> 		opp-1200000000 {</div><div class='ctx'> 			opp-hz = /bits/ 64 &lt;1200000000&gt;;</div><div class='del'>-			opp-microvolt = &lt;950000&gt;;</div><div class='add'>+			opp-microvolt = &lt;850000&gt;;</div><div class='ctx'> 			opp-supported-hw = &lt;0xb00&gt;, &lt;0x7&gt;;</div><div class='ctx'> 			clock-latency-ns = &lt;150000&gt;;</div><div class='ctx'> 			opp-suspend;</div><div class='hunk'>@@ -182,10 +209,16 @@</div><div class='ctx'> 	clk_ext4: clock-ext4 {</div><div class='ctx'> 		compatible = "fixed-clock";</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='del'>-		clock-frequency= &lt;133000000&gt;;</div><div class='add'>+		clock-frequency = &lt;133000000&gt;;</div><div class='ctx'> 		clock-output-names = "clk_ext4";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	pmu {</div><div class='add'>+		compatible = "arm,cortex-a53-pmu";</div><div class='add'>+		interrupts = &lt;GIC_PPI 7</div><div class='add'>+			     (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	psci {</div><div class='ctx'> 		compatible = "arm,psci-1.0";</div><div class='ctx'> 		method = "smc";</div><div class='hunk'>@@ -225,27 +258,179 @@</div><div class='ctx'> </div><div class='ctx'> 	timer {</div><div class='ctx'> 		compatible = "arm,armv8-timer";</div><div class='del'>-		interrupts = &lt;GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='del'>-			     &lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='del'>-			     &lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='del'>-			     &lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='ctx'> 		clock-frequency = &lt;8000000&gt;;</div><div class='ctx'> 		arm,no-tick-in-suspend;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	soc@0 {</div><div class='del'>-		compatible = "simple-bus";</div><div class='add'>+	soc: soc@0 {</div><div class='add'>+		compatible = "fsl,imx8mn-soc", "simple-bus";</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;1&gt;;</div><div class='ctx'> 		ranges = &lt;0x0 0x0 0x0 0x3e000000&gt;;</div><div class='add'>+		dma-ranges = &lt;0x40000000 0x0 0x40000000 0xc0000000&gt;;</div><div class='add'>+		nvmem-cells = &lt;&amp;imx8mn_uid&gt;;</div><div class='add'>+		nvmem-cell-names = "soc_unique_id";</div><div class='ctx'> </div><div class='ctx'> 		aips1: bus@30000000 {</div><div class='ctx'> 			compatible = "fsl,aips-bus", "simple-bus";</div><div class='del'>-			reg = &lt;0x301f0000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x30000000 0x400000&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;1&gt;;</div><div class='ctx'> 			ranges;</div><div class='ctx'> </div><div class='add'>+			spba2: spba-bus@30000000 {</div><div class='add'>+				compatible = "fsl,spba-bus", "simple-bus";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;1&gt;;</div><div class='add'>+				reg = &lt;0x30000000 0x100000&gt;;</div><div class='add'>+				ranges;</div><div class='add'>+</div><div class='add'>+				sai2: sai@30020000 {</div><div class='add'>+					compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";</div><div class='add'>+					reg = &lt;0x30020000 0x10000&gt;;</div><div class='add'>+					#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+					interrupts = &lt;GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					clocks = &lt;&amp;clk IMX8MN_CLK_SAI2_IPG&gt;,</div><div class='add'>+						&lt;&amp;clk IMX8MN_CLK_DUMMY&gt;,</div><div class='add'>+						&lt;&amp;clk IMX8MN_CLK_SAI2_ROOT&gt;,</div><div class='add'>+						&lt;&amp;clk IMX8MN_CLK_DUMMY&gt;, &lt;&amp;clk IMX8MN_CLK_DUMMY&gt;;</div><div class='add'>+					clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";</div><div class='add'>+					dmas = &lt;&amp;sdma2 2 2 0&gt;, &lt;&amp;sdma2 3 2 0&gt;;</div><div class='add'>+					dma-names = "rx", "tx";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				sai3: sai@30030000 {</div><div class='add'>+					compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";</div><div class='add'>+					reg = &lt;0x30030000 0x10000&gt;;</div><div class='add'>+					#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+					interrupts = &lt;GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					clocks = &lt;&amp;clk IMX8MN_CLK_SAI3_IPG&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MN_CLK_DUMMY&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MN_CLK_SAI3_ROOT&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MN_CLK_DUMMY&gt;, &lt;&amp;clk IMX8MN_CLK_DUMMY&gt;;</div><div class='add'>+					clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";</div><div class='add'>+					dmas = &lt;&amp;sdma2 4 2 0&gt;, &lt;&amp;sdma2 5 2 0&gt;;</div><div class='add'>+					dma-names = "rx", "tx";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				sai5: sai@30050000 {</div><div class='add'>+					compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";</div><div class='add'>+					reg = &lt;0x30050000 0x10000&gt;;</div><div class='add'>+					#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+					interrupts = &lt;GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					clocks = &lt;&amp;clk IMX8MN_CLK_SAI5_IPG&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MN_CLK_DUMMY&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MN_CLK_SAI5_ROOT&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MN_CLK_DUMMY&gt;, &lt;&amp;clk IMX8MN_CLK_DUMMY&gt;;</div><div class='add'>+					clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";</div><div class='add'>+					dmas = &lt;&amp;sdma2 8 2 0&gt;, &lt;&amp;sdma2 9 2 0&gt;;</div><div class='add'>+					dma-names = "rx", "tx";</div><div class='add'>+					fsl,shared-interrupt;</div><div class='add'>+					fsl,dataline = &lt;0 0xf 0xf&gt;;</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				sai6: sai@30060000 {</div><div class='add'>+					compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";</div><div class='add'>+					reg = &lt;0x30060000  0x10000&gt;;</div><div class='add'>+					#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+					interrupts = &lt;GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					clocks = &lt;&amp;clk IMX8MN_CLK_SAI6_IPG&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MN_CLK_DUMMY&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MN_CLK_SAI6_ROOT&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MN_CLK_DUMMY&gt;, &lt;&amp;clk IMX8MN_CLK_DUMMY&gt;;</div><div class='add'>+					clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";</div><div class='add'>+					dmas = &lt;&amp;sdma2 10 2 0&gt;, &lt;&amp;sdma2 11 2 0&gt;;</div><div class='add'>+					dma-names = "rx", "tx";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				micfil: audio-controller@30080000 {</div><div class='add'>+					compatible = "fsl,imx8mm-micfil";</div><div class='add'>+					reg = &lt;0x30080000 0x10000&gt;;</div><div class='add'>+					interrupts = &lt;GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+						     &lt;GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+						     &lt;GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+						     &lt;GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					clocks = &lt;&amp;clk IMX8MN_CLK_PDM_IPG&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MN_CLK_PDM_ROOT&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MN_AUDIO_PLL1_OUT&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MN_AUDIO_PLL2_OUT&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MN_CLK_EXT3&gt;;</div><div class='add'>+					clock-names = "ipg_clk", "ipg_clk_app",</div><div class='add'>+						      "pll8k", "pll11k", "clkext3";</div><div class='add'>+					dmas = &lt;&amp;sdma2 24 25 0x80000000&gt;;</div><div class='add'>+					dma-names = "rx";</div><div class='add'>+					#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				spdif1: spdif@30090000 {</div><div class='add'>+					compatible = "fsl,imx35-spdif";</div><div class='add'>+					reg = &lt;0x30090000 0x10000&gt;;</div><div class='add'>+					interrupts = &lt;GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					clocks = &lt;&amp;clk IMX8MN_CLK_AUDIO_AHB&gt;, /* core */</div><div class='add'>+						 &lt;&amp;clk IMX8MN_CLK_24M&gt;, /* rxtx0 */</div><div class='add'>+						 &lt;&amp;clk IMX8MN_CLK_SPDIF1&gt;, /* rxtx1 */</div><div class='add'>+						 &lt;&amp;clk IMX8MN_CLK_DUMMY&gt;, /* rxtx2 */</div><div class='add'>+						 &lt;&amp;clk IMX8MN_CLK_DUMMY&gt;, /* rxtx3 */</div><div class='add'>+						 &lt;&amp;clk IMX8MN_CLK_DUMMY&gt;, /* rxtx4 */</div><div class='add'>+						 &lt;&amp;clk IMX8MN_CLK_AUDIO_AHB&gt;, /* rxtx5 */</div><div class='add'>+						 &lt;&amp;clk IMX8MN_CLK_DUMMY&gt;, /* rxtx6 */</div><div class='add'>+						 &lt;&amp;clk IMX8MN_CLK_DUMMY&gt;, /* rxtx7 */</div><div class='add'>+						 &lt;&amp;clk IMX8MN_CLK_DUMMY&gt;; /* spba */</div><div class='add'>+					clock-names = "core", "rxtx0",</div><div class='add'>+						      "rxtx1", "rxtx2",</div><div class='add'>+						      "rxtx3", "rxtx4",</div><div class='add'>+						      "rxtx5", "rxtx6",</div><div class='add'>+						      "rxtx7", "spba";</div><div class='add'>+					dmas = &lt;&amp;sdma2 28 18 0&gt;, &lt;&amp;sdma2 29 18 0&gt;;</div><div class='add'>+					dma-names = "rx", "tx";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				sai7: sai@300b0000 {</div><div class='add'>+					compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";</div><div class='add'>+					reg = &lt;0x300b0000 0x10000&gt;;</div><div class='add'>+					#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+					interrupts = &lt;GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					clocks = &lt;&amp;clk IMX8MN_CLK_SAI7_IPG&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MN_CLK_DUMMY&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MN_CLK_SAI7_ROOT&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MN_CLK_DUMMY&gt;, &lt;&amp;clk IMX8MN_CLK_DUMMY&gt;;</div><div class='add'>+					clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";</div><div class='add'>+					dmas = &lt;&amp;sdma2 12 2 0&gt;, &lt;&amp;sdma2 13 2 0&gt;;</div><div class='add'>+					dma-names = "rx", "tx";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				easrc: easrc@300c0000 {</div><div class='add'>+					compatible = "fsl,imx8mn-easrc";</div><div class='add'>+					reg = &lt;0x300c0000 0x10000&gt;;</div><div class='add'>+					interrupts = &lt;GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					clocks = &lt;&amp;clk IMX8MN_CLK_ASRC_ROOT&gt;;</div><div class='add'>+					clock-names = "mem";</div><div class='add'>+					dmas = &lt;&amp;sdma2 16 23 0&gt; , &lt;&amp;sdma2 17 23 0&gt;,</div><div class='add'>+					       &lt;&amp;sdma2 18 23 0&gt; , &lt;&amp;sdma2 19 23 0&gt;,</div><div class='add'>+					       &lt;&amp;sdma2 20 23 0&gt; , &lt;&amp;sdma2 21 23 0&gt;,</div><div class='add'>+					       &lt;&amp;sdma2 22 23 0&gt; , &lt;&amp;sdma2 23 23 0&gt;;</div><div class='add'>+					dma-names = "ctx0_rx", "ctx0_tx",</div><div class='add'>+						    "ctx1_rx", "ctx1_tx",</div><div class='add'>+						    "ctx2_rx", "ctx2_tx",</div><div class='add'>+						    "ctx3_rx", "ctx3_tx";</div><div class='add'>+					firmware-name = "imx/easrc/easrc-imx8mn.bin";</div><div class='add'>+					fsl,asrc-rate = &lt;8000&gt;;</div><div class='add'>+					fsl,asrc-format = &lt;2&gt;;</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='ctx'> 			gpio1: gpio@30200000 {</div><div class='ctx'> 				compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";</div><div class='ctx'> 				reg = &lt;0x30200000 0x10000&gt;;</div><div class='hunk'>@@ -315,6 +500,8 @@</div><div class='ctx'> 				compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu";</div><div class='ctx'> 				reg = &lt;0x30260000 0x10000&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;clk IMX8MN_CLK_TMU_ROOT&gt;;</div><div class='add'>+				nvmem-cells = &lt;&amp;tmu_calib&gt;;</div><div class='add'>+				nvmem-cell-names = "calib";</div><div class='ctx'> 				#thermal-sensor-cells = &lt;0&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -369,27 +556,52 @@</div><div class='ctx'> 				reg = &lt;0x30330000 0x10000&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			gpr: iomuxc-gpr@30340000 {</div><div class='add'>+			gpr: syscon@30340000 {</div><div class='ctx'> 				compatible = "fsl,imx8mn-iomuxc-gpr", "syscon";</div><div class='ctx'> 				reg = &lt;0x30340000 0x10000&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			ocotp: ocotp-ctrl@30350000 {</div><div class='add'>+			ocotp: efuse@30350000 {</div><div class='ctx'> 				compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon";</div><div class='ctx'> 				reg = &lt;0x30350000 0x10000&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;clk IMX8MN_CLK_OCOTP_ROOT&gt;;</div><div class='ctx'> 				#address-cells = &lt;1&gt;;</div><div class='ctx'> 				#size-cells = &lt;1&gt;;</div><div class='ctx'> </div><div class='del'>-				cpu_speed_grade: speed-grade@10 {</div><div class='add'>+				/*</div><div class='add'>+				 * The register address below maps to the MX8M</div><div class='add'>+				 * Fusemap Description Table entries this way.</div><div class='add'>+				 * Assuming</div><div class='add'>+				 *   reg = &lt;ADDR SIZE&gt;;</div><div class='add'>+				 * then</div><div class='add'>+				 *   Fuse Address = (ADDR * 4) + 0x400</div><div class='add'>+				 * Note that if SIZE is greater than 4, then</div><div class='add'>+				 * each subsequent fuse is located at offset</div><div class='add'>+				 * +0x10 in Fusemap Description Table (e.g.</div><div class='add'>+				 * reg = &lt;0x4 0x8&gt; describes fuses 0x410 and</div><div class='add'>+				 * 0x420).</div><div class='add'>+				 */</div><div class='add'>+				imx8mn_uid: unique-id@4 { /* 0x410-0x420 */</div><div class='add'>+					reg = &lt;0x4 0x8&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_speed_grade: speed-grade@10 { /* 0x440 */</div><div class='ctx'> 					reg = &lt;0x10 4&gt;;</div><div class='ctx'> 				};</div><div class='add'>+</div><div class='add'>+				tmu_calib: calib@3c { /* 0x4f0 */</div><div class='add'>+					reg = &lt;0x3c 4&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				fec_mac_address: mac-address@90 { /* 0x640 */</div><div class='add'>+					reg = &lt;0x90 6&gt;;</div><div class='add'>+				};</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			anatop: anatop@30360000 {</div><div class='del'>-				compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop",</div><div class='del'>-					     "syscon";</div><div class='add'>+			anatop: clock-controller@30360000 {</div><div class='add'>+				compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop";</div><div class='ctx'> 				reg = &lt;0x30360000 0x10000&gt;;</div><div class='add'>+				#clock-cells = &lt;1&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			snvs: snvs@30370000 {</div><div class='hunk'>@@ -421,21 +633,31 @@</div><div class='ctx'> 			clk: clock-controller@30380000 {</div><div class='ctx'> 				compatible = "fsl,imx8mn-ccm";</div><div class='ctx'> 				reg = &lt;0x30380000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				#clock-cells = &lt;1&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;osc_32k&gt;, &lt;&amp;osc_24m&gt;, &lt;&amp;clk_ext1&gt;, &lt;&amp;clk_ext2&gt;,</div><div class='ctx'> 					 &lt;&amp;clk_ext3&gt;, &lt;&amp;clk_ext4&gt;;</div><div class='ctx'> 				clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",</div><div class='ctx'> 					      "clk_ext3", "clk_ext4";</div><div class='del'>-				assigned-clocks = &lt;&amp;clk IMX8MN_CLK_NOC&gt;,</div><div class='add'>+				assigned-clocks = &lt;&amp;clk IMX8MN_CLK_A53_SRC&gt;,</div><div class='add'>+						&lt;&amp;clk IMX8MN_CLK_A53_CORE&gt;,</div><div class='add'>+						&lt;&amp;clk IMX8MN_CLK_NOC&gt;,</div><div class='ctx'> 						&lt;&amp;clk IMX8MN_CLK_AUDIO_AHB&gt;,</div><div class='ctx'> 						&lt;&amp;clk IMX8MN_CLK_IPG_AUDIO_ROOT&gt;,</div><div class='del'>-						&lt;&amp;clk IMX8MN_SYS_PLL3&gt;;</div><div class='del'>-				assigned-clock-parents = &lt;&amp;clk IMX8MN_SYS_PLL3_OUT&gt;,</div><div class='add'>+						&lt;&amp;clk IMX8MN_SYS_PLL3&gt;,</div><div class='add'>+						&lt;&amp;clk IMX8MN_AUDIO_PLL1&gt;,</div><div class='add'>+						&lt;&amp;clk IMX8MN_AUDIO_PLL2&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;clk IMX8MN_SYS_PLL1_800M&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MN_ARM_PLL_OUT&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MN_SYS_PLL3_OUT&gt;,</div><div class='ctx'> 							 &lt;&amp;clk IMX8MN_SYS_PLL1_800M&gt;;</div><div class='del'>-				assigned-clock-rates = &lt;0&gt;,</div><div class='add'>+				assigned-clock-rates = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;,</div><div class='ctx'> 							&lt;400000000&gt;,</div><div class='ctx'> 							&lt;400000000&gt;,</div><div class='del'>-							&lt;600000000&gt;;</div><div class='add'>+							&lt;600000000&gt;,</div><div class='add'>+							&lt;393216000&gt;,</div><div class='add'>+							&lt;361267200&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			src: reset-controller@30390000 {</div><div class='hunk'>@@ -444,11 +666,56 @@</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				#reset-cells = &lt;1&gt;;</div><div class='ctx'> 			};</div><div class='add'>+</div><div class='add'>+			gpc: gpc@303a0000 {</div><div class='add'>+				compatible = "fsl,imx8mn-gpc";</div><div class='add'>+				reg = &lt;0x303a0000 0x10000&gt;;</div><div class='add'>+				interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				pgc {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					pgc_hsiomix: power-domain@0 {</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						reg = &lt;IMX8MN_POWER_DOMAIN_HSIOMIX&gt;;</div><div class='add'>+						clocks = &lt;&amp;clk IMX8MN_CLK_USB_BUS&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					pgc_otg1: power-domain@1 {</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						reg = &lt;IMX8MN_POWER_DOMAIN_OTG1&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					pgc_gpumix: power-domain@2 {</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						reg = &lt;IMX8MN_POWER_DOMAIN_GPUMIX&gt;;</div><div class='add'>+						clocks = &lt;&amp;clk IMX8MN_CLK_GPU_CORE_ROOT&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MN_CLK_GPU_SHADER&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MN_CLK_GPU_BUS_ROOT&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MN_CLK_GPU_AHB&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					pgc_dispmix: power-domain@3 {</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						reg = &lt;IMX8MN_POWER_DOMAIN_DISPMIX&gt;;</div><div class='add'>+						clocks = &lt;&amp;clk IMX8MN_CLK_DISP_AXI_ROOT&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MN_CLK_DISP_APB_ROOT&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					pgc_mipi: power-domain@4 {</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						reg = &lt;IMX8MN_POWER_DOMAIN_MIPI&gt;;</div><div class='add'>+						power-domains = &lt;&amp;pgc_dispmix&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		aips2: bus@30400000 {</div><div class='ctx'> 			compatible = "fsl,aips-bus", "simple-bus";</div><div class='del'>-			reg = &lt;0x305f0000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x30400000 0x400000&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;1&gt;;</div><div class='ctx'> 			ranges;</div><div class='hunk'>@@ -460,7 +727,7 @@</div><div class='ctx'> 				clocks = &lt;&amp;clk IMX8MN_CLK_PWM1_ROOT&gt;,</div><div class='ctx'> 					&lt;&amp;clk IMX8MN_CLK_PWM1_ROOT&gt;;</div><div class='ctx'> 				clock-names = "ipg", "per";</div><div class='del'>-				#pwm-cells = &lt;2&gt;;</div><div class='add'>+				#pwm-cells = &lt;3&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -471,7 +738,7 @@</div><div class='ctx'> 				clocks = &lt;&amp;clk IMX8MN_CLK_PWM2_ROOT&gt;,</div><div class='ctx'> 					 &lt;&amp;clk IMX8MN_CLK_PWM2_ROOT&gt;;</div><div class='ctx'> 				clock-names = "ipg", "per";</div><div class='del'>-				#pwm-cells = &lt;2&gt;;</div><div class='add'>+				#pwm-cells = &lt;3&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -482,7 +749,7 @@</div><div class='ctx'> 				clocks = &lt;&amp;clk IMX8MN_CLK_PWM3_ROOT&gt;,</div><div class='ctx'> 					 &lt;&amp;clk IMX8MN_CLK_PWM3_ROOT&gt;;</div><div class='ctx'> 				clock-names = "ipg", "per";</div><div class='del'>-				#pwm-cells = &lt;2&gt;;</div><div class='add'>+				#pwm-cells = &lt;3&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -493,7 +760,7 @@</div><div class='ctx'> 				clocks = &lt;&amp;clk IMX8MN_CLK_PWM4_ROOT&gt;,</div><div class='ctx'> 					 &lt;&amp;clk IMX8MN_CLK_PWM4_ROOT&gt;;</div><div class='ctx'> 				clock-names = "ipg", "per";</div><div class='del'>-				#pwm-cells = &lt;2&gt;;</div><div class='add'>+				#pwm-cells = &lt;3&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -508,85 +775,95 @@</div><div class='ctx'> </div><div class='ctx'> 		aips3: bus@30800000 {</div><div class='ctx'> 			compatible = "fsl,aips-bus", "simple-bus";</div><div class='del'>-			reg = &lt;0x309f0000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x30800000 0x400000&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;1&gt;;</div><div class='ctx'> 			ranges;</div><div class='ctx'> </div><div class='del'>-			ecspi1: spi@30820000 {</div><div class='del'>-				compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";</div><div class='add'>+			spba1: spba-bus@30800000 {</div><div class='add'>+				compatible = "fsl,spba-bus", "simple-bus";</div><div class='ctx'> 				#address-cells = &lt;1&gt;;</div><div class='del'>-				#size-cells = &lt;0&gt;;</div><div class='del'>-				reg = &lt;0x30820000 0x10000&gt;;</div><div class='del'>-				interrupts = &lt;GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-				clocks = &lt;&amp;clk IMX8MN_CLK_ECSPI1_ROOT&gt;,</div><div class='del'>-					 &lt;&amp;clk IMX8MN_CLK_ECSPI1_ROOT&gt;;</div><div class='del'>-				clock-names = "ipg", "per";</div><div class='del'>-				dmas = &lt;&amp;sdma1 0 7 1&gt;, &lt;&amp;sdma1 1 7 2&gt;;</div><div class='del'>-				dma-names = "rx", "tx";</div><div class='del'>-				status = "disabled";</div><div class='del'>-			};</div><div class='add'>+				#size-cells = &lt;1&gt;;</div><div class='add'>+				reg = &lt;0x30800000 0x100000&gt;;</div><div class='add'>+				ranges;</div><div class='add'>+</div><div class='add'>+				ecspi1: spi@30820000 {</div><div class='add'>+					compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+					reg = &lt;0x30820000 0x10000&gt;;</div><div class='add'>+					interrupts = &lt;GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					clocks = &lt;&amp;clk IMX8MN_CLK_ECSPI1_ROOT&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MN_CLK_ECSPI1_ROOT&gt;;</div><div class='add'>+					clock-names = "ipg", "per";</div><div class='add'>+					dmas = &lt;&amp;sdma1 0 7 1&gt;, &lt;&amp;sdma1 1 7 2&gt;;</div><div class='add'>+					dma-names = "rx", "tx";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-			ecspi2: spi@30830000 {</div><div class='del'>-				compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";</div><div class='del'>-				#address-cells = &lt;1&gt;;</div><div class='del'>-				#size-cells = &lt;0&gt;;</div><div class='del'>-				reg = &lt;0x30830000 0x10000&gt;;</div><div class='del'>-				interrupts = &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-				clocks = &lt;&amp;clk IMX8MN_CLK_ECSPI2_ROOT&gt;,</div><div class='del'>-					 &lt;&amp;clk IMX8MN_CLK_ECSPI2_ROOT&gt;;</div><div class='del'>-				clock-names = "ipg", "per";</div><div class='del'>-				dmas = &lt;&amp;sdma1 2 7 1&gt;, &lt;&amp;sdma1 3 7 2&gt;;</div><div class='del'>-				dma-names = "rx", "tx";</div><div class='del'>-				status = "disabled";</div><div class='del'>-			};</div><div class='add'>+				ecspi2: spi@30830000 {</div><div class='add'>+					compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+					reg = &lt;0x30830000 0x10000&gt;;</div><div class='add'>+					interrupts = &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					clocks = &lt;&amp;clk IMX8MN_CLK_ECSPI2_ROOT&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MN_CLK_ECSPI2_ROOT&gt;;</div><div class='add'>+					clock-names = "ipg", "per";</div><div class='add'>+					dmas = &lt;&amp;sdma1 2 7 1&gt;, &lt;&amp;sdma1 3 7 2&gt;;</div><div class='add'>+					dma-names = "rx", "tx";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-			ecspi3: spi@30840000 {</div><div class='del'>-				compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";</div><div class='del'>-				#address-cells = &lt;1&gt;;</div><div class='del'>-				#size-cells = &lt;0&gt;;</div><div class='del'>-				reg = &lt;0x30840000 0x10000&gt;;</div><div class='del'>-				interrupts = &lt;GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-				clocks = &lt;&amp;clk IMX8MN_CLK_ECSPI3_ROOT&gt;,</div><div class='del'>-					 &lt;&amp;clk IMX8MN_CLK_ECSPI3_ROOT&gt;;</div><div class='del'>-				clock-names = "ipg", "per";</div><div class='del'>-				dmas = &lt;&amp;sdma1 4 7 1&gt;, &lt;&amp;sdma1 5 7 2&gt;;</div><div class='del'>-				dma-names = "rx", "tx";</div><div class='del'>-				status = "disabled";</div><div class='del'>-			};</div><div class='add'>+				ecspi3: spi@30840000 {</div><div class='add'>+					compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+					reg = &lt;0x30840000 0x10000&gt;;</div><div class='add'>+					interrupts = &lt;GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					clocks = &lt;&amp;clk IMX8MN_CLK_ECSPI3_ROOT&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MN_CLK_ECSPI3_ROOT&gt;;</div><div class='add'>+					clock-names = "ipg", "per";</div><div class='add'>+					dmas = &lt;&amp;sdma1 4 7 1&gt;, &lt;&amp;sdma1 5 7 2&gt;;</div><div class='add'>+					dma-names = "rx", "tx";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-			uart1: serial@30860000 {</div><div class='del'>-				compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";</div><div class='del'>-				reg = &lt;0x30860000 0x10000&gt;;</div><div class='del'>-				interrupts = &lt;GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-				clocks = &lt;&amp;clk IMX8MN_CLK_UART1_ROOT&gt;,</div><div class='del'>-					 &lt;&amp;clk IMX8MN_CLK_UART1_ROOT&gt;;</div><div class='del'>-				clock-names = "ipg", "per";</div><div class='del'>-				dmas = &lt;&amp;sdma1 22 4 0&gt;, &lt;&amp;sdma1 23 4 0&gt;;</div><div class='del'>-				dma-names = "rx", "tx";</div><div class='del'>-				status = "disabled";</div><div class='del'>-			};</div><div class='add'>+				uart1: serial@30860000 {</div><div class='add'>+					compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";</div><div class='add'>+					reg = &lt;0x30860000 0x10000&gt;;</div><div class='add'>+					interrupts = &lt;GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					clocks = &lt;&amp;clk IMX8MN_CLK_UART1_ROOT&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MN_CLK_UART1_ROOT&gt;;</div><div class='add'>+					clock-names = "ipg", "per";</div><div class='add'>+					dmas = &lt;&amp;sdma1 22 4 0&gt;, &lt;&amp;sdma1 23 4 0&gt;;</div><div class='add'>+					dma-names = "rx", "tx";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-			uart3: serial@30880000 {</div><div class='del'>-				compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";</div><div class='del'>-				reg = &lt;0x30880000 0x10000&gt;;</div><div class='del'>-				interrupts = &lt;GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-				clocks = &lt;&amp;clk IMX8MN_CLK_UART3_ROOT&gt;,</div><div class='del'>-					 &lt;&amp;clk IMX8MN_CLK_UART3_ROOT&gt;;</div><div class='del'>-				clock-names = "ipg", "per";</div><div class='del'>-				dmas = &lt;&amp;sdma1 26 4 0&gt;, &lt;&amp;sdma1 27 4 0&gt;;</div><div class='del'>-				dma-names = "rx", "tx";</div><div class='del'>-				status = "disabled";</div><div class='del'>-			};</div><div class='add'>+				uart3: serial@30880000 {</div><div class='add'>+					compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";</div><div class='add'>+					reg = &lt;0x30880000 0x10000&gt;;</div><div class='add'>+					interrupts = &lt;GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					clocks = &lt;&amp;clk IMX8MN_CLK_UART3_ROOT&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MN_CLK_UART3_ROOT&gt;;</div><div class='add'>+					clock-names = "ipg", "per";</div><div class='add'>+					dmas = &lt;&amp;sdma1 26 4 0&gt;, &lt;&amp;sdma1 27 4 0&gt;;</div><div class='add'>+					dma-names = "rx", "tx";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-			uart2: serial@30890000 {</div><div class='del'>-				compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";</div><div class='del'>-				reg = &lt;0x30890000 0x10000&gt;;</div><div class='del'>-				interrupts = &lt;GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-				clocks = &lt;&amp;clk IMX8MN_CLK_UART2_ROOT&gt;,</div><div class='del'>-					 &lt;&amp;clk IMX8MN_CLK_UART2_ROOT&gt;;</div><div class='del'>-				clock-names = "ipg", "per";</div><div class='del'>-				status = "disabled";</div><div class='add'>+				uart2: serial@30890000 {</div><div class='add'>+					compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";</div><div class='add'>+					reg = &lt;0x30890000 0x10000&gt;;</div><div class='add'>+					interrupts = &lt;GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					clocks = &lt;&amp;clk IMX8MN_CLK_UART2_ROOT&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MN_CLK_UART2_ROOT&gt;;</div><div class='add'>+					clock-names = "ipg", "per";</div><div class='add'>+					dmas = &lt;&amp;sdma1 24 4 0&gt;, &lt;&amp;sdma1 25 4 0&gt;;</div><div class='add'>+					dma-names = "rx", "tx";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			crypto: crypto@30900000 {</div><div class='hunk'>@@ -604,6 +881,7 @@</div><div class='ctx'> 					 compatible = "fsl,sec-v4.0-job-ring";</div><div class='ctx'> 					 reg = &lt;0x1000 0x1000&gt;;</div><div class='ctx'> 					 interrupts = &lt;GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					 status = "disabled";</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='ctx'> 				sec_jr1: jr@2000 {</div><div class='hunk'>@@ -671,8 +949,16 @@</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='add'>+			mu: mailbox@30aa0000 {</div><div class='add'>+				compatible = "fsl,imx8mn-mu", "fsl,imx6sx-mu";</div><div class='add'>+				reg = &lt;0x30aa0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MN_CLK_MU_ROOT&gt;;</div><div class='add'>+				#mbox-cells = &lt;2&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='ctx'> 			usdhc1: mmc@30b40000 {</div><div class='del'>-				compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";</div><div class='add'>+				compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";</div><div class='ctx'> 				reg = &lt;0x30b40000 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;clk IMX8MN_CLK_IPG_ROOT&gt;,</div><div class='hunk'>@@ -680,13 +966,13 @@</div><div class='ctx'> 					 &lt;&amp;clk IMX8MN_CLK_USDHC1_ROOT&gt;;</div><div class='ctx'> 				clock-names = "ipg", "ahb", "per";</div><div class='ctx'> 				fsl,tuning-start-tap = &lt;20&gt;;</div><div class='del'>-				fsl,tuning-step= &lt;2&gt;;</div><div class='add'>+				fsl,tuning-step = &lt;2&gt;;</div><div class='ctx'> 				bus-width = &lt;4&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			usdhc2: mmc@30b50000 {</div><div class='del'>-				compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";</div><div class='add'>+				compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";</div><div class='ctx'> 				reg = &lt;0x30b50000 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;clk IMX8MN_CLK_IPG_ROOT&gt;,</div><div class='hunk'>@@ -694,13 +980,13 @@</div><div class='ctx'> 					 &lt;&amp;clk IMX8MN_CLK_USDHC2_ROOT&gt;;</div><div class='ctx'> 				clock-names = "ipg", "ahb", "per";</div><div class='ctx'> 				fsl,tuning-start-tap = &lt;20&gt;;</div><div class='del'>-				fsl,tuning-step= &lt;2&gt;;</div><div class='add'>+				fsl,tuning-step = &lt;2&gt;;</div><div class='ctx'> 				bus-width = &lt;4&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			usdhc3: mmc@30b60000 {</div><div class='del'>-				compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";</div><div class='add'>+				compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";</div><div class='ctx'> 				reg = &lt;0x30b60000 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;clk IMX8MN_CLK_IPG_ROOT&gt;,</div><div class='hunk'>@@ -708,28 +994,42 @@</div><div class='ctx'> 					 &lt;&amp;clk IMX8MN_CLK_USDHC3_ROOT&gt;;</div><div class='ctx'> 				clock-names = "ipg", "ahb", "per";</div><div class='ctx'> 				fsl,tuning-start-tap = &lt;20&gt;;</div><div class='del'>-				fsl,tuning-step= &lt;2&gt;;</div><div class='add'>+				fsl,tuning-step = &lt;2&gt;;</div><div class='ctx'> 				bus-width = &lt;4&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='add'>+			flexspi: spi@30bb0000 {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				compatible = "nxp,imx8mm-fspi";</div><div class='add'>+				reg = &lt;0x30bb0000 0x10000&gt;, &lt;0x8000000 0x10000000&gt;;</div><div class='add'>+				reg-names = "fspi_base", "fspi_mmap";</div><div class='add'>+				interrupts = &lt;GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MN_CLK_QSPI_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MN_CLK_QSPI_ROOT&gt;;</div><div class='add'>+				clock-names = "fspi_en", "fspi";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='ctx'> 			sdma1: dma-controller@30bd0000 {</div><div class='ctx'> 				compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";</div><div class='ctx'> 				reg = &lt;0x30bd0000 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;clk IMX8MN_CLK_SDMA1_ROOT&gt;,</div><div class='del'>-					 &lt;&amp;clk IMX8MN_CLK_SDMA1_ROOT&gt;;</div><div class='add'>+					 &lt;&amp;clk IMX8MN_CLK_AHB&gt;;</div><div class='ctx'> 				clock-names = "ipg", "ahb";</div><div class='ctx'> 				#dma-cells = &lt;3&gt;;</div><div class='ctx'> 				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			fec1: ethernet@30be0000 {</div><div class='del'>-				compatible = "fsl,imx8mn-fec", "fsl,imx6sx-fec";</div><div class='add'>+				compatible = "fsl,imx8mn-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";</div><div class='ctx'> 				reg = &lt;0x30be0000 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 					     &lt;GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-					     &lt;GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					     &lt;GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;clk IMX8MN_CLK_ENET1_ROOT&gt;,</div><div class='ctx'> 					 &lt;&amp;clk IMX8MN_CLK_ENET1_ROOT&gt;,</div><div class='ctx'> 					 &lt;&amp;clk IMX8MN_CLK_ENET_TIMER&gt;,</div><div class='hunk'>@@ -740,13 +1040,17 @@</div><div class='ctx'> 				assigned-clocks = &lt;&amp;clk IMX8MN_CLK_ENET_AXI&gt;,</div><div class='ctx'> 						  &lt;&amp;clk IMX8MN_CLK_ENET_TIMER&gt;,</div><div class='ctx'> 						  &lt;&amp;clk IMX8MN_CLK_ENET_REF&gt;,</div><div class='del'>-						  &lt;&amp;clk IMX8MN_CLK_ENET_TIMER&gt;;</div><div class='add'>+						  &lt;&amp;clk IMX8MN_CLK_ENET_PHY_REF&gt;;</div><div class='ctx'> 				assigned-clock-parents = &lt;&amp;clk IMX8MN_SYS_PLL1_266M&gt;,</div><div class='ctx'> 							 &lt;&amp;clk IMX8MN_SYS_PLL2_100M&gt;,</div><div class='del'>-							 &lt;&amp;clk IMX8MN_SYS_PLL2_125M&gt;;</div><div class='del'>-				assigned-clock-rates = &lt;0&gt;, &lt;0&gt;, &lt;125000000&gt;, &lt;100000000&gt;;</div><div class='add'>+							 &lt;&amp;clk IMX8MN_SYS_PLL2_125M&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MN_SYS_PLL2_50M&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;0&gt;, &lt;100000000&gt;, &lt;125000000&gt;, &lt;0&gt;;</div><div class='ctx'> 				fsl,num-tx-queues = &lt;3&gt;;</div><div class='ctx'> 				fsl,num-rx-queues = &lt;3&gt;;</div><div class='add'>+				nvmem-cells = &lt;&amp;fec_mac_address&gt;;</div><div class='add'>+				nvmem-cell-names = "mac-address";</div><div class='add'>+				fsl,stop-mode = &lt;&amp;gpr 0x10 3&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -754,51 +1058,180 @@</div><div class='ctx'> </div><div class='ctx'> 		aips4: bus@32c00000 {</div><div class='ctx'> 			compatible = "fsl,aips-bus", "simple-bus";</div><div class='del'>-			reg = &lt;0x32df0000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x32c00000 0x400000&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;1&gt;;</div><div class='ctx'> 			ranges;</div><div class='ctx'> </div><div class='add'>+			lcdif: lcdif@32e00000 {</div><div class='add'>+				compatible = "fsl,imx8mn-lcdif", "fsl,imx6sx-lcdif";</div><div class='add'>+				reg = &lt;0x32e00000 0x10000&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MN_CLK_DISP_PIXEL_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MN_CLK_DISP_APB_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MN_CLK_DISP_AXI_ROOT&gt;;</div><div class='add'>+				clock-names = "pix", "axi", "disp_axi";</div><div class='add'>+				interrupts = &lt;GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				power-domains = &lt;&amp;disp_blk_ctrl IMX8MN_DISPBLK_PD_LCDIF&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				port {</div><div class='add'>+					lcdif_to_dsim: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dsim_from_lcdif&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mipi_dsi: dsi@32e10000 {</div><div class='add'>+				compatible = "fsl,imx8mn-mipi-dsim", "fsl,imx8mm-mipi-dsim";</div><div class='add'>+				reg = &lt;0x32e10000 0x400&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MN_CLK_DSI_CORE&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MN_CLK_DSI_PHY_REF&gt;;</div><div class='add'>+				clock-names = "bus_clk", "sclk_mipi";</div><div class='add'>+				interrupts = &lt;GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				power-domains = &lt;&amp;disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_DSI&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						dsim_from_lcdif: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;lcdif_to_dsim&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						mipi_dsi_out: endpoint {</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			isi: isi@32e20000 {</div><div class='add'>+				compatible = "fsl,imx8mn-isi";</div><div class='add'>+				reg = &lt;0x32e20000 0x8000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MN_CLK_DISP_AXI_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MN_CLK_DISP_APB_ROOT&gt;;</div><div class='add'>+				clock-names = "axi", "apb";</div><div class='add'>+				fsl,blk-ctrl = &lt;&amp;disp_blk_ctrl&gt;;</div><div class='add'>+				power-domains = &lt;&amp;disp_blk_ctrl IMX8MN_DISPBLK_PD_ISI&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+						isi_in: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mipi_csi_out&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			disp_blk_ctrl: blk-ctrl@32e28000 {</div><div class='add'>+				compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon";</div><div class='add'>+				reg = &lt;0x32e28000 0x100&gt;;</div><div class='add'>+				power-domains = &lt;&amp;pgc_dispmix&gt;, &lt;&amp;pgc_dispmix&gt;,</div><div class='add'>+						&lt;&amp;pgc_dispmix&gt;, &lt;&amp;pgc_mipi&gt;,</div><div class='add'>+						&lt;&amp;pgc_mipi&gt;;</div><div class='add'>+				power-domain-names = "bus", "isi",</div><div class='add'>+						     "lcdif", "mipi-dsi",</div><div class='add'>+						     "mipi-csi";</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MN_CLK_DISP_AXI&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MN_CLK_DISP_APB&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MN_CLK_DISP_AXI_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MN_CLK_DISP_APB_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MN_CLK_DISP_AXI_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MN_CLK_DISP_APB_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MN_CLK_DISP_PIXEL_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MN_CLK_DSI_CORE&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MN_CLK_DSI_PHY_REF&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MN_CLK_CSI1_PHY_REF&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MN_CLK_CAMERA_PIXEL_ROOT&gt;;</div><div class='add'>+				clock-names = "disp_axi", "disp_apb",</div><div class='add'>+					      "disp_axi_root", "disp_apb_root",</div><div class='add'>+					      "lcdif-axi", "lcdif-apb", "lcdif-pix",</div><div class='add'>+					      "dsi-pclk", "dsi-ref",</div><div class='add'>+					      "csi-aclk", "csi-pclk";</div><div class='add'>+				assigned-clocks = &lt;&amp;clk IMX8MN_CLK_DSI_CORE&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX8MN_CLK_DSI_PHY_REF&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX8MN_CLK_DISP_PIXEL&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX8MN_CLK_DISP_AXI&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX8MN_CLK_DISP_APB&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;clk IMX8MN_SYS_PLL1_266M&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MN_CLK_24M&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MN_VIDEO_PLL1_OUT&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MN_SYS_PLL2_1000M&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MN_SYS_PLL1_800M&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;266000000&gt;,</div><div class='add'>+						       &lt;24000000&gt;,</div><div class='add'>+						       &lt;24000000&gt;,</div><div class='add'>+						       &lt;500000000&gt;,</div><div class='add'>+						       &lt;200000000&gt;;</div><div class='add'>+				#power-domain-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mipi_csi: mipi-csi@32e30000 {</div><div class='add'>+				compatible = "fsl,imx8mm-mipi-csi2";</div><div class='add'>+				reg = &lt;0x32e30000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				assigned-clocks = &lt;&amp;clk IMX8MN_CLK_CAMERA_PIXEL&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;clk IMX8MN_SYS_PLL2_1000M&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;333000000&gt;;</div><div class='add'>+				clock-frequency = &lt;333000000&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MN_CLK_DISP_APB_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MN_CLK_CAMERA_PIXEL&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MN_CLK_CSI1_PHY_REF&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MN_CLK_DISP_AXI_ROOT&gt;;</div><div class='add'>+				clock-names = "pclk", "wrap", "phy", "axi";</div><div class='add'>+				power-domains = &lt;&amp;disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_CSI&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						mipi_csi_out: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;isi_in&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='ctx'> 			usbotg1: usb@32e40000 {</div><div class='del'>-				compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";</div><div class='add'>+				compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb", "fsl,imx27-usb";</div><div class='ctx'> 				reg = &lt;0x32e40000 0x200&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;clk IMX8MN_CLK_USB1_CTRL_ROOT&gt;;</div><div class='del'>-				clock-names = "usb1_ctrl_root_clk";</div><div class='ctx'> 				assigned-clocks = &lt;&amp;clk IMX8MN_CLK_USB_BUS&gt;;</div><div class='ctx'> 				assigned-clock-parents = &lt;&amp;clk IMX8MN_SYS_PLL2_500M&gt;;</div><div class='del'>-				fsl,usbphy = &lt;&amp;usbphynop1&gt;;</div><div class='add'>+				phys = &lt;&amp;usbphynop1&gt;;</div><div class='ctx'> 				fsl,usbmisc = &lt;&amp;usbmisc1 0&gt;;</div><div class='add'>+				power-domains = &lt;&amp;pgc_hsiomix&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			usbmisc1: usbmisc@32e40200 {</div><div class='del'>-				compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";</div><div class='add'>+				compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc",</div><div class='add'>+					     "fsl,imx6q-usbmisc";</div><div class='ctx'> 				#index-cells = &lt;1&gt;;</div><div class='ctx'> 				reg = &lt;0x32e40200 0x200&gt;;</div><div class='ctx'> 			};</div><div class='del'>-</div><div class='del'>-			usbotg2: usb@32e50000 {</div><div class='del'>-				compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";</div><div class='del'>-				reg = &lt;0x32e50000 0x200&gt;;</div><div class='del'>-				interrupts = &lt;GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-				clocks = &lt;&amp;clk IMX8MN_CLK_USB1_CTRL_ROOT&gt;;</div><div class='del'>-				clock-names = "usb1_ctrl_root_clk";</div><div class='del'>-				assigned-clocks = &lt;&amp;clk IMX8MN_CLK_USB_BUS&gt;,</div><div class='del'>-						  &lt;&amp;clk IMX8MN_CLK_USB_CORE_REF&gt;;</div><div class='del'>-				assigned-clock-parents = &lt;&amp;clk IMX8MN_SYS_PLL2_500M&gt;,</div><div class='del'>-							 &lt;&amp;clk IMX8MN_SYS_PLL1_100M&gt;;</div><div class='del'>-				fsl,usbphy = &lt;&amp;usbphynop2&gt;;</div><div class='del'>-				fsl,usbmisc = &lt;&amp;usbmisc2 0&gt;;</div><div class='del'>-				status = "disabled";</div><div class='del'>-			};</div><div class='del'>-</div><div class='del'>-			usbmisc2: usbmisc@32e50200 {</div><div class='del'>-				compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";</div><div class='del'>-				#index-cells = &lt;1&gt;;</div><div class='del'>-				reg = &lt;0x32e50200 0x200&gt;;</div><div class='del'>-			};</div><div class='del'>-</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		dma_apbh: dma-controller@33000000 {</div><div class='hunk'>@@ -808,7 +1241,6 @@</div><div class='ctx'> 				     &lt;GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 				     &lt;GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 				     &lt;GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";</div><div class='ctx'> 			#dma-cells = &lt;1&gt;;</div><div class='ctx'> 			dma-channels = &lt;4&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK&gt;;</div><div class='hunk'>@@ -817,7 +1249,7 @@</div><div class='ctx'> 		gpmi: nand-controller@33002000 {</div><div class='ctx'> 			compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand";</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='del'>-			#size-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			reg = &lt;0x33002000 0x2000&gt;, &lt;0x33004000 0x4000&gt;;</div><div class='ctx'> 			reg-names = "gpmi-nand", "bch";</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='hunk'>@@ -830,6 +1262,32 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		gpu: gpu@38000000 {</div><div class='add'>+			compatible = "vivante,gc";</div><div class='add'>+			reg = &lt;0x38000000 0x8000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MN_CLK_GPU_AHB&gt;,</div><div class='add'>+				&lt;&amp;clk IMX8MN_CLK_GPU_BUS_ROOT&gt;,</div><div class='add'>+				&lt;&amp;clk IMX8MN_CLK_GPU_CORE_ROOT&gt;,</div><div class='add'>+				&lt;&amp;clk IMX8MN_CLK_GPU_SHADER&gt;;</div><div class='add'>+			clock-names = "reg", "bus", "core", "shader";</div><div class='add'>+			assigned-clocks = &lt;&amp;clk IMX8MN_CLK_GPU_CORE&gt;,</div><div class='add'>+					  &lt;&amp;clk IMX8MN_CLK_GPU_SHADER&gt;,</div><div class='add'>+					  &lt;&amp;clk IMX8MN_CLK_GPU_AXI&gt;,</div><div class='add'>+					  &lt;&amp;clk IMX8MN_CLK_GPU_AHB&gt;,</div><div class='add'>+					  &lt;&amp;clk IMX8MN_GPU_PLL&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;clk IMX8MN_GPU_PLL_OUT&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX8MN_GPU_PLL_OUT&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX8MN_SYS_PLL1_800M&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX8MN_SYS_PLL1_800M&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;400000000&gt;,</div><div class='add'>+					       &lt;400000000&gt;,</div><div class='add'>+					       &lt;800000000&gt;,</div><div class='add'>+					       &lt;400000000&gt;,</div><div class='add'>+					       &lt;1200000000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;pgc_gpumix&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		gic: interrupt-controller@38800000 {</div><div class='ctx'> 			compatible = "arm,gic-v3";</div><div class='ctx'> 			reg = &lt;0x38800000 0x10000&gt;,</div><div class='hunk'>@@ -857,18 +1315,12 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	usbphynop1: usbphynop1 {</div><div class='add'>+		#phy-cells = &lt;0&gt;;</div><div class='ctx'> 		compatible = "usb-nop-xceiv";</div><div class='ctx'> 		clocks = &lt;&amp;clk IMX8MN_CLK_USB_PHY_REF&gt;;</div><div class='ctx'> 		assigned-clocks = &lt;&amp;clk IMX8MN_CLK_USB_PHY_REF&gt;;</div><div class='ctx'> 		assigned-clock-parents = &lt;&amp;clk IMX8MN_SYS_PLL1_100M&gt;;</div><div class='ctx'> 		clock-names = "main_clk";</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	usbphynop2: usbphynop2 {</div><div class='del'>-		compatible = "usb-nop-xceiv";</div><div class='del'>-		clocks = &lt;&amp;clk IMX8MN_CLK_USB_PHY_REF&gt;;</div><div class='del'>-		assigned-clocks = &lt;&amp;clk IMX8MN_CLK_USB_PHY_REF&gt;;</div><div class='del'>-		assigned-clock-parents = &lt;&amp;clk IMX8MN_SYS_PLL1_100M&gt;;</div><div class='del'>-		clock-names = "main_clk";</div><div class='add'>+		power-domains = &lt;&amp;pgc_otg1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-aipstz.h b/arch/arm64/boot/dts/freescale/imx8mp-aipstz.h<br/>new file mode 100644<br/>index 000000000000..6481c484ca37<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-aipstz.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-aipstz.h</a></div><div class='hunk'>@@ -0,0 +1,33 @@</div><div class='add'>+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2025 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __IMX8MP_AIPSTZ_H</div><div class='add'>+#define __IMX8MP_AIPSTZ_H</div><div class='add'>+</div><div class='add'>+/* consumer type - master or peripheral */</div><div class='add'>+#define IMX8MP_AIPSTZ_MASTER		0x0</div><div class='add'>+#define IMX8MP_AIPSTZ_PERIPH		0x1</div><div class='add'>+</div><div class='add'>+/* master configuration options */</div><div class='add'>+#define IMX8MP_AIPSTZ_MPL		(1 &lt;&lt; 0)</div><div class='add'>+#define IMX8MP_AIPSTZ_MTW		(1 &lt;&lt; 1)</div><div class='add'>+#define IMX8MP_AIPSTZ_MTR		(1 &lt;&lt; 2)</div><div class='add'>+#define IMX8MP_AIPSTZ_MBW		(1 &lt;&lt; 3)</div><div class='add'>+</div><div class='add'>+/* peripheral configuration options */</div><div class='add'>+#define IMX8MP_AIPSTZ_TP		(1 &lt;&lt; 0)</div><div class='add'>+#define IMX8MP_AIPSTZ_WP		(1 &lt;&lt; 1)</div><div class='add'>+#define IMX8MP_AIPSTZ_SP		(1 &lt;&lt; 2)</div><div class='add'>+#define IMX8MP_AIPSTZ_BW		(1 &lt;&lt; 3)</div><div class='add'>+</div><div class='add'>+/* master ID definitions */</div><div class='add'>+#define IMX8MP_AIPSTZ_EDMA		0 /* AUDIOMIX EDMA */</div><div class='add'>+#define IMX8MP_AIPSTZ_CA53		1 /* Cortex-A53 cluster */</div><div class='add'>+#define IMX8MP_AIPSTZ_SDMA2		3 /* AUDIOMIX SDMA2 */</div><div class='add'>+#define IMX8MP_AIPSTZ_SDMA3		3 /* AUDIOMIX SDMA3 */</div><div class='add'>+#define IMX8MP_AIPSTZ_HIFI4		5 /* HIFI4 DSP */</div><div class='add'>+#define IMX8MP_AIPSTZ_CM7		6 /* Cortex-M7 */</div><div class='add'>+</div><div class='add'>+#endif /* __IMX8MP_AIPSTZ_H */</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-adpismarc.dts b/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-adpismarc.dts<br/>new file mode 100644<br/>index 000000000000..6a688510dad9<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-adpismarc.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-adpismarc.dts</a></div><div class='hunk'>@@ -0,0 +1,37 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2024 Heiko Schocher &lt;hs@denx.de&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include "imx8mp-aristainetos3a-som-v1.dtsi"</div><div class='add'>+</div><div class='add'>+&amp;{/} {</div><div class='add'>+	model = "Aristainetos3 ADLink PI SMARC carrier";</div><div class='add'>+	compatible = "abb,imx8mp-aristanetos3-adpismarc",</div><div class='add'>+		     "abb,imx8mp-aristanetos3-som",</div><div class='add'>+		     "fsl,imx8mp";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	gpio8: pinctrl@3e {</div><div class='add'>+		compatible = "semtech,sx1509q";</div><div class='add'>+		reg = &lt;0x3e&gt;;</div><div class='add'>+</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		semtech,probe-reset;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio6&gt;;</div><div class='add'>+		interrupts = &lt;1 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-helios-lvds.dtso b/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-helios-lvds.dtso<br/>new file mode 100644<br/>index 000000000000..9d1f3b4ccc79<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-helios-lvds.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-helios-lvds.dtso</a></div><div class='hunk'>@@ -0,0 +1,113 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2024 Heiko Schocher &lt;hs@denx.de&gt;</div><div class='add'>+ */</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pwm/pwm.h&gt;</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+&amp;{/} {</div><div class='add'>+	model = "Aristainetos3 helios carrier with LVDS";</div><div class='add'>+	compatible = "abb,imx8mp-aristanetos3-helios",</div><div class='add'>+		     "abb,imx8mp-aristanetos3-som",</div><div class='add'>+		     "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	panel_lvds: panel-lvds {</div><div class='add'>+		compatible = "lg,lb070wv8";</div><div class='add'>+		power-supply = &lt;&amp;reg_vcc_disp&gt;;</div><div class='add'>+		backlight = &lt;&amp;lvds_backlight&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			in_lvds0: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;ldb_lvds_ch0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc_disp: regulator-disp {</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_lcd0_vcc_en&gt;;</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "disp_power_en_2v8";</div><div class='add'>+		regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio1 13 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio3_hog&gt;;</div><div class='add'>+</div><div class='add'>+	lvdssel-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;23 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		output-low;</div><div class='add'>+		line-name = "LVDSSEL";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_blk_ctrl {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_pvi {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx_phy {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;irqsteer_hdmi {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ldb_lvds_ch0 {</div><div class='add'>+	remote-endpoint = &lt;&amp;in_lvds0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif1 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif3 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lvds_backlight {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lvds_bridge {</div><div class='add'>+	/* IMX8MP_CLK_MEDIA_LDB = IMX8MP_CLK_MEDIA_DISP2_PIX * 7 */</div><div class='add'>+	assigned-clock-rates = &lt;232820000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;media_blk_ctrl {</div><div class='add'>+	/*</div><div class='add'>+	 * currently it is not possible to let display clocks configure</div><div class='add'>+	 * automatically, so we need to set them manually</div><div class='add'>+	 */</div><div class='add'>+	assigned-clock-rates = &lt;500000000&gt;, &lt;200000000&gt;, &lt;0&gt;,</div><div class='add'>+		/* IMX8MP_CLK_MEDIA_DISP2_PIX = pixelclk of lvds panel */</div><div class='add'>+		&lt;33260000&gt;, &lt;0&gt;,</div><div class='add'>+		/* IMX8MP_VIDEO_PLL1 = IMX8MP_CLK_MEDIA_LDB * 2 */</div><div class='add'>+		&lt;465640000&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-helios.dts b/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-helios.dts<br/>new file mode 100644<br/>index 000000000000..a4e649a8239b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-helios.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-helios.dts</a></div><div class='hunk'>@@ -0,0 +1,98 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2024 Heiko Schocher &lt;hs@denx.de&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include "imx8mp-aristainetos3a-som-v1.dtsi"</div><div class='add'>+</div><div class='add'>+&amp;{/} {</div><div class='add'>+	model = "Aristainetos3 helios carrier";</div><div class='add'>+	compatible = "abb,imx8mp-aristanetos3-helios",</div><div class='add'>+		     "abb,imx8mp-aristanetos3-som",</div><div class='add'>+		     "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	led-controller {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			function-enumerator = &lt;20&gt;;</div><div class='add'>+			gpios = &lt;&amp;pca6416 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_YELLOW&gt;;</div><div class='add'>+			function-enumerator = &lt;20&gt;;</div><div class='add'>+			gpios = &lt;&amp;pca6416 13 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-2 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function-enumerator = &lt;20&gt;;</div><div class='add'>+			gpios = &lt;&amp;pca6416 14 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-3 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			function-enumerator = &lt;20&gt;;</div><div class='add'>+			gpios = &lt;&amp;pca6416 15 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethphy1 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	eeprom@57 {</div><div class='add'>+		compatible = "atmel,24c64";</div><div class='add'>+		reg = &lt;0x57&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	pca6416: gpio@20 {</div><div class='add'>+		compatible = "ti,tca6416";</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-line-names = "DIN0_CON",</div><div class='add'>+			"DIN1_CON",</div><div class='add'>+			"DIN2_CON",</div><div class='add'>+			"DIN3_CON",</div><div class='add'>+			"DIN4_CON",</div><div class='add'>+			"DIN5_CON",</div><div class='add'>+			"DIN6_CON",</div><div class='add'>+			"DIN7_CON",</div><div class='add'>+			"PM102_RES",</div><div class='add'>+			"COMx_RES",</div><div class='add'>+			"BPL_RES",</div><div class='add'>+			"PC_RES",</div><div class='add'>+			"LED_RED",</div><div class='add'>+			"LED_YELLOW",</div><div class='add'>+			"LED_GREEN",</div><div class='add'>+			"LED_BLUE";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rtc@68 {</div><div class='add'>+		compatible = "st,m41t00";</div><div class='add'>+		reg = &lt;0x68&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-proton2s.dts b/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-proton2s.dts<br/>new file mode 100644<br/>index 000000000000..58e36de7a2cd<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-proton2s.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-proton2s.dts</a></div><div class='hunk'>@@ -0,0 +1,161 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2024 Heiko Schocher &lt;hs@denx.de&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include "imx8mp-aristainetos3a-som-v1.dtsi"</div><div class='add'>+</div><div class='add'>+&amp;{/} {</div><div class='add'>+	model = "Aristainetos3 proton2s carrier";</div><div class='add'>+	compatible = "abb,imx8mp-aristanetos3-proton2s",</div><div class='add'>+		     "abb,imx8mp-aristanetos3-som",</div><div class='add'>+		     "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	watchdog {</div><div class='add'>+		/* MAX6371KA */</div><div class='add'>+		compatible = "linux,wdt-gpio";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_watchdog_gpio&gt;;</div><div class='add'>+		always-running;</div><div class='add'>+		gpios = &lt;&amp;gpio1 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		hw_algo = "level";</div><div class='add'>+		/* Reset triggers in 3..9 seconds */</div><div class='add'>+		hw_margin_ms = &lt;1500&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethphy1 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eqos {</div><div class='add'>+	max-speed = &lt;100&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi1&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio_proton2s&gt;;</div><div class='add'>+</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"", "", "", "", "", "", "", "POWER",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio6 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"RELAY0", "RELAY1", "RELAY2", "HEATER",</div><div class='add'>+		"FAN", "SPARE",	"CLEAR", "FAULT",</div><div class='add'>+		"", "", "", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	tlc59108@40 {</div><div class='add'>+		compatible = "ti,tlc59108";</div><div class='add'>+		reg = &lt;0x40&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		led@0 {</div><div class='add'>+			reg = &lt;0x0&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			function-enumerator = &lt;20&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led@1 {</div><div class='add'>+			reg = &lt;0x1&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function-enumerator = &lt;20&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led@2 {</div><div class='add'>+			reg = &lt;0x2&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function-enumerator = &lt;21&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led@3 {</div><div class='add'>+			reg = &lt;0x3&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			function-enumerator = &lt;21&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led@4 {</div><div class='add'>+			reg = &lt;0x4&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			function-enumerator = &lt;21&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led@5 {</div><div class='add'>+			reg = &lt;0x5&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			function-enumerator = &lt;22&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led@6 {</div><div class='add'>+			reg = &lt;0x6&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function-enumerator = &lt;22&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led@7 {</div><div class='add'>+			reg = &lt;0x7&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			function-enumerator = &lt;22&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rtc1: rtc@68 {</div><div class='add'>+		compatible = "dallas,ds1339";</div><div class='add'>+		reg = &lt;0x68&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	linux,rs485-enabled-at-boot-time;</div><div class='add'>+	rs485-rts-active-low;</div><div class='add'>+	rs485-rts-delay = &lt;0 0&gt;;</div><div class='add'>+	rts-gpios = &lt;&amp;gpio3 9 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3a-som-v1.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3a-som-v1.dtsi<br/>new file mode 100644<br/>index 000000000000..f654d866e58c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3a-som-v1.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-aristainetos3a-som-v1.dtsi</a></div><div class='hunk'>@@ -0,0 +1,1107 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2024 Heiko Schocher &lt;hs@denx.de&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/net/ti-dp83867.h&gt;</div><div class='add'>+#include &lt;dt-bindings/phy/phy-imx8-pcie.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pwm/pwm.h&gt;</div><div class='add'>+#include "imx8mp.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "ADLINK LEC-iMX8MP-Q-N-4G-32G";</div><div class='add'>+	compatible = "abb,imx8mp-aristanetos3-som", "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;eqos;</div><div class='add'>+		ethernet1 = &amp;fec;</div><div class='add'>+		mmc0 = &amp;usdhc3;	/* eMMC */</div><div class='add'>+		mmc1 = &amp;usdhc2;	/* MicroSD */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200";</div><div class='add'>+		stdout-path = &amp;uart2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	connector {</div><div class='add'>+		compatible = "usb-c-connector";</div><div class='add'>+		label = "USB-C";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			usb_dr_connector: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;usb3_dwc&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_led&gt;;</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_YELLOW&gt;;</div><div class='add'>+			function-enumerator = &lt;0&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio3 16 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "on";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lvds_backlight: backlight {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_lvds_bklt_en&gt;;</div><div class='add'>+		pwms = &lt;&amp;pwm2 0 50000 0&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;gpio1 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		brightness-levels = &lt;0 100&gt;;</div><div class='add'>+		num-interpolated-steps = &lt;100&gt;;</div><div class='add'>+		default-brightness-level = &lt;80&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		/* Memory size 512 MiB..8 GiB will be filled by U-Boot */</div><div class='add'>+		reg = &lt;0x0 0x40000000 0 0x08000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_refclk: clock-pcie-ref {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;100000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_can1_stby: regulator-can1-stby {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_flexcan1_reg&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio5 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "can1-stby";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_can2_stby: regulator-can2-stby {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_flexcan2_reg&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;gpio4 27 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "can2-stby";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_dp83867_2v5: regulator-enet {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;gpio7 15 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-name = "enet_2v5";</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb1_host_vbus: regulator-usb1-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usb1_vbus&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;gpio1 14 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-name = "usb1_host_vbus";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usdhc2_vmmc&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;gpio2 19 GPIO_ACTIVE_HIGH&gt;; /* SD2_RESET */</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "VDD_3V3_SD";</div><div class='add'>+		off-on-delay-us = &lt;12000&gt;;</div><div class='add'>+		startup-delay-us = &lt;100&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;buck4&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;clk {</div><div class='add'>+	clocks = &lt;&amp;osc_32k&gt;, &lt;&amp;osc_24m&gt;, &lt;&amp;clk_ext1&gt;, &lt;&amp;clk_ext2&gt;,</div><div class='add'>+		 &lt;&amp;clk_ext3&gt;, &lt;&amp;clk_ext4&gt;;</div><div class='add'>+	clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",</div><div class='add'>+		      "clk_ext3", "clk_ext4";</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_A53_SRC&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MP_CLK_A53_CORE&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MP_CLK_NOC&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MP_CLK_NOC_IO&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MP_CLK_GIC&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MP_CLK_AUDIO_AHB&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MP_CLK_AUDIO_AXI_SRC&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MP_AUDIO_PLL1&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MP_AUDIO_PLL2&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MP_VIDEO_PLL1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi1 &amp;pinctrl_ecspi1_cs2&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 9 GPIO_ACTIVE_LOW &amp;gpio1 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi2&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 13 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* eth0 */</div><div class='add'>+&amp;eqos {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_eqos_rgmii&gt;;</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	snps,force_thresh_dma_mode;</div><div class='add'>+	snps,mtl-tx-config = &lt;&amp;mtl_tx_setup&gt;;</div><div class='add'>+	snps,mtl-rx-config = &lt;&amp;mtl_rx_setup&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: eqos-ethernet-phy@0 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_1_75_NS&gt;;</div><div class='add'>+			ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_1_75_NS&gt;;</div><div class='add'>+			ti,fifo-depth = &lt;DP83867_PHYCR_FIFO_DEPTH_4_B_NIB&gt;;</div><div class='add'>+			ti,min-output-impedance;</div><div class='add'>+			ti,dp83867-rxctrl-strap-quirk;</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+			interrupts = &lt;21 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio4 22 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mtl_tx_setup: tx-queues-config {</div><div class='add'>+		snps,tx-queues-to-use = &lt;5&gt;;</div><div class='add'>+</div><div class='add'>+		queue0 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue1 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue2 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x4&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue3 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x8&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue4 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0xf0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mtl_rx_setup: rx-queues-config {</div><div class='add'>+		snps,rx-queues-to-use = &lt;5&gt;;</div><div class='add'>+</div><div class='add'>+		queue0 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x1&gt;;</div><div class='add'>+			snps,map-to-dma-channel = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue1 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x2&gt;;</div><div class='add'>+			snps,map-to-dma-channel = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue2 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x4&gt;;</div><div class='add'>+			snps,map-to-dma-channel = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue3 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x8&gt;;</div><div class='add'>+			snps,map-to-dma-channel = &lt;3&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue4 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0xf0&gt;;</div><div class='add'>+			snps,map-to-dma-channel = &lt;4&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* eth1 */</div><div class='add'>+&amp;fec {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec_rgmii&gt;;</div><div class='add'>+	phy-handle = &lt;&amp;ethphy1&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	fsl,magic-packet;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy1: ethernet-phy@1 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+			interrupts = &lt;3 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+			reset-gpio = &lt;&amp;gpio4 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_1_75_NS&gt;;</div><div class='add'>+			ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_1_75_NS&gt;;</div><div class='add'>+			ti,fifo-depth = &lt;DP83867_PHYCR_FIFO_DEPTH_4_B_NIB&gt;;</div><div class='add'>+			ti,min-output-impedance;</div><div class='add'>+			ti,dp83867-rxctrl-strap-quirk;</div><div class='add'>+			eee-broken-1000t;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan1&gt;;</div><div class='add'>+	xceiver-supply = &lt;&amp;reg_can1_stby&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan2&gt;;</div><div class='add'>+	xceiver-supply = &lt;&amp;reg_can1_stby&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_blk_ctrl {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_pvi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hdmi&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c1_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 14 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 15 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pmic: pmic@25 {</div><div class='add'>+		compatible = "nxp,pca9450c";</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;3 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * i.MX 8M Plus Data Sheet for Consumer Products</div><div class='add'>+		 * 3.1.4 Operating ranges</div><div class='add'>+		 * MIMX8ML8CVNKZAB</div><div class='add'>+		 */</div><div class='add'>+		regulators {</div><div class='add'>+			buck1: BUCK1 {	/* VDD_SOC (dual-phase with BUCK3) */</div><div class='add'>+				regulator-name = "buck1";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2187500&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck2: BUCK2 {	/* VDD_ARM */</div><div class='add'>+				regulator-name = "buck2";</div><div class='add'>+				nxp,dvs-run-voltage = &lt;950000&gt;;</div><div class='add'>+				nxp,dvs-standby-voltage = &lt;850000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2187500&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck4: BUCK4 {	/* VDD_3V3 */</div><div class='add'>+				regulator-name = "buck4";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck5: BUCK5 {	/* VDD_1V8 */</div><div class='add'>+				regulator-name = "buck5";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3400000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck6: BUCK6 {	/* NVCC_DRAM_1V1 */</div><div class='add'>+				regulator-name = "buck6";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3400000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo1: LDO1 {	/* NVCC_SNVS_1V8 */</div><div class='add'>+				regulator-name = "ldo1";</div><div class='add'>+				regulator-min-microvolt = &lt;1600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo2: LDO2 {	/* VDDA_1V8 */</div><div class='add'>+				regulator-name = "ldo2";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1150000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo3: LDO3 {	/* VDDA_1V8 */</div><div class='add'>+				regulator-name = "ldo3";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo4: LDO4 {	/* PMIC_LDO4 */</div><div class='add'>+				regulator-name = "ldo4";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo5: LDO5 {	/* NVCC_SD2 */</div><div class='add'>+				regulator-name = "ldo5";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c2_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 16 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 17 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c3_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 18 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c5 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c5&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c6 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c6&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c6_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio3 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio3 20 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* TPM - ST33TPHF2XI2C U2301 */</div><div class='add'>+	tpm: tpm@2e {</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_tpm_irq&gt;;</div><div class='add'>+		compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c";</div><div class='add'>+		reg = &lt;0x2e&gt;;</div><div class='add'>+</div><div class='add'>+		label = "tpm";</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+		interrupts = &lt;14 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio6 11 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SX1509(0) U2605 */</div><div class='add'>+	gpio6: pinctrl@3f {</div><div class='add'>+		compatible = "semtech,sx1509q";</div><div class='add'>+		reg = &lt;0x3f&gt;;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		semtech,probe-reset;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;12 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* RTC U2607 */</div><div class='add'>+	rtc0: rtc@51 {</div><div class='add'>+		compatible = "nxp,pcf8563";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SX1509(1) U2606 */</div><div class='add'>+	gpio7: pinctrl@70 {</div><div class='add'>+		compatible = "semtech,sx1509q";</div><div class='add'>+		reg = &lt;0x70&gt;;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		semtech,probe-reset;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;19 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+</div><div class='add'>+		gpio6-cfg {</div><div class='add'>+			pins = "gpio6";</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpio7-cfg {</div><div class='add'>+			pins = "gpio7";</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;irqsteer_hdmi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif1 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif2 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* HDMI */</div><div class='add'>+&amp;lcdif3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lvds_bridge {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_dsi {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie&gt;;</div><div class='add'>+	reset-gpio = &lt;&amp;gpio4 20 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	fsl,tx-deemph-gen1 = &lt;0x1f&gt;;</div><div class='add'>+	fsl,max-link-speed = &lt;3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	fsl,refclk-pad-mode = &lt;IMX8_PCIE_REFCLK_PAD_INPUT&gt;;</div><div class='add'>+	clocks = &lt;&amp;pcie0_refclk&gt;;</div><div class='add'>+	clock-names = "ref";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm2&gt;;</div><div class='add'>+	#pwm-cells = &lt;3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;snvs_pwrkey {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_0 {</div><div class='add'>+	adp-disable;</div><div class='add'>+	hnp-disable;</div><div class='add'>+	srp-disable;</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	role-switch-default-mode = "peripheral";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	port {</div><div class='add'>+		usb3_dwc: endpoint {</div><div class='add'>+			remote-endpoint = &lt;&amp;usb_dr_connector&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_1 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1_200mhz&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SD slot */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* eMMC */</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;buck4&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;buck5&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_ecspi1: aristainetos3-ecspi1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK		0x82</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI		0x82</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO		0x82</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09		0x40000</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi1_cs2: aristainetos3-ecspi1-cs2-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06		0x40000</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi2: aristainetos3-ecspi2-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK		0x82</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI		0x82</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO		0x82</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13		0x40000</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_eqos_rgmii: aristainetos3-eqos-rgmii-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x3</div><div class='add'>+			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x3</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL			0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL			0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f</div><div class='add'>+			MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22				0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec_rgmii: aristainetos3-fec-rgmii-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x91</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x91</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x91</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x91</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x1f</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x1f</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x1f</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x1f</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x1f</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02		0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan1: aristainetos3-flexcan1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SPDIF_RX__CAN1_RX			0x154</div><div class='add'>+			MX8MP_IOMUXC_SPDIF_TX__CAN1_TX			0x154</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan1_reg: aristainetos3-flexcan1-reg-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05  0x154</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan2: aristainetos3-flexcan2-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX         0x154</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX         0x154</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan2_reg: aristainetos3-flexcan2-reg-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27      0x154</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio3_hog: aristainetos3-gpio3-hog-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23	0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio_led: aristainetos3-gpio-led-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16	0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio_proton2s: aristainetos3-gpio-proton2s-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07	0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_hdmi: aristainetos3-hdmi-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL	0x400001c3</div><div class='add'>+			MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA	0x400001c3</div><div class='add'>+			MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD		0x40000019</div><div class='add'>+			MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC		0x40000019</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: aristainetos3-i2c1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c3</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1_gpio: aristainetos3-i2c1-gpio-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14	0x1c3</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15	0x1c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: aristainetos3-i2c2-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001c3</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2_gpio: aristainetos3-i2c2-gpio-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16	0x1c3</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17	0x1c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: aristainetos3-i2c3-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400001c3</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3_gpio: aristainetos3-i2c3-gpio-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18	0x1c3</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19	0x1c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c5: aristainetos3-i2c5-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL	0x400001c3</div><div class='add'>+			MX8MP_IOMUXC_SAI5_MCLK__I2C5_SDA	0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c6: aristainetos3-i2c6-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL	0x400001c3</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c6_gpio: aristainetos3-i2c6-gpio-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19	0x1c3</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20	0x1c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lcd0_vcc_en: aristainetos3-lcd0-vcc-en-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13	0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lvds_bklt_en: aristainetos3-lvds-bklt-en-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10	0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie: aristainetos3-pcie-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B	0x61</div><div class='add'>+			MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: aristainetos3-pmic-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm1: aristainetos3-pwm1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT	0x116</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm2: aristainetos3-pwm2-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT	0x116</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_tpm_irq: aristainetos3-tpm-irq-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14	0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: aristainetos3-uart1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX	0x140</div><div class='add'>+			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: aristainetos3-uart2-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x140</div><div class='add'>+			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x140</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06	0x140</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: aristainetos3-uart3-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_ALE__UART3_DCE_RX	0x140</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE0_B__UART3_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart4: aristainetos3-uart4-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX    0x140</div><div class='add'>+			MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX    0x140</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09	0x140</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA02__UART4_DCE_CTS 0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usb1_vbus: aristainetos3-usb1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14	0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: aristainetos3-usdhc1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x190</div><div class='add'>+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_100mhz: aristainetos3-usdhc1-100mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x194</div><div class='add'>+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_200mhz: aristainetos3-usdhc1-200mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x196</div><div class='add'>+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: aristainetos3-usdhc2-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x190</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1</div><div class='add'>+</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: aristainetos3-usdhc2-100mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x194</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: aristainetos3-usdhc2-200mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x196</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: aristainetos3-usdhc2-gpio-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12	0x40000080</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_vmmc: aristainetos3-usdhc2-vmmc-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: aristainetos3-usdhc3-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x190</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x190</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: aristainetos3-usdhc3-100mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x194</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x194</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: aristainetos3-usdhc3-200mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x196</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x196</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_watchdog_gpio: aristainetos3-wdog-gpio-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06	0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: aristainetos3-wdog-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B	0xc6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts b/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts<br/>new file mode 100644<br/>index 000000000000..31c33acb560c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts</a></div><div class='hunk'>@@ -0,0 +1,837 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Logic PD, Inc dba Beacon EmbeddedWorks</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/usb/pd.h&gt;</div><div class='add'>+#include &lt;dt-bindings/phy/phy-imx8-pcie.h&gt;</div><div class='add'>+#include "imx8mp.dtsi"</div><div class='add'>+#include "imx8mp-beacon-som.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Beacon EmbeddedWorks i.MX8MPlus Development kit";</div><div class='add'>+	compatible = "beacon,imx8mp-beacon-kit", "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;eqos;</div><div class='add'>+		ethernet1 = &amp;fec;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_xtal25: clock-xtal25 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;25000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	connector {</div><div class='add'>+		compatible = "usb-c-connector";</div><div class='add'>+		label = "USB-C";</div><div class='add'>+		data-role = "dual";</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				hs_ep: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;usb3_hs_ep&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+			port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				ss_ep: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;hd3ss3220_in_ep&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dmic_codec: dmic-codec {</div><div class='add'>+		compatible = "dmic-codec";</div><div class='add'>+		num-channels = &lt;1&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		autorepeat;</div><div class='add'>+</div><div class='add'>+		button-0 {</div><div class='add'>+			label = "btn0";</div><div class='add'>+			linux,code = &lt;BTN_0&gt;;</div><div class='add'>+			gpios = &lt;&amp;pca6416_1 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-1 {</div><div class='add'>+			label = "btn1";</div><div class='add'>+			linux,code = &lt;BTN_1&gt;;</div><div class='add'>+			gpios = &lt;&amp;pca6416_1 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-2 {</div><div class='add'>+			label = "btn2";</div><div class='add'>+			linux,code = &lt;BTN_2&gt;;</div><div class='add'>+			gpios = &lt;&amp;pca6416_1 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-3 {</div><div class='add'>+			label = "btn3";</div><div class='add'>+			linux,code = &lt;BTN_3&gt;;</div><div class='add'>+			gpios = &lt;&amp;pca6416_1 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bridge-connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		type = "a";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			hdmi_con: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;adv7535_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdmi-connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		type = "a";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			hdmi_connector: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_to_connector&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_led3&gt;;</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			label = "gen_led0";</div><div class='add'>+			gpios = &lt;&amp;pca6416_1 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			label = "gen_led1";</div><div class='add'>+			gpios = &lt;&amp;pca6416_1 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-2 {</div><div class='add'>+			label = "gen_led2";</div><div class='add'>+			gpios = &lt;&amp;pca6416_1 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-3 {</div><div class='add'>+			label = "heartbeat";</div><div class='add'>+			gpios = &lt;&amp;gpio4 28 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_audio: regulator-wm8962 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "3v3_aud";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;pca6416_1 11 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VSD_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio2 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		startup-delay-us = &lt;100&gt;;</div><div class='add'>+		off-on-delay-us = &lt;20000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb1_host_vbus: regulator-usb1-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "usb1_host_vbus";</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;pca6416_1 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-adv7535 {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,name = "sound-adv7535";</div><div class='add'>+		simple-audio-card,format = "i2s";</div><div class='add'>+</div><div class='add'>+		simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;sai5&gt;;</div><div class='add'>+			system-clock-direction-out;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		simple-audio-card,codec {</div><div class='add'>+			sound-dai = &lt;&amp;adv_bridge&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-dmic {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,name = "sound-pdm";</div><div class='add'>+		simple-audio-card,format = "i2s";</div><div class='add'>+		simple-audio-card,bitclock-master = &lt;&amp;dailink_master&gt;;</div><div class='add'>+		simple-audio-card,frame-master = &lt;&amp;dailink_master&gt;;</div><div class='add'>+</div><div class='add'>+		dailink_master: simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;micfil&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		simple-audio-card,codec {</div><div class='add'>+			sound-dai = &lt;&amp;dmic_codec&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-wm8962 {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,name = "wm8962";</div><div class='add'>+		simple-audio-card,format = "i2s";</div><div class='add'>+		simple-audio-card,widgets = "Headphone", "Headphones",</div><div class='add'>+					    "Microphone", "Headset Mic",</div><div class='add'>+					    "Speaker", "Speaker";</div><div class='add'>+		simple-audio-card,routing = "Headphones", "HPOUTL",</div><div class='add'>+					    "Headphones", "HPOUTR",</div><div class='add'>+					    "Speaker", "SPKOUTL",</div><div class='add'>+					    "Speaker", "SPKOUTR",</div><div class='add'>+					    "Headset Mic", "MICBIAS",</div><div class='add'>+					    "IN3R", "Headset Mic";</div><div class='add'>+</div><div class='add'>+		simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;sai3&gt;;</div><div class='add'>+			frame-master;</div><div class='add'>+			bitclock-master;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		simple-audio-card,codec {</div><div class='add'>+			sound-dai = &lt;&amp;wm8962&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;audio_blk_ctrl {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_AUDIO_PLL1&gt;, &lt;&amp;clk IMX8MP_AUDIO_PLL2&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;393216000&gt;, &lt;135475200&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi2&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 13 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	tpm: tpm@0 {</div><div class='add'>+		compatible = "infineon,slb9670", "tcg,tpm_tis-spi";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_tpm&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio4 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		spi-max-frequency = &lt;18500000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy1&gt;;</div><div class='add'>+	fsl,magic-packet;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy1: ethernet-phy@3 {</div><div class='add'>+			compatible = "ethernet-phy-id0022.1640",</div><div class='add'>+				     "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;3&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio4 18 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;10000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;150000&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+			interrupts = &lt;2 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio2 {</div><div class='add'>+	usb-mux-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;20 0&gt;;</div><div class='add'>+		output-low;</div><div class='add'>+		line-name = "USB-C Mux En";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hdmi&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			hdmi_to_connector:endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_connector&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;384000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pca6416_3: gpio@20 {</div><div class='add'>+		compatible = "nxp,pcal6416";</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;27 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	adv_bridge: hdmi@3d {</div><div class='add'>+		compatible = "adi,adv7535";</div><div class='add'>+		reg = &lt;0x3d&gt;;</div><div class='add'>+		reg-names = "main";</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;27 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		adi,dsi-lanes = &lt;4&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		avdd-supply = &lt;&amp;buck5&gt;;</div><div class='add'>+		dvdd-supply = &lt;&amp;buck5&gt;;</div><div class='add'>+		pvdd-supply = &lt;&amp;buck5&gt;;</div><div class='add'>+		a2vdd-supply = &lt;&amp;buck5&gt;;</div><div class='add'>+		v1p2-supply = &lt;&amp;buck5&gt;;</div><div class='add'>+		v3p3-supply = &lt;&amp;buck4&gt;;</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				adv7535_in: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;dsi_out&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				adv7535_out: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;hdmi_con&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcieclk: clock-generator@68 {</div><div class='add'>+		compatible = "renesas,9fgv0241";</div><div class='add'>+		reg = &lt;0x68&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk_xtal25&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_pvi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	/* Connected to USB Hub */</div><div class='add'>+	usb-typec@52 {</div><div class='add'>+		compatible = "nxp,ptn5110", "tcpci";</div><div class='add'>+		reg = &lt;0x52&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_typec&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;1 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		connector {</div><div class='add'>+			compatible = "usb-c-connector";</div><div class='add'>+			label = "USB-C";</div><div class='add'>+			power-role = "source";</div><div class='add'>+			data-role = "host";</div><div class='add'>+			source-pdos = &lt;PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c4&gt;;</div><div class='add'>+	clock-frequency = &lt;384000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	wm8962: audio-codec@1a {</div><div class='add'>+		compatible = "wlf,wm8962";</div><div class='add'>+		reg = &lt;0x1a&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_wm8962&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX8MP_CLK_IPP_DO_CLKO1&gt;;</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX8MP_CLK_IPP_DO_CLKO1&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;&amp;clk IMX8MP_AUDIO_PLL2_OUT&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;22576000&gt;;</div><div class='add'>+		DCVDD-supply = &lt;&amp;reg_audio&gt;;</div><div class='add'>+		DBVDD-supply = &lt;&amp;reg_audio&gt;;</div><div class='add'>+		AVDD-supply = &lt;&amp;reg_audio&gt;;</div><div class='add'>+		CPVDD-supply = &lt;&amp;reg_audio&gt;;</div><div class='add'>+		MICVDD-supply = &lt;&amp;reg_audio&gt;;</div><div class='add'>+		PLLVDD-supply = &lt;&amp;reg_audio&gt;;</div><div class='add'>+		SPKVDD1-supply = &lt;&amp;reg_audio&gt;;</div><div class='add'>+		SPKVDD2-supply = &lt;&amp;reg_audio&gt;;</div><div class='add'>+		gpio-cfg = &lt;</div><div class='add'>+			0x0000 /* 0:Default */</div><div class='add'>+			0x0000 /* 1:Default */</div><div class='add'>+			0x0000 /* 2:FN_DMICCLK */</div><div class='add'>+			0x0000 /* 3:Default */</div><div class='add'>+			0x0000 /* 4:FN_DMICCDAT */</div><div class='add'>+			0x0000 /* 5:Default */</div><div class='add'>+		&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pca6416: gpio@20 {</div><div class='add'>+		compatible = "nxp,pcal6416";</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pcal6414&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;27 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pca6416_1: gpio@21 {</div><div class='add'>+		compatible = "nxp,pcal6416";</div><div class='add'>+		reg = &lt;0x21&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;27 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		usb-hub-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;7 0&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+			line-name = "USB Hub Enable";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb-typec@47 {</div><div class='add'>+		compatible = "ti,hd3ss3220";</div><div class='add'>+		reg = &lt;0x47&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_hd3ss3220&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;19 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				hd3ss3220_in_ep: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;ss_ep&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				hd3ss3220_out_ep: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;usb3_role_switch&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;micfil {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pdm&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_PDM&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;49152000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_dsi {</div><div class='add'>+	samsung,esc-clock-frequency = &lt;10000000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			dsi_out: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;adv7535_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie&gt;;</div><div class='add'>+	reset-gpio = &lt;&amp;gpio4 21 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	fsl,clkreq-unsupported;</div><div class='add'>+	fsl,refclk-pad-mode = &lt;IMX8_PCIE_REFCLK_PAD_INPUT&gt;;</div><div class='add'>+	clocks = &lt;&amp;pcieclk 1&gt;;</div><div class='add'>+	clock-names = "ref";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai3&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_SAI3&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;12288000&gt;;</div><div class='add'>+	fsl,sai-mclk-direction-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai5 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai5&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_SAI5&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;12288000&gt;;</div><div class='add'>+	fsl,sai-mclk-direction-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;snvs_pwrkey {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_UART3&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL1_80M&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_0 {</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	hnp-disable;</div><div class='add'>+	srp-disable;</div><div class='add'>+	adp-disable;</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		port@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			usb3_hs_ep: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hs_ep&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			usb3_role_switch: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hd3ss3220_out_ep&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy0 {</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usb1_host_vbus&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_1 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_ecspi2: ecspi2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK	0x82</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI	0x82</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO	0x82</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13	0x40000</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec: fecgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC	0x2</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO	0x2</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0	0x90</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1	0x90</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2	0x90</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3	0x90</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC	0x90</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x90</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0	0x16</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1	0x16</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2	0x16</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3	0x16</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x16</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC	0x16</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02	0x140</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18	0x10</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan1: flexcan1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SPDIF_RX__CAN1_RX	0x154</div><div class='add'>+			MX8MP_IOMUXC_SPDIF_TX__CAN1_TX	0x154</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_hd3ss3220: hd3ss3220grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_hdmi: hdmigrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL	0x400001c2</div><div class='add'>+			MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA	0x400001c2</div><div class='add'>+			MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD		0x40000010</div><div class='add'>+			MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC		0x40000010</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL	0x400001c2</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA	0x400001c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4: i2c4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL	0x400001c2</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA	0x400001c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_led3: led3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcal6414: pcal6414-gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27	0x10</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie: pciegrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05	0x10 /* PCIe_nDIS */</div><div class='add'>+			MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x10	/* PCIe_nRST */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pdm: pdmgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CLK		0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_PDM_BIT_STREAM00	0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x40</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai3: sai3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC	0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK	0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00	0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00	0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK	0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai5: sai5grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_TX_DATA00	0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK	0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC	0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_tpm: tpmgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00	0x19 /* Reset */</div><div class='add'>+			MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29	0x1d6 /* IRQ */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_typec: typec1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01	0xc4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x140</div><div class='add'>+			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: uart3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX		0x140</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX		0x140</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS		0x140</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS		0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x190</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x194</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x196</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12	0x1c4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wm8962: wm8962grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1	0x59</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi<br/>new file mode 100644<br/>index 000000000000..6a62cb32e22e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi</a></div><div class='hunk'>@@ -0,0 +1,497 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 LogicPD, Inc. dba Beacon EmbeddedWorks</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		rtc0 = &amp;rtc;</div><div class='add'>+		rtc1 = &amp;snvs_rtc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x40000000 0 0xc0000000&gt;,</div><div class='add'>+		      &lt;0x1 0x00000000 0 0xc0000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_wl_bt: regulator-wifi-bt {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_wl_bt&gt;;</div><div class='add'>+		regulator-name = "wl-bt-pow-dwn";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio2 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		startup-delay-us = &lt;70000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eqos {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_eqos&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	snps,force_thresh_dma_mode;</div><div class='add'>+	snps,mtl-rx-config = &lt;&amp;mtl_rx_setup&gt;;</div><div class='add'>+	snps,mtl-tx-config = &lt;&amp;mtl_tx_setup&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@3 {</div><div class='add'>+			compatible = "ethernet-phy-id0022.1640",</div><div class='add'>+				     "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;3&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio4 10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+			interrupts = &lt;10 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mtl_rx_setup: rx-queues-config {</div><div class='add'>+		snps,rx-queues-to-use = &lt;5&gt;;</div><div class='add'>+</div><div class='add'>+		queue0 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x1&gt;;</div><div class='add'>+			snps,map-to-dma-channel = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue1 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x2&gt;;</div><div class='add'>+			snps,map-to-dma-channel = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue2 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x4&gt;;</div><div class='add'>+			snps,map-to-dma-channel = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue3 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x8&gt;;</div><div class='add'>+			snps,map-to-dma-channel = &lt;3&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue4 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0xf0&gt;;</div><div class='add'>+			snps,map-to-dma-channel = &lt;4&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mtl_tx_setup: tx-queues-config {</div><div class='add'>+		snps,tx-queues-to-use = &lt;5&gt;;</div><div class='add'>+</div><div class='add'>+		queue0 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue1 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue2 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x4&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue3 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x8&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue4 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0xf0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexspi {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexspi0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash0: flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;80000000&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;1&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	clock-frequency = &lt;384000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pmic@25 {</div><div class='add'>+		compatible = "nxp,pca9450c";</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;3 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			buck1: BUCK1 {</div><div class='add'>+				regulator-name = "BUCK1";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2187500&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck2: BUCK2 {</div><div class='add'>+				regulator-name = "BUCK2";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2187500&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+				nxp,dvs-run-voltage = &lt;950000&gt;;</div><div class='add'>+				nxp,dvs-standby-voltage = &lt;850000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck4: BUCK4 {</div><div class='add'>+				regulator-name = "BUCK4";</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck5: BUCK5 {</div><div class='add'>+				regulator-name = "BUCK5";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck6: BUCK6 {</div><div class='add'>+				regulator-name = "BUCK6";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo1: LDO1 {</div><div class='add'>+				regulator-name = "LDO1";</div><div class='add'>+				regulator-min-microvolt = &lt;1600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo3: LDO3 {</div><div class='add'>+				regulator-name = "LDO3";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo4: LDO4 {</div><div class='add'>+				regulator-name = "LDO4";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo5: LDO5 {</div><div class='add'>+				regulator-name = "LDO5";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	clock-frequency = &lt;384000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	eeprom@50 {</div><div class='add'>+		compatible = "atmel,24c64";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		read-only;	/* Manufacturing EEPROM programmed at factory */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rtc: rtc@51 {</div><div class='add'>+		compatible = "nxp,pcf85263";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_rtc&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;13 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		quartz-load-femtofarads = &lt;12500&gt;;</div><div class='add'>+		wakeup-source;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;snvs_pwrkey {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_UART1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL1_80M&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "nxp,88w8997-bt";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1_200mhz&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_wl_bt&gt;;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	sd-uhs-sdr50;</div><div class='add'>+	sd-uhs-sdr104;</div><div class='add'>+	keep-power-in-suspend;</div><div class='add'>+	wakeup-source;</div><div class='add'>+	non-removable;</div><div class='add'>+	cap-power-off-card;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mwifiex: wifi@1 {</div><div class='add'>+		compatible = "marvell,sd8997";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_wlan&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio2&gt;;</div><div class='add'>+		interrupts = &lt;9 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_eqos: eqosgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC		0x2</div><div class='add'>+			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO		0x2</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0	0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1	0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2	0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3	0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL	0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0	0x16</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1	0x16</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2	0x16</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3	0x16</div><div class='add'>+			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL	0x16</div><div class='add'>+			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x16</div><div class='add'>+			MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22		0x10</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10	0x10</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexspi0: flexspi0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK           0x1c2</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B        0x82</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00      0x82</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01      0x82</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02      0x82</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03      0x82</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c2</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400001c2</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: pmicgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03	0x1c0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_wl_bt: reg-wl-btgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06	0x40</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_rtc: rtcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX	0x140</div><div class='add'>+			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX	0x140</div><div class='add'>+			MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS	0x140</div><div class='add'>+			MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x190</div><div class='add'>+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x194</div><div class='add'>+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x196</div><div class='add'>+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x190</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x190</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x194</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x194</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x196</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x196</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B	0x166</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wlan: wlangrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09		0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-cubox-m.dts b/arch/arm64/boot/dts/freescale/imx8mp-cubox-m.dts<br/>new file mode 100644<br/>index 000000000000..8290f187b79f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-cubox-m.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-cubox-m.dts</a></div><div class='hunk'>@@ -0,0 +1,223 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2025 Josua Mayer &lt;josua@solid-run.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+#include "imx8mp-sr-som.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "SolidRun i.MX8MP CuBox-M";</div><div class='add'>+	compatible = "solidrun,imx8mp-cubox-m",</div><div class='add'>+		     "solidrun,imx8mp-sr-som", "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;eqos;</div><div class='add'>+		/delete-property/ ethernet1;</div><div class='add'>+		rtc0 = &amp;carrier_rtc;</div><div class='add'>+		rtc1 = &amp;snvs_rtc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ir-receiver {</div><div class='add'>+		compatible = "gpio-ir-receiver";</div><div class='add'>+		gpios = &lt;&amp;gpio1 10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;ir_pins&gt;;</div><div class='add'>+		linux,autosuspend-period = &lt;125&gt;;</div><div class='add'>+		wakeup-source;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;led_pins&gt;;</div><div class='add'>+</div><div class='add'>+		status {</div><div class='add'>+			label = "status";</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio1 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			function = LED_FUNCTION_HEARTBEAT;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-hdmi {</div><div class='add'>+		compatible = "fsl,imx-audio-hdmi";</div><div class='add'>+		model = "audio-hdmi";</div><div class='add'>+		audio-cpu = &lt;&amp;aud2htx&gt;;</div><div class='add'>+		hdmi-out;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vbus: regulator-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vbus";</div><div class='add'>+		gpio = &lt;&amp;gpio1 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;vbus_pins&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vmmc: regulator-mmc {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;vmmc_pins&gt;;</div><div class='add'>+		regulator-name = "vmmc";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio2 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		startup-delay-us = &lt;250&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;aud2htx {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec {</div><div class='add'>+	/* this board does not use second phy / ethernet on SoM */</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_pvi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	carrier_rtc: rtc@32 {</div><div class='add'>+		compatible = "epson,rx8130";</div><div class='add'>+		reg = &lt;0x32&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;hdmi_pins&gt;;</div><div class='add'>+</div><div class='add'>+	hdmi_pins: pinctrl-hdmi-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL	0x400001c3</div><div class='add'>+			MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA	0x400001c3</div><div class='add'>+			MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC		0x154</div><div class='add'>+			MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD		0x154</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ir_pins: pinctrl-ir-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10		0x4f</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	led_pins: pinctrl-led-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12		0x0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usdhc2_pins: pinctrl-usdhc2-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x190</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0x140</div><div class='add'>+			MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B		0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usdhc2_100mhz_pins: pinctrl-usdhc2-100mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x194</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0x140</div><div class='add'>+			MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B		0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usdhc2_200mhz_pins: pinctrl-usdhc2-200mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x196</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0x140</div><div class='add'>+			MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B		0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vbus_pins: pinctrl-vbus-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07		0x100</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vmmc_pins: pinctrl-vmmc-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19		0x0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy0 {</div><div class='add'>+	fsl,phy-tx-preemp-amp-tune-microamp = &lt;1200&gt;;</div><div class='add'>+	vbus-supply = &lt;&amp;vbus&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy1 {</div><div class='add'>+	fsl,phy-tx-preemp-amp-tune-microamp = &lt;1200&gt;;</div><div class='add'>+	vbus-supply = &lt;&amp;vbus&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_0 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_1 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;usdhc2_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;usdhc2_100mhz_pins&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;usdhc2_200mhz_pins&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;vmmc&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cap-power-off-card;</div><div class='add'>+	full-pwr-cycle;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts<br/>new file mode 100644<br/>index 000000000000..16078ff60ef0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts</a></div><div class='hunk'>@@ -0,0 +1,1103 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2022 Marek Vasut &lt;marex@denx.de&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/net/qca-ar803x.h&gt;</div><div class='add'>+#include &lt;dt-bindings/phy/phy-imx8-pcie.h&gt;</div><div class='add'>+#include "imx8mp.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Data Modul i.MX8M Plus eDM SBC";</div><div class='add'>+	compatible = "dmo,imx8mp-data-modul-edm-sbc", "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		rtc0 = &amp;rtc;</div><div class='add'>+		rtc1 = &amp;snvs_rtc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart3;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		/* There are 1/2/4 GiB options, adjusted by bootloader. */</div><div class='add'>+		reg = &lt;0x0 0x40000000 0 0x40000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	backlight: backlight {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_panel_backlight&gt;;</div><div class='add'>+		brightness-levels = &lt;0 1 10 20 30 40 50 60 70 75 80 90 100&gt;;</div><div class='add'>+		default-brightness-level = &lt;7&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;gpio3 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pwms = &lt;&amp;pwm1 0 5000000 0&gt;;</div><div class='add'>+		/* Disabled by default, unless display board plugged in. */</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_xtal25: clock-xtal25 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;25000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_pwm4: clock-pwm4 {</div><div class='add'>+		compatible = "pwm-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;12000000&gt;;</div><div class='add'>+		clock-output-names = "codec-pwm4";</div><div class='add'>+		/*</div><div class='add'>+		 * 1 / 83 ns ~= 12 MHz , but since the PWM input clock is 24 MHz</div><div class='add'>+		 * and the calculated PWM period is 1 and duty cycle is 50%, the</div><div class='add'>+		 * result is exactly 12 MHz, which is fine for SGTL5000 MCLK.</div><div class='add'>+		 */</div><div class='add'>+		pwms = &lt;&amp;pwm4 0 83 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdmi-connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		label = "J17";</div><div class='add'>+		type = "a";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			hdmi_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_tx_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	panel: panel {</div><div class='add'>+		/* Compatible string is filled in by panel board DT Overlay. */</div><div class='add'>+		backlight = &lt;&amp;backlight&gt;;</div><div class='add'>+		power-supply = &lt;&amp;reg_panel_vcc&gt;;</div><div class='add'>+		/* Disabled by default, unless display board plugged in. */</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_panel_vcc: regulator-panel-vcc {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_panel_vcc_reg&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-name = "PANEL_VCC";</div><div class='add'>+		/* GPIO flags are ignored, enable-active-high applies. */</div><div class='add'>+		gpio = &lt;&amp;gpio3 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		/* Disabled by default, unless display board plugged in. */</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usdhc2_vmmc&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "VDD_3V3_SD";</div><div class='add'>+		/* GPIO flags are ignored, enable-active-high applies. */</div><div class='add'>+		gpio = &lt;&amp;gpio2 19 GPIO_ACTIVE_HIGH&gt;; /* SD2_RESET */</div><div class='add'>+		enable-active-high;</div><div class='add'>+		off-on-delay-us = &lt;12000&gt;;</div><div class='add'>+		startup-delay-us = &lt;100&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;buck4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,name = "SGTL5000-Card";</div><div class='add'>+		simple-audio-card,format = "i2s";</div><div class='add'>+		simple-audio-card,bitclock-master = &lt;&amp;codec_dai&gt;;</div><div class='add'>+		simple-audio-card,frame-master = &lt;&amp;codec_dai&gt;;</div><div class='add'>+		simple-audio-card,widgets = "Headphone", "Headphone Jack";</div><div class='add'>+		simple-audio-card,routing = "Headphone Jack", "HP_OUT";</div><div class='add'>+</div><div class='add'>+		cpu_dai: simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;sai3&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		codec_dai: simple-audio-card,codec {</div><div class='add'>+			sound-dai = &lt;&amp;sgtl5000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	watchdog { /* TPS3813 */</div><div class='add'>+		compatible = "linux,wdt-gpio";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_watchdog_gpio&gt;;</div><div class='add'>+		always-running;</div><div class='add'>+		gpios = &lt;&amp;gpio2 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		hw_algo = "level";</div><div class='add'>+		/* Reset triggers in 2..3 seconds */</div><div class='add'>+		hw_margin_ms = &lt;1500&gt;;</div><div class='add'>+		/* Disabled by default */</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi1&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash@0 {	/* W25Q128JVEI */</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;40000000&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;1&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi2 {	/* Feature connector SPI */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi2&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 13 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	/* Disabled by default, unless feature board plugged in. */</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi3 {	/* Display connector SPI */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi3&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 25 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	/* Disabled by default, unless display board plugged in. */</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eqos {	/* First ethernet */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_eqos&gt;;</div><div class='add'>+	phy-handle = &lt;&amp;phy_eqos&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		/* Atheros AR8031 PHY */</div><div class='add'>+		phy_eqos: ethernet-phy@0 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			/*</div><div class='add'>+			 * Dedicated ENET_WOL# signal is unused, the PHY</div><div class='add'>+			 * can wake the SoC up via INT signal as well.</div><div class='add'>+			 */</div><div class='add'>+			interrupts-extended = &lt;&amp;gpio1 11 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio1 15 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;10000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;10000&gt;;</div><div class='add'>+			qca,keep-pll-enabled;</div><div class='add'>+			vddio-supply = &lt;&amp;vddio_eqos&gt;;</div><div class='add'>+</div><div class='add'>+			vddio_eqos: vddio-regulator {</div><div class='add'>+				regulator-name = "VDDIO_EQOS";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vddh_eqos: vddh-regulator {</div><div class='add'>+				regulator-name = "VDDH_EQOS";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec {	/* Second ethernet */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec&gt;;</div><div class='add'>+	phy-handle = &lt;&amp;phy_fec&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	fsl,magic-packet;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		/* Atheros AR8031 PHY */</div><div class='add'>+		phy_fec: ethernet-phy@0 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			/*</div><div class='add'>+			 * Dedicated ENET_WOL# signal is unused, the PHY</div><div class='add'>+			 * can wake the SoC up via INT signal as well.</div><div class='add'>+			 */</div><div class='add'>+			interrupts-extended = &lt;&amp;gpio2 2 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio2 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;10000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;10000&gt;;</div><div class='add'>+			qca,keep-pll-enabled;</div><div class='add'>+			vddio-supply = &lt;&amp;vddio_fec&gt;;</div><div class='add'>+</div><div class='add'>+			vddio_fec: vddio-regulator {</div><div class='add'>+				regulator-name = "VDDIO_FEC";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vddh_fec: vddh-regulator {</div><div class='add'>+				regulator-name = "VDDH_FEC";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"", "USBHUB_RESET#", "WDOG_B#", "PMIC_INT#",</div><div class='add'>+		"", "M2_PCIE_RST#", "M2_PCIE_WAKE#", "GPIO5_IO03",</div><div class='add'>+		"GPIO5_IO04", "PDM_SEL", "ENET_WOL#", "ENET_INT#",</div><div class='add'>+		"", "", "", "ENET_RST#",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio2 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"", "", "ENET2_INT#", "", "", "", "", "",</div><div class='add'>+		"WDOG_KICK#", "ENET2_RST#", "CAN_INT#", "RTC_IRQ#",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "SD2_RESET#", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio3 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"BL_ENABLE_1V8", "PG_V_IN_VAR#", "", "",</div><div class='add'>+		"", "", "TFT_ENABLE_1V8", "GRAPHICS_GPIO0_1V8",</div><div class='add'>+		"CSI2_PD_1V8", "CSI2_RESET_1V8#", "", "",</div><div class='add'>+		"", "", "EEPROM_WP_1V8#", "", "", "", "", "",</div><div class='add'>+		"MEMCFG0", "PCIE_CLK_GEN_CLKPWRGD_PD_1V8#",</div><div class='add'>+		"", "M2_W_DISABLE1_1V8#",</div><div class='add'>+		"M2_W_DISABLE2_1V8#", "", "I2C5_SCL_3V3", "I2C5_SDA_3V3",</div><div class='add'>+		"", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"DSI_RESET_1V8#", "MEMCFG2", "", "MEMCFG1", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "GRAPHICS_PRSNT_1V8#", "DSI_IRQ_1V8#",</div><div class='add'>+		"", "DIS_USB_DN1", "DIS_USB_DN2", "",</div><div class='add'>+		"", "", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio5 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"", "", "", "", "", "WDOG_EN", "", "",</div><div class='add'>+		"", "SPI1_CS#", "", "",</div><div class='add'>+		"", "SPI2_CS#", "I2C1_SCL_3V3", "I2C1_SDA_3V3",</div><div class='add'>+		"I2C2_SCL_3V3", "I2C2_SDA_3V3", "I2C3_SCL_3V3", "I2C3_SDA_3V3",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "SPI3_CS#", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_pvi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	ddc-i2c-bus = &lt;&amp;i2c5&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hdmi&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@1 {</div><div class='add'>+			hdmi_tx_out: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_connector_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c1_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	sgtl5000: audio-codec@a {</div><div class='add'>+		compatible = "fsl,sgtl5000";</div><div class='add'>+		reg = &lt;0x0a&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk_pwm4&gt;;</div><div class='add'>+		VDDA-supply = &lt;&amp;buck4&gt;;</div><div class='add'>+		VDDIO-supply = &lt;&amp;buck4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb-hub@2c {</div><div class='add'>+		compatible = "microchip,usb2514bi";</div><div class='add'>+		reg = &lt;0x2c&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usb_hub&gt;;</div><div class='add'>+		individual-port-switching;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio1 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		self-powered;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom: eeprom@50 {</div><div class='add'>+		compatible = "atmel,24c32";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rtc: rtc@68 {</div><div class='add'>+		compatible = "st,m41t62";</div><div class='add'>+		reg = &lt;0x68&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_rtc&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;gpio2 11 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcieclk: clk@6a {</div><div class='add'>+		compatible = "renesas,9fgv0241";</div><div class='add'>+		reg = &lt;0x6a&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk_xtal25&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c2_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c3_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pmic: pmic@25 {</div><div class='add'>+		compatible = "nxp,pca9450c";</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;3 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * i.MX 8M Plus Data Sheet for Consumer Products</div><div class='add'>+		 * 3.1.4 Operating ranges</div><div class='add'>+		 * MIMX8ML8CVNKZAB</div><div class='add'>+		 */</div><div class='add'>+		regulators {</div><div class='add'>+			buck1: BUCK1 {	/* VDD_SOC (dual-phase with BUCK3) */</div><div class='add'>+				regulator-min-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck2: BUCK2 {	/* VDD_ARM */</div><div class='add'>+				nxp,dvs-run-voltage = &lt;950000&gt;;</div><div class='add'>+				nxp,dvs-standby-voltage = &lt;850000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck4: BUCK4 {	/* VDD_3V3 */</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck5: BUCK5 {	/* VDD_1V8 */</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck6: BUCK6 {	/* NVCC_DRAM_1V1 */</div><div class='add'>+				regulator-min-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo1: LDO1 {	/* NVCC_SNVS_1V8 */</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo3: LDO3 {	/* VDDA_1V8 */</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo4: LDO4 {	/* PMIC_LDO4 */</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo5: LDO5 {	/* NVCC_SD2 */</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c5 {	/* HDMI EDID bus */</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c5&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c5_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	clocks = &lt;&amp;pcieclk 0&gt;;</div><div class='add'>+	clock-names = "ref";</div><div class='add'>+	fsl,refclk-pad-mode = &lt;IMX8_PCIE_REFCLK_PAD_INPUT&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie0&gt;;</div><div class='add'>+	fsl,max-link-speed = &lt;3&gt;;</div><div class='add'>+	reset-gpio = &lt;&amp;gpio1 5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_panel_pwm&gt;;</div><div class='add'>+	/* Disabled by default, unless display board plugged in. */</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai3 {</div><div class='add'>+	#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_SAI3&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;12288000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SD slot */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;ldo5&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* eMMC */</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;buck4&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;buck5&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	no-sd;</div><div class='add'>+	no-sdio;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {	/* RS485 */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "disabled";	/* Optional */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart3 {	/* A53 Debug */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart4&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_0 {</div><div class='add'>+	fsl,over-current-active-low;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_0 {	/* Lower plug direct */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usb1&gt;;</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_1 {	/* Upper plug via HUB */</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* IOMUXC node should be at the end of DT to improve readability. */</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hog_feature&gt;, &lt;&amp;pinctrl_hog_misc&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_hog_panel&gt;, &lt;&amp;pinctrl_hog_sbc&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_panel_expansion&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi1: ecspi1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK		0x44</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI		0x44</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO		0x44</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09		0x40</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi2: ecspi2-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK		0x44</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI		0x44</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO		0x44</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13		0x40</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi3: ecspi3-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK		0x44</div><div class='add'>+			MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI		0x44</div><div class='add'>+			MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO		0x44</div><div class='add'>+			MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25		0x40</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_eqos: eqos-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC		0x3</div><div class='add'>+			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO		0x3</div><div class='add'>+			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL	0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0	0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1	0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2	0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3	0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL	0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0	0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1	0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2	0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3	0x91</div><div class='add'>+			/* ENET_RST# */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15		0x6</div><div class='add'>+			/* ENET_INT# */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11		0x40000090</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec: fec-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x91</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x91</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x91</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x91</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x1f</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x1f</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x1f</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x1f</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x1f</div><div class='add'>+			/* ENET2_RST# */</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09		0x6</div><div class='add'>+			/* ENET2_INT# */</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02		0x40000090</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan1: flexcan1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SPDIF_RX__CAN1_RX			0x154</div><div class='add'>+			MX8MP_IOMUXC_SPDIF_TX__CAN1_TX			0x154</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_hdmi: hdmi-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC		0x154</div><div class='add'>+			MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD		0x154</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_hog_feature: hog-feature-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* GPIO5_IO03 */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07		0x40000006</div><div class='add'>+			/* GPIO5_IO04 */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08		0x40000006</div><div class='add'>+</div><div class='add'>+			/* CAN_INT# */</div><div class='add'>+			MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10		0x40000090</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_hog_panel: hog-panel-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* GRAPHICS_GPIO0_1V8 */</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07		0x26</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_hog_misc: hog-misc-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* ENET_WOL# -- shared by both PHYs */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10		0x40000090</div><div class='add'>+</div><div class='add'>+			/* PG_V_IN_VAR# */</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01		0x40000000</div><div class='add'>+			/* CSI2_PD_1V8 */</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08		0x0</div><div class='add'>+			/* CSI2_RESET_1V8# */</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09		0x0</div><div class='add'>+</div><div class='add'>+			/* DIS_USB_DN1 */</div><div class='add'>+			MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21		0x0</div><div class='add'>+			/* DIS_USB_DN2 */</div><div class='add'>+			MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22		0x0</div><div class='add'>+</div><div class='add'>+			/* EEPROM_WP_1V8# */</div><div class='add'>+			MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14		0x100</div><div class='add'>+			/* PCIE_CLK_GEN_CLKPWRGD_PD_1V8# */</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21		0x0</div><div class='add'>+			/* GRAPHICS_PRSNT_1V8# */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18		0x40000000</div><div class='add'>+</div><div class='add'>+			/* CLK_CCM_CLKO1_3V3 */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1		0x10</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_hog_sbc: hog-sbc-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* MEMCFG[0..2] straps */</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20		0x40000140</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03		0x40000140</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01		0x40000140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL			0x40000084</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA			0x40000084</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1_gpio: i2c1-gpio-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14		0x84</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15		0x84</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL			0x40000084</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA			0x40000084</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2_gpio: i2c2-gpio-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16		0x84</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17		0x84</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL			0x40000084</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA			0x40000084</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3_gpio: i2c3-gpio-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18		0x84</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19		0x84</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c5: i2c5-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL		0x40000084</div><div class='add'>+			MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA		0x40000084</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c5_gpio: i2c5-gpio-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26		0x84</div><div class='add'>+			MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27		0x84</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_panel_backlight: panel-backlight-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* BL_ENABLE_1V8 */</div><div class='add'>+			MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00		0x104</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_panel_expansion: panel-expansion-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* DSI_RESET_1V8# */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00		0x2</div><div class='add'>+			/* DSI_IRQ_1V8# */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19		0x40000090</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_panel_pwm: panel-pwm-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* BL_PWM_3V3 */</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SDA__PWM1_OUT			0x12</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_panel_vcc_reg: panel-vcc-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* TFT_ENABLE_1V8 */</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06		0x104</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie0: pcie-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* M2_PCIE_RST# */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05		0x2</div><div class='add'>+			/* M2_W_DISABLE1_1V8# */</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23		0x2</div><div class='add'>+			/* M2_W_DISABLE2_1V8# */</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24		0x2</div><div class='add'>+			/* CLK_M2_32K768 */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1		0x14</div><div class='add'>+			/* M2_PCIE_WAKE# */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06		0x40000140</div><div class='add'>+			/* M2_PCIE_CLKREQ# */</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B		0x61</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pdm: pdm-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* PDM_SEL */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09		0x0</div><div class='add'>+			MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_PDM_CLK		0x0</div><div class='add'>+			MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_PDM_BIT_STREAM00	0x0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: pmic-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* PMIC_nINT */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03		0x40000090</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm4: pwm4-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT		0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_rtc: rtc-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* RTC_IRQ# */</div><div class='add'>+			MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11		0x40000090</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai1: sai1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC	0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00	0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK	0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK	0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00	0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai2: sai2-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC	0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00	0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK	0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK	0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai3: sai3-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC	0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00	0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK	0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00	0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX		0x49</div><div class='add'>+			MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX		0x49</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA1__UART1_DCE_CTS		0x49</div><div class='add'>+			MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS		0x49</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA2__UART2_DCE_TX		0x49</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA3__UART2_DCE_RX		0x49</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS		0x49</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS		0x49</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: uart3-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX		0x49</div><div class='add'>+			MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX		0x49</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart4: uart4-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX		0x49</div><div class='add'>+			MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX		0x49</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x190</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x194</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x196</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19		0x20</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2-gpio-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12		0x40000080</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: usdhc3-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x190</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x190</div><div class='add'>+			MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x141</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x194</div><div class='add'>+			MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x141</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x196</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x196</div><div class='add'>+			MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x141</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usb_hub: usb-hub-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* USBHUB_RESET# */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01		0x4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usb1: usb1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR		0x6</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC		0x80</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_watchdog_gpio: watchdog-gpio-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* WDOG_B# */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B		0x26</div><div class='add'>+			/* WDOG_EN -- ungate WDT RESET# signal propagation */</div><div class='add'>+			MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05		0x6</div><div class='add'>+			/* WDOG_KICK# / WDI */</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08		0x26</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts b/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts<br/>new file mode 100644<br/>index 000000000000..9422beee30b2<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts</a></div><div class='hunk'>@@ -0,0 +1,584 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2019 NXP</div><div class='add'>+ * Copyright 2022 Ideas on Board Oy</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/usb/pd.h&gt;</div><div class='add'>+</div><div class='add'>+#include "imx8mp.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Polyhex Debix Model A i.MX8MPlus board";</div><div class='add'>+	compatible = "polyhex,imx8mp-debix-model-a", "polyhex,imx8mp-debix", "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdmi-connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		label = "hdmi";</div><div class='add'>+		type = "a";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			hdmi_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_tx_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_led&gt;;</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			function = LED_FUNCTION_POWER;</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio3 16 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "on";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usdhc2_vmmc&gt;;</div><div class='add'>+		regulator-name = "VSD_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio2 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb_hub: regulator-usb-hub {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usb_hub&gt;;</div><div class='add'>+		regulator-name = "USB_HUB";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio4 26 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eqos {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_eqos&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@1 { /* RTL8211E */</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio4 18 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;20&gt;;</div><div class='add'>+			reset-deassert-us = &lt;200000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_pvi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hdmi&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@1 {</div><div class='add'>+			hdmi_tx_out: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_connector_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pmic@25 {</div><div class='add'>+		compatible = "nxp,pca9450c";</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;3 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			buck1: BUCK1 {</div><div class='add'>+				regulator-name = "BUCK1";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2187500&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck2: BUCK2 {</div><div class='add'>+				regulator-name = "BUCK2";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2187500&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+				nxp,dvs-run-voltage = &lt;950000&gt;;</div><div class='add'>+				nxp,dvs-standby-voltage = &lt;850000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck4: BUCK4 {</div><div class='add'>+				regulator-name = "BUCK4";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck5: BUCK5 {</div><div class='add'>+				regulator-name = "BUCK5";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck6: BUCK6 {</div><div class='add'>+				regulator-name = "BUCK6";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo1: LDO1 {</div><div class='add'>+				regulator-name = "LDO1";</div><div class='add'>+				regulator-min-microvolt = &lt;1600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo2: LDO2 {</div><div class='add'>+				regulator-name = "LDO2";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1150000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo3: LDO3 {</div><div class='add'>+				regulator-name = "LDO3";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo4: LDO4 {</div><div class='add'>+				regulator-name = "LDO4";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo5: LDO5 {</div><div class='add'>+				regulator-name = "LDO5";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	eeprom@50 {</div><div class='add'>+		compatible = "atmel,24c02";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rtc@51 {</div><div class='add'>+		compatible = "haoyu,hym8563";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-output-names = "xin32k";</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio2&gt;;</div><div class='add'>+		interrupts = &lt;11 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_rtc_int&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c6 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c6&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;snvs_pwrkey {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	/* console */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_1 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usb1&gt;;</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* 2.x hub on port 1 */</div><div class='add'>+	usb_hub_2_x: hub@1 {</div><div class='add'>+		compatible = "usbbda,5411";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;reg_usb_hub&gt;;</div><div class='add'>+		peer-hub = &lt;&amp;usb_hub_3_x&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* 3.x hub on port 2 */</div><div class='add'>+	usb_hub_3_x: hub@2 {</div><div class='add'>+		compatible = "usbbda,411";</div><div class='add'>+		reg = &lt;2&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;reg_usb_hub&gt;;</div><div class='add'>+		peer-hub = &lt;&amp;usb_hub_2_x&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SD Card */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* eMMC */</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_USDHC3&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_eqos: eqosgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x3</div><div class='add'>+			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x3</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL			0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL			0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN			0x1f</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT			0x1f</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18				0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio_led: gpioledgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16				0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_hdmi: hdmigrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL			0x1c3</div><div class='add'>+			MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA			0x1c3</div><div class='add'>+			MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD				0x19</div><div class='add'>+			MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC				0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL					0x400001c2</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA					0x400001c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL					0x400001c2</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA					0x400001c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL					0x400001c2</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA					0x400001c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4: i2c4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL					0x400001c3</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA					0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c6: i2c6grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL				0x400001c3</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA					0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: pmicirqgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03				0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19				0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usb_hub: regusbhubgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26				0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_rtc_int: rtcintgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11				0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX				0x14f</div><div class='add'>+			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX				0x14f</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: uart3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX				0x49</div><div class='add'>+			MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX				0x49</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart4: uart4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX				0x49</div><div class='add'>+			MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX				0x49</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usb1: usb1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR				0x10</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK				0x190</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD				0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0				0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1				0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2				0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3				0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK				0x194</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD				0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0				0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1				0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2				0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3				0x1d4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK				0x196</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD				0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0				0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1				0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2				0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3				0x1d6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12				0x1c4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK				0x190</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD				0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0				0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1				0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2				0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3				0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4				0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5				0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6				0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7				0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE				0x190</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK				0x194</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD				0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0				0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1				0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2				0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3				0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4				0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5				0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6				0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7				0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE				0x194</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK				0x196</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD				0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0				0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1				0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2				0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3				0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4				0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5				0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6				0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7				0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE				0x196</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B				0xc6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts b/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts<br/>new file mode 100644<br/>index 000000000000..04619a722906<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts</a></div><div class='hunk'>@@ -0,0 +1,574 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2019 NXP</div><div class='add'>+ * Copyright (C) 2023 Pengutronix, Marco Felsch &lt;kernel@pengutronix.de&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mp-debix-som-a.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Polyhex i.MX8MPlus Debix SOM A on BMB-08";</div><div class='add'>+	compatible = "polyhex,imx8mp-debix-som-a-bmb-08", "polyhex,imx8mp-debix-som-a",</div><div class='add'>+		     "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;eqos;</div><div class='add'>+		ethernet1 = &amp;fec;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdmi-connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		label = "hdmi";</div><div class='add'>+		type = "a";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			hdmi_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_tx_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_baseboard_vdd3v3: regulator-baseboard-vdd3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "BB_VDD3V3";</div><div class='add'>+		/* Required timings for ethernet phy's */</div><div class='add'>+		startup-delay-us = &lt;50000&gt;;</div><div class='add'>+		off-on-delay-us = &lt;110000&gt;;</div><div class='add'>+		gpio = &lt;&amp;expander0 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_baseboard_vdd5v0: regulator-baseboard-vdd5v0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-name = "BB_VDD5V";</div><div class='add'>+		gpio = &lt;&amp;expander0 9 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	regulator-som-vdd1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-name = "SOM_VDD1V8_SW";</div><div class='add'>+		gpio = &lt;&amp;expander0 12 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	regulator-som-vdd3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "SOM_VDD3V3_SW";</div><div class='add'>+		gpio = &lt;&amp;expander0 11 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_csi1_1v8: regulator-csi1-vdd1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-name = "CSI1_VDD1V8";</div><div class='add'>+		gpio = &lt;&amp;expander0 13 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		vin-supply = &lt;&amp;reg_baseboard_vdd3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_csi1_3v3: regulator-csi1-vdd3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "CSI1_VDD3V3";</div><div class='add'>+		gpio = &lt;&amp;expander0 14 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		vin-supply = &lt;&amp;reg_vdd5v0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_csi2_1v8: regulator-csi2-vdd1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_csi2_1v8&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-name = "CSI2_VDD1V8";</div><div class='add'>+		gpio = &lt;&amp;gpio3 21 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		vin-supply = &lt;&amp;reg_baseboard_vdd3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_csi2_3v3: regulator-csi2-vdd3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_csi2_3v3&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "CSI2_VDD3V3";</div><div class='add'>+		gpio = &lt;&amp;gpio4 25 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		vin-supply = &lt;&amp;reg_vdd5v0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	regulator-vbus-usb20 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-name = "USB20_5V";</div><div class='add'>+		gpio = &lt;&amp;expander1 14 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		vin-supply = &lt;&amp;reg_baseboard_vdd5v0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	regulator-vbus-usb30 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-name = "USB30_5V";</div><div class='add'>+		gpio = &lt;&amp;expander1 12 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		vin-supply = &lt;&amp;reg_baseboard_vdd5v0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vdd5v0: regulator-vdd5v0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-name = "VDD_5V";</div><div class='add'>+		gpio = &lt;&amp;expander0 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eqos {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_eqos&gt;;</div><div class='add'>+	nvmem-cells = &lt;&amp;ethmac1&gt;;</div><div class='add'>+	nvmem-cell-names = "mac-address";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@1 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio4 18 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;20000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;150000&gt;;</div><div class='add'>+			eee-broken-1000t;</div><div class='add'>+			realtek,clkout-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec&gt;;</div><div class='add'>+	nvmem-cells = &lt;&amp;ethmac2&gt;;</div><div class='add'>+	nvmem-cell-names = "mac-address";</div><div class='add'>+	phy-supply = &lt;&amp;reg_baseboard_vdd3v3&gt;;</div><div class='add'>+	phy-handle = &lt;&amp;ethphy1&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	fsl,magic-packet;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy1: ethernet-phy@1 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio4 19 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;20000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;150000&gt;;</div><div class='add'>+			eee-broken-1000t;</div><div class='add'>+			realtek,clkout-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan1&gt;;</div><div class='add'>+	xceiver-supply = &lt;&amp;reg_vdd5v0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan2&gt;;</div><div class='add'>+	xceiver-supply = &lt;&amp;reg_vdd5v0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexspi {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexspi0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash: flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;80000000&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;1&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_pvi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hdmi&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@1 {</div><div class='add'>+			hdmi_tx_out: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_connector_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	expander0: gpio@20 {</div><div class='add'>+		compatible = "nxp,pca9535";</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;0x02&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	expander1: gpio@23 {</div><div class='add'>+		compatible = "nxp,pca9535";</div><div class='add'>+		reg = &lt;0x23&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;0x02&gt;;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Since USB1 is bound to peripheral mode we need to ensure</div><div class='add'>+		 * that VBUS is turned off.</div><div class='add'>+		 */</div><div class='add'>+		usb30-otg-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;13 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+			line-name = "USB30_OTG_EN";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rtc@51 {</div><div class='add'>+		compatible = "haoyu,hym8563";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_rtc&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;3 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@52 {</div><div class='add'>+		compatible = "atmel,24c02";</div><div class='add'>+		reg = &lt;0x52&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		/* MACs stored in ASCII */</div><div class='add'>+		ethmac1: mac-address@0 {</div><div class='add'>+			reg = &lt;0x0 0xc&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ethmac2: mac-address@c {</div><div class='add'>+			reg = &lt;0xc 0xc&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;snvs_pwrkey {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Debug */</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_0 {</div><div class='add'>+	dr_mode = "peripheral";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_1 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* 2.x hub on port 1 */</div><div class='add'>+	usb_hub_2_x: hub@1 {</div><div class='add'>+		compatible = "usb5e3,610";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;expander1 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;reg_vdd5v0&gt;;</div><div class='add'>+		peer-hub = &lt;&amp;usb_hub_3_x&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* 3.x hub on port 2 */</div><div class='add'>+	usb_hub_3_x: hub@2 {</div><div class='add'>+		compatible = "usb5e3,620";</div><div class='add'>+		reg = &lt;2&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;expander1 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;reg_vdd5v0&gt;;</div><div class='add'>+		peer-hub = &lt;&amp;usb_hub_2_x&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* µSD Card */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_USDHC2&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+	no-sdio;</div><div class='add'>+	no-mmc;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_eqos: eqosgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x3</div><div class='add'>+			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x3</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL			0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL			0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f</div><div class='add'>+</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN			0x1f</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18				0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec: fecgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x91</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x91</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x91</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x91</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x1f</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x1f</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x1f</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x1f</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x1f</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN    0x1f</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19		0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan1: flexcan1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX			0x154</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX			0x154</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan2: flexcan2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX			0x154</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX			0x154</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexspi0: flexspi0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK           0x1c2</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B        0x82</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00      0x82</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01      0x82</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02      0x82</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03      0x82</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_hdmi: hdmigrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL	0x1c3</div><div class='add'>+			MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA	0x1c3</div><div class='add'>+			MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD		0x19</div><div class='add'>+			MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC		0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL			0x400001c2</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA			0x400001c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4: i2c4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL			0x400001c3</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA			0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_rtc: rtcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03		0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: pmicgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03		0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_csi2_1v8: regcsi21v8grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21		0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_csi2_3v3: regcsi23v3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25		0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX		0x14f</div><div class='add'>+			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX		0x14f</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: uart3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX		0x49</div><div class='add'>+			MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX		0x49</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart4: uart4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX		0x49</div><div class='add'>+			MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX		0x49</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x190</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x194</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x196</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a.dtsi<br/>new file mode 100644<br/>index 000000000000..91094c227744<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-debix-som-a.dtsi</a></div><div class='hunk'>@@ -0,0 +1,307 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2019 NXP</div><div class='add'>+ * Copyright (C) 2023 Pengutronix, Marco Felsch &lt;kernel@pengutronix.de&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "imx8mp.dtsi"</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Polyhex i.MX8MPlus Debix SOM A";</div><div class='add'>+	compatible = "polyhex,imx8mp-debix-som-a", "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usdhc2_vmmc&gt;;</div><div class='add'>+		regulator-name = "VSD_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio2 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_led&gt;;</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			gpios = &lt;&amp;gpio3 16 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "on";</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pmic@25 {</div><div class='add'>+		compatible = "nxp,pca9450c";</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;3 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			buck1: BUCK1 {</div><div class='add'>+				regulator-name = "BUCK1";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2187500&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck2: BUCK2 {</div><div class='add'>+				regulator-name = "BUCK2";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2187500&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+				nxp,dvs-run-voltage = &lt;950000&gt;;</div><div class='add'>+				nxp,dvs-standby-voltage = &lt;850000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck4: BUCK4 {</div><div class='add'>+				regulator-name = "BUCK4";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck5: BUCK5 {</div><div class='add'>+				regulator-name = "BUCK5";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck6: BUCK6 {</div><div class='add'>+				regulator-name = "BUCK6";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo1: LDO1 {</div><div class='add'>+				regulator-name = "LDO1";</div><div class='add'>+				regulator-min-microvolt = &lt;1600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo2: LDO2 {</div><div class='add'>+				regulator-name = "LDO2";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1150000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo3: LDO3 {</div><div class='add'>+				regulator-name = "LDO3";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo4: LDO4 {</div><div class='add'>+				regulator-name = "LDO4";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo5: LDO5 {</div><div class='add'>+				regulator-name = "LDO5";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	adc@48 {</div><div class='add'>+		 compatible = "ti,ads1115";</div><div class='add'>+		 reg = &lt;0x48&gt;;</div><div class='add'>+		 #address-cells = &lt;1&gt;;</div><div class='add'>+		 #size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		 channel@4 {</div><div class='add'>+			 reg = &lt;4&gt;;</div><div class='add'>+			 ti,gain = &lt;1&gt;;</div><div class='add'>+			 ti,datarate = &lt;7&gt;;</div><div class='add'>+		 };</div><div class='add'>+</div><div class='add'>+		 channel@5 {</div><div class='add'>+			 reg = &lt;5&gt;;</div><div class='add'>+			 ti,gain = &lt;1&gt;;</div><div class='add'>+			 ti,datarate = &lt;7&gt;;</div><div class='add'>+		 };</div><div class='add'>+</div><div class='add'>+		 channel@6 {</div><div class='add'>+			 reg = &lt;6&gt;;</div><div class='add'>+			 ti,gain = &lt;1&gt;;</div><div class='add'>+			 ti,datarate = &lt;7&gt;;</div><div class='add'>+		 };</div><div class='add'>+</div><div class='add'>+		 channel@7 {</div><div class='add'>+			 reg = &lt;7&gt;;</div><div class='add'>+			 ti,gain = &lt;1&gt;;</div><div class='add'>+			 ti,datarate = &lt;7&gt;;</div><div class='add'>+		 };</div><div class='add'>+	 };</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;snvs_pwrkey {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* eMMC */</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_USDHC3&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_gpio_led: gpioledgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16		0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL			0x400001c2</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA			0x400001c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4: i2c4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL			0x400001c3</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA			0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: pmicgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03		0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19		0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x190</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x190</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x194</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x196</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x196</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B		0xc6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-drc02.dts b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-drc02.dts<br/>new file mode 100644<br/>index 000000000000..c6bf7fd91981<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-dhcom-drc02.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-dhcom-drc02.dts</a></div><div class='hunk'>@@ -0,0 +1,255 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2024 Marek Vasut &lt;marex@denx.de&gt;</div><div class='add'>+ *</div><div class='add'>+ * DHCOM iMX8MP variant:</div><div class='add'>+ * DHCM-iMX8ML8-C160-R204-F1638-SPI16-E2-CAN2-RTC-I-01D2</div><div class='add'>+ * DHCOM PCB number: 660-100 or newer</div><div class='add'>+ * DRC02 PCB number: 568-100 or newer</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/phy/phy-imx8-pcie.h&gt;</div><div class='add'>+#include "imx8mp-dhcom-som.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "DH electronics i.MX8M Plus DHCOM on DRC02";</div><div class='add'>+	compatible = "dh,imx8mp-dhcom-drc02", "dh,imx8mp-dhcom-som",</div><div class='add'>+		     "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart1;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eqos {	/* First ethernet */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_eqos_rmii&gt;;</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0f&gt;;</div><div class='add'>+	phy-mode = "rmii";</div><div class='add'>+</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL1_266M&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MP_SYS_PLL2_100M&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MP_SYS_PLL2_50M&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;0&gt;, &lt;100000000&gt;, &lt;50000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethphy0g {	/* Micrel KSZ9131RNXI */</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethphy0f {	/* SMSC LAN8740Ai */</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec {	/* Second ethernet */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec_rmii&gt;;</div><div class='add'>+	phy-handle = &lt;&amp;ethphy1f&gt;;</div><div class='add'>+	phy-mode = "rmii";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL1_266M&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MP_SYS_PLL2_100M&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MP_SYS_PLL2_50M&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MP_SYS_PLL2_50M&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;0&gt;, &lt;100000000&gt;, &lt;50000000&gt;, &lt;0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethphy1f {	/* SMSC LAN8740Ai */</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"DRC02-In1", "", "", "", "", "DHCOM-I", "DRC02-HW2", "DRC02-HW0",</div><div class='add'>+		"DHCOM-B", "DHCOM-A", "", "DHCOM-H", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "";</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * NOTE: On DRC02, the RS485_RX_En is controlled by a separate</div><div class='add'>+	 * GPIO line, however the i.MX8 UART driver assumes RX happens</div><div class='add'>+	 * during TX anyway and that it only controls drive enable DE</div><div class='add'>+	 * line. Hence, the RX is always enabled here.</div><div class='add'>+	 */</div><div class='add'>+	rs485-rx-en-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;13 0&gt;; /* GPIO Q */</div><div class='add'>+		line-name = "rs485-rx-en";</div><div class='add'>+		output-low;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio2 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"DHCOM-O", "DHCOM-N", "", "SOM-HW1", "", "", "", "",</div><div class='add'>+		"", "", "", "", "DRC02-In2", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio3 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "SOM-HW0", "",</div><div class='add'>+		"", "", "", "", "", "", "SOM-MEM0", "SOM-MEM1",</div><div class='add'>+		"SOM-MEM2", "SOM-HW2", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "SOM-HW1", "", "", "", "",</div><div class='add'>+		"", "", "", "DRC02-Out2", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio5 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"", "", "DHCOM-C", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "DHCOM-E", "DRC02-Out1",</div><div class='add'>+		"", "", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* No HS connector on this SoM variant, so no HDMI, PCIe and only USB HS. */</div><div class='add'>+&amp;hdmi_blk_ctrl {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_pvi {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx_phy {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	/* Resistive touch controller not populated on this one SoM variant. */</div><div class='add'>+	touchscreen@49 {</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;irqsteer_hdmi {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif3 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Console UART */</div><div class='add'>+&amp;pinctrl_uart1 {</div><div class='add'>+	fsl,pins = &lt;</div><div class='add'>+		/* No pull-ups on DRC02, enable in-SoC pull-ups */</div><div class='add'>+		MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX		0x149</div><div class='add'>+		MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX		0x149</div><div class='add'>+	&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_uart3 {</div><div class='add'>+	fsl,pins = &lt;</div><div class='add'>+		/* No pull-ups on DRC02, enable in-SoC pull-ups */</div><div class='add'>+		MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX		0x149</div><div class='add'>+		MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX		0x149</div><div class='add'>+	&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	/*</div><div class='add'>+	 * Due to the use of CAN2 the signals for CAN2 Tx and Rx are routed to</div><div class='add'>+	 * DHCOM UART1 RTS/CTS pins. Therefore this UART have to use DHCOM GPIOs</div><div class='add'>+	 * for RTS/CTS. So configure DHCOM GPIO I as RTS and GPIO M as CTS.</div><div class='add'>+	 */</div><div class='add'>+	/delete-property/ uart-has-rtscts;</div><div class='add'>+	cts-gpios = &lt;&amp;gpio5 5 GPIO_ACTIVE_HIGH&gt;; /* GPIO M */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1 &amp;pinctrl_dhcom_i &amp;pinctrl_dhcom_m&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	rts-gpios = &lt;&amp;gpio1 5 GPIO_ACTIVE_HIGH&gt;; /* GPIO I */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	/*</div><div class='add'>+	 * On DRC02 this UART is used as RS485 interface and RS485_TX_En is</div><div class='add'>+	 * controlled by DHCOM GPIO P. So remove RTS/CTS pins and the property</div><div class='add'>+	 * uart-has-rtscts from this UART and add the DHCOM GPIO P pin via</div><div class='add'>+	 * rts-gpios. The RS485_RX_En is controlled by DHCOM GPIO Q, see gpio1</div><div class='add'>+	 * node above.</div><div class='add'>+	 */</div><div class='add'>+	/delete-property/ uart-has-rtscts;</div><div class='add'>+	linux,rs485-enabled-at-boot-time;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3 &amp;pinctrl_dhcom_p &amp;pinctrl_dhcom_q&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	rts-gpios = &lt;&amp;gpio2 10 GPIO_ACTIVE_HIGH&gt;; /* GPIO P */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* No WiFi/BT chipset on this SoM variant. */</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	bluetooth {</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB_OTG port is not routed out on DRC02. */</div><div class='add'>+&amp;usb3_0 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_0 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB_HOST port has USB Hub connected to it, PWR/OC pins are unused */</div><div class='add'>+&amp;usb3_1 {</div><div class='add'>+	fsl,disable-port-power-control;</div><div class='add'>+	fsl,permanently-attached;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_1 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	maximum-speed = "high-speed";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* No WiFi/BT chipset on this SoM variant. */</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	/*</div><div class='add'>+	 * GPIO I is connected to UART1_RTS</div><div class='add'>+	 * GPIO M is connected to UART1_CTS</div><div class='add'>+	 * GPIO P is connected to RS485_TX_En</div><div class='add'>+	 * GPIO Q is connected to RS485_RX_En</div><div class='add'>+	 */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hog_base</div><div class='add'>+		     &amp;pinctrl_dhcom_a &amp;pinctrl_dhcom_b &amp;pinctrl_dhcom_c</div><div class='add'>+		     &amp;pinctrl_dhcom_d &amp;pinctrl_dhcom_e &amp;pinctrl_dhcom_f</div><div class='add'>+		     &amp;pinctrl_dhcom_g &amp;pinctrl_dhcom_h &amp;pinctrl_dhcom_j</div><div class='add'>+		     &amp;pinctrl_dhcom_k &amp;pinctrl_dhcom_l &amp;pinctrl_dhcom_n</div><div class='add'>+		     &amp;pinctrl_dhcom_o &amp;pinctrl_dhcom_r &amp;pinctrl_dhcom_s</div><div class='add'>+		     &amp;pinctrl_dhcom_int&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts<br/>new file mode 100644<br/>index 000000000000..3d18c964a22c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts</a></div><div class='hunk'>@@ -0,0 +1,269 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2022 Marek Vasut &lt;marex@denx.de&gt;</div><div class='add'>+ *</div><div class='add'>+ * DHCOM iMX8MP variant:</div><div class='add'>+ * DHCM-iMX8ML8-C160-R409-F1638-SPI16-GE-CAN2-SD-RTC-WBTA-ADC-T-RGB-CSI2-HS-I-01D2</div><div class='add'>+ * DHCOM PCB number: 660-100 or newer</div><div class='add'>+ * PDK2 PCB number: 516-400 or newer</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/phy/phy-imx8-pcie.h&gt;</div><div class='add'>+#include "imx8mp-dhcom-som.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "DH electronics i.MX8M Plus DHCOM Premium Developer Kit (2)";</div><div class='add'>+	compatible = "dh,imx8mp-dhcom-pdk2", "dh,imx8mp-dhcom-som",</div><div class='add'>+		     "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_ext_audio_codec: clock-codec {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		button-0 {</div><div class='add'>+			gpios = &lt;&amp;gpio1 9 GPIO_ACTIVE_LOW&gt;; /* GPIO A */</div><div class='add'>+			label = "TA1-GPIO-A";</div><div class='add'>+			linux,code = &lt;KEY_A&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_dhcom_a&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-1 {</div><div class='add'>+			gpios = &lt;&amp;gpio1 8 GPIO_ACTIVE_LOW&gt;; /* GPIO B */</div><div class='add'>+			label = "TA2-GPIO-B";</div><div class='add'>+			linux,code = &lt;KEY_B&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_dhcom_b&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-2 {</div><div class='add'>+			gpios = &lt;&amp;gpio5 2 GPIO_ACTIVE_LOW&gt;; /* GPIO C */</div><div class='add'>+			label = "TA3-GPIO-C";</div><div class='add'>+			linux,code = &lt;KEY_C&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_dhcom_c&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-3 {</div><div class='add'>+			gpios = &lt;&amp;gpio4 27 GPIO_ACTIVE_LOW&gt;; /* GPIO D */</div><div class='add'>+			label = "TA4-GPIO-D";</div><div class='add'>+			linux,code = &lt;KEY_D&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_dhcom_d&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdmi-connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		label = "X38";</div><div class='add'>+		type = "a";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			hdmi_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_tx_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	led {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+			function = LED_FUNCTION_INDICATOR;</div><div class='add'>+			function-enumerator = &lt;0&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio5 22 GPIO_ACTIVE_HIGH&gt;; /* GPIO E */</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_dhcom_e&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+			function = LED_FUNCTION_INDICATOR;</div><div class='add'>+			function-enumerator = &lt;1&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio5 23 GPIO_ACTIVE_HIGH&gt;; /* GPIO F */</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_dhcom_f&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-2 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+			function = LED_FUNCTION_INDICATOR;</div><div class='add'>+			function-enumerator = &lt;2&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio1 11 GPIO_ACTIVE_HIGH&gt;; /* GPIO H */</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_dhcom_h&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-3 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+			function = LED_FUNCTION_INDICATOR;</div><div class='add'>+			function-enumerator = &lt;3&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio1 5 GPIO_ACTIVE_HIGH&gt;; /* GPIO I */</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_dhcom_i&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3p3vdd: regulator-3p3vdd {	/* 3.3VDD */</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "3P3VDD";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,name = "SGTL5000-Card";</div><div class='add'>+		simple-audio-card,format = "i2s";</div><div class='add'>+		simple-audio-card,bitclock-master = &lt;&amp;codec_dai&gt;;</div><div class='add'>+		simple-audio-card,frame-master = &lt;&amp;codec_dai&gt;;</div><div class='add'>+		simple-audio-card,widgets = "Headphone", "Headphone Jack";</div><div class='add'>+		simple-audio-card,routing = "Headphone Jack", "HP_OUT";</div><div class='add'>+</div><div class='add'>+		cpu_dai: simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;sai3&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		codec_dai: simple-audio-card,codec {</div><div class='add'>+			sound-dai = &lt;&amp;sgtl5000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c5 {</div><div class='add'>+	sgtl5000: codec@a {</div><div class='add'>+		compatible = "fsl,sgtl5000";</div><div class='add'>+		reg = &lt;0x0a&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk_ext_audio_codec&gt;;</div><div class='add'>+		VDDA-supply = &lt;&amp;reg_3p3vdd&gt;;</div><div class='add'>+		VDDIO-supply = &lt;&amp;reg_vdd_3p3v_awo&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec {	/* Second ethernet */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec_rgmii&gt;;</div><div class='add'>+	phy-handle = &lt;&amp;ethphypdk&gt;;</div><div class='add'>+	phy-mode = "rgmii";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		ethphypdk: ethernet-phy@7 { /* KSZ 9021 */</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_ethphy1&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+			interrupts = &lt;3 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			max-speed = &lt;100&gt;;</div><div class='add'>+			reg = &lt;7&gt;;</div><div class='add'>+			reset-assert-us = &lt;1000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;1000&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio4 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			rxc-skew-ps = &lt;3000&gt;;</div><div class='add'>+			rxd0-skew-ps = &lt;0&gt;;</div><div class='add'>+			rxd1-skew-ps = &lt;0&gt;;</div><div class='add'>+			rxd2-skew-ps = &lt;0&gt;;</div><div class='add'>+			rxd3-skew-ps = &lt;0&gt;;</div><div class='add'>+			rxdv-skew-ps = &lt;0&gt;;</div><div class='add'>+			txc-skew-ps = &lt;3000&gt;;</div><div class='add'>+			txd0-skew-ps = &lt;0&gt;;</div><div class='add'>+			txd1-skew-ps = &lt;0&gt;;</div><div class='add'>+			txd2-skew-ps = &lt;0&gt;;</div><div class='add'>+			txd3-skew-ps = &lt;0&gt;;</div><div class='add'>+			txen-skew-ps = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_pvi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	ddc-i2c-bus = &lt;&amp;i2c5&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hdmi&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@1 {</div><div class='add'>+			hdmi_tx_out: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_connector_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	clock-names = "ref";</div><div class='add'>+	clocks = &lt;&amp;hsio_blk_ctrl&gt;;</div><div class='add'>+	fsl,clkreq-unsupported;</div><div class='add'>+	fsl,refclk-pad-mode = &lt;IMX8_PCIE_REFCLK_PAD_OUTPUT&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie {</div><div class='add'>+	fsl,max-link-speed = &lt;1&gt;;</div><div class='add'>+	reset-gpio = &lt;&amp;gpio1 6 GPIO_ACTIVE_LOW&gt;;	/* GPIO J */</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai3 {</div><div class='add'>+	#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai3&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_SAI3&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;12288000&gt;;</div><div class='add'>+	fsl,sai-mclk-direction-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_1 {</div><div class='add'>+	fsl,over-current-active-low;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	/*</div><div class='add'>+	 * GPIO_A,B,C,D are connected to buttons.</div><div class='add'>+	 * GPIO_E,F,H,I are connected to LEDs.</div><div class='add'>+	 * GPIO_M is connected to CLKOUT1.</div><div class='add'>+	 */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hog_base</div><div class='add'>+		     &amp;pinctrl_dhcom_g &amp;pinctrl_dhcom_j</div><div class='add'>+		     &amp;pinctrl_dhcom_k &amp;pinctrl_dhcom_l</div><div class='add'>+		     &amp;pinctrl_dhcom_int&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts<br/>new file mode 100644<br/>index 000000000000..ef012e8365b1<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts</a></div><div class='hunk'>@@ -0,0 +1,351 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2023 Marek Vasut &lt;marex@denx.de&gt;</div><div class='add'>+ *</div><div class='add'>+ * DHCOM iMX8MP variant:</div><div class='add'>+ * DHCM-iMX8ML8-C160-R409-F1638-SPI16-GE-CAN2-SD-RTC-WBTA-ADC-T-RGB-CSI2-HS-I-01D2</div><div class='add'>+ * DHCOM PCB number: 660-100 or newer</div><div class='add'>+ * PDK3 PCB number: 669-100 or newer</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/phy/phy-imx8-pcie.h&gt;</div><div class='add'>+#include "imx8mp-dhcom-som.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "DH electronics i.MX8M Plus DHCOM Premium Developer Kit (3)";</div><div class='add'>+	compatible = "dh,imx8mp-dhcom-pdk3", "dh,imx8mp-dhcom-som",</div><div class='add'>+		     "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_ext_audio_codec: clock-codec {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_xtal25: clock-xtal25 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;25000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		button-0 {</div><div class='add'>+			gpios = &lt;&amp;gpio1 9 GPIO_ACTIVE_LOW&gt;; /* GPIO A */</div><div class='add'>+			label = "TA1-GPIO-A";</div><div class='add'>+			linux,code = &lt;KEY_A&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_dhcom_a&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-1 {</div><div class='add'>+			gpios = &lt;&amp;gpio1 8 GPIO_ACTIVE_LOW&gt;; /* GPIO B */</div><div class='add'>+			label = "TA2-GPIO-B";</div><div class='add'>+			linux,code = &lt;KEY_B&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_dhcom_b&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-2 {</div><div class='add'>+			gpios = &lt;&amp;gpio5 2 GPIO_ACTIVE_LOW&gt;; /* GPIO C */</div><div class='add'>+			label = "TA3-GPIO-C";</div><div class='add'>+			linux,code = &lt;KEY_C&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_dhcom_c&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-3 {</div><div class='add'>+			gpios = &lt;&amp;gpio5 22 GPIO_ACTIVE_LOW&gt;; /* GPIO E */</div><div class='add'>+			label = "TA4-GPIO-E";</div><div class='add'>+			linux,code = &lt;KEY_E&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_dhcom_e&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdmi-connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		label = "X28";</div><div class='add'>+		type = "a";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			hdmi_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_tx_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	led {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+			function = LED_FUNCTION_INDICATOR;</div><div class='add'>+			function-enumerator = &lt;0&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio4 27 GPIO_ACTIVE_HIGH&gt;; /* GPIO D */</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_dhcom_d&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+			function = LED_FUNCTION_INDICATOR;</div><div class='add'>+			function-enumerator = &lt;1&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio5 23 GPIO_ACTIVE_HIGH&gt;; /* GPIO F */</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_dhcom_f&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-2 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+			function = LED_FUNCTION_INDICATOR;</div><div class='add'>+			function-enumerator = &lt;2&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio1 0 GPIO_ACTIVE_HIGH&gt;; /* GPIO G */</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_dhcom_g&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-3 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+			function = LED_FUNCTION_INDICATOR;</div><div class='add'>+			function-enumerator = &lt;3&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio1 5 GPIO_ACTIVE_HIGH&gt;; /* GPIO I */</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_dhcom_i&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3p3vdd: regulator-3p3vdd {	/* 3.3VDD */</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "3P3VDD";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,name = "SGTL5000-Card";</div><div class='add'>+		simple-audio-card,format = "i2s";</div><div class='add'>+		simple-audio-card,bitclock-master = &lt;&amp;codec_dai&gt;;</div><div class='add'>+		simple-audio-card,frame-master = &lt;&amp;codec_dai&gt;;</div><div class='add'>+		simple-audio-card,widgets = "Headphone", "Headphone Jack";</div><div class='add'>+		simple-audio-card,routing = "Headphone Jack", "HP_OUT";</div><div class='add'>+</div><div class='add'>+		cpu_dai: simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;sai3&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		codec_dai: simple-audio-card,codec {</div><div class='add'>+			sound-dai = &lt;&amp;sgtl5000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c5 {</div><div class='add'>+	i2c-mux@70 {</div><div class='add'>+		compatible = "nxp,pca9540";</div><div class='add'>+		reg = &lt;0x70&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		i2cmuxed0: i2c@0 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			sgtl5000: codec@a {</div><div class='add'>+				compatible = "fsl,sgtl5000";</div><div class='add'>+				reg = &lt;0x0a&gt;;</div><div class='add'>+				#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk_ext_audio_codec&gt;;</div><div class='add'>+				VDDA-supply = &lt;&amp;reg_3p3vdd&gt;;</div><div class='add'>+				VDDIO-supply = &lt;&amp;reg_vdd_3p3v_awo&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			csi2exp: gpio@24 {</div><div class='add'>+				compatible = "nxp,pca9570";</div><div class='add'>+				reg = &lt;0x24&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+				gpio-line-names =</div><div class='add'>+					"CSI2_#RESET", "CSI2_#PWDN",</div><div class='add'>+					"CSI_#PWDN", "CSI_#RESET";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			typec@3d {</div><div class='add'>+				compatible = "nxp,ptn5150";</div><div class='add'>+				reg = &lt;0x3d&gt;;</div><div class='add'>+				interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+				interrupts = &lt;25 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;pinctrl_ptn5150&gt;;</div><div class='add'>+</div><div class='add'>+				port {</div><div class='add'>+</div><div class='add'>+					ptn5150_out_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dwc3_0_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			power-sensor@40 {</div><div class='add'>+				compatible = "ti,ina238";</div><div class='add'>+				reg = &lt;0x40&gt;;</div><div class='add'>+				shunt-resistor = &lt;20000&gt;;	/* 0.02 R */</div><div class='add'>+				ti,shunt-gain = &lt;1&gt;;	/* Drop cca. 40mV */</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			eeprom_board: eeprom@54 {</div><div class='add'>+				compatible = "atmel,24c04";</div><div class='add'>+				pagesize = &lt;16&gt;;</div><div class='add'>+				reg = &lt;0x54&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pcieclk: clock@6b {</div><div class='add'>+				compatible = "skyworks,si52144";</div><div class='add'>+				reg = &lt;0x6b&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk_xtal25&gt;;</div><div class='add'>+				#clock-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2cmuxed1: i2c@1 {	/* HDMI DDC I2C */</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec {	/* Second ethernet */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec_rgmii&gt;;</div><div class='add'>+	phy-handle = &lt;&amp;ethphypdk&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		ethphypdk: ethernet-phy@7 { /* Micrel KSZ9131RNXI */</div><div class='add'>+			compatible = "ethernet-phy-id0022.1642",</div><div class='add'>+				     "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+			interrupts = &lt;3 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_ethphy1&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			reg = &lt;7&gt;;</div><div class='add'>+			reset-assert-us = &lt;1000&gt;;</div><div class='add'>+			/* RESET_N signal rise time ~100ms */</div><div class='add'>+			reset-deassert-us = &lt;120000&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio4 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_pvi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	ddc-i2c-bus = &lt;&amp;i2cmuxed1&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hdmi&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@1 {</div><div class='add'>+			hdmi_tx_out: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_connector_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	clocks = &lt;&amp;pcieclk 1&gt;;</div><div class='add'>+	clock-names = "ref";</div><div class='add'>+	fsl,refclk-pad-mode = &lt;IMX8_PCIE_REFCLK_PAD_INPUT&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie {</div><div class='add'>+	fsl,max-link-speed = &lt;3&gt;;</div><div class='add'>+	reset-gpio = &lt;&amp;gpio1 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai3&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_SAI3&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;12288000&gt;;</div><div class='add'>+	fsl,sai-mclk-direction-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_0 {</div><div class='add'>+	usb-role-switch;</div><div class='add'>+</div><div class='add'>+	port {</div><div class='add'>+		dwc3_0_ep: endpoint {</div><div class='add'>+			remote-endpoint = &lt;&amp;ptn5150_out_ep&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_1 {</div><div class='add'>+	fsl,disable-port-power-control;</div><div class='add'>+	fsl,permanently-attached;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_1 {</div><div class='add'>+	/* This port has USB5734 Hub connected to it, PWR/OC pins are unused */</div><div class='add'>+	/delete-property/ pinctrl-names;</div><div class='add'>+	/delete-property/ pinctrl-0;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	/*</div><div class='add'>+	 * GPIO_A,B,C,E are connected to buttons.</div><div class='add'>+	 * GPIO_D,F,G,I are connected to LEDs.</div><div class='add'>+	 * GPIO_H is connected to USB Hub RESET_N.</div><div class='add'>+	 * GPIO_M is connected to CLKOUT2.</div><div class='add'>+	 */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hog_base</div><div class='add'>+		     &amp;pinctrl_dhcom_h &amp;pinctrl_dhcom_j &amp;pinctrl_dhcom_k</div><div class='add'>+		     &amp;pinctrl_dhcom_l</div><div class='add'>+		     &amp;pinctrl_dhcom_int&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl_ptn5150: ptn5150grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25		0x40000000</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-picoitx.dts b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-picoitx.dts<br/>new file mode 100644<br/>index 000000000000..703cf0fb3d2b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-dhcom-picoitx.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-dhcom-picoitx.dts</a></div><div class='hunk'>@@ -0,0 +1,176 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2023-2024 Marek Vasut &lt;marex@denx.de&gt;</div><div class='add'>+ *</div><div class='add'>+ * DHCOM iMX8MP variant:</div><div class='add'>+ * DHCM-iMX8ML8-C160-R204-F1638-SPI16-E-SD-RTC-T-RGB-I-01D2</div><div class='add'>+ * DHCOM PCB number: 660-200 or newer</div><div class='add'>+ * PicoITX PCB number: 487-600 or newer</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include "imx8mp-dhcom-som.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "DH electronics i.MX8M Plus DHCOM PicoITX";</div><div class='add'>+	compatible = "dh,imx8mp-dhcom-picoitx", "dh,imx8mp-dhcom-som",</div><div class='add'>+		     "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	led {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_YELLOW&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+			function = LED_FUNCTION_INDICATOR;</div><div class='add'>+			gpios = &lt;&amp;gpio1 5 GPIO_ACTIVE_HIGH&gt;; /* GPIO I */</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_dhcom_i&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eqos {	/* First ethernet */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_eqos_rmii&gt;;</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0f&gt;;</div><div class='add'>+	phy-mode = "rmii";</div><div class='add'>+</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL1_266M&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MP_SYS_PLL2_100M&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MP_SYS_PLL2_50M&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;0&gt;, &lt;100000000&gt;, &lt;50000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethphy0g {	/* Micrel KSZ9131RNXI */</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethphy0f {	/* SMSC LAN8740Ai */</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"DHCOM-G", "", "", "",</div><div class='add'>+		"", "DHCOM-I", "PicoITX-HW0", "PicoITX-HW2",</div><div class='add'>+		"DHCOM-B", "DHCOM-A", "", "DHCOM-H", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio2 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "PicoITX-HW1", "", "", "", "",</div><div class='add'>+		"", "", "", "", "DHCOM-INT", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "SOM-HW1", "", "", "", "",</div><div class='add'>+		"", "", "", "PicoITX-Out2", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio5 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"", "", "PicoITX-In2", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "PicoITX-In1", "PicoITX-Out1",</div><div class='add'>+		"", "", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* No HS connector on this SoM variant, so no HDMI, PCIe and only USB HS. */</div><div class='add'>+&amp;hdmi_blk_ctrl {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_pvi {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx_phy {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;irqsteer_hdmi {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif3 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* No WiFi/BT chipset on this SoM variant. */</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	bluetooth {</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB_OTG port is not routed out on PicoITX. */</div><div class='add'>+&amp;usb3_0 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_0 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_1 {</div><div class='add'>+	fsl,over-current-active-low;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_1 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	maximum-speed = "high-speed";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* No WiFi/BT chipset on this SoM variant. */</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	/*</div><div class='add'>+	 * The following DHCOM GPIOs are used on this board.</div><div class='add'>+	 * Therefore, they have been removed from the list below.</div><div class='add'>+	 * I: yellow led</div><div class='add'>+	 */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_dhcom_a &amp;pinctrl_dhcom_b &amp;pinctrl_dhcom_c</div><div class='add'>+		     &amp;pinctrl_dhcom_d &amp;pinctrl_dhcom_e &amp;pinctrl_dhcom_f</div><div class='add'>+		     &amp;pinctrl_dhcom_g &amp;pinctrl_dhcom_h &amp;pinctrl_dhcom_j</div><div class='add'>+		     &amp;pinctrl_dhcom_k &amp;pinctrl_dhcom_l &amp;pinctrl_dhcom_m</div><div class='add'>+		     &amp;pinctrl_dhcom_n &amp;pinctrl_dhcom_o &amp;pinctrl_dhcom_p</div><div class='add'>+		     &amp;pinctrl_dhcom_q &amp;pinctrl_dhcom_r &amp;pinctrl_dhcom_s</div><div class='add'>+		     &amp;pinctrl_dhcom_int&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi<br/>new file mode 100644<br/>index 000000000000..68c2e0156a5c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi</a></div><div class='hunk'>@@ -0,0 +1,1206 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2021-2022 Marek Vasut &lt;marex@denx.de&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "imx8mp.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "DH electronics i.MX8M Plus DHCOM SoM";</div><div class='add'>+	compatible = "dh,imx8mp-dhcom-som", "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;eqos;</div><div class='add'>+		ethernet1 = &amp;fec;</div><div class='add'>+		rtc0 = &amp;rv3032;</div><div class='add'>+		rtc1 = &amp;snvs_rtc;</div><div class='add'>+		spi0 = &amp;flexspi;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		/* Memory size 512 MiB..8 GiB will be filled by U-Boot */</div><div class='add'>+		reg = &lt;0x0 0x40000000 0 0x08000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_eth_vio: regulator-eth-vio {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		gpio = &lt;&amp;ioexp 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "eth_vio";</div><div class='add'>+		vin-supply = &lt;&amp;buck4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;gpio2 19 0&gt;; /* SD2_RESET */</div><div class='add'>+		off-on-delay-us = &lt;12000&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usdhc2_vmmc&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "VDD_3V3_SD";</div><div class='add'>+		startup-delay-us = &lt;100&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;buck4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vdd_3p3v_awo: regulator-vdd-3p3v-awo {	/* VDD_3V3_AWO */</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "VDD_3P3V_AWO";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wlan_pwrseq: wifi-pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-simple";</div><div class='add'>+		reset-gpios = &lt;&amp;ioexp 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;audio_blk_ctrl {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_AUDIO_PLL1&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;393216000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi1&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 17 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi2&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 13 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eqos {	/* First ethernet */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_eqos_rgmii&gt;;</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0g&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		/* Up to one of these two PHYs may be populated. */</div><div class='add'>+		ethphy0f: ethernet-phy@1 { /* SMSC LAN8740Ai */</div><div class='add'>+			compatible = "ethernet-phy-id0007.c110",</div><div class='add'>+				     "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+			interrupts = &lt;19 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_ethphy0&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			reset-assert-us = &lt;1000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;1000&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;ioexp 4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			/* Non-default PHY population option. */</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ethphy0g: ethernet-phy@5 { /* Micrel KSZ9131RNXI */</div><div class='add'>+			compatible = "ethernet-phy-id0022.1642",</div><div class='add'>+				     "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+			interrupts = &lt;19 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			micrel,led-mode = &lt;0&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_ethphy0&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			reg = &lt;5&gt;;</div><div class='add'>+			reset-assert-us = &lt;1000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;1000&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;ioexp 4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			/* Default PHY population option. */</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec {	/* Second ethernet */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec_rmii&gt;;</div><div class='add'>+	phy-handle = &lt;&amp;ethphy1f&gt;;</div><div class='add'>+	phy-mode = "rmii";</div><div class='add'>+	fsl,magic-packet;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		/* Up to one PHY may be populated. */</div><div class='add'>+		ethphy1f: ethernet-phy@2 { /* SMSC LAN8740Ai */</div><div class='add'>+			compatible = "ethernet-phy-id0007.c110",</div><div class='add'>+				     "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+			interrupts = &lt;3 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_ethphy1&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			reg = &lt;2&gt;;</div><div class='add'>+			reset-assert-us = &lt;1000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;1000&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio4 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			/* Non-default PHY population option. */</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan1&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan2&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexspi {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexspi&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash@0 {	/* W25Q128JWPIM */</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;80000000&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;4&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"DHCOM-G", "", "", "", "", "DHCOM-I", "DHCOM-J", "DHCOM-L",</div><div class='add'>+		"DHCOM-B", "DHCOM-A", "", "DHCOM-H", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio2 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "DHCOM-K", "", "", "", "",</div><div class='add'>+		"", "", "", "", "DHCOM-INT", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio3 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "SOM-HW0", "",</div><div class='add'>+		"", "", "", "", "", "", "SOM-MEM0", "SOM-MEM1",</div><div class='add'>+		"SOM-MEM2", "SOM-HW2", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "SOM-HW1", "", "", "", "",</div><div class='add'>+		"", "", "", "DHCOM-D", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio5 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"", "", "DHCOM-C", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "DHCOM-E", "DHCOM-F",</div><div class='add'>+		"", "", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c3_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	tc_bridge: bridge@f {</div><div class='add'>+		compatible = "toshiba,tc9595", "toshiba,tc358767";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_tc9595&gt;;</div><div class='add'>+		reg = &lt;0xf&gt;;</div><div class='add'>+		clock-names = "ref";</div><div class='add'>+		clocks = &lt;&amp;clk IMX8MP_CLK_CLKOUT2&gt;;</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX8MP_CLK_CLKOUT2_SEL&gt;,</div><div class='add'>+				  &lt;&amp;clk IMX8MP_CLK_CLKOUT2&gt;,</div><div class='add'>+				  &lt;&amp;clk IMX8MP_AUDIO_PLL2_OUT&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;&amp;clk IMX8MP_AUDIO_PLL2_OUT&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;13000000&gt;, &lt;13000000&gt;, &lt;208000000&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio4 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				tc_bridge_in: endpoint {</div><div class='add'>+					data-lanes = &lt;1 2 3 4&gt;;</div><div class='add'>+					remote-endpoint = &lt;&amp;dsi_out&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmic: pmic@25 {</div><div class='add'>+		compatible = "nxp,pca9450c";</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;3 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * i.MX 8M Plus Data Sheet for Consumer Products</div><div class='add'>+		 * 3.1.4 Operating ranges</div><div class='add'>+		 * MIMX8ML8CVNKZAB</div><div class='add'>+		 */</div><div class='add'>+		regulators {</div><div class='add'>+			buck1: BUCK1 {	/* VDD_SOC (dual-phase with BUCK3) */</div><div class='add'>+				regulator-min-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck2: BUCK2 {	/* VDD_ARM */</div><div class='add'>+				nxp,dvs-run-voltage = &lt;950000&gt;;</div><div class='add'>+				nxp,dvs-standby-voltage = &lt;850000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck4: BUCK4 {	/* VDD_3V3 */</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck5: BUCK5 {	/* VDD_1V8 */</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck6: BUCK6 {	/* NVCC_DRAM_1V1 */</div><div class='add'>+				regulator-min-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo1: LDO1 {	/* NVCC_SNVS_1V8 */</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo3: LDO3 {	/* VDDA_1V8 */</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo4: LDO4 {	/* PMIC_LDO4 */</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo5: LDO5 {	/* NVCC_SD2 */</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	adc@48 {</div><div class='add'>+		compatible = "ti,ads1015";</div><div class='add'>+		reg = &lt;0x48&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;ioexp 7 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		channel@0 {	/* Voltage over AIN0 and AIN1. */</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		channel@1 {	/* Voltage over AIN0 and AIN3. */</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		channel@2 {	/* Voltage over AIN1 and AIN3. */</div><div class='add'>+			reg = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		channel@3 {	/* Voltage over AIN2 and AIN3. */</div><div class='add'>+			reg = &lt;3&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		channel@4 {	/* Voltage over AIN0 and GND. */</div><div class='add'>+			reg = &lt;4&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		channel@5 {	/* Voltage over AIN1 and GND. */</div><div class='add'>+			reg = &lt;5&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		channel@6 {	/* Voltage over AIN2 and GND. */</div><div class='add'>+			reg = &lt;6&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		channel@7 {	/* Voltage over AIN3 and GND. */</div><div class='add'>+			reg = &lt;7&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	touchscreen@49 {</div><div class='add'>+		compatible = "ti,tsc2004";</div><div class='add'>+		reg = &lt;0x49&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;gpio4 0 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_touch&gt;;</div><div class='add'>+		vio-supply = &lt;&amp;buck4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom0: eeprom@50 {	/* EEPROM with EQoS MAC address */</div><div class='add'>+		compatible = "atmel,24c32";	/* M24C32-D */</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rv3032: rtc@51 {</div><div class='add'>+		compatible = "microcrystal,rv3032";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;ioexp 3 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		wakeup-source;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom1: eeprom@53 {	/* EEPROM with FEC MAC address */</div><div class='add'>+		compatible = "atmel,24c32";	/* M24C32-D */</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		reg = &lt;0x53&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom0wl: eeprom@58 {</div><div class='add'>+		compatible = "atmel,24c32d-wl";	/* M24C32-D WL page of 0x50 */</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		reg = &lt;0x58&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom1wl: eeprom@5b {</div><div class='add'>+		compatible = "atmel,24c32d-wl";	/* M24C32-D WL page of 0x53 */</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		reg = &lt;0x5b&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ioexp: gpio@74 {</div><div class='add'>+		compatible = "nxp,pca9539";</div><div class='add'>+		reg = &lt;0x74&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;gpio3 20 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_ioexp&gt;;</div><div class='add'>+		wakeup-source;</div><div class='add'>+</div><div class='add'>+		gpio-line-names =</div><div class='add'>+			"BT_REG_EN", "WL_REG_EN", "VIO_SWITCHED_#EN", "RTC_#INT",</div><div class='add'>+			"ENET_QOS_#RST", "RGB_OSZ_ENABLE", "USB1_ID", "ADC_ALTER_RDY",</div><div class='add'>+			"DHCOM-W", "DHCOM-V", "DHCOM-U", "DHCOM-T",</div><div class='add'>+			"BT_HOST_WAKE", "BT_DEV_WAKE", "", "";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c4&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c4_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c5 {	/* HDMI EDID bus */</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c5&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c5_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_dsi {</div><div class='add'>+	samsung,burst-clock-frequency = &lt;160000000&gt;;</div><div class='add'>+	samsung,esc-clock-frequency = &lt;10000000&gt;;</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			dsi_out: endpoint {</div><div class='add'>+				data-lanes = &lt;1 2 3 4&gt;;</div><div class='add'>+				remote-endpoint = &lt;&amp;tc_bridge_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm1&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	/* CA53 console */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+	wakeup-source;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	/* Bluetooth */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * PLL1 at 80 MHz supplies UART2 root with 80 MHz clock,</div><div class='add'>+	 * which with 16x oversampling yields 5 Mbdps baud base,</div><div class='add'>+	 * which can be well divided by 5/4 to achieve 4 Mbdps,</div><div class='add'>+	 * which is exactly the maximum rate supported by muRata</div><div class='add'>+	 * 2AE bluetooth UART.</div><div class='add'>+	 */</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_UART2&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL1_80M&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;80000000&gt;;</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "cypress,cyw4373a0-bt";</div><div class='add'>+		shutdown-gpios = &lt;&amp;ioexp 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		max-speed = &lt;4000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_0 {</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usb1_vbus&gt;;</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SDIO WiFi */</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1_200mhz&gt;;</div><div class='add'>+	mmc-pwrseq = &lt;&amp;wlan_pwrseq&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;buck4&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	cap-power-off-card;</div><div class='add'>+	keep-power-in-suspend;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	brcmf: wifi@1 {	/* muRata 2AE */</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		compatible = "cypress,cyw4373-fmac", "brcm,bcm4329-fmac";</div><div class='add'>+		/*</div><div class='add'>+		 * The "host-wake" interrupt output is by default not</div><div class='add'>+		 * connected to the SoC, but can be connected on to</div><div class='add'>+		 * SoC pin on the carrier board.</div><div class='add'>+		 */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SD slot */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;ldo5&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* eMMC */</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;buck4&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;buck5&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hog_base</div><div class='add'>+		     &amp;pinctrl_dhcom_a &amp;pinctrl_dhcom_b &amp;pinctrl_dhcom_c</div><div class='add'>+		     &amp;pinctrl_dhcom_d &amp;pinctrl_dhcom_e &amp;pinctrl_dhcom_f</div><div class='add'>+		     &amp;pinctrl_dhcom_g &amp;pinctrl_dhcom_h &amp;pinctrl_dhcom_i</div><div class='add'>+		     &amp;pinctrl_dhcom_j &amp;pinctrl_dhcom_k &amp;pinctrl_dhcom_l</div><div class='add'>+		     &amp;pinctrl_dhcom_m &amp;pinctrl_dhcom_n &amp;pinctrl_dhcom_o</div><div class='add'>+		     &amp;pinctrl_dhcom_p &amp;pinctrl_dhcom_q &amp;pinctrl_dhcom_r</div><div class='add'>+		     &amp;pinctrl_dhcom_s &amp;pinctrl_dhcom_int&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	pinctrl_dhcom_a: dhcom-a-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* ENET_QOS_EVENT0-OUT */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09		0x2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_dhcom_b: dhcom-b-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* ENET_QOS_EVENT0-IN */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08		0x2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_dhcom_c: dhcom-c-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* GPIO_C */</div><div class='add'>+			MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02		0x2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_dhcom_d: dhcom-d-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* GPIO_D */</div><div class='add'>+			MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27		0x2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_dhcom_e: dhcom-e-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* GPIO_E */</div><div class='add'>+			MX8MP_IOMUXC_UART1_RXD__GPIO5_IO22		0x2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_dhcom_f: dhcom-f-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* GPIO_F */</div><div class='add'>+			MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23		0x2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_dhcom_g: dhcom-g-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* GPIO_G */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00		0x2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_dhcom_h: dhcom-h-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* GPIO_H */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11		0x2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_dhcom_i: dhcom-i-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* CSI1_SYNC */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05		0x2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_dhcom_j: dhcom-j-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* CSIx_#RST */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06		0x2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_dhcom_k: dhcom-k-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* CSIx_PWDN */</div><div class='add'>+			MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11		0x2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_dhcom_l: dhcom-l-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* CSI2_SYNC */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07		0x2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_dhcom_m: dhcom-m-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* CSIx_MCLK */</div><div class='add'>+			MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05		0x2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_dhcom_n: dhcom-n-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* CSI2_D3- */</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09		0x2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_dhcom_o: dhcom-o-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* CSI2_D3+ */</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08		0x2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_dhcom_p: dhcom-p-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* CSI2_D2- */</div><div class='add'>+			MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10		0x2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_dhcom_q: dhcom-q-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* CSI2_D2+ */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13		0x2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_dhcom_r: dhcom-r-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* CSI2_D1- */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12		0x2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_dhcom_s: dhcom-s-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* CSI2_D1+ */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10		0x2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_dhcom_int: dhcom-int-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* INT_HIGHEST_PRIO */</div><div class='add'>+			MX8MP_IOMUXC_SD2_WP__GPIO2_IO20			0x2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_hog_base: dhcom-hog-base-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* GPIOs for memory coding */</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22		0x40000080</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23		0x40000080</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24		0x40000080</div><div class='add'>+			/* GPIOs for hardware coding */</div><div class='add'>+			MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14		0x40000080</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19		0x40000080</div><div class='add'>+			MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25		0x40000080</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi1: dhcom-ecspi1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SCL__ECSPI1_SCLK		0x44</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SDA__ECSPI1_MOSI		0x44</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SCL__ECSPI1_MISO		0x44</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17		0x40</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi2: dhcom-ecspi2-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK		0x44</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI		0x44</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO		0x44</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13		0x40</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_eqos_rgmii: dhcom-eqos-rgmii-grp {	/* RGMII */</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC		0x3</div><div class='add'>+			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO		0x3</div><div class='add'>+			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL	0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0	0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1	0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2	0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3	0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL	0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0	0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1	0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2	0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3	0x91</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_eqos_rmii: dhcom-eqos-rmii-grp {	/* RMII */</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC		0x3</div><div class='add'>+			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO		0x3</div><div class='add'>+			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL	0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0	0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1	0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_RXC__ENET_QOS_RX_ER		0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL	0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0	0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1	0x91</div><div class='add'>+			/* Clock */</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK	0x4000001f</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ethphy0: dhcom-ethphy0-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* ENET_QOS_#INT Interrupt */</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19		0x22</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ethphy1: dhcom-ethphy1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* ENET1_#RST Reset */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02		0x11</div><div class='add'>+			/* ENET1_#INT Interrupt */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03		0x11</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec_rgmii: dhcom-fec-rgmii-grp {	/* RGMII */</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK		0x1f</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x91</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x91</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x91</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x91</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x1f</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x1f</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x1f</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x1f</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x1f</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER		0x1f</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec_rmii: dhcom-fec-rmii-grp {	/* RMII */</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x91</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x91</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER		0x91</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x1f</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x1f</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f</div><div class='add'>+			/* Clock */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK		0x4000001f</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan1: dhcom-flexcan1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SPDIF_RX__CAN1_RX			0x154</div><div class='add'>+			MX8MP_IOMUXC_SPDIF_TX__CAN1_TX			0x154</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan2: dhcom-flexcan2-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART3_RXD__CAN2_TX			0x154</div><div class='add'>+			MX8MP_IOMUXC_UART3_TXD__CAN2_RX			0x154</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexspi: dhcom-flexspi-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK		0x1c2</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B	0x82</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00	0x82</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01	0x82</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02	0x82</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03	0x82</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_hdmi: dhcom-hdmi-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC		0x154</div><div class='add'>+			MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD		0x154</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: dhcom-i2c3-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL			0x40000084</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA			0x40000084</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3_gpio: dhcom-i2c3-gpio-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18		0x84</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19		0x84</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4: dhcom-i2c4-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL			0x40000084</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA			0x40000084</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4_gpio: dhcom-i2c4-gpio-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20		0x84</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21		0x84</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c5: dhcom-i2c5-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL		0x40000084</div><div class='add'>+			MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA		0x40000084</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c5_gpio: dhcom-i2c5-gpio-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26		0x84</div><div class='add'>+			MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27		0x84</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ioexp: dhcom-ioexp-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* #GPIO_EXP_INT */</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20		0x22</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: dhcom-pmic-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* PMIC_nINT */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03		0x40000090</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm1: dhcom-pwm1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT		0x6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_tc9595: dhcom-tc9595-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* RESET_DSIBRIDGE */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01		0x40000146</div><div class='add'>+			/* DSI-CONV_INT Interrupt */</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21		0x141</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai3: dhcom-sai3-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC	0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK	0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00	0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00	0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_touch: dhcom-touch-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* #TOUCH_INT */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00		0x40000080</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: dhcom-uart1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* Console UART */</div><div class='add'>+			MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX		0x49</div><div class='add'>+			MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX		0x49</div><div class='add'>+			MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS		0x49</div><div class='add'>+			MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS		0x49</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: dhcom-uart2-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* Bluetooth UART */</div><div class='add'>+			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX		0x49</div><div class='add'>+			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX		0x49</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS		0x49</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS		0x49</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: dhcom-uart3-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX		0x49</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX		0x49</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS		0x49</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS		0x49</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart4: dhcom-uart4-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX		0x49</div><div class='add'>+			MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX		0x49</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usb1_vbus: dhcom-usb1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR		0x6</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC		0x80</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: dhcom-usdhc1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x190</div><div class='add'>+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_100mhz: dhcom-usdhc1-100mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x194</div><div class='add'>+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_200mhz: dhcom-usdhc1-200mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x196</div><div class='add'>+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: dhcom-usdhc2-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x190</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: dhcom-usdhc2-100mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x194</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: dhcom-usdhc2-200mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x196</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_vmmc: dhcom-usdhc2-vmmc-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19		0x20</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: dhcom-usdhc2-gpio-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12		0x40000080</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: dhcom-usdhc3-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x190</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x190</div><div class='add'>+			MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x141</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: dhcom-usdhc3-100mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x194</div><div class='add'>+			MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x141</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: dhcom-usdhc3-200mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x196</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x196</div><div class='add'>+			MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x141</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: dhcom-wdog-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B		0xc6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-edm-g-wb.dts b/arch/arm64/boot/dts/freescale/imx8mp-edm-g-wb.dts<br/>new file mode 100644<br/>index 000000000000..138f21e257aa<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-edm-g-wb.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-edm-g-wb.dts</a></div><div class='hunk'>@@ -0,0 +1,359 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 TechNexion Ltd.</div><div class='add'>+ *</div><div class='add'>+ * Author: Ray Chang &lt;ray.chang@technexion.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/phy/phy-imx8-pcie.h&gt;</div><div class='add'>+#include "imx8mp-edm-g.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "technexion,edm-g-imx8mp-wb", "technexion,edm-g-imx8mp", "fsl,imx8mp";</div><div class='add'>+	model = "TechNexion EDM-G-IMX8MP SOM on WB-EDM-G";</div><div class='add'>+</div><div class='add'>+	connector {</div><div class='add'>+		compatible = "usb-c-connector";</div><div class='add'>+		data-role = "dual";</div><div class='add'>+		label = "USB-C";</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				hs_ep: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;usb3_hs_ep&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				ss_ep: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;hd3ss3220_in_ep&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdmi-connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		label = "HDMI OUT";</div><div class='add'>+		type = "a";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			hdmi_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_tx_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led {</div><div class='add'>+			default-state = "on";</div><div class='add'>+			gpios = &lt;&amp;expander2 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			label = "gpio-led";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_refclk: clock-pcie-ref {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;100000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_pwr_3v3: regulator-pwr-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "pwr-3v3";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_pwr_5v: regulator-pwr-5v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-name = "pwr-5v";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-hdmi {</div><div class='add'>+		compatible = "fsl,imx-audio-hdmi";</div><div class='add'>+		audio-cpu = &lt;&amp;aud2htx&gt;;</div><div class='add'>+		hdmi-out;</div><div class='add'>+		model = "audio-hdmi";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-wm8960 {</div><div class='add'>+		compatible = "fsl,imx-audio-wm8960";</div><div class='add'>+		audio-asrc = &lt;&amp;easrc&gt;;</div><div class='add'>+		audio-codec = &lt;&amp;wm8960&gt;;</div><div class='add'>+		audio-cpu = &lt;&amp;sai3&gt;;</div><div class='add'>+		audio-routing = "Headphone Jack", "HP_L",</div><div class='add'>+			"Headphone Jack", "HP_R",</div><div class='add'>+			"Ext Spk", "SPK_LP",</div><div class='add'>+			"Ext Spk", "SPK_LN",</div><div class='add'>+			"Ext Spk", "SPK_RP",</div><div class='add'>+			"Ext Spk", "SPK_RN",</div><div class='add'>+			"LINPUT1", "Mic Jack",</div><div class='add'>+			"LINPUT1", "Mic Jack",</div><div class='add'>+			"Mic Jack", "MICB";</div><div class='add'>+		model = "wm8960-audio";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;aud2htx {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;easrc {</div><div class='add'>+	fsl,asrc-rate  = &lt;48000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"", "", "", "", "", "", "DSI_RST", "",</div><div class='add'>+		"", "", "", "", "", "PCIE_CLKREQ_N", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"", "", "", "", "", "", "GPIO_P249", "GPIO_P251",</div><div class='add'>+		"", "GPIO_P255", "", "", "", "", "", "",</div><div class='add'>+		"DSI_BL_EN", "DSI_VDDEN", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio4&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_pvi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hdmi&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@1 {</div><div class='add'>+			hdmi_tx_out: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	wm8960: audio-codec@1a {</div><div class='add'>+		compatible = "wlf,wm8960";</div><div class='add'>+		reg = &lt;0x1a&gt;;</div><div class='add'>+		clocks = &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1&gt;;</div><div class='add'>+		clock-names = "mclk";</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		AVDD-supply = &lt;&amp;reg_pwr_3v3&gt;;</div><div class='add'>+		DBVDD-supply = &lt;&amp;reg_pwr_3v3&gt;;</div><div class='add'>+		DCVDD-supply = &lt;&amp;reg_pwr_3v3&gt;;</div><div class='add'>+		SPKVDD1-supply = &lt;&amp;reg_pwr_5v&gt;;</div><div class='add'>+		SPKVDD2-supply = &lt;&amp;reg_pwr_5v&gt;;</div><div class='add'>+		wlf,gpio-cfg = &lt;1 2&gt;;</div><div class='add'>+		wlf,hp-cfg = &lt;2 2 3&gt;;</div><div class='add'>+		wlf,shared-lrclk;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	expander1: gpio@21 {</div><div class='add'>+		compatible = "nxp,pca9555";</div><div class='add'>+		reg = &lt;0x21&gt;;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		gpio-line-names = "EXPOSURE_TRIG_IN1", "FLASH_OUT1",</div><div class='add'>+				  "INFO_TRIG_IN1", "CAM_SHUTTER1", "XVS1",</div><div class='add'>+				  "PWR1_TIME0", "PWR1_TIME1", "PWR1_TIME2",</div><div class='add'>+				  "EXPOSURE_TRIG_IN2", "FLASH_OUT2",</div><div class='add'>+				  "INFO_TRIG_IN2", "CAM_SHUTTER2", "XVS2",</div><div class='add'>+				  "PWR2_TIME0", "PWR2_TIME1", "PWR2_TIME2";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	expander2: gpio@23 {</div><div class='add'>+		compatible = "nxp,pca9555";</div><div class='add'>+		reg = &lt;0x23&gt;;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;11 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		gpio-line-names = "M2_DISABLE_N", "LED_EN", "", "",</div><div class='add'>+				  "", "", "", "USB_OTG_OC",</div><div class='add'>+				  "EXT_GPIO8", "EXT_GPIO9", "", "",</div><div class='add'>+				  "", "CSI1_PDB", "CSI2_PDB", "PD_FAULT";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_expander2_irq&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb_typec: usb-typec@67 {</div><div class='add'>+		compatible = "ti,hd3ss3220";</div><div class='add'>+		reg = &lt;0x67&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;8 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_hd3ss3220_irq&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				hd3ss3220_in_ep: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;ss_ep&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				hd3ss3220_out_ep: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;usb3_role_switch&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c_0 {</div><div class='add'>+	eeprom2: eeprom@51 {</div><div class='add'>+		compatible = "atmel,24c02";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	clocks = &lt;&amp;pcie0_refclk&gt;;</div><div class='add'>+	clock-names = "ref";</div><div class='add'>+	fsl,clkreq-unsupported;</div><div class='add'>+	fsl,refclk-pad-mode = &lt;IMX8_PCIE_REFCLK_PAD_INPUT&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_0 {</div><div class='add'>+	/* dual role is implemented but not a full featured OTG */</div><div class='add'>+	adp-disable;</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	hnp-disable;</div><div class='add'>+	role-switch-default-mode = "peripheral";</div><div class='add'>+	srp-disable;</div><div class='add'>+	usb-role-switch;</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		port@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			usb3_hs_ep: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hs_ep&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			usb3_role_switch: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hd3ss3220_out_ep&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_1 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_expander2_irq: expander2-irqgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11		0x140 /* GPIO_P247 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio1: gpio1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06		0x16 /* DSI_RST */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio4: gpio4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD4__GPIO4_IO06		0x16 /* GPIO_P249 */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD5__GPIO4_IO07		0x16 /* GPIO_P251 */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD7__GPIO4_IO09		0x16 /* GPIO_P255 */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16		0x16 /* DSI_BL_EN */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD5__GPIO4_IO17		0x16 /* DSI_VDDEN */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_hd3ss3220_irq: hd3ss3220-irqgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08		0x41 /* GPIO_P253 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_hdmi: hdmigrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL	0x1c2</div><div class='add'>+			MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA	0x1c2</div><div class='add'>+			MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC		0x10</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-edm-g.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-edm-g.dtsi<br/>new file mode 100644<br/>index 000000000000..3f1e0837f349<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-edm-g.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-edm-g.dtsi</a></div><div class='hunk'>@@ -0,0 +1,786 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 TechNexion Ltd.</div><div class='add'>+ *</div><div class='add'>+ * Author: Ray Chang &lt;ray.chang@technexion.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "imx8mp.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c_0: i2c {</div><div class='add'>+		compatible = "i2c-gpio";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;100000&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_i2c_brd_conf&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		scl-gpios = &lt;&amp;gpio4 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+		sda-gpios = &lt;&amp;gpio4 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+</div><div class='add'>+		eeprom: eeprom@53 {</div><div class='add'>+			compatible = "atmel,24c02";</div><div class='add'>+			reg = &lt;0x53&gt;;</div><div class='add'>+			pagesize = &lt;16&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		reg = &lt;0x0 0x40000000 0 0xc0000000&gt;,</div><div class='add'>+		      &lt;0x1 0x00000000 0 0xc0000000&gt;;</div><div class='add'>+		device_type = "memory";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		off-on-delay-us = &lt;12000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "VSD_3V3";</div><div class='add'>+		startup-delay-us = &lt;100&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio2 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rfkill {</div><div class='add'>+		compatible = "rfkill-gpio";</div><div class='add'>+		name = "rfkill";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_bt_ctrl&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		radio-type = "bluetooth";</div><div class='add'>+		shutdown-gpios = &lt;&amp;gpio1 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wl_reg_on: regulator-wl-reg-on {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		off-on-delay-us = &lt;20000&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_wifi_ctrl&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "WL_REG_ON";</div><div class='add'>+		startup-delay-us = &lt;100&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio1 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi1 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	num-cs = &lt;1&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi1 &amp;pinctrl_ecspi1_cs&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eqos {</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_eqos&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	snps,force_thresh_dma_mode;</div><div class='add'>+	snps,mtl-rx-config = &lt;&amp;mtl_rx_setup&gt;;</div><div class='add'>+	snps,mtl-tx-config = &lt;&amp;mtl_tx_setup&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@1 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			eee-broken-1000t;</div><div class='add'>+			reset-assert-us = &lt;35000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;75000&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio1 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			realtek,clkout-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mtl_rx_setup: rx-queues-config {</div><div class='add'>+		snps,rx-queues-to-use = &lt;5&gt;;</div><div class='add'>+</div><div class='add'>+		queue0 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,map-to-dma-channel = &lt;0&gt;;</div><div class='add'>+			snps,priority = &lt;0x1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue1 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,map-to-dma-channel = &lt;1&gt;;</div><div class='add'>+			snps,priority = &lt;0x2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue2 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,map-to-dma-channel = &lt;2&gt;;</div><div class='add'>+			snps,priority = &lt;0x4&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue3 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,map-to-dma-channel = &lt;3&gt;;</div><div class='add'>+			snps,priority = &lt;0x8&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue4 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,map-to-dma-channel = &lt;4&gt;;</div><div class='add'>+			snps,priority = &lt;0xf0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mtl_tx_setup: tx-queues-config {</div><div class='add'>+		snps,tx-queues-to-use = &lt;5&gt;;</div><div class='add'>+</div><div class='add'>+		queue0 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue1 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue2 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x4&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue3 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x8&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue4 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0xf0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan1&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan2 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan2&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pmic: pmic@25 {</div><div class='add'>+		compatible = "nxp,pca9450c";</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;3 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			BUCK1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;720000&gt;;</div><div class='add'>+				regulator-name = "BUCK1";</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_arm: BUCK2 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1025000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;720000&gt;;</div><div class='add'>+				regulator-name = "BUCK2";</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+				nxp,dvs-run-voltage = &lt;950000&gt;;</div><div class='add'>+				nxp,dvs-standby-voltage = &lt;850000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			BUCK4 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;3600000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;3000000&gt;;</div><div class='add'>+				regulator-name = "BUCK4";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_buck5: BUCK5 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1950000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1650000&gt;;</div><div class='add'>+				regulator-name = "BUCK5";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			BUCK6 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1155000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1045000&gt;;</div><div class='add'>+				regulator-name = "BUCK6";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			LDO1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1950000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1650000&gt;;</div><div class='add'>+				regulator-name = "LDO1";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			LDO3 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1890000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1710000&gt;;</div><div class='add'>+				regulator-name = "LDO3";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			LDO5 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "LDO5";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	/* I2C_B on EDMG */</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	/* I2C_A on EDMG */</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c4&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c5 {</div><div class='add'>+	/* I2C_C on EDMG */</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c5&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	reset-gpio = &lt;&amp;gpio1 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm1&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm2 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm2&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm3 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm3&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm4 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm4&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai2 {</div><div class='add'>+	/* AUD_B on EDMG */</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_SAI2&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;12288000&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai2&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	fsl,sai-mclk-direction-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai3 {</div><div class='add'>+	/* AUD_A on EDMG */</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_SAI3&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;12288000&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai3&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	fsl,sai-mclk-direction-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	/* BT */</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_UART1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL1_80M&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	/* UART_A on EDMG, console */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	/* UART_C on EDMG */</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_UART3&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL1_80M&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	/* UART_B on EDMG */</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_UART4&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL1_80M&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart4&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	/* WIFI SDIO */</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_USDHC1&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;200000000&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	keep-power-in-suspend;</div><div class='add'>+	non-removable;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1_200mhz&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	vmmc-supply = &lt;&amp;wl_reg_on&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	/* SD card on baseboard */</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_USDHC2&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	/* eMMC on SOM */</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_USDHC3&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hog&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	pinctrl_bt_ctrl: bt-ctrlgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05	0x41 /* BT_REG_ON */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19	0x41 /* BT_WAKE_HOST */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi1_cs: ecspi1csgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09	0x40000</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi1: ecspi1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK	0x82</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI	0x82</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO	0x82</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_eqos: eqosgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC			0x3</div><div class='add'>+			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO			0x23</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0		0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1		0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2		0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3		0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0		0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1		0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2		0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3		0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09			0x19</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12			0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan1: flexcan1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX		0x154</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX		0x154</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan2: flexcan2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX		0x154</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX		0x154</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_hog: hoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD	0x40000019</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001a3</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001a3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001a3</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA		0x400001a3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400001c3</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4: i2c4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL		0x400001c3</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c5: i2c5grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL		0x400001a3</div><div class='add'>+			MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA		0x400001a3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c_brd_conf: i2cbrdconfgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28	0x1c3 /* BRD_CONF_SCL, bitbang */</div><div class='add'>+			MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29	0x1c3 /* BRD_CONF_SDA, bitbang */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie: pciegrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13	0x41 /* PCIE CLKREQ */</div><div class='add'>+			MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21	0x41 /* PCIE WAKE */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01	0x41 /* PCIE RST */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: pmicirqgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm1: pwm1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT	0x116</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm2: pwm2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT	0x116</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm3: pwm3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT		0x116</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm4: pwm4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT	0x116</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai2: sai2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK	0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC	0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK	0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00	0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00	0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai3: sai3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK	0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC	0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK	0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00	0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00	0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX	0x140</div><div class='add'>+			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX	0x140</div><div class='add'>+			MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS	0x140</div><div class='add'>+			MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x140</div><div class='add'>+			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x140</div><div class='add'>+			MX8MP_IOMUXC_UART4_RXD__UART2_DCE_CTS	0x140</div><div class='add'>+			MX8MP_IOMUXC_UART4_TXD__UART2_DCE_RTS	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: uart3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX	0x140</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX	0x140</div><div class='add'>+			MX8MP_IOMUXC_SD1_STROBE__UART3_DCE_CTS	0x140</div><div class='add'>+			MX8MP_IOMUXC_SD1_RESET_B__UART3_DCE_RTS	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart4: uart4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX	0x140</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX	0x140</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS	0x140</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x190</div><div class='add'>+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x194</div><div class='add'>+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x196</div><div class='add'>+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x190</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x194</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x196</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2-gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12	0x1c4</div><div class='add'>+			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x190</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x190</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x194</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x194</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x196</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x196</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B	0xc6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wifi_ctrl: wifi-ctrlgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00	0x41 /* WL_REG_ON */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18	0x41 /* WL_WAKE_HOST */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-imx-lvds-hdmi-common.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-evk-imx-lvds-hdmi-common.dtsi<br/>new file mode 100644<br/>index 000000000000..44b30e9b3fde<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-evk-imx-lvds-hdmi-common.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-evk-imx-lvds-hdmi-common.dtsi</a></div><div class='hunk'>@@ -0,0 +1,29 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+&amp;{/} {</div><div class='add'>+	lvds-hdmi-connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		label = "J2";</div><div class='add'>+		type = "a";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			lvds2hdmi_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;it6263_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lvds_bridge {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtso b/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtso<br/>new file mode 100644<br/>index 000000000000..4008d2fd36d6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtso</a></div><div class='hunk'>@@ -0,0 +1,44 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "imx8mp-evk-lvds0-imx-lvds-hdmi-common.dtsi"</div><div class='add'>+</div><div class='add'>+&amp;it6263 {</div><div class='add'>+	ports {</div><div class='add'>+		port@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			dual-lvds-odd-pixels;</div><div class='add'>+</div><div class='add'>+			it6263_lvds_link1: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;ldb_lvds_ch0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			dual-lvds-even-pixels;</div><div class='add'>+</div><div class='add'>+			it6263_lvds_link2: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;ldb_lvds_ch1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lvds_bridge {</div><div class='add'>+	ports {</div><div class='add'>+		port@1 {</div><div class='add'>+			ldb_lvds_ch0: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;it6263_lvds_link1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@2 {</div><div class='add'>+			ldb_lvds_ch1: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;it6263_lvds_link2&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi-common.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi-common.dtsi<br/>new file mode 100644<br/>index 000000000000..6eae7477abf8<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi-common.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi-common.dtsi</a></div><div class='hunk'>@@ -0,0 +1,43 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include "imx8mp-evk-imx-lvds-hdmi-common.dtsi"</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	it6263: hdmi@4c {</div><div class='add'>+		compatible = "ite,it6263";</div><div class='add'>+		reg = &lt;0x4c&gt;;</div><div class='add'>+		data-mapping = "jeida-24";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_lvds_en&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio1 10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		ivdd-supply = &lt;&amp;reg_buck5&gt;;</div><div class='add'>+		ovdd-supply = &lt;&amp;reg_vext_3v3&gt;;</div><div class='add'>+		txavcc18-supply = &lt;&amp;reg_buck5&gt;;</div><div class='add'>+		txavcc33-supply = &lt;&amp;reg_vext_3v3&gt;;</div><div class='add'>+		pvcc1-supply = &lt;&amp;reg_buck5&gt;;</div><div class='add'>+		pvcc2-supply = &lt;&amp;reg_buck5&gt;;</div><div class='add'>+		avcc-supply = &lt;&amp;reg_vext_3v3&gt;;</div><div class='add'>+		anvdd-supply = &lt;&amp;reg_buck5&gt;;</div><div class='add'>+		apvdd-supply = &lt;&amp;reg_buck5&gt;;</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@2 {</div><div class='add'>+				reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+				it6263_out: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;lvds2hdmi_connector_in&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi.dtso b/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi.dtso<br/>new file mode 100644<br/>index 000000000000..9e11f261ad13<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi.dtso</a></div><div class='hunk'>@@ -0,0 +1,28 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "imx8mp-evk-lvds0-imx-lvds-hdmi-common.dtsi"</div><div class='add'>+</div><div class='add'>+&amp;it6263 {</div><div class='add'>+	ports {</div><div class='add'>+		port@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			it6263_lvds_link1: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;ldb_lvds_ch0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lvds_bridge {</div><div class='add'>+	ports {</div><div class='add'>+		port@1 {</div><div class='add'>+			ldb_lvds_ch0: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;it6263_lvds_link1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtso b/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtso<br/>new file mode 100644<br/>index 000000000000..af2e73e36a1b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtso</a></div><div class='hunk'>@@ -0,0 +1,44 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "imx8mp-evk-lvds1-imx-lvds-hdmi-common.dtsi"</div><div class='add'>+</div><div class='add'>+&amp;it6263 {</div><div class='add'>+	ports {</div><div class='add'>+		port@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			dual-lvds-even-pixels;</div><div class='add'>+</div><div class='add'>+			it6263_lvds_link1: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;ldb_lvds_ch1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			dual-lvds-odd-pixels;</div><div class='add'>+</div><div class='add'>+			it6263_lvds_link2: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;ldb_lvds_ch0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lvds_bridge {</div><div class='add'>+	ports {</div><div class='add'>+		port@1 {</div><div class='add'>+			ldb_lvds_ch0: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;it6263_lvds_link2&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@2 {</div><div class='add'>+			ldb_lvds_ch1: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;it6263_lvds_link1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi-common.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi-common.dtsi<br/>new file mode 100644<br/>index 000000000000..8cc9d361c2a4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi-common.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi-common.dtsi</a></div><div class='hunk'>@@ -0,0 +1,43 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include "imx8mp-evk-imx-lvds-hdmi-common.dtsi"</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	it6263: hdmi@4c {</div><div class='add'>+		compatible = "ite,it6263";</div><div class='add'>+		reg = &lt;0x4c&gt;;</div><div class='add'>+		data-mapping = "jeida-24";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_lvds_en&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio1 10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		ivdd-supply = &lt;&amp;reg_buck5&gt;;</div><div class='add'>+		ovdd-supply = &lt;&amp;reg_vext_3v3&gt;;</div><div class='add'>+		txavcc18-supply = &lt;&amp;reg_buck5&gt;;</div><div class='add'>+		txavcc33-supply = &lt;&amp;reg_vext_3v3&gt;;</div><div class='add'>+		pvcc1-supply = &lt;&amp;reg_buck5&gt;;</div><div class='add'>+		pvcc2-supply = &lt;&amp;reg_buck5&gt;;</div><div class='add'>+		avcc-supply = &lt;&amp;reg_vext_3v3&gt;;</div><div class='add'>+		anvdd-supply = &lt;&amp;reg_buck5&gt;;</div><div class='add'>+		apvdd-supply = &lt;&amp;reg_buck5&gt;;</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@2 {</div><div class='add'>+				reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+				it6263_out: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;lvds2hdmi_connector_in&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi.dtso b/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi.dtso<br/>new file mode 100644<br/>index 000000000000..527a893a71b2<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi.dtso</a></div><div class='hunk'>@@ -0,0 +1,28 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "imx8mp-evk-lvds1-imx-lvds-hdmi-common.dtsi"</div><div class='add'>+</div><div class='add'>+&amp;it6263 {</div><div class='add'>+	ports {</div><div class='add'>+		port@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			it6263_lvds_link1: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;ldb_lvds_ch1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lvds_bridge {</div><div class='add'>+	ports {</div><div class='add'>+		port@2 {</div><div class='add'>+			ldb_lvds_ch1: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;it6263_lvds_link1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-mx8-dlvds-lcd1.dtso b/arch/arm64/boot/dts/freescale/imx8mp-evk-mx8-dlvds-lcd1.dtso<br/>new file mode 100644<br/>index 000000000000..1b71890d43d5<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-evk-mx8-dlvds-lcd1.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-evk-mx8-dlvds-lcd1.dtso</a></div><div class='hunk'>@@ -0,0 +1,77 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+&amp;{/} {</div><div class='add'>+	panel-lvds {</div><div class='add'>+		compatible = "koe,tx26d202vm0bwa";</div><div class='add'>+		backlight = &lt;&amp;backlight_lvds&gt;;</div><div class='add'>+		power-supply = &lt;&amp;reg_vext_3v3&gt;;</div><div class='add'>+</div><div class='add'>+		panel-timing {</div><div class='add'>+			clock-frequency = &lt;148500000&gt;;</div><div class='add'>+			hactive = &lt;1920&gt;;</div><div class='add'>+			vactive = &lt;1200&gt;;</div><div class='add'>+			hfront-porch = &lt;130&gt;;</div><div class='add'>+			hback-porch = &lt;70&gt;;</div><div class='add'>+			hsync-len = &lt;30&gt;;</div><div class='add'>+			vfront-porch = &lt;5&gt;;</div><div class='add'>+			vback-porch = &lt;5&gt;;</div><div class='add'>+			vsync-len = &lt;5&gt;;</div><div class='add'>+			de-active = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				dual-lvds-odd-pixels;</div><div class='add'>+</div><div class='add'>+				panel_in_odd: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;ldb_lvds_ch0&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				dual-lvds-even-pixels;</div><div class='add'>+</div><div class='add'>+				panel_in_even: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;ldb_lvds_ch1&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;backlight_lvds {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lvds_bridge {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@1 {</div><div class='add'>+			ldb_lvds_ch0: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;panel_in_odd&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@2 {</div><div class='add'>+			ldb_lvds_ch1: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;panel_in_even&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts<br/>index 3da1fff3d6fd..c6facb2ad9aa 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-evk.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-evk.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-evk.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-evk.dts</a></div><div class='hunk'>@@ -5,6 +5,7 @@</div><div class='ctx'> </div><div class='ctx'> /dts-v1/;</div><div class='ctx'> </div><div class='add'>+#include &lt;dt-bindings/phy/phy-imx8-pcie.h&gt;</div><div class='ctx'> #include "imx8mp.dtsi"</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='hunk'>@@ -15,6 +16,28 @@</div><div class='ctx'> 		stdout-path = &amp;uart2;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	backlight_lvds: backlight-lvds {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		pwms = &lt;&amp;pwm2 0 100000 0&gt;;</div><div class='add'>+		brightness-levels = &lt;0 100&gt;;</div><div class='add'>+		num-interpolated-steps = &lt;100&gt;;</div><div class='add'>+		default-brightness-level = &lt;100&gt;;</div><div class='add'>+		power-supply = &lt;&amp;reg_per_12v&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdmi-connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		label = "hdmi";</div><div class='add'>+		type = "a";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			hdmi_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;adv7535_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	gpio-leds {</div><div class='ctx'> 		compatible = "gpio-leds";</div><div class='ctx'> 		pinctrl-names = "default";</div><div class='hunk'>@@ -33,6 +56,95 @@</div><div class='ctx'> 		      &lt;0x1 0x00000000 0 0xc0000000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	native-hdmi-connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		label = "HDMI OUT";</div><div class='add'>+		type = "a";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			hdmi_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_tx_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_refclk: pcie0-refclk {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;100000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_audio_3v3: regulator-audio-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "audio-3v3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_audio_1v8: regulator-audio-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "audio-1v8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_audio_pwr: regulator-audio-pwr {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_audio_pwr_reg&gt;;</div><div class='add'>+		regulator-name = "audio-pwr";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio4 29 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_can1_stby: regulator-can1-stby {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "can1-stby";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_flexcan1_reg&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio5 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_can2_stby: regulator-can2-stby {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "can2-stby";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_flexcan2_reg&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio4 27 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_pcie0: regulator-pcie {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pcie0_reg&gt;;</div><div class='add'>+		regulator-name = "MPCIE_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio2 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_per_12v: regulator-per-12v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "PER_12V";</div><div class='add'>+		regulator-min-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;12000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;pca6416 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	reg_usdhc2_vmmc: regulator-usdhc2 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		pinctrl-names = "default";</div><div class='hunk'>@@ -43,6 +155,253 @@</div><div class='ctx'> 		gpio = &lt;&amp;gpio2 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 		enable-active-high;</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	reg_vext_3v3: regulator-vext-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VEXT_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	audio_codec_bt_sco: audio-codec-bt-sco {</div><div class='add'>+		compatible = "linux,bt-sco";</div><div class='add'>+		#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-bt-sco {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,name = "bt-sco-audio";</div><div class='add'>+		simple-audio-card,format = "dsp_a";</div><div class='add'>+		simple-audio-card,bitclock-inversion;</div><div class='add'>+		simple-audio-card,frame-master = &lt;&amp;btcpu&gt;;</div><div class='add'>+		simple-audio-card,bitclock-master = &lt;&amp;btcpu&gt;;</div><div class='add'>+</div><div class='add'>+		btcpu: simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;sai2&gt;;</div><div class='add'>+			dai-tdm-slot-num = &lt;2&gt;;</div><div class='add'>+			dai-tdm-slot-width = &lt;16&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		simple-audio-card,codec {</div><div class='add'>+			sound-dai = &lt;&amp;audio_codec_bt_sco 1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-hdmi {</div><div class='add'>+		compatible = "fsl,imx-audio-hdmi";</div><div class='add'>+		model = "audio-hdmi";</div><div class='add'>+		audio-cpu = &lt;&amp;aud2htx&gt;;</div><div class='add'>+		hdmi-out;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-micfil {</div><div class='add'>+		compatible = "fsl,imx-audio-card";</div><div class='add'>+		model = "micfil-audio";</div><div class='add'>+</div><div class='add'>+		pri-dai-link {</div><div class='add'>+			link-name = "micfil hifi";</div><div class='add'>+			format = "i2s";</div><div class='add'>+</div><div class='add'>+			cpu {</div><div class='add'>+				sound-dai = &lt;&amp;micfil&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-wm8960 {</div><div class='add'>+		compatible = "fsl,imx-audio-wm8960";</div><div class='add'>+		audio-asrc = &lt;&amp;easrc&gt;;</div><div class='add'>+		audio-codec = &lt;&amp;wm8960&gt;;</div><div class='add'>+		audio-cpu = &lt;&amp;sai3&gt;;</div><div class='add'>+		audio-routing = "Headphone Jack", "HP_L",</div><div class='add'>+			"Headphone Jack", "HP_R",</div><div class='add'>+			"Ext Spk", "SPK_LP",</div><div class='add'>+			"Ext Spk", "SPK_LN",</div><div class='add'>+			"Ext Spk", "SPK_RP",</div><div class='add'>+			"Ext Spk", "SPK_RN",</div><div class='add'>+			"LINPUT1", "Mic Jack",</div><div class='add'>+			"LINPUT3", "Mic Jack",</div><div class='add'>+			"Mic Jack", "MICB";</div><div class='add'>+		hp-det-gpio = &lt;&amp;gpio4 28 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		model = "wm8960-audio";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_hpdet&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-xcvr {</div><div class='add'>+		compatible = "fsl,imx-audio-card";</div><div class='add'>+		model = "imx-audio-xcvr";</div><div class='add'>+</div><div class='add'>+		pri-dai-link {</div><div class='add'>+			link-name = "XCVR PCM";</div><div class='add'>+</div><div class='add'>+			cpu {</div><div class='add'>+				sound-dai = &lt;&amp;xcvr&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		dsp_vdev0vring0: vdev0vring0@942f0000 {</div><div class='add'>+			reg = &lt;0 0x942f0000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dsp_vdev0vring1: vdev0vring1@942f8000 {</div><div class='add'>+			reg = &lt;0 0x942f8000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dsp_vdev0buffer: vdev0buffer@94300000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x94300000 0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexspi {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexspi0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;80000000&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;1&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;aud2htx {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsp_reserved {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsp {</div><div class='add'>+	memory-region = &lt;&amp;dsp_vdev0buffer&gt;, &lt;&amp;dsp_vdev0vring0&gt;,</div><div class='add'>+			&lt;&amp;dsp_vdev0vring1&gt;, &lt;&amp;dsp_reserved&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;easrc {</div><div class='add'>+	fsl,asrc-rate = &lt;48000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eqos {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_eqos&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	snps,force_thresh_dma_mode;</div><div class='add'>+	snps,mtl-tx-config = &lt;&amp;mtl_tx_setup&gt;;</div><div class='add'>+	snps,mtl-rx-config = &lt;&amp;mtl_rx_setup&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@1 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			eee-broken-1000t;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio4 22 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;10000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;80000&gt;;</div><div class='add'>+			realtek,clkout-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mtl_tx_setup: tx-queues-config {</div><div class='add'>+		snps,tx-queues-to-use = &lt;5&gt;;</div><div class='add'>+</div><div class='add'>+		queue0 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue1 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue2 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x4&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue3 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x8&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue4 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0xf0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mtl_rx_setup: rx-queues-config {</div><div class='add'>+		snps,rx-queues-to-use = &lt;5&gt;;</div><div class='add'>+		snps,rx-sched-sp;</div><div class='add'>+</div><div class='add'>+		queue0 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x1&gt;;</div><div class='add'>+			snps,map-to-dma-channel = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue1 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x2&gt;;</div><div class='add'>+			snps,map-to-dma-channel = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue2 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x4&gt;;</div><div class='add'>+			snps,map-to-dma-channel = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue3 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x8&gt;;</div><div class='add'>+			snps,map-to-dma-channel = &lt;3&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue4 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0xf0&gt;;</div><div class='add'>+			snps,map-to-dma-channel = &lt;4&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;fec {</div><div class='hunk'>@@ -62,6 +421,178 @@</div><div class='ctx'> 			reg = &lt;1&gt;;</div><div class='ctx'> 			eee-broken-1000t;</div><div class='ctx'> 			reset-gpios = &lt;&amp;gpio4 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;10000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;80000&gt;;</div><div class='add'>+			realtek,clkout-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan1&gt;;</div><div class='add'>+	xceiver-supply = &lt;&amp;reg_can1_stby&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan2&gt;;</div><div class='add'>+	xceiver-supply = &lt;&amp;reg_can2_stby&gt;;</div><div class='add'>+	status = "disabled";/* can2 pin conflict with pdm */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_pai {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_pvi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hdmi&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@1 {</div><div class='add'>+			hdmi_tx_out: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pmic@25 {</div><div class='add'>+		compatible = "nxp,pca9450c";</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;3 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			BUCK1 {</div><div class='add'>+				regulator-name = "BUCK1";</div><div class='add'>+				regulator-min-microvolt = &lt;720000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_arm: BUCK2 {</div><div class='add'>+				regulator-name = "BUCK2";</div><div class='add'>+				regulator-min-microvolt = &lt;720000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1025000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+				nxp,dvs-run-voltage = &lt;950000&gt;;</div><div class='add'>+				nxp,dvs-standby-voltage = &lt;850000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			BUCK4 {</div><div class='add'>+				regulator-name = "BUCK4";</div><div class='add'>+				regulator-min-microvolt = &lt;3000000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3600000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_buck5: BUCK5 {</div><div class='add'>+				regulator-name = "BUCK5";</div><div class='add'>+				regulator-min-microvolt = &lt;1650000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1950000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			BUCK6 {</div><div class='add'>+				regulator-name = "BUCK6";</div><div class='add'>+				regulator-min-microvolt = &lt;1045000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1155000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			LDO1 {</div><div class='add'>+				regulator-name = "LDO1";</div><div class='add'>+				regulator-min-microvolt = &lt;1650000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1950000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			LDO3 {</div><div class='add'>+				regulator-name = "LDO3";</div><div class='add'>+				regulator-min-microvolt = &lt;1710000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1890000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			LDO5 {</div><div class='add'>+				regulator-name = "LDO5";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	hdmi@3d {</div><div class='add'>+		compatible = "adi,adv7535";</div><div class='add'>+		reg = &lt;0x3d&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;9 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		adi,dsi-lanes = &lt;4&gt;;</div><div class='add'>+		avdd-supply = &lt;&amp;reg_buck5&gt;;</div><div class='add'>+		dvdd-supply = &lt;&amp;reg_buck5&gt;;</div><div class='add'>+		pvdd-supply = &lt;&amp;reg_buck5&gt;;</div><div class='add'>+		a2vdd-supply = &lt;&amp;reg_buck5&gt;;</div><div class='add'>+		v3p3-supply = &lt;&amp;reg_vext_3v3&gt;;</div><div class='add'>+		v1p2-supply = &lt;&amp;reg_buck5&gt;;</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				adv7535_in: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;dsi_out&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				adv7535_out: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;hdmi_connector_in&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='hunk'>@@ -72,18 +603,180 @@</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='add'>+	wm8960: codec@1a {</div><div class='add'>+		compatible = "wlf,wm8960";</div><div class='add'>+		reg = &lt;0x1a&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		clocks = &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1&gt;;</div><div class='add'>+		clock-names = "mclk";</div><div class='add'>+		wlf,shared-lrclk;</div><div class='add'>+		wlf,hp-cfg = &lt;3 2 3&gt;;</div><div class='add'>+		wlf,gpio-cfg = &lt;1 3&gt;;</div><div class='add'>+		AVDD-supply = &lt;&amp;reg_audio_3v3&gt;;</div><div class='add'>+		DBVDD-supply = &lt;&amp;reg_audio_1v8&gt;;</div><div class='add'>+		DCVDD-supply = &lt;&amp;reg_audio_1v8&gt;;</div><div class='add'>+		SPKVDD1-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+		SPKVDD2-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	pca6416: gpio@20 {</div><div class='ctx'> 		compatible = "ti,tca6416";</div><div class='ctx'> 		reg = &lt;0x20&gt;;</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pca6416_int&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;12 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		gpio-line-names = "EXT_PWREN1",</div><div class='add'>+			"EXT_PWREN2",</div><div class='add'>+			"CAN1/I2C5_SEL",</div><div class='add'>+			"PDM/CAN2_SEL",</div><div class='add'>+			"FAN_EN",</div><div class='add'>+			"PWR_MEAS_IO1",</div><div class='add'>+			"PWR_MEAS_IO2",</div><div class='add'>+			"EXP_P0_7",</div><div class='add'>+			"EXP_P1_0",</div><div class='add'>+			"EXP_P1_1",</div><div class='add'>+			"EXP_P1_2",</div><div class='add'>+			"EXP_P1_3",</div><div class='add'>+			"EXP_P1_4",</div><div class='add'>+			"EXP_P1_5",</div><div class='add'>+			"EXP_P1_6",</div><div class='add'>+			"EXP_P1_7";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* I2C on expansion connector J22. */</div><div class='add'>+&amp;i2c5 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;; /* Lower clock speed for external bus. */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c5&gt;;</div><div class='add'>+	status = "disabled"; /* can1 pins conflict with i2c5 */</div><div class='add'>+</div><div class='add'>+	/* GPIO 2 of PCA6416 is used to switch between CAN1 and I2C5 functions:</div><div class='add'>+	 *     LOW:  CAN1 (default, pull-down)</div><div class='add'>+	 *     HIGH: I2C5</div><div class='add'>+	 * You need to set it to high to enable I2C5 (for example, add gpio-hog</div><div class='add'>+	 * in pca6416 node).</div><div class='add'>+	 */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;micfil {</div><div class='add'>+	#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pdm&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_PDM&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;196608000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_dsi {</div><div class='add'>+	samsung,esc-clock-frequency = &lt;10000000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			dsi_out: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;adv7535_in&gt;;</div><div class='add'>+				data-lanes = &lt;1 2 3 4&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;mu2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	fsl,refclk-pad-mode = &lt;IMX8_PCIE_REFCLK_PAD_INPUT&gt;;</div><div class='add'>+	clocks = &lt;&amp;pcie0_refclk&gt;;</div><div class='add'>+	clock-names = "ref";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie0&gt;;</div><div class='add'>+	reset-gpio = &lt;&amp;gpio2 7 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vpcie-supply = &lt;&amp;reg_pcie0&gt;;</div><div class='add'>+	vpcie3v3aux-supply = &lt;&amp;reg_pcie0&gt;;</div><div class='add'>+	supports-clkreq;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0_ep {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai2 {</div><div class='add'>+	#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai2&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_SAI2&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;12288000&gt;;</div><div class='add'>+	fsl,sai-mclk-direction-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai3&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_SAI3&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;12288000&gt;;</div><div class='add'>+	fsl,sai-mclk-direction-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;snvs_pwrkey {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;uart1 { /* BT */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_UART1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL1_80M&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;uart2 {</div><div class='ctx'> 	/* console */</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='hunk'>@@ -91,6 +784,30 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;usb3_phy1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usb1_vbus&gt;;</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_UART3&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL1_80M&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;usdhc2 {</div><div class='ctx'> 	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_USDHC2&gt;;</div><div class='ctx'> 	assigned-clock-rates = &lt;400000000&gt;;</div><div class='hunk'>@@ -123,52 +840,264 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;xcvr {</div><div class='add'>+	#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;iomuxc {</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hog&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl_audio_pwr_reg: audiopwrreggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29		0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_eqos: eqosgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x2</div><div class='add'>+			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x2</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL			0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x16</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x16</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x16</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x16</div><div class='add'>+			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL			0x16</div><div class='add'>+			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x16</div><div class='add'>+			MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22				0x10</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='ctx'> 	pinctrl_fec: fecgrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='del'>-			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3</div><div class='del'>-			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3</div><div class='del'>-			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x91</div><div class='del'>-			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x91</div><div class='del'>-			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x91</div><div class='del'>-			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x91</div><div class='del'>-			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91</div><div class='del'>-			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91</div><div class='del'>-			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x1f</div><div class='del'>-			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x1f</div><div class='del'>-			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x1f</div><div class='del'>-			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x1f</div><div class='del'>-			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f</div><div class='del'>-			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x1f</div><div class='del'>-			MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02		0x19</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x2</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x2</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x90</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x90</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x90</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x90</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x90</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x90</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x16</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x16</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x16</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x16</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x16</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x16</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02		0x10</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan1: flexcan1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SPDIF_RX__CAN1_RX          0x154</div><div class='add'>+			MX8MP_IOMUXC_SPDIF_TX__CAN1_TX          0x154</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan2: flexcan2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX         0x154</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX         0x154</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan1_reg: flexcan1reggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05  0x154   /* CAN1_STBY */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan2_reg: flexcan2reggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27      0x154   /* CAN2_STBY */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexspi0: flexspi0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK           0x1c2</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B        0x82</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00      0x82</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01      0x82</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02      0x82</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03      0x82</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	pinctrl_gpio_led: gpioledgrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='del'>-			MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16	0x19</div><div class='add'>+			MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_hdmi: hdmigrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL	0x1c2</div><div class='add'>+			MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA	0x1c2</div><div class='add'>+			MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC		0x10</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_hog: hoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD		0x40000010</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_hpdet: hpdetgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28		0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c2</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001c2</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA		0x400001c2</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	pinctrl_i2c3: i2c3grp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='del'>-			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400001c3</div><div class='del'>-			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001c3</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400001c2</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c5: i2c5grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA         0x400001c2</div><div class='add'>+			MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL         0x400001c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lvds_en: lvdsengrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10	0x1c0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie0: pcie0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B	0x60 /* open drain, pull up */</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07	0x40</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie0_reg: pcie0reggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06	0x40</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pdm: pdmgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CLK		0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_PDM_BIT_STREAM00	0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_PDM_BIT_STREAM01	0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_PDM_BIT_STREAM02	0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_PDM_BIT_STREAM03	0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: pmicgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03	0x000001c0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pca6416_int: pca6416_int_grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12	0x146 /* Input pull-up. */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm1: pwm1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT	0x116</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm2: pwm2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT	0x116</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {</div><div class='add'>+	pinctrl_pwm4: pwm4grp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='del'>-			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x41</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT	0x116</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x40</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX	0x140</div><div class='add'>+			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX	0x140</div><div class='add'>+			MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS	0x140</div><div class='add'>+			MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai2: sai2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK	0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC	0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00	0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00	0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai3: sai3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC	0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK	0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00	0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00	0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK	0xd6</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	pinctrl_uart2: uart2grp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='del'>-			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x49</div><div class='del'>-			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x49</div><div class='add'>+			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x140</div><div class='add'>+			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usb1_vbus: usb1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR	0x10</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: uart3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX		0x140</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX		0x140</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS		0x140</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS		0x140</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -180,11 +1109,11 @@</div><div class='ctx'> 			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d0</div><div class='ctx'> 			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d0</div><div class='ctx'> 			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d0</div><div class='del'>-			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc0</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x194</div><div class='ctx'> 			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d4</div><div class='hunk'>@@ -192,11 +1121,11 @@</div><div class='ctx'> 			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d4</div><div class='ctx'> 			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d4</div><div class='ctx'> 			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d4</div><div class='del'>-			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x196</div><div class='ctx'> 			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d6</div><div class='hunk'>@@ -204,11 +1133,11 @@</div><div class='ctx'> 			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d6</div><div class='ctx'> 			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d6</div><div class='ctx'> 			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d6</div><div class='del'>-			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pinctrl_usdhc2_gpio: usdhc2grp-gpio {</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12	0x1c4</div><div class='ctx'> 		&gt;;</div><div class='hunk'>@@ -230,7 +1159,7 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x194</div><div class='ctx'> 			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d4</div><div class='hunk'>@@ -246,7 +1175,7 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x196</div><div class='ctx'> 			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d6</div><div class='hunk'>@@ -264,7 +1193,7 @@</div><div class='ctx'> </div><div class='ctx'> 	pinctrl_wdog: wdoggrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='del'>-			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B	0xc6</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B	0x166</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-mate.dts b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-mate.dts<br/>new file mode 100644<br/>index 000000000000..00614f5d58ea<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-mate.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-hummingboard-mate.dts</a></div><div class='hunk'>@@ -0,0 +1,31 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2025 Josua Mayer &lt;josua@solid-run.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mp-sr-som.dtsi"</div><div class='add'>+#include "imx8mp-hummingboard-pulse-common.dtsi"</div><div class='add'>+#include "imx8mp-hummingboard-pulse-hdmi.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "SolidRun i.MX8MP HummingBoard Mate";</div><div class='add'>+	compatible = "solidrun,imx8mp-hummingboard-mate",</div><div class='add'>+		     "solidrun,imx8mp-sr-som", "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;eqos;</div><div class='add'>+		/delete-property/ ethernet1;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec {</div><div class='add'>+	/* this board does not use second phy / ethernet on SoM */</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mikro_pwm_pins&gt;, &lt;&amp;mikro_int_pins&gt;, &lt;&amp;mikro_rst_pins&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pro.dts b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pro.dts<br/>new file mode 100644<br/>index 000000000000..36cd452f1583<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pro.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pro.dts</a></div><div class='hunk'>@@ -0,0 +1,76 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2025 Josua Mayer &lt;josua@solid-run.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/phy/phy-imx8-pcie.h&gt;</div><div class='add'>+</div><div class='add'>+#include "imx8mp-sr-som.dtsi"</div><div class='add'>+#include "imx8mp-hummingboard-pulse-codec.dtsi"</div><div class='add'>+#include "imx8mp-hummingboard-pulse-common.dtsi"</div><div class='add'>+#include "imx8mp-hummingboard-pulse-hdmi.dtsi"</div><div class='add'>+#include "imx8mp-hummingboard-pulse-m2con.dtsi"</div><div class='add'>+#include "imx8mp-hummingboard-pulse-mini-hdmi.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "SolidRun i.MX8MP HummingBoard Pro";</div><div class='add'>+	compatible = "solidrun,imx8mp-hummingboard-pro",</div><div class='add'>+		     "solidrun,imx8mp-sr-som", "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;eqos;</div><div class='add'>+		ethernet1 = &amp;fec;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mikro_pwm_pins&gt;, &lt;&amp;mikro_int_pins&gt;, &lt;&amp;hdmi_pins&gt;,</div><div class='add'>+		    &lt;&amp;m2_wwan_wake_pins&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie {</div><div class='add'>+	pinctrl-0 = &lt;&amp;m2_reset_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	reset-gpio = &lt;&amp;gpio1 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	clocks = &lt;&amp;hsio_blk_ctrl&gt;;</div><div class='add'>+	clock-names = "ref";</div><div class='add'>+	fsl,clkreq-unsupported;</div><div class='add'>+	fsl,refclk-pad-mode = &lt;IMX8_PCIE_REFCLK_PAD_OUTPUT&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;phy0 {</div><div class='add'>+	leds {</div><div class='add'>+		/* ADIN1300 LED_0 pin */</div><div class='add'>+		led@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			color = &lt;LED_COLOR_ID_ORANGE&gt;;</div><div class='add'>+			function = LED_FUNCTION_LAN;</div><div class='add'>+			default-state = "keep";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/delete-node/ led@1;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;phy1 {</div><div class='add'>+	leds {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		/* ADIN1300 LED_0 pin */</div><div class='add'>+		led@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_LAN;</div><div class='add'>+			default-state = "keep";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-codec.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-codec.dtsi<br/>new file mode 100644<br/>index 000000000000..77402a3db9ef<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-codec.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-codec.dtsi</a></div><div class='hunk'>@@ -0,0 +1,59 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2025 Josua Mayer &lt;josua@solid-run.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	sound-wm8904 {</div><div class='add'>+		compatible = "fsl,imx-audio-wm8904";</div><div class='add'>+		model = "audio-wm8904";</div><div class='add'>+		audio-cpu = &lt;&amp;sai3&gt;;</div><div class='add'>+		audio-codec = &lt;&amp;codec&gt;;</div><div class='add'>+		audio-routing =</div><div class='add'>+			"Headphone Jack", "HPOUTL",</div><div class='add'>+			"Headphone Jack", "HPOUTR",</div><div class='add'>+			"AMIC", "MICBIAS",</div><div class='add'>+			"IN2R", "AMIC";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	codec: audio-codec@1a {</div><div class='add'>+		compatible = "wlf,wm8904";</div><div class='add'>+		reg = &lt;0x1a&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		clocks = &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1&gt;;</div><div class='add'>+		clock-names = "mclk";</div><div class='add'>+		AVDD-supply = &lt;&amp;v_1_8&gt;;</div><div class='add'>+		CPVDD-supply = &lt;&amp;v_1_8&gt;;</div><div class='add'>+		DBVDD-supply = &lt;&amp;v_3_3&gt;;</div><div class='add'>+		DCVDD-supply = &lt;&amp;v_1_8&gt;;</div><div class='add'>+		MICVDD-supply = &lt;&amp;v_3_3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	sai3_pins: pinctrl-sai3-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK	0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC	0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK	0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00	0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00	0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;sai3_pins&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_SAI3&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;12288000&gt;;</div><div class='add'>+	clocks = &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG&gt;, &lt;&amp;clk IMX8MP_CLK_DUMMY&gt;,</div><div class='add'>+		 &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1&gt;, &lt;&amp;clk IMX8MP_CLK_DUMMY&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX8MP_CLK_DUMMY&gt;;</div><div class='add'>+	clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";</div><div class='add'>+	fsl,sai-mclk-direction-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-common.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-common.dtsi<br/>new file mode 100644<br/>index 000000000000..825ad6a2ba14<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-common.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-common.dtsi</a></div><div class='hunk'>@@ -0,0 +1,384 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2025 Josua Mayer &lt;josua@solid-run.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		rtc0 = &amp;carrier_rtc;</div><div class='add'>+		rtc1 = &amp;snvs_rtc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;led_pins&gt;;</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			label = "D30";</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio5 28 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "on";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			label = "D31";</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio4 24 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "on";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-2 {</div><div class='add'>+			label = "D32";</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio4 23 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "on";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-3 {</div><div class='add'>+			label = "D33";</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio4 21 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "on";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-4 {</div><div class='add'>+			label = "D34";</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio4 22 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "on";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rfkill-mpcie-wifi {</div><div class='add'>+		/*</div><div class='add'>+		 * The mpcie connector only has USB,</div><div class='add'>+		 * therefore this rfkill is for cellular radios only.</div><div class='add'>+		 */</div><div class='add'>+		compatible = "rfkill-gpio";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;mpcie_rfkill_pins&gt;;</div><div class='add'>+		label = "mpcie radio";</div><div class='add'>+		radio-type = "wwan";</div><div class='add'>+		/* rfkill-gpio inverts internally */</div><div class='add'>+		shutdown-gpios = &lt;&amp;gpio1 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vmmc: regulator-mmc {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;vmmc_pins&gt;;</div><div class='add'>+		regulator-name = "vmmc";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio2 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		startup-delay-us = &lt;250&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vbus1: regulator-vbus-1 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vbus1";</div><div class='add'>+		gpio = &lt;&amp;gpio1 14 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;vbus1_pins&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vbus2: regulator-vbus-2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vbus2";</div><div class='add'>+		gpio = &lt;&amp;gpio1 15 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;vbus2_pins&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	v_1_2: regulator-1-2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "1v2";</div><div class='add'>+		regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vmpcie {</div><div class='add'>+		/* supplies mpcie and m2 connectors */</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vmpcie";</div><div class='add'>+		gpio = &lt;&amp;gpio1 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;vmpcie_pins&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* mikrobus spi */</div><div class='add'>+&amp;ecspi2 {</div><div class='add'>+	num-cs = &lt;1&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mikro_spi_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;mpcie_reset_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	mpcie-reset-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		output-low;</div><div class='add'>+		line-name = "mpcie-reset";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	carrier_eeprom: eeprom@57{</div><div class='add'>+		compatible = "st,24c02", "atmel,24c02";</div><div class='add'>+		reg = &lt;0x57&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	carrier_rtc: rtc@69 {</div><div class='add'>+		compatible = "abracon,ab1805";</div><div class='add'>+		reg = &lt;0x69&gt;;</div><div class='add'>+		abracon,tc-diode = "schottky";</div><div class='add'>+		abracon,tc-resistor = &lt;3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	csi_pins: pinctrl-csi-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* Pin 24: STROBE */</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07		0x0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	led_pins: pinctrl-led-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22		0x0</div><div class='add'>+			MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21		0x0</div><div class='add'>+			MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23		0x0</div><div class='add'>+			MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24		0x0</div><div class='add'>+			MX8MP_IOMUXC_UART4_RXD__GPIO5_IO28		0x0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mikro_int_pins: pinctrl-mikro-int-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09		0x0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mikro_pwm_pins: pinctrl-mikro-pwm-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08		0x0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mikro_rst_pins: pinctrl-mikro-rst-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30		0x0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mikro_spi_pins: pinctrl-mikro-spi-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_SS0__ECSPI2_SS0		0x40000</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK		0x82</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO		0x82</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI		0x82</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mikro_uart_pins: pinctrl-mikro-uart-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX		0x140</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX		0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mpcie_reset_pins: pinctrl-mpcie-reset-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01		0x0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mpcie_rfkill_pins: pinctrl-pcie-rfkill-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* weak i/o, open drain */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05		0x20</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb_hub_pins: pinctrl-usb-hub-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11		0x0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usdhc2_pins: pinctrl-usdhc2-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x190</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0x140</div><div class='add'>+			MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B		0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usdhc2_100mhz_pins: pinctrl-usdhc2-100mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x194</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0x140</div><div class='add'>+			MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B		0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usdhc2_200mhz_pins: pinctrl-usdhc2-200mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x196</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0x140</div><div class='add'>+			MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B		0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vbus1_pins: pinctrl-vbus-1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14		0x20</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vbus2_pins: pinctrl-vbus-2-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15		0x20</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vmmc_pins: pinctrl-vmmc-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19		0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vmpcie_pins: pinctrl-vmpcie-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10		0x0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;phy0 {</div><div class='add'>+	leds {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		/* ADIN1300 LED_0 pin */</div><div class='add'>+		led@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			color = &lt;LED_COLOR_ID_ORANGE&gt;;</div><div class='add'>+			function = LED_FUNCTION_LAN;</div><div class='add'>+			default-state = "keep";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* ADIN1300 LINK_ST pin */</div><div class='add'>+		led@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_LAN;</div><div class='add'>+			default-state = "keep";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;snvs_pwrkey {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* mikrobus uart */</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy0 {</div><div class='add'>+	fsl,phy-tx-preemp-amp-tune-microamp = &lt;1200&gt;;</div><div class='add'>+	vbus-supply = &lt;&amp;vbus2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy1 {</div><div class='add'>+	vbus-supply = &lt;&amp;vbus1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_0 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_1 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;usb_hub_pins&gt;;</div><div class='add'>+</div><div class='add'>+	hub_2_0: hub@1 {</div><div class='add'>+		compatible = "usb4b4,6502", "usb4b4,6506";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		peer-hub = &lt;&amp;hub_3_0&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio1 11 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;v_1_2&gt;;</div><div class='add'>+		vdd2-supply = &lt;&amp;v_3_3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hub_3_0: hub@2 {</div><div class='add'>+		compatible = "usb4b4,6500", "usb4b4,6504";</div><div class='add'>+		reg = &lt;2&gt;;</div><div class='add'>+		peer-hub = &lt;&amp;hub_2_0&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio1 11 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;v_1_2&gt;;</div><div class='add'>+		vdd2-supply = &lt;&amp;v_3_3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;usdhc2_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;usdhc2_100mhz_pins&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;usdhc2_200mhz_pins&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;vmmc&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cap-power-off-card;</div><div class='add'>+	full-pwr-cycle;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-hdmi.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-hdmi.dtsi<br/>new file mode 100644<br/>index 000000000000..d7a999c0d7e0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-hdmi.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-hdmi.dtsi</a></div><div class='hunk'>@@ -0,0 +1,44 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2025 Josua Mayer &lt;josua@solid-run.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	sound-hdmi {</div><div class='add'>+		compatible = "fsl,imx-audio-hdmi";</div><div class='add'>+		model = "audio-hdmi";</div><div class='add'>+		audio-cpu = &lt;&amp;aud2htx&gt;;</div><div class='add'>+		hdmi-out;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;aud2htx {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_pvi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	hdmi_pins: pinctrl-hdmi-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL	0x400001c3</div><div class='add'>+			MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA	0x400001c3</div><div class='add'>+			MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC		0x154</div><div class='add'>+			MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD		0x154</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-m2con.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-m2con.dtsi<br/>new file mode 100644<br/>index 000000000000..8d8d8d2e3da8<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-m2con.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-m2con.dtsi</a></div><div class='hunk'>@@ -0,0 +1,60 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2025 Josua Mayer &lt;josua@solid-run.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	rfkill-m2-gnss {</div><div class='add'>+		compatible = "rfkill-gpio";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;m2_gnss_rfkill_pins&gt;;</div><div class='add'>+		label = "m.2 GNSS";</div><div class='add'>+		radio-type = "gps";</div><div class='add'>+		/* rfkill-gpio inverts internally */</div><div class='add'>+		shutdown-gpios = &lt;&amp;gpio1 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* M.2 is B-keyed, so w-disable is for WWAN */</div><div class='add'>+	rfkill-m2-wwan {</div><div class='add'>+		compatible = "rfkill-gpio";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;m2_wwan_rfkill_pins&gt;;</div><div class='add'>+		label = "m.2 WWAN";</div><div class='add'>+		radio-type = "wwan";</div><div class='add'>+		/* rfkill-gpio inverts internally */</div><div class='add'>+		shutdown-gpios = &lt;&amp;gpio1 13 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	m2_gnss_rfkill_pins: pinctrl-m2-gnss-rfkill-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* weak i/o, open drain */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07		0x20</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	m2_reset_pins: pinctrl-m2-reset-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/*</div><div class='add'>+			 * 3.3V domain on SoC, set open-drain to ensure</div><div class='add'>+			 * 1.8V logic on connector</div><div class='add'>+			 */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06		0x20</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	m2_wwan_rfkill_pins: pinctrl-m2-wwan-rfkill-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* weak i/o, open drain */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13		0x20</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	m2_wwan_wake_pins: pinctrl-m2-wwan-wake-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* weak i/o, open drain */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12		0x20</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-mini-hdmi.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-mini-hdmi.dtsi<br/>new file mode 100644<br/>index 000000000000..46916ddc0533<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-mini-hdmi.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-mini-hdmi.dtsi</a></div><div class='hunk'>@@ -0,0 +1,81 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2025 Josua Mayer &lt;josua@solid-run.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	hdmi-connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		label = "hdmi";</div><div class='add'>+		type = "c";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			hdmi_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;adv7535_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	hdmi@3d {</div><div class='add'>+		compatible = "adi,adv7535";</div><div class='add'>+		reg = &lt;0x3d&gt;, &lt;0x3f&gt;, &lt;0x3c&gt;, &lt;0x38&gt;;</div><div class='add'>+		reg-names = "main", "edid", "cec", "packet";</div><div class='add'>+		adi,dsi-lanes = &lt;4&gt;;</div><div class='add'>+		avdd-supply = &lt;&amp;v_1_8&gt;;</div><div class='add'>+		dvdd-supply = &lt;&amp;v_1_8&gt;;</div><div class='add'>+		pvdd-supply = &lt;&amp;v_1_8&gt;;</div><div class='add'>+		a2vdd-supply = &lt;&amp;v_1_8&gt;;</div><div class='add'>+		v3p3-supply = &lt;&amp;v_3_3&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;mini_hdmi_pins&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;27 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				adv7535_from_dsim: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;dsim_to_adv7535&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				adv7535_out: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;hdmi_connector_in&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	mini_hdmi_pins: pinctrl-mini-hdmi-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27		0x0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_dsi {</div><div class='add'>+	samsung,esc-clock-frequency = &lt;10000000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	port@1 {</div><div class='add'>+		dsim_to_adv7535: endpoint {</div><div class='add'>+			remote-endpoint = &lt;&amp;adv7535_from_dsim&gt;;</div><div class='add'>+			attach-bridge;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse.dts b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse.dts<br/>new file mode 100644<br/>index 000000000000..d32844c3af05<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse.dts</a></div><div class='hunk'>@@ -0,0 +1,83 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2025 Josua Mayer &lt;josua@solid-run.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/phy/phy-imx8-pcie.h&gt;</div><div class='add'>+</div><div class='add'>+#include "imx8mp-sr-som.dtsi"</div><div class='add'>+#include "imx8mp-hummingboard-pulse-codec.dtsi"</div><div class='add'>+#include "imx8mp-hummingboard-pulse-common.dtsi"</div><div class='add'>+#include "imx8mp-hummingboard-pulse-hdmi.dtsi"</div><div class='add'>+#include "imx8mp-hummingboard-pulse-m2con.dtsi"</div><div class='add'>+#include "imx8mp-hummingboard-pulse-mini-hdmi.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "SolidRun i.MX8MP HummingBoard Pulse";</div><div class='add'>+	compatible = "solidrun,imx8mp-hummingboard-pulse",</div><div class='add'>+		     "solidrun,imx8mp-sr-som", "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;eqos;</div><div class='add'>+		ethernet1 = &amp;pcie_eth;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec {</div><div class='add'>+	/* this board does not use second phy / ethernet on SoM */</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;mpcie_reset_pins&gt;, &lt;&amp;m2_reset_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	m2-reset-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		output-low;</div><div class='add'>+		line-name = "m2-reset";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mikro_pwm_pins&gt;, &lt;&amp;mikro_int_pins&gt;, &lt;&amp;hdmi_pins&gt;,</div><div class='add'>+		    &lt;&amp;m2_wwan_wake_pins&gt;;</div><div class='add'>+</div><div class='add'>+	pcie_eth_pins: pinctrl-pcie-eth-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28		0x0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pcie_eth_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	reset-gpio = &lt;&amp;gpio4 28 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	root@0,0 {</div><div class='add'>+		compatible = "pci16c3,abcd";</div><div class='add'>+		reg = &lt;0x00000000 0 0 0 0&gt;;</div><div class='add'>+		#address-cells = &lt;3&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		/* Intel i210 */</div><div class='add'>+		pcie_eth: ethernet@1,0 {</div><div class='add'>+			compatible = "pci8086,157b";</div><div class='add'>+			reg = &lt;0x00010000 0 0 0 0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	clocks = &lt;&amp;hsio_blk_ctrl&gt;;</div><div class='add'>+	clock-names = "ref";</div><div class='add'>+	fsl,clkreq-unsupported;</div><div class='add'>+	fsl,refclk-pad-mode = &lt;IMX8_PCIE_REFCLK_PAD_OUTPUT&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-ripple.dts b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-ripple.dts<br/>new file mode 100644<br/>index 000000000000..4ce5b799b6ab<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-ripple.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-hummingboard-ripple.dts</a></div><div class='hunk'>@@ -0,0 +1,31 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2025 Josua Mayer &lt;josua@solid-run.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mp-sr-som.dtsi"</div><div class='add'>+#include "imx8mp-hummingboard-pulse-common.dtsi"</div><div class='add'>+#include "imx8mp-hummingboard-pulse-mini-hdmi.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "SolidRun i.MX8MP HummingBoard Ripple";</div><div class='add'>+	compatible = "solidrun,imx8mp-hummingboard-ripple",</div><div class='add'>+		     "solidrun,imx8mp-sr-som", "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;eqos;</div><div class='add'>+		/delete-property/ ethernet1;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec {</div><div class='add'>+	/* this board does not use second phy / ethernet on SoM */</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mikro_pwm_pins&gt;, &lt;&amp;mikro_int_pins&gt;, &lt;&amp;mikro_rst_pins&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts b/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts<br/>new file mode 100644<br/>index 000000000000..a02b31c42db4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts</a></div><div class='hunk'>@@ -0,0 +1,175 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2018 NXP</div><div class='add'>+ * Copyright (c) 2019 Engicam srl</div><div class='add'>+ * Copyright (c) 2020 Amarula Solutions(India)</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mp.dtsi"</div><div class='add'>+#include "imx8mp-icore-mx8mp.dtsi"</div><div class='add'>+#include &lt;dt-bindings/usb/pd.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit";</div><div class='add'>+	compatible = "engicam,icore-mx8mp-edimm2.2", "engicam,icore-mx8mp",</div><div class='add'>+		     "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb1_vbus: regulator-usb1 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;gpio1 14 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usb1&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-name = "usb1_host_vbus";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;gpio2 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usdhc2_vmmc&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "VSD_3V3";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Ethernet */</div><div class='add'>+&amp;eqos {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_eqos&gt;;</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@7 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			micrel,led-mode = &lt;0&gt;;</div><div class='add'>+			reg = &lt;7&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* console */</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_0 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_1 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SDCARD */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	cd-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	pinctrl-names = "default" ;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_eqos: eqosgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x2</div><div class='add'>+			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x2</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL			0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x16</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x16</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x16</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x16</div><div class='add'>+			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL			0x16</div><div class='add'>+			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x16</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07				0x10</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x40</div><div class='add'>+			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x40</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: uart3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX	0x140</div><div class='add'>+			MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX	0x140</div><div class='add'>+			MX8MP_IOMUXC_SD1_STROBE__UART3_DCE_CTS	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x190</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12	0x1c4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usb1: regusb1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14	0x10</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x40</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi<br/>new file mode 100644<br/>index 000000000000..a6319824ea2e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi</a></div><div class='hunk'>@@ -0,0 +1,186 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2018 NXP</div><div class='add'>+ * Copyright (c) 2019 Engicam srl</div><div class='add'>+ * Copyright (c) 2020 Amarula Solutions(India)</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "engicam,icore-mx8mp", "fsl,imx8mp";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pca9450: pmic@25 {</div><div class='add'>+		compatible = "nxp,pca9450c";</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+		interrupts = &lt;1 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			buck1: BUCK1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-min-microvolt = &lt;720000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+				regulator-name = "BUCK1";</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck2: BUCK2  {</div><div class='add'>+				nxp,dvs-run-voltage = &lt;950000&gt;;</div><div class='add'>+				nxp,dvs-standby-voltage = &lt;850000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1025000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;720000&gt;;</div><div class='add'>+				regulator-name = "BUCK2";</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck4: BUCK4 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;3600000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;3000000&gt;;</div><div class='add'>+				regulator-name = "BUCK4";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck5: BUCK5 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1950000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1650000&gt;;</div><div class='add'>+				regulator-name = "BUCK5";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck6: BUCK6 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1155000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1045000&gt;;</div><div class='add'>+				regulator-name = "BUCK6";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo1: LDO1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1950000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1650000&gt;;</div><div class='add'>+				regulator-name = "LDO1";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo3: LDO3 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1890000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1710000&gt;;</div><div class='add'>+				regulator-name = "LDO3";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo5: LDO5 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "LDO5";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* EMMC */</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c3</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: pmicgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01	  0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x190</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x190</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x194</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x194</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x196</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x196</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-iota2-lumpy.dts b/arch/arm64/boot/dts/freescale/imx8mp-iota2-lumpy.dts<br/>new file mode 100644<br/>index 000000000000..f48cf22b423d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-iota2-lumpy.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-iota2-lumpy.dts</a></div><div class='hunk'>@@ -0,0 +1,423 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Y Soft</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mp.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "ysoft,imx8mp-iota2-lumpy", "fsl,imx8mp";</div><div class='add'>+	model = "Y Soft i.MX8MPlus IOTA2 Lumpy board";</div><div class='add'>+</div><div class='add'>+	beeper {</div><div class='add'>+		compatible = "pwm-beeper";</div><div class='add'>+		pwms = &lt;&amp;pwm4 0 500000 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio_keys: gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_keys&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		button-reset {</div><div class='add'>+			gpios = &lt;&amp;gpio1 7 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			label = "Factory RESET";</div><div class='add'>+			linux,code = &lt;BTN_0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb_host: regulator-usb-host {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usb_host_vbus&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-name = "usb-host";</div><div class='add'>+		gpio = &lt;&amp;gpio1 14 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		reg = &lt;0x0 0x40000000 0 0x80000000&gt;,</div><div class='add'>+		      &lt;0x1 0x00000000 0 0x80000000&gt;;</div><div class='add'>+		device_type = "memory";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eqos {</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_eqos&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			interrupts = &lt;21 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_ethphy0&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			reset-assert-us = &lt;1000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;1000&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio3 22 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			micrel,led-mode = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec {</div><div class='add'>+	fsl,magic-packet;</div><div class='add'>+	phy-handle = &lt;&amp;ethphy1&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy1: ethernet-phy@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			interrupts = &lt;19 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_ethphy1&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			reset-assert-us = &lt;1000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;1000&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio3 20 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			micrel,led-mode = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pmic@25 {</div><div class='add'>+		compatible = "nxp,pca9450c";</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+		interrupts = &lt;3 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			BUCK1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;720000&gt;;</div><div class='add'>+				regulator-name = "BUCK1";</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_arm: BUCK2 {</div><div class='add'>+				nxp,dvs-run-voltage = &lt;950000&gt;;</div><div class='add'>+				nxp,dvs-standby-voltage = &lt;850000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1025000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;720000&gt;;</div><div class='add'>+				regulator-name = "BUCK2";</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			BUCK4 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;3600000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;3000000&gt;;</div><div class='add'>+				regulator-name = "BUCK4";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			BUCK5 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1950000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1650000&gt;;</div><div class='add'>+				regulator-name = "BUCK5";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			BUCK6 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1155000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1045000&gt;;</div><div class='add'>+				regulator-name = "BUCK6";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			LDO1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1950000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1650000&gt;;</div><div class='add'>+				regulator-name = "LDO1";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			LDO3 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1890000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1710000&gt;;</div><div class='add'>+				regulator-name = "LDO3";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			LDO4 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;950000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-name = "LDO4";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			LDO5 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "LDO5";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	rtc: rtc@68 {</div><div class='add'>+		compatible = "dallas,ds1341";</div><div class='add'>+		reg = &lt;0x68&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm4 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm4&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy1 {</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usb_host&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_1 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_USDHC3&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_eqos: eqosgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC		0x2</div><div class='add'>+			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO		0x2</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0	0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1	0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2	0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3	0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL	0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0	0x16</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1	0x16</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2	0x16</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3	0x16</div><div class='add'>+			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL	0x16</div><div class='add'>+			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x16</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ethphy0: ethphy0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21		0x10</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22		0x10</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ethphy1: ethphy1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19		0x10</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20		0x10</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec: fecgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x2</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x2</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x90</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x90</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x90</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x90</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x90</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x90</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x16</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x16</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x16</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x16</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x16</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x16</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio_keys: gpiokeysgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07	0x80</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c2</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001c2</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA		0x400001c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: pmicgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03	0x1c0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm4: pwm4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT	0x102</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x0</div><div class='add'>+			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usb_host_vbus: usb1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR	0x0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x194</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x194</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x196</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x196</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x190</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x190</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B	0x166</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-kontron-bl-osm-s.dts b/arch/arm64/boot/dts/freescale/imx8mp-kontron-bl-osm-s.dts<br/>new file mode 100644<br/>index 000000000000..0924ac50fd2d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-kontron-bl-osm-s.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-kontron-bl-osm-s.dts</a></div><div class='hunk'>@@ -0,0 +1,332 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2022 Kontron Electronics GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mp-kontron-osm-s.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Kontron BL i.MX8MP OSM-S";</div><div class='add'>+	compatible = "kontron,imx8mp-bl-osm-s", "kontron,imx8mp-osm-s", "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;fec;</div><div class='add'>+		ethernet1 = &amp;eqos;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	connector {</div><div class='add'>+		compatible = "gpio-usb-b-connector", "usb-b-connector";</div><div class='add'>+		id-gpios = &lt;&amp;gpio1 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		label = "Type-C";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usb1_id&gt;;</div><div class='add'>+		type = "micro";</div><div class='add'>+		vbus-supply = &lt;&amp;reg_usb1_vbus&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			usb_dr_connector: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;usb3_dwc&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led1 {</div><div class='add'>+			label = "led1";</div><div class='add'>+			gpios = &lt;&amp;gpio1 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pwm-beeper {</div><div class='add'>+		compatible = "pwm-beeper";</div><div class='add'>+		pwms = &lt;&amp;pwm2 0 5000 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc_panel: regulator-vcc-panel {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		gpio = &lt;&amp;gpio4 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "VCC_PANEL";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	eeram@0 {</div><div class='add'>+		compatible = "microchip,48l640";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;20000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eqos {	/* Second ethernet (OSM-S ETH_B) */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_eqos_rgmii&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy1: ethernet-phy@1 {</div><div class='add'>+			compatible = "ethernet-phy-id4f51.e91b";</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_ethphy1&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			reset-assert-us = &lt;10000&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio1 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec { /* First ethernet (OSM-S ETH_A) */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_enet_rgmii&gt;;</div><div class='add'>+	phy-connection-type = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@1 {</div><div class='add'>+			compatible = "ethernet-phy-id4f51.e91b";</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_ethphy0&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			reset-assert-us = &lt;10000&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio1 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Rename SoM signals according to board usage:</div><div class='add'>+ *   SDIO_A_PWR_EN -&gt; CAN_ADDR2</div><div class='add'>+ *   SDIO_A_WP     -&gt; CAN_ADDR3</div><div class='add'>+ */</div><div class='add'>+&amp;gpio2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio2&gt;;</div><div class='add'>+	gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "",</div><div class='add'>+			  "SDIO_A_CD", "SDIO_A_CLK", "SDIO_A_CMD", "SDIO_A_D0",</div><div class='add'>+			  "SDIO_A_D1", "SDIO_A_D2", "SDIO_A_D3", "CAN_ADDR2",</div><div class='add'>+			  "CAN_ADDR3";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Rename SoM signals according to board usage:</div><div class='add'>+ *   GPIO_B_0      -&gt; IO_EXP_INT</div><div class='add'>+ *   GPIO_B_1      -&gt; IO_EXP_RST</div><div class='add'>+ */</div><div class='add'>+&amp;gpio3 {</div><div class='add'>+	gpio-line-names = "PCIE_WAKE", "PCIE_CLKREQ", "PCIE_A_PERST", "SDIO_B_D5",</div><div class='add'>+			  "SDIO_B_D6", "SDIO_B_D7", "SPI_A_WP", "SPI_A_HOLD",</div><div class='add'>+			  "UART_B_RTS", "UART_B_CTS", "SDIO_B_D0", "SDIO_B_D1",</div><div class='add'>+			  "SDIO_B_D2", "SDIO_B_D3", "SDIO_B_WP", "SDIO_B_D4",</div><div class='add'>+			  "PCIE_SM_ALERT", "SDIO_B_CLK", "SDIO_B_CMD", "IO_EXP_INT",</div><div class='add'>+			  "IO_EXP_RST", "", "BOOT_SEL0", "BOOT_SEL1",</div><div class='add'>+			  "", "", "SDIO_B_CD", "SDIO_B_PWR_EN",</div><div class='add'>+			  "HDMI_CEC", "HDMI_HPD";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Rename SoM signals according to board usage and remove labels for unsed pins:</div><div class='add'>+ *   GPIO_A_6      -&gt; TFT_RESET</div><div class='add'>+ *   GPIO_A_7      -&gt; TFT_STBY</div><div class='add'>+ *   GPIO_B_3      -&gt; CSI_ENABLE</div><div class='add'>+ *   GPIO_B_2      -&gt; USB_HUB_RST</div><div class='add'>+ */</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	gpio-line-names = "", "", "", "",</div><div class='add'>+			  "ETH_A_MDC", "ETH_A_MDIO", "ETH_A_RXD0", "ETH_A_RXD1",</div><div class='add'>+			  "ETH_A_RXD2", "ETH_A_RXD3", "ETH_A_RX_DV", "ETH_A_RX_CLK",</div><div class='add'>+			  "ETH_A_TXD0", "ETH_A_TXD1", "ETH_A_TXD2", "ETH_A_TXD3",</div><div class='add'>+			  "ETH_A_TX_EN", "ETH_A_TX_CLK", "CSI_ENABLE", "",</div><div class='add'>+			  "USB_HUB_RST", "TFT_RESET", "CAN_A_TX", "UART_A_CTS",</div><div class='add'>+			  "UART_A_RTS", "CAN_A_RX", "CAN_B_TX", "CAN_B_RX",</div><div class='add'>+			  "TFT_STBY", "CARRIER_PWR_EN", "I2S_A_DATA_IN", "I2S_LRCLK";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Rename SoM signals according to board usage:</div><div class='add'>+ *   SPI_A_SDI	-&gt; CAN_ADDR0</div><div class='add'>+ *   SPI_A_SDO	-&gt; CAN_ADDR1</div><div class='add'>+ */</div><div class='add'>+&amp;gpio5 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio5&gt;;</div><div class='add'>+	gpio-line-names = "I2S_BITCLK", "I2S_A_DATA_OUT", "I2S_MCLK", "PWM_2",</div><div class='add'>+			  "PWM_1", "PWM_0", "SPI_A_SCK", "CAN_ADDR1",</div><div class='add'>+			  "CAN_ADDR0", "SPI_A_CS0", "SPI_B_SCK", "SPI_B_SDO",</div><div class='add'>+			  "SPI_B_SDI", "SPI_B_CS0", "I2C_A_SCL", "I2C_A_SDA",</div><div class='add'>+			  "I2C_B_SCL", "I2C_B_SDA", "PCIE_SMCLK", "PCIE_SMDAT",</div><div class='add'>+			  "I2C_CAM_SCL", "I2C_CAM_SDA", "UART_A_RX", "UART_A_TX",</div><div class='add'>+			  "UART_C_RX", "UART_C_TX", "UART_CON_RX", "UART_CON_TX",</div><div class='add'>+			  "UART_B_RX", "UART_B_TX";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_pvi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hdmi&gt;;</div><div class='add'>+	ddc-i2c-bus = &lt;&amp;i2c2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	gpio_expander_dio: io-expander@20 {</div><div class='add'>+		compatible = "ti,tca6408";</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-line-names = "DIO1_OUT","DIO1_IN", "DIO2_OUT","DIO2_IN",</div><div class='add'>+				  "DIO3_OUT","DIO3_IN", "DIO4_OUT","DIO4_IN";</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+		interrupts = &lt;19 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio3 20 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_usdhc2_vcc {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;snvs_pwrkey {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	linux,rs485-enabled-at-boot-time;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_0 {</div><div class='add'>+	adp-disable;</div><div class='add'>+	hnp-disable;</div><div class='add'>+	srp-disable;</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	role-switch-default-mode = "peripheral";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	port {</div><div class='add'>+		usb3_dwc: endpoint {</div><div class='add'>+			remote-endpoint = &lt;&amp;usb_dr_connector&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_1 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	usb-hub@1 {</div><div class='add'>+		compatible = "usb424,2514";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio4 20 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_1 {</div><div class='add'>+	fsl,disable-port-power-control;</div><div class='add'>+	fsl,permanently-attached;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_vdd_3v3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_ethphy0: ethphy0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01		0x46</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ethphy1: ethphy1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00		0x46</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio2: gpio2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19		0x46</div><div class='add'>+			MX8MP_IOMUXC_SD2_WP__GPIO2_IO20			0x46</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio5: gpio5grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_MOSI__GPIO5_IO07		0x46 /* CAN_ADR0 */</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08		0x46 /* CAN_ADR1 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-kontron-dl.dtso b/arch/arm64/boot/dts/freescale/imx8mp-kontron-dl.dtso<br/>new file mode 100644<br/>index 000000000000..a3cba41d2b53<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-kontron-dl.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-kontron-dl.dtso</a></div><div class='hunk'>@@ -0,0 +1,111 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2023 Kontron Electronics GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include "imx8mp-pinfunc.h"</div><div class='add'>+</div><div class='add'>+&amp;{/} {</div><div class='add'>+	model = "Kontron DL i.MX8MP OSM-S";</div><div class='add'>+	compatible = "kontron,imx8mp-bl-osm-s", "kontron,imx8mp-osm-s", "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	backlight: backlight {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		pwms = &lt;&amp;pwm1 0 50000 0&gt;;</div><div class='add'>+		brightness-levels = &lt;0 100&gt;;</div><div class='add'>+		num-interpolated-steps = &lt;100&gt;;</div><div class='add'>+		default-brightness-level = &lt;100&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	panel {</div><div class='add'>+		compatible = "jenson,bl-jt60050-01a", "panel-lvds";</div><div class='add'>+		backlight = &lt;&amp;backlight&gt;;</div><div class='add'>+		data-mapping = "vesa-24";</div><div class='add'>+		enable-gpios = &lt;&amp;gpio1 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		power-supply = &lt;&amp;reg_vcc_panel&gt;;</div><div class='add'>+		height-mm = &lt;86&gt;;</div><div class='add'>+		width-mm = &lt;154&gt;;</div><div class='add'>+</div><div class='add'>+		panel-timing {</div><div class='add'>+			clock-frequency = &lt;50000000&gt;;</div><div class='add'>+			hactive = &lt;1024&gt;;</div><div class='add'>+			hback-porch = &lt;160&gt;;</div><div class='add'>+			hfront-porch = &lt;160&gt;;</div><div class='add'>+			hsync-len = &lt;1&gt;;</div><div class='add'>+			vactive = &lt;600&gt;;</div><div class='add'>+			vback-porch = &lt;23&gt;;</div><div class='add'>+			vfront-porch = &lt;12&gt;;</div><div class='add'>+			vsync-len = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			panel_in_lvds0: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;ldb_lvds_ch0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio4&gt;, &lt;&amp;pinctrl_panel_stby&gt;;</div><div class='add'>+</div><div class='add'>+	panel-rst-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;21 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		output-high;</div><div class='add'>+		line-name = "panel-reset";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	panel-stby-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;28 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		output-high;</div><div class='add'>+		line-name = "panel-standby";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	touchscreen@5d {</div><div class='add'>+		compatible = "goodix,gt928";</div><div class='add'>+		reg = &lt;0x5d&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;6 8&gt;;</div><div class='add'>+		irq-gpios = &lt;&amp;gpio1 6 0&gt;;</div><div class='add'>+		AVDD28-supply = &lt;&amp;reg_vcc_panel&gt;;</div><div class='add'>+		VDDIO-supply = &lt;&amp;reg_vcc_panel&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio1 7 0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ldb_lvds_ch0 {</div><div class='add'>+	remote-endpoint = &lt;&amp;panel_in_lvds0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lvds_bridge {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_panel_stby: panelstbygrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28		0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-kontron-osm-s.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-kontron-osm-s.dtsi<br/>new file mode 100644<br/>index 000000000000..b97bfeb1c30f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-kontron-osm-s.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-kontron-osm-s.dtsi</a></div><div class='hunk'>@@ -0,0 +1,909 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2022 Kontron Electronics GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include "imx8mp.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Kontron OSM-S i.MX8MP";</div><div class='add'>+	compatible = "kontron,imx8mp-osm-s", "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		rtc0 = &amp;rv3028;</div><div class='add'>+		rtc1 = &amp;snvs_rtc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		/*</div><div class='add'>+		 * There are multiple SoM flavors with different DDR sizes.</div><div class='add'>+		 * The smallest is 1GB. For larger sizes the bootloader will</div><div class='add'>+		 * update the reg property.</div><div class='add'>+		 */</div><div class='add'>+		reg = &lt;0x0 0x40000000 0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart3;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb1_vbus: regulator-usb1-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usb1_vbus&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio1 12 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-name = "VBUS_USB_A";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb2_vbus: regulator-usb2-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usb2_vbus&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio1 9 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-name = "VBUS_USB_B";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vcc: regulator-usdhc2-vcc {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usdhc2_vcc&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio2 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "VCC_SDIO_A";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc3_vcc: regulator-usdhc3-vcc {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usdhc3_vcc&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio3 27 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "VCC_SDIO_B";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vdd_carrier: regulator-vdd-carrier {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_vdd_carrier&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio3 16 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-name = "VDD_CARRIER";</div><div class='add'>+</div><div class='add'>+		regulator-state-standby {</div><div class='add'>+			regulator-on-in-suspend;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		regulator-state-mem {</div><div class='add'>+			regulator-off-in-suspend;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		regulator-state-disk {</div><div class='add'>+			regulator-off-in-suspend;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_vdd_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_vdd_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_vdd_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_vdd_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi1 { /* OSM-S SPI_A */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi1&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi2 { /* OSM-S SPI_B */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi2&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 13 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan1 { /* OSM-S CAN_A */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan2 { /* OSM-S CAN_B */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio1&gt;;</div><div class='add'>+	gpio-line-names = "GPIO_A_0", "GPIO_A_1", "", "",</div><div class='add'>+			  "", "GPIO_A_2", "GPIO_A_3", "GPIO_A_4",</div><div class='add'>+			  "GPIO_A_5", "USB_B_EN", "USB_A_ID", "USB_B_ID",</div><div class='add'>+			  "USB_A_EN", "USB_A_OC","CAM_MCK", "USB_B_OC",</div><div class='add'>+			  "ETH_B_MDC", "ETH_B_MDIO", "ETH_B_TXD3", "ETH_B_TXD2",</div><div class='add'>+			  "ETH_B_TXD1", "ETH_B_TXD0", "ETH_B_TX_EN", "ETH_B_TX_CLK",</div><div class='add'>+			  "ETH_B_RX_DV", "ETH_B_RX_CLK", "ETH_B_RXD0", "ETH_B_RXD1",</div><div class='add'>+			  "ETH_B_RXD2", "ETH_B_RXD3";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio2 {</div><div class='add'>+	gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "",</div><div class='add'>+			  "SDIO_A_CD", "SDIO_A_CLK", "SDIO_A_CMD", "SDIO_A_D0",</div><div class='add'>+			  "SDIO_A_D1", "SDIO_A_D2", "SDIO_A_D3", "SDIO_A_PWR_EN",</div><div class='add'>+			  "SDIO_A_WP";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio3&gt;;</div><div class='add'>+	gpio-line-names = "PCIE_WAKE", "PCIE_CLKREQ", "PCIE_A_PERST", "SDIO_B_D5",</div><div class='add'>+			  "SDIO_B_D6", "SDIO_B_D7", "SPI_A_WP", "SPI_A_HOLD",</div><div class='add'>+			  "UART_B_RTS", "UART_B_CTS", "SDIO_B_D0", "SDIO_B_D1",</div><div class='add'>+			  "SDIO_B_D2", "SDIO_B_D3", "SDIO_B_WP", "SDIO_B_D4",</div><div class='add'>+			  "PCIE_SM_ALERT", "SDIO_B_CLK", "SDIO_B_CMD", "GPIO_B_0",</div><div class='add'>+			  "GPIO_B_1", "", "BOOT_SEL0", "BOOT_SEL1",</div><div class='add'>+			  "", "", "SDIO_B_CD", "SDIO_B_PWR_EN",</div><div class='add'>+			  "HDMI_CEC", "HDMI_HPD";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio4&gt;;</div><div class='add'>+	gpio-line-names = "GPIO_B_5", "GPIO_B_6", "GPIO_B_7", "GPIO_C_0",</div><div class='add'>+			  "ETH_A_MDC", "ETH_A_MDIO", "ETH_A_RXD0", "ETH_A_RXD1",</div><div class='add'>+			  "ETH_A_RXD2", "ETH_A_RXD3", "ETH_A_RX_DV", "ETH_A_RX_CLK",</div><div class='add'>+			  "ETH_A_TXD0", "ETH_A_TXD1", "ETH_A_TXD2", "ETH_A_TXD3",</div><div class='add'>+			  "ETH_A_TX_EN", "ETH_A_TX_CLK", "GPIO_B_3", "GPIO_B_4",</div><div class='add'>+			  "GPIO_B_2", "GPIO_A_6", "CAN_A_TX", "UART_A_CTS",</div><div class='add'>+			  "UART_A_RTS", "CAN_A_RX", "CAN_B_TX", "CAN_B_RX",</div><div class='add'>+			  "GPIO_A_7", "CARRIER_PWR_EN", "I2S_A_DATA_IN", "I2S_LRCLK";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio5 {</div><div class='add'>+	gpio-line-names = "I2S_BITCLK", "I2S_A_DATA_OUT", "I2S_MCLK", "PWM_2",</div><div class='add'>+			  "PWM_1", "PWM_0", "SPI_A_SCK", "SPI_A_SDO",</div><div class='add'>+			  "SPI_A_SDI", "SPI_A_CS0", "SPI_B_SCK", "SPI_B_SDO",</div><div class='add'>+			  "SPI_B_SDI", "SPI_B_CS0", "I2C_A_SCL", "I2C_A_SDA",</div><div class='add'>+			  "I2C_B_SCL", "I2C_B_SDA", "PCIE_SMCLK", "PCIE_SMDAT",</div><div class='add'>+			  "I2C_CAM_SCL", "I2C_CAM_SDA", "UART_A_RX", "UART_A_TX",</div><div class='add'>+			  "UART_C_RX", "UART_C_TX", "UART_CON_RX", "UART_CON_TX",</div><div class='add'>+			  "UART_B_RX", "UART_B_TX";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 { /* OSM-S I2C_A */</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c1_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 { /* OSM-S I2C_B */</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c2_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 { /* OSM-S PCIe SMDAT/SMCLK */</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c3_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 { /* OSM-S I2C_CAM */</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c4&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c4_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c5 { /* PMIC, EEPROM, RTC */</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c5&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c5_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio3 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pca9450: pmic@25 {</div><div class='add'>+		compatible = "nxp,pca9450c";</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;3 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		nxp,i2c-lt-enable;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			reg_vdd_soc: BUCK1 { /* dual phase with BUCK3 */</div><div class='add'>+				regulator-name = "+0V8_VDD_SOC (BUCK1)";</div><div class='add'>+				regulator-min-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;950000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vdd_arm: BUCK2 {</div><div class='add'>+				regulator-name = "+0V9_VDD_ARM (BUCK2)";</div><div class='add'>+				regulator-min-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;950000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+				nxp,dvs-run-voltage = &lt;950000&gt;;</div><div class='add'>+				nxp,dvs-standby-voltage = &lt;850000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vdd_3v3: BUCK4 {</div><div class='add'>+				regulator-name = "+3V3 (BUCK4)";</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vdd_1v8: BUCK5 {</div><div class='add'>+				regulator-name = "+1V8 (BUCK5)";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_nvcc_dram: BUCK6 {</div><div class='add'>+				regulator-name = "+1V1_NVCC_DRAM (BUCK6)";</div><div class='add'>+				regulator-min-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_nvcc_snvs: LDO1 {</div><div class='add'>+				regulator-name = "+1V8_NVCC_SNVS (LDO1)";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vdda: LDO3 {</div><div class='add'>+				regulator-name = "+1V8_VDDA (LDO3)";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_nvcc_sd: LDO5 {</div><div class='add'>+				regulator-name = "NVCC_SD (LDO5)";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				sd-vsel-gpios = &lt;&amp;gpio1 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@50 {</div><div class='add'>+		compatible = "onnn,n24s64b", "atmel,24c64";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		size = &lt;8192&gt;;</div><div class='add'>+		num-addresses = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rv3028: rtc@52 {</div><div class='add'>+		compatible = "microcrystal,rv3028";</div><div class='add'>+		reg = &lt;0x52&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_rtc&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;gpio3 24 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm1 { /* OSM-S PWM_0 */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm2 { /* OSM-S PWM_1 */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm3 { /* OSM-S PWM_2 */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai3 { /* OSM-S I2S_A */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 { /* OSM-S UART_A */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 { /* OSM-S UART_C */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart3 { /* OSM-S UART_CON */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart4 { /* OSM-S UART_B */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart4&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_0 { /* OSM-S USB_A */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usb1_oc&gt;;</div><div class='add'>+	fsl,over-current-active-low;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_1 { /* OSM-S USB_B */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usb2_oc&gt;;</div><div class='add'>+	fsl,over-current-active-low;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc1 { /* eMMC */</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1_200mhz&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_vdd_3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_vdd_1v8&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 { /* OSM-S SDIO_A */</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;, &lt;&amp;pinctrl_usdhc2_wp&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;, &lt;&amp;pinctrl_usdhc2_wp&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;, &lt;&amp;pinctrl_usdhc2_wp&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vcc&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_nvcc_sd&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc3 { /* OSM-S SDIO_B */</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;, &lt;&amp;pinctrl_usdhc3_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;, &lt;&amp;pinctrl_usdhc3_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;, &lt;&amp;pinctrl_usdhc3_gpio&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc3_vcc&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_nvcc_sd&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio3 26 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	wp-gpios = &lt;&amp;gpio3 14 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_csi_mck: csimckgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1		0x59 /* CAM_MCK */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi1: ecspi1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO		0x44 /* SPI_A_SDI_(IO0) */</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI		0x44 /* SPI_A_SDO_(IO1) */</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK		0x44 /* SPI_A_SCK */</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09		0x40 /* SPI_A_CS0# */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi2: ecspi2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO		0x44 /* SPI_B_SDI */</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI		0x44 /* SPI_B_SDO */</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK		0x44 /* SPI_B_SCK */</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13		0x40 /* SPI_B_CS0# */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_enet_rgmii: enetrgmiigrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3 /* ETH_MDC */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3 /* ETH_MDIO */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x91 /* ETH_A_(S)(R)(G)MII_RXD0 */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x91 /* ETH_A_(S)(R)(G)MII_RXD1 */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x91 /* ETH_A_(R)(G)MII_RXD2 */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x91 /* ETH_A_(R)(G)MII_RXD3 */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91 /* ETH_A_(R)(G)MII_RX_CLK */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91 /* ETH_A_(R)(G)MII_RX_DV(_ER) */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x1f /* ETH_A_(S)(R)(G)MII_TXD0 */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x1f /* ETH_A_(S)(R)(G)MII_TXD1 */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x1f /* ETH_A_(S)(R)(G)MII_TXD2 */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x1f /* ETH_A_(S)(R)(G)MII_TXD3 */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x1f /* ETH_A_(R)(G)MII_TX_CLK */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f /* ETH_A_(R)(G)MII_TX_EN(_ER) */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_eqos_rgmii: eqosrgmiigrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC		0x3 /* ETH_B_MDC */</div><div class='add'>+			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO		0x3 /* ETH_B_MDIO */</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0	0x91 /* ETH_B_(S)(R)(G)MII_RXD0 */</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1	0x91 /* ETH_B_(S)(R)(G)MII_RXD1 */</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2	0x91 /* ETH_B_(R)(G)MII_RXD2 */</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3	0x91 /* ETH_B_(R)(G)MII_RXD3 */</div><div class='add'>+			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 /* ETH_B_(R)(G)MII_RX_CLK */</div><div class='add'>+			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL	0x91 /* ETH_B_(R)(G)MII_RX_DV(_ER) */</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0	0x1f /* ETH_B_(S)(R)(G)MII_TXD0 */</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1	0x1f /* ETH_B_(S)(R)(G)MII_TXD1 */</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2	0x1f /* ETH_B_(S)(R)(G)MII_TXD2 */</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3	0x1f /* ETH_B_(S)(R)(G)MII_TXD3 */</div><div class='add'>+			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f /* ETH_B_(R)(G)MII_TX_CLK */</div><div class='add'>+			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL	0x1f /* ETH_B_(R)(G)MII_TX_EN(_ER) */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan1: flexcan1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI2_RXC__CAN1_TX			0x154 /* CAN_A_TX */</div><div class='add'>+			MX8MP_IOMUXC_SAI2_TXC__CAN1_RX			0x154 /* CAN_A_RX */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan2: flexcan2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX			0x154 /* CAN_B_TX */</div><div class='add'>+			MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX			0x154 /* CAN_B_RX */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio1: gpio1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00		0x19 /* GPIO_A_0 */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01		0x19 /* GPIO_A_1 */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05		0x19 /* GPIO_A_2 */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06		0x19 /* GPIO_A_3 */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07		0x19 /* GPIO_A_4 */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08		0x19 /* GPIO_A_5 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio3: gpio3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01		0x19 /* GPIO_A_7 */</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19		0x19 /* GPIO_B_0 */</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20		0x19 /* GPIO_B_1 */</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22		0x19 /* BOOT_SEL0# */</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23		0x19 /* BOOT_SEL1# */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio4: gpio4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00		0x19 /* GPIO_B_5 */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01		0x19 /* GPIO_B_6 */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02		0x19 /* GPIO_B_7 */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03		0x19 /* GPIO_C_0 */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18		0x19 /* GPIO_B_3 */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19		0x19 /* GPIO_B_4 */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20		0x19 /* GPIO_B_2 */</div><div class='add'>+			MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21		0x19 /* GPIO_A_6 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_hdmi: hdmigrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD		0x19 /* HDMI_HPD */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL			0x40000084 /* I2C_A_SCL */</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA			0x40000084 /* I2C_A_SDA */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1_gpio: i2c1gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14		0x84 /* I2C_A_SCL */</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15		0x84 /* I2C_A_SDA */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL			0x40000084 /* I2C_B_SCL */</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA			0x40000084 /* I2C_B_SDA */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2_gpio: i2c2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16		0x84 /* I2C_B_SCL */</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17		0x84 /* I2C_B_SDA */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL			0x40000084 /* PCIe_SMCLK */</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA			0x40000084 /* PCIe_SMDAT */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3_gpio: i2c3gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18		0x84 /* PCIe_SMCLK */</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19		0x84 /* PCIe_SMDAT */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4: i2c4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL			0x40000084 /* I2C_CAM_SCL/CSI_TX_P */</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA			0x40000084 /* I2C_CAM_SDA/CSI_TX_N */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4_gpio: i2c4gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20		0x84 /* I2C_CAM_SCL/CSI_TX_P */</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21		0x84 /* I2C_CAM_SDA/CSI_TX_N */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c5: i2c5grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL		0x40000084</div><div class='add'>+			MX8MP_IOMUXC_SAI5_MCLK__I2C5_SDA		0x40000084</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c5_gpio: i2c5gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21		0x84</div><div class='add'>+			MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25		0x84</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie: pciegrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART4_RXD__PCIE_CLKREQ_B		0x19 /* PCIe_CLKREQ# */</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__GPIO3_IO02		0x19 /* PCIe_A_PERST# */</div><div class='add'>+			MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00		0x19 /* PCIe_WAKE# */</div><div class='add'>+			MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16		0x19 /* PCIe_SM_ALERT */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: pmicgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03		0x1c0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm1: pwm1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT		0x6 /* PWM_0 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm2: pwm2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SPDIF_RX__PWM2_OUT			0x6 /* PWM_1 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm3: pwm3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT			0x6 /* PWM_2 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usb1_vbus: regusb1vbusgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12		0x19 /* USB_A_EN */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usb2_vbus: regusb2vbusgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09		0x19 /* USB_B_EN */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usdhc2_vcc: regusdhc2vccgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19		0x19 /* SDIO_A_PWR_EN */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usdhc3_vcc: regusdhc3vccgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27		0x19 /* SDIO_B_PWR_EN */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_vdd_carrier: regvddcarriergrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29		0x19 /* CARRIER_PWR_EN */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_rtc: rtcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24		0x1c0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai3: sai3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00		0xd6 /* I2S_A_DATA_IN */</div><div class='add'>+			MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00		0xd6 /* I2S_A_DATA_OUT */</div><div class='add'>+			MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_DATA01		0xd6 /* I2S_B_DATA_IN */</div><div class='add'>+			MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_DATA01		0xd6 /* I2S_B_DATA_OUT */</div><div class='add'>+			MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK		0xd6 /* I2S_MCLK */</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA01__AUDIOMIX_SAI3_TX_SYNC		0xd6 /* I2S_LRCLK */</div><div class='add'>+			MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK		0xd6 /* I2S_BITCLK */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX		0x140 /* UART_A_RX */</div><div class='add'>+			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX		0x140 /* UART_A_TX */</div><div class='add'>+			MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS		0x140 /* UART_A_CTS */</div><div class='add'>+			MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS		0x140 /* UART_A_RTS */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX		0x140 /* UART_C_RX */</div><div class='add'>+			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX		0x140 /* UART_C_TX */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: uart3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX		0x140 /* UART_CON_RX */</div><div class='add'>+			MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX		0x140 /* UART_CON_TX */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart4: uart4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA00__UART4_DCE_RX		0x140 /* UART_B_RX */</div><div class='add'>+			MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX		0x140 /* UART_B_TX */</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA03__UART4_DCE_RTS		0x140 /* UART_B_CTS */</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA02__UART4_DCE_CTS		0x140 /* UART_B_RTS */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usb1_id: usb1idgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10		0x1c4 /* USB_A_ID */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usb1_oc: usb1ocgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC		0x1c0 /* USB_A_OC# */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usb2_id: usb2idgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO11__USB2_OTG_ID		0x1c4 /* USB_B_ID */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usb2_oc: usb2ocgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC		0x1c0 /* USB_B_OC# */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x190</div><div class='add'>+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA4__USDHC1_DATA4		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA5__USDHC1_DATA5		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA6__USDHC1_DATA6		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA7__USDHC1_DATA7		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD1_RESET_B__USDHC1_RESET_B	0x141</div><div class='add'>+			MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE		0x190</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x194</div><div class='add'>+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA4__USDHC1_DATA4		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA5__USDHC1_DATA5		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA6__USDHC1_DATA6		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA7__USDHC1_DATA7		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD1_RESET_B__USDHC1_RESET_B	0x141</div><div class='add'>+			MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE		0x194</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x196</div><div class='add'>+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA4__USDHC1_DATA4		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA5__USDHC1_DATA5		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA6__USDHC1_DATA6		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA7__USDHC1_DATA7		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD1_RESET_B__USDHC1_RESET_B	0x141</div><div class='add'>+			MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE		0x196</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x190 /* SDIO_A_CLK */</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d0 /* SDIO_A_CMD */</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d0 /* SDIO_A_D0 */</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d0 /* SDIO_A_D1 */</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d0 /* SDIO_A_D2 */</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d0 /* SDIO_A_D3 */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0x400001d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x194 /* SDIO_A_CLK */</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d4 /* SDIO_A_CMD */</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d4 /* SDIO_A_D0 */</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d4 /* SDIO_A_D1 */</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d4 /* SDIO_A_D2 */</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d4 /* SDIO_A_D3 */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0x400001d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x196 /* SDIO_A_CLK */</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d6 /* SDIO_A_CMD */</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d6 /* SDIO_A_D0 */</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d6 /* SDIO_A_D1 */</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d6 /* SDIO_A_D2 */</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d6 /* SDIO_A_D3 */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0x400001d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12		0x19 /* SDIO_A_CD# */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_wp: usdhc2wpgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_WP__USDHC2_WP			0x400000d6 /* SDIO_A_WP */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x190 /* SDIO_B_CLK */</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d0 /* SDIO_B_CMD */</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d0 /* SDIO_B_D0 */</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d0 /* SDIO_B_D1 */</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d0 /* SDIO_B_D2 */</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d0 /* SDIO_B_D3 */</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d0 /* SDIO_B_D4 */</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d0 /* SDIO_B_D5 */</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d0 /* SDIO_B_D6 */</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d0 /* SDIO_B_D7 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194 /* SDIO_B_CLK */</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4 /* SDIO_B_CMD */</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d4 /* SDIO_B_D0 */</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d4 /* SDIO_B_D1 */</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d4 /* SDIO_B_D2 */</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d4 /* SDIO_B_D3 */</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d4 /* SDIO_B_D4 */</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d4 /* SDIO_B_D5 */</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d4 /* SDIO_B_D6 */</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4 /* SDIO_B_D7 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x196 /* SDIO_B_CLK */</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d6 /* SDIO_B_CMD */</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d6 /* SDIO_B_D0 */</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d6 /* SDIO_B_D1 */</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d6 /* SDIO_B_D2 */</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d6 /* SDIO_B_D3 */</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d6 /* SDIO_B_D4 */</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d6 /* SDIO_B_D5 */</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d6 /* SDIO_B_D6 */</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d6 /* SDIO_B_D7 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_gpio: usdhc3gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26		0x19 /* SDIO_B_CD# */</div><div class='add'>+			MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14		0x19 /* SDIO_B_WP */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B		0xc6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-kontron-smarc-eval-carrier.dts b/arch/arm64/boot/dts/freescale/imx8mp-kontron-smarc-eval-carrier.dts<br/>new file mode 100644<br/>index 000000000000..2173a36ff691<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-kontron-smarc-eval-carrier.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-kontron-smarc-eval-carrier.dts</a></div><div class='hunk'>@@ -0,0 +1,254 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2024 Kontron Electronics GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/phy/phy-imx8-pcie.h&gt;</div><div class='add'>+#include "imx8mp-kontron-smarc.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Kontron SMARC Eval Carrier with i.MX8MP";</div><div class='add'>+	compatible = "kontron,imx8mp-smarc-eval-carrier", "kontron,imx8mp-smarc",</div><div class='add'>+		     "kontron,imx8mp-osm-s", "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	backlight: backlight {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		pwms = &lt;&amp;pwm1 0 50000 0&gt;;</div><div class='add'>+		brightness-levels = &lt;0 100&gt;;</div><div class='add'>+		num-interpolated-steps = &lt;100&gt;;</div><div class='add'>+		default-brightness-level = &lt;100&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;gpio3 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	extcon_usbc: usbc {</div><div class='add'>+		compatible = "linux,extcon-usb-gpio";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usb1_id&gt;;</div><div class='add'>+		id-gpios = &lt;&amp;gpio1 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,bitclock-master = &lt;&amp;codec_dai&gt;;</div><div class='add'>+		simple-audio-card,format = "i2s";</div><div class='add'>+		simple-audio-card,frame-master = &lt;&amp;codec_dai&gt;;</div><div class='add'>+		simple-audio-card,mclk-fs = &lt;256&gt;;</div><div class='add'>+		simple-audio-card,name = "imx8mp-wm8904";</div><div class='add'>+		simple-audio-card,routing =</div><div class='add'>+			"Headphone Jack", "HPOUTL",</div><div class='add'>+			"Headphone Jack", "HPOUTR",</div><div class='add'>+			"IN2L", "Line In Jack",</div><div class='add'>+			"IN2R", "Line In Jack",</div><div class='add'>+			"Headphone Jack", "MICBIAS",</div><div class='add'>+			"IN1L", "Headphone Jack";</div><div class='add'>+		simple-audio-card,widgets =</div><div class='add'>+			"Microphone", "Headphone Jack",</div><div class='add'>+			"Headphone", "Headphone Jack",</div><div class='add'>+			"Line", "Line In Jack";</div><div class='add'>+</div><div class='add'>+		codec_dai: simple-audio-card,codec {</div><div class='add'>+			clocks = &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1&gt;;</div><div class='add'>+			sound-dai = &lt;&amp;wm8904&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;sai3&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	regulator_can0: can0-regulator {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "can0_en";</div><div class='add'>+		gpio = &lt;&amp;expander_pm_out 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	regulator_can1: can1-regulator {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "can1_en";</div><div class='add'>+		gpio = &lt;&amp;expander_pm_out 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eqos {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	xceiver-supply = &lt;&amp;regulator_can0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan2 {</div><div class='add'>+	xceiver-supply = &lt;&amp;regulator_can1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_pvi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hdmi&gt;;</div><div class='add'>+	ddc-i2c-bus = &lt;&amp;i2c3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	expander_pm_out: io-expander@22 {</div><div class='add'>+		compatible = "nxp,pca9554";</div><div class='add'>+		reg = &lt;0x22&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-line-names = "EN_5V0_S0", "EN_3V3_S0", "EN_1V8_S0",</div><div class='add'>+				  "EN_1V5_S0", "EN_12V0_PCIE", "EN_3V3_S5",</div><div class='add'>+				  "CAN0_EN", "CAN1_EN";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	expander_pm_in: io-expander@24 {</div><div class='add'>+		compatible = "nxp,pca9554";</div><div class='add'>+		reg = &lt;0x24&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-line-names = "PG_5V0_3V3_S0", "PG_5V0_3V3_S5", "PG_1V8_S0",</div><div class='add'>+				  "PG_1V5_S0", "PG_BKLT_5V", "PG_BKLT_12V";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	wm8904: audio-codec@1a {</div><div class='add'>+		compatible = "wlf,wm8904";</div><div class='add'>+		reg = &lt;0x1a&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		clocks = &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1&gt;;</div><div class='add'>+		clock-names = "mclk";</div><div class='add'>+		AVDD-supply = &lt;&amp;reg_vdd_1v8&gt;;</div><div class='add'>+		CPVDD-supply = &lt;&amp;reg_vdd_1v8&gt;;</div><div class='add'>+		DBVDD-supply = &lt;&amp;reg_vdd_1v8&gt;;</div><div class='add'>+		DCVDD-supply = &lt;&amp;reg_vdd_1v8&gt;;</div><div class='add'>+		MICVDD-supply = &lt;&amp;reg_vdd_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	expander_audio: io-expander@20 {</div><div class='add'>+		compatible = "nxp,pca9554";</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-line-names = "I2C_SEL_CODEC_LOOPBACK", "FPAH_PRESENCE",</div><div class='add'>+				  "CODEC_OPTION_SW_I2S_HDA", "LINE_IN_JD",</div><div class='add'>+				  "LINE_OUT_JD", "HEADPHONES_JD", "MIC_JD";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	fsl,refclk-pad-mode = &lt;IMX8_PCIE_REFCLK_PAD_OUTPUT&gt;;</div><div class='add'>+	fsl,clkreq-unsupported;</div><div class='add'>+	clocks = &lt;&amp;hsio_blk_ctrl&gt;;</div><div class='add'>+	clock-names = "ref";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie&gt;;</div><div class='add'>+	reset-gpio = &lt;&amp;gpio3 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai3 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_SAI3&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;24576000&gt;;</div><div class='add'>+	fsl,sai-mclk-direction-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_0 {</div><div class='add'>+	adp-disable;</div><div class='add'>+	hnp-disable;</div><div class='add'>+	srp-disable;</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	extcon = &lt;&amp;extcon_usbc&gt;;</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy0 {</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usb1_vbus&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_vdd_3v3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-kontron-smarc.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-kontron-smarc.dtsi<br/>new file mode 100644<br/>index 000000000000..1e831d9b8a93<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-kontron-smarc.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-kontron-smarc.dtsi</a></div><div class='hunk'>@@ -0,0 +1,280 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2024 Kontron Electronics GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include "imx8mp-kontron-osm-s.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Kontron SMARC i.MX8MP";</div><div class='add'>+	compatible = "kontron,imx8mp-smarc", "kontron,imx8mp-osm-s", "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led1 {</div><div class='add'>+			label = "led1";</div><div class='add'>+			gpios = &lt;&amp;gpio4 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	tpm@0 {</div><div class='add'>+		compatible = "infineon,slb9670", "tcg,tpm_tis-spi";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;18500000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eqos {	/* Second ethernet (OSM-S ETH_B) */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_eqos_rgmii&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy1&gt;;</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy1: ethernet-phy@1 {</div><div class='add'>+			compatible = "ethernet-phy-id4f51.e91b";</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_ethphy1&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			reset-assert-us = &lt;10000&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio1 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec { /* First ethernet (OSM-S ETH_A) */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_enet_rgmii&gt;;</div><div class='add'>+	phy-connection-type = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@1 {</div><div class='add'>+			compatible = "ethernet-phy-id4f51.e91b";</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_ethphy0&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			reset-assert-us = &lt;10000&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio1 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Rename SoM signals according to SMARC module usage:</div><div class='add'>+ *   GPIO_A_2 -&gt; GPIO0</div><div class='add'>+ *   GPIO_A_3 -&gt; GPIO1</div><div class='add'>+ *   GPIO_A_4 -&gt; GPIO2</div><div class='add'>+ *   GPIO_A_5 -&gt; GPIO3</div><div class='add'>+ *   USB_B_EN -&gt; n.a.</div><div class='add'>+ *   USB_B_ID -&gt; n.a.</div><div class='add'>+ *   USB_B_OC -&gt; n.a.</div><div class='add'>+ */</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	gpio-line-names = "GPIO_A_0", "GPIO_A_1", "", "",</div><div class='add'>+			  "", "GPIO0", "GPIO1", "GPIO2",</div><div class='add'>+			  "GPIO3", "", "USB_A_ID", "",</div><div class='add'>+			  "USB_A_EN", "USB_A_OC","CAM_MCK", "",</div><div class='add'>+			  "ETH_B_MDC", "ETH_B_MDIO", "ETH_B_TXD3", "ETH_B_TXD2",</div><div class='add'>+			  "ETH_B_TXD1", "ETH_B_TXD0", "ETH_B_TX_EN", "ETH_B_TX_CLK",</div><div class='add'>+			  "ETH_B_RX_DV", "ETH_B_RX_CLK", "ETH_B_RXD0", "ETH_B_RXD1",</div><div class='add'>+			  "ETH_B_RXD2", "ETH_B_RXD3";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Rename SoM signals according to SMARC module usage:</div><div class='add'>+ *   SDIO_A_CD -&gt; SDIO_CD</div><div class='add'>+ *   SDIO_A_CLK -&gt; SDIO_CK</div><div class='add'>+ *   SDIO_A_CMD -&gt; SDIO_CMD</div><div class='add'>+ *   SDIO_A_D0 -&gt; SDIO_D0</div><div class='add'>+ *   SDIO_A_D1 -&gt; SDIO_D1</div><div class='add'>+ *   SDIO_A_D2 -&gt; SDIO_D2</div><div class='add'>+ *   SDIO_A_D3 -&gt; SDIO_D3</div><div class='add'>+ *   SDIO_A_PWR_EN -&gt; SDIO_PWR_EN</div><div class='add'>+ *   SDIO_A_WP -&gt; SDIO_WP</div><div class='add'>+ */</div><div class='add'>+&amp;gpio2 {</div><div class='add'>+	gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "",</div><div class='add'>+			  "SDIO_CD", "SDIO_CK", "SDIO_CMD", "SDIO_D0",</div><div class='add'>+			  "SDIO_D1", "SDIO_D2", "SDIO_D3", "SDIO_PWR_EN",</div><div class='add'>+			  "SDIO_WP";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Rename SoM signals according to SMARC module usage:</div><div class='add'>+ *   PCIE_CLKREQ -&gt; PCIE_A_CKREQ</div><div class='add'>+ *   PCIE_A_PERST -&gt; PCIE_A_RST</div><div class='add'>+ *   SDIO_B_D5 -&gt; n.a.</div><div class='add'>+ *   SDIO_B_D6 -&gt; n.a.</div><div class='add'>+ *   SDIO_B_D7 -&gt; n.a.</div><div class='add'>+ *   SPI_A_WP -&gt; n.a.</div><div class='add'>+ *   SPI_A_HOLD -&gt; n.a.</div><div class='add'>+ *   UART_B_RTS -&gt; SER2_RTS</div><div class='add'>+ *   UART_B_CTS -&gt; SER2_CTS</div><div class='add'>+ *   SDIO_B_D0 -&gt; GPIO8</div><div class='add'>+ *   SDIO_B_D1 -&gt; GPIO9</div><div class='add'>+ *   SDIO_B_D2 -&gt; GPIO10</div><div class='add'>+ *   SDIO_B_D3 -&gt; GPIO11</div><div class='add'>+ *   SDIO_B_WP -&gt; n.a.</div><div class='add'>+ *   SDIO_B_D4 -&gt; n.a.</div><div class='add'>+ *   PCIE_SM_ALERT -&gt; SMB_ALERT</div><div class='add'>+ *   SDIO_B_CLK -&gt; GPIO6</div><div class='add'>+ *   SDIO_B_CMD -&gt; GPIO7</div><div class='add'>+ *   GPIO_B_0 -&gt; LCD0_BKLT_EN</div><div class='add'>+ *   GPIO_B_1 -&gt; LCD1_BKLT_EN</div><div class='add'>+ *   BOOT_SEL0 -&gt; BOOT_SEL2</div><div class='add'>+ *   SDIO_B_CD -&gt; n.a.</div><div class='add'>+ *   SDIO_B_PWR_EN -&gt; n.a.</div><div class='add'>+ *   HDMI_CEC -&gt; n.a.</div><div class='add'>+ *   SDIO_B_PWR_EN -&gt; n.a.</div><div class='add'>+ */</div><div class='add'>+&amp;gpio3 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio3&gt;, &lt;&amp;pinctrl_gpio3_smarc&gt;;</div><div class='add'>+	gpio-line-names = "PCIE_WAKE", "PCIE_A_CKREQ", "PCIE_A_RST", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "SER2_RTS", "SER2_CTS", "GPIO8", "GPIO9",</div><div class='add'>+			  "GPIO10", "GPIO11", "", "",</div><div class='add'>+			  "SMB_ALERT", "GPIO6", "GPIO7", "LCD0_BKLT_EN",</div><div class='add'>+			  "LCD1_BKLT_EN", "", "BOOT_SEL2", "BOOT_SEL1",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "HDMI_HPD";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Rename SoM signals according to SMARC module usage:</div><div class='add'>+ *   GPIO_B_5 -&gt; n.a.</div><div class='add'>+ *   GPIO_B_6 -&gt; n.a.</div><div class='add'>+ *   GPIO_B_7 -&gt; n.a.</div><div class='add'>+ *   GPIO_C_0 -&gt; LED</div><div class='add'>+ *   GPIO_B_3 -&gt; ETH2_INT</div><div class='add'>+ *   GPIO_B_4 -&gt; USB_HUB_RST</div><div class='add'>+ *   GPIO_B_2 -&gt; ETH1_INT</div><div class='add'>+ *   GPIO_A_6 -&gt; GPIO4</div><div class='add'>+ *   CAN_A_TX -&gt; CAN0_TX</div><div class='add'>+ *   UART_A_CTS -&gt; SER0_CTS</div><div class='add'>+ *   UART_A_RTS -&gt; SER0_RTS</div><div class='add'>+ *   CAN_A_RX -&gt; CAN0_RX</div><div class='add'>+ *   CAN_B_TX -&gt; CAN1_TX</div><div class='add'>+ *   CAN_B_RX -&gt; CAN1_RX</div><div class='add'>+ *   GPIO_A_7 -&gt; TEST</div><div class='add'>+ *   I2S_A_DATA_IN -&gt; I2S0_SDIN</div><div class='add'>+ *   I2S_LRCLK -&gt; I2S0_LRCK</div><div class='add'>+ */</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	gpio-line-names = "", "", "", "LED",</div><div class='add'>+			  "ETH_A_MDC", "ETH_A_MDIO", "ETH_A_RXD0", "ETH_A_RXD1",</div><div class='add'>+			  "ETH_A_RXD2", "ETH_A_RXD3", "ETH_A_RX_DV", "ETH_A_RX_CLK",</div><div class='add'>+			  "ETH_A_TXD0", "ETH_A_TXD1", "ETH_A_TXD2", "ETH_A_TXD3",</div><div class='add'>+			  "ETH_A_TX_EN", "ETH_A_TX_CLK", "ETH2_INT", "USB_HUB_RST",</div><div class='add'>+			  "ETH1_INT", "GPIO4", "CAN0_TX", "SER0_CTS",</div><div class='add'>+			  "SER0_RTS", "CAN0_RX", "CAN1_TX", "CAN1_RX",</div><div class='add'>+			  "TEST", "CARRIER_PWR_EN", "I2S0_SDIN", "I2S0_LRCK";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Rename SoM signals according to SMARC module usage:</div><div class='add'>+ *   I2S_BITCLK -&gt; I2S0_CK</div><div class='add'>+ *   I2S_A_DATA_OUT -&gt; I2S0_SDOUT</div><div class='add'>+ *   I2S_MCLK -&gt; AUDIO_MCK</div><div class='add'>+ *   PWM_2 -&gt; GPIO5</div><div class='add'>+ *   PWM_1 -&gt; LCD1_BKLT_PWM</div><div class='add'>+ *   PWM_0 -&gt; LCD0_BKLT_PWM</div><div class='add'>+ *   SPI_A_SCK -&gt; SPI0_CK</div><div class='add'>+ *   SPI_A_SDO -&gt; SPI0_DO</div><div class='add'>+ *   SPI_A_SDI -&gt; SPI0_DIN</div><div class='add'>+ *   SPI_A_CS0 -&gt; SPI0_CS0</div><div class='add'>+ *   SPI_B_SCK -&gt; ESPI_CK</div><div class='add'>+ *   SPI_B_SDO -&gt; ESPI_IO_0</div><div class='add'>+ *   SPI_B_SDI -&gt; ESPI_IO_1</div><div class='add'>+ *   SPI_B_CS0 -&gt; ESPI_CS0</div><div class='add'>+ *   I2C_A_SCL -&gt; I2C_PM_CK</div><div class='add'>+ *   I2C_A_SDA -&gt; I2C_PM_DAT</div><div class='add'>+ *   I2C_B_SCL -&gt; I2C_GP_CK</div><div class='add'>+ *   I2C_B_SDA -&gt; I2C_GP_DAT</div><div class='add'>+ *   PCIE_SMCLK -&gt; HDMI_CTRL_CK</div><div class='add'>+ *   PCIE_SMDAT -&gt; HDMI_CTRL_DAT</div><div class='add'>+ *   I2C_CAM_SCL -&gt; I2C_CAM1_CK</div><div class='add'>+ *   I2C_CAM_SDA -&gt; I2C_CAM1_DAT</div><div class='add'>+ *   UART_A_RX -&gt; SER0_RX</div><div class='add'>+ *   UART_A_TX -&gt; SER0_TX</div><div class='add'>+ *   UART_C_RX -&gt; SER3_RX</div><div class='add'>+ *   UART_C_TX -&gt; SER3_TX</div><div class='add'>+ *   UART_CON_RX -&gt; SER1_RX</div><div class='add'>+ *   UART_CON_TX -&gt; SER1_TX</div><div class='add'>+ *   UART_B_RX -&gt; SER2_RX</div><div class='add'>+ *   UART_B_TX -&gt; SER2_TX</div><div class='add'>+ */</div><div class='add'>+&amp;gpio5 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio5_smarc&gt;;</div><div class='add'>+	gpio-line-names = "I2S0_CK", "I2S0_SDOUT", "AUDIO_MCK", "GPIO5",</div><div class='add'>+			  "LCD1_BKLT_PWM", "LCD0_BKLT_PWM", "SPI0_CK", "SPI0_DO",</div><div class='add'>+			  "SPI0_DIN", "SPI0_CS0", "ESPI_CK", "ESPI_IO_0",</div><div class='add'>+			  "ESPI_IO_1", "ESPI_CS0", "I2C_PM_CK", "I2C_PM_DAT",</div><div class='add'>+			  "I2C_GP_CK", "I2C_GP_DAT", "HDMI_CTRL_CK", "HDMI_CTRL_DAT",</div><div class='add'>+			  "I2C_CAM1_CK", "I2C_CAM1_DAT", "SER0_RX", "SER0_TX",</div><div class='add'>+			  "SER3_RX", "SER3_TX", "SER1_RX", "SER1_TX",</div><div class='add'>+			  "SER2_RX", "SER2_TX";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_1 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	usb-hub@1 {</div><div class='add'>+		compatible = "usb424,2514";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio4 19 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_1 {</div><div class='add'>+	fsl,disable-port-power-control;</div><div class='add'>+	fsl,permanently-attached;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_ethphy0: ethphy0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01		0x46</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ethphy1: ethphy1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00		0x46</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio3_smarc: gpio3smarcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__GPIO3_IO10		0x1d0 /* SMARC GPIO8 */</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__GPIO3_IO11		0x1d0 /* SMARC GPIO9 */</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__GPIO3_IO12		0x1d0 /* SMARC GPIO10 */</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__GPIO3_IO13		0x1d0 /* SMARC GPIO11 */</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__GPIO3_IO17		0x190 /* SMARC GPIO6 */</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__GPIO3_IO18		0x1d0 /* SMARC GPIO7 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio5_smarc: gpio5smarcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04		0x1d0 /* SMARC GPIO5 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtso b/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtso<br/>new file mode 100644<br/>index 000000000000..1dcf249ca90d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtso</a></div><div class='hunk'>@@ -0,0 +1,44 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2025 PHYTEC Messtechnik GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/imx8mp-clock.h&gt;</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+&amp;backlight_lvds0 {</div><div class='add'>+	brightness-levels = &lt;0 8 16 32 64 128 255&gt;;</div><div class='add'>+	default-brightness-level = &lt;8&gt;;</div><div class='add'>+	enable-gpios = &lt;&amp;gpio5 23 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	num-interpolated-steps = &lt;2&gt;;</div><div class='add'>+	pwms = &lt;&amp;pwm1 0 66667 0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lvds_bridge {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_MEDIA_LDB&gt;, &lt;&amp;clk IMX8MP_VIDEO_PLL1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_VIDEO_PLL1_OUT&gt;;</div><div class='add'>+	/*</div><div class='add'>+	 * The LVDS panel uses 72.4 MHz pixel clock, set IMX8MP_VIDEO_PLL1 to</div><div class='add'>+	 * 72.4 * 7 = 506.8 MHz so the LDB serializer and LCDIFv3 scanout</div><div class='add'>+	 * engine can reach accurate pixel clock of exactly 72.4 MHz.</div><div class='add'>+	 */</div><div class='add'>+	assigned-clock-rates = &lt;0&gt;, &lt;506800000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;panel0_lvds {</div><div class='add'>+	compatible = "edt,etml1010g3dra";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc.dts b/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc.dts<br/>new file mode 100644<br/>index 000000000000..6f3a7b863dca<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc.dts</a></div><div class='hunk'>@@ -0,0 +1,290 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2025 PHYTEC Messtechnik GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/leds/leds-pca9532.h&gt;</div><div class='add'>+#include &lt;dt-bindings/phy/phy-imx8-pcie.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pwm/pwm.h&gt;</div><div class='add'>+#include "imx8mp-phycore-fpsc.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "phytec,imx8mp-libra-rdk-fpsc",</div><div class='add'>+		     "phytec,imx8mp-phycore-fpsc", "fsl,imx8mp";</div><div class='add'>+	model = "PHYTEC i.MX8MP Libra RDK FPSC";</div><div class='add'>+</div><div class='add'>+	backlight_lvds0: backlight0 {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_lvds0&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		power-supply = &lt;&amp;reg_vdd_12v0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart4;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	panel0_lvds: panel-lvds {</div><div class='add'>+		/* compatible panel in overlay */</div><div class='add'>+		backlight = &lt;&amp;backlight_lvds0&gt;;</div><div class='add'>+		power-supply = &lt;&amp;reg_vdd_3v3&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			panel0_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;ldb_lvds_ch0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_can1_stby: regulator-can1-stby {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-name = "can1-stby";</div><div class='add'>+		gpio = &lt;&amp;gpio_expander 10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_can2_stby: regulator-can2-stby {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-name = "can2-stby";</div><div class='add'>+		gpio = &lt;&amp;gpio_expander 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vdd_12v0: regulator-vdd-12v0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-max-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-name = "VDD_12V0";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vdd_1v8: regulator-vdd-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-name = "VDD_1V8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vdd_3v3: regulator-vdd-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "VDD_3V3";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vdd_5v0: regulator-vdd-5v0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-name = "VDD_5V0";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eqos {</div><div class='add'>+	phy-handle = &lt;&amp;ethphy1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy1: ethernet-phy@1 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;0x1&gt;;</div><div class='add'>+			enet-phy-lane-no-swap;</div><div class='add'>+			ti,clk-output-sel = &lt;DP83867_CLK_O_SEL_OFF&gt;;</div><div class='add'>+			ti,fifo-depth = &lt;DP83867_PHYCR_FIFO_DEPTH_4_B_NIB&gt;;</div><div class='add'>+			ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_1_50_NS&gt;;</div><div class='add'>+			ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_1_50_NS&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* CAN FD */</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	xceiver-supply = &lt;&amp;reg_can1_stby&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan2 {</div><div class='add'>+	xceiver-supply = &lt;&amp;reg_can2_stby&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexspi {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	spi_nor: flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;80000000&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;1&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_vdd_1v8&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio5 {</div><div class='add'>+	gpio-line-names = "", "", "", "", "I2C5_SDA",</div><div class='add'>+			  "GPIO1", "", "", "", "SPI1_CS",</div><div class='add'>+			  "", "", "", "SPI2_CS", "I2C1_SCL",</div><div class='add'>+			  "I2C1_SDA", "I2C2_SCL", "I2C2_SDA", "I2C3_SCL", "I2C3_SDA",</div><div class='add'>+			  "", "GPIO2", "", "LVDS1_BL_EN", "SPI3_CS",</div><div class='add'>+			  "", "GPIO3";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	eeprom@51 {</div><div class='add'>+		compatible = "atmel,24c02";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_vdd_1v8&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	leds@62 {</div><div class='add'>+		compatible = "nxp,pca9533";</div><div class='add'>+		reg = &lt;0x62&gt;;</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			type = &lt;PCA9532_TYPE_LED&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-2 {</div><div class='add'>+			type = &lt;PCA9532_TYPE_LED&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-3 {</div><div class='add'>+			type = &lt;PCA9532_TYPE_LED&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c5 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	gpio_expander: gpio@20 {</div><div class='add'>+		compatible = "ti,tca6416";</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;3 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		gpio-line-names = "CSI1_CTRL1", "CSI1_CTRL2", "CSI1_CTRL3",</div><div class='add'>+				  "CSI1_CTRL4", "CSI2_CTRL1", "CSI2_CTRL2",</div><div class='add'>+				  "CSI2_CTRL3", "CSI2_CTRL4", "CLK_EN_AV",</div><div class='add'>+				  "nCAN2_EN", "nCAN1_EN", "PCIE1_nWAKE",</div><div class='add'>+				  "PCIE2_nWAKE", "PCIE2_nALERT_3V3",</div><div class='add'>+				  "UART1_BT_RS_SEL", "UART1_RS232_485_SEL";</div><div class='add'>+		vcc-supply = &lt;&amp;reg_vdd_1v8&gt;;</div><div class='add'>+</div><div class='add'>+		uart1_bt_rs_sel: bt-rs-hog {</div><div class='add'>+			gpios = &lt;14 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			gpio-hog;</div><div class='add'>+			line-name = "UART1_BT_RS_SEL";</div><div class='add'>+			output-low;	/* default RS232/RS485 */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart1_rs232_485_sel: rs232-485-hog {</div><div class='add'>+			gpios = &lt;15 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			gpio-hog;</div><div class='add'>+			line-name = "UART1_RS232_485_SEL";</div><div class='add'>+			output-high;	/* default RS232 */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_lvds0: lvds0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23	0x12</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+	pinctrl_rtc: rtcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25	0x1C0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lvds_bridge {</div><div class='add'>+	ports {</div><div class='add'>+		port@1 {</div><div class='add'>+			ldb_lvds_ch0: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;panel0_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Mini PCIe */</div><div class='add'>+&amp;pcie {</div><div class='add'>+	reset-gpio = &lt;&amp;gpio1 8 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vpcie-supply = &lt;&amp;reg_vdd_3v3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	clocks = &lt;&amp;hsio_blk_ctrl&gt;;</div><div class='add'>+	clock-names = "ref";</div><div class='add'>+	fsl,clkreq-unsupported;</div><div class='add'>+	fsl,refclk-pad-mode = &lt;IMX8_PCIE_REFCLK_PAD_OUTPUT&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_vdd_io {</div><div class='add'>+	regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;rv3028 {</div><div class='add'>+	interrupt-parent = &lt;&amp;gpio5&gt;;</div><div class='add'>+	interrupts = &lt;25 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	aux-voltage-chargeable = &lt;1&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_rtc&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	trickle-resistor-ohms = &lt;3000&gt;;</div><div class='add'>+	wakeup-source;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;snvs_pwrkey {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* debug console */</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SD-Card */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_USDHC2&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;200000000&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-14N0600E.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-14N0600E.dtsi<br/>new file mode 100644<br/>index 000000000000..2f5cc013e8d6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-14N0600E.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-14N0600E.dtsi</a></div><div class='hunk'>@@ -0,0 +1,68 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2022 Avnet Embedded GmbH</div><div class='add'>+ */</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mp-msc-sm2s.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x40000000 0 0x80000000&gt;; /* bank0, 2GiB */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu_alert0 {</div><div class='add'>+	temperature = &lt;95000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu_crit0 {</div><div class='add'>+	temperature = &lt;105000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;soc_alert0 {</div><div class='add'>+	temperature = &lt;95000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;soc_crit0 {</div><div class='add'>+	temperature = &lt;105000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tca6424 {</div><div class='add'>+	gbe0-int-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		input;</div><div class='add'>+		gpios = &lt;3 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gbe1-int-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		input;</div><div class='add'>+		gpios = &lt;4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cam2-rst-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		output-high;</div><div class='add'>+		gpios = &lt;9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cam2-pwr-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		output-high;</div><div class='add'>+		gpios = &lt;10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	tpm-int-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		input;</div><div class='add'>+		gpios = &lt;13 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wifi-int-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		input;</div><div class='add'>+		gpios = &lt;14 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts b/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts<br/>new file mode 100644<br/>index 000000000000..83194ea7cb81<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts</a></div><div class='hunk'>@@ -0,0 +1,148 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2022 Avnet Embedded GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mp-msc-sm2s-14N0600E.dtsi"</div><div class='add'>+#include &lt;dt-bindings/clock/imx8mp-clock.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "MSC SM2-MB-EP1 Carrier Board with SM2S-IMX8PLUS-QC6-14N0600E SoM";</div><div class='add'>+	compatible = "avnet,sm2s-imx8mp-14N0600E-ep1",</div><div class='add'>+		     "avnet,sm2s-imx8mp-14N0600E", "avnet,sm2s-imx8mp",</div><div class='add'>+		     "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	reg_vcc_3v3_audio: 3v3-audio-regulator {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCC_3V3_AUD";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc_1v8_audio: 1v8-audio-regulator {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCC_1V8_AUD";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,name = "sgtl5000-audio";</div><div class='add'>+		simple-audio-card,format = "i2s";</div><div class='add'>+		simple-audio-card,frame-master = &lt;&amp;codec_dai&gt;;</div><div class='add'>+		simple-audio-card,bitclock-master = &lt;&amp;codec_dai&gt;;</div><div class='add'>+</div><div class='add'>+		simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;sai2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		codec_dai: simple-audio-card,codec {</div><div class='add'>+			sound-dai = &lt;&amp;sgtl5000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_pvi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hdmi&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	sgtl5000: audio-codec@a {</div><div class='add'>+		compatible = "fsl,sgtl5000";</div><div class='add'>+		reg = &lt;0x0a&gt;;</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX8MP_CLK_CLKOUT1_SEL&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;&amp;clk IMX8MP_CLK_24M&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;24000000&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX8MP_CLK_CLKOUT1&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		VDDA-supply = &lt;&amp;reg_vcc_3v3_audio&gt;;</div><div class='add'>+		VDDD-supply = &lt;&amp;reg_vcc_1v8_audio&gt;;</div><div class='add'>+		VDDIO-supply = &lt;&amp;reg_vcc_1v8_audio&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* I2S-0 = sai2 */</div><div class='add'>+&amp;sai2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai2&gt;;</div><div class='add'>+</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_SAI2&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;12288000&gt;;</div><div class='add'>+</div><div class='add'>+	fsl,sai-mclk-direction-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	no-1-8-v;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_smarc_gpio&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl_hdmi: hdmigrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL	0x1c2</div><div class='add'>+			MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA	0x1c2</div><div class='add'>+			MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC		0x10</div><div class='add'>+			MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD		0x10</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai2: sai2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC   0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK    0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_smarc_gpio: smarcgpiosgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11	0x19&gt;, /* GPIO0 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01	0x19&gt;, /* GPIO1 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02	0x19&gt;, /* GPIO2 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03	0x19&gt;, /* GPIO3 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29	0x19&gt;, /* GPIO4 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02	0x19&gt;, /* GPIO5 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18	0x19&gt;, /* GPIO6 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10	0x19&gt;, /* GPIO7 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20	0x19&gt;, /* GPIO8 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21	0x19&gt;, /* GPIO9 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22	0x19&gt;, /* GPIO10 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28	0x19&gt;, /* GPIO11 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19	0x19&gt;, /* GPIO12 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00	0x19&gt;; /* GPIO13 */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s.dtsi<br/>new file mode 100644<br/>index 000000000000..0fd5c3abcdb7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s.dtsi</a></div><div class='hunk'>@@ -0,0 +1,838 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2022 Avnet Embedded GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mp.dtsi"</div><div class='add'>+#include &lt;dt-bindings/net/ti-dp83867.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		rtc0 = &amp;sys_rtc;</div><div class='add'>+		rtc1 = &amp;snvs_rtc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb0_host_vbus: regulator-usb0-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "usb0_host_vbus";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usb0_vbus&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio1 12 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb1_host_vbus: regulator-usb1-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "usb1_host_vbus";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usb1_vbus&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio1 14 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usdhc2_vmmc&gt;;</div><div class='add'>+		regulator-name = "VSD_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio2 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		startup-delay-us = &lt;100&gt;;</div><div class='add'>+		off-on-delay-us = &lt;12000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_flexcan1_xceiver: regulator-flexcan1 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "flexcan1-xceiver";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_flexcan2_xceiver: regulator-flexcan2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "flexcan2-xceiver";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lcd0_backlight: backlight-0 {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_lcd0_backlight&gt;;</div><div class='add'>+		pwms = &lt;&amp;pwm1 0 100000 0&gt;;</div><div class='add'>+		brightness-levels = &lt;0 255&gt;;</div><div class='add'>+		num-interpolated-steps = &lt;255&gt;;</div><div class='add'>+		default-brightness-level = &lt;255&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;gpio1 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lcd1_backlight: backlight-1 {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_lcd1_backlight&gt;;</div><div class='add'>+		pwms = &lt;&amp;pwm2 0 100000 0&gt;;</div><div class='add'>+		brightness-levels = &lt;0 255&gt;;</div><div class='add'>+		num-interpolated-steps = &lt;255&gt;;</div><div class='add'>+		default-brightness-level = &lt;255&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;gpio1 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_leds&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+</div><div class='add'>+		led-sw {</div><div class='add'>+			label = "sw-led";</div><div class='add'>+			gpios = &lt;&amp;gpio1 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	extcon_usb0: extcon-usb0 {</div><div class='add'>+		compatible = "linux,extcon-usb-gpio";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usb0_extcon&gt;;</div><div class='add'>+		id-gpios = &lt;&amp;gpio1 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;vcc_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;vcc_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;vcc_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;vcc_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi1 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi1&gt;;</div><div class='add'>+	cs-gpios = &lt;0&gt;, &lt;&amp;gpio2 8 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi2 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi2&gt;;</div><div class='add'>+	cs-gpios = &lt;0&gt;, &lt;&amp;gpio2 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eqos {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_eqos&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@1 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			eee-broken-1000t;</div><div class='add'>+			reset-gpios = &lt;&amp;tca6424 16 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;1000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;1000&gt;;</div><div class='add'>+			ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_2_25_NS&gt;;</div><div class='add'>+			ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_2_25_NS&gt;;</div><div class='add'>+			ti,fifo-depth = &lt;DP83867_PHYCR_FIFO_DEPTH_4_B_NIB&gt;;</div><div class='add'>+			ti,clk-output-sel = &lt;DP83867_CLK_O_SEL_OFF&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy1&gt;;</div><div class='add'>+	fsl,magic-packet;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy1: ethernet-phy@1 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			eee-broken-1000t;</div><div class='add'>+			reset-gpios = &lt;&amp;tca6424 17 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;1000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;1000&gt;;</div><div class='add'>+			ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_2_25_NS&gt;;</div><div class='add'>+			ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_2_25_NS&gt;;</div><div class='add'>+			ti,fifo-depth = &lt;DP83867_PHYCR_FIFO_DEPTH_4_B_NIB&gt;;</div><div class='add'>+			ti,clk-output-sel = &lt;DP83867_CLK_O_SEL_OFF&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c1_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	id_eeprom: eeprom@50 {</div><div class='add'>+		compatible = "atmel,24c64";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c4&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c5 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c5&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c6 {</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c6&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c6_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio3 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio3 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	tca6424: gpio@22 {</div><div class='add'>+		compatible = "ti,tca6424";</div><div class='add'>+		reg = &lt;0x22&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_tca6424&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-line-names = "BOOT_SEL0#", "BOOT_SEL1#", "BOOT_SEL2#",</div><div class='add'>+			"gbe0_int", "gbe1_int", "pmic_int", "rtc_int", "lvds_int",</div><div class='add'>+			"PCIE_WAKE#", "cam2_rst", "cam2_pwr", "SLEEP#",</div><div class='add'>+			"wifi_pd", "tpm_int", "wifi_int", "PCIE_A_RST#",</div><div class='add'>+			"gbe0_rst", "gbe1_rst", "LID#", "BATLOW#", "CHARGING#",</div><div class='add'>+			"CHARGER_PRSNT#";</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;9 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dsi_lvds_bridge: bridge@2d {</div><div class='add'>+		compatible = "ti,sn65dsi83";</div><div class='add'>+		reg = &lt;0x2d&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_lvds_bridge&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;gpio1 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmic: pmic@30 {</div><div class='add'>+		compatible = "ricoh,rn5t567";</div><div class='add'>+		reg = &lt;0x30&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;tca6424&gt;;</div><div class='add'>+		interrupts = &lt;5 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			DCDC1 {</div><div class='add'>+				regulator-name = "VCC_SOC";</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;950000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;950000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			DCDC2 {</div><div class='add'>+				regulator-name = "VCC_DRAM";</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vcc_arm: DCDC3 {</div><div class='add'>+				regulator-name = "VCC_ARM";</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;950000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;950000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			DCDC4 {</div><div class='add'>+				regulator-name = "VCC_1V8";</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			LDO1 {</div><div class='add'>+				regulator-name = "VCC_LDO1_2V5";</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;2500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2500000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			LDO2 {</div><div class='add'>+				regulator-name = "VCC_LDO2_1V8";</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			LDO3 {</div><div class='add'>+				regulator-name = "VCC_ETH_2V5";</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;2500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2500000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			LDO4 {</div><div class='add'>+				regulator-name = "VCC_DDR4_2V5";</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;2500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2500000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			LDO5 {</div><div class='add'>+				regulator-name = "VCC_LDO5_1V8";</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			LDORTC1 {</div><div class='add'>+				regulator-name = "VCC_SNVS_1V8";</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			LDORTC2 {</div><div class='add'>+				regulator-name = "VCC_SNVS_3V3";</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sys_rtc: rtc@32 {</div><div class='add'>+		compatible = "ricoh,r2221tl";</div><div class='add'>+		reg = &lt;0x32&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;tca6424&gt;;</div><div class='add'>+		interrupts = &lt;6 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	tmp_sensor: temperature-sensor@71 {</div><div class='add'>+		compatible = "ti,tmp103";</div><div class='add'>+		reg = &lt;0x71&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan1&gt;;</div><div class='add'>+	xceiver-supply = &lt;&amp;reg_flexcan1_xceiver&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan2&gt;;</div><div class='add'>+	xceiver-supply = &lt;&amp;reg_flexcan2_xceiver&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexspi {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexspi0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	qspi_flash: flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		spi-max-frequency = &lt;80000000&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;4&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm1&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm2&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm3&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm4&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;snvs_pwrkey {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart4&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy0 {</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usb0_host_vbus&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy1 {</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usb1_host_vbus&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_0 {</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	hnp-disable;</div><div class='add'>+	srp-disable;</div><div class='add'>+	adp-disable;</div><div class='add'>+	extcon = &lt;&amp;extcon_usb0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_1 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_USDHC2&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	wp-gpios = &lt;&amp;gpio2 20 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_USDHC3&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_ecspi1: ecspi1grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO		0x82&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI		0x82&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK		0x82&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_ECSPI1_SS0__ECSPI1_SS0		0x40000&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08		0x40000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi2: ecspi2grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO		0x82&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI		0x82&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK		0x82&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_ECSPI2_SS0__ECSPI2_SS0		0x40000&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09		0x40000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_eqos: eqosgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC		0x3&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO		0x3&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0	0x91&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1	0x91&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2	0x91&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3	0x91&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL	0x91&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0	0x1f&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1	0x1f&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2	0x1f&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3	0x1f&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL	0x1f&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec: fecgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0	0x91&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1	0x91&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2	0x91&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3	0x91&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0	0x1f&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1	0x1f&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2	0x1f&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3	0x1f&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC	0x1f&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan1: flexcan1grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX		0x154&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX		0x154&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan2: flexcan2grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX		0x154&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX		0x154&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexspi0: flexspi0grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK		0x1c2&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B	0x82&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00	0x82&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01	0x82&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02	0x82&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03	0x82&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14		0x19&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001e0&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001e0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1_gpio: i2c1gpiogrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14		0x1e0&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15		0x1e0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001e0&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA		0x400001e0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400001e0&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001e0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4: i2c4grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL		0x400001e0&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA		0x400001e0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c5: i2c5grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL		0x400001e0&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA		0x400001e0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c6: i2c6grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL		0x400001e0&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA		0x400001e0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c6_gpio: i2c6gpiogrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19		0x1e0&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20		0x1e0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lcd0_backlight: lcd0-backlightgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05		0x41&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lcd1_backlight: lcd1-backlightgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06		0x41&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_leds: ledsgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08		0x19&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lvds_bridge: lvds-bridgegrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07		0x41&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm1: pwm1grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT		0x116&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm2: pwm2grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT		0x116&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm3: pwm3grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_GPIO1_IO10__PWM3_OUT		0x116&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm4: pwm4grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT		0x116&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_tca6424: tca6424grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09		0x41&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX		0x49&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX		0x49&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06		0x1c4&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07		0x1c4&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX		0x49&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX		0x49&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: uart3grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10		0x1c4&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11		0x1c4&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX		0x49&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX		0x49&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart4: uart4grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX		0x49&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX		0x49&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usb0_extcon: usb0-extcongrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03		0x19&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usb0_vbus: usb0-vbusgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12		0x19&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usb1_vbus: usb1-vbusgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14		0x19&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2-gpiogrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12		0x1c4&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_WP__GPIO2_IO20		0x1c4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x190&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d0&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d0&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d0&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d0&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d0&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_vmmc: usdhc2-vmmcgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19		0x41&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x194&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d4&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d4&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d4&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d4&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d4&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x196&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d6&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d6&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d6&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d6&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d6&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x190&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d0&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d0&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d0&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d0&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d0&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d0&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d0&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d0&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d0&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x190&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d4&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d4&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d4&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d4&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d4&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d4&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d4&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x194&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x196&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d6&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d6&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d6&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d6&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d6&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d6&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d6&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d6&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d6&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x196&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B		0xc6&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-navqp.dts b/arch/arm64/boot/dts/freescale/imx8mp-navqp.dts<br/>new file mode 100644<br/>index 000000000000..4a4f7c1adc23<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-navqp.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-navqp.dts</a></div><div class='hunk'>@@ -0,0 +1,471 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021 Emcraft Systems</div><div class='add'>+ * Copyright 2024 Gilles Talis &lt;gilles.talis@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include "imx8mp.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Emcraft Systems i.MX8MPlus NavQ+ Kit";</div><div class='add'>+	compatible = "emcraft,imx8mp-navqp", "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdmi-connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		label = "J15";</div><div class='add'>+		type = "d";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			hdmi_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_tx_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_led&gt;;</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			gpios = &lt;&amp;gpio3 16 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "on";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usdhc2_vmmc&gt;;</div><div class='add'>+		regulator-name = "VSD_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio2 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		startup-delay-us = &lt;100&gt;;</div><div class='add'>+		off-on-delay-us = &lt;12000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eqos {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_eqos&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@0 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio4 22 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;1000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;10000&gt;;</div><div class='add'>+			qca,disable-smarteee;</div><div class='add'>+			qca,disable-hibernation-mode;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_pvi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hdmi&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@1 {</div><div class='add'>+			hdmi_tx_out: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_connector_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pmic@25 {</div><div class='add'>+		compatible = "nxp,pca9450c";</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;3 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			BUCK1 {</div><div class='add'>+				regulator-name = "BUCK1";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2187500&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck2: BUCK2 {</div><div class='add'>+				regulator-name = "BUCK2";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2187500&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+				nxp,dvs-run-voltage = &lt;950000&gt;;</div><div class='add'>+				nxp,dvs-standby-voltage = &lt;850000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			BUCK4 {</div><div class='add'>+				regulator-name = "BUCK4";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			BUCK5 {</div><div class='add'>+				regulator-name = "BUCK5";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			BUCK6 {</div><div class='add'>+				regulator-name = "BUCK6";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			LDO1 {</div><div class='add'>+				regulator-name = "LDO1";</div><div class='add'>+				regulator-min-microvolt = &lt;1600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			LDO2 {</div><div class='add'>+				regulator-name = "LDO2";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1150000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			LDO3 {</div><div class='add'>+				regulator-name = "LDO3";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			LDO4 {</div><div class='add'>+				regulator-name = "LDO4";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			LDO5 {</div><div class='add'>+				regulator-name = "LDO5";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	rtc@53 {</div><div class='add'>+		compatible = "nxp,pcf2131";</div><div class='add'>+		reg = &lt;0x53&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	/* console */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SD Card */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* eMMC */</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_USDHC3&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_eqos: eqosgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x3</div><div class='add'>+			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x3</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL			0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL			0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f</div><div class='add'>+			MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22				0x110</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio_led: gpioledgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16				0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_hdmi: hdmigrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL			0x1c2</div><div class='add'>+			MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA			0x1c2</div><div class='add'>+			MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD				0x10</div><div class='add'>+			MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC				0x10</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL					0x400001c3</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA					0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL					0x400001c3</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA					0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL					0x400001c3</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA					0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4: i2c4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL					0x400001c3</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA					0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: pmicgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03				0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19				0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX				0x49</div><div class='add'>+			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX				0x49</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK				0x190</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD				0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0				0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1				0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2				0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3				0x1d0</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT				0xc1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK				0x194</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD				0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0				0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1				0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2				0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3				0x1d4</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT				0xc1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK				0x196</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD				0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0				0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1				0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2				0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3				0x1d6</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT				0xc1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12				0x1c4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK				0x190</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD				0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0				0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1				0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2				0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3				0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4				0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5				0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6				0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7				0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE				0x190</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK				0x194</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD				0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0				0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1				0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2				0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3				0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4				0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5				0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6				0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7				0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE				0x194</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK				0x196</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD				0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0				0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1				0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2				0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3				0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4				0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5				0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6				0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7				0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE				0x196</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B				0xc6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-enc-carrier-board.dts b/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-enc-carrier-board.dts<br/>new file mode 100644<br/>index 000000000000..1df9488aaeb2<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-enc-carrier-board.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-nitrogen-enc-carrier-board.dts</a></div><div class='hunk'>@@ -0,0 +1,452 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2020 Boundary Devices</div><div class='add'>+ * Copyright 2025 Collabora Ltd.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mp-nitrogen-som.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Boundary Devices Nitrogen8M Plus ENC Carrier Board";</div><div class='add'>+	compatible = "boundary,imx8mp-nitrogen-enc-carrier-board",</div><div class='add'>+			"boundary,imx8mp-nitrogen-som", "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	connector {</div><div class='add'>+		compatible = "usb-c-connector";</div><div class='add'>+		data-role = "dual";</div><div class='add'>+		label = "USB-C";</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				hs_ep: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;usb3_hs_ep&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				ss_ep: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;hd3ss3220_in_ep&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdmi-connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		label = "hdmi";</div><div class='add'>+		type = "a";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			hdmi_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_tx_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb_vbus: regulator {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;gpio1 12 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usb_vbus&gt;;</div><div class='add'>+		regulator-name = "usb_vbus";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi2 {</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 13 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi2&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	usb-hub-reset-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		line-name = "usb-hub-reset";</div><div class='add'>+		output-low;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_pvi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hdmi&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@1 {</div><div class='add'>+			hdmi_tx_out: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_connector_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	i2c-mux@70 {</div><div class='add'>+		compatible = "nxp,pca9546";</div><div class='add'>+		reg = &lt;0x70&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_i2c2_pca9546&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		reset-gpios = &lt;&amp;gpio1 5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		i2c@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			clock-frequency = &lt;100000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			clock-frequency = &lt;100000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@2 {</div><div class='add'>+			reg = &lt;2&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			clock-frequency = &lt;100000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@3 {</div><div class='add'>+			reg = &lt;3&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			clock-frequency = &lt;100000&gt;;</div><div class='add'>+</div><div class='add'>+			rtc@52 {</div><div class='add'>+				compatible = "microcrystal,rv3028";</div><div class='add'>+				reg = &lt;0x52&gt;;</div><div class='add'>+				interrupts-extended = &lt;&amp;gpio1 4 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;pinctrl_rv3028&gt;;</div><div class='add'>+				wakeup-source;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	usb-mux@47 {</div><div class='add'>+		compatible = "ti,hd3ss3220";</div><div class='add'>+		reg = &lt;0x47&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;gpio1 8 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_i2c4_hd3ss3220&gt;;</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				hd3ss3220_in_ep: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;ss_ep&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				hd3ss3220_out_ep: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;usb3_role_switch&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;isp_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;snvs_pwrkey {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_UART3&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL1_80M&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_UART4&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL1_80M&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_0 {</div><div class='add'>+	fsl,over-current-active-low;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy0 {</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usb_vbus&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy1 {</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usb_vbus&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_0 {</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usb3_0&gt;;</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		port@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			usb3_hs_ep: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hs_ep&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			usb3_role_switch: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hd3ss3220_out_ep&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_1 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio2 11 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;, &lt;&amp;pinctrl_usdhc1_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1_100mhz&gt;, &lt;&amp;pinctrl_usdhc1_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1_200mhz&gt;, &lt;&amp;pinctrl_usdhc1_gpio&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hog&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi2: ecspi2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO		0x82</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI		0x82</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK		0x82</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13		0x143</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_hdmi: hdmigrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC		0x40000019</div><div class='add'>+			MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL	0x400001c3</div><div class='add'>+			MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA	0x400001c3</div><div class='add'>+			MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD		0x40000019</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_hog: hoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06		0x100</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07		0x119</div><div class='add'>+			MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20		0x16</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19		0x1c4</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06		0x41</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07		0x41</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08		0x41</div><div class='add'>+			MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10		0x41</div><div class='add'>+			MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05		0x41</div><div class='add'>+			MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04		0x41</div><div class='add'>+			MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03		0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2_pca9546: i2c2-pca9546grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05		0x100</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4_hd3ss3220: i2c4-hd3ss3220grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08		0x16</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02		0x03</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm1: pwm1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT		0x100</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm2: pwm2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO09__PWM2_OUT		0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT		0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm4: pwm4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+		MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT			0x116</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usb_vbus: reg-usb-vbusgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12		0x100</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_rv3028: rv3028grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04		0x1c0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX		0x140</div><div class='add'>+			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX		0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: uart3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX		0x140</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX		0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart4: uart4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX		0x140</div><div class='add'>+			MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX		0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usb3_0: usb3-0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC		0x1c0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO03__USDHC1_VSELECT		0x116</div><div class='add'>+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x190</div><div class='add'>+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x194</div><div class='add'>+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x196</div><div class='add'>+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_gpio: usdhc1-gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11		0x1c4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-smarc-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-smarc-som.dtsi<br/>new file mode 100644<br/>index 000000000000..5da0f1b3ed8a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-smarc-som.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-nitrogen-smarc-som.dtsi</a></div><div class='hunk'>@@ -0,0 +1,348 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Boundary Devices</div><div class='add'>+ * Copyright 2024 Silicon Signals Pvt. Ltd.</div><div class='add'>+ *</div><div class='add'>+ * Author : Bhavin Sharma &lt;bhavin.sharma@siliconsignals.io&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include "imx8mp.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Boundary Device Nitrogen8MP SMARC SoM";</div><div class='add'>+	compatible = "boundary,imx8mp-nitrogen-smarc-som", "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_led&gt;;</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			function = LED_FUNCTION_POWER;</div><div class='add'>+			gpios = &lt;&amp;gpio1 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {</div><div class='add'>+	        compatible = "regulator-fixed";</div><div class='add'>+	        regulator-name = "VSD_3V3";</div><div class='add'>+	        regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+	        regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	        gpios = &lt;&amp;gpio2 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	        enable-active-high;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+        cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+        cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+        cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+        cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pmic@25 {</div><div class='add'>+		compatible = "nxp,pca9450c";</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;14 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			buck1: BUCK1 {</div><div class='add'>+				regulator-name = "BUCK1";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2187500&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck2: BUCK2 {</div><div class='add'>+				regulator-name = "BUCK2";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2187500&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+				nxp,dvs-run-voltage = &lt;950000&gt;;</div><div class='add'>+				nxp,dvs-standby-voltage = &lt;850000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck4: BUCK4 {</div><div class='add'>+				regulator-name = "BUCK4";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck5: BUCK5 {</div><div class='add'>+				regulator-name = "BUCK5";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck6: BUCK6 {</div><div class='add'>+				regulator-name = "BUCK6";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo1: LDO1 {</div><div class='add'>+				regulator-name = "LDO1";</div><div class='add'>+				regulator-min-microvolt = &lt;1600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo2: LDO2 {</div><div class='add'>+				regulator-name = "LDO2";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1150000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo3: LDO3 {</div><div class='add'>+				regulator-name = "LDO3";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo4: LDO4 {</div><div class='add'>+				regulator-name = "LDO4";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo5: LDO5 {</div><div class='add'>+				regulator-name = "LDO5";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c6 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c6&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mcp23018: gpio@20 {</div><div class='add'>+		compatible = "microchip,mcp23018";</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;0x2&gt;;</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;gpio4 22 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;0x2&gt;;</div><div class='add'>+		microchip,irq-mirror;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_mcp23018&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio4 27 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Console */</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SD-card */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* eMMC */</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1_200mhz&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_gpio_led: gpioledgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+		        MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10                     	0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL					0x400001c3</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA					0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c6: i2c6grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+		        MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL            			0x400001c3</div><div class='add'>+		        MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA                 		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_mcp23018: mcp23018grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+		        MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22            			0x1c0</div><div class='add'>+			MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27             			0x100</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: pmicgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14				0x1c0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX                            0x40</div><div class='add'>+			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX                            0x40</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK        			0x10</div><div class='add'>+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD        			0x150</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0    			0x150</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1    			0x150</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2    			0x150</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3    			0x150</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA4__USDHC1_DATA4    			0x150</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA5__USDHC1_DATA5    			0x150</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA6__USDHC1_DATA6    			0x150</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA7__USDHC1_DATA7    			0x150</div><div class='add'>+			MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE  			0x10</div><div class='add'>+			MX8MP_IOMUXC_SD1_RESET_B__USDHC1_RESET_B 			0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK        			0x14</div><div class='add'>+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD        			0x154</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0    			0x154</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1    			0x154</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2    			0x154</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3    			0x154</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA4__USDHC1_DATA4    			0x154</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA5__USDHC1_DATA5    			0x154</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA6__USDHC1_DATA6    			0x154</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA7__USDHC1_DATA7    			0x154</div><div class='add'>+			MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE  			0x14</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK        			0x12</div><div class='add'>+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD        			0x152</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0    			0x152</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1    			0x152</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2    			0x152</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3    			0x152</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA4__USDHC1_DATA4    			0x152</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA5__USDHC1_DATA5    			0x152</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA6__USDHC1_DATA6    			0x152</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA7__USDHC1_DATA7    			0x152</div><div class='add'>+			MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE  			0x12</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK                                0x190</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD                                0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0                            0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1                            0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2                            0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3                            0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK                                0x194</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD                                0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0                            0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1                            0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2                            0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3                            0x1d4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK                                0x196</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD                                0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0                            0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1                            0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2                            0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3                            0x1d6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B				0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-smarc-universal-board.dts b/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-smarc-universal-board.dts<br/>new file mode 100644<br/>index 000000000000..46b243218dc8<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-smarc-universal-board.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-nitrogen-smarc-universal-board.dts</a></div><div class='hunk'>@@ -0,0 +1,17 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Boundary Devices</div><div class='add'>+ * Copyright 2024 Silicon Signals Pvt. Ltd.</div><div class='add'>+ *</div><div class='add'>+ * Author : Bhavin Sharma &lt;bhavin.sharma@siliconsignals.io&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mp-nitrogen-smarc-som.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Boundary Device Nitrogen8MP Universal SMARC Carrier Board";</div><div class='add'>+	compatible = "boundary,imx8mp-nitrogen-smarc-universal-board",</div><div class='add'>+			"boundary,imx8mp-nitrogen-smarc-som", "fsl,imx8mp";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-som.dtsi<br/>new file mode 100644<br/>index 000000000000..f658309612ef<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-som.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-nitrogen-som.dtsi</a></div><div class='hunk'>@@ -0,0 +1,409 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2020 Boundary Devices</div><div class='add'>+ * Copyright 2025 Collabora Ltd.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "imx8mp.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Boundary Devices Nitrogen8M Plus Som";</div><div class='add'>+	compatible = "boundary,imx8mp-nitrogen-som", "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	rfkill-bt {</div><div class='add'>+		compatible = "rfkill-gpio";</div><div class='add'>+		label = "rfkill-bluetooth";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_rfkill_bt&gt;;</div><div class='add'>+		radio-type = "bluetooth";</div><div class='add'>+		shutdown-gpios = &lt;&amp;gpio3 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rfkill-wlan {</div><div class='add'>+		compatible = "rfkill-gpio";</div><div class='add'>+		label = "rfkill-wlan";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_rfkill_wlan&gt;;</div><div class='add'>+		radio-type = "wlan";</div><div class='add'>+		shutdown-gpios = &lt;&amp;gpio2 19 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eqos {</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_eqos&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@4 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;4&gt;;</div><div class='add'>+			eee-broken-1000t;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c1_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 14 GPIO_OPEN_DRAIN&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 15 GPIO_OPEN_DRAIN&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pmic: pmic@25 {</div><div class='add'>+		compatible = "nxp,pca9450c";</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+		interrupts = &lt;0 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+</div><div class='add'>+			buck1: BUCK1 {</div><div class='add'>+				regulator-name = "VDD_SOC (BUCK1)";</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;2187500&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck2: BUCK2 {</div><div class='add'>+				regulator-name = "VDD_ARM (BUCK2)";</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;2187500&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck4: BUCK4 {</div><div class='add'>+				regulator-name = "VDD_3P3V (BUCK4)";</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;3400000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck5: BUCK5 {</div><div class='add'>+				regulator-name = "VDD_1P8V (BUCK5)";</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;3400000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck6: BUCK6 {</div><div class='add'>+				regulator-name = "NVCC_DRAM_1P1V (BUCK6)";</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;3400000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo1: LDO1 {</div><div class='add'>+				regulator-name = "NVCC_SNVS_1V8 (LDO1)";</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1600000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo3: LDO3 {</div><div class='add'>+				regulator-name = "VDDA_1V8 (LDO3)";</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo5: LDO5 {</div><div class='add'>+				regulator-name = "NVCC_SD1 (LDO5)";</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c2_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 16 GPIO_OPEN_DRAIN&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 17 GPIO_OPEN_DRAIN&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c3_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 18 GPIO_OPEN_DRAIN&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 19 GPIO_OPEN_DRAIN&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c4&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c4_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 20 GPIO_OPEN_DRAIN&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 21 GPIO_OPEN_DRAIN&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	keep-power-in-suspend;</div><div class='add'>+	non-removable;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	no-mmc-hs400;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_eqos: eqosgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x20</div><div class='add'>+			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0xa0</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL			0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL			0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f</div><div class='add'>+</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__GPIO3_IO02				0x10</div><div class='add'>+			MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16				0x100</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1_gpio: i2c1gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14	0x1c3</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15	0x1c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c3</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2_gpio: i2c2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16	0x1c3</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17	0x1c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001c3</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3_gpio: i2c3gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18	0x1c3</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19	0x1c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400001c3</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4_gpio: i2c4gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20	0x1c3</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21	0x1c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4: i2c4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL		0x400001c3</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: pmicirqgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_rfkill_bt: rfkill-btgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09	0x119</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_rfkill_wlan: rfkill-wlangrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x16</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX	0x140</div><div class='add'>+			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX	0x140</div><div class='add'>+			MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS	0x140</div><div class='add'>+			MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x190</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x194</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x196</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x10</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x150</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x150</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x150</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x150</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x150</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x150</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x150</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x150</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x150</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01	0x140</div><div class='add'>+</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x14</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x154</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x154</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x154</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x154</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x154</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x154</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x154</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x154</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x154</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x12</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x152</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x152</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x152</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x152</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x152</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x152</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x152</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x152</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x152</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B	0xc6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-nominal.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-nominal.dtsi<br/>new file mode 100644<br/>index 000000000000..f269f7a004fc<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-nominal.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-nominal.dtsi</a></div><div class='hunk'>@@ -0,0 +1,110 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2024 Pengutronix, Ahmad Fatoum &lt;kernel@pengutronix.de&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;clk {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_A53_SRC&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MP_CLK_A53_CORE&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MP_SYS_PLL3&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MP_CLK_NOC&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MP_CLK_NOC_IO&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MP_CLK_GIC&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL1_800M&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MP_ARM_PLL_OUT&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MP_SYS_PLL1_800M&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MP_SYS_PLL3_OUT&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MP_SYS_PLL1_800M&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;0&gt;, &lt;0&gt;,</div><div class='add'>+			       &lt;600000000&gt;,</div><div class='add'>+			       &lt;800000000&gt;,</div><div class='add'>+			       &lt;600000000&gt;,</div><div class='add'>+			       &lt;400000000&gt;;</div><div class='add'>+	fsl,operating-mode = "nominal";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu2d {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_GPU2D_CORE&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL1_800M&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;800000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu3d {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_GPU3D_CORE&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MP_CLK_GPU3D_SHADER_CORE&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL1_800M&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MP_SYS_PLL1_800M&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;800000000&gt;, &lt;800000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pgc_hdmimix {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_HDMI_AXI&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MP_CLK_HDMI_APB&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL1_800M&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MP_SYS_PLL1_133M&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;400000000&gt;, &lt;133000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pgc_hsiomix {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_HSIO_AXI&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL1_800M&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pgc_gpumix {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_GPU_AXI&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MP_CLK_GPU_AHB&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL3_OUT&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MP_SYS_PLL3_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;600000000&gt;, &lt;300000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pgc_mlmix {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_ML_CORE&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MP_CLK_ML_AXI&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MP_CLK_ML_AHB&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL1_800M&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MP_SYS_PLL1_800M&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MP_SYS_PLL1_800M&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;800000000&gt;,</div><div class='add'>+			       &lt;800000000&gt;,</div><div class='add'>+			       &lt;300000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;media_blk_ctrl {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_MEDIA_AXI&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MP_CLK_MEDIA_APB&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MP_CLK_MEDIA_DISP1_PIX&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MP_CLK_MEDIA_DISP2_PIX&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MP_CLK_MEDIA_ISP&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MP_VIDEO_PLL1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL1_800M&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MP_SYS_PLL1_800M&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MP_VIDEO_PLL1_OUT&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MP_VIDEO_PLL1_OUT&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MP_SYS_PLL1_800M&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;400000000&gt;, &lt;200000000&gt;,</div><div class='add'>+			       &lt;0&gt;, &lt;0&gt;, &lt;400000000&gt;,</div><div class='add'>+			       &lt;1039500000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;vpu_g1 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_VPU_G1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_VPU_PLL_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;600000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;vpu_g2 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_VPU_G2&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL2_1000M&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;500000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;vpumix_blk_ctrl {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_VPU_PLL&gt;, &lt;&amp;clk IMX8MP_CLK_VPU_BUS&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;0&gt;, &lt;&amp;clk IMX8MP_VPU_PLL_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;600000000&gt;, &lt;600000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/delete-node/ &amp;{noc_opp_table/opp-1000000000};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-etml1010g3dra.dtso b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-etml1010g3dra.dtso<br/>new file mode 100644<br/>index 000000000000..7a7f27d6bb1b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-etml1010g3dra.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-etml1010g3dra.dtso</a></div><div class='hunk'>@@ -0,0 +1,44 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2025 PHYTEC Messtechnik GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/imx8mp-clock.h&gt;</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+&amp;backlight_lvds1 {</div><div class='add'>+	brightness-levels = &lt;0 8 16 32 64 128 255&gt;;</div><div class='add'>+	default-brightness-level = &lt;8&gt;;</div><div class='add'>+	enable-gpios = &lt;&amp;gpio2 20 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	num-interpolated-steps = &lt;2&gt;;</div><div class='add'>+	pwms = &lt;&amp;pwm3 0 50000 0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lvds_bridge {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_MEDIA_LDB&gt;, &lt;&amp;clk IMX8MP_VIDEO_PLL1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_VIDEO_PLL1_OUT&gt;;</div><div class='add'>+	/*</div><div class='add'>+	 * The LVDS panel uses 72.4 MHz pixel clock, set IMX8MP_VIDEO_PLL1 to</div><div class='add'>+	 * 72.4 * 7 = 506.8 MHz so the LDB serializer and LCDIFv3 scanout</div><div class='add'>+	 * engine can reach accurate pixel clock of exactly 72.4 MHz.</div><div class='add'>+	 */</div><div class='add'>+	assigned-clock-rates = &lt;0&gt;, &lt;506800000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;panel_lvds1 {</div><div class='add'>+	compatible = "edt,etml1010g3dra";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10-etml1010g3dra.dtso b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10-etml1010g3dra.dtso<br/>new file mode 100644<br/>index 000000000000..aceb5b6056ef<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10-etml1010g3dra.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10-etml1010g3dra.dtso</a></div><div class='hunk'>@@ -0,0 +1,45 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2025 PHYTEC Messtechnik GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/imx8mp-clock.h&gt;</div><div class='add'>+#include "imx8mp-phyboard-pollux-peb-av-10.dtsi"</div><div class='add'>+</div><div class='add'>+&amp;backlight_lvds0 {</div><div class='add'>+	brightness-levels = &lt;0 8 16 32 64 128 255&gt;;</div><div class='add'>+	default-brightness-level = &lt;8&gt;;</div><div class='add'>+	enable-gpios = &lt;&amp;gpio5 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	num-interpolated-steps = &lt;2&gt;;</div><div class='add'>+	pwms = &lt;&amp;pwm4 0 50000 0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lvds_bridge {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_MEDIA_LDB&gt;, &lt;&amp;clk IMX8MP_VIDEO_PLL1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_VIDEO_PLL1_OUT&gt;;</div><div class='add'>+	/*</div><div class='add'>+	 * The LVDS panel uses 72.4 MHz pixel clock, set IMX8MP_VIDEO_PLL1 to</div><div class='add'>+	 * 72.4 * 7 = 506.8 MHz so the LDB serializer and LCDIFv3 scanout</div><div class='add'>+	 * engine can reach accurate pixel clock of exactly 72.4 MHz.</div><div class='add'>+	 */</div><div class='add'>+	assigned-clock-rates = &lt;0&gt;, &lt;506800000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;panel_lvds0 {</div><div class='add'>+	compatible = "edt,etml1010g3dra";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm4 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10-ph128800t006.dtso b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10-ph128800t006.dtso<br/>new file mode 100644<br/>index 000000000000..559286f384be<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10-ph128800t006.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10-ph128800t006.dtso</a></div><div class='hunk'>@@ -0,0 +1,45 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2025 PHYTEC Messtechnik GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/imx8mp-clock.h&gt;</div><div class='add'>+#include "imx8mp-phyboard-pollux-peb-av-10.dtsi"</div><div class='add'>+</div><div class='add'>+&amp;backlight_lvds0 {</div><div class='add'>+	brightness-levels = &lt;0 8 16 32 64 128 255&gt;;</div><div class='add'>+	default-brightness-level = &lt;8&gt;;</div><div class='add'>+	enable-gpios = &lt;&amp;gpio5 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	num-interpolated-steps = &lt;2&gt;;</div><div class='add'>+	pwms = &lt;&amp;pwm4 0 66667 0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lvds_bridge {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_MEDIA_LDB&gt;, &lt;&amp;clk IMX8MP_VIDEO_PLL1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_VIDEO_PLL1_OUT&gt;;</div><div class='add'>+	/*</div><div class='add'>+	 * The LVDS panel uses 66.5 MHz pixel clock, set IMX8MP_VIDEO_PLL1 to</div><div class='add'>+	 * 66.5 * 7 = 465.5 MHz so the LDB serializer and LCDIFv3 scanout</div><div class='add'>+	 * engine can reach accurate pixel clock of exactly 66.5 MHz.</div><div class='add'>+	 */</div><div class='add'>+	assigned-clock-rates = &lt;0&gt;, &lt;465500000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;panel_lvds0 {</div><div class='add'>+	compatible = "powertip,ph128800t006-zhc01";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm4 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10.dtsi<br/>new file mode 100644<br/>index 000000000000..bb740f845855<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10.dtsi</a></div><div class='hunk'>@@ -0,0 +1,198 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2025 PHYTEC Messtechnik GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/imx8mp-clock.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include "imx8mp-pinfunc.h"</div><div class='add'>+</div><div class='add'>+&amp;{/} {</div><div class='add'>+	backlight_lvds0: backlight0 {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_lvds0&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		power-supply = &lt;&amp;reg_vcc_12v&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	panel_lvds0: panel-lvds0 {</div><div class='add'>+		backlight = &lt;&amp;backlight_lvds0&gt;;</div><div class='add'>+		power-supply = &lt;&amp;reg_vcc_3v3_sw&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			panel0_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;ldb_lvds_ch0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc_12v: regulator-12v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-max-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-name = "VCC_12V";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc_1v8_audio: regulator-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-name = "VCC_1V8_Audio";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc_3v3_analog: regulator-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "VCC_3V3_Analog";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,name = "snd-peb-av-10";</div><div class='add'>+		simple-audio-card,format = "i2s";</div><div class='add'>+		simple-audio-card,bitclock-master = &lt;&amp;dailink_master&gt;;</div><div class='add'>+		simple-audio-card,frame-master = &lt;&amp;dailink_master&gt;;</div><div class='add'>+		simple-audio-card,mclk-fs = &lt;32&gt;;</div><div class='add'>+		simple-audio-card,widgets =</div><div class='add'>+			"Line", "Line In",</div><div class='add'>+			"Speaker", "Speaker",</div><div class='add'>+			"Microphone", "Microphone Jack",</div><div class='add'>+			"Headphone", "Headphone Jack";</div><div class='add'>+		simple-audio-card,routing =</div><div class='add'>+			"Speaker", "SPOP",</div><div class='add'>+			"Speaker", "SPOM",</div><div class='add'>+			"Headphone Jack", "HPLOUT",</div><div class='add'>+			"Headphone Jack", "HPROUT",</div><div class='add'>+			"LINE1L", "Line In",</div><div class='add'>+			"LINE1R", "Line In",</div><div class='add'>+			"MIC3R", "Microphone Jack",</div><div class='add'>+			"Microphone Jack", "Mic Bias";</div><div class='add'>+</div><div class='add'>+		simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;sai2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dailink_master: simple-audio-card,codec {</div><div class='add'>+			sound-dai = &lt;&amp;codec&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MP_CLK_SAI2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c4&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c4_gpio&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	codec: codec@18 {</div><div class='add'>+		compatible = "ti,tlv320aic3007";</div><div class='add'>+		reg = &lt;0x18&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_tlv320&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio4 28 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		ai3x-gpio-func = &lt;0xd 0x0&gt;;</div><div class='add'>+		ai3x-micbias-vg = &lt;2&gt;;</div><div class='add'>+		AVDD-supply = &lt;&amp;reg_vcc_3v3_analog&gt;;</div><div class='add'>+		DRVDD-supply = &lt;&amp;reg_vcc_3v3_analog&gt;;</div><div class='add'>+		DVDD-supply = &lt;&amp;reg_vcc_1v8_audio&gt;;</div><div class='add'>+		IOVDD-supply = &lt;&amp;reg_vcc_3v3_sw&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@57 {</div><div class='add'>+		compatible = "atmel,24c32";</div><div class='add'>+		reg = &lt;0x57&gt;;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_vcc_3v3_sw&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ldb_lvds_ch0 {</div><div class='add'>+	remote-endpoint = &lt;&amp;panel0_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm4 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm4&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai2 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai2&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_SAI2&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;12288000&gt;;</div><div class='add'>+	clocks = &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_IPG&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX8MP_CLK_DUMMY&gt;,</div><div class='add'>+		 &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX8MP_CLK_DUMMY&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX8MP_CLK_DUMMY&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX8MP_AUDIO_PLL1_OUT&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX8MP_AUDIO_PLL2_OUT&gt;;</div><div class='add'>+	clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k",</div><div class='add'>+		      "pll11k";</div><div class='add'>+	#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	fsl,sai-mclk-direction-output;</div><div class='add'>+	fsl,sai-synchronous-rx;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_i2c4: i2c4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL		0x400001c2</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA		0x400001c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4_gpio: i2c4gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20	0x1e2</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21	0x1e2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lvds0: lvds0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01	0x12</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm4: pwm4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT	0x12</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai2: sai2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK	0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI2_RX_SYNC	0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK	0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00	0xd6</div><div class='add'>+			MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_tlv320: tlv320grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28	0x16</div><div class='add'>+			MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22	0x16</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10.dtso b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10.dtso<br/>new file mode 100644<br/>index 000000000000..95078618ee09<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10.dtso</a></div><div class='hunk'>@@ -0,0 +1,9 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2025 PHYTEC Messtechnik GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+#include "imx8mp-phyboard-pollux-peb-av-10.dtsi"</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-ph128800t006.dtso b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-ph128800t006.dtso<br/>new file mode 100644<br/>index 000000000000..a39f83bf8204<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-ph128800t006.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-ph128800t006.dtso</a></div><div class='hunk'>@@ -0,0 +1,45 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2025 PHYTEC Messtechnik GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/imx8mp-clock.h&gt;</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+&amp;backlight_lvds1 {</div><div class='add'>+	brightness-levels = &lt;0 8 16 32 64 128 255&gt;;</div><div class='add'>+	default-brightness-level = &lt;8&gt;;</div><div class='add'>+	enable-gpios = &lt;&amp;gpio2 20 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	num-interpolated-steps = &lt;2&gt;;</div><div class='add'>+	pwms = &lt;&amp;pwm3 0 66667 0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lvds_bridge {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_MEDIA_LDB&gt;, &lt;&amp;clk IMX8MP_VIDEO_PLL1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_VIDEO_PLL1_OUT&gt;;</div><div class='add'>+	/*</div><div class='add'>+	 * The LVDS panel uses 72.4 MHz pixel clock, set IMX8MP_VIDEO_PLL1 to</div><div class='add'>+	 * 66.5 * 7 = 465.5 MHz so the LDB serializer and LCDIFv3 scanout</div><div class='add'>+	 * engine can reach accurate pixel clock of exactly 66.5 MHz.</div><div class='add'>+	 */</div><div class='add'>+	assigned-clock-rates = &lt;0&gt;, &lt;465500000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+&amp;panel_lvds1 {</div><div class='add'>+	compatible = "powertip,ph128800t006-zhc01";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts<br/>new file mode 100644<br/>index 000000000000..9687b4ded8f4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts</a></div><div class='hunk'>@@ -0,0 +1,540 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2020 PHYTEC Messtechnik GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/phy/phy-imx8-pcie.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/leds-pca9532.h&gt;</div><div class='add'>+#include &lt;dt-bindings/thermal/thermal.h&gt;</div><div class='add'>+#include "imx8mp-phycore-som.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "PHYTEC phyBOARD-Pollux i.MX8MP";</div><div class='add'>+	compatible = "phytec,imx8mp-phyboard-pollux-rdk",</div><div class='add'>+		     "phytec,imx8mp-phycore-som", "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	backlight_lvds1: backlight1 {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_lvds1&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		power-supply = &lt;&amp;reg_lvds1_reg_en&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fan0: fan {</div><div class='add'>+		compatible = "gpio-fan";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_fan&gt;;</div><div class='add'>+		gpio-fan,speed-map = &lt;0     0</div><div class='add'>+				      13000 1&gt;;</div><div class='add'>+		gpios = &lt;&amp;gpio5 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		#cooling-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	panel_lvds1: panel-lvds1 {</div><div class='add'>+		/* compatible panel in overlay */</div><div class='add'>+		backlight = &lt;&amp;backlight_lvds1&gt;;</div><div class='add'>+		power-supply = &lt;&amp;reg_vcc_3v3_sw&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			panel1_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;ldb_lvds_ch1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc_5v_sw: regulator-vcc-5v-sw {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-name = "VCC_5V_SW";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_can1_stby: regulator-can1-stby {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_flexcan1_reg&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio3 20 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "can1-stby";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_can2_stby: regulator-can2-stby {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_flexcan2_reg&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio3 21 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "can2-stby";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_lvds1_reg_en: regulator-lvds1 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;gpio1 9 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+		regulator-name = "lvds1_reg_en";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb1_vbus: regulator-usb1-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usb1_vbus&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio1 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-name = "usb1_host_vbus";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usdhc2_vmmc&gt;;</div><div class='add'>+		regulator-name = "VSD_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio2 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		startup-delay-us = &lt;100&gt;;</div><div class='add'>+		off-on-delay-us = &lt;12000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc_3v3_sw: regulator-vcc-3v3-sw {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCC_3V3_SW";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	thermal-zones {</div><div class='add'>+		soc-thermal {</div><div class='add'>+			trips {</div><div class='add'>+				active1: trip2 {</div><div class='add'>+					temperature = &lt;60000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "active";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map1 {</div><div class='add'>+					trip = &lt;&amp;active1&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;fan0 1 THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* TPM */</div><div class='add'>+&amp;ecspi1 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	tpm: tpm@0 {</div><div class='add'>+		compatible = "infineon,slb9670", "tcg,tpm_tis-spi";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;38000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eqos {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_eqos&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@1 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;0x1&gt;;</div><div class='add'>+			ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_1_50_NS&gt;;</div><div class='add'>+			ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_1_50_NS&gt;;</div><div class='add'>+			ti,fifo-depth = &lt;DP83867_PHYCR_FIFO_DEPTH_4_B_NIB&gt;;</div><div class='add'>+			ti,clk-output-sel = &lt;DP83867_CLK_O_SEL_OFF&gt;;</div><div class='add'>+			enet-phy-lane-no-swap;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* CAN FD */</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan1&gt;;</div><div class='add'>+	xceiver-supply = &lt;&amp;reg_can1_stby&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan2&gt;;</div><div class='add'>+	xceiver-supply = &lt;&amp;reg_can2_stby&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c2_gpio&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	eeprom@51 {</div><div class='add'>+		compatible = "atmel,24c02";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_vcc_3v3_sw&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds@62 {</div><div class='add'>+		compatible = "nxp,pca9533";</div><div class='add'>+		reg = &lt;0x62&gt;;</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			type = &lt;PCA9532_TYPE_LED&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-2 {</div><div class='add'>+			type = &lt;PCA9532_TYPE_LED&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-3 {</div><div class='add'>+			type = &lt;PCA9532_TYPE_LED&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ldb_lvds_ch1 {</div><div class='add'>+	remote-endpoint = &lt;&amp;panel1_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;snvs_pwrkey {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	clocks = &lt;&amp;hsio_blk_ctrl&gt;;</div><div class='add'>+	clock-names = "ref";</div><div class='add'>+	fsl,refclk-pad-mode = &lt;IMX8_PCIE_REFCLK_PAD_OUTPUT&gt;;</div><div class='add'>+	fsl,clkreq-unsupported;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Mini PCIe */</div><div class='add'>+&amp;pcie {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie0&gt;;</div><div class='add'>+	reset-gpio = &lt;&amp;gpio1 8 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vpcie-supply = &lt;&amp;reg_vcc_3v3_sw&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm3 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm3&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;rv3028 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_rtc&gt;;</div><div class='add'>+	interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+	interrupts = &lt;19 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	aux-voltage-chargeable = &lt;1&gt;;</div><div class='add'>+	wakeup-source;</div><div class='add'>+	trickle-resistor-ohms = &lt;3000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* debug console */</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB1 Host mode Type-A */</div><div class='add'>+&amp;usb3_phy0 {</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usb1_vbus&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_0 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB2 4-port USB3.0 HUB */</div><div class='add'>+&amp;usb3_phy1 {</div><div class='add'>+	vbus-supply = &lt;&amp;reg_vcc_5v_sw&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_1 {</div><div class='add'>+	fsl,permanently-attached;</div><div class='add'>+	fsl,disable-port-power-control;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_1 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* RS232/RS485 */</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_UART2&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL1_80M&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SD-Card */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_USDHC2&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;200000000&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_pins&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_pins&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;ldo5&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	gpio-line-names = "", "", "X_PMIC_WDOG_B", "",</div><div class='add'>+		"PMIC_SD_VSEL", "", "", "", "PCIe_nPERST", "LVDS1REG_EN",</div><div class='add'>+		"PCIe_nWAKE", "PCIe_nCLKREQ", "USB1_OTG_PWR", "",</div><div class='add'>+		"PCIe_nW_DISABLE";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio2 {</div><div class='add'>+	gpio-line-names = "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "",</div><div class='add'>+		"", "", "X_SD2_CD_B", "", "", "",</div><div class='add'>+		"", "", "", "SD2_RESET_B", "LVDS1_BL_EN";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio3 {</div><div class='add'>+	gpio-line-names = "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "nCAN1_EN", "nCAN2_EN";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	gpio-line-names = "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "",</div><div class='add'>+		"", "", "X_PMIC_IRQ_B", "nRTC_INT", "nENET0_INT_PWDN";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio5 {</div><div class='add'>+	gpio-line-names = "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "X_ECSPI1_SSO";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_ecspi1: ecspi1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO   0x80</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI   0x80</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK   0x80</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09     0x00</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_eqos: eqosgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC			0x2</div><div class='add'>+			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO			0x2</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0		0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1		0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2		0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3		0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0		0x12</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1		0x12</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2		0x12</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3		0x12</div><div class='add'>+			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x12</div><div class='add'>+			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x12</div><div class='add'>+			MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20			0x10</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fan: fan0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04       0x16</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan1: flexcan1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX		0x154</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX		0x154</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan2: flexcan2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX		0x154</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX		0x154</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan1_reg: flexcan1reggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20	0x154</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan2_reg: flexcan2reggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21	0x154</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001c2</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA		0x400001c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2_gpio: i2c2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16	0x1e2</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17	0x1e2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lvds1: lvds1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_WP__GPIO2_IO20		0x12</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie0: pcie0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08     0x40</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10     0x60</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11	0x60 /* open drain, pull up */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14     0x40</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm3: pwm3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT		0x12</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x40</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_rtc: rtcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19	0x1C0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX	0x140</div><div class='add'>+			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usb1_vbus: usb1vbusgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12     0x10</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x140</div><div class='add'>+			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x140</div><div class='add'>+			MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS	0x140</div><div class='add'>+			MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_pins: usdhc2-gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12	0x40</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x190</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x194</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x196</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-fpsc.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-fpsc.dtsi<br/>new file mode 100644<br/>index 000000000000..8b0e8cf86cad<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-phycore-fpsc.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-phycore-fpsc.dtsi</a></div><div class='hunk'>@@ -0,0 +1,796 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2025 PHYTEC Messtechnik GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/net/ti-dp83867.h&gt;</div><div class='add'>+#include "imx8mp.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "phytec,imx8mp-phycore-fpsc", "fsl,imx8mp";</div><div class='add'>+	model = "PHYTEC phyCORE-i.MX8MP FPSC";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		rtc0 = &amp;rv3028;</div><div class='add'>+		rtc1 = &amp;snvs_rtc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x40000000 0x0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2 {</div><div class='add'>+		 compatible = "regulator-fixed";</div><div class='add'>+		 off-on-delay-us = &lt;12000&gt;;</div><div class='add'>+		 pinctrl-0 = &lt;&amp;pinctrl_reg_usdhc2_vmmc&gt;;</div><div class='add'>+		 pinctrl-names = "default";</div><div class='add'>+		 regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		 regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		 regulator-name = "VDDSW_SD2";</div><div class='add'>+		 startup-delay-us = &lt;100&gt;;</div><div class='add'>+		 gpio = &lt;&amp;gpio2 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		 enable-active-high;</div><div class='add'>+	 };</div><div class='add'>+</div><div class='add'>+	reg_vdd_io: regulator-vdd-io {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-name = "VDD_IO";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi1 { /* FPSC SPI1 */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi1&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi2 { /* FPSC SPI2 */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi2&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi3 { /* FPSC SPI3 */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi3&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eqos { /* FPSC RGMII2 */</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_eqos&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec { /* FPSC GB_ETH1 */</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	fsl,magic-packet;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@0 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+			interrupts = &lt;19 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			enet-phy-lane-no-swap;</div><div class='add'>+			ti,clk-output-sel = &lt;DP83867_CLK_O_SEL_OFF&gt;;</div><div class='add'>+			ti,fifo-depth = &lt;DP83867_PHYCR_FIFO_DEPTH_4_B_NIB&gt;;</div><div class='add'>+			ti,min-output-impedance;</div><div class='add'>+			ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_1_50_NS&gt;;</div><div class='add'>+			ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_1_50_NS&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan1 { /* FPSC CAN1 */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan1&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan2 { /* FPSC CAN2 */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan2&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexspi { /* FPSC QSPI */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexspi&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	gpio-line-names = "", "", "", "", "",</div><div class='add'>+			  "", "", "", "PCIE1_nPERST";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio2 {</div><div class='add'>+	gpio-line-names = "", "", "", "", "",</div><div class='add'>+			  "", "", "", "", "",</div><div class='add'>+			  "", "", "", "", "",</div><div class='add'>+			  "", "", "", "", "SD2_RESET_B";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio3 {</div><div class='add'>+	gpio-line-names = "", "", "", "", "",</div><div class='add'>+			  "", "", "", "", "",</div><div class='add'>+			  "", "", "", "", "",</div><div class='add'>+			  "", "", "", "", "I2C6_SCL",</div><div class='add'>+			  "I2C6_SDA", "I2C5_SCL";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 { /* FPSC GPIO */</div><div class='add'>+	gpio-line-names = "GPIO6", "RGMII2_nINT", "GPIO7", "GPIO4", "",</div><div class='add'>+			  "", "", "", "", "",</div><div class='add'>+			  "", "", "", "", "",</div><div class='add'>+			  "", "", "", "X_PMIC_IRQ_B", "",</div><div class='add'>+			  "", "GPIO5", "", "", "RGMII2_EVENT_OUT",</div><div class='add'>+			  "", "", "RGMII2_EVENT_IN";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio4&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio5 { /* FPSC GPIO */</div><div class='add'>+	gpio-line-names = "", "", "", "", "I2C5_SDA",</div><div class='add'>+			  "GPIO1", "", "", "", "SPI1_CS",</div><div class='add'>+			  "", "", "", "SPI2_CS", "I2C1_SCL",</div><div class='add'>+			  "I2C1_SDA", "I2C2_SCL", "I2C2_SDA", "I2C3_SCL", "I2C3_SDA",</div><div class='add'>+			  "", "GPIO2", "", "", "SPI3_CS",</div><div class='add'>+			  "", "GPIO3";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio5&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 { /* FPSC I2C1 */</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c1_gpio&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pmic: pmic@25 {</div><div class='add'>+		compatible = "nxp,pca9450c";</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;18 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			buck1: BUCK1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;950000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-name = "VDD_SOC (BUCK1)";</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck2: BUCK2 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-name = "VDD_ARM (BUCK2)";</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+				nxp,dvs-run-voltage = &lt;950000&gt;;</div><div class='add'>+				nxp,dvs-standby-voltage = &lt;850000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck4: BUCK4 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "VDD_3V3 (BUCK4)";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck5: BUCK5 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "VDD_1V8 (BUCK5)";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck6: BUCK6 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1155000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1045000&gt;;</div><div class='add'>+				regulator-name = "NVCC_DRAM_1V1 (BUCK6)";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo1: LDO1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "NVCC_SNVS_1V8 (LDO1)";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo3: LDO3 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "VDDA_1V8 (LDO3)";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo5: LDO5 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "NVCC_SD2 (LDO5)";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* User EEPROM */</div><div class='add'>+	eeprom@50 {</div><div class='add'>+		compatible = "atmel,24c32";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_vdd_io&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* factory EEPROM */</div><div class='add'>+	eeprom@51 {</div><div class='add'>+		compatible = "atmel,24c32";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		read-only;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_vdd_io&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rv3028: rtc@52 {</div><div class='add'>+		compatible = "microcrystal,rv3028";</div><div class='add'>+		reg = &lt;0x52&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 { /* FPSC I2C2 */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c2_gpio&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 { /* FPSC I2C3 */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c3_gpio&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c5 { /* FPSC I2C4 */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c5&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c5_gpio&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	scl-gpios = &lt;&amp;gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c6 { /* FPSC I2C5 */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c6&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c6_gpio&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	scl-gpios = &lt;&amp;gpio3 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio3 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_flexcan1: can1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI2_RXC__CAN1_TX		0x154	/* CAN1_TX */</div><div class='add'>+			MX8MP_IOMUXC_SAI2_TXC__CAN1_RX		0x154	/* CAN1_RX */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan2: can2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX		0x154	/* CAN2_TX */</div><div class='add'>+			MX8MP_IOMUXC_UART3_TXD__CAN2_RX		0x154	/* CAN2_RX */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_eqos: eqosgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01				0x10	/* RGMII2_nINT */</div><div class='add'>+			MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27				0x10	/* RGMII2_EVENT_IN */</div><div class='add'>+			MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24				0x10	/* RGMII2_EVENT_OUT */</div><div class='add'>+			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x2	/* RGMII2_MDIO */</div><div class='add'>+			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x2	/* RGMII2_MDC */</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x12	/* RGMII2_TX_D3 */</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x12	/* RGMII2_TX_D2 */</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x12	/* RGMII2_TX_D1 */</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x12	/* RGMII2_TX_D0 */</div><div class='add'>+			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL			0x12	/* RGMII2_TX_CTL */</div><div class='add'>+			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x12	/* RGMII2_TXC */</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x90	/* RGMII2_RX_D3 */</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x90	/* RGMII2_RX_D2 */</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x90	/* RGMII2_RX_D1 */</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x90	/* RGMII2_RX_D0 */</div><div class='add'>+			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL			0x90	/* RGMII2_RX_CTL */</div><div class='add'>+			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x90	/* RGMII2_RXC */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec: fecgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x2</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x2</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x90</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x90</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x90</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x90</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19		0x140</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x90</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x12</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x12</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x14</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x14</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x14</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x14</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x90</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexspi: flexspigrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B	0x82	/* QSPI_CE */</div><div class='add'>+			MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK		0x1c2	/* QSPI_CLK */</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00	0x82	/* QSPI_DATA_0 */</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01	0x82	/* QSPI_DATA_1 */</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02	0x82	/* QSPI_DATA_2 */</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03	0x82	/* QSPI_DATA_3 */</div><div class='add'>+			MX8MP_IOMUXC_NAND_DQS__FLEXSPI_A_DQS		0x82	/* QSPI_DQS */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio4: gpio4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03	0x40	/* GPIO4 */</div><div class='add'>+			MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21	0x106	/* GPIO5 */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00	0x106	/* GPIO6 */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02	0x106	/* GPIO7 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio5: gpio5grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05	0x106	/* GPIO1 */</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21	0x106	/* GPIO2 */</div><div class='add'>+			MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26	0x106	/* GPIO3 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_hdmi: hdmigrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC		0x106	/* HDMI_CEC */</div><div class='add'>+			MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL	0x106	/* HDMI_SCL */</div><div class='add'>+			MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA	0x106	/* HDMI_SDA */</div><div class='add'>+			MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD		0x106	/* HDMI_HPD */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1_gpio: i2c1gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15	0x1e2</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14	0x1e2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001c2	/* I2C1_SDA_DNU */</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c2	/* I2C1_SCL_DNU */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2_gpio: i2c2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17	0x1e2</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16	0x1e2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA		0x400001c2	/* I2C2_SDA */</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001c2	/* I2C2_SCL */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3_gpio: i2c3gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19	0x1e2</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18	0x1e2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001c2	/* I2C3_SDA */</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400001c2	/* I2C3_SCL */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c5_gpio: i2c5gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04	0x1e2</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21	0x1e2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c5: i2c5grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA		0x400001c2	/* I2C4_SDA */</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL	0x400001c2	/* I2C4_SCL */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c6_gpio: i2c6gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20	0x1e2</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19	0x1e2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c6: i2c6grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA		0x400001c2	/* I2C5_SDA */</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL	0x400001c2	/* I2C5_SCL */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie0: pcie0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B	0x10	/* PCIE1_nCLKREQ */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08     0x40	/* PCIE1_nPERST */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: pmicirqgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm1: pwm1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT	0x106	/* PWM1 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm2: pwm2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO09__PWM2_OUT	0x106	/* PWM2 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm3: pwm3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT		0x106	/* PWM3 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm4: pwm4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT	0x106	/* PWM4 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19    0x40</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai5: sai5grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI5_MCLK	0x106	/* SAI1_MCLK */</div><div class='add'>+			MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI5_RX_SYNC	0x106	/* SAI1_RX_SYNC */</div><div class='add'>+			MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI5_RX_BCLK	0x106	/* SAI1_RX_BCLK */</div><div class='add'>+			MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI5_RX_DATA00	0x106	/* SAI1_RX_DATA */</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC	0x106	/* SAI1_TX_SYNC */</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK	0x106	/* SAI1_TX_BCLK */</div><div class='add'>+			MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI5_TX_DATA00	0x106	/* SAI1_TX_DATA */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi1: spi1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK	0x82	/* SPI1_SCLK */</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI	0x82	/* SPI1_MOSI */</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO	0x82	/* SPI1_MISO */</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09	0x106	/* SPI1_CS */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi2: spi2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK	0x82	/* SPI2_SCLK */</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI	0x82	/* SPI2_MOSI */</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO	0x82	/* SPI2_MISO */</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13	0x106     /* SPI2_CS */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi3: spi3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK	0x82	/* SPI3_SCLK */</div><div class='add'>+			MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI	0x82	/* SPI3_MOSI */</div><div class='add'>+			MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO	0x82	/* SPI3_MISO */</div><div class='add'>+			MX8MP_IOMUXC_UART2_RXD__GPIO5_IO24	0x106     /* SPI3_CS */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI3_TXC__UART2_DTE_RX	0x140	/* UART2_RXD */</div><div class='add'>+			MX8MP_IOMUXC_SAI3_TXFS__UART2_DTE_TX	0x140	/* UART2_TXD */</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA5__UART2_DTE_RTS	0x140	/* UART2_RTS */</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA4__UART2_DTE_CTS	0x140	/* UART2_CTS */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: uart3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA6__UART3_DTE_RX	0x140	/* UART1_RXD */</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA7__UART3_DTE_TX	0x140	/* UART1_TXD */</div><div class='add'>+			MX8MP_IOMUXC_SD1_STROBE__UART3_DTE_RTS	0x140	/* UART1_RTS */</div><div class='add'>+			MX8MP_IOMUXC_SD1_RESET_B__UART3_DTE_CTS	0x140	/* UART1_CTS */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart4: uart4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX	0x140	/* UART3_RXD */</div><div class='add'>+			MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX	0x140	/* UART3_TXD */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usb0: usb0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR	0x106	/* USB1_PWR_EN */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC	0x106	/* USB1_OC */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID	0x106	/* USB1_ID */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usb1: usb1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR	0x106	/* USB2_PWR_EN */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC	0x106	/* USB2_OC */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO11__USB2_OTG_ID	0x106	/* USB2_ID */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO07__USDHC1_WP	0x106	/* SDIO_WP */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO06__USDHC1_CD_B	0x106	/* SDIO_CD */</div><div class='add'>+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x106	/* SDIO_CLK */</div><div class='add'>+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x106	/* SDIO_CLK */</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x106	/* SDIO_DATA0 */</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x106	/* SDIO_DATA1 */</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x106	/* SDIO_DATA2 */</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x106	/* SDIO_DATA3 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B	0x40	/* SDCARD_CD */</div><div class='add'>+			MX8MP_IOMUXC_SD2_WP__USDHC2_WP		0x40	/* SDCARD_WP */</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x190	/* SDCARD_CLK */</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d0	/* SDCARD_CMD */</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d0	/* SDCARD_DATA0 */</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d0	/* SDCARD_DATA1 */</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d0	/* SDCARD_DATA2 */</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d0	/* SDCARD_DATA3 */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B	0x40	/* SDCARD_CD */</div><div class='add'>+			MX8MP_IOMUXC_SD2_WP__USDHC2_WP		0x40	/* SDCARD_WP */</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x194	/* SDCARD_CLK */</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d4	/* SDCARD_CMD */</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d4	/* SDCARD_DATA0 */</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d4	/* SDCARD_DATA1 */</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d4	/* SDCARD_DATA2 */</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d4	/* SDCARD_DATA3 */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B	0x40	/* SDCARD_CD */</div><div class='add'>+			MX8MP_IOMUXC_SD2_WP__USDHC2_WP		0x40	/* SDCARD_WP */</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x196	/* SDCARD_CLK */</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d6	/* SDCARD_CMD */</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d6	/* SDCARD_DATA0 */</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d6	/* SDCARD_DATA1 */</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d6	/* SDCARD_DATA2 */</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d6	/* SDCARD_DATA3 */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x190</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x190</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x194</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x194</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x196</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d2</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d2</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d2</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d2</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d2</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d2</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d2</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d2</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x196</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B	0xe6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie { /* FPSC PCIE1 */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm1 { /* FPSC PWM1 */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm1&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm2 { /* FPSC PWM2 */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm2&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm3 { /* FPSC PWM3 */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm3&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm4 { /* FPSC PWM4 */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm4&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai5 { /* FPSC SAI1 */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai5&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 { /* FPSC UART2 */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	fsl,dte-mode;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart3 { /* FPSC UART1 */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	fsl,dte-mode;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart4 { /* FPSC UART3 */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart4&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_0 { /* FPSC USB1 */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usb0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_1 { /* FPSC USB2 */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usb1&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc1 { /* FPSC SDIO */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 { /* FPSC SDCARD */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	sd-uhs-sdr104;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;ldo5&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* eMMC */</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_USDHC3_ROOT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-no-eth.dtso b/arch/arm64/boot/dts/freescale/imx8mp-phycore-no-eth.dtso<br/>new file mode 100644<br/>index 000000000000..5f0278bf61ee<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-phycore-no-eth.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-phycore-no-eth.dtso</a></div><div class='hunk'>@@ -0,0 +1,16 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2024 PHYTEC Messtechnik GmbH</div><div class='add'>+ * Author: Cem Tenruh &lt;c.tenruh@phytec.de&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+&amp;ethphy1 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi<br/>new file mode 100644<br/>index 000000000000..88831c0fbb7b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi</a></div><div class='hunk'>@@ -0,0 +1,325 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2020 PHYTEC Messtechnik GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/net/ti-dp83867.h&gt;</div><div class='add'>+#include "imx8mp.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "PHYTEC phyCORE-i.MX8MP";</div><div class='add'>+	compatible = "phytec,imx8mp-phycore-som", "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		rtc0 = &amp;rv3028;</div><div class='add'>+		rtc1 = &amp;snvs_rtc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x40000000 0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vdd_io: regulator-vdd-io {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "VDD_IO";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* ethernet 1 */</div><div class='add'>+&amp;fec {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec&gt;;</div><div class='add'>+	phy-handle = &lt;&amp;ethphy1&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	fsl,magic-packet;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy1: ethernet-phy@0 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			enet-phy-lane-no-swap;</div><div class='add'>+			ti,clk-output-sel = &lt;DP83867_CLK_O_SEL_OFF&gt;;</div><div class='add'>+			ti,fifo-depth = &lt;DP83867_PHYCR_FIFO_DEPTH_4_B_NIB&gt;;</div><div class='add'>+			ti,min-output-impedance;</div><div class='add'>+			ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_2_00_NS&gt;;</div><div class='add'>+			ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_2_00_NS&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexspi {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexspi0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	som_flash: flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;80000000&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c1_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pmic: pmic@25 {</div><div class='add'>+		compatible = "nxp,pca9450c";</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+		interrupts = &lt;18 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			buck1: BUCK1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;805000&gt;;</div><div class='add'>+				regulator-name = "VDD_SOC (BUCK1)";</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck2: BUCK2 {</div><div class='add'>+				nxp,dvs-run-voltage = &lt;950000&gt;;</div><div class='add'>+				nxp,dvs-standby-voltage = &lt;850000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1050000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;805000&gt;;</div><div class='add'>+				regulator-name = "VDD_ARM (BUCK2)";</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck4: BUCK4 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "VDD_3V3 (BUCK4)";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck5: BUCK5 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "VDD_1V8 (BUCK5)";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck6: BUCK6 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1155000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1045000&gt;;</div><div class='add'>+				regulator-name = "NVCC_DRAM_1V1 (BUCK6)";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo1: LDO1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1950000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1710000&gt;;</div><div class='add'>+				regulator-name = "NVCC_SNVS_1V8 (LDO1)";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo3: LDO3 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "VDDA_1V8 (LDO3)";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo5: LDO5 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "NVCC_SD2 (LDO5)";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@51 {</div><div class='add'>+		compatible = "atmel,24c32";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_vdd_io&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rv3028: rtc@52 {</div><div class='add'>+		compatible = "microcrystal,rv3028";</div><div class='add'>+		reg = &lt;0x52&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* eMMC */</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_USDHC3_ROOT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	gpio-line-names = "", "", "X_PMIC_WDOG_B";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	gpio-line-names = "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "",</div><div class='add'>+		"", "", "X_PMIC_IRQ_B";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_fec: fecgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x2</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x2</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x90</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x90</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x90</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x90</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x90</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x12</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x12</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x14</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x14</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x14</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x14</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x90</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexspi0: flexspi0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK		0x1c2</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B	0x82</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00	0x82</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01	0x82</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02	0x82</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03	0x82</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001c2</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1_gpio: i2c1gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14	0x1e2</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15	0x1e2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: pmicirqgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x190</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x190</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x194</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x194</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x196</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d2</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d2</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d2</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d2</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d2</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d2</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d2</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d2</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x196</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B	0xe6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h b/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h<br/>index da78f89b6c98..16f5899de415 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h</a></div><div class='hunk'>@@ -6,389 +6,356 @@</div><div class='ctx'> #ifndef __DTS_IMX8MP_PINFUNC_H</div><div class='ctx'> #define __DTS_IMX8MP_PINFUNC_H</div><div class='ctx'> </div><div class='add'>+/* Drive Strength */</div><div class='add'>+#define MX8MP_DSE_X1		0x0</div><div class='add'>+#define MX8MP_DSE_X2		0x4</div><div class='add'>+#define MX8MP_DSE_X4		0x2</div><div class='add'>+#define MX8MP_DSE_X6		0x6</div><div class='add'>+</div><div class='add'>+/* Slew Rate */</div><div class='add'>+#define MX8MP_FSEL_FAST		0x10</div><div class='add'>+#define MX8MP_FSEL_SLOW		0x0</div><div class='add'>+</div><div class='add'>+/* Open Drain */</div><div class='add'>+#define MX8MP_ODE_ENABLE	0x20</div><div class='add'>+#define MX8MP_ODE_DISABLE	0x0</div><div class='add'>+</div><div class='add'>+#define MX8MP_PULL_DOWN		0x0</div><div class='add'>+#define MX8MP_PULL_UP		0x40</div><div class='add'>+</div><div class='add'>+/* Hysteresis */</div><div class='add'>+#define MX8MP_HYS_CMOS		0x0</div><div class='add'>+#define MX8MP_HYS_SCHMITT	0x80</div><div class='add'>+</div><div class='add'>+#define MX8MP_PULL_ENABLE	0x100</div><div class='add'>+#define MX8MP_PULL_DISABLE	0x0</div><div class='add'>+</div><div class='add'>+/* SION force input mode */</div><div class='add'>+#define MX8MP_SION		0x40000000</div><div class='add'>+</div><div class='add'>+/* long defaults */</div><div class='add'>+#define MX8MP_USDHC_DATA_DEFAULT (MX8MP_FSEL_FAST | MX8MP_PULL_UP | \</div><div class='add'>+				  MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)</div><div class='add'>+#define MX8MP_I2C_DEFAULT (MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | \</div><div class='add'>+			   MX8MP_PULL_ENABLE | MX8MP_SION)</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  * The pin function ID is a tuple of</div><div class='ctx'>  * &lt;mux_reg conf_reg input_reg mux_mode input_val&gt;</div><div class='ctx'>  */</div><div class='ctx'> #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00                          0x014 0x274 0x000 0x0 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO00__CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT  0x014 0x274 0x000 0x1 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO00__MEDIAMIX_ISP_FL_TRIG_0              0x014 0x274 0x5D4 0x3 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO00__ANAMIX_REF_CLK_32K                  0x014 0x274 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO00__CCMSRCGPCMIX_EXT_CLK1               0x014 0x274 0x000 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO00__SJC_FAIL                            0x014 0x274 0x000 0x7 0x0</div><div class='add'>+#define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT           0x014 0x274 0x000 0x1 0x0</div><div class='add'>+#define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0                       0x014 0x274 0x5D4 0x3 0x0</div><div class='add'>+#define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1                        0x014 0x274 0x000 0x6 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01                          0x018 0x278 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT                            0x018 0x278 0x000 0x1 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO01__MEDIAMIX_ISP_SHUTTER_TRIG_0         0x018 0x278 0x5DC 0x3 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO01__ANAMIX_REF_CLK_24M                  0x018 0x278 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO01__CCMSRCGPCMIX_EXT_CLK2               0x018 0x278 0x000 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO01__SJC_ACTIVE                          0x018 0x278 0x000 0x7 0x0</div><div class='add'>+#define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0                  0x018 0x278 0x5DC 0x3 0x0</div><div class='add'>+#define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2                        0x018 0x278 0x000 0x6 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02                          0x01C 0x27C 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B                        0x01C 0x27C 0x000 0x1 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO02__MEDIAMIX_ISP_FLASH_TRIG_0           0x01C 0x27C 0x000 0x3 0x0</div><div class='add'>+#define MX8MP_IOMUXC_GPIO1_IO02__ISP_FLASH_TRIG_0                    0x01C 0x27C 0x000 0x3 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_ANY                      0x01C 0x27C 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_GPIO1_IO02__SJC_DE_B                            0x01C 0x27C 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03                          0x020 0x280 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_GPIO1_IO03__USDHC1_VSELECT                      0x020 0x280 0x000 0x1 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO03__MEDIAMIX_ISP_PRELIGHT_TRIG_0        0x020 0x280 0x000 0x3 0x0</div><div class='add'>+#define MX8MP_IOMUXC_GPIO1_IO03__ISP_PRELIGHT_TRIG_0                 0x020 0x280 0x000 0x3 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_GPIO1_IO03__SDMA1_EXT_EVENT00                   0x020 0x280 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO03__ANAMIX_XTAL_OK                      0x020 0x280 0x000 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO03__SJC_DONE                            0x020 0x280 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04                          0x024 0x284 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT                      0x024 0x284 0x000 0x1 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO04__MEDIAMIX_ISP_SHUTTER_OPEN_0         0x024 0x284 0x000 0x3 0x0</div><div class='add'>+#define MX8MP_IOMUXC_GPIO1_IO04__ISP_SHUTTER_OPEN_0                  0x024 0x284 0x000 0x3 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_GPIO1_IO04__SDMA1_EXT_EVENT01                   0x024 0x284 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO04__ANAMIX_XTAL_OK_LV                   0x024 0x284 0x000 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO04__USDHC1_TEST_TRIG                    0x024 0x284 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05                          0x028 0x288 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_GPIO1_IO05__M7_NMI                              0x028 0x288 0x000 0x1 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO05__MEDIAMIX_ISP_FL_TRIG_1              0x028 0x288 0x5D8 0x3 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO05__CCMSRCGPCMIX_PMIC_READY             0x028 0x288 0x554 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO05__CCMSRCGPCMIX_INT_BOOT               0x028 0x288 0x000 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO05__USDHC2_TEST_TRIG                    0x028 0x288 0x000 0x7 0x0</div><div class='add'>+#define MX8MP_IOMUXC_GPIO1_IO05__ISP_FL_TRIG_1                       0x028 0x288 0x5D8 0x3 0x0</div><div class='add'>+#define MX8MP_IOMUXC_GPIO1_IO05__CCM_PMIC_READY                      0x028 0x288 0x554 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06                          0x02C 0x28C 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_GPIO1_IO06__ENET_QOS_MDC                        0x02C 0x28C 0x000 0x1 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO06__MEDIAMIX_ISP_SHUTTER_TRIG_1         0x02C 0x28C 0x5E0 0x3 0x0</div><div class='add'>+#define MX8MP_IOMUXC_GPIO1_IO06__ISP_SHUTTER_TRIG_1                  0x02C 0x28C 0x5E0 0x3 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_GPIO1_IO06__USDHC1_CD_B                         0x02C 0x28C 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO06__CCMSRCGPCMIX_EXT_CLK3               0x02C 0x28C 0x000 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO06__ECSPI1_TEST_TRIG                    0x02C 0x28C 0x000 0x7 0x0</div><div class='add'>+#define MX8MP_IOMUXC_GPIO1_IO06__CCM_EXT_CLK3                        0x02C 0x28C 0x000 0x6 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07                          0x030 0x290 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_GPIO1_IO07__ENET_QOS_MDIO                       0x030 0x290 0x590 0x1 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO07__MEDIAMIX_ISP_FLASH_TRIG_1           0x030 0x290 0x000 0x3 0x0</div><div class='add'>+#define MX8MP_IOMUXC_GPIO1_IO07__ISP_FLASH_TRIG_1                    0x030 0x290 0x000 0x3 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_GPIO1_IO07__USDHC1_WP                           0x030 0x290 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO07__CCMSRCGPCMIX_EXT_CLK4               0x030 0x290 0x000 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO07__ECSPI2_TEST_TRIG                    0x030 0x290 0x000 0x7 0x0</div><div class='add'>+#define MX8MP_IOMUXC_GPIO1_IO07__CCM_EXT_CLK4                        0x030 0x290 0x000 0x6 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08                          0x034 0x294 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_GPIO1_IO08__ENET_QOS_1588_EVENT0_IN             0x034 0x294 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_GPIO1_IO08__PWM1_OUT                            0x034 0x294 0x000 0x2 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO08__MEDIAMIX_ISP_PRELIGHT_TRIG_1        0x034 0x294 0x000 0x3 0x0</div><div class='add'>+#define MX8MP_IOMUXC_GPIO1_IO08__ISP_PRELIGHT_TRIG_1                 0x034 0x294 0x000 0x3 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_GPIO1_IO08__ENET_QOS_1588_EVENT0_AUX_IN         0x034 0x294 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_GPIO1_IO08__USDHC2_RESET_B                      0x034 0x294 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO08__CCMSRCGPCMIX_WAIT                   0x034 0x294 0x000 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO08__FLEXSPI_TEST_TRIG                   0x034 0x294 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09                          0x038 0x298 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_GPIO1_IO09__ENET_QOS_1588_EVENT0_OUT            0x038 0x298 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_GPIO1_IO09__PWM2_OUT                            0x038 0x298 0x000 0x2 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO09__MEDIAMIX_ISP_SHUTTER_OPEN_1         0x038 0x298 0x000 0x3 0x0</div><div class='add'>+#define MX8MP_IOMUXC_GPIO1_IO09__ISP_SHUTTER_OPEN_1                  0x038 0x298 0x000 0x3 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B                      0x038 0x298 0x000 0x4 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO09__AUDIOMIX_EXT_EVENT00                0x038 0x298 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO09__CCMSRCGPCMIX_STOP                   0x038 0x298 0x000 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO09__RAWNAND_TEST_TRIG                   0x038 0x298 0x000 0x7 0x0</div><div class='add'>+#define MX8MP_IOMUXC_GPIO1_IO09__SDMA2_EXT_EVENT00                   0x038 0x298 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10                          0x03C 0x29C 0x000 0x0 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO10__HSIOMIX_usb1_OTG_ID                 0x03C 0x29C 0x000 0x1 0x0</div><div class='add'>+#define MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID                         0x03C 0x29C 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_GPIO1_IO10__PWM3_OUT                            0x03C 0x29C 0x000 0x2 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO10__OCOTP_FUSE_LATCHED                  0x03C 0x29C 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11                          0x040 0x2A0 0x000 0x0 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO11__HSIOMIX_usb2_OTG_ID                 0x040 0x2A0 0x000 0x1 0x0</div><div class='add'>+#define MX8MP_IOMUXC_GPIO1_IO11__USB2_OTG_ID                         0x040 0x2A0 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT                            0x040 0x2A0 0x000 0x2 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_GPIO1_IO11__USDHC3_VSELECT                      0x040 0x2A0 0x000 0x4 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO11__CCMSRCGPCMIX_PMIC_READY             0x040 0x2A0 0x554 0x5 0x1</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO11__CCMSRCGPCMIX_OUT0                   0x040 0x2A0 0x000 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO11__CAAM_RNG_OSC_OBS                    0x040 0x2A0 0x000 0x7 0x0</div><div class='add'>+#define MX8MP_IOMUXC_GPIO1_IO11__CCM_PMIC_READY                      0x040 0x2A0 0x554 0x5 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12                          0x044 0x2A4 0x000 0x0 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO12__HSIOMIX_usb1_OTG_PWR                0x044 0x2A4 0x000 0x1 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO12__AUDIOMIX_EXT_EVENT01                0x044 0x2A4 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO12__CCMSRCGPCMIX_OUT1                   0x044 0x2A4 0x000 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO12__CSU_CSU_ALARM_AUT00                 0x044 0x2A4 0x000 0x7 0x0</div><div class='add'>+#define MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR                        0x044 0x2A4 0x000 0x1 0x0</div><div class='add'>+#define MX8MP_IOMUXC_GPIO1_IO12__SDMA2_EXT_EVENT01                   0x044 0x2A4 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13                          0x048 0x2A8 0x000 0x0 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO13__HSIOMIX_usb1_OTG_OC                 0x048 0x2A8 0x000 0x1 0x0</div><div class='add'>+#define MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC                         0x048 0x2A8 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_GPIO1_IO13__PWM2_OUT                            0x048 0x2A8 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO13__CCMSRCGPCMIX_OUT2                   0x048 0x2A8 0x000 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO13__CSU_CSU_ALARM_AUT01                 0x048 0x2A8 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14                          0x04C 0x2AC 0x000 0x0 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO14__HSIOMIX_usb2_OTG_PWR                0x04C 0x2AC 0x000 0x1 0x0</div><div class='add'>+#define MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR                        0x04C 0x2AC 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_GPIO1_IO14__USDHC3_CD_B                         0x04C 0x2AC 0x608 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_GPIO1_IO14__PWM3_OUT                            0x04C 0x2AC 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO14__CCMSRCGPCMIX_CLKO1                  0x04C 0x2AC 0x000 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO14__CSU_CSU_ALARM_AUT02                 0x04C 0x2AC 0x000 0x7 0x0</div><div class='add'>+#define MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1                           0x04C 0x2AC 0x000 0x6 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15                          0x050 0x2B0 0x000 0x0 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO15__HSIOMIX_usb2_OTG_OC                 0x050 0x2B0 0x000 0x1 0x0</div><div class='add'>+#define MX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC                         0x050 0x2B0 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_GPIO1_IO15__USDHC3_WP                           0x050 0x2B0 0x634 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_GPIO1_IO15__PWM4_OUT                            0x050 0x2B0 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO15__CCMSRCGPCMIX_CLKO2                  0x050 0x2B0 0x000 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_GPIO1_IO15__CSU_CSU_INT_DEB                     0x050 0x2B0 0x000 0x7 0x0</div><div class='add'>+#define MX8MP_IOMUXC_GPIO1_IO15__CCM_CLKO2                           0x050 0x2B0 0x000 0x6 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC                          0x054 0x2B4 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_MDC__AUDIOMIX_SAI6_TX_DATA00               0x054 0x2B4 0x000 0x2 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_MDC__GPIO1_IO16                            0x054 0x2B4 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_MDC__USDHC3_STROBE                         0x054 0x2B4 0x630 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_ENET_MDC__SIM_M_HADDR15                         0x054 0x2B4 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO                        0x058 0x2B8 0x590 0x0 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_MDIO__AUDIOMIX_SAI6_TX_SYNC                0x058 0x2B8 0x528 0x2 0x0</div><div class='add'>+#define MX8MP_IOMUXC_ENET_MDIO__AUDIOMIX_PDM_BIT_STREAM03            0x058 0x2B8 0x4CC 0x3 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_MDIO__GPIO1_IO17                           0x058 0x2B8 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_MDIO__USDHC3_DATA5                         0x058 0x2B8 0x624 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_ENET_MDIO__SIM_M_HADDR16                        0x058 0x2B8 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3                    0x05C 0x2BC 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_TD3__AUDIOMIX_SAI6_TX_BCLK                 0x05C 0x2BC 0x524 0x2 0x0</div><div class='add'>+#define MX8MP_IOMUXC_ENET_TD3__AUDIOMIX_PDM_BIT_STREAM02             0x05C 0x2BC 0x4C8 0x3 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_TD3__GPIO1_IO18                            0x05C 0x2BC 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_TD3__USDHC3_DATA6                          0x05C 0x2BC 0x628 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_ENET_TD3__SIM_M_HADDR17                         0x05C 0x2BC 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2                    0x060 0x2C0 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK   0x060 0x2C0 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_TD2__AUDIOMIX_SAI6_RX_DATA00               0x060 0x2C0 0x51C 0x2 0x0</div><div class='add'>+#define MX8MP_IOMUXC_ENET_TD2__AUDIOMIX_PDM_BIT_STREAM01             0x060 0x2C0 0x4C4 0x3 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_TD2__GPIO1_IO19                            0x060 0x2C0 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_TD2__USDHC3_DATA7                          0x060 0x2C0 0x62C 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_ENET_TD2__SIM_M_HADDR18                         0x060 0x2C0 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1                    0x064 0x2C4 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_TD1__AUDIOMIX_SAI6_RX_SYNC                 0x064 0x2C4 0x520 0x2 0x0</div><div class='add'>+#define MX8MP_IOMUXC_ENET_TD1__AUDIOMIX_PDM_BIT_STREAM00             0x064 0x2C4 0x4C0 0x3 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_TD1__GPIO1_IO20                            0x064 0x2C4 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_TD1__USDHC3_CD_B                           0x064 0x2C4 0x608 0x6 0x1</div><div class='del'>-#define MX8MP_IOMUXC_ENET_TD1__SIM_M_HADDR19                         0x064 0x2C4 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0                    0x068 0x2C8 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_TD0__AUDIOMIX_SAI6_RX_BCLK                 0x068 0x2C8 0x518 0x2 0x0</div><div class='add'>+#define MX8MP_IOMUXC_ENET_TD0__AUDIOMIX_PDM_CLK                      0x068 0x2C8 0x000 0x3 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_TD0__GPIO1_IO21                            0x068 0x2C8 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_TD0__USDHC3_WP                             0x068 0x2C8 0x634 0x6 0x1</div><div class='del'>-#define MX8MP_IOMUXC_ENET_TD0__SIM_M_HADDR20                         0x068 0x2C8 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL              0x06C 0x2CC 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_TX_CTL__AUDIOMIX_SAI6_MCLK                 0x06C 0x2CC 0x514 0x2 0x0</div><div class='del'>-#define MX8MP_IOMUXC_ENET_TX_CTL__AUDIOMIX_SPDIF_OUT                 0x06C 0x2CC 0x000 0x3 0x0</div><div class='add'>+#define MX8MP_IOMUXC_ENET_TX_CTL__AUDIOMIX_SPDIF1_OUT                0x06C 0x2CC 0x000 0x3 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_TX_CTL__GPIO1_IO22                         0x06C 0x2CC 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_TX_CTL__USDHC3_DATA0                       0x06C 0x2CC 0x610 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_ENET_TX_CTL__SIM_M_HADDR21                      0x06C 0x2CC 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK    0x070 0x2D0 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_TXC__ENET_QOS_TX_ER                        0x070 0x2D0 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_TXC__AUDIOMIX_SAI7_TX_DATA00               0x070 0x2D0 0x000 0x2 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_TXC__GPIO1_IO23                            0x070 0x2D0 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_TXC__USDHC3_DATA1                          0x070 0x2D0 0x614 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_ENET_TXC__SIM_M_HADDR22                         0x070 0x2D0 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL              0x074 0x2D4 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_RX_CTL__AUDIOMIX_SAI7_TX_SYNC              0x074 0x2D4 0x540 0x2 0x0</div><div class='del'>-#define MX8MP_IOMUXC_ENET_RX_CTL__AUDIOMIX_BIT_STREAM03              0x074 0x2D4 0x4CC 0x3 0x0</div><div class='add'>+#define MX8MP_IOMUXC_ENET_RX_CTL__AUDIOMIX_PDM_BIT_STREAM03          0x074 0x2D4 0x4CC 0x3 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_RX_CTL__GPIO1_IO24                         0x074 0x2D4 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_RX_CTL__USDHC3_DATA2                       0x074 0x2D4 0x618 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_ENET_RX_CTL__SIM_M_HADDR23                      0x074 0x2D4 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK    0x078 0x2D8 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_RXC__ENET_QOS_RX_ER                        0x078 0x2D8 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_RXC__AUDIOMIX_SAI7_TX_BCLK                 0x078 0x2D8 0x53C 0x2 0x0</div><div class='del'>-#define MX8MP_IOMUXC_ENET_RXC__AUDIOMIX_BIT_STREAM02                 0x078 0x2D8 0x4C8 0x3 0x0</div><div class='add'>+#define MX8MP_IOMUXC_ENET_RXC__AUDIOMIX_PDM_BIT_STREAM02             0x078 0x2D8 0x4C8 0x3 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_RXC__GPIO1_IO25                            0x078 0x2D8 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_RXC__USDHC3_DATA3                          0x078 0x2D8 0x61C 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_ENET_RXC__SIM_M_HADDR24                         0x078 0x2D8 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0                    0x07C 0x2DC 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_RD0__AUDIOMIX_SAI7_RX_DATA00               0x07C 0x2DC 0x534 0x2 0x0</div><div class='del'>-#define MX8MP_IOMUXC_ENET_RD0__AUDIOMIX_BIT_STREAM01                 0x07C 0x2DC 0x4C4 0x3 0x0</div><div class='add'>+#define MX8MP_IOMUXC_ENET_RD0__AUDIOMIX_PDM_BIT_STREAM01             0x07C 0x2DC 0x4C4 0x3 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_RD0__GPIO1_IO26                            0x07C 0x2DC 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_RD0__USDHC3_DATA4                          0x07C 0x2DC 0x620 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_ENET_RD0__SIM_M_HADDR25                         0x07C 0x2DC 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1                    0x080 0x2E0 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_RD1__AUDIOMIX_SAI7_RX_SYNC                 0x080 0x2E0 0x538 0x2 0x0</div><div class='del'>-#define MX8MP_IOMUXC_ENET_RD1__AUDIOMIX_BIT_STREAM00                 0x080 0x2E0 0x4C0 0x3 0x0</div><div class='add'>+#define MX8MP_IOMUXC_ENET_RD1__AUDIOMIX_PDM_BIT_STREAM00             0x080 0x2E0 0x4C0 0x3 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_RD1__GPIO1_IO27                            0x080 0x2E0 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_RD1__USDHC3_RESET_B                        0x080 0x2E0 0x000 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_ENET_RD1__SIM_M_HADDR26                         0x080 0x2E0 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2                    0x084 0x2E4 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_RD2__AUDIOMIX_SAI7_RX_BCLK                 0x084 0x2E4 0x530 0x2 0x0</div><div class='del'>-#define MX8MP_IOMUXC_ENET_RD2__AUDIOMIX_CLK                          0x084 0x2E4 0x000 0x3 0x0</div><div class='add'>+#define MX8MP_IOMUXC_ENET_RD2__AUDIOMIX_PDM_CLK                      0x084 0x2E4 0x000 0x3 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_RD2__GPIO1_IO28                            0x084 0x2E4 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_RD2__USDHC3_CLK                            0x084 0x2E4 0x604 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_ENET_RD2__SIM_M_HADDR27                         0x084 0x2E4 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3                    0x088 0x2E8 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_RD3__AUDIOMIX_SAI7_MCLK                    0x088 0x2E8 0x52C 0x2 0x0</div><div class='del'>-#define MX8MP_IOMUXC_ENET_RD3__AUDIOMIX_SPDIF_IN                     0x088 0x2E8 0x544 0x3 0x0</div><div class='add'>+#define MX8MP_IOMUXC_ENET_RD3__AUDIOMIX_SPDIF1_IN                    0x088 0x2E8 0x544 0x3 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_RD3__GPIO1_IO29                            0x088 0x2E8 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ENET_RD3__USDHC3_CMD                            0x088 0x2E8 0x60C 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_ENET_RD3__SIM_M_HADDR28                         0x088 0x2E8 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK                             0x08C 0x2EC 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_CLK__ENET1_MDC                              0x08C 0x2EC 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_CLK__I2C5_SCL                               0x08C 0x2EC 0x5C4 0x3 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX                           0x08C 0x2EC 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_CLK__UART1_DTE_RX                           0x08C 0x2EC 0x5E8 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_CLK__GPIO2_IO00                             0x08C 0x2EC 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SD1_CLK__SIM_M_HADDR29                          0x08C 0x2EC 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD                             0x090 0x2F0 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_CMD__ENET1_MDIO                             0x090 0x2F0 0x57C 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_CMD__I2C5_SDA                               0x090 0x2F0 0x5C8 0x3 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX                           0x090 0x2F0 0x5E8 0x4 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_CMD__UART1_DTE_TX                           0x090 0x2F0 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_CMD__GPIO2_IO01                             0x090 0x2F0 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SD1_CMD__SIM_M_HADDR30                          0x090 0x2F0 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0                         0x094 0x2F4 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA0__ENET1_RGMII_TD1                      0x094 0x2F4 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA0__I2C6_SCL                             0x094 0x2F4 0x5CC 0x3 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA0__UART1_DCE_RTS                        0x094 0x2F4 0x5E4 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA0__UART1_DTE_CTS                        0x094 0x2F4 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02                           0x094 0x2F4 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SD1_DATA0__SIM_M_HADDR31                        0x094 0x2F4 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1                         0x098 0x2F8 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA1__ENET1_RGMII_TD0                      0x098 0x2F8 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA1__I2C6_SDA                             0x098 0x2F8 0x5D0 0x3 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA1__UART1_DCE_CTS                        0x098 0x2F8 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA1__UART1_DTE_RTS                        0x098 0x2F8 0x5E4 0x4 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA1__GPIO2_IO03                           0x098 0x2F8 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SD1_DATA1__SIM_M_HBURST00                       0x098 0x2F8 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2                         0x09C 0x2FC 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA2__ENET1_RGMII_RD0                      0x09C 0x2FC 0x580 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA2__I2C4_SCL                             0x09C 0x2FC 0x5BC 0x3 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA2__UART2_DCE_TX                         0x09C 0x2FC 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA2__UART2_DTE_RX                         0x09C 0x2FC 0x5F0 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA2__GPIO2_IO04                           0x09C 0x2FC 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SD1_DATA2__SIM_M_HBURST01                       0x09C 0x2FC 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3                         0x0A0 0x300 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA3__ENET1_RGMII_RD1                      0x0A0 0x300 0x584 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA3__I2C4_SDA                             0x0A0 0x300 0x5C0 0x3 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA3__UART2_DCE_RX                         0x0A0 0x300 0x5F0 0x4 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA3__UART2_DTE_TX                         0x0A0 0x300 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA3__GPIO2_IO05                           0x0A0 0x300 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SD1_DATA3__SIM_M_HBURST02                       0x0A0 0x300 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA4__USDHC1_DATA4                         0x0A4 0x304 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA4__ENET1_RGMII_TX_CTL                   0x0A4 0x304 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA4__I2C1_SCL                             0x0A4 0x304 0x5A4 0x3 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS                        0x0A4 0x304 0x5EC 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA4__UART2_DTE_CTS                        0x0A4 0x304 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06                           0x0A4 0x304 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SD1_DATA4__SIM_M_HRESP                          0x0A4 0x304 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA5__USDHC1_DATA5                         0x0A8 0x308 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA5__ENET1_TX_ER                          0x0A8 0x308 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA5__I2C1_SDA                             0x0A8 0x308 0x5A8 0x3 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS                        0x0A8 0x308 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA5__UART2_DTE_RTS                        0x0A8 0x308 0x5EC 0x4 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07                           0x0A8 0x308 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SD1_DATA5__TPSMP_HDATA05                        0x0A8 0x308 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA6__USDHC1_DATA6                         0x0AC 0x30C 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA6__ENET1_RGMII_RX_CTL                   0x0AC 0x30C 0x588 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA6__I2C2_SCL                             0x0AC 0x30C 0x5AC 0x3 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX                         0x0AC 0x30C 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA6__UART3_DTE_RX                         0x0AC 0x30C 0x5F8 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08                           0x0AC 0x30C 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SD1_DATA6__TPSMP_HDATA06                        0x0AC 0x30C 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA7__USDHC1_DATA7                         0x0B0 0x310 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA7__ENET1_RX_ER                          0x0B0 0x310 0x58C 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA7__I2C2_SDA                             0x0B0 0x310 0x5B0 0x3 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX                         0x0B0 0x310 0x5F8 0x4 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA7__UART3_DTE_TX                         0x0B0 0x310 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09                           0x0B0 0x310 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SD1_DATA7__TPSMP_HDATA07                        0x0B0 0x310 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_RESET_B__USDHC1_RESET_B                     0x0B4 0x314 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_RESET_B__ENET1_TX_CLK                       0x0B4 0x314 0x578 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_RESET_B__I2C3_SCL                           0x0B4 0x314 0x5B4 0x3 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_RESET_B__UART3_DCE_RTS                      0x0B4 0x314 0x5F4 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_RESET_B__UART3_DTE_CTS                      0x0B4 0x314 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10                         0x0B4 0x314 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SD1_RESET_B__ECSPI3_TEST_TRIG                   0x0B4 0x314 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE                       0x0B8 0x318 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_STROBE__I2C3_SDA                            0x0B8 0x318 0x5B8 0x3 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_STROBE__UART3_DCE_CTS                       0x0B8 0x318 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_STROBE__UART3_DTE_RTS                       0x0B8 0x318 0x5F4 0x4 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11                          0x0B8 0x318 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SD1_STROBE__USDHC3_TEST_TRIG                    0x0B8 0x318 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B                           0x0BC 0x31C 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12                            0x0BC 0x31C 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SD2_CD_B__CCMSRCGPCMIX_TESTER_ACK               0x0BC 0x31C 0x000 0x6 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK                             0x0C0 0x320 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD2_CLK__ECSPI2_SCLK                            0x0C0 0x320 0x568 0x2 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD2_CLK__UART4_DCE_RX                           0x0C0 0x320 0x600 0x3 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD2_CLK__UART4_DTE_TX                           0x0C0 0x320 0x000 0x3 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD2_CLK__GPIO2_IO13                             0x0C0 0x320 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SD2_CLK__CCMSRCGPCMIX_OBSERVE0                  0x0C0 0x320 0x000 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SD2_CLK__OBSERVE_MUX_OUT00                      0x0C0 0x320 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD                             0x0C4 0x324 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD2_CMD__ECSPI2_MOSI                            0x0C4 0x324 0x570 0x2 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD2_CMD__UART4_DCE_TX                           0x0C4 0x324 0x000 0x3 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD2_CMD__UART4_DTE_RX                           0x0C4 0x324 0x600 0x3 0x1</div><div class='del'>-#define MX8MP_IOMUXC_SD2_CMD__AUDIOMIX_CLK                           0x0C4 0x324 0x000 0x4 0x0</div><div class='add'>+#define MX8MP_IOMUXC_SD2_CMD__AUDIOMIX_PDM_CLK                       0x0C4 0x324 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14                             0x0C4 0x324 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SD2_CMD__CCMSRCGPCMIX_OBSERVE1                  0x0C4 0x324 0x000 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SD2_CMD__OBSERVE_MUX_OUT01                      0x0C4 0x324 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0                         0x0C8 0x328 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD2_DATA0__I2C4_SDA                             0x0C8 0x328 0x5C0 0x2 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_SD2_DATA0__UART2_DCE_RX                         0x0C8 0x328 0x5F0 0x3 0x2</div><div class='ctx'> #define MX8MP_IOMUXC_SD2_DATA0__UART2_DTE_TX                         0x0C8 0x328 0x000 0x3 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SD2_DATA0__AUDIOMIX_BIT_STREAM00                0x0C8 0x328 0x4C0 0x4 0x1</div><div class='add'>+#define MX8MP_IOMUXC_SD2_DATA0__AUDIOMIX_PDM_BIT_STREAM00            0x0C8 0x328 0x4C0 0x4 0x2</div><div class='ctx'> #define MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15                           0x0C8 0x328 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2                0x0C8 0x328 0x000 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SD2_DATA0__OBSERVE_MUX_OUT02                    0x0C8 0x328 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1                         0x0CC 0x32C 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD2_DATA1__I2C4_SCL                             0x0CC 0x32C 0x5BC 0x2 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_SD2_DATA1__UART2_DCE_TX                         0x0CC 0x32C 0x000 0x3 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD2_DATA1__UART2_DTE_RX                         0x0CC 0x32C 0x5F0 0x3 0x3</div><div class='del'>-#define MX8MP_IOMUXC_SD2_DATA1__AUDIOMIX_BIT_STREAM01                0x0CC 0x32C 0x4C4 0x4 0x1</div><div class='add'>+#define MX8MP_IOMUXC_SD2_DATA1__AUDIOMIX_PDM_BIT_STREAM01            0x0CC 0x32C 0x4C4 0x4 0x2</div><div class='ctx'> #define MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16                           0x0CC 0x32C 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SD2_DATA1__CCMSRCGPCMIX_WAIT                    0x0CC 0x32C 0x000 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SD2_DATA1__OBSERVE_MUX_OUT03                    0x0CC 0x32C 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2                         0x0D0 0x330 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD2_DATA2__ECSPI2_SS0                           0x0D0 0x330 0x574 0x2 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SD2_DATA2__AUDIOMIX_SPDIF_OUT                   0x0D0 0x330 0x000 0x3 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SD2_DATA2__AUDIOMIX_BIT_STREAM02                0x0D0 0x330 0x4C8 0x4 0x1</div><div class='add'>+#define MX8MP_IOMUXC_SD2_DATA2__AUDIOMIX_SPDIF1_OUT                  0x0D0 0x330 0x000 0x3 0x0</div><div class='add'>+#define MX8MP_IOMUXC_SD2_DATA2__AUDIOMIX_PDM_BIT_STREAM02            0x0D0 0x330 0x4C8 0x4 0x2</div><div class='ctx'> #define MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17                           0x0D0 0x330 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SD2_DATA2__CCMSRCGPCMIX_STOP                    0x0D0 0x330 0x000 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SD2_DATA2__OBSERVE_MUX_OUT04                    0x0D0 0x330 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3                         0x0D4 0x334 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD2_DATA3__ECSPI2_MISO                          0x0D4 0x334 0x56C 0x2 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SD2_DATA3__AUDIOMIX_SPDIF_IN                    0x0D4 0x334 0x544 0x3 0x1</div><div class='del'>-#define MX8MP_IOMUXC_SD2_DATA3__AUDIOMIX_BIT_STREAM03                0x0D4 0x334 0x4CC 0x4 0x1</div><div class='add'>+#define MX8MP_IOMUXC_SD2_DATA3__AUDIOMIX_SPDIF1_IN                   0x0D4 0x334 0x544 0x3 0x1</div><div class='add'>+#define MX8MP_IOMUXC_SD2_DATA3__AUDIOMIX_PDM_BIT_STREAM03            0x0D4 0x334 0x4CC 0x4 0x2</div><div class='ctx'> #define MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18                           0x0D4 0x334 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET             0x0D4 0x334 0x000 0x6 0x0</div><div class='add'>+#define MX8MP_IOMUXC_SD2_DATA3__SRC_EARLY_RESET                      0x0D4 0x334 0x000 0x6 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD2_RESET_B__USDHC2_RESET_B                     0x0D8 0x338 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19                         0x0D8 0x338 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET          0x0D8 0x338 0x000 0x6 0x0</div><div class='add'>+#define MX8MP_IOMUXC_SD2_RESET_B__SRC_SYSTEM_RESET                   0x0D8 0x338 0x000 0x6 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD2_WP__USDHC2_WP                               0x0DC 0x33C 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD2_WP__GPIO2_IO20                              0x0DC 0x33C 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SD2_WP__CORESIGHT_EVENTI                        0x0DC 0x33C 0x000 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SD2_WP__SIM_M_HMASTLOCK                         0x0DC 0x33C 0x000 0x7 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_ALE__RAWNAND_ALE                           0x0E0 0x340 0x000 0x0 0x0</div><div class='add'>+#define MX8MP_IOMUXC_NAND_ALE__NAND_ALE                              0x0E0 0x340 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK                        0x0E0 0x340 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_ALE__AUDIOMIX_SAI3_TX_BCLK                 0x0E0 0x340 0x4E8 0x2 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_ALE__MEDIAMIX_ISP_FL_TRIG_0                0x0E0 0x340 0x5D4 0x3 0x1</div><div class='add'>+#define MX8MP_IOMUXC_NAND_ALE__ISP_FL_TRIG_0                         0x0E0 0x340 0x5D4 0x3 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_ALE__UART3_DCE_RX                          0x0E0 0x340 0x5F8 0x4 0x2</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_ALE__UART3_DTE_TX                          0x0E0 0x340 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00                            0x0E0 0x340 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_ALE__CORESIGHT_TRACE_CLK                   0x0E0 0x340 0x000 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_ALE__SIM_M_HPROT00                         0x0E0 0x340 0x000 0x7 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_CE0_B__RAWNAND_CE0_B                       0x0E4 0x344 0x000 0x0 0x0</div><div class='add'>+#define MX8MP_IOMUXC_NAND_CE0_B__NAND_CE0_B                          0x0E4 0x344 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B                     0x0E4 0x344 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_CE0_B__AUDIOMIX_SAI3_TX_DATA00             0x0E4 0x344 0x000 0x2 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_CE0_B__MEDIAMIX_ISP_SHUTTER_TRIG_0         0x0E4 0x344 0x5DC 0x3 0x1</div><div class='add'>+#define MX8MP_IOMUXC_NAND_CE0_B__ISP_SHUTTER_TRIG_0                  0x0E4 0x344 0x5DC 0x3 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_CE0_B__UART3_DCE_TX                        0x0E4 0x344 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_CE0_B__UART3_DTE_RX                        0x0E4 0x344 0x5F8 0x4 0x3</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01                          0x0E4 0x344 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_CE0_B__CORESIGHT_TRACE_CTL                 0x0E4 0x344 0x000 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_CE0_B__SIM_M_HPROT01                       0x0E4 0x344 0x000 0x7 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_CE1_B__RAWNAND_CE1_B                       0x0E8 0x348 0x000 0x0 0x0</div><div class='add'>+#define MX8MP_IOMUXC_NAND_CE1_B__NAND_CE1_B                          0x0E8 0x348 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_CE1_B__FLEXSPI_A_SS1_B                     0x0E8 0x348 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE                       0x0E8 0x348 0x630 0x2 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_CE1_B__I2C4_SCL                            0x0E8 0x348 0x5BC 0x4 0x2</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_CE1_B__GPIO3_IO02                          0x0E8 0x348 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_CE1_B__CORESIGHT_TRACE00                   0x0E8 0x348 0x000 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_CE1_B__SIM_M_HPROT02                       0x0E8 0x348 0x000 0x7 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_CE2_B__RAWNAND_CE2_B                       0x0EC 0x34C 0x000 0x0 0x0</div><div class='add'>+#define MX8MP_IOMUXC_NAND_CE2_B__NAND_CE2_B                          0x0EC 0x34C 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_CE2_B__FLEXSPI_B_SS0_B                     0x0EC 0x34C 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5                        0x0EC 0x34C 0x624 0x2 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_CE2_B__I2C4_SDA                            0x0EC 0x34C 0x5C0 0x4 0x2</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_CE2_B__GPIO3_IO03                          0x0EC 0x34C 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_CE2_B__CORESIGHT_TRACE01                   0x0EC 0x34C 0x000 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_CE2_B__SIM_M_HPROT03                       0x0EC 0x34C 0x000 0x7 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_CE3_B__RAWNAND_CE3_B                       0x0F0 0x350 0x000 0x0 0x0</div><div class='add'>+#define MX8MP_IOMUXC_NAND_CE3_B__NAND_CE3_B                          0x0F0 0x350 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_CE3_B__FLEXSPI_B_SS1_B                     0x0F0 0x350 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6                        0x0F0 0x350 0x628 0x2 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_CE3_B__I2C3_SDA                            0x0F0 0x350 0x5B8 0x4 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_CE3_B__GPIO3_IO04                          0x0F0 0x350 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_CE3_B__CORESIGHT_TRACE02                   0x0F0 0x350 0x000 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_CE3_B__SIM_M_HADDR00                       0x0F0 0x350 0x000 0x7 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_CLE__RAWNAND_CLE                           0x0F4 0x354 0x000 0x0 0x0</div><div class='add'>+#define MX8MP_IOMUXC_NAND_CLE__NAND_CLE                              0x0F4 0x354 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_CLE__FLEXSPI_B_SCLK                        0x0F4 0x354 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7                          0x0F4 0x354 0x62C 0x2 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_CLE__UART4_DCE_RX                          0x0F4 0x354 0x600 0x4 0x2</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_CLE__UART4_DTE_TX                          0x0F4 0x354 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_CLE__GPIO3_IO05                            0x0F4 0x354 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_CLE__CORESIGHT_TRACE03                     0x0F4 0x354 0x000 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_CLE__SIM_M_HADDR01                         0x0F4 0x354 0x000 0x7 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_DATA00__RAWNAND_DATA00                     0x0F8 0x358 0x000 0x0 0x0</div><div class='add'>+#define MX8MP_IOMUXC_NAND_DATA00__NAND_DATA00                        0x0F8 0x358 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00                   0x0F8 0x358 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DATA00__AUDIOMIX_SAI3_RX_DATA00            0x0F8 0x358 0x4E4 0x2 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_DATA00__MEDIAMIX_ISP_FLASH_TRIG_0          0x0F8 0x358 0x000 0x3 0x0</div><div class='add'>+#define MX8MP_IOMUXC_NAND_DATA00__ISP_FLASH_TRIG_0                   0x0F8 0x358 0x000 0x3 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DATA00__UART4_DCE_RX                       0x0F8 0x358 0x600 0x4 0x3</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DATA00__UART4_DTE_TX                       0x0F8 0x358 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06                         0x0F8 0x358 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DATA00__CORESIGHT_TRACE04                  0x0F8 0x358 0x000 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_DATA00__SIM_M_HADDR02                      0x0F8 0x358 0x000 0x7 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_DATA01__RAWNAND_DATA01                     0x0FC 0x35C 0x000 0x0 0x0</div><div class='add'>+#define MX8MP_IOMUXC_NAND_DATA01__NAND_DATA01                        0x0FC 0x35C 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01                   0x0FC 0x35C 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DATA01__AUDIOMIX_SAI3_TX_SYNC              0x0FC 0x35C 0x4EC 0x2 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_DATA01__MEDIAMIX_ISP_PRELIGHT_TRIG_0       0x0FC 0x35C 0x000 0x3 0x0</div><div class='add'>+#define MX8MP_IOMUXC_NAND_DATA01__ISP_PRELIGHT_TRIG_0                0x0FC 0x35C 0x000 0x3 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DATA01__UART4_DCE_TX                       0x0FC 0x35C 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DATA01__UART4_DTE_RX                       0x0FC 0x35C 0x600 0x4 0x4</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07                         0x0FC 0x35C 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DATA01__CORESIGHT_TRACE05                  0x0FC 0x35C 0x000 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_DATA01__SIM_M_HADDR03                      0x0FC 0x35C 0x000 0x7 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_DATA02__RAWNAND_DATA02                     0x100 0x360 0x000 0x0 0x0</div><div class='add'>+#define MX8MP_IOMUXC_NAND_DATA02__NAND_DATA02                        0x100 0x360 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02                   0x100 0x360 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DATA02__USDHC3_CD_B                        0x100 0x360 0x608 0x2 0x2</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DATA02__UART4_DCE_CTS                      0x100 0x360 0x000 0x3 0x0</div><div class='hunk'>@@ -396,82 +363,71 @@</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DATA02__I2C4_SDA                           0x100 0x360 0x5C0 0x4 0x3</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08                         0x100 0x360 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DATA02__CORESIGHT_TRACE06                  0x100 0x360 0x000 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_DATA02__SIM_M_HADDR04                      0x100 0x360 0x000 0x7 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_DATA03__RAWNAND_DATA03                     0x104 0x364 0x000 0x0 0x0</div><div class='add'>+#define MX8MP_IOMUXC_NAND_DATA03__NAND_DATA03                        0x104 0x364 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03                   0x104 0x364 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DATA03__USDHC3_WP                          0x104 0x364 0x634 0x2 0x2</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DATA03__UART4_DCE_RTS                      0x104 0x364 0x5FC 0x3 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DATA03__UART4_DTE_CTS                      0x104 0x364 0x000 0x3 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_DATA03__MEDIAMIX_ISP_FL_TRIG_1             0x104 0x364 0x5D8 0x4 0x1</div><div class='add'>+#define MX8MP_IOMUXC_NAND_DATA03__ISP_FL_TRIG_1                      0x104 0x364 0x5D8 0x4 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09                         0x104 0x364 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DATA03__CORESIGHT_TRACE07                  0x104 0x364 0x000 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_DATA03__SIM_M_HADDR05                      0x104 0x364 0x000 0x7 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_DATA04__RAWNAND_DATA04                     0x108 0x368 0x000 0x0 0x0</div><div class='add'>+#define MX8MP_IOMUXC_NAND_DATA04__NAND_DATA04                        0x108 0x368 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DATA04__FLEXSPI_B_DATA00                   0x108 0x368 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0                       0x108 0x368 0x610 0x2 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DATA04__FLEXSPI_A_DATA04                   0x108 0x368 0x000 0x3 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_DATA04__MEDIAMIX_ISP_SHUTTER_TRIG_1        0x108 0x368 0x5E0 0x4 0x1</div><div class='add'>+#define MX8MP_IOMUXC_NAND_DATA04__ISP_SHUTTER_TRIG_1                 0x108 0x368 0x5E0 0x4 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DATA04__GPIO3_IO10                         0x108 0x368 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DATA04__CORESIGHT_TRACE08                  0x108 0x368 0x000 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_DATA04__SIM_M_HADDR06                      0x108 0x368 0x000 0x7 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_DATA05__RAWNAND_DATA05                     0x10C 0x36C 0x000 0x0 0x0</div><div class='add'>+#define MX8MP_IOMUXC_NAND_DATA05__NAND_DATA05                        0x10C 0x36C 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DATA05__FLEXSPI_B_DATA01                   0x10C 0x36C 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1                       0x10C 0x36C 0x614 0x2 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DATA05__FLEXSPI_A_DATA05                   0x10C 0x36C 0x000 0x3 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_DATA05__MEDIAMIX_ISP_FLASH_TRIG_1          0x10C 0x36C 0x000 0x4 0x0</div><div class='add'>+#define MX8MP_IOMUXC_NAND_DATA05__ISP_FLASH_TRIG_1                   0x10C 0x36C 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DATA05__GPIO3_IO11                         0x10C 0x36C 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DATA05__CORESIGHT_TRACE09                  0x10C 0x36C 0x000 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_DATA05__SIM_M_HADDR07                      0x10C 0x36C 0x000 0x7 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_DATA06__RAWNAND_DATA06                     0x110 0x370 0x000 0x0 0x0</div><div class='add'>+#define MX8MP_IOMUXC_NAND_DATA06__NAND_DATA06                        0x110 0x370 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DATA06__FLEXSPI_B_DATA02                   0x110 0x370 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2                       0x110 0x370 0x618 0x2 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DATA06__FLEXSPI_A_DATA06                   0x110 0x370 0x000 0x3 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_DATA06__MEDIAMIX_ISP_PRELIGHT_TRIG_1       0x110 0x370 0x000 0x4 0x0</div><div class='add'>+#define MX8MP_IOMUXC_NAND_DATA06__ISP_PRELIGHT_TRIG_1                0x110 0x370 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DATA06__GPIO3_IO12                         0x110 0x370 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DATA06__CORESIGHT_TRACE10                  0x110 0x370 0x000 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_DATA06__SIM_M_HADDR08                      0x110 0x370 0x000 0x7 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_DATA07__RAWNAND_DATA07                     0x114 0x374 0x000 0x0 0x0</div><div class='add'>+#define MX8MP_IOMUXC_NAND_DATA07__NAND_DATA07                        0x114 0x374 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DATA07__FLEXSPI_B_DATA03                   0x114 0x374 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3                       0x114 0x374 0x61C 0x2 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DATA07__FLEXSPI_A_DATA07                   0x114 0x374 0x000 0x3 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_DATA07__MEDIAMIX_ISP_SHUTTER_OPEN_1        0x114 0x374 0x000 0x4 0x0</div><div class='add'>+#define MX8MP_IOMUXC_NAND_DATA07__ISP_SHUTTER_OPEN_1                 0x114 0x374 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DATA07__GPIO3_IO13                         0x114 0x374 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DATA07__CORESIGHT_TRACE11                  0x114 0x374 0x000 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_DATA07__SIM_M_HADDR09                      0x114 0x374 0x000 0x7 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_DQS__RAWNAND_DQS                           0x118 0x378 0x000 0x0 0x0</div><div class='add'>+#define MX8MP_IOMUXC_NAND_DQS__NAND_DQS                              0x118 0x378 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DQS__FLEXSPI_A_DQS                         0x118 0x378 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DQS__AUDIOMIX_SAI3_MCLK                    0x118 0x378 0x4E0 0x2 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_DQS__MEDIAMIX_ISP_SHUTTER_OPEN_0           0x118 0x378 0x000 0x3 0x0</div><div class='add'>+#define MX8MP_IOMUXC_NAND_DQS__ISP_SHUTTER_OPEN_0                    0x118 0x378 0x000 0x3 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DQS__I2C3_SCL                              0x118 0x378 0x5B4 0x4 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14                            0x118 0x378 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_DQS__CORESIGHT_TRACE12                     0x118 0x378 0x000 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_DQS__SIM_M_HADDR10                         0x118 0x378 0x000 0x7 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_RE_B__RAWNAND_RE_B                         0x11C 0x37C 0x000 0x0 0x0</div><div class='add'>+#define MX8MP_IOMUXC_NAND_RE_B__NAND_RE_B                            0x11C 0x37C 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_RE_B__FLEXSPI_B_DQS                        0x11C 0x37C 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4                         0x11C 0x37C 0x620 0x2 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_RE_B__UART4_DCE_TX                         0x11C 0x37C 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_RE_B__UART4_DTE_RX                         0x11C 0x37C 0x600 0x4 0x5</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_RE_B__GPIO3_IO15                           0x11C 0x37C 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_RE_B__CORESIGHT_TRACE13                    0x11C 0x37C 0x000 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_RE_B__SIM_M_HADDR11                        0x11C 0x37C 0x000 0x7 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_READY_B__RAWNAND_READY_B                   0x120 0x380 0x000 0x0 0x0</div><div class='add'>+#define MX8MP_IOMUXC_NAND_READY_B__NAND_READY_B                      0x120 0x380 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B                    0x120 0x380 0x000 0x2 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_READY_B__I2C3_SCL                          0x120 0x380 0x5B4 0x4 0x2</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16                        0x120 0x380 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_READY_B__CORESIGHT_TRACE14                 0x120 0x380 0x000 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_READY_B__SIM_M_HADDR12                     0x120 0x380 0x000 0x7 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_WE_B__RAWNAND_WE_B                         0x124 0x384 0x000 0x0 0x0</div><div class='add'>+#define MX8MP_IOMUXC_NAND_WE_B__NAND_WE_B                            0x124 0x384 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK                           0x124 0x384 0x604 0x2 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_WE_B__I2C3_SDA                             0x124 0x384 0x5B8 0x4 0x2</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_WE_B__GPIO3_IO17                           0x124 0x384 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_WE_B__CORESIGHT_TRACE15                    0x124 0x384 0x000 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_WE_B__SIM_M_HADDR13                        0x124 0x384 0x000 0x7 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_WP_B__RAWNAND_WP_B                         0x128 0x388 0x000 0x0 0x0</div><div class='add'>+#define MX8MP_IOMUXC_NAND_WP_B__NAND_WP_B                            0x128 0x388 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD                           0x128 0x388 0x60C 0x2 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_WP_B__I2C4_SCL                             0x128 0x388 0x5BC 0x4 0x3</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_WP_B__GPIO3_IO18                           0x128 0x388 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_NAND_WP_B__CORESIGHT_EVENTO                     0x128 0x388 0x000 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_NAND_WP_B__SIM_M_HADDR14                        0x128 0x388 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI5_RX_SYNC                0x12C 0x38C 0x508 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00              0x12C 0x38C 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT                             0x12C 0x38C 0x000 0x2 0x0</div><div class='hunk'>@@ -481,33 +437,33 @@</div><div class='ctx'> #define MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_SAI1_TX_DATA01               0x130 0x390 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT                              0x130 0x390 0x000 0x2 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA                              0x130 0x390 0x5D0 0x3 0x1</div><div class='del'>-#define MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_CLK                          0x130 0x390 0x000 0x4 0x0</div><div class='add'>+#define MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CLK                      0x130 0x390 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20                            0x130 0x390 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI5_RX_DATA00              0x134 0x394 0x4F8 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI1_TX_DATA02              0x134 0x394 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT                             0x134 0x394 0x000 0x2 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL                             0x134 0x394 0x5C4 0x3 0x1</div><div class='del'>-#define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_BIT_STREAM00                0x134 0x394 0x4C0 0x4 0x2</div><div class='add'>+#define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_PDM_BIT_STREAM00            0x134 0x394 0x4C0 0x4 0x3</div><div class='ctx'> #define MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21                           0x134 0x394 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_RX_DATA01              0x138 0x398 0x4FC 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_DATA03              0x138 0x398 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC                0x138 0x398 0x4D8 0x2 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC                0x138 0x398 0x510 0x3 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_BIT_STREAM01                0x138 0x398 0x4C4 0x4 0x2</div><div class='add'>+#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_PDM_BIT_STREAM01            0x138 0x398 0x4C4 0x4 0x3</div><div class='ctx'> #define MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22                           0x138 0x398 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX                              0x138 0x398 0x000 0x6 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_RX_DATA02              0x13C 0x39C 0x500 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI1_TX_DATA04              0x13C 0x39C 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI1_TX_SYNC                0x13C 0x39C 0x4D8 0x2 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK                0x13C 0x39C 0x50C 0x3 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_BIT_STREAM02                0x13C 0x39C 0x4C8 0x4 0x2</div><div class='add'>+#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_PDM_BIT_STREAM02            0x13C 0x39C 0x4C8 0x4 0x3</div><div class='ctx'> #define MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23                           0x13C 0x39C 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX                              0x13C 0x39C 0x54C 0x6 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_RX_DATA03              0x140 0x3A0 0x504 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI1_TX_DATA05              0x140 0x3A0 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI1_TX_SYNC                0x140 0x3A0 0x4D8 0x2 0x2</div><div class='ctx'> #define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_TX_DATA00              0x140 0x3A0 0x000 0x3 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_BIT_STREAM03                0x140 0x3A0 0x4CC 0x4 0x2</div><div class='add'>+#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_PDM_BIT_STREAM03            0x140 0x3A0 0x4CC 0x4 0x3</div><div class='ctx'> #define MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24                           0x140 0x3A0 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX                              0x140 0x3A0 0x000 0x6 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI5_MCLK                   0x144 0x3A4 0x4F0 0x0 0x0</div><div class='hunk'>@@ -517,33 +473,27 @@</div><div class='ctx'> #define MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25                           0x144 0x3A4 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX                              0x144 0x3A4 0x550 0x6 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_RXFS__AUDIOMIX_SAI1_RX_SYNC                0x148 0x3A8 0x4D0 0x0 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SAI1_RXFS__AUDIOMIX_SAI5_RX_SYNC                0x148 0x3A8 0x508 0x1 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN                 0x148 0x3A8 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00                           0x148 0x3A8 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_RXC__AUDIOMIX_SAI1_RX_BCLK                 0x14C 0x3AC 0x000 0x0 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SAI1_RXC__AUDIOMIX_SAI5_RX_BCLK                 0x14C 0x3AC 0x4F4 0x1 0x1</div><div class='del'>-#define MX8MP_IOMUXC_SAI1_RXC__AUDIOMIX_CLK                          0x14C 0x3AC 0x000 0x3 0x0</div><div class='add'>+#define MX8MP_IOMUXC_SAI1_RXC__AUDIOMIX_PDM_CLK                      0x14C 0x3AC 0x000 0x3 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT                 0x14C 0x3AC 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01                            0x14C 0x3AC 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00              0x150 0x3B0 0x000 0x0 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI5_RX_DATA00              0x150 0x3B0 0x4F8 0x1 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_TX_DATA01              0x150 0x3B0 0x000 0x2 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_BIT_STREAM00                0x150 0x3B0 0x4C0 0x3 0x3</div><div class='add'>+#define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_PDM_BIT_STREAM00            0x150 0x3B0 0x4C0 0x3 0x4</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN                 0x150 0x3B0 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02                           0x150 0x3B0 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_SAI1_RX_DATA01              0x154 0x3B4 0x000 0x0 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_SAI5_RX_DATA01              0x154 0x3B4 0x4FC 0x1 0x1</div><div class='del'>-#define MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_BIT_STREAM01                0x154 0x3B4 0x4C4 0x3 0x3</div><div class='add'>+#define MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_PDM_BIT_STREAM01            0x154 0x3B4 0x4C4 0x3 0x4</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_RXD1__ENET1_1588_EVENT1_OUT                0x154 0x3B4 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03                           0x154 0x3B4 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_SAI1_RX_DATA02              0x158 0x3B8 0x000 0x0 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_SAI5_RX_DATA02              0x158 0x3B8 0x500 0x1 0x1</div><div class='del'>-#define MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_BIT_STREAM02                0x158 0x3B8 0x4C8 0x3 0x3</div><div class='add'>+#define MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_PDM_BIT_STREAM02            0x158 0x3B8 0x4C8 0x3 0x4</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC                            0x158 0x3B8 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04                           0x158 0x3B8 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_RXD3__AUDIOMIX_SAI1_RX_DATA03              0x15C 0x3BC 0x000 0x0 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SAI1_RXD3__AUDIOMIX_SAI5_RX_DATA03              0x15C 0x3BC 0x504 0x1 0x1</div><div class='del'>-#define MX8MP_IOMUXC_SAI1_RXD3__AUDIOMIX_BIT_STREAM03                0x15C 0x3BC 0x4CC 0x3 0x3</div><div class='add'>+#define MX8MP_IOMUXC_SAI1_RXD3__AUDIOMIX_PDM_BIT_STREAM03            0x15C 0x3BC 0x4CC 0x3 0x4</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO                           0x15C 0x3BC 0x57C 0x4 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05                           0x15C 0x3BC 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI1_RX_DATA04              0x160 0x3C0 0x000 0x0 0x0</div><div class='hunk'>@@ -569,27 +519,21 @@</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3                      0x16C 0x3CC 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_RXD7__GPIO4_IO09                           0x16C 0x3CC 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_TXFS__AUDIOMIX_SAI1_TX_SYNC                0x170 0x3D0 0x4D8 0x0 0x4</div><div class='del'>-#define MX8MP_IOMUXC_SAI1_TXFS__AUDIOMIX_SAI5_TX_SYNC                0x170 0x3D0 0x510 0x1 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL                   0x170 0x3D0 0x588 0x4 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_TXFS__GPIO4_IO10                           0x170 0x3D0 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_TXC__AUDIOMIX_SAI1_TX_BCLK                 0x174 0x3D4 0x4D4 0x0 0x1</div><div class='del'>-#define MX8MP_IOMUXC_SAI1_TXC__AUDIOMIX_SAI5_TX_BCLK                 0x174 0x3D4 0x50C 0x1 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC                       0x174 0x3D4 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11                            0x174 0x3D4 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_TXD0__AUDIOMIX_SAI1_TX_DATA00              0x178 0x3D8 0x000 0x0 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SAI1_TXD0__AUDIOMIX_SAI5_TX_DATA00              0x178 0x3D8 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0                      0x178 0x3D8 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12                           0x178 0x3D8 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_TXD1__AUDIOMIX_SAI1_TX_DATA01              0x17C 0x3DC 0x000 0x0 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SAI1_TXD1__AUDIOMIX_SAI5_TX_DATA01              0x17C 0x3DC 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1                      0x17C 0x3DC 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_TXD1__GPIO4_IO13                           0x17C 0x3DC 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_TXD2__AUDIOMIX_SAI1_TX_DATA02              0x180 0x3E0 0x000 0x0 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SAI1_TXD2__AUDIOMIX_SAI5_TX_DATA02              0x180 0x3E0 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2                      0x180 0x3E0 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14                           0x180 0x3E0 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_TXD3__AUDIOMIX_SAI1_TX_DATA03              0x184 0x3E4 0x000 0x0 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SAI1_TXD3__AUDIOMIX_SAI5_TX_DATA03              0x184 0x3E4 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3                      0x184 0x3E4 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_TXD3__GPIO4_IO15                           0x184 0x3E4 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI1_TX_DATA04              0x188 0x3E8 0x000 0x0 0x0</div><div class='hunk'>@@ -609,11 +553,10 @@</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18                           0x190 0x3F0 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_SAI1_TX_DATA07              0x194 0x3F4 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_SAI6_MCLK                   0x194 0x3F4 0x514 0x1 0x2</div><div class='del'>-#define MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_CLK                         0x194 0x3F4 0x000 0x3 0x0</div><div class='add'>+#define MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_PDM_CLK                     0x194 0x3F4 0x000 0x3 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_TXD7__ENET1_TX_ER                          0x194 0x3F4 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19                           0x194 0x3F4 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK                   0x198 0x3F8 0x000 0x0 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI5_MCLK                   0x198 0x3F8 0x4F0 0x1 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_TX_BCLK                0x198 0x3F8 0x4D4 0x2 0x2</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK                         0x198 0x3F8 0x578 0x4 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20                           0x198 0x3F8 0x000 0x5 0x0</div><div class='hunk'>@@ -624,16 +567,14 @@</div><div class='ctx'> #define MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX                         0x19C 0x3FC 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI2_RXFS__UART1_DTE_RX                         0x19C 0x3FC 0x5E8 0x4 0x2</div><div class='ctx'> #define MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21                           0x19C 0x3FC 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_BIT_STREAM02                0x19C 0x3FC 0x4C8 0x6 0x4</div><div class='del'>-#define MX8MP_IOMUXC_SAI2_RXFS__SIM_M_HSIZE00                        0x19C 0x3FC 0x000 0x7 0x0</div><div class='add'>+#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_PDM_BIT_STREAM02            0x19C 0x3FC 0x4C8 0x6 0x5</div><div class='ctx'> #define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_SAI2_RX_BCLK                 0x1A0 0x400 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_SAI5_TX_BCLK                 0x1A0 0x400 0x50C 0x1 0x2</div><div class='ctx'> #define MX8MP_IOMUXC_SAI2_RXC__CAN1_TX                               0x1A0 0x400 0x000 0x3 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX                          0x1A0 0x400 0x5E8 0x4 0x3</div><div class='ctx'> #define MX8MP_IOMUXC_SAI2_RXC__UART1_DTE_TX                          0x1A0 0x400 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22                            0x1A0 0x400 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_BIT_STREAM01                 0x1A0 0x400 0x4C4 0x6 0x4</div><div class='del'>-#define MX8MP_IOMUXC_SAI2_RXC__SIM_M_HSIZE01                         0x1A0 0x400 0x000 0x7 0x0</div><div class='add'>+#define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_PDM_BIT_STREAM01             0x1A0 0x400 0x4C4 0x6 0x5</div><div class='ctx'> #define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00              0x1A4 0x404 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI5_TX_DATA00              0x1A4 0x404 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI2_RXD0__ENET_QOS_1588_EVENT2_OUT             0x1A4 0x404 0x000 0x2 0x0</div><div class='hunk'>@@ -641,8 +582,7 @@</div><div class='ctx'> #define MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS                        0x1A4 0x404 0x5E4 0x4 0x2</div><div class='ctx'> #define MX8MP_IOMUXC_SAI2_RXD0__UART1_DTE_CTS                        0x1A4 0x404 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23                           0x1A4 0x404 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_BIT_STREAM03                0x1A4 0x404 0x4CC 0x6 0x4</div><div class='del'>-#define MX8MP_IOMUXC_SAI2_RXD0__SIM_M_HSIZE02                        0x1A4 0x404 0x000 0x7 0x0</div><div class='add'>+#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_PDM_BIT_STREAM03            0x1A4 0x404 0x4CC 0x6 0x5</div><div class='ctx'> #define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC                0x1A8 0x408 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI5_TX_DATA01              0x1A8 0x408 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI2_TXFS__ENET_QOS_1588_EVENT3_OUT             0x1A8 0x408 0x000 0x2 0x0</div><div class='hunk'>@@ -650,22 +590,18 @@</div><div class='ctx'> #define MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS                        0x1A8 0x408 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI2_TXFS__UART1_DTE_RTS                        0x1A8 0x408 0x5E4 0x4 0x3</div><div class='ctx'> #define MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24                           0x1A8 0x408 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_BIT_STREAM02                0x1A8 0x408 0x4C8 0x6 0x5</div><div class='del'>-#define MX8MP_IOMUXC_SAI2_TXFS__SIM_M_HWRITE                         0x1A8 0x408 0x000 0x7 0x0</div><div class='add'>+#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_PDM_BIT_STREAM02            0x1A8 0x408 0x4C8 0x6 0x6</div><div class='ctx'> #define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK                 0x1AC 0x40C 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI5_TX_DATA02               0x1AC 0x40C 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI2_TXC__CAN1_RX                               0x1AC 0x40C 0x54C 0x3 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25                            0x1AC 0x40C 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_BIT_STREAM01                 0x1AC 0x40C 0x4C4 0x6 0x5</div><div class='del'>-#define MX8MP_IOMUXC_SAI2_TXC__SIM_M_HREADYOUT                       0x1AC 0x40C 0x000 0x7 0x0</div><div class='add'>+#define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_PDM_BIT_STREAM01             0x1AC 0x40C 0x4C4 0x6 0x6</div><div class='ctx'> #define MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00              0x1B0 0x410 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI5_TX_DATA03              0x1B0 0x410 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_EVENT2_IN              0x1B0 0x410 0x000 0x2 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX                              0x1B0 0x410 0x000 0x3 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_EVENT2_AUX_IN          0x1B0 0x410 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26                           0x1B0 0x410 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SAI2_TXD0__CCMSRCGPCMIX_BOOT_MODE04             0x1B0 0x410 0x000 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SAI2_TXD0__TPSMP_CLK                            0x1B0 0x410 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK                   0x1B4 0x414 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI5_MCLK                   0x1B4 0x414 0x4F0 0x1 0x2</div><div class='ctx'> #define MX8MP_IOMUXC_SAI2_MCLK__ENET_QOS_1588_EVENT3_IN              0x1B4 0x414 0x000 0x2 0x0</div><div class='hunk'>@@ -673,15 +609,13 @@</div><div class='ctx'> #define MX8MP_IOMUXC_SAI2_MCLK__ENET_QOS_1588_EVENT3_AUX_IN          0x1B4 0x414 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27                           0x1B4 0x414 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI3_MCLK                   0x1B4 0x414 0x4E0 0x6 0x1</div><div class='del'>-#define MX8MP_IOMUXC_SAI2_MCLK__TPSMP_HDATA_DIR                      0x1B4 0x414 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_SYNC                0x1B8 0x418 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI2_RX_DATA01              0x1B8 0x418 0x4DC 0x1 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI5_RX_SYNC                0x1B8 0x418 0x508 0x2 0x2</div><div class='ctx'> #define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_DATA01              0x1B8 0x418 0x000 0x3 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SPDIF_IN                    0x1B8 0x418 0x544 0x4 0x2</div><div class='add'>+#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SPDIF1_IN                   0x1B8 0x418 0x544 0x4 0x2</div><div class='ctx'> #define MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28                           0x1B8 0x418 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_BIT_STREAM00                0x1B8 0x418 0x4C0 0x6 0x4</div><div class='del'>-#define MX8MP_IOMUXC_SAI3_RXFS__TPSMP_HTRANS00                       0x1B8 0x418 0x000 0x7 0x0</div><div class='add'>+#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_PDM_BIT_STREAM00            0x1B8 0x418 0x4C0 0x6 0x5</div><div class='ctx'> #define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI3_RX_BCLK                 0x1BC 0x41C 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI2_RX_DATA02               0x1BC 0x41C 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI5_RX_BCLK                 0x1BC 0x41C 0x4F4 0x2 0x2</div><div class='hunk'>@@ -689,16 +623,14 @@</div><div class='ctx'> #define MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS                         0x1BC 0x41C 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI3_RXC__UART2_DTE_RTS                         0x1BC 0x41C 0x5EC 0x4 0x2</div><div class='ctx'> #define MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29                            0x1BC 0x41C 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_CLK                          0x1BC 0x41C 0x000 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SAI3_RXC__TPSMP_HTRANS01                        0x1BC 0x41C 0x000 0x7 0x0</div><div class='add'>+#define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_PDM_CLK                      0x1BC 0x41C 0x000 0x6 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00               0x1C0 0x420 0x4E4 0x0 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI2_RX_DATA03               0x1C0 0x420 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI5_RX_DATA00               0x1C0 0x420 0x4F8 0x2 0x2</div><div class='ctx'> #define MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS                         0x1C0 0x420 0x5EC 0x4 0x3</div><div class='ctx'> #define MX8MP_IOMUXC_SAI3_RXD__UART2_DTE_CTS                         0x1C0 0x420 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30                            0x1C0 0x420 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_BIT_STREAM01                 0x1C0 0x420 0x4C4 0x6 0x6</div><div class='del'>-#define MX8MP_IOMUXC_SAI3_RXD__TPSMP_HDATA00                         0x1C0 0x420 0x000 0x7 0x0</div><div class='add'>+#define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_PDM_BIT_STREAM01             0x1C0 0x420 0x4C4 0x6 0x7</div><div class='ctx'> #define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC                0x1C4 0x424 0x4EC 0x0 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI2_TX_DATA01              0x1C4 0x424 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI5_RX_DATA01              0x1C4 0x424 0x4FC 0x2 0x2</div><div class='hunk'>@@ -706,8 +638,7 @@</div><div class='ctx'> #define MX8MP_IOMUXC_SAI3_TXFS__UART2_DCE_RX                         0x1C4 0x424 0x5F0 0x4 0x4</div><div class='ctx'> #define MX8MP_IOMUXC_SAI3_TXFS__UART2_DTE_TX                         0x1C4 0x424 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31                           0x1C4 0x424 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_BIT_STREAM03                0x1C4 0x424 0x4CC 0x6 0x5</div><div class='del'>-#define MX8MP_IOMUXC_SAI3_TXFS__TPSMP_HDATA01                        0x1C4 0x424 0x000 0x7 0x0</div><div class='add'>+#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_PDM_BIT_STREAM03            0x1C4 0x424 0x4CC 0x6 0x6</div><div class='ctx'> #define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK                 0x1C8 0x428 0x4E8 0x0 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI2_TX_DATA02               0x1C8 0x428 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI5_RX_DATA02               0x1C8 0x428 0x500 0x2 0x2</div><div class='hunk'>@@ -715,30 +646,26 @@</div><div class='ctx'> #define MX8MP_IOMUXC_SAI3_TXC__UART2_DCE_TX                          0x1C8 0x428 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI3_TXC__UART2_DTE_RX                          0x1C8 0x428 0x5F0 0x4 0x5</div><div class='ctx'> #define MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00                            0x1C8 0x428 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_BIT_STREAM02                 0x1C8 0x428 0x4C8 0x6 0x6</div><div class='del'>-#define MX8MP_IOMUXC_SAI3_TXC__TPSMP_HDATA02                         0x1C8 0x428 0x000 0x7 0x0</div><div class='add'>+#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_PDM_BIT_STREAM02             0x1C8 0x428 0x4C8 0x6 0x7</div><div class='ctx'> #define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00               0x1CC 0x42C 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI2_TX_DATA03               0x1CC 0x42C 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI5_RX_DATA03               0x1CC 0x42C 0x504 0x2 0x2</div><div class='ctx'> #define MX8MP_IOMUXC_SAI3_TXD__GPT1_CAPTURE2                         0x1CC 0x42C 0x598 0x3 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SPDIF_EXT_CLK                0x1CC 0x42C 0x548 0x4 0x0</div><div class='add'>+#define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SPDIF1_EXT_CLK               0x1CC 0x42C 0x548 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01                            0x1CC 0x42C 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SAI3_TXD__CCMSRCGPCMIX_BOOT_MODE05              0x1CC 0x42C 0x000 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SAI3_TXD__TPSMP_HDATA03                         0x1CC 0x42C 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK                   0x1D0 0x430 0x4E0 0x0 0x2</div><div class='ctx'> #define MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT                             0x1D0 0x430 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI5_MCLK                   0x1D0 0x430 0x4F0 0x2 0x3</div><div class='del'>-#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SPDIF_OUT                   0x1D0 0x430 0x000 0x4 0x0</div><div class='add'>+#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SPDIF1_OUT                  0x1D0 0x430 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02                           0x1D0 0x430 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SPDIF_IN                    0x1D0 0x430 0x544 0x6 0x3</div><div class='del'>-#define MX8MP_IOMUXC_SAI3_MCLK__TPSMP_HDATA04                        0x1D0 0x430 0x000 0x7 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SPDIF_TX__AUDIOMIX_SPDIF_OUT                    0x1D4 0x434 0x000 0x0 0x0</div><div class='add'>+#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SPDIF1_IN                   0x1D0 0x430 0x544 0x6 0x3</div><div class='add'>+#define MX8MP_IOMUXC_SPDIF_TX__AUDIOMIX_SPDIF1_OUT                   0x1D4 0x434 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT                              0x1D4 0x434 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL                              0x1D4 0x434 0x5C4 0x2 0x2</div><div class='ctx'> #define MX8MP_IOMUXC_SPDIF_TX__GPT1_COMPARE1                         0x1D4 0x434 0x000 0x3 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SPDIF_TX__CAN1_TX                               0x1D4 0x434 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03                            0x1D4 0x434 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SPDIF_RX__AUDIOMIX_SPDIF_IN                     0x1D8 0x438 0x544 0x0 0x4</div><div class='add'>+#define MX8MP_IOMUXC_SPDIF_RX__AUDIOMIX_SPDIF1_IN                    0x1D8 0x438 0x544 0x0 0x4</div><div class='ctx'> #define MX8MP_IOMUXC_SPDIF_RX__PWM2_OUT                              0x1D8 0x438 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA                              0x1D8 0x438 0x5C8 0x2 0x2</div><div class='ctx'> #define MX8MP_IOMUXC_SPDIF_RX__GPT1_COMPARE2                         0x1D8 0x438 0x000 0x3 0x0</div><div class='hunk'>@@ -746,7 +673,7 @@</div><div class='ctx'> #define MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04                            0x1D8 0x438 0x000 0x5 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SPDIF_EXT_CLK__GPT1_COMPARE3                    0x1DC 0x43C 0x000 0x3 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05                       0x1DC 0x43C 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_SPDIF_EXT_CLK__AUDIOMIX_SPDIF_EXT_CLK           0x1DC 0x43C 0x548 0x0 0x1</div><div class='add'>+#define MX8MP_IOMUXC_SPDIF_EXT_CLK__AUDIOMIX_SPDIF1_EXT_CLK          0x1DC 0x43C 0x548 0x0 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT                         0x1DC 0x43C 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK                        0x1E0 0x440 0x558 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX                       0x1E0 0x440 0x5F8 0x1 0x4</div><div class='hunk'>@@ -754,125 +681,105 @@</div><div class='ctx'> #define MX8MP_IOMUXC_ECSPI1_SCLK__I2C1_SCL                           0x1E0 0x440 0x5A4 0x2 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_ECSPI1_SCLK__AUDIOMIX_SAI7_RX_SYNC              0x1E0 0x440 0x538 0x3 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_ECSPI1_SCLK__GPIO5_IO06                         0x1E0 0x440 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_ECSPI1_SCLK__TPSMP_HDATA08                      0x1E0 0x440 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI                        0x1E4 0x444 0x560 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX                       0x1E4 0x444 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DTE_RX                       0x1E4 0x444 0x5F8 0x1 0x5</div><div class='ctx'> #define MX8MP_IOMUXC_ECSPI1_MOSI__I2C1_SDA                           0x1E4 0x444 0x5A8 0x2 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_ECSPI1_MOSI__AUDIOMIX_SAI7_RX_BCLK              0x1E4 0x444 0x530 0x3 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_ECSPI1_MOSI__GPIO5_IO07                         0x1E4 0x444 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_ECSPI1_MOSI__TPSMP_HDATA09                      0x1E4 0x444 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO                        0x1E8 0x448 0x55C 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS                      0x1E8 0x448 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ECSPI1_MISO__UART3_DTE_RTS                      0x1E8 0x448 0x5F4 0x1 0x2</div><div class='ctx'> #define MX8MP_IOMUXC_ECSPI1_MISO__I2C2_SCL                           0x1E8 0x448 0x5AC 0x2 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_ECSPI1_MISO__AUDIOMIX_SAI7_RX_DATA00            0x1E8 0x448 0x534 0x3 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08                         0x1E8 0x448 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_ECSPI1_MISO__TPSMP_HDATA10                      0x1E8 0x448 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ECSPI1_SS0__ECSPI1_SS0                          0x1EC 0x44C 0x564 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS                       0x1EC 0x44C 0x5F4 0x1 0x3</div><div class='ctx'> #define MX8MP_IOMUXC_ECSPI1_SS0__UART3_DTE_CTS                       0x1EC 0x44C 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ECSPI1_SS0__I2C2_SDA                            0x1EC 0x44C 0x5B0 0x2 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_ECSPI1_SS0__AUDIOMIX_SAI7_TX_SYNC               0x1EC 0x44C 0x540 0x3 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09                          0x1EC 0x44C 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_ECSPI1_SS0__TPSMP_HDATA11                       0x1EC 0x44C 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK                        0x1F0 0x450 0x568 0x0 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX                       0x1F0 0x450 0x600 0x1 0x6</div><div class='ctx'> #define MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DTE_TX                       0x1F0 0x450 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ECSPI2_SCLK__I2C3_SCL                           0x1F0 0x450 0x5B4 0x2 0x3</div><div class='ctx'> #define MX8MP_IOMUXC_ECSPI2_SCLK__AUDIOMIX_SAI7_TX_BCLK              0x1F0 0x450 0x53C 0x3 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_ECSPI2_SCLK__GPIO5_IO10                         0x1F0 0x450 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_ECSPI2_SCLK__TPSMP_HDATA12                      0x1F0 0x450 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI                        0x1F4 0x454 0x570 0x0 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX                       0x1F4 0x454 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DTE_RX                       0x1F4 0x454 0x600 0x1 0x7</div><div class='ctx'> #define MX8MP_IOMUXC_ECSPI2_MOSI__I2C3_SDA                           0x1F4 0x454 0x5B8 0x2 0x3</div><div class='ctx'> #define MX8MP_IOMUXC_ECSPI2_MOSI__AUDIOMIX_SAI7_TX_DATA00            0x1F4 0x454 0x000 0x3 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ECSPI2_MOSI__GPIO5_IO11                         0x1F4 0x454 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_ECSPI2_MOSI__TPSMP_HDATA13                      0x1F4 0x454 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12                         0x1F8 0x458 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_ECSPI2_MISO__TPSMP_HDATA14                      0x1F8 0x458 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO                        0x1F8 0x458 0x56C 0x0 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS                      0x1F8 0x458 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ECSPI2_MISO__UART4_DTE_RTS                      0x1F8 0x458 0x5FC 0x1 0x2</div><div class='ctx'> #define MX8MP_IOMUXC_ECSPI2_MISO__I2C4_SCL                           0x1F8 0x458 0x5BC 0x2 0x4</div><div class='ctx'> #define MX8MP_IOMUXC_ECSPI2_MISO__AUDIOMIX_SAI7_MCLK                 0x1F8 0x458 0x52C 0x3 0x1</div><div class='del'>-#define MX8MP_IOMUXC_ECSPI2_MISO__CCMSRCGPCMIX_CLKO1                 0x1F8 0x458 0x000 0x4 0x0</div><div class='add'>+#define MX8MP_IOMUXC_ECSPI2_MISO__CCM_CLKO1                          0x1F8 0x458 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ECSPI2_SS0__ECSPI2_SS0                          0x1FC 0x45C 0x574 0x0 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS                       0x1FC 0x45C 0x5FC 0x1 0x3</div><div class='ctx'> #define MX8MP_IOMUXC_ECSPI2_SS0__UART4_DTE_CTS                       0x1FC 0x45C 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ECSPI2_SS0__I2C4_SDA                            0x1FC 0x45C 0x5C0 0x2 0x4</div><div class='del'>-#define MX8MP_IOMUXC_ECSPI2_SS0__CCMSRCGPCMIX_CLKO2                  0x1FC 0x45C 0x000 0x4 0x0</div><div class='add'>+#define MX8MP_IOMUXC_ECSPI2_SS0__CCM_CLKO2                           0x1FC 0x45C 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13                          0x1FC 0x45C 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_ECSPI2_SS0__TPSMP_HDATA15                       0x1FC 0x45C 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL                              0x200 0x460 0x5A4 0x0 0x2</div><div class='ctx'> #define MX8MP_IOMUXC_I2C1_SCL__ENET_QOS_MDC                          0x200 0x460 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_I2C1_SCL__ECSPI1_SCLK                           0x200 0x460 0x558 0x3 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14                            0x200 0x460 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_I2C1_SCL__TPSMP_HDATA16                         0x200 0x460 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA                              0x204 0x464 0x5A8 0x0 0x2</div><div class='ctx'> #define MX8MP_IOMUXC_I2C1_SDA__ENET_QOS_MDIO                         0x204 0x464 0x590 0x1 0x2</div><div class='ctx'> #define MX8MP_IOMUXC_I2C1_SDA__ECSPI1_MOSI                           0x204 0x464 0x560 0x3 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15                            0x204 0x464 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_I2C1_SDA__TPSMP_HDATA17                         0x204 0x464 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL                              0x208 0x468 0x5AC 0x0 0x2</div><div class='ctx'> #define MX8MP_IOMUXC_I2C2_SCL__ENET_QOS_1588_EVENT1_IN               0x208 0x468 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_I2C2_SCL__USDHC3_CD_B                           0x208 0x468 0x608 0x2 0x3</div><div class='ctx'> #define MX8MP_IOMUXC_I2C2_SCL__ECSPI1_MISO                           0x208 0x468 0x55C 0x3 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_I2C2_SCL__ENET_QOS_1588_EVENT1_AUX_IN           0x208 0x468 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16                            0x208 0x468 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_I2C2_SCL__TPSMP_HDATA18                         0x208 0x468 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA                              0x20C 0x46C 0x5B0 0x0 0x2</div><div class='ctx'> #define MX8MP_IOMUXC_I2C2_SDA__ENET_QOS_1588_EVENT1_OUT              0x20C 0x46C 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_I2C2_SDA__USDHC3_WP                             0x20C 0x46C 0x634 0x2 0x3</div><div class='ctx'> #define MX8MP_IOMUXC_I2C2_SDA__ECSPI1_SS0                            0x20C 0x46C 0x564 0x3 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17                            0x20C 0x46C 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_I2C2_SDA__TPSMP_HDATA19                         0x20C 0x46C 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL                              0x210 0x470 0x5B4 0x0 0x4</div><div class='ctx'> #define MX8MP_IOMUXC_I2C3_SCL__PWM4_OUT                              0x210 0x470 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_I2C3_SCL__GPT2_CLK                              0x210 0x470 0x000 0x2 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_I2C3_SCL__ECSPI2_SCLK                           0x210 0x470 0x568 0x3 0x2</div><div class='ctx'> #define MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18                            0x210 0x470 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_I2C3_SCL__TPSMP_HDATA20                         0x210 0x470 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA                              0x214 0x474 0x5B8 0x0 0x4</div><div class='ctx'> #define MX8MP_IOMUXC_I2C3_SDA__PWM3_OUT                              0x214 0x474 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_I2C3_SDA__GPT3_CLK                              0x214 0x474 0x000 0x2 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_I2C3_SDA__ECSPI2_MOSI                           0x214 0x474 0x570 0x3 0x2</div><div class='ctx'> #define MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19                            0x214 0x474 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_I2C3_SDA__TPSMP_HDATA21                         0x214 0x474 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL                              0x218 0x478 0x5BC 0x0 0x5</div><div class='ctx'> #define MX8MP_IOMUXC_I2C4_SCL__PWM2_OUT                              0x218 0x478 0x000 0x1 0x0</div><div class='del'>-#define MX8MP_IOMUXC_I2C4_SCL__HSIOMIX_PCIE_CLKREQ_B                 0x218 0x478 0x5A0 0x2 0x0</div><div class='add'>+#define MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B                         0x218 0x478 0x5A0 0x2 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_I2C4_SCL__ECSPI2_MISO                           0x218 0x478 0x56C 0x3 0x2</div><div class='ctx'> #define MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20                            0x218 0x478 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_I2C4_SCL__TPSMP_HDATA22                         0x218 0x478 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA                              0x21C 0x47C 0x5C0 0x0 0x5</div><div class='ctx'> #define MX8MP_IOMUXC_I2C4_SDA__PWM1_OUT                              0x21C 0x47C 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_I2C4_SDA__ECSPI2_SS0                            0x21C 0x47C 0x574 0x3 0x2</div><div class='ctx'> #define MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21                            0x21C 0x47C 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_I2C4_SDA__TPSMP_HDATA23                         0x21C 0x47C 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX                         0x220 0x480 0x5E8 0x0 0x4</div><div class='ctx'> #define MX8MP_IOMUXC_UART1_RXD__UART1_DTE_TX                         0x220 0x480 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK                          0x220 0x480 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_UART1_RXD__GPIO5_IO22                           0x220 0x480 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_UART1_RXD__TPSMP_HDATA24                        0x220 0x480 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX                         0x224 0x484 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_UART1_TXD__UART1_DTE_RX                         0x224 0x484 0x5E8 0x0 0x5</div><div class='ctx'> #define MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI                          0x224 0x484 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23                           0x224 0x484 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_UART1_TXD__TPSMP_HDATA25                        0x224 0x484 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX                         0x228 0x488 0x5F0 0x0 0x6</div><div class='ctx'> #define MX8MP_IOMUXC_UART2_RXD__UART2_DTE_TX                         0x228 0x488 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO                          0x228 0x488 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_UART2_RXD__GPT1_COMPARE3                        0x228 0x488 0x000 0x3 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_UART2_RXD__GPIO5_IO24                           0x228 0x488 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_UART2_RXD__TPSMP_HDATA26                        0x228 0x488 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX                         0x22C 0x48C 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_UART2_TXD__UART2_DTE_RX                         0x22C 0x48C 0x5F0 0x0 0x7</div><div class='ctx'> #define MX8MP_IOMUXC_UART2_TXD__ECSPI3_SS0                           0x22C 0x48C 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_UART2_TXD__GPT1_COMPARE2                        0x22C 0x48C 0x000 0x3 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25                           0x22C 0x48C 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_UART2_TXD__TPSMP_HDATA27                        0x22C 0x48C 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX                         0x230 0x490 0x5F8 0x0 0x6</div><div class='ctx'> #define MX8MP_IOMUXC_UART3_RXD__UART3_DTE_TX                         0x230 0x490 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS                        0x230 0x490 0x000 0x1 0x0</div><div class='hunk'>@@ -881,7 +788,6 @@</div><div class='ctx'> #define MX8MP_IOMUXC_UART3_RXD__GPT1_CAPTURE2                        0x230 0x490 0x598 0x3 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_UART3_RXD__CAN2_TX                              0x230 0x490 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26                           0x230 0x490 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_UART3_RXD__TPSMP_HDATA28                        0x230 0x490 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX                         0x234 0x494 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_UART3_TXD__UART3_DTE_RX                         0x234 0x494 0x5F8 0x0 0x7</div><div class='ctx'> #define MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS                        0x234 0x494 0x5E4 0x1 0x5</div><div class='hunk'>@@ -890,16 +796,14 @@</div><div class='ctx'> #define MX8MP_IOMUXC_UART3_TXD__GPT1_CLK                             0x234 0x494 0x59C 0x3 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_UART3_TXD__CAN2_RX                              0x234 0x494 0x550 0x4 0x2</div><div class='ctx'> #define MX8MP_IOMUXC_UART3_TXD__GPIO5_IO27                           0x234 0x494 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_UART3_TXD__TPSMP_HDATA29                        0x234 0x494 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX                         0x238 0x498 0x600 0x0 0x8</div><div class='ctx'> #define MX8MP_IOMUXC_UART4_RXD__UART4_DTE_TX                         0x238 0x498 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_UART4_RXD__UART2_DCE_CTS                        0x238 0x498 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_UART4_RXD__UART2_DTE_RTS                        0x238 0x498 0x5EC 0x1 0x4</div><div class='del'>-#define MX8MP_IOMUXC_UART4_RXD__HSIOMIX_PCIE_CLKREQ_B                0x238 0x498 0x5A0 0x2 0x1</div><div class='add'>+#define MX8MP_IOMUXC_UART4_RXD__PCIE_CLKREQ_B                        0x238 0x498 0x5A0 0x2 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_UART4_RXD__GPT1_COMPARE1                        0x238 0x498 0x000 0x3 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_UART4_RXD__I2C6_SCL                             0x238 0x498 0x5CC 0x4 0x2</div><div class='ctx'> #define MX8MP_IOMUXC_UART4_RXD__GPIO5_IO28                           0x238 0x498 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_UART4_RXD__TPSMP_HDATA30                        0x238 0x498 0x000 0x7 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX                         0x23C 0x49C 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_UART4_TXD__UART4_DTE_RX                         0x23C 0x49C 0x600 0x0 0x9</div><div class='ctx'> #define MX8MP_IOMUXC_UART4_TXD__UART2_DCE_RTS                        0x23C 0x49C 0x5EC 0x1 0x5</div><div class='hunk'>@@ -907,23 +811,20 @@</div><div class='ctx'> #define MX8MP_IOMUXC_UART4_TXD__GPT1_CAPTURE1                        0x23C 0x49C 0x594 0x3 0x1</div><div class='ctx'> #define MX8MP_IOMUXC_UART4_TXD__I2C6_SDA                             0x23C 0x49C 0x5D0 0x4 0x2</div><div class='ctx'> #define MX8MP_IOMUXC_UART4_TXD__GPIO5_IO29                           0x23C 0x49C 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_UART4_TXD__TPSMP_HDATA31                        0x23C 0x49C 0x000 0x7 0x0</div><div class='del'>-#define MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_EARC_SCL                  0x240 0x4A0 0x000 0x0 0x0</div><div class='add'>+#define MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL                  0x240 0x4A0 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL                          0x240 0x4A0 0x5C4 0x3 0x3</div><div class='ctx'> #define MX8MP_IOMUXC_HDMI_DDC_SCL__CAN1_TX                           0x240 0x4A0 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26                        0x240 0x4A0 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_HDMI_DDC_SCL__AUDIOMIX_test_out00               0x240 0x4A0 0x000 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_EARC_SDA                  0x244 0x4A4 0x000 0x0 0x0</div><div class='add'>+#define MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA                  0x244 0x4A4 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA                          0x244 0x4A4 0x5C8 0x3 0x3</div><div class='ctx'> #define MX8MP_IOMUXC_HDMI_DDC_SDA__CAN1_RX                           0x244 0x4A4 0x54C 0x4 0x3</div><div class='ctx'> #define MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27                        0x244 0x4A4 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_HDMI_DDC_SDA__AUDIOMIX_test_out01               0x244 0x4A4 0x000 0x6 0x0</div><div class='del'>-#define MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_EARC_CEC                      0x248 0x4A8 0x000 0x0 0x0</div><div class='add'>+#define MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC                      0x248 0x4A8 0x000 0x0 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_HDMI_CEC__I2C6_SCL                              0x248 0x4A8 0x5CC 0x3 0x3</div><div class='ctx'> #define MX8MP_IOMUXC_HDMI_CEC__CAN2_TX                               0x248 0x4A8 0x000 0x4 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_HDMI_CEC__GPIO3_IO28                            0x248 0x4A8 0x000 0x5 0x0</div><div class='del'>-#define MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_EARC_DC_HPD                   0x24C 0x4AC 0x000 0x0 0x0</div><div class='del'>-#define MX8MP_IOMUXC_HDMI_HPD__AUDIOMIX_EARC_HDMI_HPD_O              0x24C 0x4AC 0x000 0x1 0x0</div><div class='add'>+#define MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD                      0x24C 0x4AC 0x000 0x0 0x0</div><div class='add'>+#define MX8MP_IOMUXC_HDMI_HPD__AUDIOMIX_HDMI_HPD_O                   0x24C 0x4AC 0x000 0x1 0x0</div><div class='ctx'> #define MX8MP_IOMUXC_HDMI_HPD__I2C6_SDA                              0x24C 0x4AC 0x5D0 0x3 0x3</div><div class='ctx'> #define MX8MP_IOMUXC_HDMI_HPD__CAN2_RX                               0x24C 0x4AC 0x550 0x4 0x3</div><div class='ctx'> #define MX8MP_IOMUXC_HDMI_HPD__GPIO3_IO29                            0x24C 0x4AC 0x000 0x5 0x0</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-prt8ml.dts b/arch/arm64/boot/dts/freescale/imx8mp-prt8ml.dts<br/>new file mode 100644<br/>index 000000000000..30616218017b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-prt8ml.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-prt8ml.dts</a></div><div class='hunk'>@@ -0,0 +1,504 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2020 Protonic Holland</div><div class='add'>+ * Copyright 2019 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mp.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Protonic PRT8ML";</div><div class='add'>+	compatible = "prt,prt8ml", "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart4;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie_refclk: pcie0-refclk {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;100000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie_refclk_oe: pcie0-refclk-oe {</div><div class='add'>+		compatible = "gpio-gate-clock";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pcie_refclk&gt;;</div><div class='add'>+		clocks = &lt;&amp;pcie_refclk&gt;;</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;gpio5 23 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;fan53555&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;fan53555&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;fan53555&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;fan53555&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;a53_opp_table {</div><div class='add'>+	opp-1200000000 {</div><div class='add'>+		opp-microvolt = &lt;900000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	opp-1600000000 {</div><div class='add'>+		opp-microvolt = &lt;980000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Power supply insuffient for 1.8 GHz */</div><div class='add'>+	/delete-node/ opp-1800000000;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi2&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 13 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+	/* Disable DMA to meet performance requirements */</div><div class='add'>+	/delete-property/ dmas;</div><div class='add'>+	/delete-property/ dma-names;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	switch@0 {</div><div class='add'>+		compatible = "nxp,sja1105q";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio_exp_1 4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		spi-cpha;</div><div class='add'>+		spi-max-frequency = &lt;4000000&gt;;</div><div class='add'>+		spi-rx-delay-us = &lt;1&gt;;</div><div class='add'>+		spi-tx-delay-us = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@3 {</div><div class='add'>+				reg = &lt;3&gt;;</div><div class='add'>+				label = "rj45";</div><div class='add'>+				phy-handle = &lt;&amp;rj45_phy&gt;;</div><div class='add'>+				phy-mode = "rgmii-id";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@4 {</div><div class='add'>+				reg = &lt;4&gt;;</div><div class='add'>+				ethernet = &lt;&amp;fec&gt;;</div><div class='add'>+				label = "cpu";</div><div class='add'>+				phy-mode = "rgmii-id";</div><div class='add'>+				rx-internal-delay-ps = &lt;2000&gt;;</div><div class='add'>+				tx-internal-delay-ps = &lt;2000&gt;;</div><div class='add'>+</div><div class='add'>+				/* Unreliable at 1000Mbps, limit RGMII to 100Mbps */</div><div class='add'>+				fixed-link {</div><div class='add'>+					full-duplex;</div><div class='add'>+					speed = &lt;100&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec&gt;;</div><div class='add'>+	phy-mode = "rgmii"; /* switch inserts delay */</div><div class='add'>+	rx-internal-delay-ps = &lt;0&gt;;</div><div class='add'>+	tx-internal-delay-ps = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	fixed-link {</div><div class='add'>+		full-duplex;</div><div class='add'>+		speed = &lt;100&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		rj45_phy: ethernet-phy@2 {</div><div class='add'>+			reg = &lt;2&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio_exp_1 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;10000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;80000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ak5558: codec@10 {</div><div class='add'>+		compatible = "asahi-kasei,ak5558";</div><div class='add'>+		reg = &lt;0x10&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio_exp_1 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio_exp_1: gpio@25 {</div><div class='add'>+		compatible = "nxp,pca9571";</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	tps65987ddh_0: usb-pd@20 {</div><div class='add'>+		compatible = "ti,tps6598x";</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_tps65987ddh_0&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;gpio1 12 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio_exp_2: gpio@25 {</div><div class='add'>+		compatible = "nxp,pca9571";</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		c0-hreset-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;7 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			line-name = "c0-hreset";</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		c1-hreset-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			line-name = "c1-hreset";</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fan53555: regulator@60 {</div><div class='add'>+		compatible = "fcs,fan53555";</div><div class='add'>+		reg = &lt;0x60&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_fan53555&gt;;</div><div class='add'>+		regulator-name = "fan53555";</div><div class='add'>+		regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;980000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		fcs,suspend-voltage-selector = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ak4458: codec@11 {</div><div class='add'>+		compatible = "asahi-kasei,ak4458";</div><div class='add'>+		reg = &lt;0x11&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio_exp_2 5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	tps65987ddh_1: usb-pd@20 {</div><div class='add'>+		compatible = "ti,tps6598x";</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_tps65987ddh_1&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;gpio1 15 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;snvs_pwrkey {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_0 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_1 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_USDHC2&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;100000000&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	no-1-8-v;</div><div class='add'>+	sd-uhs-sdr12;</div><div class='add'>+	sd-uhs-sdr25;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_USDHC3_ROOT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	no-sdio;</div><div class='add'>+	no-sd;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_ecspi2: ecspi2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK		0x154</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI		0x154</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO		0x154</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13		0x154</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fan53555: fan53555grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05		0x114</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec: fecgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x91</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x91</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x91</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x91</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x1f</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x1f</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x1f</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x1f</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x1f</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan1: flexcan1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SPDIF_RX__CAN1_RX		0x154</div><div class='add'>+			MX8MP_IOMUXC_SPDIF_TX__CAN1_TX		0x154</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan2: flexcan2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART3_TXD__CAN2_RX		0x154</div><div class='add'>+			MX8MP_IOMUXC_UART3_RXD__CAN2_TX		0x154</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_SCLK__I2C1_SCL	0x400000c3</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_MOSI__I2C1_SDA	0x400000c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400000c3</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA		0x400000c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400000c3</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400000c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie_refclk: pcierefclkgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23	0xc6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_tps65987ddh_0: tps65987ddh-0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_tps65987ddh_1: tps65987ddh-1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart4: uart4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX		0x040</div><div class='add'>+			MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX		0x040</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x190</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x194</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x196</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2-gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12		0x0d4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x190</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x190</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x194</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x196</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x196</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B		0x166</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-basic.dts b/arch/arm64/boot/dts/freescale/imx8mp-skov-basic.dts<br/>new file mode 100644<br/>index 000000000000..5a2629f3567c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-skov-basic.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-skov-basic.dts</a></div><div class='hunk'>@@ -0,0 +1,10 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mp-skov-reva.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "SKOV IMX8MP CPU basic/fallback";</div><div class='add'>+	compatible = "skov,imx8mp-skov-basic", "fsl,imx8mp";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi<br/>new file mode 100644<br/>index 000000000000..020f20c8ce66<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi</a></div><div class='hunk'>@@ -0,0 +1,798 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+</div><div class='add'>+#include "imx8mp.dtsi"</div><div class='add'>+#include "imx8mp-nominal.dtsi"</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		/* some of this aliases like backlight0, ethernetX and switch0</div><div class='add'>+		 * are needed for the bootloader.</div><div class='add'>+		 */</div><div class='add'>+		backlight0 = &amp;backlight;</div><div class='add'>+		ethernet0 = &amp;eqos;</div><div class='add'>+		ethernet1 = &amp;lan1;</div><div class='add'>+		ethernet2 = &amp;lan2;</div><div class='add'>+		rtc0 = &amp;i2c_rtc;</div><div class='add'>+		rtc1 = &amp;snvs_rtc;</div><div class='add'>+		switch0 = &amp;switch;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Backlight is present only on some of boards, so it is disabled by</div><div class='add'>+	 * default.</div><div class='add'>+	 */</div><div class='add'>+	backlight: backlight {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_backlight&gt;;</div><div class='add'>+		pwms = &lt;&amp;pwm1 0 20000 0&gt;;</div><div class='add'>+		power-supply = &lt;&amp;reg_24v&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;gpio4 24 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		brightness-levels = &lt;0 255&gt;;</div><div class='add'>+		num-interpolated-steps = &lt;17&gt;;</div><div class='add'>+		default-brightness-level = &lt;8&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_led&gt;;</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			label = "D1";</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio1 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			default-state = "on";</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			label = "D2";</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio1 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-2 {</div><div class='add'>+			label = "D3";</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio1 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "on";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_1v2: regulator-1v2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		vin-supply = &lt;&amp;reg_5v_p&gt;;</div><div class='add'>+		regulator-name = "1V2";</div><div class='add'>+		regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_2v5: regulator-2v5 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		vin-supply = &lt;&amp;reg_5v_s&gt;;</div><div class='add'>+		regulator-name = "2V5";</div><div class='add'>+		regulator-min-microvolt = &lt;2500000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;2500000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3v3: regulator-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		vin-supply = &lt;&amp;reg_5v_s&gt;;</div><div class='add'>+		regulator-name = "3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * This regulator will provide power as long as possible even if</div><div class='add'>+	 * undervoltage is detected.</div><div class='add'>+	 */</div><div class='add'>+	reg_5v_p: regulator-5v-p {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "5V_P";</div><div class='add'>+		vin-supply = &lt;&amp;reg_24v&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * This regulator will be automatically shutdown if undervoltage is</div><div class='add'>+	 * detected.</div><div class='add'>+	 */</div><div class='add'>+	reg_5v_s: regulator-5v-s {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "5V_S";</div><div class='add'>+		vin-supply = &lt;&amp;reg_24v&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_24v: regulator-24v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "24V";</div><div class='add'>+		regulator-min-microvolt = &lt;24000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;24000000&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg24v&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;gpio4 23 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		system-critical-regulator;</div><div class='add'>+		regulator-uv-less-critical-window-ms = &lt;50&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_can2rs: regulator-can2rs {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "CAN2RS";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_can2rs&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio4 22 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_canrs: regulator-canrs {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "CANRS";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_canrs&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio4 21 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_tft_vcom: regulator-tft-vcom {</div><div class='add'>+		compatible = "pwm-regulator";</div><div class='add'>+		pwms = &lt;&amp;pwm4 0 20000 0&gt;;</div><div class='add'>+		regulator-name = "VCOM";</div><div class='add'>+		vin-supply = &lt;&amp;reg_5v_s&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3600000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3600000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		voltage-table = &lt;3600000 26&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vsd_3v3: regulator-vsd-3v3 {</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_vsd_3v3&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;reg_vdd_3v3&gt;;</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VSD_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio2 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Board is passively cooled and heatsink is specced for continuous operation</div><div class='add'>+ * at 1.2 GHz only. Short bouts of 1.6 GHz are ok, but these should be done</div><div class='add'>+ * intentionally, not as part of suspend/resume cycles.</div><div class='add'>+ */</div><div class='add'>+&amp;{/opp-table/opp-1600000000} {</div><div class='add'>+	/delete-property/ opp-suspend;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;{/opp-table/opp-1800000000} {</div><div class='add'>+	/delete-property/ opp-suspend;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_vdd_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_vdd_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_vdd_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_vdd_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi2&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 13 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	adc: adc@0 {</div><div class='add'>+		compatible = "microchip,mcp3002";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		vref-supply = &lt;&amp;reg_vdd_3v3&gt;;</div><div class='add'>+		spi-max-frequency = &lt;1000000&gt;;</div><div class='add'>+		#io-channel-cells = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eqos {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_eqos&gt;;</div><div class='add'>+	phy-mode = "rgmii-rxid";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	fixed-link {</div><div class='add'>+		speed = &lt;1000&gt;;</div><div class='add'>+		full-duplex;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan1&gt;;</div><div class='add'>+	xceiver-supply = &lt;&amp;reg_canrs&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan2&gt;;</div><div class='add'>+	xceiver-supply = &lt;&amp;reg_can2rs&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c1_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pmic@25 {</div><div class='add'>+		compatible = "nxp,pca9450c";</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;gpio1 3 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			reg_vdd_soc: BUCK1 {</div><div class='add'>+				regulator-name = "VDD_SOC";</div><div class='add'>+				regulator-min-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;850000&gt;;</div><div class='add'>+				vin-supply = &lt;&amp;reg_5v_p&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vdd_arm: BUCK2 {</div><div class='add'>+				regulator-name = "VDD_ARM";</div><div class='add'>+				regulator-min-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+				vin-supply = &lt;&amp;reg_5v_p&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+				nxp,dvs-run-voltage = &lt;850000&gt;;</div><div class='add'>+				nxp,dvs-standby-voltage = &lt;850000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vdd_3v3: BUCK4 {</div><div class='add'>+				regulator-name = "VDD_3V3";</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				vin-supply = &lt;&amp;reg_5v_p&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vdd_1v8: BUCK5 {</div><div class='add'>+				regulator-name = "VDD_1V8";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				vin-supply = &lt;&amp;reg_5v_p&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_nvcc_dram_1v1: BUCK6 {</div><div class='add'>+				regulator-name = "NVCC_DRAM_1V1";</div><div class='add'>+				regulator-min-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+				vin-supply = &lt;&amp;reg_5v_p&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_nvcc_snvs_1v8: LDO1 {</div><div class='add'>+				regulator-name = "NVCC_SNVS_1V8";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				vin-supply = &lt;&amp;reg_5v_p&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vdda_1v8: LDO3 {</div><div class='add'>+				regulator-name = "VDDA_1V8";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				vin-supply = &lt;&amp;reg_5v_p&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_nvcc_sd2: LDO5 {</div><div class='add'>+				regulator-name = "NVCC_SD2";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				vin-supply = &lt;&amp;reg_5v_p&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c2_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c3_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	i2c_rtc: rtc@51 {</div><div class='add'>+		compatible = "nxp,pcf85063tp";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_rtc&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;gpio4 31 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		quartz-load-femtofarads = &lt;12500&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	clock-frequency = &lt;380000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c4&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c4_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	switch: switch@5f {</div><div class='add'>+		compatible = "microchip,ksz9893";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_switch&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio5 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		reg = &lt;0x5f&gt;;</div><div class='add'>+</div><div class='add'>+		ethernet-ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			lan1: port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				phy-mode = "internal";</div><div class='add'>+				label = "lan1";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lan2: port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				phy-mode = "internal";</div><div class='add'>+				label = "lan2";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@2 {</div><div class='add'>+				reg = &lt;2&gt;;</div><div class='add'>+				label = "cpu";</div><div class='add'>+				ethernet = &lt;&amp;eqos&gt;;</div><div class='add'>+				phy-mode = "rgmii";</div><div class='add'>+				/* 2ns RX delay is implemented on PCB */</div><div class='add'>+				tx-internal-delay-ps = &lt;2000&gt;;</div><div class='add'>+				rx-internal-delay-ps = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				fixed-link {</div><div class='add'>+					speed = &lt;1000&gt;;</div><div class='add'>+					full-duplex;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm4&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+	/*</div><div class='add'>+	 * While there is no CTS line, the property "uart-has-rtscts" is still</div><div class='add'>+	 * the right thing to do to enable the UART to do RS485. In RS485-Mode</div><div class='add'>+	 * CTS isn't used anyhow and there is no dedicated property</div><div class='add'>+	 * "uart-has-rts-but-no-cts".</div><div class='add'>+	 */</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	/* console */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy0 {</div><div class='add'>+	vbus-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy1 {</div><div class='add'>+	vbus-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_0 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_1 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SD Card */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_vsd_3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_nvcc_sd2&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	wp-gpios = &lt;&amp;gpio2 20 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* eMMC */</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_USDHC3&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_vdd_3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_vdd_1v8&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	no-sd;</div><div class='add'>+	no-sdio;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_backlight: backlightgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24			0x0100</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_can2rs: can2rsgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22			0x154</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_canrs: canrsgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21			0x154</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi2: ecspi2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK			0x44</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI			0x44</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO			0x44</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13			0x40</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_eqos: eqosgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL			0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL			0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan1: flexcan1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SPDIF_RX__CAN1_RX				0x154</div><div class='add'>+			MX8MP_IOMUXC_SPDIF_TX__CAN1_TX				0x154</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan2: flexcan2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX				0x154</div><div class='add'>+			MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX				0x154</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio_led: gpioledgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05			0x19</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06			0x19</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07			0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL				0x400001c2</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA				0x400001c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1_gpio: i2c1gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14			0x400001c2</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15			0x400001c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL				0x400001c2</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA				0x400001c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2_gpio: i2c2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16			0x400001c2</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17			0x400001c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL				0x400001c2</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA				0x400001c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3_gpio: i2c3gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18			0x400001c2</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19			0x400001c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4: i2c4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL				0x400001c3</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA				0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4_gpio: i2c4gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20			0x400001c3</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21			0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: pmicirqgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03			0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm1: pwm1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT			0x116</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm4: pwm4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT			0x116</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg24v: reg24vgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23			0x154</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_vsd_3v3: regvsd3v3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x40</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_rtc: rtcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31			0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_switch: switchgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00			0x41</div><div class='add'>+			MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01			0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_touchscreen: touchscreengrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* external 10 k pull up */</div><div class='add'>+			/* CTP_INT */</div><div class='add'>+			MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28			0x41</div><div class='add'>+			/* CTP_RST */</div><div class='add'>+			MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29			0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX			0x140</div><div class='add'>+			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX			0x140</div><div class='add'>+			MX8MP_IOMUXC_UART3_RXD__UART1_DTE_RTS			0x140</div><div class='add'>+			/* CTS pin is not connected, but needed as workaround */</div><div class='add'>+			MX8MP_IOMUXC_UART3_TXD__UART1_DTE_CTS			0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX			0x14f</div><div class='add'>+			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX			0x14f</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK			0x190</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD			0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0			0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1			0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2			0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3			0x1d0</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT			0xc0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK			0x194</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD			0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0			0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1			0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2			0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3			0x1d4</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT			0xc0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK			0x196</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD			0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0			0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1			0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2			0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3			0x1d6</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT			0xc0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12			0x1c4</div><div class='add'>+			MX8MP_IOMUXC_SD2_WP__GPIO2_IO20				0x1c4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK			0x190</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD			0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0			0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1			0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2			0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3			0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4			0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5			0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6			0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7			0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE			0x190</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK			0x194</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD			0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0			0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1			0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2			0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3			0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4			0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5			0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6			0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7			0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE			0x194</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK			0x196</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD			0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0			0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1			0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2			0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3			0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4			0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5			0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6			0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7			0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE			0x196</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B			0xc6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-hdmi.dts b/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-hdmi.dts<br/>new file mode 100644<br/>index 000000000000..32a429437cbd<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-hdmi.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-skov-revb-hdmi.dts</a></div><div class='hunk'>@@ -0,0 +1,61 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mp-skov-reva.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "SKOV IMX8MP CPU revB - HDMI";</div><div class='add'>+	compatible = "skov,imx8mp-skov-revb-hdmi", "fsl,imx8mp";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_pvi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hdmi&gt;;</div><div class='add'>+	ddc-i2c-bus = &lt;&amp;i2c5&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c5 {</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c5&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c5_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_hdmi: hdmigrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD			0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c5: i2c5grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL			0x400001c2</div><div class='add'>+			MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA			0x400001c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c5_gpio: i2c5gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26			0x400001c2</div><div class='add'>+			MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27			0x400001c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-lt6.dts b/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-lt6.dts<br/>new file mode 100644<br/>index 000000000000..e602c1c96143<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-lt6.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-skov-revb-lt6.dts</a></div><div class='hunk'>@@ -0,0 +1,161 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mp-skov-reva.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "SKOV IMX8MP CPU revB - LT6";</div><div class='add'>+	compatible = "skov,imx8mp-skov-revb-lt6", "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	lvds-decoder {</div><div class='add'>+		compatible = "ti,sn65lvds822", "lvds-decoder";</div><div class='add'>+		power-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				in_lvds1: endpoint {</div><div class='add'>+					data-mapping = "vesa-24";</div><div class='add'>+					remote-endpoint = &lt;&amp;ldb_lvds_ch1&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				lvds_decoder_out: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;panel_in&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	panel {</div><div class='add'>+		compatible = "logictechno,lttd800480070-l6wh-rt";</div><div class='add'>+		backlight = &lt;&amp;backlight&gt;;</div><div class='add'>+		power-supply = &lt;&amp;reg_tft_vcom&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			panel_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;lvds_decoder_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	touchscreen {</div><div class='add'>+		compatible = "resistive-adc-touch";</div><div class='add'>+		io-channels = &lt;&amp;adc_ts 1&gt;, &lt;&amp;adc_ts 3&gt;, &lt;&amp;adc_ts 4&gt;, &lt;&amp;adc_ts 5&gt;;</div><div class='add'>+		io-channel-names = "y", "z1", "z2", "x";</div><div class='add'>+		touchscreen-min-pressure = &lt;65000&gt;;</div><div class='add'>+		touchscreen-inverted-y;</div><div class='add'>+		touchscreen-swapped-x-y;</div><div class='add'>+		touchscreen-x-plate-ohms = &lt;300&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_tft_vcom {</div><div class='add'>+	regulator-min-microvolt = &lt;3600000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;3600000&gt;;</div><div class='add'>+	voltage-table = &lt;3600000 26&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm4 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;backlight {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi1&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	adc_ts: adc@0 {</div><div class='add'>+		compatible = "ti,tsc2046e-adc";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_touch&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		spi-max-frequency = &lt;1000000&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;gpio4 25 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		#io-channel-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		channel@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			settling-time-us = &lt;700&gt;;</div><div class='add'>+			oversampling-ratio = &lt;5&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		channel@3 {</div><div class='add'>+			reg = &lt;3&gt;;</div><div class='add'>+			settling-time-us = &lt;700&gt;;</div><div class='add'>+			oversampling-ratio = &lt;5&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		channel@4 {</div><div class='add'>+			reg = &lt;4&gt;;</div><div class='add'>+			settling-time-us = &lt;700&gt;;</div><div class='add'>+			oversampling-ratio = &lt;5&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		channel@5 {</div><div class='add'>+			reg = &lt;5&gt;;</div><div class='add'>+			settling-time-us = &lt;700&gt;;</div><div class='add'>+			oversampling-ratio = &lt;5&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lvds_bridge {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_MEDIA_LDB&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MP_VIDEO_PLL1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_VIDEO_PLL1_OUT&gt;;</div><div class='add'>+	/* IMX8MP_VIDEO_PLL1 = IMX8MP_CLK_MEDIA_DISP2_PIX * 2 * 7 */</div><div class='add'>+	assigned-clock-rates = &lt;0&gt;, &lt;462000000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@2 {</div><div class='add'>+			ldb_lvds_ch1: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;in_lvds1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_ecspi1: ecspi1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK			0x44</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI			0x44</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO			0x44</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09			0x40</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_touch: touchgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* external pull up */</div><div class='add'>+			MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25			0x40</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts b/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts<br/>new file mode 100644<br/>index 000000000000..45c9a6d55bc9<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts</a></div><div class='hunk'>@@ -0,0 +1,81 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mp-skov-reva.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "SKOV IMX8MP CPU revB - MI1010AIT-1CP1";</div><div class='add'>+	compatible = "skov,imx8mp-skov-revb-mi1010ait-1cp1", "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	panel {</div><div class='add'>+		compatible = "multi-inno,mi1010ait-1cp";</div><div class='add'>+		backlight = &lt;&amp;backlight&gt;;</div><div class='add'>+		power-supply = &lt;&amp;reg_tft_vcom&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			in_lvds0: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;ldb_lvds_ch0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;backlight {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	touchscreen@38 {</div><div class='add'>+		compatible = "edt,edt-ft5406";</div><div class='add'>+		reg = &lt;0x38&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_touchscreen&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;gpio4 28 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio4 29 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		touchscreen-size-x = &lt;1280&gt;;</div><div class='add'>+		touchscreen-size-y = &lt;800&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_vdd_3v3&gt;;</div><div class='add'>+		iovcc-supply = &lt;&amp;reg_vdd_3v3&gt;;</div><div class='add'>+		wakeup-source;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lvds_bridge {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_MEDIA_LDB&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MP_VIDEO_PLL1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_VIDEO_PLL1_OUT&gt;;</div><div class='add'>+	/* IMX8MP_VIDEO_PLL1 = IMX8MP_CLK_MEDIA_DISP2_PIX * 2 * 7 */</div><div class='add'>+	assigned-clock-rates = &lt;0&gt;, &lt;980000000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@1 {</div><div class='add'>+			ldb_lvds_ch0: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;in_lvds0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm4 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_tft_vcom {</div><div class='add'>+	regulator-min-microvolt = &lt;3160000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;3160000&gt;;</div><div class='add'>+	voltage-table = &lt;3160000 73&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-revc-bd500.dts b/arch/arm64/boot/dts/freescale/imx8mp-skov-revc-bd500.dts<br/>new file mode 100644<br/>index 000000000000..b816c6cd3bca<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-skov-revc-bd500.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-skov-revc-bd500.dts</a></div><div class='hunk'>@@ -0,0 +1,91 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mp-skov-reva.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "SKOV IMX8MP CPU revC - bd500";</div><div class='add'>+	compatible = "skov,imx8mp-skov-revc-bd500", "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		led_system_red: led-3 {</div><div class='add'>+			label = "bd500:system:red";</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			/* Inverted compared to others due to NMOS inverter */</div><div class='add'>+			gpios = &lt;&amp;gpioexp 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led_system_green: led-4 {</div><div class='add'>+			label = "bd500:system:green";</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpioexp 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "on";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led_lan1_red: led-5 {</div><div class='add'>+			label = "bd500:lan1:act";</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			linux,default-trigger = "netdev";</div><div class='add'>+			gpios = &lt;&amp;gpioexp 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led_lan1_green: led-6 {</div><div class='add'>+			label = "bd500:lan1:link";</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			linux,default-trigger = "netdev";</div><div class='add'>+			gpios = &lt;&amp;gpioexp 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led_lan2_red: led-7 {</div><div class='add'>+			label = "bd500:lan2:act";</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			linux,default-trigger = "netdev";</div><div class='add'>+			gpios = &lt;&amp;gpioexp 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led_lan2_green: led-8 {</div><div class='add'>+			label = "bd500:lan2:link";</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			linux,default-trigger = "netdev";</div><div class='add'>+			gpios = &lt;&amp;gpioexp 7 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		button-1 {</div><div class='add'>+			label = "S1";</div><div class='add'>+			linux,code = &lt;KEY_CONFIG&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpioexp 5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	gpioexp: gpio@20 {</div><div class='add'>+		compatible = "nxp,pca6408";</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_exp&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;gpio4 28 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio4 29 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_vdd_3v3&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_gpio_exp: gpioexpgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28	0x0</div><div class='add'>+			MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29	0x0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-revc-hdmi.dts b/arch/arm64/boot/dts/freescale/imx8mp-skov-revc-hdmi.dts<br/>new file mode 100644<br/>index 000000000000..c263e8fd0484<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-skov-revc-hdmi.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-skov-revc-hdmi.dts</a></div><div class='hunk'>@@ -0,0 +1,8 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+</div><div class='add'>+#include "imx8mp-skov-revb-hdmi.dts"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "SKOV IMX8MP CPU revC - HDMI";</div><div class='add'>+	compatible = "skov,imx8mp-skov-revc-hdmi", "fsl,imx8mp";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-revc-jutouch-jt101tm023.dts b/arch/arm64/boot/dts/freescale/imx8mp-skov-revc-jutouch-jt101tm023.dts<br/>new file mode 100644<br/>index 000000000000..3e320d6dea3a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-skov-revc-jutouch-jt101tm023.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-skov-revc-jutouch-jt101tm023.dts</a></div><div class='hunk'>@@ -0,0 +1,79 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mp-skov-reva.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "SKOV IMX8MP CPU revC - JuTouch JT101TM023";</div><div class='add'>+	compatible = "skov,imx8mp-skov-revc-jutouch-jt101tm023", "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	panel {</div><div class='add'>+		compatible = "jutouch,jt101tm023";</div><div class='add'>+		backlight = &lt;&amp;backlight&gt;;</div><div class='add'>+		power-supply = &lt;&amp;reg_tft_vcom&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			in_lvds0: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;ldb_lvds_ch0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;backlight {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	touchscreen@2a {</div><div class='add'>+		compatible = "eeti,exc81w32", "eeti,exc80h84";</div><div class='add'>+		reg = &lt;0x2a&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_touchscreen&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;gpio4 28 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio4 29 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		touchscreen-size-x = &lt;1280&gt;;</div><div class='add'>+		touchscreen-size-y = &lt;800&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;reg_vdd_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lvds_bridge {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_MEDIA_LDB&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MP_VIDEO_PLL1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_VIDEO_PLL1_OUT&gt;;</div><div class='add'>+	/* IMX8MP_VIDEO_PLL1 = IMX8MP_CLK_MEDIA_DISP2_PIX * 7 */</div><div class='add'>+	assigned-clock-rates = &lt;0&gt;, &lt;506800000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@1 {</div><div class='add'>+			ldb_lvds_ch0: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;in_lvds0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm4 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_tft_vcom {</div><div class='add'>+	regulator-min-microvolt = &lt;3160000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;3160000&gt;;</div><div class='add'>+	voltage-table = &lt;3160000 73&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-revc-tian-g07017.dts b/arch/arm64/boot/dts/freescale/imx8mp-skov-revc-tian-g07017.dts<br/>new file mode 100644<br/>index 000000000000..9a562c011f2c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-skov-revc-tian-g07017.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-skov-revc-tian-g07017.dts</a></div><div class='hunk'>@@ -0,0 +1,81 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mp-skov-reva.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "SKOV IMX8MP CPU revC - TIAN G07017";</div><div class='add'>+	compatible = "skov,imx8mp-skov-revc-tian-g07017", "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	panel {</div><div class='add'>+		compatible = "topland,tian-g07017-01";</div><div class='add'>+		backlight = &lt;&amp;backlight&gt;;</div><div class='add'>+		power-supply = &lt;&amp;reg_tft_vcom&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			in_lvds0: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;ldb_lvds_ch0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;backlight {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	touchscreen@38 {</div><div class='add'>+		compatible = "edt,edt-ft5506";</div><div class='add'>+		reg = &lt;0x38&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_touchscreen&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;gpio4 28 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio4 29 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		touchscreen-size-x = &lt;1024&gt;;</div><div class='add'>+		touchscreen-size-y = &lt;600&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_vdd_3v3&gt;;</div><div class='add'>+		iovcc-supply = &lt;&amp;reg_vdd_3v3&gt;;</div><div class='add'>+		wakeup-source;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lvds_bridge {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_MEDIA_LDB&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MP_VIDEO_PLL1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_VIDEO_PLL1_OUT&gt;;</div><div class='add'>+	/* IMX8MP_VIDEO_PLL1 = IMX8MP_CLK_MEDIA_DISP2_PIX * 2 * 7 */</div><div class='add'>+	assigned-clock-rates = &lt;0&gt;, &lt;358400000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@1 {</div><div class='add'>+			ldb_lvds_ch0: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;in_lvds0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm4 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_tft_vcom {</div><div class='add'>+	regulator-min-microvolt = &lt;3160000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;3160000&gt;;</div><div class='add'>+	voltage-table = &lt;3160000 73&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi<br/>new file mode 100644<br/>index 000000000000..4e6629f940bf<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi</a></div><div class='hunk'>@@ -0,0 +1,591 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2025 Josua Mayer &lt;josua@solid-run.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "imx8mp.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "SolidRun i.MX8MP SoM";</div><div class='add'>+	compatible = "solidrun,imx8mp-sr-som", "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		bootargs = "earlycon=ec_imx6q,0x30890000,115200";</div><div class='add'>+		stdout-path = &amp;uart2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x40000000 0 0xc0000000&gt;,</div><div class='add'>+		      &lt;0x1 0x00000000 0 0xc0000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usdhc1_pwrseq: usdhc1-pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-simple";</div><div class='add'>+		reset-gpios = &lt;&amp;gpio2 11 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	v_1_8: regulator-1-8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "1v8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	v_3_3: regulator-3-3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "3v3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Reserve all physical memory from within the first 1GB of DDR address</div><div class='add'>+ * space to avoid panic on low memory systems.</div><div class='add'>+ */</div><div class='add'>+&amp;dsp_reserved {</div><div class='add'>+	reg = &lt;0 0x6f000000 0 0x1000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eqos {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;eqos_pins&gt;, &lt;&amp;phy0_pins&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy = &lt;&amp;phy0&gt;;</div><div class='add'>+	snps,force_thresh_dma_mode;</div><div class='add'>+	snps,mtl-tx-config = &lt;&amp;mtl_tx_setup&gt;;</div><div class='add'>+	snps,mtl-rx-config = &lt;&amp;mtl_rx_setup&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		phy0: ethernet-phy@0 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio4 19 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+			interrupts = &lt;18 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mtl_tx_setup: tx-queues-config {</div><div class='add'>+		snps,tx-queues-to-use = &lt;5&gt;;</div><div class='add'>+</div><div class='add'>+		queue0 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue1 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue2 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x4&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue3 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x8&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue4 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0xf0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mtl_rx_setup: rx-queues-config {</div><div class='add'>+		snps,rx-queues-to-use = &lt;5&gt;;</div><div class='add'>+		snps,rx-sched-sp;</div><div class='add'>+</div><div class='add'>+		queue0 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x1&gt;;</div><div class='add'>+			snps,map-to-dma-channel = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue1 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x2&gt;;</div><div class='add'>+			snps,map-to-dma-channel = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue2 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x4&gt;;</div><div class='add'>+			snps,map-to-dma-channel = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue3 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x8&gt;;</div><div class='add'>+			snps,map-to-dma-channel = &lt;3&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue4 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0xf0&gt;;</div><div class='add'>+			snps,map-to-dma-channel = &lt;4&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;fec_pins&gt;, &lt;&amp;phy1_pins&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy = &lt;&amp;phy1&gt;;</div><div class='add'>+	fsl,magic-packet;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		phy1: ethernet-phy@1 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;0x1&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio4 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+			interrupts = &lt;3 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c1_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;i2c1_gpio_pins&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pmic: pmic@25 {</div><div class='add'>+		compatible = "nxp,pca9450c";</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pmic_pins&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;3 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		nxp,i2c-lt-enable;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			buck1: BUCK1 {</div><div class='add'>+				regulator-name = "BUCK1";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2187500&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck2: BUCK2 {</div><div class='add'>+				regulator-name = "BUCK2";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2187500&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+				nxp,dvs-run-voltage = &lt;950000&gt;;</div><div class='add'>+				nxp,dvs-standby-voltage = &lt;850000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck4: BUCK4{</div><div class='add'>+				regulator-name = "BUCK4";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck5: BUCK5{</div><div class='add'>+				regulator-name = "BUCK5";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck6: BUCK6 {</div><div class='add'>+				regulator-name = "BUCK6";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo1: LDO1 {</div><div class='add'>+				regulator-name = "LDO1";</div><div class='add'>+				regulator-min-microvolt = &lt;1600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo2: LDO2 {</div><div class='add'>+				regulator-name = "LDO2";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1150000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo3: LDO3 {</div><div class='add'>+				regulator-name = "LDO3";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo4: LDO4 {</div><div class='add'>+				regulator-name = "LDO4";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo5: LDO5 {</div><div class='add'>+				regulator-name = "LDO5";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	som_eeprom: eeprom@50{</div><div class='add'>+		compatible = "st,24c01", "atmel,24c01";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c2_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;i2c2_gpio_pins&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c3_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;i2c3_gpio_pins&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	/* routed to basler camera connector */</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c4_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;i2c4_gpio_pins&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	eqos_pins: pinctrl-eqos-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC		0x3</div><div class='add'>+			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO		0x3</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0	0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1	0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2	0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3	0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL	0x91</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0	0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1	0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2	0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3	0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL	0x1f</div><div class='add'>+			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fec_pins: pinctrl-fec-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x91</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x91</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x91</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x91</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x1f</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x1f</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x1f</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x1f</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x1f</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c1_pins: pinctrl-i2c1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL			0x400001c3</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA			0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c1_gpio_pins: pinctrl-i2c1-gpio-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14		0x400001c3</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c2_pins: pinctrl-i2c2-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL			0x400001c3</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA			0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c2_gpio_pins: pinctrl-i2c2-gpio-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16		0x400001c3</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c3_pins: pinctrl-i2c3-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL			0x400001c3</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA			0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c3_gpio_pins: pinctrl-i2c3-gpio-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18		0x400001c3</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19		0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c4_pins: pinctrl-i2c4-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL			0x400001c3</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA			0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c4_gpio_pins: pinctrl-i2c4-gpio-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20			0x400001c3</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21			0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	phy0_pins: pinctrl-phy0-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* RESET_N: weak i/o, open drain, external 1k pull-up */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19		0x20</div><div class='add'>+			/* INT_N: weak i/o, open drain, internal pull-up */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18		0x160</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	phy1_pins: pinctrl-phy-1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* RESET_N: weak i/o, open drain, external 1k pull-up */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02		0x20</div><div class='add'>+			/* INT_N: weak i/o, open drain, internal pull-up */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03		0x160</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmic_pins: pinctrl-pmic-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03		0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart1_pins: pinctrl-uart1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX		0x140</div><div class='add'>+			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX		0x140</div><div class='add'>+			MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS		0x140</div><div class='add'>+			MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS		0x140</div><div class='add'>+			/* BT_REG_ON */</div><div class='add'>+			MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10		0x0</div><div class='add'>+			/* BT_WAKE_DEV */</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07		0x0</div><div class='add'>+			/* BT_WAKE_HOST */</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08		0x100</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart2_pins: pinctrl-uart2-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX		0x49</div><div class='add'>+			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX		0x49</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usdhc1_pins: pinctrl-usdhc1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x190</div><div class='add'>+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d0</div><div class='add'>+			/* WL_REG_ON */</div><div class='add'>+			MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11		0x0</div><div class='add'>+			/* WL_WAKE_HOST */</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09		0x100</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usdhc1_100mhz_pins: pinctrl-usdhc1g-100mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x194</div><div class='add'>+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usdhc1_200mhz_pins: pinctrl-usdhc1-200mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x196</div><div class='add'>+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usdhc3_pins: pinctrl-usdhc3-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x190</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x190</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usdhc3_100mhz_pins: pinctrl-usdhc3-100mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x194</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usdhc3_200mhz_pins: pinctrl-usdhc3-200mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x196</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x196</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wdog1_pins: pinctrl-wdog1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B		0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart1_pins&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	/* select 80MHz parent clock to support maximum baudrate 4Mbps */</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_UART1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL1_80M&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "brcm,bcm4345c5";</div><div class='add'>+		device-wakeup-gpios = &lt;&amp;gpio2 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		host-wakeup-gpios = &lt;&amp;gpio2 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		shutdown-gpios = &lt;&amp;gpio2 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		/* Murata 1MW module supports max. 3M baud */</div><div class='add'>+		max-speed = &lt;3000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart2_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;usdhc1_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;usdhc1_100mhz_pins&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;usdhc1_200mhz_pins&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;v_3_3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;v_1_8&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	mmc-pwrseq = &lt;&amp;usdhc1_pwrseq&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;usdhc3_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;usdhc3_100mhz_pins&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;usdhc3_200mhz_pins&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;v_3_3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;v_1_8&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;wdog1_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc-dev.dts b/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc-dev.dts<br/>new file mode 100644<br/>index 000000000000..6f9dcd3a75c8<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc-dev.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc-dev.dts</a></div><div class='hunk'>@@ -0,0 +1,300 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/* Copyright (C) 2025 Toradex */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/pwm/pwm.h&gt;</div><div class='add'>+</div><div class='add'>+#include "imx8mp-toradex-smarc.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Toradex SMARC iMX8M Plus on Toradex SMARC Development Board";</div><div class='add'>+	compatible = "toradex,smarc-imx8mp-dev",</div><div class='add'>+		     "toradex,smarc-imx8mp",</div><div class='add'>+		     "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	hdmi-connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		label = "J64";</div><div class='add'>+		type = "a";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			native_hdmi_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_tx_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_carrier_1p8v: regulator-carrier-1p8v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-name = "On-carrier 1V8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,bitclock-master = &lt;&amp;codec_dai&gt;;</div><div class='add'>+		simple-audio-card,format = "i2s";</div><div class='add'>+		simple-audio-card,frame-master = &lt;&amp;codec_dai&gt;;</div><div class='add'>+		simple-audio-card,mclk-fs = &lt;256&gt;;</div><div class='add'>+		simple-audio-card,name = "tdx-smarc-wm8904";</div><div class='add'>+		simple-audio-card,routing =</div><div class='add'>+			"Headphone Jack", "HPOUTL",</div><div class='add'>+			"Headphone Jack", "HPOUTR",</div><div class='add'>+			"IN2L", "Line In Jack",</div><div class='add'>+			"IN2R", "Line In Jack",</div><div class='add'>+			"Microphone Jack", "MICBIAS",</div><div class='add'>+			"IN1L", "Microphone Jack";</div><div class='add'>+		simple-audio-card,widgets =</div><div class='add'>+			"Microphone", "Microphone Jack",</div><div class='add'>+			"Headphone", "Headphone Jack",</div><div class='add'>+			"Line", "Line In Jack";</div><div class='add'>+</div><div class='add'>+		codec_dai: simple-audio-card,codec {</div><div class='add'>+			clocks = &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1&gt;;</div><div class='add'>+			sound-dai = &lt;&amp;wm8904_1a&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;sai1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;aud2htx {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC SPI0 */</div><div class='add'>+&amp;ecspi1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC GBE0 */</div><div class='add'>+&amp;eqos {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC GBE1 */</div><div class='add'>+&amp;fec {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC CAN1 */</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC CAN0 */</div><div class='add'>+&amp;flexcan2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio7&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_gpio8&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_gpio9&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_gpio10&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_gpio11&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_gpio12&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_gpio13&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio4&gt;, &lt;&amp;pinctrl_gpio6&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_pvi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC HDMI */</div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@1 {</div><div class='add'>+			hdmi_tx_out: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;native_hdmi_connector_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC I2C_LCD */</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	i2c-mux@70 {</div><div class='add'>+		compatible = "nxp,pca9543";</div><div class='add'>+		reg = &lt;0x70&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		/* I2C on DSI Connector Pins 4/6 */</div><div class='add'>+		i2c_dsi_0: i2c@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* I2C on DSI Connector Pins 52/54 */</div><div class='add'>+		i2c_dsi_1: i2c@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC I2C_CAM0 */</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC I2C_GP */</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	/* Audio Codec */</div><div class='add'>+	wm8904_1a: audio-codec@1a {</div><div class='add'>+		compatible = "wlf,wm8904";</div><div class='add'>+		reg = &lt;0x1a&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_sai1&gt;, &lt;&amp;pinctrl_sai1_mclk&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		clocks = &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1&gt;;</div><div class='add'>+		clock-names = "mclk";</div><div class='add'>+		AVDD-supply = &lt;&amp;reg_carrier_1p8v&gt;;</div><div class='add'>+		CPVDD-supply = &lt;&amp;reg_carrier_1p8v&gt;;</div><div class='add'>+		DBVDD-supply = &lt;&amp;reg_carrier_1p8v&gt;;</div><div class='add'>+		DCVDD-supply = &lt;&amp;reg_carrier_1p8v&gt;;</div><div class='add'>+		MICVDD-supply = &lt;&amp;reg_carrier_1p8v&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* On-Carrier Temperature Sensor */</div><div class='add'>+	temperature-sensor@4f {</div><div class='add'>+		compatible = "ti,tmp1075";</div><div class='add'>+		reg = &lt;0x4f&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* On-Carrier EEPROM */</div><div class='add'>+	eeprom@57 {</div><div class='add'>+		compatible = "st,24c02", "atmel,24c02";</div><div class='add'>+		reg = &lt;0x57&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC I2C_CAM1 */</div><div class='add'>+&amp;i2c5 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC I2C_PM */</div><div class='add'>+&amp;i2c6 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* Fan controller */</div><div class='add'>+	fan_controller: fan@18 {</div><div class='add'>+		compatible = "ti,amc6821";</div><div class='add'>+		reg = &lt;0x18&gt;;</div><div class='add'>+		#pwm-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		fan {</div><div class='add'>+			cooling-levels = &lt;255&gt;;</div><div class='add'>+			pwms = &lt;&amp;fan_controller 40000 PWM_POLARITY_INVERTED&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Current measurement into module VDD */</div><div class='add'>+	hwmon@40 {</div><div class='add'>+		compatible = "ti,ina226";</div><div class='add'>+		reg = &lt;0x40&gt;;</div><div class='add'>+		shunt-resistor = &lt;5000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC PCIE_A, M2 Key B */</div><div class='add'>+&amp;pcie {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC LCD1_BKLT_PWM */</div><div class='add'>+&amp;pwm1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC LCD0_BKLT_PWM */</div><div class='add'>+&amp;pwm2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC I2S0 */</div><div class='add'>+&amp;sai1 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_SAI1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;24576000&gt;;</div><div class='add'>+	fsl,sai-mclk-direction-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC HDMI Audio */</div><div class='add'>+&amp;sound_hdmi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC SER0, RS485. Optional M.2 KEY E */</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	linux,rs485-enabled-at-boot-time;</div><div class='add'>+	rs485-rts-active-low;</div><div class='add'>+	rs485-rx-during-tx;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC SER2 */</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC SER1, used as the Linux Console */</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC USB0 */</div><div class='add'>+&amp;usb3_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC USB1..4 */</div><div class='add'>+&amp;usb3_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC SDIO */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc.dtsi<br/>new file mode 100644<br/>index 000000000000..bebe19eb360f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc.dtsi</a></div><div class='hunk'>@@ -0,0 +1,1308 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/* Copyright (C) 2025 Toradex */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/phy/phy-imx8-pcie.h&gt;</div><div class='add'>+#include &lt;dt-bindings/net/ti-dp83867.h&gt;</div><div class='add'>+#include "imx8mp.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		can0 = &amp;flexcan2;</div><div class='add'>+		can1 = &amp;flexcan1;</div><div class='add'>+		ethernet0 = &amp;eqos;</div><div class='add'>+		ethernet1 = &amp;fec;</div><div class='add'>+		mmc0 = &amp;usdhc3;</div><div class='add'>+		mmc1 = &amp;usdhc2;</div><div class='add'>+		mmc2 = &amp;usdhc1;</div><div class='add'>+		rtc0 = &amp;rtc_i2c;</div><div class='add'>+		rtc1 = &amp;snvs_rtc;</div><div class='add'>+		serial0 = &amp;uart1;</div><div class='add'>+		serial1 = &amp;uart4;</div><div class='add'>+		serial2 = &amp;uart2;</div><div class='add'>+		serial3 = &amp;uart3;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart4;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	connector {</div><div class='add'>+		compatible = "gpio-usb-b-connector", "usb-b-connector";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usb0_id&gt;;</div><div class='add'>+		id-gpios = &lt;&amp;gpio5 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		label = "USB0";</div><div class='add'>+		self-powered;</div><div class='add'>+		type = "micro";</div><div class='add'>+		vbus-supply = &lt;&amp;reg_usb0_vbus&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			usb_dr_connector: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;usb3_0_dwc&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_sleep&gt;;</div><div class='add'>+</div><div class='add'>+		smarc_key_sleep: key-sleep {</div><div class='add'>+			gpios = &lt;&amp;gpio3 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			label = "SMARC_SLEEP#";</div><div class='add'>+			wakeup-source;</div><div class='add'>+			linux,code = &lt;KEY_SLEEP&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smarc_switch_lid: switch-lid {</div><div class='add'>+			gpios = &lt;&amp;som_ec_gpio_expander 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			label = "SMARC_LID#";</div><div class='add'>+			linux,code = &lt;SW_LID&gt;;</div><div class='add'>+			linux,input-type = &lt;EV_SW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb0_vbus: regulator-usb0-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usb0_en_oc&gt;;</div><div class='add'>+		gpios = &lt;&amp;gpio1 12 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-name = "USB0_EN_OC#";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb1_vbus: regulator-usb1-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usb1_en_oc&gt;;</div><div class='add'>+		gpios = &lt;&amp;gpio1 14 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-name = "USB2_EN_OC#";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usdhc2_pwr_en&gt;;</div><div class='add'>+		gpios = &lt;&amp;gpio2 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		off-on-delay-us = &lt;100000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "3V3_SD";</div><div class='add'>+		startup-delay-us = &lt;20000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc {</div><div class='add'>+		compatible = "regulator-gpio";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usdhc2_vsel&gt;;</div><div class='add'>+		gpios = &lt;&amp;gpio1 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		states = &lt;1800000 0x1&gt;,</div><div class='add'>+			 &lt;3300000 0x0&gt;;</div><div class='add'>+		regulator-name = "PMIC_USDHC_VSELECT";</div><div class='add'>+		vin-supply = &lt;&amp;reg_sd_3v3_1v8&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_wifi_en: regulator-wifi-en {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_wifi_pwr_en&gt;;</div><div class='add'>+		gpios = &lt;&amp;gpio3 14 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "CTRL_EN_WIFI";</div><div class='add'>+		startup-delay-us = &lt;2000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		linux,cma {</div><div class='add'>+			size = &lt;0 0x20000000&gt;;</div><div class='add'>+			alloc-ranges = &lt;0 0x40000000 0 0x80000000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound_hdmi: sound-hdmi {</div><div class='add'>+		compatible = "fsl,imx-audio-hdmi";</div><div class='add'>+		model = "audio-hdmi";</div><div class='add'>+		audio-cpu = &lt;&amp;aud2htx&gt;;</div><div class='add'>+		hdmi-out;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_vdd_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_vdd_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_vdd_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_vdd_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC SPI0 */</div><div class='add'>+&amp;ecspi1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi1&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 9 GPIO_ACTIVE_LOW&gt;, &lt;&amp;gpio4 28 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC SPI1 */</div><div class='add'>+&amp;ecspi2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi2&gt;, &lt;&amp;pinctrl_tpm_cs&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 13 GPIO_ACTIVE_LOW&gt;,</div><div class='add'>+		   &lt;&amp;gpio4 3 GPIO_ACTIVE_LOW&gt;,</div><div class='add'>+		   &lt;&amp;gpio3 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	tpm@2 {</div><div class='add'>+		compatible = "infineon,slb9670", "tcg,tpm_tis-spi";</div><div class='add'>+		reg = &lt;2&gt;;</div><div class='add'>+		spi-max-frequency = &lt;18500000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC GBE0 */</div><div class='add'>+&amp;eqos {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_eqos&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_eth_mdio&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_eqos_1588_event&gt;;</div><div class='add'>+	phy-handle = &lt;&amp;eqos_phy&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	snps,force_thresh_dma_mode;</div><div class='add'>+	snps,mtl-rx-config = &lt;&amp;mtl_rx_setup&gt;;</div><div class='add'>+	snps,mtl-tx-config = &lt;&amp;mtl_tx_setup&gt;;</div><div class='add'>+</div><div class='add'>+	mdio: mdio {</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mtl_rx_setup: rx-queues-config {</div><div class='add'>+		snps,rx-queues-to-use = &lt;5&gt;;</div><div class='add'>+</div><div class='add'>+		queue0 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x1&gt;;</div><div class='add'>+			snps,map-to-dma-channel = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue1 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x2&gt;;</div><div class='add'>+			snps,map-to-dma-channel = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue2 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x4&gt;;</div><div class='add'>+			snps,map-to-dma-channel = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue3 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x8&gt;;</div><div class='add'>+			snps,map-to-dma-channel = &lt;3&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue4 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0xf0&gt;;</div><div class='add'>+			snps,map-to-dma-channel = &lt;4&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mtl_tx_setup: tx-queues-config {</div><div class='add'>+		snps,tx-queues-to-use = &lt;5&gt;;</div><div class='add'>+</div><div class='add'>+		queue0 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue1 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue2 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x4&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue3 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x8&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue4 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0xf0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC GBE1 */</div><div class='add'>+&amp;fec {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec&gt;, &lt;&amp;pinctrl_fec_1588_event&gt;;</div><div class='add'>+	phy-handle = &lt;&amp;fec_phy&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	fsl,magic-packet;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC CAN1 */</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC CAN0 */</div><div class='add'>+&amp;flexcan2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	gpio-line-names = "SMARC_GPIO7", /* 0 */</div><div class='add'>+			  "SMARC_GPIO8",</div><div class='add'>+			  "",</div><div class='add'>+			  "PMIC_INT#",</div><div class='add'>+			  "PMIC_USDHC_VSELECT",</div><div class='add'>+			  "SMARC_GPIO9",</div><div class='add'>+			  "SMARC_GPIO10",</div><div class='add'>+			  "SMARC_GPIO11",</div><div class='add'>+			  "SMARC_GPIO12",</div><div class='add'>+			  "",</div><div class='add'>+			  "SMARC_GPIO5", /* 10 */</div><div class='add'>+			  "",</div><div class='add'>+			  "SMARC_USB0_EN_OC#",</div><div class='add'>+			  "SMARC_GPIO13",</div><div class='add'>+			  "SMARC_USB2_EN_OC#";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio2 {</div><div class='add'>+	gpio-line-names = "", /* 0 */</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "", /* 10 */</div><div class='add'>+			  "",</div><div class='add'>+			  "SMARC_SDIO_CD#",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "SMARC_SDIO_PWR_EN",</div><div class='add'>+			  "SMARC_SDIO_WP"; /* 20 */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lvds_dsi_sel&gt;;</div><div class='add'>+	gpio-line-names = "ETH_0_INT#", /* 0 */</div><div class='add'>+			  "SLEEP#",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "TPM_CS#",</div><div class='add'>+			  "LVDS_DSI_SEL",</div><div class='add'>+			  "MCU_INT#",</div><div class='add'>+			  "GPIO_EX_INT#",</div><div class='add'>+			  "", /* 10 */</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "SMARC_SMB_ALERT#",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "SMARC_I2C_PM_DAT", /* 20 */</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "SMARC_I2C_PM_CK";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	gpio-line-names = "SMARC_PCIE_WAKE#", /* 0 */</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "SMARC_SPI1_CS1#",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "", /* 10 */</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "SMARC_GPIO4",</div><div class='add'>+			  "SMARC_PCIE_A_RST#",</div><div class='add'>+			  "", /* 20 */</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "SMARC_SPI0_CS1#",</div><div class='add'>+			  "SMARC_GPIO6";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio5 {</div><div class='add'>+	gpio-line-names = "", /* 0 */</div><div class='add'>+			  "",</div><div class='add'>+			  "SMARC_USB0_OTG_ID",</div><div class='add'>+			  "SMARC_I2C_CAM1_CK",</div><div class='add'>+			  "SMARC_I2C_CAM1_DAT",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "SMARC_SPI0_CS0#",</div><div class='add'>+			  "", /* 10 */</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "SMARC_SPI1_CS0#",</div><div class='add'>+			  "CTRL_I2C_SCL",</div><div class='add'>+			  "CTRL_I2C_SDA",</div><div class='add'>+			  "SMARC_I2C_LCD_CK",</div><div class='add'>+			  "SMARC_I2C_LCD_DAT",</div><div class='add'>+			  "SMARC_I2C_CAM0_CK",</div><div class='add'>+			  "SMARC_I2C_CAM0_DAT",</div><div class='add'>+			  "SMARC_I2C_GP_CK", /* 20 */</div><div class='add'>+			  "SMARC_I2C_GP_DAT";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC HDMI */</div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hdmi&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* On-module I2C */</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c1_gpio&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	single-master;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	som_gpio_expander: gpio@21 {</div><div class='add'>+		compatible = "nxp,pcal6408";</div><div class='add'>+		reg = &lt;0x21&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pcal6408&gt;;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+		interrupts = &lt;9 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		gpio-line-names =</div><div class='add'>+			"SMARC_GPIO0",</div><div class='add'>+			"SMARC_GPIO1",</div><div class='add'>+			"SMARC_GPIO2",</div><div class='add'>+			"SMARC_GPIO3",</div><div class='add'>+			"SMARC_LCD0_VDD_EN",</div><div class='add'>+			"SMARC_LCD0_BKLT_EN",</div><div class='add'>+			"SMARC_LCD1_VDD_EN",</div><div class='add'>+			"SMARC_LCD1_BKLT_EN";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pca9450: pmic@25 {</div><div class='add'>+		compatible = "nxp,pca9450c";</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;3 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			BUCK1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;805000&gt;;</div><div class='add'>+				regulator-name = "+VDD_SOC (PMIC BUCK1)";</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vdd_arm: BUCK2 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;805000&gt;;</div><div class='add'>+				regulator-name = "+VDD_ARM (PMIC BUCK2)";</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+				nxp,dvs-run-voltage = &lt;950000&gt;;</div><div class='add'>+				nxp,dvs-standby-voltage = &lt;850000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_3v3: BUCK4 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "+V3.3 (PMIC BUCK4)";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_1v8: BUCK5 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "+V1.8 (PMIC BUCK5)";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			BUCK6 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1155000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1045000&gt;;</div><div class='add'>+				regulator-name = "+VDD_DDR (PMIC BUCK6)";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			LDO1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1950000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1710000&gt;;</div><div class='add'>+				regulator-name = "+V1.8_SNVS (PMIC LDO1)";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			LDO3 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "+V1.8A (PMIC LDO3)";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			LDO4 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "+V3.3_ADC (PMIC LDO4)";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_sd_3v3_1v8: LDO5 {</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "+V3.3_1.8_SD (PMIC LDO5)";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	embedded-controller@28 {</div><div class='add'>+		compatible = "toradex,smarc-imx8mp-ec", "toradex,smarc-ec";</div><div class='add'>+		reg = &lt;0x28&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	som_ec_gpio_expander: gpio@29 {</div><div class='add'>+		compatible = "toradex,ecgpiol16", "nxp,pcal6416";</div><div class='add'>+		reg = &lt;0x29&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_mcu_int&gt;;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+		interrupts = &lt;8 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		gpio-line-names =</div><div class='add'>+			"SMARC_CHARGER_PRSNT#",</div><div class='add'>+			"SMARC_CHARGING#",</div><div class='add'>+			"SMARC_LID#",</div><div class='add'>+			"SMARC_BATLOW#";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rtc_i2c: rtc@32 {</div><div class='add'>+		compatible = "epson,rx8130";</div><div class='add'>+		reg = &lt;0x32&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	temperature-sensor@48 {</div><div class='add'>+		compatible = "ti,tmp1075";</div><div class='add'>+		reg = &lt;0x48&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@50 {</div><div class='add'>+		compatible = "st,24c02", "atmel,24c02";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC I2C_LCD */</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c2_gpio&gt;;</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	single-master;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC I2C_CAM0 */</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c3_gpio&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	single-master;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC I2C_GP */</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c4&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c4_gpio&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	single-master;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	eeprom@50 {</div><div class='add'>+		compatible = "st,24c32", "atmel,24c32";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC I2C_CAM1 */</div><div class='add'>+&amp;i2c5 {</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c5&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c5_gpio&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	single-master;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC I2C_PM */</div><div class='add'>+&amp;i2c6 {</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c6&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c6_gpio&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio3 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	single-master;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdio {</div><div class='add'>+	eqos_phy: ethernet-phy@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+		interrupts = &lt;0 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_2_00_NS&gt;;</div><div class='add'>+		ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_2_00_NS&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fec_phy: ethernet-phy@2 {</div><div class='add'>+		reg = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+		interrupts = &lt;0 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_2_00_NS&gt;;</div><div class='add'>+		ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_2_00_NS&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC PCIE_A */</div><div class='add'>+&amp;pcie {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie&gt;;</div><div class='add'>+	reset-gpios = &lt;&amp;gpio4 19 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	clocks = &lt;&amp;hsio_blk_ctrl&gt;;</div><div class='add'>+	clock-names = "ref";</div><div class='add'>+	fsl,clkreq-unsupported;</div><div class='add'>+	fsl,refclk-pad-mode = &lt;IMX8_PCIE_REFCLK_PAD_OUTPUT&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC LCD1_BKLT_PWM */</div><div class='add'>+&amp;pwm1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lcd1_bklt_pwm1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC LCD0_BKLT_PWM */</div><div class='add'>+&amp;pwm2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lcd0_bklt_pwm2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC GPIO5 as PWM */</div><div class='add'>+&amp;pwm3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio5_pwm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;snvs_pwrkey {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC SER0 */</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC SER2 */</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* On-module Bluetooth, optional SMARC SER3 */</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_bt_uart&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	som_bt: bluetooth {</div><div class='add'>+		compatible = "mrvl,88w8997";</div><div class='add'>+		max-speed = &lt;921600&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC SER1, used as the Linux Console */</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart4&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC USB0 */</div><div class='add'>+&amp;usb3_0 {</div><div class='add'>+	fsl,disable-port-power-control;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC USB1..4 */</div><div class='add'>+&amp;usb3_1 {</div><div class='add'>+	fsl,disable-port-power-control;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy1 {</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usb1_vbus&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_0 {</div><div class='add'>+	adp-disable;</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	hnp-disable;</div><div class='add'>+	maximum-speed = "high-speed";</div><div class='add'>+	srp-disable;</div><div class='add'>+	usb-role-switch;</div><div class='add'>+</div><div class='add'>+	port {</div><div class='add'>+		usb3_0_dwc: endpoint {</div><div class='add'>+			remote-endpoint = &lt;&amp;usb_dr_connector&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_1 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* On-module Wi-Fi */</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1_200mhz&gt;;</div><div class='add'>+	keep-power-in-suspend;</div><div class='add'>+	non-removable;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_wifi_en&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC SDIO */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_usdhc2_cd&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_usdhc2_wp&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_usdhc2_cd&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_usdhc2_wp&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_usdhc2_cd&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_usdhc2_wp&gt;;</div><div class='add'>+	pinctrl-3 = &lt;&amp;pinctrl_usdhc2_sleep&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_usdhc2_cd_sleep&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_usdhc2_wp&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_USDHC2&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_usdhc2_vqmmc&gt;;</div><div class='add'>+	wp-gpios = &lt;&amp;gpio2 20 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* On-module eMMC */</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_USDHC3_ROOT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	/* On-module Bluetooth */</div><div class='add'>+	pinctrl_bt_uart: btuartgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX	0x1c4&gt;, /* WiFi_UART_TXD */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX	0x1c4&gt;, /* WiFi_UART_RXD */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD1_STROBE__UART3_DCE_CTS	0x1c4&gt;, /* WiFi_UART_RTS */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD1_RESET_B__UART3_DCE_RTS	0x1c4&gt;; /* WiFi_UART_CTS */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC CAM_MCK */</div><div class='add'>+	pinctrl_csi_mclk: csimclkgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_GPIO1_IO15__CCM_CLKO2	0x16&gt;; /* SMARC S6 - CAM_MCK  */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC SPI0 */</div><div class='add'>+	pinctrl_ecspi1: ecspi1grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO	0x1c4&gt;, /* SMARC P45 - SPI0_DIN */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI	0x4&gt;,   /* SMARC P46 - SPI0_DO */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK	0x4&gt;,   /* SMARC P44 - SPI0_CK */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09		0x1c4&gt;, /* SMARC P43 - SPI0_CS0# */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28		0x1c4&gt;; /* SMARC P31 - SPI0_CS1# */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC SPI1 */</div><div class='add'>+	pinctrl_ecspi2: ecspi2grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO	0x1c4&gt;, /* SMARC P56 - SPI1_DIN */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI	0x4&gt;,   /* SMARC P57 - SPI1_DO */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK	0x4&gt;,   /* SMARC P58 - SPI1_CK */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13		0x1c4&gt;, /* SMARC P54 - SPI1_CS0# */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03		0x1c4&gt;; /* SMARC P55 - SPI1_CS1# */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* ETH_0 RGMII (On-module PHY) */</div><div class='add'>+	pinctrl_eqos: eqosgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x90&gt;, /* ETH0_RGMII_RXD0 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x90&gt;, /* ETH0_RGMII_RXD1 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x90&gt;, /* ETH0_RGMII_RXD2 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x90&gt;, /* ETH0_RGMII_RXD3 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x90&gt;, /* ETH0_RGMII_RXC */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x90&gt;, /* ETH0_RGMII_RX_CTL */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x16&gt;, /* ETH0_RGMII_TXD0 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x16&gt;, /* ETH0_RGMII_TXD1 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x16&gt;, /* ETH0_RGMII_TXD2 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x16&gt;, /* ETH0_RGMII_TXD3 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x16&gt;, /* ETH0_RGMII_TX_CTL */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x16&gt;; /* ETH0_RGMII_TXC */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC GBE0_SDP */</div><div class='add'>+	pinctrl_eqos_1588_event: eqos1588eventgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_GPIO1_IO09__ENET_QOS_1588_EVENT0_OUT	0x4&gt;; /* SMARC P6 - GBE0_SDP */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* ETH_0_MDIO and ETH_0_INT# shared between ETH_PHY0 and ETH_PHY1 */</div><div class='add'>+	pinctrl_eth_mdio: ethmdiogrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC		0x2&gt;,  /* ETH_0_MDC */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO	0x2&gt;,  /* ETH_0_MDIO */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00		0x80&gt;; /* ETH_0_INT# */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* ETH_1 RGMII (On-module PHY) */</div><div class='add'>+	pinctrl_fec: fecgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0	0x90&gt;, /* ETH1_RGMII_RXD0 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1	0x90&gt;, /* ETH1_RGMII_RXD1 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2	0x90&gt;, /* ETH1_RGMII_RXD2 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3	0x90&gt;, /* ETH1_RGMII_RXD3 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC	0x90&gt;, /* ETH1_RGMII_RXC */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x90&gt;, /* ETH1_RGMII_RX_CTL */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0	0x16&gt;, /* ETH1_RGMII_TXD0 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1	0x16&gt;, /* ETH1_RGMII_TXD1 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2	0x16&gt;, /* ETH1_RGMII_TXD2 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3	0x16&gt;, /* ETH1_RGMII_TXD3 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x16&gt;, /* ETH1_RGMII_TX_CTL */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC	0x16&gt;; /* ETH1_RGMII_TXC */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC GBE1_SDP */</div><div class='add'>+	pinctrl_fec_1588_event: fec1588eventgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT	0x4&gt;; /* SMARC P5 - GBE1_SDP */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC CAN1 */</div><div class='add'>+	pinctrl_flexcan1: flexcan1grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SAI2_TXC__CAN1_RX	0x154&gt;, /* SMARC P146 - CAN1_RX */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI2_RXC__CAN1_TX	0x154&gt;; /* SMARC P145 - CAN1_TX */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC CAN0 */</div><div class='add'>+	pinctrl_flexcan2: flexcan2grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX	0x154&gt;, /* SMARC P144 - CAN0_RX */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX	0x154&gt;; /* SMARC P143 - CAN0_TX */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC GPIO4 */</div><div class='add'>+	pinctrl_gpio4: gpio4grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18	0x144&gt;; /* SMARC P112 - GPIO4 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC GPIO5 */</div><div class='add'>+	pinctrl_gpio5: gpio5grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10	0x144&gt;; /* SMARC P113 - GPIO5 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC GPIO5 as PWM */</div><div class='add'>+	pinctrl_gpio5_pwm: gpio5pwmgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_GPIO1_IO10__PWM3_OUT	0x12&gt;; /* SMARC P113 - PWM_OUT */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC GPIO6 */</div><div class='add'>+	pinctrl_gpio6: gpio6grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29	0x144&gt;; /* SMARC P114 - GPIO6 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC GPIO7 */</div><div class='add'>+	pinctrl_gpio7: gpio7grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00	0x144&gt;; /* SMARC P115 - GPIO7 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC GPIO8 */</div><div class='add'>+	pinctrl_gpio8: gpio8grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01	0x144&gt;; /* SMARC P116 - GPIO8 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC GPIO9 */</div><div class='add'>+	pinctrl_gpio9: gpio9grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05	0x144&gt;; /* SMARC P117 - GPIO9 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC GPIO10 */</div><div class='add'>+	pinctrl_gpio10: gpio10grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06	0x144&gt;; /* SMARC P118 - GPIO10 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC GPIO11 */</div><div class='add'>+	pinctrl_gpio11: gpio11grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07	0x144&gt;; /* SMARC P119 - GPIO11 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC GPIO12 */</div><div class='add'>+	pinctrl_gpio12: gpio12grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08	0x144&gt;; /* SMARC S142 - GPIO12 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC GPIO13 */</div><div class='add'>+	pinctrl_gpio13: gpio13grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13	0x144&gt;; /* SMARC S123 - GPIO13 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC HDMI */</div><div class='add'>+	pinctrl_hdmi: hdmigrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL	0x400001c6&gt;, /* SMARC P105 - HDMI_CTRL_CK */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA	0x400001c6&gt;, /* SMARC P106 - HDMI_CTRL_DAT */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD	0x180&gt;;      /* SMARC P104 - HDMI_HPD */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* On-module I2C */</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL	0x400001c6&gt;, /* CTRL_I2C_SCL */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA	0x400001c6&gt;; /* CTRL_I2C_SDA */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* On-module I2C as GPIOs */</div><div class='add'>+	pinctrl_i2c1_gpio: i2c1gpiogrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14	0x400001c6&gt;, /* CTRL_I2C_SCL */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15	0x400001c6&gt;; /* CTRL_I2C_SDA */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC I2C_LCD */</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL	0x400001c6&gt;, /* SMARC S139 - I2C_LCD_CK */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA	0x400001c6&gt;; /* SMARC S140 - I2C_LCD_DAT */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC I2C_LCD as GPIOs */</div><div class='add'>+	pinctrl_i2c2_gpio: i2c2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16	0x400001c6&gt;, /* SMARC S139 - I2C_LCD_CK */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17	0x400001c6&gt;; /* SMARC S140 - I2C_LCD_DAT */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC I2C_CAM0 */</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL	0x400001c6&gt;, /* SMARC S5 - I2C_CAM0_CK */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA	0x400001c6&gt;; /* SMARC S7 - I2C_CAM0_DAT */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC I2C_CAM0 as GPIOs */</div><div class='add'>+	pinctrl_i2c3_gpio: i2c3gpiogrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18	0x400001c6&gt;, /* SMARC S5 - I2C_CAM0_CK */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19	0x400001c6&gt;; /* SMARC S7 - I2C_CAM0_DAT */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC I2C_GP */</div><div class='add'>+	pinctrl_i2c4: i2c4grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL	0x400001c6&gt;, /* SMARC S48 - I2C_GP_CK */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA	0x400001c6&gt;; /* SMARC S49 - I2C_GP_DAT */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC I2C_GP as GPIOs */</div><div class='add'>+	pinctrl_i2c4_gpio: i2c4gpiogrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20	0x400001c6&gt;, /* SMARC S48 - I2C_GP_CK */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21	0x400001c6&gt;; /* SMARC S49 - I2C_GP_DAT */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC I2C_CAM1 */</div><div class='add'>+	pinctrl_i2c5: i2c5grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA	0x400001c6&gt;, /* SMARC S2 - I2C_CAM1_DAT  */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL	0x400001c6&gt;; /* SMARC S1 - I2C_CAM1_CK  */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC I2C_CAM1 as GPIOs */</div><div class='add'>+	pinctrl_i2c5_gpio: i2c5gpiogrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04	0x400001c6&gt;, /* SMARC S2 - I2C_CAM1_DAT  */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03	0x400001c6&gt;; /* SMARC S1 - I2C_CAM1_CK  */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC I2C_PM */</div><div class='add'>+	pinctrl_i2c6: i2c6grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_HDMI_CEC__I2C6_SCL	0x400001c6&gt;, /* SMARC P121 - I2C_PM_CK */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA	0x400001c6&gt;; /* SMARC P122 - I2C_PM_DAT */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC I2C_PM as GPIOs */</div><div class='add'>+	pinctrl_i2c6_gpio: i2c6gpiogrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_HDMI_CEC__GPIO3_IO28	0x400001c6&gt;, /* SMARC P121 - I2C_PM_CK */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20	0x400001c6&gt;; /* SMARC P122 - I2C_PM_DAT */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lvds_dsi_sel: lvdsdsiselgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07	0x104&gt;; /* LVDS_DSI_SEL */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_mcu_int: mcuintgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08	0x1C0&gt;; /* MCU_INT# */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC LCD1_BKLT_PWM */</div><div class='add'>+	pinctrl_lcd1_bklt_pwm1: pwm1grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT	0x12&gt;; /* SMARC S122 - LCD1_BKLT_PWM */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC LCD0_BKLT_PWM */</div><div class='add'>+	pinctrl_lcd0_bklt_pwm2: pwm2grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT	0x12&gt;; /* SMARC S141 - LCD0_BKLT_PWM */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PCAL6408 Interrupt */</div><div class='add'>+	pinctrl_pcal6408: pcal6408intgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09	0x1c4&gt;; /* GPIO_EX_INT# */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC PCIE_A */</div><div class='add'>+	pinctrl_pcie: pciegrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00	0x1c0&gt;, /* SMARC S146 - PCIE_WAKE# */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19	0x04&gt;;  /* SMARC P75 - PCIE_A_RST# */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PMIC Interrupt */</div><div class='add'>+	pinctrl_pmic: pmicintgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03	0x1c4&gt;; /* PMIC_INT# */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC I2S0 */</div><div class='add'>+	pinctrl_sai1: sai1grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK	0x94&gt;, /* SMARC S42 - I2S0_CK */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC	0x94&gt;, /* SMARC S39 - I2S0_LRCLK */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00	0x94&gt;, /* SMARC S41 - I2S0_SDIN */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00	0x94&gt;; /* SMARC S40 - I2S0_SDOUT */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC AUDIO_MCK */</div><div class='add'>+	pinctrl_sai1_mclk: sai1mclkgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK	0x96&gt;; /* SMARC S38 - AUDIO_MCK */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC I2S2 */</div><div class='add'>+	pinctrl_sai3: sai3grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00	0x94&gt;, /* SMARC S52 - I2S2_SDIN */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK	0x94&gt;, /* SMARC S53 - I2S2_CK */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00	0x94&gt;, /* SMARC S51 - I2S2_SDOUT */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC	0x94&gt;; /* SMARC S50 - I2S2_LRCLK */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC SLEEP# */</div><div class='add'>+	pinctrl_sleep: sleepgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01	0x1C0&gt;; /* SMARC S149 - SLEEP# */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC SMB_ALERT# */</div><div class='add'>+	pinctrl_smb_alert: smbalertgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16	0x1C0&gt;; /* SMARC P1 - SMB_ALERT# */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* TPM_CS# */</div><div class='add'>+	pinctrl_tpm_cs: tpmcsgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06	0x82&gt;; /* TPM_CS# */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* WIFI_BT_WKUP_HOST/TPM_INT# */</div><div class='add'>+	pinctrl_tpm_irq_wifi_bt_wkup: tpmirq-wifibtwkupgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04	0x16&gt;; /* WIFI_BT_WKUP_HOST/TPM_INT# */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC SER0 */</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS	0x1c4&gt;, /* SMARC P132 - SER2_CTS */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS	0x1c4&gt;, /* SMARC P131 - SER2_RTS */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX	0x1c4&gt;, /* SMARC P130 - SER2_RX */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX	0x1c4&gt;; /* SMARC P139 - SER2_TX */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC SER2 */</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS	0x1c4&gt;, /* SMARC P139 - SER2_CTS */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS	0x1c4&gt;, /* SMARC P138 - SER2_RTS */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x1c4&gt;, /* SMARC P137 - SER2_RX */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x1c4&gt;; /* SMARC P136 - SER2_TX */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC SER3 */</div><div class='add'>+	pinctrl_uart3: uart3grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX	0x1c4&gt;, /* SMARC P141 - SER3_RX */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX	0x1c4&gt;; /* SMARC P140 - SER3_TX */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC SER1 */</div><div class='add'>+	pinctrl_uart4: uart4grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX	0x1c4&gt;, /* SMARC P135 - SER1_RX */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX	0x1c4&gt;; /* SMARC P134 - SER1_TX */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC USB0_OTG_ID */</div><div class='add'>+	pinctrl_usb0_id: usb0idgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02	0x1c4&gt;; /* SMARC P64 - USB0_OTG_ID */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC USB0_EN_OC# */</div><div class='add'>+	pinctrl_usb0_en_oc: usb0enocgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12	0x04&gt;; /* SMARC P62 - USB0_EN_OC# */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* On module USB Hub VBUS, or SMARC USB2_EN_OC# depending on assembling */</div><div class='add'>+	pinctrl_usb1_en_oc: usb1enocgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14	0x04&gt;; /* SMARC P71 - USB2_EN_OC# */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* On-module Wi-Fi */</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x190&gt;, /* WiFi_SDIO_CLK */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d0&gt;, /* WiFi_SDIO_CMD */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d0&gt;, /* WiFi_SDIO_DATA0 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d0&gt;, /* WiFi_SDIO_DATA1 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d0&gt;, /* WiFi_SDIO_DATA2 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d0&gt;; /* WiFi_SDIO_DATA3 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* On-module Wi-Fi */</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x194&gt;, /* WiFi_SDIO_CLK */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d4&gt;, /* WiFi_SDIO_CMD */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d4&gt;, /* WiFi_SDIO_DATA0 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d4&gt;, /* WiFi_SDIO_DATA1 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d4&gt;, /* WiFi_SDIO_DATA2 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d4&gt;; /* WiFi_SDIO_DATA3 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* On-module Wi-Fi */</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x196&gt;, /* WiFi_SDIO_CLK */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d6&gt;, /* WiFi_SDIO_CMD */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d6&gt;, /* WiFi_SDIO_DATA0 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d6&gt;, /* WiFi_SDIO_DATA1 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d6&gt;, /* WiFi_SDIO_DATA2 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d6&gt;; /* WiFi_SDIO_DATA3 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC SDIO */</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x190&gt;, /* SMARC P36 - SDIO_CK */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d0&gt;, /* SMARC P34 - SDIO_CMD */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d0&gt;, /* SMARC P39 - SDIO_DO */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d0&gt;, /* SMARC P40 - SDIO_D1 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d0&gt;, /* SMARC P41 - SDIO_D2 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d0&gt;; /* SMARC P42 - SDIO_D3 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC SDIO 100MHz */</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x194&gt;, /* SMARC P36 - SDIO_CK */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d4&gt;, /* SMARC P34 - SDIO_CMD */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d4&gt;, /* SMARC P39 - SDIO_DO */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d4&gt;, /* SMARC P40 - SDIO_D1 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d4&gt;, /* SMARC P41 - SDIO_D2 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d4&gt;; /* SMARC P42 - SDIO_D3 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC SDIO 200MHz */</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x196&gt;, /* SMARC P36 - SDIO_CK */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d6&gt;, /* SMARC P34 - SDIO_CMD */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d6&gt;, /* SMARC P39 - SDIO_DO */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d6&gt;, /* SMARC P40 - SDIO_D1 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d6&gt;, /* SMARC P41 - SDIO_D2 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d6&gt;; /* SMARC P42 - SDIO_D3 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC SDIO_CD# */</div><div class='add'>+	pinctrl_usdhc2_cd: usdhc2cdgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12	0x1c4&gt;; /* SMARC P35 - SDIO_CD# */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC SDIO_CD# */</div><div class='add'>+	pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12	0x0&gt;; /* SMARC P35 - SDIO_CD# */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC SDIO_PWR_EN */</div><div class='add'>+	pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x1c4&gt;; /* SMARC P37 - SDIO_PWR_EN */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC SDIO Sleep - Avoid backfeeding with removed card power */</div><div class='add'>+	pinctrl_usdhc2_sleep: usdhc2slpgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x100&gt;, /* SMARC P36 - SDIO_CK */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x100&gt;, /* SMARC P34 - SDIO_CMD */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x100&gt;, /* SMARC P39 - SDIO_DO */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x100&gt;, /* SMARC P39 - SDIO_D1 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x100&gt;, /* SMARC P39 - SDIO_D2 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x100&gt;; /* SMARC P39 - SDIO_D3 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_vsel: usdhc2vselgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04	0x4&gt;; /* PMIC_USDHC_VSELECT */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC SDIO_WP */</div><div class='add'>+	pinctrl_usdhc2_wp: usdhc2wpgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SD2_WP__GPIO2_IO20	0x144&gt;; /* SMARC P33 - SDIO_WP */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* On-module eMMC */</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x190&gt;, /* eMMC_STROBE */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d0&gt;, /* eMMC_DATA5 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d0&gt;, /* eMMC_DATA6 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d0&gt;, /* eMMC_DATA7 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d0&gt;, /* eMMC_DATA0 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d0&gt;, /* eMMC_DATA1 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d0&gt;, /* eMMC_DATA2 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d0&gt;, /* eMMC_DATA3 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d0&gt;, /* eMMC_DATA4 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x190&gt;, /* eMMC_CLK */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d0&gt;; /* eMMC_CMD */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* On-module eMMC */</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x194&gt;, /* eMMC_STROBE */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4&gt;, /* eMMC_DATA5 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4&gt;, /* eMMC_DATA6 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4&gt;, /* eMMC_DATA7 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4&gt;, /* eMMC_DATA0 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4&gt;, /* eMMC_DATA1 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4&gt;, /* eMMC_DATA2 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4&gt;, /* eMMC_DATA3 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4&gt;, /* eMMC_DATA4 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194&gt;, /* eMMC_CLK */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4&gt;; /* eMMC_CMD */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* On-module eMMC */</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x196&gt;, /* eMMC_STROBE */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d2&gt;, /* eMMC_DATA5 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d2&gt;, /* eMMC_DATA6 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d2&gt;, /* eMMC_DATA7 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d2&gt;, /* eMMC_DATA0 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d2&gt;, /* eMMC_DATA1 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d2&gt;, /* eMMC_DATA2 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d2&gt;, /* eMMC_DATA3 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d2&gt;, /* eMMC_DATA4 */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x196&gt;, /* eMMC_CLK */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d6&gt;; /* eMMC_CMD */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SoC Watchdog */</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B	0x4&gt;; /* CTRL_SOC_WDOG */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* On-module Wi-Fi power enable */</div><div class='add'>+	pinctrl_wifi_pwr_en: wifipwrengrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14	0x104&gt;; /* CTRL_EN_WIFI */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314-imx219.dtso b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314-imx219.dtso<br/>new file mode 100644<br/>index 000000000000..e5a2b3780215<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314-imx219.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314-imx219.dtso</a></div><div class='hunk'>@@ -0,0 +1,107 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022-2025 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Alexander Stein</div><div class='add'>+ */</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/media/video-interfaces.h&gt;</div><div class='add'>+</div><div class='add'>+#include "imx8mp-pinfunc.h"</div><div class='add'>+</div><div class='add'>+&amp;{/} {</div><div class='add'>+	/*</div><div class='add'>+	 * The three camera regulators are controlled by a single GPIO. Declare</div><div class='add'>+	 * a single regulator for the three supplies.</div><div class='add'>+	 */</div><div class='add'>+	reg_cam: regulator-cam {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "reg_cam";</div><div class='add'>+		/* pad muxing already done in gpio2grp */</div><div class='add'>+		gpio = &lt;&amp;gpio2 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		vin-supply = &lt;&amp;reg_vcc_3v3&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cam24m: clock-cam24m {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+		clock-output-names = "cam24m";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	camera@10 {</div><div class='add'>+		compatible = "sony,imx219";</div><div class='add'>+		reg = &lt;0x10&gt;;</div><div class='add'>+		clocks = &lt;&amp;cam24m&gt;;</div><div class='add'>+		VANA-supply = &lt;&amp;reg_cam&gt;;</div><div class='add'>+		VDIG-supply = &lt;&amp;reg_cam&gt;;</div><div class='add'>+		VDDL-supply = &lt;&amp;reg_cam&gt;;</div><div class='add'>+		orientation = &lt;2&gt;;</div><div class='add'>+		rotation = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			sony_imx219: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;imx8mp_mipi_csi_in&gt;;</div><div class='add'>+				clock-lanes = &lt;0&gt;;</div><div class='add'>+				clock-noncontinuous;</div><div class='add'>+				data-lanes = &lt;1 2&gt;;</div><div class='add'>+				link-frequencies = /bits/ 64 &lt;456000000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;isi_0 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@0 {</div><div class='add'>+			/delete-node/ endpoint;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;isp_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@1 {</div><div class='add'>+			isp0_in: endpoint {</div><div class='add'>+				bus-type = &lt;MEDIA_BUS_TYPE_PARALLEL&gt;;</div><div class='add'>+				remote-endpoint = &lt;&amp;mipi_csi_0_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_csi_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		port@0 {</div><div class='add'>+			imx8mp_mipi_csi_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;sony_imx219&gt;;</div><div class='add'>+				clock-lanes = &lt;0&gt;;</div><div class='add'>+				data-lanes = &lt;1 2&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_csi_0_out {</div><div class='add'>+	remote-endpoint = &lt;&amp;isp0_in&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts<br/>new file mode 100644<br/>index 000000000000..f7346b3d35fe<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts</a></div><div class='hunk'>@@ -0,0 +1,907 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2023-2024 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Martin Schmiedel</div><div class='add'>+ * Author: Alexander Stein</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/net/ti-dp83867.h&gt;</div><div class='add'>+#include &lt;dt-bindings/phy/phy-imx8-pcie.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pwm/pwm.h&gt;</div><div class='add'>+#include "imx8mp-tqma8mpql.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MP-RAS314";</div><div class='add'>+	compatible = "tq,imx8mp-tqma8mpql-mba8mp-ras314", "tq,imx8mp-tqma8mpql", "fsl,imx8mp";</div><div class='add'>+	chassis-type = "embedded";</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart4;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		mmc0 = &amp;usdhc3;</div><div class='add'>+		mmc1 = &amp;usdhc2;</div><div class='add'>+		mmc2 = &amp;usdhc1;</div><div class='add'>+		rtc0 = &amp;pcf85063;</div><div class='add'>+		rtc1 = &amp;snvs_rtc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* X8 */</div><div class='add'>+	backlight_lvds: backlight {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_backlight&gt;;</div><div class='add'>+		pwms = &lt;&amp;pwm2 0 5000000 0&gt;;</div><div class='add'>+		brightness-levels = &lt;0 4 8 16 32 64 128 255&gt;;</div><div class='add'>+		default-brightness-level = &lt;7&gt;;</div><div class='add'>+		power-supply = &lt;&amp;reg_vcc_12v0&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;gpio1 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* X7 + X8 */</div><div class='add'>+	display: display {</div><div class='add'>+		/*</div><div class='add'>+		 * Display is not fixed, so compatible has to be added from</div><div class='add'>+		 * DT overlay</div><div class='add'>+		 */</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_lvdsdisplay&gt;;</div><div class='add'>+		power-supply = &lt;&amp;reg_vcc_3v3&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;gpio1 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		backlight = &lt;&amp;backlight_lvds&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpioled&gt;;</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			function-enumerator = &lt;0&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio4 18 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-2 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_YELLOW&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			function-enumerator = &lt;1&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio4 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdmi-connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		label = "X9";</div><div class='add'>+		type = "a";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			hdmi_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_tx_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usdhc2_vmmc&gt;;</div><div class='add'>+		regulator-name = "VSD_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio2 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		startup-delay-us = &lt;100&gt;;</div><div class='add'>+		off-on-delay-us = &lt;12000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc_3v3: regulator-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "V_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc_5v0: regulator-5v0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "V_5V0";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc_12v0: regulator-12v0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "V_12V";</div><div class='add'>+		regulator-min-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;12000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		/* global autoconfigured region for contiguous allocations */</div><div class='add'>+		linux,cma {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reusable;</div><div class='add'>+			size = &lt;0 0x38000000&gt;;</div><div class='add'>+			alloc-ranges = &lt;0 0x40000000 0 0xB0000000&gt;;</div><div class='add'>+			linux,cma-default;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rfkill {</div><div class='add'>+		compatible = "rfkill-gpio";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_rfkill&gt;;</div><div class='add'>+		label = "rfkill-pcie-wlan";</div><div class='add'>+		radio-type = "wlan";</div><div class='add'>+		shutdown-gpios = &lt;&amp;gpio5 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "fsl,imx-audio-tlv320aic32x4";</div><div class='add'>+		model = "tq-mba8mp-ras314";</div><div class='add'>+		audio-cpu = &lt;&amp;sai5&gt;;</div><div class='add'>+		audio-codec = &lt;&amp;tlv320aic3x04&gt;;</div><div class='add'>+		audio-routing =</div><div class='add'>+			"IN3_L", "Mic Jack",</div><div class='add'>+			"Mic Jack", "Mic Bias",</div><div class='add'>+			"Headphone Jack", "HPL",</div><div class='add'>+			"Headphone Jack", "HPR";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi3&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 25 GPIO_ACTIVE_LOW&gt;, &lt;&amp;gpio1 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eqos {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_eqos&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy3: ethernet-phy@3 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;3&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_eqos_phy&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio4 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;500000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;50000&gt;;</div><div class='add'>+			enet-phy-lane-no-swap;</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+			interrupts = &lt;3 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+			ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_2_25_NS&gt;;</div><div class='add'>+			ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_2_25_NS&gt;;</div><div class='add'>+			ti,fifo-depth = &lt;DP83867_PHYCR_FIFO_DEPTH_4_B_NIB&gt;;</div><div class='add'>+			ti,dp83867-rxctrl-strap-quirk;</div><div class='add'>+			ti,clk-output-sel = &lt;DP83867_CLK_O_SEL_OFF&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	fsl,magic-packet;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@0 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_fec_phy&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio4 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;500000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;50000&gt;;</div><div class='add'>+			enet-phy-lane-no-swap;</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+			interrupts = &lt;1 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+			ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_2_25_NS&gt;;</div><div class='add'>+			ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_2_25_NS&gt;;</div><div class='add'>+			ti,fifo-depth = &lt;DP83867_PHYCR_FIFO_DEPTH_4_B_NIB&gt;;</div><div class='add'>+			ti,dp83867-rxctrl-strap-quirk;</div><div class='add'>+			ti,clk-output-sel = &lt;DP83867_CLK_O_SEL_OFF&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio1&gt;;</div><div class='add'>+</div><div class='add'>+	gpio-line-names = "WIFI_PMIC_EN", "LVDS_RESET#", "", "",</div><div class='add'>+			  "", "", "GPIO8", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "GPIO12", "GPIO13",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "";</div><div class='add'>+</div><div class='add'>+	wifi-pmic-en-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;0 0&gt;;</div><div class='add'>+		output-high;</div><div class='add'>+		line-name = "WIFI_PMIC_EN";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio2&gt;;</div><div class='add'>+</div><div class='add'>+	gpio-line-names = "GPIO22", "GPIO23", "GPIO24", "GPIO25",</div><div class='add'>+			  "GPIO26", "GPIO27", "CAM_GPIO1", "CAM_GPIO2",</div><div class='add'>+			  "", "", "GPIO1", "GPIO0",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio3&gt;;</div><div class='add'>+</div><div class='add'>+	gpio-line-names = "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "TEMP_EVENT#", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio4&gt;;</div><div class='add'>+</div><div class='add'>+	gpio-line-names = "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "HDMI_OC#", "GPIO14", "GPIO15", "GPIO16",</div><div class='add'>+			  "GPIO17", "PCIE_WAKE#", "GPIO19", "GPIO20",</div><div class='add'>+			  "PCIE_PERST#", "", "", "";</div><div class='add'>+</div><div class='add'>+	pewake-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;25 0&gt;;</div><div class='add'>+		input;</div><div class='add'>+		line-name = "PCIE_WAKE#";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio5 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio5&gt;, &lt;&amp;pinctrl_gpt1_gpio&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_gpt2_gpio&gt;, &lt;&amp;pinctrl_gpt3_gpio&gt;;</div><div class='add'>+</div><div class='add'>+	gpio-line-names = "", "GPIO18", "", "GPIO3",</div><div class='add'>+			  "GPIO2", "GPIO21", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "GPIO5", "GPIO6",</div><div class='add'>+			  "", "", "GPIO11", "GPIO10",</div><div class='add'>+			  "GPIO9", "GPIO7", "", "GPIO4",</div><div class='add'>+			  "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpt1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpt1&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpt2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpt2&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpt3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpt3&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_pvi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hdmi&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@1 {</div><div class='add'>+			hdmi_tx_out: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_connector_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* X5 + X6 Camera &amp; Display interface */</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;384000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c2_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* X1 ID_I2C */</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	clock-frequency = &lt;384000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c3_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio2 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio2 11 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	clock-frequency = &lt;384000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c4&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c4_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	tlv320aic3x04: audio-codec@18 {</div><div class='add'>+		compatible = "ti,tlv320aic32x4";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_tlv320aic3x04&gt;;</div><div class='add'>+		reg = &lt;0x18&gt;;</div><div class='add'>+		clock-names = "mclk";</div><div class='add'>+		clocks = &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio5 11 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		iov-supply = &lt;&amp;reg_vcc_3v3&gt;;</div><div class='add'>+		ldoin-supply = &lt;&amp;reg_vcc_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* X1 I2C */</div><div class='add'>+&amp;i2c5 {</div><div class='add'>+	clock-frequency = &lt;384000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c5&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c5_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* X1 I2C on GPIO24/GPIO25 */</div><div class='add'>+&amp;i2c6 {</div><div class='add'>+	clock-frequency = &lt;384000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c6&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c6_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio2 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio2 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcf85063 {</div><div class='add'>+	/* RTC_EVENT# is connected on MBa8MP-RAS314 */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcf85063&gt;;</div><div class='add'>+	interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+	interrupts = &lt;19 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	clocks = &lt;&amp;hsio_blk_ctrl&gt;;</div><div class='add'>+	clock-names = "ref";</div><div class='add'>+	fsl,refclk-pad-mode = &lt;IMX8_PCIE_REFCLK_PAD_OUTPUT&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie&gt;;</div><div class='add'>+	reset-gpios = &lt;&amp;gpio4 28 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm2&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_usdhc2_vqmmc {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai5 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai5&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_SAI5&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;12288000&gt;;</div><div class='add'>+	fsl,sai-mclk-direction-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;snvs_pwrkey {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* X1 UART1 */</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_UART1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL1_80M&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_UART2&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL1_80M&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "nxp,88w8987-bt";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_UART3&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL1_80M&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	/* console */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_0 {</div><div class='add'>+	fsl,disable-port-power-control;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_1 {</div><div class='add'>+	fsl,disable-port-power-control;</div><div class='add'>+	fsl,permanently-attached;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy0 {</div><div class='add'>+	vbus-supply = &lt;&amp;reg_vcc_5v0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy1 {</div><div class='add'>+	vbus-supply = &lt;&amp;reg_vcc_5v0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_0 {</div><div class='add'>+	dr_mode = "peripheral";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_1 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usbhub&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	hub_2_0: hub@1 {</div><div class='add'>+		compatible = "usb451,8142";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		peer-hub = &lt;&amp;hub_3_0&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio5 26 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;reg_vcc_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hub_3_0: hub@2 {</div><div class='add'>+		compatible = "usb451,8140";</div><div class='add'>+		reg = &lt;2&gt;;</div><div class='add'>+		peer-hub = &lt;&amp;hub_2_0&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio5 26 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;reg_vcc_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* X1 SD card on GPIO22-GPIO27 */</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	no-mmc;</div><div class='add'>+	no-sdio;</div><div class='add'>+	disable-wp;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_backlight: backlightgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03		0x14&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi3: ecspi3grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK		0x140&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI		0x140&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO		0x1c0&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25		0x140&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06		0x140&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi3_gpio: ecspi3gpiogrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_UART1_RXD__GPIO5_IO22		0x80&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23		0x80&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_UART2_RXD__GPIO5_IO24		0x80&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25		0x80&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06		0x80&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_eqos: eqosgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x40000044&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO			0x40000044&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x90&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x90&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x90&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x90&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x90&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x90&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x12&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x12&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x12&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x12&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x12&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x14&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_eqos_phy: eqosphygrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02				0x100&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03				0x1c0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec: fecgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x40000044&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x40000044&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0	0x90&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1	0x90&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2	0x90&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3	0x90&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC	0x90&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x90&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0	0x12&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1	0x12&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2	0x12&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3	0x12&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x12&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC	0x14&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec_phy: fecphygrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00		0x100&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01		0x1c0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpioled: gpioledgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18		0x14&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19		0x14&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio1: gpio1grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00		0x14&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01		0x14&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio2: gpio2grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SD1_CLK__GPIO2_IO00		0x94&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD1_CMD__GPIO2_IO01		0x94&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02		0x94&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD1_DATA1__GPIO2_IO03		0x94&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD1_DATA2__GPIO2_IO04		0x94&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD1_DATA3__GPIO2_IO05		0x94&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06		0x94&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07		0x94&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio3: gpio3grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20		0x180&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio4: gpio4grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20		0x80&gt;,</div><div class='add'>+			   /* PCIE_WAKE# */</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25		0x180&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26		0x94&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27		0x94&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio5: gpio5grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01		0x80&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05	0x80&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_hdmi: hdmigrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL	0x400001c2&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA	0x400001c2&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD	0x40000010&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC	0x40000154&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpt1: gpt1grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_UART3_TXD__GPT1_CLK		0x14&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpt1_gpio: gpt1gpiogrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_UART3_TXD__GPIO5_IO27		0x80&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpt2: gpt2grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_I2C3_SCL__GPT2_CLK		0x14&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpt2_gpio: gpt2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18		0x80&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpt3: gpt3grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_I2C3_SDA__GPT3_CLK		0x14&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpt3_gpio: gpt3gpiogrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19		0x80&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001e2&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA		0x400001e2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2_gpio: i2c2-gpiogrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16		0x400001e2&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17		0x400001e2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SD1_RESET_B__I2C3_SCL		0x400001e2&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD1_STROBE__I2C3_SDA		0x400001e2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3_gpio: i2c3-gpiogrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10	0x400001e2&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11		0x400001e2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4: i2c4grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_ECSPI2_MISO__I2C4_SCL		0x400001e2&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ECSPI2_SS0__I2C4_SDA		0x400001e2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4_gpio: i2c4-gpiogrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12	0x400001e2&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13		0x400001e2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c5: i2c5grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL		0x400001e2&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA		0x400001e2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c5_gpio: i2c5-gpiogrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03		0x400001e2&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04		0x400001e2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c6: i2c6grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SD1_DATA0__I2C6_SCL		0x400001e2&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD1_DATA1__I2C6_SDA		0x400001e2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c6_gpio: i2c6-gpiogrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02		0x400001e2&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD1_DATA1__GPIO2_IO03		0x400001e2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcf85063: pcf85063grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19		0x80&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie: pciegrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B	0x60&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28		0x94&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lvdsdisplay: lvdsdisplaygrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07		0x10&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm2: pwm2grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_GPIO1_IO09__PWM2_OUT		0x14&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm3: pwm3grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_GPIO1_IO14__PWM3_OUT		0x14&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm3_gpio: pwm3grpiogrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14		0x80&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm4: pwm4grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_GPIO1_IO15__PWM4_OUT		0x14&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm4_gpio: pwm4grpiogrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15		0x80&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_rfkill: rfkillgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02		0x14&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai5: sai5grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI5_MCLK		0x94&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI5_RX_DATA00	0x94&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_TX_DATA00	0x94&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC	0x94&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK	0x94&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_tlv320aic3x04: tlv320aic3x04grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_ECSPI2_MOSI__GPIO5_IO11		0x180&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX	0x14&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX		0x14&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI2_RXD0__UART1_DTE_CTS	0x14&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI2_TXFS__UART1_DTE_RTS	0x14&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1_gpio: uart1gpiogrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21		0x80&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22		0x80&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23		0x80&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24		0x80&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SAI3_TXC__UART2_DCE_TX		0x14&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI3_TXFS__UART2_DCE_RX	0x14&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS	0x14&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS	0x14&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: uart3grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX	0x140&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX	0x140&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart4: uart4grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX	0x140&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX	0x140&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usbhub: usbhubgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26		0x10&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x192&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d2&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d2&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d2&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d2&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x192&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d2&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d2&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d2&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d2&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x194&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x194&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2-gpiogrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12		0x1c0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtso b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtso<br/>new file mode 100644<br/>index 000000000000..5058cd9409c7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtso</a></div><div class='hunk'>@@ -0,0 +1,77 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2023 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Alexander Stein</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/imx8mp-clock.h&gt;</div><div class='add'>+</div><div class='add'>+&amp;{/} {</div><div class='add'>+	compatible = "tq,imx8mp-tqma8mpql-mba8mpxl", "tq,imx8mp-tqma8mpql", "fsl,imx8mp";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;backlight_lvds {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;display {</div><div class='add'>+	compatible = "auo,g133han01";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		port@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			dual-lvds-odd-pixels;</div><div class='add'>+</div><div class='add'>+			panel_in_lvds0: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;ldb_lvds_ch0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			dual-lvds-even-pixels;</div><div class='add'>+</div><div class='add'>+			panel_in_lvds1: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;ldb_lvds_ch1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lvds_bridge {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_MEDIA_LDB&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MP_VIDEO_PLL1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_VIDEO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;0&gt;, &lt;988400000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@1 {</div><div class='add'>+			ldb_lvds_ch0: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;panel_in_lvds0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@2 {</div><div class='add'>+			ldb_lvds_ch1: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;panel_in_lvds1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl-lvds-tm070jvhg33.dtso b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl-lvds-tm070jvhg33.dtso<br/>new file mode 100644<br/>index 000000000000..ea44d605342b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl-lvds-tm070jvhg33.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl-lvds-tm070jvhg33.dtso</a></div><div class='hunk'>@@ -0,0 +1,61 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2022 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Alexander Stein</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+&amp;{/} {</div><div class='add'>+	compatible = "tq,imx8mp-tqma8mpql-mba8mpxl", "tq,imx8mp-tqma8mpql", "fsl,imx8mp";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;backlight_lvds {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;display {</div><div class='add'>+	compatible = "tianma,tm070jvhg33";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	panel-timing {</div><div class='add'>+		clock-frequency = &lt;74250000&gt;;</div><div class='add'>+		hactive = &lt;1280&gt;;</div><div class='add'>+		vactive = &lt;800&gt;;</div><div class='add'>+		hfront-porch = &lt;64&gt;;</div><div class='add'>+		hback-porch = &lt;5&gt;;</div><div class='add'>+		hsync-len = &lt;1&gt;;</div><div class='add'>+		vfront-porch = &lt;40&gt;;</div><div class='add'>+		vback-porch = &lt;2&gt;;</div><div class='add'>+		vsync-len = &lt;1&gt;;</div><div class='add'>+		de-active = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	port {</div><div class='add'>+		panel_in_lvds0: endpoint {</div><div class='add'>+			remote-endpoint = &lt;&amp;ldb_lvds_ch0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lvds_bridge {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@1 {</div><div class='add'>+			ldb_lvds_ch0: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;panel_in_lvds0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts<br/>new file mode 100644<br/>index 000000000000..59642a8a2c44<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts</a></div><div class='hunk'>@@ -0,0 +1,1021 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021-2022 TQ-Systems GmbH</div><div class='add'>+ * Author: Alexander Stein &lt;alexander.stein@tq-group.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/net/ti-dp83867.h&gt;</div><div class='add'>+#include &lt;dt-bindings/phy/phy-imx8-pcie.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pwm/pwm.h&gt;</div><div class='add'>+#include "imx8mp-tqma8mpql.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MPxL";</div><div class='add'>+	compatible = "tq,imx8mp-tqma8mpql-mba8mpxl", "tq,imx8mp-tqma8mpql", "fsl,imx8mp";</div><div class='add'>+	chassis-type = "embedded";</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart4;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	iio-hwmon {</div><div class='add'>+		compatible = "iio-hwmon";</div><div class='add'>+		io-channels = &lt;&amp;adc 0&gt;, &lt;&amp;adc 1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		mmc0 = &amp;usdhc3;</div><div class='add'>+		mmc1 = &amp;usdhc2;</div><div class='add'>+		mmc2 = &amp;usdhc1;</div><div class='add'>+		rtc0 = &amp;pcf85063;</div><div class='add'>+		rtc1 = &amp;snvs_rtc;</div><div class='add'>+		spi0 = &amp;flexspi;</div><div class='add'>+		spi1 = &amp;ecspi1;</div><div class='add'>+		spi2 = &amp;ecspi2;</div><div class='add'>+		spi3 = &amp;ecspi3;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	backlight_lvds: backlight {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_backlight&gt;;</div><div class='add'>+		pwms = &lt;&amp;pwm2 0 5000000 0&gt;;</div><div class='add'>+		brightness-levels = &lt;0 4 8 16 32 64 128 255&gt;;</div><div class='add'>+		default-brightness-level = &lt;7&gt;;</div><div class='add'>+		power-supply = &lt;&amp;reg_vcc_12v0&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;gpio3 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_xtal25: clk-xtal25 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;25000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	connector {</div><div class='add'>+		compatible = "gpio-usb-b-connector", "usb-b-connector";</div><div class='add'>+		type = "micro";</div><div class='add'>+		label = "X29";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usbcon0&gt;;</div><div class='add'>+		id-gpios = &lt;&amp;gpio1 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			usb_dr_connector: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;usb3_dwc&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fan0: pwm-fan {</div><div class='add'>+		compatible = "pwm-fan";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pwmfan&gt;;</div><div class='add'>+		fan-supply = &lt;&amp;reg_pwm_fan&gt;;</div><div class='add'>+		#cooling-cells = &lt;2&gt;;</div><div class='add'>+		/* typical 25 kHz -&gt; 40.000 nsec */</div><div class='add'>+		pwms = &lt;&amp;pwm3 0 40000 PWM_POLARITY_INVERTED&gt;;</div><div class='add'>+		cooling-levels = &lt;0 32 64 128 196 240&gt;;</div><div class='add'>+		pulses-per-revolution = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio5&gt;;</div><div class='add'>+		interrupts = &lt;18 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpiobutton&gt;;</div><div class='add'>+		autorepeat;</div><div class='add'>+</div><div class='add'>+		switch-1 {</div><div class='add'>+			label = "S12";</div><div class='add'>+			linux,code = &lt;BTN_0&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio5 27 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		switch-2 {</div><div class='add'>+			label = "S13";</div><div class='add'>+			linux,code = &lt;BTN_1&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio5 26 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpioled&gt;;</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			function-enumerator = &lt;0&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio5 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "default-on";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_HEARTBEAT;</div><div class='add'>+			gpios = &lt;&amp;gpio5 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-2 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_YELLOW&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			function-enumerator = &lt;1&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio5 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdmi-connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		label = "X44";</div><div class='add'>+		type = "a";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			hdmi_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_tx_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	display: display {</div><div class='add'>+		/*</div><div class='add'>+		 * Display is not fixed, so compatible has to be added from</div><div class='add'>+		 * DT overlay</div><div class='add'>+		 */</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_lvdsdisplay&gt;;</div><div class='add'>+		power-supply = &lt;&amp;reg_vcc_3v3&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;gpio3 20 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		backlight = &lt;&amp;backlight_lvds&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_pwm_fan: regulator-pwm-fan {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_regpwmfan&gt;;</div><div class='add'>+		regulator-name = "FAN_PWR";</div><div class='add'>+		regulator-min-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;12000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio4 27 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		vin-supply = &lt;&amp;reg_vcc_12v0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usdhc2_vmmc&gt;;</div><div class='add'>+		regulator-name = "VSD_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio2 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		startup-delay-us = &lt;100&gt;;</div><div class='add'>+		off-on-delay-us = &lt;12000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc_12v0: regulator-12v0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg12v0&gt;;</div><div class='add'>+		regulator-name = "VCC_12V0";</div><div class='add'>+		regulator-min-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;12000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio2 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc_1v8: regulator-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCC_1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc_3v3: regulator-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCC_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc_5v0: regulator-5v0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCC_5V0";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		/* global autoconfigured region for contiguous allocations */</div><div class='add'>+		linux,cma {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reusable;</div><div class='add'>+			size = &lt;0 0x38000000&gt;;</div><div class='add'>+			alloc-ranges = &lt;0 0x40000000 0 0xB0000000&gt;;</div><div class='add'>+			linux,cma-default;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "fsl,imx-audio-tlv320aic32x4";</div><div class='add'>+		model = "tqm-tlv320aic32";</div><div class='add'>+		audio-asrc = &lt;&amp;easrc&gt;;</div><div class='add'>+		audio-cpu = &lt;&amp;sai3&gt;;</div><div class='add'>+		audio-codec = &lt;&amp;tlv320aic3x04&gt;;</div><div class='add'>+		audio-routing =</div><div class='add'>+			"IN3_L", "Mic Jack",</div><div class='add'>+			"Mic Jack", "Mic Bias",</div><div class='add'>+			"IN1_L", "Line In Jack",</div><div class='add'>+			"IN1_R", "Line In Jack",</div><div class='add'>+			"Line Out Jack", "LOL",</div><div class='add'>+			"Line Out Jack", "LOR";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	thermal-zones {</div><div class='add'>+		soc-thermal {</div><div class='add'>+			trips {</div><div class='add'>+				soc_active0: trip-active0 {</div><div class='add'>+					temperature = &lt;40000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "active";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				soc_active1: trip-active1 {</div><div class='add'>+					temperature = &lt;48000&gt;;</div><div class='add'>+					hysteresis = &lt;3000&gt;;</div><div class='add'>+					type = "active";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				soc_active2: trip-active2 {</div><div class='add'>+					temperature = &lt;60000&gt;;</div><div class='add'>+					hysteresis = &lt;10000&gt;;</div><div class='add'>+					type = "active";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map1 {</div><div class='add'>+					trip = &lt;&amp;soc_active0&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;fan0 1 1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				map2 {</div><div class='add'>+					trip = &lt;&amp;soc_active1&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;fan0 2 2&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				map3 {</div><div class='add'>+					trip = &lt;&amp;soc_active2&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;fan0 3 3&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi1&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi2&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 13 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi3&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 25 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	adc: adc@0 {</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		compatible = "microchip,mcp3202";</div><div class='add'>+		/* 100 ksps * 18 */</div><div class='add'>+		spi-max-frequency = &lt;1800000&gt;;</div><div class='add'>+		vref-supply = &lt;&amp;reg_vcc_3v3&gt;;</div><div class='add'>+		#io-channel-cells = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eqos {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_eqos&gt;, &lt;&amp;pinctrl_eqos_phy&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy3: ethernet-phy@3 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;3&gt;;</div><div class='add'>+			ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_2_25_NS&gt;;</div><div class='add'>+			ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_2_25_NS&gt;;</div><div class='add'>+			ti,fifo-depth = &lt;DP83867_PHYCR_FIFO_DEPTH_4_B_NIB&gt;;</div><div class='add'>+			ti,dp83867-rxctrl-strap-quirk;</div><div class='add'>+			ti,clk-output-sel = &lt;DP83867_CLK_O_SEL_OFF&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio4 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;500000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;50000&gt;;</div><div class='add'>+			enet-phy-lane-no-swap;</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+			interrupts = &lt;3 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec&gt;, &lt;&amp;pinctrl_fec_phy&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	fsl,magic-packet;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@0 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_2_25_NS&gt;;</div><div class='add'>+			ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_2_25_NS&gt;;</div><div class='add'>+			ti,fifo-depth = &lt;DP83867_PHYCR_FIFO_DEPTH_4_B_NIB&gt;;</div><div class='add'>+			ti,dp83867-rxctrl-strap-quirk;</div><div class='add'>+			ti,clk-output-sel = &lt;DP83867_CLK_O_SEL_OFF&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio4 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;500000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;50000&gt;;</div><div class='add'>+			enet-phy-lane-no-swap;</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+			interrupts = &lt;1 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan1&gt;;</div><div class='add'>+	xceiver-supply = &lt;&amp;reg_vcc_3v3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan2&gt;;</div><div class='add'>+	xceiver-supply = &lt;&amp;reg_vcc_3v3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio1&gt;;</div><div class='add'>+</div><div class='add'>+	gpio-line-names = "GPO1", "GPO0", "", "GPO3",</div><div class='add'>+			  "", "", "GPO2", "GPI0",</div><div class='add'>+			  "PMIC_IRQ", "GPI1", "OTG_ID", "USB_HUB_RST#",</div><div class='add'>+			  "OTG_PWR", "", "GPI2", "GPI3",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hoggpio2&gt;;</div><div class='add'>+</div><div class='add'>+	gpio-line-names = "", "", "", "",</div><div class='add'>+			  "", "", "VCC12V_EN", "PERST#",</div><div class='add'>+			  "", "", "CLKREQ#", "PEWAKE#",</div><div class='add'>+			  "USDHC2_CD", "", "", "",</div><div class='add'>+			  "", "", "", "V_SD3V3_EN",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "";</div><div class='add'>+</div><div class='add'>+	perst-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;7 0&gt;;</div><div class='add'>+		output-high;</div><div class='add'>+		line-name = "PERST#";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clkreq-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;10 0&gt;;</div><div class='add'>+		input;</div><div class='add'>+		line-name = "CLKREQ#";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pewake-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;11 0&gt;;</div><div class='add'>+		input;</div><div class='add'>+		line-name = "PEWAKE#";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio3 {</div><div class='add'>+	gpio-line-names = "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "LVDS0_RESET#", "",</div><div class='add'>+			  "", "", "", "LVDS0_BLT_EN",</div><div class='add'>+			  "LVDS0_PWR_EN", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio4&gt;;</div><div class='add'>+</div><div class='add'>+	gpio-line-names = "ENET0_RST#", "ENET0_INT#", "ENET1_RST#", "ENET1_INT#",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "DP_IRQ", "DSI_EN",</div><div class='add'>+			  "HDMI_OC#", "TEMP_EVENT#", "PCIE_REFCLK_OE#", "",</div><div class='add'>+			  "", "", "", "FAN_PWR",</div><div class='add'>+			  "RTC_EVENT#", "CODEC_RST#", "", "";</div><div class='add'>+</div><div class='add'>+	pcie-refclkreq-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;22 0&gt;;</div><div class='add'>+		output-high;</div><div class='add'>+		line-name = "PCIE_REFCLK_OE#";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio5 {</div><div class='add'>+	gpio-line-names = "", "", "", "LED2",</div><div class='add'>+			  "LED1", "LED0", "CSI0_RESET#", "CSI0_SYNC",</div><div class='add'>+			  "CSI0_TRIGGER", "CSI0_ENABLE", "", "",</div><div class='add'>+			  "", "ECSPI2_SS0", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "ECSPI3_SS0", "SWITCH_A", "SWITCH_B",</div><div class='add'>+			  "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_pvi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hdmi&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@1 {</div><div class='add'>+			hdmi_tx_out: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_connector_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;384000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c2_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	tlv320aic3x04: audio-codec@18 {</div><div class='add'>+		compatible = "ti,tlv320aic32x4";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_tlv320aic3x04&gt;;</div><div class='add'>+		reg = &lt;0x18&gt;;</div><div class='add'>+		clock-names = "mclk";</div><div class='add'>+		clocks = &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio4 29 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		iov-supply = &lt;&amp;reg_vcc_1v8&gt;;</div><div class='add'>+		ldoin-supply = &lt;&amp;reg_vcc_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	se97_1c: temperature-sensor@1c {</div><div class='add'>+		compatible = "nxp,se97b", "jedec,jc-42.4-temp";</div><div class='add'>+		reg = &lt;0x1c&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	at24c02_54: eeprom@54 {</div><div class='add'>+		compatible = "nxp,se97b", "atmel,24c02";</div><div class='add'>+		reg = &lt;0x54&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_vcc_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcieclk: clock-generator@6a {</div><div class='add'>+		compatible = "renesas,9fgv0241";</div><div class='add'>+		reg = &lt;0x6a&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk_xtal25&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	clock-frequency = &lt;384000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c4&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c4_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c6 {</div><div class='add'>+	clock-frequency = &lt;384000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c6&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c6_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio2 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio2 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcf85063 {</div><div class='add'>+	/* RTC_EVENT# is connected on MBa8MPxL */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcf85063&gt;;</div><div class='add'>+	interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+	interrupts = &lt;28 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	fsl,clkreq-unsupported;</div><div class='add'>+	fsl,refclk-pad-mode = &lt;IMX8_PCIE_REFCLK_PAD_INPUT&gt;;</div><div class='add'>+	clocks = &lt;&amp;pcieclk 0&gt;;</div><div class='add'>+	clock-names = "ref";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie {</div><div class='add'>+	clocks = &lt;&amp;clk IMX8MP_CLK_HSIO_ROOT&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX8MP_CLK_HSIO_AXI&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX8MP_CLK_PCIE_ROOT&gt;;</div><div class='add'>+	clock-names = "pcie", "pcie_bus", "pcie_aux";</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_PCIE_AUX&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;10000000&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL2_50M&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm2&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_usdhc2_vqmmc {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai3&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_SAI3&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;12288000&gt;;</div><div class='add'>+	fsl,sai-mclk-direction-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;snvs_pwrkey {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_UART1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL1_80M&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_UART2&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL1_80M&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_UART3&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL1_80M&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	/* console */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usb0&gt;;</div><div class='add'>+	fsl,over-current-active-low;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_1 {</div><div class='add'>+	fsl,disable-port-power-control;</div><div class='add'>+	fsl,permanently-attached;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy0 {</div><div class='add'>+	vbus-supply = &lt;&amp;reg_vcc_5v0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy1 {</div><div class='add'>+	vbus-supply = &lt;&amp;reg_vcc_5v0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_0 {</div><div class='add'>+	/* dual role is implemented, but not a full featured OTG */</div><div class='add'>+	hnp-disable;</div><div class='add'>+	srp-disable;</div><div class='add'>+	adp-disable;</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	role-switch-default-mode = "peripheral";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	port {</div><div class='add'>+		usb3_dwc: endpoint {</div><div class='add'>+			remote-endpoint = &lt;&amp;usb_dr_connector&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_1 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usbhub&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	hub_2_0: hub@1 {</div><div class='add'>+		compatible = "usb451,8142";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		peer-hub = &lt;&amp;hub_3_0&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio1 11 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;reg_vcc_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hub_3_0: hub@2 {</div><div class='add'>+		compatible = "usb451,8140";</div><div class='add'>+		reg = &lt;2&gt;;</div><div class='add'>+		peer-hub = &lt;&amp;hub_2_0&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio1 11 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;reg_vcc_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	no-mmc;</div><div class='add'>+	no-sdio;</div><div class='add'>+	disable-wp;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_backlight: backlightgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19		0x14&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan1: flexcan1grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX		0x150&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX		0x150&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan2: flexcan2grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX		0x150&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX		0x150&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* only on X57, primary used as CSI0 control signals */</div><div class='add'>+	pinctrl_ecspi1: ecspi1grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO	0x1c0&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI	0x1c0&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK	0x1c0&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09		0x1c0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* on X63 and optionally on X57, can also be used as CSI1 control signals */</div><div class='add'>+	pinctrl_ecspi2: ecspi2grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO	0x1c0&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI	0x1c0&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK	0x1c0&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13		0x1c0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi3: ecspi3grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI		0x1c0&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK		0x1c0&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO		0x1c0&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25		0x1c0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_eqos: eqosgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x40000044&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO			0x40000044&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x90&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x90&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x90&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x90&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x90&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x90&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x12&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x12&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x12&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x12&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x12&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x14&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_eqos_event: eqosevtgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SAI2_RXD0__ENET_QOS_1588_EVENT2_OUT		0x100&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_EVENT2_IN		0x1c0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_eqos_phy: eqosphygrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02				0x100&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03				0x1c0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec: fecgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x40000044&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x40000044&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0	0x90&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1	0x90&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2	0x90&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3	0x90&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC	0x90&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x90&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0	0x12&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1	0x12&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2	0x12&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3	0x12&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x12&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC	0x14&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec_event: fecevtgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN	0x100&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT	0x1c0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec_phy: fecphygrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00		0x100&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01		0x1c0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec_phyalt: fecphyaltgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24		0x180&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25		0x180&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpiobutton: gpiobuttongrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26		0x10&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_UART3_TXD__GPIO5_IO27		0x10&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpioled: gpioledgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05	0x14&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04		0x14&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03		0x14&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio1: gpio1grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00		0x10&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01		0x10&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03		0x10&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06		0x10&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07		0x80&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09		0x80&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14		0x80&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15		0x80&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio4: gpio4grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20		0x180&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22		0x180&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_hdmi: hdmigrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL	0x400001c2&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA	0x400001c2&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD	0x40000010&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC	0x40000010&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_hoggpio2: hoggpio2grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07		0x140&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10	0x140&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11		0x140&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001e2&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA		0x400001e2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2_gpio: i2c2-gpiogrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16		0x400001e2&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17		0x400001e2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4: i2c4grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL		0x400001e2&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA		0x400001e2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4_gpio: i2c4-gpiogrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20		0x400001e2&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21		0x400001e2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c6: i2c6grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SD1_DATA0__I2C6_SCL		0x400001e2&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD1_DATA1__I2C6_SDA		0x400001e2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c6_gpio: i2c6-gpiogrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02		0x400001e2&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD1_DATA1__GPIO2_IO03		0x400001e2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lvdsdisplay: lvdsdisplaygrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20		0x10&gt;; /* Power enable */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcf85063: pcf85063grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28		0x80&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* LVDS Backlight */</div><div class='add'>+	pinctrl_pwm2: pwm2grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT		0x14&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* FAN */</div><div class='add'>+	pinctrl_pwm3: pwm3grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_I2C3_SDA__PWM3_OUT		0x14&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwmfan: pwmfangrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18		0x80&gt;; /* FAN RPM */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg12v0: reg12v0grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06		0x140&gt;; /* VCC12V enable */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_regpwmfan: regpwmfangrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27		0x80&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai3: sai3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC	0x94</div><div class='add'>+			MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK	0x94</div><div class='add'>+			MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00	0x94</div><div class='add'>+			MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00	0x94</div><div class='add'>+			MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK	0x94</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_tlv320aic3x04: tlv320aic3x04grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* CODEC RST# */</div><div class='add'>+			MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29		0x180</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* X61 */</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX		0x140&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX		0x140&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* X61 */</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SD1_DATA2__UART2_DCE_TX	0x140&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD1_DATA3__UART2_DCE_RX	0x140&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: uart3grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX	0x140&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX	0x140&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart4: uart4grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX	0x140&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX	0x140&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usb0: usb0grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC	0x1c0&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR	0x1c0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usbcon0: usb0congrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10		0x1c0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usbhub: usbhubgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11		0x10&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x192&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d2&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d2&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d2&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d2&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x194&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x194&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2-gpiogrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12		0x1c0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi<br/>new file mode 100644<br/>index 000000000000..9716f24f7c6e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi</a></div><div class='hunk'>@@ -0,0 +1,297 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021-2025 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Alexander Stein</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "imx8mp.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "TQ-Systems i.MX8MPlus TQMa8MPxL";</div><div class='add'>+	compatible = "tq,imx8mp-tqma8mpql", "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x40000000 0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc {</div><div class='add'>+		compatible = "regulator-gpio";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usdhc2_vqmmc&gt;;</div><div class='add'>+		regulator-name = "V_SD2";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpios = &lt;&amp;gpio1 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		states = &lt;1800000 0x1&gt;,</div><div class='add'>+			 &lt;3300000 0x0&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;ldo5_reg&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;easrc {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexspi {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexspi0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash0: flash@0 {</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		spi-max-frequency = &lt;80000000&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;1&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;buck5_reg&gt;;</div><div class='add'>+</div><div class='add'>+		partitions {</div><div class='add'>+			compatible = "fixed-partitions";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;384000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c1_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	se97: temperature-sensor@1b {</div><div class='add'>+		compatible = "nxp,se97b", "jedec,jc-42.4-temp";</div><div class='add'>+		reg = &lt;0x1b&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmic: pmic@25 {</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+		compatible = "nxp,pca9450c";</div><div class='add'>+</div><div class='add'>+		/* PMIC PCA9450 PMIC_nINT GPIO1_IO08 */</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;8 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			/* V_0V85_SOC: 0.85 .. 0.95 */</div><div class='add'>+			buck1_reg: BUCK1 {</div><div class='add'>+				regulator-name = "BUCK1";</div><div class='add'>+				regulator-min-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;950000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* VDD_ARM */</div><div class='add'>+			buck2_reg: BUCK2 {</div><div class='add'>+				regulator-name = "BUCK2";</div><div class='add'>+				regulator-min-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				nxp,dvs-run-voltage = &lt;950000&gt;;</div><div class='add'>+				nxp,dvs-standby-voltage = &lt;850000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* VCC3V3 -&gt; VMMC, ... must not be changed */</div><div class='add'>+			buck4_reg: BUCK4 {</div><div class='add'>+				regulator-name = "BUCK4";</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* V_1V8 -&gt; VQMMC, SPI-NOR, ... must not be changed */</div><div class='add'>+			buck5_reg: BUCK5 {</div><div class='add'>+				regulator-name = "BUCK5";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* V_1V1 -&gt; RAM, ... must not be changed */</div><div class='add'>+			buck6_reg: BUCK6 {</div><div class='add'>+				regulator-name = "BUCK6";</div><div class='add'>+				regulator-min-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* V_1V8_SNVS */</div><div class='add'>+			ldo1_reg: LDO1 {</div><div class='add'>+				regulator-name = "LDO1";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* V_1V8_ANA */</div><div class='add'>+			ldo3_reg: LDO3 {</div><div class='add'>+				regulator-name = "LDO3";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* unused */</div><div class='add'>+			ldo4_reg: LDO4 {</div><div class='add'>+				regulator-name = "LDO4";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* VCC SD IO - switched using SD2 VSELECT */</div><div class='add'>+			ldo5_reg: LDO5 {</div><div class='add'>+				regulator-name = "LDO5";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcf85063: rtc@51 {</div><div class='add'>+		compatible = "nxp,pcf85063a";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	at24c02: eeprom@53 {</div><div class='add'>+		compatible = "nxp,se97b", "atmel,24c02";</div><div class='add'>+		read-only;</div><div class='add'>+		reg = &lt;0x53&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;buck4_reg&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	m24c64: eeprom@57 {</div><div class='add'>+		compatible = "atmel,24c64";</div><div class='add'>+		reg = &lt;0x57&gt;;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;buck4_reg&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_usdhc2_vqmmc&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	no-sd;</div><div class='add'>+	no-sdio;</div><div class='add'>+	vmmc-supply = &lt;&amp;buck4_reg&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;buck5_reg&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_flexspi0: flexspi0grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK	0x142&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B	0x82&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00	0x82&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01	0x82&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02	0x82&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03	0x82&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001e2&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001e2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1_gpio: i2c1-gpiogrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14		0x400001e2&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15		0x400001e2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: pmicirqgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08		0x1c0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x10&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usdhc2_vqmmc: regusdhc2vqmmcgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04		0xc0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x84&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x84&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x84&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x84&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x84&gt;,</div><div class='add'>+			   &lt;MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x84&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B	0x1c4&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dtso b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dtso<br/>new file mode 100644<br/>index 000000000000..e3965caca6be<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dtso</a></div><div class='hunk'>@@ -0,0 +1,94 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2025 GOcontroll B.V.</div><div class='add'>+ * Author: Maud Spierings &lt;maudspierings@gocontroll.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/imx8mp-clock.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+</div><div class='add'>+#include "imx8mp-pinfunc.h"</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+&amp;{/} {</div><div class='add'>+	model = "GOcontroll Moduline Display with BOE av101hdt-a10 display";</div><div class='add'>+</div><div class='add'>+	panel {</div><div class='add'>+		compatible = "boe,av101hdt-a10";</div><div class='add'>+		enable-gpios = &lt;&amp;gpio1 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_panel&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		power-supply = &lt;&amp;reg_3v3_per&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio1 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			panel_lvds_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;ldb_lvds_ch0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vbus: regulator-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		power-supply = &lt;&amp;reg_6v4&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-name = "usb-c-vbus";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_panel: panelgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07</div><div class='add'>+				MX8MP_DSE_X1</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09</div><div class='add'>+				MX8MP_DSE_X1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lvds_bridge {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_MEDIA_LDB&gt;, &lt;&amp;clk IMX8MP_VIDEO_PLL1&gt;;</div><div class='add'>+	/* IMX8MP_VIDEO_PLL1 = IMX8MP_CLK_MEDIA_DISP2_PIX * 2 * 7 */</div><div class='add'>+	assigned-clock-rates = &lt;0&gt;, &lt;1054620000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@1 {</div><div class='add'>+			ldb_lvds_ch0: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;panel_lvds_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_1 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+</div><div class='add'>+	connector {</div><div class='add'>+		compatible = "usb-c-connector";</div><div class='add'>+		data-role = "host";</div><div class='add'>+		pd-disable;</div><div class='add'>+		vbus-supply = &lt;&amp;reg_vbus&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			high_speed_ep: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;usb1_hs_ep&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	port {</div><div class='add'>+		usb1_hs_ep: endpoint {</div><div class='add'>+			remote-endpoint = &lt;&amp;high_speed_ep&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av123z7m-n17.dtso b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av123z7m-n17.dtso<br/>new file mode 100644<br/>index 000000000000..3eb665ce9d5d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av123z7m-n17.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av123z7m-n17.dtso</a></div><div class='hunk'>@@ -0,0 +1,139 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2025 GOcontroll B.V.</div><div class='add'>+ * Author: Maud Spierings &lt;maudspierings@gocontroll.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+</div><div class='add'>+#include "imx8mp-pinfunc.h"</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+&amp;{/} {</div><div class='add'>+	model = "GOcontroll Moduline Display with BOE av123z7m-n17 display";</div><div class='add'>+</div><div class='add'>+	panel {</div><div class='add'>+		compatible = "boe,av123z7m-n17";</div><div class='add'>+		enable-gpios = &lt;&amp;gpio1 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_panel&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		power-supply = &lt;&amp;reg_3v3_per&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio1 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				dual-lvds-odd-pixels;</div><div class='add'>+</div><div class='add'>+				panel_in0: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;lvds1_out&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				dual-lvds-even-pixels;</div><div class='add'>+</div><div class='add'>+				panel_in1: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;lvds0_out&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	/* sn65dsi85 */</div><div class='add'>+	bridge@2d {</div><div class='add'>+		compatible = "ti,sn65dsi84";</div><div class='add'>+		reg = &lt;0x2d&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;gpio4 14 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_lvds_bridge&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		vcc-supply = &lt;&amp;reg_1v8_per&gt;;</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				dsi_lvds_bridge_in: endpoint {</div><div class='add'>+					data-lanes = &lt;1 2 3 4&gt;;</div><div class='add'>+					remote-endpoint = &lt;&amp;mipi_dsi_out&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@2 {</div><div class='add'>+				reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+				lvds0_out: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;panel_in1&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@3 {</div><div class='add'>+				reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+				lvds1_out: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;panel_in0&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* max25014 @ 0x6f */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_lvds_bridge: lvdsbridgegrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14</div><div class='add'>+				MX8MP_DSE_X1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_panel: panelgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07</div><div class='add'>+				MX8MP_DSE_X1</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09</div><div class='add'>+				MX8MP_DSE_X1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_dsi {</div><div class='add'>+	/*</div><div class='add'>+	 * burst has to be at least 2x dsi clock that the sn65dsi85 expects</div><div class='add'>+	 * display pixelclock * bpp / lanes / 2 = dsi clock</div><div class='add'>+	 * 88.000.000 * 24 / 4 / 2 = 264.000.000</div><div class='add'>+	 * range gets rounded up to 265.000.000 - 270.000.000</div><div class='add'>+	 * 267.500.000 * 2 = 535.000.000</div><div class='add'>+	 */</div><div class='add'>+	samsung,burst-clock-frequency = &lt;535000000&gt;;</div><div class='add'>+	samsung,esc-clock-frequency = &lt;12000000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@1 {</div><div class='add'>+			mipi_dsi_out: endpoint {</div><div class='add'>+				data-lanes = &lt;1 2 3 4&gt;;</div><div class='add'>+				remote-endpoint = &lt; &amp;dsi_lvds_bridge_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106.dts b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106.dts<br/>new file mode 100644<br/>index 000000000000..88ad422c2760<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106.dts</a></div><div class='hunk'>@@ -0,0 +1,525 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2025 GOcontroll B.V.</div><div class='add'>+ * Author: Maud Spierings &lt;maudspierings@gocontroll.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mp-tx8p-ml81.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "gocontroll,moduline-display", "fsl,imx8mp";</div><div class='add'>+	chassis-type = "embedded";</div><div class='add'>+	hardware = "Moduline Display V1.06";</div><div class='add'>+	model = "GOcontroll Moduline Display baseboard";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		can0 = &amp;flexcan1;</div><div class='add'>+		can1 = &amp;flexcan2;</div><div class='add'>+		ethernet0 = &amp;eqos;</div><div class='add'>+		ethernet1 = &amp;fec;</div><div class='add'>+		mmc0 = &amp;usdhc3;</div><div class='add'>+		mmc1 = &amp;usdhc2;</div><div class='add'>+		rtc0 = &amp;rtc_pcf; /* i2c rtc is the main rtc */</div><div class='add'>+		rtc1 = &amp;snvs_rtc;</div><div class='add'>+		spi0 = &amp;ecspi2; /* spidev number compatibility */</div><div class='add'>+		spi1 = &amp;ecspi1; /* spidev number compatibility */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	external-sensor-supply {</div><div class='add'>+		compatible = "regulator-output";</div><div class='add'>+		vout-supply = &lt;&amp;reg_5v0_sensor&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	flexcan1_phy: can-phy0 {</div><div class='add'>+		compatible = "ti,tcan1051", "ti,tcan1042";</div><div class='add'>+		#phy-cells = &lt;0&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_flexcan1_stby&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		max-bitrate = &lt;5000000&gt;;</div><div class='add'>+		standby-gpios = &lt;&amp;gpio4 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	flexcan2_phy: can-phy1 {</div><div class='add'>+		compatible = "ti,tcan1051", "ti,tcan1042";</div><div class='add'>+		#phy-cells = &lt;0&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_flexcan2_stby&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		max-bitrate = &lt;5000000&gt;;</div><div class='add'>+		standby-gpios = &lt;&amp;gpio5 9 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_1v8_per: regulator-1v8-per {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_1v8&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		power-supply = &lt;&amp;reg_3v3_per&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-name = "1v8-per";</div><div class='add'>+		gpio = &lt;&amp;gpio3 25 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3v3_per: regulator-3v3-per {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		power-supply = &lt;&amp;reg_6v4&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "3v3-per";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_5v0: regulator-5v0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		power-supply = &lt;&amp;reg_6v4&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-name = "5v0";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_5v0_sensor: regulator-5v0-sensor {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_5v0_sensor&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-name = "5v0-supply-external-sensor";</div><div class='add'>+		gpio = &lt;&amp;gpio4 9 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_6v4: regulator-6v4 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-max-microvolt = &lt;6400000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;6400000&gt;;</div><div class='add'>+		regulator-name = "6v4";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,bitclock-master = &lt;&amp;cpudai&gt;;</div><div class='add'>+		simple-audio-card,format = "i2s";</div><div class='add'>+		simple-audio-card,frame-master = &lt;&amp;cpudai&gt;;</div><div class='add'>+		simple-audio-card,name = "tas2505-audio";</div><div class='add'>+		simple-audio-card,routing = "Speaker", "DAC";</div><div class='add'>+		simple-audio-card,widgets = "Speaker", "Speaker External";</div><div class='add'>+</div><div class='add'>+		simple-audio-card,codec {</div><div class='add'>+			sound-dai = &lt;&amp;tas2505&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpudai: simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;sai6&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wifi_powerseq: wifi-powerseq {</div><div class='add'>+		compatible = "mmc-pwrseq-simple";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_wl_reg&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		post-power-on-delay-ms = &lt;100&gt;;</div><div class='add'>+		power-off-delay-us = &lt;500000&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio2 19 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi1 {</div><div class='add'>+	cs-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;,</div><div class='add'>+		   &lt;&amp;gpio1 11 GPIO_ACTIVE_LOW&gt;,</div><div class='add'>+		   &lt;&amp;gpio1 10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi1&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	connector@0 {</div><div class='add'>+		compatible = "gocontroll,moduline-module-slot";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;5 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		i2c-bus = &lt;&amp;i2c2&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio5 10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		slot-number = &lt;1&gt;;</div><div class='add'>+		spi-max-frequency = &lt;54000000&gt;;</div><div class='add'>+		sync-gpios = &lt;&amp;gpio4 16 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		vddhpp-supply = &lt;&amp;reg_6v4&gt;;</div><div class='add'>+		vddp-supply = &lt;&amp;reg_5v0&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;reg_3v3_per&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	connector@1 {</div><div class='add'>+		compatible = "gocontroll,moduline-module-slot";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;0 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		i2c-bus = &lt;&amp;i2c2&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio1 8 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		slot-number = &lt;2&gt;;</div><div class='add'>+		spi-max-frequency = &lt;54000000&gt;;</div><div class='add'>+		sync-gpios = &lt;&amp;gpio4 16 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		vddhpp-supply = &lt;&amp;reg_6v4&gt;;</div><div class='add'>+		vddp-supply = &lt;&amp;reg_5v0&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;reg_3v3_per&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	adc@2 {</div><div class='add'>+		compatible = "microchip,mcp3004";</div><div class='add'>+		reg = &lt;2&gt;;</div><div class='add'>+		spi-max-frequency = &lt;2300000&gt;;</div><div class='add'>+		vref-supply = &lt;&amp;reg_vdd_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	phys = &lt;&amp;flexcan1_phy&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan1&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan2 {</div><div class='add'>+	phys = &lt;&amp;flexcan2_phy&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan2&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c2_gpio&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c4&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c4_gpio&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	tas2505: audio-codec@18 {</div><div class='add'>+		compatible = "ti,tas2505";</div><div class='add'>+		reg = &lt;0x18&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1&gt;;</div><div class='add'>+		clock-names = "mclk";</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		aic32x4-gpio-func = &lt;0xff 0xff 0xff 0xff 0xff&gt;;</div><div class='add'>+		av-supply = &lt;&amp;reg_1v8_per&gt;;</div><div class='add'>+		dv-supply = &lt;&amp;reg_1v8_per&gt;;</div><div class='add'>+		iov-supply = &lt;&amp;reg_vdd_3v3&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_tas_reset&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		reset-gpios = &lt;&amp;gpio3 24 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rtc_pcf: rtc@51 {</div><div class='add'>+		compatible = "nxp,pcf85063a";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		quartz-load-femtofarads = &lt;7000&gt;;</div><div class='add'>+</div><div class='add'>+		clock {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-frequency = &lt;32768&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_bt: btgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14</div><div class='add'>+				MX8MP_DSE_X1</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12</div><div class='add'>+				(MX8MP_PULL_UP | MX8MP_PULL_ENABLE | MX8MP_HYS_SCHMITT)</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15</div><div class='add'>+				MX8MP_DSE_X1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi1: ecspi1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI</div><div class='add'>+				MX8MP_DSE_X4</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO</div><div class='add'>+				(MX8MP_DSE_X4 | MX8MP_HYS_SCHMITT)</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK</div><div class='add'>+				MX8MP_DSE_X4</div><div class='add'>+			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12</div><div class='add'>+				MX8MP_DSE_X1</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11</div><div class='add'>+				MX8MP_DSE_X1</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10</div><div class='add'>+				MX8MP_DSE_X1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan1: flexcan1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			 MX8MP_IOMUXC_SPDIF_RX__CAN1_RX</div><div class='add'>+				 (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)</div><div class='add'>+			 MX8MP_IOMUXC_SPDIF_TX__CAN1_TX</div><div class='add'>+				 (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan1_stby: flexcan1stbygrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03</div><div class='add'>+				(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan2: flexcan2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART3_TXD__CAN2_RX</div><div class='add'>+				(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)</div><div class='add'>+			MX8MP_IOMUXC_UART3_RXD__CAN2_TX</div><div class='add'>+				(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan2_stby: flexcan2stbygrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09</div><div class='add'>+				(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL</div><div class='add'>+				MX8MP_I2C_DEFAULT</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA</div><div class='add'>+				MX8MP_I2C_DEFAULT</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2_gpio: i2c2-gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16</div><div class='add'>+				MX8MP_I2C_DEFAULT</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17</div><div class='add'>+				MX8MP_I2C_DEFAULT</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4: i2c4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_MISO__I2C4_SCL</div><div class='add'>+				MX8MP_I2C_DEFAULT</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_SS0__I2C4_SDA</div><div class='add'>+				MX8MP_I2C_DEFAULT</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4_gpio: i2c4-gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12</div><div class='add'>+				MX8MP_I2C_DEFAULT</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13</div><div class='add'>+				MX8MP_I2C_DEFAULT</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: pinctrlusdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK</div><div class='add'>+				(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_ENABLE)</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD</div><div class='add'>+				(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0</div><div class='add'>+				(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1</div><div class='add'>+				(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2</div><div class='add'>+				(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3</div><div class='add'>+				(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_1v8: reg-1v8-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25</div><div class='add'>+				MX8MP_DSE_X1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_5v0_sensor: reg-5v0-sensorgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD7__GPIO4_IO09</div><div class='add'>+				MX8MP_DSE_X1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai6: sai6grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI6_TX_SYNC</div><div class='add'>+				(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT)</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI6_TX_BCLK</div><div class='add'>+				(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT)</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI6_TX_DATA00</div><div class='add'>+				(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT)</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_SAI6_MCLK</div><div class='add'>+				(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT)</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI6_RX_DATA00</div><div class='add'>+				(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT)</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_tas_reset: tasresetgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24</div><div class='add'>+				MX8MP_DSE_X1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX</div><div class='add'>+				(MX8MP_PULL_UP | MX8MP_PULL_ENABLE)</div><div class='add'>+			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX</div><div class='add'>+				(MX8MP_PULL_UP | MX8MP_PULL_ENABLE)</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX</div><div class='add'>+				(MX8MP_PULL_UP | MX8MP_PULL_ENABLE)</div><div class='add'>+			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX</div><div class='add'>+				(MX8MP_PULL_UP | MX8MP_PULL_ENABLE)</div><div class='add'>+			MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS</div><div class='add'>+				(MX8MP_PULL_UP | MX8MP_PULL_ENABLE)</div><div class='add'>+			MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS</div><div class='add'>+				(MX8MP_PULL_UP | MX8MP_PULL_ENABLE)</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B</div><div class='add'>+				(MX8MP_DSE_X6 | MX8MP_HYS_SCHMITT)</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wl_int: wlintgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13</div><div class='add'>+				(MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wl_reg: wlreggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19</div><div class='add'>+				MX8MP_DSE_X1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai6 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_SAI6&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;12288000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai6&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	fsl,sai-mclk-direction-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "infineon,cyw43439-bt", "brcm,bcm4329-bt";</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;12 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		interrupt-names = "host-wakeup";</div><div class='add'>+		device-wakeup-gpios = &lt;&amp;gpio1 15 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		max-speed = &lt;921600&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_bt&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		shutdown-gpios = &lt;&amp;gpio1 14 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		vbat-supply = &lt;&amp;reg_3v3_per&gt;;</div><div class='add'>+		vddio-supply = &lt;&amp;reg_3v3_per&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_0 {</div><div class='add'>+	dr_mode = "peripheral";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_USDHC2&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;50000000&gt;;</div><div class='add'>+	cap-power-off-card;</div><div class='add'>+	keep-power-in-suspend;</div><div class='add'>+	max-frequency = &lt;50000000&gt;;</div><div class='add'>+	mmc-pwrseq = &lt;&amp;wifi_powerseq&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	sd-uhs-sdr25;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_3v3_per&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	wifi@1 {</div><div class='add'>+		compatible = "infineon,cyw43439-fmac", "brcm,bcm4329-fmac";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;13 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupt-names = "host-wake";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_wl_int&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		brcm,board-type = "GOcontroll,moduline";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi<br/>new file mode 100644<br/>index 000000000000..fe8ba16eb40e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi</a></div><div class='hunk'>@@ -0,0 +1,548 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2020 Lothar Waßmann &lt;LW@KARO-electronics.de&gt;</div><div class='add'>+ * 2025 Maud Spierings &lt;maudspierings@gocontroll.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "imx8mp.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	/* PHY regulator */</div><div class='add'>+	regulator-3v3-etn {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		gpios = &lt;&amp;gpio1 23 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_3v3_etn&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "3v3-etn";</div><div class='add'>+		vin-supply = &lt;&amp;reg_vdd_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_vdd_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_vdd_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_vdd_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_vdd_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eqos {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_ENET_AXI&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MP_CLK_ENET_QOS_TIMER&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX8MP_CLK_ENET_QOS&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL1_266M&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MP_SYS_PLL2_100M&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MP_SYS_PLL2_50M&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;266000000&gt;, &lt;100000000&gt;, &lt;50000000&gt;;</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	phy-mode = "rmii";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_eqos&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_eqos_sleep&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_ethphy_rst_b&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		reset-delay-us = &lt;25000&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio4 22 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+			interrupts = &lt;21 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MP_CLK_ENET_QOS&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_ethphy_int_b&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			smsc,disable-energy-detect;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	gpio-line-names = "SODIMM_152",</div><div class='add'>+			  "SODIMM_42",</div><div class='add'>+			  "PMIC_WDOG_B SODIMM_153",</div><div class='add'>+			  "PMIC_IRQ_B",</div><div class='add'>+			  "SODIMM_154",</div><div class='add'>+			  "SODIMM_155",</div><div class='add'>+			  "SODIMM_156",</div><div class='add'>+			  "SODIMM_157",</div><div class='add'>+			  "SODIMM_158",</div><div class='add'>+			  "SODIMM_159",</div><div class='add'>+			  "SODIMM_161",</div><div class='add'>+			  "SODIMM_162",</div><div class='add'>+			  "SODIMM_34",</div><div class='add'>+			  "SODIMM_36",</div><div class='add'>+			  "SODIMM_27",</div><div class='add'>+			  "SODIMM_28",</div><div class='add'>+			  "ENET_MDC",</div><div class='add'>+			  "ENET_MDIO",</div><div class='add'>+			  "",</div><div class='add'>+			  "ENET_XTAL1/CLKIN",</div><div class='add'>+			  "ENET_TXD1",</div><div class='add'>+			  "ENET_TXD0",</div><div class='add'>+			  "ENET_TXEN",</div><div class='add'>+			  "ENET_POWER",</div><div class='add'>+			  "ENET_COL/CRS_DV",</div><div class='add'>+			  "ENET_RXER",</div><div class='add'>+			  "ENET_RXD0",</div><div class='add'>+			  "ENET_RXD1",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio2 {</div><div class='add'>+	gpio-line-names = "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "SODIMM_51",</div><div class='add'>+			  "SODIMM_57",</div><div class='add'>+			  "SODIMM_56",</div><div class='add'>+			  "SODIMM_52",</div><div class='add'>+			  "SODIMM_53",</div><div class='add'>+			  "SODIMM_54",</div><div class='add'>+			  "SODIMM_55",</div><div class='add'>+			  "SODIMM_15",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio3 {</div><div class='add'>+	gpio-line-names = "",</div><div class='add'>+			  "",</div><div class='add'>+			  "EMMC_DS",</div><div class='add'>+			  "EMMC_DAT5",</div><div class='add'>+			  "EMMC_DAT6",</div><div class='add'>+			  "EMMC_DAT7",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "EMMC_DAT0",</div><div class='add'>+			  "EMMC_DAT1",</div><div class='add'>+			  "EMMC_DAT2",</div><div class='add'>+			  "EMMC_DAT3",</div><div class='add'>+			  "",</div><div class='add'>+			  "EMMC_DAT4",</div><div class='add'>+			  "",</div><div class='add'>+			  "EMMC_CLK",</div><div class='add'>+			  "EMMC_CMD",</div><div class='add'>+			  "SODIMM_75",</div><div class='add'>+			  "SODIMM_145",</div><div class='add'>+			  "SODIMM_163",</div><div class='add'>+			  "SODIMM_164",</div><div class='add'>+			  "SODIMM_165",</div><div class='add'>+			  "SODIMM_143",</div><div class='add'>+			  "SODIMM_144",</div><div class='add'>+			  "SODIMM_72",</div><div class='add'>+			  "SODIMM_73",</div><div class='add'>+			  "SODIMM_74",</div><div class='add'>+			  "SODIMM_93",</div><div class='add'>+			  "",</div><div class='add'>+			  "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	gpio-line-names = "SODIMM_98",</div><div class='add'>+			  "SODIMM_99",</div><div class='add'>+			  "SODIMM_100",</div><div class='add'>+			  "SODIMM_101",</div><div class='add'>+			  "SODIMM_45",</div><div class='add'>+			  "SODIMM_43",</div><div class='add'>+			  "SODIMM_105",</div><div class='add'>+			  "SODIMM_106",</div><div class='add'>+			  "SODIMM_107",</div><div class='add'>+			  "SODIMM_108",</div><div class='add'>+			  "SODIMM_104",</div><div class='add'>+			  "SODIMM_103",</div><div class='add'>+			  "SODIMM_115",</div><div class='add'>+			  "SODIMM_114",</div><div class='add'>+			  "SODIMM_113",</div><div class='add'>+			  "SODIMM_112",</div><div class='add'>+			  "SODIMM_109",</div><div class='add'>+			  "SODIMM_110",</div><div class='add'>+			  "SODIMM_95",</div><div class='add'>+			  "SODIMM_96",</div><div class='add'>+			  "SODIMM_97",</div><div class='add'>+			  "ENET_nINT",</div><div class='add'>+			  "ENET_nRST",</div><div class='add'>+			  "SODIMM_84",</div><div class='add'>+			  "SODIMM_87",</div><div class='add'>+			  "SODIMM_86",</div><div class='add'>+			  "SODIMM_85",</div><div class='add'>+			  "SODIMM_83",</div><div class='add'>+			  "",</div><div class='add'>+			  "SODIMM_66",</div><div class='add'>+			  "SODIMM_65",</div><div class='add'>+			  "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio5 {</div><div class='add'>+	gpio-line-names = "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "SODIMM_76",</div><div class='add'>+			  "SODIMM_81",</div><div class='add'>+			  "SODIMM_146",</div><div class='add'>+			  "SODIMM_48",</div><div class='add'>+			  "SODIMM_46",</div><div class='add'>+			  "SODIMM_47",</div><div class='add'>+			  "SODIMM_44",</div><div class='add'>+			  "SODIMM_49",</div><div class='add'>+			  "",</div><div class='add'>+			  "SODIMM_70",</div><div class='add'>+			  "SODIMM_69",</div><div class='add'>+			  "PMIC_SCL",</div><div class='add'>+			  "PMIC_SDA",</div><div class='add'>+			  "SODIMM_41",</div><div class='add'>+			  "SODIMM_40",</div><div class='add'>+			  "SODIMM_148",</div><div class='add'>+			  "SODIMM_149",</div><div class='add'>+			  "SODIMM_150",</div><div class='add'>+			  "SODIMM_151",</div><div class='add'>+			  "SODIMM_60",</div><div class='add'>+			  "SODIMM_59",</div><div class='add'>+			  "SODIMM_64",</div><div class='add'>+			  "SODIMM_63",</div><div class='add'>+			  "SODIMM_62",</div><div class='add'>+			  "SODIMM_61",</div><div class='add'>+			  "SODIMM_68",</div><div class='add'>+			  "SODIMM_67",</div><div class='add'>+			  "",</div><div class='add'>+			  "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c1_gpio&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pmic@25 {</div><div class='add'>+		compatible = "nxp,pca9450c";</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;3 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			reg_vdd_soc: BUCK1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;805000&gt;;</div><div class='add'>+				regulator-name = "vdd-soc";</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vdd_arm: BUCK2 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;950000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;805000&gt;;</div><div class='add'>+				regulator-name = "vdd-core";</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+				nxp,dvs-run-voltage = &lt;950000&gt;;</div><div class='add'>+				nxp,dvs-standby-voltage = &lt;850000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vdd_3v3: BUCK4 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "3v3";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_nvcc_nand: BUCK5 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "nvcc-nand";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_nvcc_dram: BUCK6 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-name = "nvcc-dram";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_snvs_1v8: LDO1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "snvs-1v8";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo2_reg: LDO2 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1150000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-name = "LDO2";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vdda_1v8: LDO3 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "vdda-1v8";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo4_reg: LDO4 {</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-name = "LDO4";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo5_reg: LDO5 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "LDO5";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_eqos: eqosgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK</div><div class='add'>+				(MX8MP_DSE_X4 | MX8MP_PULL_UP | MX8MP_PULL_ENABLE | MX8MP_SION)</div><div class='add'>+			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC</div><div class='add'>+				(MX8MP_DSE_X4 | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)</div><div class='add'>+			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO</div><div class='add'>+				(MX8MP_DSE_X4 | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0</div><div class='add'>+				(MX8MP_DSE_X6 | MX8MP_FSEL_FAST)</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1</div><div class='add'>+				(MX8MP_DSE_X6 | MX8MP_FSEL_FAST)</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0</div><div class='add'>+				(MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1</div><div class='add'>+				(MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)</div><div class='add'>+			MX8MP_IOMUXC_ENET_RXC__ENET_QOS_RX_ER</div><div class='add'>+				(MX8MP_FSEL_FAST | MX8MP_PULL_ENABLE)</div><div class='add'>+			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL</div><div class='add'>+				(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_ENABLE)</div><div class='add'>+			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL</div><div class='add'>+				(MX8MP_DSE_X6 | MX8MP_FSEL_FAST)</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_eqos_sleep: eqos-sleep-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD2__GPIO1_IO19</div><div class='add'>+				(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)</div><div class='add'>+			MX8MP_IOMUXC_ENET_MDC__GPIO1_IO16</div><div class='add'>+				(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)</div><div class='add'>+			MX8MP_IOMUXC_ENET_MDIO__GPIO1_IO17</div><div class='add'>+				(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD0__GPIO1_IO21</div><div class='add'>+				(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD1__GPIO1_IO20</div><div class='add'>+				(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD0__GPIO1_IO26</div><div class='add'>+				(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD1__GPIO1_IO27</div><div class='add'>+				(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)</div><div class='add'>+			MX8MP_IOMUXC_ENET_RXC__GPIO1_IO25</div><div class='add'>+				(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)</div><div class='add'>+			MX8MP_IOMUXC_ENET_RX_CTL__GPIO1_IO24</div><div class='add'>+				(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)</div><div class='add'>+			MX8MP_IOMUXC_ENET_TX_CTL__GPIO1_IO22</div><div class='add'>+				(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ethphy_int_b: ethphy-int-bgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21</div><div class='add'>+				(MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT)</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ethphy_rst_b: ethphy-rst-bgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22</div><div class='add'>+				(MX8MP_PULL_UP | MX8MP_PULL_ENABLE)</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL</div><div class='add'>+				MX8MP_I2C_DEFAULT</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA</div><div class='add'>+				MX8MP_I2C_DEFAULT</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1_gpio: i2c1-gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14</div><div class='add'>+				MX8MP_I2C_DEFAULT</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15</div><div class='add'>+				MX8MP_I2C_DEFAULT</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: pmicgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03</div><div class='add'>+				(MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_3v3_etn: reg-3v3-etngrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ENET_TXC__GPIO1_IO23</div><div class='add'>+				(MX8MP_PULL_UP | MX8MP_PULL_ENABLE)</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK</div><div class='add'>+				(MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD</div><div class='add'>+				MX8MP_USDHC_DATA_DEFAULT</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0</div><div class='add'>+				MX8MP_USDHC_DATA_DEFAULT</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1</div><div class='add'>+				MX8MP_USDHC_DATA_DEFAULT</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2</div><div class='add'>+				MX8MP_USDHC_DATA_DEFAULT</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3</div><div class='add'>+				MX8MP_USDHC_DATA_DEFAULT</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4</div><div class='add'>+				MX8MP_USDHC_DATA_DEFAULT</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5</div><div class='add'>+				MX8MP_USDHC_DATA_DEFAULT</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6</div><div class='add'>+				MX8MP_USDHC_DATA_DEFAULT</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7</div><div class='add'>+				MX8MP_USDHC_DATA_DEFAULT</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE</div><div class='add'>+				(MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK</div><div class='add'>+				(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD</div><div class='add'>+				(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0</div><div class='add'>+				(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1</div><div class='add'>+				(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2</div><div class='add'>+				(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3</div><div class='add'>+				(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4</div><div class='add'>+				(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5</div><div class='add'>+				(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6</div><div class='add'>+				(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7</div><div class='add'>+				(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE</div><div class='add'>+				(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK</div><div class='add'>+				(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD</div><div class='add'>+				(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0</div><div class='add'>+				(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1</div><div class='add'>+				(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2</div><div class='add'>+				(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3</div><div class='add'>+				(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4</div><div class='add'>+				(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5</div><div class='add'>+				(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6</div><div class='add'>+				(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7</div><div class='add'>+				(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE</div><div class='add'>+				(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_USDHC3&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;200000000&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_vdd_3v3&gt;;</div><div class='add'>+	voltage-ranges = &lt;3300 3300&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_nvcc_nand&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-ultra-mach-sbc.dts b/arch/arm64/boot/dts/freescale/imx8mp-ultra-mach-sbc.dts<br/>new file mode 100644<br/>index 000000000000..9ecec1a41878<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-ultra-mach-sbc.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-ultra-mach-sbc.dts</a></div><div class='hunk'>@@ -0,0 +1,907 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2025 Ultratronik</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/usb/pd.h&gt;</div><div class='add'>+#include "imx8mp.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "NXP i.MX8MPlus Ultratronik MMI_A53 board";</div><div class='add'>+	compatible = "ultratronik,imx8mp-ultra-mach-sbc", "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;fec;</div><div class='add'>+		ethernet1 = &amp;eqos;</div><div class='add'>+		rtc0 = &amp;hwrtc;</div><div class='add'>+		rtc1 = &amp;snvs_rtc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-sbu-mux {</div><div class='add'>+		compatible = "nxp,cbdtu02043", "gpio-sbu-mux";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_sbu_mux&gt;;</div><div class='add'>+		select-gpios = &lt;&amp;gpio4 20 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;gpio2 20 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		orientation-switch;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			usb3_data_ss: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;typec_con_ss&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		button-0 {</div><div class='add'>+			gpios = &lt;&amp;gpio4 27 GPIO_ACTIVE_LOW&gt;; /* Wakeup */</div><div class='add'>+			label = "Wakeup";</div><div class='add'>+			linux,code = &lt;KEY_WAKEUP&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_gpio_key_wakeup&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_leds&gt;;</div><div class='add'>+</div><div class='add'>+		led1 {</div><div class='add'>+			label = "red";</div><div class='add'>+			gpios = &lt;&amp;gpio4 24 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led2 {</div><div class='add'>+			label = "green";</div><div class='add'>+			gpios = &lt;&amp;gpio4 25 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led3 {</div><div class='add'>+			label = "yellow";</div><div class='add'>+			gpios = &lt;&amp;gpio4 26 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usba_vbus: regulator-usba-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usb1&gt;;</div><div class='add'>+		regulator-name = "usb-A-vbus";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio1 12 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usdhc2_vmmc&gt;;</div><div class='add'>+		regulator-name = "VSD_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio2 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi1 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi1 &amp;pinctrl_ecspi1_cs&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	slb9670: tpm@0 {</div><div class='add'>+		compatible = "infineon,slb9670", "tcg,tpm_tis-spi";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;32000000&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_slb9670&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;0 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi2 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi2 &amp;pinctrl_ecspi2_cs&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 13 GPIO_ACTIVE_LOW&gt;,</div><div class='add'>+		&lt;&amp;gpio1 8 GPIO_ACTIVE_LOW&gt;,</div><div class='add'>+		&lt;&amp;gpio1 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	nfc-transceiver@1 {</div><div class='add'>+		compatible = "st,st95hf";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_nfc&gt;;</div><div class='add'>+		spi-max-frequency = &lt;100000&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;7 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		enable-gpio = &lt;&amp;gpio1 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eqos {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_eqos&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@1 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;0x1&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+			interrupts = &lt;18 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy1&gt;;</div><div class='add'>+	fsl,magic-packet;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy1: ethernet-phy@2 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;0x2&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+			interrupts = &lt;1 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"#TPM_IRQ", "GPIO1", "", "#PMIC_INT",</div><div class='add'>+		"SD2_VSEL", "#TOUCH_IRQ", "#NFC_INT_I", "#NFC_INT",</div><div class='add'>+		"#SPI2_CS2", "#SPI2_CS3", "#RTS4", "",</div><div class='add'>+		"USB_PWR", "GPIO2", "GPIO3", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio2 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "#SD2_CD", "", "", "",</div><div class='add'>+		"", "", "", "", "#USB-C_EN", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio3 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "DISP_POW", "GPIO4",</div><div class='add'>+		"#", "", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"BKL_POW", "#ETH1_INT", "#TPM_RES", "#PCAP_RES",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "#ETH0_INT", "#USB-C_ALERT",</div><div class='add'>+		"#USB-C_SEL", "", "", "",</div><div class='add'>+		"LED_RED", "LED_GREEN", "LED_YELLOW", "#WAKEUP",</div><div class='add'>+		"", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio5 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "#SPI1_CS", "", "", "", "#SPI2_CS1", "", "",</div><div class='add'>+		"", "", "", "", "ENA_KAM", "ENA_LED", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_pvi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	ddc-i2c-bus = &lt;&amp;i2c5&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hdmi&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c1_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pmic@25 {</div><div class='add'>+		compatible = "nxp,pca9450c";</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;3 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * i.MX 8M Plus Data Sheet for Consumer Products</div><div class='add'>+		 * 3.1.4 Operating ranges</div><div class='add'>+		 * MIMX8ML8DVNLZAB</div><div class='add'>+		 */</div><div class='add'>+		regulators {</div><div class='add'>+			buck1: BUCK1 {	/* VDD_SOC (dual-phase with BUCK3) */</div><div class='add'>+				regulator-min-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1050000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck2: BUCK2 {	/* VDD_ARM */</div><div class='add'>+				regulator-min-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+				nxp,dvs-run-voltage = &lt;950000&gt;;</div><div class='add'>+				nxp,dvs-standby-voltage = &lt;850000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck4: BUCK4 {	/* +3V3 */</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck5: BUCK5 {	/* +1V8 */</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck6: BUCK6 {	/* DRAM_1V1 */</div><div class='add'>+				regulator-min-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo1: LDO1 {	/* NVCC_SNVS_1V8 */</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo3: LDO3 {	/* VDDA_1P8 */</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo4: LDO4 {	/* ENET_2V5 */</div><div class='add'>+				regulator-min-microvolt = &lt;2500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2500000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo5: LDO5 {	/* NVCC_SD2 */</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	crypto@35 {</div><div class='add'>+		compatible = "atmel,atecc508a";</div><div class='add'>+		reg = &lt;0x35&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@50 {</div><div class='add'>+		compatible = "atmel,24c16";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c2_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	hwrtc: rtc@32 {</div><div class='add'>+		compatible = "epson,rx8900";</div><div class='add'>+		reg = &lt;0x32&gt;;</div><div class='add'>+		epson,vdet-disable;</div><div class='add'>+		trickle-diode-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	tcpc@52 {</div><div class='add'>+		compatible = "nxp,ptn5110", "tcpci";</div><div class='add'>+		reg = &lt;0x52&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_ptn5110&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;19 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		usb_con: connector {</div><div class='add'>+			compatible = "usb-c-connector";</div><div class='add'>+			label = "USB-C";</div><div class='add'>+			power-role = "dual";</div><div class='add'>+			data-role = "dual";</div><div class='add'>+			try-power-role = "sink";</div><div class='add'>+			source-pdos = &lt;PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)&gt;;</div><div class='add'>+			sink-pdos = &lt;PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)</div><div class='add'>+				     PDO_VAR(5000, 5000, 3000)&gt;;</div><div class='add'>+			op-sink-microwatt = &lt;15000000&gt;;</div><div class='add'>+			self-powered;</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					typec_dr_sw: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;usb3_drd_sw&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					typec_con_ss: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;usb3_data_ss&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c3_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c5 {	/* HDMI EDID bus */</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c5&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c5_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;snvs_pwrkey {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	/* system console */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	/* expansion port serial connection */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_0 {</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	hnp-disable;</div><div class='add'>+	srp-disable;</div><div class='add'>+	adp-disable;</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	port {</div><div class='add'>+		usb3_drd_sw: endpoint {</div><div class='add'>+			remote-endpoint = &lt;&amp;typec_dr_sw&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy1 {</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usba_vbus&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_1 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	snps,hsphy_interface = "utmi";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_USDHC2&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;ldo5&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_USDHC3&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;buck4&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;buck5&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	no-sd;</div><div class='add'>+	no-sdio;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hog&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi1_cs: ecspi1-cs-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09		0x40	/* #SPI1_CS */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi1: ecspi1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK		0x82</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI		0x82</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO		0x82</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi2_cs: ecspi2-cs-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13		0x40	/* #SPI2_CS */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08		0x40	/* #SPI2_CS2 */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09		0x40	/* #SPI2_CS3 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi2: ecspi2-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK		0x82</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI		0x82</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO		0x82</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_eqos: eqos-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC		0x0</div><div class='add'>+			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO		0x0</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0	0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1	0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2	0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3	0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL	0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0	0x16</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1	0x16</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2	0x16</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3	0x16</div><div class='add'>+			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL	0x16</div><div class='add'>+			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x16</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18		0x10	/* #ETH0_INT */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec: fec-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC               0x0</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO              0x0</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0         0x90</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1         0x90</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2         0x90</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3         0x90</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC          0x90</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL      0x90</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0         0x16</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1         0x16</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2         0x16</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3         0x16</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL      0x16</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC         0x16</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01               0x10	/* #ETH1_INT */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan1: flexcan1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SPDIF_RX__CAN1_RX			0x154</div><div class='add'>+			MX8MP_IOMUXC_SPDIF_TX__CAN1_TX			0x154</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio_key_wakeup: gpio-key-wakeup-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27		0x40	/* #WAKEUP */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio_leds: gpio-leds-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24		0x40	/* LED_RED */</div><div class='add'>+			MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25		0x40	/* LED_GREEN */</div><div class='add'>+			MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26		0x40	/* LED_YELLOW */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_hdmi: hdmi-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC		0x154</div><div class='add'>+			MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD		0x154</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_hog: hog-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01	0x40	/* GPIO1 */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13	0x40	/* GPIO2 */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14	0x40	/* GPIO3 */</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23	0x40	/* GPIO4 */</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20	0x40	/* ENA_KAM */</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21	0x40	/* ENA_LED */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03	0x40	/* #PCAP_RES */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10	0x40	/* #RTS4 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL			0x400001c0</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA			0x400001c0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1_gpio: i2c1-gpio-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14		0xc0</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15		0xc0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL			0x400001c0</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA			0x400001c0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2_gpio: i2c2-gpio-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16		0xc0</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17		0xc0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL			0x400001c2</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA			0x400001c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3_gpio: i2c3-gpio-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18		0xc2</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19		0xc2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c5: i2c5-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL		0x400000c4</div><div class='add'>+			MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA		0x400000c4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c5_gpio: i2c5-gpio-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26		0xc4</div><div class='add'>+			MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27		0xc4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_nfc: nfc-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06		0x40	/* NFC_INT_I */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07		0x40	/* NFC_INT */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: pmic-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03		0x40	/* #PMIC_INT */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ptn5110: ptn5110-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19		0x1c4	/* #USB-C_ALERT */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm1: pwm1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT		0x116</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm2: pwm2-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT		0x116	/* EXT_PWM */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usdhc2_vmmc: reg-usdhc2-vmmc-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x40</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sbu_mux: sbu-mux-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20		0x16	/* #USB-C_SEL */</div><div class='add'>+			MX8MP_IOMUXC_SD2_WP__GPIO2_IO20			0x16	/* #USB-C_EN */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_slb9670: slb9670-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00		0x40	/* #TPM_IRQ */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02		0x40	/* #TPM_RES */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX		0x40</div><div class='add'>+			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX		0x40</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: uart3-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX		0x40</div><div class='add'>+			MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX		0x40</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart4: uart4-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX		0x40</div><div class='add'>+			MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX		0x40</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usb1: usb1-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12		0x40	/* USB_PWR */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x190</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc0	/* SD2_VSEL */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x194</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc0	/* SD2_VSEL */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x196</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc0	/* SD2_VSEL */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2-gpio-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12		0x1c4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: usdhc3-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x190</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x190</div><div class='add'>+			MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x40	/* #SD3_RESET */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x194</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x192</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d2</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d2</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d2</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d2</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d2</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d2</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d2</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d2</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d2</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x192</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdog-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B		0xc6	/* #WDOG */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts<br/>new file mode 100644<br/>index 000000000000..36d3eb865202<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts</a></div><div class='hunk'>@@ -0,0 +1,11 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 Variscite Ltd.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "imx8mp-var-som.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Variscite VAR-SOM-MX8M-PLUS on Symphony-Board";</div><div class='add'>+	compatible = "variscite,var-som-mx8mp-symphony", "variscite,var-som-mx8mp", "fsl,imx8mp";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi<br/>new file mode 100644<br/>index 000000000000..29f080904482<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi</a></div><div class='hunk'>@@ -0,0 +1,455 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 Variscite Ltd.</div><div class='add'>+ *</div><div class='add'>+ * Author: Tarang Raval &lt;tarang.raval@siliconsignals.io&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/phy/phy-imx8-pcie.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/usb/pd.h&gt;</div><div class='add'>+#include "imx8mp.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Variscite VAR-SOM-MX8M Plus module";</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-leds {</div><div class='add'>+	        compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+	        led-0 {</div><div class='add'>+	                function = LED_FUNCTION_POWER;</div><div class='add'>+	                gpios = &lt;&amp;pca9534 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	                linux,default-trigger = "heartbeat";</div><div class='add'>+	        };</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x40000000 0 0xc0000000&gt;,</div><div class='add'>+		      &lt;0x1 0x00000000 0 0xc0000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {</div><div class='add'>+	        compatible = "regulator-fixed";</div><div class='add'>+	        regulator-name = "VSD_3V3";</div><div class='add'>+	        regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+	        regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	        gpios = &lt;&amp;gpio4 22 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	        enable-active-high;</div><div class='add'>+	        startup-delay-us = &lt;100&gt;;</div><div class='add'>+	        off-on-delay-us = &lt;12000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc {</div><div class='add'>+		compatible = "regulator-gpio";</div><div class='add'>+		regulator-name = "VSD_VSEL";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		states = &lt;3300000 0x0 1800000 0x1&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;ldo5&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_phy_supply: regulator-phy-supply {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "phy-supply";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-enable-ramp-delay = &lt;20000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio2 20 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_phy_vddio: regulator-phy-vddio {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vddio-1v8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eqos {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_eqos&gt;;</div><div class='add'>+	/*</div><div class='add'>+	 * The required RGMII TX and RX 2ns delays are implemented directly</div><div class='add'>+	 * in hardware via passive delay elements on the SOM PCB.</div><div class='add'>+	 * No delay configuration is needed in software via PHY driver.</div><div class='add'>+	 */</div><div class='add'>+	phy-mode = "rgmii";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@4 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;4&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio1 10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;10000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;100000&gt;;</div><div class='add'>+			vddio-supply = &lt;&amp;reg_phy_vddio&gt;;</div><div class='add'>+</div><div class='add'>+			leds {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				led@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					color = &lt;LED_COLOR_ID_YELLOW&gt;;</div><div class='add'>+					function = LED_FUNCTION_LAN;</div><div class='add'>+					linux,default-trigger = "netdev";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				led@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+					function = LED_FUNCTION_LAN;</div><div class='add'>+					linux,default-trigger = "netdev";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pmic@25 {</div><div class='add'>+		compatible = "nxp,pca9450c";</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio5&gt;;</div><div class='add'>+		interrupts = &lt;4 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			buck1: BUCK1 {</div><div class='add'>+				regulator-name = "BUCK1";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2187500&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck2: BUCK2 {</div><div class='add'>+				regulator-name = "BUCK2";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2187500&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+				nxp,dvs-run-voltage = &lt;950000&gt;;</div><div class='add'>+				nxp,dvs-standby-voltage = &lt;850000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck4: BUCK4 {</div><div class='add'>+				regulator-name = "BUCK4";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck5: BUCK5 {</div><div class='add'>+				regulator-name = "BUCK5";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck6: BUCK6 {</div><div class='add'>+				regulator-name = "BUCK6";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo1: LDO1 {</div><div class='add'>+				regulator-name = "LDO1";</div><div class='add'>+				regulator-min-microvolt = &lt;1600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo2: LDO2 {</div><div class='add'>+				regulator-name = "LDO2";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1150000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo3: LDO3 {</div><div class='add'>+				regulator-name = "LDO3";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo4: LDO4 {</div><div class='add'>+				regulator-name = "LDO4";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo5: LDO5 {</div><div class='add'>+				regulator-name = "LDO5";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+        clock-frequency = &lt;400000&gt;;</div><div class='add'>+        pinctrl-names = "default";</div><div class='add'>+        pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+        status = "okay";</div><div class='add'>+</div><div class='add'>+	/* GPIO expander */</div><div class='add'>+	pca9534: gpio@20 {</div><div class='add'>+	        compatible = "nxp,pca9534";</div><div class='add'>+	        reg = &lt;0x20&gt;;</div><div class='add'>+	        pinctrl-names = "default";</div><div class='add'>+	        pinctrl-0 = &lt;&amp;pinctrl_pca9534&gt;;</div><div class='add'>+	        gpio-controller;</div><div class='add'>+	        #gpio-cells = &lt;2&gt;;</div><div class='add'>+	        interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+	        interrupts = &lt;15 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+	        wakeup-source;</div><div class='add'>+</div><div class='add'>+	        usb3-sata-sel-hog {</div><div class='add'>+	                gpio-hog;</div><div class='add'>+	                gpios = &lt;4 0&gt;;</div><div class='add'>+	                output-low;</div><div class='add'>+	                line-name = "usb3_sata_sel";</div><div class='add'>+	        };</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Console */</div><div class='add'>+&amp;uart2 {</div><div class='add'>+        pinctrl-names = "default";</div><div class='add'>+        pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+        status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SD-card */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+        pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+        pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+        pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+        pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+        cd-gpios = &lt;&amp;gpio1 14 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+        vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_usdhc2_vqmmc&gt;;</div><div class='add'>+        bus-width = &lt;4&gt;;</div><div class='add'>+        status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* eMMC */</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+</div><div class='add'>+	pinctrl_eqos: eqosgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x2</div><div class='add'>+			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x2</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL			0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x16</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x16</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x16</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x16</div><div class='add'>+			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL			0x16</div><div class='add'>+			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x16</div><div class='add'>+			MX8MP_IOMUXC_SD2_WP__GPIO2_IO20					0x10</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10				0x150</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA4__I2C1_SCL				0x400001c2</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA5__I2C1_SDA				0x400001c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+	        fsl,pins = &lt;</div><div class='add'>+	                MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL                                 0x400001c2</div><div class='add'>+	                MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA                                 0x400001c2</div><div class='add'>+	        &gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pca9534: pca9534grp {</div><div class='add'>+	        fsl,pins = &lt;</div><div class='add'>+	                MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15                             0xc0</div><div class='add'>+	        &gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: pmicgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04				0x1c0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+	        fsl,pins = &lt;</div><div class='add'>+		        MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX                            0x40</div><div class='add'>+			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX                            0x40</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2-gpiogrp {</div><div class='add'>+	        fsl,pins = &lt;</div><div class='add'>+	                MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14                             0x1c4</div><div class='add'>+	                MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22                               0x10</div><div class='add'>+	                MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12                               0xc0</div><div class='add'>+	        &gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+	        fsl,pins = &lt;</div><div class='add'>+	                MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK                                0x190</div><div class='add'>+	                MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD                                0x1d0</div><div class='add'>+	                MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0                            0x1d0</div><div class='add'>+	                MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1                            0x1d0</div><div class='add'>+	                MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2                            0x1d0</div><div class='add'>+	                MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3                            0x1d0</div><div class='add'>+	        &gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+	        fsl,pins = &lt;</div><div class='add'>+	                MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK                                0x194</div><div class='add'>+	                MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD                                0x1d4</div><div class='add'>+	                MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0                            0x1d4</div><div class='add'>+	                MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1                            0x1d4</div><div class='add'>+	                MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2                            0x1d4</div><div class='add'>+	                MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3                            0x1d4</div><div class='add'>+	        &gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+	        fsl,pins = &lt;</div><div class='add'>+	                MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK                                0x196</div><div class='add'>+	                MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD                                0x1d6</div><div class='add'>+	                MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0                            0x1d6</div><div class='add'>+	                MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1                            0x1d6</div><div class='add'>+	                MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2                            0x1d6</div><div class='add'>+	                MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3                            0x1d6</div><div class='add'>+	        &gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK				0x190</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD				0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0				0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1				0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2				0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3				0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4				0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5				0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6				0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7				0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE				0x190</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK				0x194</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD				0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0				0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1				0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2				0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3				0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4				0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5				0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6				0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7				0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE				0x194</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK				0x196</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD				0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0				0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1				0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2				0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3				0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4				0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5				0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6				0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7				0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE				0x196</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B				0xc6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi<br/>new file mode 100644<br/>index 000000000000..de852ebff571<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi</a></div><div class='hunk'>@@ -0,0 +1,561 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Gateworks Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/linux-event-codes.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/net/ti-dp83867.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;eqos;</div><div class='add'>+		rtc0 = &amp;gsc_rtc;</div><div class='add'>+		rtc1 = &amp;snvs_rtc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x40000000 0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		key-user-pb {</div><div class='add'>+			label = "user_pb";</div><div class='add'>+			gpios = &lt;&amp;gpio 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;BTN_0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-user-pb1x {</div><div class='add'>+			label = "user_pb1x";</div><div class='add'>+			linux,code = &lt;BTN_1&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gsc&gt;;</div><div class='add'>+			interrupts = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-erased {</div><div class='add'>+			label = "key_erased";</div><div class='add'>+			linux,code = &lt;BTN_2&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gsc&gt;;</div><div class='add'>+			interrupts = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-eeprom-wp {</div><div class='add'>+			label = "eeprom_wp";</div><div class='add'>+			linux,code = &lt;BTN_3&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gsc&gt;;</div><div class='add'>+			interrupts = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-tamper {</div><div class='add'>+			label = "tamper";</div><div class='add'>+			linux,code = &lt;BTN_4&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gsc&gt;;</div><div class='add'>+			interrupts = &lt;5&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		switch-hold {</div><div class='add'>+			label = "switch_hold";</div><div class='add'>+			linux,code = &lt;BTN_5&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gsc&gt;;</div><div class='add'>+			interrupts = &lt;7&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck3_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck3_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck3_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck3_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eqos {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_eqos&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@0 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_ethphy0&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			reg = &lt;0x0&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+			interrupts = &lt;16 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+			ti,clk-output-sel = &lt;DP83867_CLK_O_SEL_OFF&gt;;</div><div class='add'>+			ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_2_00_NS&gt;;</div><div class='add'>+			ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_2_00_NS&gt;;</div><div class='add'>+			tx-fifo-depth = &lt;DP83867_PHYCR_FIFO_DEPTH_4_B_NIB&gt;;</div><div class='add'>+			rx-fifo-depth = &lt;DP83867_PHYCR_FIFO_DEPTH_4_B_NIB&gt;;</div><div class='add'>+</div><div class='add'>+			leds {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				led@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					color = &lt;LED_COLOR_ID_AMBER&gt;;</div><div class='add'>+					function = LED_FUNCTION_LAN;</div><div class='add'>+					default-state = "keep";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				led@2 {</div><div class='add'>+					reg = &lt;2&gt;;</div><div class='add'>+					color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+					function = LED_FUNCTION_LAN;</div><div class='add'>+					default-state = "keep";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c1_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	gsc: gsc@20 {</div><div class='add'>+		compatible = "gw,gsc";</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gsc&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio2&gt;;</div><div class='add'>+		interrupts = &lt;6 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		adc {</div><div class='add'>+			compatible = "gw,gsc-adc";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			channel@6 {</div><div class='add'>+				gw,mode = &lt;0&gt;;</div><div class='add'>+				reg = &lt;0x06&gt;;</div><div class='add'>+				label = "temp";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@8 {</div><div class='add'>+				gw,mode = &lt;3&gt;;</div><div class='add'>+				reg = &lt;0x08&gt;;</div><div class='add'>+				label = "vdd_bat";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@16 {</div><div class='add'>+				gw,mode = &lt;4&gt;;</div><div class='add'>+				reg = &lt;0x16&gt;;</div><div class='add'>+				label = "fan_tach";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@82 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x82&gt;;</div><div class='add'>+				label = "vdd_vin";</div><div class='add'>+				gw,voltage-divider-ohms = &lt;22100 1000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@84 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x84&gt;;</div><div class='add'>+				label = "vdd_adc1";</div><div class='add'>+				gw,voltage-divider-ohms = &lt;10000 10000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@86 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x86&gt;;</div><div class='add'>+				label = "vdd_adc2";</div><div class='add'>+				gw,voltage-divider-ohms = &lt;10000 10000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@88 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x88&gt;;</div><div class='add'>+				label = "vdd_1p0";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@8c {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x8c&gt;;</div><div class='add'>+				label = "vdd_1p8";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@8e {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x8e&gt;;</div><div class='add'>+				label = "vdd_2p5";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@90 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x90&gt;;</div><div class='add'>+				label = "vdd_3p3";</div><div class='add'>+				gw,voltage-divider-ohms = &lt;10000 10000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@92 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x92&gt;;</div><div class='add'>+				label = "vdd_dram";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@98 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x98&gt;;</div><div class='add'>+				label = "vdd_soc";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@9a {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x9a&gt;;</div><div class='add'>+				label = "vdd_arm";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@a2 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0xa2&gt;;</div><div class='add'>+				label = "vdd_gsc";</div><div class='add'>+				gw,voltage-divider-ohms = &lt;10000 10000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		fan-controller@0 {</div><div class='add'>+			compatible = "gw,gsc-fan";</div><div class='add'>+			reg = &lt;0x0a&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio: gpio@23 {</div><div class='add'>+		compatible = "nxp,pca9555";</div><div class='add'>+		reg = &lt;0x23&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gsc&gt;;</div><div class='add'>+		interrupts = &lt;4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@50 {</div><div class='add'>+		compatible = "atmel,24c02";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@51 {</div><div class='add'>+		compatible = "atmel,24c02";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@52 {</div><div class='add'>+		compatible = "atmel,24c02";</div><div class='add'>+		reg = &lt;0x52&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@53 {</div><div class='add'>+		compatible = "atmel,24c02";</div><div class='add'>+		reg = &lt;0x53&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gsc_rtc: rtc@68 {</div><div class='add'>+		compatible = "dallas,ds1672";</div><div class='add'>+		reg = &lt;0x68&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmic@69 {</div><div class='add'>+		compatible = "mps,mp5416";</div><div class='add'>+		reg = &lt;0x69&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			/* vdd_soc */</div><div class='add'>+			buck1 {</div><div class='add'>+				regulator-name = "buck1";</div><div class='add'>+				regulator-min-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* vdd_dram */</div><div class='add'>+			buck2 {</div><div class='add'>+				regulator-name = "buck2";</div><div class='add'>+				regulator-min-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* vdd_arm */</div><div class='add'>+			buck3_reg: buck3 {</div><div class='add'>+				regulator-name = "buck3";</div><div class='add'>+				regulator-min-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* vdd_1p8 */</div><div class='add'>+			buck4 {</div><div class='add'>+				regulator-name = "buck4";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* OUT2: nvcc_snvs_1p8 */</div><div class='add'>+			ldo1 {</div><div class='add'>+				regulator-name = "ldo1";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* OUT3: vdd_1p0 */</div><div class='add'>+			ldo2 {</div><div class='add'>+				regulator-name = "ldo2";</div><div class='add'>+				regulator-min-microvolt = &lt;1000000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* OUT4: vdd_2p5 */</div><div class='add'>+			ldo3 {</div><div class='add'>+				regulator-name = "ldo3";</div><div class='add'>+				regulator-min-microvolt = &lt;2500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2500000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* OUT5: vdd_3p3 */</div><div class='add'>+			ldo4 {</div><div class='add'>+				regulator-name = "ldo4";</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* off-board header */</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c2_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	eeprom@52 {</div><div class='add'>+		compatible = "atmel,24c32";</div><div class='add'>+		reg = &lt;0x52&gt;;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* off-board header */</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c3_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* console */</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* eMMC */</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_USDHC3&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_eqos: eqosgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC			0x2</div><div class='add'>+			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO			0x2</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0		0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1		0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2		0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3		0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0		0x16</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1		0x16</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2		0x16</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3		0x16</div><div class='add'>+			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x16</div><div class='add'>+			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ethphy0: ethphy0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14	0x140 /* RST# */</div><div class='add'>+			MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16	0x150 /* IRQ# */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gsc: gscgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06	0x150 /* IRQ# */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c2</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1_gpio: i2c1gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14	0x400001c2</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15	0x400001c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001c2</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA		0x400001c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2_gpio: i2c2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16	0x400001c2</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17	0x400001c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400001c2</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3_gpio: i2c3gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18	0x400001c2</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19	0x400001c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x140</div><div class='add'>+			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x190</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x190</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x194</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x194</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x196</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x196</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B	0x166</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx-2x.dts b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx-2x.dts<br/>new file mode 100644<br/>index 000000000000..53120fc9cd7f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx-2x.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx-2x.dts</a></div><div class='hunk'>@@ -0,0 +1,19 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Gateworks Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mp.dtsi"</div><div class='add'>+#include "imx8mp-venice-gw702x.dtsi"</div><div class='add'>+#include "imx8mp-venice-gw71xx.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Gateworks Venice GW71xx-2x i.MX8MP Development Kit";</div><div class='add'>+	compatible = "gateworks,imx8mp-gw71xx-2x", "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart2;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi<br/>new file mode 100644<br/>index 000000000000..4bf818873fe3<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi</a></div><div class='hunk'>@@ -0,0 +1,255 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Gateworks Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/phy/phy-imx8-pcie.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	connector {</div><div class='add'>+		compatible = "gpio-usb-b-connector", "usb-b-connector";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usbcon1&gt;;</div><div class='add'>+		type = "micro";</div><div class='add'>+		label = "Type-C";</div><div class='add'>+		id-gpios = &lt;&amp;gpio3 21 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			usb_dr_connector: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;usb3_dwc&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	led-controller {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_leds&gt;;</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio4 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "on";</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio4 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_refclk: clock-pcie0 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;100000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pps {</div><div class='add'>+		compatible = "pps-gpio";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pps&gt;;</div><div class='add'>+		gpios = &lt;&amp;gpio4 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* off-board header */</div><div class='add'>+&amp;ecspi2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_spi2&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 13 GPIO_ACTIVE_LOW&gt;,</div><div class='add'>+		   &lt;&amp;gpio1 10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	tpm@1 {</div><div class='add'>+		compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";</div><div class='add'>+		reg = &lt;0x1&gt;;</div><div class='add'>+		spi-max-frequency = &lt;25000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"dio1", "", "", "dio0",</div><div class='add'>+		"", "", "pci_usb_sel", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"dio3", "", "dio2", "",</div><div class='add'>+		"pci_wdis#", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	accelerometer@19 {</div><div class='add'>+		compatible = "st,lis2de12";</div><div class='add'>+		reg = &lt;0x19&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_accel&gt;;</div><div class='add'>+		st,drdy-int-pin = &lt;1&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;21 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	fsl,refclk-pad-mode = &lt;IMX8_PCIE_REFCLK_PAD_INPUT&gt;;</div><div class='add'>+	fsl,clkreq-unsupported;</div><div class='add'>+	clocks = &lt;&amp;pcie0_refclk&gt;;</div><div class='add'>+	clock-names = "ref";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie0&gt;;</div><div class='add'>+	reset-gpio = &lt;&amp;gpio4 29 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* GPS */</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* off-board header */</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB1 Type-C front panel */</div><div class='add'>+&amp;usb3_0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usb1&gt;;</div><div class='add'>+	fsl,over-current-active-low;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_0 {</div><div class='add'>+	/* dual role is implemented but not a full featured OTG */</div><div class='add'>+	adp-disable;</div><div class='add'>+	hnp-disable;</div><div class='add'>+	srp-disable;</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	role-switch-default-mode = "peripheral";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	port {</div><div class='add'>+		usb3_dwc: endpoint {</div><div class='add'>+			remote-endpoint = &lt;&amp;usb_dr_connector&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB2 - MiniPCIe socket */</div><div class='add'>+&amp;usb3_1 {</div><div class='add'>+	fsl,permanently-attached;</div><div class='add'>+	fsl,disable-port-power-control;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_1 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hog&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl_hog: hoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08	0x40000146 /* DIO1 */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11	0x40000146 /* DIO0 */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14	0x40000106 /* PCIE_USBSEL */</div><div class='add'>+			MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26	0x40000146 /* DIO2 */</div><div class='add'>+			MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24	0x40000146 /* DIO3 */</div><div class='add'>+			MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28	0x40000106 /* PCIE_WDIS# */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_accel: accelgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21	0x150	/* IRQ */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio_leds: gpioledgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01	0x6	/* LEDG */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05	0x6	/* LEDR */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie0: pcie0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29	0x106</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pps: ppsgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03	0x146</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usb1: usb1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC	0x140 /* USB1_FLT# */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usbcon1: usbcon1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21	0x140 /* USB1_ID */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_spi2: spi2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK	0x140</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI	0x140</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO	0x140</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13	0x140</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX	0x140</div><div class='add'>+			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: uart3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX	0x140</div><div class='add'>+			MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx-2x.dts b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx-2x.dts<br/>new file mode 100644<br/>index 000000000000..255e36f66b00<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx-2x.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx-2x.dts</a></div><div class='hunk'>@@ -0,0 +1,19 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Gateworks Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mp.dtsi"</div><div class='add'>+#include "imx8mp-venice-gw702x.dtsi"</div><div class='add'>+#include "imx8mp-venice-gw72xx.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Gateworks Venice GW72xx-2x i.MX8MP Development Kit";</div><div class='add'>+	compatible = "gateworks,imx8mp-gw72xx-2x", "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart2;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi<br/>new file mode 100644<br/>index 000000000000..76020ef89bf3<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi</a></div><div class='hunk'>@@ -0,0 +1,415 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Gateworks Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/phy/phy-imx8-pcie.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet1 = &amp;eth1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	connector {</div><div class='add'>+		compatible = "gpio-usb-b-connector", "usb-b-connector";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usbcon1&gt;;</div><div class='add'>+		type = "micro";</div><div class='add'>+		label = "otg";</div><div class='add'>+		vbus-supply = &lt;&amp;reg_usb1_vbus&gt;;</div><div class='add'>+		id-gpios = &lt;&amp;gpio3 21 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			usb_dr_connector: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;usb3_dwc&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	led-controller {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_leds&gt;;</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio4 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "on";</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio4 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_refclk: clock-pcie0 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;100000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pps {</div><div class='add'>+		compatible = "pps-gpio";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pps&gt;;</div><div class='add'>+		gpios = &lt;&amp;gpio4 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb1_vbus: regulator-usb1 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usb1_en&gt;;</div><div class='add'>+		regulator-name = "usb1_vbus";</div><div class='add'>+		gpio = &lt;&amp;gpio1 12 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb2_vbus: regulator-usb2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usb2_en&gt;;</div><div class='add'>+		regulator-name = "usb2_vbus";</div><div class='add'>+		gpio = &lt;&amp;gpio4 12 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usdhc2_vmmc&gt;;</div><div class='add'>+		regulator-name = "VDD_3V3_SD";</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;gpio2 19 0&gt;; /* SD2_RESET */</div><div class='add'>+		off-on-delay-us = &lt;12000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		startup-delay-us = &lt;100&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* off-board header */</div><div class='add'>+&amp;ecspi2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_spi2&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 13 GPIO_ACTIVE_LOW&gt;,</div><div class='add'>+		   &lt;&amp;gpio1 10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	tpm@1 {</div><div class='add'>+		compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";</div><div class='add'>+		reg = &lt;0x1&gt;;</div><div class='add'>+		spi-max-frequency = &lt;25000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"dio1", "", "", "dio0",</div><div class='add'>+		"", "", "pci_usb_sel", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "rs485_en", "rs485_term",</div><div class='add'>+		"", "", "", "rs485_half",</div><div class='add'>+		"pci_wdis#", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	accelerometer@19 {</div><div class='add'>+		compatible = "st,lis2de12";</div><div class='add'>+		reg = &lt;0x19&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_accel&gt;;</div><div class='add'>+		st,drdy-int-pin = &lt;1&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;21 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	fsl,refclk-pad-mode = &lt;IMX8_PCIE_REFCLK_PAD_INPUT&gt;;</div><div class='add'>+	fsl,clkreq-unsupported;</div><div class='add'>+	clocks = &lt;&amp;pcie0_refclk&gt;;</div><div class='add'>+	clock-names = "ref";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie0&gt;;</div><div class='add'>+	reset-gpio = &lt;&amp;gpio4 29 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pcie@0,0 {</div><div class='add'>+		reg = &lt;0x0000 0 0 0 0&gt;;</div><div class='add'>+		device_type = "pci";</div><div class='add'>+		#address-cells = &lt;3&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		pcie@0,0 {</div><div class='add'>+			reg = &lt;0x0000 0 0 0 0&gt;;</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			pcie@3,0 {</div><div class='add'>+				reg = &lt;0x1800 0 0 0 0&gt;;</div><div class='add'>+				device_type = "pci";</div><div class='add'>+				#address-cells = &lt;3&gt;;</div><div class='add'>+				#size-cells = &lt;2&gt;;</div><div class='add'>+				ranges;</div><div class='add'>+</div><div class='add'>+				eth1: ethernet@0,0 {</div><div class='add'>+					reg = &lt;0x0000 0 0 0 0&gt;;</div><div class='add'>+					#address-cells = &lt;3&gt;;</div><div class='add'>+					#size-cells = &lt;2&gt;;</div><div class='add'>+					ranges;</div><div class='add'>+					local-mac-address = [00 00 00 00 00 00];</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* GPS */</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* off-board header */</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* RS232 */</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB1 - OTG */</div><div class='add'>+&amp;usb3_0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usb1&gt;;</div><div class='add'>+	fsl,over-current-active-low;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_0 {</div><div class='add'>+	/* dual role is implemented but not a full featured OTG */</div><div class='add'>+	adp-disable;</div><div class='add'>+	hnp-disable;</div><div class='add'>+	srp-disable;</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	role-switch-default-mode = "peripheral";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	port {</div><div class='add'>+		usb3_dwc: endpoint {</div><div class='add'>+			remote-endpoint = &lt;&amp;usb_dr_connector&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB2 - USB3.0 Hub */</div><div class='add'>+&amp;usb3_1 {</div><div class='add'>+	fsl,permanently-attached;</div><div class='add'>+	fsl,disable-port-power-control;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy1 {</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usb2_vbus&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_1 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* microSD */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hog&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl_hog: hoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08	0x40000146 /* DIO1 */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11	0x40000146 /* DIO0 */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14	0x40000106 /* PCIE_USBSEL */</div><div class='add'>+			MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27	0x40000106 /* RS485_HALF */</div><div class='add'>+			MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22	0x40000106 /* RS485_EN */</div><div class='add'>+			MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23	0x40000106 /* RS485_TERM */</div><div class='add'>+			MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28	0x40000106 /* PCIE_WDIS# */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_accel: accelgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21	0x150	/* IRQ */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio_leds: gpioledgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01	0x6	/* LEDG */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05	0x6	/* LEDR */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie0: pcie0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29	0x106</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pps: ppsgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03	0x146</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usb1_en: regusb1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12	0x146 /* USB1_EN */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usb1: usb1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC	0x140 /* USB1_FLT# */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usbcon1: usbcon1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21	0x140 /* USB1_ID */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usb2_en: regusb2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12	0x146 /* USBHUB_RST# */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_spi2: spi2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK	0x140</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI	0x140</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO	0x140</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13	0x140</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX	0x140</div><div class='add'>+			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: uart3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX	0x140</div><div class='add'>+			MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart4: uart4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX	0x140</div><div class='add'>+			MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x190</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x194</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x196</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_RESET_B__USDHC2_RESET_B	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12		0x1c4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx-2x.dts b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx-2x.dts<br/>new file mode 100644<br/>index 000000000000..000fd15e0c07<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx-2x.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx-2x.dts</a></div><div class='hunk'>@@ -0,0 +1,19 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Gateworks Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mp.dtsi"</div><div class='add'>+#include "imx8mp-venice-gw702x.dtsi"</div><div class='add'>+#include "imx8mp-venice-gw73xx.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Gateworks Venice GW73xx-2x i.MX8MP Development Kit";</div><div class='add'>+	compatible = "gateworks,imx8mp-gw73xx-2x", "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart2;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi<br/>new file mode 100644<br/>index 000000000000..5eb114d2360a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi</a></div><div class='hunk'>@@ -0,0 +1,468 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Gateworks Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/phy/phy-imx8-pcie.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet1 = &amp;eth1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	connector {</div><div class='add'>+		compatible = "gpio-usb-b-connector", "usb-b-connector";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usbcon1&gt;;</div><div class='add'>+		type = "micro";</div><div class='add'>+		label = "otg";</div><div class='add'>+		vbus-supply = &lt;&amp;reg_usb1_vbus&gt;;</div><div class='add'>+		id-gpios = &lt;&amp;gpio3 21 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			usb_dr_connector: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;usb3_dwc&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	led-controller {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_leds&gt;;</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio4 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "on";</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio4 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_refclk: clock-pcie0 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;100000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pps {</div><div class='add'>+		compatible = "pps-gpio";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pps&gt;;</div><div class='add'>+		gpios = &lt;&amp;gpio4 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb1_vbus: regulator-usb1 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usb1_en&gt;;</div><div class='add'>+		regulator-name = "usb1_vbus";</div><div class='add'>+		gpio = &lt;&amp;gpio1 12 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb2_vbus: regulator-usb2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usb2_en&gt;;</div><div class='add'>+		regulator-name = "usb2_vbus";</div><div class='add'>+		gpio = &lt;&amp;gpio4 12 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_wifi_en: regulator-wifi-en {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_wl&gt;;</div><div class='add'>+		regulator-name = "wl";</div><div class='add'>+		gpio = &lt;&amp;gpio4 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		startup-delay-us = &lt;100&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usdhc2_vmmc&gt;;</div><div class='add'>+		regulator-name = "VDD_3V3_SD";</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;gpio2 19 0&gt;; /* SD2_RESET */</div><div class='add'>+		off-on-delay-us = &lt;12000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		startup-delay-us = &lt;100&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* off-board header */</div><div class='add'>+&amp;ecspi2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_spi2&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 13 GPIO_ACTIVE_LOW&gt;,</div><div class='add'>+		   &lt;&amp;gpio1 10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	tpm@1 {</div><div class='add'>+		compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";</div><div class='add'>+		reg = &lt;0x1&gt;;</div><div class='add'>+		spi-max-frequency = &lt;25000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"dio1", "", "", "dio0",</div><div class='add'>+		"", "", "pci_usb_sel", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "rs485_en", "rs485_term",</div><div class='add'>+		"", "", "", "rs485_half",</div><div class='add'>+		"pci_wdis#", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	accelerometer@19 {</div><div class='add'>+		compatible = "st,lis2de12";</div><div class='add'>+		reg = &lt;0x19&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_accel&gt;;</div><div class='add'>+		st,drdy-int-pin = &lt;1&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;21 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	fsl,refclk-pad-mode = &lt;IMX8_PCIE_REFCLK_PAD_INPUT&gt;;</div><div class='add'>+	fsl,clkreq-unsupported;</div><div class='add'>+	clocks = &lt;&amp;pcie0_refclk&gt;;</div><div class='add'>+	clock-names = "ref";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie0&gt;;</div><div class='add'>+	reset-gpio = &lt;&amp;gpio4 29 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pcie@0,0 {</div><div class='add'>+		reg = &lt;0x0000 0 0 0 0&gt;;</div><div class='add'>+		device_type = "pci";</div><div class='add'>+		#address-cells = &lt;3&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		pcie@0,0 {</div><div class='add'>+			reg = &lt;0x0000 0 0 0 0&gt;;</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			pcie@4,0 {</div><div class='add'>+				reg = &lt;0x2000 0 0 0 0&gt;;</div><div class='add'>+				device_type = "pci";</div><div class='add'>+				#address-cells = &lt;3&gt;;</div><div class='add'>+				#size-cells = &lt;2&gt;;</div><div class='add'>+				ranges;</div><div class='add'>+</div><div class='add'>+				eth1: ethernet@0,0 {</div><div class='add'>+					reg = &lt;0x0000 0 0 0 0&gt;;</div><div class='add'>+					#address-cells = &lt;3&gt;;</div><div class='add'>+					#size-cells = &lt;2&gt;;</div><div class='add'>+					ranges;</div><div class='add'>+					local-mac-address = [00 00 00 00 00 00];</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* GPS */</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* bluetooth HCI */</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;, &lt;&amp;pinctrl_bten&gt;;</div><div class='add'>+	cts-gpios = &lt;&amp;gpio5 8 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	rts-gpios = &lt;&amp;gpio5 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "brcm,bcm4330-bt";</div><div class='add'>+		shutdown-gpios = &lt;&amp;gpio1 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* RS232 */</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB1 - OTG */</div><div class='add'>+&amp;usb3_0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usb1&gt;;</div><div class='add'>+	fsl,over-current-active-low;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_0 {</div><div class='add'>+	/* dual role is implemented but not a full featured OTG */</div><div class='add'>+	adp-disable;</div><div class='add'>+	hnp-disable;</div><div class='add'>+	srp-disable;</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	role-switch-default-mode = "peripheral";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	port {</div><div class='add'>+		usb3_dwc: endpoint {</div><div class='add'>+			remote-endpoint = &lt;&amp;usb_dr_connector&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB2 - USB3.0 Hub */</div><div class='add'>+&amp;usb3_1 {</div><div class='add'>+	fsl,permanently-attached;</div><div class='add'>+	fsl,disable-port-power-control;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy1 {</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usb2_vbus&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_1 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SDIO WiFi */</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_wifi_en&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* microSD */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hog&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl_hog: hoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08	0x40000146 /* DIO1 */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11	0x40000146 /* DIO0 */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14	0x40000106 /* PCIE_USBSEL */</div><div class='add'>+			MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27	0x40000106 /* RS485_HALF */</div><div class='add'>+			MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22	0x40000106 /* RS485_EN */</div><div class='add'>+			MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23	0x40000106 /* RS485_TERM */</div><div class='add'>+			MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28	0x40000106 /* PCIE_WDIS# */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_accel: accelgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21	0x150	/* IRQ */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_bten: btengrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16	0x146</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio_leds: gpioledgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01	0x6	/* LEDG */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05	0x6	/* LEDR */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie0: pcie0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29	0x106</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pps: ppsgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03	0x146</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_wl: regwlgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19	0x146</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usb1_en: regusb1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12	0x146 /* USB1_EN */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usb1: usb1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC	0x140 /* USB1_FLT# */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usbcon1: usbcon1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21	0x140 /* USB1_ID */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usb2_en: regusb2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12	0x146 /* USBHUB_RST# */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_spi2: spi2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK	0x140</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI	0x140</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO	0x140</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX	0x140</div><div class='add'>+			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: uart3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX	0x140</div><div class='add'>+			MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX	0x140</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08	0x140</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart4: uart4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX	0x140</div><div class='add'>+			MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x190</div><div class='add'>+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x190</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x194</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x196</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_RESET_B__USDHC2_RESET_B	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12		0x1c4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx-imx219.dtso b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx-imx219.dtso<br/>new file mode 100644<br/>index 000000000000..7d9fcdee58a7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx-imx219.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx-imx219.dtso</a></div><div class='hunk'>@@ -0,0 +1,107 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Gateworks Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+</div><div class='add'>+#include "imx8mp-pinfunc.h"</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+&amp;{/} {</div><div class='add'>+	reg_vana: regulator-2p8v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "2P8V";</div><div class='add'>+		regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vddl: regulator-1p2v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "1P2V";</div><div class='add'>+		regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_cam: regulator-cam {</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_cam&gt;;</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "reg_cam";</div><div class='add'>+		gpio = &lt;&amp;gpio1 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cam24m: cam24m {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+		clock-output-names = "cam24m";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	imx219: sensor@10 {</div><div class='add'>+		compatible = "sony,imx219";</div><div class='add'>+		reg = &lt;0x10&gt;;</div><div class='add'>+		clocks = &lt;&amp;cam24m&gt;;</div><div class='add'>+		VDIG-supply = &lt;&amp;reg_cam&gt;;</div><div class='add'>+		VANA-supply = &lt;&amp;reg_vana&gt;;</div><div class='add'>+		VDDL-supply = &lt;&amp;reg_vddl&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			/* MIPI CSI-2 bus endpoint */</div><div class='add'>+			imx219_to_mipi_csi2: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;mipi_csi_0_in&gt;;</div><div class='add'>+				clock-lanes = &lt;0&gt;;</div><div class='add'>+				data-lanes = &lt;1 2&gt;;</div><div class='add'>+				link-frequencies = /bits/ 64 &lt;456000000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;isi_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_csi_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		port@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			mipi_csi_0_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;imx219_to_mipi_csi2&gt;;</div><div class='add'>+				data-lanes = &lt;1 2&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			mipi_csi_0_out: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;isi_in_0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_reg_cam: regcamgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04	0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx-rpidsi.dtso b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx-rpidsi.dtso<br/>new file mode 100644<br/>index 000000000000..6a39f43435c2<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx-rpidsi.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx-rpidsi.dtso</a></div><div class='hunk'>@@ -0,0 +1,87 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Gateworks Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+&amp;{/} {</div><div class='add'>+	compatible = "gateworks,imx8mp-gw74xx", "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	panel {</div><div class='add'>+		compatible = "powertip,ph800480t013-idf02";</div><div class='add'>+		power-supply = &lt;&amp;attiny&gt;;</div><div class='add'>+		backlight = &lt;&amp;attiny&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			panel_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;bridge_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	attiny: regulator@45 {</div><div class='add'>+		compatible = "raspberrypi,7inch-touchscreen-panel-regulator";</div><div class='add'>+		reg = &lt;0x45&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_dsi {</div><div class='add'>+	samsung,burst-clock-frequency = &lt;891000000&gt;;</div><div class='add'>+	samsung,esc-clock-frequency = &lt;54000000&gt;;</div><div class='add'>+	samsung,pll-clock-frequency = &lt;27000000&gt;;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bridge@0 {</div><div class='add'>+		compatible = "toshiba,tc358762";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		vddc-supply = &lt;&amp;attiny&gt;;</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				bridge_in: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;dsi_out&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				bridge_out: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;panel_in&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			dsi_out: endpoint {</div><div class='add'>+				data-lanes = &lt;1 2&gt;;</div><div class='add'>+				remote-endpoint = &lt;&amp;bridge_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts<br/>new file mode 100644<br/>index 000000000000..7662663ff5da<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts</a></div><div class='hunk'>@@ -0,0 +1,1159 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021 Gateworks Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/linux-event-codes.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/phy/phy-imx8-pcie.h&gt;</div><div class='add'>+#include &lt;dt-bindings/net/ti-dp83867.h&gt;</div><div class='add'>+</div><div class='add'>+#include "imx8mp.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Gateworks Venice GW74xx i.MX8MP board";</div><div class='add'>+	compatible = "gateworks,imx8mp-gw74xx", "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;eqos;</div><div class='add'>+		ethernet1 = &amp;fec;</div><div class='add'>+		ethernet2 = &amp;lan1;</div><div class='add'>+		ethernet3 = &amp;lan2;</div><div class='add'>+		ethernet4 = &amp;lan3;</div><div class='add'>+		ethernet5 = &amp;lan4;</div><div class='add'>+		ethernet6 = &amp;lan5;</div><div class='add'>+		rtc0 = &amp;gsc_rtc;</div><div class='add'>+		rtc1 = &amp;snvs_rtc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x40000000 0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	connector {</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usbcon1&gt;;</div><div class='add'>+		compatible = "gpio-usb-b-connector", "usb-b-connector";</div><div class='add'>+		type = "micro";</div><div class='add'>+		label = "Type-C";</div><div class='add'>+		id-gpios = &lt;&amp;gpio1 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			usb_dr_connector: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;usb3_dwc&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		key-0 {</div><div class='add'>+			label = "user_pb";</div><div class='add'>+			gpios = &lt;&amp;gpio 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;BTN_0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-1 {</div><div class='add'>+			label = "user_pb1x";</div><div class='add'>+			linux,code = &lt;BTN_1&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gsc&gt;;</div><div class='add'>+			interrupts = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-2 {</div><div class='add'>+			label = "key_erased";</div><div class='add'>+			linux,code = &lt;BTN_2&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gsc&gt;;</div><div class='add'>+			interrupts = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-3 {</div><div class='add'>+			label = "eeprom_wp";</div><div class='add'>+			linux,code = &lt;BTN_3&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gsc&gt;;</div><div class='add'>+			interrupts = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-4 {</div><div class='add'>+			label = "tamper";</div><div class='add'>+			linux,code = &lt;BTN_4&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gsc&gt;;</div><div class='add'>+			interrupts = &lt;5&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-5 {</div><div class='add'>+			label = "switch_hold";</div><div class='add'>+			linux,code = &lt;BTN_5&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gsc&gt;;</div><div class='add'>+			interrupts = &lt;7&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	led-controller {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_leds&gt;;</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			function = LED_FUNCTION_HEARTBEAT;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio2 15 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "on";</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio2 16 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_refclk: pcie0-refclk {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;100000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pps {</div><div class='add'>+		compatible = "pps-gpio";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pps&gt;;</div><div class='add'>+		gpios = &lt;&amp;gpio1 12 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb2_vbus: regulator-usb2 {</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usb2&gt;;</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "usb_usb2_vbus";</div><div class='add'>+		gpio = &lt;&amp;gpio1 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_can1_stby: regulator-can1-stby {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_can1&gt;;</div><div class='add'>+		regulator-name = "can1_stby";</div><div class='add'>+		gpio = &lt;&amp;gpio3 19 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_can2_stby: regulator-can2-stby {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_can2&gt;;</div><div class='add'>+		regulator-name = "can2_stby";</div><div class='add'>+		gpio = &lt;&amp;gpio5 5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_wifi_en: regulator-wifi-en {</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_wifi&gt;;</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "wl";</div><div class='add'>+		gpio = &lt;&amp;gpio3 9 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		startup-delay-us = &lt;70000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_spi1&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	tpm@0 {</div><div class='add'>+		compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";</div><div class='add'>+		reg = &lt;0x0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;25000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* off-board header */</div><div class='add'>+&amp;ecspi2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_spi2&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 13 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eqos {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_eqos&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@0 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;0x0&gt;;</div><div class='add'>+			ti,clk-output-sel = &lt;DP83867_CLK_O_SEL_OFF&gt;;</div><div class='add'>+			ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_2_00_NS&gt;;</div><div class='add'>+			ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_2_00_NS&gt;;</div><div class='add'>+			tx-fifo-depth = &lt;DP83867_PHYCR_FIFO_DEPTH_4_B_NIB&gt;;</div><div class='add'>+			rx-fifo-depth = &lt;DP83867_PHYCR_FIFO_DEPTH_4_B_NIB&gt;;</div><div class='add'>+</div><div class='add'>+			leds {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				led@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					color = &lt;LED_COLOR_ID_AMBER&gt;;</div><div class='add'>+					function = LED_FUNCTION_LAN;</div><div class='add'>+					default-state = "keep";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				led@2 {</div><div class='add'>+					reg = &lt;2&gt;;</div><div class='add'>+					color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+					function = LED_FUNCTION_LAN;</div><div class='add'>+					default-state = "keep";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	local-mac-address = [00 00 00 00 00 00];</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	fixed-link {</div><div class='add'>+		speed = &lt;1000&gt;;</div><div class='add'>+		full-duplex;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan1&gt;;</div><div class='add'>+	xceiver-supply = &lt;&amp;reg_can1_stby&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan2&gt;;</div><div class='add'>+	xceiver-supply = &lt;&amp;reg_can2_stby&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "dio0", "", "dio1", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio2 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"", "", "", "", "", "", "m2_pin20", "",</div><div class='add'>+		"", "", "", "", "", "pcie1_wdis#", "pcie3_wdis#", "",</div><div class='add'>+		"", "", "pcie2_wdis#", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio3 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"", "", "", "", "", "", "m2_rst", "",</div><div class='add'>+		"", "", "", "", "", "", "m2_wdis2#", "",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"", "", "m2_off#", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "m2_wdis1#", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "rs485_en";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio5 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"rs485_hd", "rs485_term", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "",</div><div class='add'>+		"", "", "", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c1_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	gsc: gsc@20 {</div><div class='add'>+		compatible = "gw,gsc";</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gsc&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;20 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		adc {</div><div class='add'>+			compatible = "gw,gsc-adc";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			channel@6 {</div><div class='add'>+				gw,mode = &lt;0&gt;;</div><div class='add'>+				reg = &lt;0x06&gt;;</div><div class='add'>+				label = "temp";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@8 {</div><div class='add'>+				gw,mode = &lt;3&gt;;</div><div class='add'>+				reg = &lt;0x08&gt;;</div><div class='add'>+				label = "vdd_bat";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@16 {</div><div class='add'>+				gw,mode = &lt;4&gt;;</div><div class='add'>+				reg = &lt;0x16&gt;;</div><div class='add'>+				label = "fan_tach";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@82 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x82&gt;;</div><div class='add'>+				label = "vdd_adc1";</div><div class='add'>+				gw,voltage-divider-ohms = &lt;10000 10000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@84 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x84&gt;;</div><div class='add'>+				label = "vdd_adc2";</div><div class='add'>+				gw,voltage-divider-ohms = &lt;10000 10000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@86 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x86&gt;;</div><div class='add'>+				label = "vdd_vin";</div><div class='add'>+				gw,voltage-divider-ohms = &lt;22100 1000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@88 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x88&gt;;</div><div class='add'>+				label = "vdd_3p3";</div><div class='add'>+				gw,voltage-divider-ohms = &lt;10000 10000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@8c {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x8c&gt;;</div><div class='add'>+				label = "vdd_2p5";</div><div class='add'>+				gw,voltage-divider-ohms = &lt;10000 10000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@90 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x90&gt;;</div><div class='add'>+				label = "vdd_soc";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@92 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x92&gt;;</div><div class='add'>+				label = "vdd_arm";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@98 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x98&gt;;</div><div class='add'>+				label = "vdd_1p8";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@9a {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x9a&gt;;</div><div class='add'>+				label = "vdd_1p2";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@9c {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x9c&gt;;</div><div class='add'>+				label = "vdd_dram";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@9e {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x9e&gt;;</div><div class='add'>+				label = "vdd_1p0";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			channel@a2 {</div><div class='add'>+				gw,mode = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0xa2&gt;;</div><div class='add'>+				label = "vdd_gsc";</div><div class='add'>+				gw,voltage-divider-ohms = &lt;10000 10000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		fan-controller@a {</div><div class='add'>+			compatible = "gw,gsc-fan";</div><div class='add'>+			reg = &lt;0x0a&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio: gpio@23 {</div><div class='add'>+		compatible = "nxp,pca9555";</div><div class='add'>+		reg = &lt;0x23&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gsc&gt;;</div><div class='add'>+		interrupts = &lt;4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@50 {</div><div class='add'>+		compatible = "atmel,24c02";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@51 {</div><div class='add'>+		compatible = "atmel,24c02";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@52 {</div><div class='add'>+		compatible = "atmel,24c02";</div><div class='add'>+		reg = &lt;0x52&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@53 {</div><div class='add'>+		compatible = "atmel,24c02";</div><div class='add'>+		reg = &lt;0x53&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gsc_rtc: rtc@68 {</div><div class='add'>+		compatible = "dallas,ds1672";</div><div class='add'>+		reg = &lt;0x68&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c2_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	accelerometer@19 {</div><div class='add'>+		compatible = "st,lis2de12";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_accel&gt;;</div><div class='add'>+		reg = &lt;0x19&gt;;</div><div class='add'>+		st,drdy-int-pin = &lt;1&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;7 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	switch: switch@5f {</div><div class='add'>+		compatible = "microchip,ksz9897";</div><div class='add'>+		reg = &lt;0x5f&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_ksz&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;29 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			lan1: port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				label = "lan1";</div><div class='add'>+				phy-mode = "internal";</div><div class='add'>+				local-mac-address = [00 00 00 00 00 00];</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lan2: port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				label = "lan2";</div><div class='add'>+				phy-mode = "internal";</div><div class='add'>+				local-mac-address = [00 00 00 00 00 00];</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lan3: port@2 {</div><div class='add'>+				reg = &lt;2&gt;;</div><div class='add'>+				label = "lan3";</div><div class='add'>+				phy-mode = "internal";</div><div class='add'>+				local-mac-address = [00 00 00 00 00 00];</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lan4: port@3 {</div><div class='add'>+				reg = &lt;3&gt;;</div><div class='add'>+				label = "lan4";</div><div class='add'>+				phy-mode = "internal";</div><div class='add'>+				local-mac-address = [00 00 00 00 00 00];</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lan5: port@4 {</div><div class='add'>+				reg = &lt;4&gt;;</div><div class='add'>+				label = "lan5";</div><div class='add'>+				phy-mode = "internal";</div><div class='add'>+				local-mac-address = [00 00 00 00 00 00];</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@5 {</div><div class='add'>+				reg = &lt;5&gt;;</div><div class='add'>+				ethernet = &lt;&amp;fec&gt;;</div><div class='add'>+				phy-mode = "rgmii-id";</div><div class='add'>+</div><div class='add'>+				fixed-link {</div><div class='add'>+					speed = &lt;1000&gt;;</div><div class='add'>+					full-duplex;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c3_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pmic@25 {</div><div class='add'>+		compatible = "nxp,pca9450c";</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+		interrupts = &lt;7 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			BUCK1 {</div><div class='add'>+				regulator-name = "BUCK1";</div><div class='add'>+				regulator-min-microvolt = &lt;720000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_arm: BUCK2 {</div><div class='add'>+				regulator-name = "BUCK2";</div><div class='add'>+				regulator-min-microvolt = &lt;720000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1025000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+				nxp,dvs-run-voltage = &lt;950000&gt;;</div><div class='add'>+				nxp,dvs-standby-voltage = &lt;850000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			BUCK4 {</div><div class='add'>+				regulator-name = "BUCK4";</div><div class='add'>+				regulator-min-microvolt = &lt;3000000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3600000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			BUCK5 {</div><div class='add'>+				regulator-name = "BUCK5";</div><div class='add'>+				regulator-min-microvolt = &lt;1650000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1950000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			BUCK6 {</div><div class='add'>+				regulator-name = "BUCK6";</div><div class='add'>+				regulator-min-microvolt = &lt;1045000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1155000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			LDO1 {</div><div class='add'>+				regulator-name = "LDO1";</div><div class='add'>+				regulator-min-microvolt = &lt;1650000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1950000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			LDO3 {</div><div class='add'>+				regulator-name = "LDO3";</div><div class='add'>+				regulator-min-microvolt = &lt;1710000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1890000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			LDO5 {</div><div class='add'>+				regulator-name = "LDO5";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* off-board header */</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c4&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c4_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	fsl,refclk-pad-mode = &lt;IMX8_PCIE_REFCLK_PAD_INPUT&gt;;</div><div class='add'>+	fsl,clkreq-unsupported;</div><div class='add'>+	clocks = &lt;&amp;pcie0_refclk&gt;;</div><div class='add'>+	clock-names = "ref";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie0&gt;;</div><div class='add'>+	reset-gpio = &lt;&amp;gpio2 17 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* GPS / off-board header */</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* RS232 console */</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* bluetooth HCI */</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;, &lt;&amp;pinctrl_uart3_gpio&gt;;</div><div class='add'>+	cts-gpios = &lt;&amp;gpio3 21 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	rts-gpios = &lt;&amp;gpio3 22 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "brcm,bcm4330-bt";</div><div class='add'>+		shutdown-gpios = &lt;&amp;gpio3 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB1 - Type C front panel */</div><div class='add'>+&amp;usb3_0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usb1&gt;;</div><div class='add'>+	fsl,over-current-active-low;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_0 {</div><div class='add'>+	/* dual role is implemented but not a full featured OTG */</div><div class='add'>+	adp-disable;</div><div class='add'>+	hnp-disable;</div><div class='add'>+	srp-disable;</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	role-switch-default-mode = "peripheral";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	port {</div><div class='add'>+		usb3_dwc: endpoint {</div><div class='add'>+			remote-endpoint = &lt;&amp;usb_dr_connector&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB2 - USB3.0 Hub */</div><div class='add'>+&amp;usb3_phy1 {</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usb2_vbus&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_1 {</div><div class='add'>+	fsl,permanently-attached;</div><div class='add'>+	fsl,disable-port-power-control;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_1 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SDIO WiFi */</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1_200mhz&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_wifi_en&gt;;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	wifi@0 {</div><div class='add'>+		compatible = "cypress,cyw4373-fmac", "brcm,bcm4329-fmac";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* eMMC */</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_USDHC3&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hog&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl_hog: hoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09	0x40000040 /* DIO0 */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11	0x40000040 /* DIO1 */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02	0x40000040 /* M2SKT_OFF# */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18	0x40000150 /* M2SKT_WDIS1# */</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06	0x40000040 /* M2SKT_PIN20 */</div><div class='add'>+			MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11	0x40000040 /* M2SKT_PIN22 */</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__GPIO2_IO13	0x40000150 /* PCIE1_WDIS# */</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14	0x40000150 /* PCIE3_WDIS# */</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18	0x40000150 /* PCIE2_WDIS# */</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06	0x40000040 /* M2SKT_RST# */</div><div class='add'>+			MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14	0x40000150 /* M2KST_WDIS2# */</div><div class='add'>+			MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01	0x40000104 /* UART_TERM */</div><div class='add'>+			MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31	0x40000104 /* UART_RS485 */</div><div class='add'>+			MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00	0x40000104 /* UART_HALF */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_accel: accelgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07	0x150</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_eqos: eqosgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x2</div><div class='add'>+			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x2</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0		0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1		0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2		0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3		0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x90</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0		0x16</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1		0x16</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2		0x16</div><div class='add'>+			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3		0x16</div><div class='add'>+			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x16</div><div class='add'>+			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x16</div><div class='add'>+			MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30		0x140 /* RST# */</div><div class='add'>+			MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28		0x150 /* IRQ# */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec: fecgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x90</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x90</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x90</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x90</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x90</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x90</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x16</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x16</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x16</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x16</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x16</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x16</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN	0x140</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan1: flexcan1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SPDIF_RX__CAN1_RX		0x154</div><div class='add'>+			MX8MP_IOMUXC_SPDIF_TX__CAN1_TX		0x154</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan2: flexcan2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX		0x154</div><div class='add'>+			MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX		0x154</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gsc: gscgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20	0x150</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c2</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1_gpio: i2c1gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14	0x400001c2</div><div class='add'>+			MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15	0x400001c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001c2</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA		0x400001c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2_gpio: i2c2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16	0x400001c3</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17	0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400001c2</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3_gpio: i2c3gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18	0x400001c3</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19	0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4: i2c4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL		0x400001c2</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA		0x400001c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4_gpio: i2c4gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20	0x400001c3</div><div class='add'>+			MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21	0x400001c3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ksz: kszgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29	0x150 /* IRQ# */</div><div class='add'>+			MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02	0x140 /* RST# */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio_leds: ledgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15	0x10</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16	0x10</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie0: pciegrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17	0x106</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: pmicgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pps: ppsgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_can1: regcan1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19	0x154</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_can2: regcan2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05	0x154</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usb2: regusb2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_wifi: regwifigrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09	0x110</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_spi1: spi1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK	0x82</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI	0x82</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO	0x82</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_spi2: spi2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK	0x82</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI	0x82</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO	0x82</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX	0x140</div><div class='add'>+			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x140</div><div class='add'>+			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: uart3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX	0x140</div><div class='add'>+			MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX	0x140</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21	0x140</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3_gpio: uart3gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08	0x110</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart4: uart4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX	0x140</div><div class='add'>+			MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usb1: usb1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usbcon1: usb1congrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x190</div><div class='add'>+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x194</div><div class='add'>+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x196</div><div class='add'>+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x190</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x190</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x194</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x194</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x196</div><div class='add'>+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x196</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B	0x166</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw75xx-2x.dts b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw75xx-2x.dts<br/>new file mode 100644<br/>index 000000000000..7ca68df9e516<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-venice-gw75xx-2x.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-venice-gw75xx-2x.dts</a></div><div class='hunk'>@@ -0,0 +1,28 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Gateworks Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mp.dtsi"</div><div class='add'>+#include "imx8mp-venice-gw702x.dtsi"</div><div class='add'>+#include "imx8mp-venice-gw75xx.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Gateworks Venice GW75xx-2x i.MX8MP Development Kit";</div><div class='add'>+	compatible = "gateworks,imx8mp-gw75xx-2x", "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart2;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Disable SOM interfaces not used on baseboard */</div><div class='add'>+&amp;eqos {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw75xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw75xx.dtsi<br/>new file mode 100644<br/>index 000000000000..f90b293c85fc<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-venice-gw75xx.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-venice-gw75xx.dtsi</a></div><div class='hunk'>@@ -0,0 +1,325 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Gateworks Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/phy/phy-imx8-pcie.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	led-controller {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_leds&gt;;</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio4 22 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "on";</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio4 27 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_refclk: pcie0-refclk {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;100000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pps {</div><div class='add'>+		compatible = "pps-gpio";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pps&gt;;</div><div class='add'>+		gpios = &lt;&amp;gpio4 21 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb2_vbus: regulator-usb2-vbus {</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usb2_en&gt;;</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "usb2_vbus";</div><div class='add'>+		gpio = &lt;&amp;gpio4 12 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2 {</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usdhc2_vmmc&gt;;</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "SD2_3P3V";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio2 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* off-board header */</div><div class='add'>+&amp;ecspi2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_spi2&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 13 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "gpioa", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"", "gpiod", "", "",</div><div class='add'>+		"gpiob", "gpioc", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "pci_usb_sel", "",</div><div class='add'>+		"pci_wdis#", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	accelerometer@19 {</div><div class='add'>+		compatible = "st,lis2de12";</div><div class='add'>+		reg = &lt;0x19&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_accel&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio5&gt;;</div><div class='add'>+		interrupts = &lt;8 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		st,drdy-int-pin = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@52 {</div><div class='add'>+		compatible = "atmel,24c32";</div><div class='add'>+		reg = &lt;0x52&gt;;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* off-board header */</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	fsl,refclk-pad-mode = &lt;IMX8_PCIE_REFCLK_PAD_INPUT&gt;;</div><div class='add'>+	fsl,clkreq-unsupported;</div><div class='add'>+	clocks = &lt;&amp;pcie0_refclk&gt;;</div><div class='add'>+	clock-names = "ref";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie0&gt;;</div><div class='add'>+	reset-gpio = &lt;&amp;gpio4 29 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* GPS */</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB1 - Type C front panel SINK port J14 */</div><div class='add'>+&amp;usb3_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_0 {</div><div class='add'>+	dr_mode = "peripheral";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB2 4-port USB3.0 HUB:</div><div class='add'>+ *  P1 - USBC connector (host only)</div><div class='add'>+ *  P2 - USB2 test connector</div><div class='add'>+ *  P3 - miniPCIe full card</div><div class='add'>+ *  P4 - miniPCIe half card</div><div class='add'>+ */</div><div class='add'>+&amp;usb3_phy1 {</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usb2_vbus&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_1 {</div><div class='add'>+	fsl,permanently-attached;</div><div class='add'>+	fsl,disable-port-power-control;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_1 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* microSD */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hog&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl_hog: hoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13	0x40000040 /* GPIOA */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01	0x40000040 /* GPIOD */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04	0x40000040 /* GPIOB */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05	0x40000040 /* GPIOC */</div><div class='add'>+			MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26	0x40000106 /* PCI_USBSEL */</div><div class='add'>+			MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28	0x40000106 /* PCI_WDIS# */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_accel: accelgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08	0x159</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio_leds: gpioledgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22	0x6	/* LEDG */</div><div class='add'>+			MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27	0x6	/* LEDR */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001c2</div><div class='add'>+			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA		0x400001c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400001c2</div><div class='add'>+			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001c2</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie0: pciegrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29	0x106</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pps: ppsgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21	0x106</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usb2_en: regusb2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12	0x6 /* USBHUB_RST# (ext p/u) */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x40</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_spi2: spi2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK	0x140</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI	0x140</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO	0x140</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX	0x140</div><div class='add'>+			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x190</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d0</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x194</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d4</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x196</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d6</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12		0x1c4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw82xx-2x.dts b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw82xx-2x.dts<br/>new file mode 100644<br/>index 000000000000..597813308630<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-venice-gw82xx-2x.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-venice-gw82xx-2x.dts</a></div><div class='hunk'>@@ -0,0 +1,19 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 Gateworks Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mp.dtsi"</div><div class='add'>+#include "imx8mp-venice-gw702x.dtsi"</div><div class='add'>+#include "imx8mp-venice-gw82xx.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Gateworks Venice GW82xx-2x i.MX8MP Development Kit";</div><div class='add'>+	compatible = "gateworks,imx8mp-gw82xx-2x", "fsl,imx8mp";</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart2;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw82xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw82xx.dtsi<br/>new file mode 100644<br/>index 000000000000..2b86cc62a41a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-venice-gw82xx.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-venice-gw82xx.dtsi</a></div><div class='hunk'>@@ -0,0 +1,533 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 Gateworks Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/phy/phy-imx8-pcie.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet1 = &amp;eth1;</div><div class='add'>+		fsa1 = &amp;fsa0;</div><div class='add'>+		fsa2 = &amp;fsa1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	led-controller {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_leds&gt;;</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio4 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "on";</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio4 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_refclk: clock-pcie0 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;100000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pps {</div><div class='add'>+		compatible = "pps-gpio";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pps&gt;;</div><div class='add'>+		gpios = &lt;&amp;gpio4 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb2_vbus: regulator-usb2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usb2_en&gt;;</div><div class='add'>+		regulator-name = "usb2_vbus";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio4 12 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usdhc2_vmmc&gt;;</div><div class='add'>+		regulator-name = "VDD_3V3_SD";</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio2 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		off-on-delay-us = &lt;12000&gt;;</div><div class='add'>+		startup-delay-us = &lt;100&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_spi2&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio1 10 GPIO_ACTIVE_LOW&gt;,	/* CS0 onboard TPM */</div><div class='add'>+		   &lt;&amp;gpio5 13 GPIO_ACTIVE_LOW&gt;, /* CS1 off-board J32 SPI */</div><div class='add'>+		   &lt;&amp;gpio1 12 GPIO_ACTIVE_LOW&gt;, /* CS3 off-board J52 FSA1 */</div><div class='add'>+		   &lt;&amp;gpio4 26 GPIO_ACTIVE_LOW&gt;; /* CS2 off-board J51 FSA2 */</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	tpm@0 {</div><div class='add'>+		compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";</div><div class='add'>+		reg = &lt;0x0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;10000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_can1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_can2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "fsa2_gpio1", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"dio1", "fsa1_gpio2", "", "dio0",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "", "",</div><div class='add'>+		"", "", "rs485_en", "rs485_term",</div><div class='add'>+		"fsa2_gpio2", "fsa1_gpio1", "", "rs485_half",</div><div class='add'>+		"", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	accelerometer@19 {</div><div class='add'>+		compatible = "st,lis2de12";</div><div class='add'>+		reg = &lt;0x19&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_accel&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;21 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		st,drdy-int-pin = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	magnetometer@1e {</div><div class='add'>+		compatible = "st,lis2mdl";</div><div class='add'>+		reg = &lt;0x1e&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_mag&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;28 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	i2c-mux@70 {</div><div class='add'>+		compatible = "nxp,pca9548";</div><div class='add'>+		reg = &lt;0x70&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		/* J30 */</div><div class='add'>+		fsa1: i2c@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_fsa2i2c&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			gpio@20 {</div><div class='add'>+				compatible = "nxp,pca9555";</div><div class='add'>+				reg = &lt;0x20&gt;;</div><div class='add'>+				interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+				interrupts = &lt;4 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;2&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			eeprom@54 {</div><div class='add'>+				compatible = "atmel,24c02";</div><div class='add'>+				reg = &lt;0x54&gt;;</div><div class='add'>+				pagesize = &lt;16&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			eeprom@55 {</div><div class='add'>+				compatible = "atmel,24c02";</div><div class='add'>+				reg = &lt;0x55&gt;;</div><div class='add'>+				pagesize = &lt;16&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* J29 */</div><div class='add'>+		fsa0: i2c@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_fsa1i2c&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			gpio@20 {</div><div class='add'>+				compatible = "nxp,pca9555";</div><div class='add'>+				reg = &lt;0x20&gt;;</div><div class='add'>+				interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+				interrupts = &lt;14 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;2&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			eeprom@54 {</div><div class='add'>+				compatible = "atmel,24c02";</div><div class='add'>+				reg = &lt;0x54&gt;;</div><div class='add'>+				pagesize = &lt;16&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			eeprom@55 {</div><div class='add'>+				compatible = "atmel,24c02";</div><div class='add'>+				reg = &lt;0x55&gt;;</div><div class='add'>+				pagesize = &lt;16&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* J33 */</div><div class='add'>+		i2c@2 {</div><div class='add'>+			reg = &lt;2&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	clocks = &lt;&amp;pcie0_refclk&gt;;</div><div class='add'>+	clock-names = "ref";</div><div class='add'>+	fsl,refclk-pad-mode = &lt;IMX8_PCIE_REFCLK_PAD_INPUT&gt;;</div><div class='add'>+	fsl,clkreq-unsupported;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie0&gt;;</div><div class='add'>+	reset-gpio = &lt;&amp;gpio4 29 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pcie@0,0 {</div><div class='add'>+		reg = &lt;0x0000 0 0 0 0&gt;;</div><div class='add'>+		device_type = "pci";</div><div class='add'>+		#address-cells = &lt;3&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		pcie@0,0 {</div><div class='add'>+			reg = &lt;0x0000 0 0 0 0&gt;;</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			pcie@7,0 {</div><div class='add'>+				reg = &lt;0x3800 0 0 0 0&gt;;</div><div class='add'>+				device_type = "pci";</div><div class='add'>+				#address-cells = &lt;3&gt;;</div><div class='add'>+				#size-cells = &lt;2&gt;;</div><div class='add'>+				ranges;</div><div class='add'>+</div><div class='add'>+				eth1: ethernet@0,0 {</div><div class='add'>+					reg = &lt;0x0000 0 0 0 0&gt;;</div><div class='add'>+					#address-cells = &lt;3&gt;;</div><div class='add'>+					#size-cells = &lt;2&gt;;</div><div class='add'>+					ranges;</div><div class='add'>+					local-mac-address = [00 00 00 00 00 00];</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* GPS */</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* RS232 */</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB1 - FSA1 */</div><div class='add'>+&amp;usb3_0 {</div><div class='add'>+	fsl,permanently-attached;</div><div class='add'>+	fsl,disable-port-power-control;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_0 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB2 - USB3.0 Hub */</div><div class='add'>+&amp;usb3_1 {</div><div class='add'>+	fsl,permanently-attached;</div><div class='add'>+	fsl,disable-port-power-control;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy1 {</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usb2_vbus&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_1 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SDIO 1.8V */</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1_200mhz&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* microSD */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_HIGH&gt;; /* CD is active high */</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hog&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl_hog: hoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08	0x40000146 /* DIO1 */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11	0x40000146 /* DIO0 */</div><div class='add'>+			MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27	0x40000106 /* RS485_HALF */</div><div class='add'>+			MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22	0x40000106 /* RS485_EN */</div><div class='add'>+			MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23	0x40000106 /* RS485_TERM */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_accel: accelgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21	0x150	/* IRQ# */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_can1: can1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SPDIF_TX__CAN1_TX		0x154</div><div class='add'>+			MX8MP_IOMUXC_SPDIF_RX__CAN1_RX		0x154</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_can2: can2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX		0x154</div><div class='add'>+			MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX		0x154</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio_leds: gpioledgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01	0x6	/* LEDG */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05	0x6	/* LEDR */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fsa1i2c: fsa1i2cgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14	0x1d0		/* FSA1_ALERT# */</div><div class='add'>+			MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25	0x400001d0	/* FSA1_GPIO1 */</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD7__GPIO4_IO09	0x400001d0	/* FSA1_GPIO2 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fsa2i2c: fsa2i2cgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04	0x1d0		/* FSA2_ALERT# */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13	0x400001d0	/* FSA2_GPIO1 */</div><div class='add'>+			MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24	0x400001d0	/* FSA2_GPIO2 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_mag: maggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28	0x140	/* IRQ# */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie0: pcie0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29	0x106	/* PERST# */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pps: ppsgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03	0x146</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usb2_en: regusb2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12	0x146	/* USBHUB_RST# */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_spi2: spi2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK	0xd0</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI	0xd0</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO	0xd0</div><div class='add'>+			MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13	0x140	/* J32_CS */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10	0x140	/* TPM_CS */</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12	0x140	/* FSA1_CS */</div><div class='add'>+			MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26	0x140	/* FSA2_CS */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX	0x140</div><div class='add'>+			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart4: uart4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX	0x140</div><div class='add'>+			MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX	0x140</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x190</div><div class='add'>+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x194</div><div class='add'>+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x196</div><div class='add'>+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x190</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d0</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x194</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d4</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x196</div><div class='add'>+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d6</div><div class='add'>+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x1d0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12	0x1c4</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi<br/>new file mode 100644<br/>index 000000000000..1493319aa748<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi</a></div><div class='hunk'>@@ -0,0 +1,288 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	native-hdmi-connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		label = "X21";</div><div class='add'>+		type = "a";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			native_hdmi_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_tx_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,bitclock-master = &lt;&amp;codec_dai&gt;;</div><div class='add'>+		simple-audio-card,format = "i2s";</div><div class='add'>+		simple-audio-card,frame-master = &lt;&amp;codec_dai&gt;;</div><div class='add'>+		simple-audio-card,mclk-fs = &lt;256&gt;;</div><div class='add'>+		simple-audio-card,name = "verdin-wm8904";</div><div class='add'>+		simple-audio-card,routing =</div><div class='add'>+			"Headphone Jack", "HPOUTL",</div><div class='add'>+			"Headphone Jack", "HPOUTR",</div><div class='add'>+			"IN2L", "Line In Jack",</div><div class='add'>+			"IN2R", "Line In Jack",</div><div class='add'>+			"Microphone Jack", "MICBIAS",</div><div class='add'>+			"IN1L", "Microphone Jack";</div><div class='add'>+		simple-audio-card,widgets =</div><div class='add'>+			"Microphone", "Microphone Jack",</div><div class='add'>+			"Headphone", "Headphone Jack",</div><div class='add'>+			"Line", "Line In Jack";</div><div class='add'>+</div><div class='add'>+		codec_dai: simple-audio-card,codec {</div><div class='add'>+			clocks = &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1&gt;;</div><div class='add'>+			sound-dai = &lt;&amp;wm8904_1a&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;sai1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb_hub: regulator-usb-hub {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		enable-active-high;</div><div class='add'>+		/* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */</div><div class='add'>+		gpio = &lt;&amp;gpio4 29 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-name = "HUB_PWR_EN";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_pcie: regulator-pcie {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		enable-active-high;</div><div class='add'>+		/* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */</div><div class='add'>+		gpio = &lt;&amp;gpio4 29 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-name = "PCIE_1_PWR_EN";</div><div class='add'>+		startup-delay-us = &lt;100000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin HDMI_1 Audio */</div><div class='add'>+&amp;aud2htx {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;backlight {</div><div class='add'>+	power-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin SPI_1 */</div><div class='add'>+&amp;ecspi1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* EEPROM on display adapter boards */</div><div class='add'>+&amp;eeprom_display_adapter {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* EEPROM on Verdin Development board */</div><div class='add'>+&amp;eeprom_carrier_board {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eqos {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin QSPI_1 */</div><div class='add'>+&amp;flexspi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ctrl_sleep_moci&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin HDMI_1 */</div><div class='add'>+&amp;hdmi_pvi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@1 {</div><div class='add'>+			hdmi_tx_out: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;native_hdmi_connector_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Current measurement into module VCC */</div><div class='add'>+&amp;hwmon {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hwmon_temp {</div><div class='add'>+	vs-supply = &lt;&amp;reg_1p8v&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin I2C_2_DSI */</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin I2C_1 */</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* Audio Codec */</div><div class='add'>+	wm8904_1a: audio-codec@1a {</div><div class='add'>+		compatible = "wlf,wm8904";</div><div class='add'>+		reg = &lt;0x1a&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_sai1&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		clocks = &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1&gt;;</div><div class='add'>+		clock-names = "mclk";</div><div class='add'>+		AVDD-supply = &lt;&amp;reg_1p8v&gt;;</div><div class='add'>+		CPVDD-supply = &lt;&amp;reg_1p8v&gt;;</div><div class='add'>+		DBVDD-supply = &lt;&amp;reg_1p8v&gt;;</div><div class='add'>+		DCVDD-supply = &lt;&amp;reg_1p8v&gt;;</div><div class='add'>+		MICVDD-supply = &lt;&amp;reg_1p8v&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin I2C_3_HDMI */</div><div class='add'>+&amp;i2c5 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin PCIE_1 */</div><div class='add'>+&amp;pcie {</div><div class='add'>+	vpcie-supply = &lt;&amp;reg_pcie&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin PWM_1 */</div><div class='add'>+&amp;pwm1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin PWM_2 */</div><div class='add'>+&amp;pwm2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin PWM_3_DSI */</div><div class='add'>+&amp;pwm3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_usdhc2_vmmc {</div><div class='add'>+	vin-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* We support turning off sleep moci on Dahlia */</div><div class='add'>+&amp;reg_force_sleep_moci {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin I2S_1 */</div><div class='add'>+&amp;sai1 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_SAI1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;24576000&gt;;</div><div class='add'>+	fsl,sai-mclk-direction-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin HDMI_1 Audio */</div><div class='add'>+&amp;sound_hdmi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin UART_1 */</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin UART_2 */</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin UART_3, used as the Linux Console */</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin USB_1 */</div><div class='add'>+&amp;usb3_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin USB_2 */</div><div class='add'>+&amp;usb3_1 {</div><div class='add'>+	fsl,permanently-attached;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_1 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	usb_hub_3_0: usb-hub@1 {</div><div class='add'>+		compatible = "usb424,5744";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		peer-hub = &lt;&amp;usb_hub_2_0&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;reg_usb_hub&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb_hub_2_0: usb-hub@2 {</div><div class='add'>+		compatible = "usb424,2744";</div><div class='add'>+		reg = &lt;2&gt;;</div><div class='add'>+		peer-hub = &lt;&amp;usb_hub_3_0&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;reg_usb_hub&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin SD_1 */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi<br/>new file mode 100644<br/>index 000000000000..a38e7c947a42<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi</a></div><div class='hunk'>@@ -0,0 +1,269 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	native-hdmi-connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		label = "X37";</div><div class='add'>+		type = "a";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			native_hdmi_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_tx_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_eth2phy: regulator-eth2phy {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;gpio_expander_21 4 GPIO_ACTIVE_HIGH&gt;; /* ETH_PWR_EN */</div><div class='add'>+		off-on-delay-us = &lt;500000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "+V3.3_ETH";</div><div class='add'>+		startup-delay-us = &lt;200000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,bitclock-master = &lt;&amp;codec_dai&gt;;</div><div class='add'>+		simple-audio-card,format = "i2s";</div><div class='add'>+		simple-audio-card,frame-master = &lt;&amp;codec_dai&gt;;</div><div class='add'>+		simple-audio-card,mclk-fs = &lt;256&gt;;</div><div class='add'>+		simple-audio-card,name = "verdin-nau8822";</div><div class='add'>+		simple-audio-card,routing =</div><div class='add'>+			"Headphones", "LHP",</div><div class='add'>+			"Headphones", "RHP",</div><div class='add'>+			"Speaker", "LSPK",</div><div class='add'>+			"Speaker", "RSPK",</div><div class='add'>+			"Line Out", "AUXOUT1",</div><div class='add'>+			"Line Out", "AUXOUT2",</div><div class='add'>+			"LAUX", "Line In",</div><div class='add'>+			"RAUX", "Line In",</div><div class='add'>+			"LMICP", "Mic In",</div><div class='add'>+			"RMICP", "Mic In";</div><div class='add'>+		simple-audio-card,widgets =</div><div class='add'>+			"Headphones", "Headphones",</div><div class='add'>+			"Line Out", "Line Out",</div><div class='add'>+			"Speaker", "Speaker",</div><div class='add'>+			"Microphone", "Mic In",</div><div class='add'>+			"Line", "Line In";</div><div class='add'>+</div><div class='add'>+		codec_dai: simple-audio-card,codec {</div><div class='add'>+			clocks = &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1&gt;;</div><div class='add'>+			sound-dai = &lt;&amp;nau8822_1a&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;sai1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin HDMI_1 Audio */</div><div class='add'>+&amp;aud2htx {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;backlight {</div><div class='add'>+	power-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin SPI_1 */</div><div class='add'>+&amp;ecspi1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* EEPROM on display adapter boards */</div><div class='add'>+&amp;eeprom_display_adapter {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* EEPROM on Verdin Development board */</div><div class='add'>+&amp;eeprom_carrier_board {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eqos {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec {</div><div class='add'>+	phy-supply = &lt;&amp;reg_eth2phy&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin QSPI_1 */</div><div class='add'>+&amp;flexspi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ctrl_sleep_moci&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio_expander_21 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	vcc-supply = &lt;&amp;reg_1p8v&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin HDMI_1 */</div><div class='add'>+&amp;hdmi_pvi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@1 {</div><div class='add'>+			hdmi_tx_out: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;native_hdmi_connector_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Current measurement into module VCC */</div><div class='add'>+&amp;hwmon {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hwmon_temp {</div><div class='add'>+	vs-supply = &lt;&amp;reg_1p8v&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin I2C_2_DSI */</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin I2C_1 */</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* Audio Codec */</div><div class='add'>+	nau8822_1a: audio-codec@1a {</div><div class='add'>+		compatible = "nuvoton,nau8822";</div><div class='add'>+		reg = &lt;0x1a&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_sai1&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin I2C_3_HDMI */</div><div class='add'>+&amp;i2c5 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin PCIE_1 */</div><div class='add'>+&amp;pcie {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin PWM_1 */</div><div class='add'>+&amp;pwm1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin PWM_2 */</div><div class='add'>+&amp;pwm2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin PWM_3_DSI */</div><div class='add'>+&amp;pwm3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_usdhc2_vmmc {</div><div class='add'>+	vin-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin I2S_1 */</div><div class='add'>+&amp;sai1 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_SAI1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MP_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;24576000&gt;;</div><div class='add'>+	fsl,sai-mclk-direction-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin HDMI_1 Audio */</div><div class='add'>+&amp;sound_hdmi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin UART_1, connector X50 through RS485 transceiver */</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	linux,rs485-enabled-at-boot-time;</div><div class='add'>+	rs485-rts-active-low;</div><div class='add'>+	rs485-rx-during-tx;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin UART_2 */</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin UART_3, used as the Linux Console */</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin USB_1 */</div><div class='add'>+&amp;usb3_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin USB_2 */</div><div class='add'>+&amp;usb3_1 {</div><div class='add'>+	fsl,permanently-attached;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Limit frequency on dev board due to long traces and bad signal integrity */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	max-frequency = &lt;100000000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-ivy.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-ivy.dtsi<br/>new file mode 100644<br/>index 000000000000..db1b4ee7728c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-verdin-ivy.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-verdin-ivy.dtsi</a></div><div class='hunk'>@@ -0,0 +1,512 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 Toradex</div><div class='add'>+ *</div><div class='add'>+ * Common dtsi for Verdin IMX8MP SoM on Ivy carrier board</div><div class='add'>+ *</div><div class='add'>+ * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-plus</div><div class='add'>+ * https://www.toradex.com/products/carrier-board/ivy-carrier-board</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/mux/mux.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/net/ti-dp83867.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	/* AIN1 Voltage w/o AIN1_MODE gpio control */</div><div class='add'>+	ain1_voltage_unmanaged: voltage-divider-ain1 {</div><div class='add'>+		compatible = "voltage-divider";</div><div class='add'>+		#io-channel-cells = &lt;1&gt;;</div><div class='add'>+		io-channels = &lt;&amp;ivy_adc1 0&gt;;</div><div class='add'>+		full-ohms = &lt;19&gt;;</div><div class='add'>+		output-ohms = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* AIN1 Current w/o AIN1_MODE gpio control */</div><div class='add'>+	ain1_current_unmanaged: current-sense-shunt-ain1 {</div><div class='add'>+		compatible = "current-sense-shunt";</div><div class='add'>+		#io-channel-cells = &lt;0&gt;;</div><div class='add'>+		io-channels = &lt;&amp;ivy_adc1 1&gt;;</div><div class='add'>+		shunt-resistor-micro-ohms = &lt;100000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* AIN1_MODE - SODIMM 216 */</div><div class='add'>+	ain1_mode_mux_ctrl: mux-controller-0 {</div><div class='add'>+		compatible = "gpio-mux";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio5&gt;;</div><div class='add'>+		#mux-control-cells = &lt;0&gt;;</div><div class='add'>+		mux-gpios = &lt;&amp;gpio1 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ain1-voltage {</div><div class='add'>+		compatible = "io-channel-mux";</div><div class='add'>+		channels = "ain1_voltage", "";</div><div class='add'>+		io-channels = &lt;&amp;ain1_voltage_unmanaged 0&gt;;</div><div class='add'>+		io-channel-names = "parent";</div><div class='add'>+		mux-controls = &lt;&amp;ain1_mode_mux_ctrl&gt;;</div><div class='add'>+		settle-time-us = &lt;1000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ain1-current {</div><div class='add'>+		compatible = "io-channel-mux";</div><div class='add'>+		channels = "", "ain1_current";</div><div class='add'>+		io-channels = &lt;&amp;ain1_current_unmanaged&gt;;</div><div class='add'>+		io-channel-names = "parent";</div><div class='add'>+		mux-controls = &lt;&amp;ain1_mode_mux_ctrl&gt;;</div><div class='add'>+		settle-time-us = &lt;1000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* AIN2 Voltage w/o AIN2_MODE gpio control */</div><div class='add'>+	ain2_voltage_unmanaged: voltage-divider-ain2 {</div><div class='add'>+		compatible = "voltage-divider";</div><div class='add'>+		#io-channel-cells = &lt;1&gt;;</div><div class='add'>+		io-channels = &lt;&amp;ivy_adc2 0&gt;;</div><div class='add'>+		full-ohms = &lt;19&gt;;</div><div class='add'>+		output-ohms = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* AIN2 Current w/o AIN2_MODE gpio control */</div><div class='add'>+	ain2_current_unmanaged: current-sense-shunt-ain2 {</div><div class='add'>+		compatible = "current-sense-shunt";</div><div class='add'>+		#io-channel-cells = &lt;0&gt;;</div><div class='add'>+		io-channels = &lt;&amp;ivy_adc2 1&gt;;</div><div class='add'>+		shunt-resistor-micro-ohms = &lt;100000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* AIN2_MODE - SODIMM 218 */</div><div class='add'>+	ain2_mode_mux_ctrl: mux-controller-1 {</div><div class='add'>+		compatible = "gpio-mux";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio6&gt;;</div><div class='add'>+		#mux-control-cells = &lt;0&gt;;</div><div class='add'>+		mux-gpios = &lt;&amp;gpio1 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ain2-voltage {</div><div class='add'>+		compatible = "io-channel-mux";</div><div class='add'>+		channels = "ain2_voltage", "";</div><div class='add'>+		io-channels = &lt;&amp;ain2_voltage_unmanaged 0&gt;;</div><div class='add'>+		io-channel-names = "parent";</div><div class='add'>+		mux-controls = &lt;&amp;ain2_mode_mux_ctrl&gt;;</div><div class='add'>+		settle-time-us = &lt;1000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ain2-current {</div><div class='add'>+		compatible = "io-channel-mux";</div><div class='add'>+		channels = "", "ain2_current";</div><div class='add'>+		io-channels = &lt;&amp;ain2_current_unmanaged&gt;;</div><div class='add'>+		io-channel-names = "parent";</div><div class='add'>+		mux-controls = &lt;&amp;ain2_mode_mux_ctrl&gt;;</div><div class='add'>+		settle-time-us = &lt;1000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_ivy_leds&gt;;</div><div class='add'>+</div><div class='add'>+		/* D7 Blue - SODIMM 30 - LEDs.GPIO1 */</div><div class='add'>+		led-0 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			function-enumerator = &lt;1&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio3 25 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* D7 Green - SODIMM 32 - LEDs.GPIO2 */</div><div class='add'>+		led-1 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			function-enumerator = &lt;1&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio3 22 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* D7 Red - SODIMM 34 - LEDs.GPIO3 */</div><div class='add'>+		led-2 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			function-enumerator = &lt;1&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio3 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* D8 Blue - SODIMM 36 - LEDs.GPIO4 */</div><div class='add'>+		led-3 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			function-enumerator = &lt;2&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio4 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* D8 Green - SODIMM 54 - LEDs.GPIO5 */</div><div class='add'>+		led-4 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			function-enumerator = &lt;2&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio3 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* D8 Red - SODIMM 44 - LEDs.GPIO6 */</div><div class='add'>+		led-5 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			function-enumerator = &lt;2&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio4 31 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* D9 Blue - SODIMM 46 - LEDs.GPIO7 */</div><div class='add'>+		led-6 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			function-enumerator = &lt;3&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio5 01 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* D9 Red - SODIMM 48 - LEDs.GPIO8 */</div><div class='add'>+		led-7 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			function-enumerator = &lt;3&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio4 30 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3v2_ain1: regulator-3v2-ain1 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;3200000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3200000&gt;;</div><div class='add'>+		regulator-name = "+3V2_AIN1";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3v2_ain2: regulator-3v2-ain2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;3200000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3200000&gt;;</div><div class='add'>+		regulator-name = "+3V2_AIN2";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Ivy Power Supply Input Voltage */</div><div class='add'>+	ivy-input-voltage {</div><div class='add'>+		compatible = "voltage-divider";</div><div class='add'>+		/* Verdin ADC_1 */</div><div class='add'>+		io-channels = &lt;&amp;verdin_som_adc 7&gt;;</div><div class='add'>+		full-ohms = &lt;204700&gt;; /* 200k + 4.7k */</div><div class='add'>+		output-ohms = &lt;4700&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ivy-5v-voltage {</div><div class='add'>+		compatible = "voltage-divider";</div><div class='add'>+		/* Verdin ADC_2 */</div><div class='add'>+		io-channels = &lt;&amp;verdin_som_adc 6&gt;;</div><div class='add'>+		full-ohms = &lt;39000&gt;; /* 27k + 12k */</div><div class='add'>+		output-ohms = &lt;12000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ivy-3v3-voltage {</div><div class='add'>+		compatible = "voltage-divider";</div><div class='add'>+		/* Verdin ADC_3 */</div><div class='add'>+		io-channels = &lt;&amp;verdin_som_adc 5&gt;;</div><div class='add'>+		full-ohms = &lt;54000&gt;; /* 27k + 27k */</div><div class='add'>+		output-ohms = &lt;27000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ivy-1v8-voltage {</div><div class='add'>+		compatible = "voltage-divider";</div><div class='add'>+		/* Verdin ADC_4 */</div><div class='add'>+		io-channels = &lt;&amp;verdin_som_adc 4&gt;;</div><div class='add'>+		full-ohms = &lt;39000&gt;; /* 12k + 27k */</div><div class='add'>+		output-ohms = &lt;27000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin SPI_1 */</div><div class='add'>+&amp;ecspi1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi1&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_gpio1&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_gpio4&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 9 GPIO_ACTIVE_LOW&gt;,</div><div class='add'>+		   &lt;&amp;gpio1 0 GPIO_ACTIVE_LOW&gt;,</div><div class='add'>+		   &lt;&amp;gpio1 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	tpm@1 {</div><div class='add'>+		compatible = "infineon,slb9670", "tcg,tpm_tis-spi";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		spi-max-frequency = &lt;18500000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fram@2 {</div><div class='add'>+		compatible = "fujitsu,mb85rs256", "atmel,at25";</div><div class='add'>+		reg = &lt;2&gt;;</div><div class='add'>+		address-width = &lt;16&gt;;</div><div class='add'>+		size = &lt;32768&gt;;</div><div class='add'>+		spi-max-frequency = &lt;33000000&gt;;</div><div class='add'>+		pagesize = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* EEPROM on Ivy */</div><div class='add'>+&amp;eeprom_carrier_board {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin ETH_1 */</div><div class='add'>+&amp;eqos {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin ETH_2 */</div><div class='add'>+&amp;fec {</div><div class='add'>+	phy-handle = &lt;&amp;ethphy2&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;verdin_eth2_mdio {</div><div class='add'>+	ethphy2: ethernet-phy@2 {</div><div class='add'>+		reg = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;18 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_2_00_NS&gt;;</div><div class='add'>+		ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_2_00_NS&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin CAN_1 */</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin CAN_2 */</div><div class='add'>+&amp;flexcan2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"", /* 0 */</div><div class='add'>+		"GPIO2", /* Verdin GPIO_2 - SODIMM 208 */</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"GPIO3", /* Verdin GPIO_3 - SODIMM 210 */</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"", /* 10 */</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"", /* 20 */</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio3 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"", /* 0 */</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"DIG_1", /* SODIMM 56 */</div><div class='add'>+		"DIG_2", /* SODIMM 58 */</div><div class='add'>+		"REL1",  /* SODIMM 60 */</div><div class='add'>+		"REL2",  /* SODIMM 62 */</div><div class='add'>+		"", /* 10 */</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"REL4", /* SODIMM 66 */</div><div class='add'>+		"",</div><div class='add'>+		"REL3", /* SODIMM 64 */</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"", /* 20 */</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Temperature sensor on Ivy */</div><div class='add'>+&amp;hwmon_temp {</div><div class='add'>+	compatible = "ti,tmp1075";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin I2C_4 CSI */</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ivy_adc1: adc@40 {</div><div class='add'>+		compatible = "ti,ads1119";</div><div class='add'>+		reg = &lt;0x40&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio7&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;3 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		avdd-supply = &lt;&amp;reg_3v2_ain1&gt;;</div><div class='add'>+		dvdd-supply = &lt;&amp;reg_3v2_ain1&gt;;</div><div class='add'>+		vref-supply = &lt;&amp;reg_3v2_ain1&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#io-channel-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		/* AIN1 0-33V Voltage Input */</div><div class='add'>+		channel@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			diff-channels = &lt;0 1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* AIN1 0-20mA Current Input */</div><div class='add'>+		channel@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			diff-channels = &lt;2 3&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ivy_adc2: adc@41 {</div><div class='add'>+		compatible = "ti,ads1119";</div><div class='add'>+		reg = &lt;0x41&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio8&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;1 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		avdd-supply = &lt;&amp;reg_3v2_ain2&gt;;</div><div class='add'>+		dvdd-supply = &lt;&amp;reg_3v2_ain2&gt;;</div><div class='add'>+		vref-supply = &lt;&amp;reg_3v2_ain2&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#io-channel-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		/* AIN2 0-33V Voltage Input */</div><div class='add'>+		channel@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			diff-channels = &lt;0 1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* AIN2 0-20mA Current Input */</div><div class='add'>+		channel@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			diff-channels = &lt;2 3&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin I2C_1 */</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin PCIE_1 */</div><div class='add'>+&amp;pcie {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin UART_1 */</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin UART_2 */</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	linux,rs485-enabled-at-boot-time;</div><div class='add'>+	rs485-rx-during-tx;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin UART_3 */</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin USB_1 */</div><div class='add'>+&amp;usb3_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin USB_2 */</div><div class='add'>+&amp;usb3_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin SD_1 */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio2&gt;, &lt;&amp;pinctrl_gpio3&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_ivy_dig_inputs&gt;, &lt;&amp;pinctrl_ivy_relays&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl_ivy_dig_inputs: ivydiginputsgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06	0x96&gt;, /* SODIMM 56 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07	0x96&gt;; /* SODIMM 58 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ivy_leds: ivyledsgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25	0x16&gt;, /* SODIMM 30 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22	0x16&gt;, /* SODIMM 32 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19	0x16&gt;, /* SODIMM 34 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02	0x16&gt;, /* SODIMM 36 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31	0x16&gt;, /* SODIMM 44 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01	0x16&gt;, /* SODIMM 46 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30	0x16&gt;, /* SODIMM 48 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01	0x16&gt;; /* SODIMM 54 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ivy_relays: ivyrelaysgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08	0x16&gt;, /* SODIMM 60 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09	0x16&gt;, /* SODIMM 62 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16	0x16&gt;, /* SODIMM 64 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14	0x16&gt;; /* SODIMM 66 */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-mallow.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-mallow.dtsi<br/>new file mode 100644<br/>index 000000000000..11cf3bdc95c4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-verdin-mallow.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-verdin-mallow.dtsi</a></div><div class='hunk'>@@ -0,0 +1,251 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Toradex</div><div class='add'>+ *</div><div class='add'>+ * Common dtsi for Verdin IMX8MP SoM on Mallow carrier board</div><div class='add'>+ *</div><div class='add'>+ * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-plus</div><div class='add'>+ * https://www.toradex.com/products/carrier-board/mallow-carrier-board</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	native-hdmi-connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		label = "X14";</div><div class='add'>+		type = "a";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			native_hdmi_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_tx_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_leds&gt;;</div><div class='add'>+</div><div class='add'>+		/* SODIMM 52 - USER_LED_1_RED */</div><div class='add'>+		led-0 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			function = LED_FUNCTION_DEBUG;</div><div class='add'>+			function-enumerator = &lt;1&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio3 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* SODIMM 54 - USER_LED_1_GREEN */</div><div class='add'>+		led-1 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_DEBUG;</div><div class='add'>+			function-enumerator = &lt;1&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio3 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* SODIMM 56 - USER_LED_2_RED */</div><div class='add'>+		led-2 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			function = LED_FUNCTION_DEBUG;</div><div class='add'>+			function-enumerator = &lt;2&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio3 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* SODIMM 58 - USER_LED_2_GREEN */</div><div class='add'>+		led-3 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_DEBUG;</div><div class='add'>+			function-enumerator = &lt;2&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio3 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin HDMI_1 Audio */</div><div class='add'>+&amp;aud2htx {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;backlight {</div><div class='add'>+	power-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin SPI_1 */</div><div class='add'>+&amp;ecspi1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi1&gt;, &lt;&amp;pinctrl_tpm_cs&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 9 GPIO_ACTIVE_LOW&gt;, &lt;&amp;gpio3 16 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	tpm@1 {</div><div class='add'>+		compatible = "infineon,slb9670", "tcg,tpm_tis-spi";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_tpm_irq&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+		interrupts = &lt;14 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		spi-max-frequency = &lt;18500000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* EEPROM on Mallow */</div><div class='add'>+&amp;eeprom_carrier_board {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin ETH_1 */</div><div class='add'>+&amp;eqos {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin CAN_1 */</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin CAN_2 */</div><div class='add'>+&amp;flexcan2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin HDMI_1 */</div><div class='add'>+&amp;hdmi_pvi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@1 {</div><div class='add'>+			hdmi_tx_out: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;native_hdmi_connector_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Temperature sensor on Mallow */</div><div class='add'>+&amp;hwmon_temp {</div><div class='add'>+	compatible = "ti,tmp1075";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin I2C_2_DSI */</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin I2C_4_CSI */</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin I2C_1 */</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin I2C_3_HDMI */</div><div class='add'>+&amp;i2c5 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin PCIE_1 */</div><div class='add'>+&amp;pcie {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin PWM_1 */</div><div class='add'>+&amp;pwm1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin PWM_2 */</div><div class='add'>+&amp;pwm2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin PWM_3_DSI */</div><div class='add'>+&amp;pwm3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_usdhc2_vmmc {</div><div class='add'>+	vin-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin HDMI_1 Audio */</div><div class='add'>+&amp;sound_hdmi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin UART_1 */</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin UART_2 */</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin UART_3 */</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin USB_1 */</div><div class='add'>+&amp;usb3_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin USB_2 */</div><div class='add'>+&amp;usb3_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin SD_1 */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_leds: ledsgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00	0x106&gt;, /* SODIMM 52 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01	0x106&gt;, /* SODIMM 54 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06	0x106&gt;, /* SODIMM 56 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07	0x106&gt;; /* SODIMM 58 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_tpm_cs: tpmcsgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16	0x82&gt;; /* SODIMM 64 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_tpm_irq: tpmirqgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14	0x16&gt;; /* SODIMM 66 */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-dahlia.dts b/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-dahlia.dts<br/>new file mode 100644<br/>index 000000000000..68147b0c1b35<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-dahlia.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-dahlia.dts</a></div><div class='hunk'>@@ -0,0 +1,18 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mp-verdin.dtsi"</div><div class='add'>+#include "imx8mp-verdin-nonwifi.dtsi"</div><div class='add'>+#include "imx8mp-verdin-dahlia.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Toradex Verdin iMX8M Plus on Dahlia Board";</div><div class='add'>+	compatible = "toradex,verdin-imx8mp-nonwifi-dahlia",</div><div class='add'>+		     "toradex,verdin-imx8mp-nonwifi",</div><div class='add'>+		     "toradex,verdin-imx8mp",</div><div class='add'>+		     "fsl,imx8mp";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-dev.dts b/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-dev.dts<br/>new file mode 100644<br/>index 000000000000..879ff687cf2b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-dev.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-dev.dts</a></div><div class='hunk'>@@ -0,0 +1,18 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mp-verdin.dtsi"</div><div class='add'>+#include "imx8mp-verdin-nonwifi.dtsi"</div><div class='add'>+#include "imx8mp-verdin-dev.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Toradex Verdin iMX8M Plus on Verdin Development Board";</div><div class='add'>+	compatible = "toradex,verdin-imx8mp-nonwifi-dev",</div><div class='add'>+		     "toradex,verdin-imx8mp-nonwifi",</div><div class='add'>+		     "toradex,verdin-imx8mp",</div><div class='add'>+		     "fsl,imx8mp";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-ivy.dts b/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-ivy.dts<br/>new file mode 100644<br/>index 000000000000..cb49690050ff<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-ivy.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-ivy.dts</a></div><div class='hunk'>@@ -0,0 +1,18 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mp-verdin.dtsi"</div><div class='add'>+#include "imx8mp-verdin-nonwifi.dtsi"</div><div class='add'>+#include "imx8mp-verdin-ivy.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Toradex Verdin iMX8M Plus on Ivy";</div><div class='add'>+	compatible = "toradex,verdin-imx8mp-nonwifi-ivy",</div><div class='add'>+		     "toradex,verdin-imx8mp-nonwifi",</div><div class='add'>+		     "toradex,verdin-imx8mp",</div><div class='add'>+		     "fsl,imx8mp";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-mallow.dts b/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-mallow.dts<br/>new file mode 100644<br/>index 000000000000..6a536a4964bb<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-mallow.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-mallow.dts</a></div><div class='hunk'>@@ -0,0 +1,18 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mp-verdin.dtsi"</div><div class='add'>+#include "imx8mp-verdin-nonwifi.dtsi"</div><div class='add'>+#include "imx8mp-verdin-mallow.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Toradex Verdin iMX8M Plus on Mallow Board";</div><div class='add'>+	compatible = "toradex,verdin-imx8mp-nonwifi-mallow",</div><div class='add'>+		     "toradex,verdin-imx8mp-nonwifi",</div><div class='add'>+		     "toradex,verdin-imx8mp",</div><div class='add'>+		     "fsl,imx8mp";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-yavia.dts b/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-yavia.dts<br/>new file mode 100644<br/>index 000000000000..b28477df1ec6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-yavia.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-yavia.dts</a></div><div class='hunk'>@@ -0,0 +1,18 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mp-verdin.dtsi"</div><div class='add'>+#include "imx8mp-verdin-nonwifi.dtsi"</div><div class='add'>+#include "imx8mp-verdin-yavia.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Toradex Verdin iMX8M Plus on Yavia Board";</div><div class='add'>+	compatible = "toradex,verdin-imx8mp-nonwifi-yavia",</div><div class='add'>+		     "toradex,verdin-imx8mp-nonwifi",</div><div class='add'>+		     "toradex,verdin-imx8mp",</div><div class='add'>+		     "fsl,imx8mp";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi.dtsi<br/>new file mode 100644<br/>index 000000000000..2ee91f31e7f0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi.dtsi</a></div><div class='hunk'>@@ -0,0 +1,53 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;gpio5 {</div><div class='add'>+	gpio-line-names = "SODIMM_42",</div><div class='add'>+			  "SODIMM_46",</div><div class='add'>+			  "SODIMM_187",</div><div class='add'>+			  "SODIMM_20",</div><div class='add'>+			  "SODIMM_22",</div><div class='add'>+			  "SODIMM_15",</div><div class='add'>+			  "SODIMM_196",</div><div class='add'>+			  "SODIMM_200",</div><div class='add'>+			  "SODIMM_198",</div><div class='add'>+			  "SODIMM_202",</div><div class='add'>+			  "SODIMM_164",</div><div class='add'>+			  "SODIMM_152",</div><div class='add'>+			  "SODIMM_116",</div><div class='add'>+			  "SODIMM_128",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "SODIMM_55",</div><div class='add'>+			  "SODIMM_53",</div><div class='add'>+			  "SODIMM_95",</div><div class='add'>+			  "SODIMM_93",</div><div class='add'>+			  "SODIMM_14",</div><div class='add'>+			  "SODIMM_12",</div><div class='add'>+			  "SODIMM_129",</div><div class='add'>+			  "SODIMM_131",</div><div class='add'>+			  "SODIMM_137",</div><div class='add'>+			  "SODIMM_139",</div><div class='add'>+			  "SODIMM_147",</div><div class='add'>+			  "SODIMM_149",</div><div class='add'>+			  "SODIMM_151",</div><div class='add'>+			  "SODIMM_153";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio1&gt;, &lt;&amp;pinctrl_gpio2&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_gpio3&gt;, &lt;&amp;pinctrl_gpio4&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_gpio7&gt;, &lt;&amp;pinctrl_gpio8&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_gpio_hog1&gt;, &lt;&amp;pinctrl_gpio_hog2&gt;, &lt;&amp;pinctrl_gpio_hog3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Verdin UART_4</div><div class='add'>+ * Often used by the M7 and then should not be enabled here.</div><div class='add'>+ */</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-dahlia.dts b/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-dahlia.dts<br/>new file mode 100644<br/>index 000000000000..804567f6ccee<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-dahlia.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-dahlia.dts</a></div><div class='hunk'>@@ -0,0 +1,18 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mp-verdin.dtsi"</div><div class='add'>+#include "imx8mp-verdin-wifi.dtsi"</div><div class='add'>+#include "imx8mp-verdin-dahlia.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Toradex Verdin iMX8M Plus WB on Dahlia Board";</div><div class='add'>+	compatible = "toradex,verdin-imx8mp-wifi-dahlia",</div><div class='add'>+		     "toradex,verdin-imx8mp-wifi",</div><div class='add'>+		     "toradex,verdin-imx8mp",</div><div class='add'>+		     "fsl,imx8mp";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-dev.dts b/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-dev.dts<br/>new file mode 100644<br/>index 000000000000..c1713c28cdce<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-dev.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-dev.dts</a></div><div class='hunk'>@@ -0,0 +1,18 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mp-verdin.dtsi"</div><div class='add'>+#include "imx8mp-verdin-wifi.dtsi"</div><div class='add'>+#include "imx8mp-verdin-dev.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Toradex Verdin iMX8M Plus WB on Verdin Development Board";</div><div class='add'>+	compatible = "toradex,verdin-imx8mp-wifi-dev",</div><div class='add'>+		     "toradex,verdin-imx8mp-wifi",</div><div class='add'>+		     "toradex,verdin-imx8mp",</div><div class='add'>+		     "fsl,imx8mp";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-ivy.dts b/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-ivy.dts<br/>new file mode 100644<br/>index 000000000000..22b8fe70b36d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-ivy.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-ivy.dts</a></div><div class='hunk'>@@ -0,0 +1,18 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mp-verdin.dtsi"</div><div class='add'>+#include "imx8mp-verdin-wifi.dtsi"</div><div class='add'>+#include "imx8mp-verdin-ivy.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Toradex Verdin iMX8M Plus WB on Ivy";</div><div class='add'>+	compatible = "toradex,verdin-imx8mp-wifi-ivy",</div><div class='add'>+		     "toradex,verdin-imx8mp-wifi",</div><div class='add'>+		     "toradex,verdin-imx8mp",</div><div class='add'>+		     "fsl,imx8mp";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-mallow.dts b/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-mallow.dts<br/>new file mode 100644<br/>index 000000000000..08b7aef3fdde<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-mallow.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-mallow.dts</a></div><div class='hunk'>@@ -0,0 +1,18 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mp-verdin.dtsi"</div><div class='add'>+#include "imx8mp-verdin-wifi.dtsi"</div><div class='add'>+#include "imx8mp-verdin-mallow.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Toradex Verdin iMX8M Plus WB on Mallow Board";</div><div class='add'>+	compatible = "toradex,verdin-imx8mp-wifi-mallow",</div><div class='add'>+		     "toradex,verdin-imx8mp-wifi",</div><div class='add'>+		     "toradex,verdin-imx8mp",</div><div class='add'>+		     "fsl,imx8mp";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-yavia.dts b/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-yavia.dts<br/>new file mode 100644<br/>index 000000000000..100bef12089c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-yavia.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-yavia.dts</a></div><div class='hunk'>@@ -0,0 +1,18 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mp-verdin.dtsi"</div><div class='add'>+#include "imx8mp-verdin-wifi.dtsi"</div><div class='add'>+#include "imx8mp-verdin-yavia.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Toradex Verdin iMX8M Plus WB on Yavia Board";</div><div class='add'>+	compatible = "toradex,verdin-imx8mp-wifi-yavia",</div><div class='add'>+		     "toradex,verdin-imx8mp-wifi",</div><div class='add'>+		     "toradex,verdin-imx8mp",</div><div class='add'>+		     "fsl,imx8mp";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi.dtsi<br/>new file mode 100644<br/>index 000000000000..cae06cb67cd3<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi.dtsi</a></div><div class='hunk'>@@ -0,0 +1,85 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	reg_wifi_en: regulator-wifi-en {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;gpio2 11 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_wifi_pwr_en&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "PDn_AW-CM276NF";</div><div class='add'>+		startup-delay-us = &lt;2000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio5 {</div><div class='add'>+	gpio-line-names = "SODIMM_42",</div><div class='add'>+			  "SODIMM_46",</div><div class='add'>+			  "SODIMM_187",</div><div class='add'>+			  "SODIMM_20",</div><div class='add'>+			  "SODIMM_22",</div><div class='add'>+			  "SODIMM_15",</div><div class='add'>+			  "SODIMM_196",</div><div class='add'>+			  "SODIMM_200",</div><div class='add'>+			  "SODIMM_198",</div><div class='add'>+			  "SODIMM_202",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "SODIMM_55",</div><div class='add'>+			  "SODIMM_53",</div><div class='add'>+			  "SODIMM_95",</div><div class='add'>+			  "SODIMM_93",</div><div class='add'>+			  "SODIMM_14",</div><div class='add'>+			  "SODIMM_12",</div><div class='add'>+			  "SODIMM_129",</div><div class='add'>+			  "SODIMM_131",</div><div class='add'>+			  "SODIMM_137",</div><div class='add'>+			  "SODIMM_139",</div><div class='add'>+			  "SODIMM_147",</div><div class='add'>+			  "SODIMM_149",</div><div class='add'>+			  "SODIMM_151",</div><div class='add'>+			  "SODIMM_153";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio1&gt;, &lt;&amp;pinctrl_gpio2&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_gpio3&gt;, &lt;&amp;pinctrl_gpio4&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_gpio7&gt;, &lt;&amp;pinctrl_gpio8&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_gpio_hog2&gt;, &lt;&amp;pinctrl_gpio_hog3&gt;, &lt;&amp;pinctrl_gpio_hog4&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* On-module Bluetooth */</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_bt_uart&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "mrvl,88w8997";</div><div class='add'>+		max-speed = &lt;921600&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* On-module Wi-Fi */</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	keep-power-in-suspend;</div><div class='add'>+	non-removable;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;, &lt;&amp;pinctrl_wifi_ctrl&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1_100mhz&gt;, &lt;&amp;pinctrl_wifi_ctrl&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1_200mhz&gt;, &lt;&amp;pinctrl_wifi_ctrl&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_wifi_en&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi<br/>new file mode 100644<br/>index 000000000000..cc389cda2af2<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi</a></div><div class='hunk'>@@ -0,0 +1,269 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	native-hdmi-connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		label = "J15";</div><div class='add'>+		type = "a";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			native_hdmi_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_tx_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Carrier Board Supply +V1.8 */</div><div class='add'>+	reg_1p8v: regulator-1p8v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-name = "+V1.8_SW";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Carrier Board Supply +V3.3 */</div><div class='add'>+	reg_3p3v: regulator-3p3v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "+V3.3_SW";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_leds_yavia&gt;;</div><div class='add'>+</div><div class='add'>+		/* SODIMM 52 - LD1_RED */</div><div class='add'>+		led-0 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			function = LED_FUNCTION_DEBUG;</div><div class='add'>+			function-enumerator = &lt;1&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio3 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+		/* SODIMM 54 - LD1_GREEN */</div><div class='add'>+		led-1 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_DEBUG;</div><div class='add'>+			function-enumerator = &lt;1&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio3 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+		/* SODIMM 56 - LD1_BLUE */</div><div class='add'>+		led-2 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			function = LED_FUNCTION_DEBUG;</div><div class='add'>+			function-enumerator = &lt;1&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio3 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+		/* SODIMM 58 - LD2_RED */</div><div class='add'>+		led-3 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			function = LED_FUNCTION_DEBUG;</div><div class='add'>+			function-enumerator = &lt;2&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio3 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+		/* SODIMM 60 - LD2_GREEN */</div><div class='add'>+		led-4 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_DEBUG;</div><div class='add'>+			function-enumerator = &lt;2&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio3 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+		/* SODIMM 62 - LD2_BLUE */</div><div class='add'>+		led-5 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			function = LED_FUNCTION_DEBUG;</div><div class='add'>+			function-enumerator = &lt;2&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio3 9 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin HDMI_1 Audio */</div><div class='add'>+&amp;aud2htx {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;backlight {</div><div class='add'>+	power-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin SPI_1 */</div><div class='add'>+&amp;ecspi1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* EEPROM on display adapter boards */</div><div class='add'>+&amp;eeprom_display_adapter {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* EEPROM on Verdin Yavia board */</div><div class='add'>+&amp;eeprom_carrier_board {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eqos {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ctrl_sleep_moci&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin HDMI_1 */</div><div class='add'>+&amp;hdmi_pvi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@1 {</div><div class='add'>+			hdmi_tx_out: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;native_hdmi_connector_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_tx_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hwmon_temp {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin I2C_2_DSI */</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin I2C_3_HDMI */</div><div class='add'>+&amp;i2c5 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin PCIE_1 */</div><div class='add'>+&amp;pcie {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin PWM_1 */</div><div class='add'>+&amp;pwm1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin PWM_2 */</div><div class='add'>+&amp;pwm2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin PWM_3_DSI */</div><div class='add'>+&amp;pwm3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_usdhc2_vmmc {</div><div class='add'>+	vin-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin HDMI_1 Audio */</div><div class='add'>+&amp;sound_hdmi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin UART_1 */</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin UART_2 */</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin UART_3, used as the Linux Console */</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin USB_1 */</div><div class='add'>+&amp;usb3_phy0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin USB_2 */</div><div class='add'>+&amp;usb3_phy1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin SD_1 */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_leds_yavia: ledsyaviagrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00	0x106	/* SODIMM 52 */</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01	0x106	/* SODIMM 54 */</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06	0x106	/* SODIMM 56 */</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07	0x106	/* SODIMM 58 */</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08	0x106	/* SODIMM 60 */</div><div class='add'>+			MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09	0x106	/* SODIMM 62 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpios_ext_yavia: gpiosextyaviagrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MP_IOMUXC_NAND_CE1_B__GPIO3_IO02	0x106	/* SODIMM 64 */</div><div class='add'>+			MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14	0x106	/* SODIMM 66 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi<br/>new file mode 100644<br/>index 000000000000..d43ba0087126<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi</a></div><div class='hunk'>@@ -0,0 +1,1493 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/phy/phy-imx8-pcie.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pwm/pwm.h&gt;</div><div class='add'>+#include "imx8mp.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart3;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		/* Ethernet aliases to ensure correct MAC addresses */</div><div class='add'>+		ethernet0 = &amp;eqos;</div><div class='add'>+		ethernet1 = &amp;fec;</div><div class='add'>+		rtc0 = &amp;rtc_i2c;</div><div class='add'>+		rtc1 = &amp;snvs_rtc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	backlight: backlight {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		brightness-levels = &lt;0 45 63 88 119 158 203 255&gt;;</div><div class='add'>+		default-brightness-level = &lt;4&gt;;</div><div class='add'>+		/* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */</div><div class='add'>+		enable-gpios = &lt;&amp;gpio5 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_i2s_2_d_out_dsi_1_bkl_en&gt;;</div><div class='add'>+		power-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='add'>+		/* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */</div><div class='add'>+		pwms = &lt;&amp;pwm3 0 6666667 PWM_POLARITY_INVERTED&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	backlight_mezzanine: backlight-mezzanine {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		brightness-levels = &lt;0 45 63 88 119 158 203 255&gt;;</div><div class='add'>+		default-brightness-level = &lt;4&gt;;</div><div class='add'>+		/* Verdin GPIO 4 (SODIMM 212) */</div><div class='add'>+		enable-gpios = &lt;&amp;gpio1 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		/* Verdin PWM_2 (SODIMM 16) */</div><div class='add'>+		pwms = &lt;&amp;pwm2 0 6666667 PWM_POLARITY_INVERTED&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	connector {</div><div class='add'>+		compatible = "gpio-usb-b-connector", "usb-b-connector";</div><div class='add'>+		id-gpios = &lt;&amp;gpio2 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		label = "Type-C";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usb_1_id&gt;;</div><div class='add'>+		self-powered;</div><div class='add'>+		type = "micro";</div><div class='add'>+		vbus-supply = &lt;&amp;reg_usb1_vbus&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			usb_dr_connector: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;usb3_dwc&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_keys&gt;;</div><div class='add'>+</div><div class='add'>+		key-wakeup {</div><div class='add'>+			debounce-interval = &lt;10&gt;;</div><div class='add'>+			/* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */</div><div class='add'>+			gpios = &lt;&amp;gpio4 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			label = "Wake-Up";</div><div class='add'>+			linux,code = &lt;KEY_WAKEUP&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound_hdmi: sound-hdmi {</div><div class='add'>+		compatible = "fsl,imx-audio-hdmi";</div><div class='add'>+		model = "audio-hdmi";</div><div class='add'>+		audio-cpu = &lt;&amp;aud2htx&gt;;</div><div class='add'>+		hdmi-out;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Carrier Board Supplies */</div><div class='add'>+	reg_1p8v: regulator-1p8v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-name = "+V1.8_SW";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3p3v: regulator-3p3v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "+V3.3_SW";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_5p0v: regulator-5p0v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-name = "+V5_SW";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Non PMIC On-module Supplies */</div><div class='add'>+	reg_module_eth1phy: regulator-module-eth1phy {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;gpio2 20 GPIO_ACTIVE_HIGH&gt;; /* PMIC_EN_ETH */</div><div class='add'>+		off-on-delay-us = &lt;500000&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_eth&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "On-module +V3.3_ETH";</div><div class='add'>+		startup-delay-us = &lt;200000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;reg_vdd_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * By default we enable CTRL_SLEEP_MOCI#, this is required to have</div><div class='add'>+	 * peripherals on the carrier board powered.</div><div class='add'>+	 * If more granularity or power saving is required this can be disabled</div><div class='add'>+	 * in the carrier board device tree files.</div><div class='add'>+	 */</div><div class='add'>+	reg_force_sleep_moci: regulator-force-sleep-moci {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		enable-active-high;</div><div class='add'>+		/* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */</div><div class='add'>+		gpio = &lt;&amp;gpio4 29 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-name = "CTRL_SLEEP_MOCI#";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb1_vbus: regulator-usb1-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		enable-active-high;</div><div class='add'>+		/* Verdin USB_1_EN (SODIMM 155) */</div><div class='add'>+		gpio = &lt;&amp;gpio1 12 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usb1_vbus&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-name = "USB_1_EN";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb2_vbus: regulator-usb2-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		enable-active-high;</div><div class='add'>+		/* Verdin USB_2_EN (SODIMM 185) */</div><div class='add'>+		gpio = &lt;&amp;gpio1 14 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usb2_vbus&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-name = "USB_2_EN";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		enable-active-high;</div><div class='add'>+		/* Verdin SD_1_PWR_EN (SODIMM 76) */</div><div class='add'>+		gpio = &lt;&amp;gpio4 22 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		off-on-delay-us = &lt;100000&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usdhc2_pwr_en&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "+V3.3_SD";</div><div class='add'>+		startup-delay-us = &lt;20000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		/* Use the kernel configuration settings instead */</div><div class='add'>+		/delete-node/ linux,cma;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_vdd_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_vdd_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_vdd_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_vdd_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu_alert0 {</div><div class='add'>+	temperature = &lt;95000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu_crit0 {</div><div class='add'>+	temperature = &lt;105000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin SPI_1 */</div><div class='add'>+&amp;ecspi1 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin ETH_1 (On-module PHY) */</div><div class='add'>+&amp;eqos {</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_eqos&gt;;</div><div class='add'>+	snps,force_thresh_dma_mode;</div><div class='add'>+	snps,mtl-rx-config = &lt;&amp;mtl_rx_setup&gt;;</div><div class='add'>+	snps,mtl-tx-config = &lt;&amp;mtl_tx_setup&gt;;</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@7 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			eee-broken-100tx;</div><div class='add'>+			eee-broken-1000t;</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+			interrupts = &lt;10 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			micrel,led-mode = &lt;0&gt;;</div><div class='add'>+			reg = &lt;7&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mtl_rx_setup: rx-queues-config {</div><div class='add'>+		snps,rx-queues-to-use = &lt;5&gt;;</div><div class='add'>+</div><div class='add'>+		queue0 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x1&gt;;</div><div class='add'>+			snps,map-to-dma-channel = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue1 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x2&gt;;</div><div class='add'>+			snps,map-to-dma-channel = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue2 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x4&gt;;</div><div class='add'>+			snps,map-to-dma-channel = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue3 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x8&gt;;</div><div class='add'>+			snps,map-to-dma-channel = &lt;3&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue4 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0xf0&gt;;</div><div class='add'>+			snps,map-to-dma-channel = &lt;4&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mtl_tx_setup: tx-queues-config {</div><div class='add'>+		snps,tx-queues-to-use = &lt;5&gt;;</div><div class='add'>+</div><div class='add'>+		queue0 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue1 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue2 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x4&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue3 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x8&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue4 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0xf0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin ETH_2_RGMII */</div><div class='add'>+&amp;fec {</div><div class='add'>+	fsl,magic-packet;</div><div class='add'>+	phy-handle = &lt;&amp;ethphy1&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_fec_sleep&gt;;</div><div class='add'>+</div><div class='add'>+	verdin_eth2_mdio: mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy1: ethernet-phy@7 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+			interrupts = &lt;18 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			micrel,led-mode = &lt;0&gt;;</div><div class='add'>+			reg = &lt;7&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin CAN_1 */</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan1&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin CAN_2 */</div><div class='add'>+&amp;flexcan2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan2&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin QSPI_1 */</div><div class='add'>+&amp;flexspi {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexspi0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	gpio-line-names = "SODIMM_206",</div><div class='add'>+			  "SODIMM_208",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "SODIMM_210",</div><div class='add'>+			  "SODIMM_212",</div><div class='add'>+			  "SODIMM_216",</div><div class='add'>+			  "SODIMM_218",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "SODIMM_16",</div><div class='add'>+			  "SODIMM_155",</div><div class='add'>+			  "SODIMM_157",</div><div class='add'>+			  "SODIMM_185",</div><div class='add'>+			  "SODIMM_91";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio2 {</div><div class='add'>+	gpio-line-names = "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "SODIMM_143",</div><div class='add'>+			  "SODIMM_141",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "SODIMM_161",</div><div class='add'>+			  "",</div><div class='add'>+			  "SODIMM_84",</div><div class='add'>+			  "SODIMM_78",</div><div class='add'>+			  "SODIMM_74",</div><div class='add'>+			  "SODIMM_80",</div><div class='add'>+			  "SODIMM_82",</div><div class='add'>+			  "SODIMM_70",</div><div class='add'>+			  "SODIMM_72";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio3 {</div><div class='add'>+	gpio-line-names = "SODIMM_52",</div><div class='add'>+			  "SODIMM_54",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "SODIMM_56",</div><div class='add'>+			  "SODIMM_58",</div><div class='add'>+			  "SODIMM_60",</div><div class='add'>+			  "SODIMM_62",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "SODIMM_66",</div><div class='add'>+			  "",</div><div class='add'>+			  "SODIMM_64",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "SODIMM_34",</div><div class='add'>+			  "SODIMM_19",</div><div class='add'>+			  "",</div><div class='add'>+			  "SODIMM_32",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "SODIMM_30",</div><div class='add'>+			  "SODIMM_59",</div><div class='add'>+			  "SODIMM_57",</div><div class='add'>+			  "SODIMM_63",</div><div class='add'>+			  "SODIMM_61";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	gpio-line-names = "SODIMM_252",</div><div class='add'>+			  "SODIMM_222",</div><div class='add'>+			  "SODIMM_36",</div><div class='add'>+			  "SODIMM_220",</div><div class='add'>+			  "SODIMM_193",</div><div class='add'>+			  "SODIMM_191",</div><div class='add'>+			  "SODIMM_201",</div><div class='add'>+			  "SODIMM_203",</div><div class='add'>+			  "SODIMM_205",</div><div class='add'>+			  "SODIMM_207",</div><div class='add'>+			  "SODIMM_199",</div><div class='add'>+			  "SODIMM_197",</div><div class='add'>+			  "SODIMM_221",</div><div class='add'>+			  "SODIMM_219",</div><div class='add'>+			  "SODIMM_217",</div><div class='add'>+			  "SODIMM_215",</div><div class='add'>+			  "SODIMM_211",</div><div class='add'>+			  "SODIMM_213",</div><div class='add'>+			  "SODIMM_189",</div><div class='add'>+			  "SODIMM_244",</div><div class='add'>+			  "SODIMM_38",</div><div class='add'>+			  "",</div><div class='add'>+			  "SODIMM_76",</div><div class='add'>+			  "SODIMM_135",</div><div class='add'>+			  "SODIMM_133",</div><div class='add'>+			  "SODIMM_17",</div><div class='add'>+			  "SODIMM_24",</div><div class='add'>+			  "SODIMM_26",</div><div class='add'>+			  "SODIMM_21",</div><div class='add'>+			  "SODIMM_256",</div><div class='add'>+			  "SODIMM_48",</div><div class='add'>+			  "SODIMM_44";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin HDMI_1 */</div><div class='add'>+&amp;hdmi_tx {</div><div class='add'>+	ddc-i2c-bus = &lt;&amp;i2c5&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hdmi&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* On-module I2C */</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c1_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	single-master;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pca9450: pmic@25 {</div><div class='add'>+		compatible = "nxp,pca9450c";</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		/* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */</div><div class='add'>+		interrupts = &lt;3 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * The bootloader is expected to switch on LDO4 for the on-module +V3.3_ADC and the</div><div class='add'>+		 * I2C level shifter for the TLA2024 ADC behind this PMIC.</div><div class='add'>+		 */</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			BUCK1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;720000&gt;;</div><div class='add'>+				regulator-name = "On-module +VDD_SOC (BUCK1)";</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vdd_arm: BUCK2 {</div><div class='add'>+				nxp,dvs-run-voltage = &lt;950000&gt;;</div><div class='add'>+				nxp,dvs-standby-voltage = &lt;850000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1025000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;720000&gt;;</div><div class='add'>+				regulator-name = "On-module +VDD_ARM (BUCK2)";</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vdd_3v3: BUCK4 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "On-module +V3.3 (BUCK4)";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vdd_1v8: BUCK5 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "PWR_1V8_MOCI (BUCK5)";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			BUCK6 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1155000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1045000&gt;;</div><div class='add'>+				regulator-name = "On-module +VDD_DDR (BUCK6)";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			LDO1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1950000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1650000&gt;;</div><div class='add'>+				regulator-name = "On-module +V1.8_SNVS (LDO1)";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			LDO2 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1150000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-name = "On-module +V0.8_SNVS (LDO2)";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			LDO3 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "On-module +V1.8A (LDO3)";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			LDO4 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-name = "On-module +V3.3_ADC (LDO4)";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vdd_sdio: LDO5 {</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "On-module +V3.3_1.8_SD (LDO5)";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rtc_i2c: rtc@32 {</div><div class='add'>+		compatible = "epson,rx8130";</div><div class='add'>+		reg = &lt;0x32&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* On-module temperature sensor */</div><div class='add'>+	hwmon_temp_module: sensor@48 {</div><div class='add'>+		compatible = "ti,tmp1075";</div><div class='add'>+		reg = &lt;0x48&gt;;</div><div class='add'>+		vs-supply = &lt;&amp;reg_vdd_1v8&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	verdin_som_adc: adc@49 {</div><div class='add'>+		compatible = "ti,ads1015";</div><div class='add'>+		reg = &lt;0x49&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		#io-channel-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		/* Verdin I2C_1 (ADC_4 - ADC_3) */</div><div class='add'>+		channel@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			ti,datarate = &lt;4&gt;;</div><div class='add'>+			ti,gain = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* Verdin I2C_1 (ADC_4 - ADC_1) */</div><div class='add'>+		channel@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			ti,datarate = &lt;4&gt;;</div><div class='add'>+			ti,gain = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* Verdin I2C_1 (ADC_3 - ADC_1) */</div><div class='add'>+		channel@2 {</div><div class='add'>+			reg = &lt;2&gt;;</div><div class='add'>+			ti,datarate = &lt;4&gt;;</div><div class='add'>+			ti,gain = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* Verdin I2C_1 (ADC_2 - ADC_1) */</div><div class='add'>+		channel@3 {</div><div class='add'>+			reg = &lt;3&gt;;</div><div class='add'>+			ti,datarate = &lt;4&gt;;</div><div class='add'>+			ti,gain = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* Verdin I2C_1 ADC_4 */</div><div class='add'>+		channel@4 {</div><div class='add'>+			reg = &lt;4&gt;;</div><div class='add'>+			ti,datarate = &lt;4&gt;;</div><div class='add'>+			ti,gain = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* Verdin I2C_1 ADC_3 */</div><div class='add'>+		channel@5 {</div><div class='add'>+			reg = &lt;5&gt;;</div><div class='add'>+			ti,datarate = &lt;4&gt;;</div><div class='add'>+			ti,gain = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* Verdin I2C_1 ADC_2 */</div><div class='add'>+		channel@6 {</div><div class='add'>+			reg = &lt;6&gt;;</div><div class='add'>+			ti,datarate = &lt;4&gt;;</div><div class='add'>+			ti,gain = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* Verdin I2C_1 ADC_1 */</div><div class='add'>+		channel@7 {</div><div class='add'>+			reg = &lt;7&gt;;</div><div class='add'>+			ti,datarate = &lt;4&gt;;</div><div class='add'>+			ti,gain = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@50 {</div><div class='add'>+		compatible = "st,24c02", "atmel,24c02";</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin I2C_2_DSI */</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c2_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	single-master;</div><div class='add'>+</div><div class='add'>+	atmel_mxt_ts_mezzanine: touch-mezzanine@4a {</div><div class='add'>+		compatible = "atmel,maxtouch";</div><div class='add'>+		/* Verdin GPIO_3 (SODIMM 210) */</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;5 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		reg = &lt;0x4a&gt;;</div><div class='add'>+		/* Verdin GPIO_2 (SODIMM 208) */</div><div class='add'>+		reset-gpios = &lt;&amp;gpio1 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin I2C_4_CSI */</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c3_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	single-master;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin I2C_1 */</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c4&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c4_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	single-master;</div><div class='add'>+</div><div class='add'>+	gpio_expander_21: gpio-expander@21 {</div><div class='add'>+		compatible = "nxp,pcal6416";</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		reg = &lt;0x21&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lvds_ti_sn65dsi84: bridge@2c {</div><div class='add'>+		compatible = "ti,sn65dsi84";</div><div class='add'>+		/* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */</div><div class='add'>+		/* Verdin GPIO_10_DSI (SODIMM 21) */</div><div class='add'>+		enable-gpios = &lt;&amp;gpio4 28 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_10_dsi&gt;;</div><div class='add'>+		reg = &lt;0x2c&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Current measurement into module VCC */</div><div class='add'>+	hwmon: hwmon@40 {</div><div class='add'>+		compatible = "ti,ina219";</div><div class='add'>+		reg = &lt;0x40&gt;;</div><div class='add'>+		shunt-resistor = &lt;10000&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdmi_lontium_lt8912: hdmi@48 {</div><div class='add'>+		compatible = "lontium,lt8912b";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_10_dsi&gt;, &lt;&amp;pinctrl_pwm_3_dsi_hpd_gpio&gt;;</div><div class='add'>+		reg = &lt;0x48&gt;;</div><div class='add'>+		/* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */</div><div class='add'>+		/* Verdin GPIO_10_DSI (SODIMM 21) */</div><div class='add'>+		reset-gpios = &lt;&amp;gpio4 28 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	atmel_mxt_ts: touch@4a {</div><div class='add'>+		compatible = "atmel,maxtouch";</div><div class='add'>+		/*</div><div class='add'>+		 * Verdin GPIO_9_DSI</div><div class='add'>+		 * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI84 IRQ albeit currently unused)</div><div class='add'>+		 */</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;25 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_9_dsi&gt;, &lt;&amp;pinctrl_i2s_2_bclk_touch_reset&gt;;</div><div class='add'>+		reg = &lt;0x4a&gt;;</div><div class='add'>+		/* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */</div><div class='add'>+		reset-gpios = &lt;&amp;gpio5 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Temperature sensor on carrier board */</div><div class='add'>+	hwmon_temp: sensor@4f {</div><div class='add'>+		compatible = "ti,tmp75c";</div><div class='add'>+		reg = &lt;0x4f&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* EEPROM on display adapter (MIPI DSI Display Adapter) */</div><div class='add'>+	eeprom_display_adapter: eeprom@50 {</div><div class='add'>+		compatible = "st,24c02", "atmel,24c02";</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* EEPROM on carrier board */</div><div class='add'>+	eeprom_carrier_board: eeprom@57 {</div><div class='add'>+		compatible = "st,24c02", "atmel,24c02";</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+		reg = &lt;0x57&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin I2C_3_HDMI */</div><div class='add'>+&amp;i2c5 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c5&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c5_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	single-master;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin PCIE_1 */</div><div class='add'>+&amp;pcie {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie&gt;;</div><div class='add'>+	/* PCIE_1_RESET# (SODIMM 244) */</div><div class='add'>+	reset-gpio = &lt;&amp;gpio4 19 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	clocks = &lt;&amp;hsio_blk_ctrl&gt;;</div><div class='add'>+	clock-names = "ref";</div><div class='add'>+	fsl,clkreq-unsupported;</div><div class='add'>+	fsl,refclk-pad-mode = &lt;IMX8_PCIE_REFCLK_PAD_OUTPUT&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin PWM_1 */</div><div class='add'>+&amp;pwm1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm_1&gt;;</div><div class='add'>+	#pwm-cells = &lt;3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin PWM_2 */</div><div class='add'>+&amp;pwm2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm_2&gt;;</div><div class='add'>+	#pwm-cells = &lt;3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin PWM_3_DSI */</div><div class='add'>+&amp;pwm3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm_3&gt;;</div><div class='add'>+	#pwm-cells = &lt;3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* TODO: Verdin I2S_1 */</div><div class='add'>+</div><div class='add'>+/* TODO: Verdin I2S_2 */</div><div class='add'>+</div><div class='add'>+&amp;snvs_pwrkey {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin UART_1 */</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin UART_2 */</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin UART_3, used as the Linux Console */</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin UART_4, used for Bluetooth on Wi-Fi/Bluetooth SKUs */</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart4&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin USB_1 */</div><div class='add'>+&amp;usb3_0 {</div><div class='add'>+	fsl,disable-port-power-control;</div><div class='add'>+	fsl,over-current-active-low;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usb_1_oc_n&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_0 {</div><div class='add'>+	/* dual role only, not full featured OTG */</div><div class='add'>+	adp-disable;</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	hnp-disable;</div><div class='add'>+	maximum-speed = "high-speed";</div><div class='add'>+	role-switch-default-mode = "peripheral";</div><div class='add'>+	srp-disable;</div><div class='add'>+	usb-role-switch;</div><div class='add'>+</div><div class='add'>+	port {</div><div class='add'>+		usb3_dwc: endpoint {</div><div class='add'>+			remote-endpoint = &lt;&amp;usb_dr_connector&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin USB_2 */</div><div class='add'>+&amp;usb3_1 {</div><div class='add'>+	fsl,disable-port-power-control;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy1 {</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usb2_vbus&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_1 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Verdin SD_1 */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_USDHC2&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_cd&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_cd&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_cd&gt;;</div><div class='add'>+	pinctrl-3 = &lt;&amp;pinctrl_usdhc2_sleep&gt;, &lt;&amp;pinctrl_usdhc2_cd_sleep&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_vdd_sdio&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* On-module eMMC */</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MP_CLK_USDHC3_ROOT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_bt_uart: btuartgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS	0x1c4&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX		0x1c4&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX		0x1c4&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS		0x1c4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29		0x1c4&gt;;	/* SODIMM 256 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi1: ecspi1grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO		0x1c4&gt;,	/* SODIMM 198 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI		0x4&gt;,	/* SODIMM 200 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK		0x4&gt;,	/* SODIMM 196 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09		0x1c4&gt;;	/* SODIMM 202 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Connection On Board PHY */</div><div class='add'>+	pinctrl_eqos: eqosgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x3&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x3&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x91&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x91&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x91&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x91&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x91&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x1f&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x1f&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x1f&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x1f&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x1f&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* ETH_INT# shared with TPM_INT# (usually N/A) */</div><div class='add'>+	pinctrl_eth_tpm_int: ethtpmintgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10		0x1c4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Connection Carrier Board PHY ETH_2 */</div><div class='add'>+	pinctrl_fec: fecgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3&gt;,	/* SODIMM 193 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3&gt;,	/* SODIMM 191 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0	0x91&gt;,	/* SODIMM 201 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1	0x91&gt;,	/* SODIMM 203 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2	0x91&gt;,	/* SODIMM 205 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3	0x91&gt;,	/* SODIMM 207 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91&gt;,	/* SODIMM 197 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91&gt;,	/* SODIMM 199 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0	0x1f&gt;,	/* SODIMM 221 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1	0x1f&gt;,	/* SODIMM 219 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2	0x1f&gt;,	/* SODIMM 217 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3	0x1f&gt;,	/* SODIMM 215 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f&gt;,	/* SODIMM 211 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC	0x1f&gt;,	/* SODIMM 213 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18		0x1c4&gt;;	/* SODIMM 189 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec_sleep: fecsleepgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3&gt;,	/* SODIMM 193 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3&gt;,	/* SODIMM 191 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0	0x91&gt;,	/* SODIMM 201 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1	0x91&gt;,	/* SODIMM 203 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2	0x91&gt;,	/* SODIMM 205 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3	0x91&gt;,	/* SODIMM 207 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91&gt;,	/* SODIMM 197 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91&gt;,	/* SODIMM 199 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12		0x1f&gt;,	/* SODIMM 221 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_TXD1__GPIO4_IO13		0x1f&gt;,	/* SODIMM 219 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14		0x1f&gt;,	/* SODIMM 217 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_TXD3__GPIO4_IO15		0x1f&gt;,	/* SODIMM 215 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16		0x1f&gt;,	/* SODIMM 211 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_TXD5__GPIO4_IO17		0x1f&gt;,	/* SODIMM 213 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18		0x184&gt;;	/* SODIMM 189 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan1: flexcan1grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SPDIF_RX__CAN1_RX			0x154&gt;,	/* SODIMM 22 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SPDIF_TX__CAN1_TX			0x154&gt;;	/* SODIMM 20 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan2: flexcan2grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX		0x154&gt;,	/* SODIMM 26 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX		0x154&gt;;	/* SODIMM 24 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexspi0: flexspi0grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK		0x1c2&gt;,	/* SODIMM 52 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B	0x82&gt;,	/* SODIMM 54 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_DQS__FLEXSPI_A_DQS		0x82&gt;,	/* SODIMM 66 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00	0x82&gt;,	/* SODIMM 56 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01	0x82&gt;,	/* SODIMM 58 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02	0x82&gt;,	/* SODIMM 60 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03	0x82&gt;,	/* SODIMM 62 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16		0x82&gt;;	/* SODIMM 64 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio1: gpio1grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00		0x184&gt;;	/* SODIMM 206 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio2: gpio2grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01		0x1c4&gt;;	/* SODIMM 208 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio3: gpio3grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05		0x184&gt;;	/* SODIMM 210 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio4: gpio4grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06		0x184&gt;;	/* SODIMM 212 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio5: gpio5grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07		0x184&gt;;	/* SODIMM 216 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio6: gpio6grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08		0x184&gt;;	/* SODIMM 218 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio7: gpio7grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03		0x184&gt;;	/* SODIMM 220 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio8: gpio8grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01		0x184&gt;;	/* SODIMM 222 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Verdin GPIO_9_DSI (pulled-up as active-low) */</div><div class='add'>+	pinctrl_gpio_9_dsi: gpio9dsigrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25		0x1c4&gt;;	/* SODIMM 17 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Verdin GPIO_10_DSI */</div><div class='add'>+	pinctrl_gpio_10_dsi: gpio10dsigrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28		0x1c4&gt;;	/* SODIMM 21 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Non-wifi MSP usage only */</div><div class='add'>+	pinctrl_gpio_hog1: gpiohog1grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12		0x1c4&gt;,	/* SODIMM 116 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_ECSPI2_MOSI__GPIO5_IO11		0x1c4&gt;,	/* SODIMM 152 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_ECSPI2_SCLK__GPIO5_IO10		0x1c4&gt;,	/* SODIMM 164 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13		0x1c4&gt;;	/* SODIMM 128 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USB_2_OC# */</div><div class='add'>+	pinctrl_gpio_hog2: gpiohog2grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02		0x1c4&gt;;	/* SODIMM 187 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio_hog3: gpiohog3grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			/* CSI_1_MCLK */</div><div class='add'>+			&lt;MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15		0x1c4&gt;;	/* SODIMM 91 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Wifi usage only */</div><div class='add'>+	pinctrl_gpio_hog4: gpiohog4grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_UART4_RXD__GPIO5_IO28		0x1c4&gt;,	/* SODIMM 151 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_UART4_TXD__GPIO5_IO29		0x1c4&gt;;	/* SODIMM 153 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio_keys: gpiokeysgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00		0x1c4&gt;;	/* SODIMM 252 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_hdmi: hdmigrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC	0x140&gt;,	/* SODIMM 63 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD	0x180&gt;;	/* SODIMM 61 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* On-module I2C */</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c6&gt;,	/* PMIC_I2C_SCL */</div><div class='add'>+			&lt;MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001c6&gt;;	/* PMIC_I2C_SDA */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1_gpio: i2c1gpiogrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14		0x400001c6&gt;,	/* PMIC_I2C_SCL */</div><div class='add'>+			&lt;MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15		0x400001c6&gt;;	/* PMIC_I2C_SDA */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Verdin I2C_2_DSI */</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001c6&gt;,	/* SODIMM 55 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA		0x400001c6&gt;;	/* SODIMM 53 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2_gpio: i2c2gpiogrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16		0x400001c6&gt;,	/* SODIMM 55 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17		0x400001c6&gt;;	/* SODIMM 53 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Verdin I2C_4_CSI */</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400001c6&gt;,	/* SODIMM 95 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001c6&gt;;	/* SODIMM 93 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3_gpio: i2c3gpiogrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18		0x400001c6&gt;,	/* SODIMM 95 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19		0x400001c6&gt;;	/* SODIMM 93 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Verdin I2C_1 */</div><div class='add'>+	pinctrl_i2c4: i2c4grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL		0x400001c6&gt;,	/* SODIMM 14 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA		0x400001c6&gt;;	/* SODIMM 12 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4_gpio: i2c4gpiogrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20		0x400001c6&gt;,	/* SODIMM 14 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21		0x400001c6&gt;;	/* SODIMM 12 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Verdin I2C_3_HDMI */</div><div class='add'>+	pinctrl_i2c5: i2c5grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL		0x400001c6&gt;,	/* SODIMM 59 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA		0x400001c6&gt;;	/* SODIMM 57 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c5_gpio: i2c5gpiogrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26		0x400001c6&gt;,	/* SODIMM 59 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27		0x400001c6&gt;;	/* SODIMM 57 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Verdin I2S_2_BCLK (TOUCH_RESET#) */</div><div class='add'>+	pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00		0x184&gt;;	/* SODIMM 42 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Verdin I2S_2_D_OUT shared with SAI3 */</div><div class='add'>+	pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01		0x184&gt;;	/* SODIMM 46 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie: pciegrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19		0x4&gt;,	/* SODIMM 244 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19		0x1c4&gt;;	/* PMIC_EN_PCIe_CLK, unused */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: pmicirqgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03		0x1c4&gt;;	/* PMIC_INT# */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm_1: pwm1grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT		0x6&gt;;	/* SODIMM 15 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm_2: pwm2grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT		0x6&gt;;	/* SODIMM 16 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Verdin PWM_3_DSI shared with GPIO3_IO20 */</div><div class='add'>+	pinctrl_pwm_3: pwm3grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT		0x6&gt;;	/* SODIMM 19 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM3_OUT */</div><div class='add'>+	pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsi1hpdgpiogrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20		0x184&gt;;	/* SODIMM 19 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_eth: regethgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_WP__GPIO2_IO20		0x184&gt;;	/* PMIC_EN_ETH */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai1: sai1grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK		0x96&gt;,	/* SODIMM 38 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00	0x1d6&gt;,	/* SODIMM 36 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK		0x1d6&gt;,	/* SODIMM 30 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC		0x1d6&gt;,	/* SODIMM 32 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00	0x96&gt;;	/* SODIMM 34 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai3: sai3grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00	0x1d6&gt;,	/* SODIMM 48 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK	0x1d6&gt;,	/* SODIMM 42 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00	0x96&gt;,	/* SODIMM 46 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC	0x1d6&gt;;	/* SODIMM 44 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS		0x1c4&gt;,	/* SODIMM 135 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS		0x1c4&gt;,	/* SODIMM 133 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX		0x1c4&gt;,	/* SODIMM 129 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX		0x1c4&gt;;	/* SODIMM 131 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS		0x1c4&gt;,	/* SODIMM 143 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS		0x1c4&gt;,	/* SODIMM 141 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX		0x1c4&gt;,	/* SODIMM 137 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX		0x1c4&gt;; /* SODIMM 139 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: uart3grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX		0x1c4&gt;,	/* SODIMM 147 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX		0x1c4&gt;;	/* SODIMM 149 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Non-wifi usage only */</div><div class='add'>+	pinctrl_uart4: uart4grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX		0x1c4&gt;,	/* SODIMM 151 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX		0x1c4&gt;;	/* SODIMM 153 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usb1_vbus: usb1vbusgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12		0x106&gt;;	/* SODIMM 155 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USB_1_ID */</div><div class='add'>+	pinctrl_usb_1_id: usb1idgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10		0x1c4&gt;;	/* SODIMM 161 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USB_1_OC# */</div><div class='add'>+	pinctrl_usb_1_oc_n: usb1ocngrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC		0x1c4&gt;;	/* SODIMM 157 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usb2_vbus: usb2vbusgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14		0x106&gt;;	/* SODIMM 185 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* On-module Wi-Fi */</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x190&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d0&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d0&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d0&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d0&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x194&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d4&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d4&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d4&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d4&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x196&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d6&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d6&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d6&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d6&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d6&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_cd: usdhc2cdgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12		0x1c4&gt;;	/* SODIMM 84 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12		0x0&gt;;	/* SODIMM 84 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22		0x4&gt;;	/* SODIMM 76 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0x4&gt;,	/* PMIC_USDHC_VSELECT */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x190&gt;,	/* SODIMM 78 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d0&gt;,	/* SODIMM 74 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d0&gt;,	/* SODIMM 80 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d0&gt;,	/* SODIMM 82 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d0&gt;,	/* SODIMM 70 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d0&gt;;	/* SODIMM 72 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0x4&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x194&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d4&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d4&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d4&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d4&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0x4&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x196&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d6&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d6&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d6&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d6&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d6&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Avoid backfeeding with removed card power */</div><div class='add'>+	pinctrl_usdhc2_sleep: usdhc2slpgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0x0&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x100&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x100&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x100&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x100&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x100&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x100&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B	0x1d1&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x190&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d0&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d0&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d0&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d0&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d0&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d0&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d0&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d0&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x190&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B	0x1d1&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x194&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d4&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d4&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d4&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d4&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d4&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d4&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d4&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B	0x1d1&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x196&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d2&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d2&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d2&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d2&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d2&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d2&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d2&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d2&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x196&gt;,</div><div class='add'>+			&lt;MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d6&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B		0xc6&gt;;	/* PMIC_WDI */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_bluetooth_ctrl: bluetoothctrlgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08		0x1c4&gt;;	/* WIFI_WKUP_BT */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wifi_ctrl: wifictrlgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09		0x1c4&gt;;	/* WIFI_WKUP_WLAN */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wifi_i2s: wifii2sgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21		0x1d6&gt;,	/* WIFI_TX_SYNC */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21		0x96&gt;,	/* WIFI_RX_DATA0 */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23		0x1d6&gt;,	/* WIFI_TX_BCLK */</div><div class='add'>+			&lt;MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24		0x1d6&gt;;	/* WIFI_TX_DATA0 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wifi_pwr_en: wifipwrengrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11		0x184&gt;;	/* PMIC_EN_WIFI */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi<br/>index 9b1616e59d58..9b2b3a9bf9e8 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mp.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mp.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mp.dtsi</a></div><div class='hunk'>@@ -4,10 +4,16 @@</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;dt-bindings/clock/imx8mp-clock.h&gt;</div><div class='add'>+#include &lt;dt-bindings/power/imx8mp-power.h&gt;</div><div class='add'>+#include &lt;dt-bindings/reset/imx8mp-reset.h&gt;</div><div class='add'>+#include &lt;dt-bindings/reset/imx8mp-reset-audiomix.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interconnect/fsl,imx8mp.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/thermal/thermal.h&gt;</div><div class='ctx'> </div><div class='add'>+#include "imx8mp-aipstz.h"</div><div class='ctx'> #include "imx8mp-pinfunc.h"</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='hunk'>@@ -17,11 +23,18 @@</div><div class='ctx'> </div><div class='ctx'> 	aliases {</div><div class='ctx'> 		ethernet0 = &amp;fec;</div><div class='add'>+		ethernet1 = &amp;eqos;</div><div class='ctx'> 		gpio0 = &amp;gpio1;</div><div class='ctx'> 		gpio1 = &amp;gpio2;</div><div class='ctx'> 		gpio2 = &amp;gpio3;</div><div class='ctx'> 		gpio3 = &amp;gpio4;</div><div class='ctx'> 		gpio4 = &amp;gpio5;</div><div class='add'>+		i2c0 = &amp;i2c1;</div><div class='add'>+		i2c1 = &amp;i2c2;</div><div class='add'>+		i2c2 = &amp;i2c3;</div><div class='add'>+		i2c3 = &amp;i2c4;</div><div class='add'>+		i2c4 = &amp;i2c5;</div><div class='add'>+		i2c5 = &amp;i2c6;</div><div class='ctx'> 		mmc0 = &amp;usdhc1;</div><div class='ctx'> 		mmc1 = &amp;usdhc2;</div><div class='ctx'> 		mmc2 = &amp;usdhc3;</div><div class='hunk'>@@ -29,54 +42,161 @@</div><div class='ctx'> 		serial1 = &amp;uart2;</div><div class='ctx'> 		serial2 = &amp;uart3;</div><div class='ctx'> 		serial3 = &amp;uart4;</div><div class='add'>+		spi0 = &amp;flexspi;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	cpus {</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;0&gt;;</div><div class='ctx'> </div><div class='add'>+		idle-states {</div><div class='add'>+			entry-method = "psci";</div><div class='add'>+</div><div class='add'>+			cpu_pd_wait: cpu-pd-wait {</div><div class='add'>+				compatible = "arm,idle-state";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x0010033&gt;;</div><div class='add'>+				local-timer-stop;</div><div class='add'>+				entry-latency-us = &lt;1000&gt;;</div><div class='add'>+				exit-latency-us = &lt;700&gt;;</div><div class='add'>+				min-residency-us = &lt;2700&gt;;</div><div class='add'>+				wakeup-latency-us = &lt;1500&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		A53_0: cpu@0 {</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			reg = &lt;0x0&gt;;</div><div class='del'>-			clock-latency = &lt;61036&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;clk IMX8MP_CLK_ARM&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;A53_L2&gt;;</div><div class='add'>+			nvmem-cells = &lt;&amp;cpu_speed_grade&gt;;</div><div class='add'>+			nvmem-cell-names = "speed_grade";</div><div class='add'>+			operating-points-v2 = &lt;&amp;a53_opp_table&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_pd_wait&gt;;</div><div class='add'>+</div><div class='add'>+			cpu0_therm: thermal-idle {</div><div class='add'>+				#cooling-cells = &lt;2&gt;;</div><div class='add'>+				duration-us = &lt;10000&gt;;</div><div class='add'>+				exit-latency-us = &lt;700&gt;;</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		A53_1: cpu@1 {</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			reg = &lt;0x1&gt;;</div><div class='del'>-			clock-latency = &lt;61036&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;clk IMX8MP_CLK_ARM&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;A53_L2&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;a53_opp_table&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_pd_wait&gt;;</div><div class='add'>+</div><div class='add'>+			cpu1_therm: thermal-idle {</div><div class='add'>+				#cooling-cells = &lt;2&gt;;</div><div class='add'>+				duration-us = &lt;10000&gt;;</div><div class='add'>+				exit-latency-us = &lt;700&gt;;</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		A53_2: cpu@2 {</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			reg = &lt;0x2&gt;;</div><div class='del'>-			clock-latency = &lt;61036&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;clk IMX8MP_CLK_ARM&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;A53_L2&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;a53_opp_table&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_pd_wait&gt;;</div><div class='add'>+</div><div class='add'>+			cpu2_therm: thermal-idle {</div><div class='add'>+				#cooling-cells = &lt;2&gt;;</div><div class='add'>+				duration-us = &lt;10000&gt;;</div><div class='add'>+				exit-latency-us = &lt;700&gt;;</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		A53_3: cpu@3 {</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			reg = &lt;0x3&gt;;</div><div class='del'>-			clock-latency = &lt;61036&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;clk IMX8MP_CLK_ARM&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;A53_L2&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;a53_opp_table&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_pd_wait&gt;;</div><div class='add'>+</div><div class='add'>+			cpu3_therm: thermal-idle {</div><div class='add'>+				#cooling-cells = &lt;2&gt;;</div><div class='add'>+				duration-us = &lt;10000&gt;;</div><div class='add'>+				exit-latency-us = &lt;700&gt;;</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		A53_L2: l2-cache0 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-size = &lt;0x80000&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;512&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	a53_opp_table: opp-table {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+		opp-shared;</div><div class='add'>+</div><div class='add'>+		opp-1200000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1200000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;850000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x8a0&gt;, &lt;0x7&gt;;</div><div class='add'>+			clock-latency-ns = &lt;150000&gt;;</div><div class='add'>+			opp-suspend;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1600000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1600000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;950000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0xa0&gt;, &lt;0x7&gt;;</div><div class='add'>+			clock-latency-ns = &lt;150000&gt;;</div><div class='add'>+			opp-suspend;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1800000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1800000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x20&gt;, &lt;0x3&gt;;</div><div class='add'>+			clock-latency-ns = &lt;150000&gt;;</div><div class='add'>+			opp-suspend;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -118,34 +238,331 @@</div><div class='ctx'> 	clk_ext4: clock-ext4 {</div><div class='ctx'> 		compatible = "fixed-clock";</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='del'>-		clock-frequency= &lt;133000000&gt;;</div><div class='add'>+		clock-frequency = &lt;133000000&gt;;</div><div class='ctx'> 		clock-output-names = "clk_ext4";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	funnel {</div><div class='add'>+		/*</div><div class='add'>+		 * non-configurable funnel don't show up on the AMBA</div><div class='add'>+		 * bus.  As such no need to add "arm,primecell".</div><div class='add'>+		 */</div><div class='add'>+		compatible = "arm,coresight-static-funnel";</div><div class='add'>+</div><div class='add'>+		in-ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				ca_funnel_in_port0: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;etm0_out_port&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				ca_funnel_in_port1: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;etm1_out_port&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@2 {</div><div class='add'>+				reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+				ca_funnel_in_port2: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;etm2_out_port&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@3 {</div><div class='add'>+				reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+					ca_funnel_in_port3: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;etm3_out_port&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		out-ports {</div><div class='add'>+			port {</div><div class='add'>+</div><div class='add'>+				ca_funnel_out_port0: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;hugo_funnel_in_port0&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		dsp_reserved: dsp@92400000 {</div><div class='add'>+			reg = &lt;0 0x92400000 0 0x1000000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu {</div><div class='add'>+		compatible = "arm,cortex-a53-pmu";</div><div class='add'>+		interrupts = &lt;GIC_PPI 7</div><div class='add'>+			     (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	psci {</div><div class='ctx'> 		compatible = "arm,psci-1.0";</div><div class='ctx'> 		method = "smc";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	thermal-zones {</div><div class='add'>+		cpu-thermal {</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			polling-delay = &lt;2000&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;tmu 1&gt;;</div><div class='add'>+			trips {</div><div class='add'>+				cpu_alert0: trip0 {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_crit0: trip1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu_alert0&gt;;</div><div class='add'>+					cooling-device =</div><div class='add'>+						&lt;&amp;A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+						&lt;&amp;A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+						&lt;&amp;A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+						&lt;&amp;A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+						&lt;&amp;gpu3d THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+						&lt;&amp;gpu2d THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+						&lt;&amp;npu THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+						&lt;&amp;cpu0_therm 0 50&gt;,</div><div class='add'>+						&lt;&amp;cpu1_therm 0 50&gt;,</div><div class='add'>+						&lt;&amp;cpu2_therm 0 50&gt;,</div><div class='add'>+						&lt;&amp;cpu3_therm 0 50&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		soc-thermal {</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			polling-delay = &lt;2000&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;tmu 0&gt;;</div><div class='add'>+			trips {</div><div class='add'>+				soc_alert0: trip0 {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				soc_crit0: trip1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;soc_alert0&gt;;</div><div class='add'>+					cooling-device =</div><div class='add'>+						&lt;&amp;A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+						&lt;&amp;A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+						&lt;&amp;A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+						&lt;&amp;A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+						&lt;&amp;gpu3d THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+						&lt;&amp;gpu2d THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+						&lt;&amp;npu THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+						&lt;&amp;cpu0_therm 0 50&gt;,</div><div class='add'>+						&lt;&amp;cpu1_therm 0 50&gt;,</div><div class='add'>+						&lt;&amp;cpu2_therm 0 50&gt;,</div><div class='add'>+						&lt;&amp;cpu3_therm 0 50&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	timer {</div><div class='ctx'> 		compatible = "arm,armv8-timer";</div><div class='del'>-		interrupts = &lt;GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='del'>-			     &lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='del'>-			     &lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='del'>-			     &lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='ctx'> 		clock-frequency = &lt;8000000&gt;;</div><div class='ctx'> 		arm,no-tick-in-suspend;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	soc@0 {</div><div class='del'>-		compatible = "simple-bus";</div><div class='add'>+	soc: soc@0 {</div><div class='add'>+		compatible = "fsl,imx8mp-soc", "simple-bus";</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;1&gt;;</div><div class='ctx'> 		ranges = &lt;0x0 0x0 0x0 0x3e000000&gt;;</div><div class='add'>+		nvmem-cells = &lt;&amp;imx8mp_uid&gt;;</div><div class='add'>+		nvmem-cell-names = "soc_unique_id";</div><div class='add'>+</div><div class='add'>+		etm0: etm@28440000 {</div><div class='add'>+			compatible = "arm,coresight-etm4x", "arm,primecell";</div><div class='add'>+			reg = &lt;0x28440000 0x1000&gt;;</div><div class='add'>+			cpu = &lt;&amp;A53_0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MP_CLK_MAIN_AXI&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					etm0_out_port: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ca_funnel_in_port0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		etm1: etm@28540000 {</div><div class='add'>+			compatible = "arm,coresight-etm4x", "arm,primecell";</div><div class='add'>+			reg = &lt;0x28540000 0x1000&gt;;</div><div class='add'>+			cpu = &lt;&amp;A53_1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MP_CLK_MAIN_AXI&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					etm1_out_port: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ca_funnel_in_port1&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		etm2: etm@28640000 {</div><div class='add'>+			compatible = "arm,coresight-etm4x", "arm,primecell";</div><div class='add'>+			reg = &lt;0x28640000 0x1000&gt;;</div><div class='add'>+			cpu = &lt;&amp;A53_2&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MP_CLK_MAIN_AXI&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					etm2_out_port: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ca_funnel_in_port2&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		etm3: etm@28740000 {</div><div class='add'>+			compatible = "arm,coresight-etm4x", "arm,primecell";</div><div class='add'>+			reg = &lt;0x28740000 0x1000&gt;;</div><div class='add'>+			cpu = &lt;&amp;A53_3&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MP_CLK_MAIN_AXI&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					etm3_out_port: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ca_funnel_in_port3&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		funnel@28c03000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";</div><div class='add'>+			reg = &lt;0x28c03000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MP_CLK_MAIN_AXI&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					hugo_funnel_in_port0: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ca_funnel_out_port0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					hugo_funnel_in_port1: endpoint {</div><div class='add'>+					/* M7 input */</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@2 {</div><div class='add'>+					reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+					hugo_funnel_in_port2: endpoint {</div><div class='add'>+					/* DSP input */</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+				/* the other input ports are not connect to anything */</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					hugo_funnel_out_port0: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;etf_in_port&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		etf@28c04000 {</div><div class='add'>+			compatible = "arm,coresight-tmc", "arm,primecell";</div><div class='add'>+			reg = &lt;0x28c04000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MP_CLK_MAIN_AXI&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				port {</div><div class='add'>+					etf_in_port: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;hugo_funnel_out_port0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					etf_out_port: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;etr_in_port&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		etr@28c06000 {</div><div class='add'>+			compatible = "arm,coresight-tmc", "arm,primecell";</div><div class='add'>+			reg = &lt;0x28c06000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MP_CLK_MAIN_AXI&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				port {</div><div class='add'>+					etr_in_port: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;etf_out_port&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='ctx'> </div><div class='ctx'> 		aips1: bus@30000000 {</div><div class='ctx'> 			compatible = "fsl,aips-bus", "simple-bus";</div><div class='del'>-			reg = &lt;0x301f0000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x30000000 0x400000&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;1&gt;;</div><div class='ctx'> 			ranges;</div><div class='hunk'>@@ -186,7 +603,7 @@</div><div class='ctx'> 				#gpio-cells = &lt;2&gt;;</div><div class='ctx'> 				interrupt-controller;</div><div class='ctx'> 				#interrupt-cells = &lt;2&gt;;</div><div class='del'>-				gpio-ranges = &lt;&amp;iomuxc 0 56 26&gt;, &lt;&amp;iomuxc 0 144 4&gt;;</div><div class='add'>+				gpio-ranges = &lt;&amp;iomuxc 0 56 26&gt;, &lt;&amp;iomuxc 26 144 4&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			gpio4: gpio@30230000 {</div><div class='hunk'>@@ -215,6 +632,15 @@</div><div class='ctx'> 				gpio-ranges = &lt;&amp;iomuxc 0 114 30&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='add'>+			tmu: tmu@30260000 {</div><div class='add'>+				compatible = "fsl,imx8mp-tmu";</div><div class='add'>+				reg = &lt;0x30260000 0x10000&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MP_CLK_TSENSOR_ROOT&gt;;</div><div class='add'>+				nvmem-cells = &lt;&amp;tmu_calib&gt;;</div><div class='add'>+				nvmem-cell-names = "calib";</div><div class='add'>+				#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='ctx'> 			wdog1: watchdog@30280000 {</div><div class='ctx'> 				compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";</div><div class='ctx'> 				reg = &lt;0x30280000 0x10000&gt;;</div><div class='hunk'>@@ -223,33 +649,102 @@</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='add'>+			wdog2: watchdog@30290000 {</div><div class='add'>+				compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";</div><div class='add'>+				reg = &lt;0x30290000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MP_CLK_WDOG2_ROOT&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			wdog3: watchdog@302a0000 {</div><div class='add'>+				compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";</div><div class='add'>+				reg = &lt;0x302a0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MP_CLK_WDOG3_ROOT&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gpt1: timer@302d0000 {</div><div class='add'>+				compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";</div><div class='add'>+				reg = &lt;0x302d0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MP_CLK_GPT1_ROOT&gt;, &lt;&amp;clk IMX8MP_CLK_GPT1&gt;;</div><div class='add'>+				clock-names = "ipg", "per";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gpt2: timer@302e0000 {</div><div class='add'>+				compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";</div><div class='add'>+				reg = &lt;0x302e0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MP_CLK_GPT2_ROOT&gt;, &lt;&amp;clk IMX8MP_CLK_GPT2&gt;;</div><div class='add'>+				clock-names = "ipg", "per";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gpt3: timer@302f0000 {</div><div class='add'>+				compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";</div><div class='add'>+				reg = &lt;0x302f0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MP_CLK_GPT3_ROOT&gt;, &lt;&amp;clk IMX8MP_CLK_GPT3&gt;;</div><div class='add'>+				clock-names = "ipg", "per";</div><div class='add'>+			};</div><div class='add'>+</div><div class='ctx'> 			iomuxc: pinctrl@30330000 {</div><div class='ctx'> 				compatible = "fsl,imx8mp-iomuxc";</div><div class='ctx'> 				reg = &lt;0x30330000 0x10000&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			gpr: iomuxc-gpr@30340000 {</div><div class='add'>+			gpr: syscon@30340000 {</div><div class='ctx'> 				compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";</div><div class='ctx'> 				reg = &lt;0x30340000 0x10000&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			ocotp: ocotp-ctrl@30350000 {</div><div class='del'>-				compatible = "fsl,imx8mp-ocotp", "syscon";</div><div class='add'>+			ocotp: efuse@30350000 {</div><div class='add'>+				compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon";</div><div class='ctx'> 				reg = &lt;0x30350000 0x10000&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;clk IMX8MP_CLK_OCOTP_ROOT&gt;;</div><div class='ctx'> 				/* For nvmem subnodes */</div><div class='ctx'> 				#address-cells = &lt;1&gt;;</div><div class='ctx'> 				#size-cells = &lt;1&gt;;</div><div class='ctx'> </div><div class='del'>-				cpu_speed_grade: speed-grade@10 {</div><div class='add'>+				/*</div><div class='add'>+				 * The register address below maps to the MX8M</div><div class='add'>+				 * Fusemap Description Table entries this way.</div><div class='add'>+				 * Assuming</div><div class='add'>+				 *   reg = &lt;ADDR SIZE&gt;;</div><div class='add'>+				 * then</div><div class='add'>+				 *   Fuse Address = (ADDR * 4) + 0x400</div><div class='add'>+				 * Note that if SIZE is greater than 4, then</div><div class='add'>+				 * each subsequent fuse is located at offset</div><div class='add'>+				 * +0x10 in Fusemap Description Table (e.g.</div><div class='add'>+				 * reg = &lt;0x8 0x8&gt; describes fuses 0x420 and</div><div class='add'>+				 * 0x430).</div><div class='add'>+				 */</div><div class='add'>+				imx8mp_uid: unique-id@8 { /* 0x420-0x430 */</div><div class='add'>+					reg = &lt;0x8 0x8&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_speed_grade: speed-grade@10 { /* 0x440 */</div><div class='ctx'> 					reg = &lt;0x10 4&gt;;</div><div class='ctx'> 				};</div><div class='add'>+</div><div class='add'>+				eth_mac1: mac-address@90 { /* 0x640 */</div><div class='add'>+					reg = &lt;0x90 6&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				eth_mac2: mac-address@96 { /* 0x658 */</div><div class='add'>+					reg = &lt;0x96 6&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tmu_calib: calib@264 { /* 0xd90-0xdc0 */</div><div class='add'>+					reg = &lt;0x264 0x10&gt;;</div><div class='add'>+				};</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			anatop: anatop@30360000 {</div><div class='del'>-				compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop",</div><div class='del'>-					     "syscon";</div><div class='add'>+			anatop: clock-controller@30360000 {</div><div class='add'>+				compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop";</div><div class='ctx'> 				reg = &lt;0x30360000 0x10000&gt;;</div><div class='add'>+				#clock-cells = &lt;1&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			snvs: snvs@30370000 {</div><div class='hunk'>@@ -258,7 +753,7 @@</div><div class='ctx'> </div><div class='ctx'> 				snvs_rtc: snvs-rtc-lp {</div><div class='ctx'> 					compatible = "fsl,sec-v4.0-mon-rtc-lp";</div><div class='del'>-					regmap =&lt;&amp;snvs&gt;;</div><div class='add'>+					regmap = &lt;&amp;snvs&gt;;</div><div class='ctx'> 					offset = &lt;0x34&gt;;</div><div class='ctx'> 					interrupts = &lt;GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 						     &lt;GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='hunk'>@@ -276,49 +771,207 @@</div><div class='ctx'> 					wakeup-source;</div><div class='ctx'> 					status = "disabled";</div><div class='ctx'> 				};</div><div class='add'>+</div><div class='add'>+				snvs_lpgpr: snvs-lpgpr {</div><div class='add'>+					compatible = "fsl,imx8mp-snvs-lpgpr",</div><div class='add'>+						     "fsl,imx7d-snvs-lpgpr";</div><div class='add'>+				};</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			clk: clock-controller@30380000 {</div><div class='ctx'> 				compatible = "fsl,imx8mp-ccm";</div><div class='ctx'> 				reg = &lt;0x30380000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				#clock-cells = &lt;1&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;osc_32k&gt;, &lt;&amp;osc_24m&gt;, &lt;&amp;clk_ext1&gt;, &lt;&amp;clk_ext2&gt;,</div><div class='ctx'> 					 &lt;&amp;clk_ext3&gt;, &lt;&amp;clk_ext4&gt;;</div><div class='ctx'> 				clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",</div><div class='ctx'> 					      "clk_ext3", "clk_ext4";</div><div class='del'>-				assigned-clocks = &lt;&amp;clk IMX8MP_CLK_NOC&gt;,</div><div class='add'>+				assigned-clocks = &lt;&amp;clk IMX8MP_CLK_A53_SRC&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX8MP_CLK_A53_CORE&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX8MP_CLK_NOC&gt;,</div><div class='ctx'> 						  &lt;&amp;clk IMX8MP_CLK_NOC_IO&gt;,</div><div class='del'>-						  &lt;&amp;clk IMX8MP_CLK_GIC&gt;,</div><div class='del'>-						  &lt;&amp;clk IMX8MP_CLK_AUDIO_AHB&gt;,</div><div class='del'>-						  &lt;&amp;clk IMX8MP_CLK_AUDIO_AXI_SRC&gt;,</div><div class='del'>-						  &lt;&amp;clk IMX8MP_CLK_IPG_AUDIO_ROOT&gt;,</div><div class='del'>-						  &lt;&amp;clk IMX8MP_AUDIO_PLL1&gt;,</div><div class='del'>-						  &lt;&amp;clk IMX8MP_AUDIO_PLL2&gt;;</div><div class='del'>-				assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL2_1000M&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX8MP_CLK_GIC&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL1_800M&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MP_ARM_PLL_OUT&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MP_SYS_PLL2_1000M&gt;,</div><div class='ctx'> 							 &lt;&amp;clk IMX8MP_SYS_PLL1_800M&gt;,</div><div class='del'>-							 &lt;&amp;clk IMX8MP_SYS_PLL2_500M&gt;,</div><div class='del'>-							 &lt;&amp;clk IMX8MP_SYS_PLL1_800M&gt;,</div><div class='del'>-							 &lt;&amp;clk IMX8MP_SYS_PLL1_800M&gt;;</div><div class='del'>-				assigned-clock-rates = &lt;1000000000&gt;,</div><div class='del'>-						       &lt;800000000&gt;,</div><div class='del'>-						       &lt;500000000&gt;,</div><div class='del'>-						       &lt;400000000&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MP_SYS_PLL2_500M&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;0&gt;, &lt;0&gt;,</div><div class='add'>+						       &lt;1000000000&gt;,</div><div class='ctx'> 						       &lt;800000000&gt;,</div><div class='del'>-						       &lt;400000000&gt;,</div><div class='del'>-						       &lt;393216000&gt;,</div><div class='del'>-						       &lt;361267200&gt;;</div><div class='add'>+						       &lt;500000000&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			src: reset-controller@30390000 {</div><div class='ctx'> 				compatible = "fsl,imx8mp-src", "syscon";</div><div class='ctx'> 				reg = &lt;0x30390000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				#reset-cells = &lt;1&gt;;</div><div class='ctx'> 			};</div><div class='add'>+</div><div class='add'>+			gpc: gpc@303a0000 {</div><div class='add'>+				compatible = "fsl,imx8mp-gpc";</div><div class='add'>+				reg = &lt;0x303a0000 0x1000&gt;;</div><div class='add'>+				interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+				pgc {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					pgc_mipi_phy1: power-domain@0 {</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						reg = &lt;IMX8MP_POWER_DOMAIN_MIPI_PHY1&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					pgc_pcie_phy: power-domain@1 {</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						reg = &lt;IMX8MP_POWER_DOMAIN_PCIE_PHY&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					pgc_usb1_phy: power-domain@2 {</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						reg = &lt;IMX8MP_POWER_DOMAIN_USB1_PHY&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					pgc_usb2_phy: power-domain@3 {</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						reg = &lt;IMX8MP_POWER_DOMAIN_USB2_PHY&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					pgc_mlmix: power-domain@4 {</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						reg = &lt;IMX8MP_POWER_DOMAIN_MLMIX&gt;;</div><div class='add'>+						clocks = &lt;&amp;clk IMX8MP_CLK_ML_AXI&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MP_CLK_ML_AHB&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MP_CLK_NPU_ROOT&gt;;</div><div class='add'>+						assigned-clocks = &lt;&amp;clk IMX8MP_CLK_ML_CORE&gt;,</div><div class='add'>+								  &lt;&amp;clk IMX8MP_CLK_ML_AXI&gt;,</div><div class='add'>+								  &lt;&amp;clk IMX8MP_CLK_ML_AHB&gt;;</div><div class='add'>+						assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL2_1000M&gt;,</div><div class='add'>+									 &lt;&amp;clk IMX8MP_SYS_PLL1_800M&gt;,</div><div class='add'>+									 &lt;&amp;clk IMX8MP_SYS_PLL1_800M&gt;;</div><div class='add'>+						assigned-clock-rates = &lt;1000000000&gt;,</div><div class='add'>+								       &lt;800000000&gt;,</div><div class='add'>+								       &lt;400000000&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					pgc_audio: power-domain@5 {</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						reg = &lt;IMX8MP_POWER_DOMAIN_AUDIOMIX&gt;;</div><div class='add'>+						clocks = &lt;&amp;clk IMX8MP_CLK_AUDIO_ROOT&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MP_CLK_AUDIO_AXI&gt;;</div><div class='add'>+						assigned-clocks = &lt;&amp;clk IMX8MP_CLK_AUDIO_AHB&gt;,</div><div class='add'>+								  &lt;&amp;clk IMX8MP_CLK_AUDIO_AXI_SRC&gt;;</div><div class='add'>+						assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL1_800M&gt;,</div><div class='add'>+									 &lt;&amp;clk IMX8MP_SYS_PLL1_800M&gt;;</div><div class='add'>+						assigned-clock-rates = &lt;400000000&gt;,</div><div class='add'>+								       &lt;800000000&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					pgc_gpu2d: power-domain@6 {</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						reg = &lt;IMX8MP_POWER_DOMAIN_GPU2D&gt;;</div><div class='add'>+						clocks = &lt;&amp;clk IMX8MP_CLK_GPU2D_ROOT&gt;;</div><div class='add'>+						power-domains = &lt;&amp;pgc_gpumix&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					pgc_gpumix: power-domain@7 {</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						reg = &lt;IMX8MP_POWER_DOMAIN_GPUMIX&gt;;</div><div class='add'>+						clocks = &lt;&amp;clk IMX8MP_CLK_GPU_ROOT&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MP_CLK_GPU_AHB&gt;;</div><div class='add'>+						assigned-clocks = &lt;&amp;clk IMX8MP_CLK_GPU_AXI&gt;,</div><div class='add'>+								  &lt;&amp;clk IMX8MP_CLK_GPU_AHB&gt;;</div><div class='add'>+						assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL1_800M&gt;,</div><div class='add'>+									 &lt;&amp;clk IMX8MP_SYS_PLL1_800M&gt;;</div><div class='add'>+						assigned-clock-rates = &lt;800000000&gt;, &lt;400000000&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					pgc_vpumix: power-domain@8 {</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						reg = &lt;IMX8MP_POWER_DOMAIN_VPUMIX&gt;;</div><div class='add'>+						clocks = &lt;&amp;clk IMX8MP_CLK_VPU_ROOT&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					pgc_gpu3d: power-domain@9 {</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						reg = &lt;IMX8MP_POWER_DOMAIN_GPU3D&gt;;</div><div class='add'>+						clocks = &lt;&amp;clk IMX8MP_CLK_GPU3D_ROOT&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MP_CLK_GPU3D_SHADER_CORE&gt;;</div><div class='add'>+						power-domains = &lt;&amp;pgc_gpumix&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					pgc_mediamix: power-domain@10 {</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						reg = &lt;IMX8MP_POWER_DOMAIN_MEDIAMIX&gt;;</div><div class='add'>+						clocks = &lt;&amp;clk IMX8MP_CLK_MEDIA_AXI_ROOT&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MP_CLK_MEDIA_APB_ROOT&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					pgc_vpu_g1: power-domain@11 {</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						reg = &lt;IMX8MP_POWER_DOMAIN_VPU_G1&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					pgc_vpu_g2: power-domain@12 {</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						reg = &lt;IMX8MP_POWER_DOMAIN_VPU_G2&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					pgc_vpu_vc8000e: power-domain@13 {</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						reg = &lt;IMX8MP_POWER_DOMAIN_VPU_VC8000E&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					pgc_hdmimix: power-domain@14 {</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						reg = &lt;IMX8MP_POWER_DOMAIN_HDMIMIX&gt;;</div><div class='add'>+						clocks = &lt;&amp;clk IMX8MP_CLK_HDMI_ROOT&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MP_CLK_HDMI_APB&gt;;</div><div class='add'>+						assigned-clocks = &lt;&amp;clk IMX8MP_CLK_HDMI_AXI&gt;,</div><div class='add'>+								  &lt;&amp;clk IMX8MP_CLK_HDMI_APB&gt;;</div><div class='add'>+						assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL2_500M&gt;,</div><div class='add'>+									 &lt;&amp;clk IMX8MP_SYS_PLL1_133M&gt;;</div><div class='add'>+						assigned-clock-rates = &lt;500000000&gt;, &lt;133000000&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					pgc_hdmi_phy: power-domain@15 {</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						reg = &lt;IMX8MP_POWER_DOMAIN_HDMI_PHY&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					pgc_mipi_phy2: power-domain@16 {</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						reg = &lt;IMX8MP_POWER_DOMAIN_MIPI_PHY2&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					pgc_hsiomix: power-domain@17 {</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						reg = &lt;IMX8MP_POWER_DOMAIN_HSIOMIX&gt;;</div><div class='add'>+						clocks = &lt;&amp;clk IMX8MP_CLK_HSIO_AXI&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MP_CLK_HSIO_ROOT&gt;;</div><div class='add'>+						assigned-clocks = &lt;&amp;clk IMX8MP_CLK_HSIO_AXI&gt;;</div><div class='add'>+						assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL2_500M&gt;;</div><div class='add'>+						assigned-clock-rates = &lt;500000000&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					pgc_ispdwp: power-domain@18 {</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						reg = &lt;IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP&gt;;</div><div class='add'>+						clocks = &lt;&amp;clk IMX8MP_CLK_MEDIA_ISP_ROOT&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		aips2: bus@30400000 {</div><div class='ctx'> 			compatible = "fsl,aips-bus", "simple-bus";</div><div class='del'>-			reg = &lt;0x305f0000 0x400000&gt;;</div><div class='add'>+			reg = &lt;0x30400000 0x400000&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;1&gt;;</div><div class='ctx'> 			ranges;</div><div class='hunk'>@@ -330,7 +983,7 @@</div><div class='ctx'> 				clocks = &lt;&amp;clk IMX8MP_CLK_PWM1_ROOT&gt;,</div><div class='ctx'> 					 &lt;&amp;clk IMX8MP_CLK_PWM1_ROOT&gt;;</div><div class='ctx'> 				clock-names = "ipg", "per";</div><div class='del'>-				#pwm-cells = &lt;2&gt;;</div><div class='add'>+				#pwm-cells = &lt;3&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -341,7 +994,7 @@</div><div class='ctx'> 				clocks = &lt;&amp;clk IMX8MP_CLK_PWM2_ROOT&gt;,</div><div class='ctx'> 					 &lt;&amp;clk IMX8MP_CLK_PWM2_ROOT&gt;;</div><div class='ctx'> 				clock-names = "ipg", "per";</div><div class='del'>-				#pwm-cells = &lt;2&gt;;</div><div class='add'>+				#pwm-cells = &lt;3&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -352,7 +1005,7 @@</div><div class='ctx'> 				clocks = &lt;&amp;clk IMX8MP_CLK_PWM3_ROOT&gt;,</div><div class='ctx'> 					 &lt;&amp;clk IMX8MP_CLK_PWM3_ROOT&gt;;</div><div class='ctx'> 				clock-names = "ipg", "per";</div><div class='del'>-				#pwm-cells = &lt;2&gt;;</div><div class='add'>+				#pwm-cells = &lt;3&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -363,7 +1016,7 @@</div><div class='ctx'> 				clocks = &lt;&amp;clk IMX8MP_CLK_PWM4_ROOT&gt;,</div><div class='ctx'> 					 &lt;&amp;clk IMX8MP_CLK_PWM4_ROOT&gt;;</div><div class='ctx'> 				clock-names = "ipg", "per";</div><div class='del'>-				#pwm-cells = &lt;2&gt;;</div><div class='add'>+				#pwm-cells = &lt;3&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -374,89 +1027,162 @@</div><div class='ctx'> 				clocks = &lt;&amp;osc_24m&gt;;</div><div class='ctx'> 				clock-names = "per";</div><div class='ctx'> 			};</div><div class='add'>+</div><div class='add'>+			gpt6: timer@306e0000 {</div><div class='add'>+				compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";</div><div class='add'>+				reg = &lt;0x306e0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MP_CLK_GPT6_ROOT&gt;, &lt;&amp;clk IMX8MP_CLK_GPT6&gt;;</div><div class='add'>+				clock-names = "ipg", "per";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gpt5: timer@306f0000 {</div><div class='add'>+				compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";</div><div class='add'>+				reg = &lt;0x306f0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MP_CLK_GPT5_ROOT&gt;, &lt;&amp;clk IMX8MP_CLK_GPT5&gt;;</div><div class='add'>+				clock-names = "ipg", "per";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gpt4: timer@30700000 {</div><div class='add'>+				compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";</div><div class='add'>+				reg = &lt;0x30700000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MP_CLK_GPT4_ROOT&gt;, &lt;&amp;clk IMX8MP_CLK_GPT4&gt;;</div><div class='add'>+				clock-names = "ipg", "per";</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		aips3: bus@30800000 {</div><div class='ctx'> 			compatible = "fsl,aips-bus", "simple-bus";</div><div class='del'>-			reg = &lt;0x309f0000 0x400000&gt;;</div><div class='add'>+			reg = &lt;0x30800000 0x400000&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;1&gt;;</div><div class='ctx'> 			ranges;</div><div class='ctx'> </div><div class='del'>-			ecspi1: spi@30820000 {</div><div class='add'>+			spba-bus@30800000 {</div><div class='add'>+				compatible = "fsl,spba-bus", "simple-bus";</div><div class='add'>+				reg = &lt;0x30800000 0x100000&gt;;</div><div class='ctx'> 				#address-cells = &lt;1&gt;;</div><div class='del'>-				#size-cells = &lt;0&gt;;</div><div class='del'>-				compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";</div><div class='del'>-				reg = &lt;0x30820000 0x10000&gt;;</div><div class='del'>-				interrupts = &lt;GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-				clocks = &lt;&amp;clk IMX8MP_CLK_ECSPI1_ROOT&gt;,</div><div class='del'>-					 &lt;&amp;clk IMX8MP_CLK_ECSPI1_ROOT&gt;;</div><div class='del'>-				clock-names = "ipg", "per";</div><div class='del'>-				dmas = &lt;&amp;sdma1 0 7 1&gt;, &lt;&amp;sdma1 1 7 2&gt;;</div><div class='del'>-				dma-names = "rx", "tx";</div><div class='del'>-				status = "disabled";</div><div class='del'>-			};</div><div class='add'>+				#size-cells = &lt;1&gt;;</div><div class='add'>+				ranges;</div><div class='add'>+</div><div class='add'>+				ecspi1: spi@30820000 {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+					compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";</div><div class='add'>+					reg = &lt;0x30820000 0x10000&gt;;</div><div class='add'>+					interrupts = &lt;GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					clocks = &lt;&amp;clk IMX8MP_CLK_ECSPI1_ROOT&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MP_CLK_ECSPI1_ROOT&gt;;</div><div class='add'>+					clock-names = "ipg", "per";</div><div class='add'>+					assigned-clock-rates = &lt;80000000&gt;;</div><div class='add'>+					assigned-clocks = &lt;&amp;clk IMX8MP_CLK_ECSPI1&gt;;</div><div class='add'>+					assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL1_800M&gt;;</div><div class='add'>+					dmas = &lt;&amp;sdma1 0 7 1&gt;, &lt;&amp;sdma1 1 7 2&gt;;</div><div class='add'>+					dma-names = "rx", "tx";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-			ecspi2: spi@30830000 {</div><div class='del'>-				#address-cells = &lt;1&gt;;</div><div class='del'>-				#size-cells = &lt;0&gt;;</div><div class='del'>-				compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";</div><div class='del'>-				reg = &lt;0x30830000 0x10000&gt;;</div><div class='del'>-				interrupts = &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-				clocks = &lt;&amp;clk IMX8MP_CLK_ECSPI2_ROOT&gt;,</div><div class='del'>-					 &lt;&amp;clk IMX8MP_CLK_ECSPI2_ROOT&gt;;</div><div class='del'>-				clock-names = "ipg", "per";</div><div class='del'>-				dmas = &lt;&amp;sdma1 2 7 1&gt;, &lt;&amp;sdma1 3 7 2&gt;;</div><div class='del'>-				dma-names = "rx", "tx";</div><div class='del'>-				status = "disabled";</div><div class='del'>-			};</div><div class='add'>+				ecspi2: spi@30830000 {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+					compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";</div><div class='add'>+					reg = &lt;0x30830000 0x10000&gt;;</div><div class='add'>+					interrupts = &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					clocks = &lt;&amp;clk IMX8MP_CLK_ECSPI2_ROOT&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MP_CLK_ECSPI2_ROOT&gt;;</div><div class='add'>+					clock-names = "ipg", "per";</div><div class='add'>+					assigned-clock-rates = &lt;80000000&gt;;</div><div class='add'>+					assigned-clocks = &lt;&amp;clk IMX8MP_CLK_ECSPI2&gt;;</div><div class='add'>+					assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL1_800M&gt;;</div><div class='add'>+					dmas = &lt;&amp;sdma1 2 7 1&gt;, &lt;&amp;sdma1 3 7 2&gt;;</div><div class='add'>+					dma-names = "rx", "tx";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-			ecspi3: spi@30840000 {</div><div class='del'>-				#address-cells = &lt;1&gt;;</div><div class='del'>-				#size-cells = &lt;0&gt;;</div><div class='del'>-				compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";</div><div class='del'>-				reg = &lt;0x30840000 0x10000&gt;;</div><div class='del'>-				interrupts = &lt;GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-				clocks = &lt;&amp;clk IMX8MP_CLK_ECSPI3_ROOT&gt;,</div><div class='del'>-					 &lt;&amp;clk IMX8MP_CLK_ECSPI3_ROOT&gt;;</div><div class='del'>-				clock-names = "ipg", "per";</div><div class='del'>-				dmas = &lt;&amp;sdma1 4 7 1&gt;, &lt;&amp;sdma1 5 7 2&gt;;</div><div class='del'>-				dma-names = "rx", "tx";</div><div class='del'>-				status = "disabled";</div><div class='del'>-			};</div><div class='add'>+				ecspi3: spi@30840000 {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+					compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";</div><div class='add'>+					reg = &lt;0x30840000 0x10000&gt;;</div><div class='add'>+					interrupts = &lt;GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					clocks = &lt;&amp;clk IMX8MP_CLK_ECSPI3_ROOT&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MP_CLK_ECSPI3_ROOT&gt;;</div><div class='add'>+					clock-names = "ipg", "per";</div><div class='add'>+					assigned-clock-rates = &lt;80000000&gt;;</div><div class='add'>+					assigned-clocks = &lt;&amp;clk IMX8MP_CLK_ECSPI3&gt;;</div><div class='add'>+					assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL1_800M&gt;;</div><div class='add'>+					dmas = &lt;&amp;sdma1 4 7 1&gt;, &lt;&amp;sdma1 5 7 2&gt;;</div><div class='add'>+					dma-names = "rx", "tx";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-			uart1: serial@30860000 {</div><div class='del'>-				compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";</div><div class='del'>-				reg = &lt;0x30860000 0x10000&gt;;</div><div class='del'>-				interrupts = &lt;GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-				clocks = &lt;&amp;clk IMX8MP_CLK_UART1_ROOT&gt;,</div><div class='del'>-					 &lt;&amp;clk IMX8MP_CLK_UART1_ROOT&gt;;</div><div class='del'>-				clock-names = "ipg", "per";</div><div class='del'>-				dmas = &lt;&amp;sdma1 22 4 0&gt;, &lt;&amp;sdma1 23 4 0&gt;;</div><div class='del'>-				dma-names = "rx", "tx";</div><div class='del'>-				status = "disabled";</div><div class='del'>-			};</div><div class='add'>+				uart1: serial@30860000 {</div><div class='add'>+					compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";</div><div class='add'>+					reg = &lt;0x30860000 0x10000&gt;;</div><div class='add'>+					interrupts = &lt;GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					clocks = &lt;&amp;clk IMX8MP_CLK_UART1_ROOT&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MP_CLK_UART1_ROOT&gt;;</div><div class='add'>+					clock-names = "ipg", "per";</div><div class='add'>+					dmas = &lt;&amp;sdma1 22 4 0&gt;, &lt;&amp;sdma1 23 4 0&gt;;</div><div class='add'>+					dma-names = "rx", "tx";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-			uart3: serial@30880000 {</div><div class='del'>-				compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";</div><div class='del'>-				reg = &lt;0x30880000 0x10000&gt;;</div><div class='del'>-				interrupts = &lt;GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-				clocks = &lt;&amp;clk IMX8MP_CLK_UART3_ROOT&gt;,</div><div class='del'>-					 &lt;&amp;clk IMX8MP_CLK_UART3_ROOT&gt;;</div><div class='del'>-				clock-names = "ipg", "per";</div><div class='del'>-				dmas = &lt;&amp;sdma1 26 4 0&gt;, &lt;&amp;sdma1 27 4 0&gt;;</div><div class='del'>-				dma-names = "rx", "tx";</div><div class='del'>-				status = "disabled";</div><div class='del'>-			};</div><div class='add'>+				uart3: serial@30880000 {</div><div class='add'>+					compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";</div><div class='add'>+					reg = &lt;0x30880000 0x10000&gt;;</div><div class='add'>+					interrupts = &lt;GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					clocks = &lt;&amp;clk IMX8MP_CLK_UART3_ROOT&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MP_CLK_UART3_ROOT&gt;;</div><div class='add'>+					clock-names = "ipg", "per";</div><div class='add'>+					dmas = &lt;&amp;sdma1 26 4 0&gt;, &lt;&amp;sdma1 27 4 0&gt;;</div><div class='add'>+					dma-names = "rx", "tx";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='ctx'> </div><div class='del'>-			uart2: serial@30890000 {</div><div class='del'>-				compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";</div><div class='del'>-				reg = &lt;0x30890000 0x10000&gt;;</div><div class='del'>-				interrupts = &lt;GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-				clocks = &lt;&amp;clk IMX8MP_CLK_UART2_ROOT&gt;,</div><div class='del'>-					 &lt;&amp;clk IMX8MP_CLK_UART2_ROOT&gt;;</div><div class='del'>-				clock-names = "ipg", "per";</div><div class='del'>-				status = "disabled";</div><div class='add'>+				uart2: serial@30890000 {</div><div class='add'>+					compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";</div><div class='add'>+					reg = &lt;0x30890000 0x10000&gt;;</div><div class='add'>+					interrupts = &lt;GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					clocks = &lt;&amp;clk IMX8MP_CLK_UART2_ROOT&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MP_CLK_UART2_ROOT&gt;;</div><div class='add'>+					clock-names = "ipg", "per";</div><div class='add'>+					dmas = &lt;&amp;sdma1 24 4 0&gt;, &lt;&amp;sdma1 25 4 0&gt;;</div><div class='add'>+					dma-names = "rx", "tx";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				flexcan1: can@308c0000 {</div><div class='add'>+					compatible = "fsl,imx8mp-flexcan";</div><div class='add'>+					reg = &lt;0x308c0000 0x10000&gt;;</div><div class='add'>+					interrupts = &lt;GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					clocks = &lt;&amp;clk IMX8MP_CLK_IPG_ROOT&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MP_CLK_CAN1_ROOT&gt;;</div><div class='add'>+					clock-names = "ipg", "per";</div><div class='add'>+					assigned-clocks = &lt;&amp;clk IMX8MP_CLK_CAN1&gt;;</div><div class='add'>+					assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL1_40M&gt;;</div><div class='add'>+					assigned-clock-rates = &lt;40000000&gt;;</div><div class='add'>+					fsl,clk-source = /bits/ 8 &lt;0&gt;;</div><div class='add'>+					fsl,stop-mode = &lt;&amp;gpr 0x10 4&gt;;</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				flexcan2: can@308d0000 {</div><div class='add'>+					compatible = "fsl,imx8mp-flexcan";</div><div class='add'>+					reg = &lt;0x308d0000 0x10000&gt;;</div><div class='add'>+					interrupts = &lt;GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					clocks = &lt;&amp;clk IMX8MP_CLK_IPG_ROOT&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MP_CLK_CAN2_ROOT&gt;;</div><div class='add'>+					clock-names = "ipg", "per";</div><div class='add'>+					assigned-clocks = &lt;&amp;clk IMX8MP_CLK_CAN2&gt;;</div><div class='add'>+					assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL1_40M&gt;;</div><div class='add'>+					assigned-clock-rates = &lt;40000000&gt;;</div><div class='add'>+					fsl,clk-source = /bits/ 8 &lt;0&gt;;</div><div class='add'>+					fsl,stop-mode = &lt;&amp;gpr 0x10 5&gt;;</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			crypto: crypto@30900000 {</div><div class='hunk'>@@ -474,6 +1200,7 @@</div><div class='ctx'> 					compatible = "fsl,sec-v4.0-job-ring";</div><div class='ctx'> 					reg = &lt;0x1000 0x1000&gt;;</div><div class='ctx'> 					interrupts = &lt;GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					status = "disabled";</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='ctx'> 				sec_jr1: jr@2000 {</div><div class='hunk'>@@ -541,6 +1268,23 @@</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='add'>+			mu: mailbox@30aa0000 {</div><div class='add'>+				compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";</div><div class='add'>+				reg = &lt;0x30aa0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MP_CLK_MU_ROOT&gt;;</div><div class='add'>+				#mbox-cells = &lt;2&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mu2: mailbox@30e60000 {</div><div class='add'>+				compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";</div><div class='add'>+				reg = &lt;0x30e60000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#mbox-cells = &lt;2&gt;;</div><div class='add'>+				clocks = &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_MU2_ROOT&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='ctx'> 			i2c5: i2c@30ad0000 {</div><div class='ctx'> 				compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";</div><div class='ctx'> 				#address-cells = &lt;1&gt;;</div><div class='hunk'>@@ -562,64 +1306,80 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			usdhc1: mmc@30b40000 {</div><div class='del'>-				compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";</div><div class='add'>+				compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";</div><div class='ctx'> 				reg = &lt;0x30b40000 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-				clocks = &lt;&amp;clk IMX8MP_CLK_DUMMY&gt;,</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MP_CLK_IPG_ROOT&gt;,</div><div class='ctx'> 					 &lt;&amp;clk IMX8MP_CLK_NAND_USDHC_BUS&gt;,</div><div class='ctx'> 					 &lt;&amp;clk IMX8MP_CLK_USDHC1_ROOT&gt;;</div><div class='ctx'> 				clock-names = "ipg", "ahb", "per";</div><div class='ctx'> 				fsl,tuning-start-tap = &lt;20&gt;;</div><div class='del'>-				fsl,tuning-step= &lt;2&gt;;</div><div class='add'>+				fsl,tuning-step = &lt;2&gt;;</div><div class='ctx'> 				bus-width = &lt;4&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			usdhc2: mmc@30b50000 {</div><div class='del'>-				compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";</div><div class='add'>+				compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";</div><div class='ctx'> 				reg = &lt;0x30b50000 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-				clocks = &lt;&amp;clk IMX8MP_CLK_DUMMY&gt;,</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MP_CLK_IPG_ROOT&gt;,</div><div class='ctx'> 					 &lt;&amp;clk IMX8MP_CLK_NAND_USDHC_BUS&gt;,</div><div class='ctx'> 					 &lt;&amp;clk IMX8MP_CLK_USDHC2_ROOT&gt;;</div><div class='ctx'> 				clock-names = "ipg", "ahb", "per";</div><div class='ctx'> 				fsl,tuning-start-tap = &lt;20&gt;;</div><div class='del'>-				fsl,tuning-step= &lt;2&gt;;</div><div class='add'>+				fsl,tuning-step = &lt;2&gt;;</div><div class='ctx'> 				bus-width = &lt;4&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			usdhc3: mmc@30b60000 {</div><div class='del'>-				compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";</div><div class='add'>+				compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";</div><div class='ctx'> 				reg = &lt;0x30b60000 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-				clocks = &lt;&amp;clk IMX8MP_CLK_DUMMY&gt;,</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MP_CLK_IPG_ROOT&gt;,</div><div class='ctx'> 					 &lt;&amp;clk IMX8MP_CLK_NAND_USDHC_BUS&gt;,</div><div class='ctx'> 					 &lt;&amp;clk IMX8MP_CLK_USDHC3_ROOT&gt;;</div><div class='ctx'> 				clock-names = "ipg", "ahb", "per";</div><div class='ctx'> 				fsl,tuning-start-tap = &lt;20&gt;;</div><div class='del'>-				fsl,tuning-step= &lt;2&gt;;</div><div class='add'>+				fsl,tuning-step = &lt;2&gt;;</div><div class='ctx'> 				bus-width = &lt;4&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='add'>+			flexspi: spi@30bb0000 {</div><div class='add'>+				compatible = "nxp,imx8mp-fspi";</div><div class='add'>+				reg = &lt;0x30bb0000 0x10000&gt;, &lt;0x8000000 0x10000000&gt;;</div><div class='add'>+				reg-names = "fspi_base", "fspi_mmap";</div><div class='add'>+				interrupts = &lt;GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MP_CLK_QSPI_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_QSPI_ROOT&gt;;</div><div class='add'>+				clock-names = "fspi_en", "fspi";</div><div class='add'>+				assigned-clock-rates = &lt;80000000&gt;;</div><div class='add'>+				assigned-clocks = &lt;&amp;clk IMX8MP_CLK_QSPI&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='ctx'> 			sdma1: dma-controller@30bd0000 {</div><div class='ctx'> 				compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";</div><div class='ctx'> 				reg = &lt;0x30bd0000 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;clk IMX8MP_CLK_SDMA1_ROOT&gt;,</div><div class='del'>-					 &lt;&amp;clk IMX8MP_CLK_SDMA1_ROOT&gt;;</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_AHB&gt;;</div><div class='ctx'> 				clock-names = "ipg", "ahb";</div><div class='ctx'> 				#dma-cells = &lt;3&gt;;</div><div class='ctx'> 				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			fec: ethernet@30be0000 {</div><div class='del'>-				compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec";</div><div class='add'>+				compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";</div><div class='ctx'> 				reg = &lt;0x30be0000 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 					     &lt;GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-					     &lt;GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					     &lt;GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;clk IMX8MP_CLK_ENET1_ROOT&gt;,</div><div class='ctx'> 					 &lt;&amp;clk IMX8MP_CLK_SIM_ENET_ROOT&gt;,</div><div class='ctx'> 					 &lt;&amp;clk IMX8MP_CLK_ENET_TIMER&gt;,</div><div class='hunk'>@@ -630,25 +1390,1129 @@</div><div class='ctx'> 				assigned-clocks = &lt;&amp;clk IMX8MP_CLK_ENET_AXI&gt;,</div><div class='ctx'> 						  &lt;&amp;clk IMX8MP_CLK_ENET_TIMER&gt;,</div><div class='ctx'> 						  &lt;&amp;clk IMX8MP_CLK_ENET_REF&gt;,</div><div class='del'>-						  &lt;&amp;clk IMX8MP_CLK_ENET_TIMER&gt;;</div><div class='add'>+						  &lt;&amp;clk IMX8MP_CLK_ENET_PHY_REF&gt;;</div><div class='ctx'> 				assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL1_266M&gt;,</div><div class='ctx'> 							 &lt;&amp;clk IMX8MP_SYS_PLL2_100M&gt;,</div><div class='del'>-							 &lt;&amp;clk IMX8MP_SYS_PLL2_125M&gt;;</div><div class='del'>-				assigned-clock-rates = &lt;0&gt;, &lt;0&gt;, &lt;125000000&gt;, &lt;100000000&gt;;</div><div class='add'>+							 &lt;&amp;clk IMX8MP_SYS_PLL2_125M&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MP_SYS_PLL2_50M&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;0&gt;, &lt;100000000&gt;, &lt;125000000&gt;, &lt;0&gt;;</div><div class='ctx'> 				fsl,num-tx-queues = &lt;3&gt;;</div><div class='ctx'> 				fsl,num-rx-queues = &lt;3&gt;;</div><div class='add'>+				nvmem-cells = &lt;&amp;eth_mac1&gt;;</div><div class='add'>+				nvmem-cell-names = "mac-address";</div><div class='add'>+				fsl,stop-mode = &lt;&amp;gpr 0x10 3&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='add'>+</div><div class='add'>+			eqos: ethernet@30bf0000 {</div><div class='add'>+				compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a";</div><div class='add'>+				reg = &lt;0x30bf0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				interrupt-names = "macirq", "eth_wake_irq";</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MP_CLK_ENET_QOS_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_QOS_ENET_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_ENET_QOS_TIMER&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_ENET_QOS&gt;;</div><div class='add'>+				clock-names = "stmmaceth", "pclk", "ptp_ref", "tx";</div><div class='add'>+				assigned-clocks = &lt;&amp;clk IMX8MP_CLK_ENET_AXI&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX8MP_CLK_ENET_QOS_TIMER&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX8MP_CLK_ENET_QOS&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL1_266M&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MP_SYS_PLL2_100M&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MP_SYS_PLL2_125M&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;0&gt;, &lt;100000000&gt;, &lt;125000000&gt;;</div><div class='add'>+				nvmem-cells = &lt;&amp;eth_mac2&gt;;</div><div class='add'>+				nvmem-cell-names = "mac-address";</div><div class='add'>+				intf_mode = &lt;&amp;gpr 0x4&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aips5: bus@30df0000 {</div><div class='add'>+			compatible = "fsl,imx8mp-aipstz";</div><div class='add'>+			reg = &lt;0x30df0000 0x10000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;pgc_audio&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			#access-controller-cells = &lt;3&gt;;</div><div class='add'>+			ranges = &lt;0x30c00000 0x30c00000 0x400000&gt;;</div><div class='add'>+</div><div class='add'>+			spba-bus@30c00000 {</div><div class='add'>+				compatible = "fsl,spba-bus", "simple-bus";</div><div class='add'>+				reg = &lt;0x30c00000 0x100000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;1&gt;;</div><div class='add'>+				ranges;</div><div class='add'>+</div><div class='add'>+				sai1: sai@30c10000 {</div><div class='add'>+					compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";</div><div class='add'>+					reg = &lt;0x30c10000 0x10000&gt;;</div><div class='add'>+					#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+					clocks = &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_IPG&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MP_CLK_DUMMY&gt;,</div><div class='add'>+						 &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1&gt;,</div><div class='add'>+						 &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2&gt;,</div><div class='add'>+						 &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3&gt;;</div><div class='add'>+					clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";</div><div class='add'>+					dmas = &lt;&amp;sdma2 0 2 0&gt;, &lt;&amp;sdma2 1 2 0&gt;;</div><div class='add'>+					dma-names = "rx", "tx";</div><div class='add'>+					interrupts = &lt;GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				sai2: sai@30c20000 {</div><div class='add'>+					compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";</div><div class='add'>+					reg = &lt;0x30c20000 0x10000&gt;;</div><div class='add'>+					#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+					clocks = &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_IPG&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MP_CLK_DUMMY&gt;,</div><div class='add'>+						 &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1&gt;,</div><div class='add'>+						 &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2&gt;,</div><div class='add'>+						 &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3&gt;;</div><div class='add'>+					clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";</div><div class='add'>+					dmas = &lt;&amp;sdma2 2 2 0&gt;, &lt;&amp;sdma2 3 2 0&gt;;</div><div class='add'>+					dma-names = "rx", "tx";</div><div class='add'>+					interrupts = &lt;GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				sai3: sai@30c30000 {</div><div class='add'>+					compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";</div><div class='add'>+					reg = &lt;0x30c30000 0x10000&gt;;</div><div class='add'>+					#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+					clocks = &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MP_CLK_DUMMY&gt;,</div><div class='add'>+						 &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1&gt;,</div><div class='add'>+						 &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2&gt;,</div><div class='add'>+						 &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3&gt;;</div><div class='add'>+					clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";</div><div class='add'>+					dmas = &lt;&amp;sdma2 4 2 0&gt;, &lt;&amp;sdma2 5 2 0&gt;;</div><div class='add'>+					dma-names = "rx", "tx";</div><div class='add'>+					interrupts = &lt;GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				sai5: sai@30c50000 {</div><div class='add'>+					compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";</div><div class='add'>+					reg = &lt;0x30c50000 0x10000&gt;;</div><div class='add'>+					#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+					clocks = &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_IPG&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MP_CLK_DUMMY&gt;,</div><div class='add'>+						 &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1&gt;,</div><div class='add'>+						 &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2&gt;,</div><div class='add'>+						 &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3&gt;;</div><div class='add'>+					clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";</div><div class='add'>+					dmas = &lt;&amp;sdma2 8 2 0&gt;, &lt;&amp;sdma2 9 2 0&gt;;</div><div class='add'>+					dma-names = "rx", "tx";</div><div class='add'>+					interrupts = &lt;GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				sai6: sai@30c60000 {</div><div class='add'>+					compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";</div><div class='add'>+					reg = &lt;0x30c60000 0x10000&gt;;</div><div class='add'>+					#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+					clocks = &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_IPG&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MP_CLK_DUMMY&gt;,</div><div class='add'>+						 &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1&gt;,</div><div class='add'>+						 &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2&gt;,</div><div class='add'>+						 &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3&gt;;</div><div class='add'>+					clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";</div><div class='add'>+					dmas = &lt;&amp;sdma2 10 2 0&gt;, &lt;&amp;sdma2 11 2 0&gt;;</div><div class='add'>+					dma-names = "rx", "tx";</div><div class='add'>+					interrupts = &lt;GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				sai7: sai@30c80000 {</div><div class='add'>+					compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";</div><div class='add'>+					reg = &lt;0x30c80000 0x10000&gt;;</div><div class='add'>+					#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+					clocks = &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_IPG&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MP_CLK_DUMMY&gt;,</div><div class='add'>+						 &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1&gt;,</div><div class='add'>+						 &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2&gt;,</div><div class='add'>+						 &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3&gt;;</div><div class='add'>+					clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";</div><div class='add'>+					dmas = &lt;&amp;sdma2 12 2 0&gt;, &lt;&amp;sdma2 13 2 0&gt;;</div><div class='add'>+					dma-names = "rx", "tx";</div><div class='add'>+					interrupts = &lt;GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				easrc: easrc@30c90000 {</div><div class='add'>+					compatible = "fsl,imx8mp-easrc", "fsl,imx8mn-easrc";</div><div class='add'>+					reg = &lt;0x30c90000 0x10000&gt;;</div><div class='add'>+					interrupts = &lt;GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					clocks = &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_ASRC_IPG&gt;;</div><div class='add'>+					clock-names = "mem";</div><div class='add'>+					dmas = &lt;&amp;sdma2 16 23 0&gt; , &lt;&amp;sdma2 17 23 0&gt;,</div><div class='add'>+					       &lt;&amp;sdma2 18 23 0&gt; , &lt;&amp;sdma2 19 23 0&gt;,</div><div class='add'>+					       &lt;&amp;sdma2 20 23 0&gt; , &lt;&amp;sdma2 21 23 0&gt;,</div><div class='add'>+					       &lt;&amp;sdma2 22 23 0&gt; , &lt;&amp;sdma2 23 23 0&gt;;</div><div class='add'>+					dma-names = "ctx0_rx", "ctx0_tx",</div><div class='add'>+						    "ctx1_rx", "ctx1_tx",</div><div class='add'>+						    "ctx2_rx", "ctx2_tx",</div><div class='add'>+						    "ctx3_rx", "ctx3_tx";</div><div class='add'>+					firmware-name = "imx/easrc/easrc-imx8mn.bin";</div><div class='add'>+					fsl,asrc-rate = &lt;8000&gt;;</div><div class='add'>+					fsl,asrc-format = &lt;2&gt;;</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				micfil: audio-controller@30ca0000 {</div><div class='add'>+					compatible = "fsl,imx8mp-micfil";</div><div class='add'>+					reg = &lt;0x30ca0000 0x10000&gt;;</div><div class='add'>+					#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+					interrupts = &lt;GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+						     &lt;GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+						     &lt;GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+						     &lt;GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					clocks = &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_PDM_IPG&gt;,</div><div class='add'>+						 &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_PDM_SEL&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MP_AUDIO_PLL1_OUT&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MP_AUDIO_PLL2_OUT&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MP_CLK_EXT3&gt;;</div><div class='add'>+					clock-names = "ipg_clk", "ipg_clk_app",</div><div class='add'>+						      "pll8k", "pll11k", "clkext3";</div><div class='add'>+					dmas = &lt;&amp;sdma2 24 25 0x80000000&gt;;</div><div class='add'>+					dma-names = "rx";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				aud2htx: aud2htx@30cb0000 {</div><div class='add'>+					compatible = "fsl,imx8mp-aud2htx";</div><div class='add'>+					reg = &lt;0x30cb0000 0x10000&gt;;</div><div class='add'>+					interrupts = &lt;GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					clocks = &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_AUD2HTX_IPG&gt;;</div><div class='add'>+					clock-names = "bus";</div><div class='add'>+					dmas = &lt;&amp;sdma2 26 2 0&gt;;</div><div class='add'>+					dma-names = "tx";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xcvr: xcvr@30cc0000 {</div><div class='add'>+					compatible = "fsl,imx8mp-xcvr";</div><div class='add'>+					reg = &lt;0x30cc0000 0x800&gt;,</div><div class='add'>+					      &lt;0x30cc0800 0x400&gt;,</div><div class='add'>+					      &lt;0x30cc0c00 0x080&gt;,</div><div class='add'>+					      &lt;0x30cc0e00 0x080&gt;;</div><div class='add'>+					reg-names = "ram", "regs", "rxfifo",</div><div class='add'>+						    "txfifo";</div><div class='add'>+					interrupts = /* XCVR IRQ 0 */</div><div class='add'>+						     &lt;GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+						     /* XCVR IRQ 1 */</div><div class='add'>+						     &lt;GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+						     /* XCVR PHY - SPDIF wakeup IRQ */</div><div class='add'>+						     &lt;GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					clocks = &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_EARC_IPG&gt;,</div><div class='add'>+						 &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_EARC_PHY&gt;,</div><div class='add'>+						 &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT&gt;,</div><div class='add'>+						 &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT&gt;;</div><div class='add'>+					clock-names = "ipg", "phy", "spba", "pll_ipg";</div><div class='add'>+					dmas = &lt;&amp;sdma2 30 2 0&gt;, &lt;&amp;sdma2 31 2 0&gt;;</div><div class='add'>+					dma-names = "rx", "tx";</div><div class='add'>+					resets = &lt;&amp;audio_blk_ctrl 0&gt;;</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sdma3: dma-controller@30e00000 {</div><div class='add'>+				compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";</div><div class='add'>+				reg = &lt;0x30e00000 0x10000&gt;;</div><div class='add'>+				#dma-cells = &lt;3&gt;;</div><div class='add'>+				clocks = &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_AUDIO_ROOT&gt;;</div><div class='add'>+				clock-names = "ipg", "ahb";</div><div class='add'>+				interrupts = &lt;GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sdma2: dma-controller@30e10000 {</div><div class='add'>+				compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";</div><div class='add'>+				reg = &lt;0x30e10000 0x10000&gt;;</div><div class='add'>+				#dma-cells = &lt;3&gt;;</div><div class='add'>+				clocks = &lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_AUDIO_ROOT&gt;;</div><div class='add'>+				clock-names = "ipg", "ahb";</div><div class='add'>+				interrupts = &lt;GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			audio_blk_ctrl: clock-controller@30e20000 {</div><div class='add'>+				compatible = "fsl,imx8mp-audio-blk-ctrl";</div><div class='add'>+				reg = &lt;0x30e20000 0x10000&gt;;</div><div class='add'>+				#clock-cells = &lt;1&gt;;</div><div class='add'>+				#reset-cells = &lt;1&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MP_CLK_AUDIO_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_SAI1&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_SAI2&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_SAI3&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_SAI5&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_SAI6&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_SAI7&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_AUDIO_AXI_ROOT&gt;;</div><div class='add'>+				clock-names = "ahb",</div><div class='add'>+					      "sai1", "sai2", "sai3",</div><div class='add'>+					      "sai5", "sai6", "sai7", "axi";</div><div class='add'>+				power-domains = &lt;&amp;pgc_audio&gt;;</div><div class='add'>+				assigned-clocks = &lt;&amp;clk IMX8MP_AUDIO_PLL1&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX8MP_AUDIO_PLL2&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;393216000&gt;, &lt;361267200&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		noc: interconnect@32700000 {</div><div class='add'>+			compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc";</div><div class='add'>+			reg = &lt;0x32700000 0x100000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MP_CLK_NOC&gt;;</div><div class='add'>+			#interconnect-cells = &lt;1&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;noc_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+			noc_opp_table: opp-table {</div><div class='add'>+				compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+				opp-200000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;200000000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				/* Nominal drive mode maximum */</div><div class='add'>+				opp-800000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;800000000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				/* Overdrive mode maximum */</div><div class='add'>+				opp-1000000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;1000000000&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aips4: bus@32c00000 {</div><div class='add'>+			compatible = "fsl,aips-bus", "simple-bus";</div><div class='add'>+			reg = &lt;0x32c00000 0x400000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			isi_0: isi@32e00000 {</div><div class='add'>+				compatible = "fsl,imx8mp-isi";</div><div class='add'>+				reg = &lt;0x32e00000 0x4000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MP_CLK_MEDIA_AXI_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_MEDIA_APB_ROOT&gt;;</div><div class='add'>+				clock-names = "axi", "apb";</div><div class='add'>+				fsl,blk-ctrl = &lt;&amp;media_blk_ctrl&gt;;</div><div class='add'>+				power-domains = &lt;&amp;media_blk_ctrl IMX8MP_MEDIABLK_PD_ISI&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						isi_in_0: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mipi_csi_0_out&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						isi_in_1: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mipi_csi_1_out&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			isp_0: isp@32e10000 {</div><div class='add'>+				compatible = "fsl,imx8mp-isp";</div><div class='add'>+				reg = &lt;0x32e10000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MP_CLK_MEDIA_ISP_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_MEDIA_AXI_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_MEDIA_APB_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT&gt;;</div><div class='add'>+				clock-names = "isp", "aclk", "hclk", "pclk";</div><div class='add'>+				power-domains = &lt;&amp;media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP&gt;,</div><div class='add'>+						&lt;&amp;media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1&gt;;</div><div class='add'>+				power-domain-names = "isp", "csi2";</div><div class='add'>+				fsl,blk-ctrl = &lt;&amp;media_blk_ctrl 0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			isp_1: isp@32e20000 {</div><div class='add'>+				compatible = "fsl,imx8mp-isp";</div><div class='add'>+				reg = &lt;0x32e20000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MP_CLK_MEDIA_ISP_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_MEDIA_AXI_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_MEDIA_APB_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT&gt;;</div><div class='add'>+				clock-names = "isp", "aclk", "hclk", "pclk";</div><div class='add'>+				power-domains = &lt;&amp;media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP&gt;,</div><div class='add'>+						&lt;&amp;media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2&gt;;</div><div class='add'>+				power-domain-names = "isp", "csi2";</div><div class='add'>+				fsl,blk-ctrl = &lt;&amp;media_blk_ctrl 1&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			dewarp: dwe@32e30000 {</div><div class='add'>+				compatible = "nxp,imx8mp-dw100";</div><div class='add'>+				reg = &lt;0x32e30000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MP_CLK_MEDIA_AXI_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_MEDIA_APB_ROOT&gt;;</div><div class='add'>+				clock-names = "axi", "ahb";</div><div class='add'>+				power-domains = &lt;&amp;media_blk_ctrl IMX8MP_MEDIABLK_PD_DWE&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mipi_csi_0: csi@32e40000 {</div><div class='add'>+				compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2";</div><div class='add'>+				reg = &lt;0x32e40000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clock-frequency = &lt;250000000&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MP_CLK_MEDIA_APB_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_MEDIA_AXI_ROOT&gt;;</div><div class='add'>+				clock-names = "pclk", "wrap", "phy", "axi";</div><div class='add'>+				assigned-clocks = &lt;&amp;clk IMX8MP_CLK_MEDIA_CAM1_PIX&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL2_250M&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MP_CLK_24M&gt;;</div><div class='add'>+				power-domains = &lt;&amp;media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1&gt;;</div><div class='add'>+				fsl,num-channels = &lt;3&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						mipi_csi_0_out: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;isi_in_0&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mipi_csi_1: csi@32e50000 {</div><div class='add'>+				compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2";</div><div class='add'>+				reg = &lt;0x32e50000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clock-frequency = &lt;250000000&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MP_CLK_MEDIA_APB_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_MEDIA_AXI_ROOT&gt;;</div><div class='add'>+				clock-names = "pclk", "wrap", "phy", "axi";</div><div class='add'>+				assigned-clocks = &lt;&amp;clk IMX8MP_CLK_MEDIA_CAM2_PIX&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL2_250M&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MP_CLK_24M&gt;;</div><div class='add'>+				power-domains = &lt;&amp;media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2&gt;;</div><div class='add'>+				fsl,num-channels = &lt;3&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						mipi_csi_1_out: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;isi_in_1&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mipi_dsi: dsi@32e60000 {</div><div class='add'>+				compatible = "fsl,imx8mp-mipi-dsim";</div><div class='add'>+				reg = &lt;0x32e60000 0x400&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MP_CLK_MEDIA_APB_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF&gt;;</div><div class='add'>+				clock-names = "bus_clk", "sclk_mipi";</div><div class='add'>+				assigned-clocks = &lt;&amp;clk IMX8MP_CLK_MEDIA_APB&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL1_800M&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MP_CLK_24M&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;200000000&gt;, &lt;24000000&gt;;</div><div class='add'>+				samsung,pll-clock-frequency = &lt;24000000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				power-domains = &lt;&amp;media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_DSI_1&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						dsim_from_lcdif1: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;lcdif1_to_dsim&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						mipi_dsi_out: endpoint {</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lcdif1: display-controller@32e80000 {</div><div class='add'>+				compatible = "fsl,imx8mp-lcdif";</div><div class='add'>+				reg = &lt;0x32e80000 0x10000&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_MEDIA_APB_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_MEDIA_AXI_ROOT&gt;;</div><div class='add'>+				clock-names = "pix", "axi", "disp_axi";</div><div class='add'>+				interrupts = &lt;GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				power-domains = &lt;&amp;media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_1&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				port {</div><div class='add'>+					lcdif1_to_dsim: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dsim_from_lcdif1&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lcdif2: display-controller@32e90000 {</div><div class='add'>+				compatible = "fsl,imx8mp-lcdif";</div><div class='add'>+				reg = &lt;0x32e90000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_MEDIA_APB_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_MEDIA_AXI_ROOT&gt;;</div><div class='add'>+				clock-names = "pix", "axi", "disp_axi";</div><div class='add'>+				power-domains = &lt;&amp;media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_2&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				port {</div><div class='add'>+					lcdif2_to_ldb: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ldb_from_lcdif2&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			media_blk_ctrl: blk-ctrl@32ec0000 {</div><div class='add'>+				compatible = "fsl,imx8mp-media-blk-ctrl",</div><div class='add'>+					     "syscon";</div><div class='add'>+				reg = &lt;0x32ec0000 0x10000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;1&gt;;</div><div class='add'>+				power-domains = &lt;&amp;pgc_mediamix&gt;,</div><div class='add'>+						&lt;&amp;pgc_mipi_phy1&gt;,</div><div class='add'>+						&lt;&amp;pgc_mipi_phy1&gt;,</div><div class='add'>+						&lt;&amp;pgc_mediamix&gt;,</div><div class='add'>+						&lt;&amp;pgc_mediamix&gt;,</div><div class='add'>+						&lt;&amp;pgc_mipi_phy2&gt;,</div><div class='add'>+						&lt;&amp;pgc_mediamix&gt;,</div><div class='add'>+						&lt;&amp;pgc_ispdwp&gt;,</div><div class='add'>+						&lt;&amp;pgc_ispdwp&gt;,</div><div class='add'>+						&lt;&amp;pgc_mipi_phy2&gt;;</div><div class='add'>+				power-domain-names = "bus", "mipi-dsi1", "mipi-csi1",</div><div class='add'>+						     "lcdif1", "isi", "mipi-csi2",</div><div class='add'>+						     "lcdif2", "isp", "dwe",</div><div class='add'>+						     "mipi-dsi2";</div><div class='add'>+				interconnects =</div><div class='add'>+					&lt;&amp;noc IMX8MP_ICM_LCDIF_RD &amp;noc IMX8MP_ICN_MEDIA&gt;,</div><div class='add'>+					&lt;&amp;noc IMX8MP_ICM_LCDIF_WR &amp;noc IMX8MP_ICN_MEDIA&gt;,</div><div class='add'>+					&lt;&amp;noc IMX8MP_ICM_ISI0 &amp;noc IMX8MP_ICN_MEDIA&gt;,</div><div class='add'>+					&lt;&amp;noc IMX8MP_ICM_ISI1 &amp;noc IMX8MP_ICN_MEDIA&gt;,</div><div class='add'>+					&lt;&amp;noc IMX8MP_ICM_ISI2 &amp;noc IMX8MP_ICN_MEDIA&gt;,</div><div class='add'>+					&lt;&amp;noc IMX8MP_ICM_ISP0 &amp;noc IMX8MP_ICN_MEDIA&gt;,</div><div class='add'>+					&lt;&amp;noc IMX8MP_ICM_ISP1 &amp;noc IMX8MP_ICN_MEDIA&gt;,</div><div class='add'>+					&lt;&amp;noc IMX8MP_ICM_DWE &amp;noc IMX8MP_ICN_MEDIA&gt;;</div><div class='add'>+				interconnect-names = "lcdif-rd", "lcdif-wr", "isi0",</div><div class='add'>+						     "isi1", "isi2", "isp0", "isp1",</div><div class='add'>+						     "dwe";</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MP_CLK_MEDIA_APB_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_MEDIA_AXI_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_MEDIA_ISP_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT&gt;;</div><div class='add'>+				clock-names = "apb", "axi", "cam1", "cam2",</div><div class='add'>+					      "disp1", "disp2", "isp", "phy";</div><div class='add'>+</div><div class='add'>+				/*</div><div class='add'>+				 * The ISP maximum frequency is 400MHz in normal mode</div><div class='add'>+				 * and 500MHz in overdrive mode. The 400MHz operating</div><div class='add'>+				 * point hasn't been successfully tested yet, so set</div><div class='add'>+				 * IMX8MP_CLK_MEDIA_ISP to 500MHz for the time being.</div><div class='add'>+				 */</div><div class='add'>+				assigned-clocks = &lt;&amp;clk IMX8MP_CLK_MEDIA_AXI&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX8MP_CLK_MEDIA_APB&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX8MP_CLK_MEDIA_DISP1_PIX&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX8MP_CLK_MEDIA_DISP2_PIX&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX8MP_CLK_MEDIA_ISP&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX8MP_VIDEO_PLL1&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL2_1000M&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MP_SYS_PLL1_800M&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MP_VIDEO_PLL1_OUT&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MP_VIDEO_PLL1_OUT&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MP_SYS_PLL2_500M&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;500000000&gt;, &lt;200000000&gt;,</div><div class='add'>+						       &lt;0&gt;, &lt;0&gt;, &lt;500000000&gt;,</div><div class='add'>+						       &lt;1039500000&gt;;</div><div class='add'>+				#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				lvds_bridge: bridge@5c {</div><div class='add'>+					compatible = "fsl,imx8mp-ldb";</div><div class='add'>+					reg = &lt;0x5c 0x4&gt;, &lt;0x128 0x4&gt;;</div><div class='add'>+					reg-names = "ldb", "lvds";</div><div class='add'>+					clocks = &lt;&amp;clk IMX8MP_CLK_MEDIA_LDB_ROOT&gt;;</div><div class='add'>+					clock-names = "ldb";</div><div class='add'>+					assigned-clocks = &lt;&amp;clk IMX8MP_CLK_MEDIA_LDB&gt;;</div><div class='add'>+					assigned-clock-parents = &lt;&amp;clk IMX8MP_VIDEO_PLL1_OUT&gt;;</div><div class='add'>+					status = "disabled";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							ldb_from_lcdif2: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;lcdif2_to_ldb&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							ldb_lvds_ch0: endpoint {</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@2 {</div><div class='add'>+							reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+							ldb_lvds_ch1: endpoint {</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pcie_phy: pcie-phy@32f00000 {</div><div class='add'>+				compatible = "fsl,imx8mp-pcie-phy";</div><div class='add'>+				reg = &lt;0x32f00000 0x10000&gt;;</div><div class='add'>+				resets = &lt;&amp;src IMX8MP_RESET_PCIEPHY&gt;,</div><div class='add'>+					 &lt;&amp;src IMX8MP_RESET_PCIEPHY_PERST&gt;;</div><div class='add'>+				reset-names = "pciephy", "perst";</div><div class='add'>+				power-domains = &lt;&amp;hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE_PHY&gt;;</div><div class='add'>+				#phy-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			hsio_blk_ctrl: blk-ctrl@32f10000 {</div><div class='add'>+				compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";</div><div class='add'>+				reg = &lt;0x32f10000 0x24&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MP_CLK_USB_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_PCIE_ROOT&gt;;</div><div class='add'>+				clock-names = "usb", "pcie";</div><div class='add'>+				power-domains = &lt;&amp;pgc_hsiomix&gt;, &lt;&amp;pgc_hsiomix&gt;,</div><div class='add'>+						&lt;&amp;pgc_usb1_phy&gt;, &lt;&amp;pgc_usb2_phy&gt;,</div><div class='add'>+						&lt;&amp;pgc_hsiomix&gt;, &lt;&amp;pgc_pcie_phy&gt;;</div><div class='add'>+				power-domain-names = "bus", "usb", "usb-phy1",</div><div class='add'>+						     "usb-phy2", "pcie", "pcie-phy";</div><div class='add'>+				interconnects = &lt;&amp;noc IMX8MP_ICM_NOC_PCIE &amp;noc IMX8MP_ICN_HSIO&gt;,</div><div class='add'>+						&lt;&amp;noc IMX8MP_ICM_USB1 &amp;noc IMX8MP_ICN_HSIO&gt;,</div><div class='add'>+						&lt;&amp;noc IMX8MP_ICM_USB2 &amp;noc IMX8MP_ICN_HSIO&gt;,</div><div class='add'>+						&lt;&amp;noc IMX8MP_ICM_PCIE &amp;noc IMX8MP_ICN_HSIO&gt;;</div><div class='add'>+				interconnect-names = "noc-pcie", "usb1", "usb2", "pcie";</div><div class='add'>+				#power-domain-cells = &lt;1&gt;;</div><div class='add'>+				#clock-cells = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			hdmi_blk_ctrl: blk-ctrl@32fc0000 {</div><div class='add'>+				compatible = "fsl,imx8mp-hdmi-blk-ctrl", "syscon";</div><div class='add'>+				reg = &lt;0x32fc0000 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MP_CLK_HDMI_APB&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_HDMI_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_HDMI_REF_266M&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_HDMI_24M&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_HDMI_FDCC_TST&gt;;</div><div class='add'>+				clock-names = "apb", "axi", "ref_266m", "ref_24m", "fdcc";</div><div class='add'>+				power-domains = &lt;&amp;pgc_hdmimix&gt;, &lt;&amp;pgc_hdmimix&gt;,</div><div class='add'>+						&lt;&amp;pgc_hdmimix&gt;, &lt;&amp;pgc_hdmimix&gt;,</div><div class='add'>+						&lt;&amp;pgc_hdmimix&gt;, &lt;&amp;pgc_hdmimix&gt;,</div><div class='add'>+						&lt;&amp;pgc_hdmimix&gt;, &lt;&amp;pgc_hdmi_phy&gt;,</div><div class='add'>+						&lt;&amp;pgc_hdmimix&gt;, &lt;&amp;pgc_hdmimix&gt;;</div><div class='add'>+				power-domain-names = "bus", "irqsteer", "lcdif",</div><div class='add'>+						     "pai", "pvi", "trng",</div><div class='add'>+						     "hdmi-tx", "hdmi-tx-phy",</div><div class='add'>+						     "hdcp", "hrv";</div><div class='add'>+				interconnects = &lt;&amp;noc IMX8MP_ICM_HRV &amp;noc IMX8MP_ICN_HDMI&gt;,</div><div class='add'>+						&lt;&amp;noc IMX8MP_ICM_LCDIF_HDMI &amp;noc IMX8MP_ICN_HDMI&gt;,</div><div class='add'>+						&lt;&amp;noc IMX8MP_ICM_HDCP &amp;noc IMX8MP_ICN_HDMI&gt;;</div><div class='add'>+				interconnect-names = "hrv", "lcdif-hdmi", "hdcp";</div><div class='add'>+				#power-domain-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			irqsteer_hdmi: interrupt-controller@32fc2000 {</div><div class='add'>+				compatible = "fsl,imx8mp-irqsteer", "fsl,imx-irqsteer";</div><div class='add'>+				reg = &lt;0x32fc2000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;1&gt;;</div><div class='add'>+				fsl,channel = &lt;1&gt;;</div><div class='add'>+				fsl,num-irqs = &lt;64&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MP_CLK_HDMI_APB&gt;;</div><div class='add'>+				clock-names = "ipg";</div><div class='add'>+				power-domains = &lt;&amp;hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_IRQSTEER&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			hdmi_pvi: display-bridge@32fc4000 {</div><div class='add'>+				compatible = "fsl,imx8mp-hdmi-pvi";</div><div class='add'>+				reg = &lt;0x32fc4000 0x800&gt;;</div><div class='add'>+				interrupt-parent = &lt;&amp;irqsteer_hdmi&gt;;</div><div class='add'>+				interrupts = &lt;12&gt;;</div><div class='add'>+				power-domains = &lt;&amp;hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PVI&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+						pvi_from_lcdif3: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;lcdif3_to_pvi&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+						pvi_to_hdmi_tx: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;hdmi_tx_from_pvi&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			hdmi_pai: audio-bridge@32fc4800 {</div><div class='add'>+				compatible = "fsl,imx8mp-hdmi-pai";</div><div class='add'>+				reg = &lt;0x32fc4800 0x800&gt;;</div><div class='add'>+				interrupt-parent = &lt;&amp;irqsteer_hdmi&gt;;</div><div class='add'>+				interrupts = &lt;14&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MP_CLK_HDMI_APB&gt;;</div><div class='add'>+				clock-names = "apb";</div><div class='add'>+				power-domains = &lt;&amp;hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PAI&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				port {</div><div class='add'>+					pai_to_hdmi_tx: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;hdmi_tx_from_pai&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lcdif3: display-controller@32fc6000 {</div><div class='add'>+				compatible = "fsl,imx8mp-lcdif";</div><div class='add'>+				reg = &lt;0x32fc6000 0x1000&gt;;</div><div class='add'>+				interrupt-parent = &lt;&amp;irqsteer_hdmi&gt;;</div><div class='add'>+				interrupts = &lt;8&gt;;</div><div class='add'>+				clocks = &lt;&amp;hdmi_tx_phy&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_HDMI_APB&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_HDMI_ROOT&gt;;</div><div class='add'>+				clock-names = "pix", "axi", "disp_axi";</div><div class='add'>+				power-domains = &lt;&amp;hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_LCDIF&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				port {</div><div class='add'>+					lcdif3_to_pvi: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;pvi_from_lcdif3&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			hdmi_tx: hdmi@32fd8000 {</div><div class='add'>+				compatible = "fsl,imx8mp-hdmi-tx";</div><div class='add'>+				reg = &lt;0x32fd8000 0x7eff&gt;;</div><div class='add'>+				interrupt-parent = &lt;&amp;irqsteer_hdmi&gt;;</div><div class='add'>+				interrupts = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MP_CLK_HDMI_APB&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_HDMI_REF_266M&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_32K&gt;,</div><div class='add'>+					 &lt;&amp;hdmi_tx_phy&gt;;</div><div class='add'>+				clock-names = "iahb", "isfr", "cec", "pix";</div><div class='add'>+				assigned-clocks = &lt;&amp;clk IMX8MP_CLK_HDMI_REF_266M&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL1_266M&gt;;</div><div class='add'>+				power-domains = &lt;&amp;hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX&gt;;</div><div class='add'>+				reg-io-width = &lt;1&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						hdmi_tx_from_pvi: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;pvi_to_hdmi_tx&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+						/* Point endpoint to the HDMI connector */</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@2 {</div><div class='add'>+						reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+						hdmi_tx_from_pai: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;pai_to_hdmi_tx&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			hdmi_tx_phy: phy@32fdff00 {</div><div class='add'>+				compatible = "fsl,imx8mp-hdmi-phy";</div><div class='add'>+				reg = &lt;0x32fdff00 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MP_CLK_HDMI_APB&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_HDMI_24M&gt;;</div><div class='add'>+				clock-names = "apb", "ref";</div><div class='add'>+				assigned-clocks = &lt;&amp;clk IMX8MP_CLK_HDMI_24M&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;clk IMX8MP_CLK_24M&gt;;</div><div class='add'>+				power-domains = &lt;&amp;hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX_PHY&gt;;</div><div class='add'>+				#clock-cells = &lt;0&gt;;</div><div class='add'>+				#phy-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie0: pcie: pcie@33800000 {</div><div class='add'>+			compatible = "fsl,imx8mp-pcie";</div><div class='add'>+			reg = &lt;0x33800000 0x400000&gt;, &lt;0x1ff00000 0x80000&gt;;</div><div class='add'>+			reg-names = "dbi", "config";</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MP_CLK_HSIO_ROOT&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MP_CLK_HSIO_AXI&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MP_CLK_PCIE_ROOT&gt;;</div><div class='add'>+			clock-names = "pcie", "pcie_bus", "pcie_aux";</div><div class='add'>+			assigned-clocks = &lt;&amp;clk IMX8MP_CLK_PCIE_AUX&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;10000000&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL2_50M&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			bus-range = &lt;0x00 0xff&gt;;</div><div class='add'>+			ranges = &lt;0x81000000 0 0x00000000 0x1ff80000 0 0x00010000&gt;, /* downstream I/O 64KB */</div><div class='add'>+				 &lt;0x82000000 0 0x18000000 0x18000000 0 0x07f00000&gt;; /* non-prefetchable memory */</div><div class='add'>+			num-lanes = &lt;1&gt;;</div><div class='add'>+			num-viewport = &lt;4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "msi";</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0x7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			fsl,max-link-speed = &lt;3&gt;;</div><div class='add'>+			linux,pci-domain = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE&gt;;</div><div class='add'>+			resets = &lt;&amp;src IMX8MP_RESET_PCIE_CTRL_APPS_EN&gt;,</div><div class='add'>+				 &lt;&amp;src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF&gt;;</div><div class='add'>+			reset-names = "apps", "turnoff";</div><div class='add'>+			phys = &lt;&amp;pcie_phy&gt;;</div><div class='add'>+			phy-names = "pcie-phy";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie0_ep: pcie_ep: pcie-ep@33800000 {</div><div class='add'>+			compatible = "fsl,imx8mp-pcie-ep";</div><div class='add'>+			reg = &lt;0x33800000 0x100000&gt;,</div><div class='add'>+			      &lt;0x18000000 0x8000000&gt;,</div><div class='add'>+			      &lt;0x33900000 0x100000&gt;,</div><div class='add'>+			      &lt;0x33b00000 0x100000&gt;;</div><div class='add'>+			reg-names = "dbi", "addr_space", "dbi2", "atu";</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MP_CLK_HSIO_ROOT&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MP_CLK_HSIO_AXI&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MP_CLK_PCIE_ROOT&gt;;</div><div class='add'>+			clock-names = "pcie", "pcie_bus", "pcie_aux";</div><div class='add'>+			assigned-clocks = &lt;&amp;clk IMX8MP_CLK_PCIE_AUX&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;10000000&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL2_50M&gt;;</div><div class='add'>+			num-lanes = &lt;1&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH&gt;; /* eDMA */</div><div class='add'>+			interrupt-names = "dma";</div><div class='add'>+			fsl,max-link-speed = &lt;3&gt;;</div><div class='add'>+			power-domains = &lt;&amp;hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE&gt;;</div><div class='add'>+			resets = &lt;&amp;src IMX8MP_RESET_PCIE_CTRL_APPS_EN&gt;,</div><div class='add'>+				 &lt;&amp;src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF&gt;;</div><div class='add'>+			reset-names = "apps", "turnoff";</div><div class='add'>+			phys = &lt;&amp;pcie_phy&gt;;</div><div class='add'>+			phy-names = "pcie-phy";</div><div class='add'>+			num-ib-windows = &lt;4&gt;;</div><div class='add'>+			num-ob-windows = &lt;4&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu3d: gpu@38000000 {</div><div class='add'>+			compatible = "vivante,gc";</div><div class='add'>+			reg = &lt;0x38000000 0x8000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MP_CLK_GPU3D_ROOT&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MP_CLK_GPU3D_SHADER_CORE&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MP_CLK_GPU_ROOT&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MP_CLK_GPU_AHB&gt;;</div><div class='add'>+			clock-names = "core", "shader", "bus", "reg";</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			assigned-clocks = &lt;&amp;clk IMX8MP_CLK_GPU3D_CORE&gt;,</div><div class='add'>+					  &lt;&amp;clk IMX8MP_CLK_GPU3D_SHADER_CORE&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL2_1000M&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MP_SYS_PLL2_1000M&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;1000000000&gt;, &lt;1000000000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;pgc_gpu3d&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu2d: gpu@38008000 {</div><div class='add'>+			compatible = "vivante,gc";</div><div class='add'>+			reg = &lt;0x38008000 0x8000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MP_CLK_GPU2D_ROOT&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MP_CLK_GPU_ROOT&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MP_CLK_GPU_AHB&gt;;</div><div class='add'>+			clock-names = "core", "bus", "reg";</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			assigned-clocks = &lt;&amp;clk IMX8MP_CLK_GPU2D_CORE&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL2_1000M&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;1000000000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;pgc_gpu2d&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vpu_g1: video-codec@38300000 {</div><div class='add'>+			compatible = "nxp,imx8mm-vpu-g1";</div><div class='add'>+			reg = &lt;0x38300000 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MP_CLK_VPU_G1_ROOT&gt;;</div><div class='add'>+			assigned-clocks = &lt;&amp;clk IMX8MP_CLK_VPU_G1&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL1_800M&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;800000000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vpu_g2: video-codec@38310000 {</div><div class='add'>+			compatible = "nxp,imx8mq-vpu-g2";</div><div class='add'>+			reg = &lt;0x38310000 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MP_CLK_VPU_G2_ROOT&gt;;</div><div class='add'>+			assigned-clocks = &lt;&amp;clk IMX8MP_CLK_VPU_G2&gt;, &lt;&amp;clk IMX8MP_VPU_PLL_OUT&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;clk IMX8MP_VPU_PLL_OUT&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;700000000&gt;, &lt;700000000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vpumix_blk_ctrl: blk-ctrl@38330000 {</div><div class='add'>+			compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon";</div><div class='add'>+			reg = &lt;0x38330000 0x100&gt;;</div><div class='add'>+			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+			power-domains = &lt;&amp;pgc_vpumix&gt;, &lt;&amp;pgc_vpu_g1&gt;,</div><div class='add'>+					&lt;&amp;pgc_vpu_g2&gt;, &lt;&amp;pgc_vpu_vc8000e&gt;;</div><div class='add'>+			power-domain-names = "bus", "g1", "g2", "vc8000e";</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MP_CLK_VPU_G1_ROOT&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MP_CLK_VPU_G2_ROOT&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MP_CLK_VPU_VC8KE_ROOT&gt;;</div><div class='add'>+			clock-names = "g1", "g2", "vc8000e";</div><div class='add'>+			assigned-clocks = &lt;&amp;clk IMX8MP_CLK_VPU_BUS&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL1_800M&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;800000000&gt;;</div><div class='add'>+			interconnects = &lt;&amp;noc IMX8MP_ICM_VPU_G1 &amp;noc IMX8MP_ICN_VIDEO&gt;,</div><div class='add'>+					&lt;&amp;noc IMX8MP_ICM_VPU_G2 &amp;noc IMX8MP_ICN_VIDEO&gt;,</div><div class='add'>+					&lt;&amp;noc IMX8MP_ICM_VPU_H1 &amp;noc IMX8MP_ICN_VIDEO&gt;;</div><div class='add'>+			interconnect-names = "g1", "g2", "vc8000e";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		npu: npu@38500000 {</div><div class='add'>+			compatible = "vivante,gc";</div><div class='add'>+			reg = &lt;0x38500000 0x200000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MP_CLK_NPU_ROOT&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MP_CLK_NPU_ROOT&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MP_CLK_ML_AXI&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MP_CLK_ML_AHB&gt;;</div><div class='add'>+			clock-names = "core", "shader", "bus", "reg";</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			power-domains = &lt;&amp;pgc_mlmix&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		gic: interrupt-controller@38800000 {</div><div class='ctx'> 			compatible = "arm,gic-v3";</div><div class='ctx'> 			reg = &lt;0x38800000 0x10000&gt;,</div><div class='ctx'> 			      &lt;0x38880000 0xc0000&gt;;</div><div class='add'>+			#address-cells = &lt;0&gt;;</div><div class='ctx'> 			#interrupt-cells = &lt;3&gt;;</div><div class='ctx'> 			interrupt-controller;</div><div class='ctx'> 			interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			interrupt-parent = &lt;&amp;gic&gt;;</div><div class='ctx'> 		};</div><div class='add'>+</div><div class='add'>+		edacmc: memory-controller@3d400000 {</div><div class='add'>+			compatible = "snps,ddrc-3.80a";</div><div class='add'>+			reg = &lt;0x3d400000 0x400000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ddr-pmu@3d800000 {</div><div class='add'>+			compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu";</div><div class='add'>+			reg = &lt;0x3d800000 0x400000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb3_phy0: usb-phy@381f0040 {</div><div class='add'>+			compatible = "fsl,imx8mp-usb-phy";</div><div class='add'>+			reg = &lt;0x381f0040 0x40&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MP_CLK_USB_PHY_ROOT&gt;;</div><div class='add'>+			clock-names = "phy";</div><div class='add'>+			assigned-clocks = &lt;&amp;clk IMX8MP_CLK_USB_PHY_REF&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;clk IMX8MP_CLK_24M&gt;;</div><div class='add'>+			power-domains = &lt;&amp;hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb3_0: usb@32f10100 {</div><div class='add'>+			compatible = "fsl,imx8mp-dwc3";</div><div class='add'>+			reg = &lt;0x32f10100 0x8&gt;,</div><div class='add'>+			      &lt;0x381f0000 0x20&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MP_CLK_HSIO_ROOT&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MP_CLK_USB_SUSP&gt;;</div><div class='add'>+			clock-names = "hsio", "suspend";</div><div class='add'>+			interrupts = &lt;GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			power-domains = &lt;&amp;hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			dma-ranges = &lt;0x40000000 0x40000000 0xc0000000&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			usb_dwc3_0: usb@38100000 {</div><div class='add'>+				compatible = "snps,dwc3";</div><div class='add'>+				reg = &lt;0x38100000 0x10000&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MP_CLK_USB_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_USB_CORE_REF&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_USB_SUSP&gt;;</div><div class='add'>+				clock-names = "bus_early", "ref", "suspend";</div><div class='add'>+				interrupts = &lt;GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				phys = &lt;&amp;usb3_phy0&gt;, &lt;&amp;usb3_phy0&gt;;</div><div class='add'>+				phy-names = "usb2-phy", "usb3-phy";</div><div class='add'>+				snps,gfladj-refclk-lpm-sel-quirk;</div><div class='add'>+				snps,parkmode-disable-ss-quirk;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb3_phy1: usb-phy@382f0040 {</div><div class='add'>+			compatible = "fsl,imx8mp-usb-phy";</div><div class='add'>+			reg = &lt;0x382f0040 0x40&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MP_CLK_USB_PHY_ROOT&gt;;</div><div class='add'>+			clock-names = "phy";</div><div class='add'>+			assigned-clocks = &lt;&amp;clk IMX8MP_CLK_USB_PHY_REF&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;clk IMX8MP_CLK_24M&gt;;</div><div class='add'>+			power-domains = &lt;&amp;hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb3_1: usb@32f10108 {</div><div class='add'>+			compatible = "fsl,imx8mp-dwc3";</div><div class='add'>+			reg = &lt;0x32f10108 0x8&gt;,</div><div class='add'>+			      &lt;0x382f0000 0x20&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MP_CLK_HSIO_ROOT&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MP_CLK_USB_SUSP&gt;;</div><div class='add'>+			clock-names = "hsio", "suspend";</div><div class='add'>+			interrupts = &lt;GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			power-domains = &lt;&amp;hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			dma-ranges = &lt;0x40000000 0x40000000 0xc0000000&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			usb_dwc3_1: usb@38200000 {</div><div class='add'>+				compatible = "snps,dwc3";</div><div class='add'>+				reg = &lt;0x38200000 0x10000&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MP_CLK_USB_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_USB_CORE_REF&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MP_CLK_USB_SUSP&gt;;</div><div class='add'>+				clock-names = "bus_early", "ref", "suspend";</div><div class='add'>+				interrupts = &lt;GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				phys = &lt;&amp;usb3_phy1&gt;, &lt;&amp;usb3_phy1&gt;;</div><div class='add'>+				phy-names = "usb2-phy", "usb3-phy";</div><div class='add'>+				snps,gfladj-refclk-lpm-sel-quirk;</div><div class='add'>+				snps,parkmode-disable-ss-quirk;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dsp: dsp@3b6e8000 {</div><div class='add'>+			compatible = "fsl,imx8mp-hifi4";</div><div class='add'>+			reg = &lt;0x3b6e8000 0x88000&gt;;</div><div class='add'>+			clocks = &lt;&amp;audio_blk_ctrl  IMX8MP_CLK_AUDIOMIX_DSP_ROOT&gt;,</div><div class='add'>+				&lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG&gt;,</div><div class='add'>+				&lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSP_ROOT&gt;,</div><div class='add'>+				&lt;&amp;audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT&gt;;</div><div class='add'>+			clock-names = "ipg", "ocram", "core", "debug";</div><div class='add'>+			power-domains = &lt;&amp;pgc_audio&gt;;</div><div class='add'>+			mbox-names = "tx", "rx", "rxdb";</div><div class='add'>+			mboxes = &lt;&amp;mu2 0 0&gt;, &lt;&amp;mu2 1 0&gt;, &lt;&amp;mu2 3 0&gt;;</div><div class='add'>+			firmware-name = "imx/dsp/hifi4.bin";</div><div class='add'>+			resets = &lt;&amp;audio_blk_ctrl IMX8MP_AUDIOMIX_DSP_RUNSTALL&gt;;</div><div class='add'>+			reset-names = "runstall";</div><div class='add'>+			access-controllers = &lt;&amp;aips5</div><div class='add'>+				IMX8MP_AIPSTZ_HIFI4</div><div class='add'>+				IMX8MP_AIPSTZ_MASTER</div><div class='add'>+				(IMX8MP_AIPSTZ_MPL | IMX8MP_AIPSTZ_MTW | IMX8MP_AIPSTZ_MTR)</div><div class='add'>+			&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts<br/>index c9241abf0df3..d48f901487d4 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mq-evk.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mq-evk.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mq-evk.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mq-evk.dts</a></div><div class='hunk'>@@ -27,6 +27,17 @@</div><div class='ctx'> 		clock-frequency = &lt;100000000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	reg_pcie1: regulator-pcie {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pcie1_reg&gt;;</div><div class='add'>+		regulator-name = "MPCIE_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio5 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	reg_usdhc2_vmmc: regulator-vsd-3v3 {</div><div class='ctx'> 		pinctrl-names = "default";</div><div class='ctx'> 		pinctrl-0 = &lt;&amp;pinctrl_reg_usdhc2&gt;;</div><div class='hunk'>@@ -35,6 +46,7 @@</div><div class='ctx'> 		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='ctx'> 		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='ctx'> 		gpio = &lt;&amp;gpio2 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		off-on-delay-us = &lt;20000&gt;;</div><div class='ctx'> 		enable-active-high;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -57,6 +69,12 @@</div><div class='ctx'> 		gpios = &lt;&amp;gpio1 12 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 		pinctrl-names = "default";</div><div class='ctx'> 		pinctrl-0 = &lt;&amp;pinctrl_ir&gt;;</div><div class='add'>+		linux,autosuspend-period = &lt;125&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	audio_codec_bt_sco: audio-codec-bt-sco {</div><div class='add'>+		compatible = "linux,bt-sco";</div><div class='add'>+		#sound-dai-cells = &lt;1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	wm8524: audio-codec {</div><div class='hunk'>@@ -65,12 +83,32 @@</div><div class='ctx'> 		wlf,mute-gpios = &lt;&amp;gpio1 8 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	sound-bt-sco {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,name = "bt-sco-audio";</div><div class='add'>+		simple-audio-card,format = "dsp_a";</div><div class='add'>+		simple-audio-card,bitclock-inversion;</div><div class='add'>+		simple-audio-card,frame-master = &lt;&amp;btcpu&gt;;</div><div class='add'>+		simple-audio-card,bitclock-master = &lt;&amp;btcpu&gt;;</div><div class='add'>+</div><div class='add'>+		btcpu: simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;sai3&gt;;</div><div class='add'>+			dai-tdm-slot-num = &lt;2&gt;;</div><div class='add'>+			dai-tdm-slot-width = &lt;16&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		simple-audio-card,codec {</div><div class='add'>+			sound-dai = &lt;&amp;audio_codec_bt_sco 1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	sound-wm8524 {</div><div class='ctx'> 		compatible = "simple-audio-card";</div><div class='ctx'> 		simple-audio-card,name = "wm8524-audio";</div><div class='ctx'> 		simple-audio-card,format = "i2s";</div><div class='ctx'> 		simple-audio-card,frame-master = &lt;&amp;cpudai&gt;;</div><div class='ctx'> 		simple-audio-card,bitclock-master = &lt;&amp;cpudai&gt;;</div><div class='add'>+		simple-audio-card,mclk-fs = &lt;256&gt;;</div><div class='ctx'> 		simple-audio-card,widgets =</div><div class='ctx'> 			"Line", "Left Line Out Jack",</div><div class='ctx'> 			"Line", "Right Line Out Jack";</div><div class='hunk'>@@ -80,13 +118,42 @@</div><div class='ctx'> </div><div class='ctx'> 		cpudai: simple-audio-card,cpu {</div><div class='ctx'> 			sound-dai = &lt;&amp;sai2&gt;;</div><div class='add'>+			system-clock-direction-out;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		link_codec: simple-audio-card,codec {</div><div class='ctx'> 			sound-dai = &lt;&amp;wm8524&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk IMX8MQ_CLK_SAI2_ROOT&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	spdif_out: spdif-out {</div><div class='add'>+		compatible = "linux,spdif-dit";</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spdif_in: spdif-in {</div><div class='add'>+		compatible = "linux,spdif-dir";</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-spdif {</div><div class='add'>+		compatible = "fsl,imx-audio-spdif";</div><div class='add'>+		model = "imx-spdif";</div><div class='add'>+		audio-cpu = &lt;&amp;spdif1&gt;;</div><div class='add'>+		audio-codec = &lt;&amp;spdif_out&gt;, &lt;&amp;spdif_in&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdmi_arc_in: hdmi-arc-in {</div><div class='add'>+		compatible = "linux,spdif-dir";</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-hdmi-arc {</div><div class='add'>+		compatible = "fsl,imx-audio-spdif";</div><div class='add'>+		model = "imx-hdmi-arc";</div><div class='add'>+		audio-cpu = &lt;&amp;spdif2&gt;;</div><div class='add'>+		audio-codec = &lt;&amp;hdmi_arc_in&gt;;</div><div class='add'>+	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;A53_0 {</div><div class='hunk'>@@ -107,38 +174,41 @@</div><div class='ctx'> </div><div class='ctx'> &amp;ddrc {</div><div class='ctx'> 	operating-points-v2 = &lt;&amp;ddrc_opp_table&gt;;</div><div class='add'>+	status = "okay";</div><div class='ctx'> </div><div class='ctx'> 	ddrc_opp_table: opp-table {</div><div class='ctx'> 		compatible = "operating-points-v2";</div><div class='ctx'> </div><div class='del'>-		opp-25M {</div><div class='add'>+		opp-25000000 {</div><div class='ctx'> 			opp-hz = /bits/ 64 &lt;25000000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		opp-100M {</div><div class='add'>+		opp-100000000 {</div><div class='ctx'> 			opp-hz = /bits/ 64 &lt;100000000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		/*</div><div class='ctx'> 		 * On imx8mq B0 PLL can't be bypassed so low bus is 166M</div><div class='ctx'> 		 */</div><div class='del'>-		opp-166M {</div><div class='add'>+		opp-166000000 {</div><div class='ctx'> 			opp-hz = /bits/ 64 &lt;166935483&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		opp-800M {</div><div class='add'>+		opp-800000000 {</div><div class='ctx'> 			opp-hz = /bits/ 64 &lt;800000000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;dphy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;fec1 {</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pinctrl_fec1&gt;;</div><div class='ctx'> 	phy-mode = "rgmii-id";</div><div class='ctx'> 	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='del'>-	phy-reset-gpios = &lt;&amp;gpio1 9  GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-	phy-reset-duration = &lt;10&gt;;</div><div class='ctx'> 	fsl,magic-packet;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='hunk'>@@ -149,6 +219,13 @@</div><div class='ctx'> 		ethphy0: ethernet-phy@0 {</div><div class='ctx'> 			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='ctx'> 			reg = &lt;0&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio1 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;10000&gt;;</div><div class='add'>+			qca,disable-smarteee;</div><div class='add'>+			vddio-supply = &lt;&amp;vddh&gt;;</div><div class='add'>+</div><div class='add'>+			vddh: vddh-regulator {</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='hunk'>@@ -157,7 +234,7 @@</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pinctrl_wifi_reset&gt;;</div><div class='ctx'> </div><div class='del'>-	wl-reg-on {</div><div class='add'>+	wl-reg-on-hog {</div><div class='ctx'> 		gpio-hog;</div><div class='ctx'> 		gpios = &lt;29 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 		output-high;</div><div class='hunk'>@@ -255,22 +332,96 @@</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;lcdif {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_dsi {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	panel@0 {</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_mipi_dsi&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		compatible = "raydium,rm67191";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio5 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		dsi-lanes = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			panel_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;mipi_dsi_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			mipi_dsi_out: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;panel_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;pcie0 {</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pinctrl_pcie0&gt;;</div><div class='ctx'> 	reset-gpio = &lt;&amp;gpio5 28 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 	clocks = &lt;&amp;clk IMX8MQ_CLK_PCIE1_ROOT&gt;,</div><div class='del'>-		 &lt;&amp;clk IMX8MQ_CLK_PCIE1_AUX&gt;,</div><div class='add'>+		 &lt;&amp;pcie0_refclk&gt;,</div><div class='ctx'> 		 &lt;&amp;clk IMX8MQ_CLK_PCIE1_PHY&gt;,</div><div class='del'>-		 &lt;&amp;pcie0_refclk&gt;;</div><div class='del'>-	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";</div><div class='add'>+		 &lt;&amp;clk IMX8MQ_CLK_PCIE1_AUX&gt;;</div><div class='add'>+	vph-supply = &lt;&amp;vgen5_reg&gt;;</div><div class='add'>+	supports-clkreq;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;pcie0_ep {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie0&gt;;</div><div class='add'>+	clocks = &lt;&amp;clk IMX8MQ_CLK_PCIE1_ROOT&gt;,</div><div class='add'>+		 &lt;&amp;pcie0_refclk&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX8MQ_CLK_PCIE1_PHY&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX8MQ_CLK_PCIE1_AUX&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie1&gt;;</div><div class='add'>+	reset-gpio = &lt;&amp;gpio5 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	clocks = &lt;&amp;clk IMX8MQ_CLK_PCIE2_ROOT&gt;,</div><div class='add'>+		 &lt;&amp;pcie0_refclk&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX8MQ_CLK_PCIE2_PHY&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX8MQ_CLK_PCIE2_AUX&gt;;</div><div class='add'>+	vpcie-supply = &lt;&amp;reg_pcie1&gt;;</div><div class='add'>+	vpcie3v3aux-supply = &lt;&amp;reg_pcie1&gt;;</div><div class='add'>+	vph-supply = &lt;&amp;vgen5_reg&gt;;</div><div class='add'>+	supports-clkreq;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie1_ep {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie1&gt;;</div><div class='add'>+	clocks = &lt;&amp;clk IMX8MQ_CLK_PCIE2_ROOT&gt;,</div><div class='add'>+		 &lt;&amp;pcie0_refclk&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX8MQ_CLK_PCIE2_PHY&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX8MQ_CLK_PCIE2_AUX&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;pgc_gpu {</div><div class='ctx'> 	power-supply = &lt;&amp;sw1a_reg&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;pgc_vpu {</div><div class='add'>+	power-supply = &lt;&amp;sw1c_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;qspi0 {</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pinctrl_qspi&gt;;</div><div class='hunk'>@@ -282,6 +433,8 @@</div><div class='ctx'> 		#size-cells = &lt;1&gt;;</div><div class='ctx'> 		compatible = "micron,n25q256a", "jedec,spi-nor";</div><div class='ctx'> 		spi-max-frequency = &lt;29000000&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;1&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -291,6 +444,21 @@</div><div class='ctx'> 	assigned-clocks = &lt;&amp;clk IMX8MQ_AUDIO_PLL1_BYPASS&gt;, &lt;&amp;clk IMX8MQ_CLK_SAI2&gt;;</div><div class='ctx'> 	assigned-clock-parents = &lt;&amp;clk IMX8MQ_AUDIO_PLL1&gt;, &lt;&amp;clk IMX8MQ_AUDIO_PLL1_OUT&gt;;</div><div class='ctx'> 	assigned-clock-rates = &lt;0&gt;, &lt;24576000&gt;;</div><div class='add'>+	clocks = &lt;&amp;clk IMX8MQ_CLK_SAI2_IPG&gt;, &lt;&amp;clk IMX8MQ_CLK_DUMMY&gt;,</div><div class='add'>+		&lt;&amp;clk IMX8MQ_CLK_SAI2_ROOT&gt;, &lt;&amp;clk IMX8MQ_CLK_DUMMY&gt;,</div><div class='add'>+		&lt;&amp;clk IMX8MQ_CLK_DUMMY&gt;, &lt;&amp;clk IMX8MQ_AUDIO_PLL1_OUT&gt;,</div><div class='add'>+		&lt;&amp;clk IMX8MQ_AUDIO_PLL2_OUT&gt;;</div><div class='add'>+	clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai3 {</div><div class='add'>+	#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai3&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MQ_CLK_SAI3&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MQ_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;24576000&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -298,6 +466,22 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;spdif1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_spdif1&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MQ_CLK_SPDIF1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MQ_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;24576000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spdif2 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MQ_CLK_SPDIF2&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MQ_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;24576000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;uart1 {</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='hunk'>@@ -332,9 +516,9 @@</div><div class='ctx'> 	assigned-clocks = &lt;&amp;clk IMX8MQ_CLK_USDHC2&gt;;</div><div class='ctx'> 	assigned-clock-rates = &lt;200000000&gt;;</div><div class='ctx'> 	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='del'>-	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;;</div><div class='del'>-	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;;</div><div class='del'>-	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='ctx'> 	cd-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='hunk'>@@ -352,7 +536,6 @@</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13		0x19</div><div class='ctx'> 		&gt;;</div><div class='del'>-</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	pinctrl_fec1: fec1grp {</div><div class='hunk'>@@ -388,6 +571,12 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	pinctrl_mipi_dsi: mipidsigrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6		0x16</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	pinctrl_pcie0: pcie0grp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B		0x76</div><div class='hunk'>@@ -395,6 +584,19 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	pinctrl_pcie1: pcie1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B		0x76</div><div class='add'>+			MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12		0x16</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie1_reg: pcie1reggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10		0x16</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	pinctrl_qspi: qspigrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK	0x82</div><div class='hunk'>@@ -403,11 +605,10 @@</div><div class='ctx'> 			MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1	0x82</div><div class='ctx'> 			MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2	0x82</div><div class='ctx'> 			MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3	0x82</div><div class='del'>-</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pinctrl_reg_usdhc2: regusdhc2grpgpio {</div><div class='add'>+	pinctrl_reg_usdhc2: regusdhc2gpiogrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19		0x41</div><div class='ctx'> 		&gt;;</div><div class='hunk'>@@ -423,6 +624,22 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	pinctrl_sai3: sai3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6</div><div class='add'>+			MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6</div><div class='add'>+			MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6</div><div class='add'>+			MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0     0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_spdif1: spdif1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT	0xd6</div><div class='add'>+			MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN		0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	pinctrl_uart1: uart1grp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x49</div><div class='hunk'>@@ -481,6 +698,12 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12		0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	pinctrl_usdhc2: usdhc2grp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x83</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mq-hummingboard-pulse.dts b/arch/arm64/boot/dts/freescale/imx8mq-hummingboard-pulse.dts<br/>index bfd91c1ed6a5..e92b5d5a66b5 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mq-hummingboard-pulse.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mq-hummingboard-pulse.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mq-hummingboard-pulse.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mq-hummingboard-pulse.dts</a></div><div class='hunk'>@@ -42,7 +42,7 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='ctx'> 	typec_ptn5100: usb-typec@50 {</div><div class='del'>-		compatible = "nxp,ptn5110";</div><div class='add'>+		compatible = "nxp,ptn5110", "tcpci";</div><div class='ctx'> 		reg = &lt;0x50&gt;;</div><div class='ctx'> 		pinctrl-names = "default";</div><div class='ctx'> 		pinctrl-0 = &lt;&amp;pinctrl_typec&gt;;</div><div class='hunk'>@@ -214,13 +214,13 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pinctrl_usdhc2_gpio: usdhc2grpgpio {</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12	0x41</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pinctrl_usdhc2_vmmc: usdhc2vmmcgpio {</div><div class='add'>+	pinctrl_usdhc2_vmmc: usdhc2vmmcgpiogrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13	0x41</div><div class='ctx'> 		&gt;;</div><div class='hunk'>@@ -238,7 +238,7 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x8d</div><div class='ctx'> 			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xcd</div><div class='hunk'>@@ -250,7 +250,7 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x9f</div><div class='ctx'> 			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xdf</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts<br/>new file mode 100644<br/>index 000000000000..d8cf1f27c3ec<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts</a></div><div class='hunk'>@@ -0,0 +1,611 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Device Tree File for the Kontron pitx-imx8m board.</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) 2021 Heiko Thiery &lt;heiko.thiery@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mq.dtsi"</div><div class='add'>+#include &lt;dt-bindings/net/ti-dp83867.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Kontron pITX-imx8m";</div><div class='add'>+	compatible = "kontron,pitx-imx8m", "fsl,imx8mq";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		i2c0 = &amp;i2c1;</div><div class='add'>+		i2c1 = &amp;i2c2;</div><div class='add'>+		i2c2 = &amp;i2c3;</div><div class='add'>+		mmc0 = &amp;usdhc1;</div><div class='add'>+		mmc1 = &amp;usdhc2;</div><div class='add'>+		serial0 = &amp;uart1;</div><div class='add'>+		serial1 = &amp;uart2;</div><div class='add'>+		serial2 = &amp;uart3;</div><div class='add'>+		spi0 = &amp;qspi0;</div><div class='add'>+		spi1 = &amp;ecspi2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial2:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_refclk: pcie0-clock {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;100000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie1_refclk: pcie1-clock {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;100000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usdhc2&gt;;</div><div class='add'>+		regulator-name = "V_3V3_SD";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio2 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		off-on-delay-us = &lt;20000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi2 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi2 &amp;pinctrl_ecspi2_cs&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 13 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	tpm@0 {</div><div class='add'>+		compatible = "infineon,slb9670", "tcg,tpm_tis-spi";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;43000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec1&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	fsl,magic-packet;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@0 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_2_25_NS&gt;;</div><div class='add'>+			ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_2_75_NS&gt;;</div><div class='add'>+			ti,fifo-depth = &lt;DP83867_PHYCR_FIFO_DEPTH_4_B_NIB&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio1 11 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;10&gt;;</div><div class='add'>+			reset-deassert-us = &lt;280&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pmic@8 {</div><div class='add'>+		compatible = "fsl,pfuze100";</div><div class='add'>+		fsl,pfuze-support-disable-sw;</div><div class='add'>+		reg = &lt;0x8&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			sw1a_reg: sw1ab {</div><div class='add'>+				regulator-name = "V_0V9_GPU";</div><div class='add'>+				regulator-min-microvolt = &lt;825000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sw1c_reg: sw1c {</div><div class='add'>+				regulator-name = "V_0V9_VPU";</div><div class='add'>+				regulator-min-microvolt = &lt;825000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sw2_reg: sw2 {</div><div class='add'>+				regulator-name = "V_1V1_NVCC_DRAM";</div><div class='add'>+				regulator-min-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sw3a_reg: sw3ab {</div><div class='add'>+				regulator-name = "V_1V0_DRAM";</div><div class='add'>+				regulator-min-microvolt = &lt;825000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sw4_reg: sw4 {</div><div class='add'>+				regulator-name = "V_1V8_S0";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			swbst_reg: swbst {</div><div class='add'>+				regulator-name = "NC";</div><div class='add'>+				regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;5150000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			snvs_reg: vsnvs {</div><div class='add'>+				regulator-name = "V_0V9_SNVS";</div><div class='add'>+				regulator-min-microvolt = &lt;1000000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3000000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vref_reg: vrefddr {</div><div class='add'>+				regulator-name = "V_0V55_VREF_DDR";</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vgen1_reg: vgen1 {</div><div class='add'>+				regulator-name = "V_1V5_CSI";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1550000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vgen2_reg: vgen2 {</div><div class='add'>+				regulator-name = "V_0V9_PHY";</div><div class='add'>+				regulator-min-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;975000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vgen3_reg: vgen3 {</div><div class='add'>+				regulator-name = "V_1V8_PHY";</div><div class='add'>+				regulator-min-microvolt = &lt;1675000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1975000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vgen4_reg: vgen4 {</div><div class='add'>+				regulator-name = "V_1V8_VDDA";</div><div class='add'>+				regulator-min-microvolt = &lt;1625000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1875000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vgen5_reg: vgen5 {</div><div class='add'>+				regulator-name = "V_3V3_PHY";</div><div class='add'>+				regulator-min-microvolt = &lt;3075000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3625000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vgen6_reg: vgen6 {</div><div class='add'>+				regulator-name = "V_2V8_CAM";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fan-controller@1b {</div><div class='add'>+		compatible = "maxim,max6650";</div><div class='add'>+		reg = &lt;0x1b&gt;;</div><div class='add'>+		maxim,fan-microvolt = &lt;5000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rtc@32 {</div><div class='add'>+		compatible = "microcrystal,rv8803";</div><div class='add'>+		reg = &lt;0x32&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sensor@4b {</div><div class='add'>+		compatible = "national,lm75b";</div><div class='add'>+		reg = &lt;0x4b&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@51 {</div><div class='add'>+		compatible = "atmel,24c32";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* M.2 B-key slot */</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie0&gt;;</div><div class='add'>+	reset-gpio = &lt;&amp;gpio1 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	clocks = &lt;&amp;clk IMX8MQ_CLK_PCIE1_ROOT&gt;,</div><div class='add'>+		 &lt;&amp;pcie0_refclk&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX8MQ_CLK_PCIE1_PHY&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX8MQ_CLK_PCIE1_AUX&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Intel Ethernet Controller I210/I211 */</div><div class='add'>+&amp;pcie1 {</div><div class='add'>+	clocks = &lt;&amp;clk IMX8MQ_CLK_PCIE2_ROOT&gt;,</div><div class='add'>+		 &lt;&amp;pcie1_refclk&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX8MQ_CLK_PCIE2_PHY&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX8MQ_CLK_PCIE2_AUX&gt;;</div><div class='add'>+	fsl,max-link-speed = &lt;1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pgc_gpu {</div><div class='add'>+	power-supply = &lt;&amp;sw1a_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pgc_vpu {</div><div class='add'>+	power-supply = &lt;&amp;sw1c_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qspi0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_qspi&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;1&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+		m25p,fast-read;</div><div class='add'>+		spi-max-frequency = &lt;50000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;snvs_pwrkey {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MQ_CLK_UART1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MQ_SYS1_PLL_80M&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MQ_CLK_UART2&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MQ_SYS1_PLL_80M&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MQ_CLK_UART3&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MQ_SYS1_PLL_80M&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usb0&gt;;</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	hnp-disable;</div><div class='add'>+	srp-disable;</div><div class='add'>+	adp-disable;</div><div class='add'>+	maximum-speed = "high-speed";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_1 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MQ_CLK_USDHC1&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1_200mhz&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;sw4_reg&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	no-sd;</div><div class='add'>+	no-sdio;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MQ_CLK_USDHC2&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;200000000&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	wp-gpios = &lt;&amp;gpio2 20 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hog&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl_hog: hoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2		0x19 /* TPM Reset */</div><div class='add'>+			MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4		0x19 /* USB2 Hub Reset */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio: gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5			0x19 /* GPIO0 */</div><div class='add'>+			MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15		0x19 /* GPIO1 */</div><div class='add'>+			MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17		0x19 /* GPIO2 */</div><div class='add'>+			MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18		0x19 /* GPIO3 */</div><div class='add'>+			MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16		0x19 /* GPIO4 */</div><div class='add'>+			MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10		0x19 /* GPIO5 */</div><div class='add'>+			MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11		0x19 /* GPIO6 */</div><div class='add'>+			MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12		0x19 /* GPIO7 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie0: pcie0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x16 /* PCIE_PERST */</div><div class='add'>+			MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29		0x16 /* W_DISABLE */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usdhc2: regusdhc2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19		0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec1: fec1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC			0x3</div><div class='add'>+			MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO		0x23</div><div class='add'>+			MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f</div><div class='add'>+			MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f</div><div class='add'>+			MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f</div><div class='add'>+			MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f</div><div class='add'>+			MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91</div><div class='add'>+			MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91</div><div class='add'>+			MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91</div><div class='add'>+			MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91</div><div class='add'>+			MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f</div><div class='add'>+			MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91</div><div class='add'>+			MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91</div><div class='add'>+			MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f</div><div class='add'>+			MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x16</div><div class='add'>+			MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15		0x16</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL			0x4000007f</div><div class='add'>+			MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA			0x4000007f</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL			0x4000007f</div><div class='add'>+			MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA			0x4000007f</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL			0x4000007f</div><div class='add'>+			MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA			0x4000007f</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_qspi: qspigrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK		0x82</div><div class='add'>+			MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B		0x82</div><div class='add'>+			MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0		0x82</div><div class='add'>+			MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1		0x82</div><div class='add'>+			MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2		0x82</div><div class='add'>+			MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3		0x82</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi2: ecspi2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI		0x19</div><div class='add'>+			MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO		0x19</div><div class='add'>+			MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK		0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi2_cs: ecspi2csgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13		0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x49</div><div class='add'>+			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x49</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX		0x49</div><div class='add'>+			MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX		0x49</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: uart3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX		0x49</div><div class='add'>+			MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX		0x49</div><div class='add'>+			MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B		0x49</div><div class='add'>+			MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B	0x49</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83</div><div class='add'>+			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3</div><div class='add'>+			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x83</div><div class='add'>+			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1-100grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x8d</div><div class='add'>+			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xcd</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xcd</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xcd</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xcd</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xcd</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xcd</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xcd</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xcd</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xcd</div><div class='add'>+			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x8d</div><div class='add'>+			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1-200grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x9f</div><div class='add'>+			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xdf</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xdf</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xdf</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xdf</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xdf</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xdf</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xdf</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xdf</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xdf</div><div class='add'>+			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x9f</div><div class='add'>+			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12		0x41</div><div class='add'>+			MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20			0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x83</div><div class='add'>+			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc3</div><div class='add'>+			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3</div><div class='add'>+			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3</div><div class='add'>+			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3</div><div class='add'>+			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3</div><div class='add'>+			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x8d</div><div class='add'>+			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xcd</div><div class='add'>+			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xcd</div><div class='add'>+			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xcd</div><div class='add'>+			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xcd</div><div class='add'>+			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xcd</div><div class='add'>+			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x9f</div><div class='add'>+			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xdf</div><div class='add'>+			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xdf</div><div class='add'>+			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xdf</div><div class='add'>+			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xdf</div><div class='add'>+			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xdf</div><div class='add'>+			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usb0: usb0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_GPIO1_IO12_USB1_OTG_PWR		0x19</div><div class='add'>+			MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC		0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0xc6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts<br/>index 10eca94194be..d9f203c79519 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts</a></div><div class='hunk'>@@ -6,6 +6,8 @@</div><div class='ctx'> /dts-v1/;</div><div class='ctx'> </div><div class='ctx'> #include "dt-bindings/input/input.h"</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='ctx'> #include "dt-bindings/pwm/pwm.h"</div><div class='ctx'> #include "dt-bindings/usb/pd.h"</div><div class='ctx'> #include "imx8mq.dtsi"</div><div class='hunk'>@@ -17,7 +19,7 @@</div><div class='ctx'> 	backlight_dsi: backlight-dsi {</div><div class='ctx'> 		compatible = "pwm-backlight";</div><div class='ctx'> 		/* 200 Hz for the PAM2841 */</div><div class='del'>-		pwms = &lt;&amp;pwm1 0 5000000&gt;;</div><div class='add'>+		pwms = &lt;&amp;pwm1 0 5000000 0&gt;;</div><div class='ctx'> 		brightness-levels = &lt;0 100&gt;;</div><div class='ctx'> 		num-interpolated-steps = &lt;100&gt;;</div><div class='ctx'> 		/* Default brightness level (index into the array defined by */</div><div class='hunk'>@@ -35,46 +37,38 @@</div><div class='ctx'> 		pinctrl-names = "default";</div><div class='ctx'> 		pinctrl-0 = &lt;&amp;pinctrl_gpio_keys&gt;;</div><div class='ctx'> </div><div class='del'>-		btn1 {</div><div class='add'>+		button-1 {</div><div class='ctx'> 			label = "VOL_UP";</div><div class='ctx'> 			gpios = &lt;&amp;gpio4 21 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 			wakeup-source;</div><div class='ctx'> 			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		btn2 {</div><div class='add'>+		button-2 {</div><div class='ctx'> 			label = "VOL_DOWN";</div><div class='ctx'> 			gpios = &lt;&amp;gpio4 22 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 			wakeup-source;</div><div class='ctx'> 			linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		hp-det {</div><div class='del'>-			label = "HP_DET";</div><div class='del'>-			gpios = &lt;&amp;gpio3 20 GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-			wakeup-source;</div><div class='del'>-			linux,code = &lt;KEY_HP&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		wwan-wake {</div><div class='add'>+		button-3 {</div><div class='ctx'> 			label = "WWAN_WAKE";</div><div class='ctx'> 			gpios = &lt;&amp;gpio3 8 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 			interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='del'>-			interrupts = &lt;8 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			interrupts = &lt;8 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 			wakeup-source;</div><div class='ctx'> 			linux,code = &lt;KEY_PHONE&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	leds {</div><div class='del'>-		compatible = "gpio-leds";</div><div class='del'>-		pinctrl-names = "default";</div><div class='del'>-		pinctrl-0 = &lt;&amp;pinctrl_gpio_leds&gt;;</div><div class='add'>+		compatible = "pwm-leds";</div><div class='ctx'> </div><div class='del'>-		led1 {</div><div class='del'>-			label = "LED 1";</div><div class='del'>-			gpios = &lt;&amp;gpio1 13 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			default-state = "off";</div><div class='add'>+		led-1 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			max-brightness = &lt;248&gt;;</div><div class='add'>+			pwms = &lt;&amp;pwm2 0 50000 0&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -145,38 +139,40 @@</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {</div><div class='del'>-		compatible = "regulator-fixed";</div><div class='del'>-		pinctrl-names = "default";</div><div class='del'>-		pinctrl-0 = &lt;&amp;pinctrl_usdhc2_pwr&gt;;</div><div class='del'>-		regulator-name = "VSD_3V3";</div><div class='del'>-		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='del'>-		gpio = &lt;&amp;gpio2 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-		enable-active-high;</div><div class='del'>-		regulator-always-on;</div><div class='del'>-	};</div><div class='del'>-</div><div class='ctx'> 	wwan_codec: sound-wwan-codec {</div><div class='ctx'> 		compatible = "option,gtm601";</div><div class='ctx'> 		#sound-dai-cells = &lt;0&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	mic_mux: mic-mux {</div><div class='add'>+		compatible = "simple-audio-mux";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_micsel&gt;;</div><div class='add'>+		mux-gpios = &lt;&amp;gpio5 5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		sound-name-prefix = "Mic Mux";</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	sound {</div><div class='ctx'> 		compatible = "simple-audio-card";</div><div class='del'>-		simple-audio-card,name = "sgtl5000";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_hpdet&gt;;</div><div class='add'>+		simple-audio-card,aux-devs = &lt;&amp;speaker_amp&gt;, &lt;&amp;mic_mux&gt;;</div><div class='add'>+		simple-audio-card,name = "Librem 5 Devkit";</div><div class='ctx'> 		simple-audio-card,format = "i2s";</div><div class='ctx'> 		simple-audio-card,widgets =</div><div class='del'>-			"Microphone", "Microphone Jack",</div><div class='del'>-			"Headphone", "Headphone Jack",</div><div class='del'>-			"Speaker", "Speaker Ext",</div><div class='del'>-			"Line", "Line In Jack";</div><div class='add'>+			"Microphone", "Builtin Microphone",</div><div class='add'>+			"Microphone", "Headset Microphone",</div><div class='add'>+			"Headphone", "Headphones",</div><div class='add'>+			"Speaker", "Builtin Speaker";</div><div class='ctx'> 		simple-audio-card,routing =</div><div class='del'>-			"MIC_IN", "Microphone Jack",</div><div class='del'>-			"Microphone Jack", "Mic Bias",</div><div class='del'>-			"LINE_IN", "Line In Jack",</div><div class='del'>-			"Headphone Jack", "HP_OUT",</div><div class='del'>-			"Speaker Ext", "LINE_OUT";</div><div class='add'>+			"MIC_IN", "Mic Mux OUT",</div><div class='add'>+			"Mic Mux IN1", "Headset Microphone",</div><div class='add'>+			"Mic Mux IN2", "Builtin Microphone",</div><div class='add'>+			"Mic Mux OUT", "Mic Bias",</div><div class='add'>+			"Headphones", "HP_OUT",</div><div class='add'>+			"Builtin Speaker", "Speaker Amp OUTR",</div><div class='add'>+			"Speaker Amp INR", "LINE_OUT";</div><div class='add'>+		simple-audio-card,hp-det-gpios = &lt;&amp;gpio3 20 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> </div><div class='ctx'> 		simple-audio-card,cpu {</div><div class='ctx'> 			sound-dai = &lt;&amp;sai2&gt;;</div><div class='hunk'>@@ -206,6 +202,15 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	speaker_amp: speaker-amp {</div><div class='add'>+		compatible = "simple-audio-amplifier";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_spkamp&gt;;</div><div class='add'>+		VCC-supply = &lt;&amp;reg_3v3_p&gt;;</div><div class='add'>+		sound-name-prefix = "Speaker Amp";</div><div class='add'>+		enable-gpios = &lt;&amp;gpio5 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	vibrator {</div><div class='ctx'> 		compatible = "gpio-vibrator";</div><div class='ctx'> 		pinctrl-names = "default";</div><div class='hunk'>@@ -225,6 +230,13 @@</div><div class='ctx'> 		enable-active-high;</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	wifi_pwr_seq: pwrseq {</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usdhc2_rst&gt;;</div><div class='add'>+		compatible = "mmc-pwrseq-simple";</div><div class='add'>+		reset-gpios = &lt;&amp;gpio2 19 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;A53_0 {</div><div class='hunk'>@@ -243,11 +255,6 @@</div><div class='ctx'> 	cpu-supply = &lt;&amp;buck2_reg&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;clk {</div><div class='del'>-	assigned-clocks = &lt;&amp;clk IMX8MQ_AUDIO_PLL1&gt;, &lt;&amp;clk IMX8MQ_AUDIO_PLL2&gt;;</div><div class='del'>-	assigned-clock-rates = &lt;786432000&gt;, &lt;722534400&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> &amp;dphy {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='hunk'>@@ -285,10 +292,10 @@</div><div class='ctx'> 		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='ctx'> 		clocks = &lt;&amp;pmic_osc&gt;;</div><div class='ctx'> 		clock-names = "osc";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='ctx'> 		clock-output-names = "pmic_clk";</div><div class='ctx'> 		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='del'>-		interrupts = &lt;3 GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-		interrupt-names = "irq";</div><div class='add'>+		interrupts = &lt;3 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 		rohm,reset-snvs-powered;</div><div class='ctx'> </div><div class='ctx'> 		regulators {</div><div class='hunk'>@@ -297,6 +304,7 @@</div><div class='ctx'> 				regulator-min-microvolt = &lt;700000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='ctx'> 				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='ctx'> 				regulator-ramp-delay = &lt;1250&gt;;</div><div class='ctx'> 				rohm,dvs-run-voltage = &lt;900000&gt;;</div><div class='ctx'> 				rohm,dvs-idle-voltage = &lt;850000&gt;;</div><div class='hunk'>@@ -311,6 +319,7 @@</div><div class='ctx'> 				regulator-ramp-delay = &lt;1250&gt;;</div><div class='ctx'> 				rohm,dvs-run-voltage = &lt;1000000&gt;;</div><div class='ctx'> 				rohm,dvs-idle-voltage = &lt;900000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			buck3_reg: BUCK3 {</div><div class='hunk'>@@ -318,7 +327,7 @@</div><div class='ctx'> 				regulator-min-microvolt = &lt;700000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='ctx'> 				regulator-boot-on;</div><div class='del'>-				rohm,dvs-run-voltage = &lt;1000000&gt;;</div><div class='add'>+				rohm,dvs-run-voltage = &lt;900000&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			buck4_reg: BUCK4 {</div><div class='hunk'>@@ -333,6 +342,7 @@</div><div class='ctx'> 				regulator-min-microvolt = &lt;700000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='ctx'> 				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			buck6_reg: BUCK6 {</div><div class='hunk'>@@ -340,6 +350,7 @@</div><div class='ctx'> 				regulator-min-microvolt = &lt;3000000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='ctx'> 				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			buck7_reg: BUCK7 {</div><div class='hunk'>@@ -347,6 +358,7 @@</div><div class='ctx'> 				regulator-min-microvolt = &lt;1605000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;1995000&gt;;</div><div class='ctx'> 				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			buck8_reg: BUCK8 {</div><div class='hunk'>@@ -354,6 +366,7 @@</div><div class='ctx'> 				regulator-min-microvolt = &lt;800000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;1400000&gt;;</div><div class='ctx'> 				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			ldo1_reg: LDO1 {</div><div class='hunk'>@@ -379,6 +392,7 @@</div><div class='ctx'> 				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='ctx'> 				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			ldo4_reg: LDO4 {</div><div class='hunk'>@@ -386,12 +400,14 @@</div><div class='ctx'> 				regulator-min-microvolt = &lt;900000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			ldo5_reg: LDO5 {</div><div class='ctx'> 				regulator-name = "ldo5";</div><div class='ctx'> 				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			ldo6_reg: LDO6 {</div><div class='hunk'>@@ -399,6 +415,7 @@</div><div class='ctx'> 				regulator-min-microvolt = &lt;900000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			ldo7_reg: LDO7 {</div><div class='hunk'>@@ -406,12 +423,13 @@</div><div class='ctx'> 				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='ctx'> 				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	typec_ptn5100: usb_typec@52 {</div><div class='del'>-		compatible = "nxp,ptn5110";</div><div class='add'>+	typec_ptn5100: usb-typec@52 {</div><div class='add'>+		compatible = "nxp,ptn5110", "tcpci";</div><div class='ctx'> 		reg = &lt;0x52&gt;;</div><div class='ctx'> 		pinctrl-names = "default";</div><div class='ctx'> 		pinctrl-0 = &lt;&amp;pinctrl_typec&gt;;</div><div class='hunk'>@@ -539,9 +557,9 @@</div><div class='ctx'> 		reg = &lt;0x6a&gt;;</div><div class='ctx'> 		vdd-supply = &lt;&amp;reg_3v3_p&gt;;</div><div class='ctx'> 		vddio-supply = &lt;&amp;reg_3v3_p&gt;;</div><div class='del'>-		mount-matrix =  "1",  "0",  "0",</div><div class='del'>-				"0",  "1",  "0",</div><div class='del'>-				"0",  "0", "-1";</div><div class='add'>+		mount-matrix = "1",  "0",  "0",</div><div class='add'>+			       "0",  "1",  "0",</div><div class='add'>+			       "0",  "0", "-1";</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -593,9 +611,9 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pinctrl_gpio_leds: gpioledgrp {</div><div class='add'>+	pinctrl_pwm_led: pwmledgrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='del'>-			MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13	0x16</div><div class='add'>+			MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT	0x16</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -603,7 +621,6 @@</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21	0x16</div><div class='ctx'> 			MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22	0x16</div><div class='del'>-			MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20	0x180  /* HP_DET */</div><div class='ctx'> 			MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8	0x80   /* nWoWWAN */</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='hunk'>@@ -614,6 +631,12 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	pinctrl_hpdet: hpdetgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20	0xC0   /* HP_DET */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	pinctrl_i2c1: i2c1grp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL		0x4000001f</div><div class='hunk'>@@ -634,6 +657,18 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	pinctrl_micsel: micselgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5	0xc6  /* MIC_SEL */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_spkamp: spkampgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3		0x81  /* MUTE */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	pinctrl_pmic: pmicgrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x80  /* PMIC intr */</div><div class='hunk'>@@ -734,7 +769,7 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x8d</div><div class='ctx'> 			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xcd</div><div class='hunk'>@@ -751,7 +786,7 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x9f</div><div class='ctx'> 			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xdf</div><div class='hunk'>@@ -768,13 +803,13 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pinctrl_usdhc2_pwr: usdhc2grppwr {</div><div class='add'>+	pinctrl_usdhc2_rst: usdhc2rstgrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pinctrl_usdhc2_gpio: usdhc2grpgpio {</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20		0x80 /* WIFI_WAKE */</div><div class='ctx'> 		&gt;;</div><div class='hunk'>@@ -791,7 +826,7 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x8d</div><div class='ctx'> 			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xcd</div><div class='hunk'>@@ -802,7 +837,7 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x9f</div><div class='ctx'> 			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xcf</div><div class='hunk'>@@ -834,6 +869,39 @@</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;lcdif {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_dsi {</div><div class='add'>+	status = "okay";</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	panel@0 {</div><div class='add'>+		compatible = "rocktech,jh057n00900";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		backlight = &lt;&amp;backlight_dsi&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio3 13 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		iovcc-supply = &lt;&amp;reg_1v8_p&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_2v8_p&gt;;</div><div class='add'>+		port {</div><div class='add'>+			panel_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;mipi_dsi_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			mipi_dsi_out: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;panel_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;pgc_gpu {</div><div class='ctx'> 	power-supply = &lt;&amp;buck3_reg&gt;;</div><div class='ctx'> };</div><div class='hunk'>@@ -848,10 +916,20 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;pwm2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm_led&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;snvs_pwrkey {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;snvs_rtc {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;sai2 {</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pinctrl_sai2&gt;;</div><div class='hunk'>@@ -901,24 +979,27 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;usb_dwc3_0 {</div><div class='del'>-	#address-cells = &lt;1&gt;;</div><div class='del'>-	#size-cells = &lt;0&gt;;</div><div class='ctx'> 	dr_mode = "otg";</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='del'>-	port@0 {</div><div class='del'>-		reg = &lt;0&gt;;</div><div class='add'>+	ports {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='ctx'> </div><div class='del'>-		typec_hs: endpoint {</div><div class='del'>-			remote-endpoint = &lt;&amp;usb_con_hs&gt;;</div><div class='add'>+		port@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			typec_hs: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;usb_con_hs&gt;;</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='del'>-	};</div><div class='ctx'> </div><div class='del'>-	port@1 {</div><div class='del'>-		reg = &lt;1&gt;;</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='ctx'> </div><div class='del'>-		typec_ss: endpoint {</div><div class='del'>-			remote-endpoint = &lt;&amp;usb_con_ss&gt;;</div><div class='add'>+			typec_ss: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;usb_con_ss&gt;;</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='hunk'>@@ -948,8 +1029,8 @@</div><div class='ctx'> 	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;;</div><div class='ctx'> 	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;;</div><div class='ctx'> 	bus-width = &lt;4&gt;;</div><div class='del'>-	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='del'>-	power-supply = &lt;&amp;wifi_pwr_en&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;wifi_pwr_en&gt;;</div><div class='add'>+	mmc-pwrseq = &lt;&amp;wifi_pwr_seq&gt;;</div><div class='ctx'> 	broken-cd;</div><div class='ctx'> 	disable-wp;</div><div class='ctx'> 	cap-sdio-irq;</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r2.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r2.dts<br/>new file mode 100644<br/>index 000000000000..cf40025111c8<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mq-librem5-r2.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mq-librem5-r2.dts</a></div><div class='hunk'>@@ -0,0 +1,27 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+// Copyright (C) 2020 Purism SPC &lt;kernel@puri.sm&gt;</div><div class='add'>+//</div><div class='add'>+// Librem 5 Chestnut</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mq-librem5.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Purism Librem 5r2";</div><div class='add'>+	compatible = "purism,librem5r2", "purism,librem5", "fsl,imx8mq";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;accel_gyro {</div><div class='add'>+	mount-matrix = "1",  "0",  "0",</div><div class='add'>+		       "0", "-1",  "0",</div><div class='add'>+		       "0",  "0",  "1";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;bq25895 {</div><div class='add'>+	ti,charge-current = &lt;1600000&gt;; /* uA */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;proximity {</div><div class='add'>+	proximity-near-level = &lt;50&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dts<br/>new file mode 100644<br/>index 000000000000..077c5cd2586f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dts</a></div><div class='hunk'>@@ -0,0 +1,16 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+// Copyright (C) 2021 Purism SPC &lt;kernel@puri.sm&gt;</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mq-librem5-r3.dtsi"</div><div class='add'>+</div><div class='add'>+&amp;a53_opp_table {</div><div class='add'>+	opp-1000000000 {</div><div class='add'>+		opp-microvolt = &lt;950000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;buck3_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dtsi<br/>new file mode 100644<br/>index 000000000000..17f86496f8b0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dtsi</a></div><div class='hunk'>@@ -0,0 +1,49 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+// Copyright (C) 2021 Purism SPC &lt;kernel@puri.sm&gt;</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * This file describes hardware that is shared among r3 ("Dogwood") and</div><div class='add'>+ * later revisions of the Librem 5 so it has to be included in dts there.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "imx8mq-librem5.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Purism Librem 5r3";</div><div class='add'>+	compatible = "purism,librem5r3", "purism,librem5", "fsl,imx8mq";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;accel_gyro {</div><div class='add'>+	mount-matrix = "1",  "0",  "0",</div><div class='add'>+		       "0",  "1",  "0",</div><div class='add'>+		       "0",  "0", "-1";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;bq25895 {</div><div class='add'>+	ti,charge-current = &lt;1500000&gt;; /* uA */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;camera_front {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_csi1&gt;, &lt;&amp;pinctrl_r3_camera_pwr&gt;;</div><div class='add'>+	shutdown-gpios = &lt;&amp;gpio5 4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_r3_camera_pwr: r3camerapwrgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4		0x83</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;magnetometer {</div><div class='add'>+	mount-matrix = "1",  "0",  "0",</div><div class='add'>+		       "0", "-1",  "0",</div><div class='add'>+		       "0",  "0", "-1";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;proximity {</div><div class='add'>+	proximity-near-level = &lt;10&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r4.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r4.dts<br/>new file mode 100644<br/>index 000000000000..33f398b48119<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mq-librem5-r4.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mq-librem5-r4.dts</a></div><div class='hunk'>@@ -0,0 +1,27 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+// Copyright (C) 2021 Purism SPC &lt;kernel@puri.sm&gt;</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mq-librem5-r3.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Purism Librem 5r4";</div><div class='add'>+	compatible = "purism,librem5r4", "purism,librem5", "fsl,imx8mq";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;bat {</div><div class='add'>+	maxim,rsns-microohm = &lt;1667&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;led_backlight {</div><div class='add'>+	led-max-microamp = &lt;25000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcd_panel {</div><div class='add'>+	compatible = "ys,ys57pss36bh5gq";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;proximity {</div><div class='add'>+	proximity-near-level = &lt;7&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi<br/>new file mode 100644<br/>index 000000000000..9e0e2d7271ef<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi</a></div><div class='hunk'>@@ -0,0 +1,1419 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2018-2020 Purism SPC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "dt-bindings/input/input.h"</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include "dt-bindings/pwm/pwm.h"</div><div class='add'>+#include "dt-bindings/usb/pd.h"</div><div class='add'>+#include "imx8mq.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Purism Librem 5";</div><div class='add'>+	compatible = "purism,librem5", "fsl,imx8mq";</div><div class='add'>+	chassis-type = "handset";</div><div class='add'>+</div><div class='add'>+	backlight_dsi: backlight-dsi {</div><div class='add'>+		compatible = "led-backlight";</div><div class='add'>+		leds = &lt;&amp;led_backlight&gt;;</div><div class='add'>+		brightness-levels = &lt;255&gt;;</div><div class='add'>+		default-brightness-level = &lt;190&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmic_osc: clock-pmic {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;32768&gt;;</div><div class='add'>+		clock-output-names = "pmic_osc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_keys&gt;;</div><div class='add'>+</div><div class='add'>+		key-vol-down {</div><div class='add'>+			label = "VOL_DOWN";</div><div class='add'>+			gpios = &lt;&amp;gpio1 17 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+			debounce-interval = &lt;50&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-vol-up {</div><div class='add'>+			label = "VOL_UP";</div><div class='add'>+			gpios = &lt;&amp;gpio1 16 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+			debounce-interval = &lt;50&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	led-controller {</div><div class='add'>+		compatible = "pwm-leds-multicolor";</div><div class='add'>+</div><div class='add'>+		multi-led {</div><div class='add'>+			color = &lt;LED_COLOR_ID_RGB&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			max-brightness = &lt;248&gt;;</div><div class='add'>+</div><div class='add'>+			led-0 {</div><div class='add'>+				color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+				pwms = &lt;&amp;pwm2 0 50000 0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			led-1 {</div><div class='add'>+				color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+				pwms = &lt;&amp;pwm4 0 50000 0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			led-2 {</div><div class='add'>+				color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+				pwms = &lt;&amp;pwm3 0 50000 0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_aud_1v8: regulator-audio-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_audiopwr&gt;;</div><div class='add'>+		regulator-name = "AUD_1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio1 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_mic_2v4: regulator-mic-2v4 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "MIC_2V4";</div><div class='add'>+		regulator-min-microvolt = &lt;2400000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;2400000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;reg_aud_1v8&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * the pinctrl for reg_csi_1v8 and reg_vcam_1v8 is added to the PMIC</div><div class='add'>+	 * since we can't have it twice in the 2 different regulator nodes.</div><div class='add'>+	 */</div><div class='add'>+	reg_csi_1v8: regulator-csi-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "CAMERA_VDDIO_1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;reg_vdd_3v3&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio1 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* controlled by the CAMERA_POWER_KEY HKS */</div><div class='add'>+	reg_vcam_1v2: regulator-vcam-1v2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "CAMERA_VDDD_1V2";</div><div class='add'>+		regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;reg_vdd_1v8&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcam_2v8: regulator-vcam-2v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "CAMERA_VDDA_2V8";</div><div class='add'>+		regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;reg_vdd_3v3&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio1 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_gnss: regulator-gnss {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gnsspwr&gt;;</div><div class='add'>+		regulator-name = "GNSS";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio3 12 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_hub: regulator-hub {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_hub_pwr&gt;;</div><div class='add'>+		regulator-name = "HUB";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio1 14 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_lcd_1v8: regulator-lcd-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_dsien&gt;;</div><div class='add'>+		regulator-name = "LCD_1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;reg_vdd_1v8&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio1 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		/* Otherwise i2c3 is not functional */</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_lcd_3v4: regulator-lcd-3v4 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "LCD_3V4";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_dsibiasen&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;reg_vsys_3v4&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio1 20 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vdd_sen: regulator-vdd-sen {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_SEN";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vdd_1v8: regulator-vdd-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;buck7_reg&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vdd_3v3: regulator-vdd-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vsys_3v4: regulator-vsys-3v4 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VSYS_3V4";</div><div class='add'>+		regulator-min-microvolt = &lt;3400000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3400000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_wifi_3v3: regulator-wifi-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_wifi_pwr&gt;;</div><div class='add'>+		regulator-name = "3V3_WIFI";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio3 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		vin-supply = &lt;&amp;reg_vdd_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_hp&gt;;</div><div class='add'>+		simple-audio-card,name = "Librem 5";</div><div class='add'>+		simple-audio-card,format = "i2s";</div><div class='add'>+		simple-audio-card,widgets =</div><div class='add'>+			"Headphone", "Headphones",</div><div class='add'>+			"Microphone", "Headset Mic",</div><div class='add'>+			"Microphone", "Digital Mic",</div><div class='add'>+			"Speaker", "Speaker";</div><div class='add'>+		simple-audio-card,routing =</div><div class='add'>+			"Headphones", "HPOUTL",</div><div class='add'>+			"Headphones", "HPOUTR",</div><div class='add'>+			"Speaker", "SPKOUTL",</div><div class='add'>+			"Speaker", "SPKOUTR",</div><div class='add'>+			"Headset Mic", "MICBIAS",</div><div class='add'>+			"IN3R", "Headset Mic",</div><div class='add'>+			"DMICDAT", "Digital Mic";</div><div class='add'>+		simple-audio-card,hp-det-gpios = &lt;&amp;gpio3 9 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+		simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;sai2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		simple-audio-card,codec {</div><div class='add'>+			sound-dai = &lt;&amp;codec&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MQ_CLK_SAI2_ROOT&gt;;</div><div class='add'>+			frame-master;</div><div class='add'>+			bitclock-master;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-wwan {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,name = "Modem";</div><div class='add'>+		simple-audio-card,format = "i2s";</div><div class='add'>+</div><div class='add'>+		simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;sai6&gt;;</div><div class='add'>+			frame-inversion;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		simple-audio-card,codec {</div><div class='add'>+			sound-dai = &lt;&amp;bm818_codec&gt;;</div><div class='add'>+			frame-master;</div><div class='add'>+			bitclock-master;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usdhc2_pwrseq: pwrseq {</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_bt&gt;, &lt;&amp;pinctrl_wifi_disable&gt;;</div><div class='add'>+		compatible = "mmc-pwrseq-simple";</div><div class='add'>+		reset-gpios = &lt;&amp;gpio3 25 GPIO_ACTIVE_HIGH&gt;,</div><div class='add'>+			      &lt;&amp;gpio4 29 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bm818_codec: sound-wwan-codec {</div><div class='add'>+		compatible = "broadmobi,bm818", "option,gtm601";</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vibrator {</div><div class='add'>+		compatible = "pwm-vibrator";</div><div class='add'>+		pwms = &lt;&amp;pwm1 0 1000000000 0&gt;;</div><div class='add'>+		pwm-names = "enable";</div><div class='add'>+		vcc-supply = &lt;&amp;reg_vdd_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;buck2_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;csi1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ddrc {</div><div class='add'>+	operating-points-v2 = &lt;&amp;ddrc_opp_table&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ddrc_opp_table: opp-table {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		opp-25000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;25000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-100000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;100000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-166000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;166935483&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-800000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;800000000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dphy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi1&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	nor_flash: flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;1000000&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		partition@0 {</div><div class='add'>+			label = "protected0";</div><div class='add'>+			reg = &lt;0x0 0x30000&gt;;</div><div class='add'>+			read-only;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		partition@30000 {</div><div class='add'>+			label = "firmware";</div><div class='add'>+			reg = &lt;0x30000 0x1d0000&gt;;</div><div class='add'>+			read-only;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pmic_5v&gt;;</div><div class='add'>+</div><div class='add'>+	pmic-5v-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		input;</div><div class='add'>+		line-name = "pmic-5v";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hog&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl_hog: hoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* CLKO2 for cameras on both CSI1 and CSI2 */</div><div class='add'>+			MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2      0x1f</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_audiopwr: audiopwrgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* AUDIO_POWER_EN_3V3 */</div><div class='add'>+			MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4	0x83</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_bl: blgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* BACKLINGE_EN */</div><div class='add'>+			MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14	0x83</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_bt: btgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* BT_REG_ON */</div><div class='add'>+			MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25	0x83</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_camera_pwr: camerapwrgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* CAMERA_PWR_EN_3V3 */</div><div class='add'>+			MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0	0x83</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_csi1: csi1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* CSI1_NRST */</div><div class='add'>+			MX8MQ_IOMUXC_ENET_RXC_GPIO1_IO25	0x83</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_charger_in: chargeringrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* CHRG_INT */</div><div class='add'>+			MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3	0x80</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_dsibiasen: dsibiasengrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* DSI_BIAS_EN */</div><div class='add'>+			MX8MQ_IOMUXC_ENET_TD1_GPIO1_IO20	0x83</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_dsien: dsiengrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* DSI_EN_3V3 */</div><div class='add'>+			MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5	0x83</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_dsirst: dsirstgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* DSI_RST */</div><div class='add'>+			MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29	0x83</div><div class='add'>+			/* DSI_TE */</div><div class='add'>+			MX8MQ_IOMUXC_ENET_RD2_GPIO1_IO28	0x83</div><div class='add'>+			/* TP_RST */</div><div class='add'>+			MX8MQ_IOMUXC_ENET_RX_CTL_GPIO1_IO24	0x83</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi1: ecspigrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI	0x83</div><div class='add'>+			MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO	0x83</div><div class='add'>+			MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9	0x19</div><div class='add'>+			MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK	0x83</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gauge: gaugegrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* BAT_LOW */</div><div class='add'>+			MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20	0x80</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gnsspwr: gnsspwrgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* GPS3V3_EN */</div><div class='add'>+			MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12	0x83</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_haptic: hapticgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* MOTO */</div><div class='add'>+			MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT	0x83</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_hp: hpgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* HEADPHONE_DET_1V8 */</div><div class='add'>+			MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9	0x180</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_hub_pwr: hubpwrgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* HUB_PWR_3V3_EN */</div><div class='add'>+			MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14	0x83</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL		0x40000026</div><div class='add'>+			MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA		0x40000026</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL		0x40000026</div><div class='add'>+			MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA		0x40000026</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL		0x40000026</div><div class='add'>+			MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA		0x40000026</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4: i2c4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL		0x40000026</div><div class='add'>+			MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA		0x40000026</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_keys: keysgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* VOL- */</div><div class='add'>+			MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17	0x01C0</div><div class='add'>+			/* VOL+ */</div><div class='add'>+			MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16	0x01C0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_led_b: ledbgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* LED_B */</div><div class='add'>+			MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT	0x06</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_led_g: ledggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* LED_G */</div><div class='add'>+			MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT		0x06</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_led_r: ledrgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* LED_R */</div><div class='add'>+			MX8MQ_IOMUXC_SPDIF_TX_PWM3_OUT		0x06</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_mag: maggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* INT_MAG */</div><div class='add'>+			MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22	0x80</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: pmicgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* PMIC_NINT */</div><div class='add'>+			MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7	0x80</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic_5v: pmic5vgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* PMIC_5V */</div><div class='add'>+			MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1	0x80</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_prox: proxgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* INT_LIGHT */</div><div class='add'>+			MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7	0x80</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_rtc: rtcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* RTC_INT */</div><div class='add'>+			MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9	0x80</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai2: sai2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0	0xd6</div><div class='add'>+			MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC	0xd6</div><div class='add'>+			MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK	0xd6</div><div class='add'>+			MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0	0xd6</div><div class='add'>+			MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK	0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai6: sai6grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0	0xd6</div><div class='add'>+			MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC	0xd6</div><div class='add'>+			MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK	0xd6</div><div class='add'>+			MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0	0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_tcpc: tcpcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* TCPC_INT */</div><div class='add'>+			MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10	0x01C0</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_touch: touchgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* TP_INT */</div><div class='add'>+			MX8MQ_IOMUXC_ENET_RD1_GPIO1_IO27	0x80</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_typec: typecgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* TYPEC_MUX_EN */</div><div class='add'>+			MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11	0x83</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX	0x49</div><div class='add'>+			MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX	0x49</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX	0x49</div><div class='add'>+			MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX	0x49</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: uart3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX	0x49</div><div class='add'>+			MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX	0x49</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart4: uart4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX		0x49</div><div class='add'>+			MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX		0x49</div><div class='add'>+			MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B	0x49</div><div class='add'>+			MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B		0x49</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83</div><div class='add'>+			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3</div><div class='add'>+			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x83</div><div class='add'>+			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x8d</div><div class='add'>+			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xcd</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xcd</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xcd</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xcd</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xcd</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xcd</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xcd</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xcd</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xcd</div><div class='add'>+			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x8d</div><div class='add'>+			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x9f</div><div class='add'>+			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xdf</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xdf</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xdf</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xdf</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xdf</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xdf</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xdf</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xdf</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xdf</div><div class='add'>+			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x9f</div><div class='add'>+			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12	0x80</div><div class='add'>+			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x83</div><div class='add'>+			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xc3</div><div class='add'>+			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0	0xc3</div><div class='add'>+			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1	0xc3</div><div class='add'>+			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2	0xc3</div><div class='add'>+			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3	0xc3</div><div class='add'>+			MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0xc1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12	0x80</div><div class='add'>+			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x8d</div><div class='add'>+			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xcd</div><div class='add'>+			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0	0xcd</div><div class='add'>+			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1	0xcd</div><div class='add'>+			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2	0xcd</div><div class='add'>+			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3	0xcd</div><div class='add'>+			MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0xc1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12	0x80</div><div class='add'>+			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x9f</div><div class='add'>+			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xcf</div><div class='add'>+			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0	0xcf</div><div class='add'>+			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1	0xcf</div><div class='add'>+			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2	0xcf</div><div class='add'>+			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3	0xcf</div><div class='add'>+			MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0xc1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wifi_disable: wifidisablegrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* WIFI_REG_ON */</div><div class='add'>+			MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29	0x83</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wifi_pwr: wifipwrgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* WIFI3V3_EN */</div><div class='add'>+			MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10	0x83</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* nWDOG */</div><div class='add'>+			MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0x1f</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;384000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	typec_pd: usb-pd@3f {</div><div class='add'>+		compatible = "ti,tps6598x";</div><div class='add'>+		reg = &lt;0x3f&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_typec&gt;, &lt;&amp;pinctrl_tcpc&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;10 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupt-names = "irq";</div><div class='add'>+		wakeup-source;</div><div class='add'>+</div><div class='add'>+		connector {</div><div class='add'>+			compatible = "usb-c-connector";</div><div class='add'>+			label = "USB-C";</div><div class='add'>+			data-role = "dual";</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					usb_con_hs: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;typec_hs&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					usb_con_ss: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;typec_ss&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmic: pmic@4b {</div><div class='add'>+		compatible = "rohm,bd71837";</div><div class='add'>+		reg = &lt;0x4b&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;, &lt;&amp;pinctrl_camera_pwr&gt;;</div><div class='add'>+		clocks = &lt;&amp;pmic_osc&gt;;</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-names = "osc";</div><div class='add'>+		clock-output-names = "pmic_clk";</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;7 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		rohm,reset-snvs-powered;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			buck1_reg: BUCK1 {</div><div class='add'>+				regulator-name = "buck1";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-ramp-delay = &lt;1250&gt;;</div><div class='add'>+				rohm,dvs-run-voltage = &lt;880000&gt;;</div><div class='add'>+				rohm,dvs-idle-voltage = &lt;820000&gt;;</div><div class='add'>+				rohm,dvs-suspend-voltage = &lt;810000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck2_reg: BUCK2 {</div><div class='add'>+				regulator-name = "buck2";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-ramp-delay = &lt;1250&gt;;</div><div class='add'>+				rohm,dvs-run-voltage = &lt;950000&gt;;</div><div class='add'>+				rohm,dvs-idle-voltage = &lt;850000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck3_reg: BUCK3 {</div><div class='add'>+				regulator-name = "buck3";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				rohm,dvs-run-voltage = &lt;850000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck4_reg: BUCK4 {</div><div class='add'>+				regulator-name = "buck4";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				rohm,dvs-run-voltage = &lt;930000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck5_reg: BUCK5 {</div><div class='add'>+				regulator-name = "buck5";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck6_reg: BUCK6 {</div><div class='add'>+				regulator-name = "buck6";</div><div class='add'>+				regulator-min-microvolt = &lt;3000000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck7_reg: BUCK7 {</div><div class='add'>+				regulator-name = "buck7";</div><div class='add'>+				regulator-min-microvolt = &lt;1605000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1995000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck8_reg: BUCK8 {</div><div class='add'>+				regulator-name = "buck8";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo1_reg: LDO1 {</div><div class='add'>+				regulator-name = "ldo1";</div><div class='add'>+				regulator-min-microvolt = &lt;3000000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				/* leave on for snvs power button */</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo2_reg: LDO2 {</div><div class='add'>+				regulator-name = "ldo2";</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				/* leave on for snvs power button */</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo3_reg: LDO3 {</div><div class='add'>+				regulator-name = "ldo3";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo4_reg: LDO4 {</div><div class='add'>+				regulator-name = "ldo4";</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo5_reg: LDO5 {</div><div class='add'>+				/* VDD_PHY_0V9 - MIPI and HDMI domains */</div><div class='add'>+				regulator-name = "ldo5";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo6_reg: LDO6 {</div><div class='add'>+				/* VDD_PHY_0V9 - MIPI, HDMI and USB domains */</div><div class='add'>+				regulator-name = "ldo6";</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo7_reg: LDO7 {</div><div class='add'>+				/* VDD_PHY_3V3 - USB domain */</div><div class='add'>+				regulator-name = "ldo7";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rtc@68 {</div><div class='add'>+		compatible = "microcrystal,rv4162";</div><div class='add'>+		reg = &lt;0x68&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_rtc&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;9 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;384000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	magnetometer: magnetometer@1e	{</div><div class='add'>+		compatible = "st,lsm9ds1-magn";</div><div class='add'>+		reg = &lt;0x1e&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_mag&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+		interrupts = &lt;22 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;reg_vdd_sen&gt;;</div><div class='add'>+		vddio-supply = &lt;&amp;reg_vdd_1v8&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	regulator@3e {</div><div class='add'>+		compatible = "ti,tps65132";</div><div class='add'>+		reg = &lt;0x3e&gt;;</div><div class='add'>+</div><div class='add'>+		reg_lcd_avdd: outp {</div><div class='add'>+			regulator-name = "LCD_AVDD";</div><div class='add'>+			vin-supply = &lt;&amp;reg_lcd_3v4&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		reg_lcd_avee: outn {</div><div class='add'>+			regulator-name = "LCD_AVEE";</div><div class='add'>+			vin-supply = &lt;&amp;reg_lcd_3v4&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	proximity: prox@60 {</div><div class='add'>+		compatible = "vishay,vcnl4040";</div><div class='add'>+		reg = &lt;0x60&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_prox&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+		interrupts = &lt;7 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	accel_gyro: accel-gyro@6a	{</div><div class='add'>+		compatible = "st,lsm9ds1-imu";</div><div class='add'>+		reg = &lt;0x6a&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;reg_vdd_sen&gt;;</div><div class='add'>+		vddio-supply = &lt;&amp;reg_vdd_1v8&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	clock-frequency = &lt;384000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	codec: audio-codec@1a {</div><div class='add'>+		compatible = "wlf,wm8962";</div><div class='add'>+		reg = &lt;0x1a&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX8MQ_CLK_SAI2_ROOT&gt;;</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX8MQ_CLK_SAI2&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;&amp;clk IMX8MQ_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;24576000&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		mic-cfg = &lt;0x200&gt;;</div><div class='add'>+		DCVDD-supply = &lt;&amp;reg_aud_1v8&gt;;</div><div class='add'>+		DBVDD-supply = &lt;&amp;reg_aud_1v8&gt;;</div><div class='add'>+		AVDD-supply = &lt;&amp;reg_aud_1v8&gt;;</div><div class='add'>+		CPVDD-supply = &lt;&amp;reg_aud_1v8&gt;;</div><div class='add'>+		MICVDD-supply = &lt;&amp;reg_mic_2v4&gt;;</div><div class='add'>+		PLLVDD-supply = &lt;&amp;reg_aud_1v8&gt;;</div><div class='add'>+		SPKVDD1-supply = &lt;&amp;reg_vsys_3v4&gt;;</div><div class='add'>+		SPKVDD2-supply = &lt;&amp;reg_vsys_3v4&gt;;</div><div class='add'>+		gpio-cfg = &lt;</div><div class='add'>+			0x0000 /* n/c */</div><div class='add'>+			0x0001 /* gpio2, 1: default */</div><div class='add'>+			0x0013 /* gpio3, 2: dmicclk */</div><div class='add'>+			0x0000 /* n/c, 3: default */</div><div class='add'>+			0x8014 /* gpio5, 4: dmic_dat */</div><div class='add'>+			0x0000 /* gpio6, 5: default */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	camera_front: camera@20 {</div><div class='add'>+		compatible = "hynix,hi846";</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_csi1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX8MQ_CLK_CLKO2&gt;;</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX8MQ_CLK_CLKO2&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;25000000&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio1 25 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		vdda-supply = &lt;&amp;reg_vcam_2v8&gt;;</div><div class='add'>+		vddd-supply = &lt;&amp;reg_vcam_1v2&gt;;</div><div class='add'>+		vddio-supply = &lt;&amp;reg_csi_1v8&gt;;</div><div class='add'>+		rotation = &lt;90&gt;;</div><div class='add'>+		orientation = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			camera1_ep: endpoint {</div><div class='add'>+				data-lanes = &lt;1 2&gt;;</div><div class='add'>+				link-frequencies = /bits/ 64</div><div class='add'>+					&lt;80000000 200000000 300000000&gt;;</div><div class='add'>+				remote-endpoint = &lt;&amp;mipi1_sensor_ep&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	backlight@36 {</div><div class='add'>+		compatible = "ti,lm36922";</div><div class='add'>+		reg = &lt;0x36&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_bl&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;gpio3 14 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		vled-supply = &lt;&amp;reg_vsys_3v4&gt;;</div><div class='add'>+		ti,ovp-microvolt = &lt;25000000&gt;;</div><div class='add'>+</div><div class='add'>+		led_backlight: led@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			label = ":backlight";</div><div class='add'>+			linux,default-trigger = "backlight";</div><div class='add'>+			led-max-microamp = &lt;20000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	touchscreen@38 {</div><div class='add'>+		compatible = "edt,edt-ft5506";</div><div class='add'>+		reg = &lt;0x38&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_touch&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;27 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		touchscreen-size-x = &lt;720&gt;;</div><div class='add'>+		touchscreen-size-y = &lt;1440&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_lcd_1v8&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	clock-frequency = &lt;384000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	vcm@c {</div><div class='add'>+		compatible = "dongwoon,dw9714";</div><div class='add'>+		reg = &lt;0x0c&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_csi_1v8&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bat: fuel-gauge@36 {</div><div class='add'>+		compatible = "maxim,max17055";</div><div class='add'>+		reg = &lt;0x36&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+		interrupts = &lt;20 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gauge&gt;;</div><div class='add'>+		power-supplies = &lt;&amp;bq25895&gt;;</div><div class='add'>+		maxim,over-heat-temp = &lt;700&gt;;</div><div class='add'>+		maxim,over-volt = &lt;4500&gt;;</div><div class='add'>+		maxim,rsns-microohm = &lt;5000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bq25895: charger@6a {</div><div class='add'>+		compatible = "ti,bq25895", "ti,bq25890";</div><div class='add'>+		reg = &lt;0x6a&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_charger_in&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+		interrupts = &lt;3 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		ti,battery-regulation-voltage = &lt;4208000&gt;; /* uV */</div><div class='add'>+		ti,termination-current = &lt;128000&gt;;  /* uA */</div><div class='add'>+		ti,precharge-current = &lt;128000&gt;; /* uA */</div><div class='add'>+		ti,minimum-sys-voltage = &lt;3700000&gt;; /* uV */</div><div class='add'>+		ti,boost-voltage = &lt;5000000&gt;; /* uV */</div><div class='add'>+		ti,boost-max-current = &lt;1500000&gt;; /* uA */</div><div class='add'>+		monitored-battery = &lt;&amp;bat&gt;;</div><div class='add'>+		power-supplies = &lt;&amp;typec_pd&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_csi1 {</div><div class='add'>+	assigned-clock-rates = &lt;266000000&gt;, &lt;200000000&gt;, &lt;66000000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			mipi1_sensor_ep: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;camera1_ep&gt;;</div><div class='add'>+				data-lanes = &lt;1 2&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_dsi {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	lcd_panel: panel@0 {</div><div class='add'>+		compatible = "mantix,mlaf057we51-x";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_dsirst&gt;;</div><div class='add'>+		avdd-supply = &lt;&amp;reg_lcd_avdd&gt;;</div><div class='add'>+		avee-supply = &lt;&amp;reg_lcd_avee&gt;;</div><div class='add'>+		vddi-supply = &lt;&amp;reg_lcd_1v8&gt;;</div><div class='add'>+		backlight = &lt;&amp;backlight_dsi&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio1 29 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		mantix,tp-rstn-gpios = &lt;&amp;gpio1 24 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			panel_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;mipi_dsi_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			mipi_dsi_out: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;panel_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pgc_gpu {</div><div class='add'>+	power-supply = &lt;&amp;buck3_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pgc_mipi {</div><div class='add'>+	power-supply = &lt;&amp;ldo5_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pgc_vpu {</div><div class='add'>+	power-supply = &lt;&amp;buck4_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_haptic&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_led_b&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_led_r&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_led_g&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai2&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MQ_CLK_SAI2&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MQ_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;24576000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai6 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai6&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MQ_CLK_SAI6&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MQ_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;24576000&gt;;</div><div class='add'>+	fsl,sai-synchronous-rx;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;snvs_pwrkey {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;snvs_rtc {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 { /* console */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 { /* TPS - GPS - DEBUG */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	gnss {</div><div class='add'>+		compatible = "globaltop,pa6h";</div><div class='add'>+		vcc-supply = &lt;&amp;reg_gnss&gt;;</div><div class='add'>+		current-speed = &lt;9600&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart3 { /* SMC */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart4 { /* BT */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart4&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy1 {</div><div class='add'>+	vbus-supply = &lt;&amp;reg_hub&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_0 {</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		port@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			typec_hs: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;usb_con_hs&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			typec_ss: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;usb_con_ss&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_1 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	/* Microchip USB2642 */</div><div class='add'>+	hub@1 {</div><div class='add'>+		compatible = "usb424,2640";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		mass-storage@1 {</div><div class='add'>+			compatible = "usb424,4041";</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MQ_CLK_USDHC1&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1_200mhz&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_vdd_3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_vdd_1v8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MQ_CLK_USDHC2&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;200000000&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_wifi_3v3&gt;;</div><div class='add'>+	mmc-pwrseq = &lt;&amp;usdhc2_pwrseq&gt;;</div><div class='add'>+	post-power-on-delay-ms = &lt;20&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	max-frequency = &lt;100000000&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+	cap-sdio-irq;</div><div class='add'>+	keep-power-in-suspend;</div><div class='add'>+	wakeup-source;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;a53_opp_table {</div><div class='add'>+	opp-1000000000 {</div><div class='add'>+		opp-microvolt = &lt;850000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	opp-1500000000 {</div><div class='add'>+		opp-microvolt = &lt;950000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts b/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts<br/>new file mode 100644<br/>index 000000000000..3ae3824be027<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts</a></div><div class='hunk'>@@ -0,0 +1,353 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2019-2021 MNT Research GmbH</div><div class='add'>+ * Copyright 2021 Lucas Stach &lt;dev@lynxeye.de&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mq-nitrogen-som.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "MNT Reform 2";</div><div class='add'>+	compatible = "mntre,reform2", "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq";</div><div class='add'>+	chassis-type = "laptop";</div><div class='add'>+</div><div class='add'>+	backlight: backlight {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_backlight&gt;;</div><div class='add'>+		pwms = &lt;&amp;pwm2 0 10000 0&gt;;</div><div class='add'>+		power-supply = &lt;&amp;reg_main_usb&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;gpio1 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		brightness-levels = &lt;0 32 64 128 160 200 255&gt;;</div><div class='add'>+		default-brightness-level = &lt;6&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	panel {</div><div class='add'>+		compatible = "innolux,n125hce-gn1";</div><div class='add'>+		power-supply = &lt;&amp;reg_main_3v3&gt;;</div><div class='add'>+		backlight = &lt;&amp;backlight&gt;;</div><div class='add'>+		no-hpd;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			panel_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;edp_bridge_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie1_refclk: clock-pcie1-refclk {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;100000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_main_5v: regulator-main-5v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "5V";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_main_3v3: regulator-main-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_main_usb: regulator-main-usb {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "USB_PWR";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;reg_main_5v&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_main_1v8: regulator-main-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;reg_main_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_main_1v2: regulator-main-1v2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "1V2";</div><div class='add'>+		regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;reg_main_5v&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "fsl,imx-audio-wm8960";</div><div class='add'>+		audio-cpu = &lt;&amp;sai2&gt;;</div><div class='add'>+		audio-codec = &lt;&amp;wm8960&gt;;</div><div class='add'>+		audio-routing =</div><div class='add'>+			"Headphone Jack", "HP_L",</div><div class='add'>+			"Headphone Jack", "HP_R",</div><div class='add'>+			"Ext Spk", "SPK_LP",</div><div class='add'>+			"Ext Spk", "SPK_LN",</div><div class='add'>+			"Ext Spk", "SPK_RP",</div><div class='add'>+			"Ext Spk", "SPK_RN",</div><div class='add'>+			"LINPUT1", "Mic Jack",</div><div class='add'>+			"Mic Jack", "MICB",</div><div class='add'>+			"LINPUT2", "Line In Jack",</div><div class='add'>+			"RINPUT2", "Line In Jack";</div><div class='add'>+		model = "wm8960-audio";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dphy {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MQ_CLK_DSI_PHY_REF&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MQ_SYS1_PLL_800M&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;25000000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	wm8960: codec@1a {</div><div class='add'>+		compatible = "wlf,wm8960";</div><div class='add'>+		reg = &lt;0x1a&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX8MQ_CLK_SAI2_ROOT&gt;;</div><div class='add'>+		clock-names = "mclk";</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rtc@68 {</div><div class='add'>+		compatible = "nxp,pcf8523";</div><div class='add'>+		reg = &lt;0x68&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c4&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	edp_bridge: bridge@2c {</div><div class='add'>+		compatible = "ti,sn65dsi86";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_edp_bridge&gt;;</div><div class='add'>+		reg = &lt;0x2c&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;gpio3 20 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		vccio-supply = &lt;&amp;reg_main_1v8&gt;;</div><div class='add'>+		vpll-supply = &lt;&amp;reg_main_1v8&gt;;</div><div class='add'>+		vcca-supply = &lt;&amp;reg_main_1v2&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_main_1v2&gt;;</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				edp_bridge_in: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;mipi_dsi_out&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				edp_bridge_out: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;panel_in&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MQ_CLK_LCDIF_PIXEL&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MQ_SYS1_PLL_800M&gt;;</div><div class='add'>+	/delete-property/assigned-clock-rates;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_dsi {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			mipi_dsi_out: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;edp_bridge_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie1&gt;;</div><div class='add'>+	reset-gpio = &lt;&amp;gpio3 23 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	clocks = &lt;&amp;clk IMX8MQ_CLK_PCIE2_ROOT&gt;,</div><div class='add'>+		 &lt;&amp;pcie1_refclk&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX8MQ_CLK_PCIE2_PHY&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX8MQ_CLK_PCIE2_AUX&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_1p8v {</div><div class='add'>+	vin-supply = &lt;&amp;reg_main_5v&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_snvs {</div><div class='add'>+	vin-supply = &lt;&amp;reg_main_5v&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_arm_dram {</div><div class='add'>+	vin-supply = &lt;&amp;reg_main_5v&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_dram_1p1v {</div><div class='add'>+	vin-supply = &lt;&amp;reg_main_5v&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_soc_gpu_vpu {</div><div class='add'>+	vin-supply = &lt;&amp;reg_main_5v&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai2&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MQ_CLK_SAI2&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MQ_CLK_25M&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;25000000&gt;;</div><div class='add'>+	fsl,sai-mclk-direction-output;</div><div class='add'>+	fsl,sai-asynchronous;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;snvs_rtc {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy0 {</div><div class='add'>+	vbus-supply = &lt;&amp;reg_main_usb&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy1 {</div><div class='add'>+	vbus-supply = &lt;&amp;reg_main_usb&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_0 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_1 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MQ_CLK_USDHC2&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;200000000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_main_3v3&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_main_3v3&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_backlight: backlightgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_edp_bridge: edpbridgegrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20		0x1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL			0x40000022</div><div class='add'>+			MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA			0x40000022</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4: i2c4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL			0x40000022</div><div class='add'>+			MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA			0x40000022</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie1: pcie1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23		0x16</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm2: pwm2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT			0x3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai2: sai2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0		0xd6</div><div class='add'>+			MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC		0xd6</div><div class='add'>+			MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK		0xd6</div><div class='add'>+			MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC		0xd6</div><div class='add'>+			MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK		0xd6</div><div class='add'>+			MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK		0xd6</div><div class='add'>+			MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0		0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX		0x45</div><div class='add'>+			MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX		0x45</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_SD2_CD_B_USDHC2_CD_B		0x0</div><div class='add'>+			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x83</div><div class='add'>+			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc3</div><div class='add'>+			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3</div><div class='add'>+			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3</div><div class='add'>+			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3</div><div class='add'>+			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mq-nitrogen-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-nitrogen-som.dtsi<br/>new file mode 100644<br/>index 000000000000..395f77b5aca7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mq-nitrogen-som.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mq-nitrogen-som.dtsi</a></div><div class='hunk'>@@ -0,0 +1,278 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2018 Boundary Devices</div><div class='add'>+ * Copyright 2021 Lucas Stach &lt;dev@lynxeye.de&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "imx8mq.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Boundary Devices i.MX8MQ Nitrogen8M";</div><div class='add'>+	compatible = "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq";</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_1p8v: regulator-fixed-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "1P8V";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_snvs: regulator-fixed-snvs {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_SNVS";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;{/opp-table/opp-800000000} {</div><div class='add'>+	opp-microvolt = &lt;1000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;{/opp-table/opp-1000000000} {</div><div class='add'>+	opp-microvolt = &lt;1000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_arm_dram&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_arm_dram&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_arm_dram&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_arm_dram&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec1&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	fsl,magic-packet;</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@4 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;4&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+			interrupts = &lt;11 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio1 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;10000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;300&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	i2c-mux@70 {</div><div class='add'>+		compatible = "nxp,pca9546";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_i2c1_pca9546&gt;;</div><div class='add'>+		reg = &lt;0x70&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio1 8 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		i2c1a: i2c@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			reg_arm_dram: regulator@60 {</div><div class='add'>+				compatible = "fcs,fan53555";</div><div class='add'>+				reg = &lt;0x60&gt;;</div><div class='add'>+				regulator-name = "VDD_ARM_DRAM_1V";</div><div class='add'>+				regulator-min-microvolt = &lt;1000000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c1b: i2c@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			reg_dram_1p1v: regulator@60 {</div><div class='add'>+				compatible = "fcs,fan53555";</div><div class='add'>+				reg = &lt;0x60&gt;;</div><div class='add'>+				regulator-name = "NVCC_DRAM_1P1V";</div><div class='add'>+				regulator-min-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c1c: i2c@2 {</div><div class='add'>+			reg = &lt;2&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			reg_soc_gpu_vpu: regulator@60 {</div><div class='add'>+				compatible = "fcs,fan53555";</div><div class='add'>+				reg = &lt;0x60&gt;;</div><div class='add'>+				regulator-name = "VDD_SOC_GPU_VPU";</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c1d: i2c@3 {</div><div class='add'>+			reg = &lt;3&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pgc_gpu {</div><div class='add'>+	power-supply = &lt;&amp;reg_soc_gpu_vpu&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pgc_vpu {</div><div class='add'>+	power-supply = &lt;&amp;reg_soc_gpu_vpu&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MQ_CLK_USDHC1&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1_200mhz&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_1p8v&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_snvs&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	no-mmc-hs400;</div><div class='add'>+	no-sdio;</div><div class='add'>+	no-sd;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_fec1: fec1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC			0x3</div><div class='add'>+			MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO		0x23</div><div class='add'>+			MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f</div><div class='add'>+			MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f</div><div class='add'>+			MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f</div><div class='add'>+			MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f</div><div class='add'>+			MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f</div><div class='add'>+			MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f</div><div class='add'>+			MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91</div><div class='add'>+			MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0xd1</div><div class='add'>+			MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91</div><div class='add'>+			MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91</div><div class='add'>+			MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91</div><div class='add'>+			MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0xd1</div><div class='add'>+			MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x1</div><div class='add'>+			MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL			0x40000022</div><div class='add'>+			MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA			0x40000022</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1_pca9546: i2c1-pca9546grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8		0x49</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x45</div><div class='add'>+			MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x45</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83</div><div class='add'>+			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3</div><div class='add'>+			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x8d</div><div class='add'>+			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xcd</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xcd</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xcd</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xcd</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xcd</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xcd</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xcd</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xcd</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xcd</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x9f</div><div class='add'>+			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xdf</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xdf</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xdf</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xdf</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xdf</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xdf</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xdf</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xdf</div><div class='add'>+			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xdf</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0xc6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts b/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts<br/>index 81d269296610..767819cce886 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts</a></div><div class='hunk'>@@ -26,7 +26,7 @@</div><div class='ctx'> 		pinctrl-names = "default";</div><div class='ctx'> 		pinctrl-0 = &lt;&amp;pinctrl_gpio_keys&gt;;</div><div class='ctx'> </div><div class='del'>-		power {</div><div class='add'>+		button-power {</div><div class='ctx'> 			label = "Power Button";</div><div class='ctx'> 			gpios = &lt;&amp;gpio1 7 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 			linux,code = &lt;KEY_POWER&gt;;</div><div class='hunk'>@@ -34,6 +34,30 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	hdmi-connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		ddc-i2c-bus = &lt;&amp;ddc_i2c_bus&gt;;</div><div class='add'>+		label = "hdmi";</div><div class='add'>+		type = "a";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			hdmi_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;lt8912_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb_otg_vbus: regulator-usb-otg-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usbotg_vbus&gt;;</div><div class='add'>+		regulator-name = "usb_otg_vbus";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio1 12 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	reg_vref_0v9: regulator-vref-0v9 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "vref-0v9";</div><div class='hunk'>@@ -70,6 +94,9 @@</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;dphy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='ctx'> </div><div class='ctx'> &amp;fec1 {</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='hunk'>@@ -91,13 +118,22 @@</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+/* Release reset of the USB Host HUB */</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	usb-host-reset-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;14 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		output-high;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;i2c1 {</div><div class='ctx'> 	clock-frequency = &lt;400000&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='del'>-	i2cmux@70 {</div><div class='add'>+	i2c-mux@70 {</div><div class='ctx'> 		compatible = "nxp,pca9546";</div><div class='ctx'> 		pinctrl-names = "default";</div><div class='ctx'> 		pinctrl-0 = &lt;&amp;pinctrl_i2c1_pca9546&gt;;</div><div class='hunk'>@@ -106,7 +142,7 @@</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;0&gt;;</div><div class='ctx'> </div><div class='del'>-		i2c1a: i2c1@0 {</div><div class='add'>+		i2c1a: i2c@0 {</div><div class='ctx'> 			reg = &lt;0&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='hunk'>@@ -116,14 +152,14 @@</div><div class='ctx'> 				pinctrl-names = "default";</div><div class='ctx'> 				pinctrl-0 = &lt;&amp;pinctrl_reg_arm_dram&gt;;</div><div class='ctx'> 				reg = &lt;0x60&gt;;</div><div class='del'>-				regulator-min-microvolt =  &lt;900000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;1000000&gt;;</div><div class='ctx'> 				regulator-always-on;</div><div class='ctx'> 				vsel-gpios = &lt;&amp;gpio3 24 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		i2c1b: i2c1@1 {</div><div class='add'>+		i2c1b: i2c@1 {</div><div class='ctx'> 			reg = &lt;1&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='hunk'>@@ -140,7 +176,7 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		i2c1c: i2c1@2 {</div><div class='add'>+		i2c1c: i2c@2 {</div><div class='ctx'> 			reg = &lt;2&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='hunk'>@@ -150,14 +186,14 @@</div><div class='ctx'> 				pinctrl-names = "default";</div><div class='ctx'> 				pinctrl-0 = &lt;&amp;pinctrl_reg_soc_gpu_vpu&gt;;</div><div class='ctx'> 				reg = &lt;0x60&gt;;</div><div class='del'>-				regulator-min-microvolt =  &lt;900000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;1000000&gt;;</div><div class='ctx'> 				regulator-always-on;</div><div class='ctx'> 				vsel-gpios = &lt;&amp;gpio2 20 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		i2c1d: i2c1@3 {</div><div class='add'>+		i2c1d: i2c@3 {</div><div class='ctx'> 			reg = &lt;3&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='hunk'>@@ -174,6 +210,98 @@</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pca9546: i2c-mux@70 {</div><div class='add'>+		compatible = "nxp,pca9546";</div><div class='add'>+		reg = &lt;0x70&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		i2c@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			clock-frequency = &lt;100000&gt;;</div><div class='add'>+</div><div class='add'>+			hdmi-bridge@48 {</div><div class='add'>+				compatible = "lontium,lt8912b";</div><div class='add'>+				reg = &lt;0x48&gt; ;</div><div class='add'>+				reset-gpios = &lt;&amp;max7323 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						hdmi_out_in: endpoint {</div><div class='add'>+							data-lanes = &lt;1 2 3 4&gt;;</div><div class='add'>+							remote-endpoint = &lt;&amp;mipi_dsi_out&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						lt8912_out: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;hdmi_connector_in&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ddc_i2c_bus: i2c@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			clock-frequency = &lt;100000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@3 {</div><div class='add'>+			reg = &lt;3&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			clock-frequency = &lt;100000&gt;;</div><div class='add'>+</div><div class='add'>+			max7323: gpio-expander@68 {</div><div class='add'>+				compatible = "maxim,max7323";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;pinctrl_max7323&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+				reg = &lt;0x68&gt;;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_dsi {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			mipi_dsi_out: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_out_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;uart1 { /* console */</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='hunk'>@@ -190,6 +318,29 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;usb_dwc3_0 {</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usb3_0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy0 {</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usb_otg_vbus&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_1 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usb3_1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;usdhc1 {</div><div class='ctx'> 	assigned-clocks = &lt;&amp;clk IMX8MQ_CLK_USDHC1&gt;;</div><div class='ctx'> 	assigned-clock-rates = &lt;400000000&gt;;</div><div class='hunk'>@@ -321,6 +472,19 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	pinctrl_i2c4: i2c4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL			0x4000007f</div><div class='add'>+			MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA			0x4000007f</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_max7323: max7323grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x19</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	pinctrl_reg_arm_dram: reg-arm-dramgrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24	0x16</div><div class='hunk'>@@ -339,6 +503,12 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x16</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	pinctrl_uart1: uart1grp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x45</div><div class='hunk'>@@ -353,6 +523,18 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	pinctrl_usb3_0: usb3-0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC		0x16</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usb3_1: usb3-1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14		0x16</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	pinctrl_usdhc1: usdhc1grp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts<br/>index 77ab568fae67..e34045d10a12 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts</a></div><div class='hunk'>@@ -6,6 +6,7 @@</div><div class='ctx'> /dts-v1/;</div><div class='ctx'> </div><div class='ctx'> #include "imx8mq.dtsi"</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	model = "Google i.MX8MQ Phanbell";</div><div class='hunk'>@@ -38,7 +39,7 @@</div><div class='ctx'> </div><div class='ctx'> 	fan: gpio-fan {</div><div class='ctx'> 		compatible = "gpio-fan";</div><div class='del'>-		gpio-fan,speed-map = &lt;0 0 8600 1&gt;;</div><div class='add'>+		gpio-fan,speed-map = &lt;0 0&gt;, &lt;8600 1&gt;;</div><div class='ctx'> 		gpios = &lt;&amp;gpio3 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 		#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 		pinctrl-names = "default";</div><div class='hunk'>@@ -125,7 +126,7 @@</div><div class='ctx'> 		clocks = &lt;&amp;pmic_osc&gt;;</div><div class='ctx'> 		clock-output-names = "pmic_clk";</div><div class='ctx'> 		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='del'>-		interrupts = &lt;3 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		interrupts = &lt;3 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> </div><div class='ctx'> 		regulators {</div><div class='ctx'> 			buck1: BUCK1 {</div><div class='hunk'>@@ -262,9 +263,6 @@</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pinctrl_fec1&gt;;</div><div class='ctx'> 	phy-mode = "rgmii-id";</div><div class='del'>-	phy-reset-gpios = &lt;&amp;gpio1 9 GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-	phy-reset-duration = &lt;10&gt;;</div><div class='del'>-	phy-reset-post-delay = &lt;50&gt;;</div><div class='ctx'> 	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='ctx'> 	fsl,magic-packet;</div><div class='ctx'> 	status = "okay";</div><div class='hunk'>@@ -275,6 +273,9 @@</div><div class='ctx'> 		ethphy0: ethernet-phy@0 {</div><div class='ctx'> 			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='ctx'> 			reg = &lt;0&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio1 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;10000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;50000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='hunk'>@@ -365,7 +366,7 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pinctrl_pmic: pmicirq {</div><div class='add'>+	pinctrl_pmic: pmicirqgrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x41</div><div class='ctx'> 		&gt;;</div><div class='hunk'>@@ -395,7 +396,7 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x85</div><div class='ctx'> 			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc5</div><div class='hunk'>@@ -412,7 +413,7 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x87</div><div class='ctx'> 			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc7</div><div class='hunk'>@@ -429,7 +430,7 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pinctrl_usdhc2_gpio: usdhc2grpgpio {</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12	0x41</div><div class='ctx'> 			MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41</div><div class='hunk'>@@ -448,7 +449,7 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x85</div><div class='ctx'> 			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc5</div><div class='hunk'>@@ -460,7 +461,7 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x87</div><div class='ctx'> 			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc7</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts b/arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts<br/>index 59da96b7143f..ec89b5adeb93 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts</a></div><div class='hunk'>@@ -9,6 +9,7 @@</div><div class='ctx'> /dts-v1/;</div><div class='ctx'> </div><div class='ctx'> #include "imx8mq.dtsi"</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	model = "TechNexion PICO-PI-8M";</div><div class='hunk'>@@ -66,12 +67,12 @@</div><div class='ctx'> 		compatible = "rohm,bd71837";</div><div class='ctx'> 		pinctrl-names = "default";</div><div class='ctx'> 		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='ctx'> 		clocks = &lt;&amp;pmic_osc&gt;;</div><div class='ctx'> 		clock-names = "osc";</div><div class='ctx'> 		clock-output-names = "pmic_clk";</div><div class='ctx'> 		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='del'>-		interrupts = &lt;3 GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-		interrupt-names = "irq";</div><div class='add'>+		interrupts = &lt;3 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> </div><div class='ctx'> 		regulators {</div><div class='ctx'> 			buck1: BUCK1 {</div><div class='hunk'>@@ -297,7 +298,7 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pinctrl_pmic: pmicirq {</div><div class='add'>+	pinctrl_pmic: pmicirqgrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x41</div><div class='ctx'> 		&gt;;</div><div class='hunk'>@@ -335,7 +336,7 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x85</div><div class='ctx'> 			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc5</div><div class='hunk'>@@ -351,7 +352,7 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x87</div><div class='ctx'> 			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc7</div><div class='hunk'>@@ -367,7 +368,7 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pinctrl_usdhc2_gpio: usdhc2grpgpio {</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12	0x41</div><div class='ctx'> 		&gt;;</div><div class='hunk'>@@ -385,7 +386,7 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x85</div><div class='ctx'> 			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc5</div><div class='hunk'>@@ -397,7 +398,7 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x87</div><div class='ctx'> 			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc7</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h b/arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h<br/>index b94b02080a34..68e8fa172974 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h</a></div><div class='hunk'>@@ -130,7 +130,7 @@</div><div class='ctx'> #define MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                                     0x0A4 0x30C 0x000 0x0 0x0</div><div class='ctx'> #define MX8MQ_IOMUXC_SD1_CMD_GPIO2_IO1                                      0x0A4 0x30C 0x000 0x5 0x0</div><div class='ctx'> #define MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0                                 0x0A8 0x310 0x000 0x0 0x0</div><div class='del'>-#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2                                    0x0A8 0x31  0x000 0x5 0x0</div><div class='add'>+#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2                                    0x0A8 0x310 0x000 0x5 0x0</div><div class='ctx'> #define MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1                                 0x0AC 0x314 0x000 0x0 0x0</div><div class='ctx'> #define MX8MQ_IOMUXC_SD1_DATA1_GPIO2_IO3                                    0x0AC 0x314 0x000 0x5 0x0</div><div class='ctx'> #define MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2                                 0x0B0 0x318 0x000 0x0 0x0</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mq-sr-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-sr-som.dtsi<br/>index 602c870a7ccb..efc00f4abeb1 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mq-sr-som.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mq-sr-som.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mq-sr-som.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mq-sr-som.dtsi</a></div><div class='hunk'>@@ -20,8 +20,6 @@</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pinctrl_fec1&gt;;</div><div class='ctx'> 	phy-mode = "rgmii-id";</div><div class='ctx'> 	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='del'>-	phy-reset-gpios = &lt;&amp;gpio1 9 GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-	phy-reset-duration = &lt;2&gt;;</div><div class='ctx'> 	fsl,magic-packet;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='hunk'>@@ -32,6 +30,8 @@</div><div class='ctx'> 		ethphy0: ethernet-phy@4 {</div><div class='ctx'> 			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='ctx'> 			reg = &lt;4&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio1 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;2000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='hunk'>@@ -133,7 +133,7 @@</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;pgc_gpu{</div><div class='add'>+&amp;pgc_gpu {</div><div class='ctx'> 	power-supply = &lt;&amp;sw1a_reg&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -275,7 +275,7 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x8d</div><div class='ctx'> 			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xcd</div><div class='hunk'>@@ -292,7 +292,7 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x9f</div><div class='ctx'> 			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xdf</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mq-thor96.dts b/arch/arm64/boot/dts/freescale/imx8mq-thor96.dts<br/>index b4795a032fa2..eaa9d0c0fcc1 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mq-thor96.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mq-thor96.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mq-thor96.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mq-thor96.dts</a></div><div class='hunk'>@@ -107,7 +107,7 @@</div><div class='ctx'> 		compatible = "mmc-pwrseq-simple";</div><div class='ctx'> 		pinctrl-names = "default";</div><div class='ctx'> 		pinctrl-0 = &lt;&amp;pinctrl_wifi_reg_on&gt;;</div><div class='del'>-		gpio = &lt;&amp;gpio3 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio3 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -122,7 +122,6 @@</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pinctrl_fec1&gt;;</div><div class='ctx'> 	phy-mode = "rgmii-id";</div><div class='del'>-	phy-reset-gpios = &lt;&amp;gpio1 9 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 	phy-handle = &lt;&amp;ethphy&gt;;</div><div class='ctx'> 	fsl,magic-packet;</div><div class='ctx'> 	status = "okay";</div><div class='hunk'>@@ -134,6 +133,7 @@</div><div class='ctx'> 		ethphy: ethernet-phy@3 {</div><div class='ctx'> 			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='ctx'> 			reg = &lt;3&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio1 9 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='hunk'>@@ -339,7 +339,7 @@</div><div class='ctx'> 	bus-width = &lt;4&gt;;</div><div class='ctx'> 	non-removable;</div><div class='ctx'> 	no-sd;</div><div class='del'>-	no-emmc;</div><div class='add'>+	no-mmc;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='ctx'> 	brcmf: wifi@1 {</div><div class='hunk'>@@ -359,7 +359,7 @@</div><div class='ctx'> 	cd-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 	bus-width = &lt;4&gt;;</div><div class='ctx'> 	no-sdio;</div><div class='del'>-	no-emmc;</div><div class='add'>+	no-mmc;</div><div class='ctx'> 	disable-wp;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx-lvds-tm070jvhg33.dtso b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx-lvds-tm070jvhg33.dtso<br/>new file mode 100644<br/>index 000000000000..306977d6ba0c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx-lvds-tm070jvhg33.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx-lvds-tm070jvhg33.dtso</a></div><div class='hunk'>@@ -0,0 +1,49 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2019-2023 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Alexander Stein</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+</div><div class='add'>+&amp;{/} {</div><div class='add'>+	compatible = "tq,imx8mq-tqma8mq-mba8mx", "tq,imx8mq-tqma8mq", "fsl,imx8mq";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;backlight_lvds {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dphy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsi_lvds_bridge {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;expander0 {</div><div class='add'>+	dsi-mux-oe-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		output-high;</div><div class='add'>+		line-name = "DSI_MUX_OE#";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lcdif {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_dsi {</div><div class='add'>+       status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;panel {</div><div class='add'>+	compatible = "tianma,tm070jvhg33";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts<br/>new file mode 100644<br/>index 000000000000..0165f3a25985<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts</a></div><div class='hunk'>@@ -0,0 +1,332 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2019-2021 TQ-Systems GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8mq-tqma8mq.dtsi"</div><div class='add'>+#include "mba8mx.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "TQ-Systems GmbH i.MX8MQ TQMa8MQ on MBa8Mx";</div><div class='add'>+	compatible = "tq,imx8mq-tqma8mq-mba8mx", "tq,imx8mq-tqma8mq", "fsl,imx8mq";</div><div class='add'>+	chassis-type = "embedded";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		eeprom0 = &amp;eeprom3;</div><div class='add'>+		mmc0 = &amp;usdhc1;</div><div class='add'>+		mmc1 = &amp;usdhc2;</div><div class='add'>+		rtc0 = &amp;pcf85063;</div><div class='add'>+		rtc1 = &amp;snvs_rtc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	extcon_usbotg: extcon-usbotg0 {</div><div class='add'>+		compatible = "linux,extcon-usb-gpio";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usbcon0&gt;;</div><div class='add'>+		id-gpios = &lt;&amp;gpio1 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_otg_vbus: regulator-otg-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_regotgvbus&gt;;</div><div class='add'>+		regulator-name = "MBA8MQ_OTG_VBUS";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio1 12 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-vmmc {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VSD_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio2 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;btn2 {</div><div class='add'>+	gpios = &lt;&amp;gpio3 17 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio_leds {</div><div class='add'>+	led3 {</div><div class='add'>+		label = "led3";</div><div class='add'>+		gpios = &lt;&amp;gpio1 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	expander2: gpio@25 {</div><div class='add'>+		compatible = "nxp,pca9555";</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_vcc_3v3&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_expander&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;9 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		mpcie-rst-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;13 0&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+			line-name = "MPCIE_RST#";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;irqsteer {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;led2 {</div><div class='add'>+	gpios = &lt;&amp;gpio3 16 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* PCIe slot on X36 */</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	reset-gpio = &lt;&amp;expander0 14 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	clocks = &lt;&amp;clk IMX8MQ_CLK_PCIE1_ROOT&gt;,</div><div class='add'>+		 &lt;&amp;pcieclk 3&gt;,</div><div class='add'>+		 &lt;&amp;pcieclk 2&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX8MQ_CLK_PCIE1_AUX&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * miniPCIe on X28, also usable for cards with USB. Therefore configure the reset as</div><div class='add'>+ * static gpio hog.</div><div class='add'>+ */</div><div class='add'>+&amp;pcie1 {</div><div class='add'>+	clocks = &lt;&amp;clk IMX8MQ_CLK_PCIE2_ROOT&gt;,</div><div class='add'>+		 &lt;&amp;pcieclk 1&gt;,</div><div class='add'>+		 &lt;&amp;pcieclk 0&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX8MQ_CLK_PCIE2_AUX&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai3 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MQ_CLK_SAI3&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MQ_AUDIO_PLL1_OUT&gt;;</div><div class='add'>+	clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";</div><div class='add'>+	clocks = &lt;&amp;clk IMX8MQ_CLK_SAI3_IPG&gt;, &lt;&amp;clk IMX8MQ_CLK_DUMMY&gt;,</div><div class='add'>+		&lt;&amp;clk IMX8MQ_CLK_SAI3_ROOT&gt;, &lt;&amp;clk IMX8MQ_CLK_DUMMY&gt;,</div><div class='add'>+		&lt;&amp;clk IMX8MQ_CLK_DUMMY&gt;, &lt;&amp;clk IMX8MQ_AUDIO_PLL1_OUT&gt;,</div><div class='add'>+		&lt;&amp;clk IMX8MQ_AUDIO_PLL2_OUT&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tlv320aic3x04 {</div><div class='add'>+	clock-names = "mclk";</div><div class='add'>+	clocks = &lt;&amp;clk IMX8MQ_CLK_SAI3_ROOT&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MQ_CLK_UART1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MQ_SYS1_PLL_80M&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MQ_CLK_UART2&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MQ_SYS1_PLL_80M&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* console */</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MQ_CLK_UART3&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MQ_CLK_25M&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy0 {</div><div class='add'>+	vbus-supply = &lt;&amp;reg_otg_vbus&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_0 {</div><div class='add'>+	/* we implement dual role but not full featured OTG */</div><div class='add'>+	extcon = &lt;&amp;extcon_usbotg&gt;;</div><div class='add'>+	hnp-disable;</div><div class='add'>+	srp-disable;</div><div class='add'>+	adp-disable;</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy1 {</div><div class='add'>+	vbus-supply = &lt;&amp;reg_hub_vbus&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc3_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_ecspi1: ecspi1grp {</div><div class='add'>+		fsl,pins = &lt;MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK	0x0000004e&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI	0x0000004e&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO	0x0000004e&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9		0x0000004e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ecspi2: ecspi2grp {</div><div class='add'>+		fsl,pins = &lt;MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0x0000004e&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0x0000004e&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO	0x0000004e&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13		0x0000004e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_expander: expandergrp {</div><div class='add'>+		fsl,pins = &lt;MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9		0xd6&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec1: fec1grp {</div><div class='add'>+		fsl,pins = &lt;MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC		0x3&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO		0x23&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x1f&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x1f&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x1f&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x1f&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x91&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x91&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x91&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x91&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x1f&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x91&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpiobutton: gpiobuttongrp {</div><div class='add'>+		fsl,pins = &lt;MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5		0x41&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x41&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17		0x41&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpioled: gpioledgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0		0x41&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8		0x41&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16	0x41&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2: i2c2grp {</div><div class='add'>+		fsl,pins = &lt;MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL		0x40000067&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA		0x40000067&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c2_gpio: i2c2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16		0x40000067&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17		0x40000067&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3: i2c3grp {</div><div class='add'>+		fsl,pins = &lt;MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL		0x40000067&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA		0x40000067&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c3_gpio: i2c3gpiogrp {</div><div class='add'>+		fsl,pins = &lt;MX8MQ_IOMUXC_I2C3_SCL_GPIO5_IO18		0x40000067&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_I2C3_SDA_GPIO5_IO19		0x40000067&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm3: pwm3grp {</div><div class='add'>+		fsl,pins = &lt;MX8MQ_IOMUXC_GPIO1_IO14_PWM3_OUT		0x16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm4: pwm4grp {</div><div class='add'>+		fsl,pins = &lt;MX8MQ_IOMUXC_GPIO1_IO15_PWM4_OUT		0x16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_regotgvbus: reggotgvbusgrp {</div><div class='add'>+		/* USB1 OTG PWR as GPIO */</div><div class='add'>+		fsl,pins = &lt;MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12		0x06&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19		0xc1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai3: sai3grp {</div><div class='add'>+		fsl,pins = &lt;MX8MQ_IOMUXC_SAI3_MCLK_SAI3_MCLK		0xd6&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SAI3_RXC_SAI3_RX_BCLK		0xd6&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC		0xd6&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0		0xd6&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC		0xd6&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0		0xd6&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK		0xd6&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x79&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x79&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX		0x79&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX		0x79&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: uart3grp {</div><div class='add'>+		fsl,pins = &lt;MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX		0x79&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX		0x79&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart4: uart4grp {</div><div class='add'>+		fsl,pins = &lt;MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX		0x79&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX		0x79&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usbcon0: usb0congrp {</div><div class='add'>+		/* ID: floating / high: device, low: host -&gt; use PU */</div><div class='add'>+		fsl,pins = &lt;MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10		0xe6&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x83&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xc3&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0xc1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x85&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xc5&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc5&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc5&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc5&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc5&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0xc1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x9f&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xc7&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc7&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc7&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc7&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc7&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0xc1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2-gpiogrp {</div><div class='add'>+		fsl,pins = &lt;MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12		0x41&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi<br/>new file mode 100644<br/>index 000000000000..c92001c80f11<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi</a></div><div class='hunk'>@@ -0,0 +1,362 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2019-2021 TQ-Systems GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "imx8mq.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "TQ-Systems GmbH i.MX8MQ TQMa8MQ";</div><div class='add'>+	compatible = "tq,imx8mq-tqma8mq", "fsl,imx8mq";</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		/*  our minimum RAM config will be 1024 MiB */</div><div class='add'>+		reg = &lt;0x00000000 0x40000000 0 0x40000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* e-MMC IO, needed for HS modes */</div><div class='add'>+	reg_vcc1v8: regulator-vcc1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "TQMA8MX_VCC1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc3v3: regulator-vcc3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "TQMA8MX_VCC3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vdd_arm: regulator-vdd-arm {</div><div class='add'>+		compatible = "regulator-gpio";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_dvfs&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+		regulator-name = "TQMa8Mx_DVFS";</div><div class='add'>+		regulator-type = "voltage";</div><div class='add'>+		regulator-settling-time-us = &lt;150000&gt;;</div><div class='add'>+		gpios = &lt;&amp;gpio1 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		states = &lt;900000 0x1 1000000 0x0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		/* global autoconfigured region for contiguous allocations */</div><div class='add'>+		linux,cma {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reusable;</div><div class='add'>+			/* 640 MiB */</div><div class='add'>+			size = &lt;0 0x28000000&gt;;</div><div class='add'>+			/*  1024 - 128 MiB, our minimum RAM config will be 1024 MiB */</div><div class='add'>+			alloc-ranges = &lt;0 0x40000000 0 0x78000000&gt;;</div><div class='add'>+			linux,cma-default;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_0 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_vdd_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_1 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_vdd_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_2 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_vdd_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;A53_3 {</div><div class='add'>+	cpu-supply = &lt;&amp;reg_vdd_arm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pgc_gpu {</div><div class='add'>+	power-supply = &lt;&amp;sw1a_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pgc_vpu {</div><div class='add'>+	power-supply = &lt;&amp;sw1c_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c1_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pfuze100: pmic@8 {</div><div class='add'>+		compatible = "fsl,pfuze100";</div><div class='add'>+		fsl,pfuze-support-disable-sw;</div><div class='add'>+		reg = &lt;0x8&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			/* VDD_GPU */</div><div class='add'>+			sw1a_reg: sw1ab {</div><div class='add'>+				regulator-min-microvolt = &lt;825000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* VDD_VPU */</div><div class='add'>+			sw1c_reg: sw1c {</div><div class='add'>+				regulator-min-microvolt = &lt;825000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* NVCC_DRAM */</div><div class='add'>+			sw2_reg: sw2 {</div><div class='add'>+				regulator-min-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* VDD_DRAM */</div><div class='add'>+			sw3a_reg: sw3ab {</div><div class='add'>+				regulator-min-microvolt = &lt;825000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* 1.8 V for QSPI NOR, e-MMC IO, must not be changed */</div><div class='add'>+			nvcc_1v8_reg: sw4 {</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			swbst_reg: swbst {</div><div class='add'>+				regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;5150000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			snvs_reg: vsnvs {</div><div class='add'>+				regulator-min-microvolt = &lt;1000000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3000000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vref_reg: vrefddr {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* not used */</div><div class='add'>+			vgen1_reg: vgen1 {</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1550000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* VDD_PHY_0V9 */</div><div class='add'>+			vgen2_reg: vgen2 {</div><div class='add'>+				regulator-min-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;975000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* VDD_PHY_1V8 */</div><div class='add'>+			vgen3_reg: vgen3 {</div><div class='add'>+				regulator-min-microvolt = &lt;1675000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1975000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* VDDA_1V8 */</div><div class='add'>+			vgen4_reg: vgen4 {</div><div class='add'>+				regulator-min-microvolt = &lt;1625000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1875000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* VDD_PHY_3V3 */</div><div class='add'>+			vgen5_reg: vgen5 {</div><div class='add'>+				regulator-min-microvolt = &lt;3075000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3625000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* not used */</div><div class='add'>+			vgen6_reg: vgen6 {</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sensor0: temperature-sensor@1b {</div><div class='add'>+		compatible = "nxp,se97b", "jedec,jc-42.4-temp";</div><div class='add'>+		reg = &lt;0x1b&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcf85063: rtc@51 {</div><div class='add'>+		compatible = "nxp,pcf85063a";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_rtc&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;1 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		quartz-load-femtofarads = &lt;7000&gt;;</div><div class='add'>+</div><div class='add'>+		clock {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-frequency = &lt;32768&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom1: eeprom@53 {</div><div class='add'>+		compatible = "nxp,se97b", "atmel,24c02";</div><div class='add'>+		reg = &lt;0x53&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+		read-only;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_vcc3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom0: eeprom@57 {</div><div class='add'>+		compatible = "atmel,24c64";</div><div class='add'>+		reg = &lt;0x57&gt;;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_vcc3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	/* 3.3V supply, only way to switch on internal 1.8V supply using GPR */</div><div class='add'>+	vph-supply = &lt;&amp;vgen5_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie1 {</div><div class='add'>+	/* 3.3V supply, only way to switch on internal 1.8V supply using GPR */</div><div class='add'>+	vph-supply = &lt;&amp;vgen5_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qspi0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_qspi&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX8MQ_CLK_QSPI&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX8MQ_SYS1_PLL_266M&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash0: flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;84000000&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;1&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;nvcc_1v8_reg&gt;;</div><div class='add'>+</div><div class='add'>+		partitions {</div><div class='add'>+			compatible = "fixed-partitions";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1_200mhz&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	no-sd;</div><div class='add'>+	no-sdio;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_vcc3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_vcc1v8&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Attention: wdog reset forcing POR needs baseboard support */</div><div class='add'>+&amp;wdog1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_dvfs: dvfsgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6	0x16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL		0x4000007f&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA		0x4000007f&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1_gpio: i2c1gpiogrp {</div><div class='add'>+		fsl,pins = &lt;MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14		0x40000074&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15		0x40000074&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_qspi: qspigrp {</div><div class='add'>+		fsl,pins = &lt;MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK		0x97&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B	0x82&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0	0x97&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1	0x97&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2	0x97&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3	0x97&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_rtc: rtcgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1		0x41&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK		0x83&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD		0xc3&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE	0x83&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B	0xc1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK		0x85&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD		0xc5&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc5&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc5&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc5&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc5&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc5&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc5&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc5&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc5&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE	0x85&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B	0xc1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK		0x87&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD		0xc7&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc7&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc7&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc7&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc7&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc7&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc7&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc7&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc7&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE	0x87&gt;,</div><div class='add'>+			   &lt;MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B	0xc1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dts b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dts<br/>index 6b3581366d67..be1e7d6f0ecb 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dts</a></div><div class='hunk'>@@ -10,12 +10,62 @@</div><div class='ctx'> / {</div><div class='ctx'> 	model = "ZII Ultra RMB3 Board";</div><div class='ctx'> 	compatible = "zii,imx8mq-ultra-rmb3", "zii,imx8mq-ultra", "fsl,imx8mq";</div><div class='add'>+</div><div class='add'>+	sound1 {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,name = "front";</div><div class='add'>+		simple-audio-card,format = "i2s";</div><div class='add'>+		simple-audio-card,bitclock-master = &lt;&amp;sound1_codec&gt;;</div><div class='add'>+		simple-audio-card,frame-master = &lt;&amp;sound1_codec&gt;;</div><div class='add'>+		simple-audio-card,widgets =</div><div class='add'>+			"Headphone", "Headphone Jack Front";</div><div class='add'>+		simple-audio-card,routing =</div><div class='add'>+			"Headphone Jack Front", "HPA1 HPLEFT",</div><div class='add'>+			"Headphone Jack Front", "HPA1 HPRIGHT",</div><div class='add'>+			"HPA1 LEFTIN", "HPL",</div><div class='add'>+			"HPA1 RIGHTIN", "HPR";</div><div class='add'>+		simple-audio-card,aux-devs = &lt;&amp;hpa1&gt;;</div><div class='add'>+</div><div class='add'>+		sound1_cpu: simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;sai2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sound1_codec: simple-audio-card,codec {</div><div class='add'>+			sound-dai = &lt;&amp;codec1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cs2000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound2 {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,name = "periph";</div><div class='add'>+		simple-audio-card,format = "i2s";</div><div class='add'>+		simple-audio-card,bitclock-master = &lt;&amp;sound2_codec&gt;;</div><div class='add'>+		simple-audio-card,frame-master = &lt;&amp;sound2_codec&gt;;</div><div class='add'>+		simple-audio-card,widgets =</div><div class='add'>+			"Headphone", "Headphone Jack Back";</div><div class='add'>+		simple-audio-card,routing =</div><div class='add'>+			"Headphone Jack Back", "HPA1 HPLEFT",</div><div class='add'>+			"Headphone Jack Back", "HPA1 HPRIGHT",</div><div class='add'>+			"HPA1 LEFTIN", "HPL",</div><div class='add'>+			"HPA1 RIGHTIN", "HPR";</div><div class='add'>+		simple-audio-card,aux-devs = &lt;&amp;hpa2&gt;;</div><div class='add'>+</div><div class='add'>+		sound2_cpu: simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;sai3&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sound2_codec: simple-audio-card,codec {</div><div class='add'>+			sound-dai = &lt;&amp;codec2&gt;;</div><div class='add'>+			clocks = &lt;&amp;cs2000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;ecspi1 {</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pinctrl_ecspi1&gt;;</div><div class='del'>-	cs-gpios = &lt;&amp;gpio5 9 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 9 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> 	#address-cells = &lt;1&gt;;</div><div class='ctx'> 	#size-cells = &lt;0&gt;;</div><div class='hunk'>@@ -27,6 +77,27 @@</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;hpa2 {</div><div class='add'>+	sound-name-prefix = "HPA1";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	codec2: codec@18 {</div><div class='add'>+		compatible = "ti,tlv320dac3100";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_codec2&gt;;</div><div class='add'>+		reg = &lt;0x18&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		HPVDD-supply = &lt;&amp;reg_gen_3p3&gt;;</div><div class='add'>+		SPRVDD-supply = &lt;&amp;reg_gen_3p3&gt;;</div><div class='add'>+		SPLVDD-supply = &lt;&amp;reg_gen_3p3&gt;;</div><div class='add'>+		AVDD-supply = &lt;&amp;reg_gen_3p3&gt;;</div><div class='add'>+		IOVDD-supply = &lt;&amp;reg_gen_3p3&gt;;</div><div class='add'>+		DVDD-supply = &lt;&amp;vgen4_reg&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio3 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;i2c2 {</div><div class='ctx'> 	temp-sense@48 {</div><div class='ctx'> 		compatible = "national,lm75";</div><div class='hunk'>@@ -56,6 +127,8 @@</div><div class='ctx'> 			touchscreen-inverted-x;</div><div class='ctx'> 			touchscreen-swapped-x-y;</div><div class='ctx'> 			syna,sensor-type = &lt;1&gt;;</div><div class='add'>+			syna,delta-x-threshold = &lt;5&gt;;</div><div class='add'>+			syna,delta-y-threshold = &lt;10&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		rmi4-f12@12 {</div><div class='hunk'>@@ -79,11 +152,23 @@</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;sai3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;usbhub {</div><div class='ctx'> 	swap-dx-lanes = &lt;0&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;iomuxc {</div><div class='add'>+	pinctrl_codec2: dac2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4		0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	pinctrl_ecspi1: ecspi1grp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9	0x19</div><div class='hunk'>@@ -92,4 +177,12 @@</div><div class='ctx'> 			MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI	0x82</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai3: sai3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC		0xd6</div><div class='add'>+			MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK		0xd6</div><div class='add'>+			MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0		0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-zest.dts b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-zest.dts<br/>index 173b9e9b2bbd..f6130167a1c7 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-zest.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-zest.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-zest.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-zest.dts</a></div><div class='hunk'>@@ -10,6 +10,36 @@</div><div class='ctx'> / {</div><div class='ctx'> 	model = "ZII Ultra Zest Board";</div><div class='ctx'> 	compatible = "zii,imx8mq-ultra-zest", "zii,imx8mq-ultra", "fsl,imx8mq";</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,name = "front";</div><div class='add'>+		simple-audio-card,format = "i2s";</div><div class='add'>+		simple-audio-card,bitclock-master = &lt;&amp;sound_codec&gt;;</div><div class='add'>+		simple-audio-card,frame-master = &lt;&amp;sound_codec&gt;;</div><div class='add'>+		simple-audio-card,widgets =</div><div class='add'>+			"Headphone", "Headphone Jack Front",</div><div class='add'>+			"Headphone", "Headphone Jack Back";</div><div class='add'>+		simple-audio-card,routing =</div><div class='add'>+			"Headphone Jack Front", "HPA1 HPLEFT",</div><div class='add'>+			"Headphone Jack Front", "HPA1 HPRIGHT",</div><div class='add'>+			"Headphone Jack Back", "HPA2 HPLEFT",</div><div class='add'>+			"Headphone Jack Back", "HPA2 HPRIGHT",</div><div class='add'>+			"HPA1 LEFTIN", "HPL",</div><div class='add'>+			"HPA1 RIGHTIN", "HPR",</div><div class='add'>+			"HPA2 LEFTIN", "HPL",</div><div class='add'>+			"HPA2 RIGHTIN", "HPR";</div><div class='add'>+		simple-audio-card,aux-devs = &lt;&amp;hpa1&gt;, &lt;&amp;hpa2&gt;;</div><div class='add'>+</div><div class='add'>+		sound_cpu: simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;sai2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sound_codec: simple-audio-card,codec {</div><div class='add'>+			sound-dai = &lt;&amp;codec1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cs2000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;i2c4 {</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi<br/>index 6a55165bd76a..c7bbba45f368 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi</a></div><div class='hunk'>@@ -15,7 +15,7 @@</div><div class='ctx'> 		stdout-path = &amp;uart1;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	mdio0: bitbang-mdio {</div><div class='add'>+	mdio0: mdio {</div><div class='ctx'> 		compatible = "virtual,mdio-gpio";</div><div class='ctx'> 		pinctrl-names = "default";</div><div class='ctx'> 		pinctrl-0 = &lt;&amp;pinctrl_mdio_bitbang&gt;, &lt;&amp;pinctrl_fec1_phy_reset&gt;;</div><div class='hunk'>@@ -45,8 +45,8 @@</div><div class='ctx'> 	reg_12p0_main: regulator-12p0-main {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "12V_MAIN";</div><div class='del'>-		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;12000000&gt;;</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -102,6 +102,18 @@</div><div class='ctx'> 		           900000 0x0&gt;;</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	cs2000_ref: cs2000-ref {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;24576000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cs2000_in_dummy: cs2000-in-dummy {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;0&gt;;</div><div class='add'>+	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;A53_0 {</div><div class='hunk'>@@ -131,6 +143,8 @@</div><div class='ctx'> 	mdio {</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;12500000&gt;;</div><div class='add'>+		suppress-preamble;</div><div class='ctx'> 		status = "okay";</div><div class='ctx'> </div><div class='ctx'> 		switch: switch@0 {</div><div class='hunk'>@@ -163,7 +177,7 @@</div><div class='ctx'> </div><div class='ctx'> 				port@2 {</div><div class='ctx'> 					reg = &lt;2&gt;;</div><div class='del'>-					label = "cpu";</div><div class='add'>+					phy-mode = "rev-rmii";</div><div class='ctx'> 					ethernet = &lt;&amp;fec1&gt;;</div><div class='ctx'> </div><div class='ctx'> 					fixed-link {</div><div class='hunk'>@@ -227,28 +241,28 @@</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pinctrl_gpio3_hog&gt;;</div><div class='ctx'> </div><div class='del'>-	usb-emulation {</div><div class='add'>+	usb-emulation-hog {</div><div class='ctx'> 		gpio-hog;</div><div class='ctx'> 		gpios = &lt;10 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 		output-low;</div><div class='ctx'> 		line-name = "usb-emulation";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	usb-mode1 {</div><div class='add'>+	usb-mode1-hog {</div><div class='ctx'> 		gpio-hog;</div><div class='ctx'> 		gpios = &lt;11 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 		output-high;</div><div class='ctx'> 		line-name = "usb-mode1";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	usb-pwr {</div><div class='add'>+	usb-pwr-hog {</div><div class='ctx'> 		gpio-hog;</div><div class='ctx'> 		gpios = &lt;12 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 		output-high;</div><div class='ctx'> 		line-name = "usb-pwr-ctrl-en-n";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	usb-mode2 {</div><div class='add'>+	usb-mode2-hog {</div><div class='ctx'> 		gpio-hog;</div><div class='ctx'> 		gpios = &lt;13 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 		output-high;</div><div class='hunk'>@@ -281,9 +295,19 @@</div><div class='ctx'> 		reg = &lt;0x32&gt;;</div><div class='ctx'> 		interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='ctx'> 		interrupts = &lt;17 IRQ_TYPE_EDGE_BOTH&gt;,</div><div class='del'>-		             &lt;18 IRQ_TYPE_EDGE_BOTH&gt;;</div><div class='add'>+		             &lt;18 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='ctx'> 		interrupt-names = "a_det", "alert";</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	hpa2: amp@60 {</div><div class='add'>+		compatible = "ti,tpa6130a2";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_tpa2&gt;;</div><div class='add'>+		reg = &lt;0x60&gt;;</div><div class='add'>+		power-gpio = &lt;&amp;gpio1 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		Vdd-supply = &lt;&amp;reg_5p0_main&gt;;</div><div class='add'>+		sound-name-prefix = "HPA2";</div><div class='add'>+	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;i2c2 {</div><div class='hunk'>@@ -376,11 +400,36 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	codec1: codec@18 {</div><div class='add'>+		compatible = "ti,tlv320dac3100";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_codec1&gt;;</div><div class='add'>+		reg = &lt;0x18&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		HPVDD-supply = &lt;&amp;reg_gen_3p3&gt;;</div><div class='add'>+		SPRVDD-supply = &lt;&amp;reg_gen_3p3&gt;;</div><div class='add'>+		SPLVDD-supply = &lt;&amp;reg_gen_3p3&gt;;</div><div class='add'>+		AVDD-supply = &lt;&amp;reg_gen_3p3&gt;;</div><div class='add'>+		IOVDD-supply = &lt;&amp;reg_gen_3p3&gt;;</div><div class='add'>+		DVDD-supply = &lt;&amp;vgen4_reg&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio3 3 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	eeprom@54 {</div><div class='ctx'> 		compatible = "atmel,24c128";</div><div class='ctx'> 		reg = &lt;0x54&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	hpa1: amp@60 {</div><div class='add'>+		compatible = "ti,tpa6130a2";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_tpa1&gt;;</div><div class='add'>+		reg = &lt;0x60&gt;;</div><div class='add'>+		power-gpio = &lt;&amp;gpio4 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		Vdd-supply = &lt;&amp;reg_5p0_main&gt;;</div><div class='add'>+		sound-name-prefix = "HPA1";</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	ds1341: rtc@68 {</div><div class='ctx'> 		compatible = "dallas,ds1341";</div><div class='ctx'> 		reg = &lt;0x68&gt;;</div><div class='hunk'>@@ -394,7 +443,7 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='ctx'> 	usbhub: usbhub@2c {</div><div class='del'>-		compatible ="microchip,usb2513b";</div><div class='add'>+		compatible = "microchip,usb2513b";</div><div class='ctx'> 		pinctrl-names = "default";</div><div class='ctx'> 		pinctrl-0 = &lt;&amp;pinctrl_usbhub&gt;;</div><div class='ctx'> 		reg = &lt;0x2c&gt;;</div><div class='hunk'>@@ -405,6 +454,16 @@</div><div class='ctx'> 		compatible = "zii,rave-wdt";</div><div class='ctx'> 		reg = &lt;0x38&gt;;</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	cs2000: clkgen@4e {</div><div class='add'>+		compatible = "cirrus,cs2000-cp";</div><div class='add'>+		reg = &lt;0x4e&gt;;</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-names = "clk_in", "ref_clk";</div><div class='add'>+		clocks = &lt;&amp;cs2000_in_dummy&gt;, &lt;&amp;cs2000_ref&gt;;</div><div class='add'>+		assigned-clocks = &lt;&amp;cs2000&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;24000000&gt;;</div><div class='add'>+	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;i2c4 {</div><div class='hunk'>@@ -414,6 +473,12 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;sai2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;uart1 {</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='hunk'>@@ -425,7 +490,7 @@</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='del'>-	rave-sp {</div><div class='add'>+	mcu {</div><div class='ctx'> 		compatible = "zii,rave-sp-rdu2";</div><div class='ctx'> 		current-speed = &lt;1000000&gt;;</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='hunk'>@@ -452,8 +517,6 @@</div><div class='ctx'> 		eeprom@a4 {</div><div class='ctx'> 			compatible = "zii,rave-sp-eeprom";</div><div class='ctx'> 			reg = &lt;0xa4 0x4000&gt;;</div><div class='del'>-			#address-cells = &lt;1&gt;;</div><div class='del'>-			#size-cells = &lt;1&gt;;</div><div class='ctx'> 			zii,eeprom-name = "main-eeprom";</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='hunk'>@@ -466,6 +529,7 @@</div><div class='ctx'> </div><div class='ctx'> &amp;usb_dwc3_0 {</div><div class='ctx'> 	dr_mode = "host";</div><div class='add'>+	maximum-speed = "high-speed";</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -476,6 +540,7 @@</div><div class='ctx'> </div><div class='ctx'> &amp;usb_dwc3_1 {</div><div class='ctx'> 	dr_mode = "host";</div><div class='add'>+	maximum-speed = "high-speed";</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -484,10 +549,10 @@</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pinctrl_pcie0&gt;;</div><div class='ctx'> 	reset-gpio = &lt;&amp;gpio1 3 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 	clocks = &lt;&amp;clk IMX8MQ_CLK_PCIE1_ROOT&gt;,</div><div class='del'>-	         &lt;&amp;clk IMX8MQ_CLK_PCIE1_AUX&gt;,</div><div class='add'>+	         &lt;&amp;pcie0_refclk&gt;,</div><div class='ctx'> 	         &lt;&amp;clk IMX8MQ_CLK_PCIE1_PHY&gt;,</div><div class='del'>-	         &lt;&amp;pcie0_refclk&gt;;</div><div class='del'>-	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";</div><div class='add'>+	         &lt;&amp;clk IMX8MQ_CLK_PCIE1_AUX&gt;;</div><div class='add'>+	vph-supply = &lt;&amp;vgen5_reg&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -496,10 +561,10 @@</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pinctrl_pcie1&gt;;</div><div class='ctx'> 	reset-gpio = &lt;&amp;gpio1 6 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 	clocks = &lt;&amp;clk IMX8MQ_CLK_PCIE2_ROOT&gt;,</div><div class='del'>-	         &lt;&amp;clk IMX8MQ_CLK_PCIE2_AUX&gt;,</div><div class='add'>+	         &lt;&amp;pcie1_refclk&gt;,</div><div class='ctx'> 	         &lt;&amp;clk IMX8MQ_CLK_PCIE2_PHY&gt;,</div><div class='del'>-	         &lt;&amp;pcie1_refclk&gt;;</div><div class='del'>-	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";</div><div class='add'>+	         &lt;&amp;clk IMX8MQ_CLK_PCIE2_AUX&gt;;</div><div class='add'>+	vph-supply = &lt;&amp;vgen5_reg&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -549,6 +614,12 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	pinctrl_codec1: dac1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3		0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	pinctrl_fec1: fec1grp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC			0x3</div><div class='hunk'>@@ -581,29 +652,29 @@</div><div class='ctx'> </div><div class='ctx'> 	pinctrl_i2c1: i2c1grp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='del'>-			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL			0x4000007f</div><div class='del'>-			MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA			0x4000007f</div><div class='add'>+			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL			0x40000022</div><div class='add'>+			MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA			0x400000a2</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	pinctrl_i2c2: i2c2grp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='del'>-			MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL			0x4000007f</div><div class='del'>-			MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA			0x4000007f</div><div class='add'>+			MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL			0x40000022</div><div class='add'>+			MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA			0x400000a2</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	pinctrl_i2c3: i2c3grp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='del'>-			MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL			0x4000007f</div><div class='del'>-			MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA			0x4000007f</div><div class='add'>+			MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL			0x40000022</div><div class='add'>+			MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA			0x400000a2</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	pinctrl_i2c4: i2c4grp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='del'>-			MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL			0x4000007f</div><div class='del'>-			MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA			0x4000007f</div><div class='add'>+			MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL			0x40000022</div><div class='add'>+			MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA			0x400000a2</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -640,12 +711,32 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	pinctrl_sai2: sai2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC		0xd6</div><div class='add'>+			MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK		0xd6</div><div class='add'>+			MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0		0xd6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	pinctrl_switch_irq: switchgrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15		0x41</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	pinctrl_tpa1: tpa6130-1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_SAI1_TXFS_GPIO4_IO10		0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_tpa2: tpa6130-2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8		0x41</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	pinctrl_ts: tsgrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x96</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi<br/>index 75b384217a23..607962f807be 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mq.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8mq.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8mq.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8mq.dtsi</a></div><div class='hunk'>@@ -11,6 +11,7 @@</div><div class='ctx'> #include "dt-bindings/input/input.h"</div><div class='ctx'> #include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/thermal/thermal.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interconnect/imx8mq.h&gt;</div><div class='ctx'> #include "imx8mq-pinfunc.h"</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='hunk'>@@ -20,6 +21,7 @@</div><div class='ctx'> 	#size-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='ctx'> 	aliases {</div><div class='add'>+		ethernet0 = &amp;fec1;</div><div class='ctx'> 		gpio0 = &amp;gpio1;</div><div class='ctx'> 		gpio1 = &amp;gpio2;</div><div class='ctx'> 		gpio2 = &amp;gpio3;</div><div class='hunk'>@@ -29,6 +31,8 @@</div><div class='ctx'> 		i2c1 = &amp;i2c2;</div><div class='ctx'> 		i2c2 = &amp;i2c3;</div><div class='ctx'> 		i2c3 = &amp;i2c4;</div><div class='add'>+		mmc0 = &amp;usdhc1;</div><div class='add'>+		mmc1 = &amp;usdhc2;</div><div class='ctx'> 		serial0 = &amp;uart1;</div><div class='ctx'> 		serial1 = &amp;uart2;</div><div class='ctx'> 		serial2 = &amp;uart3;</div><div class='hunk'>@@ -59,6 +63,13 @@</div><div class='ctx'> 		clock-output-names = "osc_27m";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	hdmi_phy_27m: clock-hdmi-phy-27m {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;27000000&gt;;</div><div class='add'>+		clock-output-names = "hdmi_phy_27m";</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	clk_ext1: clock-ext1 {</div><div class='ctx'> 		compatible = "fixed-clock";</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='hunk'>@@ -83,7 +94,7 @@</div><div class='ctx'> 	clk_ext4: clock-ext4 {</div><div class='ctx'> 		compatible = "fixed-clock";</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='del'>-		clock-frequency= &lt;133000000&gt;;</div><div class='add'>+		clock-frequency = &lt;133000000&gt;;</div><div class='ctx'> 		clock-output-names = "clk_ext4";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -95,9 +106,14 @@</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			reg = &lt;0x0&gt;;</div><div class='del'>-			clock-latency = &lt;61036&gt;; /* two CLK32 periods */</div><div class='ctx'> 			clocks = &lt;&amp;clk IMX8MQ_CLK_ARM&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;A53_L2&gt;;</div><div class='ctx'> 			operating-points-v2 = &lt;&amp;a53_opp_table&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='hunk'>@@ -109,9 +125,14 @@</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			reg = &lt;0x1&gt;;</div><div class='del'>-			clock-latency = &lt;61036&gt;; /* two CLK32 periods */</div><div class='ctx'> 			clocks = &lt;&amp;clk IMX8MQ_CLK_ARM&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;A53_L2&gt;;</div><div class='ctx'> 			operating-points-v2 = &lt;&amp;a53_opp_table&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='hunk'>@@ -121,9 +142,14 @@</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			reg = &lt;0x2&gt;;</div><div class='del'>-			clock-latency = &lt;61036&gt;; /* two CLK32 periods */</div><div class='ctx'> 			clocks = &lt;&amp;clk IMX8MQ_CLK_ARM&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;A53_L2&gt;;</div><div class='ctx'> 			operating-points-v2 = &lt;&amp;a53_opp_table&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='hunk'>@@ -133,9 +159,14 @@</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			reg = &lt;0x3&gt;;</div><div class='del'>-			clock-latency = &lt;61036&gt;; /* two CLK32 periods */</div><div class='ctx'> 			clocks = &lt;&amp;clk IMX8MQ_CLK_ARM&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;A53_L2&gt;;</div><div class='ctx'> 			operating-points-v2 = &lt;&amp;a53_opp_table&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='hunk'>@@ -143,6 +174,11 @@</div><div class='ctx'> </div><div class='ctx'> 		A53_L2: l2-cache0 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x100000&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;1024&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -185,11 +221,63 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	funnel {</div><div class='add'>+		/*</div><div class='add'>+		 * non-configurable funnel don't show up on the AMBA</div><div class='add'>+		 * bus.  As such no need to add "arm,primecell".</div><div class='add'>+		 */</div><div class='add'>+		compatible = "arm,coresight-static-funnel";</div><div class='add'>+</div><div class='add'>+		in-ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				ca_funnel_in_port0: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;etm0_out_port&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				ca_funnel_in_port1: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;etm1_out_port&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@2 {</div><div class='add'>+				reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+				ca_funnel_in_port2: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;etm2_out_port&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@3 {</div><div class='add'>+				reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+				ca_funnel_in_port3: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;etm3_out_port&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		out-ports {</div><div class='add'>+			port {</div><div class='add'>+				ca_funnel_out_port0: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;hugo_funnel_in_port0&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	pmu {</div><div class='ctx'> 		compatible = "arm,cortex-a53-pmu";</div><div class='ctx'> 		interrupts = &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='del'>-		interrupt-affinity = &lt;&amp;A53_0&gt;, &lt;&amp;A53_1&gt;, &lt;&amp;A53_2&gt;, &lt;&amp;A53_3&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	psci {</div><div class='hunk'>@@ -282,16 +370,157 @@</div><div class='ctx'> 		arm,no-tick-in-suspend;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	soc@0 {</div><div class='del'>-		compatible = "simple-bus";</div><div class='add'>+	soc: soc@0 {</div><div class='add'>+		compatible = "fsl,imx8mq-soc", "simple-bus";</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;1&gt;;</div><div class='ctx'> 		ranges = &lt;0x0 0x0 0x0 0x3e000000&gt;;</div><div class='ctx'> 		dma-ranges = &lt;0x40000000 0x0 0x40000000 0xc0000000&gt;;</div><div class='add'>+		nvmem-cells = &lt;&amp;imx8mq_uid&gt;;</div><div class='add'>+		nvmem-cell-names = "soc_unique_id";</div><div class='add'>+</div><div class='add'>+		etm0: etm@28440000 {</div><div class='add'>+			compatible = "arm,coresight-etm4x", "arm,primecell";</div><div class='add'>+			reg = &lt;0x28440000 0x1000&gt;;</div><div class='add'>+			cpu = &lt;&amp;A53_0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MQ_CLK_MAIN_AXI&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					etm0_out_port: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ca_funnel_in_port0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		etm1: etm@28540000 {</div><div class='add'>+			compatible = "arm,coresight-etm4x", "arm,primecell";</div><div class='add'>+			reg = &lt;0x28540000 0x1000&gt;;</div><div class='add'>+			cpu = &lt;&amp;A53_1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MQ_CLK_MAIN_AXI&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					etm1_out_port: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ca_funnel_in_port1&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		etm2: etm@28640000 {</div><div class='add'>+			compatible = "arm,coresight-etm4x", "arm,primecell";</div><div class='add'>+			reg = &lt;0x28640000 0x1000&gt;;</div><div class='add'>+			cpu = &lt;&amp;A53_2&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MQ_CLK_MAIN_AXI&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					etm2_out_port: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ca_funnel_in_port2&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		etm3: etm@28740000 {</div><div class='add'>+			compatible = "arm,coresight-etm4x", "arm,primecell";</div><div class='add'>+			reg = &lt;0x28740000 0x1000&gt;;</div><div class='add'>+			cpu = &lt;&amp;A53_3&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MQ_CLK_MAIN_AXI&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					etm3_out_port: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ca_funnel_in_port3&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='ctx'> </div><div class='del'>-		bus@30000000 { /* AIPS1 */</div><div class='add'>+		funnel@28c03000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";</div><div class='add'>+			reg = &lt;0x28c03000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MQ_CLK_MAIN_AXI&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					hugo_funnel_in_port0: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ca_funnel_out_port0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					hugo_funnel_in_port1: endpoint {</div><div class='add'>+					/* M4 input */</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+				/* the other input ports are not connect to anything */</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					hugo_funnel_out_port0: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;etf_in_port&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		etf@28c04000 {</div><div class='add'>+			compatible = "arm,coresight-tmc", "arm,primecell";</div><div class='add'>+			reg = &lt;0x28c04000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MQ_CLK_MAIN_AXI&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				port {</div><div class='add'>+					etf_in_port: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;hugo_funnel_out_port0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					etf_out_port: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;etr_in_port&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		etr@28c06000 {</div><div class='add'>+			compatible = "arm,coresight-tmc", "arm,primecell";</div><div class='add'>+			reg = &lt;0x28c06000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MQ_CLK_MAIN_AXI&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				port {</div><div class='add'>+					etr_in_port: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;etf_out_port&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aips1: bus@30000000 { /* AIPS1 */</div><div class='ctx'> 			compatible = "fsl,aips-bus", "simple-bus";</div><div class='del'>-			reg = &lt;0x301f0000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x30000000 0x400000&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;1&gt;;</div><div class='ctx'> 			ranges = &lt;0x30000000 0x30000000 0x400000&gt;;</div><div class='hunk'>@@ -420,54 +649,54 @@</div><div class='ctx'> 			tmu: tmu@30260000 {</div><div class='ctx'> 				compatible = "fsl,imx8mq-tmu";</div><div class='ctx'> 				reg = &lt;0x30260000 0x10000&gt;;</div><div class='del'>-				interrupt = &lt;GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;clk IMX8MQ_CLK_TMU_ROOT&gt;;</div><div class='ctx'> 				little-endian;</div><div class='ctx'> 				fsl,tmu-range = &lt;0xb0000 0xa0026 0x80048 0x70061&gt;;</div><div class='del'>-				fsl,tmu-calibration = &lt;0x00000000 0x00000023</div><div class='del'>-						       0x00000001 0x00000029</div><div class='del'>-						       0x00000002 0x0000002f</div><div class='del'>-						       0x00000003 0x00000035</div><div class='del'>-						       0x00000004 0x0000003d</div><div class='del'>-						       0x00000005 0x00000043</div><div class='del'>-						       0x00000006 0x0000004b</div><div class='del'>-						       0x00000007 0x00000051</div><div class='del'>-						       0x00000008 0x00000057</div><div class='del'>-						       0x00000009 0x0000005f</div><div class='del'>-						       0x0000000a 0x00000067</div><div class='del'>-						       0x0000000b 0x0000006f</div><div class='del'>-</div><div class='del'>-						       0x00010000 0x0000001b</div><div class='del'>-						       0x00010001 0x00000023</div><div class='del'>-						       0x00010002 0x0000002b</div><div class='del'>-						       0x00010003 0x00000033</div><div class='del'>-						       0x00010004 0x0000003b</div><div class='del'>-						       0x00010005 0x00000043</div><div class='del'>-						       0x00010006 0x0000004b</div><div class='del'>-						       0x00010007 0x00000055</div><div class='del'>-						       0x00010008 0x0000005d</div><div class='del'>-						       0x00010009 0x00000067</div><div class='del'>-						       0x0001000a 0x00000070</div><div class='del'>-</div><div class='del'>-						       0x00020000 0x00000017</div><div class='del'>-						       0x00020001 0x00000023</div><div class='del'>-						       0x00020002 0x0000002d</div><div class='del'>-						       0x00020003 0x00000037</div><div class='del'>-						       0x00020004 0x00000041</div><div class='del'>-						       0x00020005 0x0000004b</div><div class='del'>-						       0x00020006 0x00000057</div><div class='del'>-						       0x00020007 0x00000063</div><div class='del'>-						       0x00020008 0x0000006f</div><div class='del'>-</div><div class='del'>-						       0x00030000 0x00000015</div><div class='del'>-						       0x00030001 0x00000021</div><div class='del'>-						       0x00030002 0x0000002d</div><div class='del'>-						       0x00030003 0x00000039</div><div class='del'>-						       0x00030004 0x00000045</div><div class='del'>-						       0x00030005 0x00000053</div><div class='del'>-						       0x00030006 0x0000005f</div><div class='del'>-						       0x00030007 0x00000071&gt;;</div><div class='del'>-				#thermal-sensor-cells =  &lt;1&gt;;</div><div class='add'>+				fsl,tmu-calibration = &lt;0x00000000 0x00000023&gt;,</div><div class='add'>+						      &lt;0x00000001 0x00000029&gt;,</div><div class='add'>+						      &lt;0x00000002 0x0000002f&gt;,</div><div class='add'>+						      &lt;0x00000003 0x00000035&gt;,</div><div class='add'>+						      &lt;0x00000004 0x0000003d&gt;,</div><div class='add'>+						      &lt;0x00000005 0x00000043&gt;,</div><div class='add'>+						      &lt;0x00000006 0x0000004b&gt;,</div><div class='add'>+						      &lt;0x00000007 0x00000051&gt;,</div><div class='add'>+						      &lt;0x00000008 0x00000057&gt;,</div><div class='add'>+						      &lt;0x00000009 0x0000005f&gt;,</div><div class='add'>+						      &lt;0x0000000a 0x00000067&gt;,</div><div class='add'>+						      &lt;0x0000000b 0x0000006f&gt;,</div><div class='add'>+</div><div class='add'>+						      &lt;0x00010000 0x0000001b&gt;,</div><div class='add'>+						      &lt;0x00010001 0x00000023&gt;,</div><div class='add'>+						      &lt;0x00010002 0x0000002b&gt;,</div><div class='add'>+						      &lt;0x00010003 0x00000033&gt;,</div><div class='add'>+						      &lt;0x00010004 0x0000003b&gt;,</div><div class='add'>+						      &lt;0x00010005 0x00000043&gt;,</div><div class='add'>+						      &lt;0x00010006 0x0000004b&gt;,</div><div class='add'>+						      &lt;0x00010007 0x00000055&gt;,</div><div class='add'>+						      &lt;0x00010008 0x0000005d&gt;,</div><div class='add'>+						      &lt;0x00010009 0x00000067&gt;,</div><div class='add'>+						      &lt;0x0001000a 0x00000070&gt;,</div><div class='add'>+</div><div class='add'>+						      &lt;0x00020000 0x00000017&gt;,</div><div class='add'>+						      &lt;0x00020001 0x00000023&gt;,</div><div class='add'>+						      &lt;0x00020002 0x0000002d&gt;,</div><div class='add'>+						      &lt;0x00020003 0x00000037&gt;,</div><div class='add'>+						      &lt;0x00020004 0x00000041&gt;,</div><div class='add'>+						      &lt;0x00020005 0x0000004b&gt;,</div><div class='add'>+						      &lt;0x00020006 0x00000057&gt;,</div><div class='add'>+						      &lt;0x00020007 0x00000063&gt;,</div><div class='add'>+						      &lt;0x00020008 0x0000006f&gt;,</div><div class='add'>+</div><div class='add'>+						      &lt;0x00030000 0x00000015&gt;,</div><div class='add'>+						      &lt;0x00030001 0x00000021&gt;,</div><div class='add'>+						      &lt;0x00030002 0x0000002d&gt;,</div><div class='add'>+						      &lt;0x00030003 0x00000039&gt;,</div><div class='add'>+						      &lt;0x00030004 0x00000045&gt;,</div><div class='add'>+						      &lt;0x00030005 0x00000053&gt;,</div><div class='add'>+						      &lt;0x00030006 0x0000005f&gt;,</div><div class='add'>+						      &lt;0x00030007 0x00000071&gt;;</div><div class='add'>+				#thermal-sensor-cells = &lt;1&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			wdog1: watchdog@30280000 {</div><div class='hunk'>@@ -494,7 +723,7 @@</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			sdma2: sdma@302c0000 {</div><div class='add'>+			sdma2: dma-controller@302c0000 {</div><div class='ctx'> 				compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";</div><div class='ctx'> 				reg = &lt;0x302c0000 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='hunk'>@@ -506,11 +735,13 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			lcdif: lcd-controller@30320000 {</div><div class='del'>-				compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif";</div><div class='add'>+				compatible = "fsl,imx8mq-lcdif", "fsl,imx6sx-lcdif";</div><div class='ctx'> 				reg = &lt;0x30320000 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-				clocks = &lt;&amp;clk IMX8MQ_CLK_LCDIF_PIXEL&gt;;</div><div class='del'>-				clock-names = "pix";</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MQ_CLK_LCDIF_PIXEL&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MQ_CLK_DISP_APB_ROOT&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MQ_CLK_DISP_AXI_ROOT&gt;;</div><div class='add'>+				clock-names = "pix", "axi", "disp_axi";</div><div class='ctx'> 				assigned-clocks = &lt;&amp;clk IMX8MQ_VIDEO_PLL1_REF_SEL&gt;,</div><div class='ctx'> 						  &lt;&amp;clk IMX8MQ_VIDEO_PLL1_BYPASS&gt;,</div><div class='ctx'> 						  &lt;&amp;clk IMX8MQ_CLK_LCDIF_PIXEL&gt;,</div><div class='hunk'>@@ -520,6 +751,12 @@</div><div class='ctx'> 						  &lt;&amp;clk IMX8MQ_VIDEO_PLL1_OUT&gt;;</div><div class='ctx'> 				assigned-clock-rates = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;, &lt;594000000&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='add'>+</div><div class='add'>+				port {</div><div class='add'>+					lcdif_mipi_dsi: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mipi_dsi_lcdif_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			iomuxc: pinctrl@30330000 {</div><div class='hunk'>@@ -528,8 +765,7 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			iomuxc_gpr: syscon@30340000 {</div><div class='del'>-				compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr",</div><div class='del'>-					     "syscon", "simple-mfd";</div><div class='add'>+				compatible = "fsl,imx8mq-iomuxc-gpr", "syscon", "simple-mfd";</div><div class='ctx'> 				reg = &lt;0x30340000 0x10000&gt;;</div><div class='ctx'> </div><div class='ctx'> 				mux: mux-controller {</div><div class='hunk'>@@ -539,31 +775,53 @@</div><div class='ctx'> 				};</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			ocotp: ocotp-ctrl@30350000 {</div><div class='add'>+			ocotp: efuse@30350000 {</div><div class='ctx'> 				compatible = "fsl,imx8mq-ocotp", "syscon";</div><div class='ctx'> 				reg = &lt;0x30350000 0x10000&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;clk IMX8MQ_CLK_OCOTP_ROOT&gt;;</div><div class='ctx'> 				#address-cells = &lt;1&gt;;</div><div class='ctx'> 				#size-cells = &lt;1&gt;;</div><div class='ctx'> </div><div class='del'>-				cpu_speed_grade: speed-grade@10 {</div><div class='add'>+				/*</div><div class='add'>+				 * The register address below maps to the MX8M</div><div class='add'>+				 * Fusemap Description Table entries this way.</div><div class='add'>+				 * Assuming</div><div class='add'>+				 *   reg = &lt;ADDR SIZE&gt;;</div><div class='add'>+				 * then</div><div class='add'>+				 *   Fuse Address = (ADDR * 4) + 0x400</div><div class='add'>+				 * Note that if SIZE is greater than 4, then</div><div class='add'>+				 * each subsequent fuse is located at offset</div><div class='add'>+				 * +0x10 in Fusemap Description Table (e.g.</div><div class='add'>+				 * reg = &lt;0x4 0x8&gt; describes fuses 0x410 and</div><div class='add'>+				 * 0x420).</div><div class='add'>+				 */</div><div class='add'>+				imx8mq_uid: soc-uid@4 { /* 0x410-0x420 */</div><div class='add'>+					reg = &lt;0x4 0x8&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_speed_grade: speed-grade@10 { /* 0x440 */</div><div class='ctx'> 					reg = &lt;0x10 4&gt;;</div><div class='ctx'> 				};</div><div class='add'>+</div><div class='add'>+				fec_mac_address: mac-address@90 { /* 0x640 */</div><div class='add'>+					reg = &lt;0x90 6&gt;;</div><div class='add'>+				};</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			anatop: syscon@30360000 {</div><div class='del'>-				compatible = "fsl,imx8mq-anatop", "syscon";</div><div class='add'>+			anatop: clock-controller@30360000 {</div><div class='add'>+				compatible = "fsl,imx8mq-anatop";</div><div class='ctx'> 				reg = &lt;0x30360000 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#clock-cells = &lt;1&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			snvs: snvs@30370000 {</div><div class='ctx'> 				compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";</div><div class='ctx'> 				reg = &lt;0x30370000 0x10000&gt;;</div><div class='ctx'> </div><div class='del'>-				snvs_rtc: snvs-rtc-lp{</div><div class='add'>+				snvs_rtc: snvs-rtc-lp {</div><div class='ctx'> 					compatible = "fsl,sec-v4.0-mon-rtc-lp";</div><div class='del'>-					regmap =&lt;&amp;snvs&gt;;</div><div class='add'>+					regmap = &lt;&amp;snvs&gt;;</div><div class='ctx'> 					offset = &lt;0x34&gt;;</div><div class='ctx'> 					interrupts = &lt;GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 						&lt;GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='hunk'>@@ -595,19 +853,40 @@</div><div class='ctx'> 				clock-names = "ckil", "osc_25m", "osc_27m",</div><div class='ctx'> 				              "clk_ext1", "clk_ext2",</div><div class='ctx'> 				              "clk_ext3", "clk_ext4";</div><div class='del'>-				assigned-clocks = &lt;&amp;clk IMX8MQ_CLK_NOC&gt;;</div><div class='del'>-				assigned-clock-rates = &lt;800000000&gt;;</div><div class='add'>+				assigned-clocks = &lt;&amp;clk IMX8MQ_CLK_A53_SRC&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX8MQ_CLK_A53_CORE&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX8MQ_CLK_NOC&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX8MQ_CLK_AUDIO_AHB&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX8MQ_AUDIO_PLL1_BYPASS&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX8MQ_AUDIO_PLL2_BYPASS&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX8MQ_AUDIO_PLL1&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX8MQ_AUDIO_PLL2&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;0&gt;, &lt;0&gt;,</div><div class='add'>+						       &lt;800000000&gt;,</div><div class='add'>+						       &lt;0&gt;,</div><div class='add'>+						       &lt;0&gt;,</div><div class='add'>+						       &lt;0&gt;,</div><div class='add'>+						       &lt;786432000&gt;,</div><div class='add'>+						       &lt;722534400&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;clk IMX8MQ_SYS1_PLL_800M&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MQ_ARM_PLL_OUT&gt;,</div><div class='add'>+							 &lt;0&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MQ_SYS2_PLL_500M&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MQ_AUDIO_PLL1&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MQ_AUDIO_PLL2&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			src: reset-controller@30390000 {</div><div class='ctx'> 				compatible = "fsl,imx8mq-src", "syscon";</div><div class='ctx'> 				reg = &lt;0x30390000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				#reset-cells = &lt;1&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			gpc: gpc@303a0000 {</div><div class='ctx'> 				compatible = "fsl,imx8mq-gpc";</div><div class='ctx'> 				reg = &lt;0x303a0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				interrupt-parent = &lt;&amp;gic&gt;;</div><div class='ctx'> 				interrupt-controller;</div><div class='ctx'> 				#interrupt-cells = &lt;3&gt;;</div><div class='hunk'>@@ -669,6 +948,21 @@</div><div class='ctx'> 					pgc_vpu: power-domain@6 {</div><div class='ctx'> 						#power-domain-cells = &lt;0&gt;;</div><div class='ctx'> 						reg = &lt;IMX8M_POWER_DOMAIN_VPU&gt;;</div><div class='add'>+						clocks = &lt;&amp;clk IMX8MQ_CLK_VPU_DEC_ROOT&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MQ_CLK_VPU_G1_ROOT&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MQ_CLK_VPU_G2_ROOT&gt;;</div><div class='add'>+						assigned-clocks = &lt;&amp;clk IMX8MQ_CLK_VPU_G1&gt;,</div><div class='add'>+								  &lt;&amp;clk IMX8MQ_CLK_VPU_G2&gt;,</div><div class='add'>+								  &lt;&amp;clk IMX8MQ_CLK_VPU_BUS&gt;,</div><div class='add'>+								  &lt;&amp;clk IMX8MQ_VPU_PLL_BYPASS&gt;;</div><div class='add'>+						assigned-clock-parents = &lt;&amp;clk IMX8MQ_VPU_PLL_OUT&gt;,</div><div class='add'>+									 &lt;&amp;clk IMX8MQ_VPU_PLL_OUT&gt;,</div><div class='add'>+									 &lt;&amp;clk IMX8MQ_SYS1_PLL_800M&gt;,</div><div class='add'>+									 &lt;&amp;clk IMX8MQ_VPU_PLL&gt;;</div><div class='add'>+						assigned-clock-rates = &lt;600000000&gt;,</div><div class='add'>+								       &lt;300000000&gt;,</div><div class='add'>+								       &lt;800000000&gt;,</div><div class='add'>+								       &lt;0&gt;;</div><div class='ctx'> 					};</div><div class='ctx'> </div><div class='ctx'> 					pgc_disp: power-domain@7 {</div><div class='hunk'>@@ -694,9 +988,9 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		bus@30400000 { /* AIPS2 */</div><div class='add'>+		aips2: bus@30400000 { /* AIPS2 */</div><div class='ctx'> 			compatible = "fsl,aips-bus", "simple-bus";</div><div class='del'>-			reg = &lt;0x305f0000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x30400000 0x400000&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;1&gt;;</div><div class='ctx'> 			ranges = &lt;0x30400000 0x30400000 0x400000&gt;;</div><div class='hunk'>@@ -708,7 +1002,7 @@</div><div class='ctx'> 				clocks = &lt;&amp;clk IMX8MQ_CLK_PWM1_ROOT&gt;,</div><div class='ctx'> 				         &lt;&amp;clk IMX8MQ_CLK_PWM1_ROOT&gt;;</div><div class='ctx'> 				clock-names = "ipg", "per";</div><div class='del'>-				#pwm-cells = &lt;2&gt;;</div><div class='add'>+				#pwm-cells = &lt;3&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -719,7 +1013,7 @@</div><div class='ctx'> 				clocks = &lt;&amp;clk IMX8MQ_CLK_PWM2_ROOT&gt;,</div><div class='ctx'> 				         &lt;&amp;clk IMX8MQ_CLK_PWM2_ROOT&gt;;</div><div class='ctx'> 				clock-names = "ipg", "per";</div><div class='del'>-				#pwm-cells = &lt;2&gt;;</div><div class='add'>+				#pwm-cells = &lt;3&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -730,7 +1024,7 @@</div><div class='ctx'> 				clocks = &lt;&amp;clk IMX8MQ_CLK_PWM3_ROOT&gt;,</div><div class='ctx'> 				         &lt;&amp;clk IMX8MQ_CLK_PWM3_ROOT&gt;;</div><div class='ctx'> 				clock-names = "ipg", "per";</div><div class='del'>-				#pwm-cells = &lt;2&gt;;</div><div class='add'>+				#pwm-cells = &lt;3&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -741,7 +1035,7 @@</div><div class='ctx'> 				clocks = &lt;&amp;clk IMX8MQ_CLK_PWM4_ROOT&gt;,</div><div class='ctx'> 				         &lt;&amp;clk IMX8MQ_CLK_PWM4_ROOT&gt;;</div><div class='ctx'> 				clock-names = "ipg", "per";</div><div class='del'>-				#pwm-cells = &lt;2&gt;;</div><div class='add'>+				#pwm-cells = &lt;3&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -754,14 +1048,38 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		bus@30800000 { /* AIPS3 */</div><div class='add'>+		aips3: bus@30800000 { /* AIPS3 */</div><div class='ctx'> 			compatible = "fsl,aips-bus", "simple-bus";</div><div class='del'>-			reg = &lt;0x309f0000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x30800000 0x400000&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;1&gt;;</div><div class='ctx'> 			ranges = &lt;0x30800000 0x30800000 0x400000&gt;,</div><div class='ctx'> 				 &lt;0x08000000 0x08000000 0x10000000&gt;;</div><div class='ctx'> </div><div class='add'>+			spdif1: spdif@30810000 {</div><div class='add'>+				compatible = "fsl,imx35-spdif";</div><div class='add'>+				reg = &lt;0x30810000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MQ_CLK_IPG_ROOT&gt;, /* core */</div><div class='add'>+					&lt;&amp;clk IMX8MQ_CLK_25M&gt;, /* rxtx0 */</div><div class='add'>+					&lt;&amp;clk IMX8MQ_CLK_SPDIF1&gt;, /* rxtx1 */</div><div class='add'>+					&lt;&amp;clk IMX8MQ_CLK_DUMMY&gt;, /* rxtx2 */</div><div class='add'>+					&lt;&amp;clk IMX8MQ_CLK_DUMMY&gt;, /* rxtx3 */</div><div class='add'>+					&lt;&amp;clk IMX8MQ_CLK_DUMMY&gt;, /* rxtx4 */</div><div class='add'>+					&lt;&amp;clk IMX8MQ_CLK_IPG_ROOT&gt;, /* rxtx5 */</div><div class='add'>+					&lt;&amp;clk IMX8MQ_CLK_DUMMY&gt;, /* rxtx6 */</div><div class='add'>+					&lt;&amp;clk IMX8MQ_CLK_DUMMY&gt;, /* rxtx7 */</div><div class='add'>+					&lt;&amp;clk IMX8MQ_CLK_DUMMY&gt;; /* spba */</div><div class='add'>+				clock-names = "core", "rxtx0",</div><div class='add'>+					      "rxtx1", "rxtx2",</div><div class='add'>+					      "rxtx3", "rxtx4",</div><div class='add'>+					      "rxtx5", "rxtx6",</div><div class='add'>+					      "rxtx7", "spba";</div><div class='add'>+				dmas = &lt;&amp;sdma1 8 18 0&gt;, &lt;&amp;sdma1 9 18 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='ctx'> 			ecspi1: spi@30820000 {</div><div class='ctx'> 				#address-cells = &lt;1&gt;;</div><div class='ctx'> 				#size-cells = &lt;0&gt;;</div><div class='hunk'>@@ -771,6 +1089,8 @@</div><div class='ctx'> 				clocks = &lt;&amp;clk IMX8MQ_CLK_ECSPI1_ROOT&gt;,</div><div class='ctx'> 					 &lt;&amp;clk IMX8MQ_CLK_ECSPI1_ROOT&gt;;</div><div class='ctx'> 				clock-names = "ipg", "per";</div><div class='add'>+				dmas = &lt;&amp;sdma1 0 7 1&gt;, &lt;&amp;sdma1 1 7 2&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -783,6 +1103,8 @@</div><div class='ctx'> 				clocks = &lt;&amp;clk IMX8MQ_CLK_ECSPI2_ROOT&gt;,</div><div class='ctx'> 					 &lt;&amp;clk IMX8MQ_CLK_ECSPI2_ROOT&gt;;</div><div class='ctx'> 				clock-names = "ipg", "per";</div><div class='add'>+				dmas = &lt;&amp;sdma1 2 7 1&gt;, &lt;&amp;sdma1 3 7 2&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -795,6 +1117,8 @@</div><div class='ctx'> 				clocks = &lt;&amp;clk IMX8MQ_CLK_ECSPI3_ROOT&gt;,</div><div class='ctx'> 					 &lt;&amp;clk IMX8MQ_CLK_ECSPI3_ROOT&gt;;</div><div class='ctx'> 				clock-names = "ipg", "per";</div><div class='add'>+				dmas = &lt;&amp;sdma1 4 7 1&gt;, &lt;&amp;sdma1 5 7 2&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -806,6 +1130,8 @@</div><div class='ctx'> 				clocks = &lt;&amp;clk IMX8MQ_CLK_UART1_ROOT&gt;,</div><div class='ctx'> 				         &lt;&amp;clk IMX8MQ_CLK_UART1_ROOT&gt;;</div><div class='ctx'> 				clock-names = "ipg", "per";</div><div class='add'>+				dmas = &lt;&amp;sdma1 22 4 0&gt;, &lt;&amp;sdma1 23 4 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -817,6 +1143,8 @@</div><div class='ctx'> 				clocks = &lt;&amp;clk IMX8MQ_CLK_UART3_ROOT&gt;,</div><div class='ctx'> 				         &lt;&amp;clk IMX8MQ_CLK_UART3_ROOT&gt;;</div><div class='ctx'> 				clock-names = "ipg", "per";</div><div class='add'>+				dmas = &lt;&amp;sdma1 26 4 0&gt;, &lt;&amp;sdma1 27 4 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -828,6 +1156,32 @@</div><div class='ctx'> 				clocks = &lt;&amp;clk IMX8MQ_CLK_UART2_ROOT&gt;,</div><div class='ctx'> 				         &lt;&amp;clk IMX8MQ_CLK_UART2_ROOT&gt;;</div><div class='ctx'> 				clock-names = "ipg", "per";</div><div class='add'>+				dmas = &lt;&amp;sdma1 24 4 0&gt;, &lt;&amp;sdma1 25 4 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spdif2: spdif@308a0000 {</div><div class='add'>+				compatible = "fsl,imx35-spdif";</div><div class='add'>+				reg = &lt;0x308a0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MQ_CLK_IPG_ROOT&gt;, /* core */</div><div class='add'>+					&lt;&amp;clk IMX8MQ_CLK_25M&gt;, /* rxtx0 */</div><div class='add'>+					&lt;&amp;clk IMX8MQ_CLK_SPDIF2&gt;, /* rxtx1 */</div><div class='add'>+					&lt;&amp;clk IMX8MQ_CLK_DUMMY&gt;, /* rxtx2 */</div><div class='add'>+					&lt;&amp;clk IMX8MQ_CLK_DUMMY&gt;, /* rxtx3 */</div><div class='add'>+					&lt;&amp;clk IMX8MQ_CLK_DUMMY&gt;, /* rxtx4 */</div><div class='add'>+					&lt;&amp;clk IMX8MQ_CLK_IPG_ROOT&gt;, /* rxtx5 */</div><div class='add'>+					&lt;&amp;clk IMX8MQ_CLK_DUMMY&gt;, /* rxtx6 */</div><div class='add'>+					&lt;&amp;clk IMX8MQ_CLK_DUMMY&gt;, /* rxtx7 */</div><div class='add'>+					&lt;&amp;clk IMX8MQ_CLK_DUMMY&gt;; /* spba */</div><div class='add'>+				clock-names = "core", "rxtx0",</div><div class='add'>+					      "rxtx1", "rxtx2",</div><div class='add'>+					      "rxtx3", "rxtx4",</div><div class='add'>+					      "rxtx5", "rxtx6",</div><div class='add'>+					      "rxtx7", "spba";</div><div class='add'>+				dmas = &lt;&amp;sdma1 16 18 0&gt;, &lt;&amp;sdma1 17 18 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -874,6 +1228,7 @@</div><div class='ctx'> 					compatible = "fsl,sec-v4.0-job-ring";</div><div class='ctx'> 					reg = &lt;0x1000 0x1000&gt;;</div><div class='ctx'> 					interrupts = &lt;GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					status = "disabled";</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='ctx'> 				sec_jr1: jr@2000 {</div><div class='hunk'>@@ -889,14 +1244,71 @@</div><div class='ctx'> 				};</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='add'>+			mipi_dsi: dsi@30a00000 {</div><div class='add'>+				compatible = "fsl,imx8mq-nwl-dsi";</div><div class='add'>+				reg = &lt;0x30a00000 0x300&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MQ_CLK_DSI_CORE&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MQ_CLK_DSI_AHB&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MQ_CLK_DSI_IPG_DIV&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MQ_CLK_DSI_PHY_REF&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX8MQ_CLK_LCDIF_PIXEL&gt;;</div><div class='add'>+				clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif";</div><div class='add'>+				assigned-clocks = &lt;&amp;clk IMX8MQ_CLK_DSI_AHB&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX8MQ_CLK_DSI_CORE&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX8MQ_CLK_DSI_IPG_DIV&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;clk IMX8MQ_SYS1_PLL_80M&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MQ_SYS1_PLL_266M&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;80000000&gt;, &lt;266000000&gt;, &lt;20000000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				mux-controls = &lt;&amp;mux 0&gt;;</div><div class='add'>+				power-domains = &lt;&amp;pgc_mipi&gt;;</div><div class='add'>+				phys = &lt;&amp;dphy&gt;;</div><div class='add'>+				phy-names = "dphy";</div><div class='add'>+				resets = &lt;&amp;src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N&gt;,</div><div class='add'>+					 &lt;&amp;src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N&gt;,</div><div class='add'>+					 &lt;&amp;src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N&gt;,</div><div class='add'>+					 &lt;&amp;src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N&gt;;</div><div class='add'>+				reset-names = "byte", "dpi", "esc", "pclk";</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+						mipi_dsi_lcdif_in: endpoint@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+							remote-endpoint = &lt;&amp;lcdif_mipi_dsi&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						mipi_dsi_out: endpoint {</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='ctx'> 			dphy: dphy@30a00300 {</div><div class='ctx'> 				compatible = "fsl,imx8mq-mipi-dphy";</div><div class='ctx'> 				reg = &lt;0x30a00300 0x100&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;clk IMX8MQ_CLK_DSI_PHY_REF&gt;;</div><div class='ctx'> 				clock-names = "phy_ref";</div><div class='del'>-				assigned-clocks = &lt;&amp;clk IMX8MQ_CLK_DSI_PHY_REF&gt;;</div><div class='del'>-				assigned-clock-parents = &lt;&amp;clk IMX8MQ_VIDEO_PLL1_OUT&gt;;</div><div class='del'>-				assigned-clock-rates = &lt;24000000&gt;;</div><div class='add'>+				assigned-clocks = &lt;&amp;clk IMX8MQ_VIDEO_PLL1_REF_SEL&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX8MQ_VIDEO_PLL1_BYPASS&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX8MQ_CLK_DSI_PHY_REF&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX8MQ_VIDEO_PLL1&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;clk IMX8MQ_CLK_25M&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX8MQ_VIDEO_PLL1&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX8MQ_VIDEO_PLL1_OUT&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;0&gt;, &lt;0&gt;, &lt;24000000&gt;, &lt;594000000&gt;;</div><div class='ctx'> 				#phy-cells = &lt;0&gt;;</div><div class='ctx'> 				power-domains = &lt;&amp;pgc_mipi&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='hunk'>@@ -950,9 +1362,123 @@</div><div class='ctx'> 				clocks = &lt;&amp;clk IMX8MQ_CLK_UART4_ROOT&gt;,</div><div class='ctx'> 				         &lt;&amp;clk IMX8MQ_CLK_UART4_ROOT&gt;;</div><div class='ctx'> 				clock-names = "ipg", "per";</div><div class='add'>+				dmas = &lt;&amp;sdma1 28 4 0&gt;, &lt;&amp;sdma1 29 4 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='add'>+			mipi_csi1: csi@30a70000 {</div><div class='add'>+				compatible = "fsl,imx8mq-mipi-csi2";</div><div class='add'>+				reg = &lt;0x30a70000 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MQ_CLK_CSI1_CORE&gt;,</div><div class='add'>+				   &lt;&amp;clk IMX8MQ_CLK_CSI1_ESC&gt;,</div><div class='add'>+				   &lt;&amp;clk IMX8MQ_CLK_CSI1_PHY_REF&gt;;</div><div class='add'>+				clock-names = "core", "esc", "ui";</div><div class='add'>+				assigned-clocks = &lt;&amp;clk IMX8MQ_CLK_CSI1_CORE&gt;,</div><div class='add'>+				    &lt;&amp;clk IMX8MQ_CLK_CSI1_PHY_REF&gt;,</div><div class='add'>+				    &lt;&amp;clk IMX8MQ_CLK_CSI1_ESC&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;266000000&gt;, &lt;333000000&gt;, &lt;66000000&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;clk IMX8MQ_SYS1_PLL_266M&gt;,</div><div class='add'>+					&lt;&amp;clk IMX8MQ_SYS2_PLL_1000M&gt;,</div><div class='add'>+					&lt;&amp;clk IMX8MQ_SYS1_PLL_800M&gt;;</div><div class='add'>+				power-domains = &lt;&amp;pgc_mipi_csi1&gt;;</div><div class='add'>+				resets = &lt;&amp;src IMX8MQ_RESET_MIPI_CSI1_CORE_RESET&gt;,</div><div class='add'>+					 &lt;&amp;src IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET&gt;,</div><div class='add'>+					 &lt;&amp;src IMX8MQ_RESET_MIPI_CSI1_ESC_RESET&gt;;</div><div class='add'>+				fsl,mipi-phy-gpr = &lt;&amp;iomuxc_gpr 0x88&gt;;</div><div class='add'>+				interconnects = &lt;&amp;noc IMX8MQ_ICM_CSI1 &amp;noc IMX8MQ_ICS_DRAM&gt;;</div><div class='add'>+				interconnect-names = "dram";</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						csi1_mipi_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;csi1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			csi1: csi@30a90000 {</div><div class='add'>+				compatible = "fsl,imx8mq-csi";</div><div class='add'>+				reg = &lt;0x30a90000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MQ_CLK_CSI1_ROOT&gt;;</div><div class='add'>+				clock-names = "mclk";</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				port {</div><div class='add'>+					csi1_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;csi1_mipi_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mipi_csi2: csi@30b60000 {</div><div class='add'>+				compatible = "fsl,imx8mq-mipi-csi2";</div><div class='add'>+				reg = &lt;0x30b60000 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MQ_CLK_CSI2_CORE&gt;,</div><div class='add'>+				   &lt;&amp;clk IMX8MQ_CLK_CSI2_ESC&gt;,</div><div class='add'>+				   &lt;&amp;clk IMX8MQ_CLK_CSI2_PHY_REF&gt;;</div><div class='add'>+				clock-names = "core", "esc", "ui";</div><div class='add'>+				assigned-clocks = &lt;&amp;clk IMX8MQ_CLK_CSI2_CORE&gt;,</div><div class='add'>+				    &lt;&amp;clk IMX8MQ_CLK_CSI2_PHY_REF&gt;,</div><div class='add'>+				    &lt;&amp;clk IMX8MQ_CLK_CSI2_ESC&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;266000000&gt;, &lt;333000000&gt;, &lt;66000000&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;clk IMX8MQ_SYS1_PLL_266M&gt;,</div><div class='add'>+					&lt;&amp;clk IMX8MQ_SYS2_PLL_1000M&gt;,</div><div class='add'>+					&lt;&amp;clk IMX8MQ_SYS1_PLL_800M&gt;;</div><div class='add'>+				power-domains = &lt;&amp;pgc_mipi_csi2&gt;;</div><div class='add'>+				resets = &lt;&amp;src IMX8MQ_RESET_MIPI_CSI2_CORE_RESET&gt;,</div><div class='add'>+					 &lt;&amp;src IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET&gt;,</div><div class='add'>+					 &lt;&amp;src IMX8MQ_RESET_MIPI_CSI2_ESC_RESET&gt;;</div><div class='add'>+				fsl,mipi-phy-gpr = &lt;&amp;iomuxc_gpr 0xa4&gt;;</div><div class='add'>+				interconnects = &lt;&amp;noc IMX8MQ_ICM_CSI2 &amp;noc IMX8MQ_ICS_DRAM&gt;;</div><div class='add'>+				interconnect-names = "dram";</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						csi2_mipi_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;csi2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			csi2: csi@30b80000 {</div><div class='add'>+				compatible = "fsl,imx8mq-csi";</div><div class='add'>+				reg = &lt;0x30b80000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MQ_CLK_CSI2_ROOT&gt;;</div><div class='add'>+				clock-names = "mclk";</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				port {</div><div class='add'>+					csi2_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;csi2_mipi_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mu: mailbox@30aa0000 {</div><div class='add'>+				compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu";</div><div class='add'>+				reg = &lt;0x30aa0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX8MQ_CLK_MU_ROOT&gt;;</div><div class='add'>+				#mbox-cells = &lt;2&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='ctx'> 			usdhc1: mmc@30b40000 {</div><div class='ctx'> 				compatible = "fsl,imx8mq-usdhc",</div><div class='ctx'> 				             "fsl,imx7d-usdhc";</div><div class='hunk'>@@ -997,7 +1523,7 @@</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			sdma1: sdma@30bd0000 {</div><div class='add'>+			sdma1: dma-controller@30bd0000 {</div><div class='ctx'> 				compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";</div><div class='ctx'> 				reg = &lt;0x30bd0000 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='hunk'>@@ -1013,7 +1539,8 @@</div><div class='ctx'> 				reg = &lt;0x30be0000 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 				             &lt;GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				             &lt;GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					     &lt;GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;clk IMX8MQ_CLK_ENET1_ROOT&gt;,</div><div class='ctx'> 				         &lt;&amp;clk IMX8MQ_CLK_ENET1_ROOT&gt;,</div><div class='ctx'> 				         &lt;&amp;clk IMX8MQ_CLK_ENET_TIMER&gt;,</div><div class='hunk'>@@ -1021,15 +1548,52 @@</div><div class='ctx'> 				         &lt;&amp;clk IMX8MQ_CLK_ENET_PHY_REF&gt;;</div><div class='ctx'> 				clock-names = "ipg", "ahb", "ptp",</div><div class='ctx'> 				              "enet_clk_ref", "enet_out";</div><div class='add'>+				assigned-clocks = &lt;&amp;clk IMX8MQ_CLK_ENET_AXI&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX8MQ_CLK_ENET_TIMER&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX8MQ_CLK_ENET_REF&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX8MQ_CLK_ENET_PHY_REF&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;clk IMX8MQ_SYS1_PLL_266M&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MQ_SYS2_PLL_100M&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MQ_SYS2_PLL_125M&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX8MQ_SYS2_PLL_50M&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;0&gt;, &lt;100000000&gt;, &lt;125000000&gt;, &lt;0&gt;;</div><div class='ctx'> 				fsl,num-tx-queues = &lt;3&gt;;</div><div class='ctx'> 				fsl,num-rx-queues = &lt;3&gt;;</div><div class='add'>+				nvmem-cells = &lt;&amp;fec_mac_address&gt;;</div><div class='add'>+				nvmem-cell-names = "mac-address";</div><div class='add'>+				fsl,stop-mode = &lt;&amp;iomuxc_gpr 0x10 3&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		bus@32c00000 { /* AIPS4 */</div><div class='add'>+		noc: interconnect@32700000 {</div><div class='add'>+			compatible = "fsl,imx8mq-noc", "fsl,imx8m-noc";</div><div class='add'>+			reg = &lt;0x32700000 0x100000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MQ_CLK_NOC&gt;;</div><div class='add'>+			fsl,ddrc = &lt;&amp;ddrc&gt;;</div><div class='add'>+			#interconnect-cells = &lt;1&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;noc_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+			noc_opp_table: opp-table {</div><div class='add'>+				compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+				opp-133000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;133333333&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-400000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;400000000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-800000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;800000000&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aips4: bus@32c00000 { /* AIPS4 */</div><div class='ctx'> 			compatible = "fsl,aips-bus", "simple-bus";</div><div class='del'>-			reg = &lt;0x32df0000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x32c00000 0x400000&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;1&gt;;</div><div class='ctx'> 			ranges = &lt;0x32c00000 0x32c00000 0x400000&gt;;</div><div class='hunk'>@@ -1088,7 +1652,7 @@</div><div class='ctx'> 			phys = &lt;&amp;usb3_phy0&gt;, &lt;&amp;usb3_phy0&gt;;</div><div class='ctx'> 			phy-names = "usb2-phy", "usb3-phy";</div><div class='ctx'> 			power-domains = &lt;&amp;pgc_otg1&gt;;</div><div class='del'>-			usb3-resume-missing-cas;</div><div class='add'>+			snps,parkmode-disable-ss-quirk;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -1120,7 +1684,7 @@</div><div class='ctx'> 			phys = &lt;&amp;usb3_phy1&gt;, &lt;&amp;usb3_phy1&gt;;</div><div class='ctx'> 			phy-names = "usb2-phy", "usb3-phy";</div><div class='ctx'> 			power-domains = &lt;&amp;pgc_otg2&gt;;</div><div class='del'>-			usb3-resume-missing-cas;</div><div class='add'>+			snps,parkmode-disable-ss-quirk;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -1136,6 +1700,33 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		vpu_g1: video-codec@38300000 {</div><div class='add'>+			compatible = "nxp,imx8mq-vpu-g1";</div><div class='add'>+			reg = &lt;0x38300000 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MQ_CLK_VPU_G1_ROOT&gt;;</div><div class='add'>+			power-domains = &lt;&amp;vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vpu_g2: video-codec@38310000 {</div><div class='add'>+			compatible = "nxp,imx8mq-vpu-g2";</div><div class='add'>+			reg = &lt;0x38310000 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MQ_CLK_VPU_G2_ROOT&gt;;</div><div class='add'>+			power-domains = &lt;&amp;vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vpu_blk_ctrl: blk-ctrl@38320000 {</div><div class='add'>+			compatible = "fsl,imx8mq-vpu-blk-ctrl";</div><div class='add'>+			reg = &lt;0x38320000 0x100&gt;;</div><div class='add'>+			power-domains = &lt;&amp;pgc_vpu&gt;, &lt;&amp;pgc_vpu&gt;, &lt;&amp;pgc_vpu&gt;;</div><div class='add'>+			power-domain-names = "bus", "g1", "g2";</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MQ_CLK_VPU_G1_ROOT&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MQ_CLK_VPU_G2_ROOT&gt;;</div><div class='add'>+			clock-names = "g1", "g2";</div><div class='add'>+			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		pcie0: pcie@33800000 {</div><div class='ctx'> 			compatible = "fsl,imx8mq-pcie";</div><div class='ctx'> 			reg = &lt;0x33800000 0x400000&gt;,</div><div class='hunk'>@@ -1145,10 +1736,9 @@</div><div class='ctx'> 			#size-cells = &lt;2&gt;;</div><div class='ctx'> 			device_type = "pci";</div><div class='ctx'> 			bus-range = &lt;0x00 0xff&gt;;</div><div class='del'>-			ranges = &lt;0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */</div><div class='del'>-			          0x82000000 0 0x18000000 0x18000000 0 0x07f00000&gt;; /* non-prefetchable memory */</div><div class='add'>+			ranges = &lt;0x81000000 0 0x00000000 0x1ff80000 0 0x00010000&gt;, /* downstream I/O 64KB */</div><div class='add'>+				 &lt;0x82000000 0 0x18000000 0x18000000 0 0x07f00000&gt;; /* non-prefetchable memory */</div><div class='ctx'> 			num-lanes = &lt;1&gt;;</div><div class='del'>-			num-viewport = &lt;4&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			interrupt-names = "msi";</div><div class='ctx'> 			#interrupt-cells = &lt;1&gt;;</div><div class='hunk'>@@ -1158,11 +1748,60 @@</div><div class='ctx'> 			                &lt;0 0 0 3 &amp;gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 			                &lt;0 0 0 4 &amp;gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			fsl,max-link-speed = &lt;2&gt;;</div><div class='add'>+			linux,pci-domain = &lt;0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MQ_CLK_PCIE1_ROOT&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MQ_CLK_PCIE1_PHY&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MQ_CLK_PCIE1_PHY&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MQ_CLK_PCIE1_AUX&gt;;</div><div class='add'>+			clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";</div><div class='ctx'> 			power-domains = &lt;&amp;pgc_pcie&gt;;</div><div class='ctx'> 			resets = &lt;&amp;src IMX8MQ_RESET_PCIEPHY&gt;,</div><div class='ctx'> 			         &lt;&amp;src IMX8MQ_RESET_PCIE_CTRL_APPS_EN&gt;,</div><div class='ctx'> 			         &lt;&amp;src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF&gt;;</div><div class='ctx'> 			reset-names = "pciephy", "apps", "turnoff";</div><div class='add'>+			assigned-clocks = &lt;&amp;clk IMX8MQ_CLK_PCIE1_CTRL&gt;,</div><div class='add'>+			                  &lt;&amp;clk IMX8MQ_CLK_PCIE1_PHY&gt;,</div><div class='add'>+			                  &lt;&amp;clk IMX8MQ_CLK_PCIE1_AUX&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;clk IMX8MQ_SYS2_PLL_250M&gt;,</div><div class='add'>+			                         &lt;&amp;clk IMX8MQ_SYS2_PLL_100M&gt;,</div><div class='add'>+			                         &lt;&amp;clk IMX8MQ_SYS1_PLL_80M&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;250000000&gt;, &lt;100000000&gt;,</div><div class='add'>+			                       &lt;10000000&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie0_ep: pcie-ep@33800000 {</div><div class='add'>+			compatible = "fsl,imx8mq-pcie-ep";</div><div class='add'>+			reg = &lt;0x33800000 0x100000&gt;,</div><div class='add'>+			      &lt;0x18000000 0x8000000&gt;,</div><div class='add'>+			      &lt;0x33900000 0x100000&gt;,</div><div class='add'>+			      &lt;0x33b00000 0x100000&gt;;</div><div class='add'>+			reg-names = "dbi", "addr_space", "dbi2", "atu";</div><div class='add'>+			num-lanes = &lt;1&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "dma";</div><div class='add'>+			linux,pci-domain = &lt;0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MQ_CLK_PCIE2_ROOT&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MQ_CLK_PCIE2_PHY&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MQ_CLK_PCIE2_PHY&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MQ_CLK_PCIE2_AUX&gt;;</div><div class='add'>+			clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";</div><div class='add'>+			power-domains = &lt;&amp;pgc_pcie&gt;;</div><div class='add'>+			resets = &lt;&amp;src IMX8MQ_RESET_PCIEPHY2&gt;,</div><div class='add'>+				 &lt;&amp;src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN&gt;,</div><div class='add'>+				 &lt;&amp;src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF&gt;;</div><div class='add'>+			reset-names = "pciephy", "apps", "turnoff";</div><div class='add'>+			assigned-clocks = &lt;&amp;clk IMX8MQ_CLK_PCIE2_CTRL&gt;,</div><div class='add'>+					  &lt;&amp;clk IMX8MQ_CLK_PCIE2_PHY&gt;,</div><div class='add'>+					  &lt;&amp;clk IMX8MQ_CLK_PCIE2_AUX&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;clk IMX8MQ_SYS2_PLL_250M&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MQ_SYS2_PLL_100M&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MQ_SYS1_PLL_80M&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;250000000&gt;, &lt;100000000&gt;,</div><div class='add'>+					       &lt;10000000&gt;;</div><div class='add'>+			num-ib-windows = &lt;4&gt;;</div><div class='add'>+			num-ob-windows = &lt;4&gt;;</div><div class='add'>+			fsl,max-link-speed = &lt;2&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -1174,10 +1813,10 @@</div><div class='ctx'> 			#address-cells = &lt;3&gt;;</div><div class='ctx'> 			#size-cells = &lt;2&gt;;</div><div class='ctx'> 			device_type = "pci";</div><div class='del'>-			ranges =  &lt;0x81000000 0 0x00000000 0x27f80000 0 0x00010000 /* downstream I/O 64KB */</div><div class='del'>-				   0x82000000 0 0x20000000 0x20000000 0 0x07f00000&gt;; /* non-prefetchable memory */</div><div class='add'>+			bus-range = &lt;0x00 0xff&gt;;</div><div class='add'>+			ranges = &lt;0x81000000 0 0x00000000 0x27f80000 0 0x00010000&gt;, /* downstream I/O 64KB */</div><div class='add'>+				 &lt;0x82000000 0 0x20000000 0x20000000 0 0x07f00000&gt;; /* non-prefetchable memory */</div><div class='ctx'> 			num-lanes = &lt;1&gt;;</div><div class='del'>-			num-viewport = &lt;4&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			interrupt-names = "msi";</div><div class='ctx'> 			#interrupt-cells = &lt;1&gt;;</div><div class='hunk'>@@ -1187,11 +1826,60 @@</div><div class='ctx'> 					&lt;0 0 0 3 &amp;gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 					&lt;0 0 0 4 &amp;gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			fsl,max-link-speed = &lt;2&gt;;</div><div class='add'>+			linux,pci-domain = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MQ_CLK_PCIE2_ROOT&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MQ_CLK_PCIE2_PHY&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MQ_CLK_PCIE2_PHY&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MQ_CLK_PCIE2_AUX&gt;;</div><div class='add'>+			clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";</div><div class='ctx'> 			power-domains = &lt;&amp;pgc_pcie&gt;;</div><div class='ctx'> 			resets = &lt;&amp;src IMX8MQ_RESET_PCIEPHY2&gt;,</div><div class='ctx'> 			         &lt;&amp;src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN&gt;,</div><div class='ctx'> 			         &lt;&amp;src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF&gt;;</div><div class='ctx'> 			reset-names = "pciephy", "apps", "turnoff";</div><div class='add'>+			assigned-clocks = &lt;&amp;clk IMX8MQ_CLK_PCIE2_CTRL&gt;,</div><div class='add'>+			                  &lt;&amp;clk IMX8MQ_CLK_PCIE2_PHY&gt;,</div><div class='add'>+			                  &lt;&amp;clk IMX8MQ_CLK_PCIE2_AUX&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;clk IMX8MQ_SYS2_PLL_250M&gt;,</div><div class='add'>+			                         &lt;&amp;clk IMX8MQ_SYS2_PLL_100M&gt;,</div><div class='add'>+			                         &lt;&amp;clk IMX8MQ_SYS1_PLL_80M&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;250000000&gt;, &lt;100000000&gt;,</div><div class='add'>+			                       &lt;10000000&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie1_ep: pcie-ep@33c00000 {</div><div class='add'>+			compatible = "fsl,imx8mq-pcie-ep";</div><div class='add'>+			reg = &lt;0x33c00000 0x100000&gt;,</div><div class='add'>+			      &lt;0x20000000 0x8000000&gt;,</div><div class='add'>+			      &lt;0x33d00000 0x100000&gt;,</div><div class='add'>+			      &lt;0x33f00000 0x100000&gt;;</div><div class='add'>+			reg-names = "dbi", "addr_space", "dbi2", "atu";</div><div class='add'>+			num-lanes = &lt;1&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "dma";</div><div class='add'>+			fsl,max-link-speed = &lt;2&gt;;</div><div class='add'>+			linux,pci-domain = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX8MQ_CLK_PCIE2_ROOT&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MQ_CLK_PCIE2_PHY&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MQ_CLK_PCIE2_PHY&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX8MQ_CLK_PCIE2_AUX&gt;;</div><div class='add'>+			clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";</div><div class='add'>+			power-domains = &lt;&amp;pgc_pcie&gt;;</div><div class='add'>+			resets = &lt;&amp;src IMX8MQ_RESET_PCIEPHY2&gt;,</div><div class='add'>+				 &lt;&amp;src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN&gt;,</div><div class='add'>+				 &lt;&amp;src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF&gt;;</div><div class='add'>+			reset-names = "pciephy", "apps", "turnoff";</div><div class='add'>+			assigned-clocks = &lt;&amp;clk IMX8MQ_CLK_PCIE2_CTRL&gt;,</div><div class='add'>+					  &lt;&amp;clk IMX8MQ_CLK_PCIE2_PHY&gt;,</div><div class='add'>+					  &lt;&amp;clk IMX8MQ_CLK_PCIE2_AUX&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;clk IMX8MQ_SYS2_PLL_250M&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MQ_SYS2_PLL_100M&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX8MQ_SYS1_PLL_80M&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;250000000&gt;, &lt;100000000&gt;,</div><div class='add'>+					       &lt;10000000&gt;;</div><div class='add'>+			num-ib-windows = &lt;4&gt;;</div><div class='add'>+			num-ob-windows = &lt;4&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -1202,6 +1890,7 @@</div><div class='ctx'> 			      &lt;0x31000000 0x2000&gt;,	/* GICC */</div><div class='ctx'> 			      &lt;0x31010000 0x2000&gt;,	/* GICV */</div><div class='ctx'> 			      &lt;0x31020000 0x2000&gt;;	/* GICH */</div><div class='add'>+			#address-cells = &lt;0&gt;;</div><div class='ctx'> 			#interrupt-cells = &lt;3&gt;;</div><div class='ctx'> 			interrupt-controller;</div><div class='ctx'> 			interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='hunk'>@@ -1216,6 +1905,7 @@</div><div class='ctx'> 				 &lt;&amp;clk IMX8MQ_DRAM_PLL_OUT&gt;,</div><div class='ctx'> 				 &lt;&amp;clk IMX8MQ_CLK_DRAM_ALT&gt;,</div><div class='ctx'> 				 &lt;&amp;clk IMX8MQ_CLK_DRAM_APB&gt;;</div><div class='add'>+			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		ddr-pmu@3d800000 {</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8qm-apalis-eval-v1.2.dts b/arch/arm64/boot/dts/freescale/imx8qm-apalis-eval-v1.2.dts<br/>new file mode 100644<br/>index 000000000000..8466a8204ed0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8qm-apalis-eval-v1.2.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8qm-apalis-eval-v1.2.dts</a></div><div class='hunk'>@@ -0,0 +1,16 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8qm-apalis.dtsi"</div><div class='add'>+#include "imx8-apalis-eval-v1.2.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Toradex Apalis iMX8QM/QP on Apalis Evaluation Board V1.2";</div><div class='add'>+	compatible = "toradex,apalis-imx8-eval-v1.2",</div><div class='add'>+		     "toradex,apalis-imx8",</div><div class='add'>+		     "fsl,imx8qm";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8qm-apalis-eval.dts b/arch/arm64/boot/dts/freescale/imx8qm-apalis-eval.dts<br/>new file mode 100644<br/>index 000000000000..b0ebf6d05450<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8qm-apalis-eval.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8qm-apalis-eval.dts</a></div><div class='hunk'>@@ -0,0 +1,16 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8qm-apalis.dtsi"</div><div class='add'>+#include "imx8-apalis-eval-v1.1.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Toradex Apalis iMX8QM/QP on Apalis Evaluation Board";</div><div class='add'>+	compatible = "toradex,apalis-imx8-eval",</div><div class='add'>+		     "toradex,apalis-imx8",</div><div class='add'>+		     "fsl,imx8qm";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8qm-apalis-ixora-v1.1.dts b/arch/arm64/boot/dts/freescale/imx8qm-apalis-ixora-v1.1.dts<br/>new file mode 100644<br/>index 000000000000..68ce58dc7102<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8qm-apalis-ixora-v1.1.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8qm-apalis-ixora-v1.1.dts</a></div><div class='hunk'>@@ -0,0 +1,16 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8qm-apalis.dtsi"</div><div class='add'>+#include "imx8-apalis-ixora-v1.1.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Toradex Apalis iMX8QM/QP on Apalis Ixora V1.1 Carrier Board";</div><div class='add'>+	compatible = "toradex,apalis-imx8-ixora-v1.1",</div><div class='add'>+		     "toradex,apalis-imx8",</div><div class='add'>+		     "fsl,imx8qm";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-eval-v1.2.dts b/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-eval-v1.2.dts<br/>new file mode 100644<br/>index 000000000000..92c0ae0c0337<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-eval-v1.2.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-eval-v1.2.dts</a></div><div class='hunk'>@@ -0,0 +1,26 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8qm-apalis-v1.1.dtsi"</div><div class='add'>+#include "imx8-apalis-eval-v1.2.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Toradex Apalis iMX8QM V1.1 on Apalis Evaluation Board V1.2";</div><div class='add'>+	compatible = "toradex,apalis-imx8-v1.1-eval-v1.2",</div><div class='add'>+		     "toradex,apalis-imx8-v1.1",</div><div class='add'>+		     "fsl,imx8qm";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis MMC1 */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	/delete-property/ no-1-8-v;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis SD1 */</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	/delete-property/ no-1-8-v;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-eval.dts b/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-eval.dts<br/>new file mode 100644<br/>index 000000000000..c998e542f93c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-eval.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-eval.dts</a></div><div class='hunk'>@@ -0,0 +1,16 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8qm-apalis-v1.1.dtsi"</div><div class='add'>+#include "imx8-apalis-eval-v1.1.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Toradex Apalis iMX8QM V1.1 on Apalis Evaluation Board";</div><div class='add'>+	compatible = "toradex,apalis-imx8-v1.1-eval",</div><div class='add'>+		     "toradex,apalis-imx8-v1.1",</div><div class='add'>+		     "fsl,imx8qm";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-ixora-v1.1.dts b/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-ixora-v1.1.dts<br/>new file mode 100644<br/>index 000000000000..ad7f644968fa<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-ixora-v1.1.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-ixora-v1.1.dts</a></div><div class='hunk'>@@ -0,0 +1,16 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8qm-apalis-v1.1.dtsi"</div><div class='add'>+#include "imx8-apalis-ixora-v1.1.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Toradex Apalis iMX8QM V1.1 on Apalis Ixora V1.1 Carrier Board";</div><div class='add'>+	compatible = "toradex,apalis-imx8-v1.1-ixora-v1.1",</div><div class='add'>+		     "toradex,apalis-imx8-v1.1",</div><div class='add'>+		     "fsl,imx8qm";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-ixora-v1.2.dts b/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-ixora-v1.2.dts<br/>new file mode 100644<br/>index 000000000000..3b2e8c93b846<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-ixora-v1.2.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-ixora-v1.2.dts</a></div><div class='hunk'>@@ -0,0 +1,16 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8qm-apalis-v1.1.dtsi"</div><div class='add'>+#include "imx8-apalis-ixora-v1.2.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Toradex Apalis iMX8QM V1.1 on Apalis Ixora V1.2 Carrier Board";</div><div class='add'>+	compatible = "toradex,apalis-imx8-v1.1-ixora-v1.2",</div><div class='add'>+		     "toradex,apalis-imx8-v1.1",</div><div class='add'>+		     "fsl,imx8qm";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1.dtsi<br/>new file mode 100644<br/>index 000000000000..8a37cbe922ac<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1.dtsi</a></div><div class='hunk'>@@ -0,0 +1,22 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/pwm/pwm.h&gt;</div><div class='add'>+#include "imx8qm.dtsi"</div><div class='add'>+#include "imx8-apalis-v1.1.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Toradex Apalis iMX8QM V1.1";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cooling_maps_map0 {</div><div class='add'>+	cooling-device =</div><div class='add'>+		&lt;&amp;A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+		&lt;&amp;A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+		&lt;&amp;A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+		&lt;&amp;A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+		&lt;&amp;A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+		&lt;&amp;A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi<br/>new file mode 100644<br/>index 000000000000..7594ac61fe56<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi</a></div><div class='hunk'>@@ -0,0 +1,333 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "imx8qm-apalis-v1.1.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Toradex Apalis iMX8QM";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethphy0 {</div><div class='add'>+	interrupts = &lt;5 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Apalis iMX8QM V1.0 has PHY KSZ9031. the Micrel PHY driver</div><div class='add'>+ * doesn't support setting internal PHY delay for TXC line for</div><div class='add'>+ * this PHY model. Use delay on MAC side instead.</div><div class='add'>+ */</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	phy-mode = "rgmii-rxid";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hsio_refa_clk {</div><div class='add'>+	enable-gpios = &lt;&amp;lsio_gpio4 27 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* TODO: Apalis HDMI1 */</div><div class='add'>+</div><div class='add'>+/* Apalis I2C2 (DDC) */</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c0&gt;;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio0 {</div><div class='add'>+	gpio-line-names = "MXM3_279",</div><div class='add'>+			  "MXM3_277",</div><div class='add'>+			  "MXM3_135",</div><div class='add'>+			  "MXM3_203",</div><div class='add'>+			  "MXM3_201",</div><div class='add'>+			  "MXM3_275",</div><div class='add'>+			  "MXM3_110",</div><div class='add'>+			  "MXM3_120",</div><div class='add'>+			  "MXM3_1/GPIO1",</div><div class='add'>+			  "MXM3_3/GPIO2",</div><div class='add'>+			  "MXM3_124",</div><div class='add'>+			  "MXM3_122",</div><div class='add'>+			  "MXM3_5/GPIO3",</div><div class='add'>+			  "MXM3_7/GPIO4",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "MXM3_4",</div><div class='add'>+			  "MXM3_211",</div><div class='add'>+			  "MXM3_209",</div><div class='add'>+			  "MXM3_2",</div><div class='add'>+			  "MXM3_136",</div><div class='add'>+			  "MXM3_134",</div><div class='add'>+			  "MXM3_6",</div><div class='add'>+			  "MXM3_8",</div><div class='add'>+			  "MXM3_112",</div><div class='add'>+			  "MXM3_118",</div><div class='add'>+			  "MXM3_114",</div><div class='add'>+			  "MXM3_116";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio1 {</div><div class='add'>+	gpio-line-names = "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "MXM3_286",</div><div class='add'>+			  "",</div><div class='add'>+			  "MXM3_87",</div><div class='add'>+			  "MXM3_99",</div><div class='add'>+			  "MXM3_138",</div><div class='add'>+			  "MXM3_140",</div><div class='add'>+			  "MXM3_239",</div><div class='add'>+			  "",</div><div class='add'>+			  "MXM3_281",</div><div class='add'>+			  "MXM3_283",</div><div class='add'>+			  "MXM3_126",</div><div class='add'>+			  "MXM3_132",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "MXM3_173",</div><div class='add'>+			  "MXM3_175",</div><div class='add'>+			  "MXM3_123";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio2 {</div><div class='add'>+	gpio-line-names = "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "MXM3_198",</div><div class='add'>+			  "MXM3_35",</div><div class='add'>+			  "MXM3_164",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "MXM3_217",</div><div class='add'>+			  "MXM3_215",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "MXM3_193",</div><div class='add'>+			  "MXM3_194",</div><div class='add'>+			  "MXM3_37",</div><div class='add'>+			  "",</div><div class='add'>+			  "MXM3_271",</div><div class='add'>+			  "MXM3_273",</div><div class='add'>+			  "MXM3_195",</div><div class='add'>+			  "MXM3_197",</div><div class='add'>+			  "MXM3_177",</div><div class='add'>+			  "MXM3_179",</div><div class='add'>+			  "MXM3_181",</div><div class='add'>+			  "MXM3_183",</div><div class='add'>+			  "MXM3_185",</div><div class='add'>+			  "MXM3_187";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio3 {</div><div class='add'>+	gpio-line-names = "MXM3_191",</div><div class='add'>+			  "",</div><div class='add'>+			  "MXM3_221",</div><div class='add'>+			  "MXM3_225",</div><div class='add'>+			  "MXM3_223",</div><div class='add'>+			  "MXM3_227",</div><div class='add'>+			  "MXM3_200",</div><div class='add'>+			  "MXM3_235",</div><div class='add'>+			  "MXM3_231",</div><div class='add'>+			  "MXM3_229",</div><div class='add'>+			  "MXM3_233",</div><div class='add'>+			  "MXM3_204",</div><div class='add'>+			  "MXM3_196",</div><div class='add'>+			  "",</div><div class='add'>+			  "MXM3_202",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "MXM3_305",</div><div class='add'>+			  "MXM3_307",</div><div class='add'>+			  "MXM3_309",</div><div class='add'>+			  "MXM3_311",</div><div class='add'>+			  "MXM3_315",</div><div class='add'>+			  "MXM3_317",</div><div class='add'>+			  "MXM3_319",</div><div class='add'>+			  "MXM3_321",</div><div class='add'>+			  "MXM3_15/GPIO7",</div><div class='add'>+			  "MXM3_63",</div><div class='add'>+			  "MXM3_17/GPIO8",</div><div class='add'>+			  "MXM3_12",</div><div class='add'>+			  "MXM3_14",</div><div class='add'>+			  "MXM3_16";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio4 {</div><div class='add'>+	gpio-line-names = "MXM3_18",</div><div class='add'>+			  "MXM3_11/GPIO5",</div><div class='add'>+			  "MXM3_13/GPIO6",</div><div class='add'>+			  "MXM3_274",</div><div class='add'>+			  "MXM3_84",</div><div class='add'>+			  "MXM3_262",</div><div class='add'>+			  "MXM3_96",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "MXM3_190",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "MXM3_269",</div><div class='add'>+			  "MXM3_251",</div><div class='add'>+			  "MXM3_253",</div><div class='add'>+			  "MXM3_295",</div><div class='add'>+			  "MXM3_299",</div><div class='add'>+			  "MXM3_301",</div><div class='add'>+			  "MXM3_297",</div><div class='add'>+			  "MXM3_293",</div><div class='add'>+			  "MXM3_291",</div><div class='add'>+			  "MXM3_289",</div><div class='add'>+			  "MXM3_287";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio5 {</div><div class='add'>+	gpio-line-names = "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "MXM3_150",</div><div class='add'>+			  "MXM3_160",</div><div class='add'>+			  "MXM3_162",</div><div class='add'>+			  "MXM3_144",</div><div class='add'>+			  "MXM3_146",</div><div class='add'>+			  "MXM3_148",</div><div class='add'>+			  "MXM3_152",</div><div class='add'>+			  "MXM3_156",</div><div class='add'>+			  "MXM3_158",</div><div class='add'>+			  "MXM3_159",</div><div class='add'>+			  "MXM3_184",</div><div class='add'>+			  "MXM3_180",</div><div class='add'>+			  "MXM3_186",</div><div class='add'>+			  "MXM3_188",</div><div class='add'>+			  "MXM3_176",</div><div class='add'>+			  "MXM3_178";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio6 {</div><div class='add'>+	gpio-line-names = "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "MXM3_261",</div><div class='add'>+			  "MXM3_263",</div><div class='add'>+			  "MXM3_259",</div><div class='add'>+			  "MXM3_257",</div><div class='add'>+			  "MXM3_255",</div><div class='add'>+			  "MXM3_128",</div><div class='add'>+			  "MXM3_130",</div><div class='add'>+			  "MXM3_265",</div><div class='add'>+			  "MXM3_249",</div><div class='add'>+			  "MXM3_247",</div><div class='add'>+			  "MXM3_245",</div><div class='add'>+			  "MXM3_243";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_fec1 {</div><div class='add'>+	fsl,pins =</div><div class='add'>+		/* Use pads in 1.8V mode */</div><div class='add'>+		&lt;IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD			0x000014a0&gt;,</div><div class='add'>+		&lt;IMX8QM_ENET0_MDC_CONN_ENET0_MDC				0x06000020&gt;,</div><div class='add'>+		&lt;IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO				0x06000020&gt;,</div><div class='add'>+		&lt;IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL		0x06000020&gt;,</div><div class='add'>+		&lt;IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC			0x06000020&gt;,</div><div class='add'>+		&lt;IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0			0x06000020&gt;,</div><div class='add'>+		&lt;IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1			0x06000020&gt;,</div><div class='add'>+		&lt;IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2			0x06000020&gt;,</div><div class='add'>+		&lt;IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3			0x06000020&gt;,</div><div class='add'>+		&lt;IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC			0x06000020&gt;,</div><div class='add'>+		&lt;IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL		0x06000020&gt;,</div><div class='add'>+		&lt;IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0			0x06000020&gt;,</div><div class='add'>+		&lt;IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1			0x06000020&gt;,</div><div class='add'>+		&lt;IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2			0x06000020&gt;,</div><div class='add'>+		&lt;IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3			0x06000020&gt;,</div><div class='add'>+		&lt;IMX8QM_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M	0x06000020&gt;,</div><div class='add'>+		/* On-module ETH_RESET# */</div><div class='add'>+		&lt;IMX8QM_LVDS1_GPIO01_LSIO_GPIO1_IO11				0x06000020&gt;,</div><div class='add'>+		/* On-module ETH_INT# */</div><div class='add'>+		&lt;IMX8QM_LVDS0_GPIO01_LSIO_GPIO1_IO05				0x04000060&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_fec1_sleep {</div><div class='add'>+	fsl,pins =</div><div class='add'>+		&lt;IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD			0x000014a0&gt;,</div><div class='add'>+		&lt;IMX8QM_ENET0_MDC_LSIO_GPIO4_IO14				0x04000040&gt;,</div><div class='add'>+		&lt;IMX8QM_ENET0_MDIO_LSIO_GPIO4_IO13				0x04000040&gt;,</div><div class='add'>+		&lt;IMX8QM_ENET0_RGMII_TX_CTL_LSIO_GPIO5_IO31			0x04000040&gt;,</div><div class='add'>+		&lt;IMX8QM_ENET0_RGMII_TXC_LSIO_GPIO5_IO30				0x04000040&gt;,</div><div class='add'>+		&lt;IMX8QM_ENET0_RGMII_TXD0_LSIO_GPIO6_IO00			0x04000040&gt;,</div><div class='add'>+		&lt;IMX8QM_ENET0_RGMII_TXD1_LSIO_GPIO6_IO01			0x04000040&gt;,</div><div class='add'>+		&lt;IMX8QM_ENET0_RGMII_TXD2_LSIO_GPIO6_IO02			0x04000040&gt;,</div><div class='add'>+		&lt;IMX8QM_ENET0_RGMII_TXD3_LSIO_GPIO6_IO03			0x04000040&gt;,</div><div class='add'>+		&lt;IMX8QM_ENET0_RGMII_RXC_LSIO_GPIO6_IO04				0x04000040&gt;,</div><div class='add'>+		&lt;IMX8QM_ENET0_RGMII_RX_CTL_LSIO_GPIO6_IO05			0x04000040&gt;,</div><div class='add'>+		&lt;IMX8QM_ENET0_RGMII_RXD0_LSIO_GPIO6_IO06			0x04000040&gt;,</div><div class='add'>+		&lt;IMX8QM_ENET0_RGMII_RXD1_LSIO_GPIO6_IO07			0x04000040&gt;,</div><div class='add'>+		&lt;IMX8QM_ENET0_RGMII_RXD2_LSIO_GPIO6_IO08			0x04000040&gt;,</div><div class='add'>+		&lt;IMX8QM_ENET0_RGMII_RXD3_LSIO_GPIO6_IO09			0x04000040&gt;,</div><div class='add'>+		&lt;IMX8QM_ENET0_REFCLK_125M_25M_LSIO_GPIO4_IO15			0x04000040&gt;,</div><div class='add'>+		&lt;IMX8QM_LVDS1_GPIO01_LSIO_GPIO1_IO11				0x04000040&gt;,</div><div class='add'>+		&lt;IMX8QM_LVDS0_GPIO01_LSIO_GPIO1_IO05				0x04000040&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	/* Apalis I2C2 (DDC) */</div><div class='add'>+	pinctrl_lpi2c0: lpi2c0grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL			0x04000022&gt;,</div><div class='add'>+			&lt;IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA			0x04000022&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* On-module PCIe_CTRL0_CLKREQ */</div><div class='add'>+&amp;pinctrl_pcie_sata_refclk {</div><div class='add'>+	fsl,pins =</div><div class='add'>+		&lt;IMX8QM_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27			0x00000021&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis MMC1 */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	/*</div><div class='add'>+	 * The PMIC on V1.0A HW generates 1.6V instead of 1.8V which creates</div><div class='add'>+	 * issues with certain SD cards, disable 1.8V signaling for now.</div><div class='add'>+	 */</div><div class='add'>+	no-1-8-v;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Apalis SD1 */</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	/*</div><div class='add'>+	 * The PMIC on V1.0A HW generates 1.6V instead of 1.8V which creates</div><div class='add'>+	 * issues with certain SD cards, disable 1.8V signaling for now.</div><div class='add'>+	 */</div><div class='add'>+	no-1-8-v;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-ov5640-csi0.dtso b/arch/arm64/boot/dts/freescale/imx8qm-mek-ov5640-csi0.dtso<br/>new file mode 100644<br/>index 000000000000..ceb63c28b21a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8qm-mek-ov5640-csi0.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8qm-mek-ov5640-csi0.dtso</a></div><div class='hunk'>@@ -0,0 +1,62 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2025 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/media/video-interfaces.h&gt;</div><div class='add'>+</div><div class='add'>+&amp;i2c_mipi_csi0 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c_mipi_csi0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ov5640_mipi_0: camera@3c {</div><div class='add'>+		compatible = "ovti,ov5640";</div><div class='add'>+		reg = &lt;0x3c&gt;;</div><div class='add'>+		clocks = &lt;&amp;xtal24m&gt;;</div><div class='add'>+		clock-names = "xclk";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_mipi_csi0&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		powerdown-gpios = &lt;&amp;lsio_gpio1 28 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;lsio_gpio1 27 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		AVDD-supply = &lt;&amp;reg_2v8&gt;;</div><div class='add'>+		DVDD-supply = &lt;&amp;reg_1v5&gt;;</div><div class='add'>+		DOVDD-supply = &lt;&amp;reg_1v8&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			ov5640_mipi_0_ep: endpoint {</div><div class='add'>+				bus-type = &lt;MEDIA_BUS_TYPE_CSI2_DPHY&gt;;</div><div class='add'>+				data-lanes = &lt;1 2&gt;;</div><div class='add'>+				remote-endpoint = &lt;&amp;mipi_csi0_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;irqsteer_csi0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;isi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_csi_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@0 {</div><div class='add'>+			mipi_csi0_in: endpoint {</div><div class='add'>+				data-lanes = &lt;1 2&gt;;</div><div class='add'>+				remote-endpoint = &lt;&amp;ov5640_mipi_0_ep&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-ov5640-csi1.dtso b/arch/arm64/boot/dts/freescale/imx8qm-mek-ov5640-csi1.dtso<br/>new file mode 100644<br/>index 000000000000..9e6d33c0315e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8qm-mek-ov5640-csi1.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8qm-mek-ov5640-csi1.dtso</a></div><div class='hunk'>@@ -0,0 +1,62 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2025 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/media/video-interfaces.h&gt;</div><div class='add'>+</div><div class='add'>+&amp;i2c_mipi_csi1 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c_mipi_csi1&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ov5640_mipi_1: camera@3c {</div><div class='add'>+		compatible = "ovti,ov5640";</div><div class='add'>+		reg = &lt;0x3c&gt;;</div><div class='add'>+		clocks = &lt;&amp;xtal24m&gt;;</div><div class='add'>+		clock-names = "xclk";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_mipi_csi1&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		powerdown-gpios = &lt;&amp;lsio_gpio1 31 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;lsio_gpio1 30 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		AVDD-supply = &lt;&amp;reg_2v8&gt;;</div><div class='add'>+		DVDD-supply = &lt;&amp;reg_1v5&gt;;</div><div class='add'>+		DOVDD-supply = &lt;&amp;reg_1v8&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			ov5640_mipi_1_ep: endpoint {</div><div class='add'>+				bus-type = &lt;MEDIA_BUS_TYPE_CSI2_DPHY&gt;;</div><div class='add'>+				data-lanes = &lt;1 2&gt;;</div><div class='add'>+				remote-endpoint = &lt;&amp;mipi_csi1_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;irqsteer_csi1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;isi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_csi_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@0 {</div><div class='add'>+			mipi_csi1_in: endpoint {</div><div class='add'>+				data-lanes = &lt;1 2&gt;;</div><div class='add'>+				remote-endpoint = &lt;&amp;ov5640_mipi_1_ep&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts<br/>new file mode 100644<br/>index 000000000000..779d9f78fb81<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8qm-mek.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8qm-mek.dts</a></div><div class='hunk'>@@ -0,0 +1,1337 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2018-2019 NXP</div><div class='add'>+ *	Dong Aisheng &lt;aisheng.dong@nxp.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/usb/pd.h&gt;</div><div class='add'>+#include "imx8qm.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Freescale i.MX8QM MEK";</div><div class='add'>+	compatible = "fsl,imx8qm-mek", "fsl,imx8qm";</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;lpuart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		/delete-node/ cpu-map;</div><div class='add'>+		/delete-node/ cpu@100;</div><div class='add'>+		/delete-node/ cpu@101;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	thermal-zones {</div><div class='add'>+		/delete-node/ cpu1-thermal;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@80000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x00000000 0x80000000 0 0x40000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	xtal24m: clock-xtal24m {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+		clock-output-names = "xtal_24MHz";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		vdev0vring0: memory@90000000 {</div><div class='add'>+			reg = &lt;0 0x90000000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev0vring1: memory@90008000 {</div><div class='add'>+			reg = &lt;0 0x90008000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev1vring0: memory@90010000 {</div><div class='add'>+			reg = &lt;0 0x90010000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev1vring1: memory@90018000 {</div><div class='add'>+			reg = &lt;0 0x90018000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rsc_table0: memory@900ff000 {</div><div class='add'>+			reg = &lt;0 0x900ff000 0 0x1000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev2vring0: memory@90100000 {</div><div class='add'>+			reg = &lt;0 0x90100000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev2vring1: memory@90108000 {</div><div class='add'>+			reg = &lt;0 0x90108000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev3vring0: memory@90110000 {</div><div class='add'>+			reg = &lt;0 0x90110000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev3vring1: memory@90118000 {</div><div class='add'>+			reg = &lt;0 0x90118000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rsc_table1: memory@901ff000 {</div><div class='add'>+			reg = &lt;0 0x901ff000 0 0x1000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdevbuffer: memory@90400000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x90400000 0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dsp_reserved: memory@92400000 {</div><div class='add'>+			reg = &lt;0 0x92400000 0 0x1000000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dsp_vdev0vring0: memory@942f0000 {</div><div class='add'>+			reg = &lt;0 0x942f0000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dsp_vdev0vring1: memory@942f8000 {</div><div class='add'>+			reg = &lt;0 0x942f8000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dsp_vdev0buffer: memory@94300000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x94300000 0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* global autoconfigured region for contiguous allocations */</div><div class='add'>+		linux,cma {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			alloc-ranges = &lt;0 0xc0000000 0 0x3c000000&gt;;</div><div class='add'>+			size = &lt;0 0x3c000000&gt;;</div><div class='add'>+			linux,cma-default;</div><div class='add'>+			reusable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lvds_backlight0: backlight-lvds0 {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		pwms = &lt;&amp;qm_pwm_lvds0 0 100000 0&gt;;</div><div class='add'>+		brightness-levels = &lt;0 100&gt;;</div><div class='add'>+		num-interpolated-steps = &lt;100&gt;;</div><div class='add'>+		default-brightness-level = &lt;80&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lvds_backlight1: backlight-lvds1 {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		pwms = &lt;&amp;pwm_lvds1 0 100000 0&gt;;</div><div class='add'>+		brightness-levels = &lt;0 100&gt;;</div><div class='add'>+		num-interpolated-steps = &lt;100&gt;;</div><div class='add'>+		default-brightness-level = &lt;80&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c-mux {</div><div class='add'>+		compatible = "i2c-mux-gpio";</div><div class='add'>+		mux-gpios = &lt;&amp;lsio_gpio5 3 GPIO_ACTIVE_HIGH&gt;; /* needs to be an unused GPIO */</div><div class='add'>+		i2c-parent = &lt;&amp;i2c1&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		i2c@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			wm8960: audio-codec@1a {</div><div class='add'>+				compatible = "wlf,wm8960";</div><div class='add'>+				reg = &lt;0x1a&gt;;</div><div class='add'>+				clocks = &lt;&amp;mclkout0_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+				clock-names = "mclk";</div><div class='add'>+				assigned-clocks = &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS&gt;,</div><div class='add'>+						  &lt;&amp;mclkout0_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;786432000&gt;,</div><div class='add'>+						       &lt;49152000&gt;,</div><div class='add'>+						       &lt;12288000&gt;,</div><div class='add'>+						       &lt;12288000&gt;;</div><div class='add'>+				wlf,shared-lrclk;</div><div class='add'>+				wlf,hp-cfg = &lt;2 2 3&gt;;</div><div class='add'>+				wlf,gpio-cfg = &lt;1 3&gt;;</div><div class='add'>+				AVDD-supply = &lt;&amp;reg_audio_3v3&gt;;</div><div class='add'>+				DBVDD-supply = &lt;&amp;reg_audio_1v8&gt;;</div><div class='add'>+				DCVDD-supply = &lt;&amp;reg_audio_1v8&gt;;</div><div class='add'>+				SPKVDD1-supply = &lt;&amp;reg_audio_5v&gt;;</div><div class='add'>+				SPKVDD2-supply = &lt;&amp;reg_audio_5v&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			wm8962: wm8962@1a {</div><div class='add'>+				compatible = "wlf,wm8962";</div><div class='add'>+				reg = &lt;0x1a&gt;;</div><div class='add'>+				clocks = &lt;&amp;mclkout0_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+				assigned-clocks = &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS&gt;,</div><div class='add'>+						  &lt;&amp;mclkout0_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;786432000&gt;,</div><div class='add'>+						       &lt;49152000&gt;,</div><div class='add'>+						       &lt;12288000&gt;,</div><div class='add'>+						       &lt;12288000&gt;;</div><div class='add'>+				DCVDD-supply = &lt;&amp;reg_audio_1v8&gt;;</div><div class='add'>+				DBVDD-supply = &lt;&amp;reg_audio_1v8&gt;;</div><div class='add'>+				AVDD-supply = &lt;&amp;reg_audio_1v8&gt;;</div><div class='add'>+				CPVDD-supply = &lt;&amp;reg_audio_1v8&gt;;</div><div class='add'>+				MICVDD-supply = &lt;&amp;reg_audio_3v3&gt;;</div><div class='add'>+				PLLVDD-supply = &lt;&amp;reg_audio_1v8&gt;;</div><div class='add'>+				SPKVDD1-supply = &lt;&amp;reg_audio_5v&gt;;</div><div class='add'>+				SPKVDD2-supply = &lt;&amp;reg_audio_5v&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mux-controller {</div><div class='add'>+		compatible = "nxp,cbdtu02043", "gpio-sbu-mux";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_typec_mux&gt;;</div><div class='add'>+		select-gpios = &lt;&amp;lsio_gpio4 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;lsio_gpio4 19 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		orientation-switch;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			usb3_data_ss: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;typec_con_ss&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_1v5: regulator-1v5 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "1v5";</div><div class='add'>+		regulator-min-microvolt = &lt;1500000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1500000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_1v8: regulator-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "1v8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_2v8: regulator-2v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "2v8";</div><div class='add'>+		regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3v3: regulator-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "3v3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: usdhc2-vmmc {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "SD1_SPWR";</div><div class='add'>+		regulator-min-microvolt = &lt;3000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;lsio_gpio4 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_audio: regulator-audio {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "cs42888_supply";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_fec2_supply: regulator-fec2-nvcc {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "fec2_nvcc";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		gpio = &lt;&amp;max7322 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_can01_en: regulator-can01-gen {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "can01-en";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;pca6416 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_can2_en: regulator-can2-gen {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "can2-en";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;pca6416 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_can01_stby: regulator-can01-stby {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "can01-stby";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;pca6416 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		vin-supply = &lt;&amp;reg_can01_en&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_can2_stby: regulator-can2-stby {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "can2-stby";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;pca6416 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		vin-supply = &lt;&amp;reg_can2_en&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_pciea: regulator-pcie {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pciea_reg&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "mpcie_3v3";</div><div class='add'>+		gpio = &lt;&amp;lsio_gpio1 13 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb_otg1_vbus: regulator-usbotg1-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "usb_otg1_vbus";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;lsio_gpio4 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vref_1v8: regulator-adc-vref {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vref_1v8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_audio_5v: regulator-audio-pwr {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "audio-5v";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_audio_3v3: regulator-audio-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "audio-3v3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_audio_1v8: regulator-audio-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "audio-1v8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bt_sco_codec: audio-codec-bt {</div><div class='add'>+		compatible = "linux,bt-sco";</div><div class='add'>+		#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-bt-sco {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,name = "bt-sco-audio";</div><div class='add'>+		simple-audio-card,format = "dsp_a";</div><div class='add'>+		simple-audio-card,bitclock-inversion;</div><div class='add'>+		simple-audio-card,frame-master = &lt;&amp;btcpu&gt;;</div><div class='add'>+		simple-audio-card,bitclock-master = &lt;&amp;btcpu&gt;;</div><div class='add'>+</div><div class='add'>+		btcpu: simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;sai0&gt;;</div><div class='add'>+			dai-tdm-slot-num = &lt;2&gt;;</div><div class='add'>+			dai-tdm-slot-width = &lt;16&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		simple-audio-card,codec {</div><div class='add'>+			sound-dai = &lt;&amp;bt_sco_codec 1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-cs42888 {</div><div class='add'>+		compatible = "fsl,imx-audio-cs42888";</div><div class='add'>+		model = "imx-cs42888";</div><div class='add'>+		audio-cpu = &lt;&amp;esai0&gt;;</div><div class='add'>+		audio-codec = &lt;&amp;cs42888&gt;;</div><div class='add'>+		audio-asrc = &lt;&amp;asrc0&gt;;</div><div class='add'>+		audio-routing = "Line Out Jack", "AOUT1L",</div><div class='add'>+				"Line Out Jack", "AOUT1R",</div><div class='add'>+				"Line Out Jack", "AOUT2L",</div><div class='add'>+				"Line Out Jack", "AOUT2R",</div><div class='add'>+				"Line Out Jack", "AOUT3L",</div><div class='add'>+				"Line Out Jack", "AOUT3R",</div><div class='add'>+				"Line Out Jack", "AOUT4L",</div><div class='add'>+				"Line Out Jack", "AOUT4R",</div><div class='add'>+				"AIN1L", "Line In Jack",</div><div class='add'>+				"AIN1R", "Line In Jack",</div><div class='add'>+				"AIN2L", "Line In Jack",</div><div class='add'>+				"AIN2R", "Line In Jack";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-wm8960 {</div><div class='add'>+		compatible = "fsl,imx-audio-wm8960";</div><div class='add'>+		model = "wm8960-audio";</div><div class='add'>+		audio-cpu = &lt;&amp;sai1&gt;;</div><div class='add'>+		audio-codec = &lt;&amp;wm8960&gt;;</div><div class='add'>+		hp-det-gpios = &lt;&amp;lsio_gpio0 31 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		audio-routing = "Headphone Jack", "HP_L",</div><div class='add'>+				"Headphone Jack", "HP_R",</div><div class='add'>+				"Ext Spk", "SPK_LP",</div><div class='add'>+				"Ext Spk", "SPK_LN",</div><div class='add'>+				"Ext Spk", "SPK_RP",</div><div class='add'>+				"Ext Spk", "SPK_RN",</div><div class='add'>+				"LINPUT1", "Mic Jack",</div><div class='add'>+				"Mic Jack", "MICB";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-wm8962 {</div><div class='add'>+		compatible = "fsl,imx-audio-wm8962";</div><div class='add'>+		model = "wm8962-audio";</div><div class='add'>+		audio-cpu = &lt;&amp;sai1&gt;;</div><div class='add'>+		audio-codec = &lt;&amp;wm8962&gt;;</div><div class='add'>+		hp-det-gpios = &lt;&amp;lsio_gpio0 31 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		audio-routing = "Headphone Jack", "HPOUTL",</div><div class='add'>+				"Headphone Jack", "HPOUTR",</div><div class='add'>+				"Ext Spk", "SPKOUTL",</div><div class='add'>+				"Ext Spk", "SPKOUTR",</div><div class='add'>+				"AMIC", "MICBIAS",</div><div class='add'>+				"IN1R", "AMIC",</div><div class='add'>+				"IN3R", "AMIC";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	imx8qm-cm4-0 {</div><div class='add'>+		compatible = "fsl,imx8qm-cm4";</div><div class='add'>+		clocks = &lt;&amp;clk_dummy&gt;;</div><div class='add'>+		mbox-names = "tx", "rx", "rxdb";</div><div class='add'>+		mboxes = &lt;&amp;lsio_mu5 0 1</div><div class='add'>+			  &amp;lsio_mu5 1 1</div><div class='add'>+			  &amp;lsio_mu5 3 1&gt;;</div><div class='add'>+		memory-region = &lt;&amp;vdevbuffer&gt;, &lt;&amp;vdev0vring0&gt;, &lt;&amp;vdev0vring1&gt;,</div><div class='add'>+				&lt;&amp;vdev1vring0&gt;, &lt;&amp;vdev1vring1&gt;, &lt;&amp;rsc_table0&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_M4_0_PID0&gt;, &lt;&amp;pd IMX_SC_R_M4_0_MU_1A&gt;;</div><div class='add'>+</div><div class='add'>+		fsl,resource-id = &lt;IMX_SC_R_M4_0_PID0&gt;;</div><div class='add'>+		fsl,entry-address = &lt;0x34fe0000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	imx8qm-cm4-1 {</div><div class='add'>+		compatible = "fsl,imx8qm-cm4";</div><div class='add'>+		clocks = &lt;&amp;clk_dummy&gt;;</div><div class='add'>+		mbox-names = "tx", "rx", "rxdb";</div><div class='add'>+		mboxes = &lt;&amp;lsio_mu6 0 1</div><div class='add'>+			  &amp;lsio_mu6 1 1</div><div class='add'>+			  &amp;lsio_mu6 3 1&gt;;</div><div class='add'>+		memory-region = &lt;&amp;vdevbuffer&gt;, &lt;&amp;vdev2vring0&gt;, &lt;&amp;vdev2vring1&gt;,</div><div class='add'>+				&lt;&amp;vdev3vring0&gt;, &lt;&amp;vdev3vring1&gt;, &lt;&amp;rsc_table1&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_M4_1_PID0&gt;, &lt;&amp;pd IMX_SC_R_M4_1_MU_1A&gt;;</div><div class='add'>+</div><div class='add'>+		fsl,resource-id = &lt;IMX_SC_R_M4_1_PID0&gt;;</div><div class='add'>+		fsl,entry-address = &lt;0x38fe0000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;adc0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_adc0&gt;;</div><div class='add'>+	vref-supply = &lt;&amp;reg_vref_1v8&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;amix {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;asrc0 {</div><div class='add'>+	fsl,asrc-rate = &lt;48000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cm41_i2c {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_cm41_i2c&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pca6416: gpio@20 {</div><div class='add'>+		compatible = "ti,tca6416";</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cs42888: audio-codec@48 {</div><div class='add'>+		compatible = "cirrus,cs42888";</div><div class='add'>+		reg = &lt;0x48&gt;;</div><div class='add'>+		clocks = &lt;&amp;mclkout0_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-names = "mclk";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_cs42888_reset&gt;;</div><div class='add'>+		VA-supply = &lt;&amp;reg_audio&gt;;</div><div class='add'>+		VD-supply = &lt;&amp;reg_audio&gt;;</div><div class='add'>+		VLS-supply = &lt;&amp;reg_audio&gt;;</div><div class='add'>+		VLC-supply = &lt;&amp;reg_audio&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;lsio_gpio4 25 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL&gt;,</div><div class='add'>+				  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS&gt;,</div><div class='add'>+				  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS&gt;,</div><div class='add'>+				  &lt;&amp;mclkout0_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;786432000&gt;, &lt;49152000&gt;, &lt;12288000&gt;, &lt;12288000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cm41_intmux {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;esai0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_esai0&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;acm IMX_ADMA_ACM_ESAI0_MCLK_SEL&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS&gt;,</div><div class='add'>+			  &lt;&amp;esai0_lpcg IMX_LPCG_CLK_4&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;aud_pll_div0_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;0&gt;, &lt;786432000&gt;, &lt;49152000&gt;, &lt;12288000&gt;, &lt;49152000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hsio_phy {</div><div class='add'>+	fsl,hsio-cfg = "pciea-pcieb-sata";</div><div class='add'>+	fsl,refclk-pad-mode = "input";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	accelerometer@19 {</div><div class='add'>+		compatible = "st,lsm303agr-accel";</div><div class='add'>+		reg = &lt;0x19&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gyrometer@20 {</div><div class='add'>+		compatible = "nxp,fxas21002c";</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	light-sensor@44 {</div><div class='add'>+		compatible = "isil,isl29023";</div><div class='add'>+		reg = &lt;0x44&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;lsio_gpio4&gt;;</div><div class='add'>+		interrupts = &lt;11 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pressure-sensor@60 {</div><div class='add'>+		compatible = "fsl,mpl3115";</div><div class='add'>+		reg = &lt;0x60&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+		vddio-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	max7322: gpio@68 {</div><div class='add'>+		compatible = "maxim,max7322";</div><div class='add'>+		reg = &lt;0x68&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gyrometer@69 {</div><div class='add'>+		compatible = "st,l3g4200d-gyro";</div><div class='add'>+		reg = &lt;0x69&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ptn5110: tcpc@51 {</div><div class='add'>+		compatible = "nxp,ptn5110", "tcpci";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_typec&gt;;</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;lsio_gpio4&gt;;</div><div class='add'>+		interrupts = &lt;26 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+</div><div class='add'>+		usb_con1: connector {</div><div class='add'>+			compatible = "usb-c-connector";</div><div class='add'>+			label = "USB-C";</div><div class='add'>+			power-role = "source";</div><div class='add'>+			data-role = "dual";</div><div class='add'>+			source-pdos = &lt;PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)&gt;;</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					typec_dr_sw: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;usb3_drd_sw&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					typec_con_ss: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;usb3_data_ss&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c1_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;lsio_gpio0 14 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;lsio_gpio0 15 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1_lvds0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lvds0_lpi2c1&gt;;</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1_lvds1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lvds1_lpi2c1&gt;;</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0_mipi0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_mipi0_lpi2c0&gt;;</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0_mipi1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_mipi1_lpi2c0&gt;;</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan1&gt;;</div><div class='add'>+	xceiver-supply = &lt;&amp;reg_can01_stby&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan2&gt;;</div><div class='add'>+	xceiver-supply = &lt;&amp;reg_can01_stby&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan3&gt;;</div><div class='add'>+	xceiver-supply = &lt;&amp;reg_can2_stby&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpuart0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpuart1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "nxp,88w8987-bt";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpuart2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpuart3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpspi2 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpspi2 &amp;pinctrl_lpspi2_cs&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;lsio_gpio3 10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_mu5 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_mu6 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexspi0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexspi0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash0: flash@0 {</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		spi-max-frequency = &lt;133000000&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;8&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;8&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec1&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	fsl,magic-packet;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@0 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ethphy1: ethernet-phy@1 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec2&gt;;</div><div class='add'>+	phy-mode = "rgmii-txid";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy1&gt;;</div><div class='add'>+	phy-supply = &lt;&amp;reg_fec2_supply&gt;;</div><div class='add'>+	nvmem-cells = &lt;&amp;fec_mac1&gt;;</div><div class='add'>+	nvmem-cell-names = "mac-address";</div><div class='add'>+	rx-internal-delay-ps = &lt;2000&gt;;</div><div class='add'>+	fsl,magic-packet;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pciea {</div><div class='add'>+	phys = &lt;&amp;hsio_phy 0 PHY_TYPE_PCIE 0&gt;;</div><div class='add'>+	phy-names = "pcie-phy";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pciea&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	reset-gpio = &lt;&amp;lsio_gpio4 29 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vpcie-supply = &lt;&amp;reg_pciea&gt;;</div><div class='add'>+	vpcie3v3aux-supply = &lt;&amp;reg_pciea&gt;;</div><div class='add'>+	supports-clkreq;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcieb {</div><div class='add'>+	phys = &lt;&amp;hsio_phy 1 PHY_TYPE_PCIE 1&gt;;</div><div class='add'>+	phy-names = "pcie-phy";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcieb&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	reset-gpio = &lt;&amp;lsio_gpio5 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qm_pwm_lvds0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm_lvds0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm_lvds1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm_lvds1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	no-sd;</div><div class='add'>+	no-sdio;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;lsio_gpio5 22 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	wp-gpios = &lt;&amp;lsio_gpio5 21 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbphy1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usb_otg1_vbus&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usbotg1&gt;;</div><div class='add'>+	srp-disable;</div><div class='add'>+	hnp-disable;</div><div class='add'>+	adp-disable;</div><div class='add'>+	disable-over-current;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg3_cdns3 {</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	port {</div><div class='add'>+		usb3_drd_sw: endpoint {</div><div class='add'>+			remote-endpoint = &lt;&amp;typec_dr_sw&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai0 {</div><div class='add'>+	#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS&gt;,</div><div class='add'>+			  &lt;&amp;sai0_lpcg IMX_LPCG_CLK_4&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;786432000&gt;, &lt;49152000&gt;, &lt;12288000&gt;, &lt;49152000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai1 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS&gt;,</div><div class='add'>+			  &lt;&amp;sai1_lpcg IMX_LPCG_CLK_4&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;786432000&gt;, &lt;49152000&gt;, &lt;12288000&gt;, &lt;49152000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai6 {</div><div class='add'>+	assigned-clocks = &lt;&amp;acm IMX_ADMA_ACM_SAI6_MCLK_SEL&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS&gt;,</div><div class='add'>+			  &lt;&amp;sai6_lpcg IMX_LPCG_CLK_4&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;aud_pll_div1_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;0&gt;, &lt;786432000&gt;, &lt;98304000&gt;, &lt;12288000&gt;, &lt;98304000&gt;;</div><div class='add'>+	fsl,sai-asynchronous;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai7 {</div><div class='add'>+	assigned-clocks = &lt;&amp;acm IMX_ADMA_ACM_SAI7_MCLK_SEL&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS&gt;,</div><div class='add'>+			  &lt;&amp;sai7_lpcg IMX_LPCG_CLK_4&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;aud_pll_div1_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;0&gt;, &lt;786432000&gt;, &lt;98304000&gt;, &lt;12288000&gt;, &lt;98304000&gt;;</div><div class='add'>+	fsl,sai-asynchronous;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sata {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;vpu_dsp {</div><div class='add'>+	memory-region = &lt;&amp;dsp_vdev0buffer&gt;, &lt;&amp;dsp_vdev0vring0&gt;,</div><div class='add'>+			&lt;&amp;dsp_vdev0vring1&gt;, &lt;&amp;dsp_reserved&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;thermal_zones {</div><div class='add'>+	pmic-thermal {</div><div class='add'>+		polling-delay-passive = &lt;250&gt;;</div><div class='add'>+		polling-delay = &lt;2000&gt;;</div><div class='add'>+		thermal-sensors = &lt;&amp;tsens IMX_SC_R_PMIC_0&gt;;</div><div class='add'>+</div><div class='add'>+		trips {</div><div class='add'>+			pmic_alert0: trip0 {</div><div class='add'>+				temperature = &lt;110000&gt;;</div><div class='add'>+				hysteresis = &lt;2000&gt;;</div><div class='add'>+				type = "passive";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pmic_crit0: trip1 {</div><div class='add'>+				temperature = &lt;125000&gt;;</div><div class='add'>+				hysteresis = &lt;2000&gt;;</div><div class='add'>+				type = "critical";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cooling-maps {</div><div class='add'>+			map0 {</div><div class='add'>+				trip = &lt;&amp;pmic_alert0&gt;;</div><div class='add'>+				cooling-device = &lt;&amp;A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+						 &lt;&amp;A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+						 &lt;&amp;A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+						 &lt;&amp;A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hog&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl_hog: hoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0			0x0600004c</div><div class='add'>+			IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31			0x0600004c</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_cs42888_reset: cs42888_resetgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QM_QSPI1A_DATA1_LSIO_GPIO4_IO25			0x0600004c</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c_mipi_csi0: i2c-mipi-csi0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QM_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL		0xc2000020</div><div class='add'>+			IMX8QM_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA		0xc2000020</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c_mipi_csi1: i2c-mipi-csi1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QM_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL		0xc2000020</div><div class='add'>+			IMX8QM_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA		0xc2000020</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c0: i2c0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL			0x06000021</div><div class='add'>+			IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA			0x06000021</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0x0600004c</div><div class='add'>+			IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA 0x0600004c</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c1_gpio: i2c1gpio-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QM_GPT0_CLK_LSIO_GPIO0_IO14		0xc600004c</div><div class='add'>+			IMX8QM_GPT0_CAPTURE_LSIO_GPIO0_IO15	0xc600004c</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_adc0: adc0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QM_ADC_IN0_DMA_ADC0_IN0				0xc0000060</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_cm41_i2c: cm41i2cgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QM_M41_I2C0_SDA_M41_I2C0_SDA			0x0600004c</div><div class='add'>+			IMX8QM_M41_I2C0_SCL_M41_I2C0_SCL			0x0600004c</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_esai0: esai0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR				0xc6000040</div><div class='add'>+			IMX8QM_ESAI0_FST_AUD_ESAI0_FST				0xc6000040</div><div class='add'>+			IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR			0xc6000040</div><div class='add'>+			IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT			0xc6000040</div><div class='add'>+			IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0				0xc6000040</div><div class='add'>+			IMX8QM_ESAI0_TX1_AUD_ESAI0_TX1				0xc6000040</div><div class='add'>+			IMX8QM_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3			0xc6000040</div><div class='add'>+			IMX8QM_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2			0xc6000040</div><div class='add'>+			IMX8QM_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1			0xc6000040</div><div class='add'>+			IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0			0xc6000040</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec1: fec1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QM_ENET0_MDC_CONN_ENET0_MDC				0x06000020</div><div class='add'>+			IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020</div><div class='add'>+			IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x06000020</div><div class='add'>+			IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC		0x06000020</div><div class='add'>+			IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0		0x06000020</div><div class='add'>+			IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1		0x06000020</div><div class='add'>+			IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2		0x06000020</div><div class='add'>+			IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3		0x06000020</div><div class='add'>+			IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC		0x06000020</div><div class='add'>+			IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x06000020</div><div class='add'>+			IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0		0x06000020</div><div class='add'>+			IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1		0x06000020</div><div class='add'>+			IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2		0x06000020</div><div class='add'>+			IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3		0x06000020</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpspi2: lpspi2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QM_SPI2_SCK_DMA_SPI2_SCK		0x06000040</div><div class='add'>+			IMX8QM_SPI2_SDO_DMA_SPI2_SDO		0x06000040</div><div class='add'>+			IMX8QM_SPI2_SDI_DMA_SPI2_SDI		0x06000040</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpspi2_cs: lpspi2csgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10		0x21</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_mipi0_lpi2c0: mipi0_lpi2c0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QM_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL	0xc6000020</div><div class='add'>+			IMX8QM_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA	0xc6000020</div><div class='add'>+			IMX8QM_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO19	0x00000020</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_mipi1_lpi2c0: mipi1_lpi2c0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QM_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL	0xc6000020</div><div class='add'>+			IMX8QM_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA	0xc6000020</div><div class='add'>+			IMX8QM_MIPI_DSI1_GPIO0_01_LSIO_GPIO1_IO23	0x00000020</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexspi0: flexspi0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0		0x06000021</div><div class='add'>+			IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1		0x06000021</div><div class='add'>+			IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2		0x06000021</div><div class='add'>+			IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3		0x06000021</div><div class='add'>+			IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS		0x06000021</div><div class='add'>+			IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B		0x06000021</div><div class='add'>+			IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B		0x06000021</div><div class='add'>+			IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK		0x06000021</div><div class='add'>+			IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK		0x06000021</div><div class='add'>+			IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0		0x06000021</div><div class='add'>+			IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1		0x06000021</div><div class='add'>+			IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2		0x06000021</div><div class='add'>+			IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3		0x06000021</div><div class='add'>+			IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS		0x06000021</div><div class='add'>+			IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B		0x06000021</div><div class='add'>+			IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B		0x06000021</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec2: fec2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD		0x000014a0</div><div class='add'>+			IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL	0x00000060</div><div class='add'>+			IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC		0x00000060</div><div class='add'>+			IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0		0x00000060</div><div class='add'>+			IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1		0x00000060</div><div class='add'>+			IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2		0x00000060</div><div class='add'>+			IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3		0x00000060</div><div class='add'>+			IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC		0x00000060</div><div class='add'>+			IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL	0x00000060</div><div class='add'>+			IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0		0x00000060</div><div class='add'>+			IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1		0x00000060</div><div class='add'>+			IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2		0x00000060</div><div class='add'>+			IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3		0x00000060</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan1: flexcan0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX			0x21</div><div class='add'>+			IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX			0x21</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan2: flexcan1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX			0x21</div><div class='add'>+			IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX			0x21</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan3: flexcan3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX			0x21</div><div class='add'>+			IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX			0x21</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpuart0: lpuart0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QM_UART0_RX_DMA_UART0_RX				0x06000020</div><div class='add'>+			IMX8QM_UART0_TX_DMA_UART0_TX				0x06000020</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpuart1: lpuart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QM_UART1_RX_DMA_UART1_RX				0x06000020</div><div class='add'>+			IMX8QM_UART1_TX_DMA_UART1_TX				0x06000020</div><div class='add'>+			IMX8QM_UART1_CTS_B_DMA_UART1_CTS_B			0x06000020</div><div class='add'>+			IMX8QM_UART1_RTS_B_DMA_UART1_RTS_B			0x06000020</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpuart2: lpuart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QM_UART0_RTS_B_DMA_UART2_RX				0x06000020</div><div class='add'>+			IMX8QM_UART0_CTS_B_DMA_UART2_TX				0x06000020</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpuart3: lpuart3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QM_M41_GPIO0_00_DMA_UART3_RX			0x06000020</div><div class='add'>+			IMX8QM_M41_GPIO0_01_DMA_UART3_TX			0x06000020</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QM_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL	0xc600004c</div><div class='add'>+			IMX8QM_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA	0xc600004c</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QM_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL	0xc600004c</div><div class='add'>+			IMX8QM_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA	0xc600004c</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_mipi_csi0: mipi-csi0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QM_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27		0xC0000041</div><div class='add'>+			IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28		0xC0000041</div><div class='add'>+			IMX8QM_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT	0xC0000041</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_mipi_csi1: mipi-csi1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30		0xC0000041</div><div class='add'>+			IMX8QM_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31		0xC0000041</div><div class='add'>+			IMX8QM_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT	0xC0000041</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pciea: pcieagrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28		0x04000021</div><div class='add'>+			IMX8QM_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29		0x06000021</div><div class='add'>+			IMX8QM_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K	0x20</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pciea_reg: pcieareggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13			0x06000021</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcieb: pciebgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QM_PCIE_CTRL1_CLKREQ_B_HSIO_PCIE1_CLKREQ_B		0x06000021</div><div class='add'>+			IMX8QM_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31		0x04000021</div><div class='add'>+			IMX8QM_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00		0x06000021</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm_lvds0: pwmlvds0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QM_LVDS0_GPIO00_LVDS0_PWM0_OUT		0x00000020</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm_lvds1: pwmlvds1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QM_LVDS1_GPIO00_LVDS1_PWM0_OUT		0x00000020</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai0: sai0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QM_SPI0_CS1_AUD_SAI0_TXC				0x0600004c</div><div class='add'>+			IMX8QM_SPI2_CS1_AUD_SAI0_TXFS				0x0600004c</div><div class='add'>+			IMX8QM_SAI1_RXFS_AUD_SAI0_RXD				0x0600004c</div><div class='add'>+			IMX8QM_SAI1_RXC_AUD_SAI0_TXD				0x0600006c</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai1: sai1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QM_SAI1_RXD_AUD_SAI1_RXD				0x06000040</div><div class='add'>+			IMX8QM_SAI1_TXFS_AUD_SAI1_TXFS				0x06000040</div><div class='add'>+			IMX8QM_SAI1_TXD_AUD_SAI1_TXD				0x06000060</div><div class='add'>+			IMX8QM_SAI1_TXC_AUD_SAI1_TXC				0x06000040</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_typec: typecgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QM_QSPI1A_DATA0_LSIO_GPIO4_IO26		0x00000021</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_typec_mux: typecmuxgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QM_QSPI1A_SS0_B_LSIO_GPIO4_IO19		0x60</div><div class='add'>+			IMX8QM_USB_SS3_TC3_LSIO_GPIO4_IO06		0x60</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usbotg1: usbotg1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QM_USB_SS3_TC0_LSIO_GPIO4_IO03		0x06000021</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK				0x06000041</div><div class='add'>+			IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD				0x00000021</div><div class='add'>+			IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0			0x00000021</div><div class='add'>+			IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1			0x00000021</div><div class='add'>+			IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2			0x00000021</div><div class='add'>+			IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3			0x00000021</div><div class='add'>+			IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4			0x00000021</div><div class='add'>+			IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5			0x00000021</div><div class='add'>+			IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6			0x00000021</div><div class='add'>+			IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7			0x00000021</div><div class='add'>+			IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE			0x00000041</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK			0x06000041</div><div class='add'>+			IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD			0x00000021</div><div class='add'>+			IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0			0x00000021</div><div class='add'>+			IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1			0x00000021</div><div class='add'>+			IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2			0x00000021</div><div class='add'>+			IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3			0x00000021</div><div class='add'>+			IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x00000021</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21			0x00000021</div><div class='add'>+			IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22			0x00000021</div><div class='add'>+			IMX8QM_USDHC1_RESET_B_LSIO_GPIO4_IO07			0x00000021</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi<br/>new file mode 100644<br/>index 000000000000..7c5386d4ab2b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi</a></div><div class='hunk'>@@ -0,0 +1,475 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 NXP</div><div class='add'>+ *	Dong Aisheng &lt;aisheng.dong@nxp.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/delete-node/ &amp;acm;</div><div class='add'>+/delete-node/ &amp;sai4;</div><div class='add'>+/delete-node/ &amp;sai5;</div><div class='add'>+/delete-node/ &amp;sai4_lpcg;</div><div class='add'>+/delete-node/ &amp;sai5_lpcg;</div><div class='add'>+</div><div class='add'>+&amp;amix {</div><div class='add'>+	dais = &lt;&amp;sai6&gt;, &lt;&amp;sai7&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;asrc0 {</div><div class='add'>+	clocks = &lt;&amp;asrc0_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+		 &lt;&amp;asrc0_lpcg IMX_LPCG_CLK_2&gt;,</div><div class='add'>+		 &lt;&amp;aud_pll_div0_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+		 &lt;&amp;aud_pll_div1_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+		 &lt;&amp;acm IMX_ADMA_ACM_AUD_CLK0_SEL&gt;,</div><div class='add'>+		 &lt;&amp;acm IMX_ADMA_ACM_AUD_CLK1_SEL&gt;,</div><div class='add'>+		 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+		 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+		 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+		 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+		 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+		 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+		 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+		 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+		 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+		 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+		 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+		 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+		 &lt;&amp;clk_dummy&gt;;</div><div class='add'>+	power-domains = &lt;&amp;pd IMX_SC_R_ASRC_0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;asrc0_lpcg {</div><div class='add'>+	clocks = &lt;&amp;audio_ipg_clk&gt;,</div><div class='add'>+		 &lt;&amp;audio_ipg_clk&gt;;</div><div class='add'>+	clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_2&gt;;</div><div class='add'>+	clock-output-names = "asrc0_lpcg_ipg_clk", "asrc0_lpcg_mem_clk";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;asrc1 {</div><div class='add'>+	clocks = &lt;&amp;asrc1_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+		 &lt;&amp;asrc1_lpcg IMX_LPCG_CLK_2&gt;,</div><div class='add'>+		 &lt;&amp;aud_pll_div0_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+		 &lt;&amp;aud_pll_div1_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+		 &lt;&amp;acm IMX_ADMA_ACM_AUD_CLK0_SEL&gt;,</div><div class='add'>+		 &lt;&amp;acm IMX_ADMA_ACM_AUD_CLK1_SEL&gt;,</div><div class='add'>+		 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+		 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+		 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+		 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+		 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+		 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+		 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+		 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+		 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+		 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+		 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+		 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+		 &lt;&amp;clk_dummy&gt;;</div><div class='add'>+	power-domains = &lt;&amp;pd IMX_SC_R_ASRC_1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;asrc1_lpcg {</div><div class='add'>+	clocks = &lt;&amp;audio_ipg_clk&gt;, &lt;&amp;audio_ipg_clk&gt;;</div><div class='add'>+	clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_2&gt;;</div><div class='add'>+	clock-output-names = "asrc1_lpcg_ipg_clk", "asrc1_lpcg_mem_clk";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;audio_subsys {</div><div class='add'>+</div><div class='add'>+	sai4: sai@59080000 {</div><div class='add'>+		compatible = "fsl,imx8qm-sai";</div><div class='add'>+		reg = &lt;0x59080000 0x10000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;sai4_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+			 &lt;&amp;sai4_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;;</div><div class='add'>+		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";</div><div class='add'>+		dma-names = "rx";</div><div class='add'>+		dmas = &lt;&amp;edma0 18 0 1&gt;;</div><div class='add'>+		fsl,dataline = &lt;0 0xf 0x0&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SAI_4&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sai5: sai@59090000 {</div><div class='add'>+		compatible = "fsl,imx8qm-sai";</div><div class='add'>+		reg = &lt;0x59090000 0x10000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;sai5_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+			 &lt;&amp;sai5_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;;</div><div class='add'>+		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";</div><div class='add'>+		dma-names = "tx";</div><div class='add'>+		dmas = &lt;&amp;edma0 19 0 0&gt;;</div><div class='add'>+		fsl,dataline = &lt;0 0x0 0xf&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SAI_5&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sai4_lpcg: clock-controller@59480000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x59480000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;acm IMX_ADMA_ACM_SAI4_MCLK_SEL&gt;,</div><div class='add'>+			 &lt;&amp;audio_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_4&gt;, &lt;IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-output-names = "sai4_lpcg_mclk", "sai4_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SAI_4&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sai5_lpcg: clock-controller@59490000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x59490000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;acm IMX_ADMA_ACM_SAI5_MCLK_SEL&gt;,</div><div class='add'>+			 &lt;&amp;audio_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_4&gt;, &lt;IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-output-names = "sai5_lpcg_mclk", "sai5_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SAI_5&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	esai1: esai@59810000 {</div><div class='add'>+		compatible = "fsl,imx8qm-esai", "fsl,imx6ull-esai";</div><div class='add'>+		reg = &lt;0x59810000 0x10000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;esai1_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;esai1_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;esai1_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;;</div><div class='add'>+		clock-names = "core", "extal", "fsys", "spba";</div><div class='add'>+		dmas = &lt;&amp;edma1 6 0 1&gt;, &lt;&amp;edma1 7 0 0&gt;;</div><div class='add'>+		dma-names = "rx", "tx";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_ESAI_1&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sai6: sai@59820000 {</div><div class='add'>+		compatible = "fsl,imx8qm-sai";</div><div class='add'>+		reg = &lt;0x59820000 0x10000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;sai6_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+			 &lt;&amp;sai6_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;;</div><div class='add'>+		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";</div><div class='add'>+		dma-names = "rx", "tx";</div><div class='add'>+		dmas = &lt;&amp;edma1 8 0 1&gt;, &lt;&amp;edma1 9 0 0&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SAI_6&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sai7: sai@59830000 {</div><div class='add'>+		compatible = "fsl,imx8qm-sai";</div><div class='add'>+		reg = &lt;0x59830000 0x10000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;sai7_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+			 &lt;&amp;sai7_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+			 &lt;&amp;clk_dummy&gt;;</div><div class='add'>+		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";</div><div class='add'>+		dma-names = "tx";</div><div class='add'>+		dmas = &lt;&amp;edma1 10 0 0&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SAI_7&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	esai1_lpcg: clock-controller@59c10000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x59c10000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;acm IMX_ADMA_ACM_ESAI1_MCLK_SEL&gt;,</div><div class='add'>+			 &lt;&amp;audio_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_4&gt;, &lt;IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-output-names = "esai1_lpcg_extal_clk", "esai1_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_ESAI_1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sai6_lpcg: clock-controller@59c20000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x59c20000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;acm IMX_ADMA_ACM_SAI6_MCLK_SEL&gt;,</div><div class='add'>+			 &lt;&amp;audio_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_4&gt;, &lt;IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-output-names = "sai6_lpcg_mclk", "sai6_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SAI_6&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sai7_lpcg: clock-controller@59c30000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x59c30000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;acm IMX_ADMA_ACM_SAI7_MCLK_SEL&gt;,</div><div class='add'>+			 &lt;&amp;audio_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_4&gt;, &lt;IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-output-names = "sai7_lpcg_mclk", "sai7_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SAI_7&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	acm: acm@59e00000 {</div><div class='add'>+		compatible = "fsl,imx8qm-acm";</div><div class='add'>+		reg = &lt;0x59e00000 0x1d0000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_AUDIO_CLK_0&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_AUDIO_CLK_1&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_MCLK_OUT_0&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_MCLK_OUT_1&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_AUDIO_PLL_0&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_AUDIO_PLL_1&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_ASRC_0&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_ASRC_1&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_ESAI_0&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_ESAI_1&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_SAI_0&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_SAI_1&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_SAI_2&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_SAI_3&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_SAI_4&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_SAI_5&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_SAI_6&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_SAI_7&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_SPDIF_0&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_SPDIF_1&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_MQS_0&gt;;</div><div class='add'>+		clocks = &lt;&amp;aud_rec0_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;aud_rec1_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;aud_pll_div0_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;aud_pll_div1_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;clk_mlb_clk&gt;,</div><div class='add'>+			 &lt;&amp;clk_hdmi_rx_mclk&gt;,</div><div class='add'>+			 &lt;&amp;clk_ext_aud_mclk0&gt;,</div><div class='add'>+			 &lt;&amp;clk_ext_aud_mclk1&gt;,</div><div class='add'>+			 &lt;&amp;clk_esai0_rx_clk&gt;,</div><div class='add'>+			 &lt;&amp;clk_esai0_rx_hf_clk&gt;,</div><div class='add'>+			 &lt;&amp;clk_esai0_tx_clk&gt;,</div><div class='add'>+			 &lt;&amp;clk_esai0_tx_hf_clk&gt;,</div><div class='add'>+			 &lt;&amp;clk_esai1_rx_clk&gt;,</div><div class='add'>+			 &lt;&amp;clk_esai1_rx_hf_clk&gt;,</div><div class='add'>+			 &lt;&amp;clk_esai1_tx_clk&gt;,</div><div class='add'>+			 &lt;&amp;clk_esai1_tx_hf_clk&gt;,</div><div class='add'>+			 &lt;&amp;clk_spdif0_rx&gt;,</div><div class='add'>+			 &lt;&amp;clk_spdif0_rx&gt;,</div><div class='add'>+			 &lt;&amp;clk_sai0_rx_bclk&gt;,</div><div class='add'>+			 &lt;&amp;clk_sai0_tx_bclk&gt;,</div><div class='add'>+			 &lt;&amp;clk_sai1_rx_bclk&gt;,</div><div class='add'>+			 &lt;&amp;clk_sai1_tx_bclk&gt;,</div><div class='add'>+			 &lt;&amp;clk_sai2_rx_bclk&gt;,</div><div class='add'>+			 &lt;&amp;clk_sai3_rx_bclk&gt;,</div><div class='add'>+			 &lt;&amp;clk_sai4_rx_bclk&gt;,</div><div class='add'>+			 &lt;&amp;clk_sai5_rx_bclk&gt;,</div><div class='add'>+			 &lt;&amp;clk_sai6_rx_bclk&gt;;</div><div class='add'>+		clock-names = "aud_rec_clk0_lpcg_clk",</div><div class='add'>+			      "aud_rec_clk1_lpcg_clk",</div><div class='add'>+			      "aud_pll_div_clk0_lpcg_clk",</div><div class='add'>+			      "aud_pll_div_clk1_lpcg_clk",</div><div class='add'>+			      "mlb_clk",</div><div class='add'>+			      "hdmi_rx_mclk",</div><div class='add'>+			      "ext_aud_mclk0",</div><div class='add'>+			      "ext_aud_mclk1",</div><div class='add'>+			      "esai0_rx_clk",</div><div class='add'>+			      "esai0_rx_hf_clk",</div><div class='add'>+			      "esai0_tx_clk",</div><div class='add'>+			      "esai0_tx_hf_clk",</div><div class='add'>+			      "esai1_rx_clk",</div><div class='add'>+			      "esai1_rx_hf_clk",</div><div class='add'>+			      "esai1_tx_clk",</div><div class='add'>+			      "esai1_tx_hf_clk",</div><div class='add'>+			      "spdif0_rx",</div><div class='add'>+			      "spdif1_rx",</div><div class='add'>+			      "sai0_rx_bclk",</div><div class='add'>+			      "sai0_tx_bclk",</div><div class='add'>+			      "sai1_rx_bclk",</div><div class='add'>+			      "sai1_tx_bclk",</div><div class='add'>+			      "sai2_rx_bclk",</div><div class='add'>+			      "sai3_rx_bclk",</div><div class='add'>+			      "sai4_rx_bclk",</div><div class='add'>+			      "sai5_tx_bclk",</div><div class='add'>+			      "sai6_rx_bclk";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsp_lpcg {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsp_ram_lpcg {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* edma2 called in imx8qm RM with the same address in edma0 of imx8qxp */</div><div class='add'>+&amp;edma0 {</div><div class='add'>+	reg = &lt;0x591f0000 0x150000&gt;;</div><div class='add'>+	dma-channels = &lt;20&gt;;</div><div class='add'>+	dma-channel-mask = &lt;0&gt;;</div><div class='add'>+	interrupts = &lt;GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH&gt;, /* asrc0 */</div><div class='add'>+		     &lt;GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH&gt;, /* esai0 */</div><div class='add'>+		     &lt;GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH&gt;, /* spdif0 */</div><div class='add'>+		     &lt;GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH&gt;, /* spdif1 */</div><div class='add'>+		     &lt;GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH&gt;, /* sai0 */</div><div class='add'>+		     &lt;GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH&gt;, /* sai1 */</div><div class='add'>+		     &lt;GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH&gt;, /* sai2 */</div><div class='add'>+		     &lt;GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH&gt;, /* sai3 */</div><div class='add'>+		     &lt;GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH&gt;, /* sai4 */</div><div class='add'>+		     &lt;GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH&gt;, /* sai5 */</div><div class='add'>+		     &lt;GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	power-domains = &lt;&amp;pd IMX_SC_R_DMA_2_CH0&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_2_CH1&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_2_CH2&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_2_CH3&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_2_CH4&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_2_CH5&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_2_CH6&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_2_CH7&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_2_CH8&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_2_CH9&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_2_CH10&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_2_CH11&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_2_CH12&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_2_CH13&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_2_CH14&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_2_CH15&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_2_CH16&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_2_CH17&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_2_CH18&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_2_CH19&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* edma3 called in imx8qm RM with the same address in edma1 of imx8qxp */</div><div class='add'>+&amp;edma1 {</div><div class='add'>+	reg = &lt;0x599f0000 0xc0000&gt;;</div><div class='add'>+	dma-channels = &lt;11&gt;;</div><div class='add'>+	dma-channel-mask = &lt;0xc0&gt;;</div><div class='add'>+	interrupts = &lt;GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH&gt;, /* asrc1 */</div><div class='add'>+		     &lt;GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH&gt;, /* no used */</div><div class='add'>+		     &lt;GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH&gt;, /* no used */</div><div class='add'>+		     &lt;GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH&gt;, /* sai6 */</div><div class='add'>+		     &lt;GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH&gt;, /* sai7 */</div><div class='add'>+		     &lt;GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	power-domains = &lt;&amp;pd IMX_SC_R_DMA_3_CH0&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_3_CH1&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_3_CH2&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_3_CH3&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_3_CH4&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_3_CH5&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_3_CH6&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_3_CH7&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_3_CH8&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_3_CH9&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_3_CH10&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;esai0 {</div><div class='add'>+	clocks = &lt;&amp;esai0_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+		 &lt;&amp;esai0_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+		 &lt;&amp;esai0_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+		 &lt;&amp;clk_dummy&gt;;</div><div class='add'>+	power-domains = &lt;&amp;pd IMX_SC_R_ESAI_0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;esai0_lpcg {</div><div class='add'>+	clock-indices = &lt;IMX_LPCG_CLK_4&gt;, &lt;IMX_LPCG_CLK_0&gt;;</div><div class='add'>+	clock-output-names = "esai0_lpcg_extal_clk", "esai0_lpcg_ipg_clk";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mqs0_lpcg {</div><div class='add'>+	clock-indices = &lt;IMX_LPCG_CLK_4&gt;, &lt;IMX_LPCG_CLK_0&gt;;</div><div class='add'>+	clock-output-names = "mqs0_lpcg_mclk", "mqs0_lpcg_ipg_clk";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai0 {</div><div class='add'>+	clocks = &lt;&amp;sai0_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+		 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+		 &lt;&amp;sai0_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+		 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+		 &lt;&amp;clk_dummy&gt;;</div><div class='add'>+	power-domains = &lt;&amp;pd IMX_SC_R_SAI_0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai0_lpcg {</div><div class='add'>+	clock-indices = &lt;IMX_LPCG_CLK_4&gt;, &lt;IMX_LPCG_CLK_0&gt;;</div><div class='add'>+	clock-output-names = "sai0_lpcg_mclk", "sai0_lpcg_ipg_clk";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai1 {</div><div class='add'>+	clocks = &lt;&amp;sai1_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+		 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+		 &lt;&amp;sai1_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+		 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+		 &lt;&amp;clk_dummy&gt;;</div><div class='add'>+	power-domains = &lt;&amp;pd IMX_SC_R_SAI_1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai1_lpcg {</div><div class='add'>+	clock-indices = &lt;IMX_LPCG_CLK_4&gt;, &lt;IMX_LPCG_CLK_0&gt;;</div><div class='add'>+	clock-output-names = "sai1_lpcg_mclk", "sai1_lpcg_ipg_clk";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai2 {</div><div class='add'>+	clocks = &lt;&amp;sai2_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+		 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+		 &lt;&amp;sai2_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+		 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+		 &lt;&amp;clk_dummy&gt;;</div><div class='add'>+	power-domains = &lt;&amp;pd IMX_SC_R_SAI_2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai2_lpcg {</div><div class='add'>+	clock-indices = &lt;IMX_LPCG_CLK_4&gt;, &lt;IMX_LPCG_CLK_0&gt;;</div><div class='add'>+	clock-output-names = "sai2_lpcg_mclk", "sai2_lpcg_ipg_clk";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai3 {</div><div class='add'>+	clocks = &lt;&amp;sai3_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+		 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+		 &lt;&amp;sai3_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+		 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+		 &lt;&amp;clk_dummy&gt;;</div><div class='add'>+	power-domains = &lt;&amp;pd IMX_SC_R_SAI_3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai3_lpcg {</div><div class='add'>+	clock-indices = &lt;IMX_LPCG_CLK_4&gt;, &lt;IMX_LPCG_CLK_0&gt;;</div><div class='add'>+	clock-output-names = "sai3_lpcg_mclk", "sai3_lpcg_ipg_clk";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spdif0 {</div><div class='add'>+	clocks = &lt;&amp;spdif0_lpcg IMX_LPCG_CLK_4&gt;,	/* core */</div><div class='add'>+		 &lt;&amp;clk_dummy&gt;,			/* rxtx0 */</div><div class='add'>+		 &lt;&amp;spdif0_lpcg IMX_LPCG_CLK_5&gt;,	/* rxtx1 */</div><div class='add'>+		 &lt;&amp;clk_dummy&gt;,			/* rxtx2 */</div><div class='add'>+		 &lt;&amp;clk_dummy&gt;,			/* rxtx3 */</div><div class='add'>+		 &lt;&amp;clk_dummy&gt;,			/* rxtx4 */</div><div class='add'>+		 &lt;&amp;audio_ipg_clk&gt;,		/* rxtx5 */</div><div class='add'>+		 &lt;&amp;clk_dummy&gt;,			/* rxtx6 */</div><div class='add'>+		 &lt;&amp;clk_dummy&gt;,			/* rxtx7 */</div><div class='add'>+		 &lt;&amp;clk_dummy&gt;;			/* spba */</div><div class='add'>+	power-domains = &lt;&amp;pd IMX_SC_R_SPDIF_0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spdif0_lpcg {</div><div class='add'>+	clock-indices = &lt;IMX_LPCG_CLK_5&gt;, &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+	clock-output-names = "spdif0_lpcg_tx_clk", "spdif0_lpcg_gclkw";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi<br/>new file mode 100644<br/>index 000000000000..ccf9f510e0f8<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi</a></div><div class='hunk'>@@ -0,0 +1,34 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2019-2020 NXP</div><div class='add'>+ *	Dong Aisheng &lt;aisheng.dong@nxp.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;usbphy1 {</div><div class='add'>+	compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	compatible = "fsl,imx8qm-fec", "fsl,imx6sx-fec";</div><div class='add'>+	iommus = &lt;&amp;smmu 0x12 0x7f80&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec2 {</div><div class='add'>+	compatible = "fsl,imx8qm-fec", "fsl,imx6sx-fec";</div><div class='add'>+	iommus = &lt;&amp;smmu 0x12 0x7f80&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";</div><div class='add'>+	iommus = &lt;&amp;smmu 0x11 0x7f80&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";</div><div class='add'>+	iommus = &lt;&amp;smmu 0x11 0x7f80&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";</div><div class='add'>+	iommus = &lt;&amp;smmu 0x11 0x7f80&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi<br/>new file mode 100644<br/>index 000000000000..5f24850bf322<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi</a></div><div class='hunk'>@@ -0,0 +1,211 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2018-2019 NXP</div><div class='add'>+ *	Dong Aisheng &lt;aisheng.dong@nxp.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/delete-node/ &amp;adma_pwm;</div><div class='add'>+/delete-node/ &amp;adma_pwm_lpcg;</div><div class='add'>+</div><div class='add'>+&amp;dma_subsys {</div><div class='add'>+	uart4_lpcg: clock-controller@5a4a0000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5a4a0000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_UART_4 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;dma_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "uart4_lpcg_baud_clk",</div><div class='add'>+				     "uart4_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_UART_4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c4: i2c@5a840000 {</div><div class='add'>+		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+		reg = &lt;0x5a840000 0x4000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		clocks = &lt;&amp;i2c4_lpcg 0&gt;,</div><div class='add'>+			 &lt;&amp;i2c4_lpcg 1&gt;;</div><div class='add'>+		clock-names = "per", "ipg";</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_I2C_4 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;24000000&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_I2C_4&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c4_lpcg: clock-controller@5ac40000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5ac40000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_I2C_4 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;dma_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "i2c4_lpcg_clk",</div><div class='add'>+				     "i2c4_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_I2C_4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	can1_lpcg: clock-controller@5ace0000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5ace0000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_CAN_1 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;dma_ipg_clk&gt;, &lt;&amp;dma_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_4&gt;, &lt;IMX_LPCG_CLK_5&gt;;</div><div class='add'>+		clock-output-names = "can1_lpcg_pe_clk",</div><div class='add'>+				     "can1_lpcg_ipg_clk",</div><div class='add'>+				     "can1_lpcg_chi_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_CAN_1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	can2_lpcg: clock-controller@5acf0000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5acf0000 0x10000&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_CAN_2 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;dma_ipg_clk&gt;, &lt;&amp;dma_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_4&gt;, &lt;IMX_LPCG_CLK_5&gt;;</div><div class='add'>+		clock-output-names = "can2_lpcg_pe_clk",</div><div class='add'>+				     "can2_lpcg_ipg_clk",</div><div class='add'>+				     "can2_lpcg_chi_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_CAN_2&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;edma2 {</div><div class='add'>+	reg = &lt;0x5a1f0000 0x170000&gt;;</div><div class='add'>+	#dma-cells = &lt;3&gt;;</div><div class='add'>+	dma-channels = &lt;22&gt;;</div><div class='add'>+	dma-channel-mask = &lt;0xf00&gt;;</div><div class='add'>+	interrupts = &lt;GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH&gt;, /* unused */</div><div class='add'>+		     &lt;GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH&gt;, /* unused */</div><div class='add'>+		     &lt;GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH&gt;, /* unused */</div><div class='add'>+		     &lt;GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH&gt;, /* unused */</div><div class='add'>+		     &lt;GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	power-domains = &lt;&amp;pd IMX_SC_R_DMA_0_CH0&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_0_CH1&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_0_CH2&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_0_CH3&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_0_CH4&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_0_CH5&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_0_CH6&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_0_CH7&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_0_CH8&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_0_CH9&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_0_CH10&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_0_CH11&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_0_CH12&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_0_CH13&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_0_CH14&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_0_CH15&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_0_CH16&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_0_CH17&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_0_CH18&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_0_CH19&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_0_CH20&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_0_CH21&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* It is eDMA1 in 8QM RM, but 8QXP it is eDMA3 */</div><div class='add'>+&amp;edma3 {</div><div class='add'>+	reg = &lt;0x5a9f0000 0x210000&gt;;</div><div class='add'>+	dma-channels = &lt;10&gt;;</div><div class='add'>+	interrupts = &lt;GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	power-domains = &lt;&amp;pd IMX_SC_R_DMA_1_CH0&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_1_CH1&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_1_CH2&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_1_CH3&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_1_CH4&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_1_CH5&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_1_CH6&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_1_CH7&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_1_CH8&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_DMA_1_CH9&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	fsl,clk-source = /bits/ 8 &lt;1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan2 {</div><div class='add'>+	clocks = &lt;&amp;can1_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+		 &lt;&amp;can1_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX_SC_R_CAN_1 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+	fsl,clk-source = /bits/ 8 &lt;1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan3 {</div><div class='add'>+	clocks = &lt;&amp;can2_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+		 &lt;&amp;can2_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX_SC_R_CAN_2 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+	fsl,clk-source = /bits/ 8 &lt;1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart0 {</div><div class='add'>+	compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";</div><div class='add'>+	dmas = &lt;&amp;edma2 13 0 0&gt;, &lt;&amp;edma2 12 0 1&gt;;</div><div class='add'>+	dma-names = "rx","tx";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart1 {</div><div class='add'>+	compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";</div><div class='add'>+	dmas = &lt;&amp;edma2 15 0 0&gt;, &lt;&amp;edma2 14 0 1&gt;;</div><div class='add'>+	dma-names = "rx","tx";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart2 {</div><div class='add'>+	compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";</div><div class='add'>+	dmas = &lt;&amp;edma2 17 0 0&gt;, &lt;&amp;edma2 16 0 1&gt;;</div><div class='add'>+	dma-names = "rx","tx";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart3 {</div><div class='add'>+	compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";</div><div class='add'>+	dmas = &lt;&amp;edma2 19 0 0&gt;, &lt;&amp;edma2 18 0 1&gt;;</div><div class='add'>+	dma-names = "rx","tx";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi<br/>new file mode 100644<br/>index 000000000000..bd6e0aa27efe<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi</a></div><div class='hunk'>@@ -0,0 +1,229 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 NXP</div><div class='add'>+ *	Richard Zhu &lt;hongxing.zhu@nxp.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;hsio_subsys {</div><div class='add'>+	compatible = "simple-bus";</div><div class='add'>+	ranges = &lt;0x5f000000 0x0 0x5f000000 0x01000000&gt;,</div><div class='add'>+		 &lt;0x40000000 0x0 0x60000000 0x10000000&gt;,</div><div class='add'>+		 &lt;0x80000000 0x0 0x70000000 0x10000000&gt;;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+	pcie0: pciea: pcie@5f000000 {</div><div class='add'>+		compatible = "fsl,imx8q-pcie";</div><div class='add'>+		reg = &lt;0x5f000000 0x10000&gt;,</div><div class='add'>+		      &lt;0x4ff00000 0x80000&gt;;</div><div class='add'>+		reg-names = "dbi", "config";</div><div class='add'>+		ranges = &lt;0x81000000 0 0x00000000 0x4ff80000 0 0x00010000&gt;,</div><div class='add'>+			 &lt;0x82000000 0 0x40000000 0x40000000 0 0x0ff00000&gt;;</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-names = "msi";</div><div class='add'>+		#address-cells = &lt;3&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		clocks = &lt;&amp;pciea_lpcg IMX_LPCG_CLK_6&gt;,</div><div class='add'>+			 &lt;&amp;pciea_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;pciea_lpcg IMX_LPCG_CLK_5&gt;;</div><div class='add'>+		clock-names = "dbi", "mstr", "slv";</div><div class='add'>+		bus-range = &lt;0x00 0xff&gt;;</div><div class='add'>+		device_type = "pci";</div><div class='add'>+		interrupt-map = &lt;0 0 0 1 &amp;gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 0 2 &amp;gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 0 3 &amp;gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 0 4 &amp;gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-map-mask = &lt;0 0 0 0x7&gt;;</div><div class='add'>+		num-lanes = &lt;1&gt;;</div><div class='add'>+		num-viewport = &lt;4&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_PCIE_A&gt;;</div><div class='add'>+		fsl,max-link-speed = &lt;3&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_ep: pciea_ep: pcie-ep@5f000000 {</div><div class='add'>+		compatible = "fsl,imx8q-pcie-ep";</div><div class='add'>+		reg = &lt;0x5f000000 0x00010000&gt;,</div><div class='add'>+		      &lt;0x40000000 0x10000000&gt;;</div><div class='add'>+		reg-names = "dbi", "addr_space";</div><div class='add'>+		num-lanes = &lt;1&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-names = "dma";</div><div class='add'>+		clocks = &lt;&amp;pciea_lpcg IMX_LPCG_CLK_6&gt;,</div><div class='add'>+			 &lt;&amp;pciea_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;pciea_lpcg IMX_LPCG_CLK_5&gt;;</div><div class='add'>+		clock-names = "dbi", "mstr", "slv";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_PCIE_A&gt;;</div><div class='add'>+		fsl,max-link-speed = &lt;3&gt;;</div><div class='add'>+		num-ib-windows = &lt;6&gt;;</div><div class='add'>+		num-ob-windows = &lt;6&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie1: pcieb: pcie@5f010000 {</div><div class='add'>+		compatible = "fsl,imx8q-pcie";</div><div class='add'>+		reg = &lt;0x5f010000 0x10000&gt;,</div><div class='add'>+		      &lt;0x8ff00000 0x80000&gt;;</div><div class='add'>+		reg-names = "dbi", "config";</div><div class='add'>+		ranges = &lt;0x81000000 0 0x00000000 0x8ff80000 0 0x00010000&gt;,</div><div class='add'>+			 &lt;0x82000000 0 0x80000000 0x80000000 0 0x0ff00000&gt;;</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-names = "msi", "dma";</div><div class='add'>+		#address-cells = &lt;3&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		clocks = &lt;&amp;pcieb_lpcg IMX_LPCG_CLK_6&gt;,</div><div class='add'>+			 &lt;&amp;pcieb_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;pcieb_lpcg IMX_LPCG_CLK_5&gt;;</div><div class='add'>+		clock-names = "dbi", "mstr", "slv";</div><div class='add'>+		bus-range = &lt;0x00 0xff&gt;;</div><div class='add'>+		device_type = "pci";</div><div class='add'>+		interrupt-map = &lt;0 0 0 1 &amp;gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 0 2 &amp;gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 0 3 &amp;gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 0 4 &amp;gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-map-mask = &lt;0 0 0 0x7&gt;;</div><div class='add'>+		num-lanes = &lt;1&gt;;</div><div class='add'>+		num-viewport = &lt;4&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_PCIE_B&gt;;</div><div class='add'>+		fsl,max-link-speed = &lt;3&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sata: sata@5f020000 {</div><div class='add'>+		compatible = "fsl,imx8qm-ahci";</div><div class='add'>+		reg = &lt;0x5f020000 0x10000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;sata_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;sata_crr4_lpcg IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-names = "sata", "sata_ref";</div><div class='add'>+		phy-names = "sata-phy", "cali-phy0", "cali-phy1";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SATA_0&gt;;</div><div class='add'>+		/*</div><div class='add'>+		 * Since "REXT" pin is only present for first lane PHY</div><div class='add'>+		 * and its calibration result will be stored, and shared</div><div class='add'>+		 * by the PHY used by SATA.</div><div class='add'>+		 *</div><div class='add'>+		 * Add the calibration PHYs for SATA here, although only</div><div class='add'>+		 * the third lane PHY is used by SATA.</div><div class='add'>+		 */</div><div class='add'>+		phys = &lt;&amp;hsio_phy 2 PHY_TYPE_SATA 0&gt;,</div><div class='add'>+		       &lt;&amp;hsio_phy 0 PHY_TYPE_PCIE 0&gt;,</div><div class='add'>+		       &lt;&amp;hsio_phy 1 PHY_TYPE_PCIE 1&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pciea_lpcg: clock-controller@5f050000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5f050000 0x10000&gt;;</div><div class='add'>+		clocks = &lt;&amp;hsio_axi_clk&gt;, &lt;&amp;hsio_axi_clk&gt;, &lt;&amp;hsio_axi_clk&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_4&gt;, &lt;IMX_LPCG_CLK_5&gt;, &lt;IMX_LPCG_CLK_6&gt;;</div><div class='add'>+		clock-output-names = "hsio_pciea_mstr_axi_clk",</div><div class='add'>+				     "hsio_pciea_slv_axi_clk",</div><div class='add'>+				     "hsio_pciea_dbi_axi_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_PCIE_A&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sata_lpcg: clock-controller@5f070000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5f070000 0x10000&gt;;</div><div class='add'>+		clocks = &lt;&amp;hsio_axi_clk&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "hsio_sata_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SATA_0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	phyx2_lpcg: clock-controller@5f080000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5f080000 0x10000&gt;;</div><div class='add'>+		clocks = &lt;&amp;hsio_refa_clk&gt;, &lt;&amp;hsio_per_clk&gt;,</div><div class='add'>+			 &lt;&amp;hsio_refa_clk&gt;, &lt;&amp;hsio_per_clk&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_1&gt;,</div><div class='add'>+				&lt;IMX_LPCG_CLK_4&gt;, &lt;IMX_LPCG_CLK_5&gt;;</div><div class='add'>+		clock-output-names = "hsio_phyx2_pclk_0",</div><div class='add'>+				     "hsio_phyx2_pclk_1",</div><div class='add'>+				     "hsio_phyx2_apbclk_0",</div><div class='add'>+				     "hsio_phyx2_apbclk_1";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SERDES_0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	phyx1_lpcg: clock-controller@5f090000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5f090000 0x10000&gt;;</div><div class='add'>+		clocks = &lt;&amp;hsio_refa_clk&gt;, &lt;&amp;hsio_per_clk&gt;,</div><div class='add'>+			 &lt;&amp;hsio_per_clk&gt;, &lt;&amp;hsio_per_clk&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_1&gt;,</div><div class='add'>+				&lt;IMX_LPCG_CLK_2&gt;, &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "hsio_phyx1_pclk",</div><div class='add'>+				     "hsio_phyx1_epcs_tx_clk",</div><div class='add'>+				     "hsio_phyx1_epcs_rx_clk",</div><div class='add'>+				     "hsio_phyx1_apb_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SERDES_1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	phyx2_crr0_lpcg: clock-controller@5f0a0000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5f0a0000 0x10000&gt;;</div><div class='add'>+		clocks = &lt;&amp;hsio_per_clk&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "hsio_phyx2_per_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SERDES_0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pciea_crr2_lpcg: clock-controller@5f0c0000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5f0c0000 0x10000&gt;;</div><div class='add'>+		clocks = &lt;&amp;hsio_per_clk&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "hsio_pciea_per_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_PCIE_A&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sata_crr4_lpcg: clock-controller@5f0e0000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5f0e0000 0x10000&gt;;</div><div class='add'>+		clocks = &lt;&amp;hsio_per_clk&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "hsio_sata_per_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SATA_0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsio_phy: phy@5f180000 {</div><div class='add'>+		compatible = "fsl,imx8qm-hsio";</div><div class='add'>+		reg = &lt;0x5f180000 0x30000&gt;,</div><div class='add'>+		      &lt;0x5f110000 0x20000&gt;,</div><div class='add'>+		      &lt;0x5f130000 0x30000&gt;,</div><div class='add'>+		      &lt;0x5f160000 0x10000&gt;;</div><div class='add'>+		reg-names = "reg", "phy", "ctrl", "misc";</div><div class='add'>+		clocks = &lt;&amp;phyx2_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;phyx2_lpcg IMX_LPCG_CLK_1&gt;,</div><div class='add'>+			 &lt;&amp;phyx2_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;phyx2_lpcg IMX_LPCG_CLK_5&gt;,</div><div class='add'>+			 &lt;&amp;phyx1_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;phyx1_lpcg IMX_LPCG_CLK_1&gt;,</div><div class='add'>+			 &lt;&amp;phyx1_lpcg IMX_LPCG_CLK_2&gt;,</div><div class='add'>+			 &lt;&amp;phyx1_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;phyx2_crr0_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;phyx1_crr1_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;pciea_crr2_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;pcieb_crr3_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;sata_crr4_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;misc_crr5_lpcg IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-names = "pclk0", "pclk1", "apb_pclk0", "apb_pclk1",</div><div class='add'>+			      "pclk2", "epcs_tx", "epcs_rx", "apb_pclk2",</div><div class='add'>+			      "phy0_crr", "phy1_crr", "ctl0_crr",</div><div class='add'>+			      "ctl1_crr", "ctl2_crr", "misc_crr";</div><div class='add'>+		#phy-cells = &lt;3&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SERDES_0&gt;, &lt;&amp;pd IMX_SC_R_SERDES_1&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi<br/>new file mode 100644<br/>index 000000000000..4b7e685daa02<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi</a></div><div class='hunk'>@@ -0,0 +1,91 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;isi {</div><div class='add'>+	compatible = "fsl,imx8qm-isi";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		port@2 {</div><div class='add'>+			reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			isi_in_2: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;mipi_csi0_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@3 {</div><div class='add'>+			reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+			isi_in_3: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;mipi_csi1_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;jpegdec {</div><div class='add'>+	compatible = "nxp,imx8qm-jpgdec", "nxp,imx8qxp-jpgdec";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;jpegenc {</div><div class='add'>+	compatible = "nxp,imx8qm-jpgenc", "nxp,imx8qxp-jpgenc";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_csi_0 {</div><div class='add'>+	compatible = "fsl,imx8qm-mipi-csi2", "fsl,imx8qxp-mipi-csi2";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		port@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			mipi_csi0_out: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;isi_in_2&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_csi_1 {</div><div class='add'>+	compatible = "fsl,imx8qm-mipi-csi2", "fsl,imx8qxp-mipi-csi2";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		port@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			mipi_csi1_out: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;isi_in_3&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pi0_ipg_lpcg {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pi0_misc_lpcg {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pi0_pxl_lpcg {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi<br/>new file mode 100644<br/>index 000000000000..b483134f84d1<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi</a></div><div class='hunk'>@@ -0,0 +1,107 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2019-2020 NXP</div><div class='add'>+ *	Dong Aisheng &lt;aisheng.dong@nxp.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio0 {</div><div class='add'>+	compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";</div><div class='add'>+	gpio-ranges = &lt;&amp;iomuxc 0 0 6&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 6 7 22&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 28 36 4&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio1 {</div><div class='add'>+	compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";</div><div class='add'>+	gpio-ranges = &lt;&amp;iomuxc 0 40 4&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 4 50 12&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 16 63 8&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 24 72 8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio2 {</div><div class='add'>+	compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";</div><div class='add'>+	gpio-ranges = &lt;&amp;iomuxc 0 80 4&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 4 85 18&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 22 104 10&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio3 {</div><div class='add'>+	compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";</div><div class='add'>+	gpio-ranges = &lt;&amp;iomuxc 0 114 2&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 2 117 16&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 18 141 1&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 19 140 1&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 20 139 1&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 21 138 1&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 22 137 1&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 23 136 1&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 24 135 1&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 25 134 1&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 26 142 3&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 29 146 3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio4 {</div><div class='add'>+	compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";</div><div class='add'>+	gpio-ranges = &lt;&amp;iomuxc 0 149 3&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 3 153 4&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 7 158 6&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 13 165 6&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 19 172 8&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 27 198 5&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio5 {</div><div class='add'>+	compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";</div><div class='add'>+	gpio-ranges = &lt;&amp;iomuxc 0 203 1&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 1 205 2&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 3 210 11&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 14 223 3&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 17 227 2&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 19 230 5&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 24 236 6&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 30 243 2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio6 {</div><div class='add'>+	compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";</div><div class='add'>+	gpio-ranges = &lt;&amp;iomuxc 0 245 10&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 10 256 12&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio7 {</div><div class='add'>+	compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_mu0 {</div><div class='add'>+	compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_mu1 {</div><div class='add'>+	compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_mu2 {</div><div class='add'>+	compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_mu3 {</div><div class='add'>+	compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_mu4 {</div><div class='add'>+	compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_mu5 {</div><div class='add'>+	compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_mu6 {</div><div class='add'>+	compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_mu13 {</div><div class='add'>+	compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi<br/>new file mode 100644<br/>index 000000000000..0514d8b2af75<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi</a></div><div class='hunk'>@@ -0,0 +1,76 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;qm_lvds0_lis_lpcg {</div><div class='add'>+	clocks = &lt;&amp;lvds_ipg_clk&gt;;</div><div class='add'>+	clock-indices = &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qm_lvds0_pwm_lpcg {</div><div class='add'>+	clocks = &lt;&amp;clk IMX_SC_R_LVDS_0_PWM_0 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+		 &lt;&amp;lvds_ipg_clk&gt;;</div><div class='add'>+	clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qm_lvds0_i2c0_lpcg {</div><div class='add'>+	clocks = &lt;&amp;clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+		 &lt;&amp;lvds_ipg_clk&gt;;</div><div class='add'>+	clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qm_pwm_lvds0 {</div><div class='add'>+	clocks = &lt;&amp;qm_lvds0_pwm_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+		 &lt;&amp;qm_lvds0_pwm_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qm_i2c0_lvds0 {</div><div class='add'>+	clocks = &lt;&amp;qm_lvds0_i2c0_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+		 &lt;&amp;qm_lvds0_i2c0_lpcg IMX_LPCG_CLK_4&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lvds0_subsys {</div><div class='add'>+	interrupt-parent = &lt;&amp;irqsteer_lvds0&gt;;</div><div class='add'>+</div><div class='add'>+	irqsteer_lvds0: interrupt-controller@56240000 {</div><div class='add'>+		compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";</div><div class='add'>+		reg = &lt;0x56240000 0x1000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;qm_lvds0_lis_lpcg IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-names = "ipg";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_LVDS_0&gt;;</div><div class='add'>+</div><div class='add'>+		fsl,channel = &lt;0&gt;;</div><div class='add'>+		fsl,num-irqs = &lt;32&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lvds0_i2c1_lpcg: clock-controller@56243014 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x56243014 0x4&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+			 &lt;&amp;lvds_ipg_clk&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "lvds0_i2c1_lpcg_clk",</div><div class='add'>+				     "lvds0_i2c1_lpcg_ipg_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_LVDS_0_I2C_0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c1_lvds0: i2c@56247000 {</div><div class='add'>+		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+		reg = &lt;0x56247000 0x1000&gt;;</div><div class='add'>+		interrupts = &lt;9&gt;;</div><div class='add'>+		clocks = &lt;&amp;lvds0_i2c1_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;lvds0_i2c1_lpcg IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-names = "per", "ipg";</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;24000000&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_LVDS_0_I2C_0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi<br/>new file mode 100644<br/>index 000000000000..f4c393fe7204<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi</a></div><div class='hunk'>@@ -0,0 +1,19 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;mipi0_lis_lpcg {</div><div class='add'>+	clocks = &lt;&amp;dsi_ipg_clk&gt;;</div><div class='add'>+	clock-indices = &lt;IMX_LPCG_CLK_0&gt;;</div><div class='add'>+	clock-output-names = "mipi0_lis_lpcg_ipg_clk";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi0_pwm_lpcg {</div><div class='add'>+	clocks = &lt;&amp;clk IMX_SC_R_MIPI_0_PWM_0 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+		 &lt;&amp;dsi_ipg_clk&gt;;</div><div class='add'>+	clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+	clock-output-names = "mipi0_pwm_lpcg_clk",</div><div class='add'>+			     "mipi0_pwm_lpcg_ipg_clk";</div><div class='add'>+};
\ No newline at end of file</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi<br/>new file mode 100644<br/>index 000000000000..cb66853b1cd3<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8qm.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8qm.dtsi</a></div><div class='hunk'>@@ -0,0 +1,651 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2018-2019 NXP</div><div class='add'>+ *	Dong Aisheng &lt;aisheng.dong@nxp.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/imx8-lpcg.h&gt;</div><div class='add'>+#include &lt;dt-bindings/firmware/imx/rsrc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/pads-imx8qm.h&gt;</div><div class='add'>+#include &lt;dt-bindings/thermal/thermal.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		mmc0 = &amp;usdhc1;</div><div class='add'>+		mmc1 = &amp;usdhc2;</div><div class='add'>+		mmc2 = &amp;usdhc3;</div><div class='add'>+		serial0 = &amp;lpuart0;</div><div class='add'>+		serial1 = &amp;lpuart1;</div><div class='add'>+		serial2 = &amp;lpuart2;</div><div class='add'>+		serial3 = &amp;lpuart3;</div><div class='add'>+		spi0 = &amp;lpspi0;</div><div class='add'>+		spi1 = &amp;lpspi1;</div><div class='add'>+		spi2 = &amp;lpspi2;</div><div class='add'>+		spi3 = &amp;lpspi3;</div><div class='add'>+		vpu-core0 = &amp;vpu_core0;</div><div class='add'>+		vpu-core1 = &amp;vpu_core1;</div><div class='add'>+		vpu-core2 = &amp;vpu_core2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu-map {</div><div class='add'>+			cluster0 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;A53_0&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;A53_1&gt;;</div><div class='add'>+				};</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;A53_2&gt;;</div><div class='add'>+				};</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;A53_3&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cluster1 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;A72_0&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;A72_1&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		A53_0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x0 0x0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;A53_L2&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;a53_opp_table&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		A53_1: cpu@1 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x0 0x1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;A53_L2&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;a53_opp_table&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		A53_2: cpu@2 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x0 0x2&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;A53_L2&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;a53_opp_table&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		A53_3: cpu@3 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x0 0x3&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;A53_L2&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;a53_opp_table&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		A72_0: cpu@100 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a72";</div><div class='add'>+			reg = &lt;0x0 0x100&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			i-cache-size = &lt;0xC000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;A72_L2&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;a72_opp_table&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		A72_1: cpu@101 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a72";</div><div class='add'>+			reg = &lt;0x0 0x101&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;A72_L2&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;a72_opp_table&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		A53_L2: l2-cache0 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x100000&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;1024&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		A72_L2: l2-cache1 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x100000&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;1024&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	a53_opp_table: opp-table-0 {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+		opp-shared;</div><div class='add'>+</div><div class='add'>+		opp-600000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;600000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;900000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;150000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-896000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;896000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1000000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;150000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1104000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1104000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1100000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;150000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1200000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1200000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1100000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;150000&gt;;</div><div class='add'>+			opp-suspend;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	a72_opp_table: opp-table-1 {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+		opp-shared;</div><div class='add'>+</div><div class='add'>+		opp-600000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;600000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1000000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;150000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1056000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1056000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1000000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;150000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1296000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1296000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1100000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;150000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1596000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1596000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1100000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;150000&gt;;</div><div class='add'>+			opp-suspend;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gic: interrupt-controller@51a00000 {</div><div class='add'>+		compatible = "arm,gic-v3";</div><div class='add'>+		reg = &lt;0x0 0x51a00000 0 0x10000&gt;, /* GIC Dist */</div><div class='add'>+		      &lt;0x0 0x51b00000 0 0xC0000&gt;, /* GICR */</div><div class='add'>+		      &lt;0x0 0x52000000 0 0x2000&gt;,  /* GICC */</div><div class='add'>+		      &lt;0x0 0x52010000 0 0x1000&gt;,  /* GICH */</div><div class='add'>+		      &lt;0x0 0x52020000 0 0x20000&gt;; /* GICV */</div><div class='add'>+		#address-cells = &lt;0&gt;;</div><div class='add'>+		#interrupt-cells = &lt;3&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu {</div><div class='add'>+		compatible = "arm,armv8-pmuv3";</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-1.0";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 IRQ_TYPE_LEVEL_LOW&gt;, /* Physical Secure */</div><div class='add'>+			     &lt;GIC_PPI 14 IRQ_TYPE_LEVEL_LOW&gt;, /* Physical Non-Secure */</div><div class='add'>+			     &lt;GIC_PPI 11 IRQ_TYPE_LEVEL_LOW&gt;, /* Virtual */</div><div class='add'>+			     &lt;GIC_PPI 10 IRQ_TYPE_LEVEL_LOW&gt;; /* Hypervisor */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	smmu: iommu@51400000 {</div><div class='add'>+		compatible = "arm,mmu-500";</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		reg = &lt;0 0x51400000 0 0x40000&gt;;</div><div class='add'>+		#global-interrupts = &lt;1&gt;;</div><div class='add'>+		#iommu-cells = &lt;2&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	system-controller {</div><div class='add'>+		compatible = "fsl,imx-scu";</div><div class='add'>+		mbox-names = "tx0",</div><div class='add'>+			     "rx0",</div><div class='add'>+			     "gip3";</div><div class='add'>+		mboxes = &lt;&amp;lsio_mu1 0 0</div><div class='add'>+			  &amp;lsio_mu1 1 0</div><div class='add'>+			  &amp;lsio_mu1 3 3&gt;;</div><div class='add'>+</div><div class='add'>+		pd: power-controller {</div><div class='add'>+			compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd";</div><div class='add'>+			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		clk: clock-controller {</div><div class='add'>+			compatible = "fsl,imx8qm-clk", "fsl,scu-clk";</div><div class='add'>+			#clock-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		iomuxc: pinctrl {</div><div class='add'>+			compatible = "fsl,imx8qm-iomuxc";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		scu_reset: reset-controller {</div><div class='add'>+			compatible = "fsl,imx-scu-reset";</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rtc: rtc {</div><div class='add'>+			compatible = "fsl,imx8qxp-sc-rtc";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ocotp: ocotp {</div><div class='add'>+			compatible = "fsl,imx8qm-scu-ocotp";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			read-only;</div><div class='add'>+</div><div class='add'>+			fec_mac0: mac@1c4 {</div><div class='add'>+				reg = &lt;0x1c4 6&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			fec_mac1: mac@1c6 {</div><div class='add'>+				reg = &lt;0x1c6 6&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tsens: thermal-sensor {</div><div class='add'>+			compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";</div><div class='add'>+			#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		watchdog {</div><div class='add'>+			compatible = "fsl,imx8qm-sc-wdt", "fsl,imx-sc-wdt";</div><div class='add'>+			timeout-sec = &lt;60&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	thermal_zones: thermal-zones {</div><div class='add'>+		cpu0-thermal {</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			polling-delay = &lt;2000&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens IMX_SC_R_A53&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu_alert0: trip0 {</div><div class='add'>+					temperature = &lt;107000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_crit0: trip1 {</div><div class='add'>+					temperature = &lt;127000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu_alert0&gt;;</div><div class='add'>+					cooling-device =</div><div class='add'>+						&lt;&amp;A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+						&lt;&amp;A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+						&lt;&amp;A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+						&lt;&amp;A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1-thermal {</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			polling-delay = &lt;2000&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens IMX_SC_R_A72&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu_alert1: trip0 {</div><div class='add'>+					temperature = &lt;107000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_crit1: trip1 {</div><div class='add'>+					temperature = &lt;127000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu_alert1&gt;;</div><div class='add'>+					cooling-device =</div><div class='add'>+						&lt;&amp;A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+						&lt;&amp;A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu0-thermal {</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			polling-delay = &lt;2000&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens IMX_SC_R_GPU_0_PID0&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				gpu_alert0: trip0 {</div><div class='add'>+					temperature = &lt;107000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpu_crit0: trip1 {</div><div class='add'>+					temperature = &lt;127000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+	       gpu1-thermal {</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			polling-delay = &lt;2000&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens IMX_SC_R_GPU_1_PID0&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				gpu_alert1: trip0 {</div><div class='add'>+					temperature = &lt;107000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpu_crit1: trip1 {</div><div class='add'>+					temperature = &lt;127000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		drc0-thermal {</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			polling-delay = &lt;2000&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens IMX_SC_R_DRC_0&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				drc_alert0: trip0 {</div><div class='add'>+					temperature = &lt;107000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				drc_crit0: trip1 {</div><div class='add'>+					temperature = &lt;127000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_dummy: clock-dummy {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;0&gt;;</div><div class='add'>+		clock-output-names = "clk_dummy";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_esai1_rx_clk: clock-esai1-rx {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;0&gt;;</div><div class='add'>+		clock-output-names = "esai1_rx_clk";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_esai1_rx_hf_clk: clock-esai1-rx-hf {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;0&gt;;</div><div class='add'>+		clock-output-names = "esai1_rx_hf_clk";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_esai1_tx_clk: clock-esai1-tx {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;0&gt;;</div><div class='add'>+		clock-output-names = "esai1_tx_clk";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_esai1_tx_hf_clk: clock-esai1-tx-hf {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;0&gt;;</div><div class='add'>+		clock-output-names = "esai1_tx_hf_clk";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_hdmi_rx_mclk: clock-hdmi-rx-mclk {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;0&gt;;</div><div class='add'>+		clock-output-names = "hdmi-rx-mclk";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_mlb_clk: clock-mlb-clk {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;0&gt;;</div><div class='add'>+		clock-output-names = "mlb_clk";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_sai5_rx_bclk: clock-sai5-rx-bclk {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;0&gt;;</div><div class='add'>+		clock-output-names = "sai5_rx_bclk";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_sai5_tx_bclk: clock-sai5-tx-bclk {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;0&gt;;</div><div class='add'>+		clock-output-names = "sai5_tx_bclk";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_sai6_rx_bclk: clock-sai6-rx-bclk {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;0&gt;;</div><div class='add'>+		clock-output-names = "sai6_rx_bclk";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_sai6_tx_bclk: clock-sai6-tx-bclk {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;0&gt;;</div><div class='add'>+		clock-output-names = "sai6_tx_bclk";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_spdif1_rx: clock-spdif1-rx {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;0&gt;;</div><div class='add'>+		clock-output-names = "spdif1_rx";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lvds_ipg_clk: clock-controller-lvds-ipg {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+		clock-output-names = "lvds0_ipg_clk";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dsi_ipg_clk: clock-controller-dsi-ipg {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;120000000&gt;;</div><div class='add'>+		clock-output-names = "dsi_ipg_clk";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mipi_pll_div2_clk: clock-controller-mipi-div2-pll {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;432000000&gt;;</div><div class='add'>+		clock-output-names = "mipi_pll_div2_clk";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vpu_subsys_dsp: bus@55000000 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges = &lt;0x55000000 0x0 0x55000000 0x1000000&gt;;</div><div class='add'>+</div><div class='add'>+		vpu_dsp: dsp@556e8000 {</div><div class='add'>+			compatible = "fsl,imx8qm-hifi4";</div><div class='add'>+			reg = &lt;0x556e8000 0x88000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk_dummy&gt;,</div><div class='add'>+				 &lt;&amp;clk_dummy&gt;,</div><div class='add'>+				 &lt;&amp;clk_dummy&gt;;</div><div class='add'>+			clock-names = "ipg", "ocram", "core";</div><div class='add'>+			power-domains = &lt;&amp;pd IMX_SC_R_MU_13B&gt;,</div><div class='add'>+					&lt;&amp;pd IMX_SC_R_DSP&gt;,</div><div class='add'>+					&lt;&amp;pd IMX_SC_R_DSP_RAM&gt;,</div><div class='add'>+					&lt;&amp;pd IMX_SC_R_MU_2A&gt;;</div><div class='add'>+			mboxes = &lt;&amp;lsio_mu13 0 0&gt;,</div><div class='add'>+				 &lt;&amp;lsio_mu13 1 0&gt;,</div><div class='add'>+				 &lt;&amp;lsio_mu13 3 0&gt;;</div><div class='add'>+			mbox-names = "tx", "rx", "rxdb";</div><div class='add'>+			firmware-name = "imx/dsp/hifi4.bin";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* sorted in register address */</div><div class='add'>+	#include "imx8-ss-security.dtsi"</div><div class='add'>+	#include "imx8-ss-cm41.dtsi"</div><div class='add'>+	#include "imx8-ss-audio.dtsi"</div><div class='add'>+	#include "imx8-ss-vpu.dtsi"</div><div class='add'>+	#include "imx8-ss-gpu0.dtsi"</div><div class='add'>+	#include "imx8-ss-mipi0.dtsi"</div><div class='add'>+	#include "imx8-ss-lvds0.dtsi"</div><div class='add'>+	#include "imx8-ss-mipi1.dtsi"</div><div class='add'>+	#include "imx8-ss-lvds1.dtsi"</div><div class='add'>+	#include "imx8-ss-img.dtsi"</div><div class='add'>+	#include "imx8-ss-dma.dtsi"</div><div class='add'>+	#include "imx8-ss-conn.dtsi"</div><div class='add'>+	#include "imx8-ss-lsio.dtsi"</div><div class='add'>+	#include "imx8-ss-hsio.dtsi"</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include "imx8qm-ss-img.dtsi"</div><div class='add'>+#include "imx8qm-ss-dma.dtsi"</div><div class='add'>+#include "imx8qm-ss-conn.dtsi"</div><div class='add'>+#include "imx8qm-ss-lsio.dtsi"</div><div class='add'>+#include "imx8qm-ss-audio.dtsi"</div><div class='add'>+#include "imx8qm-ss-lvds.dtsi"</div><div class='add'>+#include "imx8qm-ss-mipi.dtsi"</div><div class='add'>+#include "imx8qm-ss-hsio.dtsi"</div><div class='add'>+</div><div class='add'>+/delete-node/ &amp;dsp;</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts b/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts<br/>index a3f8cf195974..50bf7919c863 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts</a></div><div class='hunk'>@@ -13,13 +13,13 @@</div><div class='ctx'> 	compatible = "einfochips,imx8qxp-ai_ml", "fsl,imx8qxp";</div><div class='ctx'> </div><div class='ctx'> 	aliases {</div><div class='del'>-		serial1 = &amp;adma_lpuart1;</div><div class='del'>-		serial2 = &amp;adma_lpuart2;</div><div class='del'>-		serial3 = &amp;adma_lpuart3;</div><div class='add'>+		serial1 = &amp;lpuart1;</div><div class='add'>+		serial2 = &amp;lpuart2;</div><div class='add'>+		serial3 = &amp;lpuart3;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	chosen {</div><div class='del'>-		stdout-path = &amp;adma_lpuart2;</div><div class='add'>+		stdout-path = &amp;lpuart2;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	memory@80000000 {</div><div class='hunk'>@@ -82,7 +82,7 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* BT */</div><div class='del'>-&amp;adma_lpuart0 {</div><div class='add'>+&amp;lpuart0 {</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pinctrl_lpuart0&gt;;</div><div class='ctx'> 	uart-has-rtscts;</div><div class='hunk'>@@ -90,21 +90,21 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* LS-UART0 */</div><div class='del'>-&amp;adma_lpuart1 {</div><div class='add'>+&amp;lpuart1 {</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pinctrl_lpuart1&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* Debug */</div><div class='del'>-&amp;adma_lpuart2 {</div><div class='add'>+&amp;lpuart2 {</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pinctrl_lpuart2&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* PCI-E UART */</div><div class='del'>-&amp;adma_lpuart3 {</div><div class='add'>+&amp;lpuart3 {</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pinctrl_lpuart3&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='hunk'>@@ -133,7 +133,7 @@</div><div class='ctx'> &amp;usdhc1 {</div><div class='ctx'> 	#address-cells = &lt;1&gt;;</div><div class='ctx'> 	#size-cells = &lt;0&gt;;</div><div class='del'>-	assigned-clocks = &lt;&amp;clk IMX_CONN_SDHC0_CLK&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER&gt;;</div><div class='ctx'> 	assigned-clock-rates = &lt;200000000&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='hunk'>@@ -151,7 +151,7 @@</div><div class='ctx'> </div><div class='ctx'> /* SD */</div><div class='ctx'> &amp;usdhc2 {</div><div class='del'>-	assigned-clocks = &lt;&amp;clk IMX_CONN_SDHC1_CLK&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER&gt;;</div><div class='ctx'> 	assigned-clock-rates = &lt;200000000&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;;</div><div class='hunk'>@@ -180,7 +180,7 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pinctrl_leds: ledsgrp{</div><div class='add'>+	pinctrl_leds: ledsgrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			IMX8QXP_ESAI0_TX2_RX3_LSIO_GPIO0_IO06			0x00000021</div><div class='ctx'> 			IMX8QXP_ESAI0_TX3_RX2_LSIO_GPIO0_IO07			0x00000021</div><div class='hunk'>@@ -195,7 +195,7 @@</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			IMX8QXP_UART0_RX_ADMA_UART0_RX				0X06000020</div><div class='ctx'> 			IMX8QXP_UART0_TX_ADMA_UART0_TX				0X06000020</div><div class='del'>-			IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B 			0x06000020</div><div class='add'>+			IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B			0x06000020</div><div class='ctx'> 			IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B			0x06000020</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-aster.dts b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-aster.dts<br/>new file mode 100644<br/>index 000000000000..966ecfb2a17e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8qxp-colibri-aster.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8qxp-colibri-aster.dts</a></div><div class='hunk'>@@ -0,0 +1,16 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2018-2021 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8qxp-colibri.dtsi"</div><div class='add'>+#include "imx8x-colibri-aster.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Toradex Colibri iMX8QXP on Aster Board";</div><div class='add'>+	compatible = "toradex,colibri-imx8x-aster",</div><div class='add'>+		     "toradex,colibri-imx8x",</div><div class='add'>+		     "fsl,imx8qxp";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dts b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dts<br/>index 6b21a295c126..fe4597a6f7e0 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dts</a></div><div class='hunk'>@@ -1,4 +1,4 @@</div><div class='del'>-// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright 2019 Toradex</div><div class='ctx'>  */</div><div class='hunk'>@@ -6,10 +6,10 @@</div><div class='ctx'> /dts-v1/;</div><div class='ctx'> </div><div class='ctx'> #include "imx8qxp-colibri.dtsi"</div><div class='del'>-#include "imx8qxp-colibri-eval-v3.dtsi"</div><div class='add'>+#include "imx8x-colibri-eval-v3.dtsi"</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='del'>-	model = "Toradex Colibri iMX8QXP/DX on Colibri Evaluation Board V3";</div><div class='add'>+	model = "Toradex Colibri iMX8QXP on Colibri Evaluation Board V3";</div><div class='ctx'> 	compatible = "toradex,colibri-imx8x-eval-v3",</div><div class='ctx'> 		     "toradex,colibri-imx8x", "fsl,imx8qxp";</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi<br/>deleted file mode 100644<br/>index c7336f387605..000000000000<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi</a><br/>+++ /dev/null</div><div class='hunk'>@@ -1,62 +0,0 @@</div><div class='del'>-// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='del'>-/*</div><div class='del'>- * Copyright 2019 Toradex</div><div class='del'>- */</div><div class='del'>-</div><div class='del'>-#include "dt-bindings/input/linux-event-codes.h"</div><div class='del'>-</div><div class='del'>-/ {</div><div class='del'>-	aliases {</div><div class='del'>-		rtc0 = &amp;rtc_i2c;</div><div class='del'>-		rtc1 = &amp;rtc;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	gpio-keys {</div><div class='del'>-		compatible = "gpio-keys";</div><div class='del'>-		pinctrl-names = "default";</div><div class='del'>-		pinctrl-0 = &lt;&amp;pinctrl_gpiokeys&gt;;</div><div class='del'>-</div><div class='del'>-		wakeup {</div><div class='del'>-			label = "Wake-Up";</div><div class='del'>-			gpios = &lt;&amp;lsio_gpio3 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			linux,code = &lt;KEY_WAKEUP&gt;;</div><div class='del'>-			debounce-interval = &lt;10&gt;;</div><div class='del'>-			wakeup-source;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;adma_i2c1 {</div><div class='del'>-	status = "okay";</div><div class='del'>-</div><div class='del'>-	/* M41T0M6 real time clock on carrier board */</div><div class='del'>-	rtc_i2c: rtc@68 {</div><div class='del'>-		compatible = "st,m41t0";</div><div class='del'>-		reg = &lt;0x68&gt;;</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-/* Colibri UART_B */</div><div class='del'>-&amp;adma_lpuart0 {</div><div class='del'>-	status= "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-/* Colibri UART_C */</div><div class='del'>-&amp;adma_lpuart2 {</div><div class='del'>-	status= "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-/* Colibri UART_A */</div><div class='del'>-&amp;adma_lpuart3 {</div><div class='del'>-	status= "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-/* Colibri FastEthernet */</div><div class='del'>-&amp;fec1 {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-/* Colibri SD/MMC Card */</div><div class='del'>-&amp;usdhc2 {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-iris-v2.dts b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-iris-v2.dts<br/>new file mode 100644<br/>index 000000000000..cca33213fa9b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8qxp-colibri-iris-v2.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8qxp-colibri-iris-v2.dts</a></div><div class='hunk'>@@ -0,0 +1,16 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2018-2021 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8qxp-colibri.dtsi"</div><div class='add'>+#include "imx8x-colibri-iris-v2.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Toradex Colibri iMX8QXP on Colibri Iris V2 Board";</div><div class='add'>+	compatible = "toradex,colibri-imx8x-iris-v2",</div><div class='add'>+		     "toradex,colibri-imx8x",</div><div class='add'>+		     "fsl,imx8qxp";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-iris.dts b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-iris.dts<br/>new file mode 100644<br/>index 000000000000..fed75b5d4a1c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8qxp-colibri-iris.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8qxp-colibri-iris.dts</a></div><div class='hunk'>@@ -0,0 +1,16 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2018-2021 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8qxp-colibri.dtsi"</div><div class='add'>+#include "imx8x-colibri-iris.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Toradex Colibri iMX8QXP on Colibri Iris Board";</div><div class='add'>+	compatible = "toradex,colibri-imx8x-iris",</div><div class='add'>+		     "toradex,colibri-imx8x",</div><div class='add'>+		     "fsl,imx8qxp";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi<br/>index 75f17a29f81e..0f1aa31dd3e5 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi</a></div><div class='hunk'>@@ -1,598 +1,12 @@</div><div class='del'>-// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright 2019 Toradex</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include "imx8qxp.dtsi"</div><div class='add'>+#include "imx8x-colibri.dtsi"</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='del'>-	model = "Toradex Colibri iMX8QXP/DX Module";</div><div class='add'>+	model = "Toradex Colibri iMX8QXP Module";</div><div class='ctx'> 	compatible = "toradex,colibri-imx8x", "fsl,imx8qxp";</div><div class='del'>-</div><div class='del'>-	chosen {</div><div class='del'>-		stdout-path = &amp;adma_lpuart3;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	reg_module_3v3: regulator-module-3v3 {</div><div class='del'>-		compatible = "regulator-fixed";</div><div class='del'>-		regulator-name = "+V3.3";</div><div class='del'>-		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-/* On-module I2C */</div><div class='del'>-&amp;adma_i2c0 {</div><div class='del'>-	#address-cells = &lt;1&gt;;</div><div class='del'>-	#size-cells = &lt;0&gt;;</div><div class='del'>-	clock-frequency = &lt;100000&gt;;</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-	pinctrl-0 = &lt;&amp;pinctrl_i2c0&gt;, &lt;&amp;pinctrl_sgtl5000_usb_clk&gt;;</div><div class='del'>-	status = "okay";</div><div class='del'>-</div><div class='del'>-	/* Touch controller */</div><div class='del'>-	touchscreen@2c {</div><div class='del'>-		compatible = "adi,ad7879-1";</div><div class='del'>-		pinctrl-names = "default";</div><div class='del'>-		pinctrl-0 = &lt;&amp;pinctrl_ad7879_int&gt;;</div><div class='del'>-		reg = &lt;0x2c&gt;;</div><div class='del'>-		interrupt-parent = &lt;&amp;lsio_gpio3&gt;;</div><div class='del'>-		interrupts = &lt;5 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='del'>-		touchscreen-max-pressure = &lt;4096&gt;;</div><div class='del'>-		adi,resistance-plate-x = &lt;120&gt;;</div><div class='del'>-		adi,first-conversion-delay = /bits/ 8 &lt;3&gt;;</div><div class='del'>-		adi,acquisition-time = /bits/ 8 &lt;1&gt;;</div><div class='del'>-		adi,median-filter-size = /bits/ 8 &lt;2&gt;;</div><div class='del'>-		adi,averaging = /bits/ 8 &lt;1&gt;;</div><div class='del'>-		adi,conversion-interval = /bits/ 8 &lt;255&gt;;</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-/* Colibri I2C */</div><div class='del'>-&amp;adma_i2c1 {</div><div class='del'>-	#address-cells = &lt;1&gt;;</div><div class='del'>-	#size-cells = &lt;0&gt;;</div><div class='del'>-	clock-frequency = &lt;100000&gt;;</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-/* Colibri UART_B */</div><div class='del'>-&amp;adma_lpuart0 {</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-	pinctrl-0 = &lt;&amp;pinctrl_lpuart0&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-/* Colibri UART_C */</div><div class='del'>-&amp;adma_lpuart2 {</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-	pinctrl-0 = &lt;&amp;pinctrl_lpuart2&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-/* Colibri UART_A */</div><div class='del'>-&amp;adma_lpuart3 {</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-	pinctrl-0 = &lt;&amp;pinctrl_lpuart3&gt;, &lt;&amp;pinctrl_lpuart3_ctrl&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-/* Colibri FastEthernet */</div><div class='del'>-&amp;fec1 {</div><div class='del'>-	pinctrl-names = "default", "sleep";</div><div class='del'>-	pinctrl-0 = &lt;&amp;pinctrl_fec1&gt;;</div><div class='del'>-	pinctrl-1 = &lt;&amp;pinctrl_fec1_sleep&gt;;</div><div class='del'>-	phy-mode = "rmii";</div><div class='del'>-	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='del'>-	fsl,magic-packet;</div><div class='del'>-</div><div class='del'>-	mdio {</div><div class='del'>-		#address-cells = &lt;1&gt;;</div><div class='del'>-		#size-cells = &lt;0&gt;;</div><div class='del'>-</div><div class='del'>-		ethphy0: ethernet-phy@2 {</div><div class='del'>-			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='del'>-			max-speed = &lt;100&gt;;</div><div class='del'>-			reg = &lt;2&gt;;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-/* On-module eMMC */</div><div class='del'>-&amp;usdhc1 {</div><div class='del'>-	bus-width = &lt;8&gt;;</div><div class='del'>-	non-removable;</div><div class='del'>-	no-sd;</div><div class='del'>-	no-sdio;</div><div class='del'>-	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='del'>-	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='del'>-	pinctrl-1 = &lt;&amp;pinctrl_usdhc1_100mhz&gt;;</div><div class='del'>-	pinctrl-2 = &lt;&amp;pinctrl_usdhc1_200mhz&gt;;</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-/* Colibri SD/MMC Card */</div><div class='del'>-&amp;usdhc2 {</div><div class='del'>-	bus-width = &lt;4&gt;;</div><div class='del'>-	cd-gpios = &lt;&amp;lsio_gpio3 9 GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-	vmmc-supply = &lt;&amp;reg_module_3v3&gt;;</div><div class='del'>-	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";</div><div class='del'>-	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='del'>-	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='del'>-	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='del'>-	pinctrl-3 = &lt;&amp;pinctrl_usdhc2_sleep&gt;, &lt;&amp;pinctrl_usdhc2_gpio_sleep&gt;;</div><div class='del'>-	disable-wp;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;iomuxc {</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-	pinctrl-0 = &lt;&amp;pinctrl_ext_io0&gt;, &lt;&amp;pinctrl_hog0&gt;, &lt;&amp;pinctrl_hog1&gt;;</div><div class='del'>-</div><div class='del'>-	/* On-module touch pen-down interrupt */</div><div class='del'>-	pinctrl_ad7879_int: ad7879intgrp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			IMX8QXP_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05	0x21</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	/* Colibri Analogue Inputs */</div><div class='del'>-	pinctrl_adc0: adc0grp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			IMX8QXP_ADC_IN0_ADMA_ADC_IN0			0x60		/* SODIMM   8 */</div><div class='del'>-			IMX8QXP_ADC_IN1_ADMA_ADC_IN1			0x60		/* SODIMM   6 */</div><div class='del'>-			IMX8QXP_ADC_IN4_ADMA_ADC_IN4			0x60		/* SODIMM   4 */</div><div class='del'>-			IMX8QXP_ADC_IN5_ADMA_ADC_IN5			0x60		/* SODIMM   2 */</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	pinctrl_can_int: canintgrp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			IMX8QXP_QSPI0A_DQS_LSIO_GPIO3_IO13		0x40		/* SODIMM  73 */</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	pinctrl_csi_ctl: csictlgrp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			IMX8QXP_QSPI0A_SS0_B_LSIO_GPIO3_IO14		0x20		/* SODIMM  77 */</div><div class='del'>-			IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15		0x20		/* SODIMM  89 */</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	pinctrl_ext_io0: extio0grp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			IMX8QXP_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08	0x06000040	/* SODIMM 135 */</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	/* Colibri Ethernet: On-module 100Mbps PHY Micrel KSZ8041 */</div><div class='del'>-	pinctrl_fec1: fec1grp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			IMX8QXP_ENET0_MDC_CONN_ENET0_MDC			0x06000020</div><div class='del'>-			IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020</div><div class='del'>-			IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x61</div><div class='del'>-			IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT		0x06000061</div><div class='del'>-			IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0		0x61</div><div class='del'>-			IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1		0x61</div><div class='del'>-			IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x61</div><div class='del'>-			IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0		0x61</div><div class='del'>-			IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1		0x61</div><div class='del'>-			IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER		0x61</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	pinctrl_fec1_sleep: fec1slpgrp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			IMX8QXP_ENET0_MDC_LSIO_GPIO5_IO11		0x06000041</div><div class='del'>-			IMX8QXP_ENET0_MDIO_LSIO_GPIO5_IO10		0x06000041</div><div class='del'>-			IMX8QXP_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30	0x41</div><div class='del'>-			IMX8QXP_ENET0_RGMII_TXC_LSIO_GPIO4_IO29		0x41</div><div class='del'>-			IMX8QXP_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31	0x41</div><div class='del'>-			IMX8QXP_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00	0x41</div><div class='del'>-			IMX8QXP_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04	0x41</div><div class='del'>-			IMX8QXP_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05	0x41</div><div class='del'>-			IMX8QXP_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06	0x41</div><div class='del'>-			IMX8QXP_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07	0x41</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	/* Colibri optional CAN on UART_B RTS/CTS */</div><div class='del'>-	pinctrl_flexcan1: flexcan0grp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX		0x21		/* SODIMM  32 */</div><div class='del'>-			IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX		0x21		/* SODIMM  34 */</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	/* Colibri optional CAN on PS2 */</div><div class='del'>-	pinctrl_flexcan2: flexcan1grp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX		0x21		/* SODIMM  55 */</div><div class='del'>-			IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX		0x21		/* SODIMM  63 */</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	/* Colibri optional CAN on UART_A TXD/RXD */</div><div class='del'>-	pinctrl_flexcan3: flexcan2grp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX		0x21		/* SODIMM  35 */</div><div class='del'>-			IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX		0x21		/* SODIMM  33 */</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	/* Colibri LCD Back-Light GPIO */</div><div class='del'>-	pinctrl_gpio_bl_on: gpioblongrp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			IMX8QXP_QSPI0A_DATA3_LSIO_GPIO3_IO12		0x60		/* SODIMM  71 */</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	pinctrl_gpiokeys: gpiokeysgrp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			IMX8QXP_QSPI0A_DATA1_LSIO_GPIO3_IO10		0x06700041	/* SODIMM  45 */</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	pinctrl_hog0: hog0grp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02	0x06000020	/* SODIMM  65 */</div><div class='del'>-			IMX8QXP_CSI_D07_CI_PI_D09			0x61		/* SODIMM  65 */</div><div class='del'>-			IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11		0x20		/* SODIMM  69 */</div><div class='del'>-			IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26		0x20		/* SODIMM  79 */</div><div class='del'>-			IMX8QXP_CSI_D02_CI_PI_D04			0x61		/* SODIMM  79 */</div><div class='del'>-			IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03		0x06000020	/* SODIMM  85 */</div><div class='del'>-			IMX8QXP_CSI_D06_CI_PI_D08			0x61		/* SODIMM  85 */</div><div class='del'>-			IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17		0x20		/* SODIMM  95 */</div><div class='del'>-			IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27		0x20		/* SODIMM  97 */</div><div class='del'>-			IMX8QXP_CSI_D03_CI_PI_D05			0x61		/* SODIMM  97 */</div><div class='del'>-			IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18		0x20		/* SODIMM  99 */</div><div class='del'>-			IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28		0x20		/* SODIMM 101 */</div><div class='del'>-			IMX8QXP_CSI_D00_CI_PI_D02			0x61		/* SODIMM 101 */</div><div class='del'>-			IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25		0x20		/* SODIMM 103 */</div><div class='del'>-			IMX8QXP_CSI_D01_CI_PI_D03			0x61		/* SODIMM 103 */</div><div class='del'>-			IMX8QXP_QSPI0B_DATA1_LSIO_GPIO3_IO19		0x20		/* SODIMM 105 */</div><div class='del'>-			IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20		0x20		/* SODIMM 107 */</div><div class='del'>-			IMX8QXP_USB_SS3_TC2_LSIO_GPIO4_IO05		0x20		/* SODIMM 127 */</div><div class='del'>-			IMX8QXP_USB_SS3_TC3_LSIO_GPIO4_IO06		0x20		/* SODIMM 131 */</div><div class='del'>-			IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04		0x20		/* SODIMM 133 */</div><div class='del'>-			IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00		0x20		/* SODIMM  96 */</div><div class='del'>-			IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21		0x20		/* SODIMM  98 */</div><div class='del'>-			IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31		0x20		/* SODIMM 100 */</div><div class='del'>-			IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22		0x20		/* SODIMM 102 */</div><div class='del'>-			IMX8QXP_QSPI0B_SS0_B_LSIO_GPIO3_IO23		0x20		/* SODIMM 104 */</div><div class='del'>-			IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24		0x20		/* SODIMM 106 */</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	pinctrl_hog1: hog1grp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01		0x20		/* SODIMM  75 */</div><div class='del'>-			IMX8QXP_QSPI0A_SCLK_LSIO_GPIO3_IO16		0x20		/* SODIMM  93 */</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * This pin is used in the SCFW as a UART. Using it from</div><div class='del'>-	 * Linux would require rewritting the SCFW board file.</div><div class='del'>-	 */</div><div class='del'>-	pinctrl_hog_scfw: hogscfwgrp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			IMX8QXP_SCU_GPIO0_00_LSIO_GPIO2_IO03		0x20		/* SODIMM 144 */</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	/* On Module I2C */</div><div class='del'>-	pinctrl_i2c0: i2c0grp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			IMX8QXP_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL	0x06000021</div><div class='del'>-			IMX8QXP_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA	0x06000021</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	/* MIPI DSI I2C accessible on SODIMM (X1) and FFC (X2) */</div><div class='del'>-	pinctrl_i2c0_mipi_lvds0: i2c0mipilvds0grp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL	0xc6000020	/* SODIMM 140 */</div><div class='del'>-			IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA	0xc6000020	/* SODIMM 142 */</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	/* MIPI CSI I2C accessible on SODIMM (X1) and FFC (X3) */</div><div class='del'>-	pinctrl_i2c0_mipi_lvds1: i2c0mipilvds1grp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL	0xc6000020	/* SODIMM 186 */</div><div class='del'>-			IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA	0xc6000020	/* SODIMM 188 */</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	/* Colibri I2C */</div><div class='del'>-	pinctrl_i2c1: i2c1grp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			IMX8QXP_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL	0x06000021	/* SODIMM 196 */</div><div class='del'>-			IMX8QXP_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA	0x06000021	/* SODIMM 194 */</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	/* Colibri Parallel RGB LCD Interface */</div><div class='del'>-	pinctrl_lcdif: lcdifgrp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK		0x60		/* SODIMM  56 */</div><div class='del'>-			IMX8QXP_SPI3_CS0_ADMA_LCDIF_HSYNC		0x60		/* SODIMM  68 */</div><div class='del'>-			IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC		0x60		/* SODIMM  82 */</div><div class='del'>-			IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN			0x60		/* SODIMM  44 */</div><div class='del'>-			IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19		0x60		/* SODIMM  44 */</div><div class='del'>-			IMX8QXP_ESAI0_FSR_ADMA_LCDIF_D00		0x60		/* SODIMM  76 */</div><div class='del'>-			IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21		0x60		/* SODIMM  76 */</div><div class='del'>-			IMX8QXP_ESAI0_FST_ADMA_LCDIF_D01		0x60		/* SODIMM  70 */</div><div class='del'>-			IMX8QXP_ESAI0_SCKR_ADMA_LCDIF_D02		0x60		/* SODIMM  60 */</div><div class='del'>-			IMX8QXP_ESAI0_SCKT_ADMA_LCDIF_D03		0x60		/* SODIMM  58 */</div><div class='del'>-			IMX8QXP_ESAI0_TX0_ADMA_LCDIF_D04		0x60		/* SODIMM  78 */</div><div class='del'>-			IMX8QXP_ESAI0_TX1_ADMA_LCDIF_D05		0x60		/* SODIMM  72 */</div><div class='del'>-			IMX8QXP_ESAI0_TX2_RX3_ADMA_LCDIF_D06		0x60		/* SODIMM  80 */</div><div class='del'>-			IMX8QXP_ESAI0_TX3_RX2_ADMA_LCDIF_D07		0x60		/* SODIMM  46 */</div><div class='del'>-			IMX8QXP_ESAI0_TX4_RX1_ADMA_LCDIF_D08		0x60		/* SODIMM  62 */</div><div class='del'>-			IMX8QXP_ESAI0_TX5_RX0_ADMA_LCDIF_D09		0x60		/* SODIMM  48 */</div><div class='del'>-			IMX8QXP_SPDIF0_RX_ADMA_LCDIF_D10		0x60		/* SODIMM  74 */</div><div class='del'>-			IMX8QXP_SPDIF0_TX_ADMA_LCDIF_D11		0x60		/* SODIMM  50 */</div><div class='del'>-			IMX8QXP_SPDIF0_EXT_CLK_ADMA_LCDIF_D12		0x60		/* SODIMM  52 */</div><div class='del'>-			IMX8QXP_SPI3_SCK_ADMA_LCDIF_D13			0x60		/* SODIMM  54 */</div><div class='del'>-			IMX8QXP_SPI3_SDO_ADMA_LCDIF_D14			0x60		/* SODIMM  66 */</div><div class='del'>-			IMX8QXP_SPI3_SDI_ADMA_LCDIF_D15			0x60		/* SODIMM  64 */</div><div class='del'>-			IMX8QXP_SPI3_CS1_ADMA_LCDIF_D16			0x60		/* SODIMM  57 */</div><div class='del'>-			IMX8QXP_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01	0x60		/* SODIMM  57 */</div><div class='del'>-			IMX8QXP_UART1_CTS_B_ADMA_LCDIF_D17		0x60		/* SODIMM  61 */</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	/* Colibri SPI */</div><div class='del'>-	pinctrl_lpspi2: lpspi2grp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00		0x21		/* SODIMM  86 */</div><div class='del'>-			IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO			0x06000040	/* SODIMM  92 */</div><div class='del'>-			IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI			0x06000040	/* SODIMM  90 */</div><div class='del'>-			IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK			0x06000040	/* SODIMM  88 */</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	/* Colibri UART_B */</div><div class='del'>-	pinctrl_lpuart0: lpuart0grp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			IMX8QXP_UART0_RX_ADMA_UART0_RX			0x06000020	/* SODIMM  36 */</div><div class='del'>-			IMX8QXP_UART0_TX_ADMA_UART0_TX			0x06000020	/* SODIMM  38 */</div><div class='del'>-			IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B		0x06000020	/* SODIMM  34 */</div><div class='del'>-			IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B		0x06000020	/* SODIMM  32 */</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	/* Colibri UART_C */</div><div class='del'>-	pinctrl_lpuart2: lpuart2grp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			IMX8QXP_UART2_RX_ADMA_UART2_RX			0x06000020	/* SODIMM  19 */</div><div class='del'>-			IMX8QXP_UART2_TX_ADMA_UART2_TX			0x06000020	/* SODIMM  21 */</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	/* Colibri UART_A */</div><div class='del'>-	pinctrl_lpuart3: lpuart3grp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX		0x06000020	/* SODIMM  33 */</div><div class='del'>-			IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX		0x06000020	/* SODIMM  35 */</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	/* Colibri UART_A Control */</div><div class='del'>-	pinctrl_lpuart3_ctrl: lpuart3ctrlgrp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00	0x20		/* SODIMM  23 */</div><div class='del'>-			IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29		0x20		/* SODIMM  25 */</div><div class='del'>-			IMX8QXP_SAI1_RXC_LSIO_GPIO0_IO30		0x20		/* SODIMM  27 */</div><div class='del'>-			IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03		0x20		/* SODIMM  29 */</div><div class='del'>-			IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22		0x20		/* SODIMM  31 */</div><div class='del'>-			IMX8QXP_CSI_EN_LSIO_GPIO3_IO02			0x20		/* SODIMM  37 */</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	/* On module wifi module */</div><div class='del'>-	pinctrl_pcieb: pciebgrp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01	0x04000061	/* SODIMM 178 */</div><div class='del'>-			IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02	0x04000061	/* SODIMM  94 */</div><div class='del'>-			IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00	0x60		/* SODIMM  81 */</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	/* Colibri PWM_A */</div><div class='del'>-	pinctrl_pwm_a: pwmagrp {</div><div class='del'>-	/* both pins are connected together, reserve the unused CSI_D05 */</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			IMX8QXP_CSI_D05_CI_PI_D07			0x61		/* SODIMM  59 */</div><div class='del'>-			IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT		0x60		/* SODIMM  59 */</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	/* Colibri PWM_B */</div><div class='del'>-	pinctrl_pwm_b: pwmbgrp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			IMX8QXP_UART1_TX_LSIO_PWM0_OUT			0x60		/* SODIMM  28 */</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	/* Colibri PWM_C */</div><div class='del'>-	pinctrl_pwm_c: pwmcgrp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			IMX8QXP_UART1_RX_LSIO_PWM1_OUT			0x60		/* SODIMM  30 */</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	/* Colibri PWM_D */</div><div class='del'>-	pinctrl_pwm_d: pwmdgrp {</div><div class='del'>-	/* both pins are connected together, reserve the unused CSI_D04 */</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			IMX8QXP_CSI_D04_CI_PI_D06			0x61		/* SODIMM  67 */</div><div class='del'>-			IMX8QXP_UART1_RTS_B_LSIO_PWM2_OUT		0x60		/* SODIMM  67 */</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	/* On-module I2S */</div><div class='del'>-	pinctrl_sai0: sai0grp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			IMX8QXP_SPI0_SDI_ADMA_SAI0_TXD			0x06000040</div><div class='del'>-			IMX8QXP_SPI0_CS0_ADMA_SAI0_RXD			0x06000040</div><div class='del'>-			IMX8QXP_SPI0_SCK_ADMA_SAI0_TXC			0x06000040</div><div class='del'>-			IMX8QXP_SPI0_SDO_ADMA_SAI0_TXFS			0x06000040</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	/* Colibri Audio Analogue Microphone GND */</div><div class='del'>-	pinctrl_sgtl5000: sgtl5000grp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			/* MIC GND EN */</div><div class='del'>-			IMX8QXP_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06	0x41</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	/* On-module SGTL5000 clock */</div><div class='del'>-	pinctrl_sgtl5000_usb_clk: sgtl5000usbclkgrp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			IMX8QXP_ADC_IN3_ADMA_ACM_MCLK_OUT0		0x21</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	/* On-module USB interrupt */</div><div class='del'>-	pinctrl_usb3503a: usb3503agrp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			IMX8QXP_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04	0x61</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	/* Colibri USB Client Cable Detect */</div><div class='del'>-	pinctrl_usbc_det: usbcdetgrp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09	0x06000040	/* SODIMM 137 */</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	/* USB Host Power Enable */</div><div class='del'>-	pinctrl_usbh1_reg: usbh1reggrp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			IMX8QXP_USB_SS3_TC0_LSIO_GPIO4_IO03		0x06000040	/* SODIMM 129 */</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	/* On-module eMMC */</div><div class='del'>-	pinctrl_usdhc1: usdhc1grp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041</div><div class='del'>-			IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD		0x21</div><div class='del'>-			IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0		0x21</div><div class='del'>-			IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1		0x21</div><div class='del'>-			IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2		0x21</div><div class='del'>-			IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3		0x21</div><div class='del'>-			IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4		0x21</div><div class='del'>-			IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5		0x21</div><div class='del'>-			IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6		0x21</div><div class='del'>-			IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7		0x21</div><div class='del'>-			IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE		0x41</div><div class='del'>-			IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x21</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041</div><div class='del'>-			IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD		0x21</div><div class='del'>-			IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0		0x21</div><div class='del'>-			IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1		0x21</div><div class='del'>-			IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2		0x21</div><div class='del'>-			IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3		0x21</div><div class='del'>-			IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4		0x21</div><div class='del'>-			IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5		0x21</div><div class='del'>-			IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6		0x21</div><div class='del'>-			IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7		0x21</div><div class='del'>-			IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE		0x41</div><div class='del'>-			IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x21</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041</div><div class='del'>-			IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD		0x21</div><div class='del'>-			IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0		0x21</div><div class='del'>-			IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1		0x21</div><div class='del'>-			IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2		0x21</div><div class='del'>-			IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3		0x21</div><div class='del'>-			IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4		0x21</div><div class='del'>-			IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5		0x21</div><div class='del'>-			IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6		0x21</div><div class='del'>-			IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7		0x21</div><div class='del'>-			IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE		0x41</div><div class='del'>-			IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x21</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	/* Colibri SD/MMC Card Detect */</div><div class='del'>-	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09		0x06000021	/* SODIMM  43 */</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	pinctrl_usdhc2_gpio_sleep: usdhc2gpioslpgrp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09		0x60		/* SODIMM  43 */</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	/* Colibri SD/MMC Card */</div><div class='del'>-	pinctrl_usdhc2: usdhc2grp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041	/* SODIMM  47 */</div><div class='del'>-			IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD		0x21		/* SODIMM 190 */</div><div class='del'>-			IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0		0x21		/* SODIMM 192 */</div><div class='del'>-			IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1		0x21		/* SODIMM  49 */</div><div class='del'>-			IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2		0x21		/* SODIMM  51 */</div><div class='del'>-			IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3		0x21		/* SODIMM  53 */</div><div class='del'>-			IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x21</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041	/* SODIMM  47 */</div><div class='del'>-			IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD		0x21		/* SODIMM 190 */</div><div class='del'>-			IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0		0x21		/* SODIMM 192 */</div><div class='del'>-			IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1		0x21		/* SODIMM  49 */</div><div class='del'>-			IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2		0x21		/* SODIMM  51 */</div><div class='del'>-			IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3		0x21		/* SODIMM  53 */</div><div class='del'>-			IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x21</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041	/* SODIMM  47 */</div><div class='del'>-			IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD		0x21		/* SODIMM 190 */</div><div class='del'>-			IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0		0x21		/* SODIMM 192 */</div><div class='del'>-			IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1		0x21		/* SODIMM  49 */</div><div class='del'>-			IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2		0x21		/* SODIMM  51 */</div><div class='del'>-			IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3		0x21		/* SODIMM  53 */</div><div class='del'>-			IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x21</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	pinctrl_usdhc2_sleep: usdhc2slpgrp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			IMX8QXP_USDHC1_CLK_LSIO_GPIO4_IO23		0x60		/* SODIMM  47 */</div><div class='del'>-			IMX8QXP_USDHC1_CMD_LSIO_GPIO4_IO24		0x60		/* SODIMM 190 */</div><div class='del'>-			IMX8QXP_USDHC1_DATA0_LSIO_GPIO4_IO25		0x60		/* SODIMM 192 */</div><div class='del'>-			IMX8QXP_USDHC1_DATA1_LSIO_GPIO4_IO26		0x60		/* SODIMM  49 */</div><div class='del'>-			IMX8QXP_USDHC1_DATA2_LSIO_GPIO4_IO27		0x60		/* SODIMM  51 */</div><div class='del'>-			IMX8QXP_USDHC1_DATA3_LSIO_GPIO4_IO28		0x60		/* SODIMM  53 */</div><div class='del'>-			IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x21</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	pinctrl_wifi: wifigrp {</div><div class='del'>-		fsl,pins = &lt;</div><div class='del'>-			IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K	0x20</div><div class='del'>-		&gt;;</div><div class='del'>-	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640-csi.dtso b/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640-csi.dtso<br/>new file mode 100644<br/>index 000000000000..dd65ed8bb37c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640-csi.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640-csi.dtso</a></div><div class='hunk'>@@ -0,0 +1,61 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 NXP</div><div class='add'>+ */</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/media/video-interfaces.h&gt;</div><div class='add'>+</div><div class='add'>+&amp;i2c_mipi_csi0 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c_mipi_csi0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ov5640_mipi: camera@3c {</div><div class='add'>+		compatible = "ovti,ov5640";</div><div class='add'>+		reg = &lt;0x3c&gt;;</div><div class='add'>+		clocks = &lt;&amp;xtal24m&gt;;</div><div class='add'>+		clock-names = "xclk";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_mipi_csi0&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		powerdown-gpios = &lt;&amp;lsio_gpio3 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;lsio_gpio3 8 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		AVDD-supply = &lt;&amp;reg_2v8&gt;;</div><div class='add'>+		DVDD-supply = &lt;&amp;reg_1v5&gt;;</div><div class='add'>+		DOVDD-supply = &lt;&amp;reg_1v8&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			ov5640_mipi_ep: endpoint {</div><div class='add'>+				bus-type = &lt;MEDIA_BUS_TYPE_CSI2_DPHY&gt;;</div><div class='add'>+				data-lanes = &lt;1 2&gt;;</div><div class='add'>+				remote-endpoint = &lt;&amp;mipi_csi0_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;irqsteer_csi0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;isi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_csi_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		port@0 {</div><div class='add'>+			mipi_csi0_in: endpoint {</div><div class='add'>+				data-lanes = &lt;1 2&gt;;</div><div class='add'>+				remote-endpoint = &lt;&amp;ov5640_mipi_ep&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts<br/>index 13460a360c6a..523f48896b6b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qxp-mek.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8qxp-mek.dts</a></div><div class='hunk'>@@ -6,13 +6,33 @@</div><div class='ctx'> /dts-v1/;</div><div class='ctx'> </div><div class='ctx'> #include "imx8qxp.dtsi"</div><div class='add'>+#include &lt;dt-bindings/usb/pd.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	model = "Freescale i.MX8QXP MEK";</div><div class='ctx'> 	compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp";</div><div class='ctx'> </div><div class='add'>+	bt_sco_codec: audio-codec-bt {</div><div class='add'>+		compatible = "linux,bt-sco";</div><div class='add'>+		#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	chosen {</div><div class='del'>-		stdout-path = &amp;adma_lpuart0;</div><div class='add'>+		stdout-path = &amp;lpuart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	imx8x_cm4: imx8x-cm4 {</div><div class='add'>+		compatible = "fsl,imx8qxp-cm4";</div><div class='add'>+		mbox-names = "tx", "rx", "rxdb";</div><div class='add'>+		mboxes = &lt;&amp;lsio_mu5 0 1</div><div class='add'>+			  &amp;lsio_mu5 1 1</div><div class='add'>+			  &amp;lsio_mu5 3 1&gt;;</div><div class='add'>+		memory-region = &lt;&amp;vdevbuffer&gt;, &lt;&amp;vdev0vring0&gt;, &lt;&amp;vdev0vring1&gt;,</div><div class='add'>+				&lt;&amp;vdev1vring0&gt;, &lt;&amp;vdev1vring1&gt;, &lt;&amp;rsc_table&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_M4_0_PID0&gt;,</div><div class='add'>+				&lt;&amp;pd IMX_SC_R_M4_0_MU_1A&gt;;</div><div class='add'>+		fsl,entry-address = &lt;0x34fe0000&gt;;</div><div class='add'>+		fsl,resource-id = &lt;IMX_SC_R_M4_0_PID0&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	memory@80000000 {</div><div class='hunk'>@@ -28,11 +48,363 @@</div><div class='ctx'> 		gpio = &lt;&amp;lsio_gpio4 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 		enable-active-high;</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	gpio-sbu-mux {</div><div class='add'>+		compatible = "nxp,cbdtu02043", "gpio-sbu-mux";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_typec_mux&gt;;</div><div class='add'>+		select-gpios = &lt;&amp;lsio_gpio5 9 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;pca9557_a 7 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		orientation-switch;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			usb3_data_ss: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;typec_con_ss&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c-mux {</div><div class='add'>+		compatible = "i2c-mux-gpio";</div><div class='add'>+		mux-gpios = &lt;&amp;lsio_gpio5 0 GPIO_ACTIVE_HIGH&gt;; /* needs to be an unused GPIO */</div><div class='add'>+		i2c-parent = &lt;&amp;cm40_i2c&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		i2c@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			wm8960: audio-codec@1a {</div><div class='add'>+				compatible = "wlf,wm8960";</div><div class='add'>+				reg = &lt;0x1a&gt;;</div><div class='add'>+				clocks = &lt;&amp;mclkout0_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+				clock-names = "mclk";</div><div class='add'>+				assigned-clocks = &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS&gt;,</div><div class='add'>+						  &lt;&amp;mclkout0_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;786432000&gt;,</div><div class='add'>+						       &lt;49152000&gt;,</div><div class='add'>+						       &lt;12288000&gt;,</div><div class='add'>+						       &lt;12288000&gt;;</div><div class='add'>+				wlf,shared-lrclk;</div><div class='add'>+				wlf,hp-cfg = &lt;2 2 3&gt;;</div><div class='add'>+				wlf,gpio-cfg = &lt;1 3&gt;;</div><div class='add'>+				AVDD-supply = &lt;&amp;reg_audio_3v3&gt;;</div><div class='add'>+				DBVDD-supply = &lt;&amp;reg_audio_1v8&gt;;</div><div class='add'>+				DCVDD-supply = &lt;&amp;reg_audio_1v8&gt;;</div><div class='add'>+				SPKVDD1-supply = &lt;&amp;reg_audio_5v&gt;;</div><div class='add'>+				SPKVDD2-supply = &lt;&amp;reg_audio_5v&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			wm8962: wm8962@1a {</div><div class='add'>+				compatible = "wlf,wm8962";</div><div class='add'>+				reg = &lt;0x1a&gt;;</div><div class='add'>+				clocks = &lt;&amp;mclkout0_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+				assigned-clocks = &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS&gt;,</div><div class='add'>+						  &lt;&amp;mclkout0_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;786432000&gt;,</div><div class='add'>+						       &lt;49152000&gt;,</div><div class='add'>+						       &lt;12288000&gt;,</div><div class='add'>+						       &lt;12288000&gt;;</div><div class='add'>+				DCVDD-supply = &lt;&amp;reg_audio_1v8&gt;;</div><div class='add'>+				DBVDD-supply = &lt;&amp;reg_audio_1v8&gt;;</div><div class='add'>+				AVDD-supply = &lt;&amp;reg_audio_1v8&gt;;</div><div class='add'>+				CPVDD-supply = &lt;&amp;reg_audio_1v8&gt;;</div><div class='add'>+				MICVDD-supply = &lt;&amp;reg_audio_3v3&gt;;</div><div class='add'>+				PLLVDD-supply = &lt;&amp;reg_audio_1v8&gt;;</div><div class='add'>+				SPKVDD1-supply = &lt;&amp;reg_audio_5v&gt;;</div><div class='add'>+				SPKVDD2-supply = &lt;&amp;reg_audio_5v&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_1v5: regulator-1v5 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "1v5";</div><div class='add'>+		regulator-min-microvolt = &lt;1500000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1500000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_1v8: regulator-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "1v8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_2v8: regulator-2v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "2v8";</div><div class='add'>+		regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3v3: regulator-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "3v3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_pcieb: regulator-pcie {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "mpcie_3v3";</div><div class='add'>+		gpio = &lt;&amp;pca9557_a 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_audio: regulator-audio {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "cs42888_supply";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_audio_5v: regulator-audio-pwr {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "audio-5v";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_audio_3v3: regulator-audio-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "audio-3v3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_audio_1v8: regulator-audio-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "audio-1v8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_can_en: regulator-can-en {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "can-en";</div><div class='add'>+		gpio = &lt;&amp;pca6416 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_can_stby: regulator-can-stby {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "can-stby";</div><div class='add'>+		gpio = &lt;&amp;pca6416 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		vin-supply = &lt;&amp;reg_can_en&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_fec2_supply: regulator-fec2_nvcc {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "fec2_nvcc";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		gpio = &lt;&amp;max7322 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb_otg1_vbus: regulator-usbotg1-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-name = "usb_otg1_vbus";</div><div class='add'>+		gpio = &lt;&amp;pca9557_b 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		vdev0vring0: memory@90000000 {</div><div class='add'>+			reg = &lt;0 0x90000000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev0vring1: memory@90008000 {</div><div class='add'>+			reg = &lt;0 0x90008000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev1vring0: memory@90010000 {</div><div class='add'>+			reg = &lt;0 0x90010000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev1vring1: memory@90018000 {</div><div class='add'>+			reg = &lt;0 0x90018000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rsc_table: memory@900ff000 {</div><div class='add'>+			reg = &lt;0 0x900ff000 0 0x1000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdevbuffer: memory@90400000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x90400000 0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dsp_vdev0vring0: memory@942f0000 {</div><div class='add'>+			reg = &lt;0 0x942f0000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dsp_vdev0vring1: memory@942f8000 {</div><div class='add'>+			reg = &lt;0 0x942f8000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dsp_vdev0buffer: memory@94300000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x94300000 0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* global autoconfigured region for contiguous allocations */</div><div class='add'>+		linux,cma {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			alloc-ranges = &lt;0 0xc0000000 0 0x3c000000&gt;;</div><div class='add'>+			size = &lt;0 0x3c000000&gt;;</div><div class='add'>+			linux,cma-default;</div><div class='add'>+			reusable;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu_reserved: memory@880000000 {</div><div class='add'>+			no-map;</div><div class='add'>+			reg = &lt;0x8 0x80000000 0 0x10000000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-bt-sco {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,bitclock-inversion;</div><div class='add'>+		simple-audio-card,bitclock-master = &lt;&amp;btcpu&gt;;</div><div class='add'>+		simple-audio-card,format = "dsp_a";</div><div class='add'>+		simple-audio-card,frame-master = &lt;&amp;btcpu&gt;;</div><div class='add'>+		simple-audio-card,name = "bt-sco-audio";</div><div class='add'>+</div><div class='add'>+		simple-audio-card,codec {</div><div class='add'>+			sound-dai = &lt;&amp;bt_sco_codec 1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		btcpu: simple-audio-card,cpu {</div><div class='add'>+			dai-tdm-slot-num = &lt;2&gt;;</div><div class='add'>+			dai-tdm-slot-width = &lt;16&gt;;</div><div class='add'>+			sound-dai = &lt;&amp;sai0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-cs42888 {</div><div class='add'>+		compatible = "fsl,imx-audio-cs42888";</div><div class='add'>+		audio-asrc = &lt;&amp;asrc0&gt;;</div><div class='add'>+		audio-codec = &lt;&amp;cs42888&gt;;</div><div class='add'>+		audio-cpu = &lt;&amp;esai0&gt;;</div><div class='add'>+		audio-routing =</div><div class='add'>+			"Line Out Jack", "AOUT1L",</div><div class='add'>+			"Line Out Jack", "AOUT1R",</div><div class='add'>+			"Line Out Jack", "AOUT2L",</div><div class='add'>+			"Line Out Jack", "AOUT2R",</div><div class='add'>+			"Line Out Jack", "AOUT3L",</div><div class='add'>+			"Line Out Jack", "AOUT3R",</div><div class='add'>+			"Line Out Jack", "AOUT4L",</div><div class='add'>+			"Line Out Jack", "AOUT4R",</div><div class='add'>+			"AIN1L", "Line In Jack",</div><div class='add'>+			"AIN1R", "Line In Jack",</div><div class='add'>+			"AIN2L", "Line In Jack",</div><div class='add'>+			"AIN2R", "Line In Jack";</div><div class='add'>+		model = "imx-cs42888";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-wm8960 {</div><div class='add'>+		compatible = "fsl,imx-audio-wm8960";</div><div class='add'>+		model = "wm8960-audio";</div><div class='add'>+		audio-cpu = &lt;&amp;sai1&gt;;</div><div class='add'>+		audio-codec = &lt;&amp;wm8960&gt;;</div><div class='add'>+		hp-det-gpios = &lt;&amp;lsio_gpio1 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		audio-routing = "Headphone Jack", "HP_L",</div><div class='add'>+				"Headphone Jack", "HP_R",</div><div class='add'>+				"Ext Spk", "SPK_LP",</div><div class='add'>+				"Ext Spk", "SPK_LN",</div><div class='add'>+				"Ext Spk", "SPK_RP",</div><div class='add'>+				"Ext Spk", "SPK_RN",</div><div class='add'>+				"LINPUT1", "Mic Jack",</div><div class='add'>+				"Mic Jack", "MICB";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-wm8962 {</div><div class='add'>+		compatible = "fsl,imx-audio-wm8962";</div><div class='add'>+		model = "wm8962-audio";</div><div class='add'>+		audio-cpu = &lt;&amp;sai1&gt;;</div><div class='add'>+		audio-codec = &lt;&amp;wm8962&gt;;</div><div class='add'>+		hp-det-gpios = &lt;&amp;lsio_gpio1 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		audio-routing = "Headphone Jack", "HPOUTL",</div><div class='add'>+				"Headphone Jack", "HPOUTR",</div><div class='add'>+				"Ext Spk", "SPKOUTL",</div><div class='add'>+				"Ext Spk", "SPKOUTR",</div><div class='add'>+				"AMIC", "MICBIAS",</div><div class='add'>+				"IN3R", "AMIC",</div><div class='add'>+				"IN1R", "AMIC";</div><div class='add'>+	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;adma_lpuart0 {</div><div class='add'>+&amp;amix {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;asrc0 {</div><div class='add'>+	fsl,asrc-rate = &lt;48000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsp {</div><div class='add'>+	memory-region = &lt;&amp;dsp_vdev0buffer&gt;, &lt;&amp;dsp_vdev0vring0&gt;,</div><div class='add'>+			&lt;&amp;dsp_vdev0vring1&gt;, &lt;&amp;dsp_reserved&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsp_reserved {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;esai0 {</div><div class='add'>+	assigned-clocks = &lt;&amp;acm IMX_ADMA_ACM_ESAI0_MCLK_SEL&gt;,</div><div class='add'>+			&lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL&gt;,</div><div class='add'>+			&lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS&gt;,</div><div class='add'>+			&lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS&gt;,</div><div class='add'>+			&lt;&amp;esai0_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;aud_pll_div0_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;0&gt;, &lt;786432000&gt;, &lt;49152000&gt;, &lt;12288000&gt;, &lt;49152000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_esai0&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='del'>-	pinctrl-0 = &lt;&amp;pinctrl_lpuart0&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -41,6 +413,8 @@</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pinctrl_fec1&gt;;</div><div class='ctx'> 	phy-mode = "rgmii-id";</div><div class='ctx'> 	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	nvmem-cells = &lt;&amp;fec_mac0&gt;;</div><div class='add'>+	nvmem-cell-names = "mac-address";</div><div class='ctx'> 	fsl,magic-packet;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='hunk'>@@ -52,10 +426,27 @@</div><div class='ctx'> 			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='ctx'> 			reg = &lt;0&gt;;</div><div class='ctx'> 		};</div><div class='add'>+</div><div class='add'>+		ethphy1: ethernet-phy@1 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;adma_i2c1 {</div><div class='add'>+&amp;fec2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec2&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy1&gt;;</div><div class='add'>+	phy-supply = &lt;&amp;reg_fec2_supply&gt;;</div><div class='add'>+	fsl,magic-packet;</div><div class='add'>+	nvmem-cells = &lt;&amp;fec_mac1&gt;;</div><div class='add'>+	nvmem-cell-names = "mac-address";</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='ctx'> 	#address-cells = &lt;1&gt;;</div><div class='ctx'> 	#size-cells = &lt;0&gt;;</div><div class='ctx'> 	clock-frequency = &lt;100000&gt;;</div><div class='hunk'>@@ -63,7 +454,7 @@</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pinctrl_lpi2c1 &amp;pinctrl_ioexp_rst&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='del'>-	i2c-switch@71 {</div><div class='add'>+	i2c-mux@71 {</div><div class='ctx'> 		compatible = "nxp,pca9646", "nxp,pca9546";</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;0&gt;;</div><div class='hunk'>@@ -97,6 +488,8 @@</div><div class='ctx'> 			pressure-sensor@60 {</div><div class='ctx'> 				compatible = "fsl,mpl3115";</div><div class='ctx'> 				reg = &lt;0x60&gt;;</div><div class='add'>+				vdd-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+				vddio-supply = &lt;&amp;reg_3v3&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -129,13 +522,281 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	ptn5110: tcpc@50 {</div><div class='add'>+		compatible = "nxp,ptn5110", "tcpci";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_typec&gt;;</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;lsio_gpio1&gt;;</div><div class='add'>+		interrupts = &lt;3 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		usb_con1: connector {</div><div class='add'>+			compatible = "usb-c-connector";</div><div class='add'>+			label = "USB-C";</div><div class='add'>+			power-role = "source";</div><div class='add'>+			data-role = "dual";</div><div class='add'>+			source-pdos = &lt;PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)&gt;;</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					typec_dr_sw: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;usb3_drd_sw&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					typec_con_ss: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;usb3_data_ss&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;usdhc1 {</div><div class='del'>-	assigned-clocks = &lt;&amp;clk IMX_CONN_SDHC0_CLK&gt;;</div><div class='del'>-	assigned-clock-rates = &lt;200000000&gt;;</div><div class='add'>+&amp;cm40_i2c {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_cm40_i2c&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_cm40_i2c_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;lsio_gpio1 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;lsio_gpio1 9 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pca6416: gpio@20 {</div><div class='add'>+		compatible = "ti,tca6416";</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cs42888: audio-codec@48 {</div><div class='add'>+		compatible = "cirrus,cs42888";</div><div class='add'>+		reg = &lt;0x48&gt;;</div><div class='add'>+		clocks = &lt;&amp;mclkout0_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-names = "mclk";</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL&gt;,</div><div class='add'>+				&lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS&gt;,</div><div class='add'>+				&lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS&gt;,</div><div class='add'>+				&lt;&amp;mclkout0_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;786432000&gt;, &lt;49152000&gt;, &lt;12288000&gt;, &lt;12288000&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pca9557_b 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		VA-supply = &lt;&amp;reg_audio&gt;;</div><div class='add'>+		VD-supply = &lt;&amp;reg_audio&gt;;</div><div class='add'>+		VLC-supply = &lt;&amp;reg_audio&gt;;</div><div class='add'>+		VLS-supply = &lt;&amp;reg_audio&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cm40_intmux {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hsio_phy {</div><div class='add'>+	fsl,hsio-cfg = "pciea-x2-pcieb";</div><div class='add'>+	fsl,refclk-pad-mode = "input";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan1&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	xceiver-supply = &lt;&amp;reg_can_stby&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan2 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan2&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	xceiver-supply = &lt;&amp;reg_can_stby&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexspi0 {</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexspi0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash0: flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;133000000&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;8&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;8&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;jpegdec {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;jpegenc {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpuart0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpuart1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "nxp,88w8987-bt";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpuart2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpuart3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_mu5 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mu_m0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mu1_m0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	phys = &lt;&amp;hsio_phy 0 PHY_TYPE_PCIE 0&gt;;</div><div class='add'>+	phy-names = "pcie-phy";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcieb&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	reset-gpios = &lt;&amp;lsio_gpio4 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vpcie-supply = &lt;&amp;reg_pcieb&gt;;</div><div class='add'>+	vpcie3v3aux-supply = &lt;&amp;reg_pcieb&gt;;</div><div class='add'>+	supports-clkreq;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0_ep {</div><div class='add'>+	phys = &lt;&amp;hsio_phy 0 PHY_TYPE_PCIE 0&gt;;</div><div class='add'>+	phy-names = "pcie-phy";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcieb&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	vpcie-supply = &lt;&amp;reg_pcieb&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;scu_key {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai0 {</div><div class='add'>+	#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS&gt;,</div><div class='add'>+			  &lt;&amp;sai0_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;786432000&gt;, &lt;49152000&gt;, &lt;12288000&gt;, &lt;49152000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai1 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS&gt;,</div><div class='add'>+			  &lt;&amp;sai1_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;786432000&gt;, &lt;49152000&gt;, &lt;12288000&gt;, &lt;49152000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai4 {</div><div class='add'>+	assigned-clocks = &lt;&amp;acm IMX_ADMA_ACM_SAI4_MCLK_SEL&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS&gt;,</div><div class='add'>+			  &lt;&amp;sai4_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;aud_pll_div1_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;0&gt;, &lt;786432000&gt;, &lt;98304000&gt;, &lt;12288000&gt;, &lt;98304000&gt;;</div><div class='add'>+	fsl,sai-asynchronous;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai5 {</div><div class='add'>+	assigned-clocks = &lt;&amp;acm IMX_ADMA_ACM_SAI5_MCLK_SEL&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS&gt;,</div><div class='add'>+			  &lt;&amp;sai5_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;aud_pll_div1_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;0&gt;, &lt;786432000&gt;, &lt;98304000&gt;, &lt;12288000&gt;, &lt;98304000&gt;;</div><div class='add'>+	fsl,sai-asynchronous;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;thermal_zones {</div><div class='add'>+	pmic-thermal {</div><div class='add'>+		polling-delay-passive = &lt;250&gt;;</div><div class='add'>+		polling-delay = &lt;2000&gt;;</div><div class='add'>+		thermal-sensors = &lt;&amp;tsens IMX_SC_R_PMIC_0&gt;;</div><div class='add'>+</div><div class='add'>+		trips {</div><div class='add'>+			pmic_alert0: trip0 {</div><div class='add'>+				temperature = &lt;110000&gt;;</div><div class='add'>+				hysteresis = &lt;2000&gt;;</div><div class='add'>+				type = "passive";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pmic_crit0: trip1 {</div><div class='add'>+				temperature = &lt;125000&gt;;</div><div class='add'>+				hysteresis = &lt;2000&gt;;</div><div class='add'>+				type = "critical";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cooling-maps {</div><div class='add'>+			map0 {</div><div class='add'>+				trip = &lt;&amp;pmic_alert0&gt;;</div><div class='add'>+				cooling-device =</div><div class='add'>+					&lt;&amp;A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+					&lt;&amp;A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+					&lt;&amp;A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+					&lt;&amp;A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='ctx'> 	bus-width = &lt;8&gt;;</div><div class='ctx'> 	no-sd;</div><div class='ctx'> 	no-sdio;</div><div class='hunk'>@@ -144,10 +805,12 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;usdhc2 {</div><div class='del'>-	assigned-clocks = &lt;&amp;clk IMX_CONN_SDHC1_CLK&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER&gt;;</div><div class='ctx'> 	assigned-clock-rates = &lt;200000000&gt;;</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='ctx'> 	bus-width = &lt;4&gt;;</div><div class='ctx'> 	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='ctx'> 	cd-gpios = &lt;&amp;lsio_gpio4 22 GPIO_ACTIVE_LOW&gt;;</div><div class='hunk'>@@ -155,7 +818,89 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;usb3_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbphy1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	adp-disable;</div><div class='add'>+	hnp-disable;</div><div class='add'>+	srp-disable;</div><div class='add'>+	disable-over-current;</div><div class='add'>+	power-active-high;</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usb_otg1_vbus&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg3_cdns3 {</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	port {</div><div class='add'>+		usb3_drd_sw: endpoint {</div><div class='add'>+			remote-endpoint = &lt;&amp;typec_dr_sw&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+&amp;vpu {</div><div class='add'>+	compatible = "nxp,imx8qxp-vpu";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;vpu_core0 {</div><div class='add'>+	reg = &lt;0x2d040000 0x10000&gt;;</div><div class='add'>+	memory-region = &lt;&amp;decoder_boot&gt;, &lt;&amp;decoder_rpc&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;vpu_core1 {</div><div class='add'>+	reg = &lt;0x2d050000 0x10000&gt;;</div><div class='add'>+	memory-region = &lt;&amp;encoder_boot&gt;, &lt;&amp;encoder_rpc&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;iomuxc {</div><div class='add'>+</div><div class='add'>+	pinctrl_cm40_i2c: cm40i2cgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QXP_ADC_IN1_M40_I2C0_SDA				0x0600004c</div><div class='add'>+			IMX8QXP_ADC_IN0_M40_I2C0_SCL				0x0600004c</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_cm40_i2c_gpio: cm40i2cgpio-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QXP_ADC_IN1_LSIO_GPIO1_IO09				0xc600004c</div><div class='add'>+			IMX8QXP_ADC_IN0_LSIO_GPIO1_IO10				0xc600004c</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_esai0: esai0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QXP_ESAI0_FSR_ADMA_ESAI0_FSR			0xc6000040</div><div class='add'>+			IMX8QXP_ESAI0_FST_ADMA_ESAI0_FST			0xc6000040</div><div class='add'>+			IMX8QXP_ESAI0_SCKR_ADMA_ESAI0_SCKR			0xc6000040</div><div class='add'>+			IMX8QXP_ESAI0_SCKT_ADMA_ESAI0_SCKT			0xc6000040</div><div class='add'>+			IMX8QXP_ESAI0_TX0_ADMA_ESAI0_TX0			0xc6000040</div><div class='add'>+			IMX8QXP_ESAI0_TX1_ADMA_ESAI0_TX1			0xc6000040</div><div class='add'>+			IMX8QXP_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3		0xc6000040</div><div class='add'>+			IMX8QXP_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2		0xc6000040</div><div class='add'>+			IMX8QXP_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1		0xc6000040</div><div class='add'>+			IMX8QXP_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0		0xc6000040</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	pinctrl_fec1: fec1grp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			IMX8QXP_ENET0_MDC_CONN_ENET0_MDC			0x06000020</div><div class='hunk'>@@ -175,7 +920,66 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pinctrl_ioexp_rst: ioexp_rst_grp {</div><div class='add'>+	pinctrl_fec2: fec2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL		0x00000060</div><div class='add'>+			IMX8QXP_ESAI0_FSR_CONN_ENET1_RGMII_TXC			0x00000060</div><div class='add'>+			IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0		0x00000060</div><div class='add'>+			IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1		0x00000060</div><div class='add'>+			IMX8QXP_ESAI0_FST_CONN_ENET1_RGMII_TXD2			0x00000060</div><div class='add'>+			IMX8QXP_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3		0x00000060</div><div class='add'>+			IMX8QXP_ESAI0_TX0_CONN_ENET1_RGMII_RXC			0x00000060</div><div class='add'>+			IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL		0x00000060</div><div class='add'>+			IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0			0x00000060</div><div class='add'>+			IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1		0x00000060</div><div class='add'>+			IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2		0x00000060</div><div class='add'>+			IMX8QXP_ESAI0_TX1_CONN_ENET1_RGMII_RXD3			0x00000060</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan1: flexcan0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX			0x21</div><div class='add'>+			IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX			0x21</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan2: flexcan1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX			0x21</div><div class='add'>+			IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX			0x21</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c_mipi_csi0: i2c-mipi-csi0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QXP_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL		0xc2000020</div><div class='add'>+			IMX8QXP_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA		0xc2000020</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexspi0: flexspi0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0			0x06000021</div><div class='add'>+			IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1			0x06000021</div><div class='add'>+			IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2			0x06000021</div><div class='add'>+			IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3			0x06000021</div><div class='add'>+			IMX8QXP_QSPI0A_DQS_LSIO_QSPI0A_DQS			0x06000021</div><div class='add'>+			IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B			0x06000021</div><div class='add'>+			IMX8QXP_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B			0x06000021</div><div class='add'>+			IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK			0x06000021</div><div class='add'>+			IMX8QXP_QSPI0B_SCLK_LSIO_QSPI0B_SCLK			0x06000021</div><div class='add'>+			IMX8QXP_QSPI0B_DATA0_LSIO_QSPI0B_DATA0			0x06000021</div><div class='add'>+			IMX8QXP_QSPI0B_DATA1_LSIO_QSPI0B_DATA1			0x06000021</div><div class='add'>+			IMX8QXP_QSPI0B_DATA2_LSIO_QSPI0B_DATA2			0x06000021</div><div class='add'>+			IMX8QXP_QSPI0B_DATA3_LSIO_QSPI0B_DATA3			0x06000021</div><div class='add'>+			IMX8QXP_QSPI0B_DQS_LSIO_QSPI0B_DQS			0x06000021</div><div class='add'>+			IMX8QXP_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B			0x06000021</div><div class='add'>+			IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B			0x06000021</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ioexp_rst: ioexprstgrp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01			0x06000021</div><div class='ctx'> 		&gt;;</div><div class='hunk'>@@ -201,6 +1005,76 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	pinctrl_lpuart1: lpuart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QXP_UART1_TX_ADMA_UART1_TX				0x06000020</div><div class='add'>+			IMX8QXP_UART1_RX_ADMA_UART1_RX				0x06000020</div><div class='add'>+			IMX8QXP_UART1_RTS_B_ADMA_UART1_RTS_B			0x06000020</div><div class='add'>+			IMX8QXP_UART1_CTS_B_ADMA_UART1_CTS_B			0x06000020</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpuart2: lpuart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QXP_UART2_TX_ADMA_UART2_TX				0x06000020</div><div class='add'>+			IMX8QXP_UART2_RX_ADMA_UART2_RX				0x06000020</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpuart3: lpuart3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX			0x06000020</div><div class='add'>+			IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX			0x06000020</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_mipi_csi0: mipi-csi0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QXP_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07		0xC0000041</div><div class='add'>+			IMX8QXP_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08		0xC0000041</div><div class='add'>+			IMX8QXP_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT	0xC0000041</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcieb: pcieagrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00		0x06000021</div><div class='add'>+			IMX8QXP_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B		0x06000021</div><div class='add'>+			IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02		0x04000021</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_typec: typecgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03			0x06000021</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_typec_mux: typecmuxgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09		0x60</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai0: sai0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QXP_SAI0_TXD_ADMA_SAI0_TXD		0x06000060</div><div class='add'>+			IMX8QXP_SAI0_RXD_ADMA_SAI0_RXD		0x06000040</div><div class='add'>+			IMX8QXP_SAI0_TXC_ADMA_SAI0_TXC		0x06000040</div><div class='add'>+			IMX8QXP_SAI0_TXFS_ADMA_SAI0_TXFS	0x06000040</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai1: sai1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QXP_SAI1_RXD_ADMA_SAI1_RXD				0x06000040</div><div class='add'>+			IMX8QXP_SAI1_RXC_ADMA_SAI1_TXC				0x06000040</div><div class='add'>+			IMX8QXP_SAI1_RXFS_ADMA_SAI1_TXFS			0x06000040</div><div class='add'>+			IMX8QXP_SPI0_CS1_ADMA_SAI1_TXD				0x06000060</div><div class='add'>+			IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00			0x06000040</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	pinctrl_usdhc1: usdhc1grp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK			0x06000041</div><div class='hunk'>@@ -217,6 +1091,14 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19			0x00000021</div><div class='add'>+			IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21			0x00000021</div><div class='add'>+			IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22			0x00000021</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	pinctrl_usdhc2: usdhc2grp {</div><div class='ctx'> 		fsl,pins = &lt;</div><div class='ctx'> 			IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK			0x06000041</div><div class='hunk'>@@ -229,11 +1111,3 @@</div><div class='ctx'> 		&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='del'>-</div><div class='del'>-&amp;adma_dsp {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;scu_key {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi<br/>new file mode 100644<br/>index 000000000000..7bae516004bf<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi</a></div><div class='hunk'>@@ -0,0 +1,37 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2018-2020 NXP</div><div class='add'>+ *	Dong Aisheng &lt;aisheng.dong@nxp.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;lpuart0 {</div><div class='add'>+	compatible = "fsl,imx8qxp-lpuart";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart1 {</div><div class='add'>+	compatible = "fsl,imx8qxp-lpuart";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart2 {</div><div class='add'>+	compatible = "fsl,imx8qxp-lpuart";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart3 {</div><div class='add'>+	compatible = "fsl,imx8qxp-lpuart";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi<br/>new file mode 100644<br/>index 000000000000..4eb48ad48745<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi</a></div><div class='hunk'>@@ -0,0 +1,29 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2018-2020 NXP</div><div class='add'>+ *	Dong Aisheng &lt;aisheng.dong@nxp.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;usbphy1 {</div><div class='add'>+	compatible = "fsl,imx8qxp-usbphy", "fsl,imx7ulp-usbphy";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	compatible = "fsl,imx8qxp-fec", "fsl,imx8qm-fec", "fsl,imx6sx-fec";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec2 {</div><div class='add'>+	compatible = "fsl,imx8qxp-fec", "fsl,imx8qm-fec", "fsl,imx6sx-fec";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-hsio.dtsi<br/>new file mode 100644<br/>index 000000000000..255b8c91c88c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8qxp-ss-hsio.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8qxp-ss-hsio.dtsi</a></div><div class='hunk'>@@ -0,0 +1,47 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 NXP</div><div class='add'>+ *	Richard Zhu &lt;hongxing.zhu@nxp.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;hsio_subsys {</div><div class='add'>+	phyx1_lpcg: clock-controller@5f090000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-lpcg";</div><div class='add'>+		reg = &lt;0x5f090000 0x10000&gt;;</div><div class='add'>+		clocks = &lt;&amp;hsio_refb_clk&gt;, &lt;&amp;hsio_per_clk&gt;,</div><div class='add'>+			 &lt;&amp;hsio_per_clk&gt;, &lt;&amp;hsio_per_clk&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clock-indices = &lt;IMX_LPCG_CLK_0&gt;, &lt;IMX_LPCG_CLK_1&gt;,</div><div class='add'>+				&lt;IMX_LPCG_CLK_2&gt;, &lt;IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-output-names = "hsio_phyx1_pclk",</div><div class='add'>+				     "hsio_phyx1_epcs_tx_clk",</div><div class='add'>+				     "hsio_phyx1_epcs_rx_clk",</div><div class='add'>+				     "hsio_phyx1_apb_clk";</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SERDES_1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsio_phy: phy@5f1a0000 {</div><div class='add'>+		compatible = "fsl,imx8qxp-hsio";</div><div class='add'>+		reg = &lt;0x5f1a0000 0x10000&gt;,</div><div class='add'>+		      &lt;0x5f120000 0x10000&gt;,</div><div class='add'>+		      &lt;0x5f140000 0x10000&gt;,</div><div class='add'>+		      &lt;0x5f160000 0x10000&gt;;</div><div class='add'>+		reg-names = "reg", "phy", "ctrl", "misc";</div><div class='add'>+		clocks = &lt;&amp;phyx1_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+			 &lt;&amp;phyx1_lpcg IMX_LPCG_CLK_1&gt;,</div><div class='add'>+			 &lt;&amp;phyx1_crr1_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;pcieb_crr3_lpcg IMX_LPCG_CLK_4&gt;,</div><div class='add'>+			 &lt;&amp;misc_crr5_lpcg IMX_LPCG_CLK_4&gt;;</div><div class='add'>+		clock-names = "pclk0", "apb_pclk0", "phy0_crr", "ctl0_crr",</div><div class='add'>+			      "misc_crr";</div><div class='add'>+		#phy-cells = &lt;3&gt;;</div><div class='add'>+		power-domains = &lt;&amp;pd IMX_SC_R_SERDES_1&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0: pcie@5f010000 {</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_ep: pcie-ep@5f010000 {</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi<br/>new file mode 100644<br/>index 000000000000..232cf25dadfc<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi</a></div><div class='hunk'>@@ -0,0 +1,97 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021 NXP</div><div class='add'>+ *	Dong Aisheng &lt;aisheng.dong@nxp.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;csi1_pxl_lpcg {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;csi1_core_lpcg {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;csi1_esc_lpcg {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio0_mipi_csi1 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c_mipi_csi1 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;irqsteer_csi1 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;isi {</div><div class='add'>+	compatible = "fsl,imx8qxp-isi";</div><div class='add'>+	reg = &lt;0x58100000 0x60000&gt;;</div><div class='add'>+	interrupts = &lt;GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+		     &lt;GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	clocks = &lt;&amp;pdma0_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+		 &lt;&amp;pdma1_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+		 &lt;&amp;pdma2_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+		 &lt;&amp;pdma3_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+		 &lt;&amp;pdma4_lpcg IMX_LPCG_CLK_0&gt;,</div><div class='add'>+		 &lt;&amp;pdma5_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+	clock-names = "per0", "per1", "per2", "per3", "per4", "per5";</div><div class='add'>+	power-domains = &lt;&amp;pd IMX_SC_R_ISI_CH0&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_ISI_CH1&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_ISI_CH2&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_ISI_CH3&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_ISI_CH4&gt;,</div><div class='add'>+			&lt;&amp;pd IMX_SC_R_ISI_CH5&gt;;</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		port@2 {</div><div class='add'>+			reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			isi_in_2: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;mipi_csi0_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_csi_0 {</div><div class='add'>+	ports {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		port@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			mipi_csi0_out: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;isi_in_2&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;jpegdec {</div><div class='add'>+	compatible = "nxp,imx8qxp-jpgdec";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;jpegenc {</div><div class='add'>+	compatible = "nxp,imx8qxp-jpgenc";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_csi_1 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi<br/>new file mode 100644<br/>index 000000000000..8f722b1dd078<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi</a></div><div class='hunk'>@@ -0,0 +1,94 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2018-2020 NXP</div><div class='add'>+ *	Dong Aisheng &lt;aisheng.dong@nxp.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio0 {</div><div class='add'>+	compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";</div><div class='add'>+	gpio-ranges = &lt;&amp;iomuxc 1 56 12&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 13 69 4&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 19 75 4&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 24 80 1&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 25 82 7&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio1 {</div><div class='add'>+	compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";</div><div class='add'>+	gpio-ranges = &lt;&amp;iomuxc 0 89 9&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 9 99 16&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 25 116 7&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio2 {</div><div class='add'>+	compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";</div><div class='add'>+	gpio-ranges = &lt;&amp;iomuxc 0 123 1&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 1 126 2&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 3 129 1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio3 {</div><div class='add'>+	compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";</div><div class='add'>+	gpio-ranges = &lt;&amp;iomuxc 0 146 4&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 4 151 13&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 17 165 8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio4 {</div><div class='add'>+	compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";</div><div class='add'>+	gpio-ranges = &lt;&amp;iomuxc 0 0 3&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 3 4 4&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 7 9 6&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 13 16 6&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 19 23 2&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 21 26 2&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 23 30 6&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 29 37 3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio5 {</div><div class='add'>+	compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";</div><div class='add'>+	gpio-ranges = &lt;&amp;iomuxc 0 40 3&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 3 44 6&gt;,</div><div class='add'>+		      &lt;&amp;iomuxc 9 51 3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio6 {</div><div class='add'>+	compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio7 {</div><div class='add'>+	compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_mu0 {</div><div class='add'>+	compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_mu1 {</div><div class='add'>+	compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_mu2 {</div><div class='add'>+	compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_mu3 {</div><div class='add'>+	compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_mu4 {</div><div class='add'>+	compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_mu5 {</div><div class='add'>+	compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_mu6 {</div><div class='add'>+	compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_mu13 {</div><div class='add'>+	compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-security.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-security.dtsi<br/>new file mode 100644<br/>index 000000000000..15f1239dab24<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8qxp-ss-security.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8qxp-ss-security.dtsi</a></div><div class='hunk'>@@ -0,0 +1,16 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2025 Actia Nordic AB</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;crypto {</div><div class='add'>+	compatible = "fsl,imx8qxp-caam", "fsl,sec-v4.0";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sec_jr2 {</div><div class='add'>+	compatible = "fsl,imx8qxp-job-ring", "fsl,sec-v4.0-job-ring";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sec_jr3 {</div><div class='add'>+	compatible = "fsl,imx8qxp-job-ring", "fsl,sec-v4.0-job-ring";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-vpu.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-vpu.dtsi<br/>new file mode 100644<br/>index 000000000000..f81937b5fb72<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8qxp-ss-vpu.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8qxp-ss-vpu.dtsi</a></div><div class='hunk'>@@ -0,0 +1,25 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR X11)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Alexander Stein</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;mu_m0 {</div><div class='add'>+	interrupts = &lt;GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mu1_m0 {</div><div class='add'>+	interrupts = &lt;GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;vpu_core0 {</div><div class='add'>+	reg = &lt;0x2d040000 0x10000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;vpu_core1 {</div><div class='add'>+	reg = &lt;0x2d050000 0x10000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/delete-node/ &amp;mu2_m0;</div><div class='add'>+/delete-node/ &amp;vpu_core2;</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-tqma8xqp-mba8xx.dts b/arch/arm64/boot/dts/freescale/imx8qxp-tqma8xqp-mba8xx.dts<br/>new file mode 100644<br/>index 000000000000..7d2e98bf8bc5<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8qxp-tqma8xqp-mba8xx.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8qxp-tqma8xqp-mba8xx.dts</a></div><div class='hunk'>@@ -0,0 +1,16 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR X11)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2018-2023 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Alexander Stein</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8qxp-tqma8xqp.dtsi"</div><div class='add'>+#include "mba8xx.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "TQ-Systems i.MX8QXP TQMa8XQP on MBa8Xx";</div><div class='add'>+	compatible = "tq,imx8qxp-tqma8xqp-mba8xx", "tq,imx8qxp-tqma8xqp", "fsl,imx8qxp";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-tqma8xqp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-tqma8xqp.dtsi<br/>new file mode 100644<br/>index 000000000000..b14040bf4ddd<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8qxp-tqma8xqp.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8qxp-tqma8xqp.dtsi</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR X11)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2018-2023 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Alexander Stein</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "imx8qxp.dtsi"</div><div class='add'>+#include "tqma8xx.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "TQ-Systems i.MX8QXP TQMa8XQP";</div><div class='add'>+	compatible = "tq,imx8qxp-tqma8xqp", "fsl,imx8qxp";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-tqma8xqps-mb-smarc-2.dts b/arch/arm64/boot/dts/freescale/imx8qxp-tqma8xqps-mb-smarc-2.dts<br/>new file mode 100644<br/>index 000000000000..3fa9b5aee2c3<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8qxp-tqma8xqps-mb-smarc-2.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8qxp-tqma8xqps-mb-smarc-2.dts</a></div><div class='hunk'>@@ -0,0 +1,16 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2018-2025 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Alexander Stein</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8qxp-tqma8xqps.dtsi"</div><div class='add'>+#include "tqma8xxs-mb-smarc-2.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "TQ-Systems i.MX8QXP TQMa8XQPS on MB-SMARC-2";</div><div class='add'>+	compatible = "tq,imx8qxp-tqma8xqps-mb-smarc-2", "tq,imx8qxp-tqma8xqps", "fsl,imx8qxp";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-tqma8xqps.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-tqma8xqps.dtsi<br/>new file mode 100644<br/>index 000000000000..f008b7a34505<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8qxp-tqma8xqps.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8qxp-tqma8xqps.dtsi</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2018-2025 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Alexander Stein</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "imx8qxp.dtsi"</div><div class='add'>+#include "tqma8xxs.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "TQ-Systems i.MX8QXP TQMa8XQPS";</div><div class='add'>+	compatible = "tq,imx8qxp-tqma8xqps", "fsl,imx8qxp";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi<br/>index e8ffb7590656..7c4a50e0ec9e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8qxp.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/imx8qxp.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8qxp.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8qxp.dtsi</a></div><div class='hunk'>@@ -1,11 +1,12 @@</div><div class='ctx'> // SPDX-License-Identifier: GPL-2.0+</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (C) 2016 Freescale Semiconductor, Inc.</div><div class='del'>- * Copyright 2017-2018 NXP</div><div class='add'>+ * Copyright 2017-2020 NXP</div><div class='ctx'>  *	Dong Aisheng &lt;aisheng.dong@nxp.com&gt;</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;dt-bindings/clock/imx8-clock.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/imx8-lpcg.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/firmware/imx/rsrc.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/input/input.h&gt;</div><div class='hunk'>@@ -19,6 +20,8 @@</div><div class='ctx'> 	#size-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='ctx'> 	aliases {</div><div class='add'>+		ethernet0 = &amp;fec1;</div><div class='add'>+		ethernet1 = &amp;fec2;</div><div class='ctx'> 		gpio0 = &amp;lsio_gpio0;</div><div class='ctx'> 		gpio1 = &amp;lsio_gpio1;</div><div class='ctx'> 		gpio2 = &amp;lsio_gpio2;</div><div class='hunk'>@@ -27,14 +30,28 @@</div><div class='ctx'> 		gpio5 = &amp;lsio_gpio5;</div><div class='ctx'> 		gpio6 = &amp;lsio_gpio6;</div><div class='ctx'> 		gpio7 = &amp;lsio_gpio7;</div><div class='add'>+		i2c0 = &amp;i2c0;</div><div class='add'>+		i2c1 = &amp;i2c1;</div><div class='add'>+		i2c2 = &amp;i2c2;</div><div class='add'>+		i2c3 = &amp;i2c3;</div><div class='ctx'> 		mmc0 = &amp;usdhc1;</div><div class='ctx'> 		mmc1 = &amp;usdhc2;</div><div class='ctx'> 		mmc2 = &amp;usdhc3;</div><div class='add'>+		mu0 = &amp;lsio_mu0;</div><div class='ctx'> 		mu1 = &amp;lsio_mu1;</div><div class='del'>-		serial0 = &amp;adma_lpuart0;</div><div class='del'>-		serial1 = &amp;adma_lpuart1;</div><div class='del'>-		serial2 = &amp;adma_lpuart2;</div><div class='del'>-		serial3 = &amp;adma_lpuart3;</div><div class='add'>+		mu2 = &amp;lsio_mu2;</div><div class='add'>+		mu3 = &amp;lsio_mu3;</div><div class='add'>+		mu4 = &amp;lsio_mu4;</div><div class='add'>+		serial0 = &amp;lpuart0;</div><div class='add'>+		serial1 = &amp;lpuart1;</div><div class='add'>+		serial2 = &amp;lpuart2;</div><div class='add'>+		serial3 = &amp;lpuart3;</div><div class='add'>+		spi0 = &amp;lpspi0;</div><div class='add'>+		spi1 = &amp;lpspi1;</div><div class='add'>+		spi2 = &amp;lpspi2;</div><div class='add'>+		spi3 = &amp;lpspi3;</div><div class='add'>+		vpu-core0 = &amp;vpu_core0;</div><div class='add'>+		vpu-core1 = &amp;vpu_core1;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	cpus {</div><div class='hunk'>@@ -47,8 +64,14 @@</div><div class='ctx'> 			compatible = "arm,cortex-a35";</div><div class='ctx'> 			reg = &lt;0x0 0x0&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;A35_L2&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk IMX_A35_CLK&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU&gt;;</div><div class='ctx'> 			operating-points-v2 = &lt;&amp;a35_opp_table&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='hunk'>@@ -58,8 +81,14 @@</div><div class='ctx'> 			compatible = "arm,cortex-a35";</div><div class='ctx'> 			reg = &lt;0x0 0x1&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;A35_L2&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk IMX_A35_CLK&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU&gt;;</div><div class='ctx'> 			operating-points-v2 = &lt;&amp;a35_opp_table&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='hunk'>@@ -69,8 +98,14 @@</div><div class='ctx'> 			compatible = "arm,cortex-a35";</div><div class='ctx'> 			reg = &lt;0x0 0x2&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;A35_L2&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk IMX_A35_CLK&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU&gt;;</div><div class='ctx'> 			operating-points-v2 = &lt;&amp;a35_opp_table&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='hunk'>@@ -80,14 +115,25 @@</div><div class='ctx'> 			compatible = "arm,cortex-a35";</div><div class='ctx'> 			reg = &lt;0x0 0x3&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;A35_L2&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk IMX_A35_CLK&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU&gt;;</div><div class='ctx'> 			operating-points-v2 = &lt;&amp;a35_opp_table&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		A35_L2: l2-cache0 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x80000&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;1024&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -113,6 +159,7 @@</div><div class='ctx'> 		compatible = "arm,gic-v3";</div><div class='ctx'> 		reg = &lt;0x0 0x51a00000 0 0x10000&gt;, /* GIC Dist */</div><div class='ctx'> 		      &lt;0x0 0x51b00000 0 0xc0000&gt;; /* GICR (RD_base + SGI_base) */</div><div class='add'>+		#address-cells = &lt;0&gt;;</div><div class='ctx'> 		#interrupt-cells = &lt;3&gt;;</div><div class='ctx'> 		interrupt-controller;</div><div class='ctx'> 		interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='hunk'>@@ -123,14 +170,35 @@</div><div class='ctx'> 		#size-cells = &lt;2&gt;;</div><div class='ctx'> 		ranges;</div><div class='ctx'> </div><div class='add'>+		decoder_boot: decoder-boot@84000000 {</div><div class='add'>+			reg = &lt;0 0x84000000 0 0x2000000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		encoder_boot: encoder-boot@86000000 {</div><div class='add'>+			reg = &lt;0 0x86000000 0 0x200000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		decoder_rpc: decoder-rpc@92000000 {</div><div class='add'>+			reg = &lt;0 0x92000000 0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		dsp_reserved: dsp@92400000 {</div><div class='ctx'> 			reg = &lt;0 0x92400000 0 0x2000000&gt;;</div><div class='ctx'> 			no-map;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		encoder_rpc: encoder-rpc@94400000 {</div><div class='add'>+			reg = &lt;0 0x94400000 0 0x700000&gt;;</div><div class='add'>+			no-map;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	pmu {</div><div class='del'>-		compatible = "arm,armv8-pmuv3";</div><div class='add'>+		compatible = "arm,cortex-a35-pmu";</div><div class='ctx'> 		interrupts = &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -139,49 +207,55 @@</div><div class='ctx'> 		method = "smc";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	scu {</div><div class='add'>+	system-controller {</div><div class='ctx'> 		compatible = "fsl,imx-scu";</div><div class='del'>-		mbox-names = "tx0", "tx1", "tx2", "tx3",</div><div class='del'>-			     "rx0", "rx1", "rx2", "rx3",</div><div class='add'>+		mbox-names = "tx0",</div><div class='add'>+			     "rx0",</div><div class='ctx'> 			     "gip3";</div><div class='ctx'> 		mboxes = &lt;&amp;lsio_mu1 0 0</div><div class='del'>-			  &amp;lsio_mu1 0 1</div><div class='del'>-			  &amp;lsio_mu1 0 2</div><div class='del'>-			  &amp;lsio_mu1 0 3</div><div class='ctx'> 			  &amp;lsio_mu1 1 0</div><div class='del'>-			  &amp;lsio_mu1 1 1</div><div class='del'>-			  &amp;lsio_mu1 1 2</div><div class='del'>-			  &amp;lsio_mu1 1 3</div><div class='ctx'> 			  &amp;lsio_mu1 3 3&gt;;</div><div class='ctx'> </div><div class='add'>+		pd: power-controller {</div><div class='add'>+			compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";</div><div class='add'>+			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		clk: clock-controller {</div><div class='del'>-			compatible = "fsl,imx8qxp-clk";</div><div class='del'>-			#clock-cells = &lt;1&gt;;</div><div class='del'>-			clocks = &lt;&amp;xtal32k &amp;xtal24m&gt;;</div><div class='del'>-			clock-names = "xtal_32KHz", "xtal_24Mhz";</div><div class='add'>+			compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";</div><div class='add'>+			#clock-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		iomuxc: pinctrl {</div><div class='ctx'> 			compatible = "fsl,imx8qxp-iomuxc";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		ocotp: imx8qx-ocotp {</div><div class='add'>+		ocotp: ocotp {</div><div class='ctx'> 			compatible = "fsl,imx8qxp-scu-ocotp";</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;1&gt;;</div><div class='del'>-		};</div><div class='ctx'> </div><div class='del'>-		pd: imx8qx-pd {</div><div class='del'>-			compatible = "fsl,imx8qxp-scu-pd";</div><div class='del'>-			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+			fec_mac0: mac@2c4 {</div><div class='add'>+				reg = &lt;0x2c4 6&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			fec_mac1: mac@2c6 {</div><div class='add'>+				reg = &lt;0x2c6 6&gt;;</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		scu_key: scu-key {</div><div class='add'>+		scu_key: keys {</div><div class='ctx'> 			compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";</div><div class='ctx'> 			linux,keycodes = &lt;KEY_POWER&gt;;</div><div class='add'>+			wakeup-source;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		scu_reset: reset-controller {</div><div class='add'>+			compatible = "fsl,imx-scu-reset";</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		rtc: rtc {</div><div class='ctx'> 			compatible = "fsl,imx8qxp-sc-rtc";</div><div class='ctx'> 		};</div><div class='hunk'>@@ -205,6 +279,13 @@</div><div class='ctx'> 			     &lt;GIC_PPI 10 IRQ_TYPE_LEVEL_LOW&gt;; /* Hypervisor */</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	clk_dummy: clock-dummy {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;0&gt;;</div><div class='add'>+		clock-output-names = "clk_dummy";</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	xtal32k: clock-xtal32k {</div><div class='ctx'> 		compatible = "fixed-clock";</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='hunk'>@@ -219,382 +300,8 @@</div><div class='ctx'> 		clock-output-names = "xtal_24MHz";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	adma_subsys: bus@59000000 {</div><div class='del'>-		compatible = "simple-bus";</div><div class='del'>-		#address-cells = &lt;1&gt;;</div><div class='del'>-		#size-cells = &lt;1&gt;;</div><div class='del'>-		ranges = &lt;0x59000000 0x0 0x59000000 0x2000000&gt;;</div><div class='del'>-</div><div class='del'>-		adma_lpcg: clock-controller@59000000 {</div><div class='del'>-			compatible = "fsl,imx8qxp-lpcg-adma";</div><div class='del'>-			reg = &lt;0x59000000 0x2000000&gt;;</div><div class='del'>-			#clock-cells = &lt;1&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		adma_dsp: dsp@596e8000 {</div><div class='del'>-			compatible = "fsl,imx8qxp-dsp";</div><div class='del'>-			reg = &lt;0x596e8000 0x88000&gt;;</div><div class='del'>-			clocks = &lt;&amp;adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK&gt;,</div><div class='del'>-				&lt;&amp;adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK&gt;,</div><div class='del'>-				&lt;&amp;adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK&gt;;</div><div class='del'>-			clock-names = "ipg", "ocram", "core";</div><div class='del'>-			power-domains = &lt;&amp;pd IMX_SC_R_MU_13A&gt;,</div><div class='del'>-				&lt;&amp;pd IMX_SC_R_MU_13B&gt;,</div><div class='del'>-				&lt;&amp;pd IMX_SC_R_DSP&gt;,</div><div class='del'>-				&lt;&amp;pd IMX_SC_R_DSP_RAM&gt;;</div><div class='del'>-			mbox-names = "txdb0", "txdb1",</div><div class='del'>-				"rxdb0", "rxdb1";</div><div class='del'>-			mboxes = &lt;&amp;lsio_mu13 2 0&gt;,</div><div class='del'>-				&lt;&amp;lsio_mu13 2 1&gt;,</div><div class='del'>-				&lt;&amp;lsio_mu13 3 0&gt;,</div><div class='del'>-				&lt;&amp;lsio_mu13 3 1&gt;;</div><div class='del'>-			memory-region = &lt;&amp;dsp_reserved&gt;;</div><div class='del'>-			status = "disabled";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		adma_lpuart0: serial@5a060000 {</div><div class='del'>-			compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";</div><div class='del'>-			reg = &lt;0x5a060000 0x1000&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;adma_lpcg IMX_ADMA_LPCG_UART0_IPG_CLK&gt;,</div><div class='del'>-				 &lt;&amp;adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK&gt;;</div><div class='del'>-			clock-names = "ipg", "baud";</div><div class='del'>-			power-domains = &lt;&amp;pd IMX_SC_R_UART_0&gt;;</div><div class='del'>-			status = "disabled";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		adma_lpuart1: serial@5a070000 {</div><div class='del'>-			compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";</div><div class='del'>-			reg = &lt;0x5a070000 0x1000&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;adma_lpcg IMX_ADMA_LPCG_UART1_IPG_CLK&gt;,</div><div class='del'>-				 &lt;&amp;adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK&gt;;</div><div class='del'>-			clock-names = "ipg", "baud";</div><div class='del'>-			power-domains = &lt;&amp;pd IMX_SC_R_UART_1&gt;;</div><div class='del'>-			status = "disabled";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		adma_lpuart2: serial@5a080000 {</div><div class='del'>-			compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";</div><div class='del'>-			reg = &lt;0x5a080000 0x1000&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;adma_lpcg IMX_ADMA_LPCG_UART2_IPG_CLK&gt;,</div><div class='del'>-				 &lt;&amp;adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK&gt;;</div><div class='del'>-			clock-names = "ipg", "baud";</div><div class='del'>-			power-domains = &lt;&amp;pd IMX_SC_R_UART_2&gt;;</div><div class='del'>-			status = "disabled";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		adma_lpuart3: serial@5a090000 {</div><div class='del'>-			compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";</div><div class='del'>-			reg = &lt;0x5a090000 0x1000&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;adma_lpcg IMX_ADMA_LPCG_UART3_IPG_CLK&gt;,</div><div class='del'>-				 &lt;&amp;adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK&gt;;</div><div class='del'>-			clock-names = "ipg", "baud";</div><div class='del'>-			power-domains = &lt;&amp;pd IMX_SC_R_UART_3&gt;;</div><div class='del'>-			status = "disabled";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		adma_i2c0: i2c@5a800000 {</div><div class='del'>-			compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='del'>-			reg = &lt;0x5a800000 0x4000&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;adma_lpcg IMX_ADMA_LPCG_I2C0_CLK&gt;;</div><div class='del'>-			clock-names = "per";</div><div class='del'>-			assigned-clocks = &lt;&amp;clk IMX_ADMA_I2C0_CLK&gt;;</div><div class='del'>-			assigned-clock-rates = &lt;24000000&gt;;</div><div class='del'>-			power-domains = &lt;&amp;pd IMX_SC_R_I2C_0&gt;;</div><div class='del'>-			status = "disabled";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		adma_i2c1: i2c@5a810000 {</div><div class='del'>-			compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='del'>-			reg = &lt;0x5a810000 0x4000&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;adma_lpcg IMX_ADMA_LPCG_I2C1_CLK&gt;;</div><div class='del'>-			clock-names = "per";</div><div class='del'>-			assigned-clocks = &lt;&amp;clk IMX_ADMA_I2C1_CLK&gt;;</div><div class='del'>-			assigned-clock-rates = &lt;24000000&gt;;</div><div class='del'>-			power-domains = &lt;&amp;pd IMX_SC_R_I2C_1&gt;;</div><div class='del'>-			status = "disabled";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		adma_i2c2: i2c@5a820000 {</div><div class='del'>-			compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='del'>-			reg = &lt;0x5a820000 0x4000&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;adma_lpcg IMX_ADMA_LPCG_I2C2_CLK&gt;;</div><div class='del'>-			clock-names = "per";</div><div class='del'>-			assigned-clocks = &lt;&amp;clk IMX_ADMA_I2C2_CLK&gt;;</div><div class='del'>-			assigned-clock-rates = &lt;24000000&gt;;</div><div class='del'>-			power-domains = &lt;&amp;pd IMX_SC_R_I2C_2&gt;;</div><div class='del'>-			status = "disabled";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		adma_i2c3: i2c@5a830000 {</div><div class='del'>-			compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='del'>-			reg = &lt;0x5a830000 0x4000&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;adma_lpcg IMX_ADMA_LPCG_I2C3_CLK&gt;;</div><div class='del'>-			clock-names = "per";</div><div class='del'>-			assigned-clocks = &lt;&amp;clk IMX_ADMA_I2C3_CLK&gt;;</div><div class='del'>-			assigned-clock-rates = &lt;24000000&gt;;</div><div class='del'>-			power-domains = &lt;&amp;pd IMX_SC_R_I2C_3&gt;;</div><div class='del'>-			status = "disabled";</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	conn_subsys: bus@5b000000 {</div><div class='del'>-		compatible = "simple-bus";</div><div class='del'>-		#address-cells = &lt;1&gt;;</div><div class='del'>-		#size-cells = &lt;1&gt;;</div><div class='del'>-		ranges = &lt;0x5b000000 0x0 0x5b000000 0x1000000&gt;;</div><div class='del'>-</div><div class='del'>-		conn_lpcg: clock-controller@5b200000 {</div><div class='del'>-			compatible = "fsl,imx8qxp-lpcg-conn";</div><div class='del'>-			reg = &lt;0x5b200000 0xb0000&gt;;</div><div class='del'>-			#clock-cells = &lt;1&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		usdhc1: mmc@5b010000 {</div><div class='del'>-			compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";</div><div class='del'>-			interrupts = &lt;GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			reg = &lt;0x5b010000 0x10000&gt;;</div><div class='del'>-			clocks = &lt;&amp;conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK&gt;,</div><div class='del'>-				 &lt;&amp;conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK&gt;,</div><div class='del'>-				 &lt;&amp;conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK&gt;;</div><div class='del'>-			clock-names = "ipg", "per", "ahb";</div><div class='del'>-			power-domains = &lt;&amp;pd IMX_SC_R_SDHC_0&gt;;</div><div class='del'>-			status = "disabled";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		usdhc2: mmc@5b020000 {</div><div class='del'>-			compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";</div><div class='del'>-			interrupts = &lt;GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			reg = &lt;0x5b020000 0x10000&gt;;</div><div class='del'>-			clocks = &lt;&amp;conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK&gt;,</div><div class='del'>-				 &lt;&amp;conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK&gt;,</div><div class='del'>-				 &lt;&amp;conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK&gt;;</div><div class='del'>-			clock-names = "ipg", "per", "ahb";</div><div class='del'>-			power-domains = &lt;&amp;pd IMX_SC_R_SDHC_1&gt;;</div><div class='del'>-			fsl,tuning-start-tap = &lt;20&gt;;</div><div class='del'>-			fsl,tuning-step= &lt;2&gt;;</div><div class='del'>-			status = "disabled";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		usdhc3: mmc@5b030000 {</div><div class='del'>-			compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";</div><div class='del'>-			interrupts = &lt;GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			reg = &lt;0x5b030000 0x10000&gt;;</div><div class='del'>-			clocks = &lt;&amp;conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK&gt;,</div><div class='del'>-				 &lt;&amp;conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK&gt;,</div><div class='del'>-				 &lt;&amp;conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK&gt;;</div><div class='del'>-			clock-names = "ipg", "per", "ahb";</div><div class='del'>-			power-domains = &lt;&amp;pd IMX_SC_R_SDHC_2&gt;;</div><div class='del'>-			status = "disabled";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		fec1: ethernet@5b040000 {</div><div class='del'>-			compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec";</div><div class='del'>-			reg = &lt;0x5b040000 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				     &lt;GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				     &lt;GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				     &lt;GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK&gt;,</div><div class='del'>-				 &lt;&amp;conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK&gt;,</div><div class='del'>-				 &lt;&amp;conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK&gt;,</div><div class='del'>-				 &lt;&amp;conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK&gt;;</div><div class='del'>-			clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";</div><div class='del'>-			fsl,num-tx-queues=&lt;3&gt;;</div><div class='del'>-			fsl,num-rx-queues=&lt;3&gt;;</div><div class='del'>-			power-domains = &lt;&amp;pd IMX_SC_R_ENET_0&gt;;</div><div class='del'>-			status = "disabled";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		fec2: ethernet@5b050000 {</div><div class='del'>-			compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec";</div><div class='del'>-			reg = &lt;0x5b050000 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-					&lt;GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-					&lt;GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-					&lt;GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK&gt;,</div><div class='del'>-				 &lt;&amp;conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK&gt;,</div><div class='del'>-				 &lt;&amp;conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK&gt;,</div><div class='del'>-				 &lt;&amp;conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK&gt;;</div><div class='del'>-			clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";</div><div class='del'>-			fsl,num-tx-queues=&lt;3&gt;;</div><div class='del'>-			fsl,num-rx-queues=&lt;3&gt;;</div><div class='del'>-			power-domains = &lt;&amp;pd IMX_SC_R_ENET_1&gt;;</div><div class='del'>-			status = "disabled";</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	ddr_subsyss: bus@5c000000 {</div><div class='del'>-		compatible = "simple-bus";</div><div class='del'>-		#address-cells = &lt;1&gt;;</div><div class='del'>-		#size-cells = &lt;1&gt;;</div><div class='del'>-		ranges = &lt;0x5c000000 0x0 0x5c000000 0x1000000&gt;;</div><div class='del'>-</div><div class='del'>-		ddr-pmu@5c020000 {</div><div class='del'>-			compatible = "fsl,imx8-ddr-pmu";</div><div class='del'>-			reg = &lt;0x5c020000 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	lsio_subsys: bus@5d000000 {</div><div class='del'>-		compatible = "simple-bus";</div><div class='del'>-		#address-cells = &lt;1&gt;;</div><div class='del'>-		#size-cells = &lt;1&gt;;</div><div class='del'>-		ranges = &lt;0x5d000000 0x0 0x5d000000 0x1000000&gt;;</div><div class='del'>-</div><div class='del'>-		lsio_gpio0: gpio@5d080000 {</div><div class='del'>-			compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";</div><div class='del'>-			reg = &lt;0x5d080000 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			gpio-controller;</div><div class='del'>-			#gpio-cells = &lt;2&gt;;</div><div class='del'>-			interrupt-controller;</div><div class='del'>-			#interrupt-cells = &lt;2&gt;;</div><div class='del'>-			power-domains = &lt;&amp;pd IMX_SC_R_GPIO_0&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		lsio_gpio1: gpio@5d090000 {</div><div class='del'>-			compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";</div><div class='del'>-			reg = &lt;0x5d090000 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			gpio-controller;</div><div class='del'>-			#gpio-cells = &lt;2&gt;;</div><div class='del'>-			interrupt-controller;</div><div class='del'>-			#interrupt-cells = &lt;2&gt;;</div><div class='del'>-			power-domains = &lt;&amp;pd IMX_SC_R_GPIO_1&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		lsio_gpio2: gpio@5d0a0000 {</div><div class='del'>-			compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";</div><div class='del'>-			reg = &lt;0x5d0a0000 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			gpio-controller;</div><div class='del'>-			#gpio-cells = &lt;2&gt;;</div><div class='del'>-			interrupt-controller;</div><div class='del'>-			#interrupt-cells = &lt;2&gt;;</div><div class='del'>-			power-domains = &lt;&amp;pd IMX_SC_R_GPIO_2&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		lsio_gpio3: gpio@5d0b0000 {</div><div class='del'>-			compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";</div><div class='del'>-			reg = &lt;0x5d0b0000 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			gpio-controller;</div><div class='del'>-			#gpio-cells = &lt;2&gt;;</div><div class='del'>-			interrupt-controller;</div><div class='del'>-			#interrupt-cells = &lt;2&gt;;</div><div class='del'>-			power-domains = &lt;&amp;pd IMX_SC_R_GPIO_3&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		lsio_gpio4: gpio@5d0c0000 {</div><div class='del'>-			compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";</div><div class='del'>-			reg = &lt;0x5d0c0000 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			gpio-controller;</div><div class='del'>-			#gpio-cells = &lt;2&gt;;</div><div class='del'>-			interrupt-controller;</div><div class='del'>-			#interrupt-cells = &lt;2&gt;;</div><div class='del'>-			power-domains = &lt;&amp;pd IMX_SC_R_GPIO_4&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		lsio_gpio5: gpio@5d0d0000 {</div><div class='del'>-			compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";</div><div class='del'>-			reg = &lt;0x5d0d0000 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			gpio-controller;</div><div class='del'>-			#gpio-cells = &lt;2&gt;;</div><div class='del'>-			interrupt-controller;</div><div class='del'>-			#interrupt-cells = &lt;2&gt;;</div><div class='del'>-			power-domains = &lt;&amp;pd IMX_SC_R_GPIO_5&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		lsio_gpio6: gpio@5d0e0000 {</div><div class='del'>-			compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";</div><div class='del'>-			reg = &lt;0x5d0e0000 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			gpio-controller;</div><div class='del'>-			#gpio-cells = &lt;2&gt;;</div><div class='del'>-			interrupt-controller;</div><div class='del'>-			#interrupt-cells = &lt;2&gt;;</div><div class='del'>-			power-domains = &lt;&amp;pd IMX_SC_R_GPIO_6&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		lsio_gpio7: gpio@5d0f0000 {</div><div class='del'>-			compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";</div><div class='del'>-			reg = &lt;0x5d0f0000 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			gpio-controller;</div><div class='del'>-			#gpio-cells = &lt;2&gt;;</div><div class='del'>-			interrupt-controller;</div><div class='del'>-			#interrupt-cells = &lt;2&gt;;</div><div class='del'>-			power-domains = &lt;&amp;pd IMX_SC_R_GPIO_7&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		lsio_mu0: mailbox@5d1b0000 {</div><div class='del'>-			compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";</div><div class='del'>-			reg = &lt;0x5d1b0000 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			#mbox-cells = &lt;2&gt;;</div><div class='del'>-			status = "disabled";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		lsio_mu1: mailbox@5d1c0000 {</div><div class='del'>-			compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";</div><div class='del'>-			reg = &lt;0x5d1c0000 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			#mbox-cells = &lt;2&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		lsio_mu2: mailbox@5d1d0000 {</div><div class='del'>-			compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";</div><div class='del'>-			reg = &lt;0x5d1d0000 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			#mbox-cells = &lt;2&gt;;</div><div class='del'>-			status = "disabled";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		lsio_mu3: mailbox@5d1e0000 {</div><div class='del'>-			compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";</div><div class='del'>-			reg = &lt;0x5d1e0000 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			#mbox-cells = &lt;2&gt;;</div><div class='del'>-			status = "disabled";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		lsio_mu4: mailbox@5d1f0000 {</div><div class='del'>-			compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";</div><div class='del'>-			reg = &lt;0x5d1f0000 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			#mbox-cells = &lt;2&gt;;</div><div class='del'>-			status = "disabled";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		lsio_mu13: mailbox@5d280000 {</div><div class='del'>-			compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";</div><div class='del'>-			reg = &lt;0x5d280000 0x10000&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			#mbox-cells = &lt;2&gt;;</div><div class='del'>-			power-domains = &lt;&amp;pd IMX_SC_R_MU_13A&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		lsio_lpcg: clock-controller@5d400000 {</div><div class='del'>-			compatible = "fsl,imx8qxp-lpcg-lsio";</div><div class='del'>-			reg = &lt;0x5d400000 0x400000&gt;;</div><div class='del'>-			#clock-cells = &lt;1&gt;;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='ctx'> 	thermal_zones: thermal-zones {</div><div class='del'>-		cpu-thermal0 {</div><div class='add'>+		cpu0-thermal {</div><div class='ctx'> 			polling-delay-passive = &lt;250&gt;;</div><div class='ctx'> 			polling-delay = &lt;2000&gt;;</div><div class='ctx'> 			thermal-sensors = &lt;&amp;tsens IMX_SC_R_SYSTEM&gt;;</div><div class='hunk'>@@ -625,4 +332,24 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	/* sorted in register address */</div><div class='add'>+	#include "imx8-ss-img.dtsi"</div><div class='add'>+	#include "imx8-ss-vpu.dtsi"</div><div class='add'>+	#include "imx8-ss-security.dtsi"</div><div class='add'>+	#include "imx8-ss-cm40.dtsi"</div><div class='add'>+	#include "imx8-ss-gpu0.dtsi"</div><div class='add'>+	#include "imx8-ss-adma.dtsi"</div><div class='add'>+	#include "imx8-ss-conn.dtsi"</div><div class='add'>+	#include "imx8-ss-ddr.dtsi"</div><div class='add'>+	#include "imx8-ss-lsio.dtsi"</div><div class='add'>+	#include "imx8-ss-hsio.dtsi"</div><div class='ctx'> };</div><div class='add'>+</div><div class='add'>+#include "imx8qxp-ss-img.dtsi"</div><div class='add'>+#include "imx8qxp-ss-vpu.dtsi"</div><div class='add'>+#include "imx8qxp-ss-security.dtsi"</div><div class='add'>+#include "imx8qxp-ss-adma.dtsi"</div><div class='add'>+#include "imx8qxp-ss-conn.dtsi"</div><div class='add'>+#include "imx8qxp-ss-lsio.dtsi"</div><div class='add'>+#include "imx8qxp-ss-hsio.dtsi"</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts<br/>new file mode 100644<br/>index 000000000000..5497e3d78136<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts</a></div><div class='hunk'>@@ -0,0 +1,69 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2025 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8ulp-evk.dts"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "NXP i.MX8ULP EVK9";</div><div class='add'>+	compatible = "fsl,imx8ulp-9x9-evk", "fsl,imx8ulp";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;btcpu {</div><div class='add'>+	sound-dai = &lt;&amp;sai6&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc1 {</div><div class='add'>+	pinctrl_sai6: sai6grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8ULP_PAD_PTE10__I2S6_TX_BCLK  0x43</div><div class='add'>+			MX8ULP_PAD_PTE11__I2S6_TX_FS    0x43</div><div class='add'>+			MX8ULP_PAD_PTE14__I2S6_TXD2     0x43</div><div class='add'>+			MX8ULP_PAD_PTE6__I2S6_RXD0      0x43</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_enet {</div><div class='add'>+	fsl,pins = &lt;</div><div class='add'>+		MX8ULP_PAD_PTF9__ENET0_MDC		0x43</div><div class='add'>+		MX8ULP_PAD_PTF8__ENET0_MDIO             0x43</div><div class='add'>+		MX8ULP_PAD_PTF5__ENET0_RXER             0x43</div><div class='add'>+		MX8ULP_PAD_PTF6__ENET0_CRS_DV           0x43</div><div class='add'>+		MX8ULP_PAD_PTF1__ENET0_RXD0             0x43</div><div class='add'>+		MX8ULP_PAD_PTF0__ENET0_RXD1             0x43</div><div class='add'>+		MX8ULP_PAD_PTF4__ENET0_TXEN             0x43</div><div class='add'>+		MX8ULP_PAD_PTF3__ENET0_TXD0             0x43</div><div class='add'>+		MX8ULP_PAD_PTF2__ENET0_TXD1             0x43</div><div class='add'>+		MX8ULP_PAD_PTF7__ENET0_REFCLK           0x43</div><div class='add'>+		MX8ULP_PAD_PTF10__ENET0_1588_CLKIN      0x43</div><div class='add'>+	&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_usb1 {</div><div class='add'>+	fsl,pins = &lt;</div><div class='add'>+		MX8ULP_PAD_PTE16__USB0_ID		0x10003</div><div class='add'>+		MX8ULP_PAD_PTE18__USB0_OC		0x10003</div><div class='add'>+	&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_usb2 {</div><div class='add'>+	fsl,pins = &lt;</div><div class='add'>+		MX8ULP_PAD_PTD23__USB1_ID		0x10003</div><div class='add'>+		MX8ULP_PAD_PTE20__USB1_OC		0x10003</div><div class='add'>+	&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai6 {</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai6&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_sai6&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1&gt;, &lt;&amp;cgc2 IMX8ULP_CLK_SAI6_SEL&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;0&gt;, &lt;&amp;cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;12288000&gt;;</div><div class='add'>+	fsl,dataline = &lt;1 0x01 0x04&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts<br/>new file mode 100644<br/>index 000000000000..290a49bea2f7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8ulp-evk.dts</a></div><div class='hunk'>@@ -0,0 +1,396 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx8ulp.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "NXP i.MX8ULP EVK";</div><div class='add'>+	compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp";</div><div class='add'>+</div><div class='add'>+	bt_sco_codec: bt-sco-codec {</div><div class='add'>+		#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+		compatible = "linux,bt-sco";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;lpuart5;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@80000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x80000000 0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		linux,cma {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reusable;</div><div class='add'>+			size = &lt;0 0x28000000&gt;;</div><div class='add'>+			linux,cma-default;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		m33_reserved: noncacheable-section@a8600000 {</div><div class='add'>+			reg = &lt;0 0xa8600000 0 0x1000000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rsc_table: rsc-table@1fff8000 {</div><div class='add'>+			reg = &lt;0 0x1fff8000 0 0x1000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev0vring0: vdev0vring0@aff00000 {</div><div class='add'>+			reg = &lt;0 0xaff00000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev0vring1: vdev0vring1@aff08000 {</div><div class='add'>+			reg = &lt;0 0xaff08000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev1vring0: vdev1vring0@aff10000 {</div><div class='add'>+			reg = &lt;0 0xaff10000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev1vring1: vdev1vring1@aff18000 {</div><div class='add'>+			reg = &lt;0 0xaff18000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdevbuffer: vdevbuffer@a8400000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0xa8400000 0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clock_ext_rmii: clock-ext-rmii {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		clock-frequency = &lt;50000000&gt;;</div><div class='add'>+		clock-output-names = "ext_rmii_clk";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clock_ext_ts: clock-ext-ts {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		/* External ts clock is 50MHZ from PHY on EVK board. */</div><div class='add'>+		clock-frequency = &lt;50000000&gt;;</div><div class='add'>+		clock-output-names = "ext_ts_clk";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-bt-sco {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,name = "bt-sco-audio";</div><div class='add'>+		simple-audio-card,format = "dsp_a";</div><div class='add'>+		simple-audio-card,bitclock-inversion;</div><div class='add'>+		simple-audio-card,frame-master = &lt;&amp;btcpu&gt;;</div><div class='add'>+		simple-audio-card,bitclock-master = &lt;&amp;btcpu&gt;;</div><div class='add'>+</div><div class='add'>+		btcpu: simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;sai5&gt;;</div><div class='add'>+			dai-tdm-slot-num = &lt;2&gt;;</div><div class='add'>+			dai-tdm-slot-width = &lt;16&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		simple-audio-card,codec {</div><div class='add'>+			sound-dai = &lt;&amp;bt_sco_codec 1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-spdif {</div><div class='add'>+		compatible = "fsl,imx-audio-spdif";</div><div class='add'>+		model = "imx-spdif";</div><div class='add'>+		audio-cpu = &lt;&amp;spdif&gt;;</div><div class='add'>+		audio-codec = &lt;&amp;spdif_out&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spdif_out: spdif-out {</div><div class='add'>+		compatible = "linux,spdif-dit";</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cm33 {</div><div class='add'>+	mbox-names = "tx", "rx", "rxdb";</div><div class='add'>+	mboxes = &lt;&amp;mu 0 1&gt;,</div><div class='add'>+		 &lt;&amp;mu 1 1&gt;,</div><div class='add'>+		 &lt;&amp;mu 3 1&gt;;</div><div class='add'>+	memory-region = &lt;&amp;vdevbuffer&gt;, &lt;&amp;vdev0vring0&gt;, &lt;&amp;vdev0vring1&gt;,</div><div class='add'>+			&lt;&amp;vdev1vring0&gt;, &lt;&amp;vdev1vring1&gt;, &lt;&amp;rsc_table&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexspi2 {</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexspi2_ptd&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_flexspi2_ptd&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mx25uw51345gxdi00: flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;200000000&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;8&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;8&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart5 {</div><div class='add'>+	/* console */</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpuart5&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_lpuart5&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c7 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c7&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_lpi2c7&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ptn5150_1: typec@1d {</div><div class='add'>+		compatible = "nxp,ptn5150";</div><div class='add'>+		reg = &lt;0x1d&gt;;</div><div class='add'>+		int-gpios = &lt;&amp;gpiof 3 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_typec1&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcal6408: gpio@21 {</div><div class='add'>+		compatible = "nxp,pcal9554b";</div><div class='add'>+		reg = &lt;0x21&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ptn5150_2: typec@3d {</div><div class='add'>+		compatible = "nxp,ptn5150";</div><div class='add'>+		reg = &lt;0x3d&gt;;</div><div class='add'>+		int-gpios = &lt;&amp;gpiof 5 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_typec2&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai5 {</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai5&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_sai5&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;cgc1 IMX8ULP_CLK_SAI5_SEL&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1&gt;;</div><div class='add'>+	fsl,dataline = &lt;1 0x08 0x01&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spdif {</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_spdif&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_spdif&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;cgc2 IMX8ULP_CLK_SPDIF_SEL&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usb1&gt;;</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	hnp-disable;</div><div class='add'>+	srp-disable;</div><div class='add'>+	adp-disable;</div><div class='add'>+	over-current-active-low;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbphy1 {</div><div class='add'>+	fsl,tx-d-cal = &lt;110&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbmisc1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usb2&gt;;</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	hnp-disable;</div><div class='add'>+	srp-disable;</div><div class='add'>+	adp-disable;</div><div class='add'>+	over-current-active-low;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbphy2 {</div><div class='add'>+	fsl,tx-d-cal = &lt;110&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbmisc2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc0 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc0&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc0&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc0&gt;;</div><div class='add'>+	pinctrl-3 = &lt;&amp;pinctrl_usdhc0&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec {</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_enet&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_enet&gt;;</div><div class='add'>+	clocks = &lt;&amp;cgc1 IMX8ULP_CLK_XBAR_DIVBUS&gt;,</div><div class='add'>+		 &lt;&amp;pcc4 IMX8ULP_CLK_ENET&gt;,</div><div class='add'>+		 &lt;&amp;cgc1 IMX8ULP_CLK_ENET_TS_SEL&gt;,</div><div class='add'>+		 &lt;&amp;clock_ext_rmii&gt;;</div><div class='add'>+	clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";</div><div class='add'>+	assigned-clocks = &lt;&amp;cgc1 IMX8ULP_CLK_ENET_TS_SEL&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clock_ext_ts&gt;;</div><div class='add'>+	phy-mode = "rmii";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy: ethernet-phy@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			micrel,led-mode = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mu {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc1 {</div><div class='add'>+	pinctrl_enet: enetgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8ULP_PAD_PTE15__ENET0_MDC     0x43</div><div class='add'>+			MX8ULP_PAD_PTE14__ENET0_MDIO    0x43</div><div class='add'>+			MX8ULP_PAD_PTE17__ENET0_RXER    0x43</div><div class='add'>+			MX8ULP_PAD_PTE18__ENET0_CRS_DV  0x43</div><div class='add'>+			MX8ULP_PAD_PTF1__ENET0_RXD0     0x43</div><div class='add'>+			MX8ULP_PAD_PTE20__ENET0_RXD1    0x43</div><div class='add'>+			MX8ULP_PAD_PTE16__ENET0_TXEN    0x43</div><div class='add'>+			MX8ULP_PAD_PTE23__ENET0_TXD0    0x43</div><div class='add'>+			MX8ULP_PAD_PTE22__ENET0_TXD1    0x43</div><div class='add'>+			MX8ULP_PAD_PTE19__ENET0_REFCLK  0x43</div><div class='add'>+			MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexspi2_ptd: flexspi2ptdgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+</div><div class='add'>+			MX8ULP_PAD_PTD12__FLEXSPI2_A_SS0_B	0x42</div><div class='add'>+			MX8ULP_PAD_PTD13__FLEXSPI2_A_SCLK	0x42</div><div class='add'>+			MX8ULP_PAD_PTD14__FLEXSPI2_A_DATA3	0x42</div><div class='add'>+			MX8ULP_PAD_PTD15__FLEXSPI2_A_DATA2	0x42</div><div class='add'>+			MX8ULP_PAD_PTD16__FLEXSPI2_A_DATA1	0x42</div><div class='add'>+			MX8ULP_PAD_PTD17__FLEXSPI2_A_DATA0	0x42</div><div class='add'>+			MX8ULP_PAD_PTD18__FLEXSPI2_A_DQS	0x42</div><div class='add'>+			MX8ULP_PAD_PTD19__FLEXSPI2_A_DATA7	0x42</div><div class='add'>+			MX8ULP_PAD_PTD20__FLEXSPI2_A_DATA6	0x42</div><div class='add'>+			MX8ULP_PAD_PTD21__FLEXSPI2_A_DATA5	0x42</div><div class='add'>+			MX8ULP_PAD_PTD22__FLEXSPI2_A_DATA4	0x42</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpuart5: lpuart5grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8ULP_PAD_PTF14__LPUART5_TX	0x3</div><div class='add'>+			MX8ULP_PAD_PTF15__LPUART5_RX	0x3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c7: lpi2c7grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8ULP_PAD_PTE12__LPI2C7_SCL	0x20</div><div class='add'>+			MX8ULP_PAD_PTE13__LPI2C7_SDA	0x20</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai5: sai5grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8ULP_PAD_PTF26__I2S5_TX_BCLK	0x43</div><div class='add'>+			MX8ULP_PAD_PTF27__I2S5_TX_FS	0x43</div><div class='add'>+			MX8ULP_PAD_PTF28__I2S5_TXD0	0x43</div><div class='add'>+			MX8ULP_PAD_PTF24__I2S5_RXD3	0x43</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_spdif: spdifgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8ULP_PAD_PTF25__SPDIF_OUT1    0x43</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_typec1: typec1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8ULP_PAD_PTF3__PTF3           0x3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_typec2: typec2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8ULP_PAD_PTF5__PTF5           0x3</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usb1: usb1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8ULP_PAD_PTF2__USB0_ID	0x10003</div><div class='add'>+			MX8ULP_PAD_PTF4__USB0_OC	0x10003</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usb2: usb2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8ULP_PAD_PTD23__USB1_ID	0x10003</div><div class='add'>+			MX8ULP_PAD_PTF6__USB1_OC	0x10003</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc0: usdhc0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX8ULP_PAD_PTD1__SDHC0_CMD	0x3</div><div class='add'>+			MX8ULP_PAD_PTD2__SDHC0_CLK	0x10002</div><div class='add'>+			MX8ULP_PAD_PTD10__SDHC0_D0	0x3</div><div class='add'>+			MX8ULP_PAD_PTD9__SDHC0_D1	0x3</div><div class='add'>+			MX8ULP_PAD_PTD8__SDHC0_D2	0x3</div><div class='add'>+			MX8ULP_PAD_PTD7__SDHC0_D3	0x3</div><div class='add'>+			MX8ULP_PAD_PTD6__SDHC0_D4	0x3</div><div class='add'>+			MX8ULP_PAD_PTD5__SDHC0_D5	0x3</div><div class='add'>+			MX8ULP_PAD_PTD4__SDHC0_D6	0x3</div><div class='add'>+			MX8ULP_PAD_PTD3__SDHC0_D7	0x3</div><div class='add'>+			MX8ULP_PAD_PTD11__SDHC0_DQS	0x10002</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h b/arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h<br/>new file mode 100644<br/>index 000000000000..b204ac79b449<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h</a></div><div class='hunk'>@@ -0,0 +1,978 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0+ OR MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __DTS_IMX8ULP_PINFUNC_H</div><div class='add'>+#define __DTS_IMX8ULP_PINFUNC_H</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * The pin function ID is a tuple of</div><div class='add'>+ * &lt;mux_reg input_reg mux_mode input_val&gt;</div><div class='add'>+ */</div><div class='add'>+#define MX8ULP_PAD_PTD0__PTD0                                        0x0000 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD0__I2S6_RX_BCLK                                0x0000 0x0B44 0x7 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD0__SDHC0_RESET_B                               0x0000 0x0000 0x8 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS                              0x0000 0x0974 0x9 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD0__CLKOUT2                                     0x0000 0x0000 0xa 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B                               0x0000 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0                            0x0000 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD0__CLKOUT1                                     0x0000 0x0000 0xd 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD0__DEBUG_MUX0_0                                0x0000 0x0000 0xe 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD0__DEBUG_MUX1_0                                0x0000 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD1__PTD1                                        0x0004 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD1__I2S6_RX_FS                                  0x0004 0x0B48 0x7 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD1__SDHC0_CMD                                   0x0004 0x0000 0x8 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD1__FLEXSPI2_B_DATA7                            0x0004 0x0970 0x9 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD1__EPDC0_SDCLK                                 0x0004 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD1__DPI0_PCLK                                   0x0004 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD1__LP_APD_DBG_MUX_1                            0x0004 0x0000 0xd 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD1__DEBUG_MUX0_1                                0x0004 0x0000 0xe 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD1__DEBUG_MUX1_1                                0x0004 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD2__PTD2                                        0x0008 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD2__I2S6_RXD0                                   0x0008 0x0B34 0x7 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD2__SDHC0_CLK                                   0x0008 0x0000 0x8 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD2__FLEXSPI2_B_DATA6                            0x0008 0x096C 0x9 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD2__EPDC0_SDLE                                  0x0008 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD2__DPI0_HSYNC                                  0x0008 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD2__LP_APD_DBG_MUX_2                            0x0008 0x0000 0xd 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD2__DEBUG_MUX0_2                                0x0008 0x0000 0xe 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD2__DEBUG_MUX1_2                                0x0008 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD3__PTD3                                        0x000C 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD3__I2S6_RXD1                                   0x000C 0x0B38 0x7 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD3__SDHC0_D7                                    0x000C 0x0000 0x8 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD3__FLEXSPI2_B_DATA5                            0x000C 0x0968 0x9 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD3__EPDC0_GDSP                                  0x000C 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD3__DPI0_VSYNC                                  0x000C 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD3__LP_APD_DBG_MUX_3                            0x000C 0x0000 0xd 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD3__DEBUG_MUX0_3                                0x000C 0x0000 0xe 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD3__DEBUG_MUX1_3                                0x000C 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD4__PTD4                                        0x0010 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD4__EXT_AUD_MCLK3                               0x0010 0x0B14 0x4 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD4__SDHC0_VS                                    0x0010 0x0000 0x5 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD4__TPM8_CH5                                    0x0010 0x0B2C 0x6 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD4__I2S6_MCLK                                   0x0010 0x0000 0x7 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD4__SDHC0_D6                                    0x0010 0x0000 0x8 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD4__FLEXSPI2_B_DATA4                            0x0010 0x0964 0x9 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD4__EPDC0_SDCE0                                 0x0010 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD4__DPI0_DE                                     0x0010 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD4__LP_APD_DBG_MUX_4                            0x0010 0x0000 0xd 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD4__DEBUG_MUX0_4                                0x0010 0x0000 0xe 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD4__DEBUG_MUX1_4                                0x0010 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD5__PTD5                                        0x0014 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD5__SDHC0_CD                                    0x0014 0x0000 0x5 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD5__TPM8_CH4                                    0x0014 0x0B28 0x6 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD5__I2S6_TX_BCLK                                0x0014 0x0B4C 0x7 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD5__SDHC0_D5                                    0x0014 0x0000 0x8 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD5__FLEXSPI2_B_SS0_B                            0x0014 0x0000 0x9 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD5__FLEXSPI2_B_SCLK_B                           0x0014 0x0000 0xa 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD5__EPDC0_D0                                    0x0014 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD5__DPI0_D0                                     0x0014 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD5__LP_APD_DBG_MUX_5                            0x0014 0x0000 0xd 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD5__DEBUG_MUX0_5                                0x0014 0x0000 0xe 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD5__DEBUG_MUX1_5                                0x0014 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD6__PTD6                                        0x0018 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD6__SDHC0_WP                                    0x0018 0x0000 0x5 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD6__TPM8_CH3                                    0x0018 0x0B24 0x6 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD6__I2S6_TX_FS                                  0x0018 0x0B50 0x7 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD6__SDHC0_D4                                    0x0018 0x0000 0x8 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD6__FLEXSPI2_B_SCLK                             0x0018 0x0978 0x9 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD6__EPDC0_D1                                    0x0018 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD6__DPI0_D1                                     0x0018 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD6__LP_APD_DBG_MUX_6                            0x0018 0x0000 0xd 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD6__DEBUG_MUX0_6                                0x0018 0x0000 0xe 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD6__DEBUG_MUX1_6                                0x0018 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD7__PTD7                                        0x001C 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD7__TPM8_CH2                                    0x001C 0x0B20 0x6 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD7__I2S6_TXD0                                   0x001C 0x0000 0x7 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD7__SDHC0_D3                                    0x001C 0x0000 0x8 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD7__FLEXSPI2_B_DATA3                            0x001C 0x0960 0x9 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD7__EPDC0_D2                                    0x001C 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD7__DPI0_D2                                     0x001C 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD7__LP_APD_DBG_MUX_7                            0x001C 0x0000 0xd 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD7__DEBUG_MUX0_7                                0x001C 0x0000 0xe 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD7__DEBUG_MUX1_7                                0x001C 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD8__PTD8                                        0x0020 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD8__TPM8_CH1                                    0x0020 0x0B1C 0x6 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD8__I2S6_TXD1                                   0x0020 0x0000 0x7 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD8__SDHC0_D2                                    0x0020 0x0000 0x8 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD8__FLEXSPI2_B_DATA2                            0x0020 0x095C 0x9 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD8__EPDC0_D3                                    0x0020 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD8__DPI0_D3                                     0x0020 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD8__LP_APD_DBG_MUX_8                            0x0020 0x0000 0xe 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD8__DEBUG_MUX1_8                                0x0020 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD9__PTD9                                        0x0024 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD9__TPM8_CLKIN                                  0x0024 0x0B30 0x6 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD9__I2S6_TXD2                                   0x0024 0x0000 0x7 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD9__SDHC0_D1                                    0x0024 0x0000 0x8 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD9__FLEXSPI2_B_DATA1                            0x0024 0x0958 0x9 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD9__EPDC0_D4                                    0x0024 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD9__DPI0_D4                                     0x0024 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD9__LP_APD_DBG_MUX_9                            0x0024 0x0000 0xe 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD9__DEBUG_MUX1_9                                0x0024 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD10__PTD10                                      0x0028 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD10__TPM8_CH0                                   0x0028 0x0B18 0x6 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD10__I2S6_TXD3                                  0x0028 0x0000 0x7 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD10__SDHC0_D0                                   0x0028 0x0000 0x8 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD10__FLEXSPI2_B_DATA0                           0x0028 0x0954 0x9 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD10__EPDC0_D5                                   0x0028 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD10__DPI0_D5                                    0x0028 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD10__LP_APD_DBG_MUX_10                          0x0028 0x0000 0xe 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD10__DEBUG_MUX1_10                              0x0028 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD11__PTD11                                      0x002C 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD11__TPM8_CH5                                   0x002C 0x0B2C 0x6 0x2</div><div class='add'>+#define MX8ULP_PAD_PTD11__I2S6_RXD2                                  0x002C 0x0B3C 0x7 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD11__SDHC0_DQS                                  0x002C 0x0000 0x8 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD11__FLEXSPI2_B_SS0_B                           0x002C 0x0000 0x9 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD11__FLEXSPI2_A_SS1_B                           0x002C 0x0000 0xa 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD11__EPDC0_D6                                   0x002C 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD11__DPI0_D6                                    0x002C 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD11__LP_APD_DBG_MUX_11                          0x002C 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD12__PTD12                                      0x0030 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD12__USB0_ID                                    0x0030 0x0AC8 0x5 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD12__SDHC2_D3                                   0x0030 0x0AA4 0x6 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD12__I2S7_RX_BCLK                               0x0030 0x0B64 0x7 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD12__SDHC1_DQS                                  0x0030 0x0A84 0x8 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD12__FLEXSPI2_A_SS0_B                           0x0030 0x0000 0x9 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD12__FLEXSPI2_B_SS1_B                           0x0030 0x0000 0xa 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD12__EPDC0_D7                                   0x0030 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD12__DPI0_D7                                    0x0030 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD12__LP_APD_DBG_MUX_12                          0x0030 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD13__PTD13                                      0x0034 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD13__SPDIF_IN3                                  0x0034 0x0B80 0x4 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD13__USB0_PWR                                   0x0034 0x0000 0x5 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD13__SDHC2_D2                                   0x0034 0x0AA0 0x6 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD13__I2S7_RX_FS                                 0x0034 0x0B68 0x7 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD13__SDHC1_RESET_B                              0x0034 0x0000 0x8 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD13__FLEXSPI2_A_SCLK                            0x0034 0x0000 0x9 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD13__CLKOUT2                                    0x0034 0x0000 0xa 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD13__EPDC0_D8                                   0x0034 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD13__DPI0_D8                                    0x0034 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD13__CLKOUT1                                    0x0034 0x0000 0xd 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD13__LP_APD_DBG_MUX_13                          0x0034 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD14__PTD14                                      0x0038 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD14__SPDIF_OUT3                                 0x0038 0x0000 0x4 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD14__USB0_OC                                    0x0038 0x0AC0 0x5 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD14__SDHC2_D1                                   0x0038 0x0A9C 0x6 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD14__I2S7_RXD0                                  0x0038 0x0B54 0x7 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD14__SDHC1_D7                                   0x0038 0x0A80 0x8 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD14__FLEXSPI2_A_DATA3                           0x0038 0x0000 0x9 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD14__TRACE0_D7                                  0x0038 0x0000 0xa 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD14__EPDC0_D9                                   0x0038 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD14__DPI0_D9                                    0x0038 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD14__LP_APD_DBG_MUX_14                          0x0038 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD15__PTD15                                      0x003C 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD15__SPDIF_IN2                                  0x003C 0x0B7C 0x4 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD15__SDHC1_VS                                   0x003C 0x0000 0x5 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD15__SDHC2_D0                                   0x003C 0x0A98 0x6 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD15__I2S7_TX_BCLK                               0x003C 0x0B6C 0x7 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD15__SDHC1_D6                                   0x003C 0x0A7C 0x8 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD15__FLEXSPI2_A_DATA2                           0x003C 0x0000 0x9 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD15__TRACE0_D6                                  0x003C 0x0000 0xa 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD15__EPDC0_D10                                  0x003C 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD15__DPI0_D10                                   0x003C 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD15__LP_APD_DBG_MUX_15                          0x003C 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD16__PTD16                                      0x0040 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD16__FXIO1_D31                                  0x0040 0x08A0 0x2 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD16__LPSPI4_PCS1                                0x0040 0x08F8 0x3 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD16__SPDIF_OUT2                                 0x0040 0x0000 0x4 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD16__SDHC1_CD                                   0x0040 0x0A58 0x5 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD16__SDHC2_CLK                                  0x0040 0x0A90 0x6 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD16__I2S7_TX_FS                                 0x0040 0x0B70 0x7 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD16__SDHC1_D5                                   0x0040 0x0A78 0x8 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD16__FLEXSPI2_A_DATA1                           0x0040 0x0000 0x9 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD16__TRACE0_D5                                  0x0040 0x0000 0xa 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD16__EPDC0_D11                                  0x0040 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD16__DPI0_D11                                   0x0040 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD16__LP_APD_DBG_MUX_16                          0x0040 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD17__PTD17                                      0x0044 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD17__FXIO1_D30                                  0x0044 0x089C 0x2 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD17__LPSPI4_PCS2                                0x0044 0x08FC 0x3 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD17__EXT_AUD_MCLK3                              0x0044 0x0B14 0x4 0x2</div><div class='add'>+#define MX8ULP_PAD_PTD17__SDHC1_WP                                   0x0044 0x0A88 0x5 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD17__SDHC2_CMD                                  0x0044 0x0A94 0x6 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD17__I2S7_TXD0                                  0x0044 0x0000 0x7 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD17__SDHC1_D4                                   0x0044 0x0A74 0x8 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD17__FLEXSPI2_A_DATA0                           0x0044 0x0000 0x9 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD17__TRACE0_D4                                  0x0044 0x0000 0xa 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD17__EPDC0_D12                                  0x0044 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD17__DPI0_D12                                   0x0044 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD17__LP_APD_DBG_MUX_17                          0x0044 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD18__PTD18                                      0x0048 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD18__FXIO1_D29                                  0x0048 0x0894 0x2 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD18__LPSPI4_PCS3                                0x0048 0x0900 0x3 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD18__SPDIF_CLK                                  0x0048 0x0000 0x4 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD18__EXT_AUD_MCLK3                              0x0048 0x0B14 0x5 0x3</div><div class='add'>+#define MX8ULP_PAD_PTD18__TPM8_CH0                                   0x0048 0x0B18 0x6 0x2</div><div class='add'>+#define MX8ULP_PAD_PTD18__I2S7_MCLK                                  0x0048 0x0000 0x7 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD18__SDHC1_D3                                   0x0048 0x0A70 0x8 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD18__FLEXSPI2_A_DQS                             0x0048 0x0000 0x9 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD18__TRACE0_D3                                  0x0048 0x0000 0xa 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD18__EPDC0_D13                                  0x0048 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD18__DPI0_D13                                   0x0048 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD18__LP_APD_DBG_MUX_18                          0x0048 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD19__PTD19                                      0x004C 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD19__FXIO1_D28                                  0x004C 0x0890 0x2 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD19__SPDIF_IN0                                  0x004C 0x0B74 0x4 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD19__TPM8_CH1                                   0x004C 0x0B1C 0x6 0x2</div><div class='add'>+#define MX8ULP_PAD_PTD19__I2S6_RXD3                                  0x004C 0x0B40 0x7 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD19__SDHC1_D2                                   0x004C 0x0A6C 0x8 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD19__FLEXSPI2_A_DATA7                           0x004C 0x0000 0x9 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD19__TRACE0_D2                                  0x004C 0x0000 0xa 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD19__EPDC0_D14                                  0x004C 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD19__DPI0_D14                                   0x004C 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD19__LP_APD_DBG_MUX_19                          0x004C 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD20__PTD20                                      0x0050 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD20__FXIO1_D27                                  0x0050 0x088C 0x2 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD20__LPSPI4_SIN                                 0x0050 0x0908 0x3 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD20__SPDIF_OUT0                                 0x0050 0x0000 0x4 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD20__TPM8_CLKIN                                 0x0050 0x0B30 0x6 0x2</div><div class='add'>+#define MX8ULP_PAD_PTD20__I2S7_RXD1                                  0x0050 0x0B58 0x7 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD20__SDHC1_D1                                   0x0050 0x0A68 0x8 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD20__FLEXSPI2_A_DATA6                           0x0050 0x0000 0x9 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD20__TRACE0_D1                                  0x0050 0x0000 0xa 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD20__EPDC0_D15                                  0x0050 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD20__DPI0_D15                                   0x0050 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD20__LP_APD_DBG_MUX_20                          0x0050 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD21__PTD21                                      0x0054 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD21__FXIO1_D26                                  0x0054 0x0888 0x2 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD21__LPSPI4_SOUT                                0x0054 0x090C 0x3 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD21__SPDIF_IN1                                  0x0054 0x0B78 0x4 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD21__USB1_PWR                                   0x0054 0x0000 0x5 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD21__TPM8_CH2                                   0x0054 0x0B20 0x6 0x2</div><div class='add'>+#define MX8ULP_PAD_PTD21__I2S7_TXD1                                  0x0054 0x0000 0x7 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD21__SDHC1_D0                                   0x0054 0x0A64 0x8 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD21__FLEXSPI2_A_DATA5                           0x0054 0x0000 0x9 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD21__TRACE0_D0                                  0x0054 0x0000 0xa 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD21__DPI0_D16                                   0x0054 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD21__WDOG5_RST                                  0x0054 0x0000 0xd 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD21__LP_APD_DBG_MUX_21                          0x0054 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD22__PTD22                                      0x0058 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD22__FXIO1_D25                                  0x0058 0x0884 0x2 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD22__LPSPI4_SCK                                 0x0058 0x0904 0x3 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD22__SPDIF_OUT1                                 0x0058 0x0000 0x4 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD22__USB1_OC                                    0x0058 0x0AC4 0x5 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD22__TPM8_CH3                                   0x0058 0x0B24 0x6 0x2</div><div class='add'>+#define MX8ULP_PAD_PTD22__I2S7_TXD2                                  0x0058 0x0000 0x7 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD22__SDHC1_CLK                                  0x0058 0x0A5C 0x8 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD22__FLEXSPI2_A_DATA4                           0x0058 0x0000 0x9 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD22__TRACE0_CLKOUT                              0x0058 0x0000 0xa 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD22__DPI0_D17                                   0x0058 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD22__LP_APD_DBG_MUX_22                          0x0058 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD23__PTD23                                      0x005C 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD23__FXIO1_D24                                  0x005C 0x0880 0x2 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD23__LPSPI4_PCS0                                0x005C 0x08F4 0x3 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD23__USB1_ID                                    0x005C 0x0ACC 0x5 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD23__TPM8_CH4                                   0x005C 0x0B28 0x6 0x2</div><div class='add'>+#define MX8ULP_PAD_PTD23__I2S7_TXD3                                  0x005C 0x0000 0x7 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD23__SDHC1_CMD                                  0x005C 0x0A60 0x8 0x1</div><div class='add'>+#define MX8ULP_PAD_PTD23__FLEXSPI2_A_SS0_B                           0x005C 0x0000 0x9 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD23__FLEXSPI2_A_SCLK_B                          0x005C 0x0000 0xa 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD23__DPI0_D18                                   0x005C 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTD23__LP_APD_DBG_MUX_23                          0x005C 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE0__PTE0                                        0x0080 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE0__FXIO1_D23                                   0x0080 0x087C 0x2 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE0__SPDIF_IN3                                   0x0080 0x0B80 0x3 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE0__LPUART4_CTS_B                               0x0080 0x08DC 0x4 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE0__LPI2C4_SCL                                  0x0080 0x08C8 0x5 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE0__TPM8_CLKIN                                  0x0080 0x0B30 0x6 0x3</div><div class='add'>+#define MX8ULP_PAD_PTE0__I2S7_RXD2                                   0x0080 0x0B5C 0x7 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE0__SDHC2_D1                                    0x0080 0x0A9C 0x8 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE0__FLEXSPI2_B_DQS                              0x0080 0x0974 0x9 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE0__ENET0_CRS                                   0x0080 0x0AE8 0xa 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE0__DBI0_WRX                                    0x0080 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE0__DPI0_D19                                    0x0080 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE0__WUU1_P0                                     0x0080 0x0000 0xd 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE0__DEBUG_MUX0_8                                0x0080 0x0000 0xe 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE0__DEBUG_MUX1_11                               0x0080 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE1__PTE1                                        0x0084 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE1__FXIO1_D22                                   0x0084 0x0878 0x2 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE1__SPDIF_OUT3                                  0x0084 0x0000 0x3 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE1__LPUART4_RTS_B                               0x0084 0x0000 0x4 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE1__LPI2C4_SDA                                  0x0084 0x08CC 0x5 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE1__TPM8_CH0                                    0x0084 0x0B18 0x6 0x3</div><div class='add'>+#define MX8ULP_PAD_PTE1__I2S7_RXD3                                   0x0084 0x0B60 0x7 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE1__SDHC2_D0                                    0x0084 0x0A98 0x8 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE1__FLEXSPI2_B_DATA7                            0x0084 0x0970 0x9 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE1__ENET0_COL                                   0x0084 0x0AE4 0xa 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE1__DBI0_CSX                                    0x0084 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE1__DPI0_D20                                    0x0084 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE1__WUU1_P1                                     0x0084 0x0000 0xd 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE1__DEBUG_MUX0_9                                0x0084 0x0000 0xe 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE1__DEBUG_MUX1_12                               0x0084 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE2__PTE2                                        0x0088 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE2__FXIO1_D21                                   0x0088 0x0874 0x2 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE2__SPDIF_IN2                                   0x0088 0x0B7C 0x3 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE2__LPUART4_TX                                  0x0088 0x08E4 0x4 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE2__LPI2C4_HREQ                                 0x0088 0x08C4 0x5 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE2__TPM8_CH1                                    0x0088 0x0B1C 0x6 0x3</div><div class='add'>+#define MX8ULP_PAD_PTE2__EXT_AUD_MCLK3                               0x0088 0x0B14 0x7 0x4</div><div class='add'>+#define MX8ULP_PAD_PTE2__SDHC2_CLK                                   0x0088 0x0A90 0x8 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE2__FLEXSPI2_B_DATA6                            0x0088 0x096C 0x9 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE2__ENET0_TXER                                  0x0088 0x0000 0xa 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE2__DBI0_DCX                                    0x0088 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE2__DPI0_D21                                    0x0088 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE2__LP_HV_DBG_MUX_0                             0x0088 0x0000 0xd 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE2__DEBUG_MUX0_10                               0x0088 0x0000 0xe 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE2__DEBUG_MUX1_13                               0x0088 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE3__PTE3                                        0x008C 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE3__FXIO1_D20                                   0x008C 0x0870 0x2 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE3__SPDIF_OUT2                                  0x008C 0x0000 0x3 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE3__LPUART4_RX                                  0x008C 0x08E0 0x4 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE3__TPM8_CH2                                    0x008C 0x0B20 0x6 0x3</div><div class='add'>+#define MX8ULP_PAD_PTE3__I2S6_MCLK                                   0x008C 0x0000 0x7 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE3__SDHC2_CMD                                   0x008C 0x0A94 0x8 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE3__FLEXSPI2_B_DATA5                            0x008C 0x0968 0x9 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE3__ENET0_TXCLK                                 0x008C 0x0B10 0xa 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE3__DBI0_RWX                                    0x008C 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE3__DPI0_D22                                    0x008C 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE3__WUU1_P2                                     0x008C 0x0000 0xd 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE3__DEBUG_MUX0_11                               0x008C 0x0000 0xe 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE3__DEBUG_MUX1_14                               0x008C 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE4__PTE4                                        0x0090 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE4__FXIO1_D19                                   0x0090 0x0868 0x2 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE4__SPDIF_CLK                                   0x0090 0x0000 0x3 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE4__LPUART5_CTS_B                               0x0090 0x08E8 0x4 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE4__LPI2C5_SCL                                  0x0090 0x08D4 0x5 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE4__TPM8_CH3                                    0x0090 0x0B24 0x6 0x3</div><div class='add'>+#define MX8ULP_PAD_PTE4__I2S6_RX_BCLK                                0x0090 0x0B44 0x7 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE4__SDHC2_D3                                    0x0090 0x0AA4 0x8 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE4__FLEXSPI2_B_DATA4                            0x0090 0x0964 0x9 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE4__ENET0_TXD3                                  0x0090 0x0000 0xa 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE4__DBI0_E                                      0x0090 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE4__DPI0_D23                                    0x0090 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE4__WUU1_P3                                     0x0090 0x0000 0xd 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE4__DEBUG_MUX0_12                               0x0090 0x0000 0xe 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE4__DEBUG_MUX1_15                               0x0090 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE5__PTE5                                        0x0094 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE5__FXIO1_D18                                   0x0094 0x0864 0x2 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE5__SPDIF_IN0                                   0x0094 0x0B74 0x3 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE5__LPUART5_RTS_B                               0x0094 0x0000 0x4 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE5__LPI2C5_SDA                                  0x0094 0x08D8 0x5 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE5__TPM8_CH4                                    0x0094 0x0B28 0x6 0x3</div><div class='add'>+#define MX8ULP_PAD_PTE5__I2S6_RX_FS                                  0x0094 0x0B48 0x7 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE5__SDHC2_D2                                    0x0094 0x0AA0 0x8 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE5__FLEXSPI2_B_SS0_B                            0x0094 0x0000 0x9 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE5__ENET0_TXD2                                  0x0094 0x0000 0xa 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE5__DBI0_D0                                     0x0094 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE5__LP_HV_DBG_MUX_1                             0x0094 0x0000 0xd 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE5__DEBUG_MUX0_13                               0x0094 0x0000 0xe 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE5__DEBUG_MUX1_16                               0x0094 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE6__PTE6                                        0x0098 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE6__FXIO1_D17                                   0x0098 0x0860 0x2 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE6__SPDIF_OUT0                                  0x0098 0x0000 0x3 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE6__LPUART5_TX                                  0x0098 0x08F0 0x4 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE6__LPI2C5_HREQ                                 0x0098 0x08D0 0x5 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE6__TPM8_CH5                                    0x0098 0x0B2C 0x6 0x3</div><div class='add'>+#define MX8ULP_PAD_PTE6__I2S6_RXD0                                   0x0098 0x0B34 0x7 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE6__SDHC2_D4                                    0x0098 0x0AA8 0x8 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE6__FLEXSPI2_B_SCLK                             0x0098 0x0978 0x9 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE6__ENET0_RXCLK                                 0x0098 0x0B0C 0xa 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE6__DBI0_D1                                     0x0098 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE6__LP_HV_DBG_MUX_2                             0x0098 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE6__WDOG5_RST                                   0x0098 0x0000 0xd 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE6__DEBUG_MUX0_14                               0x0098 0x0000 0xe 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE6__DEBUG_MUX1_17                               0x0098 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE7__PTE7                                        0x009C 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE7__FXIO1_D16                                   0x009C 0x085C 0x2 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE7__SPDIF_IN1                                   0x009C 0x0B78 0x3 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE7__LPUART5_RX                                  0x009C 0x08EC 0x4 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE7__LPI2C6_HREQ                                 0x009C 0x09B4 0x5 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE7__TPM4_CLKIN                                  0x009C 0x081C 0x6 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE7__I2S6_RXD1                                   0x009C 0x0B38 0x7 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE7__SDHC2_D5                                    0x009C 0x0AAC 0x8 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE7__FLEXSPI2_B_DATA3                            0x009C 0x0960 0x9 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE7__ENET0_RXD3                                  0x009C 0x0B04 0xa 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE7__DBI0_D2                                     0x009C 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE7__EPDC0_BDR1                                  0x009C 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE7__WUU1_P4                                     0x009C 0x0000 0xd 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE7__DEBUG_MUX0_15                               0x009C 0x0000 0xe 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE7__DEBUG_MUX1_18                               0x009C 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE8__PTE8                                        0x00A0 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE8__FXIO1_D15                                   0x00A0 0x0858 0x2 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE8__LPSPI4_PCS1                                 0x00A0 0x08F8 0x3 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE8__LPUART6_CTS_B                               0x00A0 0x09CC 0x4 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE8__LPI2C6_SCL                                  0x00A0 0x09B8 0x5 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE8__TPM4_CH0                                    0x00A0 0x0804 0x6 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE8__I2S6_RXD2                                   0x00A0 0x0B3C 0x7 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE8__SDHC2_D6                                    0x00A0 0x0AB0 0x8 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE8__FLEXSPI2_B_DATA2                            0x00A0 0x095C 0x9 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE8__ENET0_RXD2                                  0x00A0 0x0B00 0xa 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE8__DBI0_D3                                     0x00A0 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE8__EPDC0_BDR0                                  0x00A0 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE8__LP_HV_DBG_MUX_3                             0x00A0 0x0000 0xe 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE8__DEBUG_MUX1_19                               0x00A0 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE9__PTE9                                        0x00A4 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE9__FXIO1_D14                                   0x00A4 0x0854 0x2 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE9__LPSPI4_PCS2                                 0x00A4 0x08FC 0x3 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE9__LPUART6_RTS_B                               0x00A4 0x0000 0x4 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE9__LPI2C6_SDA                                  0x00A4 0x09BC 0x5 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE9__TPM4_CH1                                    0x00A4 0x0808 0x6 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE9__I2S6_RXD3                                   0x00A4 0x0B40 0x7 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE9__SDHC2_D7                                    0x00A4 0x0AB4 0x8 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE9__FLEXSPI2_B_DATA1                            0x00A4 0x0958 0x9 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE9__ENET0_1588_TMR3                             0x00A4 0x0AE0 0xa 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE9__DBI0_D4                                     0x00A4 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE9__EPDC0_VCOM1                                 0x00A4 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE9__LP_HV_DBG_MUX_4                             0x00A4 0x0000 0xe 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE9__DEBUG_MUX1_20                               0x00A4 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE10__PTE10                                      0x00A8 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE10__FXIO1_D13                                  0x00A8 0x0850 0x2 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE10__LPSPI4_PCS3                                0x00A8 0x0900 0x3 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE10__LPUART6_TX                                 0x00A8 0x09D4 0x4 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE10__I3C2_SCL                                   0x00A8 0x08BC 0x5 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE10__TPM4_CH2                                   0x00A8 0x080C 0x6 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE10__I2S6_TX_BCLK                               0x00A8 0x0B4C 0x7 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE10__SDHC2_DQS                                  0x00A8 0x0AB8 0x8 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE10__FLEXSPI2_B_DATA0                           0x00A8 0x0954 0x9 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE10__ENET0_1588_TMR2                            0x00A8 0x0ADC 0xa 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE10__DBI0_D5                                    0x00A8 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE10__EPDC0_VCOM0                                0x00A8 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE10__LP_HV_DBG_MUX_5                            0x00A8 0x0000 0xe 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE10__DEBUG_MUX1_21                              0x00A8 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE11__PTE11                                      0x00AC 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE11__FXIO1_D12                                  0x00AC 0x084C 0x2 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE11__SPDIF_OUT1                                 0x00AC 0x0000 0x3 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE11__LPUART6_RX                                 0x00AC 0x09D0 0x4 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE11__I3C2_SDA                                   0x00AC 0x08C0 0x5 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE11__TPM4_CH3                                   0x00AC 0x0810 0x6 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE11__I2S6_TX_FS                                 0x00AC 0x0B50 0x7 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE11__FLEXSPI2_B_SCLK_B                          0x00AC 0x0000 0x8 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE11__FLEXSPI2_B_SS0_B                           0x00AC 0x0000 0x9 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE11__ENET0_1588_TMR1                            0x00AC 0x0AD8 0xa 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE11__DBI0_D6                                    0x00AC 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE11__EPDC0_PWRCTRL0                             0x00AC 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE11__LP_HV_DBG_MUX_6                            0x00AC 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE12__PTE12                                      0x00B0 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE12__FXIO1_D11                                  0x00B0 0x0848 0x2 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE12__LPSPI4_SIN                                 0x00B0 0x0908 0x3 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE12__LPUART7_CTS_B                              0x00B0 0x09D8 0x4 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE12__LPI2C7_SCL                                 0x00B0 0x09C4 0x5 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE12__TPM4_CH4                                   0x00B0 0x0814 0x6 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE12__I2S6_TXD0                                  0x00B0 0x0000 0x7 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE12__SDHC2_RESET_B                              0x00B0 0x0000 0x8 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE12__FLEXSPI2_B_SS1_B                           0x00B0 0x0000 0x9 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE12__ENET0_1588_TMR0                            0x00B0 0x0AD4 0xa 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE12__DBI0_D7                                    0x00B0 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE12__EPDC0_PWRCTRL1                             0x00B0 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE12__WUU1_P5                                    0x00B0 0x0000 0xd 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE13__PTE13                                      0x00B4 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE13__FXIO1_D10                                  0x00B4 0x0844 0x2 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE13__LPSPI4_SOUT                                0x00B4 0x090C 0x3 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE13__LPUART7_RTS_B                              0x00B4 0x0000 0x4 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE13__LPI2C7_SDA                                 0x00B4 0x09C8 0x5 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE13__TPM4_CH5                                   0x00B4 0x0818 0x6 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE13__I2S6_TXD1                                  0x00B4 0x0000 0x7 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE13__SDHC1_WP                                   0x00B4 0x0A88 0x8 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE13__ENET0_1588_CLKIN                           0x00B4 0x0AD0 0xa 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE13__DBI0_D8                                    0x00B4 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE13__EPDC0_PWRCTRL2                             0x00B4 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE13__LP_HV_DBG_MUX_7                            0x00B4 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE14__PTE14                                      0x00B8 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE14__FXIO1_D9                                   0x00B8 0x08B8 0x2 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE14__LPSPI4_SCK                                 0x00B8 0x0904 0x3 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE14__LPUART7_TX                                 0x00B8 0x09E0 0x4 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE14__LPI2C7_HREQ                                0x00B8 0x09C0 0x5 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE14__TPM5_CLKIN                                 0x00B8 0x0838 0x6 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE14__I2S6_TXD2                                  0x00B8 0x0000 0x7 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE14__SDHC1_CD                                   0x00B8 0x0A58 0x8 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE14__ENET0_MDIO                                 0x00B8 0x0AF0 0xa 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE14__DBI0_D9                                    0x00B8 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE14__EPDC0_PWRCTRL3                             0x00B8 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE14__LP_HV_DBG_MUX_8                            0x00B8 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE15__PTE15                                      0x00BC 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE15__FXIO1_D8                                   0x00BC 0x08B4 0x2 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE15__LPSPI4_PCS0                                0x00BC 0x08F4 0x3 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE15__LPUART7_RX                                 0x00BC 0x09DC 0x4 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE15__I3C2_PUR                                   0x00BC 0x0000 0x5 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE15__TPM5_CH0                                   0x00BC 0x0820 0x6 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE15__I2S6_TXD3                                  0x00BC 0x0000 0x7 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE15__MQS1_LEFT                                  0x00BC 0x0000 0x8 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE15__ENET0_MDC                                  0x00BC 0x0000 0xa 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE15__DBI0_D10                                   0x00BC 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE15__EPDC0_PWRCOM                               0x00BC 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE15__WUU1_P6                                    0x00BC 0x0000 0xd 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE16__PTE16                                      0x00C0 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE16__FXIO1_D7                                   0x00C0 0x08B0 0x2 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE16__LPSPI5_PCS1                                0x00C0 0x0914 0x3 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE16__LPUART4_CTS_B                              0x00C0 0x08DC 0x4 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE16__LPI2C4_SCL                                 0x00C0 0x08C8 0x5 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE16__TPM5_CH1                                   0x00C0 0x0824 0x6 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE16__MQS1_LEFT                                  0x00C0 0x0000 0x7 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE16__MQS1_RIGHT                                 0x00C0 0x0000 0x8 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE16__USB0_ID                                    0x00C0 0x0AC8 0x9 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE16__ENET0_TXEN                                 0x00C0 0x0000 0xa 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE16__DBI0_D11                                   0x00C0 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE16__EPDC0_PWRIRQ                               0x00C0 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE16__WDOG3_RST                                  0x00C0 0x0000 0xd 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE16__LP_HV_DBG_MUX_9                            0x00C0 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE17__PTE17                                      0x00C4 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE17__FXIO1_D6                                   0x00C4 0x08AC 0x2 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE17__LPSPI5_PCS2                                0x00C4 0x0918 0x3 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE17__LPUART4_RTS_B                              0x00C4 0x0000 0x4 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE17__LPI2C4_SDA                                 0x00C4 0x08CC 0x5 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE17__MQS1_RIGHT                                 0x00C4 0x0000 0x7 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE17__SDHC1_VS                                   0x00C4 0x0000 0x8 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE17__USB0_PWR                                   0x00C4 0x0000 0x9 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE17__ENET0_RXER                                 0x00C4 0x0B08 0xa 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE17__DBI0_D12                                   0x00C4 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE17__EPDC0_PWRSTAT                              0x00C4 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE17__LP_HV_DBG_MUX_10                           0x00C4 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE18__PTE18                                      0x00C8 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE18__FXIO1_D5                                   0x00C8 0x08A8 0x2 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE18__LPSPI5_PCS3                                0x00C8 0x091C 0x3 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE18__LPUART4_TX                                 0x00C8 0x08E4 0x4 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE18__LPI2C4_HREQ                                0x00C8 0x08C4 0x5 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE18__I2S7_TX_BCLK                               0x00C8 0x0B6C 0x7 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE18__USB0_OC                                    0x00C8 0x0AC0 0x9 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE18__ENET0_CRS_DV                               0x00C8 0x0AEC 0xa 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE18__DBI0_D13                                   0x00C8 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE18__EPDC0_PWRWAKE                              0x00C8 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE18__LP_HV_DBG_MUX_11                           0x00C8 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE19__PTE19                                      0x00CC 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE19__FXIO1_D4                                   0x00CC 0x08A4 0x2 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE19__LPUART4_RX                                 0x00CC 0x08E0 0x4 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE19__LPI2C5_HREQ                                0x00CC 0x08D0 0x5 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE19__I3C2_PUR                                   0x00CC 0x0000 0x6 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE19__I2S7_TX_FS                                 0x00CC 0x0B70 0x7 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE19__USB1_PWR                                   0x00CC 0x0000 0x9 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE19__ENET0_REFCLK                               0x00CC 0x0AF4 0xa 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE19__DBI0_D14                                   0x00CC 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE19__EPDC0_GDCLK                                0x00CC 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE19__WUU1_P7                                    0x00CC 0x0000 0xd 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE20__PTE20                                      0x00D0 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE20__FXIO1_D3                                   0x00D0 0x0898 0x2 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE20__LPSPI5_SIN                                 0x00D0 0x0924 0x3 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE20__LPUART5_CTS_B                              0x00D0 0x08E8 0x4 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE20__LPI2C5_SCL                                 0x00D0 0x08D4 0x5 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE20__I2S7_TXD0                                  0x00D0 0x0000 0x7 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE20__USB1_OC                                    0x00D0 0x0AC4 0x9 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE20__ENET0_RXD1                                 0x00D0 0x0AFC 0xa 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE20__DBI0_D15                                   0x00D0 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE20__EPDC0_GDOE                                 0x00D0 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE20__LP_HV_DBG_MUX_12                           0x00D0 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE21__PTE21                                      0x00D4 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE21__FXIO1_D2                                   0x00D4 0x086C 0x2 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE21__LPSPI5_SOUT                                0x00D4 0x0928 0x3 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE21__LPUART5_RTS_B                              0x00D4 0x0000 0x4 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE21__LPI2C5_SDA                                 0x00D4 0x08D8 0x5 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE21__TPM6_CLKIN                                 0x00D4 0x0994 0x6 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE21__I2S7_TXD1                                  0x00D4 0x0000 0x7 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE21__USB1_ID                                    0x00D4 0x0ACC 0x9 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE21__ENET0_RXD0                                 0x00D4 0x0AF8 0xa 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE21__EPDC0_GDRL                                 0x00D4 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE21__WDOG4_RST                                  0x00D4 0x0000 0xd 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE21__LP_HV_DBG_MUX_13                           0x00D4 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE22__PTE22                                      0x00D8 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE22__FXIO1_D1                                   0x00D8 0x0840 0x2 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE22__LPSPI5_SCK                                 0x00D8 0x0920 0x3 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE22__LPUART5_TX                                 0x00D8 0x08F0 0x4 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE22__I3C2_SCL                                   0x00D8 0x08BC 0x5 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE22__TPM6_CH0                                   0x00D8 0x097C 0x6 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE22__I2S7_TXD2                                  0x00D8 0x0000 0x7 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE22__EXT_AUD_MCLK3                              0x00D8 0x0B14 0x9 0x5</div><div class='add'>+#define MX8ULP_PAD_PTE22__ENET0_TXD1                                 0x00D8 0x0000 0xa 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE22__EPDC0_SDOED                                0x00D8 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE22__CLKOUT2                                    0x00D8 0x0000 0xd 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE22__LP_HV_DBG_MUX_14                           0x00D8 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE23__PTE23                                      0x00DC 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE23__FXIO1_D0                                   0x00DC 0x083C 0x2 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE23__LPSPI5_PCS0                                0x00DC 0x0910 0x3 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE23__LPUART5_RX                                 0x00DC 0x08EC 0x4 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE23__I3C2_SDA                                   0x00DC 0x08C0 0x5 0x2</div><div class='add'>+#define MX8ULP_PAD_PTE23__TPM6_CH1                                   0x00DC 0x0980 0x6 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE23__I2S7_TXD3                                  0x00DC 0x0000 0x7 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE23__EXT_AUD_MCLK2                              0x00DC 0x0800 0x9 0x1</div><div class='add'>+#define MX8ULP_PAD_PTE23__ENET0_TXD0                                 0x00DC 0x0000 0xa 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE23__EPDC0_SDOEZ                                0x00DC 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE23__CLKOUT1                                    0x00DC 0x0000 0xd 0x0</div><div class='add'>+#define MX8ULP_PAD_PTE23__LP_HV_DBG_MUX_15                           0x00DC 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF0__PTF0                                        0x0100 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF0__FXIO1_D0                                    0x0100 0x083C 0x2 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF0__LPUART6_CTS_B                               0x0100 0x09CC 0x4 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF0__LPI2C6_SCL                                  0x0100 0x09B8 0x5 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF0__I2S7_RX_BCLK                                0x0100 0x0B64 0x7 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF0__SDHC1_D1                                    0x0100 0x0A68 0x8 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF0__ENET0_RXD1                                  0x0100 0x0AFC 0x9 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF0__USB1_ID                                     0x0100 0x0ACC 0xa 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF0__EPDC0_SDOE                                  0x0100 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF0__DPI0_D23                                    0x0100 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF0__WUU1_P8                                     0x0100 0x0000 0xd 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF1__PTF1                                        0x0104 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF1__FXIO1_D1                                    0x0104 0x0840 0x2 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF1__LPUART6_RTS_B                               0x0104 0x0000 0x4 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF1__LPI2C6_SDA                                  0x0104 0x09BC 0x5 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF1__I2S7_RX_FS                                  0x0104 0x0B68 0x7 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF1__SDHC1_D0                                    0x0104 0x0A64 0x8 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF1__ENET0_RXD0                                  0x0104 0x0AF8 0x9 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF1__LP_HV_DBG_MUX_16                            0x0104 0x0000 0xa 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF1__EPDC0_SDSHR                                 0x0104 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF1__DPI0_D22                                    0x0104 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF1__WDOG3_RST                                   0x0104 0x0000 0xd 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF1__DEBUG_MUX0_16                               0x0104 0x0000 0xe 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF1__DEBUG_MUX1_22                               0x0104 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF2__PTF2                                        0x0108 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF2__FXIO1_D2                                    0x0108 0x086C 0x2 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF2__LPUART6_TX                                  0x0108 0x09D4 0x4 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF2__LPI2C6_HREQ                                 0x0108 0x09B4 0x5 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF2__I2S7_RXD0                                   0x0108 0x0B54 0x7 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF2__SDHC1_CLK                                   0x0108 0x0A5C 0x8 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF2__ENET0_TXD1                                  0x0108 0x0000 0x9 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF2__USB0_ID                                     0x0108 0x0AC8 0xa 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF2__EPDC0_SDCE9                                 0x0108 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF2__DPI0_D21                                    0x0108 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF2__LP_HV_DBG_MUX_17                            0x0108 0x0000 0xd 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF2__DEBUG_MUX0_17                               0x0108 0x0000 0xe 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF2__DEBUG_MUX1_23                               0x0108 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF3__PTF3                                        0x010C 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF3__FXIO1_D3                                    0x010C 0x0898 0x2 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF3__LPUART6_RX                                  0x010C 0x09D0 0x4 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF3__LPI2C7_HREQ                                 0x010C 0x09C0 0x5 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF3__I2S7_RXD1                                   0x010C 0x0B58 0x7 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF3__SDHC1_CMD                                   0x010C 0x0A60 0x8 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF3__ENET0_TXD0                                  0x010C 0x0000 0x9 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF3__USB0_PWR                                    0x010C 0x0000 0xa 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF3__EPDC0_SDCE8                                 0x010C 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF3__DPI0_D20                                    0x010C 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF3__WUU1_P9                                     0x010C 0x0000 0xd 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF3__DEBUG_MUX1_24                               0x010C 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF4__PTF4                                        0x0110 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF4__FXIO1_D4                                    0x0110 0x08A4 0x2 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF4__LPSPI4_PCS1                                 0x0110 0x08F8 0x3 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF4__LPUART7_CTS_B                               0x0110 0x09D8 0x4 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF4__LPI2C7_SCL                                  0x0110 0x09C4 0x5 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF4__TPM7_CLKIN                                  0x0110 0x09B0 0x6 0x1</div><div class='add'>+#define MX8ULP_PAD_PTF4__I2S7_RXD2                                   0x0110 0x0B5C 0x7 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF4__SDHC1_D3                                    0x0110 0x0A70 0x8 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF4__ENET0_TXEN                                  0x0110 0x0000 0x9 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF4__USB0_OC                                     0x0110 0x0AC0 0xa 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF4__EPDC0_SDCE7                                 0x0110 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF4__DPI0_D19                                    0x0110 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF4__WUU1_P10                                    0x0110 0x0000 0xd 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF4__DEBUG_MUX1_25                               0x0110 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF5__PTF5                                        0x0114 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF5__FXIO1_D5                                    0x0114 0x08A8 0x2 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF5__LPSPI4_PCS2                                 0x0114 0x08FC 0x3 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF5__LPUART7_RTS_B                               0x0114 0x0000 0x4 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF5__LPI2C7_SDA                                  0x0114 0x09C8 0x5 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF5__TPM7_CH0                                    0x0114 0x0998 0x6 0x1</div><div class='add'>+#define MX8ULP_PAD_PTF5__I2S7_RXD3                                   0x0114 0x0B60 0x7 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF5__SDHC1_D2                                    0x0114 0x0A6C 0x8 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF5__ENET0_RXER                                  0x0114 0x0B08 0x9 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF5__USB1_PWR                                    0x0114 0x0000 0xa 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF5__EPDC0_SDCE6                                 0x0114 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF5__DPI0_D18                                    0x0114 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF5__LP_HV_DBG_MUX_18                            0x0114 0x0000 0xd 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF5__DEBUG_MUX0_18                               0x0114 0x0000 0xe 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF5__DEBUG_MUX1_26                               0x0114 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF6__LP_HV_DBG_MUX_19                            0x0118 0x0000 0x0 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF6__PTF6                                        0x0118 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF6__FXIO1_D6                                    0x0118 0x08AC 0x2 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF6__LPSPI4_PCS3                                 0x0118 0x0900 0x3 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF6__LPUART7_TX                                  0x0118 0x09E0 0x4 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF6__I3C2_SCL                                    0x0118 0x08BC 0x5 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF6__TPM7_CH1                                    0x0118 0x099C 0x6 0x1</div><div class='add'>+#define MX8ULP_PAD_PTF6__I2S7_MCLK                                   0x0118 0x0000 0x7 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF6__SDHC1_D4                                    0x0118 0x0A74 0x8 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF6__ENET0_CRS_DV                                0x0118 0x0AEC 0x9 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF6__USB1_OC                                     0x0118 0x0AC4 0xa 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF6__EPDC0_SDCE5                                 0x0118 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF6__DPI0_D17                                    0x0118 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF6__WDOG4_RST                                   0x0118 0x0000 0xd 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF6__DEBUG_MUX0_19                               0x0118 0x0000 0xe 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF6__DEBUG_MUX1_27                               0x0118 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF7__PTF7                                        0x011C 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF7__FXIO1_D7                                    0x011C 0x08B0 0x2 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF7__LPUART7_RX                                  0x011C 0x09DC 0x4 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF7__I3C2_SDA                                    0x011C 0x08C0 0x5 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF7__TPM7_CH2                                    0x011C 0x09A0 0x6 0x1</div><div class='add'>+#define MX8ULP_PAD_PTF7__MQS1_LEFT                                   0x011C 0x0000 0x7 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF7__SDHC1_D5                                    0x011C 0x0A78 0x8 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF7__ENET0_REFCLK                                0x011C 0x0AF4 0x9 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF7__TRACE0_D15                                  0x011C 0x0000 0xa 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF7__EPDC0_SDCE4                                 0x011C 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF7__DPI0_D16                                    0x011C 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF7__WUU1_P11                                    0x011C 0x0000 0xd 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF7__DEBUG_MUX1_28                               0x011C 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF8__PTF8                                        0x0120 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF8__FXIO1_D8                                    0x0120 0x08B4 0x2 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF8__LPSPI4_SIN                                  0x0120 0x0908 0x3 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF8__LPUART4_CTS_B                               0x0120 0x08DC 0x4 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF8__LPI2C4_SCL                                  0x0120 0x08C8 0x5 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF8__TPM7_CH3                                    0x0120 0x09A4 0x6 0x1</div><div class='add'>+#define MX8ULP_PAD_PTF8__MQS1_RIGHT                                  0x0120 0x0000 0x7 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF8__SDHC1_D6                                    0x0120 0x0A7C 0x8 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF8__ENET0_MDIO                                  0x0120 0x0AF0 0x9 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF8__TRACE0_D14                                  0x0120 0x0000 0xa 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF8__EPDC0_D15                                   0x0120 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF8__DPI0_D15                                    0x0120 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF8__LP_HV_DBG_MUX_24                            0x0120 0x0000 0xe 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF8__DEBUG_MUX1_29                               0x0120 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF9__PTF9                                        0x0124 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF9__FXIO1_D9                                    0x0124 0x08B8 0x2 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF9__LPSPI4_SOUT                                 0x0124 0x090C 0x3 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF9__LPUART4_RTS_B                               0x0124 0x0000 0x4 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF9__LPI2C4_SDA                                  0x0124 0x08CC 0x5 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF9__TPM7_CH4                                    0x0124 0x09A8 0x6 0x1</div><div class='add'>+#define MX8ULP_PAD_PTF9__EXT_AUD_MCLK2                               0x0124 0x0800 0x7 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF9__SDHC1_D7                                    0x0124 0x0A80 0x8 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF9__ENET0_MDC                                   0x0124 0x0000 0x9 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF9__TRACE0_D13                                  0x0124 0x0000 0xa 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF9__EPDC0_D14                                   0x0124 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF9__DPI0_D14                                    0x0124 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF9__LP_HV_DBG_MUX_25                            0x0124 0x0000 0xe 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF9__DEBUG_MUX1_30                               0x0124 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF10__LP_HV_DBG_MUX_26                           0x0128 0x0000 0x0 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF10__PTF10                                      0x0128 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF10__FXIO1_D10                                  0x0128 0x0844 0x2 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF10__LPSPI4_SCK                                 0x0128 0x0904 0x3 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF10__LPUART4_TX                                 0x0128 0x08E4 0x4 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF10__LPI2C4_HREQ                                0x0128 0x08C4 0x5 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF10__TPM7_CH5                                   0x0128 0x09AC 0x6 0x1</div><div class='add'>+#define MX8ULP_PAD_PTF10__I2S4_RX_BCLK                               0x0128 0x0000 0x7 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF10__SDHC1_DQS                                  0x0128 0x0A84 0x8 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF10__ENET0_1588_CLKIN                           0x0128 0x0AD0 0x9 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF10__TRACE0_D12                                 0x0128 0x0000 0xa 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF10__EPDC0_D13                                  0x0128 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF10__DPI0_D13                                   0x0128 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF10__DEBUG_MUX0_20                              0x0128 0x0000 0xe 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF10__DEBUG_MUX1_31                              0x0128 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF11__PTF11                                      0x012C 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF11__FXIO1_D11                                  0x012C 0x0848 0x2 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF11__LPSPI4_PCS0                                0x012C 0x08F4 0x3 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF11__LPUART4_RX                                 0x012C 0x08E0 0x4 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF11__TPM4_CLKIN                                 0x012C 0x081C 0x6 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF11__I2S4_RX_FS                                 0x012C 0x0000 0x7 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF11__SDHC1_RESET_B                              0x012C 0x0000 0x8 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF11__ENET0_1588_TMR0                            0x012C 0x0AD4 0x9 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF11__TRACE0_D11                                 0x012C 0x0000 0xa 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF11__EPDC0_D12                                  0x012C 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF11__DPI0_D12                                   0x012C 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF11__LP_HV_DBG_MUX_27                           0x012C 0x0000 0xe 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF11__DEBUG_MUX1_32                              0x012C 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF12__PTF12                                      0x0130 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF12__FXIO1_D12                                  0x0130 0x084C 0x2 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF12__LPSPI5_PCS1                                0x0130 0x0914 0x3 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF12__LPUART5_CTS_B                              0x0130 0x08E8 0x4 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF12__LPI2C5_SCL                                 0x0130 0x08D4 0x5 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF12__TPM4_CH0                                   0x0130 0x0804 0x6 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF12__I2S4_RXD0                                  0x0130 0x0000 0x7 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF12__SDHC2_WP                                   0x0130 0x0ABC 0x8 0x1</div><div class='add'>+#define MX8ULP_PAD_PTF12__ENET0_1588_TMR1                            0x0130 0x0AD8 0x9 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF12__TRACE0_D10                                 0x0130 0x0000 0xa 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF12__EPDC0_D11                                  0x0130 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF12__DPI0_D11                                   0x0130 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF12__LP_HV_DBG_MUX_28                           0x0130 0x0000 0xe 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF12__DEBUG_MUX1_33                              0x0130 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF13__PTF13                                      0x0134 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF13__FXIO1_D13                                  0x0134 0x0850 0x2 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF13__LPSPI5_PCS2                                0x0134 0x0918 0x3 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF13__LPUART5_RTS_B                              0x0134 0x0000 0x4 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF13__LPI2C5_SDA                                 0x0134 0x08D8 0x5 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF13__TPM4_CH1                                   0x0134 0x0808 0x6 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF13__I2S4_RXD1                                  0x0134 0x0000 0x7 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF13__SDHC2_CD                                   0x0134 0x0A8C 0x8 0x1</div><div class='add'>+#define MX8ULP_PAD_PTF13__ENET0_1588_TMR2                            0x0134 0x0ADC 0x9 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF13__TRACE0_D9                                  0x0134 0x0000 0xa 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF13__EPDC0_D10                                  0x0134 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF13__DPI0_D10                                   0x0134 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF13__DEBUG_MUX0_21                              0x0134 0x0000 0xe 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF13__LP_HV_DBG_MUX_29                           0x0134 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF14__PTF14                                      0x0138 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF14__FXIO1_D14                                  0x0138 0x0854 0x2 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF14__LPSPI5_PCS3                                0x0138 0x091C 0x3 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF14__LPUART5_TX                                 0x0138 0x08F0 0x4 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF14__LPI2C5_HREQ                                0x0138 0x08D0 0x5 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF14__TPM4_CH2                                   0x0138 0x080C 0x6 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF14__I2S4_MCLK                                  0x0138 0x0000 0x7 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF14__SDHC2_VS                                   0x0138 0x0000 0x8 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF14__ENET0_1588_TMR3                            0x0138 0x0AE0 0x9 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF14__TRACE0_D8                                  0x0138 0x0000 0xa 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF14__EPDC0_D9                                   0x0138 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF14__DPI0_D9                                    0x0138 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF14__DEBUG_MUX0_22                              0x0138 0x0000 0xe 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF14__LP_HV_DBG_MUX_30                           0x0138 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF15__PTF15                                      0x013C 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF15__FXIO1_D15                                  0x013C 0x0858 0x2 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF15__LPUART5_RX                                 0x013C 0x08EC 0x4 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF15__TPM4_CH3                                   0x013C 0x0810 0x6 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF15__I2S4_TX_BCLK                               0x013C 0x0000 0x7 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF15__SDHC2_D1                                   0x013C 0x0A9C 0x8 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF15__ENET0_RXD2                                 0x013C 0x0B00 0x9 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF15__TRACE0_D7                                  0x013C 0x0000 0xa 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF15__EPDC0_D8                                   0x013C 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF15__DPI0_D8                                    0x013C 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF15__LP_HV_DBG_MUX_31                           0x013C 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF16__PTF16                                      0x0140 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF16__FXIO1_D16                                  0x0140 0x085C 0x2 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF16__LPSPI5_SIN                                 0x0140 0x0924 0x3 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF16__LPUART6_CTS_B                              0x0140 0x09CC 0x4 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF16__LPI2C6_SCL                                 0x0140 0x09B8 0x5 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF16__TPM4_CH4                                   0x0140 0x0814 0x6 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF16__I2S4_TX_FS                                 0x0140 0x0000 0x7 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF16__SDHC2_D0                                   0x0140 0x0A98 0x8 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF16__ENET0_RXD3                                 0x0140 0x0B04 0x9 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF16__TRACE0_D6                                  0x0140 0x0000 0xa 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF16__EPDC0_D7                                   0x0140 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF16__DPI0_D7                                    0x0140 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF16__LP_HV_DBG_MUX_32                           0x0140 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF17__PTF17                                      0x0144 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF17__FXIO1_D17                                  0x0144 0x0860 0x2 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF17__LPSPI5_SOUT                                0x0144 0x0928 0x3 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF17__LPUART6_RTS_B                              0x0144 0x0000 0x4 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF17__LPI2C6_SDA                                 0x0144 0x09BC 0x5 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF17__TPM4_CH5                                   0x0144 0x0818 0x6 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF17__I2S4_TXD0                                  0x0144 0x0000 0x7 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF17__SDHC2_CLK                                  0x0144 0x0A90 0x8 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF17__ENET0_RXCLK                                0x0144 0x0B0C 0x9 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF17__TRACE0_D5                                  0x0144 0x0000 0xa 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF17__EPDC0_D6                                   0x0144 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF17__DPI0_D6                                    0x0144 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF17__DEBUG_MUX0_23                              0x0144 0x0000 0xe 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF17__LP_HV_DBG_MUX_33                           0x0144 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF18__PTF18                                      0x0148 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF18__FXIO1_D18                                  0x0148 0x0864 0x2 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF18__LPSPI5_SCK                                 0x0148 0x0920 0x3 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF18__LPUART6_TX                                 0x0148 0x09D4 0x4 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF18__LPI2C6_HREQ                                0x0148 0x09B4 0x5 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF18__TPM5_CLKIN                                 0x0148 0x0838 0x6 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF18__I2S4_TXD1                                  0x0148 0x0000 0x7 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF18__SDHC2_CMD                                  0x0148 0x0A94 0x8 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF18__ENET0_TXD2                                 0x0148 0x0000 0x9 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF18__TRACE0_D4                                  0x0148 0x0000 0xa 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF18__EPDC0_D5                                   0x0148 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF18__DPI0_D5                                    0x0148 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF19__PTF19                                      0x014C 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF19__FXIO1_D19                                  0x014C 0x0868 0x2 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF19__LPSPI5_PCS0                                0x014C 0x0910 0x3 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF19__LPUART6_RX                                 0x014C 0x09D0 0x4 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF19__TPM5_CH0                                   0x014C 0x0820 0x6 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF19__I2S5_RX_BCLK                               0x014C 0x0000 0x7 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF19__SDHC2_D3                                   0x014C 0x0AA4 0x8 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF19__ENET0_TXD3                                 0x014C 0x0000 0x9 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF19__TRACE0_D3                                  0x014C 0x0000 0xa 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF19__EPDC0_D4                                   0x014C 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF19__DPI0_D4                                    0x014C 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF20__PTF20                                      0x0150 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF20__FXIO1_D20                                  0x0150 0x0870 0x2 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF20__LPUART7_CTS_B                              0x0150 0x09D8 0x4 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF20__LPI2C7_SCL                                 0x0150 0x09C4 0x5 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF20__TPM5_CH1                                   0x0150 0x0824 0x6 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF20__I2S5_RX_FS                                 0x0150 0x0000 0x7 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF20__SDHC2_D2                                   0x0150 0x0AA0 0x8 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF20__ENET0_TXCLK                                0x0150 0x0B10 0x9 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF20__TRACE0_D2                                  0x0150 0x0000 0xa 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF20__EPDC0_D3                                   0x0150 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF20__DPI0_D3                                    0x0150 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF21__PTF21                                      0x0154 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF21__FXIO1_D21                                  0x0154 0x0874 0x2 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF21__SPDIF_CLK                                  0x0154 0x0000 0x3 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF21__LPUART7_RTS_B                              0x0154 0x0000 0x4 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF21__LPI2C7_SDA                                 0x0154 0x09C8 0x5 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF21__TPM6_CLKIN                                 0x0154 0x0994 0x6 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF21__I2S5_RXD0                                  0x0154 0x0000 0x7 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF21__SDHC2_D4                                   0x0154 0x0AA8 0x8 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF21__ENET0_CRS                                  0x0154 0x0AE8 0x9 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF21__TRACE0_D1                                  0x0154 0x0000 0xa 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF21__EPDC0_D2                                   0x0154 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF21__DPI0_D2                                    0x0154 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF22__PTF22                                      0x0158 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF22__FXIO1_D22                                  0x0158 0x0878 0x2 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF22__SPDIF_IN0                                  0x0158 0x0B74 0x3 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF22__LPUART7_TX                                 0x0158 0x09E0 0x4 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF22__LPI2C7_HREQ                                0x0158 0x09C0 0x5 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF22__TPM6_CH0                                   0x0158 0x097C 0x6 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF22__I2S5_RXD1                                  0x0158 0x0000 0x7 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF22__SDHC2_D5                                   0x0158 0x0AAC 0x8 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF22__ENET0_COL                                  0x0158 0x0AE4 0x9 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF22__TRACE0_D0                                  0x0158 0x0000 0xa 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF22__EPDC0_D1                                   0x0158 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF22__DPI0_D1                                    0x0158 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF23__PTF23                                      0x015C 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF23__FXIO1_D23                                  0x015C 0x087C 0x2 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF23__SPDIF_OUT0                                 0x015C 0x0000 0x3 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF23__LPUART7_RX                                 0x015C 0x09DC 0x4 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF23__I3C2_PUR                                   0x015C 0x0000 0x5 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF23__TPM6_CH1                                   0x015C 0x0980 0x6 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF23__I2S5_RXD2                                  0x015C 0x0000 0x7 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF23__SDHC2_D6                                   0x015C 0x0AB0 0x8 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF23__ENET0_TXER                                 0x015C 0x0000 0x9 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF23__TRACE0_CLKOUT                              0x015C 0x0000 0xa 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF23__EPDC0_D0                                   0x015C 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF23__DPI0_D0                                    0x015C 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF24__PTF24                                      0x0160 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF24__FXIO1_D24                                  0x0160 0x0880 0x2 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF24__SPDIF_IN1                                  0x0160 0x0B78 0x3 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF24__I3C2_SCL                                   0x0160 0x08BC 0x5 0x4</div><div class='add'>+#define MX8ULP_PAD_PTF24__I2S5_RXD3                                  0x0160 0x0000 0x7 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF24__SDHC2_D7                                   0x0160 0x0AB4 0x8 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF24__DBI0_WRX                                   0x0160 0x0000 0xa 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF24__EPDC0_SDCLK                                0x0160 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF24__DPI0_PCLK                                  0x0160 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF24__WUU1_P12                                   0x0160 0x0000 0xd 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF25__PTF25                                      0x0164 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF25__FXIO1_D25                                  0x0164 0x0884 0x2 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF25__SPDIF_OUT1                                 0x0164 0x0000 0x3 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF25__I3C2_SDA                                   0x0164 0x08C0 0x5 0x4</div><div class='add'>+#define MX8ULP_PAD_PTF25__TPM7_CH5                                   0x0164 0x09AC 0x6 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF25__I2S5_MCLK                                  0x0164 0x0000 0x7 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF25__SDHC2_DQS                                  0x0164 0x0AB8 0x8 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF25__EXT_AUD_MCLK2                              0x0164 0x0800 0x9 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF25__EPDC0_GDSP                                 0x0164 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF25__DPI0_VSYNC                                 0x0164 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF25__WUU1_P13                                   0x0164 0x0000 0xd 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF26__PTF26                                      0x0168 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF26__FXIO1_D26                                  0x0168 0x0888 0x2 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF26__SPDIF_IN2                                  0x0168 0x0B7C 0x3 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF26__TPM7_CLKIN                                 0x0168 0x09B0 0x6 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF26__I2S5_TX_BCLK                               0x0168 0x0000 0x7 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF26__SDHC2_RESET_B                              0x0168 0x0000 0x8 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF26__EPDC0_SDLE                                 0x0168 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF26__DPI0_HSYNC                                 0x0168 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF26__WUU1_P14                                   0x0168 0x0000 0xd 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF27__PTF27                                      0x016C 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF27__FXIO1_D27                                  0x016C 0x088C 0x2 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF27__SPDIF_OUT2                                 0x016C 0x0000 0x3 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF27__TPM7_CH0                                   0x016C 0x0998 0x6 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF27__I2S5_TX_FS                                 0x016C 0x0000 0x7 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF27__SDHC2_WP                                   0x016C 0x0ABC 0x8 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF27__EPDC0_SDCE0                                0x016C 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF27__DPI0_DE                                    0x016C 0x0000 0xc 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF27__WUU1_P15                                   0x016C 0x0000 0xd 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF28__PTF28                                      0x0170 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF28__FXIO1_D28                                  0x0170 0x0890 0x2 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF28__SPDIF_IN3                                  0x0170 0x0B80 0x3 0x3</div><div class='add'>+#define MX8ULP_PAD_PTF28__TPM7_CH1                                   0x0170 0x099C 0x6 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF28__I2S5_TXD0                                  0x0170 0x0000 0x7 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF28__SDHC2_CD                                   0x0170 0x0A8C 0x8 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF28__EPDC0_SDCLK_B                              0x0170 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF28__LP_HV_DBG_MUX_20                           0x0170 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF29__PTF29                                      0x0174 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF29__FXIO1_D29                                  0x0174 0x0894 0x2 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF29__SPDIF_OUT3                                 0x0174 0x0000 0x3 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF29__TPM7_CH2                                   0x0174 0x09A0 0x6 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF29__I2S5_TXD1                                  0x0174 0x0000 0x7 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF29__SDHC2_VS                                   0x0174 0x0000 0x8 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF29__EPDC0_SDCE1                                0x0174 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF29__WDOG3_RST                                  0x0174 0x0000 0xd 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF29__LP_HV_DBG_MUX_21                           0x0174 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF30__PTF30                                      0x0178 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF30__FXIO1_D30                                  0x0178 0x089C 0x2 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF30__TPM7_CH3                                   0x0178 0x09A4 0x6 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF30__I2S5_TXD2                                  0x0178 0x0000 0x7 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF30__MQS1_LEFT                                  0x0178 0x0000 0x8 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF30__EPDC0_SDCE2                                0x0178 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF30__WDOG4_RST                                  0x0178 0x0000 0xd 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF30__LP_HV_DBG_MUX_22                           0x0178 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF31__PTF31                                      0x017C 0x0000 0x1 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF31__FXIO1_D31                                  0x017C 0x08A0 0x2 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF31__TPM7_CH4                                   0x017C 0x09A8 0x6 0x2</div><div class='add'>+#define MX8ULP_PAD_PTF31__I2S5_TXD3                                  0x017C 0x0000 0x7 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF31__MQS1_RIGHT                                 0x017C 0x0000 0x8 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF31__EPDC0_SDCE3                                0x017C 0x0000 0xb 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF31__WDOG5_RST                                  0x017C 0x0000 0xd 0x0</div><div class='add'>+#define MX8ULP_PAD_PTF31__LP_HV_DBG_MUX_23                           0x017C 0x0000 0xf 0x0</div><div class='add'>+#define MX8ULP_PAD_BOOT_MODE0__BOOT_MODE0                            0x0400 0x0000 0x0 0x0</div><div class='add'>+#define MX8ULP_PAD_BOOT_MODE1__BOOT_MODE1                            0x0404 0x0000 0x0 0x0</div><div class='add'>+</div><div class='add'>+#endif /* __DTS_IMX8ULP_PINFUNC_H */</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi<br/>new file mode 100644<br/>index 000000000000..13b01f3aa2a4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8ulp.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8ulp.dtsi</a></div><div class='hunk'>@@ -0,0 +1,863 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/imx8ulp-clock.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/power/imx8ulp-power.h&gt;</div><div class='add'>+#include &lt;dt-bindings/thermal/thermal.h&gt;</div><div class='add'>+</div><div class='add'>+#include "imx8ulp-pinfunc.h"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;fec;</div><div class='add'>+		gpio0 = &amp;gpiod;</div><div class='add'>+		gpio1 = &amp;gpioe;</div><div class='add'>+		gpio2 = &amp;gpiof;</div><div class='add'>+		mmc0 = &amp;usdhc0;</div><div class='add'>+		mmc1 = &amp;usdhc1;</div><div class='add'>+		mmc2 = &amp;usdhc2;</div><div class='add'>+		serial0 = &amp;lpuart4;</div><div class='add'>+		serial1 = &amp;lpuart5;</div><div class='add'>+		serial2 = &amp;lpuart6;</div><div class='add'>+		serial3 = &amp;lpuart7;</div><div class='add'>+		spi0 = &amp;lpspi4;</div><div class='add'>+		spi1 = &amp;lpspi5;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		A35_0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a35";</div><div class='add'>+			reg = &lt;0x0 0x0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;A35_L2&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_sleep&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		A35_1: cpu@1 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a35";</div><div class='add'>+			reg = &lt;0x0 0x1&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;A35_L2&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_sleep&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		A35_L2: l2-cache0 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		idle-states {</div><div class='add'>+			entry-method = "psci";</div><div class='add'>+</div><div class='add'>+			cpu_sleep: cpu-sleep {</div><div class='add'>+				compatible = "arm,idle-state";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x0&gt;;</div><div class='add'>+				local-timer-stop;</div><div class='add'>+				entry-latency-us = &lt;1000&gt;;</div><div class='add'>+				exit-latency-us = &lt;700&gt;;</div><div class='add'>+				min-residency-us = &lt;2700&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gic: interrupt-controller@2d400000 {</div><div class='add'>+		compatible = "arm,gic-v3";</div><div class='add'>+		reg = &lt;0x0 0x2d400000 0 0x10000&gt;, /* GIC Dist */</div><div class='add'>+		      &lt;0x0 0x2d440000 0 0xc0000&gt;; /* GICR (RD_base + SGI_base) */</div><div class='add'>+		#interrupt-cells = &lt;3&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu {</div><div class='add'>+		compatible = "arm,cortex-a35-pmu";</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_PPI 7</div><div class='add'>+			     (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='add'>+		interrupt-affinity = &lt;&amp;A35_0&gt;, &lt;&amp;A35_1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-1.0";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	thermal-zones {</div><div class='add'>+		cpu-thermal {</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			polling-delay = &lt;2000&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;scmi_sensor 0&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu_alert0: trip0 {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_crit0: trip1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 IRQ_TYPE_LEVEL_LOW&gt;, /* Physical Secure */</div><div class='add'>+			     &lt;GIC_PPI 14 IRQ_TYPE_LEVEL_LOW&gt;, /* Physical Non-Secure */</div><div class='add'>+			     &lt;GIC_PPI 11 IRQ_TYPE_LEVEL_LOW&gt;, /* Virtual */</div><div class='add'>+			     &lt;GIC_PPI 10 IRQ_TYPE_LEVEL_LOW&gt;; /* Hypervisor */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	frosc: clock-frosc {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		clock-frequency = &lt;192000000&gt;;</div><div class='add'>+		clock-output-names = "frosc";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lposc: clock-lposc {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		clock-frequency = &lt;1000000&gt;;</div><div class='add'>+		clock-output-names = "lposc";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rosc: clock-rosc {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		clock-frequency = &lt;32768&gt;;</div><div class='add'>+		clock-output-names = "rosc";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sosc: clock-sosc {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+		clock-output-names = "sosc";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sram@2201f000 {</div><div class='add'>+		compatible = "mmio-sram";</div><div class='add'>+		reg = &lt;0x0 0x2201f000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges = &lt;0 0x0 0x2201f000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+		scmi_buf: scmi-sram-section@0 {</div><div class='add'>+			compatible = "arm,scmi-shmem";</div><div class='add'>+			reg = &lt;0x0 0x400&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	firmware {</div><div class='add'>+		scmi {</div><div class='add'>+			compatible = "arm,scmi-smc";</div><div class='add'>+			arm,smc-id = &lt;0xc20000fe&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			shmem = &lt;&amp;scmi_buf&gt;;</div><div class='add'>+</div><div class='add'>+			scmi_devpd: protocol@11 {</div><div class='add'>+				reg = &lt;0x11&gt;;</div><div class='add'>+				#power-domain-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			scmi_sensor: protocol@15 {</div><div class='add'>+				reg = &lt;0x15&gt;;</div><div class='add'>+				#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cm33: remoteproc-cm33 {</div><div class='add'>+		compatible = "fsl,imx8ulp-cm33";</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc: soc@0 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges = &lt;0x0 0x0 0x0 0x40000000&gt;,</div><div class='add'>+			 &lt;0x60000000 0x0 0x60000000 0x1000000&gt;;</div><div class='add'>+</div><div class='add'>+		s4muap: mailbox@27020000 {</div><div class='add'>+			compatible = "fsl,imx8ulp-mu-s4";</div><div class='add'>+			reg = &lt;0x27020000 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#mbox-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		per_bridge3: bus@29000000 {</div><div class='add'>+			compatible = "simple-bus";</div><div class='add'>+			reg = &lt;0x29000000 0x800000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			edma1: dma-controller@29010000 {</div><div class='add'>+				compatible = "fsl,imx8ulp-edma";</div><div class='add'>+				reg = &lt;0x29010000 0x210000&gt;;</div><div class='add'>+				#dma-cells = &lt;3&gt;;</div><div class='add'>+				dma-channels = &lt;32&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;pcc3 IMX8ULP_CLK_DMA1_MP&gt;,</div><div class='add'>+					&lt;&amp;pcc3 IMX8ULP_CLK_DMA1_CH0&gt;, &lt;&amp;pcc3 IMX8ULP_CLK_DMA1_CH1&gt;,</div><div class='add'>+					&lt;&amp;pcc3 IMX8ULP_CLK_DMA1_CH2&gt;, &lt;&amp;pcc3 IMX8ULP_CLK_DMA1_CH3&gt;,</div><div class='add'>+					&lt;&amp;pcc3 IMX8ULP_CLK_DMA1_CH4&gt;, &lt;&amp;pcc3 IMX8ULP_CLK_DMA1_CH5&gt;,</div><div class='add'>+					&lt;&amp;pcc3 IMX8ULP_CLK_DMA1_CH6&gt;, &lt;&amp;pcc3 IMX8ULP_CLK_DMA1_CH7&gt;,</div><div class='add'>+					&lt;&amp;pcc3 IMX8ULP_CLK_DMA1_CH8&gt;, &lt;&amp;pcc3 IMX8ULP_CLK_DMA1_CH9&gt;,</div><div class='add'>+					&lt;&amp;pcc3 IMX8ULP_CLK_DMA1_CH10&gt;, &lt;&amp;pcc3 IMX8ULP_CLK_DMA1_CH11&gt;,</div><div class='add'>+					&lt;&amp;pcc3 IMX8ULP_CLK_DMA1_CH12&gt;, &lt;&amp;pcc3 IMX8ULP_CLK_DMA1_CH13&gt;,</div><div class='add'>+					&lt;&amp;pcc3 IMX8ULP_CLK_DMA1_CH14&gt;, &lt;&amp;pcc3 IMX8ULP_CLK_DMA1_CH15&gt;,</div><div class='add'>+					&lt;&amp;pcc3 IMX8ULP_CLK_DMA1_CH16&gt;, &lt;&amp;pcc3 IMX8ULP_CLK_DMA1_CH17&gt;,</div><div class='add'>+					&lt;&amp;pcc3 IMX8ULP_CLK_DMA1_CH18&gt;, &lt;&amp;pcc3 IMX8ULP_CLK_DMA1_CH19&gt;,</div><div class='add'>+					&lt;&amp;pcc3 IMX8ULP_CLK_DMA1_CH20&gt;, &lt;&amp;pcc3 IMX8ULP_CLK_DMA1_CH21&gt;,</div><div class='add'>+					&lt;&amp;pcc3 IMX8ULP_CLK_DMA1_CH22&gt;, &lt;&amp;pcc3 IMX8ULP_CLK_DMA1_CH23&gt;,</div><div class='add'>+					&lt;&amp;pcc3 IMX8ULP_CLK_DMA1_CH24&gt;, &lt;&amp;pcc3 IMX8ULP_CLK_DMA1_CH25&gt;,</div><div class='add'>+					&lt;&amp;pcc3 IMX8ULP_CLK_DMA1_CH26&gt;, &lt;&amp;pcc3 IMX8ULP_CLK_DMA1_CH27&gt;,</div><div class='add'>+					&lt;&amp;pcc3 IMX8ULP_CLK_DMA1_CH28&gt;, &lt;&amp;pcc3 IMX8ULP_CLK_DMA1_CH29&gt;,</div><div class='add'>+					&lt;&amp;pcc3 IMX8ULP_CLK_DMA1_CH30&gt;, &lt;&amp;pcc3 IMX8ULP_CLK_DMA1_CH31&gt;;</div><div class='add'>+				clock-names = "dma", "ch00","ch01", "ch02", "ch03",</div><div class='add'>+						"ch04", "ch05", "ch06", "ch07",</div><div class='add'>+						"ch08", "ch09", "ch10", "ch11",</div><div class='add'>+						"ch12", "ch13", "ch14", "ch15",</div><div class='add'>+						"ch16", "ch17", "ch18", "ch19",</div><div class='add'>+						"ch20", "ch21", "ch22", "ch23",</div><div class='add'>+						"ch24", "ch25", "ch26", "ch27",</div><div class='add'>+						"ch28", "ch29", "ch30", "ch31";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mu: mailbox@29220000 {</div><div class='add'>+				compatible = "fsl,imx8ulp-mu";</div><div class='add'>+				reg = &lt;0x29220000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#mbox-cells = &lt;2&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mu3: mailbox@29230000 {</div><div class='add'>+				compatible = "fsl,imx8ulp-mu";</div><div class='add'>+				reg = &lt;0x29230000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;pcc3 IMX8ULP_CLK_MU3_A&gt;;</div><div class='add'>+				#mbox-cells = &lt;2&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			wdog3: watchdog@292a0000 {</div><div class='add'>+				compatible = "fsl,imx8ulp-wdt", "fsl,imx7ulp-wdt";</div><div class='add'>+				reg = &lt;0x292a0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;pcc3 IMX8ULP_CLK_WDOG3&gt;;</div><div class='add'>+				assigned-clocks = &lt;&amp;pcc3 IMX8ULP_CLK_WDOG3&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;cgc1 IMX8ULP_CLK_SOSC_DIV2&gt;;</div><div class='add'>+				timeout-sec = &lt;40&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cgc1: clock-controller@292c0000 {</div><div class='add'>+				compatible = "fsl,imx8ulp-cgc1";</div><div class='add'>+				reg = &lt;0x292c0000 0x10000&gt;;</div><div class='add'>+				#clock-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pcc3: clock-controller@292d0000 {</div><div class='add'>+				compatible = "fsl,imx8ulp-pcc3";</div><div class='add'>+				reg = &lt;0x292d0000 0x10000&gt;;</div><div class='add'>+				#clock-cells = &lt;1&gt;;</div><div class='add'>+				#reset-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			crypto: crypto@292e0000 {</div><div class='add'>+				compatible = "fsl,sec-v4.0";</div><div class='add'>+				reg = &lt;0x292e0000 0x10000&gt;;</div><div class='add'>+				ranges = &lt;0 0x292e0000 0x10000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				sec_jr0: jr@1000 {</div><div class='add'>+					compatible = "fsl,sec-v4.0-job-ring";</div><div class='add'>+					reg = &lt;0x1000 0x1000&gt;;</div><div class='add'>+					interrupts = &lt;GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				sec_jr1: jr@2000 {</div><div class='add'>+					compatible = "fsl,sec-v4.0-job-ring";</div><div class='add'>+					reg = &lt;0x2000 0x1000&gt;;</div><div class='add'>+					interrupts = &lt;GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				sec_jr2: jr@3000 {</div><div class='add'>+					compatible = "fsl,sec-v4.0-job-ring";</div><div class='add'>+					reg = &lt;0x3000 0x1000&gt;;</div><div class='add'>+					interrupts = &lt;GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				sec_jr3: jr@4000 {</div><div class='add'>+					compatible = "fsl,sec-v4.0-job-ring";</div><div class='add'>+					reg = &lt;0x4000 0x1000&gt;;</div><div class='add'>+					interrupts = &lt;GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tpm5: tpm@29340000 {</div><div class='add'>+				compatible = "fsl,imx8ulp-tpm", "fsl,imx7ulp-tpm";</div><div class='add'>+				reg = &lt;0x29340000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;pcc3 IMX8ULP_CLK_TPM5&gt;,</div><div class='add'>+					 &lt;&amp;pcc3 IMX8ULP_CLK_TPM5&gt;;</div><div class='add'>+				clock-names = "ipg", "per";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpi2c4: i2c@29370000 {</div><div class='add'>+				compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+				reg = &lt;0x29370000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;pcc3 IMX8ULP_CLK_LPI2C4&gt;,</div><div class='add'>+					 &lt;&amp;pcc3 IMX8ULP_CLK_LPI2C4&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				assigned-clocks = &lt;&amp;pcc3 IMX8ULP_CLK_LPI2C4&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;cgc1 IMX8ULP_CLK_FROSC_DIV2&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;48000000&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpi2c5: i2c@29380000 {</div><div class='add'>+				compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+				reg = &lt;0x29380000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;pcc3 IMX8ULP_CLK_LPI2C5&gt;,</div><div class='add'>+					 &lt;&amp;pcc3 IMX8ULP_CLK_LPI2C5&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				assigned-clocks = &lt;&amp;pcc3 IMX8ULP_CLK_LPI2C5&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;cgc1 IMX8ULP_CLK_FROSC_DIV2&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;48000000&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpuart4: serial@29390000 {</div><div class='add'>+				compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";</div><div class='add'>+				reg = &lt;0x29390000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;pcc3 IMX8ULP_CLK_LPUART4&gt;;</div><div class='add'>+				clock-names = "ipg";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpuart5: serial@293a0000 {</div><div class='add'>+				compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";</div><div class='add'>+				reg = &lt;0x293a0000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;pcc3 IMX8ULP_CLK_LPUART5&gt;;</div><div class='add'>+				clock-names = "ipg";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpspi4: spi@293b0000 {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";</div><div class='add'>+				reg = &lt;0x293b0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;pcc3 IMX8ULP_CLK_LPSPI4&gt;,</div><div class='add'>+					 &lt;&amp;pcc3 IMX8ULP_CLK_LPSPI4&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				assigned-clocks = &lt;&amp;pcc3 IMX8ULP_CLK_LPSPI4&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;cgc1 IMX8ULP_CLK_FROSC_DIV2&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;48000000&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpspi5: spi@293c0000 {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";</div><div class='add'>+				reg = &lt;0x293c0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;pcc3 IMX8ULP_CLK_LPSPI5&gt;,</div><div class='add'>+					 &lt;&amp;pcc3 IMX8ULP_CLK_LPSPI5&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				assigned-clocks = &lt;&amp;pcc3 IMX8ULP_CLK_LPSPI5&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;cgc1 IMX8ULP_CLK_FROSC_DIV2&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;48000000&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		per_bridge4: bus@29800000 {</div><div class='add'>+			compatible = "simple-bus";</div><div class='add'>+			reg = &lt;0x29800000 0x800000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			pcc4: clock-controller@29800000 {</div><div class='add'>+				compatible = "fsl,imx8ulp-pcc4";</div><div class='add'>+				reg = &lt;0x29800000 0x10000&gt;;</div><div class='add'>+				#clock-cells = &lt;1&gt;;</div><div class='add'>+				#reset-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			flexspi2: spi@29810000 {</div><div class='add'>+				compatible = "nxp,imx8ulp-fspi";</div><div class='add'>+				reg = &lt;0x29810000 0x10000&gt;, &lt;0x60000000 0x10000000&gt;;</div><div class='add'>+				reg-names = "fspi_base", "fspi_mmap";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;pcc4 IMX8ULP_CLK_FLEXSPI2&gt;,</div><div class='add'>+					 &lt;&amp;pcc4 IMX8ULP_CLK_FLEXSPI2&gt;;</div><div class='add'>+				clock-names = "fspi_en", "fspi";</div><div class='add'>+				assigned-clocks = &lt;&amp;pcc4 IMX8ULP_CLK_FLEXSPI2&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpi2c6: i2c@29840000 {</div><div class='add'>+				compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+				reg = &lt;0x29840000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;pcc4 IMX8ULP_CLK_LPI2C6&gt;,</div><div class='add'>+					 &lt;&amp;pcc4 IMX8ULP_CLK_LPI2C6&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				assigned-clocks = &lt;&amp;pcc4 IMX8ULP_CLK_LPI2C6&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;cgc1 IMX8ULP_CLK_FROSC_DIV2&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;48000000&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpi2c7: i2c@29850000 {</div><div class='add'>+				compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+				reg = &lt;0x29850000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;pcc4 IMX8ULP_CLK_LPI2C7&gt;,</div><div class='add'>+					 &lt;&amp;pcc4 IMX8ULP_CLK_LPI2C7&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				assigned-clocks = &lt;&amp;pcc4 IMX8ULP_CLK_LPI2C7&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;cgc1 IMX8ULP_CLK_FROSC_DIV2&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;48000000&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpuart6: serial@29860000 {</div><div class='add'>+				compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";</div><div class='add'>+				reg = &lt;0x29860000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;pcc4 IMX8ULP_CLK_LPUART6&gt;;</div><div class='add'>+				clock-names = "ipg";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpuart7: serial@29870000 {</div><div class='add'>+				compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";</div><div class='add'>+				reg = &lt;0x29870000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;pcc4 IMX8ULP_CLK_LPUART7&gt;;</div><div class='add'>+				clock-names = "ipg";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sai4: sai@29880000 {</div><div class='add'>+				compatible = "fsl,imx8ulp-sai";</div><div class='add'>+				reg = &lt;0x29880000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;pcc4 IMX8ULP_CLK_SAI4&gt;, &lt;&amp;cgc1 IMX8ULP_CLK_DUMMY&gt;,</div><div class='add'>+					 &lt;&amp;cgc1 IMX8ULP_CLK_SAI4_SEL&gt;, &lt;&amp;cgc1 IMX8ULP_CLK_DUMMY&gt;,</div><div class='add'>+					 &lt;&amp;cgc1 IMX8ULP_CLK_DUMMY&gt;;</div><div class='add'>+				clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";</div><div class='add'>+				dmas = &lt;&amp;edma1 67 0 1&gt;, &lt;&amp;edma1 68 0 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+				fsl,dataline = &lt;0 0x03 0x03&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sai5: sai@29890000 {</div><div class='add'>+				compatible = "fsl,imx8ulp-sai";</div><div class='add'>+				reg = &lt;0x29890000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;pcc4 IMX8ULP_CLK_SAI5&gt;, &lt;&amp;cgc1 IMX8ULP_CLK_DUMMY&gt;,</div><div class='add'>+					 &lt;&amp;cgc1 IMX8ULP_CLK_SAI5_SEL&gt;, &lt;&amp;cgc1 IMX8ULP_CLK_DUMMY&gt;,</div><div class='add'>+					 &lt;&amp;cgc1 IMX8ULP_CLK_DUMMY&gt;;</div><div class='add'>+				clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";</div><div class='add'>+				dmas = &lt;&amp;edma1 69 0 1&gt;, &lt;&amp;edma1 70 0 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+				fsl,dataline = &lt;0 0x0f 0x0f&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			iomuxc1: pinctrl@298c0000 {</div><div class='add'>+				compatible = "fsl,imx8ulp-iomuxc1";</div><div class='add'>+				reg = &lt;0x298c0000 0x10000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			usdhc0: mmc@298d0000 {</div><div class='add'>+				compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";</div><div class='add'>+				reg = &lt;0x298d0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;cgc1 IMX8ULP_CLK_XBAR_DIVBUS&gt;,</div><div class='add'>+					 &lt;&amp;cgc1 IMX8ULP_CLK_XBAR_AD_DIVPLAT&gt;,</div><div class='add'>+					 &lt;&amp;pcc4 IMX8ULP_CLK_USDHC0&gt;;</div><div class='add'>+				clock-names = "ipg", "ahb", "per";</div><div class='add'>+				power-domains = &lt;&amp;scmi_devpd IMX8ULP_PD_USDHC0&gt;;</div><div class='add'>+				assigned-clocks = &lt;&amp;cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV1&gt;,</div><div class='add'>+						  &lt;&amp;pcc4 IMX8ULP_CLK_USDHC0&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;0&gt;, &lt;&amp;cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV1&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;389283840&gt;, &lt;389283840&gt;;</div><div class='add'>+				fsl,tuning-start-tap = &lt;20&gt;;</div><div class='add'>+				fsl,tuning-step = &lt;2&gt;;</div><div class='add'>+				bus-width = &lt;4&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			usdhc1: mmc@298e0000 {</div><div class='add'>+				compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";</div><div class='add'>+				reg = &lt;0x298e0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;cgc1 IMX8ULP_CLK_XBAR_DIVBUS&gt;,</div><div class='add'>+					 &lt;&amp;cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT&gt;,</div><div class='add'>+					 &lt;&amp;pcc4 IMX8ULP_CLK_USDHC1&gt;;</div><div class='add'>+				clock-names = "ipg", "ahb", "per";</div><div class='add'>+				power-domains = &lt;&amp;scmi_devpd IMX8ULP_PD_USDHC1&gt;;</div><div class='add'>+				assigned-clocks = &lt;&amp;cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2&gt;,</div><div class='add'>+						  &lt;&amp;pcc4 IMX8ULP_CLK_USDHC1&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;0&gt;, &lt;&amp;cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;194641920&gt;, &lt;194641920&gt;;</div><div class='add'>+				fsl,tuning-start-tap = &lt;20&gt;;</div><div class='add'>+				fsl,tuning-step = &lt;2&gt;;</div><div class='add'>+				bus-width = &lt;4&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			usdhc2: mmc@298f0000 {</div><div class='add'>+				compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";</div><div class='add'>+				reg = &lt;0x298f0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;cgc1 IMX8ULP_CLK_XBAR_DIVBUS&gt;,</div><div class='add'>+					 &lt;&amp;cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT&gt;,</div><div class='add'>+					 &lt;&amp;pcc4 IMX8ULP_CLK_USDHC2&gt;;</div><div class='add'>+				clock-names = "ipg", "ahb", "per";</div><div class='add'>+				power-domains = &lt;&amp;scmi_devpd IMX8ULP_PD_USDHC2_USB1&gt;;</div><div class='add'>+				assigned-clocks = &lt;&amp;cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2&gt;,</div><div class='add'>+						  &lt;&amp;pcc4 IMX8ULP_CLK_USDHC2&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;0&gt;, &lt;&amp;cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;194641920&gt;, &lt;194641920&gt;;</div><div class='add'>+				fsl,tuning-start-tap = &lt;20&gt;;</div><div class='add'>+				fsl,tuning-step = &lt;2&gt;;</div><div class='add'>+				bus-width = &lt;4&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			usbotg1: usb@29900000 {</div><div class='add'>+				compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb", "fsl,imx6ul-usb";</div><div class='add'>+				reg = &lt;0x29900000 0x200&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;pcc4 IMX8ULP_CLK_USB0&gt;;</div><div class='add'>+				power-domains = &lt;&amp;scmi_devpd IMX8ULP_PD_USB0&gt;;</div><div class='add'>+				phys = &lt;&amp;usbphy1&gt;;</div><div class='add'>+				fsl,usbmisc = &lt;&amp;usbmisc1 0&gt;;</div><div class='add'>+				ahb-burst-config = &lt;0x0&gt;;</div><div class='add'>+				tx-burst-size-dword = &lt;0x8&gt;;</div><div class='add'>+				rx-burst-size-dword = &lt;0x8&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			usbmisc1: usbmisc@29900200 {</div><div class='add'>+				compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7d-usbmisc",</div><div class='add'>+					     "fsl,imx6q-usbmisc";</div><div class='add'>+				reg = &lt;0x29900200 0x200&gt;;</div><div class='add'>+				#index-cells = &lt;1&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			usbphy1: usb-phy@29910000 {</div><div class='add'>+				compatible = "fsl,imx8ulp-usbphy", "fsl,imx7ulp-usbphy";</div><div class='add'>+				reg = &lt;0x29910000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;pcc4 IMX8ULP_CLK_USB0_PHY&gt;;</div><div class='add'>+				#phy-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			usbotg2: usb@29920000 {</div><div class='add'>+				compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb", "fsl,imx6ul-usb";</div><div class='add'>+				reg = &lt;0x29920000 0x200&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;pcc4 IMX8ULP_CLK_USB1&gt;;</div><div class='add'>+				power-domains = &lt;&amp;scmi_devpd IMX8ULP_PD_USDHC2_USB1&gt;;</div><div class='add'>+				phys = &lt;&amp;usbphy2&gt;;</div><div class='add'>+				fsl,usbmisc = &lt;&amp;usbmisc2 0&gt;;</div><div class='add'>+				ahb-burst-config = &lt;0x0&gt;;</div><div class='add'>+				tx-burst-size-dword = &lt;0x8&gt;;</div><div class='add'>+				rx-burst-size-dword = &lt;0x8&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			usbmisc2: usbmisc@29920200 {</div><div class='add'>+				compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7d-usbmisc",</div><div class='add'>+					     "fsl,imx6q-usbmisc";</div><div class='add'>+				reg = &lt;0x29920200 0x200&gt;;</div><div class='add'>+				#index-cells = &lt;1&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			usbphy2: usb-phy@29930000 {</div><div class='add'>+				compatible = "fsl,imx8ulp-usbphy", "fsl,imx7ulp-usbphy";</div><div class='add'>+				reg = &lt;0x29930000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;pcc4 IMX8ULP_CLK_USB1_PHY&gt;;</div><div class='add'>+				#phy-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			fec: ethernet@29950000 {</div><div class='add'>+				compatible = "fsl,imx8ulp-fec", "fsl,imx6ul-fec", "fsl,imx6q-fec";</div><div class='add'>+				reg = &lt;0x29950000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				interrupt-names = "int0";</div><div class='add'>+				fsl,num-tx-queues = &lt;1&gt;;</div><div class='add'>+				fsl,num-rx-queues = &lt;1&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpioe: gpio@2d000000 {</div><div class='add'>+				compatible = "fsl,imx8ulp-gpio";</div><div class='add'>+				reg = &lt;0x2d000000 0x1000&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;2&gt;;</div><div class='add'>+				clocks = &lt;&amp;pcc4 IMX8ULP_CLK_RGPIOE&gt;,</div><div class='add'>+					 &lt;&amp;pcc4 IMX8ULP_CLK_PCTLE&gt;;</div><div class='add'>+				clock-names = "gpio", "port";</div><div class='add'>+				gpio-ranges = &lt;&amp;iomuxc1 0 32 24&gt;;</div><div class='add'>+				ngpios = &lt;24&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpiof: gpio@2d010000 {</div><div class='add'>+				compatible = "fsl,imx8ulp-gpio";</div><div class='add'>+				reg = &lt;0x2d010000 0x1000&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;2&gt;;</div><div class='add'>+				clocks = &lt;&amp;pcc4 IMX8ULP_CLK_RGPIOF&gt;,</div><div class='add'>+					 &lt;&amp;pcc4 IMX8ULP_CLK_PCTLF&gt;;</div><div class='add'>+				clock-names = "gpio", "port";</div><div class='add'>+				gpio-ranges = &lt;&amp;iomuxc1 0 64 32&gt;;</div><div class='add'>+				ngpios = &lt;32&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		per_bridge5: bus@2d800000 {</div><div class='add'>+			compatible = "simple-bus";</div><div class='add'>+			reg = &lt;0x2d800000 0x800000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			edma2: dma-controller@2d800000 {</div><div class='add'>+				compatible = "fsl,imx8ulp-edma";</div><div class='add'>+				reg = &lt;0x2d800000 0x210000&gt;;</div><div class='add'>+				#dma-cells = &lt;3&gt;;</div><div class='add'>+				dma-channels = &lt;32&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;pcc5 IMX8ULP_CLK_DMA2_MP&gt;,</div><div class='add'>+					&lt;&amp;pcc5 IMX8ULP_CLK_DMA2_CH0&gt;, &lt;&amp;pcc5 IMX8ULP_CLK_DMA2_CH1&gt;,</div><div class='add'>+					&lt;&amp;pcc5 IMX8ULP_CLK_DMA2_CH2&gt;, &lt;&amp;pcc5 IMX8ULP_CLK_DMA2_CH3&gt;,</div><div class='add'>+					&lt;&amp;pcc5 IMX8ULP_CLK_DMA2_CH4&gt;, &lt;&amp;pcc5 IMX8ULP_CLK_DMA2_CH5&gt;,</div><div class='add'>+					&lt;&amp;pcc5 IMX8ULP_CLK_DMA2_CH6&gt;, &lt;&amp;pcc5 IMX8ULP_CLK_DMA2_CH7&gt;,</div><div class='add'>+					&lt;&amp;pcc5 IMX8ULP_CLK_DMA2_CH8&gt;, &lt;&amp;pcc5 IMX8ULP_CLK_DMA2_CH9&gt;,</div><div class='add'>+					&lt;&amp;pcc5 IMX8ULP_CLK_DMA2_CH10&gt;, &lt;&amp;pcc5 IMX8ULP_CLK_DMA2_CH11&gt;,</div><div class='add'>+					&lt;&amp;pcc5 IMX8ULP_CLK_DMA2_CH12&gt;, &lt;&amp;pcc5 IMX8ULP_CLK_DMA2_CH13&gt;,</div><div class='add'>+					&lt;&amp;pcc5 IMX8ULP_CLK_DMA2_CH14&gt;, &lt;&amp;pcc5 IMX8ULP_CLK_DMA2_CH15&gt;,</div><div class='add'>+					&lt;&amp;pcc5 IMX8ULP_CLK_DMA2_CH16&gt;, &lt;&amp;pcc5 IMX8ULP_CLK_DMA2_CH17&gt;,</div><div class='add'>+					&lt;&amp;pcc5 IMX8ULP_CLK_DMA2_CH18&gt;, &lt;&amp;pcc5 IMX8ULP_CLK_DMA2_CH19&gt;,</div><div class='add'>+					&lt;&amp;pcc5 IMX8ULP_CLK_DMA2_CH20&gt;, &lt;&amp;pcc5 IMX8ULP_CLK_DMA2_CH21&gt;,</div><div class='add'>+					&lt;&amp;pcc5 IMX8ULP_CLK_DMA2_CH22&gt;, &lt;&amp;pcc5 IMX8ULP_CLK_DMA2_CH23&gt;,</div><div class='add'>+					&lt;&amp;pcc5 IMX8ULP_CLK_DMA2_CH24&gt;, &lt;&amp;pcc5 IMX8ULP_CLK_DMA2_CH25&gt;,</div><div class='add'>+					&lt;&amp;pcc5 IMX8ULP_CLK_DMA2_CH26&gt;, &lt;&amp;pcc5 IMX8ULP_CLK_DMA2_CH27&gt;,</div><div class='add'>+					&lt;&amp;pcc5 IMX8ULP_CLK_DMA2_CH28&gt;, &lt;&amp;pcc5 IMX8ULP_CLK_DMA2_CH29&gt;,</div><div class='add'>+					&lt;&amp;pcc5 IMX8ULP_CLK_DMA2_CH30&gt;, &lt;&amp;pcc5 IMX8ULP_CLK_DMA2_CH31&gt;;</div><div class='add'>+				clock-names = "dma", "ch00","ch01", "ch02", "ch03",</div><div class='add'>+						"ch04", "ch05", "ch06", "ch07",</div><div class='add'>+						"ch08", "ch09", "ch10", "ch11",</div><div class='add'>+						"ch12", "ch13", "ch14", "ch15",</div><div class='add'>+						"ch16", "ch17", "ch18", "ch19",</div><div class='add'>+						"ch20", "ch21", "ch22", "ch23",</div><div class='add'>+						"ch24", "ch25", "ch26", "ch27",</div><div class='add'>+						"ch28", "ch29", "ch30", "ch31";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cgc2: clock-controller@2da60000 {</div><div class='add'>+				compatible = "fsl,imx8ulp-cgc2";</div><div class='add'>+				reg = &lt;0x2da60000 0x10000&gt;;</div><div class='add'>+				#clock-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pcc5: clock-controller@2da70000 {</div><div class='add'>+				compatible = "fsl,imx8ulp-pcc5";</div><div class='add'>+				reg = &lt;0x2da70000 0x10000&gt;;</div><div class='add'>+				#clock-cells = &lt;1&gt;;</div><div class='add'>+				#reset-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sai6: sai@2da90000 {</div><div class='add'>+				compatible = "fsl,imx8ulp-sai";</div><div class='add'>+				reg = &lt;0x2da90000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;pcc5 IMX8ULP_CLK_SAI6&gt;, &lt;&amp;cgc1 IMX8ULP_CLK_DUMMY&gt;,</div><div class='add'>+					 &lt;&amp;cgc2 IMX8ULP_CLK_SAI6_SEL&gt;, &lt;&amp;cgc1 IMX8ULP_CLK_DUMMY&gt;,</div><div class='add'>+					 &lt;&amp;cgc1 IMX8ULP_CLK_DUMMY&gt;;</div><div class='add'>+				clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";</div><div class='add'>+				dmas = &lt;&amp;edma2 71 0 1&gt;, &lt;&amp;edma2 72 0 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+				fsl,dataline = &lt;0 0x0f 0x0f&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sai7: sai@2daa0000 {</div><div class='add'>+				compatible = "fsl,imx8ulp-sai";</div><div class='add'>+				reg = &lt;0x2daa0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;pcc5 IMX8ULP_CLK_SAI7&gt;, &lt;&amp;cgc1 IMX8ULP_CLK_DUMMY&gt;,</div><div class='add'>+					 &lt;&amp;cgc2 IMX8ULP_CLK_SAI7_SEL&gt;, &lt;&amp;cgc1 IMX8ULP_CLK_DUMMY&gt;,</div><div class='add'>+					 &lt;&amp;cgc1 IMX8ULP_CLK_DUMMY&gt;;</div><div class='add'>+				clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";</div><div class='add'>+				dmas = &lt;&amp;edma2 73 0 1&gt;, &lt;&amp;edma2 74 0 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+				fsl,dataline = &lt;0 0x0f 0x0f&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spdif: spdif@2dab0000 {</div><div class='add'>+				compatible = "fsl,imx8ulp-spdif";</div><div class='add'>+				reg = &lt;0x2dab0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;pcc5 IMX8ULP_CLK_SPDIF&gt;, /* core */</div><div class='add'>+					 &lt;&amp;sosc&gt;, /* 0, extal */</div><div class='add'>+					 &lt;&amp;cgc2 IMX8ULP_CLK_SPDIF_SEL&gt;, /* 1, tx */</div><div class='add'>+					 &lt;&amp;cgc1 IMX8ULP_CLK_DUMMY&gt;, /* 2, tx1 */</div><div class='add'>+					 &lt;&amp;cgc1 IMX8ULP_CLK_DUMMY&gt;, /* 3, tx2 */</div><div class='add'>+					 &lt;&amp;cgc1 IMX8ULP_CLK_DUMMY&gt;, /* 4, tx3 */</div><div class='add'>+					 &lt;&amp;pcc5 IMX8ULP_CLK_SPDIF&gt;, /* 5, sys */</div><div class='add'>+					 &lt;&amp;cgc1 IMX8ULP_CLK_DUMMY&gt;, /* 6, tx4 */</div><div class='add'>+					 &lt;&amp;cgc1 IMX8ULP_CLK_DUMMY&gt;, /* 7, tx5 */</div><div class='add'>+					 &lt;&amp;cgc1 IMX8ULP_CLK_DUMMY&gt;; /* spba */</div><div class='add'>+				clock-names = "core", "rxtx0",</div><div class='add'>+					      "rxtx1", "rxtx2",</div><div class='add'>+					      "rxtx3", "rxtx4",</div><div class='add'>+					      "rxtx5", "rxtx6",</div><div class='add'>+					      "rxtx7", "spba";</div><div class='add'>+				dmas = &lt;&amp;edma2 75 0 5&gt;, &lt;&amp;edma2 76 0 4&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpiod: gpio@2e200000 {</div><div class='add'>+			compatible = "fsl,imx8ulp-gpio";</div><div class='add'>+			reg = &lt;0x2e200000 0x1000&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			clocks = &lt;&amp;pcc5 IMX8ULP_CLK_RGPIOD&gt;,</div><div class='add'>+				 &lt;&amp;pcc5 IMX8ULP_CLK_RGPIOD&gt;;</div><div class='add'>+			clock-names = "gpio", "port";</div><div class='add'>+			gpio-ranges = &lt;&amp;iomuxc1 0 0 24&gt;;</div><div class='add'>+			ngpios = &lt;24&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri-aster.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri-aster.dtsi<br/>new file mode 100644<br/>index 000000000000..f7bbb2153ae0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8x-colibri-aster.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8x-colibri-aster.dtsi</a></div><div class='hunk'>@@ -0,0 +1,80 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2018-2021 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/* Colibri Analogue Inputs */</div><div class='add'>+&amp;adc0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Colibri PWM_A */</div><div class='add'>+&amp;adma_pwm {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;colibri_gpio_keys {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;extcon_usbc_det {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Colibri Ethernet */</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hog0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Colibri SPI */</div><div class='add'>+&amp;lpspi2 {</div><div class='add'>+	cs-gpios = &lt;&amp;lsio_gpio1 0 GPIO_ACTIVE_LOW&gt;,</div><div class='add'>+		   &lt;&amp;lsio_gpio5 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Colibri UART_B */</div><div class='add'>+&amp;lpuart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Colibri UART_C */</div><div class='add'>+&amp;lpuart2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Colibri UART_A */</div><div class='add'>+&amp;lpuart3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB PHY for usbotg3 */</div><div class='add'>+&amp;usb3_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg3_cdns3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB PHY for usbotg1 */</div><div class='add'>+&amp;usbphy1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Colibri SDCard */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi<br/>new file mode 100644<br/>index 000000000000..f75499765d85<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi</a></div><div class='hunk'>@@ -0,0 +1,132 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2019 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/input/linux-event-codes.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		rtc0 = &amp;rtc_i2c;</div><div class='add'>+		rtc1 = &amp;rtc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* fixed crystal dedicated to mcp25xx */</div><div class='add'>+	clk16m: clock-16mhz {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;16000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Colibri Analogue Inputs */</div><div class='add'>+&amp;adc0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Colibri PWM_A */</div><div class='add'>+&amp;adma_pwm {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;colibri_gpio_keys {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;extcon_usbc_det {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* M41T0M6 real time clock on carrier board */</div><div class='add'>+	rtc_i2c: rtc@68 {</div><div class='add'>+		compatible = "st,m41t0";</div><div class='add'>+		reg = &lt;0x68&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ext_io0&gt;, &lt;&amp;pinctrl_hog0&gt;, &lt;&amp;pinctrl_hog1&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_lpspi2_cs2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Colibri SPI */</div><div class='add'>+&amp;lpspi2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mcp2515: can@0 {</div><div class='add'>+		compatible = "microchip,mcp2515";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;lsio_gpio3&gt;;</div><div class='add'>+		interrupts = &lt;13 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_can_int&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		clocks = &lt;&amp;clk16m&gt;;</div><div class='add'>+		spi-max-frequency = &lt;10000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Colibri UART_B */</div><div class='add'>+&amp;lpuart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Colibri UART_C */</div><div class='add'>+&amp;lpuart2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Colibri PWM_B */</div><div class='add'>+&amp;lsio_pwm0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Colibri PWM_C */</div><div class='add'>+&amp;lsio_pwm1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Colibri PWM_D */</div><div class='add'>+&amp;lsio_pwm2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Colibri UART_A */</div><div class='add'>+&amp;lpuart3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Colibri FastEthernet */</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB PHY for usbotg3 */</div><div class='add'>+&amp;usb3_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg3_cdns3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB PHY for usbotg1 */</div><div class='add'>+&amp;usbphy1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Colibri SD/MMC Card */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri-iris-v2.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri-iris-v2.dtsi<br/>new file mode 100644<br/>index 000000000000..58ec0b399c4f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8x-colibri-iris-v2.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8x-colibri-iris-v2.dtsi</a></div><div class='hunk'>@@ -0,0 +1,45 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2018-2021 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "imx8x-colibri-iris.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	reg_3v3_vmmc: regulator-3v3-vmmc {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_enable_3v3_vmmc&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;lsio_gpio0 31 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "3v3_vmmc";</div><div class='add'>+		startup-delay-us = &lt;100&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lvds_converter &amp;pinctrl_gpio_iris&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl_enable_3v3_vmmc: enable-3v3-vmmc-grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31	0x20&gt;;	/* SODIMM 100 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lvds_converter: lvds-converter-grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_FLEXCAN1_TX_LSIO_GPIO1_IO18		0x20&gt;,	/* SODIMM  55 */</div><div class='add'>+			   /* 6B/8B mode. Select LOW - 8B mode (24bit) */</div><div class='add'>+			   &lt;IMX8QXP_FLEXCAN1_RX_LSIO_GPIO1_IO17		0x20&gt;,	/* SODIMM  63 */</div><div class='add'>+			   &lt;IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17		0x20&gt;,	/* SODIMM  95 */</div><div class='add'>+			   &lt;IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18	0x20&gt;;	/* SODIMM  99 */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Colibri SD/MMC Card */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	cap-power-off-card;</div><div class='add'>+	/delete-property/ no-1-8-v;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_3v3_vmmc&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri-iris.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri-iris.dtsi<br/>new file mode 100644<br/>index 000000000000..54393a0c5cbf<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8x-colibri-iris.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8x-colibri-iris.dtsi</a></div><div class='hunk'>@@ -0,0 +1,150 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2018-2021 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		rtc0 = &amp;rtc_i2c;</div><div class='add'>+		rtc1 = &amp;rtc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3v3: regulator-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "3.3V";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Colibri Analogue Inputs */</div><div class='add'>+&amp;adc0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Colibri PWM_A */</div><div class='add'>+&amp;adma_pwm {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;colibri_gpio_keys {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;extcon_usbc_det {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Colibri FastEthernet */</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Colibri I2C */</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* M41T0M6 real time clock on carrier board */</div><div class='add'>+	rtc_i2c: rtc@68 {</div><div class='add'>+		compatible = "st,m41t0";</div><div class='add'>+		reg = &lt;0x68&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio_iris&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio_iris: gpioirisgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21	0x20&gt;,		/* SODIMM  98 */</div><div class='add'>+			   &lt;IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04		0x20&gt;,		/* SODIMM 133 */</div><div class='add'>+			   &lt;IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25		0x20&gt;,		/* SODIMM 103 */</div><div class='add'>+			   &lt;IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28		0x20&gt;,		/* SODIMM 101 */</div><div class='add'>+			   &lt;IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27		0x20&gt;,		/* SODIMM  97 */</div><div class='add'>+			   &lt;IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03	0x06000020&gt;,	/* SODIMM  85 */</div><div class='add'>+			   &lt;IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26		0x20&gt;;		/* SODIMM  79 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1_forceoff: uart1forceoffgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_QSPI0A_SS0_B_LSIO_GPIO3_IO14	0x20&gt;;	/* SODIMM 22 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart23_forceoff: uart23forceoffgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00	0x20&gt;; /* SODIMM 23 */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Colibri SPI */</div><div class='add'>+&amp;lpspi2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Colibri UART_B */</div><div class='add'>+&amp;lpuart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Colibri UART_C */</div><div class='add'>+&amp;lpuart2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Colibri UART_A */</div><div class='add'>+&amp;lpuart3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio3 {</div><div class='add'>+	/*</div><div class='add'>+	 * This turns the LVDS transceiver on. If one wants to turn the</div><div class='add'>+	 * transceiver off, that property has to be deleted and the gpio handled</div><div class='add'>+	 * in userspace.</div><div class='add'>+	 */</div><div class='add'>+	lvds-tx-on-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;18 0&gt;;</div><div class='add'>+		output-high;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Colibri PWM_B */</div><div class='add'>+&amp;lsio_pwm0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Colibri PWM_C */</div><div class='add'>+&amp;lsio_pwm1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Colibri PWM_D */</div><div class='add'>+&amp;lsio_pwm2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB PHY for usbotg3 */</div><div class='add'>+&amp;usb3_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg3_cdns3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB PHY for usbotg1 */</div><div class='add'>+&amp;usbphy1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Colibri SD/MMC Card */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi<br/>new file mode 100644<br/>index 000000000000..8e9e841cc828<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi</a></div><div class='hunk'>@@ -0,0 +1,999 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2019 Toradex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;lpuart3;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	colibri_gpio_keys: gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpiokeys&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+</div><div class='add'>+		key-wakeup {</div><div class='add'>+			debounce-interval = &lt;10&gt;;</div><div class='add'>+			gpios = &lt;&amp;lsio_gpio3 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			label = "Wake-Up";</div><div class='add'>+			linux,code = &lt;KEY_WAKEUP&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	extcon_usbc_det: usbc-det {</div><div class='add'>+		compatible = "linux,extcon-usb-gpio";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usbc_det&gt;;</div><div class='add'>+		id-gpios = &lt;&amp;lsio_gpio5 9 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_module_3v3: regulator-module-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "+V3.3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_module_3v3_avdd: regulator-module-3v3-avdd {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "+V3.3_AVDD_AUDIO";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_module_vref_1v8: regulator-module-vref-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-name = "vref-1v8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_module_wifi: regulator-module-wifi {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		gpio = &lt;&amp;gpio_expander_43 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-name = "Wi-Fi_PDn";</div><div class='add'>+		startup-delay-us = &lt;2000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usbh_vbus: regulator-usbh-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usbh1_reg&gt;;</div><div class='add'>+		gpio = &lt;&amp;lsio_gpio4 3 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-name = "usbh_vbus";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-card {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,bitclock-master = &lt;&amp;dailink_master&gt;;</div><div class='add'>+		simple-audio-card,format = "i2s";</div><div class='add'>+		simple-audio-card,frame-master = &lt;&amp;dailink_master&gt;;</div><div class='add'>+		simple-audio-card,name = "colibri-imx8x";</div><div class='add'>+</div><div class='add'>+		dailink_master: simple-audio-card,codec {</div><div class='add'>+			clocks = &lt;&amp;mclkout0_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+			sound-dai = &lt;&amp;sgtl5000_a&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;sai0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Colibri Analogue Inputs */</div><div class='add'>+&amp;adc0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_adc0&gt;;</div><div class='add'>+	vref-supply = &lt;&amp;reg_module_vref_1v8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Colibri PWM_A */</div><div class='add'>+&amp;adma_pwm {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm_a&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu_alert0 {</div><div class='add'>+	hysteresis = &lt;2000&gt;;</div><div class='add'>+	temperature = &lt;90000&gt;;</div><div class='add'>+	type = "passive";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu_crit0 {</div><div class='add'>+	hysteresis = &lt;2000&gt;;</div><div class='add'>+	temperature = &lt;105000&gt;;</div><div class='add'>+	type = "critical";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;enet0_lpcg {</div><div class='add'>+	clocks = &lt;&amp;clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER&gt;,</div><div class='add'>+		 &lt;&amp;conn_axi_clk&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX_SC_R_ENET_0 IMX_SC_C_DISABLE_50&gt;,</div><div class='add'>+		 &lt;&amp;conn_ipg_clk&gt;,</div><div class='add'>+		 &lt;&amp;conn_ipg_clk&gt;;</div><div class='add'>+	clock-output-names = "enet0_lpcg_timer_clk",</div><div class='add'>+			     "enet0_lpcg_txc_sampling_clk",</div><div class='add'>+			     "enet0_lpcg_ahb_clk",</div><div class='add'>+			     "enet0_lpcg_ref_50mhz_clk",</div><div class='add'>+			     "enet0_lpcg_ipg_clk",</div><div class='add'>+			     "enet0_lpcg_ipg_s_clk";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* On-module I2C */</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c0&gt;, &lt;&amp;pinctrl_sgtl5000_usb_clk&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* USB HUB USB3803 */</div><div class='add'>+	usb-hub@8 {</div><div class='add'>+		compatible = "smsc,usb3803";</div><div class='add'>+		reg = &lt;0x8&gt;;</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL&gt;,</div><div class='add'>+				  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS&gt;,</div><div class='add'>+				  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS&gt;,</div><div class='add'>+				  &lt;&amp;mclkout0_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;786432000&gt;, &lt;49152000&gt;, &lt;12000000&gt;, &lt;12000000&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usb3503a&gt;;</div><div class='add'>+		bypass-gpios = &lt;&amp;gpio_expander_43 5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		clocks = &lt;&amp;mclkout0_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		clock-names = "refclk";</div><div class='add'>+		disabled-ports = &lt;2&gt;;</div><div class='add'>+		initial-mode = &lt;1&gt;;</div><div class='add'>+		intn-gpios = &lt;&amp;lsio_gpio3 4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio_expander_43 4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sgtl5000_a: audio-codec@a {</div><div class='add'>+		compatible = "fsl,sgtl5000";</div><div class='add'>+		reg = &lt;0xa&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		assigned-clocks = &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL&gt;,</div><div class='add'>+				  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS&gt;,</div><div class='add'>+				  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS&gt;,</div><div class='add'>+				  &lt;&amp;mclkout0_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;786432000&gt;, &lt;49152000&gt;, &lt;12000000&gt;, &lt;12000000&gt;;</div><div class='add'>+		clocks = &lt;&amp;mclkout0_lpcg IMX_LPCG_CLK_0&gt;;</div><div class='add'>+		VDDA-supply = &lt;&amp;reg_module_3v3_avdd&gt;;</div><div class='add'>+		VDDD-supply = &lt;&amp;reg_module_vref_1v8&gt;;</div><div class='add'>+		VDDIO-supply = &lt;&amp;reg_module_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Touch controller */</div><div class='add'>+	ad7879_ts: touchscreen@2c {</div><div class='add'>+		compatible = "adi,ad7879-1";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_ad7879_int&gt;;</div><div class='add'>+		reg = &lt;0x2c&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;lsio_gpio3&gt;;</div><div class='add'>+		interrupts = &lt;5 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		touchscreen-max-pressure = &lt;4096&gt;;</div><div class='add'>+		adi,resistance-plate-x = &lt;120&gt;;</div><div class='add'>+		adi,first-conversion-delay = /bits/ 8 &lt;3&gt;;</div><div class='add'>+		adi,acquisition-time = /bits/ 8 &lt;1&gt;;</div><div class='add'>+		adi,median-filter-size = /bits/ 8 &lt;2&gt;;</div><div class='add'>+		adi,averaging = /bits/ 8 &lt;1&gt;;</div><div class='add'>+		adi,conversion-interval = /bits/ 8 &lt;255&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio_expander_43: gpio@43 {</div><div class='add'>+		compatible = "fcs,fxl6408";</div><div class='add'>+		reg = &lt;0x43&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-line-names = "Wi-Fi_W_DISABLE",</div><div class='add'>+				  "Wi-Fi_WKUP_WLAN",</div><div class='add'>+				  "PWR_EN_+V3.3_WiFi_N",</div><div class='add'>+				  "PCIe_REF_CLK_EN",</div><div class='add'>+				  "USB_RESET_N",</div><div class='add'>+				  "USB_BYPASS_N",</div><div class='add'>+				  "Wi-Fi_PDn",</div><div class='add'>+				  "Wi-Fi_WKUP_BT";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* TODO i2c lvds0 accessible on FFC (X2) */</div><div class='add'>+</div><div class='add'>+/* TODO i2c lvds1 accessible on FFC (X3) */</div><div class='add'>+</div><div class='add'>+/* Colibri I2C */</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;jpegdec {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;jpegenc {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* TODO Parallel RRB */</div><div class='add'>+</div><div class='add'>+/* Colibri UART_B */</div><div class='add'>+&amp;lpuart0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpuart0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Colibri UART_C */</div><div class='add'>+&amp;lpuart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpuart2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Colibri UART_A */</div><div class='add'>+&amp;lpuart3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpuart3&gt;, &lt;&amp;pinctrl_lpuart3_ctrl&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Colibri FastEthernet */</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_fec1_sleep&gt;;</div><div class='add'>+	phy-mode = "rmii";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	fsl,magic-packet;</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@2 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			max-speed = &lt;100&gt;;</div><div class='add'>+			reg = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hsio_phy {</div><div class='add'>+	fsl,hsio-cfg = "pciea-x2-pcieb";</div><div class='add'>+	fsl,refclk-pad-mode = "input";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hsio_refb_clk {</div><div class='add'>+	enable-gpios = &lt;&amp;gpio_expander_43 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Colibri SPI */</div><div class='add'>+&amp;lpspi2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpspi2&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;lsio_gpio1 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio0 {</div><div class='add'>+	gpio-line-names = "",</div><div class='add'>+			  "SODIMM_70",</div><div class='add'>+			  "SODIMM_60",</div><div class='add'>+			  "SODIMM_58",</div><div class='add'>+			  "SODIMM_78",</div><div class='add'>+			  "SODIMM_72",</div><div class='add'>+			  "SODIMM_80",</div><div class='add'>+			  "SODIMM_46",</div><div class='add'>+			  "SODIMM_62",</div><div class='add'>+			  "SODIMM_48",</div><div class='add'>+			  "SODIMM_74",</div><div class='add'>+			  "SODIMM_50",</div><div class='add'>+			  "SODIMM_52",</div><div class='add'>+			  "SODIMM_54",</div><div class='add'>+			  "SODIMM_66",</div><div class='add'>+			  "SODIMM_64",</div><div class='add'>+			  "SODIMM_68",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "SODIMM_82",</div><div class='add'>+			  "SODIMM_56",</div><div class='add'>+			  "SODIMM_28",</div><div class='add'>+			  "SODIMM_30",</div><div class='add'>+			  "",</div><div class='add'>+			  "SODIMM_61",</div><div class='add'>+			  "SODIMM_103",</div><div class='add'>+			  "SODIMM_79",</div><div class='add'>+			  "SODIMM_97",</div><div class='add'>+			  "",</div><div class='add'>+			  "SODIMM_25",</div><div class='add'>+			  "SODIMM_27",</div><div class='add'>+			  "SODIMM_100";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio1 {</div><div class='add'>+	gpio-line-names = "SODIMM_86",</div><div class='add'>+			  "SODIMM_92",</div><div class='add'>+			  "SODIMM_90",</div><div class='add'>+			  "SODIMM_88",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "SODIMM_59",</div><div class='add'>+			  "",</div><div class='add'>+			  "SODIMM_6",</div><div class='add'>+			  "SODIMM_8",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "SODIMM_2",</div><div class='add'>+			  "SODIMM_4",</div><div class='add'>+			  "SODIMM_34",</div><div class='add'>+			  "SODIMM_32",</div><div class='add'>+			  "SODIMM_63",</div><div class='add'>+			  "SODIMM_55",</div><div class='add'>+			  "SODIMM_33",</div><div class='add'>+			  "SODIMM_35",</div><div class='add'>+			  "SODIMM_36",</div><div class='add'>+			  "SODIMM_38",</div><div class='add'>+			  "SODIMM_21",</div><div class='add'>+			  "SODIMM_19",</div><div class='add'>+			  "SODIMM_140",</div><div class='add'>+			  "SODIMM_142",</div><div class='add'>+			  "SODIMM_196",</div><div class='add'>+			  "SODIMM_194",</div><div class='add'>+			  "SODIMM_186",</div><div class='add'>+			  "SODIMM_188",</div><div class='add'>+			  "SODIMM_138";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio2 {</div><div class='add'>+	gpio-line-names = "SODIMM_23",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "SODIMM_144";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio3 {</div><div class='add'>+	gpio-line-names = "SODIMM_96",</div><div class='add'>+			  "SODIMM_75",</div><div class='add'>+			  "SODIMM_37",</div><div class='add'>+			  "SODIMM_29",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "SODIMM_43",</div><div class='add'>+			  "SODIMM_45",</div><div class='add'>+			  "SODIMM_69",</div><div class='add'>+			  "SODIMM_71",</div><div class='add'>+			  "SODIMM_73",</div><div class='add'>+			  "SODIMM_77",</div><div class='add'>+			  "SODIMM_89",</div><div class='add'>+			  "SODIMM_93",</div><div class='add'>+			  "SODIMM_95",</div><div class='add'>+			  "SODIMM_99",</div><div class='add'>+			  "SODIMM_105",</div><div class='add'>+			  "SODIMM_107",</div><div class='add'>+			  "SODIMM_98",</div><div class='add'>+			  "SODIMM_102",</div><div class='add'>+			  "SODIMM_104",</div><div class='add'>+			  "SODIMM_106";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio4 {</div><div class='add'>+	gpio-line-names = "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "SODIMM_129",</div><div class='add'>+			  "SODIMM_133",</div><div class='add'>+			  "SODIMM_127",</div><div class='add'>+			  "SODIMM_131",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "SODIMM_44",</div><div class='add'>+			  "",</div><div class='add'>+			  "SODIMM_76",</div><div class='add'>+			  "SODIMM_31",</div><div class='add'>+			  "SODIMM_47",</div><div class='add'>+			  "SODIMM_190",</div><div class='add'>+			  "SODIMM_192",</div><div class='add'>+			  "SODIMM_49",</div><div class='add'>+			  "SODIMM_51",</div><div class='add'>+			  "SODIMM_53";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio5 {</div><div class='add'>+	gpio-line-names = "",</div><div class='add'>+			  "SODIMM_57",</div><div class='add'>+			  "SODIMM_65",</div><div class='add'>+			  "SODIMM_85",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "SODIMM_135",</div><div class='add'>+			  "SODIMM_137",</div><div class='add'>+			  "UNUSABLE_SODIMM_180",</div><div class='add'>+			  "UNUSABLE_SODIMM_184";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Colibri PWM_B */</div><div class='add'>+&amp;lsio_pwm0 {</div><div class='add'>+	#pwm-cells = &lt;3&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm_b&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Colibri PWM_C */</div><div class='add'>+&amp;lsio_pwm1 {</div><div class='add'>+	#pwm-cells = &lt;3&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm_c&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Colibri PWM_D */</div><div class='add'>+&amp;lsio_pwm2 {</div><div class='add'>+	#pwm-cells = &lt;3&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm_d&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* VPU Mailboxes */</div><div class='add'>+&amp;mu_m0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mu1_m0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* TODO MIPI CSI */</div><div class='add'>+</div><div class='add'>+/* TODO MIPI DSI with DSI-to-HDMI bridge lt8912 */</div><div class='add'>+</div><div class='add'>+/* On-module PCIe for Wi-Fi */</div><div class='add'>+&amp;pcieb {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcieb&gt;;</div><div class='add'>+	phys = &lt;&amp;hsio_phy 0 PHY_TYPE_PCIE 0&gt;;</div><div class='add'>+	phy-names = "pcie-phy";</div><div class='add'>+	reset-gpios = &lt;&amp;lsio_gpio4 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* On-module I2S */</div><div class='add'>+&amp;sai0 {</div><div class='add'>+	#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;thermal_zones {</div><div class='add'>+	pmic-thermal {</div><div class='add'>+		polling-delay-passive = &lt;250&gt;;</div><div class='add'>+		polling-delay = &lt;2000&gt;;</div><div class='add'>+		thermal-sensors = &lt;&amp;tsens IMX_SC_R_PMIC_0&gt;;</div><div class='add'>+</div><div class='add'>+		trips {</div><div class='add'>+			pmic_alert0: trip0 {</div><div class='add'>+				temperature = &lt;110000&gt;;</div><div class='add'>+				hysteresis = &lt;2000&gt;;</div><div class='add'>+				type = "passive";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pmic_crit0: trip1 {</div><div class='add'>+				temperature = &lt;125000&gt;;</div><div class='add'>+				hysteresis = &lt;2000&gt;;</div><div class='add'>+				type = "critical";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cooling-maps {</div><div class='add'>+			pmic_cooling_map0: map0 {</div><div class='add'>+				trip = &lt;&amp;pmic_alert0&gt;;</div><div class='add'>+				cooling-device = &lt;&amp;A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+						 &lt;&amp;A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+						 &lt;&amp;A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+						 &lt;&amp;A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	adp-disable;</div><div class='add'>+	disable-over-current;</div><div class='add'>+	extcon = &lt;&amp;extcon_usbc_det &amp;extcon_usbc_det&gt;;</div><div class='add'>+	hnp-disable;</div><div class='add'>+	power-active-high;</div><div class='add'>+	srp-disable;</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usbh_vbus&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg3_cdns3 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* On-module eMMC */</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	no-sd;</div><div class='add'>+	no-sdio;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1_200mhz&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Colibri SD/MMC Card */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;lsio_gpio3 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_module_3v3&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-3 = &lt;&amp;pinctrl_usdhc2_sleep&gt;, &lt;&amp;pinctrl_usdhc2_gpio_sleep&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+	no-1-8-v;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;vpu {</div><div class='add'>+	compatible = "nxp,imx8qxp-vpu";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* VPU Decoder */</div><div class='add'>+&amp;vpu_core0 {</div><div class='add'>+	reg = &lt;0x2d040000 0x10000&gt;;</div><div class='add'>+	memory-region = &lt;&amp;decoder_boot&gt;, &lt;&amp;decoder_rpc&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* VPU Encoder */</div><div class='add'>+&amp;vpu_core1 {</div><div class='add'>+	reg = &lt;0x2d050000 0x10000&gt;;</div><div class='add'>+	memory-region = &lt;&amp;encoder_boot&gt;, &lt;&amp;encoder_rpc&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	/* On-module touch pen-down interrupt */</div><div class='add'>+	pinctrl_ad7879_int: ad7879intgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05	0x21&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Colibri Analogue Inputs */</div><div class='add'>+	pinctrl_adc0: adc0grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_ADC_IN0_ADMA_ADC_IN0			0x60&gt;,		/* SODIMM   8 */</div><div class='add'>+			   &lt;IMX8QXP_ADC_IN1_ADMA_ADC_IN1			0x60&gt;,		/* SODIMM   6 */</div><div class='add'>+			   &lt;IMX8QXP_ADC_IN4_ADMA_ADC_IN4			0x60&gt;,		/* SODIMM   4 */</div><div class='add'>+			   &lt;IMX8QXP_ADC_IN5_ADMA_ADC_IN5			0x60&gt;;		/* SODIMM   2 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Atmel MXT touchsceen + Capacitive Touch Adapter */</div><div class='add'>+	/* NOTE: This pingroup conflicts with pingroups</div><div class='add'>+	 * pinctrl_pwm_b/pinctrl_pwm_c. Don't enable them</div><div class='add'>+	 * simultaneously.</div><div class='add'>+	 */</div><div class='add'>+	pinctrl_atmel_adap: atmeladaptergrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_UART1_RX_LSIO_GPIO0_IO22			0x21&gt;,		/* SODIMM  30 */</div><div class='add'>+			   &lt;IMX8QXP_UART1_TX_LSIO_GPIO0_IO21			0x4000021&gt;;	/* SODIMM  28 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Atmel MXT touchsceen + boards with built-in Capacitive Touch Connector */</div><div class='add'>+	pinctrl_atmel_conn: atmelconnectorgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20		0x4000021&gt;,	/* SODIMM 107 */</div><div class='add'>+			   &lt;IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24		0x21&gt;;		/* SODIMM 106 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_can_int: canintgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_QSPI0A_DQS_LSIO_GPIO3_IO13			0x40&gt;;		/* SODIMM  73 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_csi_ctl: csictlgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_QSPI0A_SS0_B_LSIO_GPIO3_IO14		0x20&gt;,		/* SODIMM  77 */</div><div class='add'>+			   &lt;IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15		0x20&gt;;		/* SODIMM  89 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_csi_mclk: csimclkgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_CSI_MCLK_CI_PI_MCLK				0xC0000041&gt;;	/* SODIMM  75 / X3-12 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ext_io0: extio0grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08		0x06000040&gt;;	/* SODIMM 135 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Colibri Ethernet: On-module 100Mbps PHY Micrel KSZ8041 */</div><div class='add'>+	pinctrl_fec1: fec1grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_ENET0_MDC_CONN_ENET0_MDC			0x06000020&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x61&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT	0x06000061&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x61&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x61&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x61&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x61&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x61&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER	0x61&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec1_sleep: fec1slpgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_ENET0_MDC_LSIO_GPIO5_IO11			0x06000041&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ENET0_MDIO_LSIO_GPIO5_IO10			0x06000041&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30		0x41&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ENET0_RGMII_TXC_LSIO_GPIO4_IO29		0x41&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31		0x41&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00		0x41&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04		0x41&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05		0x41&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06		0x41&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07		0x41&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Colibri optional CAN on UART_B RTS/CTS */</div><div class='add'>+	pinctrl_flexcan1: flexcan0grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX		0x21&gt;,		/* SODIMM  32 */</div><div class='add'>+			   &lt;IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX		0x21&gt;;		/* SODIMM  34 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Colibri optional CAN on PS2 */</div><div class='add'>+	pinctrl_flexcan2: flexcan1grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX		0x21&gt;,		/* SODIMM  55 */</div><div class='add'>+			   &lt;IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX		0x21&gt;;		/* SODIMM  63 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Colibri optional CAN on UART_A TXD/RXD */</div><div class='add'>+	pinctrl_flexcan3: flexcan2grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX		0x21&gt;,		/* SODIMM  35 */</div><div class='add'>+			   &lt;IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX		0x21&gt;;		/* SODIMM  33 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Colibri LCD Back-Light GPIO */</div><div class='add'>+	pinctrl_gpio_bl_on: gpioblongrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_QSPI0A_DATA3_LSIO_GPIO3_IO12		0x60&gt;;		/* SODIMM  71 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* HDMI Hot Plug Detect on FFC (X2) */</div><div class='add'>+	pinctrl_gpio_hpd: gpiohpdgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31		0x20&gt;;		/* SODIMM 138 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpiokeys: gpiokeysgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_QSPI0A_DATA1_LSIO_GPIO3_IO10		0x06700041&gt;;	/* SODIMM  45 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_hog0: hog0grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_CSI_D07_CI_PI_D09				0x61&gt;,		/* SODIMM  65 */</div><div class='add'>+			   &lt;IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11		0x20&gt;,		/* SODIMM  69 */</div><div class='add'>+			   &lt;IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26			0x20&gt;,		/* SODIMM  79 */</div><div class='add'>+			   &lt;IMX8QXP_CSI_D02_CI_PI_D04				0x61&gt;,		/* SODIMM  79 */</div><div class='add'>+			   &lt;IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03		0x06000020&gt;,	/* SODIMM  85 */</div><div class='add'>+			   &lt;IMX8QXP_CSI_D06_CI_PI_D08				0x61&gt;,		/* SODIMM  85 */</div><div class='add'>+			   &lt;IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17			0x20&gt;,		/* SODIMM  95 */</div><div class='add'>+			   &lt;IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27			0x20&gt;,		/* SODIMM  97 */</div><div class='add'>+			   &lt;IMX8QXP_CSI_D03_CI_PI_D05				0x61&gt;,		/* SODIMM  97 */</div><div class='add'>+			   &lt;IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18		0x20&gt;,		/* SODIMM  99 */</div><div class='add'>+			   &lt;IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28			0x20&gt;,		/* SODIMM 101 */</div><div class='add'>+			   &lt;IMX8QXP_CSI_D00_CI_PI_D02				0x61&gt;,		/* SODIMM 101 */</div><div class='add'>+			   &lt;IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25			0x20&gt;,		/* SODIMM 103 */</div><div class='add'>+			   &lt;IMX8QXP_CSI_D01_CI_PI_D03				0x61&gt;,		/* SODIMM 103 */</div><div class='add'>+			   &lt;IMX8QXP_QSPI0B_DATA1_LSIO_GPIO3_IO19		0x20&gt;,		/* SODIMM 105 */</div><div class='add'>+			   &lt;IMX8QXP_USB_SS3_TC2_LSIO_GPIO4_IO05			0x20&gt;,		/* SODIMM 127 */</div><div class='add'>+			   &lt;IMX8QXP_USB_SS3_TC3_LSIO_GPIO4_IO06			0x20&gt;,		/* SODIMM 131 */</div><div class='add'>+			   &lt;IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04			0x20&gt;,		/* SODIMM 133 */</div><div class='add'>+			   &lt;IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00			0x20&gt;,		/* SODIMM  96 */</div><div class='add'>+			   &lt;IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21		0x20&gt;,		/* SODIMM  98 */</div><div class='add'>+			   &lt;IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31			0x20&gt;,		/* SODIMM 100 */</div><div class='add'>+			   &lt;IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22			0x20&gt;,		/* SODIMM 102 */</div><div class='add'>+			   &lt;IMX8QXP_QSPI0B_SS0_B_LSIO_GPIO3_IO23		0x20&gt;;		/* SODIMM 104 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_hog1: hog1grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_QSPI0A_SCLK_LSIO_GPIO3_IO16			0x20&gt;;		/* SODIMM  93 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_hog2: hog2grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01			0x20&gt;;		/* SODIMM  75 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * This pin is used in the SCFW as a UART. Using it from</div><div class='add'>+	 * Linux would require rewriting the SCFW board file.</div><div class='add'>+	 */</div><div class='add'>+	pinctrl_hog_scfw: hogscfwgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_SCU_GPIO0_00_LSIO_GPIO2_IO03		0x20&gt;;		/* SODIMM 144 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* On Module I2C */</div><div class='add'>+	pinctrl_i2c0: i2c0grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL		0x06000021&gt;,</div><div class='add'>+			   &lt;IMX8QXP_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA		0x06000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* MIPI DSI I2C accessible on SODIMM (X1) and FFC (X2) */</div><div class='add'>+	pinctrl_i2c0_mipi_lvds0: i2c0mipilvds0grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL	0xc6000020&gt;,	/* SODIMM 140 */</div><div class='add'>+			   &lt;IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA	0xc6000020&gt;;	/* SODIMM 142 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* MIPI CSI I2C accessible on SODIMM (X1) and FFC (X3) */</div><div class='add'>+	pinctrl_i2c0_mipi_lvds1: i2c0mipilvds1grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL	0xc6000020&gt;,	/* SODIMM 186 */</div><div class='add'>+			   &lt;IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA	0xc6000020&gt;;	/* SODIMM 188 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Colibri I2C */</div><div class='add'>+	pinctrl_i2c1: i2c1grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL		0x06000021&gt;,	/* SODIMM 196 */</div><div class='add'>+			   &lt;IMX8QXP_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA		0x06000021&gt;;	/* SODIMM 194 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Colibri Parallel RGB LCD Interface */</div><div class='add'>+	pinctrl_lcdif: lcdifgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK			0x60&gt;,		/* SODIMM  56 */</div><div class='add'>+			   &lt;IMX8QXP_SPI3_CS0_ADMA_LCDIF_HSYNC			0x60&gt;,		/* SODIMM  68 */</div><div class='add'>+			   &lt;IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC			0x60&gt;,		/* SODIMM  82 */</div><div class='add'>+			   &lt;IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN			0x40&gt;,		/* SODIMM  44 */</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19		0x40&gt;,		/* SODIMM  44 */</div><div class='add'>+			   &lt;IMX8QXP_ESAI0_FSR_ADMA_LCDIF_D00			0x60&gt;,		/* SODIMM  76 */</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21			0x60&gt;,		/* SODIMM  76 */</div><div class='add'>+			   &lt;IMX8QXP_ESAI0_FST_ADMA_LCDIF_D01			0x60&gt;,		/* SODIMM  70 */</div><div class='add'>+			   &lt;IMX8QXP_ESAI0_SCKR_ADMA_LCDIF_D02			0x60&gt;,		/* SODIMM  60 */</div><div class='add'>+			   &lt;IMX8QXP_ESAI0_SCKT_ADMA_LCDIF_D03			0x60&gt;,		/* SODIMM  58 */</div><div class='add'>+			   &lt;IMX8QXP_ESAI0_TX0_ADMA_LCDIF_D04			0x60&gt;,		/* SODIMM  78 */</div><div class='add'>+			   &lt;IMX8QXP_ESAI0_TX1_ADMA_LCDIF_D05			0x60&gt;,		/* SODIMM  72 */</div><div class='add'>+			   &lt;IMX8QXP_ESAI0_TX2_RX3_ADMA_LCDIF_D06		0x60&gt;,		/* SODIMM  80 */</div><div class='add'>+			   &lt;IMX8QXP_ESAI0_TX3_RX2_ADMA_LCDIF_D07		0x60&gt;,		/* SODIMM  46 */</div><div class='add'>+			   &lt;IMX8QXP_ESAI0_TX4_RX1_ADMA_LCDIF_D08		0x60&gt;,		/* SODIMM  62 */</div><div class='add'>+			   &lt;IMX8QXP_ESAI0_TX5_RX0_ADMA_LCDIF_D09		0x60&gt;,		/* SODIMM  48 */</div><div class='add'>+			   &lt;IMX8QXP_SPDIF0_RX_ADMA_LCDIF_D10			0x60&gt;,		/* SODIMM  74 */</div><div class='add'>+			   &lt;IMX8QXP_SPDIF0_TX_ADMA_LCDIF_D11			0x60&gt;,		/* SODIMM  50 */</div><div class='add'>+			   &lt;IMX8QXP_SPDIF0_EXT_CLK_ADMA_LCDIF_D12		0x60&gt;,		/* SODIMM  52 */</div><div class='add'>+			   &lt;IMX8QXP_SPI3_SCK_ADMA_LCDIF_D13			0x60&gt;,		/* SODIMM  54 */</div><div class='add'>+			   &lt;IMX8QXP_SPI3_SDO_ADMA_LCDIF_D14			0x60&gt;,		/* SODIMM  66 */</div><div class='add'>+			   &lt;IMX8QXP_SPI3_SDI_ADMA_LCDIF_D15			0x60&gt;,		/* SODIMM  64 */</div><div class='add'>+			   &lt;IMX8QXP_SPI3_CS1_ADMA_LCDIF_D16			0x60&gt;,		/* SODIMM  57 */</div><div class='add'>+			   &lt;IMX8QXP_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01		0x60&gt;,		/* SODIMM  57 */</div><div class='add'>+			   &lt;IMX8QXP_UART1_CTS_B_ADMA_LCDIF_D17			0x60&gt;;		/* SODIMM  61 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Colibri SPI */</div><div class='add'>+	pinctrl_lpspi2: lpspi2grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00			0x21&gt;,		/* SODIMM  86 */</div><div class='add'>+			   &lt;IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO			0x06000040&gt;,	/* SODIMM  92 */</div><div class='add'>+			   &lt;IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI			0x06000040&gt;,	/* SODIMM  90 */</div><div class='add'>+			   &lt;IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK			0x06000040&gt;;	/* SODIMM  88 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpspi2_cs2: lpspi2cs2grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02		0x21&gt;;		/* SODIMM  65 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Colibri UART_B */</div><div class='add'>+	pinctrl_lpuart0: lpuart0grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_UART0_RX_ADMA_UART0_RX			0x06000020&gt;,	/* SODIMM  36 */</div><div class='add'>+			   &lt;IMX8QXP_UART0_TX_ADMA_UART0_TX			0x06000020&gt;,	/* SODIMM  38 */</div><div class='add'>+			   &lt;IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B		0x06000020&gt;,	/* SODIMM  34 */</div><div class='add'>+			   &lt;IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B		0x06000020&gt;;	/* SODIMM  32 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Colibri UART_C */</div><div class='add'>+	pinctrl_lpuart2: lpuart2grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_UART2_RX_ADMA_UART2_RX			0x06000020&gt;,	/* SODIMM  19 */</div><div class='add'>+			   &lt;IMX8QXP_UART2_TX_ADMA_UART2_TX			0x06000020&gt;;	/* SODIMM  21 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Colibri UART_A */</div><div class='add'>+	pinctrl_lpuart3: lpuart3grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX			0x06000020&gt;,	/* SODIMM  33 */</div><div class='add'>+			   &lt;IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX			0x06000020&gt;;	/* SODIMM  35 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Colibri UART_A Control */</div><div class='add'>+	pinctrl_lpuart3_ctrl: lpuart3ctrlgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00		0x20&gt;,		/* SODIMM  23 */</div><div class='add'>+			   &lt;IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29			0x20&gt;,		/* SODIMM  25 */</div><div class='add'>+			   &lt;IMX8QXP_SAI1_RXC_LSIO_GPIO0_IO30			0x20&gt;,		/* SODIMM  27 */</div><div class='add'>+			   &lt;IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03			0x20&gt;,		/* SODIMM  29 */</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22			0x20&gt;,		/* SODIMM  31 */</div><div class='add'>+			   &lt;IMX8QXP_CSI_EN_LSIO_GPIO3_IO02			0x20&gt;;		/* SODIMM  37 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* On module wifi module */</div><div class='add'>+	pinctrl_pcieb: pciebgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01		0x04000061&gt;,	/* SODIMM 178 */</div><div class='add'>+			   &lt;IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02		0x04000061&gt;,	/* SODIMM  94 */</div><div class='add'>+			   &lt;IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00		0x60&gt;;		/* SODIMM  81 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Colibri PWM_A */</div><div class='add'>+	pinctrl_pwm_a: pwmagrp {</div><div class='add'>+	/* both pins are connected together, reserve the unused CSI_D05 */</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_CSI_D05_CI_PI_D07				0x61&gt;,		/* SODIMM  59 */</div><div class='add'>+			   &lt;IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT			0x60&gt;;		/* SODIMM  59 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Colibri PWM_B */</div><div class='add'>+	pinctrl_pwm_b: pwmbgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_UART1_TX_LSIO_PWM0_OUT			0x60&gt;;		/* SODIMM  28 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Colibri PWM_C */</div><div class='add'>+	pinctrl_pwm_c: pwmcgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_UART1_RX_LSIO_PWM1_OUT			0x60&gt;;		/* SODIMM  30 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Colibri PWM_D */</div><div class='add'>+	pinctrl_pwm_d: pwmdgrp {</div><div class='add'>+	/* both pins are connected together, reserve the unused CSI_D04 */</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_CSI_D04_CI_PI_D06				0x61&gt;,		/* SODIMM  67 */</div><div class='add'>+			   &lt;IMX8QXP_UART1_RTS_B_LSIO_PWM2_OUT			0x60&gt;;		/* SODIMM  67 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* On-module I2S */</div><div class='add'>+	pinctrl_sai0: sai0grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_SPI0_SDI_ADMA_SAI0_TXD			0x06000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_SPI0_CS0_ADMA_SAI0_RXD			0x06000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_SPI0_SCK_ADMA_SAI0_TXC			0x06000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_SPI0_SDO_ADMA_SAI0_TXFS			0x06000040&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Colibri Audio Analogue Microphone GND */</div><div class='add'>+	pinctrl_sgtl5000: sgtl5000grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06		0x41&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* On-module SGTL5000 clock */</div><div class='add'>+	pinctrl_sgtl5000_usb_clk: sgtl5000usbclkgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_ADC_IN3_ADMA_ACM_MCLK_OUT0			0x21&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* On-module USB interrupt */</div><div class='add'>+	pinctrl_usb3503a: usb3503agrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04		0x61&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Colibri USB Client Cable Detect */</div><div class='add'>+	pinctrl_usbc_det: usbcdetgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09	0x06000040&gt;;	/* SODIMM 137 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* USB Host Power Enable */</div><div class='add'>+	pinctrl_usbh1_reg: usbh1reggrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_USB_SS3_TC0_LSIO_GPIO4_IO03			0x06000040&gt;;	/* SODIMM 129 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* On-module eMMC */</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK			0x06000041&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD			0x21&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0		0x21&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1		0x21&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2		0x21&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3		0x21&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4		0x21&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5		0x21&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6		0x21&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7		0x21&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE		0x41&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B		0x21&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK			0x06000041&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD			0x21&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0		0x21&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1		0x21&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2		0x21&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3		0x21&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4		0x21&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5		0x21&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6		0x21&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7		0x21&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE		0x41&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B		0x21&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK			0x06000041&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD			0x21&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0		0x21&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1		0x21&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2		0x21&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3		0x21&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4		0x21&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5		0x21&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6		0x21&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7		0x21&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE		0x41&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B		0x21&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Colibri SD/MMC Card Detect */</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09		0x06000021&gt;;	/* SODIMM  43 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio_sleep: usdhc2gpioslpgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09		0x60&gt;;		/* SODIMM  43 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Colibri SD/MMC Card */</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK			0x06000041&gt;,	/* SODIMM  47 */</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD			0x21&gt;,		/* SODIMM 190 */</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0		0x21&gt;,		/* SODIMM 192 */</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1		0x21&gt;,		/* SODIMM  49 */</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2		0x21&gt;,		/* SODIMM  51 */</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3		0x21&gt;,		/* SODIMM  53 */</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x21&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK			0x06000041&gt;,	/* SODIMM  47 */</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD			0x21&gt;,		/* SODIMM 190 */</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0		0x21&gt;,		/* SODIMM 192 */</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1		0x21&gt;,		/* SODIMM  49 */</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2		0x21&gt;,		/* SODIMM  51 */</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3		0x21&gt;,		/* SODIMM  53 */</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x21&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK			0x06000041&gt;,	/* SODIMM  47 */</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD			0x21&gt;,		/* SODIMM 190 */</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0		0x21&gt;,		/* SODIMM 192 */</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1		0x21&gt;,		/* SODIMM  49 */</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2		0x21&gt;,		/* SODIMM  51 */</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3		0x21&gt;,		/* SODIMM  53 */</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x21&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_sleep: usdhc2slpgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_USDHC1_CLK_LSIO_GPIO4_IO23			0x60&gt;,		/* SODIMM  47 */</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_CMD_LSIO_GPIO4_IO24			0x60&gt;,		/* SODIMM 190 */</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_DATA0_LSIO_GPIO4_IO25		0x60&gt;,		/* SODIMM 192 */</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_DATA1_LSIO_GPIO4_IO26		0x60&gt;,		/* SODIMM  49 */</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_DATA2_LSIO_GPIO4_IO27		0x60&gt;,		/* SODIMM  51 */</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_DATA3_LSIO_GPIO4_IO28		0x60&gt;,		/* SODIMM  53 */</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x21&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wifi: wifigrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K	0x20&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Delete peripherals which are not present on SOC, but are defined in imx8-ss-*.dtsi */</div><div class='add'>+</div><div class='add'>+/delete-node/ &amp;adc1;</div><div class='add'>+/delete-node/ &amp;adc1_lpcg;</div><div class='add'>+/delete-node/ &amp;dsp;</div><div class='add'>+/delete-node/ &amp;dsp_lpcg;</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts<br/>new file mode 100644<br/>index 000000000000..aca78768dbd4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts</a></div><div class='hunk'>@@ -0,0 +1,674 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2025 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/usb/pd.h&gt;</div><div class='add'>+#include "imx91.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "fsl,imx91-11x11-evk", "fsl,imx91";</div><div class='add'>+	model = "NXP i.MX91 11X11 EVK board";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;fec;</div><div class='add'>+		ethernet1 = &amp;eqos;</div><div class='add'>+		gpio0 = &amp;gpio1;</div><div class='add'>+		gpio1 = &amp;gpio2;</div><div class='add'>+		gpio2 = &amp;gpio3;</div><div class='add'>+		i2c0 = &amp;lpi2c1;</div><div class='add'>+		i2c1 = &amp;lpi2c2;</div><div class='add'>+		i2c2 = &amp;lpi2c3;</div><div class='add'>+		mmc0 = &amp;usdhc1;</div><div class='add'>+		mmc1 = &amp;usdhc2;</div><div class='add'>+		rtc0 = &amp;bbnsm_rtc;</div><div class='add'>+		serial0 = &amp;lpuart1;</div><div class='add'>+		serial1 = &amp;lpuart2;</div><div class='add'>+		serial2 = &amp;lpuart3;</div><div class='add'>+		serial3 = &amp;lpuart4;</div><div class='add'>+		serial4 = &amp;lpuart5;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;lpuart1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vref_1v8: regulator-adc-vref {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-name = "vref_1v8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_audio_pwr: regulator-audio-pwr {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "audio-pwr";</div><div class='add'>+		gpio = &lt;&amp;adp5585 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		off-on-delay-us = &lt;12000&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usdhc2_vmmc&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "VSD_3V3";</div><div class='add'>+		gpio = &lt;&amp;gpio3 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		ranges;</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		linux,cma {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			alloc-ranges = &lt;0 0x80000000 0 0x40000000&gt;;</div><div class='add'>+			reusable;</div><div class='add'>+			size = &lt;0 0x10000000&gt;;</div><div class='add'>+			linux,cma-default;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;adc1 {</div><div class='add'>+	vref-supply = &lt;&amp;reg_vref_1v8&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eqos {</div><div class='add'>+	phy-handle = &lt;&amp;ethphy1&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_eqos&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_eqos_sleep&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;5000000&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy1: ethernet-phy@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			realtek,clkout-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec {</div><div class='add'>+	phy-handle = &lt;&amp;ethphy2&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_fec_sleep&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	fsl,magic-packet;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;5000000&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy2: ethernet-phy@2 {</div><div class='add'>+			reg = &lt;2&gt;;</div><div class='add'>+			realtek,clkout-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c1 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c1&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	audio_codec: wm8962@1a {</div><div class='add'>+		compatible = "wlf,wm8962";</div><div class='add'>+		reg = &lt;0x1a&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX93_CLK_SAI3_GATE&gt;;</div><div class='add'>+		AVDD-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+		CPVDD-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+		DBVDD-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+		DCVDD-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+		MICVDD-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+		PLLVDD-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+		SPKVDD1-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+		SPKVDD2-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+		gpio-cfg = &lt;</div><div class='add'>+			0x0000 /* 0:Default */</div><div class='add'>+			0x0000 /* 1:Default */</div><div class='add'>+			0x0000 /* 2:FN_DMICCLK */</div><div class='add'>+			0x0000 /* 3:Default */</div><div class='add'>+			0x0000 /* 4:FN_DMICCDAT */</div><div class='add'>+			0x0000 /* 5:Default */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	inertial-meter@6a {</div><div class='add'>+		compatible = "st,lsm6dso";</div><div class='add'>+		reg = &lt;0x6a&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c2 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c2&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pcal6524: gpio@22 {</div><div class='add'>+		compatible = "nxp,pcal6524";</div><div class='add'>+		reg = &lt;0x22&gt;;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		interrupts = &lt;27 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pcal6524&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmic@25 {</div><div class='add'>+		compatible = "nxp,pca9451a";</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+		interrupts = &lt;11 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;pcal6524&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			buck1: BUCK1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;2237500&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;650000&gt;;</div><div class='add'>+				regulator-name = "BUCK1";</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck2: BUCK2 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;2187500&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-name = "BUCK2";</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck4: BUCK4 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;3400000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-name = "BUCK4";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck5: BUCK5 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;3400000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-name = "BUCK5";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck6: BUCK6 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;3400000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-name = "BUCK6";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo1: LDO1 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1600000&gt;;</div><div class='add'>+				regulator-name = "LDO1";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo4: LDO4 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-name = "LDO4";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo5: LDO5 {</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-name = "LDO5";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	adp5585: io-expander@34 {</div><div class='add'>+		compatible = "adi,adp5585-00", "adi,adp5585";</div><div class='add'>+		reg = &lt;0x34&gt;;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#pwm-cells = &lt;3&gt;;</div><div class='add'>+		gpio-reserved-ranges = &lt;5 1&gt;;</div><div class='add'>+</div><div class='add'>+		exp-sel-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c3 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c3&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ptn5110: tcpc@50 {</div><div class='add'>+		compatible = "nxp,ptn5110", "tcpci";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		interrupts = &lt;27 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+</div><div class='add'>+		typec1_con: connector {</div><div class='add'>+			compatible = "usb-c-connector";</div><div class='add'>+			data-role = "dual";</div><div class='add'>+			label = "USB-C";</div><div class='add'>+			op-sink-microwatt = &lt;15000000&gt;;</div><div class='add'>+			power-role = "dual";</div><div class='add'>+			self-powered;</div><div class='add'>+			sink-pdos = &lt;PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)</div><div class='add'>+				     PDO_VAR(5000, 20000, 3000)&gt;;</div><div class='add'>+			source-pdos = &lt;PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)&gt;;</div><div class='add'>+			try-power-role = "sink";</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					typec1_dr_sw: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;usb1_drd_sw&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ptn5110_2: tcpc@51 {</div><div class='add'>+		compatible = "nxp,ptn5110", "tcpci";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		interrupts = &lt;27 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+</div><div class='add'>+		typec2_con: connector {</div><div class='add'>+			compatible = "usb-c-connector";</div><div class='add'>+			data-role = "dual";</div><div class='add'>+			label = "USB-C";</div><div class='add'>+			op-sink-microwatt = &lt;15000000&gt;;</div><div class='add'>+			power-role = "dual";</div><div class='add'>+			self-powered;</div><div class='add'>+			sink-pdos = &lt;PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)</div><div class='add'>+				     PDO_VAR(5000, 20000, 3000)&gt;;</div><div class='add'>+			source-pdos = &lt;PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)&gt;;</div><div class='add'>+			try-power-role = "sink";</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					typec2_dr_sw: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;usb2_drd_sw&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcf2131: rtc@53 {</div><div class='add'>+		compatible = "nxp,pcf2131";</div><div class='add'>+		reg = &lt;0x53&gt;;</div><div class='add'>+		interrupts = &lt;1 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;pcal6524&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart5 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart5&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "nxp,88w8987-bt";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	adp-disable;</div><div class='add'>+	disable-over-current;</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	hnp-disable;</div><div class='add'>+	srp-disable;</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	samsung,picophy-dc-vol-level-adjust = &lt;7&gt;;</div><div class='add'>+	samsung,picophy-pre-emp-curr-control = &lt;3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	port {</div><div class='add'>+		usb1_drd_sw: endpoint {</div><div class='add'>+			remote-endpoint = &lt;&amp;typec1_dr_sw&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg2 {</div><div class='add'>+	adp-disable;</div><div class='add'>+	disable-over-current;</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	hnp-disable;</div><div class='add'>+	srp-disable;</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	samsung,picophy-dc-vol-level-adjust = &lt;7&gt;;</div><div class='add'>+	samsung,picophy-pre-emp-curr-control = &lt;3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	port {</div><div class='add'>+		usb2_drd_sw: endpoint {</div><div class='add'>+			remote-endpoint = &lt;&amp;typec2_dr_sw&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1_200mhz&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio3 00 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	no-mmc;</div><div class='add'>+	no-sdio;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-3 = &lt;&amp;pinctrl_usdhc2_sleep&gt;, &lt;&amp;pinctrl_usdhc2_gpio_sleep&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog3 {</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_eqos: eqosgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX91_PAD_ENET1_MDC__ENET1_MDC                           0x57e</div><div class='add'>+			MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO                      0x57e</div><div class='add'>+			MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0                  0x57e</div><div class='add'>+			MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1                  0x57e</div><div class='add'>+			MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2                  0x57e</div><div class='add'>+			MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3                  0x57e</div><div class='add'>+			MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC                  0x5fe</div><div class='add'>+			MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL            0x57e</div><div class='add'>+			MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0                  0x57e</div><div class='add'>+			MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1                     0x57e</div><div class='add'>+			MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2                  0x57e</div><div class='add'>+			MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3                  0x57e</div><div class='add'>+			MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK  0x5fe</div><div class='add'>+			MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL            0x57e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_eqos_sleep: eqossleepgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX91_PAD_ENET1_MDC__GPIO4_IO0                           0x31e</div><div class='add'>+			MX91_PAD_ENET1_MDIO__GPIO4_IO1                          0x31e</div><div class='add'>+			MX91_PAD_ENET1_RD0__GPIO4_IO10                          0x31e</div><div class='add'>+			MX91_PAD_ENET1_RD1__GPIO4_IO11                          0x31e</div><div class='add'>+			MX91_PAD_ENET1_RD2__GPIO4_IO12                          0x31e</div><div class='add'>+			MX91_PAD_ENET1_RD3__GPIO4_IO13                          0x31e</div><div class='add'>+			MX91_PAD_ENET1_RXC__GPIO4_IO9                           0x31e</div><div class='add'>+			MX91_PAD_ENET1_RX_CTL__GPIO4_IO8                        0x31e</div><div class='add'>+			MX91_PAD_ENET1_TD0__GPIO4_IO5                           0x31e</div><div class='add'>+			MX91_PAD_ENET1_TD1__GPIO4_IO4                           0x31e</div><div class='add'>+			MX91_PAD_ENET1_TD2__GPIO4_IO3                           0x31e</div><div class='add'>+			MX91_PAD_ENET1_TD3__GPIO4_IO2                           0x31e</div><div class='add'>+			MX91_PAD_ENET1_TXC__GPIO4_IO7                           0x31e</div><div class='add'>+			MX91_PAD_ENET1_TX_CTL__GPIO4_IO6                        0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec: fecgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX91_PAD_ENET2_MDC__ENET2_MDC                           0x57e</div><div class='add'>+			MX91_PAD_ENET2_MDIO__ENET2_MDIO                         0x57e</div><div class='add'>+			MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0                     0x57e</div><div class='add'>+			MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1                     0x57e</div><div class='add'>+			MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2                     0x57e</div><div class='add'>+			MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3                     0x57e</div><div class='add'>+			MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC                     0x5fe</div><div class='add'>+			MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL               0x57e</div><div class='add'>+			MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0                     0x57e</div><div class='add'>+			MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1                     0x57e</div><div class='add'>+			MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2                     0x57e</div><div class='add'>+			MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3                     0x57e</div><div class='add'>+			MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC                     0x5fe</div><div class='add'>+			MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL               0x57e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec_sleep: fecsleepgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX91_PAD_ENET2_MDC__GPIO4_IO14                          0x51e</div><div class='add'>+			MX91_PAD_ENET2_MDIO__GPIO4_IO15                         0x51e</div><div class='add'>+			MX91_PAD_ENET2_RD0__GPIO4_IO24                          0x51e</div><div class='add'>+			MX91_PAD_ENET2_RD1__GPIO4_IO25                          0x51e</div><div class='add'>+			MX91_PAD_ENET2_RD2__GPIO4_IO26                          0x51e</div><div class='add'>+			MX91_PAD_ENET2_RD3__GPIO4_IO27                          0x51e</div><div class='add'>+			MX91_PAD_ENET2_RXC__GPIO4_IO23                          0x51e</div><div class='add'>+			MX91_PAD_ENET2_RX_CTL__GPIO4_IO22                       0x51e</div><div class='add'>+			MX91_PAD_ENET2_TD0__GPIO4_IO19                          0x51e</div><div class='add'>+			MX91_PAD_ENET2_TD1__GPIO4_IO18                          0x51e</div><div class='add'>+			MX91_PAD_ENET2_TD2__GPIO4_IO17                          0x51e</div><div class='add'>+			MX91_PAD_ENET2_TD3__GPIO4_IO16                          0x51e</div><div class='add'>+			MX91_PAD_ENET2_TXC__GPIO4_IO21                          0x51e</div><div class='add'>+			MX91_PAD_ENET2_TX_CTL__GPIO4_IO20                       0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c1: lpi2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX91_PAD_I2C1_SCL__LPI2C1_SCL                           0x40000b9e</div><div class='add'>+			MX91_PAD_I2C1_SDA__LPI2C1_SDA                           0x40000b9e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c2: lpi2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX91_PAD_I2C2_SCL__LPI2C2_SCL                           0x40000b9e</div><div class='add'>+			MX91_PAD_I2C2_SDA__LPI2C2_SDA                           0x40000b9e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c3: lpi2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX91_PAD_GPIO_IO28__LPI2C3_SDA                          0x40000b9e</div><div class='add'>+			MX91_PAD_GPIO_IO29__LPI2C3_SCL                          0x40000b9e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcal6524: pcal6524grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX91_PAD_CCM_CLKO2__GPIO3_IO27                          0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX91_PAD_SD2_RESET_B__GPIO3_IO7                         0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX91_PAD_UART1_RXD__LPUART1_RX                          0x31e</div><div class='add'>+			MX91_PAD_UART1_TXD__LPUART1_TX                          0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart5: uart5grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX                   0x31e</div><div class='add'>+			MX91_PAD_DAP_TDI__LPUART5_RX                            0x31e</div><div class='add'>+			MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B                   0x31e</div><div class='add'>+			MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B                  0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX91_PAD_SD1_CLK__USDHC1_CLK                            0x158e</div><div class='add'>+			MX91_PAD_SD1_CMD__USDHC1_CMD                            0x138e</div><div class='add'>+			MX91_PAD_SD1_DATA0__USDHC1_DATA0                        0x138e</div><div class='add'>+			MX91_PAD_SD1_DATA1__USDHC1_DATA1                        0x138e</div><div class='add'>+			MX91_PAD_SD1_DATA2__USDHC1_DATA2                        0x138e</div><div class='add'>+			MX91_PAD_SD1_DATA3__USDHC1_DATA3                        0x138e</div><div class='add'>+			MX91_PAD_SD1_DATA4__USDHC1_DATA4                        0x138e</div><div class='add'>+			MX91_PAD_SD1_DATA5__USDHC1_DATA5                        0x138e</div><div class='add'>+			MX91_PAD_SD1_DATA6__USDHC1_DATA6                        0x138e</div><div class='add'>+			MX91_PAD_SD1_DATA7__USDHC1_DATA7                        0x138e</div><div class='add'>+			MX91_PAD_SD1_STROBE__USDHC1_STROBE                      0x158e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX91_PAD_SD1_CLK__USDHC1_CLK                            0x15fe</div><div class='add'>+			MX91_PAD_SD1_CMD__USDHC1_CMD                            0x13fe</div><div class='add'>+			MX91_PAD_SD1_DATA0__USDHC1_DATA0                        0x13fe</div><div class='add'>+			MX91_PAD_SD1_DATA1__USDHC1_DATA1                        0x13fe</div><div class='add'>+			MX91_PAD_SD1_DATA2__USDHC1_DATA2                        0x13fe</div><div class='add'>+			MX91_PAD_SD1_DATA3__USDHC1_DATA3                        0x13fe</div><div class='add'>+			MX91_PAD_SD1_DATA4__USDHC1_DATA4                        0x13fe</div><div class='add'>+			MX91_PAD_SD1_DATA5__USDHC1_DATA5                        0x13fe</div><div class='add'>+			MX91_PAD_SD1_DATA6__USDHC1_DATA6                        0x13fe</div><div class='add'>+			MX91_PAD_SD1_DATA7__USDHC1_DATA7                        0x13fe</div><div class='add'>+			MX91_PAD_SD1_STROBE__USDHC1_STROBE                      0x15fe</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX91_PAD_SD1_CLK__USDHC1_CLK                            0x1582</div><div class='add'>+			MX91_PAD_SD1_CMD__USDHC1_CMD                            0x1382</div><div class='add'>+			MX91_PAD_SD1_DATA0__USDHC1_DATA0                        0x1382</div><div class='add'>+			MX91_PAD_SD1_DATA1__USDHC1_DATA1                        0x1382</div><div class='add'>+			MX91_PAD_SD1_DATA2__USDHC1_DATA2                        0x1382</div><div class='add'>+			MX91_PAD_SD1_DATA3__USDHC1_DATA3                        0x1382</div><div class='add'>+			MX91_PAD_SD1_DATA4__USDHC1_DATA4                        0x1382</div><div class='add'>+			MX91_PAD_SD1_DATA5__USDHC1_DATA5                        0x1382</div><div class='add'>+			MX91_PAD_SD1_DATA6__USDHC1_DATA6                        0x1382</div><div class='add'>+			MX91_PAD_SD1_DATA7__USDHC1_DATA7                        0x1382</div><div class='add'>+			MX91_PAD_SD1_STROBE__USDHC1_STROBE                      0x1582</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX91_PAD_SD2_CLK__USDHC2_CLK                            0x158e</div><div class='add'>+			MX91_PAD_SD2_CMD__USDHC2_CMD                            0x138e</div><div class='add'>+			MX91_PAD_SD2_DATA0__USDHC2_DATA0                        0x138e</div><div class='add'>+			MX91_PAD_SD2_DATA1__USDHC2_DATA1                        0x138e</div><div class='add'>+			MX91_PAD_SD2_DATA2__USDHC2_DATA2                        0x138e</div><div class='add'>+			MX91_PAD_SD2_DATA3__USDHC2_DATA3                        0x138e</div><div class='add'>+			MX91_PAD_SD2_VSELECT__USDHC2_VSELECT                    0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX91_PAD_SD2_CLK__USDHC2_CLK                            0x15fe</div><div class='add'>+			MX91_PAD_SD2_CMD__USDHC2_CMD                            0x13fe</div><div class='add'>+			MX91_PAD_SD2_DATA0__USDHC2_DATA0                        0x13fe</div><div class='add'>+			MX91_PAD_SD2_DATA1__USDHC2_DATA1                        0x13fe</div><div class='add'>+			MX91_PAD_SD2_DATA2__USDHC2_DATA2                        0x13fe</div><div class='add'>+			MX91_PAD_SD2_DATA3__USDHC2_DATA3                        0x13fe</div><div class='add'>+			MX91_PAD_SD2_VSELECT__USDHC2_VSELECT                    0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX91_PAD_SD2_CD_B__GPIO3_IO0                            0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX91_PAD_SD2_CD_B__GPIO3_IO0                            0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX91_PAD_SD2_CLK__USDHC2_CLK                            0x1582</div><div class='add'>+			MX91_PAD_SD2_CMD__USDHC2_CMD                            0x1382</div><div class='add'>+			MX91_PAD_SD2_DATA0__USDHC2_DATA0                        0x1382</div><div class='add'>+			MX91_PAD_SD2_DATA1__USDHC2_DATA1                        0x1382</div><div class='add'>+			MX91_PAD_SD2_DATA2__USDHC2_DATA2                        0x1382</div><div class='add'>+			MX91_PAD_SD2_DATA3__USDHC2_DATA3                        0x1382</div><div class='add'>+			MX91_PAD_SD2_VSELECT__USDHC2_VSELECT                    0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_sleep: usdhc2sleepgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX91_PAD_SD2_CLK__GPIO3_IO1                             0x51e</div><div class='add'>+			MX91_PAD_SD2_CMD__GPIO3_IO2                             0x51e</div><div class='add'>+			MX91_PAD_SD2_DATA0__GPIO3_IO3                           0x51e</div><div class='add'>+			MX91_PAD_SD2_DATA1__GPIO3_IO4                           0x51e</div><div class='add'>+			MX91_PAD_SD2_DATA2__GPIO3_IO5                           0x51e</div><div class='add'>+			MX91_PAD_SD2_DATA3__GPIO3_IO6                           0x51e</div><div class='add'>+			MX91_PAD_SD2_VSELECT__GPIO3_IO19                        0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx91-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx91-phyboard-segin.dts<br/>new file mode 100644<br/>index 000000000000..7b18a58024f5<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx91-phyboard-segin.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx91-phyboard-segin.dts</a></div><div class='hunk'>@@ -0,0 +1,345 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2025 PHYTEC Messtechnik GmbH</div><div class='add'>+ * Author: Christoph Stoidner &lt;c.stoidner@phytec.de&gt;</div><div class='add'>+ *</div><div class='add'>+ * Product homepage:</div><div class='add'>+ * phyBOARD-Segin carrier board is reused for the i.MX91 design.</div><div class='add'>+ * https://www.phytec.eu/en/produkte/single-board-computer/phyboard-segin-imx6ul/</div><div class='add'>+ */</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx91-phycore-som.dtsi"</div><div class='add'>+</div><div class='add'>+/{</div><div class='add'>+	model = "PHYTEC phyBOARD-Segin-i.MX91";</div><div class='add'>+	compatible = "phytec,imx91-phyboard-segin", "phytec,imx91-phycore-som",</div><div class='add'>+		     "fsl,imx91";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet1 = &amp;eqos;</div><div class='add'>+		gpio0 = &amp;gpio1;</div><div class='add'>+		gpio1 = &amp;gpio2;</div><div class='add'>+		gpio2 = &amp;gpio3;</div><div class='add'>+		gpio3 = &amp;gpio4;</div><div class='add'>+		i2c0 = &amp;lpi2c1;</div><div class='add'>+		i2c1 = &amp;lpi2c2;</div><div class='add'>+		mmc0 = &amp;usdhc1;</div><div class='add'>+		mmc1 = &amp;usdhc2;</div><div class='add'>+		rtc0 = &amp;i2c_rtc;</div><div class='add'>+		rtc1 = &amp;bbnsm_rtc;</div><div class='add'>+		serial0 = &amp;lpuart1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;lpuart1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	flexcan1_tc: can-phy0 {</div><div class='add'>+		/* TI SN65HVD234D CAN-CC 1MBit/s */</div><div class='add'>+		compatible = "ti,tcan1043";</div><div class='add'>+		#phy-cells = &lt;0&gt;;</div><div class='add'>+		max-bitrate = &lt;1000000&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_flexcan1_tc&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;gpio4 16 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_sound_1v8: regulator-sound-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-name = "VCC1V8_AUDIO";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_sound_3v3: regulator-sound-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "VCC3V3_ANALOG";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb_otg1_vbus: regulator-usb-otg1-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "USB_OTG1_VBUS";</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb_otg2_vbus: regulator-usb-otg2-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "USB_OTG2_VBUS";</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;gpio3 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usdhc2_vmmc&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "VCC_SD";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound: sound {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,name = "phyBOARD-Segin-TLV320AIC3007";</div><div class='add'>+		simple-audio-card,format = "i2s";</div><div class='add'>+		simple-audio-card,bitclock-master = &lt;&amp;dailink_master&gt;;</div><div class='add'>+		simple-audio-card,frame-master = &lt;&amp;dailink_master&gt;;</div><div class='add'>+		simple-audio-card,widgets =</div><div class='add'>+			"Line", "Line In",</div><div class='add'>+			"Line", "Line Out",</div><div class='add'>+			"Speaker", "Speaker";</div><div class='add'>+		simple-audio-card,routing =</div><div class='add'>+			"Line Out", "LLOUT",</div><div class='add'>+			"Line Out", "RLOUT",</div><div class='add'>+			"Speaker", "SPOP",</div><div class='add'>+			"Speaker", "SPOM",</div><div class='add'>+			"LINE1L", "Line In",</div><div class='add'>+			"LINE1R", "Line In";</div><div class='add'>+</div><div class='add'>+		simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;sai1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dailink_master: simple-audio-card,codec {</div><div class='add'>+			sound-dai = &lt;&amp;audio_codec&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX93_CLK_SAI1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Ethernet */</div><div class='add'>+&amp;eqos {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_eqos&gt;;</div><div class='add'>+	phy-mode = "rmii";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy2&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX93_CLK_SYS_PLL_PFD1_DIV2&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX93_CLK_SYS_PLL_PFD1_DIV2&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;100000000&gt;, &lt;50000000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdio {</div><div class='add'>+	ethphy2: ethernet-phy@2 {</div><div class='add'>+		compatible = "ethernet-phy-id0022.1561";</div><div class='add'>+		reg = &lt;2&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX91_CLK_ENET2_REGULAR&gt;;</div><div class='add'>+		clock-names = "rmii-ref";</div><div class='add'>+		micrel,led-mode = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* CAN */</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan1&gt;;</div><div class='add'>+	phys = &lt;&amp;flexcan1_tc&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* I2C2 */</div><div class='add'>+&amp;lpi2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c2&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_lpi2c2_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* Codec */</div><div class='add'>+	audio_codec: audio-codec@18 {</div><div class='add'>+		compatible = "ti,tlv320aic3007";</div><div class='add'>+		reg = &lt;0x18&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		AVDD-supply = &lt;&amp;reg_sound_3v3&gt;;</div><div class='add'>+		IOVDD-supply = &lt;&amp;reg_sound_3v3&gt;;</div><div class='add'>+		DRVDD-supply = &lt;&amp;reg_sound_3v3&gt;;</div><div class='add'>+		DVDD-supply = &lt;&amp;reg_sound_1v8&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* RTC */</div><div class='add'>+	i2c_rtc: rtc@68 {</div><div class='add'>+		compatible = "microcrystal,rv4162";</div><div class='add'>+		reg = &lt;0x68&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_rtc&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;26 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Console */</div><div class='add'>+&amp;lpuart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Audio */</div><div class='add'>+&amp;sai1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai1&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX93_CLK_SAI1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX93_CLK_AUDIO_PLL&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;19200000&gt;;</div><div class='add'>+	fsl,sai-mclk-direction-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB  */</div><div class='add'>+&amp;usbphynop1 {</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usb_otg1_vbus&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbphynop2 {</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usb_otg2_vbus&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	disable-over-current;</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg2 {</div><div class='add'>+	disable-over-current;</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SD-Card */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2_default&gt;, &lt;&amp;pinctrl_usdhc2_cd&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_cd&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_cd&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio3 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+	no-mmc;</div><div class='add'>+	no-sdio;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_eqos: eqosgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX91_PAD_ENET1_TD2__ENET_QOS_CLOCK_GENERATE_CLK	0x4000050e</div><div class='add'>+			MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0		0x57e</div><div class='add'>+			MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1		0x57e</div><div class='add'>+			MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0		0x50e</div><div class='add'>+			MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1		0x50e</div><div class='add'>+			MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL	0x57e</div><div class='add'>+			MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL	0x50e</div><div class='add'>+			MX91_PAD_ENET1_RXC__ENET_QOS_RX_ER		0x57e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan1: flexcan1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX91_PAD_PDM_BIT_STREAM0__CAN1_RX	0x139e</div><div class='add'>+			MX91_PAD_PDM_CLK__CAN1_TX		0x139e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan1_tc: flexcan1tcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX91_PAD_ENET2_TD3__GPIO4_IO16		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c2: lpi2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX91_PAD_I2C2_SCL__LPI2C2_SCL		0x40000b9e</div><div class='add'>+			MX91_PAD_I2C2_SDA__LPI2C2_SDA		0x40000b9e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c2_gpio: lpi2c2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX91_PAD_I2C2_SCL__GPIO1_IO2		0x31e</div><div class='add'>+			MX91_PAD_I2C2_SDA__GPIO1_IO3		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX91_PAD_SD2_RESET_B__GPIO3_IO7		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_rtc: rtcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX91_PAD_ENET2_RD2__GPIO4_IO26		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai1: sai1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX91_PAD_UART2_RXD__SAI1_MCLK		0x1202</div><div class='add'>+			MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC	0x1202</div><div class='add'>+			MX91_PAD_SAI1_TXC__SAI1_TX_BCLK		0x1202</div><div class='add'>+			MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0	0x1402</div><div class='add'>+			MX91_PAD_SAI1_RXD0__SAI1_RX_DATA0	0x1402</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX91_PAD_UART1_RXD__LPUART1_RX		0x31e</div><div class='add'>+			MX91_PAD_UART1_TXD__LPUART1_TX		0x30e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_cd: usdhc2cdgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX91_PAD_SD2_CD_B__GPIO3_IO0		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_default: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX91_PAD_SD2_CLK__USDHC2_CLK		0x158e</div><div class='add'>+			MX91_PAD_SD2_CMD__USDHC2_CMD		0x1382</div><div class='add'>+			MX91_PAD_SD2_DATA0__USDHC2_DATA0	0x1386</div><div class='add'>+			MX91_PAD_SD2_DATA1__USDHC2_DATA1	0x138e</div><div class='add'>+			MX91_PAD_SD2_DATA2__USDHC2_DATA2	0x139e</div><div class='add'>+			MX91_PAD_SD2_DATA3__USDHC2_DATA3	0x139e</div><div class='add'>+			MX91_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX91_PAD_SD2_CLK__USDHC2_CLK		0x159e</div><div class='add'>+			MX91_PAD_SD2_CMD__USDHC2_CMD		0x139e</div><div class='add'>+			MX91_PAD_SD2_DATA0__USDHC2_DATA0	0x138e</div><div class='add'>+			MX91_PAD_SD2_DATA1__USDHC2_DATA1	0x138e</div><div class='add'>+			MX91_PAD_SD2_DATA2__USDHC2_DATA2	0x139e</div><div class='add'>+			MX91_PAD_SD2_DATA3__USDHC2_DATA3	0x139e</div><div class='add'>+			MX91_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX91_PAD_SD2_CLK__USDHC2_CLK		0x158e</div><div class='add'>+			MX91_PAD_SD2_CMD__USDHC2_CMD		0x138e</div><div class='add'>+			MX91_PAD_SD2_DATA0__USDHC2_DATA0	0x139e</div><div class='add'>+			MX91_PAD_SD2_DATA1__USDHC2_DATA1	0x139e</div><div class='add'>+			MX91_PAD_SD2_DATA2__USDHC2_DATA2	0x139e</div><div class='add'>+			MX91_PAD_SD2_DATA3__USDHC2_DATA3	0x139e</div><div class='add'>+			MX91_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx91-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx91-phycore-som.dtsi<br/>new file mode 100644<br/>index 000000000000..29a428a052b0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx91-phycore-som.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx91-phycore-som.dtsi</a></div><div class='hunk'>@@ -0,0 +1,304 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2025 PHYTEC Messtechnik GmbH</div><div class='add'>+ * Author: Christoph Stoidner &lt;c.stoidner@phytec.de&gt;</div><div class='add'>+ *</div><div class='add'>+ * Product homepage:</div><div class='add'>+ * https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+#include "imx91.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "PHYTEC phyCORE-i.MX91";</div><div class='add'>+	compatible = "phytec,imx91-phycore-som", "fsl,imx91";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;fec;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		ranges;</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		linux,cma {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reusable;</div><div class='add'>+			alloc-ranges = &lt;0 0x80000000 0 0x40000000&gt;;</div><div class='add'>+			size = &lt;0 0x10000000&gt;;</div><div class='add'>+			linux,cma-default;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_leds&gt;;</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_HEARTBEAT;</div><div class='add'>+			gpios = &lt;&amp;gpio1 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vdda_1v8: regulator-vdda-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDA_1V8";</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;buck5&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* ADC */</div><div class='add'>+&amp;adc1 {</div><div class='add'>+	vref-supply = &lt;&amp;reg_vdda_1v8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Ethernet */</div><div class='add'>+&amp;fec {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec&gt;;</div><div class='add'>+	phy-mode = "rmii";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy1&gt;;</div><div class='add'>+</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX91_CLK_ENET_TIMER&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX91_CLK_ENET2_REGULAR&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX93_CLK_SYS_PLL_PFD1_DIV2&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX93_CLK_SYS_PLL_PFD1_DIV2&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;100000000&gt;, &lt;50000000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio: mdio {</div><div class='add'>+		clock-frequency = &lt;5000000&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy1: ethernet-phy@1 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio4 23 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			reset-assert-us = &lt;30&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* I2C3 */</div><div class='add'>+&amp;lpi2c3 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_lpi2c3_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pmic@25 {</div><div class='add'>+		compatible = "nxp,pca9451a";</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;27 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			buck1: BUCK1 {</div><div class='add'>+				regulator-name = "VDD_SOC";</div><div class='add'>+				regulator-max-microvolt = &lt;950000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;610000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck2: BUCK2 {</div><div class='add'>+				regulator-name = "VDDQ_0V6";</div><div class='add'>+				regulator-max-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck4: BUCK4 {</div><div class='add'>+				regulator-name = "VDD_3V3_BUCK";</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck5: BUCK5 {</div><div class='add'>+				regulator-name = "VDD_1V8";</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck6: BUCK6 {</div><div class='add'>+				regulator-name = "VDD_1V1";</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo1: LDO1 {</div><div class='add'>+				regulator-name = "PMIC_SNVS_1V8";</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo4: LDO4 {</div><div class='add'>+				regulator-name = "VDD_0V8";</div><div class='add'>+				regulator-max-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo5: LDO5 {</div><div class='add'>+				regulator-name = "NVCC_SD2";</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* EEPROM */</div><div class='add'>+	eeprom@50 {</div><div class='add'>+		compatible = "atmel,24c32";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;buck4&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* eMMC */</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1_200mhz&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	no-1-8-v;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Watchdog */</div><div class='add'>+&amp;wdog3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_fec: fecgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX91_PAD_ENET2_MDC__ENET2_MDC			0x50e</div><div class='add'>+			MX91_PAD_ENET2_MDIO__ENET2_MDIO			0x502</div><div class='add'>+			/* the three pins below are connected to PHYs straps,</div><div class='add'>+			 * that is what the pull-up/down setting is for.</div><div class='add'>+			 */</div><div class='add'>+			MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0		0x37e</div><div class='add'>+			MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1		0x37e</div><div class='add'>+			MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL	0x57e</div><div class='add'>+			MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0		0x50e</div><div class='add'>+			MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1		0x50e</div><div class='add'>+			MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL	0x50e</div><div class='add'>+			MX91_PAD_ENET2_TD2__ENET2_TX_CLK2		0x4000050e</div><div class='add'>+			MX91_PAD_ENET2_RXC__GPIO4_IO23			0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_leds: ledsgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX91_PAD_I2C1_SDA__GPIO1_IO1		0x11e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c3: lpi2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX91_PAD_GPIO_IO28__LPI2C3_SDA		0x40000b9e</div><div class='add'>+			MX91_PAD_GPIO_IO29__LPI2C3_SCL		0x40000b9e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c3_gpio: lpi2c3gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX91_PAD_GPIO_IO28__GPIO2_IO28		0x31e</div><div class='add'>+			MX91_PAD_GPIO_IO29__GPIO2_IO29		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: pmicgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX91_PAD_ENET2_RD3__GPIO4_IO27		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX91_PAD_SD1_CLK__USDHC1_CLK		0x179e</div><div class='add'>+			MX91_PAD_SD1_CMD__USDHC1_CMD		0x1386</div><div class='add'>+			MX91_PAD_SD1_DATA0__USDHC1_DATA0	0x138e</div><div class='add'>+			MX91_PAD_SD1_DATA1__USDHC1_DATA1	0x1386</div><div class='add'>+			MX91_PAD_SD1_DATA2__USDHC1_DATA2	0x138e</div><div class='add'>+			MX91_PAD_SD1_DATA3__USDHC1_DATA3	0x1386</div><div class='add'>+			MX91_PAD_SD1_DATA4__USDHC1_DATA4	0x1386</div><div class='add'>+			MX91_PAD_SD1_DATA5__USDHC1_DATA5	0x1386</div><div class='add'>+			MX91_PAD_SD1_DATA6__USDHC1_DATA6	0x1386</div><div class='add'>+			MX91_PAD_SD1_DATA7__USDHC1_DATA7	0x1386</div><div class='add'>+			MX91_PAD_SD1_STROBE__USDHC1_STROBE	0x179e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX91_PAD_SD1_CLK__USDHC1_CLK		0x17be</div><div class='add'>+			MX91_PAD_SD1_CMD__USDHC1_CMD		0x139e</div><div class='add'>+			MX91_PAD_SD1_DATA0__USDHC1_DATA0	0x138e</div><div class='add'>+			MX91_PAD_SD1_DATA1__USDHC1_DATA1	0x139e</div><div class='add'>+			MX91_PAD_SD1_DATA2__USDHC1_DATA2	0x13be</div><div class='add'>+			MX91_PAD_SD1_DATA3__USDHC1_DATA3	0x139e</div><div class='add'>+			MX91_PAD_SD1_DATA4__USDHC1_DATA4	0x139e</div><div class='add'>+			MX91_PAD_SD1_DATA5__USDHC1_DATA5	0x139e</div><div class='add'>+			MX91_PAD_SD1_DATA6__USDHC1_DATA6	0x139e</div><div class='add'>+			MX91_PAD_SD1_DATA7__USDHC1_DATA7	0x139e</div><div class='add'>+			MX91_PAD_SD1_STROBE__USDHC1_STROBE	0x179e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX91_PAD_SD1_CLK__USDHC1_CLK		0x17be</div><div class='add'>+			MX91_PAD_SD1_CMD__USDHC1_CMD		0x139e</div><div class='add'>+			MX91_PAD_SD1_DATA0__USDHC1_DATA0	0x139e</div><div class='add'>+			MX91_PAD_SD1_DATA1__USDHC1_DATA1	0x13be</div><div class='add'>+			MX91_PAD_SD1_DATA2__USDHC1_DATA2	0x13be</div><div class='add'>+			MX91_PAD_SD1_DATA3__USDHC1_DATA3	0x13be</div><div class='add'>+			MX91_PAD_SD1_DATA4__USDHC1_DATA4	0x13be</div><div class='add'>+			MX91_PAD_SD1_DATA5__USDHC1_DATA5	0x13be</div><div class='add'>+			MX91_PAD_SD1_DATA6__USDHC1_DATA6	0x13be</div><div class='add'>+			MX91_PAD_SD1_DATA7__USDHC1_DATA7	0x13be</div><div class='add'>+			MX91_PAD_SD1_STROBE__USDHC1_STROBE	0x179e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX91_PAD_WDOG_ANY__WDOG1_WDOG_ANY	0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx91-pinfunc.h b/arch/arm64/boot/dts/freescale/imx91-pinfunc.h<br/>new file mode 100644<br/>index 000000000000..3e19945f5ce3<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx91-pinfunc.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx91-pinfunc.h</a></div><div class='hunk'>@@ -0,0 +1,770 @@</div><div class='add'>+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2025 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __DTS_IMX91_PINFUNC_H</div><div class='add'>+#define __DTS_IMX91_PINFUNC_H</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * The pin function ID is a tuple of</div><div class='add'>+ * &lt;mux_reg conf_reg input_reg mux_mode input_val&gt;</div><div class='add'>+ */</div><div class='add'>+#define MX91_PAD_DAP_TDI__JTAG_MUX_TDI                                           0x0000 0x01b0 0x03d8 0x00 0x00</div><div class='add'>+#define MX91_PAD_DAP_TDI__MQS2_LEFT                                              0x0000 0x01b0 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_DAP_TDI__CAN2_TX                                                0x0000 0x01b0 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_DAP_TDI__FLEXIO2_FLEXIO30                                       0x0000 0x01b0 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_DAP_TDI__GPIO3_IO28                                             0x0000 0x01b0 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_DAP_TDI__LPUART5_RX                                             0x0000 0x01b0 0x0488 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS                                     0x0004 0x01b4 0x03dc 0x00 0x00</div><div class='add'>+#define MX91_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31                                 0x0004 0x01b4 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_DAP_TMS_SWDIO__GPIO3_IO29                                       0x0004 0x01b4 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B                                    0x0004 0x01b4 0x0000 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK                                    0x0008 0x01b8 0x03d4 0x00 0x00</div><div class='add'>+#define MX91_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30                                0x0008 0x01b8 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_DAP_TCLK_SWCLK__GPIO3_IO30                                      0x0008 0x01b8 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B                                   0x0008 0x01b8 0x0484 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO                                  0x000c 0x01bc 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT                                    0x000c 0x01bc 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_DAP_TDO_TRACESWO__CAN2_RX                                       0x000c 0x01bc 0x0364 0x03 0x00</div><div class='add'>+#define MX91_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31                              0x000c 0x01bc 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_DAP_TDO_TRACESWO__GPIO3_IO31                                    0x000c 0x01bc 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX                                    0x000c 0x01bc 0x048c 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_GPIO_IO00__GPIO2_IO0                                            0x0010 0x01c0 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO00__LPI2C3_SDA                                           0x0010 0x01c0 0x03f4 0x01 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK                                     0x0010 0x01c0 0x04bc 0x02 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK                                    0x0010 0x01c0 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO00__LPSPI6_PCS0                                          0x0010 0x01c0 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO00__LPUART5_TX                                           0x0010 0x01c0 0x048c 0x05 0x01</div><div class='add'>+#define MX91_PAD_GPIO_IO00__LPI2C5_SDA                                           0x0010 0x01c0 0x0404 0x06 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO00__FLEXIO1_FLEXIO0                                      0x0010 0x01c0 0x036c 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_GPIO_IO01__GPIO2_IO1                                            0x0014 0x01c4 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO01__LPI2C3_SCL                                           0x0014 0x01c4 0x03f0 0x01 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA0                                   0x0014 0x01c4 0x0490 0x02 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO01__MEDIAMIX_DISP_DE                                     0x0014 0x01c4 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO01__LPSPI6_SIN                                           0x0014 0x01c4 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO01__LPUART5_RX                                           0x0014 0x01c4 0x0488 0x05 0x01</div><div class='add'>+#define MX91_PAD_GPIO_IO01__LPI2C5_SCL                                           0x0014 0x01c4 0x0400 0x06 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO01__FLEXIO1_FLEXIO1                                      0x0014 0x01c4 0x0370 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_GPIO_IO02__GPIO2_IO2                                            0x0018 0x01c8 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO02__LPI2C4_SDA                                           0x0018 0x01c8 0x03fc 0x01 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC                                   0x0018 0x01c8 0x04c0 0x02 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC                                  0x0018 0x01c8 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO02__LPSPI6_SOUT                                          0x0018 0x01c8 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO02__LPUART5_CTS_B                                        0x0018 0x01c8 0x0484 0x05 0x01</div><div class='add'>+#define MX91_PAD_GPIO_IO02__LPI2C6_SDA                                           0x0018 0x01c8 0x040c 0x06 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO02__FLEXIO1_FLEXIO2                                      0x0018 0x01c8 0x0374 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_GPIO_IO03__GPIO2_IO3                                            0x001c 0x01cc 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO03__LPI2C4_SCL                                           0x001c 0x01cc 0x03f8 0x01 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC                                   0x001c 0x01cc 0x04b8 0x02 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC                                  0x001c 0x01cc 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO03__LPSPI6_SCK                                           0x001c 0x01cc 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO03__LPUART5_RTS_B                                        0x001c 0x01cc 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO03__LPI2C6_SCL                                           0x001c 0x01cc 0x0408 0x06 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO03__FLEXIO1_FLEXIO3                                      0x001c 0x01cc 0x0378 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_GPIO_IO04__GPIO2_IO4                                            0x0020 0x01d0 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO04__TPM3_CH0                                             0x0020 0x01d0 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO04__PDM_CLK                                              0x0020 0x01d0 0x0000 0x02 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA0                                  0x0020 0x01d0 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO04__LPSPI7_PCS0                                          0x0020 0x01d0 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO04__LPUART6_TX                                           0x0020 0x01d0 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO04__LPI2C6_SDA                                           0x0020 0x01d0 0x040c 0x06 0x01</div><div class='add'>+#define MX91_PAD_GPIO_IO04__FLEXIO1_FLEXIO4                                      0x0020 0x01d0 0x037c 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_GPIO_IO05__GPIO2_IO5                                            0x0024 0x01d4 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO05__TPM4_CH0                                             0x0024 0x01d4 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO05__PDM_BIT_STREAM0                                      0x0024 0x01d4 0x04c4 0x02 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA1                                  0x0024 0x01d4 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO05__LPSPI7_SIN                                           0x0024 0x01d4 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO05__LPUART6_RX                                           0x0024 0x01d4 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO05__LPI2C6_SCL                                           0x0024 0x01d4 0x0408 0x06 0x01</div><div class='add'>+#define MX91_PAD_GPIO_IO05__FLEXIO1_FLEXIO5                                      0x0024 0x01d4 0x0380 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_GPIO_IO06__GPIO2_IO6                                            0x0028 0x01d8 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO06__TPM5_CH0                                             0x0028 0x01d8 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO06__PDM_BIT_STREAM1                                      0x0028 0x01d8 0x04c8 0x02 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA2                                  0x0028 0x01d8 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO06__LPSPI7_SOUT                                          0x0028 0x01d8 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO06__LPUART6_CTS_B                                        0x0028 0x01d8 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO06__LPI2C7_SDA                                           0x0028 0x01d8 0x0414 0x06 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO06__FLEXIO1_FLEXIO6                                      0x0028 0x01d8 0x0384 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_GPIO_IO07__GPIO2_IO7                                            0x002c 0x01dc 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO07__LPSPI3_PCS1                                          0x002c 0x01dc 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO07__MEDIAMIX_CAM_DATA1                                   0x002c 0x01dc 0x0494 0x02 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA3                                  0x002c 0x01dc 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO07__LPSPI7_SCK                                           0x002c 0x01dc 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO07__LPUART6_RTS_B                                        0x002c 0x01dc 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO07__LPI2C7_SCL                                           0x002c 0x01dc 0x0410 0x06 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO07__FLEXIO1_FLEXIO7                                      0x002c 0x01dc 0x0388 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_GPIO_IO08__GPIO2_IO8                                            0x0030 0x01e0 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO08__LPSPI3_PCS0                                          0x0030 0x01e0 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO08__MEDIAMIX_CAM_DATA2                                   0x0030 0x01e0 0x0498 0x02 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA4                                  0x0030 0x01e0 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO08__TPM6_CH0                                             0x0030 0x01e0 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO08__LPUART7_TX                                           0x0030 0x01e0 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO08__LPI2C7_SDA                                           0x0030 0x01e0 0x0414 0x06 0x01</div><div class='add'>+#define MX91_PAD_GPIO_IO08__FLEXIO1_FLEXIO8                                      0x0030 0x01e0 0x038c 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_GPIO_IO09__GPIO2_IO9                                            0x0034 0x01e4 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO09__LPSPI3_SIN                                           0x0034 0x01e4 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO09__MEDIAMIX_CAM_DATA3                                   0x0034 0x01e4 0x049c 0x02 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA5                                  0x0034 0x01e4 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO09__TPM3_EXTCLK                                          0x0034 0x01e4 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO09__LPUART7_RX                                           0x0034 0x01e4 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO09__LPI2C7_SCL                                           0x0034 0x01e4 0x0410 0x06 0x01</div><div class='add'>+#define MX91_PAD_GPIO_IO09__FLEXIO1_FLEXIO9                                      0x0034 0x01e4 0x0390 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_GPIO_IO10__GPIO2_IO10                                           0x0038 0x01e8 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO10__LPSPI3_SOUT                                          0x0038 0x01e8 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO10__MEDIAMIX_CAM_DATA4                                   0x0038 0x01e8 0x04a0 0x02 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA6                                  0x0038 0x01e8 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO10__TPM4_EXTCLK                                          0x0038 0x01e8 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO10__LPUART7_CTS_B                                        0x0038 0x01e8 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO10__LPI2C8_SDA                                           0x0038 0x01e8 0x041c 0x06 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO10__FLEXIO1_FLEXIO10                                     0x0038 0x01e8 0x0394 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_GPIO_IO11__GPIO2_IO11                                           0x003c 0x01ec 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO11__LPSPI3_SCK                                           0x003c 0x01ec 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO11__MEDIAMIX_CAM_DATA5                                   0x003c 0x01ec 0x04a4 0x02 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA7                                  0x003c 0x01ec 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO11__TPM5_EXTCLK                                          0x003c 0x01ec 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO11__LPUART7_RTS_B                                        0x003c 0x01ec 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO11__LPI2C8_SCL                                           0x003c 0x01ec 0x0418 0x06 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO11__FLEXIO1_FLEXIO11                                     0x003c 0x01ec 0x0398 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_GPIO_IO12__GPIO2_IO12                                           0x0040 0x01f0 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO12__TPM3_CH2                                             0x0040 0x01f0 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO12__PDM_BIT_STREAM2                                      0x0040 0x01f0 0x04cc 0x02 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA8                                  0x0040 0x01f0 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO12__LPSPI8_PCS0                                          0x0040 0x01f0 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO12__LPUART8_TX                                           0x0040 0x01f0 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO12__LPI2C8_SDA                                           0x0040 0x01f0 0x041c 0x06 0x01</div><div class='add'>+#define MX91_PAD_GPIO_IO12__SAI3_RX_SYNC                                         0x0040 0x01f0 0x04dc 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_GPIO_IO13__GPIO2_IO13                                           0x0044 0x01f4 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO13__TPM4_CH2                                             0x0044 0x01f4 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO13__PDM_BIT_STREAM3                                      0x0044 0x01f4 0x04d0 0x02 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA9                                  0x0044 0x01f4 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO13__LPSPI8_SIN                                           0x0044 0x01f4 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO13__LPUART8_RX                                           0x0044 0x01f4 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO13__LPI2C8_SCL                                           0x0044 0x01f4 0x0418 0x06 0x01</div><div class='add'>+#define MX91_PAD_GPIO_IO13__FLEXIO1_FLEXIO13                                     0x0044 0x01f4 0x039c 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_GPIO_IO14__GPIO2_IO14                                           0x0048 0x01f8 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO14__LPUART3_TX                                           0x0048 0x01f8 0x0474 0x01 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA6                                   0x0048 0x01f8 0x04a8 0x02 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10                                 0x0048 0x01f8 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO14__LPSPI8_SOUT                                          0x0048 0x01f8 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO14__LPUART8_CTS_B                                        0x0048 0x01f8 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO14__LPUART4_TX                                           0x0048 0x01f8 0x0480 0x06 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO14__FLEXIO1_FLEXIO14                                     0x0048 0x01f8 0x03a0 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_GPIO_IO15__GPIO2_IO15                                           0x004c 0x01fc 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO15__LPUART3_RX                                           0x004c 0x01fc 0x0470 0x01 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA7                                   0x004c 0x01fc 0x04ac 0x02 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11                                 0x004c 0x01fc 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO15__LPSPI8_SCK                                           0x004c 0x01fc 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO15__LPUART8_RTS_B                                        0x004c 0x01fc 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO15__LPUART4_RX                                           0x004c 0x01fc 0x047c 0x06 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO15__FLEXIO1_FLEXIO15                                     0x004c 0x01fc 0x03a4 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_GPIO_IO16__GPIO2_IO16                                           0x0050 0x0200 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO16__SAI3_TX_BCLK                                         0x0050 0x0200 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO16__PDM_BIT_STREAM2                                      0x0050 0x0200 0x04cc 0x02 0x01</div><div class='add'>+#define MX91_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12                                 0x0050 0x0200 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO16__LPUART3_CTS_B                                        0x0050 0x0200 0x046c 0x04 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO16__LPSPI4_PCS2                                          0x0050 0x0200 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO16__LPUART4_CTS_B                                        0x0050 0x0200 0x0478 0x06 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO16__FLEXIO1_FLEXIO16                                     0x0050 0x0200 0x03a8 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_GPIO_IO17__GPIO2_IO17                                           0x0054 0x0204 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO17__SAI3_MCLK                                            0x0054 0x0204 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO17__MEDIAMIX_CAM_DATA8                                   0x0054 0x0204 0x04b0 0x02 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13                                 0x0054 0x0204 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO17__LPUART3_RTS_B                                        0x0054 0x0204 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO17__LPSPI4_PCS1                                          0x0054 0x0204 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO17__LPUART4_RTS_B                                        0x0054 0x0204 0x0000 0x06 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO17__FLEXIO1_FLEXIO17                                     0x0054 0x0204 0x03ac 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_GPIO_IO18__GPIO2_IO18                                           0x0058 0x0208 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO18__SAI3_RX_BCLK                                         0x0058 0x0208 0x04d8 0x01 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA9                                   0x0058 0x0208 0x04b4 0x02 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14                                 0x0058 0x0208 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO18__LPSPI5_PCS0                                          0x0058 0x0208 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO18__LPSPI4_PCS0                                          0x0058 0x0208 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO18__TPM5_CH2                                             0x0058 0x0208 0x0000 0x06 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO18__FLEXIO1_FLEXIO18                                     0x0058 0x0208 0x03b0 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_GPIO_IO19__GPIO2_IO19                                           0x005c 0x020c 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO19__SAI3_RX_SYNC                                         0x005c 0x020c 0x04dc 0x01 0x01</div><div class='add'>+#define MX91_PAD_GPIO_IO19__PDM_BIT_STREAM3                                      0x005c 0x020c 0x04d0 0x02 0x01</div><div class='add'>+#define MX91_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15                                 0x005c 0x020c 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO19__LPSPI5_SIN                                           0x005c 0x020c 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO19__LPSPI4_SIN                                           0x005c 0x020c 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO19__TPM6_CH2                                             0x005c 0x020c 0x0000 0x06 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO19__SAI3_TX_DATA0                                        0x005c 0x020c 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_GPIO_IO20__GPIO2_IO20                                           0x0060 0x0210 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO20__SAI3_RX_DATA0                                        0x0060 0x0210 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO20__PDM_BIT_STREAM0                                      0x0060 0x0210 0x04c4 0x02 0x01</div><div class='add'>+#define MX91_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16                                 0x0060 0x0210 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO20__LPSPI5_SOUT                                          0x0060 0x0210 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO20__LPSPI4_SOUT                                          0x0060 0x0210 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO20__TPM3_CH1                                             0x0060 0x0210 0x0000 0x06 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO20__FLEXIO1_FLEXIO20                                     0x0060 0x0210 0x03b4 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_GPIO_IO21__GPIO2_IO21                                           0x0064 0x0214 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO21__SAI3_TX_DATA0                                        0x0064 0x0214 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO21__PDM_CLK                                              0x0064 0x0214 0x0000 0x02 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17                                 0x0064 0x0214 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO21__LPSPI5_SCK                                           0x0064 0x0214 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO21__LPSPI4_SCK                                           0x0064 0x0214 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO21__TPM4_CH1                                             0x0064 0x0214 0x0000 0x06 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO21__SAI3_RX_BCLK                                         0x0064 0x0214 0x04d8 0x07 0x01</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_GPIO_IO22__GPIO2_IO22                                           0x0068 0x0218 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO22__USDHC3_CLK                                           0x0068 0x0218 0x04e8 0x01 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO22__SPDIF_IN                                             0x0068 0x0218 0x04e4 0x02 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18                                 0x0068 0x0218 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO22__TPM5_CH1                                             0x0068 0x0218 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO22__TPM6_EXTCLK                                          0x0068 0x0218 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO22__LPI2C5_SDA                                           0x0068 0x0218 0x0404 0x06 0x01</div><div class='add'>+#define MX91_PAD_GPIO_IO22__FLEXIO1_FLEXIO22                                     0x0068 0x0218 0x03b8 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_GPIO_IO23__GPIO2_IO23                                           0x006c 0x021c 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO23__USDHC3_CMD                                           0x006c 0x021c 0x04ec 0x01 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO23__SPDIF_OUT                                            0x006c 0x021c 0x0000 0x02 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19                                 0x006c 0x021c 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO23__TPM6_CH1                                             0x006c 0x021c 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO23__LPI2C5_SCL                                           0x006c 0x021c 0x0400 0x06 0x01</div><div class='add'>+#define MX91_PAD_GPIO_IO23__FLEXIO1_FLEXIO23                                     0x006c 0x021c 0x03bc 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_GPIO_IO24__GPIO2_IO24                                           0x0070 0x0220 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO24__USDHC3_DATA0                                         0x0070 0x0220 0x04f0 0x01 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20                                 0x0070 0x0220 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO24__TPM3_CH3                                             0x0070 0x0220 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO24__JTAG_MUX_TDO                                         0x0070 0x0220 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO24__LPSPI6_PCS1                                          0x0070 0x0220 0x0000 0x06 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO24__FLEXIO1_FLEXIO24                                     0x0070 0x0220 0x03c0 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_GPIO_IO25__GPIO2_IO25                                           0x0074 0x0224 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO25__USDHC3_DATA1                                         0x0074 0x0224 0x04f4 0x01 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO25__CAN2_TX                                              0x0074 0x0224 0x0000 0x02 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21                                 0x0074 0x0224 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO25__TPM4_CH3                                             0x0074 0x0224 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO25__JTAG_MUX_TCK                                         0x0074 0x0224 0x03d4 0x05 0x01</div><div class='add'>+#define MX91_PAD_GPIO_IO25__LPSPI7_PCS1                                          0x0074 0x0224 0x0000 0x06 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO25__FLEXIO1_FLEXIO25                                     0x0074 0x0224 0x03c4 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_GPIO_IO26__GPIO2_IO26                                           0x0078 0x0228 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO26__USDHC3_DATA2                                         0x0078 0x0228 0x04f8 0x01 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO26__PDM_BIT_STREAM1                                      0x0078 0x0228 0x04c8 0x02 0x01</div><div class='add'>+#define MX91_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22                                 0x0078 0x0228 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO26__TPM5_CH3                                             0x0078 0x0228 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO26__JTAG_MUX_TDI                                         0x0078 0x0228 0x03d8 0x05 0x01</div><div class='add'>+#define MX91_PAD_GPIO_IO26__LPSPI8_PCS1                                          0x0078 0x0228 0x0000 0x06 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO26__SAI3_TX_SYNC                                         0x0078 0x0228 0x04e0 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_GPIO_IO27__GPIO2_IO27                                           0x007c 0x022c 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO27__USDHC3_DATA3                                         0x007c 0x022c 0x04fc 0x01 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO27__CAN2_RX                                              0x007c 0x022c 0x0364 0x02 0x01</div><div class='add'>+#define MX91_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23                                 0x007c 0x022c 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO27__TPM6_CH3                                             0x007c 0x022c 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO27__JTAG_MUX_TMS                                         0x007c 0x022c 0x03dc 0x05 0x01</div><div class='add'>+#define MX91_PAD_GPIO_IO27__LPSPI5_PCS1                                          0x007c 0x022c 0x0000 0x06 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO27__FLEXIO1_FLEXIO27                                     0x007c 0x022c 0x03c8 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_GPIO_IO28__GPIO2_IO28                                           0x0080 0x0230 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO28__LPI2C3_SDA                                           0x0080 0x0230 0x03f4 0x01 0x01</div><div class='add'>+#define MX91_PAD_GPIO_IO28__CAN1_TX                                              0x0080 0x0230 0x0000 0x02 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO28__FLEXIO1_FLEXIO28                                     0x0080 0x0230 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_GPIO_IO29__GPIO2_IO29                                           0x0084 0x0234 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO29__LPI2C3_SCL                                           0x0084 0x0234 0x03f0 0x01 0x01</div><div class='add'>+#define MX91_PAD_GPIO_IO29__CAN1_RX                                              0x0084 0x0234 0x0360 0x02 0x00</div><div class='add'>+#define MX91_PAD_GPIO_IO29__FLEXIO1_FLEXIO29                                     0x0084 0x0234 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_CCM_CLKO1__CCMSRCGPCMIX_CLKO1                                   0x0088 0x0238 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_CCM_CLKO1__FLEXIO1_FLEXIO26                                     0x0088 0x0238 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_CCM_CLKO1__GPIO3_IO26                                           0x0088 0x0238 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_CCM_CLKO2__GPIO3_IO27                                           0x008c 0x023c 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_CCM_CLKO2__CCMSRCGPCMIX_CLKO2                                   0x008c 0x023c 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_CCM_CLKO2__FLEXIO1_FLEXIO27                                     0x008c 0x023c 0x03c8 0x04 0x01</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3                                   0x0090 0x0240 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_CCM_CLKO3__FLEXIO2_FLEXIO28                                     0x0090 0x0240 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_CCM_CLKO3__GPIO4_IO28                                           0x0090 0x0240 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_CCM_CLKO4__CCMSRCGPCMIX_CLKO4                                   0x0094 0x0244 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_CCM_CLKO4__FLEXIO2_FLEXIO29                                     0x0094 0x0244 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_CCM_CLKO4__GPIO4_IO29                                           0x0094 0x0244 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_ENET1_MDC__ENET1_MDC                                            0x0098 0x0248 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_ENET1_MDC__LPUART3_DCB_B                                        0x0098 0x0248 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_ENET1_MDC__I3C2_SCL                                             0x0098 0x0248 0x03cc 0x02 0x00</div><div class='add'>+#define MX91_PAD_ENET1_MDC__HSIOMIX_OTG_ID1                                      0x0098 0x0248 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_ENET1_MDC__FLEXIO2_FLEXIO0                                      0x0098 0x0248 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_ENET1_MDC__GPIO4_IO0                                            0x0098 0x0248 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_ENET1_MDC__LPI2C1_SCL                                           0x0098 0x0248 0x03e0 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO                                       0x009c 0x024c 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_ENET1_MDIO__LPUART3_RIN_B                                       0x009c 0x024c 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_ENET1_MDIO__I3C2_SDA                                            0x009c 0x024c 0x03d0 0x02 0x00</div><div class='add'>+#define MX91_PAD_ENET1_MDIO__HSIOMIX_OTG_PWR1                                    0x009c 0x024c 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_ENET1_MDIO__FLEXIO2_FLEXIO1                                     0x009c 0x024c 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_ENET1_MDIO__GPIO4_IO1                                           0x009c 0x024c 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_ENET1_MDIO__LPI2C1_SDA                                          0x009c 0x024c 0x03e4 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3                                   0x00a0 0x0250 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_ENET1_TD3__CAN2_TX                                              0x00a0 0x0250 0x0000 0x02 0x00</div><div class='add'>+#define MX91_PAD_ENET1_TD3__HSIOMIX_OTG_ID2                                      0x00a0 0x0250 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_ENET1_TD3__FLEXIO2_FLEXIO2                                      0x00a0 0x0250 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_ENET1_TD3__GPIO4_IO2                                            0x00a0 0x0250 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_ENET1_TD3__LPI2C2_SCL                                           0x00a0 0x0250 0x03e8 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2                                   0x00a4 0x0254 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_ENET1_TD2__ENET_QOS_CLOCK_GENERATE_CLK                          0x00a4 0x0254 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_ENET1_TD2__CAN2_RX                                              0x00a4 0x0254 0x0364 0x02 0x02</div><div class='add'>+#define MX91_PAD_ENET1_TD2__HSIOMIX_OTG_OC2                                      0x00a4 0x0254 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_ENET1_TD2__FLEXIO2_FLEXIO3                                      0x00a4 0x0254 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_ENET1_TD2__GPIO4_IO3                                            0x00a4 0x0254 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_ENET1_TD2__LPI2C2_SDA                                           0x00a4 0x0254 0x03ec 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1                                      0x00a8 0x0258 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_ENET1_TD1__LPUART3_RTS_B                                        0x00a8 0x0258 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_ENET1_TD1__I3C2_PUR                                             0x00a8 0x0258 0x0000 0x02 0x00</div><div class='add'>+#define MX91_PAD_ENET1_TD1__HSIOMIX_OTG_OC1                                      0x00a8 0x0258 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_ENET1_TD1__FLEXIO2_FLEXIO4                                      0x00a8 0x0258 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_ENET1_TD1__GPIO4_IO4                                            0x00a8 0x0258 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_ENET1_TD1__I3C2_PUR_B                                           0x00a8 0x0258 0x0000 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0                                   0x00ac 0x025c 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_ENET1_TD0__LPUART3_TX                                           0x00ac 0x025c 0x0474 0x01 0x01</div><div class='add'>+#define MX91_PAD_ENET1_TD0__FLEXIO2_FLEXIO5                                      0x00ac 0x025c 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_ENET1_TD0__GPIO4_IO5                                            0x00ac 0x025c 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL                             0x00b0 0x0260 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_ENET1_TX_CTL__LPUART3_DTR_B                                     0x00b0 0x0260 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO6                                   0x00b0 0x0260 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_ENET1_TX_CTL__GPIO4_IO6                                         0x00b0 0x0260 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_ENET1_TX_CTL__LPSPI2_SCK                                        0x00b0 0x0260 0x043c 0x02 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK                   0x00b4 0x0264 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_ENET1_TXC__ENET_QOS_TX_ER                                       0x00b4 0x0264 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_ENET1_TXC__FLEXIO2_FLEXIO7                                      0x00b4 0x0264 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_ENET1_TXC__GPIO4_IO7                                            0x00b4 0x0264 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_ENET1_TXC__LPSPI2_SIN                                           0x00b4 0x0264 0x0440 0x02 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL                             0x00b8 0x0268 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_ENET1_RX_CTL__LPUART3_DSR_B                                     0x00b8 0x0268 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_ENET1_RX_CTL__HSIOMIX_OTG_PWR2                                  0x00b8 0x0268 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO8                                   0x00b8 0x0268 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_ENET1_RX_CTL__GPIO4_IO8                                         0x00b8 0x0268 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_ENET1_RX_CTL__LPSPI2_PCS0                                       0x00b8 0x0268 0x0434 0x02 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC                                   0x00bc 0x026c 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_ENET1_RXC__ENET_QOS_RX_ER                                       0x00bc 0x026c 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_ENET1_RXC__FLEXIO2_FLEXIO9                                      0x00bc 0x026c 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_ENET1_RXC__GPIO4_IO9                                            0x00bc 0x026c 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_ENET1_RXC__LPSPI2_SOUT                                          0x00bc 0x026c 0x0444 0x02 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0                                   0x00c0 0x0270 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_ENET1_RD0__LPUART3_RX                                           0x00c0 0x0270 0x0470 0x01 0x01</div><div class='add'>+#define MX91_PAD_ENET1_RD0__FLEXIO2_FLEXIO10                                     0x00c0 0x0270 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_ENET1_RD0__GPIO4_IO10                                           0x00c0 0x0270 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1                                   0x00c4 0x0274 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_ENET1_RD1__LPUART3_CTS_B                                        0x00c4 0x0274 0x046c 0x01 0x01</div><div class='add'>+#define MX91_PAD_ENET1_RD1__LPTMR2_ALT1                                          0x00c4 0x0274 0x0448 0x03 0x00</div><div class='add'>+#define MX91_PAD_ENET1_RD1__FLEXIO2_FLEXIO11                                     0x00c4 0x0274 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_ENET1_RD1__GPIO4_IO11                                           0x00c4 0x0274 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2                                   0x00c8 0x0278 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_ENET1_RD2__LPTMR2_ALT2                                          0x00c8 0x0278 0x044c 0x03 0x00</div><div class='add'>+#define MX91_PAD_ENET1_RD2__FLEXIO2_FLEXIO12                                     0x00c8 0x0278 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_ENET1_RD2__GPIO4_IO12                                           0x00c8 0x0278 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3                                   0x00cc 0x027c 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_ENET1_RD3__FLEXSPI1_TESTER_TRIGGER                              0x00cc 0x027c 0x0000 0x02 0x00</div><div class='add'>+#define MX91_PAD_ENET1_RD3__LPTMR2_ALT3                                          0x00cc 0x027c 0x0450 0x03 0x00</div><div class='add'>+#define MX91_PAD_ENET1_RD3__FLEXIO2_FLEXIO13                                     0x00cc 0x027c 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_ENET1_RD3__GPIO4_IO13                                           0x00cc 0x027c 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_ENET2_MDC__ENET2_MDC                                            0x00d0 0x0280 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_ENET2_MDC__LPUART4_DCB_B                                        0x00d0 0x0280 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_ENET2_MDC__SAI2_RX_SYNC                                         0x00d0 0x0280 0x0000 0x02 0x00</div><div class='add'>+#define MX91_PAD_ENET2_MDC__FLEXIO2_FLEXIO14                                     0x00d0 0x0280 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_ENET2_MDC__GPIO4_IO14                                           0x00d0 0x0280 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_ENET2_MDC__MEDIAMIX_CAM_CLK                                     0x00d0 0x0280 0x04bc 0x06 0x01</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_ENET2_MDIO__ENET2_MDIO                                          0x00d4 0x0284 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_ENET2_MDIO__LPUART4_RIN_B                                       0x00d4 0x0284 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_ENET2_MDIO__SAI2_RX_BCLK                                        0x00d4 0x0284 0x0000 0x02 0x00</div><div class='add'>+#define MX91_PAD_ENET2_MDIO__FLEXIO2_FLEXIO15                                    0x00d4 0x0284 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_ENET2_MDIO__GPIO4_IO15                                          0x00d4 0x0284 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_ENET2_MDIO__MEDIAMIX_CAM_DATA0                                  0x00d4 0x0284 0x0490 0x06 0x01</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_ENET2_TD3__SAI2_RX_DATA0                                        0x00d8 0x0288 0x0000 0x02 0x00</div><div class='add'>+#define MX91_PAD_ENET2_TD3__FLEXIO2_FLEXIO16                                     0x00d8 0x0288 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_ENET2_TD3__GPIO4_IO16                                           0x00d8 0x0288 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_ENET2_TD3__MEDIAMIX_CAM_VSYNC                                   0x00d8 0x0288 0x04c0 0x06 0x01</div><div class='add'>+#define MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3                                      0x00d8 0x0288 0x0000 0x00 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2                                      0x00dc 0x028c 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_ENET2_TD2__ENET2_TX_CLK2                                        0x00dc 0x028c 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_ENET2_TD2__FLEXIO2_FLEXIO17                                     0x00dc 0x028c 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_ENET2_TD2__GPIO4_IO17                                           0x00dc 0x028c 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_ENET2_TD2__MEDIAMIX_CAM_HSYNC                                   0x00dc 0x028c 0x04b8 0x06 0x01</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1                                      0x00e0 0x0290 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_ENET2_TD1__LPUART4_RTS_B                                        0x00e0 0x0290 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_ENET2_TD1__FLEXIO2_FLEXIO18                                     0x00e0 0x0290 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_ENET2_TD1__GPIO4_IO18                                           0x00e0 0x0290 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_ENET2_TD1__MEDIAMIX_CAM_DATA1                                   0x00e0 0x0290 0x0494 0x06 0x01</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0                                      0x00e4 0x0294 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_ENET2_TD0__LPUART4_TX                                           0x00e4 0x0294 0x0480 0x01 0x01</div><div class='add'>+#define MX91_PAD_ENET2_TD0__FLEXIO2_FLEXIO19                                     0x00e4 0x0294 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_ENET2_TD0__GPIO4_IO19                                           0x00e4 0x0294 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_ENET2_TD0__MEDIAMIX_CAM_DATA2                                   0x00e4 0x0294 0x0498 0x06 0x01</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL                                0x00e8 0x0298 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_ENET2_TX_CTL__LPUART4_DTR_B                                     0x00e8 0x0298 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_ENET2_TX_CTL__SAI2_TX_SYNC                                      0x00e8 0x0298 0x0000 0x02 0x00</div><div class='add'>+#define MX91_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO20                                  0x00e8 0x0298 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_ENET2_TX_CTL__GPIO4_IO20                                        0x00e8 0x0298 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_ENET2_TX_CTL__MEDIAMIX_CAM_DATA3                                0x00e8 0x0298 0x049c 0x06 0x01</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC                                      0x00ec 0x029c 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_ENET2_TXC__ENET2_TX_ER                                          0x00ec 0x029c 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_ENET2_TXC__SAI2_TX_BCLK                                         0x00ec 0x029c 0x0000 0x02 0x00</div><div class='add'>+#define MX91_PAD_ENET2_TXC__FLEXIO2_FLEXIO21                                     0x00ec 0x029c 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_ENET2_TXC__GPIO4_IO21                                           0x00ec 0x029c 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_ENET2_TXC__MEDIAMIX_CAM_DATA4                                   0x00ec 0x029c 0x04a0 0x06 0x01</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL                                0x00f0 0x02a0 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_ENET2_RX_CTL__LPUART4_DSR_B                                     0x00f0 0x02a0 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_ENET2_RX_CTL__SAI2_TX_DATA0                                     0x00f0 0x02a0 0x0000 0x02 0x00</div><div class='add'>+#define MX91_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO22                                  0x00f0 0x02a0 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_ENET2_RX_CTL__GPIO4_IO22                                        0x00f0 0x02a0 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_ENET2_RX_CTL__MEDIAMIX_CAM_DATA5                                0x00f0 0x02a0 0x04a4 0x06 0x01</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC                                      0x00f4 0x02a4 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_ENET2_RXC__ENET2_RX_ER                                          0x00f4 0x02a4 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_ENET2_RXC__FLEXIO2_FLEXIO23                                     0x00f4 0x02a4 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_ENET2_RXC__GPIO4_IO23                                           0x00f4 0x02a4 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_ENET2_RXC__MEDIAMIX_CAM_DATA6                                   0x00f4 0x02a4 0x04a8 0x06 0x01</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0                                      0x00f8 0x02a8 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_ENET2_RD0__LPUART4_RX                                           0x00f8 0x02a8 0x047c 0x01 0x01</div><div class='add'>+#define MX91_PAD_ENET2_RD0__FLEXIO2_FLEXIO24                                     0x00f8 0x02a8 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_ENET2_RD0__GPIO4_IO24                                           0x00f8 0x02a8 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_ENET2_RD0__MEDIAMIX_CAM_DATA7                                   0x00f8 0x02a8 0x04ac 0x06 0x01</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1                                      0x00fc 0x02ac 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_ENET2_RD1__SPDIF_IN                                             0x00fc 0x02ac 0x04e4 0x01 0x01</div><div class='add'>+#define MX91_PAD_ENET2_RD1__FLEXIO2_FLEXIO25                                     0x00fc 0x02ac 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_ENET2_RD1__GPIO4_IO25                                           0x00fc 0x02ac 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_ENET2_RD1__MEDIAMIX_CAM_DATA8                                   0x00fc 0x02ac 0x04b0 0x06 0x01</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2                                      0x0100 0x02b0 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_ENET2_RD2__LPUART4_CTS_B                                        0x0100 0x02b0 0x0478 0x01 0x01</div><div class='add'>+#define MX91_PAD_ENET2_RD2__SAI2_MCLK                                            0x0100 0x02b0 0x0000 0x02 0x00</div><div class='add'>+#define MX91_PAD_ENET2_RD2__MQS2_RIGHT                                           0x0100 0x02b0 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_ENET2_RD2__FLEXIO2_FLEXIO26                                     0x0100 0x02b0 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_ENET2_RD2__GPIO4_IO26                                           0x0100 0x02b0 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_ENET2_RD2__MEDIAMIX_CAM_DATA9                                   0x0100 0x02b0 0x04b4 0x06 0x01</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3                                      0x0104 0x02b4 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_ENET2_RD3__SPDIF_OUT                                            0x0104 0x02b4 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_ENET2_RD3__SPDIF_IN                                             0x0104 0x02b4 0x04e4 0x02 0x02</div><div class='add'>+#define MX91_PAD_ENET2_RD3__MQS2_LEFT                                            0x0104 0x02b4 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_ENET2_RD3__FLEXIO2_FLEXIO27                                     0x0104 0x02b4 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_ENET2_RD3__GPIO4_IO27                                           0x0104 0x02b4 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_SD1_CLK__FLEXIO1_FLEXIO8                                        0x0108 0x02b8 0x038c 0x04 0x01</div><div class='add'>+#define MX91_PAD_SD1_CLK__GPIO3_IO8                                              0x0108 0x02b8 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_SD1_CLK__USDHC1_CLK                                             0x0108 0x02b8 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_SD1_CLK__LPSPI2_SCK                                             0x0108 0x02b8 0x043c 0x03 0x01</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_SD1_CMD__USDHC1_CMD                                             0x010c 0x02bc 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_SD1_CMD__FLEXIO1_FLEXIO9                                        0x010c 0x02bc 0x0390 0x04 0x01</div><div class='add'>+#define MX91_PAD_SD1_CMD__GPIO3_IO9                                              0x010c 0x02bc 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_SD1_CMD__LPSPI2_SIN                                             0x010c 0x02bc 0x0440 0x03 0x01</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_SD1_DATA0__USDHC1_DATA0                                         0x0110 0x02c0 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_SD1_DATA0__FLEXIO1_FLEXIO10                                     0x0110 0x02c0 0x0394 0x04 0x01</div><div class='add'>+#define MX91_PAD_SD1_DATA0__GPIO3_IO10                                           0x0110 0x02c0 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_SD1_DATA0__LPSPI2_PCS0                                          0x0110 0x02c0 0x0434 0x03 0x01</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_SD1_DATA1__USDHC1_DATA1                                         0x0114 0x02c4 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_SD1_DATA1__FLEXIO1_FLEXIO11                                     0x0114 0x02c4 0x0398 0x04 0x01</div><div class='add'>+#define MX91_PAD_SD1_DATA1__GPIO3_IO11                                           0x0114 0x02c4 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_SD1_DATA1__CCMSRCGPCMIX_INT_BOOT                                0x0114 0x02c4 0x0000 0x06 0x00</div><div class='add'>+#define MX91_PAD_SD1_DATA1__LPSPI2_SOUT                                          0x0114 0x02c4 0x0444 0x03 0x01</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_SD1_DATA2__USDHC1_DATA2                                         0x0118 0x02c8 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_SD1_DATA2__FLEXIO1_FLEXIO12                                     0x0118 0x02c8 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_SD1_DATA2__GPIO3_IO12                                           0x0118 0x02c8 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_SD1_DATA2__CCMSRCGPCMIX_PMIC_READY                              0x0118 0x02c8 0x0000 0x06 0x00</div><div class='add'>+#define MX91_PAD_SD1_DATA2__LPSPI2_PCS1                                          0x0118 0x02c8 0x0438 0x03 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_SD1_DATA3__USDHC1_DATA3                                         0x011c 0x02cc 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B                                     0x011c 0x02cc 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_SD1_DATA3__FLEXIO1_FLEXIO13                                     0x011c 0x02cc 0x039c 0x04 0x01</div><div class='add'>+#define MX91_PAD_SD1_DATA3__GPIO3_IO13                                           0x011c 0x02cc 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_SD1_DATA3__LPSPI1_PCS1                                          0x011c 0x02cc 0x0424 0x03 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_SD1_DATA4__USDHC1_DATA4                                         0x0120 0x02d0 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_SD1_DATA4__FLEXSPI1_A_DATA4                                     0x0120 0x02d0 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_SD1_DATA4__FLEXIO1_FLEXIO14                                     0x0120 0x02d0 0x03a0 0x04 0x01</div><div class='add'>+#define MX91_PAD_SD1_DATA4__GPIO3_IO14                                           0x0120 0x02d0 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_SD1_DATA4__LPSPI1_PCS0                                          0x0120 0x02d0 0x0420 0x03 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_SD1_DATA5__USDHC1_DATA5                                         0x0124 0x02d4 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_SD1_DATA5__FLEXSPI1_A_DATA5                                     0x0124 0x02d4 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_SD1_DATA5__USDHC1_RESET_B                                       0x0124 0x02d4 0x0000 0x02 0x00</div><div class='add'>+#define MX91_PAD_SD1_DATA5__FLEXIO1_FLEXIO15                                     0x0124 0x02d4 0x03a4 0x04 0x01</div><div class='add'>+#define MX91_PAD_SD1_DATA5__GPIO3_IO15                                           0x0124 0x02d4 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_SD1_DATA5__LPSPI1_SIN                                           0x0124 0x02d4 0x042c 0x03 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_SD1_DATA6__USDHC1_DATA6                                         0x0128 0x02d8 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_SD1_DATA6__FLEXSPI1_A_DATA6                                     0x0128 0x02d8 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_SD1_DATA6__USDHC1_CD_B                                          0x0128 0x02d8 0x0000 0x02 0x00</div><div class='add'>+#define MX91_PAD_SD1_DATA6__FLEXIO1_FLEXIO16                                     0x0128 0x02d8 0x03a8 0x04 0x01</div><div class='add'>+#define MX91_PAD_SD1_DATA6__GPIO3_IO16                                           0x0128 0x02d8 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_SD1_DATA6__LPSPI1_SCK                                           0x0128 0x02d8 0x0428 0x03 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_SD1_DATA7__USDHC1_DATA7                                         0x012c 0x02dc 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_SD1_DATA7__FLEXSPI1_A_DATA7                                     0x012c 0x02dc 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_SD1_DATA7__USDHC1_WP                                            0x012c 0x02dc 0x0000 0x02 0x00</div><div class='add'>+#define MX91_PAD_SD1_DATA7__FLEXIO1_FLEXIO17                                     0x012c 0x02dc 0x03ac 0x04 0x01</div><div class='add'>+#define MX91_PAD_SD1_DATA7__GPIO3_IO17                                           0x012c 0x02dc 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_SD1_DATA7__LPSPI1_SOUT                                          0x012c 0x02dc 0x0430 0x03 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_SD1_STROBE__USDHC1_STROBE                                       0x0130 0x02e0 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_SD1_STROBE__FLEXSPI1_A_DQS                                      0x0130 0x02e0 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_SD1_STROBE__FLEXIO1_FLEXIO18                                    0x0130 0x02e0 0x03b0 0x04 0x01</div><div class='add'>+#define MX91_PAD_SD1_STROBE__GPIO3_IO18                                          0x0130 0x02e0 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_SD2_VSELECT__USDHC2_VSELECT                                     0x0134 0x02e4 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_SD2_VSELECT__USDHC2_WP                                          0x0134 0x02e4 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_SD2_VSELECT__LPTMR2_ALT3                                        0x0134 0x02e4 0x0450 0x02 0x01</div><div class='add'>+#define MX91_PAD_SD2_VSELECT__FLEXIO1_FLEXIO19                                   0x0134 0x02e4 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_SD2_VSELECT__GPIO3_IO19                                         0x0134 0x02e4 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_SD2_VSELECT__CCMSRCGPCMIX_EXT_CLK1                              0x0134 0x02e4 0x0368 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_SD3_CLK__USDHC3_CLK                                             0x0138 0x02e8 0x04e8 0x00 0x01</div><div class='add'>+#define MX91_PAD_SD3_CLK__FLEXSPI1_A_SCLK                                        0x0138 0x02e8 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_SD3_CLK__LPUART1_CTS_B                                          0x0138 0x02e8 0x0454 0x02 0x00</div><div class='add'>+#define MX91_PAD_SD3_CLK__FLEXIO1_FLEXIO20                                       0x0138 0x02e8 0x03b4 0x04 0x01</div><div class='add'>+#define MX91_PAD_SD3_CLK__GPIO3_IO20                                             0x0138 0x02e8 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_SD3_CMD__USDHC3_CMD                                             0x013c 0x02ec 0x04ec 0x00 0x01</div><div class='add'>+#define MX91_PAD_SD3_CMD__FLEXSPI1_A_SS0_B                                       0x013c 0x02ec 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_SD3_CMD__LPUART1_RTS_B                                          0x013c 0x02ec 0x0000 0x02 0x00</div><div class='add'>+#define MX91_PAD_SD3_CMD__FLEXIO1_FLEXIO21                                       0x013c 0x02ec 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_SD3_CMD__GPIO3_IO21                                             0x013c 0x02ec 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_SD3_DATA0__USDHC3_DATA0                                         0x0140 0x02f0 0x04f0 0x00 0x01</div><div class='add'>+#define MX91_PAD_SD3_DATA0__FLEXSPI1_A_DATA0                                     0x0140 0x02f0 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_SD3_DATA0__LPUART2_CTS_B                                        0x0140 0x02f0 0x0460 0x02 0x00</div><div class='add'>+#define MX91_PAD_SD3_DATA0__FLEXIO1_FLEXIO22                                     0x0140 0x02f0 0x03b8 0x04 0x01</div><div class='add'>+#define MX91_PAD_SD3_DATA0__GPIO3_IO22                                           0x0140 0x02f0 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_SD3_DATA1__USDHC3_DATA1                                         0x0144 0x02f4 0x04f4 0x00 0x01</div><div class='add'>+#define MX91_PAD_SD3_DATA1__FLEXSPI1_A_DATA1                                     0x0144 0x02f4 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_SD3_DATA1__LPUART2_RTS_B                                        0x0144 0x02f4 0x0000 0x02 0x00</div><div class='add'>+#define MX91_PAD_SD3_DATA1__FLEXIO1_FLEXIO23                                     0x0144 0x02f4 0x03bc 0x04 0x01</div><div class='add'>+#define MX91_PAD_SD3_DATA1__GPIO3_IO23                                           0x0144 0x02f4 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_SD3_DATA2__USDHC3_DATA2                                         0x0148 0x02f8 0x04f8 0x00 0x01</div><div class='add'>+#define MX91_PAD_SD3_DATA2__LPI2C4_SDA                                           0x0148 0x02f8 0x03fc 0x02 0x01</div><div class='add'>+#define MX91_PAD_SD3_DATA2__FLEXSPI1_A_DATA2                                     0x0148 0x02f8 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_SD3_DATA2__FLEXIO1_FLEXIO24                                     0x0148 0x02f8 0x03c0 0x04 0x01</div><div class='add'>+#define MX91_PAD_SD3_DATA2__GPIO3_IO24                                           0x0148 0x02f8 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_SD3_DATA3__USDHC3_DATA3                                         0x014c 0x02fc 0x04fc 0x00 0x01</div><div class='add'>+#define MX91_PAD_SD3_DATA3__FLEXSPI1_A_DATA3                                     0x014c 0x02fc 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_SD3_DATA3__LPI2C4_SCL                                           0x014c 0x02fc 0x03f8 0x02 0x01</div><div class='add'>+#define MX91_PAD_SD3_DATA3__FLEXIO1_FLEXIO25                                     0x014c 0x02fc 0x03c4 0x04 0x01</div><div class='add'>+#define MX91_PAD_SD3_DATA3__GPIO3_IO25                                           0x014c 0x02fc 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_SD2_CD_B__USDHC2_CD_B                                           0x0150 0x0300 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_SD2_CD_B__ENET_QOS_1588_EVENT0_IN                               0x0150 0x0300 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_SD2_CD_B__I3C2_SCL                                              0x0150 0x0300 0x03cc 0x02 0x01</div><div class='add'>+#define MX91_PAD_SD2_CD_B__FLEXIO1_FLEXIO0                                       0x0150 0x0300 0x036c 0x04 0x01</div><div class='add'>+#define MX91_PAD_SD2_CD_B__GPIO3_IO0                                             0x0150 0x0300 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_SD2_CD_B__LPI2C1_SCL                                            0x0150 0x0300 0x03e0 0x03 0x01</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_SD2_CLK__USDHC2_CLK                                             0x0154 0x0304 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_SD2_CLK__ENET_QOS_1588_EVENT0_OUT                               0x0154 0x0304 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_SD2_CLK__I2C1_SDA                                               0x0154 0x0304 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_SD2_CLK__I3C2_SDA                                               0x0154 0x0304 0x03d0 0x02 0x01</div><div class='add'>+#define MX91_PAD_SD2_CLK__FLEXIO1_FLEXIO1                                        0x0154 0x0304 0x0370 0x04 0x01</div><div class='add'>+#define MX91_PAD_SD2_CLK__GPIO3_IO1                                              0x0154 0x0304 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0                                  0x0154 0x0304 0x0000 0x06 0x00</div><div class='add'>+#define MX91_PAD_SD2_CLK__LPI2C1_SDA                                             0x0154 0x0304 0x03e4 0x03 0x01</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_SD2_CMD__USDHC2_CMD                                             0x0158 0x0308 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_SD2_CMD__ENET2_1588_EVENT0_IN                                   0x0158 0x0308 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_SD2_CMD__I3C2_PUR                                               0x0158 0x0308 0x0000 0x02 0x00</div><div class='add'>+#define MX91_PAD_SD2_CMD__I3C2_PUR_B                                             0x0158 0x0308 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_SD2_CMD__FLEXIO1_FLEXIO2                                        0x0158 0x0308 0x0374 0x04 0x01</div><div class='add'>+#define MX91_PAD_SD2_CMD__GPIO3_IO2                                              0x0158 0x0308 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1                                  0x0158 0x0308 0x0000 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_SD2_DATA0__USDHC2_DATA0                                         0x015c 0x030c 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_SD2_DATA0__ENET2_1588_EVENT0_OUT                                0x015c 0x030c 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_SD2_DATA0__CAN2_TX                                              0x015c 0x030c 0x0000 0x02 0x00</div><div class='add'>+#define MX91_PAD_SD2_DATA0__FLEXIO1_FLEXIO3                                      0x015c 0x030c 0x0378 0x04 0x01</div><div class='add'>+#define MX91_PAD_SD2_DATA0__GPIO3_IO3                                            0x015c 0x030c 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_SD2_DATA0__LPUART1_TX                                           0x015c 0x030c 0x045c 0x03 0x00</div><div class='add'>+#define MX91_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2                                0x015c 0x030c 0x0000 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_SD2_DATA1__USDHC2_DATA1                                         0x0160 0x0310 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_SD2_DATA1__ENET2_1588_EVENT1_IN                                 0x0160 0x0310 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_SD2_DATA1__CAN2_RX                                              0x0160 0x0310 0x0364 0x02 0x03</div><div class='add'>+#define MX91_PAD_SD2_DATA1__FLEXIO1_FLEXIO4                                      0x0160 0x0310 0x037c 0x04 0x01</div><div class='add'>+#define MX91_PAD_SD2_DATA1__GPIO3_IO4                                            0x0160 0x0310 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_SD2_DATA1__LPUART1_RX                                           0x0160 0x0310 0x0458 0x03 0x00</div><div class='add'>+#define MX91_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT                                    0x0160 0x0310 0x0000 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_SD2_DATA2__USDHC2_DATA2                                         0x0164 0x0314 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_SD2_DATA2__ENET2_1588_EVENT1_OUT                                0x0164 0x0314 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_SD2_DATA2__MQS2_RIGHT                                           0x0164 0x0314 0x0000 0x02 0x00</div><div class='add'>+#define MX91_PAD_SD2_DATA2__FLEXIO1_FLEXIO5                                      0x0164 0x0314 0x0380 0x04 0x01</div><div class='add'>+#define MX91_PAD_SD2_DATA2__GPIO3_IO5                                            0x0164 0x0314 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_SD2_DATA2__LPUART2_TX                                           0x0164 0x0314 0x0468 0x03 0x00</div><div class='add'>+#define MX91_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP                                    0x0164 0x0314 0x0000 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_SD2_DATA3__USDHC2_DATA3                                         0x0168 0x0318 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_SD2_DATA3__LPTMR2_ALT1                                          0x0168 0x0318 0x0448 0x01 0x01</div><div class='add'>+#define MX91_PAD_SD2_DATA3__MQS2_LEFT                                            0x0168 0x0318 0x0000 0x02 0x00</div><div class='add'>+#define MX91_PAD_SD2_DATA3__FLEXIO1_FLEXIO6                                      0x0168 0x0318 0x0384 0x04 0x01</div><div class='add'>+#define MX91_PAD_SD2_DATA3__GPIO3_IO6                                            0x0168 0x0318 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_SD2_DATA3__LPUART2_RX                                           0x0168 0x0318 0x0464 0x03 0x00</div><div class='add'>+#define MX91_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET                             0x0168 0x0318 0x0000 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_SD2_RESET_B__USDHC2_RESET_B                                     0x016c 0x031c 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_SD2_RESET_B__LPTMR2_ALT2                                        0x016c 0x031c 0x044c 0x01 0x01</div><div class='add'>+#define MX91_PAD_SD2_RESET_B__FLEXIO1_FLEXIO7                                    0x016c 0x031c 0x0388 0x04 0x01</div><div class='add'>+#define MX91_PAD_SD2_RESET_B__GPIO3_IO7                                          0x016c 0x031c 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET                          0x016c 0x031c 0x0000 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_I2C1_SCL__LPI2C1_SCL                                            0x0170 0x0320 0x03e0 0x00 0x02</div><div class='add'>+#define MX91_PAD_I2C1_SCL__I3C1_SCL                                              0x0170 0x0320 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_I2C1_SCL__LPUART1_DCB_B                                         0x0170 0x0320 0x0000 0x02 0x00</div><div class='add'>+#define MX91_PAD_I2C1_SCL__TPM2_CH0                                              0x0170 0x0320 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_I2C1_SCL__GPIO1_IO0                                             0x0170 0x0320 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_I2C1_SDA__LPI2C1_SDA                                            0x0174 0x0324 0x03e4 0x00 0x02</div><div class='add'>+#define MX91_PAD_I2C1_SDA__I3C1_SDA                                              0x0174 0x0324 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_I2C1_SDA__LPUART1_RIN_B                                         0x0174 0x0324 0x0000 0x02 0x00</div><div class='add'>+#define MX91_PAD_I2C1_SDA__TPM2_CH1                                              0x0174 0x0324 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_I2C1_SDA__GPIO1_IO1                                             0x0174 0x0324 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_I2C2_SCL__LPI2C2_SCL                                            0x0178 0x0328 0x03e8 0x00 0x01</div><div class='add'>+#define MX91_PAD_I2C2_SCL__I3C1_PUR                                              0x0178 0x0328 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_I2C2_SCL__LPUART2_DCB_B                                         0x0178 0x0328 0x0000 0x02 0x00</div><div class='add'>+#define MX91_PAD_I2C2_SCL__TPM2_CH2                                              0x0178 0x0328 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_I2C2_SCL__SAI1_RX_SYNC                                          0x0178 0x0328 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_I2C2_SCL__GPIO1_IO2                                             0x0178 0x0328 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_I2C2_SCL__I3C1_PUR_B                                            0x0178 0x0328 0x0000 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_I2C2_SDA__LPI2C2_SDA                                            0x017c 0x032c 0x03ec 0x00 0x01</div><div class='add'>+#define MX91_PAD_I2C2_SDA__LPUART2_RIN_B                                         0x017c 0x032c 0x0000 0x02 0x00</div><div class='add'>+#define MX91_PAD_I2C2_SDA__TPM2_CH3                                              0x017c 0x032c 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_I2C2_SDA__SAI1_RX_BCLK                                          0x017c 0x032c 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_I2C2_SDA__GPIO1_IO3                                             0x017c 0x032c 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_UART1_RXD__LPUART1_RX                                           0x0180 0x0330 0x0458 0x00 0x01</div><div class='add'>+#define MX91_PAD_UART1_RXD__ELE_UART_RX                                          0x0180 0x0330 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_UART1_RXD__LPSPI2_SIN                                           0x0180 0x0330 0x0440 0x02 0x02</div><div class='add'>+#define MX91_PAD_UART1_RXD__TPM1_CH0                                             0x0180 0x0330 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_UART1_RXD__GPIO1_IO4                                            0x0180 0x0330 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_UART1_TXD__LPUART1_TX                                           0x0184 0x0334 0x045c 0x00 0x01</div><div class='add'>+#define MX91_PAD_UART1_TXD__ELE_UART_TX                                          0x0184 0x0334 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_UART1_TXD__LPSPI2_PCS0                                          0x0184 0x0334 0x0434 0x02 0x02</div><div class='add'>+#define MX91_PAD_UART1_TXD__TPM1_CH1                                             0x0184 0x0334 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_UART1_TXD__GPIO1_IO5                                            0x0184 0x0334 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_UART2_RXD__LPUART2_RX                                           0x0188 0x0338 0x0464 0x00 0x01</div><div class='add'>+#define MX91_PAD_UART2_RXD__LPUART1_CTS_B                                        0x0188 0x0338 0x0454 0x01 0x01</div><div class='add'>+#define MX91_PAD_UART2_RXD__LPSPI2_SOUT                                          0x0188 0x0338 0x0444 0x02 0x02</div><div class='add'>+#define MX91_PAD_UART2_RXD__TPM1_CH2                                             0x0188 0x0338 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_UART2_RXD__SAI1_MCLK                                            0x0188 0x0338 0x04d4 0x04 0x00</div><div class='add'>+#define MX91_PAD_UART2_RXD__GPIO1_IO6                                            0x0188 0x0338 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_UART2_TXD__LPUART2_TX                                           0x018c 0x033c 0x0468 0x00 0x01</div><div class='add'>+#define MX91_PAD_UART2_TXD__LPUART1_RTS_B                                        0x018c 0x033c 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_UART2_TXD__LPSPI2_SCK                                           0x018c 0x033c 0x043c 0x02 0x02</div><div class='add'>+#define MX91_PAD_UART2_TXD__TPM1_CH3                                             0x018c 0x033c 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_UART2_TXD__GPIO1_IO7                                            0x018c 0x033c 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_UART2_TXD__SAI3_TX_SYNC                                         0x018c 0x033c 0x04e0 0x07 0x02</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_PDM_CLK__PDM_CLK                                                0x0190 0x0340 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_PDM_CLK__MQS1_LEFT                                              0x0190 0x0340 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_PDM_CLK__LPTMR1_ALT1                                            0x0190 0x0340 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_PDM_CLK__GPIO1_IO8                                              0x0190 0x0340 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_PDM_CLK__CAN1_TX                                                0x0190 0x0340 0x0000 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM0                                0x0194 0x0344 0x04c4 0x00 0x02</div><div class='add'>+#define MX91_PAD_PDM_BIT_STREAM0__MQS1_RIGHT                                     0x0194 0x0344 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1                                    0x0194 0x0344 0x0424 0x02 0x01</div><div class='add'>+#define MX91_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK                                    0x0194 0x0344 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_PDM_BIT_STREAM0__LPTMR1_ALT2                                    0x0194 0x0344 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_PDM_BIT_STREAM0__GPIO1_IO9                                      0x0194 0x0344 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_PDM_BIT_STREAM0__CAN1_RX                                        0x0194 0x0344 0x0360 0x06 0x01</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM1                                0x0198 0x0348 0x04c8 0x00 0x02</div><div class='add'>+#define MX91_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1                                    0x0198 0x0348 0x0438 0x02 0x01</div><div class='add'>+#define MX91_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK                                    0x0198 0x0348 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_PDM_BIT_STREAM1__LPTMR1_ALT3                                    0x0198 0x0348 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10                                     0x0198 0x0348 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_EXT_CLK1                          0x0198 0x0348 0x0368 0x06 0x01</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC                                         0x019c 0x034c 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_SAI1_TXFS__SAI1_TX_DATA1                                        0x019c 0x034c 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_SAI1_TXFS__LPSPI1_PCS0                                          0x019c 0x034c 0x0420 0x02 0x01</div><div class='add'>+#define MX91_PAD_SAI1_TXFS__LPUART2_DTR_B                                        0x019c 0x034c 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_SAI1_TXFS__MQS1_LEFT                                            0x019c 0x034c 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_SAI1_TXFS__GPIO1_IO11                                           0x019c 0x034c 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_SAI1_TXC__SAI1_TX_BCLK                                          0x01a0 0x0350 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_SAI1_TXC__LPUART2_CTS_B                                         0x01a0 0x0350 0x0460 0x01 0x01</div><div class='add'>+#define MX91_PAD_SAI1_TXC__LPSPI1_SIN                                            0x01a0 0x0350 0x042c 0x02 0x01</div><div class='add'>+#define MX91_PAD_SAI1_TXC__LPUART1_DSR_B                                         0x01a0 0x0350 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_SAI1_TXC__CAN1_RX                                               0x01a0 0x0350 0x0360 0x04 0x02</div><div class='add'>+#define MX91_PAD_SAI1_TXC__GPIO1_IO12                                            0x01a0 0x0350 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0                                        0x01a4 0x0354 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_SAI1_TXD0__LPUART2_RTS_B                                        0x01a4 0x0354 0x0000 0x01 0x00</div><div class='add'>+#define MX91_PAD_SAI1_TXD0__LPSPI1_SCK                                           0x01a4 0x0354 0x0428 0x02 0x01</div><div class='add'>+#define MX91_PAD_SAI1_TXD0__LPUART1_DTR_B                                        0x01a4 0x0354 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_SAI1_TXD0__CAN1_TX                                              0x01a4 0x0354 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_SAI1_TXD0__GPIO1_IO13                                           0x01a4 0x0354 0x0000 0x05 0x00</div><div class='add'>+#define MX91_PAD_SAI1_TXD0__SAI1_MCLK                                            0x01a4 0x0354 0x04d4 0x06 0x01</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_SAI1_RXD0__SAI1_RX_DATA0                                        0x01a8 0x0358 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_SAI1_RXD0__SAI1_MCLK                                            0x01a8 0x0358 0x04d4 0x01 0x02</div><div class='add'>+#define MX91_PAD_SAI1_RXD0__LPSPI1_SOUT                                          0x01a8 0x0358 0x0430 0x02 0x01</div><div class='add'>+#define MX91_PAD_SAI1_RXD0__LPUART2_DSR_B                                        0x01a8 0x0358 0x0000 0x03 0x00</div><div class='add'>+#define MX91_PAD_SAI1_RXD0__MQS1_RIGHT                                           0x01a8 0x0358 0x0000 0x04 0x00</div><div class='add'>+#define MX91_PAD_SAI1_RXD0__GPIO1_IO14                                           0x01a8 0x0358 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define MX91_PAD_WDOG_ANY__WDOG1_WDOG_ANY                                        0x01ac 0x035c 0x0000 0x00 0x00</div><div class='add'>+#define MX91_PAD_WDOG_ANY__GPIO1_IO15                                            0x01ac 0x035c 0x0000 0x05 0x00</div><div class='add'>+#endif /* __DTS_IMX91_PINFUNC_H */</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx91-tqma9131-mba91xxca.dts b/arch/arm64/boot/dts/freescale/imx91-tqma9131-mba91xxca.dts<br/>new file mode 100644<br/>index 000000000000..5c430e6fca65<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx91-tqma9131-mba91xxca.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx91-tqma9131-mba91xxca.dts</a></div><div class='hunk'>@@ -0,0 +1,739 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2022-2025 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Markus Niebel</div><div class='add'>+ * Author: Alexander Stein</div><div class='add'>+ */</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/net/ti-dp83867.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pwm/pwm.h&gt;</div><div class='add'>+#include &lt;dt-bindings/usb/pd.h&gt;</div><div class='add'>+#include "imx91-tqma9131.dtsi"</div><div class='add'>+</div><div class='add'>+/{</div><div class='add'>+	model = "TQ-Systems i.MX91 TQMa91xxLA/TQMa91xxCA on MBa91xxCA starter kit";</div><div class='add'>+	compatible = "tq,imx91-tqma9131-mba91xxca", "tq,imx91-tqma9131", "fsl,imx91";</div><div class='add'>+	chassis-type = "embedded";</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;lpuart1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		eeprom0 = &amp;eeprom0;</div><div class='add'>+		ethernet0 = &amp;eqos;</div><div class='add'>+		ethernet1 = &amp;fec;</div><div class='add'>+		gpio0 = &amp;gpio1;</div><div class='add'>+		gpio1 = &amp;gpio2;</div><div class='add'>+		gpio2 = &amp;gpio3;</div><div class='add'>+		gpio3 = &amp;gpio4;</div><div class='add'>+		i2c0 = &amp;lpi2c1;</div><div class='add'>+		i2c1 = &amp;lpi2c2;</div><div class='add'>+		i2c2 = &amp;lpi2c3;</div><div class='add'>+		mmc0 = &amp;usdhc1;</div><div class='add'>+		mmc1 = &amp;usdhc2;</div><div class='add'>+		serial0 = &amp;lpuart1;</div><div class='add'>+		serial1 = &amp;lpuart2;</div><div class='add'>+		rtc0 = &amp;pcf85063;</div><div class='add'>+		rtc1 = &amp;bbnsm_rtc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	backlight: backlight {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		pwms = &lt;&amp;tpm2 2 5000000 0&gt;;</div><div class='add'>+		brightness-levels = &lt;0 4 8 16 32 64 128 255&gt;;</div><div class='add'>+		default-brightness-level = &lt;7&gt;;</div><div class='add'>+		power-supply = &lt;&amp;reg_12v0&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;expander2 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	display: display {</div><div class='add'>+		/*</div><div class='add'>+		 * Display is not fixed, so compatible has to be added from</div><div class='add'>+		 * DT overlay</div><div class='add'>+		 */</div><div class='add'>+		power-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;expander2 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		backlight = &lt;&amp;backlight&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			panel_in: endpoint {</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fan0: gpio-fan {</div><div class='add'>+		compatible = "gpio-fan";</div><div class='add'>+		gpios = &lt;&amp;expander2 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		gpio-fan,speed-map = &lt;0 0&gt;, &lt;10000 1&gt;;</div><div class='add'>+		fan-supply = &lt;&amp;reg_12v0&gt;;</div><div class='add'>+		#cooling-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		autorepeat;</div><div class='add'>+</div><div class='add'>+		switch-a {</div><div class='add'>+			label = "switcha";</div><div class='add'>+			linux,code = &lt;BTN_0&gt;;</div><div class='add'>+			gpios = &lt;&amp;expander0 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		switch-b {</div><div class='add'>+			label = "switchb";</div><div class='add'>+			linux,code = &lt;BTN_1&gt;;</div><div class='add'>+			gpios = &lt;&amp;expander0 7 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			gpios = &lt;&amp;expander2 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "default-on";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-2 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_AMBER&gt;;</div><div class='add'>+			function = LED_FUNCTION_HEARTBEAT;</div><div class='add'>+			gpios = &lt;&amp;expander2 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	iio-hwmon {</div><div class='add'>+		compatible = "iio-hwmon";</div><div class='add'>+		io-channels = &lt;&amp;adc1 0&gt;, &lt;&amp;adc1 1&gt;, &lt;&amp;adc1 2&gt;, &lt;&amp;adc1 3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lvds_encoder: lvds-encoder {</div><div class='add'>+		compatible = "ti,sn75lvds83", "lvds-encoder";</div><div class='add'>+		powerdown-gpios = &lt;&amp;expander2 3 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		power-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				lvds_encoder_input: endpoint {</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				lvds_encoder_output: endpoint {</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3v3: regulator-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "V_3V3_MB";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_5v0: regulator-5v0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "V_5V0_MB";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_12v0: regulator-12v0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "V_12V";</div><div class='add'>+		regulator-min-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;12000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;expander1 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_mpcie_1v5: regulator-mpcie-1v5 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "V_1V5_MPCIE";</div><div class='add'>+		regulator-min-microvolt = &lt;1500000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1500000&gt;;</div><div class='add'>+		gpio = &lt;&amp;expander0 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_mpcie_3v3: regulator-mpcie-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "V_3V3_MPCIE";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;expander0 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;adc1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eqos {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_eqos&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy_eqos&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy_eqos: ethernet-phy@0 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_eqos_phy&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;expander1 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;500000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;50000&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+			interrupts = &lt;26 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			enet-phy-lane-no-swap;</div><div class='add'>+			ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_2_25_NS&gt;;</div><div class='add'>+			ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_2_25_NS&gt;;</div><div class='add'>+			ti,fifo-depth = &lt;DP83867_PHYCR_FIFO_DEPTH_4_B_NIB&gt;;</div><div class='add'>+			ti,dp83867-rxctrl-strap-quirk;</div><div class='add'>+			ti,clk-output-sel = &lt;DP83867_CLK_O_SEL_OFF&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy_fec&gt;;</div><div class='add'>+	fsl,magic-packet;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;5000000&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy_fec: ethernet-phy@0 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_fec_phy&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;expander1 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;500000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;50000&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+			interrupts = &lt;27 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			enet-phy-lane-no-swap;</div><div class='add'>+			ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_2_25_NS&gt;;</div><div class='add'>+			ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_2_25_NS&gt;;</div><div class='add'>+			ti,fifo-depth = &lt;DP83867_PHYCR_FIFO_DEPTH_4_B_NIB&gt;;</div><div class='add'>+			ti,dp83867-rxctrl-strap-quirk;</div><div class='add'>+			ti,clk-output-sel = &lt;DP83867_CLK_O_SEL_OFF&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan1&gt;;</div><div class='add'>+	xceiver-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		/* 00 */ "", "", "", "PMIC_IRQ#",</div><div class='add'>+		/* 04 */ "", "", "", "",</div><div class='add'>+		/* 08 */ "", "", "USB_C_ALERT#", "BM2_LCD_INT#",</div><div class='add'>+		/* 12 */ "PEX_INT#", "", "RTC_EVENT#", "",</div><div class='add'>+		/* 16 */ "", "", "", "",</div><div class='add'>+		/* 20 */ "", "", "", "",</div><div class='add'>+		/* 24 */ "", "", "", "",</div><div class='add'>+		/* 28 */ "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio2 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		/* 00 */ "", "", "", "",</div><div class='add'>+		/* 04 */ "", "", "", "",</div><div class='add'>+		/* 08 */ "", "", "", "",</div><div class='add'>+		/* 12 */ "", "", "", "",</div><div class='add'>+		/* 16 */ "", "", "", "",</div><div class='add'>+		/* 20 */ "", "", "", "",</div><div class='add'>+		/* 24 */ "", "", "", "",</div><div class='add'>+		/* 28 */ "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_jtag&gt;;</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		/* 00 */ "SD2_CD#", "", "", "",</div><div class='add'>+		/* 04 */ "", "", "", "SD2_RST#",</div><div class='add'>+		/* 08 */ "", "", "", "",</div><div class='add'>+		/* 12 */ "", "", "", "",</div><div class='add'>+		/* 16 */ "", "", "", "",</div><div class='add'>+		/* 20 */ "", "", "", "",</div><div class='add'>+		/* 24 */ "", "", "ENET1_INT#", "ENET2_INT#",</div><div class='add'>+		/* 28 */ "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		/* 00 */ "", "", "", "",</div><div class='add'>+		/* 04 */ "", "", "", "",</div><div class='add'>+		/* 08 */ "", "", "", "",</div><div class='add'>+		/* 12 */ "", "", "", "",</div><div class='add'>+		/* 16 */ "", "", "", "",</div><div class='add'>+		/* 20 */ "", "", "", "",</div><div class='add'>+		/* 24 */ "", "", "", "",</div><div class='add'>+		/* 28 */ "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c3 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_lpi2c3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	temperature-sensor@1c {</div><div class='add'>+		compatible = "nxp,se97b", "jedec,jc-42.4-temp";</div><div class='add'>+		reg = &lt;0x1c&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ptn5110: usb-typec@50 {</div><div class='add'>+		compatible = "nxp,ptn5110", "tcpci";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_typec&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;10 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+</div><div class='add'>+		connector {</div><div class='add'>+			compatible = "usb-c-connector";</div><div class='add'>+			label = "X17";</div><div class='add'>+			power-role = "dual";</div><div class='add'>+			data-role = "dual";</div><div class='add'>+			try-power-role = "sink";</div><div class='add'>+			typec-power-opmode = "default";</div><div class='add'>+			pd-disable;</div><div class='add'>+			self-powered;</div><div class='add'>+</div><div class='add'>+			port {</div><div class='add'>+				typec_con_hs: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;typec_hs&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom2: eeprom@54 {</div><div class='add'>+		compatible = "nxp,se97b", "atmel,24c02";</div><div class='add'>+		reg = &lt;0x54&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	expander0: gpio@70 {</div><div class='add'>+		compatible = "nxp,pca9538";</div><div class='add'>+		reg = &lt;0x70&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pexp_irq&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;12 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+		gpio-line-names = "TEMP_EVENT_MOD#", "MPCIE_WAKE#",</div><div class='add'>+				  "MPCIE_1V5_EN", "MPCIE_3V3_EN",</div><div class='add'>+				  "MPCIE_PERST#", "MPCIE_WDISABLE#",</div><div class='add'>+				  "BUTTON_A#", "BUTTON_B#";</div><div class='add'>+</div><div class='add'>+		temp-event-mod-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			input;</div><div class='add'>+			line-name = "TEMP_EVENT_MOD#";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mpcie-wake-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			input;</div><div class='add'>+			line-name = "MPCIE_WAKE#";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Controls the mPCIE slot reset which is low active as</div><div class='add'>+		 * reset signal. The output-low states, the signal is</div><div class='add'>+		 * inactive, e.g. not in reset</div><div class='add'>+		 */</div><div class='add'>+		mpcie_rst_hog: mpcie-rst-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+			line-name = "MPCIE_PERST#";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Controls the mPCIE slot WDISABLE pin which is low active</div><div class='add'>+		 * as disable signal. The output-low states, the signal is</div><div class='add'>+		 * inactive, e.g. not disabled</div><div class='add'>+		 */</div><div class='add'>+		mpcie_wdisable_hog: mpcie-wdisable-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+			line-name = "MPCIE_WDISABLE#";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	expander1: gpio@71 {</div><div class='add'>+		compatible = "nxp,pca9538";</div><div class='add'>+		reg = &lt;0x71&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+		gpio-line-names = "ENET1_RESET#", "ENET2_RESET#",</div><div class='add'>+				  "USB_RESET#", "",</div><div class='add'>+				  "WLAN_PD#", "WLAN_W_DISABLE#",</div><div class='add'>+				  "WLAN_PERST#", "12V_EN";</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Controls the WiFi card PD pin which is low active</div><div class='add'>+		 * as power down signal. The output-low states, the signal</div><div class='add'>+		 * is inactive, e.g. not power down</div><div class='add'>+		 */</div><div class='add'>+		wlan-pd-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+			line-name = "WLAN_PD#";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Controls the WiFi card disable pin which is low active</div><div class='add'>+		 * as disable signal. The output-low states, the signal</div><div class='add'>+		 * is inactive, e.g. not disabled</div><div class='add'>+		 */</div><div class='add'>+		wlan-wdisable-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+			line-name = "WLAN_W_DISABLE#";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Controls the WiFi card reset pin which is low active</div><div class='add'>+		 * as reset signal. The output-low states, the signal</div><div class='add'>+		 * is inactive, e.g. not in reset</div><div class='add'>+		 */</div><div class='add'>+		wlan-perst-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+			line-name = "WLAN_PERST#";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	expander2: gpio@72 {</div><div class='add'>+		compatible = "nxp,pca9538";</div><div class='add'>+		reg = &lt;0x72&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+		gpio-line-names = "LCD_RESET#", "LCD_PWR_EN",</div><div class='add'>+				  "LCD_BLT_EN", "LVDS_SHDN#",</div><div class='add'>+				  "FAN_PWR_EN", "",</div><div class='add'>+				  "USER_LED1", "USER_LED2";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	linux,rs485-enabled-at-boot-time;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcf85063 {</div><div class='add'>+	/* RTC_EVENT# from SoM is connected on mainboard */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcf85063&gt;;</div><div class='add'>+	interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+	interrupts = &lt;14 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;se97_som {</div><div class='add'>+	/* TEMP_EVENT# from SoM is connected on mainboard */</div><div class='add'>+	interrupt-parent = &lt;&amp;expander0&gt;;</div><div class='add'>+	interrupts = &lt;0 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tpm2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_tpm2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	hnp-disable;</div><div class='add'>+	srp-disable;</div><div class='add'>+	adp-disable;</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	disable-over-current;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	port {</div><div class='add'>+		typec_hs: endpoint {</div><div class='add'>+			remote-endpoint = &lt;&amp;typec_con_hs&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg2 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	disable-over-current;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	hub_2_0: hub@1 {</div><div class='add'>+		compatible = "usb424,2517";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;expander1 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2_hs&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_uhs&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_uhs&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio3 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	no-sdio;</div><div class='add'>+	no-mmc;</div><div class='add'>+	disable-wp;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_eqos: eqosgrp {</div><div class='add'>+		fsl,pins = /* PD | FSEL_2 | DSE X4 */</div><div class='add'>+			   &lt;MX91_PAD_ENET1_MDC__ENET1_MDC				0x51e&gt;,</div><div class='add'>+			   /* SION | HYS | FSEL_2 | DSE X4 */</div><div class='add'>+			   &lt;MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO				0x4000111e&gt;,</div><div class='add'>+			   /* HYS | FSEL_0 | DSE no drive */</div><div class='add'>+			   &lt;MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0			0x1000&gt;,</div><div class='add'>+			   &lt;MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1			0x1000&gt;,</div><div class='add'>+			   &lt;MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2			0x1000&gt;,</div><div class='add'>+			   &lt;MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3			0x1000&gt;,</div><div class='add'>+			   &lt;MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x1000&gt;,</div><div class='add'>+			   /* HYS | PD | FSEL_0 | DSE no drive */</div><div class='add'>+			   &lt;MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC			0x1400&gt;,</div><div class='add'>+			   /* PD | FSEL_2 | DSE X4 */</div><div class='add'>+			   &lt;MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0			0x51e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1				0x51e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2			0x51e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3			0x51e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x51e&gt;,</div><div class='add'>+			   /* PD | FSEL_3 | DSE X3 */</div><div class='add'>+			   &lt;MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x58e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_eqos_phy: eqosphygrp {</div><div class='add'>+		fsl,pins = /* HYS | FSEL_0 | DSE no drive */</div><div class='add'>+			   &lt;MX91_PAD_CCM_CLKO1__GPIO3_IO26		0x1000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec: fecgrp {</div><div class='add'>+		fsl,pins = /* PD | FSEL_2 | DSE X4 */</div><div class='add'>+			   &lt;MX91_PAD_ENET2_MDC__ENET2_MDC		0x51e&gt;,</div><div class='add'>+			   /* SION | HYS | FSEL_2 | DSE X4 */</div><div class='add'>+			   &lt;MX91_PAD_ENET2_MDIO__ENET2_MDIO		0x4000111e&gt;,</div><div class='add'>+			   /* HYS | FSEL_0 | DSE no drive */</div><div class='add'>+			   &lt;MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0		0x1000&gt;,</div><div class='add'>+			   &lt;MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1		0x1000&gt;,</div><div class='add'>+			   &lt;MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2		0x1000&gt;,</div><div class='add'>+			   &lt;MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3		0x1000&gt;,</div><div class='add'>+			   &lt;MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL	0x1000&gt;,</div><div class='add'>+			   /* HYS | PD | FSEL_0 | DSE no drive */</div><div class='add'>+			   &lt;MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC		0x1400&gt;,</div><div class='add'>+			   /* PD | FSEL_2 | DSE X4 */</div><div class='add'>+			   &lt;MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0		0x51e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1		0x51e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2		0x51e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3		0x51e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL	0x51e&gt;,</div><div class='add'>+			   /* PD | FSEL_3 | DSE X3 */</div><div class='add'>+			   &lt;MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC		0x58e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec_phy: fecphygrp {</div><div class='add'>+		fsl,pins = /* HYS | FSEL_0 | DSE no drive */</div><div class='add'>+			   &lt;MX91_PAD_CCM_CLKO2__GPIO3_IO27		0x1000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan1: flexcan1grp {</div><div class='add'>+		fsl,pins = /* HYS | PU | FSEL_0 | DSE no drive */</div><div class='add'>+			   &lt;MX91_PAD_PDM_BIT_STREAM0__CAN1_RX		0x1200&gt;,</div><div class='add'>+			   /* PU | FSEL_3 | DSE X4 */</div><div class='add'>+			   &lt;MX91_PAD_PDM_CLK__CAN1_TX			0x039e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_jtag: jtaggrp {</div><div class='add'>+		fsl,pins = &lt;MX91_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK	0x051e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_DAP_TDI__JTAG_MUX_TDI		0x1200&gt;,</div><div class='add'>+			   &lt;MX91_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO	0x031e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS	0x1200&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c3: lpi2c3grp {</div><div class='add'>+		fsl,pins = /* SION | HYS | OD | FSEL_3 | DSE X4 */</div><div class='add'>+			   &lt;MX91_PAD_GPIO_IO28__LPI2C3_SDA		0x4000199e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_GPIO_IO29__LPI2C3_SCL		0x4000199e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcf85063: pcf85063grp {</div><div class='add'>+		fsl,pins = &lt;MX91_PAD_SAI1_RXD0__GPIO1_IO14		0x1000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pexp_irq: pexpirqgrp {</div><div class='add'>+		fsl,pins = /* HYS | FSEL_0 | No DSE */</div><div class='add'>+			   &lt;MX91_PAD_SAI1_TXC__GPIO1_IO12		0x1000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_rgbdisp: rgbdispgrp {</div><div class='add'>+		fsl,pins = &lt;MX91_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK	0x31e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_GPIO_IO01__MEDIAMIX_DISP_DE	0x31e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC	0x31e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC	0x31e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA0	0x31e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA1	0x31e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA2	0x31e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA3	0x31e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA4	0x31e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA5	0x31e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA6	0x31e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA7	0x31e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA8	0x31e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA9	0x31e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10	0x31e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11	0x31e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12	0x31e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13	0x31e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14	0x31e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15	0x31e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16	0x31e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17	0x31e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18	0x31e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19	0x31e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20	0x31e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21	0x31e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22	0x31e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23	0x31e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_touch: touchgrp {</div><div class='add'>+		fsl,pins = /* HYS | FSEL_0 | No DSE */</div><div class='add'>+			   &lt;MX91_PAD_SAI1_TXFS__GPIO1_IO11		0x1000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_tpm2: tpm2grp {</div><div class='add'>+		fsl,pins = &lt;MX91_PAD_I2C2_SCL__TPM2_CH2			0x57e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_typec: typecgrp {</div><div class='add'>+		fsl,pins = /* HYS | FSEL_0 | No DSE */</div><div class='add'>+			   &lt;MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10	0x1000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = /* HYS | FSEL_0 | No DSE */</div><div class='add'>+			   &lt;MX91_PAD_UART1_RXD__LPUART1_RX		0x1000&gt;,</div><div class='add'>+			   /* FSEL_2 | DSE X4 */</div><div class='add'>+			   &lt;MX91_PAD_UART1_TXD__LPUART1_TX		0x011e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = /* HYS | FSEL_0 | No DSE */</div><div class='add'>+			   &lt;MX91_PAD_UART2_RXD__LPUART2_RX		0x1000&gt;,</div><div class='add'>+			   /* FSEL_2 | DSE X4 */</div><div class='add'>+			   &lt;MX91_PAD_UART2_TXD__LPUART2_TX		0x011e&gt;,</div><div class='add'>+			   /* FSEL_2 | DSE X4 */</div><div class='add'>+			   &lt;MX91_PAD_SAI1_TXD0__LPUART2_RTS_B		0x011e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='add'>+		fsl,pins = /* HYS | FSEL_0 | No DSE */</div><div class='add'>+			   &lt;MX91_PAD_SD2_CD_B__GPIO3_IO0		0x1000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* enable SION for data and cmd pad due to ERR052021 */</div><div class='add'>+	pinctrl_usdhc2_hs: usdhc2hsgrp {</div><div class='add'>+		fsl,pins = /* PD | FSEL_3 | DSE X5 */</div><div class='add'>+			   &lt;MX91_PAD_SD2_CLK__USDHC2_CLK		0x05be&gt;,</div><div class='add'>+			   /* HYS | PU | FSEL_3 | DSE X4 */</div><div class='add'>+			   &lt;MX91_PAD_SD2_CMD__USDHC2_CMD		0x4000139e&gt;,</div><div class='add'>+			   /* HYS | PU | FSEL_3 | DSE X3 */</div><div class='add'>+			   &lt;MX91_PAD_SD2_DATA0__USDHC2_DATA0		0x4000138e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_SD2_DATA1__USDHC2_DATA1		0x4000138e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_SD2_DATA2__USDHC2_DATA2		0x4000138e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_SD2_DATA3__USDHC2_DATA3		0x4000138e&gt;,</div><div class='add'>+			   /* FSEL_2 | DSE X3 */</div><div class='add'>+			   &lt;MX91_PAD_SD2_VSELECT__USDHC2_VSELECT	0x010e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* enable SION for data and cmd pad due to ERR052021 */</div><div class='add'>+	pinctrl_usdhc2_uhs: usdhc2uhsgrp {</div><div class='add'>+		fsl,pins = /* PD | FSEL_3 | DSE X6 */</div><div class='add'>+			   &lt;MX91_PAD_SD2_CLK__USDHC2_CLK		0x05fe&gt;,</div><div class='add'>+			   /* HYS | PU | FSEL_3 | DSE X4 */</div><div class='add'>+			   &lt;MX91_PAD_SD2_CMD__USDHC2_CMD		0x4000139e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_SD2_DATA0__USDHC2_DATA0		0x4000139e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_SD2_DATA1__USDHC2_DATA1		0x4000139e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_SD2_DATA2__USDHC2_DATA2		0x4000139e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_SD2_DATA3__USDHC2_DATA3		0x4000139e&gt;,</div><div class='add'>+			   /* FSEL_2 | DSE X3 */</div><div class='add'>+			   &lt;MX91_PAD_SD2_VSELECT__USDHC2_VSELECT	0x010e&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx91-tqma9131.dtsi b/arch/arm64/boot/dts/freescale/imx91-tqma9131.dtsi<br/>new file mode 100644<br/>index 000000000000..5792952b7a8e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx91-tqma9131.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx91-tqma9131.dtsi</a></div><div class='hunk'>@@ -0,0 +1,295 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2022-2025 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Markus Niebel</div><div class='add'>+ * Author: Alexander Stein</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "imx91.dtsi"</div><div class='add'>+</div><div class='add'>+/{</div><div class='add'>+	model = "TQ-Systems i.MX91 TQMa91xxCA / TQMa91xxLA SOM";</div><div class='add'>+	compatible = "tq,imx91-tqma9131", "fsl,imx91";</div><div class='add'>+</div><div class='add'>+	memory@80000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		/* our minimum RAM config will be 1024 MiB */</div><div class='add'>+		reg = &lt;0x00000000 0x80000000 0 0x40000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		/* default CMA, must not exceed assembled memory */</div><div class='add'>+		linux,cma {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reusable;</div><div class='add'>+			alloc-ranges = &lt;0 0x80000000 0 0x40000000&gt;;</div><div class='add'>+			size = &lt;0 0x10000000&gt;;</div><div class='add'>+			linux,cma-default;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* EdgeLock secure enclave  */</div><div class='add'>+		ele_reserved: ele-reserved@a4120000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0xa4120000 0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SD2 RST# via PMIC SW_EN */</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usdhc2_vmmc&gt;;</div><div class='add'>+		regulator-name = "VSD_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;buck4&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio3 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;adc1 {</div><div class='add'>+	vref-supply = &lt;&amp;buck5&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexspi1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexspi1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash0: flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		/*</div><div class='add'>+		 * no DQS, RXCLKSRC internal loop back, max 66 MHz</div><div class='add'>+		 * clk framework uses CLK_DIVIDER_ROUND_CLOSEST</div><div class='add'>+		 * selected value together with root from</div><div class='add'>+		 * IMX91_CLK_SYS_PLL_PFD1 @ 800.000.000 Hz helps to</div><div class='add'>+		 * respect the maximum value.</div><div class='add'>+		 */</div><div class='add'>+		spi-max-frequency = &lt;62000000&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;4&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;buck5&gt;;</div><div class='add'>+</div><div class='add'>+		partitions {</div><div class='add'>+			compatible = "fixed-partitions";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c1 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_lpi2c1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	se97_som: temperature-sensor@1b {</div><div class='add'>+		compatible = "nxp,se97b", "jedec,jc-42.4-temp";</div><div class='add'>+		reg = &lt;0x1b&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pca9451a: pmic@25 {</div><div class='add'>+		compatible = "nxp,pca9451a";</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pca9451&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;3 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			/* V_0V8_SOC - hw developer guide: 0.75 .. 0.9 */</div><div class='add'>+			buck1: BUCK1 {</div><div class='add'>+				regulator-name = "BUCK1";</div><div class='add'>+				regulator-min-microvolt = &lt;750000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* V_DDRQ - 1.1 V for LPDDR4 */</div><div class='add'>+			buck2: BUCK2 {</div><div class='add'>+				regulator-name = "BUCK2";</div><div class='add'>+				regulator-min-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* V_3V3 - EEPROM, RTC, ... */</div><div class='add'>+			buck4: BUCK4 {</div><div class='add'>+				regulator-name = "BUCK4";</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* V_1V8 - SPI NOR, eMMC, RAM VDD1... */</div><div class='add'>+			buck5: BUCK5 {</div><div class='add'>+				regulator-name = "BUCK5";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* V_1V1 - RAM VDD2*/</div><div class='add'>+			buck6: BUCK6 {</div><div class='add'>+				regulator-name = "BUCK6";</div><div class='add'>+				regulator-min-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* V_1V8_BBSM, fix 1.8 */</div><div class='add'>+			ldo1: LDO1 {</div><div class='add'>+				regulator-name = "LDO1";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* V_0V8_ANA */</div><div class='add'>+			ldo4: LDO4 {</div><div class='add'>+				regulator-name = "LDO4";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* V_SD2 - 3.3/1.8V USDHC2 io Voltage */</div><div class='add'>+			ldo5: LDO5 {</div><div class='add'>+				regulator-name = "LDO5";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcf85063: rtc@51 {</div><div class='add'>+		compatible = "nxp,pcf85063a";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		quartz-load-femtofarads = &lt;7000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom0: eeprom@53 {</div><div class='add'>+		compatible = "nxp,se97b", "atmel,24c02";</div><div class='add'>+		reg = &lt;0x53&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+		read-only;</div><div class='add'>+		vcc-supply = &lt;&amp;buck4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom1: eeprom@57 {</div><div class='add'>+		compatible = "atmel,24c64";</div><div class='add'>+		reg = &lt;0x57&gt;;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;buck4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* protectable identification memory (part of M24C64-D @57) */</div><div class='add'>+	eeprom@5f {</div><div class='add'>+		compatible = "atmel,24c64d-wl";</div><div class='add'>+		reg = &lt;0x5f&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;buck4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	accelerometer@6a {</div><div class='add'>+		compatible = "st,ism330dhcx";</div><div class='add'>+		reg = &lt;0x6a&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;buck4&gt;;</div><div class='add'>+		vddio-supply = &lt;&amp;buck4&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;buck4&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;buck5&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	no-sdio;</div><div class='add'>+	no-sd;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_flexspi1: flexspi1grp {</div><div class='add'>+		fsl,pins = /* FSEL 3  | DSE X6 */</div><div class='add'>+			   &lt;MX91_PAD_SD3_CMD__FLEXSPI1_A_SS0_B		0x01fe&gt;,</div><div class='add'>+			   &lt;MX91_PAD_SD3_CLK__FLEXSPI1_A_SCLK		0x01fe&gt;,</div><div class='add'>+			   /* HYS | PU | FSEL 3  | DSE X6 */</div><div class='add'>+			   &lt;MX91_PAD_SD3_DATA0__FLEXSPI1_A_DATA0	0x13fe&gt;,</div><div class='add'>+			   &lt;MX91_PAD_SD3_DATA1__FLEXSPI1_A_DATA1	0x13fe&gt;,</div><div class='add'>+			   /* HYS | FSEL 3  | DSE X6 (external PU) */</div><div class='add'>+			   &lt;MX91_PAD_SD3_DATA2__FLEXSPI1_A_DATA2	0x11fe&gt;,</div><div class='add'>+			   &lt;MX91_PAD_SD3_DATA3__FLEXSPI1_A_DATA3	0x11fe&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c1: lpi2c1grp {</div><div class='add'>+		fsl,pins = /* SION | OD | FSEL 3 | DSE X4 */</div><div class='add'>+			   &lt;MX91_PAD_I2C1_SCL__LPI2C1_SCL		0x4000199e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_I2C1_SDA__LPI2C1_SDA		0x4000199e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pca9451: pca9451grp {</div><div class='add'>+		fsl,pins = /* HYS | PU */</div><div class='add'>+			   &lt;MX91_PAD_I2C2_SDA__GPIO1_IO3		0x1200&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {</div><div class='add'>+		fsl,pins = /* FSEL 2 | DSE X2 */</div><div class='add'>+			   &lt;MX91_PAD_SD2_RESET_B__GPIO3_IO7		0x106&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* enable SION for data and cmd pad due to ERR052021 */</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = /* PD | FSEL 3 | DSE X5 */</div><div class='add'>+			   &lt;MX91_PAD_SD1_CLK__USDHC1_CLK		0x5be&gt;,</div><div class='add'>+			   /* HYS | FSEL 0 | no drive */</div><div class='add'>+			   &lt;MX91_PAD_SD1_STROBE__USDHC1_STROBE		0x1000&gt;,</div><div class='add'>+			   /* HYS | FSEL 3 | X5 */</div><div class='add'>+			   &lt;MX91_PAD_SD1_CMD__USDHC1_CMD		0x400011be&gt;,</div><div class='add'>+			   /* HYS | FSEL 3 | X4 */</div><div class='add'>+			   &lt;MX91_PAD_SD1_DATA0__USDHC1_DATA0		0x4000119e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_SD1_DATA1__USDHC1_DATA1		0x4000119e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_SD1_DATA2__USDHC1_DATA2		0x4000119e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_SD1_DATA3__USDHC1_DATA3		0x4000119e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_SD1_DATA4__USDHC1_DATA4		0x4000119e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_SD1_DATA5__USDHC1_DATA5		0x4000119e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_SD1_DATA6__USDHC1_DATA6		0x4000119e&gt;,</div><div class='add'>+			   &lt;MX91_PAD_SD1_DATA7__USDHC1_DATA7		0x4000119e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = /* PU | FSEL 1 | DSE X4 */</div><div class='add'>+			   &lt;MX91_PAD_WDOG_ANY__WDOG1_WDOG_ANY		0x31e&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx91.dtsi b/arch/arm64/boot/dts/freescale/imx91.dtsi<br/>new file mode 100644<br/>index 000000000000..4d8300b2a7bc<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx91.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx91.dtsi</a></div><div class='hunk'>@@ -0,0 +1,71 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2025 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "imx91-pinfunc.h"</div><div class='add'>+#include "imx91_93_common.dtsi"</div><div class='add'>+</div><div class='add'>+&amp;clk {</div><div class='add'>+	compatible = "fsl,imx91-ccm";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ddr_pmu {</div><div class='add'>+	compatible = "fsl,imx91-ddr-pmu", "fsl,imx93-ddr-pmu";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eqos {</div><div class='add'>+	clocks = &lt;&amp;clk IMX91_CLK_ENET1_QOS_TSN_GATE&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX91_CLK_ENET1_QOS_TSN_GATE&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX91_CLK_ENET_TIMER&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX91_CLK_ENET1_QOS_TSN&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX91_CLK_ENET1_QOS_TSN_GATE&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX91_CLK_ENET_TIMER&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX91_CLK_ENET1_QOS_TSN&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX93_CLK_SYS_PLL_PFD1_DIV2&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX93_CLK_SYS_PLL_PFD0_DIV2&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;100000000&gt;, &lt;250000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec {</div><div class='add'>+	clocks = &lt;&amp;clk IMX91_CLK_ENET2_REGULAR_GATE&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX91_CLK_ENET2_REGULAR_GATE&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX91_CLK_ENET_TIMER&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX91_CLK_ENET2_REGULAR&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX93_CLK_DUMMY&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX91_CLK_ENET_TIMER&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX91_CLK_ENET2_REGULAR&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX93_CLK_SYS_PLL_PFD1_DIV2&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX93_CLK_SYS_PLL_PFD0_DIV2&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;100000000&gt;, &lt;250000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i3c1 {</div><div class='add'>+	clocks = &lt;&amp;clk IMX93_CLK_BUS_AON&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX93_CLK_I3C1_GATE&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX93_CLK_DUMMY&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i3c2 {</div><div class='add'>+	clocks = &lt;&amp;clk IMX93_CLK_BUS_WAKEUP&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX93_CLK_I3C2_GATE&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX93_CLK_DUMMY&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	compatible = "fsl,imx91-iomuxc";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;media_blk_ctrl {</div><div class='add'>+	compatible = "fsl,imx91-media-blk-ctrl", "syscon";</div><div class='add'>+	clocks = &lt;&amp;clk IMX93_CLK_MEDIA_APB&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX93_CLK_MEDIA_AXI&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX93_CLK_NIC_MEDIA_GATE&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX93_CLK_MEDIA_DISP_PIX&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX93_CLK_CAM_PIX&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX93_CLK_LCDIF_GATE&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX93_CLK_ISI_GATE&gt;,</div><div class='add'>+		 &lt;&amp;clk IMX93_CLK_MIPI_CSI_GATE&gt;;</div><div class='add'>+	clock-names = "apb", "axi", "nic", "disp", "cam",</div><div class='add'>+		      "lcdif", "isi", "csi";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi b/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi<br/>new file mode 100644<br/>index 000000000000..7958cef35376<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx91_93_common.dtsi</a></div><div class='hunk'>@@ -0,0 +1,1187 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022,2025 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/imx93-clock.h&gt;</div><div class='add'>+#include &lt;dt-bindings/dma/fsl-edma.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/power/fsl,imx93-power.h&gt;</div><div class='add'>+#include &lt;dt-bindings/thermal/thermal.h&gt;</div><div class='add'>+</div><div class='add'>+#include "imx93-pinfunc.h"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	cpus: cpus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		idle-states {</div><div class='add'>+			entry-method = "psci";</div><div class='add'>+</div><div class='add'>+			cpu_pd_wait: cpu-pd-wait {</div><div class='add'>+				compatible = "arm,idle-state";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x0010033&gt;;</div><div class='add'>+				local-timer-stop;</div><div class='add'>+				entry-latency-us = &lt;10000&gt;;</div><div class='add'>+				exit-latency-us = &lt;7000&gt;;</div><div class='add'>+				min-residency-us = &lt;27000&gt;;</div><div class='add'>+				wakeup-latency-us = &lt;15000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		A55_0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_pd_wait&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	osc_32k: clock-osc-32k {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;32768&gt;;</div><div class='add'>+		clock-output-names = "osc_32k";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	osc_24m: clock-osc-24m {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+		clock-output-names = "osc_24m";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_ext1: clock-ext1 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;133000000&gt;;</div><div class='add'>+		clock-output-names = "clk_ext1";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu {</div><div class='add'>+		compatible = "arm,cortex-a55-pmu";</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-1.0";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+		arm,no-tick-in-suspend;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gic: interrupt-controller@48000000 {</div><div class='add'>+		compatible = "arm,gic-v3";</div><div class='add'>+		reg = &lt;0 0x48000000 0 0x10000&gt;,</div><div class='add'>+		      &lt;0 0x48040000 0 0xc0000&gt;;</div><div class='add'>+		#interrupt-cells = &lt;3&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mqs1: mqs1 {</div><div class='add'>+		compatible = "fsl,imx93-mqs";</div><div class='add'>+		gpr = &lt;&amp;aonmix_ns_gpr&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mqs2: mqs2 {</div><div class='add'>+		compatible = "fsl,imx93-mqs";</div><div class='add'>+		gpr = &lt;&amp;wakeupmix_gpr&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usbphynop1: usbphynop1 {</div><div class='add'>+		compatible = "usb-nop-xceiv";</div><div class='add'>+		#phy-cells = &lt;0&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX93_CLK_USB_PHY_BURUNIN&gt;;</div><div class='add'>+		clock-names = "main_clk";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usbphynop2: usbphynop2 {</div><div class='add'>+		compatible = "usb-nop-xceiv";</div><div class='add'>+		#phy-cells = &lt;0&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX93_CLK_USB_PHY_BURUNIN&gt;;</div><div class='add'>+		clock-names = "main_clk";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc@0 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges = &lt;0x0 0x0 0x0 0x80000000&gt;,</div><div class='add'>+			 &lt;0x28000000 0x0 0x28000000 0x10000000&gt;;</div><div class='add'>+</div><div class='add'>+		aips1: bus@44000000 {</div><div class='add'>+			compatible = "fsl,aips-bus", "simple-bus";</div><div class='add'>+			reg = &lt;0x44000000 0x800000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			edma1: dma-controller@44000000 {</div><div class='add'>+				compatible = "fsl,imx93-edma3";</div><div class='add'>+				reg = &lt;0x44000000 0x200000&gt;;</div><div class='add'>+				#dma-cells = &lt;3&gt;;</div><div class='add'>+				dma-channels = &lt;31&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH&gt;,  //  0: Reserved</div><div class='add'>+					     &lt;GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH&gt;,  //  1: CANFD1</div><div class='add'>+					     &lt;GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH&gt;,  //  2: Reserved</div><div class='add'>+					     &lt;GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH&gt;,  //  3: GPIO1 CH0</div><div class='add'>+					     &lt;GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH&gt;,  //  4: GPIO1 CH1</div><div class='add'>+					     &lt;GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH&gt;, //  5: I3C1 TO Bus</div><div class='add'>+					     &lt;GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH&gt;, //  6: I3C1 From Bus</div><div class='add'>+					     &lt;GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH&gt;, //  7: LPI2C1 M TX</div><div class='add'>+					     &lt;GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH&gt;, //  8: LPI2C1 S TX</div><div class='add'>+					     &lt;GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH&gt;, //  9: LPI2C2 M RX</div><div class='add'>+					     &lt;GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH&gt;, // 10: LPI2C2 S RX</div><div class='add'>+					     &lt;GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH&gt;, // 11: LPSPI1 TX</div><div class='add'>+					     &lt;GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH&gt;, // 12: LPSPI1 RX</div><div class='add'>+					     &lt;GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH&gt;, // 13: LPSPI2 TX</div><div class='add'>+					     &lt;GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH&gt;, // 14: LPSPI2 RX</div><div class='add'>+					     &lt;GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH&gt;, // 15: LPTMR1</div><div class='add'>+					     &lt;GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH&gt;, // 16: LPUART1 TX</div><div class='add'>+					     &lt;GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH&gt;, // 17: LPUART1 RX</div><div class='add'>+					     &lt;GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH&gt;, // 18: LPUART2 TX</div><div class='add'>+					     &lt;GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH&gt;, // 19: LPUART2 RX</div><div class='add'>+					     &lt;GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH&gt;, // 20: S400</div><div class='add'>+					     &lt;GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH&gt;, // 21: SAI TX</div><div class='add'>+					     &lt;GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH&gt;, // 22: SAI RX</div><div class='add'>+					     &lt;GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH&gt;, // 23: TPM1 CH0/CH2</div><div class='add'>+					     &lt;GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH&gt;, // 24: TPM1 CH1/CH3</div><div class='add'>+					     &lt;GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH&gt;, // 25: TPM1 Overflow</div><div class='add'>+					     &lt;GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH&gt;, // 26: TMP2 CH0/CH2</div><div class='add'>+					     &lt;GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH&gt;, // 27: TMP2 CH1/CH3</div><div class='add'>+					     &lt;GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH&gt;, // 28: TMP2 Overflow</div><div class='add'>+					     &lt;GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH&gt;, // 29: PDM</div><div class='add'>+					     &lt;GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH&gt;, // 30: ADC1</div><div class='add'>+					     &lt;GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH&gt;;  // err</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_EDMA1_GATE&gt;;</div><div class='add'>+				clock-names = "dma";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			aonmix_ns_gpr: syscon@44210000 {</div><div class='add'>+				compatible = "fsl,imx93-aonmix-ns-syscfg", "syscon";</div><div class='add'>+				reg = &lt;0x44210000 0x1000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			system_counter: timer@44290000 {</div><div class='add'>+				compatible = "nxp,sysctr-timer";</div><div class='add'>+				reg = &lt;0x44290000 0x30000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;osc_24m&gt;;</div><div class='add'>+				clock-names = "per";</div><div class='add'>+				nxp,no-divider;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			wdog1: watchdog@442d0000 {</div><div class='add'>+				compatible = "fsl,imx93-wdt";</div><div class='add'>+				reg = &lt;0x442d0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_WDOG1_GATE&gt;;</div><div class='add'>+				timeout-sec = &lt;40&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			wdog2: watchdog@442e0000 {</div><div class='add'>+				compatible = "fsl,imx93-wdt";</div><div class='add'>+				reg = &lt;0x442e0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_WDOG2_GATE&gt;;</div><div class='add'>+				timeout-sec = &lt;40&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tpm1: pwm@44310000 {</div><div class='add'>+				compatible = "fsl,imx7ulp-pwm";</div><div class='add'>+				reg = &lt;0x44310000 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_TPM1_GATE&gt;;</div><div class='add'>+				#pwm-cells = &lt;3&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tpm2: pwm@44320000 {</div><div class='add'>+				compatible = "fsl,imx7ulp-pwm";</div><div class='add'>+				reg = &lt;0x44320000 0x10000&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_TPM2_GATE&gt;;</div><div class='add'>+				#pwm-cells = &lt;3&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i3c1: i3c@44330000 {</div><div class='add'>+				compatible = "silvaco,i3c-master-v1";</div><div class='add'>+				reg = &lt;0x44330000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;3&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_BUS_AON&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_I3C1_GATE&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_I3C1_SLOW&gt;;</div><div class='add'>+				clock-names = "pclk", "fast_clk", "slow_clk";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpi2c1: i2c@44340000 {</div><div class='add'>+				compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+				reg = &lt;0x44340000 0x10000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_LPI2C1_GATE&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_BUS_AON&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma1 7 0 0&gt;, &lt;&amp;edma1 8 0 FSL_EDMA_RX&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpi2c2: i2c@44350000 {</div><div class='add'>+				compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+				reg = &lt;0x44350000 0x10000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_LPI2C2_GATE&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_BUS_AON&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma1 9 0 0&gt;, &lt;&amp;edma1 10 0 FSL_EDMA_RX&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpspi1: spi@44360000 {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";</div><div class='add'>+				reg = &lt;0x44360000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_LPSPI1_GATE&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_BUS_AON&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma1 11 0 0&gt;, &lt;&amp;edma1 12 0 FSL_EDMA_RX&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpspi2: spi@44370000 {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";</div><div class='add'>+				reg = &lt;0x44370000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_LPSPI2_GATE&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_BUS_AON&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma1 13 0 0&gt;, &lt;&amp;edma1 14 0 FSL_EDMA_RX&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpuart1: serial@44380000 {</div><div class='add'>+				compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";</div><div class='add'>+				reg = &lt;0x44380000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_LPUART1_GATE&gt;;</div><div class='add'>+				clock-names = "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma1 17 0 FSL_EDMA_RX&gt;, &lt;&amp;edma1 16 0 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpuart2: serial@44390000 {</div><div class='add'>+				compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";</div><div class='add'>+				reg = &lt;0x44390000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_LPUART2_GATE&gt;;</div><div class='add'>+				clock-names = "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma1 19 0 FSL_EDMA_RX&gt;, &lt;&amp;edma1 18 0 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			flexcan1: can@443a0000 {</div><div class='add'>+				compatible = "fsl,imx93-flexcan";</div><div class='add'>+				reg = &lt;0x443a0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_BUS_AON&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_CAN1_GATE&gt;;</div><div class='add'>+				clock-names = "ipg", "per";</div><div class='add'>+				assigned-clocks = &lt;&amp;clk IMX93_CLK_CAN1&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;clk IMX93_CLK_SYS_PLL_PFD1_DIV2&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;40000000&gt;;</div><div class='add'>+				fsl,clk-source = /bits/ 8 &lt;0&gt;;</div><div class='add'>+				fsl,stop-mode = &lt;&amp;aonmix_ns_gpr 0x14 0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sai1: sai@443b0000 {</div><div class='add'>+				compatible = "fsl,imx93-sai";</div><div class='add'>+				reg = &lt;0x443b0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_SAI1_IPG&gt;, &lt;&amp;clk IMX93_CLK_DUMMY&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_SAI1_GATE&gt;, &lt;&amp;clk IMX93_CLK_DUMMY&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_DUMMY&gt;;</div><div class='add'>+				clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";</div><div class='add'>+				dmas = &lt;&amp;edma1 22 0 FSL_EDMA_RX&gt;, &lt;&amp;edma1 21 0 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			iomuxc: pinctrl@443c0000 {</div><div class='add'>+				compatible = "fsl,imx93-iomuxc";</div><div class='add'>+				reg = &lt;0x443c0000 0x10000&gt;;</div><div class='add'>+				status = "okay";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			bbnsm: bbnsm@44440000 {</div><div class='add'>+				compatible = "nxp,imx93-bbnsm", "syscon", "simple-mfd";</div><div class='add'>+				reg = &lt;0x44440000 0x10000&gt;;</div><div class='add'>+</div><div class='add'>+				bbnsm_rtc: rtc {</div><div class='add'>+					compatible = "nxp,imx93-bbnsm-rtc";</div><div class='add'>+					interrupts = &lt;GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				bbnsm_pwrkey: pwrkey {</div><div class='add'>+					compatible = "nxp,imx93-bbnsm-pwrkey";</div><div class='add'>+					interrupts = &lt;GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			clk: clock-controller@44450000 {</div><div class='add'>+				compatible = "fsl,imx93-ccm";</div><div class='add'>+				reg = &lt;0x44450000 0x10000&gt;;</div><div class='add'>+				#clock-cells = &lt;1&gt;;</div><div class='add'>+				clocks = &lt;&amp;osc_32k&gt;, &lt;&amp;osc_24m&gt;, &lt;&amp;clk_ext1&gt;;</div><div class='add'>+				clock-names = "osc_32k", "osc_24m", "clk_ext1";</div><div class='add'>+				assigned-clocks = &lt;&amp;clk IMX93_CLK_AUDIO_PLL&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;393216000&gt;;</div><div class='add'>+				status = "okay";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			src: system-controller@44460000 {</div><div class='add'>+				compatible = "fsl,imx93-src", "syscon";</div><div class='add'>+				reg = &lt;0x44460000 0x10000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;1&gt;;</div><div class='add'>+				ranges;</div><div class='add'>+</div><div class='add'>+				mediamix: power-domain@44462400 {</div><div class='add'>+					compatible = "fsl,imx93-src-slice";</div><div class='add'>+					reg = &lt;0x44462400 0x400&gt;, &lt;0x44465800 0x400&gt;;</div><div class='add'>+					#power-domain-cells = &lt;0&gt;;</div><div class='add'>+					clocks = &lt;&amp;clk IMX93_CLK_NIC_MEDIA_GATE&gt;,</div><div class='add'>+						 &lt;&amp;clk IMX93_CLK_MEDIA_APB&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			clock-controller@44480000 {</div><div class='add'>+				compatible = "fsl,imx93-anatop";</div><div class='add'>+				reg = &lt;0x44480000 0x2000&gt;;</div><div class='add'>+				#clock-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			micfil: micfil@44520000 {</div><div class='add'>+				compatible = "fsl,imx93-micfil";</div><div class='add'>+				reg = &lt;0x44520000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_PDM_IPG&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_PDM_GATE&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_AUDIO_PLL&gt;;</div><div class='add'>+				clock-names = "ipg_clk", "ipg_clk_app", "pll8k";</div><div class='add'>+				dmas = &lt;&amp;edma1 29 0 5&gt;;</div><div class='add'>+				dma-names = "rx";</div><div class='add'>+				#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			adc1: adc@44530000 {</div><div class='add'>+				compatible = "nxp,imx93-adc";</div><div class='add'>+				reg = &lt;0x44530000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_ADC1_GATE&gt;;</div><div class='add'>+				clock-names = "ipg";</div><div class='add'>+				#io-channel-cells = &lt;1&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aips2: bus@42000000 {</div><div class='add'>+			compatible = "fsl,aips-bus", "simple-bus";</div><div class='add'>+			reg = &lt;0x42000000 0x800000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			edma2: dma-controller@42000000 {</div><div class='add'>+				compatible = "fsl,imx93-edma4";</div><div class='add'>+				reg = &lt;0x42000000 0x210000&gt;;</div><div class='add'>+				#dma-cells = &lt;3&gt;;</div><div class='add'>+				dma-channels = &lt;64&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_EDMA2_GATE&gt;;</div><div class='add'>+				clock-names = "dma";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			wakeupmix_gpr: syscon@42420000 {</div><div class='add'>+				compatible = "fsl,imx93-wakeupmix-syscfg", "syscon";</div><div class='add'>+				reg = &lt;0x42420000 0x1000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			wdog3: watchdog@42490000 {</div><div class='add'>+				compatible = "fsl,imx93-wdt";</div><div class='add'>+				reg = &lt;0x42490000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_WDOG3_GATE&gt;;</div><div class='add'>+				timeout-sec = &lt;40&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			wdog4: watchdog@424a0000 {</div><div class='add'>+				compatible = "fsl,imx93-wdt";</div><div class='add'>+				reg = &lt;0x424a0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_WDOG4_GATE&gt;;</div><div class='add'>+				timeout-sec = &lt;40&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			wdog5: watchdog@424b0000 {</div><div class='add'>+				compatible = "fsl,imx93-wdt";</div><div class='add'>+				reg = &lt;0x424b0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_WDOG5_GATE&gt;;</div><div class='add'>+				timeout-sec = &lt;40&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tpm3: pwm@424e0000 {</div><div class='add'>+				compatible = "fsl,imx7ulp-pwm";</div><div class='add'>+				reg = &lt;0x424e0000 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_TPM3_GATE&gt;;</div><div class='add'>+				#pwm-cells = &lt;3&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tpm4: pwm@424f0000 {</div><div class='add'>+				compatible = "fsl,imx7ulp-pwm";</div><div class='add'>+				reg = &lt;0x424f0000 0x10000&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_TPM4_GATE&gt;;</div><div class='add'>+				#pwm-cells = &lt;3&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tpm5: pwm@42500000 {</div><div class='add'>+				compatible = "fsl,imx7ulp-pwm";</div><div class='add'>+				reg = &lt;0x42500000 0x10000&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_TPM5_GATE&gt;;</div><div class='add'>+				#pwm-cells = &lt;3&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tpm6: pwm@42510000 {</div><div class='add'>+				compatible = "fsl,imx7ulp-pwm";</div><div class='add'>+				reg = &lt;0x42510000 0x10000&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_TPM6_GATE&gt;;</div><div class='add'>+				#pwm-cells = &lt;3&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i3c2: i3c@42520000 {</div><div class='add'>+				compatible = "silvaco,i3c-master-v1";</div><div class='add'>+				reg = &lt;0x42520000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;3&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_BUS_WAKEUP&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_I3C2_GATE&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_I3C2_SLOW&gt;;</div><div class='add'>+				clock-names = "pclk", "fast_clk", "slow_clk";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpi2c3: i2c@42530000 {</div><div class='add'>+				compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+				reg = &lt;0x42530000 0x10000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_LPI2C3_GATE&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_BUS_WAKEUP&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma2 8 0 0&gt;, &lt;&amp;edma2 9 0 FSL_EDMA_RX&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpi2c4: i2c@42540000 {</div><div class='add'>+				compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+				reg = &lt;0x42540000 0x10000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_LPI2C4_GATE&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_BUS_WAKEUP&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma2 10 0 0&gt;, &lt;&amp;edma2 11 0 FSL_EDMA_RX&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpspi3: spi@42550000 {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";</div><div class='add'>+				reg = &lt;0x42550000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_LPSPI3_GATE&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_BUS_WAKEUP&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma2 12 0 0&gt;, &lt;&amp;edma2 13 0 FSL_EDMA_RX&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpspi4: spi@42560000 {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";</div><div class='add'>+				reg = &lt;0x42560000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_LPSPI4_GATE&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_BUS_WAKEUP&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma2 14 0 0&gt;, &lt;&amp;edma2 15 0 FSL_EDMA_RX&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpuart3: serial@42570000 {</div><div class='add'>+				compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";</div><div class='add'>+				reg = &lt;0x42570000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_LPUART3_GATE&gt;;</div><div class='add'>+				clock-names = "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma2 18 0 FSL_EDMA_RX&gt;, &lt;&amp;edma2 17 0 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpuart4: serial@42580000 {</div><div class='add'>+				compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";</div><div class='add'>+				reg = &lt;0x42580000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_LPUART4_GATE&gt;;</div><div class='add'>+				clock-names = "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma2 20 0 FSL_EDMA_RX&gt;, &lt;&amp;edma2 19 0 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpuart5: serial@42590000 {</div><div class='add'>+				compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";</div><div class='add'>+				reg = &lt;0x42590000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_LPUART5_GATE&gt;;</div><div class='add'>+				clock-names = "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma2 22 0 FSL_EDMA_RX&gt;, &lt;&amp;edma2 21 0 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpuart6: serial@425a0000 {</div><div class='add'>+				compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";</div><div class='add'>+				reg = &lt;0x425a0000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_LPUART6_GATE&gt;;</div><div class='add'>+				clock-names = "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma2 24 0 FSL_EDMA_RX&gt;, &lt;&amp;edma2 23 0 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			flexcan2: can@425b0000 {</div><div class='add'>+				compatible = "fsl,imx93-flexcan";</div><div class='add'>+				reg = &lt;0x425b0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_BUS_WAKEUP&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_CAN2_GATE&gt;;</div><div class='add'>+				clock-names = "ipg", "per";</div><div class='add'>+				assigned-clocks = &lt;&amp;clk IMX93_CLK_CAN2&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;clk IMX93_CLK_SYS_PLL_PFD1_DIV2&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;40000000&gt;;</div><div class='add'>+				fsl,clk-source = /bits/ 8 &lt;0&gt;;</div><div class='add'>+				fsl,stop-mode = &lt;&amp;wakeupmix_gpr 0x0c 2&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			flexspi1: spi@425e0000 {</div><div class='add'>+				compatible = "nxp,imx93-fspi", "nxp,imx8mm-fspi";</div><div class='add'>+				reg = &lt;0x425e0000 0x10000&gt;, &lt;0x28000000 0x10000000&gt;;</div><div class='add'>+				reg-names = "fspi_base", "fspi_mmap";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_FLEXSPI1_GATE&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_FLEXSPI1_GATE&gt;;</div><div class='add'>+				clock-names = "fspi_en", "fspi";</div><div class='add'>+				assigned-clocks = &lt;&amp;clk IMX93_CLK_FLEXSPI1&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;clk IMX93_CLK_SYS_PLL_PFD1&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sai2: sai@42650000 {</div><div class='add'>+				compatible = "fsl,imx93-sai";</div><div class='add'>+				reg = &lt;0x42650000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_SAI2_IPG&gt;, &lt;&amp;clk IMX93_CLK_DUMMY&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_SAI2_GATE&gt;, &lt;&amp;clk IMX93_CLK_DUMMY&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_DUMMY&gt;;</div><div class='add'>+				clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";</div><div class='add'>+				dmas = &lt;&amp;edma2 59 0 FSL_EDMA_RX&gt;, &lt;&amp;edma2 58 0 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sai3: sai@42660000 {</div><div class='add'>+				compatible = "fsl,imx93-sai";</div><div class='add'>+				reg = &lt;0x42660000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_SAI3_IPG&gt;, &lt;&amp;clk IMX93_CLK_DUMMY&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_SAI3_GATE&gt;, &lt;&amp;clk IMX93_CLK_DUMMY&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_DUMMY&gt;;</div><div class='add'>+				clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";</div><div class='add'>+				dmas = &lt;&amp;edma2 61 0 FSL_EDMA_RX&gt;, &lt;&amp;edma2 60 0 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			xcvr: xcvr@42680000 {</div><div class='add'>+				compatible = "fsl,imx93-xcvr";</div><div class='add'>+				reg = &lt;0x42680000 0x800&gt;,</div><div class='add'>+				      &lt;0x42680800 0x400&gt;,</div><div class='add'>+				      &lt;0x42680c00 0x080&gt;,</div><div class='add'>+				      &lt;0x42680e00 0x080&gt;;</div><div class='add'>+				reg-names = "ram", "regs", "rxfifo", "txfifo";</div><div class='add'>+				interrupts = &lt;GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_SPDIF_IPG&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_SPDIF_GATE&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_DUMMY&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_AUD_XCVR_GATE&gt;;</div><div class='add'>+				clock-names = "ipg", "phy", "spba", "pll_ipg";</div><div class='add'>+				dmas = &lt;&amp;edma2 65 0 FSL_EDMA_RX&gt;, &lt;&amp;edma2 66 0 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpuart7: serial@42690000 {</div><div class='add'>+				compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";</div><div class='add'>+				reg = &lt;0x42690000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_LPUART7_GATE&gt;;</div><div class='add'>+				clock-names = "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma2 88 0 FSL_EDMA_RX&gt;, &lt;&amp;edma2 87 0 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpuart8: serial@426a0000 {</div><div class='add'>+				compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";</div><div class='add'>+				reg = &lt;0x426a0000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_LPUART8_GATE&gt;;</div><div class='add'>+				clock-names = "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma2 90 0 FSL_EDMA_RX&gt;, &lt;&amp;edma2 89 0 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpi2c5: i2c@426b0000 {</div><div class='add'>+				compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+				reg = &lt;0x426b0000 0x10000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_LPI2C5_GATE&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_BUS_WAKEUP&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma2 71 0 0&gt;, &lt;&amp;edma2 72 0 FSL_EDMA_RX&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpi2c6: i2c@426c0000 {</div><div class='add'>+				compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+				reg = &lt;0x426c0000 0x10000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_LPI2C6_GATE&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_BUS_WAKEUP&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma2 73 0 0&gt;, &lt;&amp;edma2 74 0 FSL_EDMA_RX&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpi2c7: i2c@426d0000 {</div><div class='add'>+				compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+				reg = &lt;0x426d0000 0x10000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_LPI2C7_GATE&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_BUS_WAKEUP&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma2 75 0 0&gt;, &lt;&amp;edma2 76 0 FSL_EDMA_RX&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpi2c8: i2c@426e0000 {</div><div class='add'>+				compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+				reg = &lt;0x426e0000 0x10000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_LPI2C8_GATE&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_BUS_WAKEUP&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma2 77 0 0&gt;, &lt;&amp;edma2 78 0 FSL_EDMA_RX&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpspi5: spi@426f0000 {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";</div><div class='add'>+				reg = &lt;0x426f0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_LPSPI5_GATE&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_BUS_WAKEUP&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma2 79 0 0&gt;, &lt;&amp;edma2 80 0 FSL_EDMA_RX&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpspi6: spi@42700000 {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";</div><div class='add'>+				reg = &lt;0x42700000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_LPSPI6_GATE&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_BUS_WAKEUP&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma2 81 0 0&gt;, &lt;&amp;edma2 82 0 FSL_EDMA_RX&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpspi7: spi@42710000 {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";</div><div class='add'>+				reg = &lt;0x42710000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_LPSPI7_GATE&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_BUS_WAKEUP&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma2 83 0 0&gt;, &lt;&amp;edma2 84 0 FSL_EDMA_RX&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpspi8: spi@42720000 {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";</div><div class='add'>+				reg = &lt;0x42720000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_LPSPI8_GATE&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_BUS_WAKEUP&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma2 85 0 0&gt;, &lt;&amp;edma2 86 0 FSL_EDMA_RX&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aips3: bus@42800000 {</div><div class='add'>+			compatible = "fsl,aips-bus", "simple-bus";</div><div class='add'>+			reg = &lt;0x42800000 0x800000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			usdhc1: mmc@42850000 {</div><div class='add'>+				compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";</div><div class='add'>+				reg = &lt;0x42850000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_BUS_WAKEUP&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_WAKEUP_AXI&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_USDHC1_GATE&gt;;</div><div class='add'>+				clock-names = "ipg", "ahb", "per";</div><div class='add'>+				assigned-clocks = &lt;&amp;clk IMX93_CLK_USDHC1&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;clk IMX93_CLK_SYS_PLL_PFD1&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+				bus-width = &lt;8&gt;;</div><div class='add'>+				fsl,tuning-start-tap = &lt;1&gt;;</div><div class='add'>+				fsl,tuning-step = &lt;2&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			usdhc2: mmc@42860000 {</div><div class='add'>+				compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";</div><div class='add'>+				reg = &lt;0x42860000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_BUS_WAKEUP&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_WAKEUP_AXI&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_USDHC2_GATE&gt;;</div><div class='add'>+				clock-names = "ipg", "ahb", "per";</div><div class='add'>+				assigned-clocks = &lt;&amp;clk IMX93_CLK_USDHC2&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;clk IMX93_CLK_SYS_PLL_PFD1&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+				bus-width = &lt;4&gt;;</div><div class='add'>+				fsl,tuning-start-tap = &lt;1&gt;;</div><div class='add'>+				fsl,tuning-step = &lt;2&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			fec: ethernet@42890000 {</div><div class='add'>+				compatible = "fsl,imx93-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";</div><div class='add'>+				reg = &lt;0x42890000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_ENET1_GATE&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_ENET1_GATE&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_ENET_TIMER1&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_ENET_REF&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_ENET_REF_PHY&gt;;</div><div class='add'>+				clock-names = "ipg", "ahb", "ptp",</div><div class='add'>+					      "enet_clk_ref", "enet_out";</div><div class='add'>+				assigned-clocks = &lt;&amp;clk IMX93_CLK_ENET_TIMER1&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX93_CLK_ENET_REF&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX93_CLK_ENET_REF_PHY&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;clk IMX93_CLK_SYS_PLL_PFD1_DIV2&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX93_CLK_SYS_PLL_PFD0_DIV2&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX93_CLK_SYS_PLL_PFD1_DIV2&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;100000000&gt;, &lt;250000000&gt;, &lt;50000000&gt;;</div><div class='add'>+				fsl,num-tx-queues = &lt;3&gt;;</div><div class='add'>+				fsl,num-rx-queues = &lt;3&gt;;</div><div class='add'>+				fsl,stop-mode = &lt;&amp;wakeupmix_gpr 0x0c 1&gt;;</div><div class='add'>+				nvmem-cells = &lt;&amp;eth_mac1&gt;;</div><div class='add'>+				nvmem-cell-names = "mac-address";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			eqos: ethernet@428a0000 {</div><div class='add'>+				compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a";</div><div class='add'>+				reg = &lt;0x428a0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				interrupt-names = "macirq", "eth_wake_irq";</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_ENET_QOS_GATE&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_ENET_QOS_GATE&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_ENET_TIMER2&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_ENET&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_ENET_QOS_GATE&gt;;</div><div class='add'>+				clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem";</div><div class='add'>+				assigned-clocks = &lt;&amp;clk IMX93_CLK_ENET_TIMER2&gt;,</div><div class='add'>+						  &lt;&amp;clk IMX93_CLK_ENET&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;clk IMX93_CLK_SYS_PLL_PFD1_DIV2&gt;,</div><div class='add'>+							 &lt;&amp;clk IMX93_CLK_SYS_PLL_PFD0_DIV2&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;100000000&gt;, &lt;250000000&gt;;</div><div class='add'>+				intf_mode = &lt;&amp;wakeupmix_gpr 0x28&gt;;</div><div class='add'>+				snps,clk-csr = &lt;6&gt;;</div><div class='add'>+				nvmem-cells = &lt;&amp;eth_mac2&gt;;</div><div class='add'>+				nvmem-cell-names = "mac-address";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			usdhc3: mmc@428b0000 {</div><div class='add'>+				compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";</div><div class='add'>+				reg = &lt;0x428b0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk IMX93_CLK_BUS_WAKEUP&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_WAKEUP_AXI&gt;,</div><div class='add'>+					 &lt;&amp;clk IMX93_CLK_USDHC3_GATE&gt;;</div><div class='add'>+				clock-names = "ipg", "ahb", "per";</div><div class='add'>+				assigned-clocks = &lt;&amp;clk IMX93_CLK_USDHC3&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;clk IMX93_CLK_SYS_PLL_PFD1&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+				bus-width = &lt;4&gt;;</div><div class='add'>+				fsl,tuning-start-tap = &lt;1&gt;;</div><div class='add'>+				fsl,tuning-step = &lt;2&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpio2: gpio@43810000 {</div><div class='add'>+			compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio";</div><div class='add'>+			reg = &lt;0x43810000 0x1000&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX93_CLK_GPIO2_GATE&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX93_CLK_GPIO2_GATE&gt;;</div><div class='add'>+			clock-names = "gpio", "port";</div><div class='add'>+			gpio-ranges = &lt;&amp;iomuxc 0 4 30&gt;;</div><div class='add'>+			ngpios = &lt;30&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpio3: gpio@43820000 {</div><div class='add'>+			compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio";</div><div class='add'>+			reg = &lt;0x43820000 0x1000&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX93_CLK_GPIO3_GATE&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX93_CLK_GPIO3_GATE&gt;;</div><div class='add'>+			clock-names = "gpio", "port";</div><div class='add'>+			gpio-ranges = &lt;&amp;iomuxc 0 84 8&gt;, &lt;&amp;iomuxc 8 66 18&gt;,</div><div class='add'>+				      &lt;&amp;iomuxc 26 34 2&gt;, &lt;&amp;iomuxc 28 0 4&gt;;</div><div class='add'>+			ngpios = &lt;32&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpio4: gpio@43830000 {</div><div class='add'>+			compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio";</div><div class='add'>+			reg = &lt;0x43830000 0x1000&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX93_CLK_GPIO4_GATE&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX93_CLK_GPIO4_GATE&gt;;</div><div class='add'>+			clock-names = "gpio", "port";</div><div class='add'>+			gpio-ranges = &lt;&amp;iomuxc 0 38 28&gt;, &lt;&amp;iomuxc 28 36 2&gt;;</div><div class='add'>+			ngpios = &lt;30&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpio1: gpio@47400000 {</div><div class='add'>+			compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio";</div><div class='add'>+			reg = &lt;0x47400000 0x1000&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX93_CLK_GPIO1_GATE&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX93_CLK_GPIO1_GATE&gt;;</div><div class='add'>+			clock-names = "gpio", "port";</div><div class='add'>+			gpio-ranges = &lt;&amp;iomuxc 0 92 16&gt;;</div><div class='add'>+			ngpios = &lt;16&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ocotp: efuse@47510000 {</div><div class='add'>+			compatible = "fsl,imx93-ocotp", "syscon";</div><div class='add'>+			reg = &lt;0x47510000 0x10000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			eth_mac1: mac-address@4ec {</div><div class='add'>+				reg = &lt;0x4ec 0x6&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			eth_mac2: mac-address@4f2 {</div><div class='add'>+				reg = &lt;0x4f2 0x6&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		s4muap: mailbox@47520000 {</div><div class='add'>+			compatible = "fsl,imx93-mu-s4";</div><div class='add'>+			reg = &lt;0x47520000 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "tx", "rx";</div><div class='add'>+			#mbox-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		media_blk_ctrl: system-controller@4ac10000 {</div><div class='add'>+			compatible = "fsl,imx93-media-blk-ctrl", "syscon";</div><div class='add'>+			reg = &lt;0x4ac10000 0x10000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;mediamix&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX93_CLK_MEDIA_APB&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX93_CLK_MEDIA_AXI&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX93_CLK_NIC_MEDIA_GATE&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX93_CLK_MEDIA_DISP_PIX&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX93_CLK_CAM_PIX&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX93_CLK_PXP_GATE&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX93_CLK_LCDIF_GATE&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX93_CLK_ISI_GATE&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX93_CLK_MIPI_CSI_GATE&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX93_CLK_MIPI_DSI_GATE&gt;;</div><div class='add'>+			clock-names = "apb", "axi", "nic", "disp", "cam",</div><div class='add'>+				      "pxp", "lcdif", "isi", "csi", "dsi";</div><div class='add'>+			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usbotg1: usb@4c100000 {</div><div class='add'>+			compatible = "fsl,imx93-usb", "fsl,imx7d-usb", "fsl,imx27-usb";</div><div class='add'>+			reg = &lt;0x4c100000 0x200&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX93_CLK_USB_CONTROLLER_GATE&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX93_CLK_HSIO_32K_GATE&gt;;</div><div class='add'>+			clock-names = "usb_ctrl_root", "usb_wakeup";</div><div class='add'>+			assigned-clocks = &lt;&amp;clk IMX93_CLK_HSIO&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;clk IMX93_CLK_SYS_PLL_PFD1_DIV2&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;133000000&gt;;</div><div class='add'>+			phys = &lt;&amp;usbphynop1&gt;;</div><div class='add'>+			fsl,usbmisc = &lt;&amp;usbmisc1 0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usbmisc1: usbmisc@4c100200 {</div><div class='add'>+			compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc",</div><div class='add'>+				     "fsl,imx6q-usbmisc";</div><div class='add'>+			reg = &lt;0x4c100200 0x200&gt;;</div><div class='add'>+			#index-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usbotg2: usb@4c200000 {</div><div class='add'>+			compatible = "fsl,imx93-usb", "fsl,imx7d-usb", "fsl,imx27-usb";</div><div class='add'>+			reg = &lt;0x4c200000 0x200&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX93_CLK_USB_CONTROLLER_GATE&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX93_CLK_HSIO_32K_GATE&gt;;</div><div class='add'>+			clock-names = "usb_ctrl_root", "usb_wakeup";</div><div class='add'>+			assigned-clocks = &lt;&amp;clk IMX93_CLK_HSIO&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;clk IMX93_CLK_SYS_PLL_PFD1_DIV2&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;133000000&gt;;</div><div class='add'>+			phys = &lt;&amp;usbphynop2&gt;;</div><div class='add'>+			fsl,usbmisc = &lt;&amp;usbmisc2 0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usbmisc2: usbmisc@4c200200 {</div><div class='add'>+			compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc",</div><div class='add'>+				     "fsl,imx6q-usbmisc";</div><div class='add'>+			reg = &lt;0x4c200200 0x200&gt;;</div><div class='add'>+			#index-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		memory-controller@4e300000 {</div><div class='add'>+			compatible = "nxp,imx9-memory-controller";</div><div class='add'>+			reg = &lt;0x4e300000 0x800&gt;, &lt;0x4e301000 0x1000&gt;;</div><div class='add'>+			reg-names = "ctrl", "inject";</div><div class='add'>+			interrupts = &lt;GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			little-endian;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ddr_pmu: ddr-pmu@4e300dc0 {</div><div class='add'>+			compatible = "fsl,imx93-ddr-pmu";</div><div class='add'>+			reg = &lt;0x4e300dc0 0x200&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts<br/>new file mode 100644<br/>index 000000000000..b94a24193e19<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts</a></div><div class='hunk'>@@ -0,0 +1,1058 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/usb/pd.h&gt;</div><div class='add'>+#include "imx93.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "NXP i.MX93 11X11 EVK board";</div><div class='add'>+	compatible = "fsl,imx93-11x11-evk", "fsl,imx93";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;fec;</div><div class='add'>+		ethernet1 = &amp;eqos;</div><div class='add'>+		gpio0 = &amp;gpio1;</div><div class='add'>+		gpio1 = &amp;gpio2;</div><div class='add'>+		gpio2 = &amp;gpio3;</div><div class='add'>+		i2c0 = &amp;lpi2c1;</div><div class='add'>+		i2c1 = &amp;lpi2c2;</div><div class='add'>+		i2c2 = &amp;lpi2c3;</div><div class='add'>+		mmc0 = &amp;usdhc1;</div><div class='add'>+		mmc1 = &amp;usdhc2;</div><div class='add'>+		rtc0 = &amp;bbnsm_rtc;</div><div class='add'>+		serial0 = &amp;lpuart1;</div><div class='add'>+		serial1 = &amp;lpuart2;</div><div class='add'>+		serial2 = &amp;lpuart3;</div><div class='add'>+		serial3 = &amp;lpuart4;</div><div class='add'>+		serial4 = &amp;lpuart5;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;lpuart1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		linux,cma {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reusable;</div><div class='add'>+			alloc-ranges = &lt;0 0x80000000 0 0x40000000&gt;;</div><div class='add'>+			size = &lt;0 0x10000000&gt;;</div><div class='add'>+			linux,cma-default;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev0vring0: vdev0vring0@a4000000 {</div><div class='add'>+			reg = &lt;0 0xa4000000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev0vring1: vdev0vring1@a4008000 {</div><div class='add'>+			reg = &lt;0 0xa4008000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev1vring0: vdev1vring0@a4010000 {</div><div class='add'>+			reg = &lt;0 0xa4010000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev1vring1: vdev1vring1@a4018000 {</div><div class='add'>+			reg = &lt;0 0xa4018000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rsc_table: rsc-table@2021e000 {</div><div class='add'>+			reg = &lt;0 0x2021e000 0 0x1000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdevbuffer: vdevbuffer@a4020000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0xa4020000 0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vdd_12v: regulator-vdd-12v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_12V";</div><div class='add'>+		regulator-min-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;12000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;pcal6524 14 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vref_1v8: regulator-adc-vref {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vref_1v8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_audio_pwr: regulator-audio-pwr {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "audio-pwr";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;adp5585 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_can2_standby: regulator-can2-standby {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "can2-stby";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;adp5585 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_m2_pwr: regulator-m2-pwr {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "M.2-power";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;pcal6524 13 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usdhc2_vmmc&gt;;</div><div class='add'>+		regulator-name = "VSD_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio3 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		off-on-delay-us = &lt;12000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc3_vmmc: regulator-usdhc3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "WLAN_EN";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;reg_m2_pwr&gt;;</div><div class='add'>+		gpio = &lt;&amp;pcal6524 20 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		/*</div><div class='add'>+		 * IW612 wifi chip needs more delay than other wifi chips to complete</div><div class='add'>+		 * the host interface initialization after power up, otherwise the</div><div class='add'>+		 * internal state of IW612 may be unstable, resulting in the failure of</div><div class='add'>+		 * the SDIO3.0 switch voltage.</div><div class='add'>+		 */</div><div class='add'>+		startup-delay-us = &lt;20000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usdhc3_pwrseq: usdhc3_pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-simple";</div><div class='add'>+		reset-gpios = &lt;&amp;pcal6524 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	backlight_lvds: backlight-lvds {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		pwms = &lt;&amp;adp5585 0 100000 0&gt;;</div><div class='add'>+		brightness-levels = &lt;0 100&gt;;</div><div class='add'>+		num-interpolated-steps = &lt;100&gt;;</div><div class='add'>+		default-brightness-level = &lt;100&gt;;</div><div class='add'>+		power-supply = &lt;&amp;reg_vdd_12v&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;adp5585 9 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bt_sco_codec: bt-sco-codec {</div><div class='add'>+		compatible = "linux,bt-sco";</div><div class='add'>+		#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-bt-sco {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,name = "bt-sco-audio";</div><div class='add'>+		simple-audio-card,format = "dsp_a";</div><div class='add'>+		simple-audio-card,bitclock-inversion;</div><div class='add'>+		simple-audio-card,frame-master = &lt;&amp;btcpu&gt;;</div><div class='add'>+		simple-audio-card,bitclock-master = &lt;&amp;btcpu&gt;;</div><div class='add'>+</div><div class='add'>+		btcpu: simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;sai1&gt;;</div><div class='add'>+			dai-tdm-slot-num = &lt;2&gt;;</div><div class='add'>+			dai-tdm-slot-width = &lt;16&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		simple-audio-card,codec {</div><div class='add'>+			sound-dai = &lt;&amp;bt_sco_codec 1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-micfil {</div><div class='add'>+		compatible = "fsl,imx-audio-card";</div><div class='add'>+		model = "micfil-audio";</div><div class='add'>+</div><div class='add'>+		pri-dai-link {</div><div class='add'>+			link-name = "micfil hifi";</div><div class='add'>+			format = "i2s";</div><div class='add'>+</div><div class='add'>+			cpu {</div><div class='add'>+				sound-dai = &lt;&amp;micfil&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-wm8962 {</div><div class='add'>+		compatible = "fsl,imx-audio-wm8962";</div><div class='add'>+		model = "wm8962-audio";</div><div class='add'>+		audio-cpu = &lt;&amp;sai3&gt;;</div><div class='add'>+		audio-codec = &lt;&amp;wm8962&gt;;</div><div class='add'>+		hp-det-gpio = &lt;&amp;pcal6524 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		audio-routing =</div><div class='add'>+			"Headphone Jack", "HPOUTL",</div><div class='add'>+			"Headphone Jack", "HPOUTR",</div><div class='add'>+			"Ext Spk", "SPKOUTL",</div><div class='add'>+			"Ext Spk", "SPKOUTR",</div><div class='add'>+			"AMIC", "MICBIAS",</div><div class='add'>+			"IN3R", "AMIC",</div><div class='add'>+			"IN1R", "AMIC";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-xcvr {</div><div class='add'>+		compatible = "fsl,imx-audio-card";</div><div class='add'>+		model = "imx-audio-xcvr";</div><div class='add'>+</div><div class='add'>+		pri-dai-link {</div><div class='add'>+			link-name = "XCVR PCM";</div><div class='add'>+</div><div class='add'>+			cpu {</div><div class='add'>+				sound-dai = &lt;&amp;xcvr&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;adc1 {</div><div class='add'>+	vref-supply = &lt;&amp;reg_vref_1v8&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cm33 {</div><div class='add'>+	mbox-names = "tx", "rx", "rxdb";</div><div class='add'>+	mboxes = &lt;&amp;mu1 0 1&gt;,</div><div class='add'>+		 &lt;&amp;mu1 1 1&gt;,</div><div class='add'>+		 &lt;&amp;mu1 3 1&gt;;</div><div class='add'>+	memory-region = &lt;&amp;vdevbuffer&gt;, &lt;&amp;vdev0vring0&gt;, &lt;&amp;vdev0vring1&gt;,</div><div class='add'>+			&lt;&amp;vdev1vring0&gt;, &lt;&amp;vdev1vring1&gt;, &lt;&amp;rsc_table&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eqos {</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_eqos&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_eqos_sleep&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;5000000&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy1: ethernet-phy@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;pcal6524 15 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;10000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;80000&gt;;</div><div class='add'>+			realtek,clkout-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec {</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_fec_sleep&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy2&gt;;</div><div class='add'>+	fsl,magic-packet;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;5000000&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy2: ethernet-phy@2 {</div><div class='add'>+			reg = &lt;2&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;pcal6524 16 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;10000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;80000&gt;;</div><div class='add'>+			realtek,clkout-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan2&gt;;</div><div class='add'>+	xceiver-supply = &lt;&amp;reg_can2_standby&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c1 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	wm8962: codec@1a {</div><div class='add'>+		compatible = "wlf,wm8962";</div><div class='add'>+		reg = &lt;0x1a&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX93_CLK_SAI3_GATE&gt;;</div><div class='add'>+		DCVDD-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+		DBVDD-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+		AVDD-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+		CPVDD-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+		MICVDD-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+		PLLVDD-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+		SPKVDD1-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+		SPKVDD2-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+		gpio-cfg = &lt;</div><div class='add'>+			0x0000 /* 0:Default */</div><div class='add'>+			0x0000 /* 1:Default */</div><div class='add'>+			0x0000 /* 2:FN_DMICCLK */</div><div class='add'>+			0x0000 /* 3:Default */</div><div class='add'>+			0x0000 /* 4:FN_DMICCDAT */</div><div class='add'>+			0x0000 /* 5:Default */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	inertial-meter@6a {</div><div class='add'>+		compatible = "st,lsm6dso";</div><div class='add'>+		reg = &lt;0x6a&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pcal6524: gpio@22 {</div><div class='add'>+		compatible = "nxp,pcal6524";</div><div class='add'>+		reg = &lt;0x22&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pcal6524&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+		interrupts = &lt;27 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmic@25 {</div><div class='add'>+		compatible = "nxp,pca9451a";</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;pcal6524&gt;;</div><div class='add'>+		interrupts = &lt;11 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			buck1: BUCK1 {</div><div class='add'>+				regulator-name = "BUCK1";</div><div class='add'>+				regulator-min-microvolt = &lt;610000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;950000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck2: BUCK2 {</div><div class='add'>+				regulator-name = "BUCK2";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;670000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck4: BUCK4 {</div><div class='add'>+				regulator-name = "BUCK4";</div><div class='add'>+				regulator-min-microvolt = &lt;1620000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck5: BUCK5 {</div><div class='add'>+				regulator-name = "BUCK5";</div><div class='add'>+				regulator-min-microvolt = &lt;1620000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck6: BUCK6 {</div><div class='add'>+				regulator-name = "BUCK6";</div><div class='add'>+				regulator-min-microvolt = &lt;1060000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1140000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo1: LDO1 {</div><div class='add'>+				regulator-name = "LDO1";</div><div class='add'>+				regulator-min-microvolt = &lt;1620000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1980000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo4: LDO4 {</div><div class='add'>+				regulator-name = "LDO4";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;840000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo5: LDO5 {</div><div class='add'>+				regulator-name = "LDO5";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	adp5585: io-expander@34 {</div><div class='add'>+		compatible = "adi,adp5585-00", "adi,adp5585";</div><div class='add'>+		reg = &lt;0x34&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;buck4&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-reserved-ranges = &lt;5 1&gt;;</div><div class='add'>+		#pwm-cells = &lt;3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c3 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	adp5585_isp: io-expander@34 {</div><div class='add'>+		compatible = "adi,adp5585-01", "adi,adp5585";</div><div class='add'>+		reg = &lt;0x34&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		#pwm-cells = &lt;3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ptn5110: tcpc@50 {</div><div class='add'>+		compatible = "nxp,ptn5110", "tcpci";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+		interrupts = &lt;27 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		typec1_con: connector {</div><div class='add'>+			compatible = "usb-c-connector";</div><div class='add'>+			label = "USB-C";</div><div class='add'>+			power-role = "dual";</div><div class='add'>+			data-role = "dual";</div><div class='add'>+			try-power-role = "sink";</div><div class='add'>+			source-pdos = &lt;PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)&gt;;</div><div class='add'>+			sink-pdos = &lt;PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)</div><div class='add'>+				     PDO_VAR(5000, 20000, 3000)&gt;;</div><div class='add'>+			op-sink-microwatt = &lt;15000000&gt;;</div><div class='add'>+			self-powered;</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					typec1_dr_sw: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;usb1_drd_sw&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ptn5110_2: tcpc@51 {</div><div class='add'>+		compatible = "nxp,ptn5110", "tcpci";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+		interrupts = &lt;27 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		typec2_con: connector {</div><div class='add'>+			compatible = "usb-c-connector";</div><div class='add'>+			label = "USB-C";</div><div class='add'>+			power-role = "dual";</div><div class='add'>+			data-role = "dual";</div><div class='add'>+			try-power-role = "sink";</div><div class='add'>+			source-pdos = &lt;PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)&gt;;</div><div class='add'>+			sink-pdos = &lt;PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)</div><div class='add'>+				     PDO_VAR(5000, 20000, 3000)&gt;;</div><div class='add'>+			op-sink-microwatt = &lt;15000000&gt;;</div><div class='add'>+			self-powered;</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					typec2_dr_sw: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;usb2_drd_sw&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcf2131: rtc@53 {</div><div class='add'>+		compatible = "nxp,pcf2131";</div><div class='add'>+		reg = &lt;0x53&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;pcal6524&gt;;</div><div class='add'>+		interrupts = &lt;1 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart1 { /* console */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart5 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart5&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "nxp,88w8987-bt";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;micfil {</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pdm&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_pdm_sleep&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX93_CLK_PDM&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX93_CLK_AUDIO_PLL&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;49152000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mu1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mu2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai1 {</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_sai1_sleep&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX93_CLK_SAI1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX93_CLK_AUDIO_PLL&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;12288000&gt;;</div><div class='add'>+	fsl,sai-mclk-direction-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai3 {</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_sai3_sleep&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX93_CLK_SAI3&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX93_CLK_AUDIO_PLL&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;12288000&gt;;</div><div class='add'>+	fsl,sai-mclk-direction-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	hnp-disable;</div><div class='add'>+	srp-disable;</div><div class='add'>+	adp-disable;</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	disable-over-current;</div><div class='add'>+	samsung,picophy-pre-emp-curr-control = &lt;3&gt;;</div><div class='add'>+	samsung,picophy-dc-vol-level-adjust = &lt;7&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	port {</div><div class='add'>+		usb1_drd_sw: endpoint {</div><div class='add'>+			remote-endpoint = &lt;&amp;typec1_dr_sw&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg2 {</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	hnp-disable;</div><div class='add'>+	srp-disable;</div><div class='add'>+	adp-disable;</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	disable-over-current;</div><div class='add'>+	samsung,picophy-pre-emp-curr-control = &lt;3&gt;;</div><div class='add'>+	samsung,picophy-dc-vol-level-adjust = &lt;7&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	port {</div><div class='add'>+		usb2_drd_sw: endpoint {</div><div class='add'>+			remote-endpoint = &lt;&amp;typec2_dr_sw&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1_200mhz&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-3 = &lt;&amp;pinctrl_usdhc2_sleep&gt;, &lt;&amp;pinctrl_usdhc2_gpio_sleep&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio3 00 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+	no-mmc;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;, &lt;&amp;pinctrl_usdhc3_wlan&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;, &lt;&amp;pinctrl_usdhc3_wlan&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;, &lt;&amp;pinctrl_usdhc3_wlan&gt;;</div><div class='add'>+	pinctrl-3 = &lt;&amp;pinctrl_usdhc3_sleep&gt;, &lt;&amp;pinctrl_usdhc3_wlan&gt;;</div><div class='add'>+	mmc-pwrseq = &lt;&amp;usdhc3_pwrseq&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc3_vmmc&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	keep-power-in-suspend;</div><div class='add'>+	non-removable;</div><div class='add'>+	wakeup-source;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xcvr {</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_spdif&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_spdif_sleep&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX93_CLK_SPDIF&gt;,</div><div class='add'>+			 &lt;&amp;clk IMX93_CLK_AUDIO_XCVR&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX93_CLK_AUDIO_PLL&gt;,</div><div class='add'>+			 &lt;&amp;clk IMX93_CLK_SYS_PLL_PFD1_DIV2&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;12288000&gt;, &lt;200000000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_eqos: eqosgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_ENET1_MDC__ENET_QOS_MDC			0x57e</div><div class='add'>+			MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO			0x57e</div><div class='add'>+			MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0			0x57e</div><div class='add'>+			MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1			0x57e</div><div class='add'>+			MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2			0x57e</div><div class='add'>+			MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3			0x57e</div><div class='add'>+			MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x58e</div><div class='add'>+			MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x57e</div><div class='add'>+			MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0			0x57e</div><div class='add'>+			MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1			0x57e</div><div class='add'>+			MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2			0x57e</div><div class='add'>+			MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3			0x57e</div><div class='add'>+			MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x58e</div><div class='add'>+			MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x57e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_eqos_sleep: eqossleepgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_ENET1_MDC__GPIO4_IO00				0x31e</div><div class='add'>+			MX93_PAD_ENET1_MDIO__GPIO4_IO01				0x31e</div><div class='add'>+			MX93_PAD_ENET1_RD0__GPIO4_IO10                          0x31e</div><div class='add'>+			MX93_PAD_ENET1_RD1__GPIO4_IO11				0x31e</div><div class='add'>+			MX93_PAD_ENET1_RD2__GPIO4_IO12				0x31e</div><div class='add'>+			MX93_PAD_ENET1_RD3__GPIO4_IO13				0x31e</div><div class='add'>+			MX93_PAD_ENET1_RXC__GPIO4_IO09                          0x31e</div><div class='add'>+			MX93_PAD_ENET1_RX_CTL__GPIO4_IO08			0x31e</div><div class='add'>+			MX93_PAD_ENET1_TD0__GPIO4_IO05                          0x31e</div><div class='add'>+			MX93_PAD_ENET1_TD1__GPIO4_IO04                          0x31e</div><div class='add'>+			MX93_PAD_ENET1_TD2__GPIO4_IO03				0x31e</div><div class='add'>+			MX93_PAD_ENET1_TD3__GPIO4_IO02				0x31e</div><div class='add'>+			MX93_PAD_ENET1_TXC__GPIO4_IO07                          0x31e</div><div class='add'>+			MX93_PAD_ENET1_TX_CTL__GPIO4_IO06                       0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec: fecgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_ENET2_MDC__ENET1_MDC			0x57e</div><div class='add'>+			MX93_PAD_ENET2_MDIO__ENET1_MDIO			0x57e</div><div class='add'>+			MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0		0x57e</div><div class='add'>+			MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1		0x57e</div><div class='add'>+			MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2		0x57e</div><div class='add'>+			MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3		0x57e</div><div class='add'>+			MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC		0x58e</div><div class='add'>+			MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL	0x57e</div><div class='add'>+			MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0		0x57e</div><div class='add'>+			MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1		0x57e</div><div class='add'>+			MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2		0x57e</div><div class='add'>+			MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3		0x57e</div><div class='add'>+			MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC		0x58e</div><div class='add'>+			MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL	0x57e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec_sleep: fecsleepgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_ENET2_MDC__GPIO4_IO14			0x51e</div><div class='add'>+			MX93_PAD_ENET2_MDIO__GPIO4_IO15			0x51e</div><div class='add'>+			MX93_PAD_ENET2_RD0__GPIO4_IO24			0x51e</div><div class='add'>+			MX93_PAD_ENET2_RD1__GPIO4_IO25			0x51e</div><div class='add'>+			MX93_PAD_ENET2_RD2__GPIO4_IO26			0x51e</div><div class='add'>+			MX93_PAD_ENET2_RD3__GPIO4_IO27			0x51e</div><div class='add'>+			MX93_PAD_ENET2_RXC__GPIO4_IO23                  0x51e</div><div class='add'>+			MX93_PAD_ENET2_RX_CTL__GPIO4_IO22		0x51e</div><div class='add'>+			MX93_PAD_ENET2_TD0__GPIO4_IO19			0x51e</div><div class='add'>+			MX93_PAD_ENET2_TD1__GPIO4_IO18			0x51e</div><div class='add'>+			MX93_PAD_ENET2_TD2__GPIO4_IO17			0x51e</div><div class='add'>+			MX93_PAD_ENET2_TD3__GPIO4_IO16			0x51e</div><div class='add'>+			MX93_PAD_ENET2_TXC__GPIO4_IO21                  0x51e</div><div class='add'>+			MX93_PAD_ENET2_TX_CTL__GPIO4_IO20               0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan2: flexcan2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_GPIO_IO25__CAN2_TX	0x139e</div><div class='add'>+			MX93_PAD_GPIO_IO27__CAN2_RX	0x139e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_UART1_RXD__LPUART1_RX			0x31e</div><div class='add'>+			MX93_PAD_UART1_TXD__LPUART1_TX			0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart5: uart5grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX		0x31e</div><div class='add'>+			MX93_PAD_DAP_TDI__LPUART5_RX			0x31e</div><div class='add'>+			MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B		0x31e</div><div class='add'>+			MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c1: lpi2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_I2C1_SCL__LPI2C1_SCL			0x40000b9e</div><div class='add'>+			MX93_PAD_I2C1_SDA__LPI2C1_SDA			0x40000b9e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c2: lpi2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_I2C2_SCL__LPI2C2_SCL			0x40000b9e</div><div class='add'>+			MX93_PAD_I2C2_SDA__LPI2C2_SDA			0x40000b9e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c3: lpi2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_GPIO_IO28__LPI2C3_SDA			0x40000b9e</div><div class='add'>+			MX93_PAD_GPIO_IO29__LPI2C3_SCL			0x40000b9e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcal6524: pcal6524grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_CCM_CLKO2__GPIO3_IO27			0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pdm: pdmgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_PDM_CLK__PDM_CLK			0x31e</div><div class='add'>+			MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00	0x31e</div><div class='add'>+			MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01	0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pdm_sleep: pdmsleepgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_PDM_CLK__GPIO1_IO08			0x31e</div><div class='add'>+			MX93_PAD_PDM_BIT_STREAM0__GPIO1_IO09		0x31e</div><div class='add'>+			MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai1: sai1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SAI1_TXC__SAI1_TX_BCLK			0x31e</div><div class='add'>+			MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC		0x31e</div><div class='add'>+			MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00		0x31e</div><div class='add'>+			MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai1_sleep: sai1sleepgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SAI1_TXC__GPIO1_IO12                   0x51e</div><div class='add'>+			MX93_PAD_SAI1_TXFS__GPIO1_IO11			0x51e</div><div class='add'>+			MX93_PAD_SAI1_TXD0__GPIO1_IO13			0x51e</div><div class='add'>+			MX93_PAD_SAI1_RXD0__GPIO1_IO14			0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* need to config the SION for data and cmd pad, refer to ERR052021 */</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD1_CLK__USDHC1_CLK		0x1582</div><div class='add'>+			MX93_PAD_SD1_CMD__USDHC1_CMD		0x40001382</div><div class='add'>+			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x40001382</div><div class='add'>+			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x40001382</div><div class='add'>+			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x40001382</div><div class='add'>+			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x40001382</div><div class='add'>+			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x40001382</div><div class='add'>+			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x40001382</div><div class='add'>+			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x40001382</div><div class='add'>+			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x40001382</div><div class='add'>+			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x1582</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* need to config the SION for data and cmd pad, refer to ERR052021 */</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD1_CLK__USDHC1_CLK		0x158e</div><div class='add'>+			MX93_PAD_SD1_CMD__USDHC1_CMD		0x4000138e</div><div class='add'>+			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x4000138e</div><div class='add'>+			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x4000138e</div><div class='add'>+			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x4000138e</div><div class='add'>+			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x4000138e</div><div class='add'>+			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x4000138e</div><div class='add'>+			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x4000138e</div><div class='add'>+			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x4000138e</div><div class='add'>+			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x4000138e</div><div class='add'>+			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x158e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* need to config the SION for data and cmd pad, refer to ERR052021 */</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD1_CLK__USDHC1_CLK		0x15fe</div><div class='add'>+			MX93_PAD_SD1_CMD__USDHC1_CMD		0x400013fe</div><div class='add'>+			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x400013fe</div><div class='add'>+			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x400013fe</div><div class='add'>+			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x400013fe</div><div class='add'>+			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x400013fe</div><div class='add'>+			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x400013fe</div><div class='add'>+			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x400013fe</div><div class='add'>+			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x400013fe</div><div class='add'>+			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x400013fe</div><div class='add'>+			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x15fe</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD2_RESET_B__GPIO3_IO07	0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai3: sai3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_GPIO_IO26__SAI3_TX_SYNC                0x31e</div><div class='add'>+			MX93_PAD_GPIO_IO16__SAI3_TX_BCLK                0x31e</div><div class='add'>+			MX93_PAD_GPIO_IO17__SAI3_MCLK           0x31e</div><div class='add'>+			MX93_PAD_GPIO_IO19__SAI3_TX_DATA00              0x31e</div><div class='add'>+			MX93_PAD_GPIO_IO20__SAI3_RX_DATA00              0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai3_sleep: sai3sleepgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_GPIO_IO26__GPIO2_IO26			0x51e</div><div class='add'>+			MX93_PAD_GPIO_IO16__GPIO2_IO16			0x51e</div><div class='add'>+			MX93_PAD_GPIO_IO17__GPIO2_IO17			0x51e</div><div class='add'>+			MX93_PAD_GPIO_IO19__GPIO2_IO19			0x51e</div><div class='add'>+			MX93_PAD_GPIO_IO20__GPIO2_IO20			0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_spdif: spdifgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_GPIO_IO22__SPDIF_IN		0x31e</div><div class='add'>+			MX93_PAD_GPIO_IO23__SPDIF_OUT		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_spdif_sleep: spdifsleepgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_GPIO_IO22__GPIO2_IO22		0x31e</div><div class='add'>+			MX93_PAD_GPIO_IO23__GPIO2_IO23		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD2_CD_B__GPIO3_IO00		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD2_CD_B__GPIO3_IO00		0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* need to config the SION for data and cmd pad, refer to ERR052021 */</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD2_CLK__USDHC2_CLK		0x1582</div><div class='add'>+			MX93_PAD_SD2_CMD__USDHC2_CMD		0x40001382</div><div class='add'>+			MX93_PAD_SD2_DATA0__USDHC2_DATA0	0x40001382</div><div class='add'>+			MX93_PAD_SD2_DATA1__USDHC2_DATA1	0x40001382</div><div class='add'>+			MX93_PAD_SD2_DATA2__USDHC2_DATA2	0x40001382</div><div class='add'>+			MX93_PAD_SD2_DATA3__USDHC2_DATA3	0x40001382</div><div class='add'>+			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* need to config the SION for data and cmd pad, refer to ERR052021 */</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD2_CLK__USDHC2_CLK		0x158e</div><div class='add'>+			MX93_PAD_SD2_CMD__USDHC2_CMD		0x4000138e</div><div class='add'>+			MX93_PAD_SD2_DATA0__USDHC2_DATA0	0x4000138e</div><div class='add'>+			MX93_PAD_SD2_DATA1__USDHC2_DATA1	0x4000138e</div><div class='add'>+			MX93_PAD_SD2_DATA2__USDHC2_DATA2	0x4000138e</div><div class='add'>+			MX93_PAD_SD2_DATA3__USDHC2_DATA3	0x4000138e</div><div class='add'>+			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* need to config the SION for data and cmd pad, refer to ERR052021 */</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD2_CLK__USDHC2_CLK		0x15fe</div><div class='add'>+			MX93_PAD_SD2_CMD__USDHC2_CMD		0x400013fe</div><div class='add'>+			MX93_PAD_SD2_DATA0__USDHC2_DATA0	0x400013fe</div><div class='add'>+			MX93_PAD_SD2_DATA1__USDHC2_DATA1	0x400013fe</div><div class='add'>+			MX93_PAD_SD2_DATA2__USDHC2_DATA2	0x400013fe</div><div class='add'>+			MX93_PAD_SD2_DATA3__USDHC2_DATA3	0x400013fe</div><div class='add'>+			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_sleep: usdhc2sleepgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD2_CLK__GPIO3_IO01            0x51e</div><div class='add'>+			MX93_PAD_SD2_CMD__GPIO3_IO02		0x51e</div><div class='add'>+			MX93_PAD_SD2_DATA0__GPIO3_IO03		0x51e</div><div class='add'>+			MX93_PAD_SD2_DATA1__GPIO3_IO04		0x51e</div><div class='add'>+			MX93_PAD_SD2_DATA2__GPIO3_IO05		0x51e</div><div class='add'>+			MX93_PAD_SD2_DATA3__GPIO3_IO06		0x51e</div><div class='add'>+			MX93_PAD_SD2_VSELECT__GPIO3_IO19	0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* need to config the SION for data and cmd pad, refer to ERR052021 */</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD3_CLK__USDHC3_CLK		0x1582</div><div class='add'>+			MX93_PAD_SD3_CMD__USDHC3_CMD		0x40001382</div><div class='add'>+			MX93_PAD_SD3_DATA0__USDHC3_DATA0	0x40001382</div><div class='add'>+			MX93_PAD_SD3_DATA1__USDHC3_DATA1	0x40001382</div><div class='add'>+			MX93_PAD_SD3_DATA2__USDHC3_DATA2	0x40001382</div><div class='add'>+			MX93_PAD_SD3_DATA3__USDHC3_DATA3	0x40001382</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* need to config the SION for data and cmd pad, refer to ERR052021 */</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD3_CLK__USDHC3_CLK		0x158e</div><div class='add'>+			MX93_PAD_SD3_CMD__USDHC3_CMD		0x4000138e</div><div class='add'>+			MX93_PAD_SD3_DATA0__USDHC3_DATA0	0x4000138e</div><div class='add'>+			MX93_PAD_SD3_DATA1__USDHC3_DATA1	0x4000138e</div><div class='add'>+			MX93_PAD_SD3_DATA2__USDHC3_DATA2	0x4000138e</div><div class='add'>+			MX93_PAD_SD3_DATA3__USDHC3_DATA3	0x4000138e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* need to config the SION for data and cmd pad, refer to ERR052021 */</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD3_CLK__USDHC3_CLK		0x15fe</div><div class='add'>+			MX93_PAD_SD3_CMD__USDHC3_CMD		0x400013fe</div><div class='add'>+			MX93_PAD_SD3_DATA0__USDHC3_DATA0	0x400013fe</div><div class='add'>+			MX93_PAD_SD3_DATA1__USDHC3_DATA1	0x400013fe</div><div class='add'>+			MX93_PAD_SD3_DATA2__USDHC3_DATA2	0x400013fe</div><div class='add'>+			MX93_PAD_SD3_DATA3__USDHC3_DATA3	0x400013fe</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_sleep: usdhc3grpsleepgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD3_CLK__GPIO3_IO20		0x31e</div><div class='add'>+			MX93_PAD_SD3_CMD__GPIO3_IO21		0x31e</div><div class='add'>+			MX93_PAD_SD3_DATA0__GPIO3_IO22		0x31e</div><div class='add'>+			MX93_PAD_SD3_DATA1__GPIO3_IO23		0x31e</div><div class='add'>+			MX93_PAD_SD3_DATA2__GPIO3_IO24		0x31e</div><div class='add'>+			MX93_PAD_SD3_DATA3__GPIO3_IO25		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_wlan: usdhc3wlangrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_CCM_CLKO1__GPIO3_IO26		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY	0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts b/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts<br/>new file mode 100644<br/>index 000000000000..f9eebd27d640<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts</a></div><div class='hunk'>@@ -0,0 +1,674 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/usb/pd.h&gt;</div><div class='add'>+#include "imx93.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "NXP i.MX93 14X14 EVK board";</div><div class='add'>+	compatible = "fsl,imx93-14x14-evk", "fsl,imx93";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;fec;</div><div class='add'>+		ethernet1 = &amp;eqos;</div><div class='add'>+		gpio0 = &amp;gpio1;</div><div class='add'>+		gpio1 = &amp;gpio2;</div><div class='add'>+		gpio2 = &amp;gpio3;</div><div class='add'>+		i2c0 = &amp;lpi2c1;</div><div class='add'>+		i2c1 = &amp;lpi2c2;</div><div class='add'>+		i2c2 = &amp;lpi2c3;</div><div class='add'>+		mmc0 = &amp;usdhc1;</div><div class='add'>+		mmc1 = &amp;usdhc2;</div><div class='add'>+		rtc0 = &amp;bbnsm_rtc;</div><div class='add'>+		serial0 = &amp;lpuart1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;lpuart1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		linux,cma {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reusable;</div><div class='add'>+			alloc-ranges = &lt;0 0x80000000 0 0x40000000&gt;;</div><div class='add'>+			size = &lt;0 0x10000000&gt;;</div><div class='add'>+			linux,cma-default;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev0vring0: vdev0vring0@a4000000 {</div><div class='add'>+			reg = &lt;0 0xa4000000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev0vring1: vdev0vring1@a4008000 {</div><div class='add'>+			reg = &lt;0 0xa4008000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev1vring0: vdev1vring0@a4010000 {</div><div class='add'>+			reg = &lt;0 0xa4010000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev1vring1: vdev1vring1@a4018000 {</div><div class='add'>+			reg = &lt;0 0xa4018000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rsc_table: rsc-table@2021e000 {</div><div class='add'>+			reg = &lt;0 0x2021e000 0 0x1000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdevbuffer: vdevbuffer@a4020000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0xa4020000 0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_can1_stby: regulator-can1-stby {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "can1-stby";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;pcal6524_2 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		vin-supply = &lt;&amp;reg_can1_en&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_can1_en: regulator-can1-en {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "can1-en";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;pcal6524_2 12 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_can2_stby: regulator-can2-stby {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "can2-stby";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;pcal6524_2 11 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		vin-supply = &lt;&amp;reg_can2_en&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_can2_en: regulator-can2-en {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "can2-en";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;pcal6524_2 13 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_m2_pwr: regulator-m2-pwr {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "M.2-power";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;pcal6524 13 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usdhc2_vmmc&gt;;</div><div class='add'>+		regulator-name = "VSD_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio3 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		off-on-delay-us = &lt;12000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc3_vmmc: regulator-usdhc3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "WLAN_EN";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;reg_m2_pwr&gt;;</div><div class='add'>+		gpio = &lt;&amp;pcal6524 20 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		/*</div><div class='add'>+		 * IW612 wifi chip needs more delay than other wifi chips to complete</div><div class='add'>+		 * the host interface initialization after power up, otherwise the</div><div class='add'>+		 * internal state of IW612 may be unstable, resulting in the failure of</div><div class='add'>+		 * the SDIO3.0 switch voltage.</div><div class='add'>+		 */</div><div class='add'>+		startup-delay-us = &lt;20000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vdd_12v: regulator-vdd-12v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "reg_vdd_12v";</div><div class='add'>+		regulator-min-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;12000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;pcal6524 14 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vref_1v8: regulator-adc-vref {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vref_1v8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usdhc3_pwrseq: usdhc3_pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-simple";</div><div class='add'>+		reset-gpios = &lt;&amp;pcal6524 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;adc1 {</div><div class='add'>+	vref-supply = &lt;&amp;reg_vref_1v8&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cm33 {</div><div class='add'>+	mbox-names = "tx", "rx", "rxdb";</div><div class='add'>+	mboxes = &lt;&amp;mu1 0 1&gt;,</div><div class='add'>+		 &lt;&amp;mu1 1 1&gt;,</div><div class='add'>+		 &lt;&amp;mu1 3 1&gt;;</div><div class='add'>+	memory-region = &lt;&amp;vdevbuffer&gt;, &lt;&amp;vdev0vring0&gt;, &lt;&amp;vdev0vring1&gt;,</div><div class='add'>+			&lt;&amp;vdev1vring0&gt;, &lt;&amp;vdev1vring1&gt;, &lt;&amp;rsc_table&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy2&gt;;</div><div class='add'>+	fsl,magic-packet;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;5000000&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy2: ethernet-phy@2 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;2&gt;;</div><div class='add'>+			eee-broken-1000t;</div><div class='add'>+			reset-gpios = &lt;&amp;pcal6524 16 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;10000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;80000&gt;;</div><div class='add'>+			realtek,clkout-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan1&gt;;</div><div class='add'>+	xceiver-supply = &lt;&amp;reg_can1_stby&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan2&gt;;</div><div class='add'>+	xceiver-supply = &lt;&amp;reg_can2_stby&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c1 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	lsm6dsm@6a {</div><div class='add'>+		compatible = "st,lsm6dso";</div><div class='add'>+		reg = &lt;0x6a&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pcal6524_2: gpio@20 {</div><div class='add'>+		compatible = "nxp,pcal6524";</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcal6524: gpio@22 {</div><div class='add'>+		compatible = "nxp,pcal6524";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pcal6524&gt;;</div><div class='add'>+		reg = &lt;0x22&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+		interrupts = &lt;27 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmic@25 {</div><div class='add'>+		compatible = "nxp,pca9452";</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;pcal6524&gt;;</div><div class='add'>+		interrupts = &lt;11 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			buck1: BUCK1 {</div><div class='add'>+				regulator-name = "BUCK1";</div><div class='add'>+				regulator-min-microvolt = &lt;610000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;950000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck2: BUCK2 {</div><div class='add'>+				regulator-name = "BUCK2";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;670000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck4: BUCK4 {</div><div class='add'>+				regulator-name = "BUCK4";</div><div class='add'>+				regulator-min-microvolt = &lt;1620000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck5: BUCK5 {</div><div class='add'>+				regulator-name = "BUCK5";</div><div class='add'>+				regulator-min-microvolt = &lt;1620000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck6: BUCK6 {</div><div class='add'>+				regulator-name = "BUCK6";</div><div class='add'>+				regulator-min-microvolt = &lt;1060000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1140000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo1: LDO1 {</div><div class='add'>+				regulator-name = "LDO1";</div><div class='add'>+				regulator-min-microvolt = &lt;1620000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1980000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo3: LDO3 {</div><div class='add'>+				regulator-name = "LDO3";</div><div class='add'>+				regulator-min-microvolt = &lt;1710000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1890000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo4: LDO4 {</div><div class='add'>+				regulator-name = "LDO4";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;840000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo5: LDO5 {</div><div class='add'>+				regulator-name = "LDO5";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c3 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart1 { /* console */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mu1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mu2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	hnp-disable;</div><div class='add'>+	srp-disable;</div><div class='add'>+	adp-disable;</div><div class='add'>+	disable-over-current;</div><div class='add'>+	samsung,picophy-pre-emp-curr-control = &lt;3&gt;;</div><div class='add'>+	samsung,picophy-dc-vol-level-adjust = &lt;7&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg2 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	disable-over-current;</div><div class='add'>+	samsung,picophy-pre-emp-curr-control = &lt;3&gt;;</div><div class='add'>+	samsung,picophy-dc-vol-level-adjust = &lt;7&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1_200mhz&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio3 00 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	no-mmc;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;, &lt;&amp;pinctrl_usdhc3_wlan&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;, &lt;&amp;pinctrl_usdhc3_wlan&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;, &lt;&amp;pinctrl_usdhc3_wlan&gt;;</div><div class='add'>+	pinctrl-3 = &lt;&amp;pinctrl_usdhc3_sleep&gt;, &lt;&amp;pinctrl_usdhc3_wlan&gt;;</div><div class='add'>+	mmc-pwrseq = &lt;&amp;usdhc3_pwrseq&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc3_vmmc&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	keep-power-in-suspend;</div><div class='add'>+	non-removable;</div><div class='add'>+	wakeup-source;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_flexcan1: flexcan1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_PDM_CLK__CAN1_TX		0x139e</div><div class='add'>+			MX93_PAD_PDM_BIT_STREAM0__CAN1_RX	0x139e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan2: flexcan2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_GPIO_IO25__CAN2_TX	0x139e</div><div class='add'>+			MX93_PAD_GPIO_IO27__CAN2_RX	0x139e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c1: lpi2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_I2C1_SCL__LPI2C1_SCL			0x40000b9e</div><div class='add'>+			MX93_PAD_I2C1_SDA__LPI2C1_SDA			0x40000b9e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c2: lpi2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_I2C2_SCL__LPI2C2_SCL			0x40000b9e</div><div class='add'>+			MX93_PAD_I2C2_SDA__LPI2C2_SDA			0x40000b9e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c3: lpi2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_GPIO_IO28__LPI2C3_SDA			0x40000b9e</div><div class='add'>+			MX93_PAD_GPIO_IO29__LPI2C3_SCL			0x40000b9e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcal6524: pcal6524grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_CCM_CLKO2__GPIO3_IO27			0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec: fecgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_ENET2_MDC__ENET1_MDC			0x57e</div><div class='add'>+			MX93_PAD_ENET2_MDIO__ENET1_MDIO			0x57e</div><div class='add'>+			MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0		0x57e</div><div class='add'>+			MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1		0x57e</div><div class='add'>+			MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2		0x57e</div><div class='add'>+			MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3		0x57e</div><div class='add'>+			MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC		0x58e</div><div class='add'>+			MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL	0x57e</div><div class='add'>+			MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0		0x57e</div><div class='add'>+			MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1		0x57e</div><div class='add'>+			MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2		0x57e</div><div class='add'>+			MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3		0x57e</div><div class='add'>+			MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC		0x58e</div><div class='add'>+			MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL	0x57e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_UART1_RXD__LPUART1_RX			0x31e</div><div class='add'>+			MX93_PAD_UART1_TXD__LPUART1_TX			0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart5: uart5grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX	0x31e</div><div class='add'>+			MX93_PAD_DAP_TDI__LPUART5_RX		0x31e</div><div class='add'>+			MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B	0x31e</div><div class='add'>+			MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B	0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* need to config the SION for data and cmd pad, refer to ERR052021 */</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD1_CLK__USDHC1_CLK		0x1582</div><div class='add'>+			MX93_PAD_SD1_CMD__USDHC1_CMD		0x40001382</div><div class='add'>+			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x40001382</div><div class='add'>+			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x40001382</div><div class='add'>+			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x40001382</div><div class='add'>+			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x40001382</div><div class='add'>+			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x40001382</div><div class='add'>+			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x40001382</div><div class='add'>+			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x40001382</div><div class='add'>+			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x40001382</div><div class='add'>+			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x1582</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* need to config the SION for data and cmd pad, refer to ERR052021 */</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD1_CLK__USDHC1_CLK		0x158e</div><div class='add'>+			MX93_PAD_SD1_CMD__USDHC1_CMD		0x4000138e</div><div class='add'>+			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x4000138e</div><div class='add'>+			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x4000138e</div><div class='add'>+			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x4000138e</div><div class='add'>+			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x4000138e</div><div class='add'>+			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x4000138e</div><div class='add'>+			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x4000138e</div><div class='add'>+			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x4000138e</div><div class='add'>+			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x4000138e</div><div class='add'>+			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x158e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* need to config the SION for data and cmd pad, refer to ERR052021 */</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD1_CLK__USDHC1_CLK		0x15fe</div><div class='add'>+			MX93_PAD_SD1_CMD__USDHC1_CMD		0x400013fe</div><div class='add'>+			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x400013fe</div><div class='add'>+			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x400013fe</div><div class='add'>+			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x400013fe</div><div class='add'>+			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x400013fe</div><div class='add'>+			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x400013fe</div><div class='add'>+			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x400013fe</div><div class='add'>+			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x400013fe</div><div class='add'>+			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x400013fe</div><div class='add'>+			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x15fe</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD2_RESET_B__GPIO3_IO07	0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD2_CD_B__GPIO3_IO00		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* need to config the SION for data and cmd pad, refer to ERR052021 */</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD2_CLK__USDHC2_CLK		0x1582</div><div class='add'>+			MX93_PAD_SD2_CMD__USDHC2_CMD		0x40001382</div><div class='add'>+			MX93_PAD_SD2_DATA0__USDHC2_DATA0	0x40001382</div><div class='add'>+			MX93_PAD_SD2_DATA1__USDHC2_DATA1	0x40001382</div><div class='add'>+			MX93_PAD_SD2_DATA2__USDHC2_DATA2	0x40001382</div><div class='add'>+			MX93_PAD_SD2_DATA3__USDHC2_DATA3	0x40001382</div><div class='add'>+			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* need to config the SION for data and cmd pad, refer to ERR052021 */</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD2_CLK__USDHC2_CLK		0x158e</div><div class='add'>+			MX93_PAD_SD2_CMD__USDHC2_CMD		0x4000138e</div><div class='add'>+			MX93_PAD_SD2_DATA0__USDHC2_DATA0	0x4000138e</div><div class='add'>+			MX93_PAD_SD2_DATA1__USDHC2_DATA1	0x4000138e</div><div class='add'>+			MX93_PAD_SD2_DATA2__USDHC2_DATA2	0x4000138e</div><div class='add'>+			MX93_PAD_SD2_DATA3__USDHC2_DATA3	0x4000138e</div><div class='add'>+			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* need to config the SION for data and cmd pad, refer to ERR052021 */</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD2_CLK__USDHC2_CLK		0x15fe</div><div class='add'>+			MX93_PAD_SD2_CMD__USDHC2_CMD		0x400013fe</div><div class='add'>+			MX93_PAD_SD2_DATA0__USDHC2_DATA0	0x400013fe</div><div class='add'>+			MX93_PAD_SD2_DATA1__USDHC2_DATA1	0x400013fe</div><div class='add'>+			MX93_PAD_SD2_DATA2__USDHC2_DATA2	0x400013fe</div><div class='add'>+			MX93_PAD_SD2_DATA3__USDHC2_DATA3	0x400013fe</div><div class='add'>+			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* need to config the SION for data and cmd pad, refer to ERR052021 */</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD3_CLK__USDHC3_CLK		0x1582</div><div class='add'>+			MX93_PAD_SD3_CMD__USDHC3_CMD		0x40001382</div><div class='add'>+			MX93_PAD_SD3_DATA0__USDHC3_DATA0	0x40001382</div><div class='add'>+			MX93_PAD_SD3_DATA1__USDHC3_DATA1	0x40001382</div><div class='add'>+			MX93_PAD_SD3_DATA2__USDHC3_DATA2	0x40001382</div><div class='add'>+			MX93_PAD_SD3_DATA3__USDHC3_DATA3	0x40001382</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* need to config the SION for data and cmd pad, refer to ERR052021 */</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD3_CLK__USDHC3_CLK		0x158e</div><div class='add'>+			MX93_PAD_SD3_CMD__USDHC3_CMD		0x4000138e</div><div class='add'>+			MX93_PAD_SD3_DATA0__USDHC3_DATA0	0x4000138e</div><div class='add'>+			MX93_PAD_SD3_DATA1__USDHC3_DATA1	0x4000138e</div><div class='add'>+			MX93_PAD_SD3_DATA2__USDHC3_DATA2	0x4000138e</div><div class='add'>+			MX93_PAD_SD3_DATA3__USDHC3_DATA3	0x4000138e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* need to config the SION for data and cmd pad, refer to ERR052021 */</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD3_CLK__USDHC3_CLK		0x15fe</div><div class='add'>+			MX93_PAD_SD3_CMD__USDHC3_CMD		0x400013fe</div><div class='add'>+			MX93_PAD_SD3_DATA0__USDHC3_DATA0	0x400013fe</div><div class='add'>+			MX93_PAD_SD3_DATA1__USDHC3_DATA1	0x400013fe</div><div class='add'>+			MX93_PAD_SD3_DATA2__USDHC3_DATA2	0x400013fe</div><div class='add'>+			MX93_PAD_SD3_DATA3__USDHC3_DATA3	0x400013fe</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_sleep: usdhc3grpsleepgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD3_CLK__GPIO3_IO20		0x31e</div><div class='add'>+			MX93_PAD_SD3_CMD__GPIO3_IO21		0x31e</div><div class='add'>+			MX93_PAD_SD3_DATA0__GPIO3_IO22		0x31e</div><div class='add'>+			MX93_PAD_SD3_DATA1__GPIO3_IO23		0x31e</div><div class='add'>+			MX93_PAD_SD3_DATA2__GPIO3_IO24		0x31e</div><div class='add'>+			MX93_PAD_SD3_DATA3__GPIO3_IO25		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_wlan: usdhc3wlangrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_CCM_CLKO1__GPIO3_IO26	  0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY	0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-i3c.dtso b/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-i3c.dtso<br/>new file mode 100644<br/>index 000000000000..3fe6209a3423<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-i3c.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx93-9x9-qsb-i3c.dtso</a></div><div class='hunk'>@@ -0,0 +1,72 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/i3c/i3c.h&gt;</div><div class='add'>+#include &lt;dt-bindings/usb/pd.h&gt;</div><div class='add'>+</div><div class='add'>+#include "imx93-pinfunc.h"</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+&amp;lpi2c1 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i3c1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i3c1&gt;;</div><div class='add'>+	#address-cells = &lt;3&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	i2c-scl-hz = &lt;400000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	tcpc@50 {</div><div class='add'>+		compatible = "nxp,ptn5110", "tcpci";</div><div class='add'>+		reg = &lt;0x50 0x00 (I2C_FM | I2C_NO_FILTER_LOW_FREQUENCY)&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+		interrupts = &lt;26 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		connector {</div><div class='add'>+			compatible = "usb-c-connector";</div><div class='add'>+			label = "USB-C";</div><div class='add'>+			power-role = "dual";</div><div class='add'>+			data-role = "dual";</div><div class='add'>+			try-power-role = "sink";</div><div class='add'>+			source-pdos = &lt;PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)&gt;;</div><div class='add'>+			sink-pdos = &lt;PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)</div><div class='add'>+				     PDO_VAR(5000, 20000, 3000)&gt;;</div><div class='add'>+			op-sink-microwatt = &lt;15000000&gt;;</div><div class='add'>+			self-powered;</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					typec1_dr_sw: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;usb1_drd_sw&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb1_drd_sw {</div><div class='add'>+	remote-endpoint = &lt;&amp;typec1_dr_sw&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_i3c1: i3c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_I2C1_SCL__I3C1_SCL	0x40000186</div><div class='add'>+			MX93_PAD_I2C1_SDA__I3C1_SDA	0x40000186</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts b/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts<br/>new file mode 100644<br/>index 000000000000..0852067eab2c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts</a></div><div class='hunk'>@@ -0,0 +1,772 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-only OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/usb/pd.h&gt;</div><div class='add'>+#include "imx93.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "NXP i.MX93 9x9 Quick Start Board";</div><div class='add'>+	compatible = "fsl,imx93-9x9-qsb", "fsl,imx93";</div><div class='add'>+</div><div class='add'>+	bt_sco_codec: bt-sco-codec {</div><div class='add'>+		#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+		compatible = "linux,bt-sco";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;fec;</div><div class='add'>+		ethernet1 = &amp;eqos;</div><div class='add'>+		gpio0 = &amp;gpio1;</div><div class='add'>+		gpio1 = &amp;gpio2;</div><div class='add'>+		gpio2 = &amp;gpio3;</div><div class='add'>+		i2c0 = &amp;lpi2c1;</div><div class='add'>+		i2c1 = &amp;lpi2c2;</div><div class='add'>+		mmc0 = &amp;usdhc1;</div><div class='add'>+		mmc1 = &amp;usdhc2;</div><div class='add'>+		rtc0 = &amp;bbnsm_rtc;</div><div class='add'>+		serial0 = &amp;lpuart1;</div><div class='add'>+		serial1 = &amp;lpuart2;</div><div class='add'>+		serial2 = &amp;lpuart3;</div><div class='add'>+		serial3 = &amp;lpuart4;</div><div class='add'>+		serial4 = &amp;lpuart5;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;lpuart1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		linux,cma {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reusable;</div><div class='add'>+			size = &lt;0 0x10000000&gt;;</div><div class='add'>+			linux,cma-default;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev0vring0: vdev0vring0@a4000000 {</div><div class='add'>+			reg = &lt;0 0xa4000000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev0vring1: vdev0vring1@a4008000 {</div><div class='add'>+			reg = &lt;0 0xa4008000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev1vring0: vdev1vring0@a4010000 {</div><div class='add'>+			reg = &lt;0 0xa4010000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev1vring1: vdev1vring1@a4018000 {</div><div class='add'>+			reg = &lt;0 0xa4018000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rsc_table: rsc-table@2021e000 {</div><div class='add'>+			reg = &lt;0 0x2021e000 0 0x1000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdevbuffer: vdevbuffer@a4020000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0xa4020000 0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vref_1v8: regulator-adc-vref {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VREF_1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_audio_pwr: regulator-audio-pwr {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "audio-pwr";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;pcal6524 16 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_m2_pwr: regulator-m2-pwr {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "M.2-power";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;pcal6524 13 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_rpi_3v3: regulator-rpi {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_RPI_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;pcal6524 21 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usdhc2_vmmc&gt;;</div><div class='add'>+		regulator-name = "VSD_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio3 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		off-on-delay-us = &lt;12000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc3_vmmc: regulator-usdhc3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "WLAN_EN";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;reg_m2_pwr&gt;;</div><div class='add'>+		gpio = &lt;&amp;pcal6524 20 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		/*</div><div class='add'>+		 * IW612 wifi chip needs more delay than other wifi chips to complete</div><div class='add'>+		 * the host interface initialization after power up, otherwise the</div><div class='add'>+		 * internal state of IW612 may be unstable, resulting in the failure of</div><div class='add'>+		 * the SDIO3.0 switch voltage.</div><div class='add'>+		 */</div><div class='add'>+		startup-delay-us = &lt;20000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-bt-sco {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,name = "bt-sco-audio";</div><div class='add'>+		simple-audio-card,format = "dsp_a";</div><div class='add'>+		simple-audio-card,bitclock-inversion;</div><div class='add'>+		simple-audio-card,frame-master = &lt;&amp;btcpu&gt;;</div><div class='add'>+		simple-audio-card,bitclock-master = &lt;&amp;btcpu&gt;;</div><div class='add'>+</div><div class='add'>+		btcpu: simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;sai1&gt;;</div><div class='add'>+			dai-tdm-slot-num = &lt;2&gt;;</div><div class='add'>+			dai-tdm-slot-width = &lt;16&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		simple-audio-card,codec {</div><div class='add'>+			sound-dai = &lt;&amp;bt_sco_codec 1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-micfil {</div><div class='add'>+		compatible = "fsl,imx-audio-card";</div><div class='add'>+		model = "micfil-audio";</div><div class='add'>+</div><div class='add'>+		pri-dai-link {</div><div class='add'>+			link-name = "micfil hifi";</div><div class='add'>+			format = "i2s";</div><div class='add'>+</div><div class='add'>+			cpu {</div><div class='add'>+				sound-dai = &lt;&amp;micfil&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-wm8962 {</div><div class='add'>+		compatible = "fsl,imx-audio-wm8962";</div><div class='add'>+		model = "wm8962-audio";</div><div class='add'>+		audio-cpu = &lt;&amp;sai3&gt;;</div><div class='add'>+		audio-codec = &lt;&amp;wm8962&gt;;</div><div class='add'>+		hp-det-gpio = &lt;&amp;pcal6524 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		audio-routing =</div><div class='add'>+			"Headphone Jack", "HPOUTL",</div><div class='add'>+			"Headphone Jack", "HPOUTR",</div><div class='add'>+			"Ext Spk", "SPKOUTL",</div><div class='add'>+			"Ext Spk", "SPKOUTR",</div><div class='add'>+			"AMIC", "MICBIAS",</div><div class='add'>+			"IN3R", "AMIC",</div><div class='add'>+			"IN1R", "AMIC";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usdhc3_pwrseq: usdhc3_pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-simple";</div><div class='add'>+		reset-gpios = &lt;&amp;pcal6524 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;adc1 {</div><div class='add'>+	vref-supply = &lt;&amp;reg_vref_1v8&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cm33 {</div><div class='add'>+	mbox-names = "tx", "rx", "rxdb";</div><div class='add'>+	mboxes = &lt;&amp;mu1 0 1&gt;,</div><div class='add'>+		 &lt;&amp;mu1 1 1&gt;,</div><div class='add'>+		 &lt;&amp;mu1 3 1&gt;;</div><div class='add'>+	memory-region = &lt;&amp;vdevbuffer&gt;, &lt;&amp;vdev0vring0&gt;, &lt;&amp;vdev0vring1&gt;,</div><div class='add'>+			&lt;&amp;vdev1vring0&gt;, &lt;&amp;vdev1vring1&gt;, &lt;&amp;rsc_table&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eqos {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_eqos&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;5000000&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy1: ethernet-phy@1 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;pcal6524 15 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;10000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;80000&gt;;</div><div class='add'>+			realtek,clkout-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c1 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	wm8962: audio-codec@1a {</div><div class='add'>+		compatible = "wlf,wm8962";</div><div class='add'>+		reg = &lt;0x1a&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX93_CLK_SAI3_GATE&gt;;</div><div class='add'>+		DCVDD-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+		DBVDD-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+		AVDD-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+		CPVDD-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+		MICVDD-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+		PLLVDD-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+		SPKVDD1-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+		SPKVDD2-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+		gpio-cfg = &lt;</div><div class='add'>+			0x0000 /* 0:Default */</div><div class='add'>+			0x0000 /* 1:Default */</div><div class='add'>+			0x0000 /* 2:FN_DMICCLK */</div><div class='add'>+			0x0000 /* 3:Default */</div><div class='add'>+			0x0000 /* 4:FN_DMICCDAT */</div><div class='add'>+			0x0000 /* 5:Default */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	p3t1085: temperature-sensor@48 {</div><div class='add'>+		compatible = "nxp,p3t1085";</div><div class='add'>+		reg = &lt;0x48&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ptn5110: tcpc@50 {</div><div class='add'>+		compatible = "nxp,ptn5110", "tcpci";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+		interrupts = &lt;26 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		typec1_con: connector {</div><div class='add'>+			compatible = "usb-c-connector";</div><div class='add'>+			label = "USB-C";</div><div class='add'>+			power-role = "dual";</div><div class='add'>+			data-role = "dual";</div><div class='add'>+			try-power-role = "sink";</div><div class='add'>+			source-pdos = &lt;PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)&gt;;</div><div class='add'>+			sink-pdos = &lt;PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)</div><div class='add'>+				     PDO_VAR(5000, 20000, 3000)&gt;;</div><div class='add'>+			op-sink-microwatt = &lt;15000000&gt;;</div><div class='add'>+			self-powered;</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					typec1_dr_sw: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;usb1_drd_sw&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rtc@53 {</div><div class='add'>+		compatible = "nxp,pcf2131";</div><div class='add'>+		reg = &lt;0x53&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;pcal6524&gt;;</div><div class='add'>+		interrupts = &lt;1 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	inertial-meter@6a {</div><div class='add'>+		compatible = "st,lsm6dso";</div><div class='add'>+		reg = &lt;0x6a&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pcal6524: gpio@22 {</div><div class='add'>+		compatible = "nxp,pcal6524";</div><div class='add'>+		reg = &lt;0x22&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+		interrupts = &lt;26 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pcal6524&gt;;</div><div class='add'>+</div><div class='add'>+		exp-sel-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;22 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mic-can-sel-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;17 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmic@25 {</div><div class='add'>+		compatible = "nxp,pca9451a";</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;pcal6524&gt;;</div><div class='add'>+		interrupts = &lt;11 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			buck1: BUCK1 {</div><div class='add'>+				regulator-name = "BUCK1";</div><div class='add'>+				regulator-min-microvolt = &lt;650000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2237500&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck2: BUCK2 {</div><div class='add'>+				regulator-name = "BUCK2";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2187500&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck4: BUCK4 {</div><div class='add'>+				regulator-name = "BUCK4";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck5: BUCK5 {</div><div class='add'>+				regulator-name = "BUCK5";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck6: BUCK6 {</div><div class='add'>+				regulator-name = "BUCK6";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo1: LDO1 {</div><div class='add'>+				regulator-name = "LDO1";</div><div class='add'>+				regulator-min-microvolt = &lt;1600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo4: LDO4 {</div><div class='add'>+				regulator-name = "LDO4";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo5: LDO5 {</div><div class='add'>+				regulator-name = "LDO5";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart1 { /* console */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart5 {</div><div class='add'>+	/* BT */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart5&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "nxp,88w8987-bt";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;micfil {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pdm&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX93_CLK_PDM&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX93_CLK_AUDIO_PLL&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;49152000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mu1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mu2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai1&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX93_CLK_SAI1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX93_CLK_AUDIO_PLL&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;12288000&gt;;</div><div class='add'>+	fsl,sai-mclk-direction-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai3&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX93_CLK_SAI3&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX93_CLK_AUDIO_PLL&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;12288000&gt;;</div><div class='add'>+	fsl,sai-mclk-direction-output;</div><div class='add'>+	fsl,sai-synchronous-rx;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	hnp-disable;</div><div class='add'>+	srp-disable;</div><div class='add'>+	adp-disable;</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	disable-over-current;</div><div class='add'>+	samsung,picophy-pre-emp-curr-control = &lt;3&gt;;</div><div class='add'>+	samsung,picophy-dc-vol-level-adjust = &lt;7&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	port {</div><div class='add'>+		usb1_drd_sw: endpoint {</div><div class='add'>+			remote-endpoint = &lt;&amp;typec1_dr_sw&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1_200mhz&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio3 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	no-mmc;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+	mmc-pwrseq = &lt;&amp;usdhc3_pwrseq&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc3_vmmc&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	keep-power-in-suspend;</div><div class='add'>+	non-removable;</div><div class='add'>+	wakeup-source;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_eqos: eqosgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_ENET1_MDC__ENET_QOS_MDC			0x57e</div><div class='add'>+			MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO			0x57e</div><div class='add'>+			MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0			0x57e</div><div class='add'>+			MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1			0x57e</div><div class='add'>+			MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2			0x57e</div><div class='add'>+			MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3			0x57e</div><div class='add'>+			MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x58e</div><div class='add'>+			MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x57e</div><div class='add'>+			MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0			0x57e</div><div class='add'>+			MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1			0x57e</div><div class='add'>+			MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2			0x57e</div><div class='add'>+			MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3			0x57e</div><div class='add'>+			MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x58e</div><div class='add'>+			MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x57e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c1: lpi2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_I2C1_SCL__LPI2C1_SCL		0x40000b9e</div><div class='add'>+			MX93_PAD_I2C1_SDA__LPI2C1_SDA		0x40000b9e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c2: lpi2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_I2C2_SCL__LPI2C2_SCL		0x40000b9e</div><div class='add'>+			MX93_PAD_I2C2_SDA__LPI2C2_SDA		0x40000b9e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcal6524: pcal6524grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_CCM_CLKO1__GPIO3_IO26		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pdm: pdmgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_PDM_CLK__PDM_CLK			0x31e</div><div class='add'>+			MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00	0x31e</div><div class='add'>+			MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01	0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_UART1_RXD__LPUART1_RX		0x31e</div><div class='add'>+			MX93_PAD_UART1_TXD__LPUART1_TX		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart5: uart5grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX	0x31e</div><div class='add'>+			MX93_PAD_DAP_TDI__LPUART5_RX		0x31e</div><div class='add'>+			MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B	0x31e</div><div class='add'>+			MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B	0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* need to config the SION for data and cmd pad, refer to ERR052021 */</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD1_CLK__USDHC1_CLK		0x1582</div><div class='add'>+			MX93_PAD_SD1_CMD__USDHC1_CMD		0x40001382</div><div class='add'>+			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x40001382</div><div class='add'>+			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x40001382</div><div class='add'>+			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x40001382</div><div class='add'>+			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x40001382</div><div class='add'>+			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x40001382</div><div class='add'>+			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x40001382</div><div class='add'>+			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x40001382</div><div class='add'>+			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x40001382</div><div class='add'>+			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x1582</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* need to config the SION for data and cmd pad, refer to ERR052021 */</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD1_CLK__USDHC1_CLK		0x158e</div><div class='add'>+			MX93_PAD_SD1_CMD__USDHC1_CMD		0x4000138e</div><div class='add'>+			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x4000138e</div><div class='add'>+			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x4000138e</div><div class='add'>+			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x4000138e</div><div class='add'>+			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x4000138e</div><div class='add'>+			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x4000138e</div><div class='add'>+			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x4000138e</div><div class='add'>+			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x4000138e</div><div class='add'>+			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x4000138e</div><div class='add'>+			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x158e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* need to config the SION for data and cmd pad, refer to ERR052021 */</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD1_CLK__USDHC1_CLK		0x15fe</div><div class='add'>+			MX93_PAD_SD1_CMD__USDHC1_CMD		0x400013fe</div><div class='add'>+			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x400013fe</div><div class='add'>+			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x400013fe</div><div class='add'>+			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x400013fe</div><div class='add'>+			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x400013fe</div><div class='add'>+			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x400013fe</div><div class='add'>+			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x400013fe</div><div class='add'>+			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x400013fe</div><div class='add'>+			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x400013fe</div><div class='add'>+			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x15fe</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD2_RESET_B__GPIO3_IO07	0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai1: sai1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SAI1_TXC__SAI1_TX_BCLK			0x31e</div><div class='add'>+			MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC		0x31e</div><div class='add'>+			MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00		0x31e</div><div class='add'>+			MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai3: sai3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_GPIO_IO12__SAI3_RX_SYNC		0x31e</div><div class='add'>+			MX93_PAD_GPIO_IO18__SAI3_RX_BCLK		0x31e</div><div class='add'>+			MX93_PAD_GPIO_IO17__SAI3_MCLK			0x31e</div><div class='add'>+			MX93_PAD_GPIO_IO19__SAI3_TX_DATA00		0x31e</div><div class='add'>+			MX93_PAD_GPIO_IO20__SAI3_RX_DATA00		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD2_CD_B__GPIO3_IO00		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* need to config the SION for data and cmd pad, refer to ERR052021 */</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD2_CLK__USDHC2_CLK		0x1582</div><div class='add'>+			MX93_PAD_SD2_CMD__USDHC2_CMD		0x40001382</div><div class='add'>+			MX93_PAD_SD2_DATA0__USDHC2_DATA0	0x40001382</div><div class='add'>+			MX93_PAD_SD2_DATA1__USDHC2_DATA1	0x40001382</div><div class='add'>+			MX93_PAD_SD2_DATA2__USDHC2_DATA2	0x40001382</div><div class='add'>+			MX93_PAD_SD2_DATA3__USDHC2_DATA3	0x40001382</div><div class='add'>+			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* need to config the SION for data and cmd pad, refer to ERR052021 */</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD2_CLK__USDHC2_CLK		0x158e</div><div class='add'>+			MX93_PAD_SD2_CMD__USDHC2_CMD		0x4000138e</div><div class='add'>+			MX93_PAD_SD2_DATA0__USDHC2_DATA0	0x4000138e</div><div class='add'>+			MX93_PAD_SD2_DATA1__USDHC2_DATA1	0x4000138e</div><div class='add'>+			MX93_PAD_SD2_DATA2__USDHC2_DATA2	0x4000138e</div><div class='add'>+			MX93_PAD_SD2_DATA3__USDHC2_DATA3	0x4000138e</div><div class='add'>+			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* need to config the SION for data and cmd pad, refer to ERR052021 */</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD2_CLK__USDHC2_CLK		0x15fe</div><div class='add'>+			MX93_PAD_SD2_CMD__USDHC2_CMD		0x400013fe</div><div class='add'>+			MX93_PAD_SD2_DATA0__USDHC2_DATA0	0x400013fe</div><div class='add'>+			MX93_PAD_SD2_DATA1__USDHC2_DATA1	0x400013fe</div><div class='add'>+			MX93_PAD_SD2_DATA2__USDHC2_DATA2	0x400013fe</div><div class='add'>+			MX93_PAD_SD2_DATA3__USDHC2_DATA3	0x400013fe</div><div class='add'>+			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* need to config the SION for data and cmd pad, refer to ERR052021 */</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD3_CLK__USDHC3_CLK		0x1582</div><div class='add'>+			MX93_PAD_SD3_CMD__USDHC3_CMD		0x40001382</div><div class='add'>+			MX93_PAD_SD3_DATA0__USDHC3_DATA0	0x40001382</div><div class='add'>+			MX93_PAD_SD3_DATA1__USDHC3_DATA1	0x40001382</div><div class='add'>+			MX93_PAD_SD3_DATA2__USDHC3_DATA2	0x40001382</div><div class='add'>+			MX93_PAD_SD3_DATA3__USDHC3_DATA3	0x40001382</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* need to config the SION for data and cmd pad, refer to ERR052021 */</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD3_CLK__USDHC3_CLK		0x158e</div><div class='add'>+			MX93_PAD_SD3_CMD__USDHC3_CMD		0x4000138e</div><div class='add'>+			MX93_PAD_SD3_DATA0__USDHC3_DATA0	0x4000138e</div><div class='add'>+			MX93_PAD_SD3_DATA1__USDHC3_DATA1	0x4000138e</div><div class='add'>+			MX93_PAD_SD3_DATA2__USDHC3_DATA2	0x4000138e</div><div class='add'>+			MX93_PAD_SD3_DATA3__USDHC3_DATA3	0x4000138e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* need to config the SION for data and cmd pad, refer to ERR052021 */</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD3_CLK__USDHC3_CLK		0x15fe</div><div class='add'>+			MX93_PAD_SD3_CMD__USDHC3_CMD		0x400013fe</div><div class='add'>+			MX93_PAD_SD3_DATA0__USDHC3_DATA0	0x400013fe</div><div class='add'>+			MX93_PAD_SD3_DATA1__USDHC3_DATA1	0x400013fe</div><div class='add'>+			MX93_PAD_SD3_DATA2__USDHC3_DATA2	0x400013fe</div><div class='add'>+			MX93_PAD_SD3_DATA3__USDHC3_DATA3	0x400013fe</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY	0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx93-kontron-bl-osm-s.dts b/arch/arm64/boot/dts/freescale/imx93-kontron-bl-osm-s.dts<br/>new file mode 100644<br/>index 000000000000..4620c070f4d7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx93-kontron-bl-osm-s.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx93-kontron-bl-osm-s.dts</a></div><div class='hunk'>@@ -0,0 +1,194 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2024 Kontron Electronics GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx93-kontron-osm-s.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Kontron BL i.MX93 OSM-S";</div><div class='add'>+	compatible = "kontron,imx93-bl-osm-s", "kontron,imx93-osm-s", "fsl,imx93";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;fec;</div><div class='add'>+		ethernet1 = &amp;eqos;</div><div class='add'>+		gpio0 = &amp;gpio1;</div><div class='add'>+		gpio1 = &amp;gpio2;</div><div class='add'>+		i2c0 = &amp;lpi2c1;</div><div class='add'>+		i2c1 = &amp;lpi2c2;</div><div class='add'>+		mmc0 = &amp;usdhc1;</div><div class='add'>+		mmc1 = &amp;usdhc2;</div><div class='add'>+		serial0 = &amp;lpuart1;</div><div class='add'>+		serial1 = &amp;lpuart2;</div><div class='add'>+		serial2 = &amp;lpuart3;</div><div class='add'>+		serial3 = &amp;lpuart4;</div><div class='add'>+		serial4 = &amp;lpuart5;</div><div class='add'>+		serial5 = &amp;lpuart6;</div><div class='add'>+		serial6 = &amp;lpuart7;</div><div class='add'>+		spi0 = &amp;lpspi1;</div><div class='add'>+		spi1 = &amp;lpspi2;</div><div class='add'>+		spi2 = &amp;lpspi3;</div><div class='add'>+		spi3 = &amp;lpspi4;</div><div class='add'>+		spi4 = &amp;lpspi5;</div><div class='add'>+		spi5 = &amp;lpspi6;</div><div class='add'>+		spi6 = &amp;lpspi7;</div><div class='add'>+		spi7 = &amp;lpspi8;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led1 {</div><div class='add'>+			label = "led1";</div><div class='add'>+			gpios = &lt;&amp;gpio2 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pwm-beeper {</div><div class='add'>+		compatible = "pwm-beeper";</div><div class='add'>+		pwms = &lt;&amp;tpm6 1 5000 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc_panel: regulator-vcc-panel {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_vcc_panel&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio2 21 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "VCC_PANEL";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eqos { /* Second ethernet (OSM-S ETH_B) */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_eqos_rgmii&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy1: ethernet-phy@1 {</div><div class='add'>+			compatible = "ethernet-phy-id4f51.e91b";</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			reset-assert-us = &lt;10000&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio1 10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec { /* First ethernet (OSM-S ETH_A) */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_enet_rgmii&gt;;</div><div class='add'>+	phy-connection-type = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@1 {</div><div class='add'>+			compatible = "ethernet-phy-id4f51.e91b";</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			reset-assert-us = &lt;10000&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio2 18 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	gpio_expander_dio: gpio@20 {</div><div class='add'>+		compatible = "ti,tca6408";</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-line-names = "DIO1_OUT","DIO1_IN", "DIO2_OUT","DIO2_IN",</div><div class='add'>+				  "DIO3_OUT","DIO3_IN", "DIO4_OUT","DIO4_IN";</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;28 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio2 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpspi8 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX93_CLK_LPSPI8&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX93_CLK_SYS_PLL_PFD0_DIV2&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;100000000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	eeram@0 {</div><div class='add'>+		compatible = "microchip,48l640";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;20000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart7 {</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart6 {</div><div class='add'>+	linux,rs485-enabled-at-boot-time;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tpm6 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	adp-disable;</div><div class='add'>+	hnp-disable;</div><div class='add'>+	srp-disable;</div><div class='add'>+	disable-over-current;</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg2 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	disable-over-current;</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	usb1@1 {</div><div class='add'>+		compatible = "usb424,2514";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_vdd_3v3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_reg_vcc_panel: regvccpanelgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_GPIO_IO21__GPIO2_IO21		0x31e /* PWM_2 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi b/arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi<br/>new file mode 100644<br/>index 000000000000..c79b1df339db<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi</a></div><div class='hunk'>@@ -0,0 +1,636 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2024 Kontron Electronics GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include "imx93.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Kontron OSM-S i.MX93";</div><div class='add'>+	compatible = "kontron,imx93-osm-s", "fsl,imx93";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		rtc0 = &amp;rv3028;</div><div class='add'>+		rtc1 = &amp;bbnsm_rtc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x40000000 0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;lpuart1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vcc: regulator-usdhc2-vcc {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usdhc2_vcc&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio3 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "VCC_SDIO_A";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vdd_carrier: regulator-vdd-carrier {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_vdd_carrier&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio4 29 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-name = "VDD_CARRIER";</div><div class='add'>+</div><div class='add'>+		regulator-state-standby {</div><div class='add'>+			regulator-on-in-suspend;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		regulator-state-mem {</div><div class='add'>+			regulator-off-in-suspend;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		regulator-state-disk {</div><div class='add'>+			regulator-off-in-suspend;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan1 { /* OSM-S CAN_A */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan2 { /* OSM-S CAN_B */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio1&gt;;</div><div class='add'>+	gpio-line-names = "", "", "I2C_A_SCL", "I2C_A_SDA",</div><div class='add'>+			  "UART_CON_RX", "UART_CON_TX", "UART_C_RX", "UART_C_TX",</div><div class='add'>+			  "CAN_A_TX", "CAN_A_RX", "GPIO_A_0", "SPI_A_CS0",</div><div class='add'>+			  "SPI_A_SDI", "SPI_A_SCK","SPI_A_SDO";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio2&gt;;</div><div class='add'>+	gpio-line-names = "I2C_B_SDA", "I2C_B_SCL", "GPIO_B_1", "GPIO_A_2",</div><div class='add'>+			  "UART_B_TX", "UART_B_RX", "UART_B_RTS", "UART_B_CTS",</div><div class='add'>+			  "UART_A_TX", "UART_A_RX", "UART_A_RTS", "UART_A_CTS",</div><div class='add'>+			  "SPI_B_CS0", "SPI_B_SDI", "SPI_B_SDO", "SPI_B_SCK",</div><div class='add'>+			  "I2S_BITCLK", "I2S_MCLK", "GPIO_A_1", "I2S_A_DATA_OUT",</div><div class='add'>+			  "I2S_A_DATA_IN", "PWM_2", "GPIO_A_3", "PWM_1",</div><div class='add'>+			  "PWM_0", "CAN_B_TX", "I2S_LRCLK", "CAN_B_RX", "GPIO_A_4",</div><div class='add'>+			  "GPIO_A_5";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio3&gt;;</div><div class='add'>+	gpio-line-names = "SDIO_A_CD", "SDIO_A_CLK", "SDIO_A_CMD", "SDIO_A_D0",</div><div class='add'>+			  "SDIO_A_D1", "SDIO_A_D2", "SDIO_A_D3", "SDIO_A_PWR_EN",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "SDIO_B_CLK", "SDIO_B_CMD", "SDIO_B_D0", "SDIO_B_D1",</div><div class='add'>+			  "SDIO_B_D2", "SDIO_B_D3", "GPIO_A_6", "GPIO_A_7";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio4&gt;;</div><div class='add'>+	gpio-line-names = "ETH_B_MDC", "ETH_B_MDIO", "ETH_B_TXD4", "ETH_B_TXD3",</div><div class='add'>+			  "ETH_B_TXD2", "ETH_B_TXD1", "ETH_B_TX_EN", "ETH_B_TX_CLK",</div><div class='add'>+			  "ETH_B_RX_CTL", "ETH_B_RX_CLK", "ETH_B_RXD0", "ETH_B_RXD1",</div><div class='add'>+			  "ETH_B_RXD2", "ETH_B_RXD3", "ETH_MDC", "ETH_MDIO",</div><div class='add'>+			  "ETH_A_TXD3", "ETH_A_TXD2", "ETH_A_TXD1", "ETH_A_TXD0",</div><div class='add'>+			  "ETH_A_TX_EN", "ETH_A_TX_CLK", "ETH_A_RX_CTL", "ETH_A_RX_CLK",</div><div class='add'>+			  "ETH_A_RXD0", "ETH_A_RXD1", "ETH_A_RXD2", "ETH_A_RXD3",</div><div class='add'>+			  "GPIO_B_0", "CARRIER_PWR_EN";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pca9451: pmic@25 {</div><div class='add'>+		compatible = "nxp,pca9451a";</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+		nxp,i2c-lt-enable;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			reg_vdd_soc: BUCK1 { /* dual phase with BUCK3 */</div><div class='add'>+				regulator-name = "+0V8_VDD_SOC (BUCK1)";</div><div class='add'>+				regulator-min-microvolt = &lt;650000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;950000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vddq_ddr: BUCK2 {</div><div class='add'>+				regulator-name = "+0V6_VDDQ_DDR (BUCK2)";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vdd_3v3: BUCK4 {</div><div class='add'>+				regulator-name = "+3V3 (BUCK4)";</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vdd_1v8: BUCK5 {</div><div class='add'>+				regulator-name = "+1V8 (BUCK5)";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_nvcc_dram: BUCK6 {</div><div class='add'>+				regulator-name = "+1V1_NVCC_DRAM (BUCK6)";</div><div class='add'>+				regulator-min-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_nvcc_snvs: LDO1 {</div><div class='add'>+				regulator-name = "+1V8_NVCC_SNVS (LDO1)";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_vdd_ana: LDO4 {</div><div class='add'>+				regulator-name = "+0V8_VDD_ANA (LDO4)";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			reg_nvcc_sd: LDO5 {</div><div class='add'>+				regulator-name = "NVCC_SD (LDO5)";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				nxp,sd-vsel-fixed-low;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@50 {</div><div class='add'>+		compatible = "onnn,n24s64b", "atmel,24c64";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		size = &lt;8192&gt;;</div><div class='add'>+		num-addresses = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rv3028: rtc@52 {</div><div class='add'>+		compatible = "microcrystal,rv3028";</div><div class='add'>+		reg = &lt;0x52&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_rtc&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;gpio3 19 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c2 { /* OSM-S I2C_A */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c3 { /* OSM-S I2C_B */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpspi1 { /* OSM-S SPI_A */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpspi1&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio1 11 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpspi8 { /* OSM-S SPI_B */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpspi8&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart1 { /* OSM-S UART_CON */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpuart1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart2 { /* OSM-S UART_C */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpuart2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart6 { /* OSM-S UART_B */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpuart6&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart7 { /* OSM-S UART_A */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpuart7&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tpm3 { /* OSM-S PWM_0 */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_tpm3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tpm4 { /* OSM-S PWM_2 */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_tpm4&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tpm6 { /* OSM-S PWM_1 */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_tpm6&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc1 { /* eMMC */</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1_200mhz&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_vdd_3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_vdd_1v8&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 { /* OSM-S SDIO_A */</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vcc&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_nvcc_sd&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio3 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc3 { /* OSM-S SDIO_B */</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_vdd_1v8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_enet_rgmii: enetrgmiigrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_ENET2_MDC__ENET1_MDC			0x57e /* ETH_MDC */</div><div class='add'>+			MX93_PAD_ENET2_MDIO__ENET1_MDIO			0x57e /* ETH_MDIO */</div><div class='add'>+			MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0		0x57e /* ETH_A_(S)(R)(G)MII_RXD0 */</div><div class='add'>+			MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1		0x57e /* ETH_A_(S)(R)(G)MII_RXD1 */</div><div class='add'>+			MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2		0x57e /* ETH_A_(R)(G)MII_RXD2 */</div><div class='add'>+			MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3		0x57e /* ETH_A_(R)(G)MII_RXD3 */</div><div class='add'>+			MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC		0x5fe /* ETH_A_(R)(G)MII_RX_CLK */</div><div class='add'>+			MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL	0x57e /* ETH_A_(R)(G)MII_RX_DV(_ER) */</div><div class='add'>+			MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0		0x57e /* ETH_A_(S)(R)(G)MII_TXD0 */</div><div class='add'>+			MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1		0x57e /* ETH_A_(S)(R)(G)MII_TXD1 */</div><div class='add'>+			MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2		0x57e /* ETH_A_(S)(R)(G)MII_TXD2 */</div><div class='add'>+			MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3		0x57e /* ETH_A_(S)(R)(G)MII_TXD3 */</div><div class='add'>+			MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC		0x5fe /* ETH_A_(R)(G)MII_TX_CLK */</div><div class='add'>+			MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL	0x57e /* ETH_A_(R)(G)MII_TX_EN(_ER) */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_eqos_rgmii: eqosrgmiigrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_ENET1_MDC__ENET_QOS_MDC		0x57e /* ETH_B_MDC */</div><div class='add'>+			MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO		0x57e /* ETH_B_MDIO */</div><div class='add'>+			MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0		0x57e /* ETH_B_(S)(R)(G)MII_RXD0 */</div><div class='add'>+			MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1		0x57e /* ETH_B_(S)(R)(G)MII_RXD1 */</div><div class='add'>+			MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2		0x57e /* ETH_B_(R)(G)MII_RXD2 */</div><div class='add'>+			MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3		0x57e /* ETH_B_(R)(G)MII_RXD3 */</div><div class='add'>+			MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x57e /* ETH_B_(R)(G)MII_RX_CLK */</div><div class='add'>+			MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL	0x57e /* ETH_B_(R)(G)MII_RX_DV(_ER) */</div><div class='add'>+			MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0		0x57e /* ETH_B_(S)(R)(G)MII_TXD0 */</div><div class='add'>+			MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1		0x57e /* ETH_B_(S)(R)(G)MII_TXD1 */</div><div class='add'>+			MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2		0x57e /* ETH_B_(S)(R)(G)MII_TXD2 */</div><div class='add'>+			MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3		0x57e /* ETH_B_(S)(R)(G)MII_TXD3 */</div><div class='add'>+			MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x57e /* ETH_B_(R)(G)MII_TX_CLK */</div><div class='add'>+			MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL	0x57e /* ETH_B_(R)(G)MII_TX_EN(_ER) */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan1: flexcan1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_PDM_CLK__CAN1_TX			0x139e /* CAN_A_TX */</div><div class='add'>+			MX93_PAD_PDM_BIT_STREAM0__CAN1_RX		0x139e /* CAN_A_RX */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan2: flexcan2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_GPIO_IO25__CAN2_TX			0x139e /* CAN_B_TX */</div><div class='add'>+			MX93_PAD_GPIO_IO27__CAN2_RX			0x139e /* CAN_B_RX */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio1: gpio1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10		0x31e /* GPIO_A_0 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio2: gpio2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_GPIO_IO18__GPIO2_IO18			0x31e /* GPIO_A_1 */</div><div class='add'>+			MX93_PAD_GPIO_IO03__GPIO2_IO03			0x31e /* GPIO_A_2 */</div><div class='add'>+			MX93_PAD_GPIO_IO22__GPIO2_IO22			0x31e /* GPIO_A_3 */</div><div class='add'>+			MX93_PAD_GPIO_IO28__GPIO2_IO28			0x31e /* GPIO_A_4 */</div><div class='add'>+			MX93_PAD_GPIO_IO29__GPIO2_IO29			0x31e /* GPIO_A_5 */</div><div class='add'>+			MX93_PAD_GPIO_IO02__GPIO2_IO02			0x31e /* GPIO_B_1 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio3: gpio3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_CCM_CLKO1__GPIO3_IO26			0x31e /* GPIO_A_6 */</div><div class='add'>+			MX93_PAD_CCM_CLKO2__GPIO3_IO27			0x31e /* GPIO_A_7 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio4: gpio4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_CCM_CLKO3__GPIO4_IO28			0x31e /* GPIO_B_0 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c1: lpi2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_I2C1_SCL__LPI2C1_SCL			0x40000b9e</div><div class='add'>+			MX93_PAD_I2C1_SDA__LPI2C1_SDA			0x40000b9e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c2: lpi2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_I2C2_SCL__LPI2C2_SCL			0x40000b9e /* I2C_A_SCL */</div><div class='add'>+			MX93_PAD_I2C2_SDA__LPI2C2_SDA			0x40000b9e /* I2C_A_SDA */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c3: lpi2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_GPIO_IO01__LPI2C3_SCL			0x40000b9e /* I2C_B_SCL */</div><div class='add'>+			MX93_PAD_GPIO_IO00__LPI2C3_SDA			0x40000b9e /* I2C_B_SDA */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpspi1: lpspi1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SAI1_TXC__LPSPI1_SIN			0x3fe /* SPI_A_SDI_(IO0) */</div><div class='add'>+			MX93_PAD_SAI1_RXD0__LPSPI1_SOUT			0x3fe /* SPI_A_SDO_(IO1) */</div><div class='add'>+			MX93_PAD_SAI1_TXD0__LPSPI1_SCK			0x3fe /* SPI_A_SCK */</div><div class='add'>+			MX93_PAD_SAI1_TXFS__GPIO1_IO11			0x3fe /* SPI_A_CS0# */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpspi8: lpspi8grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_GPIO_IO13__LPSPI8_SIN			0x3fe /* SPI_B_SDI */</div><div class='add'>+			MX93_PAD_GPIO_IO14__LPSPI8_SOUT			0x3fe /* SPI_B_SDO */</div><div class='add'>+			MX93_PAD_GPIO_IO15__LPSPI8_SCK			0x3fe /* SPI_B_SCK */</div><div class='add'>+			MX93_PAD_GPIO_IO12__GPIO2_IO12			0x3fe /* SPI_B_CS0# */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpuart1: lpuart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_UART1_RXD__LPUART1_RX			0x31e /* UART_CON_RX */</div><div class='add'>+			MX93_PAD_UART1_TXD__LPUART1_TX			0x31e /* UART_CON_TX */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpuart2: lpuart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_UART2_RXD__LPUART2_RX			0x31e /* UART_C_RX */</div><div class='add'>+			MX93_PAD_UART2_TXD__LPUART2_TX			0x31e /* UART_C_TX */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpuart6: lpuart6grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_GPIO_IO05__LPUART6_RX			0x31e /* UART_B_RX */</div><div class='add'>+			MX93_PAD_GPIO_IO04__LPUART6_TX			0x31e /* UART_B_TX */</div><div class='add'>+			MX93_PAD_GPIO_IO07__LPUART6_RTS_B		0x31e /* UART_B_CTS */</div><div class='add'>+			MX93_PAD_GPIO_IO06__LPUART6_CTS_B		0x31e /* UART_B_RTS */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpuart7: lpuart7grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_GPIO_IO09__LPUART7_RX			0x31e /* UART_A_RX */</div><div class='add'>+			MX93_PAD_GPIO_IO08__LPUART7_TX			0x31e /* UART_A_TX */</div><div class='add'>+			MX93_PAD_GPIO_IO11__LPUART7_RTS_B		0x31e /* UART_A_CTS */</div><div class='add'>+			MX93_PAD_GPIO_IO10__LPUART7_CTS_B		0x31e /* UART_A_RTS */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usdhc2_vcc: regusdhc2vccgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD2_RESET_B__GPIO3_IO07		0x31e /* SDIO_A_PWR_EN */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_vdd_carrier: regvddcarriergrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_CCM_CLKO4__GPIO4_IO29			0x31e /* CARRIER_PWR_EN */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_rtc: rtcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD2_VSELECT__GPIO3_IO19		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai3: sai3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_GPIO_IO20__SAI3_RX_DATA00		0x31e /* I2S_A_DATA_IN */</div><div class='add'>+			MX93_PAD_GPIO_IO19__SAI3_TX_DATA00		0x31e /* I2S_A_DATA_OUT */</div><div class='add'>+			MX93_PAD_GPIO_IO17__SAI3_MCLK			0x31e /* I2S_MCLK */</div><div class='add'>+			MX93_PAD_GPIO_IO26__SAI3_TX_SYNC		0x31e /* I2S_LRCLK */</div><div class='add'>+			MX93_PAD_GPIO_IO16__SAI3_TX_BCLK		0x31e /* I2S_BITCLK */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_tpm3: tpm3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_GPIO_IO24__TPM3_CH3			0x57e /* PWM_0 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_tpm4: tpm4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_GPIO_IO21__TPM4_CH1			0x57e /* PWM_2 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_tpm6: tpm6grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_GPIO_IO23__TPM6_CH1			0x57e /* PWM_1 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* need to config the SION for data and cmd pad, refer to ERR052021 */</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD1_CLK__USDHC1_CLK		0x1582</div><div class='add'>+			MX93_PAD_SD1_CMD__USDHC1_CMD		0x40001382</div><div class='add'>+			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x40001382</div><div class='add'>+			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x40001382</div><div class='add'>+			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x40001382</div><div class='add'>+			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x40001382</div><div class='add'>+			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x40001382</div><div class='add'>+			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x40001382</div><div class='add'>+			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x40001382</div><div class='add'>+			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x40001382</div><div class='add'>+			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x1582</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* need to config the SION for data and cmd pad, refer to ERR052021 */</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD1_CLK__USDHC1_CLK		0x158e</div><div class='add'>+			MX93_PAD_SD1_CMD__USDHC1_CMD		0x4000138e</div><div class='add'>+			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x4000138e</div><div class='add'>+			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x4000138e</div><div class='add'>+			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x4000138e</div><div class='add'>+			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x4000138e</div><div class='add'>+			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x4000138e</div><div class='add'>+			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x4000138e</div><div class='add'>+			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x4000138e</div><div class='add'>+			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x4000138e</div><div class='add'>+			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x158e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* need to config the SION for data and cmd pad, refer to ERR052021 */</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD1_CLK__USDHC1_CLK		0x15fe</div><div class='add'>+			MX93_PAD_SD1_CMD__USDHC1_CMD		0x400013fe</div><div class='add'>+			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x400013fe</div><div class='add'>+			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x400013fe</div><div class='add'>+			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x400013fe</div><div class='add'>+			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x400013fe</div><div class='add'>+			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x400013fe</div><div class='add'>+			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x400013fe</div><div class='add'>+			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x400013fe</div><div class='add'>+			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x400013fe</div><div class='add'>+			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x15fe</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD2_CLK__USDHC2_CLK			0x1582 /* SDIO_A_CLK */</div><div class='add'>+			MX93_PAD_SD2_CMD__USDHC2_CMD			0x40001382 /* SDIO_A_CMD */</div><div class='add'>+			MX93_PAD_SD2_DATA0__USDHC2_DATA0		0x40001382 /* SDIO_A_D0 */</div><div class='add'>+			MX93_PAD_SD2_DATA1__USDHC2_DATA1		0x40001382 /* SDIO_A_D1 */</div><div class='add'>+			MX93_PAD_SD2_DATA2__USDHC2_DATA2		0x40001382 /* SDIO_A_D2 */</div><div class='add'>+			MX93_PAD_SD2_DATA3__USDHC2_DATA3		0x40001382 /* SDIO_A_D3 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD2_CLK__USDHC2_CLK			0x158e /* SDIO_A_CLK */</div><div class='add'>+			MX93_PAD_SD2_CMD__USDHC2_CMD			0x4000138e /* SDIO_A_CMD */</div><div class='add'>+			MX93_PAD_SD2_DATA0__USDHC2_DATA0		0x4000138e /* SDIO_A_D0 */</div><div class='add'>+			MX93_PAD_SD2_DATA1__USDHC2_DATA1		0x4000138e /* SDIO_A_D1 */</div><div class='add'>+			MX93_PAD_SD2_DATA2__USDHC2_DATA2		0x4000138e /* SDIO_A_D2 */</div><div class='add'>+			MX93_PAD_SD2_DATA3__USDHC2_DATA3		0x4000138e /* SDIO_A_D3 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD2_CLK__USDHC2_CLK			0x15fe /* SDIO_A_CLK */</div><div class='add'>+			MX93_PAD_SD2_CMD__USDHC2_CMD			0x400013fe /* SDIO_A_CMD */</div><div class='add'>+			MX93_PAD_SD2_DATA0__USDHC2_DATA0		0x400013fe /* SDIO_A_D0 */</div><div class='add'>+			MX93_PAD_SD2_DATA1__USDHC2_DATA1		0x400013fe /* SDIO_A_D1 */</div><div class='add'>+			MX93_PAD_SD2_DATA2__USDHC2_DATA2		0x400013fe /* SDIO_A_D2 */</div><div class='add'>+			MX93_PAD_SD2_DATA3__USDHC2_DATA3		0x400013fe /* SDIO_A_D3 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD2_CD_B__GPIO3_IO00			0x31e /* SDIO_A_CD# */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD3_CLK__USDHC3_CLK			0x1582 /* SDIO_B_CLK */</div><div class='add'>+			MX93_PAD_SD3_CMD__USDHC3_CMD			0x40001382 /* SDIO_B_CMD */</div><div class='add'>+			MX93_PAD_SD3_DATA0__USDHC3_DATA0		0x40001382 /* SDIO_B_D0 */</div><div class='add'>+			MX93_PAD_SD3_DATA1__USDHC3_DATA1		0x40001382 /* SDIO_B_D1 */</div><div class='add'>+			MX93_PAD_SD3_DATA2__USDHC3_DATA2		0x40001382 /* SDIO_B_D2 */</div><div class='add'>+			MX93_PAD_SD3_DATA3__USDHC3_DATA3		0x40001382 /* SDIO_B_D3 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD3_CLK__USDHC3_CLK			0x158e /* SDIO_B_CLK */</div><div class='add'>+			MX93_PAD_SD3_CMD__USDHC3_CMD			0x4000138e /* SDIO_B_CMD */</div><div class='add'>+			MX93_PAD_SD3_DATA0__USDHC3_DATA0		0x4000138e /* SDIO_B_D0 */</div><div class='add'>+			MX93_PAD_SD3_DATA1__USDHC3_DATA1		0x4000138e /* SDIO_B_D1 */</div><div class='add'>+			MX93_PAD_SD3_DATA2__USDHC3_DATA2		0x4000138e /* SDIO_B_D2 */</div><div class='add'>+			MX93_PAD_SD3_DATA3__USDHC3_DATA3		0x4000138e /* SDIO_B_D3 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD3_CLK__USDHC3_CLK			0x15fe /* SDIO_B_CLK */</div><div class='add'>+			MX93_PAD_SD3_CMD__USDHC3_CMD			0x400013fe /* SDIO_B_CMD */</div><div class='add'>+			MX93_PAD_SD3_DATA0__USDHC3_DATA0		0x400013fe /* SDIO_B_D0 */</div><div class='add'>+			MX93_PAD_SD3_DATA1__USDHC3_DATA1		0x400013fe /* SDIO_B_D1 */</div><div class='add'>+			MX93_PAD_SD3_DATA2__USDHC3_DATA2		0x400013fe /* SDIO_B_D2 */</div><div class='add'>+			MX93_PAD_SD3_DATA3__USDHC3_DATA3		0x400013fe /* SDIO_B_D3 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY		0xc6</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-nash-jtag.dtso b/arch/arm64/boot/dts/freescale/imx93-phyboard-nash-jtag.dtso<br/>new file mode 100644<br/>index 000000000000..89f93dca3208<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx93-phyboard-nash-jtag.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx93-phyboard-nash-jtag.dtso</a></div><div class='hunk'>@@ -0,0 +1,31 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2025 PHYTEC Messtechnik GmbH</div><div class='add'>+ * Author: Primoz Fiser &lt;primoz.fiser@norik.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "imx93-pinfunc.h"</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * NOTE: Bind pinctrl_jtag to gpio2 so that the pinctrl settings are applied.</div><div class='add'>+ * JTAG itself has no dedicated driver, so without attaching it to an active</div><div class='add'>+ * device node (like gpio2), the pinmux configuration would not take effect.</div><div class='add'>+ */</div><div class='add'>+&amp;gpio2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_jtag&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_jtag: jtaggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_GPIO_IO24__JTAG_MUX_TDO	0x31e</div><div class='add'>+			MX93_PAD_GPIO_IO25__JTAG_MUX_TCK	0x31e</div><div class='add'>+			MX93_PAD_GPIO_IO26__JTAG_MUX_TDI	0x31e</div><div class='add'>+			MX93_PAD_GPIO_IO27__JTAG_MUX_TMS	0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-nash-peb-wlbt-07.dtso b/arch/arm64/boot/dts/freescale/imx93-phyboard-nash-peb-wlbt-07.dtso<br/>new file mode 100644<br/>index 000000000000..7381b87444e8<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx93-phyboard-nash-peb-wlbt-07.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx93-phyboard-nash-peb-wlbt-07.dtso</a></div><div class='hunk'>@@ -0,0 +1,88 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2025 PHYTEC Messtechnik GmbH</div><div class='add'>+ * Author: Primoz Fiser &lt;primoz.fiser@norik.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include "imx93-pinfunc.h"</div><div class='add'>+</div><div class='add'>+&amp;{/} {</div><div class='add'>+	usdhc3_pwrseq: usdhc3-pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-simple";</div><div class='add'>+		reset-gpios = &lt;&amp;gpio4 29 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart5 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart5&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "nxp,88w8987-bt";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * NOTE: When uSDHC3 port is multiplexed on GPIO_IO[27:22] pads, it only</div><div class='add'>+ * supports 50 MHz mode, due to introduction of potential variations in</div><div class='add'>+ * trace impedance, drive strength, and timing skew. Refer to i.MX 93</div><div class='add'>+ * Application Processors Data Sheet, Rev. 3, page 60 for more details.</div><div class='add'>+ */</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;, &lt;&amp;pinctrl_wlbt&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_sleep&gt;, &lt;&amp;pinctrl_wlbt&gt;;</div><div class='add'>+	mmc-pwrseq = &lt;&amp;usdhc3_pwrseq&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	keep-power-in-suspend;</div><div class='add'>+	non-removable;</div><div class='add'>+	wakeup-source;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_uart5: uart5grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX	0x31e</div><div class='add'>+			MX93_PAD_DAP_TDI__LPUART5_RX		0x31e</div><div class='add'>+			MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B	0x31e</div><div class='add'>+			MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B	0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* need to config the SION for data and cmd pad, refer to ERR052021 */</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_GPIO_IO22__USDHC3_CLK		0x179e</div><div class='add'>+			MX93_PAD_SD3_CMD__USDHC3_CMD 		0x4000178e</div><div class='add'>+			MX93_PAD_SD3_DATA0__USDHC3_DATA0	0x4000138e</div><div class='add'>+			MX93_PAD_SD3_DATA1__USDHC3_DATA1	0x4000138e</div><div class='add'>+			MX93_PAD_SD3_DATA2__USDHC3_DATA2	0x4000138e</div><div class='add'>+			MX93_PAD_SD3_DATA3__USDHC3_DATA3	0x4000138e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_sleep: usdhc3sleepgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_GPIO_IO22__USDHC3_CLK		0x31e</div><div class='add'>+			MX93_PAD_SD3_CMD__USDHC3_CMD 		0x31e</div><div class='add'>+			MX93_PAD_SD3_DATA0__USDHC3_DATA0	0x31e</div><div class='add'>+			MX93_PAD_SD3_DATA1__USDHC3_DATA1	0x31e</div><div class='add'>+			MX93_PAD_SD3_DATA2__USDHC3_DATA2	0x31e</div><div class='add'>+			MX93_PAD_SD3_DATA3__USDHC3_DATA3	0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wlbt: wlbtgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_CCM_CLKO2__GPIO3_IO27		0x31e	/* WAKE_DEV */</div><div class='add'>+			MX93_PAD_CCM_CLKO3__GPIO4_IO28		0x31e	/* WAKE_HOST */</div><div class='add'>+			MX93_PAD_CCM_CLKO4__GPIO4_IO29		0x31e	/* PDn */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-nash-pwm-fan.dtso b/arch/arm64/boot/dts/freescale/imx93-phyboard-nash-pwm-fan.dtso<br/>new file mode 100644<br/>index 000000000000..d1adf04d56d9<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx93-phyboard-nash-pwm-fan.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx93-phyboard-nash-pwm-fan.dtso</a></div><div class='hunk'>@@ -0,0 +1,75 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2025 PHYTEC Messtechnik GmbH</div><div class='add'>+ * Author: Primoz Fiser &lt;primoz.fiser@norik.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/pwm/pwm.h&gt;</div><div class='add'>+#include "imx93-pinfunc.h"</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+&amp;{/} {</div><div class='add'>+	fan0: pwm-fan {</div><div class='add'>+		compatible = "pwm-fan";</div><div class='add'>+		#cooling-cells = &lt;2&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_fan&gt;;</div><div class='add'>+		cooling-levels = &lt;1 90 150 200 255&gt;;</div><div class='add'>+		pwms = &lt;&amp;tpm6 1 40000 PWM_POLARITY_INVERTED&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	thermal-zones {</div><div class='add'>+		cpu-thermal {</div><div class='add'>+			trips {</div><div class='add'>+				cpu_low: cpu-low {</div><div class='add'>+					hysteresis = &lt;3000&gt;;</div><div class='add'>+					temperature = &lt;50000&gt;;</div><div class='add'>+					type = "active";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_med: cpu-med {</div><div class='add'>+					hysteresis = &lt;3000&gt;;</div><div class='add'>+					temperature = &lt;58000&gt;;</div><div class='add'>+					type = "active";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_high: cpu-high {</div><div class='add'>+					hysteresis = &lt;3000&gt;;</div><div class='add'>+					temperature = &lt;65000&gt;;</div><div class='add'>+					type = "active";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map1 {</div><div class='add'>+					cooling-device = &lt;&amp;fan0 1 1&gt;;</div><div class='add'>+					trip = &lt;&amp;cpu_low&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				map2 {</div><div class='add'>+					cooling-device = &lt;&amp;fan0 2 2&gt;;</div><div class='add'>+					trip = &lt;&amp;cpu_med&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				map3 {</div><div class='add'>+					cooling-device = &lt;&amp;fan0 4 4&gt;;</div><div class='add'>+					trip = &lt;&amp;cpu_high&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tpm6 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_fan: fangrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_GPIO_IO23__TPM6_CH1	0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts<br/>new file mode 100644<br/>index 000000000000..9e875e082ee8<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts</a></div><div class='hunk'>@@ -0,0 +1,367 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2025 PHYTEC Messtechnik GmbH</div><div class='add'>+ * Author: Primoz Fiser &lt;primoz.fiser@norik.com&gt;</div><div class='add'>+ *</div><div class='add'>+ * Product homepage:</div><div class='add'>+ * https://www.phytec.eu/en/produkte/development-kits/phyboard-nash/</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/net/ti-dp83867.h&gt;</div><div class='add'>+#include "imx93-phycore-som.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "PHYTEC phyBOARD-Nash-i.MX93";</div><div class='add'>+	compatible = "phytec,imx93-phyboard-nash", "phytec,imx93-phycore-som",</div><div class='add'>+		     "fsl,imx93";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet1 = &amp;eqos;</div><div class='add'>+		gpio0 = &amp;gpio1;</div><div class='add'>+		gpio1 = &amp;gpio2;</div><div class='add'>+		gpio2 = &amp;gpio3;</div><div class='add'>+		gpio3 = &amp;gpio4;</div><div class='add'>+		i2c0 = &amp;lpi2c1;</div><div class='add'>+		i2c1 = &amp;lpi2c2;</div><div class='add'>+		mmc0 = &amp;usdhc1;</div><div class='add'>+		mmc1 = &amp;usdhc2;</div><div class='add'>+		rtc0 = &amp;i2c_rtc;</div><div class='add'>+		rtc1 = &amp;bbnsm_rtc;</div><div class='add'>+		serial0 = &amp;lpuart1;</div><div class='add'>+		serial1 = &amp;lpuart2;</div><div class='add'>+		serial2 = &amp;lpuart3;</div><div class='add'>+		serial3 = &amp;lpuart4;</div><div class='add'>+		serial4 = &amp;lpuart5;</div><div class='add'>+		serial5 = &amp;lpuart6;</div><div class='add'>+		serial6 = &amp;lpuart7;</div><div class='add'>+		spi0 = &amp;lpspi1;</div><div class='add'>+		spi1 = &amp;lpspi2;</div><div class='add'>+		spi2 = &amp;lpspi3;</div><div class='add'>+		spi3 = &amp;lpspi4;</div><div class='add'>+		spi4 = &amp;lpspi5;</div><div class='add'>+		spi5 = &amp;lpspi6;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;lpuart1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	curr_sens: current-sense {</div><div class='add'>+		compatible = "current-sense-amplifier";</div><div class='add'>+		#io-channel-cells = &lt;0&gt;;</div><div class='add'>+		io-channels = &lt;&amp;adc1 1&gt;;</div><div class='add'>+		sense-gain-div = &lt;2&gt;;</div><div class='add'>+		sense-gain-mult = &lt;50&gt;;</div><div class='add'>+		sense-resistor-micro-ohms = &lt;35000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	flexcan1_tc: can-phy0 {</div><div class='add'>+		compatible = "ti,tcan1042";</div><div class='add'>+		#phy-cells = &lt;0&gt;;</div><div class='add'>+		max-bitrate = &lt;8000000&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_flexcan1_tc&gt;;</div><div class='add'>+		standby-gpios = &lt;&amp;gpio4 16 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	iio-hwmon {</div><div class='add'>+		compatible = "iio-hwmon";</div><div class='add'>+		io-channels = &lt;&amp;curr_sens 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb1_vbus: regulator-usb1-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "USB1_VBUS";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb2_vbus: regulator-usb2-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "USB2_VBUS";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		gpio = &lt;&amp;gpio3 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usdhc2_vmmc&gt;;</div><div class='add'>+		regulator-name = "VCC_SD";</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc_1v8: regulator-vcc-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCC1V8";</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* ADC */</div><div class='add'>+&amp;adc1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Ethernet */</div><div class='add'>+&amp;eqos {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_eqos&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdio {</div><div class='add'>+	ethphy2: ethernet-phy@2 {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+		reg = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+		interrupts = &lt;26 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		ti,clk-output-sel = &lt;DP83867_CLK_O_SEL_OFF&gt;;</div><div class='add'>+		ti,fifo-depth = &lt;DP83867_PHYCR_FIFO_DEPTH_4_B_NIB&gt;;</div><div class='add'>+		ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_1_75_NS&gt;;</div><div class='add'>+		ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_2_00_NS&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* CAN */</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan1&gt;;</div><div class='add'>+	phys = &lt;&amp;flexcan1_tc&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* I2C2 */</div><div class='add'>+&amp;lpi2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* RTC */</div><div class='add'>+	i2c_rtc: rtc@52 {</div><div class='add'>+		compatible = "microcrystal,rv3028";</div><div class='add'>+		reg = &lt;0x52&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;26 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_rtc&gt;;</div><div class='add'>+		trickle-resistor-ohms = &lt;3000&gt;;</div><div class='add'>+		wakeup-source;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* EEPROM */</div><div class='add'>+	eeprom@54 {</div><div class='add'>+		compatible = "atmel,24c32";</div><div class='add'>+		reg = &lt;0x54&gt;;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_vcc_1v8&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SPI6 */</div><div class='add'>+&amp;lpspi6 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpspi6&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio2 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* TPM */</div><div class='add'>+	tpm@0 {</div><div class='add'>+		compatible = "infineon,slb9670", "tcg,tpm_tis-spi";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio2&gt;;</div><div class='add'>+		interrupts = &lt;17 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_tpm&gt;;</div><div class='add'>+		spi-max-frequency = &lt;10000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Console */</div><div class='add'>+&amp;lpuart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* RS-232/RS-485 */</div><div class='add'>+&amp;lpuart7 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart7&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB */</div><div class='add'>+&amp;usbphynop1 {</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usb1_vbus&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbphynop2 {</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usb2_vbus&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	disable-over-current;</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg2 {</div><div class='add'>+	disable-over-current;</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SD-Card */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2_default&gt;, &lt;&amp;pinctrl_usdhc2_cd&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_cd&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_cd&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio3 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+	no-mmc;</div><div class='add'>+	no-sdio;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_eqos: eqosgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0	0x57e</div><div class='add'>+			MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1	0x57e</div><div class='add'>+			MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2	0x57e</div><div class='add'>+			MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3	0x57e</div><div class='add'>+			MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x5fe</div><div class='add'>+			MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL	0x57e</div><div class='add'>+			MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0	0x51e</div><div class='add'>+			MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1	0x51e</div><div class='add'>+			MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2	0x50e</div><div class='add'>+			MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3	0x50e</div><div class='add'>+			MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x58e</div><div class='add'>+			MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL	0x50e</div><div class='add'>+			MX93_PAD_CCM_CLKO1__GPIO3_IO26		0x1002</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan1: flexcan1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_PDM_BIT_STREAM0__CAN1_RX	0x139e</div><div class='add'>+			MX93_PAD_PDM_CLK__CAN1_TX		0x1382</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan1_tc: flexcan1tcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_ENET2_TD3__GPIO4_IO16		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c2: lpi2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_I2C2_SCL__LPI2C2_SCL		0x40000b9e</div><div class='add'>+			MX93_PAD_I2C2_SDA__LPI2C2_SDA		0x40000b9e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpspi6: lpspi6grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_GPIO_IO00__GPIO2_IO00		0x386</div><div class='add'>+			MX93_PAD_GPIO_IO01__LPSPI6_SIN		0x3fe</div><div class='add'>+			MX93_PAD_GPIO_IO02__LPSPI6_SOUT		0x386</div><div class='add'>+			MX93_PAD_GPIO_IO03__LPSPI6_SCK		0x386</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD2_RESET_B__GPIO3_IO07	0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_rtc: rtcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_ENET2_RD2__GPIO4_IO26		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_tpm: tpmgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_GPIO_IO17__GPIO2_IO17		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_UART1_RXD__LPUART1_RX		0x31e</div><div class='add'>+			MX93_PAD_UART1_TXD__LPUART1_TX		0x30e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart7: uart7grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_GPIO_IO08__LPUART7_TX		0x30e</div><div class='add'>+			MX93_PAD_GPIO_IO09__LPUART7_RX		0x31e</div><div class='add'>+			MX93_PAD_GPIO_IO10__LPUART7_CTS_B	0x31e</div><div class='add'>+			MX93_PAD_GPIO_IO11__LPUART7_RTS_B	0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_cd: usdhc2cdgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD2_CD_B__GPIO3_IO00		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* need to config the SION for data and cmd pad, refer to ERR052021 */</div><div class='add'>+	pinctrl_usdhc2_default: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD2_CLK__USDHC2_CLK		0x159e</div><div class='add'>+			MX93_PAD_SD2_CMD__USDHC2_CMD		0x4000178e</div><div class='add'>+			MX93_PAD_SD2_DATA0__USDHC2_DATA0	0x40001386</div><div class='add'>+			MX93_PAD_SD2_DATA1__USDHC2_DATA1	0x40001386</div><div class='add'>+			MX93_PAD_SD2_DATA2__USDHC2_DATA2	0x40001386</div><div class='add'>+			MX93_PAD_SD2_DATA3__USDHC2_DATA3	0x4000138e</div><div class='add'>+			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* need to config the SION for data and cmd pad, refer to ERR052021 */</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD2_CLK__USDHC2_CLK		0x159e</div><div class='add'>+			MX93_PAD_SD2_CMD__USDHC2_CMD		0x4000139e</div><div class='add'>+			MX93_PAD_SD2_DATA0__USDHC2_DATA0	0x4000139e</div><div class='add'>+			MX93_PAD_SD2_DATA1__USDHC2_DATA1	0x4000139e</div><div class='add'>+			MX93_PAD_SD2_DATA2__USDHC2_DATA2	0x4000139e</div><div class='add'>+			MX93_PAD_SD2_DATA3__USDHC2_DATA3	0x400013be</div><div class='add'>+			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* need to config the SION for data and cmd pad, refer to ERR052021 */</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD2_CLK__USDHC2_CLK		0x159e</div><div class='add'>+			MX93_PAD_SD2_CMD__USDHC2_CMD		0x4000139e</div><div class='add'>+			MX93_PAD_SD2_DATA0__USDHC2_DATA0	0x4000139e</div><div class='add'>+			MX93_PAD_SD2_DATA1__USDHC2_DATA1	0x4000139e</div><div class='add'>+			MX93_PAD_SD2_DATA2__USDHC2_DATA2	0x4000139e</div><div class='add'>+			MX93_PAD_SD2_DATA3__USDHC2_DATA3	0x4000139e</div><div class='add'>+			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin-peb-eval-01.dtso b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin-peb-eval-01.dtso<br/>new file mode 100644<br/>index 000000000000..a20898734741<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx93-phyboard-segin-peb-eval-01.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx93-phyboard-segin-peb-eval-01.dtso</a></div><div class='hunk'>@@ -0,0 +1,52 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2025 PHYTEC Messtechnik GmbH</div><div class='add'>+ * Author: Andrej Picej &lt;andrej.picej@norik.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include "imx93-pinfunc.h"</div><div class='add'>+</div><div class='add'>+&amp;{/} {</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio_keys&gt;;</div><div class='add'>+</div><div class='add'>+		button-s2 {</div><div class='add'>+			label = "sleep";</div><div class='add'>+			linux,code = &lt;KEY_SLEEP&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio1 10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	user-leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_user_leds&gt;;</div><div class='add'>+</div><div class='add'>+		user-led2 {</div><div class='add'>+			gpios = &lt;&amp;gpio4 13 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "on";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_gpio_keys: gpiokeysgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10	0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_user_leds: userledsgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_ENET1_RD3__GPIO4_IO13		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin-peb-wlbt-05.dtso b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin-peb-wlbt-05.dtso<br/>new file mode 100644<br/>index 000000000000..a7285f009566<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx93-phyboard-segin-peb-wlbt-05.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx93-phyboard-segin-peb-wlbt-05.dtso</a></div><div class='hunk'>@@ -0,0 +1,93 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2025 PHYTEC Messtechnik GmbH</div><div class='add'>+ * Author: Andrej Picej &lt;andrej.picej@norik.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include "imx93-pinfunc.h"</div><div class='add'>+</div><div class='add'>+&amp;{/} {</div><div class='add'>+	usdhc3_pwrseq: usdhc3-pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-simple";</div><div class='add'>+		post-power-on-delay-ms = &lt;100&gt;;</div><div class='add'>+		power-off-delay-us = &lt;60&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio4 7 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart5 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart5&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "brcm,bcm43438-bt";</div><div class='add'>+		shutdown-gpios = &lt;&amp;gpio4 13 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		host-wakeup-gpios = &lt;&amp;gpio1 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		max-speed = &lt;2000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;, &lt;&amp;pinctrl_wlbt&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_sleep&gt;, &lt;&amp;pinctrl_wlbt&gt;;</div><div class='add'>+	mmc-pwrseq = &lt;&amp;usdhc3_pwrseq&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	no-1-8-v;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	brmcf: wifi@1 {</div><div class='add'>+		compatible = "brcm,bcm4329-fmac";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_uart5: uart5grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX	0x31e</div><div class='add'>+			MX93_PAD_DAP_TDI__LPUART5_RX		0x31e</div><div class='add'>+			MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B	0x31e</div><div class='add'>+			MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B	0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* need to config the SION for data and cmd pad, refer to ERR052021 */</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_GPIO_IO22__USDHC3_CLK		0x179e</div><div class='add'>+			MX93_PAD_GPIO_IO23__USDHC3_CMD		0x4000139e</div><div class='add'>+			MX93_PAD_GPIO_IO24__USDHC3_DATA0	0x4000139e</div><div class='add'>+			MX93_PAD_GPIO_IO25__USDHC3_DATA1	0x4000139e</div><div class='add'>+			MX93_PAD_GPIO_IO26__USDHC3_DATA2	0x4000139e</div><div class='add'>+			MX93_PAD_GPIO_IO27__USDHC3_DATA3	0x4000139e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_sleep: usdhc3sleepgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_GPIO_IO22__USDHC3_CLK		0x31e</div><div class='add'>+			MX93_PAD_GPIO_IO23__USDHC3_CMD		0x31e</div><div class='add'>+			MX93_PAD_GPIO_IO24__USDHC3_DATA0	0x31e</div><div class='add'>+			MX93_PAD_GPIO_IO25__USDHC3_DATA1	0x31e</div><div class='add'>+			MX93_PAD_GPIO_IO26__USDHC3_DATA2	0x31e</div><div class='add'>+			MX93_PAD_GPIO_IO27__USDHC3_DATA3	0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wlbt: wlbtgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_ENET1_RD3__GPIO4_IO13		0x31e	/* BT ENABLE */</div><div class='add'>+			MX93_PAD_ENET1_TXC__GPIO4_IO07		0x31e	/* WLAN ENABLE */</div><div class='add'>+			MX93_PAD_I2C1_SCL__GPIO1_IO00		0x31e	/* HOST WAKEUP */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts<br/>new file mode 100644<br/>index 000000000000..ac64abacc4a2<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts</a></div><div class='hunk'>@@ -0,0 +1,338 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2023 PHYTEC Messtechnik GmbH</div><div class='add'>+ * Author: Wadim Egorov &lt;w.egorov@phytec.de&gt;, Christoph Stoidner &lt;c.stoidner@phytec.de&gt;</div><div class='add'>+ * Copyright (C) 2024 Mathieu Othacehe &lt;m.othacehe@gmail.com&gt;</div><div class='add'>+ *</div><div class='add'>+ * Product homepage:</div><div class='add'>+ * phyBOARD-Segin carrier board is reused for the i.MX93 design.</div><div class='add'>+ * https://www.phytec.eu/en/produkte/single-board-computer/phyboard-segin-imx6ul/</div><div class='add'>+ */</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx93-phycore-som.dtsi"</div><div class='add'>+</div><div class='add'>+/{</div><div class='add'>+	model = "PHYTEC phyBOARD-Segin-i.MX93";</div><div class='add'>+	compatible = "phytec,imx93-phyboard-segin", "phytec,imx93-phycore-som",</div><div class='add'>+		     "fsl,imx93";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet1 = &amp;eqos;</div><div class='add'>+		gpio0 = &amp;gpio1;</div><div class='add'>+		gpio1 = &amp;gpio2;</div><div class='add'>+		gpio2 = &amp;gpio3;</div><div class='add'>+		gpio3 = &amp;gpio4;</div><div class='add'>+		i2c0 = &amp;lpi2c1;</div><div class='add'>+		i2c1 = &amp;lpi2c2;</div><div class='add'>+		mmc0 = &amp;usdhc1;</div><div class='add'>+		mmc1 = &amp;usdhc2;</div><div class='add'>+		rtc0 = &amp;i2c_rtc;</div><div class='add'>+		rtc1 = &amp;bbnsm_rtc;</div><div class='add'>+		serial0 = &amp;lpuart1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;lpuart1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	flexcan1_tc: can-phy0 {</div><div class='add'>+		compatible = "ti,tcan1043";</div><div class='add'>+		#phy-cells = &lt;0&gt;;</div><div class='add'>+		max-bitrate = &lt;1000000&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_flexcan1_tc&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;gpio4 16 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_sound_1v8: regulator-sound-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-name = "VCC1V8_AUDIO";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_sound_3v3: regulator-sound-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "VCC3V3_ANALOG";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb_otg1_vbus: regulator-usb-otg1-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "USB_OTG1_VBUS";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb_otg2_vbus: regulator-usb-otg2-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "USB_OTG2_VBUS";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;gpio3 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usdhc2_vmmc&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "VCC_SD";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound: sound {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,name = "phyBOARD-Segin-TLV320AIC3007";</div><div class='add'>+		simple-audio-card,format = "i2s";</div><div class='add'>+		simple-audio-card,bitclock-master = &lt;&amp;dailink_master&gt;;</div><div class='add'>+		simple-audio-card,frame-master = &lt;&amp;dailink_master&gt;;</div><div class='add'>+		simple-audio-card,widgets =</div><div class='add'>+			"Line", "Line In",</div><div class='add'>+			"Line", "Line Out",</div><div class='add'>+			"Speaker", "Speaker";</div><div class='add'>+		simple-audio-card,routing =</div><div class='add'>+			"Line Out", "LLOUT",</div><div class='add'>+			"Line Out", "RLOUT",</div><div class='add'>+			"Speaker", "SPOP",</div><div class='add'>+			"Speaker", "SPOM",</div><div class='add'>+			"LINE1L", "Line In",</div><div class='add'>+			"LINE1R", "Line In";</div><div class='add'>+</div><div class='add'>+		simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;sai1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dailink_master: simple-audio-card,codec {</div><div class='add'>+			sound-dai = &lt;&amp;audio_codec&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk IMX93_CLK_SAI1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Ethernet */</div><div class='add'>+&amp;eqos {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_eqos&gt;;</div><div class='add'>+	phy-mode = "rmii";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy2&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX93_CLK_SYS_PLL_PFD1_DIV2&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX93_CLK_SYS_PLL_PFD1_DIV2&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;100000000&gt;, &lt;50000000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdio {</div><div class='add'>+	ethphy2: ethernet-phy@2 {</div><div class='add'>+		compatible = "ethernet-phy-id0022.1561";</div><div class='add'>+		reg = &lt;2&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX93_CLK_ENET_REF_PHY&gt;;</div><div class='add'>+		clock-names = "rmii-ref";</div><div class='add'>+		micrel,led-mode = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* CAN */</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan1&gt;;</div><div class='add'>+	phys = &lt;&amp;flexcan1_tc&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* I2C2 */</div><div class='add'>+&amp;lpi2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* Codec */</div><div class='add'>+	audio_codec: audio-codec@18 {</div><div class='add'>+		compatible = "ti,tlv320aic3007";</div><div class='add'>+		reg = &lt;0x18&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		AVDD-supply = &lt;&amp;reg_sound_3v3&gt;;</div><div class='add'>+		IOVDD-supply = &lt;&amp;reg_sound_3v3&gt;;</div><div class='add'>+		DRVDD-supply = &lt;&amp;reg_sound_3v3&gt;;</div><div class='add'>+		DVDD-supply = &lt;&amp;reg_sound_1v8&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* RTC */</div><div class='add'>+	i2c_rtc: rtc@68 {</div><div class='add'>+		compatible = "microcrystal,rv4162";</div><div class='add'>+		reg = &lt;0x68&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_rtc&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;26 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Console */</div><div class='add'>+&amp;lpuart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Audio */</div><div class='add'>+&amp;sai1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai1&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX93_CLK_SAI1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX93_CLK_AUDIO_PLL&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;19200000&gt;;</div><div class='add'>+	fsl,sai-mclk-direction-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB  */</div><div class='add'>+&amp;usbphynop1 {</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usb_otg1_vbus&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbphynop2 {</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usb_otg2_vbus&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	disable-over-current;</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg2 {</div><div class='add'>+	disable-over-current;</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SD-Card */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2_default&gt;, &lt;&amp;pinctrl_usdhc2_cd&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_cd&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_cd&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio3 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+	no-mmc;</div><div class='add'>+	no-sdio;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_eqos: eqosgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_ENET1_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK	0x4000050e</div><div class='add'>+			MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0		0x57e</div><div class='add'>+			MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1		0x57e</div><div class='add'>+			MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0		0x50e</div><div class='add'>+			MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1		0x50e</div><div class='add'>+			MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL	0x57e</div><div class='add'>+			MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL	0x50e</div><div class='add'>+			MX93_PAD_ENET1_RXC__ENET_QOS_RX_ER		0x57e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan1: flexcan1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_PDM_BIT_STREAM0__CAN1_RX	0x139e</div><div class='add'>+			MX93_PAD_PDM_CLK__CAN1_TX		0x139e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan1_tc: flexcan1tcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_ENET2_TD3__GPIO4_IO16		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c2: lpi2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_I2C2_SCL__LPI2C2_SCL		0x40000b9e</div><div class='add'>+			MX93_PAD_I2C2_SDA__LPI2C2_SDA		0x40000b9e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD2_RESET_B__GPIO3_IO07	0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_rtc: rtcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_ENET2_RD2__GPIO4_IO26		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai1: sai1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_UART2_RXD__SAI1_MCLK		0x1202</div><div class='add'>+			MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC	0x1202</div><div class='add'>+			MX93_PAD_SAI1_TXC__SAI1_TX_BCLK		0x1202</div><div class='add'>+			MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00	0x1402</div><div class='add'>+			MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00	0x1402</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_UART1_RXD__LPUART1_RX		0x31e</div><div class='add'>+			MX93_PAD_UART1_TXD__LPUART1_TX		0x30e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_cd: usdhc2cdgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD2_CD_B__GPIO3_IO00		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* need to config the SION for data and cmd pad, refer to ERR052021 */</div><div class='add'>+	pinctrl_usdhc2_default: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD2_CLK__USDHC2_CLK		0x159e</div><div class='add'>+			MX93_PAD_SD2_CMD__USDHC2_CMD		0x4000139e</div><div class='add'>+			MX93_PAD_SD2_DATA0__USDHC2_DATA0	0x4000138e</div><div class='add'>+			MX93_PAD_SD2_DATA1__USDHC2_DATA1	0x4000138e</div><div class='add'>+			MX93_PAD_SD2_DATA2__USDHC2_DATA2	0x4000138e</div><div class='add'>+			MX93_PAD_SD2_DATA3__USDHC2_DATA3	0x4000139e</div><div class='add'>+			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* need to config the SION for data and cmd pad, refer to ERR052021 */</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD2_CLK__USDHC2_CLK		0x159e</div><div class='add'>+			MX93_PAD_SD2_CMD__USDHC2_CMD		0x4000139e</div><div class='add'>+			MX93_PAD_SD2_DATA0__USDHC2_DATA0	0x4000138e</div><div class='add'>+			MX93_PAD_SD2_DATA1__USDHC2_DATA1	0x4000138e</div><div class='add'>+			MX93_PAD_SD2_DATA2__USDHC2_DATA2	0x4000139e</div><div class='add'>+			MX93_PAD_SD2_DATA3__USDHC2_DATA3	0x4000139e</div><div class='add'>+			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* need to config the SION for data and cmd pad, refer to ERR052021 */</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD2_CLK__USDHC2_CLK		0x158e</div><div class='add'>+			MX93_PAD_SD2_CMD__USDHC2_CMD		0x4000139e</div><div class='add'>+			MX93_PAD_SD2_DATA0__USDHC2_DATA0	0x4000139e</div><div class='add'>+			MX93_PAD_SD2_DATA1__USDHC2_DATA1	0x4000139e</div><div class='add'>+			MX93_PAD_SD2_DATA2__USDHC2_DATA2	0x4000139e</div><div class='add'>+			MX93_PAD_SD2_DATA3__USDHC2_DATA3	0x4000139e</div><div class='add'>+			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-rpmsg.dtso b/arch/arm64/boot/dts/freescale/imx93-phycore-rpmsg.dtso<br/>new file mode 100644<br/>index 000000000000..23bede7833f8<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx93-phycore-rpmsg.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx93-phycore-rpmsg.dtso</a></div><div class='hunk'>@@ -0,0 +1,60 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2025 PHYTEC Messtechnik GmbH</div><div class='add'>+ * Author: Primoz Fiser &lt;primoz.fiser@norik.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+&amp;{/} {</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		rsc_table: rsc-table@2021e000 {</div><div class='add'>+			reg = &lt;0 0x2021e000 0 0x1000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev0vring0: vdev0vring0@a4000000 {</div><div class='add'>+			reg = &lt;0 0xa4000000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev0vring1: vdev0vring1@a4008000 {</div><div class='add'>+			reg = &lt;0 0xa4008000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev1vring0: vdev1vring0@a4010000 {</div><div class='add'>+			reg = &lt;0 0xa4010000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev1vring1: vdev1vring1@a4018000 {</div><div class='add'>+			reg = &lt;0 0xa4018000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdevbuffer: vdevbuffer@a4020000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0xa4020000 0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cm33 {</div><div class='add'>+	mbox-names = "tx", "rx", "rxdb";</div><div class='add'>+	mboxes = &lt;&amp;mu1 0 1&gt;,</div><div class='add'>+		 &lt;&amp;mu1 1 1&gt;,</div><div class='add'>+		 &lt;&amp;mu1 3 1&gt;;</div><div class='add'>+	memory-region = &lt;&amp;vdevbuffer&gt;, &lt;&amp;vdev0vring0&gt;, &lt;&amp;vdev0vring1&gt;,</div><div class='add'>+		 &lt;&amp;vdev1vring0&gt;, &lt;&amp;vdev1vring1&gt;, &lt;&amp;rsc_table&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mu1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi<br/>new file mode 100644<br/>index 000000000000..3f069905cf0b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi</a></div><div class='hunk'>@@ -0,0 +1,299 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2023 PHYTEC Messtechnik GmbH</div><div class='add'>+ * Author: Wadim Egorov &lt;w.egorov@phytec.de&gt;, Christoph Stoidner &lt;c.stoidner@phytec.de&gt;</div><div class='add'>+ * Copyright (C) 2024 Mathieu Othacehe &lt;m.othacehe@gmail.com&gt;</div><div class='add'>+ *</div><div class='add'>+ * Product homepage:</div><div class='add'>+ * https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+#include "imx93.dtsi"</div><div class='add'>+</div><div class='add'>+/{</div><div class='add'>+	model = "PHYTEC phyCORE-i.MX93";</div><div class='add'>+	compatible = "phytec,imx93-phycore-som", "fsl,imx93";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;fec;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		ranges;</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		linux,cma {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reusable;</div><div class='add'>+			alloc-ranges = &lt;0 0x80000000 0 0x40000000&gt;;</div><div class='add'>+			size = &lt;0 0x10000000&gt;;</div><div class='add'>+			linux,cma-default;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_leds&gt;;</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_HEARTBEAT;</div><div class='add'>+			gpios = &lt;&amp;gpio1 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vdda_1v8: regulator-vdda-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDDA_1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;buck5&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* ADC */</div><div class='add'>+&amp;adc1 {</div><div class='add'>+	vref-supply = &lt;&amp;reg_vdda_1v8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Ethernet */</div><div class='add'>+&amp;fec {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec&gt;;</div><div class='add'>+	phy-mode = "rmii";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy1&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX93_CLK_ENET_TIMER1&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX93_CLK_ENET_REF&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX93_CLK_ENET_REF_PHY&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX93_CLK_SYS_PLL_PFD1_DIV2&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX93_CLK_SYS_PLL_PFD1_DIV2&gt;,</div><div class='add'>+				 &lt;&amp;clk IMX93_CLK_SYS_PLL_PFD1_DIV2&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;100000000&gt;, &lt;50000000&gt;, &lt;50000000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio: mdio {</div><div class='add'>+		clock-frequency = &lt;5000000&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy1: ethernet-phy@1 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio4 23 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			reset-assert-us = &lt;30&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* I2C3 */</div><div class='add'>+&amp;lpi2c3 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pmic@25 {</div><div class='add'>+		compatible = "nxp,pca9451a";</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pmic&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;27 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			buck1: BUCK1 {</div><div class='add'>+				regulator-name = "VDD_SOC";</div><div class='add'>+				regulator-min-microvolt = &lt;610000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;950000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck2: BUCK2 {</div><div class='add'>+				regulator-name = "VDDQ_0V6";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck4: BUCK4 {</div><div class='add'>+				regulator-name = "VDD_3V3_BUCK";</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck5: BUCK5 {</div><div class='add'>+				regulator-name = "VDD_1V8";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck6: BUCK6 {</div><div class='add'>+				regulator-name = "VDD_1V1";</div><div class='add'>+				regulator-min-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo1: LDO1 {</div><div class='add'>+				regulator-name = "PMIC_SNVS_1V8";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo4: LDO4 {</div><div class='add'>+				regulator-name = "VDD_0V8";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo5: LDO5 {</div><div class='add'>+				regulator-name = "NVCC_SD2";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* EEPROM */</div><div class='add'>+	eeprom@50 {</div><div class='add'>+		compatible = "atmel,24c32";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;buck4&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* eMMC */</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1_200mhz&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	no-1-8-v;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Watchdog */</div><div class='add'>+&amp;wdog3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_fec: fecgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_ENET2_MDC__ENET1_MDC			0x50e</div><div class='add'>+			MX93_PAD_ENET2_MDIO__ENET1_MDIO			0x502</div><div class='add'>+			/* the three pins below are connected to PHYs straps,</div><div class='add'>+			 * that is what the pull-up/down setting is for.</div><div class='add'>+			 */</div><div class='add'>+			MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0		0x37e</div><div class='add'>+			MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1		0x37e</div><div class='add'>+			MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL	0x57e</div><div class='add'>+			MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0		0x50e</div><div class='add'>+			MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1		0x50e</div><div class='add'>+			MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL	0x50e</div><div class='add'>+			MX93_PAD_ENET2_TD2__ENET1_TX_CLK		0x4000050e</div><div class='add'>+			MX93_PAD_ENET2_RXC__GPIO4_IO23			0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_leds: ledsgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_I2C1_SDA__GPIO1_IO01		0x11e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c3: lpi2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_GPIO_IO28__LPI2C3_SDA		0x40000b9e</div><div class='add'>+			MX93_PAD_GPIO_IO29__LPI2C3_SCL		0x40000b9e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pmic: pmicgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_ENET2_RD3__GPIO4_IO27		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* need to config the SION for data and cmd pad, refer to ERR052021 */</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD1_CLK__USDHC1_CLK		0x179e</div><div class='add'>+			MX93_PAD_SD1_CMD__USDHC1_CMD		0x40001386</div><div class='add'>+			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x4000138e</div><div class='add'>+			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x40001386</div><div class='add'>+			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x4000138e</div><div class='add'>+			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x40001386</div><div class='add'>+			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x40001386</div><div class='add'>+			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x40001386</div><div class='add'>+			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x40001386</div><div class='add'>+			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x40001386</div><div class='add'>+			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x179e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* need to config the SION for data and cmd pad, refer to ERR052021 */</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD1_CLK__USDHC1_CLK		0x17be</div><div class='add'>+			MX93_PAD_SD1_CMD__USDHC1_CMD		0x4000139e</div><div class='add'>+			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x4000138e</div><div class='add'>+			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x4000139e</div><div class='add'>+			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x400013be</div><div class='add'>+			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x4000139e</div><div class='add'>+			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x4000139e</div><div class='add'>+			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x4000139e</div><div class='add'>+			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x4000139e</div><div class='add'>+			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x4000139e</div><div class='add'>+			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x179e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* need to config the SION for data and cmd pad, refer to ERR052021 */</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD1_CLK__USDHC1_CLK		0x17be</div><div class='add'>+			MX93_PAD_SD1_CMD__USDHC1_CMD		0x4000139e</div><div class='add'>+			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x4000139e</div><div class='add'>+			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x400013be</div><div class='add'>+			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x400013be</div><div class='add'>+			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x400013be</div><div class='add'>+			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x400013be</div><div class='add'>+			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x400013be</div><div class='add'>+			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x400013be</div><div class='add'>+			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x400013be</div><div class='add'>+			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x179e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY	0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx93-pinfunc.h b/arch/arm64/boot/dts/freescale/imx93-pinfunc.h<br/>new file mode 100644<br/>index 000000000000..4298a145f8a9<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx93-pinfunc.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx93-pinfunc.h</a></div><div class='hunk'>@@ -0,0 +1,623 @@</div><div class='add'>+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __DTS_IMX93_PINFUNC_H</div><div class='add'>+#define __DTS_IMX93_PINFUNC_H</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * The pin function ID is a tuple of</div><div class='add'>+ * &lt;mux_reg conf_reg input_reg mux_mode input_val&gt;</div><div class='add'>+ */</div><div class='add'>+#define MX93_PAD_DAP_TDI__JTAG_MUX_TDI                            0x0000 0x01B0 0x03D8 0x0 0x0</div><div class='add'>+#define MX93_PAD_DAP_TDI__MQS2_LEFT                               0x0000 0x01B0 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_DAP_TDI__CAN2_TX                                 0x0000 0x01B0 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30                        0x0000 0x01B0 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_DAP_TDI__GPIO3_IO28                              0x0000 0x01B0 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_DAP_TDI__LPUART5_RX                              0x0000 0x01B0 0x0430 0x6 0x0</div><div class='add'>+#define MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS                      0x0004 0x01B4 0x03DC 0x0 0x0</div><div class='add'>+#define MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31                  0x0004 0x01B4 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29                        0x0004 0x01B4 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B                     0x0004 0x01B4 0x0000 0x6 0x0</div><div class='add'>+#define MX93_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK                     0x0008 0x01B8 0x03D4 0x0 0x0</div><div class='add'>+#define MX93_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30                 0x0008 0x01B8 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_DAP_TCLK_SWCLK__GPIO3_IO30                       0x0008 0x01B8 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B                    0x0008 0x01B8 0x042C 0x6 0x0</div><div class='add'>+#define MX93_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO                   0x000C 0x01BC 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT                     0x000C 0x01BC 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_DAP_TDO_TRACESWO__CAN2_RX                        0x000C 0x01BC 0x0364 0x3 0x0</div><div class='add'>+#define MX93_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31               0x000C 0x01BC 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_DAP_TDO_TRACESWO__GPIO3_IO31                     0x000C 0x01BC 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX                     0x000C 0x01BC 0x0434 0x6 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO00__GPIO2_IO00                            0x0010 0x01C0 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO00__LPI2C3_SDA                            0x0010 0x01C0 0x03E4 0x11 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK                      0x0010 0x01C0 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK                     0x0010 0x01C0 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO00__LPSPI6_PCS0                           0x0010 0x01C0 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO00__LPUART5_TX                            0x0010 0x01C0 0x0434 0x5 0x1</div><div class='add'>+#define MX93_PAD_GPIO_IO00__LPI2C5_SDA                            0x0010 0x01C0 0x03EC 0x16 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO00__FLEXIO1_FLEXIO00                      0x0010 0x01C0 0x036C 0x7 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO01__GPIO2_IO01                            0x0014 0x01C4 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO01__LPI2C3_SCL                            0x0014 0x01C4 0x03E0 0x11 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA00                   0x0014 0x01C4 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE                      0x0014 0x01C4 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO01__LPSPI6_SIN                            0x0014 0x01C4 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO01__LPUART5_RX                            0x0014 0x01C4 0x0430 0x5 0x1</div><div class='add'>+#define MX93_PAD_GPIO_IO01__LPI2C5_SCL                            0x0014 0x01C4 0x03E8 0x16 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO01__FLEXIO1_FLEXIO01                      0x0014 0x01C4 0x0370 0x7 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO02__GPIO2_IO02                            0x0018 0x01C8 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO02__LPI2C4_SDA                            0x0018 0x01C8 0x0000 0x11 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC                    0x0018 0x01C8 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC                   0x0018 0x01C8 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO02__LPSPI6_SOUT                           0x0018 0x01C8 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO02__LPUART5_CTS_B                         0x0018 0x01C8 0x042C 0x5 0x1</div><div class='add'>+#define MX93_PAD_GPIO_IO02__LPI2C6_SDA                            0x0018 0x01C8 0x03F4 0x16 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO02__FLEXIO1_FLEXIO02                      0x0018 0x01C8 0x0374 0x7 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO03__GPIO2_IO03                            0x001C 0x01CC 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO03__LPI2C4_SCL                            0x001C 0x01CC 0x0000 0x11 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC                    0x001C 0x01CC 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC                   0x001C 0x01CC 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO03__LPSPI6_SCK                            0x001C 0x01CC 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO03__LPUART5_RTS_B                         0x001C 0x01CC 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO03__LPI2C6_SCL                            0x001C 0x01CC 0x03F0 0x16 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO03__FLEXIO1_FLEXIO03                      0x001C 0x01CC 0x0378 0x7 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO04__GPIO2_IO04                            0x0020 0x01D0 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO04__TPM3_CH0                              0x0020 0x01D0 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO04__PDM_CLK                               0x0020 0x01D0 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00                  0x0020 0x01D0 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO04__LPSPI7_PCS0                           0x0020 0x01D0 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO04__LPUART6_TX                            0x0020 0x01D0 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO04__LPI2C6_SDA                            0x0020 0x01D0 0x03F4 0x16 0x1</div><div class='add'>+#define MX93_PAD_GPIO_IO04__FLEXIO1_FLEXIO04                      0x0020 0x01D0 0x037C 0x7 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO05__GPIO2_IO05                            0x0024 0x01D4 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO05__TPM4_CH0                              0x0024 0x01D4 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO05__PDM_BIT_STREAM00                      0x0024 0x01D4 0x0438 0x2 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01                  0x0024 0x01D4 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO05__LPSPI7_SIN                            0x0024 0x01D4 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO05__LPUART6_RX                            0x0024 0x01D4 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO05__LPI2C6_SCL                            0x0024 0x01D4 0x03F0 0x16 0x1</div><div class='add'>+#define MX93_PAD_GPIO_IO05__FLEXIO1_FLEXIO05                      0x0024 0x01D4 0x0380 0x7 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO06__GPIO2_IO06                            0x0028 0x01D8 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO06__TPM5_CH0                              0x0028 0x01D8 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO06__PDM_BIT_STREAM01                      0x0028 0x01D8 0x043C 0x2 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02                  0x0028 0x01D8 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO06__LPSPI7_SOUT                           0x0028 0x01D8 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO06__LPUART6_CTS_B                         0x0028 0x01D8 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO06__LPI2C7_SDA                            0x0028 0x01D8 0x03FC 0x16 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO06__FLEXIO1_FLEXIO06                      0x0028 0x01D8 0x0384 0x7 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO07__GPIO2_IO07                            0x002C 0x01DC 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO07__LPSPI3_PCS1                           0x002C 0x01DC 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO07__MEDIAMIX_CAM_DATA01                   0x002C 0x01DC 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03                  0x002C 0x01DC 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO07__LPSPI7_SCK                            0x002C 0x01DC 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO07__LPUART6_RTS_B                         0x002C 0x01DC 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO07__LPI2C7_SCL                            0x002C 0x01DC 0x03F8 0x16 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO07__FLEXIO1_FLEXIO07                      0x002C 0x01DC 0x0388 0x7 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO08__GPIO2_IO08                            0x0030 0x01E0 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO08__LPSPI3_PCS0                           0x0030 0x01E0 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO08__MEDIAMIX_CAM_DATA02                   0x0030 0x01E0 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04                  0x0030 0x01E0 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO08__TPM6_CH0                              0x0030 0x01E0 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO08__LPUART7_TX                            0x0030 0x01E0 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO08__LPI2C7_SDA                            0x0030 0x01E0 0x03FC 0x16 0x1</div><div class='add'>+#define MX93_PAD_GPIO_IO08__FLEXIO1_FLEXIO08                      0x0030 0x01E0 0x038C 0x7 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO09__GPIO2_IO09                            0x0034 0x01E4 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO09__LPSPI3_SIN                            0x0034 0x01E4 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO09__MEDIAMIX_CAM_DATA03                   0x0034 0x01E4 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05                  0x0034 0x01E4 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO09__TPM3_EXTCLK                           0x0034 0x01E4 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO09__LPUART7_RX                            0x0034 0x01E4 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO09__LPI2C7_SCL                            0x0034 0x01E4 0x03F8 0x16 0x1</div><div class='add'>+#define MX93_PAD_GPIO_IO09__FLEXIO1_FLEXIO09                      0x0034 0x01E4 0x0390 0x7 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO10__GPIO2_IO10                            0x0038 0x01E8 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO10__LPSPI3_SOUT                           0x0038 0x01E8 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO10__MEDIAMIX_CAM_DATA04                   0x0038 0x01E8 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06                  0x0038 0x01E8 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO10__TPM4_EXTCLK                           0x0038 0x01E8 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO10__LPUART7_CTS_B                         0x0038 0x01E8 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO10__LPI2C8_SDA                            0x0038 0x01E8 0x0404 0x16 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO10__FLEXIO1_FLEXIO10                      0x0038 0x01E8 0x0394 0x7 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO11__GPIO2_IO11                            0x003C 0x01EC 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO11__LPSPI3_SCK                            0x003C 0x01EC 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO11__MEDIAMIX_CAM_DATA05                   0x003C 0x01EC 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07                  0x003C 0x01EC 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO11__TPM5_EXTCLK                           0x003C 0x01EC 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO11__LPUART7_RTS_B                         0x003C 0x01EC 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO11__LPI2C8_SCL                            0x003C 0x01EC 0x0400 0x16 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO11__FLEXIO1_FLEXIO11                      0x003C 0x01EC 0x0398 0x7 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO12__GPIO2_IO12                            0x0040 0x01F0 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO12__TPM3_CH2                              0x0040 0x01F0 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO12__PDM_BIT_STREAM02                      0x0040 0x01F0 0x0440 0x2 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08                  0x0040 0x01F0 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO12__LPSPI8_PCS0                           0x0040 0x01F0 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO12__LPUART8_TX                            0x0040 0x01F0 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO12__LPI2C8_SDA                            0x0040 0x01F0 0x0404 0x16 0x1</div><div class='add'>+#define MX93_PAD_GPIO_IO12__SAI3_RX_SYNC                          0x0040 0x01F0 0x0450 0x7 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO13__GPIO2_IO13                            0x0044 0x01F4 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO13__TPM4_CH2                              0x0044 0x01F4 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO13__PDM_BIT_STREAM03                      0x0044 0x01F4 0x0444 0x2 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09                  0x0044 0x01F4 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO13__LPSPI8_SIN                            0x0044 0x01F4 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO13__LPUART8_RX                            0x0044 0x01F4 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO13__LPI2C8_SCL                            0x0044 0x01F4 0x0400 0x16 0x1</div><div class='add'>+#define MX93_PAD_GPIO_IO13__FLEXIO1_FLEXIO13                      0x0044 0x01F4 0x039C 0x7 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO14__GPIO2_IO14                            0x0048 0x01F8 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO14__LPUART3_TX                            0x0048 0x01F8 0x041C 0x1 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA06                   0x0048 0x01F8 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10                  0x0048 0x01F8 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO14__LPSPI8_SOUT                           0x0048 0x01F8 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO14__LPUART8_CTS_B                         0x0048 0x01F8 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO14__LPUART4_TX                            0x0048 0x01F8 0x0428 0x6 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO14__FLEXIO1_FLEXIO14                      0x0048 0x01F8 0x03A0 0x7 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO15__GPIO2_IO15                            0x004C 0x01FC 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO15__LPUART3_RX                            0x004C 0x01FC 0x0418 0x1 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA07                   0x004C 0x01FC 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11                  0x004C 0x01FC 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO15__LPSPI8_SCK                            0x004C 0x01FC 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO15__LPUART8_RTS_B                         0x004C 0x01FC 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO15__LPUART4_RX                            0x004C 0x01FC 0x0424 0x6 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO15__FLEXIO1_FLEXIO15                      0x004C 0x01FC 0x03A4 0x7 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO16__GPIO2_IO16                            0x0050 0x0200 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO16__SAI3_TX_BCLK                          0x0050 0x0200 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO16__PDM_BIT_STREAM02                      0x0050 0x0200 0x0440 0x2 0x1</div><div class='add'>+#define MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12                  0x0050 0x0200 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO16__LPUART3_CTS_B                         0x0050 0x0200 0x0414 0x4 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO16__LPSPI4_PCS2                           0x0050 0x0200 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO16__LPUART4_CTS_B                         0x0050 0x0200 0x0420 0x6 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO16__FLEXIO1_FLEXIO16                      0x0050 0x0200 0x03A8 0x7 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO17__GPIO2_IO17                            0x0054 0x0204 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO17__SAI3_MCLK                             0x0054 0x0204 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO17__MEDIAMIX_CAM_DATA08                   0x0054 0x0204 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13                  0x0054 0x0204 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO17__LPUART3_RTS_B                         0x0054 0x0204 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO17__LPSPI4_PCS1                           0x0054 0x0204 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO17__LPUART4_RTS_B                         0x0054 0x0204 0x0000 0x6 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO17__FLEXIO1_FLEXIO17                      0x0054 0x0204 0x03AC 0x7 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO18__GPIO2_IO18                            0x0058 0x0208 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO18__SAI3_RX_BCLK                          0x0058 0x0208 0x044C 0x1 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA09                   0x0058 0x0208 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14                  0x0058 0x0208 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO18__LPSPI5_PCS0                           0x0058 0x0208 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO18__LPSPI4_PCS0                           0x0058 0x0208 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO18__TPM5_CH2                              0x0058 0x0208 0x0000 0x6 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO18__FLEXIO1_FLEXIO18                      0x0058 0x0208 0x03B0 0x7 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO19__GPIO2_IO19                            0x005C 0x020C 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO19__SAI3_RX_SYNC                          0x005C 0x020C 0x0450 0x1 0x1</div><div class='add'>+#define MX93_PAD_GPIO_IO19__PDM_BIT_STREAM03                      0x005C 0x020C 0x0444 0x2 0x1</div><div class='add'>+#define MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15                  0x005C 0x020C 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO19__LPSPI5_SIN                            0x005C 0x020C 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO19__LPSPI4_SIN                            0x005C 0x020C 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO19__TPM6_CH2                              0x005C 0x020C 0x0000 0x6 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO19__SAI3_TX_DATA00                        0x005C 0x020C 0x0000 0x7 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO20__GPIO2_IO20                            0x0060 0x0210 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO20__SAI3_RX_DATA00                        0x0060 0x0210 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO20__PDM_BIT_STREAM00                      0x0060 0x0210 0x0438 0x2 0x1</div><div class='add'>+#define MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16                  0x0060 0x0210 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO20__LPSPI5_SOUT                           0x0060 0x0210 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO20__LPSPI4_SOUT                           0x0060 0x0210 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO20__TPM3_CH1                              0x0060 0x0210 0x0000 0x6 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO20__FLEXIO1_FLEXIO20                      0x0060 0x0210 0x03B4 0x7 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO21__GPIO2_IO21                            0x0064 0x0214 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO21__SAI3_TX_DATA00                        0x0064 0x0214 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO21__PDM_CLK                               0x0064 0x0214 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17                  0x0064 0x0214 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO21__LPSPI5_SCK                            0x0064 0x0214 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO21__LPSPI4_SCK                            0x0064 0x0214 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO21__TPM4_CH1                              0x0064 0x0214 0x0000 0x6 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO21__SAI3_RX_BCLK                          0x0064 0x0214 0x044C 0x7 0x1</div><div class='add'>+#define MX93_PAD_GPIO_IO22__GPIO2_IO22                            0x0068 0x0218 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO22__USDHC3_CLK                            0x0068 0x0218 0x0458 0x1 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO22__SPDIF_IN                              0x0068 0x0218 0x0454 0x2 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18                  0x0068 0x0218 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO22__TPM5_CH1                              0x0068 0x0218 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO22__TPM6_EXTCLK                           0x0068 0x0218 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO22__LPI2C5_SDA                            0x0068 0x0218 0x03EC 0x16 0x1</div><div class='add'>+#define MX93_PAD_GPIO_IO22__FLEXIO1_FLEXIO22                      0x0068 0x0218 0x03B8 0x7 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO23__GPIO2_IO23                            0x006C 0x021C 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO23__USDHC3_CMD                            0x006C 0x021C 0x045C 0x1 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO23__SPDIF_OUT                             0x006C 0x021C 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19                  0x006C 0x021C 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO23__TPM6_CH1                              0x006C 0x021C 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO23__LPI2C5_SCL                            0x006C 0x021C 0x03E8 0x16 0x1</div><div class='add'>+#define MX93_PAD_GPIO_IO23__FLEXIO1_FLEXIO23                      0x006C 0x021C 0x03BC 0x7 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO24__GPIO2_IO24                            0x0070 0x0220 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO24__USDHC3_DATA0                          0x0070 0x0220 0x0460 0x1 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20                  0x0070 0x0220 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO24__TPM3_CH3                              0x0070 0x0220 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO24__JTAG_MUX_TDO                          0x0070 0x0220 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO24__LPSPI6_PCS1                           0x0070 0x0220 0x0000 0x6 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO24__FLEXIO1_FLEXIO24                      0x0070 0x0220 0x03C0 0x7 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO25__GPIO2_IO25                            0x0074 0x0224 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO25__USDHC3_DATA1                          0x0074 0x0224 0x0464 0x1 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO25__CAN2_TX                               0x0074 0x0224 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21                  0x0074 0x0224 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO25__TPM4_CH3                              0x0074 0x0224 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO25__JTAG_MUX_TCK                          0x0074 0x0224 0x03D4 0x5 0x1</div><div class='add'>+#define MX93_PAD_GPIO_IO25__LPSPI7_PCS1                           0x0074 0x0224 0x0000 0x6 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO25__FLEXIO1_FLEXIO25                      0x0074 0x0224 0x03C4 0x7 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO26__GPIO2_IO26                            0x0078 0x0228 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO26__USDHC3_DATA2                          0x0078 0x0228 0x0468 0x1 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO26__PDM_BIT_STREAM01                      0x0078 0x0228 0x043C 0x2 0x1</div><div class='add'>+#define MX93_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22                  0x0078 0x0228 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO26__TPM5_CH3                              0x0078 0x0228 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO26__JTAG_MUX_TDI                          0x0078 0x0228 0x03D8 0x5 0x1</div><div class='add'>+#define MX93_PAD_GPIO_IO26__LPSPI8_PCS1                           0x0078 0x0228 0x0000 0x6 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO26__SAI3_TX_SYNC                          0x0078 0x0228 0x0000 0x7 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO27__GPIO2_IO27                            0x007C 0x022C 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO27__USDHC3_DATA3                          0x007C 0x022C 0x046C 0x1 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO27__CAN2_RX                               0x007C 0x022C 0x0364 0x2 0x1</div><div class='add'>+#define MX93_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23                  0x007C 0x022C 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO27__TPM6_CH3                              0x007C 0x022C 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO27__JTAG_MUX_TMS                          0x007C 0x022C 0x03DC 0x5 0x1</div><div class='add'>+#define MX93_PAD_GPIO_IO27__LPSPI5_PCS1                           0x007C 0x022C 0x0000 0x6 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO27__FLEXIO1_FLEXIO27                      0x007C 0x022C 0x03C8 0x7 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO28__GPIO2_IO28                            0x0080 0x0230 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO28__LPI2C3_SDA                            0x0080 0x0230 0x03E4 0x11 0x1</div><div class='add'>+#define MX93_PAD_GPIO_IO28__FLEXIO1_FLEXIO28                      0x0080 0x0230 0x0000 0x7 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO29__GPIO2_IO29                            0x0084 0x0234 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_GPIO_IO29__LPI2C3_SCL                            0x0084 0x0234 0x03E0 0x11 0x1</div><div class='add'>+#define MX93_PAD_GPIO_IO29__FLEXIO1_FLEXIO29                      0x0084 0x0234 0x0000 0x7 0x0</div><div class='add'>+#define MX93_PAD_CCM_CLKO1__CCMSRCGPCMIX_CLKO1                    0x0088 0x0238 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_CCM_CLKO1__FLEXIO1_FLEXIO26                      0x0088 0x0238 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_CCM_CLKO1__GPIO3_IO26                            0x0088 0x0238 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_CCM_CLKO2__GPIO3_IO27                            0x008C 0x023C 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_CCM_CLKO2__CCMSRCGPCMIX_CLKO2                    0x008C 0x023C 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_CCM_CLKO2__FLEXIO1_FLEXIO27                      0x008C 0x023C 0x03C8 0x4 0x1</div><div class='add'>+#define MX93_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3                    0x0090 0x0240 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_CCM_CLKO3__FLEXIO2_FLEXIO28                      0x0090 0x0240 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_CCM_CLKO3__GPIO4_IO28                            0x0090 0x0240 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_CCM_CLKO4__CCMSRCGPCMIX_CLKO4                    0x0094 0x0244 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_CCM_CLKO4__FLEXIO2_FLEXIO29                      0x0094 0x0244 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_CCM_CLKO4__GPIO4_IO29                            0x0094 0x0244 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_ENET1_MDC__ENET_QOS_MDC                          0x0098 0x0248 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_ENET1_MDC__LPUART3_DCB_B                         0x0098 0x0248 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_ENET1_MDC__I3C2_SCL                              0x0098 0x0248 0x03CC 0x2 0x0</div><div class='add'>+#define MX93_PAD_ENET1_MDC__HSIOMIX_OTG_ID1                       0x0098 0x0248 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_ENET1_MDC__FLEXIO2_FLEXIO00                      0x0098 0x0248 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_ENET1_MDC__GPIO4_IO00                            0x0098 0x0248 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO                        0x009C 0x024C 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_ENET1_MDIO__LPUART3_RIN_B                        0x009C 0x024C 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_ENET1_MDIO__I3C2_SDA                             0x009C 0x024C 0x03D0 0x2 0x0</div><div class='add'>+#define MX93_PAD_ENET1_MDIO__HSIOMIX_OTG_PWR1                     0x009C 0x024C 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_ENET1_MDIO__FLEXIO2_FLEXIO01                     0x009C 0x024C 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_ENET1_MDIO__GPIO4_IO01                           0x009C 0x024C 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3                    0x00A0 0x0250 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_ENET1_TD3__CAN2_TX                               0x00A0 0x0250 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_ENET1_TD3__HSIOMIX_OTG_ID2                       0x00A0 0x0250 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_ENET1_TD3__FLEXIO2_FLEXIO02                      0x00A0 0x0250 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_ENET1_TD3__GPIO4_IO02                            0x00A0 0x0250 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2                    0x00A4 0x0254 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_ENET1_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK   0x00A4 0x0254 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_ENET1_TD2__CAN2_RX                               0x00A4 0x0254 0x0364 0x2 0x2</div><div class='add'>+#define MX93_PAD_ENET1_TD2__HSIOMIX_OTG_OC2                       0x00A4 0x0254 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_ENET1_TD2__FLEXIO2_FLEXIO03                      0x00A4 0x0254 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_ENET1_TD2__GPIO4_IO03                            0x00A4 0x0254 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1                    0x00A8 0x0258 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_ENET1_TD1__LPUART3_RTS_B                         0x00A8 0x0258 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_ENET1_TD1__I3C2_PUR                              0x00A8 0x0258 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_ENET1_TD1__HSIOMIX_OTG_OC1                       0x00A8 0x0258 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_ENET1_TD1__FLEXIO2_FLEXIO04                      0x00A8 0x0258 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_ENET1_TD1__GPIO4_IO04                            0x00A8 0x0258 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_ENET1_TD1__I3C2_PUR_B                            0x00A8 0x0258 0x0000 0x6 0x0</div><div class='add'>+#define MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0                    0x00AC 0x025C 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_ENET1_TD0__LPUART3_TX                            0x00AC 0x025C 0x041C 0x1 0x1</div><div class='add'>+#define MX93_PAD_ENET1_TD0__FLEXIO2_FLEXIO05                      0x00AC 0x025C 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_ENET1_TD0__GPIO4_IO05                            0x00AC 0x025C 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL              0x00B0 0x0260 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_ENET1_TX_CTL__LPUART3_DTR_B                      0x00B0 0x0260 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO06                   0x00B0 0x0260 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_ENET1_TX_CTL__GPIO4_IO06                         0x00B0 0x0260 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK    0x00B4 0x0264 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_ENET1_TXC__ENET_QOS_TX_ER                        0x00B4 0x0264 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_ENET1_TXC__FLEXIO2_FLEXIO07                      0x00B4 0x0264 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_ENET1_TXC__GPIO4_IO07                            0x00B4 0x0264 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL              0x00B8 0x0268 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_ENET1_RX_CTL__LPUART3_DSR_B                      0x00B8 0x0268 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_ENET1_RX_CTL__HSIOMIX_OTG_PWR2                   0x00B8 0x0268 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO08                   0x00B8 0x0268 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_ENET1_RX_CTL__GPIO4_IO08                         0x00B8 0x0268 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK    0x00BC 0x026C 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_ENET1_RXC__ENET_QOS_RX_ER                        0x00BC 0x026C 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_ENET1_RXC__FLEXIO2_FLEXIO09                      0x00BC 0x026C 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_ENET1_RXC__GPIO4_IO09                            0x00BC 0x026C 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0                    0x00C0 0x0270 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_ENET1_RD0__LPUART3_RX                            0x00C0 0x0270 0x0418 0x1 0x1</div><div class='add'>+#define MX93_PAD_ENET1_RD0__FLEXIO2_FLEXIO10                      0x00C0 0x0270 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_ENET1_RD0__GPIO4_IO10                            0x00C0 0x0270 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1                    0x00C4 0x0274 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_ENET1_RD1__LPUART3_CTS_B                         0x00C4 0x0274 0x0414 0x1 0x1</div><div class='add'>+#define MX93_PAD_ENET1_RD1__LPTMR2_ALT1                           0x00C4 0x0274 0x0408 0x3 0x0</div><div class='add'>+#define MX93_PAD_ENET1_RD1__FLEXIO2_FLEXIO11                      0x00C4 0x0274 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_ENET1_RD1__GPIO4_IO11                            0x00C4 0x0274 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2                    0x00C8 0x0278 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_ENET1_RD2__LPTMR2_ALT2                           0x00C8 0x0278 0x040C 0x3 0x0</div><div class='add'>+#define MX93_PAD_ENET1_RD2__FLEXIO2_FLEXIO12                      0x00C8 0x0278 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_ENET1_RD2__GPIO4_IO12                            0x00C8 0x0278 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3                    0x00CC 0x027C 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_ENET1_RD3__FLEXSPI1_TESTER_TRIGGER               0x00CC 0x027C 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_ENET1_RD3__LPTMR2_ALT3                           0x00CC 0x027C 0x0410 0x3 0x0</div><div class='add'>+#define MX93_PAD_ENET1_RD3__FLEXIO2_FLEXIO13                      0x00CC 0x027C 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_ENET1_RD3__GPIO4_IO13                            0x00CC 0x027C 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_ENET2_MDC__ENET1_MDC                             0x00D0 0x0280 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_ENET2_MDC__LPUART4_DCB_B                         0x00D0 0x0280 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_ENET2_MDC__SAI2_RX_SYNC                          0x00D0 0x0280 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_ENET2_MDC__FLEXIO2_FLEXIO14                      0x00D0 0x0280 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_ENET2_MDC__GPIO4_IO14                            0x00D0 0x0280 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_ENET2_MDIO__ENET1_MDIO                           0x00D4 0x0284 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_ENET2_MDIO__LPUART4_RIN_B                        0x00D4 0x0284 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_ENET2_MDIO__SAI2_RX_BCLK                         0x00D4 0x0284 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_ENET2_MDIO__FLEXIO2_FLEXIO15                     0x00D4 0x0284 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_ENET2_MDIO__GPIO4_IO15                           0x00D4 0x0284 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_ENET2_TD3__SAI2_RX_DATA00                        0x00D8 0x0288 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_ENET2_TD3__FLEXIO2_FLEXIO16                      0x00D8 0x0288 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_ENET2_TD3__GPIO4_IO16                            0x00D8 0x0288 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3                       0x00D8 0x0288 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2                       0x00DC 0x028C 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_ENET2_TD2__ENET1_TX_CLK                          0x00DC 0x028C 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_ENET2_TD2__SAI2_RX_DATA01                        0x00DC 0x028C 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_ENET2_TD2__FLEXIO2_FLEXIO17                      0x00DC 0x028C 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_ENET2_TD2__GPIO4_IO17                            0x00DC 0x028C 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1                       0x00E0 0x0290 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_ENET2_TD1__LPUART4_RTS_B                         0x00E0 0x0290 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_ENET2_TD1__SAI2_RX_DATA02                        0x00E0 0x0290 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_ENET2_TD1__FLEXIO2_FLEXIO18                      0x00E0 0x0290 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_ENET2_TD1__GPIO4_IO18                            0x00E0 0x0290 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0                       0x00E4 0x0294 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_ENET2_TD0__LPUART4_TX                            0x00E4 0x0294 0x0428 0x1 0x1</div><div class='add'>+#define MX93_PAD_ENET2_TD0__SAI2_RX_DATA03                        0x00E4 0x0294 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_ENET2_TD0__FLEXIO2_FLEXIO19                      0x00E4 0x0294 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_ENET2_TD0__GPIO4_IO19                            0x00E4 0x0294 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL                 0x00E8 0x0298 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_ENET2_TX_CTL__LPUART4_DTR_B                      0x00E8 0x0298 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_ENET2_TX_CTL__SAI2_TX_SYNC                       0x00E8 0x0298 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO20                   0x00E8 0x0298 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_ENET2_TX_CTL__GPIO4_IO20                         0x00E8 0x0298 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC                       0x00EC 0x029C 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_ENET2_TXC__ENET1_TX_ER                           0x00EC 0x029C 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_ENET2_TXC__SAI2_TX_BCLK                          0x00EC 0x029C 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_ENET2_TXC__FLEXIO2_FLEXIO21                      0x00EC 0x029C 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_ENET2_TXC__GPIO4_IO21                            0x00EC 0x029C 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL                 0x00F0 0x02A0 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_ENET2_RX_CTL__LPUART4_DSR_B                      0x00F0 0x02A0 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_ENET2_RX_CTL__SAI2_TX_DATA00                     0x00F0 0x02A0 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO22                   0x00F0 0x02A0 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_ENET2_RX_CTL__GPIO4_IO22                         0x00F0 0x02A0 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC                       0x00F4 0x02A4 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_ENET2_RXC__ENET1_RX_ER                           0x00F4 0x02A4 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_ENET2_RXC__SAI2_TX_DATA01                        0x00F4 0x02A4 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_ENET2_RXC__FLEXIO2_FLEXIO23                      0x00F4 0x02A4 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_ENET2_RXC__GPIO4_IO23                            0x00F4 0x02A4 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0                       0x00F8 0x02A8 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_ENET2_RD0__LPUART4_RX                            0x00F8 0x02A8 0x0424 0x1 0x1</div><div class='add'>+#define MX93_PAD_ENET2_RD0__SAI2_TX_DATA02                        0x00F8 0x02A8 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_ENET2_RD0__FLEXIO2_FLEXIO24                      0x00F8 0x02A8 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_ENET2_RD0__GPIO4_IO24                            0x00F8 0x02A8 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1                       0x00FC 0x02AC 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_ENET2_RD1__SPDIF_IN                              0x00FC 0x02AC 0x0454 0x1 0x1</div><div class='add'>+#define MX93_PAD_ENET2_RD1__SAI2_TX_DATA03                        0x00FC 0x02AC 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_ENET2_RD1__FLEXIO2_FLEXIO25                      0x00FC 0x02AC 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_ENET2_RD1__GPIO4_IO25                            0x00FC 0x02AC 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2                       0x0100 0x02B0 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_ENET2_RD2__LPUART4_CTS_B                         0x0100 0x02B0 0x0420 0x1 0x1</div><div class='add'>+#define MX93_PAD_ENET2_RD2__SAI2_MCLK                             0x0100 0x02B0 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_ENET2_RD2__MQS2_RIGHT                            0x0100 0x02B0 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_ENET2_RD2__FLEXIO2_FLEXIO26                      0x0100 0x02B0 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_ENET2_RD2__GPIO4_IO26                            0x0100 0x02B0 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3                       0x0104 0x02B4 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_ENET2_RD3__SPDIF_OUT                             0x0104 0x02B4 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_ENET2_RD3__SPDIF_IN                              0x0104 0x02B4 0x0454 0x2 0x2</div><div class='add'>+#define MX93_PAD_ENET2_RD3__MQS2_LEFT                             0x0104 0x02B4 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_ENET2_RD3__FLEXIO2_FLEXIO27                      0x0104 0x02B4 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_ENET2_RD3__GPIO4_IO27                            0x0104 0x02B4 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_SD1_CLK__FLEXIO1_FLEXIO08                        0x0108 0x02B8 0x038C 0x4 0x1</div><div class='add'>+#define MX93_PAD_SD1_CLK__GPIO3_IO08                              0x0108 0x02B8 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_SD1_CLK__USDHC1_CLK                              0x0108 0x02B8 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_SD1_CMD__USDHC1_CMD                              0x010C 0x02BC 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_SD1_CMD__FLEXIO1_FLEXIO09                        0x010C 0x02BC 0x0390 0x4 0x1</div><div class='add'>+#define MX93_PAD_SD1_CMD__GPIO3_IO09                              0x010C 0x02BC 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_SD1_DATA0__USDHC1_DATA0                          0x0110 0x02C0 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_SD1_DATA0__FLEXIO1_FLEXIO10                      0x0110 0x02C0 0x0394 0x4 0x1</div><div class='add'>+#define MX93_PAD_SD1_DATA0__GPIO3_IO10                            0x0110 0x02C0 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_SD1_DATA1__USDHC1_DATA1                          0x0114 0x02C4 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_SD1_DATA1__FLEXIO1_FLEXIO11                      0x0114 0x02C4 0x0398 0x4 0x1</div><div class='add'>+#define MX93_PAD_SD1_DATA1__GPIO3_IO11                            0x0114 0x02C4 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_SD1_DATA1__CCMSRCGPCMIX_INT_BOOT                 0x0114 0x02C4 0x0000 0x6 0x0</div><div class='add'>+#define MX93_PAD_SD1_DATA2__USDHC1_DATA2                          0x0118 0x02C8 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_SD1_DATA2__FLEXIO1_FLEXIO12                      0x0118 0x02C8 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_SD1_DATA2__GPIO3_IO12                            0x0118 0x02C8 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_SD1_DATA2__CCMSRCGPCMIX_PMIC_READY               0x0118 0x02C8 0x0000 0x6 0x0</div><div class='add'>+#define MX93_PAD_SD1_DATA3__USDHC1_DATA3                          0x011C 0x02CC 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B                      0x011C 0x02CC 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_SD1_DATA3__FLEXIO1_FLEXIO13                      0x011C 0x02CC 0x039C 0x4 0x1</div><div class='add'>+#define MX93_PAD_SD1_DATA3__GPIO3_IO13                            0x011C 0x02CC 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_SD1_DATA4__USDHC1_DATA4                          0x0120 0x02D0 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_SD1_DATA4__FLEXSPI1_A_DATA04                     0x0120 0x02D0 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_SD1_DATA4__FLEXIO1_FLEXIO14                      0x0120 0x02D0 0x03A0 0x4 0x1</div><div class='add'>+#define MX93_PAD_SD1_DATA4__GPIO3_IO14                            0x0120 0x02D0 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_SD1_DATA5__USDHC1_DATA5                          0x0124 0x02D4 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_SD1_DATA5__FLEXSPI1_A_DATA05                     0x0124 0x02D4 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_SD1_DATA5__USDHC1_RESET_B                        0x0124 0x02D4 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_SD1_DATA5__FLEXIO1_FLEXIO15                      0x0124 0x02D4 0x03A4 0x4 0x1</div><div class='add'>+#define MX93_PAD_SD1_DATA5__GPIO3_IO15                            0x0124 0x02D4 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_SD1_DATA6__USDHC1_DATA6                          0x0128 0x02D8 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_SD1_DATA6__FLEXSPI1_A_DATA06                     0x0128 0x02D8 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_SD1_DATA6__USDHC1_CD_B                           0x0128 0x02D8 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_SD1_DATA6__FLEXIO1_FLEXIO16                      0x0128 0x02D8 0x03A8 0x4 0x1</div><div class='add'>+#define MX93_PAD_SD1_DATA6__GPIO3_IO16                            0x0128 0x02D8 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_SD1_DATA7__USDHC1_DATA7                          0x012C 0x02DC 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_SD1_DATA7__FLEXSPI1_A_DATA07                     0x012C 0x02DC 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_SD1_DATA7__USDHC1_WP                             0x012C 0x02DC 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_SD1_DATA7__FLEXIO1_FLEXIO17                      0x012C 0x02DC 0x03AC 0x4 0x1</div><div class='add'>+#define MX93_PAD_SD1_DATA7__GPIO3_IO17                            0x012C 0x02DC 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_SD1_STROBE__USDHC1_STROBE                        0x0130 0x02E0 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_SD1_STROBE__FLEXSPI1_A_DQS                       0x0130 0x02E0 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_SD1_STROBE__FLEXIO1_FLEXIO18                     0x0130 0x02E0 0x03B0 0x4 0x1</div><div class='add'>+#define MX93_PAD_SD1_STROBE__GPIO3_IO18                           0x0130 0x02E0 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_SD2_VSELECT__USDHC2_VSELECT                      0x0134 0x02E4 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_SD2_VSELECT__USDHC2_WP                           0x0134 0x02E4 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_SD2_VSELECT__LPTMR2_ALT3                         0x0134 0x02E4 0x0410 0x2 0x1</div><div class='add'>+#define MX93_PAD_SD2_VSELECT__FLEXIO1_FLEXIO19                    0x0134 0x02E4 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_SD2_VSELECT__GPIO3_IO19                          0x0134 0x02E4 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_SD2_VSELECT__CCMSRCGPCMIX_EXT_CLK1               0x0134 0x02E4 0x0368 0x6 0x0</div><div class='add'>+#define MX93_PAD_SD3_CLK__USDHC3_CLK                              0x0138 0x02E8 0x0458 0x0 0x1</div><div class='add'>+#define MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK                         0x0138 0x02E8 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_SD3_CLK__FLEXIO1_FLEXIO20                        0x0138 0x02E8 0x03B4 0x4 0x1</div><div class='add'>+#define MX93_PAD_SD3_CLK__GPIO3_IO20                              0x0138 0x02E8 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_SD3_CMD__USDHC3_CMD                              0x013C 0x02EC 0x045C 0x0 0x1</div><div class='add'>+#define MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B                        0x013C 0x02EC 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_SD3_CMD__FLEXIO1_FLEXIO21                        0x013C 0x02EC 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_SD3_CMD__GPIO3_IO21                              0x013C 0x02EC 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_SD3_DATA0__USDHC3_DATA0                          0x0140 0x02F0 0x0460 0x0 0x1</div><div class='add'>+#define MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00                     0x0140 0x02F0 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_SD3_DATA0__FLEXIO1_FLEXIO22                      0x0140 0x02F0 0x03B8 0x4 0x1</div><div class='add'>+#define MX93_PAD_SD3_DATA0__GPIO3_IO22                            0x0140 0x02F0 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_SD3_DATA1__USDHC3_DATA1                          0x0144 0x02F4 0x0464 0x0 0x1</div><div class='add'>+#define MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01                     0x0144 0x02F4 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_SD3_DATA1__FLEXIO1_FLEXIO23                      0x0144 0x02F4 0x03BC 0x4 0x1</div><div class='add'>+#define MX93_PAD_SD3_DATA1__GPIO3_IO23                            0x0144 0x02F4 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_SD3_DATA2__USDHC3_DATA2                          0x0148 0x02F8 0x0468 0x0 0x1</div><div class='add'>+#define MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02                     0x0148 0x02F8 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_SD3_DATA2__FLEXIO1_FLEXIO24                      0x0148 0x02F8 0x03C0 0x4 0x1</div><div class='add'>+#define MX93_PAD_SD3_DATA2__GPIO3_IO24                            0x0148 0x02F8 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_SD3_DATA3__USDHC3_DATA3                          0x014C 0x02FC 0x046C 0x0 0x1</div><div class='add'>+#define MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03                     0x014C 0x02FC 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_SD3_DATA3__FLEXIO1_FLEXIO25                      0x014C 0x02FC 0x03C4 0x4 0x1</div><div class='add'>+#define MX93_PAD_SD3_DATA3__GPIO3_IO25                            0x014C 0x02FC 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_SD2_CD_B__USDHC2_CD_B                            0x0150 0x0300 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_SD2_CD_B__ENET_QOS_1588_EVENT0_IN                0x0150 0x0300 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_SD2_CD_B__I3C2_SCL                               0x0150 0x0300 0x03CC 0x2 0x1</div><div class='add'>+#define MX93_PAD_SD2_CD_B__FLEXIO1_FLEXIO00                       0x0150 0x0300 0x036C 0x4 0x1</div><div class='add'>+#define MX93_PAD_SD2_CD_B__GPIO3_IO00                             0x0150 0x0300 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_SD2_CLK__USDHC2_CLK                              0x0154 0x0304 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_SD2_CLK__ENET_QOS_1588_EVENT0_OUT                0x0154 0x0304 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_SD2_CLK__I3C2_SDA                                0x0154 0x0304 0x03D0 0x2 0x1</div><div class='add'>+#define MX93_PAD_SD2_CLK__FLEXIO1_FLEXIO01                        0x0154 0x0304 0x0370 0x4 0x1</div><div class='add'>+#define MX93_PAD_SD2_CLK__GPIO3_IO01                              0x0154 0x0304 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0                   0x0154 0x0304 0x0000 0x6 0x0</div><div class='add'>+#define MX93_PAD_SD2_CMD__USDHC2_CMD                              0x0158 0x0308 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_SD2_CMD__ENET1_1588_EVENT0_IN                    0x0158 0x0308 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_SD2_CMD__I3C2_PUR                                0x0158 0x0308 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_SD2_CMD__I3C2_PUR_B                              0x0158 0x0308 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_SD2_CMD__FLEXIO1_FLEXIO02                        0x0158 0x0308 0x0374 0x4 0x1</div><div class='add'>+#define MX93_PAD_SD2_CMD__GPIO3_IO02                              0x0158 0x0308 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1                   0x0158 0x0308 0x0000 0x6 0x0</div><div class='add'>+#define MX93_PAD_SD2_DATA0__USDHC2_DATA0                          0x015C 0x030C 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_SD2_DATA0__ENET1_1588_EVENT0_OUT                 0x015C 0x030C 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_SD2_DATA0__CAN2_TX                               0x015C 0x030C 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_SD2_DATA0__FLEXIO1_FLEXIO03                      0x015C 0x030C 0x0378 0x4 0x1</div><div class='add'>+#define MX93_PAD_SD2_DATA0__GPIO3_IO03                            0x015C 0x030C 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2                 0x015C 0x030C 0x0000 0x6 0x0</div><div class='add'>+#define MX93_PAD_SD2_DATA1__USDHC2_DATA1                          0x0160 0x0310 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_SD2_DATA1__ENET1_1588_EVENT1_IN                  0x0160 0x0310 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_SD2_DATA1__CAN2_RX                               0x0160 0x0310 0x0364 0x2 0x3</div><div class='add'>+#define MX93_PAD_SD2_DATA1__FLEXIO1_FLEXIO04                      0x0160 0x0310 0x037C 0x4 0x1</div><div class='add'>+#define MX93_PAD_SD2_DATA1__GPIO3_IO04                            0x0160 0x0310 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT                     0x0160 0x0310 0x0000 0x6 0x0</div><div class='add'>+#define MX93_PAD_SD2_DATA2__USDHC2_DATA2                          0x0164 0x0314 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_SD2_DATA2__ENET1_1588_EVENT1_OUT                 0x0164 0x0314 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_SD2_DATA2__MQS2_RIGHT                            0x0164 0x0314 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_SD2_DATA2__FLEXIO1_FLEXIO05                      0x0164 0x0314 0x0380 0x4 0x1</div><div class='add'>+#define MX93_PAD_SD2_DATA2__GPIO3_IO05                            0x0164 0x0314 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP                     0x0164 0x0314 0x0000 0x6 0x0</div><div class='add'>+#define MX93_PAD_SD2_DATA3__USDHC2_DATA3                          0x0168 0x0318 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_SD2_DATA3__LPTMR2_ALT1                           0x0168 0x0318 0x0408 0x1 0x1</div><div class='add'>+#define MX93_PAD_SD2_DATA3__MQS2_LEFT                             0x0168 0x0318 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_SD2_DATA3__FLEXIO1_FLEXIO06                      0x0168 0x0318 0x0384 0x4 0x1</div><div class='add'>+#define MX93_PAD_SD2_DATA3__GPIO3_IO06                            0x0168 0x0318 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET              0x0168 0x0318 0x0000 0x6 0x0</div><div class='add'>+#define MX93_PAD_SD2_RESET_B__USDHC2_RESET_B                      0x016C 0x031C 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_SD2_RESET_B__LPTMR2_ALT2                         0x016C 0x031C 0x040C 0x1 0x1</div><div class='add'>+#define MX93_PAD_SD2_RESET_B__FLEXIO1_FLEXIO07                    0x016C 0x031C 0x0388 0x4 0x1</div><div class='add'>+#define MX93_PAD_SD2_RESET_B__GPIO3_IO07                          0x016C 0x031C 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET           0x016C 0x031C 0x0000 0x6 0x0</div><div class='add'>+#define MX93_PAD_I2C1_SCL__LPI2C1_SCL                             0x0170 0x0320 0x0000 0x10 0x0</div><div class='add'>+#define MX93_PAD_I2C1_SCL__I3C1_SCL                               0x0170 0x0320 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_I2C1_SCL__LPUART1_DCB_B                          0x0170 0x0320 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_I2C1_SCL__TPM2_CH0                               0x0170 0x0320 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_I2C1_SCL__GPIO1_IO00                             0x0170 0x0320 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_I2C1_SDA__LPI2C1_SDA                             0x0174 0x0324 0x0000 0x10 0x0</div><div class='add'>+#define MX93_PAD_I2C1_SDA__I3C1_SDA                               0x0174 0x0324 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_I2C1_SDA__LPUART1_RIN_B                          0x0174 0x0324 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_I2C1_SDA__TPM2_CH1                               0x0174 0x0324 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_I2C1_SDA__GPIO1_IO01                             0x0174 0x0324 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_I2C2_SCL__LPI2C2_SCL                             0x0178 0x0328 0x0000 0x10 0x0</div><div class='add'>+#define MX93_PAD_I2C2_SCL__I3C1_PUR                               0x0178 0x0328 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_I2C2_SCL__LPUART2_DCB_B                          0x0178 0x0328 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_I2C2_SCL__TPM2_CH2                               0x0178 0x0328 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_I2C2_SCL__SAI1_RX_SYNC                           0x0178 0x0328 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_I2C2_SCL__GPIO1_IO02                             0x0178 0x0328 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_I2C2_SCL__I3C1_PUR_B                             0x0178 0x0328 0x0000 0x6 0x0</div><div class='add'>+#define MX93_PAD_I2C2_SDA__LPI2C2_SDA                             0x017C 0x032C 0x0000 0x10 0x0</div><div class='add'>+#define MX93_PAD_I2C2_SDA__LPUART2_RIN_B                          0x017C 0x032C 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_I2C2_SDA__TPM2_CH3                               0x017C 0x032C 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_I2C2_SDA__SAI1_RX_BCLK                           0x017C 0x032C 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_I2C2_SDA__GPIO1_IO03                             0x017C 0x032C 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_UART1_RXD__LPUART1_RX                            0x0180 0x0330 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_UART1_RXD__S400_UART_RX                          0x0180 0x0330 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_UART1_RXD__LPSPI2_SIN                            0x0180 0x0330 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_UART1_RXD__TPM1_CH0                              0x0180 0x0330 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_UART1_RXD__GPIO1_IO04                            0x0180 0x0330 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_UART1_TXD__LPUART1_TX                            0x0184 0x0334 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_UART1_TXD__S400_UART_TX                          0x0184 0x0334 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_UART1_TXD__LPSPI2_PCS0                           0x0184 0x0334 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_UART1_TXD__TPM1_CH1                              0x0184 0x0334 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_UART1_TXD__GPIO1_IO05                            0x0184 0x0334 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_UART2_RXD__LPUART2_RX                            0x0188 0x0338 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_UART2_RXD__LPUART1_CTS_B                         0x0188 0x0338 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_UART2_RXD__LPSPI2_SOUT                           0x0188 0x0338 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_UART2_RXD__TPM1_CH2                              0x0188 0x0338 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_UART2_RXD__SAI1_MCLK                             0x0188 0x0338 0x0448 0x4 0x0</div><div class='add'>+#define MX93_PAD_UART2_RXD__GPIO1_IO06                            0x0188 0x0338 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_UART2_TXD__LPUART2_TX                            0x018C 0x033C 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_UART2_TXD__LPUART1_RTS_B                         0x018C 0x033C 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_UART2_TXD__LPSPI2_SCK                            0x018C 0x033C 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_UART2_TXD__TPM1_CH3                              0x018C 0x033C 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_UART2_TXD__GPIO1_IO07                            0x018C 0x033C 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_PDM_CLK__PDM_CLK                                 0x0190 0x0340 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_PDM_CLK__MQS1_LEFT                               0x0190 0x0340 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_PDM_CLK__LPTMR1_ALT1                             0x0190 0x0340 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_PDM_CLK__GPIO1_IO08                              0x0190 0x0340 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_PDM_CLK__CAN1_TX                                 0x0190 0x0340 0x0000 0x6 0x0</div><div class='add'>+#define MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00                0x0194 0x0344 0x0438 0x0 0x2</div><div class='add'>+#define MX93_PAD_PDM_BIT_STREAM0__MQS1_RIGHT                      0x0194 0x0344 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1                     0x0194 0x0344 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK                     0x0194 0x0344 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_PDM_BIT_STREAM0__LPTMR1_ALT2                     0x0194 0x0344 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_PDM_BIT_STREAM0__GPIO1_IO09                      0x0194 0x0344 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_PDM_BIT_STREAM0__CAN1_RX                         0x0194 0x0344 0x0360 0x6 0x0</div><div class='add'>+#define MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01                0x0198 0x0348 0x043C 0x0 0x2</div><div class='add'>+#define MX93_PAD_PDM_BIT_STREAM1__NMI_GLUE_NMI                    0x0198 0x0348 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1                     0x0198 0x0348 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK                     0x0198 0x0348 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_PDM_BIT_STREAM1__LPTMR1_ALT3                     0x0198 0x0348 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10                      0x0198 0x0348 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_EXT_CLK1           0x0198 0x0348 0x0368 0x6 0x1</div><div class='add'>+#define MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC                          0x019C 0x034C 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_SAI1_TXFS__SAI1_TX_DATA01                        0x019C 0x034C 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_SAI1_TXFS__LPSPI1_PCS0                           0x019C 0x034C 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_SAI1_TXFS__LPUART2_DTR_B                         0x019C 0x034C 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_SAI1_TXFS__MQS1_LEFT                             0x019C 0x034C 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_SAI1_TXFS__GPIO1_IO11                            0x019C 0x034C 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_SAI1_TXC__SAI1_TX_BCLK                           0x01A0 0x0350 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_SAI1_TXC__LPUART2_CTS_B                          0x01A0 0x0350 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_SAI1_TXC__LPSPI1_SIN                             0x01A0 0x0350 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_SAI1_TXC__LPUART1_DSR_B                          0x01A0 0x0350 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_SAI1_TXC__CAN1_RX                                0x01A0 0x0350 0x0360 0x4 0x1</div><div class='add'>+#define MX93_PAD_SAI1_TXC__GPIO1_IO12                             0x01A0 0x0350 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00                        0x01A4 0x0354 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_SAI1_TXD0__LPUART2_RTS_B                         0x01A4 0x0354 0x0000 0x1 0x0</div><div class='add'>+#define MX93_PAD_SAI1_TXD0__LPSPI1_SCK                            0x01A4 0x0354 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_SAI1_TXD0__LPUART1_DTR_B                         0x01A4 0x0354 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_SAI1_TXD0__CAN1_TX                               0x01A4 0x0354 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_SAI1_TXD0__GPIO1_IO13                            0x01A4 0x0354 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00                        0x01A8 0x0358 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_SAI1_RXD0__SAI1_MCLK                             0x01A8 0x0358 0x0448 0x1 0x1</div><div class='add'>+#define MX93_PAD_SAI1_RXD0__LPSPI1_SOUT                           0x01A8 0x0358 0x0000 0x2 0x0</div><div class='add'>+#define MX93_PAD_SAI1_RXD0__LPUART2_DSR_B                         0x01A8 0x0358 0x0000 0x3 0x0</div><div class='add'>+#define MX93_PAD_SAI1_RXD0__MQS1_RIGHT                            0x01A8 0x0358 0x0000 0x4 0x0</div><div class='add'>+#define MX93_PAD_SAI1_RXD0__GPIO1_IO14                            0x01A8 0x0358 0x0000 0x5 0x0</div><div class='add'>+#define MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY                         0x01AC 0x035C 0x0000 0x0 0x0</div><div class='add'>+#define MX93_PAD_WDOG_ANY__GPIO1_IO15                             0x01AC 0x035C 0x0000 0x5 0x0</div><div class='add'>+</div><div class='add'>+#endif /* __DTS_IMX93_PINFUNC_H */</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca.dts<br/>new file mode 100644<br/>index 000000000000..2673d9dccbf4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca.dts</a></div><div class='hunk'>@@ -0,0 +1,760 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2022-2025 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Markus Niebel</div><div class='add'>+ * Author: Alexander Stein</div><div class='add'>+ */</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/net/ti-dp83867.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pwm/pwm.h&gt;</div><div class='add'>+#include &lt;dt-bindings/usb/pd.h&gt;</div><div class='add'>+#include "imx93-tqma9352.dtsi"</div><div class='add'>+</div><div class='add'>+/{</div><div class='add'>+	model = "TQ-Systems i.MX93 TQMa93xxLA/TQMa93xxCA on MBa91xxCA starter kit";</div><div class='add'>+	compatible = "tq,imx93-tqma9352-mba91xxca", "tq,imx93-tqma9352", "fsl,imx93";</div><div class='add'>+	chassis-type = "embedded";</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;lpuart1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		eeprom0 = &amp;eeprom0;</div><div class='add'>+		ethernet0 = &amp;eqos;</div><div class='add'>+		ethernet1 = &amp;fec;</div><div class='add'>+		gpio0 = &amp;gpio1;</div><div class='add'>+		gpio1 = &amp;gpio2;</div><div class='add'>+		gpio2 = &amp;gpio3;</div><div class='add'>+		gpio3 = &amp;gpio4;</div><div class='add'>+		i2c0 = &amp;lpi2c1;</div><div class='add'>+		i2c1 = &amp;lpi2c2;</div><div class='add'>+		i2c2 = &amp;lpi2c3;</div><div class='add'>+		mmc0 = &amp;usdhc1;</div><div class='add'>+		mmc1 = &amp;usdhc2;</div><div class='add'>+		rtc0 = &amp;pcf85063;</div><div class='add'>+		rtc1 = &amp;bbnsm_rtc;</div><div class='add'>+		serial0 = &amp;lpuart1;</div><div class='add'>+		serial1 = &amp;lpuart2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	backlight: backlight {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		pwms = &lt;&amp;tpm2 2 5000000 0&gt;;</div><div class='add'>+		brightness-levels = &lt;0 4 8 16 32 64 128 255&gt;;</div><div class='add'>+		default-brightness-level = &lt;7&gt;;</div><div class='add'>+		power-supply = &lt;&amp;reg_12v0&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;expander2 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	display: display {</div><div class='add'>+		/*</div><div class='add'>+		 * Display is not fixed, so compatible has to be added from</div><div class='add'>+		 * DT overlay</div><div class='add'>+		 */</div><div class='add'>+		power-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;expander2 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		backlight = &lt;&amp;backlight&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			panel_in: endpoint {</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fan0: gpio-fan {</div><div class='add'>+		compatible = "gpio-fan";</div><div class='add'>+		gpios = &lt;&amp;expander2 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		gpio-fan,speed-map = &lt;0 0&gt;, &lt;10000 1&gt;;</div><div class='add'>+		fan-supply = &lt;&amp;reg_12v0&gt;;</div><div class='add'>+		#cooling-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		autorepeat;</div><div class='add'>+</div><div class='add'>+		switch-a {</div><div class='add'>+			label = "switcha";</div><div class='add'>+			linux,code = &lt;BTN_0&gt;;</div><div class='add'>+			gpios = &lt;&amp;expander0 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		switch-b {</div><div class='add'>+			label = "switchb";</div><div class='add'>+			linux,code = &lt;BTN_1&gt;;</div><div class='add'>+			gpios = &lt;&amp;expander0 7 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			gpios = &lt;&amp;expander2 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "default-on";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-2 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_AMBER&gt;;</div><div class='add'>+			function = LED_FUNCTION_HEARTBEAT;</div><div class='add'>+			gpios = &lt;&amp;expander2 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	iio-hwmon {</div><div class='add'>+		compatible = "iio-hwmon";</div><div class='add'>+		io-channels = &lt;&amp;adc1 0&gt;, &lt;&amp;adc1 1&gt;, &lt;&amp;adc1 2&gt;, &lt;&amp;adc1 3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lvds_encoder: lvds-encoder {</div><div class='add'>+		compatible = "ti,sn75lvds83", "lvds-encoder";</div><div class='add'>+		powerdown-gpios = &lt;&amp;expander2 3 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		power-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				lvds_encoder_input: endpoint {</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				lvds_encoder_output: endpoint {</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3v3: regulator-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "V_3V3_MB";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_5v0: regulator-5v0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "V_5V0_MB";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_12v0: regulator-12v0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "V_12V";</div><div class='add'>+		regulator-min-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;12000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;expander1 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_mpcie_1v5: regulator-mpcie-1v5 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "V_1V5_MPCIE";</div><div class='add'>+		regulator-min-microvolt = &lt;1500000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1500000&gt;;</div><div class='add'>+		gpio = &lt;&amp;expander0 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_mpcie_3v3: regulator-mpcie-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "V_3V3_MPCIE";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;expander0 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	thermal-zones {</div><div class='add'>+		cpu-thermal {</div><div class='add'>+			trips {</div><div class='add'>+				cpu_active: trip-active0 {</div><div class='add'>+					temperature = &lt;40000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "active";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map1 {</div><div class='add'>+					trip = &lt;&amp;cpu_active&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;fan0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;adc1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eqos {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_eqos&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy_eqos&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy_eqos: ethernet-phy@0 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_eqos_phy&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;expander1 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;500000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;50000&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+			interrupts = &lt;26 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+			enet-phy-lane-no-swap;</div><div class='add'>+			ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_2_25_NS&gt;;</div><div class='add'>+			ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_2_25_NS&gt;;</div><div class='add'>+			ti,fifo-depth = &lt;DP83867_PHYCR_FIFO_DEPTH_4_B_NIB&gt;;</div><div class='add'>+			ti,dp83867-rxctrl-strap-quirk;</div><div class='add'>+			ti,clk-output-sel = &lt;DP83867_CLK_O_SEL_OFF&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy_fec&gt;;</div><div class='add'>+	fsl,magic-packet;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;5000000&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy_fec: ethernet-phy@0 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_fec_phy&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;expander1 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;500000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;50000&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+			interrupts = &lt;27 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+			enet-phy-lane-no-swap;</div><div class='add'>+			ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_2_25_NS&gt;;</div><div class='add'>+			ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_2_25_NS&gt;;</div><div class='add'>+			ti,fifo-depth = &lt;DP83867_PHYCR_FIFO_DEPTH_4_B_NIB&gt;;</div><div class='add'>+			ti,dp83867-rxctrl-strap-quirk;</div><div class='add'>+			ti,clk-output-sel = &lt;DP83867_CLK_O_SEL_OFF&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan1&gt;;</div><div class='add'>+	xceiver-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		/* 00 */ "", "", "", "PMIC_IRQ#",</div><div class='add'>+		/* 04 */ "", "", "", "",</div><div class='add'>+		/* 08 */ "", "", "USB_C_ALERT#", "BM2_LCD_INT#",</div><div class='add'>+		/* 12 */ "PEX_INT#", "", "RTC_EVENT#", "",</div><div class='add'>+		/* 16 */ "", "", "", "",</div><div class='add'>+		/* 20 */ "", "", "", "",</div><div class='add'>+		/* 24 */ "", "", "", "",</div><div class='add'>+		/* 28 */ "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio2 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		/* 00 */ "", "", "", "",</div><div class='add'>+		/* 04 */ "", "", "", "",</div><div class='add'>+		/* 08 */ "", "", "", "",</div><div class='add'>+		/* 12 */ "", "", "", "",</div><div class='add'>+		/* 16 */ "", "", "", "",</div><div class='add'>+		/* 20 */ "", "", "", "",</div><div class='add'>+		/* 24 */ "", "", "", "",</div><div class='add'>+		/* 28 */ "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio3 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		/* 00 */ "SD2_CD#", "", "", "",</div><div class='add'>+		/* 04 */ "", "", "", "SD2_RST#",</div><div class='add'>+		/* 08 */ "", "", "", "",</div><div class='add'>+		/* 12 */ "", "", "", "",</div><div class='add'>+		/* 16 */ "", "", "", "",</div><div class='add'>+		/* 20 */ "", "", "", "",</div><div class='add'>+		/* 24 */ "", "", "ENET1_INT#", "ENET2_INT#",</div><div class='add'>+		/* 28 */ "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		/* 00 */ "", "", "", "",</div><div class='add'>+		/* 04 */ "", "", "", "",</div><div class='add'>+		/* 08 */ "", "", "", "",</div><div class='add'>+		/* 12 */ "", "", "", "",</div><div class='add'>+		/* 16 */ "", "", "", "",</div><div class='add'>+		/* 20 */ "", "", "", "",</div><div class='add'>+		/* 24 */ "", "", "", "",</div><div class='add'>+		/* 28 */ "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c3 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_lpi2c3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	temperature-sensor@1c {</div><div class='add'>+		compatible = "nxp,se97b", "jedec,jc-42.4-temp";</div><div class='add'>+		reg = &lt;0x1c&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ptn5110: usb-typec@50 {</div><div class='add'>+		compatible = "nxp,ptn5110", "tcpci";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_typec&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;10 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+</div><div class='add'>+		connector {</div><div class='add'>+			compatible = "usb-c-connector";</div><div class='add'>+			label = "X17";</div><div class='add'>+			power-role = "dual";</div><div class='add'>+			data-role = "dual";</div><div class='add'>+			try-power-role = "sink";</div><div class='add'>+			typec-power-opmode = "default";</div><div class='add'>+			pd-disable;</div><div class='add'>+			self-powered;</div><div class='add'>+</div><div class='add'>+			port {</div><div class='add'>+				typec_con_hs: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;typec_hs&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom2: eeprom@54 {</div><div class='add'>+		compatible = "nxp,se97b", "atmel,24c02";</div><div class='add'>+		reg = &lt;0x54&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	expander0: gpio@70 {</div><div class='add'>+		compatible = "nxp,pca9538";</div><div class='add'>+		reg = &lt;0x70&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pexp_irq&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;12 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+		gpio-line-names = "TEMP_EVENT_MOD#", "MPCIE_WAKE#",</div><div class='add'>+				  "MPCIE_1V5_EN", "MPCIE_3V3_EN",</div><div class='add'>+				  "MPCIE_PERST#", "MPCIE_WDISABLE#",</div><div class='add'>+				  "BUTTON_A#", "BUTTON_B#";</div><div class='add'>+</div><div class='add'>+		temp-event-mod-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			input;</div><div class='add'>+			line-name = "TEMP_EVENT_MOD#";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mpcie-wake-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			input;</div><div class='add'>+			line-name = "MPCIE_WAKE#";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Controls the mPCIE slot reset which is low active as</div><div class='add'>+		 * reset signal. The output-low states, the signal is</div><div class='add'>+		 * inactive, e.g. not in reset</div><div class='add'>+		 */</div><div class='add'>+		mpcie_rst_hog: mpcie-rst-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+			line-name = "MPCIE_PERST#";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Controls the mPCIE slot WDISABLE pin which is low active</div><div class='add'>+		 * as disable signal. The output-low states, the signal is</div><div class='add'>+		 * inactive, e.g. not disabled</div><div class='add'>+		 */</div><div class='add'>+		mpcie_wdisable_hog: mpcie-wdisable-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+			line-name = "MPCIE_WDISABLE#";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	expander1: gpio@71 {</div><div class='add'>+		compatible = "nxp,pca9538";</div><div class='add'>+		reg = &lt;0x71&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+		gpio-line-names = "ENET1_RESET#", "ENET2_RESET#",</div><div class='add'>+				  "USB_RESET#", "",</div><div class='add'>+				  "WLAN_PD#", "WLAN_W_DISABLE#",</div><div class='add'>+				  "WLAN_PERST#", "12V_EN";</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Controls the WiFi card PD pin which is low active</div><div class='add'>+		 * as power down signal. The output-low states, the signal</div><div class='add'>+		 * is inactive, e.g. not power down</div><div class='add'>+		 */</div><div class='add'>+		wlan-pd-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+			line-name = "WLAN_PD#";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Controls the WiFi card disable pin which is low active</div><div class='add'>+		 * as disable signal. The output-low states, the signal</div><div class='add'>+		 * is inactive, e.g. not disabled</div><div class='add'>+		 */</div><div class='add'>+		wlan-wdisable-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+			line-name = "WLAN_W_DISABLE#";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Controls the WiFi card reset pin which is low active</div><div class='add'>+		 * as reset signal. The output-low states, the signal</div><div class='add'>+		 * is inactive, e.g. not in reset</div><div class='add'>+		 */</div><div class='add'>+		wlan-perst-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+			line-name = "WLAN_PERST#";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	expander2: gpio@72 {</div><div class='add'>+		compatible = "nxp,pca9538";</div><div class='add'>+		reg = &lt;0x72&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+		gpio-line-names = "LCD_RESET#", "LCD_PWR_EN",</div><div class='add'>+				  "LCD_BLT_EN", "LVDS_SHDN#",</div><div class='add'>+				  "FAN_PWR_EN", "",</div><div class='add'>+				  "USER_LED1", "USER_LED2";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	linux,rs485-enabled-at-boot-time;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcf85063 {</div><div class='add'>+	/* RTC_EVENT# from SoM is connected on mainboard */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcf85063&gt;;</div><div class='add'>+	interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+	interrupts = &lt;14 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;se97_som {</div><div class='add'>+	/* TEMP_EVENT# from SoM is connected on mainboard */</div><div class='add'>+	interrupt-parent = &lt;&amp;expander0&gt;;</div><div class='add'>+	interrupts = &lt;0 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tpm2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_tpm2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	hnp-disable;</div><div class='add'>+	srp-disable;</div><div class='add'>+	adp-disable;</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	disable-over-current;</div><div class='add'>+	samsung,picophy-pre-emp-curr-control = &lt;3&gt;;</div><div class='add'>+	samsung,picophy-dc-vol-level-adjust = &lt;7&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	port {</div><div class='add'>+		typec_hs: endpoint {</div><div class='add'>+			remote-endpoint = &lt;&amp;typec_con_hs&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg2 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	disable-over-current;</div><div class='add'>+	samsung,picophy-pre-emp-curr-control = &lt;3&gt;;</div><div class='add'>+	samsung,picophy-dc-vol-level-adjust = &lt;7&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	hub_2_0: hub@1 {</div><div class='add'>+		compatible = "usb424,2517";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;expander1 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2_hs&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_uhs&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_uhs&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio3 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	no-sdio;</div><div class='add'>+	no-mmc;</div><div class='add'>+	disable-wp;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_eqos: eqosgrp {</div><div class='add'>+		fsl,pins = /* PD | FSEL_2 | DSE X4 */</div><div class='add'>+			   &lt;MX93_PAD_ENET1_MDC__ENET_QOS_MDC				0x51e&gt;,</div><div class='add'>+			   /* SION | HYS | ODE | FSEL_2 | DSE X4 */</div><div class='add'>+			   &lt;MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO				0x4000111e&gt;,</div><div class='add'>+			   /* HYS | FSEL_0 | DSE no drive */</div><div class='add'>+			   &lt;MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0			0x1000&gt;,</div><div class='add'>+			   &lt;MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1			0x1000&gt;,</div><div class='add'>+			   &lt;MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2			0x1000&gt;,</div><div class='add'>+			   &lt;MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3			0x1000&gt;,</div><div class='add'>+			   &lt;MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x1000&gt;,</div><div class='add'>+			   /* HYS | PD | FSEL_0 | DSE no drive */</div><div class='add'>+			   &lt;MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x1400&gt;,</div><div class='add'>+			   /* PD | FSEL_2 | DSE X4 */</div><div class='add'>+			   &lt;MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0			0x51e&gt;,</div><div class='add'>+			   &lt;MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1			0x51e&gt;,</div><div class='add'>+			   &lt;MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2			0x51e&gt;,</div><div class='add'>+			   &lt;MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3			0x51e&gt;,</div><div class='add'>+			   &lt;MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x51e&gt;,</div><div class='add'>+			   /* PD | FSEL_3 | DSE X3 */</div><div class='add'>+			   &lt;MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x58e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_eqos_phy: eqosphygrp {</div><div class='add'>+		fsl,pins = /* HYS | FSEL_0 | DSE no drive */</div><div class='add'>+			   &lt;MX93_PAD_CCM_CLKO1__GPIO3_IO26			0x1000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec: fecgrp {</div><div class='add'>+		fsl,pins = /* PD | FSEL_2 | DSE X4 */</div><div class='add'>+			   &lt;MX93_PAD_ENET2_MDC__ENET1_MDC			0x51e&gt;,</div><div class='add'>+			   /* SION | HYS | ODE | FSEL_2 | DSE X4 */</div><div class='add'>+			   &lt;MX93_PAD_ENET2_MDIO__ENET1_MDIO			0x4000111e&gt;,</div><div class='add'>+			   /* HYS | FSEL_0 | DSE no drive */</div><div class='add'>+			   &lt;MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0			0x1000&gt;,</div><div class='add'>+			   &lt;MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1			0x1000&gt;,</div><div class='add'>+			   &lt;MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2			0x1000&gt;,</div><div class='add'>+			   &lt;MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3			0x1000&gt;,</div><div class='add'>+			   &lt;MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL		0x1000&gt;,</div><div class='add'>+			   /* HYS | PD | FSEL_0 | DSE no drive */</div><div class='add'>+			   &lt;MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC			0x1400&gt;,</div><div class='add'>+			   /* PD | FSEL_2 | DSE X4 */</div><div class='add'>+			   &lt;MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0			0x51e&gt;,</div><div class='add'>+			   &lt;MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1			0x51e&gt;,</div><div class='add'>+			   &lt;MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2			0x51e&gt;,</div><div class='add'>+			   &lt;MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3			0x51e&gt;,</div><div class='add'>+			   &lt;MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL		0x51e&gt;,</div><div class='add'>+			   /* PD | FSEL_3 | DSE X3 */</div><div class='add'>+			   &lt;MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC			0x58e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec_phy: fecphygrp {</div><div class='add'>+		fsl,pins = /* HYS | FSEL_0 | DSE no drive */</div><div class='add'>+			   &lt;MX93_PAD_CCM_CLKO2__GPIO3_IO27			0x1000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan1: flexcan1grp {</div><div class='add'>+		fsl,pins = /* HYS | PU | FSEL_0 | DSE no drive */</div><div class='add'>+			   &lt;MX93_PAD_PDM_BIT_STREAM0__CAN1_RX		0x1200&gt;,</div><div class='add'>+			   /* PU | FSEL_3 | DSE X4 */</div><div class='add'>+			   &lt;MX93_PAD_PDM_CLK__CAN1_TX			0x039e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_jtag: jtaggrp {</div><div class='add'>+		fsl,pins = &lt;MX93_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK	0x051e&gt;,</div><div class='add'>+			   &lt;MX93_PAD_DAP_TDI__JTAG_MUX_TDI		0x1200&gt;,</div><div class='add'>+			   &lt;MX93_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO	0x031e&gt;,</div><div class='add'>+			   &lt;MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS	0x1200&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c3: lpi2c3grp {</div><div class='add'>+		fsl,pins = /* SION | HYS | OD | FSEL_3 | DSE X4 */</div><div class='add'>+			   &lt;MX93_PAD_GPIO_IO28__LPI2C3_SDA		0x4000199e&gt;,</div><div class='add'>+			   &lt;MX93_PAD_GPIO_IO29__LPI2C3_SCL		0x4000199e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcf85063: pcf85063grp {</div><div class='add'>+		fsl,pins = &lt;MX93_PAD_SAI1_RXD0__GPIO1_IO14		0x1000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pexp_irq: pexpirqgrp {</div><div class='add'>+		fsl,pins = /* HYS | FSEL_0 | No DSE */</div><div class='add'>+			   &lt;MX93_PAD_SAI1_TXC__GPIO1_IO12		0x1000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_rgbdisp: rgbdispgrp {</div><div class='add'>+		fsl,pins = &lt;MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK	0x31e&gt;,</div><div class='add'>+			   &lt;MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE	0x31e&gt;,</div><div class='add'>+			   &lt;MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC	0x31e&gt;,</div><div class='add'>+			   &lt;MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC	0x31e&gt;,</div><div class='add'>+			   &lt;MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00	0x31e&gt;,</div><div class='add'>+			   &lt;MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01	0x31e&gt;,</div><div class='add'>+			   &lt;MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02	0x31e&gt;,</div><div class='add'>+			   &lt;MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03	0x31e&gt;,</div><div class='add'>+			   &lt;MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04	0x31e&gt;,</div><div class='add'>+			   &lt;MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05	0x31e&gt;,</div><div class='add'>+			   &lt;MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06	0x31e&gt;,</div><div class='add'>+			   &lt;MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07	0x31e&gt;,</div><div class='add'>+			   &lt;MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08	0x31e&gt;,</div><div class='add'>+			   &lt;MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09	0x31e&gt;,</div><div class='add'>+			   &lt;MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10	0x31e&gt;,</div><div class='add'>+			   &lt;MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11	0x31e&gt;,</div><div class='add'>+			   &lt;MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12	0x31e&gt;,</div><div class='add'>+			   &lt;MX93_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13	0x31e&gt;,</div><div class='add'>+			   &lt;MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14	0x31e&gt;,</div><div class='add'>+			   &lt;MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15	0x31e&gt;,</div><div class='add'>+			   &lt;MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16	0x31e&gt;,</div><div class='add'>+			   &lt;MX93_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17	0x31e&gt;,</div><div class='add'>+			   &lt;MX93_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18	0x31e&gt;,</div><div class='add'>+			   &lt;MX93_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19	0x31e&gt;,</div><div class='add'>+			   &lt;MX93_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20	0x31e&gt;,</div><div class='add'>+			   &lt;MX93_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21	0x31e&gt;,</div><div class='add'>+			   &lt;MX93_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22	0x31e&gt;,</div><div class='add'>+			   &lt;MX93_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23	0x31e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_touch: touchgrp {</div><div class='add'>+		fsl,pins = /* HYS | FSEL_0 | No DSE */</div><div class='add'>+			   &lt;MX93_PAD_SAI1_TXFS__GPIO1_IO11		0x1000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_tpm2: tpm2grp {</div><div class='add'>+		fsl,pins = &lt;MX93_PAD_I2C2_SCL__TPM2_CH2			0x57e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_typec: typecgrp {</div><div class='add'>+		fsl,pins = /* HYS | FSEL_0 | No DSE */</div><div class='add'>+			   &lt;MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10	0x1000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = /* HYS | FSEL_0 | No DSE */</div><div class='add'>+			   &lt;MX93_PAD_UART1_RXD__LPUART1_RX		0x1000&gt;,</div><div class='add'>+			   /* FSEL_2 | DSE X4 */</div><div class='add'>+			   &lt;MX93_PAD_UART1_TXD__LPUART1_TX		0x011e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = /* HYS | FSEL_0 | No DSE */</div><div class='add'>+			   &lt;MX93_PAD_UART2_RXD__LPUART2_RX		0x1000&gt;,</div><div class='add'>+			   /* FSEL_2 | DSE X4 */</div><div class='add'>+			   &lt;MX93_PAD_UART2_TXD__LPUART2_TX		0x011e&gt;,</div><div class='add'>+			   /* FSEL_2 | DSE X4 */</div><div class='add'>+			   &lt;MX93_PAD_SAI1_TXD0__LPUART2_RTS_B		0x011e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='add'>+		fsl,pins = /* HYS | FSEL_0 | No DSE */</div><div class='add'>+			   &lt;MX93_PAD_SD2_CD_B__GPIO3_IO00		0x1000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* enable SION for data and cmd pad due to ERR052021 */</div><div class='add'>+	pinctrl_usdhc2_hs: usdhc2hsgrp {</div><div class='add'>+		fsl,pins = /* PD | FSEL_3 | DSE X5 */</div><div class='add'>+			   &lt;MX93_PAD_SD2_CLK__USDHC2_CLK		0x05be&gt;,</div><div class='add'>+			   /* HYS | PU | FSEL_3 | DSE X4 */</div><div class='add'>+			   &lt;MX93_PAD_SD2_CMD__USDHC2_CMD		0x4000139e&gt;,</div><div class='add'>+			   /* HYS | PU | FSEL_3 | DSE X3 */</div><div class='add'>+			   &lt;MX93_PAD_SD2_DATA0__USDHC2_DATA0		0x4000138e&gt;,</div><div class='add'>+			   &lt;MX93_PAD_SD2_DATA1__USDHC2_DATA1		0x4000138e&gt;,</div><div class='add'>+			   &lt;MX93_PAD_SD2_DATA2__USDHC2_DATA2		0x4000138e&gt;,</div><div class='add'>+			   &lt;MX93_PAD_SD2_DATA3__USDHC2_DATA3		0x4000138e&gt;,</div><div class='add'>+			   /* FSEL_2 | DSE X3 */</div><div class='add'>+			   &lt;MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x010e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* enable SION for data and cmd pad due to ERR052021 */</div><div class='add'>+	pinctrl_usdhc2_uhs: usdhc2uhsgrp {</div><div class='add'>+		fsl,pins = /* PD | FSEL_3 | DSE X6 */</div><div class='add'>+			   &lt;MX93_PAD_SD2_CLK__USDHC2_CLK		0x05fe&gt;,</div><div class='add'>+			   /* HYS | PU | FSEL_3 | DSE X4 */</div><div class='add'>+			   &lt;MX93_PAD_SD2_CMD__USDHC2_CMD		0x4000139e&gt;,</div><div class='add'>+			   &lt;MX93_PAD_SD2_DATA0__USDHC2_DATA0		0x4000139e&gt;,</div><div class='add'>+			   &lt;MX93_PAD_SD2_DATA1__USDHC2_DATA1		0x4000139e&gt;,</div><div class='add'>+			   &lt;MX93_PAD_SD2_DATA2__USDHC2_DATA2		0x4000139e&gt;,</div><div class='add'>+			   &lt;MX93_PAD_SD2_DATA3__USDHC2_DATA3		0x4000139e&gt;,</div><div class='add'>+			   /* FSEL_2 | DSE X3 */</div><div class='add'>+			   &lt;MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x010e&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts<br/>new file mode 100644<br/>index 000000000000..4760d07ea24b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts</a></div><div class='hunk'>@@ -0,0 +1,930 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2022-2024 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Markus Niebel</div><div class='add'>+ * Author: Alexander Stein</div><div class='add'>+ */</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/net/ti-dp83867.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pwm/pwm.h&gt;</div><div class='add'>+</div><div class='add'>+#include "imx93-tqma9352.dtsi"</div><div class='add'>+</div><div class='add'>+/{</div><div class='add'>+	model = "TQ-Systems i.MX93 TQMa93xxLA/TQMa93xxCA on MBa93xxCA starter kit";</div><div class='add'>+	compatible = "tq,imx93-tqma9352-mba93xxca",</div><div class='add'>+		     "tq,imx93-tqma9352", "fsl,imx93";</div><div class='add'>+	chassis-type = "embedded";</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;lpuart1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		eeprom0 = &amp;eeprom0;</div><div class='add'>+		ethernet0 = &amp;eqos;</div><div class='add'>+		ethernet1 = &amp;fec;</div><div class='add'>+		gpio0 = &amp;gpio1;</div><div class='add'>+		gpio1 = &amp;gpio2;</div><div class='add'>+		gpio2 = &amp;gpio3;</div><div class='add'>+		gpio3 = &amp;gpio4;</div><div class='add'>+		i2c0 = &amp;lpi2c1;</div><div class='add'>+		i2c1 = &amp;lpi2c2;</div><div class='add'>+		i2c2 = &amp;lpi2c3;</div><div class='add'>+		i2c3 = &amp;lpi2c4;</div><div class='add'>+		i2c4 = &amp;lpi2c5;</div><div class='add'>+		mmc0 = &amp;usdhc1;</div><div class='add'>+		mmc1 = &amp;usdhc2;</div><div class='add'>+		rtc0 = &amp;pcf85063;</div><div class='add'>+		rtc1 = &amp;bbnsm_rtc;</div><div class='add'>+		serial0 = &amp;lpuart1;</div><div class='add'>+		serial1 = &amp;lpuart2;</div><div class='add'>+		serial2 = &amp;lpuart3;</div><div class='add'>+		serial3 = &amp;lpuart4;</div><div class='add'>+		serial4 = &amp;lpuart5;</div><div class='add'>+		serial5 = &amp;lpuart6;</div><div class='add'>+		serial6 = &amp;lpuart7;</div><div class='add'>+		serial7 = &amp;lpuart8;</div><div class='add'>+		spi0 = &amp;lpspi1;</div><div class='add'>+		spi1 = &amp;lpspi2;</div><div class='add'>+		spi2 = &amp;lpspi3;</div><div class='add'>+		spi3 = &amp;lpspi4;</div><div class='add'>+		spi4 = &amp;lpspi5;</div><div class='add'>+		spi5 = &amp;lpspi6;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	backlight_lvds: backlight {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		pwms = &lt;&amp;tpm5 0 5000000 0&gt;;</div><div class='add'>+		brightness-levels = &lt;0 4 8 16 32 64 128 255&gt;;</div><div class='add'>+		default-brightness-level = &lt;7&gt;;</div><div class='add'>+		power-supply = &lt;&amp;reg_12v0&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;expander2 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fan0: pwm-fan {</div><div class='add'>+		compatible = "pwm-fan";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pwmfan&gt;;</div><div class='add'>+		fan-supply = &lt;&amp;reg_pwm_fan&gt;;</div><div class='add'>+		#cooling-cells = &lt;2&gt;;</div><div class='add'>+		/* typical 25 kHz -&gt; 40.000 nsec */</div><div class='add'>+		pwms = &lt;&amp;tpm6 0 40000 PWM_POLARITY_INVERTED&gt;;</div><div class='add'>+		cooling-levels = &lt;0 32 64 128 196 240&gt;;</div><div class='add'>+		pulses-per-revolution = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio2&gt;;</div><div class='add'>+		interrupts = &lt;9 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		autorepeat;</div><div class='add'>+</div><div class='add'>+		switch-a {</div><div class='add'>+			label = "switcha";</div><div class='add'>+			linux,code = &lt;BTN_0&gt;;</div><div class='add'>+			gpios = &lt;&amp;expander0 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		switch-b {</div><div class='add'>+			label = "switchb";</div><div class='add'>+			linux,code = &lt;BTN_1&gt;;</div><div class='add'>+			gpios = &lt;&amp;expander0 7 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			gpios = &lt;&amp;expander2 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "default-on";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-2 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_AMBER&gt;;</div><div class='add'>+			function = LED_FUNCTION_HEARTBEAT;</div><div class='add'>+			gpios = &lt;&amp;expander2 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	iio-hwmon {</div><div class='add'>+		compatible = "iio-hwmon";</div><div class='add'>+		io-channels = &lt;&amp;adc1 0&gt;, &lt;&amp;adc1 1&gt;, &lt;&amp;adc1 2&gt;, &lt;&amp;adc1 3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3v3: regulator-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "V_3V3_MB";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_5v0: regulator-5v0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "V_5V0_MB";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_12v0: regulator-12v0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "V_12V";</div><div class='add'>+		regulator-min-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;12000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;expander1 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_mpcie_1v5: regulator-mpcie-1v5 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "V_1V5_MPCIE";</div><div class='add'>+		regulator-min-microvolt = &lt;1500000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1500000&gt;;</div><div class='add'>+		gpio = &lt;&amp;expander0 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_mpcie_3v3: regulator-mpcie-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "V_3V3_MPCIE";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;expander0 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_pwm_fan: regulator-pwm-fan {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "FAN_PWR";</div><div class='add'>+		regulator-min-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;12000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;expander0 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		vin-supply = &lt;&amp;reg_12v0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	thermal-zones {</div><div class='add'>+		cpu-thermal {</div><div class='add'>+			trips {</div><div class='add'>+				cpu_active0: trip-active0 {</div><div class='add'>+					temperature = &lt;40000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "active";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_active1: trip-active1 {</div><div class='add'>+					temperature = &lt;48000&gt;;</div><div class='add'>+					hysteresis = &lt;3000&gt;;</div><div class='add'>+					type = "active";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_active2: trip-active2 {</div><div class='add'>+					temperature = &lt;60000&gt;;</div><div class='add'>+					hysteresis = &lt;10000&gt;;</div><div class='add'>+					type = "active";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map1 {</div><div class='add'>+					trip = &lt;&amp;cpu_active0&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;fan0 1 1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				map2 {</div><div class='add'>+					trip = &lt;&amp;cpu_active1&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;fan0 2 2&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				map3 {</div><div class='add'>+					trip = &lt;&amp;cpu_active2&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;fan0 3 3&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;adc1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eqos {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_eqos&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy_eqos&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy_eqos: ethernet-phy@0 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_eqos_phy&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;expander1 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;500000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;50000&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+			interrupts = &lt;26 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+			enet-phy-lane-no-swap;</div><div class='add'>+			ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_2_25_NS&gt;;</div><div class='add'>+			ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_2_25_NS&gt;;</div><div class='add'>+			ti,fifo-depth = &lt;DP83867_PHYCR_FIFO_DEPTH_4_B_NIB&gt;;</div><div class='add'>+			ti,dp83867-rxctrl-strap-quirk;</div><div class='add'>+			ti,clk-output-sel = &lt;DP83867_CLK_O_SEL_OFF&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy_fec&gt;;</div><div class='add'>+	fsl,magic-packet;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;5000000&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy_fec: ethernet-phy@0 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_fec_phy&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;expander1 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;500000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;50000&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+			interrupts = &lt;27 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+			enet-phy-lane-no-swap;</div><div class='add'>+			ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_2_25_NS&gt;;</div><div class='add'>+			ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_2_25_NS&gt;;</div><div class='add'>+			ti,fifo-depth = &lt;DP83867_PHYCR_FIFO_DEPTH_4_B_NIB&gt;;</div><div class='add'>+			ti,dp83867-rxctrl-strap-quirk;</div><div class='add'>+			ti,clk-output-sel = &lt;DP83867_CLK_O_SEL_OFF&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan1&gt;;</div><div class='add'>+	xceiver-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan2&gt;;</div><div class='add'>+	xceiver-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		/* 00 */ "", "", "USB_C_ALERT#", "PMIC_IRQ#",</div><div class='add'>+		/* 04 */ "", "", "", "",</div><div class='add'>+		/* 08 */ "", "", "", "BM2_TEMP_EVENT_MOD#",</div><div class='add'>+		/* 12 */ "PEX_INT#", "", "RTC_EVENT#", "",</div><div class='add'>+		/* 16 */ "", "", "", "",</div><div class='add'>+		/* 20 */ "", "", "", "",</div><div class='add'>+		/* 24 */ "", "", "", "",</div><div class='add'>+		/* 28 */ "", "", "", "";</div><div class='add'>+</div><div class='add'>+	expander-irq-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		input;</div><div class='add'>+		line-name = "PEX_INT#";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	tcpc-irq-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		input;</div><div class='add'>+		line-name = "USB_C_ALERT#";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio2&gt;;</div><div class='add'>+</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		/* 00 */ "SPI6_PCS0#", "", "", "",</div><div class='add'>+		/* 04 */ "", "", "", "",</div><div class='add'>+		/* 08 */ "", "FAN_RPM", "MIPI_CSI_TRIGGER", "MIPI_CSI_SYNC",</div><div class='add'>+		/* 12 */ "", "", "", "",</div><div class='add'>+		/* 16 */ "X1_11", "X1_21", "X1_17", "X1_13",</div><div class='add'>+		/* 20 */ "X1_15", "X1_9", "", "",</div><div class='add'>+		/* 24 */ "", "", "X1_7", "",</div><div class='add'>+		/* 28 */ "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio3 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		/* 00 */ "SD2_CD#", "", "", "",</div><div class='add'>+		/* 04 */ "", "", "", "SD2_RST#",</div><div class='add'>+		/* 08 */ "", "", "", "",</div><div class='add'>+		/* 12 */ "", "", "", "",</div><div class='add'>+		/* 16 */ "", "", "", "",</div><div class='add'>+		/* 20 */ "", "", "", "",</div><div class='add'>+		/* 24 */ "", "", "ENET1_INT#", "ENET2_INT#",</div><div class='add'>+		/* 28 */ "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		/* 00 */ "", "", "", "",</div><div class='add'>+		/* 04 */ "", "", "", "",</div><div class='add'>+		/* 08 */ "", "", "", "",</div><div class='add'>+		/* 12 */ "", "", "", "",</div><div class='add'>+		/* 16 */ "", "", "", "",</div><div class='add'>+		/* 20 */ "", "", "", "",</div><div class='add'>+		/* 24 */ "", "", "", "",</div><div class='add'>+		/* 28 */ "", "DP_INT", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c3 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_lpi2c3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	temperature-sensor@1c {</div><div class='add'>+		compatible = "nxp,se97b", "jedec,jc-42.4-temp";</div><div class='add'>+		reg = &lt;0x1c&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ptn5110: usb-typec@50 {</div><div class='add'>+		compatible = "nxp,ptn5110", "tcpci";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_typec&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;2 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+</div><div class='add'>+		connector {</div><div class='add'>+			compatible = "usb-c-connector";</div><div class='add'>+			label = "X17";</div><div class='add'>+			power-role = "dual";</div><div class='add'>+			data-role = "dual";</div><div class='add'>+			try-power-role = "sink";</div><div class='add'>+			typec-power-opmode = "default";</div><div class='add'>+			pd-disable;</div><div class='add'>+			self-powered;</div><div class='add'>+</div><div class='add'>+			port {</div><div class='add'>+				typec_con_hs: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;typec_hs&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom2: eeprom@54 {</div><div class='add'>+		compatible = "nxp,se97b", "atmel,24c02";</div><div class='add'>+		reg = &lt;0x54&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	expander0: gpio@70 {</div><div class='add'>+		compatible = "nxp,pca9538";</div><div class='add'>+		reg = &lt;0x70&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pexp_irq&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;12 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+		gpio-line-names = "FAN_PWR_EN", "MPCIE_WAKE#",</div><div class='add'>+				  "MPCIE_1V5_EN", "MPCIE_3V3_EN",</div><div class='add'>+				  "MPCIE_PERST#", "MPCIE_WDISABLE#",</div><div class='add'>+				  "BUTTON_A#", "BUTTON_B#";</div><div class='add'>+</div><div class='add'>+		mpcie-wake-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			input;</div><div class='add'>+			line-name = "MPCIE_WAKE#";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Controls the mPCIE slot reset which is low active as</div><div class='add'>+		 * reset signal. The output-low states, the signal is</div><div class='add'>+		 * inactive, e.g. not in reset</div><div class='add'>+		 */</div><div class='add'>+		mpcie_rst_hog: mpcie-rst-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+			line-name = "MPCIE_PERST#";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Controls the mPCIE slot WDISABLE pin which is low active</div><div class='add'>+		 * as disable signal. The output-low states, the signal is</div><div class='add'>+		 * inactive, e.g. not disabled</div><div class='add'>+		 */</div><div class='add'>+		mpcie_wdisable_hog: mpcie-wdisable-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+			line-name = "MPCIE_WDISABLE#";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	expander1: gpio@71 {</div><div class='add'>+		compatible = "nxp,pca9538";</div><div class='add'>+		reg = &lt;0x71&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+		gpio-line-names = "ENET1_RESET#", "ENET2_RESET#",</div><div class='add'>+				  "USB_RESET#", "",</div><div class='add'>+				  "WLAN_PD#", "WLAN_W_DISABLE#",</div><div class='add'>+				  "WLAN_PERST#", "12V_EN";</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Controls the WiFi card's low-active power down pin.</div><div class='add'>+		 * The output-low states, the signal is inactive,</div><div class='add'>+		 * resulting in high signal at power-down pin</div><div class='add'>+		 */</div><div class='add'>+		wlan-pd-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+			line-name = "WLAN_PD#";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Controls the WiFi card's low-active disable pin.</div><div class='add'>+		 * The output-low states, the signal is inactive,</div><div class='add'>+		 * resulting in high signal at power-down pin</div><div class='add'>+		 */</div><div class='add'>+		wlan-wdisable-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+			line-name = "WLAN_W_DISABLE#";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Controls the WiFi card's reset pin.</div><div class='add'>+		 * The output-low states, the signal is inactive,</div><div class='add'>+		 * resulting in high signal at power-down pin</div><div class='add'>+		 */</div><div class='add'>+		wlan-perst-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+			line-name = "WLAN_PERST#";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	expander2: gpio@72 {</div><div class='add'>+		compatible = "nxp,pca9538";</div><div class='add'>+		reg = &lt;0x72&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+		gpio-line-names = "LCD_RESET#", "LCD_PWR_EN",</div><div class='add'>+				  "LCD_BLT_EN", "DP_EN",</div><div class='add'>+				  "MIPI_CSI_EN", "MIPI_CSI_RST#",</div><div class='add'>+				  "USER_LED1", "USER_LED2";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c5 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c5&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_lpi2c5&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpspi6 {</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpspi6&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_lpspi6&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	linux,rs485-enabled-at-boot-time;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* disabled per default, console for M33 */</div><div class='add'>+&amp;lpuart3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart6 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart6&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart8 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart8&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcf85063 {</div><div class='add'>+	/* RTC_EVENT# from SoM is connected on mainboard */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcf85063&gt;;</div><div class='add'>+	interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+	interrupts = &lt;14 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;se97_som {</div><div class='add'>+	/* TEMP_EVENT# from SoM is connected on mainboard */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_temp_sensor_som&gt;;</div><div class='add'>+	interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+	interrupts = &lt;11 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tpm5 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_tpm5&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tpm6 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_tpm6&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	hnp-disable;</div><div class='add'>+	srp-disable;</div><div class='add'>+	adp-disable;</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	disable-over-current;</div><div class='add'>+	samsung,picophy-pre-emp-curr-control = &lt;3&gt;;</div><div class='add'>+	samsung,picophy-dc-vol-level-adjust = &lt;7&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	port {</div><div class='add'>+		typec_hs: endpoint {</div><div class='add'>+			remote-endpoint = &lt;&amp;typec_con_hs&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg2 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	disable-over-current;</div><div class='add'>+	samsung,picophy-pre-emp-curr-control = &lt;3&gt;;</div><div class='add'>+	samsung,picophy-dc-vol-level-adjust = &lt;7&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	hub_2_0: usb-hub@1 {</div><div class='add'>+		compatible = "usb424,2517";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;expander1 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2_hs&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_uhs&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_uhs&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio3 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	no-sdio;</div><div class='add'>+	no-mmc;</div><div class='add'>+	disable-wp;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_eqos: eqosgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* PD | FSEL_2 | DSE X4 */</div><div class='add'>+			MX93_PAD_ENET1_MDC__ENET_QOS_MDC			0x51e</div><div class='add'>+			/* SION | HYS | FSEL_2 | DSE X4 */</div><div class='add'>+			MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO			0x4000111e</div><div class='add'>+			/* HYS | FSEL_0 | DSE no drive */</div><div class='add'>+			MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0			0x1000</div><div class='add'>+			MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1			0x1000</div><div class='add'>+			MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2			0x1000</div><div class='add'>+			MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3			0x1000</div><div class='add'>+			MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x1000</div><div class='add'>+			/* HYS | PD | FSEL_0 | DSE no drive */</div><div class='add'>+			MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x1400</div><div class='add'>+			/* PD | FSEL_2 | DSE X4 */</div><div class='add'>+			MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0			0x51e</div><div class='add'>+			MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1			0x51e</div><div class='add'>+			MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2			0x51e</div><div class='add'>+			MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3			0x51e</div><div class='add'>+			MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x51e</div><div class='add'>+			/* PD | FSEL_3 | DSE X3 */</div><div class='add'>+			MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x58e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_eqos_phy: eqosphygrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* HYS | FSEL_0 | DSE no drive */</div><div class='add'>+			MX93_PAD_CCM_CLKO1__GPIO3_IO26			0x1000</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec: fecgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* PD | FSEL_2 | DSE X4 */</div><div class='add'>+			MX93_PAD_ENET2_MDC__ENET1_MDC			0x51e</div><div class='add'>+			/* SION | HYS | FSEL_2 | DSE X4 */</div><div class='add'>+			MX93_PAD_ENET2_MDIO__ENET1_MDIO			0x4000111e</div><div class='add'>+			/* HYS | FSEL_0 | DSE no drive */</div><div class='add'>+			MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0		0x1000</div><div class='add'>+			MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1		0x1000</div><div class='add'>+			MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2		0x1000</div><div class='add'>+			MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3		0x1000</div><div class='add'>+			MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL	0x1000</div><div class='add'>+			/* HYS | PD | FSEL_0 | DSE no drive */</div><div class='add'>+			MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC		0x1400</div><div class='add'>+			/* PD | FSEL_2 | DSE X4 */</div><div class='add'>+			MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0		0x51e</div><div class='add'>+			MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1		0x51e</div><div class='add'>+			MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2		0x51e</div><div class='add'>+			MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3		0x51e</div><div class='add'>+			MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL	0x51e</div><div class='add'>+			/* PD | FSEL_3 | DSE X3 */</div><div class='add'>+			MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC		0x58e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec_phy: fecphygrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* HYS | FSEL_0 | DSE no drive */</div><div class='add'>+			MX93_PAD_CCM_CLKO2__GPIO3_IO27			0x1000</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan1: flexcan1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* HYS | PU | FSEL_0 | DSE no drive */</div><div class='add'>+			MX93_PAD_PDM_BIT_STREAM0__CAN1_RX		0x1200</div><div class='add'>+			/* PU | FSEL_3 | DSE X4 */</div><div class='add'>+			MX93_PAD_PDM_CLK__CAN1_TX			0x039e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan2: flexcan2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* HYS | PU | FSEL_0 | DSE no drive */</div><div class='add'>+			MX93_PAD_GPIO_IO27__CAN2_RX			0x1200</div><div class='add'>+			/* PU | FSEL_3 | DSE X4 */</div><div class='add'>+			MX93_PAD_GPIO_IO25__CAN2_TX			0x039e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio2: gpio2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* HYS | PD | FSEL_2 | DSE X4 */</div><div class='add'>+			MX93_PAD_GPIO_IO16__GPIO2_IO16			0x151e</div><div class='add'>+			MX93_PAD_GPIO_IO17__GPIO2_IO17			0x151e</div><div class='add'>+			MX93_PAD_GPIO_IO18__GPIO2_IO18			0x151e</div><div class='add'>+			MX93_PAD_GPIO_IO19__GPIO2_IO19			0x151e</div><div class='add'>+			MX93_PAD_GPIO_IO20__GPIO2_IO20			0x151e</div><div class='add'>+			MX93_PAD_GPIO_IO21__GPIO2_IO21			0x151e</div><div class='add'>+			MX93_PAD_GPIO_IO26__GPIO2_IO26			0x151e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_jtag: jtaggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK		0x051e</div><div class='add'>+			MX93_PAD_DAP_TDI__JTAG_MUX_TDI			0x1200</div><div class='add'>+			MX93_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO		0x031e</div><div class='add'>+			MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS		0x1200</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c3: lpi2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* SION | HYS | OD | FSEL_3 | DSE X4 */</div><div class='add'>+			MX93_PAD_GPIO_IO28__LPI2C3_SDA			0x4000199e</div><div class='add'>+			MX93_PAD_GPIO_IO29__LPI2C3_SCL			0x4000199e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c5: lpi2c5grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* SION | HYS | OD | FSEL_3 | DSE X4 */</div><div class='add'>+			MX93_PAD_GPIO_IO22__LPI2C5_SDA			0x4000199e</div><div class='add'>+			MX93_PAD_GPIO_IO23__LPI2C5_SCL			0x4000199e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpspi6: lpspi6grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* FSEL_2 | DSE X4 */</div><div class='add'>+			MX93_PAD_GPIO_IO00__LPSPI6_PCS0			0x011e</div><div class='add'>+			/* HYS | PD | FSEL_0 | DSE no drive */</div><div class='add'>+			MX93_PAD_GPIO_IO01__LPSPI6_SIN			0x1400</div><div class='add'>+			/* PD | FSEL_2 | DSE X4 */</div><div class='add'>+			MX93_PAD_GPIO_IO02__LPSPI6_SOUT			0x051e</div><div class='add'>+			MX93_PAD_GPIO_IO03__LPSPI6_SCK			0x051e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_mipi_csi: mipicsigrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3		0x051e /* MCLK */</div><div class='add'>+			MX93_PAD_GPIO_IO10__GPIO2_IO10			0x051e /* TRIGGER */</div><div class='add'>+			MX93_PAD_GPIO_IO11__GPIO2_IO11			0x1400 /* SYNC */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcf85063: pcf85063grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SAI1_RXD0__GPIO1_IO14			0x1000</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pexp_irq: pexpirqgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* HYS | FSEL_0 | No DSE */</div><div class='add'>+			MX93_PAD_SAI1_TXC__GPIO1_IO12			0x1000</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwmfan: pwmfangrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* HYS | PU | FSEL_0 | no DSE */</div><div class='add'>+			MX93_PAD_GPIO_IO09__GPIO2_IO09			0x1200</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_tc9595: tc9595-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* HYS | PD | FSEL_0 | no DSE */</div><div class='add'>+			MX93_PAD_CCM_CLKO4__GPIO4_IO29			0x1400</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_temp_sensor_som: tempsensorsomgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* HYS | FSEL_0 | no DSE */</div><div class='add'>+			MX93_PAD_SAI1_TXFS__GPIO1_IO11			0x1000</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_tpm5: tpm5grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_GPIO_IO06__TPM5_CH0			0x57e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_tpm6: tpm6grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_GPIO_IO08__TPM6_CH0			0x57e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_typec: typecgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* HYS | FSEL_0 | No DSE */</div><div class='add'>+			MX93_PAD_I2C2_SCL__GPIO1_IO02			0x1000</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* HYS | FSEL_0 | No DSE */</div><div class='add'>+			MX93_PAD_UART1_RXD__LPUART1_RX			0x1000</div><div class='add'>+			/* FSEL_2 | DSE X4 */</div><div class='add'>+			MX93_PAD_UART1_TXD__LPUART1_TX			0x011e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* HYS | FSEL_0 | No DSE */</div><div class='add'>+			MX93_PAD_UART2_RXD__LPUART2_RX			0x1000</div><div class='add'>+			/* FSEL_2 | DSE X4 */</div><div class='add'>+			MX93_PAD_UART2_TXD__LPUART2_TX			0x011e</div><div class='add'>+			/* FSEL_2 | DSE X4 */</div><div class='add'>+			MX93_PAD_SAI1_TXD0__LPUART2_RTS_B		0x011e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: uart3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* HYS | FSEL_0 | No DSE */</div><div class='add'>+			MX93_PAD_GPIO_IO15__LPUART3_RX			0x1000</div><div class='add'>+			/* FSEL_2 | DSE X4 */</div><div class='add'>+			MX93_PAD_GPIO_IO14__LPUART3_TX			0x011e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart6: uart6grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* HYS | FSEL_0 | No DSE */</div><div class='add'>+			MX93_PAD_GPIO_IO05__LPUART6_RX			0x1000</div><div class='add'>+			/* FSEL_2 | DSE X4 */</div><div class='add'>+			MX93_PAD_GPIO_IO04__LPUART6_TX			0x011e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart8: uart8grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* HYS | FSEL_0 | No DSE */</div><div class='add'>+			MX93_PAD_GPIO_IO13__LPUART8_RX			0x1000</div><div class='add'>+			/* FSEL_2 | DSE X4 */</div><div class='add'>+			MX93_PAD_GPIO_IO12__LPUART8_TX			0x011e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* HYS | FSEL_0 | No DSE */</div><div class='add'>+			MX93_PAD_SD2_CD_B__GPIO3_IO00			0x1000</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* enable SION for data and cmd pad due to ERR052021 */</div><div class='add'>+	pinctrl_usdhc2_hs: usdhc2hsgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* PD | FSEL_3 | DSE X5 */</div><div class='add'>+			MX93_PAD_SD2_CLK__USDHC2_CLK			0x05be</div><div class='add'>+			/* HYS | PU | FSEL_3 | DSE X4 */</div><div class='add'>+			MX93_PAD_SD2_CMD__USDHC2_CMD			0x4000139e</div><div class='add'>+			/* HYS | PU | FSEL_3 | DSE X3 */</div><div class='add'>+			MX93_PAD_SD2_DATA0__USDHC2_DATA0		0x4000138e</div><div class='add'>+			MX93_PAD_SD2_DATA1__USDHC2_DATA1		0x4000138e</div><div class='add'>+			MX93_PAD_SD2_DATA2__USDHC2_DATA2		0x4000138e</div><div class='add'>+			MX93_PAD_SD2_DATA3__USDHC2_DATA3		0x4000138e</div><div class='add'>+			/* FSEL_2 | DSE X3 */</div><div class='add'>+			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT		0x010e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* enable SION for data and cmd pad due to ERR052021 */</div><div class='add'>+	pinctrl_usdhc2_uhs: usdhc2uhsgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* PD | FSEL_3 | DSE X6 */</div><div class='add'>+			MX93_PAD_SD2_CLK__USDHC2_CLK			0x05fe</div><div class='add'>+			/* HYS | PU | FSEL_3 | DSE X4 */</div><div class='add'>+			MX93_PAD_SD2_CMD__USDHC2_CMD			0x4000139e</div><div class='add'>+			MX93_PAD_SD2_DATA0__USDHC2_DATA0		0x4000139e</div><div class='add'>+			MX93_PAD_SD2_DATA1__USDHC2_DATA1		0x4000139e</div><div class='add'>+			MX93_PAD_SD2_DATA2__USDHC2_DATA2		0x4000139e</div><div class='add'>+			MX93_PAD_SD2_DATA3__USDHC2_DATA3		0x4000139e</div><div class='add'>+			/* FSEL_2 | DSE X3 */</div><div class='add'>+			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT		0x010e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts<br/>new file mode 100644<br/>index 000000000000..8a88c98ac05a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts</a></div><div class='hunk'>@@ -0,0 +1,892 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2022-2024 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Markus Niebel</div><div class='add'>+ * Author: Alexander Stein</div><div class='add'>+ */</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/net/ti-dp83867.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pwm/pwm.h&gt;</div><div class='add'>+#include &lt;dt-bindings/usb/pd.h&gt;</div><div class='add'>+#include "imx93-tqma9352.dtsi"</div><div class='add'>+</div><div class='add'>+/{</div><div class='add'>+	model = "TQ-Systems i.MX93 TQMa93xxLA on MBa93xxLA SBC";</div><div class='add'>+	compatible = "tq,imx93-tqma9352-mba93xxla",</div><div class='add'>+		     "tq,imx93-tqma9352", "fsl,imx93";</div><div class='add'>+	chassis-type = "embedded";</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;lpuart1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		eeprom0 = &amp;eeprom0;</div><div class='add'>+		ethernet0 = &amp;eqos;</div><div class='add'>+		ethernet1 = &amp;fec;</div><div class='add'>+		gpio0 = &amp;gpio1;</div><div class='add'>+		gpio1 = &amp;gpio2;</div><div class='add'>+		gpio2 = &amp;gpio3;</div><div class='add'>+		gpio3 = &amp;gpio4;</div><div class='add'>+		i2c0 = &amp;lpi2c1;</div><div class='add'>+		i2c1 = &amp;lpi2c2;</div><div class='add'>+		i2c2 = &amp;lpi2c3;</div><div class='add'>+		i2c3 = &amp;lpi2c4;</div><div class='add'>+		i2c4 = &amp;lpi2c5;</div><div class='add'>+		mmc0 = &amp;usdhc1;</div><div class='add'>+		mmc1 = &amp;usdhc2;</div><div class='add'>+		rtc0 = &amp;pcf85063;</div><div class='add'>+		rtc1 = &amp;bbnsm_rtc;</div><div class='add'>+		serial0 = &amp;lpuart1;</div><div class='add'>+		serial1 = &amp;lpuart2;</div><div class='add'>+		serial2 = &amp;lpuart3;</div><div class='add'>+		serial3 = &amp;lpuart4;</div><div class='add'>+		serial4 = &amp;lpuart5;</div><div class='add'>+		serial5 = &amp;lpuart6;</div><div class='add'>+		serial6 = &amp;lpuart7;</div><div class='add'>+		serial7 = &amp;lpuart8;</div><div class='add'>+		spi0 = &amp;lpspi1;</div><div class='add'>+		spi1 = &amp;lpspi2;</div><div class='add'>+		spi2 = &amp;lpspi3;</div><div class='add'>+		spi3 = &amp;lpspi4;</div><div class='add'>+		spi4 = &amp;lpspi5;</div><div class='add'>+		spi5 = &amp;lpspi6;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	backlight_lvds: backlight {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		pwms = &lt;&amp;tpm5 0 5000000 0&gt;;</div><div class='add'>+		brightness-levels = &lt;0 4 8 16 32 64 128 255&gt;;</div><div class='add'>+		default-brightness-level = &lt;7&gt;;</div><div class='add'>+		power-supply = &lt;&amp;reg_12v0&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;expander2 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_dp: clk-dp {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;26000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		autorepeat;</div><div class='add'>+</div><div class='add'>+		switch-a {</div><div class='add'>+			label = "switcha";</div><div class='add'>+			linux,code = &lt;BTN_0&gt;;</div><div class='add'>+			gpios = &lt;&amp;expander0 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		switch-b {</div><div class='add'>+			label = "switchb";</div><div class='add'>+			linux,code = &lt;BTN_1&gt;;</div><div class='add'>+			gpios = &lt;&amp;expander0 7 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			gpios = &lt;&amp;expander2 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "default-on";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-2 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_AMBER&gt;;</div><div class='add'>+			function = LED_FUNCTION_HEARTBEAT;</div><div class='add'>+			gpios = &lt;&amp;expander2 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	iio-hwmon {</div><div class='add'>+		compatible = "iio-hwmon";</div><div class='add'>+		io-channels = &lt;&amp;adc1 0&gt;, &lt;&amp;adc1 1&gt;, &lt;&amp;adc1 2&gt;, &lt;&amp;adc1 3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3v3: regulator-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "V_3V3_MB";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3v8: regulator-3v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "V_3V8";</div><div class='add'>+		regulator-min-microvolt = &lt;3800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3800000&gt;;</div><div class='add'>+		gpio = &lt;&amp;expander0 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		/* TODO: this is supply for IOT module */</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_5v0: regulator-5v0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "V_5V0_MB";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_12v0: regulator-12v0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "V_12V";</div><div class='add'>+		regulator-min-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;12000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;expander1 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;adc1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eqos {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_eqos&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy_eqos&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy_eqos: ethernet-phy@0 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_eqos_phy&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+			interrupts = &lt;26 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;expander1 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;500000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;50000&gt;;</div><div class='add'>+			enet-phy-lane-no-swap;</div><div class='add'>+			ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_2_25_NS&gt;;</div><div class='add'>+			ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_2_25_NS&gt;;</div><div class='add'>+			ti,fifo-depth = &lt;DP83867_PHYCR_FIFO_DEPTH_4_B_NIB&gt;;</div><div class='add'>+			ti,dp83867-rxctrl-strap-quirk;</div><div class='add'>+			ti,clk-output-sel = &lt;DP83867_CLK_O_SEL_OFF&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy_fec&gt;;</div><div class='add'>+	fsl,magic-packet;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;5000000&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy_fec: ethernet-phy@0 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_fec_phy&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+			interrupts = &lt;27 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;expander1 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;500000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;50000&gt;;</div><div class='add'>+			enet-phy-lane-no-swap;</div><div class='add'>+			ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_2_25_NS&gt;;</div><div class='add'>+			ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_2_25_NS&gt;;</div><div class='add'>+			ti,fifo-depth = &lt;DP83867_PHYCR_FIFO_DEPTH_4_B_NIB&gt;;</div><div class='add'>+			ti,dp83867-rxctrl-strap-quirk;</div><div class='add'>+			ti,clk-output-sel = &lt;DP83867_CLK_O_SEL_OFF&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan1&gt;;</div><div class='add'>+	xceiver-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan2&gt;;</div><div class='add'>+	xceiver-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		/* 00 */ "", "", "USB_C_ALERT#", "PMIC_IRQ#",</div><div class='add'>+		/* 04 */ "", "", "", "",</div><div class='add'>+		/* 08 */ "", "", "", "BM2_TEMP_EVENT_MOD#",</div><div class='add'>+		/* 12 */ "PEX_INT#", "", "RTC_EVENT#", "",</div><div class='add'>+		/* 16 */ "", "", "", "",</div><div class='add'>+		/* 20 */ "", "", "", "",</div><div class='add'>+		/* 24 */ "", "", "", "",</div><div class='add'>+		/* 28 */ "", "", "", "";</div><div class='add'>+</div><div class='add'>+	expander-irq-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		input;</div><div class='add'>+		line-name = "PEX_INT#";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rtc-irq-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;14 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		input;</div><div class='add'>+		line-name = "RTC_EVENT#";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio2&gt;;</div><div class='add'>+</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		/* 00 */ "", "", "", "",</div><div class='add'>+		/* 04 */ "", "", "", "AFE_RESET#",</div><div class='add'>+		/* 08 */ "AFE_SYNC", "AFE_DRDY", "MIPI_CSI_TRIGGER", "MIPI_CSI_SYNC",</div><div class='add'>+		/* 12 */ "", "", "", "",</div><div class='add'>+		/* 16 */ "X1_19", "X1_29", "X1_25", "X1_21",</div><div class='add'>+		/* 20 */ "X1_23", "X1_17", "", "",</div><div class='add'>+		/* 24 */ "AFE_INT#", "", "X1_15", "",</div><div class='add'>+		/* 28 */ "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio3 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		/* 00 */ "SD2_CD#", "", "", "",</div><div class='add'>+		/* 04 */ "", "", "", "SD2_RST#",</div><div class='add'>+		/* 08 */ "", "", "", "",</div><div class='add'>+		/* 12 */ "", "", "", "",</div><div class='add'>+		/* 16 */ "", "", "", "",</div><div class='add'>+		/* 20 */ "", "", "", "",</div><div class='add'>+		/* 24 */ "", "", "ENET1_INT#", "ENET2_INT#",</div><div class='add'>+		/* 28 */ "", "", "", "";</div><div class='add'>+</div><div class='add'>+	ethphy-eqos-irq-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;26 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		input;</div><div class='add'>+		line-name = "ENET1_INT#";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ethphy-fec-irq-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;27 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		input;</div><div class='add'>+		line-name = "ENET2_INT#";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		/* 00 */ "", "", "", "",</div><div class='add'>+		/* 04 */ "", "", "", "",</div><div class='add'>+		/* 08 */ "", "", "", "",</div><div class='add'>+		/* 12 */ "", "", "", "",</div><div class='add'>+		/* 16 */ "", "", "", "",</div><div class='add'>+		/* 20 */ "", "", "", "",</div><div class='add'>+		/* 24 */ "", "", "", "",</div><div class='add'>+		/* 28 */ "", "DP_INT", "", "";</div><div class='add'>+</div><div class='add'>+	dp-int-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;29 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		input;</div><div class='add'>+		line-name = "DP_INT";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c3 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_lpi2c3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	temperature-sensor@1c {</div><div class='add'>+		compatible = "nxp,se97b", "jedec,jc-42.4-temp";</div><div class='add'>+		reg = &lt;0x1c&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ptn5110: usb-typec@50 {</div><div class='add'>+		compatible = "nxp,ptn5110", "tcpci";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_typec&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;2 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+</div><div class='add'>+		connector {</div><div class='add'>+			compatible = "usb-c-connector";</div><div class='add'>+			label = "X17";</div><div class='add'>+			power-role = "dual";</div><div class='add'>+			data-role = "dual";</div><div class='add'>+			try-power-role = "sink";</div><div class='add'>+			typec-power-opmode = "default";</div><div class='add'>+			pd-disable;</div><div class='add'>+			self-powered;</div><div class='add'>+</div><div class='add'>+			port {</div><div class='add'>+				typec_con_hs: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;typec_hs&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom2: eeprom@54 {</div><div class='add'>+		compatible = "nxp,se97b", "atmel,24c02";</div><div class='add'>+		reg = &lt;0x54&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	expander0: gpio@70 {</div><div class='add'>+		compatible = "nxp,pca9538";</div><div class='add'>+		reg = &lt;0x70&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pexp_irq&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;12 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+		gpio-line-names = "3V8_EN", "",</div><div class='add'>+				  "", "IOT_PWRKEY",</div><div class='add'>+				  "IOT_RESET", "IOT_W_DISABLE",</div><div class='add'>+				  "BUTTON_A#", "BUTTON_B#";</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Controls the IOT W_DISABLE pin which is low active</div><div class='add'>+		 * as disable signal but inverted as seen from the CPU.</div><div class='add'>+		 * The output-low states, the signal is</div><div class='add'>+		 * inactive, e.g. not disabled</div><div class='add'>+		 */</div><div class='add'>+		iot_wdisable_hog: iot-wdisable-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+			line-name = "IOT_W_DISABLE";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	expander1: gpio@71 {</div><div class='add'>+		compatible = "nxp,pca9538";</div><div class='add'>+		reg = &lt;0x71&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+		gpio-line-names = "ENET1_RESET#", "ENET2_RESET#",</div><div class='add'>+				  "USB_RESET#", "",</div><div class='add'>+				  "WLAN_PD#", "WLAN_W_DISABLE#",</div><div class='add'>+				  "WLAN_PERST#", "12V_EN";</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Controls the WiFi card PD pin which is low active</div><div class='add'>+		 * as power down signal. The output-low states, the signal</div><div class='add'>+		 * is inactive, e.g. not power down</div><div class='add'>+		 */</div><div class='add'>+		wlan-pd-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+			line-name = "WLAN_PD#";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Controls the WiFi card disable pin which is low active</div><div class='add'>+		 * as disable signal. The output-low states, the signal</div><div class='add'>+		 * is inactive, e.g. not disabled</div><div class='add'>+		 */</div><div class='add'>+		wlan-wdisable-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+			line-name = "WLAN_W_DISABLE#";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Controls the WiFi card reset pin which is low active</div><div class='add'>+		 * as reset signal. The output-low states, the signal</div><div class='add'>+		 * is inactive, e.g. not in reset</div><div class='add'>+		 */</div><div class='add'>+		wlan-perst-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+			line-name = "WLAN_PERST#";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	expander2: gpio@72 {</div><div class='add'>+		compatible = "nxp,pca9538";</div><div class='add'>+		reg = &lt;0x72&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+		gpio-line-names = "LCD_RESET#", "LCD_PWR_EN",</div><div class='add'>+				  "LCD_BLT_EN", "DP_EN",</div><div class='add'>+				  "MIPI_CSI_EN", "MIPI_CSI_RST#",</div><div class='add'>+				  "USER_LED1", "USER_LED2";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c5 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c5&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_lpi2c5&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	dp_bridge: dp-bridge@f {</div><div class='add'>+		compatible = "toshiba,tc9595", "toshiba,tc358767";</div><div class='add'>+		reg = &lt;0x0f&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_tc9595&gt;;</div><div class='add'>+		clock-names = "ref";</div><div class='add'>+		clocks = &lt;&amp;clk_dp&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;expander2 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;29 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+		toshiba,hpd-pin = &lt;0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				dp_dsi_in: endpoint {</div><div class='add'>+					data-lanes = &lt;1 2 3 4&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpspi6 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpspi6&gt;, &lt;&amp;pinctrl_lpspi6_cs&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio2 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	linux,rs485-enabled-at-boot-time;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* disabled per default, console for M33 */</div><div class='add'>+&amp;lpuart3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart6 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart6&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart8 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart8&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcf85063 {</div><div class='add'>+	/* RTC_EVENT# from SoM is connected on mainboard */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcf85063&gt;;</div><div class='add'>+	interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+	interrupts = &lt;14 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;se97_som {</div><div class='add'>+	/* TEMP_EVENT# from SoM is connected on mainboard */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_temp_sensor_som&gt;;</div><div class='add'>+	interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+	interrupts = &lt;11 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tpm5 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_tpm5&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	hnp-disable;</div><div class='add'>+	srp-disable;</div><div class='add'>+	adp-disable;</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	disable-over-current;</div><div class='add'>+	samsung,picophy-pre-emp-curr-control = &lt;3&gt;;</div><div class='add'>+	samsung,picophy-dc-vol-level-adjust = &lt;7&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	port {</div><div class='add'>+		typec_hs: endpoint {</div><div class='add'>+			remote-endpoint = &lt;&amp;typec_con_hs&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg2 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	disable-over-current;</div><div class='add'>+	samsung,picophy-pre-emp-curr-control = &lt;3&gt;;</div><div class='add'>+	samsung,picophy-dc-vol-level-adjust = &lt;7&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	hub_2_0: usb-hub@1 {</div><div class='add'>+		compatible = "usb424,2517";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;expander1 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2_hs&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_uhs&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_uhs&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio3 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	no-sdio;</div><div class='add'>+	no-mmc;</div><div class='add'>+	disable-wp;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_afe: afegrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* FSEL_2 | DSE X4 */</div><div class='add'>+			MX93_PAD_GPIO_IO07__GPIO2_IO07			0x011e</div><div class='add'>+			/* PD | FSEL_2 | DSE X4 */</div><div class='add'>+			MX93_PAD_GPIO_IO08__GPIO2_IO08			0x051e</div><div class='add'>+			/* HYS | PD */</div><div class='add'>+			MX93_PAD_GPIO_IO09__GPIO2_IO09			0x1400</div><div class='add'>+			/* HYS */</div><div class='add'>+			MX93_PAD_GPIO_IO24__GPIO2_IO24			0x1000</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_eqos: eqosgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* PD | FSEL_2 | DSE X4 */</div><div class='add'>+			MX93_PAD_ENET1_MDC__ENET_QOS_MDC			0x51e</div><div class='add'>+			/* SION | HYS | FSEL_2 | DSE X4 */</div><div class='add'>+			MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO			0x4000111e</div><div class='add'>+			/* HYS | FSEL_0 | DSE no drive */</div><div class='add'>+			MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0			0x1000</div><div class='add'>+			MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1			0x1000</div><div class='add'>+			MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2			0x1000</div><div class='add'>+			MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3			0x1000</div><div class='add'>+			MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x1000</div><div class='add'>+			/* HYS | PD | FSEL_0 | DSE no drive */</div><div class='add'>+			MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x1400</div><div class='add'>+			/* PD | FSEL_2 | DSE X4 */</div><div class='add'>+			MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0			0x51e</div><div class='add'>+			MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1			0x51e</div><div class='add'>+			MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2			0x51e</div><div class='add'>+			MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3			0x51e</div><div class='add'>+			MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x51e</div><div class='add'>+			/* PD | FSEL_3 | DSE X3 */</div><div class='add'>+			MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x58e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_eqos_phy: eqosphygrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* HYS | FSEL_0 | DSE no drive */</div><div class='add'>+			MX93_PAD_CCM_CLKO1__GPIO3_IO26			0x1000</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec: fecgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* PD | FSEL_2 | DSE X4 */</div><div class='add'>+			MX93_PAD_ENET2_MDC__ENET1_MDC			0x51e</div><div class='add'>+			/* SION | HYS | FSEL_2 | DSE X4 */</div><div class='add'>+			MX93_PAD_ENET2_MDIO__ENET1_MDIO			0x4000111e</div><div class='add'>+			/* HYS | FSEL_0 | DSE no drive */</div><div class='add'>+			MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0		0x1000</div><div class='add'>+			MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1		0x1000</div><div class='add'>+			MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2		0x1000</div><div class='add'>+			MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3		0x1000</div><div class='add'>+			MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL	0x1000</div><div class='add'>+			/* HYS | PD | FSEL_0 | DSE no drive */</div><div class='add'>+			MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC		0x1400</div><div class='add'>+			/* PD | FSEL_2 | DSE X4 */</div><div class='add'>+			MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0		0x51e</div><div class='add'>+			MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1		0x51e</div><div class='add'>+			MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2		0x51e</div><div class='add'>+			MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3		0x51e</div><div class='add'>+			MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL	0x51e</div><div class='add'>+			/* PD | FSEL_3 | DSE X3 */</div><div class='add'>+			MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC		0x58e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec_phy: fecphygrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* HYS | FSEL_0 | DSE no drive */</div><div class='add'>+			MX93_PAD_CCM_CLKO2__GPIO3_IO27			0x1000</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan1: flexcan1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* HYS | PU | FSEL_0 | DSE no drive */</div><div class='add'>+			MX93_PAD_PDM_BIT_STREAM0__CAN1_RX		0x1200</div><div class='add'>+			/* PU | FSEL_3 | DSE X4 */</div><div class='add'>+			MX93_PAD_PDM_CLK__CAN1_TX			0x039e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan2: flexcan2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* HYS | PU | FSEL_0 | DSE no drive */</div><div class='add'>+			MX93_PAD_GPIO_IO27__CAN2_RX			0x1200</div><div class='add'>+			/* PU | FSEL_3 | DSE X4 */</div><div class='add'>+			MX93_PAD_GPIO_IO25__CAN2_TX			0x039e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio2: gpio2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* HYS | PD | FSEL_2 | DSE X4 */</div><div class='add'>+			MX93_PAD_GPIO_IO16__GPIO2_IO16			0x151e</div><div class='add'>+			MX93_PAD_GPIO_IO17__GPIO2_IO17			0x151e</div><div class='add'>+			MX93_PAD_GPIO_IO18__GPIO2_IO18			0x151e</div><div class='add'>+			MX93_PAD_GPIO_IO19__GPIO2_IO19			0x151e</div><div class='add'>+			MX93_PAD_GPIO_IO20__GPIO2_IO20			0x151e</div><div class='add'>+			MX93_PAD_GPIO_IO21__GPIO2_IO21			0x151e</div><div class='add'>+			MX93_PAD_GPIO_IO26__GPIO2_IO26			0x151e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_jtag: jtaggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK		0x051e</div><div class='add'>+			MX93_PAD_DAP_TDI__JTAG_MUX_TDI			0x1200</div><div class='add'>+			MX93_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO		0x031e</div><div class='add'>+			MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS		0x1200</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c3: lpi2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* SION | HYS | OD | FSEL_3 | DSE X4 */</div><div class='add'>+			MX93_PAD_GPIO_IO28__LPI2C3_SDA			0x4000199e</div><div class='add'>+			MX93_PAD_GPIO_IO29__LPI2C3_SCL			0x4000199e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c5: lpi2c5grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* SION | HYS | OD | FSEL_3 | DSE X4 */</div><div class='add'>+			MX93_PAD_GPIO_IO22__LPI2C5_SDA			0x4000199e</div><div class='add'>+			MX93_PAD_GPIO_IO23__LPI2C5_SCL			0x4000199e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpspi6: lpspi6grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* HYS | PD | FSEL_0 | DSE no drive */</div><div class='add'>+			MX93_PAD_GPIO_IO01__LPSPI6_SIN			0x1400</div><div class='add'>+			/* PD | FSEL_2 | DSE X4 */</div><div class='add'>+			MX93_PAD_GPIO_IO02__LPSPI6_SOUT			0x051e</div><div class='add'>+			MX93_PAD_GPIO_IO03__LPSPI6_SCK			0x051e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpspi6_cs: lpspi6csgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* FSEL_2 | DSE X4 */</div><div class='add'>+			MX93_PAD_GPIO_IO00__GPIO2_IO00			0x011e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_mipi_csi: mipicsigrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3		0x051e /* MCLK */</div><div class='add'>+			MX93_PAD_GPIO_IO10__GPIO2_IO10			0x051e /* TRIGGER */</div><div class='add'>+			MX93_PAD_GPIO_IO11__GPIO2_IO11			0x1400 /* SYNC */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcf85063: pcf85063grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* HYS | FSEL_0 | No DSE */</div><div class='add'>+			MX93_PAD_SAI1_RXD0__GPIO1_IO14			0x1000</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pexp_irq: pexpirqgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* HYS | FSEL_0 | No DSE */</div><div class='add'>+			MX93_PAD_SAI1_TXC__GPIO1_IO12			0x1000</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_tc9595: tc9595-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* HYS | PD | FSEL_0 | no DSE */</div><div class='add'>+			MX93_PAD_CCM_CLKO4__GPIO4_IO29			0x1400</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_temp_sensor_som: tempsensorsomgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* HYS | FSEL_0 | no DSE */</div><div class='add'>+			MX93_PAD_SAI1_TXFS__GPIO1_IO11			0x1000</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_tpm5: tpm5grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_GPIO_IO06__TPM5_CH0			0x57e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_typec: typecgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* HYS | FSEL_0 | No DSE */</div><div class='add'>+			MX93_PAD_I2C2_SCL__GPIO1_IO02			0x1000</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* HYS | FSEL_0 | No DSE */</div><div class='add'>+			MX93_PAD_UART1_RXD__LPUART1_RX			0x1000</div><div class='add'>+			/* FSEL_2 | DSE X4 */</div><div class='add'>+			MX93_PAD_UART1_TXD__LPUART1_TX			0x011e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* HYS | FSEL_0 | No DSE */</div><div class='add'>+			MX93_PAD_UART2_RXD__LPUART2_RX			0x1000</div><div class='add'>+			/* FSEL_2 | DSE X4 */</div><div class='add'>+			MX93_PAD_UART2_TXD__LPUART2_TX			0x011e</div><div class='add'>+			MX93_PAD_SAI1_TXD0__LPUART2_RTS_B		0x011e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart3: uart3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* HYS | FSEL_0 | No DSE */</div><div class='add'>+			MX93_PAD_GPIO_IO15__LPUART3_RX			0x1000</div><div class='add'>+			/* FSEL_2 | DSE X4 */</div><div class='add'>+			MX93_PAD_GPIO_IO14__LPUART3_TX			0x011e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart6: uart6grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* HYS | FSEL_0 | No DSE */</div><div class='add'>+			MX93_PAD_GPIO_IO05__LPUART6_RX			0x1000</div><div class='add'>+			/* FSEL_2 | DSE X4 */</div><div class='add'>+			MX93_PAD_GPIO_IO04__LPUART6_TX			0x011e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart8: uart8grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* HYS | FSEL_0 | No DSE */</div><div class='add'>+			MX93_PAD_GPIO_IO13__LPUART8_RX			0x1000</div><div class='add'>+			/* FSEL_2 | DSE X4 */</div><div class='add'>+			MX93_PAD_GPIO_IO12__LPUART8_TX			0x011e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* HYS | FSEL_0 | No DSE */</div><div class='add'>+			MX93_PAD_SD2_CD_B__GPIO3_IO00			0x1000</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* enable SION for data and cmd pad due to ERR052021 */</div><div class='add'>+	pinctrl_usdhc2_hs: usdhc2hsgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* PD | FSEL_3 | DSE X5 */</div><div class='add'>+			MX93_PAD_SD2_CLK__USDHC2_CLK			0x05be</div><div class='add'>+			/* HYS | PU | FSEL_3 | DSE X4 */</div><div class='add'>+			MX93_PAD_SD2_CMD__USDHC2_CMD			0x4000139e</div><div class='add'>+			/* HYS | PU | FSEL_3 | DSE X3 */</div><div class='add'>+			MX93_PAD_SD2_DATA0__USDHC2_DATA0		0x4000138e</div><div class='add'>+			MX93_PAD_SD2_DATA1__USDHC2_DATA1		0x4000138e</div><div class='add'>+			MX93_PAD_SD2_DATA2__USDHC2_DATA2		0x4000138e</div><div class='add'>+			MX93_PAD_SD2_DATA3__USDHC2_DATA3		0x4000138e</div><div class='add'>+			/* FSEL_2 | DSE X3 */</div><div class='add'>+			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT		0x010e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* enable SION for data and cmd pad due to ERR052021 */</div><div class='add'>+	pinctrl_usdhc2_uhs: usdhc2uhsgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* PD | FSEL_3 | DSE X6 */</div><div class='add'>+			MX93_PAD_SD2_CLK__USDHC2_CLK			0x05fe</div><div class='add'>+			/* HYS | PU | FSEL_3 | DSE X4 */</div><div class='add'>+			MX93_PAD_SD2_CMD__USDHC2_CMD			0x4000139e</div><div class='add'>+			MX93_PAD_SD2_DATA0__USDHC2_DATA0		0x4000139e</div><div class='add'>+			MX93_PAD_SD2_DATA1__USDHC2_DATA1		0x4000139e</div><div class='add'>+			MX93_PAD_SD2_DATA2__USDHC2_DATA2		0x4000139e</div><div class='add'>+			MX93_PAD_SD2_DATA3__USDHC2_DATA3		0x4000139e</div><div class='add'>+			/* FSEL_2 | DSE X3 */</div><div class='add'>+			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT		0x010e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi b/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi<br/>new file mode 100644<br/>index 000000000000..3a23e2eb9feb<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi</a></div><div class='hunk'>@@ -0,0 +1,298 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2022-2025 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Markus Niebel</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "imx93.dtsi"</div><div class='add'>+</div><div class='add'>+/{</div><div class='add'>+	model = "TQ-Systems i.MX93 TQMa93xxLA/TQMa93xxCA SOM";</div><div class='add'>+	compatible = "tq,imx93-tqma9352", "fsl,imx93";</div><div class='add'>+</div><div class='add'>+	memory@80000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		/* our minimum RAM config will be 1024 MiB */</div><div class='add'>+		reg = &lt;0x00000000 0x80000000 0 0x40000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		linux,cma {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reusable;</div><div class='add'>+			alloc-ranges = &lt;0 0x80000000 0 0x40000000&gt;;</div><div class='add'>+			size = &lt;0 0x10000000&gt;;</div><div class='add'>+			linux,cma-default;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SD2 RST# via PMIC SW_EN */</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usdhc2_vmmc&gt;;</div><div class='add'>+		regulator-name = "VSD_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;buck4&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio3 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;adc1 {</div><div class='add'>+	vref-supply = &lt;&amp;buck5&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexspi1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexspi1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash0: flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		/*</div><div class='add'>+		 * no DQS, RXCLKSRC internal loop back, max 66 MHz</div><div class='add'>+		 * clk framework uses CLK_DIVIDER_ROUND_CLOSEST</div><div class='add'>+		 * selected value together with root from</div><div class='add'>+		 * IMX93_CLK_SYS_PLL_PFD1 @ 800.000.000 Hz helps to</div><div class='add'>+		 * respect the maximum value.</div><div class='add'>+		 */</div><div class='add'>+		spi-max-frequency = &lt;62000000&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;4&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;buck5&gt;;</div><div class='add'>+</div><div class='add'>+		partitions {</div><div class='add'>+			compatible = "fixed-partitions";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c1 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_lpi2c1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	se97_som: temperature-sensor@1b {</div><div class='add'>+		compatible = "nxp,se97b", "jedec,jc-42.4-temp";</div><div class='add'>+		reg = &lt;0x1b&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pca9451a: pmic@25 {</div><div class='add'>+		compatible = "nxp,pca9451a";</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pca9451&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;3 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			/* V_0V8_SOC - hw developer guide: 0.75 .. 0.9 */</div><div class='add'>+			buck1: BUCK1 {</div><div class='add'>+				regulator-name = "BUCK1";</div><div class='add'>+				regulator-min-microvolt = &lt;750000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* V_DDRQ - 0.6 V for LPDDR4X */</div><div class='add'>+			buck2: BUCK2 {</div><div class='add'>+				regulator-name = "BUCK2";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* V_3V3 - EEPROM, RTC, ... */</div><div class='add'>+			buck4: BUCK4 {</div><div class='add'>+				regulator-name = "BUCK4";</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* V_1V8 - SPI NOR, eMMC, RAM VDD1... */</div><div class='add'>+			buck5: BUCK5 {</div><div class='add'>+				regulator-name = "BUCK5";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* V_1V1 - RAM VDD2*/</div><div class='add'>+			buck6: BUCK6 {</div><div class='add'>+				regulator-name = "BUCK6";</div><div class='add'>+				regulator-min-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* V_1V8_BBSM, fix 1.8 */</div><div class='add'>+			ldo1: LDO1 {</div><div class='add'>+				regulator-name = "LDO1";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* V_0V8_ANA */</div><div class='add'>+			ldo4: LDO4 {</div><div class='add'>+				regulator-name = "LDO4";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* V_SD2 - 3.3/1.8V USDHC2 io Voltage */</div><div class='add'>+			ldo5: LDO5 {</div><div class='add'>+				regulator-name = "LDO5";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcf85063: rtc@51 {</div><div class='add'>+		compatible = "nxp,pcf85063a";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		quartz-load-femtofarads = &lt;7000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom0: eeprom@53 {</div><div class='add'>+		compatible = "nxp,se97b", "atmel,24c02";</div><div class='add'>+		reg = &lt;0x53&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+		read-only;</div><div class='add'>+		vcc-supply = &lt;&amp;buck4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom1: eeprom@57 {</div><div class='add'>+		compatible = "atmel,24c64";</div><div class='add'>+		reg = &lt;0x57&gt;;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;buck4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* protectable identification memory (part of M24C64-D @57) */</div><div class='add'>+	eeprom@5f {</div><div class='add'>+		compatible = "atmel,24c64d-wl";</div><div class='add'>+		reg = &lt;0x5f&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;buck4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	imu@6a {</div><div class='add'>+		compatible = "st,ism330dhcx";</div><div class='add'>+		reg = &lt;0x6a&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;buck4&gt;;</div><div class='add'>+		vddio-supply = &lt;&amp;buck4&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;buck4&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;buck5&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	no-sdio;</div><div class='add'>+	no-sd;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_wdog&gt;;</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_flexspi1: flexspi1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* FSEL 3  | DSE X6 */</div><div class='add'>+			MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B	0x01fe</div><div class='add'>+			MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK	0x01fe</div><div class='add'>+			/* HYS | PU | FSEL 3  | DSE X6 */</div><div class='add'>+			MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00	0x13fe</div><div class='add'>+			MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01	0x13fe</div><div class='add'>+			/* HYS | FSEL 3  | DSE X6 (external PU) */</div><div class='add'>+			MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02	0x11fe</div><div class='add'>+			MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03	0x11fe</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c1: lpi2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* SION | OD | FSEL 3 | DSE X4 */</div><div class='add'>+			MX93_PAD_I2C1_SCL__LPI2C1_SCL		0x4000199e</div><div class='add'>+			MX93_PAD_I2C1_SDA__LPI2C1_SDA		0x4000199e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pca9451: pca9451grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* HYS | PU */</div><div class='add'>+			MX93_PAD_I2C2_SDA__GPIO1_IO03		0x1200</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* FSEL 2 | DSE X2 */</div><div class='add'>+			MX93_PAD_SD2_RESET_B__GPIO3_IO07	0x106</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* enable SION for data and cmd pad due to ERR052021 */</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* PD | FSEL 3 | DSE X5 */</div><div class='add'>+			MX93_PAD_SD1_CLK__USDHC1_CLK		0x5be</div><div class='add'>+			/* HYS | FSEL 0 | no drive */</div><div class='add'>+			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x1000</div><div class='add'>+			/* HYS | FSEL 3 | X5 */</div><div class='add'>+			MX93_PAD_SD1_CMD__USDHC1_CMD		0x400011be</div><div class='add'>+			/* HYS | FSEL 3 | X4 */</div><div class='add'>+			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x4000119e</div><div class='add'>+			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x4000119e</div><div class='add'>+			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x4000119e</div><div class='add'>+			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x4000119e</div><div class='add'>+			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x4000119e</div><div class='add'>+			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x4000119e</div><div class='add'>+			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x4000119e</div><div class='add'>+			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x4000119e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_wdog: wdoggrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			/* PU | FSEL 1 | DSE X4 */</div><div class='add'>+			MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY	0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts<br/>new file mode 100644<br/>index 000000000000..c789c1f24bdc<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts</a></div><div class='hunk'>@@ -0,0 +1,368 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021 NXP</div><div class='add'>+ * Copyright 2023 Variscite Ltd.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include "imx93-var-som.dtsi"</div><div class='add'>+</div><div class='add'>+/{</div><div class='add'>+	model = "Variscite VAR-SOM-MX93 on Symphony evaluation board";</div><div class='add'>+	compatible = "variscite,var-som-mx93-symphony",</div><div class='add'>+		     "variscite,var-som-mx93", "fsl,imx93";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;eqos;</div><div class='add'>+		ethernet1 = &amp;fec;</div><div class='add'>+		gpio0 = &amp;gpio1;</div><div class='add'>+		gpio1 = &amp;gpio2;</div><div class='add'>+		gpio2 = &amp;gpio3;</div><div class='add'>+		i2c0 = &amp;lpi2c1;</div><div class='add'>+		i2c1 = &amp;lpi2c2;</div><div class='add'>+		i2c2 = &amp;lpi2c3;</div><div class='add'>+		i2c3 = &amp;lpi2c4;</div><div class='add'>+		i2c4 = &amp;lpi2c5;</div><div class='add'>+		mmc0 = &amp;usdhc1;</div><div class='add'>+		mmc1 = &amp;usdhc2;</div><div class='add'>+		serial0 = &amp;lpuart1;</div><div class='add'>+		serial1 = &amp;lpuart2;</div><div class='add'>+		serial2 = &amp;lpuart3;</div><div class='add'>+		serial3 = &amp;lpuart4;</div><div class='add'>+		serial4 = &amp;lpuart5;</div><div class='add'>+		serial5 = &amp;lpuart6;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;lpuart1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Needed only for Symphony &lt;= v1.5</div><div class='add'>+	 */</div><div class='add'>+	reg_fec_phy: regulator-fec-phy {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "fec-phy";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-enable-ramp-delay = &lt;20000&gt;;</div><div class='add'>+		gpio = &lt;&amp;pca9534 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usdhc2_vmmc&gt;;</div><div class='add'>+		regulator-name = "VSD_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio2 18 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		off-on-delay-us = &lt;20000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vref_1v8: regulator-adc-vref {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vref_1v8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		ethosu_mem: ethosu-region@88000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reusable;</div><div class='add'>+			reg = &lt;0x0 0x88000000 0x0 0x8000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev0vring0: vdev0vring0@87ee0000 {</div><div class='add'>+			reg = &lt;0 0x87ee0000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev0vring1: vdev0vring1@87ee8000 {</div><div class='add'>+			reg = &lt;0 0x87ee8000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev1vring0: vdev1vring0@87ef0000 {</div><div class='add'>+			reg = &lt;0 0x87ef0000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev1vring1: vdev1vring1@87ef8000 {</div><div class='add'>+			reg = &lt;0 0x87ef8000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rsc_table: rsc-table@2021f000 {</div><div class='add'>+			reg = &lt;0 0x2021f000 0 0x1000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdevbuffer: vdevbuffer@87f00000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x87f00000 0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ele_reserved: ele-reserved@87de0000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x87de0000 0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		key-back {</div><div class='add'>+			label = "Back";</div><div class='add'>+			gpios = &lt;&amp;pca9534 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_BACK&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-home {</div><div class='add'>+			label = "Home";</div><div class='add'>+			gpios = &lt;&amp;pca9534 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_HOME&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-menu {</div><div class='add'>+			label = "Menu";</div><div class='add'>+			gpios = &lt;&amp;pca9534 3 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_MENU&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			gpios = &lt;&amp;pca9534 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Use external instead of internal RTC*/</div><div class='add'>+&amp;bbnsm_rtc {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eqos {</div><div class='add'>+	mdio {</div><div class='add'>+		ethphy1: ethernet-phy@5 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;5&gt;;</div><div class='add'>+			qca,disable-smarteee;</div><div class='add'>+			eee-broken-1000t;</div><div class='add'>+			reset-gpios = &lt;&amp;pca9534 5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;10000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;20000&gt;;</div><div class='add'>+			vddio-supply = &lt;&amp;vddio1&gt;;</div><div class='add'>+</div><div class='add'>+			vddio1: vddio-regulator {</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec&gt;;</div><div class='add'>+	phy-mode = "rgmii";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy1&gt;;</div><div class='add'>+	phy-supply = &lt;&amp;reg_fec_phy&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c1 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_lpi2c1_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_lpi2c1_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio1 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio1 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* DS1337 RTC module */</div><div class='add'>+	rtc@68 {</div><div class='add'>+		compatible = "dallas,ds1337";</div><div class='add'>+		reg = &lt;0x68&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c5 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c5&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_lpi2c5_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_lpi2c5_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio2 23 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio2 22 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pca9534: gpio@20 {</div><div class='add'>+		compatible = "nxp,pca9534";</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pca9534&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+		interrupts = &lt;26 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		wakeup-source;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Console */</div><div class='add'>+&amp;lpuart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* J18.7, J18.9 */</div><div class='add'>+&amp;lpuart6 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart6&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SD */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio3 00 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+	no-sdio;</div><div class='add'>+	no-mmc;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Watchdog */</div><div class='add'>+&amp;wdog3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_fec: fecgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0		0x57e</div><div class='add'>+			MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1		0x57e</div><div class='add'>+			MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2		0x57e</div><div class='add'>+			MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3		0x57e</div><div class='add'>+			MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC		0x5fe</div><div class='add'>+			MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL	0x57e</div><div class='add'>+			MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0		0x57e</div><div class='add'>+			MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1		0x57e</div><div class='add'>+			MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2		0x57e</div><div class='add'>+			MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3		0x57e</div><div class='add'>+			MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC		0x5fe</div><div class='add'>+			MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL	0x57e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan1: flexcan1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_PDM_CLK__CAN1_TX                       0x139e</div><div class='add'>+			MX93_PAD_PDM_BIT_STREAM0__CAN1_RX               0x139e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c1: lpi2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_I2C1_SCL__LPI2C1_SCL			0x40000b9e</div><div class='add'>+			MX93_PAD_I2C1_SDA__LPI2C1_SDA			0x40000b9e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c1_gpio: lpi2c1gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_I2C1_SCL__GPIO1_IO00			0x31e</div><div class='add'>+			MX93_PAD_I2C1_SDA__GPIO1_IO01			0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c5: lpi2c5grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_GPIO_IO23__LPI2C5_SCL			0x40000b9e</div><div class='add'>+			MX93_PAD_GPIO_IO22__LPI2C5_SDA			0x40000b9e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c5_gpio: lpi2c5gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_GPIO_IO23__GPIO2_IO23			0x31e</div><div class='add'>+			MX93_PAD_GPIO_IO22__GPIO2_IO22			0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pca9534: pca9534grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_CCM_CLKO1__GPIO3_IO26		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_UART1_RXD__LPUART1_RX			0x31e</div><div class='add'>+			MX93_PAD_UART1_TXD__LPUART1_TX			0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart6: uart6grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_GPIO_IO05__LPUART6_RX			0x31e</div><div class='add'>+			MX93_PAD_GPIO_IO04__LPUART6_TX			0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_GPIO_IO18__GPIO2_IO18		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD2_CLK__USDHC2_CLK		0x15fe</div><div class='add'>+			MX93_PAD_SD2_CMD__USDHC2_CMD		0x13fe</div><div class='add'>+			MX93_PAD_SD2_DATA0__USDHC2_DATA0	0x13fe</div><div class='add'>+			MX93_PAD_SD2_DATA1__USDHC2_DATA1	0x13fe</div><div class='add'>+			MX93_PAD_SD2_DATA2__USDHC2_DATA2	0x13fe</div><div class='add'>+			MX93_PAD_SD2_DATA3__USDHC2_DATA3	0x13fe</div><div class='add'>+			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD2_CD_B__GPIO3_IO00		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx93-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-var-som.dtsi<br/>new file mode 100644<br/>index 000000000000..2dc8b18ae91e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx93-var-som.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx93-var-som.dtsi</a></div><div class='hunk'>@@ -0,0 +1,456 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 NXP</div><div class='add'>+ * Copyright 2023 Variscite Ltd.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx93.dtsi"</div><div class='add'>+</div><div class='add'>+/{</div><div class='add'>+	model = "Variscite VAR-SOM-MX93 module";</div><div class='add'>+	compatible = "variscite,var-som-mx93", "fsl,imx93";</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,bitclock-master = &lt;&amp;codec_dai&gt;;</div><div class='add'>+		simple-audio-card,format = "i2s";</div><div class='add'>+		simple-audio-card,frame-master = &lt;&amp;codec_dai&gt;;</div><div class='add'>+		simple-audio-card,name = "wm8904-audio";</div><div class='add'>+		simple-audio-card,routing =</div><div class='add'>+			"Headphone Jack", "HPOUTL",</div><div class='add'>+			"Headphone Jack", "HPOUTR",</div><div class='add'>+			"IN2L", "Line In Jack",</div><div class='add'>+			"IN2R", "Line In Jack",</div><div class='add'>+			"IN1L", "Microphone Jack",</div><div class='add'>+			"IN1R", "Microphone Jack";</div><div class='add'>+		simple-audio-card,widgets =</div><div class='add'>+			"Microphone", "Microphone Jack",</div><div class='add'>+			"Headphone", "Headphone Jack",</div><div class='add'>+			"Line", "Line In Jack";</div><div class='add'>+		simple-audio-card,mclk-fs = &lt;256&gt;;</div><div class='add'>+</div><div class='add'>+		codec_dai: simple-audio-card,codec {</div><div class='add'>+			sound-dai = &lt;&amp;wm8904&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;sai1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usdhc3_pwrseq: mmc-pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-simple";</div><div class='add'>+		post-power-on-delay-ms = &lt;100&gt;;</div><div class='add'>+		power-off-delay-us = &lt;10000&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio4 14 GPIO_ACTIVE_LOW&gt;,	/* WIFI_RESET */</div><div class='add'>+			      &lt;&amp;gpio3 7 GPIO_ACTIVE_LOW&gt;;	/* WIFI_PWR_EN */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eqos {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_eqos&gt;;</div><div class='add'>+	/*</div><div class='add'>+	 * The required RGMII TX and RX 2ns delays are implemented directly</div><div class='add'>+	 * in hardware via passive delay elements on the SOM PCB.</div><div class='add'>+	 * No delay configuration is needed in software via PHY driver.</div><div class='add'>+	 */</div><div class='add'>+	phy-mode = "rgmii";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	snps,clk-csr = &lt;5&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;1000000&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@0 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			eee-broken-1000t;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio1 7 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;10000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;100000&gt;;</div><div class='add'>+</div><div class='add'>+			leds {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				led@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					color = &lt;LED_COLOR_ID_YELLOW&gt;;</div><div class='add'>+					function = LED_FUNCTION_LAN;</div><div class='add'>+					linux,default-trigger = "netdev";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				led@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+					function = LED_FUNCTION_LAN;</div><div class='add'>+					linux,default-trigger = "netdev";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c3 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_lpi2c3_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_lpi2c3_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio2 29 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio2 28 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pmic@25 {</div><div class='add'>+		compatible = "nxp,pca9451a";</div><div class='add'>+		reg = &lt;0x25&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			buck1: BUCK1 {</div><div class='add'>+				regulator-name = "BUCK1";</div><div class='add'>+				regulator-min-microvolt = &lt;650000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2237500&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck2: BUCK2 {</div><div class='add'>+				regulator-name = "BUCK2";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2187500&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-ramp-delay = &lt;3125&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck4: BUCK4{</div><div class='add'>+				regulator-name = "BUCK4";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck5: BUCK5{</div><div class='add'>+				regulator-name = "BUCK5";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck6: BUCK6 {</div><div class='add'>+				regulator-name = "BUCK6";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo1: LDO1 {</div><div class='add'>+				regulator-name = "LDO1";</div><div class='add'>+				regulator-min-microvolt = &lt;1600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo4: LDO4 {</div><div class='add'>+				regulator-name = "LDO4";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo5: LDO5 {</div><div class='add'>+				regulator-name = "LDO5";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wm8904: audio-codec@1a {</div><div class='add'>+		compatible = "wlf,wm8904";</div><div class='add'>+		reg = &lt;0x1a&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX93_CLK_SAI1_GATE&gt;;</div><div class='add'>+		clock-names = "mclk";</div><div class='add'>+		AVDD-supply = &lt;&amp;buck5&gt;;</div><div class='add'>+		CPVDD-supply = &lt;&amp;buck5&gt;;</div><div class='add'>+		DBVDD-supply = &lt;&amp;buck4&gt;;</div><div class='add'>+		DCVDD-supply = &lt;&amp;buck5&gt;;</div><div class='add'>+		MICVDD-supply = &lt;&amp;buck5&gt;;</div><div class='add'>+		wlf,drc-cfg-names = "default", "peaklimiter", "tradition",</div><div class='add'>+				    "soft", "music";</div><div class='add'>+		/*</div><div class='add'>+		 * Config registers per name, respectively:</div><div class='add'>+		 * KNEE_IP = 0,   KNEE_OP = 0,     HI_COMP = 1,   LO_COMP = 1</div><div class='add'>+		 * KNEE_IP = -24, KNEE_OP = -6,    HI_COMP = 1/4, LO_COMP = 1</div><div class='add'>+		 * KNEE_IP = -42, KNEE_OP = -3,    HI_COMP = 0,   LO_COMP = 1</div><div class='add'>+		 * KNEE_IP = -45, KNEE_OP = -9,    HI_COMP = 1/8, LO_COMP = 1</div><div class='add'>+		 * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1</div><div class='add'>+		 */</div><div class='add'>+		wlf,drc-cfg-regs = /bits/ 16 &lt;0x01af 0x3248 0x0000 0x0000&gt;,</div><div class='add'>+				   /bits/ 16 &lt;0x04af 0x324b 0x0010 0x0408&gt;,</div><div class='add'>+				   /bits/ 16 &lt;0x04af 0x324b 0x0028 0x0704&gt;,</div><div class='add'>+				   /bits/ 16 &lt;0x04af 0x324b 0x0018 0x078c&gt;,</div><div class='add'>+				   /bits/ 16 &lt;0x04af 0x324b 0x0010 0x050e&gt;;</div><div class='add'>+		/* GPIO1 = DMIC_CLK, don't touch others */</div><div class='add'>+		wlf,gpio-cfg = &lt;0x0018&gt;, &lt;0xffff&gt;, &lt;0xffff&gt;, &lt;0xffff&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpspi8 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpspi8&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* Resistive touch controller */</div><div class='add'>+	ads7846: touchscreen@0 {</div><div class='add'>+		compatible = "ti,ads7846";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_restouch&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;29 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		spi-max-frequency = &lt;1000000&gt;;</div><div class='add'>+		pendown-gpio = &lt;&amp;gpio4 29 0&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;buck5&gt;;</div><div class='add'>+		ti,x-min = /bits/ 16 &lt;125&gt;;</div><div class='add'>+		ti,x-max = /bits/ 16 &lt;4008&gt;;</div><div class='add'>+		ti,y-min = /bits/ 16 &lt;282&gt;;</div><div class='add'>+		ti,y-max = /bits/ 16 &lt;3864&gt;;</div><div class='add'>+		ti,x-plate-ohms = /bits/ 16 &lt;180&gt;;</div><div class='add'>+		ti,pressure-max = /bits/ 16 &lt;255&gt;;</div><div class='add'>+		ti,debounce-max = /bits/ 16 &lt;10&gt;;</div><div class='add'>+		ti,debounce-tol = /bits/ 16 &lt;3&gt;;</div><div class='add'>+		ti,debounce-rep = /bits/ 16 &lt;1&gt;;</div><div class='add'>+		ti,settle-delay-usec = /bits/ 16 &lt;150&gt;;</div><div class='add'>+		ti,keep-vref-on;</div><div class='add'>+		wakeup-source;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* BT module */</div><div class='add'>+&amp;lpuart5 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpuart5&gt;, &lt;&amp;pinctrl_bluetooth&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "nxp,88w8987-bt";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai1 {</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_sai1_sleep&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX93_CLK_SAI1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;clk IMX93_CLK_AUDIO_PLL&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;12288000&gt;;</div><div class='add'>+	fsl,sai-mclk-direction-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* eMMC */</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* WiFi */</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;, &lt;&amp;pinctrl_usdhc3_wlan&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;, &lt;&amp;pinctrl_usdhc3_wlan&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;, &lt;&amp;pinctrl_usdhc3_wlan&gt;;</div><div class='add'>+	pinctrl-3 = &lt;&amp;pinctrl_usdhc3_sleep&gt;, &lt;&amp;pinctrl_usdhc3_wlan&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	mmc-pwrseq = &lt;&amp;usdhc3_pwrseq&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	wakeup-source;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_bluetooth: bluetoothgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_ENET2_MDIO__GPIO4_IO15		0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_eqos: eqosgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_ENET1_MDC__ENET_QOS_MDC			0x57e</div><div class='add'>+			MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO			0x57e</div><div class='add'>+			MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0			0x57e</div><div class='add'>+			MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1			0x57e</div><div class='add'>+			MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2			0x57e</div><div class='add'>+			MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3			0x57e</div><div class='add'>+			MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x58e</div><div class='add'>+			MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x57e</div><div class='add'>+			MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0			0x57e</div><div class='add'>+			MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1			0x57e</div><div class='add'>+			MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2			0x57e</div><div class='add'>+			MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3			0x57e</div><div class='add'>+			MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x58e</div><div class='add'>+			MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x57e</div><div class='add'>+			MX93_PAD_UART2_TXD__GPIO1_IO07				0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_eqos_phy: regeqosgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_UART2_TXD__GPIO1_IO07			0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c3: lpi2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_GPIO_IO28__LPI2C3_SDA		0x40000b9e</div><div class='add'>+			MX93_PAD_GPIO_IO29__LPI2C3_SCL		0x40000b9e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c3_gpio: lpi2c3-gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_GPIO_IO28__GPIO2_IO28		0x40000b9e</div><div class='add'>+			MX93_PAD_GPIO_IO29__GPIO2_IO29		0x40000b9e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpspi8: lpspi8grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_GPIO_IO12__GPIO2_IO12		0x31e</div><div class='add'>+			MX93_PAD_GPIO_IO13__LPSPI8_SIN		0x31e</div><div class='add'>+			MX93_PAD_GPIO_IO14__LPSPI8_SOUT		0x31e</div><div class='add'>+			MX93_PAD_GPIO_IO15__LPSPI8_SCK		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpuart5: lpuart5grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX   0x31e</div><div class='add'>+			MX93_PAD_DAP_TDI__LPUART5_RX            0x31e</div><div class='add'>+			MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B   0x31e</div><div class='add'>+			MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B  0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_restouch: restouchgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_CCM_CLKO4__GPIO4_IO29		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai1: sai1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SAI1_TXC__SAI1_TX_BCLK		0x31e</div><div class='add'>+			MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC	0x31e</div><div class='add'>+			MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00	0x31e</div><div class='add'>+			MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00	0x31e</div><div class='add'>+			MX93_PAD_I2C2_SDA__SAI1_RX_BCLK		0x31e</div><div class='add'>+			MX93_PAD_I2C2_SCL__SAI1_RX_SYNC		0x31e</div><div class='add'>+			MX93_PAD_UART2_RXD__SAI1_MCLK		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai1_sleep: sai1-sleepgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SAI1_TXC__GPIO1_IO12		0x31e</div><div class='add'>+			MX93_PAD_SAI1_TXFS__GPIO1_IO11		0x31e</div><div class='add'>+			MX93_PAD_SAI1_TXD0__GPIO1_IO13		0x31e</div><div class='add'>+			MX93_PAD_SAI1_RXD0__GPIO1_IO14		0x31e</div><div class='add'>+			MX93_PAD_UART2_RXD__GPIO1_IO06		0x31e</div><div class='add'>+			MX93_PAD_I2C2_SDA__GPIO1_IO03		0x31e</div><div class='add'>+			MX93_PAD_I2C2_SCL__GPIO1_IO02		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD1_CLK__USDHC1_CLK		0x15fe</div><div class='add'>+			MX93_PAD_SD1_CMD__USDHC1_CMD		0x13fe</div><div class='add'>+			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x13fe</div><div class='add'>+			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x13fe</div><div class='add'>+			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x13fe</div><div class='add'>+			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x13fe</div><div class='add'>+			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x13fe</div><div class='add'>+			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x13fe</div><div class='add'>+			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x13fe</div><div class='add'>+			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x13fe</div><div class='add'>+			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x15fe</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD3_CLK__USDHC3_CLK		0x1582 /* SDIO_B_CLK */</div><div class='add'>+			MX93_PAD_SD3_CMD__USDHC3_CMD		0x40001382 /* SDIO_B_CMD */</div><div class='add'>+			MX93_PAD_SD3_DATA0__USDHC3_DATA0	0x40001382 /* SDIO_B_D0 */</div><div class='add'>+			MX93_PAD_SD3_DATA1__USDHC3_DATA1	0x40001382 /* SDIO_B_D1 */</div><div class='add'>+			MX93_PAD_SD3_DATA2__USDHC3_DATA2	0x40001382 /* SDIO_B_D2 */</div><div class='add'>+			MX93_PAD_SD3_DATA3__USDHC3_DATA3	0x40001382 /* SDIO_B_D3 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD3_CLK__USDHC3_CLK		0x158e /* SDIO_B_CLK */</div><div class='add'>+			MX93_PAD_SD3_CMD__USDHC3_CMD		0x4000138e /* SDIO_B_CMD */</div><div class='add'>+			MX93_PAD_SD3_DATA0__USDHC3_DATA0	0x4000138e /* SDIO_B_D0 */</div><div class='add'>+			MX93_PAD_SD3_DATA1__USDHC3_DATA1	0x4000138e /* SDIO_B_D1 */</div><div class='add'>+			MX93_PAD_SD3_DATA2__USDHC3_DATA2	0x4000138e /* SDIO_B_D2 */</div><div class='add'>+			MX93_PAD_SD3_DATA3__USDHC3_DATA3	0x4000138e /* SDIO_B_D3 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD3_CLK__USDHC3_CLK		0x15fe /* SDIO_B_CLK */</div><div class='add'>+			MX93_PAD_SD3_CMD__USDHC3_CMD		0x400013fe /* SDIO_B_CMD */</div><div class='add'>+			MX93_PAD_SD3_DATA0__USDHC3_DATA0	0x400013fe /* SDIO_B_D0 */</div><div class='add'>+			MX93_PAD_SD3_DATA1__USDHC3_DATA1	0x400013fe /* SDIO_B_D1 */</div><div class='add'>+			MX93_PAD_SD3_DATA2__USDHC3_DATA2	0x400013fe /* SDIO_B_D2 */</div><div class='add'>+			MX93_PAD_SD3_DATA3__USDHC3_DATA3	0x400013fe /* SDIO_B_D3 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_sleep: usdhc3-sleepgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_SD3_CLK__GPIO3_IO20		0x400</div><div class='add'>+			MX93_PAD_SD3_CMD__GPIO3_IO21		0x400</div><div class='add'>+			MX93_PAD_SD3_DATA0__GPIO3_IO22		0x400</div><div class='add'>+			MX93_PAD_SD3_DATA1__GPIO3_IO23		0x400</div><div class='add'>+			MX93_PAD_SD3_DATA2__GPIO3_IO24		0x400</div><div class='add'>+			MX93_PAD_SD3_DATA3__GPIO3_IO25		0x400</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_wlan: usdhc3-wlangrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			MX93_PAD_ENET2_MDC__GPIO4_IO14		0x51e /* WIFI_REG_ON     */</div><div class='add'>+			MX93_PAD_SD2_RESET_B__GPIO3_IO07	0x51e /* WIFI_PWR_EN     */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi<br/>new file mode 100644<br/>index 000000000000..7b27012dfcb5<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx93.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx93.dtsi</a></div><div class='hunk'>@@ -0,0 +1,161 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022,2025 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "imx91_93_common.dtsi"</div><div class='add'>+</div><div class='add'>+/{</div><div class='add'>+	cm33: remoteproc-cm33 {</div><div class='add'>+		compatible = "fsl,imx93-cm33";</div><div class='add'>+		clocks = &lt;&amp;clk IMX93_CLK_CM33_GATE&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	thermal-zones {</div><div class='add'>+		cpu-thermal {</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			polling-delay = &lt;2000&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tmu 0&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu_alert: cpu-alert {</div><div class='add'>+					temperature = &lt;80000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_crit: cpu-crit {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu_alert&gt;;</div><div class='add'>+					cooling-device =</div><div class='add'>+						&lt;&amp;A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+						&lt;&amp;A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;aips1 {</div><div class='add'>+	mu1: mailbox@44230000 {</div><div class='add'>+		compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";</div><div class='add'>+		reg = &lt;0x44230000 0x10000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX93_CLK_MU1_B_GATE&gt;;</div><div class='add'>+		#mbox-cells = &lt;2&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	tmu: tmu@44482000 {</div><div class='add'>+		compatible = "fsl,qoriq-tmu";</div><div class='add'>+		reg = &lt;0x44482000 0x1000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX93_CLK_TMC_GATE&gt;;</div><div class='add'>+		#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+		little-endian;</div><div class='add'>+		fsl,tmu-range = &lt;0x800000da 0x800000e9</div><div class='add'>+				 0x80000102 0x8000012a</div><div class='add'>+				 0x80000166 0x800001a7</div><div class='add'>+				 0x800001b6&gt;;</div><div class='add'>+		fsl,tmu-calibration = &lt;0x00000000 0x0000000e</div><div class='add'>+				       0x00000001 0x00000029</div><div class='add'>+				       0x00000002 0x00000056</div><div class='add'>+				       0x00000003 0x000000a2</div><div class='add'>+				       0x00000004 0x00000116</div><div class='add'>+				       0x00000005 0x00000195</div><div class='add'>+				       0x00000006 0x000001b2&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;aips2 {</div><div class='add'>+	mu2: mailbox@42440000 {</div><div class='add'>+		compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";</div><div class='add'>+		reg = &lt;0x42440000 0x10000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX93_CLK_MU2_B_GATE&gt;;</div><div class='add'>+		#mbox-cells = &lt;2&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpus {</div><div class='add'>+	A55_0: cpu@0 {</div><div class='add'>+		device_type = "cpu";</div><div class='add'>+		compatible = "arm,cortex-a55";</div><div class='add'>+		reg = &lt;0x0&gt;;</div><div class='add'>+		enable-method = "psci";</div><div class='add'>+		#cooling-cells = &lt;2&gt;;</div><div class='add'>+		cpu-idle-states = &lt;&amp;cpu_pd_wait&gt;;</div><div class='add'>+		i-cache-size = &lt;32768&gt;;</div><div class='add'>+		i-cache-line-size = &lt;64&gt;;</div><div class='add'>+		i-cache-sets = &lt;128&gt;;</div><div class='add'>+		d-cache-size = &lt;32768&gt;;</div><div class='add'>+		d-cache-line-size = &lt;64&gt;;</div><div class='add'>+		d-cache-sets = &lt;128&gt;;</div><div class='add'>+		next-level-cache = &lt;&amp;l2_cache_l0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	A55_1: cpu@100 {</div><div class='add'>+		device_type = "cpu";</div><div class='add'>+		compatible = "arm,cortex-a55";</div><div class='add'>+		reg = &lt;0x100&gt;;</div><div class='add'>+		enable-method = "psci";</div><div class='add'>+		#cooling-cells = &lt;2&gt;;</div><div class='add'>+		cpu-idle-states = &lt;&amp;cpu_pd_wait&gt;;</div><div class='add'>+		i-cache-size = &lt;32768&gt;;</div><div class='add'>+		i-cache-line-size = &lt;64&gt;;</div><div class='add'>+		i-cache-sets = &lt;128&gt;;</div><div class='add'>+		d-cache-size = &lt;32768&gt;;</div><div class='add'>+		d-cache-line-size = &lt;64&gt;;</div><div class='add'>+		d-cache-sets = &lt;128&gt;;</div><div class='add'>+		next-level-cache = &lt;&amp;l2_cache_l1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	l2_cache_l0: l2-cache-l0 {</div><div class='add'>+		compatible = "cache";</div><div class='add'>+		cache-size = &lt;65536&gt;;</div><div class='add'>+		cache-line-size = &lt;64&gt;;</div><div class='add'>+		cache-sets = &lt;256&gt;;</div><div class='add'>+		cache-level = &lt;2&gt;;</div><div class='add'>+		cache-unified;</div><div class='add'>+		next-level-cache = &lt;&amp;l3_cache&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	l2_cache_l1: l2-cache-l1 {</div><div class='add'>+		compatible = "cache";</div><div class='add'>+		cache-size = &lt;65536&gt;;</div><div class='add'>+		cache-line-size = &lt;64&gt;;</div><div class='add'>+		cache-sets = &lt;256&gt;;</div><div class='add'>+		cache-level = &lt;2&gt;;</div><div class='add'>+		cache-unified;</div><div class='add'>+		next-level-cache = &lt;&amp;l3_cache&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	l3_cache: l3-cache {</div><div class='add'>+		compatible = "cache";</div><div class='add'>+		cache-size = &lt;262144&gt;;</div><div class='add'>+		cache-line-size = &lt;64&gt;;</div><div class='add'>+		cache-sets = &lt;256&gt;;</div><div class='add'>+		cache-level = &lt;3&gt;;</div><div class='add'>+		cache-unified;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;src {</div><div class='add'>+	mlmix: power-domain@44461800 {</div><div class='add'>+		compatible = "fsl,imx93-src-slice";</div><div class='add'>+		reg = &lt;0x44461800 0x400&gt;, &lt;0x44464800 0x400&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk IMX93_CLK_ML_APB&gt;,</div><div class='add'>+			 &lt;&amp;clk IMX93_CLK_ML&gt;;</div><div class='add'>+		#power-domain-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx94-clock.h b/arch/arm64/boot/dts/freescale/imx94-clock.h<br/>new file mode 100644<br/>index 000000000000..27e8c0839722<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx94-clock.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx94-clock.h</a></div><div class='hunk'>@@ -0,0 +1,193 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024-2025 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __IMX94_CLOCK_H</div><div class='add'>+#define __IMX94_CLOCK_H</div><div class='add'>+</div><div class='add'>+#define IMX94_CLK_EXT				0</div><div class='add'>+#define IMX94_CLK_32K				1</div><div class='add'>+#define IMX94_CLK_24M				2</div><div class='add'>+#define IMX94_CLK_FRO				3</div><div class='add'>+#define IMX94_CLK_SYSPLL1_VCO			4</div><div class='add'>+#define IMX94_CLK_SYSPLL1_PFD0_UNGATED		5</div><div class='add'>+#define IMX94_CLK_SYSPLL1_PFD0			6</div><div class='add'>+#define IMX94_CLK_SYSPLL1_PFD0_DIV2		7</div><div class='add'>+#define IMX94_CLK_SYSPLL1_PFD1_UNGATED		8</div><div class='add'>+#define IMX94_CLK_SYSPLL1_PFD1			9</div><div class='add'>+#define IMX94_CLK_SYSPLL1_PFD1_DIV2		10</div><div class='add'>+#define IMX94_CLK_SYSPLL1_PFD2_UNGATED		11</div><div class='add'>+#define IMX94_CLK_SYSPLL1_PFD2			12</div><div class='add'>+#define IMX94_CLK_SYSPLL1_PFD2_DIV2		13</div><div class='add'>+#define IMX94_CLK_AUDIOPLL1_VCO			14</div><div class='add'>+#define IMX94_CLK_AUDIOPLL1			15</div><div class='add'>+#define IMX94_CLK_AUDIOPLL2_VCO			16</div><div class='add'>+#define IMX94_CLK_AUDIOPLL2			17</div><div class='add'>+#define IMX94_CLK_RESERVED18			18</div><div class='add'>+#define IMX94_CLK_RESERVED19			19</div><div class='add'>+#define IMX94_CLK_RESERVED20			20</div><div class='add'>+#define IMX94_CLK_RESERVED21			21</div><div class='add'>+#define IMX94_CLK_RESERVED22			22</div><div class='add'>+#define IMX94_CLK_RESERVED23			23</div><div class='add'>+#define IMX94_CLK_ENCPLL_VCO			24</div><div class='add'>+#define IMX94_CLK_ENCPLL_PFD0_UNGATED		25</div><div class='add'>+#define IMX94_CLK_ENCPLL_PFD0			26</div><div class='add'>+#define IMX94_CLK_ENCPLL_PFD1_UNGATED		27</div><div class='add'>+#define IMX94_CLK_ENCPLL_PFD1			28</div><div class='add'>+#define IMX94_CLK_ARMPLL_VCO			29</div><div class='add'>+#define IMX94_CLK_ARMPLL_PFD0_UNGATED		30</div><div class='add'>+#define IMX94_CLK_ARMPLL_PFD0			31</div><div class='add'>+#define IMX94_CLK_ARMPLL_PFD1_UNGATED		32</div><div class='add'>+#define IMX94_CLK_ARMPLL_PFD1			33</div><div class='add'>+#define IMX94_CLK_ARMPLL_PFD2_UNGATED		34</div><div class='add'>+#define IMX94_CLK_ARMPLL_PFD2			35</div><div class='add'>+#define IMX94_CLK_ARMPLL_PFD3_UNGATED		36</div><div class='add'>+#define IMX94_CLK_ARMPLL_PFD3			37</div><div class='add'>+#define IMX94_CLK_DRAMPLL_VCO			38</div><div class='add'>+#define IMX94_CLK_DRAMPLL			39</div><div class='add'>+#define IMX94_CLK_HSIOPLL_VCO			40</div><div class='add'>+#define IMX94_CLK_HSIOPLL			41</div><div class='add'>+#define IMX94_CLK_LDBPLL_VCO			42</div><div class='add'>+#define IMX94_CLK_LDBPLL			43</div><div class='add'>+#define IMX94_CLK_EXT1				44</div><div class='add'>+#define IMX94_CLK_EXT2				45</div><div class='add'>+#define IMX94_CLK_ADC				46</div><div class='add'>+#define IMX94_CLK_BUSAON			47</div><div class='add'>+#define IMX94_CLK_CAN1				48</div><div class='add'>+#define IMX94_CLK_GLITCHFILTER			49</div><div class='add'>+#define IMX94_CLK_GPT1				50</div><div class='add'>+#define IMX94_CLK_I3C1SLOW			51</div><div class='add'>+#define IMX94_CLK_LPI2C1			52</div><div class='add'>+#define IMX94_CLK_LPI2C2			53</div><div class='add'>+#define IMX94_CLK_LPSPI1			54</div><div class='add'>+#define IMX94_CLK_LPSPI2			55</div><div class='add'>+#define IMX94_CLK_LPTMR1			56</div><div class='add'>+#define IMX94_CLK_LPUART1			57</div><div class='add'>+#define IMX94_CLK_LPUART2			58</div><div class='add'>+#define IMX94_CLK_M33				59</div><div class='add'>+#define IMX94_CLK_M33SYSTICK			60</div><div class='add'>+#define IMX94_CLK_PDM				61</div><div class='add'>+#define IMX94_CLK_SAI1				62</div><div class='add'>+#define IMX94_CLK_TPM2				63</div><div class='add'>+#define IMX94_CLK_A55				64</div><div class='add'>+#define IMX94_CLK_A55MTRBUS			65</div><div class='add'>+#define IMX94_CLK_A55PERIPH			66</div><div class='add'>+#define IMX94_CLK_DRAMALT			67</div><div class='add'>+#define IMX94_CLK_DRAMAPB			68</div><div class='add'>+#define IMX94_CLK_DISPAPB			69</div><div class='add'>+#define IMX94_CLK_DISPAXI			70</div><div class='add'>+#define IMX94_CLK_DISPPIX			71</div><div class='add'>+#define IMX94_CLK_HSIOACSCAN480M		72</div><div class='add'>+#define IMX94_CLK_HSIOACSCAN80M			73</div><div class='add'>+#define IMX94_CLK_HSIO				74</div><div class='add'>+#define IMX94_CLK_HSIOPCIEAUX			75</div><div class='add'>+#define IMX94_CLK_HSIOPCIETEST160M		76</div><div class='add'>+#define IMX94_CLK_HSIOPCIETEST400M		77</div><div class='add'>+#define IMX94_CLK_HSIOPCIETEST500M		78</div><div class='add'>+#define IMX94_CLK_HSIOPCIETEST50M		79</div><div class='add'>+#define IMX94_CLK_HSIOUSBTEST60M		80</div><div class='add'>+#define IMX94_CLK_BUSM70			81</div><div class='add'>+#define IMX94_CLK_M70				82</div><div class='add'>+#define IMX94_CLK_M70SYSTICK			83</div><div class='add'>+#define IMX94_CLK_BUSM71			84</div><div class='add'>+#define IMX94_CLK_M71				85</div><div class='add'>+#define IMX94_CLK_M71SYSTICK			86</div><div class='add'>+#define IMX94_CLK_BUSNETCMIX			87</div><div class='add'>+#define IMX94_CLK_ECAT				88</div><div class='add'>+#define IMX94_CLK_ENET				89</div><div class='add'>+#define IMX94_CLK_ENETPHYTEST200M		90</div><div class='add'>+#define IMX94_CLK_ENETPHYTEST500M		91</div><div class='add'>+#define IMX94_CLK_ENETPHYTEST667M		92</div><div class='add'>+#define IMX94_CLK_ENETREF			93</div><div class='add'>+#define IMX94_CLK_ENETTIMER1			94</div><div class='add'>+#define IMX94_CLK_ENETTIMER2			95</div><div class='add'>+#define IMX94_CLK_ENETTIMER3			96</div><div class='add'>+#define IMX94_CLK_FLEXIO3			97</div><div class='add'>+#define IMX94_CLK_FLEXIO4			98</div><div class='add'>+#define IMX94_CLK_M33SYNC			99</div><div class='add'>+#define IMX94_CLK_M33SYNCSYSTICK		100</div><div class='add'>+#define IMX94_CLK_MAC0				101</div><div class='add'>+#define IMX94_CLK_MAC1				102</div><div class='add'>+#define IMX94_CLK_MAC2				103</div><div class='add'>+#define IMX94_CLK_MAC3				104</div><div class='add'>+#define IMX94_CLK_MAC4				105</div><div class='add'>+#define IMX94_CLK_MAC5				106</div><div class='add'>+#define IMX94_CLK_NOCAPB			107</div><div class='add'>+#define IMX94_CLK_NOC				108</div><div class='add'>+#define IMX94_CLK_NPUAPB			109</div><div class='add'>+#define IMX94_CLK_NPU				110</div><div class='add'>+#define IMX94_CLK_CCMCKO1			111</div><div class='add'>+#define IMX94_CLK_CCMCKO2			112</div><div class='add'>+#define IMX94_CLK_CCMCKO3			113</div><div class='add'>+#define IMX94_CLK_CCMCKO4			114</div><div class='add'>+#define IMX94_CLK_BISS				115</div><div class='add'>+#define IMX94_CLK_BUSWAKEUP			116</div><div class='add'>+#define IMX94_CLK_CAN2				117</div><div class='add'>+#define IMX94_CLK_CAN3				118</div><div class='add'>+#define IMX94_CLK_CAN4				119</div><div class='add'>+#define IMX94_CLK_CAN5				120</div><div class='add'>+#define IMX94_CLK_ENDAT21			121</div><div class='add'>+#define IMX94_CLK_ENDAT22			122</div><div class='add'>+#define IMX94_CLK_ENDAT31FAST			123</div><div class='add'>+#define IMX94_CLK_ENDAT31SLOW			124</div><div class='add'>+#define IMX94_CLK_FLEXIO1			125</div><div class='add'>+#define IMX94_CLK_FLEXIO2			126</div><div class='add'>+#define IMX94_CLK_GPT2				127</div><div class='add'>+#define IMX94_CLK_GPT3				128</div><div class='add'>+#define IMX94_CLK_GPT4				129</div><div class='add'>+#define IMX94_CLK_HIPERFACE1			130</div><div class='add'>+#define IMX94_CLK_HIPERFACE1SYNC		131</div><div class='add'>+#define IMX94_CLK_HIPERFACE2			132</div><div class='add'>+#define IMX94_CLK_HIPERFACE2SYNC		133</div><div class='add'>+#define IMX94_CLK_I3C2SLOW			134</div><div class='add'>+#define IMX94_CLK_LPI2C3			135</div><div class='add'>+#define IMX94_CLK_LPI2C4			136</div><div class='add'>+#define IMX94_CLK_LPI2C5			137</div><div class='add'>+#define IMX94_CLK_LPI2C6			138</div><div class='add'>+#define IMX94_CLK_LPI2C7			139</div><div class='add'>+#define IMX94_CLK_LPI2C8			140</div><div class='add'>+#define IMX94_CLK_LPSPI3			141</div><div class='add'>+#define IMX94_CLK_LPSPI4			142</div><div class='add'>+#define IMX94_CLK_LPSPI5			143</div><div class='add'>+#define IMX94_CLK_LPSPI6			144</div><div class='add'>+#define IMX94_CLK_LPSPI7			145</div><div class='add'>+#define IMX94_CLK_LPSPI8			146</div><div class='add'>+#define IMX94_CLK_LPTMR2			147</div><div class='add'>+#define IMX94_CLK_LPUART10			148</div><div class='add'>+#define IMX94_CLK_LPUART11			149</div><div class='add'>+#define IMX94_CLK_LPUART12			150</div><div class='add'>+#define IMX94_CLK_LPUART3			151</div><div class='add'>+#define IMX94_CLK_LPUART4			152</div><div class='add'>+#define IMX94_CLK_LPUART5			153</div><div class='add'>+#define IMX94_CLK_LPUART6			154</div><div class='add'>+#define IMX94_CLK_LPUART7			155</div><div class='add'>+#define IMX94_CLK_LPUART8			156</div><div class='add'>+#define IMX94_CLK_LPUART9			157</div><div class='add'>+#define IMX94_CLK_SAI2				158</div><div class='add'>+#define IMX94_CLK_SAI3				159</div><div class='add'>+#define IMX94_CLK_SAI4				160</div><div class='add'>+#define IMX94_CLK_SWOTRACE			161</div><div class='add'>+#define IMX94_CLK_TPM4				162</div><div class='add'>+#define IMX94_CLK_TPM5				163</div><div class='add'>+#define IMX94_CLK_TPM6				164</div><div class='add'>+#define IMX94_CLK_USBPHYBURUNIN			165</div><div class='add'>+#define IMX94_CLK_USDHC1			166</div><div class='add'>+#define IMX94_CLK_USDHC2			167</div><div class='add'>+#define IMX94_CLK_USDHC3			168</div><div class='add'>+#define IMX94_CLK_V2XPK				169</div><div class='add'>+#define IMX94_CLK_WAKEUPAXI			170</div><div class='add'>+#define IMX94_CLK_XSPISLVROOT			171</div><div class='add'>+#define IMX94_CLK_XSPI1				172</div><div class='add'>+#define IMX94_CLK_XSPI2				173</div><div class='add'>+#define IMX94_CLK_SEL_EXT			174</div><div class='add'>+#define IMX94_CLK_SEL_A55C0			175</div><div class='add'>+#define IMX94_CLK_SEL_A55C1			176</div><div class='add'>+#define IMX94_CLK_SEL_A55C2			177</div><div class='add'>+#define IMX94_CLK_SEL_A55C3			178</div><div class='add'>+#define IMX94_CLK_SEL_A55P			179</div><div class='add'>+#define IMX94_CLK_SEL_DRAM			180</div><div class='add'>+#define IMX94_CLK_SEL_TEMPSENSE			181</div><div class='add'>+#define IMX94_CLK_NPU_CGC			182</div><div class='add'>+</div><div class='add'>+#endif /* __IMX94_CLOCK_H */</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx94-pinfunc.h b/arch/arm64/boot/dts/freescale/imx94-pinfunc.h<br/>new file mode 100644<br/>index 000000000000..00255db89185<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx94-pinfunc.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx94-pinfunc.h</a></div><div class='hunk'>@@ -0,0 +1,1570 @@</div><div class='add'>+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024-2025 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __DTS_IMX94_PINFUNC_H</div><div class='add'>+#define __DTS_IMX94_PINFUNC_H</div><div class='add'>+</div><div class='add'>+/* Drive Strength */</div><div class='add'>+#define IMX94_DSE_X1		0x2</div><div class='add'>+#define IMX94_DSE_X2		0x6</div><div class='add'>+#define IMX94_DSE_X3		0xe</div><div class='add'>+#define IMX94_DSE_X4		0x1e</div><div class='add'>+#define IMX94_DSE_X5		0x3e</div><div class='add'>+#define IMX94_DSE_X6		0x7e</div><div class='add'>+</div><div class='add'>+/* Slew Rate */</div><div class='add'>+#define IMX94_FSEL_FAST		0x180</div><div class='add'>+#define IMX94_FSEL_SLOW		0x100</div><div class='add'>+</div><div class='add'>+/* Pull Up */</div><div class='add'>+#define IMX94_PU_ENABLE		0x200</div><div class='add'>+#define IMX94_PU_DISABLE	0x0</div><div class='add'>+</div><div class='add'>+/* Pull Down */</div><div class='add'>+#define IMX94_PD_ENABLE		0x400</div><div class='add'>+#define IMX94_PD_DISABLE	0x0</div><div class='add'>+</div><div class='add'>+/* Open Drain */</div><div class='add'>+#define IMX94_OD_ENABLE		0x800</div><div class='add'>+#define IMX94_OD_DISABLE	0x0</div><div class='add'>+</div><div class='add'>+/* Schmitt trigger */</div><div class='add'>+#define IMX94_HYS_SCHMITT	0x1000</div><div class='add'>+#define IMX94_HYS_NO_SCHMITT	0x0</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * The pin function ID is a tuple of &lt;mux_reg conf_reg input_reg mux_mode input_val&gt;</div><div class='add'>+ */</div><div class='add'>+#define IMX94_PAD_DAP_TDI__JTAG_MUX_TDI                     0x0000 0x0304 0x092c 0x00 0x00</div><div class='add'>+#define IMX94_PAD_DAP_TDI__MQS2_LEFT                        0x0000 0x0304 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_DAP_TDI__ECAT_LED_ERR                     0x0000 0x0304 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_DAP_TDI__CAN2_TX                          0x0000 0x0304 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_DAP_TDI__SINC_FILTER_GLUE3_BREAK          0x0000 0x0304 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_DAP_TDI__GPIO4_IO4                        0x0000 0x0304 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_DAP_TDI__LPUART5_RX                       0x0000 0x0304 0x07bc 0x06 0x00</div><div class='add'>+#define IMX94_PAD_DAP_TDI__XBAR1_XBAR_INOUT26               0x0000 0x0304 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS               0x0004 0x0308 0x0930 0x00 0x00</div><div class='add'>+#define IMX94_PAD_DAP_TMS_SWDIO__CAN5_TX                    0x0004 0x0308 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_DAP_TMS_SWDIO__GPT_MUX_INOUT10            0x0004 0x0308 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_DAP_TMS_SWDIO__LPUART8_TX                 0x0004 0x0308 0x07dc 0x03 0x00</div><div class='add'>+#define IMX94_PAD_DAP_TMS_SWDIO__SINC3_MOD_CLK1             0x0004 0x0308 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_DAP_TMS_SWDIO__GPIO4_IO5                  0x0004 0x0308 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B              0x0004 0x0308 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_DAP_TMS_SWDIO__XBAR1_XBAR_INOUT27         0x0004 0x0308 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK              0x0008 0x030c 0x0928 0x00 0x00</div><div class='add'>+#define IMX94_PAD_DAP_TCLK_SWCLK__CAN5_RX                   0x0008 0x030c 0x0688 0x01 0x00</div><div class='add'>+#define IMX94_PAD_DAP_TCLK_SWCLK__GPT_MUX_INOUT11           0x0008 0x030c 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_DAP_TCLK_SWCLK__LPUART8_RX                0x0008 0x030c 0x07d8 0x03 0x00</div><div class='add'>+#define IMX94_PAD_DAP_TCLK_SWCLK__SINC3_MOD_CLK0            0x0008 0x030c 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_DAP_TCLK_SWCLK__GPIO4_IO6                 0x0008 0x030c 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B             0x0008 0x030c 0x07b8 0x06 0x00</div><div class='add'>+#define IMX94_PAD_DAP_TCLK_SWCLK__XBAR1_XBAR_INOUT28        0x0008 0x030c 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO            0x000c 0x0310 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT              0x000c 0x0310 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_DAP_TDO_TRACESWO__ECAT_RESET_OUT          0x000c 0x0310 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_DAP_TDO_TRACESWO__CAN2_RX                 0x000c 0x0310 0x067c 0x03 0x00</div><div class='add'>+#define IMX94_PAD_DAP_TDO_TRACESWO__SINC3_MOD_CLK2          0x000c 0x0310 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_DAP_TDO_TRACESWO__GPIO4_IO7               0x000c 0x0310 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_DAP_TDO_TRACESWO__LPUART5_TX              0x000c 0x0310 0x07c0 0x06 0x00</div><div class='add'>+#define IMX94_PAD_DAP_TDO_TRACESWO__XBAR1_XBAR_INOUT29      0x000c 0x0310 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO00__GPIO2_IO0                      0x0010 0x0314 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO00__I3C2_PUR                       0x0010 0x0314 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO00__XBAR1_XBAR_INOUT39             0x0010 0x0314 0x08d4 0x02 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO00__I3C2_PUR_B                     0x0010 0x0314 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO00__LPSPI6_PCS0                    0x0010 0x0314 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO00__LPUART5_TX                     0x0010 0x0314 0x07c0 0x05 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO00__LPI2C5_SDA                     0x0010 0x0314 0x0740 0x06 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO00__FLEXIO1_FLEXIO0                0x0010 0x0314 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO01__GPIO2_IO1                      0x0014 0x0318 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO01__I3C2_SCL                       0x0014 0x0318 0x0720 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO01__XBAR1_XBAR_INOUT40             0x0014 0x0318 0x08d8 0x02 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO01__EWM_OUT_B                      0x0014 0x0318 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO01__LPSPI6_SIN                     0x0014 0x0318 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO01__LPUART5_RX                     0x0014 0x0318 0x07bc 0x05 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO01__LPI2C5_SCL                     0x0014 0x0318 0x073c 0x06 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO01__FLEXIO1_FLEXIO1                0x0014 0x0318 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO02__GPIO2_IO2                      0x0018 0x031c 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO02__I3C2_SDA                       0x0018 0x031c 0x0724 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO02__XBAR1_XBAR_INOUT41             0x0018 0x031c 0x08dc 0x02 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO02__GPT_MUX_INOUT1                 0x0018 0x031c 0x0700 0x03 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO02__LPSPI6_SOUT                    0x0018 0x031c 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO02__LPUART5_CTS_B                  0x0018 0x031c 0x07b8 0x05 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO02__LPI2C6_SDA                     0x0018 0x031c 0x074c 0x06 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO02__FLEXIO1_FLEXIO2                0x0018 0x031c 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO03__GPIO2_IO3                      0x001c 0x0320 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO03__EWM_OUT_B                      0x001c 0x0320 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO03__XBAR1_XBAR_INOUT42             0x001c 0x0320 0x08e0 0x02 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO03__GPT_MUX_INOUT4                 0x001c 0x0320 0x0708 0x03 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO03__LPSPI6_SCK                     0x001c 0x0320 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO03__LPUART5_RTS_B                  0x001c 0x0320 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO03__LPI2C6_SCL                     0x001c 0x0320 0x0748 0x06 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO03__FLEXIO1_FLEXIO3                0x001c 0x0320 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO04__GPIO2_IO4                      0x0020 0x0324 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO04__TPM3_CH0                       0x0020 0x0324 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO04__PDM_CLK                        0x0020 0x0324 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO04__GPT_MUX_INOUT5                 0x0020 0x0324 0x070c 0x03 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO04__LPSPI7_PCS0                    0x0020 0x0324 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO04__LPUART6_TX                     0x0020 0x0324 0x07cc 0x05 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO04__LPI2C6_SDA                     0x0020 0x0324 0x074c 0x06 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO04__FLEXIO1_FLEXIO4                0x0020 0x0324 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO05__GPIO2_IO5                      0x0024 0x0328 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO05__TPM4_CH0                       0x0024 0x0328 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO05__PDM_BIT_STREAM0                0x0024 0x0328 0x0610 0x02 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO05__GPT_MUX_INOUT7                 0x0024 0x0328 0x0714 0x03 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO05__LPSPI7_SIN                     0x0024 0x0328 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO05__LPUART6_RX                     0x0024 0x0328 0x07c8 0x05 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO05__LPI2C6_SCL                     0x0024 0x0328 0x0748 0x06 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO05__FLEXIO1_FLEXIO5                0x0024 0x0328 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO06__GPIO2_IO6                      0x0028 0x032c 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO06__TPM5_CH0                       0x0028 0x032c 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO06__PDM_BIT_STREAM1                0x0028 0x032c 0x0614 0x02 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO06__GPT_MUX_INOUT8                 0x0028 0x032c 0x0718 0x03 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO06__LPSPI7_SOUT                    0x0028 0x032c 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO06__LPUART6_CTS_B                  0x0028 0x032c 0x07c4 0x05 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO06__LPI2C7_SDA                     0x0028 0x032c 0x0754 0x06 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO06__FLEXIO1_FLEXIO6                0x0028 0x032c 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO07__GPIO2_IO7                      0x002c 0x0330 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO07__LPSPI3_PCS1                    0x002c 0x0330 0x0768 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO07__XBAR1_XBAR_INOUT43             0x002c 0x0330 0x08e4 0x02 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO07__GPT_MUX_INOUT3                 0x002c 0x0330 0x0704 0x03 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO07__LPSPI7_SCK                     0x002c 0x0330 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO07__LPUART6_RTS_B                  0x002c 0x0330 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO07__LPI2C7_SCL                     0x002c 0x0330 0x0750 0x06 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO07__FLEXIO1_FLEXIO7                0x002c 0x0330 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO08__GPIO2_IO8                      0x0030 0x0334 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO08__LPSPI3_PCS0                    0x0030 0x0334 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO08__USDHC2_WP                      0x0030 0x0334 0x0854 0x02 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO08__GPT_MUX_INOUT2                 0x0030 0x0334 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO08__TPM6_CH0                       0x0030 0x0334 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO08__LPUART7_TX                     0x0030 0x0334 0x07d4 0x05 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO08__LPI2C7_SDA                     0x0030 0x0334 0x0754 0x06 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO08__FLEXIO1_FLEXIO8                0x0030 0x0334 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO09__GPIO2_IO9                      0x0034 0x0338 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO09__LPSPI3_SIN                     0x0034 0x0338 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO09__XBAR1_XBAR_INOUT44             0x0034 0x0338 0x08e8 0x02 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO09__GPT_MUX_INOUT0                 0x0034 0x0338 0x06fc 0x03 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO09__TPM3_EXTCLK                    0x0034 0x0338 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO09__LPUART7_RX                     0x0034 0x0338 0x07d0 0x05 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO09__LPI2C7_SCL                     0x0034 0x0338 0x0750 0x06 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO09__FLEXIO1_FLEXIO9                0x0034 0x0338 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO10__GPIO2_IO10                     0x0038 0x033c 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO10__LPSPI3_SOUT                    0x0038 0x033c 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO10__XBAR1_XBAR_INOUT45             0x0038 0x033c 0x08ec 0x02 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO10__GPT_MUX_INOUT6                 0x0038 0x033c 0x0710 0x03 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO10__TPM4_EXTCLK                    0x0038 0x033c 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO10__LPUART7_CTS_B                  0x0038 0x033c 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO10__LPI2C8_SDA                     0x0038 0x033c 0x075c 0x06 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO10__FLEXIO1_FLEXIO10               0x0038 0x033c 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO11__GPIO2_IO11                     0x003c 0x0340 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO11__LPSPI3_SCK                     0x003c 0x0340 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO11__XBAR1_XBAR_INOUT46             0x003c 0x0340 0x08f0 0x02 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO11__GPT_MUX_INOUT9                 0x003c 0x0340 0x071c 0x03 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO11__TPM5_EXTCLK                    0x003c 0x0340 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO11__LPUART7_RTS_B                  0x003c 0x0340 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO11__LPI2C8_SCL                     0x003c 0x0340 0x0758 0x06 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO11__FLEXIO1_FLEXIO11               0x003c 0x0340 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO12__GPIO2_IO12                     0x0040 0x0344 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO12__TPM3_CH2                       0x0040 0x0344 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO12__PDM_BIT_STREAM2                0x0040 0x0344 0x0618 0x02 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO12__FLEXIO1_FLEXIO12               0x0040 0x0344 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO12__LPSPI8_PCS0                    0x0040 0x0344 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO12__LPUART8_TX                     0x0040 0x0344 0x07dc 0x05 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO12__LPI2C8_SDA                     0x0040 0x0344 0x075c 0x06 0x01</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO13__GPIO2_IO13                     0x0044 0x0348 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO13__TPM4_CH2                       0x0044 0x0348 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO13__PDM_BIT_STREAM3                0x0044 0x0348 0x061c 0x02 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO13__XBAR1_XBAR_INOUT47             0x0044 0x0348 0x08f4 0x03 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO13__LPSPI8_SIN                     0x0044 0x0348 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO13__LPUART8_RX                     0x0044 0x0348 0x07d8 0x05 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO13__LPI2C8_SCL                     0x0044 0x0348 0x0758 0x06 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO13__FLEXIO1_FLEXIO13               0x0044 0x0348 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO14__GPIO2_IO14                     0x0048 0x034c 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO14__LPUART10_CTS_B                 0x0048 0x034c 0x078c 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO14__ECAT_SDA                       0x0048 0x034c 0x062c 0x02 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO14__XBAR1_XBAR_INOUT48             0x0048 0x034c 0x08f8 0x03 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO14__LPSPI8_SOUT                    0x0048 0x034c 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO14__LPUART8_CTS_B                  0x0048 0x034c 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO14__LPUART4_TX                     0x0048 0x034c 0x07b4 0x06 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO14__FLEXIO1_FLEXIO14               0x0048 0x034c 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO15__GPIO2_IO15                     0x004c 0x0350 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO15__LPUART10_RTS_B                 0x004c 0x0350 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO15__ECAT_SCL                       0x004c 0x0350 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO15__XBAR1_XBAR_INOUT8              0x004c 0x0350 0x087c 0x03 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO15__LPSPI8_SCK                     0x004c 0x0350 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO15__LPUART8_RTS_B                  0x004c 0x0350 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO15__LPUART4_RX                     0x004c 0x0350 0x07b0 0x06 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO15__FLEXIO1_FLEXIO15               0x004c 0x0350 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO16__GPIO2_IO16                     0x0050 0x0354 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO16__LPI2C3_SDA                     0x0050 0x0354 0x0730 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO16__CAN3_TX                        0x0050 0x0354 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO16__EWM_OUT_B                      0x0050 0x0354 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO16__LPUART11_TX                    0x0050 0x0354 0x079c 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO16__GPT_MUX_INOUT0                 0x0050 0x0354 0x06fc 0x05 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO16__FLEXPWM4_PWMA0                 0x0050 0x0354 0x06d4 0x06 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO16__XBAR1_XBAR_INOUT30             0x0050 0x0354 0x08b0 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO17__GPIO2_IO17                     0x0054 0x0358 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO17__LPI2C3_SCL                     0x0054 0x0358 0x072c 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO17__CAN3_RX                        0x0054 0x0358 0x0680 0x02 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO17__LPI2C6_HREQ                    0x0054 0x0358 0x0744 0x03 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO17__LPUART11_RX                    0x0054 0x0358 0x0798 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO17__GPT_MUX_INOUT3                 0x0054 0x0358 0x0704 0x05 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO17__FLEXPWM4_PWMB0                 0x0054 0x0358 0x06e4 0x06 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO17__XBAR1_XBAR_INOUT31             0x0054 0x0358 0x08b4 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO18__GPIO2_IO18                     0x0058 0x035c 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO18__LPI2C4_SDA                     0x0058 0x035c 0x0738 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO18__LPUART10_TX                    0x0058 0x035c 0x0794 0x02 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO18__LPI2C7_HREQ                    0x0058 0x035c 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO18__LPUART11_CTS_B                 0x0058 0x035c 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO18__GPT_MUX_INOUT6                 0x0058 0x035c 0x0710 0x05 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO18__FLEXPWM4_PWMA1                 0x0058 0x035c 0x06d8 0x06 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO18__XBAR1_XBAR_INOUT32             0x0058 0x035c 0x08b8 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO19__GPIO2_IO19                     0x005c 0x0360 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO19__LPI2C4_SCL                     0x005c 0x0360 0x0734 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO19__LPUART10_RX                    0x005c 0x0360 0x0790 0x02 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO19__LPI2C8_HREQ                    0x005c 0x0360 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO19__LPUART11_RTS_B                 0x005c 0x0360 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO19__GPT_MUX_INOUT9                 0x005c 0x0360 0x071c 0x05 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO19__FLEXPWM4_PWMB1                 0x005c 0x0360 0x06e8 0x06 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO19__XBAR1_XBAR_INOUT33             0x005c 0x0360 0x08bc 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO20__GPIO2_IO20                     0x0060 0x0364 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO20__PCIE1_CLKREQ_B                 0x0060 0x0364 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO20__LPUART6_TX                     0x0060 0x0364 0x07cc 0x02 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO20__LPI2C8_SDA                     0x0060 0x0364 0x075c 0x03 0x02</div><div class='add'>+#define IMX94_PAD_GPIO_IO20__LPSPI4_PCS2                    0x0060 0x0364 0x076c 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO20__LPSPI3_PCS1                    0x0060 0x0364 0x0768 0x05 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO20__FLEXPWM4_PWMA2                 0x0060 0x0364 0x06dc 0x06 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO20__XBAR1_XBAR_INOUT34             0x0060 0x0364 0x08c0 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO21__GPIO2_IO21                     0x0064 0x0368 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO21__SAI2_TX_BCLK                   0x0064 0x0368 0x07f8 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO21__LPUART6_RX                     0x0064 0x0368 0x07c8 0x02 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO21__LPI2C8_SCL                     0x0064 0x0368 0x0758 0x03 0x02</div><div class='add'>+#define IMX94_PAD_GPIO_IO21__LPSPI4_PCS1                    0x0064 0x0368 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO21__LPI2C3_HREQ                    0x0064 0x0368 0x0728 0x05 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO21__FLEXPWM4_PWMB2                 0x0064 0x0368 0x06ec 0x06 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO21__XBAR1_XBAR_INOUT35             0x0064 0x0368 0x08c4 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO22__GPIO2_IO22                     0x0068 0x036c 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO22__SAI2_MCLK                      0x0068 0x036c 0x07e8 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO22__LPUART6_CTS_B                  0x0068 0x036c 0x07c4 0x02 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO22__XBAR1_XBAR_INOUT9              0x0068 0x036c 0x0880 0x03 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO22__LPSPI4_PCS0                    0x0068 0x036c 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO22__FLEXPWM3_PWMA3                 0x0068 0x036c 0x06b4 0x05 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO22__FLEXPWM4_PWMA3                 0x0068 0x036c 0x06e0 0x06 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO22__SINC4_EMCLK0                   0x0068 0x036c 0x082c 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO23__GPIO2_IO23                     0x006c 0x0370 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO23__PCIE2_CLKREQ_B                 0x006c 0x0370 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO23__LPUART6_RTS_B                  0x006c 0x0370 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO23__XBAR1_XBAR_INOUT10             0x006c 0x0370 0x0884 0x03 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO23__LPSPI4_SIN                     0x006c 0x0370 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO23__FLEXPWM3_PWMB3                 0x006c 0x0370 0x06c4 0x05 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO23__FLEXPWM4_PWMB3                 0x006c 0x0370 0x06f0 0x06 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO23__SINC4_EMBIT0                   0x006c 0x0370 0x0820 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO24__GPIO2_IO24                     0x0070 0x0374 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO24__SAI2_RX_BCLK                   0x0070 0x0374 0x07ec 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO24__LPUART11_TX                    0x0070 0x0374 0x079c 0x02 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO24__LPI2C3_HREQ                    0x0070 0x0374 0x0728 0x03 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO24__LPSPI4_SOUT                    0x0070 0x0374 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO24__SINC_FILTER_GLUE2_BREAK        0x0070 0x0374 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO24__FLEXPWM4_PWMX0                 0x0070 0x0374 0x06f4 0x06 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO24__XBAR1_XBAR_INOUT36             0x0070 0x0374 0x08c8 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO25__GPIO2_IO25                     0x0074 0x0378 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO25__SAI2_RX_SYNC                   0x0074 0x0378 0x07f4 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO25__LPUART11_RX                    0x0074 0x0378 0x0798 0x02 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO25__LPI2C4_HREQ                    0x0074 0x0378 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO25__LPSPI4_SCK                     0x0074 0x0378 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO25__SINC_FILTER_GLUE1_BREAK        0x0074 0x0378 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO25__FLEXPWM4_PWMX1                 0x0074 0x0378 0x06f8 0x06 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO25__XBAR1_XBAR_INOUT37             0x0074 0x0378 0x08cc 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO26__GPIO2_IO26                     0x0078 0x037c 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO26__LPI2C5_SCL                     0x0078 0x037c 0x073c 0x01 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO26__LPUART12_TX                    0x0078 0x037c 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO26__GPT_MUX_INOUT4                 0x0078 0x037c 0x0708 0x03 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO26__FLEXIO1_3_1_FLEXIO0            0x0078 0x037c 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO26__SAI2_RX_DATA0                  0x0078 0x037c 0x07f0 0x05 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO26__FLEXPWM4_PWMX2                 0x0078 0x037c 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO26__XBAR1_XBAR_INOUT38             0x0078 0x037c 0x08d0 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO27__GPIO2_IO27                     0x007c 0x0380 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO27__LPI2C5_SDA                     0x007c 0x0380 0x0740 0x01 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO27__LPUART12_RX                    0x007c 0x0380 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO27__GPT_MUX_INOUT5                 0x007c 0x0380 0x070c 0x03 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO27__FLEXIO1_3_1_FLEXIO1            0x007c 0x0380 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO27__SAI2_TX_DATA0                  0x007c 0x0380 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO27__FLEXPWM4_PWMX3                 0x007c 0x0380 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO27__SINC4_MOD_CLK0                 0x007c 0x0380 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO28__GPIO2_IO28                     0x0080 0x0384 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO28__LPI2C6_SCL                     0x0080 0x0384 0x0748 0x01 0x02</div><div class='add'>+#define IMX94_PAD_GPIO_IO28__LPUART12_CTS_B                 0x0080 0x0384 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO28__GPT_MUX_INOUT7                 0x0080 0x0384 0x0714 0x03 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO28__FLEXIO1_3_1_FLEXIO2            0x0080 0x0384 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO28__SAI2_TX_SYNC                   0x0080 0x0384 0x07fc 0x05 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO28__FLEXPWM1_PWMX2                 0x0080 0x0384 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO28__XBAR1_XBAR_INOUT4              0x0080 0x0384 0x086c 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO29__GPIO2_IO29                     0x0084 0x0388 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO29__LPI2C6_SDA                     0x0084 0x0388 0x074c 0x01 0x02</div><div class='add'>+#define IMX94_PAD_GPIO_IO29__LPUART12_RTS_B                 0x0084 0x0388 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO29__I3C2_SDA                       0x0084 0x0388 0x0724 0x03 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO29__FLEXIO1_3_1_FLEXIO3            0x0084 0x0388 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO29__FLEXPWM3_PWMX0                 0x0084 0x0388 0x06c8 0x05 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO29__FLEXPWM1_PWMX3                 0x0084 0x0388 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO29__XBAR1_XBAR_INOUT5              0x0084 0x0388 0x0870 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO30__GPIO2_IO30                     0x0088 0x038c 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO30__LPIT2_TRIGGER0                 0x0088 0x038c 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO30__LPUART3_TX                     0x0088 0x038c 0x07a8 0x02 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO30__I3C2_PUR                       0x0088 0x038c 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO30__FLEXIO1_3_1_FLEXIO4            0x0088 0x038c 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO30__I3C2_PUR_B                     0x0088 0x038c 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO30__FLEXPWM2_PWMX2                 0x0088 0x038c 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO30__XBAR1_XBAR_INOUT6              0x0088 0x038c 0x0874 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO31__GPIO2_IO31                     0x008c 0x0390 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO31__LPIT2_TRIGGER1                 0x008c 0x0390 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO31__LPUART3_RX                     0x008c 0x0390 0x07a4 0x02 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO31__I3C2_SCL                       0x008c 0x0390 0x0720 0x03 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO31__FLEXIO1_3_1_FLEXIO5            0x008c 0x0390 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO31__FLEXPWM3_PWMX1                 0x008c 0x0390 0x06cc 0x05 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO31__FLEXPWM2_PWMX3                 0x008c 0x0390 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO31__XBAR1_XBAR_INOUT7              0x008c 0x0390 0x0878 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO32__GPIO3_IO0                      0x0090 0x0394 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO32__LPIT3_TRIGGER0                 0x0090 0x0394 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO32__LPUART7_TX                     0x0090 0x0394 0x07d4 0x02 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO32__GPT_MUX_INOUT8                 0x0090 0x0394 0x0718 0x03 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO32__FLEXIO1_3_1_FLEXIO6            0x0090 0x0394 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO32__FLEXPWM3_PWMA0                 0x0090 0x0394 0x06a8 0x05 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO32__SINC_FILTER_GLUE2_BREAK        0x0090 0x0394 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO32__XBAR1_XBAR_INOUT8              0x0090 0x0394 0x087c 0x07 0x01</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO33__GPIO3_IO1                      0x0094 0x0398 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO33__LPIT3_TRIGGER1                 0x0094 0x0398 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO33__LPUART7_RX                     0x0094 0x0398 0x07d0 0x02 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO33__GPT_MUX_INOUT1                 0x0094 0x0398 0x0700 0x03 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO33__FLEXIO1_3_1_FLEXIO7            0x0094 0x0398 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO33__FLEXPWM3_PWMB0                 0x0094 0x0398 0x06b8 0x05 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO33__SINC_FILTER_GLUE1_BREAK        0x0094 0x0398 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO33__XBAR1_XBAR_INOUT9              0x0094 0x0398 0x0880 0x07 0x01</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO34__GPIO3_IO2                      0x0098 0x039c 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO34__LPI2C7_SDA                     0x0098 0x039c 0x0754 0x01 0x02</div><div class='add'>+#define IMX94_PAD_GPIO_IO34__CAN2_TX                        0x0098 0x039c 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO34__ECAT_SDA                       0x0098 0x039c 0x062c 0x03 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO34__FLEXIO1_3_1_FLEXIO8            0x0098 0x039c 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO34__FLEXPWM3_PWMA1                 0x0098 0x039c 0x06ac 0x05 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO34__FLEXPWM1_PWMX0                 0x0098 0x039c 0x0698 0x06 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO34__XBAR1_XBAR_INOUT10             0x0098 0x039c 0x0884 0x07 0x01</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO35__GPIO3_IO3                      0x009c 0x03a0 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO35__LPI2C7_SCL                     0x009c 0x03a0 0x0750 0x01 0x02</div><div class='add'>+#define IMX94_PAD_GPIO_IO35__CAN2_RX                        0x009c 0x03a0 0x067c 0x02 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO35__ECAT_SCL                       0x009c 0x03a0 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO35__FLEXIO1_3_1_FLEXIO9            0x009c 0x03a0 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO35__FLEXPWM3_PWMB1                 0x009c 0x03a0 0x06bc 0x05 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO35__FLEXPWM1_PWMX1                 0x009c 0x03a0 0x069c 0x06 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO35__XBAR1_XBAR_INOUT11             0x009c 0x03a0 0x0888 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO36__USDHC2_WP                      0x00a0 0x03a4 0x0854 0x03 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO36__FLEXIO1_3_1_FLEXIO10           0x00a0 0x03a4 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO36__FLEXPWM3_PWMA2                 0x00a0 0x03a4 0x06b0 0x05 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO36__FLEXPWM2_PWMX0                 0x00a0 0x03a4 0x06a0 0x06 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO36__XBAR1_XBAR_INOUT12             0x00a0 0x03a4 0x088c 0x07 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO36__GPIO3_IO4                      0x00a0 0x03a4 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO36__LPI2C8_SDA                     0x00a0 0x03a4 0x075c 0x01 0x03</div><div class='add'>+#define IMX94_PAD_GPIO_IO36__CAN4_TX                        0x00a0 0x03a4 0x0000 0x02 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO37__GPIO3_IO5                      0x00a4 0x03a8 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO37__LPI2C8_SCL                     0x00a4 0x03a8 0x0758 0x01 0x03</div><div class='add'>+#define IMX94_PAD_GPIO_IO37__CAN4_RX                        0x00a4 0x03a8 0x0684 0x02 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO37__LPI2C5_HREQ                    0x00a4 0x03a8 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO37__FLEXIO1_3_1_FLEXIO11           0x00a4 0x03a8 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO37__FLEXPWM3_PWMB2                 0x00a4 0x03a8 0x06c0 0x05 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO37__FLEXPWM2_PWMX1                 0x00a4 0x03a8 0x06a4 0x06 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO37__XBAR1_XBAR_INOUT13             0x00a4 0x03a8 0x0890 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO38__GPIO3_IO6                      0x00a8 0x03ac 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO38__NETC_1588MUX_INOUT0            0x00a8 0x03ac 0x064c 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO38__LPI2C3_SDA                     0x00a8 0x03ac 0x0730 0x02 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO38__LPIT3_TRIGGER2                 0x00a8 0x03ac 0x0764 0x03 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO38__FLEXIO1_3_1_FLEXIO12           0x00a8 0x03ac 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO38__LPUART3_CTS_B                  0x00a8 0x03ac 0x07a0 0x05 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO38__FLEXPWM3_PWMX0                 0x00a8 0x03ac 0x06c8 0x06 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO38__XBAR1_XBAR_INOUT14             0x00a8 0x03ac 0x0894 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO39__GPIO3_IO7                      0x00ac 0x03b0 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO39__NETC_1588MUX_INOUT1            0x00ac 0x03b0 0x0650 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO39__LPI2C3_SCL                     0x00ac 0x03b0 0x072c 0x02 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO39__LPIT2_TRIGGER2                 0x00ac 0x03b0 0x0760 0x03 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO39__FLEXIO1_3_1_FLEXIO13           0x00ac 0x03b0 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO39__LPUART3_RTS_B                  0x00ac 0x03b0 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO39__FLEXPWM3_PWMX1                 0x00ac 0x03b0 0x06cc 0x06 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO39__XBAR1_XBAR_INOUT15             0x00ac 0x03b0 0x0898 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO40__GPIO3_IO8                      0x00b0 0x03b4 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO40__NETC_1588MUX_INOUT2            0x00b0 0x03b4 0x0654 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO40__LPI2C7_SDA                     0x00b0 0x03b4 0x0754 0x02 0x03</div><div class='add'>+#define IMX94_PAD_GPIO_IO40__LPUART4_TX                     0x00b0 0x03b4 0x07b4 0x03 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO40__FLEXIO1_3_1_FLEXIO14           0x00b0 0x03b4 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO40__FLEXPWM3_PWMX2                 0x00b0 0x03b4 0x06d0 0x05 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO40__FLEXPWM4_PWMX0                 0x00b0 0x03b4 0x06f4 0x06 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO40__XBAR1_XBAR_INOUT16             0x00b0 0x03b4 0x089c 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO41__GPIO3_IO9                      0x00b4 0x03b8 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO41__NETC_1588MUX_INOUT3            0x00b4 0x03b8 0x0658 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO41__LPI2C7_SCL                     0x00b4 0x03b8 0x0750 0x02 0x03</div><div class='add'>+#define IMX94_PAD_GPIO_IO41__LPUART4_RX                     0x00b4 0x03b8 0x07b0 0x03 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO41__FLEXIO1_3_1_FLEXIO15           0x00b4 0x03b8 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO41__LPI2C6_HREQ                    0x00b4 0x03b8 0x0744 0x05 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO41__FLEXPWM4_PWMX1                 0x00b4 0x03b8 0x06f8 0x06 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO41__XBAR1_XBAR_INOUT17             0x00b4 0x03b8 0x08a0 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO42__GPIO3_IO10                     0x00b8 0x03bc 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO42__SAI3_TX_BCLK                   0x00b8 0x03bc 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO42__PDM_BIT_STREAM2                0x00b8 0x03bc 0x0618 0x02 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO42__XBAR1_XBAR_INOUT11             0x00b8 0x03bc 0x0888 0x03 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO42__LPUART3_TX                     0x00b8 0x03bc 0x07a8 0x04 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO42__LPSPI4_PCS2                    0x00b8 0x03bc 0x076c 0x05 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO42__LPUART4_CTS_B                  0x00b8 0x03bc 0x07ac 0x06 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO42__SINC4_EMCLK1                   0x00b8 0x03bc 0x0830 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO43__GPIO3_IO11                     0x00bc 0x03c0 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO43__SAI3_MCLK                      0x00bc 0x03c0 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO43__XBAR1_XBAR_INOUT12             0x00bc 0x03c0 0x088c 0x03 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO43__LPUART3_RX                     0x00bc 0x03c0 0x07a4 0x04 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO43__LPSPI3_PCS1                    0x00bc 0x03c0 0x0768 0x05 0x02</div><div class='add'>+#define IMX94_PAD_GPIO_IO43__LPUART4_RTS_B                  0x00bc 0x03c0 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO43__SINC4_EMBIT1                   0x00bc 0x03c0 0x0824 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO44__GPIO3_IO12                     0x00c0 0x03c4 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO44__SAI3_RX_BCLK                   0x00c0 0x03c4 0x0800 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO44__PDM_BIT_STREAM1                0x00c0 0x03c4 0x0614 0x02 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO44__LPUART9_TX                     0x00c0 0x03c4 0x07e4 0x03 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO44__LPSPI5_PCS0                    0x00c0 0x03c4 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO44__LPI2C3_SDA                     0x00c0 0x03c4 0x0730 0x05 0x02</div><div class='add'>+#define IMX94_PAD_GPIO_IO44__TPM5_CH2                       0x00c0 0x03c4 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO44__SINC_FILTER_GLUE4_BREAK        0x00c0 0x03c4 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO45__GPIO3_IO13                     0x00c4 0x03c8 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO45__SAI3_RX_SYNC                   0x00c4 0x03c8 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO45__PDM_BIT_STREAM3                0x00c4 0x03c8 0x061c 0x02 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO45__LPUART9_RX                     0x00c4 0x03c8 0x07e0 0x03 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO45__LPSPI5_SIN                     0x00c4 0x03c8 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO45__LPI2C3_SCL                     0x00c4 0x03c8 0x072c 0x05 0x02</div><div class='add'>+#define IMX94_PAD_GPIO_IO45__TPM6_CH2                       0x00c4 0x03c8 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO45__SAI3_TX_DATA0                  0x00c4 0x03c8 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO46__GPIO3_IO14                     0x00c8 0x03cc 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO46__SAI3_RX_DATA0                  0x00c8 0x03cc 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO46__PDM_BIT_STREAM0                0x00c8 0x03cc 0x0610 0x02 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO46__LPUART9_CTS_B                  0x00c8 0x03cc 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO46__LPSPI5_SOUT                    0x00c8 0x03cc 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO46__LPI2C4_SDA                     0x00c8 0x03cc 0x0738 0x05 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO46__TPM3_CH1                       0x00c8 0x03cc 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO46__EWM_OUT_B                      0x00c8 0x03cc 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO47__GPIO3_IO15                     0x00cc 0x03d0 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO47__SAI3_TX_DATA0                  0x00cc 0x03d0 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO47__PDM_CLK                        0x00cc 0x03d0 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO47__LPUART9_RTS_B                  0x00cc 0x03d0 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO47__LPSPI5_SCK                     0x00cc 0x03d0 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO47__LPI2C4_SCL                     0x00cc 0x03d0 0x0734 0x05 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO47__TPM4_CH1                       0x00cc 0x03d0 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO47__SAI3_RX_BCLK                   0x00cc 0x03d0 0x0800 0x07 0x01</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO48__GPIO3_IO16                     0x00d0 0x03d4 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO48__USDHC3_CLK                     0x00d0 0x03d4 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO48__CAN5_TX                        0x00d0 0x03d4 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO48__LPUART10_TX                    0x00d0 0x03d4 0x0794 0x03 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO48__TPM5_CH1                       0x00d0 0x03d4 0x0840 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO48__TPM6_EXTCLK                    0x00d0 0x03d4 0x0850 0x05 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO48__LPI2C5_SDA                     0x00d0 0x03d4 0x0740 0x06 0x02</div><div class='add'>+#define IMX94_PAD_GPIO_IO48__SINC4_EMCLK2                   0x00d0 0x03d4 0x0834 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO49__GPIO3_IO17                     0x00d4 0x03d8 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO49__USDHC3_CMD                     0x00d4 0x03d8 0x0858 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO49__CAN5_RX                        0x00d4 0x03d8 0x0688 0x02 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO49__LPUART10_RX                    0x00d4 0x03d8 0x0790 0x03 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO49__TPM6_CH1                       0x00d4 0x03d8 0x0848 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO49__XBAR1_XBAR_INOUT13             0x00d4 0x03d8 0x0890 0x05 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO49__LPI2C5_SCL                     0x00d4 0x03d8 0x073c 0x06 0x02</div><div class='add'>+#define IMX94_PAD_GPIO_IO49__SINC4_EMBIT2                   0x00d4 0x03d8 0x0828 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO50__GPIO3_IO18                     0x00d8 0x03dc 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO50__USDHC3_DATA0                   0x00d8 0x03dc 0x085c 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO50__XBAR1_XBAR_INOUT14             0x00d8 0x03dc 0x0894 0x02 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO50__LPUART10_CTS_B                 0x00d8 0x03dc 0x078c 0x03 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO50__TPM3_CH3                       0x00d8 0x03dc 0x0838 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO50__JTAG_MUX_TDO                   0x00d8 0x03dc 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO50__LPSPI6_PCS1                    0x00d8 0x03dc 0x0774 0x06 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO50__SINC4_EMCLK3                   0x00d8 0x03dc 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO51__GPIO3_IO19                     0x00dc 0x03e0 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO51__USDHC3_DATA1                   0x00dc 0x03e0 0x0860 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO51__CAN2_TX                        0x00dc 0x03e0 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO51__LPUART10_RTS_B                 0x00dc 0x03e0 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO51__TPM4_CH3                       0x00dc 0x03e0 0x083c 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO51__JTAG_MUX_TCK                   0x00dc 0x03e0 0x0928 0x05 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO51__LPSPI7_PCS1                    0x00dc 0x03e0 0x0778 0x06 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO51__SINC4_EMBIT3                   0x00dc 0x03e0 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO52__GPIO3_IO20                     0x00e0 0x03e4 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO52__USDHC3_DATA2                   0x00e0 0x03e4 0x0864 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO52__PDM_BIT_STREAM1                0x00e0 0x03e4 0x0614 0x02 0x02</div><div class='add'>+#define IMX94_PAD_GPIO_IO52__LPSPI4_PCS2                    0x00e0 0x03e4 0x076c 0x03 0x02</div><div class='add'>+#define IMX94_PAD_GPIO_IO52__TPM5_CH3                       0x00e0 0x03e4 0x0844 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO52__JTAG_MUX_TDI                   0x00e0 0x03e4 0x092c 0x05 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO52__LPSPI8_PCS1                    0x00e0 0x03e4 0x077c 0x06 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO52__SAI3_TX_SYNC                   0x00e0 0x03e4 0x0804 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO53__GPIO3_IO21                     0x00e4 0x03e8 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO53__USDHC3_DATA3                   0x00e4 0x03e8 0x0868 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO53__CAN2_RX                        0x00e4 0x03e8 0x067c 0x02 0x02</div><div class='add'>+#define IMX94_PAD_GPIO_IO53__LPSPI3_PCS1                    0x00e4 0x03e8 0x0768 0x03 0x03</div><div class='add'>+#define IMX94_PAD_GPIO_IO53__TPM6_CH3                       0x00e4 0x03e8 0x084c 0x04 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO53__JTAG_MUX_TMS                   0x00e4 0x03e8 0x0930 0x05 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO53__LPSPI5_PCS1                    0x00e4 0x03e8 0x0770 0x06 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO53__SINC4_MOD_CLK1                 0x00e4 0x03e8 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO54__GPIO3_IO22                     0x00e8 0x03ec 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO54__NETC_1588MUX_INOUT4            0x00e8 0x03ec 0x065c 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO54__CAN4_TX                        0x00e8 0x03ec 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO54__LPIT3_TRIGGER2                 0x00e8 0x03ec 0x0764 0x03 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO54__LPSPI6_PCS1                    0x00e8 0x03ec 0x0774 0x04 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO54__TPM3_CH3                       0x00e8 0x03ec 0x0838 0x05 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO54__SINC3_EMCLK0                   0x00e8 0x03ec 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO54__XBAR1_XBAR_INOUT18             0x00e8 0x03ec 0x08a4 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO55__GPIO3_IO23                     0x00ec 0x03f0 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO55__NETC_1588MUX_INOUT5            0x00ec 0x03f0 0x0660 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO55__CAN4_RX                        0x00ec 0x03f0 0x0684 0x02 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO55__LPIT2_TRIGGER2                 0x00ec 0x03f0 0x0760 0x03 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO55__LPSPI7_PCS1                    0x00ec 0x03f0 0x0778 0x04 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO55__TPM4_CH3                       0x00ec 0x03f0 0x083c 0x05 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO55__SINC3_EMBIT0                   0x00ec 0x03f0 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO55__XBAR1_XBAR_INOUT19             0x00ec 0x03f0 0x08a8 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO56__GPIO3_IO24                     0x00f0 0x03f4 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO56__NETC_1588MUX_INOUT6            0x00f0 0x03f4 0x0664 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO56__CAN5_TX                        0x00f0 0x03f4 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO56__LPIT3_TRIGGER3                 0x00f0 0x03f4 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO56__LPSPI8_PCS1                    0x00f0 0x03f4 0x077c 0x04 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO56__SAI3_TX_SYNC                   0x00f0 0x03f4 0x0804 0x05 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO56__SINC3_EMCLK1                   0x00f0 0x03f4 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO56__XBAR1_XBAR_INOUT20             0x00f0 0x03f4 0x08ac 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_GPIO_IO57__GPIO3_IO25                     0x00f4 0x03f8 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO57__NETC_1588MUX_INOUT7            0x00f4 0x03f8 0x0668 0x01 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO57__CAN5_RX                        0x00f4 0x03f8 0x0688 0x02 0x02</div><div class='add'>+#define IMX94_PAD_GPIO_IO57__LPIT2_TRIGGER3                 0x00f4 0x03f8 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO57__LPSPI5_PCS1                    0x00f4 0x03f8 0x0770 0x04 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO57__TPM6_CH3                       0x00f4 0x03f8 0x084c 0x05 0x01</div><div class='add'>+#define IMX94_PAD_GPIO_IO57__SINC3_EMBIT1                   0x00f4 0x03f8 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_GPIO_IO57__ENET_REF_CLK_ROOT              0x00f4 0x03f8 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_CCM_CLKO1__CLKO_1                         0x00f8 0x03fc 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_CCM_CLKO1__NETC_1588MUX_INOUT8            0x00f8 0x03fc 0x066c 0x01 0x00</div><div class='add'>+#define IMX94_PAD_CCM_CLKO1__LPUART9_TX                     0x00f8 0x03fc 0x07e4 0x02 0x01</div><div class='add'>+#define IMX94_PAD_CCM_CLKO1__ECAT_LED_RUN                   0x00f8 0x03fc 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_CCM_CLKO1__TPM6_EXTCLK                    0x00f8 0x03fc 0x0850 0x04 0x01</div><div class='add'>+#define IMX94_PAD_CCM_CLKO1__GPIO4_IO0                      0x00f8 0x03fc 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_CCM_CLKO1__SINC3_EMCLK2                   0x00f8 0x03fc 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_CCM_CLKO1__XBAR1_XBAR_INOUT22             0x00f8 0x03fc 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_CCM_CLKO2__CLKO_2                         0x00fc 0x0400 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_CCM_CLKO2__NETC_1588MUX_INOUT9            0x00fc 0x0400 0x0670 0x01 0x00</div><div class='add'>+#define IMX94_PAD_CCM_CLKO2__LPUART9_RX                     0x00fc 0x0400 0x07e0 0x02 0x01</div><div class='add'>+#define IMX94_PAD_CCM_CLKO2__ECAT_LED_ERR                   0x00fc 0x0400 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_CCM_CLKO2__TPM5_CH1                       0x00fc 0x0400 0x0840 0x04 0x01</div><div class='add'>+#define IMX94_PAD_CCM_CLKO2__GPIO4_IO1                      0x00fc 0x0400 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_CCM_CLKO2__SINC3_EMBIT2                   0x00fc 0x0400 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_CCM_CLKO2__XBAR1_XBAR_INOUT23             0x00fc 0x0400 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_CCM_CLKO3__CLKO_3                         0x0100 0x0404 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_CCM_CLKO3__NETC_1588MUX_INOUT10           0x0100 0x0404 0x0674 0x01 0x00</div><div class='add'>+#define IMX94_PAD_CCM_CLKO3__CAN3_TX                        0x0100 0x0404 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_CCM_CLKO3__ECAT_LED_STATE_RUN             0x0100 0x0404 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_CCM_CLKO3__TPM6_CH1                       0x0100 0x0404 0x0848 0x04 0x01</div><div class='add'>+#define IMX94_PAD_CCM_CLKO3__GPIO4_IO2                      0x0100 0x0404 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_CCM_CLKO3__SINC3_EMCLK3                   0x0100 0x0404 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_CCM_CLKO3__ENET_REF_CLK_ROOT              0x0100 0x0404 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_CCM_CLKO4__CLKO_4                         0x0104 0x0408 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_CCM_CLKO4__NETC_1588MUX_INOUT11           0x0104 0x0408 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_CCM_CLKO4__CAN3_RX                        0x0104 0x0408 0x0680 0x02 0x01</div><div class='add'>+#define IMX94_PAD_CCM_CLKO4__ECAT_RESET_OUT                 0x0104 0x0408 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_CCM_CLKO4__TPM5_CH3                       0x0104 0x0408 0x0844 0x04 0x01</div><div class='add'>+#define IMX94_PAD_CCM_CLKO4__GPIO4_IO3                      0x0104 0x0408 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_CCM_CLKO4__SINC3_EMBIT3                   0x0104 0x0408 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_CCM_CLKO4__XBAR1_XBAR_INOUT25             0x0104 0x0408 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH2_MDC_GPIO1__NETC_EMDC                 0x0108 0x040c 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_MDC_GPIO1__NETC_ETH2_SLV_MDC         0x0108 0x040c 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_MDC_GPIO1__I3C2_SCL                  0x0108 0x040c 0x0720 0x02 0x02</div><div class='add'>+#define IMX94_PAD_ETH2_MDC_GPIO1__USB1_OTG_ID               0x0108 0x040c 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_MDC_GPIO1__FLEXIO2_FLEXIO0           0x0108 0x040c 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_MDC_GPIO1__GPIO6_IO0                 0x0108 0x040c 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_MDC_GPIO1__FLEXPWM2_PWMX0            0x0108 0x040c 0x06a0 0x06 0x01</div><div class='add'>+#define IMX94_PAD_ETH2_MDC_GPIO1__XBAR1_XBAR_INOUT30        0x0108 0x040c 0x08b0 0x07 0x01</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH2_MDIO_GPIO2__NETC_EMDIO               0x010c 0x0410 0x0678 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_MDIO_GPIO2__NETC_ETH2_SLV_MDIO       0x010c 0x0410 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_MDIO_GPIO2__I3C2_SDA                 0x010c 0x0410 0x0724 0x02 0x02</div><div class='add'>+#define IMX94_PAD_ETH2_MDIO_GPIO2__USB1_OTG_PWR             0x010c 0x0410 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_MDIO_GPIO2__FLEXIO2_FLEXIO1          0x010c 0x0410 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_MDIO_GPIO2__GPIO6_IO1                0x010c 0x0410 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_MDIO_GPIO2__FLEXPWM2_PWMX1           0x010c 0x0410 0x06a4 0x06 0x01</div><div class='add'>+#define IMX94_PAD_ETH2_MDIO_GPIO2__XBAR1_XBAR_INOUT31       0x010c 0x0410 0x08b4 0x07 0x01</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH2_TXD3__NETC_PINMUX_ETH2_TXD3          0x0110 0x0414 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_TXD3__LPUART3_DCD_B                  0x0110 0x0414 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_TXD3__CAN2_TX                        0x0110 0x0414 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_TXD3__USB2_OTG_ID                    0x0110 0x0414 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_TXD3__FLEXIO2_FLEXIO2                0x0110 0x0414 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_TXD3__GPIO6_IO2                      0x0110 0x0414 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_TXD3__FLEXPWM2_PWMA0                 0x0110 0x0414 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_TXD3__XBAR1_XBAR_INOUT32             0x0110 0x0414 0x08b8 0x07 0x01</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH2_TXD2__NETC_PINMUX_ETH2_TXD2          0x0114 0x0418 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_TXD2__ETH2_RMII_REF50_CLK            0x0114 0x0418 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_TXD2__CAN2_RX                        0x0114 0x0418 0x067c 0x02 0x03</div><div class='add'>+#define IMX94_PAD_ETH2_TXD2__USB2_OTG_OC                    0x0114 0x0418 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_TXD2__FLEXIO2_FLEXIO3                0x0114 0x0418 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_TXD2__GPIO6_IO3                      0x0114 0x0418 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_TXD2__FLEXPWM2_PWMB0                 0x0114 0x0418 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_TXD2__XBAR1_XBAR_INOUT33             0x0114 0x0418 0x08bc 0x07 0x01</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH2_TXD1__NETC_PINMUX_ETH2_TXD1          0x0118 0x041c 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_TXD1__LPUART3_RTS_B                  0x0118 0x041c 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_TXD1__ECAT_CLK25                     0x0118 0x041c 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_TXD1__USB1_OTG_OC                    0x0118 0x041c 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_TXD1__FLEXIO2_FLEXIO4                0x0118 0x041c 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_TXD1__GPIO6_IO4                      0x0118 0x041c 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_TXD1__FLEXPWM2_PWMA1                 0x0118 0x041c 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_TXD1__XBAR1_XBAR_INOUT34             0x0118 0x041c 0x08c0 0x07 0x01</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH2_TXD0__NETC_PINMUX_ETH2_TXD0          0x011c 0x0420 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_TXD0__LPUART3_TX                     0x011c 0x0420 0x07a8 0x01 0x02</div><div class='add'>+#define IMX94_PAD_ETH2_TXD0__I3C2_PUR                       0x011c 0x0420 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_TXD0__I3C2_PUR_B                     0x011c 0x0420 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_TXD0__FLEXIO2_FLEXIO5                0x011c 0x0420 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_TXD0__GPIO6_IO5                      0x011c 0x0420 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_TXD0__FLEXPWM2_PWMB1                 0x011c 0x0420 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_TXD0__XBAR1_XBAR_INOUT35             0x011c 0x0420 0x08c4 0x07 0x01</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH2_TX_CTL__NETC_PINMUX_ETH2_TX_CTL      0x0120 0x0424 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_TX_CTL__LPUART3_DTR_B                0x0120 0x0424 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_TX_CTL__ECAT_LED_RUN                 0x0120 0x0424 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_TX_CTL__FLEXIO2_FLEXIO6              0x0120 0x0424 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_TX_CTL__GPIO6_IO6                    0x0120 0x0424 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_TX_CTL__FLEXPWM2_PWMA2               0x0120 0x0424 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_TX_CTL__XBAR1_XBAR_INOUT36           0x0120 0x0424 0x08c8 0x07 0x01</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH2_TX_CLK__NETC_PINMUX_ETH2_TX_CLK      0x0124 0x0428 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_TX_CLK__ECAT_LED_ERR                 0x0124 0x0428 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_TX_CLK__FLEXIO2_FLEXIO7              0x0124 0x0428 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_TX_CLK__GPIO6_IO7                    0x0124 0x0428 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_TX_CLK__FLEXPWM2_PWMB2               0x0124 0x0428 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_TX_CLK__XBAR1_XBAR_INOUT37           0x0124 0x0428 0x08cc 0x07 0x01</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH2_RX_CTL__NETC_PINMUX_ETH2_RX_CTL      0x0128 0x042c 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_RX_CTL__LPUART3_DSR_B                0x0128 0x042c 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_RX_CTL__ECAT_LED_STATE_RUN           0x0128 0x042c 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_RX_CTL__USB2_OTG_PWR                 0x0128 0x042c 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_RX_CTL__FLEXIO2_FLEXIO8              0x0128 0x042c 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_RX_CTL__GPIO6_IO8                    0x0128 0x042c 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_RX_CTL__FLEXPWM2_PWMA3               0x0128 0x042c 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_RX_CTL__SINC4_EMCLK0                 0x0128 0x042c 0x082c 0x07 0x01</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH2_RX_CLK__NETC_PINMUX_ETH2_RX_CLK      0x012c 0x0430 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_RX_CLK__LPUART3_RIN_B                0x012c 0x0430 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_RX_CLK__ECAT_RESET_OUT               0x012c 0x0430 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_RX_CLK__XBAR1_XBAR_INOUT38           0x012c 0x0430 0x08d0 0x03 0x01</div><div class='add'>+#define IMX94_PAD_ETH2_RX_CLK__FLEXIO2_FLEXIO9              0x012c 0x0430 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_RX_CLK__GPIO6_IO9                    0x012c 0x0430 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_RX_CLK__FLEXPWM2_PWMB3               0x012c 0x0430 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_RX_CLK__SINC4_EMBIT0                 0x012c 0x0430 0x0820 0x07 0x01</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH2_RXD0__NETC_PINMUX_ETH2_RXD0          0x0130 0x0434 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_RXD0__LPUART3_RX                     0x0130 0x0434 0x07a4 0x01 0x02</div><div class='add'>+#define IMX94_PAD_ETH2_RXD0__FLEXIO2_FLEXIO10               0x0130 0x0434 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_RXD0__GPIO6_IO10                     0x0130 0x0434 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_RXD0__DIG_ENCODER2_DATA_EN           0x0130 0x0434 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_RXD0__XBAR1_XBAR_INOUT39             0x0130 0x0434 0x08d4 0x07 0x01</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH2_RXD1__NETC_PINMUX_ETH2_RXD1          0x0134 0x0438 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_RXD1__LPUART3_CTS_B                  0x0134 0x0438 0x07a0 0x01 0x01</div><div class='add'>+#define IMX94_PAD_ETH2_RXD1__LPTMR2_ALT0                    0x0134 0x0438 0x0780 0x03 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_RXD1__FLEXIO2_FLEXIO11               0x0134 0x0438 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_RXD1__GPIO6_IO11                     0x0134 0x0438 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_RXD1__DIG_ENCODER2_DATA_CLK          0x0134 0x0438 0x068c 0x06 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_RXD1__XBAR1_XBAR_INOUT40             0x0134 0x0438 0x08d8 0x07 0x01</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH2_RXD2__NETC_PINMUX_ETH2_RXD2          0x0138 0x043c 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_RXD2__LPTMR2_ALT1                    0x0138 0x043c 0x0784 0x03 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_RXD2__FLEXIO2_FLEXIO12               0x0138 0x043c 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_RXD2__GPIO6_IO12                     0x0138 0x043c 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_RXD2__DIG_ENCODER2_DATA_OUT          0x0138 0x043c 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_RXD2__XBAR1_XBAR_INOUT41             0x0138 0x043c 0x08dc 0x07 0x01</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH2_RXD3__NETC_PINMUX_ETH2_RXD3          0x013c 0x0440 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_RXD3__LPTMR2_ALT2                    0x013c 0x0440 0x0788 0x03 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_RXD3__FLEXIO2_FLEXIO13               0x013c 0x0440 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_RXD3__GPIO6_IO13                     0x013c 0x0440 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_RXD3__DIG_ENCODER2_DATA_IN           0x013c 0x0440 0x0690 0x06 0x00</div><div class='add'>+#define IMX94_PAD_ETH2_RXD3__XBAR1_XBAR_INOUT42             0x013c 0x0440 0x08e0 0x07 0x01</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH3_MDC_GPIO1__NETC_EMDC                 0x0140 0x0444 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_MDC_GPIO1__LPUART4_DCD_B             0x0140 0x0444 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_MDC_GPIO1__NETC_ETH3_SLV_MDC         0x0140 0x0444 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_MDC_GPIO1__SAI4_TX_SYNC              0x0140 0x0444 0x081c 0x03 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_MDC_GPIO1__FLEXIO2_FLEXIO14          0x0140 0x0444 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_MDC_GPIO1__GPIO6_IO14                0x0140 0x0444 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_MDC_GPIO1__FLEXPWM1_PWMX0            0x0140 0x0444 0x0698 0x06 0x01</div><div class='add'>+#define IMX94_PAD_ETH3_MDC_GPIO1__SINC4_MOD_CLK0            0x0140 0x0444 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH3_MDIO_GPIO2__NETC_EMDIO               0x0144 0x0448 0x0678 0x00 0x01</div><div class='add'>+#define IMX94_PAD_ETH3_MDIO_GPIO2__LPUART4_RIN_B            0x0144 0x0448 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_MDIO_GPIO2__NETC_ETH3_SLV_MDIO       0x0144 0x0448 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_MDIO_GPIO2__SAI4_TX_BCLK             0x0144 0x0448 0x0818 0x03 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_MDIO_GPIO2__FLEXIO2_FLEXIO15         0x0144 0x0448 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_MDIO_GPIO2__GPIO6_IO15               0x0144 0x0448 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_MDIO_GPIO2__FLEXPWM1_PWMX1           0x0144 0x0448 0x069c 0x06 0x01</div><div class='add'>+#define IMX94_PAD_ETH3_MDIO_GPIO2__SINC4_MOD_CLK1           0x0144 0x0448 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH3_TXD3__NETC_PINMUX_ETH3_TXD3          0x0148 0x044c 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_TXD3__XSPI_SLV_DATA7                 0x0148 0x044c 0x0924 0x02 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_TXD3__SAI4_TX_DATA0                  0x0148 0x044c 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_TXD3__LPUART3_TX                     0x0148 0x044c 0x07a8 0x04 0x03</div><div class='add'>+#define IMX94_PAD_ETH3_TXD3__GPIO6_IO16                     0x0148 0x044c 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_TXD3__FLEXPWM1_PWMA0                 0x0148 0x044c 0x0000 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH3_TXD2__NETC_PINMUX_ETH3_TXD2          0x014c 0x0450 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_TXD2__ETH3_RMII_REF50_CLK            0x014c 0x0450 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_TXD2__XSPI_SLV_DATA6                 0x014c 0x0450 0x0920 0x02 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_TXD2__SAI4_RX_SYNC                   0x014c 0x0450 0x0814 0x03 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_TXD2__GPIO6_IO17                     0x014c 0x0450 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_TXD2__FLEXPWM1_PWMB0                 0x014c 0x0450 0x0000 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH3_TXD1__NETC_PINMUX_ETH3_TXD1          0x0150 0x0454 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_TXD1__LPUART4_RTS_B                  0x0150 0x0454 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_TXD1__XSPI_SLV_DATA5                 0x0150 0x0454 0x091c 0x02 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_TXD1__SAI4_RX_BCLK                   0x0150 0x0454 0x080c 0x03 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_TXD1__GPIO6_IO18                     0x0150 0x0454 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_TXD1__FLEXPWM1_PWMA1                 0x0150 0x0454 0x0000 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH3_TXD0__NETC_PINMUX_ETH3_TXD0          0x0154 0x0458 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_TXD0__LPUART4_TX                     0x0154 0x0458 0x07b4 0x01 0x02</div><div class='add'>+#define IMX94_PAD_ETH3_TXD0__XSPI_SLV_DATA4                 0x0154 0x0458 0x0918 0x02 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_TXD0__SAI4_RX_DATA0                  0x0154 0x0458 0x0810 0x03 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_TXD0__GPIO6_IO19                     0x0154 0x0458 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_TXD0__FLEXPWM1_PWMB1                 0x0154 0x0458 0x0000 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH3_TX_CTL__NETC_PINMUX_ETH3_TX_CTL      0x0158 0x045c 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_TX_CTL__LPUART4_DTR_B                0x0158 0x045c 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_TX_CTL__XSPI_SLV_DQS                 0x0158 0x045c 0x0900 0x02 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_TX_CTL__SAI4_MCLK                    0x0158 0x045c 0x0808 0x03 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_TX_CTL__LPUART3_RX                   0x0158 0x045c 0x07a4 0x04 0x03</div><div class='add'>+#define IMX94_PAD_ETH3_TX_CTL__GPIO6_IO20                   0x0158 0x045c 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_TX_CTL__FLEXPWM1_PWMA2               0x0158 0x045c 0x0000 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH3_TX_CLK__NETC_PINMUX_ETH3_TX_CLK      0x015c 0x0460 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_TX_CLK__XSPI_SLV_CLK                 0x015c 0x0460 0x0904 0x02 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_TX_CLK__SAI2_TX_SYNC                 0x015c 0x0460 0x07fc 0x03 0x01</div><div class='add'>+#define IMX94_PAD_ETH3_TX_CLK__LPUART3_CTS_B                0x015c 0x0460 0x07a0 0x04 0x02</div><div class='add'>+#define IMX94_PAD_ETH3_TX_CLK__GPIO6_IO21                   0x015c 0x0460 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_TX_CLK__FLEXPWM1_PWMB2               0x015c 0x0460 0x0000 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH3_RX_CTL__NETC_PINMUX_ETH3_RX_CTL      0x0160 0x0464 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_RX_CTL__LPUART4_DSR_B                0x0160 0x0464 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_RX_CTL__XSPI_SLV_CS                  0x0160 0x0464 0x08fc 0x02 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_RX_CTL__SAI2_TX_BCLK                 0x0160 0x0464 0x07f8 0x03 0x01</div><div class='add'>+#define IMX94_PAD_ETH3_RX_CTL__XBAR1_XBAR_INOUT43           0x0160 0x0464 0x08e4 0x04 0x01</div><div class='add'>+#define IMX94_PAD_ETH3_RX_CTL__GPIO6_IO22                   0x0160 0x0464 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_RX_CTL__FLEXPWM1_PWMA3               0x0160 0x0464 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_RX_CTL__SINC4_EMCLK1                 0x0160 0x0464 0x0830 0x07 0x01</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH3_RX_CLK__NETC_PINMUX_ETH3_RX_CLK      0x0164 0x0468 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_RX_CLK__LPUART4_CTS_B                0x0164 0x0468 0x07ac 0x01 0x01</div><div class='add'>+#define IMX94_PAD_ETH3_RX_CLK__XSPI_SLV_DATA3               0x0164 0x0468 0x0914 0x02 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_RX_CLK__SAI2_TX_DATA0                0x0164 0x0468 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_RX_CLK__XBAR1_XBAR_INOUT44           0x0164 0x0468 0x08e8 0x04 0x01</div><div class='add'>+#define IMX94_PAD_ETH3_RX_CLK__GPIO6_IO23                   0x0164 0x0468 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_RX_CLK__FLEXPWM1_PWMB3               0x0164 0x0468 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_RX_CLK__SINC4_EMBIT1                 0x0164 0x0468 0x0824 0x07 0x01</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH3_RXD0__NETC_PINMUX_ETH3_RXD0          0x0168 0x046c 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_RXD0__LPUART4_RX                     0x0168 0x046c 0x07b0 0x01 0x02</div><div class='add'>+#define IMX94_PAD_ETH3_RXD0__XSPI_SLV_DATA2                 0x0168 0x046c 0x0910 0x02 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_RXD0__SAI2_RX_SYNC                   0x0168 0x046c 0x07f4 0x03 0x01</div><div class='add'>+#define IMX94_PAD_ETH3_RXD0__GPIO6_IO24                     0x0168 0x046c 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_RXD0__DIG_ENCODER1_DATA_EN           0x0168 0x046c 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_RXD0__XBAR1_XBAR_INOUT45             0x0168 0x046c 0x08ec 0x07 0x01</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH3_RXD1__NETC_PINMUX_ETH3_RXD1          0x016c 0x0470 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_RXD1__XSPI_SLV_DATA1                 0x016c 0x0470 0x090c 0x02 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_RXD1__SAI2_RX_BCLK                   0x016c 0x0470 0x07ec 0x03 0x01</div><div class='add'>+#define IMX94_PAD_ETH3_RXD1__LPUART3_RTS_B                  0x016c 0x0470 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_RXD1__GPIO6_IO25                     0x016c 0x0470 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_RXD1__DIG_ENCODER1_DATA_CLK          0x016c 0x0470 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_RXD1__XBAR1_XBAR_INOUT46             0x016c 0x0470 0x08f0 0x07 0x01</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH3_RXD2__NETC_PINMUX_ETH3_RXD2          0x0170 0x0474 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_RXD2__MQS2_RIGHT                     0x0170 0x0474 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_RXD2__XSPI_SLV_DATA0                 0x0170 0x0474 0x0908 0x02 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_RXD2__SAI2_RX_DATA0                  0x0170 0x0474 0x07f0 0x03 0x01</div><div class='add'>+#define IMX94_PAD_ETH3_RXD2__GPIO6_IO26                     0x0170 0x0474 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_RXD2__DIG_ENCODER1_DATA_OUT          0x0170 0x0474 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_RXD2__XBAR1_XBAR_INOUT47             0x0170 0x0474 0x08f4 0x07 0x01</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH3_RXD3__NETC_PINMUX_ETH3_RXD3          0x0174 0x0478 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_RXD3__MQS2_LEFT                      0x0174 0x0478 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_RXD3__SAI2_MCLK                      0x0174 0x0478 0x07e8 0x03 0x01</div><div class='add'>+#define IMX94_PAD_ETH3_RXD3__GPIO6_IO27                     0x0174 0x0478 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_RXD3__DIG_ENCODER1_DATA_IN           0x0174 0x0478 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_ETH3_RXD3__XBAR1_XBAR_INOUT48             0x0174 0x0478 0x08f8 0x07 0x01</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH4_MDC_GPIO1__NETC_EMDC                 0x0178 0x047c 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_MDC_GPIO1__ECAT_MDC                  0x0178 0x047c 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_MDC_GPIO1__ECAT_CLK25                0x0178 0x047c 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_MDC_GPIO1__NETC_ETH4_SLV_MDC         0x0178 0x047c 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_MDC_GPIO1__FLEXIO1_3_2_FLEXIO12      0x0178 0x047c 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_MDC_GPIO1__GPIO6_IO28                0x0178 0x047c 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_MDC_GPIO1__FLEXPWM4_PWMX0            0x0178 0x047c 0x06f4 0x06 0x02</div><div class='add'>+#define IMX94_PAD_ETH4_MDC_GPIO1__SINC4_MOD_CLK2            0x0178 0x047c 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH4_MDIO_GPIO2__NETC_EMDIO               0x017c 0x0480 0x0678 0x00 0x02</div><div class='add'>+#define IMX94_PAD_ETH4_MDIO_GPIO2__ECAT_MDIO                0x017c 0x0480 0x0628 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_MDIO_GPIO2__ENET_REF_CLK_ROOT        0x017c 0x0480 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_MDIO_GPIO2__NETC_ETH4_SLV_MDIO       0x017c 0x0480 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_MDIO_GPIO2__FLEXIO1_3_2_FLEXIO13     0x017c 0x0480 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_MDIO_GPIO2__GPIO6_IO29               0x017c 0x0480 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_MDIO_GPIO2__FLEXPWM4_PWMX1           0x017c 0x0480 0x06f8 0x06 0x02</div><div class='add'>+#define IMX94_PAD_ETH4_MDIO_GPIO2__SINC_FILTER_GLUE4_BREAK  0x017c 0x0480 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH4_TX_CLK__NETC_PINMUX_ETH4_TX_CLK      0x0180 0x0484 0x0648 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_TX_CLK__USDHC3_CLK                   0x0180 0x0484 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_TX_CLK__XSPI2_A_SCLK                 0x0180 0x0484 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_TX_CLK__ECAT_LED_ERR                 0x0180 0x0484 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_TX_CLK__FLEXIO1_3_2_FLEXIO0          0x0180 0x0484 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_TX_CLK__GPIO6_IO30                   0x0180 0x0484 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_TX_CLK__FLEXPWM4_PWMA0               0x0180 0x0484 0x06d4 0x06 0x01</div><div class='add'>+#define IMX94_PAD_ETH4_TX_CLK__XBAR1_XBAR_INOUT30           0x0180 0x0484 0x08b0 0x07 0x02</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH4_TX_CTL__NETC_PINMUX_ETH4_TX_CTL      0x0184 0x0488 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_TX_CTL__USDHC3_CMD                   0x0184 0x0488 0x0858 0x01 0x01</div><div class='add'>+#define IMX94_PAD_ETH4_TX_CTL__XSPI2_A_SS0_B                0x0184 0x0488 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_TX_CTL__ECAT_RESET_OUT               0x0184 0x0488 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_TX_CTL__FLEXIO1_3_2_FLEXIO1          0x0184 0x0488 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_TX_CTL__GPIO6_IO31                   0x0184 0x0488 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_TX_CTL__FLEXPWM4_PWMB0               0x0184 0x0488 0x06e4 0x06 0x01</div><div class='add'>+#define IMX94_PAD_ETH4_TX_CTL__XBAR1_XBAR_INOUT31           0x0184 0x0488 0x08b4 0x07 0x02</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH4_TXD0__NETC_PINMUX_ETH4_TXD0          0x0188 0x048c 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_TXD0__USDHC3_DATA0                   0x0188 0x048c 0x085c 0x01 0x01</div><div class='add'>+#define IMX94_PAD_ETH4_TXD0__XSPI2_A_DATA0                  0x0188 0x048c 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_TXD0__ECAT_LED_RUN                   0x0188 0x048c 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_TXD0__FLEXIO1_3_2_FLEXIO2            0x0188 0x048c 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_TXD0__GPIO7_IO0                      0x0188 0x048c 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_TXD0__FLEXPWM4_PWMA1                 0x0188 0x048c 0x06d8 0x06 0x01</div><div class='add'>+#define IMX94_PAD_ETH4_TXD0__XBAR1_XBAR_INOUT32             0x0188 0x048c 0x08b8 0x07 0x02</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH4_TXD1__NETC_PINMUX_ETH4_TXD1          0x018c 0x0490 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_TXD1__USDHC3_DATA1                   0x018c 0x0490 0x0860 0x01 0x01</div><div class='add'>+#define IMX94_PAD_ETH4_TXD1__XSPI2_A_DATA1                  0x018c 0x0490 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_TXD1__ECAT_LED_STATE_RUN             0x018c 0x0490 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_TXD1__FLEXIO1_3_2_FLEXIO3            0x018c 0x0490 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_TXD1__GPIO7_IO1                      0x018c 0x0490 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_TXD1__FLEXPWM4_PWMB1                 0x018c 0x0490 0x06e8 0x06 0x01</div><div class='add'>+#define IMX94_PAD_ETH4_TXD1__XBAR1_XBAR_INOUT33             0x018c 0x0490 0x08bc 0x07 0x02</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH4_TXD2__NETC_PINMUX_ETH4_TXD2          0x0190 0x0494 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_TXD2__USDHC3_DATA2                   0x0190 0x0494 0x0864 0x01 0x01</div><div class='add'>+#define IMX94_PAD_ETH4_TXD2__XSPI2_A_DATA2                  0x0190 0x0494 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_TXD2__ECAT_CLK25                     0x0190 0x0494 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_TXD2__FLEXIO1_3_2_FLEXIO4            0x0190 0x0494 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_TXD2__GPIO7_IO2                      0x0190 0x0494 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_TXD2__FLEXPWM4_PWMA2                 0x0190 0x0494 0x06dc 0x06 0x01</div><div class='add'>+#define IMX94_PAD_ETH4_TXD2__ETH4_RMII_REF50_CLK            0x0190 0x0494 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH4_TXD3__NETC_PINMUX_ETH4_TXD3          0x0194 0x0498 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_TXD3__USDHC3_DATA3                   0x0194 0x0498 0x0868 0x01 0x01</div><div class='add'>+#define IMX94_PAD_ETH4_TXD3__XSPI2_A_DATA3                  0x0194 0x0498 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_TXD3__FLEXIO1_3_2_FLEXIO5            0x0194 0x0498 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_TXD3__GPIO7_IO3                      0x0194 0x0498 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_TXD3__FLEXPWM4_PWMB2                 0x0194 0x0498 0x06ec 0x06 0x01</div><div class='add'>+#define IMX94_PAD_ETH4_TXD3__XBAR1_XBAR_INOUT35             0x0194 0x0498 0x08c4 0x07 0x02</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH4_RXD0__NETC_PINMUX_ETH4_RXD0          0x0198 0x049c 0x0638 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_RXD0__XSPI2_A_DATA4                  0x0198 0x049c 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_RXD0__FLEXIO1_3_2_FLEXIO6            0x0198 0x049c 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_RXD0__GPIO7_IO4                      0x0198 0x049c 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_RXD0__FLEXPWM4_PWMA3                 0x0198 0x049c 0x06e0 0x06 0x01</div><div class='add'>+#define IMX94_PAD_ETH4_RXD0__SINC4_EMCLK2                   0x0198 0x049c 0x0834 0x07 0x01</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH4_RXD1__NETC_PINMUX_ETH4_RXD1          0x019c 0x04a0 0x063c 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_RXD1__XSPI2_A_DATA5                  0x019c 0x04a0 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_RXD1__FLEXIO2_4_1_FLEXIO11           0x019c 0x04a0 0x0694 0x03 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_RXD1__FLEXIO1_3_2_FLEXIO7            0x019c 0x04a0 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_RXD1__GPIO7_IO5                      0x019c 0x04a0 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_RXD1__FLEXPWM4_PWMB3                 0x019c 0x04a0 0x06f0 0x06 0x01</div><div class='add'>+#define IMX94_PAD_ETH4_RXD1__SINC4_EMBIT2                   0x019c 0x04a0 0x0828 0x07 0x01</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH4_RXD2__NETC_PINMUX_ETH4_RXD2          0x01a0 0x04a4 0x0640 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_RXD2__XSPI2_A_DATA6                  0x01a0 0x04a4 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_RXD2__FLEXIO2_4_1_FLEXIO12           0x01a0 0x04a4 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_RXD2__FLEXIO1_3_2_FLEXIO8            0x01a0 0x04a4 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_RXD2__GPIO7_IO6                      0x01a0 0x04a4 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_RXD2__DIG_ENCODER2_DATA_EN           0x01a0 0x04a4 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_RXD2__XBAR1_XBAR_INOUT4              0x01a0 0x04a4 0x086c 0x07 0x01</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH4_RXD3__NETC_PINMUX_ETH4_RXD3          0x01a4 0x04a8 0x0644 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_RXD3__ENET_REF_CLK_ROOT              0x01a4 0x04a8 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_RXD3__XSPI2_A_DATA7                  0x01a4 0x04a8 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_RXD3__FLEXIO2_4_1_FLEXIO13           0x01a4 0x04a8 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_RXD3__FLEXIO1_3_2_FLEXIO9            0x01a4 0x04a8 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_RXD3__GPIO7_IO7                      0x01a4 0x04a8 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_RXD3__DIG_ENCODER2_DATA_CLK          0x01a4 0x04a8 0x068c 0x06 0x01</div><div class='add'>+#define IMX94_PAD_ETH4_RXD3__XBAR1_XBAR_INOUT5              0x01a4 0x04a8 0x0870 0x07 0x01</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH4_RX_CTL__NETC_PINMUX_ETH4_RX_CTL      0x01a8 0x04ac 0x0634 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_RX_CTL__XSPI2_A_SS1_B                0x01a8 0x04ac 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_RX_CTL__FLEXIO2_4_1_FLEXIO14         0x01a8 0x04ac 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_RX_CTL__FLEXIO1_3_2_FLEXIO10         0x01a8 0x04ac 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_RX_CTL__GPIO7_IO8                    0x01a8 0x04ac 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_RX_CTL__DIG_ENCODER2_DATA_OUT        0x01a8 0x04ac 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_RX_CTL__XBAR1_XBAR_INOUT6            0x01a8 0x04ac 0x0874 0x07 0x01</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH4_RX_CLK__NETC_PINMUX_ETH4_RX_CLK      0x01ac 0x04b0 0x0630 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_RX_CLK__XSPI2_A_DQS                  0x01ac 0x04b0 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_RX_CLK__FLEXIO2_4_1_FLEXIO15         0x01ac 0x04b0 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_RX_CLK__FLEXIO1_3_2_FLEXIO11         0x01ac 0x04b0 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_RX_CLK__GPIO7_IO9                    0x01ac 0x04b0 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_ETH4_RX_CLK__DIG_ENCODER2_DATA_IN         0x01ac 0x04b0 0x0690 0x06 0x01</div><div class='add'>+#define IMX94_PAD_ETH4_RX_CLK__XBAR1_XBAR_INOUT7            0x01ac 0x04b0 0x0878 0x07 0x01</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH0_TXD0__NETC_PINMUX_ETH0_TXD0          0x01b0 0x04b4 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_TXD0__ECAT_PT0_TXD0                  0x01b0 0x04b4 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_TXD0__FLEXIO4_FLEXIO0                0x01b0 0x04b4 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_TXD0__GPIO5_IO0                      0x01b0 0x04b4 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH0_TXD1__NETC_PINMUX_ETH0_TXD1          0x01b4 0x04b8 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_TXD1__ECAT_PT0_TXD1                  0x01b4 0x04b8 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_TXD1__FLEXIO4_FLEXIO1                0x01b4 0x04b8 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_TXD1__GPIO5_IO1                      0x01b4 0x04b8 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH0_TX_EN__NETC_PINMUX_ETH0_TX_EN        0x01b8 0x04bc 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_TX_EN__ECAT_PT0_TX_EN                0x01b8 0x04bc 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_TX_EN__FLEXIO4_FLEXIO2               0x01b8 0x04bc 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_TX_EN__GPIO5_IO2                     0x01b8 0x04bc 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH0_TX_CLK__NETC_PINMUX_ETH0_TX_CLK      0x01bc 0x04c0 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_TX_CLK__ECAT_PT0_TX_CLK              0x01bc 0x04c0 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_TX_CLK__FLEXIO4_FLEXIO3              0x01bc 0x04c0 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_TX_CLK__GPIO5_IO3                    0x01bc 0x04c0 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH0_RXD0__NETC_PINMUX_ETH0_RXD0          0x01c0 0x04c4 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_RXD0__ECAT_PT0_RXD0                  0x01c0 0x04c4 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_RXD0__FLEXIO4_FLEXIO4                0x01c0 0x04c4 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_RXD0__GPIO5_IO4                      0x01c0 0x04c4 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH0_RXD1__NETC_PINMUX_ETH0_RXD1          0x01c4 0x04c8 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_RXD1__ECAT_PT0_RXD1                  0x01c4 0x04c8 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_RXD1__FLEXIO4_FLEXIO5                0x01c4 0x04c8 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_RXD1__GPIO5_IO5                      0x01c4 0x04c8 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH0_RX_DV__NETC_PINMUX_ETH0_RX_DV        0x01c8 0x04cc 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_RX_DV__ECAT_PT0_RX_DV                0x01c8 0x04cc 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_RX_DV__FLEXIO4_FLEXIO6               0x01c8 0x04cc 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_RX_DV__GPIO5_IO6                     0x01c8 0x04cc 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH0_TXD2__NETC_PINMUX_ETH0_TXD2          0x01cc 0x04d0 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_TXD2__ECAT_PT0_TXD2                  0x01cc 0x04d0 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_TXD2__ETH0_RMII_REF50_CLK            0x01cc 0x04d0 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_TXD2__FLEXIO4_FLEXIO7                0x01cc 0x04d0 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_TXD2__GPIO5_IO7                      0x01cc 0x04d0 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH0_TXD3__NETC_PINMUX_ETH0_TXD3          0x01d0 0x04d4 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_TXD3__ECAT_PT0_TXD3                  0x01d0 0x04d4 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_TXD3__FLEXIO4_FLEXIO8                0x01d0 0x04d4 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_TXD3__GPIO5_IO8                      0x01d0 0x04d4 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH0_RXD2__NETC_PINMUX_ETH0_RXD2          0x01d4 0x04d8 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_RXD2__ECAT_PT0_RXD2                  0x01d4 0x04d8 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_RXD2__FLEXIO4_FLEXIO9                0x01d4 0x04d8 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_RXD2__GPIO5_IO9                      0x01d4 0x04d8 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH0_RXD3__NETC_PINMUX_ETH0_RXD3          0x01d8 0x04dc 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_RXD3__ECAT_PT0_RXD3                  0x01d8 0x04dc 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_RXD3__FLEXIO4_FLEXIO10               0x01d8 0x04dc 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_RXD3__GPIO5_IO10                     0x01d8 0x04dc 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH0_RX_CLK__NETC_PINMUX_ETH0_RX_CLK      0x01dc 0x04e0 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_RX_CLK__ECAT_PT0_RX_CLK              0x01dc 0x04e0 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_RX_CLK__FLEXIO4_FLEXIO11             0x01dc 0x04e0 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_RX_CLK__GPIO5_IO11                   0x01dc 0x04e0 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH0_RX_ER__NETC_PINMUX_ETH0_RX_ER        0x01e0 0x04e4 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_RX_ER__ECAT_PT0_RX_ER                0x01e0 0x04e4 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_RX_ER__FLEXIO4_FLEXIO12              0x01e0 0x04e4 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_RX_ER__GPIO5_IO12                    0x01e0 0x04e4 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH0_TX_ER__NETC_PINMUX_ETH0_TX_ER        0x01e4 0x04e8 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_TX_ER__ECAT_LINK_ACT0                0x01e4 0x04e8 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_TX_ER__FLEXIO4_FLEXIO13              0x01e4 0x04e8 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_TX_ER__GPIO5_IO13                    0x01e4 0x04e8 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH0_CRS__NETC_PINMUX_ETH0_CRS            0x01e8 0x04ec 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_CRS__ECAT_LINK0                      0x01e8 0x04ec 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_CRS__NETC_EMDC                       0x01e8 0x04ec 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_CRS__FLEXIO4_FLEXIO14                0x01e8 0x04ec 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_CRS__GPIO5_IO14                      0x01e8 0x04ec 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_CRS__XBAR1_XBAR_INOUT8               0x01e8 0x04ec 0x087c 0x06 0x02</div><div class='add'>+#define IMX94_PAD_ETH0_CRS__SINC_FILTER_GLUE2_BREAK         0x01e8 0x04ec 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH0_COL__NETC_PINMUX_ETH0_COL            0x01ec 0x04f0 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_COL__ECAT_LINK1                      0x01ec 0x04f0 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_COL__NETC_EMDIO                      0x01ec 0x04f0 0x0678 0x02 0x03</div><div class='add'>+#define IMX94_PAD_ETH0_COL__FLEXIO4_FLEXIO15                0x01ec 0x04f0 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_COL__GPIO5_IO15                      0x01ec 0x04f0 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_ETH0_COL__XBAR1_XBAR_INOUT9               0x01ec 0x04f0 0x0880 0x06 0x02</div><div class='add'>+#define IMX94_PAD_ETH0_COL__SINC_FILTER_GLUE1_BREAK         0x01ec 0x04f0 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH1_TXD0__NETC_PINMUX_ETH1_TXD0          0x01f0 0x04f4 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_TXD0__ECAT_PT1_TXD0                  0x01f0 0x04f4 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_TXD0__ENCODER_DIAG0                  0x01f0 0x04f4 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_TXD0__FLEXIO3_FLEXIO0                0x01f0 0x04f4 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_TXD0__GPIO5_IO16                     0x01f0 0x04f4 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH1_TXD1__NETC_PINMUX_ETH1_TXD1          0x01f4 0x04f8 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_TXD1__ECAT_PT1_TXD1                  0x01f4 0x04f8 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_TXD1__ENCODER_DIAG1                  0x01f4 0x04f8 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_TXD1__FLEXIO3_FLEXIO1                0x01f4 0x04f8 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_TXD1__GPIO5_IO17                     0x01f4 0x04f8 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH1_TX_EN__NETC_PINMUX_ETH1_TX_EN        0x01f8 0x04fc 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_TX_EN__ECAT_PT1_TX_EN                0x01f8 0x04fc 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_TX_EN__ENCODER_DIAG2                 0x01f8 0x04fc 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_TX_EN__FLEXIO3_FLEXIO2               0x01f8 0x04fc 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_TX_EN__GPIO5_IO18                    0x01f8 0x04fc 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH1_TX_CLK__NETC_PINMUX_ETH1_TX_CLK      0x01fc 0x0500 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_TX_CLK__ECAT_PT1_TX_CLK              0x01fc 0x0500 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_TX_CLK__ENCODER_DIAG3                0x01fc 0x0500 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_TX_CLK__FLEXIO3_FLEXIO3              0x01fc 0x0500 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_TX_CLK__GPIO5_IO19                   0x01fc 0x0500 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH1_RXD0__NETC_PINMUX_ETH1_RXD0          0x0200 0x0504 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_RXD0__ECAT_PT1_RXD0                  0x0200 0x0504 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_RXD0__ENCODER_DIAG4                  0x0200 0x0504 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_RXD0__FLEXIO3_FLEXIO4                0x0200 0x0504 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_RXD0__GPIO5_IO20                     0x0200 0x0504 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH1_RXD1__NETC_PINMUX_ETH1_RXD1          0x0204 0x0508 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_RXD1__ECAT_PT1_RXD1                  0x0204 0x0508 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_RXD1__ENCODER_DIAG5                  0x0204 0x0508 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_RXD1__FLEXIO3_FLEXIO5                0x0204 0x0508 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_RXD1__GPIO5_IO21                     0x0204 0x0508 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH1_RX_DV__NETC_PINMUX_ETH1_RX_DV        0x0208 0x050c 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_RX_DV__ECAT_PT1_RX_DV                0x0208 0x050c 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_RX_DV__ENCODER_DIAG6                 0x0208 0x050c 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_RX_DV__FLEXIO3_FLEXIO6               0x0208 0x050c 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_RX_DV__GPIO5_IO22                    0x0208 0x050c 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH1_TXD2__NETC_PINMUX_ETH1_TXD2          0x020c 0x0510 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_TXD2__ECAT_PT1_TXD2                  0x020c 0x0510 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_TXD2__ETH1_RMII_REF50_CLK            0x020c 0x0510 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_TXD2__ENCODER_DIAG7                  0x020c 0x0510 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_TXD2__FLEXIO3_FLEXIO7                0x020c 0x0510 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_TXD2__GPIO5_IO23                     0x020c 0x0510 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH1_TXD3__NETC_PINMUX_ETH1_TXD3          0x0210 0x0514 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_TXD3__ECAT_PT1_TXD3                  0x0210 0x0514 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_TXD3__ENCODER_DIAG8                  0x0210 0x0514 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_TXD3__FLEXIO3_FLEXIO8                0x0210 0x0514 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_TXD3__GPIO5_IO24                     0x0210 0x0514 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH1_RXD2__NETC_PINMUX_ETH1_RXD2          0x0214 0x0518 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_RXD2__ECAT_PT1_RXD2                  0x0214 0x0518 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_RXD2__ENCODER_DIAG9                  0x0214 0x0518 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_RXD2__FLEXIO3_FLEXIO9                0x0214 0x0518 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_RXD2__GPIO5_IO25                     0x0214 0x0518 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH1_RXD3__NETC_PINMUX_ETH1_RXD3          0x0218 0x051c 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_RXD3__ECAT_PT1_RXD3                  0x0218 0x051c 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_RXD3__ENCODER_DIAG10                 0x0218 0x051c 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_RXD3__FLEXIO3_FLEXIO10               0x0218 0x051c 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_RXD3__GPIO5_IO26                     0x0218 0x051c 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH1_RX_CLK__NETC_PINMUX_ETH1_RX_CLK      0x021c 0x0520 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_RX_CLK__ECAT_PT1_RX_CLK              0x021c 0x0520 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_RX_CLK__ENCODER_DIAG11               0x021c 0x0520 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_RX_CLK__FLEXIO3_FLEXIO11             0x021c 0x0520 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_RX_CLK__GPIO5_IO27                   0x021c 0x0520 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH1_RX_ER__NETC_PINMUX_ETH1_RX_ER        0x0220 0x0524 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_RX_ER__ECAT_PT1_RX_ER                0x0220 0x0524 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_RX_ER__ENCODER_DIAG12                0x0220 0x0524 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_RX_ER__FLEXIO3_FLEXIO12              0x0220 0x0524 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_RX_ER__GPIO5_IO28                    0x0220 0x0524 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH1_TX_ER__NETC_PINMUX_ETH1_TX_ER        0x0224 0x0528 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_TX_ER__ECAT_LINK_ACT1                0x0224 0x0528 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_TX_ER__ENCODER_DIAG13                0x0224 0x0528 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_TX_ER__FLEXIO3_FLEXIO13              0x0224 0x0528 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_TX_ER__GPIO5_IO29                    0x0224 0x0528 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH1_CRS__NETC_PINMUX_ETH1_CRS            0x0228 0x052c 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_CRS__ECAT_MDC                        0x0228 0x052c 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_CRS__NETC_EMDC                       0x0228 0x052c 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_CRS__ENCODER_DIAG14                  0x0228 0x052c 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_CRS__FLEXIO3_FLEXIO14                0x0228 0x052c 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_CRS__GPIO5_IO30                      0x0228 0x052c 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_CRS__XBAR1_XBAR_INOUT10              0x0228 0x052c 0x0884 0x06 0x02</div><div class='add'>+#define IMX94_PAD_ETH1_CRS__SINC_FILTER_GLUE1_BREAK         0x0228 0x052c 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_ETH1_COL__NETC_PINMUX_ETH1_COL            0x022c 0x0530 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_COL__ECAT_MDIO                       0x022c 0x0530 0x0628 0x01 0x01</div><div class='add'>+#define IMX94_PAD_ETH1_COL__NETC_EMDIO                      0x022c 0x0530 0x0678 0x02 0x04</div><div class='add'>+#define IMX94_PAD_ETH1_COL__ENCODER_DIAG15                  0x022c 0x0530 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_COL__FLEXIO3_FLEXIO15                0x022c 0x0530 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_COL__GPIO5_IO31                      0x022c 0x0530 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_ETH1_COL__XBAR1_XBAR_INOUT11              0x022c 0x0530 0x0888 0x06 0x02</div><div class='add'>+#define IMX94_PAD_ETH1_COL__SINC_FILTER_GLUE2_BREAK         0x022c 0x0530 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_SD1_CLK__USDHC1_CLK                       0x0230 0x0534 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_SD1_CLK__SAI4_TX_BCLK                     0x0230 0x0534 0x0818 0x01 0x01</div><div class='add'>+#define IMX94_PAD_SD1_CLK__CAN4_TX                          0x0230 0x0534 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_SD1_CLK__NETC_1588MUX_INOUT0              0x0230 0x0534 0x064c 0x03 0x01</div><div class='add'>+#define IMX94_PAD_SD1_CLK__FLEXIO2_4_1_FLEXIO0              0x0230 0x0534 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_SD1_CLK__GPIO4_IO8                        0x0230 0x0534 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_SD1_CLK__FLEXPWM3_PWMX0                   0x0230 0x0534 0x06c8 0x06 0x02</div><div class='add'>+#define IMX94_PAD_SD1_CLK__SINC1_EMCLK0                     0x0230 0x0534 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_SD1_CMD__USDHC1_CMD                       0x0234 0x0538 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_SD1_CMD__SAI4_RX_BCLK                     0x0234 0x0538 0x080c 0x01 0x01</div><div class='add'>+#define IMX94_PAD_SD1_CMD__CAN4_RX                          0x0234 0x0538 0x0684 0x02 0x02</div><div class='add'>+#define IMX94_PAD_SD1_CMD__NETC_1588MUX_INOUT1              0x0234 0x0538 0x0650 0x03 0x01</div><div class='add'>+#define IMX94_PAD_SD1_CMD__FLEXIO2_4_1_FLEXIO1              0x0234 0x0538 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_SD1_CMD__GPIO4_IO9                        0x0234 0x0538 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_SD1_CMD__FLEXPWM3_PWMX1                   0x0234 0x0538 0x06cc 0x06 0x02</div><div class='add'>+#define IMX94_PAD_SD1_CMD__SINC1_EMBIT0                     0x0234 0x0538 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_SD1_DATA0__USDHC1_DATA0                   0x0238 0x053c 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_SD1_DATA0__SAI4_RX_SYNC                   0x0238 0x053c 0x0814 0x01 0x01</div><div class='add'>+#define IMX94_PAD_SD1_DATA0__CAN5_TX                        0x0238 0x053c 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_SD1_DATA0__NETC_1588MUX_INOUT2            0x0238 0x053c 0x0654 0x03 0x01</div><div class='add'>+#define IMX94_PAD_SD1_DATA0__FLEXIO2_4_1_FLEXIO2            0x0238 0x053c 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_SD1_DATA0__GPIO4_IO10                     0x0238 0x053c 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_SD1_DATA0__FLEXPWM3_PWMX2                 0x0238 0x053c 0x06d0 0x06 0x01</div><div class='add'>+#define IMX94_PAD_SD1_DATA0__SINC1_EMCLK1                   0x0238 0x053c 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_SD1_DATA1__USDHC1_DATA1                   0x023c 0x0540 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_SD1_DATA1__SAI4_TX_SYNC                   0x023c 0x0540 0x081c 0x01 0x01</div><div class='add'>+#define IMX94_PAD_SD1_DATA1__CAN5_RX                        0x023c 0x0540 0x0688 0x02 0x03</div><div class='add'>+#define IMX94_PAD_SD1_DATA1__NETC_1588MUX_INOUT3            0x023c 0x0540 0x0658 0x03 0x01</div><div class='add'>+#define IMX94_PAD_SD1_DATA1__FLEXIO2_4_1_FLEXIO3            0x023c 0x0540 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_SD1_DATA1__GPIO4_IO11                     0x023c 0x0540 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_SD1_DATA1__FLEXPWM3_PWMA3                 0x023c 0x0540 0x06b4 0x06 0x01</div><div class='add'>+#define IMX94_PAD_SD1_DATA1__SINC1_EMBIT1                   0x023c 0x0540 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_SD1_DATA2__USDHC1_DATA2                   0x0240 0x0544 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_SD1_DATA2__SAI4_TX_DATA0                  0x0240 0x0544 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_SD1_DATA2__PMIC_READY                     0x0240 0x0544 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_SD1_DATA2__NETC_1588MUX_INOUT4            0x0240 0x0544 0x065c 0x03 0x01</div><div class='add'>+#define IMX94_PAD_SD1_DATA2__FLEXIO2_4_1_FLEXIO4            0x0240 0x0544 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_SD1_DATA2__GPIO4_IO12                     0x0240 0x0544 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_SD1_DATA2__FLEXPWM3_PWMB3                 0x0240 0x0544 0x06c4 0x06 0x01</div><div class='add'>+#define IMX94_PAD_SD1_DATA2__SINC1_EMCLK2                   0x0240 0x0544 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_SD1_DATA3__USDHC1_DATA3                   0x0244 0x0548 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_SD1_DATA3__SAI4_RX_DATA0                  0x0244 0x0548 0x0810 0x01 0x01</div><div class='add'>+#define IMX94_PAD_SD1_DATA3__NETC_1588MUX_INOUT5            0x0244 0x0548 0x0660 0x03 0x01</div><div class='add'>+#define IMX94_PAD_SD1_DATA3__FLEXIO2_4_1_FLEXIO5            0x0244 0x0548 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_SD1_DATA3__GPIO4_IO13                     0x0244 0x0548 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_SD1_DATA3__FLEXPWM3_PWMA2                 0x0244 0x0548 0x06b0 0x06 0x01</div><div class='add'>+#define IMX94_PAD_SD1_DATA3__SINC1_EMBIT2                   0x0244 0x0548 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_SD1_DATA4__USDHC1_DATA4                   0x0248 0x054c 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_SD1_DATA4__SAI2_RX_DATA0                  0x0248 0x054c 0x07f0 0x01 0x02</div><div class='add'>+#define IMX94_PAD_SD1_DATA4__NETC_1588MUX_INOUT6            0x0248 0x054c 0x0664 0x03 0x01</div><div class='add'>+#define IMX94_PAD_SD1_DATA4__FLEXIO2_4_1_FLEXIO6            0x0248 0x054c 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_SD1_DATA4__GPIO4_IO14                     0x0248 0x054c 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_SD1_DATA4__FLEXPWM3_PWMB2                 0x0248 0x054c 0x06c0 0x06 0x01</div><div class='add'>+#define IMX94_PAD_SD1_DATA4__SINC1_EMCLK3                   0x0248 0x054c 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_SD1_DATA5__USDHC1_DATA5                   0x024c 0x0550 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_SD1_DATA5__SAI2_TX_DATA0                  0x024c 0x0550 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_SD1_DATA5__USDHC1_RESET_B                 0x024c 0x0550 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_SD1_DATA5__NETC_1588MUX_INOUT7            0x024c 0x0550 0x0668 0x03 0x01</div><div class='add'>+#define IMX94_PAD_SD1_DATA5__FLEXIO2_4_1_FLEXIO7            0x024c 0x0550 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_SD1_DATA5__GPIO4_IO15                     0x024c 0x0550 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_SD1_DATA5__FLEXPWM3_PWMA1                 0x024c 0x0550 0x06ac 0x06 0x01</div><div class='add'>+#define IMX94_PAD_SD1_DATA5__SINC1_EMBIT3                   0x024c 0x0550 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_SD1_DATA6__USDHC1_DATA6                   0x0250 0x0554 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_SD1_DATA6__SAI2_TX_BCLK                   0x0250 0x0554 0x07f8 0x01 0x02</div><div class='add'>+#define IMX94_PAD_SD1_DATA6__USDHC1_CD_B                    0x0250 0x0554 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_SD1_DATA6__NETC_1588MUX_INOUT8            0x0250 0x0554 0x066c 0x03 0x01</div><div class='add'>+#define IMX94_PAD_SD1_DATA6__FLEXIO2_4_1_FLEXIO8            0x0250 0x0554 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_SD1_DATA6__GPIO4_IO16                     0x0250 0x0554 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_SD1_DATA6__FLEXPWM3_PWMB1                 0x0250 0x0554 0x06bc 0x06 0x01</div><div class='add'>+#define IMX94_PAD_SD1_DATA6__SINC1_MOD_CLK0                 0x0250 0x0554 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_SD1_DATA7__USDHC1_DATA7                   0x0254 0x0558 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_SD1_DATA7__SAI2_RX_SYNC                   0x0254 0x0558 0x07f4 0x01 0x02</div><div class='add'>+#define IMX94_PAD_SD1_DATA7__USDHC1_WP                      0x0254 0x0558 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_SD1_DATA7__NETC_1588MUX_INOUT9            0x0254 0x0558 0x0670 0x03 0x01</div><div class='add'>+#define IMX94_PAD_SD1_DATA7__FLEXIO2_4_1_FLEXIO9            0x0254 0x0558 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_SD1_DATA7__GPIO4_IO17                     0x0254 0x0558 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_SD1_DATA7__FLEXPWM3_PWMA0                 0x0254 0x0558 0x06a8 0x06 0x01</div><div class='add'>+#define IMX94_PAD_SD1_DATA7__SINC1_MOD_CLK1                 0x0254 0x0558 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_SD1_STROBE__USDHC1_STROBE                 0x0258 0x055c 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_SD1_STROBE__SAI2_TX_SYNC                  0x0258 0x055c 0x07fc 0x01 0x02</div><div class='add'>+#define IMX94_PAD_SD1_STROBE__NETC_1588MUX_INOUT10          0x0258 0x055c 0x0674 0x03 0x01</div><div class='add'>+#define IMX94_PAD_SD1_STROBE__FLEXIO2_4_1_FLEXIO10          0x0258 0x055c 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_SD1_STROBE__GPIO4_IO18                    0x0258 0x055c 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_SD1_STROBE__FLEXPWM3_PWMB0                0x0258 0x055c 0x06b8 0x06 0x01</div><div class='add'>+#define IMX94_PAD_SD1_STROBE__SINC1_MOD_CLK2                0x0258 0x055c 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_SD2_VSELECT__USDHC2_VSELECT               0x025c 0x0560 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_SD2_VSELECT__SAI4_MCLK                    0x025c 0x0560 0x0808 0x01 0x01</div><div class='add'>+#define IMX94_PAD_SD2_VSELECT__USDHC2_WP                    0x025c 0x0560 0x0854 0x02 0x02</div><div class='add'>+#define IMX94_PAD_SD2_VSELECT__NETC_1588MUX_INOUT10         0x025c 0x0560 0x0674 0x03 0x02</div><div class='add'>+#define IMX94_PAD_SD2_VSELECT__FLEXIO2_4_1_FLEXIO11         0x025c 0x0560 0x0694 0x04 0x01</div><div class='add'>+#define IMX94_PAD_SD2_VSELECT__GPIO4_IO19                   0x025c 0x0560 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_SD2_VSELECT__EXT_CLK1                     0x025c 0x0560 0x0624 0x06 0x01</div><div class='add'>+#define IMX94_PAD_SD2_VSELECT__XBAR1_XBAR_INOUT12           0x025c 0x0560 0x088c 0x07 0x02</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_XSPI1_DATA0__XSPI1_A_DATA0                0x0260 0x0564 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_XSPI1_DATA0__SAI2_RX_SYNC                 0x0260 0x0564 0x07f4 0x01 0x03</div><div class='add'>+#define IMX94_PAD_XSPI1_DATA0__XSPI_SLV_DATA0               0x0260 0x0564 0x0908 0x03 0x01</div><div class='add'>+#define IMX94_PAD_XSPI1_DATA0__FLEXIO1_3_3_FLEXIO0          0x0260 0x0564 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_XSPI1_DATA0__GPIO7_IO16                   0x0260 0x0564 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_XSPI1_DATA1__XSPI1_A_DATA1                0x0264 0x0568 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_XSPI1_DATA1__SAI2_TX_SYNC                 0x0264 0x0568 0x07fc 0x01 0x03</div><div class='add'>+#define IMX94_PAD_XSPI1_DATA1__XSPI_SLV_DATA1               0x0264 0x0568 0x090c 0x03 0x01</div><div class='add'>+#define IMX94_PAD_XSPI1_DATA1__FLEXIO1_3_3_FLEXIO1          0x0264 0x0568 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_XSPI1_DATA1__GPIO7_IO17                   0x0264 0x0568 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_XSPI1_DATA2__XSPI1_A_DATA2                0x0268 0x056c 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_XSPI1_DATA2__SAI2_TX_DATA0                0x0268 0x056c 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_XSPI1_DATA2__XSPI_SLV_DATA2               0x0268 0x056c 0x0910 0x03 0x01</div><div class='add'>+#define IMX94_PAD_XSPI1_DATA2__FLEXIO1_3_3_FLEXIO2          0x0268 0x056c 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_XSPI1_DATA2__GPIO7_IO18                   0x0268 0x056c 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_XSPI1_DATA3__XSPI1_A_DATA3                0x026c 0x0570 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_XSPI1_DATA3__SAI2_RX_DATA0                0x026c 0x0570 0x07f0 0x01 0x03</div><div class='add'>+#define IMX94_PAD_XSPI1_DATA3__SAI2_MCLK                    0x026c 0x0570 0x07e8 0x02 0x02</div><div class='add'>+#define IMX94_PAD_XSPI1_DATA3__XSPI_SLV_DATA3               0x026c 0x0570 0x0914 0x03 0x01</div><div class='add'>+#define IMX94_PAD_XSPI1_DATA3__FLEXIO1_3_3_FLEXIO3          0x026c 0x0570 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_XSPI1_DATA3__GPIO7_IO19                   0x026c 0x0570 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_XSPI1_DATA4__XSPI1_A_DATA4                0x0270 0x0574 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_XSPI1_DATA4__SAI4_RX_SYNC                 0x0270 0x0574 0x0814 0x01 0x02</div><div class='add'>+#define IMX94_PAD_XSPI1_DATA4__XSPI_SLV_DATA4               0x0270 0x0574 0x0918 0x03 0x01</div><div class='add'>+#define IMX94_PAD_XSPI1_DATA4__FLEXIO1_3_3_FLEXIO4          0x0270 0x0574 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_XSPI1_DATA4__GPIO7_IO20                   0x0270 0x0574 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_XSPI1_DATA5__XSPI1_A_DATA5                0x0274 0x0578 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_XSPI1_DATA5__SAI4_TX_SYNC                 0x0274 0x0578 0x081c 0x01 0x02</div><div class='add'>+#define IMX94_PAD_XSPI1_DATA5__XSPI_SLV_DATA5               0x0274 0x0578 0x091c 0x03 0x01</div><div class='add'>+#define IMX94_PAD_XSPI1_DATA5__FLEXIO1_3_3_FLEXIO5          0x0274 0x0578 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_XSPI1_DATA5__GPIO7_IO21                   0x0274 0x0578 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_XSPI1_DATA6__XSPI1_A_DATA6                0x0278 0x057c 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_XSPI1_DATA6__SAI4_TX_DATA0                0x0278 0x057c 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_XSPI1_DATA6__XSPI_SLV_DATA6               0x0278 0x057c 0x0920 0x03 0x01</div><div class='add'>+#define IMX94_PAD_XSPI1_DATA6__FLEXIO1_3_3_FLEXIO6          0x0278 0x057c 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_XSPI1_DATA6__GPIO7_IO22                   0x0278 0x057c 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_XSPI1_DATA7__XSPI1_A_DATA7                0x027c 0x0580 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_XSPI1_DATA7__SAI4_RX_DATA0                0x027c 0x0580 0x0810 0x01 0x02</div><div class='add'>+#define IMX94_PAD_XSPI1_DATA7__SAI4_MCLK                    0x027c 0x0580 0x0808 0x02 0x02</div><div class='add'>+#define IMX94_PAD_XSPI1_DATA7__XSPI_SLV_DATA7               0x027c 0x0580 0x0924 0x03 0x01</div><div class='add'>+#define IMX94_PAD_XSPI1_DATA7__FLEXIO1_3_3_FLEXIO7          0x027c 0x0580 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_XSPI1_DATA7__GPIO7_IO23                   0x027c 0x0580 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_XSPI1_DQS__XSPI1_A_DQS                    0x0280 0x0584 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_XSPI1_DQS__SAI2_TX_BCLK                   0x0280 0x0584 0x07f8 0x01 0x03</div><div class='add'>+#define IMX94_PAD_XSPI1_DQS__XSPI_SLV_DQS                   0x0280 0x0584 0x0900 0x03 0x01</div><div class='add'>+#define IMX94_PAD_XSPI1_DQS__FLEXIO1_3_3_FLEXIO8            0x0280 0x0584 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_XSPI1_DQS__GPIO7_IO24                     0x0280 0x0584 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_XSPI1_SCLK__XSPI1_A_SCLK                  0x0284 0x0588 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_XSPI1_SCLK__SAI4_TX_BCLK                  0x0284 0x0588 0x0818 0x01 0x02</div><div class='add'>+#define IMX94_PAD_XSPI1_SCLK__XSPI_SLV_CLK                  0x0284 0x0588 0x0904 0x03 0x01</div><div class='add'>+#define IMX94_PAD_XSPI1_SCLK__FLEXIO1_3_3_FLEXIO9           0x0284 0x0588 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_XSPI1_SCLK__GPIO7_IO25                    0x0284 0x0588 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_XSPI1_SS0_B__XSPI1_A_SS0_B                0x0288 0x058c 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_XSPI1_SS0_B__SAI4_RX_BCLK                 0x0288 0x058c 0x080c 0x01 0x02</div><div class='add'>+#define IMX94_PAD_XSPI1_SS0_B__XSPI_SLV_CS                  0x0288 0x058c 0x08fc 0x03 0x01</div><div class='add'>+#define IMX94_PAD_XSPI1_SS0_B__FLEXIO1_3_3_FLEXIO10         0x0288 0x058c 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_XSPI1_SS0_B__GPIO7_IO26                   0x0288 0x058c 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_XSPI1_SS1_B__XSPI1_A_SS1_B                0x028c 0x0590 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_XSPI1_SS1_B__SAI2_RX_BCLK                 0x028c 0x0590 0x07ec 0x01 0x02</div><div class='add'>+#define IMX94_PAD_XSPI1_SS1_B__FLEXPWM3_PWMX3               0x028c 0x0590 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_XSPI1_SS1_B__FLEXIO1_3_3_FLEXIO11         0x028c 0x0590 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_XSPI1_SS1_B__GPIO7_IO27                   0x028c 0x0590 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_XSPI1_SS1_B__SINC1_MOD_CLK0               0x028c 0x0590 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_XSPI1_SS1_B__SINC_FILTER_GLUE1_BREAK      0x028c 0x0590 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_SD2_CD_B__USDHC2_CD_B                     0x0290 0x0594 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_SD2_CD_B__NETC_PINMUX_ETH4_RX_CTL         0x0290 0x0594 0x0634 0x01 0x01</div><div class='add'>+#define IMX94_PAD_SD2_CD_B__I3C2_SCL                        0x0290 0x0594 0x0720 0x02 0x03</div><div class='add'>+#define IMX94_PAD_SD2_CD_B__NETC_1588MUX_INOUT9             0x0290 0x0594 0x0670 0x03 0x02</div><div class='add'>+#define IMX94_PAD_SD2_CD_B__FLEXIO2_4_2_FLEXIO0             0x0290 0x0594 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_SD2_CD_B__GPIO4_IO20                      0x0290 0x0594 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_SD2_CD_B__XBAR1_XBAR_INOUT13              0x0290 0x0594 0x0890 0x06 0x02</div><div class='add'>+#define IMX94_PAD_SD2_CD_B__SINC2_EMCLK0                    0x0290 0x0594 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_SD2_CLK__USDHC2_CLK                       0x0294 0x0598 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_SD2_CLK__NETC_PINMUX_ETH4_TX_CLK          0x0294 0x0598 0x0648 0x01 0x01</div><div class='add'>+#define IMX94_PAD_SD2_CLK__I3C2_SDA                         0x0294 0x0598 0x0724 0x02 0x03</div><div class='add'>+#define IMX94_PAD_SD2_CLK__NETC_1588MUX_INOUT8              0x0294 0x0598 0x066c 0x03 0x02</div><div class='add'>+#define IMX94_PAD_SD2_CLK__FLEXIO2_4_2_FLEXIO1              0x0294 0x0598 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_SD2_CLK__GPIO4_IO21                       0x0294 0x0598 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_SD2_CLK__OBSERVE0                         0x0294 0x0598 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_SD2_CLK__SINC2_EMBIT0                     0x0294 0x0598 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_SD2_CMD__USDHC2_CMD                       0x0298 0x059c 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_SD2_CMD__NETC_PINMUX_ETH4_TX_CTL          0x0298 0x059c 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_SD2_CMD__I3C2_PUR                         0x0298 0x059c 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_SD2_CMD__I3C2_PUR_B                       0x0298 0x059c 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_SD2_CMD__FLEXIO2_4_2_FLEXIO2              0x0298 0x059c 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_SD2_CMD__GPIO4_IO22                       0x0298 0x059c 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_SD2_CMD__OBSERVE1                         0x0298 0x059c 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_SD2_CMD__SINC2_EMCLK1                     0x0298 0x059c 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_SD2_DATA0__USDHC2_DATA0                   0x029c 0x05a0 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_SD2_DATA0__NETC_PINMUX_ETH4_TXD0          0x029c 0x05a0 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_SD2_DATA0__CAN2_TX                        0x029c 0x05a0 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_SD2_DATA0__NETC_1588MUX_INOUT7            0x029c 0x05a0 0x0668 0x03 0x02</div><div class='add'>+#define IMX94_PAD_SD2_DATA0__FLEXIO2_4_2_FLEXIO3            0x029c 0x05a0 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_SD2_DATA0__GPIO4_IO23                     0x029c 0x05a0 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_SD2_DATA0__OBSERVE2                       0x029c 0x05a0 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_SD2_DATA0__SINC2_EMBIT1                   0x029c 0x05a0 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_SD2_DATA1__USDHC2_DATA1                   0x02a0 0x05a4 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_SD2_DATA1__NETC_PINMUX_ETH4_TXD1          0x02a0 0x05a4 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_SD2_DATA1__CAN2_RX                        0x02a0 0x05a4 0x067c 0x02 0x04</div><div class='add'>+#define IMX94_PAD_SD2_DATA1__NETC_1588MUX_INOUT6            0x02a0 0x05a4 0x0664 0x03 0x02</div><div class='add'>+#define IMX94_PAD_SD2_DATA1__FLEXIO2_4_2_FLEXIO4            0x02a0 0x05a4 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_SD2_DATA1__GPIO4_IO24                     0x02a0 0x05a4 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_SD2_DATA1__XBAR1_XBAR_INOUT14             0x02a0 0x05a4 0x0894 0x06 0x02</div><div class='add'>+#define IMX94_PAD_SD2_DATA1__SINC2_EMCLK2                   0x02a0 0x05a4 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_SD2_DATA2__USDHC2_DATA2                   0x02a4 0x05a8 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_SD2_DATA2__NETC_PINMUX_ETH4_TXD2          0x02a4 0x05a8 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_SD2_DATA2__MQS2_RIGHT                     0x02a4 0x05a8 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_SD2_DATA2__NETC_1588MUX_INOUT5            0x02a4 0x05a8 0x0660 0x03 0x02</div><div class='add'>+#define IMX94_PAD_SD2_DATA2__FLEXIO2_4_2_FLEXIO5            0x02a4 0x05a8 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_SD2_DATA2__GPIO4_IO25                     0x02a4 0x05a8 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_SD2_DATA2__XBAR1_XBAR_INOUT15             0x02a4 0x05a8 0x0898 0x06 0x01</div><div class='add'>+#define IMX94_PAD_SD2_DATA2__SINC2_EMBIT2                   0x02a4 0x05a8 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_SD2_DATA3__USDHC2_DATA3                   0x02a8 0x05ac 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_SD2_DATA3__NETC_PINMUX_ETH4_TXD3          0x02a8 0x05ac 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_SD2_DATA3__MQS2_LEFT                      0x02a8 0x05ac 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_SD2_DATA3__LPTMR2_ALT0                    0x02a8 0x05ac 0x0780 0x03 0x01</div><div class='add'>+#define IMX94_PAD_SD2_DATA3__FLEXIO2_4_2_FLEXIO6            0x02a8 0x05ac 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_SD2_DATA3__GPIO4_IO26                     0x02a8 0x05ac 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_SD2_DATA3__XBAR1_XBAR_INOUT16             0x02a8 0x05ac 0x089c 0x06 0x01</div><div class='add'>+#define IMX94_PAD_SD2_DATA3__SINC2_EMCLK3                   0x02a8 0x05ac 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_SD2_RESET_B__USDHC2_RESET_B               0x02ac 0x05b0 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_SD2_RESET_B__NETC_PINMUX_ETH4_RXD0        0x02ac 0x05b0 0x0638 0x01 0x01</div><div class='add'>+#define IMX94_PAD_SD2_RESET_B__NETC_1588MUX_INOUT4          0x02ac 0x05b0 0x065c 0x02 0x02</div><div class='add'>+#define IMX94_PAD_SD2_RESET_B__LPTMR2_ALT1                  0x02ac 0x05b0 0x0784 0x03 0x01</div><div class='add'>+#define IMX94_PAD_SD2_RESET_B__FLEXIO2_4_2_FLEXIO7          0x02ac 0x05b0 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_SD2_RESET_B__GPIO4_IO27                   0x02ac 0x05b0 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_SD2_RESET_B__XBAR1_XBAR_INOUT17           0x02ac 0x05b0 0x08a0 0x06 0x01</div><div class='add'>+#define IMX94_PAD_SD2_RESET_B__SINC2_EMBIT3                 0x02ac 0x05b0 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_SD2_GPIO0__USDHC2_WP                      0x02b0 0x05b4 0x0854 0x00 0x03</div><div class='add'>+#define IMX94_PAD_SD2_GPIO0__NETC_PINMUX_ETH4_RXD1          0x02b0 0x05b4 0x063c 0x01 0x01</div><div class='add'>+#define IMX94_PAD_SD2_GPIO0__NETC_1588MUX_INOUT3            0x02b0 0x05b4 0x0658 0x03 0x02</div><div class='add'>+#define IMX94_PAD_SD2_GPIO0__FLEXIO2_4_2_FLEXIO8            0x02b0 0x05b4 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_SD2_GPIO0__GPIO4_IO28                     0x02b0 0x05b4 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_SD2_GPIO0__XBAR1_XBAR_INOUT18             0x02b0 0x05b4 0x08a4 0x06 0x01</div><div class='add'>+#define IMX94_PAD_SD2_GPIO0__SINC2_MOD_CLK1                 0x02b0 0x05b4 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_SD2_GPIO1__LPTMR2_ALT2                    0x02b4 0x05b8 0x0788 0x00 0x01</div><div class='add'>+#define IMX94_PAD_SD2_GPIO1__NETC_PINMUX_ETH4_RXD2          0x02b4 0x05b8 0x0640 0x01 0x01</div><div class='add'>+#define IMX94_PAD_SD2_GPIO1__ECAT_CLK25                     0x02b4 0x05b8 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_SD2_GPIO1__NETC_1588MUX_INOUT2            0x02b4 0x05b8 0x0654 0x03 0x02</div><div class='add'>+#define IMX94_PAD_SD2_GPIO1__FLEXIO2_4_2_FLEXIO9            0x02b4 0x05b8 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_SD2_GPIO1__GPIO4_IO29                     0x02b4 0x05b8 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_SD2_GPIO1__XBAR1_XBAR_INOUT19             0x02b4 0x05b8 0x08a8 0x06 0x01</div><div class='add'>+#define IMX94_PAD_SD2_GPIO1__SINC2_MOD_CLK0                 0x02b4 0x05b8 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_SD2_GPIO2__NETC_PINMUX_ETH4_RXD3          0x02b8 0x05bc 0x0644 0x01 0x01</div><div class='add'>+#define IMX94_PAD_SD2_GPIO2__CAN5_TX                        0x02b8 0x05bc 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_SD2_GPIO2__NETC_1588MUX_INOUT1            0x02b8 0x05bc 0x0650 0x03 0x02</div><div class='add'>+#define IMX94_PAD_SD2_GPIO2__FLEXIO2_4_2_FLEXIO10           0x02b8 0x05bc 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_SD2_GPIO2__GPIO4_IO30                     0x02b8 0x05bc 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_SD2_GPIO2__XBAR1_XBAR_INOUT20             0x02b8 0x05bc 0x08ac 0x06 0x01</div><div class='add'>+#define IMX94_PAD_SD2_GPIO2__SINC2_MOD_CLK2                 0x02b8 0x05bc 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_SD2_GPIO3__NETC_PINMUX_ETH4_RX_CLK        0x02bc 0x05c0 0x0630 0x01 0x01</div><div class='add'>+#define IMX94_PAD_SD2_GPIO3__CAN5_RX                        0x02bc 0x05c0 0x0688 0x02 0x04</div><div class='add'>+#define IMX94_PAD_SD2_GPIO3__NETC_1588MUX_INOUT0            0x02bc 0x05c0 0x064c 0x03 0x02</div><div class='add'>+#define IMX94_PAD_SD2_GPIO3__FLEXIO2_4_2_FLEXIO11           0x02bc 0x05c0 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_SD2_GPIO3__GPIO4_IO31                     0x02bc 0x05c0 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_SD2_GPIO3__XBAR1_XBAR_INOUT21             0x02bc 0x05c0 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_SD2_GPIO3__SINC_FILTER_GLUE2_BREAK        0x02bc 0x05c0 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_I2C1_SCL__LPI2C1_SCL                      0x02c0 0x05c4 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_I2C1_SCL__I3C1_SCL                        0x02c0 0x05c4 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_I2C1_SCL__LPUART1_DCD_B                   0x02c0 0x05c4 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_I2C1_SCL__TPM2_CH0                        0x02c0 0x05c4 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_I2C1_SCL__SAI1_RX_SYNC                    0x02c0 0x05c4 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_I2C1_SCL__GPIO1_IO0                       0x02c0 0x05c4 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_I2C1_SDA__LPI2C1_SDA                      0x02c4 0x05c8 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_I2C1_SDA__I3C1_SDA                        0x02c4 0x05c8 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_I2C1_SDA__LPUART1_RIN_B                   0x02c4 0x05c8 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_I2C1_SDA__TPM2_CH1                        0x02c4 0x05c8 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_I2C1_SDA__SAI1_RX_BCLK                    0x02c4 0x05c8 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_I2C1_SDA__GPIO1_IO1                       0x02c4 0x05c8 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_I2C2_SCL__LPI2C2_SCL                      0x02c8 0x05cc 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_I2C2_SCL__I3C1_PUR                        0x02c8 0x05cc 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_I2C2_SCL__LPUART2_DCD_B                   0x02c8 0x05cc 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_I2C2_SCL__TPM2_CH2                        0x02c8 0x05cc 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_I2C2_SCL__GPT1_CLK                        0x02c8 0x05cc 0x060c 0x04 0x00</div><div class='add'>+#define IMX94_PAD_I2C2_SCL__GPIO1_IO2                       0x02c8 0x05cc 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_I2C2_SCL__I3C1_PUR_B                      0x02c8 0x05cc 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_I2C2_SCL__LPIT1_TRIGGER0                  0x02c8 0x05cc 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_I2C2_SDA__LPI2C2_SDA                      0x02cc 0x05d0 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_I2C2_SDA__LPI2C1_HREQ                     0x02cc 0x05d0 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_I2C2_SDA__LPUART2_RIN_B                   0x02cc 0x05d0 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_I2C2_SDA__TPM2_CH3                        0x02cc 0x05d0 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_I2C2_SDA__SAI1_MCLK                       0x02cc 0x05d0 0x0620 0x04 0x00</div><div class='add'>+#define IMX94_PAD_I2C2_SDA__GPIO1_IO3                       0x02cc 0x05d0 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_I2C2_SDA__EWM_OUT_B                       0x02cc 0x05d0 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_I2C2_SDA__LPIT1_TRIGGER1                  0x02cc 0x05d0 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_UART1_RXD__LPUART1_RX                     0x02d0 0x05d4 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_UART1_RXD__S400_UART_RX                   0x02d0 0x05d4 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_UART1_RXD__LPSPI2_SIN                     0x02d0 0x05d4 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_UART1_RXD__TPM1_CH0                       0x02d0 0x05d4 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_UART1_RXD__GPT1_CAPTURE1                  0x02d0 0x05d4 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_UART1_RXD__GPIO1_IO4                      0x02d0 0x05d4 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_UART1_TXD__LPUART1_TX                     0x02d4 0x05d8 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_UART1_TXD__S400_UART_TX                   0x02d4 0x05d8 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_UART1_TXD__LPSPI2_PCS0                    0x02d4 0x05d8 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_UART1_TXD__TPM1_CH1                       0x02d4 0x05d8 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_UART1_TXD__GPT1_COMPARE1                  0x02d4 0x05d8 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_UART1_TXD__GPIO1_IO5                      0x02d4 0x05d8 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_UART2_RXD__LPUART2_RX                     0x02d8 0x05dc 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_UART2_RXD__LPUART1_CTS_B                  0x02d8 0x05dc 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_UART2_RXD__LPSPI2_SOUT                    0x02d8 0x05dc 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_UART2_RXD__TPM1_CH2                       0x02d8 0x05dc 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_UART2_RXD__SAI1_MCLK                      0x02d8 0x05dc 0x0620 0x04 0x01</div><div class='add'>+#define IMX94_PAD_UART2_RXD__GPIO1_IO6                      0x02d8 0x05dc 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_UART2_RXD__GPT1_CLK                       0x02d8 0x05dc 0x060c 0x06 0x01</div><div class='add'>+#define IMX94_PAD_UART2_RXD__LPIT1_TRIGGER2                 0x02d8 0x05dc 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_UART2_TXD__LPUART2_TX                     0x02dc 0x05e0 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_UART2_TXD__LPUART1_RTS_B                  0x02dc 0x05e0 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_UART2_TXD__LPSPI2_SCK                     0x02dc 0x05e0 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_UART2_TXD__TPM1_CH3                       0x02dc 0x05e0 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_UART2_TXD__GPIO1_IO7                      0x02dc 0x05e0 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_PDM_CLK__PDM_CLK                          0x02e0 0x05e4 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_PDM_CLK__MQS1_LEFT                        0x02e0 0x05e4 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_PDM_CLK__LPTMR1_ALT0                      0x02e0 0x05e4 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_PDM_CLK__GPIO1_IO8                        0x02e0 0x05e4 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_PDM_CLK__CAN1_TX                          0x02e0 0x05e4 0x0000 0x06 0x00</div><div class='add'>+#define IMX94_PAD_PDM_CLK__EWM_OUT_B                        0x02e0 0x05e4 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM0          0x02e4 0x05e8 0x0610 0x00 0x02</div><div class='add'>+#define IMX94_PAD_PDM_BIT_STREAM0__MQS1_RIGHT               0x02e4 0x05e8 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1              0x02e4 0x05e8 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK              0x02e4 0x05e8 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_PDM_BIT_STREAM0__LPTMR1_ALT1              0x02e4 0x05e8 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_PDM_BIT_STREAM0__GPIO1_IO9                0x02e4 0x05e8 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_PDM_BIT_STREAM0__CAN1_RX                  0x02e4 0x05e8 0x0608 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM1          0x02e8 0x05ec 0x0614 0x00 0x03</div><div class='add'>+#define IMX94_PAD_PDM_BIT_STREAM1__NMI_GLUE_NMI             0x02e8 0x05ec 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1              0x02e8 0x05ec 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK              0x02e8 0x05ec 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_PDM_BIT_STREAM1__LPTMR1_ALT2              0x02e8 0x05ec 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_PDM_BIT_STREAM1__GPIO1_IO10               0x02e8 0x05ec 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_PDM_BIT_STREAM1__EXT_CLK1                 0x02e8 0x05ec 0x0624 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_SAI1_TXFS__SAI1_TX_SYNC                   0x02ec 0x05f0 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_SAI1_TXFS__SAI1_TX_DATA1                  0x02ec 0x05f0 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_SAI1_TXFS__LPSPI1_PCS0                    0x02ec 0x05f0 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_SAI1_TXFS__LPUART2_DTR_B                  0x02ec 0x05f0 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_SAI1_TXFS__MQS1_LEFT                      0x02ec 0x05f0 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_SAI1_TXFS__GPIO1_IO11                     0x02ec 0x05f0 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_SAI1_TXFS__EWM_OUT_B                      0x02ec 0x05f0 0x0000 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_SAI1_TXC__SAI1_TX_BCLK                    0x02f0 0x05f4 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_SAI1_TXC__LPUART2_CTS_B                   0x02f0 0x05f4 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_SAI1_TXC__LPSPI1_SIN                      0x02f0 0x05f4 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_SAI1_TXC__LPUART1_DSR_B                   0x02f0 0x05f4 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_SAI1_TXC__CAN1_RX                         0x02f0 0x05f4 0x0608 0x04 0x01</div><div class='add'>+#define IMX94_PAD_SAI1_TXC__GPIO1_IO12                      0x02f0 0x05f4 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_SAI1_TXD0__SAI1_TX_DATA0                  0x02f4 0x05f8 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_SAI1_TXD0__LPUART2_RTS_B                  0x02f4 0x05f8 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_SAI1_TXD0__LPSPI1_SCK                     0x02f4 0x05f8 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_SAI1_TXD0__LPUART1_DTR_B                  0x02f4 0x05f8 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_SAI1_TXD0__CAN1_TX                        0x02f4 0x05f8 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_SAI1_TXD0__GPIO1_IO13                     0x02f4 0x05f8 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_SAI1_RXD0__SAI1_RX_DATA0                  0x02f8 0x05fc 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_SAI1_RXD0__SAI1_MCLK                      0x02f8 0x05fc 0x0620 0x01 0x02</div><div class='add'>+#define IMX94_PAD_SAI1_RXD0__LPSPI1_SOUT                    0x02f8 0x05fc 0x0000 0x02 0x00</div><div class='add'>+#define IMX94_PAD_SAI1_RXD0__LPUART2_DSR_B                  0x02f8 0x05fc 0x0000 0x03 0x00</div><div class='add'>+#define IMX94_PAD_SAI1_RXD0__MQS1_RIGHT                     0x02f8 0x05fc 0x0000 0x04 0x00</div><div class='add'>+#define IMX94_PAD_SAI1_RXD0__GPIO1_IO14                     0x02f8 0x05fc 0x0000 0x05 0x00</div><div class='add'>+#define IMX94_PAD_SAI1_RXD0__LPIT1_TRIGGER3                 0x02f8 0x05fc 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX94_PAD_WDOG_ANY__WDOG_ANY                        0x02fc 0x0600 0x0000 0x00 0x00</div><div class='add'>+#define IMX94_PAD_WDOG_ANY__FCCU_EOUT1                      0x02fc 0x0600 0x0000 0x01 0x00</div><div class='add'>+#define IMX94_PAD_WDOG_ANY__GPIO1_IO15                      0x02fc 0x0600 0x0000 0x05 0x00</div><div class='add'>+#endif /* __DTS_IMX94_PINFUNC_H */</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx94-power.h b/arch/arm64/boot/dts/freescale/imx94-power.h<br/>new file mode 100644<br/>index 000000000000..5209afed60ed<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx94-power.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx94-power.h</a></div><div class='hunk'>@@ -0,0 +1,41 @@</div><div class='add'>+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */</div><div class='add'>+/*</div><div class='add'>+ *  Copyright 2024-2025 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __IMX94_POWER_H</div><div class='add'>+#define __IMX94_POWER_H</div><div class='add'>+</div><div class='add'>+#define IMX94_PD_ANA		0</div><div class='add'>+#define IMX94_PD_AON		1</div><div class='add'>+#define IMX94_PD_BBSM		2</div><div class='add'>+#define IMX94_PD_M71		3</div><div class='add'>+#define IMX94_PD_CCMSRCGPC	4</div><div class='add'>+#define IMX94_PD_A55C0		5</div><div class='add'>+#define IMX94_PD_A55C1		6</div><div class='add'>+#define IMX94_PD_A55C2		7</div><div class='add'>+#define IMX94_PD_A55C3		8</div><div class='add'>+#define IMX94_PD_A55P		9</div><div class='add'>+#define IMX94_PD_DDR		10</div><div class='add'>+#define IMX94_PD_DISPLAY	11</div><div class='add'>+#define IMX94_PD_M70		12</div><div class='add'>+#define IMX94_PD_HSIO_TOP	13</div><div class='add'>+#define IMX94_PD_HSIO_WAON	14</div><div class='add'>+#define IMX94_PD_NETC		15</div><div class='add'>+#define IMX94_PD_NOC		16</div><div class='add'>+#define IMX94_PD_NPU		17</div><div class='add'>+#define IMX94_PD_WAKEUP		18</div><div class='add'>+</div><div class='add'>+#define IMX94_PERF_M33		0</div><div class='add'>+#define IMX94_PERF_M33S		1</div><div class='add'>+#define IMX94_PERF_WAKEUP	2</div><div class='add'>+#define IMX94_PERF_M70		3</div><div class='add'>+#define IMX94_PERF_M71		4</div><div class='add'>+#define IMX94_PERF_DRAM		5</div><div class='add'>+#define IMX94_PERF_HSIO		6</div><div class='add'>+#define IMX94_PERF_NPU		7</div><div class='add'>+#define IMX94_PERF_NOC		8</div><div class='add'>+#define IMX94_PERF_A55		9</div><div class='add'>+#define IMX94_PERF_DISP		10</div><div class='add'>+</div><div class='add'>+#endif /* __IMX94_POWER_H */</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx94.dtsi b/arch/arm64/boot/dts/freescale/imx94.dtsi<br/>new file mode 100644<br/>index 000000000000..73184f03f8a3<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx94.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx94.dtsi</a></div><div class='hunk'>@@ -0,0 +1,1200 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024-2025 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/dma/fsl-edma.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+</div><div class='add'>+#include "imx94-clock.h"</div><div class='add'>+#include "imx94-pinfunc.h"</div><div class='add'>+#include "imx94-power.h"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+</div><div class='add'>+	osc_24m: clock-24m {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+		clock-output-names = "osc_24m";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dummy: clock-dummy {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;0&gt;;</div><div class='add'>+		clock-output-names = "dummy";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_ext1: clock-ext1 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;133000000&gt;;</div><div class='add'>+		clock-output-names = "clk_ext1";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sai1_mclk: clock-sai1-mclk1 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;0&gt;;</div><div class='add'>+		clock-output-names = "sai1_mclk";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sai2_mclk: clock-sai2-mclk1 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;0&gt;;</div><div class='add'>+		clock-output-names = "sai2_mclk";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sai3_mclk: clock-sai3-mclk1 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;0&gt;;</div><div class='add'>+		clock-output-names = "sai3_mclk";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sai4_mclk: clock-sai4-mclk1 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;0&gt;;</div><div class='add'>+		clock-output-names = "sai4_mclk";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	firmware {</div><div class='add'>+		scmi {</div><div class='add'>+			compatible = "arm,scmi";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			mboxes = &lt;&amp;mu2 5 0&gt;, &lt;&amp;mu2 3 0&gt;, &lt;&amp;mu2 3 1&gt;, &lt;&amp;mu2 5 1&gt;;</div><div class='add'>+			shmem = &lt;&amp;scmi_buf0&gt;, &lt;&amp;scmi_buf1&gt;;</div><div class='add'>+			arm,max-rx-timeout-ms = &lt;5000&gt;;</div><div class='add'>+</div><div class='add'>+			scmi_devpd: protocol@11 {</div><div class='add'>+				reg = &lt;0x11&gt;;</div><div class='add'>+				#power-domain-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			scmi_sys_power: protocol@12 {</div><div class='add'>+				reg = &lt;0x12&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			scmi_perf: protocol@13 {</div><div class='add'>+				reg = &lt;0x13&gt;;</div><div class='add'>+				#power-domain-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			scmi_clk: protocol@14 {</div><div class='add'>+				reg = &lt;0x14&gt;;</div><div class='add'>+				#clock-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			scmi_iomuxc: protocol@19 {</div><div class='add'>+				reg = &lt;0x19&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			scmi_bbm: protocol@81 {</div><div class='add'>+				reg = &lt;0x81&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			scmi_misc: protocol@84 {</div><div class='add'>+				reg = &lt;0x84&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mqs1: mqs1 {</div><div class='add'>+		compatible = "fsl,imx943-aonmix-mqs";</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mqs2: mqs2 {</div><div class='add'>+		compatible = "fsl,imx943-wakeupmix-mqs";</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu {</div><div class='add'>+		compatible = "arm,cortex-a55-pmu";</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-1.0";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		arm,no-tick-in-suspend;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gic: interrupt-controller@48000000 {</div><div class='add'>+		compatible = "arm,gic-v3";</div><div class='add'>+		reg = &lt;0 0x48000000 0 0x10000&gt;,</div><div class='add'>+		      &lt;0 0x48060000 0 0xc0000&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+		#interrupt-cells = &lt;3&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		dma-noncoherent;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+</div><div class='add'>+		its: msi-controller@48040000 {</div><div class='add'>+			compatible = "arm,gic-v3-its";</div><div class='add'>+			reg = &lt;0 0x48040000 0 0x20000&gt;;</div><div class='add'>+			#msi-cells = &lt;1&gt;;</div><div class='add'>+			dma-noncoherent;</div><div class='add'>+			msi-controller;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		ranges;</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		aips2: bus@42000000 {</div><div class='add'>+			compatible = "fsl,aips-bus", "simple-bus";</div><div class='add'>+			reg = &lt;0x0 0x42000000 0x0 0x800000&gt;;</div><div class='add'>+			ranges = &lt;0x42000000 0x0 0x42000000 0x8000000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			edma2: dma-controller@42000000 {</div><div class='add'>+				compatible = "fsl,imx94-edma5", "fsl,imx95-edma5";</div><div class='add'>+				reg = &lt;0x42000000 0x210000&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_BUSWAKEUP&gt;;</div><div class='add'>+				clock-names = "dma";</div><div class='add'>+				#dma-cells = &lt;3&gt;;</div><div class='add'>+				dma-channels = &lt;64&gt;;</div><div class='add'>+				interrupts-extended = &lt;&amp;a55_irqsteer 0&gt;, &lt;&amp;a55_irqsteer 1&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 2&gt;, &lt;&amp;a55_irqsteer 3&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 4&gt;, &lt;&amp;a55_irqsteer 5&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 6&gt;, &lt;&amp;a55_irqsteer 7&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 8&gt;, &lt;&amp;a55_irqsteer 9&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 10&gt;, &lt;&amp;a55_irqsteer 11&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 12&gt;, &lt;&amp;a55_irqsteer 13&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 14&gt;, &lt;&amp;a55_irqsteer 15&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 16&gt;, &lt;&amp;a55_irqsteer 17&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 18&gt;, &lt;&amp;a55_irqsteer 19&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 20&gt;, &lt;&amp;a55_irqsteer 21&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 22&gt;, &lt;&amp;a55_irqsteer 23&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 24&gt;, &lt;&amp;a55_irqsteer 25&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 26&gt;, &lt;&amp;a55_irqsteer 27&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 28&gt;, &lt;&amp;a55_irqsteer 29&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 30&gt;, &lt;&amp;a55_irqsteer 31&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 64&gt;, &lt;&amp;a55_irqsteer 65&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 66&gt;, &lt;&amp;a55_irqsteer 67&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 68&gt;, &lt;&amp;a55_irqsteer 69&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 70&gt;, &lt;&amp;a55_irqsteer 71&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 72&gt;, &lt;&amp;a55_irqsteer 73&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 74&gt;, &lt;&amp;a55_irqsteer 75&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 76&gt;, &lt;&amp;a55_irqsteer 77&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 78&gt;, &lt;&amp;a55_irqsteer 79&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 80&gt;, &lt;&amp;a55_irqsteer 81&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 82&gt;, &lt;&amp;a55_irqsteer 83&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 84&gt;, &lt;&amp;a55_irqsteer 85&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 86&gt;, &lt;&amp;a55_irqsteer 87&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 88&gt;, &lt;&amp;a55_irqsteer 89&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 90&gt;, &lt;&amp;a55_irqsteer 91&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 92&gt;, &lt;&amp;a55_irqsteer 93&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 94&gt;, &lt;&amp;a55_irqsteer 95&gt;,</div><div class='add'>+						      &lt;&amp;gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mu10: mailbox@42430000 {</div><div class='add'>+				compatible = "fsl,imx94-mu", "fsl,imx95-mu";</div><div class='add'>+				reg = &lt;0x42430000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_BUSWAKEUP&gt;;</div><div class='add'>+				#mbox-cells = &lt;2&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i3c2: i3c@42520000 {</div><div class='add'>+				compatible = "silvaco,i3c-master-v1";</div><div class='add'>+				reg = &lt;0x42520000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;3&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_BUSWAKEUP&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX94_CLK_I3C2SLOW&gt;,</div><div class='add'>+					 &lt;&amp;dummy&gt;;</div><div class='add'>+				clock-names = "pclk", "fast_clk", "slow_clk";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpi2c3: i2c@42530000 {</div><div class='add'>+				compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+				reg = &lt;0x42530000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_LPI2C3&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX94_CLK_BUSWAKEUP&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma2 5 0 0&gt;, &lt;&amp;edma2 6 0 FSL_EDMA_RX&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpi2c4: i2c@42540000 {</div><div class='add'>+				compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+				reg = &lt;0x42540000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_LPI2C4&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX94_CLK_BUSWAKEUP&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma4 4 0 0&gt;, &lt;&amp;edma4 5 0 FSL_EDMA_RX&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpspi3: spi@42550000 {</div><div class='add'>+				compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi";</div><div class='add'>+				reg = &lt;0x42550000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_LPSPI3&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX94_CLK_BUSWAKEUP&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma2 7 0 0&gt;, &lt;&amp;edma2 8 0 FSL_EDMA_RX&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpspi4: spi@42560000 {</div><div class='add'>+				compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi";</div><div class='add'>+				reg = &lt;0x42560000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_LPSPI4&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX94_CLK_BUSWAKEUP&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma4 6 0 0&gt;, &lt;&amp;edma4 7 0 FSL_EDMA_RX&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpuart3: serial@42570000 {</div><div class='add'>+				compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",</div><div class='add'>+					     "fsl,imx7ulp-lpuart";</div><div class='add'>+				reg = &lt;0x42570000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_LPUART3&gt;;</div><div class='add'>+				clock-names = "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma2 10 0 FSL_EDMA_RX&gt;, &lt;&amp;edma2 9 0 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpuart4: serial@42580000 {</div><div class='add'>+				compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",</div><div class='add'>+					     "fsl,imx7ulp-lpuart";</div><div class='add'>+				reg = &lt;0x42580000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_LPUART4&gt;;</div><div class='add'>+				clock-names = "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma4 10 0 FSL_EDMA_RX&gt;, &lt;&amp;edma4 9 0 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpuart5: serial@42590000 {</div><div class='add'>+				compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",</div><div class='add'>+					     "fsl,imx7ulp-lpuart";</div><div class='add'>+				reg = &lt;0x42590000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_LPUART5&gt;;</div><div class='add'>+				clock-names = "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma2 12 0 FSL_EDMA_RX&gt;, &lt;&amp;edma2 11 0 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpuart6: serial@425a0000 {</div><div class='add'>+				compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",</div><div class='add'>+					     "fsl,imx7ulp-lpuart";</div><div class='add'>+				reg = &lt;0x425a0000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_LPUART6&gt;;</div><div class='add'>+				clock-names = "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma4 12 0 FSL_EDMA_RX&gt;, &lt;&amp;edma4 11 0 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			flexcan2: can@425b0000 {</div><div class='add'>+				compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan";</div><div class='add'>+				reg = &lt;0x425b0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_BUSWAKEUP&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX94_CLK_CAN2&gt;;</div><div class='add'>+				clock-names = "ipg", "per";</div><div class='add'>+				assigned-clocks = &lt;&amp;scmi_clk IMX94_CLK_CAN2&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;80000000&gt;;</div><div class='add'>+				fsl,clk-source = /bits/ 8 &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			flexcan3: can@425e0000 {</div><div class='add'>+				compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan";</div><div class='add'>+				reg = &lt;0x425e0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_BUSWAKEUP&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX94_CLK_CAN3&gt;;</div><div class='add'>+				clock-names = "ipg", "per";</div><div class='add'>+				assigned-clocks = &lt;&amp;scmi_clk IMX94_CLK_CAN3&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;80000000&gt;;</div><div class='add'>+				fsl,clk-source = /bits/ 8 &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			flexcan4: can@425f0000 {</div><div class='add'>+				compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan";</div><div class='add'>+				reg = &lt;0x425f0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_BUSWAKEUP&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX94_CLK_CAN4&gt;;</div><div class='add'>+				clock-names = "ipg", "per";</div><div class='add'>+				assigned-clocks = &lt;&amp;scmi_clk IMX94_CLK_CAN4&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;80000000&gt;;</div><div class='add'>+				fsl,clk-source = /bits/ 8 &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			flexcan5: can@42600000 {</div><div class='add'>+				compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan";</div><div class='add'>+				reg = &lt;0x42600000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_BUSWAKEUP&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX94_CLK_CAN5&gt;;</div><div class='add'>+				clock-names = "ipg", "per";</div><div class='add'>+				assigned-clocks = &lt;&amp;scmi_clk IMX94_CLK_CAN5&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;80000000&gt;;</div><div class='add'>+				fsl,clk-source = /bits/ 8 &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sai2: sai@42650000 {</div><div class='add'>+				compatible = "fsl,imx94-sai", "fsl,imx95-sai";</div><div class='add'>+				reg = &lt;0x42650000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_BUSWAKEUP&gt;, &lt;&amp;dummy&gt;,</div><div class='add'>+					&lt;&amp;scmi_clk IMX94_CLK_SAI2&gt;, &lt;&amp;dummy&gt;, &lt;&amp;dummy&gt;;</div><div class='add'>+				clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";</div><div class='add'>+				dmas = &lt;&amp;edma2 30 0 FSL_EDMA_RX&gt;, &lt;&amp;edma2 29 0 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sai3: sai@42660000 {</div><div class='add'>+				compatible = "fsl,imx94-sai", "fsl,imx95-sai";</div><div class='add'>+				reg = &lt;0x42660000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_BUSWAKEUP&gt;, &lt;&amp;dummy&gt;,</div><div class='add'>+					&lt;&amp;scmi_clk IMX94_CLK_SAI3&gt;, &lt;&amp;dummy&gt;, &lt;&amp;dummy&gt;;</div><div class='add'>+				clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";</div><div class='add'>+				dmas = &lt;&amp;edma2 32 0 FSL_EDMA_RX&gt;, &lt;&amp;edma2 31 0 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sai4: sai@42670000 {</div><div class='add'>+				compatible = "fsl,imx94-sai", "fsl,imx95-sai";</div><div class='add'>+				reg = &lt;0x42670000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_BUSWAKEUP&gt;, &lt;&amp;dummy&gt;,</div><div class='add'>+					&lt;&amp;scmi_clk IMX94_CLK_SAI4&gt;, &lt;&amp;dummy&gt;, &lt;&amp;dummy&gt;;</div><div class='add'>+				clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";</div><div class='add'>+				dmas = &lt;&amp;edma2 36 0 FSL_EDMA_RX&gt;, &lt;&amp;edma2 35 0 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpuart7: serial@42690000 {</div><div class='add'>+				compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",</div><div class='add'>+					     "fsl,imx7ulp-lpuart";</div><div class='add'>+				reg = &lt;0x42690000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_LPUART7&gt;;</div><div class='add'>+				clock-names = "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma2 46 0 FSL_EDMA_RX&gt;, &lt;&amp;edma2 45 0 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpuart8: serial@426a0000 {</div><div class='add'>+				compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",</div><div class='add'>+					     "fsl,imx7ulp-lpuart";</div><div class='add'>+				reg = &lt;0x426a0000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_LPUART8&gt;;</div><div class='add'>+				clock-names = "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma4 39 0 FSL_EDMA_RX&gt;, &lt;&amp;edma4 38 0 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpi2c5: i2c@426b0000 {</div><div class='add'>+				compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+				reg = &lt;0x426b0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_LPI2C5&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX94_CLK_BUSAON&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma2 37 0 0&gt;, &lt;&amp;edma2 38 0 FSL_EDMA_RX&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpi2c6: i2c@426c0000 {</div><div class='add'>+				compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+				reg = &lt;0x426c0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_LPI2C6&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX94_CLK_BUSWAKEUP&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma4 30 0 0&gt;, &lt;&amp;edma4 31 0 FSL_EDMA_RX&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpi2c7: i2c@426d0000 {</div><div class='add'>+				compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+				reg = &lt;0x426d0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_LPI2C7&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX94_CLK_BUSWAKEUP&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma2 39 0 0&gt;, &lt;&amp;edma2 40 0 FSL_EDMA_RX&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpi2c8: i2c@426e0000 {</div><div class='add'>+				compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+				reg = &lt;0x426e0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_LPI2C8&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX94_CLK_BUSWAKEUP&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma4 32 0 0&gt;, &lt;&amp;edma4 33 0 FSL_EDMA_RX&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpspi5: spi@426f0000 {</div><div class='add'>+				compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi";</div><div class='add'>+				reg = &lt;0x426f0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_LPSPI5&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX94_CLK_BUSWAKEUP&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma2 41 0 0&gt;, &lt;&amp;edma2 42 0 FSL_EDMA_RX&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpspi6: spi@42700000 {</div><div class='add'>+				compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi";</div><div class='add'>+				reg = &lt;0x42700000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_LPSPI6&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX94_CLK_BUSWAKEUP&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma4 34 0 0&gt;, &lt;&amp;edma4 35 0 FSL_EDMA_RX&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpspi7: spi@42710000 {</div><div class='add'>+				compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi";</div><div class='add'>+				reg = &lt;0x42710000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_LPSPI7&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX94_CLK_BUSWAKEUP&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma2 43 0 0&gt;, &lt;&amp;edma2 44 0 FSL_EDMA_RX&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpspi8: spi@42720000 {</div><div class='add'>+				compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi";</div><div class='add'>+				reg = &lt;0x42720000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_LPSPI8&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX94_CLK_BUSWAKEUP&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma4 36 0 0&gt;, &lt;&amp;edma4 37 0 FSL_EDMA_RX&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mu11: mailbox@42730000 {</div><div class='add'>+				compatible = "fsl,imx94-mu", "fsl,imx95-mu";</div><div class='add'>+				reg = &lt;0x42730000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_BUSWAKEUP&gt;;</div><div class='add'>+				#mbox-cells = &lt;2&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			edma4: dma-controller@42df0000 {</div><div class='add'>+				compatible = "fsl,imx94-edma5", "fsl,imx95-edma5";</div><div class='add'>+				reg = &lt;0x42df0000 0x210000&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_BUSWAKEUP&gt;;</div><div class='add'>+				clock-names = "dma";</div><div class='add'>+				#dma-cells = &lt;3&gt;;</div><div class='add'>+				dma-channels = &lt;64&gt;;</div><div class='add'>+				interrupts-extended = &lt;&amp;a55_irqsteer 128&gt;, &lt;&amp;a55_irqsteer 129&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 130&gt;, &lt;&amp;a55_irqsteer 131&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 132&gt;, &lt;&amp;a55_irqsteer 133&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 134&gt;, &lt;&amp;a55_irqsteer 135&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 136&gt;, &lt;&amp;a55_irqsteer 137&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 138&gt;, &lt;&amp;a55_irqsteer 139&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 140&gt;, &lt;&amp;a55_irqsteer 141&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 142&gt;, &lt;&amp;a55_irqsteer 143&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 144&gt;, &lt;&amp;a55_irqsteer 145&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 146&gt;, &lt;&amp;a55_irqsteer 147&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 148&gt;, &lt;&amp;a55_irqsteer 149&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 150&gt;, &lt;&amp;a55_irqsteer 151&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 152&gt;, &lt;&amp;a55_irqsteer 153&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 154&gt;, &lt;&amp;a55_irqsteer 155&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 156&gt;, &lt;&amp;a55_irqsteer 157&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 158&gt;, &lt;&amp;a55_irqsteer 159&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 192&gt;, &lt;&amp;a55_irqsteer 193&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 194&gt;, &lt;&amp;a55_irqsteer 195&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 196&gt;, &lt;&amp;a55_irqsteer 197&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 198&gt;, &lt;&amp;a55_irqsteer 199&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 200&gt;, &lt;&amp;a55_irqsteer 201&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 202&gt;, &lt;&amp;a55_irqsteer 203&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 204&gt;, &lt;&amp;a55_irqsteer 205&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 206&gt;, &lt;&amp;a55_irqsteer 207&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 208&gt;, &lt;&amp;a55_irqsteer 209&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 210&gt;, &lt;&amp;a55_irqsteer 211&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 212&gt;, &lt;&amp;a55_irqsteer 213&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 214&gt;, &lt;&amp;a55_irqsteer 215&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 216&gt;, &lt;&amp;a55_irqsteer 217&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 218&gt;, &lt;&amp;a55_irqsteer 219&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 220&gt;, &lt;&amp;a55_irqsteer 221&gt;,</div><div class='add'>+						      &lt;&amp;a55_irqsteer 222&gt;, &lt;&amp;a55_irqsteer 223&gt;,</div><div class='add'>+						      &lt;&amp;gic GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aips3: bus@42800000 {</div><div class='add'>+			compatible = "fsl,aips-bus", "simple-bus";</div><div class='add'>+			reg = &lt;0 0x42800000 0 0x800000&gt;;</div><div class='add'>+			ranges = &lt;0x42800000 0x0 0x42800000 0x800000&gt;,</div><div class='add'>+				 &lt;0x28000000 0x0 0x28000000 0x1000000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			usdhc1: mmc@42850000 {</div><div class='add'>+				compatible = "fsl,imx94-usdhc", "fsl,imx8mm-usdhc";</div><div class='add'>+				reg = &lt;0x42850000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_BUSWAKEUP&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX94_CLK_WAKEUPAXI&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX94_CLK_USDHC1&gt;;</div><div class='add'>+				clock-names = "ipg", "ahb", "per";</div><div class='add'>+				assigned-clocks = &lt;&amp;scmi_clk IMX94_CLK_USDHC1&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;scmi_clk IMX94_CLK_SYSPLL1_PFD1&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+				bus-width = &lt;8&gt;;</div><div class='add'>+				fsl,tuning-start-tap = &lt;1&gt;;</div><div class='add'>+				fsl,tuning-step = &lt;2&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			usdhc2: mmc@42860000 {</div><div class='add'>+				compatible = "fsl,imx94-usdhc", "fsl,imx8mm-usdhc";</div><div class='add'>+				reg = &lt;0x42860000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_BUSWAKEUP&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX94_CLK_WAKEUPAXI&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX94_CLK_USDHC2&gt;;</div><div class='add'>+				clock-names = "ipg", "ahb", "per";</div><div class='add'>+				assigned-clocks = &lt;&amp;scmi_clk IMX94_CLK_USDHC2&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;scmi_clk IMX94_CLK_SYSPLL1_PFD1&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;200000000&gt;;</div><div class='add'>+				bus-width = &lt;4&gt;;</div><div class='add'>+				fsl,tuning-start-tap = &lt;1&gt;;</div><div class='add'>+				fsl,tuning-step = &lt;2&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			usdhc3: mmc@42880000 {</div><div class='add'>+				compatible = "fsl,imx94-usdhc", "fsl,imx8mm-usdhc";</div><div class='add'>+				reg = &lt;0x42880000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_BUSWAKEUP&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX94_CLK_WAKEUPAXI&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX94_CLK_USDHC3&gt;;</div><div class='add'>+				clock-names = "ipg", "ahb", "per";</div><div class='add'>+				assigned-clocks = &lt;&amp;scmi_clk IMX94_CLK_USDHC3&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;scmi_clk IMX94_CLK_SYSPLL1_PFD1&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;200000000&gt;;</div><div class='add'>+				bus-width = &lt;4&gt;;</div><div class='add'>+				fsl,tuning-start-tap = &lt;1&gt;;</div><div class='add'>+				fsl,tuning-step = &lt;2&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpuart9: serial@42a50000 {</div><div class='add'>+				compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",</div><div class='add'>+					     "fsl,imx7ulp-lpuart";</div><div class='add'>+				reg = &lt;0x42a50000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_LPUART10&gt;;</div><div class='add'>+				clock-names = "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma2 51 0 FSL_EDMA_RX&gt;, &lt;&amp;edma2 50 0 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpuart10: serial@42a60000 {</div><div class='add'>+				compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",</div><div class='add'>+					     "fsl,imx7ulp-lpuart";</div><div class='add'>+				reg = &lt;0x42a60000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_LPUART10&gt;;</div><div class='add'>+				clock-names = "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma4 47 0 FSL_EDMA_RX&gt;, &lt;&amp;edma4 46 0 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpuart11: serial@42a70000 {</div><div class='add'>+				compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",</div><div class='add'>+					     "fsl,imx7ulp-lpuart";</div><div class='add'>+				reg = &lt;0x42a70000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_LPUART11&gt;;</div><div class='add'>+				clock-names = "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma2 53 0 FSL_EDMA_RX&gt;, &lt;&amp;edma2 52 0 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpuart12: serial@42a80000 {</div><div class='add'>+				compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",</div><div class='add'>+					     "fsl,imx7ulp-lpuart";</div><div class='add'>+				reg = &lt;0x42a80000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_LPUART12&gt;;</div><div class='add'>+				clock-names = "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma4 49 0 FSL_EDMA_RX&gt;, &lt;&amp;edma4 48 0 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mu12: mailbox@42ac0000 {</div><div class='add'>+				compatible = "fsl,imx94-mu", "fsl,imx95-mu";</div><div class='add'>+				reg = &lt;0x42ac0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_BUSWAKEUP&gt;;</div><div class='add'>+				#mbox-cells = &lt;2&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mu13: mailbox@42ae0000 {</div><div class='add'>+				compatible = "fsl,imx94-mu", "fsl,imx95-mu";</div><div class='add'>+				reg = &lt;0x42ae0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_BUSWAKEUP&gt;;</div><div class='add'>+				#mbox-cells = &lt;2&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mu14: mailbox@42b00000 {</div><div class='add'>+				compatible = "fsl,imx94-mu", "fsl,imx95-mu";</div><div class='add'>+				reg = &lt;0x42b00000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_BUSWAKEUP&gt;;</div><div class='add'>+				#mbox-cells = &lt;2&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mu15: mailbox@42b20000 {</div><div class='add'>+				compatible = "fsl,imx94-mu", "fsl,imx95-mu";</div><div class='add'>+				reg = &lt;0x42b20000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_BUSWAKEUP&gt;;</div><div class='add'>+				#mbox-cells = &lt;2&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mu16: mailbox@42b40000 {</div><div class='add'>+				compatible = "fsl,imx94-mu", "fsl,imx95-mu";</div><div class='add'>+				reg = &lt;0x42b40000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_BUSWAKEUP&gt;;</div><div class='add'>+				#mbox-cells = &lt;2&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mu17: mailbox@42b60000 {</div><div class='add'>+				compatible = "fsl,imx94-mu", "fsl,imx95-mu";</div><div class='add'>+				reg = &lt;0x42b60000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_BUSWAKEUP&gt;;</div><div class='add'>+				#mbox-cells = &lt;2&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpio2: gpio@43810000 {</div><div class='add'>+			compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio";</div><div class='add'>+			reg = &lt;0x0 0x43810000 0x0 0x1000&gt;;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			interrupts = &lt;GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			gpio-ranges = &lt;&amp;scmi_iomuxc 0 4 32&gt;;</div><div class='add'>+			ngpios = &lt;32&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpio3: gpio@43820000 {</div><div class='add'>+			compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio";</div><div class='add'>+			reg = &lt;0x0 0x43820000 0x0 0x1000&gt;;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			interrupts = &lt;GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			gpio-ranges = &lt;&amp;scmi_iomuxc 0 36 26&gt;;</div><div class='add'>+			ngpios = &lt;26&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpio4: gpio@43840000 {</div><div class='add'>+			compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio";</div><div class='add'>+			reg = &lt;0x0 0x43840000 0x0 0x1000&gt;;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			interrupts = &lt;GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			gpio-ranges = &lt;&amp;scmi_iomuxc 0 62 4&gt;, &lt;&amp;scmi_iomuxc 4 0 4&gt;,</div><div class='add'>+				      &lt;&amp;scmi_iomuxc 8 140 12&gt;, &lt;&amp;scmi_iomuxc 20 164 12&gt;;</div><div class='add'>+			ngpios = &lt;32&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpio5: gpio@43850000 {</div><div class='add'>+			compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio";</div><div class='add'>+			reg = &lt;0x0 0x43850000 0x0 0x1000&gt;;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			interrupts = &lt;GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			gpio-ranges = &lt;&amp;scmi_iomuxc 0 108 32&gt;;</div><div class='add'>+			ngpios = &lt;32&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpio6: gpio@43860000 {</div><div class='add'>+			compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio";</div><div class='add'>+			reg = &lt;0x0 0x43860000 0x0 0x1000&gt;;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			interrupts = &lt;GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			gpio-ranges = &lt;&amp;scmi_iomuxc 0 66 32&gt;;</div><div class='add'>+			ngpios = &lt;32&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpio7: gpio@43870000 {</div><div class='add'>+			compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio";</div><div class='add'>+			reg = &lt;0x0 0x43870000 0x0 0x1000&gt;;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			interrupts = &lt;GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			gpio-ranges = &lt;&amp;scmi_iomuxc 0 98 10&gt;, &lt;&amp;scmi_iomuxc 16 152 12&gt;;</div><div class='add'>+			gpio-reserved-ranges = &lt;10 6&gt;;</div><div class='add'>+			ngpios = &lt;28&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aips1: bus@44000000 {</div><div class='add'>+			compatible = "fsl,aips-bus", "simple-bus";</div><div class='add'>+			reg = &lt;0x0 0x44000000 0x0 0x800000&gt;;</div><div class='add'>+			ranges = &lt;0x44000000 0x0 0x44000000 0x800000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			edma1: dma-controller@44000000 {</div><div class='add'>+				compatible = "fsl,imx94-edma3", "fsl,imx93-edma3";</div><div class='add'>+				reg = &lt;0x44000000 0x210000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_BUSAON&gt;;</div><div class='add'>+				clock-names = "dma";</div><div class='add'>+				#dma-cells = &lt;3&gt;;</div><div class='add'>+				dma-channels = &lt;32&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mu1: mailbox@44220000 {</div><div class='add'>+				compatible = "fsl,imx94-mu", "fsl,imx95-mu";</div><div class='add'>+				reg = &lt;0x44220000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_BUSAON&gt;;</div><div class='add'>+				#mbox-cells = &lt;2&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			system_counter: timer@44290000 {</div><div class='add'>+				compatible = "nxp,imx94-sysctr-timer", "nxp,imx95-sysctr-timer";</div><div class='add'>+				reg = &lt;0x44290000 0x30000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;osc_24m&gt;;</div><div class='add'>+				clock-names = "per";</div><div class='add'>+				nxp,no-divider;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tpm1: pwm@44310000 {</div><div class='add'>+				compatible = "fsl,imx94-pwm", "fsl,imx7ulp-pwm";</div><div class='add'>+				reg = &lt;0x44310000 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_BUSAON&gt;;</div><div class='add'>+				#pwm-cells = &lt;3&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tpm2: pwm@44320000 {</div><div class='add'>+				compatible = "fsl,imx94-pwm", "fsl,imx7ulp-pwm";</div><div class='add'>+				reg = &lt;0x44320000 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_TPM2&gt;;</div><div class='add'>+				#pwm-cells = &lt;3&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i3c1: i3c@44330000 {</div><div class='add'>+				compatible = "silvaco,i3c-master-v1";</div><div class='add'>+				reg = &lt;0x44330000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;3&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_BUSAON&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX94_CLK_I3C1SLOW&gt;,</div><div class='add'>+					 &lt;&amp;dummy&gt;;</div><div class='add'>+				clock-names = "pclk", "fast_clk", "slow_clk";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpi2c1: i2c@44340000 {</div><div class='add'>+				compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+				reg = &lt;0x44340000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_LPI2C1&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX94_CLK_BUSAON&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma1 12 0 0&gt;, &lt;&amp;edma1 13 0 FSL_EDMA_RX&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpi2c2: i2c@44350000 {</div><div class='add'>+				compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+				reg = &lt;0x44350000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_LPI2C2&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX94_CLK_BUSAON&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma1 14 0 0&gt;, &lt;&amp;edma1 15 0 FSL_EDMA_RX&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpspi1: spi@44360000 {</div><div class='add'>+				compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi";</div><div class='add'>+				reg = &lt;0x44360000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_LPSPI2&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX94_CLK_BUSAON&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma1 16 0 0&gt;, &lt;&amp;edma1 17 0 FSL_EDMA_RX&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpspi2: spi@44370000 {</div><div class='add'>+				compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi";</div><div class='add'>+				reg = &lt;0x44370000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_LPSPI2&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX94_CLK_BUSAON&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma1 18 0 0&gt;, &lt;&amp;edma1 19 0 FSL_EDMA_RX&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpuart1: serial@44380000 {</div><div class='add'>+				compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",</div><div class='add'>+					     "fsl,imx7ulp-lpuart";</div><div class='add'>+				reg = &lt;0x44380000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_LPUART1&gt;;</div><div class='add'>+				clock-names = "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma1 21 0 FSL_EDMA_RX&gt;, &lt;&amp;edma1 20 0 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpuart2: serial@44390000 {</div><div class='add'>+				compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",</div><div class='add'>+					     "fsl,imx7ulp-lpuart";</div><div class='add'>+				reg = &lt;0x44390000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_LPUART2&gt;;</div><div class='add'>+				clock-names = "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma1 23 0 FSL_EDMA_RX&gt;, &lt;&amp;edma1 22 0 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			flexcan1: can@443a0000 {</div><div class='add'>+				compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan";</div><div class='add'>+				reg = &lt;0x443a0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_BUSAON&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX94_CLK_CAN1&gt;;</div><div class='add'>+				clock-names = "ipg", "per";</div><div class='add'>+				assigned-clocks = &lt;&amp;scmi_clk IMX94_CLK_CAN1&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;80000000&gt;;</div><div class='add'>+				fsl,clk-source = /bits/ 8 &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sai1: sai@443b0000 {</div><div class='add'>+				compatible = "fsl,imx94-sai", "fsl,imx95-sai";</div><div class='add'>+				reg = &lt;0x443b0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_BUSAON&gt;, &lt;&amp;dummy&gt;,</div><div class='add'>+					&lt;&amp;scmi_clk IMX94_CLK_SAI1&gt;, &lt;&amp;dummy&gt;,</div><div class='add'>+					&lt;&amp;dummy&gt;, &lt;&amp;dummy&gt;;</div><div class='add'>+				clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";</div><div class='add'>+				dmas = &lt;&amp;edma1 25 0 FSL_EDMA_RX&gt;, &lt;&amp;edma1 24 0 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			micfil: micfil@44520000 {</div><div class='add'>+				compatible = "fsl,imx943-micfil";</div><div class='add'>+				reg = &lt;0x44520000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_BUSAON&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX94_CLK_PDM&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX94_CLK_AUDIOPLL1&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX94_CLK_AUDIOPLL2&gt;,</div><div class='add'>+					 &lt;&amp;dummy&gt;;</div><div class='add'>+				clock-names = "ipg_clk", "ipg_clk_app",</div><div class='add'>+					      "pll8k", "pll11k", "clkext3";</div><div class='add'>+				dmas = &lt;&amp;edma1 6 0 (FSL_EDMA_MULTI_FIFO | FSL_EDMA_RX)&gt;;</div><div class='add'>+				dma-names = "rx";</div><div class='add'>+				#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			adc1: adc@44530000 {</div><div class='add'>+				compatible = "nxp,imx94-adc", "nxp,imx93-adc";</div><div class='add'>+				reg = &lt;0x44530000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_ADC&gt;;</div><div class='add'>+				clock-names = "ipg";</div><div class='add'>+				#io-channel-cells = &lt;1&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mu2: mailbox@445b0000 {</div><div class='add'>+				compatible = "fsl,imx94-mu", "fsl,imx95-mu";</div><div class='add'>+				reg = &lt;0x445b0000 0x1000&gt;;</div><div class='add'>+				ranges;</div><div class='add'>+				interrupts = &lt;GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;1&gt;;</div><div class='add'>+				#mbox-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+				sram0: sram@445b1000 {</div><div class='add'>+					compatible = "mmio-sram";</div><div class='add'>+					reg = &lt;0x445b1000 0x400&gt;;</div><div class='add'>+					ranges = &lt;0x0 0x445b1000 0x400&gt;;</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					scmi_buf0: scmi-sram-section@0 {</div><div class='add'>+						compatible = "arm,scmi-shmem";</div><div class='add'>+						reg = &lt;0x0 0x80&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					scmi_buf1: scmi-sram-section@80 {</div><div class='add'>+						compatible = "arm,scmi-shmem";</div><div class='add'>+						reg = &lt;0x80 0x80&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mu3: mailbox@445d0000 {</div><div class='add'>+				compatible = "fsl,imx94-mu", "fsl,imx95-mu";</div><div class='add'>+				reg = &lt;0x445d0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#mbox-cells = &lt;2&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mu4: mailbox@445f0000 {</div><div class='add'>+				compatible = "fsl,imx94-mu", "fsl,imx95-mu";</div><div class='add'>+				reg = &lt;0x445f0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#mbox-cells = &lt;2&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mu6: mailbox@44630000 {</div><div class='add'>+				compatible = "fsl,imx94-mu", "fsl,imx95-mu";</div><div class='add'>+				reg = &lt;0x44630000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#mbox-cells = &lt;2&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			a55_irqsteer: interrupt-controller@446a0000 {</div><div class='add'>+				compatible = "fsl,imx94-irqsteer", "fsl,imx-irqsteer";</div><div class='add'>+				reg = &lt;0x446a0000 0x1000&gt;;</div><div class='add'>+				#interrupt-cells = &lt;1&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				interrupts = &lt;GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_BUSAON&gt;;</div><div class='add'>+				clock-names = "ipg";</div><div class='add'>+				fsl,channel = &lt;0&gt;;</div><div class='add'>+				fsl,num-irqs = &lt;960&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aips4: bus@49000000 {</div><div class='add'>+			compatible = "fsl,aips-bus", "simple-bus";</div><div class='add'>+			reg = &lt;0x0 0x49000000 0x0 0x800000&gt;;</div><div class='add'>+			ranges = &lt;0x49000000 0x0 0x49000000 0x800000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			wdog3: watchdog@49220000 {</div><div class='add'>+				compatible = "fsl,imx94-wdt", "fsl,imx93-wdt";</div><div class='add'>+				reg = &lt;0x49220000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_BUSWAKEUP&gt;;</div><div class='add'>+				timeout-sec = &lt;40&gt;;</div><div class='add'>+				fsl,ext-reset-output;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ddr-pmu@4e090dc0 {</div><div class='add'>+			compatible = "fsl,imx94-ddr-pmu", "fsl,imx93-ddr-pmu";</div><div class='add'>+			reg = &lt;0x0 0x4e090dc0 0x0 0x200&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx943-evk.dts b/arch/arm64/boot/dts/freescale/imx943-evk.dts<br/>new file mode 100644<br/>index 000000000000..c8c3eff9df1a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx943-evk.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx943-evk.dts</a></div><div class='hunk'>@@ -0,0 +1,627 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024-2025 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx943.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "fsl,imx943-evk", "fsl,imx94";</div><div class='add'>+	model = "NXP i.MX943 EVK board";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		i2c2 = &amp;lpi2c3;</div><div class='add'>+		i2c3 = &amp;lpi2c4;</div><div class='add'>+		i2c5 = &amp;lpi2c6;</div><div class='add'>+		mmc0 = &amp;usdhc1;</div><div class='add'>+		mmc1 = &amp;usdhc2;</div><div class='add'>+		serial0 = &amp;lpuart1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bt_sco_codec: bt-sco-codec {</div><div class='add'>+		compatible = "linux,bt-sco";</div><div class='add'>+		#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;lpuart1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dmic: dmic {</div><div class='add'>+		compatible = "dmic-codec";</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		off-on-delay-us = &lt;12000&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usdhc2_vmmc&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "VDD_SD2_3V3";</div><div class='add'>+		gpio = &lt;&amp;gpio4 27 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_audio_pwr: regulator-wm8962-pwr {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "audio-pwr";</div><div class='add'>+		gpio = &lt;&amp;pcal6416_i2c3_u171 12 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		ranges;</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		linux,cma {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			alloc-ranges = &lt;0 0x80000000 0 0x7f000000&gt;;</div><div class='add'>+			reusable;</div><div class='add'>+			size = &lt;0 0x10000000&gt;;</div><div class='add'>+			linux,cma-default;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-bt-sco {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,bitclock-inversion;</div><div class='add'>+		simple-audio-card,bitclock-master = &lt;&amp;btcpu&gt;;</div><div class='add'>+		simple-audio-card,format = "dsp_a";</div><div class='add'>+		simple-audio-card,frame-master = &lt;&amp;btcpu&gt;;</div><div class='add'>+		simple-audio-card,name = "bt-sco-audio";</div><div class='add'>+</div><div class='add'>+		simple-audio-card,codec {</div><div class='add'>+			sound-dai = &lt;&amp;bt_sco_codec 1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		btcpu: simple-audio-card,cpu {</div><div class='add'>+			dai-tdm-slot-num = &lt;2&gt;;</div><div class='add'>+			dai-tdm-slot-width = &lt;16&gt;;</div><div class='add'>+			sound-dai = &lt;&amp;sai3&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-micfil {</div><div class='add'>+		compatible = "fsl,imx-audio-card";</div><div class='add'>+		model = "micfil-audio";</div><div class='add'>+</div><div class='add'>+		pri-dai-link {</div><div class='add'>+			format = "i2s";</div><div class='add'>+			link-name = "micfil hifi";</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;dmic&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cpu {</div><div class='add'>+				sound-dai = &lt;&amp;micfil&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-wm8962 {</div><div class='add'>+		compatible = "fsl,imx-audio-wm8962";</div><div class='add'>+		audio-codec = &lt;&amp;wm8962&gt;;</div><div class='add'>+		audio-cpu = &lt;&amp;sai1&gt;;</div><div class='add'>+		audio-routing = "Headphone Jack", "HPOUTL",</div><div class='add'>+			"Headphone Jack", "HPOUTR",</div><div class='add'>+			"Ext Spk", "SPKOUTL",</div><div class='add'>+			"Ext Spk", "SPKOUTR",</div><div class='add'>+			"AMIC", "MICBIAS",</div><div class='add'>+			"IN3R", "AMIC",</div><div class='add'>+			"IN1R", "AMIC";</div><div class='add'>+		hp-det-gpio = &lt;&amp;pcal6416_i2c3_u48 14 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		model = "wm8962-audio";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@80000000 {</div><div class='add'>+		reg = &lt;0x0 0x80000000 0x0 0x80000000&gt;;</div><div class='add'>+		device_type = "memory";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c3 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c3&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pca9670_i2c3: gpio@23 {</div><div class='add'>+		compatible = "nxp,pca9670";</div><div class='add'>+		reg = &lt;0x23&gt;;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pca9548_i2c3: i2c-mux@77 {</div><div class='add'>+		compatible = "nxp,pca9548";</div><div class='add'>+		reg = &lt;0x77&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		i2c@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@2 {</div><div class='add'>+			reg = &lt;2&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@3 {</div><div class='add'>+			reg = &lt;3&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@4 {</div><div class='add'>+			reg = &lt;4&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			wm8962: codec@1a {</div><div class='add'>+				compatible = "wlf,wm8962";</div><div class='add'>+				reg = &lt;0x1a&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX94_CLK_SAI1&gt;;</div><div class='add'>+				AVDD-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+				CPVDD-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+				DBVDD-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+				DCVDD-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+				gpio-cfg = &lt;</div><div class='add'>+					0x0000 /* 0:Default */</div><div class='add'>+					0x0000 /* 1:Default */</div><div class='add'>+					0x0000 /* 2:FN_DMICCLK */</div><div class='add'>+					0x0000 /* 3:Default */</div><div class='add'>+					0x0000 /* 4:FN_DMICCDAT */</div><div class='add'>+					0x0000 /* 5:Default */</div><div class='add'>+				&gt;;</div><div class='add'>+				MICVDD-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+				PLLVDD-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+				SPKVDD1-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+				SPKVDD2-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@5 {</div><div class='add'>+			reg = &lt;5&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			pcal6416_i2c3_u46: gpio@20 {</div><div class='add'>+				compatible = "nxp,pcal6416";</div><div class='add'>+				reg = &lt;0x20&gt;;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+</div><div class='add'>+				sd-card-on-hog {</div><div class='add'>+					gpios = &lt;13 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+					gpio-hog;</div><div class='add'>+					output-high;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pcal6416_i2c3_u171: gpio@21 {</div><div class='add'>+				compatible = "nxp,pcal6416";</div><div class='add'>+				reg = &lt;0x21&gt;;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+</div><div class='add'>+				audio-pwren-hog {</div><div class='add'>+					gpios = &lt;12 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+					gpio-hog;</div><div class='add'>+					output-high;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				mqs-mic-sel-hog {</div><div class='add'>+					gpios = &lt;11 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+					gpio-hog;</div><div class='add'>+					output-low;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@6 {</div><div class='add'>+			reg = &lt;6&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			pcal6416_i2c3_u48: gpio@20 {</div><div class='add'>+				compatible = "nxp,pcal6416";</div><div class='add'>+				reg = &lt;0x20&gt;;</div><div class='add'>+				#interrupt-cells = &lt;2&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+				interrupts = &lt;13 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+				pinctrl-0 = &lt;&amp;pinctrl_ioexpander_int&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@7 {</div><div class='add'>+			reg = &lt;7&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			pcal6408_i2c3_u172: gpio@20 {</div><div class='add'>+				compatible = "nxp,pcal6408";</div><div class='add'>+				reg = &lt;0x20&gt;;</div><div class='add'>+				#interrupt-cells = &lt;2&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+				/* shared int pin with u48 */</div><div class='add'>+				interrupts = &lt;13 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c4 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c4&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c6 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c6&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pca9544_i2c6: i2c-mux@77 {</div><div class='add'>+		compatible = "nxp,pca9544";</div><div class='add'>+		reg = &lt;0x77&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		i2c@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			pcal6416_i2c6_u50: gpio@21 {</div><div class='add'>+				compatible = "nxp,pcal6416";</div><div class='add'>+				reg = &lt;0x21&gt;;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@2 {</div><div class='add'>+			reg = &lt;2&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			pcal6408_i2c6_u170: gpio@20 {</div><div class='add'>+				compatible = "nxp,pcal6408";</div><div class='add'>+				reg = &lt;0x20&gt;;</div><div class='add'>+				#interrupt-cells = &lt;2&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+				interrupts = &lt;3 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+				pinctrl-0 = &lt;&amp;pinctrl_ioexpander_int2&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@3 {</div><div class='add'>+			reg = &lt;3&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			pcal6416_i2c6_u44: gpio@20 {</div><div class='add'>+				compatible = "nxp,pcal6416";</div><div class='add'>+				reg = &lt;0x20&gt;;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+</div><div class='add'>+				/* pdm selection */</div><div class='add'>+				can-pdm-sel-hog {</div><div class='add'>+					gpios = &lt;12 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+					gpio-hog;</div><div class='add'>+					output-low;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				sai3-sel-hog {</div><div class='add'>+					gpios = &lt;11 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+					gpio-hog;</div><div class='add'>+					output-high;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				/* eMMC IOMUX selection */</div><div class='add'>+				sd1-sel-hog {</div><div class='add'>+					gpios = &lt;0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+					gpio-hog;</div><div class='add'>+					output-high;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				/* SD card IOMUX selection */</div><div class='add'>+				sd2-sel-hog {</div><div class='add'>+					gpios = &lt;1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+					gpio-hog;</div><div class='add'>+					output-high;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;micfil {</div><div class='add'>+	assigned-clocks = &lt;&amp;scmi_clk IMX94_CLK_AUDIOPLL1_VCO&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX94_CLK_AUDIOPLL2_VCO&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX94_CLK_AUDIOPLL1&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX94_CLK_AUDIOPLL2&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX94_CLK_PDM&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;, &lt;0&gt;,</div><div class='add'>+				 &lt;&amp;scmi_clk IMX94_CLK_AUDIOPLL1&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;3932160000&gt;,</div><div class='add'>+			       &lt;3612672000&gt;, &lt;393216000&gt;,</div><div class='add'>+			       &lt;361267200&gt;, &lt;49152000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pdm&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai1 {</div><div class='add'>+	assigned-clocks = &lt;&amp;scmi_clk IMX94_CLK_AUDIOPLL1_VCO&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX94_CLK_AUDIOPLL2_VCO&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX94_CLK_AUDIOPLL1&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX94_CLK_AUDIOPLL2&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX94_CLK_SAI1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;, &lt;0&gt;,</div><div class='add'>+				 &lt;&amp;scmi_clk IMX94_CLK_AUDIOPLL1&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;3932160000&gt;,</div><div class='add'>+			       &lt;3612672000&gt;, &lt;393216000&gt;,</div><div class='add'>+			       &lt;361267200&gt;, &lt;12288000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai1&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	fsl,sai-mclk-direction-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai3 {</div><div class='add'>+	assigned-clocks = &lt;&amp;scmi_clk IMX94_CLK_AUDIOPLL1_VCO&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX94_CLK_AUDIOPLL2_VCO&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX94_CLK_AUDIOPLL1&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX94_CLK_AUDIOPLL2&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX94_CLK_SAI3&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;, &lt;0&gt;,</div><div class='add'>+				 &lt;&amp;scmi_clk IMX94_CLK_AUDIOPLL1&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;3932160000&gt;,</div><div class='add'>+			       &lt;3612672000&gt;, &lt;393216000&gt;,</div><div class='add'>+			       &lt;361267200&gt;, &lt;12288000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai3&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	fsl,sai-mclk-direction-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;scmi_iomuxc {</div><div class='add'>+</div><div class='add'>+	pinctrl_ioexpander_int2: ioexpanderint2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX94_PAD_CCM_CLKO4__GPIO4_IO3		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ioexpander_int: ioexpanderintgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX94_PAD_GPIO_IO45__GPIO3_IO13		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c3: lpi2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX94_PAD_GPIO_IO16__LPI2C3_SDA		0x40000b9e</div><div class='add'>+			IMX94_PAD_GPIO_IO17__LPI2C3_SCL		0x40000b9e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c4: lpi2c4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX94_PAD_GPIO_IO18__LPI2C4_SDA		0x40000b9e</div><div class='add'>+			IMX94_PAD_GPIO_IO19__LPI2C4_SCL		0x40000b9e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c6: lpi2c6grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX94_PAD_GPIO_IO29__LPI2C6_SDA		0x40000b9e</div><div class='add'>+			IMX94_PAD_GPIO_IO28__LPI2C6_SCL		0x40000b9e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pdm: pdmgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX94_PAD_PDM_CLK__PDM_CLK			0x31e</div><div class='add'>+			IMX94_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM0	0x31e</div><div class='add'>+			IMX94_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM1	0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai1: sai1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX94_PAD_SAI1_TXFS__SAI1_TX_SYNC	0x31e</div><div class='add'>+			IMX94_PAD_SAI1_TXC__SAI1_TX_BCLK	0x31e</div><div class='add'>+			IMX94_PAD_SAI1_TXD0__SAI1_TX_DATA0	0x31e</div><div class='add'>+			IMX94_PAD_SAI1_RXD0__SAI1_RX_DATA0	0x31e</div><div class='add'>+			IMX94_PAD_I2C2_SDA__SAI1_MCLK		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai3: sai3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX94_PAD_GPIO_IO42__SAI3_TX_BCLK	0x31e</div><div class='add'>+			IMX94_PAD_GPIO_IO56__SAI3_TX_SYNC	0x31e</div><div class='add'>+			IMX94_PAD_GPIO_IO46__SAI3_RX_DATA0	0x31e</div><div class='add'>+			IMX94_PAD_GPIO_IO47__SAI3_TX_DATA0	0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX94_PAD_UART1_TXD__LPUART1_TX		0x31e</div><div class='add'>+			IMX94_PAD_UART1_RXD__LPUART1_RX		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX94_PAD_SD1_CLK__USDHC1_CLK		0x158e</div><div class='add'>+			IMX94_PAD_SD1_CMD__USDHC1_CMD		0x138e</div><div class='add'>+			IMX94_PAD_SD1_DATA0__USDHC1_DATA0	0x138e</div><div class='add'>+			IMX94_PAD_SD1_DATA1__USDHC1_DATA1	0x138e</div><div class='add'>+			IMX94_PAD_SD1_DATA2__USDHC1_DATA2	0x138e</div><div class='add'>+			IMX94_PAD_SD1_DATA3__USDHC1_DATA3	0x138e</div><div class='add'>+			IMX94_PAD_SD1_DATA4__USDHC1_DATA4	0x138e</div><div class='add'>+			IMX94_PAD_SD1_DATA5__USDHC1_DATA5	0x138e</div><div class='add'>+			IMX94_PAD_SD1_DATA6__USDHC1_DATA6	0x138e</div><div class='add'>+			IMX94_PAD_SD1_DATA7__USDHC1_DATA7	0x138e</div><div class='add'>+			IMX94_PAD_SD1_STROBE__USDHC1_STROBE	0x158e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX94_PAD_SD1_CLK__USDHC1_CLK		0x15fe</div><div class='add'>+			IMX94_PAD_SD1_CMD__USDHC1_CMD		0x13fe</div><div class='add'>+			IMX94_PAD_SD1_DATA0__USDHC1_DATA0	0x13fe</div><div class='add'>+			IMX94_PAD_SD1_DATA1__USDHC1_DATA1	0x13fe</div><div class='add'>+			IMX94_PAD_SD1_DATA2__USDHC1_DATA2	0x13fe</div><div class='add'>+			IMX94_PAD_SD1_DATA3__USDHC1_DATA3	0x13fe</div><div class='add'>+			IMX94_PAD_SD1_DATA4__USDHC1_DATA4	0x13fe</div><div class='add'>+			IMX94_PAD_SD1_DATA5__USDHC1_DATA5	0x13fe</div><div class='add'>+			IMX94_PAD_SD1_DATA6__USDHC1_DATA6	0x13fe</div><div class='add'>+			IMX94_PAD_SD1_DATA7__USDHC1_DATA7	0x13fe</div><div class='add'>+			IMX94_PAD_SD1_STROBE__USDHC1_STROBE	0x15fe</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX94_PAD_SD1_CLK__USDHC1_CLK		0x158e</div><div class='add'>+			IMX94_PAD_SD1_CMD__USDHC1_CMD		0x138e</div><div class='add'>+			IMX94_PAD_SD1_DATA0__USDHC1_DATA0	0x138e</div><div class='add'>+			IMX94_PAD_SD1_DATA1__USDHC1_DATA1	0x138e</div><div class='add'>+			IMX94_PAD_SD1_DATA2__USDHC1_DATA2	0x138e</div><div class='add'>+			IMX94_PAD_SD1_DATA3__USDHC1_DATA3	0x138e</div><div class='add'>+			IMX94_PAD_SD1_DATA4__USDHC1_DATA4	0x138e</div><div class='add'>+			IMX94_PAD_SD1_DATA5__USDHC1_DATA5	0x138e</div><div class='add'>+			IMX94_PAD_SD1_DATA6__USDHC1_DATA6	0x138e</div><div class='add'>+			IMX94_PAD_SD1_DATA7__USDHC1_DATA7	0x138e</div><div class='add'>+			IMX94_PAD_SD1_STROBE__USDHC1_STROBE	0x158e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX94_PAD_SD2_CLK__USDHC2_CLK		0x158e</div><div class='add'>+			IMX94_PAD_SD2_CMD__USDHC2_CMD		0x138e</div><div class='add'>+			IMX94_PAD_SD2_DATA0__USDHC2_DATA0	0x138e</div><div class='add'>+			IMX94_PAD_SD2_DATA1__USDHC2_DATA1	0x138e</div><div class='add'>+			IMX94_PAD_SD2_DATA2__USDHC2_DATA2	0x138e</div><div class='add'>+			IMX94_PAD_SD2_DATA3__USDHC2_DATA3	0x138e</div><div class='add'>+			IMX94_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX94_PAD_SD2_CLK__USDHC2_CLK		0x15fe</div><div class='add'>+			IMX94_PAD_SD2_CMD__USDHC2_CMD		0x13fe</div><div class='add'>+			IMX94_PAD_SD2_DATA0__USDHC2_DATA0	0x13fe</div><div class='add'>+			IMX94_PAD_SD2_DATA1__USDHC2_DATA1	0x13fe</div><div class='add'>+			IMX94_PAD_SD2_DATA2__USDHC2_DATA2	0x13fe</div><div class='add'>+			IMX94_PAD_SD2_DATA3__USDHC2_DATA3	0x13fe</div><div class='add'>+			IMX94_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX94_PAD_SD2_CD_B__GPIO4_IO20		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX94_PAD_SD2_CLK__USDHC2_CLK		0x158e</div><div class='add'>+			IMX94_PAD_SD2_CMD__USDHC2_CMD		0x138e</div><div class='add'>+			IMX94_PAD_SD2_DATA0__USDHC2_DATA0	0x138e</div><div class='add'>+			IMX94_PAD_SD2_DATA1__USDHC2_DATA1	0x138e</div><div class='add'>+			IMX94_PAD_SD2_DATA2__USDHC2_DATA2	0x138e</div><div class='add'>+			IMX94_PAD_SD2_DATA3__USDHC2_DATA3	0x138e</div><div class='add'>+			IMX94_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usdhc2_vmmc: usdhc2regvmmcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX94_PAD_SD2_RESET_B__GPIO4_IO27	0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1_200mhz&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	no-sdio;</div><div class='add'>+	no-sd;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	no-mmc;</div><div class='add'>+	no-sdio;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio4 20 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog3 {</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx943.dtsi b/arch/arm64/boot/dts/freescale/imx943.dtsi<br/>new file mode 100644<br/>index 000000000000..45b8da758e87<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx943.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx943.dtsi</a></div><div class='hunk'>@@ -0,0 +1,148 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2025 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "imx94.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		idle-states {</div><div class='add'>+			entry-method = "psci";</div><div class='add'>+</div><div class='add'>+			cpu_pd_wait: cpu-pd-wait {</div><div class='add'>+				compatible = "arm,idle-state";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x0010033&gt;;</div><div class='add'>+				local-timer-stop;</div><div class='add'>+				entry-latency-us = &lt;1000&gt;;</div><div class='add'>+				exit-latency-us = &lt;700&gt;;</div><div class='add'>+				min-residency-us = &lt;2700&gt;;</div><div class='add'>+				wakeup-latency-us = &lt;1500&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_pd_wait&gt;;</div><div class='add'>+			power-domains = &lt;&amp;scmi_perf IMX94_PERF_A55&gt;;</div><div class='add'>+			power-domain-names = "perf";</div><div class='add'>+			i-cache-size = &lt;32768&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;128&gt;;</div><div class='add'>+			d-cache-size = &lt;32768&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_l0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@100 {</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x100&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_pd_wait&gt;;</div><div class='add'>+			power-domains = &lt;&amp;scmi_perf IMX94_PERF_A55&gt;;</div><div class='add'>+			power-domain-names = "perf";</div><div class='add'>+			i-cache-size = &lt;32768&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;128&gt;;</div><div class='add'>+			d-cache-size = &lt;32768&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_l1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@200 {</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x200&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_pd_wait&gt;;</div><div class='add'>+			power-domains = &lt;&amp;scmi_perf IMX94_PERF_A55&gt;;</div><div class='add'>+			power-domain-names = "perf";</div><div class='add'>+			i-cache-size = &lt;32768&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;128&gt;;</div><div class='add'>+			d-cache-size = &lt;32768&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@300 {</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x300&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_pd_wait&gt;;</div><div class='add'>+			power-domains = &lt;&amp;scmi_perf IMX94_PERF_A55&gt;;</div><div class='add'>+			power-domain-names = "perf";</div><div class='add'>+			i-cache-size = &lt;32768&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;128&gt;;</div><div class='add'>+			d-cache-size = &lt;32768&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_l3&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_cache_l0: l2-cache-l0 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-size = &lt;65536&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;256&gt;;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			next-level-cache = &lt;&amp;l3_cache&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_cache_l1: l2-cache-l1 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-size = &lt;65536&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;256&gt;;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			next-level-cache = &lt;&amp;l3_cache&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_cache_l2: l2-cache-l2 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-size = &lt;65536&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;256&gt;;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			next-level-cache = &lt;&amp;l3_cache&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_cache_l3: l2-cache-l3 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-size = &lt;65536&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;256&gt;;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			next-level-cache = &lt;&amp;l3_cache&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l3_cache: l3-cache {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-size = &lt;1048576&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;1024&gt;;</div><div class='add'>+			cache-level = &lt;3&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts<br/>new file mode 100644<br/>index 000000000000..c1e245ecea9c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts</a></div><div class='hunk'>@@ -0,0 +1,1185 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2025 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/i3c/i3c.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/phy/phy-imx8-pcie.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pwm/pwm.h&gt;</div><div class='add'>+#include &lt;dt-bindings/usb/pd.h&gt;</div><div class='add'>+#include "imx95.dtsi"</div><div class='add'>+</div><div class='add'>+#define FALLING_EDGE		BIT(0)</div><div class='add'>+#define RISING_EDGE		BIT(1)</div><div class='add'>+</div><div class='add'>+#define BRD_SM_CTRL_SD3_WAKE		0x8000</div><div class='add'>+#define BRD_SM_CTRL_PCIE1_WAKE		0x8001</div><div class='add'>+#define BRD_SM_CTRL_BT_WAKE		0x8002</div><div class='add'>+#define BRD_SM_CTRL_PCIE2_WAKE		0x8003</div><div class='add'>+#define BRD_SM_CTRL_BUTTON		0x8004</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "fsl,imx95-15x15-evk", "fsl,imx95";</div><div class='add'>+	model = "NXP i.MX95 15X15 board";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;enetc_port0;</div><div class='add'>+		ethernet1 = &amp;enetc_port1;</div><div class='add'>+		gpio0 = &amp;gpio1;</div><div class='add'>+		gpio1 = &amp;gpio2;</div><div class='add'>+		gpio2 = &amp;gpio3;</div><div class='add'>+		gpio3 = &amp;gpio4;</div><div class='add'>+		gpio4 = &amp;gpio5;</div><div class='add'>+		i2c0 = &amp;lpi2c1;</div><div class='add'>+		i2c1 = &amp;lpi2c2;</div><div class='add'>+		i2c2 = &amp;lpi2c3;</div><div class='add'>+		i2c3 = &amp;lpi2c4;</div><div class='add'>+		i2c4 = &amp;lpi2c5;</div><div class='add'>+		i2c5 = &amp;lpi2c6;</div><div class='add'>+		i2c6 = &amp;lpi2c7;</div><div class='add'>+		i2c7 = &amp;lpi2c8;</div><div class='add'>+		mmc0 = &amp;usdhc1;</div><div class='add'>+		mmc1 = &amp;usdhc2;</div><div class='add'>+		mmc2 = &amp;usdhc3;</div><div class='add'>+		serial0 = &amp;lpuart1;</div><div class='add'>+		serial4 = &amp;lpuart5;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bt_sco_codec: bt-sco-codec {</div><div class='add'>+		compatible = "linux,bt-sco";</div><div class='add'>+		#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		stdout-path = &amp;lpuart1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fan0: pwm-fan {</div><div class='add'>+		compatible = "pwm-fan";</div><div class='add'>+		fan-supply = &lt;&amp;reg_vcc_12v&gt;;</div><div class='add'>+		#cooling-cells = &lt;2&gt;;</div><div class='add'>+		cooling-levels = &lt;64 128 192 255&gt;;</div><div class='add'>+		pwms = &lt;&amp;tpm6 0 4000000 PWM_POLARITY_INVERTED&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_1p8v: regulator-1p8v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-name = "+V1.8_SW";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3p3v: regulator-3p3v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "+V3.3_SW";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vref_1v8: regulator-adc-vref {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-name = "vref_1v8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_audio_pwr: regulator-audio-pwr {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "audio-pwr";</div><div class='add'>+		gpio = &lt;&amp;pcal6524 13 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_audio_switch1: regulator-audio-switch1 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "audio-switch1";</div><div class='add'>+		gpio = &lt;&amp;pcal6524 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_can2_stby: regulator-can2-stby {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "can2-stby";</div><div class='add'>+		gpio = &lt;&amp;pcal6524 14 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_m2_pwr: regulator-m2-pwr {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "M.2-power";</div><div class='add'>+		gpio = &lt;&amp;pcal6524 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		off-on-delay-us = &lt;12000&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usdhc2_vmmc&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "VDD_SD2_3V3";</div><div class='add'>+		gpio = &lt;&amp;gpio3 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc3_vmmc: regulator-usdhc3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "WLAN_EN";</div><div class='add'>+		vin-supply = &lt;&amp;reg_m2_pwr&gt;;</div><div class='add'>+		gpio = &lt;&amp;pcal6524 11 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		/*</div><div class='add'>+		 * IW612 wifi chip needs more delay than other wifi chips to complete</div><div class='add'>+		 * the host interface initialization after power up, otherwise the</div><div class='add'>+		 * internal state of IW612 may be unstable, resulting in the failure of</div><div class='add'>+		 * the SDIO3.0 switch voltage.</div><div class='add'>+		 */</div><div class='add'>+		startup-delay-us = &lt;20000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb_vbus: regulator-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "USB_VBUS";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;pcal6524 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc_12v: regulator-vcc-12v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-name = "VCC_12V";</div><div class='add'>+		gpio = &lt;&amp;pcal6524 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		ranges;</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		linux_cma: linux,cma {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			alloc-ranges = &lt;0 0x80000000 0 0x7F000000&gt;;</div><div class='add'>+			reusable;</div><div class='add'>+			size = &lt;0 0x3c000000&gt;;</div><div class='add'>+			linux,cma-default;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev0vring0: vdev0vring0@88000000 {</div><div class='add'>+			reg = &lt;0 0x88000000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev0vring1: vdev0vring1@88008000 {</div><div class='add'>+			reg = &lt;0 0x88008000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev1vring0: vdev1vring0@88010000 {</div><div class='add'>+			reg = &lt;0 0x88010000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev1vring1: vdev1vring1@88018000 {</div><div class='add'>+			reg = &lt;0 0x88018000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdevbuffer: vdevbuffer@88020000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x88020000 0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rsc_table: rsc-table@88220000 {</div><div class='add'>+			reg = &lt;0 0x88220000 0 0x1000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vpu_boot: vpu_boot@a0000000 {</div><div class='add'>+			reg = &lt;0 0xa0000000 0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-bt-sco {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,bitclock-inversion;</div><div class='add'>+		simple-audio-card,bitclock-master = &lt;&amp;btcpu&gt;;</div><div class='add'>+		simple-audio-card,format = "dsp_a";</div><div class='add'>+		simple-audio-card,frame-master = &lt;&amp;btcpu&gt;;</div><div class='add'>+		simple-audio-card,name = "bt-sco-audio";</div><div class='add'>+</div><div class='add'>+		simple-audio-card,codec {</div><div class='add'>+			sound-dai = &lt;&amp;bt_sco_codec 1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		btcpu: simple-audio-card,cpu {</div><div class='add'>+			dai-tdm-slot-num = &lt;2&gt;;</div><div class='add'>+			dai-tdm-slot-width = &lt;16&gt;;</div><div class='add'>+			sound-dai = &lt;&amp;sai1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-micfil {</div><div class='add'>+		compatible = "fsl,imx-audio-card";</div><div class='add'>+		model = "micfil-audio";</div><div class='add'>+</div><div class='add'>+		pri-dai-link {</div><div class='add'>+			format = "i2s";</div><div class='add'>+			link-name = "micfil hifi";</div><div class='add'>+</div><div class='add'>+			cpu {</div><div class='add'>+				sound-dai = &lt;&amp;micfil&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-wm8962 {</div><div class='add'>+		compatible = "fsl,imx-audio-wm8962";</div><div class='add'>+		audio-codec = &lt;&amp;wm8962&gt;;</div><div class='add'>+		audio-cpu = &lt;&amp;sai3&gt;;</div><div class='add'>+		audio-routing = "Headphone Jack", "HPOUTL", "Headphone Jack", "HPOUTR",</div><div class='add'>+				"Ext Spk", "SPKOUTL", "Ext Spk", "SPKOUTR", "AMIC", "MICBIAS",</div><div class='add'>+				"IN3R", "AMIC", "IN1R", "AMIC";</div><div class='add'>+		hp-det-gpio = &lt;&amp;gpio2 21 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		model = "wm8962-audio";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_hp&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-xcvr {</div><div class='add'>+		compatible = "fsl,imx-audio-card";</div><div class='add'>+		model = "imx-audio-xcvr";</div><div class='add'>+</div><div class='add'>+		pri-dai-link {</div><div class='add'>+			link-name = "XCVR PCM";</div><div class='add'>+</div><div class='add'>+			cpu {</div><div class='add'>+				sound-dai = &lt;&amp;xcvr&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usdhc3_pwrseq: usdhc3-pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-simple";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usdhc3_pwrseq&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		reset-gpios = &lt;&amp;gpio5 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@80000000 {</div><div class='add'>+		reg = &lt;0x0 0x80000000 0 0x80000000&gt;;</div><div class='add'>+		device_type = "memory";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;adc1 {</div><div class='add'>+	vref-supply = &lt;&amp;reg_vref_1v8&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;enetc_port0 {</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_enetc0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;enetc_port1 {</div><div class='add'>+	phy-handle = &lt;&amp;ethphy1&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_enetc1&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan2 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan2&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	xceiver-supply = &lt;&amp;reg_can2_stby&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i3c2 {</div><div class='add'>+	i2c-scl-hz = &lt;400000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i3c2&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pca9570: gpio@24 {</div><div class='add'>+		compatible = "nxp,pca9570";</div><div class='add'>+		reg = &lt;0x24 0 (I2C_FILTER)&gt;;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		gpio-line-names = "OUT1", "OUT2", "OUT3", "OUT4";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c2&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	wm8962: codec@1a {</div><div class='add'>+		compatible = "wlf,wm8962";</div><div class='add'>+		reg = &lt;0x1a&gt;;</div><div class='add'>+		clocks = &lt;&amp;scmi_clk IMX95_CLK_SAI3&gt;;</div><div class='add'>+		AVDD-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+		CPVDD-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+		DBVDD-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+		DCVDD-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+		gpio-cfg = &lt;</div><div class='add'>+			0x0000</div><div class='add'>+			0x0000</div><div class='add'>+			0x0000</div><div class='add'>+			0x0000</div><div class='add'>+			0x0000</div><div class='add'>+			0x0000</div><div class='add'>+		&gt;;</div><div class='add'>+		MICVDD-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+		PLLVDD-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+		SPKVDD1-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+		SPKVDD2-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcal6524: gpio@22 {</div><div class='add'>+		compatible = "nxp,pcal6524";</div><div class='add'>+		reg = &lt;0x22&gt;;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio5&gt;;</div><div class='add'>+		interrupts = &lt;14 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pcal6524&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c3 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c3&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ptn5110: tcpc@50 {</div><div class='add'>+		compatible = "nxp,ptn5110", "tcpci";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio5&gt;;</div><div class='add'>+		interrupts = &lt;11 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_ptn5110&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		typec_con: connector {</div><div class='add'>+			compatible = "usb-c-connector";</div><div class='add'>+			data-role = "dual";</div><div class='add'>+			label = "USB-C";</div><div class='add'>+			op-sink-microwatt = &lt;15000000&gt;;</div><div class='add'>+			power-role = "dual";</div><div class='add'>+			self-powered;</div><div class='add'>+			sink-pdos = &lt;PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)</div><div class='add'>+				     PDO_VAR(5000, 20000, 3000)&gt;;</div><div class='add'>+			source-pdos = &lt;PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)&gt;;</div><div class='add'>+			try-power-role = "sink";</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					typec_con_hs: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;usb3_data_hs&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					typec_con_ss: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;usb3_data_ss&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pca9632: led-controller@62 {</div><div class='add'>+		compatible = "nxp,pca9632";</div><div class='add'>+		reg = &lt;0x62&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		nxp,inverted-out;</div><div class='add'>+</div><div class='add'>+		led_backlight0: led@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			color = &lt;LED_COLOR_ID_WHITE&gt;;</div><div class='add'>+			function = LED_FUNCTION_BACKLIGHT;</div><div class='add'>+			function-enumerator = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led_backlight1: led@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			color = &lt;LED_COLOR_ID_WHITE&gt;;</div><div class='add'>+			function = LED_FUNCTION_BACKLIGHT;</div><div class='add'>+			function-enumerator = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c4 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c4&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c6 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c6&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart5 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart5&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "nxp,88w8987-bt";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;micfil {</div><div class='add'>+	assigned-clocks = &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL1_VCO&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL2_VCO&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL1&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL2&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_PDM&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;, &lt;0&gt;, &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL1&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;3932160000&gt;, &lt;3612672000&gt;, &lt;393216000&gt;, &lt;361267200&gt;, &lt;49152000&gt;;</div><div class='add'>+	#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pdm&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mu7 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;netc_blk_ctrl {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;netc_bus0 {</div><div class='add'>+	msi-map = &lt;0x00 &amp;its 0x60 0x1&gt;,	//ENETC0 PF</div><div class='add'>+		  &lt;0x10 &amp;its 0x61 0x1&gt;, //ENETC0 VF0</div><div class='add'>+		  &lt;0x20 &amp;its 0x62 0x1&gt;, //ENETC0 VF1</div><div class='add'>+		  &lt;0x40 &amp;its 0x63 0x1&gt;, //ENETC1 PF</div><div class='add'>+		  &lt;0x50 &amp;its 0x65 0x1&gt;, //ENETC1 VF0</div><div class='add'>+		  &lt;0x60 &amp;its 0x66 0x1&gt;, //ENETC1 VF1</div><div class='add'>+		  &lt;0x80 &amp;its 0x64 0x1&gt;, //ENETC2 PF</div><div class='add'>+		  &lt;0xc0 &amp;its 0x67 0x1&gt;;</div><div class='add'>+	iommu-map = &lt;0x0 &amp;smmu 0x20 0x1&gt;,</div><div class='add'>+		    &lt;0x10 &amp;smmu 0x21 0x1&gt;,</div><div class='add'>+		    &lt;0x20 &amp;smmu 0x22 0x1&gt;,</div><div class='add'>+		    &lt;0x40 &amp;smmu 0x23 0x1&gt;,</div><div class='add'>+		    &lt;0x50 &amp;smmu 0x25 0x1&gt;,</div><div class='add'>+		    &lt;0x60 &amp;smmu 0x26 0x1&gt;,</div><div class='add'>+		    &lt;0x80 &amp;smmu 0x24 0x1&gt;,</div><div class='add'>+		    &lt;0xc0 &amp;smmu 0x27 0x1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;netc_emdio {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_emdio&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ethphy0: ethernet-phy@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		reset-assert-us = &lt;10000&gt;;</div><div class='add'>+		reset-deassert-us = &lt;80000&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pcal6524 4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		realtek,clkout-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ethphy1: ethernet-phy@2 {</div><div class='add'>+		reg = &lt;2&gt;;</div><div class='add'>+		reset-assert-us = &lt;10000&gt;;</div><div class='add'>+		reset-deassert-us = &lt;80000&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pcal6524 5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		realtek,clkout-disable;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;netc_timer {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;netcmix_blk_ctrl {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	reset-gpio = &lt;&amp;gpio5 13 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vpcie-supply = &lt;&amp;reg_m2_pwr&gt;;</div><div class='add'>+	vpcie3v3aux-supply = &lt;&amp;reg_m2_pwr&gt;;</div><div class='add'>+	supports-clkreq;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0_ep {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	vpcie-supply = &lt;&amp;reg_m2_pwr&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai1 {</div><div class='add'>+	assigned-clocks = &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL1_VCO&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL2_VCO&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL1&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL2&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_SAI1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;, &lt;0&gt;, &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL1&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;3932160000&gt;, &lt;3612672000&gt;, &lt;393216000&gt;, &lt;361267200&gt;, &lt;12288000&gt;;</div><div class='add'>+	#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai1&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	fsl,sai-mclk-direction-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai3 {</div><div class='add'>+	assigned-clocks = &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL1_VCO&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL2_VCO&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL1&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL2&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_SAI3&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;, &lt;0&gt;, &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL1&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;3932160000&gt;, &lt;3612672000&gt;, &lt;393216000&gt;, &lt;361267200&gt;, &lt;12288000&gt;;</div><div class='add'>+	#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai3&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	fsl,sai-mclk-direction-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;scmi_iomuxc {</div><div class='add'>+	pinctrl_emdio: emdiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC		0x50e</div><div class='add'>+			IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO		0x90e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_enetc0: enetc0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3		0x50e</div><div class='add'>+			IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2		0x50e</div><div class='add'>+			IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1		0x50e</div><div class='add'>+			IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0		0x50e</div><div class='add'>+			IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL	0x57e</div><div class='add'>+			IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK	0x58e</div><div class='add'>+			IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL	0x57e</div><div class='add'>+			IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK	0x58e</div><div class='add'>+			IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0		0x57e</div><div class='add'>+			IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1		0x57e</div><div class='add'>+			IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2		0x57e</div><div class='add'>+			IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3		0x57e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_enetc1: enetc1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3		0x50e</div><div class='add'>+			IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2		0x50e</div><div class='add'>+			IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1		0x50e</div><div class='add'>+			IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0		0x50e</div><div class='add'>+			IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL	0x57e</div><div class='add'>+			IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK	0x58e</div><div class='add'>+			IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL	0x57e</div><div class='add'>+			IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK	0x58e</div><div class='add'>+			IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0		0x57e</div><div class='add'>+			IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1		0x57e</div><div class='add'>+			IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2		0x57e</div><div class='add'>+			IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3		0x57e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan2: flexcan2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_GPIO_IO25__CAN2_TX				0x39e</div><div class='add'>+			IMX95_PAD_GPIO_IO27__CAN2_RX				0x39e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_hp: hpgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_GPIO_IO21__GPIO2_IO_BIT21			0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i3c2: i3c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_ENET1_MDC__I3C2_SCL				0x40000186</div><div class='add'>+			IMX95_PAD_ENET1_MDIO__I3C2_SDA				0x40000186</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c1: lpi2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_I2C1_SCL__AONMIX_TOP_LPI2C1_SCL		0x40000b9e</div><div class='add'>+			IMX95_PAD_I2C1_SDA__AONMIX_TOP_LPI2C1_SDA		0x40000b9e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c2: lpi2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL		0x40000b9e</div><div class='add'>+			IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA		0x40000b9e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c3: lpi2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_GPIO_IO28__LPI2C3_SDA				0x40000b9e</div><div class='add'>+			IMX95_PAD_GPIO_IO29__LPI2C3_SCL				0x40000b9e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c4: lpi2c4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_GPIO_IO30__LPI2C4_SDA				0x40000b9e</div><div class='add'>+			IMX95_PAD_GPIO_IO31__LPI2C4_SCL				0x40000b9e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c6: lpi2c6grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_GPIO_IO02__LPI2C6_SDA				0x40000b9e</div><div class='add'>+			IMX95_PAD_GPIO_IO03__LPI2C6_SCL				0x40000b9e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_mipi_dsi_csi: mipidsigrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_XSPI1_DATA6__GPIO5_IO_BIT6			0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcal6524: pcal6524grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14			0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie0: pcie0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B		0x40000b1e</div><div class='add'>+			IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13			0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pdm: pdmgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK				0x31e</div><div class='add'>+			IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_BIT0	0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ptn5110: ptn5110grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11			0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7			0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai1: sai1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_RX_DATA_BIT0	0x31e</div><div class='add'>+			IMX95_PAD_SAI1_TXC__AONMIX_TOP_SAI1_TX_BCLK		0x31e</div><div class='add'>+			IMX95_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_TX_SYNC		0x31e</div><div class='add'>+			IMX95_PAD_SAI1_TXD0__AONMIX_TOP_SAI1_TX_DATA_BIT0	0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai2: sai2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_SAI2_RX_BCLK		0x31e</div><div class='add'>+			IMX95_PAD_ENET2_MDC__NETCMIX_TOP_SAI2_RX_SYNC		0x31e</div><div class='add'>+			IMX95_PAD_ENET2_TD3__NETCMIX_TOP_SAI2_RX_DATA_BIT0	0x31e</div><div class='add'>+			IMX95_PAD_ENET2_TD2__NETCMIX_TOP_SAI2_RX_DATA_BIT1	0x31e</div><div class='add'>+			IMX95_PAD_ENET2_TXC__NETCMIX_TOP_SAI2_TX_BCLK		0x31e</div><div class='add'>+			IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_SAI2_TX_SYNC	0x31e</div><div class='add'>+			IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_SAI2_TX_DATA_BIT0	0x31e</div><div class='add'>+			IMX95_PAD_ENET2_RXC__NETCMIX_TOP_SAI2_TX_DATA_BIT1	0x31e</div><div class='add'>+			IMX95_PAD_ENET2_RD0__NETCMIX_TOP_SAI2_TX_DATA_BIT2	0x31e</div><div class='add'>+			IMX95_PAD_ENET2_RD1__NETCMIX_TOP_SAI2_TX_DATA_BIT3	0x31e</div><div class='add'>+			IMX95_PAD_ENET2_RD2__NETCMIX_TOP_SAI2_MCLK		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai3: sai3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_GPIO_IO17__SAI3_MCLK				0x31e</div><div class='add'>+			IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK			0x31e</div><div class='add'>+			IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC			0x31e</div><div class='add'>+			IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0			0x31e</div><div class='add'>+			IMX95_PAD_GPIO_IO19__SAI3_TX_DATA_BIT0			0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_spdif: spdifgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_GPIO_IO22__SPDIF_IN				0x3fe</div><div class='add'>+			IMX95_PAD_GPIO_IO23__SPDIF_OUT				0x3fe</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_tpm3: tpm3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_CCM_CLKO2__GPIO3_IO_BIT27			0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_tpm6: tpm6grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_GPIO_IO08__TPM6_CH0				0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX		0x31e</div><div class='add'>+			IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart5: uart5grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_DAP_TDO_TRACESWO__LPUART5_TX			0x31e</div><div class='add'>+			IMX95_PAD_DAP_TDI__LPUART5_RX				0x31e</div><div class='add'>+			IMX95_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B			0x31e</div><div class='add'>+			IMX95_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B			0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_SD1_CLK__USDHC1_CLK				0x158e</div><div class='add'>+			IMX95_PAD_SD1_CMD__USDHC1_CMD				0x138e</div><div class='add'>+			IMX95_PAD_SD1_DATA0__USDHC1_DATA0			0x138e</div><div class='add'>+			IMX95_PAD_SD1_DATA1__USDHC1_DATA1			0x138e</div><div class='add'>+			IMX95_PAD_SD1_DATA2__USDHC1_DATA2			0x138e</div><div class='add'>+			IMX95_PAD_SD1_DATA3__USDHC1_DATA3			0x138e</div><div class='add'>+			IMX95_PAD_SD1_DATA4__USDHC1_DATA4			0x138e</div><div class='add'>+			IMX95_PAD_SD1_DATA5__USDHC1_DATA5			0x138e</div><div class='add'>+			IMX95_PAD_SD1_DATA6__USDHC1_DATA6			0x138e</div><div class='add'>+			IMX95_PAD_SD1_DATA7__USDHC1_DATA7			0x138e</div><div class='add'>+			IMX95_PAD_SD1_STROBE__USDHC1_STROBE			0x158e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_SD1_CLK__USDHC1_CLK				0x158e</div><div class='add'>+			IMX95_PAD_SD1_CMD__USDHC1_CMD				0x138e</div><div class='add'>+			IMX95_PAD_SD1_DATA0__USDHC1_DATA0			0x138e</div><div class='add'>+			IMX95_PAD_SD1_DATA1__USDHC1_DATA1			0x138e</div><div class='add'>+			IMX95_PAD_SD1_DATA2__USDHC1_DATA2			0x138e</div><div class='add'>+			IMX95_PAD_SD1_DATA3__USDHC1_DATA3			0x138e</div><div class='add'>+			IMX95_PAD_SD1_DATA4__USDHC1_DATA4			0x138e</div><div class='add'>+			IMX95_PAD_SD1_DATA5__USDHC1_DATA5			0x138e</div><div class='add'>+			IMX95_PAD_SD1_DATA6__USDHC1_DATA6			0x138e</div><div class='add'>+			IMX95_PAD_SD1_DATA7__USDHC1_DATA7			0x138e</div><div class='add'>+			IMX95_PAD_SD1_STROBE__USDHC1_STROBE			0x158e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_SD1_CLK__USDHC1_CLK				0x15fe</div><div class='add'>+			IMX95_PAD_SD1_CMD__USDHC1_CMD				0x13fe</div><div class='add'>+			IMX95_PAD_SD1_DATA0__USDHC1_DATA0			0x13fe</div><div class='add'>+			IMX95_PAD_SD1_DATA1__USDHC1_DATA1			0x13fe</div><div class='add'>+			IMX95_PAD_SD1_DATA2__USDHC1_DATA2			0x13fe</div><div class='add'>+			IMX95_PAD_SD1_DATA3__USDHC1_DATA3			0x13fe</div><div class='add'>+			IMX95_PAD_SD1_DATA4__USDHC1_DATA4			0x13fe</div><div class='add'>+			IMX95_PAD_SD1_DATA5__USDHC1_DATA5			0x13fe</div><div class='add'>+			IMX95_PAD_SD1_DATA6__USDHC1_DATA6			0x13fe</div><div class='add'>+			IMX95_PAD_SD1_DATA7__USDHC1_DATA7			0x13fe</div><div class='add'>+			IMX95_PAD_SD1_STROBE__USDHC1_STROBE			0x15fe</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0			0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_SD2_CLK__USDHC2_CLK				0x158e</div><div class='add'>+			IMX95_PAD_SD2_CMD__USDHC2_CMD				0x138e</div><div class='add'>+			IMX95_PAD_SD2_DATA0__USDHC2_DATA0			0x138e</div><div class='add'>+			IMX95_PAD_SD2_DATA1__USDHC2_DATA1			0x138e</div><div class='add'>+			IMX95_PAD_SD2_DATA2__USDHC2_DATA2			0x138e</div><div class='add'>+			IMX95_PAD_SD2_DATA3__USDHC2_DATA3			0x138e</div><div class='add'>+			IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT			0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_SD2_CLK__USDHC2_CLK				0x158e</div><div class='add'>+			IMX95_PAD_SD2_CMD__USDHC2_CMD				0x138e</div><div class='add'>+			IMX95_PAD_SD2_DATA0__USDHC2_DATA0			0x138e</div><div class='add'>+			IMX95_PAD_SD2_DATA1__USDHC2_DATA1			0x138e</div><div class='add'>+			IMX95_PAD_SD2_DATA2__USDHC2_DATA2			0x138e</div><div class='add'>+			IMX95_PAD_SD2_DATA3__USDHC2_DATA3			0x138e</div><div class='add'>+			IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT			0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_SD2_CLK__USDHC2_CLK				0x158e</div><div class='add'>+			IMX95_PAD_SD2_CMD__USDHC2_CMD				0x138e</div><div class='add'>+			IMX95_PAD_SD2_DATA0__USDHC2_DATA0			0x138e</div><div class='add'>+			IMX95_PAD_SD2_DATA1__USDHC2_DATA1			0x138e</div><div class='add'>+			IMX95_PAD_SD2_DATA2__USDHC2_DATA2			0x138e</div><div class='add'>+			IMX95_PAD_SD2_DATA3__USDHC2_DATA3			0x138e</div><div class='add'>+			IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT			0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_SD3_CLK__USDHC3_CLK				0x158e</div><div class='add'>+			IMX95_PAD_SD3_CMD__USDHC3_CMD				0x138e</div><div class='add'>+			IMX95_PAD_SD3_DATA0__USDHC3_DATA0			0x138e</div><div class='add'>+			IMX95_PAD_SD3_DATA1__USDHC3_DATA1			0x138e</div><div class='add'>+			IMX95_PAD_SD3_DATA2__USDHC3_DATA2			0x138e</div><div class='add'>+			IMX95_PAD_SD3_DATA3__USDHC3_DATA3			0x138e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_pwrseq: usdhc3pwrseqgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_XSPI1_SCLK__GPIO5_IO_BIT9			0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_SD3_CLK__USDHC3_CLK				0x158e</div><div class='add'>+			IMX95_PAD_SD3_CMD__USDHC3_CMD				0x138e</div><div class='add'>+			IMX95_PAD_SD3_DATA0__USDHC3_DATA0			0x138e</div><div class='add'>+			IMX95_PAD_SD3_DATA1__USDHC3_DATA1			0x138e</div><div class='add'>+			IMX95_PAD_SD3_DATA2__USDHC3_DATA2			0x138e</div><div class='add'>+			IMX95_PAD_SD3_DATA3__USDHC3_DATA3			0x138e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_SD3_CLK__USDHC3_CLK				0x15fe</div><div class='add'>+			IMX95_PAD_SD3_CMD__USDHC3_CMD				0x13fe</div><div class='add'>+			IMX95_PAD_SD3_DATA0__USDHC3_DATA0			0x13fe</div><div class='add'>+			IMX95_PAD_SD3_DATA1__USDHC3_DATA1			0x13fe</div><div class='add'>+			IMX95_PAD_SD3_DATA2__USDHC3_DATA2			0x13fe</div><div class='add'>+			IMX95_PAD_SD3_DATA3__USDHC3_DATA3			0x13fe</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;scmi_misc {</div><div class='add'>+	nxp,ctrl-ids = &lt;BRD_SM_CTRL_SD3_WAKE		1&gt;,</div><div class='add'>+		       &lt;BRD_SM_CTRL_PCIE1_WAKE		1&gt;,</div><div class='add'>+		       &lt;BRD_SM_CTRL_BT_WAKE		1&gt;,</div><div class='add'>+		       &lt;BRD_SM_CTRL_PCIE2_WAKE		1&gt;,</div><div class='add'>+		       &lt;BRD_SM_CTRL_BUTTON		1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;thermal_zones {</div><div class='add'>+	a55-thermal {</div><div class='add'>+		cooling-maps {</div><div class='add'>+			map1 {</div><div class='add'>+				cooling-device = &lt;&amp;fan0 0 1&gt;;</div><div class='add'>+				trip = &lt;&amp;atrip2&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			map2 {</div><div class='add'>+				cooling-device = &lt;&amp;fan0 1 2&gt;;</div><div class='add'>+				trip = &lt;&amp;atrip3&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			map3 {</div><div class='add'>+				cooling-device = &lt;&amp;fan0 2 3&gt;;</div><div class='add'>+				trip = &lt;&amp;atrip4&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		trips {</div><div class='add'>+			atrip2: trip2 {</div><div class='add'>+				hysteresis = &lt;2000&gt;;</div><div class='add'>+				temperature = &lt;55000&gt;;</div><div class='add'>+				type = "active";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			atrip3: trip3 {</div><div class='add'>+				hysteresis = &lt;2000&gt;;</div><div class='add'>+				temperature = &lt;65000&gt;;</div><div class='add'>+				type = "active";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			atrip4: trip4 {</div><div class='add'>+				hysteresis = &lt;2000&gt;;</div><div class='add'>+				temperature = &lt;75000&gt;;</div><div class='add'>+				type = "active";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pf09-thermal {</div><div class='add'>+		polling-delay = &lt;2000&gt;;</div><div class='add'>+		polling-delay-passive = &lt;250&gt;;</div><div class='add'>+		thermal-sensors = &lt;&amp;scmi_sensor 2&gt;;</div><div class='add'>+</div><div class='add'>+		trips {</div><div class='add'>+			pf09_alert: trip0 {</div><div class='add'>+				hysteresis = &lt;2000&gt;;</div><div class='add'>+				temperature = &lt;140000&gt;;</div><div class='add'>+				type = "passive";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pf09_crit: trip1 {</div><div class='add'>+				hysteresis = &lt;2000&gt;;</div><div class='add'>+				temperature = &lt;155000&gt;;</div><div class='add'>+				type = "critical";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pf53arm-thermal {</div><div class='add'>+		polling-delay = &lt;2000&gt;;</div><div class='add'>+		polling-delay-passive = &lt;250&gt;;</div><div class='add'>+		thermal-sensors = &lt;&amp;scmi_sensor 4&gt;;</div><div class='add'>+</div><div class='add'>+		cooling-maps {</div><div class='add'>+			map0 {</div><div class='add'>+				cooling-device = &lt;&amp;A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+						 &lt;&amp;A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+						 &lt;&amp;A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+						 &lt;&amp;A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+						 &lt;&amp;A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+						 &lt;&amp;A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				trip = &lt;&amp;pf5301_alert&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		trips {</div><div class='add'>+			pf5301_alert: trip0 {</div><div class='add'>+				hysteresis = &lt;2000&gt;;</div><div class='add'>+				temperature = &lt;140000&gt;;</div><div class='add'>+				type = "passive";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pf5301_crit: trip1 {</div><div class='add'>+				hysteresis = &lt;2000&gt;;</div><div class='add'>+				temperature = &lt;155000&gt;;</div><div class='add'>+				type = "critical";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pf53soc-thermal {</div><div class='add'>+		polling-delay = &lt;2000&gt;;</div><div class='add'>+		polling-delay-passive = &lt;250&gt;;</div><div class='add'>+		thermal-sensors = &lt;&amp;scmi_sensor 3&gt;;</div><div class='add'>+</div><div class='add'>+		trips {</div><div class='add'>+			pf5302_alert: trip0 {</div><div class='add'>+				hysteresis = &lt;2000&gt;;</div><div class='add'>+				temperature = &lt;140000&gt;;</div><div class='add'>+				type = "passive";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pf5302_crit: trip1 {</div><div class='add'>+				hysteresis = &lt;2000&gt;;</div><div class='add'>+				temperature = &lt;155000&gt;;</div><div class='add'>+				type = "critical";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tpm3 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_tpm3&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tpm6 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_tpm6&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb2 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usb_vbus&gt;;</div><div class='add'>+	disable-over-current;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_dwc3 {</div><div class='add'>+	adp-disable;</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	hnp-disable;</div><div class='add'>+	role-switch-default-mode = "peripheral";</div><div class='add'>+	srp-disable;</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	snps,dis-u1-entry-quirk;</div><div class='add'>+	snps,dis-u2-entry-quirk;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	port {</div><div class='add'>+		usb3_data_hs: endpoint {</div><div class='add'>+			remote-endpoint = &lt;&amp;typec_con_hs&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy {</div><div class='add'>+	orientation-switch;</div><div class='add'>+	fsl,phy-pcs-tx-deemph-3p5db-attenuation-db = &lt;17&gt;;</div><div class='add'>+	fsl,phy-pcs-tx-swing-full-percent = &lt;100&gt;;</div><div class='add'>+	fsl,phy-tx-preemp-amp-tune-microamp = &lt;600&gt;;</div><div class='add'>+	fsl,phy-tx-vboost-level-microvolt = &lt;1156&gt;;</div><div class='add'>+	fsl,phy-tx-vref-tune-percent = &lt;100&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	port {</div><div class='add'>+		usb3_data_ss: endpoint {</div><div class='add'>+			remote-endpoint = &lt;&amp;typec_con_ss&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	no-sd;</div><div class='add'>+	no-sdio;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1_200mhz&gt;;</div><div class='add'>+	pinctrl-3 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";</div><div class='add'>+	fsl,tuning-step = &lt;1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio3 00 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-3 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	fsl,tuning-step = &lt;1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	keep-power-in-suspend;</div><div class='add'>+	mmc-pwrseq = &lt;&amp;usdhc3_pwrseq&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+	pinctrl-3 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc3_vmmc&gt;;</div><div class='add'>+	wakeup-source;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xcvr {</div><div class='add'>+	clocks = &lt;&amp;scmi_clk IMX95_CLK_BUSWAKEUP&gt;,</div><div class='add'>+		 &lt;&amp;scmi_clk IMX95_CLK_SPDIF&gt;,</div><div class='add'>+		 &lt;&amp;dummy&gt;,</div><div class='add'>+		 &lt;&amp;scmi_clk IMX95_CLK_AUDIOXCVR&gt;,</div><div class='add'>+		 &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL1&gt;,</div><div class='add'>+		 &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL2&gt;;</div><div class='add'>+	clock-names = "ipg", "phy", "spba", "pll_ipg", "pll8k", "pll11k";</div><div class='add'>+	assigned-clocks = &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL1_VCO&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL2_VCO&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL1&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL2&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_SPDIF&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_AUDIOXCVR&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;, &lt;0&gt;,</div><div class='add'>+				 &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL1&gt;,</div><div class='add'>+				 &lt;&amp;scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;3932160000&gt;, &lt;3612672000&gt;,</div><div class='add'>+			       &lt;393216000&gt;, &lt;361267200&gt;,</div><div class='add'>+			       &lt;12288000&gt;, &lt;0&gt;;</div><div class='add'>+	#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_spdif&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk-sof.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk-sof.dts<br/>new file mode 100644<br/>index 000000000000..808a9fe3ebb2<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx95-19x19-evk-sof.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx95-19x19-evk-sof.dts</a></div><div class='hunk'>@@ -0,0 +1,84 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2025 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "imx95-19x19-evk.dts"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	sof_cpu: cm7-cpu@80000000 {</div><div class='add'>+		compatible = "fsl,imx95-cm7-sof";</div><div class='add'>+		reg = &lt;0x0 0x80000000 0x0 0x6100000&gt;;</div><div class='add'>+		reg-names = "sram";</div><div class='add'>+		memory-region = &lt;&amp;adma_res&gt;;</div><div class='add'>+		memory-region-names = "dma";</div><div class='add'>+		mboxes = &lt;&amp;mu7 2 0&gt;, &lt;&amp;mu7 2 1&gt;, &lt;&amp;mu7 3 0&gt;, &lt;&amp;mu7 3 1&gt;;</div><div class='add'>+		mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1";</div><div class='add'>+</div><div class='add'>+		sai3_cpu: port {</div><div class='add'>+			sai3_cpu_ep: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;wm8962_ep&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		adma_res: memory@86100000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0x0 0x86100000 0x0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sof-sound {</div><div class='add'>+		compatible = "audio-graph-card2";</div><div class='add'>+		links = &lt;&amp;sai3_cpu&gt;;</div><div class='add'>+		label = "audio";</div><div class='add'>+		hp-det-gpios = &lt;&amp;gpio2 11 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_hp&gt;;</div><div class='add'>+		widgets = "Headphone", "Headphones",</div><div class='add'>+			  "Microphone", "Headset Mic";</div><div class='add'>+		routing = "Headphones", "HPOUTL",</div><div class='add'>+			  "Headphones", "HPOUTR",</div><div class='add'>+			  "Headset Mic", "MICBIAS",</div><div class='add'>+			  "IN3R", "Headset Mic",</div><div class='add'>+			  "IN1R", "Headset Mic";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-wm8962 {</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;edma2 {</div><div class='add'>+	/* channels 30 and 31 reserved for FW usage */</div><div class='add'>+	dma-channel-mask = &lt;0xc0000000&gt;, &lt;0x0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai3 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wm8962 {</div><div class='add'>+	assigned-clocks = &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL1_VCO&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL2_VCO&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL1&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL2&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_SAI3&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;, &lt;0&gt;, &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL1&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;3932160000&gt;, &lt;3612672000&gt;,</div><div class='add'>+			       &lt;393216000&gt;, &lt;361267200&gt;,</div><div class='add'>+			       &lt;12288000&gt;;</div><div class='add'>+</div><div class='add'>+	port {</div><div class='add'>+		wm8962_ep: endpoint {</div><div class='add'>+			bitclock-master;</div><div class='add'>+			frame-master;</div><div class='add'>+			remote-endpoint = &lt;&amp;sai3_cpu_ep&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts<br/>new file mode 100644<br/>index 000000000000..aaa0da55a22b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts</a></div><div class='hunk'>@@ -0,0 +1,1144 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/pwm/pwm.h&gt;</div><div class='add'>+#include &lt;dt-bindings/usb/pd.h&gt;</div><div class='add'>+#include "imx95.dtsi"</div><div class='add'>+</div><div class='add'>+#define FALLING_EDGE			1</div><div class='add'>+#define RISING_EDGE			2</div><div class='add'>+</div><div class='add'>+#define BRD_SM_CTRL_SD3_WAKE		0x8000	/* PCAL6408A-0 */</div><div class='add'>+#define BRD_SM_CTRL_PCIE1_WAKE		0x8001	/* PCAL6408A-4 */</div><div class='add'>+#define BRD_SM_CTRL_BT_WAKE		0x8002	/* PCAL6408A-5 */</div><div class='add'>+#define BRD_SM_CTRL_PCIE2_WAKE		0x8003	/* PCAL6408A-6 */</div><div class='add'>+#define BRD_SM_CTRL_BUTTON		0x8004	/* PCAL6408A-7 */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "NXP i.MX95 19X19 board";</div><div class='add'>+	compatible = "fsl,imx95-19x19-evk", "fsl,imx95";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;enetc_port0;</div><div class='add'>+		gpio0 = &amp;gpio1;</div><div class='add'>+		gpio1 = &amp;gpio2;</div><div class='add'>+		gpio2 = &amp;gpio3;</div><div class='add'>+		gpio3 = &amp;gpio4;</div><div class='add'>+		gpio4 = &amp;gpio5;</div><div class='add'>+		i2c0 = &amp;lpi2c1;</div><div class='add'>+		i2c1 = &amp;lpi2c2;</div><div class='add'>+		i2c2 = &amp;lpi2c3;</div><div class='add'>+		i2c3 = &amp;lpi2c4;</div><div class='add'>+		i2c4 = &amp;lpi2c5;</div><div class='add'>+		i2c5 = &amp;lpi2c6;</div><div class='add'>+		i2c6 = &amp;lpi2c7;</div><div class='add'>+		i2c7 = &amp;lpi2c8;</div><div class='add'>+		mmc0 = &amp;usdhc1;</div><div class='add'>+		mmc1 = &amp;usdhc2;</div><div class='add'>+		serial0 = &amp;lpuart1;</div><div class='add'>+		serial4 = &amp;lpuart5;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bt_sco_codec: audio-codec-bt-sco {</div><div class='add'>+		#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+		compatible = "linux,bt-sco";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;lpuart1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@80000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x80000000 0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fan0: pwm-fan {</div><div class='add'>+		compatible = "pwm-fan";</div><div class='add'>+		#cooling-cells = &lt;2&gt;;</div><div class='add'>+		pwms = &lt;&amp;tpm6 2 4000000 PWM_POLARITY_INVERTED&gt;;</div><div class='add'>+		cooling-levels = &lt;64 128 192 255&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		linux_cma: linux,cma {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			alloc-ranges = &lt;0 0x80000000 0 0x7f000000&gt;;</div><div class='add'>+			size = &lt;0 0x3c000000&gt;;</div><div class='add'>+			linux,cma-default;</div><div class='add'>+			reusable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	flexcan1_phy: can-phy0 {</div><div class='add'>+		compatible = "nxp,tjr1443";</div><div class='add'>+		#phy-cells = &lt;0&gt;;</div><div class='add'>+		max-bitrate = &lt;8000000&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;i2c6_pcal6416 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		standby-gpios = &lt;&amp;i2c6_pcal6416 5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	flexcan2_phy: can-phy1 {</div><div class='add'>+		compatible = "nxp,tjr1443";</div><div class='add'>+		#phy-cells = &lt;0&gt;;</div><div class='add'>+		max-bitrate = &lt;8000000&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;i2c4_gpio_expander_21 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		standby-gpios = &lt;&amp;i2c4_gpio_expander_21 3 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vref_1v8: regulator-1p8v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-name = "+V1.8_SW";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3p3v: regulator-3p3v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "+V3.3_SW";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_audio_pwr: regulator-audio-pwr {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "audio-pwr";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;i2c4_gpio_expander_21 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_audio_slot: regulator-audio-slot {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "audio-wm8962";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;i2c4_gpio_expander_21 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_m2_pwr: regulator-m2-pwr {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "M.2-power";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;i2c7_pcal6524 20 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		/*</div><div class='add'>+		 * M.2 device only can be enabled(W_DISABLE1#) after all Power</div><div class='add'>+		 * Rails reach their minimum operating voltage (PCI Express M.2</div><div class='add'>+		 * Specification r5.1 3.1.4 Power-up Timing).</div><div class='add'>+		 * Set a delay equal to the max value of Tsettle here.</div><div class='add'>+		 */</div><div class='add'>+		startup-delay-us = &lt;5000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_pcie0: regulator-pcie {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "PCIE_WLAN_EN";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;reg_m2_pwr&gt;;</div><div class='add'>+		gpio = &lt;&amp;i2c7_pcal6524 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_slot_pwr: regulator-slot-pwr {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "PCIe slot-power";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;i2c7_pcal6524 14 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usdhc2_vmmc&gt;;</div><div class='add'>+		regulator-name = "VDD_SD2_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio3 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		off-on-delay-us = &lt;12000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb_vbus: regulator-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "USB_VBUS";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;i2c7_pcal6524 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-bt-sco {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,name = "bt-sco-audio";</div><div class='add'>+		simple-audio-card,format = "dsp_a";</div><div class='add'>+		simple-audio-card,bitclock-inversion;</div><div class='add'>+		simple-audio-card,frame-master = &lt;&amp;btcpu&gt;;</div><div class='add'>+		simple-audio-card,bitclock-master = &lt;&amp;btcpu&gt;;</div><div class='add'>+</div><div class='add'>+		btcpu: simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;sai1&gt;;</div><div class='add'>+			dai-tdm-slot-num = &lt;2&gt;;</div><div class='add'>+			dai-tdm-slot-width = &lt;16&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		simple-audio-card,codec {</div><div class='add'>+			sound-dai = &lt;&amp;bt_sco_codec 1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-micfil {</div><div class='add'>+		compatible = "fsl,imx-audio-card";</div><div class='add'>+		model = "micfil-audio";</div><div class='add'>+</div><div class='add'>+		pri-dai-link {</div><div class='add'>+			link-name = "micfil hifi";</div><div class='add'>+			format = "i2s";</div><div class='add'>+			cpu {</div><div class='add'>+				sound-dai = &lt;&amp;micfil&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-wm8962 {</div><div class='add'>+		compatible = "fsl,imx-audio-wm8962";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_hp&gt;;</div><div class='add'>+		model = "wm8962-audio";</div><div class='add'>+		audio-cpu = &lt;&amp;sai3&gt;;</div><div class='add'>+		audio-codec = &lt;&amp;wm8962&gt;;</div><div class='add'>+		hp-det-gpios = &lt;&amp;gpio2 11 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		audio-routing = "Headphone Jack", "HPOUTL",</div><div class='add'>+				"Headphone Jack", "HPOUTR",</div><div class='add'>+				"Ext Spk", "SPKOUTL",</div><div class='add'>+				"Ext Spk", "SPKOUTR",</div><div class='add'>+				"AMIC", "MICBIAS",</div><div class='add'>+				"IN3R", "AMIC",</div><div class='add'>+				"IN1R", "AMIC";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;adc1 {</div><div class='add'>+	vref-supply = &lt;&amp;reg_vref_1v8&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;enetc_port0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_enetc0&gt;;</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan1&gt;;</div><div class='add'>+	phys = &lt;&amp;flexcan1_phy&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan2&gt;;</div><div class='add'>+	phys = &lt;&amp;flexcan2_phy&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexspi1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexspi1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_flexspi1_reset&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio5 11 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		spi-max-frequency = &lt;200000000&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;8&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;8&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	adp5585: io-expander@34 {</div><div class='add'>+		compatible = "adi,adp5585-00", "adi,adp5585";</div><div class='add'>+		reg = &lt;0x34&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-reserved-ranges = &lt;5 1&gt;;</div><div class='add'>+		#pwm-cells = &lt;3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c3 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	i2c3_gpio_expander_20: gpio@20 {</div><div class='add'>+		compatible = "nxp,pcal6408";</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pca9632: pca9632@62 {</div><div class='add'>+		compatible = "nxp,pca9632";</div><div class='add'>+		reg = &lt;0x62&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		led_baclklight: led@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			label = "backlight";</div><div class='add'>+			linux,default-trigger = "none";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c4 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	wm8962: audio-codec@1a {</div><div class='add'>+		compatible = "wlf,wm8962";</div><div class='add'>+		reg = &lt;0x1a&gt;;</div><div class='add'>+		clocks = &lt;&amp;scmi_clk IMX95_CLK_SAI3&gt;;</div><div class='add'>+		DCVDD-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+		DBVDD-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+		AVDD-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+		CPVDD-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+		MICVDD-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+		PLLVDD-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+		SPKVDD1-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+		SPKVDD2-supply = &lt;&amp;reg_audio_pwr&gt;;</div><div class='add'>+		gpio-cfg = &lt; 0x0000 /* 0:Default */</div><div class='add'>+			     0x0000 /* 1:Default */</div><div class='add'>+			     0x0000 /* 2:FN_DMICCLK */</div><div class='add'>+			     0x0000 /* 3:Default */</div><div class='add'>+			     0x0000 /* 4:FN_DMICCDAT */</div><div class='add'>+			     0x0000 /* 5:Default */</div><div class='add'>+			   &gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c4_gpio_expander_21: gpio@21 {</div><div class='add'>+		compatible = "nxp,pcal6408";</div><div class='add'>+		reg = &lt;0x21&gt;;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio2&gt;;</div><div class='add'>+		interrupts = &lt;18 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_i2c4_pcal6408&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c5 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c5&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	i2c5_pcal6408: gpio@21 {</div><div class='add'>+		compatible = "nxp,pcal6408";</div><div class='add'>+		reg = &lt;0x21&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c6 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c6&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	i2c6_pcal6416: gpio@21 {</div><div class='add'>+		compatible = "nxp,pcal6416";</div><div class='add'>+		reg = &lt;0x21&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;28 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pcal6416&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c7 {</div><div class='add'>+	clock-frequency = &lt;1000000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c7&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	i2c7_pcal6524: i2c7-gpio@22 {</div><div class='add'>+		compatible = "nxp,pcal6524";</div><div class='add'>+		reg = &lt;0x22&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_i2c7_pcal6524&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio5&gt;;</div><div class='add'>+		interrupts = &lt;16 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ptn5110: tcpc@50 {</div><div class='add'>+		compatible = "nxp,ptn5110", "tcpci";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_typec&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio5&gt;;</div><div class='add'>+		interrupts = &lt;14 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		typec_con: connector {</div><div class='add'>+			compatible = "usb-c-connector";</div><div class='add'>+			label = "USB-C";</div><div class='add'>+			power-role = "dual";</div><div class='add'>+			data-role = "dual";</div><div class='add'>+			try-power-role = "sink";</div><div class='add'>+			source-pdos = &lt;PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)&gt;;</div><div class='add'>+			sink-pdos = &lt;PDO_FIXED(5000, 0, PDO_FIXED_USB_COMM)&gt;;</div><div class='add'>+			op-sink-microwatt = &lt;0&gt;;</div><div class='add'>+			self-powered;</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					typec_con_hs: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;usb3_data_hs&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					typec_con_ss: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;usb3_data_ss&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart1 {</div><div class='add'>+	/* console */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart5 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart5&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "nxp,88w8987-bt";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpspi7 {</div><div class='add'>+	num-cs = &lt;1&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpspi7&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio2 4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;micfil {</div><div class='add'>+	#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pdm&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL1_VCO&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL2_VCO&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL1&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL2&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_PDM&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;, &lt;0&gt;,</div><div class='add'>+				 &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL1&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;3932160000&gt;,</div><div class='add'>+			       &lt;3612672000&gt;, &lt;393216000&gt;,</div><div class='add'>+			       &lt;361267200&gt;, &lt;49152000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mu7 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;netcmix_blk_ctrl {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;netc_blk_ctrl {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;netc_emdio {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_emdio&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ethphy0: ethernet-phy@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;i2c5_pcal6408 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		reset-assert-us = &lt;10000&gt;;</div><div class='add'>+		reset-deassert-us = &lt;80000&gt;;</div><div class='add'>+		realtek,clkout-disable;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;netc_timer {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	reset-gpio = &lt;&amp;i2c7_pcal6524 5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vpcie-supply = &lt;&amp;reg_pcie0&gt;;</div><div class='add'>+	vpcie3v3aux-supply = &lt;&amp;reg_pcie0&gt;;</div><div class='add'>+	supports-clkreq;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0_ep {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	vpcie-supply = &lt;&amp;reg_pcie0&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie1&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	reset-gpio = &lt;&amp;i2c7_pcal6524 16 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vpcie-supply = &lt;&amp;reg_slot_pwr&gt;;</div><div class='add'>+	vpcie3v3aux-supply = &lt;&amp;reg_slot_pwr&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie1_ep {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie1&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	vpcie-supply = &lt;&amp;reg_slot_pwr&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai1 {</div><div class='add'>+	#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai1&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL1_VCO&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL2_VCO&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL1&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL2&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_SAI1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;, &lt;0&gt;,</div><div class='add'>+				 &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL1&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;3932160000&gt;,</div><div class='add'>+			       &lt;3612672000&gt;, &lt;393216000&gt;,</div><div class='add'>+			       &lt;361267200&gt;, &lt;12288000&gt;;</div><div class='add'>+	fsl,sai-mclk-direction-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai3 {</div><div class='add'>+	#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai3&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL1_VCO&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL2_VCO&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL1&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL2&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_SAI3&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;, &lt;0&gt;,</div><div class='add'>+				 &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL1&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;3932160000&gt;,</div><div class='add'>+			       &lt;3612672000&gt;, &lt;393216000&gt;,</div><div class='add'>+			       &lt;361267200&gt;, &lt;12288000&gt;;</div><div class='add'>+	fsl,sai-mclk-direction-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tpm3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_tpm3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb2 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	disable-over-current;</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usb_vbus&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_dwc3 {</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	hnp-disable;</div><div class='add'>+	srp-disable;</div><div class='add'>+	adp-disable;</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	role-switch-default-mode = "peripheral";</div><div class='add'>+	snps,dis-u1-entry-quirk;</div><div class='add'>+	snps,dis-u2-entry-quirk;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	port {</div><div class='add'>+		usb3_data_hs: endpoint {</div><div class='add'>+			remote-endpoint = &lt;&amp;typec_con_hs&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy {</div><div class='add'>+	fsl,phy-pcs-tx-deemph-3p5db-attenuation-db = &lt;17&gt;;</div><div class='add'>+	fsl,phy-pcs-tx-swing-full-percent = &lt;100&gt;;</div><div class='add'>+	fsl,phy-tx-preemp-amp-tune-microamp = &lt;600&gt;;</div><div class='add'>+	fsl,phy-tx-vboost-level-microvolt = &lt;1156&gt;;</div><div class='add'>+	fsl,phy-tx-vref-tune-percent = &lt;100&gt;;</div><div class='add'>+	orientation-switch;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	port {</div><div class='add'>+		usb3_data_ss: endpoint {</div><div class='add'>+			remote-endpoint = &lt;&amp;typec_con_ss&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1_200mhz&gt;;</div><div class='add'>+	pinctrl-3 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	no-sdio;</div><div class='add'>+	no-sd;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-3 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio3 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;scmi_misc {</div><div class='add'>+	nxp,ctrl-ids = &lt;BRD_SM_CTRL_SD3_WAKE	FALLING_EDGE</div><div class='add'>+			BRD_SM_CTRL_PCIE1_WAKE	FALLING_EDGE</div><div class='add'>+			BRD_SM_CTRL_BT_WAKE	FALLING_EDGE</div><div class='add'>+			BRD_SM_CTRL_PCIE2_WAKE	FALLING_EDGE</div><div class='add'>+			BRD_SM_CTRL_BUTTON	FALLING_EDGE&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog3 {</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;scmi_iomuxc {</div><div class='add'>+	pinctrl_emdio: emdiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC		0x50e</div><div class='add'>+			IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO		0x90e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_enetc0: enetc0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3		0x50e</div><div class='add'>+			IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2		0x50e</div><div class='add'>+			IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1		0x50e</div><div class='add'>+			IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0		0x50e</div><div class='add'>+			IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL	0x57e</div><div class='add'>+			IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK	0x58e</div><div class='add'>+			IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL	0x57e</div><div class='add'>+			IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK	0x58e</div><div class='add'>+			IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0		0x57e</div><div class='add'>+			IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1		0x57e</div><div class='add'>+			IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2		0x57e</div><div class='add'>+			IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3		0x57e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan1: flexcan1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX			0x39e</div><div class='add'>+			IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX		0x39e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan2: flexcan2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_GPIO_IO25__CAN2_TX				0x39e</div><div class='add'>+			IMX95_PAD_GPIO_IO27__CAN2_RX				0x39e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexspi1: flexspi1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_XSPI1_SS0_B__FLEXSPI1_A_SS0_B			0x3fe</div><div class='add'>+			IMX95_PAD_XSPI1_SCLK__FLEXSPI1_A_SCLK			0x3fe</div><div class='add'>+			IMX95_PAD_XSPI1_DQS__FLEXSPI1_A_DQS			0x3fe</div><div class='add'>+			IMX95_PAD_XSPI1_DATA0__FLEXSPI1_A_DATA_BIT0		0x3fe</div><div class='add'>+			IMX95_PAD_XSPI1_DATA1__FLEXSPI1_A_DATA_BIT1		0x3fe</div><div class='add'>+			IMX95_PAD_XSPI1_DATA2__FLEXSPI1_A_DATA_BIT2		0x3fe</div><div class='add'>+			IMX95_PAD_XSPI1_DATA3__FLEXSPI1_A_DATA_BIT3		0x3fe</div><div class='add'>+			IMX95_PAD_XSPI1_DATA4__FLEXSPI1_A_DATA_BIT4		0x3fe</div><div class='add'>+			IMX95_PAD_XSPI1_DATA5__FLEXSPI1_A_DATA_BIT5		0x3fe</div><div class='add'>+			IMX95_PAD_XSPI1_DATA6__FLEXSPI1_A_DATA_BIT6		0x3fe</div><div class='add'>+			IMX95_PAD_XSPI1_DATA7__FLEXSPI1_A_DATA_BIT7		0x3fe</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexspi1_reset: flexspi1-reset-grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11			0x3fe</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_hp: hpgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_GPIO_IO11__GPIO2_IO_BIT11		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4_pcal6408: i2c4pcal6498grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_GPIO_IO18__GPIO2_IO_BIT18			0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c7_pcal6524: i2c7pcal6524grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_GPIO_IO36__GPIO5_IO_BIT16			0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c1: lpi2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_I2C1_SCL__AONMIX_TOP_LPI2C1_SCL		0x40000b9e</div><div class='add'>+			IMX95_PAD_I2C1_SDA__AONMIX_TOP_LPI2C1_SDA		0x40000b9e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c2: lpi2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL		0x40000b9e</div><div class='add'>+			IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA		0x40000b9e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c3: lpi2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_GPIO_IO00__LPI2C3_SDA				0x40000b9e</div><div class='add'>+			IMX95_PAD_GPIO_IO01__LPI2C3_SCL				0x40000b9e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c4: lpi2c4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_GPIO_IO30__LPI2C4_SDA			0x40000b9e</div><div class='add'>+			IMX95_PAD_GPIO_IO31__LPI2C4_SCL			0x40000b9e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c5: lpi2c5grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_GPIO_IO22__LPI2C5_SDA			0x40000b9e</div><div class='add'>+			IMX95_PAD_GPIO_IO23__LPI2C5_SCL			0x40000b9e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c6: lpi2c6grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_GPIO_IO02__LPI2C6_SDA			0x40000b9e</div><div class='add'>+			IMX95_PAD_GPIO_IO03__LPI2C6_SCL			0x40000b9e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c7: lpi2c7grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_GPIO_IO08__LPI2C7_SDA			0x40000b9e</div><div class='add'>+			IMX95_PAD_GPIO_IO09__LPI2C7_SCL			0x40000b9e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpspi7: lpspi7grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_GPIO_IO04__GPIO2_IO_BIT4		0x3fe</div><div class='add'>+			IMX95_PAD_GPIO_IO05__LPSPI7_SIN			0x3fe</div><div class='add'>+			IMX95_PAD_GPIO_IO06__LPSPI7_SOUT		0x3fe</div><div class='add'>+			IMX95_PAD_GPIO_IO07__LPSPI7_SCK			0x3fe</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie0: pcie0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B		0x4000031e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie1: pcie1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B		0x4000031e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcal6416: pcal6416grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_CCM_CLKO3__GPIO4_IO_BIT28			0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pdm: pdmgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK				0x31e</div><div class='add'>+			IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_BIT0	0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai1: sai1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_RX_DATA_BIT0    0x31e</div><div class='add'>+			IMX95_PAD_SAI1_TXC__AONMIX_TOP_SAI1_TX_BCLK      0x31e</div><div class='add'>+			IMX95_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_TX_SYNC     0x31e</div><div class='add'>+			IMX95_PAD_SAI1_TXD0__AONMIX_TOP_SAI1_TX_DATA_BIT0    0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai2: sai2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_SAI2_RX_BCLK			0x31e</div><div class='add'>+			IMX95_PAD_ENET2_MDC__NETCMIX_TOP_SAI2_RX_SYNC			0x31e</div><div class='add'>+			IMX95_PAD_ENET2_TD3__NETCMIX_TOP_SAI2_RX_DATA_BIT0		0x31e</div><div class='add'>+			IMX95_PAD_ENET2_TD2__NETCMIX_TOP_SAI2_RX_DATA_BIT1		0x31e</div><div class='add'>+			IMX95_PAD_ENET2_TXC__NETCMIX_TOP_SAI2_TX_BCLK			0x31e</div><div class='add'>+			IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_SAI2_TX_SYNC		0x31e</div><div class='add'>+			IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_SAI2_TX_DATA_BIT0		0x31e</div><div class='add'>+			IMX95_PAD_ENET2_RXC__NETCMIX_TOP_SAI2_TX_DATA_BIT1		0x31e</div><div class='add'>+			IMX95_PAD_ENET2_RD0__NETCMIX_TOP_SAI2_TX_DATA_BIT2		0x31e</div><div class='add'>+			IMX95_PAD_ENET2_RD1__NETCMIX_TOP_SAI2_TX_DATA_BIT3		0x31e</div><div class='add'>+			IMX95_PAD_ENET2_RD2__NETCMIX_TOP_SAI2_MCLK			0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai3: sai3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_GPIO_IO17__SAI3_MCLK				0x31e</div><div class='add'>+			IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK			0x31e</div><div class='add'>+			IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC			0x31e</div><div class='add'>+			IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0			0x31e</div><div class='add'>+			IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0			0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_tpm3: tpm3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_GPIO_IO12__TPM3_CH2			0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_tpm6: tpm6grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_GPIO_IO19__TPM6_CH2			0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX      0x31e</div><div class='add'>+			IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX      0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart5: uart5grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_DAP_TDO_TRACESWO__LPUART5_TX		0x31e</div><div class='add'>+			IMX95_PAD_DAP_TDI__LPUART5_RX			0x31e</div><div class='add'>+			IMX95_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B		0x31e</div><div class='add'>+			IMX95_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_SD1_CLK__USDHC1_CLK			0x158e</div><div class='add'>+			IMX95_PAD_SD1_CMD__USDHC1_CMD			0x138e</div><div class='add'>+			IMX95_PAD_SD1_DATA0__USDHC1_DATA0		0x138e</div><div class='add'>+			IMX95_PAD_SD1_DATA1__USDHC1_DATA1		0x138e</div><div class='add'>+			IMX95_PAD_SD1_DATA2__USDHC1_DATA2		0x138e</div><div class='add'>+			IMX95_PAD_SD1_DATA3__USDHC1_DATA3		0x138e</div><div class='add'>+			IMX95_PAD_SD1_DATA4__USDHC1_DATA4		0x138e</div><div class='add'>+			IMX95_PAD_SD1_DATA5__USDHC1_DATA5		0x138e</div><div class='add'>+			IMX95_PAD_SD1_DATA6__USDHC1_DATA6		0x138e</div><div class='add'>+			IMX95_PAD_SD1_DATA7__USDHC1_DATA7		0x138e</div><div class='add'>+			IMX95_PAD_SD1_STROBE__USDHC1_STROBE		0x158e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_SD1_CLK__USDHC1_CLK			0x158e</div><div class='add'>+			IMX95_PAD_SD1_CMD__USDHC1_CMD			0x138e</div><div class='add'>+			IMX95_PAD_SD1_DATA0__USDHC1_DATA0		0x138e</div><div class='add'>+			IMX95_PAD_SD1_DATA1__USDHC1_DATA1		0x138e</div><div class='add'>+			IMX95_PAD_SD1_DATA2__USDHC1_DATA2		0x138e</div><div class='add'>+			IMX95_PAD_SD1_DATA3__USDHC1_DATA3		0x138e</div><div class='add'>+			IMX95_PAD_SD1_DATA4__USDHC1_DATA4		0x138e</div><div class='add'>+			IMX95_PAD_SD1_DATA5__USDHC1_DATA5		0x138e</div><div class='add'>+			IMX95_PAD_SD1_DATA6__USDHC1_DATA6		0x138e</div><div class='add'>+			IMX95_PAD_SD1_DATA7__USDHC1_DATA7		0x138e</div><div class='add'>+			IMX95_PAD_SD1_STROBE__USDHC1_STROBE		0x158e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_SD1_CLK__USDHC1_CLK			0x15fe</div><div class='add'>+			IMX95_PAD_SD1_CMD__USDHC1_CMD			0x13fe</div><div class='add'>+			IMX95_PAD_SD1_DATA0__USDHC1_DATA0		0x13fe</div><div class='add'>+			IMX95_PAD_SD1_DATA1__USDHC1_DATA1		0x13fe</div><div class='add'>+			IMX95_PAD_SD1_DATA2__USDHC1_DATA2		0x13fe</div><div class='add'>+			IMX95_PAD_SD1_DATA3__USDHC1_DATA3		0x13fe</div><div class='add'>+			IMX95_PAD_SD1_DATA4__USDHC1_DATA4		0x13fe</div><div class='add'>+			IMX95_PAD_SD1_DATA5__USDHC1_DATA5		0x13fe</div><div class='add'>+			IMX95_PAD_SD1_DATA6__USDHC1_DATA6		0x13fe</div><div class='add'>+			IMX95_PAD_SD1_DATA7__USDHC1_DATA7		0x13fe</div><div class='add'>+			IMX95_PAD_SD1_STROBE__USDHC1_STROBE		0x15fe</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_typec: typecgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14			0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0		0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_SD2_CLK__USDHC2_CLK			0x158e</div><div class='add'>+			IMX95_PAD_SD2_CMD__USDHC2_CMD			0x138e</div><div class='add'>+			IMX95_PAD_SD2_DATA0__USDHC2_DATA0		0x138e</div><div class='add'>+			IMX95_PAD_SD2_DATA1__USDHC2_DATA1		0x138e</div><div class='add'>+			IMX95_PAD_SD2_DATA2__USDHC2_DATA2		0x138e</div><div class='add'>+			IMX95_PAD_SD2_DATA3__USDHC2_DATA3		0x138e</div><div class='add'>+			IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT		0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_SD2_CLK__USDHC2_CLK			0x158e</div><div class='add'>+			IMX95_PAD_SD2_CMD__USDHC2_CMD			0x138e</div><div class='add'>+			IMX95_PAD_SD2_DATA0__USDHC2_DATA0		0x138e</div><div class='add'>+			IMX95_PAD_SD2_DATA1__USDHC2_DATA1		0x138e</div><div class='add'>+			IMX95_PAD_SD2_DATA2__USDHC2_DATA2		0x138e</div><div class='add'>+			IMX95_PAD_SD2_DATA3__USDHC2_DATA3		0x138e</div><div class='add'>+			IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT		0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_SD2_CLK__USDHC2_CLK			0x158e</div><div class='add'>+			IMX95_PAD_SD2_CMD__USDHC2_CMD			0x138e</div><div class='add'>+			IMX95_PAD_SD2_DATA0__USDHC2_DATA0		0x138e</div><div class='add'>+			IMX95_PAD_SD2_DATA1__USDHC2_DATA1		0x138e</div><div class='add'>+			IMX95_PAD_SD2_DATA2__USDHC2_DATA2		0x138e</div><div class='add'>+			IMX95_PAD_SD2_DATA3__USDHC2_DATA3		0x138e</div><div class='add'>+			IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT		0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;thermal_zones {</div><div class='add'>+	a55-thermal {</div><div class='add'>+		trips {</div><div class='add'>+			atrip2: trip2 {</div><div class='add'>+				temperature = &lt;55000&gt;;</div><div class='add'>+				hysteresis = &lt;2000&gt;;</div><div class='add'>+				type = "active";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			atrip3: trip3 {</div><div class='add'>+				temperature = &lt;65000&gt;;</div><div class='add'>+				hysteresis = &lt;2000&gt;;</div><div class='add'>+				type = "active";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			atrip4: trip4 {</div><div class='add'>+				temperature = &lt;75000&gt;;</div><div class='add'>+				hysteresis = &lt;2000&gt;;</div><div class='add'>+				type = "active";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cooling-maps {</div><div class='add'>+			map1 {</div><div class='add'>+				trip = &lt;&amp;atrip2&gt;;</div><div class='add'>+				cooling-device = &lt;&amp;fan0 0 1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			map2 {</div><div class='add'>+				trip = &lt;&amp;atrip3&gt;;</div><div class='add'>+				cooling-device = &lt;&amp;fan0 1 2&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			map3 {</div><div class='add'>+				trip = &lt;&amp;atrip4&gt;;</div><div class='add'>+				cooling-device = &lt;&amp;fan0 2 3&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pf09-thermal {</div><div class='add'>+		polling-delay = &lt;2000&gt;;</div><div class='add'>+		polling-delay-passive = &lt;250&gt;;</div><div class='add'>+		thermal-sensors = &lt;&amp;scmi_sensor 2&gt;;</div><div class='add'>+</div><div class='add'>+		trips {</div><div class='add'>+			pf09_alert: trip0 {</div><div class='add'>+				hysteresis = &lt;2000&gt;;</div><div class='add'>+				temperature = &lt;140000&gt;;</div><div class='add'>+				type = "passive";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pf09_crit: trip1 {</div><div class='add'>+				hysteresis = &lt;2000&gt;;</div><div class='add'>+				temperature = &lt;155000&gt;;</div><div class='add'>+				type = "critical";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pf53arm-thermal {</div><div class='add'>+		polling-delay = &lt;2000&gt;;</div><div class='add'>+		polling-delay-passive = &lt;250&gt;;</div><div class='add'>+		thermal-sensors = &lt;&amp;scmi_sensor 4&gt;;</div><div class='add'>+</div><div class='add'>+		cooling-maps {</div><div class='add'>+			map0 {</div><div class='add'>+				trip = &lt;&amp;pf5301_alert&gt;;</div><div class='add'>+				cooling-device =</div><div class='add'>+					&lt;&amp;A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+					&lt;&amp;A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+					&lt;&amp;A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+					&lt;&amp;A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+					&lt;&amp;A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+					&lt;&amp;A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		trips {</div><div class='add'>+			pf5301_alert: trip0 {</div><div class='add'>+				hysteresis = &lt;2000&gt;;</div><div class='add'>+				temperature = &lt;140000&gt;;</div><div class='add'>+				type = "passive";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pf5301_crit: trip1 {</div><div class='add'>+				hysteresis = &lt;2000&gt;;</div><div class='add'>+				temperature = &lt;155000&gt;;</div><div class='add'>+				type = "critical";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pf53soc-thermal {</div><div class='add'>+		polling-delay = &lt;2000&gt;;</div><div class='add'>+		polling-delay-passive = &lt;250&gt;;</div><div class='add'>+		thermal-sensors = &lt;&amp;scmi_sensor 3&gt;;</div><div class='add'>+</div><div class='add'>+		trips {</div><div class='add'>+			pf5302_alert: trip0 {</div><div class='add'>+				hysteresis = &lt;2000&gt;;</div><div class='add'>+				temperature = &lt;140000&gt;;</div><div class='add'>+				type = "passive";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pf5302_crit: trip1 {</div><div class='add'>+				hysteresis = &lt;2000&gt;;</div><div class='add'>+				temperature = &lt;155000&gt;;</div><div class='add'>+				type = "critical";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tpm6 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_tpm6&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-verdin-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-verdin-evk.dts<br/>new file mode 100644<br/>index 000000000000..2b0ff232f680<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx95-19x19-verdin-evk.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx95-19x19-verdin-evk.dts</a></div><div class='hunk'>@@ -0,0 +1,695 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 NXP</div><div class='add'>+ * Copyright 2025 Marek Vasut &lt;marek.vasut@mailbox.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/usb/pd.h&gt;</div><div class='add'>+#include "imx95.dtsi"</div><div class='add'>+</div><div class='add'>+#define FALLING_EDGE			1</div><div class='add'>+#define RISING_EDGE			2</div><div class='add'>+</div><div class='add'>+#define BRD_SM_CTRL_SD3_WAKE		0x8000	/* PCAL6408A-0 */</div><div class='add'>+#define BRD_SM_CTRL_PCIE1_WAKE		0x8001	/* PCAL6408A-4 */</div><div class='add'>+#define BRD_SM_CTRL_BT_WAKE		0x8002	/* PCAL6408A-5 */</div><div class='add'>+#define BRD_SM_CTRL_PCIE2_WAKE		0x8003	/* PCAL6408A-6 */</div><div class='add'>+#define BRD_SM_CTRL_BUTTON		0x8004	/* PCAL6408A-7 */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "i.MX 95 Verdin Evaluation Kit (EVK)";</div><div class='add'>+	compatible = "toradex,verdin-imx95-19x19-evk", "fsl,imx95";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;enetc_port0;</div><div class='add'>+		ethernet1 = &amp;enetc_port1;</div><div class='add'>+		ethernet2 = &amp;enetc_port2;</div><div class='add'>+		gpio0 = &amp;gpio1;</div><div class='add'>+		gpio1 = &amp;gpio2;</div><div class='add'>+		gpio2 = &amp;gpio3;</div><div class='add'>+		gpio3 = &amp;gpio4;</div><div class='add'>+		gpio4 = &amp;gpio5;</div><div class='add'>+		i2c0 = &amp;lpi2c1;</div><div class='add'>+		i2c1 = &amp;lpi2c2;</div><div class='add'>+		i2c2 = &amp;lpi2c3;</div><div class='add'>+		i2c3 = &amp;lpi2c4;</div><div class='add'>+		i2c4 = &amp;lpi2c5;</div><div class='add'>+		i2c5 = &amp;lpi2c6;</div><div class='add'>+		i2c6 = &amp;lpi2c7;</div><div class='add'>+		i2c7 = &amp;lpi2c8;</div><div class='add'>+		mmc0 = &amp;usdhc1;</div><div class='add'>+		mmc1 = &amp;usdhc2;</div><div class='add'>+		serial0 = &amp;lpuart1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;lpuart1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@80000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x80000000 0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		linux_cma: linux,cma {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			alloc-ranges = &lt;0 0x80000000 0 0x7f000000&gt;;</div><div class='add'>+			size = &lt;0 0x3c000000&gt;;</div><div class='add'>+			linux,cma-default;</div><div class='add'>+			reusable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_1p8v: regulator-1p8v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-name = "+V1.8_SW";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3p3v: regulator-3p3v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "+V3.3_SW";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_m2_pwr: regulator-m2-pwr {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "M.2-power";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio2 4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_pcie0: regulator-pcie {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "PCIE_WLAN_EN";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;reg_m2_pwr&gt;;</div><div class='add'>+		gpio = &lt;&amp;i2c7_pcal6524 18 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usdhc2_vmmc&gt;;</div><div class='add'>+		regulator-name = "VDD_SD2_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio3 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		off-on-delay-us = &lt;12000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usdhc3_pwrseq: usdhc3-pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-simple";</div><div class='add'>+		reset-gpios = &lt;&amp;i2c7_pcal6524 11 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound-wm8904 {</div><div class='add'>+		compatible = "fsl,imx-audio-wm8904";</div><div class='add'>+		model = "wm8904-audio";</div><div class='add'>+		audio-cpu = &lt;&amp;sai3&gt;;</div><div class='add'>+		audio-codec = &lt;&amp;wm8904&gt;;</div><div class='add'>+		audio-routing =</div><div class='add'>+			"Headphone Jack", "HPOUTL",</div><div class='add'>+			"Headphone Jack", "HPOUTR",</div><div class='add'>+			"AMIC", "MICBIAS",</div><div class='add'>+			"IN2L", "AMIC";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;enetc_port0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_enetc0&gt;;</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexspi1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexspi1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_flexspi1_reset&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;gpio5 11 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		spi-max-frequency = &lt;200000000&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;8&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;8&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c4 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	wm8904: codec@1a {</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		compatible = "wlf,wm8904";</div><div class='add'>+		reg = &lt;0x1a&gt;;</div><div class='add'>+		clocks = &lt;&amp;scmi_clk IMX95_CLK_SAI3&gt;;</div><div class='add'>+		clock-names = "mclk";</div><div class='add'>+		AVDD-supply = &lt;&amp;reg_1p8v&gt;;</div><div class='add'>+		CPVDD-supply = &lt;&amp;reg_1p8v&gt;;</div><div class='add'>+		DBVDD-supply = &lt;&amp;reg_1p8v&gt;;</div><div class='add'>+		DCVDD-supply = &lt;&amp;reg_1p8v&gt;;</div><div class='add'>+		MICVDD-supply = &lt;&amp;reg_1p8v&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c5 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c5&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c6 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c6&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c7 {</div><div class='add'>+	clock-frequency = &lt;1000000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c7&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	i2c7_pcal6524: i2c7-gpio@23 {</div><div class='add'>+		compatible = "nxp,pcal6524";</div><div class='add'>+		reg = &lt;0x23&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_i2c7_pcal6524&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio5&gt;;</div><div class='add'>+		interrupts = &lt;16 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Current measurement at SoM 5V power output */</div><div class='add'>+	hwmon@41 {</div><div class='add'>+		compatible = "ti,ina219";</div><div class='add'>+		reg = &lt;0x41&gt;;</div><div class='add'>+		shunt-resistor = &lt;10000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Current measurement at Board power input */</div><div class='add'>+	hwmon@45 {</div><div class='add'>+		compatible = "ti,ina219";</div><div class='add'>+		reg = &lt;0x45&gt;;</div><div class='add'>+		shunt-resistor = &lt;10000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@50 {</div><div class='add'>+		compatible = "st,24c02";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ptn5110: tcpc@52 {</div><div class='add'>+		compatible = "nxp,ptn5110", "tcpci";</div><div class='add'>+		reg = &lt;0x52&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_typec&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio5&gt;;</div><div class='add'>+		interrupts = &lt;14 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		typec_con: connector {</div><div class='add'>+			compatible = "usb-c-connector";</div><div class='add'>+			label = "USB-C";</div><div class='add'>+			power-role = "dual";</div><div class='add'>+			data-role = "dual";</div><div class='add'>+			try-power-role = "sink";</div><div class='add'>+			source-pdos = &lt;PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)&gt;;</div><div class='add'>+			sink-pdos = &lt;PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)</div><div class='add'>+				     PDO_VAR(5000, 20000, 3000)&gt;;</div><div class='add'>+			op-sink-microwatt = &lt;15000000&gt;;</div><div class='add'>+			self-powered;</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					typec_con_hs: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;usb3_data_hs&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					typec_con_ss: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;usb3_data_ss&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart1 {</div><div class='add'>+	/* console */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mu7 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;netcmix_blk_ctrl {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;netc_blk_ctrl {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;netc_emdio {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_emdio&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ethphy0: ethernet-phy@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		realtek,clkout-disable;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	reset-gpio = &lt;&amp;i2c7_pcal6524 17 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vpcie-supply = &lt;&amp;reg_pcie0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie1&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	reset-gpio = &lt;&amp;i2c7_pcal6524 16 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai1 {</div><div class='add'>+	#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai1&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL1_VCO&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL2_VCO&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL1&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL2&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_SAI1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;, &lt;0&gt;,</div><div class='add'>+				 &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL1&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;3932160000&gt;,</div><div class='add'>+			       &lt;3612672000&gt;, &lt;393216000&gt;,</div><div class='add'>+			       &lt;361267200&gt;, &lt;12288000&gt;;</div><div class='add'>+	fsl,sai-mclk-direction-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai3 {</div><div class='add'>+	#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai3&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL1_VCO&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL2_VCO&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL1&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL2&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_SAI3&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;, &lt;0&gt;,</div><div class='add'>+				 &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL1&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;3932160000&gt;,</div><div class='add'>+			       &lt;3612672000&gt;, &lt;393216000&gt;,</div><div class='add'>+			       &lt;361267200&gt;, &lt;12288000&gt;;</div><div class='add'>+	fsl,sai-mclk-direction-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_dwc3 {</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	hnp-disable;</div><div class='add'>+	srp-disable;</div><div class='add'>+	adp-disable;</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	role-switch-default-mode = "peripheral";</div><div class='add'>+	snps,dis-u1-entry-quirk;</div><div class='add'>+	snps,dis-u2-entry-quirk;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	port {</div><div class='add'>+		usb3_data_hs: endpoint {</div><div class='add'>+			remote-endpoint = &lt;&amp;typec_con_hs&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy {</div><div class='add'>+	fsl,phy-tx-preemp-amp-tune-microamp = &lt;600&gt;;</div><div class='add'>+	orientation-switch;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	port {</div><div class='add'>+		usb3_data_ss: endpoint {</div><div class='add'>+			remote-endpoint = &lt;&amp;typec_con_ss&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1_200mhz&gt;;</div><div class='add'>+	pinctrl-3 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	no-sdio;</div><div class='add'>+	no-sd;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-3 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio3 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	mmc-pwrseq = &lt;&amp;usdhc3_pwrseq&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_pcie0&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	keep-power-in-suspend;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;scmi_misc {</div><div class='add'>+	nxp,ctrl-ids = &lt;BRD_SM_CTRL_SD3_WAKE	FALLING_EDGE</div><div class='add'>+			BRD_SM_CTRL_PCIE1_WAKE	FALLING_EDGE</div><div class='add'>+			BRD_SM_CTRL_BT_WAKE	FALLING_EDGE</div><div class='add'>+			BRD_SM_CTRL_PCIE2_WAKE	FALLING_EDGE</div><div class='add'>+			BRD_SM_CTRL_BUTTON	FALLING_EDGE&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog3 {</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;scmi_iomuxc {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_hog&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl_hog: hoggrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;IMX95_PAD_GPIO_IO04__GPIO2_IO_BIT4			0x3fe&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_emdio: emdiogrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC		0x57e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO		0x97e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_enetc0: enetc0grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3	0x57e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2	0x57e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1	0x57e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0	0x57e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL	0x57e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK	0x58e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL	0x57e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK	0x58e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0	0x57e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1	0x57e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2	0x57e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3	0x57e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexspi1: flexspi1grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;IMX95_PAD_XSPI1_SS0_B__FLEXSPI1_A_SS0_B		0x3fe&gt;,</div><div class='add'>+			&lt;IMX95_PAD_XSPI1_SCLK__FLEXSPI1_A_SCLK			0x3fe&gt;,</div><div class='add'>+			&lt;IMX95_PAD_XSPI1_DQS__FLEXSPI1_A_DQS			0x3fe&gt;,</div><div class='add'>+			&lt;IMX95_PAD_XSPI1_DATA0__FLEXSPI1_A_DATA_BIT0		0x3fe&gt;,</div><div class='add'>+			&lt;IMX95_PAD_XSPI1_DATA1__FLEXSPI1_A_DATA_BIT1		0x3fe&gt;,</div><div class='add'>+			&lt;IMX95_PAD_XSPI1_DATA2__FLEXSPI1_A_DATA_BIT2		0x3fe&gt;,</div><div class='add'>+			&lt;IMX95_PAD_XSPI1_DATA3__FLEXSPI1_A_DATA_BIT3		0x3fe&gt;,</div><div class='add'>+			&lt;IMX95_PAD_XSPI1_DATA4__FLEXSPI1_A_DATA_BIT4		0x3fe&gt;,</div><div class='add'>+			&lt;IMX95_PAD_XSPI1_DATA5__FLEXSPI1_A_DATA_BIT5		0x3fe&gt;,</div><div class='add'>+			&lt;IMX95_PAD_XSPI1_DATA6__FLEXSPI1_A_DATA_BIT6		0x3fe&gt;,</div><div class='add'>+			&lt;IMX95_PAD_XSPI1_DATA7__FLEXSPI1_A_DATA_BIT7		0x3fe&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexspi1_reset: flexspi1-reset-grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;IMX95_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11			0x3fe&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_hp: hpgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;IMX95_PAD_GPIO_IO11__GPIO2_IO_BIT11			0x31e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c4_pcal6408: i2c4pcal6498grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;IMX95_PAD_GPIO_IO18__GPIO2_IO_BIT18			0x31e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c7_pcal6524: i2c7pcal6524grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;IMX95_PAD_GPIO_IO36__GPIO5_IO_BIT16			0x31e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c4: lpi2c4grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;IMX95_PAD_GPIO_IO30__LPI2C4_SDA			0x40000b9e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_GPIO_IO31__LPI2C4_SCL			0x40000b9e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c5: lpi2c5grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;IMX95_PAD_GPIO_IO22__LPI2C5_SDA			0x40000b9e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_GPIO_IO23__LPI2C5_SCL			0x40000b9e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c6: lpi2c6grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;IMX95_PAD_GPIO_IO02__LPI2C6_SDA			0x40000b9e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_GPIO_IO03__LPI2C6_SCL			0x40000b9e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c7: lpi2c7grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;IMX95_PAD_GPIO_IO08__LPI2C7_SDA			0x40000b9e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_GPIO_IO09__LPI2C7_SCL			0x40000b9e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcal6416: pcal6416grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;IMX95_PAD_CCM_CLKO3__GPIO4_IO_BIT28			0x31e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie0: pcie0grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B	0x4000031e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie1: pcie1grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B	0x4000031e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pdm: pdmgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;IMX95_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK				0x31e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_BIT0	0x31e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7		0x31e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai1: sai1grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;IMX95_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_RX_DATA_BIT0	0x31e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SAI1_TXC__AONMIX_TOP_SAI1_TX_BCLK		0x31e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_TX_SYNC		0x31e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SAI1_TXD0__AONMIX_TOP_SAI1_TX_DATA_BIT0	0x31e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai2: sai2grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_SAI2_RX_BCLK		0x31e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_ENET2_MDC__NETCMIX_TOP_SAI2_RX_SYNC		0x31e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_ENET2_TD3__NETCMIX_TOP_SAI2_RX_DATA_BIT0	0x31e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_ENET2_TD2__NETCMIX_TOP_SAI2_RX_DATA_BIT1	0x31e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_ENET2_TXC__NETCMIX_TOP_SAI2_TX_BCLK		0x31e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_SAI2_TX_SYNC	0x31e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_SAI2_TX_DATA_BIT0	0x31e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_ENET2_RXC__NETCMIX_TOP_SAI2_TX_DATA_BIT1	0x31e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_ENET2_RD0__NETCMIX_TOP_SAI2_TX_DATA_BIT2	0x31e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_ENET2_RD1__NETCMIX_TOP_SAI2_TX_DATA_BIT3	0x31e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_ENET2_RD2__NETCMIX_TOP_SAI2_MCLK		0x31e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai3: sai3grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;IMX95_PAD_GPIO_IO17__SAI3_MCLK			0x31e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK		0x31e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC		0x31e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0		0x31e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0		0x31e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_tpm6: tpm6grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;IMX95_PAD_GPIO_IO19__TPM6_CH2			0x51e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_typec: typecgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14		0x31e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX	0x31e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX	0x31e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;IMX95_PAD_SD1_CLK__USDHC1_CLK			0x158e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD1_CMD__USDHC1_CMD			0x138e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD1_DATA0__USDHC1_DATA0		0x138e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD1_DATA1__USDHC1_DATA1		0x138e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD1_DATA2__USDHC1_DATA2		0x138e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD1_DATA3__USDHC1_DATA3		0x138e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD1_DATA4__USDHC1_DATA4		0x138e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD1_DATA5__USDHC1_DATA5		0x138e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD1_DATA6__USDHC1_DATA6		0x138e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD1_DATA7__USDHC1_DATA7		0x138e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD1_STROBE__USDHC1_STROBE		0x158e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;IMX95_PAD_SD1_CLK__USDHC1_CLK			0x158e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD1_CMD__USDHC1_CMD			0x138e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD1_DATA0__USDHC1_DATA0		0x138e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD1_DATA1__USDHC1_DATA1		0x138e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD1_DATA2__USDHC1_DATA2		0x138e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD1_DATA3__USDHC1_DATA3		0x138e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD1_DATA4__USDHC1_DATA4		0x138e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD1_DATA5__USDHC1_DATA5		0x138e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD1_DATA6__USDHC1_DATA6		0x138e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD1_DATA7__USDHC1_DATA7		0x138e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD1_STROBE__USDHC1_STROBE		0x158e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;IMX95_PAD_SD1_CLK__USDHC1_CLK			0x15fe&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD1_CMD__USDHC1_CMD			0x13fe&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD1_DATA0__USDHC1_DATA0		0x13fe&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD1_DATA1__USDHC1_DATA1		0x13fe&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD1_DATA2__USDHC1_DATA2		0x13fe&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD1_DATA3__USDHC1_DATA3		0x13fe&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD1_DATA4__USDHC1_DATA4		0x13fe&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD1_DATA5__USDHC1_DATA5		0x13fe&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD1_DATA6__USDHC1_DATA6		0x13fe&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD1_DATA7__USDHC1_DATA7		0x13fe&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD1_STROBE__USDHC1_STROBE		0x15fe&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0		0x31e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;IMX95_PAD_SD2_CLK__USDHC2_CLK			0x158e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD2_CMD__USDHC2_CMD			0x138e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD2_DATA0__USDHC2_DATA0		0x138e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD2_DATA1__USDHC2_DATA1		0x138e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD2_DATA2__USDHC2_DATA2		0x138e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD2_DATA3__USDHC2_DATA3		0x138e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT		0x51e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;IMX95_PAD_SD2_CLK__USDHC2_CLK			0x158e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD2_CMD__USDHC2_CMD			0x138e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD2_DATA0__USDHC2_DATA0		0x138e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD2_DATA1__USDHC2_DATA1		0x138e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD2_DATA2__USDHC2_DATA2		0x138e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD2_DATA3__USDHC2_DATA3		0x138e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT		0x51e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;IMX95_PAD_SD2_CLK__USDHC2_CLK			0x15fe&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD2_CMD__USDHC2_CMD			0x13fe&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD2_DATA0__USDHC2_DATA0		0x13fe&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD2_DATA1__USDHC2_DATA1		0x13fe&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD2_DATA2__USDHC2_DATA2		0x13fe&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD2_DATA3__USDHC2_DATA3		0x13fe&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT		0x51e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins =</div><div class='add'>+			&lt;IMX95_PAD_SD3_CLK__USDHC3_CLK			0x158e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD3_CMD__USDHC3_CMD			0x138e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD3_DATA0__USDHC3_DATA0		0x138e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD3_DATA1__USDHC3_DATA1		0x138e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD3_DATA2__USDHC3_DATA2		0x138e&gt;,</div><div class='add'>+			&lt;IMX95_PAD_SD3_DATA3__USDHC3_DATA3		0x138e&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx95-clock.h b/arch/arm64/boot/dts/freescale/imx95-clock.h<br/>new file mode 100644<br/>index 000000000000..e1f91203e794<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx95-clock.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx95-clock.h</a></div><div class='hunk'>@@ -0,0 +1,187 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __CLOCK_IMX95_H</div><div class='add'>+#define __CLOCK_IMX95_H</div><div class='add'>+</div><div class='add'>+/* The index should match i.MX95 SCMI Firmware */</div><div class='add'>+#define IMX95_CLK_32K                       1</div><div class='add'>+#define IMX95_CLK_24M                       2</div><div class='add'>+#define IMX95_CLK_FRO                       3</div><div class='add'>+#define IMX95_CLK_SYSPLL1_VCO               4</div><div class='add'>+#define IMX95_CLK_SYSPLL1_PFD0_UNGATED      5</div><div class='add'>+#define IMX95_CLK_SYSPLL1_PFD0              6</div><div class='add'>+#define IMX95_CLK_SYSPLL1_PFD0_DIV2         7</div><div class='add'>+#define IMX95_CLK_SYSPLL1_PFD1_UNGATED      8</div><div class='add'>+#define IMX95_CLK_SYSPLL1_PFD1              9</div><div class='add'>+#define IMX95_CLK_SYSPLL1_PFD1_DIV2         10</div><div class='add'>+#define IMX95_CLK_SYSPLL1_PFD2_UNGATED      11</div><div class='add'>+#define IMX95_CLK_SYSPLL1_PFD2              12</div><div class='add'>+#define IMX95_CLK_SYSPLL1_PFD2_DIV2         13</div><div class='add'>+#define IMX95_CLK_AUDIOPLL1_VCO             14</div><div class='add'>+#define IMX95_CLK_AUDIOPLL1                 15</div><div class='add'>+#define IMX95_CLK_AUDIOPLL2_VCO             16</div><div class='add'>+#define IMX95_CLK_AUDIOPLL2                 17</div><div class='add'>+#define IMX95_CLK_VIDEOPLL1_VCO             18</div><div class='add'>+#define IMX95_CLK_VIDEOPLL1                 19</div><div class='add'>+#define IMX95_CLK_RESERVED20                20</div><div class='add'>+#define IMX95_CLK_RESERVED21                21</div><div class='add'>+#define IMX95_CLK_RESERVED22                22</div><div class='add'>+#define IMX95_CLK_RESERVED23                23</div><div class='add'>+#define IMX95_CLK_ARMPLL_VCO                24</div><div class='add'>+#define IMX95_CLK_ARMPLL_PFD0_UNGATED       25</div><div class='add'>+#define IMX95_CLK_ARMPLL_PFD0               26</div><div class='add'>+#define IMX95_CLK_ARMPLL_PFD1_UNGATED       27</div><div class='add'>+#define IMX95_CLK_ARMPLL_PFD1               28</div><div class='add'>+#define IMX95_CLK_ARMPLL_PFD2_UNGATED       29</div><div class='add'>+#define IMX95_CLK_ARMPLL_PFD2               30</div><div class='add'>+#define IMX95_CLK_ARMPLL_PFD3_UNGATED       31</div><div class='add'>+#define IMX95_CLK_ARMPLL_PFD3               32</div><div class='add'>+#define IMX95_CLK_DRAMPLL_VCO               33</div><div class='add'>+#define IMX95_CLK_DRAMPLL                   34</div><div class='add'>+#define IMX95_CLK_HSIOPLL_VCO               35</div><div class='add'>+#define IMX95_CLK_HSIOPLL                   36</div><div class='add'>+#define IMX95_CLK_LDBPLL_VCO                37</div><div class='add'>+#define IMX95_CLK_LDBPLL                    38</div><div class='add'>+#define IMX95_CLK_EXT1                      39</div><div class='add'>+#define IMX95_CLK_EXT2                      40</div><div class='add'>+</div><div class='add'>+#define IMX95_CCM_NUM_CLK_SRC               41</div><div class='add'>+</div><div class='add'>+#define IMX95_CLK_ADC                      (IMX95_CCM_NUM_CLK_SRC + 0)</div><div class='add'>+#define IMX95_CLK_TMU                      (IMX95_CCM_NUM_CLK_SRC + 1)</div><div class='add'>+#define IMX95_CLK_BUSAON                   (IMX95_CCM_NUM_CLK_SRC + 2)</div><div class='add'>+#define IMX95_CLK_CAN1                     (IMX95_CCM_NUM_CLK_SRC + 3)</div><div class='add'>+#define IMX95_CLK_I3C1                     (IMX95_CCM_NUM_CLK_SRC + 4)</div><div class='add'>+#define IMX95_CLK_I3C1SLOW                 (IMX95_CCM_NUM_CLK_SRC + 5)</div><div class='add'>+#define IMX95_CLK_LPI2C1                   (IMX95_CCM_NUM_CLK_SRC + 6)</div><div class='add'>+#define IMX95_CLK_LPI2C2                   (IMX95_CCM_NUM_CLK_SRC + 7)</div><div class='add'>+#define IMX95_CLK_LPSPI1                   (IMX95_CCM_NUM_CLK_SRC + 8)</div><div class='add'>+#define IMX95_CLK_LPSPI2                   (IMX95_CCM_NUM_CLK_SRC + 9)</div><div class='add'>+#define IMX95_CLK_LPTMR1                   (IMX95_CCM_NUM_CLK_SRC + 10)</div><div class='add'>+#define IMX95_CLK_LPUART1                  (IMX95_CCM_NUM_CLK_SRC + 11)</div><div class='add'>+#define IMX95_CLK_LPUART2                  (IMX95_CCM_NUM_CLK_SRC + 12)</div><div class='add'>+#define IMX95_CLK_M33                      (IMX95_CCM_NUM_CLK_SRC + 13)</div><div class='add'>+#define IMX95_CLK_M33SYSTICK               (IMX95_CCM_NUM_CLK_SRC + 14)</div><div class='add'>+#define IMX95_CLK_MQS1                     (IMX95_CCM_NUM_CLK_SRC + 15)</div><div class='add'>+#define IMX95_CLK_PDM                      (IMX95_CCM_NUM_CLK_SRC + 16)</div><div class='add'>+#define IMX95_CLK_SAI1                     (IMX95_CCM_NUM_CLK_SRC + 17)</div><div class='add'>+#define IMX95_CLK_SENTINEL                 (IMX95_CCM_NUM_CLK_SRC + 18)</div><div class='add'>+#define IMX95_CLK_TPM2                     (IMX95_CCM_NUM_CLK_SRC + 19)</div><div class='add'>+#define IMX95_CLK_TSTMR1                   (IMX95_CCM_NUM_CLK_SRC + 20)</div><div class='add'>+#define IMX95_CLK_CAMAPB                   (IMX95_CCM_NUM_CLK_SRC + 21)</div><div class='add'>+#define IMX95_CLK_CAMAXI                   (IMX95_CCM_NUM_CLK_SRC + 22)</div><div class='add'>+#define IMX95_CLK_CAMCM0                   (IMX95_CCM_NUM_CLK_SRC + 23)</div><div class='add'>+#define IMX95_CLK_CAMISI                   (IMX95_CCM_NUM_CLK_SRC + 24)</div><div class='add'>+#define IMX95_CLK_MIPIPHYCFG               (IMX95_CCM_NUM_CLK_SRC + 25)</div><div class='add'>+#define IMX95_CLK_MIPIPHYPLLBYPASS         (IMX95_CCM_NUM_CLK_SRC + 26)</div><div class='add'>+#define IMX95_CLK_MIPIPHYPLLREF            (IMX95_CCM_NUM_CLK_SRC + 27)</div><div class='add'>+#define IMX95_CLK_MIPITESTBYTE             (IMX95_CCM_NUM_CLK_SRC + 28)</div><div class='add'>+#define IMX95_CLK_A55                      (IMX95_CCM_NUM_CLK_SRC + 29)</div><div class='add'>+#define IMX95_CLK_A55MTRBUS                (IMX95_CCM_NUM_CLK_SRC + 30)</div><div class='add'>+#define IMX95_CLK_A55PERIPH                (IMX95_CCM_NUM_CLK_SRC + 31)</div><div class='add'>+#define IMX95_CLK_DRAMALT                  (IMX95_CCM_NUM_CLK_SRC + 32)</div><div class='add'>+#define IMX95_CLK_DRAMAPB                  (IMX95_CCM_NUM_CLK_SRC + 33)</div><div class='add'>+#define IMX95_CLK_DISPAPB                  (IMX95_CCM_NUM_CLK_SRC + 34)</div><div class='add'>+#define IMX95_CLK_DISPAXI                  (IMX95_CCM_NUM_CLK_SRC + 35)</div><div class='add'>+#define IMX95_CLK_DISPDP                   (IMX95_CCM_NUM_CLK_SRC + 36)</div><div class='add'>+#define IMX95_CLK_DISPOCRAM                (IMX95_CCM_NUM_CLK_SRC + 37)</div><div class='add'>+#define IMX95_CLK_DISPUSB31                (IMX95_CCM_NUM_CLK_SRC + 38)</div><div class='add'>+#define IMX95_CLK_DISP1PIX                 (IMX95_CCM_NUM_CLK_SRC + 39)</div><div class='add'>+#define IMX95_CLK_DISP2PIX                 (IMX95_CCM_NUM_CLK_SRC + 40)</div><div class='add'>+#define IMX95_CLK_DISP3PIX                 (IMX95_CCM_NUM_CLK_SRC + 41)</div><div class='add'>+#define IMX95_CLK_GPUAPB                   (IMX95_CCM_NUM_CLK_SRC + 42)</div><div class='add'>+#define IMX95_CLK_GPU                      (IMX95_CCM_NUM_CLK_SRC + 43)</div><div class='add'>+#define IMX95_CLK_HSIOACSCAN480M           (IMX95_CCM_NUM_CLK_SRC + 44)</div><div class='add'>+#define IMX95_CLK_HSIOACSCAN80M            (IMX95_CCM_NUM_CLK_SRC + 45)</div><div class='add'>+#define IMX95_CLK_HSIO                     (IMX95_CCM_NUM_CLK_SRC + 46)</div><div class='add'>+#define IMX95_CLK_HSIOPCIEAUX              (IMX95_CCM_NUM_CLK_SRC + 47)</div><div class='add'>+#define IMX95_CLK_HSIOPCIETEST160M         (IMX95_CCM_NUM_CLK_SRC + 48)</div><div class='add'>+#define IMX95_CLK_HSIOPCIETEST400M         (IMX95_CCM_NUM_CLK_SRC + 49)</div><div class='add'>+#define IMX95_CLK_HSIOPCIETEST500M         (IMX95_CCM_NUM_CLK_SRC + 50)</div><div class='add'>+#define IMX95_CLK_HSIOUSBTEST50M           (IMX95_CCM_NUM_CLK_SRC + 51)</div><div class='add'>+#define IMX95_CLK_HSIOUSBTEST60M           (IMX95_CCM_NUM_CLK_SRC + 52)</div><div class='add'>+#define IMX95_CLK_BUSM7                    (IMX95_CCM_NUM_CLK_SRC + 53)</div><div class='add'>+#define IMX95_CLK_M7                       (IMX95_CCM_NUM_CLK_SRC + 54)</div><div class='add'>+#define IMX95_CLK_M7SYSTICK                (IMX95_CCM_NUM_CLK_SRC + 55)</div><div class='add'>+#define IMX95_CLK_BUSNETCMIX               (IMX95_CCM_NUM_CLK_SRC + 56)</div><div class='add'>+#define IMX95_CLK_ENET                     (IMX95_CCM_NUM_CLK_SRC + 57)</div><div class='add'>+#define IMX95_CLK_ENETPHYTEST200M          (IMX95_CCM_NUM_CLK_SRC + 58)</div><div class='add'>+#define IMX95_CLK_ENETPHYTEST500M          (IMX95_CCM_NUM_CLK_SRC + 59)</div><div class='add'>+#define IMX95_CLK_ENETPHYTEST667M          (IMX95_CCM_NUM_CLK_SRC + 60)</div><div class='add'>+#define IMX95_CLK_ENETREF                  (IMX95_CCM_NUM_CLK_SRC + 61)</div><div class='add'>+#define IMX95_CLK_ENETTIMER1               (IMX95_CCM_NUM_CLK_SRC + 62)</div><div class='add'>+#define IMX95_CLK_MQS2                     (IMX95_CCM_NUM_CLK_SRC + 63)</div><div class='add'>+#define IMX95_CLK_SAI2                     (IMX95_CCM_NUM_CLK_SRC + 64)</div><div class='add'>+#define IMX95_CLK_NOCAPB                   (IMX95_CCM_NUM_CLK_SRC + 65)</div><div class='add'>+#define IMX95_CLK_NOC                      (IMX95_CCM_NUM_CLK_SRC + 66)</div><div class='add'>+#define IMX95_CLK_NPUAPB                   (IMX95_CCM_NUM_CLK_SRC + 67)</div><div class='add'>+#define IMX95_CLK_NPU                      (IMX95_CCM_NUM_CLK_SRC + 68)</div><div class='add'>+#define IMX95_CLK_CCMCKO1                  (IMX95_CCM_NUM_CLK_SRC + 69)</div><div class='add'>+#define IMX95_CLK_CCMCKO2                  (IMX95_CCM_NUM_CLK_SRC + 70)</div><div class='add'>+#define IMX95_CLK_CCMCKO3                  (IMX95_CCM_NUM_CLK_SRC + 71)</div><div class='add'>+#define IMX95_CLK_CCMCKO4                  (IMX95_CCM_NUM_CLK_SRC + 72)</div><div class='add'>+#define IMX95_CLK_VPUAPB                   (IMX95_CCM_NUM_CLK_SRC + 73)</div><div class='add'>+#define IMX95_CLK_VPU                      (IMX95_CCM_NUM_CLK_SRC + 74)</div><div class='add'>+#define IMX95_CLK_VPUDSP                   (IMX95_CCM_NUM_CLK_SRC + 75)</div><div class='add'>+#define IMX95_CLK_VPUJPEG                  (IMX95_CCM_NUM_CLK_SRC + 76)</div><div class='add'>+#define IMX95_CLK_AUDIOXCVR                (IMX95_CCM_NUM_CLK_SRC + 77)</div><div class='add'>+#define IMX95_CLK_BUSWAKEUP                (IMX95_CCM_NUM_CLK_SRC + 78)</div><div class='add'>+#define IMX95_CLK_CAN2                     (IMX95_CCM_NUM_CLK_SRC + 79)</div><div class='add'>+#define IMX95_CLK_CAN3                     (IMX95_CCM_NUM_CLK_SRC + 80)</div><div class='add'>+#define IMX95_CLK_CAN4                     (IMX95_CCM_NUM_CLK_SRC + 81)</div><div class='add'>+#define IMX95_CLK_CAN5                     (IMX95_CCM_NUM_CLK_SRC + 82)</div><div class='add'>+#define IMX95_CLK_FLEXIO1                  (IMX95_CCM_NUM_CLK_SRC + 83)</div><div class='add'>+#define IMX95_CLK_FLEXIO2                  (IMX95_CCM_NUM_CLK_SRC + 84)</div><div class='add'>+#define IMX95_CLK_FLEXSPI1                 (IMX95_CCM_NUM_CLK_SRC + 85)</div><div class='add'>+#define IMX95_CLK_I3C2                     (IMX95_CCM_NUM_CLK_SRC + 86)</div><div class='add'>+#define IMX95_CLK_I3C2SLOW                 (IMX95_CCM_NUM_CLK_SRC + 87)</div><div class='add'>+#define IMX95_CLK_LPI2C3                   (IMX95_CCM_NUM_CLK_SRC + 88)</div><div class='add'>+#define IMX95_CLK_LPI2C4                   (IMX95_CCM_NUM_CLK_SRC + 89)</div><div class='add'>+#define IMX95_CLK_LPI2C5                   (IMX95_CCM_NUM_CLK_SRC + 90)</div><div class='add'>+#define IMX95_CLK_LPI2C6                   (IMX95_CCM_NUM_CLK_SRC + 91)</div><div class='add'>+#define IMX95_CLK_LPI2C7                   (IMX95_CCM_NUM_CLK_SRC + 92)</div><div class='add'>+#define IMX95_CLK_LPI2C8                   (IMX95_CCM_NUM_CLK_SRC + 93)</div><div class='add'>+#define IMX95_CLK_LPSPI3                   (IMX95_CCM_NUM_CLK_SRC + 94)</div><div class='add'>+#define IMX95_CLK_LPSPI4                   (IMX95_CCM_NUM_CLK_SRC + 95)</div><div class='add'>+#define IMX95_CLK_LPSPI5                   (IMX95_CCM_NUM_CLK_SRC + 96)</div><div class='add'>+#define IMX95_CLK_LPSPI6                   (IMX95_CCM_NUM_CLK_SRC + 97)</div><div class='add'>+#define IMX95_CLK_LPSPI7                   (IMX95_CCM_NUM_CLK_SRC + 98)</div><div class='add'>+#define IMX95_CLK_LPSPI8                   (IMX95_CCM_NUM_CLK_SRC + 99)</div><div class='add'>+#define IMX95_CLK_LPTMR2                   (IMX95_CCM_NUM_CLK_SRC + 100)</div><div class='add'>+#define IMX95_CLK_LPUART3                  (IMX95_CCM_NUM_CLK_SRC + 101)</div><div class='add'>+#define IMX95_CLK_LPUART4                  (IMX95_CCM_NUM_CLK_SRC + 102)</div><div class='add'>+#define IMX95_CLK_LPUART5                  (IMX95_CCM_NUM_CLK_SRC + 103)</div><div class='add'>+#define IMX95_CLK_LPUART6                  (IMX95_CCM_NUM_CLK_SRC + 104)</div><div class='add'>+#define IMX95_CLK_LPUART7                  (IMX95_CCM_NUM_CLK_SRC + 105)</div><div class='add'>+#define IMX95_CLK_LPUART8                  (IMX95_CCM_NUM_CLK_SRC + 106)</div><div class='add'>+#define IMX95_CLK_SAI3                     (IMX95_CCM_NUM_CLK_SRC + 107)</div><div class='add'>+#define IMX95_CLK_SAI4                     (IMX95_CCM_NUM_CLK_SRC + 108)</div><div class='add'>+#define IMX95_CLK_SAI5                     (IMX95_CCM_NUM_CLK_SRC + 109)</div><div class='add'>+#define IMX95_CLK_SPDIF                    (IMX95_CCM_NUM_CLK_SRC + 110)</div><div class='add'>+#define IMX95_CLK_SWOTRACE                 (IMX95_CCM_NUM_CLK_SRC + 111)</div><div class='add'>+#define IMX95_CLK_TPM4                     (IMX95_CCM_NUM_CLK_SRC + 112)</div><div class='add'>+#define IMX95_CLK_TPM5                     (IMX95_CCM_NUM_CLK_SRC + 113)</div><div class='add'>+#define IMX95_CLK_TPM6                     (IMX95_CCM_NUM_CLK_SRC + 114)</div><div class='add'>+#define IMX95_CLK_TSTMR2                   (IMX95_CCM_NUM_CLK_SRC + 115)</div><div class='add'>+#define IMX95_CLK_USBPHYBURUNIN            (IMX95_CCM_NUM_CLK_SRC + 116)</div><div class='add'>+#define IMX95_CLK_USDHC1                   (IMX95_CCM_NUM_CLK_SRC + 117)</div><div class='add'>+#define IMX95_CLK_USDHC2                   (IMX95_CCM_NUM_CLK_SRC + 118)</div><div class='add'>+#define IMX95_CLK_USDHC3                   (IMX95_CCM_NUM_CLK_SRC + 119)</div><div class='add'>+#define IMX95_CLK_V2XPK                    (IMX95_CCM_NUM_CLK_SRC + 120)</div><div class='add'>+#define IMX95_CLK_WAKEUPAXI                (IMX95_CCM_NUM_CLK_SRC + 121)</div><div class='add'>+#define IMX95_CLK_XSPISLVROOT              (IMX95_CCM_NUM_CLK_SRC + 122)</div><div class='add'>+#define IMX95_CLK_SEL_EXT                  (IMX95_CCM_NUM_CLK_SRC + 123 + 0)</div><div class='add'>+#define IMX95_CLK_SEL_A55C0                (IMX95_CCM_NUM_CLK_SRC + 123 + 1)</div><div class='add'>+#define IMX95_CLK_SEL_A55C1                (IMX95_CCM_NUM_CLK_SRC + 123 + 2)</div><div class='add'>+#define IMX95_CLK_SEL_A55C2                (IMX95_CCM_NUM_CLK_SRC + 123 + 3)</div><div class='add'>+#define IMX95_CLK_SEL_A55C3                (IMX95_CCM_NUM_CLK_SRC + 123 + 4)</div><div class='add'>+#define IMX95_CLK_SEL_A55C4                (IMX95_CCM_NUM_CLK_SRC + 123 + 5)</div><div class='add'>+#define IMX95_CLK_SEL_A55C5                (IMX95_CCM_NUM_CLK_SRC + 123 + 6)</div><div class='add'>+#define IMX95_CLK_SEL_A55P                 (IMX95_CCM_NUM_CLK_SRC + 123 + 7)</div><div class='add'>+#define IMX95_CLK_SEL_DRAM                 (IMX95_CCM_NUM_CLK_SRC + 123 + 8)</div><div class='add'>+#define IMX95_CLK_SEL_TEMPSENSE            (IMX95_CCM_NUM_CLK_SRC + 123 + 9)</div><div class='add'>+</div><div class='add'>+#endif	/* __CLOCK_IMX95_H */</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx95-libra-rdk-fpsc.dts b/arch/arm64/boot/dts/freescale/imx95-libra-rdk-fpsc.dts<br/>new file mode 100644<br/>index 000000000000..26c2df9b1b60<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx95-libra-rdk-fpsc.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx95-libra-rdk-fpsc.dts</a></div><div class='hunk'>@@ -0,0 +1,318 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2025 PHYTEC Messtechnik GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/leds/leds-pca9532.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pwm/pwm.h&gt;</div><div class='add'>+</div><div class='add'>+#include "imx95-phycore-fpsc.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "phytec,imx95-libra-rdk-fpsc",</div><div class='add'>+		"phytec,imx95-phycore-fpsc", "fsl,imx95";</div><div class='add'>+	model = "PHYTEC Libra i.MX95 RDK FPSC";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		can1 = &amp;flexcan2;</div><div class='add'>+		can2 = &amp;flexcan1;</div><div class='add'>+		ethernet0 = &amp;enetc_port0;</div><div class='add'>+		serial0 = &amp;lpuart7;</div><div class='add'>+		serial1 = &amp;lpuart8;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;lpuart7;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	backlight_lvds0: backlight0 {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_lvds0&gt;;</div><div class='add'>+		power-supply = &lt;&amp;reg_vdd_12v0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	transceiver1: can-phy {</div><div class='add'>+		compatible = "ti,tcan1043";</div><div class='add'>+		#phy-cells = &lt;0&gt;;</div><div class='add'>+		max-bitrate = &lt;8000000&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;gpio_expander 10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	transceiver2: can-phy {</div><div class='add'>+		compatible = "ti,tcan1043";</div><div class='add'>+		#phy-cells = &lt;0&gt;;</div><div class='add'>+		max-bitrate = &lt;8000000&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;gpio_expander 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	panel0_lvds: panel-lvds0 {</div><div class='add'>+		backlight = &lt;&amp;backlight_lvds0&gt;;</div><div class='add'>+		power-supply = &lt;&amp;reg_vdd_3v3&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vdd_12v0: regulator-vdd-12v0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-max-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-name = "VDD_12V0";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vdd_1v8: regulator-vdd-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-name = "VDD_1V8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vdd_3v3: regulator-vdd-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "VDD_3V3";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vdd_5v0: regulator-vdd-5v0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-name = "VDD_5V0";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;enetc_port0 {</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;enetc_port2 {</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy2&gt;;</div><div class='add'>+	phy-mode = "10gbase-r";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* CAN FD */</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	phys = &lt;&amp;transceiver1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan2 {</div><div class='add'>+	phys = &lt;&amp;transceiver2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SPI-NOR */</div><div class='add'>+&amp;flexspi1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexspi&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	spi_nor: flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;166000000&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;4&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_vdd_1v8&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio2 {</div><div class='add'>+	gpio-line-names = "", "", "", "", "",</div><div class='add'>+			  "", "", "", "", "",</div><div class='add'>+			  "", "", "", "", "",</div><div class='add'>+			  "", "RGMII2_nINT", "GPIO4", "RTC_INT", "",</div><div class='add'>+			  "LVDS1_BL_EN";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c1 {</div><div class='add'>+	temperature-sensor@4f {</div><div class='add'>+		compatible = "nxp,p3t1755";</div><div class='add'>+		reg = &lt;0x4f&gt;;</div><div class='add'>+		vs-supply = &lt;&amp;reg_vdd_1v8&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	leds@62 {</div><div class='add'>+		compatible = "nxp,pca9533";</div><div class='add'>+		reg = &lt;0x62&gt;;</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			type = &lt;PCA9532_TYPE_LED&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-2 {</div><div class='add'>+			type = &lt;PCA9532_TYPE_LED&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-3 {</div><div class='add'>+			type = &lt;PCA9532_TYPE_LED&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c4 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	gpio_expander: gpio@20 {</div><div class='add'>+		compatible = "ti,tca6416";</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio2&gt;;</div><div class='add'>+		interrupts = &lt;17 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		gpio-line-names = "CSI1_CTRL1", "CSI1_CTRL2", "CSI1_CTRL3",</div><div class='add'>+				  "CSI1_CTRL4", "CSI2_CTRL1", "CSI2_CTRL2",</div><div class='add'>+				  "CSI2_CTRL3", "CSI2_CTRL4", "CLK_EN_AV",</div><div class='add'>+				  "nCAN2_EN", "nCAN1_EN", "PCIE1_nWAKE",</div><div class='add'>+				  "PCIE2_nWAKE", "PCIE2_nALERT_3V3",</div><div class='add'>+				  "UART1_BT_RS_SEL", "UART1_RS232_485_SEL";</div><div class='add'>+		vcc-supply = &lt;&amp;reg_vdd_1v8&gt;;</div><div class='add'>+</div><div class='add'>+		uart1_bt_rs_sel: bt-rs-hog {</div><div class='add'>+			gpios = &lt;14 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			gpio-hog;</div><div class='add'>+			line-name = "UART1_BT_RS_SEL";</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c5 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	eeprom@51 {</div><div class='add'>+		compatible = "atmel,24c02";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_vdd_1v8&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Used for M33 debug */</div><div class='add'>+&amp;lpuart2 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpuart2&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* A-55 debug UART */</div><div class='add'>+&amp;lpuart7 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* RS232/RS485/BT */</div><div class='add'>+&amp;lpuart8 {</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;netc_emdio { /* RGMII2 */</div><div class='add'>+	ethphy0: ethernet-phy@1 {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+		reg = &lt;0x1&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio2&gt;;</div><div class='add'>+		interrupts = &lt;16 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		enet-phy-lane-no-swap;</div><div class='add'>+		ti,clk-output-sel = &lt;DP83867_CLK_O_SEL_OFF&gt;;</div><div class='add'>+		ti,fifo-depth = &lt;DP83867_PHYCR_FIFO_DEPTH_4_B_NIB&gt;;</div><div class='add'>+		ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_1_50_NS&gt;;</div><div class='add'>+		ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_2_00_NS&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ethphy2: ethernet-phy@8 {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+		reg = &lt;0x8&gt;;</div><div class='add'>+		max-speed = &lt;10000&gt;; /* 10Gbit/s */</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	reset-gpio = &lt;&amp;gpio1 10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vpcie-supply = &lt;&amp;reg_vdd_3v3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie1 {</div><div class='add'>+	reset-gpio = &lt;&amp;gpio1 14 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vpcie-supply = &lt;&amp;reg_vdd_3v3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;rv3028 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_rtc&gt;;</div><div class='add'>+	interrupt-parent = &lt;&amp;gpio2&gt;;</div><div class='add'>+	interrupts = &lt;18 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	aux-voltage-chargeable = &lt;1&gt;;</div><div class='add'>+	wakeup-source;</div><div class='add'>+	trickle-resistor-ohms = &lt;3000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;scmi_iomuxc {</div><div class='add'>+	pinctrl_lpuart2: lpuart2grp { /* FPSC proprietary */</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART2_TX	0x31e</div><div class='add'>+			IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART2_RX	0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lvds0: lvds0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_GPIO_IO20__GPIO2_IO_BIT20	0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_rtc: rtcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_GPIO_IO18__GPIO2_IO_BIT18	0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_tpm4: tpm4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_GPIO_IO21__TPM4_CH1	0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tpm4 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_tpm4&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3 {</div><div class='add'>+	fsl,over-current-active-low;</div><div class='add'>+	fsl,power-active-low;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_dwc3 {</div><div class='add'>+	dr_mode = "peripheral";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy {</div><div class='add'>+	vbus-supply = &lt;&amp;reg_vdd_5v0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* uSD Card */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx95-phycore-fpsc.dtsi b/arch/arm64/boot/dts/freescale/imx95-phycore-fpsc.dtsi<br/>new file mode 100644<br/>index 000000000000..7519d5bd06ba<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx95-phycore-fpsc.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx95-phycore-fpsc.dtsi</a></div><div class='hunk'>@@ -0,0 +1,656 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2025 PHYTEC Messtechnik GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/net/ti-dp83867.h&gt;</div><div class='add'>+#include "imx95.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "PHYTEC phyCORE-i.MX95 FPSC";</div><div class='add'>+	compatible = "phytec,imx95-phycore-fpsc", "fsl,imx95";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet1 = &amp;enetc_port1;</div><div class='add'>+		i2c1 = &amp;lpi2c2;</div><div class='add'>+		i2c2 = &amp;lpi2c5;</div><div class='add'>+		i2c3 = &amp;lpi2c3;</div><div class='add'>+		i2c4 = &amp;lpi2c4;</div><div class='add'>+		i2c5 = &amp;lpi2c1;</div><div class='add'>+		rtc0 = &amp;rv3028;</div><div class='add'>+		rtc1 = &amp;scmi_bbm;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@80000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x00000000 0x80000000 0x00000001 0x00000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_nvcc_aon: regulator-nvcc-aon {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-name = "VDD_IO";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-usdhc2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		off-on-delay-us = &lt;12000&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_usdhc2_vmmc&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "VDDSW_SD2";</div><div class='add'>+		gpio = &lt;&amp;gpio3 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		ranges;</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		linux,cma {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			alloc-ranges = &lt;0 0x80000000 0 0x7f000000&gt;;</div><div class='add'>+			reusable;</div><div class='add'>+			size = &lt;0 0x3c000000&gt;;</div><div class='add'>+			linux,cma-default;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;enetc_port0 { /* FPSC RGMII2 */</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_enetc0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;enetc_port1 {</div><div class='add'>+	phy-handle = &lt;&amp;ethphy1&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_enetc1&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan1 { /* FPSC CAN1 */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan1&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan2 { /* FPSC CAN2 */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan2&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexspi1 { /* FPSC QSPI */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexspi&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 { /* FPSC GPIO */</div><div class='add'>+	gpio-line-names = "", "", "", "", "GPIO2",</div><div class='add'>+			  "GPIO1", "", "", "", "",</div><div class='add'>+			  "PCIE1_nPERST", "USB1_PWR_EN", "GPIO3", "USB2_PWR_EN", "PCIE2_nPERST";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio1&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio2 { /* FPSC GPIO */</div><div class='add'>+	gpio-line-names = "", "", "", "", "",</div><div class='add'>+			  "", "", "", "", "",</div><div class='add'>+			  "", "", "", "", "",</div><div class='add'>+			  "", "RGMII2_nINT", "GPIO4";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio2&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio3 {</div><div class='add'>+	gpio-line-names = "", "", "", "", "",</div><div class='add'>+			  "", "", "SD2_RESET_B";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	gpio-line-names = "ENET2_nINT";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio5 {</div><div class='add'>+	gpio-line-names = "", "", "", "", "",</div><div class='add'>+			  "", "", "", "", "",</div><div class='add'>+			  "", "", "", "USB1_OC", "USB2_OC";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c1 { /* FPSC I2C5 */</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c1&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	dram_sense: temperature-sensor@48 {</div><div class='add'>+		compatible = "ti,tmp102";</div><div class='add'>+		reg = &lt;0x48&gt;;</div><div class='add'>+		#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	emmc_sense: temperature-sensor@49 {</div><div class='add'>+		compatible = "ti,tmp102";</div><div class='add'>+		reg = &lt;0x49&gt;;</div><div class='add'>+		#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ethphy_sense: temperature-sensor@4a {</div><div class='add'>+		compatible = "ti,tmp102";</div><div class='add'>+		reg = &lt;0x4a&gt;;</div><div class='add'>+		#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmic_sense: temperature-sensor@4b {</div><div class='add'>+		compatible = "ti,tmp102";</div><div class='add'>+		reg = &lt;0x4b&gt;;</div><div class='add'>+		#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* User EEPROM */</div><div class='add'>+	eeprom@50 {</div><div class='add'>+		compatible = "st,24c32", "atmel,24c32";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_nvcc_aon&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Factory EEPROM */</div><div class='add'>+	eeprom@51 {</div><div class='add'>+		compatible = "st,24c32", "atmel,24c32";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_nvcc_aon&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rv3028: rtc@52 {</div><div class='add'>+		compatible = "microcrystal,rv3028";</div><div class='add'>+		reg = &lt;0x52&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* User EEPROM ID page */</div><div class='add'>+	eeprom@58 {</div><div class='add'>+		compatible = "st,24c32", "atmel,24c32";</div><div class='add'>+		reg = &lt;0x58&gt;;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_nvcc_aon&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c2 { /* FPSC I2C1 */</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c2&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c3 { /* FPSC I2C3 */</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c3&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c4 { /* FPSC I2C4 */</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c4&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c5 { /* FPSC I2C2 */</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c5&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpspi3 { /* FPSC SPI2 */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpspi3&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpspi4 { /* FPSC SPI3 */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpspi4&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpspi7 { /* FPSC SPI1 */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpspi7&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart5 { /* FPSC UART2 */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpuart5&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart7 { /* FPSC UART3 */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpuart7&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart8 { /* FPSC UART1 */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpuart8&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;netc_blk_ctrl {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;netc_emdio { /* FPSC RGMII2 */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_emdio&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ethphy1: ethernet-phy@0 {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+		reg = &lt;0x0&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio4&gt;;</div><div class='add'>+		interrupts = &lt;0 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		enet-phy-lane-no-swap;</div><div class='add'>+		ti,clk-output-sel = &lt;DP83867_CLK_O_SEL_OFF&gt;;</div><div class='add'>+		ti,fifo-depth = &lt;DP83867_PHYCR_FIFO_DEPTH_4_B_NIB&gt;;</div><div class='add'>+		ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_2_00_NS&gt;;</div><div class='add'>+		ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_2_00_NS&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;netcmix_blk_ctrl {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0 { /* FPSC PCIE1 */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie1 { /* FPSC PCIE2 */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie1&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai5 {	/* FPSC SAI1 */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai5&gt;;</div><div class='add'>+	pintrc-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;scmi_iomuxc {</div><div class='add'>+	pinctrl_emdio: emdiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO	0x97e	/* RGMII2_MDIO */</div><div class='add'>+			IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC	0x502	/* RGMII2_MDC */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_enetc0: enetc0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_GPIO_IO16__GPIO2_IO_BIT16			0x31e	/* RGMII2_nINT */</div><div class='add'>+			IMX95_PAD_CCM_CLKO3__NETCMIX_TOP_NETC_TMR_1588_TRIG2	0x31e	/* RGMII2_EVENT_IN */</div><div class='add'>+			IMX95_PAD_CCM_CLKO4__NETCMIX_TOP_NETC_TMR_1588_PP2	0x31e	/* RGMII2_EVENT_OUT */</div><div class='add'>+</div><div class='add'>+			IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3		0x57e	/* RGMII2_TX_3 */</div><div class='add'>+			IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2		0x57e	/* RGMII2_TX_2 */</div><div class='add'>+			IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1		0x57e	/* RGMII2_TX_1 */</div><div class='add'>+			IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0		0x57e	/* RGMII2_TX_0 */</div><div class='add'>+			IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL	0x57e	/* RGMII2_TX_CTL */</div><div class='add'>+			IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK	0x58e	/* RGMII2_TXC */</div><div class='add'>+			IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3		0x57e	/* RGMII2_RX_3 */</div><div class='add'>+			IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2		0x57e	/* RGMII2_RX_2 */</div><div class='add'>+			IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1		0x57e	/* RGMII2_RX_1 */</div><div class='add'>+			IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0		0x57e	/* RGMII2_RX_0 */</div><div class='add'>+			IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL	0x57e	/* RGMII2_RX_CTL */</div><div class='add'>+			IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK	0x58e	/* RGMII2_RXC */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_enetc1: enetc1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_ENET1_MDC__GPIO4_IO_BIT0			0x31e</div><div class='add'>+			IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0		0x57e</div><div class='add'>+			IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1		0x57e</div><div class='add'>+			IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2		0x57e</div><div class='add'>+			IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3		0x57e</div><div class='add'>+			IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL	0x57e</div><div class='add'>+			IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK	0x58e</div><div class='add'>+			IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0		0x57e</div><div class='add'>+			IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1		0x57e</div><div class='add'>+			IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2		0x57e</div><div class='add'>+			IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3		0x57e</div><div class='add'>+			IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL	0x57e</div><div class='add'>+			IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK	0x58e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan1: flexcan1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX		0x51e	/* CAN1_TX */</div><div class='add'>+			IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX	0x51e	/* CAN1_RX */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan2: flexcan2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_GPIO_IO25__CAN2_TX	0x51e	/* CAN2_TX */</div><div class='add'>+			IMX95_PAD_GPIO_IO27__CAN2_RX	0x51e	/* CAN2_RX */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexspi: flexspigrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_XSPI1_SS0_B__FLEXSPI1_A_SS0_B		0x3fe	/* QSPI_CE */</div><div class='add'>+			IMX95_PAD_XSPI1_SCLK__FLEXSPI1_A_SCLK		0x3fe	/* QSPI_CLK */</div><div class='add'>+			IMX95_PAD_XSPI1_DATA0__FLEXSPI1_A_DATA_BIT0	0x3fe	/* QSPI_DATA_0 */</div><div class='add'>+			IMX95_PAD_XSPI1_DATA1__FLEXSPI1_A_DATA_BIT1	0x3fe	/* QSPI_DATA_1 */</div><div class='add'>+			IMX95_PAD_XSPI1_DATA2__FLEXSPI1_A_DATA_BIT2	0x3fe	/* QSPI_DATA_2 */</div><div class='add'>+			IMX95_PAD_XSPI1_DATA3__FLEXSPI1_A_DATA_BIT3	0x3fe	/* QSPI_DATA_3 */</div><div class='add'>+			IMX95_PAD_XSPI1_DQS__FLEXSPI1_A_DQS		0x3fe	/* QSPI_DQS */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio1: gpio1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_UART1_TXD__AONMIX_TOP_GPIO1_IO_BIT5	0x31e	/* GPIO1 */</div><div class='add'>+			IMX95_PAD_UART1_RXD__AONMIX_TOP_GPIO1_IO_BIT4	0x31e	/* GPIO2 */</div><div class='add'>+			IMX95_PAD_SAI1_TXC__AONMIX_TOP_GPIO1_IO_BIT12	0x31e	/* GPIO3 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio2: gpio2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_GPIO_IO17__GPIO2_IO_BIT17	0x31e	/* GPIO4 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c1: lpi2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_I2C1_SCL__AONMIX_TOP_LPI2C1_SCL	0x40000b9e	/* I2C5_SCL */</div><div class='add'>+			IMX95_PAD_I2C1_SDA__AONMIX_TOP_LPI2C1_SDA	0x40000b9e	/* I2C5_SDA */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c2: lpi2c2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA	0x40000b9e	/* I2C1_SDA_DNU */</div><div class='add'>+			IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL	0x40000b9e	/* I2C1_SCL_DNU */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c3: lpi2c3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e	/* I2C3_SDA */</div><div class='add'>+			IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e	/* I2C3_SCL */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c4: lpi2c4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40000b9e	/* I2C4_SDA */</div><div class='add'>+			IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40000b9e	/* I2C4_SDL */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c5: lpi2c5grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_GPIO_IO22__LPI2C5_SDA	0x40000b9e	/* I2C2_SDA */</div><div class='add'>+			IMX95_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e	/* I2C2_SCL */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpspi3: lpspi3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_GPIO_IO11__LPSPI3_SCK		0x51e	/* SPI2_SCLK */</div><div class='add'>+			IMX95_PAD_GPIO_IO10__LPSPI3_SOUT	0x51e	/* SPI2_MOSI */</div><div class='add'>+			IMX95_PAD_GPIO_IO09__LPSPI3_SIN		0x51e	/* SPI2_MISO */</div><div class='add'>+			IMX95_PAD_GPIO_IO08__LPSPI3_PCS0	0x51e	/* SPI2_CS */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpspi4: lpspi4grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_GPIO_IO21__LPSPI4_SCK		0x51e	/* SPI3_SCLK */</div><div class='add'>+			IMX95_PAD_GPIO_IO20__LPSPI4_SOUT	0x51e	/* SPI3_MOSI */</div><div class='add'>+			IMX95_PAD_GPIO_IO19__LPSPI4_SIN		0x51e	/* SPI3_MISO */</div><div class='add'>+			IMX95_PAD_GPIO_IO18__LPSPI4_PCS0	0x51e	/* SPI3_CS */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpspi7: lpspi7grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_GPIO_IO07__LPSPI7_SCK		0x51e	/* SPI1_SCLK */</div><div class='add'>+			IMX95_PAD_GPIO_IO06__LPSPI7_SOUT	0x51e	/* SPI1_MOSI */</div><div class='add'>+			IMX95_PAD_GPIO_IO05__LPSPI7_SIN		0x51e	/* SPI1_MISO */</div><div class='add'>+			IMX95_PAD_GPIO_IO04__LPSPI7_PCS0	0x51e	/* SPI1_CS */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpuart5: lpuart5grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_GPIO_IO01__LPUART5_RX		0x51e	/* UART2_RXD */</div><div class='add'>+			IMX95_PAD_GPIO_IO00__LPUART5_TX		0x51e	/* UART2_TXD */</div><div class='add'>+			IMX95_PAD_GPIO_IO03__LPUART5_RTS_B	0x51e	/* UART2_RTS */</div><div class='add'>+			IMX95_PAD_GPIO_IO02__LPUART5_CTS_B	0x51e	/* UART2_CTS */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpuart7: lpuart7grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_GPIO_IO37__LPUART7_RX	0x31e	/* UART3_RXD */</div><div class='add'>+			IMX95_PAD_GPIO_IO36__LPUART7_TX	0x31e	/* UART3_TXD */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpuart8: lpuart8grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_GPIO_IO13__LPUART8_RX		0x51e	/* UART1_RXD */</div><div class='add'>+			IMX95_PAD_GPIO_IO12__LPUART8_TX		0x51e	/* UART1_TXD */</div><div class='add'>+			IMX95_PAD_GPIO_IO15__LPUART8_RTS_B	0x51e	/* UART1_RTS */</div><div class='add'>+			IMX95_PAD_GPIO_IO14__LPUART8_CTS_B	0x51e	/* UART1_CTS */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie0: pcie0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B		0x31e	/* PCIE1_nCLKREQ */</div><div class='add'>+			IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_GPIO1_IO_BIT10	0x31e	/* PCIE1_nPERST */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie1: pcie1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B	0x31e	/* PCIE2_nCLKREQ */</div><div class='add'>+			IMX95_PAD_SAI1_RXD0__AONMIX_TOP_GPIO1_IO_BIT14	0x31e	/* PCIE2_nPERST */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7	0x31e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai5: sai5grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_XSPI1_DQS__SAI5_RX_SYNC		0x51e	/* SAI1_RX_SYNC */</div><div class='add'>+			IMX95_PAD_XSPI1_SS1_B__SAI5_RX_BCLK		0x51e	/* SAI1_RX_BCLK */</div><div class='add'>+			IMX95_PAD_XSPI1_DATA7__SAI5_RX_DATA_BIT0	0x51e	/* SAI1_RX_DATA */</div><div class='add'>+			IMX95_PAD_XSPI1_DATA5__SAI5_TX_SYNC		0x51e	/* SAI1_TX_SYNC */</div><div class='add'>+			IMX95_PAD_XSPI1_DATA6__SAI5_TX_BCLK		0x51e	/* SAI1_TX_BCLK */</div><div class='add'>+			IMX95_PAD_XSPI1_DATA4__SAI5_TX_DATA_BIT0	0x51e	/* SAI1_TX_DATA */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_tpm3: tpm3grp {</div><div class='add'>+	      fsl,pins = &lt;</div><div class='add'>+		      IMX95_PAD_GPIO_IO24__TPM3_CH3	0x51e	/* PWM1 */</div><div class='add'>+	      &gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_tpm5: tpm5grp {</div><div class='add'>+	      fsl,pins = &lt;</div><div class='add'>+		      IMX95_PAD_GPIO_IO26__TPM5_CH3	0x51e	/* PWM2 */</div><div class='add'>+	      &gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usbc: usbcgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_SAI1_TXFS__AONMIX_TOP_GPIO1_IO_BIT11	0x51e	/* USB1_PWR_EN */</div><div class='add'>+			IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13		0x51e	/* USB1_OC */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usb2: usb2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_SAI1_TXD0__AONMIX_TOP_GPIO1_IO_BIT13	0x51e	/* USB2_PWR_EN */</div><div class='add'>+			IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14		0x51e	/* USB2_OC */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_SD1_DATA0__USDHC1_DATA0		0x138e</div><div class='add'>+			IMX95_PAD_SD1_DATA1__USDHC1_DATA1		0x138e</div><div class='add'>+			IMX95_PAD_SD1_DATA2__USDHC1_DATA2		0x138e</div><div class='add'>+			IMX95_PAD_SD1_DATA3__USDHC1_DATA3		0x138e</div><div class='add'>+			IMX95_PAD_SD1_DATA4__USDHC1_DATA4		0x138e</div><div class='add'>+			IMX95_PAD_SD1_DATA5__USDHC1_DATA5		0x138e</div><div class='add'>+			IMX95_PAD_SD1_DATA6__USDHC1_DATA6		0x138e</div><div class='add'>+			IMX95_PAD_SD1_DATA7__USDHC1_DATA7		0x138e</div><div class='add'>+			IMX95_PAD_SD1_CMD__USDHC1_CMD			0x138e</div><div class='add'>+			IMX95_PAD_SD1_CLK__USDHC1_CLK			0x158e</div><div class='add'>+			IMX95_PAD_SD1_STROBE__USDHC1_STROBE		0x158e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_SD1_DATA0__USDHC1_DATA0		0x138e</div><div class='add'>+			IMX95_PAD_SD1_DATA1__USDHC1_DATA1		0x138e</div><div class='add'>+			IMX95_PAD_SD1_DATA2__USDHC1_DATA2		0x138e</div><div class='add'>+			IMX95_PAD_SD1_DATA3__USDHC1_DATA3		0x138e</div><div class='add'>+			IMX95_PAD_SD1_DATA4__USDHC1_DATA4		0x138e</div><div class='add'>+			IMX95_PAD_SD1_DATA5__USDHC1_DATA5		0x138e</div><div class='add'>+			IMX95_PAD_SD1_DATA6__USDHC1_DATA6		0x138e</div><div class='add'>+			IMX95_PAD_SD1_DATA7__USDHC1_DATA7		0x138e</div><div class='add'>+			IMX95_PAD_SD1_CMD__USDHC1_CMD			0x138e</div><div class='add'>+			IMX95_PAD_SD1_CLK__USDHC1_CLK			0x158e</div><div class='add'>+			IMX95_PAD_SD1_STROBE__USDHC1_STROBE		0x158e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_SD1_DATA0__USDHC1_DATA0		0x13fe</div><div class='add'>+			IMX95_PAD_SD1_DATA1__USDHC1_DATA1		0x13fe</div><div class='add'>+			IMX95_PAD_SD1_DATA2__USDHC1_DATA2		0x13fe</div><div class='add'>+			IMX95_PAD_SD1_DATA3__USDHC1_DATA3		0x13fe</div><div class='add'>+			IMX95_PAD_SD1_DATA4__USDHC1_DATA4		0x13fe</div><div class='add'>+			IMX95_PAD_SD1_DATA5__USDHC1_DATA5		0x13fe</div><div class='add'>+			IMX95_PAD_SD1_DATA6__USDHC1_DATA6		0x13fe</div><div class='add'>+			IMX95_PAD_SD1_DATA7__USDHC1_DATA7		0x13fe</div><div class='add'>+			IMX95_PAD_SD1_CMD__USDHC1_CMD			0x13fe</div><div class='add'>+			IMX95_PAD_SD1_CLK__USDHC1_CLK			0x15fe</div><div class='add'>+			IMX95_PAD_SD1_STROBE__USDHC1_STROBE		0x15fe</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_SD2_CD_B__USDHC2_CD_B		0x31e	/* CD */</div><div class='add'>+			IMX95_PAD_SD2_CLK__USDHC2_CLK		0x158e	/* CLK */</div><div class='add'>+			IMX95_PAD_SD2_CMD__USDHC2_CMD		0x138e	/* CMD */</div><div class='add'>+			IMX95_PAD_SD2_DATA0__USDHC2_DATA0	0x138e	/* DATA0 */</div><div class='add'>+			IMX95_PAD_SD2_DATA1__USDHC2_DATA1	0x138e	/* DATA1 */</div><div class='add'>+			IMX95_PAD_SD2_DATA2__USDHC2_DATA2	0x138e	/* DATA2 */</div><div class='add'>+			IMX95_PAD_SD2_DATA3__USDHC2_DATA3	0x138e	/* DATA3 */</div><div class='add'>+			IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e</div><div class='add'>+</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_SD2_CD_B__USDHC2_CD_B		0x31e	/* CD */</div><div class='add'>+			IMX95_PAD_SD2_CLK__USDHC2_CLK		0x158e	/* CLK */</div><div class='add'>+			IMX95_PAD_SD2_CMD__USDHC2_CMD		0x138e	/* CMD */</div><div class='add'>+			IMX95_PAD_SD2_DATA0__USDHC2_DATA0	0x138e	/* DATA0 */</div><div class='add'>+			IMX95_PAD_SD2_DATA1__USDHC2_DATA1	0x138e	/* DATA1 */</div><div class='add'>+			IMX95_PAD_SD2_DATA2__USDHC2_DATA2	0x138e	/* DATA2 */</div><div class='add'>+			IMX95_PAD_SD2_DATA3__USDHC2_DATA3	0x138e	/* DATA3 */</div><div class='add'>+			IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_SD2_CD_B__USDHC2_CD_B		0x31e	/* CD */</div><div class='add'>+			IMX95_PAD_SD2_CLK__USDHC2_CLK		0x15fe	/* CLK */</div><div class='add'>+			IMX95_PAD_SD2_CMD__USDHC2_CMD		0x13fe	/* CMD */</div><div class='add'>+			IMX95_PAD_SD2_DATA0__USDHC2_DATA0	0x13fe	/* DATA0 */</div><div class='add'>+			IMX95_PAD_SD2_DATA1__USDHC2_DATA1	0x13fe	/* DATA1 */</div><div class='add'>+			IMX95_PAD_SD2_DATA2__USDHC2_DATA2	0x13fe	/* DATA2 */</div><div class='add'>+			IMX95_PAD_SD2_DATA3__USDHC2_DATA3	0x13fe	/* DATA3 */</div><div class='add'>+			IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX95_PAD_SD3_CLK__USDHC3_CLK		0x158e	/* SDIO_CLK */</div><div class='add'>+			IMX95_PAD_SD3_CMD__USDHC3_CMD		0x138e	/* SDIO_CMD */</div><div class='add'>+			IMX95_PAD_SD3_DATA0__USDHC3_DATA0	0x138e	/* SDIO_DATA0 */</div><div class='add'>+			IMX95_PAD_SD3_DATA1__USDHC3_DATA1	0x138e	/* SDIO_DATA1 */</div><div class='add'>+			IMX95_PAD_SD3_DATA2__USDHC3_DATA2	0x138e	/* SDIO_DATA2 */</div><div class='add'>+			IMX95_PAD_SD3_DATA3__USDHC3_DATA3	0x138e	/* SDIO_DATA3 */</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tpm3 { /* FPSC PWM1 */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_tpm3&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tpm5 {	/* FPSC PWM2 */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_tpm5&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3 { /* FPSC USB1 */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usbc&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	no-sd;</div><div class='add'>+	no-sdio;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1_200mhz&gt;;</div><div class='add'>+	pinctrl-3 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 { /* FPSC SDCARD */</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;;</div><div class='add'>+	pinctrl-3 = &lt;&amp;pinctrl_usdhc2&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";</div><div class='add'>+	sd-uhs-sdr104;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc3 { /* FPSC SDIO */</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx95-pinfunc.h b/arch/arm64/boot/dts/freescale/imx95-pinfunc.h<br/>new file mode 100644<br/>index 000000000000..9f614eea7c86<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx95-pinfunc.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx95-pinfunc.h</a></div><div class='hunk'>@@ -0,0 +1,865 @@</div><div class='add'>+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __DTS_IMX95_PINFUNC_H</div><div class='add'>+#define __DTS_IMX95_PINFUNC_H</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * The pin function ID is a tuple of</div><div class='add'>+ * &lt;mux_reg conf_reg input_reg mux_mode input_val&gt;</div><div class='add'>+ */</div><div class='add'>+#define IMX95_PAD_DAP_TDI__JTAG_MUX_TDI                               0x0000 0x0204 0x0610 0x00 0x00</div><div class='add'>+#define IMX95_PAD_DAP_TDI__NETCMIX_TOP_MQS2_LEFT                      0x0000 0x0204 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_DAP_TDI__NETCMIX_TOP_NETC_TMR_1588_ALARM1           0x0000 0x0204 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_DAP_TDI__CAN2_TX                                    0x0000 0x0204 0x0000 0x03 0x00</div><div class='add'>+#define IMX95_PAD_DAP_TDI__FLEXIO2_FLEXIO_BIT30                       0x0000 0x0204 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_DAP_TDI__GPIO3_IO_BIT28                             0x0000 0x0204 0x0000 0x05 0x00</div><div class='add'>+#define IMX95_PAD_DAP_TDI__LPUART5_RX                                 0x0000 0x0204 0x0570 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS                         0x0004 0x0208 0x0614 0x00 0x00</div><div class='add'>+#define IMX95_PAD_DAP_TMS_SWDIO__CAN4_TX                              0x0004 0x0208 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO_BIT31                 0x0004 0x0208 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_DAP_TMS_SWDIO__GPIO3_IO_BIT29                       0x0004 0x0208 0x0000 0x05 0x00</div><div class='add'>+#define IMX95_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B                        0x0004 0x0208 0x0000 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK                        0x0008 0x020C 0x060C 0x00 0x00</div><div class='add'>+#define IMX95_PAD_DAP_TCLK_SWCLK__CAN4_RX                             0x0008 0x020C 0x044C 0x02 0x00</div><div class='add'>+#define IMX95_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO_BIT30                0x0008 0x020C 0x0460 0x04 0x00</div><div class='add'>+#define IMX95_PAD_DAP_TCLK_SWCLK__GPIO3_IO_BIT30                      0x0008 0x020C 0x0000 0x05 0x00</div><div class='add'>+#define IMX95_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B                       0x0008 0x020C 0x056C 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO                      0x000C 0x0210 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_DAP_TDO_TRACESWO__NETCMIX_TOP_MQS2_RIGHT            0x000C 0x0210 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_DAP_TDO_TRACESWO__NETCMIX_TOP_NETC_TMR_1588_ALARM   0x000C 0x0210 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_DAP_TDO_TRACESWO__CAN2_RX                           0x000C 0x0210 0x0444 0x03 0x00</div><div class='add'>+#define IMX95_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO_BIT31              0x000C 0x0210 0x0464 0x04 0x00</div><div class='add'>+#define IMX95_PAD_DAP_TDO_TRACESWO__GPIO3_IO_BIT31                    0x000C 0x0210 0x0000 0x05 0x00</div><div class='add'>+#define IMX95_PAD_DAP_TDO_TRACESWO__LPUART5_TX                        0x000C 0x0210 0x0574 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_GPIO_IO00__GPIO2_IO_BIT0                            0x0010 0x0214 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO00__LPI2C3_SDA                               0x0010 0x0214 0x0504 0x11 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO00__LPSPI6_PCS0                              0x0010 0x0214 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO00__LPUART5_TX                               0x0010 0x0214 0x0574 0x05 0x01</div><div class='add'>+#define IMX95_PAD_GPIO_IO00__LPI2C5_SDA                               0x0010 0x0214 0x0514 0x16 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO00__FLEXIO1_FLEXIO_BIT0                      0x0010 0x0214 0x0468 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_GPIO_IO01__GPIO2_IO_BIT1                            0x0014 0x0218 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO01__LPI2C3_SCL                               0x0014 0x0218 0x0500 0x11 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO01__LPSPI6_SIN                               0x0014 0x0218 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO01__LPUART5_RX                               0x0014 0x0218 0x0570 0x05 0x01</div><div class='add'>+#define IMX95_PAD_GPIO_IO01__LPI2C5_SCL                               0x0014 0x0218 0x0510 0x16 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO01__FLEXIO1_FLEXIO_BIT1                      0x0014 0x0218 0x046C 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_GPIO_IO02__GPIO2_IO_BIT2                            0x0018 0x021C 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO02__LPI2C4_SDA                               0x0018 0x021C 0x050C 0x11 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO02__LPSPI6_SOUT                              0x0018 0x021C 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO02__LPUART5_CTS_B                            0x0018 0x021C 0x056C 0x05 0x01</div><div class='add'>+#define IMX95_PAD_GPIO_IO02__LPI2C6_SDA                               0x0018 0x021C 0x051C 0x16 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO02__FLEXIO1_FLEXIO_BIT2                      0x0018 0x021C 0x0470 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_GPIO_IO03__GPIO2_IO_BIT3                            0x001C 0x0220 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO03__LPI2C4_SCL                               0x001C 0x0220 0x0508 0x11 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO03__LPSPI6_SCK                               0x001C 0x0220 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO03__LPUART5_RTS_B                            0x001C 0x0220 0x0000 0x05 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO03__LPI2C6_SCL                               0x001C 0x0220 0x0518 0x16 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO03__FLEXIO1_FLEXIO_BIT3                      0x001C 0x0220 0x0474 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_GPIO_IO04__GPIO2_IO_BIT4                            0x0020 0x0224 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO04__TPM3_CH0                                 0x0020 0x0224 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO04__AONMIX_TOP_PDM_CLK                       0x0020 0x0224 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO04__CAN4_TX                                  0x0020 0x0224 0x0000 0x03 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO04__LPSPI7_PCS0                              0x0020 0x0224 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO04__LPUART6_TX                               0x0020 0x0224 0x0580 0x05 0x01</div><div class='add'>+#define IMX95_PAD_GPIO_IO04__LPI2C6_SDA                               0x0020 0x0224 0x051C 0x16 0x01</div><div class='add'>+#define IMX95_PAD_GPIO_IO04__FLEXIO1_FLEXIO_BIT4                      0x0020 0x0224 0x0478 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_GPIO_IO05__GPIO2_IO_BIT5                            0x0024 0x0228 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO05__TPM4_CH0                                 0x0024 0x0228 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO05__AONMIX_TOP_PDM_BIT_STREAM_BIT0           0x0024 0x0228 0x040C 0x02 0x01</div><div class='add'>+#define IMX95_PAD_GPIO_IO05__CAN4_RX                                  0x0024 0x0228 0x044C 0x03 0x01</div><div class='add'>+#define IMX95_PAD_GPIO_IO05__LPSPI7_SIN                               0x0024 0x0228 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO05__LPUART6_RX                               0x0024 0x0228 0x057C 0x05 0x01</div><div class='add'>+#define IMX95_PAD_GPIO_IO05__LPI2C6_SCL                               0x0024 0x0228 0x0518 0x16 0x01</div><div class='add'>+#define IMX95_PAD_GPIO_IO05__FLEXIO1_FLEXIO_BIT5                      0x0024 0x0228 0x047C 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_GPIO_IO06__GPIO2_IO_BIT6                            0x0028 0x022C 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO06__TPM5_CH0                                 0x0028 0x022C 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO06__AONMIX_TOP_PDM_BIT_STREAM_BIT1           0x0028 0x022C 0x0410 0x02 0x01</div><div class='add'>+#define IMX95_PAD_GPIO_IO06__LPSPI7_SOUT                              0x0028 0x022C 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO06__LPUART6_CTS_B                            0x0028 0x022C 0x0578 0x05 0x01</div><div class='add'>+#define IMX95_PAD_GPIO_IO06__LPI2C7_SDA                               0x0028 0x022C 0x0524 0x16 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO06__FLEXIO1_FLEXIO_BIT6                      0x0028 0x022C 0x0480 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_GPIO_IO07__GPIO2_IO_BIT7                            0x002C 0x0230 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO07__LPSPI3_PCS1                              0x002C 0x0230 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO07__LPSPI7_SCK                               0x002C 0x0230 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO07__LPUART6_RTS_B                            0x002C 0x0230 0x0000 0x05 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO07__LPI2C7_SCL                               0x002C 0x0230 0x0520 0x16 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO07__FLEXIO1_FLEXIO_BIT7                      0x002C 0x0230 0x0484 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_GPIO_IO08__GPIO2_IO_BIT8                            0x0030 0x0234 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO08__LPSPI3_PCS0                              0x0030 0x0234 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO08__TPM6_CH0                                 0x0030 0x0234 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO08__LPUART7_TX                               0x0030 0x0234 0x0588 0x05 0x01</div><div class='add'>+#define IMX95_PAD_GPIO_IO08__LPI2C7_SDA                               0x0030 0x0234 0x0524 0x16 0x01</div><div class='add'>+#define IMX95_PAD_GPIO_IO08__FLEXIO1_FLEXIO_BIT8                      0x0030 0x0234 0x0488 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_GPIO_IO09__GPIO2_IO_BIT9                            0x0034 0x0238 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO09__LPSPI3_SIN                               0x0034 0x0238 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO09__TPM3_EXTCLK                              0x0034 0x0238 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO09__LPUART7_RX                               0x0034 0x0238 0x0584 0x05 0x01</div><div class='add'>+#define IMX95_PAD_GPIO_IO09__LPI2C7_SCL                               0x0034 0x0238 0x0520 0x16 0x01</div><div class='add'>+#define IMX95_PAD_GPIO_IO09__FLEXIO1_FLEXIO_BIT9                      0x0034 0x0238 0x048C 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_GPIO_IO10__GPIO2_IO_BIT10                           0x0038 0x023C 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO10__LPSPI3_SOUT                              0x0038 0x023C 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO10__TPM4_EXTCLK                              0x0038 0x023C 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO10__LPUART7_CTS_B                            0x0038 0x023C 0x0000 0x05 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO10__LPI2C8_SDA                               0x0038 0x023C 0x052C 0x16 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO10__FLEXIO1_FLEXIO_BIT10                     0x0038 0x023C 0x0490 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_GPIO_IO11__GPIO2_IO_BIT11                           0x003C 0x0240 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO11__LPSPI3_SCK                               0x003C 0x0240 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO11__TPM5_EXTCLK                              0x003C 0x0240 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO11__LPUART7_RTS_B                            0x003C 0x0240 0x0000 0x05 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO11__LPI2C8_SCL                               0x003C 0x0240 0x0528 0x16 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO11__FLEXIO1_FLEXIO_BIT11                     0x003C 0x0240 0x0494 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_GPIO_IO12__GPIO2_IO_BIT12                           0x0040 0x0244 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO12__TPM3_CH2                                 0x0040 0x0244 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO12__AONMIX_TOP_PDM_BIT_STREAM_BIT2           0x0040 0x0244 0x0414 0x02 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO12__FLEXIO1_FLEXIO_BIT12                     0x0040 0x0244 0x0498 0x03 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO12__LPSPI8_PCS0                              0x0040 0x0244 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO12__LPUART8_TX                               0x0040 0x0244 0x0000 0x05 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO12__LPI2C8_SDA                               0x0040 0x0244 0x052C 0x16 0x01</div><div class='add'>+#define IMX95_PAD_GPIO_IO12__SAI3_RX_SYNC                             0x0040 0x0244 0x0590 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_GPIO_IO13__GPIO2_IO_BIT13                           0x0044 0x0248 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO13__TPM4_CH2                                 0x0044 0x0248 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO13__AONMIX_TOP_PDM_BIT_STREAM_BIT3           0x0044 0x0248 0x0418 0x02 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO13__LPSPI8_SIN                               0x0044 0x0248 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO13__LPUART8_RX                               0x0044 0x0248 0x0000 0x05 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO13__LPI2C8_SCL                               0x0044 0x0248 0x0528 0x16 0x01</div><div class='add'>+#define IMX95_PAD_GPIO_IO13__FLEXIO1_FLEXIO_BIT13                     0x0044 0x0248 0x049C 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_GPIO_IO14__GPIO2_IO_BIT14                           0x0048 0x024C 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO14__LPUART3_TX                               0x0048 0x024C 0x055C 0x01 0x01</div><div class='add'>+#define IMX95_PAD_GPIO_IO14__LPSPI8_SOUT                              0x0048 0x024C 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO14__LPUART8_CTS_B                            0x0048 0x024C 0x0000 0x05 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO14__LPUART4_TX                               0x0048 0x024C 0x0568 0x06 0x01</div><div class='add'>+#define IMX95_PAD_GPIO_IO14__FLEXIO1_FLEXIO_BIT14                     0x0048 0x024C 0x04A0 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_GPIO_IO15__GPIO2_IO_BIT15                           0x004C 0x0250 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO15__LPUART3_RX                               0x004C 0x0250 0x0558 0x01 0x01</div><div class='add'>+#define IMX95_PAD_GPIO_IO15__LPSPI8_SCK                               0x004C 0x0250 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO15__LPUART8_RTS_B                            0x004C 0x0250 0x0000 0x05 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO15__LPUART4_RX                               0x004C 0x0250 0x0564 0x06 0x01</div><div class='add'>+#define IMX95_PAD_GPIO_IO15__FLEXIO1_FLEXIO_BIT15                     0x004C 0x0250 0x04A4 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_GPIO_IO16__GPIO2_IO_BIT16                           0x0050 0x0254 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK                             0x0050 0x0254 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO16__AONMIX_TOP_PDM_BIT_STREAM_BIT2           0x0050 0x0254 0x0414 0x02 0x01</div><div class='add'>+#define IMX95_PAD_GPIO_IO16__LPUART3_CTS_B                            0x0050 0x0254 0x0554 0x04 0x01</div><div class='add'>+#define IMX95_PAD_GPIO_IO16__LPSPI4_PCS2                              0x0050 0x0254 0x0538 0x05 0x01</div><div class='add'>+#define IMX95_PAD_GPIO_IO16__LPUART4_CTS_B                            0x0050 0x0254 0x0560 0x06 0x01</div><div class='add'>+#define IMX95_PAD_GPIO_IO16__FLEXIO1_FLEXIO_BIT16                     0x0050 0x0254 0x04A8 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_GPIO_IO17__GPIO2_IO_BIT17                           0x0054 0x0258 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO17__SAI3_MCLK                                0x0054 0x0258 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO17__LPUART3_RTS_B                            0x0054 0x0258 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO17__LPSPI4_PCS1                              0x0054 0x0258 0x0534 0x05 0x01</div><div class='add'>+#define IMX95_PAD_GPIO_IO17__LPUART4_RTS_B                            0x0054 0x0258 0x0000 0x06 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO17__FLEXIO1_FLEXIO_BIT17                     0x0054 0x0258 0x04AC 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_GPIO_IO18__GPIO2_IO_BIT18                           0x0058 0x025C 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO18__SAI3_RX_BCLK                             0x0058 0x025C 0x058C 0x01 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO18__LPSPI5_PCS0                              0x0058 0x025C 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO18__LPSPI4_PCS0                              0x0058 0x025C 0x0530 0x05 0x01</div><div class='add'>+#define IMX95_PAD_GPIO_IO18__TPM5_CH2                                 0x0058 0x025C 0x0000 0x06 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO18__FLEXIO1_FLEXIO_BIT18                     0x0058 0x025C 0x04B0 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_GPIO_IO19__GPIO2_IO_BIT19                           0x005C 0x0260 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO19__SAI3_RX_SYNC                             0x005C 0x0260 0x0590 0x01 0x01</div><div class='add'>+#define IMX95_PAD_GPIO_IO19__AONMIX_TOP_PDM_BIT_STREAM_BIT3           0x005C 0x0260 0x0418 0x02 0x01</div><div class='add'>+#define IMX95_PAD_GPIO_IO19__FLEXIO1_FLEXIO_BIT19                     0x005C 0x0260 0x04B4 0x03 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO19__LPSPI5_SIN                               0x005C 0x0260 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO19__LPSPI4_SIN                               0x005C 0x0260 0x0540 0x05 0x01</div><div class='add'>+#define IMX95_PAD_GPIO_IO19__TPM6_CH2                                 0x005C 0x0260 0x0000 0x06 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO19__SAI3_TX_DATA_BIT0                        0x005C 0x0260 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_GPIO_IO20__GPIO2_IO_BIT20                           0x0060 0x0264 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0                        0x0060 0x0264 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO20__AONMIX_TOP_PDM_BIT_STREAM_BIT0           0x0060 0x0264 0x040C 0x02 0x02</div><div class='add'>+#define IMX95_PAD_GPIO_IO20__LPSPI5_SOUT                              0x0060 0x0264 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO20__LPSPI4_SOUT                              0x0060 0x0264 0x0544 0x05 0x01</div><div class='add'>+#define IMX95_PAD_GPIO_IO20__TPM3_CH1                                 0x0060 0x0264 0x0000 0x06 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO20__FLEXIO1_FLEXIO_BIT20                     0x0060 0x0264 0x04B8 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_GPIO_IO21__GPIO2_IO_BIT21                           0x0064 0x0268 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0                        0x0064 0x0268 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO21__AONMIX_TOP_PDM_CLK                       0x0064 0x0268 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO21__FLEXIO1_FLEXIO_BIT21                     0x0064 0x0268 0x04BC 0x03 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO21__LPSPI5_SCK                               0x0064 0x0268 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO21__LPSPI4_SCK                               0x0064 0x0268 0x053C 0x05 0x01</div><div class='add'>+#define IMX95_PAD_GPIO_IO21__TPM4_CH1                                 0x0064 0x0268 0x0000 0x06 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO21__SAI3_RX_BCLK                             0x0064 0x0268 0x058C 0x07 0x01</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_GPIO_IO22__GPIO2_IO_BIT22                           0x0068 0x026C 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO22__USDHC3_CLK                               0x0068 0x026C 0x05C8 0x01 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO22__SPDIF_IN                                 0x0068 0x026C 0x0454 0x02 0x02</div><div class='add'>+#define IMX95_PAD_GPIO_IO22__CAN5_TX                                  0x0068 0x026C 0x0000 0x03 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO22__TPM5_CH1                                 0x0068 0x026C 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO22__TPM6_EXTCLK                              0x0068 0x026C 0x0000 0x05 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO22__LPI2C5_SDA                               0x0068 0x026C 0x0514 0x16 0x01</div><div class='add'>+#define IMX95_PAD_GPIO_IO22__FLEXIO1_FLEXIO_BIT22                     0x0068 0x026C 0x04C0 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_GPIO_IO23__GPIO2_IO_BIT23                           0x006C 0x0270 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO23__USDHC3_CMD                               0x006C 0x0270 0x05CC 0x01 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO23__SPDIF_OUT                                0x006C 0x0270 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO23__CAN5_RX                                  0x006C 0x0270 0x0450 0x03 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO23__TPM6_CH1                                 0x006C 0x0270 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO23__LPI2C5_SCL                               0x006C 0x0270 0x0510 0x16 0x01</div><div class='add'>+#define IMX95_PAD_GPIO_IO23__FLEXIO1_FLEXIO_BIT23                     0x006C 0x0270 0x04C4 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_GPIO_IO24__GPIO2_IO_BIT24                           0x0070 0x0274 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO24__USDHC3_DATA0                             0x0070 0x0274 0x05D0 0x01 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO24__TPM3_CH3                                 0x0070 0x0274 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO24__JTAG_MUX_TDO                             0x0070 0x0274 0x0000 0x05 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO24__LPSPI6_PCS1                              0x0070 0x0274 0x0000 0x06 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO24__FLEXIO1_FLEXIO_BIT24                     0x0070 0x0274 0x04C8 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_GPIO_IO25__GPIO2_IO_BIT25                           0x0074 0x0278 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO25__USDHC3_DATA1                             0x0074 0x0278 0x05D4 0x01 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO25__CAN2_TX                                  0x0074 0x0278 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO25__TPM4_CH3                                 0x0074 0x0278 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO25__JTAG_MUX_TCK                             0x0074 0x0278 0x060C 0x05 0x01</div><div class='add'>+#define IMX95_PAD_GPIO_IO25__LPSPI7_PCS1                              0x0074 0x0278 0x0000 0x06 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO25__FLEXIO1_FLEXIO_BIT25                     0x0074 0x0278 0x04CC 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_GPIO_IO26__GPIO2_IO_BIT26                           0x0078 0x027C 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO26__USDHC3_DATA2                             0x0078 0x027C 0x05D8 0x01 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO26__AONMIX_TOP_PDM_BIT_STREAM_BIT1           0x0078 0x027C 0x0410 0x02 0x02</div><div class='add'>+#define IMX95_PAD_GPIO_IO26__FLEXIO1_FLEXIO_BIT26                     0x0078 0x027C 0x0458 0x03 0x01</div><div class='add'>+#define IMX95_PAD_GPIO_IO26__TPM5_CH3                                 0x0078 0x027C 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO26__JTAG_MUX_TDI                             0x0078 0x027C 0x0610 0x05 0x01</div><div class='add'>+#define IMX95_PAD_GPIO_IO26__LPSPI8_PCS1                              0x0078 0x027C 0x0000 0x06 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC                             0x0078 0x027C 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_GPIO_IO27__GPIO2_IO_BIT27                           0x007C 0x0280 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO27__USDHC3_DATA3                             0x007C 0x0280 0x05DC 0x01 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO27__CAN2_RX                                  0x007C 0x0280 0x0444 0x02 0x02</div><div class='add'>+#define IMX95_PAD_GPIO_IO27__TPM6_CH3                                 0x007C 0x0280 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO27__JTAG_MUX_TMS                             0x007C 0x0280 0x0614 0x05 0x01</div><div class='add'>+#define IMX95_PAD_GPIO_IO27__LPSPI5_PCS1                              0x007C 0x0280 0x0000 0x06 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO27__FLEXIO1_FLEXIO_BIT27                     0x007C 0x0280 0x045C 0x07 0x01</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_GPIO_IO28__GPIO2_IO_BIT28                           0x0080 0x0284 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO28__LPI2C3_SDA                               0x0080 0x0284 0x0504 0x11 0x01</div><div class='add'>+#define IMX95_PAD_GPIO_IO28__CAN3_TX                                  0x0080 0x0284 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO28__FLEXIO1_FLEXIO_BIT28                     0x0080 0x0284 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_GPIO_IO29__GPIO2_IO_BIT29                           0x0084 0x0288 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO29__LPI2C3_SCL                               0x0084 0x0288 0x0500 0x11 0x01</div><div class='add'>+#define IMX95_PAD_GPIO_IO29__CAN3_RX                                  0x0084 0x0288 0x0448 0x02 0x01</div><div class='add'>+#define IMX95_PAD_GPIO_IO29__FLEXIO1_FLEXIO_BIT29                     0x0084 0x0288 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_GPIO_IO30__GPIO2_IO_BIT30                           0x0088 0x028C 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO30__LPI2C4_SDA                               0x0088 0x028C 0x050C 0x11 0x01</div><div class='add'>+#define IMX95_PAD_GPIO_IO30__CAN5_TX                                  0x0088 0x028C 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO30__FLEXIO1_FLEXIO_BIT30                     0x0088 0x028C 0x0460 0x07 0x01</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_GPIO_IO31__GPIO2_IO_BIT31                           0x008C 0x0290 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO31__LPI2C4_SCL                               0x008C 0x0290 0x0508 0x11 0x01</div><div class='add'>+#define IMX95_PAD_GPIO_IO31__CAN5_RX                                  0x008C 0x0290 0x0450 0x02 0x01</div><div class='add'>+#define IMX95_PAD_GPIO_IO31__FLEXIO1_FLEXIO_BIT31                     0x008C 0x0290 0x0464 0x07 0x01</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_GPIO_IO32__GPIO5_IO_BIT12                           0x0090 0x0294 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B               0x0090 0x0294 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO32__LPUART6_TX                               0x0090 0x0294 0x0580 0x02 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO32__LPSPI4_PCS2                              0x0090 0x0294 0x0538 0x04 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13                           0x0094 0x0298 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO33__LPUART6_RX                               0x0094 0x0298 0x057C 0x02 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO33__LPSPI4_PCS1                              0x0094 0x0298 0x0534 0x04 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14                           0x0098 0x029C 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO34__LPUART6_CTS_B                            0x0098 0x029C 0x0578 0x02 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO34__LPSPI4_PCS0                              0x0098 0x029C 0x0530 0x04 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_GPIO_IO35__GPIO5_IO_BIT15                           0x009C 0x02A0 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B               0x009C 0x02A0 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO35__LPUART6_RTS_B                            0x009C 0x02A0 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO35__LPSPI4_SIN                               0x009C 0x02A0 0x0540 0x04 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_GPIO_IO36__LPSPI4_SOUT                              0x00A0 0x02A4 0x0544 0x04 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO36__GPIO5_IO_BIT16                           0x00A0 0x02A4 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO36__LPUART7_TX                               0x00A0 0x02A4 0x0588 0x02 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_GPIO_IO37__GPIO5_IO_BIT17                           0x00A4 0x02A8 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO37__LPUART7_RX                               0x00A4 0x02A8 0x0584 0x02 0x00</div><div class='add'>+#define IMX95_PAD_GPIO_IO37__LPSPI4_SCK                               0x00A4 0x02A8 0x053C 0x04 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_CCM_CLKO1__CCMSRCGPCMIX_TOP_CLKO_1                  0x00A8 0x02AC 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_CCM_CLKO1__NETCMIX_TOP_NETC_TMR_1588_TRIG1          0x00A8 0x02AC 0x0434 0x01 0x00</div><div class='add'>+#define IMX95_PAD_CCM_CLKO1__FLEXIO1_FLEXIO_BIT26                     0x00A8 0x02AC 0x0458 0x04 0x00</div><div class='add'>+#define IMX95_PAD_CCM_CLKO1__GPIO3_IO_BIT26                           0x00A8 0x02AC 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_CCM_CLKO2__GPIO3_IO_BIT27                           0x00AC 0x02B0 0x0000 0x05 0x00</div><div class='add'>+#define IMX95_PAD_CCM_CLKO2__CCMSRCGPCMIX_TOP_CLKO_2                  0x00AC 0x02B0 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_CCM_CLKO2__NETCMIX_TOP_NETC_TMR_1588_PP1            0x00AC 0x02B0 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_CCM_CLKO2__FLEXIO1_FLEXIO_BIT27                     0x00AC 0x02B0 0x045C 0x04 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_CCM_CLKO3__CCMSRCGPCMIX_TOP_CLKO_3                  0x00B0 0x02B4 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_CCM_CLKO3__NETCMIX_TOP_NETC_TMR_1588_TRIG2          0x00B0 0x02B4 0x0438 0x01 0x00</div><div class='add'>+#define IMX95_PAD_CCM_CLKO3__CAN3_TX                                  0x00B0 0x02B4 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_CCM_CLKO3__FLEXIO2_FLEXIO_BIT28                     0x00B0 0x02B4 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_CCM_CLKO3__GPIO4_IO_BIT28                           0x00B0 0x02B4 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_CCM_CLKO4__CCMSRCGPCMIX_TOP_CLKO_4                  0x00B4 0x02B8 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_CCM_CLKO4__NETCMIX_TOP_NETC_TMR_1588_PP2            0x00B4 0x02B8 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_CCM_CLKO4__CAN3_RX                                  0x00B4 0x02B8 0x0448 0x02 0x00</div><div class='add'>+#define IMX95_PAD_CCM_CLKO4__FLEXIO2_FLEXIO_BIT29                     0x00B4 0x02B8 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_CCM_CLKO4__GPIO4_IO_BIT29                           0x00B4 0x02B8 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC                     0x00B8 0x02BC 0x0424 0x00 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_MDC__LPUART3_DCD_B                            0x00B8 0x02BC 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_MDC__I3C2_SCL                                 0x00B8 0x02BC 0x04F8 0x02 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_MDC__HSIOMIX_TOP_USB1_OTG_ID                  0x00B8 0x02BC 0x0000 0x03 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_MDC__FLEXIO2_FLEXIO_BIT0                      0x00B8 0x02BC 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_MDC__GPIO4_IO_BIT0                            0x00B8 0x02BC 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO                   0x00BC 0x02C0 0x0428 0x00 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_MDIO__LPUART3_RIN_B                           0x00BC 0x02C0 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_MDIO__I3C2_SDA                                0x00BC 0x02C0 0x04FC 0x02 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_MDIO__HSIOMIX_TOP_USB1_OTG_PWR                0x00BC 0x02C0 0x0000 0x03 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_MDIO__FLEXIO2_FLEXIO_BIT1                     0x00BC 0x02C0 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_MDIO__GPIO4_IO_BIT1                           0x00BC 0x02C0 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3               0x00C0 0x02C4 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_TD3__CAN2_TX                                  0x00C0 0x02C4 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_TD3__HSIOMIX_TOP_USB2_OTG_ID                  0x00C0 0x02C4 0x0000 0x03 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_TD3__FLEXIO2_FLEXIO_BIT2                      0x00C0 0x02C4 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_TD3__GPIO4_IO_BIT2                            0x00C0 0x02C4 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2               0x00C4 0x02C8 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RMII_REF50_CLK          0x00C4 0x02C8 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_TD2__CAN2_RX                                  0x00C4 0x02C8 0x0444 0x02 0x01</div><div class='add'>+#define IMX95_PAD_ENET1_TD2__HSIOMIX_TOP_USB2_OTG_OC                  0x00C4 0x02C8 0x0000 0x03 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_TD2__FLEXIO2_FLEXIO_BIT3                      0x00C4 0x02C8 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_TD2__GPIO4_IO_BIT3                            0x00C4 0x02C8 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1               0x00C8 0x02CC 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_TD1__LPUART3_RTS_B                            0x00C8 0x02CC 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_TD1__I3C2_PUR                                 0x00C8 0x02CC 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_TD1__HSIOMIX_TOP_USB1_OTG_OC                  0x00C8 0x02CC 0x0000 0x03 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_TD1__FLEXIO2_FLEXIO_BIT4                      0x00C8 0x02CC 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_TD1__GPIO4_IO_BIT4                            0x00C8 0x02CC 0x0000 0x05 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_TD1__I3C2_PUR_B                               0x00C8 0x02CC 0x0000 0x06 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RMII_TXD1               0x00C8 0x02CC 0x0000 0x07 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0               0x00CC 0x02D0 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_TD0__LPUART3_TX                               0x00CC 0x02D0 0x055C 0x01 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RMII_TXD0               0x00CC 0x02D0 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_TD0__FLEXIO2_FLEXIO_BIT5                      0x00CC 0x02D0 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_TD0__GPIO4_IO_BIT5                            0x00CC 0x02D0 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL         0x00D0 0x02D4 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_TX_CTL__LPUART3_DTR_B                         0x00D0 0x02D4 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RMII_TX_EN           0x00D0 0x02D4 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO_BIT6                   0x00D0 0x02D4 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_TX_CTL__GPIO4_IO_BIT6                         0x00D0 0x02D4 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK            0x00D4 0x02D8 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_TXC__CCMSRCGPCMIX_TOP_ENET_CLK_ROOT           0x00D4 0x02D8 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_TXC__FLEXIO2_FLEXIO_BIT7                      0x00D4 0x02D8 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_TXC__GPIO4_IO_BIT7                            0x00D4 0x02D8 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL         0x00D8 0x02DC 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_RX_CTL__LPUART3_DSR_B                         0x00D8 0x02DC 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RMII_CRS_DV          0x00D8 0x02DC 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_RX_CTL__HSIOMIX_TOP_USB2_OTG_PWR              0x00D8 0x02DC 0x0000 0x03 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO_BIT8                   0x00D8 0x02DC 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_RX_CTL__GPIO4_IO_BIT8                         0x00D8 0x02DC 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK            0x00DC 0x02E0 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RMII_RX_ER              0x00DC 0x02E0 0x042C 0x01 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_RXC__FLEXIO2_FLEXIO_BIT9                      0x00DC 0x02E0 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_RXC__GPIO4_IO_BIT9                            0x00DC 0x02E0 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0               0x00E0 0x02E4 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_RD0__LPUART3_RX                               0x00E0 0x02E4 0x0558 0x01 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RMII_RXD0               0x00E0 0x02E4 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_RD0__FLEXIO2_FLEXIO_BIT10                     0x00E0 0x02E4 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_RD0__GPIO4_IO_BIT10                           0x00E0 0x02E4 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1               0x00E4 0x02E8 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_RD1__LPUART3_CTS_B                            0x00E4 0x02E8 0x0554 0x01 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RMII_RXD1               0x00E4 0x02E8 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_RD1__LPTMR2_ALT1                              0x00E4 0x02E8 0x0548 0x03 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_RD1__FLEXIO2_FLEXIO_BIT11                     0x00E4 0x02E8 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_RD1__GPIO4_IO_BIT11                           0x00E4 0x02E8 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2               0x00E8 0x02EC 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RMII_RX_ER              0x00E8 0x02EC 0x042C 0x02 0x01</div><div class='add'>+#define IMX95_PAD_ENET1_RD2__LPTMR2_ALT2                              0x00E8 0x02EC 0x054C 0x03 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_RD2__FLEXIO2_FLEXIO_BIT12                     0x00E8 0x02EC 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_RD2__GPIO4_IO_BIT12                           0x00E8 0x02EC 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3               0x00EC 0x02F0 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_RD3__LPTMR2_ALT3                              0x00EC 0x02F0 0x0550 0x03 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_RD3__FLEXIO2_FLEXIO_BIT13                     0x00EC 0x02F0 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_ENET1_RD3__GPIO4_IO_BIT13                           0x00EC 0x02F0 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC                     0x00F0 0x02F4 0x0424 0x00 0x01</div><div class='add'>+#define IMX95_PAD_ENET2_MDC__LPUART4_DCD_B                            0x00F0 0x02F4 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_MDC__NETCMIX_TOP_SAI2_RX_SYNC                 0x00F0 0x02F4 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_MDC__FLEXIO2_FLEXIO_BIT14                     0x00F0 0x02F4 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_MDC__GPIO4_IO_BIT14                           0x00F0 0x02F4 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO                   0x00F4 0x02F8 0x0428 0x00 0x01</div><div class='add'>+#define IMX95_PAD_ENET2_MDIO__LPUART4_RIN_B                           0x00F4 0x02F8 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_SAI2_RX_BCLK                0x00F4 0x02F8 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_MDIO__FLEXIO2_FLEXIO_BIT15                    0x00F4 0x02F8 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_MDIO__GPIO4_IO_BIT15                          0x00F4 0x02F8 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_ENET2_TD3__NETCMIX_TOP_SAI2_RX_DATA_BIT0            0x00F8 0x02FC 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_TD3__FLEXIO2_FLEXIO_BIT16                     0x00F8 0x02FC 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_TD3__GPIO4_IO_BIT16                           0x00F8 0x02FC 0x0000 0x05 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3               0x00F8 0x02FC 0x0000 0x00 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2               0x00FC 0x0300 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RMII_REF50_CLK          0x00FC 0x0300 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_TD2__NETCMIX_TOP_SAI2_RX_DATA_BIT1            0x00FC 0x0300 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_TD2__SAI4_TX_SYNC                             0x00FC 0x0300 0x05A4 0x03 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_TD2__FLEXIO2_FLEXIO_BIT17                     0x00FC 0x0300 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_TD2__GPIO4_IO_BIT17                           0x00FC 0x0300 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1               0x0100 0x0304 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_TD1__LPUART4_RTS_B                            0x0100 0x0304 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_TD1__NETCMIX_TOP_SAI2_RX_DATA_BIT2            0x0100 0x0304 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_TD1__SAI4_TX_BCLK                             0x0100 0x0304 0x05A0 0x03 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_TD1__FLEXIO2_FLEXIO_BIT18                     0x0100 0x0304 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_TD1__GPIO4_IO_BIT18                           0x0100 0x0304 0x0000 0x05 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RMII_TXD1               0x0100 0x0304 0x0000 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0               0x0104 0x0308 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_TD0__LPUART4_TX                               0x0104 0x0308 0x0568 0x01 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_TD0__NETCMIX_TOP_SAI2_RX_DATA_BIT3            0x0104 0x0308 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_TD0__SAI4_TX_DATA_BIT0                        0x0104 0x0308 0x0000 0x03 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_TD0__FLEXIO2_FLEXIO_BIT19                     0x0104 0x0308 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_TD0__GPIO4_IO_BIT19                           0x0104 0x0308 0x0000 0x05 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RMII_TXD0               0x0104 0x0308 0x0000 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL         0x0108 0x030C 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_TX_CTL__LPUART4_DTR_B                         0x0108 0x030C 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_SAI2_TX_SYNC              0x0108 0x030C 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RMII_TX_EN           0x0108 0x030C 0x0000 0x03 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO_BIT20                  0x0108 0x030C 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_TX_CTL__GPIO4_IO_BIT20                        0x0108 0x030C 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK            0x010C 0x0310 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_TXC__CCMSRCGPCMIX_TOP_ENET_CLK_ROOT           0x010C 0x0310 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_TXC__NETCMIX_TOP_SAI2_TX_BCLK                 0x010C 0x0310 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_TXC__FLEXIO2_FLEXIO_BIT21                     0x010C 0x0310 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_TXC__GPIO4_IO_BIT21                           0x010C 0x0310 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL         0x0110 0x0314 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_RX_CTL__LPUART4_DSR_B                         0x0110 0x0314 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_SAI2_TX_DATA_BIT0         0x0110 0x0314 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO_BIT22                  0x0110 0x0314 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_RX_CTL__GPIO4_IO_BIT22                        0x0110 0x0314 0x0000 0x05 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RMII_CRS_DV          0x0110 0x0314 0x0000 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK            0x0114 0x0318 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RMII_RX_ER              0x0114 0x0318 0x0430 0x01 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_RXC__NETCMIX_TOP_SAI2_TX_DATA_BIT1            0x0114 0x0318 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_RXC__SAI4_RX_SYNC                             0x0114 0x0318 0x059C 0x03 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_RXC__FLEXIO2_FLEXIO_BIT23                     0x0114 0x0318 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_RXC__GPIO4_IO_BIT23                           0x0114 0x0318 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0               0x0118 0x031C 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_RD0__LPUART4_RX                               0x0118 0x031C 0x0564 0x01 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_RD0__NETCMIX_TOP_SAI2_TX_DATA_BIT2            0x0118 0x031C 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_RD0__SAI4_RX_BCLK                             0x0118 0x031C 0x0594 0x03 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_RD0__FLEXIO2_FLEXIO_BIT24                     0x0118 0x031C 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_RD0__GPIO4_IO_BIT24                           0x0118 0x031C 0x0000 0x05 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RMII_RXD0               0x0118 0x031C 0x0000 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1               0x011C 0x0320 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_RD1__SPDIF_IN                                 0x011C 0x0320 0x0454 0x01 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_RD1__NETCMIX_TOP_SAI2_TX_DATA_BIT3            0x011C 0x0320 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_RD1__SAI4_RX_DATA_BIT0                        0x011C 0x0320 0x0598 0x03 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_RD1__FLEXIO2_FLEXIO_BIT25                     0x011C 0x0320 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_RD1__GPIO4_IO_BIT25                           0x011C 0x0320 0x0000 0x05 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RMII_RXD1               0x011C 0x0320 0x0000 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2               0x0120 0x0324 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_RD2__LPUART4_CTS_B                            0x0120 0x0324 0x0560 0x01 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_RD2__NETCMIX_TOP_SAI2_MCLK                    0x0120 0x0324 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_RD2__NETCMIX_TOP_MQS2_RIGHT                   0x0120 0x0324 0x0000 0x03 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_RD2__FLEXIO2_FLEXIO_BIT26                     0x0120 0x0324 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_RD2__GPIO4_IO_BIT26                           0x0120 0x0324 0x0000 0x05 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RMII_RX_ER              0x0120 0x0324 0x0430 0x06 0x01</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3               0x0124 0x0328 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_RD3__SPDIF_OUT                                0x0124 0x0328 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_RD3__SPDIF_IN                                 0x0124 0x0328 0x0454 0x02 0x01</div><div class='add'>+#define IMX95_PAD_ENET2_RD3__NETCMIX_TOP_MQS2_LEFT                    0x0124 0x0328 0x0000 0x03 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_RD3__FLEXIO2_FLEXIO_BIT27                     0x0124 0x0328 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_ENET2_RD3__GPIO4_IO_BIT27                           0x0124 0x0328 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_SD1_CLK__FLEXIO1_FLEXIO_BIT8                        0x0128 0x032C 0x0488 0x04 0x01</div><div class='add'>+#define IMX95_PAD_SD1_CLK__GPIO3_IO_BIT8                              0x0128 0x032C 0x0000 0x05 0x00</div><div class='add'>+#define IMX95_PAD_SD1_CLK__USDHC1_CLK                                 0x0128 0x032C 0x0000 0x00 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_SD1_CMD__USDHC1_CMD                                 0x012C 0x0330 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_SD1_CMD__FLEXIO1_FLEXIO_BIT9                        0x012C 0x0330 0x048C 0x04 0x01</div><div class='add'>+#define IMX95_PAD_SD1_CMD__GPIO3_IO_BIT9                              0x012C 0x0330 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_SD1_DATA0__USDHC1_DATA0                             0x0130 0x0334 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_SD1_DATA0__FLEXIO1_FLEXIO_BIT10                     0x0130 0x0334 0x0490 0x04 0x01</div><div class='add'>+#define IMX95_PAD_SD1_DATA0__GPIO3_IO_BIT10                           0x0130 0x0334 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_SD1_DATA1__USDHC1_DATA1                             0x0134 0x0338 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_SD1_DATA1__FLEXIO1_FLEXIO_BIT11                     0x0134 0x0338 0x0494 0x04 0x01</div><div class='add'>+#define IMX95_PAD_SD1_DATA1__GPIO3_IO_BIT11                           0x0134 0x0338 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_SD1_DATA2__USDHC1_DATA2                             0x0138 0x033C 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_SD1_DATA2__FLEXIO1_FLEXIO_BIT12                     0x0138 0x033C 0x0498 0x04 0x01</div><div class='add'>+#define IMX95_PAD_SD1_DATA2__GPIO3_IO_BIT12                           0x0138 0x033C 0x0000 0x05 0x00</div><div class='add'>+#define IMX95_PAD_SD1_DATA2__CCMSRCGPCMIX_TOP_PMIC_READY              0x0138 0x033C 0x0000 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_SD1_DATA3__USDHC1_DATA3                             0x013C 0x0340 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B                         0x013C 0x0340 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_SD1_DATA3__FLEXIO1_FLEXIO_BIT13                     0x013C 0x0340 0x049C 0x04 0x01</div><div class='add'>+#define IMX95_PAD_SD1_DATA3__GPIO3_IO_BIT13                           0x013C 0x0340 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_SD1_DATA4__USDHC1_DATA4                             0x0140 0x0344 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_SD1_DATA4__FLEXSPI1_A_DATA_BIT4                     0x0140 0x0344 0x04E4 0x01 0x00</div><div class='add'>+#define IMX95_PAD_SD1_DATA4__FLEXIO1_FLEXIO_BIT14                     0x0140 0x0344 0x04A0 0x04 0x01</div><div class='add'>+#define IMX95_PAD_SD1_DATA4__GPIO3_IO_BIT14                           0x0140 0x0344 0x0000 0x05 0x00</div><div class='add'>+#define IMX95_PAD_SD1_DATA4__XSPI_DATA_BIT4                           0x0140 0x0344 0x05FC 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_SD1_DATA5__USDHC1_DATA5                             0x0144 0x0348 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_SD1_DATA5__FLEXSPI1_A_DATA_BIT5                     0x0144 0x0348 0x04E8 0x01 0x00</div><div class='add'>+#define IMX95_PAD_SD1_DATA5__USDHC1_RESET_B                           0x0144 0x0348 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_SD1_DATA5__FLEXIO1_FLEXIO_BIT15                     0x0144 0x0348 0x04A4 0x04 0x01</div><div class='add'>+#define IMX95_PAD_SD1_DATA5__GPIO3_IO_BIT15                           0x0144 0x0348 0x0000 0x05 0x00</div><div class='add'>+#define IMX95_PAD_SD1_DATA5__XSPI_DATA_BIT5                           0x0144 0x0348 0x0600 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_SD1_DATA6__USDHC1_DATA6                             0x0148 0x034C 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_SD1_DATA6__FLEXSPI1_A_DATA_BIT6                     0x0148 0x034C 0x04EC 0x01 0x00</div><div class='add'>+#define IMX95_PAD_SD1_DATA6__USDHC1_CD_B                              0x0148 0x034C 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_SD1_DATA6__FLEXIO1_FLEXIO_BIT16                     0x0148 0x034C 0x04A8 0x04 0x01</div><div class='add'>+#define IMX95_PAD_SD1_DATA6__GPIO3_IO_BIT16                           0x0148 0x034C 0x0000 0x05 0x00</div><div class='add'>+#define IMX95_PAD_SD1_DATA6__XSPI_DATA_BIT6                           0x0148 0x034C 0x0604 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_SD1_DATA7__USDHC1_DATA7                             0x014C 0x0350 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_SD1_DATA7__FLEXSPI1_A_DATA_BIT7                     0x014C 0x0350 0x04F0 0x01 0x00</div><div class='add'>+#define IMX95_PAD_SD1_DATA7__USDHC1_WP                                0x014C 0x0350 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_SD1_DATA7__FLEXIO1_FLEXIO_BIT17                     0x014C 0x0350 0x04AC 0x04 0x01</div><div class='add'>+#define IMX95_PAD_SD1_DATA7__GPIO3_IO_BIT17                           0x014C 0x0350 0x0000 0x05 0x00</div><div class='add'>+#define IMX95_PAD_SD1_DATA7__XSPI_DATA_BIT7                           0x014C 0x0350 0x0608 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_SD1_STROBE__USDHC1_STROBE                           0x0150 0x0354 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_SD1_STROBE__FLEXSPI1_A_DQS                          0x0150 0x0354 0x04D0 0x01 0x00</div><div class='add'>+#define IMX95_PAD_SD1_STROBE__FLEXIO1_FLEXIO_BIT18                    0x0150 0x0354 0x04B0 0x04 0x01</div><div class='add'>+#define IMX95_PAD_SD1_STROBE__GPIO3_IO_BIT18                          0x0150 0x0354 0x0000 0x05 0x00</div><div class='add'>+#define IMX95_PAD_SD1_STROBE__XSPI_DQS                                0x0150 0x0354 0x05E4 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT                         0x0154 0x0358 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_SD2_VSELECT__USDHC2_WP                              0x0154 0x0358 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_SD2_VSELECT__LPTMR2_ALT3                            0x0154 0x0358 0x0550 0x02 0x01</div><div class='add'>+#define IMX95_PAD_SD2_VSELECT__FLEXIO1_FLEXIO_BIT19                   0x0154 0x0358 0x04B4 0x04 0x01</div><div class='add'>+#define IMX95_PAD_SD2_VSELECT__GPIO3_IO_BIT19                         0x0154 0x0358 0x0000 0x05 0x00</div><div class='add'>+#define IMX95_PAD_SD2_VSELECT__CCMSRCGPCMIX_TOP_EXT_CLK1              0x0154 0x0358 0x0420 0x06 0x01</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_SD3_CLK__USDHC3_CLK                                 0x0158 0x035C 0x05C8 0x00 0x01</div><div class='add'>+#define IMX95_PAD_SD3_CLK__FLEXSPI1_A_SCLK                            0x0158 0x035C 0x04F4 0x01 0x00</div><div class='add'>+#define IMX95_PAD_SD3_CLK__SAI5_TX_DATA_BIT1                          0x0158 0x035C 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_SD3_CLK__SAI5_RX_DATA_BIT0                          0x0158 0x035C 0x05AC 0x03 0x00</div><div class='add'>+#define IMX95_PAD_SD3_CLK__FLEXIO1_FLEXIO_BIT20                       0x0158 0x035C 0x04B8 0x04 0x01</div><div class='add'>+#define IMX95_PAD_SD3_CLK__GPIO3_IO_BIT20                             0x0158 0x035C 0x0000 0x05 0x00</div><div class='add'>+#define IMX95_PAD_SD3_CLK__XSPI_CLK                                   0x0158 0x035C 0x05E8 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_SD3_CMD__USDHC3_CMD                                 0x015C 0x0360 0x05CC 0x00 0x01</div><div class='add'>+#define IMX95_PAD_SD3_CMD__FLEXSPI1_A_SS0_B                           0x015C 0x0360 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_SD3_CMD__SAI5_TX_DATA_BIT2                          0x015C 0x0360 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_SD3_CMD__SAI5_RX_SYNC                               0x015C 0x0360 0x05BC 0x03 0x00</div><div class='add'>+#define IMX95_PAD_SD3_CMD__FLEXIO1_FLEXIO_BIT21                       0x015C 0x0360 0x04BC 0x04 0x01</div><div class='add'>+#define IMX95_PAD_SD3_CMD__GPIO3_IO_BIT21                             0x015C 0x0360 0x0000 0x05 0x00</div><div class='add'>+#define IMX95_PAD_SD3_CMD__XSPI_CS                                    0x015C 0x0360 0x05E0 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_SD3_DATA0__USDHC3_DATA0                             0x0160 0x0364 0x05D0 0x00 0x01</div><div class='add'>+#define IMX95_PAD_SD3_DATA0__FLEXSPI1_A_DATA_BIT0                     0x0160 0x0364 0x04D4 0x01 0x00</div><div class='add'>+#define IMX95_PAD_SD3_DATA0__SAI5_TX_DATA_BIT3                        0x0160 0x0364 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_SD3_DATA0__SAI5_RX_BCLK                             0x0160 0x0364 0x05A8 0x03 0x00</div><div class='add'>+#define IMX95_PAD_SD3_DATA0__FLEXIO1_FLEXIO_BIT22                     0x0160 0x0364 0x04C0 0x04 0x01</div><div class='add'>+#define IMX95_PAD_SD3_DATA0__GPIO3_IO_BIT22                           0x0160 0x0364 0x0000 0x05 0x00</div><div class='add'>+#define IMX95_PAD_SD3_DATA0__XSPI_DATA_BIT0                           0x0160 0x0364 0x05EC 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_SD3_DATA1__USDHC3_DATA1                             0x0164 0x0368 0x05D4 0x00 0x01</div><div class='add'>+#define IMX95_PAD_SD3_DATA1__FLEXSPI1_A_DATA_BIT1                     0x0164 0x0368 0x04D8 0x01 0x00</div><div class='add'>+#define IMX95_PAD_SD3_DATA1__SAI5_RX_DATA_BIT1                        0x0164 0x0368 0x05B0 0x02 0x00</div><div class='add'>+#define IMX95_PAD_SD3_DATA1__SAI5_TX_DATA_BIT0                        0x0164 0x0368 0x0000 0x03 0x00</div><div class='add'>+#define IMX95_PAD_SD3_DATA1__FLEXIO1_FLEXIO_BIT23                     0x0164 0x0368 0x04C4 0x04 0x01</div><div class='add'>+#define IMX95_PAD_SD3_DATA1__GPIO3_IO_BIT23                           0x0164 0x0368 0x0000 0x05 0x00</div><div class='add'>+#define IMX95_PAD_SD3_DATA1__XSPI_DATA_BIT1                           0x0164 0x0368 0x05F0 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_SD3_DATA2__USDHC3_DATA2                             0x0168 0x036C 0x05D8 0x00 0x01</div><div class='add'>+#define IMX95_PAD_SD3_DATA2__FLEXSPI1_A_DATA_BIT2                     0x0168 0x036C 0x04DC 0x01 0x00</div><div class='add'>+#define IMX95_PAD_SD3_DATA2__SAI5_RX_DATA_BIT2                        0x0168 0x036C 0x05B4 0x02 0x00</div><div class='add'>+#define IMX95_PAD_SD3_DATA2__SAI5_TX_SYNC                             0x0168 0x036C 0x05C4 0x03 0x00</div><div class='add'>+#define IMX95_PAD_SD3_DATA2__FLEXIO1_FLEXIO_BIT24                     0x0168 0x036C 0x04C8 0x04 0x01</div><div class='add'>+#define IMX95_PAD_SD3_DATA2__GPIO3_IO_BIT24                           0x0168 0x036C 0x0000 0x05 0x00</div><div class='add'>+#define IMX95_PAD_SD3_DATA2__XSPI_DATA_BIT2                           0x0168 0x036C 0x05F4 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_SD3_DATA3__USDHC3_DATA3                             0x016C 0x0370 0x05DC 0x00 0x01</div><div class='add'>+#define IMX95_PAD_SD3_DATA3__FLEXSPI1_A_DATA_BIT3                     0x016C 0x0370 0x04E0 0x01 0x00</div><div class='add'>+#define IMX95_PAD_SD3_DATA3__SAI5_RX_DATA_BIT3                        0x016C 0x0370 0x05B8 0x02 0x00</div><div class='add'>+#define IMX95_PAD_SD3_DATA3__SAI5_TX_BCLK                             0x016C 0x0370 0x05C0 0x03 0x00</div><div class='add'>+#define IMX95_PAD_SD3_DATA3__FLEXIO1_FLEXIO_BIT25                     0x016C 0x0370 0x04CC 0x04 0x01</div><div class='add'>+#define IMX95_PAD_SD3_DATA3__GPIO3_IO_BIT25                           0x016C 0x0370 0x0000 0x05 0x00</div><div class='add'>+#define IMX95_PAD_SD3_DATA3__XSPI_DATA_BIT3                           0x016C 0x0370 0x05F8 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_XSPI1_DATA0__FLEXSPI1_A_DATA_BIT0                   0x0170 0x0374 0x04D4 0x00 0x01</div><div class='add'>+#define IMX95_PAD_XSPI1_DATA0__NETCMIX_TOP_SAI2_TX_DATA_BIT4          0x0170 0x0374 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_XSPI1_DATA0__SAI4_TX_BCLK                           0x0170 0x0374 0x05A0 0x02 0x01</div><div class='add'>+#define IMX95_PAD_XSPI1_DATA0__SAI4_RX_DATA_BIT1                      0x0170 0x0374 0x0000 0x03 0x00</div><div class='add'>+#define IMX95_PAD_XSPI1_DATA0__XSPI_DATA_BIT0                         0x0170 0x0374 0x05EC 0x04 0x01</div><div class='add'>+#define IMX95_PAD_XSPI1_DATA0__GPIO5_IO_BIT0                          0x0170 0x0374 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_XSPI1_DATA1__FLEXSPI1_A_DATA_BIT1                   0x0174 0x0378 0x04D8 0x00 0x01</div><div class='add'>+#define IMX95_PAD_XSPI1_DATA1__NETCMIX_TOP_SAI2_TX_DATA_BIT5          0x0174 0x0378 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_XSPI1_DATA1__SAI4_TX_SYNC                           0x0174 0x0378 0x05A4 0x02 0x01</div><div class='add'>+#define IMX95_PAD_XSPI1_DATA1__SAI4_TX_DATA_BIT1                      0x0174 0x0378 0x0000 0x03 0x00</div><div class='add'>+#define IMX95_PAD_XSPI1_DATA1__XSPI_DATA_BIT1                         0x0174 0x0378 0x05F0 0x04 0x01</div><div class='add'>+#define IMX95_PAD_XSPI1_DATA1__GPIO5_IO_BIT1                          0x0174 0x0378 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_XSPI1_DATA2__FLEXSPI1_A_DATA_BIT2                   0x0178 0x037C 0x04DC 0x00 0x01</div><div class='add'>+#define IMX95_PAD_XSPI1_DATA2__NETCMIX_TOP_SAI2_TX_DATA_BIT6          0x0178 0x037C 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_XSPI1_DATA2__SAI4_TX_DATA_BIT0                      0x0178 0x037C 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_XSPI1_DATA2__XSPI_DATA_BIT2                         0x0178 0x037C 0x05F4 0x04 0x01</div><div class='add'>+#define IMX95_PAD_XSPI1_DATA2__GPIO5_IO_BIT2                          0x0178 0x037C 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_XSPI1_DATA3__FLEXSPI1_A_DATA_BIT3                   0x017C 0x0380 0x04E0 0x00 0x01</div><div class='add'>+#define IMX95_PAD_XSPI1_DATA3__NETCMIX_TOP_SAI2_TX_DATA_BIT7          0x017C 0x0380 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_XSPI1_DATA3__SAI4_RX_DATA_BIT0                      0x017C 0x0380 0x0598 0x02 0x01</div><div class='add'>+#define IMX95_PAD_XSPI1_DATA3__XSPI_DATA_BIT3                         0x017C 0x0380 0x05F8 0x04 0x01</div><div class='add'>+#define IMX95_PAD_XSPI1_DATA3__GPIO5_IO_BIT3                          0x017C 0x0380 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_XSPI1_DATA4__FLEXSPI1_A_DATA_BIT4                   0x0180 0x0384 0x04E4 0x00 0x01</div><div class='add'>+#define IMX95_PAD_XSPI1_DATA4__SAI5_TX_DATA_BIT0                      0x0180 0x0384 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_XSPI1_DATA4__SAI5_RX_DATA_BIT1                      0x0180 0x0384 0x05B0 0x02 0x01</div><div class='add'>+#define IMX95_PAD_XSPI1_DATA4__XSPI_DATA_BIT4                         0x0180 0x0384 0x05FC 0x04 0x01</div><div class='add'>+#define IMX95_PAD_XSPI1_DATA4__GPIO5_IO_BIT4                          0x0180 0x0384 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_XSPI1_DATA5__FLEXSPI1_A_DATA_BIT5                   0x0184 0x0388 0x04E8 0x00 0x01</div><div class='add'>+#define IMX95_PAD_XSPI1_DATA5__SAI5_TX_SYNC                           0x0184 0x0388 0x05C4 0x01 0x01</div><div class='add'>+#define IMX95_PAD_XSPI1_DATA5__SAI5_RX_DATA_BIT2                      0x0184 0x0388 0x05B4 0x02 0x01</div><div class='add'>+#define IMX95_PAD_XSPI1_DATA5__NETCMIX_TOP_SAI2_RX_DATA_BIT6          0x0184 0x0388 0x043C 0x03 0x00</div><div class='add'>+#define IMX95_PAD_XSPI1_DATA5__XSPI_DATA_BIT5                         0x0184 0x0388 0x0600 0x04 0x01</div><div class='add'>+#define IMX95_PAD_XSPI1_DATA5__GPIO5_IO_BIT5                          0x0184 0x0388 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_XSPI1_DATA6__FLEXSPI1_A_DATA_BIT6                   0x0188 0x038C 0x04EC 0x00 0x01</div><div class='add'>+#define IMX95_PAD_XSPI1_DATA6__SAI5_TX_BCLK                           0x0188 0x038C 0x05C0 0x01 0x01</div><div class='add'>+#define IMX95_PAD_XSPI1_DATA6__SAI5_RX_DATA_BIT3                      0x0188 0x038C 0x05B8 0x02 0x01</div><div class='add'>+#define IMX95_PAD_XSPI1_DATA6__NETCMIX_TOP_SAI2_RX_DATA_BIT7          0x0188 0x038C 0x0440 0x03 0x00</div><div class='add'>+#define IMX95_PAD_XSPI1_DATA6__XSPI_DATA_BIT6                         0x0188 0x038C 0x0604 0x04 0x01</div><div class='add'>+#define IMX95_PAD_XSPI1_DATA6__GPIO5_IO_BIT6                          0x0188 0x038C 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_XSPI1_DATA7__FLEXSPI1_A_DATA_BIT7                   0x018C 0x0390 0x04F0 0x00 0x01</div><div class='add'>+#define IMX95_PAD_XSPI1_DATA7__SAI5_RX_DATA_BIT0                      0x018C 0x0390 0x05AC 0x01 0x01</div><div class='add'>+#define IMX95_PAD_XSPI1_DATA7__SAI5_TX_DATA_BIT1                      0x018C 0x0390 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_XSPI1_DATA7__XSPI_DATA_BIT7                         0x018C 0x0390 0x0608 0x04 0x01</div><div class='add'>+#define IMX95_PAD_XSPI1_DATA7__GPIO5_IO_BIT7                          0x018C 0x0390 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_XSPI1_DQS__FLEXSPI1_A_DQS                           0x0190 0x0394 0x04D0 0x00 0x01</div><div class='add'>+#define IMX95_PAD_XSPI1_DQS__SAI5_RX_SYNC                             0x0190 0x0394 0x05BC 0x01 0x01</div><div class='add'>+#define IMX95_PAD_XSPI1_DQS__SAI5_TX_DATA_BIT2                        0x0190 0x0394 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_XSPI1_DQS__NETCMIX_TOP_SAI2_RX_DATA_BIT6            0x0190 0x0394 0x043C 0x03 0x01</div><div class='add'>+#define IMX95_PAD_XSPI1_DQS__XSPI_DQS                                 0x0190 0x0394 0x05E4 0x04 0x01</div><div class='add'>+#define IMX95_PAD_XSPI1_DQS__GPIO5_IO_BIT8                            0x0190 0x0394 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_XSPI1_SCLK__FLEXSPI1_A_SCLK                         0x0194 0x0398 0x04F4 0x00 0x01</div><div class='add'>+#define IMX95_PAD_XSPI1_SCLK__NETCMIX_TOP_SAI2_RX_DATA_BIT4           0x0194 0x0398 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_XSPI1_SCLK__SAI4_RX_SYNC                            0x0194 0x0398 0x059C 0x02 0x01</div><div class='add'>+#define IMX95_PAD_XSPI1_SCLK__EARC_DC_HPD_IN                          0x0194 0x0398 0x0000 0x03 0x00</div><div class='add'>+#define IMX95_PAD_XSPI1_SCLK__XSPI_CLK                                0x0194 0x0398 0x05E8 0x04 0x01</div><div class='add'>+#define IMX95_PAD_XSPI1_SCLK__GPIO5_IO_BIT9                           0x0194 0x0398 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_XSPI1_SS0_B__FLEXSPI1_A_SS0_B                       0x0198 0x039C 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_XSPI1_SS0_B__NETCMIX_TOP_SAI2_RX_DATA_BIT5          0x0198 0x039C 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_XSPI1_SS0_B__SAI4_RX_BCLK                           0x0198 0x039C 0x0594 0x02 0x01</div><div class='add'>+#define IMX95_PAD_XSPI1_SS0_B__EARC_CEC_OUT                           0x0198 0x039C 0x0000 0x03 0x00</div><div class='add'>+#define IMX95_PAD_XSPI1_SS0_B__XSPI_CS                                0x0198 0x039C 0x05E0 0x04 0x01</div><div class='add'>+#define IMX95_PAD_XSPI1_SS0_B__GPIO5_IO_BIT10                         0x0198 0x039C 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_XSPI1_SS1_B__FLEXSPI1_A_SS1_B                       0x019C 0x03A0 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_XSPI1_SS1_B__SAI5_RX_BCLK                           0x019C 0x03A0 0x05A8 0x01 0x01</div><div class='add'>+#define IMX95_PAD_XSPI1_SS1_B__SAI5_TX_DATA_BIT3                      0x019C 0x03A0 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_XSPI1_SS1_B__NETCMIX_TOP_SAI2_RX_DATA_BIT7          0x019C 0x03A0 0x0440 0x03 0x01</div><div class='add'>+#define IMX95_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11                         0x019C 0x03A0 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_SD2_CD_B__USDHC2_CD_B                               0x01A0 0x03A4 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_SD2_CD_B__NETCMIX_TOP_NETC_TMR_1588_TRIG1           0x01A0 0x03A4 0x0434 0x01 0x01</div><div class='add'>+#define IMX95_PAD_SD2_CD_B__I3C2_SCL                                  0x01A0 0x03A4 0x04F8 0x02 0x01</div><div class='add'>+#define IMX95_PAD_SD2_CD_B__FLEXIO1_FLEXIO_BIT0                       0x01A0 0x03A4 0x0468 0x04 0x01</div><div class='add'>+#define IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0                             0x01A0 0x03A4 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_SD2_CLK__USDHC2_CLK                                 0x01A4 0x03A8 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_SD2_CLK__NETCMIX_TOP_NETC_TMR_1588_PP1              0x01A4 0x03A8 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_SD2_CLK__I3C2_SDA                                   0x01A4 0x03A8 0x04FC 0x02 0x01</div><div class='add'>+#define IMX95_PAD_SD2_CLK__FLEXIO1_FLEXIO_BIT1                        0x01A4 0x03A8 0x046C 0x04 0x01</div><div class='add'>+#define IMX95_PAD_SD2_CLK__GPIO3_IO_BIT1                              0x01A4 0x03A8 0x0000 0x05 0x00</div><div class='add'>+#define IMX95_PAD_SD2_CLK__CCMSRCGPCMIX_TOP_OBSERVE_0                 0x01A4 0x03A8 0x0000 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_SD2_CMD__USDHC2_CMD                                 0x01A8 0x03AC 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_SD2_CMD__NETCMIX_TOP_NETC_TMR_1588_TRIG2            0x01A8 0x03AC 0x0438 0x01 0x01</div><div class='add'>+#define IMX95_PAD_SD2_CMD__I3C2_PUR                                   0x01A8 0x03AC 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_SD2_CMD__I3C2_PUR_B                                 0x01A8 0x03AC 0x0000 0x03 0x00</div><div class='add'>+#define IMX95_PAD_SD2_CMD__FLEXIO1_FLEXIO_BIT2                        0x01A8 0x03AC 0x0470 0x04 0x01</div><div class='add'>+#define IMX95_PAD_SD2_CMD__GPIO3_IO_BIT2                              0x01A8 0x03AC 0x0000 0x05 0x00</div><div class='add'>+#define IMX95_PAD_SD2_CMD__CCMSRCGPCMIX_TOP_OBSERVE_1                 0x01A8 0x03AC 0x0000 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_SD2_DATA0__USDHC2_DATA0                             0x01AC 0x03B0 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_SD2_DATA0__NETCMIX_TOP_NETC_TMR_1588_PP2            0x01AC 0x03B0 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_SD2_DATA0__CAN2_TX                                  0x01AC 0x03B0 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_SD2_DATA0__FLEXIO1_FLEXIO_BIT3                      0x01AC 0x03B0 0x0474 0x04 0x01</div><div class='add'>+#define IMX95_PAD_SD2_DATA0__GPIO3_IO_BIT3                            0x01AC 0x03B0 0x0000 0x05 0x00</div><div class='add'>+#define IMX95_PAD_SD2_DATA0__CCMSRCGPCMIX_TOP_OBSERVE_2               0x01AC 0x03B0 0x0000 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_SD2_DATA1__USDHC2_DATA1                             0x01B0 0x03B4 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_SD2_DATA1__NETCMIX_TOP_NETC_TMR_1588_CLK            0x01B0 0x03B4 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_SD2_DATA1__CAN2_RX                                  0x01B0 0x03B4 0x0444 0x02 0x03</div><div class='add'>+#define IMX95_PAD_SD2_DATA1__FLEXIO1_FLEXIO_BIT4                      0x01B0 0x03B4 0x0478 0x04 0x01</div><div class='add'>+#define IMX95_PAD_SD2_DATA1__GPIO3_IO_BIT4                            0x01B0 0x03B4 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_SD2_DATA2__USDHC2_DATA2                             0x01B4 0x03B8 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_SD2_DATA2__NETCMIX_TOP_NETC_TMR_1588_PP3            0x01B4 0x03B8 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_SD2_DATA2__NETCMIX_TOP_MQS2_RIGHT                   0x01B4 0x03B8 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_SD2_DATA2__FLEXIO1_FLEXIO_BIT5                      0x01B4 0x03B8 0x047C 0x04 0x01</div><div class='add'>+#define IMX95_PAD_SD2_DATA2__GPIO3_IO_BIT5                            0x01B4 0x03B8 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_SD2_DATA3__USDHC2_DATA3                             0x01B8 0x03BC 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_SD2_DATA3__LPTMR2_ALT1                              0x01B8 0x03BC 0x0548 0x01 0x01</div><div class='add'>+#define IMX95_PAD_SD2_DATA3__NETCMIX_TOP_MQS2_LEFT                    0x01B8 0x03BC 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_SD2_DATA3__NETCMIX_TOP_NETC_TMR_1588_ALARM1         0x01B8 0x03BC 0x0000 0x03 0x00</div><div class='add'>+#define IMX95_PAD_SD2_DATA3__FLEXIO1_FLEXIO_BIT6                      0x01B8 0x03BC 0x0480 0x04 0x01</div><div class='add'>+#define IMX95_PAD_SD2_DATA3__GPIO3_IO_BIT6                            0x01B8 0x03BC 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_SD2_RESET_B__USDHC2_RESET_B                         0x01BC 0x03C0 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_SD2_RESET_B__LPTMR2_ALT2                            0x01BC 0x03C0 0x054C 0x01 0x01</div><div class='add'>+#define IMX95_PAD_SD2_RESET_B__NETCMIX_TOP_NETC_TMR_1588_GCLK         0x01BC 0x03C0 0x0000 0x03 0x00</div><div class='add'>+#define IMX95_PAD_SD2_RESET_B__FLEXIO1_FLEXIO_BIT7                    0x01BC 0x03C0 0x0484 0x04 0x01</div><div class='add'>+#define IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7                          0x01BC 0x03C0 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_I2C1_SCL__AONMIX_TOP_LPI2C1_SCL                     0x01C0 0x03C4 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_I2C1_SCL__AONMIX_TOP_I3C1_SCL                       0x01C0 0x03C4 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_I2C1_SCL__AONMIX_TOP_LPUART1_DCD_B                  0x01C0 0x03C4 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_I2C1_SCL__AONMIX_TOP_TPM2_CH0                       0x01C0 0x03C4 0x0000 0x03 0x00</div><div class='add'>+#define IMX95_PAD_I2C1_SCL__VPUMIX_TOP_UART_RX                        0x01C0 0x03C4 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_I2C1_SCL__AONMIX_TOP_GPIO1_IO_BIT0                  0x01C0 0x03C4 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_I2C1_SDA__AONMIX_TOP_LPI2C1_SDA                     0x01C4 0x03C8 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_I2C1_SDA__AONMIX_TOP_I3C1_SDA                       0x01C4 0x03C8 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_I2C1_SDA__AONMIX_TOP_LPUART1_RIN_B                  0x01C4 0x03C8 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_I2C1_SDA__AONMIX_TOP_TPM2_CH1                       0x01C4 0x03C8 0x0000 0x03 0x00</div><div class='add'>+#define IMX95_PAD_I2C1_SDA__VPUMIX_TOP_UART_TX                        0x01C4 0x03C8 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_I2C1_SDA__AONMIX_TOP_GPIO1_IO_BIT1                  0x01C4 0x03C8 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL                     0x01C8 0x03CC 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_I2C2_SCL__AONMIX_TOP_I3C1_PUR                       0x01C8 0x03CC 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPUART2_DCD_B                  0x01C8 0x03CC 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_I2C2_SCL__AONMIX_TOP_TPM2_CH2                       0x01C8 0x03CC 0x0000 0x03 0x00</div><div class='add'>+#define IMX95_PAD_I2C2_SCL__AONMIX_TOP_SAI1_RX_SYNC                   0x01C8 0x03CC 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_I2C2_SCL__AONMIX_TOP_GPIO1_IO_BIT2                  0x01C8 0x03CC 0x0000 0x05 0x00</div><div class='add'>+#define IMX95_PAD_I2C2_SCL__AONMIX_TOP_I3C1_PUR_B                     0x01C8 0x03CC 0x0000 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA                     0x01CC 0x03D0 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPUART2_RIN_B                  0x01CC 0x03D0 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_I2C2_SDA__AONMIX_TOP_TPM2_CH3                       0x01CC 0x03D0 0x0000 0x03 0x00</div><div class='add'>+#define IMX95_PAD_I2C2_SDA__AONMIX_TOP_SAI1_RX_BCLK                   0x01CC 0x03D0 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_I2C2_SDA__AONMIX_TOP_GPIO1_IO_BIT3                  0x01CC 0x03D0 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX                    0x01D0 0x03D4 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_UART1_RXD__S400_UART_RX                             0x01D0 0x03D4 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_UART1_RXD__AONMIX_TOP_LPSPI2_SIN                    0x01D0 0x03D4 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_UART1_RXD__AONMIX_TOP_TPM1_CH0                      0x01D0 0x03D4 0x0000 0x03 0x00</div><div class='add'>+#define IMX95_PAD_UART1_RXD__AONMIX_TOP_GPIO1_IO_BIT4                 0x01D0 0x03D4 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX                    0x01D4 0x03D8 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_UART1_TXD__S400_UART_TX                             0x01D4 0x03D8 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_UART1_TXD__AONMIX_TOP_LPSPI2_PCS0                   0x01D4 0x03D8 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_UART1_TXD__AONMIX_TOP_TPM1_CH1                      0x01D4 0x03D8 0x0000 0x03 0x00</div><div class='add'>+#define IMX95_PAD_UART1_TXD__AONMIX_TOP_GPIO1_IO_BIT5                 0x01D4 0x03D8 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART2_RX                    0x01D8 0x03DC 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART1_CTS_B                 0x01D8 0x03DC 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_UART2_RXD__AONMIX_TOP_LPSPI2_SOUT                   0x01D8 0x03DC 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_UART2_RXD__AONMIX_TOP_TPM1_CH2                      0x01D8 0x03DC 0x0000 0x03 0x00</div><div class='add'>+#define IMX95_PAD_UART2_RXD__AONMIX_TOP_SAI1_MCLK                     0x01D8 0x03DC 0x041C 0x04 0x00</div><div class='add'>+#define IMX95_PAD_UART2_RXD__AONMIX_TOP_GPIO1_IO_BIT6                 0x01D8 0x03DC 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART2_TX                    0x01DC 0x03E0 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART1_RTS_B                 0x01DC 0x03E0 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_UART2_TXD__AONMIX_TOP_LPSPI2_SCK                    0x01DC 0x03E0 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_UART2_TXD__AONMIX_TOP_TPM1_CH3                      0x01DC 0x03E0 0x0000 0x03 0x00</div><div class='add'>+#define IMX95_PAD_UART2_TXD__AONMIX_TOP_GPIO1_IO_BIT7                 0x01DC 0x03E0 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK                         0x01E0 0x03E4 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_PDM_CLK__AONMIX_TOP_MQS1_LEFT                       0x01E0 0x03E4 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_PDM_CLK__AONMIX_TOP_LPTMR1_ALT1                     0x01E0 0x03E4 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_PDM_CLK__AONMIX_TOP_GPIO1_IO_BIT8                   0x01E0 0x03E4 0x0000 0x05 0x00</div><div class='add'>+#define IMX95_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX                         0x01E0 0x03E4 0x0000 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_BIT0     0x01E4 0x03E8 0x040C 0x00 0x00</div><div class='add'>+#define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_MQS1_RIGHT              0x01E4 0x03E8 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_LPSPI1_PCS1             0x01E4 0x03E8 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_TPM1_EXTCLK             0x01E4 0x03E8 0x0000 0x03 0x00</div><div class='add'>+#define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_LPTMR1_ALT2             0x01E4 0x03E8 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_GPIO1_IO_BIT9           0x01E4 0x03E8 0x0000 0x05 0x00</div><div class='add'>+#define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX                 0x01E4 0x03E8 0x0408 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_PDM_BIT_STREAM_BIT1     0x01E8 0x03EC 0x0410 0x00 0x00</div><div class='add'>+#define IMX95_PAD_PDM_BIT_STREAM1__NMI_GLUE_NMI                       0x01E8 0x03EC 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_LPSPI2_PCS1             0x01E8 0x03EC 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_TPM2_EXTCLK             0x01E8 0x03EC 0x0000 0x03 0x00</div><div class='add'>+#define IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_LPTMR1_ALT3             0x01E8 0x03EC 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_GPIO1_IO_BIT10          0x01E8 0x03EC 0x0000 0x05 0x00</div><div class='add'>+#define IMX95_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_TOP_EXT_CLK1          0x01E8 0x03EC 0x0420 0x06 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_TX_SYNC                  0x01EC 0x03F0 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_TX_DATA_BIT1             0x01EC 0x03F0 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_LPSPI1_PCS0                   0x01EC 0x03F0 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_LPUART2_DTR_B                 0x01EC 0x03F0 0x0000 0x03 0x00</div><div class='add'>+#define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_MQS1_LEFT                     0x01EC 0x03F0 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_GPIO1_IO_BIT11                0x01EC 0x03F0 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_SAI1_TXC__AONMIX_TOP_SAI1_TX_BCLK                   0x01F0 0x03F4 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_SAI1_TXC__AONMIX_TOP_LPUART2_CTS_B                  0x01F0 0x03F4 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_SAI1_TXC__AONMIX_TOP_LPSPI1_SIN                     0x01F0 0x03F4 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_SAI1_TXC__AONMIX_TOP_LPUART1_DSR_B                  0x01F0 0x03F4 0x0000 0x03 0x00</div><div class='add'>+#define IMX95_PAD_SAI1_TXC__AONMIX_TOP_CAN1_RX                        0x01F0 0x03F4 0x0408 0x04 0x01</div><div class='add'>+#define IMX95_PAD_SAI1_TXC__AONMIX_TOP_GPIO1_IO_BIT12                 0x01F0 0x03F4 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_SAI1_TX_DATA_BIT0             0x01F4 0x03F8 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_LPUART2_RTS_B                 0x01F4 0x03F8 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_LPSPI1_SCK                    0x01F4 0x03F8 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_LPUART1_DTR_B                 0x01F4 0x03F8 0x0000 0x03 0x00</div><div class='add'>+#define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_CAN1_TX                       0x01F4 0x03F8 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_GPIO1_IO_BIT13                0x01F4 0x03F8 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_RX_DATA_BIT0             0x01F8 0x03FC 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_MCLK                     0x01F8 0x03FC 0x041C 0x01 0x01</div><div class='add'>+#define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_LPSPI1_SOUT                   0x01F8 0x03FC 0x0000 0x02 0x00</div><div class='add'>+#define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_LPUART2_DSR_B                 0x01F8 0x03FC 0x0000 0x03 0x00</div><div class='add'>+#define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_MQS1_RIGHT                    0x01F8 0x03FC 0x0000 0x04 0x00</div><div class='add'>+#define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_GPIO1_IO_BIT14                0x01F8 0x03FC 0x0000 0x05 0x00</div><div class='add'>+</div><div class='add'>+#define IMX95_PAD_WDOG_ANY__AONMIX_TOP_WDOG_ANY                       0x01FC 0x0400 0x0000 0x00 0x00</div><div class='add'>+#define IMX95_PAD_WDOG_ANY__AONMIX_TOP_FCCU_EOUT1                     0x01FC 0x0400 0x0000 0x01 0x00</div><div class='add'>+#define IMX95_PAD_WDOG_ANY__AONMIX_TOP_GPIO1_IO_BIT15                 0x01FC 0x0400 0x0000 0x05 0x00</div><div class='add'>+#endif /* __DTS_IMX95_PINFUNC_H */</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx95-power.h b/arch/arm64/boot/dts/freescale/imx95-power.h<br/>new file mode 100644<br/>index 000000000000..0b7f0bc30e19<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx95-power.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx95-power.h</a></div><div class='hunk'>@@ -0,0 +1,47 @@</div><div class='add'>+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */</div><div class='add'>+/*</div><div class='add'>+ *  Copyright 2024 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __IMX95_POWER_H__</div><div class='add'>+#define __IMX95_POWER_H__</div><div class='add'>+</div><div class='add'>+#define IMX95_PD_ANA		0</div><div class='add'>+#define IMX95_PD_AON		1</div><div class='add'>+#define IMX95_PD_BBSM		2</div><div class='add'>+#define IMX95_PD_CAMERA		3</div><div class='add'>+#define IMX95_PD_CCMSRCGPC	4</div><div class='add'>+#define IMX95_PD_A55C0		5</div><div class='add'>+#define IMX95_PD_A55C1		6</div><div class='add'>+#define IMX95_PD_A55C2		7</div><div class='add'>+#define IMX95_PD_A55C3		8</div><div class='add'>+#define IMX95_PD_A55C4		9</div><div class='add'>+#define IMX95_PD_A55C5		10</div><div class='add'>+#define IMX95_PD_A55P		11</div><div class='add'>+#define IMX95_PD_DDR		12</div><div class='add'>+#define IMX95_PD_DISPLAY	13</div><div class='add'>+#define IMX95_PD_GPU		14</div><div class='add'>+#define IMX95_PD_HSIO_TOP	15</div><div class='add'>+#define IMX95_PD_HSIO_WAON	16</div><div class='add'>+#define IMX95_PD_M7		17</div><div class='add'>+#define IMX95_PD_NETC		18</div><div class='add'>+#define IMX95_PD_NOC		19</div><div class='add'>+#define IMX95_PD_NPU		20</div><div class='add'>+#define IMX95_PD_VPU		21</div><div class='add'>+#define IMX95_PD_WAKEUP		22</div><div class='add'>+</div><div class='add'>+#define IMX95_PERF_ELE		0</div><div class='add'>+#define IMX95_PERF_M33		1</div><div class='add'>+#define IMX95_PERF_WAKEUP	2</div><div class='add'>+#define IMX95_PERF_M7		3</div><div class='add'>+#define IMX95_PERF_DRAM		4</div><div class='add'>+#define IMX95_PERF_HSIO		5</div><div class='add'>+#define IMX95_PERF_NPU		6</div><div class='add'>+#define IMX95_PERF_NOC		7</div><div class='add'>+#define IMX95_PERF_A55		8</div><div class='add'>+#define IMX95_PERF_GPU		9</div><div class='add'>+#define IMX95_PERF_VPU		10</div><div class='add'>+#define IMX95_PERF_CAM		11</div><div class='add'>+#define IMX95_PERF_DISP		12</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx95-toradex-smarc-dev.dts b/arch/arm64/boot/dts/freescale/imx95-toradex-smarc-dev.dts<br/>new file mode 100644<br/>index 000000000000..5b05f256fd52<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx95-toradex-smarc-dev.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx95-toradex-smarc-dev.dts</a></div><div class='hunk'>@@ -0,0 +1,277 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2025 Toradex</div><div class='add'>+ *</div><div class='add'>+ * https://www.toradex.com/computer-on-modules/smarc-arm-family/nxp-imx95</div><div class='add'>+ * https://www.toradex.com/products/carrier-board/smarc-development-board-kit</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/pwm/pwm.h&gt;</div><div class='add'>+#include "imx95-toradex-smarc.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Toradex SMARC iMX95 on Toradex SMARC Development Board";</div><div class='add'>+	compatible = "toradex,smarc-imx95-dev",</div><div class='add'>+		     "toradex,smarc-imx95",</div><div class='add'>+		     "fsl,imx95";</div><div class='add'>+</div><div class='add'>+	reg_carrier_1p8v: regulator-carrier-1p8v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-name = "On-carrier 1V8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "simple-audio-card";</div><div class='add'>+		simple-audio-card,bitclock-master = &lt;&amp;codec_dai&gt;;</div><div class='add'>+		simple-audio-card,format = "i2s";</div><div class='add'>+		simple-audio-card,frame-master = &lt;&amp;codec_dai&gt;;</div><div class='add'>+		simple-audio-card,mclk-fs = &lt;256&gt;;</div><div class='add'>+		simple-audio-card,name = "tdx-smarc-wm8904";</div><div class='add'>+		simple-audio-card,routing =</div><div class='add'>+			"Headphone Jack", "HPOUTL",</div><div class='add'>+			"Headphone Jack", "HPOUTR",</div><div class='add'>+			"IN2L", "Line In Jack",</div><div class='add'>+			"IN2R", "Line In Jack",</div><div class='add'>+			"Microphone Jack", "MICBIAS",</div><div class='add'>+			"IN1L", "Microphone Jack";</div><div class='add'>+		simple-audio-card,widgets =</div><div class='add'>+			"Microphone", "Microphone Jack",</div><div class='add'>+			"Headphone", "Headphone Jack",</div><div class='add'>+			"Line", "Line In Jack";</div><div class='add'>+</div><div class='add'>+		codec_dai: simple-audio-card,codec {</div><div class='add'>+			clocks = &lt;&amp;scmi_clk IMX95_CLK_SAI3&gt;;</div><div class='add'>+			sound-dai = &lt;&amp;wm8904_1a&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		simple-audio-card,cpu {</div><div class='add'>+			sound-dai = &lt;&amp;sai3&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC GBE0 */</div><div class='add'>+&amp;enetc_port0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC GBE1 */</div><div class='add'>+&amp;enetc_port1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC CAN0 */</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC CAN1 */</div><div class='add'>+&amp;flexcan2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio12&gt;, &lt;&amp;pinctrl_gpio13&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio10&gt;, &lt;&amp;pinctrl_gpio11&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio5 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio2&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_gpio3&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_gpio4&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_gpio6&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_gpio8&gt;,</div><div class='add'>+		    &lt;&amp;pinctrl_gpio9&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC I2C_CAM0 */</div><div class='add'>+&amp;i2c_cam0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC I2C_CAM1 */</div><div class='add'>+&amp;i2c_cam1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC I2C_GP */</div><div class='add'>+&amp;lpi2c2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	wm8904_1a: audio-codec@1a {</div><div class='add'>+		compatible = "wlf,wm8904";</div><div class='add'>+		reg = &lt;0x1a&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_sai3&gt;, &lt;&amp;pinctrl_sai3_mclk&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		clocks = &lt;&amp;scmi_clk IMX95_CLK_SAI3&gt;;</div><div class='add'>+		clock-names = "mclk";</div><div class='add'>+		AVDD-supply = &lt;&amp;reg_carrier_1p8v&gt;;</div><div class='add'>+		CPVDD-supply = &lt;&amp;reg_carrier_1p8v&gt;;</div><div class='add'>+		DBVDD-supply = &lt;&amp;reg_carrier_1p8v&gt;;</div><div class='add'>+		DCVDD-supply = &lt;&amp;reg_carrier_1p8v&gt;;</div><div class='add'>+		MICVDD-supply = &lt;&amp;reg_carrier_1p8v&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	temperature-sensor@4f {</div><div class='add'>+		compatible = "ti,tmp1075";</div><div class='add'>+		reg = &lt;0x4f&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@57 {</div><div class='add'>+		compatible = "st,24c02", "atmel,24c02";</div><div class='add'>+		reg = &lt;0x57&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC I2C_PM */</div><div class='add'>+&amp;lpi2c3 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	fan_controller: fan@18 {</div><div class='add'>+		compatible = "ti,amc6821";</div><div class='add'>+		reg = &lt;0x18&gt;;</div><div class='add'>+		#pwm-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		fan {</div><div class='add'>+			cooling-levels = &lt;255&gt;;</div><div class='add'>+			pwms = &lt;&amp;fan_controller 40000 PWM_POLARITY_INVERTED&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Current measurement into module VCC */</div><div class='add'>+	hwmon@40 {</div><div class='add'>+		compatible = "ti,ina226";</div><div class='add'>+		reg = &lt;0x40&gt;;</div><div class='add'>+		shunt-resistor = &lt;5000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC I2C_LCD */</div><div class='add'>+&amp;lpi2c5 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	i2c-mux@70 {</div><div class='add'>+		compatible = "nxp,pca9543";</div><div class='add'>+		reg = &lt;0x70&gt;;</div><div class='add'>+		i2c-mux-idle-disconnect;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		/* I2C on DSI Connector Pins 4/6 */</div><div class='add'>+		i2c_dsi_0: i2c@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* I2C on DSI Connector Pins 52/54 */</div><div class='add'>+		i2c_dsi_1: i2c@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC SPI0 */</div><div class='add'>+&amp;lpspi6 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC SER1, used as the Linux Console */</div><div class='add'>+&amp;lpuart1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC SER0, RS485 */</div><div class='add'>+&amp;lpuart2 {</div><div class='add'>+	linux,rs485-enabled-at-boot-time;</div><div class='add'>+	rs485-rts-active-low;</div><div class='add'>+	rs485-rx-during-tx;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC SER3, RS232 */</div><div class='add'>+&amp;lpuart3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC MDIO, shared between all ethernet ports */</div><div class='add'>+&amp;netc_emdio {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ethphy3: ethernet-phy@4 {</div><div class='add'>+		reg = &lt;4&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpio7&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio5&gt;;</div><div class='add'>+		interrupts = &lt;9 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC PCIE_A / M2 Key B */</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC PCIE_B /  M2 Key E */</div><div class='add'>+&amp;pcie1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC I2S0 */</div><div class='add'>+&amp;sai3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC LCD0_BKLT_PWM */</div><div class='add'>+&amp;tpm3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC LCD1_BKLT_PWM */</div><div class='add'>+&amp;tpm4 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC GPIO5 as PWM */</div><div class='add'>+&amp;tpm5 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC USB0 */</div><div class='add'>+&amp;usb2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC USB1..4 */</div><div class='add'>+&amp;usb3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_dwc3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC SDIO */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi b/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi<br/>new file mode 100644<br/>index 000000000000..afbdadcb3686<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi</a></div><div class='hunk'>@@ -0,0 +1,1155 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2025 Toradex</div><div class='add'>+ *</div><div class='add'>+ * https://www.toradex.com/computer-on-modules/smarc-arm-family/nxp-imx95</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/net/ti-dp83867.h&gt;</div><div class='add'>+#include "imx95.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		can0 = &amp;flexcan1;</div><div class='add'>+		can1 = &amp;flexcan2;</div><div class='add'>+		ethernet0 = &amp;enetc_port0;</div><div class='add'>+		ethernet1 = &amp;enetc_port1;</div><div class='add'>+		mmc0 = &amp;usdhc1;</div><div class='add'>+		mmc1 = &amp;usdhc2;</div><div class='add'>+		mmc2 = &amp;usdhc3;</div><div class='add'>+		rtc0 = &amp;rtc_i2c;</div><div class='add'>+		rtc1 = &amp;scmi_bbm;</div><div class='add'>+		serial0 = &amp;lpuart2;</div><div class='add'>+		serial1 = &amp;lpuart1;</div><div class='add'>+		serial3 = &amp;lpuart3;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial1:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_dsi2dp_bridge: clock-dsi2dp-bridge {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;27000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_serdes_eth_ref: clock-eth-ref {</div><div class='add'>+		compatible = "gpio-gate-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		/* CTRL_ETH_REF_CLK_STBY# */</div><div class='add'>+		enable-gpios = &lt;&amp;som_gpio_expander_1 13 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	connector {</div><div class='add'>+		compatible = "gpio-usb-b-connector", "usb-b-connector";</div><div class='add'>+		/* SMARC P64 - USB0_OTG_ID */</div><div class='add'>+		id-gpios = &lt;&amp;som_gpio_expander_0 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		label = "USB0";</div><div class='add'>+		self-powered;</div><div class='add'>+		type = "micro";</div><div class='add'>+		vbus-supply = &lt;&amp;reg_usb0_vbus&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			usb_dr_connector: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;usb0_otg_id&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		smarc_key_sleep: key-sleep {</div><div class='add'>+			gpios = &lt;&amp;som_ec_gpio_expander 4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			label = "SMARC_SLEEP#";</div><div class='add'>+			wakeup-source;</div><div class='add'>+			linux,code = &lt;KEY_SLEEP&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smarc_switch_lid: switch-lid {</div><div class='add'>+			gpios = &lt;&amp;som_ec_gpio_expander 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			label = "SMARC_LID#";</div><div class='add'>+			linux,code = &lt;SW_LID&gt;;</div><div class='add'>+			linux,input-type = &lt;EV_SW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_module_1p8v: regulator-module-1p8v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-name = "On-module +V1.8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Non PMIC On-module Supplies */</div><div class='add'>+	reg_module_dp_1p2v: regulator-module-dp-1p2v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+		regulator-name = "On-module +V1.2_DP";</div><div class='add'>+		vin-supply = &lt;&amp;reg_module_1p8v&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb0_vbus: regulator-usb0-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		/* SMARC P62 - USB0_EN_OC# */</div><div class='add'>+		gpios = &lt;&amp;som_gpio_expander_0 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-name = "USB0_EN_OC#";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb1_vbus: regulator-usb1-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		/* CTRL_V_BUS_USB_HUB or SMARC P71 - USB2_EN_OC# */</div><div class='add'>+		gpios = &lt;&amp;som_gpio_expander_0 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-name = "CTRL_V_BUS_USB_HUB";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vmmc: regulator-vmmc-usdhc2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usdhc2_pwr_en&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio3 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		off-on-delay-us = &lt;100000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "SDIO_PWR_EN";</div><div class='add'>+		startup-delay-us = &lt;20000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc {</div><div class='add'>+		compatible = "regulator-gpio";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_usdhc2_vsel&gt;;</div><div class='add'>+		gpios = &lt;&amp;gpio3 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		states = &lt;1800000 0x1&gt;,</div><div class='add'>+			 &lt;3300000 0x0&gt;;</div><div class='add'>+		regulator-name = "PMIC_SD2_VSEL";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_wifi_en: regulator-wifi-en {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		/* CTRL_EN_WIFI */</div><div class='add'>+		gpios = &lt;&amp;som_gpio_expander_1 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-name = "CTRL_EN_WIFI";</div><div class='add'>+		startup-delay-us = &lt;2000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		linux_cma: linux,cma {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reusable;</div><div class='add'>+			size = &lt;0 0x3c000000&gt;;</div><div class='add'>+			alloc-ranges = &lt;0 0x80000000 0 0x7F000000&gt;;</div><div class='add'>+			linux,cma-default;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC GBE0 */</div><div class='add'>+&amp;enetc_port0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_enetc0&gt;, &lt;&amp;pinctrl_enetc0_1588_tmr&gt;;</div><div class='add'>+	phy-handle = &lt;&amp;ethphy1&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC GBE1 */</div><div class='add'>+&amp;enetc_port1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_enetc1&gt;, &lt;&amp;pinctrl_enetc1_1588_tmr&gt;;</div><div class='add'>+	phy-handle = &lt;&amp;ethphy2&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC CAN0 */</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC CAN1 */</div><div class='add'>+&amp;flexcan2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	gpio-line-names = "", /* 0 */</div><div class='add'>+			  "",</div><div class='add'>+			  "SMARC_I2C_GP_CK",</div><div class='add'>+			  "SMARC_I2C_GP_DAT",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "", /* 10 */</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "CTRL_IO_EXP_INT_B";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio2 {</div><div class='add'>+	gpio-line-names = "SMARC_SPI0_CS0#", /* 0 */</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "SMARC_GPIO5",</div><div class='add'>+			  "",</div><div class='add'>+			  "I2C_CAM_DAT",</div><div class='add'>+			  "I2C_CAM_CK",</div><div class='add'>+			  "SMARC_GPIO12", /* 10 */</div><div class='add'>+			  "SMARC_GPIO13",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "SMARC_SPI1_CS0#",</div><div class='add'>+			  "",</div><div class='add'>+			  "", /* 20 */</div><div class='add'>+			  "",</div><div class='add'>+			  "SMARC_I2C_LCD_DAT",</div><div class='add'>+			  "SMARC_I2C_LCD_CK",</div><div class='add'>+			  "SMARC_SPI0_CS1#",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "SMARC_I2C_PM_DAT",</div><div class='add'>+			  "SMARC_I2C_PM_CK",</div><div class='add'>+			  "I2C_SOM_DAT", /* 30 */</div><div class='add'>+			  "I2C_SOM_CK";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio3 {</div><div class='add'>+	gpio-line-names = "SMARC_SDIO_CD#", /* 0 */</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "SMARC_SDIO_PWR_EN",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "", /* 10 */</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "PMIC_SD2_VSEL";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	gpio-line-names = "", /* 0 */</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "", /* 10 */</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "SMARC_GPIO11",</div><div class='add'>+			  "SMARC_GPIO10",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "", /* 20 */</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "SMARC_SMB_ALERT#";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio5 {</div><div class='add'>+	gpio-line-names = "SMARC_GPIO2", /* 0 */</div><div class='add'>+			  "SMARC_GPIO3",</div><div class='add'>+			  "SMARC_GPIO4",</div><div class='add'>+			  "SMARC_GPIO6",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "SMARC_GPIO9",</div><div class='add'>+			  "SMARC_GPIO7",</div><div class='add'>+			  "SMARC_GPIO8", /* 10 */</div><div class='add'>+			  "SMARC_SPI1_CS1#",</div><div class='add'>+			  "",</div><div class='add'>+			  "SPI1_TPM_CS#";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC I2C_GP */</div><div class='add'>+&amp;lpi2c2 {</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c2&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_lpi2c2_gpio&gt;;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	eeprom@50 {</div><div class='add'>+		compatible = "st,24c32", "atmel,24c32";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC I2C_PM */</div><div class='add'>+&amp;lpi2c3 {</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_lpi2c3_gpio&gt;;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* I2C_SOM */</div><div class='add'>+&amp;lpi2c4 {</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c4&gt;, &lt;&amp;pinctrl_ctrl_io_exp_int_b&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_lpi2c4_gpio&gt;, &lt;&amp;pinctrl_ctrl_io_exp_int_b&gt;;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio2 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	som_gpio_expander_0: gpio@20 {</div><div class='add'>+		compatible = "nxp,pcal6408";</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;14 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		gpio-line-names =</div><div class='add'>+			"SMARC_PCIE_WAKE#", /* 0 */</div><div class='add'>+			"SMARC_PCIE_B_RST#",</div><div class='add'>+			"SMARC_PCIE_A_RST#",</div><div class='add'>+			"SMARC_USB0_OTG_ID",</div><div class='add'>+			"SMARC_USB0_EN", /* SMARC USB0_EN_OC# - Open Drain Output */</div><div class='add'>+			"SMARC_USB0_OC#", /* SMARC USB0_EN_OC# - Over-Current Sense Input */</div><div class='add'>+			"",</div><div class='add'>+			"SMARC_PCIE_C_RST#";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	som_gpio_expander_1: gpio@21 {</div><div class='add'>+		compatible = "nxp,pcal6416";</div><div class='add'>+		reg = &lt;0x21&gt;;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;14 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		gpio-line-names =</div><div class='add'>+			"SMARC_GPIO0", /* 0 */</div><div class='add'>+			"SMARC_GPIO1",</div><div class='add'>+			"SMARC_LCD0_VDD_EN",</div><div class='add'>+			"SMARC_LCD0_BKLT_EN",</div><div class='add'>+			"SMARC_LCD1_VDD_EN",</div><div class='add'>+			"SMARC_LCD1_BKLT_EN",</div><div class='add'>+			"",</div><div class='add'>+			"",</div><div class='add'>+			"",</div><div class='add'>+			"",</div><div class='add'>+			"", /* 10 */</div><div class='add'>+			"",</div><div class='add'>+			"",</div><div class='add'>+			"",</div><div class='add'>+			"",</div><div class='add'>+			"",</div><div class='add'>+			"",</div><div class='add'>+			"SMARC_SDIO_WP";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	embedded-controller@28 {</div><div class='add'>+		compatible = "toradex,smarc-imx95-ec", "toradex,smarc-ec";</div><div class='add'>+		reg = &lt;0x28&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	som_ec_gpio_expander: gpio@29 {</div><div class='add'>+		compatible = "toradex,ecgpiol16", "nxp,pcal6416";</div><div class='add'>+		reg = &lt;0x29&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_ec_int&gt;;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;11 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		gpio-line-names =</div><div class='add'>+			"SMARC_CHARGER_PRSNT#",</div><div class='add'>+			"SMARC_CHARGING#",</div><div class='add'>+			"SMARC_LID#",</div><div class='add'>+			"SMARC_BATLOW#",</div><div class='add'>+			"SMARC_SLEEP#";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC DP0 */</div><div class='add'>+	som_dsi2dp_bridge: bridge@2c {</div><div class='add'>+		compatible = "ti,sn65dsi86";</div><div class='add'>+		reg = &lt;0x2c&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk_dsi2dp_bridge&gt;;</div><div class='add'>+		clock-names = "refclk";</div><div class='add'>+		vcc-supply = &lt;&amp;reg_module_dp_1p2v&gt;;</div><div class='add'>+		vcca-supply = &lt;&amp;reg_module_dp_1p2v&gt;;</div><div class='add'>+		vccio-supply = &lt;&amp;reg_module_1p8v&gt;;</div><div class='add'>+		vpll-supply = &lt;&amp;reg_module_1p8v&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				sn65dsi86_in: endpoint {</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				sn65dsi86_out: endpoint {</div><div class='add'>+					data-lanes = &lt;3 2 1 0&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rtc_i2c: rtc@32 {</div><div class='add'>+		compatible = "epson,rx8130";</div><div class='add'>+		reg = &lt;0x32&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	temperature-sensor@48 {</div><div class='add'>+		compatible = "ti,tmp1075";</div><div class='add'>+		reg = &lt;0x48&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@50 {</div><div class='add'>+		compatible = "st,24c02", "atmel,24c02";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC I2C_LCD */</div><div class='add'>+&amp;lpi2c5 {</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c5&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_lpi2c5_gpio&gt;;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio2 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio2 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* I2C_CAM */</div><div class='add'>+&amp;lpi2c7 {</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c7&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_lpi2c7_gpio&gt;;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio2 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio2 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	i2c-mux@70 {</div><div class='add'>+		compatible = "nxp,pca9543";</div><div class='add'>+		reg = &lt;0x70&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		/* SMARC I2C_CAM0 */</div><div class='add'>+		i2c_cam0: i2c@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* SMARC I2C_CAM1 */</div><div class='add'>+		i2c_cam1: i2c@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC SPI1 */</div><div class='add'>+&amp;lpspi4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpspi4&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio2 18 GPIO_ACTIVE_LOW&gt;,</div><div class='add'>+		   &lt;&amp;gpio5 11 GPIO_ACTIVE_LOW&gt;,</div><div class='add'>+		   &lt;&amp;gpio5 13 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	som_tpm: tpm@2 {</div><div class='add'>+		compatible = "infineon,slb9670", "tcg,tpm_tis-spi";</div><div class='add'>+		reg = &lt;0x2&gt;;</div><div class='add'>+		spi-max-frequency = &lt;18500000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC SPI0 */</div><div class='add'>+&amp;lpspi6 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpspi6&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio2 0 GPIO_ACTIVE_LOW&gt;,</div><div class='add'>+		   &lt;&amp;gpio2 24 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC SER1, used as the Linux Console */</div><div class='add'>+&amp;lpuart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC SER0 */</div><div class='add'>+&amp;lpuart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC SER3 */</div><div class='add'>+&amp;lpuart3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC MDIO, shared between all ethernet ports */</div><div class='add'>+&amp;netc_emdio {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_emdio&gt;;</div><div class='add'>+</div><div class='add'>+	ethphy1: ethernet-phy@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;som_gpio_expander_1&gt;;</div><div class='add'>+		interrupts = &lt;6 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_2_00_NS&gt;;</div><div class='add'>+		ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_2_00_NS&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ethphy2: ethernet-phy@2 {</div><div class='add'>+		reg = &lt;2&gt;;</div><div class='add'>+		ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_2_00_NS&gt;;</div><div class='add'>+		ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_2_00_NS&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;netcmix_blk_ctrl {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;netc_blk_ctrl {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;netc_timer {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC PCIE_A */</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	reset-gpios = &lt;&amp;som_gpio_expander_0 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC PCIE_B */</div><div class='add'>+&amp;pcie1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie1&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	reset-gpios = &lt;&amp;som_gpio_expander_0 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC I2S0 */</div><div class='add'>+&amp;sai3 {</div><div class='add'>+	#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL1_VCO&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL2_VCO&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL1&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL2&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_SAI3&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;, &lt;0&gt;,</div><div class='add'>+				 &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL1&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;3932160000&gt;,</div><div class='add'>+			       &lt;3612672000&gt;, &lt;393216000&gt;,</div><div class='add'>+			       &lt;361267200&gt;, &lt;12288000&gt;;</div><div class='add'>+	fsl,sai-mclk-direction-output;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;thermal_zones {</div><div class='add'>+	/* PF09 Main PMIC */</div><div class='add'>+	pf09-thermal {</div><div class='add'>+		polling-delay = &lt;2000&gt;;</div><div class='add'>+		polling-delay-passive = &lt;250&gt;;</div><div class='add'>+		thermal-sensors = &lt;&amp;scmi_sensor 2&gt;;</div><div class='add'>+</div><div class='add'>+		trips {</div><div class='add'>+			trip0 {</div><div class='add'>+				hysteresis = &lt;2000&gt;;</div><div class='add'>+				temperature = &lt;155000&gt;;</div><div class='add'>+				type = "critical";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PF53 VDD_ARM PMIC */</div><div class='add'>+	pf53-arm-thermal {</div><div class='add'>+		polling-delay = &lt;2000&gt;;</div><div class='add'>+		polling-delay-passive = &lt;250&gt;;</div><div class='add'>+		thermal-sensors = &lt;&amp;scmi_sensor 4&gt;;</div><div class='add'>+</div><div class='add'>+		trips {</div><div class='add'>+			trip0 {</div><div class='add'>+				hysteresis = &lt;2000&gt;;</div><div class='add'>+				temperature = &lt;155000&gt;;</div><div class='add'>+				type = "critical";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PF53 VDD_SOC PMIC */</div><div class='add'>+	pf53-soc-thermal {</div><div class='add'>+		polling-delay = &lt;2000&gt;;</div><div class='add'>+		polling-delay-passive = &lt;250&gt;;</div><div class='add'>+		thermal-sensors = &lt;&amp;scmi_sensor 3&gt;;</div><div class='add'>+</div><div class='add'>+		trips {</div><div class='add'>+			trip0 {</div><div class='add'>+				hysteresis = &lt;2000&gt;;</div><div class='add'>+				temperature = &lt;155000&gt;;</div><div class='add'>+				type = "critical";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC LCD0_BKLT_PWM */</div><div class='add'>+&amp;tpm3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lcd0_bklt_pwm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC LCD1_BKLT_PWM */</div><div class='add'>+&amp;tpm4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lcd1_bklt_pwm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC GPIO5 as PWM */</div><div class='add'>+&amp;tpm5 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio5_pwm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC USB0 */</div><div class='add'>+&amp;usb2 {</div><div class='add'>+	adp-disable;</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	hnp-disable;</div><div class='add'>+	srp-disable;</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usb0_vbus&gt;;</div><div class='add'>+</div><div class='add'>+	port {</div><div class='add'>+		usb0_otg_id: endpoint {</div><div class='add'>+			remote-endpoint = &lt;&amp;usb_dr_connector&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3 {</div><div class='add'>+	fsl,disable-port-power-control;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC USB1..4  */</div><div class='add'>+&amp;usb3_dwc3 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy {</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usb1_vbus&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* On-module eMMC */</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1_200mhz&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	no-sdio;</div><div class='add'>+	no-sd;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMARC SDIO */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_cd&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_cd&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;,&lt;&amp;pinctrl_usdhc2_cd&gt;;</div><div class='add'>+	pinctrl-3 = &lt;&amp;pinctrl_usdhc2_sleep&gt;, &lt;&amp;pinctrl_usdhc2_cd&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio3 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_usdhc2_vqmmc&gt;;</div><div class='add'>+	wp-gpios = &lt;&amp;som_gpio_expander_1 15 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* On-module Wi-Fi */</div><div class='add'>+&amp;usdhc3 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc3&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc3_200mhz&gt;;</div><div class='add'>+	keep-power-in-suspend;</div><div class='add'>+	non-removable;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_wifi_en&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;scmi_bbm {</div><div class='add'>+	linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog3 {</div><div class='add'>+	fsl,ext-reset-output;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;scmi_iomuxc {</div><div class='add'>+	/* SMARC CAM_MCK */</div><div class='add'>+	pinctrl_cam_mck: cammckgrp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_CCM_CLKO1__CCMSRCGPCMIX_TOP_CLKO_1	0x51e&gt;; /* SMARC S6 - CAM_MCK */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ec_int: ecintgrp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_SAI1_TXFS__AONMIX_TOP_GPIO1_IO_BIT11	0x31e&gt;; /* SAI1_TXFS - EC_MCU_INT# */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC MDIO, shared between all ethernet ports */</div><div class='add'>+	pinctrl_emdio: emdiogrp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC		0x50e&gt;, /* SMARC S45 - MDIO_CLK */</div><div class='add'>+			   &lt;IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO		0x90e&gt;; /* SMARC S46 - MDIO_DAT */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC GBE0 */</div><div class='add'>+	pinctrl_enetc0: enetc0grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL	0x57e&gt;, /* ENET1_TX_CTL */</div><div class='add'>+			   &lt;IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK		0x58e&gt;, /* ENET1_TXC    */</div><div class='add'>+			   &lt;IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0		0x50e&gt;, /* ENET1_TDO    */</div><div class='add'>+			   &lt;IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1		0x50e&gt;, /* ENET1_TD1    */</div><div class='add'>+			   &lt;IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2		0x50e&gt;, /* ENET1_TD2    */</div><div class='add'>+			   &lt;IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3		0x50e&gt;, /* ENET1_TD3    */</div><div class='add'>+			   &lt;IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL	0x57e&gt;, /* ENET1_RX_CTL */</div><div class='add'>+			   &lt;IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK		0x58e&gt;, /* ENET1_RXC    */</div><div class='add'>+			   &lt;IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0		0x57e&gt;, /* ENET1_RD0    */</div><div class='add'>+			   &lt;IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1		0x57e&gt;, /* ENET1_RD1    */</div><div class='add'>+			   &lt;IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2		0x57e&gt;, /* ENET1_RD2    */</div><div class='add'>+			   &lt;IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3		0x57e&gt;; /* ENET1_RD3    */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC GBE0_SDP */</div><div class='add'>+	pinctrl_enetc0_1588_tmr: enetc01588tmrgrp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_CCM_CLKO2__NETCMIX_TOP_NETC_TMR_1588_PP1	0x51e&gt;; /* SMARC P6 - GBE0_SDP */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC GBE1 */</div><div class='add'>+	pinctrl_enetc1: enetc1grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL	0x57e&gt;, /* ENET2_TX_CTL */</div><div class='add'>+			   &lt;IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK		0x58e&gt;, /* ENET2_TXC    */</div><div class='add'>+			   &lt;IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0		0x50e&gt;, /* ENET2_TD0    */</div><div class='add'>+			   &lt;IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1		0x50e&gt;, /* ENET2_TD1    */</div><div class='add'>+			   &lt;IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2		0x50e&gt;, /* ENET2_TD2    */</div><div class='add'>+			   &lt;IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3		0x50e&gt;, /* ENET2_TD3    */</div><div class='add'>+			   &lt;IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL	0x57e&gt;, /* ENET2_RX_CTL */</div><div class='add'>+			   &lt;IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK		0x58e&gt;, /* ENET2_RXC    */</div><div class='add'>+			   &lt;IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0		0x57e&gt;, /* ENET2_RD0    */</div><div class='add'>+			   &lt;IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1		0x57e&gt;, /* ENET2_RD1    */</div><div class='add'>+			   &lt;IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2		0x57e&gt;, /* ENET2_RD2    */</div><div class='add'>+			   &lt;IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3		0x57e&gt;; /* ENET2_RD3    */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC GBE1_SDP */</div><div class='add'>+	pinctrl_enetc1_1588_tmr: enetc11588tmrgrp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_CCM_CLKO4__NETCMIX_TOP_NETC_TMR_1588_PP2	0x51e&gt;; /* SMARC P5 - GBE1_SDP */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC CAN0 */</div><div class='add'>+	pinctrl_flexcan1: flexcan1grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX		0x39e&gt;, /* SMARC P143 - CAN0_TX */</div><div class='add'>+			   &lt;IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX	0x39e&gt;; /* SMARC P144 - CAN0_RX */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC CAN1 */</div><div class='add'>+	pinctrl_flexcan2: flexcan2grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_GPIO_IO25__CAN2_TX	0x39e&gt;, /* SMARC P145 - CAN1_TX */</div><div class='add'>+			   &lt;IMX95_PAD_GPIO_IO27__CAN2_RX	0x39e&gt;; /* SMARC P146 - CAN1_RX */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC GPIO2 */</div><div class='add'>+	pinctrl_gpio2: gpio2grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_XSPI1_DATA0__GPIO5_IO_BIT0	0x31e&gt;; /* SMARC P110 - GPIO2 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC GPIO3 */</div><div class='add'>+	pinctrl_gpio3: gpio3grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_XSPI1_DATA1__GPIO5_IO_BIT1	0x31e&gt;; /* SMARC P111 - GPIO3 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC GPIO4 */</div><div class='add'>+	pinctrl_gpio4: gpio4grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_XSPI1_DATA2__GPIO5_IO_BIT2	0x31e&gt;; /* SMARC P112 - GPIO4 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC GPIO5 */</div><div class='add'>+	pinctrl_gpio5: gpio5grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_GPIO_IO06__GPIO2_IO_BIT6	0x31e&gt;; /* SMARC P113 - GPIO5 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC GPIO5 as PWM */</div><div class='add'>+	pinctrl_gpio5_pwm: gpio5pwmgrp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_GPIO_IO06__TPM5_CH0	0x11e&gt;; /* SMARC P113 - PWM_OUT */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC GPIO6 */</div><div class='add'>+	pinctrl_gpio6: gpio6grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_XSPI1_DATA3__GPIO5_IO_BIT3	0x31e&gt;; /* SMARC P114 - GPIO6 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC GPIO7 */</div><div class='add'>+	pinctrl_gpio7: gpio7grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_XSPI1_SCLK__GPIO5_IO_BIT9 0x31e&gt;; /* SMARC P115 - GPIO7 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC GPIO8 */</div><div class='add'>+	pinctrl_gpio8: gpio8grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_XSPI1_SS0_B__GPIO5_IO_BIT10	0x31e&gt;; /* SMARC P116 - GPIO8 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC GPIO9 */</div><div class='add'>+	pinctrl_gpio9: gpio9grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_XSPI1_DQS__GPIO5_IO_BIT8	0x31e&gt;; /* SMARC P117 - GPIO9 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC GPIO10 */</div><div class='add'>+	pinctrl_gpio10: gpio10grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_ENET2_MDIO__GPIO4_IO_BIT15	0x31e&gt;; /* SMARC P118 - GPIO10 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC GPIO11 */</div><div class='add'>+	pinctrl_gpio11: gpio11grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_ENET2_MDC__GPIO4_IO_BIT14	0x31e&gt;; /* SMARC P119 - GPIO11 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC GPIO12 */</div><div class='add'>+	pinctrl_gpio12: gpio12grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_GPIO_IO10__GPIO2_IO_BIT10	0x31e&gt;; /* SMARC S142 - GPIO12 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC GPIO13 */</div><div class='add'>+	pinctrl_gpio13: gpio13grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_GPIO_IO11__GPIO2_IO_BIT11	0x31e&gt;; /* SMARC S123 - GPIO13 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ctrl_io_exp_int_b: ioexpintgrp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_SAI1_RXD0__AONMIX_TOP_GPIO1_IO_BIT14 0x31e&gt;; /* CTRL_IO_EXP_INT_B */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC LCD0_BKLT_PWM */</div><div class='add'>+	pinctrl_lcd0_bklt_pwm: lcd0bkltpwmgrp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_GPIO_IO12__TPM3_CH2	0x51e&gt;; /* SMARC S141 - LCD0_BKLT_PWM */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC LCD1_BKLT_PWM */</div><div class='add'>+	pinctrl_lcd1_bklt_pwm: lcd1bkltpwmgrp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_GPIO_IO13__TPM4_CH2	0x51e&gt;; /* SMARC S122 - LCD1_BKLT_PWM */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC I2C_GP */</div><div class='add'>+	pinctrl_lpi2c2: lpi2c2grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL	0x40001b9e&gt;, /* SMARC S48 - I2C_GP_CK  */</div><div class='add'>+			   &lt;IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA	0x40001b9e&gt;; /* SMARC S49 - I2C_GP_DAT */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC I2C_GP as GPIOs */</div><div class='add'>+	pinctrl_lpi2c2_gpio: lpi2c2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_I2C2_SCL__AONMIX_TOP_GPIO1_IO_BIT2	0x40001b9e&gt;, /* SMARC S48 - I2C_GP_CK  */</div><div class='add'>+			   &lt;IMX95_PAD_I2C2_SDA__AONMIX_TOP_GPIO1_IO_BIT3	0x40001b9e&gt;; /* SMARC S49 - I2C_GP_DAT */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC I2C_PM */</div><div class='add'>+	pinctrl_lpi2c3: lpi2c3grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_GPIO_IO28__LPI2C3_SDA	0x40001b9e&gt;, /* SMARC P122 - I2C_PM_DAT */</div><div class='add'>+			   &lt;IMX95_PAD_GPIO_IO29__LPI2C3_SCL	0x40001b9e&gt;; /* SMARC P121 - I2C_PM_CK  */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC I2C_PM as GPIOs */</div><div class='add'>+	pinctrl_lpi2c3_gpio: lpi2c3gpiogrp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_GPIO_IO28__GPIO2_IO_BIT28	0x40001b9e&gt;, /* SMARC P122 - I2C_PM_DAT */</div><div class='add'>+			   &lt;IMX95_PAD_GPIO_IO29__GPIO2_IO_BIT29	0x40001b9e&gt;; /* SMARC P121 - I2C_PM_CK  */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* I2C_SOM */</div><div class='add'>+	pinctrl_lpi2c4: lpi2c4grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_GPIO_IO31__LPI2C4_SCL	0x40001b9e&gt;, /* I2C_SOM_CK  */</div><div class='add'>+			   &lt;IMX95_PAD_GPIO_IO30__LPI2C4_SDA	0x40001b9e&gt;; /* I2C_SOM_DAT */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* I2C_SOM as GPIOs */</div><div class='add'>+	pinctrl_lpi2c4_gpio: lpi2c4gpiogrp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_GPIO_IO31__GPIO2_IO_BIT31	0x40001b9e&gt;, /* I2C_SOM_CK  */</div><div class='add'>+			   &lt;IMX95_PAD_GPIO_IO30__GPIO2_IO_BIT30	0x40001b9e&gt;; /* I2C_SOM_DAT */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC I2C_LCD */</div><div class='add'>+	pinctrl_lpi2c5: lpi2c5grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_GPIO_IO22__LPI2C5_SDA	0x40001b9e&gt;, /* SMARC S140 - I2C_LCD_DAT */</div><div class='add'>+			   &lt;IMX95_PAD_GPIO_IO23__LPI2C5_SCL	0x40001b9e&gt;; /* SMARC S139 - I2C_LCD_CK  */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC I2C_LCD as GPIOs */</div><div class='add'>+	pinctrl_lpi2c5_gpio: lpi2c5gpiogrp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_GPIO_IO22__GPIO2_IO_BIT22	0x40001b9e&gt;, /* SMARC S140 - I2C_LCD_DAT */</div><div class='add'>+			   &lt;IMX95_PAD_GPIO_IO23__GPIO2_IO_BIT23	0x40001b9e&gt;; /* SMARC S139 - I2C_LCD_CK  */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* I2C_CAM */</div><div class='add'>+	pinctrl_lpi2c7: lpi2c7grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_GPIO_IO08__LPI2C7_SDA	0x40001b9e&gt;, /* I2C_CAM_DAT */</div><div class='add'>+			   &lt;IMX95_PAD_GPIO_IO09__LPI2C7_SCL	0x40001b9e&gt;; /* I2C_CAM_CK  */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* I2C_CAM as GPIOs */</div><div class='add'>+	pinctrl_lpi2c7_gpio: lpi2c7gpiogrp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_GPIO_IO08__GPIO2_IO_BIT8	0x40001b9e&gt;, /* I2C_CAM_DAT */</div><div class='add'>+			   &lt;IMX95_PAD_GPIO_IO09__GPIO2_IO_BIT9	0x40001b9e&gt;; /* I2C_CAM_CK  */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC SPI1 */</div><div class='add'>+	pinctrl_lpspi4: lpspi4grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_GPIO_IO37__LPSPI4_SCK		0x3fe&gt;, /* SMARC P56 - SPI1_CK   */</div><div class='add'>+			   &lt;IMX95_PAD_GPIO_IO36__LPSPI4_SOUT		0x3fe&gt;, /* SMARC P58 - SPI1_DO   */</div><div class='add'>+			   &lt;IMX95_PAD_GPIO_IO19__LPSPI4_SIN		0x3fe&gt;, /* SMARC P57 - SPI1_DIN  */</div><div class='add'>+			   &lt;IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13		0x3fe&gt;, /* SPI1_TPM_CS#          */</div><div class='add'>+			   &lt;IMX95_PAD_GPIO_IO18__GPIO2_IO_BIT18		0x3fe&gt;, /* SMARC P54 - SPI1_CS0# */</div><div class='add'>+			   &lt;IMX95_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11	0x3fe&gt;; /* SMARC P55 - SPI1_CS1# */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC SPI0 */</div><div class='add'>+	pinctrl_lpspi6: lpspi6grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_GPIO_IO00__GPIO2_IO_BIT0		0x3fe&gt;, /* SMARC P43 - SPI0_CS0# */</div><div class='add'>+			   &lt;IMX95_PAD_GPIO_IO24__GPIO2_IO_BIT24		0x3fe&gt;, /* SMARC P31 - SPI0_CS1# */</div><div class='add'>+			   &lt;IMX95_PAD_GPIO_IO01__LPSPI6_SIN		0x3fe&gt;, /* SMARC P45 - SPI0_DIN  */</div><div class='add'>+			   &lt;IMX95_PAD_GPIO_IO02__LPSPI6_SOUT		0x3fe&gt;, /* SMARC P46 - SPI0_DO   */</div><div class='add'>+			   &lt;IMX95_PAD_GPIO_IO03__LPSPI6_SCK		0x3fe&gt;; /* SMARC P44 - SPI0_CK   */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC PCIE_A */</div><div class='add'>+	pinctrl_pcie0: pcie0grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B	0x40001b1e&gt;; /* SMARC P78 - PCIE_A_CKREQ# */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC PCIE_B */</div><div class='add'>+	pinctrl_pcie1: pcie1grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B	0x40001b1e&gt;; /* SMARC P77 - PCIE_B_CKREQ# */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC I2S0 */</div><div class='add'>+	pinctrl_sai3: sai3grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK		0x11e&gt;, /* SMARC S38 - I2S0_CK */</div><div class='add'>+			   &lt;IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0	0x11e&gt;, /* SMARC S41 - I2S0_SDIN */</div><div class='add'>+			   &lt;IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0	0x11e&gt;, /* SMARC S40 - I2S0_SDOUT */</div><div class='add'>+			   &lt;IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC		0x11e&gt;; /* SMARC S39 - I2S0_LRCK */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC AUDIO_MCK */</div><div class='add'>+	pinctrl_sai3_mclk: sai3mclkgrp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_GPIO_IO17__SAI3_MCLK	0x31e&gt;; /* SMARC S42 - AUDIO_MCK */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC I2S2 */</div><div class='add'>+	pinctrl_sai5: sai5grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_XSPI1_DATA6__SAI5_TX_BCLK		0x11e&gt;, /* SMARC S53 - I2S2_CK */</div><div class='add'>+			   &lt;IMX95_PAD_XSPI1_DATA4__SAI5_TX_DATA_BIT0	0x11e&gt;, /* SMARC S51 - I2S2_SDOUT */</div><div class='add'>+			   &lt;IMX95_PAD_XSPI1_DATA7__SAI5_RX_DATA_BIT0	0x11e&gt;, /* SMARC S52 - I2S2_SDIN */</div><div class='add'>+			   &lt;IMX95_PAD_XSPI1_DATA5__SAI5_TX_SYNC		0x11e&gt;; /* SMARC S50 - I2S2_LRCK */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC SMB_ALERT# */</div><div class='add'>+	pinctrl_smb_alert_gpio: smbalertgrp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_CCM_CLKO3__GPIO4_IO_BIT28	0x31e&gt;; /* SMARC P1 - SMB_ALERT# */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC SER1, used as the Linux Console */</div><div class='add'>+	pinctrl_uart1: uart1grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX	0x31e&gt;, /* SMARC P134 - SER1_TX */</div><div class='add'>+			   &lt;IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX	0x31e&gt;; /* SMARC P135 - SER1_RX */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC SER0 */</div><div class='add'>+	pinctrl_uart2: uart2grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_SAI1_TXC__AONMIX_TOP_LPUART2_CTS_B	0x31e&gt;, /* SMARC P132 - SER0_CTS# */</div><div class='add'>+			   &lt;IMX95_PAD_SAI1_TXD0__AONMIX_TOP_LPUART2_RTS_B	0x31e&gt;, /* SMARC P131 - SER0_RTS# */</div><div class='add'>+			   &lt;IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART2_RX		0x31e&gt;, /* SMARC P130 - SER0_RX   */</div><div class='add'>+			   &lt;IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART2_TX		0x31e&gt;; /* SMARC P129 - SER0_TX   */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC SER3 */</div><div class='add'>+	pinctrl_uart3: uart3grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_GPIO_IO14__LPUART3_TX	0x31e&gt;, /* SMARC P140 - SER3_TX */</div><div class='add'>+			   &lt;IMX95_PAD_GPIO_IO15__LPUART3_RX	0x31e&gt;; /* SMARC P141 - SER3_RX */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* On-module eMMC */</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_SD1_CLK__USDHC1_CLK	0x158e&gt;, /* SD1_CLK    */</div><div class='add'>+			   &lt;IMX95_PAD_SD1_CMD__USDHC1_CMD	0x138e&gt;, /* SD1_CMD    */</div><div class='add'>+			   &lt;IMX95_PAD_SD1_DATA0__USDHC1_DATA0	0x138e&gt;, /* SD1_DATA0  */</div><div class='add'>+			   &lt;IMX95_PAD_SD1_DATA1__USDHC1_DATA1	0x138e&gt;, /* SD1_DATA1  */</div><div class='add'>+			   &lt;IMX95_PAD_SD1_DATA2__USDHC1_DATA2	0x138e&gt;, /* SD1_DATA2  */</div><div class='add'>+			   &lt;IMX95_PAD_SD1_DATA3__USDHC1_DATA3	0x138e&gt;, /* SD1_DATA3  */</div><div class='add'>+			   &lt;IMX95_PAD_SD1_DATA4__USDHC1_DATA4	0x138e&gt;, /* SD1_DATA4  */</div><div class='add'>+			   &lt;IMX95_PAD_SD1_DATA5__USDHC1_DATA5	0x138e&gt;, /* SD1_DATA5  */</div><div class='add'>+			   &lt;IMX95_PAD_SD1_DATA6__USDHC1_DATA6	0x138e&gt;, /* SD1_DATA6  */</div><div class='add'>+			   &lt;IMX95_PAD_SD1_DATA7__USDHC1_DATA7	0x138e&gt;, /* SD1_DATA7  */</div><div class='add'>+			   &lt;IMX95_PAD_SD1_STROBE__USDHC1_STROBE	0x158e&gt;; /* SD1_STROBE */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_SD1_CLK__USDHC1_CLK	0x15fe&gt;, /* SD1_CLK    */</div><div class='add'>+			   &lt;IMX95_PAD_SD1_CMD__USDHC1_CMD	0x13fe&gt;, /* SD1_CMD    */</div><div class='add'>+			   &lt;IMX95_PAD_SD1_DATA0__USDHC1_DATA0	0x13fe&gt;, /* SD1_DATA0  */</div><div class='add'>+			   &lt;IMX95_PAD_SD1_DATA1__USDHC1_DATA1	0x13fe&gt;, /* SD1_DATA1  */</div><div class='add'>+			   &lt;IMX95_PAD_SD1_DATA2__USDHC1_DATA2	0x13fe&gt;, /* SD1_DATA2  */</div><div class='add'>+			   &lt;IMX95_PAD_SD1_DATA3__USDHC1_DATA3	0x13fe&gt;, /* SD1_DATA3  */</div><div class='add'>+			   &lt;IMX95_PAD_SD1_DATA4__USDHC1_DATA4	0x13fe&gt;, /* SD1_DATA4  */</div><div class='add'>+			   &lt;IMX95_PAD_SD1_DATA5__USDHC1_DATA5	0x13fe&gt;, /* SD1_DATA5  */</div><div class='add'>+			   &lt;IMX95_PAD_SD1_DATA6__USDHC1_DATA6	0x13fe&gt;, /* SD1_DATA6  */</div><div class='add'>+			   &lt;IMX95_PAD_SD1_DATA7__USDHC1_DATA7	0x13fe&gt;, /* SD1_DATA7  */</div><div class='add'>+			   &lt;IMX95_PAD_SD1_STROBE__USDHC1_STROBE	0x15fe&gt;; /* SD1_STROBE */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC SDIO */</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_SD2_CLK__USDHC2_CLK		0x158e&gt;, /* SMARC P36 - SDIO_CK  */</div><div class='add'>+			   &lt;IMX95_PAD_SD2_CMD__USDHC2_CMD		0x138e&gt;, /* SMARC P34 - SDIO_CMD */</div><div class='add'>+			   &lt;IMX95_PAD_SD2_DATA0__USDHC2_DATA0		0x138e&gt;, /* SMARC P39 - SDIO_D0  */</div><div class='add'>+			   &lt;IMX95_PAD_SD2_DATA1__USDHC2_DATA1		0x138e&gt;, /* SMARC P40 - SDIO_D1  */</div><div class='add'>+			   &lt;IMX95_PAD_SD2_DATA2__USDHC2_DATA2		0x138e&gt;, /* SMARC P41 - SDIO_D2  */</div><div class='add'>+			   &lt;IMX95_PAD_SD2_DATA3__USDHC2_DATA3		0x138e&gt;; /* SMARC P42 - SDIO_D3  */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC SDIO */</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_SD2_CLK__USDHC2_CLK		0x15fe&gt;, /* SMARC P36 - SDIO_CK  */</div><div class='add'>+			   &lt;IMX95_PAD_SD2_CMD__USDHC2_CMD		0x13fe&gt;, /* SMARC P34 - SDIO_CMD */</div><div class='add'>+			   &lt;IMX95_PAD_SD2_DATA0__USDHC2_DATA0		0x13fe&gt;, /* SMARC P39 - SDIO_D0  */</div><div class='add'>+			   &lt;IMX95_PAD_SD2_DATA1__USDHC2_DATA1		0x13fe&gt;, /* SMARC P40 - SDIO_D1  */</div><div class='add'>+			   &lt;IMX95_PAD_SD2_DATA2__USDHC2_DATA2		0x13fe&gt;, /* SMARC P41 - SDIO_D2  */</div><div class='add'>+			   &lt;IMX95_PAD_SD2_DATA3__USDHC2_DATA3		0x13fe&gt;; /* SMARC P42 - SDIO_D3  */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC SDIO */</div><div class='add'>+	pinctrl_usdhc2_sleep: usdhc2-sleepgrp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_SD2_CLK__USDHC2_CLK		0x400&gt;, /* SMARC P36 - SDIO_CK  */</div><div class='add'>+			   &lt;IMX95_PAD_SD2_CMD__USDHC2_CMD		0x400&gt;, /* SMARC P34 - SDIO_CMD */</div><div class='add'>+			   &lt;IMX95_PAD_SD2_DATA0__USDHC2_DATA0		0x400&gt;, /* SMARC P39 - SDIO_D0  */</div><div class='add'>+			   &lt;IMX95_PAD_SD2_DATA1__USDHC2_DATA1		0x400&gt;, /* SMARC P40 - SDIO_D1  */</div><div class='add'>+			   &lt;IMX95_PAD_SD2_DATA2__USDHC2_DATA2		0x400&gt;, /* SMARC P41 - SDIO_D2  */</div><div class='add'>+			   &lt;IMX95_PAD_SD2_DATA3__USDHC2_DATA3		0x400&gt;; /* SMARC P42 - SDIO_D3  */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC SDIO_CD# */</div><div class='add'>+	pinctrl_usdhc2_cd: usdhc2-cdgrp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0	0x1100&gt;; /* SMARC P35 - SDIO_CD# */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SMARC SDIO_PWR_EN */</div><div class='add'>+	pinctrl_usdhc2_pwr_en: usdhc2-pwrengrp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7	0x11e&gt;; /* SMARC P37 - SDIO_PWR_EN */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_vsel: usdhc2-vselgrp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_SD2_VSELECT__GPIO3_IO_BIT19	0x4&gt;; /* PMIC_SD2_VSEL */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* On-module Wi-Fi */</div><div class='add'>+	pinctrl_usdhc3: usdhc3grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_SD3_CLK__USDHC3_CLK	0x158e&gt;, /* SD3_CLK   */</div><div class='add'>+			   &lt;IMX95_PAD_SD3_CMD__USDHC3_CMD	0x138e&gt;, /* SD3_CMD   */</div><div class='add'>+			   &lt;IMX95_PAD_SD3_DATA0__USDHC3_DATA0	0x138e&gt;, /* SD3_DATA0 */</div><div class='add'>+			   &lt;IMX95_PAD_SD3_DATA1__USDHC3_DATA1	0x138e&gt;, /* SD3_DATA1 */</div><div class='add'>+			   &lt;IMX95_PAD_SD3_DATA2__USDHC3_DATA2	0x138e&gt;, /* SD3_DATA2 */</div><div class='add'>+			   &lt;IMX95_PAD_SD3_DATA3__USDHC3_DATA3	0x138e&gt;; /* SD3_DATA3 */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* On-module Wi-Fi */</div><div class='add'>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_SD3_CLK__USDHC3_CLK	0x15fe&gt;, /* SD3_CLK   */</div><div class='add'>+			   &lt;IMX95_PAD_SD3_CMD__USDHC3_CMD	0x13fe&gt;, /* SD3_CMD   */</div><div class='add'>+			   &lt;IMX95_PAD_SD3_DATA0__USDHC3_DATA0	0x13fe&gt;, /* SD3_DATA1 */</div><div class='add'>+			   &lt;IMX95_PAD_SD3_DATA1__USDHC3_DATA1	0x13fe&gt;, /* SD3_DATA2 */</div><div class='add'>+			   &lt;IMX95_PAD_SD3_DATA2__USDHC3_DATA2	0x13fe&gt;, /* SD3_DATA3 */</div><div class='add'>+			   &lt;IMX95_PAD_SD3_DATA3__USDHC3_DATA3	0x13fe&gt;; /* SD3_DATA4 */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx95-tqma9596sa-mb-smarc-2.dts b/arch/arm64/boot/dts/freescale/imx95-tqma9596sa-mb-smarc-2.dts<br/>new file mode 100644<br/>index 000000000000..97726eded0f8<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx95-tqma9596sa-mb-smarc-2.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx95-tqma9596sa-mb-smarc-2.dts</a></div><div class='hunk'>@@ -0,0 +1,269 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2024 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Alexander Stein</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/phy/phy-imx8-pcie.h&gt;</div><div class='add'>+#include "imx95-tqma9596sa.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "TQ-Systems i.MX95 TQMa95xxSA on MB-SMARC-2";</div><div class='add'>+	compatible = "tq,imx95-tqma9596sa-mb-smarc-2", "tq,imx95-tqma9596sa", "fsl,imx95";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		gpio0 = &amp;gpio1;</div><div class='add'>+		gpio1 = &amp;gpio2;</div><div class='add'>+		gpio2 = &amp;gpio3;</div><div class='add'>+		gpio3 = &amp;gpio4;</div><div class='add'>+		i2c0 = &amp;lpi2c1;</div><div class='add'>+		i2c1 = &amp;lpi2c2;</div><div class='add'>+		i2c2 = &amp;lpi2c3;</div><div class='add'>+		i2c3 = &amp;lpi2c4;</div><div class='add'>+		i2c4 = &amp;lpi2c5;</div><div class='add'>+		i2c5 = &amp;lpi2c6;</div><div class='add'>+		i2c6 = &amp;lpi2c7;</div><div class='add'>+		i2c7 = &amp;lpi2c8;</div><div class='add'>+		mmc0 = &amp;usdhc1;</div><div class='add'>+		mmc1 = &amp;usdhc2;</div><div class='add'>+		rtc0 = &amp;pcf85063;</div><div class='add'>+		rtc1 = &amp;scmi_bbm;</div><div class='add'>+		serial0 = &amp;lpuart1;</div><div class='add'>+		serial1 = &amp;lpuart2;</div><div class='add'>+		serial2 = &amp;lpuart3;</div><div class='add'>+		serial3 = &amp;lpuart4;</div><div class='add'>+		serial4 = &amp;lpuart5;</div><div class='add'>+		serial5 = &amp;lpuart6;</div><div class='add'>+		serial6 = &amp;lpuart7;</div><div class='add'>+		serial7 = &amp;lpuart8;</div><div class='add'>+		spi0 = &amp;flexspi1;</div><div class='add'>+		spi1 = &amp;lpspi3;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;lpuart7;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	backlight_lvds0: backlight-lvds0 {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		pwms = &lt;&amp;tpm3 0 100000 0&gt;;</div><div class='add'>+		brightness-levels = &lt;0 4 8 16 32 64 128 255&gt;;</div><div class='add'>+		default-brightness-level = &lt;7&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;expander2 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		power-supply = &lt;&amp;reg_12v0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	backlight_lvds1: backlight-lvds1 {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		pwms = &lt;&amp;tpm4 0 100000 0&gt;;</div><div class='add'>+		brightness-levels = &lt;0 4 8 16 32 64 128 255&gt;;</div><div class='add'>+		default-brightness-level = &lt;7&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;expander2 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		power-supply = &lt;&amp;reg_12v0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	panel_lvds0: panel-lvds0 {</div><div class='add'>+		/*</div><div class='add'>+		 * Display is not fixed, so compatible has to be added from</div><div class='add'>+		 * DT overlay</div><div class='add'>+		 */</div><div class='add'>+		backlight = &lt;&amp;backlight_lvds0&gt;;</div><div class='add'>+		power-supply = &lt;&amp;reg_lvds0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			panel_in_lvds0: endpoint {</div><div class='add'>+				/* TODO: LVDS0 out */</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	panel_lvds1: panel-lvds1 {</div><div class='add'>+		/*</div><div class='add'>+		 * Display is not fixed, so compatible has to be added from</div><div class='add'>+		 * DT overlay</div><div class='add'>+		 */</div><div class='add'>+		backlight = &lt;&amp;backlight_lvds1&gt;;</div><div class='add'>+		power-supply = &lt;&amp;reg_lvds1&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			panel_in_lvds1: endpoint {</div><div class='add'>+				/* TODO: LVDS1 out */</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_1v8: regulator-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3v3: regulator-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_12v0: regulator-12v0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "12V0";</div><div class='add'>+		regulator-min-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_lvds0: regulator-lvds0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "LCD0_VDD_EN";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;expander2 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_lvds1: regulator-lvds1 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "LCD1_VDD_EN";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;expander2 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "fsl,imx-audio-tlv320aic32x4";</div><div class='add'>+		model = "tqm-tlv320aic32";</div><div class='add'>+		audio-codec = &lt;&amp;tlv320aic3x04&gt;;</div><div class='add'>+		audio-cpu = &lt;&amp;sai3&gt;;</div><div class='add'>+		audio-routing =</div><div class='add'>+			"IN3_L", "Mic Jack",</div><div class='add'>+			"Mic Jack", "Mic Bias",</div><div class='add'>+			"IN1_L", "Line In Jack",</div><div class='add'>+			"IN1_R", "Line In Jack",</div><div class='add'>+			"Line Out Jack", "LOL",</div><div class='add'>+			"Line Out Jack", "LOR";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;enetc_port0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;enetc_port1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;expander2 {</div><div class='add'>+	pcie1-clk-en-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;14 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		output-high;</div><div class='add'>+		line-name = "PCIE1_CLK_EN";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie2-clk-en-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;15 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		output-high;</div><div class='add'>+		line-name = "PCIE2_CLK_EN";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	xceiver-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan3 {</div><div class='add'>+	xceiver-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c1 {</div><div class='add'>+	tlv320aic3x04: audio-codec@18 {</div><div class='add'>+		compatible = "ti,tlv320aic32x4";</div><div class='add'>+		reg = &lt;0x18&gt;;</div><div class='add'>+		clocks = &lt;&amp;scmi_clk IMX95_CLK_SAI3&gt;;</div><div class='add'>+		clock-names = "mclk";</div><div class='add'>+		iov-supply = &lt;&amp;reg_1v8&gt;;</div><div class='add'>+		ldoin-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom2: eeprom@57 {</div><div class='add'>+		compatible = "atmel,24c32";</div><div class='add'>+		reg = &lt;0x57&gt;;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpspi3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SER0 */</div><div class='add'>+&amp;lpuart1 {</div><div class='add'>+	status = "reserved";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SER3 */</div><div class='add'>+&amp;lpuart5 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SER1 */</div><div class='add'>+&amp;lpuart7 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SER2 */</div><div class='add'>+&amp;lpuart8 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* X44 mPCIe */</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* X22 PCIe x1 socket */</div><div class='add'>+&amp;pcie1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_sdvmmc {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* X4 */</div><div class='add'>+&amp;usb2 {</div><div class='add'>+	srp-disable;</div><div class='add'>+	hnp-disable;</div><div class='add'>+	adp-disable;</div><div class='add'>+	/* DR not yet supported */</div><div class='add'>+	dr_mode = "peripheral";</div><div class='add'>+	disable-over-current;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* X16 */</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	no-mmc;</div><div class='add'>+	no-sdio;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx95-tqma9596sa.dtsi b/arch/arm64/boot/dts/freescale/imx95-tqma9596sa.dtsi<br/>new file mode 100644<br/>index 000000000000..43418844701b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx95-tqma9596sa.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx95-tqma9596sa.dtsi</a></div><div class='hunk'>@@ -0,0 +1,803 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2024 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Alexander Stein</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/net/ti-dp83867.h&gt;</div><div class='add'>+#include &lt;dt-bindings/phy/phy-imx8-pcie.h&gt;</div><div class='add'>+#include &lt;dt-bindings/usb/pd.h&gt;</div><div class='add'>+#include "imx95.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;enetc_port0;</div><div class='add'>+		ethernet1 = &amp;enetc_port1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@80000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		/*</div><div class='add'>+		 * DRAM base addr, size : 2048 MiB DRAM</div><div class='add'>+		 * should be corrected by bootloader</div><div class='add'>+		 */</div><div class='add'>+		reg = &lt;0 0x80000000 0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		linux_cma: linux,cma {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reusable;</div><div class='add'>+			size = &lt;0 0x28000000&gt;;</div><div class='add'>+			alloc-ranges = &lt;0 0x80000000 0 0x80000000&gt;;</div><div class='add'>+			linux,cma-default;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vpu_boot: vpu_boot@a0000000 {</div><div class='add'>+			reg = &lt;0 0xa0000000 0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_dp: clk-dp {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;26000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_xtal25: clk-xtal25 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;25000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_1v8: regulator-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "V_1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3v3: regulator-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "V_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Controlled by system manager */</div><div class='add'>+	reg_sdvmmc: regulator-sdvmmc {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_sdvmmc&gt;;</div><div class='add'>+		regulator-name = "SDIO_PWR_EN";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio3 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;enetc_port0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_enetc0&gt;;</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;enetc_port1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_enetc1&gt;;</div><div class='add'>+	phy-handle = &lt;&amp;ethphy3&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;netc_timer {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexcan3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexspi1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexspi1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash0: flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;66000000&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;4&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_1v8&gt;;</div><div class='add'>+</div><div class='add'>+		partitions {</div><div class='add'>+			compatible = "fixed-partitions";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio1&gt;;</div><div class='add'>+	gpio-line-names = "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "GPIO7", "GPIO8",</div><div class='add'>+			  "", "GPIO9", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_gpio2&gt;;</div><div class='add'>+	gpio-line-names = "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "SLEEP", "GPIO5",</div><div class='add'>+			  "", "", "GPIO6", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpi2c1 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	tmp1075: temperature-sensor@4a {</div><div class='add'>+		compatible = "ti,tmp1075";</div><div class='add'>+		reg = &lt;0x4a&gt;;</div><div class='add'>+		vs-supply = &lt;&amp;reg_1v8&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom_smarc: eeprom@50 {</div><div class='add'>+		compatible = "atmel,24c64";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_1v8&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcf85063: rtc@51 {</div><div class='add'>+		compatible = "nxp,pcf85063a";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		quartz-load-femtofarads = &lt;7000&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pcf85063&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio2&gt;;</div><div class='add'>+		interrupts = &lt;27 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	m24c64: eeprom@54 {</div><div class='add'>+		compatible = "atmel,24c64";</div><div class='add'>+		reg = &lt;0x54&gt;;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_1v8&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* protectable identification memory (part of M24C64-D @50) */</div><div class='add'>+	eeprom@58 {</div><div class='add'>+		compatible = "atmel,24c64d-wl";</div><div class='add'>+		reg = &lt;0x58&gt;;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_1v8&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* protectable identification memory (part of M24C64-D @54) */</div><div class='add'>+	eeprom@5c {</div><div class='add'>+		compatible = "atmel,24c64d-wl";</div><div class='add'>+		reg = &lt;0x5c&gt;;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_1v8&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcieclk: clock-generator@6a {</div><div class='add'>+		compatible = "renesas,9fgv0441";</div><div class='add'>+		reg = &lt;0x6a&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk_xtal25&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	imu@6b {</div><div class='add'>+		compatible = "st,ism330dhcx";</div><div class='add'>+		reg = &lt;0x6b&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+		vddio-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* D23 */</div><div class='add'>+	expander2: gpio@74 {</div><div class='add'>+		compatible = "ti,tca9539";</div><div class='add'>+		reg = &lt;0x74&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_1v8&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-line-names = "GPIO4", "LCD0_BLKT_EN", "LCD0_VDD_EN", "LCD1_BLKT_EN",</div><div class='add'>+				  "LCD1_VDD_EN", "ENET1_RESET#", "ENET2_RESET#", "GBE0_SDP_DIR",</div><div class='add'>+				  "GBE1_SDP_DIR", "PCIE1_RST#", "PCIE2_RST#", "DP_BRIDGE_EN",</div><div class='add'>+				  "HUB_RST#", "QSPI_RESET#", "PCIE1_CLK_EN", "PCIE2_CLK_EN";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* D21 */</div><div class='add'>+	expander1: gpio@75 {</div><div class='add'>+		compatible = "ti,tca9539";</div><div class='add'>+		reg = &lt;0x75&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_1v8&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_expander1&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio3&gt;;</div><div class='add'>+		interrupts = &lt;27 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		gpio-line-names = "GPIO10", "GPIO11", "GPIO12", "GPIO13",</div><div class='add'>+				  "CHG_PRSNT#", "CHARGING", "LID", "BATLOW#",</div><div class='add'>+				  "TEMP_EVENT#", "PGOOD_ARM", "PGOOD_SOC", "PCIE_WAKE#_1V8",</div><div class='add'>+				  "GPIO0", "GPIO1", "GPIO2", "GPIO3";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* I2C_CAM0 */</div><div class='add'>+&amp;lpi2c3 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_lpi2c3_gpio&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	dp_bridge: dp-bridge@f {</div><div class='add'>+		compatible = "toshiba,tc9595", "toshiba,tc358767";</div><div class='add'>+		reg = &lt;0x0f&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_tc9595&gt;;</div><div class='add'>+		clock-names = "ref";</div><div class='add'>+		clocks = &lt;&amp;clk_dp&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;expander2 11 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio2&gt;;</div><div class='add'>+		interrupts = &lt;25 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+		toshiba,hpd-pin = &lt;0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				dp_dsi_in: endpoint {</div><div class='add'>+					/* TODO: DSI out */</div><div class='add'>+					data-lanes = &lt;1 2 3 4&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* I2C_CAM1 */</div><div class='add'>+&amp;lpi2c4 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c4&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_lpi2c4_gpio&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio2 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* I2C_LCD */</div><div class='add'>+&amp;lpi2c6 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c6&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_lpi2c6_gpio&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio2 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio2 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpspi3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpspi3&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio2 8 GPIO_ACTIVE_LOW&gt;, &lt;&amp;gpio2 7 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SER0 */</div><div class='add'>+&amp;lpuart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpuart1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SER3 */</div><div class='add'>+&amp;lpuart5 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpuart5&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SER1 */</div><div class='add'>+&amp;lpuart7 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpuart7&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SER2 */</div><div class='add'>+&amp;lpuart8 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpuart8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;netc_blk_ctrl {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;netc_emdio {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_mdio&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ethphy0: ethernet-phy@0 {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_ethphy0&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;expander2 5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		reset-assert-us = &lt;500000&gt;;</div><div class='add'>+		reset-deassert-us = &lt;50000&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio5&gt;;</div><div class='add'>+		interrupts = &lt;13 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_2_50_NS&gt;;</div><div class='add'>+		ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_2_50_NS&gt;;</div><div class='add'>+		ti,fifo-depth = &lt;DP83867_PHYCR_FIFO_DEPTH_4_B_NIB&gt;;</div><div class='add'>+		ti,dp83867-rxctrl-strap-quirk;</div><div class='add'>+		ti,clk-output-sel = &lt;DP83867_CLK_O_SEL_OFF&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ethphy3: ethernet-phy@3 {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+		reg = &lt;3&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_ethphy3&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;expander2 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		reset-assert-us = &lt;500000&gt;;</div><div class='add'>+		reset-deassert-us = &lt;50000&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio5&gt;;</div><div class='add'>+		interrupts = &lt;14 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_2_50_NS&gt;;</div><div class='add'>+		ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_2_50_NS&gt;;</div><div class='add'>+		ti,fifo-depth = &lt;DP83867_PHYCR_FIFO_DEPTH_4_B_NIB&gt;;</div><div class='add'>+		ti,dp83867-rxctrl-strap-quirk;</div><div class='add'>+		ti,clk-output-sel = &lt;DP83867_CLK_O_SEL_OFF&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	clocks = &lt;&amp;scmi_clk IMX95_CLK_HSIO&gt;,</div><div class='add'>+		 &lt;&amp;scmi_clk IMX95_CLK_HSIOPLL&gt;,</div><div class='add'>+		 &lt;&amp;scmi_clk IMX95_CLK_HSIOPLL_VCO&gt;,</div><div class='add'>+		 &lt;&amp;scmi_clk IMX95_CLK_HSIOPCIEAUX&gt;,</div><div class='add'>+		 &lt;&amp;pcieclk 1&gt;;</div><div class='add'>+	clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref";</div><div class='add'>+	reset-gpios = &lt;&amp;expander2 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcie1&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	clocks = &lt;&amp;scmi_clk IMX95_CLK_HSIO&gt;,</div><div class='add'>+		 &lt;&amp;scmi_clk IMX95_CLK_HSIOPLL&gt;,</div><div class='add'>+		 &lt;&amp;scmi_clk IMX95_CLK_HSIOPLL_VCO&gt;,</div><div class='add'>+		 &lt;&amp;scmi_clk IMX95_CLK_HSIOPCIEAUX&gt;,</div><div class='add'>+		 &lt;&amp;pcieclk 0&gt;;</div><div class='add'>+	clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref";</div><div class='add'>+	reset-gpios = &lt;&amp;expander2 10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai3 {</div><div class='add'>+	#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai3&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL1_VCO&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL2_VCO&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL1&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL2&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_SAI3&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;, &lt;0&gt;,</div><div class='add'>+				 &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL1&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;3932160000&gt;,</div><div class='add'>+			       &lt;3612672000&gt;, &lt;393216000&gt;,</div><div class='add'>+			       &lt;361267200&gt;, &lt;12288000&gt;;</div><div class='add'>+	fsl,sai-mclk-direction-output;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai5 {</div><div class='add'>+	#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai5&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL1_VCO&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL2_VCO&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL1&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL2&gt;,</div><div class='add'>+			  &lt;&amp;scmi_clk IMX95_CLK_SAI5&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;0&gt;, &lt;0&gt;,</div><div class='add'>+				 &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL1&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;3932160000&gt;,</div><div class='add'>+			       &lt;3612672000&gt;, &lt;393216000&gt;,</div><div class='add'>+			       &lt;361267200&gt;, &lt;12288000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;scmi_bbm {</div><div class='add'>+	linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tpm3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_tpm3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tpm4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_tpm4&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tpm5 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_tpm5&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_dwc3 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	hub_2_0: hub@1 {</div><div class='add'>+		compatible = "usb451,8142";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		peer-hub = &lt;&amp;hub_3_0&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;expander2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hub_3_0: hub@2 {</div><div class='add'>+		compatible = "usb451,8140";</div><div class='add'>+		reg = &lt;2&gt;;</div><div class='add'>+		peer-hub = &lt;&amp;hub_2_0&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;expander2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1_200mhz&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	no-sdio;</div><div class='add'>+	no-sd;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_sdvmmc&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio3 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	no-1-8-v;</div><div class='add'>+	disable-wp;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wdog3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;scmi_iomuxc {</div><div class='add'>+	pinctrl_ethphy0: ethphy0grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13				0x1100&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ethphy3: ethphy3grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14				0x1100&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_enetc0: enetc0grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0		0x1100&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1		0x1100&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2		0x1100&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3		0x1100&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK		0x1100&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL	0x1100&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0		0x11e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1		0x11e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2		0x11e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3		0x11e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK		0x11e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL	0x11e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_GPIO_IO23__GPIO2_IO_BIT23				0x51e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_enetc1: enetc1grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0		0x1100&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1		0x1100&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2		0x1100&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3		0x1100&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK		0x1100&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL	0x1100&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0		0x11e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1		0x11e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2		0x11e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3		0x11e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK		0x11e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL	0x11e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_GPIO_IO24__GPIO2_IO_BIT24				0x51e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_expander1: expander1grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_CCM_CLKO2__GPIO3_IO_BIT27				0x1100&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan1: flexcan1grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX	0x1300&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX		0x31e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexcan3: flexcan3grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_CCM_CLKO3__CAN3_TX		0x31e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_CCM_CLKO4__CAN3_RX		0x1300&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexspi1: flexspi1grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_SD3_CLK__FLEXSPI1_A_SCLK		0x19e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD3_CMD__FLEXSPI1_A_SS0_B		0x19e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD3_DATA0__FLEXSPI1_A_DATA_BIT0	0x19e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD3_DATA1__FLEXSPI1_A_DATA_BIT1	0x19e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD3_DATA2__FLEXSPI1_A_DATA_BIT2	0x19e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD3_DATA3__FLEXSPI1_A_DATA_BIT3	0x19e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio1: gpio1grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_GPIO1_IO_BIT10	0x111e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SAI1_TXD0__AONMIX_TOP_GPIO1_IO_BIT13		0x111e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SAI1_TXFS__AONMIX_TOP_GPIO1_IO_BIT11		0x111e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpio2: gpio2grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_GPIO_IO18__GPIO2_IO_BIT18		0x1100&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_GPIO_IO19__GPIO2_IO_BIT19		0x111e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_GPIO_IO22__GPIO2_IO_BIT22		0x111e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c1: lpi2c1grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_I2C1_SCL__AONMIX_TOP_LPI2C1_SCL		0x4000191e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_I2C1_SDA__AONMIX_TOP_LPI2C1_SDA		0x4000191e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c3: lpi2c3grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_GPIO_IO28__LPI2C3_SDA			0x4000191e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_GPIO_IO29__LPI2C3_SCL			0x4000191e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c3_gpio: lpi2c3-gpiogrp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_GPIO_IO28__GPIO2_IO_BIT28		0x4000191e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_GPIO_IO29__GPIO2_IO_BIT29		0x4000191e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c4: lpi2c4grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_GPIO_IO30__LPI2C4_SDA		0x4000191e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_GPIO_IO31__LPI2C4_SCL		0x4000191e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c4_gpio: lpi2c4-gpiogrp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_GPIO_IO30__GPIO2_IO_BIT30		0x4000191e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_GPIO_IO31__GPIO2_IO_BIT31		0x4000191e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c6: lpi2c6grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_GPIO_IO02__LPI2C6_SDA		0x4000191e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_GPIO_IO03__LPI2C6_SCL		0x4000191e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c6_gpio: lpi2c6-gpiogrp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_GPIO_IO02__GPIO2_IO_BIT2		0x4000191e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_GPIO_IO03__GPIO2_IO_BIT3		0x4000191e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpspi3: lpspi3grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_GPIO_IO07__GPIO2_IO_BIT7		0x51e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_GPIO_IO08__GPIO2_IO_BIT8		0x51e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_GPIO_IO09__LPSPI3_SIN		0x51e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_GPIO_IO10__LPSPI3_SOUT		0x51e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_GPIO_IO11__LPSPI3_SCK		0x51e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpuart1: lpuart1grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX		0x1300&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX		0x31e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART1_RTS_B	0x1300&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART1_CTS_B	0x31e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpuart5: lpuart5grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_GPIO_IO00__LPUART5_TX			0x31e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_GPIO_IO01__LPUART5_RX			0x1300&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpuart7: lpuart7grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_GPIO_IO36__LPUART7_TX			0x31e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_GPIO_IO37__LPUART7_RX			0x1300&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpuart8: lpuart8grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_GPIO_IO12__LPUART8_TX			0x31e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_GPIO_IO13__LPUART8_RX			0x1300&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_GPIO_IO14__LPUART8_CTS_B			0x31e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_GPIO_IO15__LPUART8_RTS_B			0x1300&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_mdio: mdiogrp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC		0x51e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO		0x51e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcf85063: pcf85063grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_GPIO_IO27__GPIO2_IO_BIT27			0x1100&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie0: pcie0grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B	0x111e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcie1: pcie1grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B	0x111e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai3: sai3grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK			0x51e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_GPIO_IO17__SAI3_MCLK			0x51e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0		0x1300&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0		0x51e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC			0x51e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai5: sai5grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_XSPI1_DATA4__SAI5_TX_DATA_BIT0		0x51e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_XSPI1_DATA5__SAI5_TX_SYNC			0x51e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_XSPI1_DATA6__SAI5_TX_BCLK			0x51e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_XSPI1_DATA7__SAI5_RX_DATA_BIT0		0x1300&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sdvmmc: sdvmmcgrp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7		0x11e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_tc9595: tc9595grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_GPIO_IO25__GPIO2_IO_BIT25			0x1500&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_tpm3: tpm3grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_GPIO_IO04__TPM3_CH0			0x51e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_tpm4: tpm4grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_GPIO_IO05__TPM4_CH0			0x51e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_tpm5: tpm5grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_GPIO_IO06__TPM5_CH0			0x51e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_SD1_CLK__USDHC1_CLK	0x158e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD1_CMD__USDHC1_CMD	0x138e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD1_DATA0__USDHC1_DATA0	0x138e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD1_DATA1__USDHC1_DATA1	0x138e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD1_DATA2__USDHC1_DATA2	0x138e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD1_DATA3__USDHC1_DATA3	0x138e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD1_DATA4__USDHC1_DATA4	0x138e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD1_DATA5__USDHC1_DATA5	0x138e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD1_DATA6__USDHC1_DATA6	0x138e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD1_DATA7__USDHC1_DATA7	0x138e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD1_STROBE__USDHC1_STROBE	0x158e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_SD1_CLK__USDHC1_CLK	0x158e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD1_CMD__USDHC1_CMD	0x138e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD1_DATA0__USDHC1_DATA0	0x138e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD1_DATA1__USDHC1_DATA1	0x138e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD1_DATA2__USDHC1_DATA2	0x138e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD1_DATA3__USDHC1_DATA3	0x138e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD1_DATA4__USDHC1_DATA4	0x138e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD1_DATA5__USDHC1_DATA5	0x138e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD1_DATA6__USDHC1_DATA6	0x138e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD1_DATA7__USDHC1_DATA7	0x138e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD1_STROBE__USDHC1_STROBE	0x158e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_SD1_CLK__USDHC1_CLK	0x15fe&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD1_CMD__USDHC1_CMD	0x13fe&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD1_DATA0__USDHC1_DATA0	0x13fe&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD1_DATA1__USDHC1_DATA1	0x13fe&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD1_DATA2__USDHC1_DATA2	0x13fe&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD1_DATA3__USDHC1_DATA3	0x13fe&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD1_DATA4__USDHC1_DATA4	0x13fe&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD1_DATA5__USDHC1_DATA5	0x13fe&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD1_DATA6__USDHC1_DATA6	0x13fe&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD1_DATA7__USDHC1_DATA7	0x13fe&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD1_STROBE__USDHC1_STROBE	0x15fe&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0			0x1100&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD2_CLK__USDHC2_CLK			0x51e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD2_CMD__USDHC2_CMD			0x31e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD2_DATA0__USDHC2_DATA0			0x131e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD2_DATA1__USDHC2_DATA1			0x131e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD2_DATA2__USDHC2_DATA2			0x131e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD2_DATA3__USDHC2_DATA3			0x131e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT		0x51e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0			0x1100&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD2_CLK__USDHC2_CLK			0x158e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD2_CMD__USDHC2_CMD			0x138e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD2_DATA0__USDHC2_DATA0			0x138e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD2_DATA1__USDHC2_DATA1			0x138e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD2_DATA2__USDHC2_DATA2			0x138e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD2_DATA3__USDHC2_DATA3			0x138e&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT		0x51e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0			0x1100&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD2_CLK__USDHC2_CLK			0x15fe&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD2_CMD__USDHC2_CMD			0x13fe&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD2_DATA0__USDHC2_DATA0			0x13fe&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD2_DATA1__USDHC2_DATA1			0x13fe&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD2_DATA2__USDHC2_DATA2			0x13fe&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD2_DATA3__USDHC2_DATA3			0x13fe&gt;,</div><div class='add'>+			   &lt;IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT		0x51e&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi<br/>new file mode 100644<br/>index 000000000000..e45014d50abe<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/imx95.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/imx95.dtsi</a></div><div class='hunk'>@@ -0,0 +1,2185 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-only OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/nxp,imx95-clock.h&gt;</div><div class='add'>+#include &lt;dt-bindings/dma/fsl-edma.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/thermal/thermal.h&gt;</div><div class='add'>+</div><div class='add'>+#include "imx95-clock.h"</div><div class='add'>+#include "imx95-pinfunc.h"</div><div class='add'>+#include "imx95-power.h"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		idle-states {</div><div class='add'>+			entry-method = "psci";</div><div class='add'>+</div><div class='add'>+			cpu_pd_wait: cpu-pd-wait {</div><div class='add'>+				compatible = "arm,idle-state";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x0010033&gt;;</div><div class='add'>+				local-timer-stop;</div><div class='add'>+				entry-latency-us = &lt;10000&gt;;</div><div class='add'>+				exit-latency-us = &lt;7000&gt;;</div><div class='add'>+				min-residency-us = &lt;27000&gt;;</div><div class='add'>+				wakeup-latency-us = &lt;15000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		A55_0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_pd_wait&gt;;</div><div class='add'>+			power-domains = &lt;&amp;scmi_perf IMX95_PERF_A55&gt;;</div><div class='add'>+			power-domain-names = "perf";</div><div class='add'>+			i-cache-size = &lt;32768&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;128&gt;;</div><div class='add'>+			d-cache-size = &lt;32768&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_l0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		A55_1: cpu@100 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x100&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_pd_wait&gt;;</div><div class='add'>+			power-domains = &lt;&amp;scmi_perf IMX95_PERF_A55&gt;;</div><div class='add'>+			power-domain-names = "perf";</div><div class='add'>+			i-cache-size = &lt;32768&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;128&gt;;</div><div class='add'>+			d-cache-size = &lt;32768&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_l1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		A55_2: cpu@200 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x200&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_pd_wait&gt;;</div><div class='add'>+			power-domains = &lt;&amp;scmi_perf IMX95_PERF_A55&gt;;</div><div class='add'>+			power-domain-names = "perf";</div><div class='add'>+			i-cache-size = &lt;32768&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;128&gt;;</div><div class='add'>+			d-cache-size = &lt;32768&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		A55_3: cpu@300 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x300&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_pd_wait&gt;;</div><div class='add'>+			power-domains = &lt;&amp;scmi_perf IMX95_PERF_A55&gt;;</div><div class='add'>+			power-domain-names = "perf";</div><div class='add'>+			i-cache-size = &lt;32768&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;128&gt;;</div><div class='add'>+			d-cache-size = &lt;32768&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_l3&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		A55_4: cpu@400 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x400&gt;;</div><div class='add'>+			power-domains = &lt;&amp;scmi_perf IMX95_PERF_A55&gt;;</div><div class='add'>+			power-domain-names = "perf";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_pd_wait&gt;;</div><div class='add'>+			i-cache-size = &lt;32768&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;128&gt;;</div><div class='add'>+			d-cache-size = &lt;32768&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_l4&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		A55_5: cpu@500 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x500&gt;;</div><div class='add'>+			power-domains = &lt;&amp;scmi_perf IMX95_PERF_A55&gt;;</div><div class='add'>+			power-domain-names = "perf";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_pd_wait&gt;;</div><div class='add'>+			i-cache-size = &lt;32768&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;128&gt;;</div><div class='add'>+			d-cache-size = &lt;32768&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_cache_l5&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_cache_l0: l2-cache-l0 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-size = &lt;65536&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;256&gt;;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			next-level-cache = &lt;&amp;l3_cache&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_cache_l1: l2-cache-l1 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-size = &lt;65536&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;256&gt;;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			next-level-cache = &lt;&amp;l3_cache&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_cache_l2: l2-cache-l2 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-size = &lt;65536&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;256&gt;;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			next-level-cache = &lt;&amp;l3_cache&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_cache_l3: l2-cache-l3 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-size = &lt;65536&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;256&gt;;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			next-level-cache = &lt;&amp;l3_cache&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_cache_l4: l2-cache-l4 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-size = &lt;65536&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;256&gt;;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			next-level-cache = &lt;&amp;l3_cache&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_cache_l5: l2-cache-l5 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-size = &lt;65536&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;256&gt;;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			next-level-cache = &lt;&amp;l3_cache&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l3_cache: l3-cache {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-size = &lt;524288&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;512&gt;;</div><div class='add'>+			cache-level = &lt;3&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu-map {</div><div class='add'>+			cluster0 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;A55_0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;A55_1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;A55_2&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;A55_3&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core4 {</div><div class='add'>+					cpu = &lt;&amp;A55_4&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core5 {</div><div class='add'>+					cpu = &lt;&amp;A55_5&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dummy: clock-dummy {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;0&gt;;</div><div class='add'>+		clock-output-names = "dummy";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpu_opp_table: opp-table {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		opp-500000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;500000000&gt;;</div><div class='add'>+			opp-hz-real = /bits/ 64 &lt;500000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;920000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-800000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;800000000&gt;;</div><div class='add'>+			opp-hz-real = /bits/ 64 &lt;800000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;920000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1000000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1000000000&gt;;</div><div class='add'>+			opp-hz-real = /bits/ 64 &lt;1000000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;920000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_ext1: clock-ext1 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;133000000&gt;;</div><div class='add'>+		clock-output-names = "clk_ext1";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sai1_mclk: clock-sai-mclk1 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;0&gt;;</div><div class='add'>+		clock-output-names = "sai1_mclk";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sai2_mclk: clock-sai-mclk2 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;0&gt;;</div><div class='add'>+		clock-output-names = "sai2_mclk";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sai3_mclk: clock-sai-mclk3 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;0&gt;;</div><div class='add'>+		clock-output-names = "sai3_mclk";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sai4_mclk: clock-sai-mclk4 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;0&gt;;</div><div class='add'>+		clock-output-names = "sai4_mclk";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sai5_mclk: clock-sai-mclk5 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;0&gt;;</div><div class='add'>+		clock-output-names = "sai5_mclk";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_sys100m: clock-sys100m {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;100000000&gt;;</div><div class='add'>+		clock-output-names = "clk_sys100m";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	osc_24m: clock-24m {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+		clock-output-names = "osc_24m";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sram1: sram@204c0000 {</div><div class='add'>+		compatible = "mmio-sram";</div><div class='add'>+		reg = &lt;0x0 0x204c0000 0x0 0x18000&gt;;</div><div class='add'>+		ranges = &lt;0x0 0x0 0x204c0000 0x18000&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	firmware {</div><div class='add'>+		scmi {</div><div class='add'>+			compatible = "arm,scmi";</div><div class='add'>+			mboxes = &lt;&amp;mu2 5 0&gt;, &lt;&amp;mu2 3 0&gt;, &lt;&amp;mu2 3 1&gt;, &lt;&amp;mu2 5 1&gt;;</div><div class='add'>+			shmem = &lt;&amp;scmi_buf0&gt;, &lt;&amp;scmi_buf1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			arm,max-rx-timeout-ms = &lt;5000&gt;;</div><div class='add'>+</div><div class='add'>+			scmi_devpd: protocol@11 {</div><div class='add'>+				reg = &lt;0x11&gt;;</div><div class='add'>+				#power-domain-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			scmi_sys_power: protocol@12 {</div><div class='add'>+				reg = &lt;0x12&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			scmi_perf: protocol@13 {</div><div class='add'>+				reg = &lt;0x13&gt;;</div><div class='add'>+				#power-domain-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			scmi_clk: protocol@14 {</div><div class='add'>+				reg = &lt;0x14&gt;;</div><div class='add'>+				#clock-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			scmi_sensor: protocol@15 {</div><div class='add'>+				reg = &lt;0x15&gt;;</div><div class='add'>+				#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			scmi_iomuxc: protocol@19 {</div><div class='add'>+				reg = &lt;0x19&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			scmi_lmm: protocol@80 {</div><div class='add'>+				reg = &lt;0x80&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			scmi_bbm: protocol@81 {</div><div class='add'>+				reg = &lt;0x81&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			scmi_cpu: protocol@82 {</div><div class='add'>+				reg = &lt;0x82&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			scmi_misc: protocol@84 {</div><div class='add'>+				reg = &lt;0x84&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu {</div><div class='add'>+		compatible = "arm,cortex-a55-pmu";</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	thermal_zones: thermal-zones {</div><div class='add'>+		a55-thermal {</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			polling-delay = &lt;2000&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;scmi_sensor 1&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu_alert0: trip0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_crit0: trip1 {</div><div class='add'>+					temperature = &lt;125000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu_alert0&gt;;</div><div class='add'>+					cooling-device =</div><div class='add'>+						&lt;&amp;A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+						&lt;&amp;A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+						&lt;&amp;A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+						&lt;&amp;A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+						&lt;&amp;A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+						&lt;&amp;A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ana-thermal {</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			polling-delay = &lt;2000&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;scmi_sensor 0&gt;;</div><div class='add'>+			trips {</div><div class='add'>+				ana_alert: trip0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				ana_crit0: trip1 {</div><div class='add'>+					temperature = &lt;125000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;ana_alert&gt;;</div><div class='add'>+					cooling-device =</div><div class='add'>+						&lt;&amp;A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+						&lt;&amp;A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+						&lt;&amp;A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+						&lt;&amp;A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+						&lt;&amp;A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+						&lt;&amp;A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-1.0";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+		arm,no-tick-in-suspend;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gic: interrupt-controller@48000000 {</div><div class='add'>+		compatible = "arm,gic-v3";</div><div class='add'>+		reg = &lt;0 0x48000000 0 0x10000&gt;,</div><div class='add'>+		      &lt;0 0x48060000 0 0xc0000&gt;;</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		#interrupt-cells = &lt;3&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		dma-noncoherent;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		its: msi-controller@48040000 {</div><div class='add'>+			compatible = "arm,gic-v3-its";</div><div class='add'>+			reg = &lt;0 0x48040000 0 0x20000&gt;;</div><div class='add'>+			msi-controller;</div><div class='add'>+			#msi-cells = &lt;1&gt;;</div><div class='add'>+			dma-noncoherent;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usbphynop: usbphynop {</div><div class='add'>+		compatible = "usb-nop-xceiv";</div><div class='add'>+		clocks = &lt;&amp;scmi_clk IMX95_CLK_HSIO&gt;;</div><div class='add'>+		clock-names = "main_clk";</div><div class='add'>+		#phy-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		etm0: etm@40840000 {</div><div class='add'>+			compatible = "arm,coresight-etm4x", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x40840000 0x0 0x10000&gt;;</div><div class='add'>+			arm,primecell-periphid = &lt;0xbb95d&gt;;</div><div class='add'>+			cpu = &lt;&amp;A55_0&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_clk IMX95_CLK_A55PERIPH&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					etm0_out_port: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ca_funnel_in_port0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		funnel0: funnel {</div><div class='add'>+			/*</div><div class='add'>+			 * non-configurable funnel don't show up on the AMBA</div><div class='add'>+			 * bus.  As such no need to add "arm,primecell".</div><div class='add'>+			 */</div><div class='add'>+			compatible = "arm,coresight-static-funnel";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				port {</div><div class='add'>+					ca_funnel_in_port0: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;etm0_out_port&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					ca_funnel_out_port0: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;hugo_funnel_in_port0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		funnel1: funnel-sys {</div><div class='add'>+			compatible = "arm,coresight-static-funnel";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				port {</div><div class='add'>+					hugo_funnel_in_port0: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ca_funnel_out_port0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					hugo_funnel_out_port0: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;etf_in_port&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		etf: etf@41030000 {</div><div class='add'>+			compatible = "arm,coresight-tmc", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x41030000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_clk IMX95_CLK_A55PERIPH&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				port {</div><div class='add'>+					etf_in_port: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;hugo_funnel_out_port0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					etf_out_port: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;etr_in_port&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		etr: etr@41040000 {</div><div class='add'>+			compatible = "arm,coresight-tmc", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x41040000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_clk IMX95_CLK_A55PERIPH&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				port {</div><div class='add'>+					etr_in_port: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;etf_out_port&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aips2: bus@42000000 {</div><div class='add'>+			compatible = "fsl,aips-bus", "simple-bus";</div><div class='add'>+			reg = &lt;0x0 0x42000000 0x0 0x800000&gt;;</div><div class='add'>+			ranges = &lt;0x42000000 0x0 0x42000000 0x8000000&gt;,</div><div class='add'>+				 &lt;0x28000000 0x0 0x28000000 0x10000000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			edma2: dma-controller@42000000 {</div><div class='add'>+				compatible = "fsl,imx95-edma5";</div><div class='add'>+				reg = &lt;0x42000000 0x210000&gt;;</div><div class='add'>+				#dma-cells = &lt;3&gt;;</div><div class='add'>+				dma-channels = &lt;64&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_BUSWAKEUP&gt;;</div><div class='add'>+				clock-names = "dma";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			edma3: dma-controller@42210000 {</div><div class='add'>+				compatible = "fsl,imx95-edma5";</div><div class='add'>+				reg = &lt;0x42210000 0x210000&gt;;</div><div class='add'>+				#dma-cells = &lt;3&gt;;</div><div class='add'>+				dma-channels = &lt;64&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_BUSWAKEUP&gt;;</div><div class='add'>+				clock-names = "dma";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mu7: mailbox@42430000 {</div><div class='add'>+				compatible = "fsl,imx95-mu";</div><div class='add'>+				reg = &lt;0x42430000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_BUSWAKEUP&gt;;</div><div class='add'>+				#mbox-cells = &lt;2&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			wdog3: watchdog@42490000 {</div><div class='add'>+				compatible = "fsl,imx93-wdt";</div><div class='add'>+				reg = &lt;0x42490000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_BUSWAKEUP&gt;;</div><div class='add'>+				timeout-sec = &lt;40&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tpm3: pwm@424e0000 {</div><div class='add'>+				compatible = "fsl,imx7ulp-pwm";</div><div class='add'>+				reg = &lt;0x424e0000 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_BUSWAKEUP&gt;;</div><div class='add'>+				#pwm-cells = &lt;3&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tpm4: pwm@424f0000 {</div><div class='add'>+				compatible = "fsl,imx7ulp-pwm";</div><div class='add'>+				reg = &lt;0x424f0000 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_TPM4&gt;;</div><div class='add'>+				#pwm-cells = &lt;3&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tpm5: pwm@42500000 {</div><div class='add'>+				compatible = "fsl,imx7ulp-pwm";</div><div class='add'>+				reg = &lt;0x42500000 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_TPM5&gt;;</div><div class='add'>+				#pwm-cells = &lt;3&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tpm6: pwm@42510000 {</div><div class='add'>+				compatible = "fsl,imx7ulp-pwm";</div><div class='add'>+				reg = &lt;0x42510000 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_TPM6&gt;;</div><div class='add'>+				#pwm-cells = &lt;3&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i3c2: i3c@42520000 {</div><div class='add'>+				compatible = "nxp,imx95-i3c", "silvaco,i3c-master-v1";</div><div class='add'>+				reg = &lt;0x42520000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;3&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_BUSAON&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX95_CLK_I3C2SLOW&gt;;</div><div class='add'>+				clock-names = "pclk", "fast_clk";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpi2c3: i2c@42530000 {</div><div class='add'>+				compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+				reg = &lt;0x42530000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_LPI2C3&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX95_CLK_BUSWAKEUP&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				dmas = &lt;&amp;edma2 8 0 0&gt;, &lt;&amp;edma2 9 0 FSL_EDMA_RX&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpi2c4: i2c@42540000 {</div><div class='add'>+				compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+				reg = &lt;0x42540000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_LPI2C4&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX95_CLK_BUSWAKEUP&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				dmas = &lt;&amp;edma2 10 0 0&gt;, &lt;&amp;edma2 11 0 FSL_EDMA_RX&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpspi3: spi@42550000 {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";</div><div class='add'>+				reg = &lt;0x42550000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_LPSPI3&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX95_CLK_BUSWAKEUP&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma2 12 0 0&gt;, &lt;&amp;edma2 13 0 FSL_EDMA_RX&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpspi4: spi@42560000 {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";</div><div class='add'>+				reg = &lt;0x42560000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_LPSPI4&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX95_CLK_BUSWAKEUP&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma2 14 0 0&gt;, &lt;&amp;edma2 15 0 FSL_EDMA_RX&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpuart3: serial@42570000 {</div><div class='add'>+				compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",</div><div class='add'>+					     "fsl,imx7ulp-lpuart";</div><div class='add'>+				reg = &lt;0x42570000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_LPUART3&gt;;</div><div class='add'>+				clock-names = "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma2 18 0 FSL_EDMA_RX&gt;, &lt;&amp;edma2 17 0 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpuart4: serial@42580000 {</div><div class='add'>+				compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",</div><div class='add'>+					     "fsl,imx7ulp-lpuart";</div><div class='add'>+				reg = &lt;0x42580000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_LPUART4&gt;;</div><div class='add'>+				clock-names = "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma2 20 0 FSL_EDMA_RX&gt;, &lt;&amp;edma2 19 0 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpuart5: serial@42590000 {</div><div class='add'>+				compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",</div><div class='add'>+					     "fsl,imx7ulp-lpuart";</div><div class='add'>+				reg = &lt;0x42590000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_LPUART5&gt;;</div><div class='add'>+				clock-names = "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma2 22 0 FSL_EDMA_RX&gt;, &lt;&amp;edma2 21 0 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpuart6: serial@425a0000 {</div><div class='add'>+				compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",</div><div class='add'>+					     "fsl,imx7ulp-lpuart";</div><div class='add'>+				reg = &lt;0x425a0000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_LPUART6&gt;;</div><div class='add'>+				clock-names = "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma2 24 0 FSL_EDMA_RX&gt;, &lt;&amp;edma2 23 0 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			flexcan2: can@425b0000 {</div><div class='add'>+				compatible = "fsl,imx95-flexcan";</div><div class='add'>+				reg = &lt;0x425b0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_BUSWAKEUP&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX95_CLK_CAN2&gt;;</div><div class='add'>+				clock-names = "ipg", "per";</div><div class='add'>+				assigned-clocks = &lt;&amp;scmi_clk IMX95_CLK_CAN2&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;40000000&gt;;</div><div class='add'>+				fsl,clk-source = /bits/ 8 &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			flexcan3: can@42600000 {</div><div class='add'>+				compatible = "fsl,imx95-flexcan";</div><div class='add'>+				reg = &lt;0x42600000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_BUSWAKEUP&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX95_CLK_CAN3&gt;;</div><div class='add'>+				clock-names = "ipg", "per";</div><div class='add'>+				assigned-clocks = &lt;&amp;scmi_clk IMX95_CLK_CAN3&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;40000000&gt;;</div><div class='add'>+				fsl,clk-source = /bits/ 8 &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			flexspi1: spi@425e0000 {</div><div class='add'>+				compatible = "nxp,imx95-fspi", "nxp,imx8mm-fspi";</div><div class='add'>+				reg = &lt;0x425e0000 0x10000&gt;, &lt;0x28000000 0x8000000&gt;;</div><div class='add'>+				reg-names = "fspi_base", "fspi_mmap";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_FLEXSPI1&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX95_CLK_FLEXSPI1&gt;;</div><div class='add'>+				clock-names = "fspi_en", "fspi";</div><div class='add'>+				assigned-clocks = &lt;&amp;scmi_clk IMX95_CLK_FLEXSPI1&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;scmi_clk IMX95_CLK_SYSPLL1_PFD1&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;200000000&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sai3: sai@42650000 {</div><div class='add'>+				compatible = "fsl,imx95-sai";</div><div class='add'>+				reg = &lt;0x42650000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_BUSWAKEUP&gt;, &lt;&amp;dummy&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX95_CLK_SAI3&gt;, &lt;&amp;dummy&gt;,</div><div class='add'>+					 &lt;&amp;dummy&gt;;</div><div class='add'>+				clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";</div><div class='add'>+				dmas = &lt;&amp;edma2 61 0 FSL_EDMA_RX&gt;, &lt;&amp;edma2 60 0 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sai4: sai@42660000 {</div><div class='add'>+				compatible = "fsl,imx95-sai";</div><div class='add'>+				reg = &lt;0x42660000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_BUSWAKEUP&gt;, &lt;&amp;dummy&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX95_CLK_SAI4&gt;, &lt;&amp;dummy&gt;,</div><div class='add'>+					 &lt;&amp;dummy&gt;;</div><div class='add'>+				clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";</div><div class='add'>+				dmas = &lt;&amp;edma2 68 0 FSL_EDMA_RX&gt;, &lt;&amp;edma2 67 0 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sai5: sai@42670000 {</div><div class='add'>+				compatible = "fsl,imx95-sai";</div><div class='add'>+				reg = &lt;0x42670000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_BUSWAKEUP&gt;, &lt;&amp;dummy&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX95_CLK_SAI5&gt;, &lt;&amp;dummy&gt;,</div><div class='add'>+					 &lt;&amp;dummy&gt;;</div><div class='add'>+				clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";</div><div class='add'>+				dmas = &lt;&amp;edma2 70 0 FSL_EDMA_RX&gt;, &lt;&amp;edma2 69 0 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			xcvr: xcvr@42680000 {</div><div class='add'>+				compatible = "fsl,imx95-xcvr";</div><div class='add'>+				reg = &lt;0x42680000 0x800&gt;, &lt;0x42680800 0x400&gt;,</div><div class='add'>+				      &lt;0x42680c00 0x080&gt;, &lt;0x42680e00 0x080&gt;;</div><div class='add'>+				reg-names = "ram", "regs", "rxfifo", "txfifo";</div><div class='add'>+				interrupts = /* XCVR IRQ 0 */</div><div class='add'>+					     &lt;GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     /* XCVR IRQ 1 */</div><div class='add'>+					     &lt;GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_BUSWAKEUP&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX95_CLK_SPDIF&gt;,</div><div class='add'>+					 &lt;&amp;dummy&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX95_CLK_AUDIOXCVR&gt;;</div><div class='add'>+				clock-names = "ipg", "phy", "spba", "pll_ipg";</div><div class='add'>+				dmas = &lt;&amp;edma2 65 0 1&gt;, &lt;&amp;edma2 66 0 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpuart7: serial@42690000 {</div><div class='add'>+				compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",</div><div class='add'>+					     "fsl,imx7ulp-lpuart";</div><div class='add'>+				reg = &lt;0x42690000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_LPUART7&gt;;</div><div class='add'>+				clock-names = "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma2 88 0 FSL_EDMA_RX&gt;, &lt;&amp;edma2 87 0 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpuart8: serial@426a0000 {</div><div class='add'>+				compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",</div><div class='add'>+					     "fsl,imx7ulp-lpuart";</div><div class='add'>+				reg = &lt;0x426a0000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_LPUART8&gt;;</div><div class='add'>+				clock-names = "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma2 90 0 FSL_EDMA_RX&gt;, &lt;&amp;edma2 89 0 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpi2c5: i2c@426b0000 {</div><div class='add'>+				compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+				reg = &lt;0x426b0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_LPI2C5&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX95_CLK_BUSWAKEUP&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				dmas = &lt;&amp;edma2 71 0 0&gt;, &lt;&amp;edma2 72 0 FSL_EDMA_RX&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpi2c6: i2c@426c0000 {</div><div class='add'>+				compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+				reg = &lt;0x426c0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_LPI2C6&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX95_CLK_BUSWAKEUP&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				dmas = &lt;&amp;edma2 73 0 0&gt;, &lt;&amp;edma2 74 0 FSL_EDMA_RX&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpi2c7: i2c@426d0000 {</div><div class='add'>+				compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+				reg = &lt;0x426d0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_LPI2C7&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX95_CLK_BUSWAKEUP&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				dmas = &lt;&amp;edma2 75 0 0&gt;, &lt;&amp;edma2 76 0 FSL_EDMA_RX&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpi2c8: i2c@426e0000 {</div><div class='add'>+				compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+				reg = &lt;0x426e0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_LPI2C8&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX95_CLK_BUSWAKEUP&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				dmas = &lt;&amp;edma2 77 0 0&gt;, &lt;&amp;edma2 78 0 FSL_EDMA_RX&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpspi5: spi@426f0000 {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";</div><div class='add'>+				reg = &lt;0x426f0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_LPSPI5&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX95_CLK_BUSWAKEUP&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma2 79 0 0&gt;, &lt;&amp;edma2 80 0 FSL_EDMA_RX&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpspi6: spi@42700000 {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";</div><div class='add'>+				reg = &lt;0x42700000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_LPSPI6&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX95_CLK_BUSWAKEUP&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma2 81 0 0&gt;, &lt;&amp;edma2 82 0 FSL_EDMA_RX&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpspi7: spi@42710000 {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";</div><div class='add'>+				reg = &lt;0x42710000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_LPSPI7&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX95_CLK_BUSWAKEUP&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma2 83 0 0&gt;, &lt;&amp;edma2 84 0 FSL_EDMA_RX&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpspi8: spi@42720000 {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";</div><div class='add'>+				reg = &lt;0x42720000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_LPSPI8&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX95_CLK_BUSWAKEUP&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma2 85 0 0&gt;, &lt;&amp;edma2 86 0 FSL_EDMA_RX&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mu8: mailbox@42730000 {</div><div class='add'>+				compatible = "fsl,imx95-mu";</div><div class='add'>+				reg = &lt;0x42730000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_BUSWAKEUP&gt;;</div><div class='add'>+				#mbox-cells = &lt;2&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			flexcan4: can@427c0000 {</div><div class='add'>+				compatible = "fsl,imx95-flexcan";</div><div class='add'>+				reg = &lt;0x427c0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_BUSWAKEUP&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX95_CLK_CAN4&gt;;</div><div class='add'>+				clock-names = "ipg", "per";</div><div class='add'>+				assigned-clocks = &lt;&amp;scmi_clk IMX95_CLK_CAN4&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;40000000&gt;;</div><div class='add'>+				fsl,clk-source = /bits/ 8 &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			flexcan5: can@427d0000 {</div><div class='add'>+				compatible = "fsl,imx95-flexcan";</div><div class='add'>+				reg = &lt;0x427d0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_BUSWAKEUP&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX95_CLK_CAN5&gt;;</div><div class='add'>+				clock-names = "ipg", "per";</div><div class='add'>+				assigned-clocks = &lt;&amp;scmi_clk IMX95_CLK_CAN5&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;40000000&gt;;</div><div class='add'>+				fsl,clk-source = /bits/ 8 &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aips3: bus@42800000 {</div><div class='add'>+			compatible = "fsl,aips-bus", "simple-bus";</div><div class='add'>+			reg = &lt;0 0x42800000 0 0x800000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges = &lt;0x42800000 0x0 0x42800000 0x800000&gt;;</div><div class='add'>+</div><div class='add'>+			usdhc1: mmc@42850000 {</div><div class='add'>+				compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc";</div><div class='add'>+				reg = &lt;0x42850000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_BUSWAKEUP&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX95_CLK_WAKEUPAXI&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX95_CLK_USDHC1&gt;;</div><div class='add'>+				clock-names = "ipg", "ahb", "per";</div><div class='add'>+				assigned-clocks = &lt;&amp;scmi_clk IMX95_CLK_USDHC1&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;scmi_clk IMX95_CLK_SYSPLL1_PFD1&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+				bus-width = &lt;8&gt;;</div><div class='add'>+				fsl,tuning-start-tap = &lt;1&gt;;</div><div class='add'>+				fsl,tuning-step = &lt;2&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			usdhc2: mmc@42860000 {</div><div class='add'>+				compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc";</div><div class='add'>+				reg = &lt;0x42860000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_BUSWAKEUP&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX95_CLK_WAKEUPAXI&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX95_CLK_USDHC2&gt;;</div><div class='add'>+				clock-names = "ipg", "ahb", "per";</div><div class='add'>+				assigned-clocks = &lt;&amp;scmi_clk IMX95_CLK_USDHC2&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;scmi_clk IMX95_CLK_SYSPLL1_PFD1&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+				bus-width = &lt;4&gt;;</div><div class='add'>+				fsl,tuning-start-tap = &lt;1&gt;;</div><div class='add'>+				fsl,tuning-step = &lt;2&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			usdhc3: mmc@428b0000 {</div><div class='add'>+				compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc";</div><div class='add'>+				reg = &lt;0x428b0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_BUSWAKEUP&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX95_CLK_WAKEUPAXI&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX95_CLK_USDHC3&gt;;</div><div class='add'>+				clock-names = "ipg", "ahb", "per";</div><div class='add'>+				assigned-clocks = &lt;&amp;scmi_clk IMX95_CLK_USDHC3&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;scmi_clk IMX95_CLK_SYSPLL1_PFD1&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+				bus-width = &lt;4&gt;;</div><div class='add'>+				fsl,tuning-start-tap = &lt;1&gt;;</div><div class='add'>+				fsl,tuning-step = &lt;2&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpio2: gpio@43810000 {</div><div class='add'>+			compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio";</div><div class='add'>+			reg = &lt;0x0 0x43810000 0x0 0x1000&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_clk IMX95_CLK_BUSWAKEUP&gt;,</div><div class='add'>+				 &lt;&amp;scmi_clk IMX95_CLK_BUSWAKEUP&gt;;</div><div class='add'>+			clock-names = "gpio", "port";</div><div class='add'>+			gpio-ranges = &lt;&amp;scmi_iomuxc 0 4 32&gt;;</div><div class='add'>+			ngpios = &lt;32&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpio3: gpio@43820000 {</div><div class='add'>+			compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio";</div><div class='add'>+			reg = &lt;0x0 0x43820000 0x0 0x1000&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_clk IMX95_CLK_BUSWAKEUP&gt;,</div><div class='add'>+				 &lt;&amp;scmi_clk IMX95_CLK_BUSWAKEUP&gt;;</div><div class='add'>+			clock-names = "gpio", "port";</div><div class='add'>+			gpio-ranges = &lt;&amp;scmi_iomuxc 0 104 8&gt;, &lt;&amp;scmi_iomuxc 8 74 18&gt;,</div><div class='add'>+				      &lt;&amp;scmi_iomuxc 26 42 2&gt;, &lt;&amp;scmi_iomuxc 28 0 4&gt;;</div><div class='add'>+			ngpios = &lt;32&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpio4: gpio@43840000 {</div><div class='add'>+			compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio";</div><div class='add'>+			reg = &lt;0x0 0x43840000 0x0 0x1000&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_clk IMX95_CLK_BUSWAKEUP&gt;,</div><div class='add'>+				 &lt;&amp;scmi_clk IMX95_CLK_BUSWAKEUP&gt;;</div><div class='add'>+			clock-names = "gpio", "port";</div><div class='add'>+			gpio-ranges = &lt;&amp;scmi_iomuxc 0 46 28&gt;, &lt;&amp;scmi_iomuxc 28 44 2&gt;;</div><div class='add'>+			ngpios = &lt;30&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpio5: gpio@43850000 {</div><div class='add'>+			compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio";</div><div class='add'>+			reg = &lt;0x0 0x43850000 0x0 0x1000&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_clk IMX95_CLK_BUSWAKEUP&gt;,</div><div class='add'>+				 &lt;&amp;scmi_clk IMX95_CLK_BUSWAKEUP&gt;;</div><div class='add'>+			clock-names = "gpio", "port";</div><div class='add'>+			gpio-ranges = &lt;&amp;scmi_iomuxc 0 92 12&gt;, &lt;&amp;scmi_iomuxc 12 36 6&gt;;</div><div class='add'>+			ngpios = &lt;18&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aips1: bus@44000000 {</div><div class='add'>+			compatible = "fsl,aips-bus", "simple-bus";</div><div class='add'>+			reg = &lt;0x0 0x44000000 0x0 0x800000&gt;;</div><div class='add'>+			ranges = &lt;0x44000000 0x0 0x44000000 0x800000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			edma1: dma-controller@44000000 {</div><div class='add'>+				compatible = "fsl,imx93-edma3";</div><div class='add'>+				reg = &lt;0x44000000 0x200000&gt;;</div><div class='add'>+				#dma-cells = &lt;3&gt;;</div><div class='add'>+				dma-channels = &lt;31&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_BUSAON&gt;;</div><div class='add'>+				clock-names = "dma";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mu1: mailbox@44220000 {</div><div class='add'>+				compatible = "fsl,imx95-mu";</div><div class='add'>+				reg = &lt;0x44220000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_BUSAON&gt;;</div><div class='add'>+				#mbox-cells = &lt;2&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			system_counter: timer@44290000 {</div><div class='add'>+				compatible = "nxp,imx95-sysctr-timer";</div><div class='add'>+				reg = &lt;0x44290000 0x30000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;osc_24m&gt;;</div><div class='add'>+				clock-names = "per";</div><div class='add'>+				nxp,no-divider;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tpm1: pwm@44310000 {</div><div class='add'>+				compatible = "fsl,imx7ulp-pwm";</div><div class='add'>+				reg = &lt;0x44310000 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_BUSAON&gt;;</div><div class='add'>+				#pwm-cells = &lt;3&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tpm2: pwm@44320000 {</div><div class='add'>+				compatible = "fsl,imx7ulp-pwm";</div><div class='add'>+				reg = &lt;0x44320000 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_TPM2&gt;;</div><div class='add'>+				#pwm-cells = &lt;3&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i3c1: i3c@44330000 {</div><div class='add'>+				compatible = "nxp,imx95-i3c", "silvaco,i3c-master-v1";</div><div class='add'>+				reg = &lt;0x44330000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;3&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_BUSAON&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX95_CLK_I3C1SLOW&gt;;</div><div class='add'>+				clock-names = "pclk", "fast_clk";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpi2c1: i2c@44340000 {</div><div class='add'>+				compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+				reg = &lt;0x44340000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_LPI2C1&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX95_CLK_BUSAON&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				dmas = &lt;&amp;edma1 12 0 0&gt;, &lt;&amp;edma1 13 0 FSL_EDMA_RX&gt; ;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpi2c2: i2c@44350000 {</div><div class='add'>+				compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";</div><div class='add'>+				reg = &lt;0x44350000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_LPI2C2&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX95_CLK_BUSAON&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				dmas = &lt;&amp;edma1 14 0 0&gt;, &lt;&amp;edma1 15 0 FSL_EDMA_RX&gt; ;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpspi1: spi@44360000 {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";</div><div class='add'>+				reg = &lt;0x44360000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_LPSPI1&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX95_CLK_BUSAON&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma1 16 0 FSL_EDMA_RX&gt;, &lt;&amp;edma1 17 0 0&gt; ;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpspi2: spi@44370000 {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";</div><div class='add'>+				reg = &lt;0x44370000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_LPSPI2&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX95_CLK_BUSAON&gt;;</div><div class='add'>+				clock-names = "per", "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma1 18 0 FSL_EDMA_RX&gt;, &lt;&amp;edma1 19 0 0&gt; ;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpuart1: serial@44380000 {</div><div class='add'>+				compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",</div><div class='add'>+					     "fsl,imx7ulp-lpuart";</div><div class='add'>+				reg = &lt;0x44380000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_LPUART1&gt;;</div><div class='add'>+				clock-names = "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma1 21 0 FSL_EDMA_RX&gt;, &lt;&amp;edma1 20 0 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpuart2: serial@44390000 {</div><div class='add'>+				compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",</div><div class='add'>+					     "fsl,imx7ulp-lpuart";</div><div class='add'>+				reg = &lt;0x44390000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_LPUART2&gt;;</div><div class='add'>+				clock-names = "ipg";</div><div class='add'>+				dmas = &lt;&amp;edma1 23 0 FSL_EDMA_RX&gt;, &lt;&amp;edma1 22 0 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			flexcan1: can@443a0000 {</div><div class='add'>+				compatible = "fsl,imx95-flexcan";</div><div class='add'>+				reg = &lt;0x443a0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_BUSAON&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX95_CLK_CAN1&gt;;</div><div class='add'>+				clock-names = "ipg", "per";</div><div class='add'>+				assigned-clocks = &lt;&amp;scmi_clk IMX95_CLK_CAN1&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;40000000&gt;;</div><div class='add'>+				fsl,clk-source = /bits/ 8 &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sai1: sai@443b0000 {</div><div class='add'>+				compatible = "fsl,imx95-sai";</div><div class='add'>+				reg = &lt;0x443b0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_BUSAON&gt;, &lt;&amp;dummy&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX95_CLK_SAI1&gt;, &lt;&amp;dummy&gt;,</div><div class='add'>+					 &lt;&amp;dummy&gt;;</div><div class='add'>+				clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";</div><div class='add'>+				dmas = &lt;&amp;edma1 25 0 FSL_EDMA_RX&gt;, &lt;&amp;edma1 24 0 0&gt;;</div><div class='add'>+				dma-names = "rx", "tx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			micfil: micfil@44520000 {</div><div class='add'>+				compatible = "fsl,imx95-micfil", "fsl,imx93-micfil";</div><div class='add'>+				reg = &lt;0x44520000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_BUSAON&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX95_CLK_PDM&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL1&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX95_CLK_AUDIOPLL2&gt;,</div><div class='add'>+					 &lt;&amp;dummy&gt;;</div><div class='add'>+				clock-names = "ipg_clk", "ipg_clk_app",</div><div class='add'>+					      "pll8k", "pll11k", "clkext3";</div><div class='add'>+				dmas = &lt;&amp;edma1 6 0 5&gt;;</div><div class='add'>+				dma-names = "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			adc1: adc@44530000 {</div><div class='add'>+				compatible = "nxp,imx93-adc";</div><div class='add'>+				reg = &lt;0x44530000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_ADC&gt;;</div><div class='add'>+				clock-names = "ipg";</div><div class='add'>+				#io-channel-cells = &lt;1&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mu2: mailbox@445b0000 {</div><div class='add'>+				compatible = "fsl,imx95-mu";</div><div class='add'>+				reg = &lt;0x445b0000 0x1000&gt;;</div><div class='add'>+				ranges;</div><div class='add'>+				interrupts = &lt;GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;1&gt;;</div><div class='add'>+				#mbox-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+				sram0: sram@445b1000 {</div><div class='add'>+					compatible = "mmio-sram";</div><div class='add'>+					reg = &lt;0x445b1000 0x400&gt;;</div><div class='add'>+					ranges = &lt;0x0 0x445b1000 0x400&gt;;</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					scmi_buf0: scmi-sram-section@0 {</div><div class='add'>+						compatible = "arm,scmi-shmem";</div><div class='add'>+						reg = &lt;0x0 0x80&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					scmi_buf1: scmi-sram-section@80 {</div><div class='add'>+						compatible = "arm,scmi-shmem";</div><div class='add'>+						reg = &lt;0x80 0x80&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mu3: mailbox@445d0000 {</div><div class='add'>+				compatible = "fsl,imx95-mu";</div><div class='add'>+				reg = &lt;0x445d0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_BUSAON&gt;;</div><div class='add'>+				#mbox-cells = &lt;2&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mu4: mailbox@445f0000 {</div><div class='add'>+				compatible = "fsl,imx95-mu";</div><div class='add'>+				reg = &lt;0x445f0000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_BUSAON&gt;;</div><div class='add'>+				#mbox-cells = &lt;2&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mu6: mailbox@44630000 {</div><div class='add'>+				compatible = "fsl,imx95-mu";</div><div class='add'>+				reg = &lt;0x44630000 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_BUSAON&gt;;</div><div class='add'>+				#mbox-cells = &lt;2&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mailbox@47300000 {</div><div class='add'>+			compatible = "fsl,imx95-mu-v2x";</div><div class='add'>+			reg = &lt;0x0 0x47300000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#mbox-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mailbox@47320000 {</div><div class='add'>+			compatible = "fsl,imx95-mu-v2x";</div><div class='add'>+			reg = &lt;0x0 0x47320000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#mbox-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mailbox@47330000 {</div><div class='add'>+			compatible = "fsl,imx95-mu-v2x";</div><div class='add'>+			reg = &lt;0x0 0x47330000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#mbox-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mailbox@47340000 {</div><div class='add'>+			compatible = "fsl,imx95-mu-v2x";</div><div class='add'>+			reg = &lt;0x0 0x47340000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#mbox-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mailbox@47350000 {</div><div class='add'>+			compatible = "fsl,imx95-mu-v2x";</div><div class='add'>+			reg = &lt;0x0 0x47350000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#mbox-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* GPIO1 is under exclusive control of System Manager */</div><div class='add'>+		gpio1: gpio@47400000 {</div><div class='add'>+			compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio";</div><div class='add'>+			reg = &lt;0x0 0x47400000 0x0 0x1000&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_clk IMX95_CLK_M33&gt;,</div><div class='add'>+				 &lt;&amp;scmi_clk IMX95_CLK_M33&gt;;</div><div class='add'>+			clock-names = "gpio", "port";</div><div class='add'>+			gpio-ranges = &lt;&amp;scmi_iomuxc 0 112 16&gt;;</div><div class='add'>+			ngpios = &lt;16&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ocotp: efuse@47510000 {</div><div class='add'>+			compatible = "fsl,imx95-ocotp", "syscon";</div><div class='add'>+			reg = &lt;0x0 0x47510000 0x0 0x10000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			eth_mac0: mac-address@0 {</div><div class='add'>+				reg = &lt;0x0514 0x6&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			eth_mac1: mac-address@1 {</div><div class='add'>+				reg = &lt;0x1514 0x6&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			eth_mac2: mac-address@2 {</div><div class='add'>+				reg = &lt;0x2514 0x6&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		elemu0: mailbox@47520000 {</div><div class='add'>+			compatible = "fsl,imx95-mu-ele";</div><div class='add'>+			reg = &lt;0x0 0x47520000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#mbox-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		elemu1: mailbox@47530000 {</div><div class='add'>+			compatible = "fsl,imx95-mu-ele";</div><div class='add'>+			reg = &lt;0x0 0x47530000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#mbox-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		elemu2: mailbox@47540000 {</div><div class='add'>+			compatible = "fsl,imx95-mu-ele";</div><div class='add'>+			reg = &lt;0x0 0x47540000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#mbox-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		elemu3: mailbox@47550000 {</div><div class='add'>+			compatible = "fsl,imx95-mu-ele";</div><div class='add'>+			reg = &lt;0x0 0x47550000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#mbox-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		elemu4: mailbox@47560000 {</div><div class='add'>+			compatible = "fsl,imx95-mu-ele";</div><div class='add'>+			reg = &lt;0x0 0x47560000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#mbox-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		elemu5: mailbox@47570000 {</div><div class='add'>+			compatible = "fsl,imx95-mu-ele";</div><div class='add'>+			reg = &lt;0x0 0x47570000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#mbox-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aips4: bus@49000000 {</div><div class='add'>+			compatible = "fsl,aips-bus", "simple-bus";</div><div class='add'>+			reg = &lt;0x0 0x49000000 0x0 0x800000&gt;;</div><div class='add'>+			ranges = &lt;0x49000000 0x0 0x49000000 0x800000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			smmu: iommu@490d0000 {</div><div class='add'>+				compatible = "arm,smmu-v3";</div><div class='add'>+				reg = &lt;0x490d0000 0x100000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 325 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					     &lt;GIC_SPI 328 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					     &lt;GIC_SPI 334 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					     &lt;GIC_SPI 326 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";</div><div class='add'>+				#iommu-cells = &lt;1&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb3: usb@4c010010 {</div><div class='add'>+			compatible = "fsl,imx95-dwc3", "fsl,imx8mp-dwc3";</div><div class='add'>+			reg = &lt;0x0 0x4c010010 0x0 0x04&gt;,</div><div class='add'>+			      &lt;0x0 0x4c1f0000 0x0 0x20&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_clk IMX95_CLK_HSIO&gt;,</div><div class='add'>+				 &lt;&amp;scmi_clk IMX95_CLK_32K&gt;;</div><div class='add'>+			clock-names = "hsio", "suspend";</div><div class='add'>+			interrupts = &lt;GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			power-domains = &lt;&amp;scmi_devpd IMX95_PD_HSIO_TOP&gt;;</div><div class='add'>+			dma-ranges = &lt;0x0 0x0 0x0 0x0 0x10 0x0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			usb3_dwc3: usb@4c100000 {</div><div class='add'>+				compatible = "snps,dwc3";</div><div class='add'>+				reg = &lt;0x0 0x4c100000 0x0 0x10000&gt;;</div><div class='add'>+				clocks = &lt;&amp;scmi_clk IMX95_CLK_HSIO&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX95_CLK_24M&gt;,</div><div class='add'>+					 &lt;&amp;scmi_clk IMX95_CLK_32K&gt;;</div><div class='add'>+				clock-names = "bus_early", "ref", "suspend";</div><div class='add'>+				interrupts = &lt;GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				phys = &lt;&amp;usb3_phy&gt;, &lt;&amp;usb3_phy&gt;;</div><div class='add'>+				phy-names = "usb2-phy", "usb3-phy";</div><div class='add'>+				snps,gfladj-refclk-lpm-sel-quirk;</div><div class='add'>+				snps,parkmode-disable-ss-quirk;</div><div class='add'>+				iommus = &lt;&amp;smmu 0xe&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		hsio_blk_ctl: syscon@4c0100c0 {</div><div class='add'>+			compatible = "nxp,imx95-hsio-blk-ctl", "syscon";</div><div class='add'>+			reg = &lt;0x0 0x4c0100c0 0x0 0x1&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk_sys100m&gt;;</div><div class='add'>+			power-domains = &lt;&amp;scmi_devpd IMX95_PD_HSIO_TOP&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb3_phy: phy@4c1f0040 {</div><div class='add'>+			compatible = "fsl,imx95-usb-phy", "fsl,imx8mp-usb-phy";</div><div class='add'>+			reg = &lt;0x0 0x4c1f0040 0x0 0x40&gt;,</div><div class='add'>+			      &lt;0x0 0x4c1fc000 0x0 0x100&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_clk IMX95_CLK_HSIO&gt;;</div><div class='add'>+			clock-names = "phy";</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;scmi_devpd IMX95_PD_HSIO_TOP&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb2: usb@4c200000 {</div><div class='add'>+			compatible = "fsl,imx95-usb", "fsl,imx7d-usb", "fsl,imx27-usb";</div><div class='add'>+			reg = &lt;0x0 0x4c200000 0x0 0x200&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_clk IMX95_CLK_HSIO&gt;,</div><div class='add'>+				 &lt;&amp;scmi_clk IMX95_CLK_32K&gt;;</div><div class='add'>+			clock-names = "usb_ctrl_root", "usb_wakeup";</div><div class='add'>+			iommus = &lt;&amp;smmu 0xf&gt;;</div><div class='add'>+			phys = &lt;&amp;usbphynop&gt;;</div><div class='add'>+			power-domains = &lt;&amp;scmi_devpd IMX95_PD_HSIO_TOP&gt;;</div><div class='add'>+			fsl,usbmisc = &lt;&amp;usbmisc 0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usbmisc: usbmisc@4c200200 {</div><div class='add'>+			compatible = "fsl,imx95-usbmisc", "fsl,imx7d-usbmisc",</div><div class='add'>+				     "fsl,imx6q-usbmisc";</div><div class='add'>+			reg = &lt;0x0 0x4c200200 0x0 0x200&gt;,</div><div class='add'>+			      &lt;0x0 0x4c010014 0x0 0x04&gt;;</div><div class='add'>+			#index-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie0: pcie@4c300000 {</div><div class='add'>+			compatible = "fsl,imx95-pcie";</div><div class='add'>+			reg = &lt;0 0x4c300000 0 0x10000&gt;,</div><div class='add'>+			      &lt;0 0x60100000 0 0xfe00000&gt;,</div><div class='add'>+			      &lt;0 0x4c360000 0 0x10000&gt;,</div><div class='add'>+			      &lt;0 0x4c340000 0 0x4000&gt;;</div><div class='add'>+			reg-names = "dbi", "config", "atu", "app";</div><div class='add'>+			ranges = &lt;0x81000000 0x0 0x00000000 0x0 0x6ff00000 0 0x00100000&gt;,</div><div class='add'>+				 &lt;0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x10000000&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			linux,pci-domain = &lt;0&gt;;</div><div class='add'>+			bus-range = &lt;0x00 0xff&gt;;</div><div class='add'>+			num-lanes = &lt;1&gt;;</div><div class='add'>+			num-viewport = &lt;8&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "msi";</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0x7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;gic 0 0 GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;gic 0 0 GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;gic 0 0 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;gic 0 0 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_clk IMX95_CLK_HSIO&gt;,</div><div class='add'>+				 &lt;&amp;scmi_clk IMX95_CLK_HSIOPLL&gt;,</div><div class='add'>+				 &lt;&amp;scmi_clk IMX95_CLK_HSIOPLL_VCO&gt;,</div><div class='add'>+				 &lt;&amp;scmi_clk IMX95_CLK_HSIOPCIEAUX&gt;,</div><div class='add'>+				 &lt;&amp;hsio_blk_ctl 0&gt;;</div><div class='add'>+			clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref";</div><div class='add'>+			assigned-clocks = &lt;&amp;scmi_clk IMX95_CLK_HSIOPLL_VCO&gt;,</div><div class='add'>+					  &lt;&amp;scmi_clk IMX95_CLK_HSIOPLL&gt;,</div><div class='add'>+					  &lt;&amp;scmi_clk IMX95_CLK_HSIOPCIEAUX&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;3600000000&gt;, &lt;100000000&gt;, &lt;10000000&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;0&gt;, &lt;0&gt;,</div><div class='add'>+						 &lt;&amp;scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2&gt;;</div><div class='add'>+			power-domains = &lt;&amp;scmi_devpd IMX95_PD_HSIO_TOP&gt;;</div><div class='add'>+			/* pcie0's Devid(BIT[7:6]) is 0x00, stream id(BIT[5:0]) is 0x10~0x17 */</div><div class='add'>+			msi-map = &lt;0x0 &amp;its 0x10 0x1&gt;,</div><div class='add'>+				  &lt;0x100 &amp;its 0x11 0x7&gt;;</div><div class='add'>+			iommu-map = &lt;0x000 &amp;smmu 0x10 0x1&gt;,</div><div class='add'>+				    &lt;0x100 &amp;smmu 0x11 0x7&gt;;</div><div class='add'>+			iommu-map-mask = &lt;0x1ff&gt;;</div><div class='add'>+			fsl,max-link-speed = &lt;3&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie0_ep: pcie-ep@4c300000 {</div><div class='add'>+			compatible = "fsl,imx95-pcie-ep";</div><div class='add'>+			reg = &lt;0 0x4c300000 0 0x10000&gt;,</div><div class='add'>+			      &lt;0 0x4c360000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x4c320000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x4c340000 0 0x4000&gt;,</div><div class='add'>+			      &lt;0 0x4c370000 0 0x10000&gt;,</div><div class='add'>+			      &lt;0x9 0 1 0&gt;;</div><div class='add'>+			reg-names = "dbi","atu", "dbi2", "app", "dma", "addr_space";</div><div class='add'>+			num-lanes = &lt;1&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "dma";</div><div class='add'>+			clocks = &lt;&amp;scmi_clk IMX95_CLK_HSIO&gt;,</div><div class='add'>+				 &lt;&amp;scmi_clk IMX95_CLK_HSIOPLL&gt;,</div><div class='add'>+				 &lt;&amp;scmi_clk IMX95_CLK_HSIOPLL_VCO&gt;,</div><div class='add'>+				 &lt;&amp;scmi_clk IMX95_CLK_HSIOPCIEAUX&gt;;</div><div class='add'>+			clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";</div><div class='add'>+			assigned-clocks = &lt;&amp;scmi_clk IMX95_CLK_HSIOPLL_VCO&gt;,</div><div class='add'>+					  &lt;&amp;scmi_clk IMX95_CLK_HSIOPLL&gt;,</div><div class='add'>+					  &lt;&amp;scmi_clk IMX95_CLK_HSIOPCIEAUX&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;3600000000&gt;, &lt;100000000&gt;, &lt;10000000&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;0&gt;, &lt;0&gt;,</div><div class='add'>+						 &lt;&amp;scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2&gt;;</div><div class='add'>+			msi-map = &lt;0x0 &amp;its 0x10 0x1&gt;;</div><div class='add'>+			power-domains = &lt;&amp;scmi_devpd IMX95_PD_HSIO_TOP&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie1: pcie@4c380000 {</div><div class='add'>+			compatible = "fsl,imx95-pcie";</div><div class='add'>+			reg = &lt;0 0x4c380000 0 0x10000&gt;,</div><div class='add'>+			      &lt;8 0x80100000 0 0xfe00000&gt;,</div><div class='add'>+			      &lt;0 0x4c3e0000 0 0x10000&gt;,</div><div class='add'>+			      &lt;0 0x4c3c0000 0 0x4000&gt;;</div><div class='add'>+			reg-names = "dbi", "config", "atu", "app";</div><div class='add'>+			ranges = &lt;0x81000000 0 0x00000000 0x8 0x8ff00000 0 0x00100000&gt;,</div><div class='add'>+				 &lt;0x82000000 0 0x10000000 0xa 0x10000000 0 0x10000000&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			linux,pci-domain = &lt;1&gt;;</div><div class='add'>+			bus-range = &lt;0x00 0xff&gt;;</div><div class='add'>+			num-lanes = &lt;1&gt;;</div><div class='add'>+			num-viewport = &lt;8&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "msi";</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0x7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;gic 0 0 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;gic 0 0 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;gic 0 0 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;gic 0 0 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_clk IMX95_CLK_HSIO&gt;,</div><div class='add'>+				 &lt;&amp;scmi_clk IMX95_CLK_HSIOPLL&gt;,</div><div class='add'>+				 &lt;&amp;scmi_clk IMX95_CLK_HSIOPLL_VCO&gt;,</div><div class='add'>+				 &lt;&amp;scmi_clk IMX95_CLK_HSIOPCIEAUX&gt;,</div><div class='add'>+				 &lt;&amp;hsio_blk_ctl 0&gt;;</div><div class='add'>+			clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref";</div><div class='add'>+			assigned-clocks = &lt;&amp;scmi_clk IMX95_CLK_HSIOPLL_VCO&gt;,</div><div class='add'>+					  &lt;&amp;scmi_clk IMX95_CLK_HSIOPLL&gt;,</div><div class='add'>+					  &lt;&amp;scmi_clk IMX95_CLK_HSIOPCIEAUX&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;3600000000&gt;, &lt;100000000&gt;, &lt;10000000&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;0&gt;, &lt;0&gt;,</div><div class='add'>+						 &lt;&amp;scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2&gt;;</div><div class='add'>+			power-domains = &lt;&amp;scmi_devpd IMX95_PD_HSIO_TOP&gt;;</div><div class='add'>+			/* pcie1's Devid(BIT[7:6]) is 0x10, stream id(BIT[5:0]) is 0x18~0x1f */</div><div class='add'>+			msi-map = &lt;0x0 &amp;its 0x98 0x1&gt;,</div><div class='add'>+				  &lt;0x100 &amp;its 0x99 0x7&gt;;</div><div class='add'>+			msi-map-mask = &lt;0x1ff&gt;;</div><div class='add'>+			/* smmu have not Devid(BIT[7:6]) */</div><div class='add'>+			iommu-map = &lt;0x000 &amp;smmu 0x18 0x1&gt;,</div><div class='add'>+				    &lt;0x100 &amp;smmu 0x19 0x7&gt;;</div><div class='add'>+			iommu-map-mask = &lt;0x1ff&gt;;</div><div class='add'>+			fsl,max-link-speed = &lt;3&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie1_ep: pcie-ep@4c380000 {</div><div class='add'>+			compatible = "fsl,imx95-pcie-ep";</div><div class='add'>+			reg = &lt;0 0x4c380000 0 0x10000&gt;,</div><div class='add'>+			      &lt;0 0x4c3e0000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x4c3a0000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x4c3c0000 0 0x4000&gt;,</div><div class='add'>+			      &lt;0 0x4c3f0000 0 0x10000&gt;,</div><div class='add'>+			      &lt;0xa 0 1 0&gt;;</div><div class='add'>+			reg-names = "dbi", "atu", "dbi2", "app", "dma", "addr_space";</div><div class='add'>+			num-lanes = &lt;1&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "dma";</div><div class='add'>+			clocks = &lt;&amp;scmi_clk IMX95_CLK_HSIO&gt;,</div><div class='add'>+				 &lt;&amp;scmi_clk IMX95_CLK_HSIOPLL&gt;,</div><div class='add'>+				 &lt;&amp;scmi_clk IMX95_CLK_HSIOPLL_VCO&gt;,</div><div class='add'>+				 &lt;&amp;scmi_clk IMX95_CLK_HSIOPCIEAUX&gt;;</div><div class='add'>+			clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";</div><div class='add'>+			assigned-clocks = &lt;&amp;scmi_clk IMX95_CLK_HSIOPLL_VCO&gt;,</div><div class='add'>+					  &lt;&amp;scmi_clk IMX95_CLK_HSIOPLL&gt;,</div><div class='add'>+					  &lt;&amp;scmi_clk IMX95_CLK_HSIOPCIEAUX&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;3600000000&gt;, &lt;100000000&gt;, &lt;10000000&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;0&gt;, &lt;0&gt;,</div><div class='add'>+						 &lt;&amp;scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2&gt;;</div><div class='add'>+			msi-map = &lt;0x0 &amp;its 0x98 0x1&gt;;</div><div class='add'>+			power-domains = &lt;&amp;scmi_devpd IMX95_PD_HSIO_TOP&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vpu_blk_ctrl: clock-controller@4c410000 {</div><div class='add'>+			compatible = "nxp,imx95-vpu-csr", "syscon";</div><div class='add'>+			reg = &lt;0x0 0x4c410000 0x0 0x10000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_clk IMX95_CLK_VPUAPB&gt;;</div><div class='add'>+			power-domains = &lt;&amp;scmi_devpd IMX95_PD_VPU&gt;;</div><div class='add'>+			assigned-clocks = &lt;&amp;scmi_clk IMX95_CLK_VPUAPB&gt;,</div><div class='add'>+					  &lt;&amp;scmi_clk IMX95_CLK_VPU&gt;,</div><div class='add'>+					  &lt;&amp;scmi_clk IMX95_CLK_VPUJPEG&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2&gt;,</div><div class='add'>+						 &lt;&amp;scmi_clk IMX95_CLK_SYSPLL1_PFD2&gt;,</div><div class='add'>+						 &lt;&amp;scmi_clk IMX95_CLK_SYSPLL1_PFD0&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;133333333&gt;, &lt;667000000&gt;, &lt;500000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		jpegdec: jpegdec@4c500000 {</div><div class='add'>+			compatible = "nxp,imx95-jpgdec", "nxp,imx8qxp-jpgdec";</div><div class='add'>+			reg = &lt;0x0 0x4C500000 0x0 0x00050000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_clk IMX95_CLK_VPU&gt;,</div><div class='add'>+				 &lt;&amp;vpu_blk_ctrl IMX95_CLK_VPUBLK_JPEG_DEC&gt;;</div><div class='add'>+			assigned-clocks = &lt;&amp;vpu_blk_ctrl IMX95_CLK_VPUBLK_JPEG_DEC&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;scmi_clk IMX95_CLK_VPUJPEG&gt;;</div><div class='add'>+			power-domains = &lt;&amp;scmi_devpd IMX95_PD_VPU&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		jpegenc: jpegenc@4c550000 {</div><div class='add'>+			compatible = "nxp,imx95-jpgenc", "nxp,imx8qxp-jpgenc";</div><div class='add'>+			reg = &lt;0x0 0x4C550000 0x0 0x00050000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_clk IMX95_CLK_VPU&gt;,</div><div class='add'>+				 &lt;&amp;vpu_blk_ctrl IMX95_CLK_VPUBLK_JPEG_ENC&gt;;</div><div class='add'>+			assigned-clocks = &lt;&amp;vpu_blk_ctrl IMX95_CLK_VPUBLK_JPEG_ENC&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;scmi_clk IMX95_CLK_VPUJPEG&gt;;</div><div class='add'>+			power-domains = &lt;&amp;scmi_devpd IMX95_PD_VPU&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		netcmix_blk_ctrl: syscon@4c810000 {</div><div class='add'>+			compatible = "nxp,imx95-netcmix-blk-ctrl", "syscon";</div><div class='add'>+			reg = &lt;0x0 0x4c810000 0x0 0x8&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_clk IMX95_CLK_BUSNETCMIX&gt;;</div><div class='add'>+			assigned-clocks = &lt;&amp;scmi_clk IMX95_CLK_BUSNETCMIX&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;133333333&gt;;</div><div class='add'>+			power-domains = &lt;&amp;scmi_devpd IMX95_PD_NETC&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sai2: sai@4c880000 {</div><div class='add'>+			compatible = "fsl,imx95-sai";</div><div class='add'>+			reg = &lt;0x0 0x4c880000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_clk IMX95_CLK_BUSNETCMIX&gt;, &lt;&amp;dummy&gt;,</div><div class='add'>+				 &lt;&amp;scmi_clk IMX95_CLK_SAI2&gt;, &lt;&amp;dummy&gt;,</div><div class='add'>+				 &lt;&amp;dummy&gt;;</div><div class='add'>+			clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";</div><div class='add'>+			power-domains = &lt;&amp;scmi_devpd IMX95_PD_NETC&gt;;</div><div class='add'>+			dmas = &lt;&amp;edma2 59 0 FSL_EDMA_RX&gt;, &lt;&amp;edma2 58 0 0&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		netc_blk_ctrl: system-controller@4cde0000 {</div><div class='add'>+			compatible = "nxp,imx95-netc-blk-ctrl";</div><div class='add'>+			reg = &lt;0x0 0x4cde0000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0x4cdf0000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0x4c81000c 0x0 0x18&gt;;</div><div class='add'>+			reg-names = "ierb", "prb", "netcmix";</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			power-domains = &lt;&amp;scmi_devpd IMX95_PD_NETC&gt;;</div><div class='add'>+			assigned-clocks = &lt;&amp;scmi_clk IMX95_CLK_ENET&gt;,</div><div class='add'>+					  &lt;&amp;scmi_clk IMX95_CLK_ENETREF&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;scmi_clk IMX95_CLK_SYSPLL1_PFD2&gt;,</div><div class='add'>+						 &lt;&amp;scmi_clk IMX95_CLK_SYSPLL1_PFD0&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;666666666&gt;, &lt;250000000&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_clk IMX95_CLK_ENET&gt;;</div><div class='add'>+			clock-names = "ipg";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			netc_bus0: pcie@4ca00000 {</div><div class='add'>+				compatible = "pci-host-ecam-generic";</div><div class='add'>+				reg = &lt;0x0 0x4ca00000 0x0 0x100000&gt;;</div><div class='add'>+				#address-cells = &lt;3&gt;;</div><div class='add'>+				#size-cells = &lt;2&gt;;</div><div class='add'>+				device_type = "pci";</div><div class='add'>+				bus-range = &lt;0x0 0x0&gt;;</div><div class='add'>+				msi-map = &lt;0x0 &amp;its 0x60 0x1&gt;,	//ENETC0 PF</div><div class='add'>+					  &lt;0x10 &amp;its 0x61 0x1&gt;, //ENETC0 VF0</div><div class='add'>+					  &lt;0x20 &amp;its 0x62 0x1&gt;, //ENETC0 VF1</div><div class='add'>+					  &lt;0x40 &amp;its 0x63 0x1&gt;, //ENETC1 PF</div><div class='add'>+					  &lt;0x80 &amp;its 0x64 0x1&gt;, //ENETC2 PF</div><div class='add'>+					  &lt;0x90 &amp;its 0x65 0x1&gt;, //ENETC2 VF0</div><div class='add'>+					  &lt;0xa0 &amp;its 0x66 0x1&gt;, //ENETC2 VF1</div><div class='add'>+					  &lt;0xc0 &amp;its 0x67 0x1&gt;; //NETC Timer</div><div class='add'>+				iommu-map = &lt;0x0 &amp;smmu 0x20 0x1&gt;,</div><div class='add'>+					    &lt;0x10 &amp;smmu 0x21 0x1&gt;,</div><div class='add'>+					    &lt;0x20 &amp;smmu 0x22 0x1&gt;,</div><div class='add'>+					    &lt;0x40 &amp;smmu 0x23 0x1&gt;,</div><div class='add'>+					    &lt;0x80 &amp;smmu 0x24 0x1&gt;,</div><div class='add'>+					    &lt;0x90 &amp;smmu 0x25 0x1&gt;,</div><div class='add'>+					    &lt;0xa0 &amp;smmu 0x26 0x1&gt;,</div><div class='add'>+					    &lt;0xc0 &amp;smmu 0x27 0x1&gt;;</div><div class='add'>+					 /* ENETC0~2 and Timer BAR0 - non-prefetchable memory */</div><div class='add'>+				ranges = &lt;0x82000000 0x0 0x4cc00000  0x0 0x4cc00000  0x0 0xe0000</div><div class='add'>+					 /* Timer BAR2 - prefetchable memory */</div><div class='add'>+					 0xc2000000 0x0 0x4cd00000  0x0 0x4cd00000  0x0 0x10000</div><div class='add'>+					 /* ENETC0~2: VF0-1 BAR0 - non-prefetchable memory */</div><div class='add'>+					 0x82000000 0x0 0x4cd20000  0x0 0x4cd20000  0x0 0x60000</div><div class='add'>+					 /* ENETC0~2: VF0-1 BAR2 - prefetchable memory */</div><div class='add'>+					 0xc2000000 0x0 0x4cd80000  0x0 0x4cd80000  0x0 0x60000&gt;;</div><div class='add'>+</div><div class='add'>+				enetc_port0: ethernet@0,0 {</div><div class='add'>+					compatible = "pci1131,e101";</div><div class='add'>+					reg = &lt;0x000000 0 0 0 0&gt;;</div><div class='add'>+					clocks = &lt;&amp;scmi_clk IMX95_CLK_ENETREF&gt;;</div><div class='add'>+					clock-names = "ref";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				enetc_port1: ethernet@8,0 {</div><div class='add'>+					compatible = "pci1131,e101";</div><div class='add'>+					reg = &lt;0x004000 0 0 0 0&gt;;</div><div class='add'>+					clocks = &lt;&amp;scmi_clk IMX95_CLK_ENETREF&gt;;</div><div class='add'>+					clock-names = "ref";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				enetc_port2: ethernet@10,0 {</div><div class='add'>+					compatible = "pci1131,e101";</div><div class='add'>+					reg = &lt;0x008000 0 0 0 0&gt;;</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				netc_timer: ethernet@18,0 {</div><div class='add'>+					compatible = "pci1131,ee02";</div><div class='add'>+					reg = &lt;0x00c000 0 0 0 0&gt;;</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			netc_bus1: pcie@4cb00000 {</div><div class='add'>+				compatible = "pci-host-ecam-generic";</div><div class='add'>+				reg = &lt;0x0 0x4cb00000 0x0 0x100000&gt;;</div><div class='add'>+				#address-cells = &lt;3&gt;;</div><div class='add'>+				#size-cells = &lt;2&gt;;</div><div class='add'>+				device_type = "pci";</div><div class='add'>+				bus-range = &lt;0x1 0x1&gt;;</div><div class='add'>+					 /* EMDIO BAR0 - non-prefetchable memory */</div><div class='add'>+				ranges = &lt;0x82000000 0x0 0x4cce0000  0x0 0x4cce0000  0x0 0x20000</div><div class='add'>+					 /* EMDIO BAR2 - prefetchable memory */</div><div class='add'>+					 0xc2000000 0x0 0x4cd10000  0x0 0x4cd10000  0x0 0x10000&gt;;</div><div class='add'>+</div><div class='add'>+				netc_emdio: mdio@0,0 {</div><div class='add'>+					compatible = "pci1131,ee00";</div><div class='add'>+					reg = &lt;0x010000 0 0 0 0&gt;;</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu: gpu@4d900000 {</div><div class='add'>+			compatible = "nxp,imx95-mali", "arm,mali-valhall-csf";</div><div class='add'>+			reg = &lt;0 0x4d900000 0 0x480000&gt;;</div><div class='add'>+			clocks = &lt;&amp;scmi_clk IMX95_CLK_GPU&gt;, &lt;&amp;scmi_clk IMX95_CLK_GPUAPB&gt;;</div><div class='add'>+			clock-names = "core", "coregroup";</div><div class='add'>+			interrupts = &lt;GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "job", "mmu", "gpu";</div><div class='add'>+			operating-points-v2 = &lt;&amp;gpu_opp_table&gt;;</div><div class='add'>+			power-domains = &lt;&amp;scmi_devpd IMX95_PD_GPU&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;1013&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ddr-pmu@4e090dc0 {</div><div class='add'>+			compatible = "fsl,imx95-ddr-pmu", "fsl,imx93-ddr-pmu";</div><div class='add'>+			reg = &lt;0x0 0x4e090dc0 0x0 0x200&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/mba8mx.dtsi b/arch/arm64/boot/dts/freescale/mba8mx.dtsi<br/>new file mode 100644<br/>index 000000000000..225cd2f1220b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/mba8mx.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/mba8mx.dtsi</a></div><div class='hunk'>@@ -0,0 +1,387 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2020-2021 TQ-Systems GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/net/ti-dp83867.h&gt;</div><div class='add'>+</div><div class='add'>+/* TQ-Systems GmbH MBa8Mx baseboard */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	backlight_lvds: backlight {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		pwms = &lt;&amp;pwm3 0 5000000 0&gt;;</div><div class='add'>+		brightness-levels = &lt;0 4 8 16 32 64 128 255&gt;;</div><div class='add'>+		default-brightness-level = &lt;7&gt;;</div><div class='add'>+		power-supply = &lt;&amp;reg_12v&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;expander2 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	beeper {</div><div class='add'>+		compatible = "pwm-beeper";</div><div class='add'>+		pwms = &lt;&amp;pwm4 0 250000 0&gt;;</div><div class='add'>+		beeper-hz = &lt;4000&gt;;</div><div class='add'>+		amp-supply = &lt;&amp;reg_vcc_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;uart3;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_xtal25: clk-xtal25 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;25000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpiobutton&gt;;</div><div class='add'>+		autorepeat;</div><div class='add'>+</div><div class='add'>+		switch-1 {</div><div class='add'>+			label = "switch1";</div><div class='add'>+			linux,code = &lt;BTN_0&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio1 5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		btn2: switch-2 {</div><div class='add'>+			label = "switch2";</div><div class='add'>+			linux,code = &lt;BTN_1&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio2 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		switch-3 {</div><div class='add'>+			label = "switch3";</div><div class='add'>+			linux,code = &lt;BTN_2&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio1 7 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio_leds: gpio-leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpioled&gt;;</div><div class='add'>+</div><div class='add'>+		led1 {</div><div class='add'>+			label = "led1";</div><div class='add'>+			gpios = &lt;&amp;gpio1 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "default-on";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led2: led2 {</div><div class='add'>+			label = "led2";</div><div class='add'>+			gpios = &lt;&amp;gpio3 14 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio_delays: gpio-delays {</div><div class='add'>+		compatible = "gpio-delay";</div><div class='add'>+		#gpio-cells = &lt;3&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		gpios = &lt;&amp;expander0 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		gpio-line-names = "LVDS_BRIDGE_EN_1V8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	panel: panel-lvds {</div><div class='add'>+		/*</div><div class='add'>+		 * Display is not fixed, so compatible has to be added from</div><div class='add'>+		 * DT overlay</div><div class='add'>+		 */</div><div class='add'>+		backlight = &lt;&amp;backlight_lvds&gt;;</div><div class='add'>+		power-supply = &lt;&amp;reg_vcc_3v3&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			panel_in_lvds: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;lvds_bridge_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_12v: regulator-12v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "MBA8MX_12V";</div><div class='add'>+		regulator-min-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_hub_vbus: regulator-hub-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "MBA8MX_HUB_VBUS";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_sn65dsi83_1v8: regulator-sn65dsi83-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "SN65DSI83_1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		gpio = &lt;&amp;expander0 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc_3v3: regulator-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "MBA8MX_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound: sound {</div><div class='add'>+		compatible = "fsl,imx-audio-tlv320aic32x4";</div><div class='add'>+		model = "tqm-tlv320aic32";</div><div class='add'>+		ssi-controller = &lt;&amp;sai3&gt;;</div><div class='add'>+		audio-codec = &lt;&amp;tlv320aic3x04&gt;;</div><div class='add'>+		audio-routing =</div><div class='add'>+			"IN3_L", "Mic Jack",</div><div class='add'>+			"Mic Jack", "Mic Bias",</div><div class='add'>+			"IN1_L", "Line In Jack",</div><div class='add'>+			"IN1_R", "Line In Jack",</div><div class='add'>+			"Line Out Jack", "LOL",</div><div class='add'>+			"Line Out Jack", "LOR";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi1&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ecspi2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_ecspi2&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;gpio5 13 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec1&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	phy-supply = &lt;&amp;reg_vcc_3v3&gt;;</div><div class='add'>+	fsl,magic-packet;</div><div class='add'>+	mac-address = [ 00 00 00 00 00 00 ];</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@e {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;0xe&gt;;</div><div class='add'>+			ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_2_50_NS&gt;;</div><div class='add'>+			ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_2_50_NS&gt;;</div><div class='add'>+			ti,fifo-depth = &lt;DP83867_PHYCR_FIFO_DEPTH_4_B_NIB&gt;;</div><div class='add'>+			ti,dp83867-rxctrl-strap-quirk;</div><div class='add'>+			ti,clk-output-sel = &lt;DP83867_CLK_O_SEL_OFF&gt;;</div><div class='add'>+			enet-phy-lane-no-swap;</div><div class='add'>+			reset-gpios = &lt;&amp;expander2 7 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;500000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;500&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;expander2&gt;;</div><div class='add'>+			interrupts = &lt;6 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	expander0: gpio@23 {</div><div class='add'>+		compatible = "nxp,pca9555";</div><div class='add'>+		reg = &lt;0x23&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_vcc_3v3&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;9 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		gpio-line-names = "", "", "", "",</div><div class='add'>+				  "", "", "LVDS_BRIDGE_EN", "",</div><div class='add'>+				  "", "", "", "",</div><div class='add'>+				  "", "", "", "";</div><div class='add'>+</div><div class='add'>+		sd-mux-oe-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;8 0&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+			line-name = "SD_MUX_EN#";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		boot-cfg-oe-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;12 0&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+			line-name = "BOOT_CFG_OE#";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rst_usb_hub_hog: rst-usb-hub-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;13 0&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+			line-name = "RST_USB_HUB#";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	expander1: gpio@24 {</div><div class='add'>+		compatible = "nxp,pca9555";</div><div class='add'>+		reg = &lt;0x24&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_vcc_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c2&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c2_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	tlv320aic3x04: audio-codec@18 {</div><div class='add'>+		compatible = "ti,tlv320aic32x4";</div><div class='add'>+		reg = &lt;0x18&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;expander2 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		iov-supply = &lt;&amp;reg_vcc_3v3&gt;;</div><div class='add'>+		ldoin-supply = &lt;&amp;reg_vcc_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sensor1: temperator-sensor@1f {</div><div class='add'>+		compatible = "nxp,se97b", "jedec,jc-42.4-temp";</div><div class='add'>+		reg = &lt;0x1f&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * TUSB8041 is at 0x41, but not connected by default</div><div class='add'>+	 * Note: TUSB8041 only supports 100 kHz!</div><div class='add'>+	 */</div><div class='add'>+</div><div class='add'>+	eeprom3: eeprom@57 {</div><div class='add'>+		compatible = "nxp,se97b", "atmel,24c02";</div><div class='add'>+		reg = &lt;0x57&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_vcc_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcieclk: clk@68 {</div><div class='add'>+		compatible = "renesas,9fgv0441";</div><div class='add'>+		reg = &lt;0x68&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk_xtal25&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_i2c3&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_i2c3_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	dsi_lvds_bridge: bridge@2d {</div><div class='add'>+		compatible = "ti,sn65dsi84";</div><div class='add'>+		reg = &lt;0x2d&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;gpio_delays 0 130000 0&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_sn65dsi83_1v8&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				lvds_bridge_in: endpoint {</div><div class='add'>+					data-lanes = &lt;1 2 3 4&gt;;</div><div class='add'>+					remote-endpoint = &lt;&amp;mipi_dsi_out&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@2 {</div><div class='add'>+				reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+				lvds_bridge_out: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;panel_in_lvds&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_dsi_out {</div><div class='add'>+	data-lanes = &lt;1 2 3 4&gt;;</div><div class='add'>+	remote-endpoint = &lt;&amp;lvds_bridge_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pwm4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai3&gt;;</div><div class='add'>+	#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;49152000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;snvs_pwrkey {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* console */</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio2 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+	no-mmc;</div><div class='add'>+	no-sdio;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_usdhc2_vmmc&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/mba8xx.dtsi b/arch/arm64/boot/dts/freescale/mba8xx.dtsi<br/>new file mode 100644<br/>index 000000000000..f534dab44e8e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/mba8xx.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/mba8xx.dtsi</a></div><div class='hunk'>@@ -0,0 +1,582 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR X11)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2018-2023 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Alexander Stein</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/net/ti-dp83867.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	adc {</div><div class='add'>+		compatible = "iio-hwmon";</div><div class='add'>+		io-channels = &lt;&amp;adc0 0&gt;, &lt;&amp;adc0 1&gt;, &lt;&amp;adc0 2&gt;, &lt;&amp;adc0 3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		rtc0 = &amp;pcf85063;</div><div class='add'>+		rtc1 = &amp;rtc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	backlight_lvds: backlight-lvds {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_bl_lvds&gt;;</div><div class='add'>+		pwms = &lt;&amp;adma_pwm 0 5000000 0&gt;;</div><div class='add'>+		brightness-levels = &lt;0 4 8 16 32 64 128 255&gt;;</div><div class='add'>+		default-brightness-level = &lt;7&gt;;</div><div class='add'>+		power-supply = &lt;&amp;reg_12v0&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;lsio_gpio1 30 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;lpuart1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Non-controllable PCIe reference clock generator */</div><div class='add'>+	pcie_refclk: clock-pcie-ref {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;100000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_gpiobuttons&gt;;</div><div class='add'>+		autorepeat;</div><div class='add'>+</div><div class='add'>+		switch-a {</div><div class='add'>+			label = "switcha";</div><div class='add'>+			linux,code = &lt;BTN_0&gt;;</div><div class='add'>+			gpios = &lt;&amp;lsio_gpio1 13 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		switch-b {</div><div class='add'>+			label = "switchb";</div><div class='add'>+			linux,code = &lt;BTN_1&gt;;</div><div class='add'>+			gpios = &lt;&amp;lsio_gpio1 14 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led1 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			gpios = &lt;&amp;expander 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "default-on";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led2 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_HEARTBEAT;</div><div class='add'>+			gpios = &lt;&amp;expander 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* TODO LVDS panels */</div><div class='add'>+</div><div class='add'>+	reg_12v0: regulator-12v0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "V_12V";</div><div class='add'>+		regulator-min-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;12000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;expander 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_pcie_1v5: regulator-pcie-1v5 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "MBA8XX_PCIE_1V5";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_pcie_1v5&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;1500000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1500000&gt;;</div><div class='add'>+		gpio = &lt;&amp;lsio_gpio0 30 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		startup-delay-us = &lt;1000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_pcie_3v3: regulator-pcie-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "MBA8XX_PCIE_3V3";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_reg_pcie_3v3&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;lsio_gpio0 31 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		startup-delay-us = &lt;1000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3v3_mb: regulator-usdhc2-vmmc {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "V_3V3_MB";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "fsl,imx-audio-tlv320aic32x4";</div><div class='add'>+		model = "tqm-tlv320aic32";</div><div class='add'>+		audio-codec = &lt;&amp;tlv320aic3x04&gt;;</div><div class='add'>+		ssi-controller = &lt;&amp;sai1&gt;;</div><div class='add'>+		audio-routing =</div><div class='add'>+			"IN3_L", "Mic Jack",</div><div class='add'>+			"Mic Jack", "Mic Bias",</div><div class='add'>+			"IN1_L", "Line In Jack",</div><div class='add'>+			"IN1_R", "Line In Jack",</div><div class='add'>+			"Line Out Jack", "LOL",</div><div class='add'>+			"Line Out Jack", "LOR";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;adc0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_adc0&gt;;</div><div class='add'>+	vref-supply = &lt;&amp;reg_1v8&gt;;</div><div class='add'>+	#io-channel-cells = &lt;1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;adma_pwm {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_admapwm&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec1&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@0 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_ethphy0&gt;;</div><div class='add'>+			ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_2_25_NS&gt;;</div><div class='add'>+			ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_2_25_NS&gt;;</div><div class='add'>+			ti,fifo-depth = &lt;DP83867_PHYCR_FIFO_DEPTH_4_B_NIB&gt;;</div><div class='add'>+			ti,dp83867-rxctrl-strap-quirk;</div><div class='add'>+			ti,clk-output-sel = &lt;DP83867_CLK_O_SEL_OFF&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;lsio_gpio3 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;500000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;50000&gt;;</div><div class='add'>+			enet-phy-lane-no-swap;</div><div class='add'>+			interrupt-parent = &lt;&amp;lsio_gpio3&gt;;</div><div class='add'>+			interrupts = &lt;0 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ethphy3: ethernet-phy@3 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;3&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_ethphy3&gt;;</div><div class='add'>+			ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_2_25_NS&gt;;</div><div class='add'>+			ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_2_25_NS&gt;;</div><div class='add'>+			ti,fifo-depth = &lt;DP83867_PHYCR_FIFO_DEPTH_4_B_NIB&gt;;</div><div class='add'>+			ti,dp83867-rxctrl-strap-quirk;</div><div class='add'>+			ti,clk-output-sel = &lt;DP83867_CLK_O_SEL_OFF&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;lsio_gpio3 3 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;500000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;50000&gt;;</div><div class='add'>+			enet-phy-lane-no-swap;</div><div class='add'>+			interrupt-parent = &lt;&amp;lsio_gpio3&gt;;</div><div class='add'>+			interrupts = &lt;1 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec2&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_can0&gt;;</div><div class='add'>+	xceiver-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_can1&gt;;</div><div class='add'>+	xceiver-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hsio_phy {</div><div class='add'>+	fsl,hsio-cfg = "pciea-x2-pcieb";</div><div class='add'>+	fsl,refclk-pad-mode = "input";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	tlv320aic3x04: audio-codec@18 {</div><div class='add'>+		compatible = "ti,tlv320aic32x4";</div><div class='add'>+		reg = &lt;0x18&gt;;</div><div class='add'>+		clocks = &lt;&amp;mclkout0_lpcg 0&gt;;</div><div class='add'>+		clock-names = "mclk";</div><div class='add'>+		iov-supply = &lt;&amp;reg_1v8&gt;;</div><div class='add'>+		ldoin-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	se97b_1c: temperature-sensor@1c {</div><div class='add'>+		compatible = "nxp,se97b", "jedec,jc-42.4-temp";</div><div class='add'>+		reg = &lt;0x1c&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	at24c02_54: eeprom@54 {</div><div class='add'>+		compatible = "nxp,se97b", "atmel,24c02";</div><div class='add'>+		reg = &lt;0x54&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	expander: gpio@70 {</div><div class='add'>+		compatible = "nxp,pca9538";</div><div class='add'>+		reg = &lt;0x70&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_pca9538&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;lsio_gpio4&gt;;</div><div class='add'>+		interrupts = &lt;19 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_1v8&gt;;</div><div class='add'>+</div><div class='add'>+		gpio-line-names = "", "LED_A",</div><div class='add'>+				  "LED_B", "",</div><div class='add'>+				  "DSI_EN", "USB_RESET#",</div><div class='add'>+				  "V_12V_EN", "PCIE_DIS#";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c2&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_lpi2c2gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;lsio_gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;lsio_gpio2 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* TODO LDB */</div><div class='add'>+</div><div class='add'>+&amp;lpspi1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_spi1&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;lsio_gpio0 27 GPIO_ACTIVE_LOW&gt;, &lt;&amp;lsio_gpio0 29 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpspi2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_spi2&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;lsio_gpio1 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpspi3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_spi3&gt;;</div><div class='add'>+	num-cs = &lt;2&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;lsio_gpio0 16 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpuart1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpuart3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lsgpio3&gt;;</div><div class='add'>+	gpio-line-names = "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "X4_15",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcieb {</div><div class='add'>+	phys = &lt;&amp;hsio_phy 0 PHY_TYPE_PCIE 0&gt;;</div><div class='add'>+	phy-names = "pcie-phy";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_pcieb&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	reset-gpios = &lt;&amp;lsio_gpio4 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vpcie-supply = &lt;&amp;reg_pcie_1v5&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai1 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS&gt;,</div><div class='add'>+			  &lt;&amp;sai1_lpcg 0&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;786432000&gt;, &lt;49152000&gt;, &lt;12288000&gt;, &lt;49152000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usbotg1&gt;;</div><div class='add'>+	srp-disable;</div><div class='add'>+	hnp-disable;</div><div class='add'>+	adp-disable;</div><div class='add'>+	power-active-high;</div><div class='add'>+	over-current-active-low;</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg3_cdns3 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbphy1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;lsio_gpio4 22 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	wp-gpios = &lt;&amp;lsio_gpio4 21 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_3v3_mb&gt;;</div><div class='add'>+	no-1-8-v;</div><div class='add'>+	no-sdio;</div><div class='add'>+	no-mmc;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_adc0: adc0grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_ADC_IN0_ADMA_ADC_IN0	0x02000060&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ADC_IN1_ADMA_ADC_IN1	0x02000060&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ADC_IN2_ADMA_ADC_IN2	0x02000060&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ADC_IN3_ADMA_ADC_IN3	0x02000060&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_admapwm: admapwmgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT	0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_bl_lvds: bllvdsgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO30	0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_can0: can0grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_UART0_RX_ADMA_FLEXCAN0_RX		0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QXP_UART0_TX_ADMA_FLEXCAN0_TX		0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_can1: can1grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_UART2_RX_ADMA_FLEXCAN1_RX		0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QXP_UART2_TX_ADMA_FLEXCAN1_TX		0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ethphy0: ethphy0grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_CSI_EN_LSIO_GPIO3_IO02		0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00		0x00000040&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ethphy3: ethphy3grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03		0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01		0x00000040&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec1: fec1grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_ENET0_MDC_CONN_ENET0_MDC			0x06000041&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO			0x06000041&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC	0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2	0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3	0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC	0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2	0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3	0x00000040&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec2: fec2grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL		0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ESAI0_FSR_CONN_ENET1_RGMII_TXC		0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0		0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1		0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ESAI0_FST_CONN_ENET1_RGMII_TXD2		0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3		0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ESAI0_TX0_CONN_ENET1_RGMII_RXC		0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL		0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0		0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1		0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2		0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ESAI0_TX1_CONN_ENET1_RGMII_RXD3		0x00000040&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_gpiobuttons: gpiobuttonsgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_ADC_IN5_LSIO_GPIO1_IO13	0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ADC_IN4_LSIO_GPIO1_IO14	0x00000020&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c2: lpi2c2grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_MIPI_DSI1_GPIO0_00_ADMA_I2C2_SCL	0x06000021&gt;,</div><div class='add'>+			   &lt;IMX8QXP_MIPI_DSI1_GPIO0_01_ADMA_I2C2_SDA	0x06000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c2gpio: lpi2c2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31	0x06000021&gt;,</div><div class='add'>+			   &lt;IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00	0x06000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpuart1: lpuart1grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_UART1_RX_ADMA_UART1_RX	0x06000020&gt;,</div><div class='add'>+			   &lt;IMX8QXP_UART1_TX_ADMA_UART1_TX	0x06000020&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpuart3: lpuart3grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX	0x06000020&gt;,</div><div class='add'>+			   &lt;IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX	0x06000020&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lsgpio3: lsgpio3grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15	0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pca9538: pca9538grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19	0x00000020&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcieb: pciebgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00		0x06000041&gt;,</div><div class='add'>+			   &lt;IMX8QXP_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B	0x06000041&gt;,</div><div class='add'>+			   &lt;IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02		0x04000041&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_pcie_1v5: regpcie1v5grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_SAI1_RXC_LSIO_GPIO0_IO30	0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_reg_pcie_3v3: regpcie3v3grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31	0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai1: sai1grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_MCLK_OUT0_ADMA_ACM_MCLK_OUT0	0x06000041&gt;,</div><div class='add'>+			   &lt;IMX8QXP_FLEXCAN0_RX_ADMA_SAI1_TXC		0x06000041&gt;,</div><div class='add'>+			   &lt;IMX8QXP_FLEXCAN0_TX_ADMA_SAI1_TXFS		0x06000041&gt;,</div><div class='add'>+			   &lt;IMX8QXP_FLEXCAN1_RX_ADMA_SAI1_TXD		0x06000041&gt;,</div><div class='add'>+			   &lt;IMX8QXP_FLEXCAN1_TX_ADMA_SAI1_RXD		0x06000041&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_spi1: spi1grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_SAI0_TXC_ADMA_SPI1_SDI	0x00000041&gt;,</div><div class='add'>+			   &lt;IMX8QXP_SAI0_TXD_ADMA_SPI1_SDO	0x00000041&gt;,</div><div class='add'>+			   &lt;IMX8QXP_SAI0_TXFS_ADMA_SPI1_SCK	0x00000041&gt;,</div><div class='add'>+			   &lt;IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27	0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29	0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_spi2: spi2grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK	0x00000041&gt;,</div><div class='add'>+			   &lt;IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI	0x00000041&gt;,</div><div class='add'>+			   &lt;IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO	0x00000041&gt;,</div><div class='add'>+			   &lt;IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00	0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_spi3: spi3grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_SPI3_SCK_ADMA_SPI3_SCK	0x00000041&gt;,</div><div class='add'>+			   &lt;IMX8QXP_SPI3_SDI_ADMA_SPI3_SDI	0x00000041&gt;,</div><div class='add'>+			   &lt;IMX8QXP_SPI3_SDO_ADMA_SPI3_SDO	0x00000041&gt;,</div><div class='add'>+			   &lt;IMX8QXP_SPI3_CS0_LSIO_GPIO0_IO16	0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QXP_SPI3_CS1_ADMA_SPI3_CS1	0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usbotg1: usbotg1grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_USB_SS3_TC0_CONN_USB_OTG1_PWR	0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QXP_USB_SS3_TC2_CONN_USB_OTG1_OC	0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21		0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22		0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041&gt;,</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD		0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD		0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000020&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD		0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000020&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi<br/>index dbd2fc3ba790..1b2b20c6126d 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi</a></div><div class='hunk'>@@ -27,12 +27,13 @@ fman@1a00000 {</div><div class='ctx'> 		reg = &lt;0xf0000 0x1000&gt;;</div><div class='ctx'> 		fsl,fman-ports = &lt;&amp;fman0_rx_0x10 &amp;fman0_tx_0x30&gt;;</div><div class='ctx'> 		pcsphy-handle = &lt;&amp;pcsphy6&gt;;</div><div class='add'>+		pcs-handle = &lt;&amp;pcsphy6&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	mdio@f1000 {</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;0&gt;;</div><div class='del'>-		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";</div><div class='add'>+		compatible = "fsl,fman-memac-mdio";</div><div class='ctx'> 		reg = &lt;0xf1000 0x1000&gt;;</div><div class='ctx'> </div><div class='ctx'> 		pcsphy6: ethernet-phy@0 {</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi<br/>index 6fc5d2560057..55d78f6f7c6c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi</a></div><div class='hunk'>@@ -27,12 +27,13 @@ fman@1a00000 {</div><div class='ctx'> 		reg = &lt;0xf2000 0x1000&gt;;</div><div class='ctx'> 		fsl,fman-ports = &lt;&amp;fman0_rx_0x11 &amp;fman0_tx_0x31&gt;;</div><div class='ctx'> 		pcsphy-handle = &lt;&amp;pcsphy7&gt;;</div><div class='add'>+		pcs-handle = &lt;&amp;pcsphy7&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	mdio@f3000 {</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;0&gt;;</div><div class='del'>-		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";</div><div class='add'>+		compatible = "fsl,fman-memac-mdio";</div><div class='ctx'> 		reg = &lt;0xf3000 0x1000&gt;;</div><div class='ctx'> </div><div class='ctx'> 		pcsphy7: ethernet-phy@0 {</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi<br/>index 4e02276fcf99..18916a860c2e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi</a></div><div class='hunk'>@@ -26,12 +26,13 @@ fman@1a00000 {</div><div class='ctx'> 		fsl,fman-ports = &lt;&amp;fman0_rx_0x08 &amp;fman0_tx_0x28&gt;;</div><div class='ctx'> 		ptp-timer = &lt;&amp;ptp_timer0&gt;;</div><div class='ctx'> 		pcsphy-handle = &lt;&amp;pcsphy0&gt;;</div><div class='add'>+		pcs-handle = &lt;&amp;pcsphy0&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	mdio@e1000 {</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;0&gt;;</div><div class='del'>-		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";</div><div class='add'>+		compatible = "fsl,fman-memac-mdio";</div><div class='ctx'> 		reg = &lt;0xe1000 0x1000&gt;;</div><div class='ctx'> </div><div class='ctx'> 		pcsphy0: ethernet-phy@0 {</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi<br/>index 0312fa43fa77..e90af445a293 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi</a></div><div class='hunk'>@@ -26,12 +26,13 @@ fman@1a00000 {</div><div class='ctx'> 		fsl,fman-ports = &lt;&amp;fman0_rx_0x09 &amp;fman0_tx_0x29&gt;;</div><div class='ctx'> 		ptp-timer = &lt;&amp;ptp_timer0&gt;;</div><div class='ctx'> 		pcsphy-handle = &lt;&amp;pcsphy1&gt;;</div><div class='add'>+		pcs-handle = &lt;&amp;pcsphy1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	mdio@e3000 {</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;0&gt;;</div><div class='del'>-		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";</div><div class='add'>+		compatible = "fsl,fman-memac-mdio";</div><div class='ctx'> 		reg = &lt;0xe3000 0x1000&gt;;</div><div class='ctx'> </div><div class='ctx'> 		pcsphy1: ethernet-phy@0 {</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi<br/>index af2df07971dd..fec93905bc81 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi</a></div><div class='hunk'>@@ -26,12 +26,13 @@ fman@1a00000 {</div><div class='ctx'> 		fsl,fman-ports = &lt;&amp;fman0_rx_0x0a &amp;fman0_tx_0x2a&gt;;</div><div class='ctx'> 		ptp-timer = &lt;&amp;ptp_timer0&gt;;</div><div class='ctx'> 		pcsphy-handle = &lt;&amp;pcsphy2&gt;;</div><div class='add'>+		pcs-handle = &lt;&amp;pcsphy2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	mdio@e5000 {</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;0&gt;;</div><div class='del'>-		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";</div><div class='add'>+		compatible = "fsl,fman-memac-mdio";</div><div class='ctx'> 		reg = &lt;0xe5000 0x1000&gt;;</div><div class='ctx'> </div><div class='ctx'> 		pcsphy2: ethernet-phy@0 {</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi<br/>index 4ac98dc8b227..2aa953faa62b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi</a></div><div class='hunk'>@@ -26,12 +26,13 @@ fman@1a00000 {</div><div class='ctx'> 		fsl,fman-ports = &lt;&amp;fman0_rx_0x0b &amp;fman0_tx_0x2b&gt;;</div><div class='ctx'> 		ptp-timer = &lt;&amp;ptp_timer0&gt;;</div><div class='ctx'> 		pcsphy-handle = &lt;&amp;pcsphy3&gt;;</div><div class='add'>+		pcs-handle = &lt;&amp;pcsphy3&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	mdio@e7000 {</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;0&gt;;</div><div class='del'>-		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";</div><div class='add'>+		compatible = "fsl,fman-memac-mdio";</div><div class='ctx'> 		reg = &lt;0xe7000 0x1000&gt;;</div><div class='ctx'> </div><div class='ctx'> 		pcsphy3: ethernet-phy@0 {</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi<br/>index bd932d8b0160..948e39411415 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi</a></div><div class='hunk'>@@ -26,12 +26,13 @@ fman@1a00000 {</div><div class='ctx'> 		fsl,fman-ports = &lt;&amp;fman0_rx_0x0c &amp;fman0_tx_0x2c&gt;;</div><div class='ctx'> 		ptp-timer = &lt;&amp;ptp_timer0&gt;;</div><div class='ctx'> 		pcsphy-handle = &lt;&amp;pcsphy4&gt;;</div><div class='add'>+		pcs-handle = &lt;&amp;pcsphy4&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	mdio@e9000 {</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;0&gt;;</div><div class='del'>-		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";</div><div class='add'>+		compatible = "fsl,fman-memac-mdio";</div><div class='ctx'> 		reg = &lt;0xe9000 0x1000&gt;;</div><div class='ctx'> </div><div class='ctx'> 		pcsphy4: ethernet-phy@0 {</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi<br/>index 7de1c5203f3e..01b78c0463a7 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi</a></div><div class='hunk'>@@ -31,7 +31,7 @@ fman@1a00000 {</div><div class='ctx'> 	mdio@eb000 {</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;0&gt;;</div><div class='del'>-		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";</div><div class='add'>+		compatible = "fsl,fman-memac-mdio";</div><div class='ctx'> 		reg = &lt;0xeb000 0x1000&gt;;</div><div class='ctx'> </div><div class='ctx'> 		pcsphy5: ethernet-phy@0 {</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi<br/>index 263b972a6d1e..b0390b711fef 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi</a></div><div class='hunk'>@@ -6,6 +6,8 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+#include &lt;dt-bindings/clock/fsl,qoriq-clockgen.h&gt;</div><div class='add'>+</div><div class='ctx'> fman0: fman@1a00000 {</div><div class='ctx'> 	#address-cells = &lt;1&gt;;</div><div class='ctx'> 	#size-cells = &lt;1&gt;;</div><div class='hunk'>@@ -15,10 +17,11 @@ fman0: fman@1a00000 {</div><div class='ctx'> 	reg = &lt;0x0 0x1a00000 0x0 0xfe000&gt;;</div><div class='ctx'> 	interrupts = &lt;GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 		     &lt;GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-	clocks = &lt;&amp;clockgen 3 0&gt;;</div><div class='add'>+	clocks = &lt;&amp;clockgen QORIQ_CLK_FMAN 0&gt;;</div><div class='ctx'> 	clock-names = "fmanclk";</div><div class='ctx'> 	fsl,qman-channel-range = &lt;0x800 0x10&gt;;</div><div class='ctx'> 	ptimer-handle = &lt;&amp;ptp_timer0&gt;;</div><div class='add'>+	dma-coherent;</div><div class='ctx'> </div><div class='ctx'> 	muram@0 {</div><div class='ctx'> 		compatible = "fsl,fman-muram";</div><div class='hunk'>@@ -64,14 +67,14 @@ fman0: fman@1a00000 {</div><div class='ctx'> 	mdio0: mdio@fc000 {</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;0&gt;;</div><div class='del'>-		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";</div><div class='add'>+		compatible = "fsl,fman-memac-mdio";</div><div class='ctx'> 		reg = &lt;0xfc000 0x1000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	xmdio0: mdio@fd000 {</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;0&gt;;</div><div class='del'>-		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";</div><div class='add'>+		compatible = "fsl,fman-memac-mdio";</div><div class='ctx'> 		reg = &lt;0xfd000 0x1000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='hunk'>@@ -80,5 +83,6 @@ ptp_timer0: ptp-timer@1afe000 {</div><div class='ctx'> 	compatible = "fsl,fman-ptp-timer";</div><div class='ctx'> 	reg = &lt;0x0 0x1afe000 0x0 0x1000&gt;;</div><div class='ctx'> 	interrupts = &lt;GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-	clocks = &lt;&amp;clockgen 3 0&gt;;</div><div class='add'>+	clocks = &lt;&amp;clockgen QORIQ_CLK_FMAN 0&gt;;</div><div class='add'>+	fsl,extts-fifo;</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi<br/>new file mode 100644<br/>index 000000000000..51d00dac12de<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/s32g2.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/s32g2.dtsi</a></div><div class='hunk'>@@ -0,0 +1,798 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * NXP S32G2 SoC family</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2021 SUSE LLC</div><div class='add'>+ * Copyright 2017-2021, 2024-2025 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "nxp,s32g2";</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	reserved-memory  {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		scmi_buf: shm@d0000000 {</div><div class='add'>+			compatible = "arm,scmi-shmem";</div><div class='add'>+			reg = &lt;0x0 0xd0000000 0x0 0x80&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;cluster0_l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@1 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x1&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;cluster0_l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@100 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x100&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;cluster1_l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@101 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x101&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;cluster1_l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cluster0_l2: l2-cache0 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cluster1_l2: l2-cache1 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu {</div><div class='add'>+		compatible = "arm,cortex-a53-pmu";</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	firmware {</div><div class='add'>+		scmi {</div><div class='add'>+			compatible = "arm,scmi-smc";</div><div class='add'>+			arm,smc-id = &lt;0xc20000fe&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			shmem = &lt;&amp;scmi_buf&gt;;</div><div class='add'>+</div><div class='add'>+			clks: protocol@14 {</div><div class='add'>+				reg = &lt;0x14&gt;;</div><div class='add'>+				#clock-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		psci {</div><div class='add'>+			compatible = "arm,psci-1.0";</div><div class='add'>+			method = "smc";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc@0 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges = &lt;0 0 0 0x80000000&gt;;</div><div class='add'>+</div><div class='add'>+		rtc0: rtc@40060000 {</div><div class='add'>+			compatible = "nxp,s32g2-rtc";</div><div class='add'>+			reg = &lt;0x40060000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 54&gt;, &lt;&amp;clks 55&gt;;</div><div class='add'>+			clock-names = "ipg", "source0";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl: pinctrl@4009c240 {</div><div class='add'>+			compatible = "nxp,s32g2-siul2-pinctrl";</div><div class='add'>+				/* MSCR0-MSCR101 registers on siul2_0 */</div><div class='add'>+			reg = &lt;0x4009c240 0x198&gt;,</div><div class='add'>+				/* MSCR112-MSCR122 registers on siul2_1 */</div><div class='add'>+			      &lt;0x44010400 0x2c&gt;,</div><div class='add'>+				/* MSCR144-MSCR190 registers on siul2_1 */</div><div class='add'>+			      &lt;0x44010480 0xbc&gt;,</div><div class='add'>+				/* IMCR0-IMCR83 registers on siul2_0 */</div><div class='add'>+			      &lt;0x4009ca40 0x150&gt;,</div><div class='add'>+				/* IMCR119-IMCR397 registers on siul2_1 */</div><div class='add'>+			      &lt;0x44010c1c 0x45c&gt;,</div><div class='add'>+				/* IMCR430-IMCR495 registers on siul2_1 */</div><div class='add'>+			      &lt;0x440110f8 0x108&gt;;</div><div class='add'>+</div><div class='add'>+			jtag_pins: jtag-pins {</div><div class='add'>+				jtag-grp0 {</div><div class='add'>+					pinmux = &lt;0x0&gt;;</div><div class='add'>+					input-enable;</div><div class='add'>+					bias-pull-up;</div><div class='add'>+					slew-rate = &lt;166&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				jtag-grp1 {</div><div class='add'>+					pinmux = &lt;0x11&gt;;</div><div class='add'>+					slew-rate = &lt;166&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				jtag-grp2 {</div><div class='add'>+					pinmux = &lt;0x40&gt;;</div><div class='add'>+					input-enable;</div><div class='add'>+					bias-pull-down;</div><div class='add'>+					slew-rate = &lt;166&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				jtag-grp3 {</div><div class='add'>+					pinmux = &lt;0x23c0&gt;,</div><div class='add'>+						 &lt;0x23d0&gt;,</div><div class='add'>+						 &lt;0x2320&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				jtag-grp4 {</div><div class='add'>+					pinmux = &lt;0x51&gt;;</div><div class='add'>+					input-enable;</div><div class='add'>+					bias-pull-up;</div><div class='add'>+					slew-rate = &lt;166&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pinctrl_usdhc0: usdhc0grp-pins {</div><div class='add'>+				usdhc0-grp0 {</div><div class='add'>+					pinmux = &lt;0x2e1&gt;,</div><div class='add'>+						 &lt;0x381&gt;;</div><div class='add'>+					output-enable;</div><div class='add'>+					bias-pull-down;</div><div class='add'>+					slew-rate = &lt;150&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usdhc0-grp1 {</div><div class='add'>+					pinmux = &lt;0x2f1&gt;,</div><div class='add'>+						 &lt;0x301&gt;,</div><div class='add'>+						 &lt;0x311&gt;,</div><div class='add'>+						 &lt;0x321&gt;,</div><div class='add'>+						 &lt;0x331&gt;,</div><div class='add'>+						 &lt;0x341&gt;,</div><div class='add'>+						 &lt;0x351&gt;,</div><div class='add'>+						 &lt;0x361&gt;,</div><div class='add'>+						 &lt;0x371&gt;;</div><div class='add'>+					output-enable;</div><div class='add'>+					input-enable;</div><div class='add'>+					bias-pull-up;</div><div class='add'>+					slew-rate = &lt;150&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usdhc0-grp2 {</div><div class='add'>+					pinmux = &lt;0x391&gt;;</div><div class='add'>+					output-enable;</div><div class='add'>+					slew-rate = &lt;150&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usdhc0-grp3 {</div><div class='add'>+					pinmux = &lt;0x3a0&gt;;</div><div class='add'>+					input-enable;</div><div class='add'>+					slew-rate = &lt;150&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usdhc0-grp4 {</div><div class='add'>+					pinmux = &lt;0x2032&gt;,</div><div class='add'>+						 &lt;0x2042&gt;,</div><div class='add'>+						 &lt;0x2052&gt;,</div><div class='add'>+						 &lt;0x2062&gt;,</div><div class='add'>+						 &lt;0x2072&gt;,</div><div class='add'>+						 &lt;0x2082&gt;,</div><div class='add'>+						 &lt;0x2092&gt;,</div><div class='add'>+						 &lt;0x20a2&gt;,</div><div class='add'>+						 &lt;0x20b2&gt;,</div><div class='add'>+						 &lt;0x20c2&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pinctrl_usdhc0_100mhz: usdhc0-100mhzgrp-pins {</div><div class='add'>+				usdhc0-100mhz-grp0 {</div><div class='add'>+					pinmux = &lt;0x2e1&gt;,</div><div class='add'>+						 &lt;0x381&gt;;</div><div class='add'>+					output-enable;</div><div class='add'>+					bias-pull-down;</div><div class='add'>+					slew-rate = &lt;150&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usdhc0-100mhz-grp1 {</div><div class='add'>+					pinmux = &lt;0x2f1&gt;,</div><div class='add'>+						 &lt;0x301&gt;,</div><div class='add'>+						 &lt;0x311&gt;,</div><div class='add'>+						 &lt;0x321&gt;,</div><div class='add'>+						 &lt;0x331&gt;,</div><div class='add'>+						 &lt;0x341&gt;,</div><div class='add'>+						 &lt;0x351&gt;,</div><div class='add'>+						 &lt;0x361&gt;,</div><div class='add'>+						 &lt;0x371&gt;;</div><div class='add'>+					output-enable;</div><div class='add'>+					input-enable;</div><div class='add'>+					bias-pull-up;</div><div class='add'>+					slew-rate = &lt;150&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usdhc0-100mhz-grp2 {</div><div class='add'>+					pinmux = &lt;0x391&gt;;</div><div class='add'>+					output-enable;</div><div class='add'>+					slew-rate = &lt;150&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usdhc0-100mhz-grp3 {</div><div class='add'>+					pinmux = &lt;0x3a0&gt;;</div><div class='add'>+					input-enable;</div><div class='add'>+					slew-rate = &lt;150&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usdhc0-100mhz-grp4 {</div><div class='add'>+					pinmux = &lt;0x2032&gt;,</div><div class='add'>+						 &lt;0x2042&gt;,</div><div class='add'>+						 &lt;0x2052&gt;,</div><div class='add'>+						 &lt;0x2062&gt;,</div><div class='add'>+						 &lt;0x2072&gt;,</div><div class='add'>+						 &lt;0x2082&gt;,</div><div class='add'>+						 &lt;0x2092&gt;,</div><div class='add'>+						 &lt;0x20a2&gt;,</div><div class='add'>+						 &lt;0x20b2&gt;,</div><div class='add'>+						 &lt;0x20c2&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pinctrl_usdhc0_200mhz: usdhc0-200mhzgrp-pins {</div><div class='add'>+				usdhc0-200mhz-grp0 {</div><div class='add'>+					pinmux = &lt;0x2e1&gt;,</div><div class='add'>+						 &lt;0x381&gt;;</div><div class='add'>+					output-enable;</div><div class='add'>+					bias-pull-down;</div><div class='add'>+					slew-rate = &lt;208&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usdhc0-200mhz-grp1 {</div><div class='add'>+					pinmux = &lt;0x2f1&gt;,</div><div class='add'>+						 &lt;0x301&gt;,</div><div class='add'>+						 &lt;0x311&gt;,</div><div class='add'>+						 &lt;0x321&gt;,</div><div class='add'>+						 &lt;0x331&gt;,</div><div class='add'>+						 &lt;0x341&gt;,</div><div class='add'>+						 &lt;0x351&gt;,</div><div class='add'>+						 &lt;0x361&gt;,</div><div class='add'>+						 &lt;0x371&gt;;</div><div class='add'>+					output-enable;</div><div class='add'>+					input-enable;</div><div class='add'>+					bias-pull-up;</div><div class='add'>+					slew-rate = &lt;208&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usdhc0-200mhz-grp2 {</div><div class='add'>+					pinmux = &lt;0x391&gt;;</div><div class='add'>+					output-enable;</div><div class='add'>+					slew-rate = &lt;208&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usdhc0-200mhz-grp3 {</div><div class='add'>+					pinmux = &lt;0x3a0&gt;;</div><div class='add'>+					input-enable;</div><div class='add'>+					slew-rate = &lt;208&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usdhc0-200mhz-grp4 {</div><div class='add'>+					pinmux = &lt;0x2032&gt;,</div><div class='add'>+						 &lt;0x2042&gt;,</div><div class='add'>+						 &lt;0x2052&gt;,</div><div class='add'>+						 &lt;0x2062&gt;,</div><div class='add'>+						 &lt;0x2072&gt;,</div><div class='add'>+						 &lt;0x2082&gt;,</div><div class='add'>+						 &lt;0x2092&gt;,</div><div class='add'>+						 &lt;0x20a2&gt;,</div><div class='add'>+						 &lt;0x20b2&gt;,</div><div class='add'>+						 &lt;0x20c2&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ocotp: nvmem@400a4000 {</div><div class='add'>+			compatible = "nxp,s32g2-ocotp";</div><div class='add'>+			reg = &lt;0x400a4000 0x400&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		swt0: watchdog@40100000 {</div><div class='add'>+			compatible = "nxp,s32g2-swt";</div><div class='add'>+			reg = &lt;0x40100000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 0x3a&gt;, &lt;&amp;clks 0x3b&gt;, &lt;&amp;clks 0x3b&gt;;</div><div class='add'>+			clock-names = "counter", "module", "register";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		swt1: watchdog@40104000 {</div><div class='add'>+			compatible = "nxp,s32g2-swt";</div><div class='add'>+			reg = &lt;0x40104000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 0x3a&gt;, &lt;&amp;clks 0x3b&gt;, &lt;&amp;clks 0x3b&gt;;</div><div class='add'>+			clock-names = "counter", "module", "register";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		swt2: watchdog@40108000 {</div><div class='add'>+			compatible = "nxp,s32g2-swt";</div><div class='add'>+			reg = &lt;0x40108000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 0x3a&gt;, &lt;&amp;clks 0x3b&gt;, &lt;&amp;clks 0x3b&gt;;</div><div class='add'>+			clock-names = "counter", "module", "register";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		swt3: watchdog@4010c000 {</div><div class='add'>+			compatible = "nxp,s32g2-swt";</div><div class='add'>+			reg = &lt;0x4010c000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 0x3a&gt;, &lt;&amp;clks 0x3b&gt;, &lt;&amp;clks 0x3b&gt;;</div><div class='add'>+			clock-names = "counter", "module", "register";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		stm0: timer@4011c000 {</div><div class='add'>+			compatible = "nxp,s32g2-stm";</div><div class='add'>+			reg = &lt;0x4011c000 0x3000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 0x3b&gt;, &lt;&amp;clks 0x3c&gt;, &lt;&amp;clks 0x3c&gt;;</div><div class='add'>+			clock-names = "counter", "module", "register";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		stm1: timer@40120000 {</div><div class='add'>+			compatible = "nxp,s32g2-stm";</div><div class='add'>+			reg = &lt;0x40120000 0x3000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 0x3b&gt;, &lt;&amp;clks 0x3c&gt;, &lt;&amp;clks 0x3c&gt;;</div><div class='add'>+			clock-names = "counter", "module", "register";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		stm2: timer@40124000 {</div><div class='add'>+			compatible = "nxp,s32g2-stm";</div><div class='add'>+			reg = &lt;0x40124000 0x3000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 0x3b&gt;, &lt;&amp;clks 0x3c&gt;, &lt;&amp;clks 0x3c&gt;;</div><div class='add'>+			clock-names = "counter", "module", "register";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		stm3: timer@40128000 {</div><div class='add'>+			compatible = "nxp,s32g2-stm";</div><div class='add'>+			reg = &lt;0x40128000 0x3000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 0x3b&gt;, &lt;&amp;clks 0x3c&gt;, &lt;&amp;clks 0x3c&gt;;</div><div class='add'>+			clock-names = "counter", "module", "register";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		edma0: dma-controller@40144000 {</div><div class='add'>+			compatible = "nxp,s32g2-edma";</div><div class='add'>+			reg = &lt;0x40144000 0x24000&gt;,</div><div class='add'>+			      &lt;0x4012c000 0x3000&gt;,</div><div class='add'>+			      &lt;0x40130000 0x3000&gt;;</div><div class='add'>+			#dma-cells = &lt;2&gt;;</div><div class='add'>+			dma-channels = &lt;32&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "tx-0-15",</div><div class='add'>+					  "tx-16-31",</div><div class='add'>+					  "err";</div><div class='add'>+			clocks = &lt;&amp;clks 63&gt;, &lt;&amp;clks 64&gt;;</div><div class='add'>+			clock-names = "dmamux0", "dmamux1";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		can0: can@401b4000 {</div><div class='add'>+			compatible = "nxp,s32g2-flexcan";</div><div class='add'>+			reg = &lt;0x401b4000 0xa000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "mb-0", "state", "berr", "mb-1";</div><div class='add'>+			clocks = &lt;&amp;clks 9&gt;, &lt;&amp;clks 11&gt;;</div><div class='add'>+			clock-names = "ipg", "per";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		can1: can@401be000 {</div><div class='add'>+			compatible = "nxp,s32g2-flexcan";</div><div class='add'>+			reg = &lt;0x401be000 0xa000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "mb-0", "state", "berr", "mb-1";</div><div class='add'>+			clocks = &lt;&amp;clks 9&gt;, &lt;&amp;clks 11&gt;;</div><div class='add'>+			clock-names = "ipg", "per";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart0: serial@401c8000 {</div><div class='add'>+			compatible = "nxp,s32g2-linflexuart",</div><div class='add'>+				     "fsl,s32v234-linflexuart";</div><div class='add'>+			reg = &lt;0x401c8000 0x3000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 82 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart1: serial@401cc000 {</div><div class='add'>+			compatible = "nxp,s32g2-linflexuart",</div><div class='add'>+				     "fsl,s32v234-linflexuart";</div><div class='add'>+			reg = &lt;0x401cc000 0x3000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 83 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usbmisc: usbmisc@44064200 {</div><div class='add'>+			#index-cells = &lt;1&gt;;</div><div class='add'>+			compatible = "nxp,s32g2-usbmisc";</div><div class='add'>+			reg = &lt;0x44064200 0x200&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usbotg: usb@44064000 {</div><div class='add'>+			compatible = "nxp,s32g2-usb";</div><div class='add'>+			reg = &lt;0x44064000 0x200&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH&gt;, /* OTG Core */</div><div class='add'>+					 &lt;GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH&gt;; /* OTG Wakeup */</div><div class='add'>+			clocks = &lt;&amp;clks 94&gt;, &lt;&amp;clks 95&gt;;</div><div class='add'>+			fsl,usbmisc = &lt;&amp;usbmisc 0&gt;;</div><div class='add'>+			ahb-burst-config = &lt;0x3&gt;;</div><div class='add'>+			tx-burst-size-dword = &lt;0x10&gt;;</div><div class='add'>+			rx-burst-size-dword = &lt;0x10&gt;;</div><div class='add'>+			phy_type = "ulpi";</div><div class='add'>+			dr_mode = "host";</div><div class='add'>+			maximum-speed = "high-speed";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi0: spi@401d4000 {</div><div class='add'>+			compatible = "nxp,s32g2-dspi";</div><div class='add'>+			reg = &lt;0x401d4000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 26&gt;;</div><div class='add'>+			clock-names = "dspi";</div><div class='add'>+			spi-num-chipselects = &lt;8&gt;;</div><div class='add'>+			bus-num = &lt;0&gt;;</div><div class='add'>+			dmas = &lt;&amp;edma0 0 7&gt;, &lt;&amp;edma0 0 8&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi1: spi@401d8000 {</div><div class='add'>+			compatible = "nxp,s32g2-dspi";</div><div class='add'>+			reg = &lt;0x401d8000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 26&gt;;</div><div class='add'>+			clock-names = "dspi";</div><div class='add'>+			spi-num-chipselects = &lt;5&gt;;</div><div class='add'>+			bus-num = &lt;1&gt;;</div><div class='add'>+			dmas = &lt;&amp;edma0 0 10&gt;, &lt;&amp;edma0 0 11&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi2: spi@401dc000 {</div><div class='add'>+			compatible = "nxp,s32g2-dspi";</div><div class='add'>+			reg = &lt;0x401dc000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 26&gt;;</div><div class='add'>+			clock-names = "dspi";</div><div class='add'>+			spi-num-chipselects = &lt;5&gt;;</div><div class='add'>+			bus-num = &lt;2&gt;;</div><div class='add'>+			dmas = &lt;&amp;edma0 0 13&gt;, &lt;&amp;edma0 0 14&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c0: i2c@401e4000 {</div><div class='add'>+			compatible = "nxp,s32g2-i2c";</div><div class='add'>+			reg = &lt;0x401e4000 0x1000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 40&gt;;</div><div class='add'>+			clock-names = "ipg";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c1: i2c@401e8000 {</div><div class='add'>+			compatible = "nxp,s32g2-i2c";</div><div class='add'>+			reg = &lt;0x401e8000 0x1000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 40&gt;;</div><div class='add'>+			clock-names = "ipg";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c2: i2c@401ec000 {</div><div class='add'>+			compatible = "nxp,s32g2-i2c";</div><div class='add'>+			reg = &lt;0x401ec000 0x1000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 40&gt;;</div><div class='add'>+			clock-names = "ipg";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		swt4: watchdog@40200000 {</div><div class='add'>+			compatible = "nxp,s32g2-swt";</div><div class='add'>+			reg = &lt;0x40200000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 0x3a&gt;, &lt;&amp;clks 0x3b&gt;, &lt;&amp;clks 0x3b&gt;;</div><div class='add'>+			clock-names = "counter", "module", "register";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		swt5: watchdog@40204000 {</div><div class='add'>+			compatible = "nxp,s32g2-swt";</div><div class='add'>+			reg = &lt;0x40204000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 0x3a&gt;, &lt;&amp;clks 0x3b&gt;, &lt;&amp;clks 0x3b&gt;;</div><div class='add'>+			clock-names = "counter", "module", "register";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		swt6: watchdog@40208000 {</div><div class='add'>+			compatible = "nxp,s32g2-swt";</div><div class='add'>+			reg = &lt;0x40208000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 0x3a&gt;, &lt;&amp;clks 0x3b&gt;, &lt;&amp;clks 0x3b&gt;;</div><div class='add'>+			clock-names = "counter", "module", "register";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		stm4: timer@4021c000 {</div><div class='add'>+			compatible = "nxp,s32g2-stm";</div><div class='add'>+			reg = &lt;0x4021c000 0x3000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 0x3b&gt;, &lt;&amp;clks 0x3c&gt;, &lt;&amp;clks 0x3c&gt;;</div><div class='add'>+			clock-names = "counter", "module", "register";</div><div class='add'>+			interrupts = &lt;GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		stm5: timer@40220000 {</div><div class='add'>+			compatible = "nxp,s32g2-stm";</div><div class='add'>+			reg = &lt;0x40220000 0x3000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 0x3b&gt;, &lt;&amp;clks 0x3c&gt;, &lt;&amp;clks 0x3c&gt;;</div><div class='add'>+			clock-names = "counter", "module", "register";</div><div class='add'>+			interrupts = &lt;GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		stm6: timer@40224000 {</div><div class='add'>+			compatible = "nxp,s32g2-stm";</div><div class='add'>+			reg = &lt;0x40224000 0x3000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 0x3b&gt;, &lt;&amp;clks 0x3c&gt;, &lt;&amp;clks 0x3c&gt;;</div><div class='add'>+			clock-names = "counter", "module", "register";</div><div class='add'>+			interrupts = &lt;GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		edma1: dma-controller@40244000 {</div><div class='add'>+			compatible = "nxp,s32g2-edma";</div><div class='add'>+			reg = &lt;0x40244000 0x24000&gt;,</div><div class='add'>+			      &lt;0x4022c000 0x3000&gt;,</div><div class='add'>+			      &lt;0x40230000 0x3000&gt;;</div><div class='add'>+			#dma-cells = &lt;2&gt;;</div><div class='add'>+			dma-channels = &lt;32&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "tx-0-15",</div><div class='add'>+					  "tx-16-31",</div><div class='add'>+					  "err";</div><div class='add'>+			clocks = &lt;&amp;clks 63&gt;, &lt;&amp;clks 64&gt;;</div><div class='add'>+			clock-names = "dmamux0", "dmamux1";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		can2: can@402a8000 {</div><div class='add'>+			compatible = "nxp,s32g2-flexcan";</div><div class='add'>+			reg = &lt;0x402a8000 0xa000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "mb-0", "state", "berr", "mb-1";</div><div class='add'>+			clocks = &lt;&amp;clks 9&gt;, &lt;&amp;clks 11&gt;;</div><div class='add'>+			clock-names = "ipg", "per";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		can3: can@402b2000 {</div><div class='add'>+			compatible = "nxp,s32g2-flexcan";</div><div class='add'>+			reg = &lt;0x402b2000 0xa000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "mb-0", "state", "berr", "mb-1";</div><div class='add'>+			clocks = &lt;&amp;clks 9&gt;, &lt;&amp;clks 11&gt;;</div><div class='add'>+			clock-names = "ipg", "per";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart2: serial@402bc000 {</div><div class='add'>+			compatible = "nxp,s32g2-linflexuart",</div><div class='add'>+				     "fsl,s32v234-linflexuart";</div><div class='add'>+			reg = &lt;0x402bc000 0x3000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 84 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi3: spi@402c8000 {</div><div class='add'>+			compatible = "nxp,s32g2-dspi";</div><div class='add'>+			reg = &lt;0x402c8000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 26&gt;;</div><div class='add'>+			clock-names = "dspi";</div><div class='add'>+			spi-num-chipselects = &lt;5&gt;;</div><div class='add'>+			bus-num = &lt;3&gt;;</div><div class='add'>+			dmas = &lt;&amp;edma0 1 7&gt;, &lt;&amp;edma0 1 8&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi4: spi@402cc000 {</div><div class='add'>+			compatible = "nxp,s32g2-dspi";</div><div class='add'>+			reg = &lt;0x402cc000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 26&gt;;</div><div class='add'>+			clock-names = "dspi";</div><div class='add'>+			spi-num-chipselects = &lt;5&gt;;</div><div class='add'>+			bus-num = &lt;4&gt;;</div><div class='add'>+			dmas = &lt;&amp;edma0 1 10&gt;, &lt;&amp;edma0 1 11&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi5: spi@402d0000 {</div><div class='add'>+			compatible = "nxp,s32g2-dspi";</div><div class='add'>+			reg = &lt;0x402d0000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 26&gt;;</div><div class='add'>+			clock-names = "dspi";</div><div class='add'>+			spi-num-chipselects = &lt;5&gt;;</div><div class='add'>+			bus-num = &lt;5&gt;;</div><div class='add'>+			dmas = &lt;&amp;edma0 1 13&gt;, &lt;&amp;edma0 1 14&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c3: i2c@402d8000 {</div><div class='add'>+			compatible = "nxp,s32g2-i2c";</div><div class='add'>+			reg = &lt;0x402d8000 0x1000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 40&gt;;</div><div class='add'>+			clock-names = "ipg";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c4: i2c@402dc000 {</div><div class='add'>+			compatible = "nxp,s32g2-i2c";</div><div class='add'>+			reg = &lt;0x402dc000 0x1000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 40&gt;;</div><div class='add'>+			clock-names = "ipg";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usdhc0: mmc@402f0000 {</div><div class='add'>+			compatible = "nxp,s32g2-usdhc";</div><div class='add'>+			reg = &lt;0x402f0000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 32&gt;, &lt;&amp;clks 31&gt;, &lt;&amp;clks 33&gt;;</div><div class='add'>+			clock-names = "ipg", "ahb", "per";</div><div class='add'>+			bus-width = &lt;8&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gmac0: ethernet@4033c000 {</div><div class='add'>+			compatible = "nxp,s32g2-dwmac";</div><div class='add'>+			reg = &lt;0x4033c000 0x2000&gt;, /* gmac IP */</div><div class='add'>+			      &lt;0x4007c004 0x4&gt;;    /* GMAC_0_CTRL_STS */</div><div class='add'>+			interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "macirq";</div><div class='add'>+			snps,mtl-rx-config = &lt;&amp;mtl_rx_setup&gt;;</div><div class='add'>+			snps,mtl-tx-config = &lt;&amp;mtl_tx_setup&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			mtl_rx_setup: rx-queues-config {</div><div class='add'>+				snps,rx-queues-to-use = &lt;5&gt;;</div><div class='add'>+</div><div class='add'>+				queue0 {</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				queue1 {</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				queue2 {</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				queue3 {</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				queue4 {</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mtl_tx_setup: tx-queues-config {</div><div class='add'>+				snps,tx-queues-to-use = &lt;5&gt;;</div><div class='add'>+</div><div class='add'>+				queue0 {</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				queue1 {</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				queue2 {</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				queue3 {</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				queue4 {</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gmac0mdio: mdio {</div><div class='add'>+				compatible = "snps,dwmac-mdio";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@50800000 {</div><div class='add'>+			compatible = "arm,gic-v3";</div><div class='add'>+			reg = &lt;0x50800000 0x10000&gt;,</div><div class='add'>+			      &lt;0x50880000 0x80000&gt;,</div><div class='add'>+			      &lt;0x50400000 0x2000&gt;,</div><div class='add'>+			      &lt;0x50410000 0x2000&gt;,</div><div class='add'>+			      &lt;0x50420000 0x2000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts<br/>new file mode 100644<br/>index 000000000000..aa40a52f8e53<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/s32g274a-evb.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/s32g274a-evb.dts</a></div><div class='hunk'>@@ -0,0 +1,61 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2021 SUSE LLC</div><div class='add'>+ * Copyright 2019-2021, 2024-2025 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "s32g2.dtsi"</div><div class='add'>+#include "s32gxxxa-evb.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "NXP S32G2 Evaluation Board (S32G-VNP-EVB)";</div><div class='add'>+	compatible = "nxp,s32g274a-evb", "nxp,s32g2";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;gmac0;</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* 4GiB RAM */</div><div class='add'>+	memory@80000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x80000000 0 0x80000000&gt;,</div><div class='add'>+		      &lt;0x8 0x80000000 0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* UART (J58) to Micro USB port */</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc0 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc0&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc0_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc0_200mhz&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+	no-1-8-v;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gmac0 {</div><div class='add'>+	clocks = &lt;&amp;clks 24&gt;, &lt;&amp;clks 19&gt;, &lt;&amp;clks 18&gt;, &lt;&amp;clks 15&gt;;</div><div class='add'>+	clock-names = "stmmaceth", "tx", "rx", "ptp_ref";</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;rgmiiaphy4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gmac0mdio {</div><div class='add'>+	/* KSZ 9031 on RGMII */</div><div class='add'>+	rgmiiaphy4: ethernet-phy@4 {</div><div class='add'>+		reg = &lt;4&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts<br/>new file mode 100644<br/>index 000000000000..ee3121b192e5<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts</a></div><div class='hunk'>@@ -0,0 +1,95 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2021 SUSE LLC</div><div class='add'>+ * Copyright 2019-2021, 2024 NXP</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "s32g2.dtsi"</div><div class='add'>+#include "s32gxxxa-rdb.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "NXP S32G2 Reference Design Board 2 (S32G-VNP-RDB2)";</div><div class='add'>+	compatible = "nxp,s32g274a-rdb2", "nxp,s32g2";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;gmac0;</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+		serial1 = &amp;uart1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* 4GiB RAM */</div><div class='add'>+	memory@80000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x80000000 0 0x80000000&gt;,</div><div class='add'>+		      &lt;0x8 0x80000000 0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* UART (J2) to Micro USB port */</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* UART (J1) to Micro USB port */</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;stm0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;stm1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;stm2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;stm3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;swt0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc0 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc0&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc0_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc0_200mhz&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+	/* Remove no-1-8-v to enable higher speed modes for SD card.</div><div class='add'>+	 * However, this is not enough to enable HS400 or HS200 modes for eMMC.</div><div class='add'>+	 * In this case, the position of the resistor R797 must be changed</div><div class='add'>+	 * from A to B before removing the property.</div><div class='add'>+	 * If the property is removed without changing the resistor position,</div><div class='add'>+	 * HS*00 may be enabled, but the interface might be unstable because of</div><div class='add'>+	 * the wrong VCCQ voltage applied to the eMMC.</div><div class='add'>+	 */</div><div class='add'>+	no-1-8-v;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gmac0 {</div><div class='add'>+	clocks = &lt;&amp;clks 24&gt;, &lt;&amp;clks 19&gt;, &lt;&amp;clks 18&gt;, &lt;&amp;clks 15&gt;;</div><div class='add'>+	clock-names = "stmmaceth", "tx", "rx", "ptp_ref";</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;rgmiiaphy1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gmac0mdio {</div><div class='add'>+	/* KSZ 9031 on RGMII */</div><div class='add'>+	rgmiiaphy1: ethernet-phy@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi<br/>new file mode 100644<br/>index 000000000000..eff7673e7f34<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/s32g3.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/s32g3.dtsi</a></div><div class='hunk'>@@ -0,0 +1,954 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021-2025 NXP</div><div class='add'>+ *</div><div class='add'>+ * Authors: Ghennadi Procopciuc &lt;ghennadi.procopciuc@nxp.com&gt;</div><div class='add'>+ *          Ciprian Costea &lt;ciprianmarian.costea@nxp.com&gt;</div><div class='add'>+ *          Andra-Teodora Ilie &lt;andra.ilie@nxp.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "nxp,s32g3";</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+	#address-cells = &lt;0x02&gt;;</div><div class='add'>+	#size-cells = &lt;0x02&gt;;</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu-map {</div><div class='add'>+			cluster0 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu2&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu3&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cluster1 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu4&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu5&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu6&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu7&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clocks = &lt;&amp;dfs 0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@1 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x1&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clocks = &lt;&amp;dfs 0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@2 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x2&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clocks = &lt;&amp;dfs 0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@3 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x3&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clocks = &lt;&amp;dfs 0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu4: cpu@100 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x100&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clocks = &lt;&amp;dfs 0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu5: cpu@101 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x101&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clocks = &lt;&amp;dfs 0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu6: cpu@102 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x102&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clocks = &lt;&amp;dfs 0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu7: cpu@103 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x103&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clocks = &lt;&amp;dfs 0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	firmware {</div><div class='add'>+		scmi: scmi {</div><div class='add'>+			compatible = "arm,scmi-smc";</div><div class='add'>+			shmem = &lt;&amp;scmi_shmem&gt;;</div><div class='add'>+			arm,smc-id = &lt;0xc20000fe&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			dfs: protocol@13 {</div><div class='add'>+				reg = &lt;0x13&gt;;</div><div class='add'>+				#clock-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			clks: protocol@14 {</div><div class='add'>+				reg = &lt;0x14&gt;;</div><div class='add'>+				#clock-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		psci: psci {</div><div class='add'>+			compatible = "arm,psci-1.0";</div><div class='add'>+			method = "smc";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	pmu {</div><div class='add'>+		compatible = "arm,cortex-a53-pmu";</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory  {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		scmi_shmem: shm@d0000000 {</div><div class='add'>+			compatible = "arm,scmi-shmem";</div><div class='add'>+			reg = &lt;0x0 0xd0000000 0x0 0x80&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc@0 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges = &lt;0 0 0 0x80000000&gt;;</div><div class='add'>+</div><div class='add'>+		rtc0: rtc@40060000 {</div><div class='add'>+			compatible = "nxp,s32g3-rtc",</div><div class='add'>+				     "nxp,s32g2-rtc";</div><div class='add'>+			reg = &lt;0x40060000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 54&gt;, &lt;&amp;clks 55&gt;;</div><div class='add'>+			clock-names = "ipg", "source0";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl: pinctrl@4009c240 {</div><div class='add'>+			compatible = "nxp,s32g2-siul2-pinctrl";</div><div class='add'>+				/* MSCR0-MSCR101 registers on siul2_0 */</div><div class='add'>+			reg = &lt;0x4009c240 0x198&gt;,</div><div class='add'>+				/* MSCR112-MSCR122 registers on siul2_1 */</div><div class='add'>+			      &lt;0x44010400 0x2c&gt;,</div><div class='add'>+				/* MSCR144-MSCR190 registers on siul2_1 */</div><div class='add'>+			      &lt;0x44010480 0xbc&gt;,</div><div class='add'>+				/* IMCR0-IMCR83 registers on siul2_0 */</div><div class='add'>+			      &lt;0x4009ca40 0x150&gt;,</div><div class='add'>+				/* IMCR119-IMCR397 registers on siul2_1 */</div><div class='add'>+			      &lt;0x44010c1c 0x45c&gt;,</div><div class='add'>+				/* IMCR430-IMCR495 registers on siul2_1 */</div><div class='add'>+			      &lt;0x440110f8 0x108&gt;;</div><div class='add'>+</div><div class='add'>+			jtag_pins: jtag-pins {</div><div class='add'>+				jtag-grp0 {</div><div class='add'>+					pinmux = &lt;0x0&gt;;</div><div class='add'>+					input-enable;</div><div class='add'>+					bias-pull-up;</div><div class='add'>+					slew-rate = &lt;166&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				jtag-grp1 {</div><div class='add'>+					pinmux = &lt;0x11&gt;;</div><div class='add'>+					slew-rate = &lt;166&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				jtag-grp2 {</div><div class='add'>+					pinmux = &lt;0x40&gt;;</div><div class='add'>+					input-enable;</div><div class='add'>+					bias-pull-down;</div><div class='add'>+					slew-rate = &lt;166&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				jtag-grp3 {</div><div class='add'>+					pinmux = &lt;0x23c0&gt;,</div><div class='add'>+						 &lt;0x23d0&gt;,</div><div class='add'>+						 &lt;0x2320&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				jtag-grp4 {</div><div class='add'>+					pinmux = &lt;0x51&gt;;</div><div class='add'>+					input-enable;</div><div class='add'>+					bias-pull-up;</div><div class='add'>+					slew-rate = &lt;166&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pinctrl_usdhc0: usdhc0grp-pins {</div><div class='add'>+				usdhc0-grp0 {</div><div class='add'>+					pinmux = &lt;0x2e1&gt;,</div><div class='add'>+						 &lt;0x381&gt;;</div><div class='add'>+					output-enable;</div><div class='add'>+					bias-pull-down;</div><div class='add'>+					slew-rate = &lt;150&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usdhc0-grp1 {</div><div class='add'>+					pinmux = &lt;0x2f1&gt;,</div><div class='add'>+						 &lt;0x301&gt;,</div><div class='add'>+						 &lt;0x311&gt;,</div><div class='add'>+						 &lt;0x321&gt;,</div><div class='add'>+						 &lt;0x331&gt;,</div><div class='add'>+						 &lt;0x341&gt;,</div><div class='add'>+						 &lt;0x351&gt;,</div><div class='add'>+						 &lt;0x361&gt;,</div><div class='add'>+						 &lt;0x371&gt;;</div><div class='add'>+					output-enable;</div><div class='add'>+					input-enable;</div><div class='add'>+					bias-pull-up;</div><div class='add'>+					slew-rate = &lt;150&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usdhc0-grp2 {</div><div class='add'>+					pinmux = &lt;0x391&gt;;</div><div class='add'>+					output-enable;</div><div class='add'>+					slew-rate = &lt;150&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usdhc0-grp3 {</div><div class='add'>+					pinmux = &lt;0x3a0&gt;;</div><div class='add'>+					input-enable;</div><div class='add'>+					slew-rate = &lt;150&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usdhc0-grp4 {</div><div class='add'>+					pinmux = &lt;0x2032&gt;,</div><div class='add'>+						 &lt;0x2042&gt;,</div><div class='add'>+						 &lt;0x2052&gt;,</div><div class='add'>+						 &lt;0x2062&gt;,</div><div class='add'>+						 &lt;0x2072&gt;,</div><div class='add'>+						 &lt;0x2082&gt;,</div><div class='add'>+						 &lt;0x2092&gt;,</div><div class='add'>+						 &lt;0x20a2&gt;,</div><div class='add'>+						 &lt;0x20b2&gt;,</div><div class='add'>+						 &lt;0x20c2&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pinctrl_usdhc0_100mhz: usdhc0-100mhzgrp-pins {</div><div class='add'>+				usdhc0-100mhz-grp0 {</div><div class='add'>+					pinmux = &lt;0x2e1&gt;,</div><div class='add'>+						 &lt;0x381&gt;;</div><div class='add'>+					output-enable;</div><div class='add'>+					bias-pull-down;</div><div class='add'>+					slew-rate = &lt;150&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usdhc0-100mhz-grp1 {</div><div class='add'>+					pinmux = &lt;0x2f1&gt;,</div><div class='add'>+						 &lt;0x301&gt;,</div><div class='add'>+						 &lt;0x311&gt;,</div><div class='add'>+						 &lt;0x321&gt;,</div><div class='add'>+						 &lt;0x331&gt;,</div><div class='add'>+						 &lt;0x341&gt;,</div><div class='add'>+						 &lt;0x351&gt;,</div><div class='add'>+						 &lt;0x361&gt;,</div><div class='add'>+						 &lt;0x371&gt;;</div><div class='add'>+					output-enable;</div><div class='add'>+					input-enable;</div><div class='add'>+					bias-pull-up;</div><div class='add'>+					slew-rate = &lt;150&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usdhc0-100mhz-grp2 {</div><div class='add'>+					pinmux = &lt;0x391&gt;;</div><div class='add'>+					output-enable;</div><div class='add'>+					slew-rate = &lt;150&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usdhc0-100mhz-grp3 {</div><div class='add'>+					pinmux = &lt;0x3a0&gt;;</div><div class='add'>+					input-enable;</div><div class='add'>+					slew-rate = &lt;150&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usdhc0-100mhz-grp4 {</div><div class='add'>+					pinmux = &lt;0x2032&gt;,</div><div class='add'>+						 &lt;0x2042&gt;,</div><div class='add'>+						 &lt;0x2052&gt;,</div><div class='add'>+						 &lt;0x2062&gt;,</div><div class='add'>+						 &lt;0x2072&gt;,</div><div class='add'>+						 &lt;0x2082&gt;,</div><div class='add'>+						 &lt;0x2092&gt;,</div><div class='add'>+						 &lt;0x20a2&gt;,</div><div class='add'>+						 &lt;0x20b2&gt;,</div><div class='add'>+						 &lt;0x20c2&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pinctrl_usdhc0_200mhz: usdhc0-200mhzgrp-pins {</div><div class='add'>+				usdhc0-200mhz-grp0 {</div><div class='add'>+					pinmux = &lt;0x2e1&gt;,</div><div class='add'>+						 &lt;0x381&gt;;</div><div class='add'>+					output-enable;</div><div class='add'>+					bias-pull-down;</div><div class='add'>+					slew-rate = &lt;208&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usdhc0-200mhz-grp1 {</div><div class='add'>+					pinmux = &lt;0x2f1&gt;,</div><div class='add'>+						 &lt;0x301&gt;,</div><div class='add'>+						 &lt;0x311&gt;,</div><div class='add'>+						 &lt;0x321&gt;,</div><div class='add'>+						 &lt;0x331&gt;,</div><div class='add'>+						 &lt;0x341&gt;,</div><div class='add'>+						 &lt;0x351&gt;,</div><div class='add'>+						 &lt;0x361&gt;,</div><div class='add'>+						 &lt;0x371&gt;;</div><div class='add'>+					output-enable;</div><div class='add'>+					input-enable;</div><div class='add'>+					bias-pull-up;</div><div class='add'>+					slew-rate = &lt;208&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usdhc0-200mhz-grp2 {</div><div class='add'>+					pinmux = &lt;0x391&gt;;</div><div class='add'>+					output-enable;</div><div class='add'>+					slew-rate = &lt;208&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usdhc0-200mhz-grp3 {</div><div class='add'>+					pinmux = &lt;0x3a0&gt;;</div><div class='add'>+					input-enable;</div><div class='add'>+					slew-rate = &lt;208&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usdhc0-200mhz-grp4 {</div><div class='add'>+					pinmux = &lt;0x2032&gt;,</div><div class='add'>+						 &lt;0x2042&gt;,</div><div class='add'>+						 &lt;0x2052&gt;,</div><div class='add'>+						 &lt;0x2062&gt;,</div><div class='add'>+						 &lt;0x2072&gt;,</div><div class='add'>+						 &lt;0x2082&gt;,</div><div class='add'>+						 &lt;0x2092&gt;,</div><div class='add'>+						 &lt;0x20a2&gt;,</div><div class='add'>+						 &lt;0x20b2&gt;,</div><div class='add'>+						 &lt;0x20c2&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ocotp: nvmem@400a4000 {</div><div class='add'>+			compatible = "nxp,s32g3-ocotp", "nxp,s32g2-ocotp";</div><div class='add'>+			reg = &lt;0x400a4000 0x400&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		swt0: watchdog@40100000 {</div><div class='add'>+			compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";</div><div class='add'>+			reg = &lt;0x40100000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 0x3a&gt;, &lt;&amp;clks 0x3b&gt;, &lt;&amp;clks 0x3b&gt;;</div><div class='add'>+			clock-names = "counter", "module", "register";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		swt1: watchdog@40104000 {</div><div class='add'>+			compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";</div><div class='add'>+			reg = &lt;0x40104000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 0x3a&gt;, &lt;&amp;clks 0x3b&gt;, &lt;&amp;clks 0x3b&gt;;</div><div class='add'>+			clock-names = "counter", "module", "register";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		swt2: watchdog@40108000 {</div><div class='add'>+			compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";</div><div class='add'>+			reg = &lt;0x40108000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 0x3a&gt;, &lt;&amp;clks 0x3b&gt;, &lt;&amp;clks 0x3b&gt;;</div><div class='add'>+			clock-names = "counter", "module", "register";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		swt3: watchdog@4010c000 {</div><div class='add'>+			compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";</div><div class='add'>+			reg = &lt;0x4010c000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 0x3a&gt;, &lt;&amp;clks 0x3b&gt;, &lt;&amp;clks 0x3b&gt;;</div><div class='add'>+			clock-names = "counter", "module", "register";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		stm0: timer@4011c000 {</div><div class='add'>+			compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";</div><div class='add'>+			reg = &lt;0x4011c000 0x3000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 0x3b&gt;, &lt;&amp;clks 0x3c&gt;, &lt;&amp;clks 0x3c&gt;;</div><div class='add'>+			clock-names = "counter", "module", "register";</div><div class='add'>+			interrupts = &lt;GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		stm1: timer@40120000 {</div><div class='add'>+			compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";</div><div class='add'>+			reg = &lt;0x40120000 0x3000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 0x3b&gt;, &lt;&amp;clks 0x3c&gt;, &lt;&amp;clks 0x3c&gt;;</div><div class='add'>+			clock-names = "counter", "module", "register";</div><div class='add'>+			interrupts = &lt;GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		stm2: timer@40124000 {</div><div class='add'>+			compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";</div><div class='add'>+			reg = &lt;0x40124000 0x3000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 0x3b&gt;, &lt;&amp;clks 0x3c&gt;, &lt;&amp;clks 0x3c&gt;;</div><div class='add'>+			clock-names = "counter", "module", "register";</div><div class='add'>+			interrupts = &lt;GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		stm3: timer@40128000 {</div><div class='add'>+			compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";</div><div class='add'>+			reg = &lt;0x40128000 0x3000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 0x3b&gt;, &lt;&amp;clks 0x3c&gt;, &lt;&amp;clks 0x3c&gt;;</div><div class='add'>+			clock-names = "counter", "module", "register";</div><div class='add'>+			interrupts = &lt;GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		edma0: dma-controller@40144000 {</div><div class='add'>+			compatible = "nxp,s32g3-edma", "nxp,s32g2-edma";</div><div class='add'>+			reg = &lt;0x40144000 0x24000&gt;,</div><div class='add'>+			      &lt;0x4012c000 0x3000&gt;,</div><div class='add'>+			      &lt;0x40130000 0x3000&gt;;</div><div class='add'>+			#dma-cells = &lt;2&gt;;</div><div class='add'>+			dma-channels = &lt;32&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "tx-0-15",</div><div class='add'>+					  "tx-16-31",</div><div class='add'>+					  "err";</div><div class='add'>+			clocks = &lt;&amp;clks 63&gt;, &lt;&amp;clks 64&gt;;</div><div class='add'>+			clock-names = "dmamux0", "dmamux1";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		can0: can@401b4000 {</div><div class='add'>+			compatible = "nxp,s32g3-flexcan",</div><div class='add'>+					   "nxp,s32g2-flexcan";</div><div class='add'>+			reg = &lt;0x401b4000 0xa000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "mb-0", "state", "berr", "mb-1";</div><div class='add'>+			clocks = &lt;&amp;clks 9&gt;, &lt;&amp;clks 11&gt;;</div><div class='add'>+			clock-names = "ipg", "per";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		can1: can@401be000 {</div><div class='add'>+			compatible = "nxp,s32g3-flexcan",</div><div class='add'>+					   "nxp,s32g2-flexcan";</div><div class='add'>+			reg = &lt;0x401be000 0xa000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "mb-0", "state", "berr", "mb-1";</div><div class='add'>+			clocks = &lt;&amp;clks 9&gt;, &lt;&amp;clks 11&gt;;</div><div class='add'>+			clock-names = "ipg", "per";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart0: serial@401c8000 {</div><div class='add'>+			compatible = "nxp,s32g3-linflexuart",</div><div class='add'>+				     "fsl,s32v234-linflexuart";</div><div class='add'>+			reg = &lt;0x401c8000 0x3000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 82 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart1: serial@401cc000 {</div><div class='add'>+			compatible = "nxp,s32g3-linflexuart",</div><div class='add'>+				     "fsl,s32v234-linflexuart";</div><div class='add'>+			reg = &lt;0x401cc000 0x3000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 83 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usbmisc: usbmisc@44064200 {</div><div class='add'>+			#index-cells = &lt;1&gt;;</div><div class='add'>+			compatible = "nxp,s32g3-usbmisc";</div><div class='add'>+			reg = &lt;0x44064200 0x200&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+                usbotg: usb@44064000 {</div><div class='add'>+                        compatible = "nxp,s32g3-usb", "nxp,s32g2-usb";</div><div class='add'>+                        reg = &lt;0x44064000 0x200&gt;;</div><div class='add'>+                        interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+                        interrupts = &lt;GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH&gt;, /* OTG Core */</div><div class='add'>+                                     &lt;GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH&gt;; /* OTG Wakeup */</div><div class='add'>+                        clocks = &lt;&amp;clks 94&gt;, &lt;&amp;clks 95&gt;;</div><div class='add'>+                        fsl,usbmisc = &lt;&amp;usbmisc 0&gt;;</div><div class='add'>+                        ahb-burst-config = &lt;0x3&gt;;</div><div class='add'>+                        tx-burst-size-dword = &lt;0x10&gt;;</div><div class='add'>+                        rx-burst-size-dword = &lt;0x10&gt;;</div><div class='add'>+                        phy_type = "ulpi";</div><div class='add'>+                        dr_mode = "host";</div><div class='add'>+                        maximum-speed = "high-speed";</div><div class='add'>+                        status = "disabled";</div><div class='add'>+                };</div><div class='add'>+</div><div class='add'>+		spi0: spi@401d4000 {</div><div class='add'>+			compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi";</div><div class='add'>+			reg = &lt;0x401d4000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 26&gt;;</div><div class='add'>+			clock-names = "dspi";</div><div class='add'>+			spi-num-chipselects = &lt;8&gt;;</div><div class='add'>+			bus-num = &lt;0&gt;;</div><div class='add'>+			dmas = &lt;&amp;edma0 0 7&gt;, &lt;&amp;edma0 0 8&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi1: spi@401d8000 {</div><div class='add'>+			compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi";</div><div class='add'>+			reg = &lt;0x401d8000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 26&gt;;</div><div class='add'>+			clock-names = "dspi";</div><div class='add'>+			spi-num-chipselects = &lt;5&gt;;</div><div class='add'>+			bus-num = &lt;1&gt;;</div><div class='add'>+			dmas = &lt;&amp;edma0 0 10&gt;, &lt;&amp;edma0 0 11&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi2: spi@401dc000 {</div><div class='add'>+			compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi";</div><div class='add'>+			reg = &lt;0x401dc000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 26&gt;;</div><div class='add'>+			clock-names = "dspi";</div><div class='add'>+			spi-num-chipselects = &lt;5&gt;;</div><div class='add'>+			bus-num = &lt;2&gt;;</div><div class='add'>+			dmas = &lt;&amp;edma0 0 13&gt;, &lt;&amp;edma0 0 14&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c0: i2c@401e4000 {</div><div class='add'>+			compatible = "nxp,s32g3-i2c",</div><div class='add'>+				     "nxp,s32g2-i2c";</div><div class='add'>+			reg = &lt;0x401e4000 0x1000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 40&gt;;</div><div class='add'>+			clock-names = "ipg";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c1: i2c@401e8000 {</div><div class='add'>+			compatible = "nxp,s32g3-i2c",</div><div class='add'>+				     "nxp,s32g2-i2c";</div><div class='add'>+			reg = &lt;0x401e8000 0x1000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 40&gt;;</div><div class='add'>+			clock-names = "ipg";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c2: i2c@401ec000 {</div><div class='add'>+			compatible = "nxp,s32g3-i2c",</div><div class='add'>+				     "nxp,s32g2-i2c";</div><div class='add'>+			reg = &lt;0x401ec000 0x1000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 40&gt;;</div><div class='add'>+			clock-names = "ipg";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		swt4: watchdog@40200000 {</div><div class='add'>+			compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";</div><div class='add'>+			reg = &lt;0x40200000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 0x3a&gt;, &lt;&amp;clks 0x3b&gt;, &lt;&amp;clks 0x3b&gt;;</div><div class='add'>+			clock-names = "counter", "module", "register";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		swt5: watchdog@40204000 {</div><div class='add'>+			compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";</div><div class='add'>+			reg = &lt;0x40204000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 0x3a&gt;, &lt;&amp;clks 0x3b&gt;, &lt;&amp;clks 0x3b&gt;;</div><div class='add'>+			clock-names = "counter", "module", "register";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		swt6: watchdog@40208000 {</div><div class='add'>+			compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";</div><div class='add'>+			reg = &lt;0x40208000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 0x3a&gt;, &lt;&amp;clks 0x3b&gt;, &lt;&amp;clks 0x3b&gt;;</div><div class='add'>+			clock-names = "counter", "module", "register";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		swt7: watchdog@4020C000 {</div><div class='add'>+			compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";</div><div class='add'>+			reg = &lt;0x4020C000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 0x3a&gt;, &lt;&amp;clks 0x3b&gt;, &lt;&amp;clks 0x3b&gt;;</div><div class='add'>+			clock-names = "counter", "module", "register";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		stm4: timer@4021c000 {</div><div class='add'>+			compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";</div><div class='add'>+			reg = &lt;0x4021c000 0x3000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 0x3b&gt;, &lt;&amp;clks 0x3c&gt;, &lt;&amp;clks 0x3c&gt;;</div><div class='add'>+			clock-names = "counter", "module", "register";</div><div class='add'>+			interrupts = &lt;GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		stm5: timer@40220000 {</div><div class='add'>+			compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";</div><div class='add'>+			reg = &lt;0x40220000 0x3000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 0x3b&gt;, &lt;&amp;clks 0x3c&gt;, &lt;&amp;clks 0x3c&gt;;</div><div class='add'>+			clock-names = "counter", "module", "register";</div><div class='add'>+			interrupts = &lt;GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		stm6: timer@40224000 {</div><div class='add'>+			compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";</div><div class='add'>+			reg = &lt;0x40224000 0x3000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 0x3b&gt;, &lt;&amp;clks 0x3c&gt;, &lt;&amp;clks 0x3c&gt;;</div><div class='add'>+			clock-names = "counter", "module", "register";</div><div class='add'>+			interrupts = &lt;GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		edma1: dma-controller@40244000 {</div><div class='add'>+			compatible = "nxp,s32g3-edma", "nxp,s32g2-edma";</div><div class='add'>+			reg = &lt;0x40244000 0x24000&gt;,</div><div class='add'>+			      &lt;0x4022c000 0x3000&gt;,</div><div class='add'>+			      &lt;0x40230000 0x3000&gt;;</div><div class='add'>+			#dma-cells = &lt;2&gt;;</div><div class='add'>+			dma-channels = &lt;32&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "tx-0-15",</div><div class='add'>+					  "tx-16-31",</div><div class='add'>+					  "err";</div><div class='add'>+			clocks = &lt;&amp;clks 63&gt;, &lt;&amp;clks 64&gt;;</div><div class='add'>+			clock-names = "dmamux0", "dmamux1";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		can2: can@402a8000 {</div><div class='add'>+			compatible = "nxp,s32g3-flexcan",</div><div class='add'>+					   "nxp,s32g2-flexcan";</div><div class='add'>+			reg = &lt;0x402a8000 0xa000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "mb-0", "state", "berr", "mb-1";</div><div class='add'>+			clocks = &lt;&amp;clks 9&gt;, &lt;&amp;clks 11&gt;;</div><div class='add'>+			clock-names = "ipg", "per";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		can3: can@402b2000 {</div><div class='add'>+			compatible = "nxp,s32g3-flexcan",</div><div class='add'>+					   "nxp,s32g2-flexcan";</div><div class='add'>+			reg = &lt;0x402b2000 0xa000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "mb-0", "state", "berr", "mb-1";</div><div class='add'>+			clocks = &lt;&amp;clks 9&gt;, &lt;&amp;clks 11&gt;;</div><div class='add'>+			clock-names = "ipg", "per";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart2: serial@402bc000 {</div><div class='add'>+			compatible = "nxp,s32g3-linflexuart",</div><div class='add'>+				     "fsl,s32v234-linflexuart";</div><div class='add'>+			reg = &lt;0x402bc000 0x3000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 84 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi3: spi@402c8000 {</div><div class='add'>+			compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi";</div><div class='add'>+			reg = &lt;0x402c8000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 26&gt;;</div><div class='add'>+			clock-names = "dspi";</div><div class='add'>+			spi-num-chipselects = &lt;5&gt;;</div><div class='add'>+			bus-num = &lt;3&gt;;</div><div class='add'>+			dmas = &lt;&amp;edma0 1 7&gt;, &lt;&amp;edma0 1 8&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi4: spi@402cc000 {</div><div class='add'>+			compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi";</div><div class='add'>+			reg = &lt;0x402cc000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 26&gt;;</div><div class='add'>+			clock-names = "dspi";</div><div class='add'>+			spi-num-chipselects = &lt;5&gt;;</div><div class='add'>+			bus-num = &lt;4&gt;;</div><div class='add'>+			dmas = &lt;&amp;edma0 1 10&gt;, &lt;&amp;edma0 1 11&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi5: spi@402d0000 {</div><div class='add'>+			compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi";</div><div class='add'>+			reg = &lt;0x402d0000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 26&gt;;</div><div class='add'>+			clock-names = "dspi";</div><div class='add'>+			spi-num-chipselects = &lt;5&gt;;</div><div class='add'>+			bus-num = &lt;5&gt;;</div><div class='add'>+			dmas = &lt;&amp;edma0 1 13&gt;, &lt;&amp;edma0 1 14&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c3: i2c@402d8000 {</div><div class='add'>+			compatible = "nxp,s32g3-i2c",</div><div class='add'>+				     "nxp,s32g2-i2c";</div><div class='add'>+			reg = &lt;0x402d8000 0x1000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 40&gt;;</div><div class='add'>+			clock-names = "ipg";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c4: i2c@402dc000 {</div><div class='add'>+			compatible = "nxp,s32g3-i2c",</div><div class='add'>+				     "nxp,s32g2-i2c";</div><div class='add'>+			reg = &lt;0x402dc000 0x1000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 40&gt;;</div><div class='add'>+			clock-names = "ipg";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usdhc0: mmc@402f0000 {</div><div class='add'>+			compatible = "nxp,s32g3-usdhc",</div><div class='add'>+				     "nxp,s32g2-usdhc";</div><div class='add'>+			reg = &lt;0x402f0000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 32&gt;,</div><div class='add'>+				 &lt;&amp;clks 31&gt;,</div><div class='add'>+				 &lt;&amp;clks 33&gt;;</div><div class='add'>+			clock-names = "ipg", "ahb", "per";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gmac0: ethernet@4033c000 {</div><div class='add'>+			compatible = "nxp,s32g2-dwmac";</div><div class='add'>+			reg = &lt;0x4033c000 0x2000&gt;, /* gmac IP */</div><div class='add'>+			      &lt;0x4007c004 0x4&gt;;    /* GMAC_0_CTRL_STS */</div><div class='add'>+			interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "macirq";</div><div class='add'>+			snps,mtl-rx-config = &lt;&amp;mtl_rx_setup&gt;;</div><div class='add'>+			snps,mtl-tx-config = &lt;&amp;mtl_tx_setup&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			mtl_rx_setup: rx-queues-config {</div><div class='add'>+				snps,rx-queues-to-use = &lt;5&gt;;</div><div class='add'>+</div><div class='add'>+				queue0 {</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				queue1 {</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				queue2 {</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				queue3 {</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				queue4 {</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mtl_tx_setup: tx-queues-config {</div><div class='add'>+				snps,tx-queues-to-use = &lt;5&gt;;</div><div class='add'>+</div><div class='add'>+				queue0 {</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				queue1 {</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				queue2 {</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				queue3 {</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				queue4 {</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gmac0mdio: mdio {</div><div class='add'>+				compatible = "snps,dwmac-mdio";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		swt8: watchdog@40500000 {</div><div class='add'>+			compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";</div><div class='add'>+			reg = &lt;40500000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 0x3a&gt;, &lt;&amp;clks 0x3b&gt;, &lt;&amp;clks 0x3b&gt;;</div><div class='add'>+			clock-names = "counter", "module", "register";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		swt9: watchdog@40504000 {</div><div class='add'>+			compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";</div><div class='add'>+			reg = &lt;0x40504000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 0x3a&gt;, &lt;&amp;clks 0x3b&gt;, &lt;&amp;clks 0x3b&gt;;</div><div class='add'>+			clock-names = "counter", "module", "register";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		swt10: watchdog@40508000 {</div><div class='add'>+			compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";</div><div class='add'>+			reg = &lt;0x40508000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 0x3a&gt;, &lt;&amp;clks 0x3b&gt;, &lt;&amp;clks 0x3b&gt;;</div><div class='add'>+			clock-names = "counter", "module", "register";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		swt11: watchdog@4050c000 {</div><div class='add'>+			compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";</div><div class='add'>+			reg = &lt;0x4050c000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 0x3a&gt;, &lt;&amp;clks 0x3b&gt;, &lt;&amp;clks 0x3b&gt;;</div><div class='add'>+			clock-names = "counter", "module", "register";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		stm8: timer@40520000 {</div><div class='add'>+			compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";</div><div class='add'>+			reg = &lt;0x40520000 0x3000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 0x3b&gt;, &lt;&amp;clks 0x3c&gt;, &lt;&amp;clks 0x3c&gt;;</div><div class='add'>+			clock-names = "counter", "module", "register";</div><div class='add'>+			interrupts = &lt;GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		stm9: timer@40524000 {</div><div class='add'>+			compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";</div><div class='add'>+			reg = &lt;0x40524000 0x3000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 0x3b&gt;, &lt;&amp;clks 0x3c&gt;, &lt;&amp;clks 0x3c&gt;;</div><div class='add'>+			clock-names = "counter", "module", "register";</div><div class='add'>+			interrupts = &lt;GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		stm10: timer@40528000 {</div><div class='add'>+			compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";</div><div class='add'>+			reg = &lt;0x40528000 0x3000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 0x3b&gt;, &lt;&amp;clks 0x3c&gt;, &lt;&amp;clks 0x3c&gt;;</div><div class='add'>+			clock-names = "counter", "module", "register";</div><div class='add'>+			interrupts = &lt;GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		stm11: timer@4052c000 {</div><div class='add'>+			compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";</div><div class='add'>+			reg = &lt;0x4052c000 0x3000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clks 0x3b&gt;, &lt;&amp;clks 0x3c&gt;, &lt;&amp;clks 0x3c&gt;;</div><div class='add'>+			clock-names = "counter", "module", "register";</div><div class='add'>+			interrupts = &lt;GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@50800000 {</div><div class='add'>+			compatible = "arm,gic-v3";</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			reg = &lt;0x50800000 0x10000&gt;,</div><div class='add'>+			      &lt;0x50900000 0x200000&gt;,</div><div class='add'>+			      &lt;0x50400000 0x2000&gt;,</div><div class='add'>+			      &lt;0x50410000 0x2000&gt;,</div><div class='add'>+			      &lt;0x50420000 0x2000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 IRQ_TYPE_LEVEL_LOW&gt;, /* sec-phys */</div><div class='add'>+			     &lt;GIC_PPI 14 IRQ_TYPE_LEVEL_LOW&gt;, /* phys */</div><div class='add'>+			     &lt;GIC_PPI 11 IRQ_TYPE_LEVEL_LOW&gt;, /* virt */</div><div class='add'>+			     &lt;GIC_PPI 10 IRQ_TYPE_LEVEL_LOW&gt;, /* hyp-phys */</div><div class='add'>+			     &lt;GIC_PPI 12 IRQ_TYPE_LEVEL_LOW&gt;; /* hyp-virt */</div><div class='add'>+		arm,no-tick-in-suspend;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts<br/>new file mode 100644<br/>index 000000000000..326322b62192<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts</a></div><div class='hunk'>@@ -0,0 +1,111 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021-2025 NXP</div><div class='add'>+ *</div><div class='add'>+ * NXP S32G3 Reference Design Board 3 (S32G-VNP-RDB3)</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "s32g3.dtsi"</div><div class='add'>+#include "s32gxxxa-rdb.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "NXP S32G3 Reference Design Board 3 (S32G-VNP-RDB3)";</div><div class='add'>+	compatible = "nxp,s32g399a-rdb3", "nxp,s32g3";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;gmac0;</div><div class='add'>+		mmc0 = &amp;usdhc0;</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+		serial1 = &amp;uart1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* 4GiB RAM */</div><div class='add'>+	memory@80000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x80000000 0 0x80000000&gt;,</div><div class='add'>+		      &lt;0x8 0x80000000 0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;stm0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;stm1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;stm2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;stm3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;stm4 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;stm5 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;stm6 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;stm8 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;swt0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	current-sensor@40 {</div><div class='add'>+		compatible = "ti,ina231";</div><div class='add'>+		reg = &lt;0x40&gt;;</div><div class='add'>+		shunt-resistor = &lt;1000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc0 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc0&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc0_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc0_200mhz&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gmac0 {</div><div class='add'>+	clocks = &lt;&amp;clks 24&gt;, &lt;&amp;clks 19&gt;, &lt;&amp;clks 18&gt;, &lt;&amp;clks 15&gt;;</div><div class='add'>+	clock-names = "stmmaceth", "tx", "rx", "ptp_ref";</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;rgmiiaphy1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gmac0mdio {</div><div class='add'>+	/* KSZ 9031 on RGMII */</div><div class='add'>+	rgmiiaphy1: ethernet-phy@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi<br/>new file mode 100644<br/>index 000000000000..f1969cdcef19<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi</a></div><div class='hunk'>@@ -0,0 +1,306 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 NXP</div><div class='add'>+ *</div><div class='add'>+ * Authors: Ciprian Marian Costea &lt;ciprianmarian.costea@oss.nxp.com&gt;</div><div class='add'>+ *          Ghennadi Procopciuc &lt;ghennadi.procopciuc@oss.nxp.com&gt;</div><div class='add'>+ *          Larisa Grigore &lt;larisa.grigore@nxp.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;pinctrl {</div><div class='add'>+	can0_pins: can0-pins {</div><div class='add'>+		can0-grp0 {</div><div class='add'>+			pinmux = &lt;0x2c1&gt;;</div><div class='add'>+			output-enable;</div><div class='add'>+			slew-rate = &lt;133&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		can0-grp1 {</div><div class='add'>+			pinmux = &lt;0x2b0&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			slew-rate = &lt;133&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		can0-grp2 {</div><div class='add'>+			pinmux = &lt;0x2012&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	can2_pins: can2-pins {</div><div class='add'>+		can2-grp0 {</div><div class='add'>+			pinmux = &lt;0x1b2&gt;;</div><div class='add'>+			output-enable;</div><div class='add'>+			slew-rate = &lt;133&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		can2-grp1 {</div><div class='add'>+			pinmux = &lt;0x1c0&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			slew-rate = &lt;133&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		can2-grp2 {</div><div class='add'>+			pinmux = &lt;0x2782&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	can3_pins: can3-pins {</div><div class='add'>+		can3-grp0 {</div><div class='add'>+			pinmux = &lt;0x192&gt;;</div><div class='add'>+			output-enable;</div><div class='add'>+			slew-rate = &lt;133&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		can3-grp1 {</div><div class='add'>+			pinmux = &lt;0x1a0&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			slew-rate = &lt;133&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		can3-grp2 {</div><div class='add'>+			pinmux = &lt;0x2792&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c0_pins: i2c0-pins {</div><div class='add'>+		i2c0-grp0 {</div><div class='add'>+			pinmux = &lt;0x101&gt;, &lt;0x111&gt;;</div><div class='add'>+			drive-open-drain;</div><div class='add'>+			output-enable;</div><div class='add'>+			input-enable;</div><div class='add'>+			slew-rate = &lt;133&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c0-grp1 {</div><div class='add'>+			pinmux = &lt;0x2352&gt;, &lt;0x2362&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c0_gpio_pins: i2c0-gpio-pins {</div><div class='add'>+		i2c0-gpio-grp0 {</div><div class='add'>+			pinmux = &lt;0x100&gt;, &lt;0x110&gt;;</div><div class='add'>+			drive-open-drain;</div><div class='add'>+			output-enable;</div><div class='add'>+			input-enable;</div><div class='add'>+			slew-rate = &lt;133&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c0-gpio-grp1 {</div><div class='add'>+			pinmux = &lt;0x2350&gt;, &lt;0x2360&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c1_pins: i2c1-pins {</div><div class='add'>+		i2c1-grp0 {</div><div class='add'>+			pinmux = &lt;0x131&gt;, &lt;0x141&gt;;</div><div class='add'>+			drive-open-drain;</div><div class='add'>+			output-enable;</div><div class='add'>+			input-enable;</div><div class='add'>+			slew-rate = &lt;133&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c1-grp1 {</div><div class='add'>+			pinmux = &lt;0x2cd2&gt;, &lt;0x2ce2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c1_gpio_pins: i2c1-gpio-pins {</div><div class='add'>+		i2c1-gpio-grp0 {</div><div class='add'>+			pinmux = &lt;0x130&gt;, &lt;0x140&gt;;</div><div class='add'>+			drive-open-drain;</div><div class='add'>+			output-enable;</div><div class='add'>+			input-enable;</div><div class='add'>+			slew-rate = &lt;133&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c1-gpio-grp1 {</div><div class='add'>+			pinmux = &lt;0x2cd0&gt;, &lt;0x2ce0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c2_pins: i2c2-pins {</div><div class='add'>+		i2c2-grp0 {</div><div class='add'>+			pinmux = &lt;0x151&gt;, &lt;0x161&gt;;</div><div class='add'>+			drive-open-drain;</div><div class='add'>+			output-enable;</div><div class='add'>+			input-enable;</div><div class='add'>+			slew-rate = &lt;133&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c2-grp1 {</div><div class='add'>+			pinmux = &lt;0x2cf2&gt;, &lt;0x2d02&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c2_gpio_pins: i2c2-gpio-pins {</div><div class='add'>+		i2c2-gpio-grp0 {</div><div class='add'>+			pinmux = &lt;0x150&gt;, &lt;0x160&gt;;</div><div class='add'>+			drive-open-drain;</div><div class='add'>+			output-enable;</div><div class='add'>+			input-enable;</div><div class='add'>+			slew-rate = &lt;133&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c2-gpio-grp1 {</div><div class='add'>+			pinmux = &lt;0x2cf0&gt;, &lt;0x2d00&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c4_pins: i2c4-pins {</div><div class='add'>+		i2c4-grp0 {</div><div class='add'>+			pinmux = &lt;0x211&gt;, &lt;0x222&gt;;</div><div class='add'>+			drive-open-drain;</div><div class='add'>+			output-enable;</div><div class='add'>+			input-enable;</div><div class='add'>+			slew-rate = &lt;133&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c4-grp1 {</div><div class='add'>+			pinmux = &lt;0x2d43&gt;, &lt;0x2d33&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c4_gpio_pins: i2c4-gpio-pins {</div><div class='add'>+		i2c4-gpio-grp0 {</div><div class='add'>+			pinmux = &lt;0x210&gt;, &lt;0x220&gt;;</div><div class='add'>+			drive-open-drain;</div><div class='add'>+			output-enable;</div><div class='add'>+			input-enable;</div><div class='add'>+			slew-rate = &lt;133&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c4-gpio-grp1 {</div><div class='add'>+			pinmux = &lt;0x2d40&gt;, &lt;0x2d30&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dspi1_pins: dspi1-pins {</div><div class='add'>+		dspi1-grp0 {</div><div class='add'>+			pinmux = &lt;0x72&gt;;</div><div class='add'>+			output-enable;</div><div class='add'>+			input-enable;</div><div class='add'>+			slew-rate = &lt;150&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dspi1-grp1 {</div><div class='add'>+			pinmux = &lt;0x62&gt;;</div><div class='add'>+			output-enable;</div><div class='add'>+			slew-rate = &lt;150&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dspi1-grp2 {</div><div class='add'>+			pinmux = &lt;0x83&gt;;</div><div class='add'>+			output-enable;</div><div class='add'>+			input-enable;</div><div class='add'>+			slew-rate = &lt;150&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dspi1-grp3 {</div><div class='add'>+			pinmux = &lt;0x5F0&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			slew-rate = &lt;150&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dspi1-grp4 {</div><div class='add'>+			pinmux = &lt;0x3D92&gt;,</div><div class='add'>+				 &lt;0x3DA2&gt;,</div><div class='add'>+				 &lt;0x3DB2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dspi5_pins: dspi5-pins {</div><div class='add'>+		dspi5-grp0 {</div><div class='add'>+			pinmux = &lt;0x93&gt;;</div><div class='add'>+			output-enable;</div><div class='add'>+			input-enable;</div><div class='add'>+			slew-rate = &lt;150&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dspi5-grp1 {</div><div class='add'>+			pinmux = &lt;0xA0&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			slew-rate = &lt;150&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dspi5-grp2 {</div><div class='add'>+			pinmux = &lt;0x3ED2&gt;,</div><div class='add'>+				 &lt;0x3EE2&gt;,</div><div class='add'>+				 &lt;0x3EF2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dspi5-grp3 {</div><div class='add'>+			pinmux = &lt;0xB3&gt;;</div><div class='add'>+			output-enable;</div><div class='add'>+			slew-rate = &lt;150&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dspi5-grp4 {</div><div class='add'>+			pinmux = &lt;0xC3&gt;;</div><div class='add'>+			output-enable;</div><div class='add'>+			input-enable;</div><div class='add'>+			slew-rate = &lt;150&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;can0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;can0_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;can2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;can2_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;can3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;can3_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c0_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;i2c0_gpio_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c1_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;i2c1_gpio_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c2_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;i2c2_gpio_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c4_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;i2c4_gpio_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;dspi1_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi5 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;dspi5_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi<br/>new file mode 100644<br/>index 000000000000..3bc3335c9248<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi</a></div><div class='hunk'>@@ -0,0 +1,259 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 NXP</div><div class='add'>+ *</div><div class='add'>+ * Authors: Ciprian Marian Costea &lt;ciprianmarian.costea@oss.nxp.com&gt;</div><div class='add'>+ *          Ghennadi Procopciuc &lt;ghennadi.procopciuc@oss.nxp.com&gt;</div><div class='add'>+ *          Larisa Grigore &lt;larisa.grigore@nxp.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;pinctrl {</div><div class='add'>+	can0_pins: can0-pins {</div><div class='add'>+		can0-grp0 {</div><div class='add'>+			pinmux = &lt;0x112&gt;;</div><div class='add'>+			output-enable;</div><div class='add'>+			slew-rate = &lt;133&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		can0-grp1 {</div><div class='add'>+			pinmux = &lt;0x120&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			slew-rate = &lt;133&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		can0-grp2 {</div><div class='add'>+			pinmux = &lt;0x2013&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	can1_pins: can1-pins {</div><div class='add'>+		can1-grp0 {</div><div class='add'>+			pinmux = &lt;0x132&gt;;</div><div class='add'>+			output-enable;</div><div class='add'>+			slew-rate = &lt;133&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		can1-grp1 {</div><div class='add'>+			pinmux = &lt;0x140&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			slew-rate = &lt;133&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		can1-grp2 {</div><div class='add'>+			pinmux = &lt;0x2772&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c0_pins: i2c0-pins {</div><div class='add'>+		i2c0-grp0 {</div><div class='add'>+			pinmux = &lt;0x1f2&gt;, &lt;0x201&gt;;</div><div class='add'>+			drive-open-drain;</div><div class='add'>+			output-enable;</div><div class='add'>+			input-enable;</div><div class='add'>+			slew-rate = &lt;133&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c0-grp1 {</div><div class='add'>+			pinmux = &lt;0x2353&gt;, &lt;0x2363&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c0_gpio_pins: i2c0-gpio-pins {</div><div class='add'>+		i2c0-gpio-grp0 {</div><div class='add'>+			pinmux = &lt;0x1f0&gt;, &lt;0x200&gt;;</div><div class='add'>+			drive-open-drain;</div><div class='add'>+			output-enable;</div><div class='add'>+			input-enable;</div><div class='add'>+			slew-rate = &lt;133&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c0-gpio-grp1 {</div><div class='add'>+			pinmux = &lt;0x2350&gt;, &lt;0x2360&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c2_pins: i2c2-pins {</div><div class='add'>+		i2c2-grp0 {</div><div class='add'>+			pinmux = &lt;0x151&gt;, &lt;0x161&gt;;</div><div class='add'>+			drive-open-drain;</div><div class='add'>+			output-enable;</div><div class='add'>+			input-enable;</div><div class='add'>+			slew-rate = &lt;133&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c2-grp1 {</div><div class='add'>+			pinmux = &lt;0x2cf2&gt;, &lt;0x2d02&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c2_gpio_pins: i2c2-gpio-pins {</div><div class='add'>+		i2c2-gpio-grp0 {</div><div class='add'>+			pinmux = &lt;0x2cf0&gt;, &lt;0x2d00&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c2-gpio-grp1 {</div><div class='add'>+			pinmux = &lt;0x150&gt;, &lt;0x160&gt;;</div><div class='add'>+			drive-open-drain;</div><div class='add'>+			output-enable;</div><div class='add'>+			input-enable;</div><div class='add'>+			slew-rate = &lt;133&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c4_pins: i2c4-pins {</div><div class='add'>+		i2c4-grp0 {</div><div class='add'>+			pinmux = &lt;0x211&gt;, &lt;0x222&gt;;</div><div class='add'>+			drive-open-drain;</div><div class='add'>+			output-enable;</div><div class='add'>+			input-enable;</div><div class='add'>+			slew-rate = &lt;133&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c4-grp1 {</div><div class='add'>+			pinmux = &lt;0x2d43&gt;, &lt;0x2d33&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c4_gpio_pins: i2c4-gpio-pins {</div><div class='add'>+		i2c4-gpio-grp0 {</div><div class='add'>+			pinmux = &lt;0x210&gt;, &lt;0x220&gt;;</div><div class='add'>+			drive-open-drain;</div><div class='add'>+			output-enable;</div><div class='add'>+			input-enable;</div><div class='add'>+			slew-rate = &lt;133&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c4-gpio-grp1 {</div><div class='add'>+			pinmux = &lt;0x2d40&gt;, &lt;0x2d30&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dspi1_pins: dspi1-pins {</div><div class='add'>+		dspi1-grp0 {</div><div class='add'>+			pinmux = &lt;0x72&gt;;</div><div class='add'>+			output-enable;</div><div class='add'>+			input-enable;</div><div class='add'>+			slew-rate = &lt;150&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dspi1-grp1 {</div><div class='add'>+			pinmux = &lt;0x62&gt;;</div><div class='add'>+			output-enable;</div><div class='add'>+			slew-rate = &lt;150&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dspi1-grp2 {</div><div class='add'>+			pinmux = &lt;0x83&gt;;</div><div class='add'>+			output-enable;</div><div class='add'>+			input-enable;</div><div class='add'>+			slew-rate = &lt;150&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dspi1-grp3 {</div><div class='add'>+			pinmux = &lt;0x5F0&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			slew-rate = &lt;150&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dspi1-grp4 {</div><div class='add'>+			pinmux = &lt;0x3D92&gt;,</div><div class='add'>+				 &lt;0x3DA2&gt;,</div><div class='add'>+				 &lt;0x3DB2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dspi5_pins: dspi5-pins {</div><div class='add'>+		dspi5-grp0 {</div><div class='add'>+			pinmux = &lt;0x93&gt;;</div><div class='add'>+			output-enable;</div><div class='add'>+			input-enable;</div><div class='add'>+			slew-rate = &lt;150&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dspi5-grp1 {</div><div class='add'>+			pinmux = &lt;0xA0&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			slew-rate = &lt;150&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dspi5-grp2 {</div><div class='add'>+			pinmux = &lt;0x3ED2&gt;,</div><div class='add'>+				 &lt;0x3EE2&gt;,</div><div class='add'>+				 &lt;0x3EF2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dspi5-grp3 {</div><div class='add'>+			pinmux = &lt;0xB3&gt;;</div><div class='add'>+			output-enable;</div><div class='add'>+			slew-rate = &lt;150&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dspi5-grp4 {</div><div class='add'>+			pinmux = &lt;0xC3&gt;;</div><div class='add'>+			output-enable;</div><div class='add'>+			input-enable;</div><div class='add'>+			slew-rate = &lt;150&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;can0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;can0_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;can1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;can1_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c0_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;i2c0_gpio_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pcal6524: gpio-expander@22 {</div><div class='add'>+		compatible = "nxp,pcal6524";</div><div class='add'>+		reg = &lt;0x22&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pca85073a: rtc@51 {</div><div class='add'>+		compatible = "nxp,pca85073a";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;dspi1_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi5 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;dspi5_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c2_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;i2c2_gpio_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c4_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;i2c4_gpio_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/s32v234.dtsi b/arch/arm64/boot/dts/freescale/s32v234.dtsi<br/>index ba0b5305d481..bf608ded5dda 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/s32v234.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/freescale/s32v234.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/s32v234.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/s32v234.dtsi</a></div><div class='hunk'>@@ -61,10 +61,14 @@</div><div class='ctx'> </div><div class='ctx'> 		cluster0_l2_cache: l2-cache0 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cluster1_l2_cache: l2-cache1 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -85,7 +89,7 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	gic: interrupt-controller@7d001000 {</div><div class='del'>-		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";</div><div class='add'>+		compatible = "arm,cortex-a15-gic";</div><div class='ctx'> 		#interrupt-cells = &lt;3&gt;;</div><div class='ctx'> 		#address-cells = &lt;0&gt;;</div><div class='ctx'> 		interrupt-controller;</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/tqma8xx.dtsi b/arch/arm64/boot/dts/freescale/tqma8xx.dtsi<br/>new file mode 100644<br/>index 000000000000..58693b774d4c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/tqma8xx.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/tqma8xx.dtsi</a></div><div class='hunk'>@@ -0,0 +1,277 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR X11)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2018-2023 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Alexander Stein</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	memory@80000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x00000000 0x80000000 0 0x40000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_1v8: regulator-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "V_1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3v3: regulator-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "V_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * global autoconfigured region for contiguous allocations</div><div class='add'>+		 * must not exceed memory size and region</div><div class='add'>+		 */</div><div class='add'>+		linux,cma {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reusable;</div><div class='add'>+			size = &lt;0 0x20000000&gt;;</div><div class='add'>+			alloc-ranges = &lt;0 0x96000000 0 0x30000000&gt;;</div><div class='add'>+			linux,cma-default;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* TQMa8Xx only uses industrial grade, reduce trip points accordingly */</div><div class='add'>+&amp;cpu_alert0 {</div><div class='add'>+	temperature = &lt;95000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu_crit0 {</div><div class='add'>+	temperature = &lt;100000&gt;;</div><div class='add'>+};</div><div class='add'>+/* end of temperature grade adjustments */</div><div class='add'>+</div><div class='add'>+&amp;flexspi0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexspi0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash0: flash@0 {</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		spi-max-frequency = &lt;66000000&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;1&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_1v8&gt;;</div><div class='add'>+</div><div class='add'>+		partitions {</div><div class='add'>+			compatible = "fixed-partitions";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_lpi2c1gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;lsio_gpio1 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;lsio_gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	se97: temperature-sensor@1b {</div><div class='add'>+		compatible = "nxp,se97b", "jedec,jc-42.4-temp";</div><div class='add'>+		reg = &lt;0x1b&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcf85063: rtc@51 {</div><div class='add'>+		compatible = "nxp,pcf85063a";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		quartz-load-femtofarads = &lt;7000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	at24c02: eeprom@53 {</div><div class='add'>+		compatible = "nxp,se97b", "atmel,24c02";</div><div class='add'>+		reg = &lt;0x53&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+		read-only;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	m24c64: eeprom@57 {</div><div class='add'>+		compatible = "atmel,24c64";</div><div class='add'>+		reg = &lt;0x57&gt;;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;jpegdec {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;jpegenc {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+&amp;mu_m0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mu1_m0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;thermal_zones {</div><div class='add'>+	pmic_thermal: pmic-thermal {</div><div class='add'>+		polling-delay-passive = &lt;250&gt;;</div><div class='add'>+		polling-delay = &lt;2000&gt;;</div><div class='add'>+		thermal-sensors = &lt;&amp;tsens IMX_SC_R_PMIC_0&gt;;</div><div class='add'>+</div><div class='add'>+		trips {</div><div class='add'>+			pmic_alert0: trip0 {</div><div class='add'>+				temperature = &lt;110000&gt;;</div><div class='add'>+				hysteresis = &lt;2000&gt;;</div><div class='add'>+				type = "passive";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pmic_crit0: trip1 {</div><div class='add'>+				temperature = &lt;125000&gt;;</div><div class='add'>+				hysteresis = &lt;2000&gt;;</div><div class='add'>+				type = "critical";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cooling-maps {</div><div class='add'>+			map0 {</div><div class='add'>+				trip = &lt;&amp;pmic_alert0&gt;;</div><div class='add'>+				cooling-device =</div><div class='add'>+					&lt;&amp;A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+					&lt;&amp;A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+					&lt;&amp;A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+					&lt;&amp;A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1_200mhz&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_1v8&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	no-sdio;</div><div class='add'>+	no-sd;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;vpu {</div><div class='add'>+	compatible = "nxp,imx8qxp-vpu";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;vpu_core0 {</div><div class='add'>+	memory-region = &lt;&amp;decoder_boot&gt;, &lt;&amp;decoder_rpc&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;vpu_core1 {</div><div class='add'>+	memory-region = &lt;&amp;encoder_boot&gt;, &lt;&amp;encoder_rpc&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_flexspi0: flexspi0grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0	0x0600004d</div><div class='add'>+			IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1	0x0600004d</div><div class='add'>+			IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2	0x0600004d</div><div class='add'>+			IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3	0x0600004d</div><div class='add'>+			IMX8QXP_QSPI0A_DQS_LSIO_QSPI0A_DQS	0x0600004d</div><div class='add'>+			IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B	0x0600004d</div><div class='add'>+			IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK	0x0600004d</div><div class='add'>+			IMX8QXP_QSPI0B_SCLK_LSIO_QSPI0B_SCLK	0x0600004d</div><div class='add'>+			IMX8QXP_QSPI0B_DATA0_LSIO_QSPI0B_DATA0	0x0600004d</div><div class='add'>+			IMX8QXP_QSPI0B_DATA1_LSIO_QSPI0B_DATA1	0x0600004d</div><div class='add'>+			IMX8QXP_QSPI0B_DATA2_LSIO_QSPI0B_DATA2	0x0600004d</div><div class='add'>+			IMX8QXP_QSPI0B_DATA3_LSIO_QSPI0B_DATA3	0x0600004d</div><div class='add'>+			IMX8QXP_QSPI0B_DQS_LSIO_QSPI0B_DQS	0x0600004d</div><div class='add'>+			IMX8QXP_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B	0x0600004d</div><div class='add'>+			IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B	0x0600004d</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c1: lpi2c1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QXP_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL	0x06000021</div><div class='add'>+			IMX8QXP_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA	0x06000021</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c1gpio: lpi2c1gpiogrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QXP_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO27	0x06000021</div><div class='add'>+			IMX8QXP_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28	0x06000021</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK	0x06000041</div><div class='add'>+			IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD	0x00000021</div><div class='add'>+			IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021</div><div class='add'>+			IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021</div><div class='add'>+			IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021</div><div class='add'>+			IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021</div><div class='add'>+			IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021</div><div class='add'>+			IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021</div><div class='add'>+			IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021</div><div class='add'>+			IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021</div><div class='add'>+			IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK	0x06000040</div><div class='add'>+			IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD	0x00000020</div><div class='add'>+			IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020</div><div class='add'>+			IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020</div><div class='add'>+			IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020</div><div class='add'>+			IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020</div><div class='add'>+			IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020</div><div class='add'>+			IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020</div><div class='add'>+			IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020</div><div class='add'>+			IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020</div><div class='add'>+			IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000040</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;</div><div class='add'>+			IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK	0x06000040</div><div class='add'>+			IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD	0x00000020</div><div class='add'>+			IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020</div><div class='add'>+			IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020</div><div class='add'>+			IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020</div><div class='add'>+			IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020</div><div class='add'>+			IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020</div><div class='add'>+			IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020</div><div class='add'>+			IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020</div><div class='add'>+			IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020</div><div class='add'>+			IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000040</div><div class='add'>+		&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/tqma8xxs-mb-smarc-2.dtsi b/arch/arm64/boot/dts/freescale/tqma8xxs-mb-smarc-2.dtsi<br/>new file mode 100644<br/>index 000000000000..3d20e3bf32ce<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/tqma8xxs-mb-smarc-2.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/tqma8xxs-mb-smarc-2.dtsi</a></div><div class='hunk'>@@ -0,0 +1,201 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2018-2025 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Alexander Stein</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		rtc0 = &amp;rtc1;</div><div class='add'>+		rtc1 = &amp;rtc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	backlight_lvds0: backlight-lvds0 {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_backlight_lvds0&gt;;</div><div class='add'>+		/* PWM support still missing */</div><div class='add'>+		brightness-levels = &lt;0 4 8 16 32 64 128 255&gt;;</div><div class='add'>+		default-brightness-level = &lt;7&gt;;</div><div class='add'>+		power-supply = &lt;&amp;reg_12v0&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;lsio_gpio1 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	backlight_lvds1: backlight-lvds1 {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_backlight_lvds1&gt;;</div><div class='add'>+		/* PWM support still missing */</div><div class='add'>+		brightness-levels = &lt;0 4 8 16 32 64 128 255&gt;;</div><div class='add'>+		default-brightness-level = &lt;7&gt;;</div><div class='add'>+		power-supply = &lt;&amp;reg_12v0&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;lsio_gpio1 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;lpuart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	panel_lvds0: panel-lvds0 {</div><div class='add'>+		/*</div><div class='add'>+		 * Display is not fixed, so compatible has to be added from</div><div class='add'>+		 * DT</div><div class='add'>+		 */</div><div class='add'>+		backlight = &lt;&amp;backlight_lvds0&gt;;</div><div class='add'>+		power-supply = &lt;&amp;reg_lvds0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			panel_in_lvds0: endpoint {</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	panel_lvds1: panel-lvds1 {</div><div class='add'>+		/*</div><div class='add'>+		 * Display is not fixed, so compatible has to be added from</div><div class='add'>+		 * DT</div><div class='add'>+		 */</div><div class='add'>+		backlight = &lt;&amp;backlight_lvds1&gt;;</div><div class='add'>+		power-supply = &lt;&amp;reg_lvds1&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			panel_in_lvds1: endpoint {</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_1v8: regulator-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3v3: regulator-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_12v0: regulator-12v0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "12V0";</div><div class='add'>+		regulator-min-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "fsl,imx-audio-tlv320aic32x4";</div><div class='add'>+		model = "tqm-tlv320aic32";</div><div class='add'>+		ssi-controller = &lt;&amp;sai1&gt;;</div><div class='add'>+		audio-codec = &lt;&amp;tlv320aic3x04&gt;;</div><div class='add'>+		audio-routing =</div><div class='add'>+			"IN3_L", "Mic Jack",</div><div class='add'>+			"Mic Jack", "Mic Bias",</div><div class='add'>+			"IN1_L", "Line In Jack",</div><div class='add'>+			"IN1_R", "Line In Jack",</div><div class='add'>+			"Line Out Jack", "LOL",</div><div class='add'>+			"Line Out Jack", "LOR";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan2 {</div><div class='add'>+	xceiver-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan3 {</div><div class='add'>+	xceiver-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	tlv320aic3x04: audio-codec@18 {</div><div class='add'>+		compatible = "ti,tlv320aic32x4";</div><div class='add'>+		reg = &lt;0x18&gt;;</div><div class='add'>+		clocks = &lt;&amp;mclkout0_lpcg 0&gt;;</div><div class='add'>+		clock-names = "mclk";</div><div class='add'>+		iov-supply = &lt;&amp;reg_1v8&gt;;</div><div class='add'>+		ldoin-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom2: eeprom@57 {</div><div class='add'>+		compatible = "atmel,24c32";</div><div class='add'>+		reg = &lt;0x57&gt;;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpspi1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;reg_sdvmmc {</div><div class='add'>+	off-on-delay-us = &lt;200000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usbotg1&gt;;</div><div class='add'>+	srp-disable;</div><div class='add'>+	hnp-disable;</div><div class='add'>+	adp-disable;</div><div class='add'>+	power-active-high;</div><div class='add'>+	over-current-active-low;</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbotg3_cdns3 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbphy1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	cd-gpios = &lt;&amp;lsio_gpio4 22 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	wp-gpios = &lt;&amp;lsio_gpio4 21 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_sdvmmc&gt;;</div><div class='add'>+	no-1-8-v;</div><div class='add'>+	no-mmc;</div><div class='add'>+	no-sdio;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/tqma8xxs.dtsi b/arch/arm64/boot/dts/freescale/tqma8xxs.dtsi<br/>new file mode 100644<br/>index 000000000000..2d0a329c2fa5<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/tqma8xxs.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/tqma8xxs.dtsi</a></div><div class='hunk'>@@ -0,0 +1,768 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2018-2025 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Alexander Stein</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/net/ti-dp83867.h&gt;</div><div class='add'>+</div><div class='add'>+/delete-node/ &amp;encoder_rpc;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	memory@80000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		/*</div><div class='add'>+		 * DRAM base addr, minimal size : 1024 MiB DRAM</div><div class='add'>+		 * should be corrected by bootloader</div><div class='add'>+		 */</div><div class='add'>+		reg = &lt;0x00000000 0x80000000 0 0x40000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_xtal25: clk-xtal25 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;25000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_tqma8xxs_3v3: regulator-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_lvds0: regulator-lvds0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_lvds0&gt;;</div><div class='add'>+		regulator-name = "LCD0_VDD_EN";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;lsio_gpio1 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_lvds1: regulator-lvds1 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_lvds1&gt;;</div><div class='add'>+		regulator-name = "LCD1_VDD_EN";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;lsio_gpio1 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_sdvmmc: regulator-sdvmmc {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_sdvmmc&gt;;</div><div class='add'>+		regulator-name = "SD1_VMMC";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;lsio_gpio4 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vmmc: regulator-vmmc {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "MMC0_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vqmmc: regulator-vqmmc {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "MMC0_1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * global autoconfigured region for contiguous allocations</div><div class='add'>+		 * must not exceed memory size and region</div><div class='add'>+		 */</div><div class='add'>+		linux,cma {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reusable;</div><div class='add'>+			size = &lt;0 0x20000000&gt;;</div><div class='add'>+			alloc-ranges = &lt;0 0x96000000 0 0x30000000&gt;;</div><div class='add'>+			linux,cma-default;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		decoder_boot: decoder-boot@84000000 {</div><div class='add'>+			reg = &lt;0 0x84000000 0 0x2000000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		encoder_boot: encoder-boot@86000000 {</div><div class='add'>+			reg = &lt;0 0x86000000 0 0x200000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		m4_reserved: m4@88000000 {</div><div class='add'>+			no-map;</div><div class='add'>+			reg = &lt;0 0x88000000 0 0x8000000&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev0vring0: vdev0vring0@90000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x90000000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev0vring1: vdev0vring1@90008000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x90008000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev1vring0: vdev1vring0@90010000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x90010000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdev1vring1: vdev1vring1@90018000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x90018000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rsc_table: rsc-table@900ff000 {</div><div class='add'>+			reg = &lt;0 0x900ff000 0 0x1000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdevbuffer: vdevbuffer@90400000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x90400000 0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		decoder_rpc: decoder-rpc@92000000 {</div><div class='add'>+			reg = &lt;0 0x92000000 0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		encoder_rpc: encoder-rpc@92100000 {</div><div class='add'>+			reg = &lt;0 0x92100000 0 0x700000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* TQMa8XxS only uses industrial grade, reduce trip points accordingly */</div><div class='add'>+&amp;cpu_alert0 {</div><div class='add'>+	temperature = &lt;95000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu_crit0 {</div><div class='add'>+	temperature = &lt;100000&gt;;</div><div class='add'>+};</div><div class='add'>+/* end of temperature grade adjustments */</div><div class='add'>+</div><div class='add'>+&amp;fec1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec1&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy0&gt;;</div><div class='add'>+	fsl,magic-packet;</div><div class='add'>+	mac-address = [ 00 00 00 00 00 00 ];</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ethphy0: ethernet-phy@0 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_ethphy0&gt;;</div><div class='add'>+			ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_2_50_NS&gt;;</div><div class='add'>+			ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_2_50_NS&gt;;</div><div class='add'>+			ti,fifo-depth = &lt;DP83867_PHYCR_FIFO_DEPTH_4_B_NIB&gt;;</div><div class='add'>+			ti,dp83867-rxctrl-strap-quirk;</div><div class='add'>+			ti,clk-output-sel = &lt;DP83867_CLK_O_SEL_OFF&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;lsio_gpio3 22 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;500000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;50000&gt;;</div><div class='add'>+			enet-phy-lane-no-swap;</div><div class='add'>+			interrupt-parent = &lt;&amp;lsio_gpio1&gt;;</div><div class='add'>+			interrupts = &lt;30 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ethphy3: ethernet-phy@3 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+			reg = &lt;3&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;pinctrl_ethphy1&gt;;</div><div class='add'>+			ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_2_50_NS&gt;;</div><div class='add'>+			ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_2_50_NS&gt;;</div><div class='add'>+			ti,fifo-depth = &lt;DP83867_PHYCR_FIFO_DEPTH_4_B_NIB&gt;;</div><div class='add'>+			ti,dp83867-rxctrl-strap-quirk;</div><div class='add'>+			ti,clk-output-sel = &lt;DP83867_CLK_O_SEL_OFF&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;lsio_gpio0 24 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;500000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;50000&gt;;</div><div class='add'>+			enet-phy-lane-no-swap;</div><div class='add'>+			interrupt-parent = &lt;&amp;lsio_gpio1&gt;;</div><div class='add'>+			interrupts = &lt;14 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fec2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_fec2&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethphy3&gt;;</div><div class='add'>+	fsl,magic-packet;</div><div class='add'>+	mac-address = [ 00 00 00 00 00 00 ];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_can1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexcan3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_can2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;flexspi0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_flexspi0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash0: flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;66000000&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;1&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+		partitions {</div><div class='add'>+			compatible = "fixed-partitions";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_smarc_fangpio&gt;, &lt;&amp;pinctrl_smarc_mngtpio&gt;;</div><div class='add'>+</div><div class='add'>+	gpio-line-names = "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "LID", "SLEEP", "CHARGING#", "CHGPRSNT#",</div><div class='add'>+			  "BATLOW#", "", "", "",</div><div class='add'>+			  "", "SMARC_GPIO6", "SMARC_GPIO5", "",</div><div class='add'>+			  "PHY3 RST#", "", "", "SPI0_CS0",</div><div class='add'>+			  "", "SPI0_CS1", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_smarc_gpio&gt;;</div><div class='add'>+</div><div class='add'>+	gpio-line-names = "LCD1_BLKT_EN", "LCD1_VDD_EN", "LCD0_BLKT_EN", "LCD0_VDD_EN",</div><div class='add'>+			  "SMARC_GPIO0", "SMARC_GPIO1", "SMARC_GPIO2", "",</div><div class='add'>+			  "SMARC_GPIO3", "SMARC_GPIO8", "SMARC_GPIO7", "SMARC_GPIO10",</div><div class='add'>+			  "SMARC_GPIO9", "SMARC_GPIO4", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio2 {</div><div class='add'>+	gpio-line-names = "RTC_INT#", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio3 {</div><div class='add'>+	gpio-line-names = "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "PHY0_RST#", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lsio_gpio4 {</div><div class='add'>+	gpio-line-names = "PCIE_PERST#", "", "PCIE_WAKE#", "USB_OTG1_PWR",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "SDIO_PWR_EN",</div><div class='add'>+			  "", "SDIO_WP", "SDIO_CD#", "",</div><div class='add'>+			  "", "", "", "",</div><div class='add'>+			  "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default", "gpio";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpi2c0&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_lpi2c0_gpio&gt;;</div><div class='add'>+	scl-gpios = &lt;&amp;lsio_gpio3 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;lsio_gpio3 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* NXP SE97BTP with temperature sensor + eeprom */</div><div class='add'>+	sensor0: temperature-sensor@1b {</div><div class='add'>+		compatible = "nxp,se97b", "jedec,jc-42.4-temp";</div><div class='add'>+		reg = &lt;0x1b&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom0: eeprom@50 {</div><div class='add'>+		compatible = "atmel,24c64";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_tqma8xxs_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rtc1: rtc@51 {</div><div class='add'>+		compatible = "nxp,pcf85063a";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_rtc&gt;;</div><div class='add'>+		quartz-load-femtofarads = &lt;7000&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;lsio_gpio2&gt;;</div><div class='add'>+		interrupts = &lt;0 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom1: eeprom@53 {</div><div class='add'>+		compatible = "nxp,se97b", "atmel,24c02";</div><div class='add'>+		reg = &lt;0x53&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+		read-only;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_tqma8xxs_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcieclk: clock-generator@6a {</div><div class='add'>+		compatible = "renesas,9fgv0241";</div><div class='add'>+		reg = &lt;0x6a&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk_xtal25&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpspi1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_spi1&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;lsio_gpio0 27 GPIO_ACTIVE_LOW&gt;, &lt;&amp;lsio_gpio0 29 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpuart0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpuart3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_lpuart3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mu_m0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mu1_m0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sai1 {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS&gt;,</div><div class='add'>+			  &lt;&amp;clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS&gt;,</div><div class='add'>+			  &lt;&amp;sai1_lpcg 0&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;786432000&gt;, &lt;49152000&gt;, &lt;12288000&gt;, &lt;49152000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_sai1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;thermal_zones {</div><div class='add'>+	pmic0_thermal: pmic0-thermal {</div><div class='add'>+		polling-delay-passive = &lt;250&gt;;</div><div class='add'>+		polling-delay = &lt;2000&gt;;</div><div class='add'>+		thermal-sensors = &lt;&amp;tsens IMX_SC_R_PMIC_0&gt;;</div><div class='add'>+</div><div class='add'>+		trips {</div><div class='add'>+			pmic_alert0: trip0 {</div><div class='add'>+				temperature = &lt;110000&gt;;</div><div class='add'>+				hysteresis = &lt;2000&gt;;</div><div class='add'>+				type = "passive";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pmic_crit0: trip1 {</div><div class='add'>+				temperature = &lt;125000&gt;;</div><div class='add'>+				hysteresis = &lt;2000&gt;;</div><div class='add'>+				type = "critical";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cooling-maps {</div><div class='add'>+			map0 {</div><div class='add'>+				trip = &lt;&amp;pmic_alert0&gt;;</div><div class='add'>+				cooling-device =</div><div class='add'>+					&lt;&amp;A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+					&lt;&amp;A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+					&lt;&amp;A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+					&lt;&amp;A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc1 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc1&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc1_100mhz&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc1_200mhz&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_vmmc&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_vqmmc&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	no-sd;</div><div class='add'>+	no-sdio;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usdhc2 {</div><div class='add'>+	pinctrl-names = "default", "state_100mhz", "state_200mhz";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_usdhc2&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_usdhc2_100mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_usdhc2_200mhz&gt;, &lt;&amp;pinctrl_usdhc2_gpio&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	/* NOTE: CD / WP and VMMC support depends on mainboard */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;vpu {</div><div class='add'>+	compatible = "nxp,imx8qxp-vpu";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;vpu_core0 {</div><div class='add'>+	memory-region = &lt;&amp;decoder_boot&gt;, &lt;&amp;decoder_rpc&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;vpu_core1 {</div><div class='add'>+	memory-region = &lt;&amp;encoder_boot&gt;, &lt;&amp;encoder_rpc&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iomuxc {</div><div class='add'>+	pinctrl_backlight_lvds0: backlight-lvds0grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_SPI2_SDI_LSIO_GPIO1_IO02	0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_backlight_lvds1: backlight-lvds1grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00	0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_can1: can1grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_UART2_TX_ADMA_FLEXCAN1_TX	0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QXP_UART2_RX_ADMA_FLEXCAN1_RX	0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_can2: can2grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX	0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX	0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ethphy0: ethphy0grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO30	0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22		0x00000040&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_ethphy1: ethphy1grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_ADC_IN4_LSIO_GPIO1_IO14		0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_UART1_CTS_B_LSIO_GPIO0_IO24		0x00000040&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec1: fec1grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_ENET0_MDC_CONN_ENET0_MDC			0x06000041&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO			0x06000041&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC	0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2	0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3	0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC	0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2	0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3	0x00000040&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_fec2: fec2grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL		0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ESAI0_FSR_CONN_ENET1_RGMII_TXC		0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0		0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1		0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ESAI0_FST_CONN_ENET1_RGMII_TXD2		0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3		0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ESAI0_TX0_CONN_ENET1_RGMII_RXC		0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL		0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0		0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1		0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2		0x00000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_ESAI0_TX1_CONN_ENET1_RGMII_RXD3		0x00000040&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_flexspi0: flexspi0grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0	0x0000004d&gt;,</div><div class='add'>+			   &lt;IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1	0x0000004d&gt;,</div><div class='add'>+			   &lt;IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2	0x0000004d&gt;,</div><div class='add'>+			   &lt;IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3	0x0000004d&gt;,</div><div class='add'>+			   &lt;IMX8QXP_QSPI0A_DQS_LSIO_QSPI0A_DQS		0x0000004d&gt;,</div><div class='add'>+			   &lt;IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B	0x0000004d&gt;,</div><div class='add'>+			   &lt;IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK	0x0000004d&gt;,</div><div class='add'>+			   &lt;IMX8QXP_QSPI0B_SCLK_LSIO_QSPI0B_SCLK	0x0000004d&gt;,</div><div class='add'>+			   &lt;IMX8QXP_QSPI0B_DATA0_LSIO_QSPI0B_DATA0	0x0000004d&gt;,</div><div class='add'>+			   &lt;IMX8QXP_QSPI0B_DATA1_LSIO_QSPI0B_DATA1	0x0000004d&gt;,</div><div class='add'>+			   &lt;IMX8QXP_QSPI0B_DATA2_LSIO_QSPI0B_DATA2	0x0000004d&gt;,</div><div class='add'>+			   &lt;IMX8QXP_QSPI0B_DATA3_LSIO_QSPI0B_DATA3	0x0000004d&gt;,</div><div class='add'>+			   &lt;IMX8QXP_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B	0x0000004d&gt;,</div><div class='add'>+			   &lt;IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B	0x0000004d&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_smarc_gpio: smarcgpiogrp {</div><div class='add'>+		fsl,pins = /* SMARC_GPIO0 / CAM0_PWR# */</div><div class='add'>+			   &lt;IMX8QXP_SPI0_SCK_LSIO_GPIO1_IO04	0x00000021&gt;,</div><div class='add'>+			   /* SMARC_GPIO1 / CAM1_PWR# */</div><div class='add'>+			   &lt;IMX8QXP_SPI0_SDI_LSIO_GPIO1_IO05	0x00000021&gt;,</div><div class='add'>+			   /* SMARC_GPIO2 / CAM0_RST# */</div><div class='add'>+			   &lt;IMX8QXP_SPI0_SDO_LSIO_GPIO1_IO06	0x00000021&gt;,</div><div class='add'>+			   /* SMARC_GPIO3 / CAM1_RST# */</div><div class='add'>+			   &lt;IMX8QXP_SPI0_CS0_LSIO_GPIO1_IO08	0x00000021&gt;,</div><div class='add'>+			   /* SMARC_GPIO4 / HDA_RST# */</div><div class='add'>+			   &lt;IMX8QXP_ADC_IN5_LSIO_GPIO1_IO13	0x00000021&gt;,</div><div class='add'>+			   /* SMARC_GPIO7 */</div><div class='add'>+			   &lt;IMX8QXP_ADC_IN0_LSIO_GPIO1_IO10	0x00000021&gt;,</div><div class='add'>+			   /* SMARC_GPIO8 */</div><div class='add'>+			   &lt;IMX8QXP_ADC_IN1_LSIO_GPIO1_IO09	0x00000021&gt;,</div><div class='add'>+			   /* SMARC_GPIO9 */</div><div class='add'>+			   &lt;IMX8QXP_ADC_IN2_LSIO_GPIO1_IO12	0x00000021&gt;,</div><div class='add'>+			   /* SMARC_GPIO10 */</div><div class='add'>+			   &lt;IMX8QXP_ADC_IN3_LSIO_GPIO1_IO11	0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_smarc_fangpio: smarcfangpiogrp {</div><div class='add'>+		fsl,pins = /* SMARC_GPIO5 */</div><div class='add'>+			   &lt;IMX8QXP_UART1_RX_LSIO_GPIO0_IO22	0x00000021&gt;,</div><div class='add'>+			   /* SMARC_GPIO6 */</div><div class='add'>+			   &lt;IMX8QXP_UART1_TX_LSIO_GPIO0_IO21	0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_smarc_mngtpio: smarcmngtgpiogrp {</div><div class='add'>+		fsl,pins = /* SMARC BATLOW# */</div><div class='add'>+			   &lt;IMX8QXP_SPI3_CS0_LSIO_GPIO0_IO16		0x00000021&gt;,</div><div class='add'>+			   /* SMARC SLEEP */</div><div class='add'>+			   &lt;IMX8QXP_SPI3_SCK_LSIO_GPIO0_IO13		0x00000021&gt;,</div><div class='add'>+			   /* SMARC CHGPRSNT# */</div><div class='add'>+			   &lt;IMX8QXP_SPI3_SDI_LSIO_GPIO0_IO15		0x00000021&gt;,</div><div class='add'>+			   /* SMARC CHARGING# */</div><div class='add'>+			   &lt;IMX8QXP_SPI3_SDO_LSIO_GPIO0_IO14		0x00000021&gt;,</div><div class='add'>+			   /* SMARC LID */</div><div class='add'>+			   &lt;IMX8QXP_SPDIF0_EXT_CLK_LSIO_GPIO0_IO12	0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lvds0: lbdpanel0grp {</div><div class='add'>+		fsl,pins = /* LCD PWR */</div><div class='add'>+			&lt;IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03		0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lvds1: lbdpanel1grp {</div><div class='add'>+		fsl,pins = /* LCD PWR */</div><div class='add'>+			&lt;IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01		0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c0: lpi2c0grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL	0x06000021&gt;,</div><div class='add'>+			   &lt;IMX8QXP_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA	0x06000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpi2c0_gpio: lpi2c0gpiogrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08	0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QXP_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07	0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpuart0: lpuart0grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_UART0_RX_ADMA_UART0_RX		0x06000020&gt;,</div><div class='add'>+			   &lt;IMX8QXP_UART0_TX_ADMA_UART0_TX		0x06000020&gt;,</div><div class='add'>+			   &lt;IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B	0x06000020&gt;,</div><div class='add'>+			   &lt;IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B	0x06000020&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lpuart3: lpuart3grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_SCU_GPIO0_00_ADMA_UART3_RX		0x06000020&gt;,</div><div class='add'>+			   &lt;IMX8QXP_SCU_GPIO0_01_ADMA_UART3_TX		0x06000020&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c0_mipi_lvds0: mipi-lvds0-i2c0grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL	0x06000021&gt;,</div><div class='add'>+			   &lt;IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA	0x06000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_i2c0_gpio_mipi_lvds0: mipi-lvds0-i2c0-gpiogrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO25	0x0000021&gt;,</div><div class='add'>+			   &lt;IMX8QXP_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO26	0x0000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pcieb: pcieagrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00	0x06000041&gt;,</div><div class='add'>+			   &lt;IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01	0x06000041&gt;,</div><div class='add'>+			   &lt;IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02	0x04000041&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm_mipi_lvds0: mipi-lvds0-pwmgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT	0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_pwm_mipi_lvds1: mipi-lvds1-pwmgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT	0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_rtc: rtcgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00		0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1: usdhc1grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD		0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000040&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_100mhz: usdhc1100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc1_200mhz: usdhc1200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sdvmmc: sdvmmcgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19	0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_spi1: spi1grp {</div><div class='add'>+		fsl,pins = /* PD + PDRV Low + INOUT - MEK has 0x0600004c */</div><div class='add'>+			   &lt;IMX8QXP_SAI0_TXC_ADMA_SPI1_SDI		0x06000041&gt;,</div><div class='add'>+			   &lt;IMX8QXP_SAI0_TXD_ADMA_SPI1_SDO		0x06000041&gt;,</div><div class='add'>+			   &lt;IMX8QXP_SAI0_TXFS_ADMA_SPI1_SCK		0x06000041&gt;,</div><div class='add'>+			   &lt;IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27		0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29		0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_sai1: sai1grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_MCLK_OUT0_ADMA_ACM_MCLK_OUT0	0x06000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_SAI1_RXC_ADMA_SAI1_TXC		0x06000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_SAI1_RXFS_ADMA_SAI1_TXFS		0x06000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_FLEXCAN1_RX_ADMA_SAI1_TXD		0x06000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_FLEXCAN1_TX_ADMA_SAI1_RXD		0x06000040&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usbotg1: usbotg1grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_USB_SS3_TC0_CONN_USB_OTG1_PWR	0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QXP_USB_SS3_TC2_CONN_USB_OTG1_OC	0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21		0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22		0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2: usdhc2grp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041&gt;,</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD		0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000021&gt;,</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_100mhz: usdhc2100mhzgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD		0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000020&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_usdhc2_200mhz: usdhc2200mhzgrp {</div><div class='add'>+		fsl,pins = &lt;IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040&gt;,</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD		0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000020&gt;,</div><div class='add'>+			   &lt;IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000020&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/tqmls104xa-mbls10xxa-fman.dtsi b/arch/arm64/boot/dts/freescale/tqmls104xa-mbls10xxa-fman.dtsi<br/>new file mode 100644<br/>index 000000000000..4c38dd541143<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/tqmls104xa-mbls10xxa-fman.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/tqmls104xa-mbls10xxa-fman.dtsi</a></div><div class='hunk'>@@ -0,0 +1,104 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2019,2023 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Gregor Herburger, Timo Herbrecher</div><div class='add'>+ *</div><div class='add'>+ * Device Tree Include file for MBLS10xxA from TQ (FMAN related sections)</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/net/ti-dp83867.h&gt;</div><div class='add'>+</div><div class='add'>+&amp;enet0 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;enet1 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;enet2 {</div><div class='add'>+	phy-handle = &lt;&amp;rgmii_phy1&gt;;</div><div class='add'>+	phy-connection-type = "rgmii";</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;enet3 {</div><div class='add'>+	phy-handle = &lt;&amp;rgmii_phy2&gt;;</div><div class='add'>+	phy-connection-type = "rgmii";</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;enet4 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;enet5 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;enet6 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdio0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	qsgmii2_phy1: ethernet-phy@0 {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+		reg = &lt;0x00&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	qsgmii2_phy2: ethernet-phy@1 {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+		reg = &lt;0x01&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	qsgmii2_phy3: ethernet-phy@2 {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+		reg = &lt;0x02&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	qsgmii2_phy4: ethernet-phy@3 {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+		reg = &lt;0x03&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rgmii_phy2: ethernet-phy@c {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+		reg = &lt;0x0c&gt;;</div><div class='add'>+		ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_1_50_NS&gt;;</div><div class='add'>+		ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_1_50_NS&gt;;</div><div class='add'>+		ti,fifo-depth = &lt;DP83867_PHYCR_FIFO_DEPTH_8_B_NIB&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rgmii_phy1: ethernet-phy@e {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+		reg = &lt;0x0e&gt;;</div><div class='add'>+		ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_1_50_NS&gt;;</div><div class='add'>+		ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_1_50_NS&gt;;</div><div class='add'>+		ti,fifo-depth = &lt;DP83867_PHYCR_FIFO_DEPTH_8_B_NIB&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	qsgmii1_phy1: ethernet-phy@1c {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+		reg = &lt;0x1c&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	qsgmii1_phy2: ethernet-phy@1d {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+		reg = &lt;0x1d&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	qsgmii1_phy3: ethernet-phy@1e {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+		reg = &lt;0x1e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	qsgmii1_phy4: ethernet-phy@1f {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+		reg = &lt;0x1f&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/tqmls1088a-mbls10xxa-mc.dtsi b/arch/arm64/boot/dts/freescale/tqmls1088a-mbls10xxa-mc.dtsi<br/>new file mode 100644<br/>index 000000000000..9d44f488c083<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/tqmls1088a-mbls10xxa-mc.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/tqmls1088a-mbls10xxa-mc.dtsi</a></div><div class='hunk'>@@ -0,0 +1,130 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2018-2023 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Gregor Herburger, Timo Herbrecher</div><div class='add'>+ *</div><div class='add'>+ * Device Tree Include file for MBLS10xxA from TQ (MC related sections)</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/net/ti-dp83867.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac1 {</div><div class='add'>+	pcs-handle = &lt;&amp;pcs1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac2 {</div><div class='add'>+	pcs-handle = &lt;&amp;pcs2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac3 {</div><div class='add'>+	pcs-handle = &lt;&amp;pcs3_0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac4 {</div><div class='add'>+	pcs-handle = &lt;&amp;pcs3_1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac5 {</div><div class='add'>+	pcs-handle = &lt;&amp;pcs3_2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac6 {</div><div class='add'>+	pcs-handle = &lt;&amp;pcs3_3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac7 {</div><div class='add'>+	pcs-handle = &lt;&amp;pcs7_0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac8 {</div><div class='add'>+	pcs-handle = &lt;&amp;pcs7_1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac9 {</div><div class='add'>+	pcs-handle = &lt;&amp;pcs7_2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpmac10 {</div><div class='add'>+	pcs-handle = &lt;&amp;pcs7_3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;emdio1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	qsgmii2_phy1: ethernet-phy@0 {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+		reg = &lt;0x00&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	qsgmii2_phy2: ethernet-phy@1 {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+		reg = &lt;0x01&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	qsgmii2_phy3: ethernet-phy@2 {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+		reg = &lt;0x02&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	qsgmii2_phy4: ethernet-phy@3 {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+		reg = &lt;0x03&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rgmii_phy2: ethernet-phy@c {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+		reg = &lt;0x0c&gt;;</div><div class='add'>+		ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_1_50_NS&gt;;</div><div class='add'>+		ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_1_50_NS&gt;;</div><div class='add'>+		ti,fifo-depth = &lt;DP83867_PHYCR_FIFO_DEPTH_8_B_NIB&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rgmii_phy1: ethernet-phy@e {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+		reg = &lt;0x0e&gt;;</div><div class='add'>+		ti,rx-internal-delay = &lt;DP83867_RGMIIDCTL_1_50_NS&gt;;</div><div class='add'>+		ti,tx-internal-delay = &lt;DP83867_RGMIIDCTL_1_50_NS&gt;;</div><div class='add'>+		ti,fifo-depth = &lt;DP83867_PHYCR_FIFO_DEPTH_8_B_NIB&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	qsgmii1_phy1: ethernet-phy@1c {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+		reg = &lt;0x1c&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	qsgmii1_phy2: ethernet-phy@1d {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+		reg = &lt;0x1d&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	qsgmii1_phy3: ethernet-phy@1e {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+		reg = &lt;0x1e&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	qsgmii1_phy4: ethernet-phy@1f {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+		reg = &lt;0x1f&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcs_mdio7 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/tqmls10xxa-mbls10xxa.dtsi b/arch/arm64/boot/dts/freescale/tqmls10xxa-mbls10xxa.dtsi<br/>new file mode 100644<br/>index 000000000000..444bbf511596<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/tqmls10xxa-mbls10xxa.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/tqmls10xxa-mbls10xxa.dtsi</a></div><div class='hunk'>@@ -0,0 +1,157 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2018-2023 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Gregor Herburger, Timo Herbrecher</div><div class='add'>+ *</div><div class='add'>+ * Device Tree Include file for MBLS10xxA from TQ</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	gpio-keys-polled {</div><div class='add'>+		compatible = "gpio-keys-polled";</div><div class='add'>+		poll-interval = &lt;100&gt;;</div><div class='add'>+		autorepeat;</div><div class='add'>+</div><div class='add'>+		button-0 {</div><div class='add'>+			label = "button0";</div><div class='add'>+			gpios = &lt;&amp;gpioexp3 5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_F1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-1 {</div><div class='add'>+			label = "button1";</div><div class='add'>+			gpios = &lt;&amp;gpioexp3 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_F2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-user {</div><div class='add'>+			gpios = &lt;&amp;gpioexp3 13 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_HEARTBEAT;</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3v3: regulator-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "V_3V3_MB";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp1: sfp1 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;sfp1_i2c&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;gpioexp2 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;gpioexp2 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;gpioexp2 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;gpioexp2 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp2: sfp2 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;sfp2_i2c&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;gpioexp2 10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;gpioexp2 11 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;gpioexp2 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;gpioexp2 9 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;duart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;duart1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;esdhc {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	i2c-mux@70 {</div><div class='add'>+		compatible = "nxp,pca9544";</div><div class='add'>+		reg = &lt;0x70&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+</div><div class='add'>+		i2c@0 {</div><div class='add'>+			reg = &lt;0x0&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			gpioexp1: gpio@20 {</div><div class='add'>+				compatible = "nxp,pca9555";</div><div class='add'>+				reg = &lt;0x20&gt;;</div><div class='add'>+				vcc-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gpioexp2: gpio@21 {</div><div class='add'>+				compatible = "nxp,pca9555";</div><div class='add'>+				reg = &lt;0x21&gt;;</div><div class='add'>+				vcc-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gpioexp3: gpio@22 {</div><div class='add'>+				compatible = "nxp,pca9555";</div><div class='add'>+				reg = &lt;0x22&gt;;</div><div class='add'>+				vcc-supply = &lt;&amp;reg_3v3&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sfp1_i2c: i2c@1 {</div><div class='add'>+			reg = &lt;0x1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sfp2_i2c: i2c@2 {</div><div class='add'>+			reg = &lt;0x2&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@3 {</div><div class='add'>+			reg = &lt;0x3&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sata {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb1 {</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/freescale/tqmls10xxa.dtsi b/arch/arm64/boot/dts/freescale/tqmls10xxa.dtsi<br/>new file mode 100644<br/>index 000000000000..7da1bfd83cca<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/freescale/tqmls10xxa.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/freescale/tqmls10xxa.dtsi</a></div><div class='hunk'>@@ -0,0 +1,66 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2018-2023 TQ-Systems GmbH &lt;linux@ew.tq-group.com&gt;,</div><div class='add'>+ * D-82229 Seefeld, Germany.</div><div class='add'>+ * Author: Gregor Herburger, Timo Herbrecher</div><div class='add'>+ *</div><div class='add'>+ * Device Tree Include file for TQMLs10xxA SoM of TQ</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	reg_vcc1v8: regulator-vcc1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCC1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vcc3v3: regulator-vcc3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VCC3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	temperature-sensor@18 {</div><div class='add'>+		compatible = "nxp,se97b", "jedec,jc-42.4-temp";</div><div class='add'>+		reg = &lt;0x18&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@50 {</div><div class='add'>+		compatible = "nxp,se97b", "atmel,24c02";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		pagesize = &lt;16&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_vcc3v3&gt;;</div><div class='add'>+		read-only;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rtc@51 {</div><div class='add'>+		compatible = "nxp,pcf85063a";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@57 {</div><div class='add'>+		compatible = "atmel,24c64";</div><div class='add'>+		reg = &lt;0x57&gt;;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;reg_vcc3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;esdhc {</div><div class='add'>+	/* eSDHC or eMMC: set by bootloader */</div><div class='add'>+	non-removable;</div><div class='add'>+	disable-wp;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	sd-uhs-sdr104;</div><div class='add'>+	sd-uhs-sdr50;</div><div class='add'>+	sd-uhs-sdr25;</div><div class='add'>+	sd-uhs-sdr12;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi<br/>index d607f2f6698c..4c6a075908d1 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi</a></div><div class='hunk'>@@ -3,7 +3,7 @@</div><div class='ctx'> /*</div><div class='ctx'>  * dtsi for Hisilicon Hi3660 Coresight</div><div class='ctx'>  *</div><div class='del'>- * Copyright (C) 2016-2018 Hisilicon Ltd.</div><div class='add'>+ * Copyright (C) 2016-2018 HiSilicon Ltd.</div><div class='ctx'>  *</div><div class='ctx'>  * Author: Wanglai Shi &lt;shiwanglai@hisilicon.com&gt;</div><div class='ctx'>  *</div><div class='hunk'>@@ -17,6 +17,7 @@</div><div class='ctx'> 			clocks = &lt;&amp;crg_ctrl HI3660_PCLK&gt;;</div><div class='ctx'> 			clock-names = "apb_pclk";</div><div class='ctx'> 			cpu = &lt;&amp;cpu0&gt;;</div><div class='add'>+			arm,coresight-loses-context-with-cpu;</div><div class='ctx'> </div><div class='ctx'> 			out-ports {</div><div class='ctx'> 				port {</div><div class='hunk'>@@ -34,6 +35,7 @@</div><div class='ctx'> 			clocks = &lt;&amp;crg_ctrl HI3660_PCLK&gt;;</div><div class='ctx'> 			clock-names = "apb_pclk";</div><div class='ctx'> 			cpu = &lt;&amp;cpu1&gt;;</div><div class='add'>+			arm,coresight-loses-context-with-cpu;</div><div class='ctx'> </div><div class='ctx'> 			out-ports {</div><div class='ctx'> 				port {</div><div class='hunk'>@@ -51,6 +53,7 @@</div><div class='ctx'> 			clocks = &lt;&amp;crg_ctrl HI3660_PCLK&gt;;</div><div class='ctx'> 			clock-names = "apb_pclk";</div><div class='ctx'> 			cpu = &lt;&amp;cpu2&gt;;</div><div class='add'>+			arm,coresight-loses-context-with-cpu;</div><div class='ctx'> </div><div class='ctx'> 			out-ports {</div><div class='ctx'> 				port {</div><div class='hunk'>@@ -68,6 +71,7 @@</div><div class='ctx'> 			clocks = &lt;&amp;crg_ctrl HI3660_PCLK&gt;;</div><div class='ctx'> 			clock-names = "apb_pclk";</div><div class='ctx'> 			cpu = &lt;&amp;cpu3&gt;;</div><div class='add'>+			arm,coresight-loses-context-with-cpu;</div><div class='ctx'> </div><div class='ctx'> 			out-ports {</div><div class='ctx'> 				port {</div><div class='hunk'>@@ -160,6 +164,7 @@</div><div class='ctx'> 			clocks = &lt;&amp;crg_ctrl HI3660_PCLK&gt;;</div><div class='ctx'> 			clock-names = "apb_pclk";</div><div class='ctx'> 			cpu = &lt;&amp;cpu4&gt;;</div><div class='add'>+			arm,coresight-loses-context-with-cpu;</div><div class='ctx'> </div><div class='ctx'> 			out-ports {</div><div class='ctx'> 				port {</div><div class='hunk'>@@ -177,6 +182,7 @@</div><div class='ctx'> 			clocks = &lt;&amp;crg_ctrl HI3660_PCLK&gt;;</div><div class='ctx'> 			clock-names = "apb_pclk";</div><div class='ctx'> 			cpu = &lt;&amp;cpu5&gt;;</div><div class='add'>+			arm,coresight-loses-context-with-cpu;</div><div class='ctx'> </div><div class='ctx'> 			out-ports {</div><div class='ctx'> 				port {</div><div class='hunk'>@@ -194,6 +200,7 @@</div><div class='ctx'> 			clocks = &lt;&amp;crg_ctrl HI3660_PCLK&gt;;</div><div class='ctx'> 			clock-names = "apb_pclk";</div><div class='ctx'> 			cpu = &lt;&amp;cpu6&gt;;</div><div class='add'>+			arm,coresight-loses-context-with-cpu;</div><div class='ctx'> </div><div class='ctx'> 			out-ports {</div><div class='ctx'> 				port {</div><div class='hunk'>@@ -211,6 +218,7 @@</div><div class='ctx'> 			clocks = &lt;&amp;crg_ctrl HI3660_PCLK&gt;;</div><div class='ctx'> 			clock-names = "apb_pclk";</div><div class='ctx'> 			cpu = &lt;&amp;cpu7&gt;;</div><div class='add'>+			arm,coresight-loses-context-with-cpu;</div><div class='ctx'> </div><div class='ctx'> 			out-ports {</div><div class='ctx'> 				port {</div><div class='head'>diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts<br/>index e035cf195b19..3f13a960f34e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts</a></div><div class='hunk'>@@ -2,7 +2,7 @@</div><div class='ctx'> /*</div><div class='ctx'>  * dts file for Hisilicon HiKey960 Development Board</div><div class='ctx'>  *</div><div class='del'>- * Copyright (C) 2016, Hisilicon Ltd.</div><div class='add'>+ * Copyright (C) 2016, HiSilicon Ltd.</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='hunk'>@@ -13,6 +13,7 @@</div><div class='ctx'> #include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/input/input.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/usb/pd.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	model = "HiKey960";</div><div class='hunk'>@@ -48,9 +49,9 @@</div><div class='ctx'> 		ramoops@32000000 {</div><div class='ctx'> 			compatible = "ramoops";</div><div class='ctx'> 			reg = &lt;0x0 0x32000000 0x0 0x00100000&gt;;</div><div class='del'>-			record-size	= &lt;0x00020000&gt;;</div><div class='del'>-			console-size	= &lt;0x00020000&gt;;</div><div class='del'>-			ftrace-size	= &lt;0x00020000&gt;;</div><div class='add'>+			record-size = &lt;0x00020000&gt;;</div><div class='add'>+			console-size = &lt;0x00020000&gt;;</div><div class='add'>+			ftrace-size = &lt;0x00020000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -62,9 +63,9 @@</div><div class='ctx'> 			compatible = "syscon-reboot-mode";</div><div class='ctx'> 			offset = &lt;0x0&gt;;</div><div class='ctx'> </div><div class='del'>-			mode-normal	= &lt;0x77665501&gt;;</div><div class='del'>-			mode-bootloader	= &lt;0x77665500&gt;;</div><div class='del'>-			mode-recovery	= &lt;0x77665502&gt;;</div><div class='add'>+			mode-normal = &lt;0x77665501&gt;;</div><div class='add'>+			mode-bootloader = &lt;0x77665500&gt;;</div><div class='add'>+			mode-recovery = &lt;0x77665502&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -73,7 +74,7 @@</div><div class='ctx'> 		pinctrl-names = "default";</div><div class='ctx'> 		pinctrl-0 = &lt;&amp;pwr_key_pmx_func &amp;pwr_key_cfg_func&gt;;</div><div class='ctx'> </div><div class='del'>-		power {</div><div class='add'>+		key-power {</div><div class='ctx'> 			wakeup-source;</div><div class='ctx'> 			gpios = &lt;&amp;gpio4 2 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 			label = "GPIO Power";</div><div class='hunk'>@@ -84,28 +85,28 @@</div><div class='ctx'> 	leds {</div><div class='ctx'> 		compatible = "gpio-leds";</div><div class='ctx'> </div><div class='del'>-		user_led1 {</div><div class='add'>+		led-user-1 {</div><div class='ctx'> 			label = "green:user1";</div><div class='ctx'> 			/* gpio_150_user_led1 */</div><div class='ctx'> 			gpios = &lt;&amp;gpio18 6 0&gt;;</div><div class='ctx'> 			linux,default-trigger = "heartbeat";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		user_led2 {</div><div class='add'>+		led-user-2 {</div><div class='ctx'> 			label = "green:user2";</div><div class='ctx'> 			/* gpio_151_user_led2 */</div><div class='ctx'> 			gpios = &lt;&amp;gpio18 7 0&gt;;</div><div class='ctx'> 			linux,default-trigger = "none";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		user_led3 {</div><div class='add'>+		led-user-3 {</div><div class='ctx'> 			label = "green:user3";</div><div class='ctx'> 			/* gpio_189_user_led3 */</div><div class='ctx'> 			gpios = &lt;&amp;gpio23 5 0&gt;;</div><div class='ctx'> 			linux,default-trigger = "mmc0";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		user_led4 {</div><div class='add'>+		led-user-4 {</div><div class='ctx'> 			label = "green:user4";</div><div class='ctx'> 			/* gpio_190_user_led4 */</div><div class='ctx'> 			gpios = &lt;&amp;gpio23 6 0&gt;;</div><div class='hunk'>@@ -113,7 +114,7 @@</div><div class='ctx'> 			linux,default-trigger = "none";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		wlan_active_led {</div><div class='add'>+		led-wlan {</div><div class='ctx'> 			label = "yellow:wlan";</div><div class='ctx'> 			/* gpio_205_wifi_active */</div><div class='ctx'> 			gpios = &lt;&amp;gpio25 5 0&gt;;</div><div class='hunk'>@@ -121,7 +122,7 @@</div><div class='ctx'> 			default-state = "off";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		bt_active_led {</div><div class='add'>+		led-bt {</div><div class='ctx'> 			label = "blue:bt";</div><div class='ctx'> 			gpios = &lt;&amp;gpio25 7 0&gt;;</div><div class='ctx'> 			/* gpio_207_user_led1 */</div><div class='hunk'>@@ -526,10 +527,63 @@</div><div class='ctx'> &amp;i2c1 {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='add'>+	rt1711h: rt1711h@4e {</div><div class='add'>+		compatible = "richtek,rt1711h";</div><div class='add'>+		reg = &lt;0x4e&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio27&gt;;</div><div class='add'>+		interrupts = &lt;3 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;usb_cfg_func&gt;;</div><div class='add'>+</div><div class='add'>+		usb_con: connector {</div><div class='add'>+			compatible = "usb-c-connector";</div><div class='add'>+			label = "USB-C";</div><div class='add'>+			data-role = "dual";</div><div class='add'>+			power-role = "dual";</div><div class='add'>+			try-power-role = "sink";</div><div class='add'>+			source-pdos = &lt;PDO_FIXED(5000, 500, PDO_FIXED_USB_COMM)&gt;;</div><div class='add'>+			sink-pdos = &lt;PDO_FIXED(5000, 500, PDO_FIXED_USB_COMM)</div><div class='add'>+				PDO_VAR(5000, 5000, 1000)&gt;;</div><div class='add'>+			op-sink-microwatt = &lt;10000000&gt;;</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					usb_con_ss: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dwc3_ss&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+		port {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			rt1711h_ep: endpoint@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				remote-endpoint = &lt;&amp;dwc3_role_switch&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	adv7533: adv7533@39 {</div><div class='del'>-		status = "ok";</div><div class='add'>+		status = "okay";</div><div class='ctx'> 		compatible = "adi,adv7533";</div><div class='ctx'> 		reg = &lt;0x39&gt;;</div><div class='add'>+		adi,dsi-lanes = &lt;4&gt;;</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+			port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -602,7 +656,7 @@</div><div class='ctx'> 		     &amp;sdio_cfg_func&gt;;</div><div class='ctx'> 	/* WL_EN */</div><div class='ctx'> 	vmmc-supply = &lt;&amp;wlan_en&gt;;</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> </div><div class='ctx'> 	wlcore: wlcore@2 {</div><div class='ctx'> 		compatible = "ti,wl1837";</div><div class='hunk'>@@ -612,3 +666,32 @@</div><div class='ctx'> 		interrupts = &lt;3 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='add'>+</div><div class='add'>+&amp;dwc3 { /* USB */</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	maximum-speed = "super-speed";</div><div class='add'>+	phy_type = "utmi";</div><div class='add'>+	snps,dis-del-phy-power-chg-quirk;</div><div class='add'>+	snps,lfps_filter_quirk;</div><div class='add'>+	snps,dis_u2_susphy_quirk;</div><div class='add'>+	snps,dis_u3_susphy_quirk;</div><div class='add'>+	snps,tx_de_emphasis_quirk;</div><div class='add'>+	snps,tx_de_emphasis = &lt;1&gt;;</div><div class='add'>+	snps,dis_enblslpm_quirk;</div><div class='add'>+	snps,gctl-reset-quirk;</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	role-switch-default-mode = "host";</div><div class='add'>+	port {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		dwc3_role_switch: endpoint@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			remote-endpoint = &lt;&amp;rt1711h_ep&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dwc3_ss: endpoint@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			remote-endpoint = &lt;&amp;usb_con_ss&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi<br/>index 253cc345f143..957a1b41f19b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/hisilicon/hi3660.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/hisilicon/hi3660.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/hisilicon/hi3660.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/hisilicon/hi3660.dtsi</a></div><div class='hunk'>@@ -2,7 +2,7 @@</div><div class='ctx'> /*</div><div class='ctx'>  * dts file for Hisilicon Hi3660 SoC</div><div class='ctx'>  *</div><div class='del'>- * Copyright (C) 2016, Hisilicon Ltd.</div><div class='add'>+ * Copyright (C) 2016, HiSilicon Ltd.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='hunk'>@@ -203,14 +203,18 @@</div><div class='ctx'> </div><div class='ctx'> 		A53_L2: l2-cache0 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		A73_L2: l2-cache1 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	cluster0_opp: opp_table0 {</div><div class='add'>+	cluster0_opp: opp-table-0 {</div><div class='ctx'> 		compatible = "operating-points-v2";</div><div class='ctx'> 		opp-shared;</div><div class='ctx'> </div><div class='hunk'>@@ -245,7 +249,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	cluster1_opp: opp_table1 {</div><div class='add'>+	cluster1_opp: opp-table-1 {</div><div class='ctx'> 		compatible = "operating-points-v2";</div><div class='ctx'> 		opp-shared;</div><div class='ctx'> </div><div class='hunk'>@@ -479,7 +483,7 @@</div><div class='ctx'> 			reg = &lt;0x0 0xfdf00000 0x0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			dma-names = "rx", "tx";</div><div class='del'>-			dmas =  &lt;&amp;dma0 2 &amp;dma0 3&gt;;</div><div class='add'>+			dmas = &lt;&amp;dma0 2 &amp;dma0 3&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;crg_ctrl HI3660_CLK_GATE_UART1&gt;,</div><div class='ctx'> 				 &lt;&amp;crg_ctrl HI3660_CLK_GATE_UART1&gt;;</div><div class='ctx'> 			clock-names = "uartclk", "apb_pclk";</div><div class='hunk'>@@ -493,7 +497,7 @@</div><div class='ctx'> 			reg = &lt;0x0 0xfdf03000 0x0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			dma-names = "rx", "tx";</div><div class='del'>-			dmas =  &lt;&amp;dma0 4 &amp;dma0 5&gt;;</div><div class='add'>+			dmas = &lt;&amp;dma0 4 &amp;dma0 5&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;crg_ctrl HI3660_CLK_GATE_UART2&gt;,</div><div class='ctx'> 				 &lt;&amp;crg_ctrl HI3660_PCLK&gt;;</div><div class='ctx'> 			clock-names = "uartclk", "apb_pclk";</div><div class='hunk'>@@ -519,7 +523,7 @@</div><div class='ctx'> 			reg = &lt;0x0 0xfdf01000 0x0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			dma-names = "rx", "tx";</div><div class='del'>-			dmas =  &lt;&amp;dma0 6 &amp;dma0 7&gt;;</div><div class='add'>+			dmas = &lt;&amp;dma0 6 &amp;dma0 7&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;crg_ctrl HI3660_CLK_GATE_UART4&gt;,</div><div class='ctx'> 				 &lt;&amp;crg_ctrl HI3660_CLK_GATE_UART4&gt;;</div><div class='ctx'> 			clock-names = "uartclk", "apb_pclk";</div><div class='hunk'>@@ -533,7 +537,7 @@</div><div class='ctx'> 			reg = &lt;0x0 0xfdf05000 0x0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			dma-names = "rx", "tx";</div><div class='del'>-			dmas =  &lt;&amp;dma0 8 &amp;dma0 9&gt;;</div><div class='add'>+			dmas = &lt;&amp;dma0 8 &amp;dma0 9&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;crg_ctrl HI3660_CLK_GATE_UART5&gt;,</div><div class='ctx'> 				 &lt;&amp;crg_ctrl HI3660_CLK_GATE_UART5&gt;;</div><div class='ctx'> 			clock-names = "uartclk", "apb_pclk";</div><div class='hunk'>@@ -971,10 +975,10 @@</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;crg_ctrl HI3660_CLK_GATE_SPI2&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='add'>+			clocks = &lt;&amp;crg_ctrl HI3660_CLK_GATE_SPI2&gt;, &lt;&amp;crg_ctrl HI3660_CLK_GATE_SPI2&gt;;</div><div class='add'>+			clock-names = "sspclk", "apb_pclk";</div><div class='ctx'> 			pinctrl-names = "default";</div><div class='del'>-			pinctrl-0 = &lt;&amp;spi2_pmx_func&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;spi2_pmx_func &amp;spi2_cfg_func&gt;;</div><div class='ctx'> 			num-cs = &lt;1&gt;;</div><div class='ctx'> 			cs-gpios = &lt;&amp;gpio27 2 0&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='hunk'>@@ -986,10 +990,10 @@</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;crg_ctrl HI3660_CLK_GATE_SPI3&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='add'>+			clocks = &lt;&amp;crg_ctrl HI3660_CLK_GATE_SPI3&gt;, &lt;&amp;crg_ctrl HI3660_CLK_GATE_SPI3&gt;;</div><div class='add'>+			clock-names = "sspclk", "apb_pclk";</div><div class='ctx'> 			pinctrl-names = "default";</div><div class='del'>-			pinctrl-0 = &lt;&amp;spi3_pmx_func&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;spi3_pmx_func &amp;spi3_cfg_func&gt;;</div><div class='ctx'> 			num-cs = &lt;1&gt;;</div><div class='ctx'> 			cs-gpios = &lt;&amp;gpio18 5 0&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='hunk'>@@ -1002,7 +1006,7 @@</div><div class='ctx'> 			      &lt;0x0 0xf3f20000 0x0 0x40000&gt;,</div><div class='ctx'> 			      &lt;0x0 0xf5000000 0x0 0x2000&gt;;</div><div class='ctx'> 			reg-names = "dbi", "apb", "phy", "config";</div><div class='del'>-			bus-range = &lt;0x0  0x1&gt;;</div><div class='add'>+			bus-range = &lt;0x0 0xff&gt;;</div><div class='ctx'> 			#address-cells = &lt;3&gt;;</div><div class='ctx'> 			#size-cells = &lt;2&gt;;</div><div class='ctx'> 			device_type = "pci";</div><div class='hunk'>@@ -1045,7 +1049,8 @@</div><div class='ctx'> 			clocks = &lt;&amp;crg_ctrl HI3660_CLK_GATE_UFSIO_REF&gt;,</div><div class='ctx'> 				&lt;&amp;crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG&gt;;</div><div class='ctx'> 			clock-names = "ref_clk", "phy_clk";</div><div class='del'>-			freq-table-hz = &lt;0 0&gt;, &lt;0 0&gt;;</div><div class='add'>+			freq-table-hz = &lt;0 0&gt;,</div><div class='add'>+					&lt;0 0&gt;;</div><div class='ctx'> 			/* offset: 0x84; bit: 12 */</div><div class='ctx'> 			resets = &lt;&amp;crg_rst 0x84 12&gt;;</div><div class='ctx'> 			reset-names = "rst";</div><div class='hunk'>@@ -1086,19 +1091,21 @@</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		watchdog0: watchdog@e8a06000 {</div><div class='del'>-			compatible = "arm,sp805-wdt", "arm,primecell";</div><div class='add'>+			compatible = "arm,sp805", "arm,primecell";</div><div class='ctx'> 			reg = &lt;0x0 0xe8a06000 0x0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;crg_ctrl HI3660_OSC32K&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='add'>+			clocks = &lt;&amp;crg_ctrl HI3660_OSC32K&gt;,</div><div class='add'>+				 &lt;&amp;crg_ctrl HI3660_OSC32K&gt;;</div><div class='add'>+			clock-names = "wdog_clk", "apb_pclk";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		watchdog1: watchdog@e8a07000 {</div><div class='del'>-			compatible = "arm,sp805-wdt", "arm,primecell";</div><div class='add'>+			compatible = "arm,sp805", "arm,primecell";</div><div class='ctx'> 			reg = &lt;0x0 0xe8a07000 0x0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;crg_ctrl HI3660_OSC32K&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='add'>+			clocks = &lt;&amp;crg_ctrl HI3660_OSC32K&gt;,</div><div class='add'>+				 &lt;&amp;crg_ctrl HI3660_OSC32K&gt;;</div><div class='add'>+			clock-names = "wdog_clk", "apb_pclk";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		tsensor: tsensor@fff30000 {</div><div class='hunk'>@@ -1110,7 +1117,7 @@</div><div class='ctx'> </div><div class='ctx'> 		thermal-zones {</div><div class='ctx'> </div><div class='del'>-			cls0: cls0 {</div><div class='add'>+			cls0: cls0-thermal {</div><div class='ctx'> 				polling-delay = &lt;1000&gt;;</div><div class='ctx'> 				polling-delay-passive = &lt;100&gt;;</div><div class='ctx'> 				sustainable-power = &lt;4500&gt;;</div><div class='hunk'>@@ -1119,13 +1126,13 @@</div><div class='ctx'> 				thermal-sensors = &lt;&amp;tsensor 1&gt;;</div><div class='ctx'> </div><div class='ctx'> 				trips {</div><div class='del'>-					threshold: trip-point@0 {</div><div class='add'>+					threshold: trip-point0 {</div><div class='ctx'> 						temperature = &lt;65000&gt;;</div><div class='ctx'> 						hysteresis = &lt;1000&gt;;</div><div class='ctx'> 						type = "passive";</div><div class='ctx'> 					};</div><div class='ctx'> </div><div class='del'>-					target: trip-point@1 {</div><div class='add'>+					target: trip-point1 {</div><div class='ctx'> 						temperature = &lt;75000&gt;;</div><div class='ctx'> 						hysteresis = &lt;1000&gt;;</div><div class='ctx'> 						type = "passive";</div><div class='hunk'>@@ -1152,6 +1159,40 @@</div><div class='ctx'> 				};</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='add'>+</div><div class='add'>+		usb3_otg_bc: usb3_otg_bc@ff200000 {</div><div class='add'>+			compatible = "hisilicon,hi3660-usb3-otg-bc", "syscon", "simple-mfd";</div><div class='add'>+			reg = &lt;0x0 0xff200000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			usb_phy: usb-phy {</div><div class='add'>+				compatible = "hisilicon,hi3660-usb-phy";</div><div class='add'>+				#phy-cells = &lt;0&gt;;</div><div class='add'>+				hisilicon,pericrg-syscon = &lt;&amp;crg_ctrl&gt;;</div><div class='add'>+				hisilicon,pctrl-syscon = &lt;&amp;pctrl&gt;;</div><div class='add'>+				hisilicon,eye-diagram-param = &lt;0x22466e4&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dwc3: usb@ff100000 {</div><div class='add'>+			compatible = "snps,dwc3";</div><div class='add'>+			reg = &lt;0x0 0xff100000 0x0 0x100000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;crg_ctrl HI3660_CLK_ABB_USB&gt;,</div><div class='add'>+				 &lt;&amp;crg_ctrl HI3660_ACLK_GATE_USB3OTG&gt;;</div><div class='add'>+			clock-names = "ref", "bus_early";</div><div class='add'>+</div><div class='add'>+			assigned-clocks = &lt;&amp;crg_ctrl HI3660_ACLK_GATE_USB3OTG&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;229000000&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;crg_rst 0x90 8&gt;,</div><div class='add'>+				 &lt;&amp;crg_rst 0x90 7&gt;,</div><div class='add'>+				 &lt;&amp;crg_rst 0x90 6&gt;,</div><div class='add'>+				 &lt;&amp;crg_rst 0x90 5&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;0 159 4&gt;, &lt;0 161 4&gt;;</div><div class='add'>+			phys = &lt;&amp;usb_phy&gt;;</div><div class='add'>+			phy-names = "usb3-phy";</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts b/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts<br/>index 7dac33d4fd5c..7c32f5fd5cc5 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts</a></div><div class='hunk'>@@ -2,7 +2,7 @@</div><div class='ctx'> /*</div><div class='ctx'>  * dts file for Hisilicon HiKey970 Development Board</div><div class='ctx'>  *</div><div class='del'>- * Copyright (C) 2016, Hisilicon Ltd.</div><div class='add'>+ * Copyright (C) 2016, HiSilicon Ltd.</div><div class='ctx'>  * Copyright (C) 2018, Linaro Ltd.</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='hunk'>@@ -12,6 +12,7 @@</div><div class='ctx'> </div><div class='ctx'> #include "hi3670.dtsi"</div><div class='ctx'> #include "hikey970-pinctrl.dtsi"</div><div class='add'>+#include "hikey970-pmic.dtsi"</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	model = "HiKey970";</div><div class='hunk'>@@ -39,23 +40,6 @@</div><div class='ctx'> 		reg = &lt;0x0 0x0 0x0 0x0&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sd_1v8: regulator-1v8 {</div><div class='del'>-		compatible = "regulator-fixed";</div><div class='del'>-		regulator-name = "fixed-1.8V";</div><div class='del'>-		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='del'>-		regulator-always-on;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	sd_3v3: regulator-3v3 {</div><div class='del'>-		compatible = "regulator-fixed";</div><div class='del'>-		regulator-name = "fixed-3.3V";</div><div class='del'>-		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='del'>-		regulator-boot-on;</div><div class='del'>-		regulator-always-on;</div><div class='del'>-	};</div><div class='del'>-</div><div class='ctx'> 	wlan_en: wlan-en-1-8v {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "wlan-en-regulator";</div><div class='hunk'>@@ -402,8 +386,8 @@</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;sd_pmx_func</div><div class='ctx'> 		     &amp;sd_clk_cfg_func</div><div class='ctx'> 		     &amp;sd_cfg_func&gt;;</div><div class='del'>-	vmmc-supply = &lt;&amp;sd_3v3&gt;;</div><div class='del'>-	vqmmc-supply = &lt;&amp;sd_1v8&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;ldo16&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;ldo9&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -418,7 +402,7 @@</div><div class='ctx'> 		     &amp;sdio_cfg_func&gt;;</div><div class='ctx'> 	/* WL_EN */</div><div class='ctx'> 	vmmc-supply = &lt;&amp;wlan_en&gt;;</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> </div><div class='ctx'> 	wlcore: wlcore@2 {</div><div class='ctx'> 		compatible = "ti,wl1837";</div><div class='head'>diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi<br/>index 2dcffa3ed218..886b93c5893a 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/hisilicon/hi3670.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/hisilicon/hi3670.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/hisilicon/hi3670.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/hisilicon/hi3670.dtsi</a></div><div class='hunk'>@@ -2,7 +2,7 @@</div><div class='ctx'> /*</div><div class='ctx'>  * dts file for Hisilicon Hi3670 SoC</div><div class='ctx'>  *</div><div class='del'>- * Copyright (C) 2016, Hisilicon Ltd.</div><div class='add'>+ * Copyright (C) 2016, HiSilicon Ltd.</div><div class='ctx'>  * Copyright (C) 2018, Linaro Ltd.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='hunk'>@@ -194,6 +194,12 @@</div><div class='ctx'> 			#clock-cells = &lt;1&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		iomcu_rst: reset {</div><div class='add'>+			compatible = "hisilicon,hi3660-reset";</div><div class='add'>+			hisi,rst-syscon = &lt;&amp;iomcu&gt;;</div><div class='add'>+			#reset-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		uart0: serial@fdf02000 {</div><div class='ctx'> 			compatible = "arm,pl011", "arm,primecell";</div><div class='ctx'> 			reg = &lt;0x0 0xfdf02000 0x0 0x1000&gt;;</div><div class='hunk'>@@ -213,7 +219,6 @@</div><div class='ctx'> 			clocks = &lt;&amp;crg_ctrl HI3670_CLK_GATE_UART1&gt;,</div><div class='ctx'> 				 &lt;&amp;crg_ctrl HI3670_PCLK&gt;;</div><div class='ctx'> 			clock-names = "uartclk", "apb_pclk";</div><div class='del'>-			pinctrl-names = "default";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -260,7 +265,6 @@</div><div class='ctx'> 			clocks = &lt;&amp;crg_ctrl HI3670_CLK_GATE_UART5&gt;,</div><div class='ctx'> 				 &lt;&amp;crg_ctrl HI3670_PCLK&gt;;</div><div class='ctx'> 			clock-names = "uartclk", "apb_pclk";</div><div class='del'>-			pinctrl-names = "default";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -320,7 +324,7 @@</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			gpio-controller;</div><div class='ctx'> 			#gpio-cells = &lt;2&gt;;</div><div class='del'>-			gpio-ranges =  &lt;&amp;pmx0 0 13 4 &amp;pmx0 7 17 1&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;pmx0 0 13 4 &amp;pmx0 7 17 1&gt;;</div><div class='ctx'> 			interrupt-controller;</div><div class='ctx'> 			#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;crg_ctrl HI3670_PCLK_GPIO3&gt;;</div><div class='hunk'>@@ -665,9 +669,10 @@</div><div class='ctx'> 			interrupt-parent = &lt;&amp;gic&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;crg_ctrl HI3670_CLK_GATE_UFSIO_REF&gt;,</div><div class='del'>-				&lt;&amp;crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS&gt;;</div><div class='add'>+				 &lt;&amp;crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS&gt;;</div><div class='ctx'> 			clock-names = "ref_clk", "phy_clk";</div><div class='del'>-			freq-table-hz = &lt;0 0&gt;, &lt;0 0&gt;;</div><div class='add'>+			freq-table-hz = &lt;0 0&gt;,</div><div class='add'>+					&lt;0 0&gt;;</div><div class='ctx'> 			/* offset: 0x84; bit: 12 */</div><div class='ctx'> 			resets = &lt;&amp;crg_rst 0x84 12&gt;;</div><div class='ctx'> 			reset-names = "rst";</div><div class='hunk'>@@ -709,5 +714,76 @@</div><div class='ctx'> 			card-detect-delay = &lt;200&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='add'>+</div><div class='add'>+		/* I2C */</div><div class='add'>+		i2c0: i2c@ffd71000 {</div><div class='add'>+			compatible = "snps,designware-i2c";</div><div class='add'>+			reg = &lt;0x0 0xffd71000 0x0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			clock-frequency = &lt;400000&gt;;</div><div class='add'>+			clocks = &lt;&amp;iomcu HI3670_CLK_GATE_I2C0&gt;;</div><div class='add'>+			resets = &lt;&amp;iomcu_rst 0x20 3&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c0_pmx_func &amp;i2c0_cfg_func&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c1: i2c@ffd72000 {</div><div class='add'>+			compatible = "snps,designware-i2c";</div><div class='add'>+			reg = &lt;0x0 0xffd72000 0x0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			clock-frequency = &lt;400000&gt;;</div><div class='add'>+			clocks = &lt;&amp;iomcu HI3670_CLK_GATE_I2C1&gt;;</div><div class='add'>+			resets = &lt;&amp;iomcu_rst 0x20 4&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c1_pmx_func &amp;i2c1_cfg_func&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c2: i2c@ffd73000 {</div><div class='add'>+			compatible = "snps,designware-i2c";</div><div class='add'>+			reg = &lt;0x0 0xffd73000 0x0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			clock-frequency = &lt;400000&gt;;</div><div class='add'>+			clocks = &lt;&amp;iomcu HI3670_CLK_GATE_I2C2&gt;;</div><div class='add'>+			resets = &lt;&amp;iomcu_rst 0x20 5&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c2_pmx_func &amp;i2c2_cfg_func&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c3: i2c@fdf0c000 {</div><div class='add'>+			compatible = "snps,designware-i2c";</div><div class='add'>+			reg = &lt;0x0 0xfdf0c000 0x0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			clock-frequency = &lt;400000&gt;;</div><div class='add'>+			clocks = &lt;&amp;crg_ctrl HI3670_CLK_GATE_I2C3&gt;;</div><div class='add'>+			resets = &lt;&amp;crg_rst 0x78 7&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c3_pmx_func &amp;i2c3_cfg_func&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c4: i2c@fdf0d000 {</div><div class='add'>+			compatible = "snps,designware-i2c";</div><div class='add'>+			reg = &lt;0x0 0xfdf0d000 0x0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			clock-frequency = &lt;400000&gt;;</div><div class='add'>+			clocks = &lt;&amp;crg_ctrl HI3670_CLK_GATE_I2C4&gt;;</div><div class='add'>+			resets = &lt;&amp;crg_rst 0x78 27&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c4_pmx_func &amp;i2c4_cfg_func&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi<br/>index 12bc1d3ed424..f6bc001c3832 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi</a></div><div class='hunk'>@@ -31,6 +31,13 @@</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			reg = &lt;0x0 0x0&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;; /* 32 KiB */</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;; /* 32 KiB */</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;L2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu@1 {</div><div class='hunk'>@@ -38,6 +45,13 @@</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			reg = &lt;0x0 0x1&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;; /* 32 KiB */</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;; /* 32 KiB */</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;L2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu@2 {</div><div class='hunk'>@@ -45,6 +59,13 @@</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			reg = &lt;0x0 0x2&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;; /* 32 KiB */</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;; /* 32 KiB */</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;L2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu@3 {</div><div class='hunk'>@@ -52,13 +73,33 @@</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			reg = &lt;0x0 0x3&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;; /* 32 KiB */</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;; /* 32 KiB */</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;L2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	L2: l2-cache {</div><div class='add'>+		compatible = "cache";</div><div class='add'>+		cache-unified;</div><div class='add'>+		cache-size = &lt;0x80000&gt;; /* 512 KiB */</div><div class='add'>+		cache-line-size = &lt;64&gt;;</div><div class='add'>+		cache-sets = &lt;512&gt;;</div><div class='add'>+		cache-level = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	gic: interrupt-controller@f1001000 {</div><div class='ctx'> 		compatible = "arm,gic-400";</div><div class='ctx'> 		reg = &lt;0x0 0xf1001000 0x0 0x1000&gt;,  /* GICD */</div><div class='del'>-		      &lt;0x0 0xf1002000 0x0 0x100&gt;;   /* GICC */</div><div class='add'>+		      &lt;0x0 0xf1002000 0x0 0x2000&gt;,  /* GICC */</div><div class='add'>+		      &lt;0x0 0xf1004000 0x0 0x2000&gt;,  /* GICH */</div><div class='add'>+		      &lt;0x0 0xf1006000 0x0 0x2000&gt;;  /* GICV */</div><div class='add'>+		interrupts = &lt;GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |</div><div class='add'>+			      IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='ctx'> 		#address-cells = &lt;0&gt;;</div><div class='ctx'> 		#interrupt-cells = &lt;3&gt;;</div><div class='ctx'> 		interrupt-controller;</div><div class='hunk'>@@ -91,11 +132,10 @@</div><div class='ctx'> 			gmacphyrst: reset-controller {</div><div class='ctx'> 				compatible = "ti,syscon-reset";</div><div class='ctx'> 				#reset-cells = &lt;1&gt;;</div><div class='del'>-				ti,reset-bits =</div><div class='del'>-					&lt;0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR |</div><div class='del'>-					 DEASSERT_SET|STATUS_NONE)&gt;,</div><div class='del'>-					&lt;0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR |</div><div class='del'>-					 DEASSERT_SET|STATUS_NONE)&gt;;</div><div class='add'>+				ti,reset-bits = &lt;</div><div class='add'>+					0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR | DEASSERT_SET | STATUS_NONE)</div><div class='add'>+					0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR | DEASSERT_SET | STATUS_NONE)</div><div class='add'>+				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -114,7 +154,7 @@</div><div class='ctx'> 			#size-cells = &lt;1&gt;;</div><div class='ctx'> 			ranges = &lt;0x0 0x8a20000 0x1000&gt;;</div><div class='ctx'> </div><div class='del'>-			usb2_phy1: usb2-phy@120 {</div><div class='add'>+			usb2_phy1: usb2_phy@120 {</div><div class='ctx'> 				compatible = "hisilicon,hi3798cv200-usb2-phy";</div><div class='ctx'> 				reg = &lt;0x120 0x4&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;crg HISTB_USB2_PHY1_REF_CLK&gt;;</div><div class='hunk'>@@ -135,7 +175,7 @@</div><div class='ctx'> 				};</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			usb2_phy2: usb2-phy@124 {</div><div class='add'>+			usb2_phy2: usb2_phy@124 {</div><div class='ctx'> 				compatible = "hisilicon,hi3798cv200-usb2-phy";</div><div class='ctx'> 				reg = &lt;0x124 0x4&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;crg HISTB_USB2_PHY2_REF_CLK&gt;;</div><div class='hunk'>@@ -217,8 +257,8 @@</div><div class='ctx'> 			compatible = "arm,pl011", "arm,primecell";</div><div class='ctx'> 			reg = &lt;0x8b00000 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;sysctrl HISTB_UART0_CLK&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='add'>+			clocks = &lt;&amp;sysctrl HISTB_UART0_CLK&gt;, &lt;&amp;sysctrl HISTB_UART0_CLK&gt;;</div><div class='add'>+			clock-names = "uartclk", "apb_pclk";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -226,8 +266,8 @@</div><div class='ctx'> 			compatible = "arm,pl011", "arm,primecell";</div><div class='ctx'> 			reg = &lt;0x8b02000 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;crg HISTB_UART2_CLK&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='add'>+			clocks = &lt;&amp;crg HISTB_UART2_CLK&gt;, &lt;&amp;crg HISTB_UART2_CLK&gt;;</div><div class='add'>+			clock-names = "uartclk", "apb_pclk";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -292,8 +332,8 @@</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			num-cs = &lt;1&gt;;</div><div class='ctx'> 			cs-gpios = &lt;&amp;gpio7 1 0&gt;;</div><div class='del'>-			clocks = &lt;&amp;crg HISTB_SPI0_CLK&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='add'>+			clocks = &lt;&amp;crg HISTB_SPI0_CLK&gt;, &lt;&amp;crg HISTB_SPI0_CLK&gt;;</div><div class='add'>+			clock-names = "sspclk", "apb_pclk";</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='hunk'>@@ -303,9 +343,9 @@</div><div class='ctx'> 			compatible = "snps,dw-mshc";</div><div class='ctx'> 			reg = &lt;0x9820000 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;crg HISTB_SDIO0_CIU_CLK&gt;,</div><div class='del'>-				 &lt;&amp;crg HISTB_SDIO0_BIU_CLK&gt;;</div><div class='del'>-			clock-names = "ciu", "biu";</div><div class='add'>+			clocks = &lt;&amp;crg HISTB_SDIO0_BIU_CLK&gt;,</div><div class='add'>+				 &lt;&amp;crg HISTB_SDIO0_CIU_CLK&gt;;</div><div class='add'>+			clock-names = "biu", "ciu";</div><div class='ctx'> 			resets = &lt;&amp;crg 0x9c 4&gt;;</div><div class='ctx'> 			reset-names = "reset";</div><div class='ctx'> 			status = "disabled";</div><div class='hunk'>@@ -566,8 +606,8 @@</div><div class='ctx'> 			device_type = "pci";</div><div class='ctx'> 			bus-range = &lt;0x00 0xff&gt;;</div><div class='ctx'> 			num-lanes = &lt;1&gt;;</div><div class='del'>-			ranges = &lt;0x81000000 0x0 0x00000000 0x4f00000 0x0 0x100000</div><div class='del'>-				  0x82000000 0x0 0x3000000 0x3000000 0x0 0x01f00000&gt;;</div><div class='add'>+			ranges = &lt;0x81000000 0x0 0x00000000 0x4f00000 0x0 0x100000&gt;,</div><div class='add'>+				 &lt;0x82000000 0x0 0x3000000 0x3000000 0x0 0x01f00000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			interrupt-names = "msi";</div><div class='ctx'> 			#interrupt-cells = &lt;1&gt;;</div><div class='hunk'>@@ -585,7 +625,7 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		ohci: ohci@9880000 {</div><div class='add'>+		ohci: usb@9880000 {</div><div class='ctx'> 			compatible = "generic-ohci";</div><div class='ctx'> 			reg = &lt;0x9880000 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='hunk'>@@ -600,7 +640,7 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		ehci: ehci@9890000 {</div><div class='add'>+		ehci: usb@9890000 {</div><div class='ctx'> 			compatible = "generic-ehci";</div><div class='ctx'> 			reg = &lt;0x9890000 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='head'>diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi<br/>index 651771a73ed6..3f387f4cf5e0 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi</a></div><div class='hunk'>@@ -2,7 +2,7 @@</div><div class='ctx'> /*</div><div class='ctx'>  * dtsi file for Hisilicon Hi6220 coresight</div><div class='ctx'>  *</div><div class='del'>- * Copyright (C) 2017 Hisilicon Ltd.</div><div class='add'>+ * Copyright (C) 2017 HiSilicon Ltd.</div><div class='ctx'>  *</div><div class='ctx'>  * Author: Pengcheng Li &lt;lipengcheng8@huawei.com&gt;</div><div class='ctx'>  *         Leo Yan &lt;leo.yan@linaro.org&gt;</div><div class='hunk'>@@ -213,7 +213,7 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		etm@f659c000 {</div><div class='add'>+		etm0: etm@f659c000 {</div><div class='ctx'> 			compatible = "arm,coresight-etm4x", "arm,primecell";</div><div class='ctx'> 			reg = &lt;0 0xf659c000 0 0x1000&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -232,7 +232,7 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		etm@f659d000 {</div><div class='add'>+		etm1: etm@f659d000 {</div><div class='ctx'> 			compatible = "arm,coresight-etm4x", "arm,primecell";</div><div class='ctx'> 			reg = &lt;0 0xf659d000 0 0x1000&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -251,7 +251,7 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		etm@f659e000 {</div><div class='add'>+		etm2: etm@f659e000 {</div><div class='ctx'> 			compatible = "arm,coresight-etm4x", "arm,primecell";</div><div class='ctx'> 			reg = &lt;0 0xf659e000 0 0x1000&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -270,7 +270,7 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		etm@f659f000 {</div><div class='add'>+		etm3: etm@f659f000 {</div><div class='ctx'> 			compatible = "arm,coresight-etm4x", "arm,primecell";</div><div class='ctx'> 			reg = &lt;0 0xf659f000 0 0x1000&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -289,7 +289,7 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		etm@f65dc000 {</div><div class='add'>+		etm4: etm@f65dc000 {</div><div class='ctx'> 			compatible = "arm,coresight-etm4x", "arm,primecell";</div><div class='ctx'> 			reg = &lt;0 0xf65dc000 0 0x1000&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -308,7 +308,7 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		etm@f65dd000 {</div><div class='add'>+		etm5: etm@f65dd000 {</div><div class='ctx'> 			compatible = "arm,coresight-etm4x", "arm,primecell";</div><div class='ctx'> 			reg = &lt;0 0xf65dd000 0 0x1000&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -327,7 +327,7 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		etm@f65de000 {</div><div class='add'>+		etm6: etm@f65de000 {</div><div class='ctx'> 			compatible = "arm,coresight-etm4x", "arm,primecell";</div><div class='ctx'> 			reg = &lt;0 0xf65de000 0 0x1000&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -346,7 +346,7 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		etm@f65df000 {</div><div class='add'>+		etm7: etm@f65df000 {</div><div class='ctx'> 			compatible = "arm,coresight-etm4x", "arm,primecell";</div><div class='ctx'> 			reg = &lt;0 0xf65df000 0 0x1000&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -364,5 +364,119 @@</div><div class='ctx'> 				};</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='add'>+</div><div class='add'>+		/* System CTIs */</div><div class='add'>+		/* CTI 0 - TMC and TPIU connections */</div><div class='add'>+		cti@f6403000 {</div><div class='add'>+			compatible = "arm,coresight-cti", "arm,primecell";</div><div class='add'>+			reg = &lt;0 0xf6403000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;acpu_sctrl HI6220_ACPU_SFT_AT_S&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* CTI - CPU-0 */</div><div class='add'>+		cti@f6598000 {</div><div class='add'>+			compatible = "arm,coresight-cti-v8-arch",</div><div class='add'>+				     "arm,coresight-cti", "arm,primecell";</div><div class='add'>+			reg = &lt;0 0xf6598000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;acpu_sctrl HI6220_ACPU_SFT_AT_S&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			cpu = &lt;&amp;cpu0&gt;;</div><div class='add'>+			arm,cs-dev-assoc = &lt;&amp;etm0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* CTI - CPU-1 */</div><div class='add'>+		cti@f6599000 {</div><div class='add'>+			compatible = "arm,coresight-cti-v8-arch",</div><div class='add'>+				     "arm,coresight-cti", "arm,primecell";</div><div class='add'>+			reg = &lt;0 0xf6599000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;acpu_sctrl HI6220_ACPU_SFT_AT_S&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			cpu = &lt;&amp;cpu1&gt;;</div><div class='add'>+			arm,cs-dev-assoc = &lt;&amp;etm1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* CTI - CPU-2 */</div><div class='add'>+		cti@f659a000 {</div><div class='add'>+			compatible = "arm,coresight-cti-v8-arch",</div><div class='add'>+				     "arm,coresight-cti", "arm,primecell";</div><div class='add'>+			reg = &lt;0 0xf659a000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;acpu_sctrl HI6220_ACPU_SFT_AT_S&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			cpu = &lt;&amp;cpu2&gt;;</div><div class='add'>+			arm,cs-dev-assoc = &lt;&amp;etm2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* CTI - CPU-3 */</div><div class='add'>+		cti@f659b000 {</div><div class='add'>+			compatible = "arm,coresight-cti-v8-arch",</div><div class='add'>+				     "arm,coresight-cti", "arm,primecell";</div><div class='add'>+			reg = &lt;0 0xf659b000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;acpu_sctrl HI6220_ACPU_SFT_AT_S&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			cpu = &lt;&amp;cpu3&gt;;</div><div class='add'>+			arm,cs-dev-assoc = &lt;&amp;etm3&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* CTI - CPU-4 */</div><div class='add'>+		cti@f65d8000 {</div><div class='add'>+			compatible = "arm,coresight-cti-v8-arch",</div><div class='add'>+				     "arm,coresight-cti", "arm,primecell";</div><div class='add'>+			reg = &lt;0 0xf65d8000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;acpu_sctrl HI6220_ACPU_SFT_AT_S&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			cpu = &lt;&amp;cpu4&gt;;</div><div class='add'>+			arm,cs-dev-assoc = &lt;&amp;etm4&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* CTI - CPU-5 */</div><div class='add'>+		cti@f65d9000 {</div><div class='add'>+			compatible = "arm,coresight-cti-v8-arch",</div><div class='add'>+				     "arm,coresight-cti", "arm,primecell";</div><div class='add'>+			reg = &lt;0 0xf65d9000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;acpu_sctrl HI6220_ACPU_SFT_AT_S&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			cpu = &lt;&amp;cpu5&gt;;</div><div class='add'>+			arm,cs-dev-assoc = &lt;&amp;etm5&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* CTI - CPU-6 */</div><div class='add'>+		cti@f65da000 {</div><div class='add'>+			compatible = "arm,coresight-cti-v8-arch",</div><div class='add'>+				     "arm,coresight-cti", "arm,primecell";</div><div class='add'>+			reg = &lt;0 0xf65da000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;acpu_sctrl HI6220_ACPU_SFT_AT_S&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			cpu = &lt;&amp;cpu6&gt;;</div><div class='add'>+			arm,cs-dev-assoc = &lt;&amp;etm6&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* CTI - CPU-7 */</div><div class='add'>+		cti@f65db000 {</div><div class='add'>+			compatible = "arm,coresight-cti-v8-arch",</div><div class='add'>+				     "arm,coresight-cti", "arm,primecell";</div><div class='add'>+			reg = &lt;0 0xf65db000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;acpu_sctrl HI6220_ACPU_SFT_AT_S&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			cpu = &lt;&amp;cpu7&gt;;</div><div class='add'>+			arm,cs-dev-assoc = &lt;&amp;etm7&gt;;</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts<br/>index c14205cd6bf5..2d304efe081d 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts</a></div><div class='hunk'>@@ -2,7 +2,7 @@</div><div class='ctx'> /*</div><div class='ctx'>  * dts file for Hisilicon HiKey Development Board</div><div class='ctx'>  *</div><div class='del'>- * Copyright (C) 2015, Hisilicon Ltd.</div><div class='add'>+ * Copyright (C) 2015, HiSilicon Ltd.</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='hunk'>@@ -54,9 +54,9 @@</div><div class='ctx'> 		ramoops@21f00000 {</div><div class='ctx'> 			compatible = "ramoops";</div><div class='ctx'> 			reg = &lt;0x0 0x21f00000 0x0 0x00100000&gt;;</div><div class='del'>-			record-size	= &lt;0x00020000&gt;;</div><div class='del'>-			console-size	= &lt;0x00020000&gt;;</div><div class='del'>-			ftrace-size	= &lt;0x00020000&gt;;</div><div class='add'>+			record-size = &lt;0x00020000&gt;;</div><div class='add'>+			console-size = &lt;0x00020000&gt;;</div><div class='add'>+			ftrace-size = &lt;0x00020000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		/* global autoconfigured region for contiguous allocations */</div><div class='hunk'>@@ -76,13 +76,13 @@</div><div class='ctx'> 			compatible = "syscon-reboot-mode";</div><div class='ctx'> 			offset = &lt;0x0&gt;;</div><div class='ctx'> </div><div class='del'>-			mode-normal	= &lt;0x77665501&gt;;</div><div class='del'>-			mode-bootloader	= &lt;0x77665500&gt;;</div><div class='del'>-			mode-recovery	= &lt;0x77665502&gt;;</div><div class='add'>+			mode-normal = &lt;0x77665501&gt;;</div><div class='add'>+			mode-bootloader = &lt;0x77665500&gt;;</div><div class='add'>+			mode-recovery = &lt;0x77665502&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	reg_sys_5v: regulator@0 {</div><div class='add'>+	reg_sys_5v: regulator-0 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "SYS_5V";</div><div class='ctx'> 		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='hunk'>@@ -91,7 +91,7 @@</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	reg_vdd_3v3: regulator@1 {</div><div class='add'>+	reg_vdd_3v3: regulator-1 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "VDD_3V3";</div><div class='ctx'> 		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='hunk'>@@ -101,7 +101,7 @@</div><div class='ctx'> 		vin-supply = &lt;&amp;reg_sys_5v&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	reg_5v_hub: regulator@2 {</div><div class='add'>+	reg_5v_hub: regulator-2 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "5V_HUB";</div><div class='ctx'> 		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='hunk'>@@ -122,258 +122,42 @@</div><div class='ctx'> 		power-off-delay-us = &lt;10&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	soc {</div><div class='del'>-		spi0: spi@f7106000 {</div><div class='del'>-			status = "ok";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		i2c0: i2c@f7100000 {</div><div class='del'>-			status = "ok";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		i2c1: i2c@f7101000 {</div><div class='del'>-			status = "ok";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		uart1: uart@f7111000 {</div><div class='del'>-			assigned-clocks = &lt;&amp;sys_ctrl HI6220_UART1_SRC&gt;;</div><div class='del'>-			assigned-clock-rates = &lt;150000000&gt;;</div><div class='del'>-			status = "ok";</div><div class='del'>-</div><div class='del'>-			bluetooth {</div><div class='del'>-				compatible = "ti,wl1835-st";</div><div class='del'>-				enable-gpios = &lt;&amp;gpio1 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-				clocks = &lt;&amp;pmic&gt;;</div><div class='del'>-				clock-names = "ext_clock";</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		uart2: uart@f7112000 {</div><div class='del'>-			status = "ok";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		uart3: uart@f7113000 {</div><div class='del'>-			status = "ok";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		/*</div><div class='del'>-		 * Legend: proper name = the GPIO line is used as GPIO</div><div class='del'>-		 *         NC = not connected (not routed from the SoC)</div><div class='del'>-		 *         "[PER]" = pin is muxed for peripheral (not GPIO)</div><div class='del'>-		 *         "" = no idea, schematic doesn't say, could be</div><div class='del'>-		 *              unrouted (not connected to any external pin)</div><div class='del'>-		 *         LSEC = Low Speed External Connector</div><div class='del'>-		 *         HSEC = High Speed External Connector</div><div class='del'>-		 *</div><div class='del'>-		 * Pin assignments taken from LeMaker and CircuitCo Schematics</div><div class='del'>-		 * Rev A1.</div><div class='del'>-		 *</div><div class='del'>-		 * For the lines routed to the external connectors the</div><div class='del'>-		 * lines are named after the 96Boards CE Specification 1.0,</div><div class='del'>-		 * Appendix "Expansion Connector Signal Description".</div><div class='del'>-		 *</div><div class='del'>-		 * When the 96Board naming of a line and the schematic name of</div><div class='del'>-		 * the same line are in conflict, the 96Board specification</div><div class='del'>-		 * takes precedence, which means that the external UART on the</div><div class='del'>-		 * LSEC is named UART0 while the schematic and SoC names this</div><div class='del'>-		 * UART2. This is only for the informational lines i.e. "[FOO]",</div><div class='del'>-		 * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only</div><div class='del'>-		 * ones actually used for GPIO.</div><div class='del'>-		 */</div><div class='del'>-		gpio0: gpio@f8011000 {</div><div class='del'>-			gpio-line-names = "PWR_HOLD", "DSI_SEL",</div><div class='del'>-			"USB_HUB_RESET_N", "USB_SEL", "HDMI_PD", "WL_REG_ON",</div><div class='del'>-			"PWRON_DET", "5V_HUB_EN";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		gpio1: gpio@f8012000 {</div><div class='del'>-			gpio-line-names = "SD_DET", "HDMI_INT", "PMU_IRQ_N",</div><div class='del'>-			"WL_HOST_WAKE", "NC", "NC", "NC", "BT_REG_ON";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		gpio2: gpio@f8013000 {</div><div class='del'>-			gpio-line-names =</div><div class='del'>-				"GPIO-A", /* LSEC Pin 23: GPIO2_0 */</div><div class='del'>-				"GPIO-B", /* LSEC Pin 24: GPIO2_1 */</div><div class='del'>-				"GPIO-C", /* LSEC Pin 25: GPIO2_2 */</div><div class='del'>-				"GPIO-D", /* LSEC Pin 26: GPIO2_3 */</div><div class='del'>-				"GPIO-E", /* LSEC Pin 27: GPIO2_4 */</div><div class='del'>-				"USB_ID_DET", "USB_VBUS_DET",</div><div class='del'>-				"GPIO-H"; /* LSEC Pin 30: GPIO2_7 */</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		gpio3: gpio@f8014000 {</div><div class='del'>-			gpio-line-names = "GPIO3_0", "NC", "NC", "", "NC", "",</div><div class='del'>-			"WLAN_ACTIVE", "NC", "NC";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		gpio4: gpio@f7020000 {</div><div class='del'>-			gpio-line-names = "USER_LED1", "USER_LED2", "USER_LED3",</div><div class='del'>-			"USER_LED4", "SD_SEL", "NC", "NC", "BT_ACTIVE";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		gpio5: gpio@f7021000 {</div><div class='del'>-			gpio-line-names = "NC", "NC",</div><div class='del'>-			"[UART1_RxD]", /* LSEC Pin 11: UART3_RX */</div><div class='del'>-			"[UART1_TxD]", /* LSEC Pin 13: UART3_TX */</div><div class='del'>-			"[AUX_SSI1]", "NC",</div><div class='del'>-			"[PCM_CLK]", /* LSEC Pin 18: MODEM_PCM_XCLK */</div><div class='del'>-			"[PCM_FS]"; /* LSEC Pin 16: MODEM_PCM_XFS */</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		gpio6: gpio@f7022000 {</div><div class='del'>-			gpio-line-names =</div><div class='del'>-			"[SPI0_DIN]", /* Pin 10: SPI0_DI */</div><div class='del'>-			"[SPI0_DOUT]", /* Pin 14: SPI0_DO */</div><div class='del'>-			"[SPI0_CS]", /* Pin 12: SPI0_CS_N */</div><div class='del'>-			"[SPI0_SCLK]", /* Pin 8: SPI0_SCLK */</div><div class='del'>-			"NC", "NC", "NC",</div><div class='del'>-			"GPIO-G"; /* Pin 29: GPIO6_7_DSI_TE0 */</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		gpio7: gpio@f7023000 {</div><div class='del'>-			gpio-line-names = "NC", "NC", "NC", "NC",</div><div class='del'>-			"[PCM_DI]", /* Pin 22: MODEM_PCM_DI */</div><div class='del'>-			"[PCM_DO]", /* Pin 20: MODEM_PCM_DO */</div><div class='del'>-			"NC", "NC";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		gpio8: gpio@f7024000 {</div><div class='del'>-			gpio-line-names = "NC", "[CEC_CLK_19_2MHZ]", "NC",</div><div class='del'>-			"", "", "", "", "", "";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		gpio9: gpio@f7025000 {</div><div class='del'>-			gpio-line-names = "",</div><div class='del'>-			"GPIO-J", /* LSEC Pin 32: ISP_PWDN0_GPIO9_1 */</div><div class='del'>-			"GPIO-L", /* LSEC Pin 34: ISP_PWDN1_GPIO9_2 */</div><div class='del'>-			"NC", "NC", "NC", "NC", "[ISP_CCLK0]";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		gpio10: gpio@f7026000 {</div><div class='del'>-			gpio-line-names = "BOOT_SEL",</div><div class='del'>-			"[ISP_CCLK1]",</div><div class='del'>-			"GPIO-I", /* LSEC Pin 31: ISP_RSTB0_GPIO10_2 */</div><div class='del'>-			"GPIO-K", /* LSEC Pin 33: ISP_RSTB1_GPIO10_3 */</div><div class='del'>-			"NC", "NC",</div><div class='del'>-			"[I2C2_SDA]", /* HSEC Pin 34: ISP0_SDA */</div><div class='del'>-			"[I2C2_SCL]"; /* HSEC Pin 32: ISP0_SCL */</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		gpio11: gpio@f7027000 {</div><div class='del'>-			gpio-line-names =</div><div class='del'>-			"[I2C3_SDA]", /* HSEC Pin 38: ISP1_SDA */</div><div class='del'>-			"[I2C3_SCL]", /* HSEC Pin 36: ISP1_SCL */</div><div class='del'>-			"", "NC", "NC", "NC", "", "";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		gpio12: gpio@f7028000 {</div><div class='del'>-			gpio-line-names = "[BT_PCM_XFS]", "[BT_PCM_DI]",</div><div class='del'>-			"[BT_PCM_DO]",</div><div class='del'>-			"NC", "NC", "NC", "NC",</div><div class='del'>-			"GPIO-F"; /* LSEC Pin 28: BL_PWM_GPIO12_7 */</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		gpio13: gpio@f7029000 {</div><div class='del'>-			gpio-line-names = "[UART0_RX]", "[UART0_TX]",</div><div class='del'>-			"[BT_UART1_CTS]", "[BT_UART1_RTS]",</div><div class='del'>-			"[BT_UART1_RX]", "[BT_UART1_TX]",</div><div class='del'>-			"[UART0_CTS]", /* LSEC Pin 3: UART2_CTS_N */</div><div class='del'>-			"[UART0_RTS]"; /* LSEC Pin 9: UART2_RTS_N */</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		gpio14: gpio@f702a000 {</div><div class='del'>-			gpio-line-names =</div><div class='del'>-			"[UART0_RxD]", /* LSEC Pin 7: UART2_RX */</div><div class='del'>-			"[UART0_TxD]", /* LSEC Pin 5: UART2_TX */</div><div class='del'>-			"[I2C0_SCL]", /* LSEC Pin 15: I2C0_SCL */</div><div class='del'>-			"[I2C0_SDA]", /* LSEC Pin 17: I2C0_SDA */</div><div class='del'>-			"[I2C1_SCL]", /* LSEC Pin 19: I2C1_SCL */</div><div class='del'>-			"[I2C1_SDA]", /* LSEC Pin 21: I2C1_SDA */</div><div class='del'>-			"[I2C2_SCL]", "[I2C2_SDA]";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		gpio15: gpio@f702b000 {</div><div class='del'>-			gpio-line-names = "", "", "", "", "", "", "NC", "";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		/* GPIO blocks 16 thru 19 do not appear to be routed to pins */</div><div class='del'>-</div><div class='del'>-		dwmmc_0: dwmmc0@f723d000 {</div><div class='del'>-			cap-mmc-highspeed;</div><div class='del'>-			non-removable;</div><div class='del'>-			bus-width = &lt;0x8&gt;;</div><div class='del'>-			vmmc-supply = &lt;&amp;ldo19&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		dwmmc_1: dwmmc1@f723e000 {</div><div class='del'>-			card-detect-delay = &lt;200&gt;;</div><div class='del'>-			cap-sd-highspeed;</div><div class='del'>-			sd-uhs-sdr12;</div><div class='del'>-			sd-uhs-sdr25;</div><div class='del'>-			sd-uhs-sdr50;</div><div class='del'>-			vqmmc-supply = &lt;&amp;ldo7&gt;;</div><div class='del'>-			vmmc-supply = &lt;&amp;ldo10&gt;;</div><div class='del'>-			bus-width = &lt;0x4&gt;;</div><div class='del'>-			disable-wp;</div><div class='del'>-			cd-gpios = &lt;&amp;gpio1 0 1&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		dwmmc_2: dwmmc2@f723f000 {</div><div class='del'>-			bus-width = &lt;0x4&gt;;</div><div class='del'>-			non-removable;</div><div class='del'>-			cap-power-off-card;</div><div class='del'>-			vmmc-supply = &lt;&amp;reg_vdd_3v3&gt;;</div><div class='del'>-			mmc-pwrseq = &lt;&amp;wl1835_pwrseq&gt;;</div><div class='del'>-</div><div class='del'>-			#address-cells = &lt;0x1&gt;;</div><div class='del'>-			#size-cells = &lt;0x0&gt;;</div><div class='del'>-			wlcore: wlcore@2 {</div><div class='del'>-				compatible = "ti,wl1835";</div><div class='del'>-				reg = &lt;2&gt;;	/* sdio func num */</div><div class='del'>-				/* WL_IRQ, WL_HOST_WAKE_GPIO1_3 */</div><div class='del'>-				interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='del'>-				interrupts = &lt;3 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='ctx'> 	leds {</div><div class='ctx'> 		compatible = "gpio-leds";</div><div class='ctx'> </div><div class='del'>-		user_led1 {</div><div class='add'>+		led-user-1 {</div><div class='ctx'> 			label = "green:user1";</div><div class='ctx'> 			gpios = &lt;&amp;gpio4 0 0&gt;; /* &lt;&amp;gpio_user_led_1&gt;; */</div><div class='ctx'> 			linux,default-trigger = "heartbeat";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		user_led2 {</div><div class='add'>+		led-user-2 {</div><div class='ctx'> 			label = "green:user2";</div><div class='ctx'> 			gpios = &lt;&amp;gpio4 1 0&gt;; /* &lt;&amp;gpio_user_led_2&gt;; */</div><div class='ctx'> 			linux,default-trigger = "mmc0";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		user_led3 {</div><div class='add'>+		led-user-3 {</div><div class='ctx'> 			label = "green:user3";</div><div class='ctx'> 			gpios = &lt;&amp;gpio4 2 0&gt;; /* &lt;&amp;gpio_user_led_3&gt;; */</div><div class='ctx'> 			linux,default-trigger = "mmc1";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		user_led4 {</div><div class='add'>+		led-user-4 {</div><div class='ctx'> 			label = "green:user4";</div><div class='ctx'> 			gpios = &lt;&amp;gpio4 3 0&gt;; /* &lt;&amp;gpio_user_led_4&gt;; */</div><div class='ctx'> 			panic-indicator;</div><div class='ctx'> 			linux,default-trigger = "none";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		wlan_active_led {</div><div class='add'>+		led-wlan {</div><div class='ctx'> 			label = "yellow:wlan";</div><div class='ctx'> 			gpios = &lt;&amp;gpio3 5 0&gt;; /* &lt;&amp;gpio_wlan_active_led&gt;; */</div><div class='ctx'> 			linux,default-trigger = "phy0tx";</div><div class='ctx'> 			default-state = "off";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		bt_active_led {</div><div class='add'>+		led-bt {</div><div class='ctx'> 			label = "blue:bt";</div><div class='ctx'> 			gpios = &lt;&amp;gpio4 7 0&gt;; /* &lt;&amp;gpio_bt_active_led&gt;; */</div><div class='ctx'> 			linux,default-trigger = "hci0-power";</div><div class='hunk'>@@ -480,19 +264,35 @@</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;uart1 {</div><div class='add'>+	assigned-clocks = &lt;&amp;sys_ctrl HI6220_UART1_SRC&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;150000000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "ti,wl1835-st";</div><div class='add'>+		enable-gpios = &lt;&amp;gpio1 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;pmic&gt;;</div><div class='add'>+		clock-names = "ext_clock";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;uart2 {</div><div class='add'>+	status = "okay";</div><div class='ctx'> 	label = "LS-UART0";</div><div class='ctx'> };</div><div class='add'>+</div><div class='ctx'> &amp;uart3 {</div><div class='add'>+	status = "okay";</div><div class='ctx'> 	label = "LS-UART1";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;ade {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;dsi {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> </div><div class='ctx'> 	ports {</div><div class='ctx'> 		/* 1 for output port */</div><div class='hunk'>@@ -506,17 +306,207 @@</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;dwmmc_0 {</div><div class='add'>+	cap-mmc-highspeed;</div><div class='add'>+	non-removable;</div><div class='add'>+	bus-width = &lt;0x8&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;ldo19&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dwmmc_1 {</div><div class='add'>+	card-detect-delay = &lt;200&gt;;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	sd-uhs-sdr12;</div><div class='add'>+	sd-uhs-sdr25;</div><div class='add'>+	sd-uhs-sdr50;</div><div class='add'>+	vqmmc-supply = &lt;&amp;ldo7&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;ldo10&gt;;</div><div class='add'>+	bus-width = &lt;0x4&gt;;</div><div class='add'>+	disable-wp;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio1 0 1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dwmmc_2 {</div><div class='add'>+	bus-width = &lt;0x4&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	cap-power-off-card;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_vdd_3v3&gt;;</div><div class='add'>+	mmc-pwrseq = &lt;&amp;wl1835_pwrseq&gt;;</div><div class='add'>+</div><div class='add'>+	#address-cells = &lt;0x1&gt;;</div><div class='add'>+	#size-cells = &lt;0x0&gt;;</div><div class='add'>+	wlcore: wlcore@2 {</div><div class='add'>+		compatible = "ti,wl1835";</div><div class='add'>+		reg = &lt;2&gt;;	/* sdio func num */</div><div class='add'>+		/* WL_IRQ, WL_HOST_WAKE_GPIO1_3 */</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='add'>+		interrupts = &lt;3 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Legend: proper name = the GPIO line is used as GPIO</div><div class='add'>+ *         NC = not connected (not routed from the SoC)</div><div class='add'>+ *         "[PER]" = pin is muxed for peripheral (not GPIO)</div><div class='add'>+ *         "" = no idea, schematic doesn't say, could be</div><div class='add'>+ *              unrouted (not connected to any external pin)</div><div class='add'>+ *         LSEC = Low Speed External Connector</div><div class='add'>+ *         HSEC = High Speed External Connector</div><div class='add'>+ *</div><div class='add'>+ * Pin assignments taken from LeMaker and CircuitCo Schematics</div><div class='add'>+ * Rev A1.</div><div class='add'>+ *</div><div class='add'>+ * For the lines routed to the external connectors the</div><div class='add'>+ * lines are named after the 96Boards CE Specification 1.0,</div><div class='add'>+ * Appendix "Expansion Connector Signal Description".</div><div class='add'>+ *</div><div class='add'>+ * When the 96Board naming of a line and the schematic name of</div><div class='add'>+ * the same line are in conflict, the 96Board specification</div><div class='add'>+ * takes precedence, which means that the external UART on the</div><div class='add'>+ * LSEC is named UART0 while the schematic and SoC names this</div><div class='add'>+ * UART2. This is only for the informational lines i.e. "[FOO]",</div><div class='add'>+ * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only</div><div class='add'>+ * ones actually used for GPIO.</div><div class='add'>+ */</div><div class='add'>+&amp;gpio0 {</div><div class='add'>+	gpio-line-names = "PWR_HOLD", "DSI_SEL",</div><div class='add'>+	"USB_HUB_RESET_N", "USB_SEL", "HDMI_PD", "WL_REG_ON",</div><div class='add'>+	"PWRON_DET", "5V_HUB_EN";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	gpio-line-names = "SD_DET", "HDMI_INT", "PMU_IRQ_N",</div><div class='add'>+	"WL_HOST_WAKE", "NC", "NC", "NC", "BT_REG_ON";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio2 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"GPIO-A", /* LSEC Pin 23: GPIO2_0 */</div><div class='add'>+		"GPIO-B", /* LSEC Pin 24: GPIO2_1 */</div><div class='add'>+		"GPIO-C", /* LSEC Pin 25: GPIO2_2 */</div><div class='add'>+		"GPIO-D", /* LSEC Pin 26: GPIO2_3 */</div><div class='add'>+		"GPIO-E", /* LSEC Pin 27: GPIO2_4 */</div><div class='add'>+		"USB_ID_DET", "USB_VBUS_DET",</div><div class='add'>+		"GPIO-H"; /* LSEC Pin 30: GPIO2_7 */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio3 {</div><div class='add'>+	gpio-line-names = "GPIO3_0", "NC", "NC", "", "NC", "",</div><div class='add'>+	"WLAN_ACTIVE", "NC", "NC";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio4 {</div><div class='add'>+	gpio-line-names = "USER_LED1", "USER_LED2", "USER_LED3",</div><div class='add'>+	"USER_LED4", "SD_SEL", "NC", "NC", "BT_ACTIVE";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio5 {</div><div class='add'>+	gpio-line-names = "NC", "NC",</div><div class='add'>+	"[UART1_RxD]", /* LSEC Pin 11: UART3_RX */</div><div class='add'>+	"[UART1_TxD]", /* LSEC Pin 13: UART3_TX */</div><div class='add'>+	"[AUX_SSI1]", "NC",</div><div class='add'>+	"[PCM_CLK]", /* LSEC Pin 18: MODEM_PCM_XCLK */</div><div class='add'>+	"[PCM_FS]"; /* LSEC Pin 16: MODEM_PCM_XFS */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio6 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+	"[SPI0_DIN]", /* Pin 10: SPI0_DI */</div><div class='add'>+	"[SPI0_DOUT]", /* Pin 14: SPI0_DO */</div><div class='add'>+	"[SPI0_CS]", /* Pin 12: SPI0_CS_N */</div><div class='add'>+	"[SPI0_SCLK]", /* Pin 8: SPI0_SCLK */</div><div class='add'>+	"NC", "NC", "NC",</div><div class='add'>+	"GPIO-G"; /* Pin 29: GPIO6_7_DSI_TE0 */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio7 {</div><div class='add'>+	gpio-line-names = "NC", "NC", "NC", "NC",</div><div class='add'>+	"[PCM_DI]", /* Pin 22: MODEM_PCM_DI */</div><div class='add'>+	"[PCM_DO]", /* Pin 20: MODEM_PCM_DO */</div><div class='add'>+	"NC", "NC";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio8 {</div><div class='add'>+	gpio-line-names = "NC", "[CEC_CLK_19_2MHZ]", "NC",</div><div class='add'>+	"", "", "", "", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio9 {</div><div class='add'>+	gpio-line-names = "",</div><div class='add'>+	"GPIO-J", /* LSEC Pin 32: ISP_PWDN0_GPIO9_1 */</div><div class='add'>+	"GPIO-L", /* LSEC Pin 34: ISP_PWDN1_GPIO9_2 */</div><div class='add'>+	"NC", "NC", "NC", "NC", "[ISP_CCLK0]";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio10 {</div><div class='add'>+	gpio-line-names = "BOOT_SEL",</div><div class='add'>+	"[ISP_CCLK1]",</div><div class='add'>+	"GPIO-I", /* LSEC Pin 31: ISP_RSTB0_GPIO10_2 */</div><div class='add'>+	"GPIO-K", /* LSEC Pin 33: ISP_RSTB1_GPIO10_3 */</div><div class='add'>+	"NC", "NC",</div><div class='add'>+	"[I2C2_SDA]", /* HSEC Pin 34: ISP0_SDA */</div><div class='add'>+	"[I2C2_SCL]"; /* HSEC Pin 32: ISP0_SCL */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio11 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+	"[I2C3_SDA]", /* HSEC Pin 38: ISP1_SDA */</div><div class='add'>+	"[I2C3_SCL]", /* HSEC Pin 36: ISP1_SCL */</div><div class='add'>+	"", "NC", "NC", "NC", "", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio12 {</div><div class='add'>+	gpio-line-names = "[BT_PCM_XFS]", "[BT_PCM_DI]",</div><div class='add'>+	"[BT_PCM_DO]",</div><div class='add'>+	"NC", "NC", "NC", "NC",</div><div class='add'>+	"GPIO-F"; /* LSEC Pin 28: BL_PWM_GPIO12_7 */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio13 {</div><div class='add'>+	gpio-line-names = "[UART0_RX]", "[UART0_TX]",</div><div class='add'>+	"[BT_UART1_CTS]", "[BT_UART1_RTS]",</div><div class='add'>+	"[BT_UART1_RX]", "[BT_UART1_TX]",</div><div class='add'>+	"[UART0_CTS]", /* LSEC Pin 3: UART2_CTS_N */</div><div class='add'>+	"[UART0_RTS]"; /* LSEC Pin 9: UART2_RTS_N */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio14 {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+	"[UART0_RxD]", /* LSEC Pin 7: UART2_RX */</div><div class='add'>+	"[UART0_TxD]", /* LSEC Pin 5: UART2_TX */</div><div class='add'>+	"[I2C0_SCL]", /* LSEC Pin 15: I2C0_SCL */</div><div class='add'>+	"[I2C0_SDA]", /* LSEC Pin 17: I2C0_SDA */</div><div class='add'>+	"[I2C1_SCL]", /* LSEC Pin 19: I2C1_SCL */</div><div class='add'>+	"[I2C1_SDA]", /* LSEC Pin 21: I2C1_SDA */</div><div class='add'>+	"[I2C2_SCL]", "[I2C2_SDA]";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio15 {</div><div class='add'>+	gpio-line-names = "", "", "", "", "", "", "NC", "";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* GPIO blocks 16 thru 19 do not appear to be routed to pins */</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;i2c2 {</div><div class='ctx'> 	#address-cells = &lt;1&gt;;</div><div class='ctx'> 	#size-cells = &lt;0&gt;;</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> </div><div class='ctx'> 	adv7533: adv7533@39 {</div><div class='ctx'> 		compatible = "adi,adv7533";</div><div class='ctx'> 		reg = &lt;0x39&gt;;</div><div class='ctx'> 		interrupt-parent = &lt;&amp;gpio1&gt;;</div><div class='ctx'> 		interrupts = &lt;1 2&gt;;</div><div class='del'>-		pd-gpio = &lt;&amp;gpio0 4 0&gt;;</div><div class='add'>+		pd-gpios = &lt;&amp;gpio0 4 0&gt;;</div><div class='ctx'> 		adi,dsi-lanes = &lt;4&gt;;</div><div class='ctx'> 		#sound-dai-cells = &lt;0&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -524,6 +514,7 @@</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='ctx'> 				adv7533_in: endpoint {</div><div class='ctx'> 					remote-endpoint = &lt;&amp;dsi_out0&gt;;</div><div class='ctx'> 				};</div><div class='hunk'>@@ -549,3 +540,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='add'>+</div><div class='add'>+&amp;spi0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi<br/>index 2072b637b5af..f8b56d443850 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/hisilicon/hi6220.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/hisilicon/hi6220.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/hisilicon/hi6220.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/hisilicon/hi6220.dtsi</a></div><div class='hunk'>@@ -2,7 +2,7 @@</div><div class='ctx'> /*</div><div class='ctx'>  * dts file for Hisilicon Hi6220 SoC</div><div class='ctx'>  *</div><div class='del'>- * Copyright (C) 2015, Hisilicon Ltd.</div><div class='add'>+ * Copyright (C) 2015, HiSilicon Ltd.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='hunk'>@@ -186,14 +186,18 @@</div><div class='ctx'> </div><div class='ctx'> 		CLUSTER0_L2: l2-cache0 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		CLUSTER1_L2: l2-cache1 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	cpu_opp_table: cpu_opp_table {</div><div class='add'>+	cpu_opp_table: opp-table-0 {</div><div class='ctx'> 		compatible = "operating-points-v2";</div><div class='ctx'> 		opp-shared;</div><div class='ctx'> </div><div class='hunk'>@@ -302,7 +306,7 @@</div><div class='ctx'> 			mboxes = &lt;&amp;mailbox 1 0 11&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		uart0: uart@f8015000 {	/* console */</div><div class='add'>+		uart0: serial@f8015000 {	/* console */</div><div class='ctx'> 			compatible = "arm,pl011", "arm,primecell";</div><div class='ctx'> 			reg = &lt;0x0 0xf8015000 0x0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='hunk'>@@ -311,7 +315,7 @@</div><div class='ctx'> 			clock-names = "uartclk", "apb_pclk";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		uart1: uart@f7111000 {</div><div class='add'>+		uart1: serial@f7111000 {</div><div class='ctx'> 			compatible = "arm,pl011", "arm,primecell";</div><div class='ctx'> 			reg = &lt;0x0 0xf7111000 0x0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='hunk'>@@ -325,7 +329,7 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		uart2: uart@f7112000 {</div><div class='add'>+		uart2: serial@f7112000 {</div><div class='ctx'> 			compatible = "arm,pl011", "arm,primecell";</div><div class='ctx'> 			reg = &lt;0x0 0xf7112000 0x0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='hunk'>@@ -337,7 +341,7 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		uart3: uart@f7113000 {</div><div class='add'>+		uart3: serial@f7113000 {</div><div class='ctx'> 			compatible = "arm,pl011", "arm,primecell";</div><div class='ctx'> 			reg = &lt;0x0 0xf7113000 0x0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='hunk'>@@ -349,7 +353,7 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		uart4: uart@f7114000 {</div><div class='add'>+		uart4: serial@f7114000 {</div><div class='ctx'> 			compatible = "arm,pl011", "arm,primecell";</div><div class='ctx'> 			reg = &lt;0x0 0xf7114000 0x0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='hunk'>@@ -371,7 +375,7 @@</div><div class='ctx'> 			clocks = &lt;&amp;sys_ctrl HI6220_EDMAC_ACLK&gt;;</div><div class='ctx'> 			dma-no-cci;</div><div class='ctx'> 			dma-type = "hi6220_dma";</div><div class='del'>-			status = "ok";</div><div class='add'>+			status = "okay";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		dual_timer0: timer@f8008000 {</div><div class='hunk'>@@ -405,7 +409,7 @@</div><div class='ctx'> 			compatible = "pinctrl-single";</div><div class='ctx'> 			reg = &lt;0x0 0xf7010000  0x0 0x27c&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='del'>-			#size-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			#pinctrl-cells = &lt;1&gt;;</div><div class='ctx'> 			#gpio-range-cells = &lt;3&gt;;</div><div class='ctx'> 			pinctrl-single,register-width = &lt;32&gt;;</div><div class='hunk'>@@ -444,7 +448,7 @@</div><div class='ctx'> 			compatible = "pinconf-single";</div><div class='ctx'> 			reg = &lt;0x0 0xf7010800 0x0 0x28c&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='del'>-			#size-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			#pinctrl-cells = &lt;1&gt;;</div><div class='ctx'> 			pinctrl-single,register-width = &lt;32&gt;;</div><div class='ctx'> 		};</div><div class='hunk'>@@ -453,7 +457,7 @@</div><div class='ctx'> 			compatible = "pinconf-single";</div><div class='ctx'> 			reg = &lt;0x0 0xf8001800 0x0 0x78&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='del'>-			#size-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			#pinctrl-cells = &lt;1&gt;;</div><div class='ctx'> 			pinctrl-single,register-width = &lt;32&gt;;</div><div class='ctx'> 		};</div><div class='hunk'>@@ -723,10 +727,8 @@</div><div class='ctx'> 			compatible = "arm,pl022", "arm,primecell";</div><div class='ctx'> 			reg = &lt;0x0 0xf7106000 0x0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;0 50 4&gt;;</div><div class='del'>-			bus-id = &lt;0&gt;;</div><div class='del'>-			enable-dma = &lt;0&gt;;</div><div class='del'>-			clocks = &lt;&amp;sys_ctrl HI6220_SPI_CLK&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='add'>+			clocks = &lt;&amp;sys_ctrl HI6220_SPI_CLK&gt;, &lt;&amp;sys_ctrl HI6220_SPI_CLK&gt;;</div><div class='add'>+			clock-names = "sspclk", "apb_pclk";</div><div class='ctx'> 			pinctrl-names = "default";</div><div class='ctx'> 			pinctrl-0 = &lt;&amp;spi0_pmx_func &amp;spi0_cfg_func&gt;;</div><div class='ctx'> 			num-cs = &lt;1&gt;;</div><div class='hunk'>@@ -840,14 +842,15 @@</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		watchdog0: watchdog@f8005000 {</div><div class='del'>-			compatible = "arm,sp805-wdt", "arm,primecell";</div><div class='add'>+			compatible = "arm,sp805", "arm,primecell";</div><div class='ctx'> 			reg = &lt;0x0 0xf8005000 0x0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;ao_ctrl HI6220_WDT0_PCLK&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='add'>+			clocks = &lt;&amp;ao_ctrl HI6220_WDT0_PCLK&gt;,</div><div class='add'>+				 &lt;&amp;ao_ctrl HI6220_WDT0_PCLK&gt;;</div><div class='add'>+			clock-names = "wdog_clk", "apb_pclk";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		tsensor: tsensor@0,f7030700 {</div><div class='add'>+		tsensor: tsensor@f7030700 {</div><div class='ctx'> 			compatible = "hisilicon,tsensor";</div><div class='ctx'> 			reg = &lt;0x0 0xf7030700 0x0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='hunk'>@@ -856,7 +859,7 @@</div><div class='ctx'> 			#thermal-sensor-cells = &lt;1&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		i2s0: i2s@f7118000{</div><div class='add'>+		i2s0: i2s@f7118000 {</div><div class='ctx'> 			compatible = "hisilicon,hi6210-i2s";</div><div class='ctx'> 			reg = &lt;0x0 0xf7118000 0x0 0x8000&gt;; /* i2s unit */</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH&gt;; /* 155 "DigACodec_intr"-32 */</div><div class='hunk'>@@ -871,7 +874,7 @@</div><div class='ctx'> </div><div class='ctx'> 		thermal-zones {</div><div class='ctx'> </div><div class='del'>-			cls0: cls0 {</div><div class='add'>+			cls0: cls0-thermal {</div><div class='ctx'> 				polling-delay = &lt;1000&gt;;</div><div class='ctx'> 				polling-delay-passive = &lt;100&gt;;</div><div class='ctx'> 				sustainable-power = &lt;3326&gt;;</div><div class='hunk'>@@ -880,13 +883,13 @@</div><div class='ctx'> 				thermal-sensors = &lt;&amp;tsensor 2&gt;;</div><div class='ctx'> </div><div class='ctx'> 				trips {</div><div class='del'>-					threshold: trip-point@0 {</div><div class='add'>+					threshold: trip-point0 {</div><div class='ctx'> 						temperature = &lt;65000&gt;;</div><div class='ctx'> 						hysteresis = &lt;0&gt;;</div><div class='ctx'> 						type = "passive";</div><div class='ctx'> 					};</div><div class='ctx'> </div><div class='del'>-					target: trip-point@1 {</div><div class='add'>+					target: trip-point1 {</div><div class='ctx'> 						temperature = &lt;75000&gt;;</div><div class='ctx'> 						hysteresis = &lt;0&gt;;</div><div class='ctx'> 						type = "passive";</div><div class='hunk'>@@ -1027,17 +1030,17 @@</div><div class='ctx'> 			compatible = "hisilicon,hi6220-mali", "arm,mali-450";</div><div class='ctx'> 			reg = &lt;0x0 0xf4080000 0x0 0x00040000&gt;;</div><div class='ctx'> 			interrupt-parent = &lt;&amp;gic&gt;;</div><div class='del'>-			interrupts =	&lt;GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-					&lt;GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-					&lt;GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-					&lt;GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-					&lt;GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-					&lt;GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-					&lt;GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-					&lt;GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-					&lt;GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-					&lt;GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-					&lt;GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupts = &lt;GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> </div><div class='ctx'> 			interrupt-names = "gp",</div><div class='ctx'> 					  "gpmmu",</div><div class='hunk'>@@ -1052,7 +1055,7 @@</div><div class='ctx'> 					  "ppmmu3";</div><div class='ctx'> 			clocks = &lt;&amp;media_ctrl HI6220_G3D_CLK&gt;,</div><div class='ctx'> 				 &lt;&amp;media_ctrl HI6220_G3D_PCLK&gt;;</div><div class='del'>-			clock-names = "core", "bus";</div><div class='add'>+			clock-names = "bus", "core";</div><div class='ctx'> 			assigned-clocks = &lt;&amp;media_ctrl HI6220_G3D_CLK&gt;,</div><div class='ctx'> 					  &lt;&amp;media_ctrl HI6220_G3D_PCLK&gt;;</div><div class='ctx'> 			assigned-clock-rates = &lt;500000000&gt;, &lt;144000000&gt;;</div><div class='head'>diff --git a/arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi b/arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi<br/>index e7d22619a4c0..3e27624c31de 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi</a></div><div class='hunk'>@@ -17,13 +17,13 @@</div><div class='ctx'> 				&amp;bl_pwm_pmx_func</div><div class='ctx'> 				&gt;;</div><div class='ctx'> </div><div class='del'>-			boot_sel_pmx_func: boot_sel_pmx_func {</div><div class='add'>+			boot_sel_pmx_func: boot-sel-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x0    MUX_M0	/* BOOT_SEL     (IOMG000) */</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			emmc_pmx_func: emmc_pmx_func {</div><div class='add'>+			emmc_pmx_func: emmc-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x100  MUX_M0	/* EMMC_CLK     (IOMG064) */</div><div class='ctx'> 					0x104  MUX_M0	/* EMMC_CMD     (IOMG065) */</div><div class='hunk'>@@ -38,7 +38,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			sd_pmx_func: sd_pmx_func {</div><div class='add'>+			sd_pmx_func: sd-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0xc    MUX_M0	/* SD_CLK       (IOMG003) */</div><div class='ctx'> 					0x10   MUX_M0	/* SD_CMD       (IOMG004) */</div><div class='hunk'>@@ -48,7 +48,7 @@</div><div class='ctx'> 					0x20   MUX_M0	/* SD_DATA3     (IOMG008) */</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='del'>-			sd_pmx_idle: sd_pmx_idle {</div><div class='add'>+			sd_pmx_idle: sd-idle-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0xc    MUX_M1	/* SD_CLK       (IOMG003) */</div><div class='ctx'> 					0x10   MUX_M1	/* SD_CMD       (IOMG004) */</div><div class='hunk'>@@ -59,7 +59,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			sdio_pmx_func: sdio_pmx_func {</div><div class='add'>+			sdio_pmx_func: sdio-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x128  MUX_M0	/* SDIO_CLK     (IOMG074) */</div><div class='ctx'> 					0x12c  MUX_M0	/* SDIO_CMD     (IOMG075) */</div><div class='hunk'>@@ -69,7 +69,7 @@</div><div class='ctx'> 					0x13c  MUX_M0	/* SDIO_DATA3   (IOMG079) */</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='del'>-			sdio_pmx_idle: sdio_pmx_idle {</div><div class='add'>+			sdio_pmx_idle: sdio-idle-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x128  MUX_M1	/* SDIO_CLK     (IOMG074) */</div><div class='ctx'> 					0x12c  MUX_M1	/* SDIO_CMD     (IOMG075) */</div><div class='hunk'>@@ -80,7 +80,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			isp_pmx_func: isp_pmx_func {</div><div class='add'>+			isp_pmx_func: isp-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x24   MUX_M0	/* ISP_PWDN0    (IOMG009) */</div><div class='ctx'> 					0x28   MUX_M0	/* ISP_PWDN1    (IOMG010) */</div><div class='hunk'>@@ -101,19 +101,19 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			hkadc_ssi_pmx_func: hkadc_ssi_pmx_func {</div><div class='add'>+			hkadc_ssi_pmx_func: hkadc-ssi-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x68   MUX_M0	/* HKADC_SSI    (IOMG026) */</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			codec_clk_pmx_func: codec_clk_pmx_func {</div><div class='add'>+			codec_clk_pmx_func: codec-clk-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x6c   MUX_M0	/* CODEC_CLK    (IOMG027) */</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			codec_pmx_func: codec_pmx_func {</div><div class='add'>+			codec_pmx_func: codec-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x70   MUX_M1	/* DMIC_CLK     (IOMG028) */</div><div class='ctx'> 					0x74   MUX_M0	/* CODEC_SYNC   (IOMG029) */</div><div class='hunk'>@@ -122,7 +122,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			fm_pmx_func: fm_pmx_func {</div><div class='add'>+			fm_pmx_func: fm-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x80   MUX_M1	/* FM_XCLK      (IOMG032) */</div><div class='ctx'> 					0x84   MUX_M1	/* FM_XFS       (IOMG033) */</div><div class='hunk'>@@ -131,7 +131,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			bt_pmx_func: bt_pmx_func {</div><div class='add'>+			bt_pmx_func: bt-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x90   MUX_M0	/* BT_XCLK      (IOMG036) */</div><div class='ctx'> 					0x94   MUX_M0	/* BT_XFS       (IOMG037) */</div><div class='hunk'>@@ -140,26 +140,26 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			pwm_in_pmx_func: pwm_in_pmx_func {</div><div class='add'>+			pwm_in_pmx_func: pwm-in-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0xb8   MUX_M1	/* PWM_IN       (IOMG046) */</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			bl_pwm_pmx_func: bl_pwm_pmx_func {</div><div class='add'>+			bl_pwm_pmx_func: bl-pwm-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0xbc   MUX_M1	/* BL_PWM       (IOMG047) */</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			uart0_pmx_func: uart0_pmx_func {</div><div class='add'>+			uart0_pmx_func: uart0-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0xc0   MUX_M0	/* UART0_RXD    (IOMG048) */</div><div class='ctx'> 					0xc4   MUX_M0	/* UART0_TXD    (IOMG049) */</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			uart1_pmx_func: uart1_pmx_func {</div><div class='add'>+			uart1_pmx_func: uart1-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0xc8   MUX_M0	/* UART1_CTS_N  (IOMG050) */</div><div class='ctx'> 					0xcc   MUX_M0	/* UART1_RTS_N  (IOMG051) */</div><div class='hunk'>@@ -168,7 +168,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			uart2_pmx_func: uart2_pmx_func {</div><div class='add'>+			uart2_pmx_func: uart2-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0xd8   MUX_M0	/* UART2_CTS_N  (IOMG054) */</div><div class='ctx'> 					0xdc   MUX_M0	/* UART2_RTS_N  (IOMG055) */</div><div class='hunk'>@@ -177,7 +177,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			uart3_pmx_func: uart3_pmx_func {</div><div class='add'>+			uart3_pmx_func: uart3-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x180  MUX_M1	/* UART3_CTS_N  (IOMG096) */</div><div class='ctx'> 					0x184  MUX_M1	/* UART3_RTS_N  (IOMG097) */</div><div class='hunk'>@@ -186,7 +186,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			uart4_pmx_func: uart4_pmx_func {</div><div class='add'>+			uart4_pmx_func: uart4-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x1d0  MUX_M1	/* UART4_CTS_N  (IOMG116) */</div><div class='ctx'> 					0x1d4  MUX_M1	/* UART4_RTS_N  (IOMG117) */</div><div class='hunk'>@@ -195,35 +195,35 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			uart5_pmx_func: uart5_pmx_func {</div><div class='add'>+			uart5_pmx_func: uart5-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x1c8  MUX_M1	/* UART5_RXD    (IOMG114) */</div><div class='ctx'> 					0x1cc  MUX_M1	/* UART5_TXD    (IOMG115) */</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			i2c0_pmx_func: i2c0_pmx_func {</div><div class='add'>+			i2c0_pmx_func: i2c0-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0xe8   MUX_M0	/* I2C0_SCL     (IOMG058) */</div><div class='ctx'> 					0xec   MUX_M0	/* I2C0_SDA     (IOMG059) */</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			i2c1_pmx_func: i2c1_pmx_func {</div><div class='add'>+			i2c1_pmx_func: i2c1-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0xf0   MUX_M0	/* I2C1_SCL     (IOMG060) */</div><div class='ctx'> 					0xf4   MUX_M0	/* I2C1_SDA     (IOMG061) */</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			i2c2_pmx_func: i2c2_pmx_func {</div><div class='add'>+			i2c2_pmx_func: i2c2-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0xf8   MUX_M0	/* I2C2_SCL     (IOMG062) */</div><div class='ctx'> 					0xfc   MUX_M0	/* I2C2_SDA     (IOMG063) */</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			spi0_pmx_func: spi0_pmx_func {</div><div class='add'>+			spi0_pmx_func: spi0-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x1a0  MUX_M1   /* SPI0_DI      (IOMG104) */</div><div class='ctx'> 					0x1a4  MUX_M1	/* SPI0_DO	(IOMG105) */</div><div class='hunk'>@@ -244,7 +244,7 @@</div><div class='ctx'> 				&amp;bl_pwm_cfg_func</div><div class='ctx'> 				&gt;;</div><div class='ctx'> </div><div class='del'>-			boot_sel_cfg_func: boot_sel_cfg_func {</div><div class='add'>+			boot_sel_cfg_func: boot-sel-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x0    0x0	/* BOOT_SEL     (IOCFG000) */</div><div class='ctx'> 				&gt;;</div><div class='hunk'>@@ -253,7 +253,7 @@</div><div class='ctx'> 				pinctrl-single,drive-strength = &lt;DRIVE1_02MA DRIVE_MASK&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			hkadc_ssi_cfg_func: hkadc_ssi_cfg_func {</div><div class='add'>+			hkadc_ssi_cfg_func: hkadc-ssi-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x6c   0x0	/* HKADC_SSI    (IOCFG027) */</div><div class='ctx'> 				&gt;;</div><div class='hunk'>@@ -262,7 +262,7 @@</div><div class='ctx'> 				pinctrl-single,drive-strength = &lt;DRIVE1_02MA DRIVE_MASK&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			emmc_clk_cfg_func: emmc_clk_cfg_func {</div><div class='add'>+			emmc_clk_cfg_func: emmc-clk-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x104  0x0	/* EMMC_CLK     (IOCFG065) */</div><div class='ctx'> 				&gt;;</div><div class='hunk'>@@ -271,7 +271,7 @@</div><div class='ctx'> 				pinctrl-single,drive-strength = &lt;DRIVE1_08MA DRIVE_MASK&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			emmc_cfg_func: emmc_cfg_func {</div><div class='add'>+			emmc_cfg_func: emmc-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x108  0x0	/* EMMC_CMD     (IOCFG066) */</div><div class='ctx'> 					0x10c  0x0	/* EMMC_DATA0   (IOCFG067) */</div><div class='hunk'>@@ -288,7 +288,7 @@</div><div class='ctx'> 				pinctrl-single,drive-strength = &lt;DRIVE1_04MA DRIVE_MASK&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			emmc_rst_cfg_func: emmc_rst_cfg_func {</div><div class='add'>+			emmc_rst_cfg_func: emmc-rst-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x12c  0x0	/* EMMC_RST_N   (IOCFG075) */</div><div class='ctx'> 				&gt;;</div><div class='hunk'>@@ -297,7 +297,7 @@</div><div class='ctx'> 				pinctrl-single,drive-strength = &lt;DRIVE1_04MA DRIVE_MASK&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			sd_clk_cfg_func: sd_clk_cfg_func {</div><div class='add'>+			sd_clk_cfg_func: sd-clk-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0xc    0x0	/* SD_CLK       (IOCFG003) */</div><div class='ctx'> 				&gt;;</div><div class='hunk'>@@ -305,7 +305,7 @@</div><div class='ctx'> 				pinctrl-single,bias-pullup    = &lt;PULL_DIS  PULL_UP   PULL_DIS  PULL_UP&gt;;</div><div class='ctx'> 				pinctrl-single,drive-strength = &lt;DRIVE1_10MA DRIVE_MASK&gt;;</div><div class='ctx'> 			};</div><div class='del'>-			sd_clk_cfg_idle: sd_clk_cfg_idle {</div><div class='add'>+			sd_clk_cfg_idle: sd-clk-cfg-idle-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0xc    0x0	/* SD_CLK       (IOCFG003) */</div><div class='ctx'> 				&gt;;</div><div class='hunk'>@@ -314,7 +314,7 @@</div><div class='ctx'> 				pinctrl-single,drive-strength = &lt;DRIVE1_02MA DRIVE_MASK&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			sd_cfg_func: sd_cfg_func {</div><div class='add'>+			sd_cfg_func: sd-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x10   0x0	/* SD_CMD       (IOCFG004) */</div><div class='ctx'> 					0x14   0x0	/* SD_DATA0     (IOCFG005) */</div><div class='hunk'>@@ -326,7 +326,7 @@</div><div class='ctx'> 				pinctrl-single,bias-pullup    = &lt;PULL_DIS  PULL_UP   PULL_DIS  PULL_UP&gt;;</div><div class='ctx'> 				pinctrl-single,drive-strength = &lt;DRIVE1_08MA DRIVE_MASK&gt;;</div><div class='ctx'> 			};</div><div class='del'>-			sd_cfg_idle: sd_cfg_idle {</div><div class='add'>+			sd_cfg_idle: sd-cfg-idle-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x10   0x0	/* SD_CMD       (IOCFG004) */</div><div class='ctx'> 					0x14   0x0	/* SD_DATA0     (IOCFG005) */</div><div class='hunk'>@@ -339,7 +339,7 @@</div><div class='ctx'> 				pinctrl-single,drive-strength = &lt;DRIVE1_02MA DRIVE_MASK&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			sdio_clk_cfg_func: sdio_clk_cfg_func {</div><div class='add'>+			sdio_clk_cfg_func: sdio-clk-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x134  0x0	/* SDIO_CLK     (IOCFG077) */</div><div class='ctx'> 				&gt;;</div><div class='hunk'>@@ -347,7 +347,7 @@</div><div class='ctx'> 				pinctrl-single,bias-pullup    = &lt;PULL_DIS  PULL_UP   PULL_DIS  PULL_UP&gt;;</div><div class='ctx'> 				pinctrl-single,drive-strength = &lt;DRIVE1_08MA DRIVE_MASK&gt;;</div><div class='ctx'> 			};</div><div class='del'>-			sdio_clk_cfg_idle: sdio_clk_cfg_idle {</div><div class='add'>+			sdio_clk_cfg_idle: sdio-clk-cfg-idle-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x134  0x0	/* SDIO_CLK     (IOCFG077) */</div><div class='ctx'> 				&gt;;</div><div class='hunk'>@@ -356,7 +356,7 @@</div><div class='ctx'> 				pinctrl-single,drive-strength = &lt;DRIVE1_02MA DRIVE_MASK&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			sdio_cfg_func: sdio_cfg_func {</div><div class='add'>+			sdio_cfg_func: sdio-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x138  0x0	/* SDIO_CMD     (IOCFG078) */</div><div class='ctx'> 					0x13c  0x0	/* SDIO_DATA0   (IOCFG079) */</div><div class='hunk'>@@ -368,7 +368,7 @@</div><div class='ctx'> 				pinctrl-single,bias-pullup    = &lt;PULL_UP   PULL_UP   PULL_DIS  PULL_UP&gt;;</div><div class='ctx'> 				pinctrl-single,drive-strength = &lt;DRIVE1_04MA DRIVE_MASK&gt;;</div><div class='ctx'> 			};</div><div class='del'>-			sdio_cfg_idle: sdio_cfg_idle {</div><div class='add'>+			sdio_cfg_idle: sdio-cfg-idle-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x138  0x0	/* SDIO_CMD     (IOCFG078) */</div><div class='ctx'> 					0x13c  0x0	/* SDIO_DATA0   (IOCFG079) */</div><div class='hunk'>@@ -381,7 +381,7 @@</div><div class='ctx'> 				pinctrl-single,drive-strength = &lt;DRIVE1_02MA DRIVE_MASK&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			isp_cfg_func1: isp_cfg_func1 {</div><div class='add'>+			isp_cfg_func1: isp-cfg-func1-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x28   0x0	/* ISP_PWDN0    (IOCFG010) */</div><div class='ctx'> 					0x2c   0x0	/* ISP_PWDN1    (IOCFG011) */</div><div class='hunk'>@@ -403,7 +403,7 @@</div><div class='ctx'> 				pinctrl-single,bias-pullup    = &lt;PULL_DIS  PULL_UP   PULL_DIS  PULL_UP&gt;;</div><div class='ctx'> 				pinctrl-single,drive-strength = &lt;DRIVE1_02MA DRIVE_MASK&gt;;</div><div class='ctx'> 			};</div><div class='del'>-			isp_cfg_idle1: isp_cfg_idle1 {</div><div class='add'>+			isp_cfg_idle1: isp-cfg-idle1-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x34   0x0	/* ISP_SHUTTER0 (IOCFG013) */</div><div class='ctx'> 					0x38   0x0	/* ISP_SHUTTER1 (IOCFG014) */</div><div class='hunk'>@@ -413,7 +413,7 @@</div><div class='ctx'> 				pinctrl-single,drive-strength = &lt;DRIVE1_02MA DRIVE_MASK&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			isp_cfg_func2: isp_cfg_func2 {</div><div class='add'>+			isp_cfg_func2: isp-cfg-func2-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x54   0x0	/* ISP_STROBE1  (IOCFG021) */</div><div class='ctx'> 				&gt;;</div><div class='hunk'>@@ -422,7 +422,7 @@</div><div class='ctx'> 				pinctrl-single,drive-strength = &lt;DRIVE1_02MA DRIVE_MASK&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			codec_clk_cfg_func: codec_clk_cfg_func {</div><div class='add'>+			codec_clk_cfg_func: codec-clk-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x70   0x0	/* CODEC_CLK    (IOCFG028) */</div><div class='ctx'> 				&gt;;</div><div class='hunk'>@@ -430,7 +430,7 @@</div><div class='ctx'> 				pinctrl-single,bias-pullup    = &lt;PULL_DIS  PULL_UP   PULL_DIS  PULL_UP&gt;;</div><div class='ctx'> 				pinctrl-single,drive-strength = &lt;DRIVE1_04MA DRIVE_MASK&gt;;</div><div class='ctx'> 			};</div><div class='del'>-			codec_clk_cfg_idle: codec_clk_cfg_idle {</div><div class='add'>+			codec_clk_cfg_idle: codec-clk-cfg-idle-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x70   0x0	/* CODEC_CLK    (IOCFG028) */</div><div class='ctx'> 				&gt;;</div><div class='hunk'>@@ -439,7 +439,7 @@</div><div class='ctx'> 				pinctrl-single,drive-strength = &lt;DRIVE1_02MA DRIVE_MASK&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			codec_cfg_func1: codec_cfg_func1 {</div><div class='add'>+			codec_cfg_func1: codec-cfg-func1-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x74   0x0	/* DMIC_CLK     (IOCFG029) */</div><div class='ctx'> 				&gt;;</div><div class='hunk'>@@ -448,7 +448,7 @@</div><div class='ctx'> 				pinctrl-single,drive-strength = &lt;DRIVE1_02MA DRIVE_MASK&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			codec_cfg_func2: codec_cfg_func2 {</div><div class='add'>+			codec_cfg_func2: codec-cfg-func2-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x78   0x0	/* CODEC_SYNC   (IOCFG030) */</div><div class='ctx'> 					0x7c   0x0	/* CODEC_DI     (IOCFG031) */</div><div class='hunk'>@@ -458,7 +458,7 @@</div><div class='ctx'> 				pinctrl-single,bias-pullup    = &lt;PULL_DIS  PULL_UP   PULL_DIS  PULL_UP&gt;;</div><div class='ctx'> 				pinctrl-single,drive-strength = &lt;DRIVE1_04MA DRIVE_MASK&gt;;</div><div class='ctx'> 			};</div><div class='del'>-			codec_cfg_idle2: codec_cfg_idle2 {</div><div class='add'>+			codec_cfg_idle2: codec-cfg-idle2-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x78   0x0	/* CODEC_SYNC   (IOCFG030) */</div><div class='ctx'> 					0x7c   0x0	/* CODEC_DI     (IOCFG031) */</div><div class='hunk'>@@ -469,7 +469,7 @@</div><div class='ctx'> 				pinctrl-single,drive-strength = &lt;DRIVE1_02MA DRIVE_MASK&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			fm_cfg_func: fm_cfg_func {</div><div class='add'>+			fm_cfg_func: fm-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x84   0x0	/* FM_XCLK      (IOCFG033) */</div><div class='ctx'> 					0x88   0x0	/* FM_XFS       (IOCFG034) */</div><div class='hunk'>@@ -481,7 +481,7 @@</div><div class='ctx'> 				pinctrl-single,drive-strength = &lt;DRIVE1_02MA DRIVE_MASK&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			bt_cfg_func: bt_cfg_func {</div><div class='add'>+			bt_cfg_func: bt-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x94   0x0	/* BT_XCLK      (IOCFG037) */</div><div class='ctx'> 					0x98   0x0	/* BT_XFS       (IOCFG038) */</div><div class='hunk'>@@ -492,7 +492,7 @@</div><div class='ctx'> 				pinctrl-single,bias-pullup    = &lt;PULL_DIS  PULL_UP   PULL_DIS  PULL_UP&gt;;</div><div class='ctx'> 				pinctrl-single,drive-strength = &lt;DRIVE1_02MA DRIVE_MASK&gt;;</div><div class='ctx'> 			};</div><div class='del'>-			bt_cfg_idle: bt_cfg_idle {</div><div class='add'>+			bt_cfg_idle: bt-cfg-idle-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x94   0x0	/* BT_XCLK      (IOCFG037) */</div><div class='ctx'> 					0x98   0x0	/* BT_XFS       (IOCFG038) */</div><div class='hunk'>@@ -504,7 +504,7 @@</div><div class='ctx'> 				pinctrl-single,drive-strength = &lt;DRIVE1_02MA DRIVE_MASK&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			pwm_in_cfg_func: pwm_in_cfg_func {</div><div class='add'>+			pwm_in_cfg_func: pwm-in-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0xbc   0x0	/* PWM_IN       (IOCFG047) */</div><div class='ctx'> 				&gt;;</div><div class='hunk'>@@ -513,7 +513,7 @@</div><div class='ctx'> 				pinctrl-single,drive-strength = &lt;DRIVE1_02MA DRIVE_MASK&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			bl_pwm_cfg_func: bl_pwm_cfg_func {</div><div class='add'>+			bl_pwm_cfg_func: bl-pwm-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0xc0   0x0	/* BL_PWM       (IOCFG048) */</div><div class='ctx'> 				&gt;;</div><div class='hunk'>@@ -522,7 +522,7 @@</div><div class='ctx'> 				pinctrl-single,drive-strength = &lt;DRIVE1_02MA DRIVE_MASK&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			uart0_cfg_func1: uart0_cfg_func1 {</div><div class='add'>+			uart0_cfg_func1: uart0-cfg-func1-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0xc4   0x0	/* UART0_RXD    (IOCFG049) */</div><div class='ctx'> 				&gt;;</div><div class='hunk'>@@ -531,7 +531,7 @@</div><div class='ctx'> 				pinctrl-single,drive-strength = &lt;DRIVE1_02MA DRIVE_MASK&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			uart0_cfg_func2: uart0_cfg_func2 {</div><div class='add'>+			uart0_cfg_func2: uart0-cfg-func2-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0xc8   0x0	/* UART0_TXD    (IOCFG050) */</div><div class='ctx'> 				&gt;;</div><div class='hunk'>@@ -540,7 +540,7 @@</div><div class='ctx'> 				pinctrl-single,drive-strength = &lt;DRIVE1_04MA DRIVE_MASK&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			uart1_cfg_func1: uart1_cfg_func1 {</div><div class='add'>+			uart1_cfg_func1: uart1-cfg-func1-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0xcc   0x0	/* UART1_CTS_N  (IOCFG051) */</div><div class='ctx'> 					0xd4   0x0	/* UART1_RXD    (IOCFG053) */</div><div class='hunk'>@@ -550,7 +550,7 @@</div><div class='ctx'> 				pinctrl-single,drive-strength = &lt;DRIVE1_02MA DRIVE_MASK&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			uart1_cfg_func2: uart1_cfg_func2 {</div><div class='add'>+			uart1_cfg_func2: uart1-cfg-func2-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0xd0   0x0	/* UART1_RTS_N  (IOCFG052) */</div><div class='ctx'> 					0xd8   0x0	/* UART1_TXD    (IOCFG054) */</div><div class='hunk'>@@ -560,7 +560,7 @@</div><div class='ctx'> 				pinctrl-single,drive-strength = &lt;DRIVE1_02MA DRIVE_MASK&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			uart2_cfg_func: uart2_cfg_func {</div><div class='add'>+			uart2_cfg_func: uart2-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0xdc   0x0	/* UART2_CTS_N  (IOCFG055) */</div><div class='ctx'> 					0xe0   0x0	/* UART2_RTS_N  (IOCFG056) */</div><div class='hunk'>@@ -572,7 +572,7 @@</div><div class='ctx'> 				pinctrl-single,drive-strength = &lt;DRIVE1_02MA DRIVE_MASK&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			uart3_cfg_func: uart3_cfg_func {</div><div class='add'>+			uart3_cfg_func: uart3-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x190  0x0	/* UART3_CTS_N  (IOCFG100) */</div><div class='ctx'> 					0x194  0x0	/* UART3_RTS_N  (IOCFG101) */</div><div class='hunk'>@@ -584,7 +584,7 @@</div><div class='ctx'> 				pinctrl-single,drive-strength = &lt;DRIVE1_02MA DRIVE_MASK&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			uart4_cfg_func: uart4_cfg_func {</div><div class='add'>+			uart4_cfg_func: uart4-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x1e0  0x0	/* UART4_CTS_N  (IOCFG120) */</div><div class='ctx'> 					0x1e4  0x0	/* UART4_RTS_N  (IOCFG121) */</div><div class='hunk'>@@ -596,7 +596,7 @@</div><div class='ctx'> 				pinctrl-single,drive-strength = &lt;DRIVE1_02MA DRIVE_MASK&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			uart5_cfg_func: uart5_cfg_func {</div><div class='add'>+			uart5_cfg_func: uart5-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x1d8  0x0	/* UART4_RXD    (IOCFG118) */</div><div class='ctx'> 					0x1dc  0x0	/* UART4_TXD    (IOCFG119) */</div><div class='hunk'>@@ -606,7 +606,7 @@</div><div class='ctx'> 				pinctrl-single,drive-strength = &lt;DRIVE1_02MA DRIVE_MASK&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			i2c0_cfg_func: i2c0_cfg_func {</div><div class='add'>+			i2c0_cfg_func: i2c0-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0xec   0x0	/* I2C0_SCL     (IOCFG059) */</div><div class='ctx'> 					0xf0   0x0	/* I2C0_SDA     (IOCFG060) */</div><div class='hunk'>@@ -616,7 +616,7 @@</div><div class='ctx'> 				pinctrl-single,drive-strength = &lt;DRIVE1_02MA DRIVE_MASK&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			i2c1_cfg_func: i2c1_cfg_func {</div><div class='add'>+			i2c1_cfg_func: i2c1-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0xf4   0x0	/* I2C1_SCL     (IOCFG061) */</div><div class='ctx'> 					0xf8   0x0	/* I2C1_SDA     (IOCFG062) */</div><div class='hunk'>@@ -626,7 +626,7 @@</div><div class='ctx'> 				pinctrl-single,drive-strength = &lt;DRIVE1_02MA DRIVE_MASK&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			i2c2_cfg_func: i2c2_cfg_func {</div><div class='add'>+			i2c2_cfg_func: i2c2-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0xfc   0x0	/* I2C2_SCL     (IOCFG063) */</div><div class='ctx'> 					0x100  0x0	/* I2C2_SDA     (IOCFG064) */</div><div class='hunk'>@@ -636,7 +636,7 @@</div><div class='ctx'> 				pinctrl-single,drive-strength = &lt;DRIVE1_02MA DRIVE_MASK&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			spi0_cfg_func: spi0_cfg_func {</div><div class='add'>+			spi0_cfg_func: spi0-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x1b0  0x0	/* SPI0_DI	(IOCFG108) */</div><div class='ctx'> 					0x1b4  0x0	/* SPI0_DO	(IOCFG109) */</div><div class='hunk'>@@ -656,7 +656,7 @@</div><div class='ctx'> 				&amp;rstout_n_cfg_func</div><div class='ctx'> 				&gt;;</div><div class='ctx'> </div><div class='del'>-			rstout_n_cfg_func: rstout_n_cfg_func {</div><div class='add'>+			rstout_n_cfg_func: rstout-n-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x0    0x0	/* RSTOUT_N     (IOCFG000) */</div><div class='ctx'> 				&gt;;</div><div class='hunk'>@@ -665,7 +665,7 @@</div><div class='ctx'> 				pinctrl-single,drive-strength = &lt;DRIVE1_02MA DRIVE_MASK&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			pmu_peri_en_cfg_func: pmu_peri_en_cfg_func {</div><div class='add'>+			pmu_peri_en_cfg_func: pmu-peri-en-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x4    0x0	/* PMU_PERI_EN  (IOCFG001) */</div><div class='ctx'> 				&gt;;</div><div class='hunk'>@@ -674,7 +674,7 @@</div><div class='ctx'> 				pinctrl-single,drive-strength = &lt;DRIVE1_02MA DRIVE_MASK&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			sysclk0_en_cfg_func: sysclk0_en_cfg_func {</div><div class='add'>+			sysclk0_en_cfg_func: sysclk0-en-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x8    0x0	/* SYSCLK0_EN   (IOCFG002) */</div><div class='ctx'> 				&gt;;</div><div class='hunk'>@@ -683,7 +683,7 @@</div><div class='ctx'> 				pinctrl-single,drive-strength = &lt;DRIVE1_02MA DRIVE_MASK&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			jtag_tdo_cfg_func: jtag_tdo_cfg_func {</div><div class='add'>+			jtag_tdo_cfg_func: jtag-tdo-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0xc    0x0	/* JTAG_TDO     (IOCFG003) */</div><div class='ctx'> 				&gt;;</div><div class='hunk'>@@ -692,7 +692,7 @@</div><div class='ctx'> 				pinctrl-single,drive-strength = &lt;DRIVE1_08MA DRIVE_MASK&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			rf_reset_cfg_func: rf_reset_cfg_func {</div><div class='add'>+			rf_reset_cfg_func: rf-reset-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x70   0x0	/* RF_RESET0    (IOCFG028) */</div><div class='ctx'> 					0x74   0x0	/* RF_RESET1    (IOCFG029) */</div><div class='head'>diff --git a/arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi b/arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi<br/>index d11efc81958c..b801a48041f9 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi</a></div><div class='hunk'>@@ -25,7 +25,7 @@</div><div class='ctx'> 				&amp;range 0 7 0</div><div class='ctx'> 				&amp;range 8 116 0&gt;;</div><div class='ctx'> </div><div class='del'>-			pmu_pmx_func: pmu_pmx_func {</div><div class='add'>+			pmu_pmx_func: pmu-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x008 MUX_M1 /* PMU1_SSI */</div><div class='ctx'> 					0x00c MUX_M1 /* PMU2_SSI */</div><div class='hunk'>@@ -34,19 +34,19 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			csi0_pwd_n_pmx_func: csi0_pwd_n_pmx_func {</div><div class='add'>+			csi0_pwd_n_pmx_func: csi0-pwd-n-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x044 MUX_M0 /* CSI0_PWD_N */</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			csi1_pwd_n_pmx_func: csi1_pwd_n_pmx_func {</div><div class='add'>+			csi1_pwd_n_pmx_func: csi1-pwd-n-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x04c MUX_M0 /* CSI1_PWD_N */</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			isp0_pmx_func: isp0_pmx_func {</div><div class='add'>+			isp0_pmx_func: isp0-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x058 MUX_M1 /* ISP_CLK0 */</div><div class='ctx'> 					0x064 MUX_M1 /* ISP_SCL0 */</div><div class='hunk'>@@ -54,7 +54,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			isp1_pmx_func: isp1_pmx_func {</div><div class='add'>+			isp1_pmx_func: isp1-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x05c MUX_M1 /* ISP_CLK1 */</div><div class='ctx'> 					0x06c MUX_M1 /* ISP_SCL1 */</div><div class='hunk'>@@ -62,47 +62,47 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			pwr_key_pmx_func: pwr_key_pmx_func {</div><div class='add'>+			pwr_key_pmx_func: pwr-key-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x080 MUX_M0 /* GPIO_034 */</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			i2c3_pmx_func: i2c3_pmx_func {</div><div class='add'>+			i2c3_pmx_func: i2c3-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x02c MUX_M1 /* I2C3_SCL */</div><div class='ctx'> 					0x030 MUX_M1 /* I2C3_SDA */</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			i2c4_pmx_func: i2c4_pmx_func {</div><div class='add'>+			i2c4_pmx_func: i2c4-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x090 MUX_M1 /* I2C4_SCL */</div><div class='ctx'> 					0x094 MUX_M1 /* I2C4_SDA */</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			pcie_perstn_pmx_func: pcie_perstn_pmx_func {</div><div class='add'>+			pcie_perstn_pmx_func: pcie-perstn-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x15c MUX_M1 /* PCIE_PERST_N */</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			usbhub5734_pmx_func: usbhub5734_pmx_func {</div><div class='add'>+			usbhub5734_pmx_func: usbhub5734-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x11c MUX_M0 /* GPIO_073 */</div><div class='ctx'> 					0x120 MUX_M0 /* GPIO_074 */</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			uart0_pmx_func: uart0_pmx_func {</div><div class='add'>+			uart0_pmx_func: uart0-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x0cc MUX_M2 /* UART0_RXD */</div><div class='ctx'> 					0x0d0 MUX_M2 /* UART0_TXD */</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			uart1_pmx_func: uart1_pmx_func {</div><div class='add'>+			uart1_pmx_func: uart1-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x0b0 MUX_M2 /* UART1_CTS_N */</div><div class='ctx'> 					0x0b4 MUX_M2 /* UART1_RTS_N */</div><div class='hunk'>@@ -111,7 +111,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			uart2_pmx_func: uart2_pmx_func {</div><div class='add'>+			uart2_pmx_func: uart2-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x0bc MUX_M2 /* UART2_CTS_N */</div><div class='ctx'> 					0x0c0 MUX_M2 /* UART2_RTS_N */</div><div class='hunk'>@@ -120,7 +120,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			uart3_pmx_func: uart3_pmx_func {</div><div class='add'>+			uart3_pmx_func: uart3-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x0dc MUX_M1 /* UART3_CTS_N */</div><div class='ctx'> 					0x0e0 MUX_M1 /* UART3_RTS_N */</div><div class='hunk'>@@ -129,7 +129,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			uart4_pmx_func: uart4_pmx_func {</div><div class='add'>+			uart4_pmx_func: uart4-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x0ec MUX_M1 /* UART4_CTS_N */</div><div class='ctx'> 					0x0f0 MUX_M1 /* UART4_RTS_N */</div><div class='hunk'>@@ -138,7 +138,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			uart5_pmx_func: uart5_pmx_func {</div><div class='add'>+			uart5_pmx_func: uart5-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x0c4 MUX_M3 /* UART5_CTS_N */</div><div class='ctx'> 					0x0c8 MUX_M3 /* UART5_RTS_N */</div><div class='hunk'>@@ -147,7 +147,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			uart6_pmx_func: uart6_pmx_func {</div><div class='add'>+			uart6_pmx_func: uart6-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x0cc MUX_M1 /* UART6_CTS_N */</div><div class='ctx'> 					0x0d0 MUX_M1 /* UART6_RTS_N */</div><div class='hunk'>@@ -156,13 +156,13 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			cam0_rst_pmx_func: cam0_rst_pmx_func {</div><div class='add'>+			cam0_rst_pmx_func: cam0-rst-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x0c8 MUX_M0 /* CAM0_RST */</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			cam1_rst_pmx_func: cam1_rst_pmx_func {</div><div class='add'>+			cam1_rst_pmx_func: cam1-rst-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x124 MUX_M0 /* CAM1_RST */</div><div class='ctx'> 				&gt;;</div><div class='hunk'>@@ -180,7 +180,7 @@</div><div class='ctx'> 			/* pin base, nr pins &amp; gpio function */</div><div class='ctx'> 			pinctrl-single,gpio-range = &lt;&amp;range 0 6 0&gt;;</div><div class='ctx'> </div><div class='del'>-			sd_pmx_func: sd_pmx_func {</div><div class='add'>+			sd_pmx_func: sd-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x000 MUX_M1 /* SD_CLK */</div><div class='ctx'> 					0x004 MUX_M1 /* SD_CMD */</div><div class='hunk'>@@ -203,14 +203,14 @@</div><div class='ctx'> 			/* pin base, nr pins &amp; gpio function */</div><div class='ctx'> 			pinctrl-single,gpio-range = &lt;&amp;range 0 12 0&gt;;</div><div class='ctx'> </div><div class='del'>-			ufs_pmx_func: ufs_pmx_func {</div><div class='add'>+			ufs_pmx_func: ufs-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x000 MUX_M1 /* UFS_REF_CLK */</div><div class='ctx'> 					0x004 MUX_M1 /* UFS_RST_N */</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			spi3_pmx_func: spi3_pmx_func {</div><div class='add'>+			spi3_pmx_func: spi3-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x008 MUX_M1 /* SPI3_CLK */</div><div class='ctx'> 					0x00c MUX_M1 /* SPI3_DI */</div><div class='hunk'>@@ -231,7 +231,7 @@</div><div class='ctx'> 			/* pin base, nr pins &amp; gpio function */</div><div class='ctx'> 			pinctrl-single,gpio-range = &lt;&amp;range 0 6 0&gt;;</div><div class='ctx'> </div><div class='del'>-			sdio_pmx_func: sdio_pmx_func {</div><div class='add'>+			sdio_pmx_func: sdio-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x000 MUX_M1 /* SDIO_CLK */</div><div class='ctx'> 					0x004 MUX_M1 /* SDIO_CMD */</div><div class='hunk'>@@ -254,7 +254,7 @@</div><div class='ctx'> 			/* pin base in node, nr pins &amp; gpio function */</div><div class='ctx'> 			pinctrl-single,gpio-range = &lt;&amp;range 0 42 0&gt;;</div><div class='ctx'> </div><div class='del'>-			i2s2_pmx_func: i2s2_pmx_func {</div><div class='add'>+			i2s2_pmx_func: i2s2-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x044 MUX_M1 /* I2S2_DI */</div><div class='ctx'> 					0x048 MUX_M1 /* I2S2_DO */</div><div class='hunk'>@@ -263,42 +263,42 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			slimbus_pmx_func: slimbus_pmx_func {</div><div class='add'>+			slimbus_pmx_func: slimbus-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x02c MUX_M1 /* SLIMBUS_CLK */</div><div class='ctx'> 					0x030 MUX_M1 /* SLIMBUS_DATA */</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			i2c0_pmx_func: i2c0_pmx_func {</div><div class='add'>+			i2c0_pmx_func: i2c0-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x014 MUX_M1 /* I2C0_SCL */</div><div class='ctx'> 					0x018 MUX_M1 /* I2C0_SDA */</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			i2c1_pmx_func: i2c1_pmx_func {</div><div class='add'>+			i2c1_pmx_func: i2c1-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x01c MUX_M1 /* I2C1_SCL */</div><div class='ctx'> 					0x020 MUX_M1 /* I2C1_SDA */</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			i2c7_pmx_func: i2c7_pmx_func {</div><div class='add'>+			i2c7_pmx_func: i2c7-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x024 MUX_M3 /* I2C7_SCL */</div><div class='ctx'> 					0x028 MUX_M3 /* I2C7_SDA */</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			pcie_pmx_func: pcie_pmx_func {</div><div class='add'>+			pcie_pmx_func: pcie-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x084 MUX_M1 /* PCIE_CLKREQ_N */</div><div class='ctx'> 					0x088 MUX_M1 /* PCIE_WAKE_N */</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			spi2_pmx_func: spi2_pmx_func {</div><div class='add'>+			spi2_pmx_func: spi2-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x08c MUX_M1 /* SPI2_CLK */</div><div class='ctx'> 					0x090 MUX_M1 /* SPI2_DI */</div><div class='hunk'>@@ -307,7 +307,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			i2s0_pmx_func: i2s0_pmx_func {</div><div class='add'>+			i2s0_pmx_func: i2s0-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x034 MUX_M1 /* I2S0_DI */</div><div class='ctx'> 					0x038 MUX_M1 /* I2S0_DO */</div><div class='hunk'>@@ -323,7 +323,7 @@</div><div class='ctx'> 			#pinctrl-cells = &lt;1&gt;;</div><div class='ctx'> 			pinctrl-single,register-width = &lt;0x20&gt;;</div><div class='ctx'> </div><div class='del'>-			pmu_cfg_func: pmu_cfg_func {</div><div class='add'>+			pmu_cfg_func: pmu-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x010 0x0 /* PMU1_SSI */</div><div class='ctx'> 					0x014 0x0 /* PMU2_SSI */</div><div class='hunk'>@@ -347,7 +347,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			i2c3_cfg_func: i2c3_cfg_func {</div><div class='add'>+			i2c3_cfg_func: i2c3-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x038 0x0 /* I2C3_SCL */</div><div class='ctx'> 					0x03c 0x0 /* I2C3_SDA */</div><div class='hunk'>@@ -369,7 +369,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			csi0_pwd_n_cfg_func: csi0_pwd_n_cfg_func {</div><div class='add'>+			csi0_pwd_n_cfg_func: csi0-pwd-n-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x050 0x0 /* CSI0_PWD_N */</div><div class='ctx'> 				&gt;;</div><div class='hunk'>@@ -390,7 +390,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			csi1_pwd_n_cfg_func: csi1_pwd_n_cfg_func {</div><div class='add'>+			csi1_pwd_n_cfg_func: csi1-pwd-n-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x058 0x0 /* CSI1_PWD_N */</div><div class='ctx'> 				&gt;;</div><div class='hunk'>@@ -411,7 +411,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			isp0_cfg_func: isp0_cfg_func {</div><div class='add'>+			isp0_cfg_func: isp0-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x064 0x0 /* ISP_CLK0 */</div><div class='ctx'> 					0x070 0x0 /* ISP_SCL0 */</div><div class='hunk'>@@ -433,7 +433,7 @@</div><div class='ctx'> 					DRIVE7_04MA DRIVE6_MASK&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			isp1_cfg_func: isp1_cfg_func {</div><div class='add'>+			isp1_cfg_func: isp1-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x068 0x0 /* ISP_CLK1 */</div><div class='ctx'> 					0x078 0x0 /* ISP_SCL1 */</div><div class='hunk'>@@ -456,7 +456,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			pwr_key_cfg_func: pwr_key_cfg_func {</div><div class='add'>+			pwr_key_cfg_func: pwr-key-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x08c 0x0 /* GPIO_034 */</div><div class='ctx'> 				&gt;;</div><div class='hunk'>@@ -477,7 +477,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			uart1_cfg_func: uart1_cfg_func {</div><div class='add'>+			uart1_cfg_func: uart1-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x0b4 0x0 /* UART1_RXD */</div><div class='ctx'> 					0x0b8 0x0 /* UART1_TXD */</div><div class='hunk'>@@ -501,7 +501,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			uart2_cfg_func: uart2_cfg_func {</div><div class='add'>+			uart2_cfg_func: uart2-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x0c8 0x0 /* UART2_CTS_N */</div><div class='ctx'> 					0x0cc 0x0 /* UART2_RTS_N */</div><div class='hunk'>@@ -525,7 +525,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			uart5_cfg_func: uart5_cfg_func {</div><div class='add'>+			uart5_cfg_func: uart5-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x0c8 0x0 /* UART5_RXD */</div><div class='ctx'> 					0x0cc 0x0 /* UART5_TXD */</div><div class='hunk'>@@ -549,7 +549,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			cam0_rst_cfg_func: cam0_rst_cfg_func {</div><div class='add'>+			cam0_rst_cfg_func: cam0-rst-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x0d4 0x0 /* CAM0_RST */</div><div class='ctx'> 				&gt;;</div><div class='hunk'>@@ -570,7 +570,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			uart0_cfg_func: uart0_cfg_func {</div><div class='add'>+			uart0_cfg_func: uart0-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x0d8 0x0 /* UART0_RXD */</div><div class='ctx'> 					0x0dc 0x0 /* UART0_TXD */</div><div class='hunk'>@@ -592,7 +592,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			uart6_cfg_func: uart6_cfg_func {</div><div class='add'>+			uart6_cfg_func: uart6-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x0d8 0x0 /* UART6_CTS_N */</div><div class='ctx'> 					0x0dc 0x0 /* UART6_RTS_N */</div><div class='hunk'>@@ -616,7 +616,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			uart3_cfg_func: uart3_cfg_func {</div><div class='add'>+			uart3_cfg_func: uart3-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x0e8 0x0 /* UART3_CTS_N */</div><div class='ctx'> 					0x0ec 0x0 /* UART3_RTS_N */</div><div class='hunk'>@@ -640,7 +640,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			uart4_cfg_func: uart4_cfg_func {</div><div class='add'>+			uart4_cfg_func: uart4-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x0f8 0x0 /* UART4_CTS_N */</div><div class='ctx'> 					0x0fc 0x0 /* UART4_RTS_N */</div><div class='hunk'>@@ -664,7 +664,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			cam1_rst_cfg_func: cam1_rst_cfg_func {</div><div class='add'>+			cam1_rst_cfg_func: cam1-rst-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x130 0x0 /* CAM1_RST */</div><div class='ctx'> 				&gt;;</div><div class='hunk'>@@ -692,7 +692,7 @@</div><div class='ctx'> 			#pinctrl-cells = &lt;1&gt;;</div><div class='ctx'> 			pinctrl-single,register-width = &lt;0x20&gt;;</div><div class='ctx'> </div><div class='del'>-			ufs_cfg_func: ufs_cfg_func {</div><div class='add'>+			ufs_cfg_func: ufs-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x000 0x0 /* UFS_REF_CLK */</div><div class='ctx'> 					0x004 0x0 /* UFS_RST_N */</div><div class='hunk'>@@ -714,10 +714,10 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			spi3_cfg_func: spi3_cfg_func {</div><div class='add'>+			spi3_cfg_func: spi3-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x008 0x0 /* SPI3_CLK */</div><div class='del'>-					0x0 /* SPI3_DI */</div><div class='add'>+					0x00c 0x0 /* SPI3_DI */</div><div class='ctx'> 					0x010 0x0 /* SPI3_DO */</div><div class='ctx'> 					0x014 0x0 /* SPI3_CS0_N */</div><div class='ctx'> 				&gt;;</div><div class='hunk'>@@ -734,7 +734,7 @@</div><div class='ctx'> 					PULL_UP</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 				pinctrl-single,drive-strength = &lt;</div><div class='del'>-					DRIVE7_02MA DRIVE6_MASK</div><div class='add'>+					DRIVE7_06MA DRIVE6_MASK</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='hunk'>@@ -745,7 +745,7 @@</div><div class='ctx'> 			#pinctrl-cells = &lt;1&gt;;</div><div class='ctx'> 			pinctrl-single,register-width = &lt;0x20&gt;;</div><div class='ctx'> </div><div class='del'>-			sdio_clk_cfg_func: sdio_clk_cfg_func {</div><div class='add'>+			sdio_clk_cfg_func: sdio-clk-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x000 0x0 /* SDIO_CLK */</div><div class='ctx'> 				&gt;;</div><div class='hunk'>@@ -766,7 +766,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			sdio_cfg_func: sdio_cfg_func {</div><div class='add'>+			sdio_cfg_func: sdio-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x004 0x0 /* SDIO_CMD */</div><div class='ctx'> 					0x008 0x0 /* SDIO_DATA0 */</div><div class='hunk'>@@ -798,7 +798,7 @@</div><div class='ctx'> 			#pinctrl-cells = &lt;1&gt;;</div><div class='ctx'> 			pinctrl-single,register-width = &lt;0x20&gt;;</div><div class='ctx'> </div><div class='del'>-			sd_clk_cfg_func: sd_clk_cfg_func {</div><div class='add'>+			sd_clk_cfg_func: sd-clk-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x000 0x0 /* SD_CLK */</div><div class='ctx'> 				&gt;;</div><div class='hunk'>@@ -820,7 +820,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			sd_cfg_func: sd_cfg_func {</div><div class='add'>+			sd_cfg_func: sd-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x004 0x0 /* SD_CMD */</div><div class='ctx'> 					0x008 0x0 /* SD_DATA0 */</div><div class='hunk'>@@ -853,7 +853,7 @@</div><div class='ctx'> 			#pinctrl-cells = &lt;1&gt;;</div><div class='ctx'> 			pinctrl-single,register-width = &lt;0x20&gt;;</div><div class='ctx'> </div><div class='del'>-			i2c0_cfg_func: i2c0_cfg_func {</div><div class='add'>+			i2c0_cfg_func: i2c0-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x01c 0x0 /* I2C0_SCL */</div><div class='ctx'> 					0x020 0x0 /* I2C0_SDA */</div><div class='hunk'>@@ -875,7 +875,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			i2c1_cfg_func: i2c1_cfg_func {</div><div class='add'>+			i2c1_cfg_func: i2c1-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x024 0x0 /* I2C1_SCL */</div><div class='ctx'> 					0x028 0x0 /* I2C1_SDA */</div><div class='hunk'>@@ -897,7 +897,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			i2c7_cfg_func: i2c7_cfg_func {</div><div class='add'>+			i2c7_cfg_func: i2c7-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x02c 0x0 /* I2C7_SCL */</div><div class='ctx'> 					0x030 0x0 /* I2C7_SDA */</div><div class='hunk'>@@ -919,7 +919,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			slimbus_cfg_func: slimbus_cfg_func {</div><div class='add'>+			slimbus_cfg_func: slimbus-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x034 0x0 /* SLIMBUS_CLK */</div><div class='ctx'> 					0x038 0x0 /* SLIMBUS_DATA */</div><div class='hunk'>@@ -941,7 +941,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			i2s0_cfg_func: i2s0_cfg_func {</div><div class='add'>+			i2s0_cfg_func: i2s0-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x040 0x0 /* I2S0_DI */</div><div class='ctx'> 					0x044 0x0 /* I2S0_DO */</div><div class='hunk'>@@ -965,7 +965,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			i2s2_cfg_func: i2s2_cfg_func {</div><div class='add'>+			i2s2_cfg_func: i2s2-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x050 0x0 /* I2S2_DI */</div><div class='ctx'> 					0x054 0x0 /* I2S2_DO */</div><div class='hunk'>@@ -989,7 +989,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			pcie_cfg_func: pcie_cfg_func {</div><div class='add'>+			pcie_cfg_func: pcie-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x094 0x0 /* PCIE_CLKREQ_N */</div><div class='ctx'> 					0x098 0x0 /* PCIE_WAKE_N */</div><div class='hunk'>@@ -1011,7 +1011,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			spi2_cfg_func: spi2_cfg_func {</div><div class='add'>+			spi2_cfg_func: spi2-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x09c 0x0 /* SPI2_CLK */</div><div class='ctx'> 					0x0a0 0x0 /* SPI2_DI */</div><div class='hunk'>@@ -1031,11 +1031,11 @@</div><div class='ctx'> 					PULL_UP</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 				pinctrl-single,drive-strength = &lt;</div><div class='del'>-					DRIVE7_02MA DRIVE6_MASK</div><div class='add'>+					DRIVE7_06MA DRIVE6_MASK</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			usb_cfg_func: usb_cfg_func {</div><div class='add'>+			usb_cfg_func: usb-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x0ac 0x0 /* GPIO_219 */</div><div class='ctx'> 				&gt;;</div><div class='head'>diff --git a/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi b/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi<br/>index d456b0aa6f58..8f7bf80e6ece 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi</a></div><div class='hunk'>@@ -21,14 +21,14 @@</div><div class='ctx'> 			/* pin base, nr pins &amp; gpio function */</div><div class='ctx'> 			pinctrl-single,gpio-range = &lt;&amp;range 0 82 0&gt;;</div><div class='ctx'> </div><div class='del'>-			uart0_pmx_func: uart0_pmx_func {</div><div class='add'>+			uart0_pmx_func: uart0-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x054 MUX_M2 /* UART0_RXD */</div><div class='ctx'> 					0x058 MUX_M2 /* UART0_TXD */</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			uart2_pmx_func: uart2_pmx_func {</div><div class='add'>+			uart2_pmx_func: uart2-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x700 MUX_M2 /* UART2_CTS_N */</div><div class='ctx'> 					0x704 MUX_M2 /* UART2_RTS_N */</div><div class='hunk'>@@ -37,7 +37,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			uart3_pmx_func: uart3_pmx_func {</div><div class='add'>+			uart3_pmx_func: uart3-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x064 MUX_M1 /* UART3_CTS_N */</div><div class='ctx'> 					0x068 MUX_M1 /* UART3_RTS_N */</div><div class='hunk'>@@ -46,7 +46,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			uart4_pmx_func: uart4_pmx_func {</div><div class='add'>+			uart4_pmx_func: uart4-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x074 MUX_M1 /* UART4_CTS_N */</div><div class='ctx'> 					0x078 MUX_M1 /* UART4_RTS_N */</div><div class='hunk'>@@ -55,12 +55,159 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			uart6_pmx_func: uart6_pmx_func {</div><div class='add'>+			uart6_pmx_func: uart6-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x05c MUX_M1 /* UART6_RXD */</div><div class='ctx'> 					0x060 MUX_M1 /* UART6_TXD */</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='add'>+</div><div class='add'>+			i2c3_pmx_func: i2c3-pins {</div><div class='add'>+				pinctrl-single,pins = &lt;</div><div class='add'>+					0x010 MUX_M1 /* I2C3_SCL */</div><div class='add'>+					0x014 MUX_M1 /* I2C3_SDA */</div><div class='add'>+				&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c4_pmx_func: i2c4-pins {</div><div class='add'>+				pinctrl-single,pins = &lt;</div><div class='add'>+					0x03c MUX_M1 /* I2C4_SCL */</div><div class='add'>+					0x040 MUX_M1 /* I2C4_SDA */</div><div class='add'>+				&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cam0_rst_pmx_func: cam0-rst-pins {</div><div class='add'>+				pinctrl-single,pins = &lt;</div><div class='add'>+					0x714 MUX_M0 /* CAM0_RST */</div><div class='add'>+				&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cam1_rst_pmx_func: cam1-rst-pins {</div><div class='add'>+				pinctrl-single,pins = &lt;</div><div class='add'>+					0x048 MUX_M0 /* CAM1_RST */</div><div class='add'>+				&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cam0_pwd_n_pmx_func: cam0-pwd-n-pins {</div><div class='add'>+				pinctrl-single,pins = &lt;</div><div class='add'>+					0x098 MUX_M0 /* CAM0_PWD_N */</div><div class='add'>+				&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cam1_pwd_n_pmx_func: cam1-pwd-n-pins {</div><div class='add'>+				pinctrl-single,pins = &lt;</div><div class='add'>+					0x044 MUX_M0 /* CAM1_PWD_N */</div><div class='add'>+				&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			isp0_pmx_func: isp0-pins {</div><div class='add'>+				pinctrl-single,pins = &lt;</div><div class='add'>+					0x018 MUX_M1 /* ISP_CLK0 */</div><div class='add'>+					0x024 MUX_M1 /* ISP_SCL0 */</div><div class='add'>+					0x028 MUX_M1 /* ISP_SDA0 */</div><div class='add'>+				&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			isp1_pmx_func: isp1-pins {</div><div class='add'>+				pinctrl-single,pins = &lt;</div><div class='add'>+					0x01c MUX_M1 /* ISP_CLK1 */</div><div class='add'>+					0x02c MUX_M1 /* ISP_SCL1 */</div><div class='add'>+					0x030 MUX_M1 /* ISP_SDA1 */</div><div class='add'>+				&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmx1: pinmux@fff11000 {</div><div class='add'>+			compatible = "pinctrl-single";</div><div class='add'>+			reg = &lt;0x0 0xfff11000 0x0 0x73c&gt;;</div><div class='add'>+			#gpio-range-cells = &lt;0x3&gt;;</div><div class='add'>+			#pinctrl-cells = &lt;1&gt;;</div><div class='add'>+			pinctrl-single,register-width = &lt;0x20&gt;;</div><div class='add'>+			pinctrl-single,function-mask = &lt;0x7&gt;;</div><div class='add'>+			/* pin base, nr pins &amp; gpio function */</div><div class='add'>+			pinctrl-single,gpio-range = &lt;&amp;range 0 46 0&gt;;</div><div class='add'>+</div><div class='add'>+			pwr_key_pmx_func: pwr-key-pins {</div><div class='add'>+				pinctrl-single,pins = &lt;</div><div class='add'>+					0x064 MUX_M0 /* GPIO_203 */</div><div class='add'>+				&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pd_pmx_func: pd-pins {</div><div class='add'>+				pinctrl-single,pins = &lt;</div><div class='add'>+					0x080 MUX_M0 /* GPIO_221 */</div><div class='add'>+				&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2s2_pmx_func: i2s2-pins {</div><div class='add'>+			    pinctrl-single,pins = &lt;</div><div class='add'>+					0x050 MUX_M1 /* I2S2_DI */</div><div class='add'>+					0x054 MUX_M1 /* I2S2_DO */</div><div class='add'>+					0x058 MUX_M1 /* I2S2_XCLK */</div><div class='add'>+					0x05c MUX_M1 /* I2S2_XFS */</div><div class='add'>+			    &gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi0_pmx_func: spi0-pins {</div><div class='add'>+				pinctrl-single,pins = &lt;</div><div class='add'>+					0x094 MUX_M1 /* SPI0_CLK */</div><div class='add'>+					0x098 MUX_M1 /* SPI0_DI */</div><div class='add'>+					0x09c MUX_M1 /* SPI0_DO */</div><div class='add'>+					0x0a0 MUX_M1 /* SPI0_CS0_N */</div><div class='add'>+				&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi2_pmx_func: spi2-pins {</div><div class='add'>+				pinctrl-single,pins = &lt;</div><div class='add'>+					0x710 MUX_M1 /* SPI2_CLK */</div><div class='add'>+					0x714 MUX_M1 /* SPI2_DI */</div><div class='add'>+					0x718 MUX_M1 /* SPI2_DO */</div><div class='add'>+					0x71c MUX_M1 /* SPI2_CS0_N */</div><div class='add'>+				&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi3_pmx_func: spi3-pins {</div><div class='add'>+				pinctrl-single,pins = &lt;</div><div class='add'>+					0x72c MUX_M1 /* SPI3_CLK */</div><div class='add'>+					0x730 MUX_M1 /* SPI3_DI */</div><div class='add'>+					0x734 MUX_M1 /* SPI3_DO */</div><div class='add'>+					0x738 MUX_M1 /* SPI3_CS0_N */</div><div class='add'>+				&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c0_pmx_func: i2c0-pins {</div><div class='add'>+				pinctrl-single,pins = &lt;</div><div class='add'>+					0x020 MUX_M1 /* I2C0_SCL */</div><div class='add'>+					0x024 MUX_M1 /* I2C0_SDA */</div><div class='add'>+				&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c1_pmx_func: i2c1-pins {</div><div class='add'>+				pinctrl-single,pins = &lt;</div><div class='add'>+					0x028 MUX_M1 /* I2C1_SCL */</div><div class='add'>+					0x02c MUX_M1 /* I2C1_SDA */</div><div class='add'>+				&gt;;</div><div class='add'>+			};</div><div class='add'>+			i2c2_pmx_func: i2c2-pins {</div><div class='add'>+				pinctrl-single,pins = &lt;</div><div class='add'>+					0x030 MUX_M1 /* I2C2_SCL */</div><div class='add'>+					0x034 MUX_M1 /* I2C2_SDA */</div><div class='add'>+				&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pcie_clkreq_pmx_func: pcie-clkreq-pins {</div><div class='add'>+				pinctrl-single,pins = &lt;</div><div class='add'>+					0x084 MUX_M1 /* PCIE0_CLKREQ_N */</div><div class='add'>+				&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gpio185_pmx_func: gpio185-pins {</div><div class='add'>+				pinctrl-single,pins = &lt;0x01C    0x1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gpio185_pmx_idle: gpio185-idle-pins {</div><div class='add'>+				pinctrl-single,pins = &lt;0x01C    0x0&gt;;</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		pmx2: pinmux@e896c800 {</div><div class='hunk'>@@ -69,7 +216,7 @@</div><div class='ctx'> 			#pinctrl-cells = &lt;1&gt;;</div><div class='ctx'> 			pinctrl-single,register-width = &lt;0x20&gt;;</div><div class='ctx'> </div><div class='del'>-			uart0_cfg_func: uart0_cfg_func {</div><div class='add'>+			uart0_cfg_func: uart0-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x058 0x0 /* UART0_RXD */</div><div class='ctx'> 					0x05c 0x0 /* UART0_TXD */</div><div class='hunk'>@@ -91,7 +238,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			uart2_cfg_func: uart2_cfg_func {</div><div class='add'>+			uart2_cfg_func: uart2-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x700 0x0 /* UART2_CTS_N */</div><div class='ctx'> 					0x704 0x0 /* UART2_RTS_N */</div><div class='hunk'>@@ -115,7 +262,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			uart3_cfg_func: uart3_cfg_func {</div><div class='add'>+			uart3_cfg_func: uart3-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x068 0x0 /* UART3_CTS_N */</div><div class='ctx'> 					0x06c 0x0 /* UART3_RTS_N */</div><div class='hunk'>@@ -139,7 +286,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			uart4_cfg_func: uart4_cfg_func {</div><div class='add'>+			uart4_cfg_func: uart4-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x078 0x0 /* UART4_CTS_N */</div><div class='ctx'> 					0x07c 0x0 /* UART4_RTS_N */</div><div class='hunk'>@@ -163,7 +310,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			uart6_cfg_func: uart6_cfg_func {</div><div class='add'>+			uart6_cfg_func: uart6-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x060 0x0 /* UART6_RXD */</div><div class='ctx'> 					0x064 0x0 /* UART6_TXD */</div><div class='hunk'>@@ -184,6 +331,180 @@</div><div class='ctx'> 					DRIVE7_02MA DRIVE6_MASK</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='add'>+</div><div class='add'>+			i2c3_cfg_func: i2c3-cfg-pins {</div><div class='add'>+				pinctrl-single,pins = &lt;</div><div class='add'>+					0x014 0x0 /* I2C3_SCL */</div><div class='add'>+					0x018 0x0 /* I2C3_SDA */</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,bias-pulldown = &lt;</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_DOWN</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_DOWN</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,bias-pullup = &lt;</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_UP</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_UP</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,drive-strength = &lt;</div><div class='add'>+					DRIVE7_04MA DRIVE6_MASK</div><div class='add'>+				&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c4_cfg_func: i2c4-cfg-pins {</div><div class='add'>+				pinctrl-single,pins = &lt;</div><div class='add'>+					0x040 0x0 /* I2C4_SCL */</div><div class='add'>+					0x044 0x0 /* I2C4_SDA */</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,bias-pulldown = &lt;</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_DOWN</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_DOWN</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,bias-pullup = &lt;</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_UP</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_UP</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,drive-strength = &lt;</div><div class='add'>+					DRIVE7_04MA DRIVE6_MASK</div><div class='add'>+				&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cam0_rst_cfg_func: cam0-rst-cfg-pins {</div><div class='add'>+				pinctrl-single,pins = &lt;</div><div class='add'>+					0x714 0x0 /* CAM0_RST */</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,bias-pulldown = &lt;</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_DOWN</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_DOWN</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,bias-pullup = &lt;</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_UP</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_UP</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,drive-strength = &lt;</div><div class='add'>+					DRIVE7_04MA DRIVE6_MASK</div><div class='add'>+				&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cam1_rst_cfg_func: cam1-rst-cfg-pins {</div><div class='add'>+				pinctrl-single,pins = &lt;</div><div class='add'>+					0x04C 0x0 /* CAM1_RST */</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,bias-pulldown = &lt;</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_DOWN</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_DOWN</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,bias-pullup = &lt;</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_UP</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_UP</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,drive-strength = &lt;</div><div class='add'>+					DRIVE7_04MA DRIVE6_MASK</div><div class='add'>+				&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cam0_pwd_n_cfg_func: cam0-pwd-n-cfg-pins {</div><div class='add'>+				pinctrl-single,pins = &lt;</div><div class='add'>+					0x09C 0x0 /* CAM0_PWD_N */</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,bias-pulldown = &lt;</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_DOWN</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_DOWN</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,bias-pullup = &lt;</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_UP</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_UP</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,drive-strength = &lt;</div><div class='add'>+					DRIVE7_04MA DRIVE6_MASK</div><div class='add'>+				&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cam1_pwd_n_cfg_func: cam1-pwd-n-cfg-pins {</div><div class='add'>+				pinctrl-single,pins = &lt;</div><div class='add'>+					0x048 0x0 /* CAM1_PWD_N */</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,bias-pulldown = &lt;</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_DOWN</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_DOWN</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,bias-pullup = &lt;</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_UP</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_UP</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,drive-strength = &lt;</div><div class='add'>+					DRIVE7_04MA DRIVE6_MASK</div><div class='add'>+				&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			isp0_cfg_func: isp0-cfg-pins {</div><div class='add'>+				pinctrl-single,pins = &lt;</div><div class='add'>+					0x01C 0x0 /* ISP_CLK0 */</div><div class='add'>+					0x028 0x0 /* ISP_SCL0 */</div><div class='add'>+					0x02C 0x0 /* ISP_SDA0 */</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,bias-pulldown = &lt;</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_DOWN</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_DOWN</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,bias-pullup = &lt;</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_UP</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_UP</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,drive-strength = &lt;</div><div class='add'>+					DRIVE7_04MA DRIVE6_MASK</div><div class='add'>+				&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			isp1_cfg_func: isp1-cfg-pins {</div><div class='add'>+				pinctrl-single,pins = &lt;</div><div class='add'>+					0x020 0x0 /* ISP_CLK1 */</div><div class='add'>+					0x030 0x0 /* ISP_SCL1 */</div><div class='add'>+					0x034 0x0 /* ISP_SDA1 */</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,bias-pulldown = &lt;</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_DOWN</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_DOWN</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,bias-pullup = &lt;</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_UP</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_UP</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,drive-strength = &lt;</div><div class='add'>+					DRIVE7_04MA DRIVE6_MASK</div><div class='add'>+				&gt;;</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		pmx5: pinmux@fc182000 {</div><div class='hunk'>@@ -196,7 +517,7 @@</div><div class='ctx'> 			/* pin base, nr pins &amp; gpio function */</div><div class='ctx'> 			pinctrl-single,gpio-range = &lt;&amp;range 0 10 0&gt;;</div><div class='ctx'> </div><div class='del'>-			sdio_pmx_func: sdio_pmx_func {</div><div class='add'>+			sdio_pmx_func: sdio-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x000 MUX_M1 /* SDIO_CLK */</div><div class='ctx'> 					0x004 MUX_M1 /* SDIO_CMD */</div><div class='hunk'>@@ -214,7 +535,7 @@</div><div class='ctx'> 			#pinctrl-cells = &lt;1&gt;;</div><div class='ctx'> 			pinctrl-single,register-width = &lt;0x20&gt;;</div><div class='ctx'> </div><div class='del'>-			sdio_clk_cfg_func: sdio_clk_cfg_func {</div><div class='add'>+			sdio_clk_cfg_func: sdio-clk-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x000 0x0 /* SDIO_CLK */</div><div class='ctx'> 				&gt;;</div><div class='hunk'>@@ -235,7 +556,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			sdio_cfg_func: sdio_cfg_func {</div><div class='add'>+			sdio_cfg_func: sdio-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x004 0x0 /* SDIO_CMD */</div><div class='ctx'> 					0x008 0x0 /* SDIO_DATA0 */</div><div class='hunk'>@@ -271,7 +592,7 @@</div><div class='ctx'> 			/* pin base, nr pins &amp; gpio function */</div><div class='ctx'> 			pinctrl-single,gpio-range = &lt;&amp;range 0 12 0&gt;;</div><div class='ctx'> </div><div class='del'>-			sd_pmx_func: sd_pmx_func {</div><div class='add'>+			sd_pmx_func: sd-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x000 MUX_M1 /* SD_CLK */</div><div class='ctx'> 					0x004 MUX_M1 /* SD_CMD */</div><div class='hunk'>@@ -289,7 +610,7 @@</div><div class='ctx'> 			#pinctrl-cells = &lt;1&gt;;</div><div class='ctx'> 			pinctrl-single,register-width = &lt;0x20&gt;;</div><div class='ctx'> </div><div class='del'>-			sd_clk_cfg_func: sd_clk_cfg_func {</div><div class='add'>+			sd_clk_cfg_func: sd-clk-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x000 0x0 /* SD_CLK */</div><div class='ctx'> 				&gt;;</div><div class='hunk'>@@ -311,7 +632,7 @@</div><div class='ctx'> 				&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			sd_cfg_func: sd_cfg_func {</div><div class='add'>+			sd_cfg_func: sd-cfg-pins {</div><div class='ctx'> 				pinctrl-single,pins = &lt;</div><div class='ctx'> 					0x004 0x0 /* SD_CMD */</div><div class='ctx'> 					0x008 0x0 /* SD_DATA0 */</div><div class='hunk'>@@ -338,22 +659,311 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		pmx1: pinmux@fff11000 {</div><div class='del'>-			compatible = "pinctrl-single";</div><div class='del'>-			reg = &lt;0x0 0xfff11000 0x0 0x73c&gt;;</div><div class='del'>-			#gpio-range-cells = &lt;0x3&gt;;</div><div class='del'>-			#pinctrl-cells = &lt;1&gt;;</div><div class='del'>-			pinctrl-single,register-width = &lt;0x20&gt;;</div><div class='del'>-			pinctrl-single,function-mask = &lt;0x7&gt;;</div><div class='del'>-			/* pin base, nr pins &amp; gpio function */</div><div class='del'>-			pinctrl-single,gpio-range = &lt;&amp;range 0 46 0&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='ctx'> 		pmx16: pinmux@fff11800 {</div><div class='ctx'> 			compatible = "pinconf-single";</div><div class='ctx'> 			reg = &lt;0x0 0xfff11800 0x0 0x73c&gt;;</div><div class='ctx'> 			#pinctrl-cells = &lt;1&gt;;</div><div class='ctx'> 			pinctrl-single,register-width = &lt;0x20&gt;;</div><div class='add'>+</div><div class='add'>+			pwr_key_cfg_func: pwr-key-cfg-pins {</div><div class='add'>+				pinctrl-single,pins = &lt;</div><div class='add'>+					0x090 0x0 /* GPIO_203 */</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,bias-pulldown = &lt;</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_DOWN</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_DOWN</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,bias-pullup = &lt;</div><div class='add'>+					PULL_UP</div><div class='add'>+					PULL_UP</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_UP</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,drive-strength = &lt;</div><div class='add'>+					DRIVE7_02MA DRIVE6_MASK</div><div class='add'>+				&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			usb_cfg_func: usb-cfg-pins {</div><div class='add'>+				pinctrl-single,pins = &lt;</div><div class='add'>+					0x0AC 0x0 /* GPIO_221 */</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,bias-pulldown  = &lt;</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_DOWN</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_DOWN</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,bias-pullup    = &lt;</div><div class='add'>+					PULL_UP</div><div class='add'>+					PULL_UP</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_UP</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,drive-strength = &lt;</div><div class='add'>+					DRIVE7_02MA DRIVE6_MASK</div><div class='add'>+				&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi0_cfg_func: spi0-cfg-pins {</div><div class='add'>+				pinctrl-single,pins = &lt;</div><div class='add'>+					0x0c8 0x0 /* SPI0_DI */</div><div class='add'>+					0x0cc 0x0 /* SPI0_DO */</div><div class='add'>+					0x0d0 0x0 /* SPI0_CS0_N */</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,bias-pulldown = &lt;</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_DOWN</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_DOWN</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,bias-pullup = &lt;</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_UP</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_UP</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,drive-strength = &lt;</div><div class='add'>+					DRIVE7_06MA DRIVE6_MASK</div><div class='add'>+				&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi2_cfg_func: spi2-cfg-pins {</div><div class='add'>+				pinctrl-single,pins = &lt;</div><div class='add'>+					0x714 0x0 /* SPI2_DI */</div><div class='add'>+					0x718 0x0 /* SPI2_DO */</div><div class='add'>+					0x71c 0x0 /* SPI2_CS0_N */</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,bias-pulldown = &lt;</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_DOWN</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_DOWN</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,bias-pullup = &lt;</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_UP</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_UP</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,drive-strength = &lt;</div><div class='add'>+					DRIVE7_06MA DRIVE6_MASK</div><div class='add'>+				&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi3_cfg_func: spi3-cfg-pins {</div><div class='add'>+				pinctrl-single,pins = &lt;</div><div class='add'>+					0x730 0x0 /* SPI3_DI */</div><div class='add'>+					0x734 0x0 /* SPI3_DO */</div><div class='add'>+					0x738 0x0 /* SPI3_CS0_N */</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,bias-pulldown = &lt;</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_DOWN</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_DOWN</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,bias-pullup = &lt;</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_UP</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_UP</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,drive-strength = &lt;</div><div class='add'>+					DRIVE7_06MA DRIVE6_MASK</div><div class='add'>+				&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi0_clk_cfg_func: spi0-clk-cfg-pins {</div><div class='add'>+				pinctrl-single,pins = &lt;</div><div class='add'>+					0x0c4 0x0 /* SPI0_CLK */</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,bias-pulldown = &lt;</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_DOWN</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_DOWN</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,bias-pullup = &lt;</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_UP</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_UP</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,drive-strength = &lt;</div><div class='add'>+					DRIVE7_10MA DRIVE6_MASK</div><div class='add'>+				&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi2_clk_cfg_func: spi2-clk-cfg-pins {</div><div class='add'>+				pinctrl-single,pins = &lt;</div><div class='add'>+					0x710 0x0 /* SPI2_CLK */</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,bias-pulldown = &lt;</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_DOWN</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_DOWN</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,bias-pullup = &lt;</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_UP</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_UP</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,drive-strength = &lt;</div><div class='add'>+					DRIVE7_10MA DRIVE6_MASK</div><div class='add'>+				&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi3_clk_cfg_func: spi3-clk-cfg-pins {</div><div class='add'>+				pinctrl-single,pins = &lt;</div><div class='add'>+					0x72c 0x0 /* SPI3_CLK */</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,bias-pulldown = &lt;</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_DOWN</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_DOWN</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,bias-pullup = &lt;</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_UP</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_UP</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,drive-strength = &lt;</div><div class='add'>+					DRIVE7_10MA DRIVE6_MASK</div><div class='add'>+				&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c0_cfg_func: i2c0-cfg-pins {</div><div class='add'>+				pinctrl-single,pins = &lt;</div><div class='add'>+					0x04c 0x0 /* I2C0_SCL */</div><div class='add'>+					0x050 0x0 /* I2C0_SDA */</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,bias-pulldown = &lt;</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_DOWN</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_DOWN</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,bias-pullup = &lt;</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_UP</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_UP</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,drive-strength = &lt;</div><div class='add'>+					DRIVE7_04MA DRIVE6_MASK</div><div class='add'>+				&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c1_cfg_func: i2c1-cfg-pins {</div><div class='add'>+				pinctrl-single,pins = &lt;</div><div class='add'>+					0x054 0x0 /* I2C1_SCL */</div><div class='add'>+					0x058 0x0 /* I2C1_SDA */</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,bias-pulldown = &lt;</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_DOWN</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_DOWN</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,bias-pullup = &lt;</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_UP</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_UP</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,drive-strength = &lt;</div><div class='add'>+					DRIVE7_04MA DRIVE6_MASK</div><div class='add'>+				&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c2_cfg_func: i2c2-cfg-pins {</div><div class='add'>+				pinctrl-single,pins = &lt;</div><div class='add'>+					0x05c 0x0 /* I2C2_SCL */</div><div class='add'>+					0x060 0x0 /* I2C2_SDA */</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,bias-pulldown = &lt;</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_DOWN</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_DOWN</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,bias-pullup = &lt;</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_UP</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_UP</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,drive-strength = &lt;</div><div class='add'>+					DRIVE7_04MA DRIVE6_MASK</div><div class='add'>+				&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pcie_clkreq_cfg_func: pcie-clkreq-cfg-pins {</div><div class='add'>+				pinctrl-single,pins = &lt;</div><div class='add'>+					0x0b0 0x0</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,bias-pulldown = &lt;</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_DOWN</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_DOWN</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,bias-pullup = &lt;</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_UP</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_UP</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,drive-strength = &lt;</div><div class='add'>+					DRIVE7_06MA DRIVE6_MASK</div><div class='add'>+				&gt;;</div><div class='add'>+			};</div><div class='add'>+			i2s2_cfg_func: i2s2-cfg-pins {</div><div class='add'>+				pinctrl-single,pins = &lt;</div><div class='add'>+					0x07c 0x0 /* I2S2_DI */</div><div class='add'>+					0x080 0x0 /* I2S2_DO */</div><div class='add'>+					0x084 0x0 /* I2S2_XCLK */</div><div class='add'>+					0x088 0x0 /* I2S2_XFS */</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,bias-pulldown = &lt;</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_DOWN</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_DOWN</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,bias-pullup = &lt;</div><div class='add'>+					PULL_UP</div><div class='add'>+					PULL_UP</div><div class='add'>+					PULL_DIS</div><div class='add'>+					PULL_UP</div><div class='add'>+				&gt;;</div><div class='add'>+				pinctrl-single,drive-strength = &lt;</div><div class='add'>+					DRIVE7_02MA DRIVE6_MASK</div><div class='add'>+				&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gpio185_cfg_func: gpio185-cfg-pins {</div><div class='add'>+				pinctrl-single,pins = &lt;0x048  0&gt;;</div><div class='add'>+				pinctrl-single,bias-pulldown = &lt;0 2 0 2&gt;;</div><div class='add'>+				pinctrl-single,bias-pullup = &lt;0 1 0 1&gt;;</div><div class='add'>+				pinctrl-single,drive-strength = &lt;0x00 0x70&gt;;</div><div class='add'>+				pinctrl-single,slew-rate = &lt;0x0 0x80&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gpio185_cfg_idle: gpio185-cfg-idle-pins {</div><div class='add'>+				pinctrl-single,pins = &lt;0x048  0&gt;;</div><div class='add'>+				pinctrl-single,bias-pulldown = &lt;2 2 0 2&gt;;</div><div class='add'>+				pinctrl-single,bias-pullup = &lt;0 1 0 1&gt;;</div><div class='add'>+				pinctrl-single,drive-strength = &lt;0x00 0x70&gt;;</div><div class='add'>+				pinctrl-single,slew-rate = &lt;0x0 0x80&gt;;</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi b/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi<br/>new file mode 100644<br/>index 000000000000..299c4ab630e8<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi</a></div><div class='hunk'>@@ -0,0 +1,82 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * dts file for Hi6421v600 SPMI PMIC used at the HiKey970 Development Board</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) 2020, Huawei Tech. Co., Ltd.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/spmi/spmi.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	spmi: spmi@fff24000 {</div><div class='add'>+		compatible = "hisilicon,kirin970-spmi-controller";</div><div class='add'>+		reg = &lt;0x0 0xfff24000 0x0 0x1000&gt;;</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		hisilicon,spmi-channel = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		pmic: pmic@0 {</div><div class='add'>+			compatible = "hisilicon,hi6421-spmi";</div><div class='add'>+			reg = &lt;0 SPMI_USID&gt;;</div><div class='add'>+</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			gpios = &lt;&amp;gpio28 0 0&gt;;</div><div class='add'>+</div><div class='add'>+			regulators {</div><div class='add'>+				ldo3: ldo3 { /* HDMI */</div><div class='add'>+					regulator-name = "ldo3";</div><div class='add'>+					regulator-min-microvolt = &lt;1500000&gt;;</div><div class='add'>+					regulator-max-microvolt = &lt;2000000&gt;;</div><div class='add'>+					regulator-boot-on;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				ldo4: ldo4 { /* 40 PIN */</div><div class='add'>+					regulator-name = "ldo4";</div><div class='add'>+					regulator-min-microvolt = &lt;1725000&gt;;</div><div class='add'>+					regulator-max-microvolt = &lt;1900000&gt;;</div><div class='add'>+					regulator-boot-on;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				ldo9: ldo9 { /* SDCARD I/O */</div><div class='add'>+					regulator-name = "ldo9";</div><div class='add'>+					regulator-min-microvolt = &lt;1750000&gt;;</div><div class='add'>+					regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+					regulator-boot-on;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				ldo15: ldo15 { /* UFS */</div><div class='add'>+					regulator-name = "ldo15";</div><div class='add'>+					regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+					regulator-max-microvolt = &lt;3000000&gt;;</div><div class='add'>+					regulator-always-on;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				ldo16: ldo16 { /* SD */</div><div class='add'>+					regulator-name = "ldo16";</div><div class='add'>+					regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+					regulator-max-microvolt = &lt;3000000&gt;;</div><div class='add'>+					regulator-boot-on;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				ldo17: ldo17 { /* USB HUB */</div><div class='add'>+					regulator-name = "ldo17";</div><div class='add'>+					regulator-min-microvolt = &lt;2500000&gt;;</div><div class='add'>+					regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				ldo33: ldo33 { /* PEX8606 */</div><div class='add'>+					regulator-name = "ldo33";</div><div class='add'>+					regulator-min-microvolt = &lt;2500000&gt;;</div><div class='add'>+					regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				ldo34: ldo34 { /* GPS AUX IN VDD */</div><div class='add'>+					regulator-name = "ldo34";</div><div class='add'>+					regulator-min-microvolt = &lt;2600000&gt;;</div><div class='add'>+					regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts<br/>index e93c65ede06c..b7792d443189 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/hisilicon/hip05-d02.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/hisilicon/hip05-d02.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/hisilicon/hip05-d02.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/hisilicon/hip05-d02.dts</a></div><div class='hunk'>@@ -2,7 +2,7 @@</div><div class='ctx'> /**</div><div class='ctx'>  * dts file for Hisilicon D02 Development Board</div><div class='ctx'>  *</div><div class='del'>- * Copyright (C) 2014,2015 Hisilicon Ltd.</div><div class='add'>+ * Copyright (C) 2014,2015 HiSilicon Ltd.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> /dts-v1/;</div><div class='hunk'>@@ -27,12 +27,10 @@</div><div class='ctx'> 		stdout-path = "serial0:115200n8";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpio_keys {</div><div class='add'>+	gpio-keys {</div><div class='ctx'> 		compatible = "gpio-keys";</div><div class='del'>-		#address-cells = &lt;1&gt;;</div><div class='del'>-		#size-cells = &lt;0&gt;;</div><div class='ctx'> </div><div class='del'>-		pwrbutton {</div><div class='add'>+		pwr-button {</div><div class='ctx'> 			label = "Power Button";</div><div class='ctx'> 			gpios = &lt;&amp;porta 8 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 			linux,code = &lt;116&gt;;</div><div class='hunk'>@@ -42,21 +40,21 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;uart0 {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;peri_gpio0 {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;lbc {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> 	#address-cells = &lt;2&gt;;</div><div class='ctx'> 	#size-cells = &lt;1&gt;;</div><div class='ctx'> 	ranges = &lt;0 0 0x0 0x90000000 0x08000000&gt;,</div><div class='ctx'> 		 &lt;1 0 0x0 0x98000000 0x08000000&gt;;</div><div class='ctx'> </div><div class='del'>-	nor-flash@0,0 {</div><div class='add'>+	nor-flash@0 {</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;1&gt;;</div><div class='ctx'> 		compatible = "numonyx,js28f00a", "cfi-flash";</div><div class='hunk'>@@ -77,7 +75,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	cpld@1,0 {</div><div class='add'>+	cpld@100000000 {</div><div class='ctx'> 		compatible = "hisilicon,hip05-cpld";</div><div class='ctx'> 		reg = &lt;1 0x0 0x100&gt;;</div><div class='ctx'> 	};</div><div class='head'>diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi<br/>index bc49955360db..d0912ca5f237 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/hisilicon/hip05.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/hisilicon/hip05.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/hisilicon/hip05.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/hisilicon/hip05.dtsi</a></div><div class='hunk'>@@ -2,7 +2,7 @@</div><div class='ctx'> /**</div><div class='ctx'>  * dts file for Hisilicon D02 Development Board</div><div class='ctx'>  *</div><div class='del'>- * Copyright (C) 2014,2015 Hisilicon Ltd.</div><div class='add'>+ * Copyright (C) 2014,2015 HiSilicon Ltd.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='hunk'>@@ -211,18 +211,26 @@</div><div class='ctx'> </div><div class='ctx'> 		cluster0_l2: l2-cache0 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cluster1_l2: l2-cache1 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cluster2_l2: l2-cache2 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cluster3_l2: l2-cache3 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -242,28 +250,28 @@</div><div class='ctx'> 		      &lt;0x0 0xfe020000 0 0x10000&gt;;       /* GICV */</div><div class='ctx'> 		interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> </div><div class='del'>-		its_peri: interrupt-controller@8c000000 {</div><div class='add'>+		its_peri: msi-controller@8c000000 {</div><div class='ctx'> 			compatible = "arm,gic-v3-its";</div><div class='ctx'> 			msi-controller;</div><div class='ctx'> 			#msi-cells = &lt;1&gt;;</div><div class='ctx'> 			reg = &lt;0x0 0x8c000000 0x0 0x40000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		its_m3: interrupt-controller@a3000000 {</div><div class='add'>+		its_m3: msi-controller@a3000000 {</div><div class='ctx'> 			compatible = "arm,gic-v3-its";</div><div class='ctx'> 			msi-controller;</div><div class='ctx'> 			#msi-cells = &lt;1&gt;;</div><div class='ctx'> 			reg = &lt;0x0 0xa3000000 0x0 0x40000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		its_pcie: interrupt-controller@b7000000 {</div><div class='add'>+		its_pcie: msi-controller@b7000000 {</div><div class='ctx'> 			compatible = "arm,gic-v3-its";</div><div class='ctx'> 			msi-controller;</div><div class='ctx'> 			#msi-cells = &lt;1&gt;;</div><div class='ctx'> 			reg = &lt;0x0 0xb7000000 0x0 0x40000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		its_dsa: interrupt-controller@c6000000 {</div><div class='add'>+		its_dsa: msi-controller@c6000000 {</div><div class='ctx'> 			compatible = "arm,gic-v3-its";</div><div class='ctx'> 			msi-controller;</div><div class='ctx'> 			#msi-cells = &lt;1&gt;;</div><div class='hunk'>@@ -271,6 +279,12 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	refclk200mhz: refclk200mhz {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;200000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	timer {</div><div class='ctx'> 		compatible = "arm,armv8-timer";</div><div class='ctx'> 		interrupts = &lt;GIC_PPI 13 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='hunk'>@@ -290,35 +304,29 @@</div><div class='ctx'> 		#size-cells = &lt;2&gt;;</div><div class='ctx'> 		ranges;</div><div class='ctx'> </div><div class='del'>-		refclk200mhz: refclk200mhz {</div><div class='del'>-			compatible = "fixed-clock";</div><div class='del'>-			#clock-cells = &lt;0&gt;;</div><div class='del'>-			clock-frequency = &lt;200000000&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		uart0: uart@80300000 {</div><div class='add'>+		uart0: serial@80300000 {</div><div class='ctx'> 			compatible = "snps,dw-apb-uart";</div><div class='ctx'> 			reg = &lt;0x0 0x80300000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;refclk200mhz&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='add'>+			clocks = &lt;&amp;refclk200mhz&gt;, &lt;&amp;refclk200mhz&gt;;</div><div class='add'>+			clock-names = "baudclk", "apb_pclk";</div><div class='ctx'> 			reg-shift = &lt;2&gt;;</div><div class='ctx'> 			reg-io-width = &lt;4&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		uart1: uart@80310000 {</div><div class='add'>+		uart1: serial@80310000 {</div><div class='ctx'> 			compatible = "snps,dw-apb-uart";</div><div class='ctx'> 			reg = &lt;0x0 0x80310000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;refclk200mhz&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='add'>+			clocks = &lt;&amp;refclk200mhz&gt;, &lt;&amp;refclk200mhz&gt;;</div><div class='add'>+			clock-names = "baudclk", "apb_pclk";</div><div class='ctx'> 			reg-shift = &lt;2&gt;;</div><div class='ctx'> 			reg-io-width = &lt;4&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		lbc: localbus@80380000 {</div><div class='add'>+		lbc: local-bus@80380000 {</div><div class='ctx'> 			compatible = "hisilicon,hisi-localbus", "simple-bus";</div><div class='ctx'> 			reg = &lt;0x0 0x80380000 0x0 0x10000&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='hunk'>@@ -335,7 +343,7 @@</div><div class='ctx'> 				compatible = "snps,dw-apb-gpio-port";</div><div class='ctx'> 				gpio-controller;</div><div class='ctx'> 				#gpio-cells = &lt;2&gt;;</div><div class='del'>-				snps,nr-gpios = &lt;32&gt;;</div><div class='add'>+				ngpios = &lt;32&gt;;</div><div class='ctx'> 				reg = &lt;0&gt;;</div><div class='ctx'> 				interrupt-controller;</div><div class='ctx'> 				#interrupt-cells = &lt;2&gt;;</div><div class='hunk'>@@ -354,7 +362,7 @@</div><div class='ctx'> 				compatible = "snps,dw-apb-gpio-port";</div><div class='ctx'> 				gpio-controller;</div><div class='ctx'> 				#gpio-cells = &lt;2&gt;;</div><div class='del'>-				snps,nr-gpios = &lt;32&gt;;</div><div class='add'>+				ngpios = &lt;32&gt;;</div><div class='ctx'> 				reg = &lt;0&gt;;</div><div class='ctx'> 				interrupt-controller;</div><div class='ctx'> 				#interrupt-cells = &lt;2&gt;;</div><div class='head'>diff --git a/arch/arm64/boot/dts/hisilicon/hip06-d03.dts b/arch/arm64/boot/dts/hisilicon/hip06-d03.dts<br/>index 677862beebef..35af5d3821e8 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/hisilicon/hip06-d03.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/hisilicon/hip06-d03.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/hisilicon/hip06-d03.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/hisilicon/hip06-d03.dts</a></div><div class='hunk'>@@ -2,7 +2,7 @@</div><div class='ctx'> /**</div><div class='ctx'>  * dts file for Hisilicon D03 Development Board</div><div class='ctx'>  *</div><div class='del'>- * Copyright (C) 2016 Hisilicon Ltd.</div><div class='add'>+ * Copyright (C) 2016 HiSilicon Ltd.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> /dts-v1/;</div><div class='hunk'>@@ -22,37 +22,37 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;ipmi0 {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;uart0 {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;eth0 {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;eth1 {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;eth2 {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;eth3 {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;sas1 {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;usb_ohci {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;usb_ehci {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi<br/>index 50ceaa959bdc..3d7285e6700e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/hisilicon/hip06.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/hisilicon/hip06.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/hisilicon/hip06.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/hisilicon/hip06.dtsi</a></div><div class='hunk'>@@ -2,7 +2,7 @@</div><div class='ctx'> /**</div><div class='ctx'>  * dts file for Hisilicon D03 Development Board</div><div class='ctx'>  *</div><div class='del'>- * Copyright (C) 2016 Hisilicon Ltd.</div><div class='add'>+ * Copyright (C) 2016 HiSilicon Ltd.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='hunk'>@@ -211,18 +211,26 @@</div><div class='ctx'> </div><div class='ctx'> 		cluster0_l2: l2-cache0 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cluster1_l2: l2-cache1 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cluster2_l2: l2-cache2 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cluster3_l2: l2-cache3 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -242,7 +250,7 @@</div><div class='ctx'> 		      &lt;0x0 0xfe020000 0 0x10000&gt;;       /* GICV */</div><div class='ctx'> 		interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> </div><div class='del'>-		its_dsa: interrupt-controller@c6000000 {</div><div class='add'>+		its_dsa: msi-controller@c6000000 {</div><div class='ctx'> 			compatible = "arm,gic-v3-its";</div><div class='ctx'> 			msi-controller;</div><div class='ctx'> 			#msi-cells = &lt;1&gt;;</div><div class='hunk'>@@ -250,6 +258,48 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	eth2: ethernet-0 {</div><div class='add'>+		compatible = "hisilicon,hns-nic-v2";</div><div class='add'>+		ae-handle = &lt;&amp;dsaf0&gt;;</div><div class='add'>+		port-idx-in-ae = &lt;0&gt;;</div><div class='add'>+		local-mac-address = [00 00 00 00 00 00];</div><div class='add'>+		status = "disabled";</div><div class='add'>+		dma-coherent;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eth3: ethernet-1 {</div><div class='add'>+		compatible = "hisilicon,hns-nic-v2";</div><div class='add'>+		ae-handle = &lt;&amp;dsaf0&gt;;</div><div class='add'>+		port-idx-in-ae = &lt;1&gt;;</div><div class='add'>+		local-mac-address = [00 00 00 00 00 00];</div><div class='add'>+		status = "disabled";</div><div class='add'>+		dma-coherent;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eth0: ethernet-4 {</div><div class='add'>+		compatible = "hisilicon,hns-nic-v2";</div><div class='add'>+		ae-handle = &lt;&amp;dsaf0&gt;;</div><div class='add'>+		port-idx-in-ae = &lt;4&gt;;</div><div class='add'>+		local-mac-address = [00 00 00 00 00 00];</div><div class='add'>+		status = "disabled";</div><div class='add'>+		dma-coherent;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eth1: ethernet-5 {</div><div class='add'>+		compatible = "hisilicon,hns-nic-v2";</div><div class='add'>+		ae-handle = &lt;&amp;dsaf0&gt;;</div><div class='add'>+		port-idx-in-ae = &lt;5&gt;;</div><div class='add'>+		local-mac-address = [00 00 00 00 00 00];</div><div class='add'>+		status = "disabled";</div><div class='add'>+		dma-coherent;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	refclk: refclk {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		clock-frequency = &lt;50000000&gt;;</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	timer {</div><div class='ctx'> 		compatible = "arm,armv8-timer";</div><div class='ctx'> 		interrupts = &lt;GIC_PPI 13 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='hunk'>@@ -330,12 +380,11 @@</div><div class='ctx'> 	 *  when iommu-map entry is used along with the PCIe node.</div><div class='ctx'> 	 *  Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html</div><div class='ctx'> 	 */</div><div class='del'>-	smmu0: smmu_pcie {</div><div class='add'>+	smmu0: iommu@a0040000 {</div><div class='ctx'> 		compatible = "arm,smmu-v3";</div><div class='ctx'> 		reg = &lt;0x0 0xa0040000 0x0 0x20000&gt;;</div><div class='ctx'> 		#iommu-cells = &lt;1&gt;;</div><div class='ctx'> 		dma-coherent;</div><div class='del'>-		smmu-cb-memtype = &lt;0x0 0x1&gt;;</div><div class='ctx'> 		hisilicon,broken-prefetch-cmd;</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='hunk'>@@ -359,7 +408,7 @@</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			uart0: lpc-uart@2f8 {</div><div class='add'>+			uart0: serial@2f8 {</div><div class='ctx'> 				compatible = "ns16550a";</div><div class='ctx'> 				clock-frequency = &lt;1843200&gt;;</div><div class='ctx'> 				reg = &lt;0x01 0x2f8 0x08&gt;;</div><div class='hunk'>@@ -367,13 +416,7 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		refclk: refclk {</div><div class='del'>-			compatible = "fixed-clock";</div><div class='del'>-			clock-frequency = &lt;50000000&gt;;</div><div class='del'>-			#clock-cells = &lt;0&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		usb_ohci: ohci@a7030000 {</div><div class='add'>+		usb_ohci: usb@a7030000 {</div><div class='ctx'> 			compatible = "generic-ohci";</div><div class='ctx'> 			reg = &lt;0x0 0xa7030000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupt-parent = &lt;&amp;mbigen_usb&gt;;</div><div class='hunk'>@@ -382,7 +425,7 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		usb_ehci: ehci@a7020000 {</div><div class='add'>+		usb_ehci: usb@a7020000 {</div><div class='ctx'> 			compatible = "generic-ehci";</div><div class='ctx'> 			reg = &lt;0x0 0xa7020000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupt-parent = &lt;&amp;mbigen_usb&gt;;</div><div class='hunk'>@@ -429,13 +472,13 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		dsaf0: dsa@c7000000 {</div><div class='add'>+		dsaf0: dsa@c5000000 {</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			compatible = "hisilicon,hns-dsaf-v2";</div><div class='ctx'> 			mode = "6port-16rss";</div><div class='del'>-			reg = &lt;0x0 0xc5000000 0x0 0x890000</div><div class='del'>-			       0x0 0xc7000000 0x0 0x600000&gt;;</div><div class='add'>+			reg = &lt;0x0 0xc5000000 0x0 0x890000&gt;,</div><div class='add'>+			      &lt;0x0 0xc7000000 0x0 0x600000&gt;;</div><div class='ctx'> 			reg-names = "ppe-base", "dsaf-base";</div><div class='ctx'> 			interrupt-parent = &lt;&amp;mbigen_dsaf0&gt;;</div><div class='ctx'> 			subctrl-syscon = &lt;&amp;dsa_subctrl&gt;;</div><div class='hunk'>@@ -538,7 +581,7 @@</div><div class='ctx'> </div><div class='ctx'> 			port@1 {</div><div class='ctx'> 				reg = &lt;1&gt;;</div><div class='del'>-				serdes-syscon= &lt;&amp;serdes_ctrl&gt;;</div><div class='add'>+				serdes-syscon = &lt;&amp;serdes_ctrl&gt;;</div><div class='ctx'> 				port-rst-offset = &lt;1&gt;;</div><div class='ctx'> 				port-mode-offset = &lt;1&gt;;</div><div class='ctx'> 				media-type = "fiber";</div><div class='hunk'>@@ -547,7 +590,7 @@</div><div class='ctx'> 			port@4 {</div><div class='ctx'> 				reg = &lt;4&gt;;</div><div class='ctx'> 				phy-handle = &lt;&amp;phy0&gt;;</div><div class='del'>-				serdes-syscon= &lt;&amp;serdes_ctrl&gt;;</div><div class='add'>+				serdes-syscon = &lt;&amp;serdes_ctrl&gt;;</div><div class='ctx'> 				port-rst-offset = &lt;4&gt;;</div><div class='ctx'> 				port-mode-offset = &lt;2&gt;;</div><div class='ctx'> 				media-type = "copper";</div><div class='hunk'>@@ -556,49 +599,13 @@</div><div class='ctx'> 			port@5 {</div><div class='ctx'> 				reg = &lt;5&gt;;</div><div class='ctx'> 				phy-handle = &lt;&amp;phy1&gt;;</div><div class='del'>-				serdes-syscon= &lt;&amp;serdes_ctrl&gt;;</div><div class='add'>+				serdes-syscon = &lt;&amp;serdes_ctrl&gt;;</div><div class='ctx'> 				port-rst-offset = &lt;5&gt;;</div><div class='ctx'> 				port-mode-offset = &lt;3&gt;;</div><div class='ctx'> 				media-type = "copper";</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		eth0: ethernet-4{</div><div class='del'>-			compatible = "hisilicon,hns-nic-v2";</div><div class='del'>-			ae-handle = &lt;&amp;dsaf0&gt;;</div><div class='del'>-			port-idx-in-ae = &lt;4&gt;;</div><div class='del'>-			local-mac-address = [00 00 00 00 00 00];</div><div class='del'>-			status = "disabled";</div><div class='del'>-			dma-coherent;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		eth1: ethernet-5{</div><div class='del'>-			compatible = "hisilicon,hns-nic-v2";</div><div class='del'>-			ae-handle = &lt;&amp;dsaf0&gt;;</div><div class='del'>-			port-idx-in-ae = &lt;5&gt;;</div><div class='del'>-			local-mac-address = [00 00 00 00 00 00];</div><div class='del'>-			status = "disabled";</div><div class='del'>-			dma-coherent;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		eth2: ethernet-0{</div><div class='del'>-			compatible = "hisilicon,hns-nic-v2";</div><div class='del'>-			ae-handle = &lt;&amp;dsaf0&gt;;</div><div class='del'>-			port-idx-in-ae = &lt;0&gt;;</div><div class='del'>-			local-mac-address = [00 00 00 00 00 00];</div><div class='del'>-			status = "disabled";</div><div class='del'>-			dma-coherent;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		eth3: ethernet-1{</div><div class='del'>-			compatible = "hisilicon,hns-nic-v2";</div><div class='del'>-			ae-handle = &lt;&amp;dsaf0&gt;;</div><div class='del'>-			port-idx-in-ae = &lt;1&gt;;</div><div class='del'>-			local-mac-address = [00 00 00 00 00 00];</div><div class='del'>-			status = "disabled";</div><div class='del'>-			dma-coherent;</div><div class='del'>-		};</div><div class='del'>-</div><div class='ctx'> 		sas0: sas@c3000000 {</div><div class='ctx'> 			compatible = "hisilicon,hip06-sas-v2";</div><div class='ctx'> 			reg = &lt;0 0xc3000000 0 0x10000&gt;;</div><div class='hunk'>@@ -726,7 +733,7 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		pcie0: pcie@a0090000 {</div><div class='add'>+		pcie0: pcie@b0000000 {</div><div class='ctx'> 			compatible = "hisilicon,hip06-pcie-ecam";</div><div class='ctx'> 			reg = &lt;0 0xb0000000 0 0x2000000&gt;,</div><div class='ctx'> 			      &lt;0 0xa0090000 0 0x10000&gt;;</div><div class='hunk'>@@ -737,9 +744,8 @@</div><div class='ctx'> 			#size-cells = &lt;2&gt;;</div><div class='ctx'> 			device_type = "pci";</div><div class='ctx'> 			dma-coherent;</div><div class='del'>-			ranges = &lt;0x02000000 0 0xb2000000 0x0 0xb2000000 0</div><div class='del'>-				 0x5ff0000 0x01000000 0 0 0 0xb7ff0000</div><div class='del'>-				 0 0x10000&gt;;</div><div class='add'>+			ranges = &lt;0x02000000 0 0xb2000000 0x0 0xb2000000 0 0x5ff0000&gt;,</div><div class='add'>+				 &lt;0x01000000 0 0 0 0xb7ff0000 0 0x10000&gt;;</div><div class='ctx'> 			#interrupt-cells = &lt;1&gt;;</div><div class='ctx'> 			interrupt-map-mask = &lt;0xf800 0 0 7&gt;;</div><div class='ctx'> 			interrupt-map = &lt;0x0 0 0 1 &amp;mbigen_pcie0 650 4</div><div class='head'>diff --git a/arch/arm64/boot/dts/hisilicon/hip07-d05.dts b/arch/arm64/boot/dts/hisilicon/hip07-d05.dts<br/>index fcbdffe0868b..c3df67845f03 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/hisilicon/hip07-d05.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/hisilicon/hip07-d05.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/hisilicon/hip07-d05.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/hisilicon/hip07-d05.dts</a></div><div class='hunk'>@@ -2,7 +2,7 @@</div><div class='ctx'> /**</div><div class='ctx'>  * dts file for Hisilicon D05 Development Board</div><div class='ctx'>  *</div><div class='del'>- * Copyright (C) 2016 Hisilicon Ltd.</div><div class='add'>+ * Copyright (C) 2016 HiSilicon Ltd.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> /dts-v1/;</div><div class='hunk'>@@ -50,41 +50,41 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;uart0 {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;ipmi0 {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;usb_ohci {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;usb_ehci {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;eth0 {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;eth1 {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;eth2 {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;eth3 {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;sas1 {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;p0_pcie2_a {</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi<br/>index 4773a533fce5..00a6bfa7478c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/hisilicon/hip07.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/hisilicon/hip07.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/hisilicon/hip07.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/hisilicon/hip07.dtsi</a></div><div class='hunk'>@@ -2,7 +2,7 @@</div><div class='ctx'> /**</div><div class='ctx'>  * dts file for Hisilicon D05 Development Board</div><div class='ctx'>  *</div><div class='del'>- * Copyright (C) 2016 Hisilicon Ltd.</div><div class='add'>+ * Copyright (C) 2016 HiSilicon Ltd.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='hunk'>@@ -842,66 +842,98 @@</div><div class='ctx'> </div><div class='ctx'> 		cluster0_l2: l2-cache0 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cluster1_l2: l2-cache1 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cluster2_l2: l2-cache2 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cluster3_l2: l2-cache3 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cluster4_l2: l2-cache4 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cluster5_l2: l2-cache5 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cluster6_l2: l2-cache6 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cluster7_l2: l2-cache7 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cluster8_l2: l2-cache8 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cluster9_l2: l2-cache9 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cluster10_l2: l2-cache10 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cluster11_l2: l2-cache11 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cluster12_l2: l2-cache12 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cluster13_l2: l2-cache13 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cluster14_l2: l2-cache14 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cluster15_l2: l2-cache15 {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -924,56 +956,56 @@</div><div class='ctx'> 		      &lt;0x0 0xfe020000 0x0 0x10000&gt;;	/* GICV */</div><div class='ctx'> 		interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> </div><div class='del'>-		p0_its_peri_a: interrupt-controller@4c000000 {</div><div class='add'>+		p0_its_peri_a: msi-controller@4c000000 {</div><div class='ctx'> 			compatible = "arm,gic-v3-its";</div><div class='ctx'> 			msi-controller;</div><div class='ctx'> 			#msi-cells = &lt;1&gt;;</div><div class='ctx'> 			reg = &lt;0x0 0x4c000000 0x0 0x40000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		p0_its_peri_b: interrupt-controller@6c000000 {</div><div class='add'>+		p0_its_peri_b: msi-controller@6c000000 {</div><div class='ctx'> 			compatible = "arm,gic-v3-its";</div><div class='ctx'> 			msi-controller;</div><div class='ctx'> 			#msi-cells = &lt;1&gt;;</div><div class='ctx'> 			reg = &lt;0x0 0x6c000000 0x0 0x40000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		p0_its_dsa_a: interrupt-controller@c6000000 {</div><div class='add'>+		p0_its_dsa_a: msi-controller@c6000000 {</div><div class='ctx'> 			compatible = "arm,gic-v3-its";</div><div class='ctx'> 			msi-controller;</div><div class='ctx'> 			#msi-cells = &lt;1&gt;;</div><div class='ctx'> 			reg = &lt;0x0 0xc6000000 0x0 0x40000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		p0_its_dsa_b: interrupt-controller@8,c6000000 {</div><div class='add'>+		p0_its_dsa_b: msi-controller@8c6000000 {</div><div class='ctx'> 			compatible = "arm,gic-v3-its";</div><div class='ctx'> 			msi-controller;</div><div class='ctx'> 			#msi-cells = &lt;1&gt;;</div><div class='ctx'> 			reg = &lt;0x8 0xc6000000 0x0 0x40000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		p1_its_peri_a: interrupt-controller@400,4c000000 {</div><div class='add'>+		p1_its_peri_a: msi-controller@4004c000000 {</div><div class='ctx'> 			compatible = "arm,gic-v3-its";</div><div class='ctx'> 			msi-controller;</div><div class='ctx'> 			#msi-cells = &lt;1&gt;;</div><div class='ctx'> 			reg = &lt;0x400 0x4c000000 0x0 0x40000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		p1_its_peri_b: interrupt-controller@400,6c000000 {</div><div class='add'>+		p1_its_peri_b: msi-controller@4006c000000 {</div><div class='ctx'> 			compatible = "arm,gic-v3-its";</div><div class='ctx'> 			msi-controller;</div><div class='ctx'> 			#msi-cells = &lt;1&gt;;</div><div class='ctx'> 			reg = &lt;0x400 0x6c000000 0x0 0x40000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		p1_its_dsa_a: interrupt-controller@400,c6000000 {</div><div class='add'>+		p1_its_dsa_a: msi-controller@400c6000000 {</div><div class='ctx'> 			compatible = "arm,gic-v3-its";</div><div class='ctx'> 			msi-controller;</div><div class='ctx'> 			#msi-cells = &lt;1&gt;;</div><div class='ctx'> 			reg = &lt;0x400 0xc6000000 0x0 0x40000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		p1_its_dsa_b: interrupt-controller@408,c6000000 {</div><div class='add'>+		p1_its_dsa_b: msi-controller@408c6000000 {</div><div class='ctx'> 			compatible = "arm,gic-v3-its";</div><div class='ctx'> 			msi-controller;</div><div class='ctx'> 			#msi-cells = &lt;1&gt;;</div><div class='hunk'>@@ -981,6 +1013,42 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	eth0: ethernet-0 {</div><div class='add'>+		compatible = "hisilicon,hns-nic-v2";</div><div class='add'>+		ae-handle = &lt;&amp;dsaf0&gt;;</div><div class='add'>+		port-idx-in-ae = &lt;4&gt;;</div><div class='add'>+		local-mac-address = [00 00 00 00 00 00];</div><div class='add'>+		status = "disabled";</div><div class='add'>+		dma-coherent;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eth1: ethernet-1 {</div><div class='add'>+		compatible = "hisilicon,hns-nic-v2";</div><div class='add'>+		ae-handle = &lt;&amp;dsaf0&gt;;</div><div class='add'>+		port-idx-in-ae = &lt;5&gt;;</div><div class='add'>+		local-mac-address = [00 00 00 00 00 00];</div><div class='add'>+		status = "disabled";</div><div class='add'>+		dma-coherent;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eth2: ethernet-2 {</div><div class='add'>+		compatible = "hisilicon,hns-nic-v2";</div><div class='add'>+		ae-handle = &lt;&amp;dsaf0&gt;;</div><div class='add'>+		port-idx-in-ae = &lt;0&gt;;</div><div class='add'>+		local-mac-address = [00 00 00 00 00 00];</div><div class='add'>+		status = "disabled";</div><div class='add'>+		dma-coherent;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eth3: ethernet-3 {</div><div class='add'>+		compatible = "hisilicon,hns-nic-v2";</div><div class='add'>+		ae-handle = &lt;&amp;dsaf0&gt;;</div><div class='add'>+		port-idx-in-ae = &lt;1&gt;;</div><div class='add'>+		local-mac-address = [00 00 00 00 00 00];</div><div class='add'>+		status = "disabled";</div><div class='add'>+		dma-coherent;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	timer {</div><div class='ctx'> 		compatible = "arm,armv8-timer";</div><div class='ctx'> 		interrupts = &lt;GIC_PPI 13 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='hunk'>@@ -1161,16 +1229,15 @@</div><div class='ctx'> 	 *  when iommu-map entry is used along with the PCIe node.</div><div class='ctx'> 	 *  Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html</div><div class='ctx'> 	 */</div><div class='del'>-	smmu0: smmu_pcie {</div><div class='add'>+	smmu0: iommu@a0040000 {</div><div class='ctx'> 		compatible = "arm,smmu-v3";</div><div class='ctx'> 		reg = &lt;0x0 0xa0040000 0x0 0x20000&gt;;</div><div class='ctx'> 		#iommu-cells = &lt;1&gt;;</div><div class='ctx'> 		dma-coherent;</div><div class='del'>-		smmu-cb-memtype = &lt;0x0 0x1&gt;;</div><div class='ctx'> 		hisilicon,broken-prefetch-cmd;</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='del'>-	p0_smmu_alg_a: smmu_alg@d0040000 {</div><div class='add'>+	p0_smmu_alg_a: iommu@d0040000 {</div><div class='ctx'> 		compatible = "arm,smmu-v3";</div><div class='ctx'> 		reg = &lt;0x0 0xd0040000 0x0 0x20000&gt;;</div><div class='ctx'> 		interrupt-parent = &lt;&amp;p0_mbigen_smmu_alg_a&gt;;</div><div class='hunk'>@@ -1181,9 +1248,8 @@</div><div class='ctx'> 		#iommu-cells = &lt;1&gt;;</div><div class='ctx'> 		dma-coherent;</div><div class='ctx'> 		hisilicon,broken-prefetch-cmd;</div><div class='del'>-		/* smmu-cb-memtype = &lt;0x0 0x1&gt;;*/</div><div class='ctx'> 	};</div><div class='del'>-	p0_smmu_alg_b: smmu_alg@8,d0040000 {</div><div class='add'>+	p0_smmu_alg_b: iommu@8d0040000 {</div><div class='ctx'> 		compatible = "arm,smmu-v3";</div><div class='ctx'> 		reg = &lt;0x8 0xd0040000 0x0 0x20000&gt;;</div><div class='ctx'> 		interrupt-parent = &lt;&amp;p0_mbigen_smmu_alg_b&gt;;</div><div class='hunk'>@@ -1194,9 +1260,8 @@</div><div class='ctx'> 		#iommu-cells = &lt;1&gt;;</div><div class='ctx'> 		dma-coherent;</div><div class='ctx'> 		hisilicon,broken-prefetch-cmd;</div><div class='del'>-		/* smmu-cb-memtype = &lt;0x0 0x1&gt;;*/</div><div class='ctx'> 	};</div><div class='del'>-	p1_smmu_alg_a: smmu_alg@400,d0040000 {</div><div class='add'>+	p1_smmu_alg_a: iommu@400d0040000 {</div><div class='ctx'> 		compatible = "arm,smmu-v3";</div><div class='ctx'> 		reg = &lt;0x400 0xd0040000 0x0 0x20000&gt;;</div><div class='ctx'> 		interrupt-parent = &lt;&amp;p1_mbigen_smmu_alg_a&gt;;</div><div class='hunk'>@@ -1207,9 +1272,8 @@</div><div class='ctx'> 		#iommu-cells = &lt;1&gt;;</div><div class='ctx'> 		dma-coherent;</div><div class='ctx'> 		hisilicon,broken-prefetch-cmd;</div><div class='del'>-		/* smmu-cb-memtype = &lt;0x0 0x1&gt;;*/</div><div class='ctx'> 	};</div><div class='del'>-	p1_smmu_alg_b: smmu_alg@408,d0040000 {</div><div class='add'>+	p1_smmu_alg_b: iommu@408d0040000 {</div><div class='ctx'> 		compatible = "arm,smmu-v3";</div><div class='ctx'> 		reg = &lt;0x408 0xd0040000 0x0 0x20000&gt;;</div><div class='ctx'> 		interrupt-parent = &lt;&amp;p1_mbigen_smmu_alg_b&gt;;</div><div class='hunk'>@@ -1220,7 +1284,6 @@</div><div class='ctx'> 		#iommu-cells = &lt;1&gt;;</div><div class='ctx'> 		dma-coherent;</div><div class='ctx'> 		hisilicon,broken-prefetch-cmd;</div><div class='del'>-		/* smmu-cb-memtype = &lt;0x0 0x1&gt;;*/</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	soc {</div><div class='hunk'>@@ -1243,7 +1306,7 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		uart0: uart@602b0000 {</div><div class='add'>+		uart0: serial@602b0000 {</div><div class='ctx'> 			compatible = "arm,sbsa-uart";</div><div class='ctx'> 			reg = &lt;0x0 0x602b0000 0x0 0x1000&gt;;</div><div class='ctx'> 			interrupt-parent = &lt;&amp;mbigen_uart&gt;;</div><div class='hunk'>@@ -1253,7 +1316,7 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		usb_ohci: ohci@a7030000 {</div><div class='add'>+		usb_ohci: usb@a7030000 {</div><div class='ctx'> 			compatible = "generic-ohci";</div><div class='ctx'> 			reg = &lt;0x0 0xa7030000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupt-parent = &lt;&amp;mbigen_usb&gt;;</div><div class='hunk'>@@ -1262,7 +1325,7 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		usb_ehci: ehci@a7020000 {</div><div class='add'>+		usb_ehci: usb@a7020000 {</div><div class='ctx'> 			compatible = "generic-ehci";</div><div class='ctx'> 			reg = &lt;0x0 0xa7020000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupt-parent = &lt;&amp;mbigen_usb&gt;;</div><div class='hunk'>@@ -1316,13 +1379,13 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		dsaf0: dsa@c7000000 {</div><div class='add'>+		dsaf0: dsa@c5000000 {</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			compatible = "hisilicon,hns-dsaf-v2";</div><div class='ctx'> 			mode = "6port-16rss";</div><div class='del'>-			reg = &lt;0x0 0xc5000000 0x0 0x890000</div><div class='del'>-			       0x0 0xc7000000 0x0 0x600000&gt;;</div><div class='add'>+			reg = &lt;0x0 0xc5000000 0x0 0x890000&gt;,</div><div class='add'>+			      &lt;0x0 0xc7000000 0x0 0x600000&gt;;</div><div class='ctx'> 			reg-names = "ppe-base", "dsaf-base";</div><div class='ctx'> 			interrupt-parent = &lt;&amp;mbigen_dsaf0&gt;;</div><div class='ctx'> 			subctrl-syscon = &lt;&amp;dsa_subctrl&gt;;</div><div class='hunk'>@@ -1427,7 +1490,7 @@</div><div class='ctx'> </div><div class='ctx'> 			port@1 {</div><div class='ctx'> 				reg = &lt;1&gt;;</div><div class='del'>-				serdes-syscon= &lt;&amp;serdes_ctrl&gt;;</div><div class='add'>+				serdes-syscon = &lt;&amp;serdes_ctrl&gt;;</div><div class='ctx'> 				cpld-syscon = &lt;&amp;dsa_cpld 0x4&gt;;</div><div class='ctx'> 				port-rst-offset = &lt;1&gt;;</div><div class='ctx'> 				port-mode-offset = &lt;1&gt;;</div><div class='hunk'>@@ -1438,7 +1501,7 @@</div><div class='ctx'> 			port@4 {</div><div class='ctx'> 				reg = &lt;4&gt;;</div><div class='ctx'> 				phy-handle = &lt;&amp;phy0&gt;;</div><div class='del'>-				serdes-syscon= &lt;&amp;serdes_ctrl&gt;;</div><div class='add'>+				serdes-syscon = &lt;&amp;serdes_ctrl&gt;;</div><div class='ctx'> 				port-rst-offset = &lt;4&gt;;</div><div class='ctx'> 				port-mode-offset = &lt;2&gt;;</div><div class='ctx'> 				mc-mac-mask = [ff f0 00 00 00 00];</div><div class='hunk'>@@ -1448,7 +1511,7 @@</div><div class='ctx'> 			port@5 {</div><div class='ctx'> 				reg = &lt;5&gt;;</div><div class='ctx'> 				phy-handle = &lt;&amp;phy1&gt;;</div><div class='del'>-				serdes-syscon= &lt;&amp;serdes_ctrl&gt;;</div><div class='add'>+				serdes-syscon = &lt;&amp;serdes_ctrl&gt;;</div><div class='ctx'> 				port-rst-offset = &lt;5&gt;;</div><div class='ctx'> 				port-mode-offset = &lt;3&gt;;</div><div class='ctx'> 				mc-mac-mask = [ff f0 00 00 00 00];</div><div class='hunk'>@@ -1456,42 +1519,6 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		eth0: ethernet@4{</div><div class='del'>-			compatible = "hisilicon,hns-nic-v2";</div><div class='del'>-			ae-handle = &lt;&amp;dsaf0&gt;;</div><div class='del'>-			port-idx-in-ae = &lt;4&gt;;</div><div class='del'>-			local-mac-address = [00 00 00 00 00 00];</div><div class='del'>-			status = "disabled";</div><div class='del'>-			dma-coherent;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		eth1: ethernet@5{</div><div class='del'>-			compatible = "hisilicon,hns-nic-v2";</div><div class='del'>-			ae-handle = &lt;&amp;dsaf0&gt;;</div><div class='del'>-			port-idx-in-ae = &lt;5&gt;;</div><div class='del'>-			local-mac-address = [00 00 00 00 00 00];</div><div class='del'>-			status = "disabled";</div><div class='del'>-			dma-coherent;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		eth2: ethernet@0{</div><div class='del'>-			compatible = "hisilicon,hns-nic-v2";</div><div class='del'>-			ae-handle = &lt;&amp;dsaf0&gt;;</div><div class='del'>-			port-idx-in-ae = &lt;0&gt;;</div><div class='del'>-			local-mac-address = [00 00 00 00 00 00];</div><div class='del'>-			status = "disabled";</div><div class='del'>-			dma-coherent;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		eth3: ethernet@1{</div><div class='del'>-			compatible = "hisilicon,hns-nic-v2";</div><div class='del'>-			ae-handle = &lt;&amp;dsaf0&gt;;</div><div class='del'>-			port-idx-in-ae = &lt;1&gt;;</div><div class='del'>-			local-mac-address = [00 00 00 00 00 00];</div><div class='del'>-			status = "disabled";</div><div class='del'>-			dma-coherent;</div><div class='del'>-		};</div><div class='del'>-</div><div class='ctx'> 		infiniband@c4000000 {</div><div class='ctx'> 			compatible = "hisilicon,hns-roce-v1";</div><div class='ctx'> 			reg = &lt;0x0 0xc4000000 0x0 0x100000&gt;;</div><div class='hunk'>@@ -1697,7 +1724,7 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		p0_pcie2_a: pcie@a00a0000 {</div><div class='add'>+		p0_pcie2_a: pcie@af800000 {</div><div class='ctx'> 			compatible = "hisilicon,hip07-pcie-ecam";</div><div class='ctx'> 			reg = &lt;0 0xaf800000 0 0x800000&gt;,</div><div class='ctx'> 			      &lt;0 0xa00a0000 0 0x10000&gt;;</div><div class='hunk'>@@ -1708,8 +1735,8 @@</div><div class='ctx'> 			#size-cells = &lt;2&gt;;</div><div class='ctx'> 			device_type = "pci";</div><div class='ctx'> 			dma-coherent;</div><div class='del'>-			ranges = &lt;0x02000000 0 0xa8000000 0 0xa8000000 0 0x77f0000</div><div class='del'>-				  0x01000000 0 0 0 0xaf7f0000 0 0x10000&gt;;</div><div class='add'>+			ranges = &lt;0x02000000 0 0xa8000000 0 0xa8000000 0 0x77f0000&gt;,</div><div class='add'>+				 &lt;0x01000000 0 0 0 0xaf7f0000 0 0x10000&gt;;</div><div class='ctx'> 			#interrupt-cells = &lt;1&gt;;</div><div class='ctx'> 			interrupt-map-mask = &lt;0xf800 0 0 7&gt;;</div><div class='ctx'> 			interrupt-map = &lt;0x0 0 0 1 &amp;mbigen_pcie2_a 671 4</div><div class='hunk'>@@ -1718,26 +1745,26 @@</div><div class='ctx'> 					 0x0 0 0 4 &amp;mbigen_pcie2_a 671 4&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='del'>-		p0_sec_a: crypto@d2000000 {</div><div class='add'>+		p0_sec_a: crypto@d0000000 {</div><div class='ctx'> 			compatible = "hisilicon,hip07-sec";</div><div class='del'>-			reg = &lt;0x0 0xd0000000 0x0 0x10000</div><div class='del'>-			       0x0 0xd2000000 0x0 0x10000</div><div class='del'>-			       0x0 0xd2010000 0x0 0x10000</div><div class='del'>-			       0x0 0xd2020000 0x0 0x10000</div><div class='del'>-			       0x0 0xd2030000 0x0 0x10000</div><div class='del'>-			       0x0 0xd2040000 0x0 0x10000</div><div class='del'>-			       0x0 0xd2050000 0x0 0x10000</div><div class='del'>-			       0x0 0xd2060000 0x0 0x10000</div><div class='del'>-			       0x0 0xd2070000 0x0 0x10000</div><div class='del'>-			       0x0 0xd2080000 0x0 0x10000</div><div class='del'>-			       0x0 0xd2090000 0x0 0x10000</div><div class='del'>-			       0x0 0xd20a0000 0x0 0x10000</div><div class='del'>-			       0x0 0xd20b0000 0x0 0x10000</div><div class='del'>-			       0x0 0xd20c0000 0x0 0x10000</div><div class='del'>-			       0x0 0xd20d0000 0x0 0x10000</div><div class='del'>-			       0x0 0xd20e0000 0x0 0x10000</div><div class='del'>-			       0x0 0xd20f0000 0x0 0x10000</div><div class='del'>-			       0x0 0xd2100000 0x0 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0xd0000000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0xd2000000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0xd2010000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0xd2020000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0xd2030000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0xd2040000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0xd2050000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0xd2060000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0xd2070000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0xd2080000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0xd2090000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0xd20a0000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0xd20b0000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0xd20c0000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0xd20d0000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0xd20e0000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0xd20f0000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0xd2100000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupt-parent = &lt;&amp;p0_mbigen_sec_a&gt;;</div><div class='ctx'> 			iommus = &lt;&amp;p0_smmu_alg_a 0x600&gt;;</div><div class='ctx'> 			dma-coherent;</div><div class='hunk'>@@ -1759,26 +1786,26 @@</div><div class='ctx'> 				     &lt;605 1&gt;, &lt;606 4&gt;,</div><div class='ctx'> 				     &lt;607 1&gt;, &lt;608 4&gt;;</div><div class='ctx'> 		};</div><div class='del'>-		p0_sec_b: crypto@8,d2000000 {</div><div class='add'>+		p0_sec_b: crypto@8d0000000 {</div><div class='ctx'> 			compatible = "hisilicon,hip07-sec";</div><div class='del'>-			reg = &lt;0x8 0xd0000000 0x0 0x10000</div><div class='del'>-			       0x8 0xd2000000 0x0 0x10000</div><div class='del'>-			       0x8 0xd2010000 0x0 0x10000</div><div class='del'>-			       0x8 0xd2020000 0x0 0x10000</div><div class='del'>-			       0x8 0xd2030000 0x0 0x10000</div><div class='del'>-			       0x8 0xd2040000 0x0 0x10000</div><div class='del'>-			       0x8 0xd2050000 0x0 0x10000</div><div class='del'>-			       0x8 0xd2060000 0x0 0x10000</div><div class='del'>-			       0x8 0xd2070000 0x0 0x10000</div><div class='del'>-			       0x8 0xd2080000 0x0 0x10000</div><div class='del'>-			       0x8 0xd2090000 0x0 0x10000</div><div class='del'>-			       0x8 0xd20a0000 0x0 0x10000</div><div class='del'>-			       0x8 0xd20b0000 0x0 0x10000</div><div class='del'>-			       0x8 0xd20c0000 0x0 0x10000</div><div class='del'>-			       0x8 0xd20d0000 0x0 0x10000</div><div class='del'>-			       0x8 0xd20e0000 0x0 0x10000</div><div class='del'>-			       0x8 0xd20f0000 0x0 0x10000</div><div class='del'>-			       0x8 0xd2100000 0x0 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x8 0xd0000000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x8 0xd2000000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x8 0xd2010000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x8 0xd2020000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x8 0xd2030000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x8 0xd2040000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x8 0xd2050000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x8 0xd2060000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x8 0xd2070000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x8 0xd2080000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x8 0xd2090000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x8 0xd20a0000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x8 0xd20b0000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x8 0xd20c0000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x8 0xd20d0000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x8 0xd20e0000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x8 0xd20f0000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x8 0xd2100000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupt-parent = &lt;&amp;p0_mbigen_sec_b&gt;;</div><div class='ctx'> 			iommus = &lt;&amp;p0_smmu_alg_b 0x600&gt;;</div><div class='ctx'> 			dma-coherent;</div><div class='hunk'>@@ -1800,26 +1827,26 @@</div><div class='ctx'> 				     &lt;605 1&gt;, &lt;606 4&gt;,</div><div class='ctx'> 				     &lt;607 1&gt;, &lt;608 4&gt;;</div><div class='ctx'> 		};</div><div class='del'>-		p1_sec_a: crypto@400,d2000000 {</div><div class='add'>+		p1_sec_a: crypto@400d0000000 {</div><div class='ctx'> 			compatible = "hisilicon,hip07-sec";</div><div class='del'>-			reg = &lt;0x400 0xd0000000 0x0 0x10000</div><div class='del'>-			       0x400 0xd2000000 0x0 0x10000</div><div class='del'>-			       0x400 0xd2010000 0x0 0x10000</div><div class='del'>-			       0x400 0xd2020000 0x0 0x10000</div><div class='del'>-			       0x400 0xd2030000 0x0 0x10000</div><div class='del'>-			       0x400 0xd2040000 0x0 0x10000</div><div class='del'>-			       0x400 0xd2050000 0x0 0x10000</div><div class='del'>-			       0x400 0xd2060000 0x0 0x10000</div><div class='del'>-			       0x400 0xd2070000 0x0 0x10000</div><div class='del'>-			       0x400 0xd2080000 0x0 0x10000</div><div class='del'>-			       0x400 0xd2090000 0x0 0x10000</div><div class='del'>-			       0x400 0xd20a0000 0x0 0x10000</div><div class='del'>-			       0x400 0xd20b0000 0x0 0x10000</div><div class='del'>-			       0x400 0xd20c0000 0x0 0x10000</div><div class='del'>-			       0x400 0xd20d0000 0x0 0x10000</div><div class='del'>-			       0x400 0xd20e0000 0x0 0x10000</div><div class='del'>-			       0x400 0xd20f0000 0x0 0x10000</div><div class='del'>-			       0x400 0xd2100000 0x0 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x400 0xd0000000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x400 0xd2000000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x400 0xd2010000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x400 0xd2020000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x400 0xd2030000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x400 0xd2040000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x400 0xd2050000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x400 0xd2060000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x400 0xd2070000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x400 0xd2080000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x400 0xd2090000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x400 0xd20a0000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x400 0xd20b0000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x400 0xd20c0000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x400 0xd20d0000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x400 0xd20e0000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x400 0xd20f0000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x400 0xd2100000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupt-parent = &lt;&amp;p1_mbigen_sec_a&gt;;</div><div class='ctx'> 			iommus = &lt;&amp;p1_smmu_alg_a 0x600&gt;;</div><div class='ctx'> 			dma-coherent;</div><div class='hunk'>@@ -1841,26 +1868,26 @@</div><div class='ctx'> 				     &lt;605 1&gt;, &lt;606 4&gt;,</div><div class='ctx'> 				     &lt;607 1&gt;, &lt;608 4&gt;;</div><div class='ctx'> 		};</div><div class='del'>-		p1_sec_b: crypto@408,d2000000 {</div><div class='add'>+		p1_sec_b: crypto@408d0000000 {</div><div class='ctx'> 			compatible = "hisilicon,hip07-sec";</div><div class='del'>-			reg = &lt;0x408 0xd0000000 0x0 0x10000</div><div class='del'>-			       0x408 0xd2000000 0x0 0x10000</div><div class='del'>-			       0x408 0xd2010000 0x0 0x10000</div><div class='del'>-			       0x408 0xd2020000 0x0 0x10000</div><div class='del'>-			       0x408 0xd2030000 0x0 0x10000</div><div class='del'>-			       0x408 0xd2040000 0x0 0x10000</div><div class='del'>-			       0x408 0xd2050000 0x0 0x10000</div><div class='del'>-			       0x408 0xd2060000 0x0 0x10000</div><div class='del'>-			       0x408 0xd2070000 0x0 0x10000</div><div class='del'>-			       0x408 0xd2080000 0x0 0x10000</div><div class='del'>-			       0x408 0xd2090000 0x0 0x10000</div><div class='del'>-			       0x408 0xd20a0000 0x0 0x10000</div><div class='del'>-			       0x408 0xd20b0000 0x0 0x10000</div><div class='del'>-			       0x408 0xd20c0000 0x0 0x10000</div><div class='del'>-			       0x408 0xd20d0000 0x0 0x10000</div><div class='del'>-			       0x408 0xd20e0000 0x0 0x10000</div><div class='del'>-			       0x408 0xd20f0000 0x0 0x10000</div><div class='del'>-			       0x408 0xd2100000 0x0 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x408 0xd0000000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x408 0xd2000000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x408 0xd2010000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x408 0xd2020000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x408 0xd2030000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x408 0xd2040000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x408 0xd2050000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x408 0xd2060000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x408 0xd2070000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x408 0xd2080000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x408 0xd2090000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x408 0xd20a0000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x408 0xd20b0000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x408 0xd20c0000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x408 0xd20d0000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x408 0xd20e0000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x408 0xd20f0000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x408 0xd2100000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupt-parent = &lt;&amp;p1_mbigen_sec_b&gt;;</div><div class='ctx'> 			iommus = &lt;&amp;p1_smmu_alg_b 0x600&gt;;</div><div class='ctx'> 			dma-coherent;</div><div class='head'>diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile<br/>index 40cb16e8c814..a117268267ee 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/intel/Makefile?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/intel/Makefile</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/intel/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/intel/Makefile</a></div><div class='hunk'>@@ -1,3 +1,10 @@</div><div class='ctx'> # SPDX-License-Identifier: GPL-2.0-only</div><div class='del'>-dtb-$(CONFIG_ARCH_AGILEX) += socfpga_agilex_socdk.dtb \</div><div class='del'>-			     socfpga_agilex_socdk_nand.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \</div><div class='add'>+				socfpga_agilex_socdk.dtb \</div><div class='add'>+				socfpga_agilex_socdk_nand.dtb \</div><div class='add'>+				socfpga_agilex3_socdk.dtb \</div><div class='add'>+				socfpga_agilex5_socdk.dtb \</div><div class='add'>+				socfpga_agilex5_socdk_013b.dtb \</div><div class='add'>+				socfpga_agilex5_socdk_nand.dtb \</div><div class='add'>+				socfpga_n5x_socdk.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb</div><div class='head'>diff --git a/arch/arm64/boot/dts/intel/keembay-evm.dts b/arch/arm64/boot/dts/intel/keembay-evm.dts<br/>new file mode 100644<br/>index 000000000000..466c85363a29<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/intel/keembay-evm.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/intel/keembay-evm.dts</a></div><div class='hunk'>@@ -0,0 +1,37 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2020, Intel Corporation</div><div class='add'>+ *</div><div class='add'>+ * Device tree describing Keem Bay EVM board.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "keembay-soc.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Keem Bay EVM";</div><div class='add'>+	compatible = "intel,keembay-evm", "intel,keembay";</div><div class='add'>+</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart3;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@80000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		/* 2GB of DDR memory. */</div><div class='add'>+		reg = &lt;0x0 0x80000000 0x0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/intel/keembay-soc.dtsi b/arch/arm64/boot/dts/intel/keembay-soc.dtsi<br/>new file mode 100644<br/>index 000000000000..ae00e9e54e82<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/intel/keembay-soc.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/intel/keembay-soc.dtsi</a></div><div class='hunk'>@@ -0,0 +1,123 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2020, Intel Corporation.</div><div class='add'>+ *</div><div class='add'>+ * Device tree describing Keem Bay SoC.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu@0 {</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu@1 {</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x1&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu@2 {</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x2&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu@3 {</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x3&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-0.2";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gic: interrupt-controller@20500000 {</div><div class='add'>+		compatible = "arm,gic-v3";</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;3&gt;;</div><div class='add'>+		reg = &lt;0x0 0x20500000 0x0 0x20000&gt;,	/* GICD */</div><div class='add'>+		      &lt;0x0 0x20580000 0x0 0x80000&gt;;	/* GICR */</div><div class='add'>+		/* VGIC maintenance interrupt */</div><div class='add'>+		interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		/* Secure, non-secure, virtual, and hypervisor */</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu {</div><div class='add'>+		compatible = "arm,cortex-a53-pmu";</div><div class='add'>+		interrupts = &lt;GIC_PPI 0x7 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		uart0: serial@20150000 {</div><div class='add'>+			compatible = "snps,dw-apb-uart";</div><div class='add'>+			reg = &lt;0x0 0x20150000 0x0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clock-frequency = &lt;24000000&gt;;</div><div class='add'>+			reg-shift = &lt;2&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart1: serial@20160000 {</div><div class='add'>+			compatible = "snps,dw-apb-uart";</div><div class='add'>+			reg = &lt;0x0 0x20160000 0x0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clock-frequency = &lt;24000000&gt;;</div><div class='add'>+			reg-shift = &lt;2&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart2: serial@20170000 {</div><div class='add'>+			compatible = "snps,dw-apb-uart";</div><div class='add'>+			reg = &lt;0x0 0x20170000 0x0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clock-frequency = &lt;24000000&gt;;</div><div class='add'>+			reg-shift = &lt;2&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart3: serial@20180000 {</div><div class='add'>+			compatible = "snps,dw-apb-uart";</div><div class='add'>+			reg = &lt;0x0 0x20180000 0x0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clock-frequency = &lt;24000000&gt;;</div><div class='add'>+			reg-shift = &lt;2&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi<br/>index d8c44d3ca15a..0dfbafde8822 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/intel/socfpga_agilex.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/intel/socfpga_agilex.dtsi</a></div><div class='hunk'>@@ -6,6 +6,8 @@</div><div class='ctx'> /dts-v1/;</div><div class='ctx'> #include &lt;dt-bindings/reset/altr,rst-mgr-s10.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/agilex-clock.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	compatible = "intel,socfpga-agilex";</div><div class='hunk'>@@ -19,7 +21,7 @@</div><div class='ctx'> </div><div class='ctx'> 		service_reserved: svcbuffer@0 {</div><div class='ctx'> 			compatible = "shared-dma-pool";</div><div class='del'>-			reg = &lt;0x0 0x0 0x0 0x1000000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x0 0x0 0x2000000&gt;;</div><div class='ctx'> 			alignment = &lt;0x1000&gt;;</div><div class='ctx'> 			no-map;</div><div class='ctx'> 		};</div><div class='hunk'>@@ -58,12 +60,31 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	firmware {</div><div class='add'>+		svc {</div><div class='add'>+			compatible = "intel,agilex-svc";</div><div class='add'>+			method = "smc";</div><div class='add'>+			memory-region = &lt;&amp;service_reserved&gt;;</div><div class='add'>+</div><div class='add'>+			fpga_mgr: fpga-mgr {</div><div class='add'>+				compatible = "intel,agilex-soc-fpga-mgr";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fpga-region {</div><div class='add'>+		compatible = "fpga-region";</div><div class='add'>+		#address-cells = &lt;0x2&gt;;</div><div class='add'>+		#size-cells = &lt;0x2&gt;;</div><div class='add'>+		fpga-mgr = &lt;&amp;fpga_mgr&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	pmu {</div><div class='del'>-		compatible = "arm,armv8-pmuv3";</div><div class='del'>-		interrupts = &lt;0 170 4&gt;,</div><div class='del'>-			     &lt;0 171 4&gt;,</div><div class='del'>-			     &lt;0 172 4&gt;,</div><div class='del'>-			     &lt;0 173 4&gt;;</div><div class='add'>+		compatible = "arm,cortex-a53-pmu";</div><div class='add'>+		interrupts = &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		interrupt-affinity = &lt;&amp;cpu0&gt;,</div><div class='ctx'> 				     &lt;&amp;cpu1&gt;,</div><div class='ctx'> 				     &lt;&amp;cpu2&gt;,</div><div class='hunk'>@@ -76,17 +97,65 @@</div><div class='ctx'> 		method = "smc";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	intc: intc@fffc1000 {</div><div class='add'>+	intc: interrupt-controller@fffc1000 {</div><div class='ctx'> 		compatible = "arm,gic-400", "arm,cortex-a15-gic";</div><div class='ctx'> 		#interrupt-cells = &lt;3&gt;;</div><div class='ctx'> 		interrupt-controller;</div><div class='add'>+		interrupt-parent = &lt;&amp;intc&gt;;</div><div class='ctx'> 		reg = &lt;0x0 0xfffc1000 0x0 0x1000&gt;,</div><div class='ctx'> 		      &lt;0x0 0xfffc2000 0x0 0x2000&gt;,</div><div class='ctx'> 		      &lt;0x0 0xfffc4000 0x0 0x2000&gt;,</div><div class='ctx'> 		      &lt;0x0 0xfffc6000 0x0 0x2000&gt;;</div><div class='add'>+		/* VGIC maintenance interrupt */</div><div class='add'>+		interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clocks {</div><div class='add'>+		cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			clock-frequency = &lt;200000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cb_intosc_ls_clk: cb-intosc-ls-clk {</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			clock-frequency = &lt;400000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		f2s_free_clk: f2s-free-clk {</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			clock-frequency = &lt;100000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		osc1: osc1 {</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qspi_clk: qspi-clk {</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			clock-frequency = &lt;200000000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupt-parent = &lt;&amp;intc&gt;;</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	soc {</div><div class='add'>+	usbphy0: usbphy {</div><div class='add'>+		#phy-cells = &lt;0&gt;;</div><div class='add'>+		compatible = "usb-nop-xceiv";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc@0 {</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;1&gt;;</div><div class='ctx'> 		compatible = "simple-bus";</div><div class='hunk'>@@ -94,58 +163,64 @@</div><div class='ctx'> 		interrupt-parent = &lt;&amp;intc&gt;;</div><div class='ctx'> 		ranges = &lt;0 0 0 0xffffffff&gt;;</div><div class='ctx'> </div><div class='del'>-		base_fpga_region {</div><div class='del'>-			#address-cells = &lt;0x1&gt;;</div><div class='del'>-			#size-cells = &lt;0x1&gt;;</div><div class='del'>-			compatible = "fpga-region";</div><div class='del'>-			fpga-mgr = &lt;&amp;fpga_mgr&gt;;</div><div class='add'>+		clkmgr: clock-controller@ffd10000 {</div><div class='add'>+			compatible = "intel,agilex-clkmgr";</div><div class='add'>+			reg = &lt;0xffd10000 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;osc1&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		gmac0: ethernet@ff800000 {</div><div class='ctx'> 			compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";</div><div class='ctx'> 			reg = &lt;0xff800000 0x2000&gt;;</div><div class='del'>-			interrupts = &lt;0 90 4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			interrupt-names = "macirq";</div><div class='ctx'> 			mac-address = [00 00 00 00 00 00];</div><div class='ctx'> 			resets = &lt;&amp;rst EMAC0_RESET&gt;, &lt;&amp;rst EMAC0_OCP_RESET&gt;;</div><div class='del'>-			reset-names = "stmmaceth", "stmmaceth-ocp";</div><div class='add'>+			reset-names = "stmmaceth", "ahb";</div><div class='ctx'> 			tx-fifo-depth = &lt;16384&gt;;</div><div class='ctx'> 			rx-fifo-depth = &lt;16384&gt;;</div><div class='ctx'> 			snps,multicast-filter-bins = &lt;256&gt;;</div><div class='ctx'> 			iommus = &lt;&amp;smmu 1&gt;;</div><div class='ctx'> 			altr,sysmgr-syscon = &lt;&amp;sysmgr 0x44 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX_EMAC0_CLK&gt;, &lt;&amp;clkmgr AGILEX_EMAC_PTP_CLK&gt;;</div><div class='add'>+			clock-names = "stmmaceth", "ptp_ref";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		gmac1: ethernet@ff802000 {</div><div class='ctx'> 			compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";</div><div class='ctx'> 			reg = &lt;0xff802000 0x2000&gt;;</div><div class='del'>-			interrupts = &lt;0 91 4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			interrupt-names = "macirq";</div><div class='ctx'> 			mac-address = [00 00 00 00 00 00];</div><div class='ctx'> 			resets = &lt;&amp;rst EMAC1_RESET&gt;, &lt;&amp;rst EMAC1_OCP_RESET&gt;;</div><div class='del'>-			reset-names = "stmmaceth", "stmmaceth-ocp";</div><div class='add'>+			reset-names = "stmmaceth", "ahb";</div><div class='ctx'> 			tx-fifo-depth = &lt;16384&gt;;</div><div class='ctx'> 			rx-fifo-depth = &lt;16384&gt;;</div><div class='ctx'> 			snps,multicast-filter-bins = &lt;256&gt;;</div><div class='ctx'> 			iommus = &lt;&amp;smmu 2&gt;;</div><div class='del'>-			altr,sysmgr-syscon = &lt;&amp;sysmgr 0x48 8&gt;;</div><div class='add'>+			altr,sysmgr-syscon = &lt;&amp;sysmgr 0x48 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX_EMAC1_CLK&gt;, &lt;&amp;clkmgr AGILEX_EMAC_PTP_CLK&gt;;</div><div class='add'>+			clock-names = "stmmaceth", "ptp_ref";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		gmac2: ethernet@ff804000 {</div><div class='ctx'> 			compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";</div><div class='ctx'> 			reg = &lt;0xff804000 0x2000&gt;;</div><div class='del'>-			interrupts = &lt;0 92 4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			interrupt-names = "macirq";</div><div class='ctx'> 			mac-address = [00 00 00 00 00 00];</div><div class='ctx'> 			resets = &lt;&amp;rst EMAC2_RESET&gt;, &lt;&amp;rst EMAC2_OCP_RESET&gt;;</div><div class='del'>-			reset-names = "stmmaceth", "stmmaceth-ocp";</div><div class='add'>+			reset-names = "stmmaceth", "ahb";</div><div class='ctx'> 			tx-fifo-depth = &lt;16384&gt;;</div><div class='ctx'> 			rx-fifo-depth = &lt;16384&gt;;</div><div class='ctx'> 			snps,multicast-filter-bins = &lt;256&gt;;</div><div class='ctx'> 			iommus = &lt;&amp;smmu 3&gt;;</div><div class='del'>-			altr,sysmgr-syscon = &lt;&amp;sysmgr 0x4c 16&gt;;</div><div class='add'>+			altr,sysmgr-syscon = &lt;&amp;sysmgr 0x4c 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX_EMAC2_CLK&gt;, &lt;&amp;clkmgr AGILEX_EMAC_PTP_CLK&gt;;</div><div class='add'>+			clock-names = "stmmaceth", "ptp_ref";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -165,7 +240,7 @@</div><div class='ctx'> 				reg = &lt;0&gt;;</div><div class='ctx'> 				interrupt-controller;</div><div class='ctx'> 				#interrupt-cells = &lt;2&gt;;</div><div class='del'>-				interrupts = &lt;0 110 4&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -185,7 +260,7 @@</div><div class='ctx'> 				reg = &lt;0&gt;;</div><div class='ctx'> 				interrupt-controller;</div><div class='ctx'> 				#interrupt-cells = &lt;2&gt;;</div><div class='del'>-				interrupts = &lt;0 111 4&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -194,8 +269,9 @@</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			compatible = "snps,designware-i2c";</div><div class='ctx'> 			reg = &lt;0xffc02800 0x100&gt;;</div><div class='del'>-			interrupts = &lt;0 103 4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			resets = &lt;&amp;rst I2C0_RESET&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX_L4_SP_CLK&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -204,8 +280,9 @@</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			compatible = "snps,designware-i2c";</div><div class='ctx'> 			reg = &lt;0xffc02900 0x100&gt;;</div><div class='del'>-			interrupts = &lt;0 104 4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			resets = &lt;&amp;rst I2C1_RESET&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX_L4_SP_CLK&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -214,8 +291,9 @@</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			compatible = "snps,designware-i2c";</div><div class='ctx'> 			reg = &lt;0xffc02a00 0x100&gt;;</div><div class='del'>-			interrupts = &lt;0 105 4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			resets = &lt;&amp;rst I2C2_RESET&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX_L4_SP_CLK&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -224,8 +302,9 @@</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			compatible = "snps,designware-i2c";</div><div class='ctx'> 			reg = &lt;0xffc02b00 0x100&gt;;</div><div class='del'>-			interrupts = &lt;0 106 4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			resets = &lt;&amp;rst I2C3_RESET&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX_L4_SP_CLK&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -234,32 +313,41 @@</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			compatible = "snps,designware-i2c";</div><div class='ctx'> 			reg = &lt;0xffc02c00 0x100&gt;;</div><div class='del'>-			interrupts = &lt;0 107 4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			resets = &lt;&amp;rst I2C4_RESET&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX_L4_SP_CLK&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		mmc: dwmmc0@ff808000 {</div><div class='add'>+		mmc: mmc@ff808000 {</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			compatible = "altr,socfpga-dw-mshc";</div><div class='ctx'> 			reg = &lt;0xff808000 0x1000&gt;;</div><div class='del'>-			interrupts = &lt;0 96 4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			fifo-depth = &lt;0x400&gt;;</div><div class='ctx'> 			resets = &lt;&amp;rst SDMMC_RESET&gt;;</div><div class='ctx'> 			reset-names = "reset";</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX_L4_MP_CLK&gt;,</div><div class='add'>+				 &lt;&amp;clkmgr AGILEX_SDMMC_CLK&gt;;</div><div class='add'>+			clock-names = "biu", "ciu";</div><div class='ctx'> 			iommus = &lt;&amp;smmu 5&gt;;</div><div class='add'>+			altr,sysmgr-syscon = &lt;&amp;sysmgr 0x28 4&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		nand: nand@ffb90000 {</div><div class='add'>+		nand: nand-controller@ffb90000 {</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			compatible = "altr,socfpga-denali-nand";</div><div class='ctx'> 			reg = &lt;0xffb90000 0x10000&gt;,</div><div class='ctx'> 			      &lt;0xffb80000 0x1000&gt;;</div><div class='ctx'> 			reg-names = "nand_data", "denali_reg";</div><div class='del'>-			interrupts = &lt;0 97 4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX_NAND_CLK&gt;,</div><div class='add'>+				 &lt;&amp;clkmgr AGILEX_NAND_X_CLK&gt;,</div><div class='add'>+				 &lt;&amp;clkmgr AGILEX_NAND_ECC_CLK&gt;;</div><div class='add'>+			clock-names = "nand", "nand_x", "ecc";</div><div class='ctx'> 			resets = &lt;&amp;rst NAND_RESET&gt;, &lt;&amp;rst NAND_OCP_RESET&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='hunk'>@@ -267,31 +355,49 @@</div><div class='ctx'> 		ocram: sram@ffe00000 {</div><div class='ctx'> 			compatible = "mmio-sram";</div><div class='ctx'> 			reg = &lt;0xffe00000 0x40000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges = &lt;0 0xffe00000 0x40000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		pdma: pdma@ffda0000 {</div><div class='add'>+		pdma: dma-controller@ffda0000 {</div><div class='ctx'> 			compatible = "arm,pl330", "arm,primecell";</div><div class='ctx'> 			reg = &lt;0xffda0000 0x1000&gt;;</div><div class='del'>-			interrupts = &lt;0 81 4&gt;,</div><div class='del'>-				     &lt;0 82 4&gt;,</div><div class='del'>-				     &lt;0 83 4&gt;,</div><div class='del'>-				     &lt;0 84 4&gt;,</div><div class='del'>-				     &lt;0 85 4&gt;,</div><div class='del'>-				     &lt;0 86 4&gt;,</div><div class='del'>-				     &lt;0 87 4&gt;,</div><div class='del'>-				     &lt;0 88 4&gt;,</div><div class='del'>-				     &lt;0 89 4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			#dma-cells = &lt;1&gt;;</div><div class='del'>-			#dma-channels = &lt;8&gt;;</div><div class='del'>-			#dma-requests = &lt;32&gt;;</div><div class='ctx'> 			resets = &lt;&amp;rst DMA_RESET&gt;, &lt;&amp;rst DMA_OCP_RESET&gt;;</div><div class='ctx'> 			reset-names = "dma", "dma-ocp";</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX_L4_MAIN_CLK&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl0: pinctrl@ffd13000 {</div><div class='add'>+			compatible = "pinctrl-single";</div><div class='add'>+			#pinctrl-cells = &lt;1&gt;;</div><div class='add'>+			reg = &lt;0xffd13000 0xa0&gt;;</div><div class='add'>+			pinctrl-single,register-width = &lt;32&gt;;</div><div class='add'>+			pinctrl-single,function-mask = &lt;0x0000000f&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl1: pinctrl@ffd13100 {</div><div class='add'>+			compatible = "pinctrl-single";</div><div class='add'>+			#pinctrl-cells = &lt;1&gt;;</div><div class='add'>+			reg = &lt;0xffd13100 0x20&gt;;</div><div class='add'>+			pinctrl-single,register-width = &lt;32&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		rst: rstmgr@ffd11000 {</div><div class='del'>-			#reset-cells = &lt;1&gt;;</div><div class='del'>-			compatible = "altr,stratix10-rst-mgr";</div><div class='add'>+			compatible = "altr,stratix10-rst-mgr", "altr,rst-mgr";</div><div class='ctx'> 			reg = &lt;0xffd11000 0x100&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		smmu: iommu@fa000000 {</div><div class='hunk'>@@ -300,18 +406,47 @@</div><div class='ctx'> 			#global-interrupts = &lt;2&gt;;</div><div class='ctx'> 			#iommu-cells = &lt;1&gt;;</div><div class='ctx'> 			interrupt-parent = &lt;&amp;intc&gt;;</div><div class='del'>-			interrupts = &lt;0 128 4&gt;,	/* Global Secure Fault */</div><div class='del'>-				&lt;0 129 4&gt;, /* Global Non-secure Fault */</div><div class='add'>+			/* Global Secure Fault */</div><div class='add'>+			interrupts = &lt;GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				/* Global Non-secure Fault */</div><div class='add'>+				&lt;GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 				/* Non-secure Context Interrupts (32) */</div><div class='del'>-				&lt;0 138 4&gt;, &lt;0 139 4&gt;, &lt;0 140 4&gt;, &lt;0 141 4&gt;,</div><div class='del'>-				&lt;0 142 4&gt;, &lt;0 143 4&gt;, &lt;0 144 4&gt;, &lt;0 145 4&gt;,</div><div class='del'>-				&lt;0 146 4&gt;, &lt;0 147 4&gt;, &lt;0 148 4&gt;, &lt;0 149 4&gt;,</div><div class='del'>-				&lt;0 150 4&gt;, &lt;0 151 4&gt;, &lt;0 152 4&gt;, &lt;0 153 4&gt;,</div><div class='del'>-				&lt;0 154 4&gt;, &lt;0 155 4&gt;, &lt;0 156 4&gt;, &lt;0 157 4&gt;,</div><div class='del'>-				&lt;0 158 4&gt;, &lt;0 159 4&gt;, &lt;0 160 4&gt;, &lt;0 161 4&gt;,</div><div class='del'>-				&lt;0 162 4&gt;, &lt;0 163 4&gt;, &lt;0 164 4&gt;, &lt;0 165 4&gt;,</div><div class='del'>-				&lt;0 166 4&gt;, &lt;0 167 4&gt;, &lt;0 168 4&gt;, &lt;0 169 4&gt;;</div><div class='add'>+				&lt;GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			stream-match-mask = &lt;0x7ff0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX_MPU_CCU_CLK&gt;,</div><div class='add'>+				 &lt;&amp;clkmgr AGILEX_L3_MAIN_FREE_CLK&gt;,</div><div class='add'>+				 &lt;&amp;clkmgr AGILEX_L4_MAIN_CLK&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -320,10 +455,14 @@</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			reg = &lt;0xffda4000 0x1000&gt;;</div><div class='del'>-			interrupts = &lt;0 99 4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			resets = &lt;&amp;rst SPIM0_RESET&gt;;</div><div class='add'>+			reset-names = "spi";</div><div class='ctx'> 			reg-io-width = &lt;4&gt;;</div><div class='ctx'> 			num-cs = &lt;4&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX_L4_MAIN_CLK&gt;;</div><div class='add'>+			dmas = &lt;&amp;pdma 16&gt;, &lt;&amp;pdma 17&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -332,10 +471,14 @@</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			reg = &lt;0xffda5000 0x1000&gt;;</div><div class='del'>-			interrupts = &lt;0 100 4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			resets = &lt;&amp;rst SPIM1_RESET&gt;;</div><div class='add'>+			reset-names = "spi";</div><div class='ctx'> 			reg-io-width = &lt;4&gt;;</div><div class='ctx'> 			num-cs = &lt;4&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX_L4_MAIN_CLK&gt;;</div><div class='add'>+			dmas = &lt;&amp;pdma 20&gt;, &lt;&amp;pdma 21&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -344,118 +487,120 @@</div><div class='ctx'> 			reg = &lt;0xffd12000 0x500&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		/* Local timer */</div><div class='del'>-		timer {</div><div class='del'>-			compatible = "arm,armv8-timer";</div><div class='del'>-			interrupts = &lt;1 13 0xf08&gt;,</div><div class='del'>-				     &lt;1 14 0xf08&gt;,</div><div class='del'>-				     &lt;1 11 0xf08&gt;,</div><div class='del'>-				     &lt;1 10 0xf08&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='ctx'> 		timer0: timer0@ffc03000 {</div><div class='ctx'> 			compatible = "snps,dw-apb-timer";</div><div class='del'>-			interrupts = &lt;0 113 4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			reg = &lt;0xffc03000 0x100&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX_L4_SP_CLK&gt;;</div><div class='add'>+			clock-names = "timer";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		timer1: timer1@ffc03100 {</div><div class='ctx'> 			compatible = "snps,dw-apb-timer";</div><div class='del'>-			interrupts = &lt;0 114 4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			reg = &lt;0xffc03100 0x100&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX_L4_SP_CLK&gt;;</div><div class='add'>+			clock-names = "timer";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		timer2: timer2@ffd00000 {</div><div class='ctx'> 			compatible = "snps,dw-apb-timer";</div><div class='del'>-			interrupts = &lt;0 115 4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			reg = &lt;0xffd00000 0x100&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX_L4_SP_CLK&gt;;</div><div class='add'>+			clock-names = "timer";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		timer3: timer3@ffd00100 {</div><div class='ctx'> 			compatible = "snps,dw-apb-timer";</div><div class='del'>-			interrupts = &lt;0 116 4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			reg = &lt;0xffd00100 0x100&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX_L4_SP_CLK&gt;;</div><div class='add'>+			clock-names = "timer";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		uart0: serial0@ffc02000 {</div><div class='add'>+		uart0: serial@ffc02000 {</div><div class='ctx'> 			compatible = "snps,dw-apb-uart";</div><div class='ctx'> 			reg = &lt;0xffc02000 0x100&gt;;</div><div class='del'>-			interrupts = &lt;0 108 4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			reg-shift = &lt;2&gt;;</div><div class='ctx'> 			reg-io-width = &lt;4&gt;;</div><div class='ctx'> 			resets = &lt;&amp;rst UART0_RESET&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX_L4_SP_CLK&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		uart1: serial1@ffc02100 {</div><div class='add'>+		uart1: serial@ffc02100 {</div><div class='ctx'> 			compatible = "snps,dw-apb-uart";</div><div class='ctx'> 			reg = &lt;0xffc02100 0x100&gt;;</div><div class='del'>-			interrupts = &lt;0 109 4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			reg-shift = &lt;2&gt;;</div><div class='ctx'> 			reg-io-width = &lt;4&gt;;</div><div class='ctx'> 			resets = &lt;&amp;rst UART1_RESET&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX_L4_SP_CLK&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		usbphy0: usbphy@0 {</div><div class='del'>-			#phy-cells = &lt;0&gt;;</div><div class='del'>-			compatible = "usb-nop-xceiv";</div><div class='del'>-			status = "okay";</div><div class='del'>-		};</div><div class='del'>-</div><div class='ctx'> 		usb0: usb@ffb00000 {</div><div class='del'>-			compatible = "snps,dwc2";</div><div class='add'>+			compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2";</div><div class='ctx'> 			reg = &lt;0xffb00000 0x40000&gt;;</div><div class='del'>-			interrupts = &lt;0 93 4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			phys = &lt;&amp;usbphy0&gt;;</div><div class='ctx'> 			phy-names = "usb2-phy";</div><div class='ctx'> 			resets = &lt;&amp;rst USB0_RESET&gt;, &lt;&amp;rst USB0_OCP_RESET&gt;;</div><div class='ctx'> 			reset-names = "dwc2", "dwc2-ecc";</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX_USB_CLK&gt;;</div><div class='add'>+			clock-names = "otg";</div><div class='ctx'> 			iommus = &lt;&amp;smmu 6&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		usb1: usb@ffb40000 {</div><div class='del'>-			compatible = "snps,dwc2";</div><div class='add'>+			compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2";</div><div class='ctx'> 			reg = &lt;0xffb40000 0x40000&gt;;</div><div class='del'>-			interrupts = &lt;0 94 4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			phys = &lt;&amp;usbphy0&gt;;</div><div class='ctx'> 			phy-names = "usb2-phy";</div><div class='ctx'> 			resets = &lt;&amp;rst USB1_RESET&gt;, &lt;&amp;rst USB1_OCP_RESET&gt;;</div><div class='ctx'> 			reset-names = "dwc2", "dwc2-ecc";</div><div class='ctx'> 			iommus = &lt;&amp;smmu 7&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX_USB_CLK&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		watchdog0: watchdog@ffd00200 {</div><div class='ctx'> 			compatible = "snps,dw-wdt";</div><div class='ctx'> 			reg = &lt;0xffd00200 0x100&gt;;</div><div class='del'>-			interrupts = &lt;0 117 4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			resets = &lt;&amp;rst WATCHDOG0_RESET&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX_L4_SYS_FREE_CLK&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		watchdog1: watchdog@ffd00300 {</div><div class='ctx'> 			compatible = "snps,dw-wdt";</div><div class='ctx'> 			reg = &lt;0xffd00300 0x100&gt;;</div><div class='del'>-			interrupts = &lt;0 118 4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			resets = &lt;&amp;rst WATCHDOG1_RESET&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX_L4_SYS_FREE_CLK&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		watchdog2: watchdog@ffd00400 {</div><div class='ctx'> 			compatible = "snps,dw-wdt";</div><div class='ctx'> 			reg = &lt;0xffd00400 0x100&gt;;</div><div class='del'>-			interrupts = &lt;0 125 4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			resets = &lt;&amp;rst WATCHDOG2_RESET&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX_L4_SYS_FREE_CLK&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		watchdog3: watchdog@ffd00500 {</div><div class='ctx'> 			compatible = "snps,dw-wdt";</div><div class='ctx'> 			reg = &lt;0xffd00500 0x100&gt;;</div><div class='del'>-			interrupts = &lt;0 126 4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			resets = &lt;&amp;rst WATCHDOG3_RESET&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX_L4_SYS_FREE_CLK&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -470,7 +615,7 @@</div><div class='ctx'> 			altr,sysmgr-syscon = &lt;&amp;sysmgr&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;1&gt;;</div><div class='del'>-			interrupts = &lt;0 15 4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			interrupt-controller;</div><div class='ctx'> 			#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 			ranges;</div><div class='hunk'>@@ -478,7 +623,7 @@</div><div class='ctx'> 			sdramedac {</div><div class='ctx'> 				compatible = "altr,sdram-edac-s10";</div><div class='ctx'> 				altr,sdr-syscon = &lt;&amp;sdr&gt;;</div><div class='del'>-				interrupts = &lt;16 4&gt;;</div><div class='add'>+				interrupts = &lt;16 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			ocram-ecc@ff8cc000 {</div><div class='hunk'>@@ -486,7 +631,7 @@</div><div class='ctx'> 					     "altr,socfpga-a10-ocram-ecc";</div><div class='ctx'> 				reg = &lt;0xff8cc000 0x100&gt;;</div><div class='ctx'> 				altr,ecc-parent = &lt;&amp;ocram&gt;;</div><div class='del'>-				interrupts = &lt;1 4&gt;;</div><div class='add'>+				interrupts = &lt;1 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			usb0-ecc@ff8c4000 {</div><div class='hunk'>@@ -494,7 +639,7 @@</div><div class='ctx'> 					     "altr,socfpga-usb-ecc";</div><div class='ctx'> 				reg = &lt;0xff8c4000 0x100&gt;;</div><div class='ctx'> 				altr,ecc-parent = &lt;&amp;usb0&gt;;</div><div class='del'>-				interrupts = &lt;2 4&gt;;</div><div class='add'>+				interrupts = &lt;2 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			emac0-rx-ecc@ff8c0000 {</div><div class='hunk'>@@ -502,7 +647,7 @@</div><div class='ctx'> 					     "altr,socfpga-eth-mac-ecc";</div><div class='ctx'> 				reg = &lt;0xff8c0000 0x100&gt;;</div><div class='ctx'> 				altr,ecc-parent = &lt;&amp;gmac0&gt;;</div><div class='del'>-				interrupts = &lt;4 4&gt;;</div><div class='add'>+				interrupts = &lt;4 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			emac0-tx-ecc@ff8c0400 {</div><div class='hunk'>@@ -510,7 +655,7 @@</div><div class='ctx'> 					     "altr,socfpga-eth-mac-ecc";</div><div class='ctx'> 				reg = &lt;0xff8c0400 0x100&gt;;</div><div class='ctx'> 				altr,ecc-parent = &lt;&amp;gmac0&gt;;</div><div class='del'>-				interrupts = &lt;5 4&gt;;</div><div class='add'>+				interrupts = &lt;5 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			sdmmca-ecc@ff8c8c00 {</div><div class='hunk'>@@ -518,35 +663,24 @@</div><div class='ctx'> 					     "altr,socfpga-sdmmc-ecc";</div><div class='ctx'> 				reg = &lt;0xff8c8c00 0x100&gt;;</div><div class='ctx'> 				altr,ecc-parent = &lt;&amp;mmc&gt;;</div><div class='del'>-				interrupts = &lt;14 4&gt;,</div><div class='del'>-					     &lt;15 4&gt;;</div><div class='add'>+				interrupts = &lt;14 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;15 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		qspi: spi@ff8d2000 {</div><div class='del'>-			compatible = "cdns,qspi-nor";</div><div class='add'>+			compatible = "intel,socfpga-qspi", "cdns,qspi-nor";</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			reg = &lt;0xff8d2000 0x100&gt;,</div><div class='ctx'> 			      &lt;0xff900000 0x100000&gt;;</div><div class='del'>-			interrupts = &lt;0 3 4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			cdns,fifo-depth = &lt;128&gt;;</div><div class='ctx'> 			cdns,fifo-width = &lt;4&gt;;</div><div class='ctx'> 			cdns,trigger-address = &lt;0x00000000&gt;;</div><div class='add'>+			clocks = &lt;&amp;qspi_clk&gt;;</div><div class='ctx'> </div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='del'>-</div><div class='del'>-		firmware {</div><div class='del'>-			svc {</div><div class='del'>-				compatible = "intel,stratix10-svc";</div><div class='del'>-				method = "smc";</div><div class='del'>-				memory-region = &lt;&amp;service_reserved&gt;;</div><div class='del'>-</div><div class='del'>-				fpga_mgr: fpga-mgr {</div><div class='del'>-					compatible = "intel,stratix10-soc-fpga-mgr";</div><div class='del'>-				};</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts<br/>new file mode 100644<br/>index 000000000000..14b299f19f3a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts</a></div><div class='hunk'>@@ -0,0 +1,132 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2025, Altera Corporation</div><div class='add'>+ */</div><div class='add'>+#include "socfpga_agilex5.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "SoCFPGA Agilex3 SoCDK";</div><div class='add'>+	compatible = "intel,socfpga-agilex3-socdk", "intel,socfpga-agilex3",</div><div class='add'>+		     "intel,socfpga-agilex5";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+		ethernet2 = &amp;gmac2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		/delete-node/ cpu@2;</div><div class='add'>+		/delete-node/ cpu@3;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led0 {</div><div class='add'>+			label = "hps_led0";</div><div class='add'>+			gpios = &lt;&amp;porta 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led1 {</div><div class='add'>+			label = "hps_led1";</div><div class='add'>+			gpios = &lt;&amp;porta 12 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@80000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		/* We expect the bootloader to fill in the reg */</div><div class='add'>+		reg = &lt;0x0 0x80000000 0x0 0x0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gmac2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;emac2_phy0&gt;;</div><div class='add'>+	max-frame-size = &lt;9000&gt;;</div><div class='add'>+</div><div class='add'>+	mdio0 {</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		emac2_phy0: ethernet-phy@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			rxc-skew-ps = &lt;0&gt;;</div><div class='add'>+			rxdv-skew-ps = &lt;0&gt;;</div><div class='add'>+			rxd0-skew-ps = &lt;0&gt;;</div><div class='add'>+			rxd1-skew-ps = &lt;0&gt;;</div><div class='add'>+			rxd2-skew-ps = &lt;0&gt;;</div><div class='add'>+			rxd3-skew-ps = &lt;0&gt;;</div><div class='add'>+			txc-skew-ps = &lt;0&gt;;</div><div class='add'>+			txen-skew-ps = &lt;60&gt;;</div><div class='add'>+			txd0-skew-ps = &lt;60&gt;;</div><div class='add'>+			txd1-skew-ps = &lt;60&gt;;</div><div class='add'>+			txd2-skew-ps = &lt;60&gt;;</div><div class='add'>+			txd3-skew-ps = &lt;60&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;osc1 {</div><div class='add'>+	clock-frequency = &lt;25000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qspi {</div><div class='add'>+	status = "okay";</div><div class='add'>+	flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;100000000&gt;;</div><div class='add'>+		m25p,fast-read;</div><div class='add'>+		cdns,read-delay = &lt;2&gt;;</div><div class='add'>+		cdns,tshsl-ns = &lt;50&gt;;</div><div class='add'>+		cdns,tsd2d-ns = &lt;50&gt;;</div><div class='add'>+		cdns,tchsh-ns = &lt;4&gt;;</div><div class='add'>+		cdns,tslch-ns = &lt;4&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;4&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+		partitions {</div><div class='add'>+			compatible = "fixed-partitions";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			qspi_boot: partition@0 {</div><div class='add'>+				label = "u-boot";</div><div class='add'>+				reg = &lt;0x0 0x00c00000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			root: partition@c00000 {</div><div class='add'>+				label = "root";</div><div class='add'>+				reg = &lt;0x00c00000 0x03400000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;smmu {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;watchdog0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi<br/>new file mode 100644<br/>index 000000000000..a5c2025a616e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi</a></div><div class='hunk'>@@ -0,0 +1,937 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2023, Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include &lt;dt-bindings/reset/altr,rst-mgr-s10.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/intel,agilex5-clkmgr.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "intel,socfpga-agilex5";</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		service_reserved: svcbuffer@0 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0x0 0x80000000 0x0 0x2000000&gt;;</div><div class='add'>+			alignment = &lt;0x1000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x0&gt;;</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;L2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@1 {</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x100&gt;;</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;L2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@2 {</div><div class='add'>+			compatible = "arm,cortex-a76";</div><div class='add'>+			reg = &lt;0x200&gt;;</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;L2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@3 {</div><div class='add'>+			compatible = "arm,cortex-a76";</div><div class='add'>+			reg = &lt;0x300&gt;;</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;L2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		L2: l2-cache {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;L3&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		L3: l3-cache {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;3&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	firmware {</div><div class='add'>+		svc {</div><div class='add'>+			compatible = "intel,agilex5-svc";</div><div class='add'>+			method = "smc";</div><div class='add'>+			memory-region = &lt;&amp;service_reserved&gt;;</div><div class='add'>+			iommus = &lt;&amp;smmu 10&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-0.2";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	intc: interrupt-controller@1d000000 {</div><div class='add'>+		compatible = "arm,gic-v3";</div><div class='add'>+		reg = &lt;0x0 0x1d000000 0 0x10000&gt;,</div><div class='add'>+			&lt;0x0 0x1d060000 0 0x100000&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+		#interrupt-cells = &lt;3&gt;;</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		interrupt-parent = &lt;&amp;intc&gt;;</div><div class='add'>+		#redistributor-regions = &lt;1&gt;;</div><div class='add'>+		redistributor-stride = &lt;0x0 0x20000&gt;;</div><div class='add'>+		/* VGIC maintenance interrupt */</div><div class='add'>+		interrupts = &lt;GIC_PPI 25 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+		its: msi-controller@1d040000 {</div><div class='add'>+			compatible = "arm,gic-v3-its";</div><div class='add'>+			reg = &lt;0x0 0x1d040000 0x0 0x20000&gt;;</div><div class='add'>+			msi-controller;</div><div class='add'>+			#msi-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Clock tree 5 main sources*/</div><div class='add'>+	clocks {</div><div class='add'>+		cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			clock-frequency = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cb_intosc_ls_clk: cb-intosc-ls-clk {</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			clock-frequency = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		f2s_free_clk: f2s-free-clk {</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			clock-frequency = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		osc1: osc1 {</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			clock-frequency = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qspi_clk: qspi-clk {</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			clock-frequency = &lt;200000000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupt-parent = &lt;&amp;intc&gt;;</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usbphy0: usbphy {</div><div class='add'>+		#phy-cells = &lt;0&gt;;</div><div class='add'>+		compatible = "usb-nop-xceiv";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu0: pmu {</div><div class='add'>+		compatible = "arm,armv8-pmuv3";</div><div class='add'>+		interrupt-parent = &lt;&amp;intc&gt;;</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc: soc@0 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		ranges = &lt;0 0 0 0xffffffff&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		device_type = "soc";</div><div class='add'>+		interrupt-parent = &lt;&amp;intc&gt;;</div><div class='add'>+</div><div class='add'>+		clkmgr: clock-controller@10d10000 {</div><div class='add'>+			compatible = "intel,agilex5-clkmgr";</div><div class='add'>+			reg = &lt;0x10d10000 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c0: i2c@10c02800 {</div><div class='add'>+			compatible = "snps,designware-i2c";</div><div class='add'>+			reg = &lt;0x10c02800 0x100&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			resets = &lt;&amp;rst I2C0_RESET&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX5_L4_SP_CLK&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c1: i2c@10c02900 {</div><div class='add'>+			compatible = "snps,designware-i2c";</div><div class='add'>+			reg = &lt;0x10c02900 0x100&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			resets = &lt;&amp;rst I2C1_RESET&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX5_L4_SP_CLK&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c2: i2c@10c02a00 {</div><div class='add'>+			compatible = "snps,designware-i2c";</div><div class='add'>+			reg = &lt;0x10c02a00 0x100&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			resets = &lt;&amp;rst I2C2_RESET&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX5_L4_SP_CLK&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c3: i2c@10c02b00 {</div><div class='add'>+			compatible = "snps,designware-i2c";</div><div class='add'>+			reg = &lt;0x10c02b00 0x100&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			resets = &lt;&amp;rst I2C3_RESET&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX5_L4_SP_CLK&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c4: i2c@10c02c00 {</div><div class='add'>+			compatible = "snps,designware-i2c";</div><div class='add'>+			reg = &lt;0x10c02c00 0x100&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			resets = &lt;&amp;rst I2C4_RESET&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX5_L4_SP_CLK&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i3c0: i3c@10da0000 {</div><div class='add'>+			compatible = "altr,agilex5-dw-i3c-master",</div><div class='add'>+				     "snps,dw-i3c-master-1.00a";</div><div class='add'>+			reg = &lt;0x10da0000 0x1000&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX5_L4_MP_CLK&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i3c1: i3c@10da1000 {</div><div class='add'>+			compatible = "altr,agilex5-dw-i3c-master",</div><div class='add'>+				     "snps,dw-i3c-master-1.00a";</div><div class='add'>+			reg = &lt;0x10da1000 0x1000&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX5_L4_MP_CLK&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpio0: gpio@10c03200 {</div><div class='add'>+			compatible = "snps,dw-apb-gpio";</div><div class='add'>+			reg = &lt;0x10c03200 0x100&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			resets = &lt;&amp;rst GPIO0_RESET&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			porta: gpio-controller@0 {</div><div class='add'>+				compatible = "snps,dw-apb-gpio-port";</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+				snps,nr-gpios = &lt;24&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;2&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpio1: gpio@10c03300 {</div><div class='add'>+			compatible = "snps,dw-apb-gpio";</div><div class='add'>+			reg = &lt;0x10c03300 0x100&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			resets = &lt;&amp;rst GPIO1_RESET&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			portb: gpio-controller@0 {</div><div class='add'>+				compatible = "snps,dw-apb-gpio-port";</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+				snps,nr-gpios = &lt;24&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;2&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nand: nand-controller@10b80000 {</div><div class='add'>+			compatible = "cdns,hp-nfc";</div><div class='add'>+			reg = &lt;0x10b80000 0x10000&gt;,</div><div class='add'>+					&lt;0x10840000 0x10000&gt;;</div><div class='add'>+			reg-names = "reg", "sdma";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX5_NAND_NF_CLK&gt;;</div><div class='add'>+			clock-names = "nf_clk";</div><div class='add'>+			cdns,board-delay-ps = &lt;4830&gt;;</div><div class='add'>+			iommus = &lt;&amp;smmu 4&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ocram: sram@0 {</div><div class='add'>+			compatible = "mmio-sram";</div><div class='add'>+			reg = &lt;0x00000000 0x80000&gt;;</div><div class='add'>+			ranges = &lt;0 0 0x80000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dmac0: dma-controller@10db0000 {</div><div class='add'>+			compatible = "snps,axi-dma-1.01a";</div><div class='add'>+			reg = &lt;0x10db0000 0x500&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX5_L4_MAIN_CLK&gt;,</div><div class='add'>+				 &lt;&amp;clkmgr AGILEX5_L4_MP_CLK&gt;;</div><div class='add'>+			clock-names = "core-clk", "cfgr-clk";</div><div class='add'>+			interrupt-parent = &lt;&amp;intc&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+			dma-channels = &lt;4&gt;;</div><div class='add'>+			snps,dma-masters = &lt;1&gt;;</div><div class='add'>+			snps,data-width = &lt;2&gt;;</div><div class='add'>+			snps,block-size = &lt;32767 32767 32767 32767&gt;;</div><div class='add'>+			snps,priority = &lt;0 1 2 3&gt;;</div><div class='add'>+			snps,axi-max-burst-len = &lt;8&gt;;</div><div class='add'>+			iommus = &lt;&amp;smmu 8&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dmac1: dma-controller@10dc0000 {</div><div class='add'>+			compatible = "snps,axi-dma-1.01a";</div><div class='add'>+			reg = &lt;0x10dc0000 0x500&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX5_L4_MAIN_CLK&gt;,</div><div class='add'>+				 &lt;&amp;clkmgr AGILEX5_L4_MP_CLK&gt;;</div><div class='add'>+			clock-names = "core-clk", "cfgr-clk";</div><div class='add'>+			interrupt-parent = &lt;&amp;intc&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+			dma-channels = &lt;4&gt;;</div><div class='add'>+			snps,dma-masters = &lt;1&gt;;</div><div class='add'>+			snps,data-width = &lt;2&gt;;</div><div class='add'>+			snps,block-size = &lt;32767 32767 32767 32767&gt;;</div><div class='add'>+			snps,priority = &lt;0 1 2 3&gt;;</div><div class='add'>+			snps,axi-max-burst-len = &lt;8&gt;;</div><div class='add'>+			iommus = &lt;&amp;smmu 9&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rst: rstmgr@10d11000 {</div><div class='add'>+			compatible = "altr,stratix10-rst-mgr", "altr,rst-mgr";</div><div class='add'>+			reg = &lt;0x10d11000 0x1000&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smmu: iommu@16000000 {</div><div class='add'>+			compatible = "arm,smmu-v3";</div><div class='add'>+			reg = &lt;0x16000000 0x30000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 134 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 129 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 132 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			interrupt-names = "eventq", "gerror", "priq";</div><div class='add'>+			dma-coherent;</div><div class='add'>+			#iommu-cells = &lt;1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi0: spi@10da4000 {</div><div class='add'>+			compatible = "snps,dw-apb-ssi";</div><div class='add'>+			reg = &lt;0x10da4000 0x1000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			resets = &lt;&amp;rst SPIM0_RESET&gt;;</div><div class='add'>+			reset-names = "spi";</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+			num-cs = &lt;4&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX5_L4_MAIN_CLK&gt;;</div><div class='add'>+			dmas = &lt;&amp;dmac0 16&gt;, &lt;&amp;dmac0 17&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi1: spi@10da5000 {</div><div class='add'>+			compatible = "snps,dw-apb-ssi";</div><div class='add'>+			reg = &lt;0x10da5000 0x1000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			resets = &lt;&amp;rst SPIM1_RESET&gt;;</div><div class='add'>+			reset-names = "spi";</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+			num-cs = &lt;4&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX5_L4_MAIN_CLK&gt;;</div><div class='add'>+			dmas = &lt;&amp;dmac0 20&gt;, &lt;&amp;dmac0 21&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sysmgr: sysmgr@10d12000 {</div><div class='add'>+			compatible = "altr,sys-mgr-s10","altr,sys-mgr";</div><div class='add'>+			reg = &lt;0x10d12000 0x500&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		timer0: timer0@10c03000 {</div><div class='add'>+			compatible = "snps,dw-apb-timer";</div><div class='add'>+			reg = &lt;0x10c03000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX5_L4_SP_CLK&gt;;</div><div class='add'>+			clock-names = "timer";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		timer1: timer1@10c03100 {</div><div class='add'>+			compatible = "snps,dw-apb-timer";</div><div class='add'>+			reg = &lt;0x10c03100 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX5_L4_SP_CLK&gt;;</div><div class='add'>+			clock-names = "timer";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		timer2: timer2@10d00000 {</div><div class='add'>+			compatible = "snps,dw-apb-timer";</div><div class='add'>+			reg = &lt;0x10d00000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX5_L4_SP_CLK&gt;;</div><div class='add'>+			clock-names = "timer";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		timer3: timer3@10d00100 {</div><div class='add'>+			compatible = "snps,dw-apb-timer";</div><div class='add'>+			reg = &lt;0x10d00100 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX5_L4_SP_CLK&gt;;</div><div class='add'>+			clock-names = "timer";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart0: serial@10c02000 {</div><div class='add'>+			compatible = "snps,dw-apb-uart";</div><div class='add'>+			reg = &lt;0x10c02000 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			reg-shift = &lt;2&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+			resets = &lt;&amp;rst UART0_RESET&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX5_L4_SP_CLK&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart1: serial@10c02100 {</div><div class='add'>+			compatible = "snps,dw-apb-uart";</div><div class='add'>+			reg = &lt;0x10c02100 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			reg-shift = &lt;2&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+			resets = &lt;&amp;rst UART1_RESET&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX5_L4_SP_CLK&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb0: usb@10b00000 {</div><div class='add'>+			compatible = "snps,dwc2";</div><div class='add'>+			reg = &lt;0x10b00000 0x40000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			phys = &lt;&amp;usbphy0&gt;;</div><div class='add'>+			phy-names = "usb2-phy";</div><div class='add'>+			resets = &lt;&amp;rst USB0_RESET&gt;, &lt;&amp;rst USB0_OCP_RESET&gt;;</div><div class='add'>+			reset-names = "dwc2", "dwc2-ecc";</div><div class='add'>+			iommus = &lt;&amp;smmu 6&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX5_USB2OTG_HCLK&gt;;</div><div class='add'>+			clock-names = "otg";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		watchdog0: watchdog@10d00200 {</div><div class='add'>+			compatible = "snps,dw-wdt";</div><div class='add'>+			reg = &lt;0x10d00200 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			resets = &lt;&amp;rst WATCHDOG0_RESET&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX5_L4_SYS_FREE_CLK&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		watchdog1: watchdog@10d00300 {</div><div class='add'>+			compatible = "snps,dw-wdt";</div><div class='add'>+			reg = &lt;0x10d00300 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			resets = &lt;&amp;rst WATCHDOG1_RESET&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX5_L4_SYS_FREE_CLK&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		watchdog2: watchdog@10d00400 {</div><div class='add'>+			compatible = "snps,dw-wdt";</div><div class='add'>+			reg = &lt;0x10d00400 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			resets = &lt;&amp;rst WATCHDOG2_RESET&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX5_L4_SYS_FREE_CLK&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		watchdog3: watchdog@10d00500 {</div><div class='add'>+			compatible = "snps,dw-wdt";</div><div class='add'>+			reg = &lt;0x10d00500 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			resets = &lt;&amp;rst WATCHDOG3_RESET&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX5_L4_SYS_FREE_CLK&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		watchdog4: watchdog@10d00600 {</div><div class='add'>+			compatible = "snps,dw-wdt";</div><div class='add'>+			reg = &lt;0x10d00600 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			resets = &lt;&amp;rst WATCHDOG4_RESET&gt;;</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX5_L4_SYS_FREE_CLK&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qspi: spi@108d2000 {</div><div class='add'>+			compatible = "intel,socfpga-qspi", "cdns,qspi-nor";</div><div class='add'>+			reg = &lt;0x108d2000 0x100&gt;,</div><div class='add'>+			      &lt;0x10900000 0x100000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			cdns,fifo-depth = &lt;128&gt;;</div><div class='add'>+			cdns,fifo-width = &lt;4&gt;;</div><div class='add'>+			cdns,trigger-address = &lt;0x00000000&gt;;</div><div class='add'>+			clocks = &lt;&amp;qspi_clk&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gmac0: ethernet@10810000 {</div><div class='add'>+			compatible = "altr,socfpga-stmmac-agilex5",</div><div class='add'>+				     "snps,dwxgmac-2.10";</div><div class='add'>+			reg = &lt;0x10810000 0x3500&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "macirq";</div><div class='add'>+			resets = &lt;&amp;rst EMAC0_RESET&gt;, &lt;&amp;rst EMAC0_OCP_RESET&gt;;</div><div class='add'>+			reset-names = "stmmaceth", "ahb";</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX5_EMAC0_CLK&gt;,</div><div class='add'>+				 &lt;&amp;clkmgr AGILEX5_EMAC_PTP_CLK&gt;;</div><div class='add'>+			clock-names = "stmmaceth", "ptp_ref";</div><div class='add'>+			mac-address = [00 00 00 00 00 00];</div><div class='add'>+			tx-fifo-depth = &lt;32768&gt;;</div><div class='add'>+			rx-fifo-depth = &lt;16384&gt;;</div><div class='add'>+			snps,multicast-filter-bins = &lt;64&gt;;</div><div class='add'>+			snps,perfect-filter-entries = &lt;64&gt;;</div><div class='add'>+			snps,axi-config = &lt;&amp;stmmac_axi_emac0_setup&gt;;</div><div class='add'>+			snps,mtl-rx-config = &lt;&amp;mtl_rx_emac0_setup&gt;;</div><div class='add'>+			snps,mtl-tx-config = &lt;&amp;mtl_tx_emac0_setup&gt;;</div><div class='add'>+			snps,pbl = &lt;32&gt;;</div><div class='add'>+			snps,tso;</div><div class='add'>+			altr,sysmgr-syscon = &lt;&amp;sysmgr 0x44 0&gt;;</div><div class='add'>+			snps,clk-csr = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			stmmac_axi_emac0_setup: stmmac-axi-config {</div><div class='add'>+				snps,wr_osr_lmt = &lt;31&gt;;</div><div class='add'>+				snps,rd_osr_lmt = &lt;31&gt;;</div><div class='add'>+				snps,blen = &lt;0 0 0 32 16 8 4&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mtl_rx_emac0_setup: rx-queues-config {</div><div class='add'>+				snps,rx-queues-to-use = &lt;8&gt;;</div><div class='add'>+				snps,rx-sched-sp;</div><div class='add'>+				queue0 {</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+					snps,map-to-dma-channel = &lt;0x0&gt;;</div><div class='add'>+				};</div><div class='add'>+				queue1 {</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+					snps,map-to-dma-channel = &lt;0x1&gt;;</div><div class='add'>+				};</div><div class='add'>+				queue2 {</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+					snps,map-to-dma-channel = &lt;0x2&gt;;</div><div class='add'>+				};</div><div class='add'>+				queue3 {</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+					snps,map-to-dma-channel = &lt;0x3&gt;;</div><div class='add'>+				};</div><div class='add'>+				queue4 {</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+					snps,map-to-dma-channel = &lt;0x4&gt;;</div><div class='add'>+				};</div><div class='add'>+				queue5 {</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+					snps,map-to-dma-channel = &lt;0x5&gt;;</div><div class='add'>+				};</div><div class='add'>+				queue6 {</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+					snps,map-to-dma-channel = &lt;0x6&gt;;</div><div class='add'>+				};</div><div class='add'>+				queue7 {</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+					snps,map-to-dma-channel = &lt;0x7&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mtl_tx_emac0_setup: tx-queues-config {</div><div class='add'>+				snps,tx-queues-to-use = &lt;8&gt;;</div><div class='add'>+				snps,tx-sched-wrr;</div><div class='add'>+				queue0 {</div><div class='add'>+					snps,weight = &lt;0x09&gt;;</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+				};</div><div class='add'>+				queue1 {</div><div class='add'>+					snps,weight = &lt;0x0A&gt;;</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+				};</div><div class='add'>+				queue2 {</div><div class='add'>+					snps,weight = &lt;0x0B&gt;;</div><div class='add'>+					snps,coe-unsupported;</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+				};</div><div class='add'>+				queue3 {</div><div class='add'>+					snps,weight = &lt;0x0C&gt;;</div><div class='add'>+					snps,coe-unsupported;</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+				};</div><div class='add'>+				queue4 {</div><div class='add'>+					snps,weight = &lt;0x0D&gt;;</div><div class='add'>+					snps,coe-unsupported;</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+				};</div><div class='add'>+				queue5 {</div><div class='add'>+					snps,weight = &lt;0x0E&gt;;</div><div class='add'>+					snps,coe-unsupported;</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+				};</div><div class='add'>+				queue6 {</div><div class='add'>+					snps,weight = &lt;0x0F&gt;;</div><div class='add'>+					snps,coe-unsupported;</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+				};</div><div class='add'>+				queue7 {</div><div class='add'>+					snps,weight = &lt;0x10&gt;;</div><div class='add'>+					snps,coe-unsupported;</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gmac1: ethernet@10820000 {</div><div class='add'>+			compatible = "altr,socfpga-stmmac-agilex5",</div><div class='add'>+				     "snps,dwxgmac-2.10";</div><div class='add'>+			reg = &lt;0x10820000 0x3500&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "macirq";</div><div class='add'>+			resets = &lt;&amp;rst EMAC1_RESET&gt;, &lt;&amp;rst EMAC1_OCP_RESET&gt;;</div><div class='add'>+			reset-names = "stmmaceth", "ahb";</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX5_EMAC1_CLK&gt;,</div><div class='add'>+				 &lt;&amp;clkmgr AGILEX5_EMAC_PTP_CLK&gt;;</div><div class='add'>+			clock-names = "stmmaceth", "ptp_ref";</div><div class='add'>+			mac-address = [00 00 00 00 00 00];</div><div class='add'>+			tx-fifo-depth = &lt;32768&gt;;</div><div class='add'>+			rx-fifo-depth = &lt;16384&gt;;</div><div class='add'>+			snps,multicast-filter-bins = &lt;64&gt;;</div><div class='add'>+			snps,perfect-filter-entries = &lt;64&gt;;</div><div class='add'>+			snps,axi-config = &lt;&amp;stmmac_axi_emac1_setup&gt;;</div><div class='add'>+			snps,mtl-rx-config = &lt;&amp;mtl_rx_emac1_setup&gt;;</div><div class='add'>+			snps,mtl-tx-config = &lt;&amp;mtl_tx_emac1_setup&gt;;</div><div class='add'>+			snps,pbl = &lt;32&gt;;</div><div class='add'>+			snps,tso;</div><div class='add'>+			altr,sysmgr-syscon = &lt;&amp;sysmgr 0x48 0&gt;;</div><div class='add'>+			snps,clk-csr = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			stmmac_axi_emac1_setup: stmmac-axi-config {</div><div class='add'>+				snps,wr_osr_lmt = &lt;31&gt;;</div><div class='add'>+				snps,rd_osr_lmt = &lt;31&gt;;</div><div class='add'>+				snps,blen = &lt;0 0 0 32 16 8 4&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mtl_rx_emac1_setup: rx-queues-config {</div><div class='add'>+				snps,rx-queues-to-use = &lt;8&gt;;</div><div class='add'>+				snps,rx-sched-sp;</div><div class='add'>+				queue0 {</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+					snps,map-to-dma-channel = &lt;0x0&gt;;</div><div class='add'>+				};</div><div class='add'>+				queue1 {</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+					snps,map-to-dma-channel = &lt;0x1&gt;;</div><div class='add'>+				};</div><div class='add'>+				queue2 {</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+					snps,map-to-dma-channel = &lt;0x2&gt;;</div><div class='add'>+				};</div><div class='add'>+				queue3 {</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+					snps,map-to-dma-channel = &lt;0x3&gt;;</div><div class='add'>+				};</div><div class='add'>+				queue4 {</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+					snps,map-to-dma-channel = &lt;0x4&gt;;</div><div class='add'>+				};</div><div class='add'>+				queue5 {</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+					snps,map-to-dma-channel = &lt;0x5&gt;;</div><div class='add'>+				};</div><div class='add'>+				queue6 {</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+					snps,map-to-dma-channel = &lt;0x6&gt;;</div><div class='add'>+				};</div><div class='add'>+				queue7 {</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+					snps,map-to-dma-channel = &lt;0x7&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mtl_tx_emac1_setup: tx-queues-config {</div><div class='add'>+				snps,tx-queues-to-use = &lt;8&gt;;</div><div class='add'>+				snps,tx-sched-wrr;</div><div class='add'>+				queue0 {</div><div class='add'>+					snps,weight = &lt;0x09&gt;;</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+				};</div><div class='add'>+				queue1 {</div><div class='add'>+					snps,weight = &lt;0x0A&gt;;</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+				};</div><div class='add'>+				queue2 {</div><div class='add'>+					snps,weight = &lt;0x0B&gt;;</div><div class='add'>+					snps,coe-unsupported;</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+				};</div><div class='add'>+				queue3 {</div><div class='add'>+					snps,weight = &lt;0x0C&gt;;</div><div class='add'>+					snps,coe-unsupported;</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+				};</div><div class='add'>+				queue4 {</div><div class='add'>+					snps,weight = &lt;0x0D&gt;;</div><div class='add'>+					snps,coe-unsupported;</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+				};</div><div class='add'>+				queue5 {</div><div class='add'>+					snps,weight = &lt;0x0E&gt;;</div><div class='add'>+					snps,coe-unsupported;</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+				};</div><div class='add'>+				queue6 {</div><div class='add'>+					snps,weight = &lt;0x0F&gt;;</div><div class='add'>+					snps,coe-unsupported;</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+				};</div><div class='add'>+				queue7 {</div><div class='add'>+					snps,weight = &lt;0x10&gt;;</div><div class='add'>+					snps,coe-unsupported;</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gmac2: ethernet@10830000 {</div><div class='add'>+			compatible = "altr,socfpga-stmmac-agilex5",</div><div class='add'>+				     "snps,dwxgmac-2.10";</div><div class='add'>+			reg = &lt;0x10830000 0x3500&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "macirq";</div><div class='add'>+			resets = &lt;&amp;rst EMAC2_RESET&gt;, &lt;&amp;rst EMAC2_OCP_RESET&gt;;</div><div class='add'>+			reset-names = "stmmaceth", "ahb";</div><div class='add'>+			clocks = &lt;&amp;clkmgr AGILEX5_EMAC2_CLK&gt;,</div><div class='add'>+				 &lt;&amp;clkmgr AGILEX5_EMAC_PTP_CLK&gt;;</div><div class='add'>+			clock-names = "stmmaceth", "ptp_ref";</div><div class='add'>+			mac-address = [00 00 00 00 00 00];</div><div class='add'>+			tx-fifo-depth = &lt;32768&gt;;</div><div class='add'>+			rx-fifo-depth = &lt;16384&gt;;</div><div class='add'>+			snps,multicast-filter-bins = &lt;64&gt;;</div><div class='add'>+			snps,perfect-filter-entries = &lt;64&gt;;</div><div class='add'>+			snps,axi-config = &lt;&amp;stmmac_axi_emac2_setup&gt;;</div><div class='add'>+			snps,mtl-rx-config = &lt;&amp;mtl_rx_emac2_setup&gt;;</div><div class='add'>+			snps,mtl-tx-config = &lt;&amp;mtl_tx_emac2_setup&gt;;</div><div class='add'>+			snps,pbl = &lt;32&gt;;</div><div class='add'>+			snps,tso;</div><div class='add'>+			altr,sysmgr-syscon = &lt;&amp;sysmgr 0x4c 0&gt;;</div><div class='add'>+			snps,clk-csr = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			stmmac_axi_emac2_setup: stmmac-axi-config {</div><div class='add'>+				snps,wr_osr_lmt = &lt;31&gt;;</div><div class='add'>+				snps,rd_osr_lmt = &lt;31&gt;;</div><div class='add'>+				snps,blen = &lt;0 0 0 32 16 8 4&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mtl_rx_emac2_setup: rx-queues-config {</div><div class='add'>+				snps,rx-queues-to-use = &lt;8&gt;;</div><div class='add'>+				snps,rx-sched-sp;</div><div class='add'>+				queue0 {</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+					snps,map-to-dma-channel = &lt;0x0&gt;;</div><div class='add'>+				};</div><div class='add'>+				queue1 {</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+					snps,map-to-dma-channel = &lt;0x1&gt;;</div><div class='add'>+				};</div><div class='add'>+				queue2 {</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+					snps,map-to-dma-channel = &lt;0x2&gt;;</div><div class='add'>+				};</div><div class='add'>+				queue3 {</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+					snps,map-to-dma-channel = &lt;0x3&gt;;</div><div class='add'>+				};</div><div class='add'>+				queue4 {</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+					snps,map-to-dma-channel = &lt;0x4&gt;;</div><div class='add'>+				};</div><div class='add'>+				queue5 {</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+					snps,map-to-dma-channel = &lt;0x5&gt;;</div><div class='add'>+				};</div><div class='add'>+				queue6 {</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+					snps,map-to-dma-channel = &lt;0x6&gt;;</div><div class='add'>+				};</div><div class='add'>+				queue7 {</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+					snps,map-to-dma-channel = &lt;0x7&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mtl_tx_emac2_setup: tx-queues-config {</div><div class='add'>+				snps,tx-queues-to-use = &lt;8&gt;;</div><div class='add'>+				snps,tx-sched-wrr;</div><div class='add'>+				queue0 {</div><div class='add'>+					snps,weight = &lt;0x09&gt;;</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+				};</div><div class='add'>+				queue1 {</div><div class='add'>+					snps,weight = &lt;0x0A&gt;;</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+				};</div><div class='add'>+				queue2 {</div><div class='add'>+					snps,weight = &lt;0x0B&gt;;</div><div class='add'>+					snps,coe-unsupported;</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+				};</div><div class='add'>+				queue3 {</div><div class='add'>+					snps,weight = &lt;0x0C&gt;;</div><div class='add'>+					snps,coe-unsupported;</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+				};</div><div class='add'>+				queue4 {</div><div class='add'>+					snps,weight = &lt;0x0D&gt;;</div><div class='add'>+					snps,coe-unsupported;</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+				};</div><div class='add'>+				queue5 {</div><div class='add'>+					snps,weight = &lt;0x0E&gt;;</div><div class='add'>+					snps,coe-unsupported;</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+				};</div><div class='add'>+				queue6 {</div><div class='add'>+					snps,weight = &lt;0x0F&gt;;</div><div class='add'>+					snps,coe-unsupported;</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+				};</div><div class='add'>+				queue7 {</div><div class='add'>+					snps,weight = &lt;0x10&gt;;</div><div class='add'>+					snps,coe-unsupported;</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmu0_tcu: pmu@16002000 {</div><div class='add'>+			compatible = "arm,smmu-v3-pmcg";</div><div class='add'>+			reg = &lt;0x16002000 0x1000&gt;,</div><div class='add'>+				&lt;0x16022000 0x1000&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;intc&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 136 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmu0_tbu0: pmu@16042000 {</div><div class='add'>+			compatible = "arm,smmu-v3-pmcg";</div><div class='add'>+			reg = &lt;0x16042000 0x1000&gt;,</div><div class='add'>+				&lt;0x16052000 0x1000&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;intc&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 138 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmu0_tbu1: pmu@16062000 {</div><div class='add'>+			compatible = "arm,smmu-v3-pmcg";</div><div class='add'>+			reg = &lt;0x16062000 0x1000&gt;,</div><div class='add'>+				&lt;0x16072000 0x1000&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;intc&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 140 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmu0_tbu2: pmu@16082000 {</div><div class='add'>+			compatible = "arm,smmu-v3-pmcg";</div><div class='add'>+			reg = &lt;0x16082000 0x1000&gt;,</div><div class='add'>+				&lt;0x16092000 0x1000&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;intc&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 142 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmu0_tbu3: pmu@160a2000 {</div><div class='add'>+			compatible = "arm,smmu-v3-pmcg";</div><div class='add'>+			reg = &lt;0x160A2000 0x1000&gt;,</div><div class='add'>+				&lt;0x160B2000 0x1000&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;intc&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 144 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmu0_tbu4: pmu@160c2000 {</div><div class='add'>+			compatible = "arm,smmu-v3-pmcg";</div><div class='add'>+			reg = &lt;0x160C2000 0x1000&gt;,</div><div class='add'>+				&lt;0x160D2000 0x1000&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;intc&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 146 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmu0_tbu5: pmu@160e2000 {</div><div class='add'>+			compatible = "arm,smmu-v3-pmcg";</div><div class='add'>+			reg = &lt;0x160E2000 0x1000&gt;,</div><div class='add'>+				&lt;0x160F2000 0x1000&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;intc&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 150 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts<br/>new file mode 100644<br/>index 000000000000..262bb3e8e5c7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts</a></div><div class='hunk'>@@ -0,0 +1,112 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2023, Intel Corporation</div><div class='add'>+ */</div><div class='add'>+#include "socfpga_agilex5.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "SoCFPGA Agilex5 SoCDK";</div><div class='add'>+	compatible = "intel,socfpga-agilex5-socdk", "intel,socfpga-agilex5";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+		ethernet0 = &amp;gmac0;</div><div class='add'>+		ethernet1 = &amp;gmac1;</div><div class='add'>+		ethernet2 = &amp;gmac2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			label = "hps_led0";</div><div class='add'>+			gpios = &lt;&amp;porta 11 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@80000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		/* We expect the bootloader to fill in the reg */</div><div class='add'>+		reg = &lt;0x0 0x80000000 0x0 0x0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gmac2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;emac2_phy0&gt;;</div><div class='add'>+	max-frame-size = &lt;9000&gt;;</div><div class='add'>+</div><div class='add'>+	mdio0 {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+</div><div class='add'>+		emac2_phy0: ethernet-phy@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;osc1 {</div><div class='add'>+	clock-frequency = &lt;25000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qspi {</div><div class='add'>+	status = "okay";</div><div class='add'>+	flash@0 {</div><div class='add'>+		compatible = "micron,mt25qu02g", "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;100000000&gt;;</div><div class='add'>+		m25p,fast-read;</div><div class='add'>+		cdns,read-delay = &lt;2&gt;;</div><div class='add'>+		cdns,tshsl-ns = &lt;50&gt;;</div><div class='add'>+		cdns,tsd2d-ns = &lt;50&gt;;</div><div class='add'>+		cdns,tchsh-ns = &lt;4&gt;;</div><div class='add'>+		cdns,tslch-ns = &lt;4&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;4&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+		partitions {</div><div class='add'>+			compatible = "fixed-partitions";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			qspi_boot: partition@0 {</div><div class='add'>+				label = "u-boot";</div><div class='add'>+				reg = &lt;0x0 0x04200000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			root: partition@4200000 {</div><div class='add'>+				label = "root";</div><div class='add'>+				reg = &lt;0x04200000 0x0be00000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	disable-over-current;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;watchdog0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts<br/>new file mode 100644<br/>index 000000000000..f71e1280c778<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts</a></div><div class='hunk'>@@ -0,0 +1,126 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2025, Altera Corporation</div><div class='add'>+ */</div><div class='add'>+#include "socfpga_agilex5.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "SoCFPGA Agilex5 013B SoCDK";</div><div class='add'>+	compatible = "intel,socfpga-agilex5-socdk-013b", "intel,socfpga-agilex5";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+		ethernet2 = &amp;gmac2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led0 {</div><div class='add'>+			label = "hps_led0";</div><div class='add'>+			gpios = &lt;&amp;porta 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led1 {</div><div class='add'>+			label = "hps_led1";</div><div class='add'>+			gpios = &lt;&amp;porta 12 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@80000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		/* We expect the bootloader to fill in the reg */</div><div class='add'>+		reg = &lt;0x0 0x80000000 0x0 0x0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gmac2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;emac2_phy0&gt;;</div><div class='add'>+	max-frame-size = &lt;9000&gt;;</div><div class='add'>+</div><div class='add'>+	mdio0 {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+</div><div class='add'>+		emac2_phy0: ethernet-phy@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			rxc-skew-ps = &lt;0&gt;;</div><div class='add'>+			rxdv-skew-ps = &lt;0&gt;;</div><div class='add'>+			rxd0-skew-ps = &lt;0&gt;;</div><div class='add'>+			rxd1-skew-ps = &lt;0&gt;;</div><div class='add'>+			rxd2-skew-ps = &lt;0&gt;;</div><div class='add'>+			rxd3-skew-ps = &lt;0&gt;;</div><div class='add'>+			txc-skew-ps = &lt;0&gt;;</div><div class='add'>+			txen-skew-ps = &lt;60&gt;;</div><div class='add'>+			txd0-skew-ps = &lt;60&gt;;</div><div class='add'>+			txd1-skew-ps = &lt;60&gt;;</div><div class='add'>+			txd2-skew-ps = &lt;60&gt;;</div><div class='add'>+			txd3-skew-ps = &lt;60&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;osc1 {</div><div class='add'>+	clock-frequency = &lt;25000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qspi {</div><div class='add'>+	status = "okay";</div><div class='add'>+	flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;100000000&gt;;</div><div class='add'>+		m25p,fast-read;</div><div class='add'>+		cdns,read-delay = &lt;2&gt;;</div><div class='add'>+		cdns,tshsl-ns = &lt;50&gt;;</div><div class='add'>+		cdns,tsd2d-ns = &lt;50&gt;;</div><div class='add'>+		cdns,tchsh-ns = &lt;4&gt;;</div><div class='add'>+		cdns,tslch-ns = &lt;4&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;4&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+		partitions {</div><div class='add'>+			compatible = "fixed-partitions";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			qspi_boot: partition@0 {</div><div class='add'>+				label = "u-boot";</div><div class='add'>+				reg = &lt;0x0 0x00c00000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			root: partition@c00000  {</div><div class='add'>+				label = "root";</div><div class='add'>+				reg = &lt;0x00c00000 0x03400000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;smmu {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;watchdog0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts<br/>new file mode 100644<br/>index 000000000000..ec4541d44c9b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts</a></div><div class='hunk'>@@ -0,0 +1,107 @@</div><div class='add'>+// SPDX-License-Identifier:     GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2025, Altera Corporation</div><div class='add'>+ */</div><div class='add'>+#include "socfpga_agilex5.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "SoCFPGA Agilex5 SoCDK NAND daughter board";</div><div class='add'>+	compatible = "intel,socfpga-agilex5-socdk-nand", "intel,socfpga-agilex5";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+		ethernet0 = &amp;gmac0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		led0 {</div><div class='add'>+			label = "hps_led0";</div><div class='add'>+			gpios = &lt;&amp;porta 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led1 {</div><div class='add'>+			label = "hps_led1";</div><div class='add'>+			gpios = &lt;&amp;porta 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@80000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		/* We expect the bootloader to fill in the reg */</div><div class='add'>+		reg = &lt;0x0 0x80000000 0x0 0x0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gmac0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;emac0_phy0&gt;;</div><div class='add'>+	max-frame-size = &lt;9000&gt;;</div><div class='add'>+</div><div class='add'>+	mdio0 {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+</div><div class='add'>+		emac0_phy0: ethernet-phy@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i3c0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i3c1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;nand {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	nand@0 {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		nand-bus-width = &lt;8&gt;;</div><div class='add'>+</div><div class='add'>+		partition@0 {</div><div class='add'>+			label = "u-boot";</div><div class='add'>+			reg = &lt;0 0x200000&gt;;</div><div class='add'>+		};</div><div class='add'>+		partition@200000 {</div><div class='add'>+			label = "root";</div><div class='add'>+			reg = &lt;0x200000 0xffe00000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;osc1 {</div><div class='add'>+	clock-frequency = &lt;25000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;watchdog0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts<br/>new file mode 100644<br/>index 000000000000..d22de06e9839<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts</a></div><div class='hunk'>@@ -0,0 +1,66 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2021-2022, Intel Corporation</div><div class='add'>+ */</div><div class='add'>+#include "socfpga_agilex.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "SoCFPGA Agilex n6000";</div><div class='add'>+	compatible = "intel,socfpga-agilex-n6000", "intel,socfpga-agilex";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart1;</div><div class='add'>+		serial1 = &amp;uart0;</div><div class='add'>+		ethernet0 = &amp;gmac0;</div><div class='add'>+		ethernet1 = &amp;gmac1;</div><div class='add'>+		ethernet2 = &amp;gmac2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@80000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		/* We expect the bootloader to fill in the reg */</div><div class='add'>+		reg = &lt;0 0x80000000 0 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc@0 {</div><div class='add'>+		bus@80000000 {</div><div class='add'>+			compatible = "simple-bus";</div><div class='add'>+			reg = &lt;0x80000000 0x60000000&gt;,</div><div class='add'>+				&lt;0xf9000000 0x00100000&gt;;</div><div class='add'>+			reg-names = "axi_h2f", "axi_h2f_lw";</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges = &lt;0x00000000 0x00000000 0xf9000000 0x00001000&gt;;</div><div class='add'>+</div><div class='add'>+			dma-controller@0 {</div><div class='add'>+				compatible = "intel,hps-copy-engine";</div><div class='add'>+				reg = &lt;0x00000000 0x00000000 0x00001000&gt;;</div><div class='add'>+				#dma-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;osc1 {</div><div class='add'>+	clock-frequency = &lt;25000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;watchdog0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fpga_mgr {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts<br/>index 51d948323bfd..9ee312bae8d2 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts</a></div><div class='hunk'>@@ -6,6 +6,7 @@</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	model = "SoCFPGA Agilex SoCDK";</div><div class='add'>+	compatible = "intel,socfpga-agilex-socdk", "intel,socfpga-agilex";</div><div class='ctx'> </div><div class='ctx'> 	aliases {</div><div class='ctx'> 		serial0 = &amp;uart0;</div><div class='hunk'>@@ -20,26 +21,26 @@</div><div class='ctx'> </div><div class='ctx'> 	leds {</div><div class='ctx'> 		compatible = "gpio-leds";</div><div class='del'>-		hps0 {</div><div class='add'>+		led0 {</div><div class='ctx'> 			label = "hps_led0";</div><div class='ctx'> 			gpios = &lt;&amp;portb 20 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		hps1 {</div><div class='add'>+		led1 {</div><div class='ctx'> 			label = "hps_led1";</div><div class='ctx'> 			gpios = &lt;&amp;portb 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		hps2 {</div><div class='add'>+		led2 {</div><div class='ctx'> 			label = "hps_led2";</div><div class='ctx'> 			gpios = &lt;&amp;portb 21 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	memory {</div><div class='add'>+	memory@80000000 {</div><div class='ctx'> 		device_type = "memory";</div><div class='ctx'> 		/* We expect the bootloader to fill in the reg */</div><div class='del'>-		reg = &lt;0 0 0 0&gt;;</div><div class='add'>+		reg = &lt;0 0x80000000 0 0&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -82,6 +83,11 @@</div><div class='ctx'> 	cap-sd-highspeed;</div><div class='ctx'> 	broken-cd;</div><div class='ctx'> 	bus-width = &lt;4&gt;;</div><div class='add'>+	clk-phase-sd-hs = &lt;0&gt;, &lt;135&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;osc1 {</div><div class='add'>+	clock-frequency = &lt;25000000&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;uart0 {</div><div class='hunk'>@@ -98,21 +104,20 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;qspi {</div><div class='add'>+	status = "okay";</div><div class='ctx'> 	flash@0 {</div><div class='del'>-		#address-cells = &lt;1&gt;;</div><div class='del'>-		#size-cells = &lt;1&gt;;</div><div class='del'>-		compatible = "mt25qu02g";</div><div class='add'>+		compatible = "micron,mt25qu02g", "jedec,spi-nor";</div><div class='ctx'> 		reg = &lt;0&gt;;</div><div class='ctx'> 		spi-max-frequency = &lt;100000000&gt;;</div><div class='ctx'> </div><div class='ctx'> 		m25p,fast-read;</div><div class='del'>-		cdns,page-size = &lt;256&gt;;</div><div class='del'>-		cdns,block-size = &lt;16&gt;;</div><div class='del'>-		cdns,read-delay = &lt;1&gt;;</div><div class='add'>+		cdns,read-delay = &lt;2&gt;;</div><div class='ctx'> 		cdns,tshsl-ns = &lt;50&gt;;</div><div class='ctx'> 		cdns,tsd2d-ns = &lt;50&gt;;</div><div class='ctx'> 		cdns,tchsh-ns = &lt;4&gt;;</div><div class='ctx'> 		cdns,tslch-ns = &lt;4&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;4&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='ctx'> </div><div class='ctx'> 		partitions {</div><div class='ctx'> 			compatible = "fixed-partitions";</div><div class='hunk'>@@ -121,12 +126,12 @@</div><div class='ctx'> </div><div class='ctx'> 			qspi_boot: partition@0 {</div><div class='ctx'> 				label = "Boot and fpga data";</div><div class='del'>-				reg = &lt;0x0 0x03FE0000&gt;;</div><div class='add'>+				reg = &lt;0x0 0x04200000&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			qspi_rootfs: partition@3FE0000 {</div><div class='del'>-				label = "Root Filesystem - JFFS2";</div><div class='del'>-				reg = &lt;0x03FE0000 0x0C020000&gt;;</div><div class='add'>+			root: partition@4200000 {</div><div class='add'>+				label = "Root Filesystem - UBIFS";</div><div class='add'>+				reg = &lt;0x04200000 0x0BE00000&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='head'>diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts<br/>index 979aa59a6bd0..98900cb410dc 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts</a></div><div class='hunk'>@@ -6,6 +6,7 @@</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	model = "SoCFPGA Agilex SoCDK";</div><div class='add'>+	compatible = "intel,socfpga-agilex-socdk", "intel,socfpga-agilex";</div><div class='ctx'> </div><div class='ctx'> 	aliases {</div><div class='ctx'> 		serial0 = &amp;uart0;</div><div class='hunk'>@@ -20,34 +21,26 @@</div><div class='ctx'> </div><div class='ctx'> 	leds {</div><div class='ctx'> 		compatible = "gpio-leds";</div><div class='del'>-		hps0 {</div><div class='add'>+		led0 {</div><div class='ctx'> 			label = "hps_led0";</div><div class='ctx'> 			gpios = &lt;&amp;portb 20 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		hps1 {</div><div class='add'>+		led1 {</div><div class='ctx'> 			label = "hps_led1";</div><div class='ctx'> 			gpios = &lt;&amp;portb 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		hps2 {</div><div class='add'>+		led2 {</div><div class='ctx'> 			label = "hps_led2";</div><div class='ctx'> 			gpios = &lt;&amp;portb 21 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	memory {</div><div class='add'>+	memory@80000000 {</div><div class='ctx'> 		device_type = "memory";</div><div class='ctx'> 		/* We expect the bootloader to fill in the reg */</div><div class='del'>-		reg = &lt;0 0 0 0&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	soc {</div><div class='del'>-		clocks {</div><div class='del'>-			osc1 {</div><div class='del'>-				clock-frequency = &lt;25000000&gt;;</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='add'>+		reg = &lt;0 0x80000000 0 0&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -88,7 +81,7 @@</div><div class='ctx'> &amp;nand {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='del'>-	flash@0 {</div><div class='add'>+	nand@0 {</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;1&gt;;</div><div class='ctx'> 		reg = &lt;0&gt;;</div><div class='hunk'>@@ -99,28 +92,16 @@</div><div class='ctx'> 			reg = &lt;0 0x200000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 		partition@200000 {</div><div class='del'>-			label = "env";</div><div class='del'>-			reg = &lt;0x200000 0x40000&gt;;</div><div class='del'>-		};</div><div class='del'>-		partition@240000 {</div><div class='del'>-			label = "dtb";</div><div class='del'>-			reg = &lt;0x240000 0x40000&gt;;</div><div class='del'>-		};</div><div class='del'>-		partition@280000 {</div><div class='del'>-			label = "kernel";</div><div class='del'>-			reg = &lt;0x280000 0x2000000&gt;;</div><div class='del'>-		};</div><div class='del'>-		partition@2280000 {</div><div class='del'>-			label = "misc";</div><div class='del'>-			reg = &lt;0x2280000 0x2000000&gt;;</div><div class='del'>-		};</div><div class='del'>-		partition@4280000 {</div><div class='del'>-			label = "rootfs";</div><div class='del'>-			reg = &lt;0x4280000 0x3bd80000&gt;;</div><div class='add'>+			label = "root";</div><div class='add'>+			reg = &lt;0x200000 0x3fe00000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;osc1 {</div><div class='add'>+	clock-frequency = &lt;25000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;uart0 {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts<br/>new file mode 100644<br/>index 000000000000..0034a4897220<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts</a></div><div class='hunk'>@@ -0,0 +1,128 @@</div><div class='add'>+// SPDX-License-Identifier:     GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2021, Intel Corporation</div><div class='add'>+ */</div><div class='add'>+#include "socfpga_agilex.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "eASIC N5X SoCDK";</div><div class='add'>+	compatible = "intel,n5x-socdk", "intel,socfpga-agilex";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+		ethernet0 = &amp;gmac0;</div><div class='add'>+		ethernet1 = &amp;gmac1;</div><div class='add'>+		ethernet2 = &amp;gmac2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@80000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		/* We expect the bootloader to fill in the reg */</div><div class='add'>+		reg = &lt;0 0x80000000 0 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc@0 {</div><div class='add'>+		sdram_edac: memory-controller@f87f8000 {</div><div class='add'>+			compatible = "snps,ddrc-3.80a";</div><div class='add'>+			reg = &lt;0xf87f8000 0x400&gt;;</div><div class='add'>+			interrupts = &lt;0 175 4&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;clkmgr {</div><div class='add'>+	compatible = "intel,easic-n5x-clkmgr";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gmac0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	phy-mode = "rgmii";</div><div class='add'>+	phy-handle = &lt;&amp;phy0&gt;;</div><div class='add'>+</div><div class='add'>+	max-frame-size = &lt;9000&gt;;</div><div class='add'>+</div><div class='add'>+	mdio0 {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+		phy0: ethernet-phy@0 {</div><div class='add'>+			reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+			txd0-skew-ps = &lt;0&gt;; /* -420ps */</div><div class='add'>+			txd1-skew-ps = &lt;0&gt;; /* -420ps */</div><div class='add'>+			txd2-skew-ps = &lt;0&gt;; /* -420ps */</div><div class='add'>+			txd3-skew-ps = &lt;0&gt;; /* -420ps */</div><div class='add'>+			rxd0-skew-ps = &lt;420&gt;; /* 0ps */</div><div class='add'>+			rxd1-skew-ps = &lt;420&gt;; /* 0ps */</div><div class='add'>+			rxd2-skew-ps = &lt;420&gt;; /* 0ps */</div><div class='add'>+			rxd3-skew-ps = &lt;420&gt;; /* 0ps */</div><div class='add'>+			txen-skew-ps = &lt;0&gt;; /* -420ps */</div><div class='add'>+			txc-skew-ps = &lt;900&gt;; /* 0ps */</div><div class='add'>+			rxdv-skew-ps = &lt;420&gt;; /* 0ps */</div><div class='add'>+			rxc-skew-ps = &lt;1680&gt;; /* 780ps */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc {</div><div class='add'>+	status = "okay";</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	broken-cd;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	clk-phase-sd-hs = &lt;0&gt;, &lt;135&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;osc1 {</div><div class='add'>+	clock-frequency = &lt;25000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qspi {</div><div class='add'>+	status = "okay";</div><div class='add'>+	flash@0 {</div><div class='add'>+		compatible = "micron,mt25qu02g", "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;100000000&gt;;</div><div class='add'>+</div><div class='add'>+		m25p,fast-read;</div><div class='add'>+		cdns,read-delay = &lt;2&gt;;</div><div class='add'>+		cdns,tshsl-ns = &lt;50&gt;;</div><div class='add'>+		cdns,tsd2d-ns = &lt;50&gt;;</div><div class='add'>+		cdns,tchsh-ns = &lt;4&gt;;</div><div class='add'>+		cdns,tslch-ns = &lt;4&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;4&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+		partitions {</div><div class='add'>+			compatible = "fixed-partitions";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			qspi_boot: partition@0 {</div><div class='add'>+				label = "Boot and fpga data";</div><div class='add'>+				reg = &lt;0x0 0x03FE0000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qspi_rootfs: partition@3fe0000 {</div><div class='add'>+				label = "Root Filesystem - JFFS2";</div><div class='add'>+				reg = &lt;0x03FE0000 0x0C020000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	disable-over-current;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;watchdog0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/lg/lg1312-ref.dts b/arch/arm64/boot/dts/lg/lg1312-ref.dts<br/>index 260a2c5b19e5..cdd10f138098 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/lg/lg1312-ref.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/lg/lg1312-ref.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/lg/lg1312-ref.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/lg/lg1312-ref.dts</a></div><div class='hunk'>@@ -22,7 +22,7 @@</div><div class='ctx'> 		serial2 = &amp;uart2;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	memory {</div><div class='add'>+	memory@0 {</div><div class='ctx'> 		device_type = "memory";</div><div class='ctx'> 		reg = &lt;0x0 0x00000000 0x20000000&gt;;</div><div class='ctx'> 	};</div><div class='head'>diff --git a/arch/arm64/boot/dts/lg/lg1312.dtsi b/arch/arm64/boot/dts/lg/lg1312.dtsi<br/>index 64f3b135068d..e83fdc92621e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/lg/lg1312.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/lg/lg1312.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/lg/lg1312.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/lg/lg1312.dtsi</a></div><div class='hunk'>@@ -5,101 +5,12 @@</div><div class='ctx'>  * Copyright (C) 2016, LG Electronics</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='ctx'> </div><div class='del'>-/ {</div><div class='del'>-	#address-cells = &lt;2&gt;;</div><div class='del'>-	#size-cells = &lt;2&gt;;</div><div class='add'>+#include "lg131x.dtsi"</div><div class='ctx'> </div><div class='add'>+/ {</div><div class='ctx'> 	compatible = "lge,lg1312";</div><div class='del'>-	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='del'>-</div><div class='del'>-	cpus {</div><div class='del'>-		#address-cells = &lt;2&gt;;</div><div class='del'>-		#size-cells = &lt;0&gt;;</div><div class='del'>-</div><div class='del'>-		cpu0: cpu@0 {</div><div class='del'>-			device_type = "cpu";</div><div class='del'>-			compatible = "arm,cortex-a53";</div><div class='del'>-			reg = &lt;0x0 0x0&gt;;</div><div class='del'>-			next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='del'>-		};</div><div class='del'>-		cpu1: cpu@1 {</div><div class='del'>-			device_type = "cpu";</div><div class='del'>-			compatible = "arm,cortex-a53";</div><div class='del'>-			reg = &lt;0x0 0x1&gt;;</div><div class='del'>-			enable-method = "psci";</div><div class='del'>-			next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='del'>-		};</div><div class='del'>-		cpu2: cpu@2 {</div><div class='del'>-			device_type = "cpu";</div><div class='del'>-			compatible = "arm,cortex-a53";</div><div class='del'>-			reg = &lt;0x0 0x2&gt;;</div><div class='del'>-			enable-method = "psci";</div><div class='del'>-			next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='del'>-		};</div><div class='del'>-		cpu3: cpu@3 {</div><div class='del'>-			device_type = "cpu";</div><div class='del'>-			compatible = "arm,cortex-a53";</div><div class='del'>-			reg = &lt;0x0 0x3&gt;;</div><div class='del'>-			enable-method = "psci";</div><div class='del'>-			next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='del'>-		};</div><div class='del'>-		L2_0: l2-cache0 {</div><div class='del'>-			compatible = "cache";</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	psci {</div><div class='del'>-		compatible  = "arm,psci-0.2", "arm,psci";</div><div class='del'>-		method = "smc";</div><div class='del'>-		cpu_suspend = &lt;0x84000001&gt;;</div><div class='del'>-		cpu_off = &lt;0x84000002&gt;;</div><div class='del'>-		cpu_on = &lt;0x84000003&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	gic: interrupt-controller@c0001000 {</div><div class='del'>-		#interrupt-cells = &lt;3&gt;;</div><div class='del'>-		compatible = "arm,gic-400";</div><div class='del'>-		interrupt-controller;</div><div class='del'>-		reg = &lt;0x0 0xc0001000 0x1000&gt;,</div><div class='del'>-		      &lt;0x0 0xc0002000 0x2000&gt;,</div><div class='del'>-		      &lt;0x0 0xc0004000 0x2000&gt;,</div><div class='del'>-		      &lt;0x0 0xc0006000 0x2000&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	pmu {</div><div class='del'>-		compatible = "arm,cortex-a53-pmu";</div><div class='del'>-		interrupts = &lt;GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-			     &lt;GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-			     &lt;GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-			     &lt;GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-		interrupt-affinity = &lt;&amp;cpu0&gt;,</div><div class='del'>-				     &lt;&amp;cpu1&gt;,</div><div class='del'>-				     &lt;&amp;cpu2&gt;,</div><div class='del'>-				     &lt;&amp;cpu3&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	timer {</div><div class='del'>-		compatible = "arm,armv8-timer";</div><div class='del'>-		interrupts = &lt;GIC_PPI 13 (GIC_CPU_MASK_RAW(0x0f) |</div><div class='del'>-			      IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='del'>-			     &lt;GIC_PPI 14 (GIC_CPU_MASK_RAW(0x0f) |</div><div class='del'>-			      IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='del'>-			     &lt;GIC_PPI 11 (GIC_CPU_MASK_RAW(0x0f) |</div><div class='del'>-			      IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='del'>-			     &lt;GIC_PPI 10 (GIC_CPU_MASK_RAW(0x0f) |</div><div class='del'>-			      IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	clk_bus: clk_bus {</div><div class='del'>-		#clock-cells = &lt;0&gt;;</div><div class='del'>-</div><div class='del'>-		compatible = "fixed-clock";</div><div class='del'>-		clock-frequency = &lt;198000000&gt;;</div><div class='del'>-		clock-output-names = "BUSCLK";</div><div class='del'>-	};</div><div class='ctx'> </div><div class='ctx'> 	soc {</div><div class='ctx'> 		#address-cells = &lt;2&gt;;</div><div class='hunk'>@@ -120,233 +31,4 @@</div><div class='ctx'> 			mac-address = [ 00 00 00 00 00 00 ];</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='del'>-</div><div class='del'>-	amba {</div><div class='del'>-		#address-cells = &lt;2&gt;;</div><div class='del'>-		#size-cells = &lt;1&gt;;</div><div class='del'>-		#interrupt-cells = &lt;3&gt;;</div><div class='del'>-</div><div class='del'>-		compatible = "simple-bus";</div><div class='del'>-		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='del'>-		ranges;</div><div class='del'>-</div><div class='del'>-		timers: timer@fd100000 {</div><div class='del'>-			compatible = "arm,sp804";</div><div class='del'>-			reg = &lt;0x0 0xfd100000 0x1000&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-		};</div><div class='del'>-		wdog: watchdog@fd200000 {</div><div class='del'>-			compatible = "arm,sp805", "arm,primecell";</div><div class='del'>-			reg = &lt;0x0 0xfd200000 0x1000&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-		};</div><div class='del'>-		uart0: serial@fe000000 {</div><div class='del'>-			compatible = "arm,pl011", "arm,primecell";</div><div class='del'>-			reg = &lt;0x0 0xfe000000 0x1000&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-			status="disabled";</div><div class='del'>-		};</div><div class='del'>-		uart1: serial@fe100000 {</div><div class='del'>-			compatible = "arm,pl011", "arm,primecell";</div><div class='del'>-			reg = &lt;0x0 0xfe100000 0x1000&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-			status="disabled";</div><div class='del'>-		};</div><div class='del'>-		uart2: serial@fe200000 {</div><div class='del'>-			compatible = "arm,pl011", "arm,primecell";</div><div class='del'>-			reg = &lt;0x0 0xfe200000 0x1000&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-			status="disabled";</div><div class='del'>-		};</div><div class='del'>-		spi0: spi@fe800000 {</div><div class='del'>-			compatible = "arm,pl022", "arm,primecell";</div><div class='del'>-			reg = &lt;0x0 0xfe800000 0x1000&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-		};</div><div class='del'>-		spi1: spi@fe900000 {</div><div class='del'>-			compatible = "arm,pl022", "arm,primecell";</div><div class='del'>-			reg = &lt;0x0 0xfe900000 0x1000&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-		};</div><div class='del'>-		dmac0: dma@c1128000 {</div><div class='del'>-			compatible = "arm,pl330", "arm,primecell";</div><div class='del'>-			reg = &lt;0x0 0xc1128000 0x1000&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-		};</div><div class='del'>-		gpio0: gpio@fd400000 {</div><div class='del'>-			#gpio-cells = &lt;2&gt;;</div><div class='del'>-			compatible = "arm,pl061", "arm,primecell";</div><div class='del'>-			gpio-controller;</div><div class='del'>-			reg = &lt;0x0 0xfd400000 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-			status="disabled";</div><div class='del'>-		};</div><div class='del'>-		gpio1: gpio@fd410000 {</div><div class='del'>-			#gpio-cells = &lt;2&gt;;</div><div class='del'>-			compatible = "arm,pl061", "arm,primecell";</div><div class='del'>-			gpio-controller;</div><div class='del'>-			reg = &lt;0x0 0xfd410000 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-			status="disabled";</div><div class='del'>-		};</div><div class='del'>-		gpio2: gpio@fd420000 {</div><div class='del'>-			#gpio-cells = &lt;2&gt;;</div><div class='del'>-			compatible = "arm,pl061", "arm,primecell";</div><div class='del'>-			gpio-controller;</div><div class='del'>-			reg = &lt;0x0 0xfd420000 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-			status="disabled";</div><div class='del'>-		};</div><div class='del'>-		gpio3: gpio@fd430000 {</div><div class='del'>-			#gpio-cells = &lt;2&gt;;</div><div class='del'>-			compatible = "arm,pl061", "arm,primecell";</div><div class='del'>-			gpio-controller;</div><div class='del'>-			reg = &lt;0x0 0xfd430000 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-		};</div><div class='del'>-		gpio4: gpio@fd440000 {</div><div class='del'>-			#gpio-cells = &lt;2&gt;;</div><div class='del'>-			compatible = "arm,pl061", "arm,primecell";</div><div class='del'>-			gpio-controller;</div><div class='del'>-			reg = &lt;0x0 0xfd440000 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-			status="disabled";</div><div class='del'>-		};</div><div class='del'>-		gpio5: gpio@fd450000 {</div><div class='del'>-			#gpio-cells = &lt;2&gt;;</div><div class='del'>-			compatible = "arm,pl061", "arm,primecell";</div><div class='del'>-			gpio-controller;</div><div class='del'>-			reg = &lt;0x0 0xfd450000 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-			status="disabled";</div><div class='del'>-		};</div><div class='del'>-		gpio6: gpio@fd460000 {</div><div class='del'>-			#gpio-cells = &lt;2&gt;;</div><div class='del'>-			compatible = "arm,pl061", "arm,primecell";</div><div class='del'>-			gpio-controller;</div><div class='del'>-			reg = &lt;0x0 0xfd460000 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-			status="disabled";</div><div class='del'>-		};</div><div class='del'>-		gpio7: gpio@fd470000 {</div><div class='del'>-			#gpio-cells = &lt;2&gt;;</div><div class='del'>-			compatible = "arm,pl061", "arm,primecell";</div><div class='del'>-			gpio-controller;</div><div class='del'>-			reg = &lt;0x0 0xfd470000 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-			status="disabled";</div><div class='del'>-		};</div><div class='del'>-		gpio8: gpio@fd480000 {</div><div class='del'>-			#gpio-cells = &lt;2&gt;;</div><div class='del'>-			compatible = "arm,pl061", "arm,primecell";</div><div class='del'>-			gpio-controller;</div><div class='del'>-			reg = &lt;0x0 0xfd480000 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-			status="disabled";</div><div class='del'>-		};</div><div class='del'>-		gpio9: gpio@fd490000 {</div><div class='del'>-			#gpio-cells = &lt;2&gt;;</div><div class='del'>-			compatible = "arm,pl061", "arm,primecell";</div><div class='del'>-			gpio-controller;</div><div class='del'>-			reg = &lt;0x0 0xfd490000 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-			status="disabled";</div><div class='del'>-		};</div><div class='del'>-		gpio10: gpio@fd4a0000 {</div><div class='del'>-			#gpio-cells = &lt;2&gt;;</div><div class='del'>-			compatible = "arm,pl061", "arm,primecell";</div><div class='del'>-			gpio-controller;</div><div class='del'>-			reg = &lt;0x0 0xfd4a0000 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-			status="disabled";</div><div class='del'>-		};</div><div class='del'>-		gpio11: gpio@fd4b0000 {</div><div class='del'>-			#gpio-cells = &lt;2&gt;;</div><div class='del'>-			compatible = "arm,pl061", "arm,primecell";</div><div class='del'>-			gpio-controller;</div><div class='del'>-			reg = &lt;0x0 0xfd4b0000 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-		};</div><div class='del'>-		gpio12: gpio@fd4c0000 {</div><div class='del'>-			#gpio-cells = &lt;2&gt;;</div><div class='del'>-			compatible = "arm,pl061", "arm,primecell";</div><div class='del'>-			gpio-controller;</div><div class='del'>-			reg = &lt;0x0 0xfd4c0000 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-			status="disabled";</div><div class='del'>-		};</div><div class='del'>-		gpio13: gpio@fd4d0000 {</div><div class='del'>-			#gpio-cells = &lt;2&gt;;</div><div class='del'>-			compatible = "arm,pl061", "arm,primecell";</div><div class='del'>-			gpio-controller;</div><div class='del'>-			reg = &lt;0x0 0xfd4d0000 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-			status="disabled";</div><div class='del'>-		};</div><div class='del'>-		gpio14: gpio@fd4e0000 {</div><div class='del'>-			#gpio-cells = &lt;2&gt;;</div><div class='del'>-			compatible = "arm,pl061", "arm,primecell";</div><div class='del'>-			gpio-controller;</div><div class='del'>-			reg = &lt;0x0 0xfd4e0000 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-			status="disabled";</div><div class='del'>-		};</div><div class='del'>-		gpio15: gpio@fd4f0000 {</div><div class='del'>-			#gpio-cells = &lt;2&gt;;</div><div class='del'>-			compatible = "arm,pl061", "arm,primecell";</div><div class='del'>-			gpio-controller;</div><div class='del'>-			reg = &lt;0x0 0xfd4f0000 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-			status="disabled";</div><div class='del'>-		};</div><div class='del'>-		gpio16: gpio@fd500000 {</div><div class='del'>-			#gpio-cells = &lt;2&gt;;</div><div class='del'>-			compatible = "arm,pl061", "arm,primecell";</div><div class='del'>-			gpio-controller;</div><div class='del'>-			reg = &lt;0x0 0xfd500000 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-			status="disabled";</div><div class='del'>-		};</div><div class='del'>-		gpio17: gpio@fd510000 {</div><div class='del'>-			#gpio-cells = &lt;2&gt;;</div><div class='del'>-			compatible = "arm,pl061", "arm,primecell";</div><div class='del'>-			gpio-controller;</div><div class='del'>-			reg = &lt;0x0 0xfd510000 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/lg/lg1313-ref.dts b/arch/arm64/boot/dts/lg/lg1313-ref.dts<br/>index e89ae853788a..6ace977ff4cf 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/lg/lg1313-ref.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/lg/lg1313-ref.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/lg/lg1313-ref.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/lg/lg1313-ref.dts</a></div><div class='hunk'>@@ -22,7 +22,7 @@</div><div class='ctx'> 		serial2 = &amp;uart2;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	memory {</div><div class='add'>+	memory@0 {</div><div class='ctx'> 		device_type = "memory";</div><div class='ctx'> 		reg = &lt;0x0 0x00000000 0x20000000&gt;;</div><div class='ctx'> 	};</div><div class='head'>diff --git a/arch/arm64/boot/dts/lg/lg1313.dtsi b/arch/arm64/boot/dts/lg/lg1313.dtsi<br/>index ac23592ab011..92fa5694cad1 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/lg/lg1313.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/lg/lg1313.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/lg/lg1313.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/lg/lg1313.dtsi</a></div><div class='hunk'>@@ -5,101 +5,12 @@</div><div class='ctx'>  * Copyright (C) 2016, LG Electronics</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='ctx'> </div><div class='del'>-/ {</div><div class='del'>-	#address-cells = &lt;2&gt;;</div><div class='del'>-	#size-cells = &lt;2&gt;;</div><div class='add'>+#include "lg131x.dtsi"</div><div class='ctx'> </div><div class='add'>+/ {</div><div class='ctx'> 	compatible = "lge,lg1313";</div><div class='del'>-	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='del'>-</div><div class='del'>-	cpus {</div><div class='del'>-		#address-cells = &lt;2&gt;;</div><div class='del'>-		#size-cells = &lt;0&gt;;</div><div class='del'>-</div><div class='del'>-		cpu0: cpu@0 {</div><div class='del'>-			device_type = "cpu";</div><div class='del'>-			compatible = "arm,cortex-a53";</div><div class='del'>-			reg = &lt;0x0 0x0&gt;;</div><div class='del'>-			next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='del'>-		};</div><div class='del'>-		cpu1: cpu@1 {</div><div class='del'>-			device_type = "cpu";</div><div class='del'>-			compatible = "arm,cortex-a53";</div><div class='del'>-			reg = &lt;0x0 0x1&gt;;</div><div class='del'>-			enable-method = "psci";</div><div class='del'>-			next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='del'>-		};</div><div class='del'>-		cpu2: cpu@2 {</div><div class='del'>-			device_type = "cpu";</div><div class='del'>-			compatible = "arm,cortex-a53";</div><div class='del'>-			reg = &lt;0x0 0x2&gt;;</div><div class='del'>-			enable-method = "psci";</div><div class='del'>-			next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='del'>-		};</div><div class='del'>-		cpu3: cpu@3 {</div><div class='del'>-			device_type = "cpu";</div><div class='del'>-			compatible = "arm,cortex-a53";</div><div class='del'>-			reg = &lt;0x0 0x3&gt;;</div><div class='del'>-			enable-method = "psci";</div><div class='del'>-			next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='del'>-		};</div><div class='del'>-		L2_0: l2-cache0 {</div><div class='del'>-			compatible = "cache";</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	psci {</div><div class='del'>-		compatible  = "arm,psci-0.2", "arm,psci";</div><div class='del'>-		method = "smc";</div><div class='del'>-		cpu_suspend = &lt;0x84000001&gt;;</div><div class='del'>-		cpu_off = &lt;0x84000002&gt;;</div><div class='del'>-		cpu_on = &lt;0x84000003&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	gic: interrupt-controller@c0001000 {</div><div class='del'>-		#interrupt-cells = &lt;3&gt;;</div><div class='del'>-		compatible = "arm,gic-400";</div><div class='del'>-		interrupt-controller;</div><div class='del'>-		reg = &lt;0x0 0xc0001000 0x1000&gt;,</div><div class='del'>-		      &lt;0x0 0xc0002000 0x2000&gt;,</div><div class='del'>-		      &lt;0x0 0xc0004000 0x2000&gt;,</div><div class='del'>-		      &lt;0x0 0xc0006000 0x2000&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	pmu {</div><div class='del'>-		compatible = "arm,cortex-a53-pmu";</div><div class='del'>-		interrupts = &lt;GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-			     &lt;GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-			     &lt;GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-			     &lt;GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-		interrupt-affinity = &lt;&amp;cpu0&gt;,</div><div class='del'>-				     &lt;&amp;cpu1&gt;,</div><div class='del'>-				     &lt;&amp;cpu2&gt;,</div><div class='del'>-				     &lt;&amp;cpu3&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	timer {</div><div class='del'>-		compatible = "arm,armv8-timer";</div><div class='del'>-		interrupts = &lt;GIC_PPI 13 (GIC_CPU_MASK_RAW(0x0f) |</div><div class='del'>-			      IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='del'>-			     &lt;GIC_PPI 14 (GIC_CPU_MASK_RAW(0x0f) |</div><div class='del'>-			      IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='del'>-			     &lt;GIC_PPI 11 (GIC_CPU_MASK_RAW(0x0f) |</div><div class='del'>-			      IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='del'>-			     &lt;GIC_PPI 10 (GIC_CPU_MASK_RAW(0x0f) |</div><div class='del'>-			      IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	clk_bus: clk_bus {</div><div class='del'>-		#clock-cells = &lt;0&gt;;</div><div class='del'>-</div><div class='del'>-		compatible = "fixed-clock";</div><div class='del'>-		clock-frequency = &lt;198000000&gt;;</div><div class='del'>-		clock-output-names = "BUSCLK";</div><div class='del'>-	};</div><div class='ctx'> </div><div class='ctx'> 	soc {</div><div class='ctx'> 		#address-cells = &lt;2&gt;;</div><div class='hunk'>@@ -120,233 +31,4 @@</div><div class='ctx'> 			mac-address = [ 00 00 00 00 00 00 ];</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='del'>-</div><div class='del'>-	amba {</div><div class='del'>-		#address-cells = &lt;2&gt;;</div><div class='del'>-		#size-cells = &lt;1&gt;;</div><div class='del'>-		#interrupt-cells = &lt;3&gt;;</div><div class='del'>-</div><div class='del'>-		compatible = "simple-bus";</div><div class='del'>-		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='del'>-		ranges;</div><div class='del'>-</div><div class='del'>-		timers: timer@fd100000 {</div><div class='del'>-			compatible = "arm,sp804";</div><div class='del'>-			reg = &lt;0x0 0xfd100000 0x1000&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-		};</div><div class='del'>-		wdog: watchdog@fd200000 {</div><div class='del'>-			compatible = "arm,sp805", "arm,primecell";</div><div class='del'>-			reg = &lt;0x0 0xfd200000 0x1000&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-		};</div><div class='del'>-		uart0: serial@fe000000 {</div><div class='del'>-			compatible = "arm,pl011", "arm,primecell";</div><div class='del'>-			reg = &lt;0x0 0xfe000000 0x1000&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-			status="disabled";</div><div class='del'>-		};</div><div class='del'>-		uart1: serial@fe100000 {</div><div class='del'>-			compatible = "arm,pl011", "arm,primecell";</div><div class='del'>-			reg = &lt;0x0 0xfe100000 0x1000&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-			status="disabled";</div><div class='del'>-		};</div><div class='del'>-		uart2: serial@fe200000 {</div><div class='del'>-			compatible = "arm,pl011", "arm,primecell";</div><div class='del'>-			reg = &lt;0x0 0xfe200000 0x1000&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-			status="disabled";</div><div class='del'>-		};</div><div class='del'>-		spi0: spi@fe800000 {</div><div class='del'>-			compatible = "arm,pl022", "arm,primecell";</div><div class='del'>-			reg = &lt;0x0 0xfe800000 0x1000&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-		};</div><div class='del'>-		spi1: spi@fe900000 {</div><div class='del'>-			compatible = "arm,pl022", "arm,primecell";</div><div class='del'>-			reg = &lt;0x0 0xfe900000 0x1000&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-		};</div><div class='del'>-		dmac0: dma@c1128000 {</div><div class='del'>-			compatible = "arm,pl330", "arm,primecell";</div><div class='del'>-			reg = &lt;0x0 0xc1128000 0x1000&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-		};</div><div class='del'>-		gpio0: gpio@fd400000 {</div><div class='del'>-			#gpio-cells = &lt;2&gt;;</div><div class='del'>-			compatible = "arm,pl061", "arm,primecell";</div><div class='del'>-			gpio-controller;</div><div class='del'>-			reg = &lt;0x0 0xfd400000 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-			status="disabled";</div><div class='del'>-		};</div><div class='del'>-		gpio1: gpio@fd410000 {</div><div class='del'>-			#gpio-cells = &lt;2&gt;;</div><div class='del'>-			compatible = "arm,pl061", "arm,primecell";</div><div class='del'>-			gpio-controller;</div><div class='del'>-			reg = &lt;0x0 0xfd410000 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-			status="disabled";</div><div class='del'>-		};</div><div class='del'>-		gpio2: gpio@fd420000 {</div><div class='del'>-			#gpio-cells = &lt;2&gt;;</div><div class='del'>-			compatible = "arm,pl061", "arm,primecell";</div><div class='del'>-			gpio-controller;</div><div class='del'>-			reg = &lt;0x0 0xfd420000 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-			status="disabled";</div><div class='del'>-		};</div><div class='del'>-		gpio3: gpio@fd430000 {</div><div class='del'>-			#gpio-cells = &lt;2&gt;;</div><div class='del'>-			compatible = "arm,pl061", "arm,primecell";</div><div class='del'>-			gpio-controller;</div><div class='del'>-			reg = &lt;0x0 0xfd430000 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-		};</div><div class='del'>-		gpio4: gpio@fd440000 {</div><div class='del'>-			#gpio-cells = &lt;2&gt;;</div><div class='del'>-			compatible = "arm,pl061", "arm,primecell";</div><div class='del'>-			gpio-controller;</div><div class='del'>-			reg = &lt;0x0 0xfd440000 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-			status="disabled";</div><div class='del'>-		};</div><div class='del'>-		gpio5: gpio@fd450000 {</div><div class='del'>-			#gpio-cells = &lt;2&gt;;</div><div class='del'>-			compatible = "arm,pl061", "arm,primecell";</div><div class='del'>-			gpio-controller;</div><div class='del'>-			reg = &lt;0x0 0xfd450000 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-			status="disabled";</div><div class='del'>-		};</div><div class='del'>-		gpio6: gpio@fd460000 {</div><div class='del'>-			#gpio-cells = &lt;2&gt;;</div><div class='del'>-			compatible = "arm,pl061", "arm,primecell";</div><div class='del'>-			gpio-controller;</div><div class='del'>-			reg = &lt;0x0 0xfd460000 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-			status="disabled";</div><div class='del'>-		};</div><div class='del'>-		gpio7: gpio@fd470000 {</div><div class='del'>-			#gpio-cells = &lt;2&gt;;</div><div class='del'>-			compatible = "arm,pl061", "arm,primecell";</div><div class='del'>-			gpio-controller;</div><div class='del'>-			reg = &lt;0x0 0xfd470000 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-			status="disabled";</div><div class='del'>-		};</div><div class='del'>-		gpio8: gpio@fd480000 {</div><div class='del'>-			#gpio-cells = &lt;2&gt;;</div><div class='del'>-			compatible = "arm,pl061", "arm,primecell";</div><div class='del'>-			gpio-controller;</div><div class='del'>-			reg = &lt;0x0 0xfd480000 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-			status="disabled";</div><div class='del'>-		};</div><div class='del'>-		gpio9: gpio@fd490000 {</div><div class='del'>-			#gpio-cells = &lt;2&gt;;</div><div class='del'>-			compatible = "arm,pl061", "arm,primecell";</div><div class='del'>-			gpio-controller;</div><div class='del'>-			reg = &lt;0x0 0xfd490000 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-			status="disabled";</div><div class='del'>-		};</div><div class='del'>-		gpio10: gpio@fd4a0000 {</div><div class='del'>-			#gpio-cells = &lt;2&gt;;</div><div class='del'>-			compatible = "arm,pl061", "arm,primecell";</div><div class='del'>-			gpio-controller;</div><div class='del'>-			reg = &lt;0x0 0xfd4a0000 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-			status="disabled";</div><div class='del'>-		};</div><div class='del'>-		gpio11: gpio@fd4b0000 {</div><div class='del'>-			#gpio-cells = &lt;2&gt;;</div><div class='del'>-			compatible = "arm,pl061", "arm,primecell";</div><div class='del'>-			gpio-controller;</div><div class='del'>-			reg = &lt;0x0 0xfd4b0000 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-		};</div><div class='del'>-		gpio12: gpio@fd4c0000 {</div><div class='del'>-			#gpio-cells = &lt;2&gt;;</div><div class='del'>-			compatible = "arm,pl061", "arm,primecell";</div><div class='del'>-			gpio-controller;</div><div class='del'>-			reg = &lt;0x0 0xfd4c0000 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-			status="disabled";</div><div class='del'>-		};</div><div class='del'>-		gpio13: gpio@fd4d0000 {</div><div class='del'>-			#gpio-cells = &lt;2&gt;;</div><div class='del'>-			compatible = "arm,pl061", "arm,primecell";</div><div class='del'>-			gpio-controller;</div><div class='del'>-			reg = &lt;0x0 0xfd4d0000 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-			status="disabled";</div><div class='del'>-		};</div><div class='del'>-		gpio14: gpio@fd4e0000 {</div><div class='del'>-			#gpio-cells = &lt;2&gt;;</div><div class='del'>-			compatible = "arm,pl061", "arm,primecell";</div><div class='del'>-			gpio-controller;</div><div class='del'>-			reg = &lt;0x0 0xfd4e0000 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-			status="disabled";</div><div class='del'>-		};</div><div class='del'>-		gpio15: gpio@fd4f0000 {</div><div class='del'>-			#gpio-cells = &lt;2&gt;;</div><div class='del'>-			compatible = "arm,pl061", "arm,primecell";</div><div class='del'>-			gpio-controller;</div><div class='del'>-			reg = &lt;0x0 0xfd4f0000 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-			status="disabled";</div><div class='del'>-		};</div><div class='del'>-		gpio16: gpio@fd500000 {</div><div class='del'>-			#gpio-cells = &lt;2&gt;;</div><div class='del'>-			compatible = "arm,pl061", "arm,primecell";</div><div class='del'>-			gpio-controller;</div><div class='del'>-			reg = &lt;0x0 0xfd500000 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-			status="disabled";</div><div class='del'>-		};</div><div class='del'>-		gpio17: gpio@fd510000 {</div><div class='del'>-			#gpio-cells = &lt;2&gt;;</div><div class='del'>-			compatible = "arm,pl061", "arm,primecell";</div><div class='del'>-			gpio-controller;</div><div class='del'>-			reg = &lt;0x0 0xfd510000 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk_bus&gt;;</div><div class='del'>-			clock-names = "apb_pclk";</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/lg/lg131x.dtsi b/arch/arm64/boot/dts/lg/lg131x.dtsi<br/>new file mode 100644<br/>index 000000000000..4cb1e4510897<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/lg/lg131x.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/lg/lg131x.dtsi</a></div><div class='hunk'>@@ -0,0 +1,333 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * dts file for lg131x SoCs</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) 2016, LG Electronics</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x0 0x0&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='add'>+		};</div><div class='add'>+		cpu1: cpu@1 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x0 0x1&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='add'>+		};</div><div class='add'>+		cpu2: cpu@2 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x0 0x2&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='add'>+		};</div><div class='add'>+		cpu3: cpu@3 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x0 0x3&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='add'>+		};</div><div class='add'>+		L2_0: l2-cache0 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-0.2", "arm,psci";</div><div class='add'>+		method = "smc";</div><div class='add'>+		cpu_suspend = &lt;0x84000001&gt;;</div><div class='add'>+		cpu_off = &lt;0x84000002&gt;;</div><div class='add'>+		cpu_on = &lt;0x84000003&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gic: interrupt-controller@c0001000 {</div><div class='add'>+		#interrupt-cells = &lt;3&gt;;</div><div class='add'>+		compatible = "arm,gic-400";</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		reg = &lt;0x0 0xc0001000 0x1000&gt;,</div><div class='add'>+		      &lt;0x0 0xc0002000 0x2000&gt;,</div><div class='add'>+		      &lt;0x0 0xc0004000 0x2000&gt;,</div><div class='add'>+		      &lt;0x0 0xc0006000 0x2000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu {</div><div class='add'>+		compatible = "arm,cortex-a53-pmu";</div><div class='add'>+		interrupts = &lt;GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-affinity = &lt;&amp;cpu0&gt;,</div><div class='add'>+				     &lt;&amp;cpu1&gt;,</div><div class='add'>+				     &lt;&amp;cpu2&gt;,</div><div class='add'>+				     &lt;&amp;cpu3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 (GIC_CPU_MASK_RAW(0x0f) |</div><div class='add'>+			      IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 (GIC_CPU_MASK_RAW(0x0f) |</div><div class='add'>+			      IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 (GIC_CPU_MASK_RAW(0x0f) |</div><div class='add'>+			      IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 (GIC_CPU_MASK_RAW(0x0f) |</div><div class='add'>+			      IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_bus: clk_bus {</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		clock-frequency = &lt;198000000&gt;;</div><div class='add'>+		clock-output-names = "BUSCLK";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	amba {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		timers: timer@fd100000 {</div><div class='add'>+			compatible = "arm,sp804", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0xfd100000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk_bus&gt;, &lt;&amp;clk_bus&gt;, &lt;&amp;clk_bus&gt;;</div><div class='add'>+			clock-names = "timer0clk", "timer1clk", "apb_pclk";</div><div class='add'>+		};</div><div class='add'>+		wdog: watchdog@fd200000 {</div><div class='add'>+			compatible = "arm,sp805", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0xfd200000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk_bus&gt;, &lt;&amp;clk_bus&gt;;</div><div class='add'>+			clock-names = "wdog_clk", "apb_pclk";</div><div class='add'>+		};</div><div class='add'>+		uart0: serial@fe000000 {</div><div class='add'>+			compatible = "arm,pl011", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0xfe000000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk_bus&gt;, &lt;&amp;clk_bus&gt;;</div><div class='add'>+			clock-names = "uartclk", "apb_pclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+		uart1: serial@fe100000 {</div><div class='add'>+			compatible = "arm,pl011", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0xfe100000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk_bus&gt;, &lt;&amp;clk_bus&gt;;</div><div class='add'>+			clock-names = "uartclk", "apb_pclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+		uart2: serial@fe200000 {</div><div class='add'>+			compatible = "arm,pl011", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0xfe200000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk_bus&gt;, &lt;&amp;clk_bus&gt;;</div><div class='add'>+			clock-names = "uartclk", "apb_pclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+		spi0: spi@fe800000 {</div><div class='add'>+			compatible = "arm,pl022", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0xfe800000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk_bus&gt;, &lt;&amp;clk_bus&gt;;</div><div class='add'>+			clock-names = "sspclk", "apb_pclk";</div><div class='add'>+		};</div><div class='add'>+		spi1: spi@fe900000 {</div><div class='add'>+			compatible = "arm,pl022", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0xfe900000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk_bus&gt;, &lt;&amp;clk_bus&gt;;</div><div class='add'>+			clock-names = "sspclk", "apb_pclk";</div><div class='add'>+		};</div><div class='add'>+		dmac0: dma-controller@c1128000 {</div><div class='add'>+			compatible = "arm,pl330", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0xc1128000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk_bus&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+		gpio0: gpio@fd400000 {</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			compatible = "arm,pl061", "arm,primecell";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			reg = &lt;0x0 0xfd400000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk_bus&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+		gpio1: gpio@fd410000 {</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			compatible = "arm,pl061", "arm,primecell";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			reg = &lt;0x0 0xfd410000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk_bus&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+		gpio2: gpio@fd420000 {</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			compatible = "arm,pl061", "arm,primecell";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			reg = &lt;0x0 0xfd420000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk_bus&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+		gpio3: gpio@fd430000 {</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			compatible = "arm,pl061", "arm,primecell";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			reg = &lt;0x0 0xfd430000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk_bus&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+		};</div><div class='add'>+		gpio4: gpio@fd440000 {</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			compatible = "arm,pl061", "arm,primecell";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			reg = &lt;0x0 0xfd440000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk_bus&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+		gpio5: gpio@fd450000 {</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			compatible = "arm,pl061", "arm,primecell";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			reg = &lt;0x0 0xfd450000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk_bus&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+		gpio6: gpio@fd460000 {</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			compatible = "arm,pl061", "arm,primecell";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			reg = &lt;0x0 0xfd460000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk_bus&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+		gpio7: gpio@fd470000 {</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			compatible = "arm,pl061", "arm,primecell";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			reg = &lt;0x0 0xfd470000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk_bus&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+		gpio8: gpio@fd480000 {</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			compatible = "arm,pl061", "arm,primecell";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			reg = &lt;0x0 0xfd480000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk_bus&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+		gpio9: gpio@fd490000 {</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			compatible = "arm,pl061", "arm,primecell";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			reg = &lt;0x0 0xfd490000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk_bus&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+		gpio10: gpio@fd4a0000 {</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			compatible = "arm,pl061", "arm,primecell";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			reg = &lt;0x0 0xfd4a0000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk_bus&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+		gpio11: gpio@fd4b0000 {</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			compatible = "arm,pl061", "arm,primecell";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			reg = &lt;0x0 0xfd4b0000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk_bus&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+		};</div><div class='add'>+		gpio12: gpio@fd4c0000 {</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			compatible = "arm,pl061", "arm,primecell";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			reg = &lt;0x0 0xfd4c0000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk_bus&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+		gpio13: gpio@fd4d0000 {</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			compatible = "arm,pl061", "arm,primecell";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			reg = &lt;0x0 0xfd4d0000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk_bus&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+		gpio14: gpio@fd4e0000 {</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			compatible = "arm,pl061", "arm,primecell";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			reg = &lt;0x0 0xfd4e0000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk_bus&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+		gpio15: gpio@fd4f0000 {</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			compatible = "arm,pl061", "arm,primecell";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			reg = &lt;0x0 0xfd4f0000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk_bus&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+		gpio16: gpio@fd500000 {</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			compatible = "arm,pl061", "arm,primecell";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			reg = &lt;0x0 0xfd500000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk_bus&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+		gpio17: gpio@fd510000 {</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			compatible = "arm,pl061", "arm,primecell";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			reg = &lt;0x0 0xfd510000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk_bus&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile<br/>index 3e5f2e7a040c..a774bc74a0a0 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/Makefile?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/Makefile</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/Makefile</a></div><div class='hunk'>@@ -1,18 +1,37 @@</div><div class='ctx'> # SPDX-License-Identifier: GPL-2.0</div><div class='ctx'> # Mvebu SoC Family</div><div class='add'>+dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-atlas-v5.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-db.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-eDPU.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin-emmc.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin-ultra.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin-v7.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin-v7-emmc.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-gl-mv1000.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-turris-mox.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-uDPU.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MVEBU) += armada-7040-db.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MVEBU) += armada-7040-mochabin.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-clearfog-gt-8k.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-db.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin-singleshot.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-puzzle-m801.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MVEBU) += armada-8080-db.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MVEBU) += cn9130-db.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MVEBU) += cn9130-db-B.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db-B.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MVEBU) += ac5x-rd-carrier-cn9131.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MVEBU) += ac5-98dx35xx-rd.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MVEBU) += cn9130-cf-base.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MVEBU) += cn9130-cf-pro.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MVEBU) += cn9131-cf-solidwan.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MVEBU) += cn9132-clearfog.dtb</div><div class='add'>+</div><div class='add'>+subdir-y	+= mmp</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi<br/>new file mode 100644<br/>index 000000000000..4878773883c9<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi</a></div><div class='hunk'>@@ -0,0 +1,368 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Device Tree For AC5.</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) 2021 Marvell</div><div class='add'>+ * Copyright (C) 2022 Allied Telesis Labs</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Marvell AC5 SoC";</div><div class='add'>+	compatible = "marvell,ac5";</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu-map {</div><div class='add'>+			cluster0 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu0&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu1&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x0 0x0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@1 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x0 0x100&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2: l2-cache {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-0.2";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu {</div><div class='add'>+		compatible = "arm,cortex-a55-pmu";</div><div class='add'>+		interrupts = &lt;GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		bus@7f000000 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			compatible = "simple-bus";</div><div class='add'>+			/* 16M internal register @ 0x7f00_0000 */</div><div class='add'>+			ranges = &lt;0x0 0x0 0x7f000000 0x1000000&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+</div><div class='add'>+			uart0: serial@12000 {</div><div class='add'>+				compatible = "snps,dw-apb-uart";</div><div class='add'>+				reg = &lt;0x12000 0x100&gt;;</div><div class='add'>+				reg-shift = &lt;2&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				reg-io-width = &lt;1&gt;;</div><div class='add'>+				clocks = &lt;&amp;cnm_clock&gt;;</div><div class='add'>+				status = "okay";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart1: serial@12100 {</div><div class='add'>+				compatible = "snps,dw-apb-uart";</div><div class='add'>+				reg = &lt;0x12100 0x100&gt;;</div><div class='add'>+				reg-shift = &lt;2&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				reg-io-width = &lt;1&gt;;</div><div class='add'>+				clocks = &lt;&amp;cnm_clock&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart2: serial@12200 {</div><div class='add'>+				compatible = "snps,dw-apb-uart";</div><div class='add'>+				reg = &lt;0x12200 0x100&gt;;</div><div class='add'>+				reg-shift = &lt;2&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				reg-io-width = &lt;1&gt;;</div><div class='add'>+				clocks = &lt;&amp;cnm_clock&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart3: serial@12300 {</div><div class='add'>+				compatible = "snps,dw-apb-uart";</div><div class='add'>+				reg = &lt;0x12300 0x100&gt;;</div><div class='add'>+				reg-shift = &lt;2&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				reg-io-width = &lt;1&gt;;</div><div class='add'>+				clocks = &lt;&amp;cnm_clock&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mdio: mdio@22004 {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				compatible = "marvell,orion-mdio";</div><div class='add'>+				reg = &lt;0x22004 0x4&gt;;</div><div class='add'>+				clocks = &lt;&amp;cnm_clock&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c0: i2c@11000 {</div><div class='add'>+				compatible = "marvell,mv78230-i2c";</div><div class='add'>+				reg = &lt;0x11000 0x20&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;cnm_clock&gt;;</div><div class='add'>+				clock-names = "core";</div><div class='add'>+				interrupts = &lt;GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clock-frequency = &lt;100000&gt;;</div><div class='add'>+</div><div class='add'>+				pinctrl-names = "default", "gpio";</div><div class='add'>+				pinctrl-0 = &lt;&amp;i2c0_pins&gt;;</div><div class='add'>+				pinctrl-1 = &lt;&amp;i2c0_gpio&gt;;</div><div class='add'>+				scl-gpios = &lt;&amp;gpio0 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+				sda-gpios = &lt;&amp;gpio0 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c1: i2c@11100 {</div><div class='add'>+				compatible = "marvell,mv78230-i2c";</div><div class='add'>+				reg = &lt;0x11100 0x20&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;cnm_clock&gt;;</div><div class='add'>+				clock-names = "core";</div><div class='add'>+				interrupts = &lt;GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clock-frequency = &lt;100000&gt;;</div><div class='add'>+</div><div class='add'>+				pinctrl-names = "default", "gpio";</div><div class='add'>+				pinctrl-0 = &lt;&amp;i2c1_pins&gt;;</div><div class='add'>+				pinctrl-1 = &lt;&amp;i2c1_gpio&gt;;</div><div class='add'>+				scl-gpios = &lt;&amp;gpio0 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+				sda-gpios = &lt;&amp;gpio0 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gpio0: gpio@18100 {</div><div class='add'>+				compatible = "marvell,orion-gpio";</div><div class='add'>+				reg = &lt;0x18100 0x40&gt;;</div><div class='add'>+				ngpios = &lt;32&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+				gpio-ranges = &lt;&amp;pinctrl0 0 0 32&gt;;</div><div class='add'>+				marvell,pwm-offset = &lt;0x1f0&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;2&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gpio1: gpio@18140 {</div><div class='add'>+				reg = &lt;0x18140 0x40&gt;;</div><div class='add'>+				compatible = "marvell,orion-gpio";</div><div class='add'>+				ngpios = &lt;14&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+				gpio-ranges = &lt;&amp;pinctrl0 0 32 14&gt;;</div><div class='add'>+				marvell,pwm-offset = &lt;0x1f0&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;2&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmc_dma: bus@80500000 {</div><div class='add'>+				compatible = "simple-bus";</div><div class='add'>+				ranges;</div><div class='add'>+				#address-cells = &lt;0x2&gt;;</div><div class='add'>+				#size-cells = &lt;0x2&gt;;</div><div class='add'>+				reg = &lt;0x0 0x80500000 0x0 0x100000&gt;;</div><div class='add'>+				dma-ranges = &lt;0x0 0x0 0x2 0x0 0x0 0x80000000&gt;;</div><div class='add'>+				dma-coherent;</div><div class='add'>+</div><div class='add'>+				sdhci: mmc@805c0000 {</div><div class='add'>+					compatible = "marvell,ac5-sdhci",</div><div class='add'>+						     "marvell,armada-ap806-sdhci";</div><div class='add'>+					reg = &lt;0x0 0x805c0000 0x0 0x1000&gt;;</div><div class='add'>+					interrupts = &lt;GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+					clocks = &lt;&amp;emmc_clock&gt;, &lt;&amp;cnm_clock&gt;;</div><div class='add'>+					clock-names = "core", "axi";</div><div class='add'>+					bus-width = &lt;8&gt;;</div><div class='add'>+					non-removable;</div><div class='add'>+					mmc-ddr-1_8v;</div><div class='add'>+					mmc-hs200-1_8v;</div><div class='add'>+					mmc-hs400-1_8v;</div><div class='add'>+				};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Dedicated section for devices behind 32bit controllers so we</div><div class='add'>+		 * can configure specific DMA mapping for them</div><div class='add'>+		 */</div><div class='add'>+		behind-32bit-controller@7f000000 {</div><div class='add'>+			compatible = "simple-bus";</div><div class='add'>+			#address-cells = &lt;0x2&gt;;</div><div class='add'>+			#size-cells = &lt;0x2&gt;;</div><div class='add'>+			ranges = &lt;0x0 0x0 0x0 0x7f000000 0x0 0x1000000&gt;;</div><div class='add'>+			/* Host phy ram starts at 0x200M */</div><div class='add'>+			dma-ranges = &lt;0x0 0x0 0x2 0x0 0x1 0x0&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+</div><div class='add'>+			eth0: ethernet@20000 {</div><div class='add'>+				compatible = "marvell,armada-ac5-neta";</div><div class='add'>+				reg = &lt;0x0 0x20000 0x0 0x4000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;cnm_clock&gt;;</div><div class='add'>+				phy-mode = "sgmii";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			eth1: ethernet@24000 {</div><div class='add'>+				compatible = "marvell,armada-ac5-neta";</div><div class='add'>+				reg = &lt;0x0 0x24000 0x0 0x4000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;cnm_clock&gt;;</div><div class='add'>+				phy-mode = "sgmii";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			usb0: usb@80000 {</div><div class='add'>+				compatible = "marvell,orion-ehci";</div><div class='add'>+				reg = &lt;0x0 0x80000 0x0 0x500&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			usb1: usb@a0000 {</div><div class='add'>+				compatible = "marvell,orion-ehci";</div><div class='add'>+				reg = &lt;0x0 0xa0000 0x0 0x500&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl0: pinctrl@80020100 {</div><div class='add'>+			compatible = "marvell,ac5-pinctrl";</div><div class='add'>+			reg = &lt;0 0x80020100 0 0x20&gt;;</div><div class='add'>+</div><div class='add'>+			i2c0_pins: i2c0-pins {</div><div class='add'>+				marvell,pins = "mpp26", "mpp27";</div><div class='add'>+				marvell,function = "i2c0";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c0_gpio: i2c0-gpio-pins {</div><div class='add'>+				marvell,pins = "mpp26", "mpp27";</div><div class='add'>+				marvell,function = "gpio";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c1_pins: i2c1-pins {</div><div class='add'>+				marvell,pins = "mpp20", "mpp21";</div><div class='add'>+				marvell,function = "i2c1";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c1_gpio: i2c1-gpio-pins {</div><div class='add'>+				marvell,pins = "mpp20", "mpp21";</div><div class='add'>+				marvell,function = "i2c1";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi0: spi@805a0000 {</div><div class='add'>+			compatible = "marvell,armada-3700-spi";</div><div class='add'>+			reg = &lt;0x0 0x805a0000 0x0 0x50&gt;;</div><div class='add'>+			#address-cells = &lt;0x1&gt;;</div><div class='add'>+			#size-cells = &lt;0x0&gt;;</div><div class='add'>+			clocks = &lt;&amp;spi_clock&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			num-cs = &lt;1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi1: spi@805a8000 {</div><div class='add'>+			compatible = "marvell,armada-3700-spi";</div><div class='add'>+			reg = &lt;0x0 0x805a8000 0x0 0x50&gt;;</div><div class='add'>+			#address-cells = &lt;0x1&gt;;</div><div class='add'>+			#size-cells = &lt;0x0&gt;;</div><div class='add'>+			clocks = &lt;&amp;spi_clock&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			num-cs = &lt;1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nand: nand-controller@805b0000 {</div><div class='add'>+			compatible = "marvell,ac5-nand-controller";</div><div class='add'>+			reg = &lt;0x0 0x805b0000 0x0 0x00000054&gt;;</div><div class='add'>+			#address-cells = &lt;0x1&gt;;</div><div class='add'>+			#size-cells = &lt;0x0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;nand_clock&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@80600000 {</div><div class='add'>+			compatible = "arm,gic-v3";</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			reg = &lt;0x0 0x80600000 0x0 0x10000&gt;, /* GICD */</div><div class='add'>+			      &lt;0x0 0x80660000 0x0 0x40000&gt;; /* GICR */</div><div class='add'>+			interrupts = &lt;GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clocks {</div><div class='add'>+		cnm_clock: cnm-clock {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-frequency = &lt;328000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi_clock: spi-clock {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-frequency = &lt;200000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nand_clock: nand-clock {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-frequency = &lt;400000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		emmc_clock: emmc-clock {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-frequency = &lt;400000000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx35xx-rd.dts b/arch/arm64/boot/dts/marvell/ac5-98dx35xx-rd.dts<br/>new file mode 100644<br/>index 000000000000..0c973d7a215a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/ac5-98dx35xx-rd.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/ac5-98dx35xx-rd.dts</a></div><div class='hunk'>@@ -0,0 +1,105 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Device Tree For RD-AC5X.</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) 2021 Marvell</div><div class='add'>+ * Copyright (C) 2022 Allied Telesis Labs</div><div class='add'>+ */</div><div class='add'>+/*</div><div class='add'>+ * Device Tree file for Marvell Alleycat 5X development board</div><div class='add'>+ * This board file supports the B configuration of the board</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "ac5-98dx35xx.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Marvell RD-AC5X Board";</div><div class='add'>+	compatible = "marvell,rd-ac5x", "marvell,ac5x", "marvell,ac5";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+		spiflash0 = &amp;spiflash0;</div><div class='add'>+		gpio0 = &amp;gpio0;</div><div class='add'>+		gpio1 = &amp;gpio1;</div><div class='add'>+		ethernet0 = &amp;eth0;</div><div class='add'>+		ethernet1 = &amp;eth1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x2 0x00000000 0x0 0x40000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb1phy: usb-phy {</div><div class='add'>+		compatible = "usb-nop-xceiv";</div><div class='add'>+		#phy-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdio {</div><div class='add'>+	phy0: ethernet-phy@0 {</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eth0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	phy-handle = &lt;&amp;phy0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB0 is a host USB */</div><div class='add'>+&amp;usb0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB1 is a peripheral USB */</div><div class='add'>+&amp;usb1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	phys = &lt;&amp;usb1phy&gt;;</div><div class='add'>+	phy-names = "usb-phy";</div><div class='add'>+	dr_mode = "peripheral";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	spiflash0: flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		spi-max-frequency = &lt;50000000&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;1&gt;; /* 1-single, 2-dual, 4-quad */</div><div class='add'>+		spi-rx-bus-width = &lt;1&gt;; /* 1-single, 2-dual, 4-quad */</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		partition@0 {</div><div class='add'>+			label = "spi_flash_part0";</div><div class='add'>+			reg = &lt;0x0 0x800000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		parition@1 {</div><div class='add'>+			label = "spi_flash_part1";</div><div class='add'>+			reg = &lt;0x800000 0x700000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		parition@2 {</div><div class='add'>+			label = "spi_flash_part2";</div><div class='add'>+			reg = &lt;0xF00000 0x100000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sdhci {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx35xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx35xx.dtsi<br/>new file mode 100644<br/>index 000000000000..2ab72f854bea<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/ac5-98dx35xx.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/ac5-98dx35xx.dtsi</a></div><div class='hunk'>@@ -0,0 +1,17 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Device Tree For AC5X.</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) 2022 Allied Telesis Labs</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "ac5-98dx25xx.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Marvell AC5X SoC";</div><div class='add'>+	compatible = "marvell,ac5x", "marvell,ac5";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cnm_clock {</div><div class='add'>+	clock-frequency = &lt;325000000&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/ac5x-rd-carrier-cn9131.dts b/arch/arm64/boot/dts/marvell/ac5x-rd-carrier-cn9131.dts<br/>new file mode 100644<br/>index 000000000000..2a0b07000089<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/ac5x-rd-carrier-cn9131.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/ac5x-rd-carrier-cn9131.dts</a></div><div class='hunk'>@@ -0,0 +1,44 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2023 Marvell International Ltd.</div><div class='add'>+ *</div><div class='add'>+ * Device tree for the AC5X RD Type 7 Com Express carrier board,</div><div class='add'>+ * Utilizing the CN913x COM Express CPU module board.</div><div class='add'>+ * This specific carrier board in this mode of operation (external)</div><div class='add'>+ * only maintains a PCIe link with the CPU module,</div><div class='add'>+ * which does not require any special DTS definitions.</div><div class='add'>+ *</div><div class='add'>+ * AC5X RD works here in external mode (switch selectable at the back of the</div><div class='add'>+ * board), and connect via an external cable a kit</div><div class='add'>+ * which would allow it to use an external CN9131 CPU COM Express module,</div><div class='add'>+ * mounted on top of an interposer kit.</div><div class='add'>+ *</div><div class='add'>+ * So in this case, once the switch is set to external mode as explained above,</div><div class='add'>+ * the AC5X RD becomes part of the carrier solution.</div><div class='add'>+ *</div><div class='add'>+ * When the board boots in the external CPU mode, the internal CPU is disabled,</div><div class='add'>+ * and only the switch portion of the SOC acts as a PCIe end-point, Hence there</div><div class='add'>+ * is no need to describe this internal (disabled CPU) in the device tree.</div><div class='add'>+ *</div><div class='add'>+ * There is no CPU booting in this mode on the carrier, only on the</div><div class='add'>+ * CN9131 COM Express CPU module.</div><div class='add'>+ * What runs the Linux is the CN9131 on the COM Express CPU module,</div><div class='add'>+ * And it accesses the switch end-point on the AC5X RD portion of the carrier</div><div class='add'>+ * via PCIe.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "cn9131-db-comexpress.dtsi"</div><div class='add'>+#include "ac5x-rd-carrier.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Marvell Armada AC5X RD COM EXPRESS type 7 carrier board with CN9131 CPU module";</div><div class='add'>+	compatible = "marvell,cn9131-ac5x-carrier", "marvell,rd-ac5x-carrier",</div><div class='add'>+			"marvell,cn9131-cpu-module", "marvell,cn9131",</div><div class='add'>+			"marvell,armada-ap807-quad", "marvell,armada-ap807";</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x0 0x2 0x00000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/ac5x-rd-carrier.dtsi b/arch/arm64/boot/dts/marvell/ac5x-rd-carrier.dtsi<br/>new file mode 100644<br/>index 000000000000..f98629abb58b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/ac5x-rd-carrier.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/ac5x-rd-carrier.dtsi</a></div><div class='hunk'>@@ -0,0 +1,34 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2023 Marvell International Ltd.</div><div class='add'>+ *</div><div class='add'>+ * Device tree for the AC5X RD Type 7 Com Express carrier board,</div><div class='add'>+ * This specific board in external mode (see below) only maintains</div><div class='add'>+ * a PCIe link with the COM Express CPU module, which does not</div><div class='add'>+ * require any special DTS definitions.</div><div class='add'>+ *</div><div class='add'>+ * AC5X RD can either work as you would expect, as a complete standalone</div><div class='add'>+ * box using the internal CPU, or you can move the switch on the back of</div><div class='add'>+ * the box to "external" mode, and connect via an external cable a kit</div><div class='add'>+ * which would allow it to use an external CPU COM Express module,</div><div class='add'>+ * mounted on top of an interposer kit.</div><div class='add'>+ *</div><div class='add'>+ * So in this case, once the switch is set to external mode as explained above,</div><div class='add'>+ * the AC5X RD becomes part of the carrier solution.</div><div class='add'>+ * This is a development/reference solution, not a full commercial solution,</div><div class='add'>+ * hence it was designed with the flexibility to be configured in different</div><div class='add'>+ * modes of operation.</div><div class='add'>+ *</div><div class='add'>+ * When the board boots in the external CPU mode, the internal CPU is disabled,</div><div class='add'>+ * and only the switch portion of the SOC acts as a PCIe end-point, Hence there</div><div class='add'>+ * is no need to describe this internal (disabled CPU) in the device tree.</div><div class='add'>+ *</div><div class='add'>+ * There is no CPU booting in this mode on the carrier,</div><div class='add'>+ * only on the COM Express CPU module.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Marvell Armada AC5X RD COM EXPRESS type 7 carrier board";</div><div class='add'>+	compatible = "marvell,rd-ac5x-carrier";</div><div class='add'>+</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/armada-371x.dtsi b/arch/arm64/boot/dts/marvell/armada-371x.dtsi<br/>deleted file mode 100644<br/>index dc1182ec9fa1..000000000000<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-371x.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-371x.dtsi</a><br/>+++ /dev/null</div><div class='hunk'>@@ -1,17 +0,0 @@</div><div class='del'>-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='del'>-/*</div><div class='del'>- * Device Tree Include file for Marvell Armada 371x family of SoCs</div><div class='del'>- * (also named 88F3710)</div><div class='del'>- *</div><div class='del'>- * Copyright (C) 2016 Marvell</div><div class='del'>- *</div><div class='del'>- * Gregory CLEMENT &lt;gregory.clement@free-electrons.com&gt;</div><div class='del'>- *</div><div class='del'>- */</div><div class='del'>-</div><div class='del'>-#include "armada-37xx.dtsi"</div><div class='del'>-</div><div class='del'>-/ {</div><div class='del'>-	model = "Marvell Armada 3710 SoC";</div><div class='del'>-	compatible = "marvell,armada3710", "marvell,armada3700";</div><div class='del'>-};</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/armada-3720-atlas-v5.dts b/arch/arm64/boot/dts/marvell/armada-3720-atlas-v5.dts<br/>new file mode 100644<br/>index 000000000000..070d10a705bb<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-3720-atlas-v5.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/armada-3720-atlas-v5.dts</a></div><div class='hunk'>@@ -0,0 +1,110 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Device Tree file for RIPE Atlas Probe v5</div><div class='add'>+ * 2025 by Marek Behún &lt;kabel@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/bus/moxtet.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include "armada-372x.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "RIPE Atlas Probe v5";</div><div class='add'>+	compatible = "ripe,atlas-v5", "marvell,armada3720",</div><div class='add'>+		     "marvell,armada3710";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;eth0;</div><div class='add'>+		mmc0 = &amp;sdhci0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x00000000 0x00000000 0x00000000 0x20000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led {</div><div class='add'>+			gpios = &lt;&amp;gpiosb 21 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			function = LED_FUNCTION_ACTIVITY;</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			linux,default-trigger = "default-on";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vsdc_reg: vsdc-reg {</div><div class='add'>+		compatible = "regulator-gpio";</div><div class='add'>+		regulator-name = "vsdc";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+</div><div class='add'>+		gpios = &lt;&amp;gpiosb 23 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		gpios-states = &lt;0&gt;;</div><div class='add'>+		states = &lt;1800000 0x1</div><div class='add'>+			  3300000 0x0&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	firmware {</div><div class='add'>+		armada-3700-rwtm {</div><div class='add'>+			compatible = "marvell,armada-3700-rwtm-firmware", "cznic,turris-mox-rwtm";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart1_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eth0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;rgmii_pins&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;phy1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sdhci0 {</div><div class='add'>+	non-removable;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	mmc-ddr-1_8v;</div><div class='add'>+	mmc-hs400-1_8v;</div><div class='add'>+	sd-uhs-sdr104;</div><div class='add'>+	marvell,xenon-emmc;</div><div class='add'>+	marvell,xenon-tun-count = &lt;9&gt;;</div><div class='add'>+	marvell,pad-type = "fixed-1-8v";</div><div class='add'>+	vqmmc-supply = &lt;&amp;vsdc_reg&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	mmccard: mmccard@0 {</div><div class='add'>+		compatible = "mmc-card";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdio {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;smi_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	phy1: ethernet-phy@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts b/arch/arm64/boot/dts/marvell/armada-3720-db.dts<br/>index f2cc00594d64..bd4e61d5448e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-3720-db.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-3720-db.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-3720-db.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/armada-3720-db.dts</a></div><div class='hunk'>@@ -128,6 +128,9 @@</div><div class='ctx'> </div><div class='ctx'> /* CON15(V2.0)/CON17(V1.4) : PCIe / CON15(V2.0)/CON12(V1.4) :mini-PCIe */</div><div class='ctx'> &amp;pcie0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pcie_reset_pins &amp;pcie_clkreq_pins&gt;;</div><div class='add'>+	reset-gpios = &lt;&amp;gpiosb 3 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -161,7 +164,7 @@</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;spi_quad_pins&gt;;</div><div class='ctx'> </div><div class='del'>-	m25p80@0 {</div><div class='add'>+	flash@0 {</div><div class='ctx'> 		compatible = "jedec,spi-nor";</div><div class='ctx'> 		reg = &lt;0&gt;;</div><div class='ctx'> 		spi-max-frequency = &lt;108000000&gt;;</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/armada-3720-eDPU.dts b/arch/arm64/boot/dts/marvell/armada-3720-eDPU.dts<br/>new file mode 100644<br/>index 000000000000..91c2f8b4edfa<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-3720-eDPU.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/armada-3720-eDPU.dts</a></div><div class='hunk'>@@ -0,0 +1,59 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "armada-3720-uDPU.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Methode eDPU Board";</div><div class='add'>+	compatible = "methode,edpu", "marvell,armada3720", "marvell,armada3710";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eth0 {</div><div class='add'>+	phy-mode = "2500base-x";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * External MV88E6361 switch is only available on v2 of the board.</div><div class='add'>+ * U-Boot will enable the MDIO bus and switch nodes.</div><div class='add'>+ */</div><div class='add'>+&amp;mdio {</div><div class='add'>+	status = "disabled";</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;smi_pins&gt;;</div><div class='add'>+</div><div class='add'>+	/* Actual device is MV88E6361 */</div><div class='add'>+	switch: switch@0 {</div><div class='add'>+		compatible = "marvell,mv88e6190";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				label = "cpu";</div><div class='add'>+				phy-mode = "2500base-x";</div><div class='add'>+				managed = "in-band-status";</div><div class='add'>+				ethernet = &lt;&amp;eth0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@9 {</div><div class='add'>+				reg = &lt;9&gt;;</div><div class='add'>+				label = "downlink";</div><div class='add'>+				phy-mode = "2500base-x";</div><div class='add'>+				managed = "in-band-status";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@a {</div><div class='add'>+				reg = &lt;10&gt;;</div><div class='add'>+				label = "uplink";</div><div class='add'>+				phy-mode = "2500base-x";</div><div class='add'>+				managed = "in-band-status";</div><div class='add'>+				sfp = &lt;&amp;sfp_eth1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-emmc.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-emmc.dts<br/>index ec72a11ed80f..5c4d8f379704 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-3720-espressobin-emmc.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-3720-espressobin-emmc.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-3720-espressobin-emmc.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/armada-3720-espressobin-emmc.dts</a></div><div class='hunk'>@@ -21,24 +21,6 @@</div><div class='ctx'> 		     "marvell,armada3720", "marvell,armada3710";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-/* U11 */</div><div class='ctx'> &amp;sdhci0 {</div><div class='del'>-	non-removable;</div><div class='del'>-	bus-width = &lt;8&gt;;</div><div class='del'>-	mmc-ddr-1_8v;</div><div class='del'>-	mmc-hs400-1_8v;</div><div class='del'>-	marvell,xenon-emmc;</div><div class='del'>-	marvell,xenon-tun-count = &lt;9&gt;;</div><div class='del'>-	marvell,pad-type = "fixed-1-8v";</div><div class='del'>-</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-	pinctrl-0 = &lt;&amp;mmc_pins&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='del'>-</div><div class='del'>-	#address-cells = &lt;1&gt;;</div><div class='del'>-	#size-cells = &lt;0&gt;;</div><div class='del'>-	mmccard: mmccard@0 {</div><div class='del'>-		compatible = "mmc-card";</div><div class='del'>-		reg = &lt;0&gt;;</div><div class='del'>-	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts<br/>new file mode 100644<br/>index 000000000000..97a180c8dcd9<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts</a></div><div class='hunk'>@@ -0,0 +1,197 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Device Tree file for ESPRESSObin-Ultra board.</div><div class='add'>+ * Copyright (C) 2019 Globalscale technologies, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Jason Hung &lt;jhung@globalscaletechnologies.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "armada-3720-espressobin.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Globalscale Marvell ESPRESSOBin Ultra Board";</div><div class='add'>+	compatible = "globalscale,espressobin-ultra", "globalscale,espressobin",</div><div class='add'>+		     "marvell,armada3720", "marvell,armada3710";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		/* ethernet1 is WAN port */</div><div class='add'>+		ethernet1 = &amp;switch0port5;</div><div class='add'>+		ethernet2 = &amp;switch0port1;</div><div class='add'>+		ethernet3 = &amp;switch0port2;</div><div class='add'>+		ethernet4 = &amp;switch0port3;</div><div class='add'>+		ethernet5 = &amp;switch0port4;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/delete-node/ regulator;</div><div class='add'>+</div><div class='add'>+	reg_usb3_vbus: usb3-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "usb3-vbus";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;gpionb 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb3_phy: usb3-phy {</div><div class='add'>+		compatible = "usb-nop-xceiv";</div><div class='add'>+		vcc-supply = &lt;&amp;reg_usb3_vbus&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-leds {</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		/* No assigned functions to the LEDs by default */</div><div class='add'>+		led1 {</div><div class='add'>+			label = "ebin-ultra:blue:led1";</div><div class='add'>+			gpios = &lt;&amp;gpionb 11 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+		led2 {</div><div class='add'>+			label = "ebin-ultra:green:led2";</div><div class='add'>+			gpios = &lt;&amp;gpionb 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+		led3 {</div><div class='add'>+			label = "ebin-ultra:red:led3";</div><div class='add'>+			gpios = &lt;&amp;gpionb 13 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+		led4 {</div><div class='add'>+			label = "ebin-ultra:yellow:led4";</div><div class='add'>+			gpios = &lt;&amp;gpionb 14 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sdhci0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sdhci1 {</div><div class='add'>+	/delete-property/ vqmmc-supply;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi0 {</div><div class='add'>+	flash@0 {</div><div class='add'>+		partitions {</div><div class='add'>+			compatible = "fixed-partitions";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			partition@0 {</div><div class='add'>+				label = "firmware";</div><div class='add'>+				reg = &lt;0x0 0x3e0000&gt;;</div><div class='add'>+			};</div><div class='add'>+			partition@3e0000 {</div><div class='add'>+				label = "hw-info";</div><div class='add'>+				reg = &lt;0x3e0000 0x10000&gt;;</div><div class='add'>+				read-only;</div><div class='add'>+			};</div><div class='add'>+			partition@3f0000 {</div><div class='add'>+				label = "u-boot-env";</div><div class='add'>+				reg = &lt;0x3f0000 0x10000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c1_pins&gt;;</div><div class='add'>+</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+</div><div class='add'>+	rtc@51 {</div><div class='add'>+		compatible = "nxp,pcf8563";</div><div class='add'>+		reg = &lt;0x51&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3 {</div><div class='add'>+	usb-phy = &lt;&amp;usb3_phy&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdio {</div><div class='add'>+	/* Switch is @3, not @1 */</div><div class='add'>+	/delete-node/ ethernet-switch@1;</div><div class='add'>+	extphy: ethernet-phy@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		reset-gpios = &lt;&amp;gpionb 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	switch0: ethernet-switch@3 {</div><div class='add'>+		compatible = "marvell,mv88e6085";</div><div class='add'>+		reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+		reset-gpios = &lt;&amp;gpiosb 23 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		dsa,member = &lt;0 0&gt;;</div><div class='add'>+</div><div class='add'>+		ethernet-ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			switch0port0: ethernet-port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				label = "cpu";</div><div class='add'>+				ethernet = &lt;&amp;eth0&gt;;</div><div class='add'>+				phy-mode = "rgmii-id";</div><div class='add'>+				fixed-link {</div><div class='add'>+					speed = &lt;1000&gt;;</div><div class='add'>+					full-duplex;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			switch0port1: ethernet-port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				label = "lan0";</div><div class='add'>+				phy-handle = &lt;&amp;switch0phy0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			switch0port2: ethernet-port@2 {</div><div class='add'>+				reg = &lt;2&gt;;</div><div class='add'>+				label = "lan1";</div><div class='add'>+				phy-handle = &lt;&amp;switch0phy1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			switch0port3: ethernet-port@3 {</div><div class='add'>+				reg = &lt;3&gt;;</div><div class='add'>+				label = "lan2";</div><div class='add'>+				phy-handle = &lt;&amp;switch0phy2&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			switch0port4: ethernet-port@4 {</div><div class='add'>+				reg = &lt;4&gt;;</div><div class='add'>+				label = "lan3";</div><div class='add'>+				phy-handle = &lt;&amp;switch0phy3&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			switch0port5: ethernet-port@5 {</div><div class='add'>+				reg = &lt;5&gt;;</div><div class='add'>+				label = "wan";</div><div class='add'>+				phy-handle = &lt;&amp;extphy&gt;;</div><div class='add'>+				phy-mode = "sgmii";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			switch0phy0: ethernet-phy@11 {</div><div class='add'>+				reg = &lt;0x11&gt;;</div><div class='add'>+			};</div><div class='add'>+			switch0phy1: ethernet-phy@12 {</div><div class='add'>+				reg = &lt;0x12&gt;;</div><div class='add'>+			};</div><div class='add'>+			switch0phy2: ethernet-phy@13 {</div><div class='add'>+				reg = &lt;0x13&gt;;</div><div class='add'>+			};</div><div class='add'>+			switch0phy3: ethernet-phy@14 {</div><div class='add'>+				reg = &lt;0x14&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts<br/>index 03733fd92732..75401eab4d42 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts</a></div><div class='hunk'>@@ -8,7 +8,7 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> /*</div><div class='del'>- * Schematic available at http://wiki.espressobin.net/tiki-download_file.php?fileId=200</div><div class='add'>+ * Schematic available at http://espressobin.net/wp-content/uploads/2020/05/ESPRESSObin_V7-0_Schematic.pdf</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> /dts-v1/;</div><div class='hunk'>@@ -20,42 +20,26 @@</div><div class='ctx'> 	compatible = "globalscale,espressobin-v7-emmc", "globalscale,espressobin-v7",</div><div class='ctx'> 		     "globalscale,espressobin", "marvell,armada3720",</div><div class='ctx'> 		     "marvell,armada3710";</div><div class='del'>-};</div><div class='ctx'> </div><div class='del'>-&amp;switch0 {</div><div class='del'>-	ports {</div><div class='del'>-		port@1 {</div><div class='del'>-			reg = &lt;1&gt;;</div><div class='del'>-			label = "lan1";</div><div class='del'>-			phy-handle = &lt;&amp;switch0phy0&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		port@3 {</div><div class='del'>-			reg = &lt;3&gt;;</div><div class='del'>-			label = "wan";</div><div class='del'>-			phy-handle = &lt;&amp;switch0phy2&gt;;</div><div class='del'>-		};</div><div class='add'>+	aliases {</div><div class='add'>+		/* ethernet1 is wan port */</div><div class='add'>+		ethernet1 = &amp;switch0port3;</div><div class='add'>+		ethernet3 = &amp;switch0port1;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-/* U11 */</div><div class='add'>+&amp;switch0port1 {</div><div class='add'>+	label = "lan1";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;switch0port3 {</div><div class='add'>+	label = "wan";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;sdhci0 {</div><div class='del'>-	non-removable;</div><div class='del'>-	bus-width = &lt;8&gt;;</div><div class='del'>-	mmc-ddr-1_8v;</div><div class='del'>-	mmc-hs400-1_8v;</div><div class='del'>-	marvell,xenon-emmc;</div><div class='del'>-	marvell,xenon-tun-count = &lt;9&gt;;</div><div class='del'>-	marvell,pad-type = "fixed-1-8v";</div><div class='del'>-</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-	pinctrl-0 = &lt;&amp;mmc_pins&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='add'>+};</div><div class='ctx'> </div><div class='del'>-	#address-cells = &lt;1&gt;;</div><div class='del'>-	#size-cells = &lt;0&gt;;</div><div class='del'>-	mmccard: mmccard@0 {</div><div class='del'>-		compatible = "mmc-card";</div><div class='del'>-		reg = &lt;0&gt;;</div><div class='del'>-	};</div><div class='add'>+&amp;led2 {</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts<br/>index 8570c5f47d7d..48a7f50fb427 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts</a></div><div class='hunk'>@@ -8,7 +8,7 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> /*</div><div class='del'>- * Schematic available at http://wiki.espressobin.net/tiki-download_file.php?fileId=200</div><div class='add'>+ * Schematic available at http://espressobin.net/wp-content/uploads/2020/05/ESPRESSObin_V7-0_Schematic.pdf</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> /dts-v1/;</div><div class='hunk'>@@ -19,20 +19,22 @@</div><div class='ctx'> 	model = "Globalscale Marvell ESPRESSOBin Board V7";</div><div class='ctx'> 	compatible = "globalscale,espressobin-v7", "globalscale,espressobin",</div><div class='ctx'> 		     "marvell,armada3720", "marvell,armada3710";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		/* ethernet1 is wan port */</div><div class='add'>+		ethernet1 = &amp;switch0port3;</div><div class='add'>+		ethernet3 = &amp;switch0port1;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;switch0port1 {</div><div class='add'>+	label = "lan1";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;switch0 {</div><div class='del'>-	ports {</div><div class='del'>-		port@1 {</div><div class='del'>-			reg = &lt;1&gt;;</div><div class='del'>-			label = "lan1";</div><div class='del'>-			phy-handle = &lt;&amp;switch0phy0&gt;;</div><div class='del'>-		};</div><div class='add'>+&amp;switch0port3 {</div><div class='add'>+	label = "wan";</div><div class='add'>+};</div><div class='ctx'> </div><div class='del'>-		port@3 {</div><div class='del'>-			reg = &lt;3&gt;;</div><div class='del'>-			label = "wan";</div><div class='del'>-			phy-handle = &lt;&amp;switch0phy2&gt;;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='add'>+&amp;led2 {</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi<br/>index 42e992f9c8a5..fed2dcecb323 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi</a></div><div class='hunk'>@@ -13,8 +13,10 @@</div><div class='ctx'> / {</div><div class='ctx'> 	aliases {</div><div class='ctx'> 		ethernet0 = &amp;eth0;</div><div class='del'>-		serial0 = &amp;uart0;</div><div class='del'>-		serial1 = &amp;uart1;</div><div class='add'>+		/* for DSA user port device */</div><div class='add'>+		ethernet1 = &amp;switch0port1;</div><div class='add'>+		ethernet2 = &amp;switch0port2;</div><div class='add'>+		ethernet3 = &amp;switch0port3;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	chosen {</div><div class='hunk'>@@ -39,21 +41,56 @@</div><div class='ctx'> 			  3300000 0x0&gt;;</div><div class='ctx'> 		enable-active-high;</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	led2: gpio-led2 {</div><div class='add'>+		/* led2 is working only on v7 board */</div><div class='add'>+		status = "disabled";</div><div class='add'>+</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led2 {</div><div class='add'>+			label = "led2";</div><div class='add'>+			gpios = &lt;&amp;gpionb 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* J9 */</div><div class='ctx'> &amp;pcie0 {</div><div class='ctx'> 	status = "okay";</div><div class='del'>-	phys = &lt;&amp;comphy1 0&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pcie_reset_pins &amp;pcie_clkreq_pins&gt;;</div><div class='add'>+	reset-gpios = &lt;&amp;gpiosb 3 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* J6 */</div><div class='ctx'> &amp;sata {</div><div class='ctx'> 	status = "okay";</div><div class='del'>-	phys = &lt;&amp;comphy2 0&gt;;</div><div class='del'>-	phy-names = "sata-phy";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* U11 */</div><div class='add'>+&amp;sdhci0 {</div><div class='add'>+	/* Main DTS file for Espressobin is without eMMC */</div><div class='add'>+	status = "disabled";</div><div class='add'>+</div><div class='add'>+	non-removable;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	mmc-ddr-1_8v;</div><div class='add'>+	mmc-hs400-1_8v;</div><div class='add'>+	marvell,xenon-emmc;</div><div class='add'>+	marvell,xenon-tun-count = &lt;9&gt;;</div><div class='add'>+	marvell,pad-type = "fixed-1-8v";</div><div class='add'>+</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc_pins&gt;;</div><div class='add'>+</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	mmccard: mmccard@0 {</div><div class='add'>+		compatible = "mmc-card";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* J1 */</div><div class='hunk'>@@ -108,19 +145,17 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;mdio {</div><div class='del'>-	switch0: switch0@1 {</div><div class='add'>+	switch0: ethernet-switch@1 {</div><div class='ctx'> 		compatible = "marvell,mv88e6085";</div><div class='del'>-		#address-cells = &lt;1&gt;;</div><div class='del'>-		#size-cells = &lt;0&gt;;</div><div class='ctx'> 		reg = &lt;1&gt;;</div><div class='ctx'> </div><div class='ctx'> 		dsa,member = &lt;0 0&gt;;</div><div class='ctx'> </div><div class='del'>-		ports {</div><div class='add'>+		ethernet-ports {</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> </div><div class='del'>-			port@0 {</div><div class='add'>+			switch0port0: ethernet-port@0 {</div><div class='ctx'> 				reg = &lt;0&gt;;</div><div class='ctx'> 				label = "cpu";</div><div class='ctx'> 				ethernet = &lt;&amp;eth0&gt;;</div><div class='hunk'>@@ -131,19 +166,19 @@</div><div class='ctx'> 				};</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			port@1 {</div><div class='add'>+			switch0port1: ethernet-port@1 {</div><div class='ctx'> 				reg = &lt;1&gt;;</div><div class='ctx'> 				label = "wan";</div><div class='ctx'> 				phy-handle = &lt;&amp;switch0phy0&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			port@2 {</div><div class='add'>+			switch0port2: ethernet-port@2 {</div><div class='ctx'> 				reg = &lt;2&gt;;</div><div class='ctx'> 				label = "lan0";</div><div class='ctx'> 				phy-handle = &lt;&amp;switch0phy1&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			port@3 {</div><div class='add'>+			switch0port3: ethernet-port@3 {</div><div class='ctx'> 				reg = &lt;3&gt;;</div><div class='ctx'> 				label = "lan1";</div><div class='ctx'> 				phy-handle = &lt;&amp;switch0phy2&gt;;</div><div class='hunk'>@@ -155,13 +190,13 @@</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> </div><div class='del'>-			switch0phy0: switch0phy0@11 {</div><div class='add'>+			switch0phy0: ethernet-phy@11 {</div><div class='ctx'> 				reg = &lt;0x11&gt;;</div><div class='ctx'> 			};</div><div class='del'>-			switch0phy1: switch0phy1@12 {</div><div class='add'>+			switch0phy1: ethernet-phy@12 {</div><div class='ctx'> 				reg = &lt;0x12&gt;;</div><div class='ctx'> 			};</div><div class='del'>-			switch0phy2: switch0phy2@13 {</div><div class='add'>+			switch0phy2: ethernet-phy@13 {</div><div class='ctx'> 				reg = &lt;0x13&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts b/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts<br/>new file mode 100644<br/>index 000000000000..9f4bafeddd82<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts</a></div><div class='hunk'>@@ -0,0 +1,237 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include "armada-372x.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "GL.iNet GL-MV1000";</div><div class='add'>+	compatible = "glinet,gl-mv1000", "marvell,armada3720", "marvell,armada3710";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		led-boot = &amp;led_power;</div><div class='add'>+		led-failsafe = &amp;led_power;</div><div class='add'>+		led-running = &amp;led_power;</div><div class='add'>+		led-upgrade = &amp;led_power;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x00000000 0x00000000 0x00000000 0x20000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vcc_sd_reg1: regulator {</div><div class='add'>+		compatible = "regulator-gpio";</div><div class='add'>+		regulator-name = "vcc_sd1";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+</div><div class='add'>+		gpios-states = &lt;0&gt;;</div><div class='add'>+		states = &lt;1800000 0x1</div><div class='add'>+			3300000 0x0&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		button-reset {</div><div class='add'>+			label = "reset";</div><div class='add'>+			linux,code = &lt;KEY_RESTART&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpionb 14 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		switch {</div><div class='add'>+			label = "switch";</div><div class='add'>+			linux,code = &lt;BTN_0&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpiosb 22 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-vpn {</div><div class='add'>+			label = "green:vpn";</div><div class='add'>+			gpios = &lt;&amp;gpionb 11 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-wan {</div><div class='add'>+			label = "green:wan";</div><div class='add'>+			gpios = &lt;&amp;gpionb 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led_power: led-power {</div><div class='add'>+			label = "green:power";</div><div class='add'>+			gpios = &lt;&amp;gpionb 13 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "on";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash@0 {</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		spi-max-frequency = &lt;104000000&gt;;</div><div class='add'>+		m25p,fast-read;</div><div class='add'>+		partitions {</div><div class='add'>+			compatible = "fixed-partitions";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			partition@0 {</div><div class='add'>+				label = "firmware";</div><div class='add'>+				reg = &lt;0 0xf0000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			partition@f0000 {</div><div class='add'>+				label = "u-boot-env";</div><div class='add'>+				reg = &lt;0xf0000 0x8000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			factory: partition@f8000 {</div><div class='add'>+				label = "factory";</div><div class='add'>+				reg = &lt;0xf8000 0x8000&gt;;</div><div class='add'>+				read-only;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			partition@100000 {</div><div class='add'>+				label = "dtb";</div><div class='add'>+				reg = &lt;0x100000 0x10000&gt;;</div><div class='add'>+				read-only;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			partition@110000 {</div><div class='add'>+				label = "rescue";</div><div class='add'>+				reg = &lt;0x110000 0x1000000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sdhci1 {</div><div class='add'>+	wp-inverted;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpionb 17 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	marvell,pad-type = "sd";</div><div class='add'>+	no-1-8-v;</div><div class='add'>+	vqmmc-supply = &lt;&amp;vcc_sd_reg1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sdhci0 {</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	mmc-ddr-1_8v;</div><div class='add'>+	mmc-hs400-1_8v;</div><div class='add'>+	non-removable;</div><div class='add'>+	no-sd;</div><div class='add'>+	no-sdio;</div><div class='add'>+	marvell,pad-type = "fixed-1-8v";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdio {</div><div class='add'>+	switch0: ethernet-switch@1 {</div><div class='add'>+		compatible = "marvell,mv88e6085";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		dsa,member = &lt;0 0&gt;;</div><div class='add'>+</div><div class='add'>+		ports: ethernet-ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			ethernet-port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				label = "cpu";</div><div class='add'>+				ethernet = &lt;&amp;eth0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ethernet-port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				label = "wan";</div><div class='add'>+				phy-handle = &lt;&amp;switch0phy0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ethernet-port@2 {</div><div class='add'>+				reg = &lt;2&gt;;</div><div class='add'>+				label = "lan0";</div><div class='add'>+				phy-handle = &lt;&amp;switch0phy1&gt;;</div><div class='add'>+</div><div class='add'>+				nvmem-cells = &lt;&amp;macaddr_factory_6&gt;;</div><div class='add'>+				nvmem-cell-names = "mac-address";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ethernet-port@3 {</div><div class='add'>+				reg = &lt;3&gt;;</div><div class='add'>+				label = "lan1";</div><div class='add'>+				phy-handle = &lt;&amp;switch0phy2&gt;;</div><div class='add'>+</div><div class='add'>+				nvmem-cells = &lt;&amp;macaddr_factory_6&gt;;</div><div class='add'>+				nvmem-cell-names = "mac-address";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			switch0phy0: ethernet-phy@11 {</div><div class='add'>+				reg = &lt;0x11&gt;;</div><div class='add'>+			};</div><div class='add'>+			switch0phy1: ethernet-phy@12 {</div><div class='add'>+				reg = &lt;0x12&gt;;</div><div class='add'>+			};</div><div class='add'>+			switch0phy2: ethernet-phy@13 {</div><div class='add'>+				reg = &lt;0x13&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eth0 {</div><div class='add'>+	nvmem-cells = &lt;&amp;macaddr_factory_0&gt;;</div><div class='add'>+	nvmem-cell-names = "mac-address";</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	fixed-link {</div><div class='add'>+		speed = &lt;1000&gt;;</div><div class='add'>+		full-duplex;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;factory {</div><div class='add'>+	compatible = "nvmem-cells";</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+	macaddr_factory_0: macaddr@0 {</div><div class='add'>+		reg = &lt;0x0 0x6&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	macaddr_factory_6: macaddr@6 {</div><div class='add'>+		reg = &lt;0x6 0x6&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts<br/>index bb42d1e6a4e9..f4d73c8b1a6d 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='ctx'> /*</div><div class='ctx'>  * Device Tree file for CZ.NIC Turris Mox Board</div><div class='del'>- * 2019 by Marek Behun &lt;marek.behun@nic.cz&gt;</div><div class='add'>+ * 2019 by Marek Behún &lt;kabel@kernel.org&gt;</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> /dts-v1/;</div><div class='hunk'>@@ -18,7 +18,10 @@</div><div class='ctx'> </div><div class='ctx'> 	aliases {</div><div class='ctx'> 		spi0 = &amp;spi0;</div><div class='add'>+		ethernet0 = &amp;eth0;</div><div class='ctx'> 		ethernet1 = &amp;eth1;</div><div class='add'>+		mmc0 = &amp;sdhci0;</div><div class='add'>+		mmc1 = &amp;sdhci1;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	chosen {</div><div class='hunk'>@@ -32,7 +35,7 @@</div><div class='ctx'> </div><div class='ctx'> 	leds {</div><div class='ctx'> 		compatible = "gpio-leds";</div><div class='del'>-		red {</div><div class='add'>+		led {</div><div class='ctx'> 			label = "mox:red:activity";</div><div class='ctx'> 			gpios = &lt;&amp;gpiosb 21 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 			linux,default-trigger = "default-on";</div><div class='hunk'>@@ -42,7 +45,7 @@</div><div class='ctx'> 	gpio-keys {</div><div class='ctx'> 		compatible = "gpio-keys";</div><div class='ctx'> </div><div class='del'>-		reset {</div><div class='add'>+		key-reset {</div><div class='ctx'> 			label = "reset";</div><div class='ctx'> 			linux,code = &lt;KEY_RESTART&gt;;</div><div class='ctx'> 			gpios = &lt;&amp;gpiosb 20 GPIO_ACTIVE_LOW&gt;;</div><div class='hunk'>@@ -95,23 +98,22 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	sfp: sfp {</div><div class='del'>-		compatible = "sff,sfp+";</div><div class='add'>+		compatible = "sff,sfp";</div><div class='ctx'> 		i2c-bus = &lt;&amp;i2c0&gt;;</div><div class='del'>-		los-gpio = &lt;&amp;moxtet_sfp 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-		tx-fault-gpio = &lt;&amp;moxtet_sfp 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-		mod-def0-gpio = &lt;&amp;moxtet_sfp 2 GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-		tx-disable-gpio = &lt;&amp;moxtet_sfp 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-		rate-select0-gpio = &lt;&amp;moxtet_sfp 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;moxtet_sfp 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;moxtet_sfp 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;moxtet_sfp 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;moxtet_sfp 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		rate-select0-gpios = &lt;&amp;moxtet_sfp 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		maximum-power-milliwatt = &lt;3000&gt;;</div><div class='ctx'> </div><div class='ctx'> 		/* enabled by U-Boot if SFP module is present */</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	firmware {</div><div class='del'>-		turris-mox-rwtm {</div><div class='del'>-			compatible = "cznic,turris-mox-rwtm";</div><div class='del'>-			mboxes = &lt;&amp;rwtm 0&gt;;</div><div class='del'>-			status = "okay";</div><div class='add'>+		armada-3700-rwtm {</div><div class='add'>+			compatible = "marvell,armada-3700-rwtm-firmware", "cznic,turris-mox-rwtm";</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='hunk'>@@ -120,25 +122,46 @@</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;i2c1_pins&gt;;</div><div class='ctx'> 	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	/delete-property/ mrvl,i2c-fast-mode;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='add'>+	/* MCP7940MT-I/MNY RTC */</div><div class='ctx'> 	rtc@6f {</div><div class='ctx'> 		compatible = "microchip,mcp7940x";</div><div class='ctx'> 		reg = &lt;0x6f&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpiosb&gt;;</div><div class='add'>+		interrupts = &lt;5 IRQ_TYPE_EDGE_FALLING&gt;; /* GPIO2_5 */</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;pcie_reset_pins {</div><div class='del'>-	function = "gpio";</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> &amp;pcie0 {</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pcie_reset_pins &amp;pcie_clkreq_pins&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='del'>-	max-link-speed = &lt;2&gt;;</div><div class='ctx'> 	reset-gpios = &lt;&amp;gpiosb 3 GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-	phys = &lt;&amp;comphy1 0&gt;;</div><div class='add'>+	slot-power-limit-milliwatt = &lt;10000&gt;;</div><div class='add'>+	/*</div><div class='add'>+	 * U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property</div><div class='add'>+	 * contains exactly 2 ranges with 3 (child) address cells, 2 (parent) address cells and</div><div class='add'>+	 * 2 size cells and also expects that the second range starts at 16 MB offset. Also it</div><div class='add'>+	 * expects that first range uses same address for PCI (child) and CPU (parent) cells (so</div><div class='add'>+	 * no remapping) and that this address is the lowest from all specified ranges. If these</div><div class='add'>+	 * conditions are not met then U-Boot crashes during loading kernel DTB file. PCIe address</div><div class='add'>+	 * space is 128 MB long, so the best split between MEM and IO is to use fixed 16 MB window</div><div class='add'>+	 * for IO and the rest 112 MB (64+32+16) for MEM, despite that maximal IO size is just 64 kB.</div><div class='add'>+	 * This bug is not present in U-Boot ports for other Armada 3700 devices and is fixed in</div><div class='add'>+	 * U-Boot version 2021.07. See relevant U-Boot commits (the last one contains fix):</div><div class='add'>+	 * https://source.denx.de/u-boot/u-boot/-/commit/cb2ddb291ee6fcbddd6d8f4ff49089dfe580f5d7</div><div class='add'>+	 * https://source.denx.de/u-boot/u-boot/-/commit/c64ac3b3185aeb3846297ad7391fc6df8ecd73bf</div><div class='add'>+	 * https://source.denx.de/u-boot/u-boot/-/commit/4a82fca8e330157081fc132a591ebd99ba02ee33</div><div class='add'>+	 * Bug related to requirement of same child and parent addresses for first range is fixed</div><div class='add'>+	 * in U-Boot version 2022.04 by following commit:</div><div class='add'>+	 * https://source.denx.de/u-boot/u-boot/-/commit/1fd54253bca7d43d046bba4853fe5fafd034bc17</div><div class='add'>+	 */</div><div class='add'>+	#address-cells = &lt;3&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+	ranges = &lt;0x81000000 0 0xe8000000   0 0xe8000000   0 0x01000000   /* Port 0 IO */</div><div class='add'>+		  0x82000000 0 0xe9000000   0 0xe9000000   0 0x07000000&gt;; /* Port 0 MEM */</div><div class='ctx'> </div><div class='ctx'> 	/* enabled by U-Boot if PCIe module is present */</div><div class='ctx'> 	status = "disabled";</div><div class='hunk'>@@ -152,7 +175,7 @@</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;rgmii_pins&gt;;</div><div class='ctx'> 	phy-mode = "rgmii-id";</div><div class='del'>-	phy = &lt;&amp;phy1&gt;;</div><div class='add'>+	phy-handle = &lt;&amp;phy1&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -179,6 +202,8 @@</div><div class='ctx'> 	marvell,pad-type = "sd";</div><div class='ctx'> 	vqmmc-supply = &lt;&amp;vsdio_reg&gt;;</div><div class='ctx'> 	mmc-pwrseq = &lt;&amp;sdhci1_pwrseq&gt;;</div><div class='add'>+	/* forbid SDR104 for FCC purposes */</div><div class='add'>+	sdhci-caps-mask = &lt;0x2 0x0&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -190,9 +215,7 @@</div><div class='ctx'> 	assigned-clock-parents = &lt;&amp;tbg 1&gt;;</div><div class='ctx'> 	assigned-clock-rates = &lt;20000000&gt;;</div><div class='ctx'> </div><div class='del'>-	spi-flash@0 {</div><div class='del'>-		#address-cells = &lt;1&gt;;</div><div class='del'>-		#size-cells = &lt;1&gt;;</div><div class='add'>+	flash@0 {</div><div class='ctx'> 		compatible = "jedec,spi-nor";</div><div class='ctx'> 		reg = &lt;0&gt;;</div><div class='ctx'> 		spi-max-frequency = &lt;20000000&gt;;</div><div class='hunk'>@@ -208,7 +231,7 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			partition@20000 {</div><div class='del'>-				label = "u-boot";</div><div class='add'>+				label = "a53-firmware";</div><div class='ctx'> 				reg = &lt;0x20000 0x160000&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -279,10 +302,16 @@</div><div class='ctx'> 		reg = &lt;1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	/* switch nodes are enabled by U-Boot if modules are present */</div><div class='add'>+	/*</div><div class='add'>+	 * NOTE: switch nodes are enabled by U-Boot if modules are present</div><div class='add'>+	 * DO NOT change this node name (switch0@10) even if it is not following</div><div class='add'>+	 * conventions! Deployed U-Boot binaries are explicitly looking for</div><div class='add'>+	 * this node in order to augment the device tree!</div><div class='add'>+	 * Also do not touch the "ports" or "port@n" nodes. These are also ABI.</div><div class='add'>+	 */</div><div class='ctx'> 	switch0@10 {</div><div class='del'>-		compatible = "marvell,mv88e6190";</div><div class='del'>-		reg = &lt;0x10 0&gt;;</div><div class='add'>+		compatible = "marvell,turris-mox-mv88e6190", "marvell,mv88e6190";</div><div class='add'>+		reg = &lt;0x10&gt;;</div><div class='ctx'> 		dsa,member = &lt;0 0&gt;;</div><div class='ctx'> 		interrupt-parent = &lt;&amp;moxtet&gt;;</div><div class='ctx'> 		interrupts = &lt;MOXTET_IRQ_PERIDOT(0)&gt;;</div><div class='hunk'>@@ -292,35 +321,35 @@</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> </div><div class='del'>-			switch0phy1: switch0phy1@1 {</div><div class='add'>+			switch0phy1: ethernet-phy@1 {</div><div class='ctx'> 				reg = &lt;0x1&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			switch0phy2: switch0phy2@2 {</div><div class='add'>+			switch0phy2: ethernet-phy@2 {</div><div class='ctx'> 				reg = &lt;0x2&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			switch0phy3: switch0phy3@3 {</div><div class='add'>+			switch0phy3: ethernet-phy@3 {</div><div class='ctx'> 				reg = &lt;0x3&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			switch0phy4: switch0phy4@4 {</div><div class='add'>+			switch0phy4: ethernet-phy@4 {</div><div class='ctx'> 				reg = &lt;0x4&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			switch0phy5: switch0phy5@5 {</div><div class='add'>+			switch0phy5: ethernet-phy@5 {</div><div class='ctx'> 				reg = &lt;0x5&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			switch0phy6: switch0phy6@6 {</div><div class='add'>+			switch0phy6: ethernet-phy@6 {</div><div class='ctx'> 				reg = &lt;0x6&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			switch0phy7: switch0phy7@7 {</div><div class='add'>+			switch0phy7: ethernet-phy@7 {</div><div class='ctx'> 				reg = &lt;0x7&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			switch0phy8: switch0phy8@8 {</div><div class='add'>+			switch0phy8: ethernet-phy@8 {</div><div class='ctx'> 				reg = &lt;0x8&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='hunk'>@@ -405,9 +434,10 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	/* NOTE: this node name is ABI, don't change it! */</div><div class='ctx'> 	switch0@2 {</div><div class='del'>-		compatible = "marvell,mv88e6085";</div><div class='del'>-		reg = &lt;0x2 0&gt;;</div><div class='add'>+		compatible = "marvell,turris-mox-mv88e6085", "marvell,mv88e6085";</div><div class='add'>+		reg = &lt;0x2&gt;;</div><div class='ctx'> 		dsa,member = &lt;0 0&gt;;</div><div class='ctx'> 		interrupt-parent = &lt;&amp;moxtet&gt;;</div><div class='ctx'> 		interrupts = &lt;MOXTET_IRQ_TOPAZ&gt;;</div><div class='hunk'>@@ -417,19 +447,19 @@</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> </div><div class='del'>-			switch0phy1_topaz: switch0phy1@11 {</div><div class='add'>+			switch0phy1_topaz: ethernet-phy@11 {</div><div class='ctx'> 				reg = &lt;0x11&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			switch0phy2_topaz: switch0phy2@12 {</div><div class='add'>+			switch0phy2_topaz: ethernet-phy@12 {</div><div class='ctx'> 				reg = &lt;0x12&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			switch0phy3_topaz: switch0phy3@13 {</div><div class='add'>+			switch0phy3_topaz: ethernet-phy@13 {</div><div class='ctx'> 				reg = &lt;0x13&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			switch0phy4_topaz: switch0phy4@14 {</div><div class='add'>+			switch0phy4_topaz: ethernet-phy@14 {</div><div class='ctx'> 				reg = &lt;0x14&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='hunk'>@@ -472,9 +502,10 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	/* NOTE: this node name is ABI, don't change it! */</div><div class='ctx'> 	switch1@11 {</div><div class='del'>-		compatible = "marvell,mv88e6190";</div><div class='del'>-		reg = &lt;0x11 0&gt;;</div><div class='add'>+		compatible = "marvell,turris-mox-mv88e6190", "marvell,mv88e6190";</div><div class='add'>+		reg = &lt;0x11&gt;;</div><div class='ctx'> 		dsa,member = &lt;0 1&gt;;</div><div class='ctx'> 		interrupt-parent = &lt;&amp;moxtet&gt;;</div><div class='ctx'> 		interrupts = &lt;MOXTET_IRQ_PERIDOT(1)&gt;;</div><div class='hunk'>@@ -484,35 +515,35 @@</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> </div><div class='del'>-			switch1phy1: switch1phy1@1 {</div><div class='add'>+			switch1phy1: ethernet-phy@1 {</div><div class='ctx'> 				reg = &lt;0x1&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			switch1phy2: switch1phy2@2 {</div><div class='add'>+			switch1phy2: ethernet-phy@2 {</div><div class='ctx'> 				reg = &lt;0x2&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			switch1phy3: switch1phy3@3 {</div><div class='add'>+			switch1phy3: ethernet-phy@3 {</div><div class='ctx'> 				reg = &lt;0x3&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			switch1phy4: switch1phy4@4 {</div><div class='add'>+			switch1phy4: ethernet-phy@4 {</div><div class='ctx'> 				reg = &lt;0x4&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			switch1phy5: switch1phy5@5 {</div><div class='add'>+			switch1phy5: ethernet-phy@5 {</div><div class='ctx'> 				reg = &lt;0x5&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			switch1phy6: switch1phy6@6 {</div><div class='add'>+			switch1phy6: ethernet-phy@6 {</div><div class='ctx'> 				reg = &lt;0x6&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			switch1phy7: switch1phy7@7 {</div><div class='add'>+			switch1phy7: ethernet-phy@7 {</div><div class='ctx'> 				reg = &lt;0x7&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			switch1phy8: switch1phy8@8 {</div><div class='add'>+			switch1phy8: ethernet-phy@8 {</div><div class='ctx'> 				reg = &lt;0x8&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='hunk'>@@ -597,9 +628,10 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	/* NOTE: this node name is ABI, don't change it! */</div><div class='ctx'> 	switch1@2 {</div><div class='del'>-		compatible = "marvell,mv88e6085";</div><div class='del'>-		reg = &lt;0x2 0&gt;;</div><div class='add'>+		compatible = "marvell,turris-mox-mv88e6085", "marvell,mv88e6085";</div><div class='add'>+		reg = &lt;0x2&gt;;</div><div class='ctx'> 		dsa,member = &lt;0 1&gt;;</div><div class='ctx'> 		interrupt-parent = &lt;&amp;moxtet&gt;;</div><div class='ctx'> 		interrupts = &lt;MOXTET_IRQ_TOPAZ&gt;;</div><div class='hunk'>@@ -609,19 +641,19 @@</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> </div><div class='del'>-			switch1phy1_topaz: switch1phy1@11 {</div><div class='add'>+			switch1phy1_topaz: ethernet-phy@11 {</div><div class='ctx'> 				reg = &lt;0x11&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			switch1phy2_topaz: switch1phy2@12 {</div><div class='add'>+			switch1phy2_topaz: ethernet-phy@12 {</div><div class='ctx'> 				reg = &lt;0x12&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			switch1phy3_topaz: switch1phy3@13 {</div><div class='add'>+			switch1phy3_topaz: ethernet-phy@13 {</div><div class='ctx'> 				reg = &lt;0x13&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			switch1phy4_topaz: switch1phy4@14 {</div><div class='add'>+			switch1phy4_topaz: ethernet-phy@14 {</div><div class='ctx'> 				reg = &lt;0x14&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='hunk'>@@ -664,9 +696,10 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	/* NOTE: this node name is ABI, don't change it! */</div><div class='ctx'> 	switch2@12 {</div><div class='del'>-		compatible = "marvell,mv88e6190";</div><div class='del'>-		reg = &lt;0x12 0&gt;;</div><div class='add'>+		compatible = "marvell,turris-mox-mv88e6190", "marvell,mv88e6190";</div><div class='add'>+		reg = &lt;0x12&gt;;</div><div class='ctx'> 		dsa,member = &lt;0 2&gt;;</div><div class='ctx'> 		interrupt-parent = &lt;&amp;moxtet&gt;;</div><div class='ctx'> 		interrupts = &lt;MOXTET_IRQ_PERIDOT(2)&gt;;</div><div class='hunk'>@@ -676,35 +709,35 @@</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> </div><div class='del'>-			switch2phy1: switch2phy1@1 {</div><div class='add'>+			switch2phy1: ethernet-phy@1 {</div><div class='ctx'> 				reg = &lt;0x1&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			switch2phy2: switch2phy2@2 {</div><div class='add'>+			switch2phy2: ethernet-phy@2 {</div><div class='ctx'> 				reg = &lt;0x2&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			switch2phy3: switch2phy3@3 {</div><div class='add'>+			switch2phy3: ethernet-phy@3 {</div><div class='ctx'> 				reg = &lt;0x3&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			switch2phy4: switch2phy4@4 {</div><div class='add'>+			switch2phy4: ethernet-phy@4 {</div><div class='ctx'> 				reg = &lt;0x4&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			switch2phy5: switch2phy5@5 {</div><div class='add'>+			switch2phy5: ethernet-phy@5 {</div><div class='ctx'> 				reg = &lt;0x5&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			switch2phy6: switch2phy6@6 {</div><div class='add'>+			switch2phy6: ethernet-phy@6 {</div><div class='ctx'> 				reg = &lt;0x6&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			switch2phy7: switch2phy7@7 {</div><div class='add'>+			switch2phy7: ethernet-phy@7 {</div><div class='ctx'> 				reg = &lt;0x7&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			switch2phy8: switch2phy8@8 {</div><div class='add'>+			switch2phy8: ethernet-phy@8 {</div><div class='ctx'> 				reg = &lt;0x8&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='hunk'>@@ -780,9 +813,10 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	/* NOTE: this node name is ABI, don't change it! */</div><div class='ctx'> 	switch2@2 {</div><div class='del'>-		compatible = "marvell,mv88e6085";</div><div class='del'>-		reg = &lt;0x2 0&gt;;</div><div class='add'>+		compatible = "marvell,turris-mox-mv88e6085", "marvell,mv88e6085";</div><div class='add'>+		reg = &lt;0x2&gt;;</div><div class='ctx'> 		dsa,member = &lt;0 2&gt;;</div><div class='ctx'> 		interrupt-parent = &lt;&amp;moxtet&gt;;</div><div class='ctx'> 		interrupts = &lt;MOXTET_IRQ_TOPAZ&gt;;</div><div class='hunk'>@@ -792,19 +826,19 @@</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> </div><div class='del'>-			switch2phy1_topaz: switch2phy1@11 {</div><div class='add'>+			switch2phy1_topaz: ethernet-phy@11 {</div><div class='ctx'> 				reg = &lt;0x11&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			switch2phy2_topaz: switch2phy2@12 {</div><div class='add'>+			switch2phy2_topaz: ethernet-phy@12 {</div><div class='ctx'> 				reg = &lt;0x12&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			switch2phy3_topaz: switch2phy3@13 {</div><div class='add'>+			switch2phy3_topaz: ethernet-phy@13 {</div><div class='ctx'> 				reg = &lt;0x13&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			switch2phy4_topaz: switch2phy4@14 {</div><div class='add'>+			switch2phy4_topaz: ethernet-phy@14 {</div><div class='ctx'> 				reg = &lt;0x14&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts b/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts<br/>index 7eb6c1796cef..c76eceabd33e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts</a></div><div class='hunk'>@@ -1,170 +1,42 @@</div><div class='ctx'> // SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='del'>-/*</div><div class='del'>- * Device tree for the uDPU board.</div><div class='del'>- * Based on Marvell Armada 3720 development board (DB-88F3720-DDR3)</div><div class='del'>- * Copyright (C) 2016 Marvell</div><div class='del'>- * Copyright (C) 2019 Methode Electronics</div><div class='del'>- * Copyright (C) 2019 Telus</div><div class='del'>- *</div><div class='del'>- * Vladimir Vid &lt;vladimir.vid@sartura.hr&gt;</div><div class='del'>- */</div><div class='ctx'> </div><div class='ctx'> /dts-v1/;</div><div class='ctx'> </div><div class='del'>-#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='del'>-#include "armada-372x.dtsi"</div><div class='add'>+#include "armada-3720-uDPU.dtsi"</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	model = "Methode uDPU Board";</div><div class='del'>-	compatible = "methode,udpu", "marvell,armada3720";</div><div class='del'>-</div><div class='del'>-	chosen {</div><div class='del'>-		stdout-path = "serial0:115200n8";</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	memory@0 {</div><div class='del'>-		device_type = "memory";</div><div class='del'>-		reg = &lt;0x00000000 0x00000000 0x00000000 0x20000000&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	leds {</div><div class='del'>-		pinctrl-names = "default";</div><div class='del'>-		compatible = "gpio-leds";</div><div class='del'>-</div><div class='del'>-		power1 {</div><div class='del'>-			label = "udpu:green:power";</div><div class='del'>-			gpios = &lt;&amp;gpionb 11 GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		power2 {</div><div class='del'>-			label = "udpu:red:power";</div><div class='del'>-			gpios = &lt;&amp;gpionb 12 GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		network1 {</div><div class='del'>-			label = "udpu:green:network";</div><div class='del'>-			gpios = &lt;&amp;gpionb 13 GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		network2 {</div><div class='del'>-			label = "udpu:red:network";</div><div class='del'>-			gpios = &lt;&amp;gpionb 14 GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		alarm1 {</div><div class='del'>-			label = "udpu:green:alarm";</div><div class='del'>-			gpios = &lt;&amp;gpionb 15 GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		alarm2 {</div><div class='del'>-			label = "udpu:red:alarm";</div><div class='del'>-			gpios = &lt;&amp;gpionb 16 GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='add'>+	compatible = "methode,udpu", "marvell,armada3720", "marvell,armada3710";</div><div class='ctx'> </div><div class='ctx'> 	sfp_eth0: sfp-eth0 {</div><div class='ctx'> 		compatible = "sff,sfp";</div><div class='ctx'> 		i2c-bus = &lt;&amp;i2c0&gt;;</div><div class='del'>-		los-gpio = &lt;&amp;gpiosb 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-		mod-def0-gpio = &lt;&amp;gpiosb 3 GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-		tx-disable-gpio = &lt;&amp;gpiosb 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-		tx-fault-gpio = &lt;&amp;gpiosb 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-		maximum-power-milliwatt = &lt;3000&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	sfp_eth1: sfp-eth1 {</div><div class='del'>-		compatible = "sff,sfp";</div><div class='del'>-		i2c-bus = &lt;&amp;i2c1&gt;;</div><div class='del'>-		los-gpio = &lt;&amp;gpiosb 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-		mod-def0-gpio = &lt;&amp;gpiosb 8 GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-		tx-disable-gpio = &lt;&amp;gpiosb 9 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-		tx-fault-gpio = &lt;&amp;gpiosb 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;gpiosb 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;gpiosb 3 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;gpiosb 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;gpiosb 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 		maximum-power-milliwatt = &lt;3000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;sdhci0 {</div><div class='del'>-	status = "okay";</div><div class='del'>-	bus-width = &lt;8&gt;;</div><div class='del'>-	mmc-ddr-1_8v;</div><div class='del'>-	mmc-hs400-1_8v;</div><div class='del'>-	marvell,pad-type = "fixed-1-8v";</div><div class='del'>-	non-removable;</div><div class='del'>-	no-sd;</div><div class='del'>-	no-sdio;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;spi0 {</div><div class='del'>-	status = "okay";</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-	pinctrl-0 = &lt;&amp;spi_quad_pins&gt;;</div><div class='del'>-</div><div class='del'>-	m25p80@0 {</div><div class='del'>-		compatible = "jedec,spi-nor";</div><div class='del'>-		reg = &lt;0&gt;;</div><div class='del'>-		spi-max-frequency = &lt;54000000&gt;;</div><div class='del'>-</div><div class='del'>-		partitions {</div><div class='del'>-			compatible = "fixed-partitions";</div><div class='del'>-			#address-cells = &lt;1&gt;;</div><div class='del'>-			#size-cells = &lt;1&gt;;</div><div class='del'>-			/* only bootloader is located on the SPI */</div><div class='del'>-			partition@0 {</div><div class='del'>-				label = "uboot";</div><div class='del'>-				reg = &lt;0 0x400000&gt;;</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='add'>+&amp;pinctrl_nb {</div><div class='add'>+	i2c1_recovery_pins: i2c1-recovery-pins {</div><div class='add'>+		groups = "i2c1";</div><div class='add'>+		function = "gpio";</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;i2c0 {</div><div class='ctx'> 	status = "okay";</div><div class='del'>-	pinctrl-names = "default";</div><div class='add'>+	pinctrl-names = "default", "recovery";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;i2c1_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;i2c1_recovery_pins&gt;;</div><div class='ctx'> 	/delete-property/mrvl,i2c-fast-mode;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;i2c1 {</div><div class='del'>-	status = "okay";</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-	pinctrl-0 = &lt;&amp;i2c2_pins&gt;;</div><div class='del'>-	/delete-property/mrvl,i2c-fast-mode;</div><div class='del'>-</div><div class='del'>-	lm75@48 {</div><div class='del'>-		status = "okay";</div><div class='del'>-		compatible = "lm75";</div><div class='del'>-		reg = &lt;0x48&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	lm75@49 {</div><div class='del'>-		status = "okay";</div><div class='del'>-		compatible = "lm75";</div><div class='del'>-		reg = &lt;0x49&gt;;</div><div class='del'>-	};</div><div class='add'>+	scl-gpios = &lt;&amp;gpionb 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpionb 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;eth0 {</div><div class='ctx'> 	phy-mode = "sgmii";</div><div class='del'>-	status = "okay";</div><div class='del'>-	managed = "in-band-status";</div><div class='del'>-	phys = &lt;&amp;comphy1 0&gt;;</div><div class='ctx'> 	sfp = &lt;&amp;sfp_eth0&gt;;</div><div class='ctx'> };</div><div class='del'>-</div><div class='del'>-&amp;eth1 {</div><div class='del'>-	phy-mode = "sgmii";</div><div class='del'>-	status = "okay";</div><div class='del'>-	managed = "in-band-status";</div><div class='del'>-	phys = &lt;&amp;comphy0 1&gt;;</div><div class='del'>-	sfp = &lt;&amp;sfp_eth1&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;usb3 {</div><div class='del'>-	status = "okay";</div><div class='del'>-	phys = &lt;&amp;usb2_utmi_otg_phy&gt;;</div><div class='del'>-	phy-names = "usb2-utmi-otg-phy";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;uart0 {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dtsi b/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dtsi<br/>new file mode 100644<br/>index 000000000000..242820845707<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/armada-3720-uDPU.dtsi</a></div><div class='hunk'>@@ -0,0 +1,164 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Device tree for the uDPU board.</div><div class='add'>+ * Based on Marvell Armada 3720 development board (DB-88F3720-DDR3)</div><div class='add'>+ * Copyright (C) 2016 Marvell</div><div class='add'>+ * Copyright (C) 2019 Methode Electronics</div><div class='add'>+ * Copyright (C) 2019 Telus</div><div class='add'>+ *</div><div class='add'>+ * Vladimir Vid &lt;vladimir.vid@sartura.hr&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include "armada-372x.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x00000000 0x00000000 0x00000000 0x20000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;spi_quad_pins&gt;;</div><div class='add'>+</div><div class='add'>+		led-power1 {</div><div class='add'>+			label = "udpu:green:power";</div><div class='add'>+			gpios = &lt;&amp;gpionb 11 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-power2 {</div><div class='add'>+			label = "udpu:red:power";</div><div class='add'>+			gpios = &lt;&amp;gpionb 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-network1 {</div><div class='add'>+			label = "udpu:green:network";</div><div class='add'>+			gpios = &lt;&amp;gpionb 13 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-network2 {</div><div class='add'>+			label = "udpu:red:network";</div><div class='add'>+			gpios = &lt;&amp;gpionb 14 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-alarm1 {</div><div class='add'>+			label = "udpu:green:alarm";</div><div class='add'>+			gpios = &lt;&amp;gpionb 15 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-alarm2 {</div><div class='add'>+			label = "udpu:red:alarm";</div><div class='add'>+			gpios = &lt;&amp;gpionb 16 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp_eth1: sfp-eth1 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;i2c1&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;gpiosb 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;gpiosb 8 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;gpiosb 9 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;gpiosb 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		maximum-power-milliwatt = &lt;3000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sdhci0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	mmc-ddr-1_8v;</div><div class='add'>+	mmc-hs400-1_8v;</div><div class='add'>+	marvell,pad-type = "fixed-1-8v";</div><div class='add'>+	non-removable;</div><div class='add'>+	no-sd;</div><div class='add'>+	no-sdio;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;54000000&gt;;</div><div class='add'>+</div><div class='add'>+		partitions {</div><div class='add'>+			compatible = "fixed-partitions";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			partition@0 {</div><div class='add'>+				label = "firmware";</div><div class='add'>+				reg = &lt;0x0 0x180000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			partition@180000 {</div><div class='add'>+				label = "u-boot-env";</div><div class='add'>+				reg = &lt;0x180000 0x10000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi_quad_pins {</div><div class='add'>+	function = "gpio";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl_nb {</div><div class='add'>+	i2c2_recovery_pins: i2c2-recovery-pins {</div><div class='add'>+		groups = "i2c2";</div><div class='add'>+		function = "gpio";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-names = "default", "recovery";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c2_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;i2c2_recovery_pins&gt;;</div><div class='add'>+	/delete-property/mrvl,i2c-fast-mode;</div><div class='add'>+	scl-gpios = &lt;&amp;gpionb 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+	sda-gpios = &lt;&amp;gpionb 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+</div><div class='add'>+	temp-sensor@48 {</div><div class='add'>+		compatible = "ti,tmp75c";</div><div class='add'>+		reg = &lt;0x48&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	temp-sensor@49 {</div><div class='add'>+		compatible = "ti,tmp75c";</div><div class='add'>+		reg = &lt;0x49&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eth0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	phys = &lt;&amp;comphy1 0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eth1 {</div><div class='add'>+	phy-mode = "sgmii";</div><div class='add'>+	status = "okay";</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	phys = &lt;&amp;comphy0 1&gt;;</div><div class='add'>+	sfp = &lt;&amp;sfp_eth1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	phys = &lt;&amp;usb2_utmi_otg_phy&gt;;</div><div class='add'>+	phy-names = "usb2-utmi-otg-phy";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/armada-372x.dtsi b/arch/arm64/boot/dts/marvell/armada-372x.dtsi<br/>index 5ce55bdbb995..b99ac4c03a48 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-372x.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-372x.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-372x.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/armada-372x.dtsi</a></div><div class='hunk'>@@ -12,9 +12,6 @@</div><div class='ctx'> #include "armada-37xx.dtsi"</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='del'>-	model = "Marvell Armada 3720 SoC";</div><div class='del'>-	compatible = "marvell,armada3720", "marvell,armada3710";</div><div class='del'>-</div><div class='ctx'> 	cpus {</div><div class='ctx'> 		cpu1: cpu@1 {</div><div class='ctx'> 			device_type = "cpu";</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi<br/>index 000c135e39b7..c612317043ea 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-37xx.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-37xx.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-37xx.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/armada-37xx.dtsi</a></div><div class='hunk'>@@ -11,8 +11,6 @@</div><div class='ctx'> #include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='del'>-	model = "Marvell Armada 37xx SoC";</div><div class='del'>-	compatible = "marvell,armada3700";</div><div class='ctx'> 	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='ctx'> 	#address-cells = &lt;2&gt;;</div><div class='ctx'> 	#size-cells = &lt;2&gt;;</div><div class='hunk'>@@ -35,6 +33,11 @@</div><div class='ctx'> 			reg = &lt;0 0x4000000 0 0x200000&gt;;</div><div class='ctx'> 			no-map;</div><div class='ctx'> 		};</div><div class='add'>+</div><div class='add'>+		tee@4400000 {</div><div class='add'>+			reg = &lt;0 0x4400000 0 0x1000000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	cpus {</div><div class='hunk'>@@ -63,7 +66,7 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	pmu {</div><div class='del'>-		compatible = "arm,armv8-pmuv3";</div><div class='add'>+		compatible = "arm,cortex-a53-pmu";</div><div class='ctx'> 		interrupts = &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -73,7 +76,7 @@</div><div class='ctx'> 		#size-cells = &lt;2&gt;;</div><div class='ctx'> 		ranges;</div><div class='ctx'> </div><div class='del'>-		internal-regs@d0000000 {</div><div class='add'>+		bus@d0000000 {</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;1&gt;;</div><div class='ctx'> 			compatible = "simple-bus";</div><div class='hunk'>@@ -132,10 +135,20 @@</div><div class='ctx'> 				reg = &lt;0x11500 0x40&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='add'>+			uartclk: clock-controller@12010 {</div><div class='add'>+				compatible = "marvell,armada-3700-uart-clock";</div><div class='add'>+				reg = &lt;0x12010 0x4&gt;, &lt;0x12210 0x4&gt;;</div><div class='add'>+				clocks = &lt;&amp;tbg 0&gt;, &lt;&amp;tbg 1&gt;, &lt;&amp;tbg 2&gt;,</div><div class='add'>+					 &lt;&amp;tbg 3&gt;, &lt;&amp;xtalclk&gt;;</div><div class='add'>+				clock-names = "TBG-A-P", "TBG-B-P", "TBG-A-S",</div><div class='add'>+					      "TBG-B-S", "xtal";</div><div class='add'>+				#clock-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='ctx'> 			uart0: serial@12000 {</div><div class='ctx'> 				compatible = "marvell,armada-3700-uart";</div><div class='del'>-				reg = &lt;0x12000 0x200&gt;;</div><div class='del'>-				clocks = &lt;&amp;xtalclk&gt;;</div><div class='add'>+				reg = &lt;0x12000 0x18&gt;;</div><div class='add'>+				clocks = &lt;&amp;uartclk 0&gt;;</div><div class='ctx'> 				interrupts =</div><div class='ctx'> 				&lt;GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 				&lt;GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='hunk'>@@ -147,7 +160,7 @@</div><div class='ctx'> 			uart1: serial@12200 {</div><div class='ctx'> 				compatible = "marvell,armada-3700-uart-ext";</div><div class='ctx'> 				reg = &lt;0x12200 0x30&gt;;</div><div class='del'>-				clocks = &lt;&amp;xtalclk&gt;;</div><div class='add'>+				clocks = &lt;&amp;uartclk 1&gt;;</div><div class='ctx'> 				interrupts =</div><div class='ctx'> 				&lt;GIC_SPI 30 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='ctx'> 				&lt;GIC_SPI 31 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='hunk'>@@ -156,7 +169,8 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			nb_periph_clk: nb-periph-clk@13000 {</div><div class='del'>-				compatible = "marvell,armada-3700-periph-clock-nb";</div><div class='add'>+				compatible = "marvell,armada-3700-periph-clock-nb",</div><div class='add'>+					     "syscon";</div><div class='ctx'> 				reg = &lt;0x13000 0x100&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;tbg 0&gt;, &lt;&amp;tbg 1&gt;, &lt;&amp;tbg 2&gt;,</div><div class='ctx'> 				&lt;&amp;tbg 3&gt;, &lt;&amp;xtalclk&gt;;</div><div class='hunk'>@@ -264,6 +278,8 @@</div><div class='ctx'> 					    "lane2_sata_usb3";</div><div class='ctx'> 				#address-cells = &lt;1&gt;;</div><div class='ctx'> 				#size-cells = &lt;0&gt;;</div><div class='add'>+				clocks = &lt;&amp;xtalclk&gt;;</div><div class='add'>+				clock-names = "xtal";</div><div class='ctx'> </div><div class='ctx'> 				comphy0: phy@0 {</div><div class='ctx'> 					reg = &lt;0&gt;;</div><div class='hunk'>@@ -316,8 +332,8 @@</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='ctx'> 				pcie_reset_pins: pcie-reset-pins {</div><div class='del'>-					groups = "pcie1";</div><div class='del'>-					function = "pcie";</div><div class='add'>+					groups = "pcie1"; /* this actually controls "pcie1_reset" */</div><div class='add'>+					function = "gpio";</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='ctx'> 				pcie_clkreq_pins: pcie-clkreq-pins {</div><div class='hunk'>@@ -413,14 +429,14 @@</div><div class='ctx'> 			crypto: crypto@90000 {</div><div class='ctx'> 				compatible = "inside-secure,safexcel-eip97ies";</div><div class='ctx'> 				reg = &lt;0x90000 0x20000&gt;;</div><div class='del'>-				interrupts = &lt;GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-					     &lt;GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				interrupts = &lt;GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 					     &lt;GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 					     &lt;GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 					     &lt;GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-					     &lt;GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-				interrupt-names = "mem", "ring0", "ring1",</div><div class='del'>-						  "ring2", "ring3", "eip";</div><div class='add'>+					     &lt;GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				interrupt-names = "ring0", "ring1", "ring2",</div><div class='add'>+						  "ring3", "eip", "mem";</div><div class='ctx'> 				clocks = &lt;&amp;nb_periph_clk 15&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -431,7 +447,7 @@</div><div class='ctx'> 				#mbox-cells = &lt;1&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			sdhci1: sdhci@d0000 {</div><div class='add'>+			sdhci1: mmc@d0000 {</div><div class='ctx'> 				compatible = "marvell,armada-3700-sdhci",</div><div class='ctx'> 					     "marvell,sdhci-xenon";</div><div class='ctx'> 				reg = &lt;0xd0000 0x300&gt;,</div><div class='hunk'>@@ -442,7 +458,7 @@</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			sdhci0: sdhci@d8000 {</div><div class='add'>+			sdhci0: mmc@d8000 {</div><div class='ctx'> 				compatible = "marvell,armada-3700-sdhci",</div><div class='ctx'> 					     "marvell,sdhci-xenon";</div><div class='ctx'> 				reg = &lt;0xd8000 0x300&gt;,</div><div class='hunk'>@@ -458,6 +474,8 @@</div><div class='ctx'> 				reg = &lt;0xe0000 0x178&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;nb_periph_clk 1&gt;;</div><div class='add'>+				phys = &lt;&amp;comphy2 0&gt;;</div><div class='add'>+				phy-names = "sata-phy";</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -484,19 +502,38 @@</div><div class='ctx'> 			bus-range = &lt;0x00 0xff&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;sb_periph_clk 13&gt;;</div><div class='ctx'> 			msi-parent = &lt;&amp;pcie0&gt;;</div><div class='ctx'> 			msi-controller;</div><div class='del'>-			ranges = &lt;0x82000000 0 0xe8000000   0 0xe8000000 0 0x1000000 /* Port 0 MEM */</div><div class='del'>-				  0x81000000 0 0xe9000000   0 0xe9000000 0 0x10000&gt;; /* Port 0 IO*/</div><div class='add'>+			/*</div><div class='add'>+			 * The 128 MiB address range [0xe8000000-0xf0000000] is</div><div class='add'>+			 * dedicated for PCIe and can be assigned to 8 windows</div><div class='add'>+			 * with size a power of two. Use one 64 KiB window for</div><div class='add'>+			 * IO at the end and the remaining seven windows</div><div class='add'>+			 * (totaling 127 MiB) for MEM.</div><div class='add'>+			 */</div><div class='add'>+			ranges = &lt;0x82000000 0 0xe8000000   0 0xe8000000   0 0x07f00000   /* Port 0 MEM */</div><div class='add'>+				  0x81000000 0 0x00000000   0 0xefff0000   0 0x00010000&gt;; /* Port 0 IO */</div><div class='ctx'> 			interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='ctx'> 			interrupt-map = &lt;0 0 0 1 &amp;pcie_intc 0&gt;,</div><div class='ctx'> 					&lt;0 0 0 2 &amp;pcie_intc 1&gt;,</div><div class='ctx'> 					&lt;0 0 0 3 &amp;pcie_intc 2&gt;,</div><div class='ctx'> 					&lt;0 0 0 4 &amp;pcie_intc 3&gt;;</div><div class='add'>+			max-link-speed = &lt;2&gt;;</div><div class='add'>+			phys = &lt;&amp;comphy1 0&gt;;</div><div class='ctx'> 			pcie_intc: interrupt-controller {</div><div class='ctx'> 				interrupt-controller;</div><div class='ctx'> 				#interrupt-cells = &lt;1&gt;;</div><div class='add'>+				#address-cells = &lt;0&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	firmware {</div><div class='add'>+		armada-3700-rwtm {</div><div class='add'>+			compatible = "marvell,armada-3700-rwtm-firmware";</div><div class='add'>+			mboxes = &lt;&amp;rwtm 0&gt;;</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/armada-7020.dtsi b/arch/arm64/boot/dts/marvell/armada-7020.dtsi<br/>index 4e46326dd123..570f901b4f4a 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-7020.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-7020.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-7020.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/armada-7020.dtsi</a></div><div class='hunk'>@@ -8,9 +8,3 @@</div><div class='ctx'> </div><div class='ctx'> #include "armada-ap806-dual.dtsi"</div><div class='ctx'> #include "armada-70x0.dtsi"</div><div class='del'>-</div><div class='del'>-/ {</div><div class='del'>-	model = "Marvell Armada 7020";</div><div class='del'>-	compatible = "marvell,armada7020", "marvell,armada-ap806-dual",</div><div class='del'>-		     "marvell,armada-ap806";</div><div class='del'>-};</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts b/arch/arm64/boot/dts/marvell/armada-7040-db.dts<br/>index a7eb4e7697a2..3add6506ff20 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-7040-db.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-7040-db.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-7040-db.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/armada-7040-db.dts</a></div><div class='hunk'>@@ -83,7 +83,7 @@</div><div class='ctx'> &amp;spi0 {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='del'>-	spi-flash@0 {</div><div class='add'>+	flash@0 {</div><div class='ctx'> 		compatible = "jedec,spi-nor";</div><div class='ctx'> 		reg = &lt;0&gt;;</div><div class='ctx'> 		spi-max-frequency = &lt;10000000&gt;;</div><div class='hunk'>@@ -124,7 +124,6 @@</div><div class='ctx'> </div><div class='ctx'> 	expander0: pca9555@21 {</div><div class='ctx'> 		compatible = "nxp,pca9555";</div><div class='del'>-		pinctrl-names = "default";</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> 		reg = &lt;0x21&gt;;</div><div class='hunk'>@@ -186,7 +185,7 @@</div><div class='ctx'> &amp;cp0_spi1 {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='del'>-	spi-flash@0 {</div><div class='add'>+	flash@0 {</div><div class='ctx'> 		compatible = "jedec,spi-nor";</div><div class='ctx'> 		reg = &lt;0x0&gt;;</div><div class='ctx'> 		spi-max-frequency = &lt;20000000&gt;;</div><div class='hunk'>@@ -214,10 +213,14 @@</div><div class='ctx'> </div><div class='ctx'> 	sata-port@1 {</div><div class='ctx'> 		phys = &lt;&amp;cp0_comphy3 1&gt;;</div><div class='del'>-		phy-names = "cp0-sata0-1-phy";</div><div class='add'>+		status = "okay";</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;cp0_utmi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;cp0_comphy1 {</div><div class='ctx'> 	cp0_usbh0_con: connector {</div><div class='ctx'> 		compatible = "usb-a-connector";</div><div class='hunk'>@@ -226,8 +229,9 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cp0_usb3_0 {</div><div class='del'>-	phys = &lt;&amp;cp0_comphy1 0&gt;;</div><div class='del'>-	phy-names = "cp0-usb3h0-comphy";</div><div class='add'>+	phys = &lt;&amp;cp0_comphy1 0&gt;, &lt;&amp;cp0_utmi0&gt;;</div><div class='add'>+	phy-names = "cp0-usb3h0-comphy", "utmi";</div><div class='add'>+	dr_mode = "host";</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -239,8 +243,9 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cp0_usb3_1 {</div><div class='del'>-	phys = &lt;&amp;cp0_comphy4 1&gt;;</div><div class='del'>-	phy-names = "cp0-usb3h1-comphy";</div><div class='add'>+	phys = &lt;&amp;cp0_comphy4 1&gt;, &lt;&amp;cp0_utmi1&gt;;</div><div class='add'>+	phy-names = "cp0-usb3h1-comphy", "utmi";</div><div class='add'>+	dr_mode = "host";</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -276,7 +281,7 @@</div><div class='ctx'> &amp;cp0_eth0 {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> 	/* Network PHY */</div><div class='del'>-	phy-mode = "10gbase-kr";</div><div class='add'>+	phy-mode = "10gbase-r";</div><div class='ctx'> 	/* Generic PHY, providing serdes lanes */</div><div class='ctx'> 	phys = &lt;&amp;cp0_comphy2 0&gt;;</div><div class='ctx'> </div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts b/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts<br/>new file mode 100644<br/>index 000000000000..6bdc4f1e6939<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts</a></div><div class='hunk'>@@ -0,0 +1,457 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Device Tree file for Globalscale MOCHAbin</div><div class='add'>+ * Copyright (C) 2019 Globalscale technologies, Inc.</div><div class='add'>+ * Copyright (C) 2021 Sartura Ltd.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include "armada-7040.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Globalscale MOCHAbin";</div><div class='add'>+	compatible = "globalscale,mochabin", "marvell,armada7040",</div><div class='add'>+		     "marvell,armada-ap806-quad", "marvell,armada-ap806";</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;cp0_eth0;</div><div class='add'>+		ethernet1 = &amp;cp0_eth1;</div><div class='add'>+		ethernet2 = &amp;cp0_eth2;</div><div class='add'>+		ethernet3 = &amp;swport1;</div><div class='add'>+		ethernet4 = &amp;swport2;</div><div class='add'>+		ethernet5 = &amp;swport3;</div><div class='add'>+		ethernet6 = &amp;swport4;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SFP+ 10G */</div><div class='add'>+	sfp_eth0: sfp-eth0 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;cp0_i2c1&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;sfp_gpio 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;sfp_gpio 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;sfp_gpio 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;sfp_gpio 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SFP 1G */</div><div class='add'>+	sfp_eth2: sfp-eth2 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;cp0_i2c0&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;sfp_gpio 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;sfp_gpio 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;sfp_gpio 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;sfp_gpio 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* microUSB UART console */</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart0_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* eMMC */</div><div class='add'>+&amp;ap_sdhci0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	/delete-property/ marvell,xenon-phy-slow-mode;</div><div class='add'>+	no-1-8-v;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_pinctrl {</div><div class='add'>+	cp0_uart0_pins: cp0-uart0-pins {</div><div class='add'>+		marvell,pins = "mpp6", "mpp7";</div><div class='add'>+		marvell,function = "uart0";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cp0_spi0_pins: cp0-spi0-pins {</div><div class='add'>+		marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59";</div><div class='add'>+		marvell,function = "spi0";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cp0_spi1_pins: cp0-spi1-pins {</div><div class='add'>+		marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";</div><div class='add'>+		marvell,function = "spi1";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cp0_i2c0_pins: cp0-i2c0-pins {</div><div class='add'>+		marvell,pins = "mpp37", "mpp38";</div><div class='add'>+		marvell,function = "i2c0";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cp0_i2c1_pins: cp0-i2c1-pins {</div><div class='add'>+		marvell,pins = "mpp2", "mpp3";</div><div class='add'>+		marvell,function = "i2c1";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pca9554_int_pins: pca9554-int-pins {</div><div class='add'>+		marvell,pins = "mpp27";</div><div class='add'>+		marvell,function = "gpio";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cp0_rgmii1_pins: cp0-rgmii1-pins {</div><div class='add'>+		marvell,pins = "mpp44", "mpp45", "mpp46", "mpp47", "mpp48", "mpp49",</div><div class='add'>+			       "mpp50", "mpp51", "mpp52", "mpp53", "mpp54", "mpp55";</div><div class='add'>+		marvell,function = "ge1";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	is31_sdb_pins: is31-sdb-pins {</div><div class='add'>+		marvell,pins = "mpp30";</div><div class='add'>+		marvell,function = "gpio";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cp0_pcie_reset_pins: cp0-pcie-reset-pins {</div><div class='add'>+		marvell,pins = "mpp9";</div><div class='add'>+		marvell,function = "gpio";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cp0_pcie_clkreq_pins: cp0-pcie-clkreq-pins {</div><div class='add'>+		marvell,pins = "mpp5";</div><div class='add'>+		marvell,function = "pcie1";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cp0_switch_pins: cp0-switch-pins {</div><div class='add'>+		marvell,pins = "mpp0", "mpp1";</div><div class='add'>+		marvell,function = "gpio";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cp0_phy_pins: cp0-phy-pins {</div><div class='add'>+		marvell,pins = "mpp12";</div><div class='add'>+		marvell,function = "gpio";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* mikroBUS UART */</div><div class='add'>+&amp;cp0_uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp0_uart0_pins&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* mikroBUS SPI */</div><div class='add'>+&amp;cp0_spi0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp0_spi0_pins&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SPI-NOR */</div><div class='add'>+&amp;cp0_spi1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp0_spi1_pins&gt;;</div><div class='add'>+</div><div class='add'>+	flash@0 {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;20000000&gt;;</div><div class='add'>+</div><div class='add'>+		partitions {</div><div class='add'>+			compatible = "fixed-partitions";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			partition@0 {</div><div class='add'>+				label = "firmware";</div><div class='add'>+				reg = &lt;0x0 0x3e0000&gt;;</div><div class='add'>+				read-only;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			partition@3e0000 {</div><div class='add'>+				label = "hw-info";</div><div class='add'>+				reg = &lt;0x3e0000 0x10000&gt;;</div><div class='add'>+				read-only;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			partition@3f0000 {</div><div class='add'>+				label = "u-boot-env";</div><div class='add'>+				reg = &lt;0x3f0000 0x10000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* mikroBUS, 1G SFP and GPIO expander */</div><div class='add'>+&amp;cp0_i2c0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp0_i2c0_pins&gt;;</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+</div><div class='add'>+	sfp_gpio: pca9554@39 {</div><div class='add'>+		compatible = "nxp,pca9554";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pca9554_int_pins&gt;;</div><div class='add'>+		reg = &lt;0x39&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-parent = &lt;&amp;cp0_gpio1&gt;;</div><div class='add'>+		interrupts = &lt;27 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * IO0_0: SFP+_TX_FAULT</div><div class='add'>+		 * IO0_1: SFP+_TX_DISABLE</div><div class='add'>+		 * IO0_2: SFP+_PRSNT</div><div class='add'>+		 * IO0_3: SFP+_LOSS</div><div class='add'>+		 * IO0_4: SFP_TX_FAULT</div><div class='add'>+		 * IO0_5: SFP_TX_DISABLE</div><div class='add'>+		 * IO0_6: SFP_PRSNT</div><div class='add'>+		 * IO0_7: SFP_LOSS</div><div class='add'>+		 */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* IS31FL3199, mini-PCIe and 10G SFP+ */</div><div class='add'>+&amp;cp0_i2c1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp0_i2c1_pins&gt;;</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+</div><div class='add'>+	leds@64 {</div><div class='add'>+		compatible = "issi,is31fl3199";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;is31_sdb_pins&gt;;</div><div class='add'>+		shutdown-gpios = &lt;&amp;cp0_gpio1 30 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		reg = &lt;0x64&gt;;</div><div class='add'>+</div><div class='add'>+		led1_red: led@1 {</div><div class='add'>+			label = "red:led1";</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			led-max-microamp = &lt;20000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led1_green: led@2 {</div><div class='add'>+			label = "green:led1";</div><div class='add'>+			reg = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led1_blue: led@3 {</div><div class='add'>+			label = "blue:led1";</div><div class='add'>+			reg = &lt;3&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led2_red: led@4 {</div><div class='add'>+			label = "red:led2";</div><div class='add'>+			reg = &lt;4&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led2_green: led@5 {</div><div class='add'>+			label = "green:led2";</div><div class='add'>+			reg = &lt;5&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led2_blue: led@6 {</div><div class='add'>+			label = "blue:led2";</div><div class='add'>+			reg = &lt;6&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led3_red: led@7 {</div><div class='add'>+			label = "red:led3";</div><div class='add'>+			reg = &lt;7&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led3_green: led@8 {</div><div class='add'>+			label = "green:led3";</div><div class='add'>+			reg = &lt;8&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led3_blue: led@9 {</div><div class='add'>+			label = "blue:led3";</div><div class='add'>+			reg = &lt;9&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_mdio {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* 88E1512 PHY */</div><div class='add'>+	eth2phy: ethernet-phy@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		sfp = &lt;&amp;sfp_eth2&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;cp0_phy_pins&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;cp0_gpio1 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* 88E6141 Topaz switch */</div><div class='add'>+	switch: ethernet-switch@3 {</div><div class='add'>+		compatible = "marvell,mv88e6085";</div><div class='add'>+		reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;cp0_switch_pins&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;cp0_gpio1 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-parent = &lt;&amp;cp0_gpio1&gt;;</div><div class='add'>+		interrupts = &lt;1 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		ethernet-ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			swport1: ethernet-port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				label = "lan0";</div><div class='add'>+				phy-handle = &lt;&amp;swphy1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			swport2: ethernet-port@2 {</div><div class='add'>+				reg = &lt;2&gt;;</div><div class='add'>+				label = "lan1";</div><div class='add'>+				phy-handle = &lt;&amp;swphy2&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			swport3: ethernet-port@3 {</div><div class='add'>+				reg = &lt;3&gt;;</div><div class='add'>+				label = "lan2";</div><div class='add'>+				phy-handle = &lt;&amp;swphy3&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			swport4: ethernet-port@4 {</div><div class='add'>+				reg = &lt;4&gt;;</div><div class='add'>+				label = "lan3";</div><div class='add'>+				phy-handle = &lt;&amp;swphy4&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ethernet-port@5 {</div><div class='add'>+				reg = &lt;5&gt;;</div><div class='add'>+				label = "cpu";</div><div class='add'>+				ethernet = &lt;&amp;cp0_eth1&gt;;</div><div class='add'>+				phy-mode = "2500base-x";</div><div class='add'>+				managed = "in-band-status";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			swphy1: ethernet-phy@17 {</div><div class='add'>+				reg = &lt;17&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			swphy2: ethernet-phy@18 {</div><div class='add'>+				reg = &lt;18&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			swphy3: ethernet-phy@19 {</div><div class='add'>+				reg = &lt;19&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			swphy4: ethernet-phy@20 {</div><div class='add'>+				reg = &lt;20&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_ethernet {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* 10G SFP+ */</div><div class='add'>+&amp;cp0_eth0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	phy-mode = "10gbase-r";</div><div class='add'>+	phys = &lt;&amp;cp0_comphy4 0&gt;;</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	sfp = &lt;&amp;sfp_eth0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Topaz switch uplink */</div><div class='add'>+&amp;cp0_eth1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	phy-mode = "2500base-x";</div><div class='add'>+	phys = &lt;&amp;cp0_comphy0 1&gt;;</div><div class='add'>+</div><div class='add'>+	fixed-link {</div><div class='add'>+		speed = &lt;2500&gt;;</div><div class='add'>+		full-duplex;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* 1G SFP or 1G RJ45 */</div><div class='add'>+&amp;cp0_eth2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp0_rgmii1_pins&gt;;</div><div class='add'>+</div><div class='add'>+	phy = &lt;&amp;eth2phy&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_utmi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SMSC USB5434B hub */</div><div class='add'>+&amp;cp0_usb3_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	phys = &lt;&amp;cp0_comphy1 0&gt;, &lt;&amp;cp0_utmi0&gt;;</div><div class='add'>+	phy-names = "cp0-usb3h0-comphy", "utmi";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* miniPCI-E USB */</div><div class='add'>+&amp;cp0_usb3_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_sata0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* 7 + 12 SATA connector (J24) */</div><div class='add'>+	sata-port@0 {</div><div class='add'>+		phys = &lt;&amp;cp0_comphy2 0&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* M.2-2250 B-key (J39) */</div><div class='add'>+	sata-port@1 {</div><div class='add'>+		phys = &lt;&amp;cp0_comphy3 1&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* miniPCI-E (J5) */</div><div class='add'>+&amp;cp0_pcie2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pinctrl-names = "default", "clkreq";</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp0_pcie_reset_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;cp0_pcie_clkreq_pins&gt;;</div><div class='add'>+	phys = &lt;&amp;cp0_comphy5 2&gt;;</div><div class='add'>+	phy-names = "cp0-pcie2-x1-phy";</div><div class='add'>+	reset-gpios = &lt;&amp;cp0_gpio1 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	ranges = &lt;0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x8000000&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/armada-7040.dtsi b/arch/arm64/boot/dts/marvell/armada-7040.dtsi<br/>index 47247215770d..710ac44870bd 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-7040.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-7040.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-7040.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/armada-7040.dtsi</a></div><div class='hunk'>@@ -9,8 +9,26 @@</div><div class='ctx'> #include "armada-ap806-quad.dtsi"</div><div class='ctx'> #include "armada-70x0.dtsi"</div><div class='ctx'> </div><div class='del'>-/ {</div><div class='del'>-	model = "Marvell Armada 7040";</div><div class='del'>-	compatible = "marvell,armada7040", "marvell,armada-ap806-quad",</div><div class='del'>-		     "marvell,armada-ap806";</div><div class='add'>+&amp;cp0_pcie0 {</div><div class='add'>+	iommu-map =</div><div class='add'>+		&lt;0x0   &amp;smmu 0x480 0x20&gt;,</div><div class='add'>+		&lt;0x100 &amp;smmu 0x4a0 0x20&gt;,</div><div class='add'>+		&lt;0x200 &amp;smmu 0x4c0 0x20&gt;;</div><div class='add'>+	iommu-map-mask = &lt;0x031f&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_sata0 {</div><div class='add'>+	iommus = &lt;&amp;smmu 0x444&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_sdhci0 {</div><div class='add'>+	iommus = &lt;&amp;smmu 0x445&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_usb3_0 {</div><div class='add'>+	iommus = &lt;&amp;smmu 0x440&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_usb3_1 {</div><div class='add'>+	iommus = &lt;&amp;smmu 0x441&gt;;</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi<br/>index 293403a1a333..df939426d258 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-70x0.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-70x0.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-70x0.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/armada-70x0.dtsi</a></div><div class='hunk'>@@ -56,7 +56,7 @@</div><div class='ctx'> 			marvell,function = "dev";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		nand_rb: nand-rb {</div><div class='add'>+		nand_rb: nand-rb-pins {</div><div class='ctx'> 			marvell,pins = "mpp13";</div><div class='ctx'> 			marvell,function = "nf";</div><div class='ctx'> 		};</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/armada-8020.dtsi b/arch/arm64/boot/dts/marvell/armada-8020.dtsi<br/>index ba1307c0fadb..b6fc18876093 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-8020.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-8020.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-8020.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/armada-8020.dtsi</a></div><div class='hunk'>@@ -9,12 +9,6 @@</div><div class='ctx'> #include "armada-ap806-dual.dtsi"</div><div class='ctx'> #include "armada-80x0.dtsi"</div><div class='ctx'> </div><div class='del'>-/ {</div><div class='del'>-	model = "Marvell Armada 8020";</div><div class='del'>-	compatible = "marvell,armada8020", "marvell,armada-ap806-dual",</div><div class='del'>-		     "marvell,armada-ap806";</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> /* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock</div><div class='ctx'>  * in CP master is not connected (by package) to the oscillator. So</div><div class='ctx'>  * disable it. However, the RTC clock in CP slave is connected to the</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts<br/>index b90d78a5724b..90ae93274a16 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts</a></div><div class='hunk'>@@ -20,7 +20,7 @@</div><div class='ctx'> 		stdout-path = "serial0:115200n8";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	memory@00000000 {</div><div class='add'>+	memory@0 {</div><div class='ctx'> 		device_type = "memory";</div><div class='ctx'> 		reg = &lt;0x0 0x0 0x0 0x80000000&gt;;</div><div class='ctx'> 	};</div><div class='hunk'>@@ -31,6 +31,16 @@</div><div class='ctx'> 		ethernet2 = &amp;cp1_eth2;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	fan: pwm {</div><div class='add'>+		compatible = "pwm-fan";</div><div class='add'>+		/* 20% steps */</div><div class='add'>+		cooling-levels = &lt;0 51 102 153 204 255&gt;;</div><div class='add'>+		#cooling-cells = &lt;2&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;cp0_fan_pwm_pins&gt;;</div><div class='add'>+		pwms = &lt;&amp;cp0_gpio2 16 40000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	v_3_3: regulator-3-3v {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "v_3_3";</div><div class='hunk'>@@ -54,8 +64,8 @@</div><div class='ctx'> 	sfp_cp0_eth0: sfp-cp0-eth0 {</div><div class='ctx'> 		compatible = "sff,sfp";</div><div class='ctx'> 		i2c-bus = &lt;&amp;cp0_i2c1&gt;;</div><div class='del'>-		mod-def0-gpio = &lt;&amp;cp0_gpio2 17 GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-		tx-disable-gpio = &lt;&amp;cp1_gpio1 29 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;cp0_gpio2 17 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;cp1_gpio1 29 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 		pinctrl-names = "default";</div><div class='ctx'> 		pinctrl-0 = &lt;&amp;cp0_sfp_present_pins &amp;cp1_sfp_tx_disable_pins&gt;;</div><div class='ctx'> 		maximum-power-milliwatt = &lt;2000&gt;;</div><div class='hunk'>@@ -84,7 +94,7 @@</div><div class='ctx'> 		pinctrl-0 = &lt;&amp;cp0_gpio_reset_pins &amp;cp1_wps_button_pins&gt;;</div><div class='ctx'> 		pinctrl-names = "default";</div><div class='ctx'> </div><div class='del'>-		button_0 {</div><div class='add'>+		button-0 {</div><div class='ctx'> 			/* The rear button */</div><div class='ctx'> 			label = "Rear Button";</div><div class='ctx'> 			gpios = &lt;&amp;cp0_gpio2 7 GPIO_ACTIVE_LOW&gt;;</div><div class='hunk'>@@ -92,7 +102,7 @@</div><div class='ctx'> 			linux,code = &lt;BTN_0&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		button_1 {</div><div class='add'>+		button-1 {</div><div class='ctx'> 			/* The wps button */</div><div class='ctx'> 			label = "WPS Button";</div><div class='ctx'> 			gpios = &lt;&amp;cp1_gpio1 30 GPIO_ACTIVE_LOW&gt;;</div><div class='hunk'>@@ -102,6 +112,123 @@</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;ap_thermal_ic {</div><div class='add'>+	polling-delay = &lt;1000&gt;; /* milliseconds */</div><div class='add'>+	trips {</div><div class='add'>+		ap_active: trip-active {</div><div class='add'>+			temperature = &lt;40000&gt;; /* millicelsius */</div><div class='add'>+			hysteresis = &lt;4000&gt;; /* millicelsius */</div><div class='add'>+			type = "active";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+	cooling-maps {</div><div class='add'>+		map0 {</div><div class='add'>+			trip = &lt;&amp;ap_active&gt;;</div><div class='add'>+			cooling-device = &lt;&amp;fan THERMAL_NO_LIMIT 4&gt;;</div><div class='add'>+		};</div><div class='add'>+		map1 {</div><div class='add'>+			trip = &lt;&amp;ap_crit&gt;;</div><div class='add'>+			cooling-device = &lt;&amp;fan 4 5&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_thermal_ic {</div><div class='add'>+	polling-delay = &lt;1000&gt;; /* milliseconds */</div><div class='add'>+	trips {</div><div class='add'>+		cp0_active0: trip-active0 {</div><div class='add'>+			temperature = &lt;40000&gt;; /* millicelsius */</div><div class='add'>+			hysteresis = &lt;2500&gt;; /* millicelsius */</div><div class='add'>+			type = "active";</div><div class='add'>+		};</div><div class='add'>+		cp0_active1: trip-active1 {</div><div class='add'>+			temperature = &lt;45000&gt;; /* millicelsius */</div><div class='add'>+			hysteresis = &lt;2500&gt;; /* millicelsius */</div><div class='add'>+			type = "active";</div><div class='add'>+		};</div><div class='add'>+		cp0_active2: trip-active2 {</div><div class='add'>+			temperature = &lt;50000&gt;; /* millicelsius */</div><div class='add'>+			hysteresis = &lt;2500&gt;; /* millicelsius */</div><div class='add'>+			type = "active";</div><div class='add'>+		};</div><div class='add'>+		cp0_active3: trip-active3 {</div><div class='add'>+			temperature = &lt;60000&gt;; /* millicelsius */</div><div class='add'>+			hysteresis = &lt;2500&gt;; /* millicelsius */</div><div class='add'>+			type = "active";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+	cooling-maps {</div><div class='add'>+		map0 {</div><div class='add'>+			trip = &lt;&amp;cp0_active0&gt;;</div><div class='add'>+			cooling-device = &lt;&amp;fan 0 1&gt;;</div><div class='add'>+		};</div><div class='add'>+		map1 {</div><div class='add'>+			trip = &lt;&amp;cp0_active1&gt;;</div><div class='add'>+			cooling-device = &lt;&amp;fan 1 2&gt;;</div><div class='add'>+		};</div><div class='add'>+		map2 {</div><div class='add'>+			trip = &lt;&amp;cp0_active2&gt;;</div><div class='add'>+			cooling-device = &lt;&amp;fan 2 3&gt;;</div><div class='add'>+		};</div><div class='add'>+		map3 {</div><div class='add'>+			trip = &lt;&amp;cp0_active3&gt;;</div><div class='add'>+			cooling-device = &lt;&amp;fan 3 4&gt;;</div><div class='add'>+		};</div><div class='add'>+		map4 {</div><div class='add'>+			trip = &lt;&amp;cp0_crit&gt;;</div><div class='add'>+			cooling-device = &lt;&amp;fan 4 5&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp1_thermal_ic {</div><div class='add'>+	polling-delay = &lt;1000&gt;; /* milliseconds */</div><div class='add'>+	trips {</div><div class='add'>+		cp1_active0: trip-active0 {</div><div class='add'>+			temperature = &lt;40000&gt;; /* millicelsius */</div><div class='add'>+			hysteresis = &lt;2500&gt;; /* millicelsius */</div><div class='add'>+			type = "active";</div><div class='add'>+		};</div><div class='add'>+		cp1_active1: trip-active1 {</div><div class='add'>+			temperature = &lt;45000&gt;; /* millicelsius */</div><div class='add'>+			hysteresis = &lt;2500&gt;; /* millicelsius */</div><div class='add'>+			type = "active";</div><div class='add'>+		};</div><div class='add'>+		cp1_active2: trip-active2 {</div><div class='add'>+			temperature = &lt;50000&gt;; /* millicelsius */</div><div class='add'>+			hysteresis = &lt;2500&gt;; /* millicelsius */</div><div class='add'>+			type = "active";</div><div class='add'>+		};</div><div class='add'>+		cp1_active3: trip-active3 {</div><div class='add'>+			temperature = &lt;60000&gt;; /* millicelsius */</div><div class='add'>+			hysteresis = &lt;2500&gt;; /* millicelsius */</div><div class='add'>+			type = "active";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+	cooling-maps {</div><div class='add'>+		map0 {</div><div class='add'>+			trip = &lt;&amp;cp1_active0&gt;;</div><div class='add'>+			cooling-device = &lt;&amp;fan 0 1&gt;;</div><div class='add'>+		};</div><div class='add'>+		map1 {</div><div class='add'>+			trip = &lt;&amp;cp1_active1&gt;;</div><div class='add'>+			cooling-device = &lt;&amp;fan 1 2&gt;;</div><div class='add'>+		};</div><div class='add'>+		map2 {</div><div class='add'>+			trip = &lt;&amp;cp1_active2&gt;;</div><div class='add'>+			cooling-device = &lt;&amp;fan 2 3&gt;;</div><div class='add'>+		};</div><div class='add'>+		map3 {</div><div class='add'>+			trip = &lt;&amp;cp1_active3&gt;;</div><div class='add'>+			cooling-device = &lt;&amp;fan 3 4&gt;;</div><div class='add'>+		};</div><div class='add'>+		map4 {</div><div class='add'>+			trip = &lt;&amp;cp1_crit&gt;;</div><div class='add'>+			cooling-device = &lt;&amp;fan 4 5&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;uart0 {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;uart0_pins&gt;;</div><div class='hunk'>@@ -244,25 +371,25 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cp0_gpio2 {</div><div class='del'>-	sata_reset {</div><div class='add'>+	sata-reset-hog {</div><div class='ctx'> 		gpio-hog;</div><div class='ctx'> 		gpios = &lt;1 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 		output-high;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	lte_reset {</div><div class='add'>+	lte-reset-hog {</div><div class='ctx'> 		gpio-hog;</div><div class='ctx'> 		gpios = &lt;2 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 		output-low;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	wlan_disable {</div><div class='add'>+	wlan_disable-hog {</div><div class='ctx'> 		gpio-hog;</div><div class='ctx'> 		gpios = &lt;19 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 		output-low;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	lte_disable {</div><div class='add'>+	lte-disable-hog {</div><div class='ctx'> 		gpio-hog;</div><div class='ctx'> 		gpios = &lt;21 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 		output-low;</div><div class='hunk'>@@ -276,7 +403,7 @@</div><div class='ctx'> /* SFP */</div><div class='ctx'> &amp;cp0_eth0 {</div><div class='ctx'> 	status = "okay";</div><div class='del'>-	phy-mode = "10gbase-kr";</div><div class='add'>+	phy-mode = "10gbase-r";</div><div class='ctx'> 	managed = "in-band-status";</div><div class='ctx'> 	phys = &lt;&amp;cp0_comphy2 0&gt;;</div><div class='ctx'> 	sfp = &lt;&amp;sfp_cp0_eth0&gt;;</div><div class='hunk'>@@ -348,7 +475,7 @@</div><div class='ctx'> </div><div class='ctx'> 	sata-port@1 {</div><div class='ctx'> 		phys = &lt;&amp;cp1_comphy0 1&gt;;</div><div class='del'>-		phy-names = "cp1-sata0-1-phy";</div><div class='add'>+		status = "okay";</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -370,42 +497,42 @@</div><div class='ctx'> 		reset-deassert-us = &lt;10000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	switch0: switch0@4 {</div><div class='add'>+	switch0: ethernet-switch@4 {</div><div class='ctx'> 		compatible = "marvell,mv88e6085";</div><div class='ctx'> 		reg = &lt;4&gt;;</div><div class='ctx'> 		pinctrl-names = "default";</div><div class='ctx'> 		pinctrl-0 = &lt;&amp;cp1_switch_reset_pins&gt;;</div><div class='ctx'> 		reset-gpios = &lt;&amp;cp1_gpio1 24 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> </div><div class='del'>-		ports {</div><div class='add'>+		ethernet-ports {</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> </div><div class='del'>-			port@1 {</div><div class='add'>+			ethernet-port@1 {</div><div class='ctx'> 				reg = &lt;1&gt;;</div><div class='ctx'> 				label = "lan2";</div><div class='ctx'> 				phy-handle = &lt;&amp;switch0phy0&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			port@2 {</div><div class='add'>+			ethernet-port@2 {</div><div class='ctx'> 				reg = &lt;2&gt;;</div><div class='ctx'> 				label = "lan1";</div><div class='ctx'> 				phy-handle = &lt;&amp;switch0phy1&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			port@3 {</div><div class='add'>+			ethernet-port@3 {</div><div class='ctx'> 				reg = &lt;3&gt;;</div><div class='ctx'> 				label = "lan4";</div><div class='ctx'> 				phy-handle = &lt;&amp;switch0phy2&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			port@4 {</div><div class='add'>+			ethernet-port@4 {</div><div class='ctx'> 				reg = &lt;4&gt;;</div><div class='ctx'> 				label = "lan3";</div><div class='ctx'> 				phy-handle = &lt;&amp;switch0phy3&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			port@5 {</div><div class='add'>+			ethernet-port@5 {</div><div class='ctx'> 				reg = &lt;5&gt;;</div><div class='ctx'> 				label = "cpu";</div><div class='ctx'> 				ethernet = &lt;&amp;cp1_eth2&gt;;</div><div class='hunk'>@@ -418,19 +545,19 @@</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> </div><div class='del'>-			switch0phy0: switch0phy0@11 {</div><div class='add'>+			switch0phy0: ethernet-phy@11 {</div><div class='ctx'> 				reg = &lt;0x11&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			switch0phy1: switch0phy1@12 {</div><div class='add'>+			switch0phy1: ethernet-phy@12 {</div><div class='ctx'> 				reg = &lt;0x12&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			switch0phy2: switch0phy2@13 {</div><div class='add'>+			switch0phy2: ethernet-phy@13 {</div><div class='ctx'> 				reg = &lt;0x13&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			switch0phy3: switch0phy3@14 {</div><div class='add'>+			switch0phy3: ethernet-phy@14 {</div><div class='ctx'> 				reg = &lt;0x14&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='hunk'>@@ -454,10 +581,7 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> 	phy-mode = "2500base-x";</div><div class='ctx'> 	phys = &lt;&amp;cp1_comphy5 2&gt;;</div><div class='del'>-	fixed-link {</div><div class='del'>-		speed = &lt;2500&gt;;</div><div class='del'>-		full-duplex;</div><div class='del'>-	};</div><div class='add'>+	managed = "in-band-status";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cp1_spi1 {</div><div class='hunk'>@@ -465,7 +589,7 @@</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;cp1_spi1_pins&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='del'>-	spi-flash@0 {</div><div class='add'>+	flash@0 {</div><div class='ctx'> 		compatible = "st,w25q32";</div><div class='ctx'> 		spi-max-frequency = &lt;50000000&gt;;</div><div class='ctx'> 		reg = &lt;0&gt;;</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts<br/>index 09fb5256f1db..21ecb9c12505 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-8040-db.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-8040-db.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-8040-db.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/armada-8040-db.dts</a></div><div class='hunk'>@@ -72,7 +72,7 @@</div><div class='ctx'> &amp;spi0 {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='del'>-	spi-flash@0 {</div><div class='add'>+	flash@0 {</div><div class='ctx'> 		compatible = "jedec,spi-nor";</div><div class='ctx'> 		reg = &lt;0&gt;;</div><div class='ctx'> 		spi-max-frequency = &lt;10000000&gt;;</div><div class='hunk'>@@ -122,7 +122,6 @@</div><div class='ctx'> 	/* U31 */</div><div class='ctx'> 	expander0: pca9555@21 {</div><div class='ctx'> 		compatible = "nxp,pca9555";</div><div class='del'>-		pinctrl-names = "default";</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> 		reg = &lt;0x21&gt;;</div><div class='hunk'>@@ -131,7 +130,6 @@</div><div class='ctx'> 	/* U25 */</div><div class='ctx'> 	expander1: pca9555@25 {</div><div class='ctx'> 		compatible = "nxp,pca9555";</div><div class='del'>-		pinctrl-names = "default";</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> 		reg = &lt;0x25&gt;;</div><div class='hunk'>@@ -145,17 +143,25 @@</div><div class='ctx'> </div><div class='ctx'> 	sata-port@0 {</div><div class='ctx'> 		phys = &lt;&amp;cp0_comphy1 0&gt;;</div><div class='del'>-		phy-names = "cp0-sata0-0-phy";</div><div class='add'>+		status = "okay";</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='ctx'> 	sata-port@1 {</div><div class='ctx'> 		phys = &lt;&amp;cp0_comphy3 1&gt;;</div><div class='del'>-		phy-names = "cp0-sata0-1-phy";</div><div class='add'>+		status = "okay";</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* CON9 on CP0 expansion */</div><div class='add'>+&amp;cp0_utmi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;cp0_usb3_0 {</div><div class='ctx'> 	usb-phy = &lt;&amp;cp0_usb3_0_phy&gt;;</div><div class='add'>+	phys = &lt;&amp;cp0_utmi0&gt;;</div><div class='add'>+	phy-names = "utmi";</div><div class='add'>+	dr_mode = "host";</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -168,8 +174,9 @@</div><div class='ctx'> </div><div class='ctx'> /* CON10 on CP0 expansion */</div><div class='ctx'> &amp;cp0_usb3_1 {</div><div class='del'>-	phys = &lt;&amp;cp0_comphy4 1&gt;;</div><div class='del'>-	phy-names = "cp0-usb3h1-comphy";</div><div class='add'>+	phys = &lt;&amp;cp0_comphy4 1&gt;, &lt;&amp;cp0_utmi1&gt;;</div><div class='add'>+	phy-names = "usb", "utmi";</div><div class='add'>+	dr_mode = "host";</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -187,7 +194,7 @@</div><div class='ctx'> </div><div class='ctx'> &amp;cp0_eth0 {</div><div class='ctx'> 	status = "okay";</div><div class='del'>-	phy-mode = "10gbase-kr";</div><div class='add'>+	phy-mode = "10gbase-r";</div><div class='ctx'> </div><div class='ctx'> 	fixed-link {</div><div class='ctx'> 		speed = &lt;10000&gt;;</div><div class='hunk'>@@ -230,7 +237,7 @@</div><div class='ctx'> &amp;cp1_spi1 {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='del'>-	spi-flash@0 {</div><div class='add'>+	flash@0 {</div><div class='ctx'> 		compatible = "jedec,spi-nor";</div><div class='ctx'> 		reg = &lt;0x0&gt;;</div><div class='ctx'> 		spi-max-frequency = &lt;20000000&gt;;</div><div class='hunk'>@@ -298,22 +305,29 @@</div><div class='ctx'> </div><div class='ctx'> 	sata-port@0 {</div><div class='ctx'> 		phys = &lt;&amp;cp1_comphy1 0&gt;;</div><div class='del'>-		phy-names = "cp1-sata0-0-phy";</div><div class='ctx'> 	};</div><div class='ctx'> 	sata-port@1 {</div><div class='ctx'> 		phys = &lt;&amp;cp1_comphy3 1&gt;;</div><div class='del'>-		phy-names = "cp1-sata0-1-phy";</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;cp1_utmi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /* CON9 on CP1 expansion */</div><div class='ctx'> &amp;cp1_usb3_0 {</div><div class='ctx'> 	usb-phy = &lt;&amp;cp1_usb3_0_phy&gt;;</div><div class='add'>+	phys = &lt;&amp;cp1_utmi0&gt;;</div><div class='add'>+	phy-names = "utmi";</div><div class='add'>+	dr_mode = "host";</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* CON10 on CP1 expansion */</div><div class='ctx'> &amp;cp1_usb3_1 {</div><div class='add'>+	phys = &lt;&amp;cp1_utmi1&gt;;</div><div class='add'>+	phy-names = "utmi";</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -331,7 +345,7 @@</div><div class='ctx'> </div><div class='ctx'> &amp;cp1_eth0 {</div><div class='ctx'> 	status = "okay";</div><div class='del'>-	phy-mode = "10gbase-kr";</div><div class='add'>+	phy-mode = "10gbase-r";</div><div class='ctx'> </div><div class='ctx'> 	fixed-link {</div><div class='ctx'> 		speed = &lt;10000&gt;;</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts b/arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts<br/>index c3e18fd5bc27..411d20064271 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts</a></div><div class='hunk'>@@ -5,6 +5,8 @@</div><div class='ctx'>  * Device Tree file for MACCHIATOBin Armada 8040 community board platform</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='ctx'> #include "armada-8040-mcbin.dtsi"</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='hunk'>@@ -12,18 +14,38 @@</div><div class='ctx'> 	compatible = "marvell,armada8040-mcbin-singleshot",</div><div class='ctx'> 			"marvell,armada8040-mcbin", "marvell,armada8040",</div><div class='ctx'> 			"marvell,armada-ap806-quad", "marvell,armada-ap806";</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-0 = &lt;&amp;cp0_led18_pins&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		led18 {</div><div class='add'>+			gpios = &lt;&amp;cp0_gpio2 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			function = LED_FUNCTION_HEARTBEAT;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cp0_eth0 {</div><div class='ctx'> 	status = "okay";</div><div class='del'>-	phy-mode = "10gbase-kr";</div><div class='add'>+	phy-mode = "10gbase-r";</div><div class='ctx'> 	managed = "in-band-status";</div><div class='ctx'> 	sfp = &lt;&amp;sfp_eth0&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cp1_eth0 {</div><div class='ctx'> 	status = "okay";</div><div class='del'>-	phy-mode = "10gbase-kr";</div><div class='add'>+	phy-mode = "10gbase-r";</div><div class='ctx'> 	managed = "in-band-status";</div><div class='ctx'> 	sfp = &lt;&amp;sfp_eth1&gt;;</div><div class='ctx'> };</div><div class='add'>+</div><div class='add'>+&amp;cp0_pinctrl {</div><div class='add'>+	cp0_led18_pins: led18-pins {</div><div class='add'>+		marvell,pins = "mpp33";</div><div class='add'>+		marvell,function = "gpio";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts<br/>index d06f5ab7ddab..1766cf58101b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts</a></div><div class='hunk'>@@ -34,12 +34,12 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> 	/* Network PHY */</div><div class='ctx'> 	phy = &lt;&amp;phy0&gt;;</div><div class='del'>-	phy-mode = "10gbase-kr";</div><div class='add'>+	phy-mode = "10gbase-r";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cp1_eth0 {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> 	/* Network PHY */</div><div class='ctx'> 	phy = &lt;&amp;phy8&gt;;</div><div class='del'>-	phy-mode = "10gbase-kr";</div><div class='add'>+	phy-mode = "10gbase-r";</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi<br/>index cbcb210cb6d8..f2d278d171eb 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi</a></div><div class='hunk'>@@ -65,10 +65,10 @@</div><div class='ctx'> 		/* CON15,16 - CPM lane 4 */</div><div class='ctx'> 		compatible = "sff,sfp";</div><div class='ctx'> 		i2c-bus = &lt;&amp;sfpp0_i2c&gt;;</div><div class='del'>-		los-gpio = &lt;&amp;cp1_gpio1 28 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-		mod-def0-gpio = &lt;&amp;cp1_gpio1 27 GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-		tx-disable-gpio = &lt;&amp;cp1_gpio1 29 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-		tx-fault-gpio  = &lt;&amp;cp1_gpio1 26 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;cp1_gpio1 28 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;cp1_gpio1 27 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;cp1_gpio1 29 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;cp1_gpio1 26 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 		pinctrl-names = "default";</div><div class='ctx'> 		pinctrl-0 = &lt;&amp;cp1_sfpp0_pins&gt;;</div><div class='ctx'> 		maximum-power-milliwatt = &lt;2000&gt;;</div><div class='hunk'>@@ -78,10 +78,10 @@</div><div class='ctx'> 		/* CON17,18 - CPS lane 4 */</div><div class='ctx'> 		compatible = "sff,sfp";</div><div class='ctx'> 		i2c-bus = &lt;&amp;sfpp1_i2c&gt;;</div><div class='del'>-		los-gpio = &lt;&amp;cp1_gpio1 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-		mod-def0-gpio = &lt;&amp;cp1_gpio1 11 GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-		tx-disable-gpio = &lt;&amp;cp1_gpio1 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-		tx-fault-gpio = &lt;&amp;cp0_gpio2 30 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;cp1_gpio1 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;cp1_gpio1 11 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;cp1_gpio1 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;cp0_gpio2 30 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 		pinctrl-names = "default";</div><div class='ctx'> 		pinctrl-0 = &lt;&amp;cp1_sfpp1_pins &amp;cp0_sfpp1_pins&gt;;</div><div class='ctx'> 		maximum-power-milliwatt = &lt;2000&gt;;</div><div class='hunk'>@@ -91,10 +91,10 @@</div><div class='ctx'> 		/* CON13,14 - CPS lane 5 */</div><div class='ctx'> 		compatible = "sff,sfp";</div><div class='ctx'> 		i2c-bus = &lt;&amp;sfp_1g_i2c&gt;;</div><div class='del'>-		los-gpio = &lt;&amp;cp0_gpio2 22 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-		mod-def0-gpio = &lt;&amp;cp0_gpio2 21 GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-		tx-disable-gpio = &lt;&amp;cp1_gpio1 24 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-		tx-fault-gpio = &lt;&amp;cp0_gpio2 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;cp0_gpio2 22 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;cp0_gpio2 21 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;cp1_gpio1 24 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;cp0_gpio2 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 		pinctrl-names = "default";</div><div class='ctx'> 		pinctrl-0 = &lt;&amp;cp0_sfp_1g_pins &amp;cp1_sfp_1g_pins&gt;;</div><div class='ctx'> 		maximum-power-milliwatt = &lt;2000&gt;;</div><div class='hunk'>@@ -135,7 +135,7 @@</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;cp0_i2c1_pins&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='del'>-	i2c-switch@70 {</div><div class='add'>+	i2c-mux@70 {</div><div class='ctx'> 		compatible = "nxp,pca9548";</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;0&gt;;</div><div class='hunk'>@@ -245,7 +245,7 @@</div><div class='ctx'> 	/* CPM Lane 5 - U29 */</div><div class='ctx'> 	sata-port@1 {</div><div class='ctx'> 		phys = &lt;&amp;cp0_comphy5 1&gt;;</div><div class='del'>-		phy-names = "cp0-sata0-1-phy";</div><div class='add'>+		status = "okay";</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -259,13 +259,23 @@</div><div class='ctx'> 	vqmmc-supply = &lt;&amp;v_3_3&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;cp0_utmi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;cp0_usb3_0 {</div><div class='ctx'> 	/* J38? - USB2.0 only */</div><div class='add'>+	phys = &lt;&amp;cp0_utmi0&gt;;</div><div class='add'>+	phy-names = "utmi";</div><div class='add'>+	dr_mode = "host";</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;cp0_usb3_1 {</div><div class='ctx'> 	/* J38? - USB2.0 only */</div><div class='add'>+	phys = &lt;&amp;cp0_utmi1&gt;;</div><div class='add'>+	phy-names = "utmi";</div><div class='add'>+	dr_mode = "host";</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -335,13 +345,13 @@</div><div class='ctx'> 	/* CPS Lane 1 - U32 */</div><div class='ctx'> 	sata-port@0 {</div><div class='ctx'> 		phys = &lt;&amp;cp1_comphy1 0&gt;;</div><div class='del'>-		phy-names = "cp1-sata0-0-phy";</div><div class='add'>+		status = "okay";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	/* CPS Lane 3 - U31 */</div><div class='ctx'> 	sata-port@1 {</div><div class='ctx'> 		phys = &lt;&amp;cp1_comphy3 1&gt;;</div><div class='del'>-		phy-names = "cp1-sata0-1-phy";</div><div class='add'>+		status = "okay";</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -350,7 +360,7 @@</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;cp1_spi1_pins&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='del'>-	spi-flash@0 {</div><div class='add'>+	flash@0 {</div><div class='ctx'> 		compatible = "st,w25q32";</div><div class='ctx'> 		spi-max-frequency = &lt;50000000&gt;;</div><div class='ctx'> 		reg = &lt;0&gt;;</div><div class='hunk'>@@ -364,9 +374,14 @@</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;cp1_utmi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;cp1_usb3_0 {</div><div class='ctx'> 	/* CPS Lane 2 - CON7 */</div><div class='del'>-	phys = &lt;&amp;cp1_comphy2 0&gt;;</div><div class='del'>-	phy-names = "cp1-usb3h0-comphy";</div><div class='add'>+	phys = &lt;&amp;cp1_comphy2 0&gt;, &lt;&amp;cp1_utmi0&gt;;</div><div class='add'>+	phy-names = "cp1-usb3h0-comphy", "utmi";</div><div class='add'>+	dr_mode = "host";</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts b/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts<br/>new file mode 100644<br/>index 000000000000..def25d51c4bf<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts</a></div><div class='hunk'>@@ -0,0 +1,523 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2016 Marvell Technology Group Ltd.</div><div class='add'>+ * Copyright (C) 2020 Sartura Ltd.</div><div class='add'>+ *</div><div class='add'>+ * Device Tree file for IEI Puzzle-M801</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "armada-8040.dtsi"</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "IEI-Puzzle-M801";</div><div class='add'>+	compatible = "iei,puzzle-m801", "marvell,armada8040", "marvell,armada-ap806-quad", "marvell,armada-ap806";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;cp0_eth0;</div><div class='add'>+		ethernet1 = &amp;cp1_eth0;</div><div class='add'>+		ethernet2 = &amp;cp0_eth1;</div><div class='add'>+		ethernet3 = &amp;cp0_eth2;</div><div class='add'>+		ethernet4 = &amp;cp1_eth1;</div><div class='add'>+		ethernet5 = &amp;cp1_eth2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x0 0x0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Regulator labels correspond with schematics */</div><div class='add'>+	v_3_3: regulator-3-3v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "v_3_3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;cp0_gpio2 15 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;cp0_xhci_vbus_pins&gt;;</div><div class='add'>+		regulator-name = "v_5v0_usb3_hst_vbus";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	v_vddo_h: regulator-1-8v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "v_vddo_h";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp_cp0_eth0: sfp-cp0-eth0 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;sfpplus0_i2c&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;sfpplus_gpio 11 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;sfpplus_gpio 10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;sfpplus_gpio 9 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;sfpplus_gpio 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		maximum-power-milliwatt = &lt;3000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp_cp1_eth0: sfp-cp1-eth0 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;sfpplus1_i2c&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;sfpplus_gpio 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;sfpplus_gpio 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;sfpplus_gpio 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;sfpplus_gpio 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		maximum-power-milliwatt = &lt;3000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		status = "okay";</div><div class='add'>+		pinctrl-0 = &lt;&amp;cp0_sfpplus_led_pins &amp;cp1_sfpplus_led_pins&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			/* SFP+ port 2: Activity */</div><div class='add'>+			function = LED_FUNCTION_LAN;</div><div class='add'>+			function-enumerator = &lt;0&gt;;</div><div class='add'>+			gpios = &lt;&amp;cp1_gpio1 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			/* SFP+ port 1: Activity */</div><div class='add'>+			function = LED_FUNCTION_LAN;</div><div class='add'>+			function-enumerator = &lt;1&gt;;</div><div class='add'>+			gpios = &lt;&amp;cp1_gpio1 14 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-2 {</div><div class='add'>+			/* SFP+ port 2: 10 Gbps indicator */</div><div class='add'>+			function = LED_FUNCTION_LAN;</div><div class='add'>+			function-enumerator = &lt;2&gt;;</div><div class='add'>+			gpios = &lt;&amp;cp1_gpio1 7 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-3 {</div><div class='add'>+			/* SFP+ port 2: 1 Gbps indicator */</div><div class='add'>+			function = LED_FUNCTION_LAN;</div><div class='add'>+			function-enumerator = &lt;3&gt;;</div><div class='add'>+			gpios = &lt;&amp;cp1_gpio1 8 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-4 {</div><div class='add'>+			/* SFP+ port 1: 10 Gbps indicator */</div><div class='add'>+			function = LED_FUNCTION_LAN;</div><div class='add'>+			function-enumerator = &lt;4&gt;;</div><div class='add'>+			gpios = &lt;&amp;cp1_gpio1 10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-5 {</div><div class='add'>+			/* SFP+ port 1: 1 Gbps indicator */</div><div class='add'>+			function = LED_FUNCTION_LAN;</div><div class='add'>+			function-enumerator = &lt;5&gt;;</div><div class='add'>+			gpios = &lt;&amp;cp1_gpio1 31 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-6 {</div><div class='add'>+			function = LED_FUNCTION_DISK;</div><div class='add'>+			linux,default-trigger = "disk-activity";</div><div class='add'>+			gpios = &lt;&amp;cp0_gpio2 22 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ap_sdhci0 {</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	/*</div><div class='add'>+	 * Not stable in HS modes - phy needs "more calibration", so add</div><div class='add'>+	 * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes.</div><div class='add'>+	 */</div><div class='add'>+	marvell,xenon-phy-slow-mode;</div><div class='add'>+	no-1-8-v;</div><div class='add'>+	no-sd;</div><div class='add'>+	no-sdio;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+	vqmmc-supply = &lt;&amp;v_vddo_h&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ap_thermal_cpu1 {</div><div class='add'>+	trips {</div><div class='add'>+		cpu_active: cpu-active {</div><div class='add'>+			temperature = &lt;44000&gt;;</div><div class='add'>+			hysteresis = &lt;2000&gt;;</div><div class='add'>+			type = "active";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+	cooling-maps {</div><div class='add'>+		fan-map {</div><div class='add'>+			trip = &lt;&amp;cpu_active&gt;;</div><div class='add'>+			cooling-device = &lt;&amp;chassis_fan_group0 64 THERMAL_NO_LIMIT&gt;,</div><div class='add'>+					&lt;&amp;chassis_fan_group1 64 THERMAL_NO_LIMIT&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	rtc@32 {</div><div class='add'>+		compatible = "epson,rx8010";</div><div class='add'>+		reg = &lt;0x32&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	flash@0 {</div><div class='add'>+		#address-cells = &lt;0x1&gt;;</div><div class='add'>+		#size-cells = &lt;0x1&gt;;</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0x0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;20000000&gt;;</div><div class='add'>+		partition@u-boot {</div><div class='add'>+			label = "u-boot";</div><div class='add'>+			reg = &lt;0x00000000 0x001f0000&gt;;</div><div class='add'>+		};</div><div class='add'>+		partition@u-boot-env {</div><div class='add'>+			label = "u-boot-env";</div><div class='add'>+			reg = &lt;0x001f0000 0x00010000&gt;;</div><div class='add'>+		};</div><div class='add'>+		partition@ubi1 {</div><div class='add'>+			label = "ubi1";</div><div class='add'>+			reg = &lt;0x00200000 0x03f00000&gt;;</div><div class='add'>+		};</div><div class='add'>+		partition@ubi2 {</div><div class='add'>+			label = "ubi2";</div><div class='add'>+			reg = &lt;0x04100000 0x03f00000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart0_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	/* IEI WT61P803 PUZZLE MCU Controller */</div><div class='add'>+	mcu {</div><div class='add'>+		compatible = "iei,wt61p803-puzzle";</div><div class='add'>+		current-speed = &lt;115200&gt;;</div><div class='add'>+		enable-beep;</div><div class='add'>+</div><div class='add'>+		leds {</div><div class='add'>+			compatible = "iei,wt61p803-puzzle-leds";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			led@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				function = LED_FUNCTION_POWER;</div><div class='add'>+				color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		hwmon {</div><div class='add'>+			compatible = "iei,wt61p803-puzzle-hwmon";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			chassis_fan_group0:fan-group@0 {</div><div class='add'>+				#cooling-cells = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x00&gt;;</div><div class='add'>+				cooling-levels = &lt;64 102 170 230 250&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			chassis_fan_group1:fan-group@1 {</div><div class='add'>+				#cooling-cells = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x01&gt;;</div><div class='add'>+				cooling-levels = &lt;64 102 170 230 250&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_rtc {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_i2c0 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp0_i2c0_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	sfpplus_gpio: gpio@21 {</div><div class='add'>+		compatible = "nxp,pca9555";</div><div class='add'>+		reg = &lt;0x21&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@54 {</div><div class='add'>+		compatible = "atmel,24c04";</div><div class='add'>+		reg = &lt;0x54&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_i2c1 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp0_i2c1_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	i2c-mux@70 {</div><div class='add'>+		compatible = "nxp,pca9544";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		reg = &lt;0x70&gt;;</div><div class='add'>+</div><div class='add'>+		sfpplus0_i2c: i2c@0 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sfpplus1_i2c: i2c@1 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp0_uart1_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_mdio {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ge_phy2: ethernet-phy@0 {</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ge_phy3: ethernet-phy@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_pcie0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp0_pcie_pins&gt;;</div><div class='add'>+	num-lanes = &lt;1&gt;;</div><div class='add'>+	num-viewport = &lt;8&gt;;</div><div class='add'>+	reset-gpios = &lt;&amp;cp0_gpio2 20 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	ranges = &lt;0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000&gt;;</div><div class='add'>+	phys = &lt;&amp;cp0_comphy0 0&gt;;</div><div class='add'>+	phy-names = "cp0-pcie0-x1-phy";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_pinctrl {</div><div class='add'>+	cp0_ge_mdio_pins: ge-mdio-pins {</div><div class='add'>+		marvell,pins = "mpp32", "mpp34";</div><div class='add'>+		marvell,function = "ge";</div><div class='add'>+	};</div><div class='add'>+	cp0_i2c1_pins: i2c1-pins {</div><div class='add'>+		marvell,pins = "mpp35", "mpp36";</div><div class='add'>+		marvell,function = "i2c1";</div><div class='add'>+	};</div><div class='add'>+	cp0_i2c0_pins: i2c0-pins {</div><div class='add'>+		marvell,pins = "mpp37", "mpp38";</div><div class='add'>+		marvell,function = "i2c0";</div><div class='add'>+	};</div><div class='add'>+	cp0_uart1_pins: uart1-pins {</div><div class='add'>+		marvell,pins = "mpp40", "mpp41";</div><div class='add'>+		marvell,function = "uart1";</div><div class='add'>+	};</div><div class='add'>+	cp0_xhci_vbus_pins: xhci0-vbus-pins {</div><div class='add'>+		marvell,pins = "mpp47";</div><div class='add'>+		marvell,function = "gpio";</div><div class='add'>+	};</div><div class='add'>+	cp0_pcie_pins: pcie-pins {</div><div class='add'>+		marvell,pins = "mpp52";</div><div class='add'>+		marvell,function = "gpio";</div><div class='add'>+	};</div><div class='add'>+	cp0_sdhci_pins: sdhci-pins {</div><div class='add'>+		marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59",</div><div class='add'>+			       "mpp60", "mpp61";</div><div class='add'>+		marvell,function = "sdio";</div><div class='add'>+	};</div><div class='add'>+	cp0_sfpplus_led_pins: sfpplus-led-pins {</div><div class='add'>+		marvell,pins = "mpp54";</div><div class='add'>+		marvell,function = "gpio";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_ethernet {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_eth0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	phy-mode = "10gbase-r";</div><div class='add'>+	phys = &lt;&amp;cp0_comphy4 0&gt;;</div><div class='add'>+	local-mac-address = [ae 00 00 00 ff 00];</div><div class='add'>+	sfp = &lt;&amp;sfp_cp0_eth0&gt;;</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_eth1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	phy = &lt;&amp;ge_phy2&gt;;</div><div class='add'>+	phy-mode = "sgmii";</div><div class='add'>+	local-mac-address = [ae 00 00 00 ff 01];</div><div class='add'>+	phys = &lt;&amp;cp0_comphy3 1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_eth2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	phy-mode = "sgmii";</div><div class='add'>+	phys = &lt;&amp;cp0_comphy1 2&gt;;</div><div class='add'>+	local-mac-address = [ae 00 00 00 ff 02];</div><div class='add'>+	phy = &lt;&amp;ge_phy3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_sata0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	sata-port@0 {</div><div class='add'>+		phys = &lt;&amp;cp0_comphy2 0&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sata-port@1 {</div><div class='add'>+		phys = &lt;&amp;cp0_comphy5 1&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_sdhci0 {</div><div class='add'>+	broken-cd;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp0_sdhci_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+	vqmmc-supply = &lt;&amp;v_3_3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_usb3_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_usb3_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp1_i2c0 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp1_i2c1 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp1_rtc {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp1_ethernet {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp1_eth0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	phy-mode = "10gbase-r";</div><div class='add'>+	phys = &lt;&amp;cp1_comphy4 0&gt;;</div><div class='add'>+	local-mac-address = [ae 00 00 00 ff 03];</div><div class='add'>+	sfp = &lt;&amp;sfp_cp1_eth0&gt;;</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp1_eth1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	phy = &lt;&amp;ge_phy4&gt;;</div><div class='add'>+	phy-mode = "sgmii";</div><div class='add'>+	local-mac-address = [ae 00 00 00 ff 04];</div><div class='add'>+	phys = &lt;&amp;cp1_comphy3 1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp1_eth2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	phy-mode = "sgmii";</div><div class='add'>+	local-mac-address = [ae 00 00 00 ff 05];</div><div class='add'>+	phys = &lt;&amp;cp1_comphy5 2&gt;;</div><div class='add'>+	phy = &lt;&amp;ge_phy5&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp1_pinctrl {</div><div class='add'>+	cp1_sfpplus_led_pins: sfpplus-led-pins {</div><div class='add'>+		marvell,pins = "mpp6", "mpp7", "mpp8", "mpp10", "mpp14", "mpp31";</div><div class='add'>+		marvell,function = "gpio";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp1_uart0 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp1_comphy2 {</div><div class='add'>+	cp1_usbh0_con: connector {</div><div class='add'>+		compatible = "usb-a-connector";</div><div class='add'>+		phy-supply = &lt;&amp;v_5v0_usb3_hst_vbus&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp1_usb3_0 {</div><div class='add'>+	phys = &lt;&amp;cp1_comphy2 0&gt;;</div><div class='add'>+	phy-names = "cp1-usb3h0-comphy";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp1_mdio {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ge_phy4: ethernet-phy@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+	ge_phy5: ethernet-phy@0 {</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp1_pcie0 {</div><div class='add'>+	num-lanes = &lt;2&gt;;</div><div class='add'>+	phys = &lt;&amp;cp1_comphy0 0&gt;, &lt;&amp;cp1_comphy1 0&gt;;</div><div class='add'>+	phy-names = "cp1-pcie0-x2-lane0-phy", "cp1-pcie0-x2-lane1-phy";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/armada-8040.dtsi b/arch/arm64/boot/dts/marvell/armada-8040.dtsi<br/>index 7699b19224c2..3efd9b9e6892 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-8040.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-8040.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-8040.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/armada-8040.dtsi</a></div><div class='hunk'>@@ -9,10 +9,12 @@</div><div class='ctx'> #include "armada-ap806-quad.dtsi"</div><div class='ctx'> #include "armada-80x0.dtsi"</div><div class='ctx'> </div><div class='del'>-/ {</div><div class='del'>-	model = "Marvell Armada 8040";</div><div class='del'>-	compatible = "marvell,armada8040", "marvell,armada-ap806-quad",</div><div class='del'>-		     "marvell,armada-ap806";</div><div class='add'>+&amp;cp0_pcie0 {</div><div class='add'>+	iommu-map =</div><div class='add'>+		&lt;0x0   &amp;smmu 0x480 0x20&gt;,</div><div class='add'>+		&lt;0x100 &amp;smmu 0x4a0 0x20&gt;,</div><div class='add'>+		&lt;0x200 &amp;smmu 0x4c0 0x20&gt;;</div><div class='add'>+	iommu-map-mask = &lt;0x031f&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock</div><div class='hunk'>@@ -23,3 +25,31 @@</div><div class='ctx'> &amp;cp0_rtc {</div><div class='ctx'> 	status = "disabled";</div><div class='ctx'> };</div><div class='add'>+</div><div class='add'>+&amp;cp0_sata0 {</div><div class='add'>+	iommus = &lt;&amp;smmu 0x444&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_sdhci0 {</div><div class='add'>+	iommus = &lt;&amp;smmu 0x445&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_usb3_0 {</div><div class='add'>+	iommus = &lt;&amp;smmu 0x440&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_usb3_1 {</div><div class='add'>+	iommus = &lt;&amp;smmu 0x441&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp1_sata0 {</div><div class='add'>+	iommus = &lt;&amp;smmu 0x454&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp1_usb3_0 {</div><div class='add'>+	iommus = &lt;&amp;smmu 0x450&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp1_usb3_1 {</div><div class='add'>+	iommus = &lt;&amp;smmu 0x451&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/armada-8080.dtsi b/arch/arm64/boot/dts/marvell/armada-8080.dtsi<br/>index 299e814d1ded..32bb56f2fe3f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-8080.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-8080.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-8080.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/armada-8080.dtsi</a></div><div class='hunk'>@@ -6,9 +6,3 @@</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include "armada-ap810-ap0-octa-core.dtsi"</div><div class='del'>-</div><div class='del'>-/ {</div><div class='del'>-	model = "Marvell 8080 board";</div><div class='del'>-	compatible = "marvell,armada-8080", "marvell,armada-ap810-octa",</div><div class='del'>-				"marvell,armada-ap810";</div><div class='del'>-};</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi<br/>index ee67c70bf02e..fb361d657a77 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-80x0.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-80x0.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-80x0.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/armada-80x0.dtsi</a></div><div class='hunk'>@@ -89,7 +89,7 @@</div><div class='ctx'> 			marvell,function = "dev";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		nand_rb: nand-rb {</div><div class='add'>+		nand_rb: nand-rb-pins {</div><div class='ctx'> 			marvell,pins = "mpp13", "mpp12";</div><div class='ctx'> 			marvell,function = "nf";</div><div class='ctx'> 		};</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi<br/>index fcab5173fe67..82f4dedfc25e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi</a></div><div class='hunk'>@@ -8,9 +8,6 @@</div><div class='ctx'> #include "armada-ap806.dtsi"</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='del'>-	model = "Marvell Armada AP806 Dual";</div><div class='del'>-	compatible = "marvell,armada-ap806-dual", "marvell,armada-ap806";</div><div class='del'>-</div><div class='ctx'> 	cpus {</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;0&gt;;</div><div class='hunk'>@@ -51,6 +48,8 @@</div><div class='ctx'> 			cache-size = &lt;0x80000&gt;;</div><div class='ctx'> 			cache-line-size = &lt;64&gt;;</div><div class='ctx'> 			cache-sets = &lt;512&gt;;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi<br/>index 3db427122f9e..f37f49c79a50 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi</a></div><div class='hunk'>@@ -8,9 +8,6 @@</div><div class='ctx'> #include "armada-ap806.dtsi"</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='del'>-	model = "Marvell Armada AP806 Quad";</div><div class='del'>-	compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806";</div><div class='del'>-</div><div class='ctx'> 	cpus {</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;0&gt;;</div><div class='hunk'>@@ -81,6 +78,8 @@</div><div class='ctx'> 			cache-size = &lt;0x80000&gt;;</div><div class='ctx'> 			cache-line-size = &lt;64&gt;;</div><div class='ctx'> 			cache-sets = &lt;512&gt;;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		l2_1: l2-cache1 {</div><div class='hunk'>@@ -88,6 +87,8 @@</div><div class='ctx'> 			cache-size = &lt;0x80000&gt;;</div><div class='ctx'> 			cache-line-size = &lt;64&gt;;</div><div class='ctx'> 			cache-sets = &lt;512&gt;;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi<br/>index 866628679ac7..73a570cf1010 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-ap806.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-ap806.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-ap806.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/armada-ap806.dtsi</a></div><div class='hunk'>@@ -5,14 +5,8 @@</div><div class='ctx'>  * Device Tree file for Marvell Armada AP806.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-#define AP_NAME		ap806</div><div class='ctx'> #include "armada-ap80x.dtsi"</div><div class='ctx'> </div><div class='del'>-/ {</div><div class='del'>-	model = "Marvell Armada AP806";</div><div class='del'>-	compatible = "marvell,armada-ap806";</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> &amp;ap_syscon0 {</div><div class='ctx'> 	ap_clk: clock {</div><div class='ctx'> 		compatible = "marvell,ap806-clock";</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi<br/>index 68782f161f12..e8af7546e893 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi</a></div><div class='hunk'>@@ -8,9 +8,6 @@</div><div class='ctx'> #include "armada-ap807.dtsi"</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='del'>-	model = "Marvell Armada AP807 Quad";</div><div class='del'>-	compatible = "marvell,armada-ap807-quad", "marvell,armada-ap807";</div><div class='del'>-</div><div class='ctx'> 	cpus {</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;0&gt;;</div><div class='hunk'>@@ -81,6 +78,8 @@</div><div class='ctx'> 			cache-size = &lt;0x80000&gt;;</div><div class='ctx'> 			cache-line-size = &lt;64&gt;;</div><div class='ctx'> 			cache-sets = &lt;512&gt;;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		l2_1: l2-cache1 {</div><div class='hunk'>@@ -88,6 +87,8 @@</div><div class='ctx'> 			cache-size = &lt;0x80000&gt;;</div><div class='ctx'> 			cache-line-size = &lt;64&gt;;</div><div class='ctx'> 			cache-sets = &lt;512&gt;;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/armada-ap807.dtsi b/arch/arm64/boot/dts/marvell/armada-ap807.dtsi<br/>index 623010f3ca89..196793d8715c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-ap807.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-ap807.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-ap807.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/armada-ap807.dtsi</a></div><div class='hunk'>@@ -5,14 +5,8 @@</div><div class='ctx'>  * Copyright (C) 2019 Marvell Technology Group Ltd.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-#define AP_NAME		ap807</div><div class='ctx'> #include "armada-ap80x.dtsi"</div><div class='ctx'> </div><div class='del'>-/ {</div><div class='del'>-	model = "Marvell Armada AP807";</div><div class='del'>-	compatible = "marvell,armada-ap807";</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> &amp;ap_syscon0 {</div><div class='ctx'> 	ap_clk: clock {</div><div class='ctx'> 		compatible = "marvell,ap807-clock";</div><div class='hunk'>@@ -27,3 +21,12 @@</div><div class='ctx'> 		#clock-cells = &lt;1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='add'>+</div><div class='add'>+&amp;ap_sdhci0 {</div><div class='add'>+	compatible = "marvell,armada-ap807-sdhci",</div><div class='add'>+		     "marvell,armada-ap806-sdhci"; /* Backward compatibility */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ap_thermal {</div><div class='add'>+	compatible = "marvell,armada-ap807-thermal";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi<br/>index e7438c21ccee..40e146982921 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-ap80x.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/armada-ap80x.dtsi</a></div><div class='hunk'>@@ -41,21 +41,59 @@</div><div class='ctx'> 			reg = &lt;0x0 0x4000000 0x0 0x200000&gt;;</div><div class='ctx'> 			no-map;</div><div class='ctx'> 		};</div><div class='add'>+</div><div class='add'>+		tee@4400000 {</div><div class='add'>+			reg = &lt;0 0x4400000 0 0x1000000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	AP_NAME {</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+				&lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+				&lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+				&lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu {</div><div class='add'>+		compatible = "arm,cortex-a72-pmu";</div><div class='add'>+		interrupt-parent = &lt;&amp;pic&gt;;</div><div class='add'>+		interrupts = &lt;17&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='ctx'> 		#address-cells = &lt;2&gt;;</div><div class='ctx'> 		#size-cells = &lt;2&gt;;</div><div class='ctx'> 		compatible = "simple-bus";</div><div class='ctx'> 		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='ctx'> 		ranges;</div><div class='ctx'> </div><div class='del'>-		config-space@f0000000 {</div><div class='add'>+		bus@f0000000 {</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;1&gt;;</div><div class='ctx'> 			compatible = "simple-bus";</div><div class='ctx'> 			ranges = &lt;0x0 0x0 0xf0000000 0x1000000&gt;;</div><div class='ctx'> </div><div class='add'>+			smmu: iommu@100000 {</div><div class='add'>+				compatible = "marvell,ap806-smmu-500", "arm,mmu-500";</div><div class='add'>+				reg = &lt;0x100000 0x100000&gt;;</div><div class='add'>+				dma-coherent;</div><div class='add'>+				#iommu-cells = &lt;1&gt;;</div><div class='add'>+				#global-interrupts = &lt;1&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='ctx'> 			gic: interrupt-controller@210000 {</div><div class='ctx'> 				compatible = "arm,gic-400";</div><div class='ctx'> 				#interrupt-cells = &lt;3&gt;;</div><div class='hunk'>@@ -99,23 +137,8 @@</div><div class='ctx'> 				};</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			timer {</div><div class='del'>-				compatible = "arm,armv8-timer";</div><div class='del'>-				interrupts = &lt;GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='del'>-					     &lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='del'>-					     &lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='del'>-					     &lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='del'>-			};</div><div class='del'>-</div><div class='del'>-			pmu {</div><div class='del'>-				compatible = "arm,cortex-a72-pmu";</div><div class='del'>-				interrupt-parent = &lt;&amp;pic&gt;;</div><div class='del'>-				interrupts = &lt;17&gt;;</div><div class='del'>-			};</div><div class='del'>-</div><div class='ctx'> 			odmi: odmi@300000 {</div><div class='ctx'> 				compatible = "marvell,odmi-controller";</div><div class='del'>-				interrupt-controller;</div><div class='ctx'> 				msi-controller;</div><div class='ctx'> 				marvell,odmi-frames = &lt;4&gt;;</div><div class='ctx'> 				reg = &lt;0x300000 0x4000&gt;,</div><div class='hunk'>@@ -201,7 +224,6 @@</div><div class='ctx'> 				#address-cells = &lt;1&gt;;</div><div class='ctx'> 				#size-cells = &lt;0&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-				timeout-ms = &lt;1000&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;ap_clk 3&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='hunk'>@@ -233,7 +255,7 @@</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			ap_sdhci0: sdhci@6e0000 {</div><div class='add'>+			ap_sdhci0: mmc@6e0000 {</div><div class='ctx'> 				compatible = "marvell,armada-ap806-sdhci";</div><div class='ctx'> 				reg = &lt;0x6e0000 0x300&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='hunk'>@@ -264,6 +286,9 @@</div><div class='ctx'> 					gpio-controller;</div><div class='ctx'> 					#gpio-cells = &lt;2&gt;;</div><div class='ctx'> 					gpio-ranges = &lt;&amp;ap_pinctrl 0 0 20&gt;;</div><div class='add'>+					marvell,pwm-offset = &lt;0x10c0&gt;;</div><div class='add'>+					#pwm-cells = &lt;2&gt;;</div><div class='add'>+					clocks = &lt;&amp;ap_clk 3&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -292,7 +317,7 @@</div><div class='ctx'> 	 * first one that will have a critical trip point will be chosen.</div><div class='ctx'> 	 */</div><div class='ctx'> 	thermal-zones {</div><div class='del'>-		ap_thermal_ic: ap-thermal-ic {</div><div class='add'>+		ap_thermal_ic: ap-ic-thermal {</div><div class='ctx'> 			polling-delay-passive = &lt;0&gt;; /* Interrupt driven */</div><div class='ctx'> 			polling-delay = &lt;0&gt;; /* Interrupt driven */</div><div class='ctx'> </div><div class='hunk'>@@ -309,7 +334,7 @@</div><div class='ctx'> 			cooling-maps { };</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		ap_thermal_cpu0: ap-thermal-cpu0 {</div><div class='add'>+		ap_thermal_cpu0: ap-cpu0-thermal {</div><div class='ctx'> 			polling-delay-passive = &lt;1000&gt;;</div><div class='ctx'> 			polling-delay = &lt;1000&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -342,7 +367,7 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		ap_thermal_cpu1: ap-thermal-cpu1 {</div><div class='add'>+		ap_thermal_cpu1: ap-cpu1-thermal {</div><div class='ctx'> 			polling-delay-passive = &lt;1000&gt;;</div><div class='ctx'> 			polling-delay = &lt;1000&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -375,7 +400,7 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		ap_thermal_cpu2: ap-thermal-cpu2 {</div><div class='add'>+		ap_thermal_cpu2: ap-cpu2-thermal {</div><div class='ctx'> 			polling-delay-passive = &lt;1000&gt;;</div><div class='ctx'> 			polling-delay = &lt;1000&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -408,7 +433,7 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		ap_thermal_cpu3: ap-thermal-cpu3 {</div><div class='add'>+		ap_thermal_cpu3: ap-cpu3-thermal {</div><div class='ctx'> 			polling-delay-passive = &lt;1000&gt;;</div><div class='ctx'> 			polling-delay = &lt;1000&gt;;</div><div class='ctx'> </div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi b/arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi<br/>index d1a7143ef3d4..2e719ffc8289 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi</a></div><div class='hunk'>@@ -11,7 +11,6 @@</div><div class='ctx'> 	cpus {</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;0&gt;;</div><div class='del'>-		compatible = "marvell,armada-ap810-octa";</div><div class='ctx'> </div><div class='ctx'> 		cpu0: cpu@0 {</div><div class='ctx'> 			device_type = "cpu";</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/armada-ap810-ap0.dtsi b/arch/arm64/boot/dts/marvell/armada-ap810-ap0.dtsi<br/>index 8107d120a8a7..abb37e5fc2c0 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-ap810-ap0.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-ap810-ap0.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-ap810-ap0.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/armada-ap810-ap0.dtsi</a></div><div class='hunk'>@@ -10,10 +10,9 @@</div><div class='ctx'> /dts-v1/;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='del'>-	model = "Marvell Armada AP810";</div><div class='del'>-	compatible = "marvell,armada-ap810";</div><div class='ctx'> 	#address-cells = &lt;2&gt;;</div><div class='ctx'> 	#size-cells = &lt;2&gt;;</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='ctx'> </div><div class='ctx'> 	aliases {</div><div class='ctx'> 		serial0 = &amp;uart0_ap0;</div><div class='hunk'>@@ -25,14 +24,21 @@</div><div class='ctx'> 		method = "smc";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	ap810-ap0 {</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+				&lt;GIC_PPI 14 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+				&lt;GIC_PPI 11 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+				&lt;GIC_PPI 10 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='ctx'> 		#address-cells = &lt;2&gt;;</div><div class='ctx'> 		#size-cells = &lt;2&gt;;</div><div class='ctx'> 		compatible = "simple-bus";</div><div class='del'>-		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='ctx'> 		ranges;</div><div class='ctx'> </div><div class='del'>-		config-space@e8000000 {</div><div class='add'>+		bus@e8000000 {</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;1&gt;;</div><div class='ctx'> 			compatible = "simple-bus";</div><div class='hunk'>@@ -54,7 +60,7 @@</div><div class='ctx'> 				      &lt;0x00d0000 0x1000&gt;,	/* GICH */</div><div class='ctx'> 				      &lt;0x00e0000 0x2000&gt;;	/* GICV */</div><div class='ctx'> </div><div class='del'>-				gic_its_ap0: interrupt-controller@3040000 {</div><div class='add'>+				gic_its_ap0: msi-controller@3040000 {</div><div class='ctx'> 					compatible = "arm,gic-v3-its";</div><div class='ctx'> 					msi-controller;</div><div class='ctx'> 					#msi-cells = &lt;1&gt;;</div><div class='hunk'>@@ -62,14 +68,6 @@</div><div class='ctx'> 				};</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			timer {</div><div class='del'>-				compatible = "arm,armv8-timer";</div><div class='del'>-				interrupts = &lt;GIC_PPI 13 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='del'>-					     &lt;GIC_PPI 14 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='del'>-					     &lt;GIC_PPI 11 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='del'>-					     &lt;GIC_PPI 10 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='del'>-			};</div><div class='del'>-</div><div class='ctx'> 			xor@400000 {</div><div class='ctx'> 				compatible = "marvell,armada-7k-xor", "marvell,xor-v2";</div><div class='ctx'> 				reg = &lt;0x400000 0x1000&gt;,</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi<br/>index 4fd33b0fa56e..e3cfd168becc 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-cp110.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-cp110.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-cp110.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/armada-cp110.dtsi</a></div><div class='hunk'>@@ -5,8 +5,4 @@</div><div class='ctx'>  * Device Tree file for Marvell Armada CP110.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-#define CP11X_TYPE cp110</div><div class='del'>-</div><div class='ctx'> #include "armada-cp11x.dtsi"</div><div class='del'>-</div><div class='del'>-#undef CP11X_TYPE</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/armada-cp115.dtsi b/arch/arm64/boot/dts/marvell/armada-cp115.dtsi<br/>index 1d0a9653e681..ec6432c8db7c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-cp115.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-cp115.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-cp115.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/armada-cp115.dtsi</a></div><div class='hunk'>@@ -5,8 +5,4 @@</div><div class='ctx'>  * Device Tree file for Marvell Armada CP115.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-#define CP11X_TYPE cp115</div><div class='del'>-</div><div class='ctx'> #include "armada-cp11x.dtsi"</div><div class='del'>-</div><div class='del'>-#undef CP11X_TYPE</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi<br/>index 9dcf16beabf5..d9d409eac259 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/armada-cp11x.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/armada-cp11x.dtsi</a></div><div class='hunk'>@@ -17,7 +17,7 @@</div><div class='ctx'> 	 * The contents of the node are defined below, in order to</div><div class='ctx'> 	 * save one indentation level</div><div class='ctx'> 	 */</div><div class='del'>-	CP11X_NAME: CP11X_NAME { };</div><div class='add'>+	CP11X_NAME: CP11X_NODE_NAME(bus) { };</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * CPs only have one sensor in the thermal IC.</div><div class='hunk'>@@ -25,7 +25,7 @@</div><div class='ctx'> 	 * The cooling maps are empty as there are no cooling devices.</div><div class='ctx'> 	 */</div><div class='ctx'> 	thermal-zones {</div><div class='del'>-		CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(thermal-ic) {</div><div class='add'>+		CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(ic-thermal) {</div><div class='ctx'> 			polling-delay-passive = &lt;0&gt;; /* Interrupt driven */</div><div class='ctx'> 			polling-delay = &lt;0&gt;; /* Interrupt driven */</div><div class='ctx'> </div><div class='hunk'>@@ -51,15 +51,17 @@</div><div class='ctx'> 	interrupt-parent = &lt;&amp;CP11X_LABEL(icu_nsr)&gt;;</div><div class='ctx'> 	ranges;</div><div class='ctx'> </div><div class='del'>-	config-space@CP11X_BASE {</div><div class='add'>+	bus@CP11X_BASE {</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;1&gt;;</div><div class='ctx'> 		compatible = "simple-bus";</div><div class='ctx'> 		ranges = &lt;0x0 0x0 ADDRESSIFY(CP11X_BASE) 0x2000000&gt;;</div><div class='ctx'> </div><div class='ctx'> 		CP11X_LABEL(ethernet): ethernet@0 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			compatible = "marvell,armada-7k-pp22";</div><div class='del'>-			reg = &lt;0x0 0x100000&gt;, &lt;0x129000 0xb000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x100000&gt;, &lt;0x129000 0xb000&gt;, &lt;0x220000 0x800&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;CP11X_LABEL(clk) 1 3&gt;, &lt;&amp;CP11X_LABEL(clk) 1 9&gt;,</div><div class='ctx'> 				 &lt;&amp;CP11X_LABEL(clk) 1 5&gt;, &lt;&amp;CP11X_LABEL(clk) 1 6&gt;,</div><div class='ctx'> 				 &lt;&amp;CP11X_LABEL(clk) 1 18&gt;;</div><div class='hunk'>@@ -69,7 +71,7 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 			dma-coherent;</div><div class='ctx'> </div><div class='del'>-			CP11X_LABEL(eth0): eth0 {</div><div class='add'>+			CP11X_LABEL(eth0): ethernet-port@0 {</div><div class='ctx'> 				interrupts = &lt;39 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 					&lt;43 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 					&lt;47 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='hunk'>@@ -83,12 +85,13 @@</div><div class='ctx'> 				interrupt-names = "hif0", "hif1", "hif2",</div><div class='ctx'> 					"hif3", "hif4", "hif5", "hif6", "hif7",</div><div class='ctx'> 					"hif8", "link";</div><div class='del'>-				port-id = &lt;0&gt;;</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				port-id = &lt;0&gt;; /* For backward compatibility. */</div><div class='ctx'> 				gop-port-id = &lt;0&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			CP11X_LABEL(eth1): eth1 {</div><div class='add'>+			CP11X_LABEL(eth1): ethernet-port@1 {</div><div class='ctx'> 				interrupts = &lt;40 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 					&lt;44 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 					&lt;48 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='hunk'>@@ -102,12 +105,13 @@</div><div class='ctx'> 				interrupt-names = "hif0", "hif1", "hif2",</div><div class='ctx'> 					"hif3", "hif4", "hif5", "hif6", "hif7",</div><div class='ctx'> 					"hif8", "link";</div><div class='del'>-				port-id = &lt;1&gt;;</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				port-id = &lt;1&gt;; /* For backward compatibility. */</div><div class='ctx'> 				gop-port-id = &lt;2&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			CP11X_LABEL(eth2): eth2 {</div><div class='add'>+			CP11X_LABEL(eth2): ethernet-port@2 {</div><div class='ctx'> 				interrupts = &lt;41 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 					&lt;45 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 					&lt;49 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='hunk'>@@ -121,7 +125,8 @@</div><div class='ctx'> 				interrupt-names = "hif0", "hif1", "hif2",</div><div class='ctx'> 					"hif3", "hif4", "hif5", "hif6", "hif7",</div><div class='ctx'> 					"hif8", "link";</div><div class='del'>-				port-id = &lt;2&gt;;</div><div class='add'>+				reg = &lt;2&gt;;</div><div class='add'>+				port-id = &lt;2&gt;; /* For backward compatibility. */</div><div class='ctx'> 				gop-port-id = &lt;3&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='hunk'>@@ -197,6 +202,7 @@</div><div class='ctx'> 			CP11X_LABEL(icu_nsr): interrupt-controller@10 {</div><div class='ctx'> 				compatible = "marvell,cp110-icu-nsr";</div><div class='ctx'> 				reg = &lt;0x10 0x20&gt;;</div><div class='add'>+				#address-cells = &lt;0&gt;;</div><div class='ctx'> 				#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 				interrupt-controller;</div><div class='ctx'> 				msi-parent = &lt;&amp;gicp&gt;;</div><div class='hunk'>@@ -234,12 +240,17 @@</div><div class='ctx'> 				gpio-controller;</div><div class='ctx'> 				#gpio-cells = &lt;2&gt;;</div><div class='ctx'> 				gpio-ranges = &lt;&amp;CP11X_LABEL(pinctrl) 0 0 32&gt;;</div><div class='add'>+				marvell,pwm-offset = &lt;0x1f0&gt;;</div><div class='add'>+				#pwm-cells = &lt;2&gt;;</div><div class='ctx'> 				interrupt-controller;</div><div class='ctx'> 				interrupts = &lt;86 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 					&lt;85 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 					&lt;84 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 					&lt;83 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				#interrupt-cells = &lt;2&gt;;</div><div class='add'>+				clock-names = "core", "axi";</div><div class='add'>+				clocks = &lt;&amp;CP11X_LABEL(clk) 1 21&gt;,</div><div class='add'>+					 &lt;&amp;CP11X_LABEL(clk) 1 17&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -250,12 +261,17 @@</div><div class='ctx'> 				gpio-controller;</div><div class='ctx'> 				#gpio-cells = &lt;2&gt;;</div><div class='ctx'> 				gpio-ranges = &lt;&amp;CP11X_LABEL(pinctrl) 0 32 31&gt;;</div><div class='add'>+				marvell,pwm-offset = &lt;0x1f0&gt;;</div><div class='add'>+				#pwm-cells = &lt;2&gt;;</div><div class='ctx'> 				interrupt-controller;</div><div class='ctx'> 				interrupts = &lt;82 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 					&lt;81 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 					&lt;80 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 					&lt;79 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				#interrupt-cells = &lt;2&gt;;</div><div class='add'>+				clock-names = "core", "axi";</div><div class='add'>+				clocks = &lt;&amp;CP11X_LABEL(clk) 1 21&gt;,</div><div class='add'>+					 &lt;&amp;CP11X_LABEL(clk) 1 17&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='hunk'>@@ -275,7 +291,26 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		CP11X_LABEL(usb3_0): usb3@500000 {</div><div class='add'>+		CP11X_LABEL(utmi): utmi@580000 {</div><div class='add'>+			compatible = "marvell,cp110-utmi-phy";</div><div class='add'>+			reg = &lt;0x580000 0x2000&gt;;</div><div class='add'>+			marvell,system-controller = &lt;&amp;CP11X_LABEL(syscon0)&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			CP11X_LABEL(utmi0): usb-phy@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				#phy-cells = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			CP11X_LABEL(utmi1): usb-phy@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				#phy-cells = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		CP11X_LABEL(usb3_0): usb@500000 {</div><div class='ctx'> 			compatible = "marvell,armada-8k-xhci",</div><div class='ctx'> 			"generic-xhci";</div><div class='ctx'> 			reg = &lt;0x500000 0x4000&gt;;</div><div class='hunk'>@@ -287,7 +322,7 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		CP11X_LABEL(usb3_1): usb3@510000 {</div><div class='add'>+		CP11X_LABEL(usb3_1): usb@510000 {</div><div class='ctx'> 			compatible = "marvell,armada-8k-xhci",</div><div class='ctx'> 			"generic-xhci";</div><div class='ctx'> 			reg = &lt;0x510000 0x4000&gt;;</div><div class='hunk'>@@ -313,10 +348,12 @@</div><div class='ctx'> </div><div class='ctx'> 			sata-port@0 {</div><div class='ctx'> 				reg = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			sata-port@1 {</div><div class='ctx'> 				reg = &lt;1&gt;;</div><div class='add'>+				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -434,7 +471,7 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		CP11X_LABEL(nand_controller): nand@720000 {</div><div class='add'>+		CP11X_LABEL(nand_controller): nand-controller@720000 {</div><div class='ctx'> 			/*</div><div class='ctx'> 			 * Due to the limitation of the pins available</div><div class='ctx'> 			 * this controller is only usable on the CPM</div><div class='hunk'>@@ -464,7 +501,7 @@</div><div class='ctx'> 			status = "okay";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		CP11X_LABEL(sdhci0): sdhci@780000 {</div><div class='add'>+		CP11X_LABEL(sdhci0): mmc@780000 {</div><div class='ctx'> 			compatible = "marvell,armada-cp110-sdhci";</div><div class='ctx'> 			reg = &lt;0x780000 0x300&gt;;</div><div class='ctx'> 			interrupts = &lt;27 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='hunk'>@@ -477,14 +514,14 @@</div><div class='ctx'> 		CP11X_LABEL(crypto): crypto@800000 {</div><div class='ctx'> 			compatible = "inside-secure,safexcel-eip197b";</div><div class='ctx'> 			reg = &lt;0x800000 0x200000&gt;;</div><div class='del'>-			interrupts = &lt;87 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;88 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			interrupts = &lt;88 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 				&lt;89 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 				&lt;90 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 				&lt;91 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				&lt;92 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			interrupt-names = "mem", "ring0", "ring1",</div><div class='del'>-				"ring2", "ring3", "eip";</div><div class='add'>+				&lt;92 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;87 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "ring0", "ring1", "ring2", "ring3",</div><div class='add'>+					  "eip", "mem";</div><div class='ctx'> 			clock-names = "core", "reg";</div><div class='ctx'> 			clocks = &lt;&amp;CP11X_LABEL(clk) 1 26&gt;,</div><div class='ctx'> 				 &lt;&amp;CP11X_LABEL(clk) 1 17&gt;;</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/cn9130-cf-base.dts b/arch/arm64/boot/dts/marvell/cn9130-cf-base.dts<br/>new file mode 100644<br/>index 000000000000..788a5c302b17<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/cn9130-cf-base.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/cn9130-cf-base.dts</a></div><div class='hunk'>@@ -0,0 +1,178 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2024 Josua Mayer &lt;josua@solid-run.com&gt;</div><div class='add'>+ *</div><div class='add'>+ * DTS for SolidRun CN9130 Clearfog Base.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+#include "cn9130.dtsi"</div><div class='add'>+#include "cn9130-sr-som.dtsi"</div><div class='add'>+#include "cn9130-cf.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "SolidRun CN9130 Clearfog Base";</div><div class='add'>+	compatible = "solidrun,cn9130-clearfog-base",</div><div class='add'>+		     "solidrun,cn9130-sr-som", "marvell,cn9130";</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		pinctrl-0 = &lt;&amp;rear_button_pins&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		button-0 {</div><div class='add'>+			/* The rear SW3 button */</div><div class='add'>+			label = "Rear Button";</div><div class='add'>+			gpios = &lt;&amp;cp0_gpio1 31 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,can-disable;</div><div class='add'>+			linux,code = &lt;BTN_0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rfkill-m2-gnss {</div><div class='add'>+		compatible = "rfkill-gpio";</div><div class='add'>+		label = "m.2 GNSS";</div><div class='add'>+		radio-type = "gps";</div><div class='add'>+		/* rfkill-gpio inverts internally */</div><div class='add'>+		shutdown-gpios = &lt;&amp;expander0 9 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* M.2 is B-keyed, so w-disable is for WWAN */</div><div class='add'>+	rfkill-m2-wwan {</div><div class='add'>+		compatible = "rfkill-gpio";</div><div class='add'>+		label = "m.2 WWAN";</div><div class='add'>+		radio-type = "wwan";</div><div class='add'>+		/* rfkill-gpio inverts internally */</div><div class='add'>+		shutdown-gpios = &lt;&amp;expander0 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SRDS #3 - SGMII 1GE */</div><div class='add'>+&amp;cp0_eth1 {</div><div class='add'>+	phy = &lt;&amp;phy1&gt;;</div><div class='add'>+	phys = &lt;&amp;cp0_comphy3 1&gt;;</div><div class='add'>+	phy-mode = "sgmii";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_eth2_phy {</div><div class='add'>+	/*</div><div class='add'>+	 * Configure LEDs default behaviour:</div><div class='add'>+	 * - LED[0]: link/activity: On/blink (green)</div><div class='add'>+	 * - LED[1]: link is 100/1000Mbps: On (yellow)</div><div class='add'>+	 * - LED[2]: high impedance (floating)</div><div class='add'>+	 */</div><div class='add'>+	marvell,reg-init = &lt;3 16 0xf000 0x0a61&gt;;</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		led@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_WAN;</div><div class='add'>+			default-state = "keep";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			color = &lt;LED_COLOR_ID_YELLOW&gt;;</div><div class='add'>+			function = LED_FUNCTION_WAN;</div><div class='add'>+			default-state = "keep";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_gpio1 {</div><div class='add'>+	sim-select-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;27 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		output-high;</div><div class='add'>+		line-name = "sim-select";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_mdio {</div><div class='add'>+	phy1: ethernet-phy@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		/*</div><div class='add'>+		 * Configure LEDs default behaviour:</div><div class='add'>+		 * - LED[0]: link/activity: On/blink (green)</div><div class='add'>+		 * - LED[1]: link is 100/1000Mbps: On (yellow)</div><div class='add'>+		 * - LED[2]: high impedance (floating)</div><div class='add'>+		 *</div><div class='add'>+		 * Configure LEDs electrical polarity</div><div class='add'>+		 * - on-state: low</div><div class='add'>+		 * - off-state: high (not hi-z, to avoid residual glow)</div><div class='add'>+		 */</div><div class='add'>+		marvell,reg-init = &lt;3 16 0xf000 0x0a61&gt;,</div><div class='add'>+				   &lt;3 17 0x003f 0x000a&gt;;</div><div class='add'>+</div><div class='add'>+		leds {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			led@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+				function = LED_FUNCTION_LAN;</div><div class='add'>+				default-state = "keep";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			led@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				color = &lt;LED_COLOR_ID_YELLOW&gt;;</div><div class='add'>+				function = LED_FUNCTION_LAN;</div><div class='add'>+				default-state = "keep";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_pinctrl {</div><div class='add'>+	pinctrl-0 = &lt;&amp;sim_select_pins&gt;;</div><div class='add'>+	pintrl-names = "default";</div><div class='add'>+</div><div class='add'>+	rear_button_pins: cp0-rear-button-pins {</div><div class='add'>+		marvell,pins = "mpp31";</div><div class='add'>+		marvell,function = "gpio";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sim_select_pins: cp0-sim-select-pins {</div><div class='add'>+		marvell,pins = "mpp27";</div><div class='add'>+		marvell,function = "gpio";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * SRDS #4 - USB 3.0 host on M.2 connector</div><div class='add'>+ * USB-2.0 Host on Type-A connector</div><div class='add'>+ */</div><div class='add'>+&amp;cp0_usb3_1 {</div><div class='add'>+	phys = &lt;&amp;cp0_comphy4 1&gt;, &lt;&amp;cp0_utmi1&gt;;</div><div class='add'>+	phy-names = "comphy", "utmi";</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;expander0 {</div><div class='add'>+	m2-full-card-power-off-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		output-low;</div><div class='add'>+		line-name = "m2-full-card-power-off";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	m2-reset-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		output-low;</div><div class='add'>+		line-name = "m2-reset";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/cn9130-cf-pro.dts b/arch/arm64/boot/dts/marvell/cn9130-cf-pro.dts<br/>new file mode 100644<br/>index 000000000000..a27fe0042867<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/cn9130-cf-pro.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/cn9130-cf-pro.dts</a></div><div class='hunk'>@@ -0,0 +1,375 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2024 Josua Mayer &lt;josua@solid-run.com&gt;</div><div class='add'>+ *</div><div class='add'>+ * DTS for SolidRun CN9130 Clearfog Pro.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+#include "cn9130.dtsi"</div><div class='add'>+#include "cn9130-sr-som.dtsi"</div><div class='add'>+#include "cn9130-cf.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "SolidRun CN9130 Clearfog Pro";</div><div class='add'>+	compatible = "solidrun,cn9130-clearfog-pro",</div><div class='add'>+		     "solidrun,cn9130-sr-som", "marvell,cn9130";</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		pinctrl-0 = &lt;&amp;rear_button_pins&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		button-0 {</div><div class='add'>+			/* The rear SW3 button */</div><div class='add'>+			label = "Rear Button";</div><div class='add'>+			gpios = &lt;&amp;cp0_gpio2 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,can-disable;</div><div class='add'>+			linux,code = &lt;BTN_0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SRDS #3 - SGMII 1GE to L2 switch */</div><div class='add'>+&amp;cp0_eth1 {</div><div class='add'>+	phys = &lt;&amp;cp0_comphy3 1&gt;;</div><div class='add'>+	phy-mode = "sgmii";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	fixed-link {</div><div class='add'>+		speed = &lt;1000&gt;;</div><div class='add'>+		full-duplex;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_eth2_phy {</div><div class='add'>+	/*</div><div class='add'>+	 * Configure LEDs default behaviour similar to switch ports:</div><div class='add'>+	 * - LED[0]: link/activity: On/blink (green)</div><div class='add'>+	 * - LED[1]: link is 100/1000Mbps: On (red)</div><div class='add'>+	 * - LED[2]: high impedance (floating)</div><div class='add'>+	 *</div><div class='add'>+	 * Switch port defaults:</div><div class='add'>+	 * - LED0: link/activity: On/blink (green)</div><div class='add'>+	 * - LED1: link is 1000Mbps: On (red)</div><div class='add'>+	 *</div><div class='add'>+	 * Identical configuration is impossible with hardware offload.</div><div class='add'>+	 */</div><div class='add'>+	marvell,reg-init = &lt;3 16 0xf000 0x0a61&gt;;</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		led@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_WAN;</div><div class='add'>+			label = "LED2";</div><div class='add'>+			default-state = "keep";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			function = LED_FUNCTION_WAN;</div><div class='add'>+			label = "LED1";</div><div class='add'>+			default-state = "keep";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_mdio {</div><div class='add'>+	ethernet-switch@4 {</div><div class='add'>+		compatible = "marvell,mv88e6085";</div><div class='add'>+		reg = &lt;4&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;dsa_clk_pins &amp;dsa_pins&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		reset-gpios = &lt;&amp;cp0_gpio1 27 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;cp0_gpio1&gt;;</div><div class='add'>+		interrupts = &lt;29 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+</div><div class='add'>+		ethernet-ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			ethernet-port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				label = "lan5";</div><div class='add'>+				phy = &lt;&amp;switch0phy0&gt;;</div><div class='add'>+</div><div class='add'>+				leds {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					led@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+						color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+						function = LED_FUNCTION_LAN;</div><div class='add'>+						label = "LED12";</div><div class='add'>+						default-state = "keep";</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					led@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+						color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+						function = LED_FUNCTION_LAN;</div><div class='add'>+						label = "LED11";</div><div class='add'>+						default-state = "keep";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ethernet-port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				label = "lan4";</div><div class='add'>+				phy = &lt;&amp;switch0phy1&gt;;</div><div class='add'>+</div><div class='add'>+				leds {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					led@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+						color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+						function = LED_FUNCTION_LAN;</div><div class='add'>+						label = "LED10";</div><div class='add'>+						default-state = "keep";</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					led@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+						color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+						function = LED_FUNCTION_LAN;</div><div class='add'>+						label = "LED9";</div><div class='add'>+						default-state = "keep";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ethernet-port@2 {</div><div class='add'>+				reg = &lt;2&gt;;</div><div class='add'>+				label = "lan3";</div><div class='add'>+				phy = &lt;&amp;switch0phy2&gt;;</div><div class='add'>+</div><div class='add'>+				leds {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					led@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+						color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+						function = LED_FUNCTION_LAN;</div><div class='add'>+						label = "LED8";</div><div class='add'>+						default-state = "keep";</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					led@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+						color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+						function = LED_FUNCTION_LAN;</div><div class='add'>+						label = "LED7";</div><div class='add'>+						default-state = "keep";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ethernet-port@3 {</div><div class='add'>+				reg = &lt;3&gt;;</div><div class='add'>+				label = "lan2";</div><div class='add'>+				phy = &lt;&amp;switch0phy3&gt;;</div><div class='add'>+</div><div class='add'>+				leds {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					led@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+						color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+						function = LED_FUNCTION_LAN;</div><div class='add'>+						label = "LED6";</div><div class='add'>+						default-state = "keep";</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					led@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+						color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+						function = LED_FUNCTION_LAN;</div><div class='add'>+						label = "LED5";</div><div class='add'>+						default-state = "keep";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ethernet-port@4 {</div><div class='add'>+				reg = &lt;4&gt;;</div><div class='add'>+				label = "lan1";</div><div class='add'>+				phy = &lt;&amp;switch0phy4&gt;;</div><div class='add'>+</div><div class='add'>+				leds {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					led@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+						color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+						function = LED_FUNCTION_LAN;</div><div class='add'>+						label = "LED4";</div><div class='add'>+						default-state = "keep";</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					led@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+						color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+						function = LED_FUNCTION_LAN;</div><div class='add'>+						label = "LED3";</div><div class='add'>+						default-state = "keep";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ethernet-port@5 {</div><div class='add'>+				reg = &lt;5&gt;;</div><div class='add'>+				label = "cpu";</div><div class='add'>+				ethernet = &lt;&amp;cp0_eth1&gt;;</div><div class='add'>+				phy-mode = "sgmii";</div><div class='add'>+</div><div class='add'>+				fixed-link {</div><div class='add'>+					speed = &lt;1000&gt;;</div><div class='add'>+					full-duplex;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ethernet-port@6 {</div><div class='add'>+				reg = &lt;6&gt;;</div><div class='add'>+				label = "lan6";</div><div class='add'>+				phy-mode = "rgmii";</div><div class='add'>+</div><div class='add'>+				/*</div><div class='add'>+				 * Because of mdio address conflict the</div><div class='add'>+				 * external phy is not readable.</div><div class='add'>+				 * Force a fixed link instead.</div><div class='add'>+				 */</div><div class='add'>+				fixed-link {</div><div class='add'>+					speed = &lt;1000&gt;;</div><div class='add'>+					full-duplex;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			switch0phy0: ethernet-phy@0 {</div><div class='add'>+				reg = &lt;0x0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			switch0phy1: ethernet-phy@1 {</div><div class='add'>+				reg = &lt;0x1&gt;;</div><div class='add'>+				/*</div><div class='add'>+				 * Indirectly configure default behaviour</div><div class='add'>+				 * for port lan6 leds behind external phy.</div><div class='add'>+				 * Internal PHYs are not using page 3,</div><div class='add'>+				 * therefore writing to it is safe.</div><div class='add'>+				 */</div><div class='add'>+				marvell,reg-init = &lt;3 16 0xf000 0x0a61&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			switch0phy2: ethernet-phy@2 {</div><div class='add'>+				reg = &lt;0x2&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			switch0phy3: ethernet-phy@3 {</div><div class='add'>+				reg = &lt;0x3&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			switch0phy4: ethernet-phy@4 {</div><div class='add'>+				reg = &lt;0x4&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * There is an external phy on the switch mdio bus.</div><div class='add'>+		 * Because its mdio address collides with internal phys,</div><div class='add'>+		 * it is not readable.</div><div class='add'>+		 *</div><div class='add'>+		 * mdio-external {</div><div class='add'>+		 *	compatible = "marvell,mv88e6xxx-mdio-external";</div><div class='add'>+		 *	#address-cells = &lt;1&gt;;</div><div class='add'>+		 *	#size-cells = &lt;0&gt;;</div><div class='add'>+		 *</div><div class='add'>+		 *	ethernet-phy@1 {</div><div class='add'>+		 *		reg = &lt;0x1&gt;;</div><div class='add'>+		 *	};</div><div class='add'>+		 * };</div><div class='add'>+		 */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SRDS #4 - miniPCIe (CON2) */</div><div class='add'>+&amp;cp0_pcie1 {</div><div class='add'>+	num-lanes = &lt;1&gt;;</div><div class='add'>+	phys = &lt;&amp;cp0_comphy4 1&gt;;</div><div class='add'>+	/* dw-pcie inverts internally */</div><div class='add'>+	reset-gpios = &lt;&amp;expander0 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_pinctrl {</div><div class='add'>+	dsa_clk_pins: cp0-dsa-clk-pins {</div><div class='add'>+		marvell,pins = "mpp40";</div><div class='add'>+		marvell,function = "synce1";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dsa_pins: cp0-dsa-pins {</div><div class='add'>+		marvell,pins = "mpp27", "mpp29";</div><div class='add'>+		marvell,function = "gpio";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rear_button_pins: cp0-rear-button-pins {</div><div class='add'>+		marvell,pins = "mpp32";</div><div class='add'>+		marvell,function = "gpio";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cp0_spi1_cs1_pins: cp0-spi1-cs1-pins {</div><div class='add'>+		marvell,pins = "mpp12";</div><div class='add'>+		marvell,function = "spi1";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_spi1 {</div><div class='add'>+	/* add pin for chip-select 1 on mikrobus */</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp0_spi1_pins &amp;cp0_spi1_cs1_pins&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB-2.0 Host on Type-A connector */</div><div class='add'>+&amp;cp0_usb3_1 {</div><div class='add'>+	phys = &lt;&amp;cp0_utmi1&gt;;</div><div class='add'>+	phy-names = "utmi";</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;expander0 {</div><div class='add'>+	/* CON2 */</div><div class='add'>+	pcie1-0-clkreq-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		input;</div><div class='add'>+		line-name = "pcie1.0-clkreq";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* CON2 */</div><div class='add'>+	pcie1-0-w-disable-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;7 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		output-low;</div><div class='add'>+		line-name = "pcie1.0-w-disable";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/cn9130-cf.dtsi b/arch/arm64/boot/dts/marvell/cn9130-cf.dtsi<br/>new file mode 100644<br/>index 000000000000..bd42bfbe408b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/cn9130-cf.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/cn9130-cf.dtsi</a></div><div class='hunk'>@@ -0,0 +1,198 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2024 Josua Mayer &lt;josua@solid-run.com&gt;</div><div class='add'>+ *</div><div class='add'>+ * DTS for common base of SolidRun CN9130 Clearfog Base and Pro.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		/* label nics same order as armada 388 clearfog */</div><div class='add'>+		ethernet0 = &amp;cp0_eth2;</div><div class='add'>+		ethernet1 = &amp;cp0_eth1;</div><div class='add'>+		ethernet2 = &amp;cp0_eth0;</div><div class='add'>+		i2c1 = &amp;cp0_i2c1;</div><div class='add'>+		mmc1 = &amp;cp0_sdhci0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb3_vbus0: regulator-usb3-vbus0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vbus0";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		gpios = &lt;&amp;expander0 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp: sfp {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;cp0_i2c1&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;expander0 12 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;expander0 15 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;expander0 14 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;expander0 13 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		maximum-power-milliwatt = &lt;2000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SRDS #2 - SFP+ 10GE */</div><div class='add'>+&amp;cp0_eth0 {</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	phys = &lt;&amp;cp0_comphy2 0&gt;;</div><div class='add'>+	phy-mode = "10gbase-r";</div><div class='add'>+	sfp = &lt;&amp;sfp&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_i2c0 {</div><div class='add'>+	expander0: gpio-expander@20 {</div><div class='add'>+		compatible = "nxp,pca9555";</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;expander0_pins&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		interrupt-parent = &lt;&amp;cp0_gpio1&gt;;</div><div class='add'>+		interrupts = &lt;4 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		/* CON3 */</div><div class='add'>+		pcie2-0-clkreq-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			input;</div><div class='add'>+			line-name = "pcie2.0-clkreq";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* CON3 */</div><div class='add'>+		pcie2-0-w-disable-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;3 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+			line-name = "pcie2.0-w-disable";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb3-ilimit-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			input;</div><div class='add'>+			line-name = "usb3-current-limit";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		m2-devslp-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;11 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+			line-name = "m.2 devslp";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* The MCP3021 supports standard and fast modes */</div><div class='add'>+	adc@4c {</div><div class='add'>+		compatible = "microchip,mcp3021";</div><div class='add'>+		reg = &lt;0x4c&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	carrier_eeprom: eeprom@52 {</div><div class='add'>+		compatible = "atmel,24c02";</div><div class='add'>+		reg = &lt;0x52&gt;;</div><div class='add'>+		pagesize = &lt;8&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_i2c1 {</div><div class='add'>+	/*</div><div class='add'>+	 * Routed to SFP, M.2, mikrobus, and miniPCIe</div><div class='add'>+	 * SFP limits this to 100kHz, and requires an AT24C01A/02/04 with</div><div class='add'>+	 *  address pins tied low, which takes addresses 0x50 and 0x51.</div><div class='add'>+	 * Mikrobus doesn't specify beyond an I2C bus being present.</div><div class='add'>+	 * PCIe uses ARP to assign addresses, or 0x63-0x64.</div><div class='add'>+	 */</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp0_i2c1_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SRDS #5 - miniPCIe (CON3) */</div><div class='add'>+&amp;cp0_pcie2 {</div><div class='add'>+	num-lanes = &lt;1&gt;;</div><div class='add'>+	phys = &lt;&amp;cp0_comphy5 2&gt;;</div><div class='add'>+	/* dw-pcie inverts internally */</div><div class='add'>+	reset-gpios = &lt;&amp;expander0 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_pinctrl {</div><div class='add'>+	cp0_i2c1_pins: cp0-i2c1-pins {</div><div class='add'>+		marvell,pins = "mpp35", "mpp36";</div><div class='add'>+		marvell,function = "i2c1";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cp0_mmc0_pins: cp0-mmc0-pins {</div><div class='add'>+		marvell,pins = "mpp43", "mpp56", "mpp57", "mpp58",</div><div class='add'>+			       "mpp59", "mpp60", "mpp61";</div><div class='add'>+		marvell,function = "sdio";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mikro_spi_pins: cp0-spi1-cs1-pins {</div><div class='add'>+		marvell,pins = "mpp12";</div><div class='add'>+		marvell,function = "spi1";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mikro_uart_pins: cp0-uart-pins {</div><div class='add'>+		marvell,pins = "mpp2", "mpp3";</div><div class='add'>+		marvell,function = "uart1";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	expander0_pins: cp0-expander0-pins {</div><div class='add'>+		marvell,pins = "mpp4";</div><div class='add'>+		marvell,function = "gpio";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SRDS #0 - SATA on M.2 connector */</div><div class='add'>+&amp;cp0_sata0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	sata-port@1 {</div><div class='add'>+		phys = &lt;&amp;cp0_comphy0 1&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* microSD */</div><div class='add'>+&amp;cp0_sdhci0 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp0_mmc0_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	no-1-8-v;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_spi1 {</div><div class='add'>+	/* CS1 for mikrobus */</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp0_spi1_pins &amp;mikro_spi_pins&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * SRDS #1 - USB-3.0 Host on Type-A connector</div><div class='add'>+ * USB-2.0 Host on mPCI-e connector (CON3)</div><div class='add'>+ */</div><div class='add'>+&amp;cp0_usb3_0 {</div><div class='add'>+	phys = &lt;&amp;cp0_comphy1 0&gt;, &lt;&amp;cp0_utmi0&gt;;</div><div class='add'>+	phy-names = "comphy", "utmi";</div><div class='add'>+	vbus-supply = &lt;&amp;reg_usb3_vbus0&gt;;</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_utmi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* mikrobus uart */</div><div class='add'>+&amp;cp0_uart0 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;mikro_uart_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb-A.dts b/arch/arm64/boot/dts/marvell/cn9130-crb-A.dts<br/>new file mode 100644<br/>index 000000000000..a7b6dfba8af5<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/cn9130-crb-A.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/cn9130-crb-A.dts</a></div><div class='hunk'>@@ -0,0 +1,38 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2020 Marvell International Ltd.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "cn9130-crb.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Marvell Armada CN9130-CRB-A";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_pcie0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	num-lanes = &lt;4&gt;;</div><div class='add'>+	num-viewport = &lt;8&gt;;</div><div class='add'>+	/* Generic PHY, providing serdes lanes */</div><div class='add'>+	phys = &lt;&amp;cp0_comphy0 0</div><div class='add'>+		&amp;cp0_comphy1 0</div><div class='add'>+		&amp;cp0_comphy2 0</div><div class='add'>+		&amp;cp0_comphy3 0&gt;;</div><div class='add'>+	iommu-map =</div><div class='add'>+		&lt;0x0   &amp;smmu 0x480 0x20&gt;,</div><div class='add'>+		&lt;0x100 &amp;smmu 0x4a0 0x20&gt;,</div><div class='add'>+		&lt;0x200 &amp;smmu 0x4c0 0x20&gt;;</div><div class='add'>+	iommu-map-mask = &lt;0x031f&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_usb3_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	usb-phy = &lt;&amp;cp0_usb3_0_phy0&gt;;</div><div class='add'>+	phy-names = "usb";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_usb3_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	usb-phy = &lt;&amp;cp0_usb3_0_phy1&gt;;</div><div class='add'>+	phy-names = "usb";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb-B.dts b/arch/arm64/boot/dts/marvell/cn9130-crb-B.dts<br/>new file mode 100644<br/>index 000000000000..34194745f79e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/cn9130-crb-B.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/cn9130-crb-B.dts</a></div><div class='hunk'>@@ -0,0 +1,47 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2020 Marvell International Ltd.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "cn9130-crb.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Marvell Armada CN9130-CRB-B";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_pcie0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	num-lanes = &lt;1&gt;;</div><div class='add'>+	num-viewport = &lt;8&gt;;</div><div class='add'>+	/* Generic PHY, providing serdes lanes */</div><div class='add'>+	phys = &lt;&amp;cp0_comphy0 0&gt;;</div><div class='add'>+	iommu-map =</div><div class='add'>+		&lt;0x0   &amp;smmu 0x480 0x20&gt;,</div><div class='add'>+		&lt;0x100 &amp;smmu 0x4a0 0x20&gt;,</div><div class='add'>+		&lt;0x200 &amp;smmu 0x4c0 0x20&gt;;</div><div class='add'>+	iommu-map-mask = &lt;0x031f&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_sata0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	sata-port@0 {</div><div class='add'>+		status = "okay";</div><div class='add'>+		/* Generic PHY, providing serdes lanes */</div><div class='add'>+		phys = &lt;&amp;cp0_comphy2 0&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_usb3_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	usb-phy = &lt;&amp;cp0_usb3_0_phy0&gt;;</div><div class='add'>+	phy-names = "usb";</div><div class='add'>+	phys = &lt;&amp;cp0_comphy1 0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_usb3_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	usb-phy = &lt;&amp;cp0_usb3_0_phy1&gt;;</div><div class='add'>+	phy-names = "usb";</div><div class='add'>+	phys = &lt;&amp;cp0_comphy3 1&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi<br/>new file mode 100644<br/>index 000000000000..5e7d6de3cdde<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/cn9130-crb.dtsi</a></div><div class='hunk'>@@ -0,0 +1,360 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2020 Marvell International Ltd.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "cn9130.dtsi" /* include SoC device tree */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		i2c0 = &amp;cp0_i2c0;</div><div class='add'>+		ethernet0 = &amp;cp0_eth0;</div><div class='add'>+		ethernet1 = &amp;cp0_eth1;</div><div class='add'>+		ethernet2 = &amp;cp0_eth2;</div><div class='add'>+		gpio1 = &amp;cp0_gpio1;</div><div class='add'>+		gpio2 = &amp;cp0_gpio2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x0 0x0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ap0_reg_mmc_vccq: regulator-1 {</div><div class='add'>+		compatible = "regulator-gpio";</div><div class='add'>+		regulator-name = "ap0_mmc_vccq";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpios = &lt;&amp;expander0 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		states = &lt;1800000 0x1</div><div class='add'>+			  3300000 0x0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cp0_reg_usb3_vbus1: regulator-2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "cp0-xhci1-vbus";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;expander0 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cp0_usb3_0_phy0: usb-phy-1 {</div><div class='add'>+		compatible = "usb-nop-xceiv";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cp0_usb3_0_phy1: usb-phy-2 {</div><div class='add'>+		compatible = "usb-nop-xceiv";</div><div class='add'>+		vcc-supply = &lt;&amp;cp0_reg_usb3_vbus1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cp0_reg_sd_vccq: regulator-3 {</div><div class='add'>+		compatible = "regulator-gpio";</div><div class='add'>+		regulator-name = "cp0_sd_vccq";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpios = &lt;&amp;cp0_gpio2 18 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		states = &lt;1800000 0x1</div><div class='add'>+			  3300000 0x0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cp0_reg_sd_vcc: regulator-4 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "cp0_sd_vcc";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;cp0_gpio2 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp: sfp {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;cp0_i2c1&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;expander0 3 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;expander0 15 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;expander0 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;cp0_gpio1 24 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		maximum-power-milliwatt = &lt;3000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* on-board eMMC U6 */</div><div class='add'>+&amp;ap_sdhci0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+	mmc-ddr-1_8v;</div><div class='add'>+	vqmmc-supply = &lt;&amp;ap0_reg_mmc_vccq&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_syscon0 {</div><div class='add'>+	cp0_pinctrl: pinctrl {</div><div class='add'>+		compatible = "marvell,cp115-standalone-pinctrl";</div><div class='add'>+</div><div class='add'>+		cp0_i2c0_pins: cp0-i2c-pins-0 {</div><div class='add'>+			marvell,pins = "mpp37", "mpp38";</div><div class='add'>+			marvell,function = "i2c0";</div><div class='add'>+		};</div><div class='add'>+		cp0_i2c1_pins: cp0-i2c-pins-1 {</div><div class='add'>+			marvell,pins = "mpp35", "mpp36";</div><div class='add'>+			marvell,function = "i2c1";</div><div class='add'>+		};</div><div class='add'>+		cp0_sdhci_cd_pins_crb: cp0-sdhci-cd-pins-crb {</div><div class='add'>+			marvell,pins = "mpp55";</div><div class='add'>+			marvell,function = "gpio";</div><div class='add'>+		};</div><div class='add'>+		cp0_sdhci_pins: cp0-sdhi-pins-0 {</div><div class='add'>+			marvell,pins = "mpp56", "mpp57", "mpp58",</div><div class='add'>+				       "mpp59", "mpp60", "mpp61";</div><div class='add'>+			marvell,function = "sdio";</div><div class='add'>+		};</div><div class='add'>+		cp0_spi1_pins: cp0-spi-pins-1 {</div><div class='add'>+			marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";</div><div class='add'>+			marvell,function = "spi1";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_gpio1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_gpio2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_i2c0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp0_i2c0_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	expander0: mcp23x17@20 {</div><div class='add'>+		compatible = "microchip,mcp23017";</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_i2c1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp0_i2c1_pins&gt;;</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+&amp;cp0_sdhci0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp0_sdhci_pins</div><div class='add'>+		     &amp;cp0_sdhci_cd_pins_crb&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;cp0_gpio2 23 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;cp0_reg_sd_vccq&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;cp0_reg_sd_vcc&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_spi1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp0_spi1_pins&gt;;</div><div class='add'>+	reg = &lt;0x700680 0x50&gt;,		/* control */</div><div class='add'>+	      &lt;0x2000000 0x1000000&gt;;	/* CS0 */</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash@0 {</div><div class='add'>+		#address-cells = &lt;0x1&gt;;</div><div class='add'>+		#size-cells = &lt;0x1&gt;;</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0x0&gt;;</div><div class='add'>+		/* On-board MUX does not allow higher frequencies */</div><div class='add'>+		spi-max-frequency = &lt;40000000&gt;;</div><div class='add'>+</div><div class='add'>+		partitions {</div><div class='add'>+			compatible = "fixed-partitions";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			partition@0 {</div><div class='add'>+				label = "U-Boot";</div><div class='add'>+				reg = &lt;0x0 0x200000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			partition@400000 {</div><div class='add'>+				label = "Filesystem";</div><div class='add'>+				reg = &lt;0x200000 0xe00000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_mdio {</div><div class='add'>+	status = "okay";</div><div class='add'>+	phy0: ethernet-phy@0 {</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	switch6: ethernet-switch@6 {</div><div class='add'>+		/* Actual device is MV88E6393X */</div><div class='add'>+		compatible = "marvell,mv88e6190";</div><div class='add'>+		reg = &lt;6&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;cp0_gpio1&gt;;</div><div class='add'>+		interrupts = &lt;28 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		dsa,member = &lt;0 0&gt;;</div><div class='add'>+</div><div class='add'>+		ethernet-ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			ethernet-port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				label = "p1";</div><div class='add'>+				phy-handle = &lt;&amp;switch0phy1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ethernet-port@2 {</div><div class='add'>+				reg = &lt;2&gt;;</div><div class='add'>+				label = "p2";</div><div class='add'>+				phy-handle = &lt;&amp;switch0phy2&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ethernet-port@3 {</div><div class='add'>+				reg = &lt;3&gt;;</div><div class='add'>+				label = "p3";</div><div class='add'>+				phy-handle = &lt;&amp;switch0phy3&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ethernet-port@4 {</div><div class='add'>+				reg = &lt;4&gt;;</div><div class='add'>+				label = "p4";</div><div class='add'>+				phy-handle = &lt;&amp;switch0phy4&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ethernet-port@5 {</div><div class='add'>+				reg = &lt;5&gt;;</div><div class='add'>+				label = "p5";</div><div class='add'>+				phy-handle = &lt;&amp;switch0phy5&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ethernet-port@6 {</div><div class='add'>+				reg = &lt;6&gt;;</div><div class='add'>+				label = "p6";</div><div class='add'>+				phy-handle = &lt;&amp;switch0phy6&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ethernet-port@7 {</div><div class='add'>+				reg = &lt;7&gt;;</div><div class='add'>+				label = "p7";</div><div class='add'>+				phy-handle = &lt;&amp;switch0phy7&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ethernet-port@8 {</div><div class='add'>+				reg = &lt;8&gt;;</div><div class='add'>+				label = "p8";</div><div class='add'>+				phy-handle = &lt;&amp;switch0phy8&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ethernet-port@9 {</div><div class='add'>+				reg = &lt;9&gt;;</div><div class='add'>+				label = "p9";</div><div class='add'>+				phy-mode = "10gbase-r";</div><div class='add'>+				sfp = &lt;&amp;sfp&gt;;</div><div class='add'>+				managed = "in-band-status";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ethernet-port@a {</div><div class='add'>+				reg = &lt;10&gt;;</div><div class='add'>+				ethernet = &lt;&amp;cp0_eth0&gt;;</div><div class='add'>+				phy-mode = "10gbase-r";</div><div class='add'>+				managed = "in-band-status";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			switch0phy1: ethernet-phy@1 {</div><div class='add'>+				reg = &lt;0x1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			switch0phy2: ethernet-phy@2 {</div><div class='add'>+				reg = &lt;0x2&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			switch0phy3: ethernet-phy@3 {</div><div class='add'>+				reg = &lt;0x3&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			switch0phy4: ethernet-phy@4 {</div><div class='add'>+				reg = &lt;0x4&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			switch0phy5: ethernet-phy@5 {</div><div class='add'>+				reg = &lt;0x5&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			switch0phy6: ethernet-phy@6 {</div><div class='add'>+				reg = &lt;0x6&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			switch0phy7: ethernet-phy@7 {</div><div class='add'>+				reg = &lt;0x7&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			switch0phy8: ethernet-phy@8 {</div><div class='add'>+				reg = &lt;0x8&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_xmdio {</div><div class='add'>+	status = "okay";</div><div class='add'>+	nbaset_phy0: ethernet-phy@0 {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_ethernet {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_eth0 {</div><div class='add'>+	/* This port is connected to 88E6393X switch */</div><div class='add'>+	status = "okay";</div><div class='add'>+	phy-mode = "10gbase-r";</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	phys = &lt;&amp;cp0_comphy4 0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_eth1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	phy = &lt;&amp;phy0&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_eth2 {</div><div class='add'>+	/* This port uses "2500base-t" phy-mode */</div><div class='add'>+	status = "disabled";</div><div class='add'>+	phy = &lt;&amp;nbaset_phy0&gt;;</div><div class='add'>+	phys = &lt;&amp;cp0_comphy5 2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/cn9130-db-B.dts b/arch/arm64/boot/dts/marvell/cn9130-db-B.dts<br/>new file mode 100644<br/>index 000000000000..57e41cacd483<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/cn9130-db-B.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/cn9130-db-B.dts</a></div><div class='hunk'>@@ -0,0 +1,22 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2020 Marvell International Ltd.</div><div class='add'>+ *</div><div class='add'>+ * Device tree for the CN9130-DB board (setup "B").</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "cn9130-db.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Marvell Armada CN9130-DB setup B";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Setup B has NAND flash as a boot device, while regular setup uses SPI flash.</div><div class='add'>+ * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated</div><div class='add'>+ * simultaneously. When NAND controller is enabled, SPI1 should be disabled.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;cp0_nand_controller {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi b/arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi<br/>new file mode 100644<br/>index 000000000000..028496ebc473<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi</a></div><div class='hunk'>@@ -0,0 +1,96 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2023 Marvell International Ltd.</div><div class='add'>+ *</div><div class='add'>+ * Device tree for the CN9130-DB Com Express CPU module board.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "cn9130-db.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Marvell Armada CN9130-DB COM EXPRESS type 7 CPU module board";</div><div class='add'>+	compatible = "marvell,cn9130-cpu-module", "marvell,cn9130",</div><div class='add'>+		     "marvell,armada-ap807-quad", "marvell,armada-ap807";</div><div class='add'>+</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ap0_reg_sd_vccq {</div><div class='add'>+	regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	states = &lt;1800000 0x1 1800000 0x0&gt;;</div><div class='add'>+	/delete-property/ gpios;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_reg_usb3_vbus0 {</div><div class='add'>+	/delete-property/ gpio;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_reg_usb3_vbus1 {</div><div class='add'>+	/delete-property/ gpio;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_reg_sd_vcc {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_reg_sd_vccq {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_sdhci0 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_eth0 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_eth1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	phy = &lt;&amp;phy0&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_eth2 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_mdio {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp0_ge_mdio_pins&gt;;</div><div class='add'>+	phy0: ethernet-phy@0 {</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_syscon0 {</div><div class='add'>+	cp0_pinctrl: pinctrl {</div><div class='add'>+		compatible = "marvell,cp115-standalone-pinctrl";</div><div class='add'>+</div><div class='add'>+		cp0_ge_mdio_pins: ge-mdio-pins {</div><div class='add'>+			marvell,pins = "mpp40", "mpp41";</div><div class='add'>+			marvell,function = "ge";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_sdhci0 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_spi1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_usb3_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	usb-phy = &lt;&amp;cp0_usb3_0_phy0&gt;;</div><div class='add'>+	phy-names = "usb";</div><div class='add'>+	/delete-property/ phys;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_usb3_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	usb-phy = &lt;&amp;cp0_usb3_0_phy1&gt;;</div><div class='add'>+	phy-names = "usb";</div><div class='add'>+	/delete-property/ phys;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/cn9130-db.dts b/arch/arm64/boot/dts/marvell/cn9130-db.dts<br/>index ce49a70d88a0..994f347f2973 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/cn9130-db.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/cn9130-db.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/cn9130-db.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/cn9130-db.dts</a></div><div class='hunk'>@@ -5,399 +5,18 @@</div><div class='ctx'>  * Device tree for the CN9130-DB board.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-#include "cn9130.dtsi"</div><div class='del'>-</div><div class='del'>-#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include "cn9130-db.dtsi"</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='del'>-	model = "Marvell Armada CN9130-DB";</div><div class='del'>-</div><div class='del'>-	chosen {</div><div class='del'>-		stdout-path = "serial0:115200n8";</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	aliases {</div><div class='del'>-		gpio1 = &amp;cp0_gpio1;</div><div class='del'>-		gpio2 = &amp;cp0_gpio2;</div><div class='del'>-		i2c0 = &amp;cp0_i2c0;</div><div class='del'>-		ethernet0 = &amp;cp0_eth0;</div><div class='del'>-		ethernet1 = &amp;cp0_eth1;</div><div class='del'>-		ethernet2 = &amp;cp0_eth2;</div><div class='del'>-		spi1 = &amp;cp0_spi0;</div><div class='del'>-		spi2 = &amp;cp0_spi1;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	memory@00000000 {</div><div class='del'>-		device_type = "memory";</div><div class='del'>-		reg = &lt;0x0 0x0 0x0 0x80000000&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	ap0_reg_sd_vccq: ap0_sd_vccq@0 {</div><div class='del'>-		compatible = "regulator-gpio";</div><div class='del'>-		regulator-name = "ap0_sd_vccq";</div><div class='del'>-		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='del'>-		gpios = &lt;&amp;expander0 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-		states = &lt;1800000 0x1 3300000 0x0&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 {</div><div class='del'>-		compatible = "regulator-fixed";</div><div class='del'>-		regulator-name = "cp0-xhci0-vbus";</div><div class='del'>-		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='del'>-		enable-active-high;</div><div class='del'>-		gpio = &lt;&amp;expander0 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	cp0_usb3_0_phy0: cp0_usb3_phy@0 {</div><div class='del'>-		compatible = "usb-nop-xceiv";</div><div class='del'>-		vcc-supply = &lt;&amp;cp0_reg_usb3_vbus0&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {</div><div class='del'>-		compatible = "regulator-fixed";</div><div class='del'>-		regulator-name = "cp0-xhci1-vbus";</div><div class='del'>-		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='del'>-		enable-active-high;</div><div class='del'>-		gpio = &lt;&amp;expander0 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	cp0_usb3_0_phy1: cp0_usb3_phy@1 {</div><div class='del'>-		compatible = "usb-nop-xceiv";</div><div class='del'>-		vcc-supply = &lt;&amp;cp0_reg_usb3_vbus1&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	cp0_reg_sd_vccq: cp0_sd_vccq@0 {</div><div class='del'>-		compatible = "regulator-gpio";</div><div class='del'>-		regulator-name = "cp0_sd_vccq";</div><div class='del'>-		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='del'>-		gpios = &lt;&amp;expander0 15 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-		states = &lt;1800000 0x1</div><div class='del'>-			  3300000 0x0&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	cp0_reg_sd_vcc: cp0_sd_vcc@0 {</div><div class='del'>-		compatible = "regulator-fixed";</div><div class='del'>-		regulator-name = "cp0_sd_vcc";</div><div class='del'>-		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='del'>-		gpio = &lt;&amp;expander0 14 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-		enable-active-high;</div><div class='del'>-		regulator-always-on;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	cp0_sfp_eth0: sfp-eth@0 {</div><div class='del'>-		compatible = "sff,sfp";</div><div class='del'>-		i2c-bus = &lt;&amp;cp0_sfpp0_i2c&gt;;</div><div class='del'>-		los-gpio = &lt;&amp;cp0_module_expander1 11 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-		mod-def0-gpio = &lt;&amp;cp0_module_expander1 10 GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-		tx-disable-gpio = &lt;&amp;cp0_module_expander1 9 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-		tx-fault-gpio = &lt;&amp;cp0_module_expander1 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-		/*</div><div class='del'>-		 * SFP cages are unconnected on early PCBs because of an the I2C</div><div class='del'>-		 * lanes not being connected. Prevent the port for being</div><div class='del'>-		 * unusable by disabling the SFP node.</div><div class='del'>-		 */</div><div class='del'>-		status = "disabled";</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;uart0 {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-/* on-board eMMC - U9 */</div><div class='del'>-&amp;ap_sdhci0 {</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-	bus-width = &lt;8&gt;;</div><div class='del'>-	vqmmc-supply = &lt;&amp;ap0_reg_sd_vccq&gt;;</div><div class='del'>-	status = "okay";</div><div class='add'>+	model = "Marvell Armada CN9130-DB setup A";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;cp0_crypto {</div><div class='del'>-	status = "disabled";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;cp0_ethernet {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-/* SLM-1521-V2, CON9 */</div><div class='del'>-&amp;cp0_eth0 {</div><div class='del'>-	status = "disabled";</div><div class='del'>-	phy-mode = "10gbase-kr";</div><div class='del'>-	/* Generic PHY, providing serdes lanes */</div><div class='del'>-	phys = &lt;&amp;cp0_comphy4 0&gt;;</div><div class='del'>-	managed = "in-band-status";</div><div class='del'>-	sfp = &lt;&amp;cp0_sfp_eth0&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-/* CON56 */</div><div class='del'>-&amp;cp0_eth1 {</div><div class='del'>-	status = "okay";</div><div class='del'>-	phy = &lt;&amp;phy0&gt;;</div><div class='del'>-	phy-mode = "rgmii-id";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-/* CON57 */</div><div class='del'>-&amp;cp0_eth2 {</div><div class='del'>-	status = "okay";</div><div class='del'>-	phy = &lt;&amp;phy1&gt;;</div><div class='del'>-	phy-mode = "rgmii-id";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;cp0_gpio1 {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;cp0_gpio2 {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;cp0_i2c0 {</div><div class='del'>-	status = "okay";</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-	pinctrl-0 = &lt;&amp;cp0_i2c0_pins&gt;;</div><div class='del'>-	clock-frequency = &lt;100000&gt;;</div><div class='del'>-</div><div class='del'>-	/* U36 */</div><div class='del'>-	expander0: pca953x@21 {</div><div class='del'>-		compatible = "nxp,pca9555";</div><div class='del'>-		pinctrl-names = "default";</div><div class='del'>-		gpio-controller;</div><div class='del'>-		#gpio-cells = &lt;2&gt;;</div><div class='del'>-		reg = &lt;0x21&gt;;</div><div class='del'>-		status = "okay";</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	/* U42 */</div><div class='del'>-	eeprom0: eeprom@50 {</div><div class='del'>-		compatible = "atmel,24c64";</div><div class='del'>-		reg = &lt;0x50&gt;;</div><div class='del'>-		pagesize = &lt;0x20&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	/* U38 */</div><div class='del'>-	eeprom1: eeprom@57 {</div><div class='del'>-		compatible = "atmel,24c64";</div><div class='del'>-		reg = &lt;0x57&gt;;</div><div class='del'>-		pagesize = &lt;0x20&gt;;</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;cp0_i2c1 {</div><div class='del'>-	status = "okay";</div><div class='del'>-	clock-frequency = &lt;100000&gt;;</div><div class='del'>-</div><div class='del'>-	/* SLM-1521-V2 - U3 */</div><div class='del'>-	i2c-mux@72 { /* verify address - depends on dpr */</div><div class='del'>-		compatible = "nxp,pca9544";</div><div class='del'>-		#address-cells = &lt;1&gt;;</div><div class='del'>-		#size-cells = &lt;0&gt;;</div><div class='del'>-		reg = &lt;0x72&gt;;</div><div class='del'>-		cp0_sfpp0_i2c: i2c@0 {</div><div class='del'>-			#address-cells = &lt;1&gt;;</div><div class='del'>-			#size-cells = &lt;0&gt;;</div><div class='del'>-			reg = &lt;0&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		i2c@1 {</div><div class='del'>-			#address-cells = &lt;1&gt;;</div><div class='del'>-			#size-cells = &lt;0&gt;;</div><div class='del'>-			reg = &lt;1&gt;;</div><div class='del'>-			/* U12 */</div><div class='del'>-			cp0_module_expander1: pca9555@21 {</div><div class='del'>-				compatible = "nxp,pca9555";</div><div class='del'>-				pinctrl-names = "default";</div><div class='del'>-				gpio-controller;</div><div class='del'>-				#gpio-cells = &lt;2&gt;;</div><div class='del'>-				reg = &lt;0x21&gt;;</div><div class='del'>-			};</div><div class='del'>-</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;cp0_mdio {</div><div class='del'>-	status = "okay";</div><div class='del'>-</div><div class='del'>-	phy0: ethernet-phy@0 {</div><div class='del'>-		reg = &lt;0&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	phy1: ethernet-phy@1 {</div><div class='del'>-		reg = &lt;1&gt;;</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-/* U54 */</div><div class='del'>-&amp;cp0_nand_controller {</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-	pinctrl-0 = &lt;&amp;nand_pins &amp;nand_rb&gt;;</div><div class='del'>-</div><div class='del'>-	nand@0 {</div><div class='del'>-		reg = &lt;0&gt;;</div><div class='del'>-		label = "main-storage";</div><div class='del'>-		nand-rb = &lt;0&gt;;</div><div class='del'>-		nand-ecc-mode = "hw";</div><div class='del'>-		nand-on-flash-bbt;</div><div class='del'>-		nand-ecc-strength = &lt;8&gt;;</div><div class='del'>-		nand-ecc-step-size = &lt;512&gt;;</div><div class='del'>-</div><div class='del'>-		partitions {</div><div class='del'>-			compatible = "fixed-partitions";</div><div class='del'>-			#address-cells = &lt;1&gt;;</div><div class='del'>-			#size-cells = &lt;1&gt;;</div><div class='del'>-</div><div class='del'>-			partition@0 {</div><div class='del'>-				label = "U-Boot";</div><div class='del'>-				reg = &lt;0 0x200000&gt;;</div><div class='del'>-			};</div><div class='del'>-			partition@200000 {</div><div class='del'>-				label = "Linux";</div><div class='del'>-				reg = &lt;0x200000 0xd00000&gt;;</div><div class='del'>-			};</div><div class='del'>-			partition@1000000 {</div><div class='del'>-				label = "Filesystem";</div><div class='del'>-				reg = &lt;0x1000000 0x3f000000&gt;;</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-/* SLM-1521-V2, CON6 */</div><div class='del'>-&amp;cp0_pcie0 {</div><div class='del'>-	status = "okay";</div><div class='del'>-	num-lanes = &lt;4&gt;;</div><div class='del'>-	num-viewport = &lt;8&gt;;</div><div class='del'>-	/* Generic PHY, providing serdes lanes */</div><div class='del'>-	phys = &lt;&amp;cp0_comphy0 0</div><div class='del'>-		&amp;cp0_comphy1 0</div><div class='del'>-		&amp;cp0_comphy2 0</div><div class='del'>-		&amp;cp0_comphy3 0&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;cp0_sata0 {</div><div class='del'>-	status = "okay";</div><div class='del'>-</div><div class='del'>-	/* SLM-1521-V2, CON2 */</div><div class='del'>-	sata-port@1 {</div><div class='del'>-		status = "okay";</div><div class='del'>-		/* Generic PHY, providing serdes lanes */</div><div class='del'>-		phys = &lt;&amp;cp0_comphy5 1&gt;;</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-/* CON 28 */</div><div class='del'>-&amp;cp0_sdhci0 {</div><div class='del'>-	status = "okay";</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-	pinctrl-0 = &lt;&amp;cp0_sdhci_pins</div><div class='del'>-		     &amp;cp0_sdhci_cd_pins&gt;;</div><div class='del'>-	bus-width = &lt;4&gt;;</div><div class='del'>-	cd-gpios = &lt;&amp;cp0_gpio2 11 GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-	no-1-8-v;</div><div class='del'>-	vqmmc-supply = &lt;&amp;cp0_reg_sd_vccq&gt;;</div><div class='del'>-	vmmc-supply = &lt;&amp;cp0_reg_sd_vcc&gt;;</div><div class='del'>-};</div><div class='add'>+/* Setup A has SPI1 flash as a boot device, while setup B uses NAND flash.</div><div class='add'>+ * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated</div><div class='add'>+ * simultaneously. When SPI controller is enabled, NAND should be disabled.</div><div class='add'>+ */</div><div class='ctx'> </div><div class='del'>-/* U55 */</div><div class='ctx'> &amp;cp0_spi1 {</div><div class='ctx'> 	status = "okay";</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-	pinctrl-0 = &lt;&amp;cp0_spi0_pins&gt;;</div><div class='del'>-	reg = &lt;0x700680 0x50&gt;;</div><div class='del'>-</div><div class='del'>-	spi-flash@0 {</div><div class='del'>-		#address-cells = &lt;0x1&gt;;</div><div class='del'>-		#size-cells = &lt;0x1&gt;;</div><div class='del'>-		compatible = "jedec,spi-nor";</div><div class='del'>-		reg = &lt;0x0&gt;;</div><div class='del'>-		/* On-board MUX does not allow higher frequencies */</div><div class='del'>-		spi-max-frequency = &lt;40000000&gt;;</div><div class='del'>-</div><div class='del'>-		partitions {</div><div class='del'>-			compatible = "fixed-partitions";</div><div class='del'>-			#address-cells = &lt;1&gt;;</div><div class='del'>-			#size-cells = &lt;1&gt;;</div><div class='del'>-</div><div class='del'>-			partition@0 {</div><div class='del'>-				label = "U-Boot-0";</div><div class='del'>-				reg = &lt;0x0 0x200000&gt;;</div><div class='del'>-			};</div><div class='del'>-</div><div class='del'>-			partition@400000 {</div><div class='del'>-				label = "Filesystem-0";</div><div class='del'>-				reg = &lt;0x200000 0xe00000&gt;;</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;cp0_syscon0 {</div><div class='del'>-	cp0_pinctrl: pinctrl {</div><div class='del'>-		compatible = "marvell,cp115-standalone-pinctrl";</div><div class='del'>-</div><div class='del'>-		cp0_i2c0_pins: cp0-i2c-pins-0 {</div><div class='del'>-			marvell,pins = "mpp37", "mpp38";</div><div class='del'>-			marvell,function = "i2c0";</div><div class='del'>-		};</div><div class='del'>-		cp0_i2c1_pins: cp0-i2c-pins-1 {</div><div class='del'>-			marvell,pins = "mpp35", "mpp36";</div><div class='del'>-			marvell,function = "i2c1";</div><div class='del'>-		};</div><div class='del'>-		cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {</div><div class='del'>-			marvell,pins = "mpp0", "mpp1", "mpp2",</div><div class='del'>-				       "mpp3", "mpp4", "mpp5",</div><div class='del'>-				       "mpp6", "mpp7", "mpp8",</div><div class='del'>-				       "mpp9", "mpp10", "mpp11";</div><div class='del'>-			marvell,function = "ge0";</div><div class='del'>-		};</div><div class='del'>-		cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {</div><div class='del'>-			marvell,pins = "mpp44", "mpp45", "mpp46",</div><div class='del'>-				       "mpp47", "mpp48", "mpp49",</div><div class='del'>-				       "mpp50", "mpp51", "mpp52",</div><div class='del'>-				       "mpp53", "mpp54", "mpp55";</div><div class='del'>-			marvell,function = "ge1";</div><div class='del'>-		};</div><div class='del'>-		cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {</div><div class='del'>-			marvell,pins = "mpp43";</div><div class='del'>-			marvell,function = "gpio";</div><div class='del'>-		};</div><div class='del'>-		cp0_sdhci_pins: cp0-sdhi-pins-0 {</div><div class='del'>-			marvell,pins = "mpp56", "mpp57", "mpp58",</div><div class='del'>-				       "mpp59", "mpp60", "mpp61";</div><div class='del'>-			marvell,function = "sdio";</div><div class='del'>-		};</div><div class='del'>-		cp0_spi0_pins: cp0-spi-pins-0 {</div><div class='del'>-			marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";</div><div class='del'>-			marvell,function = "spi1";</div><div class='del'>-		};</div><div class='del'>-		nand_pins: nand-pins {</div><div class='del'>-			marvell,pins = "mpp15", "mpp16", "mpp17", "mpp18",</div><div class='del'>-				       "mpp19", "mpp20", "mpp21", "mpp22",</div><div class='del'>-				       "mpp23", "mpp24", "mpp25", "mpp26",</div><div class='del'>-				       "mpp27";</div><div class='del'>-			marvell,function = "dev";</div><div class='del'>-		};</div><div class='del'>-		nand_rb: nand-rb {</div><div class='del'>-			marvell,pins = "mpp13";</div><div class='del'>-			marvell,function = "nf";</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;cp0_usb3_0 {</div><div class='del'>-	status = "okay";</div><div class='del'>-	usb-phy = &lt;&amp;cp0_usb3_0_phy0&gt;;</div><div class='del'>-	phy-names = "usb";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;cp0_usb3_1 {</div><div class='del'>-	status = "okay";</div><div class='del'>-	usb-phy = &lt;&amp;cp0_usb3_0_phy1&gt;;</div><div class='del'>-	phy-names = "usb";</div><div class='del'>-};</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/cn9130-db.dtsi b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi<br/>new file mode 100644<br/>index 000000000000..3cc320f569ad<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/cn9130-db.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/cn9130-db.dtsi</a></div><div class='hunk'>@@ -0,0 +1,407 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2019 Marvell International Ltd.</div><div class='add'>+ *</div><div class='add'>+ * Device tree for the CN9130-DB board.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "cn9130.dtsi"</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		gpio1 = &amp;cp0_gpio1;</div><div class='add'>+		gpio2 = &amp;cp0_gpio2;</div><div class='add'>+		i2c0 = &amp;cp0_i2c0;</div><div class='add'>+		ethernet0 = &amp;cp0_eth0;</div><div class='add'>+		ethernet1 = &amp;cp0_eth1;</div><div class='add'>+		ethernet2 = &amp;cp0_eth2;</div><div class='add'>+		spi1 = &amp;cp0_spi0;</div><div class='add'>+		spi2 = &amp;cp0_spi1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x0 0x0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ap0_reg_sd_vccq: regulator-1 {</div><div class='add'>+		compatible = "regulator-gpio";</div><div class='add'>+		regulator-name = "ap0_sd_vccq";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpios = &lt;&amp;expander0 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		states = &lt;1800000 0x1 3300000 0x0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cp0_reg_usb3_vbus0: regulator-2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "cp0-xhci0-vbus";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;expander0 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cp0_usb3_0_phy0: usb-phy-1 {</div><div class='add'>+		compatible = "usb-nop-xceiv";</div><div class='add'>+		vcc-supply = &lt;&amp;cp0_reg_usb3_vbus0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cp0_reg_usb3_vbus1: regulator-3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "cp0-xhci1-vbus";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;expander0 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cp0_usb3_0_phy1: usb-phy-2 {</div><div class='add'>+		compatible = "usb-nop-xceiv";</div><div class='add'>+		vcc-supply = &lt;&amp;cp0_reg_usb3_vbus1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cp0_reg_sd_vccq: regulator-4 {</div><div class='add'>+		compatible = "regulator-gpio";</div><div class='add'>+		regulator-name = "cp0_sd_vccq";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpios = &lt;&amp;expander0 15 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		states = &lt;1800000 0x1</div><div class='add'>+			  3300000 0x0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cp0_reg_sd_vcc: regulator-5 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "cp0_sd_vcc";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;expander0 14 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cp0_sfp_eth0: sfp-eth-1 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;cp0_sfpp0_i2c&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;cp0_module_expander1 11 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;cp0_module_expander1 10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;cp0_module_expander1 9 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;cp0_module_expander1 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		/*</div><div class='add'>+		 * SFP cages are unconnected on early PCBs because of an the I2C</div><div class='add'>+		 * lanes not being connected. Prevent the port for being</div><div class='add'>+		 * unusable by disabling the SFP node.</div><div class='add'>+		 */</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* on-board eMMC - U9 */</div><div class='add'>+&amp;ap_sdhci0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;ap0_reg_sd_vccq&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_crypto {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_ethernet {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SLM-1521-V2, CON9 */</div><div class='add'>+&amp;cp0_eth0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	phy-mode = "10gbase-r";</div><div class='add'>+	/* Generic PHY, providing serdes lanes */</div><div class='add'>+	phys = &lt;&amp;cp0_comphy4 0&gt;;</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	sfp = &lt;&amp;cp0_sfp_eth0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* CON56 */</div><div class='add'>+&amp;cp0_eth1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	phy = &lt;&amp;phy0&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* CON57 */</div><div class='add'>+&amp;cp0_eth2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	phy = &lt;&amp;phy1&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_gpio1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_gpio2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_i2c0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp0_i2c0_pins&gt;;</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+</div><div class='add'>+	/* U36 */</div><div class='add'>+	expander0: pca953x@21 {</div><div class='add'>+		compatible = "nxp,pca9555";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		reg = &lt;0x21&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* U42 */</div><div class='add'>+	eeprom0: eeprom@50 {</div><div class='add'>+		compatible = "atmel,24c64";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		pagesize = &lt;0x20&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* U38 */</div><div class='add'>+	eeprom1: eeprom@57 {</div><div class='add'>+		compatible = "atmel,24c64";</div><div class='add'>+		reg = &lt;0x57&gt;;</div><div class='add'>+		pagesize = &lt;0x20&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_i2c1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+</div><div class='add'>+	/* SLM-1521-V2 - U3 */</div><div class='add'>+	i2c-mux@72 { /* verify address - depends on dpr */</div><div class='add'>+		compatible = "nxp,pca9544";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		reg = &lt;0x72&gt;;</div><div class='add'>+		cp0_sfpp0_i2c: i2c@0 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@1 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			/* U12 */</div><div class='add'>+			cp0_module_expander1: pca9555@21 {</div><div class='add'>+				compatible = "nxp,pca9555";</div><div class='add'>+				gpio-controller;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x21&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_mdio {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	phy0: ethernet-phy@0 {</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	phy1: ethernet-phy@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* U54 */</div><div class='add'>+&amp;cp0_nand_controller {</div><div class='add'>+	status = "disabled";</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;nand_pins &amp;nand_rb&gt;;</div><div class='add'>+</div><div class='add'>+	nand@0 {</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		label = "main-storage";</div><div class='add'>+		nand-rb = &lt;0&gt;;</div><div class='add'>+		nand-ecc-mode = "hw";</div><div class='add'>+		nand-on-flash-bbt;</div><div class='add'>+		nand-ecc-strength = &lt;8&gt;;</div><div class='add'>+		nand-ecc-step-size = &lt;512&gt;;</div><div class='add'>+</div><div class='add'>+		partitions {</div><div class='add'>+			compatible = "fixed-partitions";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			partition@0 {</div><div class='add'>+				label = "U-Boot";</div><div class='add'>+				reg = &lt;0 0x200000&gt;;</div><div class='add'>+			};</div><div class='add'>+			partition@200000 {</div><div class='add'>+				label = "Linux";</div><div class='add'>+				reg = &lt;0x200000 0xe00000&gt;;</div><div class='add'>+			};</div><div class='add'>+			partition@1000000 {</div><div class='add'>+				label = "Filesystem";</div><div class='add'>+				reg = &lt;0x1000000 0x3f000000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SLM-1521-V2, CON6 */</div><div class='add'>+&amp;cp0_pcie0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	num-lanes = &lt;4&gt;;</div><div class='add'>+	num-viewport = &lt;8&gt;;</div><div class='add'>+	/* Generic PHY, providing serdes lanes */</div><div class='add'>+	phys = &lt;&amp;cp0_comphy0 0</div><div class='add'>+		&amp;cp0_comphy1 0</div><div class='add'>+		&amp;cp0_comphy2 0</div><div class='add'>+		&amp;cp0_comphy3 0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_sata0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* SLM-1521-V2, CON2 */</div><div class='add'>+	sata-port@1 {</div><div class='add'>+		status = "okay";</div><div class='add'>+		/* Generic PHY, providing serdes lanes */</div><div class='add'>+		phys = &lt;&amp;cp0_comphy5 1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* CON 28 */</div><div class='add'>+&amp;cp0_sdhci0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp0_sdhci_pins</div><div class='add'>+		     &amp;cp0_sdhci_cd_pins&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;cp0_gpio2 11 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	no-1-8-v;</div><div class='add'>+	vqmmc-supply = &lt;&amp;cp0_reg_sd_vccq&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;cp0_reg_sd_vcc&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* U55 */</div><div class='add'>+&amp;cp0_spi1 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp0_spi1_pins&gt;;</div><div class='add'>+	reg = &lt;0x700680 0x50&gt;;</div><div class='add'>+</div><div class='add'>+	flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0x0&gt;;</div><div class='add'>+		/* On-board MUX does not allow higher frequencies */</div><div class='add'>+		spi-max-frequency = &lt;40000000&gt;;</div><div class='add'>+</div><div class='add'>+		partitions {</div><div class='add'>+			compatible = "fixed-partitions";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			partition@0 {</div><div class='add'>+				label = "U-Boot-0";</div><div class='add'>+				reg = &lt;0x0 0x200000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			partition@400000 {</div><div class='add'>+				label = "Filesystem-0";</div><div class='add'>+				reg = &lt;0x200000 0xe00000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_syscon0 {</div><div class='add'>+	cp0_pinctrl: pinctrl {</div><div class='add'>+		compatible = "marvell,cp115-standalone-pinctrl";</div><div class='add'>+</div><div class='add'>+		cp0_i2c0_pins: cp0-i2c-pins-0 {</div><div class='add'>+			marvell,pins = "mpp37", "mpp38";</div><div class='add'>+			marvell,function = "i2c0";</div><div class='add'>+		};</div><div class='add'>+		cp0_i2c1_pins: cp0-i2c-pins-1 {</div><div class='add'>+			marvell,pins = "mpp35", "mpp36";</div><div class='add'>+			marvell,function = "i2c1";</div><div class='add'>+		};</div><div class='add'>+		cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {</div><div class='add'>+			marvell,pins = "mpp0", "mpp1", "mpp2",</div><div class='add'>+				       "mpp3", "mpp4", "mpp5",</div><div class='add'>+				       "mpp6", "mpp7", "mpp8",</div><div class='add'>+				       "mpp9", "mpp10", "mpp11";</div><div class='add'>+			marvell,function = "ge0";</div><div class='add'>+		};</div><div class='add'>+		cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {</div><div class='add'>+			marvell,pins = "mpp44", "mpp45", "mpp46",</div><div class='add'>+				       "mpp47", "mpp48", "mpp49",</div><div class='add'>+				       "mpp50", "mpp51", "mpp52",</div><div class='add'>+				       "mpp53", "mpp54", "mpp55";</div><div class='add'>+			marvell,function = "ge1";</div><div class='add'>+		};</div><div class='add'>+		cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {</div><div class='add'>+			marvell,pins = "mpp43";</div><div class='add'>+			marvell,function = "gpio";</div><div class='add'>+		};</div><div class='add'>+		cp0_sdhci_pins: cp0-sdhi-pins-0 {</div><div class='add'>+			marvell,pins = "mpp56", "mpp57", "mpp58",</div><div class='add'>+				       "mpp59", "mpp60", "mpp61";</div><div class='add'>+			marvell,function = "sdio";</div><div class='add'>+		};</div><div class='add'>+		cp0_spi1_pins: cp0-spi-pins-1 {</div><div class='add'>+			marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";</div><div class='add'>+			marvell,function = "spi1";</div><div class='add'>+		};</div><div class='add'>+		nand_pins: nand-pins {</div><div class='add'>+			marvell,pins = "mpp15", "mpp16", "mpp17", "mpp18",</div><div class='add'>+				       "mpp19", "mpp20", "mpp21", "mpp22",</div><div class='add'>+				       "mpp23", "mpp24", "mpp25", "mpp26",</div><div class='add'>+				       "mpp27";</div><div class='add'>+			marvell,function = "dev";</div><div class='add'>+		};</div><div class='add'>+		nand_rb: nand-rb-pins {</div><div class='add'>+			marvell,pins = "mpp13";</div><div class='add'>+			marvell,function = "nf";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_utmi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_usb3_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	usb-phy = &lt;&amp;cp0_usb3_0_phy0&gt;;</div><div class='add'>+	phys = &lt;&amp;cp0_utmi0&gt;;</div><div class='add'>+	phy-names = "utmi";</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_usb3_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	usb-phy = &lt;&amp;cp0_usb3_0_phy1&gt;;</div><div class='add'>+	phys = &lt;&amp;cp0_utmi1&gt;;</div><div class='add'>+	phy-names = "utmi";</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/cn9130-sr-som.dtsi b/arch/arm64/boot/dts/marvell/cn9130-sr-som.dtsi<br/>new file mode 100644<br/>index 000000000000..f95202decfce<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/cn9130-sr-som.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/cn9130-sr-som.dtsi</a></div><div class='hunk'>@@ -0,0 +1,159 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2024 Josua Mayer &lt;josua@solid-run.com&gt;</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;cp0_eth0;</div><div class='add'>+		ethernet1 = &amp;cp0_eth1;</div><div class='add'>+		ethernet2 = &amp;cp0_eth2;</div><div class='add'>+		i2c0 = &amp;cp0_i2c0;</div><div class='add'>+		mmc0 = &amp;ap_sdhci0;</div><div class='add'>+		rtc0 = &amp;cp0_rtc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	v_1_8: regulator-1-8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "1v8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* requires assembly of R9307 */</div><div class='add'>+	vhv: regulator-vhv-1-8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vhv-1v8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;cp0_reg_vhv_pins&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		gpios = &lt;&amp;cp0_gpio2 9 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ap_pinctrl {</div><div class='add'>+	ap_mmc0_pins: ap-mmc0-pins {</div><div class='add'>+		marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", "mpp4", "mpp5",</div><div class='add'>+					   "mpp6", "mpp7", "mpp8", "mpp9", "mpp10", "mpp12";</div><div class='add'>+		marvell,function = "sdio";</div><div class='add'>+		/*</div><div class='add'>+		 * mpp12 is emmc reset, function should be sdio (hw_rst),</div><div class='add'>+		 * but pinctrl-mvebu does not support this.</div><div class='add'>+		 *</div><div class='add'>+		 * From pinctrl-mvebu.h:</div><div class='add'>+		 * "The name will be used to switch to this setting in DT description, e.g.</div><div class='add'>+		 * marvell,function = "uart2". subname is only for debugging purposes."</div><div class='add'>+		 */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ap_sdhci0 {</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;ap_mmc0_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	vqmmc-supply = &lt;&amp;v_1_8&gt;;</div><div class='add'>+	no-sdio;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_ethernet {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* for assembly with phy */</div><div class='add'>+&amp;cp0_eth2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp0_eth2_pins&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy = &lt;&amp;cp0_eth2_phy&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_i2c0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp0_i2c0_pins&gt;;</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	som_eeprom: eeprom@53 {</div><div class='add'>+		compatible = "atmel,24c02";</div><div class='add'>+		reg = &lt;0x53&gt;;</div><div class='add'>+		pagesize = &lt;8&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_mdio {</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp0_mdio_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* assembly option */</div><div class='add'>+	cp0_eth2_phy: ethernet-phy@0 {</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_spi1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp0_spi1_pins&gt;;</div><div class='add'>+	/* max speed limited by a mux */</div><div class='add'>+	spi-max-frequency = &lt;1800000000&gt;;</div><div class='add'>+</div><div class='add'>+	flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		/* read command supports max. 50MHz */</div><div class='add'>+		spi-max-frequency = &lt;50000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_syscon0 {</div><div class='add'>+	cp0_pinctrl: pinctrl {</div><div class='add'>+		compatible = "marvell,cp115-standalone-pinctrl";</div><div class='add'>+</div><div class='add'>+		cp0_eth2_pins: cp0-ge2-rgmii-pins {</div><div class='add'>+			marvell,pins = "mpp44", "mpp45", "mpp46", "mpp47",</div><div class='add'>+				       "mpp48", "mpp49", "mpp50", "mpp51",</div><div class='add'>+				       "mpp52", "mpp53", "mpp54", "mpp55";</div><div class='add'>+			/* docs call it "ge2", but cp110-pinctrl "ge1" */</div><div class='add'>+			marvell,function = "ge1";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp0_i2c0_pins: cp0-i2c0-pins {</div><div class='add'>+			marvell,pins = "mpp37", "mpp38";</div><div class='add'>+			marvell,function = "i2c0";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp0_mdio_pins: cp0-mdio-pins {</div><div class='add'>+			marvell,pins = "mpp0", "mpp1";</div><div class='add'>+			marvell,function = "ge";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp0_spi1_pins: cp0-spi1-pins {</div><div class='add'>+			marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";</div><div class='add'>+			marvell,function = "spi1";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp0_reg_vhv_pins: cp0-reg-vhv-pins {</div><div class='add'>+			marvell,pins = "mpp41";</div><div class='add'>+			marvell,function = "gpio";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* AP default console */</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart0_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/cn9130.dtsi b/arch/arm64/boot/dts/marvell/cn9130.dtsi<br/>index a2b7e5ec979d..327b04134134 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/cn9130.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/cn9130.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/cn9130.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/cn9130.dtsi</a></div><div class='hunk'>@@ -11,6 +11,13 @@</div><div class='ctx'> 	model = "Marvell Armada CN9130 SoC";</div><div class='ctx'> 	compatible = "marvell,cn9130", "marvell,armada-ap807-quad",</div><div class='ctx'> 		     "marvell,armada-ap807";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		gpio1 = &amp;cp0_gpio1;</div><div class='add'>+		gpio2 = &amp;cp0_gpio2;</div><div class='add'>+		spi1 = &amp;cp0_spi0;</div><div class='add'>+		spi2 = &amp;cp0_spi1;</div><div class='add'>+	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -35,3 +42,11 @@</div><div class='ctx'> #undef CP11X_PCIE0_BASE</div><div class='ctx'> #undef CP11X_PCIE1_BASE</div><div class='ctx'> #undef CP11X_PCIE2_BASE</div><div class='add'>+</div><div class='add'>+&amp;cp0_gpio1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_gpio2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts b/arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts<br/>new file mode 100644<br/>index 000000000000..338853d3b179<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts</a></div><div class='hunk'>@@ -0,0 +1,639 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2024 Josua Mayer &lt;josua@solid-run.com&gt;</div><div class='add'>+ *</div><div class='add'>+ * DTS for SolidRun CN9130 Clearfog Base.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+#include "cn9130.dtsi"</div><div class='add'>+#include "cn9130-sr-som.dtsi"</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Instantiate the external CP115</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#define CP11X_NAME		cp1</div><div class='add'>+#define CP11X_BASE		f4000000</div><div class='add'>+#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))</div><div class='add'>+#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000</div><div class='add'>+#define CP11X_PCIE0_BASE	f4600000</div><div class='add'>+#define CP11X_PCIE1_BASE	f4620000</div><div class='add'>+#define CP11X_PCIE2_BASE	f4640000</div><div class='add'>+</div><div class='add'>+#include "armada-cp115.dtsi"</div><div class='add'>+</div><div class='add'>+#undef CP11X_NAME</div><div class='add'>+#undef CP11X_BASE</div><div class='add'>+#undef CP11X_PCIEx_MEM_BASE</div><div class='add'>+#undef CP11X_PCIEx_MEM_SIZE</div><div class='add'>+#undef CP11X_PCIE0_BASE</div><div class='add'>+#undef CP11X_PCIE1_BASE</div><div class='add'>+#undef CP11X_PCIE2_BASE</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "SolidRun CN9131 SolidWAN";</div><div class='add'>+	compatible = "solidrun,cn9131-solidwan",</div><div class='add'>+		     "solidrun,cn9130-sr-som", "marvell,cn9130";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;cp1_eth1;</div><div class='add'>+		ethernet1 = &amp;cp1_eth2;</div><div class='add'>+		ethernet2 = &amp;cp0_eth1;</div><div class='add'>+		ethernet3 = &amp;cp0_eth2;</div><div class='add'>+		ethernet4 = &amp;cp0_eth0;</div><div class='add'>+		ethernet5 = &amp;cp1_eth0;</div><div class='add'>+		gpio0 = &amp;ap_gpio;</div><div class='add'>+		gpio1 = &amp;cp0_gpio1;</div><div class='add'>+		gpio2 = &amp;cp0_gpio2;</div><div class='add'>+		gpio3 = &amp;cp1_gpio1;</div><div class='add'>+		gpio4 = &amp;cp1_gpio2;</div><div class='add'>+		gpio5 = &amp;expander0;</div><div class='add'>+		i2c0 = &amp;cp0_i2c0;</div><div class='add'>+		i2c1 = &amp;cp0_i2c1;</div><div class='add'>+		i2c2 = &amp;cp1_i2c1;</div><div class='add'>+		mmc0 = &amp;ap_sdhci0;</div><div class='add'>+		mmc1 = &amp;cp0_sdhci0;</div><div class='add'>+		rtc0 = &amp;cp0_rtc;</div><div class='add'>+		rtc1 = &amp;carrier_rtc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;cp0_led_pins &amp;cp1_led_pins&gt;;</div><div class='add'>+</div><div class='add'>+		/* for sfp-1 (J42) */</div><div class='add'>+		led-sfp1-activity {</div><div class='add'>+			label = "sfp1:green";</div><div class='add'>+			gpios = &lt;&amp;cp0_gpio1 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* for sfp-1 (J42) */</div><div class='add'>+		led-sfp1-link {</div><div class='add'>+			label = "sfp1:yellow";</div><div class='add'>+			gpios = &lt;&amp;cp0_gpio1 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* (J28) */</div><div class='add'>+		led-sfp0-activity {</div><div class='add'>+			label = "sfp0:green";</div><div class='add'>+			gpios = &lt;&amp;cp1_gpio2 22 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* (J28) */</div><div class='add'>+		led-sfp0-link {</div><div class='add'>+			label = "sfp0:yellow";</div><div class='add'>+			gpios = &lt;&amp;cp1_gpio2 23 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Type-A port on J53 */</div><div class='add'>+	reg_usb_a_vbus0: regulator-usb-a-vbus0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-0 = &lt;&amp;cp0_reg_usb_a_vbus0_pins&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		regulator-name = "vbus0";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		gpios = &lt;&amp;cp0_gpio1 27 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_usb_a_vbus1: regulator-usb-a-vbus1 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-0 = &lt;&amp;cp0_reg_usb_a_vbus1_pins&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		regulator-name = "vbus1";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		gpios = &lt;&amp;cp0_gpio1 28 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp0: sfp-0 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		pinctrl-0 = &lt;&amp;cp0_sfp0_pins&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		i2c-bus = &lt;&amp;cp0_i2c1&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;cp0_gpio2 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;cp0_gpio2 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;cp0_gpio2 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;cp0_gpio1 31 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		maximum-power-milliwatt = &lt;2000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp1: sfp-1 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		pinctrl-0 = &lt;&amp;cp1_sfp1_pins&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		i2c-bus = &lt;&amp;cp1_i2c1&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;cp1_gpio2 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;cp1_gpio2 18 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;cp1_gpio2 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;cp1_gpio2 17 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		maximum-power-milliwatt = &lt;2000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_ethernet {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SRDS #2 - SFP+ 10GE */</div><div class='add'>+&amp;cp0_eth0 {</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	phy-mode = "10gbase-r";</div><div class='add'>+	phys = &lt;&amp;cp0_comphy2 0&gt;;</div><div class='add'>+	sfp = &lt;&amp;sfp0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SRDS #3 - SGMII 1GE */</div><div class='add'>+&amp;cp0_eth1 {</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	phy-mode = "sgmii";</div><div class='add'>+	/* Without mdio phy access rely on sgmii auto-negotiation. */</div><div class='add'>+	phys = &lt;&amp;cp0_comphy3 1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SRDS #1 - SGMII */</div><div class='add'>+&amp;cp0_eth2 {</div><div class='add'>+	/delete-property/ pinctrl-0;</div><div class='add'>+	/delete-property/ pinctrl-names;</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	phy-mode = "sgmii";</div><div class='add'>+	phy = &lt;&amp;cp0_phy1&gt;;</div><div class='add'>+	phys = &lt;&amp;cp0_comphy1 2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_gpio1 {</div><div class='add'>+	pcie0-0-w-disable-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		output-low;</div><div class='add'>+		line-name = "pcie0.0-w-disable";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* J34 */</div><div class='add'>+	m2-full-card-power-off-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;8 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		output-low;</div><div class='add'>+		line-name = "m2-full-card-power-off";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_i2c0 {</div><div class='add'>+	/* assembly option */</div><div class='add'>+	fan-controller@18 {</div><div class='add'>+		compatible = "ti,amc6821";</div><div class='add'>+		reg = &lt;0x18&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	expander0: gpio@41 {</div><div class='add'>+		compatible = "nxp,pca9536";</div><div class='add'>+		reg = &lt;0x41&gt;;</div><div class='add'>+</div><div class='add'>+		usb-a-vbus0-ilimit-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			input;</div><div class='add'>+			line-name = "vbus0-ilimit";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* duplicate connection, controlled by soc gpio */</div><div class='add'>+		usb-vbus0-enable-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			input;</div><div class='add'>+			line-name = "vbus0-enable";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb-a-vbus1-ilimit-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			input;</div><div class='add'>+			line-name = "vbus1-ilimit";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* duplicate connection, controlled by soc gpio */</div><div class='add'>+		usb-vbus1-enable-hog {</div><div class='add'>+			gpio-hog;</div><div class='add'>+			gpios = &lt;3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			input;</div><div class='add'>+			line-name = "vbus1-enable";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	carrier_eeprom: eeprom@52 {</div><div class='add'>+		compatible = "atmel,24c02";</div><div class='add'>+		reg = &lt;0x52&gt;;</div><div class='add'>+		pagesize = &lt;8&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* usb-hub@60 */</div><div class='add'>+</div><div class='add'>+	/* assembly option */</div><div class='add'>+	carrier_rtc: rtc@68 {</div><div class='add'>+		compatible = "st,m41t83";</div><div class='add'>+		reg = &lt;0x68&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;cp1_rtc_pins&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		interrupt-parent = &lt;&amp;cp1_gpio1&gt;;</div><div class='add'>+		interrupts = &lt;12 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;cp1_gpio1 13 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_i2c1 {</div><div class='add'>+	/*</div><div class='add'>+	 * Routed to SFP.</div><div class='add'>+	 * Limit to 100kHz for compatibility with SFP modules,</div><div class='add'>+	 * featuring AT24C01A/02/04 at addresses 0x50/0x51.</div><div class='add'>+	 */</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp0_i2c1_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_mdio {</div><div class='add'>+	/*</div><div class='add'>+	 * SoM + Carrier each have a PHY at address 0.</div><div class='add'>+	 * Remove the SoM phy node, and skip adding the carrier node.</div><div class='add'>+	 * SGMII Auto-Negotation is enabled by bootloader for</div><div class='add'>+	 * autonomous operation without mdio control.</div><div class='add'>+	 */</div><div class='add'>+	/delete-node/ ethernet-phy@0;</div><div class='add'>+</div><div class='add'>+	/* U17016 */</div><div class='add'>+	cp0_phy1: ethernet-phy@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		/*</div><div class='add'>+		 * Configure LEDs default behaviour:</div><div class='add'>+		 * - LED[0]: link is 1000Mbps: On (yellow)</div><div class='add'>+		 * - LED[1]: link/activity: On/blink (green)</div><div class='add'>+		 * - LED[2]: high impedance (floating)</div><div class='add'>+		 */</div><div class='add'>+		marvell,reg-init = &lt;3 16 0xf000 0x0a17&gt;;</div><div class='add'>+</div><div class='add'>+		leds {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			led@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				color = &lt;LED_COLOR_ID_YELLOW&gt;;</div><div class='add'>+				function = LED_FUNCTION_LAN;</div><div class='add'>+				default-state = "keep";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			led@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+				function = LED_FUNCTION_LAN;</div><div class='add'>+				default-state = "keep";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SRDS #0 - miniPCIe */</div><div class='add'>+&amp;cp0_pcie0 {</div><div class='add'>+	num-lanes = &lt;1&gt;;</div><div class='add'>+	phys = &lt;&amp;cp0_comphy0 0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SRDS #5 - M.2 B-Key (J34) */</div><div class='add'>+&amp;cp0_pcie2 {</div><div class='add'>+	num-lanes = &lt;1&gt;;</div><div class='add'>+	phys = &lt;&amp;cp0_comphy5 2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_pinctrl {</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp0_m2_0_shutdown_pins &amp;cp0_mpcie_rfkill_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	cp0_i2c1_pins: cp0-i2c1-pins {</div><div class='add'>+		marvell,pins = "mpp35", "mpp36";</div><div class='add'>+		marvell,function = "i2c1";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cp0_led_pins: cp0-led-pins {</div><div class='add'>+		marvell,pins = "mpp4", "mpp7";</div><div class='add'>+		marvell,function = "gpio";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cp0_m2_0_shutdown_pins: cp0-m2-0-shutdown-pins {</div><div class='add'>+		marvell,pins = "mpp8";</div><div class='add'>+		marvell,function = "gpio";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cp0_mmc0_pins: cp0-mmc0-pins {</div><div class='add'>+		marvell,pins = "mpp43", "mpp56", "mpp57", "mpp58",</div><div class='add'>+			       "mpp59", "mpp60", "mpp61";</div><div class='add'>+		marvell,function = "sdio";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cp0_mpcie_rfkill_pins: cp0-mpcie-rfkill-pins {</div><div class='add'>+		marvell,pins = "mpp6";</div><div class='add'>+		marvell,function = "gpio";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cp0_reg_usb_a_vbus0_pins: cp0-reg-usb-a-vbus0-pins {</div><div class='add'>+		marvell,pins = "mpp27";</div><div class='add'>+		marvell,function = "gpio";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cp0_reg_usb_a_vbus1_pins: cp0-reg-usb-a-vbus1-pins {</div><div class='add'>+		marvell,pins = "mpp28";</div><div class='add'>+		marvell,function = "gpio";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cp0_sfp0_pins: cp0-sfp0-pins {</div><div class='add'>+		marvell,pins = "mpp31", "mpp32", "mpp33", "mpp34";</div><div class='add'>+		marvell,function = "gpio";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cp0_spi1_cs1_pins: cp0-spi1-cs1-pins {</div><div class='add'>+		marvell,pins = "mpp12";</div><div class='add'>+		marvell,function = "spi1";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* microSD */</div><div class='add'>+&amp;cp0_sdhci0 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp0_mmc0_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	no-1-8-v;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_spi1 {</div><div class='add'>+	/* add pin for chip-select 1 */</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp0_spi1_pins &amp;cp0_spi1_cs1_pins&gt;;</div><div class='add'>+</div><div class='add'>+	flash@1 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		/* read command supports max. 50MHz */</div><div class='add'>+		spi-max-frequency = &lt;50000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB-2.0 Host to USB-Hub */</div><div class='add'>+&amp;cp0_usb3_0 {</div><div class='add'>+	phys = &lt;&amp;cp0_utmi0&gt;;</div><div class='add'>+	phy-names = "utmi";</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SRDS #4 - USB-3.0 Host to USB-Hub */</div><div class='add'>+&amp;cp0_usb3_1 {</div><div class='add'>+	phys = &lt;&amp;cp0_comphy4 1&gt;, &lt;&amp;cp0_utmi1&gt;;</div><div class='add'>+	phy-names = "comphy", "utmi";</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_utmi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_utmi1 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp1_ethernet {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SRDS #4 - SFP+ 10GE */</div><div class='add'>+&amp;cp1_eth0 {</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	phy-mode = "10gbase-r";</div><div class='add'>+	phys = &lt;&amp;cp1_comphy4 0&gt;;</div><div class='add'>+	sfp = &lt;&amp;sfp1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SRDS #3 - SGMII 1GE */</div><div class='add'>+&amp;cp1_eth1 {</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	phy-mode = "sgmii";</div><div class='add'>+	phy = &lt;&amp;cp1_phy0&gt;;</div><div class='add'>+	phys = &lt;&amp;cp1_comphy3 1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SRDS #5 - SGMII 1GE */</div><div class='add'>+&amp;cp1_eth2 {</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	phy-mode = "sgmii";</div><div class='add'>+	phy = &lt;&amp;cp1_phy1&gt;;</div><div class='add'>+	phys = &lt;&amp;cp1_comphy5 2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp1_gpio1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* J30 */</div><div class='add'>+	m2-full-card-power-off-hog-0 {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;29 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		output-low;</div><div class='add'>+		line-name = "m2-full-card-power-off";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* J44 */</div><div class='add'>+	m2-full-card-power-off-hog-1 {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;30 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		output-low;</div><div class='add'>+		line-name = "m2-full-card-power-off";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp1_gpio2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp1_i2c1 {</div><div class='add'>+	/*</div><div class='add'>+	 * Routed to SFP.</div><div class='add'>+	 * Limit to 100kHz for compatibility with SFP modules,</div><div class='add'>+	 * featuring AT24C01A/02/04 at addresses 0x50/0x51.</div><div class='add'>+	 */</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp1_i2c1_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp1_mdio {</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp1_mdio_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	cp1_phy0: ethernet-phy@0 {</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		/*</div><div class='add'>+		 * Configure LEDs default behaviour:</div><div class='add'>+		 * - LED[0]: link is 1000Mbps: On (yellow)</div><div class='add'>+		 * - LED[1]: link/activity: On/blink (green)</div><div class='add'>+		 * - LED[2]: high impedance (floating)</div><div class='add'>+		 */</div><div class='add'>+		marvell,reg-init = &lt;3 16 0xf000 0x0a17&gt;;</div><div class='add'>+</div><div class='add'>+		leds {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			led@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				color = &lt;LED_COLOR_ID_YELLOW&gt;;</div><div class='add'>+				function = LED_FUNCTION_LAN;</div><div class='add'>+				default-state = "keep";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			led@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+				function = LED_FUNCTION_LAN;</div><div class='add'>+				default-state = "keep";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cp1_phy1: ethernet-phy@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		/*</div><div class='add'>+		 * Configure LEDs default behaviour:</div><div class='add'>+		 * - LED[0]: link is 1000Mbps: On (yellow)</div><div class='add'>+		 * - LED[1]: link/activity: On/blink (green)</div><div class='add'>+		 * - LED[2]: high impedance (floating)</div><div class='add'>+		 */</div><div class='add'>+		marvell,reg-init = &lt;3 16 0xf000 0x0a17&gt;;</div><div class='add'>+</div><div class='add'>+		leds {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			led@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				color = &lt;LED_COLOR_ID_YELLOW&gt;;</div><div class='add'>+				function = LED_FUNCTION_LAN;</div><div class='add'>+				default-state = "keep";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			led@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+				function = LED_FUNCTION_LAN;</div><div class='add'>+				default-state = "keep";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SRDS #0 - M.2 (J30) */</div><div class='add'>+&amp;cp1_pcie0 {</div><div class='add'>+	num-lanes = &lt;1&gt;;</div><div class='add'>+	phys = &lt;&amp;cp1_comphy0 0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp1_rtc {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SRDS #1 - SATA on M.2 (J44) */</div><div class='add'>+&amp;cp1_sata0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* only port 0 is available */</div><div class='add'>+	sata-port@0 {</div><div class='add'>+		phys = &lt;&amp;cp1_comphy1 0&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp1_syscon0 {</div><div class='add'>+	cp1_pinctrl: pinctrl {</div><div class='add'>+		compatible = "marvell,cp115-standalone-pinctrl";</div><div class='add'>+		pinctrl-0 = &lt;&amp;cp1_m2_1_shutdown_pins &amp;cp1_m2_2_shutdown_pins&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		cp1_i2c1_pins: cp0-i2c1-pins {</div><div class='add'>+			marvell,pins = "mpp35", "mpp36";</div><div class='add'>+			marvell,function = "i2c1";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp1_led_pins: cp1-led-pins {</div><div class='add'>+			marvell,pins = "mpp54", "mpp55";</div><div class='add'>+			marvell,function = "gpio";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp1_m2_1_shutdown_pins: cp1-m2-1-shutdown-pins {</div><div class='add'>+			marvell,pins = "mpp29";</div><div class='add'>+			marvell,function = "gpio";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp1_m2_2_shutdown_pins: cp1-m2-2-shutdown-pins {</div><div class='add'>+			marvell,pins = "mpp30";</div><div class='add'>+			marvell,function = "gpio";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp1_mdio_pins: cp1-mdio-pins {</div><div class='add'>+			marvell,pins = "mpp37", "mpp38";</div><div class='add'>+			marvell,function = "ge";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp1_rtc_pins: cp1-rtc-pins {</div><div class='add'>+			marvell,pins = "mpp12", "mpp13";</div><div class='add'>+			marvell,function = "gpio";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp1_sfp1_pins: cp1-sfp1-pins {</div><div class='add'>+			marvell,pins = "mpp33", "mpp34", "mpp49", "mpp50";</div><div class='add'>+			marvell,function = "gpio";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * SRDS #2 - USB-3.0 Host to M.2 (J44)</div><div class='add'>+ * USB-2.0 Host to M.2 (J30)</div><div class='add'>+ */</div><div class='add'>+&amp;cp1_usb3_0 {</div><div class='add'>+	phys = &lt;&amp;cp1_comphy2 0&gt;, &lt;&amp;cp1_utmi0&gt;;</div><div class='add'>+	phy-names = "comphy", "utmi";</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB-2.0 Host to M.2 (J44) */</div><div class='add'>+&amp;cp1_usb3_1 {</div><div class='add'>+	phys = &lt;&amp;cp1_utmi1&gt;;</div><div class='add'>+	phy-names = "utmi";</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp1_utmi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/cn9131-db-B.dts b/arch/arm64/boot/dts/marvell/cn9131-db-B.dts<br/>new file mode 100644<br/>index 000000000000..183b1ec8b1f0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/cn9131-db-B.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/cn9131-db-B.dts</a></div><div class='hunk'>@@ -0,0 +1,22 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2020 Marvell International Ltd.</div><div class='add'>+ *</div><div class='add'>+ * Device tree for the CN9131-DB board (setup "B").</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "cn9131-db.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Marvell Armada CN9131-DB setup B";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Setup B has NAND flash as a boot device, while regular setup uses SPI flash.</div><div class='add'>+ * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated</div><div class='add'>+ * simultaneously. When NAND controller is enabled, SPI1 should be disabled.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;cp0_nand_controller {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi b/arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi<br/>new file mode 100644<br/>index 000000000000..6f3914bcfd01<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi</a></div><div class='hunk'>@@ -0,0 +1,108 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2023 Marvell International Ltd.</div><div class='add'>+ *</div><div class='add'>+ * Device tree for the CN9131-DB Com Express CPU module board.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "cn9131-db.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Marvell Armada CN9131-DB COM EXPRESS type 7 CPU module board";</div><div class='add'>+	compatible = "marvell,cn9131-cpu-module", "marvell,cn9131", "marvell,cn9130",</div><div class='add'>+		     "marvell,armada-ap807-quad", "marvell,armada-ap807";</div><div class='add'>+</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ap0_reg_sd_vccq {</div><div class='add'>+	regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	states = &lt;1800000 0x1 1800000 0x0&gt;;</div><div class='add'>+	/delete-property/ gpios;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_reg_usb3_vbus0 {</div><div class='add'>+	/delete-property/ gpio;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_reg_usb3_vbus1 {</div><div class='add'>+	/delete-property/ gpio;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp1_reg_usb3_vbus0 {</div><div class='add'>+	/delete-property/ gpio;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_reg_sd_vcc {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_reg_sd_vccq {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_sdhci0 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_eth0 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_eth1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	phy = &lt;&amp;phy0&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_eth2 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_mdio {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp0_ge_mdio_pins&gt;;</div><div class='add'>+	phy0: ethernet-phy@0 {</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_syscon0 {</div><div class='add'>+	cp0_pinctrl: pinctrl {</div><div class='add'>+		compatible = "marvell,cp115-standalone-pinctrl";</div><div class='add'>+</div><div class='add'>+		cp0_ge_mdio_pins: ge-mdio-pins {</div><div class='add'>+			marvell,pins = "mpp40", "mpp41";</div><div class='add'>+			marvell,function = "ge";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_sdhci0 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_spi1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_usb3_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	usb-phy = &lt;&amp;cp0_usb3_0_phy0&gt;;</div><div class='add'>+	phy-names = "usb";</div><div class='add'>+	/delete-property/ phys;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_usb3_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	usb-phy = &lt;&amp;cp0_usb3_0_phy1&gt;;</div><div class='add'>+	phy-names = "usb";</div><div class='add'>+	/delete-property/ phys;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp1_usb3_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	usb-phy = &lt;&amp;cp1_usb3_0_phy0&gt;;</div><div class='add'>+	/* Generic PHY, providing serdes lanes */</div><div class='add'>+	phys = &lt;&amp;cp1_comphy3 1&gt;;</div><div class='add'>+	phy-names = "usb";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/cn9131-db.dts b/arch/arm64/boot/dts/marvell/cn9131-db.dts<br/>index 3c975f98b2a3..a60fdee79bf8 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/cn9131-db.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/cn9131-db.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/cn9131-db.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/cn9131-db.dts</a></div><div class='hunk'>@@ -5,198 +5,18 @@</div><div class='ctx'>  * Device tree for the CN9131-DB board.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-#include "cn9130-db.dts"</div><div class='add'>+#include "cn9131-db.dtsi"</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='del'>-	model = "Marvell Armada CN9131-DB";</div><div class='del'>-	compatible = "marvell,cn9131", "marvell,cn9130",</div><div class='del'>-		     "marvell,armada-ap807-quad", "marvell,armada-ap807";</div><div class='del'>-</div><div class='del'>-	aliases {</div><div class='del'>-		gpio3 = &amp;cp1_gpio1;</div><div class='del'>-		gpio4 = &amp;cp1_gpio2;</div><div class='del'>-		ethernet3 = &amp;cp1_eth0;</div><div class='del'>-		ethernet4 = &amp;cp1_eth1;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	cp1_reg_usb3_vbus0: cp1_usb3_vbus@0 {</div><div class='del'>-		compatible = "regulator-fixed";</div><div class='del'>-		pinctrl-names = "default";</div><div class='del'>-		pinctrl-0 = &lt;&amp;cp1_xhci0_vbus_pins&gt;;</div><div class='del'>-		regulator-name = "cp1-xhci0-vbus";</div><div class='del'>-		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='del'>-		enable-active-high;</div><div class='del'>-		gpio = &lt;&amp;cp1_gpio1 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	cp1_usb3_0_phy0: cp1_usb3_phy0 {</div><div class='del'>-		compatible = "usb-nop-xceiv";</div><div class='del'>-		vcc-supply = &lt;&amp;cp1_reg_usb3_vbus0&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	cp1_sfp_eth1: sfp-eth1 {</div><div class='del'>-		compatible = "sff,sfp";</div><div class='del'>-		i2c-bus = &lt;&amp;cp1_i2c0&gt;;</div><div class='del'>-		los-gpio = &lt;&amp;cp1_gpio1 11 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-		mod-def0-gpio = &lt;&amp;cp1_gpio1 10 GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-		tx-disable-gpio = &lt;&amp;cp1_gpio1 9 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-		tx-fault-gpio = &lt;&amp;cp1_gpio1 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-		pinctrl-names = "default";</div><div class='del'>-		pinctrl-0 = &lt;&amp;cp1_sfp_pins&gt;;</div><div class='del'>-		/*</div><div class='del'>-		 * SFP cages are unconnected on early PCBs because of an the I2C</div><div class='del'>-		 * lanes not being connected. Prevent the port for being</div><div class='del'>-		 * unusable by disabling the SFP node.</div><div class='del'>-		 */</div><div class='del'>-		status = "disabled";</div><div class='del'>-	};</div><div class='add'>+	model = "Marvell Armada CN9131-DB setup A";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-/*</div><div class='del'>- * Instantiate the first slave CP115</div><div class='add'>+/* Setup A has SPI1 flash as a boot device, while setup B uses NAND flash.</div><div class='add'>+ * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated</div><div class='add'>+ * simultaneously. When SPI controller is enabled, NAND should be disabled.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-#define CP11X_NAME		cp1</div><div class='del'>-#define CP11X_BASE		f4000000</div><div class='del'>-#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))</div><div class='del'>-#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000</div><div class='del'>-#define CP11X_PCIE0_BASE	f4600000</div><div class='del'>-#define CP11X_PCIE1_BASE	f4620000</div><div class='del'>-#define CP11X_PCIE2_BASE	f4640000</div><div class='del'>-</div><div class='del'>-#include "armada-cp115.dtsi"</div><div class='del'>-</div><div class='del'>-#undef CP11X_NAME</div><div class='del'>-#undef CP11X_BASE</div><div class='del'>-#undef CP11X_PCIEx_MEM_BASE</div><div class='del'>-#undef CP11X_PCIEx_MEM_SIZE</div><div class='del'>-#undef CP11X_PCIE0_BASE</div><div class='del'>-#undef CP11X_PCIE1_BASE</div><div class='del'>-#undef CP11X_PCIE2_BASE</div><div class='del'>-</div><div class='del'>-&amp;cp1_crypto {</div><div class='del'>-	status = "disabled";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;cp1_ethernet {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-/* CON50 */</div><div class='del'>-&amp;cp1_eth0 {</div><div class='del'>-	status = "disabled";</div><div class='del'>-	phy-mode = "10gbase-kr";</div><div class='del'>-	/* Generic PHY, providing serdes lanes */</div><div class='del'>-	phys = &lt;&amp;cp1_comphy4 0&gt;;</div><div class='del'>-	managed = "in-band-status";</div><div class='del'>-	sfp = &lt;&amp;cp1_sfp_eth1&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;cp1_gpio1 {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;cp1_gpio2 {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;cp1_i2c0 {</div><div class='add'>+&amp;cp0_spi1 {</div><div class='ctx'> 	status = "okay";</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-	pinctrl-0 = &lt;&amp;cp1_i2c0_pins&gt;;</div><div class='del'>-	clock-frequency = &lt;100000&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-/* CON40 */</div><div class='del'>-&amp;cp1_pcie0 {</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-	pinctrl-0 = &lt;&amp;cp1_pcie_reset_pins&gt;;</div><div class='del'>-	num-lanes = &lt;2&gt;;</div><div class='del'>-	num-viewport = &lt;8&gt;;</div><div class='del'>-	marvell,reset-gpio = &lt;&amp;cp1_gpio1 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-	status = "okay";</div><div class='del'>-	/* Generic PHY, providing serdes lanes */</div><div class='del'>-	phys = &lt;&amp;cp1_comphy0 0</div><div class='del'>-		&amp;cp1_comphy1 0&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;cp1_sata0 {</div><div class='del'>-	status = "okay";</div><div class='del'>-</div><div class='del'>-	/* CON32 */</div><div class='del'>-	sata-port@1 {</div><div class='del'>-		/* Generic PHY, providing serdes lanes */</div><div class='del'>-		phys = &lt;&amp;cp1_comphy5 1&gt;;</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-/* U24 */</div><div class='del'>-&amp;cp1_spi1 {</div><div class='del'>-	status = "okay";</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-	pinctrl-0 = &lt;&amp;cp1_spi0_pins&gt;;</div><div class='del'>-	reg = &lt;0x700680 0x50&gt;;</div><div class='del'>-</div><div class='del'>-	spi-flash@0 {</div><div class='del'>-		#address-cells = &lt;0x1&gt;;</div><div class='del'>-		#size-cells = &lt;0x1&gt;;</div><div class='del'>-		compatible = "jedec,spi-nor";</div><div class='del'>-		reg = &lt;0x0&gt;;</div><div class='del'>-		/* On-board MUX does not allow higher frequencies */</div><div class='del'>-		spi-max-frequency = &lt;40000000&gt;;</div><div class='del'>-</div><div class='del'>-		partitions {</div><div class='del'>-			compatible = "fixed-partitions";</div><div class='del'>-			#address-cells = &lt;1&gt;;</div><div class='del'>-			#size-cells = &lt;1&gt;;</div><div class='del'>-</div><div class='del'>-			partition@0 {</div><div class='del'>-				label = "U-Boot-1";</div><div class='del'>-				reg = &lt;0x0 0x200000&gt;;</div><div class='del'>-			};</div><div class='del'>-</div><div class='del'>-			partition@400000 {</div><div class='del'>-				label = "Filesystem-1";</div><div class='del'>-				reg = &lt;0x200000 0xe00000&gt;;</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;cp1_syscon0 {</div><div class='del'>-	cp1_pinctrl: pinctrl {</div><div class='del'>-		compatible = "marvell,cp115-standalone-pinctrl";</div><div class='del'>-</div><div class='del'>-		cp1_i2c0_pins: cp1-i2c-pins-0 {</div><div class='del'>-			marvell,pins = "mpp37", "mpp38";</div><div class='del'>-			marvell,function = "i2c0";</div><div class='del'>-		};</div><div class='del'>-		cp1_spi0_pins: cp1-spi-pins-0 {</div><div class='del'>-			marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";</div><div class='del'>-			marvell,function = "spi1";</div><div class='del'>-		};</div><div class='del'>-		cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {</div><div class='del'>-			marvell,pins = "mpp3";</div><div class='del'>-			marvell,function = "gpio";</div><div class='del'>-		};</div><div class='del'>-		cp1_sfp_pins: sfp-pins {</div><div class='del'>-			marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11";</div><div class='del'>-			marvell,function = "gpio";</div><div class='del'>-		};</div><div class='del'>-		cp1_pcie_reset_pins: cp1-pcie-reset-pins {</div><div class='del'>-			marvell,pins = "mpp0";</div><div class='del'>-			marvell,function = "gpio";</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-/* CON58 */</div><div class='del'>-&amp;cp1_usb3_1 {</div><div class='del'>-	status = "okay";</div><div class='del'>-	usb-phy = &lt;&amp;cp1_usb3_0_phy0&gt;;</div><div class='del'>-	/* Generic PHY, providing serdes lanes */</div><div class='del'>-	phys = &lt;&amp;cp1_comphy3 1&gt;;</div><div class='del'>-	phy-names = "usb";</div><div class='del'>-};</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/cn9131-db.dtsi b/arch/arm64/boot/dts/marvell/cn9131-db.dtsi<br/>new file mode 100644<br/>index 000000000000..626042fce7e2<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/cn9131-db.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/cn9131-db.dtsi</a></div><div class='hunk'>@@ -0,0 +1,205 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2020 Marvell International Ltd.</div><div class='add'>+ *</div><div class='add'>+ * Device tree for the CN9131-DB board.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "cn9130-db.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "marvell,cn9131", "marvell,cn9130",</div><div class='add'>+		     "marvell,armada-ap807-quad", "marvell,armada-ap807";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		gpio3 = &amp;cp1_gpio1;</div><div class='add'>+		gpio4 = &amp;cp1_gpio2;</div><div class='add'>+		ethernet3 = &amp;cp1_eth0;</div><div class='add'>+		ethernet4 = &amp;cp1_eth1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cp1_reg_usb3_vbus0: regulator-6 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;cp1_xhci0_vbus_pins&gt;;</div><div class='add'>+		regulator-name = "cp1-xhci0-vbus";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;cp1_gpio1 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cp1_usb3_0_phy0: usb-phy-3 {</div><div class='add'>+		compatible = "usb-nop-xceiv";</div><div class='add'>+		vcc-supply = &lt;&amp;cp1_reg_usb3_vbus0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cp1_sfp_eth1: sfp-eth-2 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;cp1_i2c0&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;cp1_gpio1 11 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;cp1_gpio1 10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;cp1_gpio1 9 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;cp1_gpio1 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;cp1_sfp_pins&gt;;</div><div class='add'>+		/*</div><div class='add'>+		 * SFP cages are unconnected on early PCBs because of an the I2C</div><div class='add'>+		 * lanes not being connected. Prevent the port for being</div><div class='add'>+		 * unusable by disabling the SFP node.</div><div class='add'>+		 */</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Instantiate the first slave CP115</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#define CP11X_NAME		cp1</div><div class='add'>+#define CP11X_BASE		f4000000</div><div class='add'>+#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))</div><div class='add'>+#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000</div><div class='add'>+#define CP11X_PCIE0_BASE	f4600000</div><div class='add'>+#define CP11X_PCIE1_BASE	f4620000</div><div class='add'>+#define CP11X_PCIE2_BASE	f4640000</div><div class='add'>+</div><div class='add'>+#include "armada-cp115.dtsi"</div><div class='add'>+</div><div class='add'>+#undef CP11X_NAME</div><div class='add'>+#undef CP11X_BASE</div><div class='add'>+#undef CP11X_PCIEx_MEM_BASE</div><div class='add'>+#undef CP11X_PCIEx_MEM_SIZE</div><div class='add'>+#undef CP11X_PCIE0_BASE</div><div class='add'>+#undef CP11X_PCIE1_BASE</div><div class='add'>+#undef CP11X_PCIE2_BASE</div><div class='add'>+</div><div class='add'>+&amp;cp1_crypto {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp1_ethernet {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* CON50 */</div><div class='add'>+&amp;cp1_eth0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	phy-mode = "10gbase-r";</div><div class='add'>+	/* Generic PHY, providing serdes lanes */</div><div class='add'>+	phys = &lt;&amp;cp1_comphy4 0&gt;;</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	sfp = &lt;&amp;cp1_sfp_eth1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp1_gpio1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp1_gpio2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp1_i2c0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp1_i2c0_pins&gt;;</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* CON40 */</div><div class='add'>+&amp;cp1_pcie0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp1_pcie_reset_pins&gt;;</div><div class='add'>+	num-lanes = &lt;2&gt;;</div><div class='add'>+	num-viewport = &lt;8&gt;;</div><div class='add'>+	marvell,reset-gpio = &lt;&amp;cp1_gpio1 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+	/* Generic PHY, providing serdes lanes */</div><div class='add'>+	phys = &lt;&amp;cp1_comphy0 0</div><div class='add'>+		&amp;cp1_comphy1 0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp1_sata0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* CON32 */</div><div class='add'>+	sata-port@1 {</div><div class='add'>+		/* Generic PHY, providing serdes lanes */</div><div class='add'>+		phys = &lt;&amp;cp1_comphy5 1&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* U24 */</div><div class='add'>+&amp;cp1_spi1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp1_spi0_pins&gt;;</div><div class='add'>+	reg = &lt;0x700680 0x50&gt;;</div><div class='add'>+</div><div class='add'>+	flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0x0&gt;;</div><div class='add'>+		/* On-board MUX does not allow higher frequencies */</div><div class='add'>+		spi-max-frequency = &lt;40000000&gt;;</div><div class='add'>+</div><div class='add'>+		partitions {</div><div class='add'>+			compatible = "fixed-partitions";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			partition@0 {</div><div class='add'>+				label = "U-Boot-1";</div><div class='add'>+				reg = &lt;0x0 0x200000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			partition@400000 {</div><div class='add'>+				label = "Filesystem-1";</div><div class='add'>+				reg = &lt;0x200000 0xe00000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp1_syscon0 {</div><div class='add'>+	cp1_pinctrl: pinctrl {</div><div class='add'>+		compatible = "marvell,cp115-standalone-pinctrl";</div><div class='add'>+</div><div class='add'>+		cp1_i2c0_pins: cp1-i2c-pins-0 {</div><div class='add'>+			marvell,pins = "mpp37", "mpp38";</div><div class='add'>+			marvell,function = "i2c0";</div><div class='add'>+		};</div><div class='add'>+		cp1_spi0_pins: cp1-spi-pins-0 {</div><div class='add'>+			marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";</div><div class='add'>+			marvell,function = "spi1";</div><div class='add'>+		};</div><div class='add'>+		cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {</div><div class='add'>+			marvell,pins = "mpp3";</div><div class='add'>+			marvell,function = "gpio";</div><div class='add'>+		};</div><div class='add'>+		cp1_sfp_pins: sfp-pins {</div><div class='add'>+			marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11";</div><div class='add'>+			marvell,function = "gpio";</div><div class='add'>+		};</div><div class='add'>+		cp1_pcie_reset_pins: cp1-pcie-reset-pins {</div><div class='add'>+			marvell,pins = "mpp0";</div><div class='add'>+			marvell,function = "gpio";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* CON58 */</div><div class='add'>+&amp;cp1_utmi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp1_usb3_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	usb-phy = &lt;&amp;cp1_usb3_0_phy0&gt;;</div><div class='add'>+	/* Generic PHY, providing serdes lanes */</div><div class='add'>+	phys = &lt;&amp;cp1_comphy3 1&gt;, &lt;&amp;cp1_utmi1&gt;;</div><div class='add'>+	phy-names = "usb", "utmi";</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/cn9132-clearfog.dts b/arch/arm64/boot/dts/marvell/cn9132-clearfog.dts<br/>new file mode 100644<br/>index 000000000000..2507896d58f9<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/cn9132-clearfog.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/cn9132-clearfog.dts</a></div><div class='hunk'>@@ -0,0 +1,671 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2024 Josua Mayer &lt;josua@solid-run.com&gt;</div><div class='add'>+ *</div><div class='add'>+ * DTS for SolidRun CN9132 Clearfog.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+#include "cn9130.dtsi"</div><div class='add'>+#include "cn9132-sr-cex7.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "SolidRun CN9132 Clearfog";</div><div class='add'>+	compatible = "solidrun,cn9132-clearfog",</div><div class='add'>+		     "solidrun,cn9132-sr-cex7", "marvell,cn9130";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet1 = &amp;cp0_eth2;</div><div class='add'>+		ethernet2 = &amp;cp0_eth0;</div><div class='add'>+		ethernet3 = &amp;cp2_eth0;</div><div class='add'>+		ethernet4 = &amp;cp1_eth0;</div><div class='add'>+		i2c7 = &amp;carrier_mpcie_i2c;</div><div class='add'>+		i2c8 = &amp;carrier_ptp_i2c;</div><div class='add'>+		mmc1 = &amp;cp0_sdhci0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;cp1_wake0_pins&gt;;</div><div class='add'>+</div><div class='add'>+		button-0 {</div><div class='add'>+			label = "SW2";</div><div class='add'>+			gpios = &lt;&amp;cp1_gpio2 8 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,can-disable;</div><div class='add'>+			linux,code = &lt;BTN_2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;cp1_batlow_pins &amp;cp2_rsvd4_pins&gt;;</div><div class='add'>+</div><div class='add'>+		/* LED11 */</div><div class='add'>+		led-io-0 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_DISK;</div><div class='add'>+			function-enumerator = &lt;0&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+			gpios = &lt;&amp;cp1_gpio1 11 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* LED12 */</div><div class='add'>+		led-io-1 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_DISK;</div><div class='add'>+			function-enumerator = &lt;1&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+			gpios = &lt;&amp;cp2_gpio1 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* CON4 W_DISABLE1/W_DISABLE2 */</div><div class='add'>+	rfkill-m2-wlan {</div><div class='add'>+		compatible = "rfkill-gpio";</div><div class='add'>+		label = "m.2 wlan (CON4)";</div><div class='add'>+		radio-type = "wlan";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;cp1_10g_phy_rst_01_pins&gt;;</div><div class='add'>+		/* rfkill-gpio inverts internally */</div><div class='add'>+		shutdown-gpios = &lt;&amp;cp1_gpio2 11 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* CON5 W_DISABLE1/W_DISABLE2 */</div><div class='add'>+	rfkill-m2-wlan {</div><div class='add'>+		compatible = "rfkill-gpio";</div><div class='add'>+		label = "m.2 wlan (CON5)";</div><div class='add'>+		radio-type = "wlan";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;cp1_10g_phy_rst_23_pins&gt;;</div><div class='add'>+		/* rfkill-gpio inverts internally */</div><div class='add'>+		shutdown-gpios = &lt;&amp;cp1_gpio2 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* J21 W_DISABLE1 */</div><div class='add'>+	rfkill-m2-wwan {</div><div class='add'>+		compatible = "rfkill-gpio";</div><div class='add'>+		label = "m.2 wwan (J21)";</div><div class='add'>+		radio-type = "wwan";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;cp2_rsvd3_pins&gt;;</div><div class='add'>+		/* rfkill-gpio inverts internally */</div><div class='add'>+		shutdown-gpios = &lt;&amp;cp2_gpio1 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* J21 W_DISABLE1 */</div><div class='add'>+	rfkill-m2-gnss {</div><div class='add'>+		compatible = "rfkill-gpio";</div><div class='add'>+		label = "m.2 gnss (J21)";</div><div class='add'>+		radio-type = "gps";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;cp2_rsvd8_pins&gt;;</div><div class='add'>+		/* rfkill-gpio inverts internally */</div><div class='add'>+		shutdown-gpios = &lt;&amp;cp2_gpio1 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* J14 W_DISABLE */</div><div class='add'>+	rfkill-mpcie-wlan {</div><div class='add'>+		compatible = "rfkill-gpio";</div><div class='add'>+		label = "mpcie wlan (J14)";</div><div class='add'>+		radio-type = "wlan";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;cp2_rsvd2_pins&gt;;</div><div class='add'>+		/* rfkill-gpio inverts internally */</div><div class='add'>+		shutdown-gpios = &lt;&amp;cp2_gpio1 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp: sfp {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;com_10g_sfp_i2c0&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;com_10g_int0_pins&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;cp0_gpio1 24 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		maximum-power-milliwatt = &lt;2000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;com_smbus {</div><div class='add'>+	/* This bus is also routed to STM32 BMC Microcontroller (U2) */</div><div class='add'>+</div><div class='add'>+	power-sensor@40 {</div><div class='add'>+		compatible = "ti,ina220";</div><div class='add'>+		reg = &lt;0x40&gt;;</div><div class='add'>+		#io-channel-cells = &lt;1&gt;;</div><div class='add'>+		label = "vdd_12v0";</div><div class='add'>+		shunt-resistor = &lt;2000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	adc@48 {</div><div class='add'>+		compatible = "ti,tla2021";</div><div class='add'>+		reg = &lt;0x48&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		/* supplied by chaoskey hardware noise generator circuit */</div><div class='add'>+		channel@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_eth_phy0 {</div><div class='add'>+	/*</div><div class='add'>+	 * Configure LEDs default behaviour:</div><div class='add'>+	 * - LED[0]: link is 1000Mbps: On (yellow): 0111</div><div class='add'>+	 * - LED[1]: link/activity: On/Blink (green): 0001</div><div class='add'>+	 * - LED[2]: Off (green): 1000</div><div class='add'>+	 */</div><div class='add'>+	marvell,reg-init = &lt;3 16 0xf000 0x0817&gt;;</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		led@0 {</div><div class='add'>+			/* link */</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			color = &lt;LED_COLOR_ID_YELLOW&gt;;</div><div class='add'>+			function = LED_FUNCTION_LAN;</div><div class='add'>+			default-state = "keep";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led@1 {</div><div class='add'>+			/* act */</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_LAN;</div><div class='add'>+			default-state = "keep";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led@2 {</div><div class='add'>+			/* 1000 */</div><div class='add'>+			reg = &lt;2&gt;;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_LAN;</div><div class='add'>+			default-state = "keep";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SRDS #4 - 10GE */</div><div class='add'>+&amp;cp0_eth0 {</div><div class='add'>+	phys = &lt;&amp;cp0_comphy4 0&gt;;</div><div class='add'>+	phy-mode = "10gbase-r";</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	sfp = &lt;&amp;sfp&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_eth2 {</div><div class='add'>+	phy-mode = "2500base-x";</div><div class='add'>+	phys = &lt;&amp;cp0_comphy5 2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	fixed-link {</div><div class='add'>+		speed = &lt;2500&gt;;</div><div class='add'>+		full-duplex;</div><div class='add'>+		pause;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_i2c1 {</div><div class='add'>+	/*</div><div class='add'>+	 * Both COM and Carrier Board have a PCA9547 i2c mux at 0x77.</div><div class='add'>+	 * Describe them as a single device merging each child bus.</div><div class='add'>+	 */</div><div class='add'>+</div><div class='add'>+	i2c-mux@77 {</div><div class='add'>+		i2c@0 {</div><div class='add'>+			/* Routed to Full PCIe (J4) */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@1 {</div><div class='add'>+			/* Routed to USB Hub (U29) */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@2 {</div><div class='add'>+			/* Routed to M.2 (CON4) */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@3 {</div><div class='add'>+			/* Routed to M.2 (CON5) */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@4 {</div><div class='add'>+			/* Routed to M.2 (J21) */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		carrier_mpcie_i2c: i2c@5 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;5&gt;;</div><div class='add'>+</div><div class='add'>+			/* Routed to mini-PCIe (J14) */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		carrier_ptp_i2c: i2c@6 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;6&gt;;</div><div class='add'>+</div><div class='add'>+			/* Routed to various optional PTP related components */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_mdio {</div><div class='add'>+	ethernet-switch@4 {</div><div class='add'>+		compatible = "marvell,mv88e6085";</div><div class='add'>+		reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+		mdio {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			sw_phy1: ethernet-phy@1 {</div><div class='add'>+				reg = &lt;0x11&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sw_phy2: ethernet-phy@2 {</div><div class='add'>+				reg = &lt;0x12&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sw_phy3: ethernet-phy@3 {</div><div class='add'>+				reg = &lt;0x13&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sw_phy4: ethernet-phy@4 {</div><div class='add'>+				reg = &lt;0x14&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ethernet-ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			ethernet-port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				label = "lan1";</div><div class='add'>+				phy-handle = &lt;&amp;sw_phy1&gt;;</div><div class='add'>+				phy-mode = "internal";</div><div class='add'>+</div><div class='add'>+				leds {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					led@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+						color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+						function = LED_FUNCTION_LAN;</div><div class='add'>+						default-state = "keep";</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					led@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+						color = &lt;LED_COLOR_ID_YELLOW&gt;;</div><div class='add'>+						function = LED_FUNCTION_LAN;</div><div class='add'>+						default-state = "keep";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ethernet-port@2 {</div><div class='add'>+				reg = &lt;2&gt;;</div><div class='add'>+				label = "lan2";</div><div class='add'>+				phy-handle = &lt;&amp;sw_phy2&gt;;</div><div class='add'>+				phy-mode = "internal";</div><div class='add'>+</div><div class='add'>+				leds {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					led@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+						color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+						function = LED_FUNCTION_LAN;</div><div class='add'>+						default-state = "keep";</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					led@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+						color = &lt;LED_COLOR_ID_YELLOW&gt;;</div><div class='add'>+						function = LED_FUNCTION_LAN;</div><div class='add'>+						default-state = "keep";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ethernet-port@3 {</div><div class='add'>+				reg = &lt;3&gt;;</div><div class='add'>+				label = "lan3";</div><div class='add'>+				phy-handle = &lt;&amp;sw_phy3&gt;;</div><div class='add'>+				phy-mode = "internal";</div><div class='add'>+</div><div class='add'>+				leds {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					led@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+						color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+						function = LED_FUNCTION_LAN;</div><div class='add'>+						default-state = "keep";</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					led@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+						color = &lt;LED_COLOR_ID_YELLOW&gt;;</div><div class='add'>+						function = LED_FUNCTION_LAN;</div><div class='add'>+						default-state = "keep";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ethernet-port@4 {</div><div class='add'>+				reg = &lt;4&gt;;</div><div class='add'>+				label = "lan4";</div><div class='add'>+				phy-handle = &lt;&amp;sw_phy4&gt;;</div><div class='add'>+				phy-mode = "internal";</div><div class='add'>+</div><div class='add'>+				leds {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					led@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+						color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+						function = LED_FUNCTION_LAN;</div><div class='add'>+						default-state = "keep";</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					led@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+						color = &lt;LED_COLOR_ID_YELLOW&gt;;</div><div class='add'>+						function = LED_FUNCTION_LAN;</div><div class='add'>+						default-state = "keep";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ethernet-port@5 {</div><div class='add'>+				reg = &lt;5&gt;;</div><div class='add'>+				label = "cpu";</div><div class='add'>+				ethernet = &lt;&amp;cp0_eth2&gt;;</div><div class='add'>+				phy-mode = "2500base-x";</div><div class='add'>+</div><div class='add'>+				fixed-link {</div><div class='add'>+					speed = &lt;2500&gt;;</div><div class='add'>+					full-duplex;</div><div class='add'>+					pause;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SRDS #0,#1,#2,#3 - PCIe */</div><div class='add'>+&amp;cp0_pcie0 {</div><div class='add'>+	num-lanes = &lt;4&gt;;</div><div class='add'>+	phys = &lt;&amp;cp0_comphy0 0&gt;, &lt;&amp;cp0_comphy1 0&gt;, &lt;&amp;cp0_comphy2 0&gt;, &lt;&amp;cp0_comphy3 0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_pinctrl {</div><div class='add'>+	/*</div><div class='add'>+	 * configure unused gpios exposed via pin headers:</div><div class='add'>+	 * - J7-10: PWRBTN</div><div class='add'>+	 */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp0_pwrbtn_pins&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* microSD */</div><div class='add'>+&amp;cp0_sdhci0 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp0_mmc0_pins&gt;, &lt;&amp;cp0_mmc0_cd_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	no-1-8-v;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_spi1 {</div><div class='add'>+	/* add CS1 */</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp0_spi1_pins&gt;, &lt;&amp;cp0_spi1_cs1_pins&gt;;</div><div class='add'>+</div><div class='add'>+	flash@1 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		/* read command supports max. 50MHz */</div><div class='add'>+		spi-max-frequency = &lt;50000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* J38 */</div><div class='add'>+&amp;cp0_uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp0_uart2_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_utmi {</div><div class='add'>+	/* M.2 "CON5" swaps D+/D- */</div><div class='add'>+	swap-dx-lanes = &lt;1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp1_ethernet {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SRDS #2 - 5GE */</div><div class='add'>+&amp;cp1_eth0 {</div><div class='add'>+	phys = &lt;&amp;cp1_comphy2 0&gt;;</div><div class='add'>+	phy-mode = "5gbase-r";</div><div class='add'>+	phy = &lt;&amp;cp1_eth_phy0&gt;;</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SRDS #0,#1 - PCIe */</div><div class='add'>+&amp;cp1_pcie0 {</div><div class='add'>+	num-lanes = &lt;2&gt;;</div><div class='add'>+	phys = &lt;&amp;cp1_comphy0 0&gt;, &lt;&amp;cp1_comphy1 0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SRDS #4 - PCIe */</div><div class='add'>+&amp;cp1_pcie1 {</div><div class='add'>+	num-lanes = &lt;1&gt;;</div><div class='add'>+	phys = &lt;&amp;cp1_comphy4 1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SRDS #5 - PCIe */</div><div class='add'>+&amp;cp1_pcie2 {</div><div class='add'>+	num-lanes = &lt;1&gt;;</div><div class='add'>+	phys = &lt;&amp;cp1_comphy5 2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp1_pinctrl {</div><div class='add'>+	/*</div><div class='add'>+	 * configure unused gpios exposed via pin headers:</div><div class='add'>+	 * - J7-8: RSVD16</div><div class='add'>+	 * - J7-10: THRM</div><div class='add'>+	 * - J10-1: WAKE1</div><div class='add'>+	 * - J10-2: SATA_ACT</div><div class='add'>+	 * - J10-8: THERMTRIP</div><div class='add'>+	 */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp1_rsvd16_pins &amp;cp1_sata_act_pins &amp;cp1_thrm_irq_pins&gt;,</div><div class='add'>+		    &lt;&amp;cp1_thrm_trip_pins &amp;cp1_wake1_pins&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SRDS #3 - SATA */</div><div class='add'>+&amp;cp1_sata0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* only port 1 is available */</div><div class='add'>+	sata-port@1 {</div><div class='add'>+		phys = &lt;&amp;cp1_comphy3 1&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp1_utmi {</div><div class='add'>+	/* M.2 "CON4" swaps D+/D- */</div><div class='add'>+	swap-dx-lanes = &lt;0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp1_xmdio {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp1_xmdio_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	cp1_eth_phy0: ethernet-phy@8 {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+		reg = &lt;8&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;com_10g_int1_pins&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;cp1_gpio2&gt;;</div><div class='add'>+		interrupts = &lt;18 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+</div><div class='add'>+		leds {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			led@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				color = &lt;LED_COLOR_ID_YELLOW&gt;;</div><div class='add'>+				function = LED_FUNCTION_LAN;</div><div class='add'>+				default-state = "keep";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			led@2 {</div><div class='add'>+				reg = &lt;2&gt;;</div><div class='add'>+				color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+				function = LED_FUNCTION_LAN;</div><div class='add'>+				default-state = "keep";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp2_ethernet {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SRDS #2 - 5GE */</div><div class='add'>+&amp;cp2_eth0 {</div><div class='add'>+	phys = &lt;&amp;cp2_comphy2 0&gt;;</div><div class='add'>+	phy-mode = "5gbase-r";</div><div class='add'>+	phy = &lt;&amp;cp2_eth_phy0&gt;;</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp2_gpio1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp2_rsvd9_pins&gt;;</div><div class='add'>+</div><div class='add'>+	/* J21 */</div><div class='add'>+	m2-wwan-reset-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;9 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+		output-low;</div><div class='add'>+		line-name = "m2-wwan-reset";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SRDS #0 - PCIe */</div><div class='add'>+&amp;cp2_pcie0 {</div><div class='add'>+	num-lanes = &lt;1&gt;;</div><div class='add'>+	phys = &lt;&amp;cp2_comphy0 0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SRDS #4 - PCIe */</div><div class='add'>+&amp;cp2_pcie1 {</div><div class='add'>+	num-lanes = &lt;1&gt;;</div><div class='add'>+	phys = &lt;&amp;cp2_comphy4 1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SRDS #5 - PCIe */</div><div class='add'>+&amp;cp2_pcie2 {</div><div class='add'>+	num-lanes = &lt;1&gt;;</div><div class='add'>+	phys = &lt;&amp;cp2_comphy5 2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp2_pinctrl {</div><div class='add'>+	/*</div><div class='add'>+	 * configure unused gpios exposed via pin headers:</div><div class='add'>+	 * - J7-1: RSVD10</div><div class='add'>+	 * - J7-3: RSVD11</div><div class='add'>+	 * - J7-5: RSVD56</div><div class='add'>+	 * - J7-6: RSVD7</div><div class='add'>+	 * - J7-7: RSVD27</div><div class='add'>+	 * - J10-3: RSVD31</div><div class='add'>+	 * - J10-5: RSVD5</div><div class='add'>+	 * - J10-6: RSVD32</div><div class='add'>+	 * - J10-7: RSVD0</div><div class='add'>+	 * - J10-9: RSVD1</div><div class='add'>+	 */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp2_rsvd0_pins &amp;cp2_rsvd1_pins &amp;cp2_rsvd5_pins&gt;,</div><div class='add'>+		    &lt;&amp;cp2_rsvd7_pins &amp;cp2_rsvd10_pins &amp;cp2_rsvd11_pins&gt;,</div><div class='add'>+		    &lt;&amp;cp2_rsvd27_pins &amp;cp2_rsvd31_pins &amp;cp2_rsvd32_pins&gt;,</div><div class='add'>+		    &lt;&amp;cp2_rsvd56_pins&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SRDS #3 - SATA */</div><div class='add'>+&amp;cp2_sata0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* only port 1 is available */</div><div class='add'>+	sata-port@1 {</div><div class='add'>+		status = "okay";</div><div class='add'>+		phys = &lt;&amp;cp2_comphy3 1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp2_xmdio {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp2_xmdio_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	cp2_eth_phy0: ethernet-phy@8 {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+		reg = &lt;8&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;com_10g_int2_pins&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;cp2_gpio2&gt;;</div><div class='add'>+		interrupts = &lt;18 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+</div><div class='add'>+		leds {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			led@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				color = &lt;LED_COLOR_ID_YELLOW&gt;;</div><div class='add'>+				function = LED_FUNCTION_LAN;</div><div class='add'>+				default-state = "keep";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			led@2 {</div><div class='add'>+				reg = &lt;2&gt;;</div><div class='add'>+				color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+				function = LED_FUNCTION_LAN;</div><div class='add'>+				default-state = "keep";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/cn9132-db-B.dts b/arch/arm64/boot/dts/marvell/cn9132-db-B.dts<br/>new file mode 100644<br/>index 000000000000..7137a6f22d0f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/cn9132-db-B.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/cn9132-db-B.dts</a></div><div class='hunk'>@@ -0,0 +1,22 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2019 Marvell International Ltd.</div><div class='add'>+ *</div><div class='add'>+ * Device tree for the CN9132-DB board.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "cn9132-db.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Marvell Armada CN9132-DB setup B";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Setup B has NAND flash as a boot device, while regular setup uses SPI flash.</div><div class='add'>+ * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated</div><div class='add'>+ * simultaneously. When NAND controller is enabled, SPI1 should be disabled.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;cp0_nand_controller {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/cn9132-db.dts b/arch/arm64/boot/dts/marvell/cn9132-db.dts<br/>index 4ef0df3097ca..1f2e6377afc3 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/cn9132-db.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/marvell/cn9132-db.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/cn9132-db.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/cn9132-db.dts</a></div><div class='hunk'>@@ -5,217 +5,18 @@</div><div class='ctx'>  * Device tree for the CN9132-DB board.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-#include "cn9131-db.dts"</div><div class='add'>+#include "cn9132-db.dtsi"</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='del'>-	model = "Marvell Armada CN9132-DB";</div><div class='del'>-	compatible = "marvell,cn9132", "marvell,cn9131", "marvell,cn9130",</div><div class='del'>-		     "marvell,armada-ap807-quad", "marvell,armada-ap807";</div><div class='del'>-</div><div class='del'>-	aliases {</div><div class='del'>-		gpio5 = &amp;cp2_gpio1;</div><div class='del'>-		gpio6 = &amp;cp2_gpio2;</div><div class='del'>-		ethernet5 = &amp;cp2_eth0;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 {</div><div class='del'>-		compatible = "regulator-fixed";</div><div class='del'>-		regulator-name = "cp2-xhci0-vbus";</div><div class='del'>-		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='del'>-		enable-active-high;</div><div class='del'>-		gpio = &lt;&amp;cp2_gpio1 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	cp2_usb3_0_phy0: cp2_usb3_phy0 {</div><div class='del'>-		compatible = "usb-nop-xceiv";</div><div class='del'>-		vcc-supply = &lt;&amp;cp2_reg_usb3_vbus0&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	cp2_reg_usb3_vbus1: cp2_usb3_vbus@1 {</div><div class='del'>-		compatible = "regulator-fixed";</div><div class='del'>-		regulator-name = "cp2-xhci1-vbus";</div><div class='del'>-		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='del'>-		enable-active-high;</div><div class='del'>-		gpio = &lt;&amp;cp2_gpio1 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	cp2_usb3_0_phy1: cp2_usb3_phy1 {</div><div class='del'>-		compatible = "usb-nop-xceiv";</div><div class='del'>-		vcc-supply = &lt;&amp;cp2_reg_usb3_vbus1&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	cp2_reg_sd_vccq: cp2_sd_vccq@0 {</div><div class='del'>-		compatible = "regulator-gpio";</div><div class='del'>-		regulator-name = "cp2_sd_vcc";</div><div class='del'>-		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='del'>-		gpios = &lt;&amp;cp2_gpio2 17 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-		states = &lt;1800000 0x1 3300000 0x0&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	cp2_sfp_eth0: sfp-eth0 {</div><div class='del'>-		compatible = "sff,sfp";</div><div class='del'>-		i2c-bus = &lt;&amp;cp2_sfpp0_i2c&gt;;</div><div class='del'>-		los-gpio = &lt;&amp;cp2_module_expander1 11 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-		mod-def0-gpio = &lt;&amp;cp2_module_expander1 10 GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-		tx-disable-gpio = &lt;&amp;cp2_module_expander1 9 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-		tx-fault-gpio = &lt;&amp;cp2_module_expander1 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-		/*</div><div class='del'>-		 * SFP cages are unconnected on early PCBs because of an the I2C</div><div class='del'>-		 * lanes not being connected. Prevent the port for being</div><div class='del'>-		 * unusable by disabling the SFP node.</div><div class='del'>-		 */</div><div class='del'>-		status = "disabled";</div><div class='del'>-	};</div><div class='add'>+	model = "Marvell Armada CN9132-DB setup A";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-/*</div><div class='del'>- * Instantiate the second slave CP115</div><div class='add'>+/* Setup A has SPI1 flash as a boot device, while setup B uses NAND flash.</div><div class='add'>+ * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated</div><div class='add'>+ * simultaneously. When SPI controller is enabled, NAND should be disabled.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-#define CP11X_NAME		cp2</div><div class='del'>-#define CP11X_BASE		f6000000</div><div class='del'>-#define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000))</div><div class='del'>-#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000</div><div class='del'>-#define CP11X_PCIE0_BASE	f6600000</div><div class='del'>-#define CP11X_PCIE1_BASE	f6620000</div><div class='del'>-#define CP11X_PCIE2_BASE	f6640000</div><div class='del'>-</div><div class='del'>-#include "armada-cp115.dtsi"</div><div class='del'>-</div><div class='del'>-#undef CP11X_NAME</div><div class='del'>-#undef CP11X_BASE</div><div class='del'>-#undef CP11X_PCIEx_MEM_BASE</div><div class='del'>-#undef CP11X_PCIEx_MEM_SIZE</div><div class='del'>-#undef CP11X_PCIE0_BASE</div><div class='del'>-#undef CP11X_PCIE1_BASE</div><div class='del'>-#undef CP11X_PCIE2_BASE</div><div class='del'>-</div><div class='del'>-&amp;cp2_crypto {</div><div class='del'>-	status = "disabled";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;cp2_ethernet {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-/* SLM-1521-V2, CON9 */</div><div class='del'>-&amp;cp2_eth0 {</div><div class='del'>-	status = "disabled";</div><div class='del'>-	phy-mode = "10gbase-kr";</div><div class='del'>-	/* Generic PHY, providing serdes lanes */</div><div class='del'>-	phys = &lt;&amp;cp2_comphy4 0&gt;;</div><div class='del'>-	managed = "in-band-status";</div><div class='del'>-	sfp = &lt;&amp;cp2_sfp_eth0&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;cp2_gpio1 {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;cp2_gpio2 {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;cp2_i2c0 {</div><div class='del'>-	clock-frequency = &lt;100000&gt;;</div><div class='del'>-</div><div class='del'>-	/* SLM-1521-V2 - U3 */</div><div class='del'>-	i2c-mux@72 {</div><div class='del'>-		compatible = "nxp,pca9544";</div><div class='del'>-		#address-cells = &lt;1&gt;;</div><div class='del'>-		#size-cells = &lt;0&gt;;</div><div class='del'>-		reg = &lt;0x72&gt;;</div><div class='del'>-		cp2_sfpp0_i2c: i2c@0 {</div><div class='del'>-			#address-cells = &lt;1&gt;;</div><div class='del'>-			#size-cells = &lt;0&gt;;</div><div class='del'>-			reg = &lt;0&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		i2c@1 {</div><div class='del'>-			#address-cells = &lt;1&gt;;</div><div class='del'>-			#size-cells = &lt;0&gt;;</div><div class='del'>-			reg = &lt;1&gt;;</div><div class='del'>-			/* U12 */</div><div class='del'>-			cp2_module_expander1: pca9555@21 {</div><div class='del'>-				compatible = "nxp,pca9555";</div><div class='del'>-				pinctrl-names = "default";</div><div class='del'>-				gpio-controller;</div><div class='del'>-				#gpio-cells = &lt;2&gt;;</div><div class='del'>-				reg = &lt;0x21&gt;;</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-/* SLM-1521-V2, CON6 */</div><div class='del'>-&amp;cp2_pcie0 {</div><div class='del'>-	status = "okay";</div><div class='del'>-	num-lanes = &lt;2&gt;;</div><div class='del'>-	num-viewport = &lt;8&gt;;</div><div class='del'>-	/* Generic PHY, providing serdes lanes */</div><div class='del'>-	phys = &lt;&amp;cp2_comphy0 0</div><div class='del'>-		&amp;cp2_comphy1 0&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-/* SLM-1521-V2, CON8 */</div><div class='del'>-&amp;cp2_pcie2 {</div><div class='del'>-	status = "okay";</div><div class='del'>-	num-lanes = &lt;1&gt;;</div><div class='del'>-	num-viewport = &lt;8&gt;;</div><div class='del'>-	/* Generic PHY, providing serdes lanes */</div><div class='del'>-	phys = &lt;&amp;cp2_comphy5 2&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;cp2_sata0 {</div><div class='add'>+&amp;cp0_spi1 {</div><div class='ctx'> 	status = "okay";</div><div class='del'>-</div><div class='del'>-	/* SLM-1521-V2, CON4 */</div><div class='del'>-	sata-port@0 {</div><div class='del'>-		/* Generic PHY, providing serdes lanes */</div><div class='del'>-		phys = &lt;&amp;cp2_comphy2 0&gt;;</div><div class='del'>-	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-/* CON 2 on SLM-1683 - microSD */</div><div class='del'>-&amp;cp2_sdhci0 {</div><div class='del'>-	status = "okay";</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-	pinctrl-0 = &lt;&amp;cp2_sdhci_pins&gt;;</div><div class='del'>-	bus-width = &lt;4&gt;;</div><div class='del'>-	cd-gpios = &lt;&amp;cp2_gpio2 23 GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-	vqmmc-supply = &lt;&amp;cp2_reg_sd_vccq&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;cp2_syscon0 {</div><div class='del'>-	cp2_pinctrl: pinctrl {</div><div class='del'>-		compatible = "marvell,cp115-standalone-pinctrl";</div><div class='del'>-</div><div class='del'>-		cp2_i2c0_pins: cp2-i2c-pins-0 {</div><div class='del'>-			marvell,pins = "mpp37", "mpp38";</div><div class='del'>-			marvell,function = "i2c0";</div><div class='del'>-		};</div><div class='del'>-		cp2_sdhci_pins: cp2-sdhi-pins-0 {</div><div class='del'>-			marvell,pins = "mpp56", "mpp57", "mpp58",</div><div class='del'>-				       "mpp59", "mpp60", "mpp61";</div><div class='del'>-			marvell,function = "sdio";</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;cp2_usb3_0 {</div><div class='del'>-	status = "okay";</div><div class='del'>-	usb-phy = &lt;&amp;cp2_usb3_0_phy0&gt;;</div><div class='del'>-	phy-names = "usb";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-/* SLM-1521-V2, CON11 */</div><div class='del'>-&amp;cp2_usb3_1 {</div><div class='del'>-	status = "okay";</div><div class='del'>-	usb-phy = &lt;&amp;cp2_usb3_0_phy1&gt;;</div><div class='del'>-	phy-names = "usb";</div><div class='del'>-	/* Generic PHY, providing serdes lanes */</div><div class='del'>-	phys = &lt;&amp;cp2_comphy3 1&gt;;</div><div class='del'>-};</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/cn9132-db.dtsi b/arch/arm64/boot/dts/marvell/cn9132-db.dtsi<br/>new file mode 100644<br/>index 000000000000..f91fc69905b8<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/cn9132-db.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/cn9132-db.dtsi</a></div><div class='hunk'>@@ -0,0 +1,228 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2020 Marvell International Ltd.</div><div class='add'>+ *</div><div class='add'>+ * Device tree for the CN9132-DB board.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "cn9131-db.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "marvell,cn9132", "marvell,cn9131", "marvell,cn9130",</div><div class='add'>+		     "marvell,armada-ap807-quad", "marvell,armada-ap807";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		gpio5 = &amp;cp2_gpio1;</div><div class='add'>+		gpio6 = &amp;cp2_gpio2;</div><div class='add'>+		ethernet5 = &amp;cp2_eth0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cp2_reg_usb3_vbus0: regulator-7 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "cp2-xhci0-vbus";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;cp2_gpio1 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cp2_usb3_0_phy0: usb-phy-4 {</div><div class='add'>+		compatible = "usb-nop-xceiv";</div><div class='add'>+		vcc-supply = &lt;&amp;cp2_reg_usb3_vbus0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cp2_reg_usb3_vbus1: regulator-8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "cp2-xhci1-vbus";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;cp2_gpio1 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cp2_usb3_0_phy1: usb-phy-5 {</div><div class='add'>+		compatible = "usb-nop-xceiv";</div><div class='add'>+		vcc-supply = &lt;&amp;cp2_reg_usb3_vbus1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cp2_reg_sd_vccq: regulator-9 {</div><div class='add'>+		compatible = "regulator-gpio";</div><div class='add'>+		regulator-name = "cp2_sd_vcc";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpios = &lt;&amp;cp2_gpio2 17 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		states = &lt;1800000 0x1 3300000 0x0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cp2_sfp_eth0: sfp-eth-3 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;cp2_sfpp0_i2c&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;cp2_module_expander1 11 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;cp2_module_expander1 10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;cp2_module_expander1 9 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;cp2_module_expander1 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		/*</div><div class='add'>+		 * SFP cages are unconnected on early PCBs because of an the I2C</div><div class='add'>+		 * lanes not being connected. Prevent the port for being</div><div class='add'>+		 * unusable by disabling the SFP node.</div><div class='add'>+		 */</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Instantiate the second slave CP115</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#define CP11X_NAME		cp2</div><div class='add'>+#define CP11X_BASE		f6000000</div><div class='add'>+#define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000))</div><div class='add'>+#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000</div><div class='add'>+#define CP11X_PCIE0_BASE	f6600000</div><div class='add'>+#define CP11X_PCIE1_BASE	f6620000</div><div class='add'>+#define CP11X_PCIE2_BASE	f6640000</div><div class='add'>+</div><div class='add'>+#include "armada-cp115.dtsi"</div><div class='add'>+</div><div class='add'>+#undef CP11X_NAME</div><div class='add'>+#undef CP11X_BASE</div><div class='add'>+#undef CP11X_PCIEx_MEM_BASE</div><div class='add'>+#undef CP11X_PCIEx_MEM_SIZE</div><div class='add'>+#undef CP11X_PCIE0_BASE</div><div class='add'>+#undef CP11X_PCIE1_BASE</div><div class='add'>+#undef CP11X_PCIE2_BASE</div><div class='add'>+</div><div class='add'>+&amp;cp2_crypto {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp2_ethernet {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SLM-1521-V2, CON9 */</div><div class='add'>+&amp;cp2_eth0 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+	phy-mode = "10gbase-r";</div><div class='add'>+	/* Generic PHY, providing serdes lanes */</div><div class='add'>+	phys = &lt;&amp;cp2_comphy4 0&gt;;</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	sfp = &lt;&amp;cp2_sfp_eth0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp2_gpio1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp2_gpio2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp2_i2c0 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+</div><div class='add'>+	/* SLM-1521-V2 - U3 */</div><div class='add'>+	i2c-mux@72 {</div><div class='add'>+		compatible = "nxp,pca9544";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		reg = &lt;0x72&gt;;</div><div class='add'>+		cp2_sfpp0_i2c: i2c@0 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@1 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			/* U12 */</div><div class='add'>+			cp2_module_expander1: pca9555@21 {</div><div class='add'>+				compatible = "nxp,pca9555";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				gpio-controller;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+				reg = &lt;0x21&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SLM-1521-V2, CON6 */</div><div class='add'>+&amp;cp2_pcie0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	num-lanes = &lt;2&gt;;</div><div class='add'>+	num-viewport = &lt;8&gt;;</div><div class='add'>+	/* Generic PHY, providing serdes lanes */</div><div class='add'>+	phys = &lt;&amp;cp2_comphy0 0</div><div class='add'>+		&amp;cp2_comphy1 0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SLM-1521-V2, CON8 */</div><div class='add'>+&amp;cp2_pcie2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	num-lanes = &lt;1&gt;;</div><div class='add'>+	num-viewport = &lt;8&gt;;</div><div class='add'>+	/* Generic PHY, providing serdes lanes */</div><div class='add'>+	phys = &lt;&amp;cp2_comphy5 2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp2_sata0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* SLM-1521-V2, CON4 */</div><div class='add'>+	sata-port@0 {</div><div class='add'>+		/* Generic PHY, providing serdes lanes */</div><div class='add'>+		phys = &lt;&amp;cp2_comphy2 0&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* CON 2 on SLM-1683 - microSD */</div><div class='add'>+&amp;cp2_sdhci0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp2_sdhci_pins&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;cp2_gpio2 23 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;cp2_reg_sd_vccq&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp2_syscon0 {</div><div class='add'>+	cp2_pinctrl: pinctrl {</div><div class='add'>+		compatible = "marvell,cp115-standalone-pinctrl";</div><div class='add'>+</div><div class='add'>+		cp2_i2c0_pins: cp2-i2c-pins-0 {</div><div class='add'>+			marvell,pins = "mpp37", "mpp38";</div><div class='add'>+			marvell,function = "i2c0";</div><div class='add'>+		};</div><div class='add'>+		cp2_sdhci_pins: cp2-sdhi-pins-0 {</div><div class='add'>+			marvell,pins = "mpp56", "mpp57", "mpp58",</div><div class='add'>+				       "mpp59", "mpp60", "mpp61";</div><div class='add'>+			marvell,function = "sdio";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp2_utmi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp2_usb3_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	usb-phy = &lt;&amp;cp2_usb3_0_phy0&gt;;</div><div class='add'>+	phys = &lt;&amp;cp2_utmi0&gt;;</div><div class='add'>+	phy-names = "usb";</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SLM-1521-V2, CON11 */</div><div class='add'>+&amp;cp2_usb3_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	usb-phy = &lt;&amp;cp2_usb3_0_phy1&gt;;</div><div class='add'>+	/* Generic PHY, providing serdes lanes */</div><div class='add'>+	phys = &lt;&amp;cp2_comphy3 1&gt;, &lt;&amp;cp2_utmi1&gt;;</div><div class='add'>+	phy-names = "usb", "utmi";</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/cn9132-sr-cex7.dtsi b/arch/arm64/boot/dts/marvell/cn9132-sr-cex7.dtsi<br/>new file mode 100644<br/>index 000000000000..91ba5f7dc9b4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/cn9132-sr-cex7.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/cn9132-sr-cex7.dtsi</a></div><div class='hunk'>@@ -0,0 +1,720 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2024 Josua Mayer &lt;josua@solid-run.com&gt;</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Instantiate the first external CP115</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#define CP11X_NAME		cp1</div><div class='add'>+#define CP11X_BASE		f4000000</div><div class='add'>+#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))</div><div class='add'>+#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000</div><div class='add'>+#define CP11X_PCIE0_BASE	f4600000</div><div class='add'>+#define CP11X_PCIE1_BASE	f4620000</div><div class='add'>+#define CP11X_PCIE2_BASE	f4640000</div><div class='add'>+</div><div class='add'>+#include "armada-cp115.dtsi"</div><div class='add'>+</div><div class='add'>+#undef CP11X_NAME</div><div class='add'>+#undef CP11X_BASE</div><div class='add'>+#undef CP11X_PCIEx_MEM_BASE</div><div class='add'>+#undef CP11X_PCIEx_MEM_SIZE</div><div class='add'>+#undef CP11X_PCIE0_BASE</div><div class='add'>+#undef CP11X_PCIE1_BASE</div><div class='add'>+#undef CP11X_PCIE2_BASE</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Instantiate the second external CP115</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#define CP11X_NAME		cp2</div><div class='add'>+#define CP11X_BASE		f6000000</div><div class='add'>+#define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000))</div><div class='add'>+#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000</div><div class='add'>+#define CP11X_PCIE0_BASE	f6600000</div><div class='add'>+#define CP11X_PCIE1_BASE	f6620000</div><div class='add'>+#define CP11X_PCIE2_BASE	f6640000</div><div class='add'>+</div><div class='add'>+#include "armada-cp115.dtsi"</div><div class='add'>+</div><div class='add'>+#undef CP11X_NAME</div><div class='add'>+#undef CP11X_BASE</div><div class='add'>+#undef CP11X_PCIEx_MEM_BASE</div><div class='add'>+#undef CP11X_PCIEx_MEM_SIZE</div><div class='add'>+#undef CP11X_PCIE0_BASE</div><div class='add'>+#undef CP11X_PCIE1_BASE</div><div class='add'>+#undef CP11X_PCIE2_BASE</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "SolidRun CN9132 COM Express Type 7 Module";</div><div class='add'>+	compatible = "solidrun,cn9132-sr-cex7", "marvell,cn9130";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;cp0_eth1;</div><div class='add'>+		gpio3 = &amp;cp1_gpio1;</div><div class='add'>+		gpio4 = &amp;cp1_gpio2;</div><div class='add'>+		gpio5 = &amp;cp2_gpio1;</div><div class='add'>+		gpio6 = &amp;cp2_gpio2;</div><div class='add'>+		i2c0 = &amp;cp0_i2c0;</div><div class='add'>+		i2c1 = &amp;cp0_i2c1;</div><div class='add'>+		i2c2 = &amp;com_clkgen_i2c;</div><div class='add'>+		i2c3 = &amp;com_10g_led_i2c;</div><div class='add'>+		i2c4 = &amp;com_10g_sfp_i2c0;</div><div class='add'>+		i2c5 = &amp;com_smbus;</div><div class='add'>+		i2c6 = &amp;com_fanctrl_i2c;</div><div class='add'>+		mmc0 = &amp;ap_sdhci0;</div><div class='add'>+		rtc0 = &amp;cp0_rtc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fan: pwm-fan {</div><div class='add'>+		compatible = "pwm-fan";</div><div class='add'>+		cooling-levels = &lt;0 51 102 153 204 255&gt;;</div><div class='add'>+		#cooling-cells = &lt;2&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;cp0_fan_pwm_pins &amp;cp0_fan_tacho_pins&gt;;</div><div class='add'>+		pwms = &lt;&amp;cp0_gpio2 7 40000&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;cp0_gpio1&gt;;</div><div class='add'>+		interrupts = &lt;26 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	v_1_8: regulator-1-8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "1v8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ap_vhv: regulator-ap-vhv-1-8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "ap-vhv-1v8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;cp0_reg_ap_vhv_pins&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		gpios = &lt;&amp;cp0_gpio2 21 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cp_vhv: regulator-cp-vhv-1-8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "cp-vhv-1v8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;cp0_reg_cp_vhv_pins&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		gpios = &lt;&amp;cp0_gpio2 17 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ap_pinctrl {</div><div class='add'>+	ap_mmc0_pins: ap-mmc0-pins {</div><div class='add'>+		marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", "mpp4", "mpp5",</div><div class='add'>+					   "mpp6", "mpp7", "mpp8", "mpp9", "mpp10", "mpp12";</div><div class='add'>+		marvell,function = "sdio";</div><div class='add'>+		/*</div><div class='add'>+		 * mpp12 is emmc reset, function should be sdio (hw_rst),</div><div class='add'>+		 * but pinctrl-mvebu does not support this.</div><div class='add'>+		 *</div><div class='add'>+		 * From pinctrl-mvebu.h:</div><div class='add'>+		 * "The name will be used to switch to this setting in DT description, e.g.</div><div class='add'>+		 * marvell,function = "uart2". subname is only for debugging purposes."</div><div class='add'>+		 */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ap_sdhci0 {</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;ap_mmc0_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	vqmmc-supply = &lt;&amp;v_1_8&gt;;</div><div class='add'>+	/*</div><div class='add'>+	 * Not stable in HS modes - phy needs "more calibration", so disable</div><div class='add'>+	 * UHS (by preventing voltage switch), SDR104, SDR50 and DDR50 modes.</div><div class='add'>+	 */</div><div class='add'>+	no-1-8-v;</div><div class='add'>+	no-sd;</div><div class='add'>+	no-sdio;</div><div class='add'>+	non-removable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ap_thermal_ic {</div><div class='add'>+	polling-delay = &lt;1000&gt;;</div><div class='add'>+</div><div class='add'>+	trips {</div><div class='add'>+		ap_active: trip-active {</div><div class='add'>+			temperature = &lt;40000&gt;;</div><div class='add'>+			hysteresis = &lt;4000&gt;;</div><div class='add'>+			type = "active";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cooling-maps {</div><div class='add'>+		map0 {</div><div class='add'>+			trip = &lt;&amp;ap_active&gt;;</div><div class='add'>+			cooling-device = &lt;&amp;fan THERMAL_NO_LIMIT 4&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		map1 {</div><div class='add'>+			trip = &lt;&amp;ap_crit&gt;;</div><div class='add'>+			cooling-device = &lt;&amp;fan 4 5&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_ethernet {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_eth1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp0_eth1_pins&gt;;</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy = &lt;&amp;cp0_eth_phy0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_gpio1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Tacho signal used as interrupt source by pwm-fan driver.</div><div class='add'>+	 * Hog IO as input to ensure mvebu-gpio irq driver`s</div><div class='add'>+	 * irq_set_type can succeed.</div><div class='add'>+	 */</div><div class='add'>+	pwm-tacho-irq-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;26 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+		input;</div><div class='add'>+		line-name = "fan-tacho";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_gpio2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_i2c0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp0_i2c0_pins&gt;;</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	com_eeprom: eeprom@50 {</div><div class='add'>+		compatible = "atmel,24c02";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		pagesize = &lt;8&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@53 {</div><div class='add'>+		compatible = "atmel,spd";</div><div class='add'>+		reg = &lt;0x53&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_i2c1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp0_i2c1_pins&gt;;</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	i2c-mux@77 {</div><div class='add'>+		compatible = "nxp,pca9547";</div><div class='add'>+		reg = &lt;0x77&gt;;</div><div class='add'>+		i2c-mux-idle-disconnect;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		com_clkgen_i2c: i2c@0 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			/* clock-controller@6b */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		com_10g_led_i2c: i2c@1 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			/* Routed to B2B Connector as I2C_10G_LED_SCL/SDA */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		com_10g_sfp_i2c0: i2c@2 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			/* Routed to B2B Connector as I2C_SFP0_CP0_SCL/SDA */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		com_smbus: i2c@3 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+			/* Routed to B2B Connector as SBM_CLK/DAT */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		com_fanctrl_i2c: i2c@4 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+			/* fan-controller@2f (assembly option) */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_mdio {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp0_mdio_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	cp0_eth_phy0: ethernet-phy@0 {</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_spi1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp0_spi1_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		/* read command supports max. 50MHz */</div><div class='add'>+		spi-max-frequency = &lt;50000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_syscon0 {</div><div class='add'>+	cp0_pinctrl: pinctrl {</div><div class='add'>+		compatible = "marvell,cp115-standalone-pinctrl";</div><div class='add'>+</div><div class='add'>+		com_10g_int0_pins: cp0-10g-int-pins {</div><div class='add'>+			marvell,pins = "mpp24";</div><div class='add'>+			marvell,function = "gpio";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp0_eth1_pins: cp0-eth1-pins {</div><div class='add'>+			marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",</div><div class='add'>+				       "mpp4", "mpp5", "mpp6", "mpp7",</div><div class='add'>+				       "mpp8", "mpp9", "mpp10", "mpp11";</div><div class='add'>+			/* docs call it "ge1", but cp110-pinctrl "ge0" */</div><div class='add'>+			marvell,function = "ge0";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp0_fan_pwm_pins: cp0-fan-pwm-pins {</div><div class='add'>+			marvell,pins = "mpp39";</div><div class='add'>+			marvell,function = "gpio";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp0_fan_tacho_pins: cp0-fan-tacho-pins {</div><div class='add'>+			marvell,pins = "mpp26";</div><div class='add'>+			marvell,function = "gpio";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp0_i2c0_pins: cp0-i2c0-pins {</div><div class='add'>+			marvell,pins = "mpp37", "mpp38";</div><div class='add'>+			marvell,function = "i2c0";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp0_i2c1_pins: cp0-i2c1-pins {</div><div class='add'>+			marvell,pins = "mpp35", "mpp36";</div><div class='add'>+			marvell,function = "i2c1";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp0_mdio_pins: cp0-mdio-pins {</div><div class='add'>+			marvell,pins = "mpp40", "mpp41";</div><div class='add'>+			marvell,function = "ge";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp0_mmc0_pins: cp0-mmc0-pins {</div><div class='add'>+			marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59",</div><div class='add'>+				       "mpp60", "mpp61";</div><div class='add'>+			marvell,function = "sdio";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp0_mmc0_cd_pins: cp0-mmc0-cd-pins {</div><div class='add'>+			marvell,pins = "mpp55";</div><div class='add'>+			marvell,function = "sdio_cd";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp0_pwrbtn_pins:  cp0-pwrbtn-pins {</div><div class='add'>+			marvell,pins = "mpp31";</div><div class='add'>+			marvell,function = "gpio";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp0_reg_ap_vhv_pins: cp0-reg-ap-vhv-pins {</div><div class='add'>+			marvell,pins = "mpp53";</div><div class='add'>+			marvell,function = "gpio";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp0_reg_cp_vhv_pins: cp0-reg-cp-vhv-pins {</div><div class='add'>+			marvell,pins = "mpp49";</div><div class='add'>+			marvell,function = "gpio";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp0_spi1_pins: cp0-spi1-pins {</div><div class='add'>+			marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";</div><div class='add'>+			marvell,function = "spi1";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp0_spi1_cs1_pins: cp0-spi1-cs1-pins {</div><div class='add'>+			marvell,pins = "mpp12";</div><div class='add'>+			marvell,function = "spi1";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp0_uart2_pins: cp0-uart2-pins  {</div><div class='add'>+			marvell,pins = "mpp50", "mpp51";</div><div class='add'>+			marvell,function = "uart2";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_thermal_ic {</div><div class='add'>+	polling-delay = &lt;1000&gt;;</div><div class='add'>+</div><div class='add'>+	trips {</div><div class='add'>+		cp0_active: trip-active {</div><div class='add'>+			temperature = &lt;40000&gt;;</div><div class='add'>+			hysteresis = &lt;4000&gt;;</div><div class='add'>+			type = "active";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cooling-maps {</div><div class='add'>+		map0 {</div><div class='add'>+			trip = &lt;&amp;cp0_active&gt;;</div><div class='add'>+			cooling-device = &lt;&amp;fan THERMAL_NO_LIMIT 4&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		map1 {</div><div class='add'>+			trip = &lt;&amp;cp0_crit&gt;;</div><div class='add'>+			cooling-device = &lt;&amp;fan 4 5&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB-2.0 Host */</div><div class='add'>+&amp;cp0_usb3_0 {</div><div class='add'>+	phys = &lt;&amp;cp0_utmi0&gt;;</div><div class='add'>+	phy-names = "utmi";</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB-2.0 Host */</div><div class='add'>+&amp;cp0_usb3_1 {</div><div class='add'>+	phys = &lt;&amp;cp0_utmi1&gt;;</div><div class='add'>+	phy-names = "utmi";</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp0_utmi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp1_gpio1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp1_gpio2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp1_rtc {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp1_spi1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;cp1_spi1_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	tpm@0 {</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		compatible = "infineon,slb9670", "tcg,tpm_tis-spi";</div><div class='add'>+		spi-max-frequency = &lt;10000000&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;cp1_tpm_irq_pins&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;cp1_gpio1&gt;;</div><div class='add'>+		interrupts = &lt;17 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp1_syscon0 {</div><div class='add'>+	cp1_pinctrl: pinctrl {</div><div class='add'>+		compatible = "marvell,cp115-standalone-pinctrl";</div><div class='add'>+</div><div class='add'>+		com_10g_int1_pins: cp1-10g-int-pins {</div><div class='add'>+			marvell,pins = "mpp50";</div><div class='add'>+			marvell,function = "gpio";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp1_10g_phy_rst_01_pins: cp1-10g-phy-rst-01-pins {</div><div class='add'>+			marvell,pins = "mpp43";</div><div class='add'>+			marvell,function = "gpio";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp1_10g_phy_rst_23_pins: cp1-10g-phy-rst-23-pins {</div><div class='add'>+			marvell,pins = "mpp42";</div><div class='add'>+			marvell,function = "gpio";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp1_batlow_pins: cp1-batlow-pins {</div><div class='add'>+			marvell,pins = "mpp11";</div><div class='add'>+			marvell,function = "gpio";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp1_rsvd16_pins: cp1-rsvd16-pins {</div><div class='add'>+			marvell,pins = "mpp29";</div><div class='add'>+			marvell,function = "gpio";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp1_sata_act_pins: cp1-sata-act-pins {</div><div class='add'>+			marvell,pins = "mpp39";</div><div class='add'>+			marvell,function = "gpio";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp1_spi1_pins: cp1-spi1-pins {</div><div class='add'>+			marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";</div><div class='add'>+			marvell,function = "spi1";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp1_thrm_irq_pins: cp1-thrm-irq-pins {</div><div class='add'>+			marvell,pins = "mpp34";</div><div class='add'>+			marvell,function = "gpio";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp1_thrm_trip_pins: cp1-thrm-trip-pins {</div><div class='add'>+			marvell,pins = "mpp33";</div><div class='add'>+			marvell,function = "gpio";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp1_tpm_irq_pins: cp1-tpm-irq-pins {</div><div class='add'>+			marvell,pins = "mpp17";</div><div class='add'>+			marvell,function = "gpio";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp1_wake0_pins: cp1-wake0-pins {</div><div class='add'>+			marvell,pins = "mpp40";</div><div class='add'>+			marvell,function = "gpio";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp1_wake1_pins: cp1-wake1-pins {</div><div class='add'>+			marvell,pins = "mpp51";</div><div class='add'>+			marvell,function = "gpio";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp1_xmdio_pins: cp1-xmdio-pins {</div><div class='add'>+			marvell,pins = "mpp37", "mpp38";</div><div class='add'>+			marvell,function = "xg";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp1_thermal_ic {</div><div class='add'>+	polling-delay = &lt;1000&gt;;</div><div class='add'>+</div><div class='add'>+	trips {</div><div class='add'>+		cp1_active: trip-active {</div><div class='add'>+			temperature = &lt;40000&gt;;</div><div class='add'>+			hysteresis = &lt;4000&gt;;</div><div class='add'>+			type = "active";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cooling-maps {</div><div class='add'>+		map0 {</div><div class='add'>+			trip = &lt;&amp;cp1_active&gt;;</div><div class='add'>+			cooling-device = &lt;&amp;fan THERMAL_NO_LIMIT 4&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		map1 {</div><div class='add'>+			trip = &lt;&amp;cp1_crit&gt;;</div><div class='add'>+			cooling-device = &lt;&amp;fan 4 5&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB-2.0 Host */</div><div class='add'>+&amp;cp1_usb3_0 {</div><div class='add'>+	phys = &lt;&amp;cp1_utmi0&gt;;</div><div class='add'>+	phy-names = "utmi";</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp1_utmi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp2_ethernet {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp2_gpio1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp2_gpio2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp2_rtc {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp2_syscon0 {</div><div class='add'>+	cp2_pinctrl: pinctrl {</div><div class='add'>+		compatible = "marvell,cp115-standalone-pinctrl";</div><div class='add'>+</div><div class='add'>+		com_10g_int2_pins: cp2-10g-int-pins {</div><div class='add'>+			marvell,pins = "mpp50";</div><div class='add'>+			marvell,function = "gpio";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp2_rsvd0_pins: cp2-rsvd0-pins {</div><div class='add'>+			marvell,pins = "mpp0";</div><div class='add'>+			marvell,function = "gpio";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp2_rsvd1_pins: cp2-rsvd1-pins {</div><div class='add'>+			marvell,pins = "mpp1";</div><div class='add'>+			marvell,function = "gpio";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp2_rsvd2_pins: cp2-rsvd2-pins {</div><div class='add'>+			marvell,pins = "mpp2";</div><div class='add'>+			marvell,function = "gpio";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp2_rsvd3_pins: cp2-rsvd3-pins {</div><div class='add'>+			marvell,pins = "mpp3";</div><div class='add'>+			marvell,function = "gpio";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp2_rsvd4_pins: cp2-rsvd4-pins {</div><div class='add'>+			marvell,pins = "mpp4";</div><div class='add'>+			marvell,function = "gpio";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp2_rsvd5_pins: cp2-rsvd5-pins {</div><div class='add'>+			marvell,pins = "mpp54";</div><div class='add'>+			marvell,function = "gpio";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp2_rsvd7_pins: cp2-rsvd7-pins {</div><div class='add'>+			marvell,pins = "mpp7";</div><div class='add'>+			marvell,function = "gpio";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp2_rsvd8_pins: cp2-rsvd8-pins {</div><div class='add'>+			marvell,pins = "mpp8";</div><div class='add'>+			marvell,function = "gpio";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp2_rsvd9_pins: cp2-rsvd9-pins {</div><div class='add'>+			marvell,pins = "mpp9";</div><div class='add'>+			marvell,function = "gpio";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp2_rsvd10_pins: cp2-rsvd10-pins {</div><div class='add'>+			marvell,pins = "mpp10";</div><div class='add'>+			marvell,function = "gpio";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp2_rsvd11_pins: cp2-rsvd11-pins {</div><div class='add'>+			marvell,pins = "mpp11";</div><div class='add'>+			marvell,function = "gpio";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp2_rsvd27_pins: cp2-rsvd27-pins {</div><div class='add'>+			marvell,pins = "mpp11";</div><div class='add'>+			marvell,function = "gpio";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp2_rsvd31_pins: cp2-rsvd31-pins {</div><div class='add'>+			marvell,pins = "mpp31";</div><div class='add'>+			marvell,function = "gpio";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp2_rsvd32_pins: cp2-rsvd32-pins {</div><div class='add'>+			marvell,pins = "mpp32";</div><div class='add'>+			marvell,function = "gpio";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp2_rsvd55_pins: cp2-rsvd55-pins {</div><div class='add'>+			marvell,pins = "mpp55";</div><div class='add'>+			marvell,function = "gpio";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp2_rsvd56_pins: cp2-rsvd56-pins {</div><div class='add'>+			marvell,pins = "mpp56";</div><div class='add'>+			marvell,function = "gpio";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cp2_xmdio_pins: cp2-xmdio-pins {</div><div class='add'>+			marvell,pins = "mpp37", "mpp38";</div><div class='add'>+			marvell,function = "xg";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp2_thermal_ic {</div><div class='add'>+	polling-delay = &lt;1000&gt;;</div><div class='add'>+</div><div class='add'>+	trips {</div><div class='add'>+		cp2_active: trip-active {</div><div class='add'>+			temperature = &lt;40000&gt;;</div><div class='add'>+			hysteresis = &lt;4000&gt;;</div><div class='add'>+			type = "active";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cooling-maps {</div><div class='add'>+		map0 {</div><div class='add'>+			trip = &lt;&amp;cp2_active&gt;;</div><div class='add'>+			cooling-device = &lt;&amp;fan THERMAL_NO_LIMIT 4&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		map1 {</div><div class='add'>+			trip = &lt;&amp;cp2_crit&gt;;</div><div class='add'>+			cooling-device = &lt;&amp;fan 4 5&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB-2.0/3.0 Host */</div><div class='add'>+&amp;cp2_usb3_0 {</div><div class='add'>+	phys = &lt;&amp;cp2_utmi0&gt;, &lt;&amp;cp2_comphy1 0&gt;;</div><div class='add'>+	phy-names = "utmi", "comphy";</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cp2_utmi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* AP default console */</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart0_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/mmp/Makefile b/arch/arm64/boot/dts/marvell/mmp/Makefile<br/>new file mode 100644<br/>index 000000000000..103175ed63b0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/mmp/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/mmp/Makefile</a></div><div class='hunk'>@@ -0,0 +1,2 @@</div><div class='add'>+# SPDX-License-Identifier: GPL-2.0</div><div class='add'>+dtb-$(CONFIG_ARCH_MMP) += pxa1908-samsung-coreprimevelte.dtb</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/mmp/pxa1908-samsung-coreprimevelte.dts b/arch/arm64/boot/dts/marvell/mmp/pxa1908-samsung-coreprimevelte.dts<br/>new file mode 100644<br/>index 000000000000..b2ce5edd9c6a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/mmp/pxa1908-samsung-coreprimevelte.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/mmp/pxa1908-samsung-coreprimevelte.dts</a></div><div class='hunk'>@@ -0,0 +1,530 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+#include "pxa1908.dtsi"</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/linux-event-codes.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Samsung Galaxy Core Prime VE LTE";</div><div class='add'>+	compatible = "samsung,coreprimevelte", "marvell,pxa1908";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		mmc0 = &amp;sdh2; /* eMMC */</div><div class='add'>+		mmc1 = &amp;sdh0; /* SD card */</div><div class='add'>+		mmc2 = &amp;sdh1; /* SDIO */</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+</div><div class='add'>+		fb0: framebuffer@17177000 {</div><div class='add'>+			compatible = "simple-framebuffer";</div><div class='add'>+			reg = &lt;0 0x17177000 0 (480 * 800 * 4)&gt;;</div><div class='add'>+			power-domains = &lt;&amp;apmu PXA1908_POWER_DOMAIN_DSI&gt;;</div><div class='add'>+			width = &lt;480&gt;;</div><div class='add'>+			height = &lt;800&gt;;</div><div class='add'>+			stride = &lt;(480 * 4)&gt;;</div><div class='add'>+			format = "a8r8g8b8";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0 0 0 0x40000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		/*</div><div class='add'>+		 * Reserved by the vendor bootloader as a "secure region".</div><div class='add'>+		 *</div><div class='add'>+		 * TODO: See if the responsible stage of the bootloader can be</div><div class='add'>+		 * replaced</div><div class='add'>+		 */</div><div class='add'>+		secure-region@0 {</div><div class='add'>+			reg = &lt;0 0 0 0x1000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		framebuffer@17000000 {</div><div class='add'>+			reg = &lt;0 0x17000000 0 0x1800000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c-muic {</div><div class='add'>+		compatible = "i2c-gpio";</div><div class='add'>+		sda-gpios = &lt;&amp;gpio 30 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+		scl-gpios = &lt;&amp;gpio 29 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+		i2c-gpio,delay-us = &lt;3&gt;;</div><div class='add'>+		i2c-gpio,timeout-ms = &lt;100&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;i2c_muic_pins&gt;;</div><div class='add'>+</div><div class='add'>+		muic: extcon@14 {</div><div class='add'>+			compatible = "siliconmitus,sm5504-muic";</div><div class='add'>+			reg = &lt;0x14&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio&gt;;</div><div class='add'>+			interrupts = &lt;0 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+</div><div class='add'>+			usb_con: connector {</div><div class='add'>+				compatible = "usb-b-connector";</div><div class='add'>+				label = "micro-USB";</div><div class='add'>+				type = "micro";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;gpio_keys_pins&gt;;</div><div class='add'>+		autorepeat;</div><div class='add'>+</div><div class='add'>+		key-home {</div><div class='add'>+			label = "Home";</div><div class='add'>+			linux,code = &lt;KEY_HOME&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio 50 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-volup {</div><div class='add'>+			label = "Volume Up";</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio 16 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-voldown {</div><div class='add'>+			label = "Volume Down";</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio 17 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	backlight {</div><div class='add'>+		compatible = "kinetic,ktd2801";</div><div class='add'>+		ctrl-gpios = &lt;&amp;gpio 97 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		max-brightness = &lt;210&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vibrator {</div><div class='add'>+		compatible = "pwm-vibrator";</div><div class='add'>+		pwm-names = "enable";</div><div class='add'>+		pwms = &lt;&amp;pwm3 100000&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;gpio 20 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;vibrator_pin&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;smmu {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pmx {</div><div class='add'>+	pinctrl-single,gpio-range = &lt;&amp;range 55 55 0&gt;,</div><div class='add'>+				    &lt;&amp;range 110 32 0&gt;,</div><div class='add'>+				    &lt;&amp;range 52 1 0&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;board_pins_0 &amp;board_pins_1 &amp;board_pins_2&gt;;</div><div class='add'>+</div><div class='add'>+	board_pins_0: board-pins-0 {</div><div class='add'>+		pinctrl-single,pins = &lt;</div><div class='add'>+			0x160 0</div><div class='add'>+			0x164 0</div><div class='add'>+			0x168 0</div><div class='add'>+			0x16c 0</div><div class='add'>+		&gt;;</div><div class='add'>+		pinctrl-single,drive-strength = &lt;0x1000 0x1800&gt;;</div><div class='add'>+		pinctrl-single,bias-pullup = &lt;0x8000 0x8000 0 0xc000&gt;;</div><div class='add'>+		pinctrl-single,bias-pulldown = &lt;0x8000 0x8000 0 0xa000&gt;;</div><div class='add'>+		pinctrl-single,input-schmitt = &lt;0 0x30&gt;;</div><div class='add'>+		pinctrl-single,input-schmitt-enable = &lt;0x40 0 0x40 0x40&gt;;</div><div class='add'>+		pinctrl-single,low-power-mode = &lt;0x288 0x388&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	board_pins_1: board-pins-1 {</div><div class='add'>+		pinctrl-single,pins = &lt;</div><div class='add'>+			0x44 1</div><div class='add'>+			0x48 1</div><div class='add'>+			0x20 1</div><div class='add'>+			0x18 1</div><div class='add'>+			0x14 1</div><div class='add'>+			0x10 1</div><div class='add'>+			0xc 1</div><div class='add'>+			0x8 1</div><div class='add'>+			0x68 1</div><div class='add'>+			0x58 0</div><div class='add'>+			0x54 0</div><div class='add'>+			0x7c 0</div><div class='add'>+			0x6c 0</div><div class='add'>+			0x70 0</div><div class='add'>+			0x4c 1</div><div class='add'>+			0x50 1</div><div class='add'>+			0xac 0</div><div class='add'>+			0x90 0</div><div class='add'>+			0x8c 0</div><div class='add'>+			0x88 0</div><div class='add'>+			0x84 0</div><div class='add'>+			0xc8 0</div><div class='add'>+			0x128 0</div><div class='add'>+			0x190 0</div><div class='add'>+			0x194 0</div><div class='add'>+			0x1a0 0</div><div class='add'>+			0x114 0</div><div class='add'>+			0x118 0</div><div class='add'>+			0x1d8 0</div><div class='add'>+			0x1e4 0</div><div class='add'>+			0xe8 0</div><div class='add'>+			0x100 0</div><div class='add'>+			0x204 0</div><div class='add'>+			0x210 0</div><div class='add'>+			0x218 0</div><div class='add'>+		&gt;;</div><div class='add'>+		pinctrl-single,bias-pullup = &lt;0xc000 0xc000 0 0xc000&gt;;</div><div class='add'>+		pinctrl-single,bias-pulldown = &lt;0x8000 0xa000 0x8000 0xc000&gt;;</div><div class='add'>+		pinctrl-single,low-power-mode = &lt;0x288 0x388&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	board_pins_2: board-pins-2 {</div><div class='add'>+		pinctrl-single,pins = &lt;</div><div class='add'>+			0x260 0</div><div class='add'>+			0x264 0</div><div class='add'>+			0x268 0</div><div class='add'>+			0x26c 0</div><div class='add'>+			0x270 0</div><div class='add'>+			0x274 0</div><div class='add'>+			0x78 0</div><div class='add'>+			0x74 0</div><div class='add'>+			0xb0 1</div><div class='add'>+		&gt;;</div><div class='add'>+		pinctrl-single,drive-strength = &lt;0x1000 0x1800&gt;;</div><div class='add'>+		pinctrl-single,bias-pullup = &lt;0 0xc000 0 0xc000&gt;;</div><div class='add'>+		pinctrl-single,bias-pulldown = &lt;0 0xa000 0 0xa000&gt;;</div><div class='add'>+		pinctrl-single,input-schmitt = &lt;0 0x30&gt;;</div><div class='add'>+		pinctrl-single,input-schmitt-enable = &lt;0x40 0 0x40 0x40&gt;;</div><div class='add'>+		pinctrl-single,low-power-mode = &lt;0 0x388&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart0_pins: uart0-pins {</div><div class='add'>+		pinctrl-single,pins = &lt;</div><div class='add'>+			0x198 6</div><div class='add'>+			0x19c 6</div><div class='add'>+		&gt;;</div><div class='add'>+		pinctrl-single,drive-strength = &lt;0x1000 0x1800&gt;;</div><div class='add'>+		pinctrl-single,bias-pullup = &lt;0 0xc000 0 0xc000&gt;;</div><div class='add'>+		pinctrl-single,bias-pulldown = &lt;0 0xa000 0 0xa000&gt;;</div><div class='add'>+		pinctrl-single,input-schmitt = &lt;0 0x30&gt;;</div><div class='add'>+		pinctrl-single,input-schmitt-enable = &lt;0x40 0 0x40 0x40&gt;;</div><div class='add'>+		pinctrl-single,low-power-mode = &lt;0 0x388&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio_keys_pins: gpio-keys-pins {</div><div class='add'>+		pinctrl-single,pins = &lt;</div><div class='add'>+			0x11c 0</div><div class='add'>+			0x120 0</div><div class='add'>+			0x1a4 0</div><div class='add'>+		&gt;;</div><div class='add'>+		pinctrl-single,drive-strength = &lt;0x1000 0x1800&gt;;</div><div class='add'>+		pinctrl-single,bias-pullup = &lt;0xc000 0xc000 0 0xc000&gt;;</div><div class='add'>+		pinctrl-single,bias-pulldown = &lt;0x8000 0xa0000 0x8000 0xa000&gt;;</div><div class='add'>+		pinctrl-single,input-schmitt = &lt;0 0x30&gt;;</div><div class='add'>+		pinctrl-single,input-schmitt-enable = &lt;0x40 0 0x40 0x40&gt;;</div><div class='add'>+		pinctrl-single,low-power-mode = &lt;0 0x388&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c_muic_pins: i2c-muic-pins {</div><div class='add'>+		pinctrl-single,pins = &lt;</div><div class='add'>+			0x154 0</div><div class='add'>+			0x150 0</div><div class='add'>+		&gt;;</div><div class='add'>+		pinctrl-single,drive-strength = &lt;0x1000 0x1800&gt;;</div><div class='add'>+		pinctrl-single,bias-pullup = &lt;0 0xc000 0 0xc000&gt;;</div><div class='add'>+		pinctrl-single,bias-pulldown = &lt;0 0xa000 0 0xa000&gt;;</div><div class='add'>+		pinctrl-single,input-schmitt = &lt;0 0x30&gt;;</div><div class='add'>+		pinctrl-single,input-schmitt-enable = &lt;0x40 0 0x40 0x40&gt;;</div><div class='add'>+		pinctrl-single,low-power-mode = &lt;0x288 0x388&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdh0_pins_0: sdh0-pins-0 {</div><div class='add'>+		pinctrl-single,pins = &lt;</div><div class='add'>+			0x108 0</div><div class='add'>+		&gt;;</div><div class='add'>+		pinctrl-single,drive-strength = &lt;0x1000 0x1800&gt;;</div><div class='add'>+		pinctrl-single,bias-pullup = &lt;0xc000 0xc000 0 0xc000&gt;;</div><div class='add'>+		pinctrl-single,bias-pulldown = &lt;0x8000 0xa000 0x8000 0xa000&gt;;</div><div class='add'>+		pinctrl-single,input-schmitt = &lt;0 0x30&gt;;</div><div class='add'>+		pinctrl-single,input-schmitt-enable = &lt;0x40 0 0x40 0x40&gt;;</div><div class='add'>+		pinctrl-single,low-power-mode = &lt;0 0x388&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdh0_pins_1: sdh0-pins-1 {</div><div class='add'>+		pinctrl-single,pins = &lt;</div><div class='add'>+			0x94 0</div><div class='add'>+			0x98 0</div><div class='add'>+			0x9c 0</div><div class='add'>+			0xa0 0</div><div class='add'>+			0xa4 0</div><div class='add'>+		&gt;;</div><div class='add'>+		pinctrl-single,drive-strength = &lt;0x800 0x1800&gt;;</div><div class='add'>+		pinctrl-single,bias-pullup = &lt;0xc000 0xc000 0 0xc000&gt;;</div><div class='add'>+		pinctrl-single,bias-pulldown = &lt;0x8000 0xa000 0x8000 0xa000&gt;;</div><div class='add'>+		pinctrl-single,input-schmitt = &lt;0 0x30&gt;;</div><div class='add'>+		pinctrl-single,input-schmitt-enable = &lt;0x40 0 0x40 0x40&gt;;</div><div class='add'>+		pinctrl-single,low-power-mode = &lt;0 0x388&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdh0_pins_2: sdh0-pins-2 {</div><div class='add'>+		pinctrl-single,pins = &lt;</div><div class='add'>+			0xa8 0</div><div class='add'>+		&gt;;</div><div class='add'>+		pinctrl-single,drive-strength = &lt;0x1000 0x1800&gt;;</div><div class='add'>+		pinctrl-single,bias-pullup = &lt;0 0xc000 0 0xc000&gt;;</div><div class='add'>+		pinctrl-single,bias-pulldown = &lt;0 0xa000 0 0xa000&gt;;</div><div class='add'>+		pinctrl-single,input-schmitt = &lt;0 0x30&gt;;</div><div class='add'>+		pinctrl-single,input-schmitt-enable = &lt;0x40 0 0x40 0x40&gt;;</div><div class='add'>+		pinctrl-single,low-power-mode = &lt;0x208 0x388&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdh1_pins_0: sdh1-pins-0 {</div><div class='add'>+		pinctrl-single,pins = &lt;</div><div class='add'>+			0x170 1</div><div class='add'>+			0x174 1</div><div class='add'>+			0x178 1</div><div class='add'>+			0x17c 1</div><div class='add'>+			0x180 1</div><div class='add'>+		&gt;;</div><div class='add'>+		pinctrl-single,drive-strength = &lt;0x1000 0x1800&gt;;</div><div class='add'>+		pinctrl-single,bias-pullup = &lt;0 0xc000 0 0xc000&gt;;</div><div class='add'>+		pinctrl-single,bias-pulldown = &lt;0 0xa000 0 0xa000&gt;;</div><div class='add'>+		pinctrl-single,input-schmitt = &lt;0 0x30&gt;;</div><div class='add'>+		pinctrl-single,input-schmitt-enable = &lt;0x40 0 0x40 0x40&gt;;</div><div class='add'>+		pinctrl-single,low-power-mode = &lt;0 0x388&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdh1_pins_1: sdh1-pins-1 {</div><div class='add'>+		pinctrl-single,pins = &lt;0x184 1&gt;;</div><div class='add'>+		pinctrl-single,drive-strength = &lt;0 0x1800&gt;;</div><div class='add'>+		pinctrl-single,bias-pullup = &lt;0 0xc000 0 0xc000&gt;;</div><div class='add'>+		pinctrl-single,bias-pulldown = &lt;0 0xa000 0 0xa000&gt;;</div><div class='add'>+		pinctrl-single,input-schmitt = &lt;0 0x30&gt;;</div><div class='add'>+		pinctrl-single,input-schmitt-enable = &lt;0x40 0 0x40 0x40&gt;;</div><div class='add'>+		pinctrl-single,low-power-mode = &lt;0x208 0x388&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdh1_pins_2: sdh1-pins-2 {</div><div class='add'>+		pinctrl-single,pins = &lt;0xec 0&gt;;</div><div class='add'>+		pinctrl-single,drive-strength = &lt;0x1000 0x1800&gt;;</div><div class='add'>+		pinctrl-single,bias-pullup = &lt;0x8000 0x8000 0 0xc000&gt;;</div><div class='add'>+		pinctrl-single,bias-pulldown = &lt;0x8000 0x8000 0 0xa000&gt;;</div><div class='add'>+		pinctrl-single,input-schmitt = &lt;0 0x30&gt;;</div><div class='add'>+		pinctrl-single,input-schmitt-enable = &lt;0x40 0 0x40 0x40&gt;;</div><div class='add'>+		pinctrl-single,low-power-mode = &lt;0 0x388&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdh1_fast_pins_0: sdh1-fast-pins-0 {</div><div class='add'>+		pinctrl-single,pins = &lt;</div><div class='add'>+			0x170 1</div><div class='add'>+			0x174 1</div><div class='add'>+			0x178 1</div><div class='add'>+			0x17c 1</div><div class='add'>+			0x180 1</div><div class='add'>+		&gt;;</div><div class='add'>+		pinctrl-single,drive-strength = &lt;0x1800 0x1800&gt;;</div><div class='add'>+		pinctrl-single,bias-pullup = &lt;0 0xc000 0 0xc000&gt;;</div><div class='add'>+		pinctrl-single,bias-pulldown = &lt;0 0xa000 0 0xa000&gt;;</div><div class='add'>+		pinctrl-single,input-schmitt = &lt;0 0x30&gt;;</div><div class='add'>+		pinctrl-single,input-schmitt-enable = &lt;0x40 0 0x40 0x40&gt;;</div><div class='add'>+		pinctrl-single,low-power-mode = &lt;0 0x388&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdh1_fast_pins_1: sdh1-fast-pins-1 {</div><div class='add'>+		pinctrl-single,pins = &lt;0x184 1&gt;;</div><div class='add'>+		pinctrl-single,drive-strength = &lt;0x1800 0x1800&gt;;</div><div class='add'>+		pinctrl-single,bias-pullup = &lt;0 0xc000 0 0xc000&gt;;</div><div class='add'>+		pinctrl-single,bias-pulldown = &lt;0 0xa000 0 0xa000&gt;;</div><div class='add'>+		pinctrl-single,input-schmitt = &lt;0 0x30&gt;;</div><div class='add'>+		pinctrl-single,input-schmitt-enable = &lt;0x40 0 0x40 0x40&gt;;</div><div class='add'>+		pinctrl-single,low-power-mode = &lt;0x208 0x388&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdh2_pins_0: sdh2-pins-0 {</div><div class='add'>+		pinctrl-single,pins = &lt;</div><div class='add'>+			0x24 1</div><div class='add'>+			0x28 1</div><div class='add'>+			0x2c 1</div><div class='add'>+			0x30 1</div><div class='add'>+			0x34 1</div><div class='add'>+			0x38 1</div><div class='add'>+			0x3c 1</div><div class='add'>+			0x40 1</div><div class='add'>+		&gt;;</div><div class='add'>+		pinctrl-single,drive-strength = &lt;0x1000 0x1800&gt;;</div><div class='add'>+		pinctrl-single,bias-pullup = &lt;0 0xc000 0 0xc000&gt;;</div><div class='add'>+		pinctrl-single,bias-pulldown = &lt;0 0xa000 0 0xa000&gt;;</div><div class='add'>+		pinctrl-single,input-schmitt = &lt;0 0x30&gt;;</div><div class='add'>+		pinctrl-single,input-schmitt-enable = &lt;0x40 0 0x40 0x40&gt;;</div><div class='add'>+		pinctrl-single,low-power-mode = &lt;0 0x388&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdh2_pins_1: sdh2-pins-1 {</div><div class='add'>+		pinctrl-single,pins = &lt;0x64 1&gt;;</div><div class='add'>+		pinctrl-single,drive-strength = &lt;0x1000 0x1800&gt;;</div><div class='add'>+		pinctrl-single,bias-pullup = &lt;0 0xc000 0 0xc000&gt;;</div><div class='add'>+		pinctrl-single,bias-pulldown = &lt;0 0xa000 0 0xa000&gt;;</div><div class='add'>+		pinctrl-single,input-schmitt = &lt;0 0x30&gt;;</div><div class='add'>+		pinctrl-single,input-schmitt-enable = &lt;0x40 0 0x40 0x40&gt;;</div><div class='add'>+		pinctrl-single,low-power-mode = &lt;0x208 0x388&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdh2_pins_2: sdh2-pins-2 {</div><div class='add'>+		pinctrl-single,pins = &lt;0x5c 1&gt;;</div><div class='add'>+		pinctrl-single,bias-pullup = &lt;0xc000 0xc000 0 0xc000&gt;;</div><div class='add'>+		pinctrl-single,bias-pulldown = &lt;0x8000 0xa000 0x8000 0xa000&gt;;</div><div class='add'>+		pinctrl-single,low-power-mode = &lt;0x288 0x388&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdh2_fast_pins_0: sdh2-fast-pins-0 {</div><div class='add'>+		pinctrl-single,pins = &lt;</div><div class='add'>+			0x24 1</div><div class='add'>+			0x28 1</div><div class='add'>+			0x2c 1</div><div class='add'>+			0x30 1</div><div class='add'>+			0x34 1</div><div class='add'>+			0x38 1</div><div class='add'>+			0x3c 1</div><div class='add'>+			0x40 1</div><div class='add'>+		&gt;;</div><div class='add'>+		pinctrl-single,drive-strength = &lt;0x1800 0x1800&gt;;</div><div class='add'>+		pinctrl-single,bias-pullup = &lt;0 0xc000 0 0xc000&gt;;</div><div class='add'>+		pinctrl-single,bias-pulldown = &lt;0 0xa000 0 0xa000&gt;;</div><div class='add'>+		pinctrl-single,input-schmitt = &lt;0 0x30&gt;;</div><div class='add'>+		pinctrl-single,input-schmitt-enable = &lt;0x40 0 0x40 0x40&gt;;</div><div class='add'>+		pinctrl-single,low-power-mode = &lt;0 0x388&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdh2_fast_pins_1: sdh2-fast-pins-1 {</div><div class='add'>+		pinctrl-single,pins = &lt;0x64 1&gt;;</div><div class='add'>+		pinctrl-single,drive-strength = &lt;0x1800 0x1800&gt;;</div><div class='add'>+		pinctrl-single,bias-pullup = &lt;0 0xc000 0 0xc000&gt;;</div><div class='add'>+		pinctrl-single,bias-pulldown = &lt;0 0xa000 0 0xa000&gt;;</div><div class='add'>+		pinctrl-single,input-schmitt = &lt;0 0x30&gt;;</div><div class='add'>+		pinctrl-single,input-schmitt-enable = &lt;0x40 0 0x40 0x40&gt;;</div><div class='add'>+		pinctrl-single,low-power-mode = &lt;0x208 0x388&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdh2_fast_pins_2: sdh2-fast-pins-2 {</div><div class='add'>+		pinctrl-single,pins = &lt;0x5c 1&gt;;</div><div class='add'>+		pinctrl-single,drive-strength = &lt;0x1800 0x1800&gt;;</div><div class='add'>+		pinctrl-single,bias-pullup = &lt;0xc000 0xc000 0 0xc000&gt;;</div><div class='add'>+		pinctrl-single,bias-pulldown = &lt;0x8000 0xa000 0x8000 0xa000&gt;;</div><div class='add'>+		pinctrl-single,low-power-mode = &lt;0x288 0x388&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vibrator_pin: vibrator-pin {</div><div class='add'>+		pinctrl-single,pins = &lt;0x12c 0&gt;;</div><div class='add'>+		pinctrl-single,drive-strength = &lt;0x1000 0x1800&gt;;</div><div class='add'>+		pinctrl-single,bias-pullup = &lt;0x8000 0xc000 0x8000 0xc000&gt;;</div><div class='add'>+		pinctrl-single,bias-pulldown = &lt;0xa000 0xa000 0 0xa000&gt;;</div><div class='add'>+		pinctrl-single,input-schmitt = &lt;0 0x30&gt;;</div><div class='add'>+		pinctrl-single,input-schmitt-enable = &lt;0x40 0 0x40 0x40&gt;;</div><div class='add'>+		pinctrl-single,low-power-mode = &lt;0 0x388&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart0_pins&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;twsi0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;twsi1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;twsi2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pmic@30 {</div><div class='add'>+		compatible = "marvell,88pm886-a1";</div><div class='add'>+		reg = &lt;0x30&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		wakeup-source;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			ldo2: ldo2 {</div><div class='add'>+				regulator-min-microvolt = &lt;1900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3100000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo6: ldo6 {</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo14: ldo14 {</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;twsi3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	touchscreen@50 {</div><div class='add'>+		compatible = "imagis,ist3032c";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio&gt;;</div><div class='add'>+		interrupts = &lt;72 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;ldo2&gt;;</div><div class='add'>+		touchscreen-size-x = &lt;480&gt;;</div><div class='add'>+		touchscreen-size-y = &lt;800&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb {</div><div class='add'>+	extcon = &lt;&amp;muic&gt;, &lt;&amp;muic&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sdh2 {</div><div class='add'>+	pinctrl-names = "default", "state_uhs";</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdh2_pins_0 &amp;sdh2_pins_1 &amp;sdh2_pins_2&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;sdh2_fast_pins_0 &amp;sdh2_fast_pins_1 &amp;sdh2_fast_pins_2&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	mmc-ddr-1_8v;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sdh0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdh0_pins_0 &amp;sdh0_pins_1 &amp;sdh0_pins_2&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;gpio 11 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	wp-inverted;</div><div class='add'>+	vmmc-supply = &lt;&amp;ldo14&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;ldo6&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sdh1 {</div><div class='add'>+	pinctrl-names = "default", "state_uhs";</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdh1_pins_0 &amp;sdh1_pins_1 &amp;sdh1_pins_2&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;sdh1_fast_pins_0 &amp;sdh1_fast_pins_1 &amp;sdh1_pins_2&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/marvell/mmp/pxa1908.dtsi b/arch/arm64/boot/dts/marvell/mmp/pxa1908.dtsi<br/>new file mode 100644<br/>index 000000000000..5778bfdb8567<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/marvell/mmp/pxa1908.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/marvell/mmp/pxa1908.dtsi</a></div><div class='hunk'>@@ -0,0 +1,349 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/marvell,pxa1908.h&gt;</div><div class='add'>+#include &lt;dt-bindings/power/marvell,pxa1908-power.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Marvell Armada PXA1908";</div><div class='add'>+	compatible = "marvell,pxa1908";</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0 0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@1 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0 1&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@2 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0 2&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@3 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0 3&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu {</div><div class='add'>+		compatible = "arm,cortex-a53-pmu";</div><div class='add'>+		interrupts = &lt;GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			&lt;GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			&lt;GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			&lt;GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-affinity = &lt;&amp;cpu0&gt;, &lt;&amp;cpu1&gt;, &lt;&amp;cpu2&gt;, &lt;&amp;cpu3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-0.2";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		ramoops@8100000 {</div><div class='add'>+			compatible = "ramoops";</div><div class='add'>+			reg = &lt;0 0x8100000 0 0x40000&gt;;</div><div class='add'>+			record-size = &lt;0x8000&gt;;</div><div class='add'>+			console-size = &lt;0x20000&gt;;</div><div class='add'>+			max-reason = &lt;5&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			&lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			&lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			&lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		smmu: iommu@c0010000 {</div><div class='add'>+			compatible = "arm,mmu-400";</div><div class='add'>+			reg = &lt;0 0xc0010000 0 0x10000&gt;;</div><div class='add'>+			#global-interrupts = &lt;1&gt;;</div><div class='add'>+			#iommu-cells = &lt;1&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			power-domains = &lt;&amp;apmu PXA1908_POWER_DOMAIN_VPU&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@d1df9000 {</div><div class='add'>+			compatible = "arm,gic-400";</div><div class='add'>+			reg = &lt;0 0xd1df9000 0 0x1000&gt;,</div><div class='add'>+				&lt;0 0xd1dfa000 0 0x2000&gt;,</div><div class='add'>+				/* The subsequent registers are guesses. */</div><div class='add'>+				&lt;0 0xd1dfc000 0 0x2000&gt;,</div><div class='add'>+				&lt;0 0xd1dfe000 0 0x2000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		apb@d4000000 {</div><div class='add'>+			compatible = "simple-bus";</div><div class='add'>+			reg = &lt;0 0xd4000000 0 0x200000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges = &lt;0 0 0xd4000000 0x200000&gt;;</div><div class='add'>+</div><div class='add'>+			pdma: dma-controller@0 {</div><div class='add'>+				compatible = "marvell,pdma-1.0";</div><div class='add'>+				reg = &lt;0 0x10000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				dma-channels = &lt;30&gt;;</div><div class='add'>+				#dma-cells = &lt;2&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			twsi1: i2c@10800 {</div><div class='add'>+				compatible = "mrvl,mmp-twsi";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				reg = &lt;0x10800 0x64&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;apbc PXA1908_CLK_TWSI1&gt;;</div><div class='add'>+				mrvl,i2c-fast-mode;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			twsi0: i2c@11000 {</div><div class='add'>+				compatible = "mrvl,mmp-twsi";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				reg = &lt;0x11000 0x64&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;apbc PXA1908_CLK_TWSI0&gt;;</div><div class='add'>+				mrvl,i2c-fast-mode;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			twsi3: i2c@13800 {</div><div class='add'>+				compatible = "mrvl,mmp-twsi";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				reg = &lt;0x13800 0x64&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;apbc PXA1908_CLK_TWSI3&gt;;</div><div class='add'>+				mrvl,i2c-fast-mode;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			apbc: clock-controller@15000 {</div><div class='add'>+				compatible = "marvell,pxa1908-apbc";</div><div class='add'>+				reg = &lt;0x15000 0x1000&gt;;</div><div class='add'>+				#clock-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart0: serial@17000 {</div><div class='add'>+				compatible = "mrvl,mmp-uart", "intel,xscale-uart";</div><div class='add'>+				reg = &lt;0x17000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;apbc PXA1908_CLK_UART0&gt;;</div><div class='add'>+				reg-shift = &lt;2&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart1: serial@18000 {</div><div class='add'>+				compatible = "mrvl,mmp-uart", "intel,xscale-uart";</div><div class='add'>+				reg = &lt;0x18000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;apbc PXA1908_CLK_UART1&gt;;</div><div class='add'>+				reg-shift = &lt;2&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gpio: gpio@19000 {</div><div class='add'>+				compatible = "marvell,mmp-gpio";</div><div class='add'>+				reg = &lt;0x19000 0x800&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;1&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+				clocks = &lt;&amp;apbc PXA1908_CLK_GPIO&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				interrupt-names = "gpio_mux";</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;2&gt;;</div><div class='add'>+				ranges = &lt;0 0x19000 0x800&gt;;</div><div class='add'>+</div><div class='add'>+				gpio@0 {</div><div class='add'>+					reg = &lt;0x0 0x4&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpio@4 {</div><div class='add'>+					reg = &lt;0x4 0x4&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpio@8 {</div><div class='add'>+					reg = &lt;0x8 0x4&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpio@100 {</div><div class='add'>+					reg = &lt;0x100 0x4&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pwm0: pwm@1a000 {</div><div class='add'>+				compatible = "marvell,pxa250-pwm";</div><div class='add'>+				reg = &lt;0x1a000 0x10&gt;;</div><div class='add'>+				clocks = &lt;&amp;apbc PXA1908_CLK_PWM0&gt;;</div><div class='add'>+				#pwm-cells = &lt;1&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pwm1: pwm@1a400 {</div><div class='add'>+				compatible = "marvell,pxa250-pwm";</div><div class='add'>+				reg = &lt;0x1a400 0x10&gt;;</div><div class='add'>+				clocks = &lt;&amp;apbc PXA1908_CLK_PWM1&gt;;</div><div class='add'>+				#pwm-cells = &lt;1&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pwm2: pwm@1a800 {</div><div class='add'>+				compatible = "marvell,pxa250-pwm";</div><div class='add'>+				reg = &lt;0x1a800 0x10&gt;;</div><div class='add'>+				clocks = &lt;&amp;apbc PXA1908_CLK_PWM2&gt;;</div><div class='add'>+				#pwm-cells = &lt;1&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pwm3: pwm@1ac00 {</div><div class='add'>+				compatible = "marvell,pxa250-pwm";</div><div class='add'>+				reg = &lt;0x1ac00 0x10&gt;;</div><div class='add'>+				clocks = &lt;&amp;apbc PXA1908_CLK_PWM3&gt;;</div><div class='add'>+				#pwm-cells = &lt;1&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pmx: pinmux@1e000 {</div><div class='add'>+				compatible = "marvell,pxa1908-padconf", "pinconf-single";</div><div class='add'>+				reg = &lt;0x1e000 0x330&gt;;</div><div class='add'>+</div><div class='add'>+				#pinctrl-cells = &lt;1&gt;;</div><div class='add'>+				pinctrl-single,register-width = &lt;32&gt;;</div><div class='add'>+				pinctrl-single,function-mask = &lt;7&gt;;</div><div class='add'>+</div><div class='add'>+				range: gpio-range {</div><div class='add'>+					#pinctrl-single,gpio-range-cells = &lt;3&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart2: serial@36000 {</div><div class='add'>+				compatible = "mrvl,mmp-uart", "intel,xscale-uart";</div><div class='add'>+				reg = &lt;0x36000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;apbcp PXA1908_CLK_UART2&gt;;</div><div class='add'>+				reg-shift = &lt;2&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			twsi2: i2c@37000 {</div><div class='add'>+				compatible = "mrvl,mmp-twsi";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				reg = &lt;0x37000 0x64&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;apbcp PXA1908_CLK_TWSI2&gt;;</div><div class='add'>+				mrvl,i2c-fast-mode;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			apbcp: clock-controller@3b000 {</div><div class='add'>+				compatible = "marvell,pxa1908-apbcp";</div><div class='add'>+				reg = &lt;0x3b000 0x1000&gt;;</div><div class='add'>+				#clock-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mpmu: clock-controller@50000 {</div><div class='add'>+				compatible = "marvell,pxa1908-mpmu";</div><div class='add'>+				reg = &lt;0x50000 0x1000&gt;;</div><div class='add'>+				#clock-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		axi@d4200000 {</div><div class='add'>+			compatible = "simple-bus";</div><div class='add'>+			reg = &lt;0 0xd4200000 0 0x200000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges = &lt;0 0 0xd4200000 0x200000&gt;;</div><div class='add'>+</div><div class='add'>+			usbphy: phy@7000 {</div><div class='add'>+				compatible = "marvell,pxa1928-usb-phy";</div><div class='add'>+				reg = &lt;0x7000 0x200&gt;;</div><div class='add'>+				clocks = &lt;&amp;apmu PXA1908_CLK_USB&gt;;</div><div class='add'>+				#phy-cells = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			usb: usb@8000 {</div><div class='add'>+				compatible = "chipidea,usb2";</div><div class='add'>+				reg = &lt;0x8000 0x200&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;apmu PXA1908_CLK_USB&gt;;</div><div class='add'>+				phys = &lt;&amp;usbphy&gt;;</div><div class='add'>+				phy-names = "usb-phy";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sdh0: mmc@80000 {</div><div class='add'>+				compatible = "mrvl,pxav3-mmc";</div><div class='add'>+				reg = &lt;0x80000 0x120&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;apmu PXA1908_CLK_SDH0&gt;;</div><div class='add'>+				clock-names = "io";</div><div class='add'>+				mrvl,clk-delay-cycles = &lt;31&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sdh1: mmc@80800 {</div><div class='add'>+				compatible = "mrvl,pxav3-mmc";</div><div class='add'>+				reg = &lt;0x80800 0x120&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;apmu PXA1908_CLK_SDH1&gt;;</div><div class='add'>+				clock-names = "io";</div><div class='add'>+				mrvl,clk-delay-cycles = &lt;31&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sdh2: mmc@81000 {</div><div class='add'>+				compatible = "mrvl,pxav3-mmc";</div><div class='add'>+				reg = &lt;0x81000 0x120&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;apmu PXA1908_CLK_SDH2&gt;;</div><div class='add'>+				clock-names = "io";</div><div class='add'>+				mrvl,clk-delay-cycles = &lt;31&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			apmu: clock-controller@82800 {</div><div class='add'>+				compatible = "marvell,pxa1908-apmu", "syscon";</div><div class='add'>+				reg = &lt;0x82800 0x400&gt;;</div><div class='add'>+				#clock-cells = &lt;1&gt;;</div><div class='add'>+				#power-domain-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile<br/>index 2f8967cb8717..c5fd6191a925 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/Makefile?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/Makefile</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/Makefile</a></div><div class='hunk'>@@ -1,11 +1,125 @@</div><div class='ctx'> # SPDX-License-Identifier: GPL-2.0</div><div class='ctx'> dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt6779-evb.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-sony-xperia-m5.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7981b-cudy-wr3000-v1.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7981b-openwrt-one.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7981b-xiaomi-ax3000t.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-acelink-ew-7886cax.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-mini.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-emmc.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nand.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nor.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sata.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sd.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-2g5.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-emmc.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-4e.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-8x.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-cn15.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-cn18.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-emmc.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-sd.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-sd.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana-rev7.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-burnet.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-cozmo.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-damu.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku1.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku6.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku7.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel14.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel14-sku2.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-juniper-sku16.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kappa.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kenzo.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-makomo-sku0.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-makomo-sku1.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-pico.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-pico6.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku0.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku1.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kakadu.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kakadu-sku22.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-katsu-sku32.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-katsu-sku38.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku16.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku272.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku288.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku32.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-chinchou-sku0.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-chinchou-sku1.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-chinchou-sku16.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-magneton-sku393216.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-magneton-sku393217.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-magneton-sku393218.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-ponyta-sku0.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-ponyta-sku1.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-rusty-sku196608.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-squirtle.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-starmie-sku0.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-starmie-sku1.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-steelix-sku131072.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-steelix-sku131073.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacool-sku327681.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacool-sku327683.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacruel-sku262144.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacruel-sku262148.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-voltorb.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-evb.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku0.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku1.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku2.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku3.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku4.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku5.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku6.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku7.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r1.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-spherion-r0.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-dojo-r1.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r1.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r2.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r3.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-demo.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8365-evk.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8370-genio-510-evk.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8370-grinn-genio-510-sbc.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-genio-1200-evk.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-genio-1200-evk-ufs.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-genio-700-evk.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-grinn-genio-700-sbc.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-kontron-3-5-sbc-i1200.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-radxa-nio-12l.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-radxa-nio-12l-8-hd-panel.dtbo</div><div class='ctx'> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb</div><div class='add'>+</div><div class='add'>+# Device tree overlays support</div><div class='add'>+DTC_FLAGS_mt7986a-bananapi-bpi-r3 := -@</div><div class='add'>+DTC_FLAGS_mt7986a-bananapi-bpi-r3-mini := -@</div><div class='add'>+DTC_FLAGS_mt7988a-bananapi-bpi-r4 := -@</div><div class='add'>+DTC_FLAGS_mt7988a-bananapi-bpi-r4-2g5 := -@</div><div class='add'>+DTC_FLAGS_mt7988a-bananapi-bpi-r4-pro-4e := -@</div><div class='add'>+DTC_FLAGS_mt7988a-bananapi-bpi-r4-pro-8x := -@</div><div class='add'>+DTC_FLAGS_mt8395-radxa-nio-12l := -@</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts<br/>index 2b91daf5c1a6..0449686bd06b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt2712-evb.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt2712-evb.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt2712-evb.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt2712-evb.dts</a></div><div class='hunk'>@@ -11,6 +11,7 @@</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	model = "MediaTek MT2712 evaluation board";</div><div class='add'>+	chassis-type = "embedded";</div><div class='ctx'> 	compatible = "mediatek,mt2712-evb", "mediatek,mt2712";</div><div class='ctx'> </div><div class='ctx'> 	aliases {</div><div class='hunk'>@@ -26,14 +27,14 @@</div><div class='ctx'> 		stdout-path = "serial0:921600n8";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	cpus_fixed_vproc0: fixedregulator@0 {</div><div class='add'>+	cpus_fixed_vproc0: regulator-vproc-buck0 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "vproc_buck0";</div><div class='ctx'> 		regulator-min-microvolt = &lt;1000000&gt;;</div><div class='ctx'> 		regulator-max-microvolt = &lt;1000000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	cpus_fixed_vproc1: fixedregulator@1 {</div><div class='add'>+	cpus_fixed_vproc1: regulator-vproc-buck1 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "vproc_buck1";</div><div class='ctx'> 		regulator-min-microvolt = &lt;1000000&gt;;</div><div class='hunk'>@@ -42,15 +43,15 @@</div><div class='ctx'> </div><div class='ctx'> 	extcon_usb: extcon_iddig {</div><div class='ctx'> 		compatible = "linux,extcon-usb-gpio";</div><div class='del'>-		id-gpio = &lt;&amp;pio 12 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		id-gpios = &lt;&amp;pio 12 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	extcon_usb1: extcon_iddig1 {</div><div class='ctx'> 		compatible = "linux,extcon-usb-gpio";</div><div class='del'>-		id-gpio = &lt;&amp;pio 14 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		id-gpios = &lt;&amp;pio 14 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	usb_p0_vbus: regulator@2 {</div><div class='add'>+	usb_p0_vbus: regulator-usb-p0-vbus {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "p0_vbus";</div><div class='ctx'> 		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='hunk'>@@ -59,7 +60,7 @@</div><div class='ctx'> 		enable-active-high;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	usb_p1_vbus: regulator@3 {</div><div class='add'>+	usb_p1_vbus: regulator-usb-p1-vbus {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "p1_vbus";</div><div class='ctx'> 		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='hunk'>@@ -68,7 +69,7 @@</div><div class='ctx'> 		enable-active-high;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	usb_p2_vbus: regulator@4 {</div><div class='add'>+	usb_p2_vbus: regulator-usb-p2-vbus {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "p2_vbus";</div><div class='ctx'> 		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='hunk'>@@ -77,7 +78,7 @@</div><div class='ctx'> 		enable-active-high;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	usb_p3_vbus: regulator@5 {</div><div class='add'>+	usb_p3_vbus: regulator-usb-p3-vbus {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "p3_vbus";</div><div class='ctx'> 		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='hunk'>@@ -105,15 +106,91 @@</div><div class='ctx'> 	proc-supply = &lt;&amp;cpus_fixed_vproc1&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;eth {</div><div class='add'>+	phy-mode = "rgmii-rxid";</div><div class='add'>+	phy-handle = &lt;&amp;ethernet_phy0&gt;;</div><div class='add'>+	mediatek,tx-delay-ps = &lt;1530&gt;;</div><div class='add'>+	snps,reset-gpio = &lt;&amp;pio 87 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	snps,reset-delays-us = &lt;0 10000 10000&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;eth_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;eth_sleep&gt;;</div><div class='add'>+	mediatek,mac-wol;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		ethernet_phy0: ethernet-phy@5 {</div><div class='add'>+			compatible = "ethernet-phy-id0243.0d90";</div><div class='add'>+			reg = &lt;0x5&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;pio {</div><div class='del'>-	usb0_id_pins_float: usb0_iddig {</div><div class='add'>+	eth_default: eth-default-pins {</div><div class='add'>+		tx_pins {</div><div class='add'>+			pinmux = &lt;MT2712_PIN_71_GBE_TXD3__FUNC_GBE_TXD3&gt;,</div><div class='add'>+				 &lt;MT2712_PIN_72_GBE_TXD2__FUNC_GBE_TXD2&gt;,</div><div class='add'>+				 &lt;MT2712_PIN_73_GBE_TXD1__FUNC_GBE_TXD1&gt;,</div><div class='add'>+				 &lt;MT2712_PIN_74_GBE_TXD0__FUNC_GBE_TXD0&gt;,</div><div class='add'>+				 &lt;MT2712_PIN_75_GBE_TXC__FUNC_GBE_TXC&gt;,</div><div class='add'>+				 &lt;MT2712_PIN_76_GBE_TXEN__FUNC_GBE_TXEN&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+		};</div><div class='add'>+		rx_pins {</div><div class='add'>+			pinmux = &lt;MT2712_PIN_78_GBE_RXD3__FUNC_GBE_RXD3&gt;,</div><div class='add'>+				 &lt;MT2712_PIN_79_GBE_RXD2__FUNC_GBE_RXD2&gt;,</div><div class='add'>+				 &lt;MT2712_PIN_80_GBE_RXD1__FUNC_GBE_RXD1&gt;,</div><div class='add'>+				 &lt;MT2712_PIN_81_GBE_RXD0__FUNC_GBE_RXD0&gt;,</div><div class='add'>+				 &lt;MT2712_PIN_82_GBE_RXDV__FUNC_GBE_RXDV&gt;,</div><div class='add'>+				 &lt;MT2712_PIN_84_GBE_RXC__FUNC_GBE_RXC&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+		mdio_pins {</div><div class='add'>+			pinmux = &lt;MT2712_PIN_85_GBE_MDC__FUNC_GBE_MDC&gt;,</div><div class='add'>+				 &lt;MT2712_PIN_86_GBE_MDIO__FUNC_GBE_MDIO&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eth_sleep: eth-sleep-pins {</div><div class='add'>+		tx_pins {</div><div class='add'>+			pinmux = &lt;MT2712_PIN_71_GBE_TXD3__FUNC_GPIO71&gt;,</div><div class='add'>+				 &lt;MT2712_PIN_72_GBE_TXD2__FUNC_GPIO72&gt;,</div><div class='add'>+				 &lt;MT2712_PIN_73_GBE_TXD1__FUNC_GPIO73&gt;,</div><div class='add'>+				 &lt;MT2712_PIN_74_GBE_TXD0__FUNC_GPIO74&gt;,</div><div class='add'>+				 &lt;MT2712_PIN_75_GBE_TXC__FUNC_GPIO75&gt;,</div><div class='add'>+				 &lt;MT2712_PIN_76_GBE_TXEN__FUNC_GPIO76&gt;;</div><div class='add'>+		};</div><div class='add'>+		rx_pins {</div><div class='add'>+			pinmux = &lt;MT2712_PIN_78_GBE_RXD3__FUNC_GPIO78&gt;,</div><div class='add'>+				 &lt;MT2712_PIN_79_GBE_RXD2__FUNC_GPIO79&gt;,</div><div class='add'>+				 &lt;MT2712_PIN_80_GBE_RXD1__FUNC_GPIO80&gt;,</div><div class='add'>+				 &lt;MT2712_PIN_81_GBE_RXD0__FUNC_GPIO81&gt;,</div><div class='add'>+				 &lt;MT2712_PIN_82_GBE_RXDV__FUNC_GPIO82&gt;,</div><div class='add'>+				 &lt;MT2712_PIN_84_GBE_RXC__FUNC_GPIO84&gt;;</div><div class='add'>+			input-disable;</div><div class='add'>+		};</div><div class='add'>+		mdio_pins {</div><div class='add'>+			pinmux = &lt;MT2712_PIN_85_GBE_MDC__FUNC_GPIO85&gt;,</div><div class='add'>+				 &lt;MT2712_PIN_86_GBE_MDIO__FUNC_GPIO86&gt;;</div><div class='add'>+			input-disable;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb0_id_pins_float: usb0-iddig-pins {</div><div class='ctx'> 		pins_iddig {</div><div class='ctx'> 			pinmux = &lt;MT2712_PIN_12_IDDIG_P0__FUNC_IDDIG_A&gt;;</div><div class='ctx'> 			bias-pull-up;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	usb1_id_pins_float: usb1_iddig {</div><div class='add'>+	usb1_id_pins_float: usb1-iddig-pins {</div><div class='ctx'> 		pins_iddig {</div><div class='ctx'> 			pinmux = &lt;MT2712_PIN_14_IDDIG_P1__FUNC_IDDIG_B&gt;;</div><div class='ctx'> 			bias-pull-up;</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi<br/>index 2cd8b33886e5..082672efba0a 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt2712e.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt2712e.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt2712e.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt2712e.dtsi</a></div><div class='hunk'>@@ -19,7 +19,7 @@</div><div class='ctx'> 	#address-cells = &lt;2&gt;;</div><div class='ctx'> 	#size-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='del'>-	cluster0_opp: opp_table0 {</div><div class='add'>+	cluster0_opp: opp-table-0 {</div><div class='ctx'> 		compatible = "operating-points-v2";</div><div class='ctx'> 		opp-shared;</div><div class='ctx'> 		opp00 {</div><div class='hunk'>@@ -36,7 +36,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	cluster1_opp: opp_table1 {</div><div class='add'>+	cluster1_opp: opp-table-1 {</div><div class='ctx'> 		compatible = "operating-points-v2";</div><div class='ctx'> 		opp-shared;</div><div class='ctx'> 		opp00 {</div><div class='hunk'>@@ -160,70 +160,70 @@</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	clk26m: oscillator@0 {</div><div class='add'>+	clk26m: oscillator-26m {</div><div class='ctx'> 		compatible = "fixed-clock";</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='ctx'> 		clock-frequency = &lt;26000000&gt;;</div><div class='ctx'> 		clock-output-names = "clk26m";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	clk32k: oscillator@1 {</div><div class='add'>+	clk32k: oscillator-32k {</div><div class='ctx'> 		compatible = "fixed-clock";</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='ctx'> 		clock-frequency = &lt;32768&gt;;</div><div class='ctx'> 		clock-output-names = "clk32k";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	clkfpc: oscillator@2 {</div><div class='add'>+	clkfpc: oscillator-50m {</div><div class='ctx'> 		compatible = "fixed-clock";</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='ctx'> 		clock-frequency = &lt;50000000&gt;;</div><div class='ctx'> 		clock-output-names = "clkfpc";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	clkaud_ext_i_0: oscillator@3 {</div><div class='add'>+	clkaud_ext_i_0: oscillator-aud0 {</div><div class='ctx'> 		compatible = "fixed-clock";</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='ctx'> 		clock-frequency = &lt;6500000&gt;;</div><div class='ctx'> 		clock-output-names = "clkaud_ext_i_0";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	clkaud_ext_i_1: oscillator@4 {</div><div class='add'>+	clkaud_ext_i_1: oscillator-aud1 {</div><div class='ctx'> 		compatible = "fixed-clock";</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='ctx'> 		clock-frequency = &lt;196608000&gt;;</div><div class='ctx'> 		clock-output-names = "clkaud_ext_i_1";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	clkaud_ext_i_2: oscillator@5 {</div><div class='add'>+	clkaud_ext_i_2: oscillator-aud2 {</div><div class='ctx'> 		compatible = "fixed-clock";</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='ctx'> 		clock-frequency = &lt;180633600&gt;;</div><div class='ctx'> 		clock-output-names = "clkaud_ext_i_2";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	clki2si0_mck_i: oscillator@6 {</div><div class='add'>+	clki2si0_mck_i: oscillator-i2s0 {</div><div class='ctx'> 		compatible = "fixed-clock";</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='ctx'> 		clock-frequency = &lt;30000000&gt;;</div><div class='ctx'> 		clock-output-names = "clki2si0_mck_i";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	clki2si1_mck_i: oscillator@7 {</div><div class='add'>+	clki2si1_mck_i: oscillator-i2s1 {</div><div class='ctx'> 		compatible = "fixed-clock";</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='ctx'> 		clock-frequency = &lt;30000000&gt;;</div><div class='ctx'> 		clock-output-names = "clki2si1_mck_i";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	clki2si2_mck_i: oscillator@8 {</div><div class='add'>+	clki2si2_mck_i: oscillator-i2s2 {</div><div class='ctx'> 		compatible = "fixed-clock";</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='ctx'> 		clock-frequency = &lt;30000000&gt;;</div><div class='ctx'> 		clock-output-names = "clki2si2_mck_i";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	clktdmin_mclk_i: oscillator@9 {</div><div class='add'>+	clktdmin_mclk_i: oscillator-mclk {</div><div class='ctx'> 		compatible = "fixed-clock";</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='ctx'> 		clock-frequency = &lt;30000000&gt;;</div><div class='hunk'>@@ -249,10 +249,11 @@</div><div class='ctx'> 		#clock-cells = &lt;1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	infracfg: syscon@10001000 {</div><div class='add'>+	infracfg: clock-controller@10001000 {</div><div class='ctx'> 		compatible = "mediatek,mt2712-infracfg", "syscon";</div><div class='ctx'> 		reg = &lt;0 0x10001000 0 0x1000&gt;;</div><div class='ctx'> 		#clock-cells = &lt;1&gt;;</div><div class='add'>+		#reset-cells = &lt;1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	pericfg: syscon@10003000 {</div><div class='hunk'>@@ -261,16 +262,15 @@</div><div class='ctx'> 		#clock-cells = &lt;1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	syscfg_pctl_a: syscfg_pctl_a@10005000 {</div><div class='add'>+	syscfg_pctl_a: syscon@10005000 {</div><div class='ctx'> 		compatible = "mediatek,mt2712-pctl-a-syscfg", "syscon";</div><div class='ctx'> 		reg = &lt;0 0x10005000 0 0x1000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pio: pinctrl@10005000 {</div><div class='add'>+	pio: pinctrl@1000b000 {</div><div class='ctx'> 		compatible = "mediatek,mt2712-pinctrl";</div><div class='ctx'> 		reg = &lt;0 0x1000b000 0 0x1000&gt;;</div><div class='ctx'> 		mediatek,pctl-regmap = &lt;&amp;syscfg_pctl_a&gt;;</div><div class='del'>-		pins-are-numbered;</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> 		interrupt-controller;</div><div class='hunk'>@@ -300,6 +300,9 @@</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 127 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 		clocks = &lt;&amp;baud_clk&gt;, &lt;&amp;sys_clk&gt;;</div><div class='ctx'> 		clock-names = "baud", "bus";</div><div class='add'>+		dmas = &lt;&amp;apdma 10</div><div class='add'>+			&amp;apdma 11&gt;;</div><div class='add'>+		dma-names = "tx", "rx";</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -326,8 +329,9 @@</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 147 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 		clocks = &lt;&amp;infracfg CLK_INFRA_M4U&gt;;</div><div class='ctx'> 		clock-names = "bclk";</div><div class='del'>-		mediatek,larbs = &lt;&amp;larb0 &amp;larb1 &amp;larb2</div><div class='del'>-				  &amp;larb3 &amp;larb6&gt;;</div><div class='add'>+		mediatek,infracfg = &lt;&amp;infracfg&gt;;</div><div class='add'>+		mediatek,larbs = &lt;&amp;larb0&gt;, &lt;&amp;larb1&gt;, &lt;&amp;larb2&gt;,</div><div class='add'>+				 &lt;&amp;larb3&gt;, &lt;&amp;larb6&gt;;</div><div class='ctx'> 		#iommu-cells = &lt;1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -343,7 +347,8 @@</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 145 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 		clocks = &lt;&amp;infracfg CLK_INFRA_M4U&gt;;</div><div class='ctx'> 		clock-names = "bclk";</div><div class='del'>-		mediatek,larbs = &lt;&amp;larb4 &amp;larb5 &amp;larb7&gt;;</div><div class='add'>+		mediatek,infracfg = &lt;&amp;infracfg&gt;;</div><div class='add'>+		mediatek,larbs = &lt;&amp;larb4&gt;, &lt;&amp;larb5&gt;, &lt;&amp;larb7&gt;;</div><div class='ctx'> 		#iommu-cells = &lt;1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -375,6 +380,39 @@</div><div class='ctx'> 			 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	apdma: dma-controller@11000400 {</div><div class='add'>+		compatible = "mediatek,mt2712-uart-dma",</div><div class='add'>+			     "mediatek,mt6577-uart-dma";</div><div class='add'>+		reg = &lt;0 0x11000400 0 0x80&gt;,</div><div class='add'>+		      &lt;0 0x11000480 0 0x80&gt;,</div><div class='add'>+		      &lt;0 0x11000500 0 0x80&gt;,</div><div class='add'>+		      &lt;0 0x11000580 0 0x80&gt;,</div><div class='add'>+		      &lt;0 0x11000600 0 0x80&gt;,</div><div class='add'>+		      &lt;0 0x11000680 0 0x80&gt;,</div><div class='add'>+		      &lt;0 0x11000700 0 0x80&gt;,</div><div class='add'>+		      &lt;0 0x11000780 0 0x80&gt;,</div><div class='add'>+		      &lt;0 0x11000800 0 0x80&gt;,</div><div class='add'>+		      &lt;0 0x11000880 0 0x80&gt;,</div><div class='add'>+		      &lt;0 0x11000900 0 0x80&gt;,</div><div class='add'>+		      &lt;0 0x11000980 0 0x80&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 103 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_SPI 104 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_SPI 105 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_SPI 106 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_SPI 107 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_SPI 108 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_SPI 109 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_SPI 110 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_SPI 111 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_SPI 112 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_SPI 113 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_SPI 114 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		dma-requests = &lt;12&gt;;</div><div class='add'>+		clocks = &lt;&amp;pericfg CLK_PERI_AP_DMA&gt;;</div><div class='add'>+		clock-names = "apdma";</div><div class='add'>+		#dma-cells = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	auxadc: adc@11001000 {</div><div class='ctx'> 		compatible = "mediatek,mt2712-auxadc";</div><div class='ctx'> 		reg = &lt;0 0x11001000 0 0x1000&gt;;</div><div class='hunk'>@@ -391,6 +429,9 @@</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 91 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 		clocks = &lt;&amp;baud_clk&gt;, &lt;&amp;sys_clk&gt;;</div><div class='ctx'> 		clock-names = "baud", "bus";</div><div class='add'>+		dmas = &lt;&amp;apdma 0</div><div class='add'>+			&amp;apdma 1&gt;;</div><div class='add'>+		dma-names = "tx", "rx";</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -401,6 +442,9 @@</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 92 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 		clocks = &lt;&amp;baud_clk&gt;, &lt;&amp;sys_clk&gt;;</div><div class='ctx'> 		clock-names = "baud", "bus";</div><div class='add'>+		dmas = &lt;&amp;apdma 2</div><div class='add'>+			&amp;apdma 3&gt;;</div><div class='add'>+		dma-names = "tx", "rx";</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -411,6 +455,9 @@</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 93 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 		clocks = &lt;&amp;baud_clk&gt;, &lt;&amp;sys_clk&gt;;</div><div class='ctx'> 		clock-names = "baud", "bus";</div><div class='add'>+		dmas = &lt;&amp;apdma 4</div><div class='add'>+			&amp;apdma 5&gt;;</div><div class='add'>+		dma-names = "tx", "rx";</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -421,6 +468,9 @@</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 94 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 		clocks = &lt;&amp;baud_clk&gt;, &lt;&amp;sys_clk&gt;;</div><div class='ctx'> 		clock-names = "baud", "bus";</div><div class='add'>+		dmas = &lt;&amp;apdma 6</div><div class='add'>+			&amp;apdma 7&gt;;</div><div class='add'>+		dma-names = "tx", "rx";</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -510,7 +560,7 @@</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	nandc: nfi@1100e000 {</div><div class='add'>+	nandc: nand-controller@1100e000 {</div><div class='ctx'> 		compatible = "mediatek,mt2712-nfc";</div><div class='ctx'> 		reg = &lt;0 0x1100e000 0 0x1000&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 96 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='hunk'>@@ -635,6 +685,78 @@</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 126 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 		clocks = &lt;&amp;baud_clk&gt;, &lt;&amp;sys_clk&gt;;</div><div class='ctx'> 		clock-names = "baud", "bus";</div><div class='add'>+		dmas = &lt;&amp;apdma 8</div><div class='add'>+			&amp;apdma 9&gt;;</div><div class='add'>+		dma-names = "tx", "rx";</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	stmmac_axi_setup: stmmac-axi-config {</div><div class='add'>+		snps,wr_osr_lmt = &lt;0x7&gt;;</div><div class='add'>+		snps,rd_osr_lmt = &lt;0x7&gt;;</div><div class='add'>+		snps,blen = &lt;0 0 0 0 16 8 4&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mtl_rx_setup: rx-queues-config {</div><div class='add'>+		snps,rx-queues-to-use = &lt;1&gt;;</div><div class='add'>+		snps,rx-sched-sp;</div><div class='add'>+		queue0 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,map-to-dma-channel = &lt;0x0&gt;;</div><div class='add'>+			snps,priority = &lt;0x0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mtl_tx_setup: tx-queues-config {</div><div class='add'>+		snps,tx-queues-to-use = &lt;3&gt;;</div><div class='add'>+		snps,tx-sched-wrr;</div><div class='add'>+		queue0 {</div><div class='add'>+			snps,weight = &lt;0x10&gt;;</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x0&gt;;</div><div class='add'>+		};</div><div class='add'>+		queue1 {</div><div class='add'>+			snps,weight = &lt;0x11&gt;;</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x1&gt;;</div><div class='add'>+		};</div><div class='add'>+		queue2 {</div><div class='add'>+			snps,weight = &lt;0x12&gt;;</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,priority = &lt;0x2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eth: ethernet@1101c000 {</div><div class='add'>+		compatible = "mediatek,mt2712-gmac", "snps,dwmac-4.20a";</div><div class='add'>+		reg = &lt;0 0x1101c000 0 0x1300&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 237 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupt-names = "macirq";</div><div class='add'>+		mac-address = [00 55 7b b5 7d f7];</div><div class='add'>+		clock-names = "axi",</div><div class='add'>+			      "apb",</div><div class='add'>+			      "mac_main",</div><div class='add'>+			      "ptp_ref",</div><div class='add'>+			      "rmii_internal";</div><div class='add'>+		clocks = &lt;&amp;pericfg CLK_PERI_GMAC&gt;,</div><div class='add'>+			 &lt;&amp;pericfg CLK_PERI_GMAC_PCLK&gt;,</div><div class='add'>+			 &lt;&amp;topckgen CLK_TOP_ETHER_125M_SEL&gt;,</div><div class='add'>+			 &lt;&amp;topckgen CLK_TOP_ETHER_50M_SEL&gt;,</div><div class='add'>+			 &lt;&amp;topckgen CLK_TOP_ETHER_50M_RMII_SEL&gt;;</div><div class='add'>+		assigned-clocks = &lt;&amp;topckgen CLK_TOP_ETHER_125M_SEL&gt;,</div><div class='add'>+				  &lt;&amp;topckgen CLK_TOP_ETHER_50M_SEL&gt;,</div><div class='add'>+				  &lt;&amp;topckgen CLK_TOP_ETHER_50M_RMII_SEL&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_ETHERPLL_125M&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_APLL1_D3&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_ETHERPLL_50M&gt;;</div><div class='add'>+		power-domains = &lt;&amp;scpsys MT2712_POWER_DOMAIN_AUDIO&gt;;</div><div class='add'>+		mediatek,pericfg = &lt;&amp;pericfg&gt;;</div><div class='add'>+		snps,axi-config = &lt;&amp;stmmac_axi_setup&gt;;</div><div class='add'>+		snps,mtl-rx-config = &lt;&amp;mtl_rx_setup&gt;;</div><div class='add'>+		snps,mtl-tx-config = &lt;&amp;mtl_tx_setup&gt;;</div><div class='add'>+		snps,txpbl = &lt;1&gt;;</div><div class='add'>+		snps,rxpbl = &lt;1&gt;;</div><div class='add'>+		snps,clk-csr = &lt;0&gt;;</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -644,9 +766,9 @@</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 79 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 		clocks = &lt;&amp;pericfg CLK_PERI_MSDC30_0&gt;,</div><div class='ctx'> 			 &lt;&amp;pericfg CLK_PERI_MSDC50_0_HCLK_EN&gt;,</div><div class='del'>-			 &lt;&amp;pericfg CLK_PERI_MSDC30_0_QTR_EN&gt;,</div><div class='del'>-			 &lt;&amp;pericfg CLK_PERI_MSDC50_0_EN&gt;;</div><div class='del'>-		clock-names = "source", "hclk", "bus_clk", "source_cg";</div><div class='add'>+			 &lt;&amp;pericfg CLK_PERI_MSDC50_0_EN&gt;,</div><div class='add'>+			 &lt;&amp;pericfg CLK_PERI_MSDC30_0_QTR_EN&gt;;</div><div class='add'>+		clock-names = "source", "hclk", "source_cg", "bus_clk";</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -689,7 +811,7 @@</div><div class='ctx'> 		ranges;</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> </div><div class='del'>-		usb_host0: xhci@11270000 {</div><div class='add'>+		usb_host0: usb@11270000 {</div><div class='ctx'> 			compatible = "mediatek,mt2712-xhci",</div><div class='ctx'> 				     "mediatek,mtk-xhci";</div><div class='ctx'> 			reg = &lt;0 0x11270000 0 0x1000&gt;;</div><div class='hunk'>@@ -702,31 +824,32 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	u3phy0: usb-phy@11290000 {</div><div class='del'>-		compatible = "mediatek,mt2712-u3phy";</div><div class='del'>-		#address-cells = &lt;2&gt;;</div><div class='del'>-		#size-cells = &lt;2&gt;;</div><div class='del'>-		ranges;</div><div class='add'>+	u3phy0: t-phy@11290000 {</div><div class='add'>+		compatible = "mediatek,mt2712-tphy",</div><div class='add'>+			     "mediatek,generic-tphy-v2";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges = &lt;0 0 0x11290000 0x9000&gt;;</div><div class='ctx'> 		status = "okay";</div><div class='ctx'> </div><div class='del'>-		u2port0: usb-phy@11290000 {</div><div class='del'>-			reg = &lt;0 0x11290000 0 0x700&gt;;</div><div class='add'>+		u2port0: usb-phy@0 {</div><div class='add'>+			reg = &lt;0x0 0x700&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;clk26m&gt;;</div><div class='ctx'> 			clock-names = "ref";</div><div class='ctx'> 			#phy-cells = &lt;1&gt;;</div><div class='ctx'> 			status = "okay";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		u2port1: usb-phy@11298000 {</div><div class='del'>-			reg = &lt;0 0x11298000 0 0x700&gt;;</div><div class='add'>+		u2port1: usb-phy@8000 {</div><div class='add'>+			reg = &lt;0x8000 0x700&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;clk26m&gt;;</div><div class='ctx'> 			clock-names = "ref";</div><div class='ctx'> 			#phy-cells = &lt;1&gt;;</div><div class='ctx'> 			status = "okay";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		u3port0: usb-phy@11298700 {</div><div class='del'>-			reg = &lt;0 0x11298700 0 0x900&gt;;</div><div class='add'>+		u3port0: usb-phy@8700 {</div><div class='add'>+			reg = &lt;0x8700 0x900&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;clk26m&gt;;</div><div class='ctx'> 			clock-names = "ref";</div><div class='ctx'> 			#phy-cells = &lt;1&gt;;</div><div class='hunk'>@@ -752,7 +875,7 @@</div><div class='ctx'> 		ranges;</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> </div><div class='del'>-		usb_host1: xhci@112c0000 {</div><div class='add'>+		usb_host1: usb@112c0000 {</div><div class='ctx'> 			compatible = "mediatek,mt2712-xhci",</div><div class='ctx'> 				     "mediatek,mtk-xhci";</div><div class='ctx'> 			reg = &lt;0 0x112c0000 0 0x1000&gt;;</div><div class='hunk'>@@ -765,31 +888,32 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	u3phy1: usb-phy@112e0000 {</div><div class='del'>-		compatible = "mediatek,mt2712-u3phy";</div><div class='del'>-		#address-cells = &lt;2&gt;;</div><div class='del'>-		#size-cells = &lt;2&gt;;</div><div class='del'>-		ranges;</div><div class='add'>+	u3phy1: t-phy@112e0000 {</div><div class='add'>+		compatible = "mediatek,mt2712-tphy",</div><div class='add'>+			     "mediatek,generic-tphy-v2";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges = &lt;0 0 0x112e0000 0x9000&gt;;</div><div class='ctx'> 		status = "okay";</div><div class='ctx'> </div><div class='del'>-		u2port2: usb-phy@112e0000 {</div><div class='del'>-			reg = &lt;0 0x112e0000 0 0x700&gt;;</div><div class='add'>+		u2port2: usb-phy@0 {</div><div class='add'>+			reg = &lt;0x0 0x700&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;clk26m&gt;;</div><div class='ctx'> 			clock-names = "ref";</div><div class='ctx'> 			#phy-cells = &lt;1&gt;;</div><div class='ctx'> 			status = "okay";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		u2port3: usb-phy@112e8000 {</div><div class='del'>-			reg = &lt;0 0x112e8000 0 0x700&gt;;</div><div class='add'>+		u2port3: usb-phy@8000 {</div><div class='add'>+			reg = &lt;0x8000 0x700&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;clk26m&gt;;</div><div class='ctx'> 			clock-names = "ref";</div><div class='ctx'> 			#phy-cells = &lt;1&gt;;</div><div class='ctx'> 			status = "okay";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		u3port1: usb-phy@112e8700 {</div><div class='del'>-			reg = &lt;0 0x112e8700 0 0x900&gt;;</div><div class='add'>+		u3port1: usb-phy@8700 {</div><div class='add'>+			reg = &lt;0x8700 0x900&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;clk26m&gt;;</div><div class='ctx'> 			clock-names = "ref";</div><div class='ctx'> 			#phy-cells = &lt;1&gt;;</div><div class='hunk'>@@ -797,64 +921,67 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pcie: pcie@11700000 {</div><div class='add'>+	pcie1: pcie@112ff000 {</div><div class='ctx'> 		compatible = "mediatek,mt2712-pcie";</div><div class='ctx'> 		device_type = "pci";</div><div class='del'>-		reg = &lt;0 0x11700000 0 0x1000&gt;,</div><div class='del'>-		      &lt;0 0x112ff000 0 0x1000&gt;;</div><div class='del'>-		reg-names = "port0", "port1";</div><div class='add'>+		reg = &lt;0 0x112ff000 0 0x1000&gt;;</div><div class='add'>+		reg-names = "port1";</div><div class='add'>+		linux,pci-domain = &lt;1&gt;;</div><div class='ctx'> 		#address-cells = &lt;3&gt;;</div><div class='ctx'> 		#size-cells = &lt;2&gt;;</div><div class='del'>-		interrupts = &lt;GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-			     &lt;GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-		clocks = &lt;&amp;topckgen CLK_TOP_PE2_MAC_P0_SEL&gt;,</div><div class='del'>-			 &lt;&amp;topckgen CLK_TOP_PE2_MAC_P1_SEL&gt;,</div><div class='del'>-			 &lt;&amp;pericfg CLK_PERI_PCIE0&gt;,</div><div class='add'>+		interrupts = &lt;GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-names = "pcie_irq";</div><div class='add'>+		clocks = &lt;&amp;topckgen CLK_TOP_PE2_MAC_P1_SEL&gt;,</div><div class='ctx'> 			 &lt;&amp;pericfg CLK_PERI_PCIE1&gt;;</div><div class='del'>-		clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";</div><div class='del'>-		phys = &lt;&amp;u3port0 PHY_TYPE_PCIE&gt;, &lt;&amp;u3port1 PHY_TYPE_PCIE&gt;;</div><div class='del'>-		phy-names = "pcie-phy0", "pcie-phy1";</div><div class='add'>+		clock-names = "sys_ck1", "ahb_ck1";</div><div class='add'>+		phys = &lt;&amp;u3port1 PHY_TYPE_PCIE&gt;;</div><div class='add'>+		phy-names = "pcie-phy1";</div><div class='ctx'> 		bus-range = &lt;0x00 0xff&gt;;</div><div class='del'>-		ranges = &lt;0x82000000 0 0x20000000  0x0 0x20000000  0 0x10000000&gt;;</div><div class='add'>+		ranges = &lt;0x82000000 0 0x11400000  0x0 0x11400000  0 0x300000&gt;;</div><div class='add'>+		status = "disabled";</div><div class='ctx'> </div><div class='del'>-		pcie0: pcie@0,0 {</div><div class='del'>-			device_type = "pci";</div><div class='del'>-			status = "disabled";</div><div class='del'>-			reg = &lt;0x0000 0 0 0 0&gt;;</div><div class='del'>-			#address-cells = &lt;3&gt;;</div><div class='del'>-			#size-cells = &lt;2&gt;;</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='add'>+		interrupt-map = &lt;0 0 0 1 &amp;pcie_intc1 0&gt;,</div><div class='add'>+				&lt;0 0 0 2 &amp;pcie_intc1 1&gt;,</div><div class='add'>+				&lt;0 0 0 3 &amp;pcie_intc1 2&gt;,</div><div class='add'>+				&lt;0 0 0 4 &amp;pcie_intc1 3&gt;;</div><div class='add'>+		pcie_intc1: interrupt-controller {</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#address-cells = &lt;0&gt;;</div><div class='ctx'> 			#interrupt-cells = &lt;1&gt;;</div><div class='del'>-			ranges;</div><div class='del'>-			interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='del'>-			interrupt-map = &lt;0 0 0 1 &amp;pcie_intc0 0&gt;,</div><div class='del'>-					&lt;0 0 0 2 &amp;pcie_intc0 1&gt;,</div><div class='del'>-					&lt;0 0 0 3 &amp;pcie_intc0 2&gt;,</div><div class='del'>-					&lt;0 0 0 4 &amp;pcie_intc0 3&gt;;</div><div class='del'>-			pcie_intc0: interrupt-controller {</div><div class='del'>-				interrupt-controller;</div><div class='del'>-				#address-cells = &lt;0&gt;;</div><div class='del'>-				#interrupt-cells = &lt;1&gt;;</div><div class='del'>-			};</div><div class='ctx'> 		};</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		pcie1: pcie@1,0 {</div><div class='del'>-			device_type = "pci";</div><div class='del'>-			status = "disabled";</div><div class='del'>-			reg = &lt;0x0800 0 0 0 0&gt;;</div><div class='del'>-			#address-cells = &lt;3&gt;;</div><div class='del'>-			#size-cells = &lt;2&gt;;</div><div class='add'>+	pcie0: pcie@11700000 {</div><div class='add'>+		compatible = "mediatek,mt2712-pcie";</div><div class='add'>+		device_type = "pci";</div><div class='add'>+		reg = &lt;0 0x11700000 0 0x1000&gt;;</div><div class='add'>+		reg-names = "port0";</div><div class='add'>+		linux,pci-domain = &lt;0&gt;;</div><div class='add'>+		#address-cells = &lt;3&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-names = "pcie_irq";</div><div class='add'>+		clocks = &lt;&amp;topckgen CLK_TOP_PE2_MAC_P0_SEL&gt;,</div><div class='add'>+			 &lt;&amp;pericfg CLK_PERI_PCIE0&gt;;</div><div class='add'>+		clock-names = "sys_ck0", "ahb_ck0";</div><div class='add'>+		phys = &lt;&amp;u3port0 PHY_TYPE_PCIE&gt;;</div><div class='add'>+		phy-names = "pcie-phy0";</div><div class='add'>+		bus-range = &lt;0x00 0xff&gt;;</div><div class='add'>+		ranges = &lt;0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='add'>+		interrupt-map = &lt;0 0 0 1 &amp;pcie_intc0 0&gt;,</div><div class='add'>+				&lt;0 0 0 2 &amp;pcie_intc0 1&gt;,</div><div class='add'>+				&lt;0 0 0 3 &amp;pcie_intc0 2&gt;,</div><div class='add'>+				&lt;0 0 0 4 &amp;pcie_intc0 3&gt;;</div><div class='add'>+		pcie_intc0: interrupt-controller {</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#address-cells = &lt;0&gt;;</div><div class='ctx'> 			#interrupt-cells = &lt;1&gt;;</div><div class='del'>-			ranges;</div><div class='del'>-			interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='del'>-			interrupt-map = &lt;0 0 0 1 &amp;pcie_intc1 0&gt;,</div><div class='del'>-					&lt;0 0 0 2 &amp;pcie_intc1 1&gt;,</div><div class='del'>-					&lt;0 0 0 3 &amp;pcie_intc1 2&gt;,</div><div class='del'>-					&lt;0 0 0 4 &amp;pcie_intc1 3&gt;;</div><div class='del'>-			pcie_intc1: interrupt-controller {</div><div class='del'>-				interrupt-controller;</div><div class='del'>-				#address-cells = &lt;0&gt;;</div><div class='del'>-				#interrupt-cells = &lt;1&gt;;</div><div class='del'>-			};</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt6331.dtsi b/arch/arm64/boot/dts/mediatek/mt6331.dtsi<br/>new file mode 100644<br/>index 000000000000..243afbffa21f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt6331.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt6331.dtsi</a></div><div class='hunk'>@@ -0,0 +1,284 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2023 Collabora Ltd.</div><div class='add'>+ * Author: AngeloGioacchino Del Regno &lt;angelogioacchino.delregno@collabora.com&gt;</div><div class='add'>+ */</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+</div><div class='add'>+&amp;pwrap {</div><div class='add'>+	pmic: pmic {</div><div class='add'>+		compatible = "mediatek,mt6331";</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		mt6331regulator: regulators {</div><div class='add'>+			compatible = "mediatek,mt6331-regulator";</div><div class='add'>+</div><div class='add'>+			mt6331_vdvfs11_reg: buck-vdvfs11 {</div><div class='add'>+				regulator-name = "vdvfs11";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1493750&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12500&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;0&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;0 1&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6331_vdvfs12_reg: buck-vdvfs12 {</div><div class='add'>+				regulator-name = "vdvfs12";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1493750&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12500&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;0&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;0 1&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6331_vdvfs13_reg: buck-vdvfs13 {</div><div class='add'>+				regulator-name = "vdvfs13";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1493750&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12500&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;0&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;0 1&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6331_vdvfs14_reg: buck-vdvfs14 {</div><div class='add'>+				regulator-name = "vdvfs14";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1493750&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12500&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;0&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;0 1&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6331_vcore2_reg: buck-vcore2 {</div><div class='add'>+				regulator-name = "vcore2";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1493750&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12500&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;0&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;0 1&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6331_vio18_reg: buck-vio18 {</div><div class='add'>+				regulator-name = "vio18";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12500&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;0&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;0 1&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6331_vtcxo1_reg: ldo-vtcxo1 {</div><div class='add'>+				regulator-name = "vtcxo1";</div><div class='add'>+				regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;0&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6331_vtcxo2_reg: ldo-vtcxo2 {</div><div class='add'>+				regulator-name = "vtcxo2";</div><div class='add'>+				regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;0&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6331_avdd32_aud_reg: ldo-avdd32aud {</div><div class='add'>+				regulator-name = "avdd32_aud";</div><div class='add'>+				regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3200000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;0&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6331_vauxa32_reg: ldo-vauxa32 {</div><div class='add'>+				regulator-name = "vauxa32";</div><div class='add'>+				regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3200000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6331_vcama_reg: ldo-vcama {</div><div class='add'>+				regulator-name = "vcama";</div><div class='add'>+				regulator-min-microvolt = &lt;1500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6331_vio28_reg: ldo-vio28 {</div><div class='add'>+				regulator-name = "vio28";</div><div class='add'>+				regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;0&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6331_vcamaf_reg: ldo-vcamaf {</div><div class='add'>+				regulator-name = "vcam_af";</div><div class='add'>+				regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6331_vmc_reg: ldo-vmc {</div><div class='add'>+				regulator-name = "vmc";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6331_vmch_reg: ldo-vmch {</div><div class='add'>+				regulator-name = "vmch";</div><div class='add'>+				regulator-min-microvolt = &lt;3000000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6331_vemc33_reg: ldo-vemc33 {</div><div class='add'>+				regulator-name = "vemc33";</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;0&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6331_vgp1_reg: ldo-vgp1 {</div><div class='add'>+				regulator-name = "vgp1";</div><div class='add'>+				regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;0&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6331_vsim1_reg: ldo-vsim1 {</div><div class='add'>+				regulator-name = "vsim1";</div><div class='add'>+				regulator-min-microvolt = &lt;1700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3100000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;0&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6331_vsim2_reg: ldo-vsim2 {</div><div class='add'>+				regulator-name = "vsim2";</div><div class='add'>+				regulator-min-microvolt = &lt;1700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3100000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6331_vmipi_reg: ldo-vmipi {</div><div class='add'>+				regulator-name = "vmipi";</div><div class='add'>+				regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;0&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6331_vibr_reg: ldo-vibr {</div><div class='add'>+				regulator-name = "vibr";</div><div class='add'>+				regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6331_vgp4_reg: ldo-vgp4 {</div><div class='add'>+				regulator-name = "vgp4";</div><div class='add'>+				regulator-min-microvolt = &lt;1600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2200000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;0&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6331_vcamd_reg: ldo-vcamd {</div><div class='add'>+				regulator-name = "vcamd";</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1500000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;0&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6331_vusb10_reg: ldo-vusb10 {</div><div class='add'>+				regulator-name = "vusb";</div><div class='add'>+				regulator-min-microvolt = &lt;1000000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;0&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6331_vcamio_reg: ldo-vcamio {</div><div class='add'>+				regulator-name = "vcam_io";</div><div class='add'>+				regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6331_vsram_reg: ldo-vsram {</div><div class='add'>+				regulator-name = "vsram";</div><div class='add'>+				regulator-min-microvolt = &lt;1012500&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1012500&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;0&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6331_vgp2_reg: ldo-vgp2 {</div><div class='add'>+				regulator-name = "vgp2";</div><div class='add'>+				regulator-min-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1500000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;0&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6331_vgp3_reg: ldo-vgp3 {</div><div class='add'>+				regulator-name = "vgp3";</div><div class='add'>+				regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;0&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6331_vrtc_reg: ldo-vrtc {</div><div class='add'>+				regulator-name = "vrtc";</div><div class='add'>+				regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;0&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6331_vdig18_reg: ldo-vdig18 {</div><div class='add'>+				regulator-name = "vdig18";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;0&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mt6331rtc: rtc {</div><div class='add'>+			compatible = "mediatek,mt6331-rtc";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mt6331keys: keys {</div><div class='add'>+			compatible = "mediatek,mt6331-keys";</div><div class='add'>+			power {</div><div class='add'>+				linux,keycodes = &lt;KEY_POWER&gt;;</div><div class='add'>+				wakeup-source;</div><div class='add'>+			};</div><div class='add'>+			home {</div><div class='add'>+				linux,keycodes = &lt;KEY_HOME&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt6357.dtsi b/arch/arm64/boot/dts/mediatek/mt6357.dtsi<br/>new file mode 100644<br/>index 000000000000..dca4e5c3d8e2<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt6357.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt6357.dtsi</a></div><div class='hunk'>@@ -0,0 +1,277 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2020 MediaTek Inc.</div><div class='add'>+ * Copyright (c) 2023 BayLibre Inc.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+</div><div class='add'>+&amp;pwrap {</div><div class='add'>+	mt6357_pmic: pmic {</div><div class='add'>+		compatible = "mediatek,mt6357";</div><div class='add'>+</div><div class='add'>+		pmic_adc: adc {</div><div class='add'>+			compatible = "mediatek,mt6357-auxadc";</div><div class='add'>+			#io-channel-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			mt6357_vproc_reg: buck-vproc {</div><div class='add'>+				regulator-name = "vproc";</div><div class='add'>+				regulator-min-microvolt = &lt;518750&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1312500&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;6250&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;220&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6357_vcore_reg: buck-vcore {</div><div class='add'>+				regulator-name = "vcore";</div><div class='add'>+				regulator-min-microvolt = &lt;518750&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1312500&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;6250&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;220&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6357_vmodem_reg: buck-vmodem {</div><div class='add'>+				regulator-name = "vmodem";</div><div class='add'>+				regulator-min-microvolt = &lt;500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1193750&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;6250&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;220&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6357_vs1_reg: buck-vs1 {</div><div class='add'>+				regulator-name = "vs1";</div><div class='add'>+				regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2200000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12500&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;220&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6357_vpa_reg: buck-vpa {</div><div class='add'>+				regulator-name = "vpa";</div><div class='add'>+				regulator-min-microvolt = &lt;500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3650000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;50000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;220&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6357_vfe28_reg: ldo-vfe28 {</div><div class='add'>+				regulator-name = "vfe28";</div><div class='add'>+				regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;264&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6357_vxo22_reg: ldo-vxo22 {</div><div class='add'>+				regulator-name = "vxo22";</div><div class='add'>+				regulator-min-microvolt = &lt;2200000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2400000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;110&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6357_vrf18_reg: ldo-vrf18 {</div><div class='add'>+				regulator-name = "vrf18";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;110&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6357_vrf12_reg: ldo-vrf12 {</div><div class='add'>+				regulator-name = "vrf12";</div><div class='add'>+				regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;110&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6357_vefuse_reg: ldo-vefuse {</div><div class='add'>+				regulator-name = "vefuse";</div><div class='add'>+				regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;264&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6357_vcn33_bt_reg: ldo-vcn33-bt {</div><div class='add'>+				regulator-name = "vcn33-bt";</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3500000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;264&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6357_vcn33_wifi_reg: ldo-vcn33-wifi {</div><div class='add'>+				regulator-name = "vcn33-wifi";</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3500000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;264&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6357_vcn28_reg: ldo-vcn28 {</div><div class='add'>+				regulator-name = "vcn28";</div><div class='add'>+				regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;264&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6357_vcn18_reg: ldo-vcn18 {</div><div class='add'>+				regulator-name = "vcn18";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;264&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6357_vcama_reg: ldo-vcama {</div><div class='add'>+				regulator-name = "vcama";</div><div class='add'>+				regulator-min-microvolt = &lt;2500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;264&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6357_vcamd_reg: ldo-vcamd {</div><div class='add'>+				regulator-name = "vcamd";</div><div class='add'>+				regulator-min-microvolt = &lt;1000000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;264&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6357_vcamio_reg: ldo-vcamio18 {</div><div class='add'>+				regulator-name = "vcamio";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;264&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6357_vldo28_reg: ldo-vldo28 {</div><div class='add'>+				regulator-name = "vldo28";</div><div class='add'>+				regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3000000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;264&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6357_vsram_others_reg: ldo-vsram-others {</div><div class='add'>+				regulator-name = "vsram-others";</div><div class='add'>+				regulator-min-microvolt = &lt;518750&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1312500&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;6250&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;110&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6357_vsram_proc_reg: ldo-vsram-proc {</div><div class='add'>+				regulator-name = "vsram-proc";</div><div class='add'>+				regulator-min-microvolt = &lt;518750&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1312500&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;6250&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;110&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6357_vaux18_reg: ldo-vaux18 {</div><div class='add'>+				regulator-name = "vaux18";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;264&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6357_vaud28_reg: ldo-vaud28 {</div><div class='add'>+				regulator-name = "vaud28";</div><div class='add'>+				regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;264&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6357_vio28_reg: ldo-vio28 {</div><div class='add'>+				regulator-name = "vio28";</div><div class='add'>+				regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;264&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6357_vio18_reg: ldo-vio18 {</div><div class='add'>+				regulator-name = "vio18";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;264&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6357_vdram_reg: ldo-vdram {</div><div class='add'>+				regulator-name = "vdram";</div><div class='add'>+				regulator-min-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;3300&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6357_vmc_reg: ldo-vmc {</div><div class='add'>+				regulator-name = "vmc";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;44&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6357_vmch_reg: ldo-vmch {</div><div class='add'>+				regulator-name = "vmch";</div><div class='add'>+				regulator-min-microvolt = &lt;2900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;44&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6357_vemc_reg: ldo-vemc {</div><div class='add'>+				regulator-name = "vemc";</div><div class='add'>+				regulator-min-microvolt = &lt;2900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;44&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6357_vsim1_reg: ldo-vsim1 {</div><div class='add'>+				regulator-name = "vsim1";</div><div class='add'>+				regulator-min-microvolt = &lt;1700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3100000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;264&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6357_vsim2_reg: ldo-vsim2 {</div><div class='add'>+				regulator-name = "vsim2";</div><div class='add'>+				regulator-min-microvolt = &lt;1700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3100000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;264&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6357_vibr_reg: ldo-vibr {</div><div class='add'>+				regulator-name = "vibr";</div><div class='add'>+				regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;44&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6357_vusb33_reg: ldo-vusb33 {</div><div class='add'>+				regulator-name = "vusb33";</div><div class='add'>+				regulator-min-microvolt = &lt;3000000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3100000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;264&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rtc {</div><div class='add'>+			compatible = "mediatek,mt6357-rtc";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		keys {</div><div class='add'>+			compatible = "mediatek,mt6357-keys";</div><div class='add'>+</div><div class='add'>+			key-power {</div><div class='add'>+				linux,keycodes = &lt;KEY_POWER&gt;;</div><div class='add'>+				wakeup-source;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			key-home {</div><div class='add'>+				linux,keycodes = &lt;KEY_HOME&gt;;</div><div class='add'>+				wakeup-source;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt6358.dtsi b/arch/arm64/boot/dts/mediatek/mt6358.dtsi<br/>new file mode 100644<br/>index 000000000000..e23672a2eea4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt6358.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt6358.dtsi</a></div><div class='hunk'>@@ -0,0 +1,356 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2020 MediaTek Inc.</div><div class='add'>+ */</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+</div><div class='add'>+&amp;pwrap {</div><div class='add'>+	pmic: pmic {</div><div class='add'>+		compatible = "mediatek,mt6358";</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		pmic_adc: adc {</div><div class='add'>+			compatible = "mediatek,mt6358-auxadc";</div><div class='add'>+			#io-channel-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mt6358codec: audio-codec {</div><div class='add'>+			compatible = "mediatek,mt6358-sound";</div><div class='add'>+			mediatek,dmic-mode = &lt;0&gt;; /* two-wires */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mt6358regulator: regulators {</div><div class='add'>+			compatible = "mediatek,mt6358-regulator";</div><div class='add'>+</div><div class='add'>+			mt6358_vdram1_reg: buck_vdram1 {</div><div class='add'>+				regulator-name = "vdram1";</div><div class='add'>+				regulator-min-microvolt = &lt;500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2087500&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12500&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;0&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-allowed-modes = &lt;0 1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6358_vcore_reg: buck_vcore {</div><div class='add'>+				regulator-name = "vcore";</div><div class='add'>+				regulator-min-microvolt = &lt;500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1293750&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;6250&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;200&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-allowed-modes = &lt;0 1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6358_vpa_reg: buck_vpa {</div><div class='add'>+				regulator-name = "vpa";</div><div class='add'>+				regulator-min-microvolt = &lt;500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3650000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;50000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;250&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;0 1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6358_vproc11_reg: buck_vproc11 {</div><div class='add'>+				regulator-name = "vproc11";</div><div class='add'>+				regulator-min-microvolt = &lt;500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1293750&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;6250&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;200&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-allowed-modes = &lt;0 1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6358_vproc12_reg: buck_vproc12 {</div><div class='add'>+				regulator-name = "vproc12";</div><div class='add'>+				regulator-min-microvolt = &lt;500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1293750&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;6250&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;200&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-allowed-modes = &lt;0 1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6358_vgpu_reg: buck_vgpu {</div><div class='add'>+				regulator-name = "vgpu";</div><div class='add'>+				regulator-min-microvolt = &lt;500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1293750&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;6250&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;200&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;0 1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6358_vs2_reg: buck_vs2 {</div><div class='add'>+				regulator-name = "vs2";</div><div class='add'>+				regulator-min-microvolt = &lt;500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2087500&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12500&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;0&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6358_vmodem_reg: buck_vmodem {</div><div class='add'>+				regulator-name = "vmodem";</div><div class='add'>+				regulator-min-microvolt = &lt;500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1293750&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;6250&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;900&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-allowed-modes = &lt;0 1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6358_vs1_reg: buck_vs1 {</div><div class='add'>+				regulator-name = "vs1";</div><div class='add'>+				regulator-min-microvolt = &lt;1000000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2587500&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12500&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;0&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6358_vdram2_reg: ldo_vdram2 {</div><div class='add'>+				regulator-name = "vdram2";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;3300&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6358_vsim1_reg: ldo_vsim1 {</div><div class='add'>+				regulator-name = "vsim1";</div><div class='add'>+				regulator-min-microvolt = &lt;1700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3100000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;540&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6358_vibr_reg: ldo_vibr {</div><div class='add'>+				regulator-name = "vibr";</div><div class='add'>+				regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;60&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6358_vrf12_reg: ldo_vrf12 {</div><div class='add'>+				regulator-name = "vrf12";</div><div class='add'>+				regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;120&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6358_vio18_reg: ldo_vio18 {</div><div class='add'>+				regulator-name = "vio18";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;2700&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6358_vusb_reg: ldo_vusb {</div><div class='add'>+				regulator-name = "vusb";</div><div class='add'>+				regulator-min-microvolt = &lt;3000000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3100000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;270&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6358_vcamio_reg: ldo_vcamio {</div><div class='add'>+				regulator-name = "vcamio";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;325&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6358_vcamd_reg: ldo_vcamd {</div><div class='add'>+				regulator-name = "vcamd";</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;325&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6358_vcn18_reg: ldo_vcn18 {</div><div class='add'>+				regulator-name = "vcn18";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;270&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6358_vfe28_reg: ldo_vfe28 {</div><div class='add'>+				regulator-name = "vfe28";</div><div class='add'>+				regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;270&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6358_vsram_proc11_reg: ldo_vsram_proc11 {</div><div class='add'>+				regulator-name = "vsram_proc11";</div><div class='add'>+				regulator-min-microvolt = &lt;500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1293750&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;6250&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;240&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6358_vcn28_reg: ldo_vcn28 {</div><div class='add'>+				regulator-name = "vcn28";</div><div class='add'>+				regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;270&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6358_vsram_others_reg: ldo_vsram_others {</div><div class='add'>+				regulator-name = "vsram_others";</div><div class='add'>+				regulator-min-microvolt = &lt;500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1293750&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;6250&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;240&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6358_vsram_gpu_reg: ldo_vsram_gpu {</div><div class='add'>+				regulator-name = "vsram_gpu";</div><div class='add'>+				regulator-min-microvolt = &lt;500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1293750&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;6250&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;240&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6358_vxo22_reg: ldo_vxo22 {</div><div class='add'>+				regulator-name = "vxo22";</div><div class='add'>+				regulator-min-microvolt = &lt;2200000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2200000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;120&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6358_vefuse_reg: ldo_vefuse {</div><div class='add'>+				regulator-name = "vefuse";</div><div class='add'>+				regulator-min-microvolt = &lt;1700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1900000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;270&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6358_vaux18_reg: ldo_vaux18 {</div><div class='add'>+				regulator-name = "vaux18";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;270&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6358_vmch_reg: ldo_vmch {</div><div class='add'>+				regulator-name = "vmch";</div><div class='add'>+				regulator-min-microvolt = &lt;2900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;60&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6358_vbif28_reg: ldo_vbif28 {</div><div class='add'>+				regulator-name = "vbif28";</div><div class='add'>+				regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;270&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6358_vsram_proc12_reg: ldo_vsram_proc12 {</div><div class='add'>+				regulator-name = "vsram_proc12";</div><div class='add'>+				regulator-min-microvolt = &lt;500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1293750&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;6250&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;240&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6358_vcama1_reg: ldo_vcama1 {</div><div class='add'>+				regulator-name = "vcama1";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3000000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;325&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6358_vemc_reg: ldo_vemc {</div><div class='add'>+				regulator-name = "vemc";</div><div class='add'>+				regulator-min-microvolt = &lt;2900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;60&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6358_vio28_reg: ldo_vio28 {</div><div class='add'>+				regulator-name = "vio28";</div><div class='add'>+				regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;270&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6358_va12_reg: ldo_va12 {</div><div class='add'>+				regulator-name = "va12";</div><div class='add'>+				regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;270&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6358_vrf18_reg: ldo_vrf18 {</div><div class='add'>+				regulator-name = "vrf18";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;120&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6358_vcn33_reg: ldo_vcn33 {</div><div class='add'>+				regulator-name = "vcn33";</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3500000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;270&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6358_vcama2_reg: ldo_vcama2 {</div><div class='add'>+				regulator-name = "vcama2";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3000000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;325&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6358_vmc_reg: ldo_vmc {</div><div class='add'>+				regulator-name = "vmc";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;60&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6358_vldo28_reg: ldo_vldo28 {</div><div class='add'>+				regulator-name = "vldo28";</div><div class='add'>+				regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3000000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;270&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6358_vaud28_reg: ldo_vaud28 {</div><div class='add'>+				regulator-name = "vaud28";</div><div class='add'>+				regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;270&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6358_vsim2_reg: ldo_vsim2 {</div><div class='add'>+				regulator-name = "vsim2";</div><div class='add'>+				regulator-min-microvolt = &lt;1700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3100000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;540&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mt6358rtc: rtc {</div><div class='add'>+			compatible = "mediatek,mt6358-rtc";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mt6358keys: keys {</div><div class='add'>+			compatible = "mediatek,mt6358-keys";</div><div class='add'>+			power {</div><div class='add'>+				linux,keycodes = &lt;KEY_POWER&gt;;</div><div class='add'>+				wakeup-source;</div><div class='add'>+			};</div><div class='add'>+			home {</div><div class='add'>+				linux,keycodes = &lt;KEY_HOME&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt6359.dtsi b/arch/arm64/boot/dts/mediatek/mt6359.dtsi<br/>new file mode 100644<br/>index 000000000000..467d8a4c2aa7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt6359.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt6359.dtsi</a></div><div class='hunk'>@@ -0,0 +1,307 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2022 MediaTek Inc.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;pwrap {</div><div class='add'>+	pmic: pmic {</div><div class='add'>+		compatible = "mediatek,mt6359";</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		pmic_adc: adc {</div><div class='add'>+			compatible = "mediatek,mt6359-auxadc";</div><div class='add'>+			#io-channel-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mt6359codec: audio-codec {</div><div class='add'>+			compatible = "mediatek,mt6359-codec";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			compatible = "mediatek,mt6359-regulator";</div><div class='add'>+</div><div class='add'>+			mt6359_vs1_buck_reg: buck_vs1 {</div><div class='add'>+				regulator-name = "vs1";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2200000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;0&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+			mt6359_vgpu11_buck_reg: buck_vgpu11 {</div><div class='add'>+				regulator-name = "vgpu11";</div><div class='add'>+				regulator-min-microvolt = &lt;400000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1193750&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;5000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;200&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;0 1 2&gt;;</div><div class='add'>+			};</div><div class='add'>+			mt6359_vmodem_buck_reg: buck_vmodem {</div><div class='add'>+				regulator-name = "vmodem";</div><div class='add'>+				regulator-min-microvolt = &lt;400000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;10760&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;200&gt;;</div><div class='add'>+			};</div><div class='add'>+			mt6359_vpu_buck_reg: buck_vpu {</div><div class='add'>+				regulator-name = "vpu";</div><div class='add'>+				regulator-min-microvolt = &lt;400000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1193750&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;5000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;200&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;0 1 2&gt;;</div><div class='add'>+			};</div><div class='add'>+			mt6359_vcore_buck_reg: buck_vcore {</div><div class='add'>+				regulator-name = "vcore";</div><div class='add'>+				regulator-min-microvolt = &lt;400000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;5000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;200&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;0 1 2&gt;;</div><div class='add'>+			};</div><div class='add'>+			mt6359_vs2_buck_reg: buck_vs2 {</div><div class='add'>+				regulator-name = "vs2";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1600000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;0&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+			mt6359_vpa_buck_reg: buck_vpa {</div><div class='add'>+				regulator-name = "vpa";</div><div class='add'>+				regulator-min-microvolt = &lt;500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3650000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;300&gt;;</div><div class='add'>+			};</div><div class='add'>+			mt6359_vproc2_buck_reg: buck_vproc2 {</div><div class='add'>+				regulator-name = "vproc2";</div><div class='add'>+				regulator-min-microvolt = &lt;400000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1193750&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;7500&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;200&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;0 1 2&gt;;</div><div class='add'>+			};</div><div class='add'>+			mt6359_vproc1_buck_reg: buck_vproc1 {</div><div class='add'>+				regulator-name = "vproc1";</div><div class='add'>+				regulator-min-microvolt = &lt;400000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1193750&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;7500&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;200&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;0 1 2&gt;;</div><div class='add'>+			};</div><div class='add'>+			mt6359_vcore_sshub_buck_reg: buck_vcore_sshub {</div><div class='add'>+				regulator-name = "vcore_sshub";</div><div class='add'>+				regulator-min-microvolt = &lt;400000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1193750&gt;;</div><div class='add'>+			};</div><div class='add'>+			mt6359_vgpu11_sshub_buck_reg: buck_vgpu11_sshub {</div><div class='add'>+				regulator-name = "vgpu11_sshub";</div><div class='add'>+				regulator-min-microvolt = &lt;400000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1193750&gt;;</div><div class='add'>+			};</div><div class='add'>+			mt6359_vaud18_ldo_reg: ldo_vaud18 {</div><div class='add'>+				regulator-name = "vaud18";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;240&gt;;</div><div class='add'>+			};</div><div class='add'>+			mt6359_vsim1_ldo_reg: ldo_vsim1 {</div><div class='add'>+				regulator-name = "vsim1";</div><div class='add'>+				regulator-min-microvolt = &lt;1700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3100000&gt;;</div><div class='add'>+			};</div><div class='add'>+			mt6359_vibr_ldo_reg: ldo_vibr {</div><div class='add'>+				regulator-name = "vibr";</div><div class='add'>+				regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+			};</div><div class='add'>+			mt6359_vrf12_ldo_reg: ldo_vrf12 {</div><div class='add'>+				regulator-name = "vrf12";</div><div class='add'>+				regulator-min-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+			};</div><div class='add'>+			mt6359_vusb_ldo_reg: ldo_vusb {</div><div class='add'>+				regulator-name = "vusb";</div><div class='add'>+				regulator-min-microvolt = &lt;3000000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3000000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;960&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+			mt6359_vsram_proc2_ldo_reg: ldo_vsram_proc2 {</div><div class='add'>+				regulator-name = "vsram_proc2";</div><div class='add'>+				regulator-min-microvolt = &lt;500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1293750&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;7500&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;240&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+			mt6359_vio18_ldo_reg: ldo_vio18 {</div><div class='add'>+				regulator-name = "vio18";</div><div class='add'>+				regulator-min-microvolt = &lt;1700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1900000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;960&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+			mt6359_vcamio_ldo_reg: ldo_vcamio {</div><div class='add'>+				regulator-name = "vcamio";</div><div class='add'>+				regulator-min-microvolt = &lt;1700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1900000&gt;;</div><div class='add'>+			};</div><div class='add'>+			mt6359_vcn18_ldo_reg: ldo_vcn18 {</div><div class='add'>+				regulator-name = "vcn18";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;240&gt;;</div><div class='add'>+			};</div><div class='add'>+			mt6359_vfe28_ldo_reg: ldo_vfe28 {</div><div class='add'>+				regulator-name = "vfe28";</div><div class='add'>+				regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;120&gt;;</div><div class='add'>+			};</div><div class='add'>+			mt6359_vcn13_ldo_reg: ldo_vcn13 {</div><div class='add'>+				regulator-name = "vcn13";</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+			};</div><div class='add'>+			mt6359_vcn33_1_bt_ldo_reg: ldo_vcn33_1_bt {</div><div class='add'>+				regulator-name = "vcn33_1_bt";</div><div class='add'>+				regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3500000&gt;;</div><div class='add'>+			};</div><div class='add'>+			mt6359_vcn33_1_wifi_ldo_reg: ldo_vcn33_1_wifi {</div><div class='add'>+				regulator-name = "vcn33_1_wifi";</div><div class='add'>+				regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3500000&gt;;</div><div class='add'>+			};</div><div class='add'>+			mt6359_vaux18_ldo_reg: ldo_vaux18 {</div><div class='add'>+				regulator-name = "vaux18";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;240&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+			mt6359_vsram_others_ldo_reg: ldo_vsram_others {</div><div class='add'>+				regulator-name = "vsram_others";</div><div class='add'>+				regulator-min-microvolt = &lt;500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1293750&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;5000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;240&gt;;</div><div class='add'>+			};</div><div class='add'>+			mt6359_vefuse_ldo_reg: ldo_vefuse {</div><div class='add'>+				regulator-name = "vefuse";</div><div class='add'>+				regulator-min-microvolt = &lt;1700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2000000&gt;;</div><div class='add'>+			};</div><div class='add'>+			mt6359_vxo22_ldo_reg: ldo_vxo22 {</div><div class='add'>+				regulator-name = "vxo22";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2200000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+			mt6359_vrfck_ldo_reg: ldo_vrfck {</div><div class='add'>+				regulator-name = "vrfck";</div><div class='add'>+				regulator-min-microvolt = &lt;1500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1700000&gt;;</div><div class='add'>+			};</div><div class='add'>+			mt6359_vrfck_1_ldo_reg: ldo_vrfck_1 {</div><div class='add'>+				regulator-name = "vrfck";</div><div class='add'>+				regulator-min-microvolt = &lt;1240000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1600000&gt;;</div><div class='add'>+			};</div><div class='add'>+			mt6359_vbif28_ldo_reg: ldo_vbif28 {</div><div class='add'>+				regulator-name = "vbif28";</div><div class='add'>+				regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;240&gt;;</div><div class='add'>+			};</div><div class='add'>+			mt6359_vio28_ldo_reg: ldo_vio28 {</div><div class='add'>+				regulator-name = "vio28";</div><div class='add'>+				regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+			mt6359_vemc_ldo_reg: ldo_vemc {</div><div class='add'>+				regulator-name = "vemc";</div><div class='add'>+				regulator-min-microvolt = &lt;2900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+			};</div><div class='add'>+			mt6359_vemc_1_ldo_reg: ldo_vemc_1 {</div><div class='add'>+				regulator-name = "vemc";</div><div class='add'>+				regulator-min-microvolt = &lt;2500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+			};</div><div class='add'>+			mt6359_vcn33_2_bt_ldo_reg: ldo_vcn33_2_bt {</div><div class='add'>+				regulator-name = "vcn33_2_bt";</div><div class='add'>+				regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3500000&gt;;</div><div class='add'>+			};</div><div class='add'>+			mt6359_vcn33_2_wifi_ldo_reg: ldo_vcn33_2_wifi {</div><div class='add'>+				regulator-name = "vcn33_2_wifi";</div><div class='add'>+				regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3500000&gt;;</div><div class='add'>+			};</div><div class='add'>+			mt6359_va12_ldo_reg: ldo_va12 {</div><div class='add'>+				regulator-name = "va12";</div><div class='add'>+				regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+			mt6359_va09_ldo_reg: ldo_va09 {</div><div class='add'>+				regulator-name = "va09";</div><div class='add'>+				regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+			};</div><div class='add'>+			mt6359_vrf18_ldo_reg: ldo_vrf18 {</div><div class='add'>+				regulator-name = "vrf18";</div><div class='add'>+				regulator-min-microvolt = &lt;1700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1810000&gt;;</div><div class='add'>+			};</div><div class='add'>+			mt6359_vsram_md_ldo_reg: ldo_vsram_md {</div><div class='add'>+				regulator-name = "vsram_md";</div><div class='add'>+				regulator-min-microvolt = &lt;500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1293750&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;10760&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;240&gt;;</div><div class='add'>+			};</div><div class='add'>+			mt6359_vufs_ldo_reg: ldo_vufs {</div><div class='add'>+				regulator-name = "vufs";</div><div class='add'>+				regulator-min-microvolt = &lt;1700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1900000&gt;;</div><div class='add'>+			};</div><div class='add'>+			mt6359_vm18_ldo_reg: ldo_vm18 {</div><div class='add'>+				regulator-name = "vm18";</div><div class='add'>+				regulator-min-microvolt = &lt;1700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1900000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+			mt6359_vbbck_ldo_reg: ldo_vbbck {</div><div class='add'>+				regulator-name = "vbbck";</div><div class='add'>+				regulator-min-microvolt = &lt;1100000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+			};</div><div class='add'>+			mt6359_vsram_proc1_ldo_reg: ldo_vsram_proc1 {</div><div class='add'>+				regulator-name = "vsram_proc1";</div><div class='add'>+				regulator-min-microvolt = &lt;500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1293750&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;7500&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;240&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+			mt6359_vsim2_ldo_reg: ldo_vsim2 {</div><div class='add'>+				regulator-name = "vsim2";</div><div class='add'>+				regulator-min-microvolt = &lt;1700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3100000&gt;;</div><div class='add'>+			};</div><div class='add'>+			mt6359_vsram_others_sshub_ldo: ldo_vsram_others_sshub {</div><div class='add'>+				regulator-name = "vsram_others_sshub";</div><div class='add'>+				regulator-min-microvolt = &lt;500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1293750&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mt6359rtc: rtc {</div><div class='add'>+			compatible = "mediatek,mt6358-rtc";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt6755-evb.dts b/arch/arm64/boot/dts/mediatek/mt6755-evb.dts<br/>index e079b7932ba3..00b14f85c6a1 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt6755-evb.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt6755-evb.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt6755-evb.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt6755-evb.dts</a></div><div class='hunk'>@@ -9,6 +9,7 @@</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	model = "MediaTek MT6755 EVB";</div><div class='add'>+	chassis-type = "embedded";</div><div class='ctx'> 	compatible = "mediatek,mt6755-evb", "mediatek,mt6755";</div><div class='ctx'> </div><div class='ctx'> 	aliases {</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt6755.dtsi b/arch/arm64/boot/dts/mediatek/mt6755.dtsi<br/>index 01ba77669717..8da5c0a56a02 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt6755.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt6755.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt6755.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt6755.dtsi</a></div><div class='hunk'>@@ -1,14 +1,7 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2016 MediaTek Inc.</div><div class='ctx'>  * Author: Mars.C &lt;mars.cheng@mediatek.com&gt;</div><div class='del'>- *</div><div class='del'>- * This program is free software; you can redistribute it and/or modify</div><div class='del'>- * it under the terms of the GNU General Public License version 2 as</div><div class='del'>- * published by the Free Software Foundation.</div><div class='del'>- *</div><div class='del'>- * This program is distributed in the hope that it will be useful,</div><div class='del'>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the</div><div class='del'>- * GNU General Public License for more details.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='hunk'>@@ -105,7 +98,7 @@</div><div class='ctx'> 			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sysirq: intpol-controller@10200620 {</div><div class='add'>+	sysirq: interrupt-controller@10200620 {</div><div class='ctx'> 		compatible = "mediatek,mt6755-sysirq",</div><div class='ctx'> 			     "mediatek,mt6577-sysirq";</div><div class='ctx'> 		interrupt-controller;</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt6779-evb.dts b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts<br/>new file mode 100644<br/>index 000000000000..56b1bf06e26b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt6779-evb.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt6779-evb.dts</a></div><div class='hunk'>@@ -0,0 +1,32 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2019 MediaTek Inc.</div><div class='add'>+ * Author: Mars.C &lt;mars.cheng@mediatek.com&gt;</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt6779.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "MediaTek MT6779 EVB";</div><div class='add'>+	chassis-type = "embedded";</div><div class='add'>+	compatible = "mediatek,mt6779-evb", "mediatek,mt6779";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0 0x40000000 0 0x1e800000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:921600n8";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi<br/>new file mode 100644<br/>index 000000000000..70f3375916e8<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt6779.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt6779.dtsi</a></div><div class='hunk'>@@ -0,0 +1,288 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2019 MediaTek Inc.</div><div class='add'>+ * Author: Mars.C &lt;mars.cheng@mediatek.com&gt;</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/mt6779-clk.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/mt6779-pinfunc.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "mediatek,mt6779";</div><div class='add'>+	interrupt-parent = &lt;&amp;sysirq&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-0.2";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			reg = &lt;0x000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@1 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			reg = &lt;0x100&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@2 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			reg = &lt;0x200&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@3 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			reg = &lt;0x300&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu4: cpu@4 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			reg = &lt;0x400&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu5: cpu@5 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			reg = &lt;0x500&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu6: cpu@6 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a75";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			reg = &lt;0x600&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu7: cpu@7 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a75";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			reg = &lt;0x700&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu {</div><div class='add'>+		compatible = "arm,armv8-pmuv3";</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_LOW 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk26m: oscillator-26m {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;26000000&gt;;</div><div class='add'>+		clock-output-names = "clk26m";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk32k: oscillator-32k {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;32768&gt;;</div><div class='add'>+		clock-output-names = "clk32k";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@c000000 {</div><div class='add'>+			compatible = "arm,gic-v3";</div><div class='add'>+			#interrupt-cells = &lt;4&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			reg = &lt;0 0x0c000000 0 0x40000&gt;,  /* GICD */</div><div class='add'>+			      &lt;0 0x0c040000 0 0x200000&gt;; /* GICR */</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+</div><div class='add'>+			ppi-partitions {</div><div class='add'>+				ppi_cluster0: interrupt-partition-0 {</div><div class='add'>+					affinity = &lt;&amp;cpu0 &amp;cpu1 \</div><div class='add'>+						&amp;cpu2 &amp;cpu3 &amp;cpu4 &amp;cpu5&gt;;</div><div class='add'>+				};</div><div class='add'>+				ppi_cluster1: interrupt-partition-1 {</div><div class='add'>+					affinity = &lt;&amp;cpu6 &amp;cpu7&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sysirq: interrupt-controller@c53a650 {</div><div class='add'>+			compatible = "mediatek,mt6779-sysirq",</div><div class='add'>+				     "mediatek,mt6577-sysirq";</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+			reg = &lt;0 0x0c53a650 0 0x50&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		topckgen: clock-controller@10000000 {</div><div class='add'>+			compatible = "mediatek,mt6779-topckgen", "syscon";</div><div class='add'>+			reg = &lt;0 0x10000000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		infracfg_ao: clock-controller@10001000 {</div><div class='add'>+			compatible = "mediatek,mt6779-infracfg_ao", "syscon";</div><div class='add'>+			reg = &lt;0 0x10001000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pio: pinctrl@10005000 {</div><div class='add'>+			compatible = "mediatek,mt6779-pinctrl";</div><div class='add'>+			reg = &lt;0 0x10005000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11c20000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11d10000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11e20000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11e70000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11ea0000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11f20000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11f30000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x1000b000 0 0x1000&gt;;</div><div class='add'>+			reg-names = "gpio", "iocfg_rm",</div><div class='add'>+				    "iocfg_br", "iocfg_lm",</div><div class='add'>+				    "iocfg_lb", "iocfg_rt",</div><div class='add'>+				    "iocfg_lt", "iocfg_tl",</div><div class='add'>+				    "eint";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;pio 0 0 210&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		apmixed: clock-controller@1000c000 {</div><div class='add'>+			compatible = "mediatek,mt6779-apmixed", "syscon";</div><div class='add'>+			reg = &lt;0 0x1000c000 0 0xe00&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pwrap: pwrap@1000d000 {</div><div class='add'>+			compatible = "mediatek,mt6779-pwrap";</div><div class='add'>+			reg = &lt;0 0x1000d000 0 0x1000&gt;;</div><div class='add'>+			reg-names = "pwrap";</div><div class='add'>+			interrupts = &lt;GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk26m&gt;, &lt;&amp;infracfg_ao CLK_INFRA_PMIC_AP&gt;;</div><div class='add'>+			clock-names = "spi", "wrap";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		devapc: devapc@10207000 {</div><div class='add'>+			compatible = "mediatek,mt6779-devapc";</div><div class='add'>+			reg = &lt;0 0x10207000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 168 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg_ao CLK_INFRA_DEVICE_APC&gt;;</div><div class='add'>+			clock-names = "devapc-infra-clock";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart0: serial@11002000 {</div><div class='add'>+			compatible = "mediatek,mt6779-uart",</div><div class='add'>+				     "mediatek,mt6577-uart";</div><div class='add'>+			reg = &lt;0 0x11002000 0 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 115 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk26m&gt;, &lt;&amp;infracfg_ao CLK_INFRA_UART0&gt;;</div><div class='add'>+			clock-names = "baud", "bus";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart1: serial@11003000 {</div><div class='add'>+			compatible = "mediatek,mt6779-uart",</div><div class='add'>+				     "mediatek,mt6577-uart";</div><div class='add'>+			reg = &lt;0 0x11003000 0 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 116 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk26m&gt;, &lt;&amp;infracfg_ao CLK_INFRA_UART1&gt;;</div><div class='add'>+			clock-names = "baud", "bus";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart2: serial@11004000 {</div><div class='add'>+			compatible = "mediatek,mt6779-uart",</div><div class='add'>+				     "mediatek,mt6577-uart";</div><div class='add'>+			reg = &lt;0 0x11004000 0 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 117 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk26m&gt;, &lt;&amp;infracfg_ao CLK_INFRA_UART2&gt;;</div><div class='add'>+			clock-names = "baud", "bus";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		audio: clock-controller@11210000 {</div><div class='add'>+			compatible = "mediatek,mt6779-audio", "syscon";</div><div class='add'>+			reg = &lt;0 0x11210000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mfgcfg: clock-controller@13fbf000 {</div><div class='add'>+			compatible = "mediatek,mt6779-mfgcfg", "syscon";</div><div class='add'>+			reg = &lt;0 0x13fbf000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmsys: syscon@14000000 {</div><div class='add'>+			compatible = "mediatek,mt6779-mmsys", "syscon";</div><div class='add'>+			reg = &lt;0 0x14000000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		imgsys: clock-controller@15020000 {</div><div class='add'>+			compatible = "mediatek,mt6779-imgsys", "syscon";</div><div class='add'>+			reg = &lt;0 0x15020000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdecsys: clock-controller@16000000 {</div><div class='add'>+			compatible = "mediatek,mt6779-vdecsys", "syscon";</div><div class='add'>+			reg = &lt;0 0x16000000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vencsys: clock-controller@17000000 {</div><div class='add'>+			compatible = "mediatek,mt6779-vencsys", "syscon";</div><div class='add'>+			reg = &lt;0 0x17000000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		camsys: clock-controller@1a000000 {</div><div class='add'>+			compatible = "mediatek,mt6779-camsys", "syscon";</div><div class='add'>+			reg = &lt;0 0x1a000000 0 0x10000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ipesys: clock-controller@1b000000 {</div><div class='add'>+			compatible = "mediatek,mt6779-ipesys", "syscon";</div><div class='add'>+			reg = &lt;0 0x1b000000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt6795-evb.dts b/arch/arm64/boot/dts/mediatek/mt6795-evb.dts<br/>index 1ed2f81edeff..e0d4d7a63139 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt6795-evb.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt6795-evb.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt6795-evb.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt6795-evb.dts</a></div><div class='hunk'>@@ -9,6 +9,7 @@</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	model = "MediaTek MT6795 Evaluation Board";</div><div class='add'>+	chassis-type = "embedded";</div><div class='ctx'> 	compatible = "mediatek,mt6795-evb", "mediatek,mt6795";</div><div class='ctx'> </div><div class='ctx'> 	aliases {</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts<br/>new file mode 100644<br/>index 000000000000..fccb948cfa45<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts</a></div><div class='hunk'>@@ -0,0 +1,494 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2022, Collabora Ltd</div><div class='add'>+ * Author: AngeloGioacchino Del Regno &lt;angelogioacchino.delregno@collabora.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include "mt6795.dtsi"</div><div class='add'>+#include "mt6331.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Sony Xperia M5";</div><div class='add'>+	compatible = "sony,xperia-m5", "mediatek,mt6795";</div><div class='add'>+	chassis-type = "handset";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		mmc0 = &amp;mmc0;</div><div class='add'>+		mmc1 = &amp;mmc1;</div><div class='add'>+		mmc2 = &amp;mmc2;</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+		serial1 = &amp;uart1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	backlight_lcd0: backlight {</div><div class='add'>+		compatible = "led-backlight";</div><div class='add'>+		leds = &lt;&amp;disp_led_pwm&gt;, &lt;&amp;pmic_bl_led&gt;;</div><div class='add'>+</div><div class='add'>+		default-brightness-level = &lt;300&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	led-controller-display {</div><div class='add'>+		compatible = "pwm-leds";</div><div class='add'>+</div><div class='add'>+		disp_led_pwm: led-0 {</div><div class='add'>+			label = "backlight-pwm";</div><div class='add'>+			pwms = &lt;&amp;pwm0 0 500000&gt;;</div><div class='add'>+			max-brightness = &lt;1024&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0 0x40000000 0 0x1e800000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved_memory: reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		/* 128 KiB reserved for ARM Trusted Firmware (BL31) */</div><div class='add'>+		bl31_secmon_reserved: secmon@43000000 {</div><div class='add'>+			reg = &lt;0 0x43000000 0 0x30000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* preloader and bootloader regions cannot be touched */</div><div class='add'>+		preloader-region@44800000 {</div><div class='add'>+			reg = &lt;0 0x44800000 0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		bootloader-region@46000000 {</div><div class='add'>+			reg = &lt;0 0x46000000 0 0x400000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vreg_disp_avdd: regulator-disp-avdd {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "disp_avdd";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;pio 138 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vreg_disp_avee: regulator-disp-avee {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "disp_avee";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;pio 139 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vreg_disp_vddh: regulator-disp-vddh {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "disp_vddh";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsi0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	panel: panel@0 {</div><div class='add'>+		compatible = "sharp,ls060t1sx01";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		avdd-supply = &lt;&amp;vreg_disp_avdd&gt;;</div><div class='add'>+		avee-supply = &lt;&amp;vreg_disp_avee&gt;;</div><div class='add'>+		vddi-supply = &lt;&amp;mt6331_vgp3_reg&gt;;</div><div class='add'>+		vddh-supply = &lt;&amp;vreg_disp_vddh&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pio 106 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		backlight = &lt;&amp;backlight_lcd0&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;disp_rst_pins&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			panel_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;dsi0_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	port {</div><div class='add'>+		dsi0_out: endpoint {</div><div class='add'>+			remote-endpoint = &lt;&amp;panel_in&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fhctl {</div><div class='add'>+	clocks = &lt;&amp;apmixedsys CLK_APMIXED_MAINPLL&gt;, &lt;&amp;apmixedsys CLK_APMIXED_MPLL&gt;,</div><div class='add'>+		 &lt;&amp;apmixedsys CLK_APMIXED_MSDCPLL&gt;;</div><div class='add'>+	mediatek,hopping-ssc-percent = &lt;8&gt;, &lt;5&gt;, &lt;8&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c0_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c1_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	accelerometer@10 {</div><div class='add'>+		compatible = "bosch,bma255";</div><div class='add'>+		reg = &lt;0x10&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;accel_pins&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	magnetometer@12 {</div><div class='add'>+		compatible = "bosch,bmm150";</div><div class='add'>+		reg = &lt;0x12&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c2_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	touchscreen@20 {</div><div class='add'>+		compatible = "syna,rmi4-i2c";</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 6 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;ts_pins&gt;;</div><div class='add'>+		syna,startup-delay-ms = &lt;160&gt;;</div><div class='add'>+		syna,reset-delay-ms = &lt;90&gt;;</div><div class='add'>+</div><div class='add'>+		rmi4-f01@1 {</div><div class='add'>+			reg = &lt;0x1&gt;;</div><div class='add'>+			syna,nosleep-mode = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rmi4-f12@12 {</div><div class='add'>+			reg = &lt;0x12&gt;;</div><div class='add'>+			syna,sensor-type = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c3_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pn547: nfc@28 {</div><div class='add'>+		compatible = "nxp,pn544-i2c";</div><div class='add'>+		reg = &lt;0x28&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 3 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;nfc_pins&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;pio 149 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		firmware-gpios = &lt;&amp;pio 94 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	proximity@48 {</div><div class='add'>+		compatible = "sensortek,stk3310";</div><div class='add'>+		reg = &lt;0x48&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 8 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;proximity_pins&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc0 {</div><div class='add'>+	/* eMMC controller */</div><div class='add'>+	mediatek,latch-ck = &lt;4&gt;; /* hs400 */</div><div class='add'>+	mediatek,hs200-cmd-int-delay = &lt;1&gt;;</div><div class='add'>+	mediatek,hs400-cmd-int-delay = &lt;1&gt;;</div><div class='add'>+	mediatek,hs400-ds-dly3 = &lt;0x1a&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	pinctrl-names = "default", "state_uhs";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc0_pins_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;mmc0_pins_uhs&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;mt6331_vemc33_reg&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;mt6331_vio18_reg&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc1 {</div><div class='add'>+	/* MicroSD card slot */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc1_pins_default&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;mt6331_vmc_reg&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;mt6331_vmch_reg&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc2 {</div><div class='add'>+	/* SDIO WiFi on MMC2 */</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc2_pins_default&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;mt6331_vmc_reg&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;mt6331_vmch_reg&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6331_vgp3_reg {</div><div class='add'>+	regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	disp_rst_pins: lcm-pins {</div><div class='add'>+		pins-rst {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO106__FUNC_GPIO106&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc0_pins_default: emmc-sdr-pins {</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO154__FUNC_MSDC0_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO155__FUNC_MSDC0_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO156__FUNC_MSDC0_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO157__FUNC_MSDC0_DAT3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO158__FUNC_MSDC0_DAT4&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO159__FUNC_MSDC0_DAT5&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO160__FUNC_MSDC0_DAT6&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO161__FUNC_MSDC0_DAT7&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO162__FUNC_MSDC0_CMD&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO163__FUNC_MSDC0_CLK&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-rst {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO165__FUNC_MSDC0_RSTB&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc0_pins_uhs: emmc-uhs-pins {</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO154__FUNC_MSDC0_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO155__FUNC_MSDC0_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO156__FUNC_MSDC0_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO157__FUNC_MSDC0_DAT3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO158__FUNC_MSDC0_DAT4&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO159__FUNC_MSDC0_DAT5&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO160__FUNC_MSDC0_DAT6&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO161__FUNC_MSDC0_DAT7&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO162__FUNC_MSDC0_CMD&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO163__FUNC_MSDC0_CLK&gt;;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-rst {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO165__FUNC_MSDC0_RSTB&gt;;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-ds {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO164__FUNC_MSDC0_DSL&gt;;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc1_pins_default: microsd-pins {</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO171__FUNC_MSDC1_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO172__FUNC_MSDC1_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO173__FUNC_MSDC1_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO174__FUNC_MSDC1_DAT3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO170__FUNC_MSDC1_CMD&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO175__FUNC_MSDC1_CLK&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc2_pins_default: sdio-pins {</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO100__FUNC_MSDC2_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO101__FUNC_MSDC2_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO102__FUNC_MSDC2_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO103__FUNC_MSDC2_DAT3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO105__FUNC_MSDC2_CMD&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO104__FUNC_MSDC2_CLK&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	nfc_pins: nfc-pins {</div><div class='add'>+		pins-irq {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO3__FUNC_GPIO3&gt;;</div><div class='add'>+			bias-pull-down;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-fw-ven {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO94__FUNC_GPIO94&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO149__FUNC_GPIO149&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ts_pins: touchscreen-pins {</div><div class='add'>+		pins-irq {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO6__FUNC_GPIO6&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-rst {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO102__FUNC_GPIO102&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	proximity_pins: proximity-pins {</div><div class='add'>+		pins-irq {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO8__FUNC_GPIO8&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	accel_pins: accelerometer-pins {</div><div class='add'>+		pins-irq {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO12__FUNC_GPIO12&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c0_pins: i2c0-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO45__FUNC_SDA0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO46__FUNC_SCL0&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c1_pins: i2c1-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO125__FUNC_SDA1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO126__FUNC_SCL1&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c2_pins: i2c2-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO43__FUNC_SDA2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO44__FUNC_SCL2&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c3_pins: i2c3-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO136__FUNC_SDA3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO137__FUNC_SCL3&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c4_pins: i2c4-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO100__FUNC_SDA4&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO101__FUNC_SCL4&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart0_pins: uart0-pins {</div><div class='add'>+		pins-rx {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO113__FUNC_URXD0&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+		pins-tx {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO114__FUNC_UTXD0&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart2_pins: uart2-pins {</div><div class='add'>+		pins-rx {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO31__FUNC_URXD2&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+		pins-tx {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO32__FUNC_UTXD2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pmic {</div><div class='add'>+	/*</div><div class='add'>+	 * Smartphones, including the Xperia M5, are equipped with a companion</div><div class='add'>+	 * MT6332 PMIC: when this is present, the main MT6331 PMIC will fire</div><div class='add'>+	 * an interrupt on the companion, so we use the MT6332 IRQ GPIO.</div><div class='add'>+	 */</div><div class='add'>+	interrupts = &lt;GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+	mt6332-led {</div><div class='add'>+		compatible = "mediatek,mt6332-led";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		pmic_bl_led: led@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			label = "backlight-pmic";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart0_pins&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart2_pins&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi<br/>index c85659d0ff5d..58833e5135c8 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt6795.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt6795.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt6795.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt6795.dtsi</a></div><div class='hunk'>@@ -1,18 +1,19 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2015 MediaTek Inc.</div><div class='del'>- * Author: Mars.C &lt;mars.cheng@mediatek.com&gt;</div><div class='del'>- *</div><div class='del'>- * This program is free software; you can redistribute it and/or modify</div><div class='del'>- * it under the terms of the GNU General Public License version 2 as</div><div class='del'>- * published by the Free Software Foundation.</div><div class='del'>- *</div><div class='del'>- * This program is distributed in the hope that it will be useful,</div><div class='del'>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the</div><div class='del'>- * GNU General Public License for more details.</div><div class='add'>+ * Copyright (C) 2023 Collabora Ltd.</div><div class='add'>+ * Authors: Mars.C &lt;mars.cheng@mediatek.com&gt;</div><div class='add'>+ *          AngeloGioacchino Del Regno &lt;angelogioacchino.delregno@collabora.com&gt;</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/mediatek,mt6795-clk.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gce/mediatek,mt6795-gce.h&gt;</div><div class='add'>+#include &lt;dt-bindings/memory/mt6795-larb-port.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/mt6795-pinfunc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/power/mt6795-power.h&gt;</div><div class='add'>+#include &lt;dt-bindings/reset/mediatek,mt6795-resets.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	compatible = "mediatek,mt6795";</div><div class='hunk'>@@ -20,6 +21,23 @@</div><div class='ctx'> 	#address-cells = &lt;2&gt;;</div><div class='ctx'> 	#size-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='add'>+	aliases {</div><div class='add'>+		ovl0 = &amp;ovl0;</div><div class='add'>+		ovl1 = &amp;ovl1;</div><div class='add'>+		rdma0 = &amp;rdma0;</div><div class='add'>+		rdma1 = &amp;rdma1;</div><div class='add'>+		rdma2 = &amp;rdma2;</div><div class='add'>+		wdma0 = &amp;wdma0;</div><div class='add'>+		wdma1 = &amp;wdma1;</div><div class='add'>+		color0 = &amp;color0;</div><div class='add'>+		color1 = &amp;color1;</div><div class='add'>+		split0 = &amp;split0;</div><div class='add'>+		split1 = &amp;split1;</div><div class='add'>+		dpi0 = &amp;dpi0;</div><div class='add'>+		dsi0 = &amp;dsi0;</div><div class='add'>+		dsi1 = &amp;dsi1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	psci {</div><div class='ctx'> 		compatible = "arm,psci-0.2";</div><div class='ctx'> 		method = "smc";</div><div class='hunk'>@@ -34,6 +52,8 @@</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			reg = &lt;0x000&gt;;</div><div class='add'>+			cci-control-port = &lt;&amp;cci_control2&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu1: cpu@1 {</div><div class='hunk'>@@ -41,6 +61,14 @@</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			reg = &lt;0x001&gt;;</div><div class='add'>+			cci-control-port = &lt;&amp;cci_control2&gt;;</div><div class='add'>+			i-cache-size = &lt;32768&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;32768&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu2: cpu@2 {</div><div class='hunk'>@@ -48,6 +76,14 @@</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			reg = &lt;0x002&gt;;</div><div class='add'>+			cci-control-port = &lt;&amp;cci_control2&gt;;</div><div class='add'>+			i-cache-size = &lt;32768&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;32768&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu3: cpu@3 {</div><div class='hunk'>@@ -55,6 +91,14 @@</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			reg = &lt;0x003&gt;;</div><div class='add'>+			cci-control-port = &lt;&amp;cci_control2&gt;;</div><div class='add'>+			i-cache-size = &lt;32768&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;32768&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu4: cpu@100 {</div><div class='hunk'>@@ -62,6 +106,14 @@</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			reg = &lt;0x100&gt;;</div><div class='add'>+			cci-control-port = &lt;&amp;cci_control1&gt;;</div><div class='add'>+			i-cache-size = &lt;32768&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;32768&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_1&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu5: cpu@101 {</div><div class='hunk'>@@ -69,6 +121,14 @@</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			reg = &lt;0x101&gt;;</div><div class='add'>+			cci-control-port = &lt;&amp;cci_control1&gt;;</div><div class='add'>+			i-cache-size = &lt;32768&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;32768&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_1&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu6: cpu@102 {</div><div class='hunk'>@@ -76,6 +136,14 @@</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			reg = &lt;0x102&gt;;</div><div class='add'>+			cci-control-port = &lt;&amp;cci_control1&gt;;</div><div class='add'>+			i-cache-size = &lt;32768&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;32768&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_1&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu7: cpu@103 {</div><div class='hunk'>@@ -83,27 +151,102 @@</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			reg = &lt;0x103&gt;;</div><div class='add'>+			cci-control-port = &lt;&amp;cci_control1&gt;;</div><div class='add'>+			i-cache-size = &lt;32768&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;32768&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu-map {</div><div class='add'>+			cluster0 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu2&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu3&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cluster1 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu4&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu5&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu6&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu7&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_0: l2-cache0 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-size = &lt;1048576&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;1024&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_1: l2-cache1 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-size = &lt;1048576&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;1024&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	system_clk: dummy13m {</div><div class='add'>+	clk26m: oscillator-26m {</div><div class='ctx'> 		compatible = "fixed-clock";</div><div class='del'>-		clock-frequency = &lt;13000000&gt;;</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;26000000&gt;;</div><div class='add'>+		clock-output-names = "clk26m";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	rtc_clk: dummy32k {</div><div class='add'>+	clk32k: oscillator-32k {</div><div class='ctx'> 		compatible = "fixed-clock";</div><div class='del'>-		clock-frequency = &lt;32000&gt;;</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;32000&gt;;</div><div class='add'>+		clock-output-names = "clk32k";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	uart_clk: dummy26m {</div><div class='add'>+	system_clk: dummy13m {</div><div class='ctx'> 		compatible = "fixed-clock";</div><div class='del'>-		clock-frequency = &lt;26000000&gt;;</div><div class='add'>+		clock-frequency = &lt;13000000&gt;;</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	pmu {</div><div class='add'>+		compatible = "arm,cortex-a53-pmu";</div><div class='add'>+		interrupts = &lt;GIC_SPI  8 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_SPI  9 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_SPI 10 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_SPI 11 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupt-affinity = &lt;&amp;cpu0&gt;, &lt;&amp;cpu1&gt;, &lt;&amp;cpu2&gt;, &lt;&amp;cpu3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	timer {</div><div class='ctx'> 		compatible = "arm,armv8-timer";</div><div class='ctx'> 		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='hunk'>@@ -117,59 +260,746 @@</div><div class='ctx'> 			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sysirq: intpol-controller@10200620 {</div><div class='del'>-		compatible = "mediatek,mt6795-sysirq",</div><div class='del'>-			     "mediatek,mt6577-sysirq";</div><div class='del'>-		interrupt-controller;</div><div class='del'>-		#interrupt-cells = &lt;3&gt;;</div><div class='del'>-		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='del'>-		reg = &lt;0 0x10200620 0 0x20&gt;;</div><div class='del'>-	};</div><div class='add'>+	soc {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		ranges;</div><div class='ctx'> </div><div class='del'>-	gic: interrupt-controller@10221000 {</div><div class='del'>-		compatible = "arm,gic-400";</div><div class='del'>-		#interrupt-cells = &lt;3&gt;;</div><div class='del'>-		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='del'>-		interrupt-controller;</div><div class='del'>-		reg = &lt;0 0x10221000 0 0x1000&gt;,</div><div class='del'>-		      &lt;0 0x10222000 0 0x2000&gt;,</div><div class='del'>-		      &lt;0 0x10224000 0 0x2000&gt;,</div><div class='del'>-		      &lt;0 0x10226000 0 0x2000&gt;;</div><div class='del'>-	};</div><div class='add'>+		topckgen: syscon@10000000 {</div><div class='add'>+			compatible = "mediatek,mt6795-topckgen", "syscon";</div><div class='add'>+			reg = &lt;0 0x10000000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='ctx'> </div><div class='del'>-	uart0: serial@11002000 {</div><div class='del'>-		compatible = "mediatek,mt6795-uart",</div><div class='del'>-			     "mediatek,mt6577-uart";</div><div class='del'>-		reg = &lt;0 0x11002000 0 0x400&gt;;</div><div class='del'>-		interrupts = &lt;GIC_SPI 91 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='del'>-		clocks = &lt;&amp;uart_clk&gt;;</div><div class='del'>-		status = "disabled";</div><div class='del'>-	};</div><div class='add'>+		infracfg: syscon@10001000 {</div><div class='add'>+			compatible = "mediatek,mt6795-infracfg", "syscon";</div><div class='add'>+			reg = &lt;0 0x10001000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='ctx'> </div><div class='del'>-	uart1: serial@11003000 {</div><div class='del'>-		compatible = "mediatek,mt6795-uart",</div><div class='del'>-			     "mediatek,mt6577-uart";</div><div class='del'>-		reg = &lt;0 0x11003000 0 0x400&gt;;</div><div class='del'>-		interrupts = &lt;GIC_SPI 92 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='del'>-		clocks = &lt;&amp;uart_clk&gt;;</div><div class='del'>-		status = "disabled";</div><div class='del'>-	};</div><div class='add'>+		pericfg: syscon@10003000 {</div><div class='add'>+			compatible = "mediatek,mt6795-pericfg", "syscon";</div><div class='add'>+			reg = &lt;0 0x10003000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='ctx'> </div><div class='del'>-	uart2: serial@11004000 {</div><div class='del'>-		compatible = "mediatek,mt6795-uart",</div><div class='del'>-			     "mediatek,mt6577-uart";</div><div class='del'>-		reg = &lt;0 0x11004000 0 0x400&gt;;</div><div class='del'>-		interrupts = &lt;GIC_SPI 93 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='del'>-		clocks = &lt;&amp;uart_clk&gt;;</div><div class='del'>-		status = "disabled";</div><div class='del'>-	};</div><div class='add'>+		scpsys: syscon@10006000 {</div><div class='add'>+			compatible = "syscon", "simple-mfd";</div><div class='add'>+			reg = &lt;0 0x10006000 0 0x1000&gt;;</div><div class='add'>+			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			/* System Power Manager */</div><div class='add'>+			spm: power-controller {</div><div class='add'>+				compatible = "mediatek,mt6795-power-controller";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				/* power domains of the SoC */</div><div class='add'>+				power-domain@MT6795_POWER_DOMAIN_VDEC {</div><div class='add'>+					reg = &lt;MT6795_POWER_DOMAIN_VDEC&gt;;</div><div class='add'>+					clocks = &lt;&amp;topckgen CLK_TOP_MM_SEL&gt;;</div><div class='add'>+					clock-names = "mm";</div><div class='add'>+					#power-domain-cells = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+				power-domain@MT6795_POWER_DOMAIN_VENC {</div><div class='add'>+					reg = &lt;MT6795_POWER_DOMAIN_VENC&gt;;</div><div class='add'>+					clocks = &lt;&amp;topckgen CLK_TOP_MM_SEL&gt;,</div><div class='add'>+						 &lt;&amp;topckgen CLK_TOP_VENC_SEL&gt;;</div><div class='add'>+					clock-names = "mm", "venc";</div><div class='add'>+					#power-domain-cells = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+				power-domain@MT6795_POWER_DOMAIN_ISP {</div><div class='add'>+					reg = &lt;MT6795_POWER_DOMAIN_ISP&gt;;</div><div class='add'>+					clocks = &lt;&amp;topckgen CLK_TOP_MM_SEL&gt;;</div><div class='add'>+					clock-names = "mm";</div><div class='add'>+					#power-domain-cells = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				power-domain@MT6795_POWER_DOMAIN_MM {</div><div class='add'>+					reg = &lt;MT6795_POWER_DOMAIN_MM&gt;;</div><div class='add'>+					clocks = &lt;&amp;topckgen CLK_TOP_MM_SEL&gt;;</div><div class='add'>+					clock-names = "mm";</div><div class='add'>+					#power-domain-cells = &lt;0&gt;;</div><div class='add'>+					mediatek,infracfg = &lt;&amp;infracfg&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				power-domain@MT6795_POWER_DOMAIN_MJC {</div><div class='add'>+					reg = &lt;MT6795_POWER_DOMAIN_MJC&gt;;</div><div class='add'>+					clocks = &lt;&amp;topckgen CLK_TOP_MM_SEL&gt;,</div><div class='add'>+						 &lt;&amp;topckgen CLK_TOP_MJC_SEL&gt;;</div><div class='add'>+					clock-names = "mm", "mjc";</div><div class='add'>+					#power-domain-cells = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				power-domain@MT6795_POWER_DOMAIN_AUDIO {</div><div class='add'>+					reg = &lt;MT6795_POWER_DOMAIN_AUDIO&gt;;</div><div class='add'>+					#power-domain-cells = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				mfg_async: power-domain@MT6795_POWER_DOMAIN_MFG_ASYNC {</div><div class='add'>+					reg = &lt;MT6795_POWER_DOMAIN_MFG_ASYNC&gt;;</div><div class='add'>+					clocks = &lt;&amp;clk26m&gt;;</div><div class='add'>+					clock-names = "mfg";</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+					#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					power-domain@MT6795_POWER_DOMAIN_MFG_2D {</div><div class='add'>+						reg = &lt;MT6795_POWER_DOMAIN_MFG_2D&gt;;</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+						#power-domain-cells = &lt;1&gt;;</div><div class='ctx'> </div><div class='del'>-	uart3: serial@11005000 {</div><div class='del'>-		compatible = "mediatek,mt6795-uart",</div><div class='del'>-			     "mediatek,mt6577-uart";</div><div class='del'>-		reg = &lt;0 0x11005000 0 0x400&gt;;</div><div class='del'>-		interrupts = &lt;GIC_SPI 94 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='del'>-		clocks = &lt;&amp;uart_clk&gt;;</div><div class='del'>-		status = "disabled";</div><div class='add'>+						power-domain@MT6795_POWER_DOMAIN_MFG {</div><div class='add'>+							reg = &lt;MT6795_POWER_DOMAIN_MFG&gt;;</div><div class='add'>+							#power-domain-cells = &lt;0&gt;;</div><div class='add'>+							mediatek,infracfg = &lt;&amp;infracfg&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pio: pinctrl@10005000 {</div><div class='add'>+			compatible = "mediatek,mt6795-pinctrl";</div><div class='add'>+			reg = &lt;0 0x10005000 0 0x1000&gt;, &lt;0 0x1000b000 0 0x1000&gt;;</div><div class='add'>+			reg-names = "base", "eint";</div><div class='add'>+			interrupts = &lt;GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;pio 0 0 196&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		watchdog: watchdog@10007000 {</div><div class='add'>+			compatible = "mediatek,mt6795-wdt";</div><div class='add'>+			reg = &lt;0 0x10007000 0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 128 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+			timeout-sec = &lt;20&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		timer: timer@10008000 {</div><div class='add'>+			compatible = "mediatek,mt6795-timer",</div><div class='add'>+				     "mediatek,mt6577-timer";</div><div class='add'>+			reg = &lt;0 0x10008000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 152 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			clocks = &lt;&amp;system_clk&gt;, &lt;&amp;clk32k&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pwrap: pwrap@1000d000 {</div><div class='add'>+			compatible = "mediatek,mt6795-pwrap";</div><div class='add'>+			reg = &lt;0 0x1000d000 0 0x1000&gt;;</div><div class='add'>+			reg-names = "pwrap";</div><div class='add'>+			interrupts = &lt;GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			resets = &lt;&amp;infracfg MT6795_INFRA_RST0_PMIC_WRAP_RST&gt;;</div><div class='add'>+			reset-names = "pwrap";</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_PMICSPI_SEL&gt;, &lt;&amp;clk26m&gt;;</div><div class='add'>+			clock-names = "spi", "wrap";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sysirq: interrupt-controller@10200620 {</div><div class='add'>+			compatible = "mediatek,mt6795-sysirq",</div><div class='add'>+				     "mediatek,mt6577-sysirq";</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+			reg = &lt;0 0x10200620 0 0x20&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		systimer: timer@10200670 {</div><div class='add'>+			compatible = "mediatek,mt6795-systimer";</div><div class='add'>+			reg = &lt;0 0x10200670 0 0x10&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;system_clk&gt;;</div><div class='add'>+			clock-names = "clk13m";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		iommu: iommu@10205000 {</div><div class='add'>+			compatible = "mediatek,mt6795-m4u";</div><div class='add'>+			reg = &lt;0 0x10205000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_M4U&gt;;</div><div class='add'>+			clock-names = "bclk";</div><div class='add'>+			interrupts = &lt;GIC_SPI 146 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			mediatek,infracfg = &lt;&amp;infracfg&gt;;</div><div class='add'>+			mediatek,larbs = &lt;&amp;larb0 &amp;larb1 &amp;larb2 &amp;larb3&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT6795_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			#iommu-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		apmixedsys: syscon@10209000 {</div><div class='add'>+			compatible = "mediatek,mt6795-apmixedsys", "syscon";</div><div class='add'>+			reg = &lt;0 0x10209000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		fhctl: clock-controller@10209f00 {</div><div class='add'>+			compatible = "mediatek,mt6795-fhctl";</div><div class='add'>+			reg = &lt;0 0x10209f00 0 0x100&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gce: mailbox@10212000 {</div><div class='add'>+			compatible = "mediatek,mt6795-gce", "mediatek,mt8173-gce";</div><div class='add'>+			reg = &lt;0 0x10212000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 143 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_GCE&gt;;</div><div class='add'>+			clock-names = "gce";</div><div class='add'>+			#mbox-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mipi_tx0: dsi-phy@10215000 {</div><div class='add'>+			compatible = "mediatek,mt8173-mipi-tx";</div><div class='add'>+			reg = &lt;0 0x10215000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk26m&gt;;</div><div class='add'>+			clock-output-names = "mipi_tx0_pll";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mipi_tx1: dsi-phy@10216000 {</div><div class='add'>+			compatible = "mediatek,mt8173-mipi-tx";</div><div class='add'>+			reg = &lt;0 0x10216000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk26m&gt;;</div><div class='add'>+			clock-output-names = "mipi_tx1_pll";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@10221000 {</div><div class='add'>+			compatible = "arm,gic-400";</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			reg = &lt;0 0x10221000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x10222000 0 0x2000&gt;,</div><div class='add'>+			      &lt;0 0x10224000 0 0x2000&gt;,</div><div class='add'>+			      &lt;0 0x10226000 0 0x2000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9</div><div class='add'>+				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cci: cci@10390000 {</div><div class='add'>+			compatible = "arm,cci-400";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			reg = &lt;0 0x10390000 0 0x1000&gt;;</div><div class='add'>+			ranges = &lt;0 0 0x10390000 0x10000&gt;;</div><div class='add'>+</div><div class='add'>+			cci_control0: slave-if@1000 {</div><div class='add'>+				compatible = "arm,cci-400-ctrl-if";</div><div class='add'>+				interface-type = "ace-lite";</div><div class='add'>+				reg = &lt;0x1000 0x1000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cci_control1: slave-if@4000 {</div><div class='add'>+				compatible = "arm,cci-400-ctrl-if";</div><div class='add'>+				interface-type = "ace";</div><div class='add'>+				reg = &lt;0x4000 0x1000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cci_control2: slave-if@5000 {</div><div class='add'>+				compatible = "arm,cci-400-ctrl-if";</div><div class='add'>+				interface-type = "ace";</div><div class='add'>+				reg = &lt;0x5000 0x1000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pmu@9000 {</div><div class='add'>+				compatible = "arm,cci-400-pmu,r1";</div><div class='add'>+				reg = &lt;0x9000 0x5000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart0: serial@11002000 {</div><div class='add'>+			compatible = "mediatek,mt6795-uart",</div><div class='add'>+				     "mediatek,mt6577-uart";</div><div class='add'>+			reg = &lt;0 0x11002000 0 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 91 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			clocks = &lt;&amp;pericfg CLK_PERI_UART0_SEL&gt;, &lt;&amp;pericfg CLK_PERI_UART0&gt;;</div><div class='add'>+			clock-names = "baud", "bus";</div><div class='add'>+			dmas = &lt;&amp;apdma 0&gt;, &lt;&amp;apdma 1&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart1: serial@11003000 {</div><div class='add'>+			compatible = "mediatek,mt6795-uart",</div><div class='add'>+				     "mediatek,mt6577-uart";</div><div class='add'>+			reg = &lt;0 0x11003000 0 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 92 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			clocks = &lt;&amp;pericfg CLK_PERI_UART1_SEL&gt;, &lt;&amp;pericfg CLK_PERI_UART1&gt;;</div><div class='add'>+			clock-names = "baud", "bus";</div><div class='add'>+			dmas = &lt;&amp;apdma 2&gt;, &lt;&amp;apdma 3&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		apdma: dma-controller@11000380 {</div><div class='add'>+			compatible = "mediatek,mt6795-uart-dma",</div><div class='add'>+				     "mediatek,mt6577-uart-dma";</div><div class='add'>+			reg = &lt;0 0x11000380 0 0x60&gt;,</div><div class='add'>+			      &lt;0 0x11000400 0 0x60&gt;,</div><div class='add'>+			      &lt;0 0x11000480 0 0x60&gt;,</div><div class='add'>+			      &lt;0 0x11000500 0 0x60&gt;,</div><div class='add'>+			      &lt;0 0x11000580 0 0x60&gt;,</div><div class='add'>+			      &lt;0 0x11000600 0 0x60&gt;,</div><div class='add'>+			      &lt;0 0x11000680 0 0x60&gt;,</div><div class='add'>+			      &lt;0 0x11000700 0 0x60&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 103 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+				     &lt;GIC_SPI 104 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+				     &lt;GIC_SPI 105 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+				     &lt;GIC_SPI 106 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+				     &lt;GIC_SPI 107 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+				     &lt;GIC_SPI 108 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+				     &lt;GIC_SPI 109 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+				     &lt;GIC_SPI 110 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			dma-requests = &lt;8&gt;;</div><div class='add'>+			clocks = &lt;&amp;pericfg CLK_PERI_AP_DMA&gt;;</div><div class='add'>+			clock-names = "apdma";</div><div class='add'>+			mediatek,dma-33bits;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart2: serial@11004000 {</div><div class='add'>+			compatible = "mediatek,mt6795-uart",</div><div class='add'>+				     "mediatek,mt6577-uart";</div><div class='add'>+			reg = &lt;0 0x11004000 0 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 93 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			clocks = &lt;&amp;pericfg CLK_PERI_UART2_SEL&gt;, &lt;&amp;pericfg CLK_PERI_UART2&gt;;</div><div class='add'>+			clock-names = "baud", "bus";</div><div class='add'>+			dmas = &lt;&amp;apdma 4&gt;, &lt;&amp;apdma 5&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart3: serial@11005000 {</div><div class='add'>+			compatible = "mediatek,mt6795-uart",</div><div class='add'>+				     "mediatek,mt6577-uart";</div><div class='add'>+			reg = &lt;0 0x11005000 0 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 94 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			clocks = &lt;&amp;pericfg CLK_PERI_UART3_SEL&gt;, &lt;&amp;pericfg CLK_PERI_UART3&gt;;</div><div class='add'>+			clock-names = "baud", "bus";</div><div class='add'>+			dmas = &lt;&amp;apdma 6&gt;, &lt;&amp;apdma 7&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pwm2: pwm@11006000 {</div><div class='add'>+			compatible = "mediatek,mt6795-pwm";</div><div class='add'>+			reg = &lt;0 0x11006000 0 0x1000&gt;;</div><div class='add'>+			#pwm-cells = &lt;2&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 77 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_PWM_SEL&gt;,</div><div class='add'>+				 &lt;&amp;pericfg CLK_PERI_PWM&gt;,</div><div class='add'>+				 &lt;&amp;pericfg CLK_PERI_PWM1&gt;,</div><div class='add'>+				 &lt;&amp;pericfg CLK_PERI_PWM2&gt;,</div><div class='add'>+				 &lt;&amp;pericfg CLK_PERI_PWM3&gt;,</div><div class='add'>+				 &lt;&amp;pericfg CLK_PERI_PWM4&gt;,</div><div class='add'>+				 &lt;&amp;pericfg CLK_PERI_PWM5&gt;,</div><div class='add'>+				 &lt;&amp;pericfg CLK_PERI_PWM6&gt;,</div><div class='add'>+				 &lt;&amp;pericfg CLK_PERI_PWM7&gt;;</div><div class='add'>+			clock-names = "top", "main", "pwm1", "pwm2", "pwm3",</div><div class='add'>+				      "pwm4", "pwm5", "pwm6", "pwm7";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c0: i2c@11007000 {</div><div class='add'>+			compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c";</div><div class='add'>+			reg = &lt;0 0x11007000 0 0x70&gt;, &lt;0 0x11000100 0 0x80&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 84 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			clock-div = &lt;16&gt;;</div><div class='add'>+			clocks = &lt;&amp;pericfg CLK_PERI_I2C0&gt;, &lt;&amp;pericfg CLK_PERI_AP_DMA&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c1: i2c@11008000 {</div><div class='add'>+			compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c";</div><div class='add'>+			reg = &lt;0 0x11008000 0 0x70&gt;, &lt;0 0x11000180 0 0x80&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 85 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			clock-div = &lt;16&gt;;</div><div class='add'>+			clocks = &lt;&amp;pericfg CLK_PERI_I2C1&gt;, &lt;&amp;pericfg CLK_PERI_AP_DMA&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c2: i2c@11009000 {</div><div class='add'>+			compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c";</div><div class='add'>+			reg = &lt;0 0x11009000 0 0x70&gt;, &lt;0 0x11000200 0 0x80&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 86 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			clock-div = &lt;16&gt;;</div><div class='add'>+			clocks = &lt;&amp;pericfg CLK_PERI_I2C2&gt;, &lt;&amp;pericfg CLK_PERI_AP_DMA&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c3: i2c@11010000 {</div><div class='add'>+			compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c";</div><div class='add'>+			reg = &lt;0 0x11010000 0 0x70&gt;, &lt;0 0x11000280 0 0x80&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 87 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			clock-div = &lt;16&gt;;</div><div class='add'>+			clocks = &lt;&amp;pericfg CLK_PERI_I2C3&gt;, &lt;&amp;pericfg CLK_PERI_AP_DMA&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c4: i2c@11011000 {</div><div class='add'>+			compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c";</div><div class='add'>+			reg = &lt;0 0x11011000 0 0x70&gt;, &lt;0 0x11000300 0 0x80&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 88 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			clock-div = &lt;16&gt;;</div><div class='add'>+			clocks = &lt;&amp;pericfg CLK_PERI_I2C4&gt;, &lt;&amp;pericfg CLK_PERI_AP_DMA&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmc0: mmc@11230000 {</div><div class='add'>+			compatible = "mediatek,mt6795-mmc";</div><div class='add'>+			reg = &lt;0 0x11230000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 79 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			clocks = &lt;&amp;pericfg CLK_PERI_MSDC30_0&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_MSDC50_0_H_SEL&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_MSDC50_0_SEL&gt;;</div><div class='add'>+			clock-names = "source", "hclk", "source_cg";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmc1: mmc@11240000 {</div><div class='add'>+			compatible = "mediatek,mt6795-mmc";</div><div class='add'>+			reg = &lt;0 0x11240000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 80 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			clocks = &lt;&amp;pericfg CLK_PERI_MSDC30_1&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_AXI_SEL&gt;;</div><div class='add'>+			clock-names = "source", "hclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmc2: mmc@11250000 {</div><div class='add'>+			compatible = "mediatek,mt6795-mmc";</div><div class='add'>+			reg = &lt;0 0x11250000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 81 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			clocks = &lt;&amp;pericfg CLK_PERI_MSDC30_2&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_AXI_SEL&gt;;</div><div class='add'>+			clock-names = "source", "hclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmc3: mmc@11260000 {</div><div class='add'>+			compatible = "mediatek,mt6795-mmc";</div><div class='add'>+			reg = &lt;0 0x11260000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 82 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			clocks = &lt;&amp;pericfg CLK_PERI_MSDC30_3&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_AXI_SEL&gt;;</div><div class='add'>+			clock-names = "source", "hclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmsys: syscon@14000000 {</div><div class='add'>+			compatible = "mediatek,mt6795-mmsys", "syscon";</div><div class='add'>+			reg = &lt;0 0x14000000 0 0x1000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT6795_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			assigned-clocks = &lt;&amp;topckgen CLK_TOP_MM_SEL&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;400000000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+			mboxes = &lt;&amp;gce 0 CMDQ_THR_PRIO_HIGHEST&gt;,</div><div class='add'>+				 &lt;&amp;gce 1 CMDQ_THR_PRIO_HIGHEST&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1400XXXX 0 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ovl0: ovl@1400c000 {</div><div class='add'>+			compatible = "mediatek,mt6795-disp-ovl", "mediatek,mt8173-disp-ovl";</div><div class='add'>+			reg = &lt;0 0x1400c000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 188 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT6795_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_OVL0&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu M4U_PORT_DISP_OVL0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1400XXXX 0xc000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ovl1: ovl@1400d000 {</div><div class='add'>+			compatible = "mediatek,mt6795-disp-ovl", "mediatek,mt8173-disp-ovl";</div><div class='add'>+			reg = &lt;0 0x1400d000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 189 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT6795_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_OVL1&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu M4U_PORT_DISP_OVL1&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1400XXXX 0xd000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rdma0: rdma@1400e000 {</div><div class='add'>+			compatible = "mediatek,mt6795-disp-rdma", "mediatek,mt8173-disp-rdma";</div><div class='add'>+			reg = &lt;0 0x1400e000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 190 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT6795_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_RDMA0&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu M4U_PORT_DISP_RDMA0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1400XXXX 0xe000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rdma1: rdma@1400f000 {</div><div class='add'>+			compatible = "mediatek,mt6795-disp-rdma", "mediatek,mt8173-disp-rdma";</div><div class='add'>+			reg = &lt;0 0x1400f000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 191 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT6795_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_RDMA1&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu M4U_PORT_DISP_RDMA1&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1400XXXX 0xf000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rdma2: rdma@14010000 {</div><div class='add'>+			compatible = "mediatek,mt6795-disp-rdma", "mediatek,mt8173-disp-rdma";</div><div class='add'>+			reg = &lt;0 0x14010000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 192 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT6795_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_RDMA2&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu M4U_PORT_DISP_RDMA2&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1401XXXX 0 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wdma0: wdma@14011000 {</div><div class='add'>+			compatible = "mediatek,mt6795-disp-wdma", "mediatek,mt8173-disp-wdma";</div><div class='add'>+			reg = &lt;0 0x14011000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 193 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT6795_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_WDMA0&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu M4U_PORT_DISP_WDMA0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1401XXXX 0x1000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wdma1: wdma@14012000 {</div><div class='add'>+			compatible = "mediatek,mt6795-disp-wdma", "mediatek,mt8173-disp-wdma";</div><div class='add'>+			reg = &lt;0 0x14012000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 194 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT6795_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_WDMA1&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu M4U_PORT_DISP_WDMA1&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1401XXXX 0x2000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		color0: color@14013000 {</div><div class='add'>+			compatible = "mediatek,mt6795-disp-color", "mediatek,mt8173-disp-color";</div><div class='add'>+			reg = &lt;0 0x14013000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 195 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT6795_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_COLOR0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1401XXXX 0x3000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		color1: color@14014000 {</div><div class='add'>+			compatible = "mediatek,mt6795-disp-color", "mediatek,mt8173-disp-color";</div><div class='add'>+			reg = &lt;0 0x14014000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 196 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT6795_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_COLOR1&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1401XXXX 0x4000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aal@14015000 {</div><div class='add'>+			compatible = "mediatek,mt6795-disp-aal", "mediatek,mt8173-disp-aal";</div><div class='add'>+			reg = &lt;0 0x14015000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 197 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT6795_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_AAL&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1401XXXX 0x5000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gamma@14016000 {</div><div class='add'>+			compatible = "mediatek,mt6795-disp-gamma", "mediatek,mt8173-disp-gamma";</div><div class='add'>+			reg = &lt;0 0x14016000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 198 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT6795_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_GAMMA&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1401XXXX 0x6000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		merge@14017000 {</div><div class='add'>+			compatible = "mediatek,mt6795-disp-merge", "mediatek,mt8173-disp-merge";</div><div class='add'>+			reg = &lt;0 0x14017000 0 0x1000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT6795_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_MERGE&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		split0: split@14018000 {</div><div class='add'>+			compatible = "mediatek,mt6795-disp-split", "mediatek,mt8173-disp-split";</div><div class='add'>+			reg = &lt;0 0x14018000 0 0x1000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT6795_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_SPLIT0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		split1: split@14019000 {</div><div class='add'>+			compatible = "mediatek,mt6795-disp-split", "mediatek,mt8173-disp-split";</div><div class='add'>+			reg = &lt;0 0x14019000 0 0x1000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT6795_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_SPLIT1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ufoe@1401a000 {</div><div class='add'>+			compatible = "mediatek,mt6795-disp-ufoe", "mediatek,mt8173-disp-ufoe";</div><div class='add'>+			reg = &lt;0 0x1401a000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 199 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT6795_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_UFOE&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1401XXXX 0xa000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dsi0: dsi@1401b000 {</div><div class='add'>+			compatible = "mediatek,mt6795-dsi", "mediatek,mt8173-dsi";</div><div class='add'>+			reg = &lt;0 0x1401b000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 200 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT6795_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DSI0_ENGINE&gt;,</div><div class='add'>+				 &lt;&amp;mmsys CLK_MM_DSI0_DIGITAL&gt;,</div><div class='add'>+				 &lt;&amp;mipi_tx0&gt;;</div><div class='add'>+			clock-names = "engine", "digital", "hs";</div><div class='add'>+			phys = &lt;&amp;mipi_tx0&gt;;</div><div class='add'>+			phy-names = "dphy";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dsi1: dsi@1401c000 {</div><div class='add'>+			compatible = "mediatek,mt6795-dsi", "mediatek,mt8173-dsi";</div><div class='add'>+			reg = &lt;0 0x1401c000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 201 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT6795_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DSI1_ENGINE&gt;,</div><div class='add'>+				 &lt;&amp;mmsys CLK_MM_DSI1_DIGITAL&gt;,</div><div class='add'>+				 &lt;&amp;mipi_tx1&gt;;</div><div class='add'>+			clock-names = "engine", "digital", "hs";</div><div class='add'>+			phys = &lt;&amp;mipi_tx1&gt;;</div><div class='add'>+			phy-names = "dphy";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dpi0: dpi@1401d000 {</div><div class='add'>+			compatible = "mediatek,mt6795-dpi", "mediatek,mt8183-dpi";</div><div class='add'>+			reg = &lt;0 0x1401d000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 202 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT6795_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DPI_PIXEL&gt;,</div><div class='add'>+				 &lt;&amp;mmsys CLK_MM_DPI_ENGINE&gt;,</div><div class='add'>+				 &lt;&amp;apmixedsys CLK_APMIXED_TVDPLL&gt;;</div><div class='add'>+			clock-names = "pixel", "engine", "pll";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pwm0: pwm@1401e000 {</div><div class='add'>+			compatible = "mediatek,mt6795-disp-pwm", "mediatek,mt8173-disp-pwm";</div><div class='add'>+			reg = &lt;0 0x1401e000 0 0x1000&gt;;</div><div class='add'>+			#pwm-cells = &lt;2&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_PWM026M&gt;, &lt;&amp;mmsys CLK_MM_DISP_PWM0MM&gt;;</div><div class='add'>+			clock-names = "main", "mm";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pwm1: pwm@1401f000 {</div><div class='add'>+			compatible = "mediatek,mt6795-disp-pwm", "mediatek,mt8173-disp-pwm";</div><div class='add'>+			reg = &lt;0 0x1401f000 0 0x1000&gt;;</div><div class='add'>+			#pwm-cells = &lt;2&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_PWM126M&gt;, &lt;&amp;mmsys CLK_MM_DISP_PWM1MM&gt;;</div><div class='add'>+			clock-names = "main", "mm";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mutex: mutex@14020000 {</div><div class='add'>+			compatible = "mediatek,mt8173-disp-mutex";</div><div class='add'>+			reg = &lt;0 0x14020000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 177 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT6795_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_MUTEX_32K&gt;;</div><div class='add'>+			mediatek,gce-events = &lt;CMDQ_EVENT_MUTEX0_STREAM_EOF&gt;,</div><div class='add'>+					      &lt;CMDQ_EVENT_MUTEX1_STREAM_EOF&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1402XXXX 0 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb0: larb@14021000 {</div><div class='add'>+			compatible = "mediatek,mt6795-smi-larb";</div><div class='add'>+			reg = &lt;0 0x14021000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_SMI_COMMON&gt;, &lt;&amp;mmsys CLK_MM_SMI_LARB0&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT6795_POWER_DOMAIN_MM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smi_common: smi@14022000 {</div><div class='add'>+			compatible = "mediatek,mt6795-smi-common";</div><div class='add'>+			reg = &lt;0 0x14022000 0 0x1000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT6795_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_SMI&gt;, &lt;&amp;mmsys CLK_MM_SMI_COMMON&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		od@14023000 {</div><div class='add'>+			compatible = "mediatek,mt6795-disp-od", "mediatek,mt8173-disp-od";</div><div class='add'>+			reg = &lt;0 0x14023000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_OD&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1402XXXX 0x3000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb2: larb@15001000 {</div><div class='add'>+			compatible = "mediatek,mt6795-smi-larb";</div><div class='add'>+			reg = &lt;0 0x15001000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_SMI_COMMON&gt;, &lt;&amp;infracfg CLK_INFRA_SMI&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;2&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT6795_POWER_DOMAIN_ISP&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdecsys: clock-controller@16000000 {</div><div class='add'>+			compatible = "mediatek,mt6795-vdecsys";</div><div class='add'>+			reg = &lt;0 0x16000000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb1: larb@16010000 {</div><div class='add'>+			compatible = "mediatek,mt6795-smi-larb";</div><div class='add'>+			reg = &lt;0 0x16010000 0 0x1000&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdecsys CLK_VDEC_CKEN&gt;, &lt;&amp;vdecsys CLK_VDEC_LARB_CKEN&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT6795_POWER_DOMAIN_VDEC&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vencsys: clock-controller@18000000 {</div><div class='add'>+			compatible = "mediatek,mt6795-vencsys";</div><div class='add'>+			reg = &lt;0 0x18000000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb3: larb@18001000 {</div><div class='add'>+			compatible = "mediatek,mt6795-smi-larb";</div><div class='add'>+			reg = &lt;0 0x18001000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vencsys CLK_VENC_VENC&gt;, &lt;&amp;vencsys CLK_VENC_LARB&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;3&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT6795_POWER_DOMAIN_VENC&gt;;</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt6797-evb.dts b/arch/arm64/boot/dts/mediatek/mt6797-evb.dts<br/>index 2327e752d164..c927932afa0d 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt6797-evb.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt6797-evb.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt6797-evb.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt6797-evb.dts</a></div><div class='hunk'>@@ -9,6 +9,7 @@</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	model = "MediaTek MT6797 Evaluation Board";</div><div class='add'>+	chassis-type = "embedded";</div><div class='ctx'> 	compatible = "mediatek,mt6797-evb", "mediatek,mt6797";</div><div class='ctx'> </div><div class='ctx'> 	aliases {</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts b/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts<br/>index 13939d55b85b..9534cf3a09d0 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts</a></div><div class='hunk'>@@ -12,6 +12,7 @@</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	model = "Mediatek X20 Development Board";</div><div class='add'>+	chassis-type = "embedded";</div><div class='ctx'> 	compatible = "archermind,mt6797-x20-dev", "mediatek,mt6797";</div><div class='ctx'> </div><div class='ctx'> 	aliases {</div><div class='hunk'>@@ -28,6 +29,55 @@</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+/* HDMI */</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c1_pins_a&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* HS - I2C2 */</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c2_pins_a&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* HS - I2C3 */</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c3_pins_a&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* LS - I2C0 */</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c4_pins_a&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* LS - I2C1 */</div><div class='add'>+&amp;i2c5 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c5_pins_a&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* POWER_VPROC */</div><div class='add'>+&amp;i2c6 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c6_pins_a&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* FAN53555 */</div><div class='add'>+&amp;i2c7 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c7_pins_a&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;uart1 {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt6797.dtsi b/arch/arm64/boot/dts/mediatek/mt6797.dtsi<br/>index 136ef9527a0d..8ac98a378fd6 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt6797.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt6797.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt6797.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt6797.dtsi</a></div><div class='hunk'>@@ -1,14 +1,7 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2017 MediaTek Inc.</div><div class='ctx'>  * Author: Mars.C &lt;mars.cheng@mediatek.com&gt;</div><div class='del'>- *</div><div class='del'>- * This program is free software; you can redistribute it and/or modify</div><div class='del'>- * it under the terms of the GNU General Public License version 2 as</div><div class='del'>- * published by the Free Software Foundation.</div><div class='del'>- *</div><div class='del'>- * This program is distributed in the hope that it will be useful,</div><div class='del'>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the</div><div class='del'>- * GNU General Public License for more details.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;dt-bindings/clock/mt6797-clk.h&gt;</div><div class='hunk'>@@ -102,7 +95,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	clk26m: oscillator@0 {</div><div class='add'>+	clk26m: oscillator-26m {</div><div class='ctx'> 		compatible = "fixed-clock";</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='ctx'> 		clock-frequency = &lt;26000000&gt;;</div><div class='hunk'>@@ -124,7 +117,7 @@</div><div class='ctx'> 		#clock-cells = &lt;1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	infrasys: infracfg_ao@10001000 {</div><div class='add'>+	infrasys: syscon@10001000 {</div><div class='ctx'> 		compatible = "mediatek,mt6797-infracfg", "syscon";</div><div class='ctx'> 		reg = &lt;0 0x10001000 0 0x1000&gt;;</div><div class='ctx'> 		#clock-cells = &lt;1&gt;;</div><div class='hunk'>@@ -142,19 +135,75 @@</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='del'>-		uart0_pins_a: uart0 {</div><div class='del'>-			pins0 {</div><div class='add'>+		uart0_pins_a: uart0-pins {</div><div class='add'>+			pins-bus {</div><div class='ctx'> 				pinmux = &lt;MT6797_GPIO234__FUNC_UTXD0&gt;,</div><div class='ctx'> 					 &lt;MT6797_GPIO235__FUNC_URXD0&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		uart1_pins_a: uart1 {</div><div class='del'>-			pins1 {</div><div class='add'>+		uart1_pins_a: uart1-pins {</div><div class='add'>+			pins-bus {</div><div class='ctx'> 				pinmux = &lt;MT6797_GPIO232__FUNC_URXD1&gt;,</div><div class='ctx'> 					 &lt;MT6797_GPIO233__FUNC_UTXD1&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='add'>+</div><div class='add'>+		i2c0_pins_a: i2c0-pins {</div><div class='add'>+			pins-bus {</div><div class='add'>+				pinmux = &lt;MT6797_GPIO37__FUNC_SCL0_0&gt;,</div><div class='add'>+					 &lt;MT6797_GPIO38__FUNC_SDA0_0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c1_pins_a: i2c1-pins {</div><div class='add'>+			pins-bus {</div><div class='add'>+				pinmux = &lt;MT6797_GPIO55__FUNC_SCL1_0&gt;,</div><div class='add'>+					 &lt;MT6797_GPIO56__FUNC_SDA1_0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c2_pins_a: i2c2-pins {</div><div class='add'>+			pins-bus {</div><div class='add'>+				pinmux = &lt;MT6797_GPIO96__FUNC_SCL2_0&gt;,</div><div class='add'>+					 &lt;MT6797_GPIO95__FUNC_SDA2_0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c3_pins_a: i2c3-pins {</div><div class='add'>+			pins-bus {</div><div class='add'>+				pinmux = &lt;MT6797_GPIO75__FUNC_SDA3_0&gt;,</div><div class='add'>+					 &lt;MT6797_GPIO74__FUNC_SCL3_0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c4_pins_a: i2c4-pins {</div><div class='add'>+			pins-bus {</div><div class='add'>+				pinmux = &lt;MT6797_GPIO238__FUNC_SDA4_0&gt;,</div><div class='add'>+					 &lt;MT6797_GPIO239__FUNC_SCL4_0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c5_pins_a: i2c5-pins {</div><div class='add'>+			pins-bus {</div><div class='add'>+				pinmux = &lt;MT6797_GPIO240__FUNC_SDA5_0&gt;,</div><div class='add'>+					 &lt;MT6797_GPIO241__FUNC_SCL5_0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c6_pins_a: i2c6-pins {</div><div class='add'>+			pins-bus {</div><div class='add'>+				pinmux = &lt;MT6797_GPIO152__FUNC_SDA6_0&gt;,</div><div class='add'>+					 &lt;MT6797_GPIO151__FUNC_SCL6_0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c7_pins_a: i2c7-pins {</div><div class='add'>+			pins-bus {</div><div class='add'>+				pinmux = &lt;MT6797_GPIO154__FUNC_SDA7_0&gt;,</div><div class='add'>+					 &lt;MT6797_GPIO153__FUNC_SCL7_0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	scpsys: power-controller@10006000 {</div><div class='hunk'>@@ -179,7 +228,7 @@</div><div class='ctx'> 		#clock-cells = &lt;1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sysirq: intpol-controller@10200620 {</div><div class='add'>+	sysirq: interrupt-controller@10200620 {</div><div class='ctx'> 		compatible = "mediatek,mt6797-sysirq",</div><div class='ctx'> 			     "mediatek,mt6577-sysirq";</div><div class='ctx'> 		interrupt-controller;</div><div class='hunk'>@@ -233,25 +282,179 @@</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	mmsys: mmsys_config@14000000 {</div><div class='add'>+	i2c0: i2c@11007000 {</div><div class='add'>+		compatible = "mediatek,mt6797-i2c",</div><div class='add'>+			     "mediatek,mt6577-i2c";</div><div class='add'>+		reg = &lt;0 0x11007000 0 0x1000&gt;,</div><div class='add'>+		      &lt;0 0x11000100 0 0x80&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 84 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		clocks = &lt;&amp;infrasys CLK_INFRA_I2C0&gt;,</div><div class='add'>+			 &lt;&amp;infrasys CLK_INFRA_AP_DMA&gt;;</div><div class='add'>+		clock-names = "main", "dma";</div><div class='add'>+		clock-div = &lt;10&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c1: i2c@11008000 {</div><div class='add'>+		compatible = "mediatek,mt6797-i2c",</div><div class='add'>+			     "mediatek,mt6577-i2c";</div><div class='add'>+		reg = &lt;0 0x11008000 0 0x1000&gt;,</div><div class='add'>+		      &lt;0 0x11000180 0 0x80&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 85 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		clocks = &lt;&amp;infrasys CLK_INFRA_I2C1&gt;,</div><div class='add'>+			 &lt;&amp;infrasys CLK_INFRA_AP_DMA&gt;;</div><div class='add'>+		clock-names = "main", "dma";</div><div class='add'>+		clock-div = &lt;10&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c8: i2c@11009000 {</div><div class='add'>+		compatible = "mediatek,mt6797-i2c",</div><div class='add'>+			     "mediatek,mt6577-i2c";</div><div class='add'>+		reg = &lt;0 0x11009000 0 0x1000&gt;,</div><div class='add'>+		      &lt;0 0x11000200 0 0x80&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 86 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		clocks = &lt;&amp;infrasys CLK_INFRA_I2C2&gt;,</div><div class='add'>+			 &lt;&amp;infrasys CLK_INFRA_AP_DMA&gt;,</div><div class='add'>+			 &lt;&amp;infrasys CLK_INFRA_I2C2_ARB&gt;;</div><div class='add'>+		clock-names = "main", "dma", "arb";</div><div class='add'>+		clock-div = &lt;10&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c9: i2c@1100d000 {</div><div class='add'>+		compatible = "mediatek,mt6797-i2c",</div><div class='add'>+			     "mediatek,mt6577-i2c";</div><div class='add'>+		reg = &lt;0 0x1100d000 0 0x1000&gt;,</div><div class='add'>+		      &lt;0 0x11000280 0 0x80&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 87 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		clocks = &lt;&amp;infrasys CLK_INFRA_I2C3&gt;,</div><div class='add'>+			 &lt;&amp;infrasys CLK_INFRA_AP_DMA&gt;,</div><div class='add'>+			 &lt;&amp;infrasys CLK_INFRA_I2C3_ARB&gt;;</div><div class='add'>+		clock-names = "main", "dma", "arb";</div><div class='add'>+		clock-div = &lt;10&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c6: i2c@1100e000 {</div><div class='add'>+		compatible = "mediatek,mt6797-i2c",</div><div class='add'>+			     "mediatek,mt6577-i2c";</div><div class='add'>+		reg = &lt;0 0x1100e000 0 0x1000&gt;,</div><div class='add'>+		      &lt;0 0x11000500 0 0x80&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 88 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		clocks = &lt;&amp;infrasys CLK_INFRA_I2C_APPM&gt;,</div><div class='add'>+			 &lt;&amp;infrasys CLK_INFRA_AP_DMA&gt;;</div><div class='add'>+		clock-names = "main", "dma";</div><div class='add'>+		clock-div = &lt;10&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c7: i2c@11010000 {</div><div class='add'>+		compatible = "mediatek,mt6797-i2c",</div><div class='add'>+			     "mediatek,mt6577-i2c";</div><div class='add'>+		reg = &lt;0 0x11010000 0 0x1000&gt;,</div><div class='add'>+		      &lt;0 0x11000580 0 0x80&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 89 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		clocks = &lt;&amp;infrasys CLK_INFRA_I2C_GPUPM&gt;,</div><div class='add'>+			 &lt;&amp;infrasys CLK_INFRA_AP_DMA&gt;;</div><div class='add'>+		clock-names = "main", "dma";</div><div class='add'>+		clock-div = &lt;10&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c4: i2c@11011000 {</div><div class='add'>+		compatible = "mediatek,mt6797-i2c",</div><div class='add'>+			     "mediatek,mt6577-i2c";</div><div class='add'>+		reg = &lt;0 0x11011000 0 0x1000&gt;,</div><div class='add'>+		      &lt;0 0x11000300 0 0x80&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 90 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		clocks = &lt;&amp;infrasys CLK_INFRA_I2C4&gt;,</div><div class='add'>+			 &lt;&amp;infrasys CLK_INFRA_AP_DMA&gt;;</div><div class='add'>+		clock-names = "main", "dma";</div><div class='add'>+		clock-div = &lt;10&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c2: i2c@11013000 {</div><div class='add'>+		compatible = "mediatek,mt6797-i2c",</div><div class='add'>+			     "mediatek,mt6577-i2c";</div><div class='add'>+		reg = &lt;0 0x11013000 0 0x1000&gt;,</div><div class='add'>+		      &lt;0 0x11000400 0 0x80&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 95 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		clocks = &lt;&amp;infrasys CLK_INFRA_I2C2_IMM&gt;,</div><div class='add'>+			 &lt;&amp;infrasys CLK_INFRA_AP_DMA&gt;,</div><div class='add'>+			 &lt;&amp;infrasys CLK_INFRA_I2C2_ARB&gt;;</div><div class='add'>+		clock-names = "main", "dma", "arb";</div><div class='add'>+		clock-div = &lt;10&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c3: i2c@11014000 {</div><div class='add'>+		compatible = "mediatek,mt6797-i2c",</div><div class='add'>+			     "mediatek,mt6577-i2c";</div><div class='add'>+		reg = &lt;0 0x11014000 0 0x1000&gt;,</div><div class='add'>+		      &lt;0 0x11000480 0 0x80&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 96 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		clocks = &lt;&amp;infrasys CLK_INFRA_I2C3_IMM&gt;,</div><div class='add'>+			 &lt;&amp;infrasys CLK_INFRA_AP_DMA&gt;,</div><div class='add'>+			 &lt;&amp;infrasys CLK_INFRA_I2C3_ARB&gt;;</div><div class='add'>+		clock-names = "main", "dma", "arb";</div><div class='add'>+		clock-div = &lt;10&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c5: i2c@1101c000 {</div><div class='add'>+		compatible = "mediatek,mt6797-i2c",</div><div class='add'>+			     "mediatek,mt6577-i2c";</div><div class='add'>+		reg = &lt;0 0x1101c000 0 0x1000&gt;,</div><div class='add'>+		      &lt;0 0x11000380 0 0x80&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 83 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		clocks = &lt;&amp;infrasys CLK_INFRA_I2C5&gt;,</div><div class='add'>+			 &lt;&amp;infrasys CLK_INFRA_AP_DMA&gt;;</div><div class='add'>+		clock-names = "main", "dma";</div><div class='add'>+		clock-div = &lt;10&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmsys: syscon@14000000 {</div><div class='ctx'> 		compatible = "mediatek,mt6797-mmsys", "syscon";</div><div class='ctx'> 		reg = &lt;0 0x14000000 0 0x1000&gt;;</div><div class='ctx'> 		#clock-cells = &lt;1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	imgsys: imgsys_config@15000000  {</div><div class='add'>+	imgsys: syscon@15000000  {</div><div class='ctx'> 		compatible = "mediatek,mt6797-imgsys", "syscon";</div><div class='ctx'> 		reg = &lt;0 0x15000000 0 0x1000&gt;;</div><div class='ctx'> 		#clock-cells = &lt;1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vdecsys: vdec_gcon@16000000 {</div><div class='add'>+	vdecsys: syscon@16000000 {</div><div class='ctx'> 		compatible = "mediatek,mt6797-vdecsys", "syscon";</div><div class='ctx'> 		reg = &lt;0 0x16000000 0 0x10000&gt;;</div><div class='ctx'> 		#clock-cells = &lt;1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	vencsys: venc_gcon@17000000 {</div><div class='add'>+	vencsys: syscon@17000000 {</div><div class='ctx'> 		compatible = "mediatek,mt6797-vencsys", "syscon";</div><div class='ctx'> 		reg = &lt;0 0x17000000 0 0x1000&gt;;</div><div class='ctx'> 		#clock-cells = &lt;1&gt;;</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt6878-pinfunc.h b/arch/arm64/boot/dts/mediatek/mt6878-pinfunc.h<br/>new file mode 100644<br/>index 000000000000..4e8e475a7454<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt6878-pinfunc.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt6878-pinfunc.h</a></div><div class='hunk'>@@ -0,0 +1,1201 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0 */</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2023 MediaTek Inc.</div><div class='add'>+ * Author: Light Hsieh &lt;light.hsieh@mediatek.com&gt;</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) 2025 Igor Belwon &lt;igor.belwon@mentallysanemainliners.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __MT6878_PINFUNC_H</div><div class='add'>+#define __MT6878_PINFUNC_H</div><div class='add'>+</div><div class='add'>+#include "mt65xx.h"</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)</div><div class='add'>+#define PINMUX_GPIO0__FUNC_TP_GPIO0_AO (MTK_PIN_NO(0) | 1)</div><div class='add'>+#define PINMUX_GPIO0__FUNC_SRCLKENA1 (MTK_PIN_NO(0) | 2)</div><div class='add'>+#define PINMUX_GPIO0__FUNC_DBG_MON_A3 (MTK_PIN_NO(0) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)</div><div class='add'>+#define PINMUX_GPIO1__FUNC_TP_GPIO1_AO (MTK_PIN_NO(1) | 1)</div><div class='add'>+#define PINMUX_GPIO1__FUNC_SRCLKENA1 (MTK_PIN_NO(1) | 2)</div><div class='add'>+#define PINMUX_GPIO1__FUNC_SRCLKENA2 (MTK_PIN_NO(1) | 3)</div><div class='add'>+#define PINMUX_GPIO1__FUNC_IDDIG (MTK_PIN_NO(1) | 5)</div><div class='add'>+#define PINMUX_GPIO1__FUNC_DBG_MON_A4 (MTK_PIN_NO(1) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)</div><div class='add'>+#define PINMUX_GPIO2__FUNC_TP_GPIO2_AO (MTK_PIN_NO(2) | 1)</div><div class='add'>+#define PINMUX_GPIO2__FUNC_SRCLKENAI0 (MTK_PIN_NO(2) | 2)</div><div class='add'>+#define PINMUX_GPIO2__FUNC_SCP_DMIC_CLK (MTK_PIN_NO(2) | 4)</div><div class='add'>+#define PINMUX_GPIO2__FUNC_DMIC_CLK (MTK_PIN_NO(2) | 5)</div><div class='add'>+#define PINMUX_GPIO2__FUNC_DBG_MON_A5 (MTK_PIN_NO(2) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)</div><div class='add'>+#define PINMUX_GPIO3__FUNC_TP_GPIO3_AO (MTK_PIN_NO(3) | 1)</div><div class='add'>+#define PINMUX_GPIO3__FUNC_SRCLKENAI1 (MTK_PIN_NO(3) | 2)</div><div class='add'>+#define PINMUX_GPIO3__FUNC_SCP_DMIC_DAT (MTK_PIN_NO(3) | 4)</div><div class='add'>+#define PINMUX_GPIO3__FUNC_DMIC_DAT (MTK_PIN_NO(3) | 5)</div><div class='add'>+#define PINMUX_GPIO3__FUNC_DBG_MON_A6 (MTK_PIN_NO(3) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)</div><div class='add'>+#define PINMUX_GPIO4__FUNC_SPI7_CLK (MTK_PIN_NO(4) | 1)</div><div class='add'>+#define PINMUX_GPIO4__FUNC_TP_GPIO4_AO (MTK_PIN_NO(4) | 2)</div><div class='add'>+#define PINMUX_GPIO4__FUNC_ANT_SEL0 (MTK_PIN_NO(4) | 3)</div><div class='add'>+#define PINMUX_GPIO4__FUNC_DMIC1_CLK (MTK_PIN_NO(4) | 5)</div><div class='add'>+#define PINMUX_GPIO4__FUNC_MD_INT4 (MTK_PIN_NO(4) | 6)</div><div class='add'>+#define PINMUX_GPIO4__FUNC_DBG_MON_A7 (MTK_PIN_NO(4) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)</div><div class='add'>+#define PINMUX_GPIO5__FUNC_SPI7_CSB (MTK_PIN_NO(5) | 1)</div><div class='add'>+#define PINMUX_GPIO5__FUNC_TP_GPIO5_AO (MTK_PIN_NO(5) | 2)</div><div class='add'>+#define PINMUX_GPIO5__FUNC_ANT_SEL1 (MTK_PIN_NO(5) | 3)</div><div class='add'>+#define PINMUX_GPIO5__FUNC_DMIC1_DAT (MTK_PIN_NO(5) | 5)</div><div class='add'>+#define PINMUX_GPIO5__FUNC_MD_INT0 (MTK_PIN_NO(5) | 6)</div><div class='add'>+#define PINMUX_GPIO5__FUNC_DBG_MON_A8 (MTK_PIN_NO(5) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)</div><div class='add'>+#define PINMUX_GPIO6__FUNC_SPI7_MO (MTK_PIN_NO(6) | 1)</div><div class='add'>+#define PINMUX_GPIO6__FUNC_TP_GPIO6_AO (MTK_PIN_NO(6) | 2)</div><div class='add'>+#define PINMUX_GPIO6__FUNC_ANT_SEL2 (MTK_PIN_NO(6) | 3)</div><div class='add'>+#define PINMUX_GPIO6__FUNC_MD32_0_GPIO0 (MTK_PIN_NO(6) | 4)</div><div class='add'>+#define PINMUX_GPIO6__FUNC_MD_INT3 (MTK_PIN_NO(6) | 6)</div><div class='add'>+#define PINMUX_GPIO6__FUNC_DBG_MON_B0 (MTK_PIN_NO(6) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)</div><div class='add'>+#define PINMUX_GPIO7__FUNC_SPI7_MI (MTK_PIN_NO(7) | 1)</div><div class='add'>+#define PINMUX_GPIO7__FUNC_TP_GPIO7_AO (MTK_PIN_NO(7) | 2)</div><div class='add'>+#define PINMUX_GPIO7__FUNC_ANT_SEL3 (MTK_PIN_NO(7) | 3)</div><div class='add'>+#define PINMUX_GPIO7__FUNC_MD32_1_GPIO0 (MTK_PIN_NO(7) | 4)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)</div><div class='add'>+#define PINMUX_GPIO8__FUNC_SCP_JTAG0_TRSTN_VLP (MTK_PIN_NO(8) | 2)</div><div class='add'>+#define PINMUX_GPIO8__FUNC_SPM_JTAG_TRSTN_VLP (MTK_PIN_NO(8) | 3)</div><div class='add'>+#define PINMUX_GPIO8__FUNC_SSPM_JTAG_TRSTN_VLP (MTK_PIN_NO(8) | 4)</div><div class='add'>+#define PINMUX_GPIO8__FUNC_HFRP_JTAG0_TRSTN (MTK_PIN_NO(8) | 5)</div><div class='add'>+#define PINMUX_GPIO8__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(8) | 6)</div><div class='add'>+#define PINMUX_GPIO8__FUNC_CONN_BGF_MCU_TDI (MTK_PIN_NO(8) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)</div><div class='add'>+#define PINMUX_GPIO9__FUNC_SCP_JTAG0_TCK_VLP (MTK_PIN_NO(9) | 2)</div><div class='add'>+#define PINMUX_GPIO9__FUNC_SPM_JTAG_TCK_VLP (MTK_PIN_NO(9) | 3)</div><div class='add'>+#define PINMUX_GPIO9__FUNC_SSPM_JTAG_TCK_VLP (MTK_PIN_NO(9) | 4)</div><div class='add'>+#define PINMUX_GPIO9__FUNC_HFRP_JTAG0_TCK (MTK_PIN_NO(9) | 5)</div><div class='add'>+#define PINMUX_GPIO9__FUNC_IO_JTAG_TCK (MTK_PIN_NO(9) | 6)</div><div class='add'>+#define PINMUX_GPIO9__FUNC_CONN_BGF_MCU_TRST_B (MTK_PIN_NO(9) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)</div><div class='add'>+#define PINMUX_GPIO10__FUNC_SCP_JTAG0_TMS_VLP (MTK_PIN_NO(10) | 2)</div><div class='add'>+#define PINMUX_GPIO10__FUNC_SPM_JTAG_TMS_VLP (MTK_PIN_NO(10) | 3)</div><div class='add'>+#define PINMUX_GPIO10__FUNC_SSPM_JTAG_TMS_VLP (MTK_PIN_NO(10) | 4)</div><div class='add'>+#define PINMUX_GPIO10__FUNC_HFRP_JTAG0_TMS (MTK_PIN_NO(10) | 5)</div><div class='add'>+#define PINMUX_GPIO10__FUNC_IO_JTAG_TMS (MTK_PIN_NO(10) | 6)</div><div class='add'>+#define PINMUX_GPIO10__FUNC_CONN_BGF_MCU_TCK (MTK_PIN_NO(10) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)</div><div class='add'>+#define PINMUX_GPIO11__FUNC_SCP_JTAG0_TDI_VLP (MTK_PIN_NO(11) | 2)</div><div class='add'>+#define PINMUX_GPIO11__FUNC_SPM_JTAG_TDI_VLP (MTK_PIN_NO(11) | 3)</div><div class='add'>+#define PINMUX_GPIO11__FUNC_SSPM_JTAG_TDI_VLP (MTK_PIN_NO(11) | 4)</div><div class='add'>+#define PINMUX_GPIO11__FUNC_HFRP_JTAG0_TDI (MTK_PIN_NO(11) | 5)</div><div class='add'>+#define PINMUX_GPIO11__FUNC_IO_JTAG_TDI (MTK_PIN_NO(11) | 6)</div><div class='add'>+#define PINMUX_GPIO11__FUNC_CONN_BGF_MCU_TDO (MTK_PIN_NO(11) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)</div><div class='add'>+#define PINMUX_GPIO12__FUNC_SCP_JTAG0_TDO_VLP (MTK_PIN_NO(12) | 2)</div><div class='add'>+#define PINMUX_GPIO12__FUNC_SPM_JTAG_TDO_VLP (MTK_PIN_NO(12) | 3)</div><div class='add'>+#define PINMUX_GPIO12__FUNC_SSPM_JTAG_TDO_VLP (MTK_PIN_NO(12) | 4)</div><div class='add'>+#define PINMUX_GPIO12__FUNC_HFRP_JTAG0_TDO (MTK_PIN_NO(12) | 5)</div><div class='add'>+#define PINMUX_GPIO12__FUNC_IO_JTAG_TDO (MTK_PIN_NO(12) | 6)</div><div class='add'>+#define PINMUX_GPIO12__FUNC_CONN_BGF_MCU_TMS (MTK_PIN_NO(12) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)</div><div class='add'>+#define PINMUX_GPIO13__FUNC_MFG_EB_JTAG_TDI (MTK_PIN_NO(13) | 1)</div><div class='add'>+#define PINMUX_GPIO13__FUNC_CONN_WF_MCU_TDI (MTK_PIN_NO(13) | 2)</div><div class='add'>+#define PINMUX_GPIO13__FUNC_SCP_JTAG0_TDI_VCORE (MTK_PIN_NO(13) | 3)</div><div class='add'>+#define PINMUX_GPIO13__FUNC_SPM_JTAG_TDI_VCORE (MTK_PIN_NO(13) | 5)</div><div class='add'>+#define PINMUX_GPIO13__FUNC_MCUPM_JTAG_TDI (MTK_PIN_NO(13) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)</div><div class='add'>+#define PINMUX_GPIO14__FUNC_MFG_EB_JTAG_TRSTN (MTK_PIN_NO(14) | 1)</div><div class='add'>+#define PINMUX_GPIO14__FUNC_CONN_WF_MCU_TRST_B (MTK_PIN_NO(14) | 2)</div><div class='add'>+#define PINMUX_GPIO14__FUNC_SCP_JTAG0_TRSTN_VCORE (MTK_PIN_NO(14) | 3)</div><div class='add'>+#define PINMUX_GPIO14__FUNC_SPM_JTAG_TRSTN_VCORE (MTK_PIN_NO(14) | 5)</div><div class='add'>+#define PINMUX_GPIO14__FUNC_MCUPM_JTAG_TRSTN (MTK_PIN_NO(14) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)</div><div class='add'>+#define PINMUX_GPIO15__FUNC_MFG_EB_JTAG_TCK (MTK_PIN_NO(15) | 1)</div><div class='add'>+#define PINMUX_GPIO15__FUNC_CONN_WF_MCU_TCK (MTK_PIN_NO(15) | 2)</div><div class='add'>+#define PINMUX_GPIO15__FUNC_SCP_JTAG0_TCK_VCORE (MTK_PIN_NO(15) | 3)</div><div class='add'>+#define PINMUX_GPIO15__FUNC_SPM_JTAG_TCK_VCORE (MTK_PIN_NO(15) | 5)</div><div class='add'>+#define PINMUX_GPIO15__FUNC_MCUPM_JTAG_TCK (MTK_PIN_NO(15) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0)</div><div class='add'>+#define PINMUX_GPIO16__FUNC_MFG_EB_JTAG_TDO (MTK_PIN_NO(16) | 1)</div><div class='add'>+#define PINMUX_GPIO16__FUNC_CONN_WF_MCU_TDO (MTK_PIN_NO(16) | 2)</div><div class='add'>+#define PINMUX_GPIO16__FUNC_SCP_JTAG0_TDO_VCORE (MTK_PIN_NO(16) | 3)</div><div class='add'>+#define PINMUX_GPIO16__FUNC_SPM_JTAG_TDO_VCORE (MTK_PIN_NO(16) | 5)</div><div class='add'>+#define PINMUX_GPIO16__FUNC_MCUPM_JTAG_TDO (MTK_PIN_NO(16) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0)</div><div class='add'>+#define PINMUX_GPIO17__FUNC_MFG_EB_JTAG_TMS (MTK_PIN_NO(17) | 1)</div><div class='add'>+#define PINMUX_GPIO17__FUNC_CONN_WF_MCU_TMS (MTK_PIN_NO(17) | 2)</div><div class='add'>+#define PINMUX_GPIO17__FUNC_SCP_JTAG0_TMS_VCORE (MTK_PIN_NO(17) | 3)</div><div class='add'>+#define PINMUX_GPIO17__FUNC_SPM_JTAG_TMS_VCORE (MTK_PIN_NO(17) | 5)</div><div class='add'>+#define PINMUX_GPIO17__FUNC_MCUPM_JTAG_TMS (MTK_PIN_NO(17) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)</div><div class='add'>+#define PINMUX_GPIO18__FUNC_CONN_BT_TXD (MTK_PIN_NO(18) | 2)</div><div class='add'>+#define PINMUX_GPIO18__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(18) | 3)</div><div class='add'>+#define PINMUX_GPIO18__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(18) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)</div><div class='add'>+#define PINMUX_GPIO19__FUNC_PWM_0 (MTK_PIN_NO(19) | 1)</div><div class='add'>+#define PINMUX_GPIO19__FUNC_SDA10 (MTK_PIN_NO(19) | 3)</div><div class='add'>+#define PINMUX_GPIO19__FUNC_MD32_0_GPIO0 (MTK_PIN_NO(19) | 4)</div><div class='add'>+#define PINMUX_GPIO19__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(19) | 5)</div><div class='add'>+#define PINMUX_GPIO19__FUNC_DBG_MON_A9 (MTK_PIN_NO(19) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)</div><div class='add'>+#define PINMUX_GPIO20__FUNC_PWM_1 (MTK_PIN_NO(20) | 1)</div><div class='add'>+#define PINMUX_GPIO20__FUNC_SPI4_CLK (MTK_PIN_NO(20) | 2)</div><div class='add'>+#define PINMUX_GPIO20__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(20) | 4)</div><div class='add'>+#define PINMUX_GPIO20__FUNC_DAP_SONIC_SWCK (MTK_PIN_NO(20) | 6)</div><div class='add'>+#define PINMUX_GPIO20__FUNC_DBG_MON_A10 (MTK_PIN_NO(20) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)</div><div class='add'>+#define PINMUX_GPIO21__FUNC_PWM_2 (MTK_PIN_NO(21) | 1)</div><div class='add'>+#define PINMUX_GPIO21__FUNC_SPI4_CSB (MTK_PIN_NO(21) | 2)</div><div class='add'>+#define PINMUX_GPIO21__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(21) | 4)</div><div class='add'>+#define PINMUX_GPIO21__FUNC_IDDIG (MTK_PIN_NO(21) | 5)</div><div class='add'>+#define PINMUX_GPIO21__FUNC_DAP_SONIC_SWD (MTK_PIN_NO(21) | 6)</div><div class='add'>+#define PINMUX_GPIO21__FUNC_DBG_MON_A11 (MTK_PIN_NO(21) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)</div><div class='add'>+#define PINMUX_GPIO22__FUNC_PWM_3 (MTK_PIN_NO(22) | 1)</div><div class='add'>+#define PINMUX_GPIO22__FUNC_SPI4_MO (MTK_PIN_NO(22) | 2)</div><div class='add'>+#define PINMUX_GPIO22__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(22) | 4)</div><div class='add'>+#define PINMUX_GPIO22__FUNC_VBUSVALID (MTK_PIN_NO(22) | 5)</div><div class='add'>+#define PINMUX_GPIO22__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(22) | 6)</div><div class='add'>+#define PINMUX_GPIO22__FUNC_DBG_MON_A12 (MTK_PIN_NO(22) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)</div><div class='add'>+#define PINMUX_GPIO23__FUNC_SPI4_MI (MTK_PIN_NO(23) | 2)</div><div class='add'>+#define PINMUX_GPIO23__FUNC_MD32_1_GPIO0 (MTK_PIN_NO(23) | 4)</div><div class='add'>+#define PINMUX_GPIO23__FUNC_USB_DRVVBUS (MTK_PIN_NO(23) | 5)</div><div class='add'>+#define PINMUX_GPIO23__FUNC_DAP_MD32_SWD (MTK_PIN_NO(23) | 6)</div><div class='add'>+#define PINMUX_GPIO23__FUNC_DBG_MON_A13 (MTK_PIN_NO(23) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)</div><div class='add'>+#define PINMUX_GPIO24__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(24) | 1)</div><div class='add'>+#define PINMUX_GPIO24__FUNC_SCL12 (MTK_PIN_NO(24) | 2)</div><div class='add'>+#define PINMUX_GPIO24__FUNC_SCL10 (MTK_PIN_NO(24) | 3)</div><div class='add'>+#define PINMUX_GPIO24__FUNC_CMVREF0 (MTK_PIN_NO(24) | 4)</div><div class='add'>+#define PINMUX_GPIO24__FUNC_CONN_WIFI_TXD (MTK_PIN_NO(24) | 5)</div><div class='add'>+#define PINMUX_GPIO24__FUNC_CMFLASH0 (MTK_PIN_NO(24) | 6)</div><div class='add'>+#define PINMUX_GPIO24__FUNC_DBG_MON_A14 (MTK_PIN_NO(24) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)</div><div class='add'>+#define PINMUX_GPIO25__FUNC_SPI6_CLK (MTK_PIN_NO(25) | 1)</div><div class='add'>+#define PINMUX_GPIO25__FUNC_SCL11 (MTK_PIN_NO(25) | 2)</div><div class='add'>+#define PINMUX_GPIO25__FUNC_CMVREF1 (MTK_PIN_NO(25) | 4)</div><div class='add'>+#define PINMUX_GPIO25__FUNC_CMFLASH1 (MTK_PIN_NO(25) | 6)</div><div class='add'>+#define PINMUX_GPIO25__FUNC_DBG_MON_A15 (MTK_PIN_NO(25) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)</div><div class='add'>+#define PINMUX_GPIO26__FUNC_SPI6_CSB (MTK_PIN_NO(26) | 1)</div><div class='add'>+#define PINMUX_GPIO26__FUNC_SDA11 (MTK_PIN_NO(26) | 2)</div><div class='add'>+#define PINMUX_GPIO26__FUNC_USB_DRVVBUS (MTK_PIN_NO(26) | 3)</div><div class='add'>+#define PINMUX_GPIO26__FUNC_CMVREF2 (MTK_PIN_NO(26) | 4)</div><div class='add'>+#define PINMUX_GPIO26__FUNC_CMFLASH2 (MTK_PIN_NO(26) | 6)</div><div class='add'>+#define PINMUX_GPIO26__FUNC_DBG_MON_A16 (MTK_PIN_NO(26) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)</div><div class='add'>+#define PINMUX_GPIO27__FUNC_SPI6_MO (MTK_PIN_NO(27) | 1)</div><div class='add'>+#define PINMUX_GPIO27__FUNC_VBUSVALID (MTK_PIN_NO(27) | 3)</div><div class='add'>+#define PINMUX_GPIO27__FUNC_CMVREF3 (MTK_PIN_NO(27) | 4)</div><div class='add'>+#define PINMUX_GPIO27__FUNC_DMIC1_CLK (MTK_PIN_NO(27) | 5)</div><div class='add'>+#define PINMUX_GPIO27__FUNC_CMFLASH3 (MTK_PIN_NO(27) | 6)</div><div class='add'>+#define PINMUX_GPIO27__FUNC_DBG_MON_A17 (MTK_PIN_NO(27) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)</div><div class='add'>+#define PINMUX_GPIO28__FUNC_SPI6_MI (MTK_PIN_NO(28) | 1)</div><div class='add'>+#define PINMUX_GPIO28__FUNC_IDDIG (MTK_PIN_NO(28) | 3)</div><div class='add'>+#define PINMUX_GPIO28__FUNC_DMIC1_DAT (MTK_PIN_NO(28) | 5)</div><div class='add'>+#define PINMUX_GPIO28__FUNC_CMFLASH0 (MTK_PIN_NO(28) | 6)</div><div class='add'>+#define PINMUX_GPIO28__FUNC_DBG_MON_A18 (MTK_PIN_NO(28) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)</div><div class='add'>+#define PINMUX_GPIO29__FUNC_I2SIN2_BCK (MTK_PIN_NO(29) | 1)</div><div class='add'>+#define PINMUX_GPIO29__FUNC_TP_UTXD1_VCORE (MTK_PIN_NO(29) | 2)</div><div class='add'>+#define PINMUX_GPIO29__FUNC_MD_UTXD0 (MTK_PIN_NO(29) | 3)</div><div class='add'>+#define PINMUX_GPIO29__FUNC_SSPM_UTXD_AO_VCORE (MTK_PIN_NO(29) | 4)</div><div class='add'>+#define PINMUX_GPIO29__FUNC_MD32_1_TXD (MTK_PIN_NO(29) | 5)</div><div class='add'>+#define PINMUX_GPIO29__FUNC_CONN_BT_TXD (MTK_PIN_NO(29) | 6)</div><div class='add'>+#define PINMUX_GPIO29__FUNC_PTA_TXD (MTK_PIN_NO(29) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0)</div><div class='add'>+#define PINMUX_GPIO30__FUNC_I2SIN2_LRCK (MTK_PIN_NO(30) | 1)</div><div class='add'>+#define PINMUX_GPIO30__FUNC_TP_URXD1_VCORE (MTK_PIN_NO(30) | 2)</div><div class='add'>+#define PINMUX_GPIO30__FUNC_MD_URXD0 (MTK_PIN_NO(30) | 3)</div><div class='add'>+#define PINMUX_GPIO30__FUNC_SSPM_URXD_AO_VCORE (MTK_PIN_NO(30) | 4)</div><div class='add'>+#define PINMUX_GPIO30__FUNC_MD32_1_RXD (MTK_PIN_NO(30) | 5)</div><div class='add'>+#define PINMUX_GPIO30__FUNC_PTA_RXD (MTK_PIN_NO(30) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0)</div><div class='add'>+#define PINMUX_GPIO31__FUNC_I2SOUT2_DO (MTK_PIN_NO(31) | 1)</div><div class='add'>+#define PINMUX_GPIO31__FUNC_TP_UTXD2_VCORE (MTK_PIN_NO(31) | 2)</div><div class='add'>+#define PINMUX_GPIO31__FUNC_MD_UTXD1 (MTK_PIN_NO(31) | 3)</div><div class='add'>+#define PINMUX_GPIO31__FUNC_HFRP_UTXD1 (MTK_PIN_NO(31) | 4)</div><div class='add'>+#define PINMUX_GPIO31__FUNC_MD32_0_TXD (MTK_PIN_NO(31) | 5)</div><div class='add'>+#define PINMUX_GPIO31__FUNC_CONN_WIFI_TXD (MTK_PIN_NO(31) | 6)</div><div class='add'>+#define PINMUX_GPIO31__FUNC_CONN_BGF_UART0_TXD (MTK_PIN_NO(31) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0)</div><div class='add'>+#define PINMUX_GPIO32__FUNC_I2SIN2_DI (MTK_PIN_NO(32) | 1)</div><div class='add'>+#define PINMUX_GPIO32__FUNC_TP_URXD2_VCORE (MTK_PIN_NO(32) | 2)</div><div class='add'>+#define PINMUX_GPIO32__FUNC_MD_URXD1 (MTK_PIN_NO(32) | 3)</div><div class='add'>+#define PINMUX_GPIO32__FUNC_HFRP_URXD1 (MTK_PIN_NO(32) | 4)</div><div class='add'>+#define PINMUX_GPIO32__FUNC_MD32_0_RXD (MTK_PIN_NO(32) | 5)</div><div class='add'>+#define PINMUX_GPIO32__FUNC_CONN_BGF_UART0_RXD (MTK_PIN_NO(32) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)</div><div class='add'>+#define PINMUX_GPIO33__FUNC_ANT_SEL0 (MTK_PIN_NO(33) | 1)</div><div class='add'>+#define PINMUX_GPIO33__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(33) | 3)</div><div class='add'>+#define PINMUX_GPIO33__FUNC_SCL1 (MTK_PIN_NO(33) | 4)</div><div class='add'>+#define PINMUX_GPIO33__FUNC_CONN_BPI_BUS18_ANT1 (MTK_PIN_NO(33) | 5)</div><div class='add'>+#define PINMUX_GPIO33__FUNC_MD_UCTS0 (MTK_PIN_NO(33) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)</div><div class='add'>+#define PINMUX_GPIO34__FUNC_ANT_SEL1 (MTK_PIN_NO(34) | 1)</div><div class='add'>+#define PINMUX_GPIO34__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(34) | 3)</div><div class='add'>+#define PINMUX_GPIO34__FUNC_SDA1 (MTK_PIN_NO(34) | 4)</div><div class='add'>+#define PINMUX_GPIO34__FUNC_CONN_BPI_BUS19_ANT2 (MTK_PIN_NO(34) | 5)</div><div class='add'>+#define PINMUX_GPIO34__FUNC_MD_URTS0 (MTK_PIN_NO(34) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)</div><div class='add'>+#define PINMUX_GPIO35__FUNC_ANT_SEL2 (MTK_PIN_NO(35) | 1)</div><div class='add'>+#define PINMUX_GPIO35__FUNC_SSPM_JTAG_TCK_VCORE (MTK_PIN_NO(35) | 2)</div><div class='add'>+#define PINMUX_GPIO35__FUNC_UDI_TCK (MTK_PIN_NO(35) | 3)</div><div class='add'>+#define PINMUX_GPIO35__FUNC_CONN_BPI_BUS20_ANT3 (MTK_PIN_NO(35) | 5)</div><div class='add'>+#define PINMUX_GPIO35__FUNC_MD_UCTS1 (MTK_PIN_NO(35) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)</div><div class='add'>+#define PINMUX_GPIO36__FUNC_ANT_SEL3 (MTK_PIN_NO(36) | 1)</div><div class='add'>+#define PINMUX_GPIO36__FUNC_SSPM_JTAG_TRSTN_VCORE (MTK_PIN_NO(36) | 2)</div><div class='add'>+#define PINMUX_GPIO36__FUNC_UDI_NTRST (MTK_PIN_NO(36) | 3)</div><div class='add'>+#define PINMUX_GPIO36__FUNC_CONN_BPI_BUS21_ANT4 (MTK_PIN_NO(36) | 5)</div><div class='add'>+#define PINMUX_GPIO36__FUNC_MD_URTS1 (MTK_PIN_NO(36) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)</div><div class='add'>+#define PINMUX_GPIO37__FUNC_ANT_SEL4 (MTK_PIN_NO(37) | 1)</div><div class='add'>+#define PINMUX_GPIO37__FUNC_SSPM_JTAG_TDI_VCORE (MTK_PIN_NO(37) | 2)</div><div class='add'>+#define PINMUX_GPIO37__FUNC_UDI_TDI (MTK_PIN_NO(37) | 3)</div><div class='add'>+#define PINMUX_GPIO37__FUNC_TP_UCTS1_VCORE (MTK_PIN_NO(37) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0)</div><div class='add'>+#define PINMUX_GPIO38__FUNC_ANT_SEL5 (MTK_PIN_NO(38) | 1)</div><div class='add'>+#define PINMUX_GPIO38__FUNC_SSPM_JTAG_TMS_VCORE (MTK_PIN_NO(38) | 2)</div><div class='add'>+#define PINMUX_GPIO38__FUNC_UDI_TMS (MTK_PIN_NO(38) | 3)</div><div class='add'>+#define PINMUX_GPIO38__FUNC_TP_URTS1_VCORE (MTK_PIN_NO(38) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)</div><div class='add'>+#define PINMUX_GPIO39__FUNC_ANT_SEL6 (MTK_PIN_NO(39) | 1)</div><div class='add'>+#define PINMUX_GPIO39__FUNC_SSPM_JTAG_TDO_VCORE (MTK_PIN_NO(39) | 2)</div><div class='add'>+#define PINMUX_GPIO39__FUNC_UDI_TDO (MTK_PIN_NO(39) | 3)</div><div class='add'>+#define PINMUX_GPIO39__FUNC_CLKM3 (MTK_PIN_NO(39) | 5)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)</div><div class='add'>+#define PINMUX_GPIO40__FUNC_ANT_SEL7 (MTK_PIN_NO(40) | 1)</div><div class='add'>+#define PINMUX_GPIO40__FUNC_PMSR_SMAP (MTK_PIN_NO(40) | 2)</div><div class='add'>+#define PINMUX_GPIO40__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(40) | 3)</div><div class='add'>+#define PINMUX_GPIO40__FUNC_CONN_WIFI_TXD (MTK_PIN_NO(40) | 4)</div><div class='add'>+#define PINMUX_GPIO40__FUNC_GPS_PPS (MTK_PIN_NO(40) | 5)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0)</div><div class='add'>+#define PINMUX_GPIO41__FUNC_I2SIN1_MCK (MTK_PIN_NO(41) | 1)</div><div class='add'>+#define PINMUX_GPIO41__FUNC_IDDIG (MTK_PIN_NO(41) | 2)</div><div class='add'>+#define PINMUX_GPIO41__FUNC_GPS_PPS (MTK_PIN_NO(41) | 3)</div><div class='add'>+#define PINMUX_GPIO41__FUNC_HFRP_UCTS1 (MTK_PIN_NO(41) | 4)</div><div class='add'>+#define PINMUX_GPIO41__FUNC_TP_UCTS2_VCORE (MTK_PIN_NO(41) | 5)</div><div class='add'>+#define PINMUX_GPIO41__FUNC_ANT_SEL8 (MTK_PIN_NO(41) | 6)</div><div class='add'>+#define PINMUX_GPIO41__FUNC_DBG_MON_B1 (MTK_PIN_NO(41) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0)</div><div class='add'>+#define PINMUX_GPIO42__FUNC_I2SIN1_BCK (MTK_PIN_NO(42) | 1)</div><div class='add'>+#define PINMUX_GPIO42__FUNC_I2SIN4_BCK (MTK_PIN_NO(42) | 2)</div><div class='add'>+#define PINMUX_GPIO42__FUNC_HFRP_URTS1 (MTK_PIN_NO(42) | 4)</div><div class='add'>+#define PINMUX_GPIO42__FUNC_TP_URTS2_VCORE (MTK_PIN_NO(42) | 5)</div><div class='add'>+#define PINMUX_GPIO42__FUNC_ANT_SEL9 (MTK_PIN_NO(42) | 6)</div><div class='add'>+#define PINMUX_GPIO42__FUNC_DBG_MON_B2 (MTK_PIN_NO(42) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0)</div><div class='add'>+#define PINMUX_GPIO43__FUNC_I2SIN1_LRCK (MTK_PIN_NO(43) | 1)</div><div class='add'>+#define PINMUX_GPIO43__FUNC_I2SIN4_LRCK (MTK_PIN_NO(43) | 2)</div><div class='add'>+#define PINMUX_GPIO43__FUNC_ANT_SEL10 (MTK_PIN_NO(43) | 6)</div><div class='add'>+#define PINMUX_GPIO43__FUNC_DBG_MON_B3 (MTK_PIN_NO(43) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0)</div><div class='add'>+#define PINMUX_GPIO44__FUNC_I2SOUT1_DO (MTK_PIN_NO(44) | 1)</div><div class='add'>+#define PINMUX_GPIO44__FUNC_I2SOUT4_DATA0 (MTK_PIN_NO(44) | 2)</div><div class='add'>+#define PINMUX_GPIO44__FUNC_ANT_SEL11 (MTK_PIN_NO(44) | 6)</div><div class='add'>+#define PINMUX_GPIO44__FUNC_DBG_MON_B4 (MTK_PIN_NO(44) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0)</div><div class='add'>+#define PINMUX_GPIO45__FUNC_I2SIN1_DI (MTK_PIN_NO(45) | 1)</div><div class='add'>+#define PINMUX_GPIO45__FUNC_I2SIN4_DATA0 (MTK_PIN_NO(45) | 2)</div><div class='add'>+#define PINMUX_GPIO45__FUNC_AGPS_SYNC (MTK_PIN_NO(45) | 5)</div><div class='add'>+#define PINMUX_GPIO45__FUNC_ANT_SEL12 (MTK_PIN_NO(45) | 6)</div><div class='add'>+#define PINMUX_GPIO45__FUNC_DBG_MON_B5 (MTK_PIN_NO(45) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0)</div><div class='add'>+#define PINMUX_GPIO46__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(46) | 1)</div><div class='add'>+#define PINMUX_GPIO46__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(46) | 2)</div><div class='add'>+#define PINMUX_GPIO46__FUNC_SRCLKENAI0 (MTK_PIN_NO(46) | 3)</div><div class='add'>+#define PINMUX_GPIO46__FUNC_SSPM_UTXD_AO_VLP (MTK_PIN_NO(46) | 5)</div><div class='add'>+#define PINMUX_GPIO46__FUNC_MD_MCIF_UTXD0 (MTK_PIN_NO(46) | 6)</div><div class='add'>+#define PINMUX_GPIO46__FUNC_DBG_MON_B6 (MTK_PIN_NO(46) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0)</div><div class='add'>+#define PINMUX_GPIO47__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(47) | 1)</div><div class='add'>+#define PINMUX_GPIO47__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(47) | 2)</div><div class='add'>+#define PINMUX_GPIO47__FUNC_SRCLKENAI1 (MTK_PIN_NO(47) | 3)</div><div class='add'>+#define PINMUX_GPIO47__FUNC_SRCLKENA1 (MTK_PIN_NO(47) | 4)</div><div class='add'>+#define PINMUX_GPIO47__FUNC_SSPM_URXD_AO_VLP (MTK_PIN_NO(47) | 5)</div><div class='add'>+#define PINMUX_GPIO47__FUNC_MD_MCIF_URXD0 (MTK_PIN_NO(47) | 6)</div><div class='add'>+#define PINMUX_GPIO47__FUNC_DBG_MON_B7 (MTK_PIN_NO(47) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0)</div><div class='add'>+#define PINMUX_GPIO48__FUNC_UTXD0 (MTK_PIN_NO(48) | 1)</div><div class='add'>+#define PINMUX_GPIO48__FUNC_MD_UTXD1 (MTK_PIN_NO(48) | 3)</div><div class='add'>+#define PINMUX_GPIO48__FUNC_HFRP_UTXD1 (MTK_PIN_NO(48) | 4)</div><div class='add'>+#define PINMUX_GPIO48__FUNC_MD32_0_TXD (MTK_PIN_NO(48) | 5)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0)</div><div class='add'>+#define PINMUX_GPIO49__FUNC_URXD0 (MTK_PIN_NO(49) | 1)</div><div class='add'>+#define PINMUX_GPIO49__FUNC_MD_URXD1 (MTK_PIN_NO(49) | 3)</div><div class='add'>+#define PINMUX_GPIO49__FUNC_HFRP_URXD1 (MTK_PIN_NO(49) | 4)</div><div class='add'>+#define PINMUX_GPIO49__FUNC_MD32_0_RXD (MTK_PIN_NO(49) | 5)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0)</div><div class='add'>+#define PINMUX_GPIO50__FUNC_MD_UTXD0 (MTK_PIN_NO(50) | 1)</div><div class='add'>+#define PINMUX_GPIO50__FUNC_TP_UTXD1_VLP (MTK_PIN_NO(50) | 2)</div><div class='add'>+#define PINMUX_GPIO50__FUNC_CONN_BGF_UART0_TXD (MTK_PIN_NO(50) | 3)</div><div class='add'>+#define PINMUX_GPIO50__FUNC_SSPM_UTXD_AO_VLP (MTK_PIN_NO(50) | 4)</div><div class='add'>+#define PINMUX_GPIO50__FUNC_MD_MCIF_UTXD0 (MTK_PIN_NO(50) | 5)</div><div class='add'>+#define PINMUX_GPIO50__FUNC_TP_UTXD2_VLP (MTK_PIN_NO(50) | 6)</div><div class='add'>+#define PINMUX_GPIO50__FUNC_UTXD1 (MTK_PIN_NO(50) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0)</div><div class='add'>+#define PINMUX_GPIO51__FUNC_MD_URXD0 (MTK_PIN_NO(51) | 1)</div><div class='add'>+#define PINMUX_GPIO51__FUNC_TP_URXD1_VLP (MTK_PIN_NO(51) | 2)</div><div class='add'>+#define PINMUX_GPIO51__FUNC_CONN_BGF_UART0_RXD (MTK_PIN_NO(51) | 3)</div><div class='add'>+#define PINMUX_GPIO51__FUNC_SSPM_URXD_AO_VLP (MTK_PIN_NO(51) | 4)</div><div class='add'>+#define PINMUX_GPIO51__FUNC_MD_MCIF_URXD0 (MTK_PIN_NO(51) | 5)</div><div class='add'>+#define PINMUX_GPIO51__FUNC_TP_URXD2_VLP (MTK_PIN_NO(51) | 6)</div><div class='add'>+#define PINMUX_GPIO51__FUNC_URXD1 (MTK_PIN_NO(51) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0)</div><div class='add'>+#define PINMUX_GPIO52__FUNC_KPROW0 (MTK_PIN_NO(52) | 1)</div><div class='add'>+#define PINMUX_GPIO52__FUNC_CMFLASH0 (MTK_PIN_NO(52) | 2)</div><div class='add'>+#define PINMUX_GPIO52__FUNC_SDA12 (MTK_PIN_NO(52) | 3)</div><div class='add'>+#define PINMUX_GPIO52__FUNC_DSI_TE1 (MTK_PIN_NO(52) | 4)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0)</div><div class='add'>+#define PINMUX_GPIO53__FUNC_KPROW1 (MTK_PIN_NO(53) | 1)</div><div class='add'>+#define PINMUX_GPIO53__FUNC_CMFLASH1 (MTK_PIN_NO(53) | 2)</div><div class='add'>+#define PINMUX_GPIO53__FUNC_SCL12 (MTK_PIN_NO(53) | 3)</div><div class='add'>+#define PINMUX_GPIO53__FUNC_LCM_RST1 (MTK_PIN_NO(53) | 4)</div><div class='add'>+#define PINMUX_GPIO53__FUNC_EXTIF0_ACT (MTK_PIN_NO(53) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0)</div><div class='add'>+#define PINMUX_GPIO54__FUNC_KPCOL0_VLP (MTK_PIN_NO(54) | 1)</div><div class='add'>+#define PINMUX_GPIO54__FUNC_KPCOL0_VLP_A (MTK_PIN_NO(54) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0)</div><div class='add'>+#define PINMUX_GPIO55__FUNC_KPCOL1 (MTK_PIN_NO(55) | 1)</div><div class='add'>+#define PINMUX_GPIO55__FUNC_SDA12 (MTK_PIN_NO(55) | 3)</div><div class='add'>+#define PINMUX_GPIO55__FUNC_DISP_PWM1 (MTK_PIN_NO(55) | 4)</div><div class='add'>+#define PINMUX_GPIO55__FUNC_JTRSTN_SEL1_VCORE (MTK_PIN_NO(55) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0)</div><div class='add'>+#define PINMUX_GPIO56__FUNC_SPI0_CLK (MTK_PIN_NO(56) | 1)</div><div class='add'>+#define PINMUX_GPIO56__FUNC_JTCK_SEL1_VCORE (MTK_PIN_NO(56) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0)</div><div class='add'>+#define PINMUX_GPIO57__FUNC_SPI0_CSB (MTK_PIN_NO(57) | 1)</div><div class='add'>+#define PINMUX_GPIO57__FUNC_JTMS_SEL1_VCORE (MTK_PIN_NO(57) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0)</div><div class='add'>+#define PINMUX_GPIO58__FUNC_SPI0_MO (MTK_PIN_NO(58) | 1)</div><div class='add'>+#define PINMUX_GPIO58__FUNC_JTDO_SEL1_VCORE (MTK_PIN_NO(58) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0)</div><div class='add'>+#define PINMUX_GPIO59__FUNC_SPI0_MI (MTK_PIN_NO(59) | 1)</div><div class='add'>+#define PINMUX_GPIO59__FUNC_JTDI_SEL1_VCORE (MTK_PIN_NO(59) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0)</div><div class='add'>+#define PINMUX_GPIO60__FUNC_SCP_SPI1_CK (MTK_PIN_NO(60) | 1)</div><div class='add'>+#define PINMUX_GPIO60__FUNC_SPI1_CLK (MTK_PIN_NO(60) | 2)</div><div class='add'>+#define PINMUX_GPIO60__FUNC_SCP_SCL3 (MTK_PIN_NO(60) | 4)</div><div class='add'>+#define PINMUX_GPIO60__FUNC_TP_GPIO0_AO (MTK_PIN_NO(60) | 5)</div><div class='add'>+#define PINMUX_GPIO60__FUNC_UTXD0 (MTK_PIN_NO(60) | 6)</div><div class='add'>+#define PINMUX_GPIO60__FUNC_TP_UTXD2_VLP (MTK_PIN_NO(60) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0)</div><div class='add'>+#define PINMUX_GPIO61__FUNC_SCP_SPI1_CS (MTK_PIN_NO(61) | 1)</div><div class='add'>+#define PINMUX_GPIO61__FUNC_SPI1_CSB (MTK_PIN_NO(61) | 2)</div><div class='add'>+#define PINMUX_GPIO61__FUNC_TP_GPIO1_AO (MTK_PIN_NO(61) | 5)</div><div class='add'>+#define PINMUX_GPIO61__FUNC_URXD0 (MTK_PIN_NO(61) | 6)</div><div class='add'>+#define PINMUX_GPIO61__FUNC_TP_URXD2_VLP (MTK_PIN_NO(61) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0)</div><div class='add'>+#define PINMUX_GPIO62__FUNC_SCP_SPI1_MO (MTK_PIN_NO(62) | 1)</div><div class='add'>+#define PINMUX_GPIO62__FUNC_SPI1_MO (MTK_PIN_NO(62) | 2)</div><div class='add'>+#define PINMUX_GPIO62__FUNC_SCP_SCL3 (MTK_PIN_NO(62) | 3)</div><div class='add'>+#define PINMUX_GPIO62__FUNC_SCP_SDA3 (MTK_PIN_NO(62) | 4)</div><div class='add'>+#define PINMUX_GPIO62__FUNC_TP_GPIO2_AO (MTK_PIN_NO(62) | 5)</div><div class='add'>+#define PINMUX_GPIO62__FUNC_DBG_MON_B29 (MTK_PIN_NO(62) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0)</div><div class='add'>+#define PINMUX_GPIO63__FUNC_SCP_SPI1_MI (MTK_PIN_NO(63) | 1)</div><div class='add'>+#define PINMUX_GPIO63__FUNC_SPI1_MI (MTK_PIN_NO(63) | 2)</div><div class='add'>+#define PINMUX_GPIO63__FUNC_SCP_SDA3 (MTK_PIN_NO(63) | 3)</div><div class='add'>+#define PINMUX_GPIO63__FUNC_TP_GPIO3_AO (MTK_PIN_NO(63) | 5)</div><div class='add'>+#define PINMUX_GPIO63__FUNC_DBG_MON_B30 (MTK_PIN_NO(63) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0)</div><div class='add'>+#define PINMUX_GPIO64__FUNC_SCP_SPI2_CK (MTK_PIN_NO(64) | 1)</div><div class='add'>+#define PINMUX_GPIO64__FUNC_SPI2_CLK (MTK_PIN_NO(64) | 2)</div><div class='add'>+#define PINMUX_GPIO64__FUNC_SCP_SCL2 (MTK_PIN_NO(64) | 4)</div><div class='add'>+#define PINMUX_GPIO64__FUNC_TP_GPIO4_AO (MTK_PIN_NO(64) | 5)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0)</div><div class='add'>+#define PINMUX_GPIO65__FUNC_SCP_SPI2_CS (MTK_PIN_NO(65) | 1)</div><div class='add'>+#define PINMUX_GPIO65__FUNC_SPI2_CSB (MTK_PIN_NO(65) | 2)</div><div class='add'>+#define PINMUX_GPIO65__FUNC_TP_GPIO5_AO (MTK_PIN_NO(65) | 5)</div><div class='add'>+#define PINMUX_GPIO65__FUNC_DBG_MON_B31 (MTK_PIN_NO(65) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0)</div><div class='add'>+#define PINMUX_GPIO66__FUNC_SCP_SPI2_MO (MTK_PIN_NO(66) | 1)</div><div class='add'>+#define PINMUX_GPIO66__FUNC_SPI2_MO (MTK_PIN_NO(66) | 2)</div><div class='add'>+#define PINMUX_GPIO66__FUNC_SCP_SCL2 (MTK_PIN_NO(66) | 3)</div><div class='add'>+#define PINMUX_GPIO66__FUNC_SCP_SDA2 (MTK_PIN_NO(66) | 4)</div><div class='add'>+#define PINMUX_GPIO66__FUNC_TP_GPIO6_AO (MTK_PIN_NO(66) | 5)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0)</div><div class='add'>+#define PINMUX_GPIO67__FUNC_SCP_SPI2_MI (MTK_PIN_NO(67) | 1)</div><div class='add'>+#define PINMUX_GPIO67__FUNC_SPI2_MI (MTK_PIN_NO(67) | 2)</div><div class='add'>+#define PINMUX_GPIO67__FUNC_SCP_SDA2 (MTK_PIN_NO(67) | 3)</div><div class='add'>+#define PINMUX_GPIO67__FUNC_TP_GPIO7_AO (MTK_PIN_NO(67) | 5)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0)</div><div class='add'>+#define PINMUX_GPIO68__FUNC_SCP_SPI3_CK (MTK_PIN_NO(68) | 1)</div><div class='add'>+#define PINMUX_GPIO68__FUNC_SPI3_CLK (MTK_PIN_NO(68) | 2)</div><div class='add'>+#define PINMUX_GPIO68__FUNC_MD_INT4 (MTK_PIN_NO(68) | 3)</div><div class='add'>+#define PINMUX_GPIO68__FUNC_SCP_SCL4 (MTK_PIN_NO(68) | 4)</div><div class='add'>+#define PINMUX_GPIO68__FUNC_TP_GPIO8_AO (MTK_PIN_NO(68) | 5)</div><div class='add'>+#define PINMUX_GPIO68__FUNC_DBG_MON_A19 (MTK_PIN_NO(68) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0)</div><div class='add'>+#define PINMUX_GPIO69__FUNC_SCP_SPI3_CS (MTK_PIN_NO(69) | 1)</div><div class='add'>+#define PINMUX_GPIO69__FUNC_SPI3_CSB (MTK_PIN_NO(69) | 2)</div><div class='add'>+#define PINMUX_GPIO69__FUNC_MD_INT3 (MTK_PIN_NO(69) | 3)</div><div class='add'>+#define PINMUX_GPIO69__FUNC_TP_GPIO9_AO (MTK_PIN_NO(69) | 5)</div><div class='add'>+#define PINMUX_GPIO69__FUNC_DBG_MON_A20 (MTK_PIN_NO(69) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0)</div><div class='add'>+#define PINMUX_GPIO70__FUNC_SCP_SPI3_MO (MTK_PIN_NO(70) | 1)</div><div class='add'>+#define PINMUX_GPIO70__FUNC_SPI3_MO (MTK_PIN_NO(70) | 2)</div><div class='add'>+#define PINMUX_GPIO70__FUNC_SCP_SCL4 (MTK_PIN_NO(70) | 3)</div><div class='add'>+#define PINMUX_GPIO70__FUNC_SCP_SDA4 (MTK_PIN_NO(70) | 4)</div><div class='add'>+#define PINMUX_GPIO70__FUNC_TP_GPIO10_AO (MTK_PIN_NO(70) | 5)</div><div class='add'>+#define PINMUX_GPIO70__FUNC_DBG_MON_A21 (MTK_PIN_NO(70) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0)</div><div class='add'>+#define PINMUX_GPIO71__FUNC_SCP_SPI3_MI (MTK_PIN_NO(71) | 1)</div><div class='add'>+#define PINMUX_GPIO71__FUNC_SPI3_MI (MTK_PIN_NO(71) | 2)</div><div class='add'>+#define PINMUX_GPIO71__FUNC_SCP_SDA4 (MTK_PIN_NO(71) | 3)</div><div class='add'>+#define PINMUX_GPIO71__FUNC_MD_INT0 (MTK_PIN_NO(71) | 4)</div><div class='add'>+#define PINMUX_GPIO71__FUNC_TP_GPIO11_AO (MTK_PIN_NO(71) | 5)</div><div class='add'>+#define PINMUX_GPIO71__FUNC_DBG_MON_A22 (MTK_PIN_NO(71) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0)</div><div class='add'>+#define PINMUX_GPIO72__FUNC_SPI5_CLK (MTK_PIN_NO(72) | 1)</div><div class='add'>+#define PINMUX_GPIO72__FUNC_SCP_SPI0_CK (MTK_PIN_NO(72) | 2)</div><div class='add'>+#define PINMUX_GPIO72__FUNC_UCTS2 (MTK_PIN_NO(72) | 3)</div><div class='add'>+#define PINMUX_GPIO72__FUNC_MBISTREADEN_TRIGGER (MTK_PIN_NO(72) | 4)</div><div class='add'>+#define PINMUX_GPIO72__FUNC_TP_GPIO12_AO (MTK_PIN_NO(72) | 5)</div><div class='add'>+#define PINMUX_GPIO72__FUNC_EXTIF0_ACT (MTK_PIN_NO(72) | 6)</div><div class='add'>+#define PINMUX_GPIO72__FUNC_DAP_SONIC_SWCK (MTK_PIN_NO(72) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0)</div><div class='add'>+#define PINMUX_GPIO73__FUNC_SPI5_CSB (MTK_PIN_NO(73) | 1)</div><div class='add'>+#define PINMUX_GPIO73__FUNC_SCP_SPI0_CS (MTK_PIN_NO(73) | 2)</div><div class='add'>+#define PINMUX_GPIO73__FUNC_URTS2 (MTK_PIN_NO(73) | 3)</div><div class='add'>+#define PINMUX_GPIO73__FUNC_MBISTWRITEEN_TRIGGER (MTK_PIN_NO(73) | 4)</div><div class='add'>+#define PINMUX_GPIO73__FUNC_TP_GPIO13_AO (MTK_PIN_NO(73) | 5)</div><div class='add'>+#define PINMUX_GPIO73__FUNC_EXTIF0_PRI (MTK_PIN_NO(73) | 6)</div><div class='add'>+#define PINMUX_GPIO73__FUNC_DAP_SONIC_SWD (MTK_PIN_NO(73) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0)</div><div class='add'>+#define PINMUX_GPIO74__FUNC_SPI5_MO (MTK_PIN_NO(74) | 1)</div><div class='add'>+#define PINMUX_GPIO74__FUNC_SCP_SPI0_MO (MTK_PIN_NO(74) | 2)</div><div class='add'>+#define PINMUX_GPIO74__FUNC_UTXD2 (MTK_PIN_NO(74) | 3)</div><div class='add'>+#define PINMUX_GPIO74__FUNC_TP_UTXD2_VCORE (MTK_PIN_NO(74) | 4)</div><div class='add'>+#define PINMUX_GPIO74__FUNC_TP_GPIO14_AO (MTK_PIN_NO(74) | 5)</div><div class='add'>+#define PINMUX_GPIO74__FUNC_EXTIF0_GNT_B (MTK_PIN_NO(74) | 6)</div><div class='add'>+#define PINMUX_GPIO74__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(74) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0)</div><div class='add'>+#define PINMUX_GPIO75__FUNC_SPI5_MI (MTK_PIN_NO(75) | 1)</div><div class='add'>+#define PINMUX_GPIO75__FUNC_SCP_SPI0_MI (MTK_PIN_NO(75) | 2)</div><div class='add'>+#define PINMUX_GPIO75__FUNC_URXD2 (MTK_PIN_NO(75) | 3)</div><div class='add'>+#define PINMUX_GPIO75__FUNC_TP_URXD2_VCORE (MTK_PIN_NO(75) | 4)</div><div class='add'>+#define PINMUX_GPIO75__FUNC_TP_GPIO15_AO (MTK_PIN_NO(75) | 5)</div><div class='add'>+#define PINMUX_GPIO75__FUNC_DAP_MD32_SWD (MTK_PIN_NO(75) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0)</div><div class='add'>+#define PINMUX_GPIO76__FUNC_AP_GOOD (MTK_PIN_NO(76) | 1)</div><div class='add'>+#define PINMUX_GPIO76__FUNC_CONN_WIFI_TXD (MTK_PIN_NO(76) | 3)</div><div class='add'>+#define PINMUX_GPIO76__FUNC_GPS_PPS (MTK_PIN_NO(76) | 4)</div><div class='add'>+#define PINMUX_GPIO76__FUNC_PMSR_SMAP (MTK_PIN_NO(76) | 5)</div><div class='add'>+#define PINMUX_GPIO76__FUNC_AGPS_SYNC (MTK_PIN_NO(76) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0)</div><div class='add'>+#define PINMUX_GPIO77__FUNC_MSDC1_CLK (MTK_PIN_NO(77) | 1)</div><div class='add'>+#define PINMUX_GPIO77__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(77) | 2)</div><div class='add'>+#define PINMUX_GPIO77__FUNC_UDI_TCK (MTK_PIN_NO(77) | 3)</div><div class='add'>+#define PINMUX_GPIO77__FUNC_CONN_DSP_JCK (MTK_PIN_NO(77) | 4)</div><div class='add'>+#define PINMUX_GPIO77__FUNC_TSFDC_EN (MTK_PIN_NO(77) | 6)</div><div class='add'>+#define PINMUX_GPIO77__FUNC_SSPM_JTAG_TCK_VCORE (MTK_PIN_NO(77) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0)</div><div class='add'>+#define PINMUX_GPIO78__FUNC_MSDC1_CMD (MTK_PIN_NO(78) | 1)</div><div class='add'>+#define PINMUX_GPIO78__FUNC_CONN_WF_MCU_AICE_TMSC (MTK_PIN_NO(78) | 2)</div><div class='add'>+#define PINMUX_GPIO78__FUNC_UDI_TMS (MTK_PIN_NO(78) | 3)</div><div class='add'>+#define PINMUX_GPIO78__FUNC_CONN_DSP_JMS (MTK_PIN_NO(78) | 4)</div><div class='add'>+#define PINMUX_GPIO78__FUNC_TSFDC_VCO_RST (MTK_PIN_NO(78) | 6)</div><div class='add'>+#define PINMUX_GPIO78__FUNC_SSPM_JTAG_TMS_VCORE (MTK_PIN_NO(78) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0)</div><div class='add'>+#define PINMUX_GPIO79__FUNC_MSDC1_DAT0 (MTK_PIN_NO(79) | 1)</div><div class='add'>+#define PINMUX_GPIO79__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(79) | 2)</div><div class='add'>+#define PINMUX_GPIO79__FUNC_UDI_TDI (MTK_PIN_NO(79) | 3)</div><div class='add'>+#define PINMUX_GPIO79__FUNC_CONN_DSP_JDI (MTK_PIN_NO(79) | 4)</div><div class='add'>+#define PINMUX_GPIO79__FUNC_TSFDC_TSSEL2 (MTK_PIN_NO(79) | 6)</div><div class='add'>+#define PINMUX_GPIO79__FUNC_SSPM_JTAG_TDI_VCORE (MTK_PIN_NO(79) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0)</div><div class='add'>+#define PINMUX_GPIO80__FUNC_MSDC1_DAT1 (MTK_PIN_NO(80) | 1)</div><div class='add'>+#define PINMUX_GPIO80__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(80) | 2)</div><div class='add'>+#define PINMUX_GPIO80__FUNC_UDI_TDO (MTK_PIN_NO(80) | 3)</div><div class='add'>+#define PINMUX_GPIO80__FUNC_CONN_DSP_JDO (MTK_PIN_NO(80) | 4)</div><div class='add'>+#define PINMUX_GPIO80__FUNC_TSFDC_TSSEL1 (MTK_PIN_NO(80) | 6)</div><div class='add'>+#define PINMUX_GPIO80__FUNC_SSPM_JTAG_TDO_VCORE (MTK_PIN_NO(80) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0)</div><div class='add'>+#define PINMUX_GPIO81__FUNC_MSDC1_DAT2 (MTK_PIN_NO(81) | 1)</div><div class='add'>+#define PINMUX_GPIO81__FUNC_CONN_WF_MCU_AICE_TCKC (MTK_PIN_NO(81) | 2)</div><div class='add'>+#define PINMUX_GPIO81__FUNC_UDI_NTRST (MTK_PIN_NO(81) | 3)</div><div class='add'>+#define PINMUX_GPIO81__FUNC_CONN_BGF_MCU_AICE_TCKC (MTK_PIN_NO(81) | 4)</div><div class='add'>+#define PINMUX_GPIO81__FUNC_MIPI3_D_SDATA (MTK_PIN_NO(81) | 5)</div><div class='add'>+#define PINMUX_GPIO81__FUNC_TSFDC_TSSEL0 (MTK_PIN_NO(81) | 6)</div><div class='add'>+#define PINMUX_GPIO81__FUNC_SSPM_JTAG_TRSTN_VCORE (MTK_PIN_NO(81) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0)</div><div class='add'>+#define PINMUX_GPIO82__FUNC_MSDC1_DAT3 (MTK_PIN_NO(82) | 1)</div><div class='add'>+#define PINMUX_GPIO82__FUNC_CONN_BGF_MCU_AICE_TMSC (MTK_PIN_NO(82) | 3)</div><div class='add'>+#define PINMUX_GPIO82__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(82) | 4)</div><div class='add'>+#define PINMUX_GPIO82__FUNC_MIPI3_D_SCLK (MTK_PIN_NO(82) | 5)</div><div class='add'>+#define PINMUX_GPIO82__FUNC_TSFDC_RCK_SELB (MTK_PIN_NO(82) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0)</div><div class='add'>+#define PINMUX_GPIO83__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(83) | 1)</div><div class='add'>+#define PINMUX_GPIO83__FUNC_TSFDC_26M (MTK_PIN_NO(83) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0)</div><div class='add'>+#define PINMUX_GPIO84__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(84) | 1)</div><div class='add'>+#define PINMUX_GPIO84__FUNC_SPM_JTAG_TCK_VCORE (MTK_PIN_NO(84) | 3)</div><div class='add'>+#define PINMUX_GPIO84__FUNC_APU_JTAG_TCK (MTK_PIN_NO(84) | 4)</div><div class='add'>+#define PINMUX_GPIO84__FUNC_TSFDC_SDO (MTK_PIN_NO(84) | 6)</div><div class='add'>+#define PINMUX_GPIO84__FUNC_CONN_DSP_L5_JCK (MTK_PIN_NO(84) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0)</div><div class='add'>+#define PINMUX_GPIO85__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(85) | 1)</div><div class='add'>+#define PINMUX_GPIO85__FUNC_SPM_JTAG_TRSTN_VCORE (MTK_PIN_NO(85) | 3)</div><div class='add'>+#define PINMUX_GPIO85__FUNC_APU_JTAG_TRST (MTK_PIN_NO(85) | 4)</div><div class='add'>+#define PINMUX_GPIO85__FUNC_TSFDC_FOUT (MTK_PIN_NO(85) | 6)</div><div class='add'>+#define PINMUX_GPIO85__FUNC_CONN_DSP_L5_JINTP (MTK_PIN_NO(85) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0)</div><div class='add'>+#define PINMUX_GPIO86__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(86) | 1)</div><div class='add'>+#define PINMUX_GPIO86__FUNC_SPM_JTAG_TDI_VCORE (MTK_PIN_NO(86) | 3)</div><div class='add'>+#define PINMUX_GPIO86__FUNC_APU_JTAG_TDI (MTK_PIN_NO(86) | 4)</div><div class='add'>+#define PINMUX_GPIO86__FUNC_TSFDC_SCK (MTK_PIN_NO(86) | 6)</div><div class='add'>+#define PINMUX_GPIO86__FUNC_CONN_DSP_L5_JDI (MTK_PIN_NO(86) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0)</div><div class='add'>+#define PINMUX_GPIO87__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(87) | 1)</div><div class='add'>+#define PINMUX_GPIO87__FUNC_SPM_JTAG_TMS_VCORE (MTK_PIN_NO(87) | 3)</div><div class='add'>+#define PINMUX_GPIO87__FUNC_APU_JTAG_TMS (MTK_PIN_NO(87) | 4)</div><div class='add'>+#define PINMUX_GPIO87__FUNC_TSFDC_SDI (MTK_PIN_NO(87) | 6)</div><div class='add'>+#define PINMUX_GPIO87__FUNC_CONN_DSP_L5_JMS (MTK_PIN_NO(87) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0)</div><div class='add'>+#define PINMUX_GPIO88__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(88) | 1)</div><div class='add'>+#define PINMUX_GPIO88__FUNC_SPM_JTAG_TDO_VCORE (MTK_PIN_NO(88) | 3)</div><div class='add'>+#define PINMUX_GPIO88__FUNC_APU_JTAG_TDO (MTK_PIN_NO(88) | 4)</div><div class='add'>+#define PINMUX_GPIO88__FUNC_TSFDC_SCF (MTK_PIN_NO(88) | 6)</div><div class='add'>+#define PINMUX_GPIO88__FUNC_CONN_DSP_L5_JDO (MTK_PIN_NO(88) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0)</div><div class='add'>+#define PINMUX_GPIO89__FUNC_DSI_TE (MTK_PIN_NO(89) | 1)</div><div class='add'>+#define PINMUX_GPIO89__FUNC_DBG_MON_B8 (MTK_PIN_NO(89) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0)</div><div class='add'>+#define PINMUX_GPIO90__FUNC_LCM_RST (MTK_PIN_NO(90) | 1)</div><div class='add'>+#define PINMUX_GPIO90__FUNC_DBG_MON_B9 (MTK_PIN_NO(90) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0)</div><div class='add'>+#define PINMUX_GPIO91__FUNC_DISP_PWM (MTK_PIN_NO(91) | 1)</div><div class='add'>+#define PINMUX_GPIO91__FUNC_DBG_MON_B10 (MTK_PIN_NO(91) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0)</div><div class='add'>+#define PINMUX_GPIO92__FUNC_CMMCLK0 (MTK_PIN_NO(92) | 1)</div><div class='add'>+#define PINMUX_GPIO92__FUNC_DBG_MON_A23 (MTK_PIN_NO(92) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0)</div><div class='add'>+#define PINMUX_GPIO93__FUNC_CMMCLK1 (MTK_PIN_NO(93) | 1)</div><div class='add'>+#define PINMUX_GPIO93__FUNC_DBG_MON_A24 (MTK_PIN_NO(93) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0)</div><div class='add'>+#define PINMUX_GPIO94__FUNC_CMMCLK2 (MTK_PIN_NO(94) | 1)</div><div class='add'>+#define PINMUX_GPIO94__FUNC_DBG_MON_A25 (MTK_PIN_NO(94) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0)</div><div class='add'>+#define PINMUX_GPIO95__FUNC_CMMCLK3 (MTK_PIN_NO(95) | 1)</div><div class='add'>+#define PINMUX_GPIO95__FUNC_MD32_1_TXD (MTK_PIN_NO(95) | 5)</div><div class='add'>+#define PINMUX_GPIO95__FUNC_PTA_TXD (MTK_PIN_NO(95) | 6)</div><div class='add'>+#define PINMUX_GPIO95__FUNC_DBG_MON_A26 (MTK_PIN_NO(95) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0)</div><div class='add'>+#define PINMUX_GPIO96__FUNC_CMMCLK4 (MTK_PIN_NO(96) | 1)</div><div class='add'>+#define PINMUX_GPIO96__FUNC_MD32_1_RXD (MTK_PIN_NO(96) | 5)</div><div class='add'>+#define PINMUX_GPIO96__FUNC_PTA_RXD (MTK_PIN_NO(96) | 6)</div><div class='add'>+#define PINMUX_GPIO96__FUNC_DBG_MON_A27 (MTK_PIN_NO(96) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0)</div><div class='add'>+#define PINMUX_GPIO97__FUNC_MD_UCNT_A_TGL (MTK_PIN_NO(97) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0)</div><div class='add'>+#define PINMUX_GPIO98__FUNC_DIGRF_IRQ (MTK_PIN_NO(98) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0)</div><div class='add'>+#define PINMUX_GPIO99__FUNC_BPI_BUS0 (MTK_PIN_NO(99) | 1)</div><div class='add'>+#define PINMUX_GPIO99__FUNC_MFG_TSFDC_EN (MTK_PIN_NO(99) | 4)</div><div class='add'>+#define PINMUX_GPIO99__FUNC_ANT_SEL0 (MTK_PIN_NO(99) | 6)</div><div class='add'>+#define PINMUX_GPIO99__FUNC_DBG_MON_B11 (MTK_PIN_NO(99) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0)</div><div class='add'>+#define PINMUX_GPIO100__FUNC_BPI_BUS1 (MTK_PIN_NO(100) | 1)</div><div class='add'>+#define PINMUX_GPIO100__FUNC_MFG_TSFDC_VCO_RST (MTK_PIN_NO(100) | 4)</div><div class='add'>+#define PINMUX_GPIO100__FUNC_ANT_SEL1 (MTK_PIN_NO(100) | 6)</div><div class='add'>+#define PINMUX_GPIO100__FUNC_DBG_MON_B12 (MTK_PIN_NO(100) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0)</div><div class='add'>+#define PINMUX_GPIO101__FUNC_BPI_BUS2 (MTK_PIN_NO(101) | 1)</div><div class='add'>+#define PINMUX_GPIO101__FUNC_DMIC1_CLK (MTK_PIN_NO(101) | 3)</div><div class='add'>+#define PINMUX_GPIO101__FUNC_MFG_TSFDC_TSSEL2 (MTK_PIN_NO(101) | 4)</div><div class='add'>+#define PINMUX_GPIO101__FUNC_ANT_SEL2 (MTK_PIN_NO(101) | 6)</div><div class='add'>+#define PINMUX_GPIO101__FUNC_DBG_MON_B13 (MTK_PIN_NO(101) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0)</div><div class='add'>+#define PINMUX_GPIO102__FUNC_BPI_BUS3 (MTK_PIN_NO(102) | 1)</div><div class='add'>+#define PINMUX_GPIO102__FUNC_DMIC1_DAT (MTK_PIN_NO(102) | 3)</div><div class='add'>+#define PINMUX_GPIO102__FUNC_MFG_TSFDC_TSSEL1 (MTK_PIN_NO(102) | 4)</div><div class='add'>+#define PINMUX_GPIO102__FUNC_ANT_SEL3 (MTK_PIN_NO(102) | 6)</div><div class='add'>+#define PINMUX_GPIO102__FUNC_DBG_MON_B14 (MTK_PIN_NO(102) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0)</div><div class='add'>+#define PINMUX_GPIO103__FUNC_BPI_BUS4 (MTK_PIN_NO(103) | 1)</div><div class='add'>+#define PINMUX_GPIO103__FUNC_MFG_TSFDC_TSSEL0 (MTK_PIN_NO(103) | 4)</div><div class='add'>+#define PINMUX_GPIO103__FUNC_ANT_SEL4 (MTK_PIN_NO(103) | 6)</div><div class='add'>+#define PINMUX_GPIO103__FUNC_DBG_MON_B15 (MTK_PIN_NO(103) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0)</div><div class='add'>+#define PINMUX_GPIO104__FUNC_BPI_BUS5 (MTK_PIN_NO(104) | 1)</div><div class='add'>+#define PINMUX_GPIO104__FUNC_MFG_TSFDC_RCK_SELB (MTK_PIN_NO(104) | 4)</div><div class='add'>+#define PINMUX_GPIO104__FUNC_ANT_SEL5 (MTK_PIN_NO(104) | 6)</div><div class='add'>+#define PINMUX_GPIO104__FUNC_DBG_MON_B16 (MTK_PIN_NO(104) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0)</div><div class='add'>+#define PINMUX_GPIO105__FUNC_BPI_BUS6 (MTK_PIN_NO(105) | 1)</div><div class='add'>+#define PINMUX_GPIO105__FUNC_CONN_BPI_BUS6 (MTK_PIN_NO(105) | 2)</div><div class='add'>+#define PINMUX_GPIO105__FUNC_ANT_SEL6 (MTK_PIN_NO(105) | 6)</div><div class='add'>+#define PINMUX_GPIO105__FUNC_DBG_MON_B17 (MTK_PIN_NO(105) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0)</div><div class='add'>+#define PINMUX_GPIO106__FUNC_BPI_BUS7 (MTK_PIN_NO(106) | 1)</div><div class='add'>+#define PINMUX_GPIO106__FUNC_CONN_BPI_BUS7 (MTK_PIN_NO(106) | 2)</div><div class='add'>+#define PINMUX_GPIO106__FUNC_MFG_TSFDC_SDO (MTK_PIN_NO(106) | 4)</div><div class='add'>+#define PINMUX_GPIO106__FUNC_AUD_DAC_26M_CLK (MTK_PIN_NO(106) | 5)</div><div class='add'>+#define PINMUX_GPIO106__FUNC_ANT_SEL7 (MTK_PIN_NO(106) | 6)</div><div class='add'>+#define PINMUX_GPIO106__FUNC_DBG_MON_B18 (MTK_PIN_NO(106) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0)</div><div class='add'>+#define PINMUX_GPIO107__FUNC_BPI_BUS8 (MTK_PIN_NO(107) | 1)</div><div class='add'>+#define PINMUX_GPIO107__FUNC_CONN_BPI_BUS8 (MTK_PIN_NO(107) | 2)</div><div class='add'>+#define PINMUX_GPIO107__FUNC_MFG_TSFDC_FOUT (MTK_PIN_NO(107) | 4)</div><div class='add'>+#define PINMUX_GPIO107__FUNC_I2SOUT4_DATA0 (MTK_PIN_NO(107) | 5)</div><div class='add'>+#define PINMUX_GPIO107__FUNC_ANT_SEL8 (MTK_PIN_NO(107) | 6)</div><div class='add'>+#define PINMUX_GPIO107__FUNC_DBG_MON_B19 (MTK_PIN_NO(107) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0)</div><div class='add'>+#define PINMUX_GPIO108__FUNC_BPI_BUS9 (MTK_PIN_NO(108) | 1)</div><div class='add'>+#define PINMUX_GPIO108__FUNC_CONN_BPI_BUS9 (MTK_PIN_NO(108) | 2)</div><div class='add'>+#define PINMUX_GPIO108__FUNC_I2SOUT4_DATA1 (MTK_PIN_NO(108) | 5)</div><div class='add'>+#define PINMUX_GPIO108__FUNC_ANT_SEL9 (MTK_PIN_NO(108) | 6)</div><div class='add'>+#define PINMUX_GPIO108__FUNC_DBG_MON_B20 (MTK_PIN_NO(108) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0)</div><div class='add'>+#define PINMUX_GPIO109__FUNC_BPI_BUS10 (MTK_PIN_NO(109) | 1)</div><div class='add'>+#define PINMUX_GPIO109__FUNC_CONN_BPI_BUS10 (MTK_PIN_NO(109) | 2)</div><div class='add'>+#define PINMUX_GPIO109__FUNC_I2SOUT4_DATA2 (MTK_PIN_NO(109) | 5)</div><div class='add'>+#define PINMUX_GPIO109__FUNC_ANT_SEL10 (MTK_PIN_NO(109) | 6)</div><div class='add'>+#define PINMUX_GPIO109__FUNC_DBG_MON_B21 (MTK_PIN_NO(109) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0)</div><div class='add'>+#define PINMUX_GPIO110__FUNC_BPI_BUS11 (MTK_PIN_NO(110) | 1)</div><div class='add'>+#define PINMUX_GPIO110__FUNC_CONN_BPI_BUS11_OLAT0 (MTK_PIN_NO(110) | 2)</div><div class='add'>+#define PINMUX_GPIO110__FUNC_I2SOUT4_DATA3 (MTK_PIN_NO(110) | 5)</div><div class='add'>+#define PINMUX_GPIO110__FUNC_ANT_SEL11 (MTK_PIN_NO(110) | 6)</div><div class='add'>+#define PINMUX_GPIO110__FUNC_DBG_MON_B22 (MTK_PIN_NO(110) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0)</div><div class='add'>+#define PINMUX_GPIO111__FUNC_BPI_BUS12 (MTK_PIN_NO(111) | 1)</div><div class='add'>+#define PINMUX_GPIO111__FUNC_CONN_BPI_BUS12_OLAT1 (MTK_PIN_NO(111) | 2)</div><div class='add'>+#define PINMUX_GPIO111__FUNC_CLKM0 (MTK_PIN_NO(111) | 3)</div><div class='add'>+#define PINMUX_GPIO111__FUNC_I2SIN4_BCK (MTK_PIN_NO(111) | 5)</div><div class='add'>+#define PINMUX_GPIO111__FUNC_ANT_SEL12 (MTK_PIN_NO(111) | 6)</div><div class='add'>+#define PINMUX_GPIO111__FUNC_DBG_MON_B23 (MTK_PIN_NO(111) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0)</div><div class='add'>+#define PINMUX_GPIO112__FUNC_BPI_BUS13 (MTK_PIN_NO(112) | 1)</div><div class='add'>+#define PINMUX_GPIO112__FUNC_CONN_BPI_BUS13_OLAT2 (MTK_PIN_NO(112) | 2)</div><div class='add'>+#define PINMUX_GPIO112__FUNC_CLKM1 (MTK_PIN_NO(112) | 3)</div><div class='add'>+#define PINMUX_GPIO112__FUNC_I2SIN4_DATA0 (MTK_PIN_NO(112) | 5)</div><div class='add'>+#define PINMUX_GPIO112__FUNC_ANT_SEL13 (MTK_PIN_NO(112) | 6)</div><div class='add'>+#define PINMUX_GPIO112__FUNC_DBG_MON_B24 (MTK_PIN_NO(112) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0)</div><div class='add'>+#define PINMUX_GPIO113__FUNC_BPI_BUS14 (MTK_PIN_NO(113) | 1)</div><div class='add'>+#define PINMUX_GPIO113__FUNC_CONN_BPI_BUS14_OLAT3 (MTK_PIN_NO(113) | 2)</div><div class='add'>+#define PINMUX_GPIO113__FUNC_CLKM2 (MTK_PIN_NO(113) | 3)</div><div class='add'>+#define PINMUX_GPIO113__FUNC_I2SIN4_DATA1 (MTK_PIN_NO(113) | 5)</div><div class='add'>+#define PINMUX_GPIO113__FUNC_ANT_SEL14 (MTK_PIN_NO(113) | 6)</div><div class='add'>+#define PINMUX_GPIO113__FUNC_DBG_MON_B25 (MTK_PIN_NO(113) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0)</div><div class='add'>+#define PINMUX_GPIO114__FUNC_BPI_BUS15 (MTK_PIN_NO(114) | 1)</div><div class='add'>+#define PINMUX_GPIO114__FUNC_CONN_BPI_BUS15_OLAT4 (MTK_PIN_NO(114) | 2)</div><div class='add'>+#define PINMUX_GPIO114__FUNC_CLKM3 (MTK_PIN_NO(114) | 3)</div><div class='add'>+#define PINMUX_GPIO114__FUNC_I2SIN4_DATA2 (MTK_PIN_NO(114) | 5)</div><div class='add'>+#define PINMUX_GPIO114__FUNC_ANT_SEL15 (MTK_PIN_NO(114) | 6)</div><div class='add'>+#define PINMUX_GPIO114__FUNC_DBG_MON_B26 (MTK_PIN_NO(114) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0)</div><div class='add'>+#define PINMUX_GPIO115__FUNC_BPI_BUS16 (MTK_PIN_NO(115) | 1)</div><div class='add'>+#define PINMUX_GPIO115__FUNC_CONN_BPI_BUS16_OLAT5 (MTK_PIN_NO(115) | 2)</div><div class='add'>+#define PINMUX_GPIO115__FUNC_I2SIN4_DATA3 (MTK_PIN_NO(115) | 5)</div><div class='add'>+#define PINMUX_GPIO115__FUNC_ANT_SEL16 (MTK_PIN_NO(115) | 6)</div><div class='add'>+#define PINMUX_GPIO115__FUNC_DBG_MON_B27 (MTK_PIN_NO(115) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0)</div><div class='add'>+#define PINMUX_GPIO116__FUNC_BPI_BUS17 (MTK_PIN_NO(116) | 1)</div><div class='add'>+#define PINMUX_GPIO116__FUNC_CONN_BPI_BUS17_ANT0 (MTK_PIN_NO(116) | 2)</div><div class='add'>+#define PINMUX_GPIO116__FUNC_I2SIN4_LRCK (MTK_PIN_NO(116) | 5)</div><div class='add'>+#define PINMUX_GPIO116__FUNC_ANT_SEL17 (MTK_PIN_NO(116) | 6)</div><div class='add'>+#define PINMUX_GPIO116__FUNC_DBG_MON_B28 (MTK_PIN_NO(116) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0)</div><div class='add'>+#define PINMUX_GPIO117__FUNC_MIPI0_D_SCLK (MTK_PIN_NO(117) | 1)</div><div class='add'>+#define PINMUX_GPIO117__FUNC_CONN_MIPI0_SCLK (MTK_PIN_NO(117) | 2)</div><div class='add'>+#define PINMUX_GPIO117__FUNC_BPI_BUS18 (MTK_PIN_NO(117) | 3)</div><div class='add'>+#define PINMUX_GPIO117__FUNC_ANT_SEL18 (MTK_PIN_NO(117) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0)</div><div class='add'>+#define PINMUX_GPIO118__FUNC_MIPI0_D_SDATA (MTK_PIN_NO(118) | 1)</div><div class='add'>+#define PINMUX_GPIO118__FUNC_CONN_MIPI0_SDATA (MTK_PIN_NO(118) | 2)</div><div class='add'>+#define PINMUX_GPIO118__FUNC_BPI_BUS19 (MTK_PIN_NO(118) | 3)</div><div class='add'>+#define PINMUX_GPIO118__FUNC_ANT_SEL19 (MTK_PIN_NO(118) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0)</div><div class='add'>+#define PINMUX_GPIO119__FUNC_MIPI1_D_SCLK (MTK_PIN_NO(119) | 1)</div><div class='add'>+#define PINMUX_GPIO119__FUNC_CONN_MIPI1_SCLK (MTK_PIN_NO(119) | 2)</div><div class='add'>+#define PINMUX_GPIO119__FUNC_BPI_BUS20 (MTK_PIN_NO(119) | 3)</div><div class='add'>+#define PINMUX_GPIO119__FUNC_ANT_SEL20 (MTK_PIN_NO(119) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0)</div><div class='add'>+#define PINMUX_GPIO120__FUNC_MIPI1_D_SDATA (MTK_PIN_NO(120) | 1)</div><div class='add'>+#define PINMUX_GPIO120__FUNC_CONN_MIPI1_SDATA (MTK_PIN_NO(120) | 2)</div><div class='add'>+#define PINMUX_GPIO120__FUNC_BPI_BUS21 (MTK_PIN_NO(120) | 3)</div><div class='add'>+#define PINMUX_GPIO120__FUNC_ANT_SEL21 (MTK_PIN_NO(120) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0)</div><div class='add'>+#define PINMUX_GPIO121__FUNC_MIPI2_D_SCLK (MTK_PIN_NO(121) | 1)</div><div class='add'>+#define PINMUX_GPIO121__FUNC_MIPI4_D_SCLK (MTK_PIN_NO(121) | 2)</div><div class='add'>+#define PINMUX_GPIO121__FUNC_BPI_BUS22 (MTK_PIN_NO(121) | 3)</div><div class='add'>+#define PINMUX_GPIO121__FUNC_MD_GPS_L1_BLANK (MTK_PIN_NO(121) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0)</div><div class='add'>+#define PINMUX_GPIO122__FUNC_MIPI2_D_SDATA (MTK_PIN_NO(122) | 1)</div><div class='add'>+#define PINMUX_GPIO122__FUNC_MIPI4_D_SDATA (MTK_PIN_NO(122) | 2)</div><div class='add'>+#define PINMUX_GPIO122__FUNC_BPI_BUS23 (MTK_PIN_NO(122) | 3)</div><div class='add'>+#define PINMUX_GPIO122__FUNC_MD_GPS_L5_BLANK (MTK_PIN_NO(122) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0)</div><div class='add'>+#define PINMUX_GPIO123__FUNC_MIPI_M_SCLK (MTK_PIN_NO(123) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0)</div><div class='add'>+#define PINMUX_GPIO124__FUNC_MIPI_M_SDATA (MTK_PIN_NO(124) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0)</div><div class='add'>+#define PINMUX_GPIO125__FUNC_SCL0 (MTK_PIN_NO(125) | 1)</div><div class='add'>+#define PINMUX_GPIO125__FUNC_SCP_SCL4 (MTK_PIN_NO(125) | 2)</div><div class='add'>+#define PINMUX_GPIO125__FUNC_TP_UTXD2_VLP (MTK_PIN_NO(125) | 3)</div><div class='add'>+#define PINMUX_GPIO125__FUNC_TP_UCTS1_VLP (MTK_PIN_NO(125) | 4)</div><div class='add'>+#define PINMUX_GPIO125__FUNC_TP_GPIO4_AO (MTK_PIN_NO(125) | 5)</div><div class='add'>+#define PINMUX_GPIO125__FUNC_UTXD2 (MTK_PIN_NO(125) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0)</div><div class='add'>+#define PINMUX_GPIO126__FUNC_SDA0 (MTK_PIN_NO(126) | 1)</div><div class='add'>+#define PINMUX_GPIO126__FUNC_SCP_SDA4 (MTK_PIN_NO(126) | 2)</div><div class='add'>+#define PINMUX_GPIO126__FUNC_TP_URXD2_VLP (MTK_PIN_NO(126) | 3)</div><div class='add'>+#define PINMUX_GPIO126__FUNC_TP_URTS1_VLP (MTK_PIN_NO(126) | 4)</div><div class='add'>+#define PINMUX_GPIO126__FUNC_TP_GPIO5_AO (MTK_PIN_NO(126) | 5)</div><div class='add'>+#define PINMUX_GPIO126__FUNC_URXD2 (MTK_PIN_NO(126) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0)</div><div class='add'>+#define PINMUX_GPIO127__FUNC_SCL1 (MTK_PIN_NO(127) | 1)</div><div class='add'>+#define PINMUX_GPIO127__FUNC_SCP_SCL5 (MTK_PIN_NO(127) | 2)</div><div class='add'>+#define PINMUX_GPIO127__FUNC_TP_UCTS2_VLP (MTK_PIN_NO(127) | 3)</div><div class='add'>+#define PINMUX_GPIO127__FUNC_TP_UTXD1_VLP (MTK_PIN_NO(127) | 4)</div><div class='add'>+#define PINMUX_GPIO127__FUNC_TP_GPIO6_AO (MTK_PIN_NO(127) | 5)</div><div class='add'>+#define PINMUX_GPIO127__FUNC_MD_MCIF_UTXD0 (MTK_PIN_NO(127) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0)</div><div class='add'>+#define PINMUX_GPIO128__FUNC_SDA1 (MTK_PIN_NO(128) | 1)</div><div class='add'>+#define PINMUX_GPIO128__FUNC_SCP_SDA5 (MTK_PIN_NO(128) | 2)</div><div class='add'>+#define PINMUX_GPIO128__FUNC_TP_URTS2_VLP (MTK_PIN_NO(128) | 3)</div><div class='add'>+#define PINMUX_GPIO128__FUNC_TP_URXD1_VLP (MTK_PIN_NO(128) | 4)</div><div class='add'>+#define PINMUX_GPIO128__FUNC_TP_GPIO7_AO (MTK_PIN_NO(128) | 5)</div><div class='add'>+#define PINMUX_GPIO128__FUNC_MD_MCIF_URXD0 (MTK_PIN_NO(128) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0)</div><div class='add'>+#define PINMUX_GPIO129__FUNC_SCL2 (MTK_PIN_NO(129) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0)</div><div class='add'>+#define PINMUX_GPIO130__FUNC_SDA2 (MTK_PIN_NO(130) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0)</div><div class='add'>+#define PINMUX_GPIO131__FUNC_SCL3 (MTK_PIN_NO(131) | 1)</div><div class='add'>+#define PINMUX_GPIO131__FUNC_TP_UTXD2_VCORE (MTK_PIN_NO(131) | 3)</div><div class='add'>+#define PINMUX_GPIO131__FUNC_SSPM_UTXD_AO_VCORE (MTK_PIN_NO(131) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0)</div><div class='add'>+#define PINMUX_GPIO132__FUNC_SDA3 (MTK_PIN_NO(132) | 1)</div><div class='add'>+#define PINMUX_GPIO132__FUNC_TP_URXD2_VCORE (MTK_PIN_NO(132) | 3)</div><div class='add'>+#define PINMUX_GPIO132__FUNC_SSPM_URXD_AO_VCORE (MTK_PIN_NO(132) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0)</div><div class='add'>+#define PINMUX_GPIO133__FUNC_SCL4 (MTK_PIN_NO(133) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0)</div><div class='add'>+#define PINMUX_GPIO134__FUNC_SDA4 (MTK_PIN_NO(134) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0)</div><div class='add'>+#define PINMUX_GPIO135__FUNC_SCL5 (MTK_PIN_NO(135) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0)</div><div class='add'>+#define PINMUX_GPIO136__FUNC_SDA5 (MTK_PIN_NO(136) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0)</div><div class='add'>+#define PINMUX_GPIO137__FUNC_SCL6 (MTK_PIN_NO(137) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0)</div><div class='add'>+#define PINMUX_GPIO138__FUNC_SDA6 (MTK_PIN_NO(138) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0)</div><div class='add'>+#define PINMUX_GPIO139__FUNC_SCL7 (MTK_PIN_NO(139) | 1)</div><div class='add'>+#define PINMUX_GPIO139__FUNC_TP_UTXD1_VCORE (MTK_PIN_NO(139) | 3)</div><div class='add'>+#define PINMUX_GPIO139__FUNC_MD_UTXD0 (MTK_PIN_NO(139) | 4)</div><div class='add'>+#define PINMUX_GPIO139__FUNC_UTXD1 (MTK_PIN_NO(139) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0)</div><div class='add'>+#define PINMUX_GPIO140__FUNC_SDA7 (MTK_PIN_NO(140) | 1)</div><div class='add'>+#define PINMUX_GPIO140__FUNC_TP_URXD1_VCORE (MTK_PIN_NO(140) | 3)</div><div class='add'>+#define PINMUX_GPIO140__FUNC_MD_URXD0 (MTK_PIN_NO(140) | 4)</div><div class='add'>+#define PINMUX_GPIO140__FUNC_URXD1 (MTK_PIN_NO(140) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0)</div><div class='add'>+#define PINMUX_GPIO141__FUNC_SCL8 (MTK_PIN_NO(141) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0)</div><div class='add'>+#define PINMUX_GPIO142__FUNC_SDA8 (MTK_PIN_NO(142) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0)</div><div class='add'>+#define PINMUX_GPIO143__FUNC_SCL9 (MTK_PIN_NO(143) | 1)</div><div class='add'>+#define PINMUX_GPIO143__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(143) | 2)</div><div class='add'>+#define PINMUX_GPIO143__FUNC_HFRP_UTXD1 (MTK_PIN_NO(143) | 3)</div><div class='add'>+#define PINMUX_GPIO143__FUNC_CONN_BGF_MCU_AICE_TMSC (MTK_PIN_NO(143) | 4)</div><div class='add'>+#define PINMUX_GPIO143__FUNC_CONN_WF_MCU_AICE_TMSC (MTK_PIN_NO(143) | 5)</div><div class='add'>+#define PINMUX_GPIO143__FUNC_MBISTREADEN_TRIGGER (MTK_PIN_NO(143) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0)</div><div class='add'>+#define PINMUX_GPIO144__FUNC_SDA9 (MTK_PIN_NO(144) | 1)</div><div class='add'>+#define PINMUX_GPIO144__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(144) | 2)</div><div class='add'>+#define PINMUX_GPIO144__FUNC_HFRP_URXD1 (MTK_PIN_NO(144) | 3)</div><div class='add'>+#define PINMUX_GPIO144__FUNC_CONN_BGF_MCU_AICE_TCKC (MTK_PIN_NO(144) | 4)</div><div class='add'>+#define PINMUX_GPIO144__FUNC_CONN_WF_MCU_AICE_TCKC (MTK_PIN_NO(144) | 5)</div><div class='add'>+#define PINMUX_GPIO144__FUNC_MBISTWRITEEN_TRIGGER (MTK_PIN_NO(144) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0)</div><div class='add'>+#define PINMUX_GPIO145__FUNC_SCL10 (MTK_PIN_NO(145) | 1)</div><div class='add'>+#define PINMUX_GPIO145__FUNC_SCP_SCL0 (MTK_PIN_NO(145) | 2)</div><div class='add'>+#define PINMUX_GPIO145__FUNC_TP_GPIO8_AO (MTK_PIN_NO(145) | 5)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0)</div><div class='add'>+#define PINMUX_GPIO146__FUNC_SDA10 (MTK_PIN_NO(146) | 1)</div><div class='add'>+#define PINMUX_GPIO146__FUNC_SCP_SDA0 (MTK_PIN_NO(146) | 2)</div><div class='add'>+#define PINMUX_GPIO146__FUNC_TP_GPIO9_AO (MTK_PIN_NO(146) | 5)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0)</div><div class='add'>+#define PINMUX_GPIO147__FUNC_SCL11 (MTK_PIN_NO(147) | 1)</div><div class='add'>+#define PINMUX_GPIO147__FUNC_SCP_SCL1 (MTK_PIN_NO(147) | 2)</div><div class='add'>+#define PINMUX_GPIO147__FUNC_SCP_DMIC_CLK (MTK_PIN_NO(147) | 3)</div><div class='add'>+#define PINMUX_GPIO147__FUNC_DMIC_CLK (MTK_PIN_NO(147) | 4)</div><div class='add'>+#define PINMUX_GPIO147__FUNC_TP_GPIO10_AO (MTK_PIN_NO(147) | 5)</div><div class='add'>+#define PINMUX_GPIO147__FUNC_EXTIF0_PRI (MTK_PIN_NO(147) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0)</div><div class='add'>+#define PINMUX_GPIO148__FUNC_SDA11 (MTK_PIN_NO(148) | 1)</div><div class='add'>+#define PINMUX_GPIO148__FUNC_SCP_SDA1 (MTK_PIN_NO(148) | 2)</div><div class='add'>+#define PINMUX_GPIO148__FUNC_SCP_DMIC_DAT (MTK_PIN_NO(148) | 3)</div><div class='add'>+#define PINMUX_GPIO148__FUNC_DMIC_DAT (MTK_PIN_NO(148) | 4)</div><div class='add'>+#define PINMUX_GPIO148__FUNC_TP_GPIO11_AO (MTK_PIN_NO(148) | 5)</div><div class='add'>+#define PINMUX_GPIO148__FUNC_EXTIF0_GNT_B (MTK_PIN_NO(148) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0)</div><div class='add'>+#define PINMUX_GPIO149__FUNC_KPROW2 (MTK_PIN_NO(149) | 1)</div><div class='add'>+#define PINMUX_GPIO149__FUNC_PWM_VLP (MTK_PIN_NO(149) | 2)</div><div class='add'>+#define PINMUX_GPIO149__FUNC_MD_INT0 (MTK_PIN_NO(149) | 4)</div><div class='add'>+#define PINMUX_GPIO149__FUNC_TP_GPIO12_AO (MTK_PIN_NO(149) | 5)</div><div class='add'>+#define PINMUX_GPIO149__FUNC_SCL0 (MTK_PIN_NO(149) | 6)</div><div class='add'>+#define PINMUX_GPIO149__FUNC_DBG_MON_A28 (MTK_PIN_NO(149) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0)</div><div class='add'>+#define PINMUX_GPIO150__FUNC_KPCOL2 (MTK_PIN_NO(150) | 1)</div><div class='add'>+#define PINMUX_GPIO150__FUNC_PWM_VLP (MTK_PIN_NO(150) | 2)</div><div class='add'>+#define PINMUX_GPIO150__FUNC_CMMCLK5 (MTK_PIN_NO(150) | 3)</div><div class='add'>+#define PINMUX_GPIO150__FUNC_MD_INT3 (MTK_PIN_NO(150) | 4)</div><div class='add'>+#define PINMUX_GPIO150__FUNC_TP_GPIO13_AO (MTK_PIN_NO(150) | 5)</div><div class='add'>+#define PINMUX_GPIO150__FUNC_SDA0 (MTK_PIN_NO(150) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0)</div><div class='add'>+#define PINMUX_GPIO151__FUNC_SRCLKENAI0 (MTK_PIN_NO(151) | 1)</div><div class='add'>+#define PINMUX_GPIO151__FUNC_MD_INT4 (MTK_PIN_NO(151) | 4)</div><div class='add'>+#define PINMUX_GPIO151__FUNC_TP_GPIO14_AO (MTK_PIN_NO(151) | 5)</div><div class='add'>+#define PINMUX_GPIO151__FUNC_DBG_MON_A29 (MTK_PIN_NO(151) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0)</div><div class='add'>+#define PINMUX_GPIO152__FUNC_SRCLKENAI1 (MTK_PIN_NO(152) | 1)</div><div class='add'>+#define PINMUX_GPIO152__FUNC_SPMI_M_TRIG_FLAG (MTK_PIN_NO(152) | 4)</div><div class='add'>+#define PINMUX_GPIO152__FUNC_TP_GPIO15_AO (MTK_PIN_NO(152) | 5)</div><div class='add'>+#define PINMUX_GPIO152__FUNC_DBG_MON_A30 (MTK_PIN_NO(152) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0)</div><div class='add'>+#define PINMUX_GPIO153__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(153) | 1)</div><div class='add'>+#define PINMUX_GPIO153__FUNC_DISP_PWM1 (MTK_PIN_NO(153) | 2)</div><div class='add'>+#define PINMUX_GPIO153__FUNC_SPMI_P_TRIG_FLAG (MTK_PIN_NO(153) | 4)</div><div class='add'>+#define PINMUX_GPIO153__FUNC_DBG_MON_A0 (MTK_PIN_NO(153) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0)</div><div class='add'>+#define PINMUX_GPIO154__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(154) | 1)</div><div class='add'>+#define PINMUX_GPIO154__FUNC_LCM_RST1 (MTK_PIN_NO(154) | 2)</div><div class='add'>+#define PINMUX_GPIO154__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(154) | 3)</div><div class='add'>+#define PINMUX_GPIO154__FUNC_CMFLASH2 (MTK_PIN_NO(154) | 4)</div><div class='add'>+#define PINMUX_GPIO154__FUNC_MBISTREADEN_TRIGGER (MTK_PIN_NO(154) | 5)</div><div class='add'>+#define PINMUX_GPIO154__FUNC_DBG_MON_A1 (MTK_PIN_NO(154) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0)</div><div class='add'>+#define PINMUX_GPIO155__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(155) | 1)</div><div class='add'>+#define PINMUX_GPIO155__FUNC_DSI_TE1 (MTK_PIN_NO(155) | 2)</div><div class='add'>+#define PINMUX_GPIO155__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(155) | 3)</div><div class='add'>+#define PINMUX_GPIO155__FUNC_CMFLASH3 (MTK_PIN_NO(155) | 4)</div><div class='add'>+#define PINMUX_GPIO155__FUNC_MBISTWRITEEN_TRIGGER (MTK_PIN_NO(155) | 5)</div><div class='add'>+#define PINMUX_GPIO155__FUNC_DBG_MON_A2 (MTK_PIN_NO(155) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0)</div><div class='add'>+#define PINMUX_GPIO156__FUNC_SPMI_M_SCL (MTK_PIN_NO(156) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0)</div><div class='add'>+#define PINMUX_GPIO157__FUNC_SPMI_M_SDA (MTK_PIN_NO(157) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0)</div><div class='add'>+#define PINMUX_GPIO158__FUNC_SPMI_P_SCL (MTK_PIN_NO(158) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0)</div><div class='add'>+#define PINMUX_GPIO159__FUNC_SPMI_P_SDA (MTK_PIN_NO(159) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0)</div><div class='add'>+#define PINMUX_GPIO160__FUNC_SRCLKENA0 (MTK_PIN_NO(160) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0)</div><div class='add'>+#define PINMUX_GPIO161__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(161) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0)</div><div class='add'>+#define PINMUX_GPIO162__FUNC_RTC32K_CK (MTK_PIN_NO(162) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0)</div><div class='add'>+#define PINMUX_GPIO163__FUNC_WATCHDOG (MTK_PIN_NO(163) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0)</div><div class='add'>+#define PINMUX_GPIO164__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(164) | 1)</div><div class='add'>+#define PINMUX_GPIO164__FUNC_AUD_CLK_MOSI_A (MTK_PIN_NO(164) | 3)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0)</div><div class='add'>+#define PINMUX_GPIO165__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(165) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0)</div><div class='add'>+#define PINMUX_GPIO166__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(166) | 1)</div><div class='add'>+#define PINMUX_GPIO166__FUNC_AUD_DAT_MOSI0_A (MTK_PIN_NO(166) | 3)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0)</div><div class='add'>+#define PINMUX_GPIO167__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(167) | 1)</div><div class='add'>+#define PINMUX_GPIO167__FUNC_AUD_DAT_MOSI1_A (MTK_PIN_NO(167) | 3)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0)</div><div class='add'>+#define PINMUX_GPIO168__FUNC_AUD_NLE_MOSI0 (MTK_PIN_NO(168) | 1)</div><div class='add'>+#define PINMUX_GPIO168__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(168) | 2)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0)</div><div class='add'>+#define PINMUX_GPIO169__FUNC_AUD_NLE_MOSI1 (MTK_PIN_NO(169) | 1)</div><div class='add'>+#define PINMUX_GPIO169__FUNC_AUD_CLK_MISO (MTK_PIN_NO(169) | 2)</div><div class='add'>+#define PINMUX_GPIO169__FUNC_AUD_CLK_MISO_A (MTK_PIN_NO(169) | 3)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0)</div><div class='add'>+#define PINMUX_GPIO170__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(170) | 1)</div><div class='add'>+#define PINMUX_GPIO170__FUNC_VOW_DAT_MISO (MTK_PIN_NO(170) | 2)</div><div class='add'>+#define PINMUX_GPIO170__FUNC_AUD_DAT_MISO0_A (MTK_PIN_NO(170) | 3)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0)</div><div class='add'>+#define PINMUX_GPIO171__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(171) | 1)</div><div class='add'>+#define PINMUX_GPIO171__FUNC_VOW_CLK_MISO (MTK_PIN_NO(171) | 2)</div><div class='add'>+#define PINMUX_GPIO171__FUNC_AUD_DAT_MISO1_A (MTK_PIN_NO(171) | 3)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0)</div><div class='add'>+#define PINMUX_GPIO172__FUNC_CONN_TOP_CLK (MTK_PIN_NO(172) | 1)</div><div class='add'>+#define PINMUX_GPIO172__FUNC_DBG_MON_A31 (MTK_PIN_NO(172) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0)</div><div class='add'>+#define PINMUX_GPIO173__FUNC_CONN_TOP_DATA (MTK_PIN_NO(173) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0)</div><div class='add'>+#define PINMUX_GPIO174__FUNC_CONN_BT_CLK (MTK_PIN_NO(174) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0)</div><div class='add'>+#define PINMUX_GPIO175__FUNC_CONN_BT_DATA (MTK_PIN_NO(175) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0)</div><div class='add'>+#define PINMUX_GPIO176__FUNC_CONN_HRST_B (MTK_PIN_NO(176) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0)</div><div class='add'>+#define PINMUX_GPIO177__FUNC_CONN_WB_PTA (MTK_PIN_NO(177) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0)</div><div class='add'>+#define PINMUX_GPIO178__FUNC_CONN_WF_CTRL0 (MTK_PIN_NO(178) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0)</div><div class='add'>+#define PINMUX_GPIO179__FUNC_CONN_WF_CTRL1 (MTK_PIN_NO(179) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO180__FUNC_GPIO180 (MTK_PIN_NO(180) | 0)</div><div class='add'>+#define PINMUX_GPIO180__FUNC_CONN_WF_CTRL2 (MTK_PIN_NO(180) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO181__FUNC_GPIO181 (MTK_PIN_NO(181) | 0)</div><div class='add'>+#define PINMUX_GPIO181__FUNC_CONN_WF_CTRL3 (MTK_PIN_NO(181) | 1)</div><div class='add'>+#define PINMUX_GPIO181__FUNC_CONN_TOP_CLK_2 (MTK_PIN_NO(181) | 2)</div><div class='add'>+#define PINMUX_GPIO181__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(181) | 3)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO182__FUNC_GPIO182 (MTK_PIN_NO(182) | 0)</div><div class='add'>+#define PINMUX_GPIO182__FUNC_CONN_WF_CTRL4 (MTK_PIN_NO(182) | 1)</div><div class='add'>+#define PINMUX_GPIO182__FUNC_CONN_TOP_DATA_2 (MTK_PIN_NO(182) | 2)</div><div class='add'>+#define PINMUX_GPIO182__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(182) | 3)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO183__FUNC_GPIO183 (MTK_PIN_NO(183) | 0)</div><div class='add'>+#define PINMUX_GPIO183__FUNC_CONN_HRST_B_2 (MTK_PIN_NO(183) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO184__FUNC_GPIO184 (MTK_PIN_NO(184) | 0)</div><div class='add'>+#define PINMUX_GPIO184__FUNC_MSDC0_DSL (MTK_PIN_NO(184) | 1)</div><div class='add'>+#define PINMUX_GPIO184__FUNC_ANT_SEL13 (MTK_PIN_NO(184) | 3)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO185__FUNC_GPIO185 (MTK_PIN_NO(185) | 0)</div><div class='add'>+#define PINMUX_GPIO185__FUNC_MSDC0_CLK (MTK_PIN_NO(185) | 1)</div><div class='add'>+#define PINMUX_GPIO185__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(185) | 2)</div><div class='add'>+#define PINMUX_GPIO185__FUNC_ANT_SEL14 (MTK_PIN_NO(185) | 3)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO186__FUNC_GPIO186 (MTK_PIN_NO(186) | 0)</div><div class='add'>+#define PINMUX_GPIO186__FUNC_MSDC0_CMD (MTK_PIN_NO(186) | 1)</div><div class='add'>+#define PINMUX_GPIO186__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(186) | 2)</div><div class='add'>+#define PINMUX_GPIO186__FUNC_ANT_SEL15 (MTK_PIN_NO(186) | 3)</div><div class='add'>+#define PINMUX_GPIO186__FUNC_I2SOUT4_DATA0 (MTK_PIN_NO(186) | 5)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO187__FUNC_GPIO187 (MTK_PIN_NO(187) | 0)</div><div class='add'>+#define PINMUX_GPIO187__FUNC_MSDC0_RSTB (MTK_PIN_NO(187) | 1)</div><div class='add'>+#define PINMUX_GPIO187__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(187) | 2)</div><div class='add'>+#define PINMUX_GPIO187__FUNC_ANT_SEL16 (MTK_PIN_NO(187) | 3)</div><div class='add'>+#define PINMUX_GPIO187__FUNC_I2SOUT4_DATA1 (MTK_PIN_NO(187) | 5)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO188__FUNC_GPIO188 (MTK_PIN_NO(188) | 0)</div><div class='add'>+#define PINMUX_GPIO188__FUNC_MSDC0_DAT0 (MTK_PIN_NO(188) | 1)</div><div class='add'>+#define PINMUX_GPIO188__FUNC_ANT_SEL17 (MTK_PIN_NO(188) | 3)</div><div class='add'>+#define PINMUX_GPIO188__FUNC_I2SOUT4_DATA2 (MTK_PIN_NO(188) | 5)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO189__FUNC_GPIO189 (MTK_PIN_NO(189) | 0)</div><div class='add'>+#define PINMUX_GPIO189__FUNC_MSDC0_DAT1 (MTK_PIN_NO(189) | 1)</div><div class='add'>+#define PINMUX_GPIO189__FUNC_ANT_SEL18 (MTK_PIN_NO(189) | 3)</div><div class='add'>+#define PINMUX_GPIO189__FUNC_I2SOUT4_DATA3 (MTK_PIN_NO(189) | 5)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO190__FUNC_GPIO190 (MTK_PIN_NO(190) | 0)</div><div class='add'>+#define PINMUX_GPIO190__FUNC_MSDC0_DAT2 (MTK_PIN_NO(190) | 1)</div><div class='add'>+#define PINMUX_GPIO190__FUNC_DMIC1_CLK (MTK_PIN_NO(190) | 2)</div><div class='add'>+#define PINMUX_GPIO190__FUNC_ANT_SEL19 (MTK_PIN_NO(190) | 3)</div><div class='add'>+#define PINMUX_GPIO190__FUNC_I2SIN4_BCK (MTK_PIN_NO(190) | 5)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO191__FUNC_GPIO191 (MTK_PIN_NO(191) | 0)</div><div class='add'>+#define PINMUX_GPIO191__FUNC_MSDC0_DAT3 (MTK_PIN_NO(191) | 1)</div><div class='add'>+#define PINMUX_GPIO191__FUNC_DMIC1_DAT (MTK_PIN_NO(191) | 2)</div><div class='add'>+#define PINMUX_GPIO191__FUNC_ANT_SEL20 (MTK_PIN_NO(191) | 3)</div><div class='add'>+#define PINMUX_GPIO191__FUNC_I2SIN4_DATA0 (MTK_PIN_NO(191) | 5)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO192__FUNC_GPIO192 (MTK_PIN_NO(192) | 0)</div><div class='add'>+#define PINMUX_GPIO192__FUNC_MSDC0_DAT4 (MTK_PIN_NO(192) | 1)</div><div class='add'>+#define PINMUX_GPIO192__FUNC_IDDIG (MTK_PIN_NO(192) | 2)</div><div class='add'>+#define PINMUX_GPIO192__FUNC_ANT_SEL21 (MTK_PIN_NO(192) | 3)</div><div class='add'>+#define PINMUX_GPIO192__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(192) | 4)</div><div class='add'>+#define PINMUX_GPIO192__FUNC_I2SIN4_DATA1 (MTK_PIN_NO(192) | 5)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO193__FUNC_GPIO193 (MTK_PIN_NO(193) | 0)</div><div class='add'>+#define PINMUX_GPIO193__FUNC_MSDC0_DAT5 (MTK_PIN_NO(193) | 1)</div><div class='add'>+#define PINMUX_GPIO193__FUNC_USB_DRVVBUS (MTK_PIN_NO(193) | 2)</div><div class='add'>+#define PINMUX_GPIO193__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(193) | 4)</div><div class='add'>+#define PINMUX_GPIO193__FUNC_I2SIN4_DATA2 (MTK_PIN_NO(193) | 5)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO194__FUNC_GPIO194 (MTK_PIN_NO(194) | 0)</div><div class='add'>+#define PINMUX_GPIO194__FUNC_MSDC0_DAT6 (MTK_PIN_NO(194) | 1)</div><div class='add'>+#define PINMUX_GPIO194__FUNC_VBUSVALID (MTK_PIN_NO(194) | 2)</div><div class='add'>+#define PINMUX_GPIO194__FUNC_I2SIN4_DATA3 (MTK_PIN_NO(194) | 5)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO195__FUNC_GPIO195 (MTK_PIN_NO(195) | 0)</div><div class='add'>+#define PINMUX_GPIO195__FUNC_MSDC0_DAT7 (MTK_PIN_NO(195) | 1)</div><div class='add'>+#define PINMUX_GPIO195__FUNC_I2SIN4_LRCK (MTK_PIN_NO(195) | 5)</div><div class='add'>+</div><div class='add'>+#endif /* __MT6878_PINFUNC_H */</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt6893-pinfunc.h b/arch/arm64/boot/dts/mediatek/mt6893-pinfunc.h<br/>new file mode 100644<br/>index 000000000000..982bc95c471c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt6893-pinfunc.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt6893-pinfunc.h</a></div><div class='hunk'>@@ -0,0 +1,1356 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0 */</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2019 MediaTek Inc.</div><div class='add'>+ * Copyright (c) 2025 Collabora Ltd</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __MT6893_PINFUNC_H</div><div class='add'>+#define __MT6893_PINFUNC_H</div><div class='add'>+</div><div class='add'>+#include "mt65xx.h"</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)</div><div class='add'>+#define PINMUX_GPIO0__FUNC_SPI6_CLK (MTK_PIN_NO(0) | 1)</div><div class='add'>+#define PINMUX_GPIO0__FUNC_I2S5_MCK (MTK_PIN_NO(0) | 2)</div><div class='add'>+#define PINMUX_GPIO0__FUNC_PWM_0 (MTK_PIN_NO(0) | 3)</div><div class='add'>+#define PINMUX_GPIO0__FUNC_MD_INT0 (MTK_PIN_NO(0) | 4)</div><div class='add'>+#define PINMUX_GPIO0__FUNC_TP_GPIO0_AO (MTK_PIN_NO(0) | 5)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)</div><div class='add'>+#define PINMUX_GPIO1__FUNC_SPI6_CSB (MTK_PIN_NO(1) | 1)</div><div class='add'>+#define PINMUX_GPIO1__FUNC_I2S5_BCK (MTK_PIN_NO(1) | 2)</div><div class='add'>+#define PINMUX_GPIO1__FUNC_PWM_1 (MTK_PIN_NO(1) | 3)</div><div class='add'>+#define PINMUX_GPIO1__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(1) | 4)</div><div class='add'>+#define PINMUX_GPIO1__FUNC_TP_GPIO1_AO (MTK_PIN_NO(1) | 5)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)</div><div class='add'>+#define PINMUX_GPIO2__FUNC_SPI6_MI (MTK_PIN_NO(2) | 1)</div><div class='add'>+#define PINMUX_GPIO2__FUNC_I2S5_LRCK (MTK_PIN_NO(2) | 2)</div><div class='add'>+#define PINMUX_GPIO2__FUNC_PWM_2 (MTK_PIN_NO(2) | 3)</div><div class='add'>+#define PINMUX_GPIO2__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(2) | 4)</div><div class='add'>+#define PINMUX_GPIO2__FUNC_TP_GPIO2_AO (MTK_PIN_NO(2) | 5)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)</div><div class='add'>+#define PINMUX_GPIO3__FUNC_SPI6_MO (MTK_PIN_NO(3) | 1)</div><div class='add'>+#define PINMUX_GPIO3__FUNC_I2S5_DO (MTK_PIN_NO(3) | 2)</div><div class='add'>+#define PINMUX_GPIO3__FUNC_PWM_3 (MTK_PIN_NO(3) | 3)</div><div class='add'>+#define PINMUX_GPIO3__FUNC_CLKM0 (MTK_PIN_NO(3) | 4)</div><div class='add'>+#define PINMUX_GPIO3__FUNC_TP_GPIO3_AO (MTK_PIN_NO(3) | 5)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)</div><div class='add'>+#define PINMUX_GPIO4__FUNC_SPI7_A_CLK (MTK_PIN_NO(4) | 1)</div><div class='add'>+#define PINMUX_GPIO4__FUNC_I2S2_MCK (MTK_PIN_NO(4) | 2)</div><div class='add'>+#define PINMUX_GPIO4__FUNC_DMIC1_CLK (MTK_PIN_NO(4) | 3)</div><div class='add'>+#define PINMUX_GPIO4__FUNC_PCM1_DI (MTK_PIN_NO(4) | 4)</div><div class='add'>+#define PINMUX_GPIO4__FUNC_TP_GPIO4_AO (MTK_PIN_NO(4) | 5)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)</div><div class='add'>+#define PINMUX_GPIO5__FUNC_SPI7_A_CSB (MTK_PIN_NO(5) | 1)</div><div class='add'>+#define PINMUX_GPIO5__FUNC_I2S2_BCK (MTK_PIN_NO(5) | 2)</div><div class='add'>+#define PINMUX_GPIO5__FUNC_DMIC1_DAT (MTK_PIN_NO(5) | 3)</div><div class='add'>+#define PINMUX_GPIO5__FUNC_PCM1_CLK (MTK_PIN_NO(5) | 4)</div><div class='add'>+#define PINMUX_GPIO5__FUNC_TP_GPIO5_AO (MTK_PIN_NO(5) | 5)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)</div><div class='add'>+#define PINMUX_GPIO6__FUNC_SPI7_A_MI (MTK_PIN_NO(6) | 1)</div><div class='add'>+#define PINMUX_GPIO6__FUNC_I2S2_LRCK (MTK_PIN_NO(6) | 2)</div><div class='add'>+#define PINMUX_GPIO6__FUNC_DMIC_CLK (MTK_PIN_NO(6) | 3)</div><div class='add'>+#define PINMUX_GPIO6__FUNC_PCM1_SYNC (MTK_PIN_NO(6) | 4)</div><div class='add'>+#define PINMUX_GPIO6__FUNC_TP_GPIO6_AO (MTK_PIN_NO(6) | 5)</div><div class='add'>+#define PINMUX_GPIO6__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(6) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)</div><div class='add'>+#define PINMUX_GPIO7__FUNC_SPI7_A_MO (MTK_PIN_NO(7) | 1)</div><div class='add'>+#define PINMUX_GPIO7__FUNC_I2S2_DI (MTK_PIN_NO(7) | 2)</div><div class='add'>+#define PINMUX_GPIO7__FUNC_DMIC_DAT (MTK_PIN_NO(7) | 3)</div><div class='add'>+#define PINMUX_GPIO7__FUNC_PCM1_DO0 (MTK_PIN_NO(7) | 4)</div><div class='add'>+#define PINMUX_GPIO7__FUNC_TP_GPIO7_AO (MTK_PIN_NO(7) | 5)</div><div class='add'>+#define PINMUX_GPIO7__FUNC_WIFI_TXD (MTK_PIN_NO(7) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)</div><div class='add'>+#define PINMUX_GPIO8__FUNC_SRCLKENAI1 (MTK_PIN_NO(8) | 1)</div><div class='add'>+#define PINMUX_GPIO8__FUNC_I2S2_DI2 (MTK_PIN_NO(8) | 2)</div><div class='add'>+#define PINMUX_GPIO8__FUNC_KPCOL2 (MTK_PIN_NO(8) | 3)</div><div class='add'>+#define PINMUX_GPIO8__FUNC_PCM1_DO1 (MTK_PIN_NO(8) | 4)</div><div class='add'>+#define PINMUX_GPIO8__FUNC_CLKM1 (MTK_PIN_NO(8) | 5)</div><div class='add'>+#define PINMUX_GPIO8__FUNC_CONN_BT_TXD (MTK_PIN_NO(8) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)</div><div class='add'>+#define PINMUX_GPIO9__FUNC_SRCLKENAI0 (MTK_PIN_NO(9) | 1)</div><div class='add'>+#define PINMUX_GPIO9__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(9) | 2)</div><div class='add'>+#define PINMUX_GPIO9__FUNC_KPROW2 (MTK_PIN_NO(9) | 3)</div><div class='add'>+#define PINMUX_GPIO9__FUNC_PCM1_DO2 (MTK_PIN_NO(9) | 4)</div><div class='add'>+#define PINMUX_GPIO9__FUNC_CLKM3 (MTK_PIN_NO(9) | 5)</div><div class='add'>+#define PINMUX_GPIO9__FUNC_CMMCLK4 (MTK_PIN_NO(9) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)</div><div class='add'>+#define PINMUX_GPIO10__FUNC_MSDC1_CLK_A (MTK_PIN_NO(10) | 1)</div><div class='add'>+#define PINMUX_GPIO10__FUNC_SPI4_B_CLK (MTK_PIN_NO(10) | 2)</div><div class='add'>+#define PINMUX_GPIO10__FUNC_I2S8_MCK (MTK_PIN_NO(10) | 3)</div><div class='add'>+#define PINMUX_GPIO10__FUNC_DSI1_TE (MTK_PIN_NO(10) | 4)</div><div class='add'>+#define PINMUX_GPIO10__FUNC_MD_INT0 (MTK_PIN_NO(10) | 5)</div><div class='add'>+#define PINMUX_GPIO10__FUNC_TP_GPIO0_AO (MTK_PIN_NO(10) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)</div><div class='add'>+#define PINMUX_GPIO11__FUNC_MSDC1_CMD_A (MTK_PIN_NO(11) | 1)</div><div class='add'>+#define PINMUX_GPIO11__FUNC_SPI4_B_CSB (MTK_PIN_NO(11) | 2)</div><div class='add'>+#define PINMUX_GPIO11__FUNC_I2S8_BCK (MTK_PIN_NO(11) | 3)</div><div class='add'>+#define PINMUX_GPIO11__FUNC_LCM1_RST (MTK_PIN_NO(11) | 4)</div><div class='add'>+#define PINMUX_GPIO11__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(11) | 5)</div><div class='add'>+#define PINMUX_GPIO11__FUNC_TP_GPIO1_AO (MTK_PIN_NO(11) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)</div><div class='add'>+#define PINMUX_GPIO12__FUNC_MSDC1_DAT3_A (MTK_PIN_NO(12) | 1)</div><div class='add'>+#define PINMUX_GPIO12__FUNC_SPI4_B_MI (MTK_PIN_NO(12) | 2)</div><div class='add'>+#define PINMUX_GPIO12__FUNC_I2S8_LRCK (MTK_PIN_NO(12) | 3)</div><div class='add'>+#define PINMUX_GPIO12__FUNC_DMIC1_CLK (MTK_PIN_NO(12) | 4)</div><div class='add'>+#define PINMUX_GPIO12__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(12) | 5)</div><div class='add'>+#define PINMUX_GPIO12__FUNC_TP_GPIO2_AO (MTK_PIN_NO(12) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)</div><div class='add'>+#define PINMUX_GPIO13__FUNC_MSDC1_DAT0_A (MTK_PIN_NO(13) | 1)</div><div class='add'>+#define PINMUX_GPIO13__FUNC_SPI4_B_MO (MTK_PIN_NO(13) | 2)</div><div class='add'>+#define PINMUX_GPIO13__FUNC_I2S8_DI (MTK_PIN_NO(13) | 3)</div><div class='add'>+#define PINMUX_GPIO13__FUNC_DMIC1_DAT (MTK_PIN_NO(13) | 4)</div><div class='add'>+#define PINMUX_GPIO13__FUNC_ANT_SEL10 (MTK_PIN_NO(13) | 5)</div><div class='add'>+#define PINMUX_GPIO13__FUNC_TP_GPIO3_AO (MTK_PIN_NO(13) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)</div><div class='add'>+#define PINMUX_GPIO14__FUNC_MSDC1_DAT2_A (MTK_PIN_NO(14) | 1)</div><div class='add'>+#define PINMUX_GPIO14__FUNC_SPI5_C_CLK (MTK_PIN_NO(14) | 2)</div><div class='add'>+#define PINMUX_GPIO14__FUNC_I2S9_MCK (MTK_PIN_NO(14) | 3)</div><div class='add'>+#define PINMUX_GPIO14__FUNC_IDDIG (MTK_PIN_NO(14) | 4)</div><div class='add'>+#define PINMUX_GPIO14__FUNC_ANT_SEL11 (MTK_PIN_NO(14) | 5)</div><div class='add'>+#define PINMUX_GPIO14__FUNC_TP_GPIO4_AO (MTK_PIN_NO(14) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)</div><div class='add'>+#define PINMUX_GPIO15__FUNC_MSDC1_DAT1_A (MTK_PIN_NO(15) | 1)</div><div class='add'>+#define PINMUX_GPIO15__FUNC_SPI5_C_CSB (MTK_PIN_NO(15) | 2)</div><div class='add'>+#define PINMUX_GPIO15__FUNC_I2S9_BCK (MTK_PIN_NO(15) | 3)</div><div class='add'>+#define PINMUX_GPIO15__FUNC_USB_DRVVBUS (MTK_PIN_NO(15) | 4)</div><div class='add'>+#define PINMUX_GPIO15__FUNC_ANT_SEL12 (MTK_PIN_NO(15) | 5)</div><div class='add'>+#define PINMUX_GPIO15__FUNC_TP_GPIO5_AO (MTK_PIN_NO(15) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0)</div><div class='add'>+#define PINMUX_GPIO16__FUNC_SRCLKENAI1 (MTK_PIN_NO(16) | 1)</div><div class='add'>+#define PINMUX_GPIO16__FUNC_SPI5_C_MI (MTK_PIN_NO(16) | 2)</div><div class='add'>+#define PINMUX_GPIO16__FUNC_I2S9_LRCK (MTK_PIN_NO(16) | 3)</div><div class='add'>+#define PINMUX_GPIO16__FUNC_KPCOL2 (MTK_PIN_NO(16) | 4)</div><div class='add'>+#define PINMUX_GPIO16__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(16) | 5)</div><div class='add'>+#define PINMUX_GPIO16__FUNC_TP_GPIO6_AO (MTK_PIN_NO(16) | 6)</div><div class='add'>+#define PINMUX_GPIO16__FUNC_DBG_MON_A30 (MTK_PIN_NO(16) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0)</div><div class='add'>+#define PINMUX_GPIO17__FUNC_SRCLKENAI0 (MTK_PIN_NO(17) | 1)</div><div class='add'>+#define PINMUX_GPIO17__FUNC_SPI5_C_MO (MTK_PIN_NO(17) | 2)</div><div class='add'>+#define PINMUX_GPIO17__FUNC_I2S9_DO (MTK_PIN_NO(17) | 3)</div><div class='add'>+#define PINMUX_GPIO17__FUNC_KPROW2 (MTK_PIN_NO(17) | 4)</div><div class='add'>+#define PINMUX_GPIO17__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(17) | 5)</div><div class='add'>+#define PINMUX_GPIO17__FUNC_TP_GPIO7_AO (MTK_PIN_NO(17) | 6)</div><div class='add'>+#define PINMUX_GPIO17__FUNC_DBG_MON_A31 (MTK_PIN_NO(17) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)</div><div class='add'>+#define PINMUX_GPIO18__FUNC_DP_TX_HPD (MTK_PIN_NO(18) | 1)</div><div class='add'>+#define PINMUX_GPIO18__FUNC_SPI4_C_MI (MTK_PIN_NO(18) | 2)</div><div class='add'>+#define PINMUX_GPIO18__FUNC_SPI1_B_MI (MTK_PIN_NO(18) | 3)</div><div class='add'>+#define PINMUX_GPIO18__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(18) | 4)</div><div class='add'>+#define PINMUX_GPIO18__FUNC_ANT_SEL10 (MTK_PIN_NO(18) | 5)</div><div class='add'>+#define PINMUX_GPIO18__FUNC_MD_INT0 (MTK_PIN_NO(18) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)</div><div class='add'>+#define PINMUX_GPIO19__FUNC_SRCLKENAI1 (MTK_PIN_NO(19) | 1)</div><div class='add'>+#define PINMUX_GPIO19__FUNC_SPI4_C_MO (MTK_PIN_NO(19) | 2)</div><div class='add'>+#define PINMUX_GPIO19__FUNC_SPI1_B_MO (MTK_PIN_NO(19) | 3)</div><div class='add'>+#define PINMUX_GPIO19__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(19) | 4)</div><div class='add'>+#define PINMUX_GPIO19__FUNC_ANT_SEL11 (MTK_PIN_NO(19) | 5)</div><div class='add'>+#define PINMUX_GPIO19__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(19) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)</div><div class='add'>+#define PINMUX_GPIO20__FUNC_SRCLKENAI0 (MTK_PIN_NO(20) | 1)</div><div class='add'>+#define PINMUX_GPIO20__FUNC_SPI4_C_CLK (MTK_PIN_NO(20) | 2)</div><div class='add'>+#define PINMUX_GPIO20__FUNC_SPI1_B_CLK (MTK_PIN_NO(20) | 3)</div><div class='add'>+#define PINMUX_GPIO20__FUNC_PWM_3 (MTK_PIN_NO(20) | 4)</div><div class='add'>+#define PINMUX_GPIO20__FUNC_ANT_SEL12 (MTK_PIN_NO(20) | 5)</div><div class='add'>+#define PINMUX_GPIO20__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(20) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)</div><div class='add'>+#define PINMUX_GPIO21__FUNC_DP_TX_HPD (MTK_PIN_NO(21) | 1)</div><div class='add'>+#define PINMUX_GPIO21__FUNC_SPI4_C_CSB (MTK_PIN_NO(21) | 2)</div><div class='add'>+#define PINMUX_GPIO21__FUNC_SPI1_B_CSB (MTK_PIN_NO(21) | 3)</div><div class='add'>+#define PINMUX_GPIO21__FUNC_I2S7_MCK (MTK_PIN_NO(21) | 4)</div><div class='add'>+#define PINMUX_GPIO21__FUNC_I2S9_MCK (MTK_PIN_NO(21) | 5)</div><div class='add'>+#define PINMUX_GPIO21__FUNC_IDDIG (MTK_PIN_NO(21) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)</div><div class='add'>+#define PINMUX_GPIO22__FUNC_LCM1_RST (MTK_PIN_NO(22) | 1)</div><div class='add'>+#define PINMUX_GPIO22__FUNC_SPI0_C_CLK (MTK_PIN_NO(22) | 2)</div><div class='add'>+#define PINMUX_GPIO22__FUNC_SPI7_B_CLK (MTK_PIN_NO(22) | 3)</div><div class='add'>+#define PINMUX_GPIO22__FUNC_I2S7_BCK (MTK_PIN_NO(22) | 4)</div><div class='add'>+#define PINMUX_GPIO22__FUNC_I2S9_BCK (MTK_PIN_NO(22) | 5)</div><div class='add'>+#define PINMUX_GPIO22__FUNC_SCL13 (MTK_PIN_NO(22) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)</div><div class='add'>+#define PINMUX_GPIO23__FUNC_DSI1_TE (MTK_PIN_NO(23) | 1)</div><div class='add'>+#define PINMUX_GPIO23__FUNC_SPI0_C_CSB (MTK_PIN_NO(23) | 2)</div><div class='add'>+#define PINMUX_GPIO23__FUNC_SPI7_B_CSB (MTK_PIN_NO(23) | 3)</div><div class='add'>+#define PINMUX_GPIO23__FUNC_I2S7_LRCK (MTK_PIN_NO(23) | 4)</div><div class='add'>+#define PINMUX_GPIO23__FUNC_I2S9_LRCK (MTK_PIN_NO(23) | 5)</div><div class='add'>+#define PINMUX_GPIO23__FUNC_SDA13 (MTK_PIN_NO(23) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)</div><div class='add'>+#define PINMUX_GPIO24__FUNC_SRCLKENAI1 (MTK_PIN_NO(24) | 1)</div><div class='add'>+#define PINMUX_GPIO24__FUNC_SPI0_C_MI (MTK_PIN_NO(24) | 2)</div><div class='add'>+#define PINMUX_GPIO24__FUNC_SPI7_B_MI (MTK_PIN_NO(24) | 3)</div><div class='add'>+#define PINMUX_GPIO24__FUNC_I2S6_DI (MTK_PIN_NO(24) | 4)</div><div class='add'>+#define PINMUX_GPIO24__FUNC_I2S8_DI (MTK_PIN_NO(24) | 5)</div><div class='add'>+#define PINMUX_GPIO24__FUNC_SCL_6306 (MTK_PIN_NO(24) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)</div><div class='add'>+#define PINMUX_GPIO25__FUNC_SRCLKENAI0 (MTK_PIN_NO(25) | 1)</div><div class='add'>+#define PINMUX_GPIO25__FUNC_SPI0_C_MO (MTK_PIN_NO(25) | 2)</div><div class='add'>+#define PINMUX_GPIO25__FUNC_SPI7_B_MO (MTK_PIN_NO(25) | 3)</div><div class='add'>+#define PINMUX_GPIO25__FUNC_I2S7_DO (MTK_PIN_NO(25) | 4)</div><div class='add'>+#define PINMUX_GPIO25__FUNC_I2S9_DO (MTK_PIN_NO(25) | 5)</div><div class='add'>+#define PINMUX_GPIO25__FUNC_SDA_6306 (MTK_PIN_NO(25) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)</div><div class='add'>+#define PINMUX_GPIO26__FUNC_PWM_2 (MTK_PIN_NO(26) | 1)</div><div class='add'>+#define PINMUX_GPIO26__FUNC_CLKM0 (MTK_PIN_NO(26) | 2)</div><div class='add'>+#define PINMUX_GPIO26__FUNC_USB_DRVVBUS (MTK_PIN_NO(26) | 3)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)</div><div class='add'>+#define PINMUX_GPIO27__FUNC_PWM_3 (MTK_PIN_NO(27) | 1)</div><div class='add'>+#define PINMUX_GPIO27__FUNC_CLKM1 (MTK_PIN_NO(27) | 2)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)</div><div class='add'>+#define PINMUX_GPIO28__FUNC_PWM_0 (MTK_PIN_NO(28) | 1)</div><div class='add'>+#define PINMUX_GPIO28__FUNC_CLKM2 (MTK_PIN_NO(28) | 2)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)</div><div class='add'>+#define PINMUX_GPIO29__FUNC_PWM_1 (MTK_PIN_NO(29) | 1)</div><div class='add'>+#define PINMUX_GPIO29__FUNC_CLKM3 (MTK_PIN_NO(29) | 2)</div><div class='add'>+#define PINMUX_GPIO29__FUNC_DSI1_TE (MTK_PIN_NO(29) | 3)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0)</div><div class='add'>+#define PINMUX_GPIO30__FUNC_PWM_2 (MTK_PIN_NO(30) | 1)</div><div class='add'>+#define PINMUX_GPIO30__FUNC_CLKM0 (MTK_PIN_NO(30) | 2)</div><div class='add'>+#define PINMUX_GPIO30__FUNC_LCM1_RST (MTK_PIN_NO(30) | 3)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0)</div><div class='add'>+#define PINMUX_GPIO31__FUNC_I2S3_MCK (MTK_PIN_NO(31) | 1)</div><div class='add'>+#define PINMUX_GPIO31__FUNC_I2S1_MCK (MTK_PIN_NO(31) | 2)</div><div class='add'>+#define PINMUX_GPIO31__FUNC_I2S5_MCK (MTK_PIN_NO(31) | 3)</div><div class='add'>+#define PINMUX_GPIO31__FUNC_SRCLKENAI0 (MTK_PIN_NO(31) | 4)</div><div class='add'>+#define PINMUX_GPIO31__FUNC_I2S0_MCK (MTK_PIN_NO(31) | 5)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0)</div><div class='add'>+#define PINMUX_GPIO32__FUNC_I2S3_BCK (MTK_PIN_NO(32) | 1)</div><div class='add'>+#define PINMUX_GPIO32__FUNC_I2S1_BCK (MTK_PIN_NO(32) | 2)</div><div class='add'>+#define PINMUX_GPIO32__FUNC_I2S5_BCK (MTK_PIN_NO(32) | 3)</div><div class='add'>+#define PINMUX_GPIO32__FUNC_PCM0_CLK (MTK_PIN_NO(32) | 4)</div><div class='add'>+#define PINMUX_GPIO32__FUNC_I2S0_BCK (MTK_PIN_NO(32) | 5)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)</div><div class='add'>+#define PINMUX_GPIO33__FUNC_I2S3_LRCK (MTK_PIN_NO(33) | 1)</div><div class='add'>+#define PINMUX_GPIO33__FUNC_I2S1_LRCK (MTK_PIN_NO(33) | 2)</div><div class='add'>+#define PINMUX_GPIO33__FUNC_I2S5_LRCK (MTK_PIN_NO(33) | 3)</div><div class='add'>+#define PINMUX_GPIO33__FUNC_PCM0_SYNC (MTK_PIN_NO(33) | 4)</div><div class='add'>+#define PINMUX_GPIO33__FUNC_I2S0_LRCK (MTK_PIN_NO(33) | 5)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)</div><div class='add'>+#define PINMUX_GPIO34__FUNC_I2S0_DI (MTK_PIN_NO(34) | 1)</div><div class='add'>+#define PINMUX_GPIO34__FUNC_I2S2_DI (MTK_PIN_NO(34) | 2)</div><div class='add'>+#define PINMUX_GPIO34__FUNC_I2S2_DI2 (MTK_PIN_NO(34) | 3)</div><div class='add'>+#define PINMUX_GPIO34__FUNC_PCM0_DI (MTK_PIN_NO(34) | 4)</div><div class='add'>+#define PINMUX_GPIO34__FUNC_I2S0_DI_A (MTK_PIN_NO(34) | 5)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)</div><div class='add'>+#define PINMUX_GPIO35__FUNC_I2S3_DO (MTK_PIN_NO(35) | 1)</div><div class='add'>+#define PINMUX_GPIO35__FUNC_I2S1_DO (MTK_PIN_NO(35) | 2)</div><div class='add'>+#define PINMUX_GPIO35__FUNC_I2S5_DO (MTK_PIN_NO(35) | 3)</div><div class='add'>+#define PINMUX_GPIO35__FUNC_PCM0_DO (MTK_PIN_NO(35) | 4)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)</div><div class='add'>+#define PINMUX_GPIO36__FUNC_SPI5_A_CLK (MTK_PIN_NO(36) | 1)</div><div class='add'>+#define PINMUX_GPIO36__FUNC_DMIC1_CLK (MTK_PIN_NO(36) | 2)</div><div class='add'>+#define PINMUX_GPIO36__FUNC_IDDIG (MTK_PIN_NO(36) | 3)</div><div class='add'>+#define PINMUX_GPIO36__FUNC_MD_URXD0 (MTK_PIN_NO(36) | 4)</div><div class='add'>+#define PINMUX_GPIO36__FUNC_UCTS0 (MTK_PIN_NO(36) | 5)</div><div class='add'>+#define PINMUX_GPIO36__FUNC_URXD1 (MTK_PIN_NO(36) | 6)</div><div class='add'>+#define PINMUX_GPIO36__FUNC_DBG_MON_A0 (MTK_PIN_NO(36) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)</div><div class='add'>+#define PINMUX_GPIO37__FUNC_SPI5_A_CSB (MTK_PIN_NO(37) | 1)</div><div class='add'>+#define PINMUX_GPIO37__FUNC_DMIC1_DAT (MTK_PIN_NO(37) | 2)</div><div class='add'>+#define PINMUX_GPIO37__FUNC_USB_DRVVBUS (MTK_PIN_NO(37) | 3)</div><div class='add'>+#define PINMUX_GPIO37__FUNC_MD_UTXD0 (MTK_PIN_NO(37) | 4)</div><div class='add'>+#define PINMUX_GPIO37__FUNC_URTS0 (MTK_PIN_NO(37) | 5)</div><div class='add'>+#define PINMUX_GPIO37__FUNC_UTXD1 (MTK_PIN_NO(37) | 6)</div><div class='add'>+#define PINMUX_GPIO37__FUNC_DBG_MON_A1 (MTK_PIN_NO(37) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0)</div><div class='add'>+#define PINMUX_GPIO38__FUNC_SPI5_A_MI (MTK_PIN_NO(38) | 1)</div><div class='add'>+#define PINMUX_GPIO38__FUNC_DMIC_CLK (MTK_PIN_NO(38) | 2)</div><div class='add'>+#define PINMUX_GPIO38__FUNC_DSI1_TE (MTK_PIN_NO(38) | 3)</div><div class='add'>+#define PINMUX_GPIO38__FUNC_MD_URXD1 (MTK_PIN_NO(38) | 4)</div><div class='add'>+#define PINMUX_GPIO38__FUNC_URXD0 (MTK_PIN_NO(38) | 5)</div><div class='add'>+#define PINMUX_GPIO38__FUNC_UCTS1 (MTK_PIN_NO(38) | 6)</div><div class='add'>+#define PINMUX_GPIO38__FUNC_DBG_MON_A2 (MTK_PIN_NO(38) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)</div><div class='add'>+#define PINMUX_GPIO39__FUNC_SPI5_A_MO (MTK_PIN_NO(39) | 1)</div><div class='add'>+#define PINMUX_GPIO39__FUNC_DMIC_DAT (MTK_PIN_NO(39) | 2)</div><div class='add'>+#define PINMUX_GPIO39__FUNC_LCM1_RST (MTK_PIN_NO(39) | 3)</div><div class='add'>+#define PINMUX_GPIO39__FUNC_MD_UTXD1 (MTK_PIN_NO(39) | 4)</div><div class='add'>+#define PINMUX_GPIO39__FUNC_UTXD0 (MTK_PIN_NO(39) | 5)</div><div class='add'>+#define PINMUX_GPIO39__FUNC_URTS1 (MTK_PIN_NO(39) | 6)</div><div class='add'>+#define PINMUX_GPIO39__FUNC_DBG_MON_A3 (MTK_PIN_NO(39) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)</div><div class='add'>+#define PINMUX_GPIO40__FUNC_DISP_PWM (MTK_PIN_NO(40) | 1)</div><div class='add'>+#define PINMUX_GPIO40__FUNC_DBG_MON_A6 (MTK_PIN_NO(40) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0)</div><div class='add'>+#define PINMUX_GPIO41__FUNC_DSI_TE (MTK_PIN_NO(41) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0)</div><div class='add'>+#define PINMUX_GPIO42__FUNC_LCM_RST (MTK_PIN_NO(42) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0)</div><div class='add'>+#define PINMUX_GPIO43__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(43) | 1)</div><div class='add'>+#define PINMUX_GPIO43__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(43) | 2)</div><div class='add'>+#define PINMUX_GPIO43__FUNC_SCL_6306 (MTK_PIN_NO(43) | 3)</div><div class='add'>+#define PINMUX_GPIO43__FUNC_ADSP_URXD0 (MTK_PIN_NO(43) | 4)</div><div class='add'>+#define PINMUX_GPIO43__FUNC_PTA_RXD (MTK_PIN_NO(43) | 5)</div><div class='add'>+#define PINMUX_GPIO43__FUNC_SSPM_URXD_AO (MTK_PIN_NO(43) | 6)</div><div class='add'>+#define PINMUX_GPIO43__FUNC_DBG_MON_A4 (MTK_PIN_NO(43) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0)</div><div class='add'>+#define PINMUX_GPIO44__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(44) | 1)</div><div class='add'>+#define PINMUX_GPIO44__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(44) | 2)</div><div class='add'>+#define PINMUX_GPIO44__FUNC_SDA_6306 (MTK_PIN_NO(44) | 3)</div><div class='add'>+#define PINMUX_GPIO44__FUNC_ADSP_UTXD0 (MTK_PIN_NO(44) | 4)</div><div class='add'>+#define PINMUX_GPIO44__FUNC_PTA_TXD (MTK_PIN_NO(44) | 5)</div><div class='add'>+#define PINMUX_GPIO44__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(44) | 6)</div><div class='add'>+#define PINMUX_GPIO44__FUNC_DBG_MON_A5 (MTK_PIN_NO(44) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0)</div><div class='add'>+#define PINMUX_GPIO45__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(45) | 1)</div><div class='add'>+#define PINMUX_GPIO45__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(45) | 2)</div><div class='add'>+#define PINMUX_GPIO45__FUNC_MCUPM_JTAG_TDI (MTK_PIN_NO(45) | 3)</div><div class='add'>+#define PINMUX_GPIO45__FUNC_APU_JTAG_TDI (MTK_PIN_NO(45) | 4)</div><div class='add'>+#define PINMUX_GPIO45__FUNC_CCU_JTAG_TDI (MTK_PIN_NO(45) | 5)</div><div class='add'>+#define PINMUX_GPIO45__FUNC_LVTS_SCK (MTK_PIN_NO(45) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0)</div><div class='add'>+#define PINMUX_GPIO46__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(46) | 1)</div><div class='add'>+#define PINMUX_GPIO46__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(46) | 2)</div><div class='add'>+#define PINMUX_GPIO46__FUNC_MCUPM_JTAG_TMS (MTK_PIN_NO(46) | 3)</div><div class='add'>+#define PINMUX_GPIO46__FUNC_APU_JTAG_TMS (MTK_PIN_NO(46) | 4)</div><div class='add'>+#define PINMUX_GPIO46__FUNC_CCU_JTAG_TMS (MTK_PIN_NO(46) | 5)</div><div class='add'>+#define PINMUX_GPIO46__FUNC_LVTS_SDI (MTK_PIN_NO(46) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0)</div><div class='add'>+#define PINMUX_GPIO47__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(47) | 1)</div><div class='add'>+#define PINMUX_GPIO47__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(47) | 2)</div><div class='add'>+#define PINMUX_GPIO47__FUNC_MCUPM_JTAG_TDO (MTK_PIN_NO(47) | 3)</div><div class='add'>+#define PINMUX_GPIO47__FUNC_APU_JTAG_TDO (MTK_PIN_NO(47) | 4)</div><div class='add'>+#define PINMUX_GPIO47__FUNC_CCU_JTAG_TDO (MTK_PIN_NO(47) | 5)</div><div class='add'>+#define PINMUX_GPIO47__FUNC_LVTS_SCF (MTK_PIN_NO(47) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0)</div><div class='add'>+#define PINMUX_GPIO48__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(48) | 1)</div><div class='add'>+#define PINMUX_GPIO48__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(48) | 2)</div><div class='add'>+#define PINMUX_GPIO48__FUNC_MCUPM_JTAG_TRSTN (MTK_PIN_NO(48) | 3)</div><div class='add'>+#define PINMUX_GPIO48__FUNC_APU_JTAG_TRST (MTK_PIN_NO(48) | 4)</div><div class='add'>+#define PINMUX_GPIO48__FUNC_CCU_JTAG_TRST (MTK_PIN_NO(48) | 5)</div><div class='add'>+#define PINMUX_GPIO48__FUNC_LVTS_FOUT (MTK_PIN_NO(48) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0)</div><div class='add'>+#define PINMUX_GPIO49__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(49) | 1)</div><div class='add'>+#define PINMUX_GPIO49__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(49) | 2)</div><div class='add'>+#define PINMUX_GPIO49__FUNC_MCUPM_JTAG_TCK (MTK_PIN_NO(49) | 3)</div><div class='add'>+#define PINMUX_GPIO49__FUNC_APU_JTAG_TCK (MTK_PIN_NO(49) | 4)</div><div class='add'>+#define PINMUX_GPIO49__FUNC_CCU_JTAG_TCK (MTK_PIN_NO(49) | 5)</div><div class='add'>+#define PINMUX_GPIO49__FUNC_LVTS_SDO (MTK_PIN_NO(49) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0)</div><div class='add'>+#define PINMUX_GPIO50__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(50) | 1)</div><div class='add'>+#define PINMUX_GPIO50__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(50) | 2)</div><div class='add'>+#define PINMUX_GPIO50__FUNC_LVTS_26M (MTK_PIN_NO(50) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0)</div><div class='add'>+#define PINMUX_GPIO51__FUNC_MSDC1_CLK (MTK_PIN_NO(51) | 1)</div><div class='add'>+#define PINMUX_GPIO51__FUNC_PCM1_CLK (MTK_PIN_NO(51) | 2)</div><div class='add'>+#define PINMUX_GPIO51__FUNC_VPU_UDI_TCK (MTK_PIN_NO(51) | 3)</div><div class='add'>+#define PINMUX_GPIO51__FUNC_UDI_TCK (MTK_PIN_NO(51) | 4)</div><div class='add'>+#define PINMUX_GPIO51__FUNC_IPU_JTAG_TCK (MTK_PIN_NO(51) | 5)</div><div class='add'>+#define PINMUX_GPIO51__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(51) | 6)</div><div class='add'>+#define PINMUX_GPIO51__FUNC_JTCK_SEL3 (MTK_PIN_NO(51) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0)</div><div class='add'>+#define PINMUX_GPIO52__FUNC_MSDC1_CMD (MTK_PIN_NO(52) | 1)</div><div class='add'>+#define PINMUX_GPIO52__FUNC_PCM1_SYNC (MTK_PIN_NO(52) | 2)</div><div class='add'>+#define PINMUX_GPIO52__FUNC_VPU_UDI_TMS (MTK_PIN_NO(52) | 3)</div><div class='add'>+#define PINMUX_GPIO52__FUNC_UDI_TMS (MTK_PIN_NO(52) | 4)</div><div class='add'>+#define PINMUX_GPIO52__FUNC_IPU_JTAG_TMS (MTK_PIN_NO(52) | 5)</div><div class='add'>+#define PINMUX_GPIO52__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(52) | 6)</div><div class='add'>+#define PINMUX_GPIO52__FUNC_JTMS_SEL3 (MTK_PIN_NO(52) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0)</div><div class='add'>+#define PINMUX_GPIO53__FUNC_MSDC1_DAT3 (MTK_PIN_NO(53) | 1)</div><div class='add'>+#define PINMUX_GPIO53__FUNC_PCM1_DI (MTK_PIN_NO(53) | 2)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0)</div><div class='add'>+#define PINMUX_GPIO54__FUNC_MSDC1_DAT0 (MTK_PIN_NO(54) | 1)</div><div class='add'>+#define PINMUX_GPIO54__FUNC_PCM1_DO0 (MTK_PIN_NO(54) | 2)</div><div class='add'>+#define PINMUX_GPIO54__FUNC_VPU_UDI_TDI (MTK_PIN_NO(54) | 3)</div><div class='add'>+#define PINMUX_GPIO54__FUNC_UDI_TDI (MTK_PIN_NO(54) | 4)</div><div class='add'>+#define PINMUX_GPIO54__FUNC_IPU_JTAG_TDI (MTK_PIN_NO(54) | 5)</div><div class='add'>+#define PINMUX_GPIO54__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(54) | 6)</div><div class='add'>+#define PINMUX_GPIO54__FUNC_JTDI_SEL3 (MTK_PIN_NO(54) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0)</div><div class='add'>+#define PINMUX_GPIO55__FUNC_MSDC1_DAT2 (MTK_PIN_NO(55) | 1)</div><div class='add'>+#define PINMUX_GPIO55__FUNC_PCM1_DO2 (MTK_PIN_NO(55) | 2)</div><div class='add'>+#define PINMUX_GPIO55__FUNC_VPU_UDI_NTRST (MTK_PIN_NO(55) | 3)</div><div class='add'>+#define PINMUX_GPIO55__FUNC_UDI_NTRST (MTK_PIN_NO(55) | 4)</div><div class='add'>+#define PINMUX_GPIO55__FUNC_IPU_JTAG_TRST (MTK_PIN_NO(55) | 5)</div><div class='add'>+#define PINMUX_GPIO55__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(55) | 6)</div><div class='add'>+#define PINMUX_GPIO55__FUNC_JTRSTN_SEL3 (MTK_PIN_NO(55) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0)</div><div class='add'>+#define PINMUX_GPIO56__FUNC_MSDC1_DAT1 (MTK_PIN_NO(56) | 1)</div><div class='add'>+#define PINMUX_GPIO56__FUNC_PCM1_DO1 (MTK_PIN_NO(56) | 2)</div><div class='add'>+#define PINMUX_GPIO56__FUNC_VPU_UDI_TDO (MTK_PIN_NO(56) | 3)</div><div class='add'>+#define PINMUX_GPIO56__FUNC_UDI_TDO (MTK_PIN_NO(56) | 4)</div><div class='add'>+#define PINMUX_GPIO56__FUNC_IPU_JTAG_TDO (MTK_PIN_NO(56) | 5)</div><div class='add'>+#define PINMUX_GPIO56__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(56) | 6)</div><div class='add'>+#define PINMUX_GPIO56__FUNC_JTDO_SEL3 (MTK_PIN_NO(56) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0)</div><div class='add'>+#define PINMUX_GPIO57__FUNC_MIPI2_D_SCLK (MTK_PIN_NO(57) | 1)</div><div class='add'>+#define PINMUX_GPIO57__FUNC_DBG_MON_A14 (MTK_PIN_NO(57) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0)</div><div class='add'>+#define PINMUX_GPIO58__FUNC_MIPI2_D_SDATA (MTK_PIN_NO(58) | 1)</div><div class='add'>+#define PINMUX_GPIO58__FUNC_DBG_MON_A15 (MTK_PIN_NO(58) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0)</div><div class='add'>+#define PINMUX_GPIO59__FUNC_MIPI_M_SCLK (MTK_PIN_NO(59) | 1)</div><div class='add'>+#define PINMUX_GPIO59__FUNC_DBG_MON_A17 (MTK_PIN_NO(59) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0)</div><div class='add'>+#define PINMUX_GPIO60__FUNC_MIPI_M_SDATA (MTK_PIN_NO(60) | 1)</div><div class='add'>+#define PINMUX_GPIO60__FUNC_DBG_MON_A18 (MTK_PIN_NO(60) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0)</div><div class='add'>+#define PINMUX_GPIO61__FUNC_MD_UCNT_A_TGL (MTK_PIN_NO(61) | 1)</div><div class='add'>+#define PINMUX_GPIO61__FUNC_DBG_MON_A16 (MTK_PIN_NO(61) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0)</div><div class='add'>+#define PINMUX_GPIO62__FUNC_DIGRF_IRQ (MTK_PIN_NO(62) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0)</div><div class='add'>+#define PINMUX_GPIO63__FUNC_BPI_BUS0 (MTK_PIN_NO(63) | 1)</div><div class='add'>+#define PINMUX_GPIO63__FUNC_DBG_MON_A19 (MTK_PIN_NO(63) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0)</div><div class='add'>+#define PINMUX_GPIO64__FUNC_BPI_BUS1 (MTK_PIN_NO(64) | 1)</div><div class='add'>+#define PINMUX_GPIO64__FUNC_DBG_MON_A20 (MTK_PIN_NO(64) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0)</div><div class='add'>+#define PINMUX_GPIO65__FUNC_BPI_BUS2 (MTK_PIN_NO(65) | 1)</div><div class='add'>+#define PINMUX_GPIO65__FUNC_DBG_MON_A21 (MTK_PIN_NO(65) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0)</div><div class='add'>+#define PINMUX_GPIO66__FUNC_BPI_BUS3 (MTK_PIN_NO(66) | 1)</div><div class='add'>+#define PINMUX_GPIO66__FUNC_DBG_MON_A22 (MTK_PIN_NO(66) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0)</div><div class='add'>+#define PINMUX_GPIO67__FUNC_BPI_BUS4 (MTK_PIN_NO(67) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0)</div><div class='add'>+#define PINMUX_GPIO68__FUNC_BPI_BUS5 (MTK_PIN_NO(68) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0)</div><div class='add'>+#define PINMUX_GPIO69__FUNC_BPI_BUS6 (MTK_PIN_NO(69) | 1)</div><div class='add'>+#define PINMUX_GPIO69__FUNC_CONN_BPI_BUS6 (MTK_PIN_NO(69) | 2)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0)</div><div class='add'>+#define PINMUX_GPIO70__FUNC_BPI_BUS7 (MTK_PIN_NO(70) | 1)</div><div class='add'>+#define PINMUX_GPIO70__FUNC_CONN_BPI_BUS7 (MTK_PIN_NO(70) | 2)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0)</div><div class='add'>+#define PINMUX_GPIO71__FUNC_BPI_BUS8 (MTK_PIN_NO(71) | 1)</div><div class='add'>+#define PINMUX_GPIO71__FUNC_CONN_BPI_BUS8 (MTK_PIN_NO(71) | 2)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0)</div><div class='add'>+#define PINMUX_GPIO72__FUNC_BPI_BUS9 (MTK_PIN_NO(72) | 1)</div><div class='add'>+#define PINMUX_GPIO72__FUNC_CONN_BPI_BUS9 (MTK_PIN_NO(72) | 2)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0)</div><div class='add'>+#define PINMUX_GPIO73__FUNC_BPI_BUS10 (MTK_PIN_NO(73) | 1)</div><div class='add'>+#define PINMUX_GPIO73__FUNC_CONN_BPI_BUS10 (MTK_PIN_NO(73) | 2)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0)</div><div class='add'>+#define PINMUX_GPIO74__FUNC_BPI_BUS11_OLAT0 (MTK_PIN_NO(74) | 1)</div><div class='add'>+#define PINMUX_GPIO74__FUNC_CONN_BPI_BUS11_OLAT0 (MTK_PIN_NO(74) | 2)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0)</div><div class='add'>+#define PINMUX_GPIO75__FUNC_BPI_BUS12_OLAT1 (MTK_PIN_NO(75) | 1)</div><div class='add'>+#define PINMUX_GPIO75__FUNC_CONN_BPI_BUS12_OLAT1 (MTK_PIN_NO(75) | 2)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0)</div><div class='add'>+#define PINMUX_GPIO76__FUNC_BPI_BUS13_OLAT2 (MTK_PIN_NO(76) | 1)</div><div class='add'>+#define PINMUX_GPIO76__FUNC_CONN_BPI_BUS13_OLAT2 (MTK_PIN_NO(76) | 2)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0)</div><div class='add'>+#define PINMUX_GPIO77__FUNC_BPI_BUS14_OLAT3 (MTK_PIN_NO(77) | 1)</div><div class='add'>+#define PINMUX_GPIO77__FUNC_CONN_BPI_BUS14_OLAT3 (MTK_PIN_NO(77) | 2)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0)</div><div class='add'>+#define PINMUX_GPIO78__FUNC_BPI_BUS15_OLAT4 (MTK_PIN_NO(78) | 1)</div><div class='add'>+#define PINMUX_GPIO78__FUNC_CONN_BPI_BUS15_OLAT4 (MTK_PIN_NO(78) | 2)</div><div class='add'>+#define PINMUX_GPIO78__FUNC_DBG_MON_A7 (MTK_PIN_NO(78) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0)</div><div class='add'>+#define PINMUX_GPIO79__FUNC_BPI_BUS16_OLAT5 (MTK_PIN_NO(79) | 1)</div><div class='add'>+#define PINMUX_GPIO79__FUNC_CONN_BPI_BUS16_OLAT5 (MTK_PIN_NO(79) | 2)</div><div class='add'>+#define PINMUX_GPIO79__FUNC_DBG_MON_A8 (MTK_PIN_NO(79) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0)</div><div class='add'>+#define PINMUX_GPIO80__FUNC_BPI_BUS17_ANT0 (MTK_PIN_NO(80) | 1)</div><div class='add'>+#define PINMUX_GPIO80__FUNC_CONN_BPI_BUS17_ANT0 (MTK_PIN_NO(80) | 2)</div><div class='add'>+#define PINMUX_GPIO80__FUNC_DBG_MON_A9 (MTK_PIN_NO(80) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0)</div><div class='add'>+#define PINMUX_GPIO81__FUNC_BPI_BUS18_ANT1 (MTK_PIN_NO(81) | 1)</div><div class='add'>+#define PINMUX_GPIO81__FUNC_CONN_BPI_BUS18_ANT1 (MTK_PIN_NO(81) | 2)</div><div class='add'>+#define PINMUX_GPIO81__FUNC_DBG_MON_A10 (MTK_PIN_NO(81) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0)</div><div class='add'>+#define PINMUX_GPIO82__FUNC_BPI_BUS19_ANT2 (MTK_PIN_NO(82) | 1)</div><div class='add'>+#define PINMUX_GPIO82__FUNC_CONN_BPI_BUS19_ANT2 (MTK_PIN_NO(82) | 2)</div><div class='add'>+#define PINMUX_GPIO82__FUNC_DBG_MON_A11 (MTK_PIN_NO(82) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0)</div><div class='add'>+#define PINMUX_GPIO83__FUNC_BPI_BUS20_ANT3 (MTK_PIN_NO(83) | 1)</div><div class='add'>+#define PINMUX_GPIO83__FUNC_CONN_BPI_BUS20_ANT3 (MTK_PIN_NO(83) | 2)</div><div class='add'>+#define PINMUX_GPIO83__FUNC_DBG_MON_A12 (MTK_PIN_NO(83) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0)</div><div class='add'>+#define PINMUX_GPIO84__FUNC_BPI_BUS21_ANT4 (MTK_PIN_NO(84) | 1)</div><div class='add'>+#define PINMUX_GPIO84__FUNC_CONN_BPI_BUS21_ANT4 (MTK_PIN_NO(84) | 2)</div><div class='add'>+#define PINMUX_GPIO84__FUNC_DBG_MON_A13 (MTK_PIN_NO(84) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0)</div><div class='add'>+#define PINMUX_GPIO85__FUNC_MIPI1_D_SCLK (MTK_PIN_NO(85) | 1)</div><div class='add'>+#define PINMUX_GPIO85__FUNC_CONN_MIPI1_SCLK (MTK_PIN_NO(85) | 2)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0)</div><div class='add'>+#define PINMUX_GPIO86__FUNC_MIPI1_D_SDATA (MTK_PIN_NO(86) | 1)</div><div class='add'>+#define PINMUX_GPIO86__FUNC_CONN_MIPI1_SDATA (MTK_PIN_NO(86) | 2)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0)</div><div class='add'>+#define PINMUX_GPIO87__FUNC_MIPI0_D_SCLK (MTK_PIN_NO(87) | 1)</div><div class='add'>+#define PINMUX_GPIO87__FUNC_CONN_MIPI0_SCLK (MTK_PIN_NO(87) | 2)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0)</div><div class='add'>+#define PINMUX_GPIO88__FUNC_MIPI0_D_SDATA (MTK_PIN_NO(88) | 1)</div><div class='add'>+#define PINMUX_GPIO88__FUNC_CONN_MIPI0_SDATA (MTK_PIN_NO(88) | 2)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0)</div><div class='add'>+#define PINMUX_GPIO89__FUNC_SPMI_SCL (MTK_PIN_NO(89) | 1)</div><div class='add'>+#define PINMUX_GPIO89__FUNC_SCL10 (MTK_PIN_NO(89) | 2)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0)</div><div class='add'>+#define PINMUX_GPIO90__FUNC_SPMI_SDA (MTK_PIN_NO(90) | 1)</div><div class='add'>+#define PINMUX_GPIO90__FUNC_SDA10 (MTK_PIN_NO(90) | 2)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0)</div><div class='add'>+#define PINMUX_GPIO91__FUNC_AP_GOOD (MTK_PIN_NO(91) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0)</div><div class='add'>+#define PINMUX_GPIO92__FUNC_URXD0 (MTK_PIN_NO(92) | 1)</div><div class='add'>+#define PINMUX_GPIO92__FUNC_MD_URXD0 (MTK_PIN_NO(92) | 2)</div><div class='add'>+#define PINMUX_GPIO92__FUNC_MD_URXD1 (MTK_PIN_NO(92) | 3)</div><div class='add'>+#define PINMUX_GPIO92__FUNC_SSPM_URXD_AO (MTK_PIN_NO(92) | 4)</div><div class='add'>+#define PINMUX_GPIO92__FUNC_CONN_BGF_UART0_RXD (MTK_PIN_NO(92) | 5)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0)</div><div class='add'>+#define PINMUX_GPIO93__FUNC_UTXD0 (MTK_PIN_NO(93) | 1)</div><div class='add'>+#define PINMUX_GPIO93__FUNC_MD_UTXD0 (MTK_PIN_NO(93) | 2)</div><div class='add'>+#define PINMUX_GPIO93__FUNC_MD_UTXD1 (MTK_PIN_NO(93) | 3)</div><div class='add'>+#define PINMUX_GPIO93__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(93) | 4)</div><div class='add'>+#define PINMUX_GPIO93__FUNC_CONN_BGF_UART0_TXD (MTK_PIN_NO(93) | 5)</div><div class='add'>+#define PINMUX_GPIO93__FUNC_WIFI_TXD (MTK_PIN_NO(93) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0)</div><div class='add'>+#define PINMUX_GPIO94__FUNC_URXD1 (MTK_PIN_NO(94) | 1)</div><div class='add'>+#define PINMUX_GPIO94__FUNC_ADSP_URXD0 (MTK_PIN_NO(94) | 2)</div><div class='add'>+#define PINMUX_GPIO94__FUNC_MD32_0_RXD (MTK_PIN_NO(94) | 3)</div><div class='add'>+#define PINMUX_GPIO94__FUNC_SSPM_URXD_AO (MTK_PIN_NO(94) | 4)</div><div class='add'>+#define PINMUX_GPIO94__FUNC_TP_URXD1_AO (MTK_PIN_NO(94) | 5)</div><div class='add'>+#define PINMUX_GPIO94__FUNC_TP_URXD2_AO (MTK_PIN_NO(94) | 6)</div><div class='add'>+#define PINMUX_GPIO94__FUNC_MBISTREADEN_TRIGGER (MTK_PIN_NO(94) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0)</div><div class='add'>+#define PINMUX_GPIO95__FUNC_UTXD1 (MTK_PIN_NO(95) | 1)</div><div class='add'>+#define PINMUX_GPIO95__FUNC_ADSP_UTXD0 (MTK_PIN_NO(95) | 2)</div><div class='add'>+#define PINMUX_GPIO95__FUNC_MD32_0_TXD (MTK_PIN_NO(95) | 3)</div><div class='add'>+#define PINMUX_GPIO95__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(95) | 4)</div><div class='add'>+#define PINMUX_GPIO95__FUNC_TP_UTXD1_AO (MTK_PIN_NO(95) | 5)</div><div class='add'>+#define PINMUX_GPIO95__FUNC_TP_UTXD2_AO (MTK_PIN_NO(95) | 6)</div><div class='add'>+#define PINMUX_GPIO95__FUNC_MBISTWRITEEN_TRIGGER (MTK_PIN_NO(95) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0)</div><div class='add'>+#define PINMUX_GPIO96__FUNC_TDM_LRCK (MTK_PIN_NO(96) | 1)</div><div class='add'>+#define PINMUX_GPIO96__FUNC_I2S7_LRCK (MTK_PIN_NO(96) | 2)</div><div class='add'>+#define PINMUX_GPIO96__FUNC_I2S9_LRCK (MTK_PIN_NO(96) | 3)</div><div class='add'>+#define PINMUX_GPIO96__FUNC_SPI4_A_CLK (MTK_PIN_NO(96) | 4)</div><div class='add'>+#define PINMUX_GPIO96__FUNC_ADSP_JTAG0_TDI (MTK_PIN_NO(96) | 5)</div><div class='add'>+#define PINMUX_GPIO96__FUNC_CONN_BGF_DSP_L1_JDI (MTK_PIN_NO(96) | 6)</div><div class='add'>+#define PINMUX_GPIO96__FUNC_IO_JTAG_TDI (MTK_PIN_NO(96) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0)</div><div class='add'>+#define PINMUX_GPIO97__FUNC_TDM_BCK (MTK_PIN_NO(97) | 1)</div><div class='add'>+#define PINMUX_GPIO97__FUNC_I2S7_BCK (MTK_PIN_NO(97) | 2)</div><div class='add'>+#define PINMUX_GPIO97__FUNC_I2S9_BCK (MTK_PIN_NO(97) | 3)</div><div class='add'>+#define PINMUX_GPIO97__FUNC_SPI4_A_CSB (MTK_PIN_NO(97) | 4)</div><div class='add'>+#define PINMUX_GPIO97__FUNC_ADSP_JTAG0_TRSTN (MTK_PIN_NO(97) | 5)</div><div class='add'>+#define PINMUX_GPIO97__FUNC_CONN_BGF_DSP_L1_JINTP (MTK_PIN_NO(97) | 6)</div><div class='add'>+#define PINMUX_GPIO97__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(97) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0)</div><div class='add'>+#define PINMUX_GPIO98__FUNC_TDM_MCK (MTK_PIN_NO(98) | 1)</div><div class='add'>+#define PINMUX_GPIO98__FUNC_I2S7_MCK (MTK_PIN_NO(98) | 2)</div><div class='add'>+#define PINMUX_GPIO98__FUNC_I2S9_MCK (MTK_PIN_NO(98) | 3)</div><div class='add'>+#define PINMUX_GPIO98__FUNC_SPI4_A_MI (MTK_PIN_NO(98) | 4)</div><div class='add'>+#define PINMUX_GPIO98__FUNC_ADSP_JTAG0_TCK (MTK_PIN_NO(98) | 5)</div><div class='add'>+#define PINMUX_GPIO98__FUNC_CONN_BGF_DSP_L1_JCK (MTK_PIN_NO(98) | 6)</div><div class='add'>+#define PINMUX_GPIO98__FUNC_IO_JTAG_TCK (MTK_PIN_NO(98) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0)</div><div class='add'>+#define PINMUX_GPIO99__FUNC_TDM_DATA0 (MTK_PIN_NO(99) | 1)</div><div class='add'>+#define PINMUX_GPIO99__FUNC_I2S6_DI (MTK_PIN_NO(99) | 2)</div><div class='add'>+#define PINMUX_GPIO99__FUNC_I2S8_DI (MTK_PIN_NO(99) | 3)</div><div class='add'>+#define PINMUX_GPIO99__FUNC_SPI4_A_MO (MTK_PIN_NO(99) | 4)</div><div class='add'>+#define PINMUX_GPIO99__FUNC_ADSP_JTAG0_TDO (MTK_PIN_NO(99) | 5)</div><div class='add'>+#define PINMUX_GPIO99__FUNC_CONN_BGF_DSP_L1_JDO (MTK_PIN_NO(99) | 6)</div><div class='add'>+#define PINMUX_GPIO99__FUNC_IO_JTAG_TDO (MTK_PIN_NO(99) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0)</div><div class='add'>+#define PINMUX_GPIO100__FUNC_TDM_DATA1 (MTK_PIN_NO(100) | 1)</div><div class='add'>+#define PINMUX_GPIO100__FUNC_I2S7_DO (MTK_PIN_NO(100) | 2)</div><div class='add'>+#define PINMUX_GPIO100__FUNC_I2S9_DO (MTK_PIN_NO(100) | 3)</div><div class='add'>+#define PINMUX_GPIO100__FUNC_DP_TX_HPD (MTK_PIN_NO(100) | 4)</div><div class='add'>+#define PINMUX_GPIO100__FUNC_ADSP_JTAG0_TMS (MTK_PIN_NO(100) | 5)</div><div class='add'>+#define PINMUX_GPIO100__FUNC_CONN_BGF_DSP_L1_JMS (MTK_PIN_NO(100) | 6)</div><div class='add'>+#define PINMUX_GPIO100__FUNC_IO_JTAG_TMS (MTK_PIN_NO(100) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0)</div><div class='add'>+#define PINMUX_GPIO101__FUNC_TDM_DATA2 (MTK_PIN_NO(101) | 1)</div><div class='add'>+#define PINMUX_GPIO101__FUNC_DMIC1_CLK (MTK_PIN_NO(101) | 2)</div><div class='add'>+#define PINMUX_GPIO101__FUNC_SRCLKENAI0 (MTK_PIN_NO(101) | 3)</div><div class='add'>+#define PINMUX_GPIO101__FUNC_SPI5_B_CLK (MTK_PIN_NO(101) | 4)</div><div class='add'>+#define PINMUX_GPIO101__FUNC_CLKM0 (MTK_PIN_NO(101) | 5)</div><div class='add'>+#define PINMUX_GPIO101__FUNC_DAP_MD32_SWD (MTK_PIN_NO(101) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0)</div><div class='add'>+#define PINMUX_GPIO102__FUNC_TDM_DATA3 (MTK_PIN_NO(102) | 1)</div><div class='add'>+#define PINMUX_GPIO102__FUNC_DMIC1_DAT (MTK_PIN_NO(102) | 2)</div><div class='add'>+#define PINMUX_GPIO102__FUNC_SRCLKENAI1 (MTK_PIN_NO(102) | 3)</div><div class='add'>+#define PINMUX_GPIO102__FUNC_SPI5_B_CSB (MTK_PIN_NO(102) | 4)</div><div class='add'>+#define PINMUX_GPIO102__FUNC_DP_TX_HPD (MTK_PIN_NO(102) | 5)</div><div class='add'>+#define PINMUX_GPIO102__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(102) | 6)</div><div class='add'>+#define PINMUX_GPIO102__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(102) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0)</div><div class='add'>+#define PINMUX_GPIO103__FUNC_SPI0_A_MI (MTK_PIN_NO(103) | 1)</div><div class='add'>+#define PINMUX_GPIO103__FUNC_SCP_SPI0_MI (MTK_PIN_NO(103) | 2)</div><div class='add'>+#define PINMUX_GPIO103__FUNC_DFD_TDO (MTK_PIN_NO(103) | 5)</div><div class='add'>+#define PINMUX_GPIO103__FUNC_SPM_JTAG_TDO (MTK_PIN_NO(103) | 6)</div><div class='add'>+#define PINMUX_GPIO103__FUNC_JTDO_SEL1 (MTK_PIN_NO(103) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0)</div><div class='add'>+#define PINMUX_GPIO104__FUNC_SPI0_A_CSB (MTK_PIN_NO(104) | 1)</div><div class='add'>+#define PINMUX_GPIO104__FUNC_SCP_SPI0_CS (MTK_PIN_NO(104) | 2)</div><div class='add'>+#define PINMUX_GPIO104__FUNC_DFD_TMS (MTK_PIN_NO(104) | 5)</div><div class='add'>+#define PINMUX_GPIO104__FUNC_SPM_JTAG_TMS (MTK_PIN_NO(104) | 6)</div><div class='add'>+#define PINMUX_GPIO104__FUNC_JTMS_SEL1 (MTK_PIN_NO(104) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0)</div><div class='add'>+#define PINMUX_GPIO105__FUNC_SPI0_A_MO (MTK_PIN_NO(105) | 1)</div><div class='add'>+#define PINMUX_GPIO105__FUNC_SCP_SPI0_MO (MTK_PIN_NO(105) | 2)</div><div class='add'>+#define PINMUX_GPIO105__FUNC_SCP_SDA0 (MTK_PIN_NO(105) | 3)</div><div class='add'>+#define PINMUX_GPIO105__FUNC_DFD_TDI (MTK_PIN_NO(105) | 5)</div><div class='add'>+#define PINMUX_GPIO105__FUNC_SPM_JTAG_TDI (MTK_PIN_NO(105) | 6)</div><div class='add'>+#define PINMUX_GPIO105__FUNC_JTDI_SEL1 (MTK_PIN_NO(105) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0)</div><div class='add'>+#define PINMUX_GPIO106__FUNC_SPI0_A_CLK (MTK_PIN_NO(106) | 1)</div><div class='add'>+#define PINMUX_GPIO106__FUNC_SCP_SPI0_CK (MTK_PIN_NO(106) | 2)</div><div class='add'>+#define PINMUX_GPIO106__FUNC_SCP_SCL0 (MTK_PIN_NO(106) | 3)</div><div class='add'>+#define PINMUX_GPIO106__FUNC_DFD_TCK_XI (MTK_PIN_NO(106) | 5)</div><div class='add'>+#define PINMUX_GPIO106__FUNC_SPM_JTAG_TCK (MTK_PIN_NO(106) | 6)</div><div class='add'>+#define PINMUX_GPIO106__FUNC_JTCK_SEL1 (MTK_PIN_NO(106) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0)</div><div class='add'>+#define PINMUX_GPIO107__FUNC_DMIC_CLK (MTK_PIN_NO(107) | 1)</div><div class='add'>+#define PINMUX_GPIO107__FUNC_PWM_0 (MTK_PIN_NO(107) | 2)</div><div class='add'>+#define PINMUX_GPIO107__FUNC_CLKM2 (MTK_PIN_NO(107) | 3)</div><div class='add'>+#define PINMUX_GPIO107__FUNC_SPI5_B_MI (MTK_PIN_NO(107) | 4)</div><div class='add'>+#define PINMUX_GPIO107__FUNC_SPM_JTAG_TRSTN (MTK_PIN_NO(107) | 6)</div><div class='add'>+#define PINMUX_GPIO107__FUNC_JTRSTN_SEL1 (MTK_PIN_NO(107) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0)</div><div class='add'>+#define PINMUX_GPIO108__FUNC_DMIC_DAT (MTK_PIN_NO(108) | 1)</div><div class='add'>+#define PINMUX_GPIO108__FUNC_PWM_1 (MTK_PIN_NO(108) | 2)</div><div class='add'>+#define PINMUX_GPIO108__FUNC_CLKM3 (MTK_PIN_NO(108) | 3)</div><div class='add'>+#define PINMUX_GPIO108__FUNC_SPI5_B_MO (MTK_PIN_NO(108) | 4)</div><div class='add'>+#define PINMUX_GPIO108__FUNC_DAP_SONIC_SWD (MTK_PIN_NO(108) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0)</div><div class='add'>+#define PINMUX_GPIO109__FUNC_I2S1_MCK (MTK_PIN_NO(109) | 1)</div><div class='add'>+#define PINMUX_GPIO109__FUNC_I2S3_MCK (MTK_PIN_NO(109) | 2)</div><div class='add'>+#define PINMUX_GPIO109__FUNC_I2S2_MCK (MTK_PIN_NO(109) | 3)</div><div class='add'>+#define PINMUX_GPIO109__FUNC_DP_TX_HPD (MTK_PIN_NO(109) | 4)</div><div class='add'>+#define PINMUX_GPIO109__FUNC_I2S2_MCK_A (MTK_PIN_NO(109) | 5)</div><div class='add'>+#define PINMUX_GPIO109__FUNC_SRCLKENAI0 (MTK_PIN_NO(109) | 6)</div><div class='add'>+#define PINMUX_GPIO109__FUNC_DAP_SONIC_SWCK (MTK_PIN_NO(109) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0)</div><div class='add'>+#define PINMUX_GPIO110__FUNC_I2S1_BCK (MTK_PIN_NO(110) | 1)</div><div class='add'>+#define PINMUX_GPIO110__FUNC_I2S3_BCK (MTK_PIN_NO(110) | 2)</div><div class='add'>+#define PINMUX_GPIO110__FUNC_I2S2_BCK (MTK_PIN_NO(110) | 3)</div><div class='add'>+#define PINMUX_GPIO110__FUNC_PCM0_CLK (MTK_PIN_NO(110) | 4)</div><div class='add'>+#define PINMUX_GPIO110__FUNC_I2S2_BCK_A (MTK_PIN_NO(110) | 5)</div><div class='add'>+#define PINMUX_GPIO110__FUNC_CONN_BGF_MCU_TDO (MTK_PIN_NO(110) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0)</div><div class='add'>+#define PINMUX_GPIO111__FUNC_I2S1_LRCK (MTK_PIN_NO(111) | 1)</div><div class='add'>+#define PINMUX_GPIO111__FUNC_I2S3_LRCK (MTK_PIN_NO(111) | 2)</div><div class='add'>+#define PINMUX_GPIO111__FUNC_I2S2_LRCK (MTK_PIN_NO(111) | 3)</div><div class='add'>+#define PINMUX_GPIO111__FUNC_PCM0_SYNC (MTK_PIN_NO(111) | 4)</div><div class='add'>+#define PINMUX_GPIO111__FUNC_I2S2_LRCK_A (MTK_PIN_NO(111) | 5)</div><div class='add'>+#define PINMUX_GPIO111__FUNC_CONN_BGF_MCU_TDI (MTK_PIN_NO(111) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0)</div><div class='add'>+#define PINMUX_GPIO112__FUNC_I2S2_DI (MTK_PIN_NO(112) | 1)</div><div class='add'>+#define PINMUX_GPIO112__FUNC_I2S0_DI (MTK_PIN_NO(112) | 2)</div><div class='add'>+#define PINMUX_GPIO112__FUNC_I2S2_DI2 (MTK_PIN_NO(112) | 3)</div><div class='add'>+#define PINMUX_GPIO112__FUNC_PCM0_DI (MTK_PIN_NO(112) | 4)</div><div class='add'>+#define PINMUX_GPIO112__FUNC_I2S2_DI_A (MTK_PIN_NO(112) | 5)</div><div class='add'>+#define PINMUX_GPIO112__FUNC_CONN_BGF_MCU_TMS (MTK_PIN_NO(112) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0)</div><div class='add'>+#define PINMUX_GPIO113__FUNC_I2S1_DO (MTK_PIN_NO(113) | 1)</div><div class='add'>+#define PINMUX_GPIO113__FUNC_I2S3_DO (MTK_PIN_NO(113) | 2)</div><div class='add'>+#define PINMUX_GPIO113__FUNC_I2S5_DO (MTK_PIN_NO(113) | 3)</div><div class='add'>+#define PINMUX_GPIO113__FUNC_PCM0_DO (MTK_PIN_NO(113) | 4)</div><div class='add'>+#define PINMUX_GPIO113__FUNC_I2S2_DI2 (MTK_PIN_NO(113) | 5)</div><div class='add'>+#define PINMUX_GPIO113__FUNC_CONN_BGF_MCU_TCK (MTK_PIN_NO(113) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0)</div><div class='add'>+#define PINMUX_GPIO114__FUNC_SPI2_MI (MTK_PIN_NO(114) | 1)</div><div class='add'>+#define PINMUX_GPIO114__FUNC_SCP_SPI2_MI (MTK_PIN_NO(114) | 2)</div><div class='add'>+#define PINMUX_GPIO114__FUNC_CONN_BGF_MCU_TRST_B (MTK_PIN_NO(114) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0)</div><div class='add'>+#define PINMUX_GPIO115__FUNC_SPI2_CSB (MTK_PIN_NO(115) | 1)</div><div class='add'>+#define PINMUX_GPIO115__FUNC_SCP_SPI2_CS (MTK_PIN_NO(115) | 2)</div><div class='add'>+#define PINMUX_GPIO115__FUNC_CONN_BGF_MCU_DBGI_N (MTK_PIN_NO(115) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0)</div><div class='add'>+#define PINMUX_GPIO116__FUNC_SPI2_MO (MTK_PIN_NO(116) | 1)</div><div class='add'>+#define PINMUX_GPIO116__FUNC_SCP_SPI2_MO (MTK_PIN_NO(116) | 2)</div><div class='add'>+#define PINMUX_GPIO116__FUNC_SCP_SDA1 (MTK_PIN_NO(116) | 3)</div><div class='add'>+#define PINMUX_GPIO116__FUNC_CONN_BGF_MCU_DBGACK_N (MTK_PIN_NO(116) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0)</div><div class='add'>+#define PINMUX_GPIO117__FUNC_SPI2_CLK (MTK_PIN_NO(117) | 1)</div><div class='add'>+#define PINMUX_GPIO117__FUNC_SCP_SPI2_CK (MTK_PIN_NO(117) | 2)</div><div class='add'>+#define PINMUX_GPIO117__FUNC_SCP_SCL1 (MTK_PIN_NO(117) | 3)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0)</div><div class='add'>+#define PINMUX_GPIO118__FUNC_SCL1 (MTK_PIN_NO(118) | 1)</div><div class='add'>+#define PINMUX_GPIO118__FUNC_SCP_SCL0 (MTK_PIN_NO(118) | 2)</div><div class='add'>+#define PINMUX_GPIO118__FUNC_SCP_SCL1 (MTK_PIN_NO(118) | 3)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0)</div><div class='add'>+#define PINMUX_GPIO119__FUNC_SDA1 (MTK_PIN_NO(119) | 1)</div><div class='add'>+#define PINMUX_GPIO119__FUNC_SCP_SDA0 (MTK_PIN_NO(119) | 2)</div><div class='add'>+#define PINMUX_GPIO119__FUNC_SCP_SDA1 (MTK_PIN_NO(119) | 3)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0)</div><div class='add'>+#define PINMUX_GPIO120__FUNC_SCL9 (MTK_PIN_NO(120) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0)</div><div class='add'>+#define PINMUX_GPIO121__FUNC_SDA9 (MTK_PIN_NO(121) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0)</div><div class='add'>+#define PINMUX_GPIO122__FUNC_SCL8 (MTK_PIN_NO(122) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0)</div><div class='add'>+#define PINMUX_GPIO123__FUNC_SDA8 (MTK_PIN_NO(123) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0)</div><div class='add'>+#define PINMUX_GPIO124__FUNC_SCL7 (MTK_PIN_NO(124) | 1)</div><div class='add'>+#define PINMUX_GPIO124__FUNC_DMIC1_CLK (MTK_PIN_NO(124) | 2)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0)</div><div class='add'>+#define PINMUX_GPIO125__FUNC_SDA7 (MTK_PIN_NO(125) | 1)</div><div class='add'>+#define PINMUX_GPIO125__FUNC_DMIC1_DAT (MTK_PIN_NO(125) | 2)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0)</div><div class='add'>+#define PINMUX_GPIO126__FUNC_CMFLASH0 (MTK_PIN_NO(126) | 1)</div><div class='add'>+#define PINMUX_GPIO126__FUNC_PWM_2 (MTK_PIN_NO(126) | 2)</div><div class='add'>+#define PINMUX_GPIO126__FUNC_TP_UCTS1_AO (MTK_PIN_NO(126) | 3)</div><div class='add'>+#define PINMUX_GPIO126__FUNC_UCTS0 (MTK_PIN_NO(126) | 4)</div><div class='add'>+#define PINMUX_GPIO126__FUNC_SCL11 (MTK_PIN_NO(126) | 5)</div><div class='add'>+#define PINMUX_GPIO126__FUNC_MD32_1_GPIO0 (MTK_PIN_NO(126) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0)</div><div class='add'>+#define PINMUX_GPIO127__FUNC_CMFLASH1 (MTK_PIN_NO(127) | 1)</div><div class='add'>+#define PINMUX_GPIO127__FUNC_PWM_3 (MTK_PIN_NO(127) | 2)</div><div class='add'>+#define PINMUX_GPIO127__FUNC_TP_URTS1_AO (MTK_PIN_NO(127) | 3)</div><div class='add'>+#define PINMUX_GPIO127__FUNC_URTS0 (MTK_PIN_NO(127) | 4)</div><div class='add'>+#define PINMUX_GPIO127__FUNC_SDA11 (MTK_PIN_NO(127) | 5)</div><div class='add'>+#define PINMUX_GPIO127__FUNC_MD32_1_GPIO1 (MTK_PIN_NO(127) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0)</div><div class='add'>+#define PINMUX_GPIO128__FUNC_CMFLASH2 (MTK_PIN_NO(128) | 1)</div><div class='add'>+#define PINMUX_GPIO128__FUNC_PWM_0 (MTK_PIN_NO(128) | 2)</div><div class='add'>+#define PINMUX_GPIO128__FUNC_TP_UCTS2_AO (MTK_PIN_NO(128) | 3)</div><div class='add'>+#define PINMUX_GPIO128__FUNC_UCTS1 (MTK_PIN_NO(128) | 4)</div><div class='add'>+#define PINMUX_GPIO128__FUNC_SCL12 (MTK_PIN_NO(128) | 5)</div><div class='add'>+#define PINMUX_GPIO128__FUNC_MD32_1_GPIO2 (MTK_PIN_NO(128) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0)</div><div class='add'>+#define PINMUX_GPIO129__FUNC_CMFLASH3 (MTK_PIN_NO(129) | 1)</div><div class='add'>+#define PINMUX_GPIO129__FUNC_PWM_1 (MTK_PIN_NO(129) | 2)</div><div class='add'>+#define PINMUX_GPIO129__FUNC_TP_URTS2_AO (MTK_PIN_NO(129) | 3)</div><div class='add'>+#define PINMUX_GPIO129__FUNC_URTS1 (MTK_PIN_NO(129) | 4)</div><div class='add'>+#define PINMUX_GPIO129__FUNC_SDA12 (MTK_PIN_NO(129) | 5)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0)</div><div class='add'>+#define PINMUX_GPIO130__FUNC_CMVREF0 (MTK_PIN_NO(130) | 1)</div><div class='add'>+#define PINMUX_GPIO130__FUNC_ANT_SEL10 (MTK_PIN_NO(130) | 2)</div><div class='add'>+#define PINMUX_GPIO130__FUNC_SCP_JTAG0_TDO (MTK_PIN_NO(130) | 3)</div><div class='add'>+#define PINMUX_GPIO130__FUNC_MD32_0_JTAG_TDO (MTK_PIN_NO(130) | 4)</div><div class='add'>+#define PINMUX_GPIO130__FUNC_SCL11 (MTK_PIN_NO(130) | 5)</div><div class='add'>+#define PINMUX_GPIO130__FUNC_CONN_WF_MCU_TDO (MTK_PIN_NO(130) | 6)</div><div class='add'>+#define PINMUX_GPIO130__FUNC_DBG_MON_A23 (MTK_PIN_NO(130) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0)</div><div class='add'>+#define PINMUX_GPIO131__FUNC_CMVREF1 (MTK_PIN_NO(131) | 1)</div><div class='add'>+#define PINMUX_GPIO131__FUNC_ANT_SEL11 (MTK_PIN_NO(131) | 2)</div><div class='add'>+#define PINMUX_GPIO131__FUNC_SCP_JTAG0_TDI (MTK_PIN_NO(131) | 3)</div><div class='add'>+#define PINMUX_GPIO131__FUNC_MD32_0_JTAG_TDI (MTK_PIN_NO(131) | 4)</div><div class='add'>+#define PINMUX_GPIO131__FUNC_SDA11 (MTK_PIN_NO(131) | 5)</div><div class='add'>+#define PINMUX_GPIO131__FUNC_CONN_WF_MCU_TDI (MTK_PIN_NO(131) | 6)</div><div class='add'>+#define PINMUX_GPIO131__FUNC_DBG_MON_A26 (MTK_PIN_NO(131) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0)</div><div class='add'>+#define PINMUX_GPIO132__FUNC_CMVREF2 (MTK_PIN_NO(132) | 1)</div><div class='add'>+#define PINMUX_GPIO132__FUNC_ANT_SEL12 (MTK_PIN_NO(132) | 2)</div><div class='add'>+#define PINMUX_GPIO132__FUNC_SCP_JTAG0_TMS (MTK_PIN_NO(132) | 3)</div><div class='add'>+#define PINMUX_GPIO132__FUNC_MD32_0_JTAG_TMS (MTK_PIN_NO(132) | 4)</div><div class='add'>+#define PINMUX_GPIO132__FUNC_CONN_WF_MCU_TMS (MTK_PIN_NO(132) | 6)</div><div class='add'>+#define PINMUX_GPIO132__FUNC_DBG_MON_A28 (MTK_PIN_NO(132) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0)</div><div class='add'>+#define PINMUX_GPIO133__FUNC_CMVREF3 (MTK_PIN_NO(133) | 1)</div><div class='add'>+#define PINMUX_GPIO133__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(133) | 2)</div><div class='add'>+#define PINMUX_GPIO133__FUNC_SCP_JTAG0_TCK (MTK_PIN_NO(133) | 3)</div><div class='add'>+#define PINMUX_GPIO133__FUNC_MD32_0_JTAG_TCK (MTK_PIN_NO(133) | 4)</div><div class='add'>+#define PINMUX_GPIO133__FUNC_CONN_WF_MCU_TCK (MTK_PIN_NO(133) | 6)</div><div class='add'>+#define PINMUX_GPIO133__FUNC_DBG_MON_A24 (MTK_PIN_NO(133) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0)</div><div class='add'>+#define PINMUX_GPIO134__FUNC_CMVREF4 (MTK_PIN_NO(134) | 1)</div><div class='add'>+#define PINMUX_GPIO134__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(134) | 2)</div><div class='add'>+#define PINMUX_GPIO134__FUNC_SCP_JTAG0_TRSTN (MTK_PIN_NO(134) | 3)</div><div class='add'>+#define PINMUX_GPIO134__FUNC_MD32_0_JTAG_TRST (MTK_PIN_NO(134) | 4)</div><div class='add'>+#define PINMUX_GPIO134__FUNC_CONN_WF_MCU_TRST_B (MTK_PIN_NO(134) | 6)</div><div class='add'>+#define PINMUX_GPIO134__FUNC_DBG_MON_A27 (MTK_PIN_NO(134) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0)</div><div class='add'>+#define PINMUX_GPIO135__FUNC_PWM_0 (MTK_PIN_NO(135) | 1)</div><div class='add'>+#define PINMUX_GPIO135__FUNC_SRCLKENAI1 (MTK_PIN_NO(135) | 2)</div><div class='add'>+#define PINMUX_GPIO135__FUNC_MD_URXD0 (MTK_PIN_NO(135) | 3)</div><div class='add'>+#define PINMUX_GPIO135__FUNC_MD32_0_RXD (MTK_PIN_NO(135) | 4)</div><div class='add'>+#define PINMUX_GPIO135__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(135) | 5)</div><div class='add'>+#define PINMUX_GPIO135__FUNC_CONN_WF_MCU_DBGI_N (MTK_PIN_NO(135) | 6)</div><div class='add'>+#define PINMUX_GPIO135__FUNC_DBG_MON_A29 (MTK_PIN_NO(135) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0)</div><div class='add'>+#define PINMUX_GPIO136__FUNC_CMMCLK3 (MTK_PIN_NO(136) | 1)</div><div class='add'>+#define PINMUX_GPIO136__FUNC_CLKM1 (MTK_PIN_NO(136) | 2)</div><div class='add'>+#define PINMUX_GPIO136__FUNC_MD_UTXD0 (MTK_PIN_NO(136) | 3)</div><div class='add'>+#define PINMUX_GPIO136__FUNC_MD32_0_TXD (MTK_PIN_NO(136) | 4)</div><div class='add'>+#define PINMUX_GPIO136__FUNC_CONN_BT_TXD (MTK_PIN_NO(136) | 5)</div><div class='add'>+#define PINMUX_GPIO136__FUNC_CONN_WF_MCU_DBGACK_N (MTK_PIN_NO(136) | 6)</div><div class='add'>+#define PINMUX_GPIO136__FUNC_DBG_MON_A25 (MTK_PIN_NO(136) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0)</div><div class='add'>+#define PINMUX_GPIO137__FUNC_CMMCLK4 (MTK_PIN_NO(137) | 1)</div><div class='add'>+#define PINMUX_GPIO137__FUNC_CLKM2 (MTK_PIN_NO(137) | 2)</div><div class='add'>+#define PINMUX_GPIO137__FUNC_MD_URXD1 (MTK_PIN_NO(137) | 3)</div><div class='add'>+#define PINMUX_GPIO137__FUNC_MD32_1_RXD (MTK_PIN_NO(137) | 4)</div><div class='add'>+#define PINMUX_GPIO137__FUNC_ILDO_DOUT0 (MTK_PIN_NO(137) | 5)</div><div class='add'>+#define PINMUX_GPIO137__FUNC_CONN_BGF_UART0_RXD (MTK_PIN_NO(137) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0)</div><div class='add'>+#define PINMUX_GPIO138__FUNC_CMMCLK5 (MTK_PIN_NO(138) | 1)</div><div class='add'>+#define PINMUX_GPIO138__FUNC_CLKM3 (MTK_PIN_NO(138) | 2)</div><div class='add'>+#define PINMUX_GPIO138__FUNC_MD_UTXD1 (MTK_PIN_NO(138) | 3)</div><div class='add'>+#define PINMUX_GPIO138__FUNC_MD32_1_TXD (MTK_PIN_NO(138) | 4)</div><div class='add'>+#define PINMUX_GPIO138__FUNC_ILDO_DOUT1 (MTK_PIN_NO(138) | 5)</div><div class='add'>+#define PINMUX_GPIO138__FUNC_CONN_BGF_UART0_TXD (MTK_PIN_NO(138) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0)</div><div class='add'>+#define PINMUX_GPIO139__FUNC_SCL4 (MTK_PIN_NO(139) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0)</div><div class='add'>+#define PINMUX_GPIO140__FUNC_SDA4 (MTK_PIN_NO(140) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0)</div><div class='add'>+#define PINMUX_GPIO141__FUNC_SCL2 (MTK_PIN_NO(141) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0)</div><div class='add'>+#define PINMUX_GPIO142__FUNC_SDA2 (MTK_PIN_NO(142) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0)</div><div class='add'>+#define PINMUX_GPIO143__FUNC_CMVREF0 (MTK_PIN_NO(143) | 1)</div><div class='add'>+#define PINMUX_GPIO143__FUNC_SPI3_CLK (MTK_PIN_NO(143) | 2)</div><div class='add'>+#define PINMUX_GPIO143__FUNC_ADSP_JTAG1_TDO (MTK_PIN_NO(143) | 3)</div><div class='add'>+#define PINMUX_GPIO143__FUNC_SCP_JTAG1_TDO (MTK_PIN_NO(143) | 4)</div><div class='add'>+#define PINMUX_GPIO143__FUNC_MD32_1_JTAG_TDO (MTK_PIN_NO(143) | 5)</div><div class='add'>+#define PINMUX_GPIO143__FUNC_CONN_BGF_DSP_L5_JDO (MTK_PIN_NO(143) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0)</div><div class='add'>+#define PINMUX_GPIO144__FUNC_CMVREF1 (MTK_PIN_NO(144) | 1)</div><div class='add'>+#define PINMUX_GPIO144__FUNC_SPI3_CSB (MTK_PIN_NO(144) | 2)</div><div class='add'>+#define PINMUX_GPIO144__FUNC_ADSP_JTAG1_TDI (MTK_PIN_NO(144) | 3)</div><div class='add'>+#define PINMUX_GPIO144__FUNC_SCP_JTAG1_TDI (MTK_PIN_NO(144) | 4)</div><div class='add'>+#define PINMUX_GPIO144__FUNC_MD32_1_JTAG_TDI (MTK_PIN_NO(144) | 5)</div><div class='add'>+#define PINMUX_GPIO144__FUNC_CONN_BGF_DSP_L5_JDI (MTK_PIN_NO(144) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0)</div><div class='add'>+#define PINMUX_GPIO145__FUNC_CMVREF2 (MTK_PIN_NO(145) | 1)</div><div class='add'>+#define PINMUX_GPIO145__FUNC_SPI3_MI (MTK_PIN_NO(145) | 2)</div><div class='add'>+#define PINMUX_GPIO145__FUNC_ADSP_JTAG1_TMS (MTK_PIN_NO(145) | 3)</div><div class='add'>+#define PINMUX_GPIO145__FUNC_SCP_JTAG1_TMS (MTK_PIN_NO(145) | 4)</div><div class='add'>+#define PINMUX_GPIO145__FUNC_MD32_1_JTAG_TMS (MTK_PIN_NO(145) | 5)</div><div class='add'>+#define PINMUX_GPIO145__FUNC_CONN_BGF_DSP_L5_JMS (MTK_PIN_NO(145) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0)</div><div class='add'>+#define PINMUX_GPIO146__FUNC_CMVREF3 (MTK_PIN_NO(146) | 1)</div><div class='add'>+#define PINMUX_GPIO146__FUNC_SPI3_MO (MTK_PIN_NO(146) | 2)</div><div class='add'>+#define PINMUX_GPIO146__FUNC_ADSP_JTAG1_TCK (MTK_PIN_NO(146) | 3)</div><div class='add'>+#define PINMUX_GPIO146__FUNC_SCP_JTAG1_TCK (MTK_PIN_NO(146) | 4)</div><div class='add'>+#define PINMUX_GPIO146__FUNC_MD32_1_JTAG_TCK (MTK_PIN_NO(146) | 5)</div><div class='add'>+#define PINMUX_GPIO146__FUNC_CONN_BGF_DSP_L5_JCK (MTK_PIN_NO(146) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0)</div><div class='add'>+#define PINMUX_GPIO147__FUNC_CMVREF4 (MTK_PIN_NO(147) | 1)</div><div class='add'>+#define PINMUX_GPIO147__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(147) | 2)</div><div class='add'>+#define PINMUX_GPIO147__FUNC_ADSP_JTAG1_TRSTN (MTK_PIN_NO(147) | 3)</div><div class='add'>+#define PINMUX_GPIO147__FUNC_SCP_JTAG1_TRSTN (MTK_PIN_NO(147) | 4)</div><div class='add'>+#define PINMUX_GPIO147__FUNC_MD32_1_JTAG_TRST (MTK_PIN_NO(147) | 5)</div><div class='add'>+#define PINMUX_GPIO147__FUNC_CONN_BGF_DSP_L5_JINTP (MTK_PIN_NO(147) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0)</div><div class='add'>+#define PINMUX_GPIO148__FUNC_PWM_1 (MTK_PIN_NO(148) | 1)</div><div class='add'>+#define PINMUX_GPIO148__FUNC_AGPS_SYNC (MTK_PIN_NO(148) | 2)</div><div class='add'>+#define PINMUX_GPIO148__FUNC_CMMCLK5 (MTK_PIN_NO(148) | 3)</div><div class='add'>+#define PINMUX_GPIO148__FUNC_CONN_WF_MCU_AICE_TMSC (MTK_PIN_NO(148) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0)</div><div class='add'>+#define PINMUX_GPIO149__FUNC_CMMCLK0 (MTK_PIN_NO(149) | 1)</div><div class='add'>+#define PINMUX_GPIO149__FUNC_CLKM0 (MTK_PIN_NO(149) | 2)</div><div class='add'>+#define PINMUX_GPIO149__FUNC_MD32_0_GPIO0 (MTK_PIN_NO(149) | 3)</div><div class='add'>+#define PINMUX_GPIO149__FUNC_CONN_WF_MCU_AICE_TCKC (MTK_PIN_NO(149) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0)</div><div class='add'>+#define PINMUX_GPIO150__FUNC_CMMCLK1 (MTK_PIN_NO(150) | 1)</div><div class='add'>+#define PINMUX_GPIO150__FUNC_CLKM1 (MTK_PIN_NO(150) | 2)</div><div class='add'>+#define PINMUX_GPIO150__FUNC_MD32_0_GPIO1 (MTK_PIN_NO(150) | 3)</div><div class='add'>+#define PINMUX_GPIO150__FUNC_CONN_BGF_MCU_AICE_TMSC (MTK_PIN_NO(150) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0)</div><div class='add'>+#define PINMUX_GPIO151__FUNC_CMMCLK2 (MTK_PIN_NO(151) | 1)</div><div class='add'>+#define PINMUX_GPIO151__FUNC_CLKM2 (MTK_PIN_NO(151) | 2)</div><div class='add'>+#define PINMUX_GPIO151__FUNC_MD32_0_GPIO2 (MTK_PIN_NO(151) | 3)</div><div class='add'>+#define PINMUX_GPIO151__FUNC_CONN_BGF_MCU_AICE_TCKC (MTK_PIN_NO(151) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0)</div><div class='add'>+#define PINMUX_GPIO152__FUNC_KPROW1 (MTK_PIN_NO(152) | 1)</div><div class='add'>+#define PINMUX_GPIO152__FUNC_PWM_2 (MTK_PIN_NO(152) | 2)</div><div class='add'>+#define PINMUX_GPIO152__FUNC_IDDIG (MTK_PIN_NO(152) | 3)</div><div class='add'>+#define PINMUX_GPIO152__FUNC_DP_TX_HPD (MTK_PIN_NO(152) | 4)</div><div class='add'>+#define PINMUX_GPIO152__FUNC_DSI1_TE (MTK_PIN_NO(152) | 5)</div><div class='add'>+#define PINMUX_GPIO152__FUNC_MBISTREADEN_TRIGGER (MTK_PIN_NO(152) | 6)</div><div class='add'>+#define PINMUX_GPIO152__FUNC_DBG_MON_B2 (MTK_PIN_NO(152) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0)</div><div class='add'>+#define PINMUX_GPIO153__FUNC_KPROW0 (MTK_PIN_NO(153) | 1)</div><div class='add'>+#define PINMUX_GPIO153__FUNC_DBG_MON_B1 (MTK_PIN_NO(153) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0)</div><div class='add'>+#define PINMUX_GPIO154__FUNC_KPCOL0 (MTK_PIN_NO(154) | 1)</div><div class='add'>+#define PINMUX_GPIO154__FUNC_DBG_MON_A32 (MTK_PIN_NO(154) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0)</div><div class='add'>+#define PINMUX_GPIO155__FUNC_KPCOL1 (MTK_PIN_NO(155) | 1)</div><div class='add'>+#define PINMUX_GPIO155__FUNC_PWM_3 (MTK_PIN_NO(155) | 2)</div><div class='add'>+#define PINMUX_GPIO155__FUNC_USB_DRVVBUS (MTK_PIN_NO(155) | 3)</div><div class='add'>+#define PINMUX_GPIO155__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(155) | 4)</div><div class='add'>+#define PINMUX_GPIO155__FUNC_LCM1_RST (MTK_PIN_NO(155) | 5)</div><div class='add'>+#define PINMUX_GPIO155__FUNC_MBISTWRITEEN_TRIGGER (MTK_PIN_NO(155) | 6)</div><div class='add'>+#define PINMUX_GPIO155__FUNC_DBG_MON_B0 (MTK_PIN_NO(155) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0)</div><div class='add'>+#define PINMUX_GPIO156__FUNC_SPI1_A_CLK (MTK_PIN_NO(156) | 1)</div><div class='add'>+#define PINMUX_GPIO156__FUNC_SCP_SPI1_A_CK (MTK_PIN_NO(156) | 2)</div><div class='add'>+#define PINMUX_GPIO156__FUNC_MRG_CLK (MTK_PIN_NO(156) | 3)</div><div class='add'>+#define PINMUX_GPIO156__FUNC_AGPS_SYNC (MTK_PIN_NO(156) | 4)</div><div class='add'>+#define PINMUX_GPIO156__FUNC_SCL12 (MTK_PIN_NO(156) | 5)</div><div class='add'>+#define PINMUX_GPIO156__FUNC_DBG_MON_B3 (MTK_PIN_NO(156) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0)</div><div class='add'>+#define PINMUX_GPIO157__FUNC_SPI1_A_CSB (MTK_PIN_NO(157) | 1)</div><div class='add'>+#define PINMUX_GPIO157__FUNC_SCP_SPI1_A_CS (MTK_PIN_NO(157) | 2)</div><div class='add'>+#define PINMUX_GPIO157__FUNC_MRG_SYNC (MTK_PIN_NO(157) | 3)</div><div class='add'>+#define PINMUX_GPIO157__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(157) | 4)</div><div class='add'>+#define PINMUX_GPIO157__FUNC_SDA12 (MTK_PIN_NO(157) | 5)</div><div class='add'>+#define PINMUX_GPIO157__FUNC_DBG_MON_B4 (MTK_PIN_NO(157) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0)</div><div class='add'>+#define PINMUX_GPIO158__FUNC_SPI1_A_MI (MTK_PIN_NO(158) | 1)</div><div class='add'>+#define PINMUX_GPIO158__FUNC_SCP_SPI1_A_MI (MTK_PIN_NO(158) | 2)</div><div class='add'>+#define PINMUX_GPIO158__FUNC_MRG_DI (MTK_PIN_NO(158) | 3)</div><div class='add'>+#define PINMUX_GPIO158__FUNC_PTA_RXD (MTK_PIN_NO(158) | 4)</div><div class='add'>+#define PINMUX_GPIO158__FUNC_SCL13 (MTK_PIN_NO(158) | 5)</div><div class='add'>+#define PINMUX_GPIO158__FUNC_DBG_MON_B5 (MTK_PIN_NO(158) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0)</div><div class='add'>+#define PINMUX_GPIO159__FUNC_SPI1_A_MO (MTK_PIN_NO(159) | 1)</div><div class='add'>+#define PINMUX_GPIO159__FUNC_SCP_SPI1_A_MO (MTK_PIN_NO(159) | 2)</div><div class='add'>+#define PINMUX_GPIO159__FUNC_MRG_DO (MTK_PIN_NO(159) | 3)</div><div class='add'>+#define PINMUX_GPIO159__FUNC_PTA_TXD (MTK_PIN_NO(159) | 4)</div><div class='add'>+#define PINMUX_GPIO159__FUNC_SDA13 (MTK_PIN_NO(159) | 5)</div><div class='add'>+#define PINMUX_GPIO159__FUNC_DBG_MON_B6 (MTK_PIN_NO(159) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0)</div><div class='add'>+#define PINMUX_GPIO160__FUNC_SCL3 (MTK_PIN_NO(160) | 1)</div><div class='add'>+#define PINMUX_GPIO160__FUNC_SCP_SCL0 (MTK_PIN_NO(160) | 2)</div><div class='add'>+#define PINMUX_GPIO160__FUNC_SCP_SCL1 (MTK_PIN_NO(160) | 3)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0)</div><div class='add'>+#define PINMUX_GPIO161__FUNC_SDA3 (MTK_PIN_NO(161) | 1)</div><div class='add'>+#define PINMUX_GPIO161__FUNC_SCP_SDA0 (MTK_PIN_NO(161) | 2)</div><div class='add'>+#define PINMUX_GPIO161__FUNC_SCP_SDA1 (MTK_PIN_NO(161) | 3)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0)</div><div class='add'>+#define PINMUX_GPIO162__FUNC_ANT_SEL0 (MTK_PIN_NO(162) | 1)</div><div class='add'>+#define PINMUX_GPIO162__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(162) | 2)</div><div class='add'>+#define PINMUX_GPIO162__FUNC_DBG_MON_B7 (MTK_PIN_NO(162) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0)</div><div class='add'>+#define PINMUX_GPIO163__FUNC_ANT_SEL1 (MTK_PIN_NO(163) | 1)</div><div class='add'>+#define PINMUX_GPIO163__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(163) | 2)</div><div class='add'>+#define PINMUX_GPIO163__FUNC_DBG_MON_B8 (MTK_PIN_NO(163) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0)</div><div class='add'>+#define PINMUX_GPIO164__FUNC_ANT_SEL2 (MTK_PIN_NO(164) | 1)</div><div class='add'>+#define PINMUX_GPIO164__FUNC_SCP_SPI1_B_CK (MTK_PIN_NO(164) | 2)</div><div class='add'>+#define PINMUX_GPIO164__FUNC_TP_URXD1_AO (MTK_PIN_NO(164) | 3)</div><div class='add'>+#define PINMUX_GPIO164__FUNC_UCTS0 (MTK_PIN_NO(164) | 5)</div><div class='add'>+#define PINMUX_GPIO164__FUNC_DBG_MON_B9 (MTK_PIN_NO(164) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0)</div><div class='add'>+#define PINMUX_GPIO165__FUNC_ANT_SEL3 (MTK_PIN_NO(165) | 1)</div><div class='add'>+#define PINMUX_GPIO165__FUNC_SCP_SPI1_B_CS (MTK_PIN_NO(165) | 2)</div><div class='add'>+#define PINMUX_GPIO165__FUNC_TP_UTXD1_AO (MTK_PIN_NO(165) | 3)</div><div class='add'>+#define PINMUX_GPIO165__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(165) | 4)</div><div class='add'>+#define PINMUX_GPIO165__FUNC_URTS0 (MTK_PIN_NO(165) | 5)</div><div class='add'>+#define PINMUX_GPIO165__FUNC_DBG_MON_B10 (MTK_PIN_NO(165) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0)</div><div class='add'>+#define PINMUX_GPIO166__FUNC_ANT_SEL4 (MTK_PIN_NO(166) | 1)</div><div class='add'>+#define PINMUX_GPIO166__FUNC_SCP_SPI1_B_MI (MTK_PIN_NO(166) | 2)</div><div class='add'>+#define PINMUX_GPIO166__FUNC_TP_URXD2_AO (MTK_PIN_NO(166) | 3)</div><div class='add'>+#define PINMUX_GPIO166__FUNC_SRCLKENAI1 (MTK_PIN_NO(166) | 4)</div><div class='add'>+#define PINMUX_GPIO166__FUNC_UCTS1 (MTK_PIN_NO(166) | 5)</div><div class='add'>+#define PINMUX_GPIO166__FUNC_DBG_MON_B11 (MTK_PIN_NO(166) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0)</div><div class='add'>+#define PINMUX_GPIO167__FUNC_ANT_SEL5 (MTK_PIN_NO(167) | 1)</div><div class='add'>+#define PINMUX_GPIO167__FUNC_SCP_SPI1_B_MO (MTK_PIN_NO(167) | 2)</div><div class='add'>+#define PINMUX_GPIO167__FUNC_TP_UTXD2_AO (MTK_PIN_NO(167) | 3)</div><div class='add'>+#define PINMUX_GPIO167__FUNC_SRCLKENAI0 (MTK_PIN_NO(167) | 4)</div><div class='add'>+#define PINMUX_GPIO167__FUNC_URTS1 (MTK_PIN_NO(167) | 5)</div><div class='add'>+#define PINMUX_GPIO167__FUNC_DBG_MON_B12 (MTK_PIN_NO(167) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0)</div><div class='add'>+#define PINMUX_GPIO168__FUNC_ANT_SEL6 (MTK_PIN_NO(168) | 1)</div><div class='add'>+#define PINMUX_GPIO168__FUNC_SPI0_B_CLK (MTK_PIN_NO(168) | 2)</div><div class='add'>+#define PINMUX_GPIO168__FUNC_TP_UCTS1_AO (MTK_PIN_NO(168) | 3)</div><div class='add'>+#define PINMUX_GPIO168__FUNC_KPCOL2 (MTK_PIN_NO(168) | 4)</div><div class='add'>+#define PINMUX_GPIO168__FUNC_MD_UCTS0 (MTK_PIN_NO(168) | 5)</div><div class='add'>+#define PINMUX_GPIO168__FUNC_SCL12 (MTK_PIN_NO(168) | 6)</div><div class='add'>+#define PINMUX_GPIO168__FUNC_DBG_MON_B13 (MTK_PIN_NO(168) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0)</div><div class='add'>+#define PINMUX_GPIO169__FUNC_ANT_SEL7 (MTK_PIN_NO(169) | 1)</div><div class='add'>+#define PINMUX_GPIO169__FUNC_SPI0_B_CSB (MTK_PIN_NO(169) | 2)</div><div class='add'>+#define PINMUX_GPIO169__FUNC_TP_URTS1_AO (MTK_PIN_NO(169) | 3)</div><div class='add'>+#define PINMUX_GPIO169__FUNC_KPROW2 (MTK_PIN_NO(169) | 4)</div><div class='add'>+#define PINMUX_GPIO169__FUNC_MD_URTS0 (MTK_PIN_NO(169) | 5)</div><div class='add'>+#define PINMUX_GPIO169__FUNC_SDA12 (MTK_PIN_NO(169) | 6)</div><div class='add'>+#define PINMUX_GPIO169__FUNC_DBG_MON_B14 (MTK_PIN_NO(169) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0)</div><div class='add'>+#define PINMUX_GPIO170__FUNC_ANT_SEL8 (MTK_PIN_NO(170) | 1)</div><div class='add'>+#define PINMUX_GPIO170__FUNC_SPI0_B_MI (MTK_PIN_NO(170) | 2)</div><div class='add'>+#define PINMUX_GPIO170__FUNC_TP_UCTS2_AO (MTK_PIN_NO(170) | 3)</div><div class='add'>+#define PINMUX_GPIO170__FUNC_SRCLKENAI1 (MTK_PIN_NO(170) | 4)</div><div class='add'>+#define PINMUX_GPIO170__FUNC_MD_UCTS1 (MTK_PIN_NO(170) | 5)</div><div class='add'>+#define PINMUX_GPIO170__FUNC_SCL13 (MTK_PIN_NO(170) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0)</div><div class='add'>+#define PINMUX_GPIO171__FUNC_ANT_SEL9 (MTK_PIN_NO(171) | 1)</div><div class='add'>+#define PINMUX_GPIO171__FUNC_SPI0_B_MO (MTK_PIN_NO(171) | 2)</div><div class='add'>+#define PINMUX_GPIO171__FUNC_TP_URTS2_AO (MTK_PIN_NO(171) | 3)</div><div class='add'>+#define PINMUX_GPIO171__FUNC_SRCLKENAI0 (MTK_PIN_NO(171) | 4)</div><div class='add'>+#define PINMUX_GPIO171__FUNC_MD_URTS1 (MTK_PIN_NO(171) | 5)</div><div class='add'>+#define PINMUX_GPIO171__FUNC_SDA13 (MTK_PIN_NO(171) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0)</div><div class='add'>+#define PINMUX_GPIO172__FUNC_CONN_TOP_CLK (MTK_PIN_NO(172) | 1)</div><div class='add'>+#define PINMUX_GPIO172__FUNC_AUXIF_CLK0 (MTK_PIN_NO(172) | 2)</div><div class='add'>+#define PINMUX_GPIO172__FUNC_DBG_MON_B18 (MTK_PIN_NO(172) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0)</div><div class='add'>+#define PINMUX_GPIO173__FUNC_CONN_TOP_DATA (MTK_PIN_NO(173) | 1)</div><div class='add'>+#define PINMUX_GPIO173__FUNC_AUXIF_ST0 (MTK_PIN_NO(173) | 2)</div><div class='add'>+#define PINMUX_GPIO173__FUNC_DBG_MON_B19 (MTK_PIN_NO(173) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0)</div><div class='add'>+#define PINMUX_GPIO174__FUNC_CONN_HRST_B (MTK_PIN_NO(174) | 1)</div><div class='add'>+#define PINMUX_GPIO174__FUNC_DBG_MON_B17 (MTK_PIN_NO(174) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0)</div><div class='add'>+#define PINMUX_GPIO175__FUNC_CONN_WB_PTA (MTK_PIN_NO(175) | 1)</div><div class='add'>+#define PINMUX_GPIO175__FUNC_DBG_MON_B20 (MTK_PIN_NO(175) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0)</div><div class='add'>+#define PINMUX_GPIO176__FUNC_CONN_BT_CLK (MTK_PIN_NO(176) | 1)</div><div class='add'>+#define PINMUX_GPIO176__FUNC_AUXIF_CLK1 (MTK_PIN_NO(176) | 2)</div><div class='add'>+#define PINMUX_GPIO176__FUNC_DBG_MON_B15 (MTK_PIN_NO(176) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0)</div><div class='add'>+#define PINMUX_GPIO177__FUNC_CONN_BT_DATA (MTK_PIN_NO(177) | 1)</div><div class='add'>+#define PINMUX_GPIO177__FUNC_AUXIF_ST1 (MTK_PIN_NO(177) | 2)</div><div class='add'>+#define PINMUX_GPIO177__FUNC_DBG_MON_B16 (MTK_PIN_NO(177) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0)</div><div class='add'>+#define PINMUX_GPIO178__FUNC_CONN_WF_CTRL0 (MTK_PIN_NO(178) | 1)</div><div class='add'>+#define PINMUX_GPIO178__FUNC_DBG_MON_B21 (MTK_PIN_NO(178) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0)</div><div class='add'>+#define PINMUX_GPIO179__FUNC_CONN_WF_CTRL1 (MTK_PIN_NO(179) | 1)</div><div class='add'>+#define PINMUX_GPIO179__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(179) | 2)</div><div class='add'>+#define PINMUX_GPIO179__FUNC_DBG_MON_B22 (MTK_PIN_NO(179) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO180__FUNC_GPIO180 (MTK_PIN_NO(180) | 0)</div><div class='add'>+#define PINMUX_GPIO180__FUNC_CONN_WF_CTRL2 (MTK_PIN_NO(180) | 1)</div><div class='add'>+#define PINMUX_GPIO180__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(180) | 2)</div><div class='add'>+#define PINMUX_GPIO180__FUNC_DBG_MON_B23 (MTK_PIN_NO(180) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO181__FUNC_GPIO181 (MTK_PIN_NO(181) | 0)</div><div class='add'>+#define PINMUX_GPIO181__FUNC_CONN_WF_CTRL3 (MTK_PIN_NO(181) | 1)</div><div class='add'>+#define PINMUX_GPIO181__FUNC_UFS_UNIPRO_SDA (MTK_PIN_NO(181) | 2)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO182__FUNC_GPIO182 (MTK_PIN_NO(182) | 0)</div><div class='add'>+#define PINMUX_GPIO182__FUNC_CONN_WF_CTRL4 (MTK_PIN_NO(182) | 1)</div><div class='add'>+#define PINMUX_GPIO182__FUNC_UFS_UNIPRO_SCL (MTK_PIN_NO(182) | 2)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO183__FUNC_GPIO183 (MTK_PIN_NO(183) | 0)</div><div class='add'>+#define PINMUX_GPIO183__FUNC_MSDC0_CMD (MTK_PIN_NO(183) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO184__FUNC_GPIO184 (MTK_PIN_NO(184) | 0)</div><div class='add'>+#define PINMUX_GPIO184__FUNC_MSDC0_DAT0 (MTK_PIN_NO(184) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO185__FUNC_GPIO185 (MTK_PIN_NO(185) | 0)</div><div class='add'>+#define PINMUX_GPIO185__FUNC_MSDC0_DAT2 (MTK_PIN_NO(185) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO186__FUNC_GPIO186 (MTK_PIN_NO(186) | 0)</div><div class='add'>+#define PINMUX_GPIO186__FUNC_MSDC0_DAT4 (MTK_PIN_NO(186) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO187__FUNC_GPIO187 (MTK_PIN_NO(187) | 0)</div><div class='add'>+#define PINMUX_GPIO187__FUNC_MSDC0_DAT6 (MTK_PIN_NO(187) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO188__FUNC_GPIO188 (MTK_PIN_NO(188) | 0)</div><div class='add'>+#define PINMUX_GPIO188__FUNC_MSDC0_DAT1 (MTK_PIN_NO(188) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO189__FUNC_GPIO189 (MTK_PIN_NO(189) | 0)</div><div class='add'>+#define PINMUX_GPIO189__FUNC_MSDC0_DAT5 (MTK_PIN_NO(189) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO190__FUNC_GPIO190 (MTK_PIN_NO(190) | 0)</div><div class='add'>+#define PINMUX_GPIO190__FUNC_MSDC0_DAT7 (MTK_PIN_NO(190) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO191__FUNC_GPIO191 (MTK_PIN_NO(191) | 0)</div><div class='add'>+#define PINMUX_GPIO191__FUNC_MSDC0_DSL (MTK_PIN_NO(191) | 1)</div><div class='add'>+#define PINMUX_GPIO191__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(191) | 2)</div><div class='add'>+#define PINMUX_GPIO191__FUNC_IDDIG (MTK_PIN_NO(191) | 3)</div><div class='add'>+#define PINMUX_GPIO191__FUNC_DMIC_CLK (MTK_PIN_NO(191) | 4)</div><div class='add'>+#define PINMUX_GPIO191__FUNC_DSI1_TE (MTK_PIN_NO(191) | 5)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO192__FUNC_GPIO192 (MTK_PIN_NO(192) | 0)</div><div class='add'>+#define PINMUX_GPIO192__FUNC_MSDC0_CLK (MTK_PIN_NO(192) | 1)</div><div class='add'>+#define PINMUX_GPIO192__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(192) | 2)</div><div class='add'>+#define PINMUX_GPIO192__FUNC_USB_DRVVBUS (MTK_PIN_NO(192) | 3)</div><div class='add'>+#define PINMUX_GPIO192__FUNC_DMIC_DAT (MTK_PIN_NO(192) | 4)</div><div class='add'>+#define PINMUX_GPIO192__FUNC_LCM1_RST (MTK_PIN_NO(192) | 5)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO193__FUNC_GPIO193 (MTK_PIN_NO(193) | 0)</div><div class='add'>+#define PINMUX_GPIO193__FUNC_MSDC0_DAT3 (MTK_PIN_NO(193) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO194__FUNC_GPIO194 (MTK_PIN_NO(194) | 0)</div><div class='add'>+#define PINMUX_GPIO194__FUNC_MSDC0_RSTB (MTK_PIN_NO(194) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO195__FUNC_GPIO195 (MTK_PIN_NO(195) | 0)</div><div class='add'>+#define PINMUX_GPIO195__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(195) | 1)</div><div class='add'>+#define PINMUX_GPIO195__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(195) | 2)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO196__FUNC_GPIO196 (MTK_PIN_NO(196) | 0)</div><div class='add'>+#define PINMUX_GPIO196__FUNC_AUD_DAT_MOSI2 (MTK_PIN_NO(196) | 1)</div><div class='add'>+#define PINMUX_GPIO196__FUNC_DBG_MON_B27 (MTK_PIN_NO(196) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO197__FUNC_GPIO197 (MTK_PIN_NO(197) | 0)</div><div class='add'>+#define PINMUX_GPIO197__FUNC_AUD_NLE_MOSI1 (MTK_PIN_NO(197) | 1)</div><div class='add'>+#define PINMUX_GPIO197__FUNC_AUD_CLK_MISO (MTK_PIN_NO(197) | 2)</div><div class='add'>+#define PINMUX_GPIO197__FUNC_I2S2_MCK (MTK_PIN_NO(197) | 3)</div><div class='add'>+#define PINMUX_GPIO197__FUNC_I2S6_MCK (MTK_PIN_NO(197) | 4)</div><div class='add'>+#define PINMUX_GPIO197__FUNC_I2S8_MCK (MTK_PIN_NO(197) | 5)</div><div class='add'>+#define PINMUX_GPIO197__FUNC_UFS_UNIPRO_SDA (MTK_PIN_NO(197) | 6)</div><div class='add'>+#define PINMUX_GPIO197__FUNC_DBG_MON_B28 (MTK_PIN_NO(197) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO198__FUNC_GPIO198 (MTK_PIN_NO(198) | 0)</div><div class='add'>+#define PINMUX_GPIO198__FUNC_AUD_NLE_MOSI0 (MTK_PIN_NO(198) | 1)</div><div class='add'>+#define PINMUX_GPIO198__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(198) | 2)</div><div class='add'>+#define PINMUX_GPIO198__FUNC_I2S2_BCK (MTK_PIN_NO(198) | 3)</div><div class='add'>+#define PINMUX_GPIO198__FUNC_I2S6_BCK (MTK_PIN_NO(198) | 4)</div><div class='add'>+#define PINMUX_GPIO198__FUNC_I2S8_BCK (MTK_PIN_NO(198) | 5)</div><div class='add'>+#define PINMUX_GPIO198__FUNC_DBG_MON_B29 (MTK_PIN_NO(198) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO199__FUNC_GPIO199 (MTK_PIN_NO(199) | 0)</div><div class='add'>+#define PINMUX_GPIO199__FUNC_AUD_DAT_MISO2 (MTK_PIN_NO(199) | 1)</div><div class='add'>+#define PINMUX_GPIO199__FUNC_I2S2_DI2 (MTK_PIN_NO(199) | 3)</div><div class='add'>+#define PINMUX_GPIO199__FUNC_DBG_MON_B32 (MTK_PIN_NO(199) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO200__FUNC_GPIO200 (MTK_PIN_NO(200) | 0)</div><div class='add'>+#define PINMUX_GPIO200__FUNC_SCL6 (MTK_PIN_NO(200) | 1)</div><div class='add'>+#define PINMUX_GPIO200__FUNC_SCP_SCL0 (MTK_PIN_NO(200) | 2)</div><div class='add'>+#define PINMUX_GPIO200__FUNC_SCP_SCL1 (MTK_PIN_NO(200) | 3)</div><div class='add'>+#define PINMUX_GPIO200__FUNC_SCL_6306 (MTK_PIN_NO(200) | 4)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO201__FUNC_GPIO201 (MTK_PIN_NO(201) | 0)</div><div class='add'>+#define PINMUX_GPIO201__FUNC_SDA6 (MTK_PIN_NO(201) | 1)</div><div class='add'>+#define PINMUX_GPIO201__FUNC_SCP_SDA0 (MTK_PIN_NO(201) | 2)</div><div class='add'>+#define PINMUX_GPIO201__FUNC_SCP_SDA1 (MTK_PIN_NO(201) | 3)</div><div class='add'>+#define PINMUX_GPIO201__FUNC_SDA_6306 (MTK_PIN_NO(201) | 4)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO202__FUNC_GPIO202 (MTK_PIN_NO(202) | 0)</div><div class='add'>+#define PINMUX_GPIO202__FUNC_SCL5 (MTK_PIN_NO(202) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO203__FUNC_GPIO203 (MTK_PIN_NO(203) | 0)</div><div class='add'>+#define PINMUX_GPIO203__FUNC_SDA5 (MTK_PIN_NO(203) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO204__FUNC_GPIO204 (MTK_PIN_NO(204) | 0)</div><div class='add'>+#define PINMUX_GPIO204__FUNC_SCL0 (MTK_PIN_NO(204) | 1)</div><div class='add'>+#define PINMUX_GPIO204__FUNC_SPI4_C_CLK (MTK_PIN_NO(204) | 2)</div><div class='add'>+#define PINMUX_GPIO204__FUNC_SPI7_B_CLK (MTK_PIN_NO(204) | 3)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO205__FUNC_GPIO205 (MTK_PIN_NO(205) | 0)</div><div class='add'>+#define PINMUX_GPIO205__FUNC_SDA0 (MTK_PIN_NO(205) | 1)</div><div class='add'>+#define PINMUX_GPIO205__FUNC_SPI4_C_CSB (MTK_PIN_NO(205) | 2)</div><div class='add'>+#define PINMUX_GPIO205__FUNC_SPI7_B_CSB (MTK_PIN_NO(205) | 3)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO206__FUNC_GPIO206 (MTK_PIN_NO(206) | 0)</div><div class='add'>+#define PINMUX_GPIO206__FUNC_SRCLKENA0 (MTK_PIN_NO(206) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO207__FUNC_GPIO207 (MTK_PIN_NO(207) | 0)</div><div class='add'>+#define PINMUX_GPIO207__FUNC_SRCLKENA1 (MTK_PIN_NO(207) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO208__FUNC_GPIO208 (MTK_PIN_NO(208) | 0)</div><div class='add'>+#define PINMUX_GPIO208__FUNC_WATCHDOG (MTK_PIN_NO(208) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO209__FUNC_GPIO209 (MTK_PIN_NO(209) | 0)</div><div class='add'>+#define PINMUX_GPIO209__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(209) | 1)</div><div class='add'>+#define PINMUX_GPIO209__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(209) | 2)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO210__FUNC_GPIO210 (MTK_PIN_NO(210) | 0)</div><div class='add'>+#define PINMUX_GPIO210__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(210) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO211__FUNC_GPIO211 (MTK_PIN_NO(211) | 0)</div><div class='add'>+#define PINMUX_GPIO211__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(211) | 1)</div><div class='add'>+#define PINMUX_GPIO211__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(211) | 2)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO212__FUNC_GPIO212 (MTK_PIN_NO(212) | 0)</div><div class='add'>+#define PINMUX_GPIO212__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(212) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO213__FUNC_GPIO213 (MTK_PIN_NO(213) | 0)</div><div class='add'>+#define PINMUX_GPIO213__FUNC_RTC32K_CK (MTK_PIN_NO(213) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO214__FUNC_GPIO214 (MTK_PIN_NO(214) | 0)</div><div class='add'>+#define PINMUX_GPIO214__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(214) | 1)</div><div class='add'>+#define PINMUX_GPIO214__FUNC_I2S1_MCK (MTK_PIN_NO(214) | 3)</div><div class='add'>+#define PINMUX_GPIO214__FUNC_I2S7_MCK (MTK_PIN_NO(214) | 4)</div><div class='add'>+#define PINMUX_GPIO214__FUNC_I2S9_MCK (MTK_PIN_NO(214) | 5)</div><div class='add'>+#define PINMUX_GPIO214__FUNC_UFS_UNIPRO_SCL (MTK_PIN_NO(214) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO215__FUNC_GPIO215 (MTK_PIN_NO(215) | 0)</div><div class='add'>+#define PINMUX_GPIO215__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(215) | 1)</div><div class='add'>+#define PINMUX_GPIO215__FUNC_I2S1_BCK (MTK_PIN_NO(215) | 3)</div><div class='add'>+#define PINMUX_GPIO215__FUNC_I2S7_BCK (MTK_PIN_NO(215) | 4)</div><div class='add'>+#define PINMUX_GPIO215__FUNC_I2S9_BCK (MTK_PIN_NO(215) | 5)</div><div class='add'>+#define PINMUX_GPIO215__FUNC_DBG_MON_B24 (MTK_PIN_NO(215) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO216__FUNC_GPIO216 (MTK_PIN_NO(216) | 0)</div><div class='add'>+#define PINMUX_GPIO216__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(216) | 1)</div><div class='add'>+#define PINMUX_GPIO216__FUNC_I2S1_LRCK (MTK_PIN_NO(216) | 3)</div><div class='add'>+#define PINMUX_GPIO216__FUNC_I2S7_LRCK (MTK_PIN_NO(216) | 4)</div><div class='add'>+#define PINMUX_GPIO216__FUNC_I2S9_LRCK (MTK_PIN_NO(216) | 5)</div><div class='add'>+#define PINMUX_GPIO216__FUNC_DBG_MON_B25 (MTK_PIN_NO(216) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO217__FUNC_GPIO217 (MTK_PIN_NO(217) | 0)</div><div class='add'>+#define PINMUX_GPIO217__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(217) | 1)</div><div class='add'>+#define PINMUX_GPIO217__FUNC_I2S1_DO (MTK_PIN_NO(217) | 3)</div><div class='add'>+#define PINMUX_GPIO217__FUNC_I2S7_DO (MTK_PIN_NO(217) | 4)</div><div class='add'>+#define PINMUX_GPIO217__FUNC_I2S9_DO (MTK_PIN_NO(217) | 5)</div><div class='add'>+#define PINMUX_GPIO217__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(217) | 6)</div><div class='add'>+#define PINMUX_GPIO217__FUNC_DBG_MON_B26 (MTK_PIN_NO(217) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO218__FUNC_GPIO218 (MTK_PIN_NO(218) | 0)</div><div class='add'>+#define PINMUX_GPIO218__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(218) | 1)</div><div class='add'>+#define PINMUX_GPIO218__FUNC_VOW_DAT_MISO (MTK_PIN_NO(218) | 2)</div><div class='add'>+#define PINMUX_GPIO218__FUNC_I2S2_LRCK (MTK_PIN_NO(218) | 3)</div><div class='add'>+#define PINMUX_GPIO218__FUNC_I2S6_LRCK (MTK_PIN_NO(218) | 4)</div><div class='add'>+#define PINMUX_GPIO218__FUNC_I2S8_LRCK (MTK_PIN_NO(218) | 5)</div><div class='add'>+#define PINMUX_GPIO218__FUNC_DBG_MON_B30 (MTK_PIN_NO(218) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO219__FUNC_GPIO219 (MTK_PIN_NO(219) | 0)</div><div class='add'>+#define PINMUX_GPIO219__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(219) | 1)</div><div class='add'>+#define PINMUX_GPIO219__FUNC_VOW_CLK_MISO (MTK_PIN_NO(219) | 2)</div><div class='add'>+#define PINMUX_GPIO219__FUNC_I2S2_DI (MTK_PIN_NO(219) | 3)</div><div class='add'>+#define PINMUX_GPIO219__FUNC_I2S6_DI (MTK_PIN_NO(219) | 4)</div><div class='add'>+#define PINMUX_GPIO219__FUNC_I2S8_DI (MTK_PIN_NO(219) | 5)</div><div class='add'>+#define PINMUX_GPIO219__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(219) | 6)</div><div class='add'>+#define PINMUX_GPIO219__FUNC_DBG_MON_B31 (MTK_PIN_NO(219) | 7)</div><div class='add'>+</div><div class='add'>+#endif /* __MT6893-PINFUNC_H */</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts<br/>index 83e10591e0e5..9f100b18a676 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts</a></div><div class='hunk'>@@ -8,12 +8,14 @@</div><div class='ctx'> /dts-v1/;</div><div class='ctx'> #include &lt;dt-bindings/input/input.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "mt7622.dtsi"</div><div class='ctx'> #include "mt6380.dtsi"</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	model = "Bananapi BPI-R64";</div><div class='add'>+	chassis-type = "embedded";</div><div class='ctx'> 	compatible = "bananapi,bpi-r64", "mediatek,mt7622";</div><div class='ctx'> </div><div class='ctx'> 	aliases {</div><div class='hunk'>@@ -40,37 +42,40 @@</div><div class='ctx'> 	gpio-keys {</div><div class='ctx'> 		compatible = "gpio-keys";</div><div class='ctx'> </div><div class='del'>-		factory {</div><div class='add'>+		factory-key {</div><div class='ctx'> 			label = "factory";</div><div class='ctx'> 			linux,code = &lt;BTN_0&gt;;</div><div class='ctx'> 			gpios = &lt;&amp;pio 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		wps {</div><div class='add'>+		wps-key {</div><div class='ctx'> 			label = "wps";</div><div class='ctx'> 			linux,code = &lt;KEY_WPS_BUTTON&gt;;</div><div class='del'>-			gpios = &lt;&amp;pio 102 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			gpios = &lt;&amp;pio 102 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	leds {</div><div class='ctx'> 		compatible = "gpio-leds";</div><div class='ctx'> </div><div class='del'>-		green {</div><div class='add'>+		led-0 {</div><div class='ctx'> 			label = "bpi-r64:pio:green";</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='ctx'> 			gpios = &lt;&amp;pio 89 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 			default-state = "off";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		red {</div><div class='add'>+		led-1 {</div><div class='ctx'> 			label = "bpi-r64:pio:red";</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='ctx'> 			gpios = &lt;&amp;pio 88 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 			default-state = "off";</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	memory {</div><div class='add'>+	memory@40000000 {</div><div class='ctx'> 		reg = &lt;0 0x40000000 0 0x40000000&gt;;</div><div class='add'>+		device_type = "memory";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	reg_1p8v: regulator-1p8v {</div><div class='hunk'>@@ -143,6 +148,71 @@</div><div class='ctx'> 	mdio: mdio-bus {</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		switch@1f {</div><div class='add'>+			compatible = "mediatek,mt7531";</div><div class='add'>+			reg = &lt;0x1f&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupts-extended = &lt;&amp;pio 53 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;pio 54 0&gt;;</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					label = "wan";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					label = "lan0";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@2 {</div><div class='add'>+					reg = &lt;2&gt;;</div><div class='add'>+					label = "lan1";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@3 {</div><div class='add'>+					reg = &lt;3&gt;;</div><div class='add'>+					label = "lan2";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@4 {</div><div class='add'>+					reg = &lt;4&gt;;</div><div class='add'>+					label = "lan3";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@5 {</div><div class='add'>+					reg = &lt;5&gt;;</div><div class='add'>+					ethernet = &lt;&amp;gmac1&gt;;</div><div class='add'>+					phy-mode = "rgmii";</div><div class='add'>+</div><div class='add'>+					fixed-link {</div><div class='add'>+						speed = &lt;1000&gt;;</div><div class='add'>+						full-duplex;</div><div class='add'>+						pause;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@6 {</div><div class='add'>+					reg = &lt;6&gt;;</div><div class='add'>+					label = "cpu";</div><div class='add'>+					ethernet = &lt;&amp;gmac0&gt;;</div><div class='add'>+					phy-mode = "2500base-x";</div><div class='add'>+</div><div class='add'>+					fixed-link {</div><div class='add'>+						speed = &lt;2500&gt;;</div><div class='add'>+						full-duplex;</div><div class='add'>+						pause;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -182,7 +252,6 @@</div><div class='ctx'> 	bus-width = &lt;4&gt;;</div><div class='ctx'> 	max-frequency = &lt;50000000&gt;;</div><div class='ctx'> 	cap-sd-highspeed;</div><div class='del'>-	r_smpl = &lt;1&gt;;</div><div class='ctx'> 	cd-gpios = &lt;&amp;pio 81 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 	vmmc-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='ctx'> 	vqmmc-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='hunk'>@@ -196,36 +265,62 @@</div><div class='ctx'> 	status = "disabled";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;nor_flash {</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-	pinctrl-0 = &lt;&amp;spi_nor_pins&gt;;</div><div class='del'>-	status = "disabled";</div><div class='add'>+&amp;bch {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='ctx'> </div><div class='add'>+&amp;snfi {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;serial_nand_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='ctx'> 	flash@0 {</div><div class='del'>-		compatible = "jedec,spi-nor";</div><div class='add'>+		compatible = "spi-nand";</div><div class='ctx'> 		reg = &lt;0&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;4&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+		nand-ecc-engine = &lt;&amp;snfi&gt;;</div><div class='add'>+		partitions {</div><div class='add'>+			compatible = "fixed-partitions";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			partition@0 {</div><div class='add'>+				label = "bl2";</div><div class='add'>+				reg = &lt;0x0 0x80000&gt;;</div><div class='add'>+				read-only;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			partition@80000 {</div><div class='add'>+				label = "fip";</div><div class='add'>+				reg = &lt;0x80000 0x200000&gt;;</div><div class='add'>+				read-only;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ubi: partition@280000 {</div><div class='add'>+				label = "ubi";</div><div class='add'>+				reg = &lt;0x280000 0x7d80000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;pcie {</div><div class='add'>+&amp;pcie0 {</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='del'>-	pinctrl-0 = &lt;&amp;pcie0_pins&gt;, &lt;&amp;pcie1_pins&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pcie0_pins&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='add'>+};</div><div class='ctx'> </div><div class='del'>-	pcie@0,0 {</div><div class='del'>-		status = "okay";</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	pcie@1,0 {</div><div class='del'>-		status = "okay";</div><div class='del'>-	};</div><div class='add'>+&amp;pcie1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pcie1_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;pio {</div><div class='ctx'> 	/* Attention: GPIO 90 is used to switch between PCIe@1,0 and</div><div class='ctx'> 	 * SATA functions. i.e. output-high: PCIe, output-low: SATA</div><div class='ctx'> 	 */</div><div class='del'>-	asm_sel {</div><div class='add'>+	asm-sel-hog {</div><div class='ctx'> 		gpio-hog;</div><div class='ctx'> 		gpios = &lt;90 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 		output-high;</div><div class='hunk'>@@ -234,8 +329,8 @@</div><div class='ctx'> 	/* eMMC is shared pin with parallel NAND */</div><div class='ctx'> 	emmc_pins_default: emmc-pins-default {</div><div class='ctx'> 		mux {</div><div class='del'>-			function = "emmc", "emmc_rst";</div><div class='del'>-			groups = "emmc";</div><div class='add'>+			function = "emmc";</div><div class='add'>+			groups = "emmc", "emmc_rst";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		/* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",</div><div class='hunk'>@@ -288,23 +383,23 @@</div><div class='ctx'> 	i2c1_pins: i2c1-pins {</div><div class='ctx'> 		mux {</div><div class='ctx'> 			function = "i2c";</div><div class='del'>-			groups =  "i2c1_0";</div><div class='add'>+			groups = "i2c1_0";</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	i2c2_pins: i2c2-pins {</div><div class='ctx'> 		mux {</div><div class='ctx'> 			function = "i2c";</div><div class='del'>-			groups =  "i2c2_0";</div><div class='add'>+			groups = "i2c2_0";</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	i2s1_pins: i2s1-pins {</div><div class='ctx'> 		mux {</div><div class='ctx'> 			function = "i2s";</div><div class='del'>-			groups =  "i2s_out_mclk_bclk_ws",</div><div class='del'>-				  "i2s1_in_data",</div><div class='del'>-				  "i2s1_out_data";</div><div class='add'>+			groups = "i2s_out_mclk_bclk_ws",</div><div class='add'>+				 "i2s1_in_data",</div><div class='add'>+				 "i2s1_out_data";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		conf {</div><div class='hunk'>@@ -318,14 +413,14 @@</div><div class='ctx'> 	irrx_pins: irrx-pins {</div><div class='ctx'> 		mux {</div><div class='ctx'> 			function = "ir";</div><div class='del'>-			groups =  "ir_1_rx";</div><div class='add'>+			groups = "ir_1_rx";</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	irtx_pins: irtx-pins {</div><div class='ctx'> 		mux {</div><div class='ctx'> 			function = "ir";</div><div class='del'>-			groups =  "ir_1_tx";</div><div class='add'>+			groups = "ir_1_tx";</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -362,10 +457,15 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pwm7_pins: pwm1-2-pins {</div><div class='add'>+	pwm_pins: pwm-pins {</div><div class='ctx'> 		mux {</div><div class='ctx'> 			function = "pwm";</div><div class='del'>-			groups = "pwm_ch7_2";</div><div class='add'>+			groups = "pwm_ch1_0", /* mt7622_pwm_ch1_0_pins[] = { 51, }; */</div><div class='add'>+				 "pwm_ch2_0", /* mt7622_pwm_ch2_0_pins[] = { 52, }; */</div><div class='add'>+				 "pwm_ch3_2", /* mt7622_pwm_ch3_2_pins[] = { 97, }; */</div><div class='add'>+				 "pwm_ch4_1", /* mt7622_pwm_ch4_1_pins[] = { 67, }; */</div><div class='add'>+				 "pwm_ch5_0", /* mt7622_pwm_ch5_0_pins[] = { 68, }; */</div><div class='add'>+				 "pwm_ch6_0"; /* mt7622_pwm_ch6_0_pins[] = { 69, }; */</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -485,7 +585,7 @@</div><div class='ctx'> </div><div class='ctx'> &amp;pwm {</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='del'>-	pinctrl-0 = &lt;&amp;pwm7_pins&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm_pins&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -497,11 +597,11 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;sata {</div><div class='del'>-	status = "disable";</div><div class='add'>+	status = "disabled";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;sata_phy {</div><div class='del'>-	status = "disable";</div><div class='add'>+	status = "disabled";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;spi0 {</div><div class='hunk'>@@ -513,7 +613,6 @@</div><div class='ctx'> &amp;spi1 {</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;spic1_pins&gt;;</div><div class='del'>-	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;ssusb {</div><div class='hunk'>@@ -535,7 +634,6 @@</div><div class='ctx'> &amp;uart2 {</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;uart2_pins&gt;;</div><div class='del'>-	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;watchdog {</div><div class='hunk'>@@ -543,3 +641,7 @@</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;watchdog_pins&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='add'>+</div><div class='add'>+&amp;wmac {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts<br/>index 3f783348c66a..8c3e2e2578bc 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts</a></div><div class='hunk'>@@ -15,6 +15,7 @@</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	model = "MediaTek MT7622 RFB1 board";</div><div class='add'>+	chassis-type = "embedded";</div><div class='ctx'> 	compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";</div><div class='ctx'> </div><div class='ctx'> 	aliases {</div><div class='hunk'>@@ -40,23 +41,23 @@</div><div class='ctx'> </div><div class='ctx'> 	gpio-keys {</div><div class='ctx'> 		compatible = "gpio-keys";</div><div class='del'>-		poll-interval = &lt;100&gt;;</div><div class='ctx'> </div><div class='del'>-		factory {</div><div class='add'>+		key-factory {</div><div class='ctx'> 			label = "factory";</div><div class='ctx'> 			linux,code = &lt;BTN_0&gt;;</div><div class='ctx'> 			gpios = &lt;&amp;pio 0 0&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		wps {</div><div class='add'>+		key-wps {</div><div class='ctx'> 			label = "wps";</div><div class='ctx'> 			linux,code = &lt;KEY_WPS_BUTTON&gt;;</div><div class='ctx'> 			gpios = &lt;&amp;pio 102 0&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	memory {</div><div class='add'>+	memory@40000000 {</div><div class='ctx'> 		reg = &lt;0 0x40000000 0 0x20000000&gt;;</div><div class='add'>+		device_type = "memory";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	reg_1p8v: regulator-1p8v {</div><div class='hunk'>@@ -105,20 +106,95 @@</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;eth_pins&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> </div><div class='add'>+	gmac0: mac@0 {</div><div class='add'>+		compatible = "mediatek,eth-mac";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		phy-mode = "2500base-x";</div><div class='add'>+</div><div class='add'>+		fixed-link {</div><div class='add'>+			speed = &lt;2500&gt;;</div><div class='add'>+			full-duplex;</div><div class='add'>+			pause;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	gmac1: mac@1 {</div><div class='ctx'> 		compatible = "mediatek,eth-mac";</div><div class='ctx'> 		reg = &lt;1&gt;;</div><div class='del'>-		phy-handle = &lt;&amp;phy5&gt;;</div><div class='add'>+		phy-mode = "rgmii";</div><div class='add'>+</div><div class='add'>+		fixed-link {</div><div class='add'>+			speed = &lt;1000&gt;;</div><div class='add'>+			full-duplex;</div><div class='add'>+			pause;</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	mdio-bus {</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;0&gt;;</div><div class='ctx'> </div><div class='del'>-		phy5: ethernet-phy@5 {</div><div class='del'>-			reg = &lt;5&gt;;</div><div class='del'>-			phy-mode = "sgmii";</div><div class='add'>+		switch@0 {</div><div class='add'>+			compatible = "mediatek,mt7531";</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;pio 54 0&gt;;</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					label = "lan0";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					label = "lan1";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@2 {</div><div class='add'>+					reg = &lt;2&gt;;</div><div class='add'>+					label = "lan2";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@3 {</div><div class='add'>+					reg = &lt;3&gt;;</div><div class='add'>+					label = "lan3";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@4 {</div><div class='add'>+					reg = &lt;4&gt;;</div><div class='add'>+					label = "wan";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@5 {</div><div class='add'>+					reg = &lt;5&gt;;</div><div class='add'>+					ethernet = &lt;&amp;gmac1&gt;;</div><div class='add'>+					phy-mode = "rgmii";</div><div class='add'>+</div><div class='add'>+					fixed-link {</div><div class='add'>+						speed = &lt;1000&gt;;</div><div class='add'>+						full-duplex;</div><div class='add'>+						pause;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@6 {</div><div class='add'>+					reg = &lt;6&gt;;</div><div class='add'>+					label = "cpu";</div><div class='add'>+					ethernet = &lt;&amp;gmac0&gt;;</div><div class='add'>+					phy-mode = "2500base-x";</div><div class='add'>+</div><div class='add'>+					fixed-link {</div><div class='add'>+						speed = &lt;2500&gt;;</div><div class='add'>+						full-duplex;</div><div class='add'>+						pause;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='add'>+</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -158,7 +234,6 @@</div><div class='ctx'> 	bus-width = &lt;4&gt;;</div><div class='ctx'> 	max-frequency = &lt;50000000&gt;;</div><div class='ctx'> 	cap-sd-highspeed;</div><div class='del'>-	r_smpl = &lt;1&gt;;</div><div class='ctx'> 	cd-gpios = &lt;&amp;pio 81 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 	vmmc-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='ctx'> 	vqmmc-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='hunk'>@@ -183,22 +258,18 @@</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;pcie {</div><div class='add'>+&amp;pcie0 {</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;pcie0_pins&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='del'>-</div><div class='del'>-	pcie@0,0 {</div><div class='del'>-		status = "okay";</div><div class='del'>-	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;pio {</div><div class='ctx'> 	/* eMMC is shared pin with parallel NAND */</div><div class='ctx'> 	emmc_pins_default: emmc-pins-default {</div><div class='ctx'> 		mux {</div><div class='del'>-			function = "emmc", "emmc_rst";</div><div class='del'>-			groups = "emmc";</div><div class='add'>+			function = "emmc";</div><div class='add'>+			groups = "emmc", "emmc_rst";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		/* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",</div><div class='hunk'>@@ -251,23 +322,23 @@</div><div class='ctx'> 	i2c1_pins: i2c1-pins {</div><div class='ctx'> 		mux {</div><div class='ctx'> 			function = "i2c";</div><div class='del'>-			groups =  "i2c1_0";</div><div class='add'>+			groups = "i2c1_0";</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	i2c2_pins: i2c2-pins {</div><div class='ctx'> 		mux {</div><div class='ctx'> 			function = "i2c";</div><div class='del'>-			groups =  "i2c2_0";</div><div class='add'>+			groups = "i2c2_0";</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	i2s1_pins: i2s1-pins {</div><div class='ctx'> 		mux {</div><div class='ctx'> 			function = "i2s";</div><div class='del'>-			groups =  "i2s_out_mclk_bclk_ws",</div><div class='del'>-				  "i2s1_in_data",</div><div class='del'>-				  "i2s1_out_data";</div><div class='add'>+			groups = "i2s_out_mclk_bclk_ws",</div><div class='add'>+				 "i2s1_in_data",</div><div class='add'>+				 "i2s1_out_data";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		conf {</div><div class='hunk'>@@ -281,14 +352,14 @@</div><div class='ctx'> 	irrx_pins: irrx-pins {</div><div class='ctx'> 		mux {</div><div class='ctx'> 			function = "ir";</div><div class='del'>-			groups =  "ir_1_rx";</div><div class='add'>+			groups = "ir_1_rx";</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	irtx_pins: irtx-pins {</div><div class='ctx'> 		mux {</div><div class='ctx'> 			function = "ir";</div><div class='del'>-			groups =  "ir_1_tx";</div><div class='add'>+			groups = "ir_1_tx";</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -444,6 +515,16 @@</div><div class='ctx'> 			groups = "watchdog";</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	wmac_pins: wmac-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "antsel";</div><div class='add'>+			groups = "antsel0", "antsel1", "antsel2", "antsel3",</div><div class='add'>+				 "antsel4", "antsel5", "antsel6", "antsel7",</div><div class='add'>+				 "antsel8", "antsel9", "antsel12", "antsel13",</div><div class='add'>+				 "antsel14", "antsel15", "antsel16", "antsel17";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;pwm {</div><div class='hunk'>@@ -506,3 +587,9 @@</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;watchdog_pins&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='add'>+</div><div class='add'>+&amp;wmac {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;wmac_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi<br/>index 339dc9f88f43..158bd9a305d7 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt7622.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt7622.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt7622.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt7622.dtsi</a></div><div class='hunk'>@@ -80,6 +80,7 @@</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			clock-frequency = &lt;1300000000&gt;;</div><div class='ctx'> 			cci-control-port = &lt;&amp;cci_control2&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;L2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu1: cpu@1 {</div><div class='hunk'>@@ -94,6 +95,13 @@</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			clock-frequency = &lt;1300000000&gt;;</div><div class='ctx'> 			cci-control-port = &lt;&amp;cci_control2&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;L2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		L2: l2-cache {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -111,8 +119,8 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	psci {</div><div class='del'>-		compatible  = "arm,psci-0.2";</div><div class='del'>-		method      = "smc";</div><div class='add'>+		compatible = "arm,psci-0.2";</div><div class='add'>+		method = "smc";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	pmu {</div><div class='hunk'>@@ -244,7 +252,7 @@</div><div class='ctx'> 		clock-names = "hif_sel";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	cir: cir@10009000 {</div><div class='add'>+	cir: ir-receiver@10009000 {</div><div class='ctx'> 		compatible = "mediatek,mt7622-cir";</div><div class='ctx'> 		reg = &lt;0 0x10009000 0 0x1000&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 175 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='hunk'>@@ -270,21 +278,23 @@</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;1&gt;;</div><div class='ctx'> </div><div class='add'>+		soc-uuid@140 {</div><div class='add'>+			reg = &lt;0x140 0x8&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		thermal_calibration: calib@198 {</div><div class='ctx'> 			reg = &lt;0x198 0xc&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	apmixedsys: apmixedsys@10209000 {</div><div class='del'>-		compatible = "mediatek,mt7622-apmixedsys",</div><div class='del'>-			     "syscon";</div><div class='add'>+	apmixedsys: clock-controller@10209000 {</div><div class='add'>+		compatible = "mediatek,mt7622-apmixedsys";</div><div class='ctx'> 		reg = &lt;0 0x10209000 0 0x1000&gt;;</div><div class='ctx'> 		#clock-cells = &lt;1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	topckgen: topckgen@10210000 {</div><div class='del'>-		compatible = "mediatek,mt7622-topckgen",</div><div class='del'>-			     "syscon";</div><div class='add'>+	topckgen: clock-controller@10210000 {</div><div class='add'>+		compatible = "mediatek,mt7622-topckgen";</div><div class='ctx'> 		reg = &lt;0 0x10210000 0 0x1000&gt;;</div><div class='ctx'> 		#clock-cells = &lt;1&gt;;</div><div class='ctx'> 	};</div><div class='hunk'>@@ -357,7 +367,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cci_control2: slave-if@5000 {</div><div class='del'>-			compatible = "arm,cci-400-ctrl-if";</div><div class='add'>+			compatible = "arm,cci-400-ctrl-if", "syscon";</div><div class='ctx'> 			interface-type = "ace";</div><div class='ctx'> 			reg = &lt;0x5000 0x1000&gt;;</div><div class='ctx'> 		};</div><div class='hunk'>@@ -428,6 +438,7 @@</div><div class='ctx'> 	pwm: pwm@11006000 {</div><div class='ctx'> 		compatible = "mediatek,mt7622-pwm";</div><div class='ctx'> 		reg = &lt;0 0x11006000 0 0x1000&gt;;</div><div class='add'>+		#pwm-cells = &lt;2&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 77 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 		clocks = &lt;&amp;topckgen CLK_TOP_PWM_SEL&gt;,</div><div class='ctx'> 			 &lt;&amp;pericfg CLK_PERI_PWM_PD&gt;,</div><div class='hunk'>@@ -506,7 +517,6 @@</div><div class='ctx'> 			 &lt;&amp;pericfg CLK_PERI_AUXADC_PD&gt;;</div><div class='ctx'> 		clock-names = "therm", "auxadc";</div><div class='ctx'> 		resets = &lt;&amp;pericfg MT7622_PERI_THERM_SW_RST&gt;;</div><div class='del'>-		reset-names = "therm";</div><div class='ctx'> 		mediatek,auxadc = &lt;&amp;auxadc&gt;;</div><div class='ctx'> 		mediatek,apmixedsys = &lt;&amp;apmixedsys&gt;;</div><div class='ctx'> 		nvmem-cells = &lt;&amp;thermal_calibration&gt;;</div><div class='hunk'>@@ -519,7 +529,6 @@</div><div class='ctx'> 		reg = &lt;0 0x1100c000 0 0x1000&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 90 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 		clocks = &lt;&amp;pericfg CLK_PERI_BTIF_PD&gt;;</div><div class='del'>-		clock-names = "main";</div><div class='ctx'> 		reg-shift = &lt;2&gt;;</div><div class='ctx'> 		reg-io-width = &lt;4&gt;;</div><div class='ctx'> 		status = "disabled";</div><div class='hunk'>@@ -532,7 +541,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	nandc: nfi@1100d000 {</div><div class='add'>+	nandc: nand-controller@1100d000 {</div><div class='ctx'> 		compatible = "mediatek,mt7622-nfc";</div><div class='ctx'> 		reg = &lt;0 0x1100D000 0 0x1000&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 96 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='hunk'>@@ -545,6 +554,18 @@</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	snfi: spi@1100d000 {</div><div class='add'>+		compatible = "mediatek,mt7622-snand";</div><div class='add'>+		reg = &lt;0 0x1100d000 0 0x1000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 96 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		clocks = &lt;&amp;pericfg CLK_PERI_NFI_PD&gt;, &lt;&amp;pericfg CLK_PERI_SNFI_PD&gt;;</div><div class='add'>+		clock-names = "nfi_clk", "pad_clk";</div><div class='add'>+		nand-ecc-engine = &lt;&amp;bch&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	bch: ecc@1100e000 {</div><div class='ctx'> 		compatible = "mediatek,mt7622-ecc";</div><div class='ctx'> 		reg = &lt;0 0x1100e000 0 0x1000&gt;;</div><div class='hunk'>@@ -597,9 +618,9 @@</div><div class='ctx'> </div><div class='ctx'> 		afe: audio-controller {</div><div class='ctx'> 			compatible = "mediatek,mt7622-audio";</div><div class='del'>-			interrupts =  &lt;GIC_SPI 144 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='del'>-				      &lt;GIC_SPI 145 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='del'>-			interrupt-names	= "afe", "asys";</div><div class='add'>+			interrupts = &lt;GIC_SPI 144 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+				     &lt;GIC_SPI 145 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			interrupt-names = "afe", "asys";</div><div class='ctx'> </div><div class='ctx'> 			clocks = &lt;&amp;infracfg CLK_INFRA_AUDIO_PD&gt;,</div><div class='ctx'> 				 &lt;&amp;topckgen CLK_TOP_AUD1_SEL&gt;,</div><div class='hunk'>@@ -686,6 +707,8 @@</div><div class='ctx'> 		clocks = &lt;&amp;pericfg CLK_PERI_MSDC30_0_PD&gt;,</div><div class='ctx'> 			 &lt;&amp;topckgen CLK_TOP_MSDC50_0_SEL&gt;;</div><div class='ctx'> 		clock-names = "source", "hclk";</div><div class='add'>+		resets = &lt;&amp;pericfg MT7622_PERI_MSDC0_SW_RST&gt;;</div><div class='add'>+		reset-names = "hrst";</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -696,12 +719,24 @@</div><div class='ctx'> 		clocks = &lt;&amp;pericfg CLK_PERI_MSDC30_1_PD&gt;,</div><div class='ctx'> 			 &lt;&amp;topckgen CLK_TOP_AXI_SEL&gt;;</div><div class='ctx'> 		clock-names = "source", "hclk";</div><div class='add'>+		resets = &lt;&amp;pericfg MT7622_PERI_MSDC1_SW_RST&gt;;</div><div class='add'>+		reset-names = "hrst";</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	ssusbsys: ssusbsys@1a000000 {</div><div class='del'>-		compatible = "mediatek,mt7622-ssusbsys",</div><div class='del'>-			     "syscon";</div><div class='add'>+	wmac: wmac@18000000 {</div><div class='add'>+		compatible = "mediatek,mt7622-wmac";</div><div class='add'>+		reg = &lt;0 0x18000000 0 0x100000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 211 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		mediatek,infracfg = &lt;&amp;infracfg&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+</div><div class='add'>+		power-domains = &lt;&amp;scpsys MT7622_POWER_DOMAIN_WB&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ssusbsys: clock-controller@1a000000 {</div><div class='add'>+		compatible = "mediatek,mt7622-ssusbsys";</div><div class='ctx'> 		reg = &lt;0 0x1a000000 0 0x1000&gt;;</div><div class='ctx'> 		#clock-cells = &lt;1&gt;;</div><div class='ctx'> 		#reset-cells = &lt;1&gt;;</div><div class='hunk'>@@ -727,8 +762,8 @@</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	u3phy: usb-phy@1a0c4000 {</div><div class='del'>-		compatible = "mediatek,mt7622-u3phy",</div><div class='add'>+	u3phy: t-phy@1a0c4000 {</div><div class='add'>+		compatible = "mediatek,mt7622-tphy",</div><div class='ctx'> 			     "mediatek,generic-tphy-v1";</div><div class='ctx'> 		reg = &lt;0 0x1a0c4000 0 0x700&gt;;</div><div class='ctx'> 		#address-cells = &lt;2&gt;;</div><div class='hunk'>@@ -758,83 +793,90 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pciesys: pciesys@1a100800 {</div><div class='del'>-		compatible = "mediatek,mt7622-pciesys",</div><div class='del'>-			     "syscon";</div><div class='add'>+	pciesys: clock-controller@1a100800 {</div><div class='add'>+		compatible = "mediatek,mt7622-pciesys";</div><div class='ctx'> 		reg = &lt;0 0x1a100800 0 0x1000&gt;;</div><div class='ctx'> 		#clock-cells = &lt;1&gt;;</div><div class='ctx'> 		#reset-cells = &lt;1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pcie: pcie@1a140000 {</div><div class='add'>+	pciecfg: pciecfg@1a140000 {</div><div class='add'>+		compatible = "mediatek,generic-pciecfg", "syscon";</div><div class='add'>+		reg = &lt;0 0x1a140000 0 0x1000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0: pcie@1a143000 {</div><div class='ctx'> 		compatible = "mediatek,mt7622-pcie";</div><div class='ctx'> 		device_type = "pci";</div><div class='del'>-		reg = &lt;0 0x1a140000 0 0x1000&gt;,</div><div class='del'>-		      &lt;0 0x1a143000 0 0x1000&gt;,</div><div class='del'>-		      &lt;0 0x1a145000 0 0x1000&gt;;</div><div class='del'>-		reg-names = "subsys", "port0", "port1";</div><div class='add'>+		reg = &lt;0 0x1a143000 0 0x1000&gt;;</div><div class='add'>+		reg-names = "port0";</div><div class='add'>+		linux,pci-domain = &lt;0&gt;;</div><div class='ctx'> 		#address-cells = &lt;3&gt;;</div><div class='ctx'> 		#size-cells = &lt;2&gt;;</div><div class='del'>-		interrupts = &lt;GIC_SPI 228 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='del'>-			     &lt;GIC_SPI 229 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 228 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupt-names = "pcie_irq";</div><div class='ctx'> 		clocks = &lt;&amp;pciesys CLK_PCIE_P0_MAC_EN&gt;,</div><div class='del'>-			 &lt;&amp;pciesys CLK_PCIE_P1_MAC_EN&gt;,</div><div class='del'>-			 &lt;&amp;pciesys CLK_PCIE_P0_AHB_EN&gt;,</div><div class='ctx'> 			 &lt;&amp;pciesys CLK_PCIE_P0_AHB_EN&gt;,</div><div class='ctx'> 			 &lt;&amp;pciesys CLK_PCIE_P0_AUX_EN&gt;,</div><div class='del'>-			 &lt;&amp;pciesys CLK_PCIE_P1_AUX_EN&gt;,</div><div class='ctx'> 			 &lt;&amp;pciesys CLK_PCIE_P0_AXI_EN&gt;,</div><div class='del'>-			 &lt;&amp;pciesys CLK_PCIE_P1_AXI_EN&gt;,</div><div class='ctx'> 			 &lt;&amp;pciesys CLK_PCIE_P0_OBFF_EN&gt;,</div><div class='del'>-			 &lt;&amp;pciesys CLK_PCIE_P1_OBFF_EN&gt;,</div><div class='del'>-			 &lt;&amp;pciesys CLK_PCIE_P0_PIPE_EN&gt;,</div><div class='del'>-			 &lt;&amp;pciesys CLK_PCIE_P1_PIPE_EN&gt;;</div><div class='del'>-		clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",</div><div class='del'>-			      "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",</div><div class='del'>-			      "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";</div><div class='add'>+			 &lt;&amp;pciesys CLK_PCIE_P0_PIPE_EN&gt;;</div><div class='add'>+		clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",</div><div class='add'>+			      "axi_ck0", "obff_ck0", "pipe_ck0";</div><div class='add'>+</div><div class='ctx'> 		power-domains = &lt;&amp;scpsys MT7622_POWER_DOMAIN_HIF0&gt;;</div><div class='ctx'> 		bus-range = &lt;0x00 0xff&gt;;</div><div class='del'>-		ranges = &lt;0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000&gt;;</div><div class='add'>+		ranges = &lt;0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000&gt;;</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> </div><div class='del'>-		pcie0: pcie@0,0 {</div><div class='del'>-			reg = &lt;0x0000 0 0 0 0&gt;;</div><div class='del'>-			#address-cells = &lt;3&gt;;</div><div class='del'>-			#size-cells = &lt;2&gt;;</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='add'>+		interrupt-map = &lt;0 0 0 1 &amp;pcie_intc0 0&gt;,</div><div class='add'>+				&lt;0 0 0 2 &amp;pcie_intc0 1&gt;,</div><div class='add'>+				&lt;0 0 0 3 &amp;pcie_intc0 2&gt;,</div><div class='add'>+				&lt;0 0 0 4 &amp;pcie_intc0 3&gt;;</div><div class='add'>+		pcie_intc0: interrupt-controller {</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#address-cells = &lt;0&gt;;</div><div class='ctx'> 			#interrupt-cells = &lt;1&gt;;</div><div class='del'>-			ranges;</div><div class='del'>-			status = "disabled";</div><div class='del'>-</div><div class='del'>-			interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='del'>-			interrupt-map = &lt;0 0 0 1 &amp;pcie_intc0 0&gt;,</div><div class='del'>-					&lt;0 0 0 2 &amp;pcie_intc0 1&gt;,</div><div class='del'>-					&lt;0 0 0 3 &amp;pcie_intc0 2&gt;,</div><div class='del'>-					&lt;0 0 0 4 &amp;pcie_intc0 3&gt;;</div><div class='del'>-			pcie_intc0: interrupt-controller {</div><div class='del'>-				interrupt-controller;</div><div class='del'>-				#address-cells = &lt;0&gt;;</div><div class='del'>-				#interrupt-cells = &lt;1&gt;;</div><div class='del'>-			};</div><div class='ctx'> 		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie1: pcie@1a145000 {</div><div class='add'>+		compatible = "mediatek,mt7622-pcie";</div><div class='add'>+		device_type = "pci";</div><div class='add'>+		reg = &lt;0 0x1a145000 0 0x1000&gt;;</div><div class='add'>+		reg-names = "port1";</div><div class='add'>+		linux,pci-domain = &lt;1&gt;;</div><div class='add'>+		#address-cells = &lt;3&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 229 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupt-names = "pcie_irq";</div><div class='add'>+		clocks = &lt;&amp;pciesys CLK_PCIE_P1_MAC_EN&gt;,</div><div class='add'>+			 /* designer has connect RC1 with p0_ahb clock */</div><div class='add'>+			 &lt;&amp;pciesys CLK_PCIE_P0_AHB_EN&gt;,</div><div class='add'>+			 &lt;&amp;pciesys CLK_PCIE_P1_AUX_EN&gt;,</div><div class='add'>+			 &lt;&amp;pciesys CLK_PCIE_P1_AXI_EN&gt;,</div><div class='add'>+			 &lt;&amp;pciesys CLK_PCIE_P1_OBFF_EN&gt;,</div><div class='add'>+			 &lt;&amp;pciesys CLK_PCIE_P1_PIPE_EN&gt;;</div><div class='add'>+		clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",</div><div class='add'>+			      "axi_ck1", "obff_ck1", "pipe_ck1";</div><div class='add'>+</div><div class='add'>+		power-domains = &lt;&amp;scpsys MT7622_POWER_DOMAIN_HIF0&gt;;</div><div class='add'>+		bus-range = &lt;0x00 0xff&gt;;</div><div class='add'>+		ranges = &lt;0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000&gt;;</div><div class='add'>+		status = "disabled";</div><div class='ctx'> </div><div class='del'>-		pcie1: pcie@1,0 {</div><div class='del'>-			reg = &lt;0x0800 0 0 0 0&gt;;</div><div class='del'>-			#address-cells = &lt;3&gt;;</div><div class='del'>-			#size-cells = &lt;2&gt;;</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='add'>+		interrupt-map = &lt;0 0 0 1 &amp;pcie_intc1 0&gt;,</div><div class='add'>+				&lt;0 0 0 2 &amp;pcie_intc1 1&gt;,</div><div class='add'>+				&lt;0 0 0 3 &amp;pcie_intc1 2&gt;,</div><div class='add'>+				&lt;0 0 0 4 &amp;pcie_intc1 3&gt;;</div><div class='add'>+		pcie_intc1: interrupt-controller {</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#address-cells = &lt;0&gt;;</div><div class='ctx'> 			#interrupt-cells = &lt;1&gt;;</div><div class='del'>-			ranges;</div><div class='del'>-			status = "disabled";</div><div class='del'>-</div><div class='del'>-			interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='del'>-			interrupt-map = &lt;0 0 0 1 &amp;pcie_intc1 0&gt;,</div><div class='del'>-					&lt;0 0 0 2 &amp;pcie_intc1 1&gt;,</div><div class='del'>-					&lt;0 0 0 3 &amp;pcie_intc1 2&gt;,</div><div class='del'>-					&lt;0 0 0 4 &amp;pcie_intc1 3&gt;;</div><div class='del'>-			pcie_intc1: interrupt-controller {</div><div class='del'>-				interrupt-controller;</div><div class='del'>-				#address-cells = &lt;0&gt;;</div><div class='del'>-				#interrupt-cells = &lt;1&gt;;</div><div class='del'>-			};</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -862,8 +904,9 @@</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sata_phy: sata-phy@1a243000 {</div><div class='del'>-		compatible = "mediatek,generic-tphy-v1";</div><div class='add'>+	sata_phy: t-phy {</div><div class='add'>+		compatible = "mediatek,mt7622-tphy",</div><div class='add'>+			     "mediatek,generic-tphy-v1";</div><div class='ctx'> 		#address-cells = &lt;2&gt;;</div><div class='ctx'> 		#size-cells = &lt;2&gt;;</div><div class='ctx'> 		ranges;</div><div class='hunk'>@@ -877,7 +920,13 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	ethsys: syscon@1b000000 {</div><div class='add'>+	hifsys: clock-controller@1af00000 {</div><div class='add'>+		compatible = "mediatek,mt7622-hifsys";</div><div class='add'>+		reg = &lt;0 0x1af00000 0 0x70&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ethsys: clock-controller@1b000000 {</div><div class='ctx'> 		compatible = "mediatek,mt7622-ethsys",</div><div class='ctx'> 			     "syscon";</div><div class='ctx'> 		reg = &lt;0 0x1b000000 0 0x1000&gt;;</div><div class='hunk'>@@ -893,12 +942,31 @@</div><div class='ctx'> 		clock-names = "hsdma";</div><div class='ctx'> 		power-domains = &lt;&amp;scpsys MT7622_POWER_DOMAIN_ETHSYS&gt;;</div><div class='ctx'> 		#dma-cells = &lt;1&gt;;</div><div class='add'>+		dma-requests = &lt;3&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	eth: ethernet@1b100000 {</div><div class='del'>-		compatible = "mediatek,mt7622-eth",</div><div class='del'>-			     "mediatek,mt2701-eth",</div><div class='add'>+	pcie_mirror: pcie-mirror@10000400 {</div><div class='add'>+		compatible = "mediatek,mt7622-pcie-mirror",</div><div class='ctx'> 			     "syscon";</div><div class='add'>+		reg = &lt;0 0x10000400 0 0x10&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wed0: wed@1020a000 {</div><div class='add'>+		compatible = "mediatek,mt7622-wed",</div><div class='add'>+			     "syscon";</div><div class='add'>+		reg = &lt;0 0x1020a000 0 0x1000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 214 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wed1: wed@1020b000 {</div><div class='add'>+		compatible = "mediatek,mt7622-wed",</div><div class='add'>+			     "syscon";</div><div class='add'>+		reg = &lt;0 0x1020b000 0 0x1000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 215 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eth: ethernet@1b100000 {</div><div class='add'>+		compatible = "mediatek,mt7622-eth";</div><div class='ctx'> 		reg = &lt;0 0x1b100000 0 0x20000&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 223 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='ctx'> 			     &lt;GIC_SPI 224 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='hunk'>@@ -921,6 +989,11 @@</div><div class='ctx'> 		power-domains = &lt;&amp;scpsys MT7622_POWER_DOMAIN_ETHSYS&gt;;</div><div class='ctx'> 		mediatek,ethsys = &lt;&amp;ethsys&gt;;</div><div class='ctx'> 		mediatek,sgmiisys = &lt;&amp;sgmiisys&gt;;</div><div class='add'>+		cci-control-port = &lt;&amp;cci_control2&gt;;</div><div class='add'>+		mediatek,wed = &lt;&amp;wed0&gt;, &lt;&amp;wed1&gt;;</div><div class='add'>+		mediatek,pcie-mirror = &lt;&amp;pcie_mirror&gt;;</div><div class='add'>+		mediatek,hifsys = &lt;&amp;hifsys&gt;;</div><div class='add'>+		dma-coherent;</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;0&gt;;</div><div class='ctx'> 		status = "disabled";</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt7981b-cudy-wr3000-v1.dts b/arch/arm64/boot/dts/mediatek/mt7981b-cudy-wr3000-v1.dts<br/>new file mode 100644<br/>index 000000000000..54101cc08a25<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt7981b-cudy-wr3000-v1.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt7981b-cudy-wr3000-v1.dts</a></div><div class='hunk'>@@ -0,0 +1,74 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only OR MIT</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+#include "mt7981b.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "cudy,wr3000-v1", "mediatek,mt7981b";</div><div class='add'>+	model = "Cudy WR3000 V1";</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		reg = &lt;0 0x40000000 0 0x10000000&gt;;</div><div class='add'>+		device_type = "memory";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		key-wps {</div><div class='add'>+			label = "WPS";</div><div class='add'>+			gpios = &lt;&amp;pio 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_WPS_BUTTON&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-reset {</div><div class='add'>+			label = "RESET";</div><div class='add'>+			gpios = &lt;&amp;pio 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_RESTART&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			function = LED_FUNCTION_WAN;</div><div class='add'>+			gpios = &lt;&amp;pio 5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			function = LED_FUNCTION_WLAN_2GHZ;</div><div class='add'>+			gpios = &lt;&amp;pio 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-2 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			function = LED_FUNCTION_WLAN_5GHZ;</div><div class='add'>+			gpios = &lt;&amp;pio 7 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-3 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			function = LED_FUNCTION_LAN;</div><div class='add'>+			gpios = &lt;&amp;pio 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-4 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			gpios = &lt;&amp;pio 10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-5 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			function = LED_FUNCTION_WAN_ONLINE;</div><div class='add'>+			gpios = &lt;&amp;pio 11 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts<br/>new file mode 100644<br/>index 000000000000..2e39e7287730<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts</a></div><div class='hunk'>@@ -0,0 +1,165 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only OR MIT</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "mt7981b.dtsi"</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include "dt-bindings/pinctrl/mt65xx.h"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "openwrt,one", "mediatek,mt7981b";</div><div class='add'>+	model = "OpenWrt One";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		reg = &lt;0 0x40000000 0 0x40000000&gt;;</div><div class='add'>+		device_type = "memory";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pwm-leds {</div><div class='add'>+		compatible = "pwm-leds";</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_WHITE&gt;;</div><div class='add'>+			default-brightness = &lt;0&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			max-brightness = &lt;255&gt;;</div><div class='add'>+			pwms = &lt;&amp;pwm 0 10000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			default-brightness = &lt;0&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			max-brightness = &lt;255&gt;;</div><div class='add'>+			pwms = &lt;&amp;pwm 1 10000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			gpios = &lt;&amp;pio 9 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_AMBER&gt;;</div><div class='add'>+			function = LED_FUNCTION_LAN;</div><div class='add'>+			gpios = &lt;&amp;pio 34 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,default-trigger = "netdev";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-2 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_LAN;</div><div class='add'>+			gpios = &lt;&amp;pio 35 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,default-trigger = "netdev";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	pwm_pins: pwm-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "pwm";</div><div class='add'>+			groups = "pwm0_0", "pwm1_1";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi2_flash_pins: spi2-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "spi";</div><div class='add'>+			groups = "spi2";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		conf-pu {</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_11&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			pins = "SPI2_CS", "SPI2_WP";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		conf-pd {</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_11&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;spi2_flash_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;40000000&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		partitions {</div><div class='add'>+			compatible = "fixed-partitions";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			partition@0 {</div><div class='add'>+				reg = &lt;0x00000 0x40000&gt;;</div><div class='add'>+				label = "bl2-nor";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			partition@40000 {</div><div class='add'>+				reg = &lt;0x40000 0xc0000&gt;;</div><div class='add'>+				label = "factory";</div><div class='add'>+				read-only;</div><div class='add'>+</div><div class='add'>+				nvmem-layout {</div><div class='add'>+					compatible = "fixed-layout";</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					wifi_factory_calibration: eeprom@0 {</div><div class='add'>+						reg = &lt;0x0 0x1000&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					wan_factory_mac: macaddr@24 {</div><div class='add'>+						reg = &lt;0x24 0x6&gt;;</div><div class='add'>+						compatible = "mac-base";</div><div class='add'>+						#nvmem-cell-cells = &lt;1&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			partition@100000 {</div><div class='add'>+				reg = &lt;0x100000 0x80000&gt;;</div><div class='add'>+				label = "fip-nor";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			partition@180000 {</div><div class='add'>+				reg = &lt;0x180000 0xc80000&gt;;</div><div class='add'>+				label = "recovery";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt7981b-xiaomi-ax3000t.dts b/arch/arm64/boot/dts/mediatek/mt7981b-xiaomi-ax3000t.dts<br/>new file mode 100644<br/>index 000000000000..a314c3e05e50<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt7981b-xiaomi-ax3000t.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt7981b-xiaomi-ax3000t.dts</a></div><div class='hunk'>@@ -0,0 +1,15 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only OR MIT</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "mt7981b.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "xiaomi,ax3000t", "mediatek,mt7981b";</div><div class='add'>+	model = "Xiaomi AX3000T";</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		reg = &lt;0 0x40000000 0 0x10000000&gt;;</div><div class='add'>+		device_type = "memory";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi<br/>new file mode 100644<br/>index 000000000000..416096b80770<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt7981b.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt7981b.dtsi</a></div><div class='hunk'>@@ -0,0 +1,302 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only OR MIT</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/mediatek,mt7981-clk.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/reset/mt7986-resets.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "mediatek,mt7981b";</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu@0 {</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x0&gt;;</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu@1 {</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x1&gt;;</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	oscillator-40m {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		clock-frequency = &lt;40000000&gt;;</div><div class='add'>+		clock-output-names = "clkxtal";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-1.0";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */</div><div class='add'>+		secmon_reserved: secmon@43000000 {</div><div class='add'>+			reg = &lt;0 0x43000000 0 0x30000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		ranges;</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@c000000 {</div><div class='add'>+			compatible = "arm,gic-v3";</div><div class='add'>+			reg = &lt;0 0x0c000000 0 0x40000&gt;,  /* GICD */</div><div class='add'>+			      &lt;0 0x0c080000 0 0x200000&gt;; /* GICR */</div><div class='add'>+			interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		infracfg: clock-controller@10001000 {</div><div class='add'>+			compatible = "mediatek,mt7981-infracfg", "syscon";</div><div class='add'>+			reg = &lt;0 0x10001000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		topckgen: clock-controller@1001b000 {</div><div class='add'>+			compatible = "mediatek,mt7981-topckgen", "syscon";</div><div class='add'>+			reg = &lt;0 0x1001b000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		watchdog: watchdog@1001c000 {</div><div class='add'>+			compatible = "mediatek,mt7986-wdt";</div><div class='add'>+			reg = &lt;0 0x1001c000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		apmixedsys: clock-controller@1001e000 {</div><div class='add'>+			compatible = "mediatek,mt7981-apmixedsys";</div><div class='add'>+			reg = &lt;0 0x1001e000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pwm: pwm@10048000 {</div><div class='add'>+			compatible = "mediatek,mt7981-pwm";</div><div class='add'>+			reg = &lt;0 0x10048000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_PWM_STA&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_PWM_HCK&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_PWM1_CK&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_PWM2_CK&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_PWM3_CK&gt;;</div><div class='add'>+			clock-names = "top", "main", "pwm1", "pwm2", "pwm3";</div><div class='add'>+			#pwm-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart0: serial@11002000 {</div><div class='add'>+			compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart";</div><div class='add'>+			reg = &lt;0 0x11002000 0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "uart", "wakeup";</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_UART0_SEL&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_UART0_CK&gt;;</div><div class='add'>+			clock-names = "baud", "bus";</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;uart0_pins&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart1: serial@11003000 {</div><div class='add'>+			compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart";</div><div class='add'>+			reg = &lt;0 0x11003000 0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "uart", "wakeup";</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_UART1_SEL&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_UART1_CK&gt;;</div><div class='add'>+			clock-names = "baud", "bus";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart2: serial@11004000 {</div><div class='add'>+			compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart";</div><div class='add'>+			reg = &lt;0 0x11004000 0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "uart", "wakeup";</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_UART2_SEL&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_UART2_CK&gt;;</div><div class='add'>+			clock-names = "baud", "bus";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@11007000 {</div><div class='add'>+			compatible = "mediatek,mt7981-i2c";</div><div class='add'>+			reg = &lt;0 0x11007000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x10217080 0 0x80&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_I2C0_CK&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_AP_DMA_CK&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_I2C_MCK_CK&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_I2C_PCK_CK&gt;;</div><div class='add'>+			clock-names = "main", "dma", "arb", "pmic";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi2: spi@11009000 {</div><div class='add'>+			compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm";</div><div class='add'>+			reg = &lt;0 0x11009000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_CB_M_D2&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SPI_SEL&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_SPI2_CK&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_SPI2_HCK_CK&gt;;</div><div class='add'>+			clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi@1100a000 {</div><div class='add'>+			compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm";</div><div class='add'>+			reg = &lt;0 0x1100a000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_CB_M_D2&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SPI_SEL&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_SPI0_CK&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_SPI0_HCK_CK&gt;;</div><div class='add'>+			clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi@1100b000 {</div><div class='add'>+			compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm";</div><div class='add'>+			reg = &lt;0 0x1100b000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_CB_M_D2&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SPI_SEL&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_SPI1_CK&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_SPI1_HCK_CK&gt;;</div><div class='add'>+			clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		thermal@1100c800 {</div><div class='add'>+			compatible = "mediatek,mt7981-thermal",</div><div class='add'>+				     "mediatek,mt7986-thermal";</div><div class='add'>+			reg = &lt;0 0x1100c800 0 0x800&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_THERM_CK&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_ADC_26M_CK&gt;;</div><div class='add'>+			clock-names = "therm", "auxadc";</div><div class='add'>+			nvmem-cells = &lt;&amp;thermal_calibration&gt;;</div><div class='add'>+			nvmem-cell-names = "calibration-data";</div><div class='add'>+			#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+			mediatek,auxadc = &lt;&amp;auxadc&gt;;</div><div class='add'>+			mediatek,apmixedsys = &lt;&amp;apmixedsys&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		auxadc: adc@1100d000 {</div><div class='add'>+			compatible = "mediatek,mt7981-auxadc",</div><div class='add'>+				     "mediatek,mt7986-auxadc";</div><div class='add'>+			reg = &lt;0 0x1100d000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_ADC_26M_CK&gt;;</div><div class='add'>+			clock-names = "main";</div><div class='add'>+			#io-channel-cells = &lt;1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pio: pinctrl@11d00000 {</div><div class='add'>+			compatible = "mediatek,mt7981-pinctrl";</div><div class='add'>+			reg = &lt;0 0x11d00000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11c00000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11c10000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11d20000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11e00000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11e20000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11f00000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11f10000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x1000b000 0 0x1000&gt;;</div><div class='add'>+			reg-names = "gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb", "iocfg_lb",</div><div class='add'>+				    "iocfg_bl", "iocfg_tm", "iocfg_tl", "eint";</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			interrupts = &lt;GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;pio 0 0 56&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			uart0_pins: uart0-pins {</div><div class='add'>+				mux {</div><div class='add'>+					function = "uart";</div><div class='add'>+					groups = "uart0";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		efuse@11f20000 {</div><div class='add'>+			compatible = "mediatek,mt7981-efuse", "mediatek,efuse";</div><div class='add'>+			reg = &lt;0 0x11f20000 0 0x1000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			soc-uuid@140 {</div><div class='add'>+				reg = &lt;0x140 0x10&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			thermal_calibration: thermal-calib@274 {</div><div class='add'>+				reg = &lt;0x274 0xc&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		clock-controller@15000000 {</div><div class='add'>+			compatible = "mediatek,mt7981-ethsys", "syscon";</div><div class='add'>+			reg = &lt;0 0x15000000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wifi@18000000 {</div><div class='add'>+			compatible = "mediatek,mt7981-wmac";</div><div class='add'>+			reg = &lt;0 0x18000000 0 0x1000000&gt;,</div><div class='add'>+			      &lt;0 0x10003000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11d10000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_NETSYS_MCU_SEL&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_AP2CNN_HOST_SEL&gt;;</div><div class='add'>+			clock-names = "mcu", "ap2conn";</div><div class='add'>+			resets = &lt;&amp;watchdog MT7986_TOPRGU_CONSYS_SW_RST&gt;;</div><div class='add'>+			reset-names = "consys";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-acelink-ew-7886cax.dts b/arch/arm64/boot/dts/mediatek/mt7986a-acelink-ew-7886cax.dts<br/>new file mode 100644<br/>index 000000000000..30805a610262<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt7986a-acelink-ew-7886cax.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt7986a-acelink-ew-7886cax.dts</a></div><div class='hunk'>@@ -0,0 +1,171 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only OR MIT</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+#include "mt7986a.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "acelink,ew-7886cax", "mediatek,mt7986a";</div><div class='add'>+	model = "Acelink EW-7886CAX";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		reg = &lt;0 0x40000000 0 0x20000000&gt;;</div><div class='add'>+		device_type = "memory";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		key-restart {</div><div class='add'>+			label = "Reset";</div><div class='add'>+			gpios = &lt;&amp;pio 7 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_RESTART&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			gpios = &lt;&amp;pio 18 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			gpios = &lt;&amp;pio 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-2 {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			gpios = &lt;&amp;pio 20 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;crypto {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eth {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mac@1 {</div><div class='add'>+		compatible = "mediatek,eth-mac";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		phy-mode = "2500base-x";</div><div class='add'>+		phy-handle = &lt;&amp;phy6&gt;;</div><div class='add'>+		nvmem-cells = &lt;&amp;macaddr&gt;;</div><div class='add'>+		nvmem-cell-names = "mac-address";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mdio-bus {</div><div class='add'>+		reset-gpios = &lt;&amp;pio 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		reset-delay-us = &lt;50000&gt;;</div><div class='add'>+		reset-post-delay-us = &lt;20000&gt;;</div><div class='add'>+</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		phy6: phy@6 {</div><div class='add'>+			compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+			reg = &lt;6&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash@0 {</div><div class='add'>+		compatible = "spi-nand";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;52000000&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+		partitions {</div><div class='add'>+			compatible = "fixed-partitions";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			partition@0 {</div><div class='add'>+				reg = &lt;0x0 0x100000&gt;;</div><div class='add'>+				label = "bootloader";</div><div class='add'>+				read-only;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			partition@100000 {</div><div class='add'>+				reg = &lt;0x100000 0x80000&gt;;</div><div class='add'>+				label = "u-boot-env";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			partition@180000 {</div><div class='add'>+				compatible = "nvmem-cells";</div><div class='add'>+				reg = &lt;0x180000 0x200000&gt;;</div><div class='add'>+				label = "factory";</div><div class='add'>+				read-only;</div><div class='add'>+</div><div class='add'>+				nvmem-layout {</div><div class='add'>+					compatible = "fixed-layout";</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					eeprom: eeprom@0 {</div><div class='add'>+						reg = &lt;0x0 0x1000&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					macaddr: macaddr@4 {</div><div class='add'>+						reg = &lt;0x4 0x6&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			partition@380000 {</div><div class='add'>+				reg = &lt;0x380000 0x200000&gt;;</div><div class='add'>+				label = "fip";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			partition@580000 {</div><div class='add'>+				reg = &lt;0x580000 0x4000000&gt;;</div><div class='add'>+				label = "ubi";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;trng {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;watchdog {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wifi {</div><div class='add'>+	nvmem-cells = &lt;&amp;eeprom&gt;;</div><div class='add'>+	nvmem-cell-names = "eeprom";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso<br/>new file mode 100644<br/>index 000000000000..047a8388811e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso</a></div><div class='hunk'>@@ -0,0 +1,25 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2021 MediaTek Inc.</div><div class='add'>+ * Author: Sam.Shih &lt;sam.shih@mediatek.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;{/soc/mmc@11230000} {</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	cap-mmc-highspeed;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	mmc-hs400-1_8v;</div><div class='add'>+	hs400-ds-delay = &lt;0x14014&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	no-sd;</div><div class='add'>+	no-sdio;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-mini.dts b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-mini.dts<br/>new file mode 100644<br/>index 000000000000..e2a2fea7adf0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-mini.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-mini.dts</a></div><div class='hunk'>@@ -0,0 +1,493 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2021 MediaTek Inc.</div><div class='add'>+ * Authors: Frank Wunderlich &lt;frank-w@public-files.de&gt;</div><div class='add'>+ *          Eric Woudstra &lt;ericwouds@gmail.com&gt;</div><div class='add'>+ *          Tianling Shen &lt;cnsztl@immortalwrt.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/mt65xx.h&gt;</div><div class='add'>+</div><div class='add'>+#include "mt7986a.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Bananapi BPI-R3 Mini";</div><div class='add'>+	chassis-type = "embedded";</div><div class='add'>+	compatible = "bananapi,bpi-r3mini", "mediatek,mt7986a";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+		ethernet0 = &amp;gmac0;</div><div class='add'>+		ethernet1 = &amp;gmac1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dcin: regulator-12v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "12vd";</div><div class='add'>+		regulator-min-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fan: pwm-fan {</div><div class='add'>+		compatible = "pwm-fan";</div><div class='add'>+		#cooling-cells = &lt;2&gt;;</div><div class='add'>+		/*</div><div class='add'>+		 * The signal is inverted on this board and the PWM driver</div><div class='add'>+		 * does not support polarity inversion.</div><div class='add'>+		 */</div><div class='add'>+		/* cooling level (0, 1, 2) */</div><div class='add'>+		cooling-levels = &lt;255 96 0&gt;;</div><div class='add'>+		pwms = &lt;&amp;pwm 0 10000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_1p8v: regulator-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "1.8vd";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		vin-supply = &lt;&amp;dcin&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3p3v: regulator-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "3.3vd";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		vin-supply = &lt;&amp;dcin&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb_vbus: regulator-5v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "usb_vbus";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		gpios = &lt;&amp;pio 20 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	en8811_a: regulator-phy1 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "phy1";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;pio 16 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	en8811_b: regulator-phy2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "phy2";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;pio 17 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		green_led: led-0 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_POWER;</div><div class='add'>+			gpios = &lt;&amp;pio 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "on";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		reset-key {</div><div class='add'>+			label = "reset";</div><div class='add'>+			linux,code = &lt;KEY_RESTART&gt;;</div><div class='add'>+			gpios = &lt;&amp;pio 7 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu_thermal {</div><div class='add'>+	cooling-maps {</div><div class='add'>+		map0 {</div><div class='add'>+			/* active: set fan to cooling level 2 */</div><div class='add'>+			cooling-device = &lt;&amp;fan 2 2&gt;;</div><div class='add'>+			trip = &lt;&amp;cpu_trip_active_high&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		map1 {</div><div class='add'>+			/* active: set fan to cooling level 1 */</div><div class='add'>+			cooling-device = &lt;&amp;fan 1 1&gt;;</div><div class='add'>+			trip = &lt;&amp;cpu_trip_active_med&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		map2 {</div><div class='add'>+			/* active: set fan to cooling level 0 */</div><div class='add'>+			cooling-device = &lt;&amp;fan 0 0&gt;;</div><div class='add'>+			trip = &lt;&amp;cpu_trip_active_low&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;crypto {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eth {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	gmac0: mac@0 {</div><div class='add'>+		compatible = "mediatek,eth-mac";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		phy-mode = "2500base-x";</div><div class='add'>+		phy-handle = &lt;&amp;phy0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gmac1: mac@1 {</div><div class='add'>+		compatible = "mediatek,eth-mac";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		phy-mode = "2500base-x";</div><div class='add'>+		phy-handle = &lt;&amp;phy1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mdio: mdio-bus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc0 {</div><div class='add'>+	pinctrl-names = "default", "state_uhs";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc0_pins_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;mmc0_pins_uhs&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_1p8v&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* MAC Address EEPROM */</div><div class='add'>+	eeprom@50 {</div><div class='add'>+		compatible = "atmel,24c02";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+</div><div class='add'>+		address-width = &lt;8&gt;;</div><div class='add'>+		pagesize = &lt;8&gt;;</div><div class='add'>+		size = &lt;256&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdio {</div><div class='add'>+	phy0: ethernet-phy@14 {</div><div class='add'>+		reg = &lt;14&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 48 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pio 49 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		reset-assert-us = &lt;10000&gt;;</div><div class='add'>+		reset-deassert-us = &lt;20000&gt;;</div><div class='add'>+		phy-mode = "2500base-x";</div><div class='add'>+		full-duplex;</div><div class='add'>+		pause;</div><div class='add'>+		airoha,pnswap-rx;</div><div class='add'>+</div><div class='add'>+		leds {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			led@0 { /* en8811_a_gpio5 */</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				color = &lt;LED_COLOR_ID_YELLOW&gt;;</div><div class='add'>+				function = LED_FUNCTION_LAN;</div><div class='add'>+				function-enumerator = &lt;1&gt;;</div><div class='add'>+				default-state = "keep";</div><div class='add'>+			};</div><div class='add'>+			led@1 { /* en8811_a_gpio4 */</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+				function = LED_FUNCTION_LAN;</div><div class='add'>+				function-enumerator = &lt;2&gt;;</div><div class='add'>+				default-state = "keep";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	phy1: ethernet-phy@15 {</div><div class='add'>+		reg = &lt;15&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 46 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pio 47 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		reset-assert-us = &lt;10000&gt;;</div><div class='add'>+		reset-deassert-us = &lt;20000&gt;;</div><div class='add'>+		phy-mode = "2500base-x";</div><div class='add'>+		full-duplex;</div><div class='add'>+		pause;</div><div class='add'>+		airoha,pnswap-rx;</div><div class='add'>+</div><div class='add'>+		leds {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			led@0 { /* en8811_b_gpio5 */</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				color = &lt;LED_COLOR_ID_YELLOW&gt;;</div><div class='add'>+				function = LED_FUNCTION_WAN;</div><div class='add'>+				function-enumerator = &lt;1&gt;;</div><div class='add'>+				default-state = "keep";</div><div class='add'>+			};</div><div class='add'>+			led@1 { /* en8811_b_gpio4 */</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+				function = LED_FUNCTION_WAN;</div><div class='add'>+				function-enumerator = &lt;2&gt;;</div><div class='add'>+				default-state = "keep";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pcie_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	i2c_pins: i2c-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "i2c";</div><div class='add'>+			groups = "i2c";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc0_pins_default: mmc0-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "emmc";</div><div class='add'>+			groups = "emmc_51";</div><div class='add'>+		};</div><div class='add'>+		conf-cmd-dat {</div><div class='add'>+			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",</div><div class='add'>+			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",</div><div class='add'>+			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;4&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;; /* pull-up 10K */</div><div class='add'>+		};</div><div class='add'>+		conf-clk {</div><div class='add'>+			pins = "EMMC_CK";</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;; /* pull-down 50K */</div><div class='add'>+		};</div><div class='add'>+		conf-ds {</div><div class='add'>+			pins = "EMMC_DSL";</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;; /* pull-down 50K */</div><div class='add'>+		};</div><div class='add'>+		conf-rst {</div><div class='add'>+			pins = "EMMC_RSTB";</div><div class='add'>+			drive-strength = &lt;4&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;; /* pull-up 10K */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc0_pins_uhs: mmc0-uhs-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "emmc";</div><div class='add'>+			groups = "emmc_51";</div><div class='add'>+		};</div><div class='add'>+		conf-cmd-dat {</div><div class='add'>+			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",</div><div class='add'>+			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",</div><div class='add'>+			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;4&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;; /* pull-up 10K */</div><div class='add'>+		};</div><div class='add'>+		conf-clk {</div><div class='add'>+			pins = "EMMC_CK";</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;; /* pull-down 50K */</div><div class='add'>+		};</div><div class='add'>+		conf-ds {</div><div class='add'>+			pins = "EMMC_DSL";</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;; /* pull-down 50K */</div><div class='add'>+		};</div><div class='add'>+		conf-rst {</div><div class='add'>+			pins = "EMMC_RSTB";</div><div class='add'>+			drive-strength = &lt;4&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;; /* pull-up 10K */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie_pins: pcie-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "pcie";</div><div class='add'>+			groups = "pcie_clk", "pcie_wake", "pcie_pereset";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pwm_pins: pwm-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "pwm";</div><div class='add'>+			groups = "pwm0";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi_flash_pins: spi-flash-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "spi";</div><div class='add'>+			groups = "spi0", "spi0_wp_hold";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb_ngff_pins: usb-ngff-pins {</div><div class='add'>+		ngff-gnss-off-conf {</div><div class='add'>+			pins = "GPIO_6";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			mediatek,pull-up-adv = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+		ngff-pe-rst-conf {</div><div class='add'>+			pins = "GPIO_7";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			mediatek,pull-up-adv = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+		ngff-wwan-off-conf {</div><div class='add'>+			pins = "GPIO_8";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			mediatek,pull-up-adv = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+		ngff-pwr-off-conf {</div><div class='add'>+			pins = "GPIO_9";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			mediatek,pull-up-adv = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+		ngff-rst-conf {</div><div class='add'>+			pins = "GPIO_10";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			mediatek,pull-up-adv = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+		ngff-coex-conf {</div><div class='add'>+			pins = "SPI1_CS";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			mediatek,pull-up-adv = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wf_2g_5g_pins: wf-2g-5g-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "wifi";</div><div class='add'>+			groups = "wf_2g", "wf_5g";</div><div class='add'>+		};</div><div class='add'>+		conf {</div><div class='add'>+			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",</div><div class='add'>+			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",</div><div class='add'>+			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",</div><div class='add'>+			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",</div><div class='add'>+			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",</div><div class='add'>+			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",</div><div class='add'>+			       "WF1_TOP_CLK", "WF1_TOP_DATA";</div><div class='add'>+			drive-strength = &lt;4&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wf_dbdc_pins: wf-dbdc-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "wifi";</div><div class='add'>+			groups = "wf_dbdc";</div><div class='add'>+		};</div><div class='add'>+		conf {</div><div class='add'>+			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",</div><div class='add'>+			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",</div><div class='add'>+			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",</div><div class='add'>+			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",</div><div class='add'>+			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",</div><div class='add'>+			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",</div><div class='add'>+			       "WF1_TOP_CLK", "WF1_TOP_DATA";</div><div class='add'>+			drive-strength = &lt;4&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wf_led_pins: wf-led-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "led";</div><div class='add'>+			groups = "wifi_led";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;spi_flash_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash@0 {</div><div class='add'>+		compatible = "spi-nand";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		spi-max-frequency = &lt;20000000&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;4&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ssusb {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;usb_ngff_pins&gt;;</div><div class='add'>+	vusb33-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='add'>+	vbus-supply = &lt;&amp;usb_vbus&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;trng {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;watchdog {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wifi {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-names = "default", "dbdc";</div><div class='add'>+	pinctrl-0 = &lt;&amp;wf_2g_5g_pins&gt;, &lt;&amp;wf_led_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;wf_dbdc_pins&gt;, &lt;&amp;wf_led_pins&gt;;</div><div class='add'>+</div><div class='add'>+	led {</div><div class='add'>+		led-active-low;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso<br/>new file mode 100644<br/>index 000000000000..24398f8a7da4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso</a></div><div class='hunk'>@@ -0,0 +1,53 @@</div><div class='add'>+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */</div><div class='add'>+/*</div><div class='add'>+ * Authors: Daniel Golle &lt;daniel@makrotopia.org&gt;</div><div class='add'>+ *          Frank Wunderlich &lt;frank-w@public-files.de&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;{/soc/spi@1100a000} {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	spi_nand: flash@0 {</div><div class='add'>+		compatible = "spi-nand";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;10000000&gt;;</div><div class='add'>+		spi-tx-buswidth = &lt;4&gt;;</div><div class='add'>+		spi-rx-buswidth = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+		partitions {</div><div class='add'>+			compatible = "fixed-partitions";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			partition@0 {</div><div class='add'>+				label = "bl2";</div><div class='add'>+				reg = &lt;0x0 0x100000&gt;;</div><div class='add'>+				read-only;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			partition@100000 {</div><div class='add'>+				label = "reserved";</div><div class='add'>+				reg = &lt;0x100000 0x280000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			partition@380000 {</div><div class='add'>+				label = "fip";</div><div class='add'>+				reg = &lt;0x380000 0x200000&gt;;</div><div class='add'>+				read-only;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			partition@580000 {</div><div class='add'>+				label = "ubi";</div><div class='add'>+				reg = &lt;0x580000 0x7a80000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso<br/>new file mode 100644<br/>index 000000000000..6a0d529b54ac<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso</a></div><div class='hunk'>@@ -0,0 +1,61 @@</div><div class='add'>+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */</div><div class='add'>+/*</div><div class='add'>+ * Authors: Daniel Golle &lt;daniel@makrotopia.org&gt;</div><div class='add'>+ *          Frank Wunderlich &lt;frank-w@public-files.de&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;{/soc/spi@1100a000} {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;10000000&gt;;</div><div class='add'>+</div><div class='add'>+		partitions {</div><div class='add'>+			compatible = "fixed-partitions";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			partition@0 {</div><div class='add'>+				label = "bl2";</div><div class='add'>+				reg = &lt;0x0 0x40000&gt;;</div><div class='add'>+				read-only;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			partition@40000 {</div><div class='add'>+				label = "u-boot-env";</div><div class='add'>+				reg = &lt;0x40000 0x40000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			partition@80000 {</div><div class='add'>+				label = "reserved2";</div><div class='add'>+				reg = &lt;0x80000 0x80000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			partition@100000 {</div><div class='add'>+				label = "fip";</div><div class='add'>+				reg = &lt;0x100000 0x80000&gt;;</div><div class='add'>+				read-only;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			partition@180000 {</div><div class='add'>+				label = "recovery";</div><div class='add'>+				reg = &lt;0x180000 0xa80000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			partition@c00000 {</div><div class='add'>+				label = "fit";</div><div class='add'>+				reg = &lt;0xc00000 0x1400000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sata.dtso b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sata.dtso<br/>new file mode 100644<br/>index 000000000000..f7dd52981977<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sata.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sata.dtso</a></div><div class='hunk'>@@ -0,0 +1,34 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2021 MediaTek Inc.</div><div class='add'>+ * Author: Frank Wunderlich &lt;frank-w@public-files.de&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+</div><div class='add'>+&amp;{/} {</div><div class='add'>+	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";</div><div class='add'>+</div><div class='add'>+	reg_sata12v: regulator-sata12v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "sata12v";</div><div class='add'>+		regulator-min-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;12000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;pio 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_sata5v: regulator-sata5v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "sata5v";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		vin-supply = &lt;&amp;reg_sata12v&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso<br/>new file mode 100644<br/>index 000000000000..d9e01967acc4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso</a></div><div class='hunk'>@@ -0,0 +1,19 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2021 MediaTek Inc.</div><div class='add'>+ * Author: Sam.Shih &lt;sam.shih@mediatek.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;{/soc/mmc@11230000} {</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	max-frequency = &lt;52000000&gt;;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts<br/>new file mode 100644<br/>index 000000000000..19f538d160ab<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts</a></div><div class='hunk'>@@ -0,0 +1,497 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2021 MediaTek Inc.</div><div class='add'>+ * Authors: Sam.Shih &lt;sam.shih@mediatek.com&gt;</div><div class='add'>+ *          Frank Wunderlich &lt;frank-w@public-files.de&gt;</div><div class='add'>+ *          Daniel Golle &lt;daniel@makrotopia.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/mt65xx.h&gt;</div><div class='add'>+</div><div class='add'>+#include "mt7986a.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Bananapi BPI-R3";</div><div class='add'>+	chassis-type = "embedded";</div><div class='add'>+	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+		ethernet0 = &amp;gmac0;</div><div class='add'>+		ethernet1 = &amp;gmac1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dcin: regulator-12vd {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "12vd";</div><div class='add'>+		regulator-min-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fan: pwm-fan {</div><div class='add'>+		compatible = "pwm-fan";</div><div class='add'>+		#cooling-cells = &lt;2&gt;;</div><div class='add'>+		/* cooling level (0, 1, 2) - pwm inverted */</div><div class='add'>+		cooling-levels = &lt;255 40 0&gt;;</div><div class='add'>+		pwms = &lt;&amp;pwm 0 10000&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		reset-key {</div><div class='add'>+			label = "reset";</div><div class='add'>+			linux,code = &lt;KEY_RESTART&gt;;</div><div class='add'>+			gpios = &lt;&amp;pio 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wps-key {</div><div class='add'>+			label = "wps";</div><div class='add'>+			linux,code = &lt;KEY_WPS_BUTTON&gt;;</div><div class='add'>+			gpios = &lt;&amp;pio 10 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* i2c of the left SFP cage (wan) */</div><div class='add'>+	i2c_sfp1: i2c-0 {</div><div class='add'>+		compatible = "i2c-gpio";</div><div class='add'>+		sda-gpios = &lt;&amp;pio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+		scl-gpios = &lt;&amp;pio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+		i2c-gpio,delay-us = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* i2c of the right SFP cage (lan) */</div><div class='add'>+	i2c_sfp2: i2c-1 {</div><div class='add'>+		compatible = "i2c-gpio";</div><div class='add'>+		sda-gpios = &lt;&amp;pio 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+		scl-gpios = &lt;&amp;pio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)&gt;;</div><div class='add'>+		i2c-gpio,delay-us = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		green_led: led-0 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_POWER;</div><div class='add'>+			gpios = &lt;&amp;pio 69 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "on";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		blue_led: led-1 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			gpios = &lt;&amp;pio 86 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_1p8v: regulator-1p8v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "1.8vd";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		vin-supply = &lt;&amp;dcin&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3p3v: regulator-3p3v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "3.3vd";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		vin-supply = &lt;&amp;dcin&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* left SFP cage (wan) */</div><div class='add'>+	sfp1: sfp-1 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;i2c_sfp1&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;pio 46 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		maximum-power-milliwatt = &lt;3000&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;pio 49 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;pio 20 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;pio 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* right SFP cage (lan) */</div><div class='add'>+	sfp2: sfp-2 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;i2c_sfp2&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;pio 31 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;pio 47 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		maximum-power-milliwatt = &lt;3000&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;pio 15 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;pio 48 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu_thermal {</div><div class='add'>+	cooling-maps {</div><div class='add'>+		map-cpu-active-high {</div><div class='add'>+			/* active: set fan to cooling level 2 */</div><div class='add'>+			cooling-device = &lt;&amp;fan 2 2&gt;;</div><div class='add'>+			trip = &lt;&amp;cpu_trip_active_high&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		map-cpu-active-med {</div><div class='add'>+			/* active: set fan to cooling level 1 */</div><div class='add'>+			cooling-device = &lt;&amp;fan 1 1&gt;;</div><div class='add'>+			trip = &lt;&amp;cpu_trip_active_med&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		map-cpu-active-low {</div><div class='add'>+			/* active: set fan to cooling level 0 */</div><div class='add'>+			cooling-device = &lt;&amp;fan 0 0&gt;;</div><div class='add'>+			trip = &lt;&amp;cpu_trip_active_low&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;crypto {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eth {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	gmac0: mac@0 {</div><div class='add'>+		compatible = "mediatek,eth-mac";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		phy-mode = "2500base-x";</div><div class='add'>+</div><div class='add'>+		fixed-link {</div><div class='add'>+			speed = &lt;2500&gt;;</div><div class='add'>+			full-duplex;</div><div class='add'>+			pause;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gmac1: mac@1 {</div><div class='add'>+		compatible = "mediatek,eth-mac";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		phy-mode = "2500base-x";</div><div class='add'>+		sfp = &lt;&amp;sfp1&gt;;</div><div class='add'>+		managed = "in-band-status";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mdio: mdio-bus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdio {</div><div class='add'>+	switch: switch@31 {</div><div class='add'>+		compatible = "mediatek,mt7531";</div><div class='add'>+		reg = &lt;31&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		interrupt-parent = &lt;&amp;pio&gt;;</div><div class='add'>+		interrupts = &lt;66 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pio 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc0 {</div><div class='add'>+	pinctrl-names = "default", "state_uhs";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc0_pins_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;mmc0_pins_uhs&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_1p8v&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pcie_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	i2c_pins: i2c-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "i2c";</div><div class='add'>+			groups = "i2c";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc0_pins_default: mmc0-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "emmc";</div><div class='add'>+			groups = "emmc_51";</div><div class='add'>+		};</div><div class='add'>+		conf-cmd-dat {</div><div class='add'>+			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",</div><div class='add'>+			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",</div><div class='add'>+			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;4&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;; /* pull-up 10K */</div><div class='add'>+		};</div><div class='add'>+		conf-clk {</div><div class='add'>+			pins = "EMMC_CK";</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;; /* pull-down 50K */</div><div class='add'>+		};</div><div class='add'>+		conf-ds {</div><div class='add'>+			pins = "EMMC_DSL";</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;; /* pull-down 50K */</div><div class='add'>+		};</div><div class='add'>+		conf-rst {</div><div class='add'>+			pins = "EMMC_RSTB";</div><div class='add'>+			drive-strength = &lt;4&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;; /* pull-up 10K */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc0_pins_uhs: mmc0-uhs-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "emmc";</div><div class='add'>+			groups = "emmc_51";</div><div class='add'>+		};</div><div class='add'>+		conf-cmd-dat {</div><div class='add'>+			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",</div><div class='add'>+			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",</div><div class='add'>+			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;4&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;; /* pull-up 10K */</div><div class='add'>+		};</div><div class='add'>+		conf-clk {</div><div class='add'>+			pins = "EMMC_CK";</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;; /* pull-down 50K */</div><div class='add'>+		};</div><div class='add'>+		conf-ds {</div><div class='add'>+			pins = "EMMC_DSL";</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;; /* pull-down 50K */</div><div class='add'>+		};</div><div class='add'>+		conf-rst {</div><div class='add'>+			pins = "EMMC_RSTB";</div><div class='add'>+			drive-strength = &lt;4&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;; /* pull-up 10K */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie_pins: pcie-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "pcie";</div><div class='add'>+			groups = "pcie_clk", "pcie_pereset";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pwm_pins: pwm-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "pwm";</div><div class='add'>+			groups = "pwm0", "pwm1_0";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi_flash_pins: spi-flash-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "spi";</div><div class='add'>+			groups = "spi0", "spi0_wp_hold";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spic_pins: spic-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "spi";</div><div class='add'>+			groups = "spi1_0";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart1_pins: uart1-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "uart";</div><div class='add'>+			groups = "uart1_rx_tx";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart2_pins: uart2-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "uart";</div><div class='add'>+			groups = "uart2_0_rx_tx";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wf_2g_5g_pins: wf-2g-5g-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "wifi";</div><div class='add'>+			groups = "wf_2g", "wf_5g";</div><div class='add'>+		};</div><div class='add'>+		conf {</div><div class='add'>+			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",</div><div class='add'>+			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",</div><div class='add'>+			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",</div><div class='add'>+			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",</div><div class='add'>+			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",</div><div class='add'>+			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",</div><div class='add'>+			       "WF1_TOP_CLK", "WF1_TOP_DATA";</div><div class='add'>+			drive-strength = &lt;4&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wf_dbdc_pins: wf-dbdc-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "wifi";</div><div class='add'>+			groups = "wf_dbdc";</div><div class='add'>+		};</div><div class='add'>+		conf {</div><div class='add'>+			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",</div><div class='add'>+			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",</div><div class='add'>+			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",</div><div class='add'>+			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",</div><div class='add'>+			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",</div><div class='add'>+			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",</div><div class='add'>+			       "WF1_TOP_CLK", "WF1_TOP_DATA";</div><div class='add'>+			drive-strength = &lt;4&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wf_led_pins: wf-led-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "led";</div><div class='add'>+			groups = "wifi_led";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;spi_flash_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;spic_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ssusb {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;switch {</div><div class='add'>+	ports {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		port@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			label = "wan";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			label = "lan0";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@2 {</div><div class='add'>+			reg = &lt;2&gt;;</div><div class='add'>+			label = "lan1";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@3 {</div><div class='add'>+			reg = &lt;3&gt;;</div><div class='add'>+			label = "lan2";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@4 {</div><div class='add'>+			reg = &lt;4&gt;;</div><div class='add'>+			label = "lan3";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port5: port@5 {</div><div class='add'>+			reg = &lt;5&gt;;</div><div class='add'>+			label = "lan4";</div><div class='add'>+			phy-mode = "2500base-x";</div><div class='add'>+			sfp = &lt;&amp;sfp2&gt;;</div><div class='add'>+			managed = "in-band-status";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@6 {</div><div class='add'>+			reg = &lt;6&gt;;</div><div class='add'>+			label = "cpu";</div><div class='add'>+			ethernet = &lt;&amp;gmac0&gt;;</div><div class='add'>+			phy-mode = "2500base-x";</div><div class='add'>+</div><div class='add'>+			fixed-link {</div><div class='add'>+				speed = &lt;2500&gt;;</div><div class='add'>+				full-duplex;</div><div class='add'>+				pause;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;trng {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart1_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart2_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;watchdog {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wifi {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-names = "default", "dbdc";</div><div class='add'>+	pinctrl-0 = &lt;&amp;wf_2g_5g_pins&gt;, &lt;&amp;wf_led_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;wf_dbdc_pins&gt;, &lt;&amp;wf_led_pins&gt;;</div><div class='add'>+</div><div class='add'>+	led {</div><div class='add'>+		led-active-low;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts<br/>new file mode 100644<br/>index 000000000000..5d8e3d3f6c20<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts</a></div><div class='hunk'>@@ -0,0 +1,355 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2021 MediaTek Inc.</div><div class='add'>+ * Author: Sam.Shih &lt;sam.shih@mediatek.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/mt65xx.h&gt;</div><div class='add'>+</div><div class='add'>+#include "mt7986a.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "MediaTek MT7986a RFB";</div><div class='add'>+	chassis-type = "embedded";</div><div class='add'>+	compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0 0x40000000 0 0x40000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_1p8v: regulator-1p8v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "fixed-1.8V";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3p3v: regulator-3p3v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "fixed-3.3V";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;crypto {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eth {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	gmac0: mac@0 {</div><div class='add'>+		compatible = "mediatek,eth-mac";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		phy-mode = "2500base-x";</div><div class='add'>+</div><div class='add'>+		fixed-link {</div><div class='add'>+			speed = &lt;2500&gt;;</div><div class='add'>+			full-duplex;</div><div class='add'>+			pause;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gmac1: mac@1 {</div><div class='add'>+		compatible = "mediatek,eth-mac";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		phy-mode = "rgmii";</div><div class='add'>+</div><div class='add'>+		fixed-link {</div><div class='add'>+			speed = &lt;1000&gt;;</div><div class='add'>+			full-duplex;</div><div class='add'>+			pause;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mdio: mdio-bus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdio {</div><div class='add'>+	switch: switch@0 {</div><div class='add'>+		compatible = "mediatek,mt7531";</div><div class='add'>+		reg = &lt;31&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pio 5 0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc0 {</div><div class='add'>+	pinctrl-names = "default", "state_uhs";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc0_pins_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;mmc0_pins_uhs&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	cap-mmc-highspeed;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	mmc-hs400-1_8v;</div><div class='add'>+	hs400-ds-delay = &lt;0x14014&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_1p8v&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	no-sd;</div><div class='add'>+	no-sdio;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pcie_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	mmc0_pins_default: mmc0-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "emmc";</div><div class='add'>+			groups = "emmc_51";</div><div class='add'>+		};</div><div class='add'>+		conf-cmd-dat {</div><div class='add'>+			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",</div><div class='add'>+			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",</div><div class='add'>+			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;4&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;; /* pull-up 10K */</div><div class='add'>+		};</div><div class='add'>+		conf-clk {</div><div class='add'>+			pins = "EMMC_CK";</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;; /* pull-down 50K */</div><div class='add'>+		};</div><div class='add'>+		conf-ds {</div><div class='add'>+			pins = "EMMC_DSL";</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;; /* pull-down 50K */</div><div class='add'>+		};</div><div class='add'>+		conf-rst {</div><div class='add'>+			pins = "EMMC_RSTB";</div><div class='add'>+			drive-strength = &lt;4&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;; /* pull-up 10K */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc0_pins_uhs: mmc0-uhs-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "emmc";</div><div class='add'>+			groups = "emmc_51";</div><div class='add'>+		};</div><div class='add'>+		conf-cmd-dat {</div><div class='add'>+			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",</div><div class='add'>+			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",</div><div class='add'>+			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;4&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;; /* pull-up 10K */</div><div class='add'>+		};</div><div class='add'>+		conf-clk {</div><div class='add'>+			pins = "EMMC_CK";</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;; /* pull-down 50K */</div><div class='add'>+		};</div><div class='add'>+		conf-ds {</div><div class='add'>+			pins = "EMMC_DSL";</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;; /* pull-down 50K */</div><div class='add'>+		};</div><div class='add'>+		conf-rst {</div><div class='add'>+			pins = "EMMC_RSTB";</div><div class='add'>+			drive-strength = &lt;4&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;; /* pull-up 10K */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie_pins: pcie-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "pcie";</div><div class='add'>+			groups = "pcie_clk", "pcie_wake", "pcie_pereset";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi_flash_pins: spi-flash-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "spi";</div><div class='add'>+			groups = "spi0", "spi0_wp_hold";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spic_pins: spic-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "spi";</div><div class='add'>+			groups = "spi1_2";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart1_pins: uart1-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "uart";</div><div class='add'>+			groups = "uart1";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart2_pins: uart2-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "uart";</div><div class='add'>+			groups = "uart2";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wf_2g_5g_pins: wf-2g-5g-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "wifi";</div><div class='add'>+			groups = "wf_2g", "wf_5g";</div><div class='add'>+		};</div><div class='add'>+		conf {</div><div class='add'>+			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",</div><div class='add'>+			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",</div><div class='add'>+			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",</div><div class='add'>+			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",</div><div class='add'>+			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",</div><div class='add'>+			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",</div><div class='add'>+			       "WF1_TOP_CLK", "WF1_TOP_DATA";</div><div class='add'>+			drive-strength = &lt;4&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wf_dbdc_pins: wf-dbdc-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "wifi";</div><div class='add'>+			groups = "wf_dbdc";</div><div class='add'>+		};</div><div class='add'>+		conf {</div><div class='add'>+			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",</div><div class='add'>+			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",</div><div class='add'>+			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",</div><div class='add'>+			       "WF0_TOP_CLK", "WF0_TOP_DATA";</div><div class='add'>+			drive-strength = &lt;4&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;spi_flash_pins&gt;;</div><div class='add'>+	cs-gpios = &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	spi_nand: flash@0 {</div><div class='add'>+		compatible = "spi-nand";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;10000000&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;4&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;spic_pins&gt;;</div><div class='add'>+	cs-gpios = &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ssusb {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;switch {</div><div class='add'>+	ports {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		port@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			label = "lan0";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			label = "lan1";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@2 {</div><div class='add'>+			reg = &lt;2&gt;;</div><div class='add'>+			label = "lan2";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@3 {</div><div class='add'>+			reg = &lt;3&gt;;</div><div class='add'>+			label = "lan3";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@4 {</div><div class='add'>+			reg = &lt;4&gt;;</div><div class='add'>+			label = "lan4";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@5 {</div><div class='add'>+			reg = &lt;5&gt;;</div><div class='add'>+			ethernet = &lt;&amp;gmac1&gt;;</div><div class='add'>+			phy-mode = "rgmii";</div><div class='add'>+</div><div class='add'>+			fixed-link {</div><div class='add'>+				speed = &lt;1000&gt;;</div><div class='add'>+				full-duplex;</div><div class='add'>+				pause;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@6 {</div><div class='add'>+			reg = &lt;6&gt;;</div><div class='add'>+			label = "cpu";</div><div class='add'>+			ethernet = &lt;&amp;gmac0&gt;;</div><div class='add'>+			phy-mode = "2500base-x";</div><div class='add'>+</div><div class='add'>+			fixed-link {</div><div class='add'>+				speed = &lt;2500&gt;;</div><div class='add'>+				full-duplex;</div><div class='add'>+				pause;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart1_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart2_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wifi {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-names = "default", "dbdc";</div><div class='add'>+	pinctrl-0 = &lt;&amp;wf_2g_5g_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;wf_dbdc_pins&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi<br/>new file mode 100644<br/>index 000000000000..7790601586cc<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt7986a.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt7986a.dtsi</a></div><div class='hunk'>@@ -0,0 +1,665 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2021 MediaTek Inc.</div><div class='add'>+ * Author: Sam.Shih &lt;sam.shih@mediatek.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/mt7986-clk.h&gt;</div><div class='add'>+#include &lt;dt-bindings/reset/mt7986-resets.h&gt;</div><div class='add'>+#include &lt;dt-bindings/phy/phy.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "mediatek,mt7986a";</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x0&gt;;</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@1 {</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x1&gt;;</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@2 {</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x2&gt;;</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@3 {</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x3&gt;;</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk40m: oscillator-40m {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		clock-frequency = &lt;40000000&gt;;</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-output-names = "clkxtal";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-0.2";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */</div><div class='add'>+		secmon_reserved: secmon@43000000 {</div><div class='add'>+			reg = &lt;0 0x43000000 0 0x30000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wmcpu_emi: wmcpu-reserved@4fc00000 {</div><div class='add'>+			no-map;</div><div class='add'>+			reg = &lt;0 0x4fc00000 0 0x00100000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wo_emi0: wo-emi@4fd00000 {</div><div class='add'>+			reg = &lt;0 0x4fd00000 0 0x40000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wo_emi1: wo-emi@4fd40000 {</div><div class='add'>+			reg = &lt;0 0x4fd40000 0 0x40000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wo_ilm0: wo-ilm@151e0000 {</div><div class='add'>+			reg = &lt;0 0x151e0000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wo_ilm1: wo-ilm@151f0000 {</div><div class='add'>+			reg = &lt;0 0x151f0000 0 0x8000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wo_data: wo-data@4fd80000 {</div><div class='add'>+			reg = &lt;0 0x4fd80000 0 0x240000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wo_dlm0: wo-dlm@151e8000 {</div><div class='add'>+			reg = &lt;0 0x151e8000 0 0x2000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wo_dlm1: wo-dlm@151f8000 {</div><div class='add'>+			reg = &lt;0 0x151f8000 0 0x2000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wo_boot: wo-boot@15194000 {</div><div class='add'>+			reg = &lt;0 0x15194000 0 0x1000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		ranges;</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@c000000 {</div><div class='add'>+			compatible = "arm,gic-v3";</div><div class='add'>+			reg = &lt;0 0x0c000000 0 0x10000&gt;,  /* GICD */</div><div class='add'>+			      &lt;0 0x0c080000 0 0x80000&gt;,  /* GICR */</div><div class='add'>+			      &lt;0 0x0c400000 0 0x2000&gt;,   /* GICC */</div><div class='add'>+			      &lt;0 0x0c410000 0 0x1000&gt;,   /* GICH */</div><div class='add'>+			      &lt;0 0x0c420000 0 0x2000&gt;;   /* GICV */</div><div class='add'>+			interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		infracfg: infracfg@10001000 {</div><div class='add'>+			compatible = "mediatek,mt7986-infracfg", "syscon";</div><div class='add'>+			reg = &lt;0 0x10001000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wed_pcie: wed-pcie@10003000 {</div><div class='add'>+			compatible = "mediatek,mt7986-wed-pcie",</div><div class='add'>+				     "syscon";</div><div class='add'>+			reg = &lt;0 0x10003000 0 0x10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		topckgen: topckgen@1001b000 {</div><div class='add'>+			compatible = "mediatek,mt7986-topckgen", "syscon";</div><div class='add'>+			reg = &lt;0 0x1001B000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		watchdog: watchdog@1001c000 {</div><div class='add'>+			compatible = "mediatek,mt7986-wdt";</div><div class='add'>+			reg = &lt;0 0x1001c000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		apmixedsys: apmixedsys@1001e000 {</div><div class='add'>+			compatible = "mediatek,mt7986-apmixedsys";</div><div class='add'>+			reg = &lt;0 0x1001E000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pio: pinctrl@1001f000 {</div><div class='add'>+			compatible = "mediatek,mt7986a-pinctrl";</div><div class='add'>+			reg = &lt;0 0x1001f000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11c30000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11c40000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11e20000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11e30000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11f00000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11f10000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x1000b000 0 0x1000&gt;;</div><div class='add'>+			reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt",</div><div class='add'>+				    "iocfg_lb", "iocfg_tr", "iocfg_tl", "eint";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;pio 0 0 100&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			interrupts = &lt;GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pwm: pwm@10048000 {</div><div class='add'>+			compatible = "mediatek,mt7986-pwm";</div><div class='add'>+			reg = &lt;0 0x10048000 0 0x1000&gt;;</div><div class='add'>+			#pwm-cells = &lt;2&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_PWM_SEL&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_PWM_STA&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_PWM1_CK&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_PWM2_CK&gt;;</div><div class='add'>+			clock-names = "top", "main", "pwm1", "pwm2";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sgmiisys0: syscon@10060000 {</div><div class='add'>+			compatible = "mediatek,mt7986-sgmiisys_0",</div><div class='add'>+				     "syscon";</div><div class='add'>+			reg = &lt;0 0x10060000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sgmiisys1: syscon@10070000 {</div><div class='add'>+			compatible = "mediatek,mt7986-sgmiisys_1",</div><div class='add'>+				     "syscon";</div><div class='add'>+			reg = &lt;0 0x10070000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		trng: rng@1020f000 {</div><div class='add'>+			compatible = "mediatek,mt7986-rng",</div><div class='add'>+				     "mediatek,mt7623-rng";</div><div class='add'>+			reg = &lt;0 0x1020f000 0 0x100&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_TRNG_CK&gt;;</div><div class='add'>+			clock-names = "rng";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		crypto: crypto@10320000 {</div><div class='add'>+			compatible = "inside-secure,safexcel-eip97";</div><div class='add'>+			reg = &lt;0 0x10320000 0 0x40000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "ring0", "ring1", "ring2", "ring3";</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_EIP97_CK&gt;;</div><div class='add'>+			assigned-clocks = &lt;&amp;topckgen CLK_TOP_EIP_B_SEL&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;apmixedsys CLK_APMIXED_NET2PLL&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart0: serial@11002000 {</div><div class='add'>+			compatible = "mediatek,mt7986-uart",</div><div class='add'>+				     "mediatek,mt6577-uart";</div><div class='add'>+			reg = &lt;0 0x11002000 0 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_UART0_SEL&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_UART0_CK&gt;;</div><div class='add'>+			clock-names = "baud", "bus";</div><div class='add'>+			assigned-clocks = &lt;&amp;topckgen CLK_TOP_UART_SEL&gt;,</div><div class='add'>+					  &lt;&amp;infracfg CLK_INFRA_UART0_SEL&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_XTAL&gt;,</div><div class='add'>+						 &lt;&amp;topckgen CLK_TOP_UART_SEL&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart1: serial@11003000 {</div><div class='add'>+			compatible = "mediatek,mt7986-uart",</div><div class='add'>+				     "mediatek,mt6577-uart";</div><div class='add'>+			reg = &lt;0 0x11003000 0 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_UART1_SEL&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_UART1_CK&gt;;</div><div class='add'>+			clock-names = "baud", "bus";</div><div class='add'>+			assigned-clocks = &lt;&amp;infracfg CLK_INFRA_UART1_SEL&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_F26M_SEL&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart2: serial@11004000 {</div><div class='add'>+			compatible = "mediatek,mt7986-uart",</div><div class='add'>+				     "mediatek,mt6577-uart";</div><div class='add'>+			reg = &lt;0 0x11004000 0 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_UART2_SEL&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_UART2_CK&gt;;</div><div class='add'>+			clock-names = "baud", "bus";</div><div class='add'>+			assigned-clocks = &lt;&amp;infracfg CLK_INFRA_UART2_SEL&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_F26M_SEL&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c0: i2c@11008000 {</div><div class='add'>+			compatible = "mediatek,mt7986-i2c";</div><div class='add'>+			reg = &lt;0 0x11008000 0 0x90&gt;,</div><div class='add'>+			      &lt;0 0x10217080 0 0x80&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clock-div = &lt;5&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_I2C0_CK&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_AP_DMA_CK&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi0: spi@1100a000 {</div><div class='add'>+			compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";</div><div class='add'>+			reg = &lt;0 0x1100a000 0 0x100&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_MPLL_D2&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SPI_SEL&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_SPI0_CK&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_SPI0_HCK_CK&gt;;</div><div class='add'>+			clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi1: spi@1100b000 {</div><div class='add'>+			compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";</div><div class='add'>+			reg = &lt;0 0x1100b000 0 0x100&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_MPLL_D2&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SPIM_MST_SEL&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_SPI1_CK&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_SPI1_HCK_CK&gt;;</div><div class='add'>+			clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		thermal: thermal@1100c800 {</div><div class='add'>+			compatible = "mediatek,mt7986-thermal";</div><div class='add'>+			reg = &lt;0 0x1100c800 0 0x800&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_THERM_CK&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_ADC_26M_CK&gt;;</div><div class='add'>+			clock-names = "therm", "auxadc";</div><div class='add'>+			nvmem-cells = &lt;&amp;thermal_calibration&gt;;</div><div class='add'>+			nvmem-cell-names = "calibration-data";</div><div class='add'>+			#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+			mediatek,auxadc = &lt;&amp;auxadc&gt;;</div><div class='add'>+			mediatek,apmixedsys = &lt;&amp;apmixedsys&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		auxadc: adc@1100d000 {</div><div class='add'>+			compatible = "mediatek,mt7986-auxadc";</div><div class='add'>+			reg = &lt;0 0x1100d000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_ADC_26M_CK&gt;;</div><div class='add'>+			clock-names = "main";</div><div class='add'>+			#io-channel-cells = &lt;1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ssusb: usb@11200000 {</div><div class='add'>+			compatible = "mediatek,mt7986-xhci",</div><div class='add'>+				     "mediatek,mtk-xhci";</div><div class='add'>+			reg = &lt;0 0x11200000 0 0x2e00&gt;,</div><div class='add'>+			      &lt;0 0x11203e00 0 0x0100&gt;;</div><div class='add'>+			reg-names = "mac", "ippc";</div><div class='add'>+			interrupts = &lt;GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_IUSB_SYS_CK&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_IUSB_CK&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_IUSB_133_CK&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_IUSB_66M_CK&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_U2U3_XHCI_SEL&gt;;</div><div class='add'>+			clock-names = "sys_ck",</div><div class='add'>+				      "ref_ck",</div><div class='add'>+				      "mcu_ck",</div><div class='add'>+				      "dma_ck",</div><div class='add'>+				      "xhci_ck";</div><div class='add'>+			phys = &lt;&amp;u2port0 PHY_TYPE_USB2&gt;,</div><div class='add'>+			       &lt;&amp;u3port0 PHY_TYPE_USB3&gt;,</div><div class='add'>+			       &lt;&amp;u2port1 PHY_TYPE_USB2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmc0: mmc@11230000 {</div><div class='add'>+			compatible = "mediatek,mt7986-mmc";</div><div class='add'>+			reg = &lt;0 0x11230000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11c20000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			assigned-clocks = &lt;&amp;topckgen CLK_TOP_EMMC_416M_SEL&gt;,</div><div class='add'>+					  &lt;&amp;topckgen CLK_TOP_EMMC_250M_SEL&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;apmixedsys CLK_APMIXED_MPLL&gt;,</div><div class='add'>+						 &lt;&amp;topckgen CLK_TOP_NET1PLL_D5_D2&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_EMMC_416M_SEL&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_MSDC_HCK_CK&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_MSDC_CK&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_MSDC_133M_CK&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_MSDC_66M_CK&gt;;</div><div class='add'>+			clock-names = "source", "hclk", "source_cg", "bus_clk",</div><div class='add'>+				      "sys_cg";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie: pcie@11280000 {</div><div class='add'>+			compatible = "mediatek,mt7986-pcie",</div><div class='add'>+				     "mediatek,mt8192-pcie";</div><div class='add'>+			reg = &lt;0x00 0x11280000 0x00 0x4000&gt;;</div><div class='add'>+			reg-names = "pcie-mac";</div><div class='add'>+			ranges = &lt;0x82000000 0x00 0x20000000 0x00</div><div class='add'>+				  0x20000000 0x00 0x10000000&gt;;</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			bus-range = &lt;0x00 0xff&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_IPCIE_PIPE_CK&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_IPCIE_CK&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_IPCIER_CK&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_IPCIEB_CK&gt;;</div><div class='add'>+			clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m";</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;pcie_port PHY_TYPE_PCIE&gt;;</div><div class='add'>+			phy-names = "pcie-phy";</div><div class='add'>+</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0x7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;pcie_intc 0&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;pcie_intc 1&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;pcie_intc 2&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;pcie_intc 3&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcie_intc: interrupt-controller {</div><div class='add'>+				#address-cells = &lt;0&gt;;</div><div class='add'>+				#interrupt-cells = &lt;1&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie_phy: t-phy@11c00000 {</div><div class='add'>+			compatible = "mediatek,mt7986-tphy",</div><div class='add'>+				     "mediatek,generic-tphy-v2";</div><div class='add'>+			ranges = &lt;0 0 0x11c00000 0x20000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcie_port: pcie-phy@0 {</div><div class='add'>+				reg = &lt;0 0x20000&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk40m&gt;;</div><div class='add'>+				clock-names = "ref";</div><div class='add'>+				#phy-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		efuse: efuse@11d00000 {</div><div class='add'>+			compatible = "mediatek,mt7986-efuse", "mediatek,efuse";</div><div class='add'>+			reg = &lt;0 0x11d00000 0 0x1000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			soc-uuid@140 {</div><div class='add'>+				reg = &lt;0x140 0x8&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			thermal_calibration: calib@274 {</div><div class='add'>+				reg = &lt;0x274 0xc&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_phy: t-phy@11e10000 {</div><div class='add'>+			compatible = "mediatek,mt7986-tphy",</div><div class='add'>+				     "mediatek,generic-tphy-v2";</div><div class='add'>+			ranges = &lt;0 0 0x11e10000 0x1700&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			u2port0: usb-phy@0 {</div><div class='add'>+				reg = &lt;0x0 0x700&gt;;</div><div class='add'>+				clocks = &lt;&amp;topckgen CLK_TOP_DA_U2_REFSEL&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_DA_U2_CK_1P_SEL&gt;;</div><div class='add'>+				clock-names = "ref", "da_ref";</div><div class='add'>+				#phy-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			u3port0: usb-phy@700 {</div><div class='add'>+				reg = &lt;0x700 0x900&gt;;</div><div class='add'>+				clocks = &lt;&amp;topckgen CLK_TOP_USB3_PHY_SEL&gt;;</div><div class='add'>+				clock-names = "ref";</div><div class='add'>+				#phy-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			u2port1: usb-phy@1000 {</div><div class='add'>+				reg = &lt;0x1000 0x700&gt;;</div><div class='add'>+				clocks = &lt;&amp;topckgen CLK_TOP_DA_U2_REFSEL&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_DA_U2_CK_1P_SEL&gt;;</div><div class='add'>+				clock-names = "ref", "da_ref";</div><div class='add'>+				#phy-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ethsys: syscon@15000000 {</div><div class='add'>+			 compatible = "mediatek,mt7986-ethsys",</div><div class='add'>+				      "syscon";</div><div class='add'>+			 reg = &lt;0 0x15000000 0 0x1000&gt;;</div><div class='add'>+			 #clock-cells = &lt;1&gt;;</div><div class='add'>+			 #reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wed0: wed@15010000 {</div><div class='add'>+			compatible = "mediatek,mt7986-wed",</div><div class='add'>+				     "syscon";</div><div class='add'>+			reg = &lt;0 0x15010000 0 0x1000&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			memory-region = &lt;&amp;wo_emi0&gt;, &lt;&amp;wo_ilm0&gt;, &lt;&amp;wo_dlm0&gt;,</div><div class='add'>+					&lt;&amp;wo_data&gt;, &lt;&amp;wo_boot&gt;;</div><div class='add'>+			memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",</div><div class='add'>+					      "wo-data", "wo-boot";</div><div class='add'>+			mediatek,wo-ccif = &lt;&amp;wo_ccif0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wed1: wed@15011000 {</div><div class='add'>+			compatible = "mediatek,mt7986-wed",</div><div class='add'>+				     "syscon";</div><div class='add'>+			reg = &lt;0 0x15011000 0 0x1000&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			memory-region = &lt;&amp;wo_emi1&gt;, &lt;&amp;wo_ilm1&gt;, &lt;&amp;wo_dlm1&gt;,</div><div class='add'>+					&lt;&amp;wo_data&gt;, &lt;&amp;wo_boot&gt;;</div><div class='add'>+			memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",</div><div class='add'>+					      "wo-data", "wo-boot";</div><div class='add'>+			mediatek,wo-ccif = &lt;&amp;wo_ccif1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		eth: ethernet@15100000 {</div><div class='add'>+			compatible = "mediatek,mt7986-eth";</div><div class='add'>+			reg = &lt;0 0x15100000 0 0x40000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "fe0", "fe1", "fe2", "fe3", "pdma0",</div><div class='add'>+					  "pdma1", "pdma2", "pdma3";</div><div class='add'>+			clocks = &lt;&amp;ethsys CLK_ETH_FE_EN&gt;,</div><div class='add'>+				 &lt;&amp;ethsys CLK_ETH_GP2_EN&gt;,</div><div class='add'>+				 &lt;&amp;ethsys CLK_ETH_GP1_EN&gt;,</div><div class='add'>+				 &lt;&amp;ethsys CLK_ETH_WOCPU1_EN&gt;,</div><div class='add'>+				 &lt;&amp;ethsys CLK_ETH_WOCPU0_EN&gt;,</div><div class='add'>+				 &lt;&amp;sgmiisys0 CLK_SGMII0_TX250M_EN&gt;,</div><div class='add'>+				 &lt;&amp;sgmiisys0 CLK_SGMII0_RX250M_EN&gt;,</div><div class='add'>+				 &lt;&amp;sgmiisys0 CLK_SGMII0_CDR_REF&gt;,</div><div class='add'>+				 &lt;&amp;sgmiisys0 CLK_SGMII0_CDR_FB&gt;,</div><div class='add'>+				 &lt;&amp;sgmiisys1 CLK_SGMII1_TX250M_EN&gt;,</div><div class='add'>+				 &lt;&amp;sgmiisys1 CLK_SGMII1_RX250M_EN&gt;,</div><div class='add'>+				 &lt;&amp;sgmiisys1 CLK_SGMII1_CDR_REF&gt;,</div><div class='add'>+				 &lt;&amp;sgmiisys1 CLK_SGMII1_CDR_FB&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_NETSYS_SEL&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_NETSYS_500M_SEL&gt;;</div><div class='add'>+			clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",</div><div class='add'>+				      "sgmii_tx250m", "sgmii_rx250m",</div><div class='add'>+				      "sgmii_cdr_ref", "sgmii_cdr_fb",</div><div class='add'>+				      "sgmii2_tx250m", "sgmii2_rx250m",</div><div class='add'>+				      "sgmii2_cdr_ref", "sgmii2_cdr_fb",</div><div class='add'>+				      "netsys0", "netsys1";</div><div class='add'>+			assigned-clocks = &lt;&amp;topckgen CLK_TOP_NETSYS_2X_SEL&gt;,</div><div class='add'>+					  &lt;&amp;topckgen CLK_TOP_SGM_325M_SEL&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;apmixedsys CLK_APMIXED_NET2PLL&gt;,</div><div class='add'>+						 &lt;&amp;apmixedsys CLK_APMIXED_SGMPLL&gt;;</div><div class='add'>+			sram = &lt;&amp;eth_sram&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			mediatek,ethsys = &lt;&amp;ethsys&gt;;</div><div class='add'>+			mediatek,sgmiisys = &lt;&amp;sgmiisys0&gt;, &lt;&amp;sgmiisys1&gt;;</div><div class='add'>+			mediatek,wed-pcie = &lt;&amp;wed_pcie&gt;;</div><div class='add'>+			mediatek,wed = &lt;&amp;wed0&gt;, &lt;&amp;wed1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/*15100000+0x40000*/</div><div class='add'>+		eth_sram: sram@15140000 {</div><div class='add'>+			compatible = "mmio-sram";</div><div class='add'>+			reg = &lt;0 0x15140000 0 0x40000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges = &lt;0 0x15140000 0 0x40000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wo_ccif0: syscon@151a5000 {</div><div class='add'>+			compatible = "mediatek,mt7986-wo-ccif", "syscon";</div><div class='add'>+			reg = &lt;0 0x151a5000 0 0x1000&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wo_ccif1: syscon@151ad000 {</div><div class='add'>+			compatible = "mediatek,mt7986-wo-ccif", "syscon";</div><div class='add'>+			reg = &lt;0 0x151ad000 0 0x1000&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wifi: wifi@18000000 {</div><div class='add'>+			compatible = "mediatek,mt7986-wmac";</div><div class='add'>+			reg = &lt;0 0x18000000 0 0x1000000&gt;,</div><div class='add'>+			      &lt;0 0x10003000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11d10000 0 0x1000&gt;;</div><div class='add'>+			resets = &lt;&amp;watchdog MT7986_TOPRGU_CONSYS_SW_RST&gt;;</div><div class='add'>+			reset-names = "consys";</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_CONN_MCUSYS_SEL&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_AP2CNN_HOST_SEL&gt;;</div><div class='add'>+			clock-names = "mcu", "ap2conn";</div><div class='add'>+			interrupts = &lt;GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			memory-region = &lt;&amp;wmcpu_emi&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	thermal-zones {</div><div class='add'>+		cpu_thermal: cpu-thermal {</div><div class='add'>+			polling-delay-passive = &lt;1000&gt;;</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;thermal 0&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu_trip_crit: crit {</div><div class='add'>+					temperature = &lt;125000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_trip_hot: hot {</div><div class='add'>+					temperature = &lt;120000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_trip_active_high: active-high {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "active";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_trip_active_med: active-med {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "active";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_trip_active_low: active-low {</div><div class='add'>+					temperature = &lt;60000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "active";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts<br/>new file mode 100644<br/>index 000000000000..58f77d932429<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts</a></div><div class='hunk'>@@ -0,0 +1,213 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2021 MediaTek Inc.</div><div class='add'>+ * Author: Sam.Shih &lt;sam.shih@mediatek.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt7986b.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "MediaTek MT7986b RFB";</div><div class='add'>+	chassis-type = "embedded";</div><div class='add'>+	compatible = "mediatek,mt7986b-rfb", "mediatek,mt7986b";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0 0x40000000 0 0x40000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;crypto {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eth {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	gmac0: mac@0 {</div><div class='add'>+		compatible = "mediatek,eth-mac";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		phy-mode = "2500base-x";</div><div class='add'>+</div><div class='add'>+		fixed-link {</div><div class='add'>+			speed = &lt;2500&gt;;</div><div class='add'>+			full-duplex;</div><div class='add'>+			pause;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gmac1: mac@1 {</div><div class='add'>+		compatible = "mediatek,eth-mac";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		phy-mode = "rgmii";</div><div class='add'>+</div><div class='add'>+		fixed-link {</div><div class='add'>+			speed = &lt;1000&gt;;</div><div class='add'>+			full-duplex;</div><div class='add'>+			pause;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mdio: mdio-bus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		switch@0 {</div><div class='add'>+			compatible = "mediatek,mt7531";</div><div class='add'>+			reg = &lt;31&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;pio 5 0&gt;;</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					label = "lan0";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					label = "lan1";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@2 {</div><div class='add'>+					reg = &lt;2&gt;;</div><div class='add'>+					label = "lan2";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@3 {</div><div class='add'>+					reg = &lt;3&gt;;</div><div class='add'>+					label = "lan3";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@4 {</div><div class='add'>+					reg = &lt;4&gt;;</div><div class='add'>+					label = "lan4";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@5 {</div><div class='add'>+					reg = &lt;5&gt;;</div><div class='add'>+					ethernet = &lt;&amp;gmac1&gt;;</div><div class='add'>+					phy-mode = "rgmii";</div><div class='add'>+</div><div class='add'>+					fixed-link {</div><div class='add'>+						speed = &lt;1000&gt;;</div><div class='add'>+						full-duplex;</div><div class='add'>+						pause;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@6 {</div><div class='add'>+					reg = &lt;6&gt;;</div><div class='add'>+					label = "cpu";</div><div class='add'>+					ethernet = &lt;&amp;gmac0&gt;;</div><div class='add'>+					phy-mode = "2500base-x";</div><div class='add'>+</div><div class='add'>+					fixed-link {</div><div class='add'>+						speed = &lt;2500&gt;;</div><div class='add'>+						full-duplex;</div><div class='add'>+						pause;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	spi_flash_pins: spi-flash-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "spi";</div><div class='add'>+			groups = "spi0", "spi0_wp_hold";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spic_pins: spic-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "spi";</div><div class='add'>+			groups = "spi1_2";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wf_2g_5g_pins: wf-2g-5g-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "wifi";</div><div class='add'>+			groups = "wf_2g", "wf_5g";</div><div class='add'>+		};</div><div class='add'>+		conf {</div><div class='add'>+			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",</div><div class='add'>+			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",</div><div class='add'>+			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",</div><div class='add'>+			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",</div><div class='add'>+			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",</div><div class='add'>+			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",</div><div class='add'>+			       "WF1_TOP_CLK", "WF1_TOP_DATA";</div><div class='add'>+			drive-strength = &lt;4&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wf_dbdc_pins: wf-dbdc-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "wifi";</div><div class='add'>+			groups = "wf_dbdc";</div><div class='add'>+		};</div><div class='add'>+		conf {</div><div class='add'>+			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",</div><div class='add'>+			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",</div><div class='add'>+			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",</div><div class='add'>+			       "WF0_TOP_CLK", "WF0_TOP_DATA";</div><div class='add'>+			drive-strength = &lt;4&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;spi_flash_pins&gt;;</div><div class='add'>+	cs-gpios = &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	spi_nand: flash@0 {</div><div class='add'>+		compatible = "spi-nand";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;10000000&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;4&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;spic_pins&gt;;</div><div class='add'>+	cs-gpios = &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ssusb {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wifi {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-names = "default", "dbdc";</div><div class='add'>+	pinctrl-0 = &lt;&amp;wf_2g_5g_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;wf_dbdc_pins&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt7986b.dtsi b/arch/arm64/boot/dts/mediatek/mt7986b.dtsi<br/>new file mode 100644<br/>index 000000000000..db5189664c29<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt7986b.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt7986b.dtsi</a></div><div class='hunk'>@@ -0,0 +1,15 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2021 MediaTek Inc.</div><div class='add'>+ * Author: Sam.Shih &lt;sam.shih@mediatek.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "mt7986a.dtsi"</div><div class='add'>+/ {</div><div class='add'>+	compatible = "mediatek,mt7986b";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	compatible = "mediatek,mt7986b-pinctrl";</div><div class='add'>+	gpio-ranges = &lt;&amp;pio 0 0 41&gt;, &lt;&amp;pio 66 66 35&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts<br/>new file mode 100644<br/>index 000000000000..0e41c07d3a5f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts</a></div><div class='hunk'>@@ -0,0 +1,23 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only OR MIT</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "mt7988a-bananapi-bpi-r4.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "bananapi,bpi-r4-2g5", "bananapi,bpi-r4", "mediatek,mt7988a";</div><div class='add'>+	model = "Banana Pi BPI-R4 (1x SFP+, 1x 2.5GbE)";</div><div class='add'>+	chassis-type = "embedded";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gmac1 {</div><div class='add'>+	phy = &lt;&amp;int_2p5g_phy&gt;;</div><div class='add'>+	phy-mode = "internal";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;int_2p5g_phy {</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2p5gbe_led0_pins&gt;;</div><div class='add'>+	pinctrl-names = "i2p5gbe-led";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-emmc.dtso b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-emmc.dtso<br/>new file mode 100644<br/>index 000000000000..3e320b2f83d5<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-emmc.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-emmc.dtso</a></div><div class='hunk'>@@ -0,0 +1,33 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2021 MediaTek Inc.</div><div class='add'>+ * Author: Frank Wunderlich &lt;frank-w@public-files.de&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "bananapi,bpi-r4", "mediatek,mt7988a";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;{/soc/mmc@11230000} {</div><div class='add'>+	pinctrl-names = "default", "state_uhs";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc0_pins_emmc_51&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;mmc0_pins_emmc_51&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	cap-mmc-highspeed;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	mmc-hs400-1_8v;</div><div class='add'>+	hs400-ds-delay = &lt;0x12814&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_1p8v&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	no-sd;</div><div class='add'>+	no-sdio;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-4e.dts b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-4e.dts<br/>new file mode 100644<br/>index 000000000000..c7ea6e88c4f4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-4e.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-4e.dts</a></div><div class='hunk'>@@ -0,0 +1,16 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2025 MediaTek Inc.</div><div class='add'>+ * Author: Frank Wunderlich &lt;frank-w@public-files.de&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "mt7988a-bananapi-bpi-r4-pro.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Bananapi BPI-R4";</div><div class='add'>+	compatible = "bananapi,bpi-r4-pro-4e",</div><div class='add'>+		     "bananapi,bpi-r4-pro",</div><div class='add'>+		     "mediatek,mt7988a";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-8x.dts b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-8x.dts<br/>new file mode 100644<br/>index 000000000000..c9a0e69e9dd5<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-8x.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-8x.dts</a></div><div class='hunk'>@@ -0,0 +1,16 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2025 MediaTek Inc.</div><div class='add'>+ * Author: Frank Wunderlich &lt;frank-w@public-files.de&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "mt7988a-bananapi-bpi-r4-pro.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Bananapi BPI-R4";</div><div class='add'>+	compatible = "bananapi,bpi-r4-pro-8x",</div><div class='add'>+		     "bananapi,bpi-r4-pro",</div><div class='add'>+		     "mediatek,mt7988a";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-cn15.dtso b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-cn15.dtso<br/>new file mode 100644<br/>index 000000000000..9750916042de<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-cn15.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-cn15.dtso</a></div><div class='hunk'>@@ -0,0 +1,20 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2025 MediaTek Inc.</div><div class='add'>+ * Author: Frank Wunderlich &lt;frank-w@public-files.de&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/* This enables key-b slot CN15 on pcie2(11280000 1L0) on BPI-R4-Pro */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "bananapi,bpi-r4-pro", "mediatek,mt7988a";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;{/soc/pinctrl@1001f000/pcie-2-hog} {</div><div class='add'>+	output-low;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-cn18.dtso b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-cn18.dtso<br/>new file mode 100644<br/>index 000000000000..9830fb0fd97a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-cn18.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-cn18.dtso</a></div><div class='hunk'>@@ -0,0 +1,20 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2025 MediaTek Inc.</div><div class='add'>+ * Author: Frank Wunderlich &lt;frank-w@public-files.de&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/* This enables key-b slot CN18 on pcie3(11290000 1L1) on BPI-R4-Pro */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "bananapi,bpi-r4-pro", "mediatek,mt7988a";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;{/soc/pinctrl@1001f000/pcie-3-hog} {</div><div class='add'>+	output-low;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-emmc.dtso b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-emmc.dtso<br/>new file mode 100644<br/>index 000000000000..5ed2f0a6bd66<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-emmc.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-emmc.dtso</a></div><div class='hunk'>@@ -0,0 +1,33 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2021 MediaTek Inc.</div><div class='add'>+ * Author: Frank Wunderlich &lt;frank-w@public-files.de&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "bananapi,bpi-r4-pro", "mediatek,mt7988a";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;{/soc/mmc@11230000} {</div><div class='add'>+	pinctrl-names = "default", "state_uhs";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc0_pins_emmc_51&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;mmc0_pins_emmc_51&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	cap-mmc-highspeed;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	mmc-hs400-1_8v;</div><div class='add'>+	hs400-ds-delay = &lt;0x12814&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_1p8v&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	no-sd;</div><div class='add'>+	no-sdio;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-sd.dtso b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-sd.dtso<br/>new file mode 100644<br/>index 000000000000..1ec1a9fbd8ba<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-sd.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-sd.dtso</a></div><div class='hunk'>@@ -0,0 +1,31 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2023 MediaTek Inc.</div><div class='add'>+ * Author: Frank Wunderlich &lt;frank-w@public-files.de&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "bananapi,bpi-r4-pro", "mediatek,mt7988a";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;{/soc/mmc@11230000} {</div><div class='add'>+	pinctrl-names = "default", "state_uhs";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc0_pins_sdcard&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;mmc0_pins_sdcard&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;pio 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	max-frequency = &lt;48000000&gt;;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='add'>+	no-mmc;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi<br/>new file mode 100644<br/>index 000000000000..a48132f09411<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi</a></div><div class='hunk'>@@ -0,0 +1,534 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2025 MediaTek Inc.</div><div class='add'>+ * Author: Sam.Shih &lt;sam.shih@mediatek.com&gt;</div><div class='add'>+ * Author: Frank Wunderlich &lt;frank-w@public-files.de&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "mt7988a.dtsi"</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/regulator/richtek,rt5190a-regulator.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;gmac0;</div><div class='add'>+		i2c0 = &amp;i2c0;</div><div class='add'>+		i2c1 = &amp;i2c1;</div><div class='add'>+		i2c2 = &amp;i2c2;</div><div class='add'>+		/* PCA9548 (0-0070) provides 4 i2c channels */</div><div class='add'>+		i2c3 = &amp;imux0;</div><div class='add'>+		i2c4 = &amp;imux1_sfp1;</div><div class='add'>+		i2c5 = &amp;imux2_sfp2;</div><div class='add'>+		i2c6 = &amp;imux3_wifi;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;serial0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fan: pwm-fan {</div><div class='add'>+		compatible = "pwm-fan";</div><div class='add'>+		/* cooling level (0, 1, 2, 3) : (0% duty, 30% duty, 50% duty, 100% duty) */</div><div class='add'>+		cooling-levels = &lt;0 80 128 255&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pwm0_pins&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pwms = &lt;&amp;pwm 0 50000&gt;;</div><div class='add'>+		#cooling-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		button-reset {</div><div class='add'>+			label = "reset";</div><div class='add'>+			gpios = &lt;&amp;pio 13 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_RESTART&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-wps {</div><div class='add'>+			label = "WPS";</div><div class='add'>+			gpios = &lt;&amp;pio 14 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_WPS_BUTTON&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led_red: sys-led-red {</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			gpios = &lt;&amp;pca9555 15 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "on";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led_blue: sys-led-blue {</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			gpios = &lt;&amp;pca9555 14 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "on";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_1p8v: regulator-dvdd1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "DVDD1V8_SOC";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3p3v: regulator-3v3vd {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "3V3VD";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SFP1 cage (LAN) */</div><div class='add'>+	sfp1: sfp1 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;imux1_sfp1&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;pio 70 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;pio 69 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;pio 21 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		maximum-power-milliwatt = &lt;3000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SFP2 cage (WAN) */</div><div class='add'>+	sfp2: sfp2 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;imux2_sfp2&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;pio 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;pio 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;pio 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		maximum-power-milliwatt = &lt;3000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cci {</div><div class='add'>+	proc-supply = &lt;&amp;rt5190_buck3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	proc-supply = &lt;&amp;rt5190_buck3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu1 {</div><div class='add'>+	proc-supply = &lt;&amp;rt5190_buck3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu2 {</div><div class='add'>+	proc-supply = &lt;&amp;rt5190_buck3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu3 {</div><div class='add'>+	proc-supply = &lt;&amp;rt5190_buck3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu_thermal {</div><div class='add'>+	trips {</div><div class='add'>+		cpu_trip_hot: hot {</div><div class='add'>+			temperature = &lt;120000&gt;;</div><div class='add'>+			hysteresis = &lt;2000&gt;;</div><div class='add'>+			type = "hot";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_trip_active_high: active-high {</div><div class='add'>+			temperature = &lt;115000&gt;;</div><div class='add'>+			hysteresis = &lt;2000&gt;;</div><div class='add'>+			type = "active";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_trip_active_med: active-med {</div><div class='add'>+			temperature = &lt;85000&gt;;</div><div class='add'>+			hysteresis = &lt;2000&gt;;</div><div class='add'>+			type = "active";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_trip_active_low: active-low {</div><div class='add'>+			temperature = &lt;40000&gt;;</div><div class='add'>+			hysteresis = &lt;2000&gt;;</div><div class='add'>+			type = "active";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cooling-maps {</div><div class='add'>+		map-cpu-active-high {</div><div class='add'>+			/* active: set fan to cooling level 2 */</div><div class='add'>+			cooling-device = &lt;&amp;fan 3 3&gt;;</div><div class='add'>+			trip = &lt;&amp;cpu_trip_active_high&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		map-cpu-active-med {</div><div class='add'>+			/* active: set fan to cooling level 1 */</div><div class='add'>+			cooling-device = &lt;&amp;fan 2 2&gt;;</div><div class='add'>+			trip = &lt;&amp;cpu_trip_active_med&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		map-cpu-active-low {</div><div class='add'>+			/* active: set fan to cooling level 0 */</div><div class='add'>+			cooling-device = &lt;&amp;fan 1 1&gt;;</div><div class='add'>+			trip = &lt;&amp;cpu_trip_active_low&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eth {</div><div class='add'>+	pinctrl-0 = &lt;&amp;mdio0_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;fan {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm0_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pwms = &lt;&amp;pwm 0 50000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gmac0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gsw_phy0 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;gbe0_led0_pins&gt;;</div><div class='add'>+	pinctrl-names = "gbe-led";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gsw_phy0_led0 {</div><div class='add'>+	color = &lt;LED_COLOR_ID_YELLOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gsw_port0 {</div><div class='add'>+	label = "mgmt";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* R4Pro has only port 0 connected, so disable the others */</div><div class='add'>+&amp;gsw_phy1 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gsw_port1 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gsw_phy2 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gsw_port2 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gsw_phy3 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gsw_port3 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c0_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	rt5190a_64: rt5190a@64 {</div><div class='add'>+		compatible = "richtek,rt5190a";</div><div class='add'>+		reg = &lt;0x64&gt;;</div><div class='add'>+		vin2-supply = &lt;&amp;rt5190_buck1&gt;;</div><div class='add'>+		vin3-supply = &lt;&amp;rt5190_buck1&gt;;</div><div class='add'>+		vin4-supply = &lt;&amp;rt5190_buck1&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			rt5190_buck1: buck1 {</div><div class='add'>+				regulator-name = "rt5190a-buck1";</div><div class='add'>+				regulator-min-microvolt = &lt;5090000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;5090000&gt;;</div><div class='add'>+				regulator-allowed-modes =</div><div class='add'>+				&lt;RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck2 {</div><div class='add'>+				regulator-name = "vcore";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			rt5190_buck3: buck3 {</div><div class='add'>+				regulator-name = "vproc";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			buck4 {</div><div class='add'>+				regulator-name = "rt5190a-buck4";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-allowed-modes =</div><div class='add'>+				&lt;RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ldo {</div><div class='add'>+				regulator-name = "rt5190a-ldo";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c1_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c2_1_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pca9545: i2c-mux@70 {</div><div class='add'>+		compatible = "nxp,pca9545";</div><div class='add'>+		reg = &lt;0x70&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		imux0: i2c@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			pca9555: i2c-gpio-expander@20 {</div><div class='add'>+				compatible = "nxp,pca9555";</div><div class='add'>+				reg = &lt;0x20&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			rtc@51 {</div><div class='add'>+				compatible = "nxp,pcf8563";</div><div class='add'>+				reg = &lt;0x51&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			eeprom@57 {</div><div class='add'>+				compatible = "atmel,24c02";</div><div class='add'>+				reg = &lt;0x57&gt;;</div><div class='add'>+				address-width = &lt;8&gt;;</div><div class='add'>+				pagesize = &lt;8&gt;;</div><div class='add'>+				size = &lt;256&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		imux1_sfp1: i2c@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		imux2_sfp2: i2c@2 {</div><div class='add'>+			reg = &lt;2&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		imux3_wifi: i2c@3 {</div><div class='add'>+			reg = &lt;3&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* mPCIe SIM2 (11300000) */</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* mPCIe (11310000 near leds) SIM3 */</div><div class='add'>+&amp;pcie1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* M.2 (11280000) 1L0 key-m SSD1 CN13 / key-b SIM1 CN15 */</div><div class='add'>+&amp;pcie2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* M.2 (11290000) 1L1 key-m SSD2 CN14 / key-b SIM2 CN18 */</div><div class='add'>+&amp;pcie3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	gbe0_led0_pins: gbe0-led0-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "led";</div><div class='add'>+			groups = "gbe0_led0";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c0_pins: i2c0-g0-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "i2c";</div><div class='add'>+			groups = "i2c0_1";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c1_pins: i2c1-g0-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "i2c";</div><div class='add'>+			groups = "i2c1_0";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c2_1_pins: i2c2-g1-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "i2c";</div><div class='add'>+			groups = "i2c2_1";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mdio0_pins: mdio0-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "eth";</div><div class='add'>+			groups = "mdc_mdio0";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		conf {</div><div class='add'>+			pins = "SMI_0_MDC", "SMI_0_MDIO";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc0_pins_emmc_51: mmc0-emmc-51-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "flash";</div><div class='add'>+			groups = "emmc_51";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc0_pins_sdcard: mmc0-sdcard-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "flash";</div><div class='add'>+			groups = "sdcard";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* 1L0 0=key-b (CN15), 1=key-m (CN13) */</div><div class='add'>+	pcie-2-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;79 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		output-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* 1L1 0=key-b (CN18), 1=key-m (CN14) */</div><div class='add'>+	pcie-3-hog {</div><div class='add'>+		gpio-hog;</div><div class='add'>+		gpios = &lt;63 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		output-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pwm0_pins: pwm0-pins {</div><div class='add'>+		mux {</div><div class='add'>+			groups = "pwm0";</div><div class='add'>+			function = "pwm";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi0_flash_pins: spi0-flash-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "spi";</div><div class='add'>+			groups = "spi0", "spi0_wp_hold";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;serial0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi0 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;spi0_flash_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	spi_nand: nand@0 {</div><div class='add'>+		compatible = "spi-nand";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;52000000&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;4&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi_nand {</div><div class='add'>+	partitions {</div><div class='add'>+		compatible = "fixed-partitions";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		partition@0 {</div><div class='add'>+			reg = &lt;0x0 0x200000&gt;;</div><div class='add'>+			label = "bl2";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		partition@200000 {</div><div class='add'>+			compatible = "linux,ubi";</div><div class='add'>+			reg = &lt;0x200000 0xfe00000&gt;;</div><div class='add'>+			label = "ubi";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* back USB */</div><div class='add'>+&amp;ssusb0 {</div><div class='add'>+	/* Use U2P only instead of both U3P/U2P due to U3P serdes shared with pcie2 */</div><div class='add'>+	phys = &lt;&amp;xphyu2port0 PHY_TYPE_USB2&gt;;</div><div class='add'>+	mediatek,u3p-dis-msk = &lt;1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* front USB */</div><div class='add'>+&amp;ssusb1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;switch {</div><div class='add'>+	dsa,member = &lt;1 0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tphy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;watchdog {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xsphy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-sd.dtso b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-sd.dtso<br/>new file mode 100644<br/>index 000000000000..663c6345dd31<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-sd.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-sd.dtso</a></div><div class='hunk'>@@ -0,0 +1,31 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2023 MediaTek Inc.</div><div class='add'>+ * Author: Frank Wunderlich &lt;frank-w@public-files.de&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "bananapi,bpi-r4", "mediatek,mt7988a";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;{/soc/mmc@11230000} {</div><div class='add'>+	pinctrl-names = "default", "state_uhs";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc0_pins_sdcard&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;mmc0_pins_sdcard&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;pio 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	max-frequency = &lt;52000000&gt;;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;reg_3p3v&gt;;</div><div class='add'>+	no-mmc;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts<br/>new file mode 100644<br/>index 000000000000..4b3796ba82e3<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts</a></div><div class='hunk'>@@ -0,0 +1,38 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only OR MIT</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "mt7988a-bananapi-bpi-r4.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "bananapi,bpi-r4", "mediatek,mt7988a";</div><div class='add'>+	model = "Banana Pi BPI-R4 (2x SFP+)";</div><div class='add'>+	chassis-type = "embedded";</div><div class='add'>+</div><div class='add'>+	/* SFP2 cage (LAN) */</div><div class='add'>+	sfp2: sfp2 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;i2c_sfp2&gt;;</div><div class='add'>+		maximum-power-milliwatt = &lt;3000&gt;;</div><div class='add'>+</div><div class='add'>+		los-gpios = &lt;&amp;pio 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;pio 83 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		rate-select0-gpios = &lt;&amp;pio 3 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;pio 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;pio 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gmac1 {</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	phy-mode = "usxgmii";</div><div class='add'>+	sfp = &lt;&amp;sfp2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pca9545 {</div><div class='add'>+	i2c_sfp2: i2c@2 {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		reg = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi<br/>new file mode 100644<br/>index 000000000000..0ff69dae45d3<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi</a></div><div class='hunk'>@@ -0,0 +1,471 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only OR MIT</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/regulator/richtek,rt5190a-regulator.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+#include "mt7988a.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;gmac0;</div><div class='add'>+		ethernet1 = &amp;gmac1;</div><div class='add'>+		ethernet2 = &amp;gmac2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fan: pwm-fan {</div><div class='add'>+		compatible = "pwm-fan";</div><div class='add'>+		/* cooling level (0, 1, 2, 3) : (0% duty, 30% duty, 50% duty, 100% duty) */</div><div class='add'>+		cooling-levels = &lt;0 80 128 255&gt;;</div><div class='add'>+		#cooling-cells = &lt;2&gt;;</div><div class='add'>+		pwms = &lt;&amp;pwm 0 50000&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led_green: led-green {</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			gpios = &lt;&amp;pio 79 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "on";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led_blue: led-blue {</div><div class='add'>+			function = LED_FUNCTION_WPS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			gpios = &lt;&amp;pio 63 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	reg_1p8v: regulator-1p8v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "fixed-1.8V";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_3p3v: regulator-3p3v {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "fixed-3.3V";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SFP1 cage (WAN) */</div><div class='add'>+	sfp1: sfp1 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;i2c_sfp1&gt;;</div><div class='add'>+		maximum-power-milliwatt = &lt;3000&gt;;</div><div class='add'>+</div><div class='add'>+		los-gpios = &lt;&amp;pio 54 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;pio 82 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		rate-select0-gpios = &lt;&amp;pio 21 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;pio 70 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;pio 69 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cci {</div><div class='add'>+	proc-supply = &lt;&amp;rt5190_buck3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	proc-supply = &lt;&amp;rt5190_buck3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu1 {</div><div class='add'>+	proc-supply = &lt;&amp;rt5190_buck3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu2 {</div><div class='add'>+	proc-supply = &lt;&amp;rt5190_buck3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu3 {</div><div class='add'>+	proc-supply = &lt;&amp;rt5190_buck3&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu_thermal {</div><div class='add'>+	trips {</div><div class='add'>+		cpu_trip_hot: hot {</div><div class='add'>+			temperature = &lt;120000&gt;;</div><div class='add'>+			hysteresis = &lt;2000&gt;;</div><div class='add'>+			type = "hot";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_trip_active_high: active-high {</div><div class='add'>+			temperature = &lt;115000&gt;;</div><div class='add'>+			hysteresis = &lt;2000&gt;;</div><div class='add'>+			type = "active";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_trip_active_med: active-med {</div><div class='add'>+			temperature = &lt;85000&gt;;</div><div class='add'>+			hysteresis = &lt;2000&gt;;</div><div class='add'>+			type = "active";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_trip_active_low: active-low {</div><div class='add'>+			temperature = &lt;40000&gt;;</div><div class='add'>+			hysteresis = &lt;2000&gt;;</div><div class='add'>+			type = "active";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cooling-maps {</div><div class='add'>+		map-cpu-active-high {</div><div class='add'>+			/* active: set fan to cooling level 2 */</div><div class='add'>+			cooling-device = &lt;&amp;fan 3 3&gt;;</div><div class='add'>+			trip = &lt;&amp;cpu_trip_active_high&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		map-cpu-active-med {</div><div class='add'>+			/* active: set fan to cooling level 1 */</div><div class='add'>+			cooling-device = &lt;&amp;fan 2 2&gt;;</div><div class='add'>+			trip = &lt;&amp;cpu_trip_active_med&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		map-cpu-active-low {</div><div class='add'>+			/* active: set fan to cooling level 0 */</div><div class='add'>+			cooling-device = &lt;&amp;fan 1 1&gt;;</div><div class='add'>+			trip = &lt;&amp;cpu_trip_active_low&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gmac2 {</div><div class='add'>+	managed = "in-band-status";</div><div class='add'>+	phy-mode = "usxgmii";</div><div class='add'>+	sfp = &lt;&amp;sfp1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gsw_phy0 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;gbe0_led0_pins&gt;;</div><div class='add'>+	pinctrl-names = "gbe-led";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gsw_phy0_led0 {</div><div class='add'>+	function = LED_FUNCTION_WAN;</div><div class='add'>+	color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gsw_port0 {</div><div class='add'>+	label = "wan";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gsw_phy1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;gbe1_led0_pins&gt;;</div><div class='add'>+	pinctrl-names = "gbe-led";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gsw_phy1_led0 {</div><div class='add'>+	function = LED_FUNCTION_LAN;</div><div class='add'>+	color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gsw_port1 {</div><div class='add'>+	label = "lan1";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gsw_phy2 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;gbe2_led0_pins&gt;;</div><div class='add'>+	pinctrl-names = "gbe-led";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gsw_phy2_led0 {</div><div class='add'>+	function = LED_FUNCTION_LAN;</div><div class='add'>+	color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gsw_port2 {</div><div class='add'>+	label = "lan2";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gsw_phy3 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;gbe3_led0_pins&gt;;</div><div class='add'>+	pinctrl-names = "gbe-led";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gsw_phy3_led0 {</div><div class='add'>+	function = LED_FUNCTION_LAN;</div><div class='add'>+	color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gsw_port3 {</div><div class='add'>+	label = "lan3";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c0_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	rt5190a_64: rt5190a@64 {</div><div class='add'>+		compatible = "richtek,rt5190a";</div><div class='add'>+		reg = &lt;0x64&gt;;</div><div class='add'>+		vin2-supply = &lt;&amp;rt5190_buck1&gt;;</div><div class='add'>+		vin3-supply = &lt;&amp;rt5190_buck1&gt;;</div><div class='add'>+		vin4-supply = &lt;&amp;rt5190_buck1&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			rt5190_buck1: buck1 {</div><div class='add'>+				regulator-name = "rt5190a-buck1";</div><div class='add'>+				regulator-min-microvolt = &lt;5090000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;5090000&gt;;</div><div class='add'>+				regulator-allowed-modes =</div><div class='add'>+				&lt;RT5190A_OPMODE_AUTO&gt;, &lt;RT5190A_OPMODE_FPWM&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+			buck2 {</div><div class='add'>+				regulator-name = "vcore";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+			rt5190_buck3: buck3 {</div><div class='add'>+				regulator-name = "vproc";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1400000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+			};</div><div class='add'>+			buck4 {</div><div class='add'>+				regulator-name = "rt5190a-buck4";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-allowed-modes =</div><div class='add'>+				&lt;RT5190A_OPMODE_AUTO&gt;, &lt;RT5190A_OPMODE_FPWM&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+			ldo {</div><div class='add'>+				regulator-name = "rt5190a-ldo";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-boot-on;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c2_1_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pca9545: i2c-mux@70 {</div><div class='add'>+		compatible = "nxp,pca9545";</div><div class='add'>+		reg = &lt;0x70&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pio 5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		i2c@0 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			pcf8563: rtc@51 {</div><div class='add'>+				compatible = "nxp,pcf8563";</div><div class='add'>+				reg = &lt;0x51&gt;;</div><div class='add'>+				#clock-cells = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			eeprom@57 {</div><div class='add'>+				compatible = "atmel,24c02";</div><div class='add'>+				reg = &lt;0x57&gt;;</div><div class='add'>+				size = &lt;256&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c_sfp1: i2c@1 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* mPCIe SIM2 */</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* mPCIe SIM3 */</div><div class='add'>+&amp;pcie1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* M.2 key-B SIM1 */</div><div class='add'>+&amp;pcie2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* M.2 key-M SSD */</div><div class='add'>+&amp;pcie3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	i2c0_pins: i2c0-g0-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "i2c";</div><div class='add'>+			groups = "i2c0_1";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c1_pins: i2c1-g0-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "i2c";</div><div class='add'>+			groups = "i2c1_0";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c2_1_pins: i2c2-g1-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "i2c";</div><div class='add'>+			groups = "i2c2_1";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gbe0_led0_pins: gbe0-led0-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "led";</div><div class='add'>+			groups = "gbe0_led0";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gbe1_led0_pins: gbe1-led0-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "led";</div><div class='add'>+			groups = "gbe1_led0";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gbe2_led0_pins: gbe2-led0-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "led";</div><div class='add'>+			groups = "gbe2_led0";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gbe3_led0_pins: gbe3-led0-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "led";</div><div class='add'>+			groups = "gbe3_led0";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2p5gbe_led0_pins: 2p5gbe-led0-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "led";</div><div class='add'>+			groups = "2p5gbe_led0";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc0_pins_emmc_45: mmc0-emmc-45-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "flash";</div><div class='add'>+			groups = "emmc_45";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc0_pins_emmc_51: mmc0-emmc-51-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "flash";</div><div class='add'>+			groups = "emmc_51";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc0_pins_sdcard: mmc0-sdcard-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "flash";</div><div class='add'>+			groups = "sdcard";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi0_flash_pins: spi0-flash-pins {</div><div class='add'>+		mux {</div><div class='add'>+			function = "spi";</div><div class='add'>+			groups = "spi0", "spi0_wp_hold";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;serial0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;spi0_flash_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	spi_nand: flash@0 {</div><div class='add'>+		compatible = "spi-nand";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;52000000&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;4&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi_nand {</div><div class='add'>+	partitions {</div><div class='add'>+		compatible = "fixed-partitions";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		partition@0 {</div><div class='add'>+			label = "bl2";</div><div class='add'>+			reg = &lt;0x0 0x200000&gt;;</div><div class='add'>+			read-only;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ssusb1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tphy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;watchdog {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xsphy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi<br/>new file mode 100644<br/>index 000000000000..bec590d26659<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt7988a.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt7988a.dtsi</a></div><div class='hunk'>@@ -0,0 +1,1039 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only OR MIT</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/mediatek,mt7988-clk.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/phy/phy.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/mt65xx.h&gt;</div><div class='add'>+#include &lt;dt-bindings/reset/mediatek,mt7988-resets.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "mediatek,mt7988a";</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	cci: cci {</div><div class='add'>+		compatible = "mediatek,mt7988-cci", "mediatek,mt8183-cci";</div><div class='add'>+		clocks = &lt;&amp;mcusys CLK_MCU_BUS_DIV_SEL&gt;,</div><div class='add'>+			 &lt;&amp;topckgen CLK_TOP_XTAL&gt;;</div><div class='add'>+		clock-names = "cci", "intermediate";</div><div class='add'>+		operating-points-v2 = &lt;&amp;cci_opp&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cci_opp: opp-table-cci {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+		opp-shared;</div><div class='add'>+		opp-480000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;480000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;850000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-660000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;660000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;850000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-900000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;900000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;850000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-1080000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1080000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;900000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			compatible = "arm,cortex-a73";</div><div class='add'>+			reg = &lt;0x0&gt;;</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clocks = &lt;&amp;mcusys CLK_MCU_ARM_DIV_SEL&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_XTAL&gt;;</div><div class='add'>+			clock-names = "cpu", "intermediate";</div><div class='add'>+			operating-points-v2 = &lt;&amp;cluster0_opp&gt;;</div><div class='add'>+			mediatek,cci = &lt;&amp;cci&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@1 {</div><div class='add'>+			compatible = "arm,cortex-a73";</div><div class='add'>+			reg = &lt;0x1&gt;;</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clocks = &lt;&amp;mcusys CLK_MCU_ARM_DIV_SEL&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_XTAL&gt;;</div><div class='add'>+			clock-names = "cpu", "intermediate";</div><div class='add'>+			operating-points-v2 = &lt;&amp;cluster0_opp&gt;;</div><div class='add'>+			mediatek,cci = &lt;&amp;cci&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@2 {</div><div class='add'>+			compatible = "arm,cortex-a73";</div><div class='add'>+			reg = &lt;0x2&gt;;</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clocks = &lt;&amp;mcusys CLK_MCU_ARM_DIV_SEL&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_XTAL&gt;;</div><div class='add'>+			clock-names = "cpu", "intermediate";</div><div class='add'>+			operating-points-v2 = &lt;&amp;cluster0_opp&gt;;</div><div class='add'>+			mediatek,cci = &lt;&amp;cci&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@3 {</div><div class='add'>+			compatible = "arm,cortex-a73";</div><div class='add'>+			reg = &lt;0x3&gt;;</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clocks = &lt;&amp;mcusys CLK_MCU_ARM_DIV_SEL&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_XTAL&gt;;</div><div class='add'>+			clock-names = "cpu", "intermediate";</div><div class='add'>+			operating-points-v2 = &lt;&amp;cluster0_opp&gt;;</div><div class='add'>+			mediatek,cci = &lt;&amp;cci&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cluster0_opp: opp-table-0 {</div><div class='add'>+			compatible = "operating-points-v2";</div><div class='add'>+			opp-shared;</div><div class='add'>+</div><div class='add'>+			opp-800000000 {</div><div class='add'>+				opp-hz = /bits/ 64 &lt;800000000&gt;;</div><div class='add'>+				opp-microvolt = &lt;850000&gt;;</div><div class='add'>+			};</div><div class='add'>+			opp-1100000000 {</div><div class='add'>+				opp-hz = /bits/ 64 &lt;1100000000&gt;;</div><div class='add'>+				opp-microvolt = &lt;850000&gt;;</div><div class='add'>+			};</div><div class='add'>+			opp-1500000000 {</div><div class='add'>+				opp-hz = /bits/ 64 &lt;1500000000&gt;;</div><div class='add'>+				opp-microvolt = &lt;850000&gt;;</div><div class='add'>+			};</div><div class='add'>+			opp-1800000000 {</div><div class='add'>+				opp-hz = /bits/ 64 &lt;1800000000&gt;;</div><div class='add'>+				opp-microvolt = &lt;900000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	oscillator-40m {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		clock-frequency = &lt;40000000&gt;;</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-output-names = "clkxtal";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu {</div><div class='add'>+		compatible = "arm,cortex-a73-pmu";</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-0.2";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		/* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */</div><div class='add'>+		secmon@43000000 {</div><div class='add'>+			reg = &lt;0 0x43000000 0 0x50000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		ranges;</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@c000000 {</div><div class='add'>+			compatible = "arm,gic-v3";</div><div class='add'>+			reg = &lt;0 0x0c000000 0 0x40000&gt;,  /* GICD */</div><div class='add'>+			      &lt;0 0x0c080000 0 0x200000&gt;, /* GICR */</div><div class='add'>+			      &lt;0 0x0c400000 0 0x2000&gt;,   /* GICC */</div><div class='add'>+			      &lt;0 0x0c410000 0 0x1000&gt;,   /* GICH */</div><div class='add'>+			      &lt;0 0x0c420000 0 0x2000&gt;;   /* GICV */</div><div class='add'>+			interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		infracfg: clock-controller@10001000 {</div><div class='add'>+			compatible = "mediatek,mt7988-infracfg", "syscon";</div><div class='add'>+			reg = &lt;0 0x10001000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		topckgen: clock-controller@1001b000 {</div><div class='add'>+			compatible = "mediatek,mt7988-topckgen", "syscon";</div><div class='add'>+			reg = &lt;0 0x1001b000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		watchdog: watchdog@1001c000 {</div><div class='add'>+			compatible = "mediatek,mt7988-wdt";</div><div class='add'>+			reg = &lt;0 0x1001c000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		apmixedsys: clock-controller@1001e000 {</div><div class='add'>+			compatible = "mediatek,mt7988-apmixedsys";</div><div class='add'>+			reg = &lt;0 0x1001e000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pio: pinctrl@1001f000 {</div><div class='add'>+			compatible = "mediatek,mt7988-pinctrl";</div><div class='add'>+			reg = &lt;0 0x1001f000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11c10000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11d00000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11d20000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11e00000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11f00000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x1000b000 0 0x1000&gt;;</div><div class='add'>+			reg-names = "gpio", "iocfg_tr",</div><div class='add'>+				    "iocfg_br", "iocfg_rb",</div><div class='add'>+				    "iocfg_lb", "iocfg_tl", "eint";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;pio 0 0 84&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			interrupts = &lt;GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			pcie0_pins: pcie0-pins {</div><div class='add'>+				mux {</div><div class='add'>+					function = "pcie";</div><div class='add'>+					groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0",</div><div class='add'>+						 "pcie_wake_n0_0";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pcie1_pins: pcie1-pins {</div><div class='add'>+				mux {</div><div class='add'>+					function = "pcie";</div><div class='add'>+					groups = "pcie_2l_1_pereset", "pcie_clk_req_n1",</div><div class='add'>+						 "pcie_wake_n1_0";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pcie2_pins: pcie2-pins {</div><div class='add'>+				mux {</div><div class='add'>+					function = "pcie";</div><div class='add'>+					groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0",</div><div class='add'>+						 "pcie_wake_n2_0";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pcie3_pins: pcie3-pins {</div><div class='add'>+				mux {</div><div class='add'>+					function = "pcie";</div><div class='add'>+					groups = "pcie_1l_1_pereset", "pcie_clk_req_n3",</div><div class='add'>+						 "pcie_wake_n3_0";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi1_pins: spi1-pins {</div><div class='add'>+				mux {</div><div class='add'>+					function = "spi";</div><div class='add'>+					groups = "spi1";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart0_pins: uart0-pins {</div><div class='add'>+				mux {</div><div class='add'>+					function = "uart";</div><div class='add'>+					groups =  "uart0";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pwm: pwm@10048000 {</div><div class='add'>+			compatible = "mediatek,mt7988-pwm";</div><div class='add'>+			reg = &lt;0 0x10048000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_66M_PWM_BCK&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_66M_PWM_HCK&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_66M_PWM_CK1&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_66M_PWM_CK2&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_66M_PWM_CK3&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_66M_PWM_CK4&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_66M_PWM_CK5&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_66M_PWM_CK6&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_66M_PWM_CK7&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_66M_PWM_CK8&gt;;</div><div class='add'>+			clock-names = "top", "main", "pwm1", "pwm2", "pwm3",</div><div class='add'>+				      "pwm4", "pwm5", "pwm6", "pwm7", "pwm8";</div><div class='add'>+			#pwm-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mcusys: mcusys@100e0000 {</div><div class='add'>+			compatible = "mediatek,mt7988-mcusys", "syscon";</div><div class='add'>+			reg = &lt;0 0x100e0000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		serial0: serial@11000000 {</div><div class='add'>+			compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart";</div><div class='add'>+			reg = &lt;0 0x11000000 0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "uart", "wakeup";</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_UART_SEL&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_52M_UART0_CK&gt;;</div><div class='add'>+			clock-names = "baud", "bus";</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;uart0_pins&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		serial@11000100 {</div><div class='add'>+			compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart";</div><div class='add'>+			reg = &lt;0 0x11000100 0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "uart", "wakeup";</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_UART_SEL&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_52M_UART1_CK&gt;;</div><div class='add'>+			clock-names = "baud", "bus";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		serial@11000200 {</div><div class='add'>+			compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart";</div><div class='add'>+			reg = &lt;0 0x11000200 0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "uart", "wakeup";</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_UART_SEL&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_52M_UART2_CK&gt;;</div><div class='add'>+			clock-names = "baud", "bus";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c0: i2c@11003000 {</div><div class='add'>+			compatible = "mediatek,mt7981-i2c";</div><div class='add'>+			reg = &lt;0 0x11003000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x10217080 0 0x80&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clock-div = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_I2C_BCK&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_66M_AP_DMA_BCK&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c1: i2c@11004000 {</div><div class='add'>+			compatible = "mediatek,mt7981-i2c";</div><div class='add'>+			reg = &lt;0 0x11004000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x10217100 0 0x80&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clock-div = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_I2C_BCK&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_66M_AP_DMA_BCK&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c2: i2c@11005000 {</div><div class='add'>+			compatible = "mediatek,mt7981-i2c";</div><div class='add'>+			reg = &lt;0 0x11005000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x10217180 0 0x80&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clock-div = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_I2C_BCK&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_66M_AP_DMA_BCK&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi0: spi@11007000 {</div><div class='add'>+			compatible = "mediatek,mt7988-spi-quad", "mediatek,spi-ipm";</div><div class='add'>+			reg = &lt;0 0x11007000 0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_MPLL_D2&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SPI_SEL&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_104M_SPI0&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_66M_SPI0_HCK&gt;;</div><div class='add'>+			clock-names = "parent-clk", "sel-clk", "spi-clk",</div><div class='add'>+				      "hclk";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi1: spi@11008000 {</div><div class='add'>+			compatible = "mediatek,mt7988-spi-single", "mediatek,spi-ipm";</div><div class='add'>+			reg = &lt;0 0x11008000 0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_MPLL_D2&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SPIM_MST_SEL&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_104M_SPI1&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_66M_SPI1_HCK&gt;;</div><div class='add'>+			clock-names = "parent-clk", "sel-clk", "spi-clk",</div><div class='add'>+				      "hclk";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;spi1_pins&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi2: spi@11009000 {</div><div class='add'>+			compatible = "mediatek,mt7988-spi-quad", "mediatek,spi-ipm";</div><div class='add'>+			reg = &lt;0 0x11009000 0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_MPLL_D2&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SPI_SEL&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_104M_SPI2_BCK&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_66M_SPI2_HCK&gt;;</div><div class='add'>+			clock-names = "parent-clk", "sel-clk", "spi-clk",</div><div class='add'>+				      "hclk";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		lvts: lvts@1100a000 {</div><div class='add'>+			compatible = "mediatek,mt7988-lvts-ap";</div><div class='add'>+			#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+			reg = &lt;0 0x1100a000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_26M_THERM_SYSTEM&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			resets = &lt;&amp;infracfg MT7988_INFRA_RST1_THERM_CTRL_SWRST&gt;;</div><div class='add'>+			nvmem-cells = &lt;&amp;lvts_calibration&gt;;</div><div class='add'>+			nvmem-cell-names = "lvts-calib-data-1";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ssusb0: usb@11190000 {</div><div class='add'>+			compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci";</div><div class='add'>+			reg = &lt;0 0x11190000 0 0x2e00&gt;,</div><div class='add'>+			      &lt;0 0x11193e00 0 0x0100&gt;;</div><div class='add'>+			reg-names = "mac", "ippc";</div><div class='add'>+			interrupts = &lt;GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_USB_SYS&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_USB_REF&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_66M_USB_HCK&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_133M_USB_HCK&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_USB_XHCI&gt;;</div><div class='add'>+			clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";</div><div class='add'>+			phys = &lt;&amp;xphyu2port0 PHY_TYPE_USB2&gt;,</div><div class='add'>+			       &lt;&amp;xphyu3port0 PHY_TYPE_USB3&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ssusb1: usb@11200000 {</div><div class='add'>+			compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci";</div><div class='add'>+			reg = &lt;0 0x11200000 0 0x2e00&gt;,</div><div class='add'>+			      &lt;0 0x11203e00 0 0x0100&gt;;</div><div class='add'>+			reg-names = "mac", "ippc";</div><div class='add'>+			interrupts = &lt;GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_USB_SYS_CK_P1&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_USB_CK_P1&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_66M_USB_HCK_CK_P1&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_133M_USB_HCK_CK_P1&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_USB_XHCI_CK_P1&gt;;</div><div class='add'>+			clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";</div><div class='add'>+			phys = &lt;&amp;tphyu2port0 PHY_TYPE_USB2&gt;,</div><div class='add'>+			       &lt;&amp;tphyu3port0 PHY_TYPE_USB3&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmc0: mmc@11230000 {</div><div class='add'>+			compatible = "mediatek,mt7988-mmc";</div><div class='add'>+			reg = &lt;0 0x11230000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11D60000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_MSDC400&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_MSDC2_HCK&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_66M_MSDC_0_HCK&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_133M_MSDC_0_HCK&gt;;</div><div class='add'>+			assigned-clocks = &lt;&amp;topckgen CLK_TOP_EMMC_250M_SEL&gt;,</div><div class='add'>+					  &lt;&amp;topckgen CLK_TOP_EMMC_400M_SEL&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_NET1PLL_D5_D2&gt;,</div><div class='add'>+						 &lt;&amp;apmixedsys CLK_APMIXED_MSDCPLL&gt;;</div><div class='add'>+			clock-names = "source", "hclk", "axi_cg", "ahb_cg";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie2: pcie@11280000 {</div><div class='add'>+			compatible = "mediatek,mt7986-pcie",</div><div class='add'>+				     "mediatek,mt8192-pcie";</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			reg = &lt;0 0x11280000 0 0x2000&gt;;</div><div class='add'>+			reg-names = "pcie-mac";</div><div class='add'>+			linux,pci-domain = &lt;3&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			bus-range = &lt;0x00 0xff&gt;;</div><div class='add'>+			ranges = &lt;0x81000000 0x00 0x20000000 0x00</div><div class='add'>+				  0x20000000 0x00 0x00200000&gt;,</div><div class='add'>+				 &lt;0x82000000 0x00 0x20200000 0x00</div><div class='add'>+				  0x20200000 0x00 0x07e00000&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_PCIE_PIPE_P2&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_PCIE_GFMUX_TL_P2&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_133M_PCIE_CK_P2&gt;;</div><div class='add'>+			clock-names = "pl_250m", "tl_26m", "peri_26m",</div><div class='add'>+				      "top_133m";</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;pcie2_pins&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;xphyu3port0 PHY_TYPE_PCIE&gt;;</div><div class='add'>+			phy-names = "pcie-phy";</div><div class='add'>+</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0x7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;pcie_intc2 0&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;pcie_intc2 1&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;pcie_intc2 2&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;pcie_intc2 3&gt;;</div><div class='add'>+			pcie_intc2: interrupt-controller {</div><div class='add'>+				#address-cells = &lt;0&gt;;</div><div class='add'>+				#interrupt-cells = &lt;1&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie3: pcie@11290000 {</div><div class='add'>+			compatible = "mediatek,mt7986-pcie",</div><div class='add'>+				     "mediatek,mt8192-pcie";</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			reg = &lt;0 0x11290000 0 0x2000&gt;;</div><div class='add'>+			reg-names = "pcie-mac";</div><div class='add'>+			linux,pci-domain = &lt;2&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			bus-range = &lt;0x00 0xff&gt;;</div><div class='add'>+			ranges = &lt;0x81000000 0x00 0x28000000 0x00</div><div class='add'>+				  0x28000000 0x00 0x00200000&gt;,</div><div class='add'>+				 &lt;0x82000000 0x00 0x28200000 0x00</div><div class='add'>+				  0x28200000 0x00 0x07e00000&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_PCIE_PIPE_P3&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_PCIE_GFMUX_TL_P3&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_133M_PCIE_CK_P3&gt;;</div><div class='add'>+			clock-names = "pl_250m", "tl_26m", "peri_26m",</div><div class='add'>+				      "top_133m";</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;pcie3_pins&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0x7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;pcie_intc3 0&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;pcie_intc3 1&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;pcie_intc3 2&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;pcie_intc3 3&gt;;</div><div class='add'>+			pcie_intc3: interrupt-controller {</div><div class='add'>+				#address-cells = &lt;0&gt;;</div><div class='add'>+				#interrupt-cells = &lt;1&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie0: pcie@11300000 {</div><div class='add'>+			compatible = "mediatek,mt7986-pcie",</div><div class='add'>+				     "mediatek,mt8192-pcie";</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			reg = &lt;0 0x11300000 0 0x2000&gt;;</div><div class='add'>+			reg-names = "pcie-mac";</div><div class='add'>+			linux,pci-domain = &lt;0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			bus-range = &lt;0x00 0xff&gt;;</div><div class='add'>+			ranges = &lt;0x81000000 0x00 0x30000000 0x00</div><div class='add'>+				  0x30000000 0x00 0x00200000&gt;,</div><div class='add'>+				 &lt;0x82000000 0x00 0x30200000 0x00</div><div class='add'>+				  0x30200000 0x00 0x07e00000&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_PCIE_PIPE_P0&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_PCIE_GFMUX_TL_P0&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_133M_PCIE_CK_P0&gt;;</div><div class='add'>+			clock-names = "pl_250m", "tl_26m", "peri_26m",</div><div class='add'>+				      "top_133m";</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;pcie0_pins&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0x7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;pcie_intc0 0&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;pcie_intc0 1&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;pcie_intc0 2&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;pcie_intc0 3&gt;;</div><div class='add'>+			pcie_intc0: interrupt-controller {</div><div class='add'>+				#address-cells = &lt;0&gt;;</div><div class='add'>+				#interrupt-cells = &lt;1&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie1: pcie@11310000 {</div><div class='add'>+			compatible = "mediatek,mt7986-pcie",</div><div class='add'>+				     "mediatek,mt8192-pcie";</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			reg = &lt;0 0x11310000 0 0x2000&gt;;</div><div class='add'>+			reg-names = "pcie-mac";</div><div class='add'>+			linux,pci-domain = &lt;1&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			bus-range = &lt;0x00 0xff&gt;;</div><div class='add'>+			ranges = &lt;0x81000000 0x00 0x38000000 0x00</div><div class='add'>+				  0x38000000 0x00 0x00200000&gt;,</div><div class='add'>+				 &lt;0x82000000 0x00 0x38200000 0x00</div><div class='add'>+				  0x38200000 0x00 0x07e00000&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_PCIE_PIPE_P1&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_PCIE_GFMUX_TL_P1&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_133M_PCIE_CK_P1&gt;;</div><div class='add'>+			clock-names = "pl_250m", "tl_26m", "peri_26m",</div><div class='add'>+				      "top_133m";</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;pcie1_pins&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0x7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;pcie_intc1 0&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;pcie_intc1 1&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;pcie_intc1 2&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;pcie_intc1 3&gt;;</div><div class='add'>+			pcie_intc1: interrupt-controller {</div><div class='add'>+				#address-cells = &lt;0&gt;;</div><div class='add'>+				#interrupt-cells = &lt;1&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tphy: t-phy@11c50000 {</div><div class='add'>+			compatible = "mediatek,mt7986-tphy",</div><div class='add'>+				     "mediatek,generic-tphy-v2";</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			tphyu2port0: usb-phy@11c50000 {</div><div class='add'>+				reg = &lt;0 0x11c50000 0 0x700&gt;;</div><div class='add'>+				clocks = &lt;&amp;infracfg CLK_INFRA_USB_UTMI_CK_P1&gt;;</div><div class='add'>+				clock-names = "ref";</div><div class='add'>+				#phy-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tphyu3port0: usb-phy@11c50700 {</div><div class='add'>+				reg = &lt;0 0x11c50700 0 0x900&gt;;</div><div class='add'>+				clocks = &lt;&amp;infracfg CLK_INFRA_USB_PIPE_CK_P1&gt;;</div><div class='add'>+				clock-names = "ref";</div><div class='add'>+				#phy-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+		topmisc: system-controller@11d10084 {</div><div class='add'>+			compatible = "mediatek,mt7988-topmisc",</div><div class='add'>+				     "syscon";</div><div class='add'>+			reg = &lt;0 0x11d10084 0 0xff80&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		xsphy: xs-phy@11e10000 {</div><div class='add'>+			compatible = "mediatek,mt7988-xsphy",</div><div class='add'>+				     "mediatek,xsphy";</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			xphyu2port0: usb-phy@11e10000 {</div><div class='add'>+				reg = &lt;0 0x11e10000 0 0x400&gt;;</div><div class='add'>+				clocks = &lt;&amp;infracfg CLK_INFRA_USB_UTMI&gt;;</div><div class='add'>+				clock-names = "ref";</div><div class='add'>+				#phy-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			xphyu3port0: usb-phy@11e13000 {</div><div class='add'>+				reg = &lt;0 0x11e13400 0 0x500&gt;;</div><div class='add'>+				clocks = &lt;&amp;infracfg CLK_INFRA_USB_PIPE&gt;;</div><div class='add'>+				clock-names = "ref";</div><div class='add'>+				#phy-cells = &lt;1&gt;;</div><div class='add'>+				mediatek,syscon-type = &lt;&amp;topmisc 0x194 0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		xfi_tphy0: phy@11f20000 {</div><div class='add'>+			compatible = "mediatek,mt7988-xfi-tphy";</div><div class='add'>+			reg = &lt;0 0x11f20000 0 0x10000&gt;;</div><div class='add'>+			clocks = &lt;&amp;xfi_pll CLK_XFIPLL_PLL_EN&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL&gt;;</div><div class='add'>+			clock-names = "xfipll", "topxtal";</div><div class='add'>+			resets = &lt;&amp;watchdog 14&gt;;</div><div class='add'>+			mediatek,usxgmii-performance-errata;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		xfi_tphy1: phy@11f30000 {</div><div class='add'>+			compatible = "mediatek,mt7988-xfi-tphy";</div><div class='add'>+			reg = &lt;0 0x11f30000 0 0x10000&gt;;</div><div class='add'>+			clocks = &lt;&amp;xfi_pll CLK_XFIPLL_PLL_EN&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL&gt;;</div><div class='add'>+			clock-names = "xfipll", "topxtal";</div><div class='add'>+			resets = &lt;&amp;watchdog 15&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		xfi_pll: clock-controller@11f40000 {</div><div class='add'>+			compatible = "mediatek,mt7988-xfi-pll";</div><div class='add'>+			reg = &lt;0 0x11f40000 0 0x1000&gt;;</div><div class='add'>+			resets = &lt;&amp;watchdog 16&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		efuse@11f50000 {</div><div class='add'>+			compatible = "mediatek,mt7988-efuse", "mediatek,efuse";</div><div class='add'>+			reg = &lt;0 0x11f50000 0 0x1000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			soc-uuid@140 {</div><div class='add'>+				reg = &lt;0x140 0x10&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lvts_calibration: calib@918 {</div><div class='add'>+				reg = &lt;0x918 0x28&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			phy_calibration_p0: calib@940 {</div><div class='add'>+				reg = &lt;0x940 0x10&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			phy_calibration_p1: calib@954 {</div><div class='add'>+				reg = &lt;0x954 0x10&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			phy_calibration_p2: calib@968 {</div><div class='add'>+				reg = &lt;0x968 0x10&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			phy_calibration_p3: calib@97c {</div><div class='add'>+				reg = &lt;0x97c 0x10&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ethsys: clock-controller@15000000 {</div><div class='add'>+			compatible = "mediatek,mt7988-ethsys", "syscon";</div><div class='add'>+			reg = &lt;0 0x15000000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		switch: switch@15020000 {</div><div class='add'>+			compatible = "mediatek,mt7988-switch";</div><div class='add'>+			reg = &lt;0 0x15020000 0 0x8000&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			resets = &lt;&amp;ethwarp MT7988_ETHWARP_RST_SWITCH&gt;;</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				gsw_port0: port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					phy-handle = &lt;&amp;gsw_phy0&gt;;</div><div class='add'>+					phy-mode = "internal";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gsw_port1: port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					phy-handle = &lt;&amp;gsw_phy1&gt;;</div><div class='add'>+					phy-mode = "internal";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gsw_port2: port@2 {</div><div class='add'>+					reg = &lt;2&gt;;</div><div class='add'>+					phy-handle = &lt;&amp;gsw_phy2&gt;;</div><div class='add'>+					phy-mode = "internal";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gsw_port3: port@3 {</div><div class='add'>+					reg = &lt;3&gt;;</div><div class='add'>+					phy-handle = &lt;&amp;gsw_phy3&gt;;</div><div class='add'>+					phy-mode = "internal";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@6 {</div><div class='add'>+					reg = &lt;6&gt;;</div><div class='add'>+					ethernet = &lt;&amp;gmac0&gt;;</div><div class='add'>+					phy-mode = "internal";</div><div class='add'>+</div><div class='add'>+					fixed-link {</div><div class='add'>+						speed = &lt;10000&gt;;</div><div class='add'>+						full-duplex;</div><div class='add'>+						pause;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mdio {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				mediatek,pio = &lt;&amp;pio&gt;;</div><div class='add'>+</div><div class='add'>+				gsw_phy0: ethernet-phy@0 {</div><div class='add'>+					compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					interrupts = &lt;0&gt;;</div><div class='add'>+					nvmem-cells = &lt;&amp;phy_calibration_p0&gt;;</div><div class='add'>+					nvmem-cell-names = "phy-cal-data";</div><div class='add'>+</div><div class='add'>+					leds {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						gsw_phy0_led0: led@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+							status = "disabled";</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						gsw_phy0_led1: led@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+							status = "disabled";</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gsw_phy1: ethernet-phy@1 {</div><div class='add'>+					compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					interrupts = &lt;1&gt;;</div><div class='add'>+					nvmem-cells = &lt;&amp;phy_calibration_p1&gt;;</div><div class='add'>+					nvmem-cell-names = "phy-cal-data";</div><div class='add'>+</div><div class='add'>+					leds {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						gsw_phy1_led0: led@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+							status = "disabled";</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						gsw_phy1_led1: led@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+							status = "disabled";</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gsw_phy2: ethernet-phy@2 {</div><div class='add'>+					compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+					reg = &lt;2&gt;;</div><div class='add'>+					interrupts = &lt;2&gt;;</div><div class='add'>+					nvmem-cells = &lt;&amp;phy_calibration_p2&gt;;</div><div class='add'>+					nvmem-cell-names = "phy-cal-data";</div><div class='add'>+</div><div class='add'>+					leds {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						gsw_phy2_led0: led@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+							status = "disabled";</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						gsw_phy2_led1: led@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+							status = "disabled";</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gsw_phy3: ethernet-phy@3 {</div><div class='add'>+					compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+					reg = &lt;3&gt;;</div><div class='add'>+					interrupts = &lt;3&gt;;</div><div class='add'>+					nvmem-cells = &lt;&amp;phy_calibration_p3&gt;;</div><div class='add'>+					nvmem-cell-names = "phy-cal-data";</div><div class='add'>+</div><div class='add'>+					leds {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						gsw_phy3_led0: led@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+							status = "disabled";</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						gsw_phy3_led1: led@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+							status = "disabled";</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ethwarp: clock-controller@15031000 {</div><div class='add'>+			compatible = "mediatek,mt7988-ethwarp";</div><div class='add'>+			reg = &lt;0 0x15031000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		eth: ethernet@15100000 {</div><div class='add'>+			compatible = "mediatek,mt7988-eth";</div><div class='add'>+			reg = &lt;0 0x15100000 0 0x40000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "fe0", "fe1", "fe2", "fe3", "pdma0",</div><div class='add'>+					  "pdma1", "pdma2", "pdma3";</div><div class='add'>+			clocks = &lt;&amp;ethsys CLK_ETHDMA_CRYPT0_EN&gt;,</div><div class='add'>+				 &lt;&amp;ethsys CLK_ETHDMA_FE_EN&gt;,</div><div class='add'>+				 &lt;&amp;ethsys CLK_ETHDMA_GP2_EN&gt;,</div><div class='add'>+				 &lt;&amp;ethsys CLK_ETHDMA_GP1_EN&gt;,</div><div class='add'>+				 &lt;&amp;ethsys CLK_ETHDMA_GP3_EN&gt;,</div><div class='add'>+				 &lt;&amp;ethwarp CLK_ETHWARP_WOCPU2_EN&gt;,</div><div class='add'>+				 &lt;&amp;ethwarp CLK_ETHWARP_WOCPU1_EN&gt;,</div><div class='add'>+				 &lt;&amp;ethwarp CLK_ETHWARP_WOCPU0_EN&gt;,</div><div class='add'>+				 &lt;&amp;ethsys CLK_ETHDMA_ESW_EN&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_ETH_GMII_SEL&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_ETH_REFCK_50M_SEL&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_ETH_SYS_200M_SEL&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_ETH_SYS_SEL&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_ETH_XGMII_SEL&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_ETH_MII_SEL&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_NETSYS_SEL&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_NETSYS_500M_SEL&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_NETSYS_PAO_2X_SEL&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_NETSYS_SYNC_250M_SEL&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_NETSYS_WARP_SEL&gt;,</div><div class='add'>+				 &lt;&amp;ethsys CLK_ETHDMA_XGP1_EN&gt;,</div><div class='add'>+				 &lt;&amp;ethsys CLK_ETHDMA_XGP2_EN&gt;,</div><div class='add'>+				 &lt;&amp;ethsys CLK_ETHDMA_XGP3_EN&gt;;</div><div class='add'>+			clock-names = "crypto", "fe", "gp2", "gp1", "gp3",</div><div class='add'>+				      "ethwarp_wocpu2", "ethwarp_wocpu1",</div><div class='add'>+				      "ethwarp_wocpu0", "esw", "top_eth_gmii_sel",</div><div class='add'>+				      "top_eth_refck_50m_sel", "top_eth_sys_200m_sel",</div><div class='add'>+				      "top_eth_sys_sel", "top_eth_xgmii_sel",</div><div class='add'>+				      "top_eth_mii_sel", "top_netsys_sel",</div><div class='add'>+				      "top_netsys_500m_sel", "top_netsys_pao_2x_sel",</div><div class='add'>+				      "top_netsys_sync_250m_sel",</div><div class='add'>+				      "top_netsys_ppefb_250m_sel",</div><div class='add'>+				      "top_netsys_warp_sel","xgp1", "xgp2", "xgp3";</div><div class='add'>+			assigned-clocks = &lt;&amp;topckgen CLK_TOP_NETSYS_2X_SEL&gt;,</div><div class='add'>+					  &lt;&amp;topckgen CLK_TOP_NETSYS_GSW_SEL&gt;,</div><div class='add'>+					  &lt;&amp;topckgen CLK_TOP_USXGMII_SBUS_0_SEL&gt;,</div><div class='add'>+					  &lt;&amp;topckgen CLK_TOP_USXGMII_SBUS_1_SEL&gt;,</div><div class='add'>+					  &lt;&amp;topckgen CLK_TOP_SGM_0_SEL&gt;,</div><div class='add'>+					  &lt;&amp;topckgen CLK_TOP_SGM_1_SEL&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;apmixedsys CLK_APMIXED_NET2PLL&gt;,</div><div class='add'>+						 &lt;&amp;topckgen CLK_TOP_NET1PLL_D4&gt;,</div><div class='add'>+						 &lt;&amp;topckgen CLK_TOP_NET1PLL_D8_D4&gt;,</div><div class='add'>+						 &lt;&amp;topckgen CLK_TOP_NET1PLL_D8_D4&gt;,</div><div class='add'>+						 &lt;&amp;apmixedsys CLK_APMIXED_SGMPLL&gt;,</div><div class='add'>+						 &lt;&amp;apmixedsys CLK_APMIXED_SGMPLL&gt;;</div><div class='add'>+			sram = &lt;&amp;eth_sram&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			mediatek,ethsys = &lt;&amp;ethsys&gt;;</div><div class='add'>+			mediatek,infracfg = &lt;&amp;topmisc&gt;;</div><div class='add'>+</div><div class='add'>+			gmac0: mac@0 {</div><div class='add'>+				compatible = "mediatek,eth-mac";</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				phy-mode = "internal";</div><div class='add'>+</div><div class='add'>+				/* Connected to internal switch */</div><div class='add'>+				fixed-link {</div><div class='add'>+					speed = &lt;10000&gt;;</div><div class='add'>+					full-duplex;</div><div class='add'>+					pause;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gmac1: mac@1 {</div><div class='add'>+				compatible = "mediatek,eth-mac";</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gmac2: mac@2 {</div><div class='add'>+				compatible = "mediatek,eth-mac";</div><div class='add'>+				reg = &lt;2&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mdio_bus: mdio-bus {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				/* internal 2.5G PHY */</div><div class='add'>+				int_2p5g_phy: ethernet-phy@15 {</div><div class='add'>+					compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+					reg = &lt;15&gt;;</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		eth_sram: sram@15400000 {</div><div class='add'>+			compatible = "mmio-sram";</div><div class='add'>+			reg = &lt;0 0x15400000 0 0x200000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges = &lt;0 0x15400000 0 0x200000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	thermal-zones {</div><div class='add'>+		cpu_thermal: cpu-thermal {</div><div class='add'>+			polling-delay-passive = &lt;1000&gt;;</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts 0&gt;;</div><div class='add'>+			trips {</div><div class='add'>+				cpu_trip_crit: crit {</div><div class='add'>+					temperature = &lt;125000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8167-pinfunc.h b/arch/arm64/boot/dts/mediatek/mt8167-pinfunc.h<br/>new file mode 100644<br/>index 000000000000..061c3255a973<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8167-pinfunc.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8167-pinfunc.h</a></div><div class='hunk'>@@ -0,0 +1,744 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0 */</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2020 MediaTek Inc.</div><div class='add'>+ */</div><div class='add'>+#ifndef __DTS_MT8167_PINFUNC_H</div><div class='add'>+#define __DTS_MT8167_PINFUNC_H</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/pinctrl/mt65xx.h&gt;</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_0_EINT0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)</div><div class='add'>+#define MT8167_PIN_0_EINT0__FUNC_PWM_B (MTK_PIN_NO(0) | 1)</div><div class='add'>+#define MT8167_PIN_0_EINT0__FUNC_DPI_CK (MTK_PIN_NO(0) | 2)</div><div class='add'>+#define MT8167_PIN_0_EINT0__FUNC_I2S2_BCK (MTK_PIN_NO(0) | 3)</div><div class='add'>+#define MT8167_PIN_0_EINT0__FUNC_EXT_TXD0 (MTK_PIN_NO(0) | 4)</div><div class='add'>+#define MT8167_PIN_0_EINT0__FUNC_SQICS (MTK_PIN_NO(0) | 6)</div><div class='add'>+#define MT8167_PIN_0_EINT0__FUNC_DBG_MON_A_6 (MTK_PIN_NO(0) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_1_EINT1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)</div><div class='add'>+#define MT8167_PIN_1_EINT1__FUNC_PWM_C (MTK_PIN_NO(1) | 1)</div><div class='add'>+#define MT8167_PIN_1_EINT1__FUNC_DPI_D12 (MTK_PIN_NO(1) | 2)</div><div class='add'>+#define MT8167_PIN_1_EINT1__FUNC_I2S2_DI (MTK_PIN_NO(1) | 3)</div><div class='add'>+#define MT8167_PIN_1_EINT1__FUNC_EXT_TXD1 (MTK_PIN_NO(1) | 4)</div><div class='add'>+#define MT8167_PIN_1_EINT1__FUNC_CONN_MCU_TDO (MTK_PIN_NO(1) | 5)</div><div class='add'>+#define MT8167_PIN_1_EINT1__FUNC_SQISO (MTK_PIN_NO(1) | 6)</div><div class='add'>+#define MT8167_PIN_1_EINT1__FUNC_DBG_MON_A_7 (MTK_PIN_NO(1) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_2_EINT2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)</div><div class='add'>+#define MT8167_PIN_2_EINT2__FUNC_CLKM0 (MTK_PIN_NO(2) | 1)</div><div class='add'>+#define MT8167_PIN_2_EINT2__FUNC_DPI_D13 (MTK_PIN_NO(2) | 2)</div><div class='add'>+#define MT8167_PIN_2_EINT2__FUNC_I2S2_LRCK (MTK_PIN_NO(2) | 3)</div><div class='add'>+#define MT8167_PIN_2_EINT2__FUNC_EXT_TXD2 (MTK_PIN_NO(2) | 4)</div><div class='add'>+#define MT8167_PIN_2_EINT2__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(2) | 5)</div><div class='add'>+#define MT8167_PIN_2_EINT2__FUNC_SQISI (MTK_PIN_NO(2) | 6)</div><div class='add'>+#define MT8167_PIN_2_EINT2__FUNC_DBG_MON_A_8 (MTK_PIN_NO(2) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_3_EINT3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)</div><div class='add'>+#define MT8167_PIN_3_EINT3__FUNC_CLKM1 (MTK_PIN_NO(3) | 1)</div><div class='add'>+#define MT8167_PIN_3_EINT3__FUNC_DPI_D14 (MTK_PIN_NO(3) | 2)</div><div class='add'>+#define MT8167_PIN_3_EINT3__FUNC_SPI_MI (MTK_PIN_NO(3) | 3)</div><div class='add'>+#define MT8167_PIN_3_EINT3__FUNC_EXT_TXD3 (MTK_PIN_NO(3) | 4)</div><div class='add'>+#define MT8167_PIN_3_EINT3__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(3) | 5)</div><div class='add'>+#define MT8167_PIN_3_EINT3__FUNC_SQIWP (MTK_PIN_NO(3) | 6)</div><div class='add'>+#define MT8167_PIN_3_EINT3__FUNC_DBG_MON_A_9 (MTK_PIN_NO(3) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_4_EINT4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)</div><div class='add'>+#define MT8167_PIN_4_EINT4__FUNC_CLKM2 (MTK_PIN_NO(4) | 1)</div><div class='add'>+#define MT8167_PIN_4_EINT4__FUNC_DPI_D15 (MTK_PIN_NO(4) | 2)</div><div class='add'>+#define MT8167_PIN_4_EINT4__FUNC_SPI_MO (MTK_PIN_NO(4) | 3)</div><div class='add'>+#define MT8167_PIN_4_EINT4__FUNC_EXT_TXC (MTK_PIN_NO(4) | 4)</div><div class='add'>+#define MT8167_PIN_4_EINT4__FUNC_CONN_MCU_TCK (MTK_PIN_NO(4) | 5)</div><div class='add'>+#define MT8167_PIN_4_EINT4__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(4) | 6)</div><div class='add'>+#define MT8167_PIN_4_EINT4__FUNC_DBG_MON_A_10 (MTK_PIN_NO(4) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_5_EINT5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)</div><div class='add'>+#define MT8167_PIN_5_EINT5__FUNC_UCTS2 (MTK_PIN_NO(5) | 1)</div><div class='add'>+#define MT8167_PIN_5_EINT5__FUNC_DPI_D16 (MTK_PIN_NO(5) | 2)</div><div class='add'>+#define MT8167_PIN_5_EINT5__FUNC_SPI_CSB (MTK_PIN_NO(5) | 3)</div><div class='add'>+#define MT8167_PIN_5_EINT5__FUNC_EXT_RXER (MTK_PIN_NO(5) | 4)</div><div class='add'>+#define MT8167_PIN_5_EINT5__FUNC_CONN_MCU_TDI (MTK_PIN_NO(5) | 5)</div><div class='add'>+#define MT8167_PIN_5_EINT5__FUNC_CONN_TEST_CK (MTK_PIN_NO(5) | 6)</div><div class='add'>+#define MT8167_PIN_5_EINT5__FUNC_DBG_MON_A_11 (MTK_PIN_NO(5) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_6_EINT6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)</div><div class='add'>+#define MT8167_PIN_6_EINT6__FUNC_URTS2 (MTK_PIN_NO(6) | 1)</div><div class='add'>+#define MT8167_PIN_6_EINT6__FUNC_DPI_D17 (MTK_PIN_NO(6) | 2)</div><div class='add'>+#define MT8167_PIN_6_EINT6__FUNC_SPI_CLK (MTK_PIN_NO(6) | 3)</div><div class='add'>+#define MT8167_PIN_6_EINT6__FUNC_EXT_RXC (MTK_PIN_NO(6) | 4)</div><div class='add'>+#define MT8167_PIN_6_EINT6__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(6) | 5)</div><div class='add'>+#define MT8167_PIN_6_EINT6__FUNC_MM_TEST_CK (MTK_PIN_NO(6) | 6)</div><div class='add'>+#define MT8167_PIN_6_EINT6__FUNC_DBG_MON_A_12 (MTK_PIN_NO(6) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_7_EINT7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)</div><div class='add'>+#define MT8167_PIN_7_EINT7__FUNC_SQIRST (MTK_PIN_NO(7) | 1)</div><div class='add'>+#define MT8167_PIN_7_EINT7__FUNC_DPI_D6 (MTK_PIN_NO(7) | 2)</div><div class='add'>+#define MT8167_PIN_7_EINT7__FUNC_SDA1_0 (MTK_PIN_NO(7) | 3)</div><div class='add'>+#define MT8167_PIN_7_EINT7__FUNC_EXT_RXDV (MTK_PIN_NO(7) | 4)</div><div class='add'>+#define MT8167_PIN_7_EINT7__FUNC_CONN_MCU_TMS (MTK_PIN_NO(7) | 5)</div><div class='add'>+#define MT8167_PIN_7_EINT7__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(7) | 6)</div><div class='add'>+#define MT8167_PIN_7_EINT7__FUNC_DBG_MON_A_13 (MTK_PIN_NO(7) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_8_EINT8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)</div><div class='add'>+#define MT8167_PIN_8_EINT8__FUNC_SQICK (MTK_PIN_NO(8) | 1)</div><div class='add'>+#define MT8167_PIN_8_EINT8__FUNC_CLKM3 (MTK_PIN_NO(8) | 2)</div><div class='add'>+#define MT8167_PIN_8_EINT8__FUNC_SCL1_0 (MTK_PIN_NO(8) | 3)</div><div class='add'>+#define MT8167_PIN_8_EINT8__FUNC_EXT_RXD0 (MTK_PIN_NO(8) | 4)</div><div class='add'>+#define MT8167_PIN_8_EINT8__FUNC_ANT_SEL0 (MTK_PIN_NO(8) | 5)</div><div class='add'>+#define MT8167_PIN_8_EINT8__FUNC_DPI_D7 (MTK_PIN_NO(8) | 6)</div><div class='add'>+#define MT8167_PIN_8_EINT8__FUNC_DBG_MON_A_14 (MTK_PIN_NO(8) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_9_EINT9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)</div><div class='add'>+#define MT8167_PIN_9_EINT9__FUNC_CLKM4 (MTK_PIN_NO(9) | 1)</div><div class='add'>+#define MT8167_PIN_9_EINT9__FUNC_SDA2_0 (MTK_PIN_NO(9) | 2)</div><div class='add'>+#define MT8167_PIN_9_EINT9__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(9) | 3)</div><div class='add'>+#define MT8167_PIN_9_EINT9__FUNC_EXT_RXD1 (MTK_PIN_NO(9) | 4)</div><div class='add'>+#define MT8167_PIN_9_EINT9__FUNC_ANT_SEL1 (MTK_PIN_NO(9) | 5)</div><div class='add'>+#define MT8167_PIN_9_EINT9__FUNC_DPI_D8 (MTK_PIN_NO(9) | 6)</div><div class='add'>+#define MT8167_PIN_9_EINT9__FUNC_DBG_MON_A_15 (MTK_PIN_NO(9) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_10_EINT10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)</div><div class='add'>+#define MT8167_PIN_10_EINT10__FUNC_CLKM5 (MTK_PIN_NO(10) | 1)</div><div class='add'>+#define MT8167_PIN_10_EINT10__FUNC_SCL2_0 (MTK_PIN_NO(10) | 2)</div><div class='add'>+#define MT8167_PIN_10_EINT10__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(10) | 3)</div><div class='add'>+#define MT8167_PIN_10_EINT10__FUNC_EXT_RXD2 (MTK_PIN_NO(10) | 4)</div><div class='add'>+#define MT8167_PIN_10_EINT10__FUNC_ANT_SEL2 (MTK_PIN_NO(10) | 5)</div><div class='add'>+#define MT8167_PIN_10_EINT10__FUNC_DPI_D9 (MTK_PIN_NO(10) | 6)</div><div class='add'>+#define MT8167_PIN_10_EINT10__FUNC_DBG_MON_A_16 (MTK_PIN_NO(10) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_11_EINT11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)</div><div class='add'>+#define MT8167_PIN_11_EINT11__FUNC_CLKM4 (MTK_PIN_NO(11) | 1)</div><div class='add'>+#define MT8167_PIN_11_EINT11__FUNC_PWM_C (MTK_PIN_NO(11) | 2)</div><div class='add'>+#define MT8167_PIN_11_EINT11__FUNC_CONN_TEST_CK (MTK_PIN_NO(11) | 3)</div><div class='add'>+#define MT8167_PIN_11_EINT11__FUNC_ANT_SEL3 (MTK_PIN_NO(11) | 4)</div><div class='add'>+#define MT8167_PIN_11_EINT11__FUNC_DPI_D10 (MTK_PIN_NO(11) | 5)</div><div class='add'>+#define MT8167_PIN_11_EINT11__FUNC_EXT_RXD3 (MTK_PIN_NO(11) | 6)</div><div class='add'>+#define MT8167_PIN_11_EINT11__FUNC_DBG_MON_A_17 (MTK_PIN_NO(11) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_12_EINT12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)</div><div class='add'>+#define MT8167_PIN_12_EINT12__FUNC_CLKM5 (MTK_PIN_NO(12) | 1)</div><div class='add'>+#define MT8167_PIN_12_EINT12__FUNC_PWM_A (MTK_PIN_NO(12) | 2)</div><div class='add'>+#define MT8167_PIN_12_EINT12__FUNC_SPDIF_OUT (MTK_PIN_NO(12) | 3)</div><div class='add'>+#define MT8167_PIN_12_EINT12__FUNC_ANT_SEL4 (MTK_PIN_NO(12) | 4)</div><div class='add'>+#define MT8167_PIN_12_EINT12__FUNC_DPI_D11 (MTK_PIN_NO(12) | 5)</div><div class='add'>+#define MT8167_PIN_12_EINT12__FUNC_EXT_TXEN (MTK_PIN_NO(12) | 6)</div><div class='add'>+#define MT8167_PIN_12_EINT12__FUNC_DBG_MON_A_18 (MTK_PIN_NO(12) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_13_EINT13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)</div><div class='add'>+#define MT8167_PIN_13_EINT13__FUNC_TSF_IN (MTK_PIN_NO(13) | 3)</div><div class='add'>+#define MT8167_PIN_13_EINT13__FUNC_ANT_SEL5 (MTK_PIN_NO(13) | 4)</div><div class='add'>+#define MT8167_PIN_13_EINT13__FUNC_DPI_D0 (MTK_PIN_NO(13) | 5)</div><div class='add'>+#define MT8167_PIN_13_EINT13__FUNC_SPDIF_IN (MTK_PIN_NO(13) | 6)</div><div class='add'>+#define MT8167_PIN_13_EINT13__FUNC_DBG_MON_A_19 (MTK_PIN_NO(13) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_14_EINT14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)</div><div class='add'>+#define MT8167_PIN_14_EINT14__FUNC_I2S_8CH_DO1 (MTK_PIN_NO(14) | 2)</div><div class='add'>+#define MT8167_PIN_14_EINT14__FUNC_TDM_RX_MCK (MTK_PIN_NO(14) | 3)</div><div class='add'>+#define MT8167_PIN_14_EINT14__FUNC_ANT_SEL1 (MTK_PIN_NO(14) | 4)</div><div class='add'>+#define MT8167_PIN_14_EINT14__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(14) | 5)</div><div class='add'>+#define MT8167_PIN_14_EINT14__FUNC_NCLE (MTK_PIN_NO(14) | 6)</div><div class='add'>+#define MT8167_PIN_14_EINT14__FUNC_DBG_MON_B_8 (MTK_PIN_NO(14) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_15_EINT15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)</div><div class='add'>+#define MT8167_PIN_15_EINT15__FUNC_I2S_8CH_LRCK (MTK_PIN_NO(15) | 2)</div><div class='add'>+#define MT8167_PIN_15_EINT15__FUNC_TDM_RX_BCK (MTK_PIN_NO(15) | 3)</div><div class='add'>+#define MT8167_PIN_15_EINT15__FUNC_ANT_SEL2 (MTK_PIN_NO(15) | 4)</div><div class='add'>+#define MT8167_PIN_15_EINT15__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(15) | 5)</div><div class='add'>+#define MT8167_PIN_15_EINT15__FUNC_NCEB1 (MTK_PIN_NO(15) | 6)</div><div class='add'>+#define MT8167_PIN_15_EINT15__FUNC_DBG_MON_B_9 (MTK_PIN_NO(15) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_16_EINT16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0)</div><div class='add'>+#define MT8167_PIN_16_EINT16__FUNC_I2S_8CH_BCK (MTK_PIN_NO(16) | 2)</div><div class='add'>+#define MT8167_PIN_16_EINT16__FUNC_TDM_RX_LRCK (MTK_PIN_NO(16) | 3)</div><div class='add'>+#define MT8167_PIN_16_EINT16__FUNC_ANT_SEL3 (MTK_PIN_NO(16) | 4)</div><div class='add'>+#define MT8167_PIN_16_EINT16__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(16) | 5)</div><div class='add'>+#define MT8167_PIN_16_EINT16__FUNC_NCEB0 (MTK_PIN_NO(16) | 6)</div><div class='add'>+#define MT8167_PIN_16_EINT16__FUNC_DBG_MON_B_10 (MTK_PIN_NO(16) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_17_EINT17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0)</div><div class='add'>+#define MT8167_PIN_17_EINT17__FUNC_I2S_8CH_MCK (MTK_PIN_NO(17) | 2)</div><div class='add'>+#define MT8167_PIN_17_EINT17__FUNC_TDM_RX_DI (MTK_PIN_NO(17) | 3)</div><div class='add'>+#define MT8167_PIN_17_EINT17__FUNC_IDDIG (MTK_PIN_NO(17) | 4)</div><div class='add'>+#define MT8167_PIN_17_EINT17__FUNC_ANT_SEL4 (MTK_PIN_NO(17) | 5)</div><div class='add'>+#define MT8167_PIN_17_EINT17__FUNC_NREB (MTK_PIN_NO(17) | 6)</div><div class='add'>+#define MT8167_PIN_17_EINT17__FUNC_DBG_MON_B_11 (MTK_PIN_NO(17) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_18_EINT18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)</div><div class='add'>+#define MT8167_PIN_18_EINT18__FUNC_USB_DRVVBUS (MTK_PIN_NO(18) | 2)</div><div class='add'>+#define MT8167_PIN_18_EINT18__FUNC_I2S3_LRCK (MTK_PIN_NO(18) | 3)</div><div class='add'>+#define MT8167_PIN_18_EINT18__FUNC_CLKM1 (MTK_PIN_NO(18) | 4)</div><div class='add'>+#define MT8167_PIN_18_EINT18__FUNC_ANT_SEL3 (MTK_PIN_NO(18) | 5)</div><div class='add'>+#define MT8167_PIN_18_EINT18__FUNC_I2S2_BCK (MTK_PIN_NO(18) | 6)</div><div class='add'>+#define MT8167_PIN_18_EINT18__FUNC_DBG_MON_A_20 (MTK_PIN_NO(18) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_19_EINT19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)</div><div class='add'>+#define MT8167_PIN_19_EINT19__FUNC_UCTS1 (MTK_PIN_NO(19) | 1)</div><div class='add'>+#define MT8167_PIN_19_EINT19__FUNC_IDDIG (MTK_PIN_NO(19) | 2)</div><div class='add'>+#define MT8167_PIN_19_EINT19__FUNC_I2S3_BCK (MTK_PIN_NO(19) | 3)</div><div class='add'>+#define MT8167_PIN_19_EINT19__FUNC_CLKM2 (MTK_PIN_NO(19) | 4)</div><div class='add'>+#define MT8167_PIN_19_EINT19__FUNC_ANT_SEL4 (MTK_PIN_NO(19) | 5)</div><div class='add'>+#define MT8167_PIN_19_EINT19__FUNC_I2S2_DI (MTK_PIN_NO(19) | 6)</div><div class='add'>+#define MT8167_PIN_19_EINT19__FUNC_DBG_MON_A_21 (MTK_PIN_NO(19) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_20_EINT20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)</div><div class='add'>+#define MT8167_PIN_20_EINT20__FUNC_URTS1 (MTK_PIN_NO(20) | 1)</div><div class='add'>+#define MT8167_PIN_20_EINT20__FUNC_I2S3_DO (MTK_PIN_NO(20) | 3)</div><div class='add'>+#define MT8167_PIN_20_EINT20__FUNC_CLKM3 (MTK_PIN_NO(20) | 4)</div><div class='add'>+#define MT8167_PIN_20_EINT20__FUNC_ANT_SEL5 (MTK_PIN_NO(20) | 5)</div><div class='add'>+#define MT8167_PIN_20_EINT20__FUNC_I2S2_LRCK (MTK_PIN_NO(20) | 6)</div><div class='add'>+#define MT8167_PIN_20_EINT20__FUNC_DBG_MON_A_22 (MTK_PIN_NO(20) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_21_EINT21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)</div><div class='add'>+#define MT8167_PIN_21_EINT21__FUNC_NRNB (MTK_PIN_NO(21) | 1)</div><div class='add'>+#define MT8167_PIN_21_EINT21__FUNC_ANT_SEL0 (MTK_PIN_NO(21) | 2)</div><div class='add'>+#define MT8167_PIN_21_EINT21__FUNC_I2S_8CH_DO4 (MTK_PIN_NO(21) | 3)</div><div class='add'>+#define MT8167_PIN_21_EINT21__FUNC_DBG_MON_B_31 (MTK_PIN_NO(21) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_22_EINT22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)</div><div class='add'>+#define MT8167_PIN_22_EINT22__FUNC_I2S_8CH_DO2 (MTK_PIN_NO(22) | 2)</div><div class='add'>+#define MT8167_PIN_22_EINT22__FUNC_TSF_IN (MTK_PIN_NO(22) | 3)</div><div class='add'>+#define MT8167_PIN_22_EINT22__FUNC_USB_DRVVBUS (MTK_PIN_NO(22) | 4)</div><div class='add'>+#define MT8167_PIN_22_EINT22__FUNC_SPDIF_OUT (MTK_PIN_NO(22) | 5)</div><div class='add'>+#define MT8167_PIN_22_EINT22__FUNC_NRE_C (MTK_PIN_NO(22) | 6)</div><div class='add'>+#define MT8167_PIN_22_EINT22__FUNC_DBG_MON_B_12 (MTK_PIN_NO(22) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_23_EINT23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)</div><div class='add'>+#define MT8167_PIN_23_EINT23__FUNC_I2S_8CH_DO3 (MTK_PIN_NO(23) | 2)</div><div class='add'>+#define MT8167_PIN_23_EINT23__FUNC_CLKM0 (MTK_PIN_NO(23) | 3)</div><div class='add'>+#define MT8167_PIN_23_EINT23__FUNC_IR (MTK_PIN_NO(23) | 4)</div><div class='add'>+#define MT8167_PIN_23_EINT23__FUNC_SPDIF_IN (MTK_PIN_NO(23) | 5)</div><div class='add'>+#define MT8167_PIN_23_EINT23__FUNC_NDQS_C (MTK_PIN_NO(23) | 6)</div><div class='add'>+#define MT8167_PIN_23_EINT23__FUNC_DBG_MON_B_13 (MTK_PIN_NO(23) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_24_EINT24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)</div><div class='add'>+#define MT8167_PIN_24_EINT24__FUNC_DPI_D20 (MTK_PIN_NO(24) | 1)</div><div class='add'>+#define MT8167_PIN_24_EINT24__FUNC_DPI_DE (MTK_PIN_NO(24) | 2)</div><div class='add'>+#define MT8167_PIN_24_EINT24__FUNC_ANT_SEL1 (MTK_PIN_NO(24) | 3)</div><div class='add'>+#define MT8167_PIN_24_EINT24__FUNC_UCTS2 (MTK_PIN_NO(24) | 4)</div><div class='add'>+#define MT8167_PIN_24_EINT24__FUNC_PWM_A (MTK_PIN_NO(24) | 5)</div><div class='add'>+#define MT8167_PIN_24_EINT24__FUNC_I2S0_MCK (MTK_PIN_NO(24) | 6)</div><div class='add'>+#define MT8167_PIN_24_EINT24__FUNC_DBG_MON_A_0 (MTK_PIN_NO(24) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_25_EINT25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)</div><div class='add'>+#define MT8167_PIN_25_EINT25__FUNC_DPI_D19 (MTK_PIN_NO(25) | 1)</div><div class='add'>+#define MT8167_PIN_25_EINT25__FUNC_DPI_VSYNC (MTK_PIN_NO(25) | 2)</div><div class='add'>+#define MT8167_PIN_25_EINT25__FUNC_ANT_SEL0 (MTK_PIN_NO(25) | 3)</div><div class='add'>+#define MT8167_PIN_25_EINT25__FUNC_URTS2 (MTK_PIN_NO(25) | 4)</div><div class='add'>+#define MT8167_PIN_25_EINT25__FUNC_PWM_B (MTK_PIN_NO(25) | 5)</div><div class='add'>+#define MT8167_PIN_25_EINT25__FUNC_I2S_8CH_MCK (MTK_PIN_NO(25) | 6)</div><div class='add'>+#define MT8167_PIN_25_EINT25__FUNC_DBG_MON_A_1 (MTK_PIN_NO(25) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_26_PWRAP_SPI0_MI__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)</div><div class='add'>+#define MT8167_PIN_26_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(26) | 1)</div><div class='add'>+#define MT8167_PIN_26_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(26) | 2)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_27_PWRAP_SPI0_MO__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)</div><div class='add'>+#define MT8167_PIN_27_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(27) | 1)</div><div class='add'>+#define MT8167_PIN_27_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(27) | 2)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_28_PWRAP_INT__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)</div><div class='add'>+#define MT8167_PIN_28_PWRAP_INT__FUNC_I2S0_MCK (MTK_PIN_NO(28) | 1)</div><div class='add'>+#define MT8167_PIN_28_PWRAP_INT__FUNC_I2S_8CH_MCK (MTK_PIN_NO(28) | 4)</div><div class='add'>+#define MT8167_PIN_28_PWRAP_INT__FUNC_I2S2_MCK (MTK_PIN_NO(28) | 5)</div><div class='add'>+#define MT8167_PIN_28_PWRAP_INT__FUNC_I2S3_MCK (MTK_PIN_NO(28) | 6)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_29_PWRAP_SPI0_CK__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)</div><div class='add'>+#define MT8167_PIN_29_PWRAP_SPI0_CK__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(29) | 1)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_30_PWRAP_SPI0_CSN__FUNC_GPIO30 (MTK_PIN_NO(30) | 0)</div><div class='add'>+#define MT8167_PIN_30_PWRAP_SPI0_CSN__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(30) | 1)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_31_RTC32K_CK__FUNC_GPIO31 (MTK_PIN_NO(31) | 0)</div><div class='add'>+#define MT8167_PIN_31_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(31) | 1)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_32_WATCHDOG__FUNC_GPIO32 (MTK_PIN_NO(32) | 0)</div><div class='add'>+#define MT8167_PIN_32_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(32) | 1)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_33_SRCLKENA__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)</div><div class='add'>+#define MT8167_PIN_33_SRCLKENA__FUNC_SRCLKENA0 (MTK_PIN_NO(33) | 1)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_34_URXD2__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)</div><div class='add'>+#define MT8167_PIN_34_URXD2__FUNC_URXD2 (MTK_PIN_NO(34) | 1)</div><div class='add'>+#define MT8167_PIN_34_URXD2__FUNC_DPI_D5 (MTK_PIN_NO(34) | 2)</div><div class='add'>+#define MT8167_PIN_34_URXD2__FUNC_UTXD2 (MTK_PIN_NO(34) | 3)</div><div class='add'>+#define MT8167_PIN_34_URXD2__FUNC_DBG_SCL (MTK_PIN_NO(34) | 4)</div><div class='add'>+#define MT8167_PIN_34_URXD2__FUNC_I2S2_MCK (MTK_PIN_NO(34) | 6)</div><div class='add'>+#define MT8167_PIN_34_URXD2__FUNC_DBG_MON_B_0 (MTK_PIN_NO(34) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_35_UTXD2__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)</div><div class='add'>+#define MT8167_PIN_35_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(35) | 1)</div><div class='add'>+#define MT8167_PIN_35_UTXD2__FUNC_DPI_HSYNC (MTK_PIN_NO(35) | 2)</div><div class='add'>+#define MT8167_PIN_35_UTXD2__FUNC_URXD2 (MTK_PIN_NO(35) | 3)</div><div class='add'>+#define MT8167_PIN_35_UTXD2__FUNC_DBG_SDA (MTK_PIN_NO(35) | 4)</div><div class='add'>+#define MT8167_PIN_35_UTXD2__FUNC_DPI_D18 (MTK_PIN_NO(35) | 5)</div><div class='add'>+#define MT8167_PIN_35_UTXD2__FUNC_I2S3_MCK (MTK_PIN_NO(35) | 6)</div><div class='add'>+#define MT8167_PIN_35_UTXD2__FUNC_DBG_MON_B_1 (MTK_PIN_NO(35) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_36_MRG_CLK__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)</div><div class='add'>+#define MT8167_PIN_36_MRG_CLK__FUNC_MRG_CLK (MTK_PIN_NO(36) | 1)</div><div class='add'>+#define MT8167_PIN_36_MRG_CLK__FUNC_DPI_D4 (MTK_PIN_NO(36) | 2)</div><div class='add'>+#define MT8167_PIN_36_MRG_CLK__FUNC_I2S0_BCK (MTK_PIN_NO(36) | 3)</div><div class='add'>+#define MT8167_PIN_36_MRG_CLK__FUNC_I2S3_BCK (MTK_PIN_NO(36) | 4)</div><div class='add'>+#define MT8167_PIN_36_MRG_CLK__FUNC_PCM0_CLK (MTK_PIN_NO(36) | 5)</div><div class='add'>+#define MT8167_PIN_36_MRG_CLK__FUNC_IR (MTK_PIN_NO(36) | 6)</div><div class='add'>+#define MT8167_PIN_36_MRG_CLK__FUNC_DBG_MON_A_2 (MTK_PIN_NO(36) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_37_MRG_SYNC__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)</div><div class='add'>+#define MT8167_PIN_37_MRG_SYNC__FUNC_MRG_SYNC (MTK_PIN_NO(37) | 1)</div><div class='add'>+#define MT8167_PIN_37_MRG_SYNC__FUNC_DPI_D3 (MTK_PIN_NO(37) | 2)</div><div class='add'>+#define MT8167_PIN_37_MRG_SYNC__FUNC_I2S0_LRCK (MTK_PIN_NO(37) | 3)</div><div class='add'>+#define MT8167_PIN_37_MRG_SYNC__FUNC_I2S3_LRCK (MTK_PIN_NO(37) | 4)</div><div class='add'>+#define MT8167_PIN_37_MRG_SYNC__FUNC_PCM0_SYNC (MTK_PIN_NO(37) | 5)</div><div class='add'>+#define MT8167_PIN_37_MRG_SYNC__FUNC_EXT_COL (MTK_PIN_NO(37) | 6)</div><div class='add'>+#define MT8167_PIN_37_MRG_SYNC__FUNC_DBG_MON_A_3 (MTK_PIN_NO(37) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_38_MRG_DI__FUNC_GPIO38 (MTK_PIN_NO(38) | 0)</div><div class='add'>+#define MT8167_PIN_38_MRG_DI__FUNC_MRG_DI (MTK_PIN_NO(38) | 1)</div><div class='add'>+#define MT8167_PIN_38_MRG_DI__FUNC_DPI_D1 (MTK_PIN_NO(38) | 2)</div><div class='add'>+#define MT8167_PIN_38_MRG_DI__FUNC_I2S0_DI (MTK_PIN_NO(38) | 3)</div><div class='add'>+#define MT8167_PIN_38_MRG_DI__FUNC_I2S3_DO (MTK_PIN_NO(38) | 4)</div><div class='add'>+#define MT8167_PIN_38_MRG_DI__FUNC_PCM0_DI (MTK_PIN_NO(38) | 5)</div><div class='add'>+#define MT8167_PIN_38_MRG_DI__FUNC_EXT_MDIO (MTK_PIN_NO(38) | 6)</div><div class='add'>+#define MT8167_PIN_38_MRG_DI__FUNC_DBG_MON_A_4 (MTK_PIN_NO(38) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_39_MRG_DO__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)</div><div class='add'>+#define MT8167_PIN_39_MRG_DO__FUNC_MRG_DO (MTK_PIN_NO(39) | 1)</div><div class='add'>+#define MT8167_PIN_39_MRG_DO__FUNC_DPI_D2 (MTK_PIN_NO(39) | 2)</div><div class='add'>+#define MT8167_PIN_39_MRG_DO__FUNC_I2S0_MCK (MTK_PIN_NO(39) | 3)</div><div class='add'>+#define MT8167_PIN_39_MRG_DO__FUNC_I2S3_MCK (MTK_PIN_NO(39) | 4)</div><div class='add'>+#define MT8167_PIN_39_MRG_DO__FUNC_PCM0_DO (MTK_PIN_NO(39) | 5)</div><div class='add'>+#define MT8167_PIN_39_MRG_DO__FUNC_EXT_MDC (MTK_PIN_NO(39) | 6)</div><div class='add'>+#define MT8167_PIN_39_MRG_DO__FUNC_DBG_MON_A_5 (MTK_PIN_NO(39) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_40_KPROW0__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)</div><div class='add'>+#define MT8167_PIN_40_KPROW0__FUNC_KPROW0 (MTK_PIN_NO(40) | 1)</div><div class='add'>+#define MT8167_PIN_40_KPROW0__FUNC_IMG_TEST_CK (MTK_PIN_NO(40) | 4)</div><div class='add'>+#define MT8167_PIN_40_KPROW0__FUNC_DBG_MON_B_4 (MTK_PIN_NO(40) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_41_KPROW1__FUNC_GPIO41 (MTK_PIN_NO(41) | 0)</div><div class='add'>+#define MT8167_PIN_41_KPROW1__FUNC_KPROW1 (MTK_PIN_NO(41) | 1)</div><div class='add'>+#define MT8167_PIN_41_KPROW1__FUNC_IDDIG (MTK_PIN_NO(41) | 2)</div><div class='add'>+#define MT8167_PIN_41_KPROW1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(41) | 3)</div><div class='add'>+#define MT8167_PIN_41_KPROW1__FUNC_MFG_TEST_CK (MTK_PIN_NO(41) | 4)</div><div class='add'>+#define MT8167_PIN_41_KPROW1__FUNC_DBG_MON_B_5 (MTK_PIN_NO(41) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_42_KPCOL0__FUNC_GPIO42 (MTK_PIN_NO(42) | 0)</div><div class='add'>+#define MT8167_PIN_42_KPCOL0__FUNC_KPCOL0 (MTK_PIN_NO(42) | 1)</div><div class='add'>+#define MT8167_PIN_42_KPCOL0__FUNC_DBG_MON_B_6 (MTK_PIN_NO(42) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_43_KPCOL1__FUNC_GPIO43 (MTK_PIN_NO(43) | 0)</div><div class='add'>+#define MT8167_PIN_43_KPCOL1__FUNC_KPCOL1 (MTK_PIN_NO(43) | 1)</div><div class='add'>+#define MT8167_PIN_43_KPCOL1__FUNC_USB_DRVVBUS (MTK_PIN_NO(43) | 2)</div><div class='add'>+#define MT8167_PIN_43_KPCOL1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(43) | 3)</div><div class='add'>+#define MT8167_PIN_43_KPCOL1__FUNC_TSF_IN (MTK_PIN_NO(43) | 4)</div><div class='add'>+#define MT8167_PIN_43_KPCOL1__FUNC_DFD_NTRST_XI (MTK_PIN_NO(43) | 5)</div><div class='add'>+#define MT8167_PIN_43_KPCOL1__FUNC_UDI_NTRST_XI (MTK_PIN_NO(43) | 6)</div><div class='add'>+#define MT8167_PIN_43_KPCOL1__FUNC_DBG_MON_B_7 (MTK_PIN_NO(43) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_44_JTMS__FUNC_GPIO44 (MTK_PIN_NO(44) | 0)</div><div class='add'>+#define MT8167_PIN_44_JTMS__FUNC_JTMS (MTK_PIN_NO(44) | 1)</div><div class='add'>+#define MT8167_PIN_44_JTMS__FUNC_CONN_MCU_TMS (MTK_PIN_NO(44) | 2)</div><div class='add'>+#define MT8167_PIN_44_JTMS__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(44) | 3)</div><div class='add'>+#define MT8167_PIN_44_JTMS__FUNC_GPUDFD_TMS_XI (MTK_PIN_NO(44) | 4)</div><div class='add'>+#define MT8167_PIN_44_JTMS__FUNC_DFD_TMS_XI (MTK_PIN_NO(44) | 5)</div><div class='add'>+#define MT8167_PIN_44_JTMS__FUNC_UDI_TMS_XI (MTK_PIN_NO(44) | 6)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_45_JTCK__FUNC_GPIO45 (MTK_PIN_NO(45) | 0)</div><div class='add'>+#define MT8167_PIN_45_JTCK__FUNC_JTCK (MTK_PIN_NO(45) | 1)</div><div class='add'>+#define MT8167_PIN_45_JTCK__FUNC_CONN_MCU_TCK (MTK_PIN_NO(45) | 2)</div><div class='add'>+#define MT8167_PIN_45_JTCK__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(45) | 3)</div><div class='add'>+#define MT8167_PIN_45_JTCK__FUNC_GPUDFD_TCK_XI (MTK_PIN_NO(45) | 4)</div><div class='add'>+#define MT8167_PIN_45_JTCK__FUNC_DFD_TCK_XI (MTK_PIN_NO(45) | 5)</div><div class='add'>+#define MT8167_PIN_45_JTCK__FUNC_UDI_TCK_XI (MTK_PIN_NO(45) | 6)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_46_JTDI__FUNC_GPIO46 (MTK_PIN_NO(46) | 0)</div><div class='add'>+#define MT8167_PIN_46_JTDI__FUNC_JTDI (MTK_PIN_NO(46) | 1)</div><div class='add'>+#define MT8167_PIN_46_JTDI__FUNC_CONN_MCU_TDI (MTK_PIN_NO(46) | 2)</div><div class='add'>+#define MT8167_PIN_46_JTDI__FUNC_GPUDFD_TDI_XI (MTK_PIN_NO(46) | 4)</div><div class='add'>+#define MT8167_PIN_46_JTDI__FUNC_DFD_TDI_XI (MTK_PIN_NO(46) | 5)</div><div class='add'>+#define MT8167_PIN_46_JTDI__FUNC_UDI_TDI_XI (MTK_PIN_NO(46) | 6)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_47_JTDO__FUNC_GPIO47 (MTK_PIN_NO(47) | 0)</div><div class='add'>+#define MT8167_PIN_47_JTDO__FUNC_JTDO (MTK_PIN_NO(47) | 1)</div><div class='add'>+#define MT8167_PIN_47_JTDO__FUNC_CONN_MCU_TDO (MTK_PIN_NO(47) | 2)</div><div class='add'>+#define MT8167_PIN_47_JTDO__FUNC_GPUDFD_TDO (MTK_PIN_NO(47) | 4)</div><div class='add'>+#define MT8167_PIN_47_JTDO__FUNC_DFD_TDO (MTK_PIN_NO(47) | 5)</div><div class='add'>+#define MT8167_PIN_47_JTDO__FUNC_UDI_TDO (MTK_PIN_NO(47) | 6)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_48_SPI_CS__FUNC_GPIO48 (MTK_PIN_NO(48) | 0)</div><div class='add'>+#define MT8167_PIN_48_SPI_CS__FUNC_SPI_CSB (MTK_PIN_NO(48) | 1)</div><div class='add'>+#define MT8167_PIN_48_SPI_CS__FUNC_I2S0_DI (MTK_PIN_NO(48) | 3)</div><div class='add'>+#define MT8167_PIN_48_SPI_CS__FUNC_I2S2_BCK (MTK_PIN_NO(48) | 4)</div><div class='add'>+#define MT8167_PIN_48_SPI_CS__FUNC_DBG_MON_A_23 (MTK_PIN_NO(48) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_49_SPI_CK__FUNC_GPIO49 (MTK_PIN_NO(49) | 0)</div><div class='add'>+#define MT8167_PIN_49_SPI_CK__FUNC_SPI_CLK (MTK_PIN_NO(49) | 1)</div><div class='add'>+#define MT8167_PIN_49_SPI_CK__FUNC_I2S0_LRCK (MTK_PIN_NO(49) | 3)</div><div class='add'>+#define MT8167_PIN_49_SPI_CK__FUNC_I2S2_DI (MTK_PIN_NO(49) | 4)</div><div class='add'>+#define MT8167_PIN_49_SPI_CK__FUNC_DBG_MON_A_24 (MTK_PIN_NO(49) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_50_SPI_MI__FUNC_GPIO50 (MTK_PIN_NO(50) | 0)</div><div class='add'>+#define MT8167_PIN_50_SPI_MI__FUNC_SPI_MI (MTK_PIN_NO(50) | 1)</div><div class='add'>+#define MT8167_PIN_50_SPI_MI__FUNC_SPI_MO (MTK_PIN_NO(50) | 2)</div><div class='add'>+#define MT8167_PIN_50_SPI_MI__FUNC_I2S0_BCK (MTK_PIN_NO(50) | 3)</div><div class='add'>+#define MT8167_PIN_50_SPI_MI__FUNC_I2S2_LRCK (MTK_PIN_NO(50) | 4)</div><div class='add'>+#define MT8167_PIN_50_SPI_MI__FUNC_DBG_MON_A_25 (MTK_PIN_NO(50) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_51_SPI_MO__FUNC_GPIO51 (MTK_PIN_NO(51) | 0)</div><div class='add'>+#define MT8167_PIN_51_SPI_MO__FUNC_SPI_MO (MTK_PIN_NO(51) | 1)</div><div class='add'>+#define MT8167_PIN_51_SPI_MO__FUNC_SPI_MI (MTK_PIN_NO(51) | 2)</div><div class='add'>+#define MT8167_PIN_51_SPI_MO__FUNC_I2S0_MCK (MTK_PIN_NO(51) | 3)</div><div class='add'>+#define MT8167_PIN_51_SPI_MO__FUNC_I2S2_MCK (MTK_PIN_NO(51) | 4)</div><div class='add'>+#define MT8167_PIN_51_SPI_MO__FUNC_DBG_MON_A_26 (MTK_PIN_NO(51) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_52_SDA1__FUNC_GPIO52 (MTK_PIN_NO(52) | 0)</div><div class='add'>+#define MT8167_PIN_52_SDA1__FUNC_SDA1_0 (MTK_PIN_NO(52) | 1)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_53_SCL1__FUNC_GPIO53 (MTK_PIN_NO(53) | 0)</div><div class='add'>+#define MT8167_PIN_53_SCL1__FUNC_SCL1_0 (MTK_PIN_NO(53) | 1)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_54_DISP_PWM__FUNC_GPIO54 (MTK_PIN_NO(54) | 0)</div><div class='add'>+#define MT8167_PIN_54_DISP_PWM__FUNC_DISP_PWM (MTK_PIN_NO(54) | 1)</div><div class='add'>+#define MT8167_PIN_54_DISP_PWM__FUNC_PWM_B (MTK_PIN_NO(54) | 2)</div><div class='add'>+#define MT8167_PIN_54_DISP_PWM__FUNC_DBG_MON_B_2 (MTK_PIN_NO(54) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_55_I2S_DATA_IN__FUNC_GPIO55 (MTK_PIN_NO(55) | 0)</div><div class='add'>+#define MT8167_PIN_55_I2S_DATA_IN__FUNC_I2S0_DI (MTK_PIN_NO(55) | 1)</div><div class='add'>+#define MT8167_PIN_55_I2S_DATA_IN__FUNC_UCTS0 (MTK_PIN_NO(55) | 2)</div><div class='add'>+#define MT8167_PIN_55_I2S_DATA_IN__FUNC_I2S3_DO (MTK_PIN_NO(55) | 3)</div><div class='add'>+#define MT8167_PIN_55_I2S_DATA_IN__FUNC_I2S_8CH_DO1 (MTK_PIN_NO(55) | 4)</div><div class='add'>+#define MT8167_PIN_55_I2S_DATA_IN__FUNC_PWM_A (MTK_PIN_NO(55) | 5)</div><div class='add'>+#define MT8167_PIN_55_I2S_DATA_IN__FUNC_I2S2_BCK (MTK_PIN_NO(55) | 6)</div><div class='add'>+#define MT8167_PIN_55_I2S_DATA_IN__FUNC_DBG_MON_A_28 (MTK_PIN_NO(55) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_56_I2S_LRCK__FUNC_GPIO56 (MTK_PIN_NO(56) | 0)</div><div class='add'>+#define MT8167_PIN_56_I2S_LRCK__FUNC_I2S0_LRCK (MTK_PIN_NO(56) | 1)</div><div class='add'>+#define MT8167_PIN_56_I2S_LRCK__FUNC_I2S3_LRCK (MTK_PIN_NO(56) | 3)</div><div class='add'>+#define MT8167_PIN_56_I2S_LRCK__FUNC_I2S_8CH_LRCK (MTK_PIN_NO(56) | 4)</div><div class='add'>+#define MT8167_PIN_56_I2S_LRCK__FUNC_PWM_B (MTK_PIN_NO(56) | 5)</div><div class='add'>+#define MT8167_PIN_56_I2S_LRCK__FUNC_I2S2_DI (MTK_PIN_NO(56) | 6)</div><div class='add'>+#define MT8167_PIN_56_I2S_LRCK__FUNC_DBG_MON_A_29 (MTK_PIN_NO(56) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_57_I2S_BCK__FUNC_GPIO57 (MTK_PIN_NO(57) | 0)</div><div class='add'>+#define MT8167_PIN_57_I2S_BCK__FUNC_I2S0_BCK (MTK_PIN_NO(57) | 1)</div><div class='add'>+#define MT8167_PIN_57_I2S_BCK__FUNC_URTS0 (MTK_PIN_NO(57) | 2)</div><div class='add'>+#define MT8167_PIN_57_I2S_BCK__FUNC_I2S3_BCK (MTK_PIN_NO(57) | 3)</div><div class='add'>+#define MT8167_PIN_57_I2S_BCK__FUNC_I2S_8CH_BCK (MTK_PIN_NO(57) | 4)</div><div class='add'>+#define MT8167_PIN_57_I2S_BCK__FUNC_PWM_C (MTK_PIN_NO(57) | 5)</div><div class='add'>+#define MT8167_PIN_57_I2S_BCK__FUNC_I2S2_LRCK (MTK_PIN_NO(57) | 6)</div><div class='add'>+#define MT8167_PIN_57_I2S_BCK__FUNC_DBG_MON_A_30 (MTK_PIN_NO(57) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_58_SDA0__FUNC_GPIO58 (MTK_PIN_NO(58) | 0)</div><div class='add'>+#define MT8167_PIN_58_SDA0__FUNC_SDA0_0 (MTK_PIN_NO(58) | 1)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_59_SCL0__FUNC_GPIO59 (MTK_PIN_NO(59) | 0)</div><div class='add'>+#define MT8167_PIN_59_SCL0__FUNC_SCL0_0 (MTK_PIN_NO(59) | 1)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_60_SDA2__FUNC_GPIO60 (MTK_PIN_NO(60) | 0)</div><div class='add'>+#define MT8167_PIN_60_SDA2__FUNC_SDA2_0 (MTK_PIN_NO(60) | 1)</div><div class='add'>+#define MT8167_PIN_60_SDA2__FUNC_PWM_B (MTK_PIN_NO(60) | 2)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_61_SCL2__FUNC_GPIO61 (MTK_PIN_NO(61) | 0)</div><div class='add'>+#define MT8167_PIN_61_SCL2__FUNC_SCL2_0 (MTK_PIN_NO(61) | 1)</div><div class='add'>+#define MT8167_PIN_61_SCL2__FUNC_PWM_C (MTK_PIN_NO(61) | 2)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_62_URXD0__FUNC_GPIO62 (MTK_PIN_NO(62) | 0)</div><div class='add'>+#define MT8167_PIN_62_URXD0__FUNC_URXD0 (MTK_PIN_NO(62) | 1)</div><div class='add'>+#define MT8167_PIN_62_URXD0__FUNC_UTXD0 (MTK_PIN_NO(62) | 2)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_63_UTXD0__FUNC_GPIO63 (MTK_PIN_NO(63) | 0)</div><div class='add'>+#define MT8167_PIN_63_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(63) | 1)</div><div class='add'>+#define MT8167_PIN_63_UTXD0__FUNC_URXD0 (MTK_PIN_NO(63) | 2)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_64_URXD1__FUNC_GPIO64 (MTK_PIN_NO(64) | 0)</div><div class='add'>+#define MT8167_PIN_64_URXD1__FUNC_URXD1 (MTK_PIN_NO(64) | 1)</div><div class='add'>+#define MT8167_PIN_64_URXD1__FUNC_UTXD1 (MTK_PIN_NO(64) | 2)</div><div class='add'>+#define MT8167_PIN_64_URXD1__FUNC_DBG_MON_A_27 (MTK_PIN_NO(64) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_65_UTXD1__FUNC_GPIO65 (MTK_PIN_NO(65) | 0)</div><div class='add'>+#define MT8167_PIN_65_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(65) | 1)</div><div class='add'>+#define MT8167_PIN_65_UTXD1__FUNC_URXD1 (MTK_PIN_NO(65) | 2)</div><div class='add'>+#define MT8167_PIN_65_UTXD1__FUNC_DBG_MON_A_31 (MTK_PIN_NO(65) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_66_LCM_RST__FUNC_GPIO66 (MTK_PIN_NO(66) | 0)</div><div class='add'>+#define MT8167_PIN_66_LCM_RST__FUNC_LCM_RST (MTK_PIN_NO(66) | 1)</div><div class='add'>+#define MT8167_PIN_66_LCM_RST__FUNC_I2S0_MCK (MTK_PIN_NO(66) | 3)</div><div class='add'>+#define MT8167_PIN_66_LCM_RST__FUNC_DBG_MON_B_3 (MTK_PIN_NO(66) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_67_DSI_TE__FUNC_GPIO67 (MTK_PIN_NO(67) | 0)</div><div class='add'>+#define MT8167_PIN_67_DSI_TE__FUNC_DSI_TE (MTK_PIN_NO(67) | 1)</div><div class='add'>+#define MT8167_PIN_67_DSI_TE__FUNC_I2S_8CH_MCK (MTK_PIN_NO(67) | 3)</div><div class='add'>+#define MT8167_PIN_67_DSI_TE__FUNC_DBG_MON_B_14 (MTK_PIN_NO(67) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_68_MSDC2_CMD__FUNC_GPIO68 (MTK_PIN_NO(68) | 0)</div><div class='add'>+#define MT8167_PIN_68_MSDC2_CMD__FUNC_MSDC2_CMD (MTK_PIN_NO(68) | 1)</div><div class='add'>+#define MT8167_PIN_68_MSDC2_CMD__FUNC_I2S_8CH_DO4 (MTK_PIN_NO(68) | 2)</div><div class='add'>+#define MT8167_PIN_68_MSDC2_CMD__FUNC_SDA1_0 (MTK_PIN_NO(68) | 3)</div><div class='add'>+#define MT8167_PIN_68_MSDC2_CMD__FUNC_USB_SDA (MTK_PIN_NO(68) | 5)</div><div class='add'>+#define MT8167_PIN_68_MSDC2_CMD__FUNC_I2S3_BCK (MTK_PIN_NO(68) | 6)</div><div class='add'>+#define MT8167_PIN_68_MSDC2_CMD__FUNC_DBG_MON_B_15 (MTK_PIN_NO(68) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_69_MSDC2_CLK__FUNC_GPIO69 (MTK_PIN_NO(69) | 0)</div><div class='add'>+#define MT8167_PIN_69_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(69) | 1)</div><div class='add'>+#define MT8167_PIN_69_MSDC2_CLK__FUNC_I2S_8CH_DO3 (MTK_PIN_NO(69) | 2)</div><div class='add'>+#define MT8167_PIN_69_MSDC2_CLK__FUNC_SCL1_0 (MTK_PIN_NO(69) | 3)</div><div class='add'>+#define MT8167_PIN_69_MSDC2_CLK__FUNC_DPI_D21 (MTK_PIN_NO(69) | 4)</div><div class='add'>+#define MT8167_PIN_69_MSDC2_CLK__FUNC_USB_SCL (MTK_PIN_NO(69) | 5)</div><div class='add'>+#define MT8167_PIN_69_MSDC2_CLK__FUNC_I2S3_LRCK (MTK_PIN_NO(69) | 6)</div><div class='add'>+#define MT8167_PIN_69_MSDC2_CLK__FUNC_DBG_MON_B_16 (MTK_PIN_NO(69) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_70_MSDC2_DAT0__FUNC_GPIO70 (MTK_PIN_NO(70) | 0)</div><div class='add'>+#define MT8167_PIN_70_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MTK_PIN_NO(70) | 1)</div><div class='add'>+#define MT8167_PIN_70_MSDC2_DAT0__FUNC_I2S_8CH_DO2 (MTK_PIN_NO(70) | 2)</div><div class='add'>+#define MT8167_PIN_70_MSDC2_DAT0__FUNC_DPI_D22 (MTK_PIN_NO(70) | 4)</div><div class='add'>+#define MT8167_PIN_70_MSDC2_DAT0__FUNC_UTXD0 (MTK_PIN_NO(70) | 5)</div><div class='add'>+#define MT8167_PIN_70_MSDC2_DAT0__FUNC_I2S3_DO (MTK_PIN_NO(70) | 6)</div><div class='add'>+#define MT8167_PIN_70_MSDC2_DAT0__FUNC_DBG_MON_B_17 (MTK_PIN_NO(70) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_71_MSDC2_DAT1__FUNC_GPIO71 (MTK_PIN_NO(71) | 0)</div><div class='add'>+#define MT8167_PIN_71_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MTK_PIN_NO(71) | 1)</div><div class='add'>+#define MT8167_PIN_71_MSDC2_DAT1__FUNC_I2S_8CH_DO1 (MTK_PIN_NO(71) | 2)</div><div class='add'>+#define MT8167_PIN_71_MSDC2_DAT1__FUNC_PWM_A (MTK_PIN_NO(71) | 3)</div><div class='add'>+#define MT8167_PIN_71_MSDC2_DAT1__FUNC_I2S3_MCK (MTK_PIN_NO(71) | 4)</div><div class='add'>+#define MT8167_PIN_71_MSDC2_DAT1__FUNC_URXD0 (MTK_PIN_NO(71) | 5)</div><div class='add'>+#define MT8167_PIN_71_MSDC2_DAT1__FUNC_PWM_B (MTK_PIN_NO(71) | 6)</div><div class='add'>+#define MT8167_PIN_71_MSDC2_DAT1__FUNC_DBG_MON_B_18 (MTK_PIN_NO(71) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_72_MSDC2_DAT2__FUNC_GPIO72 (MTK_PIN_NO(72) | 0)</div><div class='add'>+#define MT8167_PIN_72_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MTK_PIN_NO(72) | 1)</div><div class='add'>+#define MT8167_PIN_72_MSDC2_DAT2__FUNC_I2S_8CH_LRCK (MTK_PIN_NO(72) | 2)</div><div class='add'>+#define MT8167_PIN_72_MSDC2_DAT2__FUNC_SDA2_0 (MTK_PIN_NO(72) | 3)</div><div class='add'>+#define MT8167_PIN_72_MSDC2_DAT2__FUNC_DPI_D23 (MTK_PIN_NO(72) | 4)</div><div class='add'>+#define MT8167_PIN_72_MSDC2_DAT2__FUNC_UTXD1 (MTK_PIN_NO(72) | 5)</div><div class='add'>+#define MT8167_PIN_72_MSDC2_DAT2__FUNC_PWM_C (MTK_PIN_NO(72) | 6)</div><div class='add'>+#define MT8167_PIN_72_MSDC2_DAT2__FUNC_DBG_MON_B_19 (MTK_PIN_NO(72) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_73_MSDC2_DAT3__FUNC_GPIO73 (MTK_PIN_NO(73) | 0)</div><div class='add'>+#define MT8167_PIN_73_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MTK_PIN_NO(73) | 1)</div><div class='add'>+#define MT8167_PIN_73_MSDC2_DAT3__FUNC_I2S_8CH_BCK (MTK_PIN_NO(73) | 2)</div><div class='add'>+#define MT8167_PIN_73_MSDC2_DAT3__FUNC_SCL2_0 (MTK_PIN_NO(73) | 3)</div><div class='add'>+#define MT8167_PIN_73_MSDC2_DAT3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(73) | 4)</div><div class='add'>+#define MT8167_PIN_73_MSDC2_DAT3__FUNC_URXD1 (MTK_PIN_NO(73) | 5)</div><div class='add'>+#define MT8167_PIN_73_MSDC2_DAT3__FUNC_PWM_A (MTK_PIN_NO(73) | 6)</div><div class='add'>+#define MT8167_PIN_73_MSDC2_DAT3__FUNC_DBG_MON_B_20 (MTK_PIN_NO(73) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_74_TDN3__FUNC_GPI74 (MTK_PIN_NO(74) | 0)</div><div class='add'>+#define MT8167_PIN_74_TDN3__FUNC_TDN3 (MTK_PIN_NO(74) | 1)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_75_TDP3__FUNC_GPI75 (MTK_PIN_NO(75) | 0)</div><div class='add'>+#define MT8167_PIN_75_TDP3__FUNC_TDP3 (MTK_PIN_NO(75) | 1)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_76_TDN2__FUNC_GPI76 (MTK_PIN_NO(76) | 0)</div><div class='add'>+#define MT8167_PIN_76_TDN2__FUNC_TDN2 (MTK_PIN_NO(76) | 1)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_77_TDP2__FUNC_GPI77 (MTK_PIN_NO(77) | 0)</div><div class='add'>+#define MT8167_PIN_77_TDP2__FUNC_TDP2 (MTK_PIN_NO(77) | 1)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_78_TCN__FUNC_GPI78 (MTK_PIN_NO(78) | 0)</div><div class='add'>+#define MT8167_PIN_78_TCN__FUNC_TCN (MTK_PIN_NO(78) | 1)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_79_TCP__FUNC_GPI79 (MTK_PIN_NO(79) | 0)</div><div class='add'>+#define MT8167_PIN_79_TCP__FUNC_TCP (MTK_PIN_NO(79) | 1)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_80_TDN1__FUNC_GPI80 (MTK_PIN_NO(80) | 0)</div><div class='add'>+#define MT8167_PIN_80_TDN1__FUNC_TDN1 (MTK_PIN_NO(80) | 1)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_81_TDP1__FUNC_GPI81 (MTK_PIN_NO(81) | 0)</div><div class='add'>+#define MT8167_PIN_81_TDP1__FUNC_TDP1 (MTK_PIN_NO(81) | 1)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_82_TDN0__FUNC_GPI82 (MTK_PIN_NO(82) | 0)</div><div class='add'>+#define MT8167_PIN_82_TDN0__FUNC_TDN0 (MTK_PIN_NO(82) | 1)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_83_TDP0__FUNC_GPI83 (MTK_PIN_NO(83) | 0)</div><div class='add'>+#define MT8167_PIN_83_TDP0__FUNC_TDP0 (MTK_PIN_NO(83) | 1)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_84_RDN0__FUNC_GPI84 (MTK_PIN_NO(84) | 0)</div><div class='add'>+#define MT8167_PIN_84_RDN0__FUNC_RDN0 (MTK_PIN_NO(84) | 1)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_85_RDP0__FUNC_GPI85 (MTK_PIN_NO(85) | 0)</div><div class='add'>+#define MT8167_PIN_85_RDP0__FUNC_RDP0 (MTK_PIN_NO(85) | 1)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_86_RDN1__FUNC_GPI86 (MTK_PIN_NO(86) | 0)</div><div class='add'>+#define MT8167_PIN_86_RDN1__FUNC_RDN1 (MTK_PIN_NO(86) | 1)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_87_RDP1__FUNC_GPI87 (MTK_PIN_NO(87) | 0)</div><div class='add'>+#define MT8167_PIN_87_RDP1__FUNC_RDP1 (MTK_PIN_NO(87) | 1)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_88_RCN__FUNC_GPI88 (MTK_PIN_NO(88) | 0)</div><div class='add'>+#define MT8167_PIN_88_RCN__FUNC_RCN (MTK_PIN_NO(88) | 1)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_89_RCP__FUNC_GPI89 (MTK_PIN_NO(89) | 0)</div><div class='add'>+#define MT8167_PIN_89_RCP__FUNC_RCP (MTK_PIN_NO(89) | 1)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_90_RDN2__FUNC_GPI90 (MTK_PIN_NO(90) | 0)</div><div class='add'>+#define MT8167_PIN_90_RDN2__FUNC_RDN2 (MTK_PIN_NO(90) | 1)</div><div class='add'>+#define MT8167_PIN_90_RDN2__FUNC_CMDAT8 (MTK_PIN_NO(90) | 2)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_91_RDP2__FUNC_GPI91 (MTK_PIN_NO(91) | 0)</div><div class='add'>+#define MT8167_PIN_91_RDP2__FUNC_RDP2 (MTK_PIN_NO(91) | 1)</div><div class='add'>+#define MT8167_PIN_91_RDP2__FUNC_CMDAT9 (MTK_PIN_NO(91) | 2)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_92_RDN3__FUNC_GPI92 (MTK_PIN_NO(92) | 0)</div><div class='add'>+#define MT8167_PIN_92_RDN3__FUNC_RDN3 (MTK_PIN_NO(92) | 1)</div><div class='add'>+#define MT8167_PIN_92_RDN3__FUNC_CMDAT4 (MTK_PIN_NO(92) | 2)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_93_RDP3__FUNC_GPI93 (MTK_PIN_NO(93) | 0)</div><div class='add'>+#define MT8167_PIN_93_RDP3__FUNC_RDP3 (MTK_PIN_NO(93) | 1)</div><div class='add'>+#define MT8167_PIN_93_RDP3__FUNC_CMDAT5 (MTK_PIN_NO(93) | 2)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_94_RCN_A__FUNC_GPI94 (MTK_PIN_NO(94) | 0)</div><div class='add'>+#define MT8167_PIN_94_RCN_A__FUNC_RCN_A (MTK_PIN_NO(94) | 1)</div><div class='add'>+#define MT8167_PIN_94_RCN_A__FUNC_CMDAT6 (MTK_PIN_NO(94) | 2)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_95_RCP_A__FUNC_GPI95 (MTK_PIN_NO(95) | 0)</div><div class='add'>+#define MT8167_PIN_95_RCP_A__FUNC_RCP_A (MTK_PIN_NO(95) | 1)</div><div class='add'>+#define MT8167_PIN_95_RCP_A__FUNC_CMDAT7 (MTK_PIN_NO(95) | 2)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_96_RDN1_A__FUNC_GPI96 (MTK_PIN_NO(96) | 0)</div><div class='add'>+#define MT8167_PIN_96_RDN1_A__FUNC_RDN1_A (MTK_PIN_NO(96) | 1)</div><div class='add'>+#define MT8167_PIN_96_RDN1_A__FUNC_CMDAT2 (MTK_PIN_NO(96) | 2)</div><div class='add'>+#define MT8167_PIN_96_RDN1_A__FUNC_CMCSD2 (MTK_PIN_NO(96) | 3)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_97_RDP1_A__FUNC_GPI97 (MTK_PIN_NO(97) | 0)</div><div class='add'>+#define MT8167_PIN_97_RDP1_A__FUNC_RDP1_A (MTK_PIN_NO(97) | 1)</div><div class='add'>+#define MT8167_PIN_97_RDP1_A__FUNC_CMDAT3 (MTK_PIN_NO(97) | 2)</div><div class='add'>+#define MT8167_PIN_97_RDP1_A__FUNC_CMCSD3 (MTK_PIN_NO(97) | 3)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_98_RDN0_A__FUNC_GPI98 (MTK_PIN_NO(98) | 0)</div><div class='add'>+#define MT8167_PIN_98_RDN0_A__FUNC_RDN0_A (MTK_PIN_NO(98) | 1)</div><div class='add'>+#define MT8167_PIN_98_RDN0_A__FUNC_CMHSYNC (MTK_PIN_NO(98) | 2)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_99_RDP0_A__FUNC_GPI99 (MTK_PIN_NO(99) | 0)</div><div class='add'>+#define MT8167_PIN_99_RDP0_A__FUNC_RDP0_A (MTK_PIN_NO(99) | 1)</div><div class='add'>+#define MT8167_PIN_99_RDP0_A__FUNC_CMVSYNC (MTK_PIN_NO(99) | 2)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_100_CMDAT0__FUNC_GPIO100 (MTK_PIN_NO(100) | 0)</div><div class='add'>+#define MT8167_PIN_100_CMDAT0__FUNC_CMDAT0 (MTK_PIN_NO(100) | 1)</div><div class='add'>+#define MT8167_PIN_100_CMDAT0__FUNC_CMCSD0 (MTK_PIN_NO(100) | 2)</div><div class='add'>+#define MT8167_PIN_100_CMDAT0__FUNC_ANT_SEL2 (MTK_PIN_NO(100) | 3)</div><div class='add'>+#define MT8167_PIN_100_CMDAT0__FUNC_TDM_RX_MCK (MTK_PIN_NO(100) | 5)</div><div class='add'>+#define MT8167_PIN_100_CMDAT0__FUNC_DBG_MON_B_21 (MTK_PIN_NO(100) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_101_CMDAT1__FUNC_GPIO101 (MTK_PIN_NO(101) | 0)</div><div class='add'>+#define MT8167_PIN_101_CMDAT1__FUNC_CMDAT1 (MTK_PIN_NO(101) | 1)</div><div class='add'>+#define MT8167_PIN_101_CMDAT1__FUNC_CMCSD1 (MTK_PIN_NO(101) | 2)</div><div class='add'>+#define MT8167_PIN_101_CMDAT1__FUNC_ANT_SEL3 (MTK_PIN_NO(101) | 3)</div><div class='add'>+#define MT8167_PIN_101_CMDAT1__FUNC_CMFLASH (MTK_PIN_NO(101) | 4)</div><div class='add'>+#define MT8167_PIN_101_CMDAT1__FUNC_TDM_RX_BCK (MTK_PIN_NO(101) | 5)</div><div class='add'>+#define MT8167_PIN_101_CMDAT1__FUNC_DBG_MON_B_22 (MTK_PIN_NO(101) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_102_CMMCLK__FUNC_GPIO102 (MTK_PIN_NO(102) | 0)</div><div class='add'>+#define MT8167_PIN_102_CMMCLK__FUNC_CMMCLK (MTK_PIN_NO(102) | 1)</div><div class='add'>+#define MT8167_PIN_102_CMMCLK__FUNC_ANT_SEL4 (MTK_PIN_NO(102) | 3)</div><div class='add'>+#define MT8167_PIN_102_CMMCLK__FUNC_TDM_RX_LRCK (MTK_PIN_NO(102) | 5)</div><div class='add'>+#define MT8167_PIN_102_CMMCLK__FUNC_DBG_MON_B_23 (MTK_PIN_NO(102) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_103_CMPCLK__FUNC_GPIO103 (MTK_PIN_NO(103) | 0)</div><div class='add'>+#define MT8167_PIN_103_CMPCLK__FUNC_CMPCLK (MTK_PIN_NO(103) | 1)</div><div class='add'>+#define MT8167_PIN_103_CMPCLK__FUNC_CMCSK (MTK_PIN_NO(103) | 2)</div><div class='add'>+#define MT8167_PIN_103_CMPCLK__FUNC_ANT_SEL5 (MTK_PIN_NO(103) | 3)</div><div class='add'>+#define MT8167_PIN_103_CMPCLK__FUNC_TDM_RX_DI (MTK_PIN_NO(103) | 5)</div><div class='add'>+#define MT8167_PIN_103_CMPCLK__FUNC_DBG_MON_B_24 (MTK_PIN_NO(103) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_104_MSDC1_CMD__FUNC_GPIO104 (MTK_PIN_NO(104) | 0)</div><div class='add'>+#define MT8167_PIN_104_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(104) | 1)</div><div class='add'>+#define MT8167_PIN_104_MSDC1_CMD__FUNC_SQICS (MTK_PIN_NO(104) | 4)</div><div class='add'>+#define MT8167_PIN_104_MSDC1_CMD__FUNC_DBG_MON_B_25 (MTK_PIN_NO(104) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_105_MSDC1_CLK__FUNC_GPIO105 (MTK_PIN_NO(105) | 0)</div><div class='add'>+#define MT8167_PIN_105_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(105) | 1)</div><div class='add'>+#define MT8167_PIN_105_MSDC1_CLK__FUNC_UDI_NTRST_XI (MTK_PIN_NO(105) | 2)</div><div class='add'>+#define MT8167_PIN_105_MSDC1_CLK__FUNC_DFD_NTRST_XI (MTK_PIN_NO(105) | 3)</div><div class='add'>+#define MT8167_PIN_105_MSDC1_CLK__FUNC_SQISO (MTK_PIN_NO(105) | 4)</div><div class='add'>+#define MT8167_PIN_105_MSDC1_CLK__FUNC_GPUEJ_NTRST_XI (MTK_PIN_NO(105) | 5)</div><div class='add'>+#define MT8167_PIN_105_MSDC1_CLK__FUNC_DBG_MON_B_26 (MTK_PIN_NO(105) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_106_MSDC1_DAT0__FUNC_GPIO106 (MTK_PIN_NO(106) | 0)</div><div class='add'>+#define MT8167_PIN_106_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(106) | 1)</div><div class='add'>+#define MT8167_PIN_106_MSDC1_DAT0__FUNC_UDI_TMS_XI (MTK_PIN_NO(106) | 2)</div><div class='add'>+#define MT8167_PIN_106_MSDC1_DAT0__FUNC_DFD_TMS_XI (MTK_PIN_NO(106) | 3)</div><div class='add'>+#define MT8167_PIN_106_MSDC1_DAT0__FUNC_SQISI (MTK_PIN_NO(106) | 4)</div><div class='add'>+#define MT8167_PIN_106_MSDC1_DAT0__FUNC_GPUEJ_TMS_XI (MTK_PIN_NO(106) | 5)</div><div class='add'>+#define MT8167_PIN_106_MSDC1_DAT0__FUNC_DBG_MON_B_27 (MTK_PIN_NO(106) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_107_MSDC1_DAT1__FUNC_GPIO107 (MTK_PIN_NO(107) | 0)</div><div class='add'>+#define MT8167_PIN_107_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(107) | 1)</div><div class='add'>+#define MT8167_PIN_107_MSDC1_DAT1__FUNC_UDI_TCK_XI (MTK_PIN_NO(107) | 2)</div><div class='add'>+#define MT8167_PIN_107_MSDC1_DAT1__FUNC_DFD_TCK_XI (MTK_PIN_NO(107) | 3)</div><div class='add'>+#define MT8167_PIN_107_MSDC1_DAT1__FUNC_SQIWP (MTK_PIN_NO(107) | 4)</div><div class='add'>+#define MT8167_PIN_107_MSDC1_DAT1__FUNC_GPUEJ_TCK_XI (MTK_PIN_NO(107) | 5)</div><div class='add'>+#define MT8167_PIN_107_MSDC1_DAT1__FUNC_DBG_MON_B_28 (MTK_PIN_NO(107) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_108_MSDC1_DAT2__FUNC_GPIO108 (MTK_PIN_NO(108) | 0)</div><div class='add'>+#define MT8167_PIN_108_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(108) | 1)</div><div class='add'>+#define MT8167_PIN_108_MSDC1_DAT2__FUNC_UDI_TDI_XI (MTK_PIN_NO(108) | 2)</div><div class='add'>+#define MT8167_PIN_108_MSDC1_DAT2__FUNC_DFD_TDI_XI (MTK_PIN_NO(108) | 3)</div><div class='add'>+#define MT8167_PIN_108_MSDC1_DAT2__FUNC_SQIRST (MTK_PIN_NO(108) | 4)</div><div class='add'>+#define MT8167_PIN_108_MSDC1_DAT2__FUNC_GPUEJ_TDI_XI (MTK_PIN_NO(108) | 5)</div><div class='add'>+#define MT8167_PIN_108_MSDC1_DAT2__FUNC_DBG_MON_B_29 (MTK_PIN_NO(108) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_109_MSDC1_DAT3__FUNC_GPIO109 (MTK_PIN_NO(109) | 0)</div><div class='add'>+#define MT8167_PIN_109_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(109) | 1)</div><div class='add'>+#define MT8167_PIN_109_MSDC1_DAT3__FUNC_UDI_TDO (MTK_PIN_NO(109) | 2)</div><div class='add'>+#define MT8167_PIN_109_MSDC1_DAT3__FUNC_DFD_TDO (MTK_PIN_NO(109) | 3)</div><div class='add'>+#define MT8167_PIN_109_MSDC1_DAT3__FUNC_SQICK (MTK_PIN_NO(109) | 4)</div><div class='add'>+#define MT8167_PIN_109_MSDC1_DAT3__FUNC_GPUEJ_TDO (MTK_PIN_NO(109) | 5)</div><div class='add'>+#define MT8167_PIN_109_MSDC1_DAT3__FUNC_DBG_MON_B_30 (MTK_PIN_NO(109) | 7)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_110_MSDC0_DAT7__FUNC_GPIO110 (MTK_PIN_NO(110) | 0)</div><div class='add'>+#define MT8167_PIN_110_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(110) | 1)</div><div class='add'>+#define MT8167_PIN_110_MSDC0_DAT7__FUNC_NLD7 (MTK_PIN_NO(110) | 4)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_111_MSDC0_DAT6__FUNC_GPIO111 (MTK_PIN_NO(111) | 0)</div><div class='add'>+#define MT8167_PIN_111_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(111) | 1)</div><div class='add'>+#define MT8167_PIN_111_MSDC0_DAT6__FUNC_NLD6 (MTK_PIN_NO(111) | 4)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_112_MSDC0_DAT5__FUNC_GPIO112 (MTK_PIN_NO(112) | 0)</div><div class='add'>+#define MT8167_PIN_112_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(112) | 1)</div><div class='add'>+#define MT8167_PIN_112_MSDC0_DAT5__FUNC_NLD4 (MTK_PIN_NO(112) | 4)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_113_MSDC0_DAT4__FUNC_GPIO113 (MTK_PIN_NO(113) | 0)</div><div class='add'>+#define MT8167_PIN_113_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(113) | 1)</div><div class='add'>+#define MT8167_PIN_113_MSDC0_DAT4__FUNC_NLD3 (MTK_PIN_NO(113) | 4)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_114_MSDC0_RSTB__FUNC_GPIO114 (MTK_PIN_NO(114) | 0)</div><div class='add'>+#define MT8167_PIN_114_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(114) | 1)</div><div class='add'>+#define MT8167_PIN_114_MSDC0_RSTB__FUNC_NLD0 (MTK_PIN_NO(114) | 4)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_115_MSDC0_CMD__FUNC_GPIO115 (MTK_PIN_NO(115) | 0)</div><div class='add'>+#define MT8167_PIN_115_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(115) | 1)</div><div class='add'>+#define MT8167_PIN_115_MSDC0_CMD__FUNC_NALE (MTK_PIN_NO(115) | 4)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_116_MSDC0_CLK__FUNC_GPIO116 (MTK_PIN_NO(116) | 0)</div><div class='add'>+#define MT8167_PIN_116_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(116) | 1)</div><div class='add'>+#define MT8167_PIN_116_MSDC0_CLK__FUNC_NWEB (MTK_PIN_NO(116) | 4)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_117_MSDC0_DAT3__FUNC_GPIO117 (MTK_PIN_NO(117) | 0)</div><div class='add'>+#define MT8167_PIN_117_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(117) | 1)</div><div class='add'>+#define MT8167_PIN_117_MSDC0_DAT3__FUNC_NLD1 (MTK_PIN_NO(117) | 4)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_118_MSDC0_DAT2__FUNC_GPIO118 (MTK_PIN_NO(118) | 0)</div><div class='add'>+#define MT8167_PIN_118_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(118) | 1)</div><div class='add'>+#define MT8167_PIN_118_MSDC0_DAT2__FUNC_NLD5 (MTK_PIN_NO(118) | 4)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_119_MSDC0_DAT1__FUNC_GPIO119 (MTK_PIN_NO(119) | 0)</div><div class='add'>+#define MT8167_PIN_119_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(119) | 1)</div><div class='add'>+#define MT8167_PIN_119_MSDC0_DAT1__FUNC_NLD8 (MTK_PIN_NO(119) | 4)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_120_MSDC0_DAT0__FUNC_GPIO120 (MTK_PIN_NO(120) | 0)</div><div class='add'>+#define MT8167_PIN_120_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(120) | 1)</div><div class='add'>+#define MT8167_PIN_120_MSDC0_DAT0__FUNC_WATCHDOG (MTK_PIN_NO(120) | 4)</div><div class='add'>+#define MT8167_PIN_120_MSDC0_DAT0__FUNC_NLD2 (MTK_PIN_NO(120) | 5)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_121_CEC__FUNC_GPIO121 (MTK_PIN_NO(121) | 0)</div><div class='add'>+#define MT8167_PIN_121_CEC__FUNC_CEC (MTK_PIN_NO(121) | 1)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_122_HTPLG__FUNC_GPIO122 (MTK_PIN_NO(122) | 0)</div><div class='add'>+#define MT8167_PIN_122_HTPLG__FUNC_HTPLG (MTK_PIN_NO(122) | 1)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_123_HDMISCK__FUNC_GPIO123 (MTK_PIN_NO(123) | 0)</div><div class='add'>+#define MT8167_PIN_123_HDMISCK__FUNC_HDMISCK (MTK_PIN_NO(123) | 1)</div><div class='add'>+</div><div class='add'>+#define MT8167_PIN_124_HDMISD__FUNC_GPIO124 (MTK_PIN_NO(124) | 0)</div><div class='add'>+#define MT8167_PIN_124_HDMISD__FUNC_HDMISD (MTK_PIN_NO(124) | 1)</div><div class='add'>+</div><div class='add'>+#endif /* __DTS_MT8167_PINFUNC_H */</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts<br/>new file mode 100644<br/>index 000000000000..ebf1a358f42a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts</a></div><div class='hunk'>@@ -0,0 +1,21 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2020 BayLibre, SAS.</div><div class='add'>+ * Author: Fabien Parent &lt;fparent@baylibre.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "mt8167.dtsi"</div><div class='add'>+#include "pumpkin-common.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Pumpkin MT8167";</div><div class='add'>+	chassis-type = "embedded";</div><div class='add'>+	compatible = "mediatek,mt8167-pumpkin", "mediatek,mt8167";</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0 0x40000000 0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi<br/>new file mode 100644<br/>index 000000000000..2374c0953057<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8167.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8167.dtsi</a></div><div class='hunk'>@@ -0,0 +1,180 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2020 MediaTek Inc.</div><div class='add'>+ * Copyright (c) 2020 BayLibre, SAS.</div><div class='add'>+ * Author: Fabien Parent &lt;fparent@baylibre.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/mt8167-clk.h&gt;</div><div class='add'>+#include &lt;dt-bindings/memory/mt8167-larb-port.h&gt;</div><div class='add'>+#include &lt;dt-bindings/power/mt8167-power.h&gt;</div><div class='add'>+</div><div class='add'>+#include "mt8167-pinfunc.h"</div><div class='add'>+</div><div class='add'>+#include "mt8516.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "mediatek,mt8167";</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='add'>+		topckgen: topckgen@10000000 {</div><div class='add'>+			compatible = "mediatek,mt8167-topckgen", "syscon";</div><div class='add'>+			reg = &lt;0 0x10000000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		infracfg: infracfg@10001000 {</div><div class='add'>+			compatible = "mediatek,mt8167-infracfg", "syscon";</div><div class='add'>+			reg = &lt;0 0x10001000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		apmixedsys: apmixedsys@10018000 {</div><div class='add'>+			compatible = "mediatek,mt8167-apmixedsys", "syscon";</div><div class='add'>+			reg = &lt;0 0x10018000 0 0x710&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		scpsys: syscon@10006000 {</div><div class='add'>+			compatible = "mediatek,mt8167-scpsys", "syscon", "simple-mfd";</div><div class='add'>+			reg = &lt;0 0x10006000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			spm: power-controller {</div><div class='add'>+				compatible = "mediatek,mt8167-power-controller";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				/* power domains of the SoC */</div><div class='add'>+				power-domain@MT8167_POWER_DOMAIN_MM {</div><div class='add'>+					reg = &lt;MT8167_POWER_DOMAIN_MM&gt;;</div><div class='add'>+					clocks = &lt;&amp;topckgen CLK_TOP_SMI_MM&gt;;</div><div class='add'>+					clock-names = "mm";</div><div class='add'>+					#power-domain-cells = &lt;0&gt;;</div><div class='add'>+					mediatek,infracfg = &lt;&amp;infracfg&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				power-domain@MT8167_POWER_DOMAIN_VDEC {</div><div class='add'>+					reg = &lt;MT8167_POWER_DOMAIN_VDEC&gt;;</div><div class='add'>+					clocks = &lt;&amp;topckgen CLK_TOP_SMI_MM&gt;,</div><div class='add'>+						 &lt;&amp;topckgen CLK_TOP_RG_VDEC&gt;;</div><div class='add'>+					clock-names = "mm", "vdec";</div><div class='add'>+					#power-domain-cells = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				power-domain@MT8167_POWER_DOMAIN_ISP {</div><div class='add'>+					reg = &lt;MT8167_POWER_DOMAIN_ISP&gt;;</div><div class='add'>+					clocks = &lt;&amp;topckgen CLK_TOP_SMI_MM&gt;;</div><div class='add'>+					clock-names = "mm";</div><div class='add'>+					#power-domain-cells = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				power-domain@MT8167_POWER_DOMAIN_MFG_ASYNC {</div><div class='add'>+					reg = &lt;MT8167_POWER_DOMAIN_MFG_ASYNC&gt;;</div><div class='add'>+					clocks = &lt;&amp;topckgen CLK_TOP_RG_AXI_MFG&gt;,</div><div class='add'>+						 &lt;&amp;topckgen CLK_TOP_RG_SLOW_MFG&gt;;</div><div class='add'>+					clock-names = "axi_mfg", "mfg";</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+					#power-domain-cells = &lt;1&gt;;</div><div class='add'>+					mediatek,infracfg = &lt;&amp;infracfg&gt;;</div><div class='add'>+</div><div class='add'>+					power-domain@MT8167_POWER_DOMAIN_MFG_2D {</div><div class='add'>+						reg = &lt;MT8167_POWER_DOMAIN_MFG_2D&gt;;</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+						#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						power-domain@MT8167_POWER_DOMAIN_MFG {</div><div class='add'>+							reg = &lt;MT8167_POWER_DOMAIN_MFG&gt;;</div><div class='add'>+							#power-domain-cells = &lt;0&gt;;</div><div class='add'>+							mediatek,infracfg = &lt;&amp;infracfg&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				power-domain@MT8167_POWER_DOMAIN_CONN {</div><div class='add'>+					reg = &lt;MT8167_POWER_DOMAIN_CONN&gt;;</div><div class='add'>+					#power-domain-cells = &lt;0&gt;;</div><div class='add'>+					mediatek,infracfg = &lt;&amp;infracfg&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		imgsys: syscon@15000000 {</div><div class='add'>+			compatible = "mediatek,mt8167-imgsys", "syscon";</div><div class='add'>+			reg = &lt;0 0x15000000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdecsys: syscon@16000000 {</div><div class='add'>+			compatible = "mediatek,mt8167-vdecsys", "syscon";</div><div class='add'>+			reg = &lt;0 0x16000000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pio: pinctrl@1000b000 {</div><div class='add'>+			compatible = "mediatek,mt8167-pinctrl";</div><div class='add'>+			reg = &lt;0 0x1000b000 0 0x1000&gt;;</div><div class='add'>+			mediatek,pctl-regmap = &lt;&amp;syscfg_pctl&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmsys: syscon@14000000 {</div><div class='add'>+			compatible = "mediatek,mt8167-mmsys", "syscon";</div><div class='add'>+			reg = &lt;0 0x14000000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smi_common: smi@14017000 {</div><div class='add'>+			compatible = "mediatek,mt8167-smi-common";</div><div class='add'>+			reg = &lt;0 0x14017000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_SMI_COMMON&gt;,</div><div class='add'>+				 &lt;&amp;mmsys CLK_MM_SMI_COMMON&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8167_POWER_DOMAIN_MM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb0: larb@14016000 {</div><div class='add'>+			compatible = "mediatek,mt8167-smi-larb";</div><div class='add'>+			reg = &lt;0 0x14016000 0 0x1000&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_SMI_LARB0&gt;,</div><div class='add'>+				 &lt;&amp;mmsys CLK_MM_SMI_LARB0&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8167_POWER_DOMAIN_MM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb1: larb@15001000 {</div><div class='add'>+			compatible = "mediatek,mt8167-smi-larb";</div><div class='add'>+			reg = &lt;0 0x15001000 0 0x1000&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+			clocks = &lt;&amp;imgsys CLK_IMG_LARB1_SMI&gt;,</div><div class='add'>+				 &lt;&amp;imgsys CLK_IMG_LARB1_SMI&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8167_POWER_DOMAIN_ISP&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb2: larb@16010000 {</div><div class='add'>+			compatible = "mediatek,mt8167-smi-larb";</div><div class='add'>+			reg = &lt;0 0x16010000 0 0x1000&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdecsys CLK_VDEC_CKEN&gt;,</div><div class='add'>+				 &lt;&amp;vdecsys CLK_VDEC_LARB1_CKEN&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8167_POWER_DOMAIN_VDEC&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		iommu: m4u@10203000 {</div><div class='add'>+			compatible = "mediatek,mt8167-m4u";</div><div class='add'>+			reg = &lt;0 0x10203000 0 0x1000&gt;;</div><div class='add'>+			mediatek,larbs = &lt;&amp;larb0&gt;, &lt;&amp;larb1&gt;, &lt;&amp;larb2&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 121 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			#iommu-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts<br/>new file mode 100644<br/>index 000000000000..1c9fc791bdfc<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts</a></div><div class='hunk'>@@ -0,0 +1,28 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2019 MediaTek Inc.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8173-elm-hana.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google Hanawl";</div><div class='add'>+	chassis-type = "laptop";</div><div class='add'>+	compatible = "google,hana-rev7", "mediatek,mt8173";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu_thermal {</div><div class='add'>+	trips {</div><div class='add'>+		cpu_crit: cpu-crit0 {</div><div class='add'>+			temperature = &lt;100000&gt;;</div><div class='add'>+			type = "critical";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio_keys {</div><div class='add'>+	/delete-node/switch-tablet-mode;</div><div class='add'>+	/delete-node/switch-volume-down;</div><div class='add'>+	/delete-node/switch-volume-up;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts<br/>new file mode 100644<br/>index 000000000000..fcf0cb76a87c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts</a></div><div class='hunk'>@@ -0,0 +1,15 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2016 MediaTek Inc.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8173-elm-hana.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google Hana";</div><div class='add'>+	chassis-type = "laptop";</div><div class='add'>+	compatible = "google,hana-rev6", "google,hana-rev5",</div><div class='add'>+		     "google,hana-rev4", "google,hana-rev3",</div><div class='add'>+		     "google,hana", "mediatek,mt8173";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi<br/>new file mode 100644<br/>index 000000000000..dfc5c2f0ddef<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi</a></div><div class='hunk'>@@ -0,0 +1,98 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2016 MediaTek Inc.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "mt8173-elm.dtsi"</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	clock-frequency = &lt;200000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	touchscreen2: touchscreen@34 {</div><div class='add'>+		compatible = "melfas,mip4_ts";</div><div class='add'>+		reg = &lt;0x34&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 88 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		status = "fail-needs-probe";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Lenovo 100e Chromebook 2nd Gen (MTK) and Lenovo 300e Chromebook 2nd</div><div class='add'>+	 * Gen (MTK) are using synaptics touchscreen (hid-over-i2c driver) as a</div><div class='add'>+	 * second source touchscreen.</div><div class='add'>+	 */</div><div class='add'>+	touchscreen3: touchscreen@20 {</div><div class='add'>+		compatible = "hid-over-i2c";</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+		hid-descr-addr = &lt;0x0020&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 88 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		status = "fail-needs-probe";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Lenovo Ideapad C330 uses G2Touch touchscreen as a 2nd source touchscreen */</div><div class='add'>+	touchscreen@40 {</div><div class='add'>+		compatible = "hid-over-i2c";</div><div class='add'>+		reg = &lt;0x40&gt;;</div><div class='add'>+		hid-descr-addr = &lt;0x0001&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;pio&gt;;</div><div class='add'>+		interrupts = &lt;88 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		status = "fail-needs-probe";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	/*</div><div class='add'>+	 * Lenovo 100e Chromebook 2nd Gen (MTK) and Lenovo 300e Chromebook 2nd</div><div class='add'>+	 * Gen (MTK) are using synaptics trackpad (hid-over-i2c driver) as a</div><div class='add'>+	 * second source trackpad.</div><div class='add'>+	 */</div><div class='add'>+	trackpad2: trackpad@2c {</div><div class='add'>+		compatible = "hid-over-i2c";</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 117 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;trackpad_irq&gt;;</div><div class='add'>+		reg = &lt;0x2c&gt;;</div><div class='add'>+		hid-descr-addr = &lt;0x0020&gt;;</div><div class='add'>+		/*</div><div class='add'>+		 * The trackpad needs a post-power-on delay of 100ms,</div><div class='add'>+		 * but at time of writing, the power supply for it on</div><div class='add'>+		 * this board is always on. The delay is therefore not</div><div class='add'>+		 * added to avoid impacting the readiness of the</div><div class='add'>+		 * trackpad.</div><div class='add'>+		 */</div><div class='add'>+		vdd-supply = &lt;&amp;mt6397_vgp6_reg&gt;;</div><div class='add'>+		wakeup-source;</div><div class='add'>+		status = "fail-needs-probe";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc1 {</div><div class='add'>+	wp-gpios = &lt;&amp;pio 42 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	hdmi_mux_pins: hdmi_mux_pins {</div><div class='add'>+		pins2 {</div><div class='add'>+			pinmux = &lt;MT8173_PIN_98_URTS1__FUNC_GPIO98&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc1_pins_default: mmc1default {</div><div class='add'>+		pins_wp {</div><div class='add'>+			pinmux = &lt;MT8173_PIN_42_DSI_TE__FUNC_GPIO42&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;touchscreen {</div><div class='add'>+	status = "fail-needs-probe";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;trackpad {</div><div class='add'>+	status = "fail-needs-probe";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dts b/arch/arm64/boot/dts/mediatek/mt8173-elm.dts<br/>new file mode 100644<br/>index 000000000000..2390d04204e8<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8173-elm.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8173-elm.dts</a></div><div class='hunk'>@@ -0,0 +1,15 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2016 MediaTek Inc.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8173-elm.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google Elm";</div><div class='add'>+	chassis-type = "laptop";</div><div class='add'>+	compatible = "google,elm-rev8", "google,elm-rev7", "google,elm-rev6",</div><div class='add'>+		     "google,elm-rev5", "google,elm-rev4", "google,elm-rev3",</div><div class='add'>+		     "google,elm", "mediatek,mt8173";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi<br/>new file mode 100644<br/>index 000000000000..0d995b342d46<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi</a></div><div class='hunk'>@@ -0,0 +1,1168 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2016 MediaTek Inc.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/linux-event-codes.h&gt;</div><div class='add'>+#include &lt;dt-bindings/regulator/dlg,da9211-regulator.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include "mt8173.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		mmc0 = &amp;mmc0;</div><div class='add'>+		mmc1 = &amp;mmc1;</div><div class='add'>+		mmc2 = &amp;mmc3;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0 0x40000000 0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	backlight: backlight {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		pwms = &lt;&amp;pwm0 0 1000000&gt;;</div><div class='add'>+		power-supply = &lt;&amp;bl_fixed_reg&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;pio 95 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;panel_backlight_en_pins&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bl_fixed_reg: fixedregulator2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "bl_fixed";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		startup-delay-us = &lt;1000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;pio 32 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;bl_fixed_pins&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio_keys: gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;gpio_keys_pins&gt;;</div><div class='add'>+</div><div class='add'>+		switch-lid {</div><div class='add'>+			label = "Lid";</div><div class='add'>+			gpios = &lt;&amp;pio 69 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;SW_LID&gt;;</div><div class='add'>+			linux,input-type = &lt;EV_SW&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		switch-power {</div><div class='add'>+			label = "Power";</div><div class='add'>+			gpios = &lt;&amp;pio 14 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+			debounce-interval = &lt;30&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		switch-tablet-mode {</div><div class='add'>+			label = "Tablet_mode";</div><div class='add'>+			gpios = &lt;&amp;pio 121 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,code = &lt;SW_TABLET_MODE&gt;;</div><div class='add'>+			linux,input-type = &lt;EV_SW&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		switch-volume-down {</div><div class='add'>+			label = "Volume_down";</div><div class='add'>+			gpios = &lt;&amp;pio 123 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		switch-volume-up {</div><div class='add'>+			label = "Volume_up";</div><div class='add'>+			gpios = &lt;&amp;pio 124 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	panel_fixed_3v3: regulator1 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "PANEL_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		off-on-delay-us = &lt;500000&gt;;</div><div class='add'>+		gpio = &lt;&amp;pio 41 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;panel_fixed_pins&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps8640_fixed_1v2: regulator2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "PS8640_1V2";</div><div class='add'>+		regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+		regulator-enable-ramp-delay = &lt;2000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		gpio = &lt;&amp;pio 30 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;ps8640_fixed_pins&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdio_fixed_3v3: fixedregulator0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;pio 85 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;sdio_fixed_3v3_pins&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound: sound {</div><div class='add'>+		compatible = "mediatek,mt8173-rt5650";</div><div class='add'>+		mediatek,audio-codec = &lt;&amp;rt5650 &amp;hdmi0&gt;;</div><div class='add'>+		mediatek,platform = &lt;&amp;afe&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;aud_i2s2&gt;;</div><div class='add'>+</div><div class='add'>+		mediatek,mclk = &lt;1&gt;;</div><div class='add'>+		codec-capture {</div><div class='add'>+			sound-dai = &lt;&amp;rt5650 1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdmicon: connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		label = "hdmi";</div><div class='add'>+		type = "a";</div><div class='add'>+		ddc-i2c-bus = &lt;&amp;hdmiddc0&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			hdmi_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi0_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	watchdog {</div><div class='add'>+		compatible = "arm,smc-wdt";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Disable the original MMIO watch dog and switch to the SMC watchdog, which</div><div class='add'>+ * operates on the same MMIO.</div><div class='add'>+ */</div><div class='add'>+&amp;watchdog {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mfg_async {</div><div class='add'>+	domain-supply = &lt;&amp;da9211_vgpu_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cec {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	proc-supply = &lt;&amp;mt6397_vpca15_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu1 {</div><div class='add'>+	proc-supply = &lt;&amp;mt6397_vpca15_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu2 {</div><div class='add'>+	proc-supply = &lt;&amp;da9211_vcpu_reg&gt;;</div><div class='add'>+	sram-supply = &lt;&amp;mt6397_vsramca7_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu3 {</div><div class='add'>+	proc-supply = &lt;&amp;da9211_vcpu_reg&gt;;</div><div class='add'>+	sram-supply = &lt;&amp;mt6397_vsramca7_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu_thermal {</div><div class='add'>+	sustainable-power = &lt;4500&gt;; /* milliwatts */</div><div class='add'>+	trips {</div><div class='add'>+		threshold: trip-point0 {</div><div class='add'>+			temperature = &lt;60000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		target: trip-point1 {</div><div class='add'>+			temperature = &lt;65000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsi0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	ports {</div><div class='add'>+		port {</div><div class='add'>+			dsi0_out: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;ps8640_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpi0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	ports {</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			hdmi0_out: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_connector_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hdmi_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+	mediatek,ibias = &lt;0xc&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	rt5650: audio-codec@1a {</div><div class='add'>+		compatible = "realtek,rt5650";</div><div class='add'>+		reg = &lt;0x1a&gt;;</div><div class='add'>+		avdd-supply = &lt;&amp;mt6397_vgp1_reg&gt;;</div><div class='add'>+		cpvdd-supply = &lt;&amp;mt6397_vcama_reg&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 3 IRQ_TYPE_EDGE_BOTH&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;rt5650_irq&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+		realtek,dmic1-data-pin = &lt;2&gt;;</div><div class='add'>+		realtek,jd-mode = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps8640: edp-bridge@8 {</div><div class='add'>+		compatible = "parade,ps8640";</div><div class='add'>+		reg = &lt;0x8&gt;;</div><div class='add'>+		powerdown-gpios = &lt;&amp;pio 127 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pio 115 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;ps8640_pins&gt;;</div><div class='add'>+		vdd12-supply = &lt;&amp;ps8640_fixed_1v2&gt;;</div><div class='add'>+		vdd33-supply = &lt;&amp;mt6397_vgp2_reg&gt;;</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				ps8640_in: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;dsi0_out&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				ps8640_out: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;panel_in&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aux-bus {</div><div class='add'>+			panel: panel {</div><div class='add'>+				compatible = "edp-panel";</div><div class='add'>+				power-supply = &lt;&amp;panel_fixed_3v3&gt;;</div><div class='add'>+				backlight = &lt;&amp;backlight&gt;;</div><div class='add'>+</div><div class='add'>+				port {</div><div class='add'>+					panel_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ps8640_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;1500000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	da9211: da9211@68 {</div><div class='add'>+		compatible = "dlg,da9211";</div><div class='add'>+		reg = &lt;0x68&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 15 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			da9211_vcpu_reg: BUCKA {</div><div class='add'>+				regulator-name = "VBUCKA";</div><div class='add'>+				regulator-min-microvolt = &lt; 700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1310000&gt;;</div><div class='add'>+				regulator-min-microamp = &lt;2000000&gt;;</div><div class='add'>+				regulator-max-microamp = &lt;4400000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;10000&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-allowed-modes = &lt;DA9211_BUCK_MODE_SYNC</div><div class='add'>+							   DA9211_BUCK_MODE_AUTO&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			da9211_vgpu_reg: BUCKB {</div><div class='add'>+				regulator-name = "VBUCKB";</div><div class='add'>+				regulator-min-microvolt = &lt; 700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1310000&gt;;</div><div class='add'>+				regulator-min-microamp = &lt;2000000&gt;;</div><div class='add'>+				regulator-max-microamp = &lt;3000000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;10000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	tpm: tpm@20 {</div><div class='add'>+		compatible = "infineon,slb9645tt";</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+		powered-while-suspended;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	touchscreen: touchscreen@10 {</div><div class='add'>+		compatible = "elan,ekth3500";</div><div class='add'>+		reg = &lt;0x10&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 88 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	trackpad: trackpad@15 {</div><div class='add'>+		compatible = "elan,ekth3000";</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 117 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;trackpad_irq&gt;;</div><div class='add'>+		reg = &lt;0x15&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;mt6397_vgp6_reg&gt;;</div><div class='add'>+		wakeup-source;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_tx0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-names = "default", "state_uhs";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc0_pins_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;mmc0_pins_uhs&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	cap-mmc-highspeed;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	mmc-hs400-1_8v;</div><div class='add'>+	cap-mmc-hw-reset;</div><div class='add'>+	hs400-ds-delay = &lt;0x14015&gt;;</div><div class='add'>+	mediatek,hs200-cmd-int-delay = &lt;30&gt;;</div><div class='add'>+	mediatek,hs400-cmd-int-delay = &lt;14&gt;;</div><div class='add'>+	mediatek,hs400-cmd-resp-sel-rising;</div><div class='add'>+	vmmc-supply = &lt;&amp;mt6397_vemc_3v3_reg&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;mt6397_vio18_reg&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;topckgen CLK_TOP_MSDC50_0_SEL&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_MSDCPLL_D2&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-names = "default", "state_uhs";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc1_pins_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;mmc1_pins_uhs&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	sd-uhs-sdr50;</div><div class='add'>+	sd-uhs-sdr104;</div><div class='add'>+	cd-gpios = &lt;&amp;pio 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;mt6397_vmch_reg&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;mt6397_vmc_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-names = "default", "state_uhs";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc3_pins_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;mmc3_pins_uhs&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	sd-uhs-sdr50;</div><div class='add'>+	sd-uhs-sdr104;</div><div class='add'>+	keep-power-in-suspend;</div><div class='add'>+	wakeup-source;</div><div class='add'>+	cap-sdio-irq;</div><div class='add'>+	vmmc-supply = &lt;&amp;sdio_fixed_3v3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;mt6397_vgp3_reg&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	cap-power-off-card;</div><div class='add'>+</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	btmrvl: btmrvl@2 {</div><div class='add'>+		compatible = "marvell,sd8897-bt";</div><div class='add'>+		reg = &lt;2&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 119 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		marvell,wakeup-pin = /bits/ 16 &lt;0x0d&gt;;</div><div class='add'>+		marvell,wakeup-gap-ms = /bits/ 16 &lt;0x64&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mwifiex: mwifiex@1 {</div><div class='add'>+		compatible = "marvell,sd8897";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 38 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		marvell,wakeup-pin = &lt;3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;nor_flash {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;nor_gpio1_pins&gt;;</div><div class='add'>+</div><div class='add'>+	flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;50000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	gpio-line-names = "EC_INT_1V8",</div><div class='add'>+			  "SD_CD_L",</div><div class='add'>+			  "ALC5514_IRQ",</div><div class='add'>+			  "ALC5650_IRQ",</div><div class='add'>+			  /*</div><div class='add'>+			   * AP_FLASH_WP_L is crossystem ABI. Schematics</div><div class='add'>+			   * call it SFWP_B.</div><div class='add'>+			   */</div><div class='add'>+			  "AP_FLASH_WP_L",</div><div class='add'>+			  "SFIN",</div><div class='add'>+			  "SFCS0",</div><div class='add'>+			  "SFHOLD",</div><div class='add'>+			  "SFOUT",</div><div class='add'>+			  "SFCK",</div><div class='add'>+			  "WRAP_EVENT_S_EINT10",</div><div class='add'>+			  "PMU_INT",</div><div class='add'>+			  "I2S2_WS_ALC5650",</div><div class='add'>+			  "I2S2_BCK_ALC5650",</div><div class='add'>+			  "PWR_BTN_1V8",</div><div class='add'>+			  "DA9212_IRQ",</div><div class='add'>+			  "IDDIG",</div><div class='add'>+			  "WATCHDOG",</div><div class='add'>+			  "CEC",</div><div class='add'>+			  "HDMISCK",</div><div class='add'>+			  "HDMISD",</div><div class='add'>+			  "HTPLG",</div><div class='add'>+			  "MSDC3_DAT0",</div><div class='add'>+			  "MSDC3_DAT1",</div><div class='add'>+			  "MSDC3_DAT2",</div><div class='add'>+			  "MSDC3_DAT3",</div><div class='add'>+			  "MSDC3_CLK",</div><div class='add'>+			  "MSDC3_CMD",</div><div class='add'>+			  "USB_C0_OC_FLAGB",</div><div class='add'>+			  "USBA_OC1_L",</div><div class='add'>+			  "PS8640_1V2_ENABLE",</div><div class='add'>+			  "THERM_ALERT_N",</div><div class='add'>+			  "PANEL_LCD_POWER_EN",</div><div class='add'>+			  "ANX7688_CHIP_PD_C",</div><div class='add'>+			  "EC_IN_RW_1V8",</div><div class='add'>+			  "ANX7688_1V_EN_C",</div><div class='add'>+			  "USB_DP_HPD_C",</div><div class='add'>+			  "TPM_DAVINT_N",</div><div class='add'>+			  "MARVELL8897_IRQ",</div><div class='add'>+			  "EN_USB_A0_PWR",</div><div class='add'>+			  "USBA_A0_OC_L",</div><div class='add'>+			  "EN_PP3300_DX_EDP",</div><div class='add'>+			  "",</div><div class='add'>+			  "SOC_I2C2_1V8_SDA_400K",</div><div class='add'>+			  "SOC_I2C2_1V8_SCL_400K",</div><div class='add'>+			  "SOC_I2C0_1V8_SDA_400K",</div><div class='add'>+			  "SOC_I2C0_1V8_SCL_400K",</div><div class='add'>+			  "EMMC_ID1",</div><div class='add'>+			  "EMMC_ID0",</div><div class='add'>+			  "MEM_CONFIG3",</div><div class='add'>+			  "EMMC_ID2",</div><div class='add'>+			  "MEM_CONFIG1",</div><div class='add'>+			  "MEM_CONFIG2",</div><div class='add'>+			  "BRD_ID2",</div><div class='add'>+			  "MEM_CONFIG0",</div><div class='add'>+			  "BRD_ID0",</div><div class='add'>+			  "BRD_ID1",</div><div class='add'>+			  "EMMC_DAT0",</div><div class='add'>+			  "EMMC_DAT1",</div><div class='add'>+			  "EMMC_DAT2",</div><div class='add'>+			  "EMMC_DAT3",</div><div class='add'>+			  "EMMC_DAT4",</div><div class='add'>+			  "EMMC_DAT5",</div><div class='add'>+			  "EMMC_DAT6",</div><div class='add'>+			  "EMMC_DAT7",</div><div class='add'>+			  "EMMC_CLK",</div><div class='add'>+			  "EMMC_CMD",</div><div class='add'>+			  "EMMC_RCLK",</div><div class='add'>+			  "PLT_RST_L",</div><div class='add'>+			  "LID_OPEN_1V8_L",</div><div class='add'>+			  "AUDIO_SPI_MISO_R",</div><div class='add'>+			  "",</div><div class='add'>+			  "AC_OK_1V8",</div><div class='add'>+			  "SD_DATA0",</div><div class='add'>+			  "SD_DATA1",</div><div class='add'>+			  "SD_DATA2",</div><div class='add'>+			  "SD_DATA3",</div><div class='add'>+			  "SD_CLK",</div><div class='add'>+			  "SD_CMD",</div><div class='add'>+			  "PWRAP_SPI0_MI",</div><div class='add'>+			  "PWRAP_SPI0_MO",</div><div class='add'>+			  "PWRAP_SPI0_CK",</div><div class='add'>+			  "PWRAP_SPI0_CSN",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "WIFI_PDN",</div><div class='add'>+			  "RTC32K_1V8",</div><div class='add'>+			  "DISP_PWM0",</div><div class='add'>+			  "TOUCHSCREEN_INT_L",</div><div class='add'>+			  "",</div><div class='add'>+			  "SRCLKENA0",</div><div class='add'>+			  "SRCLKENA1",</div><div class='add'>+			  "PS8640_MODE_CONF",</div><div class='add'>+			  "TOUCHSCREEN_RESET_R",</div><div class='add'>+			  "PLATFORM_PROCHOT_L",</div><div class='add'>+			  "PANEL_POWER_EN",</div><div class='add'>+			  "REC_MODE_L",</div><div class='add'>+			  "EC_FW_UPDATE_L",</div><div class='add'>+			  "ACCEL2_INT_L",</div><div class='add'>+			  "HDMI_DP_INT",</div><div class='add'>+			  "ACCELGYRO3_INT_L",</div><div class='add'>+			  "ACCELGYRO4_INT_L",</div><div class='add'>+			  "SPI_EC_CLK",</div><div class='add'>+			  "SPI_EC_MI",</div><div class='add'>+			  "SPI_EC_MO",</div><div class='add'>+			  "SPI_EC_CSN",</div><div class='add'>+			  "SOC_I2C3_1V8_SDA_400K",</div><div class='add'>+			  "SOC_I2C3_1V8_SCL_400K",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "PS8640_SYSRSTN_1V8",</div><div class='add'>+			  "APIN_MAX98090_DOUT2",</div><div class='add'>+			  "TP_INT_1V8_L_R",</div><div class='add'>+			  "RST_USB_HUB_R",</div><div class='add'>+			  "BT_WAKE_L",</div><div class='add'>+			  "ACCEL1_INT_L",</div><div class='add'>+			  "TABLET_MODE_L",</div><div class='add'>+			  "",</div><div class='add'>+			  "V_UP_IN_L_R",</div><div class='add'>+			  "V_DOWN_IN_L_R",</div><div class='add'>+			  "SOC_I2C1_1V8_SDA_1M",</div><div class='add'>+			  "SOC_I2C1_1V8_SCL_1M",</div><div class='add'>+			  "PS8640_PDN_1V8",</div><div class='add'>+			  "MAX98090_LRCLK",</div><div class='add'>+			  "MAX98090_BCLK",</div><div class='add'>+			  "MAX98090_MCLK",</div><div class='add'>+			  "APOUT_MAX98090_DIN",</div><div class='add'>+			  "APIN_MAX98090_DOUT",</div><div class='add'>+			  "SOC_I2C4_1V8_SDA_400K",</div><div class='add'>+			  "SOC_I2C4_1V8_SCL_400K";</div><div class='add'>+</div><div class='add'>+	aud_i2s2: aud_i2s2 {</div><div class='add'>+		pins1 {</div><div class='add'>+			pinmux = &lt;MT8173_PIN_128_I2S0_LRCK__FUNC_I2S1_WS&gt;,</div><div class='add'>+				 &lt;MT8173_PIN_129_I2S0_BCK__FUNC_I2S1_BCK&gt;,</div><div class='add'>+				 &lt;MT8173_PIN_130_I2S0_MCK__FUNC_I2S1_MCK&gt;,</div><div class='add'>+				 &lt;MT8173_PIN_131_I2S0_DATA0__FUNC_I2S1_DO_1&gt;,</div><div class='add'>+				 &lt;MT8173_PIN_12_EINT12__FUNC_I2S2_WS&gt;,</div><div class='add'>+				 &lt;MT8173_PIN_13_EINT13__FUNC_I2S2_BCK&gt;,</div><div class='add'>+				 &lt;MT8173_PIN_132_I2S0_DATA1__FUNC_I2S2_DI_2&gt;;</div><div class='add'>+			bias-pull-down;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bl_fixed_pins: bl_fixed_pins {</div><div class='add'>+		pins1 {</div><div class='add'>+			pinmux = &lt;MT8173_PIN_32_UTXD2__FUNC_GPIO32&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bt_wake_pins: bt_wake_pins {</div><div class='add'>+		pins1 {</div><div class='add'>+			pinmux = &lt;MT8173_PIN_119_KPROW0__FUNC_GPIO119&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	disp_pwm0_pins: disp_pwm0_pins {</div><div class='add'>+		pins1 {</div><div class='add'>+			pinmux = &lt;MT8173_PIN_87_DISP_PWM0__FUNC_DISP_PWM0&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio_keys_pins: gpio_keys_pins {</div><div class='add'>+		volume_pins {</div><div class='add'>+			pinmux = &lt;MT8173_PIN_123_KPCOL1__FUNC_GPIO123&gt;,</div><div class='add'>+				 &lt;MT8173_PIN_124_KPCOL2__FUNC_GPIO124&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tablet_mode_pins {</div><div class='add'>+			pinmux = &lt;MT8173_PIN_121_KPROW2__FUNC_GPIO121&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdmi_mux_pins: hdmi_mux_pins {</div><div class='add'>+		pins1 {</div><div class='add'>+			pinmux = &lt;MT8173_PIN_36_DAISYNC__FUNC_GPIO36&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c1_pins_a: i2c1 {</div><div class='add'>+		da9211_pins {</div><div class='add'>+			pinmux = &lt;MT8173_PIN_15_EINT15__FUNC_GPIO15&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc0_pins_default: mmc0default {</div><div class='add'>+		pins_cmd_dat {</div><div class='add'>+			pinmux = &lt;MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0&gt;,</div><div class='add'>+				 &lt;MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1&gt;,</div><div class='add'>+				 &lt;MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2&gt;,</div><div class='add'>+				 &lt;MT8173_PIN_60_MSDC0_DAT3__FUNC_MSDC0_DAT3&gt;,</div><div class='add'>+				 &lt;MT8173_PIN_61_MSDC0_DAT4__FUNC_MSDC0_DAT4&gt;,</div><div class='add'>+				 &lt;MT8173_PIN_62_MSDC0_DAT5__FUNC_MSDC0_DAT5&gt;,</div><div class='add'>+				 &lt;MT8173_PIN_63_MSDC0_DAT6__FUNC_MSDC0_DAT6&gt;,</div><div class='add'>+				 &lt;MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7&gt;,</div><div class='add'>+				 &lt;MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins_clk {</div><div class='add'>+			pinmux = &lt;MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK&gt;;</div><div class='add'>+			bias-pull-down;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins_rst {</div><div class='add'>+			pinmux = &lt;MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc1_pins_default: mmc1default {</div><div class='add'>+		pins_cmd_dat {</div><div class='add'>+			pinmux = &lt;MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0&gt;,</div><div class='add'>+				 &lt;MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1&gt;,</div><div class='add'>+				 &lt;MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2&gt;,</div><div class='add'>+				 &lt;MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3&gt;,</div><div class='add'>+				 &lt;MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;MTK_DRIVE_4mA&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins_clk {</div><div class='add'>+			pinmux = &lt;MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK&gt;;</div><div class='add'>+			bias-pull-down;</div><div class='add'>+			drive-strength = &lt;MTK_DRIVE_4mA&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins_insert {</div><div class='add'>+			pinmux = &lt;MT8173_PIN_1_EINT1__FUNC_GPIO1&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc3_pins_default: mmc3default {</div><div class='add'>+		pins_dat {</div><div class='add'>+			pinmux = &lt;MT8173_PIN_22_MSDC3_DAT0__FUNC_MSDC3_DAT0&gt;,</div><div class='add'>+				 &lt;MT8173_PIN_23_MSDC3_DAT1__FUNC_MSDC3_DAT1&gt;,</div><div class='add'>+				 &lt;MT8173_PIN_24_MSDC3_DAT2__FUNC_MSDC3_DAT2&gt;,</div><div class='add'>+				 &lt;MT8173_PIN_25_MSDC3_DAT3__FUNC_MSDC3_DAT3&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;MTK_DRIVE_8mA&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins_cmd {</div><div class='add'>+			pinmux = &lt;MT8173_PIN_27_MSDC3_CMD__FUNC_MSDC3_CMD&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;MTK_DRIVE_8mA&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins_clk {</div><div class='add'>+			pinmux = &lt;MT8173_PIN_26_MSDC3_CLK__FUNC_MSDC3_CLK&gt;;</div><div class='add'>+			bias-pull-down;</div><div class='add'>+			drive-strength = &lt;MTK_DRIVE_8mA&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc0_pins_uhs: mmc0 {</div><div class='add'>+		pins_cmd_dat {</div><div class='add'>+			pinmux = &lt;MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0&gt;,</div><div class='add'>+				 &lt;MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1&gt;,</div><div class='add'>+				 &lt;MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2&gt;,</div><div class='add'>+				 &lt;MT8173_PIN_60_MSDC0_DAT3__FUNC_MSDC0_DAT3&gt;,</div><div class='add'>+				 &lt;MT8173_PIN_61_MSDC0_DAT4__FUNC_MSDC0_DAT4&gt;,</div><div class='add'>+				 &lt;MT8173_PIN_62_MSDC0_DAT5__FUNC_MSDC0_DAT5&gt;,</div><div class='add'>+				 &lt;MT8173_PIN_63_MSDC0_DAT6__FUNC_MSDC0_DAT6&gt;,</div><div class='add'>+				 &lt;MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7&gt;,</div><div class='add'>+				 &lt;MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;MTK_DRIVE_6mA&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins_clk {</div><div class='add'>+			pinmux = &lt;MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK&gt;;</div><div class='add'>+			drive-strength = &lt;MTK_DRIVE_6mA&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins_ds {</div><div class='add'>+			pinmux = &lt;MT8173_PIN_67_MSDC0_DSL__FUNC_MSDC0_DSL&gt;;</div><div class='add'>+			drive-strength = &lt;MTK_DRIVE_10mA&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins_rst {</div><div class='add'>+			pinmux = &lt;MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc1_pins_uhs: mmc1 {</div><div class='add'>+		pins_cmd_dat {</div><div class='add'>+			pinmux = &lt;MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0&gt;,</div><div class='add'>+				 &lt;MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1&gt;,</div><div class='add'>+				 &lt;MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2&gt;,</div><div class='add'>+				 &lt;MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3&gt;,</div><div class='add'>+				 &lt;MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;MTK_DRIVE_6mA&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins_clk {</div><div class='add'>+			pinmux = &lt;MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK&gt;;</div><div class='add'>+			drive-strength = &lt;MTK_DRIVE_8mA&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc3_pins_uhs: mmc3 {</div><div class='add'>+		pins_dat {</div><div class='add'>+			pinmux = &lt;MT8173_PIN_22_MSDC3_DAT0__FUNC_MSDC3_DAT0&gt;,</div><div class='add'>+				 &lt;MT8173_PIN_23_MSDC3_DAT1__FUNC_MSDC3_DAT1&gt;,</div><div class='add'>+				 &lt;MT8173_PIN_24_MSDC3_DAT2__FUNC_MSDC3_DAT2&gt;,</div><div class='add'>+				 &lt;MT8173_PIN_25_MSDC3_DAT3__FUNC_MSDC3_DAT3&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;MTK_DRIVE_8mA&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins_cmd {</div><div class='add'>+			pinmux = &lt;MT8173_PIN_27_MSDC3_CMD__FUNC_MSDC3_CMD&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;MTK_DRIVE_8mA&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins_clk {</div><div class='add'>+			pinmux = &lt;MT8173_PIN_26_MSDC3_CLK__FUNC_MSDC3_CLK&gt;;</div><div class='add'>+			drive-strength = &lt;MTK_DRIVE_8mA&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	nor_gpio1_pins: nor {</div><div class='add'>+		pins1 {</div><div class='add'>+			pinmux = &lt;MT8173_PIN_6_EINT6__FUNC_SFCS0&gt;,</div><div class='add'>+				 &lt;MT8173_PIN_7_EINT7__FUNC_SFHOLD&gt;,</div><div class='add'>+				 &lt;MT8173_PIN_8_EINT8__FUNC_SFIN&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;MTK_DRIVE_4mA&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins2 {</div><div class='add'>+			pinmux = &lt;MT8173_PIN_5_EINT5__FUNC_SFOUT&gt;;</div><div class='add'>+			drive-strength = &lt;MTK_DRIVE_4mA&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins_clk {</div><div class='add'>+			pinmux = &lt;MT8173_PIN_9_EINT9__FUNC_SFCK&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;MTK_DRIVE_4mA&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	panel_backlight_en_pins: panel_backlight_en_pins {</div><div class='add'>+		pins1 {</div><div class='add'>+			pinmux = &lt;MT8173_PIN_95_PCM_TX__FUNC_GPIO95&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	panel_fixed_pins: panel_fixed_pins {</div><div class='add'>+		pins1 {</div><div class='add'>+			pinmux = &lt;MT8173_PIN_41_CMMCLK__FUNC_GPIO41&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps8640_pins: ps8640_pins {</div><div class='add'>+		pins1 {</div><div class='add'>+			pinmux = &lt;MT8173_PIN_92_PCM_CLK__FUNC_GPIO92&gt;,</div><div class='add'>+				 &lt;MT8173_PIN_115_URTS0__FUNC_GPIO115&gt;,</div><div class='add'>+				 &lt;MT8173_PIN_127_LCM_RST__FUNC_GPIO127&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps8640_fixed_pins: ps8640_fixed_pins {</div><div class='add'>+		pins1 {</div><div class='add'>+			pinmux = &lt;MT8173_PIN_30_URTS2__FUNC_GPIO30&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rt5650_irq: rt5650_irq {</div><div class='add'>+		pins1 {</div><div class='add'>+			pinmux = &lt;MT8173_PIN_3_EINT3__FUNC_GPIO3&gt;;</div><div class='add'>+			bias-pull-down;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdio_fixed_3v3_pins: sdio_fixed_3v3_pins {</div><div class='add'>+		pins1 {</div><div class='add'>+			pinmux = &lt;MT8173_PIN_85_AUD_DAT_MOSI__FUNC_GPIO85&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi_pins_a: spi1 {</div><div class='add'>+		pins1 {</div><div class='add'>+			pinmux = &lt;MT8173_PIN_0_EINT0__FUNC_GPIO0&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins_spi {</div><div class='add'>+			pinmux = &lt;MT8173_PIN_102_MSDC2_DAT2__FUNC_SPI_CK_1_&gt;,</div><div class='add'>+				 &lt;MT8173_PIN_103_MSDC2_DAT3__FUNC_SPI_MI_1_&gt;,</div><div class='add'>+				 &lt;MT8173_PIN_104_MSDC2_CLK__FUNC_SPI_MO_1_&gt;,</div><div class='add'>+				 &lt;MT8173_PIN_105_MSDC2_CMD__FUNC_SPI_CS_1_&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	trackpad_irq: trackpad_irq {</div><div class='add'>+		pins1 {</div><div class='add'>+			pinmux = &lt;MT8173_PIN_117_URXD3__FUNC_GPIO117&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb_pins: usb {</div><div class='add'>+		pins1 {</div><div class='add'>+			pinmux = &lt;MT8173_PIN_101_MSDC2_DAT1__FUNC_GPIO101&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wifi_wake_pins: wifi_wake_pins {</div><div class='add'>+		pins1 {</div><div class='add'>+			pinmux = &lt;MT8173_PIN_38_CONN_RST__FUNC_GPIO38&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;disp_pwm0_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwrap {</div><div class='add'>+	pmic: pmic {</div><div class='add'>+		compatible = "mediatek,mt6397";</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 11 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		clock: clocks {</div><div class='add'>+			compatible = "mediatek,mt6397-clk";</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pio6397: pinctrl {</div><div class='add'>+			compatible = "mediatek,mt6397-pinctrl";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			compatible = "mediatek,mt6397-regulator";</div><div class='add'>+</div><div class='add'>+			mt6397_vpca15_reg: buck_vpca15 {</div><div class='add'>+				regulator-name = "vpca15";</div><div class='add'>+				regulator-min-microvolt = &lt; 700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12500&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+				regulator-allowed-modes = &lt;0 1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6397_vpca7_reg: buck_vpca7 {</div><div class='add'>+				regulator-name = "vpca7";</div><div class='add'>+				regulator-min-microvolt = &lt; 700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12500&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;115&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6397_vsramca15_reg: buck_vsramca15 {</div><div class='add'>+				regulator-name = "vsramca15";</div><div class='add'>+				regulator-min-microvolt = &lt; 700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12500&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6397_vsramca7_reg: buck_vsramca7 {</div><div class='add'>+				regulator-name = "vsramca7";</div><div class='add'>+				regulator-min-microvolt = &lt; 700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12500&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6397_vcore_reg: buck_vcore {</div><div class='add'>+				regulator-name = "vcore";</div><div class='add'>+				regulator-min-microvolt = &lt; 700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12500&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6397_vgpu_reg: buck_vgpu {</div><div class='add'>+				regulator-name = "vgpu";</div><div class='add'>+				regulator-min-microvolt = &lt; 700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12500&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;115&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6397_vdrm_reg: buck_vdrm {</div><div class='add'>+				regulator-name = "vdrm";</div><div class='add'>+				regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1400000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12500&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6397_vio18_reg: buck_vio18 {</div><div class='add'>+				regulator-name = "vio18";</div><div class='add'>+				regulator-min-microvolt = &lt;1620000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1980000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12500&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6397_vtcxo_reg: ldo_vtcxo {</div><div class='add'>+				regulator-name = "vtcxo";</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6397_va28_reg: ldo_va28 {</div><div class='add'>+				regulator-name = "va28";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6397_vcama_reg: ldo_vcama {</div><div class='add'>+				regulator-name = "vcama";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;218&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6397_vio28_reg: ldo_vio28 {</div><div class='add'>+				regulator-name = "vio28";</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6397_vusb_reg: ldo_vusb {</div><div class='add'>+				regulator-name = "vusb";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6397_vmc_reg: ldo_vmc {</div><div class='add'>+				regulator-name = "vmc";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;218&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6397_vmch_reg: ldo_vmch {</div><div class='add'>+				regulator-name = "vmch";</div><div class='add'>+				regulator-min-microvolt = &lt;3000000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;218&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6397_vemc_3v3_reg: ldo_vemc3v3 {</div><div class='add'>+				regulator-name = "vemc_3v3";</div><div class='add'>+				regulator-min-microvolt = &lt;3000000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;218&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6397_vgp1_reg: ldo_vgp1 {</div><div class='add'>+				regulator-name = "vcamd";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;240&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6397_vgp2_reg: ldo_vgp2 {</div><div class='add'>+				regulator-name = "vcamio";</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;218&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6397_vgp3_reg: ldo_vgp3 {</div><div class='add'>+				regulator-name = "vcamaf";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;218&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6397_vgp4_reg: ldo_vgp4 {</div><div class='add'>+				regulator-name = "vgp4";</div><div class='add'>+				regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;218&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6397_vgp5_reg: ldo_vgp5 {</div><div class='add'>+				regulator-name = "vgp5";</div><div class='add'>+				regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3000000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;218&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6397_vgp6_reg: ldo_vgp6 {</div><div class='add'>+				regulator-name = "vgp6";</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;218&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6397_vibr_reg: ldo_vibr {</div><div class='add'>+				regulator-name = "vibr";</div><div class='add'>+				regulator-min-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;218&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rtc: rtc {</div><div class='add'>+			compatible = "mediatek,mt6397-rtc";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;spi_pins_a&gt;;</div><div class='add'>+	mediatek,pad-select = &lt;1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+	/* clients */</div><div class='add'>+	cros_ec: ec@0 {</div><div class='add'>+		compatible = "google,cros-ec-spi";</div><div class='add'>+		reg = &lt;0x0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;12000000&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 0 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		google,cros-ec-spi-msg-delay = &lt;500&gt;;</div><div class='add'>+		wakeup-source;</div><div class='add'>+</div><div class='add'>+		i2c_tunnel: i2c-tunnel0 {</div><div class='add'>+			compatible = "google,cros-ec-i2c-tunnel";</div><div class='add'>+			google,remote-bus = &lt;0&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			battery: sbs-battery@b {</div><div class='add'>+				compatible = "sbs,sbs-battery";</div><div class='add'>+				reg = &lt;0xb&gt;;</div><div class='add'>+				sbs,i2c-retry-count = &lt;2&gt;;</div><div class='add'>+				sbs,poll-retry-count = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ssusb {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	wakeup-source;</div><div class='add'>+	vusb33-supply = &lt;&amp;mt6397_vusb_reg&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;thermal {</div><div class='add'>+	bank0-supply = &lt;&amp;mt6397_vpca15_reg&gt;;</div><div class='add'>+	bank1-supply = &lt;&amp;da9211_vcpu_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_host {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;usb_pins&gt;;</div><div class='add'>+	vusb33-supply = &lt;&amp;mt6397_vusb_reg&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include &lt;arm/cros-ec-keyboard.dtsi&gt;</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts<br/>index 6dffada2e66b..9fffed0ef4bf 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8173-evb.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8173-evb.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8173-evb.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8173-evb.dts</a></div><div class='hunk'>@@ -10,6 +10,7 @@</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	model = "MediaTek MT8173 evaluation board";</div><div class='add'>+	chassis-type = "embedded";</div><div class='ctx'> 	compatible = "mediatek,mt8173-evb", "mediatek,mt8173";</div><div class='ctx'> </div><div class='ctx'> 	aliases {</div><div class='hunk'>@@ -40,10 +41,10 @@</div><div class='ctx'> </div><div class='ctx'> 	extcon_usb: extcon_iddig {</div><div class='ctx'> 		compatible = "linux,extcon-usb-gpio";</div><div class='del'>-		id-gpio = &lt;&amp;pio 16 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		id-gpios = &lt;&amp;pio 16 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	usb_p1_vbus: regulator@0 {</div><div class='add'>+	usb_p1_vbus: regulator-usb-p1 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "usb_vbus";</div><div class='ctx'> 		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='hunk'>@@ -52,7 +53,7 @@</div><div class='ctx'> 		enable-active-high;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	usb_p0_vbus: regulator@1 {</div><div class='add'>+	usb_p0_vbus: regulator-usb-p0 {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='ctx'> 		regulator-name = "vbus";</div><div class='ctx'> 		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='hunk'>@@ -62,6 +63,10 @@</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;mfg_async {</div><div class='add'>+	domain-supply = &lt;&amp;da9211_vgpu_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;cec {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='hunk'>@@ -118,8 +123,8 @@</div><div class='ctx'> 				regulator-name = "VBUCKA";</div><div class='ctx'> 				regulator-min-microvolt = &lt; 700000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;1310000&gt;;</div><div class='del'>-				regulator-min-microamp	= &lt;2000000&gt;;</div><div class='del'>-				regulator-max-microamp	= &lt;4400000&gt;;</div><div class='add'>+				regulator-min-microamp = &lt;2000000&gt;;</div><div class='add'>+				regulator-max-microamp = &lt;4400000&gt;;</div><div class='ctx'> 				regulator-ramp-delay = &lt;10000&gt;;</div><div class='ctx'> 				regulator-always-on;</div><div class='ctx'> 			};</div><div class='hunk'>@@ -128,8 +133,8 @@</div><div class='ctx'> 				regulator-name = "VBUCKB";</div><div class='ctx'> 				regulator-min-microvolt = &lt; 700000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;1310000&gt;;</div><div class='del'>-				regulator-min-microamp	= &lt;2000000&gt;;</div><div class='del'>-				regulator-max-microamp	= &lt;3000000&gt;;</div><div class='add'>+				regulator-min-microamp = &lt;2000000&gt;;</div><div class='add'>+				regulator-max-microamp = &lt;3000000&gt;;</div><div class='ctx'> 				regulator-ramp-delay = &lt;10000&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='hunk'>@@ -144,8 +149,8 @@</div><div class='ctx'> 	bus-width = &lt;8&gt;;</div><div class='ctx'> 	max-frequency = &lt;50000000&gt;;</div><div class='ctx'> 	cap-mmc-highspeed;</div><div class='del'>-	mediatek,hs200-cmd-int-delay=&lt;26&gt;;</div><div class='del'>-	mediatek,hs400-cmd-int-delay=&lt;14&gt;;</div><div class='add'>+	mediatek,hs200-cmd-int-delay = &lt;26&gt;;</div><div class='add'>+	mediatek,hs400-cmd-int-delay = &lt;14&gt;;</div><div class='ctx'> 	mediatek,hs400-cmd-resp-sel-rising;</div><div class='ctx'> 	vmmc-supply = &lt;&amp;mt6397_vemc_3v3_reg&gt;;</div><div class='ctx'> 	vqmmc-supply = &lt;&amp;mt6397_vio18_reg&gt;;</div><div class='hunk'>@@ -208,14 +213,14 @@</div><div class='ctx'> 				 &lt;MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3&gt;,</div><div class='ctx'> 				 &lt;MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD&gt;;</div><div class='ctx'> 			input-enable;</div><div class='del'>-			drive-strength = &lt;MTK_DRIVE_4mA&gt;;</div><div class='add'>+			drive-strength = &lt;4&gt;;</div><div class='ctx'> 			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		pins_clk {</div><div class='ctx'> 			pinmux = &lt;MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK&gt;;</div><div class='ctx'> 			bias-pull-down;</div><div class='del'>-			drive-strength = &lt;MTK_DRIVE_4mA&gt;;</div><div class='add'>+			drive-strength = &lt;4&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		pins_insert {</div><div class='hunk'>@@ -236,13 +241,13 @@</div><div class='ctx'> 				 &lt;MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7&gt;,</div><div class='ctx'> 				 &lt;MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD&gt;;</div><div class='ctx'> 			input-enable;</div><div class='del'>-			drive-strength = &lt;MTK_DRIVE_2mA&gt;;</div><div class='add'>+			drive-strength = &lt;2&gt;;</div><div class='ctx'> 			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		pins_clk {</div><div class='ctx'> 			pinmux = &lt;MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK&gt;;</div><div class='del'>-			drive-strength = &lt;MTK_DRIVE_2mA&gt;;</div><div class='add'>+			drive-strength = &lt;2&gt;;</div><div class='ctx'> 			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -260,13 +265,13 @@</div><div class='ctx'> 				 &lt;MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3&gt;,</div><div class='ctx'> 				 &lt;MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD&gt;;</div><div class='ctx'> 			input-enable;</div><div class='del'>-			drive-strength = &lt;MTK_DRIVE_4mA&gt;;</div><div class='add'>+			drive-strength = &lt;4&gt;;</div><div class='ctx'> 			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		pins_clk {</div><div class='ctx'> 			pinmux = &lt;MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK&gt;;</div><div class='del'>-			drive-strength = &lt;MTK_DRIVE_4mA&gt;;</div><div class='add'>+			drive-strength = &lt;4&gt;;</div><div class='ctx'> 			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='hunk'>@@ -294,20 +299,18 @@</div><div class='ctx'> </div><div class='ctx'> &amp;pwrap {</div><div class='ctx'> 	/* Only MT8173 E1 needs USB power domain */</div><div class='del'>-	power-domains = &lt;&amp;scpsys MT8173_POWER_DOMAIN_USB&gt;;</div><div class='add'>+	power-domains = &lt;&amp;spm MT8173_POWER_DOMAIN_USB&gt;;</div><div class='ctx'> </div><div class='del'>-	pmic: mt6397 {</div><div class='add'>+	pmic: pmic {</div><div class='ctx'> 		compatible = "mediatek,mt6397";</div><div class='del'>-		interrupt-parent = &lt;&amp;pio&gt;;</div><div class='del'>-		interrupts = &lt;11 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 11 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		interrupt-controller;</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='del'>-		mt6397regulator: mt6397regulator {</div><div class='add'>+		regulators {</div><div class='ctx'> 			compatible = "mediatek,mt6397-regulator";</div><div class='ctx'> </div><div class='ctx'> 			mt6397_vpca15_reg: buck_vpca15 {</div><div class='del'>-				regulator-compatible = "buck_vpca15";</div><div class='ctx'> 				regulator-name = "vpca15";</div><div class='ctx'> 				regulator-min-microvolt = &lt; 700000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='hunk'>@@ -316,7 +319,6 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			mt6397_vpca7_reg: buck_vpca7 {</div><div class='del'>-				regulator-compatible = "buck_vpca7";</div><div class='ctx'> 				regulator-name = "vpca7";</div><div class='ctx'> 				regulator-min-microvolt = &lt; 700000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='hunk'>@@ -325,7 +327,6 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			mt6397_vsramca15_reg: buck_vsramca15 {</div><div class='del'>-				regulator-compatible = "buck_vsramca15";</div><div class='ctx'> 				regulator-name = "vsramca15";</div><div class='ctx'> 				regulator-min-microvolt = &lt; 700000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='hunk'>@@ -334,7 +335,6 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			mt6397_vsramca7_reg: buck_vsramca7 {</div><div class='del'>-				regulator-compatible = "buck_vsramca7";</div><div class='ctx'> 				regulator-name = "vsramca7";</div><div class='ctx'> 				regulator-min-microvolt = &lt; 700000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='hunk'>@@ -343,7 +343,6 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			mt6397_vcore_reg: buck_vcore {</div><div class='del'>-				regulator-compatible = "buck_vcore";</div><div class='ctx'> 				regulator-name = "vcore";</div><div class='ctx'> 				regulator-min-microvolt = &lt; 700000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='hunk'>@@ -352,7 +351,6 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			mt6397_vgpu_reg: buck_vgpu {</div><div class='del'>-				regulator-compatible = "buck_vgpu";</div><div class='ctx'> 				regulator-name = "vgpu";</div><div class='ctx'> 				regulator-min-microvolt = &lt; 700000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='hunk'>@@ -361,7 +359,6 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			mt6397_vdrm_reg: buck_vdrm {</div><div class='del'>-				regulator-compatible = "buck_vdrm";</div><div class='ctx'> 				regulator-name = "vdrm";</div><div class='ctx'> 				regulator-min-microvolt = &lt;1200000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;1400000&gt;;</div><div class='hunk'>@@ -370,7 +367,6 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			mt6397_vio18_reg: buck_vio18 {</div><div class='del'>-				regulator-compatible = "buck_vio18";</div><div class='ctx'> 				regulator-name = "vio18";</div><div class='ctx'> 				regulator-min-microvolt = &lt;1620000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;1980000&gt;;</div><div class='hunk'>@@ -379,19 +375,16 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			mt6397_vtcxo_reg: ldo_vtcxo {</div><div class='del'>-				regulator-compatible = "ldo_vtcxo";</div><div class='ctx'> 				regulator-name = "vtcxo";</div><div class='ctx'> 				regulator-always-on;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			mt6397_va28_reg: ldo_va28 {</div><div class='del'>-				regulator-compatible = "ldo_va28";</div><div class='ctx'> 				regulator-name = "va28";</div><div class='ctx'> 				regulator-always-on;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			mt6397_vcama_reg: ldo_vcama {</div><div class='del'>-				regulator-compatible = "ldo_vcama";</div><div class='ctx'> 				regulator-name = "vcama";</div><div class='ctx'> 				regulator-min-microvolt = &lt;1500000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;2800000&gt;;</div><div class='hunk'>@@ -399,18 +392,15 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			mt6397_vio28_reg: ldo_vio28 {</div><div class='del'>-				regulator-compatible = "ldo_vio28";</div><div class='ctx'> 				regulator-name = "vio28";</div><div class='ctx'> 				regulator-always-on;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			mt6397_vusb_reg: ldo_vusb {</div><div class='del'>-				regulator-compatible = "ldo_vusb";</div><div class='ctx'> 				regulator-name = "vusb";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			mt6397_vmc_reg: ldo_vmc {</div><div class='del'>-				regulator-compatible = "ldo_vmc";</div><div class='ctx'> 				regulator-name = "vmc";</div><div class='ctx'> 				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='hunk'>@@ -418,7 +408,6 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			mt6397_vmch_reg: ldo_vmch {</div><div class='del'>-				regulator-compatible = "ldo_vmch";</div><div class='ctx'> 				regulator-name = "vmch";</div><div class='ctx'> 				regulator-min-microvolt = &lt;3000000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='hunk'>@@ -426,7 +415,6 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			mt6397_vemc_3v3_reg: ldo_vemc3v3 {</div><div class='del'>-				regulator-compatible = "ldo_vemc3v3";</div><div class='ctx'> 				regulator-name = "vemc_3v3";</div><div class='ctx'> 				regulator-min-microvolt = &lt;3000000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='hunk'>@@ -434,7 +422,6 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			mt6397_vgp1_reg: ldo_vgp1 {</div><div class='del'>-				regulator-compatible = "ldo_vgp1";</div><div class='ctx'> 				regulator-name = "vcamd";</div><div class='ctx'> 				regulator-min-microvolt = &lt;1220000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='hunk'>@@ -442,7 +429,6 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			mt6397_vgp2_reg: ldo_vgp2 {</div><div class='del'>-				regulator-compatible = "ldo_vgp2";</div><div class='ctx'> 				regulator-name = "vcamio";</div><div class='ctx'> 				regulator-min-microvolt = &lt;1000000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='hunk'>@@ -450,7 +436,6 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			mt6397_vgp3_reg: ldo_vgp3 {</div><div class='del'>-				regulator-compatible = "ldo_vgp3";</div><div class='ctx'> 				regulator-name = "vcamaf";</div><div class='ctx'> 				regulator-min-microvolt = &lt;1200000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='hunk'>@@ -458,7 +443,6 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			mt6397_vgp4_reg: ldo_vgp4 {</div><div class='del'>-				regulator-compatible = "ldo_vgp4";</div><div class='ctx'> 				regulator-name = "vgp4";</div><div class='ctx'> 				regulator-min-microvolt = &lt;1200000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='hunk'>@@ -466,7 +450,6 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			mt6397_vgp5_reg: ldo_vgp5 {</div><div class='del'>-				regulator-compatible = "ldo_vgp5";</div><div class='ctx'> 				regulator-name = "vgp5";</div><div class='ctx'> 				regulator-min-microvolt = &lt;1200000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;3000000&gt;;</div><div class='hunk'>@@ -474,7 +457,6 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			mt6397_vgp6_reg: ldo_vgp6 {</div><div class='del'>-				regulator-compatible = "ldo_vgp6";</div><div class='ctx'> 				regulator-name = "vgp6";</div><div class='ctx'> 				regulator-min-microvolt = &lt;1200000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='hunk'>@@ -482,7 +464,6 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			mt6397_vibr_reg: ldo_vibr {</div><div class='del'>-				regulator-compatible = "ldo_vibr";</div><div class='ctx'> 				regulator-name = "vibr";</div><div class='ctx'> 				regulator-min-microvolt = &lt;1300000&gt;;</div><div class='ctx'> 				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='hunk'>@@ -516,10 +497,8 @@</div><div class='ctx'> 	extcon = &lt;&amp;extcon_usb&gt;;</div><div class='ctx'> 	dr_mode = "otg";</div><div class='ctx'> 	wakeup-source;</div><div class='del'>-	pinctrl-names = "default", "id_float", "id_ground";</div><div class='add'>+	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;usb_id_pins_float&gt;;</div><div class='del'>-	pinctrl-1 = &lt;&amp;usb_id_pins_float&gt;;</div><div class='del'>-	pinctrl-2 = &lt;&amp;usb_id_pins_ground&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi<br/>index ccb8e88a60c5..122a57c3780b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8173.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8173.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8173.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8173.dtsi</a></div><div class='hunk'>@@ -1,14 +1,7 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2014 MediaTek Inc.</div><div class='ctx'>  * Author: Eddie Huang &lt;eddie.huang@mediatek.com&gt;</div><div class='del'>- *</div><div class='del'>- * This program is free software; you can redistribute it and/or modify</div><div class='del'>- * it under the terms of the GNU General Public License version 2 as</div><div class='del'>- * published by the Free Software Foundation.</div><div class='del'>- *</div><div class='del'>- * This program is distributed in the hope that it will be useful,</div><div class='del'>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the</div><div class='del'>- * GNU General Public License for more details.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;dt-bindings/clock/mt8173-clk.h&gt;</div><div class='hunk'>@@ -19,6 +12,7 @@</div><div class='ctx'> #include &lt;dt-bindings/power/mt8173-power.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/reset/mt8173-resets.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/gce/mt8173-gce.h&gt;</div><div class='add'>+#include &lt;dt-bindings/thermal/thermal.h&gt;</div><div class='ctx'> #include "mt8173-pinfunc.h"</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='hunk'>@@ -42,17 +36,21 @@</div><div class='ctx'> 		dpi0 = &amp;dpi0;</div><div class='ctx'> 		dsi0 = &amp;dsi0;</div><div class='ctx'> 		dsi1 = &amp;dsi1;</div><div class='del'>-		mdp_rdma0 = &amp;mdp_rdma0;</div><div class='del'>-		mdp_rdma1 = &amp;mdp_rdma1;</div><div class='del'>-		mdp_rsz0 = &amp;mdp_rsz0;</div><div class='del'>-		mdp_rsz1 = &amp;mdp_rsz1;</div><div class='del'>-		mdp_rsz2 = &amp;mdp_rsz2;</div><div class='del'>-		mdp_wdma0 = &amp;mdp_wdma0;</div><div class='del'>-		mdp_wrot0 = &amp;mdp_wrot0;</div><div class='del'>-		mdp_wrot1 = &amp;mdp_wrot1;</div><div class='add'>+		mdp-rdma0 = &amp;mdp_rdma0;</div><div class='add'>+		mdp-rdma1 = &amp;mdp_rdma1;</div><div class='add'>+		mdp-rsz0 = &amp;mdp_rsz0;</div><div class='add'>+		mdp-rsz1 = &amp;mdp_rsz1;</div><div class='add'>+		mdp-rsz2 = &amp;mdp_rsz2;</div><div class='add'>+		mdp-wdma0 = &amp;mdp_wdma0;</div><div class='add'>+		mdp-wrot0 = &amp;mdp_wrot0;</div><div class='add'>+		mdp-wrot1 = &amp;mdp_wrot1;</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+		serial1 = &amp;uart1;</div><div class='add'>+		serial2 = &amp;uart2;</div><div class='add'>+		serial3 = &amp;uart3;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	cluster0_opp: opp_table0 {</div><div class='add'>+	cluster0_opp: opp-table-0 {</div><div class='ctx'> 		compatible = "operating-points-v2";</div><div class='ctx'> 		opp-shared;</div><div class='ctx'> 		opp-507000000 {</div><div class='hunk'>@@ -89,7 +87,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	cluster1_opp: opp_table1 {</div><div class='add'>+	cluster1_opp: opp-table-1 {</div><div class='ctx'> 		compatible = "operating-points-v2";</div><div class='ctx'> 		opp-shared;</div><div class='ctx'> 		opp-507000000 {</div><div class='hunk'>@@ -162,6 +160,7 @@</div><div class='ctx'> 				 &lt;&amp;apmixedsys CLK_APMIXED_MAINPLL&gt;;</div><div class='ctx'> 			clock-names = "cpu", "intermediate";</div><div class='ctx'> 			operating-points-v2 = &lt;&amp;cluster0_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;740&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu1: cpu@1 {</div><div class='hunk'>@@ -176,6 +175,7 @@</div><div class='ctx'> 				 &lt;&amp;apmixedsys CLK_APMIXED_MAINPLL&gt;;</div><div class='ctx'> 			clock-names = "cpu", "intermediate";</div><div class='ctx'> 			operating-points-v2 = &lt;&amp;cluster0_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;740&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu2: cpu@100 {</div><div class='hunk'>@@ -190,6 +190,7 @@</div><div class='ctx'> 				 &lt;&amp;apmixedsys CLK_APMIXED_MAINPLL&gt;;</div><div class='ctx'> 			clock-names = "cpu", "intermediate";</div><div class='ctx'> 			operating-points-v2 = &lt;&amp;cluster1_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu3: cpu@101 {</div><div class='hunk'>@@ -204,6 +205,7 @@</div><div class='ctx'> 				 &lt;&amp;apmixedsys CLK_APMIXED_MAINPLL&gt;;</div><div class='ctx'> 			clock-names = "cpu", "intermediate";</div><div class='ctx'> 			operating-points-v2 = &lt;&amp;cluster1_opp&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		idle-states {</div><div class='hunk'>@@ -220,14 +222,14 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pmu_a53 {</div><div class='add'>+	pmu-a53 {</div><div class='ctx'> 		compatible = "arm,cortex-a53-pmu";</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 8 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='ctx'> 			     &lt;GIC_SPI 9 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 		interrupt-affinity = &lt;&amp;cpu0&gt;, &lt;&amp;cpu1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	pmu_a72 {</div><div class='add'>+	pmu-a72 {</div><div class='ctx'> 		compatible = "arm,cortex-a72-pmu";</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 12 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='ctx'> 			     &lt;GIC_SPI 13 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='hunk'>@@ -237,26 +239,26 @@</div><div class='ctx'> 	psci {</div><div class='ctx'> 		compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";</div><div class='ctx'> 		method = "smc";</div><div class='del'>-		cpu_suspend   = &lt;0x84000001&gt;;</div><div class='del'>-		cpu_off	      = &lt;0x84000002&gt;;</div><div class='del'>-		cpu_on	      = &lt;0x84000003&gt;;</div><div class='add'>+		cpu_suspend = &lt;0x84000001&gt;;</div><div class='add'>+		cpu_off	 = &lt;0x84000002&gt;;</div><div class='add'>+		cpu_on	 = &lt;0x84000003&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	clk26m: oscillator@0 {</div><div class='add'>+	clk26m: oscillator0 {</div><div class='ctx'> 		compatible = "fixed-clock";</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='ctx'> 		clock-frequency = &lt;26000000&gt;;</div><div class='ctx'> 		clock-output-names = "clk26m";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	clk32k: oscillator@1 {</div><div class='add'>+	clk32k: oscillator1 {</div><div class='ctx'> 		compatible = "fixed-clock";</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='ctx'> 		clock-frequency = &lt;32000&gt;;</div><div class='ctx'> 		clock-output-names = "clk32k";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	cpum_ck: oscillator@2 {</div><div class='add'>+	cpum_ck: oscillator2 {</div><div class='ctx'> 		compatible = "fixed-clock";</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='ctx'> 		clock-frequency = &lt;0&gt;;</div><div class='hunk'>@@ -264,7 +266,7 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	thermal-zones {</div><div class='del'>-		cpu_thermal: cpu_thermal {</div><div class='add'>+		cpu_thermal: cpu-thermal {</div><div class='ctx'> 			polling-delay-passive = &lt;1000&gt;; /* milliseconds */</div><div class='ctx'> 			polling-delay = &lt;1000&gt;; /* milliseconds */</div><div class='ctx'> </div><div class='hunk'>@@ -272,19 +274,19 @@</div><div class='ctx'> 			sustainable-power = &lt;1500&gt;; /* milliwatts */</div><div class='ctx'> </div><div class='ctx'> 			trips {</div><div class='del'>-				threshold: trip-point@0 {</div><div class='add'>+				threshold: trip-point0 {</div><div class='ctx'> 					temperature = &lt;68000&gt;;</div><div class='ctx'> 					hysteresis = &lt;2000&gt;;</div><div class='ctx'> 					type = "passive";</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				target: trip-point@1 {</div><div class='add'>+				target: trip-point1 {</div><div class='ctx'> 					temperature = &lt;85000&gt;;</div><div class='ctx'> 					hysteresis = &lt;2000&gt;;</div><div class='ctx'> 					type = "passive";</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				cpu_crit: cpu_crit@0 {</div><div class='add'>+				cpu_crit: cpu-crit0 {</div><div class='ctx'> 					temperature = &lt;115000&gt;;</div><div class='ctx'> 					hysteresis = &lt;2000&gt;;</div><div class='ctx'> 					type = "critical";</div><div class='hunk'>@@ -292,16 +294,20 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			cooling-maps {</div><div class='del'>-				map@0 {</div><div class='add'>+				map0 {</div><div class='ctx'> 					trip = &lt;&amp;target&gt;;</div><div class='del'>-					cooling-device = &lt;&amp;cpu0 0 0&gt;,</div><div class='del'>-							 &lt;&amp;cpu1 0 0&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT</div><div class='add'>+							  THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu1 THERMAL_NO_LIMIT</div><div class='add'>+							  THERMAL_NO_LIMIT&gt;;</div><div class='ctx'> 					contribution = &lt;3072&gt;;</div><div class='ctx'> 				};</div><div class='del'>-				map@1 {</div><div class='add'>+				map1 {</div><div class='ctx'> 					trip = &lt;&amp;target&gt;;</div><div class='del'>-					cooling-device = &lt;&amp;cpu2 0 0&gt;,</div><div class='del'>-							 &lt;&amp;cpu3 0 0&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu2 THERMAL_NO_LIMIT</div><div class='add'>+							  THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu3 THERMAL_NO_LIMIT</div><div class='add'>+							  THERMAL_NO_LIMIT&gt;;</div><div class='ctx'> 					contribution = &lt;1024&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> 			};</div><div class='hunk'>@@ -312,7 +318,15 @@</div><div class='ctx'> 		#address-cells = &lt;2&gt;;</div><div class='ctx'> 		#size-cells = &lt;2&gt;;</div><div class='ctx'> 		ranges;</div><div class='del'>-		vpu_dma_reserved: vpu_dma_mem_region {</div><div class='add'>+</div><div class='add'>+		afe_dma_mem: audio-dma-pool {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			size = &lt;0 0x100000&gt;;</div><div class='add'>+			alignment = &lt;0 0x10&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vpu_dma_reserved: vpu-dma-mem@b7000000 {</div><div class='ctx'> 			compatible = "shared-dma-pool";</div><div class='ctx'> 			reg = &lt;0 0xb7000000 0 0x500000&gt;;</div><div class='ctx'> 			alignment = &lt;0x1000&gt;;</div><div class='hunk'>@@ -346,30 +360,29 @@</div><div class='ctx'> 			#clock-cells = &lt;1&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		infracfg: power-controller@10001000 {</div><div class='add'>+		infracfg: clock-controller@10001000 {</div><div class='ctx'> 			compatible = "mediatek,mt8173-infracfg", "syscon";</div><div class='ctx'> 			reg = &lt;0 0x10001000 0 0x1000&gt;;</div><div class='ctx'> 			#clock-cells = &lt;1&gt;;</div><div class='ctx'> 			#reset-cells = &lt;1&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		pericfg: power-controller@10003000 {</div><div class='add'>+		pericfg: clock-controller@10003000 {</div><div class='ctx'> 			compatible = "mediatek,mt8173-pericfg", "syscon";</div><div class='ctx'> 			reg = &lt;0 0x10003000 0 0x1000&gt;;</div><div class='ctx'> 			#clock-cells = &lt;1&gt;;</div><div class='ctx'> 			#reset-cells = &lt;1&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		syscfg_pctl_a: syscfg_pctl_a@10005000 {</div><div class='add'>+		syscfg_pctl_a: syscon@10005000 {</div><div class='ctx'> 			compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";</div><div class='ctx'> 			reg = &lt;0 0x10005000 0 0x1000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		pio: pinctrl@10005000 {</div><div class='add'>+		pio: pinctrl@1000b000 {</div><div class='ctx'> 			compatible = "mediatek,mt8173-pinctrl";</div><div class='ctx'> 			reg = &lt;0 0x1000b000 0 0x1000&gt;;</div><div class='ctx'> 			mediatek,pctl-regmap = &lt;&amp;syscfg_pctl_a&gt;;</div><div class='del'>-			pins-are-numbered;</div><div class='ctx'> 			gpio-controller;</div><div class='ctx'> 			#gpio-cells = &lt;2&gt;;</div><div class='ctx'> 			interrupt-controller;</div><div class='hunk'>@@ -437,16 +450,81 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		scpsys: power-controller@10006000 {</div><div class='del'>-			compatible = "mediatek,mt8173-scpsys";</div><div class='del'>-			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+		scpsys: syscon@10006000 {</div><div class='add'>+			compatible = "mediatek,mt8173-scpsys", "syscon", "simple-mfd";</div><div class='ctx'> 			reg = &lt;0 0x10006000 0 0x1000&gt;;</div><div class='del'>-			clocks = &lt;&amp;clk26m&gt;,</div><div class='del'>-				 &lt;&amp;topckgen CLK_TOP_MM_SEL&gt;,</div><div class='del'>-				 &lt;&amp;topckgen CLK_TOP_VENC_SEL&gt;,</div><div class='del'>-				 &lt;&amp;topckgen CLK_TOP_VENC_LT_SEL&gt;;</div><div class='del'>-			clock-names = "mfg", "mm", "venc", "venc_lt";</div><div class='del'>-			infracfg = &lt;&amp;infracfg&gt;;</div><div class='add'>+</div><div class='add'>+			/* System Power Manager */</div><div class='add'>+			spm: power-controller {</div><div class='add'>+				compatible = "mediatek,mt8173-power-controller";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				/* power domains of the SoC */</div><div class='add'>+				power-domain@MT8173_POWER_DOMAIN_VDEC {</div><div class='add'>+					reg = &lt;MT8173_POWER_DOMAIN_VDEC&gt;;</div><div class='add'>+					clocks = &lt;&amp;topckgen CLK_TOP_MM_SEL&gt;;</div><div class='add'>+					clock-names = "mm";</div><div class='add'>+					#power-domain-cells = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+				power-domain@MT8173_POWER_DOMAIN_VENC {</div><div class='add'>+					reg = &lt;MT8173_POWER_DOMAIN_VENC&gt;;</div><div class='add'>+					clocks = &lt;&amp;topckgen CLK_TOP_MM_SEL&gt;,</div><div class='add'>+						 &lt;&amp;topckgen CLK_TOP_VENC_SEL&gt;;</div><div class='add'>+					clock-names = "mm", "venc";</div><div class='add'>+					#power-domain-cells = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+				power-domain@MT8173_POWER_DOMAIN_ISP {</div><div class='add'>+					reg = &lt;MT8173_POWER_DOMAIN_ISP&gt;;</div><div class='add'>+					clocks = &lt;&amp;topckgen CLK_TOP_MM_SEL&gt;;</div><div class='add'>+					clock-names = "mm";</div><div class='add'>+					#power-domain-cells = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+				power-domain@MT8173_POWER_DOMAIN_MM {</div><div class='add'>+					reg = &lt;MT8173_POWER_DOMAIN_MM&gt;;</div><div class='add'>+					clocks = &lt;&amp;topckgen CLK_TOP_MM_SEL&gt;;</div><div class='add'>+					clock-names = "mm";</div><div class='add'>+					#power-domain-cells = &lt;0&gt;;</div><div class='add'>+					mediatek,infracfg = &lt;&amp;infracfg&gt;;</div><div class='add'>+				};</div><div class='add'>+				power-domain@MT8173_POWER_DOMAIN_VENC_LT {</div><div class='add'>+					reg = &lt;MT8173_POWER_DOMAIN_VENC_LT&gt;;</div><div class='add'>+					clocks = &lt;&amp;topckgen CLK_TOP_MM_SEL&gt;,</div><div class='add'>+						 &lt;&amp;topckgen CLK_TOP_VENC_LT_SEL&gt;;</div><div class='add'>+					clock-names = "mm", "venclt";</div><div class='add'>+					#power-domain-cells = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+				power-domain@MT8173_POWER_DOMAIN_AUDIO {</div><div class='add'>+					reg = &lt;MT8173_POWER_DOMAIN_AUDIO&gt;;</div><div class='add'>+					#power-domain-cells = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+				power-domain@MT8173_POWER_DOMAIN_USB {</div><div class='add'>+					reg = &lt;MT8173_POWER_DOMAIN_USB&gt;;</div><div class='add'>+					#power-domain-cells = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+				mfg_async: power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {</div><div class='add'>+					reg = &lt;MT8173_POWER_DOMAIN_MFG_ASYNC&gt;;</div><div class='add'>+					clocks = &lt;&amp;clk26m&gt;;</div><div class='add'>+					clock-names = "mfg";</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+					#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					power-domain@MT8173_POWER_DOMAIN_MFG_2D {</div><div class='add'>+						reg = &lt;MT8173_POWER_DOMAIN_MFG_2D&gt;;</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+						#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						power-domain@MT8173_POWER_DOMAIN_MFG {</div><div class='add'>+							reg = &lt;MT8173_POWER_DOMAIN_MFG&gt;;</div><div class='add'>+							#power-domain-cells = &lt;0&gt;;</div><div class='add'>+							mediatek,infracfg = &lt;&amp;infracfg&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		watchdog: watchdog@10007000 {</div><div class='hunk'>@@ -494,7 +572,7 @@</div><div class='ctx'> 			memory-region = &lt;&amp;vpu_dma_reserved&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		sysirq: intpol-controller@10200620 {</div><div class='add'>+		sysirq: interrupt-controller@10200620 {</div><div class='ctx'> 			compatible = "mediatek,mt8173-sysirq",</div><div class='ctx'> 				     "mediatek,mt6577-sysirq";</div><div class='ctx'> 			interrupt-controller;</div><div class='hunk'>@@ -509,8 +587,9 @@</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 139 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;infracfg CLK_INFRA_M4U&gt;;</div><div class='ctx'> 			clock-names = "bclk";</div><div class='del'>-			mediatek,larbs = &lt;&amp;larb0 &amp;larb1 &amp;larb2</div><div class='del'>-					  &amp;larb3 &amp;larb4 &amp;larb5&gt;;</div><div class='add'>+			mediatek,infracfg = &lt;&amp;infracfg&gt;;</div><div class='add'>+			mediatek,larbs = &lt;&amp;larb0&gt;, &lt;&amp;larb1&gt;, &lt;&amp;larb2&gt;,</div><div class='add'>+					 &lt;&amp;larb3&gt;, &lt;&amp;larb4&gt;, &lt;&amp;larb5&gt;;</div><div class='ctx'> 			#iommu-cells = &lt;1&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -519,6 +598,15 @@</div><div class='ctx'> 			reg = &lt;0 0x10206000 0 0x1000&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			socinfo-data1@40 {</div><div class='add'>+				reg = &lt;0x040 0x4&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			socinfo-data2@44 {</div><div class='add'>+				reg = &lt;0x044 0x4&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='ctx'> 			thermal_calibration: calib@528 {</div><div class='ctx'> 				reg = &lt;0x528 0xc&gt;;</div><div class='ctx'> 			};</div><div class='hunk'>@@ -549,10 +637,10 @@</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 135 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;infracfg CLK_INFRA_GCE&gt;;</div><div class='ctx'> 			clock-names = "gce";</div><div class='del'>-			#mbox-cells = &lt;3&gt;;</div><div class='add'>+			#mbox-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		mipi_tx0: mipi-dphy@10215000 {</div><div class='add'>+		mipi_tx0: dsi-phy@10215000 {</div><div class='ctx'> 			compatible = "mediatek,mt8173-mipi-tx";</div><div class='ctx'> 			reg = &lt;0 0x10215000 0 0x1000&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;clk26m&gt;;</div><div class='hunk'>@@ -562,7 +650,7 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		mipi_tx1: mipi-dphy@10216000 {</div><div class='add'>+		mipi_tx1: dsi-phy@10216000 {</div><div class='ctx'> 			compatible = "mediatek,mt8173-mipi-tx";</div><div class='ctx'> 			reg = &lt;0 0x10216000 0 0x1000&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;clk26m&gt;;</div><div class='hunk'>@@ -572,7 +660,7 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		gic: interrupt-controller@10220000 {</div><div class='add'>+		gic: interrupt-controller@10221000 {</div><div class='ctx'> 			compatible = "arm,gic-400";</div><div class='ctx'> 			#interrupt-cells = &lt;3&gt;;</div><div class='ctx'> 			interrupt-parent = &lt;&amp;gic&gt;;</div><div class='hunk'>@@ -711,9 +799,12 @@</div><div class='ctx'> 		nor_flash: spi@1100d000 {</div><div class='ctx'> 			compatible = "mediatek,mt8173-nor";</div><div class='ctx'> 			reg = &lt;0 0x1100d000 0 0xe0&gt;;</div><div class='add'>+			assigned-clocks = &lt;&amp;topckgen CLK_TOP_SPI_SEL&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;clk26m&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;pericfg CLK_PERI_SPI&gt;,</div><div class='del'>-				 &lt;&amp;topckgen CLK_TOP_SPINFI_IFR_SEL&gt;;</div><div class='del'>-			clock-names = "spi", "sf";</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SPINFI_IFR_SEL&gt;,</div><div class='add'>+				 &lt;&amp;pericfg CLK_PERI_NFI&gt;;</div><div class='add'>+			clock-names = "spi", "sf", "axi";</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='hunk'>@@ -779,7 +870,7 @@</div><div class='ctx'> 			compatible = "mediatek,mt8173-afe-pcm";</div><div class='ctx'> 			reg = &lt;0 0x11220000 0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 134 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='del'>-			power-domains = &lt;&amp;scpsys MT8173_POWER_DOMAIN_AUDIO&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8173_POWER_DOMAIN_AUDIO&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;infracfg CLK_INFRA_AUDIO&gt;,</div><div class='ctx'> 				 &lt;&amp;topckgen CLK_TOP_AUDIO_SEL&gt;,</div><div class='ctx'> 				 &lt;&amp;topckgen CLK_TOP_AUD_INTBUS_SEL&gt;,</div><div class='hunk'>@@ -804,6 +895,7 @@</div><div class='ctx'> 					  &lt;&amp;topckgen CLK_TOP_AUD_2_SEL&gt;;</div><div class='ctx'> 			assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_APLL1&gt;,</div><div class='ctx'> 						 &lt;&amp;topckgen CLK_TOP_APLL2&gt;;</div><div class='add'>+			memory-region = &lt;&amp;afe_dma_mem&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		mmc0: mmc@11230000 {</div><div class='hunk'>@@ -847,7 +939,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		ssusb: usb@11271000 {</div><div class='del'>-			compatible = "mediatek,mt8173-mtu3";</div><div class='add'>+			compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3";</div><div class='ctx'> 			reg = &lt;0 0x11271000 0 0x3000&gt;,</div><div class='ctx'> 			      &lt;0 0x11280700 0 0x0100&gt;;</div><div class='ctx'> 			reg-names = "mac", "ippc";</div><div class='hunk'>@@ -855,7 +947,7 @@</div><div class='ctx'> 			phys = &lt;&amp;u2port0 PHY_TYPE_USB2&gt;,</div><div class='ctx'> 			       &lt;&amp;u3port0 PHY_TYPE_USB3&gt;,</div><div class='ctx'> 			       &lt;&amp;u2port1 PHY_TYPE_USB2&gt;;</div><div class='del'>-			power-domains = &lt;&amp;scpsys MT8173_POWER_DOMAIN_USB&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8173_POWER_DOMAIN_USB&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;topckgen CLK_TOP_USB30_SEL&gt;, &lt;&amp;clk26m&gt;;</div><div class='ctx'> 			clock-names = "sys_ck", "ref_ck";</div><div class='ctx'> 			mediatek,syscon-wakeup = &lt;&amp;pericfg 0x400 1&gt;;</div><div class='hunk'>@@ -864,19 +956,20 @@</div><div class='ctx'> 			ranges;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> </div><div class='del'>-			usb_host: xhci@11270000 {</div><div class='del'>-				compatible = "mediatek,mt8173-xhci";</div><div class='add'>+			usb_host: usb@11270000 {</div><div class='add'>+				compatible = "mediatek,mt8173-xhci",</div><div class='add'>+					     "mediatek,mtk-xhci";</div><div class='ctx'> 				reg = &lt;0 0x11270000 0 0x1000&gt;;</div><div class='ctx'> 				reg-names = "mac";</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 115 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='del'>-				power-domains = &lt;&amp;scpsys MT8173_POWER_DOMAIN_USB&gt;;</div><div class='add'>+				power-domains = &lt;&amp;spm MT8173_POWER_DOMAIN_USB&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;topckgen CLK_TOP_USB30_SEL&gt;, &lt;&amp;clk26m&gt;;</div><div class='ctx'> 				clock-names = "sys_ck", "ref_ck";</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		u3phy: usb-phy@11290000 {</div><div class='add'>+		u3phy: t-phy@11290000 {</div><div class='ctx'> 			compatible = "mediatek,mt8173-u3phy";</div><div class='ctx'> 			reg = &lt;0 0x11290000 0 0x800&gt;;</div><div class='ctx'> 			#address-cells = &lt;2&gt;;</div><div class='hunk'>@@ -909,13 +1002,17 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		mmsys: clock-controller@14000000 {</div><div class='add'>+		mmsys: syscon@14000000 {</div><div class='ctx'> 			compatible = "mediatek,mt8173-mmsys", "syscon";</div><div class='ctx'> 			reg = &lt;0 0x14000000 0 0x1000&gt;;</div><div class='del'>-			power-domains = &lt;&amp;scpsys MT8173_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8173_POWER_DOMAIN_MM&gt;;</div><div class='ctx'> 			assigned-clocks = &lt;&amp;topckgen CLK_TOP_MM_SEL&gt;;</div><div class='ctx'> 			assigned-clock-rates = &lt;400000000&gt;;</div><div class='ctx'> 			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+			mboxes = &lt;&amp;gce 0 CMDQ_THR_PRIO_HIGHEST&gt;,</div><div class='add'>+				 &lt;&amp;gce 1 CMDQ_THR_PRIO_HIGHEST&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1400XXXX 0 0x1000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		mdp_rdma0: rdma@14001000 {</div><div class='hunk'>@@ -924,9 +1021,8 @@</div><div class='ctx'> 			reg = &lt;0 0x14001000 0 0x1000&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;mmsys CLK_MM_MDP_RDMA0&gt;,</div><div class='ctx'> 				 &lt;&amp;mmsys CLK_MM_MUTEX_32K&gt;;</div><div class='del'>-			power-domains = &lt;&amp;scpsys MT8173_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8173_POWER_DOMAIN_MM&gt;;</div><div class='ctx'> 			iommus = &lt;&amp;iommu M4U_PORT_MDP_RDMA0&gt;;</div><div class='del'>-			mediatek,larb = &lt;&amp;larb0&gt;;</div><div class='ctx'> 			mediatek,vpu = &lt;&amp;vpu&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -935,179 +1031,179 @@</div><div class='ctx'> 			reg = &lt;0 0x14002000 0 0x1000&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;mmsys CLK_MM_MDP_RDMA1&gt;,</div><div class='ctx'> 				 &lt;&amp;mmsys CLK_MM_MUTEX_32K&gt;;</div><div class='del'>-			power-domains = &lt;&amp;scpsys MT8173_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8173_POWER_DOMAIN_MM&gt;;</div><div class='ctx'> 			iommus = &lt;&amp;iommu M4U_PORT_MDP_RDMA1&gt;;</div><div class='del'>-			mediatek,larb = &lt;&amp;larb4&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		mdp_rsz0: rsz@14003000 {</div><div class='ctx'> 			compatible = "mediatek,mt8173-mdp-rsz";</div><div class='ctx'> 			reg = &lt;0 0x14003000 0 0x1000&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;mmsys CLK_MM_MDP_RSZ0&gt;;</div><div class='del'>-			power-domains = &lt;&amp;scpsys MT8173_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8173_POWER_DOMAIN_MM&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		mdp_rsz1: rsz@14004000 {</div><div class='ctx'> 			compatible = "mediatek,mt8173-mdp-rsz";</div><div class='ctx'> 			reg = &lt;0 0x14004000 0 0x1000&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;mmsys CLK_MM_MDP_RSZ1&gt;;</div><div class='del'>-			power-domains = &lt;&amp;scpsys MT8173_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8173_POWER_DOMAIN_MM&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		mdp_rsz2: rsz@14005000 {</div><div class='ctx'> 			compatible = "mediatek,mt8173-mdp-rsz";</div><div class='ctx'> 			reg = &lt;0 0x14005000 0 0x1000&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;mmsys CLK_MM_MDP_RSZ2&gt;;</div><div class='del'>-			power-domains = &lt;&amp;scpsys MT8173_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8173_POWER_DOMAIN_MM&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		mdp_wdma0: wdma@14006000 {</div><div class='ctx'> 			compatible = "mediatek,mt8173-mdp-wdma";</div><div class='ctx'> 			reg = &lt;0 0x14006000 0 0x1000&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;mmsys CLK_MM_MDP_WDMA&gt;;</div><div class='del'>-			power-domains = &lt;&amp;scpsys MT8173_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8173_POWER_DOMAIN_MM&gt;;</div><div class='ctx'> 			iommus = &lt;&amp;iommu M4U_PORT_MDP_WDMA&gt;;</div><div class='del'>-			mediatek,larb = &lt;&amp;larb0&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		mdp_wrot0: wrot@14007000 {</div><div class='ctx'> 			compatible = "mediatek,mt8173-mdp-wrot";</div><div class='ctx'> 			reg = &lt;0 0x14007000 0 0x1000&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;mmsys CLK_MM_MDP_WROT0&gt;;</div><div class='del'>-			power-domains = &lt;&amp;scpsys MT8173_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8173_POWER_DOMAIN_MM&gt;;</div><div class='ctx'> 			iommus = &lt;&amp;iommu M4U_PORT_MDP_WROT0&gt;;</div><div class='del'>-			mediatek,larb = &lt;&amp;larb0&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		mdp_wrot1: wrot@14008000 {</div><div class='ctx'> 			compatible = "mediatek,mt8173-mdp-wrot";</div><div class='ctx'> 			reg = &lt;0 0x14008000 0 0x1000&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;mmsys CLK_MM_MDP_WROT1&gt;;</div><div class='del'>-			power-domains = &lt;&amp;scpsys MT8173_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8173_POWER_DOMAIN_MM&gt;;</div><div class='ctx'> 			iommus = &lt;&amp;iommu M4U_PORT_MDP_WROT1&gt;;</div><div class='del'>-			mediatek,larb = &lt;&amp;larb4&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		ovl0: ovl@1400c000 {</div><div class='ctx'> 			compatible = "mediatek,mt8173-disp-ovl";</div><div class='ctx'> 			reg = &lt;0 0x1400c000 0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 180 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='del'>-			power-domains = &lt;&amp;scpsys MT8173_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8173_POWER_DOMAIN_MM&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;mmsys CLK_MM_DISP_OVL0&gt;;</div><div class='ctx'> 			iommus = &lt;&amp;iommu M4U_PORT_DISP_OVL0&gt;;</div><div class='del'>-			mediatek,larb = &lt;&amp;larb0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1400XXXX 0xc000 0x1000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		ovl1: ovl@1400d000 {</div><div class='ctx'> 			compatible = "mediatek,mt8173-disp-ovl";</div><div class='ctx'> 			reg = &lt;0 0x1400d000 0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 181 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='del'>-			power-domains = &lt;&amp;scpsys MT8173_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8173_POWER_DOMAIN_MM&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;mmsys CLK_MM_DISP_OVL1&gt;;</div><div class='ctx'> 			iommus = &lt;&amp;iommu M4U_PORT_DISP_OVL1&gt;;</div><div class='del'>-			mediatek,larb = &lt;&amp;larb4&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1400XXXX 0xd000 0x1000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		rdma0: rdma@1400e000 {</div><div class='ctx'> 			compatible = "mediatek,mt8173-disp-rdma";</div><div class='ctx'> 			reg = &lt;0 0x1400e000 0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 182 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='del'>-			power-domains = &lt;&amp;scpsys MT8173_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8173_POWER_DOMAIN_MM&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;mmsys CLK_MM_DISP_RDMA0&gt;;</div><div class='ctx'> 			iommus = &lt;&amp;iommu M4U_PORT_DISP_RDMA0&gt;;</div><div class='del'>-			mediatek,larb = &lt;&amp;larb0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1400XXXX 0xe000 0x1000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		rdma1: rdma@1400f000 {</div><div class='ctx'> 			compatible = "mediatek,mt8173-disp-rdma";</div><div class='ctx'> 			reg = &lt;0 0x1400f000 0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 183 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='del'>-			power-domains = &lt;&amp;scpsys MT8173_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8173_POWER_DOMAIN_MM&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;mmsys CLK_MM_DISP_RDMA1&gt;;</div><div class='ctx'> 			iommus = &lt;&amp;iommu M4U_PORT_DISP_RDMA1&gt;;</div><div class='del'>-			mediatek,larb = &lt;&amp;larb4&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1400XXXX 0xf000 0x1000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		rdma2: rdma@14010000 {</div><div class='ctx'> 			compatible = "mediatek,mt8173-disp-rdma";</div><div class='ctx'> 			reg = &lt;0 0x14010000 0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 184 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='del'>-			power-domains = &lt;&amp;scpsys MT8173_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8173_POWER_DOMAIN_MM&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;mmsys CLK_MM_DISP_RDMA2&gt;;</div><div class='ctx'> 			iommus = &lt;&amp;iommu M4U_PORT_DISP_RDMA2&gt;;</div><div class='del'>-			mediatek,larb = &lt;&amp;larb4&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1401XXXX 0 0x1000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		wdma0: wdma@14011000 {</div><div class='ctx'> 			compatible = "mediatek,mt8173-disp-wdma";</div><div class='ctx'> 			reg = &lt;0 0x14011000 0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 185 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='del'>-			power-domains = &lt;&amp;scpsys MT8173_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8173_POWER_DOMAIN_MM&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;mmsys CLK_MM_DISP_WDMA0&gt;;</div><div class='ctx'> 			iommus = &lt;&amp;iommu M4U_PORT_DISP_WDMA0&gt;;</div><div class='del'>-			mediatek,larb = &lt;&amp;larb0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1401XXXX 0x1000 0x1000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		wdma1: wdma@14012000 {</div><div class='ctx'> 			compatible = "mediatek,mt8173-disp-wdma";</div><div class='ctx'> 			reg = &lt;0 0x14012000 0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 186 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='del'>-			power-domains = &lt;&amp;scpsys MT8173_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8173_POWER_DOMAIN_MM&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;mmsys CLK_MM_DISP_WDMA1&gt;;</div><div class='ctx'> 			iommus = &lt;&amp;iommu M4U_PORT_DISP_WDMA1&gt;;</div><div class='del'>-			mediatek,larb = &lt;&amp;larb4&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1401XXXX 0x2000 0x1000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		color0: color@14013000 {</div><div class='ctx'> 			compatible = "mediatek,mt8173-disp-color";</div><div class='ctx'> 			reg = &lt;0 0x14013000 0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 187 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='del'>-			power-domains = &lt;&amp;scpsys MT8173_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8173_POWER_DOMAIN_MM&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;mmsys CLK_MM_DISP_COLOR0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1401XXXX 0x3000 0x1000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		color1: color@14014000 {</div><div class='ctx'> 			compatible = "mediatek,mt8173-disp-color";</div><div class='ctx'> 			reg = &lt;0 0x14014000 0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 188 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='del'>-			power-domains = &lt;&amp;scpsys MT8173_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8173_POWER_DOMAIN_MM&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;mmsys CLK_MM_DISP_COLOR1&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1401XXXX 0x4000 0x1000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		aal@14015000 {</div><div class='ctx'> 			compatible = "mediatek,mt8173-disp-aal";</div><div class='ctx'> 			reg = &lt;0 0x14015000 0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 189 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='del'>-			power-domains = &lt;&amp;scpsys MT8173_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8173_POWER_DOMAIN_MM&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;mmsys CLK_MM_DISP_AAL&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1401XXXX 0x5000 0x1000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		gamma@14016000 {</div><div class='ctx'> 			compatible = "mediatek,mt8173-disp-gamma";</div><div class='ctx'> 			reg = &lt;0 0x14016000 0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 190 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='del'>-			power-domains = &lt;&amp;scpsys MT8173_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8173_POWER_DOMAIN_MM&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;mmsys CLK_MM_DISP_GAMMA&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1401XXXX 0x6000 0x1000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		merge@14017000 {</div><div class='ctx'> 			compatible = "mediatek,mt8173-disp-merge";</div><div class='ctx'> 			reg = &lt;0 0x14017000 0 0x1000&gt;;</div><div class='del'>-			power-domains = &lt;&amp;scpsys MT8173_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8173_POWER_DOMAIN_MM&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;mmsys CLK_MM_DISP_MERGE&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		split0: split@14018000 {</div><div class='ctx'> 			compatible = "mediatek,mt8173-disp-split";</div><div class='ctx'> 			reg = &lt;0 0x14018000 0 0x1000&gt;;</div><div class='del'>-			power-domains = &lt;&amp;scpsys MT8173_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8173_POWER_DOMAIN_MM&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;mmsys CLK_MM_DISP_SPLIT0&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		split1: split@14019000 {</div><div class='ctx'> 			compatible = "mediatek,mt8173-disp-split";</div><div class='ctx'> 			reg = &lt;0 0x14019000 0 0x1000&gt;;</div><div class='del'>-			power-domains = &lt;&amp;scpsys MT8173_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8173_POWER_DOMAIN_MM&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;mmsys CLK_MM_DISP_SPLIT1&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -1115,19 +1211,21 @@</div><div class='ctx'> 			compatible = "mediatek,mt8173-disp-ufoe";</div><div class='ctx'> 			reg = &lt;0 0x1401a000 0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 191 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='del'>-			power-domains = &lt;&amp;scpsys MT8173_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8173_POWER_DOMAIN_MM&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;mmsys CLK_MM_DISP_UFOE&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1401XXXX 0xa000 0x1000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		dsi0: dsi@1401b000 {</div><div class='ctx'> 			compatible = "mediatek,mt8173-dsi";</div><div class='ctx'> 			reg = &lt;0 0x1401b000 0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 192 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='del'>-			power-domains = &lt;&amp;scpsys MT8173_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8173_POWER_DOMAIN_MM&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;mmsys CLK_MM_DSI0_ENGINE&gt;,</div><div class='ctx'> 				 &lt;&amp;mmsys CLK_MM_DSI0_DIGITAL&gt;,</div><div class='ctx'> 				 &lt;&amp;mipi_tx0&gt;;</div><div class='ctx'> 			clock-names = "engine", "digital", "hs";</div><div class='add'>+			resets = &lt;&amp;mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0&gt;;</div><div class='ctx'> 			phys = &lt;&amp;mipi_tx0&gt;;</div><div class='ctx'> 			phy-names = "dphy";</div><div class='ctx'> 			status = "disabled";</div><div class='hunk'>@@ -1137,12 +1235,12 @@</div><div class='ctx'> 			compatible = "mediatek,mt8173-dsi";</div><div class='ctx'> 			reg = &lt;0 0x1401c000 0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 193 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='del'>-			power-domains = &lt;&amp;scpsys MT8173_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8173_POWER_DOMAIN_MM&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;mmsys CLK_MM_DSI1_ENGINE&gt;,</div><div class='ctx'> 				 &lt;&amp;mmsys CLK_MM_DSI1_DIGITAL&gt;,</div><div class='ctx'> 				 &lt;&amp;mipi_tx1&gt;;</div><div class='ctx'> 			clock-names = "engine", "digital", "hs";</div><div class='del'>-			phy = &lt;&amp;mipi_tx1&gt;;</div><div class='add'>+			phys = &lt;&amp;mipi_tx1&gt;;</div><div class='ctx'> 			phy-names = "dphy";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='hunk'>@@ -1151,7 +1249,7 @@</div><div class='ctx'> 			compatible = "mediatek,mt8173-dpi";</div><div class='ctx'> 			reg = &lt;0 0x1401d000 0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 194 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='del'>-			power-domains = &lt;&amp;scpsys MT8173_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8173_POWER_DOMAIN_MM&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;mmsys CLK_MM_DPI_PIXEL&gt;,</div><div class='ctx'> 				 &lt;&amp;mmsys CLK_MM_DPI_ENGINE&gt;,</div><div class='ctx'> 				 &lt;&amp;apmixedsys CLK_APMIXED_TVDPLL&gt;;</div><div class='hunk'>@@ -1166,8 +1264,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		pwm0: pwm@1401e000 {</div><div class='del'>-			compatible = "mediatek,mt8173-disp-pwm",</div><div class='del'>-				     "mediatek,mt6595-disp-pwm";</div><div class='add'>+			compatible = "mediatek,mt8173-disp-pwm";</div><div class='ctx'> 			reg = &lt;0 0x1401e000 0 0x1000&gt;;</div><div class='ctx'> 			#pwm-cells = &lt;2&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;mmsys CLK_MM_DISP_PWM026M&gt;,</div><div class='hunk'>@@ -1177,8 +1274,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		pwm1: pwm@1401f000 {</div><div class='del'>-			compatible = "mediatek,mt8173-disp-pwm",</div><div class='del'>-				     "mediatek,mt6595-disp-pwm";</div><div class='add'>+			compatible = "mediatek,mt8173-disp-pwm";</div><div class='ctx'> 			reg = &lt;0 0x1401f000 0 0x1000&gt;;</div><div class='ctx'> 			#pwm-cells = &lt;2&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;mmsys CLK_MM_DISP_PWM126M&gt;,</div><div class='hunk'>@@ -1191,15 +1287,18 @@</div><div class='ctx'> 			compatible = "mediatek,mt8173-disp-mutex";</div><div class='ctx'> 			reg = &lt;0 0x14020000 0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 169 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='del'>-			power-domains = &lt;&amp;scpsys MT8173_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8173_POWER_DOMAIN_MM&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;mmsys CLK_MM_MUTEX_32K&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1402XXXX 0 0x1000&gt;;</div><div class='add'>+			mediatek,gce-events = &lt;CMDQ_EVENT_MUTEX0_STREAM_EOF&gt;,</div><div class='add'>+                                              &lt;CMDQ_EVENT_MUTEX1_STREAM_EOF&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		larb0: larb@14021000 {</div><div class='ctx'> 			compatible = "mediatek,mt8173-smi-larb";</div><div class='ctx'> 			reg = &lt;0 0x14021000 0 0x1000&gt;;</div><div class='ctx'> 			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='del'>-			power-domains = &lt;&amp;scpsys MT8173_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8173_POWER_DOMAIN_MM&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;mmsys CLK_MM_SMI_LARB0&gt;,</div><div class='ctx'> 				 &lt;&amp;mmsys CLK_MM_SMI_LARB0&gt;;</div><div class='ctx'> 			clock-names = "apb", "smi";</div><div class='hunk'>@@ -1208,7 +1307,7 @@</div><div class='ctx'> 		smi_common: smi@14022000 {</div><div class='ctx'> 			compatible = "mediatek,mt8173-smi-common";</div><div class='ctx'> 			reg = &lt;0 0x14022000 0 0x1000&gt;;</div><div class='del'>-			power-domains = &lt;&amp;scpsys MT8173_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8173_POWER_DOMAIN_MM&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;mmsys CLK_MM_SMI_COMMON&gt;,</div><div class='ctx'> 				 &lt;&amp;mmsys CLK_MM_SMI_COMMON&gt;;</div><div class='ctx'> 			clock-names = "apb", "smi";</div><div class='hunk'>@@ -1218,6 +1317,7 @@</div><div class='ctx'> 			compatible = "mediatek,mt8173-disp-od";</div><div class='ctx'> 			reg = &lt;0 0x14023000 0 0x1000&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;mmsys CLK_MM_DISP_OD&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1402XXXX 0x3000 0x1000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		hdmi0: hdmi@14025000 {</div><div class='hunk'>@@ -1256,7 +1356,7 @@</div><div class='ctx'> 			compatible = "mediatek,mt8173-smi-larb";</div><div class='ctx'> 			reg = &lt;0 0x14027000 0 0x1000&gt;;</div><div class='ctx'> 			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='del'>-			power-domains = &lt;&amp;scpsys MT8173_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8173_POWER_DOMAIN_MM&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;mmsys CLK_MM_SMI_LARB4&gt;,</div><div class='ctx'> 				 &lt;&amp;mmsys CLK_MM_SMI_LARB4&gt;;</div><div class='ctx'> 			clock-names = "apb", "smi";</div><div class='hunk'>@@ -1272,7 +1372,7 @@</div><div class='ctx'> 			compatible = "mediatek,mt8173-smi-larb";</div><div class='ctx'> 			reg = &lt;0 0x15001000 0 0x1000&gt;;</div><div class='ctx'> 			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='del'>-			power-domains = &lt;&amp;scpsys MT8173_POWER_DOMAIN_ISP&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8173_POWER_DOMAIN_ISP&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;imgsys CLK_IMG_LARB2_SMI&gt;,</div><div class='ctx'> 				 &lt;&amp;imgsys CLK_IMG_LARB2_SMI&gt;;</div><div class='ctx'> 			clock-names = "apb", "smi";</div><div class='hunk'>@@ -1284,10 +1384,9 @@</div><div class='ctx'> 			#clock-cells = &lt;1&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		vcodec_dec: vcodec@16000000 {</div><div class='add'>+		vcodec_dec: vcodec@16020000 {</div><div class='ctx'> 			compatible = "mediatek,mt8173-vcodec-dec";</div><div class='del'>-			reg = &lt;0 0x16000000 0 0x100&gt;,	/* VDEC_SYS */</div><div class='del'>-			      &lt;0 0x16020000 0 0x1000&gt;,	/* VDEC_MISC */</div><div class='add'>+			reg = &lt;0 0x16020000 0 0x1000&gt;,	/* VDEC_MISC */</div><div class='ctx'> 			      &lt;0 0x16021000 0 0x800&gt;,	/* VDEC_LD */</div><div class='ctx'> 			      &lt;0 0x16021800 0 0x800&gt;,	/* VDEC_TOP */</div><div class='ctx'> 			      &lt;0 0x16022000 0 0x1000&gt;,	/* VDEC_CM */</div><div class='hunk'>@@ -1298,8 +1397,9 @@</div><div class='ctx'> 			      &lt;0 0x16027000 0 0x800&gt;,	/* VDEC_HWQ */</div><div class='ctx'> 			      &lt;0 0x16027800 0 0x800&gt;,	/* VDEC_HWB */</div><div class='ctx'> 			      &lt;0 0x16028400 0 0x400&gt;;	/* VDEC_HWG */</div><div class='add'>+			reg-names = "misc", "ld", "top", "cm", "ad", "av", "pp",</div><div class='add'>+				    "hwd", "hwq", "hwb", "hwg";</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 204 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='del'>-			mediatek,larb = &lt;&amp;larb1&gt;;</div><div class='ctx'> 			iommus = &lt;&amp;iommu M4U_PORT_HW_VDEC_MC_EXT&gt;,</div><div class='ctx'> 				 &lt;&amp;iommu M4U_PORT_HW_VDEC_PP_EXT&gt;,</div><div class='ctx'> 				 &lt;&amp;iommu M4U_PORT_HW_VDEC_AVC_MV_EXT&gt;,</div><div class='hunk'>@@ -1309,7 +1409,8 @@</div><div class='ctx'> 				 &lt;&amp;iommu M4U_PORT_HW_VDEC_VLD_EXT&gt;,</div><div class='ctx'> 				 &lt;&amp;iommu M4U_PORT_HW_VDEC_VLD2_EXT&gt;;</div><div class='ctx'> 			mediatek,vpu = &lt;&amp;vpu&gt;;</div><div class='del'>-			power-domains = &lt;&amp;scpsys MT8173_POWER_DOMAIN_VDEC&gt;;</div><div class='add'>+			mediatek,vdecsys = &lt;&amp;vdecsys&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8173_POWER_DOMAIN_VDEC&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;apmixedsys CLK_APMIXED_VCODECPLL&gt;,</div><div class='ctx'> 				 &lt;&amp;topckgen CLK_TOP_UNIVPLL_D2&gt;,</div><div class='ctx'> 				 &lt;&amp;topckgen CLK_TOP_CCI400_SEL&gt;,</div><div class='hunk'>@@ -1341,7 +1442,7 @@</div><div class='ctx'> 			compatible = "mediatek,mt8173-smi-larb";</div><div class='ctx'> 			reg = &lt;0 0x16010000 0 0x1000&gt;;</div><div class='ctx'> 			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='del'>-			power-domains = &lt;&amp;scpsys MT8173_POWER_DOMAIN_VDEC&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8173_POWER_DOMAIN_VDEC&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;vdecsys CLK_VDEC_CKEN&gt;,</div><div class='ctx'> 				 &lt;&amp;vdecsys CLK_VDEC_LARB_CKEN&gt;;</div><div class='ctx'> 			clock-names = "apb", "smi";</div><div class='hunk'>@@ -1357,20 +1458,16 @@</div><div class='ctx'> 			compatible = "mediatek,mt8173-smi-larb";</div><div class='ctx'> 			reg = &lt;0 0x18001000 0 0x1000&gt;;</div><div class='ctx'> 			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='del'>-			power-domains = &lt;&amp;scpsys MT8173_POWER_DOMAIN_VENC&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8173_POWER_DOMAIN_VENC&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;vencsys CLK_VENC_CKE1&gt;,</div><div class='ctx'> 				 &lt;&amp;vencsys CLK_VENC_CKE0&gt;;</div><div class='ctx'> 			clock-names = "apb", "smi";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		vcodec_enc: vcodec@18002000 {</div><div class='add'>+		vcodec_enc_avc: vcodec@18002000 {</div><div class='ctx'> 			compatible = "mediatek,mt8173-vcodec-enc";</div><div class='del'>-			reg = &lt;0 0x18002000 0 0x1000&gt;,	/* VENC_SYS */</div><div class='del'>-			      &lt;0 0x19002000 0 0x1000&gt;;	/* VENC_LT_SYS */</div><div class='del'>-			interrupts = &lt;GIC_SPI 198 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='del'>-				     &lt;GIC_SPI 202 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='del'>-			mediatek,larb = &lt;&amp;larb3&gt;,</div><div class='del'>-					&lt;&amp;larb5&gt;;</div><div class='add'>+			reg = &lt;0 0x18002000 0 0x1000&gt;;	/* VENC_SYS */</div><div class='add'>+			interrupts = &lt;GIC_SPI 198 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 			iommus = &lt;&amp;iommu M4U_PORT_VENC_RCPU&gt;,</div><div class='ctx'> 				 &lt;&amp;iommu M4U_PORT_VENC_REC&gt;,</div><div class='ctx'> 				 &lt;&amp;iommu M4U_PORT_VENC_BSDMA&gt;,</div><div class='hunk'>@@ -1381,29 +1478,13 @@</div><div class='ctx'> 				 &lt;&amp;iommu M4U_PORT_VENC_REF_LUMA&gt;,</div><div class='ctx'> 				 &lt;&amp;iommu M4U_PORT_VENC_REF_CHROMA&gt;,</div><div class='ctx'> 				 &lt;&amp;iommu M4U_PORT_VENC_NBM_RDMA&gt;,</div><div class='del'>-				 &lt;&amp;iommu M4U_PORT_VENC_NBM_WDMA&gt;,</div><div class='del'>-				 &lt;&amp;iommu M4U_PORT_VENC_RCPU_SET2&gt;,</div><div class='del'>-				 &lt;&amp;iommu M4U_PORT_VENC_REC_FRM_SET2&gt;,</div><div class='del'>-				 &lt;&amp;iommu M4U_PORT_VENC_BSDMA_SET2&gt;,</div><div class='del'>-				 &lt;&amp;iommu M4U_PORT_VENC_SV_COMA_SET2&gt;,</div><div class='del'>-				 &lt;&amp;iommu M4U_PORT_VENC_RD_COMA_SET2&gt;,</div><div class='del'>-				 &lt;&amp;iommu M4U_PORT_VENC_CUR_LUMA_SET2&gt;,</div><div class='del'>-				 &lt;&amp;iommu M4U_PORT_VENC_CUR_CHROMA_SET2&gt;,</div><div class='del'>-				 &lt;&amp;iommu M4U_PORT_VENC_REF_LUMA_SET2&gt;,</div><div class='del'>-				 &lt;&amp;iommu M4U_PORT_VENC_REC_CHROMA_SET2&gt;;</div><div class='add'>+				 &lt;&amp;iommu M4U_PORT_VENC_NBM_WDMA&gt;;</div><div class='ctx'> 			mediatek,vpu = &lt;&amp;vpu&gt;;</div><div class='del'>-			clocks = &lt;&amp;topckgen CLK_TOP_VENCPLL_D2&gt;,</div><div class='del'>-				 &lt;&amp;topckgen CLK_TOP_VENC_SEL&gt;,</div><div class='del'>-				 &lt;&amp;topckgen CLK_TOP_UNIVPLL1_D2&gt;,</div><div class='del'>-				 &lt;&amp;topckgen CLK_TOP_VENC_LT_SEL&gt;;</div><div class='del'>-			clock-names = "venc_sel_src",</div><div class='del'>-				      "venc_sel",</div><div class='del'>-				      "venc_lt_sel_src",</div><div class='del'>-				      "venc_lt_sel";</div><div class='del'>-			assigned-clocks = &lt;&amp;topckgen CLK_TOP_VENC_SEL&gt;,</div><div class='del'>-					  &lt;&amp;topckgen CLK_TOP_VENC_LT_SEL&gt;;</div><div class='del'>-			assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_VENCPLL_D2&gt;,</div><div class='del'>-						 &lt;&amp;topckgen CLK_TOP_UNIVPLL1_D2&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_VENC_SEL&gt;;</div><div class='add'>+			clock-names = "venc_sel";</div><div class='add'>+			assigned-clocks = &lt;&amp;topckgen CLK_TOP_VENC_SEL&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_VCODECPLL&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8173_POWER_DOMAIN_VENC&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		jpegdec: jpegdec@18004000 {</div><div class='hunk'>@@ -1414,8 +1495,7 @@</div><div class='ctx'> 				 &lt;&amp;vencsys CLK_VENC_CKE3&gt;;</div><div class='ctx'> 			clock-names = "jpgdec-smi",</div><div class='ctx'> 				      "jpgdec";</div><div class='del'>-			power-domains = &lt;&amp;scpsys MT8173_POWER_DOMAIN_VENC&gt;;</div><div class='del'>-			mediatek,larb = &lt;&amp;larb3&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8173_POWER_DOMAIN_VENC&gt;;</div><div class='ctx'> 			iommus = &lt;&amp;iommu M4U_PORT_JPGDEC_WDMA&gt;,</div><div class='ctx'> 				 &lt;&amp;iommu M4U_PORT_JPGDEC_BSDMA&gt;;</div><div class='ctx'> 		};</div><div class='hunk'>@@ -1430,11 +1510,32 @@</div><div class='ctx'> 			compatible = "mediatek,mt8173-smi-larb";</div><div class='ctx'> 			reg = &lt;0 0x19001000 0 0x1000&gt;;</div><div class='ctx'> 			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='del'>-			power-domains = &lt;&amp;scpsys MT8173_POWER_DOMAIN_VENC_LT&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8173_POWER_DOMAIN_VENC_LT&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;vencltsys CLK_VENCLT_CKE1&gt;,</div><div class='ctx'> 				 &lt;&amp;vencltsys CLK_VENCLT_CKE0&gt;;</div><div class='ctx'> 			clock-names = "apb", "smi";</div><div class='ctx'> 		};</div><div class='add'>+</div><div class='add'>+		vcodec_enc_vp8: vcodec@19002000 {</div><div class='add'>+			compatible = "mediatek,mt8173-vcodec-enc-vp8";</div><div class='add'>+			reg = &lt;0 0x19002000 0 0x1000&gt;; /* VENC_LT_SYS */</div><div class='add'>+			interrupts = &lt;GIC_SPI 202 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu M4U_PORT_VENC_RCPU_SET2&gt;,</div><div class='add'>+				 &lt;&amp;iommu M4U_PORT_VENC_REC_FRM_SET2&gt;,</div><div class='add'>+				 &lt;&amp;iommu M4U_PORT_VENC_BSDMA_SET2&gt;,</div><div class='add'>+				 &lt;&amp;iommu M4U_PORT_VENC_SV_COMA_SET2&gt;,</div><div class='add'>+				 &lt;&amp;iommu M4U_PORT_VENC_RD_COMA_SET2&gt;,</div><div class='add'>+				 &lt;&amp;iommu M4U_PORT_VENC_CUR_LUMA_SET2&gt;,</div><div class='add'>+				 &lt;&amp;iommu M4U_PORT_VENC_CUR_CHROMA_SET2&gt;,</div><div class='add'>+				 &lt;&amp;iommu M4U_PORT_VENC_REF_LUMA_SET2&gt;,</div><div class='add'>+				 &lt;&amp;iommu M4U_PORT_VENC_REC_CHROMA_SET2&gt;;</div><div class='add'>+			mediatek,vpu = &lt;&amp;vpu&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_VENC_LT_SEL&gt;;</div><div class='add'>+			clock-names = "venc_lt_sel";</div><div class='add'>+			assigned-clocks = &lt;&amp;topckgen CLK_TOP_VENC_LT_SEL&gt;;</div><div class='add'>+			assigned-clock-parents =</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_VCODECPLL_370P5&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8173_POWER_DOMAIN_VENC_LT&gt;;</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='del'>-</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts<br/>index 1fb195c683c3..f04baea5d6cb 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183-evb.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-evb.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183-evb.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8183-evb.dts</a></div><div class='hunk'>@@ -7,9 +7,11 @@</div><div class='ctx'> </div><div class='ctx'> /dts-v1/;</div><div class='ctx'> #include "mt8183.dtsi"</div><div class='add'>+#include "mt6358.dtsi"</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	model = "MediaTek MT8183 evaluation board";</div><div class='add'>+	chassis-type = "embedded";</div><div class='ctx'> 	compatible = "mediatek,mt8183-evb", "mediatek,mt8183";</div><div class='ctx'> </div><div class='ctx'> 	aliases {</div><div class='hunk'>@@ -24,12 +26,35 @@</div><div class='ctx'> 	chosen {</div><div class='ctx'> 		stdout-path = "serial0:921600n8";</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+		scp_mem_reserved: memory@50000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x50000000 0 0x2900000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	thermal-sensor {</div><div class='add'>+		compatible = "murata,ncp03wf104";</div><div class='add'>+		pullup-uv = &lt;1800000&gt;;</div><div class='add'>+		pullup-ohm = &lt;390000&gt;;</div><div class='add'>+		pulldown-ohm = &lt;0&gt;;</div><div class='add'>+		io-channels = &lt;&amp;auxadc 0&gt;;</div><div class='add'>+	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;auxadc {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;gpu {</div><div class='add'>+	mali-supply = &lt;&amp;mt6358_vgpu_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;i2c0 {</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;i2c_pins_0&gt;;</div><div class='hunk'>@@ -72,63 +97,114 @@</div><div class='ctx'> 	clock-frequency = &lt;1000000&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;mmc0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-names = "default", "state_uhs";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc0_pins_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;mmc0_pins_uhs&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	cap-mmc-highspeed;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	mmc-hs400-1_8v;</div><div class='add'>+	cap-mmc-hw-reset;</div><div class='add'>+	no-sdio;</div><div class='add'>+	no-sd;</div><div class='add'>+	hs400-ds-delay = &lt;0x12814&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;mt6358_vemc_reg&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;mt6358_vio18_reg&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;topckgen CLK_TOP_MUX_MSDC50_0&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_MSDCPLL_CK&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-names = "default", "state_uhs";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc1_pins_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;mmc1_pins_uhs&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	sd-uhs-sdr50;</div><div class='add'>+	sd-uhs-sdr104;</div><div class='add'>+	cap-sdio-irq;</div><div class='add'>+	no-mmc;</div><div class='add'>+	no-sd;</div><div class='add'>+	vmmc-supply = &lt;&amp;mt6358_vmch_reg&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;mt6358_vmc_reg&gt;;</div><div class='add'>+	keep-power-in-suspend;</div><div class='add'>+	wakeup-source;</div><div class='add'>+	non-removable;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6358_vgpu_reg {</div><div class='add'>+	regulator-min-microvolt = &lt;625000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;900000&gt;;</div><div class='add'>+</div><div class='add'>+	regulator-coupled-with = &lt;&amp;mt6358_vsram_gpu_reg&gt;;</div><div class='add'>+	regulator-coupled-max-spread = &lt;100000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6358_vsram_gpu_reg {</div><div class='add'>+	regulator-min-microvolt = &lt;850000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+</div><div class='add'>+	regulator-coupled-with = &lt;&amp;mt6358_vgpu_reg&gt;;</div><div class='add'>+	regulator-coupled-max-spread = &lt;100000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;pio {</div><div class='del'>-	i2c_pins_0: i2c0{</div><div class='del'>-		pins_i2c{</div><div class='add'>+	i2c_pins_0: i2c0 {</div><div class='add'>+		pins_i2c {</div><div class='ctx'> 			pinmux = &lt;PINMUX_GPIO82__FUNC_SDA0&gt;,</div><div class='ctx'> 				 &lt;PINMUX_GPIO83__FUNC_SCL0&gt;;</div><div class='ctx'> 			mediatek,pull-up-adv = &lt;3&gt;;</div><div class='del'>-			mediatek,drive-strength-adv = &lt;00&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	i2c_pins_1: i2c1{</div><div class='del'>-		pins_i2c{</div><div class='add'>+	i2c_pins_1: i2c1 {</div><div class='add'>+		pins_i2c {</div><div class='ctx'> 			pinmux = &lt;PINMUX_GPIO81__FUNC_SDA1&gt;,</div><div class='ctx'> 				 &lt;PINMUX_GPIO84__FUNC_SCL1&gt;;</div><div class='ctx'> 			mediatek,pull-up-adv = &lt;3&gt;;</div><div class='del'>-			mediatek,drive-strength-adv = &lt;00&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	i2c_pins_2: i2c2{</div><div class='del'>-		pins_i2c{</div><div class='add'>+	i2c_pins_2: i2c2 {</div><div class='add'>+		pins_i2c {</div><div class='ctx'> 			pinmux = &lt;PINMUX_GPIO103__FUNC_SCL2&gt;,</div><div class='ctx'> 				 &lt;PINMUX_GPIO104__FUNC_SDA2&gt;;</div><div class='ctx'> 			mediatek,pull-up-adv = &lt;3&gt;;</div><div class='del'>-			mediatek,drive-strength-adv = &lt;00&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	i2c_pins_3: i2c3{</div><div class='del'>-		pins_i2c{</div><div class='add'>+	i2c_pins_3: i2c3 {</div><div class='add'>+		pins_i2c {</div><div class='ctx'> 			pinmux = &lt;PINMUX_GPIO50__FUNC_SCL3&gt;,</div><div class='ctx'> 				 &lt;PINMUX_GPIO51__FUNC_SDA3&gt;;</div><div class='ctx'> 			mediatek,pull-up-adv = &lt;3&gt;;</div><div class='del'>-			mediatek,drive-strength-adv = &lt;00&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	i2c_pins_4: i2c4{</div><div class='del'>-		pins_i2c{</div><div class='add'>+	i2c_pins_4: i2c4 {</div><div class='add'>+		pins_i2c {</div><div class='ctx'> 			pinmux = &lt;PINMUX_GPIO105__FUNC_SCL4&gt;,</div><div class='ctx'> 				 &lt;PINMUX_GPIO106__FUNC_SDA4&gt;;</div><div class='ctx'> 			mediatek,pull-up-adv = &lt;3&gt;;</div><div class='del'>-			mediatek,drive-strength-adv = &lt;00&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	i2c_pins_5: i2c5{</div><div class='del'>-		pins_i2c{</div><div class='add'>+	i2c_pins_5: i2c5 {</div><div class='add'>+		pins_i2c {</div><div class='ctx'> 			pinmux = &lt;PINMUX_GPIO48__FUNC_SCL5&gt;,</div><div class='ctx'> 				 &lt;PINMUX_GPIO49__FUNC_SDA5&gt;;</div><div class='ctx'> 			mediatek,pull-up-adv = &lt;3&gt;;</div><div class='del'>-			mediatek,drive-strength-adv = &lt;00&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	spi_pins_0: spi0{</div><div class='del'>-		pins_spi{</div><div class='add'>+	spi_pins_0: spi0 {</div><div class='add'>+		pins_spi {</div><div class='ctx'> 			pinmux = &lt;PINMUX_GPIO85__FUNC_SPI0_MI&gt;,</div><div class='ctx'> 				 &lt;PINMUX_GPIO86__FUNC_SPI0_CSB&gt;,</div><div class='ctx'> 				 &lt;PINMUX_GPIO87__FUNC_SPI0_MO&gt;,</div><div class='hunk'>@@ -137,8 +213,113 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	spi_pins_1: spi1{</div><div class='del'>-		pins_spi{</div><div class='add'>+	mmc0_pins_default: mmc0default {</div><div class='add'>+		pins_cmd_dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO123__FUNC_MSDC0_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO128__FUNC_MSDC0_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO125__FUNC_MSDC0_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO132__FUNC_MSDC0_DAT3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO126__FUNC_MSDC0_DAT4&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO129__FUNC_MSDC0_DAT5&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO127__FUNC_MSDC0_DAT6&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO130__FUNC_MSDC0_DAT7&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO122__FUNC_MSDC0_CMD&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins_clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO124__FUNC_MSDC0_CLK&gt;;</div><div class='add'>+			bias-pull-down;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins_rst {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO133__FUNC_MSDC0_RSTB&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc0_pins_uhs: mmc0 {</div><div class='add'>+		pins_cmd_dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO123__FUNC_MSDC0_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO128__FUNC_MSDC0_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO125__FUNC_MSDC0_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO132__FUNC_MSDC0_DAT3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO126__FUNC_MSDC0_DAT4&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO129__FUNC_MSDC0_DAT5&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO127__FUNC_MSDC0_DAT6&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO130__FUNC_MSDC0_DAT7&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO122__FUNC_MSDC0_CMD&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;MTK_DRIVE_10mA&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins_clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO124__FUNC_MSDC0_CLK&gt;;</div><div class='add'>+			drive-strength = &lt;MTK_DRIVE_10mA&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins_ds {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO131__FUNC_MSDC0_DSL&gt;;</div><div class='add'>+			drive-strength = &lt;MTK_DRIVE_10mA&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins_rst {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO133__FUNC_MSDC0_RSTB&gt;;</div><div class='add'>+			drive-strength = &lt;MTK_DRIVE_10mA&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc1_pins_default: mmc1default {</div><div class='add'>+		pins_cmd_dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO31__FUNC_MSDC1_CMD&gt;,</div><div class='add'>+				   &lt;PINMUX_GPIO32__FUNC_MSDC1_DAT0&gt;,</div><div class='add'>+				   &lt;PINMUX_GPIO34__FUNC_MSDC1_DAT1&gt;,</div><div class='add'>+				   &lt;PINMUX_GPIO33__FUNC_MSDC1_DAT2&gt;,</div><div class='add'>+				   &lt;PINMUX_GPIO30__FUNC_MSDC1_DAT3&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins_clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO29__FUNC_MSDC1_CLK&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-down;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins_pmu {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO178__FUNC_GPIO178&gt;,</div><div class='add'>+				   &lt;PINMUX_GPIO166__FUNC_GPIO166&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc1_pins_uhs: mmc1 {</div><div class='add'>+		pins_cmd_dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO31__FUNC_MSDC1_CMD&gt;,</div><div class='add'>+				   &lt;PINMUX_GPIO32__FUNC_MSDC1_DAT0&gt;,</div><div class='add'>+				   &lt;PINMUX_GPIO34__FUNC_MSDC1_DAT1&gt;,</div><div class='add'>+				   &lt;PINMUX_GPIO33__FUNC_MSDC1_DAT2&gt;,</div><div class='add'>+				   &lt;PINMUX_GPIO30__FUNC_MSDC1_DAT3&gt;;</div><div class='add'>+			drive-strength = &lt;MTK_DRIVE_6mA&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins_clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO29__FUNC_MSDC1_CLK&gt;;</div><div class='add'>+			drive-strength = &lt;MTK_DRIVE_6mA&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi_pins_1: spi1 {</div><div class='add'>+		pins_spi {</div><div class='ctx'> 			pinmux = &lt;PINMUX_GPIO161__FUNC_SPI1_A_MI&gt;,</div><div class='ctx'> 				 &lt;PINMUX_GPIO162__FUNC_SPI1_A_CSB&gt;,</div><div class='ctx'> 				 &lt;PINMUX_GPIO163__FUNC_SPI1_A_MO&gt;,</div><div class='hunk'>@@ -147,8 +328,8 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	spi_pins_2: spi2{</div><div class='del'>-		pins_spi{</div><div class='add'>+	spi_pins_2: spi2 {</div><div class='add'>+		pins_spi {</div><div class='ctx'> 			pinmux = &lt;PINMUX_GPIO0__FUNC_SPI2_CSB&gt;,</div><div class='ctx'> 				 &lt;PINMUX_GPIO1__FUNC_SPI2_MO&gt;,</div><div class='ctx'> 				 &lt;PINMUX_GPIO2__FUNC_SPI2_CLK&gt;,</div><div class='hunk'>@@ -157,8 +338,8 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	spi_pins_3: spi3{</div><div class='del'>-		pins_spi{</div><div class='add'>+	spi_pins_3: spi3 {</div><div class='add'>+		pins_spi {</div><div class='ctx'> 			pinmux = &lt;PINMUX_GPIO21__FUNC_SPI3_MI&gt;,</div><div class='ctx'> 				 &lt;PINMUX_GPIO22__FUNC_SPI3_CSB&gt;,</div><div class='ctx'> 				 &lt;PINMUX_GPIO23__FUNC_SPI3_MO&gt;,</div><div class='hunk'>@@ -167,8 +348,8 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	spi_pins_4: spi4{</div><div class='del'>-		pins_spi{</div><div class='add'>+	spi_pins_4: spi4 {</div><div class='add'>+		pins_spi {</div><div class='ctx'> 			pinmux = &lt;PINMUX_GPIO17__FUNC_SPI4_MI&gt;,</div><div class='ctx'> 				 &lt;PINMUX_GPIO18__FUNC_SPI4_CSB&gt;,</div><div class='ctx'> 				 &lt;PINMUX_GPIO19__FUNC_SPI4_MO&gt;,</div><div class='hunk'>@@ -177,8 +358,8 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	spi_pins_5: spi5{</div><div class='del'>-		pins_spi{</div><div class='add'>+	spi_pins_5: spi5 {</div><div class='add'>+		pins_spi {</div><div class='ctx'> 			pinmux = &lt;PINMUX_GPIO13__FUNC_SPI5_MI&gt;,</div><div class='ctx'> 				 &lt;PINMUX_GPIO14__FUNC_SPI5_CSB&gt;,</div><div class='ctx'> 				 &lt;PINMUX_GPIO15__FUNC_SPI5_MO&gt;,</div><div class='hunk'>@@ -186,6 +367,20 @@</div><div class='ctx'> 			bias-disable;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	pwm_pins_1: pwm1 {</div><div class='add'>+		pins_pwm {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO90__FUNC_PWM_A&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pmic {</div><div class='add'>+	interrupts-extended = &lt;&amp;pio 182 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mfg {</div><div class='add'>+	domain-supply = &lt;&amp;mt6358_vgpu_reg&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;spi0 {</div><div class='hunk'>@@ -231,6 +426,48 @@</div><div class='ctx'> </div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;cci {</div><div class='add'>+	proc-supply = &lt;&amp;mt6358_vproc12_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	proc-supply = &lt;&amp;mt6358_vproc12_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu1 {</div><div class='add'>+	proc-supply = &lt;&amp;mt6358_vproc12_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu2 {</div><div class='add'>+	proc-supply = &lt;&amp;mt6358_vproc12_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu3 {</div><div class='add'>+	proc-supply = &lt;&amp;mt6358_vproc12_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu4 {</div><div class='add'>+	proc-supply = &lt;&amp;mt6358_vproc11_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu5 {</div><div class='add'>+	proc-supply = &lt;&amp;mt6358_vproc11_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu6 {</div><div class='add'>+	proc-supply = &lt;&amp;mt6358_vproc11_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu7 {</div><div class='add'>+	proc-supply = &lt;&amp;mt6358_vproc11_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;uart0 {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='add'>+</div><div class='add'>+&amp;pwm1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm_pins_1&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219-max98357a.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219-max98357a.dtsi<br/>new file mode 100644<br/>index 000000000000..e4aeea4599f5<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219-max98357a.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219-max98357a.dtsi</a></div><div class='hunk'>@@ -0,0 +1,13 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Google Kukui (and derivatives) da7219-max98357a sound card.</div><div class='add'>+ *</div><div class='add'>+ * Copyright 2019 Google LLC.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "mt8183-kukui-audio-da7219.dtsi"</div><div class='add'>+#include "mt8183-kukui-audio-max98357a.dtsi"</div><div class='add'>+</div><div class='add'>+&amp;sound {</div><div class='add'>+	compatible = "mediatek,mt8183_da7219_max98357";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219-rt1015p.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219-rt1015p.dtsi<br/>new file mode 100644<br/>index 000000000000..16ce5a3612ee<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219-rt1015p.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219-rt1015p.dtsi</a></div><div class='hunk'>@@ -0,0 +1,13 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Google Kukui (and derivatives) da7219-rt1015p sound card.</div><div class='add'>+ *</div><div class='add'>+ * Copyright 2020 Google LLC.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "mt8183-kukui-audio-da7219.dtsi"</div><div class='add'>+#include "mt8183-kukui-audio-rt1015p.dtsi"</div><div class='add'>+</div><div class='add'>+&amp;sound {</div><div class='add'>+	compatible = "mediatek,mt8183_da7219_rt1015p";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219.dtsi<br/>new file mode 100644<br/>index 000000000000..f69ffcb9792a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219.dtsi</a></div><div class='hunk'>@@ -0,0 +1,53 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Google Kukui (and derivatives) audio fragment for da7219.</div><div class='add'>+ *</div><div class='add'>+ * Copyright 2020 Google LLC.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;i2c5 {</div><div class='add'>+	da7219: da7219@1a {</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;da7219_pins&gt;;</div><div class='add'>+		compatible = "dlg,da7219";</div><div class='add'>+		reg = &lt;0x1a&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 165 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		dlg,micbias-lvl = &lt;2600&gt;;</div><div class='add'>+		dlg,mic-amp-in-sel = "diff";</div><div class='add'>+		VDD-supply = &lt;&amp;pp1800_alw&gt;;</div><div class='add'>+		VDDMIC-supply = &lt;&amp;pp3300_alw&gt;;</div><div class='add'>+		VDDIO-supply = &lt;&amp;pp1800_alw&gt;;</div><div class='add'>+</div><div class='add'>+		status = "okay";</div><div class='add'>+</div><div class='add'>+		da7219_aad {</div><div class='add'>+			dlg,adc-1bit-rpt = &lt;1&gt;;</div><div class='add'>+			dlg,btn-avg = &lt;4&gt;;</div><div class='add'>+			dlg,btn-cfg = &lt;50&gt;;</div><div class='add'>+			dlg,mic-det-thr = &lt;500&gt;;</div><div class='add'>+			dlg,jack-ins-deb = &lt;20&gt;;</div><div class='add'>+			dlg,jack-det-rate = "32_64";</div><div class='add'>+			dlg,jack-rem-deb = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			dlg,a-d-btn-thr = &lt;0xa&gt;;</div><div class='add'>+			dlg,d-b-btn-thr = &lt;0x16&gt;;</div><div class='add'>+			dlg,b-c-btn-thr = &lt;0x21&gt;;</div><div class='add'>+			dlg,c-mic-btn-thr = &lt;0x3E&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	da7219_pins: da7219-pins {</div><div class='add'>+		pins-intn {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO165__FUNC_GPIO165&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sound {</div><div class='add'>+	mediatek,headset-codec = &lt;&amp;da7219&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-max98357a.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-max98357a.dtsi<br/>new file mode 100644<br/>index 000000000000..2b60967c0c1c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-max98357a.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-max98357a.dtsi</a></div><div class='hunk'>@@ -0,0 +1,13 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Google Kukui (and derivatives) audio fragment for max98357a.</div><div class='add'>+ *</div><div class='add'>+ * Copyright 2020 Google LLC.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	max98357a: max98357a {</div><div class='add'>+		compatible = "maxim,max98357a";</div><div class='add'>+		sdmode-gpios = &lt;&amp;pio 175 0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-rt1015p.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-rt1015p.dtsi<br/>new file mode 100644<br/>index 000000000000..658a764fe9ee<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-rt1015p.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-rt1015p.dtsi</a></div><div class='hunk'>@@ -0,0 +1,13 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Google Kukui (and derivatives) audio fragment for rt1015p.</div><div class='add'>+ *</div><div class='add'>+ * Copyright 2020 Google LLC.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	rt1015p: rt1015p {</div><div class='add'>+		compatible = "realtek,rt1015p";</div><div class='add'>+		sdb-gpios = &lt;&amp;pio 175 0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e-max98357a.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e-max98357a.dtsi<br/>new file mode 100644<br/>index 000000000000..260a5f561495<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e-max98357a.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e-max98357a.dtsi</a></div><div class='hunk'>@@ -0,0 +1,13 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Google Kukui (and derivatives) ts3a227e-max98357a sound card.</div><div class='add'>+ *</div><div class='add'>+ * Copyright 2020 Google LLC.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "mt8183-kukui-audio-max98357a.dtsi"</div><div class='add'>+#include "mt8183-kukui-audio-ts3a227e.dtsi"</div><div class='add'>+</div><div class='add'>+&amp;sound {</div><div class='add'>+	compatible = "mediatek,mt8183_mt6358_ts3a227_max98357";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e-rt1015p.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e-rt1015p.dtsi<br/>new file mode 100644<br/>index 000000000000..2f7d1fa1c90f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e-rt1015p.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e-rt1015p.dtsi</a></div><div class='hunk'>@@ -0,0 +1,13 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Google Kukui (and derivatives) mt6358-ts3a227-rt1015p sound card.</div><div class='add'>+ *</div><div class='add'>+ * Copyright 2021 Google LLC.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "mt8183-kukui-audio-ts3a227e.dtsi"</div><div class='add'>+#include "mt8183-kukui-audio-rt1015p.dtsi"</div><div class='add'>+</div><div class='add'>+&amp;sound {</div><div class='add'>+	compatible = "mediatek,mt8183_mt6358_ts3a227_rt1015p";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e.dtsi<br/>new file mode 100644<br/>index 000000000000..c4aedf8cbfcd<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e.dtsi</a></div><div class='hunk'>@@ -0,0 +1,31 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Google Kukui (and derivatives) audio fragment for ts3a227e.</div><div class='add'>+ *</div><div class='add'>+ * Copyright 2019 Google LLC.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;i2c5 {</div><div class='add'>+	ts3a227e: ts3a227e@3b {</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;ts3a227e_pins&gt;;</div><div class='add'>+		compatible = "ti,ts3a227e";</div><div class='add'>+		reg = &lt;0x3b&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 157 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	ts3a227e_pins: ts3a227e-pins {</div><div class='add'>+		pins1 {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO157__FUNC_GPIO157&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sound {</div><div class='add'>+	mediatek,headset-codec = &lt;&amp;ts3a227e&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts<br/>new file mode 100644<br/>index 000000000000..20b71f2e7159<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts</a></div><div class='hunk'>@@ -0,0 +1,35 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8183-kukui-jacuzzi.dtsi"</div><div class='add'>+#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google burnet board";</div><div class='add'>+	chassis-type = "convertible";</div><div class='add'>+	compatible = "google,burnet", "mediatek,mt8183";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6358codec {</div><div class='add'>+	mediatek,dmic-mode = &lt;1&gt;; /* one-wire */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	touchscreen@2c {</div><div class='add'>+		compatible = "hid-over-i2c";</div><div class='add'>+		reg = &lt;0x2c&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;touchscreen_pins&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 155 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		post-power-on-delay-ms = &lt;200&gt;;</div><div class='add'>+		hid-descr-addr = &lt;0x0020&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	i2c-scl-internal-delay-ns = &lt;4100&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dts<br/>new file mode 100644<br/>index 000000000000..83bbcfe62083<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dts</a></div><div class='hunk'>@@ -0,0 +1,39 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8183-kukui-jacuzzi.dtsi"</div><div class='add'>+#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google cozmo board";</div><div class='add'>+	chassis-type = "laptop";</div><div class='add'>+	compatible = "google,cozmo", "mediatek,mt8183";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c_tunnel {</div><div class='add'>+	google,remote-bus = &lt;0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	i2c-scl-internal-delay-ns = &lt;25000&gt;;</div><div class='add'>+</div><div class='add'>+	trackpad@2c {</div><div class='add'>+		compatible = "hid-over-i2c";</div><div class='add'>+		reg = &lt;0x2c&gt;;</div><div class='add'>+		hid-descr-addr = &lt;0x20&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;trackpad_pins&gt;;</div><div class='add'>+</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 7 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		wakeup-source;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qca_wifi {</div><div class='add'>+	qcom,ath10k-calibration-variant = "GO_COZMO";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts<br/>new file mode 100644<br/>index 000000000000..7bc7c2687d6f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts</a></div><div class='hunk'>@@ -0,0 +1,36 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8183-kukui-jacuzzi.dtsi"</div><div class='add'>+#include "mt8183-kukui-audio-da7219-max98357a.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google damu board";</div><div class='add'>+	chassis-type = "convertible";</div><div class='add'>+	compatible = "google,damu", "mediatek,mt8183";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;touchscreen {</div><div class='add'>+	compatible = "elan,ekth6a12nay";</div><div class='add'>+</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;touchscreen_pins&gt;;</div><div class='add'>+</div><div class='add'>+	vcc33-supply = &lt;&amp;pp3300_alw&gt;;</div><div class='add'>+	vccio-supply = &lt;&amp;pp1800_alw&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6358codec {</div><div class='add'>+	mediatek,dmic-mode = &lt;1&gt;; /* one-wire */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qca_wifi {</div><div class='add'>+	qcom,ath10k-calibration-variant = "GO_DAMU";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	i2c-scl-internal-delay-ns = &lt;20000&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts<br/>new file mode 100644<br/>index 000000000000..863f3e403de8<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts</a></div><div class='hunk'>@@ -0,0 +1,41 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8183-kukui-jacuzzi-fennel.dtsi"</div><div class='add'>+#include "mt8183-kukui-audio-da7219-rt1015p.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google fennel sku1 board";</div><div class='add'>+	chassis-type = "convertible";</div><div class='add'>+	compatible = "google,fennel-sku1", "google,fennel", "mediatek,mt8183";</div><div class='add'>+</div><div class='add'>+	pwmleds {</div><div class='add'>+		compatible = "pwm-leds";</div><div class='add'>+		keyboard_backlight: led-0 {</div><div class='add'>+			label = "cros_ec::kbd_backlight";</div><div class='add'>+			pwms = &lt;&amp;cros_ec_pwm 0&gt;;</div><div class='add'>+			max-brightness = &lt;1023&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cros_ec_pwm {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;touchscreen {</div><div class='add'>+	compatible = "elan,ekth6a12nay";</div><div class='add'>+</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;touchscreen_pins&gt;;</div><div class='add'>+</div><div class='add'>+	vcc33-supply = &lt;&amp;pp3300_alw&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qca_wifi {</div><div class='add'>+	qcom,ath10k-calibration-variant = "GO_FENNEL";</div><div class='add'>+};</div><div class='add'>+</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts<br/>new file mode 100644<br/>index 000000000000..e0a583ce4a0b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts</a></div><div class='hunk'>@@ -0,0 +1,29 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8183-kukui-jacuzzi-fennel.dtsi"</div><div class='add'>+#include "mt8183-kukui-audio-da7219-rt1015p.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google fennel sku6 board";</div><div class='add'>+	chassis-type = "convertible";</div><div class='add'>+	compatible = "google,fennel-sku6", "google,fennel", "mediatek,mt8183";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;touchscreen {</div><div class='add'>+	compatible = "elan,ekth6a12nay";</div><div class='add'>+</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;touchscreen_pins&gt;;</div><div class='add'>+</div><div class='add'>+	vcc33-supply = &lt;&amp;pp3300_alw&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+&amp;qca_wifi {</div><div class='add'>+	qcom,ath10k-calibration-variant = "GO_FENNEL";</div><div class='add'>+};</div><div class='add'>+</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts<br/>new file mode 100644<br/>index 000000000000..7874c9a20e12<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts</a></div><div class='hunk'>@@ -0,0 +1,29 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8183-kukui-jacuzzi-fennel.dtsi"</div><div class='add'>+#include "mt8183-kukui-audio-ts3a227e-rt1015p.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google fennel sku7 board";</div><div class='add'>+	chassis-type = "convertible";</div><div class='add'>+	compatible = "google,fennel-sku7", "google,fennel", "mediatek,mt8183";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;touchscreen {</div><div class='add'>+	compatible = "elan,ekth6a12nay";</div><div class='add'>+</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;touchscreen_pins&gt;;</div><div class='add'>+</div><div class='add'>+	vcc33-supply = &lt;&amp;pp3300_alw&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+&amp;qca_wifi {</div><div class='add'>+	qcom,ath10k-calibration-variant = "GO_FENNEL";</div><div class='add'>+};</div><div class='add'>+</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel.dtsi<br/>new file mode 100644<br/>index 000000000000..f9c1ec366b26<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel.dtsi</a></div><div class='hunk'>@@ -0,0 +1,30 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8183-kukui-jacuzzi.dtsi"</div><div class='add'>+</div><div class='add'>+&amp;mt6358codec {</div><div class='add'>+	mediatek,dmic-mode = &lt;1&gt;; /* one-wire */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	trackpad@2c {</div><div class='add'>+		compatible = "hid-over-i2c";</div><div class='add'>+		reg = &lt;0x2c&gt;;</div><div class='add'>+		hid-descr-addr = &lt;0x20&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;trackpad_pins&gt;;</div><div class='add'>+</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 7 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		wakeup-source;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	i2c-scl-internal-delay-ns = &lt;21500&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14-sku2.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14-sku2.dts<br/>new file mode 100644<br/>index 000000000000..877256eab262<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14-sku2.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14-sku2.dts</a></div><div class='hunk'>@@ -0,0 +1,18 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8183-kukui-jacuzzi-fennel.dtsi"</div><div class='add'>+#include "mt8183-kukui-audio-ts3a227e-rt1015p.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google fennel14 sku2 board";</div><div class='add'>+	chassis-type = "laptop";</div><div class='add'>+	compatible = "google,fennel-sku2", "google,fennel", "mediatek,mt8183";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qca_wifi {</div><div class='add'>+	qcom,ath10k-calibration-variant = "GO_FENNEL14";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts<br/>new file mode 100644<br/>index 000000000000..b981dd31a430<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts</a></div><div class='hunk'>@@ -0,0 +1,18 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8183-kukui-jacuzzi-fennel.dtsi"</div><div class='add'>+#include "mt8183-kukui-audio-da7219-rt1015p.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google fennel14 sku0 board";</div><div class='add'>+	chassis-type = "laptop";</div><div class='add'>+	compatible = "google,fennel-sku0", "google,fennel", "mediatek,mt8183";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qca_wifi {</div><div class='add'>+	qcom,ath10k-calibration-variant = "GO_FENNEL14";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts<br/>new file mode 100644<br/>index 000000000000..8ac6bf5b17f9<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts</a></div><div class='hunk'>@@ -0,0 +1,15 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8183-kukui-jacuzzi-juniper.dtsi"</div><div class='add'>+#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google juniper sku16 board";</div><div class='add'>+	chassis-type = "convertible";</div><div class='add'>+	compatible = "google,juniper-sku16", "google,juniper", "mediatek,mt8183";</div><div class='add'>+};</div><div class='add'>+</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper.dtsi<br/>new file mode 100644<br/>index 000000000000..078bc765646f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper.dtsi</a></div><div class='hunk'>@@ -0,0 +1,27 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8183-kukui-jacuzzi.dtsi"</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	trackpad@2c {</div><div class='add'>+		compatible = "hid-over-i2c";</div><div class='add'>+		reg = &lt;0x2c&gt;;</div><div class='add'>+		hid-descr-addr = &lt;0x20&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;trackpad_pins&gt;;</div><div class='add'>+</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 7 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		wakeup-source;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qca_wifi {</div><div class='add'>+	qcom,ath10k-calibration-variant = "GO_JUNIPER";</div><div class='add'>+};</div><div class='add'>+</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dts<br/>new file mode 100644<br/>index 000000000000..f3ac9c074226<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dts</a></div><div class='hunk'>@@ -0,0 +1,18 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8183-kukui-jacuzzi.dtsi"</div><div class='add'>+#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google kappa board";</div><div class='add'>+	chassis-type = "laptop";</div><div class='add'>+	compatible = "google,kappa", "mediatek,mt8183";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6358codec {</div><div class='add'>+	mediatek,dmic-mode = &lt;1&gt;; /* one-wire */</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts<br/>new file mode 100644<br/>index 000000000000..561770fcf69e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts</a></div><div class='hunk'>@@ -0,0 +1,29 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8183-kukui-jacuzzi-juniper.dtsi"</div><div class='add'>+#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google kenzo sku17 board";</div><div class='add'>+	chassis-type = "laptop";</div><div class='add'>+	compatible = "google,juniper-sku17", "google,juniper", "mediatek,mt8183";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	touchscreen@40 {</div><div class='add'>+		compatible = "hid-over-i2c";</div><div class='add'>+		reg = &lt;0x40&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;touchscreen_pins&gt;;</div><div class='add'>+</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 155 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		post-power-on-delay-ms = &lt;70&gt;;</div><div class='add'>+		hid-descr-addr = &lt;0x0001&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku0.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku0.dts<br/>new file mode 100644<br/>index 000000000000..ddb993521bbf<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku0.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku0.dts</a></div><div class='hunk'>@@ -0,0 +1,24 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8183-kukui-jacuzzi-fennel.dtsi"</div><div class='add'>+#include "mt8183-kukui-audio-da7219-rt1015p.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google makomo sku0 board";</div><div class='add'>+	chassis-type = "laptop";</div><div class='add'>+	compatible = "google,makomo-sku0", "google,makomo", "mediatek,mt8183";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qca_wifi {</div><div class='add'>+	qcom,ath10k-calibration-variant = "GO_FENNEL14";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc1_pins_uhs {</div><div class='add'>+	pins-clk {</div><div class='add'>+		drive-strength = &lt;6&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku1.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku1.dts<br/>new file mode 100644<br/>index 000000000000..10c4f920a7d8<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku1.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku1.dts</a></div><div class='hunk'>@@ -0,0 +1,24 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8183-kukui-jacuzzi-fennel.dtsi"</div><div class='add'>+#include "mt8183-kukui-audio-ts3a227e-rt1015p.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google makomo sku1 board";</div><div class='add'>+	chassis-type = "laptop";</div><div class='add'>+	compatible = "google,makomo-sku1", "google,makomo", "mediatek,mt8183";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qca_wifi {</div><div class='add'>+	qcom,ath10k-calibration-variant = "GO_FENNEL14";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc1_pins_uhs {</div><div class='add'>+	pins-clk {</div><div class='add'>+		drive-strength = &lt;6&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico.dts<br/>new file mode 100644<br/>index 000000000000..8ce9568fee95<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico.dts</a></div><div class='hunk'>@@ -0,0 +1,35 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8183-kukui-jacuzzi.dtsi"</div><div class='add'>+#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google pico board";</div><div class='add'>+	chassis-type = "convertible";</div><div class='add'>+	compatible = "google,pico-sku1", "google,pico", "mediatek,mt8183";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c_tunnel {</div><div class='add'>+	google,remote-bus = &lt;0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	i2c-scl-internal-delay-ns = &lt;25000&gt;;</div><div class='add'>+</div><div class='add'>+	trackpad@2c {</div><div class='add'>+		compatible = "hid-over-i2c";</div><div class='add'>+		reg = &lt;0x2c&gt;;</div><div class='add'>+		hid-descr-addr = &lt;0x20&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;trackpad_pins&gt;;</div><div class='add'>+</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 7 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		wakeup-source;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico6.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico6.dts<br/>new file mode 100644<br/>index 000000000000..cce326aec1aa<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico6.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico6.dts</a></div><div class='hunk'>@@ -0,0 +1,109 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8183-kukui-jacuzzi.dtsi"</div><div class='add'>+#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google pico6 board";</div><div class='add'>+	chassis-type = "convertible";</div><div class='add'>+	compatible = "google,pico-sku2", "google,pico", "mediatek,mt8183";</div><div class='add'>+</div><div class='add'>+	bt_wakeup: bt-wakeup {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;bt_pins_wakeup&gt;;</div><div class='add'>+</div><div class='add'>+		event-wobt {</div><div class='add'>+			label = "Wake on BT";</div><div class='add'>+			gpios = &lt;&amp;pio 42 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,code = &lt;KEY_WAKEUP&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c_tunnel {</div><div class='add'>+	google,remote-bus = &lt;0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	i2c-scl-internal-delay-ns = &lt;25000&gt;;</div><div class='add'>+</div><div class='add'>+	trackpad@2c {</div><div class='add'>+		compatible = "hid-over-i2c";</div><div class='add'>+		reg = &lt;0x2c&gt;;</div><div class='add'>+		hid-descr-addr = &lt;0x20&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;trackpad_pins&gt;;</div><div class='add'>+</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 7 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		wakeup-source;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wifi_wakeup_event {</div><div class='add'>+	gpios = &lt;&amp;pio 113 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wifi_pwrseq {</div><div class='add'>+	post-power-on-delay-ms = &lt;50&gt;;</div><div class='add'>+</div><div class='add'>+	/* Toggle WIFI_ENABLE to reset the chip. */</div><div class='add'>+	reset-gpios = &lt;&amp;pio 8 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wifi_pins_pwrseq {</div><div class='add'>+	pins-wifi-enable {</div><div class='add'>+		pinmux = &lt;PINMUX_GPIO8__FUNC_GPIO8&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc1_pins_default {</div><div class='add'>+	pins-cmd-dat {</div><div class='add'>+		drive-strength = &lt;6&gt;;</div><div class='add'>+	};</div><div class='add'>+	pins-clk {</div><div class='add'>+		drive-strength = &lt;6&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc1_pins_uhs {</div><div class='add'>+	pins-clk {</div><div class='add'>+		drive-strength = &lt;6&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc1 {</div><div class='add'>+	bluetooth@2 {</div><div class='add'>+		reg = &lt;2&gt;;</div><div class='add'>+		compatible = "mediatek,mt7921s-bluetooth";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;bt_pins_reset&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pio 120 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	bt_pins_wakeup: bt-pins-wakeup {</div><div class='add'>+		piins-bt-wakeup {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO42__FUNC_GPIO42&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bt_pins_reset: bt-pins-reset {</div><div class='add'>+		pins-bt-reset {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO120__FUNC_GPIO120&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/delete-node/ &amp;bluetooth;</div><div class='add'>+/delete-node/ &amp;bt_pins;</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts<br/>new file mode 100644<br/>index 000000000000..928b205a616a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts</a></div><div class='hunk'>@@ -0,0 +1,15 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8183-kukui-jacuzzi-willow.dtsi"</div><div class='add'>+#include "mt8183-kukui-audio-da7219-max98357a.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google willow board sku0";</div><div class='add'>+	chassis-type = "laptop";</div><div class='add'>+	compatible = "google,willow-sku0", "google,willow", "mediatek,mt8183";</div><div class='add'>+};</div><div class='add'>+</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts<br/>new file mode 100644<br/>index 000000000000..71307a8052d6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8183-kukui-jacuzzi-willow.dtsi"</div><div class='add'>+#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google willow board sku1";</div><div class='add'>+	chassis-type = "laptop";</div><div class='add'>+	compatible = "google,willow-sku1", "google,willow", "mediatek,mt8183";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow.dtsi<br/>new file mode 100644<br/>index 000000000000..c942e461a177<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow.dtsi</a></div><div class='hunk'>@@ -0,0 +1,41 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8183-kukui-jacuzzi.dtsi"</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	touchscreen@40 {</div><div class='add'>+		compatible = "hid-over-i2c";</div><div class='add'>+		reg = &lt;0x40&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;touchscreen_pins&gt;;</div><div class='add'>+</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 155 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		post-power-on-delay-ms = &lt;70&gt;;</div><div class='add'>+		hid-descr-addr = &lt;0x0001&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	trackpad@2c {</div><div class='add'>+		compatible = "hid-over-i2c";</div><div class='add'>+		reg = &lt;0x2c&gt;;</div><div class='add'>+		hid-descr-addr = &lt;0x20&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;trackpad_pins&gt;;</div><div class='add'>+</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 7 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		wakeup-source;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qca_wifi {</div><div class='add'>+	qcom,ath10k-calibration-variant = "GO_JUNIPER";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi<br/>new file mode 100644<br/>index 000000000000..1b74ec171c10<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi</a></div><div class='hunk'>@@ -0,0 +1,483 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "mt8183-kukui.dtsi"</div><div class='add'>+/* Must come after mt8183-kukui.dtsi to modify cros_ec */</div><div class='add'>+#include &lt;arm/cros-ec-keyboard.dtsi&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	pp1000_mipibrdg: pp1000-mipibrdg {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "pp1000_mipibrdg";</div><div class='add'>+		regulator-min-microvolt = &lt;1000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pp1000_mipibrdg_en&gt;;</div><div class='add'>+</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;pio 54 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;pp1800_alw&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pp1800_mipibrdg: pp1800-mipibrdg {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "pp1800_mipibrdg";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pp1800_mipibrdg_en&gt;;</div><div class='add'>+</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;pio 36 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;pp1800_alw&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pp3300_panel: pp3300-panel {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "pp3300_panel";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pp3300_panel_pins&gt;;</div><div class='add'>+</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;pio 35 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;pp3300_alw&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pp3300_mipibrdg: pp3300-mipibrdg {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "pp3300_mipibrdg";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pp3300_mipibrdg_en&gt;;</div><div class='add'>+</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;pio 37 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;pp3300_alw&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	volume_buttons: volume-buttons {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;volume_button_pins&gt;;</div><div class='add'>+</div><div class='add'>+		button-volume-down {</div><div class='add'>+			label = "Volume Down";</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+			debounce-interval = &lt;100&gt;;</div><div class='add'>+</div><div class='add'>+			gpios = &lt;&amp;pio 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-volume-up {</div><div class='add'>+			label = "Volume Up";</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+			debounce-interval = &lt;100&gt;;</div><div class='add'>+</div><div class='add'>+			gpios = &lt;&amp;pio 5 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cros_ec {</div><div class='add'>+	cros_ec_pwm: pwm {</div><div class='add'>+		compatible = "google,cros-ec-pwm";</div><div class='add'>+		#pwm-cells = &lt;1&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsi_out {</div><div class='add'>+	remote-endpoint = &lt;&amp;anx7625_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	touchscreen: touchscreen@10 {</div><div class='add'>+		compatible = "elan,ekth3500";</div><div class='add'>+		reg = &lt;0x10&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;touchscreen_pins&gt;;</div><div class='add'>+</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 155 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		reset-gpios = &lt;&amp;pio 156 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c2_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+</div><div class='add'>+	trackpad@15 {</div><div class='add'>+		compatible = "elan,ekth3000";</div><div class='add'>+		reg = &lt;0x15&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;trackpad_pins&gt;;</div><div class='add'>+</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 7 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		wakeup-source;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c4_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+</div><div class='add'>+	anx_bridge: anx7625@58 {</div><div class='add'>+		compatible = "analogix,anx7625";</div><div class='add'>+		reg = &lt;0x58&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;anx7625_pins&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;pio 45 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pio 73 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		vdd10-supply = &lt;&amp;pp1000_mipibrdg&gt;;</div><div class='add'>+		vdd18-supply = &lt;&amp;pp1800_mipibrdg&gt;;</div><div class='add'>+		vdd33-supply = &lt;&amp;pp3300_mipibrdg&gt;;</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				anx7625_in: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;dsi_out&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				anx7625_out: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;panel_in&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aux-bus {</div><div class='add'>+			panel: panel {</div><div class='add'>+				compatible = "edp-panel";</div><div class='add'>+				power-supply = &lt;&amp;pp3300_panel&gt;;</div><div class='add'>+				backlight = &lt;&amp;backlight_lcd0&gt;;</div><div class='add'>+</div><div class='add'>+				port {</div><div class='add'>+					panel_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;anx7625_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c_tunnel {</div><div class='add'>+	google,remote-bus = &lt;2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	/* 192 lines */</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"SPI_AP_EC_CS_L",</div><div class='add'>+		"SPI_AP_EC_MOSI",</div><div class='add'>+		"SPI_AP_EC_CLK",</div><div class='add'>+		"I2S3_DO",</div><div class='add'>+		"USB_PD_INT_ODL",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"IT6505_HPD_L",</div><div class='add'>+		"I2S3_TDM_D3",</div><div class='add'>+		"SOC_I2C6_1V8_SCL",</div><div class='add'>+		"SOC_I2C6_1V8_SDA",</div><div class='add'>+		"DPI_D0",</div><div class='add'>+		"DPI_D1",</div><div class='add'>+		"DPI_D2",</div><div class='add'>+		"DPI_D3",</div><div class='add'>+		"DPI_D4",</div><div class='add'>+		"DPI_D5",</div><div class='add'>+		"DPI_D6",</div><div class='add'>+		"DPI_D7",</div><div class='add'>+		"DPI_D8",</div><div class='add'>+		"DPI_D9",</div><div class='add'>+		"DPI_D10",</div><div class='add'>+		"DPI_D11",</div><div class='add'>+		"DPI_HSYNC",</div><div class='add'>+		"DPI_VSYNC",</div><div class='add'>+		"DPI_DE",</div><div class='add'>+		"DPI_CK",</div><div class='add'>+		"AP_MSDC1_CLK",</div><div class='add'>+		"AP_MSDC1_DAT3",</div><div class='add'>+		"AP_MSDC1_CMD",</div><div class='add'>+		"AP_MSDC1_DAT0",</div><div class='add'>+		"AP_MSDC1_DAT2",</div><div class='add'>+		"AP_MSDC1_DAT1",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"OTG_EN",</div><div class='add'>+		"DRVBUS",</div><div class='add'>+		"DISP_PWM",</div><div class='add'>+		"DSI_TE",</div><div class='add'>+		"LCM_RST_1V8",</div><div class='add'>+		"AP_CTS_WIFI_RTS",</div><div class='add'>+		"AP_RTS_WIFI_CTS",</div><div class='add'>+		"SOC_I2C5_1V8_SCL",</div><div class='add'>+		"SOC_I2C5_1V8_SDA",</div><div class='add'>+		"SOC_I2C3_1V8_SCL",</div><div class='add'>+		"SOC_I2C3_1V8_SDA",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"SOC_I2C1_1V8_SDA",</div><div class='add'>+		"SOC_I2C0_1V8_SDA",</div><div class='add'>+		"SOC_I2C0_1V8_SCL",</div><div class='add'>+		"SOC_I2C1_1V8_SCL",</div><div class='add'>+		"AP_SPI_H1_MISO",</div><div class='add'>+		"AP_SPI_H1_CS_L",</div><div class='add'>+		"AP_SPI_H1_MOSI",</div><div class='add'>+		"AP_SPI_H1_CLK",</div><div class='add'>+		"I2S5_BCK",</div><div class='add'>+		"I2S5_LRCK",</div><div class='add'>+		"I2S5_DO",</div><div class='add'>+		"BOOTBLOCK_EN_L",</div><div class='add'>+		"MT8183_KPCOL0",</div><div class='add'>+		"SPI_AP_EC_MISO",</div><div class='add'>+		"UART_DBG_TX_AP_RX",</div><div class='add'>+		"UART_AP_TX_DBG_RX",</div><div class='add'>+		"I2S2_MCK",</div><div class='add'>+		"I2S2_BCK",</div><div class='add'>+		"CLK_5M_WCAM",</div><div class='add'>+		"CLK_2M_UCAM",</div><div class='add'>+		"I2S2_LRCK",</div><div class='add'>+		"I2S2_DI",</div><div class='add'>+		"SOC_I2C2_1V8_SCL",</div><div class='add'>+		"SOC_I2C2_1V8_SDA",</div><div class='add'>+		"SOC_I2C4_1V8_SCL",</div><div class='add'>+		"SOC_I2C4_1V8_SDA",</div><div class='add'>+		"",</div><div class='add'>+		"SCL8",</div><div class='add'>+		"SDA8",</div><div class='add'>+		"FCAM_PWDN_L",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"I2S_PMIC",</div><div class='add'>+		"I2S_PMIC",</div><div class='add'>+		"I2S_PMIC",</div><div class='add'>+		"I2S_PMIC",</div><div class='add'>+		"I2S_PMIC",</div><div class='add'>+		"I2S_PMIC",</div><div class='add'>+		"I2S_PMIC",</div><div class='add'>+		"I2S_PMIC",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		/*</div><div class='add'>+		 * AP_FLASH_WP_L is crossystem ABI. Rev1 schematics</div><div class='add'>+		 * call it BIOS_FLASH_WP_R_L.</div><div class='add'>+		 */</div><div class='add'>+		"AP_FLASH_WP_L",</div><div class='add'>+		"EC_AP_INT_ODL",</div><div class='add'>+		"IT6505_INT_ODL",</div><div class='add'>+		"H1_INT_OD_L",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"AP_SPI_FLASH_MISO",</div><div class='add'>+		"AP_SPI_FLASH_CS_L",</div><div class='add'>+		"AP_SPI_FLASH_MOSI",</div><div class='add'>+		"AP_SPI_FLASH_CLK",</div><div class='add'>+		"DA7219_IRQ",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"";</div><div class='add'>+</div><div class='add'>+	pp1000_mipibrdg_en: pp1000-mipibrdg-en-pins {</div><div class='add'>+		pins1 {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO54__FUNC_GPIO54&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pp1800_mipibrdg_en: pp1800-mipibrdg-en-pins {</div><div class='add'>+		pins1 {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO36__FUNC_GPIO36&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pp3300_panel_pins: pp3300-panel-pins {</div><div class='add'>+		panel_3v3_enable: pins-panel-en {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO35__FUNC_GPIO35&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ppvarp_lcd_en: ppvarp-lcd-en-pins {</div><div class='add'>+		pins1 {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO66__FUNC_GPIO66&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ppvarn_lcd_en: ppvarn-lcd-en-pins {</div><div class='add'>+		pins1 {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO166__FUNC_GPIO166&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	anx7625_pins: anx7625-pins {</div><div class='add'>+		pins1 {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO45__FUNC_GPIO45&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO73__FUNC_GPIO73&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+		pins2 {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO4__FUNC_GPIO4&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	touchscreen_pins: touchscreen-pins {</div><div class='add'>+		pins-intn {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO155__FUNC_GPIO155&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-rst {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO156__FUNC_GPIO156&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	trackpad_pins: trackpad-pins {</div><div class='add'>+		pins-intn {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO7__FUNC_GPIO7&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-disable; /* pulled externally */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pp3300_mipibrdg_en: pp3300-mipibrdg-en-pins {</div><div class='add'>+		pins1 {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO37__FUNC_GPIO37&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	volume_button_pins: volume-button-pins {</div><div class='add'>+		pins-voldn {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO6__FUNC_GPIO6&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-volup {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO5__FUNC_GPIO5&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts<br/>new file mode 100644<br/>index 000000000000..1ecf39458d93<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts</a></div><div class='hunk'>@@ -0,0 +1,38 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8183-kukui-kakadu.dtsi"</div><div class='add'>+#include "mt8183-kukui-audio-rt1015p.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "MediaTek kakadu board sku22";</div><div class='add'>+	chassis-type = "tablet";</div><div class='add'>+	compatible = "google,kakadu-rev3-sku22", "google,kakadu-rev2-sku22",</div><div class='add'>+		     "google,kakadu", "mediatek,mt8183";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	touchscreen: touchscreen@10 {</div><div class='add'>+		compatible = "hid-over-i2c";</div><div class='add'>+		reg = &lt;0x10&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;open_touch&gt;;</div><div class='add'>+</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 155 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+</div><div class='add'>+		post-power-on-delay-ms = &lt;10&gt;;</div><div class='add'>+		hid-descr-addr = &lt;0x0001&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;panel {</div><div class='add'>+	compatible = "boe,tv105wum-nw0";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sound {</div><div class='add'>+	compatible = "mediatek,mt8183_mt6358_ts3a227_rt1015p";</div><div class='add'>+};</div><div class='add'>+</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts<br/>new file mode 100644<br/>index 000000000000..ba74109a4909<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts</a></div><div class='hunk'>@@ -0,0 +1,33 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2020 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8183-kukui-kakadu.dtsi"</div><div class='add'>+#include "mt8183-kukui-audio-da7219-rt1015p.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "MediaTek kakadu board";</div><div class='add'>+	chassis-type = "tablet";</div><div class='add'>+	compatible = "google,kakadu-rev3", "google,kakadu-rev2",</div><div class='add'>+			"google,kakadu", "mediatek,mt8183";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	touchscreen: touchscreen@10 {</div><div class='add'>+		compatible = "hid-over-i2c";</div><div class='add'>+		reg = &lt;0x10&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;open_touch&gt;;</div><div class='add'>+</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 155 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+</div><div class='add'>+		post-power-on-delay-ms = &lt;10&gt;;</div><div class='add'>+		hid-descr-addr = &lt;0x0001&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;panel {</div><div class='add'>+	compatible = "boe,tv105wum-nw0";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi<br/>new file mode 100644<br/>index 000000000000..d71972c94e42<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi</a></div><div class='hunk'>@@ -0,0 +1,406 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2020 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "mt8183-kukui.dtsi"</div><div class='add'>+#include &lt;dt-bindings/input/gpio-keys.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	ppvarn_lcd: ppvarn-lcd {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "ppvarn_lcd";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;ppvarn_lcd_en&gt;;</div><div class='add'>+</div><div class='add'>+		enable-active-high;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;pio 66 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ppvarp_lcd: ppvarp-lcd {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "ppvarp_lcd";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;ppvarp_lcd_en&gt;;</div><div class='add'>+</div><div class='add'>+		enable-active-high;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;pio 166 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pp1800_lcd: pp1800-lcd {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "pp1800_lcd";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pp1800_lcd_en&gt;;</div><div class='add'>+</div><div class='add'>+		enable-active-high;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;pio 36 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pen_eject&gt;;</div><div class='add'>+</div><div class='add'>+		switch-pen-insert {</div><div class='add'>+			label = "Pen Insert";</div><div class='add'>+			/* Insert = low, eject = high */</div><div class='add'>+			gpios = &lt;&amp;pio 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;SW_PEN_INSERTED&gt;;</div><div class='add'>+			linux,input-type = &lt;EV_SW&gt;;</div><div class='add'>+			wakeup-event-action = &lt;EV_ACT_DEASSERTED&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;bluetooth {</div><div class='add'>+	firmware-name = "nvm_00440302_i2s_eu.bin";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsi0 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	panel: panel@0 {</div><div class='add'>+		/* compatible will be set in board dts */</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;pio 45 0&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;panel_pins_default&gt;;</div><div class='add'>+		avdd-supply = &lt;&amp;ppvarn_lcd&gt;;</div><div class='add'>+		avee-supply = &lt;&amp;ppvarp_lcd&gt;;</div><div class='add'>+		pp1800-supply = &lt;&amp;pp1800_lcd&gt;;</div><div class='add'>+		backlight = &lt;&amp;backlight_lcd0&gt;;</div><div class='add'>+		rotation = &lt;270&gt;;</div><div class='add'>+		port {</div><div class='add'>+			panel_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;dsi_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsi_out {</div><div class='add'>+	remote-endpoint = &lt;&amp;panel_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6358_vcama2_reg {</div><div class='add'>+	regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c2_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	vbus-supply = &lt;&amp;mt6358_vcamio_reg&gt;;</div><div class='add'>+</div><div class='add'>+	eeprom@58 {</div><div class='add'>+		compatible = "atmel,24c32";</div><div class='add'>+		reg = &lt;0x58&gt;;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;mt6358_vcama2_reg&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c4_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	vbus-supply = &lt;&amp;mt6358_vcn18_reg&gt;;</div><div class='add'>+</div><div class='add'>+	eeprom@50 {</div><div class='add'>+		compatible = "atmel,24c32";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;mt6358_vcn18_reg&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_tx0 {</div><div class='add'>+	drive-strength-microamp = &lt;5800&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	/* 192 lines */</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"SPI_AP_EC_CS_L",</div><div class='add'>+		"SPI_AP_EC_MOSI",</div><div class='add'>+		"SPI_AP_EC_CLK",</div><div class='add'>+		"I2S3_DO",</div><div class='add'>+		"USB_PD_INT_ODL",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"IT6505_HPD_L",</div><div class='add'>+		"I2S3_TDM_D3",</div><div class='add'>+		"SOC_I2C6_1V8_SCL",</div><div class='add'>+		"SOC_I2C6_1V8_SDA",</div><div class='add'>+		"DPI_D0",</div><div class='add'>+		"DPI_D1",</div><div class='add'>+		"DPI_D2",</div><div class='add'>+		"DPI_D3",</div><div class='add'>+		"DPI_D4",</div><div class='add'>+		"DPI_D5",</div><div class='add'>+		"DPI_D6",</div><div class='add'>+		"DPI_D7",</div><div class='add'>+		"DPI_D8",</div><div class='add'>+		"DPI_D9",</div><div class='add'>+		"DPI_D10",</div><div class='add'>+		"DPI_D11",</div><div class='add'>+		"DPI_HSYNC",</div><div class='add'>+		"DPI_VSYNC",</div><div class='add'>+		"DPI_DE",</div><div class='add'>+		"DPI_CK",</div><div class='add'>+		"AP_MSDC1_CLK",</div><div class='add'>+		"AP_MSDC1_DAT3",</div><div class='add'>+		"AP_MSDC1_CMD",</div><div class='add'>+		"AP_MSDC1_DAT0",</div><div class='add'>+		"AP_MSDC1_DAT2",</div><div class='add'>+		"AP_MSDC1_DAT1",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"OTG_EN",</div><div class='add'>+		"DRVBUS",</div><div class='add'>+		"DISP_PWM",</div><div class='add'>+		"DSI_TE",</div><div class='add'>+		"LCM_RST_1V8",</div><div class='add'>+		"AP_CTS_WIFI_RTS",</div><div class='add'>+		"AP_RTS_WIFI_CTS",</div><div class='add'>+		"SOC_I2C5_1V8_SCL",</div><div class='add'>+		"SOC_I2C5_1V8_SDA",</div><div class='add'>+		"SOC_I2C3_1V8_SCL",</div><div class='add'>+		"SOC_I2C3_1V8_SDA",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"SOC_I2C1_1V8_SDA",</div><div class='add'>+		"SOC_I2C0_1V8_SDA",</div><div class='add'>+		"SOC_I2C0_1V8_SCL",</div><div class='add'>+		"SOC_I2C1_1V8_SCL",</div><div class='add'>+		"AP_SPI_H1_MISO",</div><div class='add'>+		"AP_SPI_H1_CS_L",</div><div class='add'>+		"AP_SPI_H1_MOSI",</div><div class='add'>+		"AP_SPI_H1_CLK",</div><div class='add'>+		"I2S5_BCK",</div><div class='add'>+		"I2S5_LRCK",</div><div class='add'>+		"I2S5_DO",</div><div class='add'>+		"BOOTBLOCK_EN_L",</div><div class='add'>+		"MT8183_KPCOL0",</div><div class='add'>+		"SPI_AP_EC_MISO",</div><div class='add'>+		"UART_DBG_TX_AP_RX",</div><div class='add'>+		"UART_AP_TX_DBG_RX",</div><div class='add'>+		"I2S2_MCK",</div><div class='add'>+		"I2S2_BCK",</div><div class='add'>+		"CLK_5M_WCAM",</div><div class='add'>+		"CLK_2M_UCAM",</div><div class='add'>+		"I2S2_LRCK",</div><div class='add'>+		"I2S2_DI",</div><div class='add'>+		"SOC_I2C2_1V8_SCL",</div><div class='add'>+		"SOC_I2C2_1V8_SDA",</div><div class='add'>+		"SOC_I2C4_1V8_SCL",</div><div class='add'>+		"SOC_I2C4_1V8_SDA",</div><div class='add'>+		"",</div><div class='add'>+		"SCL8",</div><div class='add'>+		"SDA8",</div><div class='add'>+		"FCAM_PWDN_L",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"I2S_PMIC",</div><div class='add'>+		"I2S_PMIC",</div><div class='add'>+		"I2S_PMIC",</div><div class='add'>+		"I2S_PMIC",</div><div class='add'>+		"I2S_PMIC",</div><div class='add'>+		"I2S_PMIC",</div><div class='add'>+		"I2S_PMIC",</div><div class='add'>+		"I2S_PMIC",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		/*</div><div class='add'>+		 * AP_FLASH_WP_L is crossystem ABI. Rev1 schematics</div><div class='add'>+		 * call it BIOS_FLASH_WP_R_L.</div><div class='add'>+		 */</div><div class='add'>+		"AP_FLASH_WP_L",</div><div class='add'>+		"EC_AP_INT_ODL",</div><div class='add'>+		"IT6505_INT_ODL",</div><div class='add'>+		"H1_INT_OD_L",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"AP_SPI_FLASH_MISO",</div><div class='add'>+		"AP_SPI_FLASH_CS_L",</div><div class='add'>+		"AP_SPI_FLASH_MOSI",</div><div class='add'>+		"AP_SPI_FLASH_CLK",</div><div class='add'>+		"DA7219_IRQ",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"";</div><div class='add'>+</div><div class='add'>+	ppvarp_lcd_en: ppvarp-lcd-en-pins {</div><div class='add'>+		pins1 {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO66__FUNC_GPIO66&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ppvarn_lcd_en: ppvarn-lcd-en-pins {</div><div class='add'>+		pins1 {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO166__FUNC_GPIO166&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pp1800_lcd_en: pp1800-lcd-en-pins {</div><div class='add'>+		pins1 {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO36__FUNC_GPIO36&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	open_touch: opentouch-pins {</div><div class='add'>+		pins-intn {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO155__FUNC_GPIO155&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-rst {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO156__FUNC_GPIO156&gt;;</div><div class='add'>+</div><div class='add'>+			/*</div><div class='add'>+			 * The pen driver doesn't currently support  driving</div><div class='add'>+			 * this reset line.  By specifying output-high here</div><div class='add'>+			 * we're relying on the fact that this pin has a default</div><div class='add'>+			 * pulldown at boot (which makes sure the pen was in</div><div class='add'>+			 * reset if it was powered) and then we set it high here</div><div class='add'>+			 * to take it out of reset.  Better would be if the pen</div><div class='add'>+			 * driver could control this and we could remove</div><div class='add'>+			 * "output-high" here.</div><div class='add'>+			 */</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pen_eject: pen-pins {</div><div class='add'>+		pins-eject {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO6__FUNC_GPIO6&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			/* External pull-up. */</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cros_ec {</div><div class='add'>+	cbas {</div><div class='add'>+		compatible = "google,cros-cbas";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	keyboard-controller {</div><div class='add'>+		compatible = "google,cros-ec-keyb-switches";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qca_wifi {</div><div class='add'>+	qcom,ath10k-calibration-variant = "GO_KAKADU";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;panel {</div><div class='add'>+	status = "okay";</div><div class='add'>+	/* compatible will be set in board dts */</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-katsu-sku32.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-katsu-sku32.dts<br/>new file mode 100644<br/>index 000000000000..2b5a8d1f900e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183-kukui-katsu-sku32.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8183-kukui-katsu-sku32.dts</a></div><div class='hunk'>@@ -0,0 +1,36 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8183-kukui-kakadu.dtsi"</div><div class='add'>+#include "mt8183-kukui-audio-da7219-rt1015p.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google katsu board";</div><div class='add'>+	chassis-type = "tablet";</div><div class='add'>+	compatible = "google,katsu-sku32", "google,katsu", "mediatek,mt8183";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	touchscreen1: touchscreen@5d {</div><div class='add'>+		compatible = "goodix,gt7375p";</div><div class='add'>+		reg = &lt;0x5d&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;open_touch&gt;;</div><div class='add'>+</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 155 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		reset-gpios = &lt;&amp;pio 156 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;pp3300_alw&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;panel {</div><div class='add'>+	compatible = "starry,2081101qfh032011-53g";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qca_wifi {</div><div class='add'>+	qcom,ath10k-calibration-variant = "GO_KATSU";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-katsu-sku38.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-katsu-sku38.dts<br/>new file mode 100644<br/>index 000000000000..75fadf2c7059<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183-kukui-katsu-sku38.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8183-kukui-katsu-sku38.dts</a></div><div class='hunk'>@@ -0,0 +1,40 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8183-kukui-kakadu.dtsi"</div><div class='add'>+#include "mt8183-kukui-audio-rt1015p.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google katsu sku38 board";</div><div class='add'>+	chassis-type = "tablet";</div><div class='add'>+	compatible = "google,katsu-sku38", "google,katsu", "mediatek,mt8183";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	touchscreen1: touchscreen@5d {</div><div class='add'>+		compatible = "goodix,gt7375p";</div><div class='add'>+		reg = &lt;0x5d&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;open_touch&gt;;</div><div class='add'>+</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 155 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		reset-gpios = &lt;&amp;pio 156 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;pp3300_alw&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;panel {</div><div class='add'>+	compatible = "starry,2081101qfh032011-53g";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qca_wifi {</div><div class='add'>+	qcom,ath10k-calibration-variant = "GO_KATSU";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sound {</div><div class='add'>+	compatible = "mediatek,mt8183_mt6358_ts3a227_rt1015p";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts<br/>new file mode 100644<br/>index 000000000000..7213cdcca612<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts</a></div><div class='hunk'>@@ -0,0 +1,22 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021 Google LLC</div><div class='add'>+ *</div><div class='add'>+ * SKU: 0x10 =&gt; 16</div><div class='add'>+ *  - bit 8: Camera: 0 (OV5695)</div><div class='add'>+ *  - bits 7..4: Panel ID: 0x1 (AUO)</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8183-kukui-kodama.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "MediaTek kodama sku16 board";</div><div class='add'>+	chassis-type = "tablet";</div><div class='add'>+	compatible = "google,kodama-sku16", "google,kodama", "mediatek,mt8183";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;panel {</div><div class='add'>+	status = "okay";</div><div class='add'>+	compatible = "auo,b101uan08.3";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts<br/>new file mode 100644<br/>index 000000000000..bbf0cd1aa66d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts</a></div><div class='hunk'>@@ -0,0 +1,22 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2020 Google LLC</div><div class='add'>+ *</div><div class='add'>+ * SKU: 0x110 =&gt; 272</div><div class='add'>+ *  - bit 8: Camera: 1 (GC5035)</div><div class='add'>+ *  - bits 7..4: Panel ID: 0x1 (AUO)</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8183-kukui-kodama.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "MediaTek kodama sku272 board";</div><div class='add'>+	chassis-type = "tablet";</div><div class='add'>+	compatible = "google,kodama-sku272", "google,kodama", "mediatek,mt8183";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;panel {</div><div class='add'>+	status = "okay";</div><div class='add'>+	compatible = "auo,b101uan08.3";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts<br/>new file mode 100644<br/>index 000000000000..a429ffeac3bd<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts</a></div><div class='hunk'>@@ -0,0 +1,22 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2020 Google LLC</div><div class='add'>+ *</div><div class='add'>+ * SKU: 0x120 =&gt; 288</div><div class='add'>+ *  - bit 8: Camera: 1 (GC5035)</div><div class='add'>+ *  - bits 7..4: Panel ID: 0x2 (BOE)</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8183-kukui-kodama.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "MediaTek kodama sku288 board";</div><div class='add'>+	chassis-type = "tablet";</div><div class='add'>+	compatible = "google,kodama-sku288", "google,kodama", "mediatek,mt8183";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;panel {</div><div class='add'>+	status = "okay";</div><div class='add'>+	compatible = "boe,tv101wum-n53";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku32.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku32.dts<br/>new file mode 100644<br/>index 000000000000..5a416143b4a0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku32.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku32.dts</a></div><div class='hunk'>@@ -0,0 +1,22 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021 Google LLC</div><div class='add'>+ *</div><div class='add'>+ * SKU: 0x20 =&gt; 32</div><div class='add'>+ *  - bit 8: Camera: 0 (OV5695)</div><div class='add'>+ *  - bits 7..4: Panel ID: 0x2 (BOE)</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8183-kukui-kodama.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "MediaTek kodama sku32 board";</div><div class='add'>+	chassis-type = "tablet";</div><div class='add'>+	compatible = "google,kodama-sku32", "google,kodama", "mediatek,mt8183";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;panel {</div><div class='add'>+	status = "okay";</div><div class='add'>+	compatible = "boe,tv101wum-n53";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi<br/>new file mode 100644<br/>index 000000000000..b702ff066636<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi</a></div><div class='hunk'>@@ -0,0 +1,385 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8183-kukui.dtsi"</div><div class='add'>+#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	ppvarn_lcd: ppvarn-lcd {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "ppvarn_lcd";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;ppvarn_lcd_en&gt;;</div><div class='add'>+</div><div class='add'>+		enable-active-high;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;pio 66 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ppvarp_lcd: ppvarp-lcd {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "ppvarp_lcd";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;ppvarp_lcd_en&gt;;</div><div class='add'>+</div><div class='add'>+		enable-active-high;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;pio 166 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pp1800_lcd: pp1800-lcd {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "pp1800_lcd";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pp1800_lcd_en&gt;;</div><div class='add'>+</div><div class='add'>+		enable-active-high;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;pio 36 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsi0 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	panel: panel@0 {</div><div class='add'>+		/* compatible will be set in board dts */</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;pio 45 0&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;panel_pins_default&gt;;</div><div class='add'>+		avdd-supply = &lt;&amp;ppvarn_lcd&gt;;</div><div class='add'>+		avee-supply = &lt;&amp;ppvarp_lcd&gt;;</div><div class='add'>+		pp1800-supply = &lt;&amp;pp1800_lcd&gt;;</div><div class='add'>+		backlight = &lt;&amp;backlight_lcd0&gt;;</div><div class='add'>+		rotation = &lt;270&gt;;</div><div class='add'>+		port {</div><div class='add'>+			panel_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;dsi_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsi_out {</div><div class='add'>+	remote-endpoint = &lt;&amp;panel_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	touchscreen: touchscreen@10 {</div><div class='add'>+		compatible = "hid-over-i2c";</div><div class='add'>+		reg = &lt;0x10&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 155 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;touch_default&gt;;</div><div class='add'>+</div><div class='add'>+		post-power-on-delay-ms = &lt;10&gt;;</div><div class='add'>+		hid-descr-addr = &lt;0x0001&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+        pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c2_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	vbus-supply = &lt;&amp;mt6358_vcamio_reg&gt;;</div><div class='add'>+</div><div class='add'>+	eeprom@58 {</div><div class='add'>+		compatible = "atmel,24c64";</div><div class='add'>+		reg = &lt;0x58&gt;;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;mt6358_vcamio_reg&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+        pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c4_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	vbus-supply = &lt;&amp;mt6358_vcn18_reg&gt;;</div><div class='add'>+</div><div class='add'>+	eeprom@50 {</div><div class='add'>+		compatible = "atmel,24c64";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;mt6358_vcn18_reg&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6358_vcama2_reg {</div><div class='add'>+	regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	/* 192 lines */</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"SPI_AP_EC_CS_L",</div><div class='add'>+		"SPI_AP_EC_MOSI",</div><div class='add'>+		"SPI_AP_EC_CLK",</div><div class='add'>+		"I2S3_DO",</div><div class='add'>+		"USB_PD_INT_ODL",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"IT6505_HPD_L",</div><div class='add'>+		"I2S3_TDM_D3",</div><div class='add'>+		"SOC_I2C6_1V8_SCL",</div><div class='add'>+		"SOC_I2C6_1V8_SDA",</div><div class='add'>+		"DPI_D0",</div><div class='add'>+		"DPI_D1",</div><div class='add'>+		"DPI_D2",</div><div class='add'>+		"DPI_D3",</div><div class='add'>+		"DPI_D4",</div><div class='add'>+		"DPI_D5",</div><div class='add'>+		"DPI_D6",</div><div class='add'>+		"DPI_D7",</div><div class='add'>+		"DPI_D8",</div><div class='add'>+		"DPI_D9",</div><div class='add'>+		"DPI_D10",</div><div class='add'>+		"DPI_D11",</div><div class='add'>+		"DPI_HSYNC",</div><div class='add'>+		"DPI_VSYNC",</div><div class='add'>+		"DPI_DE",</div><div class='add'>+		"DPI_CK",</div><div class='add'>+		"AP_MSDC1_CLK",</div><div class='add'>+		"AP_MSDC1_DAT3",</div><div class='add'>+		"AP_MSDC1_CMD",</div><div class='add'>+		"AP_MSDC1_DAT0",</div><div class='add'>+		"AP_MSDC1_DAT2",</div><div class='add'>+		"AP_MSDC1_DAT1",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"OTG_EN",</div><div class='add'>+		"DRVBUS",</div><div class='add'>+		"DISP_PWM",</div><div class='add'>+		"DSI_TE",</div><div class='add'>+		"LCM_RST_1V8",</div><div class='add'>+		"AP_CTS_WIFI_RTS",</div><div class='add'>+		"AP_RTS_WIFI_CTS",</div><div class='add'>+		"SOC_I2C5_1V8_SCL",</div><div class='add'>+		"SOC_I2C5_1V8_SDA",</div><div class='add'>+		"SOC_I2C3_1V8_SCL",</div><div class='add'>+		"SOC_I2C3_1V8_SDA",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"SOC_I2C1_1V8_SDA",</div><div class='add'>+		"SOC_I2C0_1V8_SDA",</div><div class='add'>+		"SOC_I2C0_1V8_SCL",</div><div class='add'>+		"SOC_I2C1_1V8_SCL",</div><div class='add'>+		"AP_SPI_H1_MISO",</div><div class='add'>+		"AP_SPI_H1_CS_L",</div><div class='add'>+		"AP_SPI_H1_MOSI",</div><div class='add'>+		"AP_SPI_H1_CLK",</div><div class='add'>+		"I2S5_BCK",</div><div class='add'>+		"I2S5_LRCK",</div><div class='add'>+		"I2S5_DO",</div><div class='add'>+		"BOOTBLOCK_EN_L",</div><div class='add'>+		"MT8183_KPCOL0",</div><div class='add'>+		"SPI_AP_EC_MISO",</div><div class='add'>+		"UART_DBG_TX_AP_RX",</div><div class='add'>+		"UART_AP_TX_DBG_RX",</div><div class='add'>+		"I2S2_MCK",</div><div class='add'>+		"I2S2_BCK",</div><div class='add'>+		"CLK_5M_WCAM",</div><div class='add'>+		"CLK_2M_UCAM",</div><div class='add'>+		"I2S2_LRCK",</div><div class='add'>+		"I2S2_DI",</div><div class='add'>+		"SOC_I2C2_1V8_SCL",</div><div class='add'>+		"SOC_I2C2_1V8_SDA",</div><div class='add'>+		"SOC_I2C4_1V8_SCL",</div><div class='add'>+		"SOC_I2C4_1V8_SDA",</div><div class='add'>+		"",</div><div class='add'>+		"SCL8",</div><div class='add'>+		"SDA8",</div><div class='add'>+		"FCAM_PWDN_L",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"I2S_PMIC",</div><div class='add'>+		"I2S_PMIC",</div><div class='add'>+		"I2S_PMIC",</div><div class='add'>+		"I2S_PMIC",</div><div class='add'>+		"I2S_PMIC",</div><div class='add'>+		"I2S_PMIC",</div><div class='add'>+		"I2S_PMIC",</div><div class='add'>+		"I2S_PMIC",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		/*</div><div class='add'>+		 * AP_FLASH_WP_L is crossystem ABI. Rev1 schematics</div><div class='add'>+		 * call it BIOS_FLASH_WP_R_L.</div><div class='add'>+		 */</div><div class='add'>+		"AP_FLASH_WP_L",</div><div class='add'>+		"EC_AP_INT_ODL",</div><div class='add'>+		"IT6505_INT_ODL",</div><div class='add'>+		"H1_INT_OD_L",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"AP_SPI_FLASH_MISO",</div><div class='add'>+		"AP_SPI_FLASH_CS_L",</div><div class='add'>+		"AP_SPI_FLASH_MOSI",</div><div class='add'>+		"AP_SPI_FLASH_CLK",</div><div class='add'>+		"DA7219_IRQ",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"";</div><div class='add'>+</div><div class='add'>+	ppvarp_lcd_en: ppvarp-lcd-en-pins {</div><div class='add'>+		pins1 {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO66__FUNC_GPIO66&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ppvarn_lcd_en: ppvarn-lcd-en-pins {</div><div class='add'>+		pins1 {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO166__FUNC_GPIO166&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pp1800_lcd_en: pp1800-lcd-en-pins {</div><div class='add'>+		pins1 {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO36__FUNC_GPIO36&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	touch_default: touch-pins {</div><div class='add'>+		pins-intn {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO155__FUNC_GPIO155&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		touch_pin_reset: pins-rst {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO156__FUNC_GPIO156&gt;;</div><div class='add'>+</div><div class='add'>+			/*</div><div class='add'>+			 * The touchscreen driver doesn't currently support driving</div><div class='add'>+			 * this reset line.  By specifying output-high here</div><div class='add'>+			 * we're relying on the fact that this pin has a default</div><div class='add'>+			 * pulldown at boot (which makes sure the controller was in</div><div class='add'>+			 * reset if it was powered) and then we set it high here</div><div class='add'>+			 * to take it out of reset.  Better would be if the touchscreen</div><div class='add'>+			 * driver could control this and we could remove</div><div class='add'>+			 * "output-high" here.</div><div class='add'>+			 */</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cros_ec {</div><div class='add'>+	cbas {</div><div class='add'>+		compatible = "google,cros-cbas";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	keyboard-controller {</div><div class='add'>+		compatible = "google,cros-ec-keyb-switches";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qca_wifi {</div><div class='add'>+	qcom,ath10k-calibration-variant = "GO_KODAMA";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c_tunnel {</div><div class='add'>+        google,remote-bus = &lt;2&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts<br/>new file mode 100644<br/>index 000000000000..4ac75806fa94<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts</a></div><div class='hunk'>@@ -0,0 +1,24 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2019 Google LLC</div><div class='add'>+ *</div><div class='add'>+ * Device-tree for Krane sku0.</div><div class='add'>+ *</div><div class='add'>+ * SKU is a 8-bit value (0x00 == 0):</div><div class='add'>+ *  - Bits 7..4: Panel ID: 0x0 (AUO)</div><div class='add'>+ *  - Bits 3..0: SKU ID:   0x0 (default)</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8183-kukui-krane.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "MediaTek krane sku0 board";</div><div class='add'>+	chassis-type = "tablet";</div><div class='add'>+	compatible = "google,krane-sku0", "google,krane", "mediatek,mt8183";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;panel {</div><div class='add'>+	status = "okay";</div><div class='add'>+	compatible = "auo,kd101n80-45na";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts<br/>new file mode 100644<br/>index 000000000000..095279e55d50<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts</a></div><div class='hunk'>@@ -0,0 +1,24 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2019 Google LLC</div><div class='add'>+ *</div><div class='add'>+ * Device-tree for Krane sku176.</div><div class='add'>+ *</div><div class='add'>+ * SKU is a 8-bit value (0xb0 == 176):</div><div class='add'>+ *  - Bits 7..4: Panel ID: 0xb (BOE)</div><div class='add'>+ *  - Bits 3..0: SKU ID:   0x0 (default)</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8183-kukui-krane.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "MediaTek krane sku176 board";</div><div class='add'>+	chassis-type = "tablet";</div><div class='add'>+	compatible = "google,krane-sku176", "google,krane", "mediatek,mt8183";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;panel {</div><div class='add'>+        status = "okay";</div><div class='add'>+        compatible = "boe,tv101wum-nl6";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi<br/>new file mode 100644<br/>index 000000000000..b6cfcafd8b06<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi</a></div><div class='hunk'>@@ -0,0 +1,389 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2019 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "mt8183-kukui.dtsi"</div><div class='add'>+#include "mt8183-kukui-audio-max98357a.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	ppvarn_lcd: ppvarn-lcd {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "ppvarn_lcd";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;ppvarn_lcd_en&gt;;</div><div class='add'>+</div><div class='add'>+		enable-active-high;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;pio 66 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ppvarp_lcd: ppvarp-lcd {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "ppvarp_lcd";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;ppvarp_lcd_en&gt;;</div><div class='add'>+</div><div class='add'>+		enable-active-high;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;pio 166 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pp1800_lcd: pp1800-lcd {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "pp1800_lcd";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pp1800_lcd_en&gt;;</div><div class='add'>+</div><div class='add'>+		enable-active-high;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;pio 36 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;bluetooth {</div><div class='add'>+	firmware-name = "nvm_00440302_i2s_eu.bin";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsi0 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	panel: panel@0 {</div><div class='add'>+		/* compatible will be set in board dts */</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;pio 45 0&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;panel_pins_default&gt;;</div><div class='add'>+		avdd-supply = &lt;&amp;ppvarn_lcd&gt;;</div><div class='add'>+		avee-supply = &lt;&amp;ppvarp_lcd&gt;;</div><div class='add'>+		pp1800-supply = &lt;&amp;pp1800_lcd&gt;;</div><div class='add'>+		backlight = &lt;&amp;backlight_lcd0&gt;;</div><div class='add'>+		rotation = &lt;270&gt;;</div><div class='add'>+		port {</div><div class='add'>+			panel_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;dsi_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsi_out {</div><div class='add'>+	remote-endpoint = &lt;&amp;panel_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	touchscreen4: touchscreen@5d {</div><div class='add'>+		compatible = "hid-over-i2c";</div><div class='add'>+		reg = &lt;0x5d&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;open_touch&gt;;</div><div class='add'>+</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 155 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+</div><div class='add'>+		post-power-on-delay-ms = &lt;10&gt;;</div><div class='add'>+		hid-descr-addr = &lt;0x0001&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6358_vcama2_reg {</div><div class='add'>+	regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c2_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	vbus-supply = &lt;&amp;mt6358_vcamio_reg&gt;;</div><div class='add'>+</div><div class='add'>+	eeprom@58 {</div><div class='add'>+		compatible = "atmel,24c32";</div><div class='add'>+		reg = &lt;0x58&gt;;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;mt6358_vcama2_reg&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c4_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	vbus-supply = &lt;&amp;mt6358_vcn18_reg&gt;;</div><div class='add'>+</div><div class='add'>+	eeprom@50 {</div><div class='add'>+		compatible = "atmel,24c32";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		pagesize = &lt;32&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;mt6358_vcn18_reg&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	/* 192 lines */</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"SPI_AP_EC_CS_L",</div><div class='add'>+		"SPI_AP_EC_MOSI",</div><div class='add'>+		"SPI_AP_EC_CLK",</div><div class='add'>+		"I2S3_DO",</div><div class='add'>+		"USB_PD_INT_ODL",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"IT6505_HPD_L",</div><div class='add'>+		"I2S3_TDM_D3",</div><div class='add'>+		"SOC_I2C6_1V8_SCL",</div><div class='add'>+		"SOC_I2C6_1V8_SDA",</div><div class='add'>+		"DPI_D0",</div><div class='add'>+		"DPI_D1",</div><div class='add'>+		"DPI_D2",</div><div class='add'>+		"DPI_D3",</div><div class='add'>+		"DPI_D4",</div><div class='add'>+		"DPI_D5",</div><div class='add'>+		"DPI_D6",</div><div class='add'>+		"DPI_D7",</div><div class='add'>+		"DPI_D8",</div><div class='add'>+		"DPI_D9",</div><div class='add'>+		"DPI_D10",</div><div class='add'>+		"DPI_D11",</div><div class='add'>+		"DPI_HSYNC",</div><div class='add'>+		"DPI_VSYNC",</div><div class='add'>+		"DPI_DE",</div><div class='add'>+		"DPI_CK",</div><div class='add'>+		"AP_MSDC1_CLK",</div><div class='add'>+		"AP_MSDC1_DAT3",</div><div class='add'>+		"AP_MSDC1_CMD",</div><div class='add'>+		"AP_MSDC1_DAT0",</div><div class='add'>+		"AP_MSDC1_DAT2",</div><div class='add'>+		"AP_MSDC1_DAT1",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"OTG_EN",</div><div class='add'>+		"DRVBUS",</div><div class='add'>+		"DISP_PWM",</div><div class='add'>+		"DSI_TE",</div><div class='add'>+		"LCM_RST_1V8",</div><div class='add'>+		"AP_CTS_WIFI_RTS",</div><div class='add'>+		"AP_RTS_WIFI_CTS",</div><div class='add'>+		"SOC_I2C5_1V8_SCL",</div><div class='add'>+		"SOC_I2C5_1V8_SDA",</div><div class='add'>+		"SOC_I2C3_1V8_SCL",</div><div class='add'>+		"SOC_I2C3_1V8_SDA",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"SOC_I2C1_1V8_SDA",</div><div class='add'>+		"SOC_I2C0_1V8_SDA",</div><div class='add'>+		"SOC_I2C0_1V8_SCL",</div><div class='add'>+		"SOC_I2C1_1V8_SCL",</div><div class='add'>+		"AP_SPI_H1_MISO",</div><div class='add'>+		"AP_SPI_H1_CS_L",</div><div class='add'>+		"AP_SPI_H1_MOSI",</div><div class='add'>+		"AP_SPI_H1_CLK",</div><div class='add'>+		"I2S5_BCK",</div><div class='add'>+		"I2S5_LRCK",</div><div class='add'>+		"I2S5_DO",</div><div class='add'>+		"BOOTBLOCK_EN_L",</div><div class='add'>+		"MT8183_KPCOL0",</div><div class='add'>+		"SPI_AP_EC_MISO",</div><div class='add'>+		"UART_DBG_TX_AP_RX",</div><div class='add'>+		"UART_AP_TX_DBG_RX",</div><div class='add'>+		"I2S2_MCK",</div><div class='add'>+		"I2S2_BCK",</div><div class='add'>+		"CLK_5M_WCAM",</div><div class='add'>+		"CLK_2M_UCAM",</div><div class='add'>+		"I2S2_LRCK",</div><div class='add'>+		"I2S2_DI",</div><div class='add'>+		"SOC_I2C2_1V8_SCL",</div><div class='add'>+		"SOC_I2C2_1V8_SDA",</div><div class='add'>+		"SOC_I2C4_1V8_SCL",</div><div class='add'>+		"SOC_I2C4_1V8_SDA",</div><div class='add'>+		"",</div><div class='add'>+		"SCL8",</div><div class='add'>+		"SDA8",</div><div class='add'>+		"FCAM_PWDN_L",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"I2S_PMIC",</div><div class='add'>+		"I2S_PMIC",</div><div class='add'>+		"I2S_PMIC",</div><div class='add'>+		"I2S_PMIC",</div><div class='add'>+		"I2S_PMIC",</div><div class='add'>+		"I2S_PMIC",</div><div class='add'>+		"I2S_PMIC",</div><div class='add'>+		"I2S_PMIC",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		/*</div><div class='add'>+		 * AP_FLASH_WP_L is crossystem ABI. Rev1 schematics</div><div class='add'>+		 * call it BIOS_FLASH_WP_R_L.</div><div class='add'>+		 */</div><div class='add'>+		"AP_FLASH_WP_L",</div><div class='add'>+		"EC_AP_INT_ODL",</div><div class='add'>+		"IT6505_INT_ODL",</div><div class='add'>+		"H1_INT_OD_L",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"AP_SPI_FLASH_MISO",</div><div class='add'>+		"AP_SPI_FLASH_CS_L",</div><div class='add'>+		"AP_SPI_FLASH_MOSI",</div><div class='add'>+		"AP_SPI_FLASH_CLK",</div><div class='add'>+		"DA7219_IRQ",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"";</div><div class='add'>+</div><div class='add'>+	ppvarp_lcd_en: ppvarp-lcd-en-pins {</div><div class='add'>+		pins1 {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO66__FUNC_GPIO66&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ppvarn_lcd_en: ppvarn-lcd-en-pins {</div><div class='add'>+		pins1 {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO166__FUNC_GPIO166&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pp1800_lcd_en: pp1800-lcd-en-pins {</div><div class='add'>+		pins1 {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO36__FUNC_GPIO36&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	open_touch: opentouch-pins {</div><div class='add'>+		pins-intn {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO155__FUNC_GPIO155&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-rst {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO156__FUNC_GPIO156&gt;;</div><div class='add'>+</div><div class='add'>+			/*</div><div class='add'>+			 * The pen driver doesn't currently support  driving</div><div class='add'>+			 * this reset line.  By specifying output-high here</div><div class='add'>+			 * we're relying on the fact that this pin has a default</div><div class='add'>+			 * pulldown at boot (which makes sure the pen was in</div><div class='add'>+			 * reset if it was powered) and then we set it high here</div><div class='add'>+			 * to take it out of reset.  Better would be if the pen</div><div class='add'>+			 * driver could control this and we could remove</div><div class='add'>+			 * "output-high" here.</div><div class='add'>+			 */</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cros_ec {</div><div class='add'>+	cbas {</div><div class='add'>+		compatible = "google,cros-cbas";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	keyboard-controller {</div><div class='add'>+		compatible = "google,cros-ec-keyb-switches";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qca_wifi {</div><div class='add'>+	qcom,ath10k-calibration-variant = "LE_Krane";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sound {</div><div class='add'>+	compatible = "mediatek,mt8183_mt6358_ts3a227_max98357";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi<br/>new file mode 100644<br/>index 000000000000..4b87d4940c8c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi</a></div><div class='hunk'>@@ -0,0 +1,982 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2018 MediaTek Inc.</div><div class='add'>+ * Author: Ben Ho &lt;ben.ho@mediatek.com&gt;</div><div class='add'>+ *	   Erin Lo &lt;erin.lo@mediatek.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include "mt8183.dtsi"</div><div class='add'>+#include "mt6358.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+		mmc0 = &amp;mmc0;</div><div class='add'>+		mmc1 = &amp;mmc1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	backlight_lcd0: backlight_lcd0 {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		pwms = &lt;&amp;pwm0 0 500000&gt;;</div><div class='add'>+		power-supply = &lt;&amp;reg_vsys&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;pio 176 0&gt;;</div><div class='add'>+		brightness-levels = &lt;0 1023&gt;;</div><div class='add'>+		num-interpolated-steps = &lt;1023&gt;;</div><div class='add'>+		default-brightness-level = &lt;576&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0 0x40000000 0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk32k: oscillator1 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;32768&gt;;</div><div class='add'>+		clock-output-names = "clk32k";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	it6505_pp18_reg: regulator0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "it6505_pp18";</div><div class='add'>+		gpio = &lt;&amp;pio 178 0&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		vin-supply = &lt;&amp;pp1800_alw&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pp1800_alw: regulator5 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "pp1800_alw";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;reg_vsys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pp3300_alw: regulator6 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "pp3300_alw";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;reg_vsys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* system wide semi-regulated power rail from charger */</div><div class='add'>+	reg_vsys: regulator-vsys {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vsys";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved_memory: reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		afe_dma_mem: audio-dma-pool {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			size = &lt;0 0x100000&gt;;</div><div class='add'>+			alignment = &lt;0 0x10&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		scp_mem_reserved: memory@50000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x50000000 0 0x2900000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound: mt8183-sound {</div><div class='add'>+		mediatek,platform = &lt;&amp;afe&gt;;</div><div class='add'>+		pinctrl-names = "default",</div><div class='add'>+				"aud_tdm_out_on",</div><div class='add'>+				"aud_tdm_out_off";</div><div class='add'>+		pinctrl-0 = &lt;&amp;aud_pins_default&gt;;</div><div class='add'>+		pinctrl-1 = &lt;&amp;aud_pins_tdm_out_on&gt;;</div><div class='add'>+		pinctrl-2 = &lt;&amp;aud_pins_tdm_out_off&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	btsco: bt-sco {</div><div class='add'>+		compatible = "linux,bt-sco";</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wifi_pwrseq: wifi-pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-simple";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;wifi_pins_pwrseq&gt;;</div><div class='add'>+</div><div class='add'>+		/* Toggle WIFI_ENABLE to reset the chip. */</div><div class='add'>+		reset-gpios = &lt;&amp;pio 119 1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wifi_wakeup: wifi-wakeup {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;wifi_pins_wakeup&gt;;</div><div class='add'>+</div><div class='add'>+		wifi_wakeup_event: event-wowlan {</div><div class='add'>+			label = "Wake on WiFi";</div><div class='add'>+			gpios = &lt;&amp;pio 113 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,code = &lt;KEY_WAKEUP&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	tboard_thermistor1: thermal-sensor1 {</div><div class='add'>+		compatible = "generic-adc-thermal";</div><div class='add'>+		#thermal-sensor-cells = &lt;0&gt;;</div><div class='add'>+		io-channels = &lt;&amp;auxadc 0&gt;;</div><div class='add'>+		io-channel-names = "sensor-channel";</div><div class='add'>+		temperature-lookup-table = &lt;    (-5000) 1553</div><div class='add'>+						0 1488</div><div class='add'>+						5000 1412</div><div class='add'>+						10000 1326</div><div class='add'>+						15000 1232</div><div class='add'>+						20000 1132</div><div class='add'>+						25000 1029</div><div class='add'>+						30000 925</div><div class='add'>+						35000 823</div><div class='add'>+						40000 726</div><div class='add'>+						45000 635</div><div class='add'>+						50000 552</div><div class='add'>+						55000 478</div><div class='add'>+						60000 411</div><div class='add'>+						65000 353</div><div class='add'>+						70000 303</div><div class='add'>+						75000 260</div><div class='add'>+						80000 222</div><div class='add'>+						85000 190</div><div class='add'>+						90000 163</div><div class='add'>+						95000 140</div><div class='add'>+						100000 121</div><div class='add'>+						105000 104</div><div class='add'>+						110000 90</div><div class='add'>+						115000 78</div><div class='add'>+						120000 67</div><div class='add'>+						125000 59&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	tboard_thermistor2: thermal-sensor2 {</div><div class='add'>+		compatible = "generic-adc-thermal";</div><div class='add'>+		#thermal-sensor-cells = &lt;0&gt;;</div><div class='add'>+		io-channels = &lt;&amp;auxadc 1&gt;;</div><div class='add'>+		io-channel-names = "sensor-channel";</div><div class='add'>+		temperature-lookup-table = &lt;    (-5000) 1553</div><div class='add'>+						0 1488</div><div class='add'>+						5000 1412</div><div class='add'>+						10000 1326</div><div class='add'>+						15000 1232</div><div class='add'>+						20000 1132</div><div class='add'>+						25000 1029</div><div class='add'>+						30000 925</div><div class='add'>+						35000 823</div><div class='add'>+						40000 726</div><div class='add'>+						45000 635</div><div class='add'>+						50000 552</div><div class='add'>+						55000 478</div><div class='add'>+						60000 411</div><div class='add'>+						65000 353</div><div class='add'>+						70000 303</div><div class='add'>+						75000 260</div><div class='add'>+						80000 222</div><div class='add'>+						85000 190</div><div class='add'>+						90000 163</div><div class='add'>+						95000 140</div><div class='add'>+						100000 121</div><div class='add'>+						105000 104</div><div class='add'>+						110000 90</div><div class='add'>+						115000 78</div><div class='add'>+						120000 67</div><div class='add'>+						125000 59&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;afe {</div><div class='add'>+	memory-region = &lt;&amp;afe_dma_mem&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;auxadc {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cci {</div><div class='add'>+	proc-supply = &lt;&amp;mt6358_vproc12_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	proc-supply = &lt;&amp;mt6358_vproc12_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu1 {</div><div class='add'>+	proc-supply = &lt;&amp;mt6358_vproc12_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu2 {</div><div class='add'>+	proc-supply = &lt;&amp;mt6358_vproc12_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu3 {</div><div class='add'>+	proc-supply = &lt;&amp;mt6358_vproc12_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu4 {</div><div class='add'>+	proc-supply = &lt;&amp;mt6358_vproc11_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu5 {</div><div class='add'>+	proc-supply = &lt;&amp;mt6358_vproc11_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu6 {</div><div class='add'>+	proc-supply = &lt;&amp;mt6358_vproc11_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu7 {</div><div class='add'>+	proc-supply = &lt;&amp;mt6358_vproc11_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsi0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gic {</div><div class='add'>+	mediatek,broken-save-restore-fw;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	mali-supply = &lt;&amp;mt6358_vgpu_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c0_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c1_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c3_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c5 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c5_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c6 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c6_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_tx0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-names = "default", "state_uhs";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc0_pins_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;mmc0_pins_uhs&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	cap-mmc-highspeed;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	mmc-hs400-1_8v;</div><div class='add'>+	cap-mmc-hw-reset;</div><div class='add'>+	no-sdio;</div><div class='add'>+	no-sd;</div><div class='add'>+	hs400-ds-delay = &lt;0x12814&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;mt6358_vemc_reg&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;mt6358_vio18_reg&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;topckgen CLK_TOP_MUX_MSDC50_0&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_MSDCPLL_CK&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-names = "default", "state_uhs";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc1_pins_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;mmc1_pins_uhs&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;pp3300_alw&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;pp1800_alw&gt;;</div><div class='add'>+	mmc-pwrseq = &lt;&amp;wifi_pwrseq&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	sd-uhs-sdr50;</div><div class='add'>+	sd-uhs-sdr104;</div><div class='add'>+	keep-power-in-suspend;</div><div class='add'>+	wakeup-source;</div><div class='add'>+	cap-sdio-irq;</div><div class='add'>+	non-removable;</div><div class='add'>+	no-mmc;</div><div class='add'>+	no-sd;</div><div class='add'>+	assigned-clocks = &lt;&amp;topckgen CLK_TOP_MUX_MSDC30_1&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_MSDCPLL_D2&gt;;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	qca_wifi: qca-wifi@1 {</div><div class='add'>+		compatible = "qcom,ath10k";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6358_vdram2_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6358codec {</div><div class='add'>+	Avdd-supply = &lt;&amp;mt6358_vaud28_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6358regulator {</div><div class='add'>+	vsys-ldo1-supply = &lt;&amp;reg_vsys&gt;;</div><div class='add'>+	vsys-ldo2-supply = &lt;&amp;reg_vsys&gt;;</div><div class='add'>+	vsys-ldo3-supply = &lt;&amp;reg_vsys&gt;;</div><div class='add'>+	vsys-vcore-supply = &lt;&amp;reg_vsys&gt;;</div><div class='add'>+	vsys-vdram1-supply = &lt;&amp;reg_vsys&gt;;</div><div class='add'>+	vsys-vgpu-supply = &lt;&amp;reg_vsys&gt;;</div><div class='add'>+	vsys-vmodem-supply = &lt;&amp;reg_vsys&gt;;</div><div class='add'>+	vsys-vpa-supply = &lt;&amp;reg_vsys&gt;;</div><div class='add'>+	vsys-vproc11-supply = &lt;&amp;reg_vsys&gt;;</div><div class='add'>+	vsys-vproc12-supply = &lt;&amp;reg_vsys&gt;;</div><div class='add'>+	vsys-vs1-supply = &lt;&amp;reg_vsys&gt;;</div><div class='add'>+	vsys-vs2-supply = &lt;&amp;reg_vsys&gt;;</div><div class='add'>+	vs1-ldo1-supply = &lt;&amp;mt6358_vs1_reg&gt;;</div><div class='add'>+	vs2-ldo1-supply = &lt;&amp;mt6358_vdram1_reg&gt;;</div><div class='add'>+	vs2-ldo2-supply = &lt;&amp;mt6358_vs2_reg&gt;;</div><div class='add'>+	vs2-ldo3-supply = &lt;&amp;mt6358_vs2_reg&gt;;</div><div class='add'>+	vs2-ldo4-supply = &lt;&amp;mt6358_vs2_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6358_vgpu_reg {</div><div class='add'>+	regulator-max-microvolt = &lt;900000&gt;;</div><div class='add'>+</div><div class='add'>+	regulator-coupled-with = &lt;&amp;mt6358_vsram_gpu_reg&gt;;</div><div class='add'>+	regulator-coupled-max-spread = &lt;100000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6358_vsim1_reg {</div><div class='add'>+	regulator-min-microvolt = &lt;2700000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;2700000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6358_vsim2_reg {</div><div class='add'>+	regulator-min-microvolt = &lt;2700000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;2700000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6358_vsram_gpu_reg {</div><div class='add'>+	regulator-min-microvolt = &lt;850000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+</div><div class='add'>+	regulator-coupled-with = &lt;&amp;mt6358_vgpu_reg&gt;;</div><div class='add'>+	regulator-coupled-max-spread = &lt;100000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	aud_pins_default: audio-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO97__FUNC_I2S2_MCK&gt;,</div><div class='add'>+				&lt;PINMUX_GPIO98__FUNC_I2S2_BCK&gt;,</div><div class='add'>+				&lt;PINMUX_GPIO101__FUNC_I2S2_LRCK&gt;,</div><div class='add'>+				&lt;PINMUX_GPIO102__FUNC_I2S2_DI&gt;,</div><div class='add'>+				&lt;PINMUX_GPIO3__FUNC_I2S3_DO&gt;, /*i2s to da7219/max98357*/</div><div class='add'>+				&lt;PINMUX_GPIO89__FUNC_I2S5_BCK&gt;,</div><div class='add'>+				&lt;PINMUX_GPIO90__FUNC_I2S5_LRCK&gt;,</div><div class='add'>+				&lt;PINMUX_GPIO91__FUNC_I2S5_DO&gt;,</div><div class='add'>+				&lt;PINMUX_GPIO174__FUNC_I2S0_DI&gt;, /*i2s to wifi/bt*/</div><div class='add'>+				&lt;PINMUX_GPIO136__FUNC_AUD_CLK_MOSI&gt;,</div><div class='add'>+				&lt;PINMUX_GPIO137__FUNC_AUD_SYNC_MOSI&gt;,</div><div class='add'>+				&lt;PINMUX_GPIO138__FUNC_AUD_DAT_MOSI0&gt;,</div><div class='add'>+				&lt;PINMUX_GPIO139__FUNC_AUD_DAT_MOSI1&gt;,</div><div class='add'>+				&lt;PINMUX_GPIO140__FUNC_AUD_CLK_MISO&gt;,</div><div class='add'>+				&lt;PINMUX_GPIO141__FUNC_AUD_SYNC_MISO&gt;,</div><div class='add'>+				&lt;PINMUX_GPIO142__FUNC_AUD_DAT_MISO0&gt;,</div><div class='add'>+				&lt;PINMUX_GPIO143__FUNC_AUD_DAT_MISO1&gt;; /*mtkaif3.0*/</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_pins_tdm_out_on: audio-tdmout-on-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO169__FUNC_TDM_BCK_2ND&gt;,</div><div class='add'>+				&lt;PINMUX_GPIO170__FUNC_TDM_LRCK_2ND&gt;,</div><div class='add'>+				&lt;PINMUX_GPIO171__FUNC_TDM_DATA0_2ND&gt;,</div><div class='add'>+				&lt;PINMUX_GPIO172__FUNC_TDM_DATA1_2ND&gt;,</div><div class='add'>+				&lt;PINMUX_GPIO173__FUNC_TDM_DATA2_2ND&gt;,</div><div class='add'>+				&lt;PINMUX_GPIO10__FUNC_TDM_DATA3&gt;; /*8ch-i2s to it6505*/</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_pins_tdm_out_off: audio-tdmout-off-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO169__FUNC_GPIO169&gt;,</div><div class='add'>+				&lt;PINMUX_GPIO170__FUNC_GPIO170&gt;,</div><div class='add'>+				&lt;PINMUX_GPIO171__FUNC_GPIO171&gt;,</div><div class='add'>+				&lt;PINMUX_GPIO172__FUNC_GPIO172&gt;,</div><div class='add'>+				&lt;PINMUX_GPIO173__FUNC_GPIO173&gt;,</div><div class='add'>+				&lt;PINMUX_GPIO10__FUNC_GPIO10&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-down;</div><div class='add'>+			drive-strength = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bt_pins: bt-pins {</div><div class='add'>+		pins-bt-en {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO120__FUNC_GPIO120&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ec_ap_int_odl: ec-ap-int-odl-pins {</div><div class='add'>+		pins-intn {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO151__FUNC_GPIO151&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	h1_int_od_l: h1-int-od-l-pins {</div><div class='add'>+		pins-intn {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO153__FUNC_GPIO153&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c0_pins: i2c0-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO82__FUNC_SDA0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO83__FUNC_SCL0&gt;;</div><div class='add'>+			mediatek,pull-up-adv = &lt;3&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c1_pins: i2c1-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO81__FUNC_SDA1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO84__FUNC_SCL1&gt;;</div><div class='add'>+			mediatek,pull-up-adv = &lt;3&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c2_pins: i2c2-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO103__FUNC_SCL2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO104__FUNC_SDA2&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c3_pins: i2c3-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO50__FUNC_SCL3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO51__FUNC_SDA3&gt;;</div><div class='add'>+			mediatek,pull-up-adv = &lt;3&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c4_pins: i2c4-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO105__FUNC_SCL4&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO106__FUNC_SDA4&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c5_pins: i2c5-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO48__FUNC_SCL5&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO49__FUNC_SDA5&gt;;</div><div class='add'>+			mediatek,pull-up-adv = &lt;3&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c6_pins: i2c6-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO11__FUNC_SCL6&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO12__FUNC_SDA6&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc0_pins_default: mmc0-default-pins {</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO123__FUNC_MSDC0_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO128__FUNC_MSDC0_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO125__FUNC_MSDC0_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO132__FUNC_MSDC0_DAT3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO126__FUNC_MSDC0_DAT4&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO129__FUNC_MSDC0_DAT5&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO127__FUNC_MSDC0_DAT6&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO130__FUNC_MSDC0_DAT7&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO122__FUNC_MSDC0_CMD&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;MTK_DRIVE_14mA&gt;;</div><div class='add'>+			mediatek,pull-up-adv = &lt;01&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO124__FUNC_MSDC0_CLK&gt;;</div><div class='add'>+			drive-strength = &lt;MTK_DRIVE_14mA&gt;;</div><div class='add'>+			mediatek,pull-down-adv = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-rst {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO133__FUNC_MSDC0_RSTB&gt;;</div><div class='add'>+			drive-strength = &lt;MTK_DRIVE_14mA&gt;;</div><div class='add'>+			mediatek,pull-down-adv = &lt;01&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc0_pins_uhs: mmc0-pins-uhs {</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO123__FUNC_MSDC0_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO128__FUNC_MSDC0_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO125__FUNC_MSDC0_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO132__FUNC_MSDC0_DAT3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO126__FUNC_MSDC0_DAT4&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO129__FUNC_MSDC0_DAT5&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO127__FUNC_MSDC0_DAT6&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO130__FUNC_MSDC0_DAT7&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO122__FUNC_MSDC0_CMD&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;MTK_DRIVE_14mA&gt;;</div><div class='add'>+			mediatek,pull-up-adv = &lt;01&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO124__FUNC_MSDC0_CLK&gt;;</div><div class='add'>+			drive-strength = &lt;MTK_DRIVE_14mA&gt;;</div><div class='add'>+			mediatek,pull-down-adv = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-ds {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO131__FUNC_MSDC0_DSL&gt;;</div><div class='add'>+			drive-strength = &lt;MTK_DRIVE_14mA&gt;;</div><div class='add'>+			mediatek,pull-down-adv = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-rst {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO133__FUNC_MSDC0_RSTB&gt;;</div><div class='add'>+			drive-strength = &lt;MTK_DRIVE_14mA&gt;;</div><div class='add'>+			mediatek,pull-up-adv = &lt;01&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc1_pins_default: mmc1-default-pins {</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO31__FUNC_MSDC1_CMD&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO32__FUNC_MSDC1_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO34__FUNC_MSDC1_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO33__FUNC_MSDC1_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO30__FUNC_MSDC1_DAT3&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			mediatek,pull-up-adv = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO29__FUNC_MSDC1_CLK&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			mediatek,pull-down-adv = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc1_pins_uhs: mmc1-uhs-pins {</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO31__FUNC_MSDC1_CMD&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO32__FUNC_MSDC1_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO34__FUNC_MSDC1_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO33__FUNC_MSDC1_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO30__FUNC_MSDC1_DAT3&gt;;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			mediatek,pull-up-adv = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO29__FUNC_MSDC1_CLK&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			mediatek,pull-down-adv = &lt;2&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	panel_pins_default: panel-pins {</div><div class='add'>+		pins-panel-reset {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO45__FUNC_GPIO45&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pwm0_pin_default: pwm0-pins {</div><div class='add'>+		pins1 {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO176__FUNC_GPIO176&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+		pins2 {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO43__FUNC_DISP_PWM&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	scp_pins: scp-pins {</div><div class='add'>+		pins-scp-uart {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO110__FUNC_TP_URXD1_AO&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO112__FUNC_TP_UTXD1_AO&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi0_pins: spi0-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO85__FUNC_SPI0_MI&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO86__FUNC_GPIO86&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO87__FUNC_SPI0_MO&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO88__FUNC_SPI0_CLK&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi1_pins: spi1-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO161__FUNC_SPI1_A_MI&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO162__FUNC_SPI1_A_CSB&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO163__FUNC_SPI1_A_MO&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO164__FUNC_SPI1_A_CLK&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi2_pins: spi2-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO0__FUNC_SPI2_CSB&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO1__FUNC_SPI2_MO&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO2__FUNC_SPI2_CLK&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+		pins-miso {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO94__FUNC_SPI2_MI&gt;;</div><div class='add'>+			mediatek,pull-down-adv = &lt;00&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi3_pins: spi3-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO21__FUNC_SPI3_MI&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO22__FUNC_SPI3_CSB&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO23__FUNC_SPI3_MO&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO24__FUNC_SPI3_CLK&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi4_pins: spi4-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO17__FUNC_SPI4_MI&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO18__FUNC_SPI4_CSB&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO19__FUNC_SPI4_MO&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO20__FUNC_SPI4_CLK&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi5_pins: spi5-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO13__FUNC_SPI5_MI&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO14__FUNC_SPI5_CSB&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO15__FUNC_SPI5_MO&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO16__FUNC_SPI5_CLK&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart0_pins_default: uart0-pins {</div><div class='add'>+		pins-rx {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO95__FUNC_URXD0&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+		pins-tx {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO96__FUNC_UTXD0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart1_pins_default: uart1-pins {</div><div class='add'>+		pins-rx {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO121__FUNC_URXD1&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+		pins-tx {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO115__FUNC_UTXD1&gt;;</div><div class='add'>+		};</div><div class='add'>+		pins-rts {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO47__FUNC_URTS1&gt;;</div><div class='add'>+		};</div><div class='add'>+		pins-cts {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO46__FUNC_UCTS1&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart1_pins_sleep: uart1-sleep-pins {</div><div class='add'>+		pins-rx {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO121__FUNC_GPIO121&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+		pins-tx {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO115__FUNC_UTXD1&gt;;</div><div class='add'>+		};</div><div class='add'>+		pins-rts {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO47__FUNC_URTS1&gt;;</div><div class='add'>+		};</div><div class='add'>+		pins-cts {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO46__FUNC_UCTS1&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wifi_pins_pwrseq: wifi-pwr-pins {</div><div class='add'>+		pins-wifi-enable {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO119__FUNC_GPIO119&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wifi_pins_wakeup: wifi-wake-pins {</div><div class='add'>+		pins-wifi-wakeup {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO113__FUNC_GPIO113&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pmic {</div><div class='add'>+	interrupts-extended = &lt;&amp;pio 182 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm0_pin_default&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;scp {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	firmware-name = "mediatek/mt8183/scp.img";</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;scp_pins&gt;;</div><div class='add'>+</div><div class='add'>+	cros-ec-rpmsg {</div><div class='add'>+		compatible = "google,cros-ec-rpmsg";</div><div class='add'>+		mediatek,rpmsg-name = "cros-ec-rpmsg";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mfg_async {</div><div class='add'>+	domain-supply = &lt;&amp;mt6358_vsram_gpu_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mfg {</div><div class='add'>+	domain-supply = &lt;&amp;mt6358_vgpu_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;spi0_pins&gt;;</div><div class='add'>+	mediatek,pad-select = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+	cs-gpios = &lt;&amp;pio 86 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+	tpm@0 {</div><div class='add'>+		compatible = "google,cr50";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;1000000&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;h1_int_od_l&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 153 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;spi1_pins&gt;;</div><div class='add'>+	mediatek,pad-select = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	w25q64dw: flash@0 {</div><div class='add'>+		compatible = "winbond,w25q64dw", "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;25000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;spi2_pins&gt;;</div><div class='add'>+	mediatek,pad-select = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	cros_ec: cros-ec@0 {</div><div class='add'>+		compatible = "google,cros-ec-spi";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;3000000&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 151 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;ec_ap_int_odl&gt;;</div><div class='add'>+		wakeup-source;</div><div class='add'>+</div><div class='add'>+		i2c_tunnel: i2c-tunnel {</div><div class='add'>+			compatible = "google,cros-ec-i2c-tunnel";</div><div class='add'>+			google,remote-bus = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usbc_extcon: extcon0 {</div><div class='add'>+			compatible = "google,extcon-usbc-cros-ec";</div><div class='add'>+			google,usb-port-id = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		typec {</div><div class='add'>+			compatible = "google,cros-ec-typec";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			usb_c0: connector@0 {</div><div class='add'>+				compatible = "usb-c-connector";</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				power-role = "dual";</div><div class='add'>+				data-role = "host";</div><div class='add'>+				try-power-role = "sink";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;spi3_pins&gt;;</div><div class='add'>+	mediatek,pad-select = &lt;0&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;spi4_pins&gt;;</div><div class='add'>+	mediatek,pad-select = &lt;0&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi5 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;spi5_pins&gt;;</div><div class='add'>+	mediatek,pad-select = &lt;0&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ssusb {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	wakeup-source;</div><div class='add'>+	vusb33-supply = &lt;&amp;mt6358_vusb_reg&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;thermal_zones {</div><div class='add'>+	tboard1-thermal {</div><div class='add'>+		polling-delay = &lt;1000&gt;; /* milliseconds */</div><div class='add'>+		polling-delay-passive = &lt;0&gt;; /* milliseconds */</div><div class='add'>+		thermal-sensors = &lt;&amp;tboard_thermistor1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	tboard2-thermal {</div><div class='add'>+		polling-delay = &lt;1000&gt;; /* milliseconds */</div><div class='add'>+		polling-delay-passive = &lt;0&gt;; /* milliseconds */</div><div class='add'>+		thermal-sensors = &lt;&amp;tboard_thermistor2&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;u3phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart0_pins_default&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart1_pins_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;uart1_pins_sleep&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+	/delete-property/ interrupts;</div><div class='add'>+	interrupts-extended = &lt;&amp;sysirq GIC_SPI 92 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			      &lt;&amp;pio 121 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+</div><div class='add'>+	bluetooth: bluetooth {</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;bt_pins&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+		compatible = "qcom,qca6174-bt";</div><div class='add'>+		enable-gpios = &lt;&amp;pio 120 0&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk32k&gt;;</div><div class='add'>+		firmware-name = "nvm_00440302_i2s.bin";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_host {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	vusb33-supply = &lt;&amp;mt6358_vusb_reg&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	hub@1 {</div><div class='add'>+		compatible = "usb5e3,610";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include &lt;arm/cros-ec-sbs.dtsi&gt;</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h b/arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h<br/>deleted file mode 100644<br/>index 6221cd712718..000000000000<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h</a><br/>+++ /dev/null</div><div class='hunk'>@@ -1,1120 +0,0 @@</div><div class='del'>-/* SPDX-License-Identifier: GPL-2.0 */</div><div class='del'>-/*</div><div class='del'>- * Copyright (C) 2018 MediaTek Inc.</div><div class='del'>- * Author: Zhiyong Tao &lt;zhiyong.tao@mediatek.com&gt;</div><div class='del'>- *</div><div class='del'>- */</div><div class='del'>-</div><div class='del'>-#ifndef __MT8183_PINFUNC_H</div><div class='del'>-#define __MT8183_PINFUNC_H</div><div class='del'>-</div><div class='del'>-#include &lt;dt-bindings/pinctrl/mt65xx.h&gt;</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)</div><div class='del'>-#define PINMUX_GPIO0__FUNC_MRG_SYNC (MTK_PIN_NO(0) | 1)</div><div class='del'>-#define PINMUX_GPIO0__FUNC_PCM0_SYNC (MTK_PIN_NO(0) | 2)</div><div class='del'>-#define PINMUX_GPIO0__FUNC_TP_GPIO0_AO (MTK_PIN_NO(0) | 3)</div><div class='del'>-#define PINMUX_GPIO0__FUNC_SRCLKENAI0 (MTK_PIN_NO(0) | 4)</div><div class='del'>-#define PINMUX_GPIO0__FUNC_SCP_SPI2_CS (MTK_PIN_NO(0) | 5)</div><div class='del'>-#define PINMUX_GPIO0__FUNC_I2S3_MCK (MTK_PIN_NO(0) | 6)</div><div class='del'>-#define PINMUX_GPIO0__FUNC_SPI2_CSB (MTK_PIN_NO(0) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)</div><div class='del'>-#define PINMUX_GPIO1__FUNC_MRG_CLK (MTK_PIN_NO(1) | 1)</div><div class='del'>-#define PINMUX_GPIO1__FUNC_PCM0_CLK (MTK_PIN_NO(1) | 2)</div><div class='del'>-#define PINMUX_GPIO1__FUNC_TP_GPIO1_AO (MTK_PIN_NO(1) | 3)</div><div class='del'>-#define PINMUX_GPIO1__FUNC_CLKM3 (MTK_PIN_NO(1) | 4)</div><div class='del'>-#define PINMUX_GPIO1__FUNC_SCP_SPI2_MO (MTK_PIN_NO(1) | 5)</div><div class='del'>-#define PINMUX_GPIO1__FUNC_I2S3_BCK (MTK_PIN_NO(1) | 6)</div><div class='del'>-#define PINMUX_GPIO1__FUNC_SPI2_MO (MTK_PIN_NO(1) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)</div><div class='del'>-#define PINMUX_GPIO2__FUNC_MRG_DO (MTK_PIN_NO(2) | 1)</div><div class='del'>-#define PINMUX_GPIO2__FUNC_PCM0_DO (MTK_PIN_NO(2) | 2)</div><div class='del'>-#define PINMUX_GPIO2__FUNC_TP_GPIO2_AO (MTK_PIN_NO(2) | 3)</div><div class='del'>-#define PINMUX_GPIO2__FUNC_SCL6 (MTK_PIN_NO(2) | 4)</div><div class='del'>-#define PINMUX_GPIO2__FUNC_SCP_SPI2_CK (MTK_PIN_NO(2) | 5)</div><div class='del'>-#define PINMUX_GPIO2__FUNC_I2S3_LRCK (MTK_PIN_NO(2) | 6)</div><div class='del'>-#define PINMUX_GPIO2__FUNC_SPI2_CLK (MTK_PIN_NO(2) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)</div><div class='del'>-#define PINMUX_GPIO3__FUNC_MRG_DI (MTK_PIN_NO(3) | 1)</div><div class='del'>-#define PINMUX_GPIO3__FUNC_PCM0_DI (MTK_PIN_NO(3) | 2)</div><div class='del'>-#define PINMUX_GPIO3__FUNC_TP_GPIO3_AO (MTK_PIN_NO(3) | 3)</div><div class='del'>-#define PINMUX_GPIO3__FUNC_SDA6 (MTK_PIN_NO(3) | 4)</div><div class='del'>-#define PINMUX_GPIO3__FUNC_TDM_MCK (MTK_PIN_NO(3) | 5)</div><div class='del'>-#define PINMUX_GPIO3__FUNC_I2S3_DO (MTK_PIN_NO(3) | 6)</div><div class='del'>-#define PINMUX_GPIO3__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(3) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)</div><div class='del'>-#define PINMUX_GPIO4__FUNC_PWM_B (MTK_PIN_NO(4) | 1)</div><div class='del'>-#define PINMUX_GPIO4__FUNC_I2S0_MCK (MTK_PIN_NO(4) | 2)</div><div class='del'>-#define PINMUX_GPIO4__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(4) | 3)</div><div class='del'>-#define PINMUX_GPIO4__FUNC_MD_URXD1 (MTK_PIN_NO(4) | 4)</div><div class='del'>-#define PINMUX_GPIO4__FUNC_TDM_BCK (MTK_PIN_NO(4) | 5)</div><div class='del'>-#define PINMUX_GPIO4__FUNC_TP_GPIO4_AO (MTK_PIN_NO(4) | 6)</div><div class='del'>-#define PINMUX_GPIO4__FUNC_DAP_MD32_SWD (MTK_PIN_NO(4) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)</div><div class='del'>-#define PINMUX_GPIO5__FUNC_PWM_C (MTK_PIN_NO(5) | 1)</div><div class='del'>-#define PINMUX_GPIO5__FUNC_I2S0_BCK (MTK_PIN_NO(5) | 2)</div><div class='del'>-#define PINMUX_GPIO5__FUNC_SSPM_URXD_AO (MTK_PIN_NO(5) | 3)</div><div class='del'>-#define PINMUX_GPIO5__FUNC_MD_UTXD1 (MTK_PIN_NO(5) | 4)</div><div class='del'>-#define PINMUX_GPIO5__FUNC_TDM_LRCK (MTK_PIN_NO(5) | 5)</div><div class='del'>-#define PINMUX_GPIO5__FUNC_TP_GPIO5_AO (MTK_PIN_NO(5) | 6)</div><div class='del'>-#define PINMUX_GPIO5__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(5) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)</div><div class='del'>-#define PINMUX_GPIO6__FUNC_PWM_A (MTK_PIN_NO(6) | 1)</div><div class='del'>-#define PINMUX_GPIO6__FUNC_I2S0_LRCK (MTK_PIN_NO(6) | 2)</div><div class='del'>-#define PINMUX_GPIO6__FUNC_IDDIG (MTK_PIN_NO(6) | 3)</div><div class='del'>-#define PINMUX_GPIO6__FUNC_MD_URXD0 (MTK_PIN_NO(6) | 4)</div><div class='del'>-#define PINMUX_GPIO6__FUNC_TDM_DATA0 (MTK_PIN_NO(6) | 5)</div><div class='del'>-#define PINMUX_GPIO6__FUNC_TP_GPIO6_AO (MTK_PIN_NO(6) | 6)</div><div class='del'>-#define PINMUX_GPIO6__FUNC_CMFLASH (MTK_PIN_NO(6) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)</div><div class='del'>-#define PINMUX_GPIO7__FUNC_SPI1_B_MI (MTK_PIN_NO(7) | 1)</div><div class='del'>-#define PINMUX_GPIO7__FUNC_I2S0_DI (MTK_PIN_NO(7) | 2)</div><div class='del'>-#define PINMUX_GPIO7__FUNC_USB_DRVVBUS (MTK_PIN_NO(7) | 3)</div><div class='del'>-#define PINMUX_GPIO7__FUNC_MD_UTXD0 (MTK_PIN_NO(7) | 4)</div><div class='del'>-#define PINMUX_GPIO7__FUNC_TDM_DATA1 (MTK_PIN_NO(7) | 5)</div><div class='del'>-#define PINMUX_GPIO7__FUNC_TP_GPIO7_AO (MTK_PIN_NO(7) | 6)</div><div class='del'>-#define PINMUX_GPIO7__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(7) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)</div><div class='del'>-#define PINMUX_GPIO8__FUNC_SPI1_B_CSB (MTK_PIN_NO(8) | 1)</div><div class='del'>-#define PINMUX_GPIO8__FUNC_ANT_SEL3 (MTK_PIN_NO(8) | 2)</div><div class='del'>-#define PINMUX_GPIO8__FUNC_SCL7 (MTK_PIN_NO(8) | 3)</div><div class='del'>-#define PINMUX_GPIO8__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(8) | 4)</div><div class='del'>-#define PINMUX_GPIO8__FUNC_TDM_DATA2 (MTK_PIN_NO(8) | 5)</div><div class='del'>-#define PINMUX_GPIO8__FUNC_MD_INT0 (MTK_PIN_NO(8) | 6)</div><div class='del'>-#define PINMUX_GPIO8__FUNC_JTRSTN_SEL1 (MTK_PIN_NO(8) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)</div><div class='del'>-#define PINMUX_GPIO9__FUNC_SPI1_B_MO (MTK_PIN_NO(9) | 1)</div><div class='del'>-#define PINMUX_GPIO9__FUNC_ANT_SEL4 (MTK_PIN_NO(9) | 2)</div><div class='del'>-#define PINMUX_GPIO9__FUNC_CMMCLK2 (MTK_PIN_NO(9) | 3)</div><div class='del'>-#define PINMUX_GPIO9__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(9) | 4)</div><div class='del'>-#define PINMUX_GPIO9__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(9) | 5)</div><div class='del'>-#define PINMUX_GPIO9__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(9) | 6)</div><div class='del'>-#define PINMUX_GPIO9__FUNC_DBG_MON_B10 (MTK_PIN_NO(9) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)</div><div class='del'>-#define PINMUX_GPIO10__FUNC_SPI1_B_CLK (MTK_PIN_NO(10) | 1)</div><div class='del'>-#define PINMUX_GPIO10__FUNC_ANT_SEL5 (MTK_PIN_NO(10) | 2)</div><div class='del'>-#define PINMUX_GPIO10__FUNC_CMMCLK3 (MTK_PIN_NO(10) | 3)</div><div class='del'>-#define PINMUX_GPIO10__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(10) | 4)</div><div class='del'>-#define PINMUX_GPIO10__FUNC_TDM_DATA3 (MTK_PIN_NO(10) | 5)</div><div class='del'>-#define PINMUX_GPIO10__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(10) | 6)</div><div class='del'>-#define PINMUX_GPIO10__FUNC_DBG_MON_B11 (MTK_PIN_NO(10) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)</div><div class='del'>-#define PINMUX_GPIO11__FUNC_TP_URXD1_AO (MTK_PIN_NO(11) | 1)</div><div class='del'>-#define PINMUX_GPIO11__FUNC_IDDIG (MTK_PIN_NO(11) | 2)</div><div class='del'>-#define PINMUX_GPIO11__FUNC_SCL6 (MTK_PIN_NO(11) | 3)</div><div class='del'>-#define PINMUX_GPIO11__FUNC_UCTS1 (MTK_PIN_NO(11) | 4)</div><div class='del'>-#define PINMUX_GPIO11__FUNC_UCTS0 (MTK_PIN_NO(11) | 5)</div><div class='del'>-#define PINMUX_GPIO11__FUNC_SRCLKENAI1 (MTK_PIN_NO(11) | 6)</div><div class='del'>-#define PINMUX_GPIO11__FUNC_I2S5_MCK (MTK_PIN_NO(11) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)</div><div class='del'>-#define PINMUX_GPIO12__FUNC_TP_UTXD1_AO (MTK_PIN_NO(12) | 1)</div><div class='del'>-#define PINMUX_GPIO12__FUNC_USB_DRVVBUS (MTK_PIN_NO(12) | 2)</div><div class='del'>-#define PINMUX_GPIO12__FUNC_SDA6 (MTK_PIN_NO(12) | 3)</div><div class='del'>-#define PINMUX_GPIO12__FUNC_URTS1 (MTK_PIN_NO(12) | 4)</div><div class='del'>-#define PINMUX_GPIO12__FUNC_URTS0 (MTK_PIN_NO(12) | 5)</div><div class='del'>-#define PINMUX_GPIO12__FUNC_I2S2_DI2 (MTK_PIN_NO(12) | 6)</div><div class='del'>-#define PINMUX_GPIO12__FUNC_I2S5_BCK (MTK_PIN_NO(12) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)</div><div class='del'>-#define PINMUX_GPIO13__FUNC_DBPI_D0 (MTK_PIN_NO(13) | 1)</div><div class='del'>-#define PINMUX_GPIO13__FUNC_SPI5_MI (MTK_PIN_NO(13) | 2)</div><div class='del'>-#define PINMUX_GPIO13__FUNC_PCM0_SYNC (MTK_PIN_NO(13) | 3)</div><div class='del'>-#define PINMUX_GPIO13__FUNC_MD_URXD0 (MTK_PIN_NO(13) | 4)</div><div class='del'>-#define PINMUX_GPIO13__FUNC_ANT_SEL3 (MTK_PIN_NO(13) | 5)</div><div class='del'>-#define PINMUX_GPIO13__FUNC_I2S0_MCK (MTK_PIN_NO(13) | 6)</div><div class='del'>-#define PINMUX_GPIO13__FUNC_DBG_MON_B15 (MTK_PIN_NO(13) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)</div><div class='del'>-#define PINMUX_GPIO14__FUNC_DBPI_D1 (MTK_PIN_NO(14) | 1)</div><div class='del'>-#define PINMUX_GPIO14__FUNC_SPI5_CSB (MTK_PIN_NO(14) | 2)</div><div class='del'>-#define PINMUX_GPIO14__FUNC_PCM0_CLK (MTK_PIN_NO(14) | 3)</div><div class='del'>-#define PINMUX_GPIO14__FUNC_MD_UTXD0 (MTK_PIN_NO(14) | 4)</div><div class='del'>-#define PINMUX_GPIO14__FUNC_ANT_SEL4 (MTK_PIN_NO(14) | 5)</div><div class='del'>-#define PINMUX_GPIO14__FUNC_I2S0_BCK (MTK_PIN_NO(14) | 6)</div><div class='del'>-#define PINMUX_GPIO14__FUNC_DBG_MON_B16 (MTK_PIN_NO(14) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)</div><div class='del'>-#define PINMUX_GPIO15__FUNC_DBPI_D2 (MTK_PIN_NO(15) | 1)</div><div class='del'>-#define PINMUX_GPIO15__FUNC_SPI5_MO (MTK_PIN_NO(15) | 2)</div><div class='del'>-#define PINMUX_GPIO15__FUNC_PCM0_DO (MTK_PIN_NO(15) | 3)</div><div class='del'>-#define PINMUX_GPIO15__FUNC_MD_URXD1 (MTK_PIN_NO(15) | 4)</div><div class='del'>-#define PINMUX_GPIO15__FUNC_ANT_SEL5 (MTK_PIN_NO(15) | 5)</div><div class='del'>-#define PINMUX_GPIO15__FUNC_I2S0_LRCK (MTK_PIN_NO(15) | 6)</div><div class='del'>-#define PINMUX_GPIO15__FUNC_DBG_MON_B17 (MTK_PIN_NO(15) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0)</div><div class='del'>-#define PINMUX_GPIO16__FUNC_DBPI_D3 (MTK_PIN_NO(16) | 1)</div><div class='del'>-#define PINMUX_GPIO16__FUNC_SPI5_CLK (MTK_PIN_NO(16) | 2)</div><div class='del'>-#define PINMUX_GPIO16__FUNC_PCM0_DI (MTK_PIN_NO(16) | 3)</div><div class='del'>-#define PINMUX_GPIO16__FUNC_MD_UTXD1 (MTK_PIN_NO(16) | 4)</div><div class='del'>-#define PINMUX_GPIO16__FUNC_ANT_SEL6 (MTK_PIN_NO(16) | 5)</div><div class='del'>-#define PINMUX_GPIO16__FUNC_I2S0_DI (MTK_PIN_NO(16) | 6)</div><div class='del'>-#define PINMUX_GPIO16__FUNC_DBG_MON_B23 (MTK_PIN_NO(16) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0)</div><div class='del'>-#define PINMUX_GPIO17__FUNC_DBPI_D4 (MTK_PIN_NO(17) | 1)</div><div class='del'>-#define PINMUX_GPIO17__FUNC_SPI4_MI (MTK_PIN_NO(17) | 2)</div><div class='del'>-#define PINMUX_GPIO17__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(17) | 3)</div><div class='del'>-#define PINMUX_GPIO17__FUNC_MD_INT0 (MTK_PIN_NO(17) | 4)</div><div class='del'>-#define PINMUX_GPIO17__FUNC_ANT_SEL7 (MTK_PIN_NO(17) | 5)</div><div class='del'>-#define PINMUX_GPIO17__FUNC_I2S3_MCK (MTK_PIN_NO(17) | 6)</div><div class='del'>-#define PINMUX_GPIO17__FUNC_DBG_MON_A1 (MTK_PIN_NO(17) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)</div><div class='del'>-#define PINMUX_GPIO18__FUNC_DBPI_D5 (MTK_PIN_NO(18) | 1)</div><div class='del'>-#define PINMUX_GPIO18__FUNC_SPI4_CSB (MTK_PIN_NO(18) | 2)</div><div class='del'>-#define PINMUX_GPIO18__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(18) | 3)</div><div class='del'>-#define PINMUX_GPIO18__FUNC_MD_INT0 (MTK_PIN_NO(18) | 4)</div><div class='del'>-#define PINMUX_GPIO18__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(18) | 5)</div><div class='del'>-#define PINMUX_GPIO18__FUNC_I2S3_BCK (MTK_PIN_NO(18) | 6)</div><div class='del'>-#define PINMUX_GPIO18__FUNC_DBG_MON_A2 (MTK_PIN_NO(18) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)</div><div class='del'>-#define PINMUX_GPIO19__FUNC_DBPI_D6 (MTK_PIN_NO(19) | 1)</div><div class='del'>-#define PINMUX_GPIO19__FUNC_SPI4_MO (MTK_PIN_NO(19) | 2)</div><div class='del'>-#define PINMUX_GPIO19__FUNC_CONN_MCU_TDO (MTK_PIN_NO(19) | 3)</div><div class='del'>-#define PINMUX_GPIO19__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(19) | 4)</div><div class='del'>-#define PINMUX_GPIO19__FUNC_URXD1 (MTK_PIN_NO(19) | 5)</div><div class='del'>-#define PINMUX_GPIO19__FUNC_I2S3_LRCK (MTK_PIN_NO(19) | 6)</div><div class='del'>-#define PINMUX_GPIO19__FUNC_DBG_MON_A3 (MTK_PIN_NO(19) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)</div><div class='del'>-#define PINMUX_GPIO20__FUNC_DBPI_D7 (MTK_PIN_NO(20) | 1)</div><div class='del'>-#define PINMUX_GPIO20__FUNC_SPI4_CLK (MTK_PIN_NO(20) | 2)</div><div class='del'>-#define PINMUX_GPIO20__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(20) | 3)</div><div class='del'>-#define PINMUX_GPIO20__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(20) | 4)</div><div class='del'>-#define PINMUX_GPIO20__FUNC_UTXD1 (MTK_PIN_NO(20) | 5)</div><div class='del'>-#define PINMUX_GPIO20__FUNC_I2S3_DO (MTK_PIN_NO(20) | 6)</div><div class='del'>-#define PINMUX_GPIO20__FUNC_DBG_MON_A19 (MTK_PIN_NO(20) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)</div><div class='del'>-#define PINMUX_GPIO21__FUNC_DBPI_D8 (MTK_PIN_NO(21) | 1)</div><div class='del'>-#define PINMUX_GPIO21__FUNC_SPI3_MI (MTK_PIN_NO(21) | 2)</div><div class='del'>-#define PINMUX_GPIO21__FUNC_CONN_MCU_TMS (MTK_PIN_NO(21) | 3)</div><div class='del'>-#define PINMUX_GPIO21__FUNC_DAP_MD32_SWD (MTK_PIN_NO(21) | 4)</div><div class='del'>-#define PINMUX_GPIO21__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(21) | 5)</div><div class='del'>-#define PINMUX_GPIO21__FUNC_I2S2_MCK (MTK_PIN_NO(21) | 6)</div><div class='del'>-#define PINMUX_GPIO21__FUNC_DBG_MON_B5 (MTK_PIN_NO(21) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)</div><div class='del'>-#define PINMUX_GPIO22__FUNC_DBPI_D9 (MTK_PIN_NO(22) | 1)</div><div class='del'>-#define PINMUX_GPIO22__FUNC_SPI3_CSB (MTK_PIN_NO(22) | 2)</div><div class='del'>-#define PINMUX_GPIO22__FUNC_CONN_MCU_TCK (MTK_PIN_NO(22) | 3)</div><div class='del'>-#define PINMUX_GPIO22__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(22) | 4)</div><div class='del'>-#define PINMUX_GPIO22__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(22) | 5)</div><div class='del'>-#define PINMUX_GPIO22__FUNC_I2S2_BCK (MTK_PIN_NO(22) | 6)</div><div class='del'>-#define PINMUX_GPIO22__FUNC_DBG_MON_B6 (MTK_PIN_NO(22) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)</div><div class='del'>-#define PINMUX_GPIO23__FUNC_DBPI_D10 (MTK_PIN_NO(23) | 1)</div><div class='del'>-#define PINMUX_GPIO23__FUNC_SPI3_MO (MTK_PIN_NO(23) | 2)</div><div class='del'>-#define PINMUX_GPIO23__FUNC_CONN_MCU_TDI (MTK_PIN_NO(23) | 3)</div><div class='del'>-#define PINMUX_GPIO23__FUNC_UCTS1 (MTK_PIN_NO(23) | 4)</div><div class='del'>-#define PINMUX_GPIO23__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(23) | 5)</div><div class='del'>-#define PINMUX_GPIO23__FUNC_I2S2_LRCK (MTK_PIN_NO(23) | 6)</div><div class='del'>-#define PINMUX_GPIO23__FUNC_DBG_MON_B7 (MTK_PIN_NO(23) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)</div><div class='del'>-#define PINMUX_GPIO24__FUNC_DBPI_D11 (MTK_PIN_NO(24) | 1)</div><div class='del'>-#define PINMUX_GPIO24__FUNC_SPI3_CLK (MTK_PIN_NO(24) | 2)</div><div class='del'>-#define PINMUX_GPIO24__FUNC_SRCLKENAI0 (MTK_PIN_NO(24) | 3)</div><div class='del'>-#define PINMUX_GPIO24__FUNC_URTS1 (MTK_PIN_NO(24) | 4)</div><div class='del'>-#define PINMUX_GPIO24__FUNC_IO_JTAG_TCK (MTK_PIN_NO(24) | 5)</div><div class='del'>-#define PINMUX_GPIO24__FUNC_I2S2_DI (MTK_PIN_NO(24) | 6)</div><div class='del'>-#define PINMUX_GPIO24__FUNC_DBG_MON_B31 (MTK_PIN_NO(24) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)</div><div class='del'>-#define PINMUX_GPIO25__FUNC_DBPI_HSYNC (MTK_PIN_NO(25) | 1)</div><div class='del'>-#define PINMUX_GPIO25__FUNC_ANT_SEL0 (MTK_PIN_NO(25) | 2)</div><div class='del'>-#define PINMUX_GPIO25__FUNC_SCL6 (MTK_PIN_NO(25) | 3)</div><div class='del'>-#define PINMUX_GPIO25__FUNC_KPCOL2 (MTK_PIN_NO(25) | 4)</div><div class='del'>-#define PINMUX_GPIO25__FUNC_IO_JTAG_TMS (MTK_PIN_NO(25) | 5)</div><div class='del'>-#define PINMUX_GPIO25__FUNC_I2S1_MCK (MTK_PIN_NO(25) | 6)</div><div class='del'>-#define PINMUX_GPIO25__FUNC_DBG_MON_B0 (MTK_PIN_NO(25) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)</div><div class='del'>-#define PINMUX_GPIO26__FUNC_DBPI_VSYNC (MTK_PIN_NO(26) | 1)</div><div class='del'>-#define PINMUX_GPIO26__FUNC_ANT_SEL1 (MTK_PIN_NO(26) | 2)</div><div class='del'>-#define PINMUX_GPIO26__FUNC_SDA6 (MTK_PIN_NO(26) | 3)</div><div class='del'>-#define PINMUX_GPIO26__FUNC_KPROW2 (MTK_PIN_NO(26) | 4)</div><div class='del'>-#define PINMUX_GPIO26__FUNC_IO_JTAG_TDI (MTK_PIN_NO(26) | 5)</div><div class='del'>-#define PINMUX_GPIO26__FUNC_I2S1_BCK (MTK_PIN_NO(26) | 6)</div><div class='del'>-#define PINMUX_GPIO26__FUNC_DBG_MON_B1 (MTK_PIN_NO(26) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)</div><div class='del'>-#define PINMUX_GPIO27__FUNC_DBPI_DE (MTK_PIN_NO(27) | 1)</div><div class='del'>-#define PINMUX_GPIO27__FUNC_ANT_SEL2 (MTK_PIN_NO(27) | 2)</div><div class='del'>-#define PINMUX_GPIO27__FUNC_SCL7 (MTK_PIN_NO(27) | 3)</div><div class='del'>-#define PINMUX_GPIO27__FUNC_DMIC_CLK (MTK_PIN_NO(27) | 4)</div><div class='del'>-#define PINMUX_GPIO27__FUNC_IO_JTAG_TDO (MTK_PIN_NO(27) | 5)</div><div class='del'>-#define PINMUX_GPIO27__FUNC_I2S1_LRCK (MTK_PIN_NO(27) | 6)</div><div class='del'>-#define PINMUX_GPIO27__FUNC_DBG_MON_B9 (MTK_PIN_NO(27) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)</div><div class='del'>-#define PINMUX_GPIO28__FUNC_DBPI_CK (MTK_PIN_NO(28) | 1)</div><div class='del'>-#define PINMUX_GPIO28__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(28) | 2)</div><div class='del'>-#define PINMUX_GPIO28__FUNC_SDA7 (MTK_PIN_NO(28) | 3)</div><div class='del'>-#define PINMUX_GPIO28__FUNC_DMIC_DAT (MTK_PIN_NO(28) | 4)</div><div class='del'>-#define PINMUX_GPIO28__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(28) | 5)</div><div class='del'>-#define PINMUX_GPIO28__FUNC_I2S1_DO (MTK_PIN_NO(28) | 6)</div><div class='del'>-#define PINMUX_GPIO28__FUNC_DBG_MON_B32 (MTK_PIN_NO(28) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)</div><div class='del'>-#define PINMUX_GPIO29__FUNC_MSDC1_CLK (MTK_PIN_NO(29) | 1)</div><div class='del'>-#define PINMUX_GPIO29__FUNC_IO_JTAG_TCK (MTK_PIN_NO(29) | 2)</div><div class='del'>-#define PINMUX_GPIO29__FUNC_UDI_TCK (MTK_PIN_NO(29) | 3)</div><div class='del'>-#define PINMUX_GPIO29__FUNC_CONN_DSP_JCK (MTK_PIN_NO(29) | 4)</div><div class='del'>-#define PINMUX_GPIO29__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(29) | 5)</div><div class='del'>-#define PINMUX_GPIO29__FUNC_PCM1_CLK (MTK_PIN_NO(29) | 6)</div><div class='del'>-#define PINMUX_GPIO29__FUNC_DBG_MON_A6 (MTK_PIN_NO(29) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0)</div><div class='del'>-#define PINMUX_GPIO30__FUNC_MSDC1_DAT3 (MTK_PIN_NO(30) | 1)</div><div class='del'>-#define PINMUX_GPIO30__FUNC_DAP_MD32_SWD (MTK_PIN_NO(30) | 2)</div><div class='del'>-#define PINMUX_GPIO30__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(30) | 3)</div><div class='del'>-#define PINMUX_GPIO30__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(30) | 4)</div><div class='del'>-#define PINMUX_GPIO30__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(30) | 5)</div><div class='del'>-#define PINMUX_GPIO30__FUNC_PCM1_DI (MTK_PIN_NO(30) | 6)</div><div class='del'>-#define PINMUX_GPIO30__FUNC_DBG_MON_A7 (MTK_PIN_NO(30) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0)</div><div class='del'>-#define PINMUX_GPIO31__FUNC_MSDC1_CMD (MTK_PIN_NO(31) | 1)</div><div class='del'>-#define PINMUX_GPIO31__FUNC_IO_JTAG_TMS (MTK_PIN_NO(31) | 2)</div><div class='del'>-#define PINMUX_GPIO31__FUNC_UDI_TMS (MTK_PIN_NO(31) | 3)</div><div class='del'>-#define PINMUX_GPIO31__FUNC_CONN_DSP_JMS (MTK_PIN_NO(31) | 4)</div><div class='del'>-#define PINMUX_GPIO31__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(31) | 5)</div><div class='del'>-#define PINMUX_GPIO31__FUNC_PCM1_SYNC (MTK_PIN_NO(31) | 6)</div><div class='del'>-#define PINMUX_GPIO31__FUNC_DBG_MON_A8 (MTK_PIN_NO(31) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0)</div><div class='del'>-#define PINMUX_GPIO32__FUNC_MSDC1_DAT0 (MTK_PIN_NO(32) | 1)</div><div class='del'>-#define PINMUX_GPIO32__FUNC_IO_JTAG_TDI (MTK_PIN_NO(32) | 2)</div><div class='del'>-#define PINMUX_GPIO32__FUNC_UDI_TDI (MTK_PIN_NO(32) | 3)</div><div class='del'>-#define PINMUX_GPIO32__FUNC_CONN_DSP_JDI (MTK_PIN_NO(32) | 4)</div><div class='del'>-#define PINMUX_GPIO32__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(32) | 5)</div><div class='del'>-#define PINMUX_GPIO32__FUNC_PCM1_DO0 (MTK_PIN_NO(32) | 6)</div><div class='del'>-#define PINMUX_GPIO32__FUNC_DBG_MON_A9 (MTK_PIN_NO(32) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)</div><div class='del'>-#define PINMUX_GPIO33__FUNC_MSDC1_DAT2 (MTK_PIN_NO(33) | 1)</div><div class='del'>-#define PINMUX_GPIO33__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(33) | 2)</div><div class='del'>-#define PINMUX_GPIO33__FUNC_UDI_NTRST (MTK_PIN_NO(33) | 3)</div><div class='del'>-#define PINMUX_GPIO33__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(33) | 4)</div><div class='del'>-#define PINMUX_GPIO33__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(33) | 5)</div><div class='del'>-#define PINMUX_GPIO33__FUNC_PCM1_DO2 (MTK_PIN_NO(33) | 6)</div><div class='del'>-#define PINMUX_GPIO33__FUNC_DBG_MON_A10 (MTK_PIN_NO(33) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)</div><div class='del'>-#define PINMUX_GPIO34__FUNC_MSDC1_DAT1 (MTK_PIN_NO(34) | 1)</div><div class='del'>-#define PINMUX_GPIO34__FUNC_IO_JTAG_TDO (MTK_PIN_NO(34) | 2)</div><div class='del'>-#define PINMUX_GPIO34__FUNC_UDI_TDO (MTK_PIN_NO(34) | 3)</div><div class='del'>-#define PINMUX_GPIO34__FUNC_CONN_DSP_JDO (MTK_PIN_NO(34) | 4)</div><div class='del'>-#define PINMUX_GPIO34__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(34) | 5)</div><div class='del'>-#define PINMUX_GPIO34__FUNC_PCM1_DO1 (MTK_PIN_NO(34) | 6)</div><div class='del'>-#define PINMUX_GPIO34__FUNC_DBG_MON_A11 (MTK_PIN_NO(34) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)</div><div class='del'>-#define PINMUX_GPIO35__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(35) | 1)</div><div class='del'>-#define PINMUX_GPIO35__FUNC_CCU_JTAG_TDO (MTK_PIN_NO(35) | 2)</div><div class='del'>-#define PINMUX_GPIO35__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(35) | 3)</div><div class='del'>-#define PINMUX_GPIO35__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(35) | 5)</div><div class='del'>-#define PINMUX_GPIO35__FUNC_CONN_DSP_JMS (MTK_PIN_NO(35) | 6)</div><div class='del'>-#define PINMUX_GPIO35__FUNC_DBG_MON_A28 (MTK_PIN_NO(35) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)</div><div class='del'>-#define PINMUX_GPIO36__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(36) | 1)</div><div class='del'>-#define PINMUX_GPIO36__FUNC_CCU_JTAG_TMS (MTK_PIN_NO(36) | 2)</div><div class='del'>-#define PINMUX_GPIO36__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(36) | 3)</div><div class='del'>-#define PINMUX_GPIO36__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(36) | 4)</div><div class='del'>-#define PINMUX_GPIO36__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(36) | 5)</div><div class='del'>-#define PINMUX_GPIO36__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(36) | 6)</div><div class='del'>-#define PINMUX_GPIO36__FUNC_DBG_MON_A29 (MTK_PIN_NO(36) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)</div><div class='del'>-#define PINMUX_GPIO37__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(37) | 1)</div><div class='del'>-#define PINMUX_GPIO37__FUNC_CCU_JTAG_TDI (MTK_PIN_NO(37) | 2)</div><div class='del'>-#define PINMUX_GPIO37__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(37) | 3)</div><div class='del'>-#define PINMUX_GPIO37__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(37) | 5)</div><div class='del'>-#define PINMUX_GPIO37__FUNC_CONN_DSP_JDO (MTK_PIN_NO(37) | 6)</div><div class='del'>-#define PINMUX_GPIO37__FUNC_DBG_MON_A30 (MTK_PIN_NO(37) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0)</div><div class='del'>-#define PINMUX_GPIO38__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(38) | 1)</div><div class='del'>-#define PINMUX_GPIO38__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(38) | 3)</div><div class='del'>-#define PINMUX_GPIO38__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(38) | 4)</div><div class='del'>-#define PINMUX_GPIO38__FUNC_DBG_MON_A20 (MTK_PIN_NO(38) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)</div><div class='del'>-#define PINMUX_GPIO39__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(39) | 1)</div><div class='del'>-#define PINMUX_GPIO39__FUNC_CCU_JTAG_TCK (MTK_PIN_NO(39) | 2)</div><div class='del'>-#define PINMUX_GPIO39__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(39) | 3)</div><div class='del'>-#define PINMUX_GPIO39__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(39) | 5)</div><div class='del'>-#define PINMUX_GPIO39__FUNC_CONN_DSP_JCK (MTK_PIN_NO(39) | 6)</div><div class='del'>-#define PINMUX_GPIO39__FUNC_DBG_MON_A31 (MTK_PIN_NO(39) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)</div><div class='del'>-#define PINMUX_GPIO40__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(40) | 1)</div><div class='del'>-#define PINMUX_GPIO40__FUNC_CCU_JTAG_TRST (MTK_PIN_NO(40) | 2)</div><div class='del'>-#define PINMUX_GPIO40__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(40) | 3)</div><div class='del'>-#define PINMUX_GPIO40__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(40) | 5)</div><div class='del'>-#define PINMUX_GPIO40__FUNC_CONN_DSP_JDI (MTK_PIN_NO(40) | 6)</div><div class='del'>-#define PINMUX_GPIO40__FUNC_DBG_MON_A32 (MTK_PIN_NO(40) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0)</div><div class='del'>-#define PINMUX_GPIO41__FUNC_IDDIG (MTK_PIN_NO(41) | 1)</div><div class='del'>-#define PINMUX_GPIO41__FUNC_URXD1 (MTK_PIN_NO(41) | 2)</div><div class='del'>-#define PINMUX_GPIO41__FUNC_UCTS0 (MTK_PIN_NO(41) | 3)</div><div class='del'>-#define PINMUX_GPIO41__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(41) | 4)</div><div class='del'>-#define PINMUX_GPIO41__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(41) | 5)</div><div class='del'>-#define PINMUX_GPIO41__FUNC_DMIC_CLK (MTK_PIN_NO(41) | 6)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0)</div><div class='del'>-#define PINMUX_GPIO42__FUNC_USB_DRVVBUS (MTK_PIN_NO(42) | 1)</div><div class='del'>-#define PINMUX_GPIO42__FUNC_UTXD1 (MTK_PIN_NO(42) | 2)</div><div class='del'>-#define PINMUX_GPIO42__FUNC_URTS0 (MTK_PIN_NO(42) | 3)</div><div class='del'>-#define PINMUX_GPIO42__FUNC_SSPM_URXD_AO (MTK_PIN_NO(42) | 4)</div><div class='del'>-#define PINMUX_GPIO42__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(42) | 5)</div><div class='del'>-#define PINMUX_GPIO42__FUNC_DMIC_DAT (MTK_PIN_NO(42) | 6)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0)</div><div class='del'>-#define PINMUX_GPIO43__FUNC_DISP_PWM (MTK_PIN_NO(43) | 1)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0)</div><div class='del'>-#define PINMUX_GPIO44__FUNC_DSI_TE (MTK_PIN_NO(44) | 1)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0)</div><div class='del'>-#define PINMUX_GPIO45__FUNC_LCM_RST (MTK_PIN_NO(45) | 1)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0)</div><div class='del'>-#define PINMUX_GPIO46__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(46) | 1)</div><div class='del'>-#define PINMUX_GPIO46__FUNC_URXD1 (MTK_PIN_NO(46) | 2)</div><div class='del'>-#define PINMUX_GPIO46__FUNC_UCTS1 (MTK_PIN_NO(46) | 3)</div><div class='del'>-#define PINMUX_GPIO46__FUNC_CCU_UTXD_AO (MTK_PIN_NO(46) | 4)</div><div class='del'>-#define PINMUX_GPIO46__FUNC_TP_UCTS1_AO (MTK_PIN_NO(46) | 5)</div><div class='del'>-#define PINMUX_GPIO46__FUNC_IDDIG (MTK_PIN_NO(46) | 6)</div><div class='del'>-#define PINMUX_GPIO46__FUNC_I2S5_LRCK (MTK_PIN_NO(46) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0)</div><div class='del'>-#define PINMUX_GPIO47__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(47) | 1)</div><div class='del'>-#define PINMUX_GPIO47__FUNC_UTXD1 (MTK_PIN_NO(47) | 2)</div><div class='del'>-#define PINMUX_GPIO47__FUNC_URTS1 (MTK_PIN_NO(47) | 3)</div><div class='del'>-#define PINMUX_GPIO47__FUNC_CCU_URXD_AO (MTK_PIN_NO(47) | 4)</div><div class='del'>-#define PINMUX_GPIO47__FUNC_TP_URTS1_AO (MTK_PIN_NO(47) | 5)</div><div class='del'>-#define PINMUX_GPIO47__FUNC_USB_DRVVBUS (MTK_PIN_NO(47) | 6)</div><div class='del'>-#define PINMUX_GPIO47__FUNC_I2S5_DO (MTK_PIN_NO(47) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0)</div><div class='del'>-#define PINMUX_GPIO48__FUNC_SCL5 (MTK_PIN_NO(48) | 1)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0)</div><div class='del'>-#define PINMUX_GPIO49__FUNC_SDA5 (MTK_PIN_NO(49) | 1)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0)</div><div class='del'>-#define PINMUX_GPIO50__FUNC_SCL3 (MTK_PIN_NO(50) | 1)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0)</div><div class='del'>-#define PINMUX_GPIO51__FUNC_SDA3 (MTK_PIN_NO(51) | 1)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0)</div><div class='del'>-#define PINMUX_GPIO52__FUNC_BPI_ANT2 (MTK_PIN_NO(52) | 1)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0)</div><div class='del'>-#define PINMUX_GPIO53__FUNC_BPI_ANT0 (MTK_PIN_NO(53) | 1)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0)</div><div class='del'>-#define PINMUX_GPIO54__FUNC_BPI_OLAT1 (MTK_PIN_NO(54) | 1)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0)</div><div class='del'>-#define PINMUX_GPIO55__FUNC_BPI_BUS8 (MTK_PIN_NO(55) | 1)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0)</div><div class='del'>-#define PINMUX_GPIO56__FUNC_BPI_BUS9 (MTK_PIN_NO(56) | 1)</div><div class='del'>-#define PINMUX_GPIO56__FUNC_SCL_6306 (MTK_PIN_NO(56) | 2)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0)</div><div class='del'>-#define PINMUX_GPIO57__FUNC_BPI_BUS10 (MTK_PIN_NO(57) | 1)</div><div class='del'>-#define PINMUX_GPIO57__FUNC_SDA_6306 (MTK_PIN_NO(57) | 2)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0)</div><div class='del'>-#define PINMUX_GPIO58__FUNC_RFIC0_BSI_D2 (MTK_PIN_NO(58) | 1)</div><div class='del'>-#define PINMUX_GPIO58__FUNC_SPM_BSI_D2 (MTK_PIN_NO(58) | 2)</div><div class='del'>-#define PINMUX_GPIO58__FUNC_PWM_B (MTK_PIN_NO(58) | 3)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0)</div><div class='del'>-#define PINMUX_GPIO59__FUNC_RFIC0_BSI_D1 (MTK_PIN_NO(59) | 1)</div><div class='del'>-#define PINMUX_GPIO59__FUNC_SPM_BSI_D1 (MTK_PIN_NO(59) | 2)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0)</div><div class='del'>-#define PINMUX_GPIO60__FUNC_RFIC0_BSI_D0 (MTK_PIN_NO(60) | 1)</div><div class='del'>-#define PINMUX_GPIO60__FUNC_SPM_BSI_D0 (MTK_PIN_NO(60) | 2)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0)</div><div class='del'>-#define PINMUX_GPIO61__FUNC_MIPI1_SDATA (MTK_PIN_NO(61) | 1)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0)</div><div class='del'>-#define PINMUX_GPIO62__FUNC_MIPI1_SCLK (MTK_PIN_NO(62) | 1)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0)</div><div class='del'>-#define PINMUX_GPIO63__FUNC_MIPI0_SDATA (MTK_PIN_NO(63) | 1)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0)</div><div class='del'>-#define PINMUX_GPIO64__FUNC_MIPI0_SCLK (MTK_PIN_NO(64) | 1)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0)</div><div class='del'>-#define PINMUX_GPIO65__FUNC_MIPI3_SDATA (MTK_PIN_NO(65) | 1)</div><div class='del'>-#define PINMUX_GPIO65__FUNC_BPI_OLAT2 (MTK_PIN_NO(65) | 2)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0)</div><div class='del'>-#define PINMUX_GPIO66__FUNC_MIPI3_SCLK (MTK_PIN_NO(66) | 1)</div><div class='del'>-#define PINMUX_GPIO66__FUNC_BPI_OLAT3 (MTK_PIN_NO(66) | 2)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0)</div><div class='del'>-#define PINMUX_GPIO67__FUNC_MIPI2_SDATA (MTK_PIN_NO(67) | 1)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0)</div><div class='del'>-#define PINMUX_GPIO68__FUNC_MIPI2_SCLK (MTK_PIN_NO(68) | 1)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0)</div><div class='del'>-#define PINMUX_GPIO69__FUNC_BPI_BUS7 (MTK_PIN_NO(69) | 1)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0)</div><div class='del'>-#define PINMUX_GPIO70__FUNC_BPI_BUS6 (MTK_PIN_NO(70) | 1)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0)</div><div class='del'>-#define PINMUX_GPIO71__FUNC_BPI_BUS5 (MTK_PIN_NO(71) | 1)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0)</div><div class='del'>-#define PINMUX_GPIO72__FUNC_BPI_BUS4 (MTK_PIN_NO(72) | 1)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0)</div><div class='del'>-#define PINMUX_GPIO73__FUNC_BPI_BUS3 (MTK_PIN_NO(73) | 1)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0)</div><div class='del'>-#define PINMUX_GPIO74__FUNC_BPI_BUS2 (MTK_PIN_NO(74) | 1)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0)</div><div class='del'>-#define PINMUX_GPIO75__FUNC_BPI_BUS1 (MTK_PIN_NO(75) | 1)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0)</div><div class='del'>-#define PINMUX_GPIO76__FUNC_BPI_BUS0 (MTK_PIN_NO(76) | 1)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0)</div><div class='del'>-#define PINMUX_GPIO77__FUNC_BPI_ANT1 (MTK_PIN_NO(77) | 1)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0)</div><div class='del'>-#define PINMUX_GPIO78__FUNC_BPI_OLAT0 (MTK_PIN_NO(78) | 1)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0)</div><div class='del'>-#define PINMUX_GPIO79__FUNC_BPI_PA_VM1 (MTK_PIN_NO(79) | 1)</div><div class='del'>-#define PINMUX_GPIO79__FUNC_MIPI4_SDATA (MTK_PIN_NO(79) | 2)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0)</div><div class='del'>-#define PINMUX_GPIO80__FUNC_BPI_PA_VM0 (MTK_PIN_NO(80) | 1)</div><div class='del'>-#define PINMUX_GPIO80__FUNC_MIPI4_SCLK (MTK_PIN_NO(80) | 2)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0)</div><div class='del'>-#define PINMUX_GPIO81__FUNC_SDA1 (MTK_PIN_NO(81) | 1)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0)</div><div class='del'>-#define PINMUX_GPIO82__FUNC_SDA0 (MTK_PIN_NO(82) | 1)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0)</div><div class='del'>-#define PINMUX_GPIO83__FUNC_SCL0 (MTK_PIN_NO(83) | 1)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0)</div><div class='del'>-#define PINMUX_GPIO84__FUNC_SCL1 (MTK_PIN_NO(84) | 1)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0)</div><div class='del'>-#define PINMUX_GPIO85__FUNC_SPI0_MI (MTK_PIN_NO(85) | 1)</div><div class='del'>-#define PINMUX_GPIO85__FUNC_SCP_SPI0_MI (MTK_PIN_NO(85) | 2)</div><div class='del'>-#define PINMUX_GPIO85__FUNC_CLKM3 (MTK_PIN_NO(85) | 3)</div><div class='del'>-#define PINMUX_GPIO85__FUNC_I2S1_BCK (MTK_PIN_NO(85) | 4)</div><div class='del'>-#define PINMUX_GPIO85__FUNC_MFG_DFD_JTAG_TDO (MTK_PIN_NO(85) | 5)</div><div class='del'>-#define PINMUX_GPIO85__FUNC_DFD_TDO (MTK_PIN_NO(85) | 6)</div><div class='del'>-#define PINMUX_GPIO85__FUNC_JTDO_SEL1 (MTK_PIN_NO(85) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0)</div><div class='del'>-#define PINMUX_GPIO86__FUNC_SPI0_CSB (MTK_PIN_NO(86) | 1)</div><div class='del'>-#define PINMUX_GPIO86__FUNC_SCP_SPI0_CS (MTK_PIN_NO(86) | 2)</div><div class='del'>-#define PINMUX_GPIO86__FUNC_CLKM0 (MTK_PIN_NO(86) | 3)</div><div class='del'>-#define PINMUX_GPIO86__FUNC_I2S1_LRCK (MTK_PIN_NO(86) | 4)</div><div class='del'>-#define PINMUX_GPIO86__FUNC_MFG_DFD_JTAG_TMS (MTK_PIN_NO(86) | 5)</div><div class='del'>-#define PINMUX_GPIO86__FUNC_DFD_TMS (MTK_PIN_NO(86) | 6)</div><div class='del'>-#define PINMUX_GPIO86__FUNC_JTMS_SEL1 (MTK_PIN_NO(86) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0)</div><div class='del'>-#define PINMUX_GPIO87__FUNC_SPI0_MO (MTK_PIN_NO(87) | 1)</div><div class='del'>-#define PINMUX_GPIO87__FUNC_SCP_SPI0_MO (MTK_PIN_NO(87) | 2)</div><div class='del'>-#define PINMUX_GPIO87__FUNC_SDA1 (MTK_PIN_NO(87) | 3)</div><div class='del'>-#define PINMUX_GPIO87__FUNC_I2S1_DO (MTK_PIN_NO(87) | 4)</div><div class='del'>-#define PINMUX_GPIO87__FUNC_MFG_DFD_JTAG_TDI (MTK_PIN_NO(87) | 5)</div><div class='del'>-#define PINMUX_GPIO87__FUNC_DFD_TDI (MTK_PIN_NO(87) | 6)</div><div class='del'>-#define PINMUX_GPIO87__FUNC_JTDI_SEL1 (MTK_PIN_NO(87) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0)</div><div class='del'>-#define PINMUX_GPIO88__FUNC_SPI0_CLK (MTK_PIN_NO(88) | 1)</div><div class='del'>-#define PINMUX_GPIO88__FUNC_SCP_SPI0_CK (MTK_PIN_NO(88) | 2)</div><div class='del'>-#define PINMUX_GPIO88__FUNC_SCL1 (MTK_PIN_NO(88) | 3)</div><div class='del'>-#define PINMUX_GPIO88__FUNC_I2S1_MCK (MTK_PIN_NO(88) | 4)</div><div class='del'>-#define PINMUX_GPIO88__FUNC_MFG_DFD_JTAG_TCK (MTK_PIN_NO(88) | 5)</div><div class='del'>-#define PINMUX_GPIO88__FUNC_DFD_TCK_XI (MTK_PIN_NO(88) | 6)</div><div class='del'>-#define PINMUX_GPIO88__FUNC_JTCK_SEL1 (MTK_PIN_NO(88) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0)</div><div class='del'>-#define PINMUX_GPIO89__FUNC_SRCLKENAI0 (MTK_PIN_NO(89) | 1)</div><div class='del'>-#define PINMUX_GPIO89__FUNC_PWM_C (MTK_PIN_NO(89) | 2)</div><div class='del'>-#define PINMUX_GPIO89__FUNC_I2S5_BCK (MTK_PIN_NO(89) | 3)</div><div class='del'>-#define PINMUX_GPIO89__FUNC_ANT_SEL6 (MTK_PIN_NO(89) | 4)</div><div class='del'>-#define PINMUX_GPIO89__FUNC_SDA8 (MTK_PIN_NO(89) | 5)</div><div class='del'>-#define PINMUX_GPIO89__FUNC_CMVREF0 (MTK_PIN_NO(89) | 6)</div><div class='del'>-#define PINMUX_GPIO89__FUNC_DBG_MON_A21 (MTK_PIN_NO(89) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0)</div><div class='del'>-#define PINMUX_GPIO90__FUNC_PWM_A (MTK_PIN_NO(90) | 1)</div><div class='del'>-#define PINMUX_GPIO90__FUNC_CMMCLK2 (MTK_PIN_NO(90) | 2)</div><div class='del'>-#define PINMUX_GPIO90__FUNC_I2S5_LRCK (MTK_PIN_NO(90) | 3)</div><div class='del'>-#define PINMUX_GPIO90__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(90) | 4)</div><div class='del'>-#define PINMUX_GPIO90__FUNC_SCL8 (MTK_PIN_NO(90) | 5)</div><div class='del'>-#define PINMUX_GPIO90__FUNC_PTA_RXD (MTK_PIN_NO(90) | 6)</div><div class='del'>-#define PINMUX_GPIO90__FUNC_DBG_MON_A22 (MTK_PIN_NO(90) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0)</div><div class='del'>-#define PINMUX_GPIO91__FUNC_KPROW1 (MTK_PIN_NO(91) | 1)</div><div class='del'>-#define PINMUX_GPIO91__FUNC_PWM_B (MTK_PIN_NO(91) | 2)</div><div class='del'>-#define PINMUX_GPIO91__FUNC_I2S5_DO (MTK_PIN_NO(91) | 3)</div><div class='del'>-#define PINMUX_GPIO91__FUNC_ANT_SEL7 (MTK_PIN_NO(91) | 4)</div><div class='del'>-#define PINMUX_GPIO91__FUNC_CMMCLK3 (MTK_PIN_NO(91) | 5)</div><div class='del'>-#define PINMUX_GPIO91__FUNC_PTA_TXD (MTK_PIN_NO(91) | 6)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0)</div><div class='del'>-#define PINMUX_GPIO92__FUNC_KPROW0 (MTK_PIN_NO(92) | 1)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0)</div><div class='del'>-#define PINMUX_GPIO93__FUNC_KPCOL0 (MTK_PIN_NO(93) | 1)</div><div class='del'>-#define PINMUX_GPIO93__FUNC_DBG_MON_B27 (MTK_PIN_NO(93) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0)</div><div class='del'>-#define PINMUX_GPIO94__FUNC_KPCOL1 (MTK_PIN_NO(94) | 1)</div><div class='del'>-#define PINMUX_GPIO94__FUNC_I2S2_DI2 (MTK_PIN_NO(94) | 2)</div><div class='del'>-#define PINMUX_GPIO94__FUNC_I2S5_MCK (MTK_PIN_NO(94) | 3)</div><div class='del'>-#define PINMUX_GPIO94__FUNC_CMMCLK2 (MTK_PIN_NO(94) | 4)</div><div class='del'>-#define PINMUX_GPIO94__FUNC_SCP_SPI2_MI (MTK_PIN_NO(94) | 5)</div><div class='del'>-#define PINMUX_GPIO94__FUNC_SRCLKENAI1 (MTK_PIN_NO(94) | 6)</div><div class='del'>-#define PINMUX_GPIO94__FUNC_SPI2_MI (MTK_PIN_NO(94) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0)</div><div class='del'>-#define PINMUX_GPIO95__FUNC_URXD0 (MTK_PIN_NO(95) | 1)</div><div class='del'>-#define PINMUX_GPIO95__FUNC_UTXD0 (MTK_PIN_NO(95) | 2)</div><div class='del'>-#define PINMUX_GPIO95__FUNC_MD_URXD0 (MTK_PIN_NO(95) | 3)</div><div class='del'>-#define PINMUX_GPIO95__FUNC_MD_URXD1 (MTK_PIN_NO(95) | 4)</div><div class='del'>-#define PINMUX_GPIO95__FUNC_SSPM_URXD_AO (MTK_PIN_NO(95) | 5)</div><div class='del'>-#define PINMUX_GPIO95__FUNC_CCU_URXD_AO (MTK_PIN_NO(95) | 6)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0)</div><div class='del'>-#define PINMUX_GPIO96__FUNC_UTXD0 (MTK_PIN_NO(96) | 1)</div><div class='del'>-#define PINMUX_GPIO96__FUNC_URXD0 (MTK_PIN_NO(96) | 2)</div><div class='del'>-#define PINMUX_GPIO96__FUNC_MD_UTXD0 (MTK_PIN_NO(96) | 3)</div><div class='del'>-#define PINMUX_GPIO96__FUNC_MD_UTXD1 (MTK_PIN_NO(96) | 4)</div><div class='del'>-#define PINMUX_GPIO96__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(96) | 5)</div><div class='del'>-#define PINMUX_GPIO96__FUNC_CCU_UTXD_AO (MTK_PIN_NO(96) | 6)</div><div class='del'>-#define PINMUX_GPIO96__FUNC_DBG_MON_B2 (MTK_PIN_NO(96) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0)</div><div class='del'>-#define PINMUX_GPIO97__FUNC_UCTS0 (MTK_PIN_NO(97) | 1)</div><div class='del'>-#define PINMUX_GPIO97__FUNC_I2S2_MCK (MTK_PIN_NO(97) | 2)</div><div class='del'>-#define PINMUX_GPIO97__FUNC_IDDIG (MTK_PIN_NO(97) | 3)</div><div class='del'>-#define PINMUX_GPIO97__FUNC_CONN_MCU_TDO (MTK_PIN_NO(97) | 4)</div><div class='del'>-#define PINMUX_GPIO97__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(97) | 5)</div><div class='del'>-#define PINMUX_GPIO97__FUNC_IO_JTAG_TDO (MTK_PIN_NO(97) | 6)</div><div class='del'>-#define PINMUX_GPIO97__FUNC_DBG_MON_B3 (MTK_PIN_NO(97) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0)</div><div class='del'>-#define PINMUX_GPIO98__FUNC_URTS0 (MTK_PIN_NO(98) | 1)</div><div class='del'>-#define PINMUX_GPIO98__FUNC_I2S2_BCK (MTK_PIN_NO(98) | 2)</div><div class='del'>-#define PINMUX_GPIO98__FUNC_USB_DRVVBUS (MTK_PIN_NO(98) | 3)</div><div class='del'>-#define PINMUX_GPIO98__FUNC_CONN_MCU_TMS (MTK_PIN_NO(98) | 4)</div><div class='del'>-#define PINMUX_GPIO98__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(98) | 5)</div><div class='del'>-#define PINMUX_GPIO98__FUNC_IO_JTAG_TMS (MTK_PIN_NO(98) | 6)</div><div class='del'>-#define PINMUX_GPIO98__FUNC_DBG_MON_B4 (MTK_PIN_NO(98) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0)</div><div class='del'>-#define PINMUX_GPIO99__FUNC_CMMCLK0 (MTK_PIN_NO(99) | 1)</div><div class='del'>-#define PINMUX_GPIO99__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(99) | 4)</div><div class='del'>-#define PINMUX_GPIO99__FUNC_DBG_MON_B28 (MTK_PIN_NO(99) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0)</div><div class='del'>-#define PINMUX_GPIO100__FUNC_CMMCLK1 (MTK_PIN_NO(100) | 1)</div><div class='del'>-#define PINMUX_GPIO100__FUNC_PWM_C (MTK_PIN_NO(100) | 2)</div><div class='del'>-#define PINMUX_GPIO100__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(100) | 3)</div><div class='del'>-#define PINMUX_GPIO100__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(100) | 4)</div><div class='del'>-#define PINMUX_GPIO100__FUNC_DBG_MON_B29 (MTK_PIN_NO(100) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0)</div><div class='del'>-#define PINMUX_GPIO101__FUNC_CLKM2 (MTK_PIN_NO(101) | 1)</div><div class='del'>-#define PINMUX_GPIO101__FUNC_I2S2_LRCK (MTK_PIN_NO(101) | 2)</div><div class='del'>-#define PINMUX_GPIO101__FUNC_CMVREF1 (MTK_PIN_NO(101) | 3)</div><div class='del'>-#define PINMUX_GPIO101__FUNC_CONN_MCU_TCK (MTK_PIN_NO(101) | 4)</div><div class='del'>-#define PINMUX_GPIO101__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(101) | 5)</div><div class='del'>-#define PINMUX_GPIO101__FUNC_IO_JTAG_TCK (MTK_PIN_NO(101) | 6)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0)</div><div class='del'>-#define PINMUX_GPIO102__FUNC_CLKM1 (MTK_PIN_NO(102) | 1)</div><div class='del'>-#define PINMUX_GPIO102__FUNC_I2S2_DI (MTK_PIN_NO(102) | 2)</div><div class='del'>-#define PINMUX_GPIO102__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(102) | 3)</div><div class='del'>-#define PINMUX_GPIO102__FUNC_CONN_MCU_TDI (MTK_PIN_NO(102) | 4)</div><div class='del'>-#define PINMUX_GPIO102__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(102) | 5)</div><div class='del'>-#define PINMUX_GPIO102__FUNC_IO_JTAG_TDI (MTK_PIN_NO(102) | 6)</div><div class='del'>-#define PINMUX_GPIO102__FUNC_DBG_MON_B8 (MTK_PIN_NO(102) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0)</div><div class='del'>-#define PINMUX_GPIO103__FUNC_SCL2 (MTK_PIN_NO(103) | 1)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0)</div><div class='del'>-#define PINMUX_GPIO104__FUNC_SDA2 (MTK_PIN_NO(104) | 1)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0)</div><div class='del'>-#define PINMUX_GPIO105__FUNC_SCL4 (MTK_PIN_NO(105) | 1)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0)</div><div class='del'>-#define PINMUX_GPIO106__FUNC_SDA4 (MTK_PIN_NO(106) | 1)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0)</div><div class='del'>-#define PINMUX_GPIO107__FUNC_DMIC_CLK (MTK_PIN_NO(107) | 1)</div><div class='del'>-#define PINMUX_GPIO107__FUNC_ANT_SEL0 (MTK_PIN_NO(107) | 2)</div><div class='del'>-#define PINMUX_GPIO107__FUNC_CLKM0 (MTK_PIN_NO(107) | 3)</div><div class='del'>-#define PINMUX_GPIO107__FUNC_SDA7 (MTK_PIN_NO(107) | 4)</div><div class='del'>-#define PINMUX_GPIO107__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(107) | 5)</div><div class='del'>-#define PINMUX_GPIO107__FUNC_PWM_A (MTK_PIN_NO(107) | 6)</div><div class='del'>-#define PINMUX_GPIO107__FUNC_DBG_MON_B12 (MTK_PIN_NO(107) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0)</div><div class='del'>-#define PINMUX_GPIO108__FUNC_CMMCLK2 (MTK_PIN_NO(108) | 1)</div><div class='del'>-#define PINMUX_GPIO108__FUNC_ANT_SEL1 (MTK_PIN_NO(108) | 2)</div><div class='del'>-#define PINMUX_GPIO108__FUNC_CLKM1 (MTK_PIN_NO(108) | 3)</div><div class='del'>-#define PINMUX_GPIO108__FUNC_SCL8 (MTK_PIN_NO(108) | 4)</div><div class='del'>-#define PINMUX_GPIO108__FUNC_DAP_MD32_SWD (MTK_PIN_NO(108) | 5)</div><div class='del'>-#define PINMUX_GPIO108__FUNC_PWM_B (MTK_PIN_NO(108) | 6)</div><div class='del'>-#define PINMUX_GPIO108__FUNC_DBG_MON_B13 (MTK_PIN_NO(108) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0)</div><div class='del'>-#define PINMUX_GPIO109__FUNC_DMIC_DAT (MTK_PIN_NO(109) | 1)</div><div class='del'>-#define PINMUX_GPIO109__FUNC_ANT_SEL2 (MTK_PIN_NO(109) | 2)</div><div class='del'>-#define PINMUX_GPIO109__FUNC_CLKM2 (MTK_PIN_NO(109) | 3)</div><div class='del'>-#define PINMUX_GPIO109__FUNC_SDA8 (MTK_PIN_NO(109) | 4)</div><div class='del'>-#define PINMUX_GPIO109__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(109) | 5)</div><div class='del'>-#define PINMUX_GPIO109__FUNC_PWM_C (MTK_PIN_NO(109) | 6)</div><div class='del'>-#define PINMUX_GPIO109__FUNC_DBG_MON_B14 (MTK_PIN_NO(109) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0)</div><div class='del'>-#define PINMUX_GPIO110__FUNC_SCL7 (MTK_PIN_NO(110) | 1)</div><div class='del'>-#define PINMUX_GPIO110__FUNC_ANT_SEL0 (MTK_PIN_NO(110) | 2)</div><div class='del'>-#define PINMUX_GPIO110__FUNC_TP_URXD1_AO (MTK_PIN_NO(110) | 3)</div><div class='del'>-#define PINMUX_GPIO110__FUNC_USB_DRVVBUS (MTK_PIN_NO(110) | 4)</div><div class='del'>-#define PINMUX_GPIO110__FUNC_SRCLKENAI1 (MTK_PIN_NO(110) | 5)</div><div class='del'>-#define PINMUX_GPIO110__FUNC_KPCOL2 (MTK_PIN_NO(110) | 6)</div><div class='del'>-#define PINMUX_GPIO110__FUNC_URXD1 (MTK_PIN_NO(110) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0)</div><div class='del'>-#define PINMUX_GPIO111__FUNC_CMMCLK3 (MTK_PIN_NO(111) | 1)</div><div class='del'>-#define PINMUX_GPIO111__FUNC_ANT_SEL1 (MTK_PIN_NO(111) | 2)</div><div class='del'>-#define PINMUX_GPIO111__FUNC_SRCLKENAI0 (MTK_PIN_NO(111) | 3)</div><div class='del'>-#define PINMUX_GPIO111__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(111) | 4)</div><div class='del'>-#define PINMUX_GPIO111__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(111) | 5)</div><div class='del'>-#define PINMUX_GPIO111__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(111) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0)</div><div class='del'>-#define PINMUX_GPIO112__FUNC_SDA7 (MTK_PIN_NO(112) | 1)</div><div class='del'>-#define PINMUX_GPIO112__FUNC_ANT_SEL2 (MTK_PIN_NO(112) | 2)</div><div class='del'>-#define PINMUX_GPIO112__FUNC_TP_UTXD1_AO (MTK_PIN_NO(112) | 3)</div><div class='del'>-#define PINMUX_GPIO112__FUNC_IDDIG (MTK_PIN_NO(112) | 4)</div><div class='del'>-#define PINMUX_GPIO112__FUNC_AGPS_SYNC (MTK_PIN_NO(112) | 5)</div><div class='del'>-#define PINMUX_GPIO112__FUNC_KPROW2 (MTK_PIN_NO(112) | 6)</div><div class='del'>-#define PINMUX_GPIO112__FUNC_UTXD1 (MTK_PIN_NO(112) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0)</div><div class='del'>-#define PINMUX_GPIO113__FUNC_CONN_TOP_CLK (MTK_PIN_NO(113) | 1)</div><div class='del'>-#define PINMUX_GPIO113__FUNC_SCL6 (MTK_PIN_NO(113) | 3)</div><div class='del'>-#define PINMUX_GPIO113__FUNC_AUXIF_CLK0 (MTK_PIN_NO(113) | 4)</div><div class='del'>-#define PINMUX_GPIO113__FUNC_TP_UCTS1_AO (MTK_PIN_NO(113) | 6)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0)</div><div class='del'>-#define PINMUX_GPIO114__FUNC_CONN_TOP_DATA (MTK_PIN_NO(114) | 1)</div><div class='del'>-#define PINMUX_GPIO114__FUNC_SDA6 (MTK_PIN_NO(114) | 3)</div><div class='del'>-#define PINMUX_GPIO114__FUNC_AUXIF_ST0 (MTK_PIN_NO(114) | 4)</div><div class='del'>-#define PINMUX_GPIO114__FUNC_TP_URTS1_AO (MTK_PIN_NO(114) | 6)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0)</div><div class='del'>-#define PINMUX_GPIO115__FUNC_CONN_BT_CLK (MTK_PIN_NO(115) | 1)</div><div class='del'>-#define PINMUX_GPIO115__FUNC_UTXD1 (MTK_PIN_NO(115) | 2)</div><div class='del'>-#define PINMUX_GPIO115__FUNC_PTA_TXD (MTK_PIN_NO(115) | 3)</div><div class='del'>-#define PINMUX_GPIO115__FUNC_AUXIF_CLK1 (MTK_PIN_NO(115) | 4)</div><div class='del'>-#define PINMUX_GPIO115__FUNC_DAP_MD32_SWD (MTK_PIN_NO(115) | 5)</div><div class='del'>-#define PINMUX_GPIO115__FUNC_TP_UTXD1_AO (MTK_PIN_NO(115) | 6)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0)</div><div class='del'>-#define PINMUX_GPIO116__FUNC_CONN_BT_DATA (MTK_PIN_NO(116) | 1)</div><div class='del'>-#define PINMUX_GPIO116__FUNC_IPU_JTAG_TRST (MTK_PIN_NO(116) | 2)</div><div class='del'>-#define PINMUX_GPIO116__FUNC_AUXIF_ST1 (MTK_PIN_NO(116) | 4)</div><div class='del'>-#define PINMUX_GPIO116__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(116) | 5)</div><div class='del'>-#define PINMUX_GPIO116__FUNC_TP_URXD2_AO (MTK_PIN_NO(116) | 6)</div><div class='del'>-#define PINMUX_GPIO116__FUNC_DBG_MON_A0 (MTK_PIN_NO(116) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0)</div><div class='del'>-#define PINMUX_GPIO117__FUNC_CONN_WF_HB0 (MTK_PIN_NO(117) | 1)</div><div class='del'>-#define PINMUX_GPIO117__FUNC_IPU_JTAG_TDO (MTK_PIN_NO(117) | 2)</div><div class='del'>-#define PINMUX_GPIO117__FUNC_TP_UTXD2_AO (MTK_PIN_NO(117) | 6)</div><div class='del'>-#define PINMUX_GPIO117__FUNC_DBG_MON_A4 (MTK_PIN_NO(117) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0)</div><div class='del'>-#define PINMUX_GPIO118__FUNC_CONN_WF_HB1 (MTK_PIN_NO(118) | 1)</div><div class='del'>-#define PINMUX_GPIO118__FUNC_IPU_JTAG_TDI (MTK_PIN_NO(118) | 2)</div><div class='del'>-#define PINMUX_GPIO118__FUNC_SSPM_URXD_AO (MTK_PIN_NO(118) | 5)</div><div class='del'>-#define PINMUX_GPIO118__FUNC_TP_UCTS2_AO (MTK_PIN_NO(118) | 6)</div><div class='del'>-#define PINMUX_GPIO118__FUNC_DBG_MON_A5 (MTK_PIN_NO(118) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0)</div><div class='del'>-#define PINMUX_GPIO119__FUNC_CONN_WF_HB2 (MTK_PIN_NO(119) | 1)</div><div class='del'>-#define PINMUX_GPIO119__FUNC_IPU_JTAG_TCK (MTK_PIN_NO(119) | 2)</div><div class='del'>-#define PINMUX_GPIO119__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(119) | 5)</div><div class='del'>-#define PINMUX_GPIO119__FUNC_TP_URTS2_AO (MTK_PIN_NO(119) | 6)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0)</div><div class='del'>-#define PINMUX_GPIO120__FUNC_CONN_WB_PTA (MTK_PIN_NO(120) | 1)</div><div class='del'>-#define PINMUX_GPIO120__FUNC_IPU_JTAG_TMS (MTK_PIN_NO(120) | 2)</div><div class='del'>-#define PINMUX_GPIO120__FUNC_CCU_URXD_AO (MTK_PIN_NO(120) | 5)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0)</div><div class='del'>-#define PINMUX_GPIO121__FUNC_CONN_HRST_B (MTK_PIN_NO(121) | 1)</div><div class='del'>-#define PINMUX_GPIO121__FUNC_URXD1 (MTK_PIN_NO(121) | 2)</div><div class='del'>-#define PINMUX_GPIO121__FUNC_PTA_RXD (MTK_PIN_NO(121) | 3)</div><div class='del'>-#define PINMUX_GPIO121__FUNC_CCU_UTXD_AO (MTK_PIN_NO(121) | 5)</div><div class='del'>-#define PINMUX_GPIO121__FUNC_TP_URXD1_AO (MTK_PIN_NO(121) | 6)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0)</div><div class='del'>-#define PINMUX_GPIO122__FUNC_MSDC0_CMD (MTK_PIN_NO(122) | 1)</div><div class='del'>-#define PINMUX_GPIO122__FUNC_SSPM_URXD2_AO (MTK_PIN_NO(122) | 2)</div><div class='del'>-#define PINMUX_GPIO122__FUNC_ANT_SEL1 (MTK_PIN_NO(122) | 3)</div><div class='del'>-#define PINMUX_GPIO122__FUNC_DBG_MON_A12 (MTK_PIN_NO(122) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0)</div><div class='del'>-#define PINMUX_GPIO123__FUNC_MSDC0_DAT0 (MTK_PIN_NO(123) | 1)</div><div class='del'>-#define PINMUX_GPIO123__FUNC_ANT_SEL0 (MTK_PIN_NO(123) | 3)</div><div class='del'>-#define PINMUX_GPIO123__FUNC_DBG_MON_A13 (MTK_PIN_NO(123) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0)</div><div class='del'>-#define PINMUX_GPIO124__FUNC_MSDC0_CLK (MTK_PIN_NO(124) | 1)</div><div class='del'>-#define PINMUX_GPIO124__FUNC_DBG_MON_A14 (MTK_PIN_NO(124) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0)</div><div class='del'>-#define PINMUX_GPIO125__FUNC_MSDC0_DAT2 (MTK_PIN_NO(125) | 1)</div><div class='del'>-#define PINMUX_GPIO125__FUNC_MRG_CLK (MTK_PIN_NO(125) | 3)</div><div class='del'>-#define PINMUX_GPIO125__FUNC_DBG_MON_A15 (MTK_PIN_NO(125) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0)</div><div class='del'>-#define PINMUX_GPIO126__FUNC_MSDC0_DAT4 (MTK_PIN_NO(126) | 1)</div><div class='del'>-#define PINMUX_GPIO126__FUNC_ANT_SEL5 (MTK_PIN_NO(126) | 3)</div><div class='del'>-#define PINMUX_GPIO126__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(126) | 6)</div><div class='del'>-#define PINMUX_GPIO126__FUNC_DBG_MON_A16 (MTK_PIN_NO(126) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0)</div><div class='del'>-#define PINMUX_GPIO127__FUNC_MSDC0_DAT6 (MTK_PIN_NO(127) | 1)</div><div class='del'>-#define PINMUX_GPIO127__FUNC_ANT_SEL4 (MTK_PIN_NO(127) | 3)</div><div class='del'>-#define PINMUX_GPIO127__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(127) | 6)</div><div class='del'>-#define PINMUX_GPIO127__FUNC_DBG_MON_A17 (MTK_PIN_NO(127) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0)</div><div class='del'>-#define PINMUX_GPIO128__FUNC_MSDC0_DAT1 (MTK_PIN_NO(128) | 1)</div><div class='del'>-#define PINMUX_GPIO128__FUNC_ANT_SEL2 (MTK_PIN_NO(128) | 3)</div><div class='del'>-#define PINMUX_GPIO128__FUNC_UFS_UNIPRO_SDA (MTK_PIN_NO(128) | 6)</div><div class='del'>-#define PINMUX_GPIO128__FUNC_DBG_MON_A18 (MTK_PIN_NO(128) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0)</div><div class='del'>-#define PINMUX_GPIO129__FUNC_MSDC0_DAT5 (MTK_PIN_NO(129) | 1)</div><div class='del'>-#define PINMUX_GPIO129__FUNC_ANT_SEL3 (MTK_PIN_NO(129) | 3)</div><div class='del'>-#define PINMUX_GPIO129__FUNC_UFS_UNIPRO_SCL (MTK_PIN_NO(129) | 6)</div><div class='del'>-#define PINMUX_GPIO129__FUNC_DBG_MON_A23 (MTK_PIN_NO(129) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0)</div><div class='del'>-#define PINMUX_GPIO130__FUNC_MSDC0_DAT7 (MTK_PIN_NO(130) | 1)</div><div class='del'>-#define PINMUX_GPIO130__FUNC_MRG_DO (MTK_PIN_NO(130) | 3)</div><div class='del'>-#define PINMUX_GPIO130__FUNC_DBG_MON_A24 (MTK_PIN_NO(130) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0)</div><div class='del'>-#define PINMUX_GPIO131__FUNC_MSDC0_DSL (MTK_PIN_NO(131) | 1)</div><div class='del'>-#define PINMUX_GPIO131__FUNC_MRG_SYNC (MTK_PIN_NO(131) | 3)</div><div class='del'>-#define PINMUX_GPIO131__FUNC_DBG_MON_A25 (MTK_PIN_NO(131) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0)</div><div class='del'>-#define PINMUX_GPIO132__FUNC_MSDC0_DAT3 (MTK_PIN_NO(132) | 1)</div><div class='del'>-#define PINMUX_GPIO132__FUNC_MRG_DI (MTK_PIN_NO(132) | 3)</div><div class='del'>-#define PINMUX_GPIO132__FUNC_DBG_MON_A26 (MTK_PIN_NO(132) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0)</div><div class='del'>-#define PINMUX_GPIO133__FUNC_MSDC0_RSTB (MTK_PIN_NO(133) | 1)</div><div class='del'>-#define PINMUX_GPIO133__FUNC_AGPS_SYNC (MTK_PIN_NO(133) | 3)</div><div class='del'>-#define PINMUX_GPIO133__FUNC_DBG_MON_A27 (MTK_PIN_NO(133) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0)</div><div class='del'>-#define PINMUX_GPIO134__FUNC_RTC32K_CK (MTK_PIN_NO(134) | 1)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0)</div><div class='del'>-#define PINMUX_GPIO135__FUNC_WATCHDOG (MTK_PIN_NO(135) | 1)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0)</div><div class='del'>-#define PINMUX_GPIO136__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(136) | 1)</div><div class='del'>-#define PINMUX_GPIO136__FUNC_AUD_CLK_MISO (MTK_PIN_NO(136) | 2)</div><div class='del'>-#define PINMUX_GPIO136__FUNC_I2S1_MCK (MTK_PIN_NO(136) | 3)</div><div class='del'>-#define PINMUX_GPIO136__FUNC_UFS_UNIPRO_SCL (MTK_PIN_NO(136) | 6)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0)</div><div class='del'>-#define PINMUX_GPIO137__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(137) | 1)</div><div class='del'>-#define PINMUX_GPIO137__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(137) | 2)</div><div class='del'>-#define PINMUX_GPIO137__FUNC_I2S1_BCK (MTK_PIN_NO(137) | 3)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0)</div><div class='del'>-#define PINMUX_GPIO138__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(138) | 1)</div><div class='del'>-#define PINMUX_GPIO138__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(138) | 2)</div><div class='del'>-#define PINMUX_GPIO138__FUNC_I2S1_LRCK (MTK_PIN_NO(138) | 3)</div><div class='del'>-#define PINMUX_GPIO138__FUNC_DBG_MON_B24 (MTK_PIN_NO(138) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0)</div><div class='del'>-#define PINMUX_GPIO139__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(139) | 1)</div><div class='del'>-#define PINMUX_GPIO139__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(139) | 2)</div><div class='del'>-#define PINMUX_GPIO139__FUNC_I2S1_DO (MTK_PIN_NO(139) | 3)</div><div class='del'>-#define PINMUX_GPIO139__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(139) | 6)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0)</div><div class='del'>-#define PINMUX_GPIO140__FUNC_AUD_CLK_MISO (MTK_PIN_NO(140) | 1)</div><div class='del'>-#define PINMUX_GPIO140__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(140) | 2)</div><div class='del'>-#define PINMUX_GPIO140__FUNC_I2S0_MCK (MTK_PIN_NO(140) | 3)</div><div class='del'>-#define PINMUX_GPIO140__FUNC_UFS_UNIPRO_SDA (MTK_PIN_NO(140) | 6)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0)</div><div class='del'>-#define PINMUX_GPIO141__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(141) | 1)</div><div class='del'>-#define PINMUX_GPIO141__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(141) | 2)</div><div class='del'>-#define PINMUX_GPIO141__FUNC_I2S0_BCK (MTK_PIN_NO(141) | 3)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0)</div><div class='del'>-#define PINMUX_GPIO142__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(142) | 1)</div><div class='del'>-#define PINMUX_GPIO142__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(142) | 2)</div><div class='del'>-#define PINMUX_GPIO142__FUNC_I2S0_LRCK (MTK_PIN_NO(142) | 3)</div><div class='del'>-#define PINMUX_GPIO142__FUNC_VOW_DAT_MISO (MTK_PIN_NO(142) | 4)</div><div class='del'>-#define PINMUX_GPIO142__FUNC_DBG_MON_B25 (MTK_PIN_NO(142) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0)</div><div class='del'>-#define PINMUX_GPIO143__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(143) | 1)</div><div class='del'>-#define PINMUX_GPIO143__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(143) | 2)</div><div class='del'>-#define PINMUX_GPIO143__FUNC_I2S0_DI (MTK_PIN_NO(143) | 3)</div><div class='del'>-#define PINMUX_GPIO143__FUNC_VOW_CLK_MISO (MTK_PIN_NO(143) | 4)</div><div class='del'>-#define PINMUX_GPIO143__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(143) | 6)</div><div class='del'>-#define PINMUX_GPIO143__FUNC_DBG_MON_B26 (MTK_PIN_NO(143) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0)</div><div class='del'>-#define PINMUX_GPIO144__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(144) | 1)</div><div class='del'>-#define PINMUX_GPIO144__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(144) | 2)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0)</div><div class='del'>-#define PINMUX_GPIO145__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(145) | 1)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0)</div><div class='del'>-#define PINMUX_GPIO146__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(146) | 1)</div><div class='del'>-#define PINMUX_GPIO146__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(146) | 2)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0)</div><div class='del'>-#define PINMUX_GPIO147__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(147) | 1)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0)</div><div class='del'>-#define PINMUX_GPIO148__FUNC_SRCLKENA0 (MTK_PIN_NO(148) | 1)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0)</div><div class='del'>-#define PINMUX_GPIO149__FUNC_SRCLKENA1 (MTK_PIN_NO(149) | 1)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0)</div><div class='del'>-#define PINMUX_GPIO150__FUNC_PWM_A (MTK_PIN_NO(150) | 1)</div><div class='del'>-#define PINMUX_GPIO150__FUNC_CMFLASH (MTK_PIN_NO(150) | 2)</div><div class='del'>-#define PINMUX_GPIO150__FUNC_CLKM0 (MTK_PIN_NO(150) | 3)</div><div class='del'>-#define PINMUX_GPIO150__FUNC_DBG_MON_B30 (MTK_PIN_NO(150) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0)</div><div class='del'>-#define PINMUX_GPIO151__FUNC_PWM_B (MTK_PIN_NO(151) | 1)</div><div class='del'>-#define PINMUX_GPIO151__FUNC_CMVREF0 (MTK_PIN_NO(151) | 2)</div><div class='del'>-#define PINMUX_GPIO151__FUNC_CLKM1 (MTK_PIN_NO(151) | 3)</div><div class='del'>-#define PINMUX_GPIO151__FUNC_DBG_MON_B20 (MTK_PIN_NO(151) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0)</div><div class='del'>-#define PINMUX_GPIO152__FUNC_PWM_C (MTK_PIN_NO(152) | 1)</div><div class='del'>-#define PINMUX_GPIO152__FUNC_CMFLASH (MTK_PIN_NO(152) | 2)</div><div class='del'>-#define PINMUX_GPIO152__FUNC_CLKM2 (MTK_PIN_NO(152) | 3)</div><div class='del'>-#define PINMUX_GPIO152__FUNC_DBG_MON_B21 (MTK_PIN_NO(152) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0)</div><div class='del'>-#define PINMUX_GPIO153__FUNC_PWM_A (MTK_PIN_NO(153) | 1)</div><div class='del'>-#define PINMUX_GPIO153__FUNC_CMVREF0 (MTK_PIN_NO(153) | 2)</div><div class='del'>-#define PINMUX_GPIO153__FUNC_CLKM3 (MTK_PIN_NO(153) | 3)</div><div class='del'>-#define PINMUX_GPIO153__FUNC_DBG_MON_B22 (MTK_PIN_NO(153) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0)</div><div class='del'>-#define PINMUX_GPIO154__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(154) | 1)</div><div class='del'>-#define PINMUX_GPIO154__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(154) | 2)</div><div class='del'>-#define PINMUX_GPIO154__FUNC_DBG_MON_B18 (MTK_PIN_NO(154) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0)</div><div class='del'>-#define PINMUX_GPIO155__FUNC_ANT_SEL0 (MTK_PIN_NO(155) | 1)</div><div class='del'>-#define PINMUX_GPIO155__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(155) | 2)</div><div class='del'>-#define PINMUX_GPIO155__FUNC_CMVREF1 (MTK_PIN_NO(155) | 3)</div><div class='del'>-#define PINMUX_GPIO155__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(155) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0)</div><div class='del'>-#define PINMUX_GPIO156__FUNC_ANT_SEL1 (MTK_PIN_NO(156) | 1)</div><div class='del'>-#define PINMUX_GPIO156__FUNC_SRCLKENAI0 (MTK_PIN_NO(156) | 2)</div><div class='del'>-#define PINMUX_GPIO156__FUNC_SCL6 (MTK_PIN_NO(156) | 3)</div><div class='del'>-#define PINMUX_GPIO156__FUNC_KPCOL2 (MTK_PIN_NO(156) | 4)</div><div class='del'>-#define PINMUX_GPIO156__FUNC_IDDIG (MTK_PIN_NO(156) | 5)</div><div class='del'>-#define PINMUX_GPIO156__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(156) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0)</div><div class='del'>-#define PINMUX_GPIO157__FUNC_ANT_SEL2 (MTK_PIN_NO(157) | 1)</div><div class='del'>-#define PINMUX_GPIO157__FUNC_SRCLKENAI1 (MTK_PIN_NO(157) | 2)</div><div class='del'>-#define PINMUX_GPIO157__FUNC_SDA6 (MTK_PIN_NO(157) | 3)</div><div class='del'>-#define PINMUX_GPIO157__FUNC_KPROW2 (MTK_PIN_NO(157) | 4)</div><div class='del'>-#define PINMUX_GPIO157__FUNC_USB_DRVVBUS (MTK_PIN_NO(157) | 5)</div><div class='del'>-#define PINMUX_GPIO157__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(157) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0)</div><div class='del'>-#define PINMUX_GPIO158__FUNC_ANT_SEL3 (MTK_PIN_NO(158) | 1)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0)</div><div class='del'>-#define PINMUX_GPIO159__FUNC_ANT_SEL4 (MTK_PIN_NO(159) | 1)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0)</div><div class='del'>-#define PINMUX_GPIO160__FUNC_ANT_SEL5 (MTK_PIN_NO(160) | 1)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0)</div><div class='del'>-#define PINMUX_GPIO161__FUNC_SPI1_A_MI (MTK_PIN_NO(161) | 1)</div><div class='del'>-#define PINMUX_GPIO161__FUNC_SCP_SPI1_MI (MTK_PIN_NO(161) | 2)</div><div class='del'>-#define PINMUX_GPIO161__FUNC_IDDIG (MTK_PIN_NO(161) | 3)</div><div class='del'>-#define PINMUX_GPIO161__FUNC_ANT_SEL6 (MTK_PIN_NO(161) | 4)</div><div class='del'>-#define PINMUX_GPIO161__FUNC_KPCOL2 (MTK_PIN_NO(161) | 5)</div><div class='del'>-#define PINMUX_GPIO161__FUNC_PTA_RXD (MTK_PIN_NO(161) | 6)</div><div class='del'>-#define PINMUX_GPIO161__FUNC_DBG_MON_B19 (MTK_PIN_NO(161) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0)</div><div class='del'>-#define PINMUX_GPIO162__FUNC_SPI1_A_CSB (MTK_PIN_NO(162) | 1)</div><div class='del'>-#define PINMUX_GPIO162__FUNC_SCP_SPI1_CS (MTK_PIN_NO(162) | 2)</div><div class='del'>-#define PINMUX_GPIO162__FUNC_USB_DRVVBUS (MTK_PIN_NO(162) | 3)</div><div class='del'>-#define PINMUX_GPIO162__FUNC_ANT_SEL5 (MTK_PIN_NO(162) | 4)</div><div class='del'>-#define PINMUX_GPIO162__FUNC_KPROW2 (MTK_PIN_NO(162) | 5)</div><div class='del'>-#define PINMUX_GPIO162__FUNC_PTA_TXD (MTK_PIN_NO(162) | 6)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0)</div><div class='del'>-#define PINMUX_GPIO163__FUNC_SPI1_A_MO (MTK_PIN_NO(163) | 1)</div><div class='del'>-#define PINMUX_GPIO163__FUNC_SCP_SPI1_MO (MTK_PIN_NO(163) | 2)</div><div class='del'>-#define PINMUX_GPIO163__FUNC_SDA1 (MTK_PIN_NO(163) | 3)</div><div class='del'>-#define PINMUX_GPIO163__FUNC_ANT_SEL4 (MTK_PIN_NO(163) | 4)</div><div class='del'>-#define PINMUX_GPIO163__FUNC_CMMCLK2 (MTK_PIN_NO(163) | 5)</div><div class='del'>-#define PINMUX_GPIO163__FUNC_DMIC_CLK (MTK_PIN_NO(163) | 6)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0)</div><div class='del'>-#define PINMUX_GPIO164__FUNC_SPI1_A_CLK (MTK_PIN_NO(164) | 1)</div><div class='del'>-#define PINMUX_GPIO164__FUNC_SCP_SPI1_CK (MTK_PIN_NO(164) | 2)</div><div class='del'>-#define PINMUX_GPIO164__FUNC_SCL1 (MTK_PIN_NO(164) | 3)</div><div class='del'>-#define PINMUX_GPIO164__FUNC_ANT_SEL3 (MTK_PIN_NO(164) | 4)</div><div class='del'>-#define PINMUX_GPIO164__FUNC_CMMCLK3 (MTK_PIN_NO(164) | 5)</div><div class='del'>-#define PINMUX_GPIO164__FUNC_DMIC_DAT (MTK_PIN_NO(164) | 6)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0)</div><div class='del'>-#define PINMUX_GPIO165__FUNC_PWM_B (MTK_PIN_NO(165) | 1)</div><div class='del'>-#define PINMUX_GPIO165__FUNC_CMMCLK2 (MTK_PIN_NO(165) | 2)</div><div class='del'>-#define PINMUX_GPIO165__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(165) | 3)</div><div class='del'>-#define PINMUX_GPIO165__FUNC_TDM_MCK_2ND (MTK_PIN_NO(165) | 6)</div><div class='del'>-#define PINMUX_GPIO165__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(165) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0)</div><div class='del'>-#define PINMUX_GPIO166__FUNC_ANT_SEL6 (MTK_PIN_NO(166) | 1)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0)</div><div class='del'>-#define PINMUX_GPIO167__FUNC_RFIC0_BSI_EN (MTK_PIN_NO(167) | 1)</div><div class='del'>-#define PINMUX_GPIO167__FUNC_SPM_BSI_EN (MTK_PIN_NO(167) | 2)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0)</div><div class='del'>-#define PINMUX_GPIO168__FUNC_RFIC0_BSI_CK (MTK_PIN_NO(168) | 1)</div><div class='del'>-#define PINMUX_GPIO168__FUNC_SPM_BSI_CK (MTK_PIN_NO(168) | 2)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0)</div><div class='del'>-#define PINMUX_GPIO169__FUNC_PWM_C (MTK_PIN_NO(169) | 1)</div><div class='del'>-#define PINMUX_GPIO169__FUNC_CMMCLK3 (MTK_PIN_NO(169) | 2)</div><div class='del'>-#define PINMUX_GPIO169__FUNC_CMVREF1 (MTK_PIN_NO(169) | 3)</div><div class='del'>-#define PINMUX_GPIO169__FUNC_ANT_SEL7 (MTK_PIN_NO(169) | 4)</div><div class='del'>-#define PINMUX_GPIO169__FUNC_AGPS_SYNC (MTK_PIN_NO(169) | 5)</div><div class='del'>-#define PINMUX_GPIO169__FUNC_TDM_BCK_2ND (MTK_PIN_NO(169) | 6)</div><div class='del'>-#define PINMUX_GPIO169__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(169) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0)</div><div class='del'>-#define PINMUX_GPIO170__FUNC_I2S1_BCK (MTK_PIN_NO(170) | 1)</div><div class='del'>-#define PINMUX_GPIO170__FUNC_I2S3_BCK (MTK_PIN_NO(170) | 2)</div><div class='del'>-#define PINMUX_GPIO170__FUNC_SCL7 (MTK_PIN_NO(170) | 3)</div><div class='del'>-#define PINMUX_GPIO170__FUNC_I2S5_BCK (MTK_PIN_NO(170) | 4)</div><div class='del'>-#define PINMUX_GPIO170__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(170) | 5)</div><div class='del'>-#define PINMUX_GPIO170__FUNC_TDM_LRCK_2ND (MTK_PIN_NO(170) | 6)</div><div class='del'>-#define PINMUX_GPIO170__FUNC_ANT_SEL3 (MTK_PIN_NO(170) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0)</div><div class='del'>-#define PINMUX_GPIO171__FUNC_I2S1_LRCK (MTK_PIN_NO(171) | 1)</div><div class='del'>-#define PINMUX_GPIO171__FUNC_I2S3_LRCK (MTK_PIN_NO(171) | 2)</div><div class='del'>-#define PINMUX_GPIO171__FUNC_SDA7 (MTK_PIN_NO(171) | 3)</div><div class='del'>-#define PINMUX_GPIO171__FUNC_I2S5_LRCK (MTK_PIN_NO(171) | 4)</div><div class='del'>-#define PINMUX_GPIO171__FUNC_URXD1 (MTK_PIN_NO(171) | 5)</div><div class='del'>-#define PINMUX_GPIO171__FUNC_TDM_DATA0_2ND (MTK_PIN_NO(171) | 6)</div><div class='del'>-#define PINMUX_GPIO171__FUNC_ANT_SEL4 (MTK_PIN_NO(171) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0)</div><div class='del'>-#define PINMUX_GPIO172__FUNC_I2S1_DO (MTK_PIN_NO(172) | 1)</div><div class='del'>-#define PINMUX_GPIO172__FUNC_I2S3_DO (MTK_PIN_NO(172) | 2)</div><div class='del'>-#define PINMUX_GPIO172__FUNC_SCL8 (MTK_PIN_NO(172) | 3)</div><div class='del'>-#define PINMUX_GPIO172__FUNC_I2S5_DO (MTK_PIN_NO(172) | 4)</div><div class='del'>-#define PINMUX_GPIO172__FUNC_UTXD1 (MTK_PIN_NO(172) | 5)</div><div class='del'>-#define PINMUX_GPIO172__FUNC_TDM_DATA1_2ND (MTK_PIN_NO(172) | 6)</div><div class='del'>-#define PINMUX_GPIO172__FUNC_ANT_SEL5 (MTK_PIN_NO(172) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0)</div><div class='del'>-#define PINMUX_GPIO173__FUNC_I2S1_MCK (MTK_PIN_NO(173) | 1)</div><div class='del'>-#define PINMUX_GPIO173__FUNC_I2S3_MCK (MTK_PIN_NO(173) | 2)</div><div class='del'>-#define PINMUX_GPIO173__FUNC_SDA8 (MTK_PIN_NO(173) | 3)</div><div class='del'>-#define PINMUX_GPIO173__FUNC_I2S5_MCK (MTK_PIN_NO(173) | 4)</div><div class='del'>-#define PINMUX_GPIO173__FUNC_UCTS0 (MTK_PIN_NO(173) | 5)</div><div class='del'>-#define PINMUX_GPIO173__FUNC_TDM_DATA2_2ND (MTK_PIN_NO(173) | 6)</div><div class='del'>-#define PINMUX_GPIO173__FUNC_ANT_SEL6 (MTK_PIN_NO(173) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0)</div><div class='del'>-#define PINMUX_GPIO174__FUNC_I2S2_DI (MTK_PIN_NO(174) | 1)</div><div class='del'>-#define PINMUX_GPIO174__FUNC_I2S0_DI (MTK_PIN_NO(174) | 2)</div><div class='del'>-#define PINMUX_GPIO174__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(174) | 3)</div><div class='del'>-#define PINMUX_GPIO174__FUNC_I2S2_DI2 (MTK_PIN_NO(174) | 4)</div><div class='del'>-#define PINMUX_GPIO174__FUNC_URTS0 (MTK_PIN_NO(174) | 5)</div><div class='del'>-#define PINMUX_GPIO174__FUNC_TDM_DATA3_2ND (MTK_PIN_NO(174) | 6)</div><div class='del'>-#define PINMUX_GPIO174__FUNC_ANT_SEL7 (MTK_PIN_NO(174) | 7)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0)</div><div class='del'>-#define PINMUX_GPIO175__FUNC_ANT_SEL7 (MTK_PIN_NO(175) | 1)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0)</div><div class='del'>-</div><div class='del'>-#define PINMUX_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0)</div><div class='del'>-</div><div class='del'>-#endif /* __MT8183-PINFUNC_H */</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts<br/>new file mode 100644<br/>index 000000000000..f60ef3e53a09<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts</a></div><div class='hunk'>@@ -0,0 +1,538 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2021 BayLibre, SAS.</div><div class='add'>+ * Author: Fabien Parent &lt;fparent@baylibre.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include "mt8183.dtsi"</div><div class='add'>+#include "mt6358.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Pumpkin MT8183";</div><div class='add'>+	compatible = "mediatek,mt8183-pumpkin", "mediatek,mt8183";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0 0x40000000 0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:921600n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		scp_mem_reserved: scp-mem@50000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x50000000 0 0x2900000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-red {</div><div class='add'>+			label = "red";</div><div class='add'>+			gpios = &lt;&amp;pio 155 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-green {</div><div class='add'>+			label = "green";</div><div class='add'>+			gpios = &lt;&amp;pio 156 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	thermistor {</div><div class='add'>+		compatible = "murata,ncp03wf104";</div><div class='add'>+		pullup-uv = &lt;1800000&gt;;</div><div class='add'>+		pullup-ohm = &lt;390000&gt;;</div><div class='add'>+		pulldown-ohm = &lt;0&gt;;</div><div class='add'>+		io-channels = &lt;&amp;auxadc 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		label = "hdmi";</div><div class='add'>+		type = "d";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			hdmi_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_connector_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;auxadc {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	mali-supply = &lt;&amp;mt6358_vgpu_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c_pins_0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c_pins_1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c_pins_2&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c_pins_3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c_pins_4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c5 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c_pins_5&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c6 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c6_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	it66121hdmitx: hdmitx@4c {</div><div class='add'>+		compatible = "ite,it66121";</div><div class='add'>+		reg = &lt;0x4c&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;ite_pins&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pio 160 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;pio&gt;;</div><div class='add'>+		interrupts = &lt;4 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		vcn33-supply = &lt;&amp;mt6358_vcn33_reg&gt;;</div><div class='add'>+		vcn18-supply = &lt;&amp;mt6358_vcn18_reg&gt;;</div><div class='add'>+		vrf12-supply = &lt;&amp;mt6358_vrf12_reg&gt;;</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				it66121_in: endpoint {</div><div class='add'>+					bus-width = &lt;12&gt;;</div><div class='add'>+					remote-endpoint = &lt;&amp;dpi_out&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				hdmi_connector_out: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;hdmi_connector_in&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;keyboard {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;keyboard_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+	linux,keymap = &lt;MATRIX_KEY(0x00, 0x00, KEY_VOLUMEDOWN)</div><div class='add'>+			MATRIX_KEY(0x01, 0x00, KEY_VOLUMEUP)&gt;;</div><div class='add'>+	keypad,num-rows = &lt;2&gt;;</div><div class='add'>+	keypad,num-columns = &lt;1&gt;;</div><div class='add'>+	debounce-delay-ms = &lt;32&gt;;</div><div class='add'>+	mediatek,keys-per-group = &lt;2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-names = "default", "state_uhs";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc0_pins_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;mmc0_pins_uhs&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	cap-mmc-highspeed;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	mmc-hs400-1_8v;</div><div class='add'>+	cap-mmc-hw-reset;</div><div class='add'>+	no-sdio;</div><div class='add'>+	no-sd;</div><div class='add'>+	hs400-ds-delay = &lt;0x12814&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;mt6358_vemc_reg&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;mt6358_vio18_reg&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;topckgen CLK_TOP_MUX_MSDC50_0&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_MSDCPLL_CK&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-names = "default", "state_uhs";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc1_pins_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;mmc1_pins_uhs&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	sd-uhs-sdr50;</div><div class='add'>+	sd-uhs-sdr104;</div><div class='add'>+	cap-sdio-irq;</div><div class='add'>+	no-mmc;</div><div class='add'>+	no-sd;</div><div class='add'>+	vmmc-supply = &lt;&amp;mt6358_vmch_reg&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;mt6358_vmc_reg&gt;;</div><div class='add'>+	keep-power-in-suspend;</div><div class='add'>+	wakeup-source;</div><div class='add'>+	non-removable;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6358_vgpu_reg {</div><div class='add'>+	regulator-min-microvolt = &lt;625000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;900000&gt;;</div><div class='add'>+</div><div class='add'>+	regulator-coupled-with = &lt;&amp;mt6358_vsram_gpu_reg&gt;;</div><div class='add'>+	regulator-coupled-max-spread = &lt;100000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6358_vsram_gpu_reg {</div><div class='add'>+	regulator-min-microvolt = &lt;850000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+</div><div class='add'>+	regulator-coupled-with = &lt;&amp;mt6358_vgpu_reg&gt;;</div><div class='add'>+	regulator-coupled-max-spread = &lt;100000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	i2c_pins_0: i2c0 {</div><div class='add'>+		pins_i2c {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO82__FUNC_SDA0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO83__FUNC_SCL0&gt;;</div><div class='add'>+			mediatek,pull-up-adv = &lt;3&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c_pins_1: i2c1 {</div><div class='add'>+		pins_i2c {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO81__FUNC_SDA1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO84__FUNC_SCL1&gt;;</div><div class='add'>+			mediatek,pull-up-adv = &lt;3&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c_pins_2: i2c2 {</div><div class='add'>+		pins_i2c {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO103__FUNC_SCL2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO104__FUNC_SDA2&gt;;</div><div class='add'>+			mediatek,pull-up-adv = &lt;3&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c_pins_3: i2c3 {</div><div class='add'>+		pins_i2c {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO50__FUNC_SCL3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO51__FUNC_SDA3&gt;;</div><div class='add'>+			mediatek,pull-up-adv = &lt;3&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c_pins_4: i2c4 {</div><div class='add'>+		pins_i2c {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO105__FUNC_SCL4&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO106__FUNC_SDA4&gt;;</div><div class='add'>+			mediatek,pull-up-adv = &lt;3&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c_pins_5: i2c5 {</div><div class='add'>+		pins_i2c {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO48__FUNC_SCL5&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO49__FUNC_SDA5&gt;;</div><div class='add'>+			mediatek,pull-up-adv = &lt;3&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c6_pins: i2c6 {</div><div class='add'>+		pins_cmd_dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO113__FUNC_SCL6&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO114__FUNC_SDA6&gt;;</div><div class='add'>+			mediatek,pull-up-adv = &lt;3&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	keyboard_pins: keyboard {</div><div class='add'>+		pins_keyboard {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO91__FUNC_KPROW1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO92__FUNC_KPROW0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO93__FUNC_KPCOL0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc0_pins_default: mmc0-pins-default {</div><div class='add'>+		pins_cmd_dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO123__FUNC_MSDC0_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO128__FUNC_MSDC0_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO125__FUNC_MSDC0_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO132__FUNC_MSDC0_DAT3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO126__FUNC_MSDC0_DAT4&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO129__FUNC_MSDC0_DAT5&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO127__FUNC_MSDC0_DAT6&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO130__FUNC_MSDC0_DAT7&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO122__FUNC_MSDC0_CMD&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;MTK_DRIVE_14mA&gt;;</div><div class='add'>+			mediatek,pull-up-adv = &lt;01&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins_clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO124__FUNC_MSDC0_CLK&gt;;</div><div class='add'>+			drive-strength = &lt;MTK_DRIVE_14mA&gt;;</div><div class='add'>+			mediatek,pull-down-adv = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins_rst {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO133__FUNC_MSDC0_RSTB&gt;;</div><div class='add'>+			drive-strength = &lt;MTK_DRIVE_14mA&gt;;</div><div class='add'>+			mediatek,pull-down-adv = &lt;01&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc0_pins_uhs: mmc0-pins-uhs {</div><div class='add'>+		pins_cmd_dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO123__FUNC_MSDC0_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO128__FUNC_MSDC0_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO125__FUNC_MSDC0_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO132__FUNC_MSDC0_DAT3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO126__FUNC_MSDC0_DAT4&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO129__FUNC_MSDC0_DAT5&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO127__FUNC_MSDC0_DAT6&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO130__FUNC_MSDC0_DAT7&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO122__FUNC_MSDC0_CMD&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;MTK_DRIVE_14mA&gt;;</div><div class='add'>+			mediatek,pull-up-adv = &lt;01&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins_clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO124__FUNC_MSDC0_CLK&gt;;</div><div class='add'>+			drive-strength = &lt;MTK_DRIVE_14mA&gt;;</div><div class='add'>+			mediatek,pull-down-adv = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins_ds {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO131__FUNC_MSDC0_DSL&gt;;</div><div class='add'>+			drive-strength = &lt;MTK_DRIVE_14mA&gt;;</div><div class='add'>+			mediatek,pull-down-adv = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins_rst {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO133__FUNC_MSDC0_RSTB&gt;;</div><div class='add'>+			drive-strength = &lt;MTK_DRIVE_14mA&gt;;</div><div class='add'>+			mediatek,pull-up-adv = &lt;01&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc1_pins_default: mmc1-pins-default {</div><div class='add'>+		pins_cmd_dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO31__FUNC_MSDC1_CMD&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO32__FUNC_MSDC1_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO34__FUNC_MSDC1_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO33__FUNC_MSDC1_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO30__FUNC_MSDC1_DAT3&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			mediatek,pull-up-adv = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins_clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO29__FUNC_MSDC1_CLK&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			mediatek,pull-down-adv = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins_pmu {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO178__FUNC_GPIO178&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc1_pins_uhs: mmc1-pins-uhs {</div><div class='add'>+		pins_cmd_dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO31__FUNC_MSDC1_CMD&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO32__FUNC_MSDC1_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO34__FUNC_MSDC1_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO33__FUNC_MSDC1_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO30__FUNC_MSDC1_DAT3&gt;;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			mediatek,pull-up-adv = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins_clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO29__FUNC_MSDC1_CLK&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			mediatek,pull-down-adv = &lt;2&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ite_pins: ite-pins {</div><div class='add'>+		pins-irq {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO4__FUNC_GPIO4&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-rst {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO160__FUNC_GPIO160&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dpi_func_pins: dpi-func-pins {</div><div class='add'>+		pins-dpi {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO12__FUNC_I2S5_BCK&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO46__FUNC_I2S5_LRCK&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO47__FUNC_I2S5_DO&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO13__FUNC_DBPI_D0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO14__FUNC_DBPI_D1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO15__FUNC_DBPI_D2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO16__FUNC_DBPI_D3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO17__FUNC_DBPI_D4&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO18__FUNC_DBPI_D5&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO19__FUNC_DBPI_D6&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO20__FUNC_DBPI_D7&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO21__FUNC_DBPI_D8&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO22__FUNC_DBPI_D9&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO23__FUNC_DBPI_D10&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO24__FUNC_DBPI_D11&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO25__FUNC_DBPI_HSYNC&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO26__FUNC_DBPI_VSYNC&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO27__FUNC_DBPI_DE&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO28__FUNC_DBPI_CK&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dpi_idle_pins: dpi-idle-pins {</div><div class='add'>+		pins-idle {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO12__FUNC_GPIO12&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO46__FUNC_GPIO46&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO47__FUNC_GPIO47&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO13__FUNC_GPIO13&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO14__FUNC_GPIO14&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO15__FUNC_GPIO15&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO16__FUNC_GPIO16&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO17__FUNC_GPIO17&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO18__FUNC_GPIO18&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO19__FUNC_GPIO19&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO20__FUNC_GPIO20&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO21__FUNC_GPIO21&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO22__FUNC_GPIO22&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO23__FUNC_GPIO23&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO24__FUNC_GPIO24&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO25__FUNC_GPIO25&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO26__FUNC_GPIO26&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO27__FUNC_GPIO27&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO28__FUNC_GPIO28&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pmic {</div><div class='add'>+	interrupts-extended = &lt;&amp;pio 182 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mfg {</div><div class='add'>+	domain-supply = &lt;&amp;mt6358_vgpu_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cci {</div><div class='add'>+	proc-supply = &lt;&amp;mt6358_vproc12_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	proc-supply = &lt;&amp;mt6358_vproc12_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu1 {</div><div class='add'>+	proc-supply = &lt;&amp;mt6358_vproc12_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu2 {</div><div class='add'>+	proc-supply = &lt;&amp;mt6358_vproc12_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu3 {</div><div class='add'>+	proc-supply = &lt;&amp;mt6358_vproc12_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu4 {</div><div class='add'>+	proc-supply = &lt;&amp;mt6358_vproc11_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu5 {</div><div class='add'>+	proc-supply = &lt;&amp;mt6358_vproc11_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu6 {</div><div class='add'>+	proc-supply = &lt;&amp;mt6358_vproc11_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu7 {</div><div class='add'>+	proc-supply = &lt;&amp;mt6358_vproc11_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;scp {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpi0 {</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;dpi_func_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;dpi_idle_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpi_out {</div><div class='add'>+	remote-endpoint = &lt;&amp;it66121_in&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi<br/>index 97863adb7bc0..4e20a8f2eb25 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8183.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8183.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8183.dtsi</a></div><div class='hunk'>@@ -6,10 +6,15 @@</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;dt-bindings/clock/mt8183-clk.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gce/mt8183-gce.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='del'>-#include &lt;dt-bindings/reset-controller/mt8183-resets.h&gt;</div><div class='del'>-#include "mt8183-pinfunc.h"</div><div class='add'>+#include &lt;dt-bindings/memory/mt8183-larb-port.h&gt;</div><div class='add'>+#include &lt;dt-bindings/power/mt8183-power.h&gt;</div><div class='add'>+#include &lt;dt-bindings/reset/mt8183-resets.h&gt;</div><div class='add'>+#include &lt;dt-bindings/phy/phy.h&gt;</div><div class='add'>+#include &lt;dt-bindings/thermal/thermal.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/mt8183-pinfunc.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	compatible = "mediatek,mt8183";</div><div class='hunk'>@@ -30,6 +35,257 @@</div><div class='ctx'> 		i2c9 = &amp;i2c9;</div><div class='ctx'> 		i2c10 = &amp;i2c10;</div><div class='ctx'> 		i2c11 = &amp;i2c11;</div><div class='add'>+		ovl0 = &amp;ovl0;</div><div class='add'>+		ovl-2l0 = &amp;ovl_2l0;</div><div class='add'>+		ovl-2l1 = &amp;ovl_2l1;</div><div class='add'>+		rdma0 = &amp;rdma0;</div><div class='add'>+		rdma1 = &amp;rdma1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cluster0_opp: opp-table-cluster0 {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+		opp-shared;</div><div class='add'>+		opp0-793000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;793000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;650000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;opp2_00&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp0-910000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;910000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;687500&gt;;</div><div class='add'>+			required-opps = &lt;&amp;opp2_01&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp0-1014000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1014000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;718750&gt;;</div><div class='add'>+			required-opps = &lt;&amp;opp2_02&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp0-1131000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1131000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;756250&gt;;</div><div class='add'>+			required-opps = &lt;&amp;opp2_03&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp0-1248000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1248000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;800000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;opp2_04&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp0-1326000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1326000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;818750&gt;;</div><div class='add'>+			required-opps = &lt;&amp;opp2_05&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp0-1417000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1417000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;850000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;opp2_06&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp0-1508000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1508000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;868750&gt;;</div><div class='add'>+			required-opps = &lt;&amp;opp2_07&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp0-1586000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1586000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;893750&gt;;</div><div class='add'>+			required-opps = &lt;&amp;opp2_08&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp0-1625000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1625000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;906250&gt;;</div><div class='add'>+			required-opps = &lt;&amp;opp2_09&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp0-1677000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1677000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;931250&gt;;</div><div class='add'>+			required-opps = &lt;&amp;opp2_10&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp0-1716000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1716000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;943750&gt;;</div><div class='add'>+			required-opps = &lt;&amp;opp2_11&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp0-1781000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1781000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;975000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;opp2_12&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp0-1846000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1846000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1000000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;opp2_13&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp0-1924000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1924000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1025000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;opp2_14&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp0-1989000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1989000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1050000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;opp2_15&gt;;</div><div class='add'>+		};	};</div><div class='add'>+</div><div class='add'>+	cluster1_opp: opp-table-cluster1 {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+		opp-shared;</div><div class='add'>+		opp1-793000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;793000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;700000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;opp2_00&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp1-910000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;910000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;725000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;opp2_01&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp1-1014000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1014000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;750000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;opp2_02&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp1-1131000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1131000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;775000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;opp2_03&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp1-1248000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1248000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;800000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;opp2_04&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp1-1326000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1326000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;825000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;opp2_05&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp1-1417000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1417000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;850000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;opp2_06&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp1-1508000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1508000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;875000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;opp2_07&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp1-1586000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1586000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;900000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;opp2_08&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp1-1625000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1625000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;912500&gt;;</div><div class='add'>+			required-opps = &lt;&amp;opp2_09&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp1-1677000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1677000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;931250&gt;;</div><div class='add'>+			required-opps = &lt;&amp;opp2_10&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp1-1716000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1716000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;950000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;opp2_11&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp1-1781000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1781000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;975000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;opp2_12&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp1-1846000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1846000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1000000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;opp2_13&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp1-1924000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1924000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1025000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;opp2_14&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp1-1989000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1989000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1050000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;opp2_15&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cci_opp: opp-table-cci {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+		opp-shared;</div><div class='add'>+		opp2_00: opp-273000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;273000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;650000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp2_01: opp-338000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;338000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;687500&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp2_02: opp-403000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;403000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;718750&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp2_03: opp-463000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;463000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;756250&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp2_04: opp-546000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;546000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;800000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp2_05: opp-624000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;624000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;818750&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp2_06: opp-689000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;689000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;850000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp2_07: opp-767000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;767000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;868750&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp2_08: opp-845000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;845000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;893750&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp2_09: opp-871000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;871000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;906250&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp2_10: opp-923000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;923000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;931250&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp2_11: opp-962000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;962000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;943750&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp2_12: opp-1027000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1027000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;975000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp2_13: opp-1092000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1092000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1000000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp2_14: opp-1144000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1144000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1025000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp2_15: opp-1196000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1196000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1050000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cci: cci {</div><div class='add'>+		compatible = "mediatek,mt8183-cci";</div><div class='add'>+		clocks = &lt;&amp;mcucfg CLK_MCU_BUS_SEL&gt;,</div><div class='add'>+			 &lt;&amp;topckgen CLK_TOP_ARMPLL_DIV_PLL1&gt;;</div><div class='add'>+		clock-names = "cci", "intermediate";</div><div class='add'>+		operating-points-v2 = &lt;&amp;cci_opp&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	cpus {</div><div class='hunk'>@@ -74,9 +330,21 @@</div><div class='ctx'> 			reg = &lt;0x000&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			capacity-dmips-mhz = &lt;741&gt;;</div><div class='del'>-			cpu-idle-states = &lt;&amp;CPU_SLEEP &amp;CLUSTER_SLEEP&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;CPU_SLEEP &amp;CLUSTER_SLEEP0&gt;;</div><div class='add'>+			clocks = &lt;&amp;mcucfg CLK_MCU_MP0_SEL&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_ARMPLL_DIV_PLL1&gt;;</div><div class='add'>+			clock-names = "cpu", "intermediate";</div><div class='add'>+			operating-points-v2 = &lt;&amp;cluster0_opp&gt;;</div><div class='ctx'> 			dynamic-power-coefficient = &lt;84&gt;;</div><div class='add'>+			i-cache-size = &lt;32768&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;32768&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			mediatek,cci = &lt;&amp;cci&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu1: cpu@1 {</div><div class='hunk'>@@ -85,9 +353,21 @@</div><div class='ctx'> 			reg = &lt;0x001&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			capacity-dmips-mhz = &lt;741&gt;;</div><div class='del'>-			cpu-idle-states = &lt;&amp;CPU_SLEEP &amp;CLUSTER_SLEEP&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;CPU_SLEEP &amp;CLUSTER_SLEEP0&gt;;</div><div class='add'>+			clocks = &lt;&amp;mcucfg CLK_MCU_MP0_SEL&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_ARMPLL_DIV_PLL1&gt;;</div><div class='add'>+			clock-names = "cpu", "intermediate";</div><div class='add'>+			operating-points-v2 = &lt;&amp;cluster0_opp&gt;;</div><div class='ctx'> 			dynamic-power-coefficient = &lt;84&gt;;</div><div class='add'>+			i-cache-size = &lt;32768&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;32768&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			mediatek,cci = &lt;&amp;cci&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu2: cpu@2 {</div><div class='hunk'>@@ -96,9 +376,21 @@</div><div class='ctx'> 			reg = &lt;0x002&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			capacity-dmips-mhz = &lt;741&gt;;</div><div class='del'>-			cpu-idle-states = &lt;&amp;CPU_SLEEP &amp;CLUSTER_SLEEP&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;CPU_SLEEP &amp;CLUSTER_SLEEP0&gt;;</div><div class='add'>+			clocks = &lt;&amp;mcucfg CLK_MCU_MP0_SEL&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_ARMPLL_DIV_PLL1&gt;;</div><div class='add'>+			clock-names = "cpu", "intermediate";</div><div class='add'>+			operating-points-v2 = &lt;&amp;cluster0_opp&gt;;</div><div class='ctx'> 			dynamic-power-coefficient = &lt;84&gt;;</div><div class='add'>+			i-cache-size = &lt;32768&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;32768&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			mediatek,cci = &lt;&amp;cci&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu3: cpu@3 {</div><div class='hunk'>@@ -107,9 +399,21 @@</div><div class='ctx'> 			reg = &lt;0x003&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			capacity-dmips-mhz = &lt;741&gt;;</div><div class='del'>-			cpu-idle-states = &lt;&amp;CPU_SLEEP &amp;CLUSTER_SLEEP&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;CPU_SLEEP &amp;CLUSTER_SLEEP0&gt;;</div><div class='add'>+			clocks = &lt;&amp;mcucfg CLK_MCU_MP0_SEL&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_ARMPLL_DIV_PLL1&gt;;</div><div class='add'>+			clock-names = "cpu", "intermediate";</div><div class='add'>+			operating-points-v2 = &lt;&amp;cluster0_opp&gt;;</div><div class='ctx'> 			dynamic-power-coefficient = &lt;84&gt;;</div><div class='add'>+			i-cache-size = &lt;32768&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;32768&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			mediatek,cci = &lt;&amp;cci&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu4: cpu@100 {</div><div class='hunk'>@@ -118,9 +422,21 @@</div><div class='ctx'> 			reg = &lt;0x100&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='del'>-			cpu-idle-states = &lt;&amp;CPU_SLEEP &amp;CLUSTER_SLEEP&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;CPU_SLEEP &amp;CLUSTER_SLEEP1&gt;;</div><div class='add'>+			clocks = &lt;&amp;mcucfg CLK_MCU_MP2_SEL&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_ARMPLL_DIV_PLL1&gt;;</div><div class='add'>+			clock-names = "cpu", "intermediate";</div><div class='add'>+			operating-points-v2 = &lt;&amp;cluster1_opp&gt;;</div><div class='ctx'> 			dynamic-power-coefficient = &lt;211&gt;;</div><div class='add'>+			i-cache-size = &lt;65536&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;65536&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_1&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			mediatek,cci = &lt;&amp;cci&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu5: cpu@101 {</div><div class='hunk'>@@ -129,9 +445,21 @@</div><div class='ctx'> 			reg = &lt;0x101&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='del'>-			cpu-idle-states = &lt;&amp;CPU_SLEEP &amp;CLUSTER_SLEEP&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;CPU_SLEEP &amp;CLUSTER_SLEEP1&gt;;</div><div class='add'>+			clocks = &lt;&amp;mcucfg CLK_MCU_MP2_SEL&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_ARMPLL_DIV_PLL1&gt;;</div><div class='add'>+			clock-names = "cpu", "intermediate";</div><div class='add'>+			operating-points-v2 = &lt;&amp;cluster1_opp&gt;;</div><div class='ctx'> 			dynamic-power-coefficient = &lt;211&gt;;</div><div class='add'>+			i-cache-size = &lt;65536&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;65536&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_1&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			mediatek,cci = &lt;&amp;cci&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu6: cpu@102 {</div><div class='hunk'>@@ -140,9 +468,21 @@</div><div class='ctx'> 			reg = &lt;0x102&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='del'>-			cpu-idle-states = &lt;&amp;CPU_SLEEP &amp;CLUSTER_SLEEP&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;CPU_SLEEP &amp;CLUSTER_SLEEP1&gt;;</div><div class='add'>+			clocks = &lt;&amp;mcucfg CLK_MCU_MP2_SEL&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_ARMPLL_DIV_PLL1&gt;;</div><div class='add'>+			clock-names = "cpu", "intermediate";</div><div class='add'>+			operating-points-v2 = &lt;&amp;cluster1_opp&gt;;</div><div class='ctx'> 			dynamic-power-coefficient = &lt;211&gt;;</div><div class='add'>+			i-cache-size = &lt;65536&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;65536&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_1&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			mediatek,cci = &lt;&amp;cci&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu7: cpu@103 {</div><div class='hunk'>@@ -151,9 +491,21 @@</div><div class='ctx'> 			reg = &lt;0x103&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='del'>-			cpu-idle-states = &lt;&amp;CPU_SLEEP &amp;CLUSTER_SLEEP&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;CPU_SLEEP &amp;CLUSTER_SLEEP1&gt;;</div><div class='add'>+			clocks = &lt;&amp;mcucfg CLK_MCU_MP2_SEL&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_ARMPLL_DIV_PLL1&gt;;</div><div class='add'>+			clock-names = "cpu", "intermediate";</div><div class='add'>+			operating-points-v2 = &lt;&amp;cluster1_opp&gt;;</div><div class='ctx'> 			dynamic-power-coefficient = &lt;211&gt;;</div><div class='add'>+			i-cache-size = &lt;65536&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;65536&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_1&gt;;</div><div class='ctx'> 			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			mediatek,cci = &lt;&amp;cci&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		idle-states {</div><div class='hunk'>@@ -168,7 +520,15 @@</div><div class='ctx'> 				min-residency-us = &lt;800&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			CLUSTER_SLEEP: cluster-sleep {</div><div class='add'>+			CLUSTER_SLEEP0: cluster-sleep-0 {</div><div class='add'>+				compatible = "arm,idle-state";</div><div class='add'>+				local-timer-stop;</div><div class='add'>+				arm,psci-suspend-param = &lt;0x01010001&gt;;</div><div class='add'>+				entry-latency-us = &lt;250&gt;;</div><div class='add'>+				exit-latency-us = &lt;400&gt;;</div><div class='add'>+				min-residency-us = &lt;1000&gt;;</div><div class='add'>+			};</div><div class='add'>+			CLUSTER_SLEEP1: cluster-sleep-1 {</div><div class='ctx'> 				compatible = "arm,idle-state";</div><div class='ctx'> 				local-timer-stop;</div><div class='ctx'> 				arm,psci-suspend-param = &lt;0x01010001&gt;;</div><div class='hunk'>@@ -177,6 +537,109 @@</div><div class='ctx'> 				min-residency-us = &lt;1300&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='add'>+</div><div class='add'>+		l2_0: l2-cache0 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-size = &lt;1048576&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;1024&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_1: l2-cache1 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-size = &lt;1048576&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;1024&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpu_opp_table: opp-table-0 {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+		opp-shared;</div><div class='add'>+</div><div class='add'>+		opp-300000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;300000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;625000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-320000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;320000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;631250&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-340000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;340000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;637500&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-360000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;360000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;643750&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-380000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;380000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;650000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-400000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;400000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;656250&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-420000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;420000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;662500&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-460000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;460000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;675000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-500000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;500000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;687500&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-540000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;540000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;700000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-580000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;580000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;712500&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-620000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;620000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;725000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-653000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;653000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;743750&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-698000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;698000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;768750&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-743000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;743000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;793750&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-800000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;800000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;825000&gt;;</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	pmu-a53 {</div><div class='hunk'>@@ -192,8 +655,17 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	psci {</div><div class='del'>-		compatible      = "arm,psci-1.0";</div><div class='del'>-		method          = "smc";</div><div class='add'>+		compatible = "arm,psci-1.0";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk13m: fixed-factor-clock-13m {</div><div class='add'>+		compatible = "fixed-factor-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk26m&gt;;</div><div class='add'>+		clock-div = &lt;2&gt;;</div><div class='add'>+		clock-mult = &lt;1&gt;;</div><div class='add'>+		clock-output-names = "clk13m";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	clk26m: oscillator {</div><div class='hunk'>@@ -218,7 +690,7 @@</div><div class='ctx'> 		compatible = "simple-bus";</div><div class='ctx'> 		ranges;</div><div class='ctx'> </div><div class='del'>-		soc_data: soc_data@8000000 {</div><div class='add'>+		soc_data: efuse@8000000 {</div><div class='ctx'> 			compatible = "mediatek,mt8183-efuse",</div><div class='ctx'> 				     "mediatek,efuse";</div><div class='ctx'> 			reg = &lt;0 0x08000000 0 0x0010&gt;;</div><div class='hunk'>@@ -264,6 +736,70 @@</div><div class='ctx'> 			reg = &lt;0 0x0c530a80 0 0x50&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		cpu_debug0: cpu-debug@d410000 {</div><div class='add'>+			compatible = "arm,coresight-cpu-debug", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0xd410000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_DEBUGSYS&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			cpu = &lt;&amp;cpu0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_debug1: cpu-debug@d510000 {</div><div class='add'>+			compatible = "arm,coresight-cpu-debug", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0xd510000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_DEBUGSYS&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			cpu = &lt;&amp;cpu1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_debug2: cpu-debug@d610000 {</div><div class='add'>+			compatible = "arm,coresight-cpu-debug", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0xd610000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_DEBUGSYS&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			cpu = &lt;&amp;cpu2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_debug3: cpu-debug@d710000 {</div><div class='add'>+			compatible = "arm,coresight-cpu-debug", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0xd710000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_DEBUGSYS&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			cpu = &lt;&amp;cpu3&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_debug4: cpu-debug@d810000 {</div><div class='add'>+			compatible = "arm,coresight-cpu-debug", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0xd810000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_DEBUGSYS&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			cpu = &lt;&amp;cpu4&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_debug5: cpu-debug@d910000 {</div><div class='add'>+			compatible = "arm,coresight-cpu-debug", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0xd910000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_DEBUGSYS&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			cpu = &lt;&amp;cpu5&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_debug6: cpu-debug@da10000 {</div><div class='add'>+			compatible = "arm,coresight-cpu-debug", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0xda10000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_DEBUGSYS&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			cpu = &lt;&amp;cpu6&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_debug7: cpu-debug@db10000 {</div><div class='add'>+			compatible = "arm,coresight-cpu-debug", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0xdb10000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_DEBUGSYS&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			cpu = &lt;&amp;cpu7&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		topckgen: syscon@10000000 {</div><div class='ctx'> 			compatible = "mediatek,mt8183-topckgen", "syscon";</div><div class='ctx'> 			reg = &lt;0 0x10000000 0 0x1000&gt;;</div><div class='hunk'>@@ -277,6 +813,12 @@</div><div class='ctx'> 			#reset-cells = &lt;1&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		pericfg: syscon@10003000 {</div><div class='add'>+			compatible = "mediatek,mt8183-pericfg", "syscon";</div><div class='add'>+			reg = &lt;0 0x10003000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		pio: pinctrl@10005000 {</div><div class='ctx'> 			compatible = "mediatek,mt8183-pinctrl";</div><div class='ctx'> 			reg = &lt;0 0x10005000 0 0x1000&gt;,</div><div class='hunk'>@@ -301,9 +843,166 @@</div><div class='ctx'> 			#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		scpsys: syscon@10006000 {</div><div class='add'>+			compatible = "mediatek,mt8183-scpsys", "syscon", "simple-mfd";</div><div class='add'>+			reg = &lt;0 0x10006000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			/* System Power Manager */</div><div class='add'>+			spm: power-controller {</div><div class='add'>+				compatible = "mediatek,mt8183-power-controller";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				/* power domain of the SoC */</div><div class='add'>+				power-domain@MT8183_POWER_DOMAIN_AUDIO {</div><div class='add'>+					reg = &lt;MT8183_POWER_DOMAIN_AUDIO&gt;;</div><div class='add'>+					clocks = &lt;&amp;topckgen CLK_TOP_MUX_AUD_INTBUS&gt;,</div><div class='add'>+						 &lt;&amp;infracfg CLK_INFRA_AUDIO&gt;,</div><div class='add'>+						 &lt;&amp;infracfg CLK_INFRA_AUDIO_26M_BCLK&gt;;</div><div class='add'>+					clock-names = "audio", "audio1", "audio2";</div><div class='add'>+					#power-domain-cells = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				power-domain@MT8183_POWER_DOMAIN_CONN {</div><div class='add'>+					reg = &lt;MT8183_POWER_DOMAIN_CONN&gt;;</div><div class='add'>+					mediatek,infracfg = &lt;&amp;infracfg&gt;;</div><div class='add'>+					#power-domain-cells = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				mfg_async: power-domain@MT8183_POWER_DOMAIN_MFG_ASYNC {</div><div class='add'>+					reg = &lt;MT8183_POWER_DOMAIN_MFG_ASYNC&gt;;</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+					#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					mfg: power-domain@MT8183_POWER_DOMAIN_MFG {</div><div class='add'>+						reg = &lt;MT8183_POWER_DOMAIN_MFG&gt;;</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+						#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						power-domain@MT8183_POWER_DOMAIN_MFG_CORE0 {</div><div class='add'>+							reg = &lt;MT8183_POWER_DOMAIN_MFG_CORE0&gt;;</div><div class='add'>+							#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						power-domain@MT8183_POWER_DOMAIN_MFG_CORE1 {</div><div class='add'>+							reg = &lt;MT8183_POWER_DOMAIN_MFG_CORE1&gt;;</div><div class='add'>+							#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						power-domain@MT8183_POWER_DOMAIN_MFG_2D {</div><div class='add'>+							reg = &lt;MT8183_POWER_DOMAIN_MFG_2D&gt;;</div><div class='add'>+							mediatek,infracfg = &lt;&amp;infracfg&gt;;</div><div class='add'>+							#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				power-domain@MT8183_POWER_DOMAIN_DISP {</div><div class='add'>+					reg = &lt;MT8183_POWER_DOMAIN_DISP&gt;;</div><div class='add'>+					clocks = &lt;&amp;topckgen CLK_TOP_MUX_MM&gt;,</div><div class='add'>+						 &lt;&amp;mmsys CLK_MM_SMI_COMMON&gt;,</div><div class='add'>+						 &lt;&amp;mmsys CLK_MM_SMI_LARB0&gt;,</div><div class='add'>+						 &lt;&amp;mmsys CLK_MM_SMI_LARB1&gt;,</div><div class='add'>+						 &lt;&amp;mmsys CLK_MM_GALS_COMM0&gt;,</div><div class='add'>+						 &lt;&amp;mmsys CLK_MM_GALS_COMM1&gt;,</div><div class='add'>+						 &lt;&amp;mmsys CLK_MM_GALS_CCU2MM&gt;,</div><div class='add'>+						 &lt;&amp;mmsys CLK_MM_GALS_IPU12MM&gt;,</div><div class='add'>+						 &lt;&amp;mmsys CLK_MM_GALS_IMG2MM&gt;,</div><div class='add'>+						 &lt;&amp;mmsys CLK_MM_GALS_CAM2MM&gt;,</div><div class='add'>+						 &lt;&amp;mmsys CLK_MM_GALS_IPU2MM&gt;;</div><div class='add'>+					clock-names = "mm", "mm-0", "mm-1", "mm-2", "mm-3",</div><div class='add'>+						      "mm-4", "mm-5", "mm-6", "mm-7",</div><div class='add'>+						      "mm-8", "mm-9";</div><div class='add'>+					mediatek,infracfg = &lt;&amp;infracfg&gt;;</div><div class='add'>+					mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+					#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					power-domain@MT8183_POWER_DOMAIN_CAM {</div><div class='add'>+						reg = &lt;MT8183_POWER_DOMAIN_CAM&gt;;</div><div class='add'>+						clocks = &lt;&amp;topckgen CLK_TOP_MUX_CAM&gt;,</div><div class='add'>+							 &lt;&amp;camsys CLK_CAM_LARB6&gt;,</div><div class='add'>+							 &lt;&amp;camsys CLK_CAM_LARB3&gt;,</div><div class='add'>+							 &lt;&amp;camsys CLK_CAM_SENINF&gt;,</div><div class='add'>+							 &lt;&amp;camsys CLK_CAM_CAMSV0&gt;,</div><div class='add'>+							 &lt;&amp;camsys CLK_CAM_CAMSV1&gt;,</div><div class='add'>+							 &lt;&amp;camsys CLK_CAM_CAMSV2&gt;,</div><div class='add'>+							 &lt;&amp;camsys CLK_CAM_CCU&gt;;</div><div class='add'>+						clock-names = "cam", "cam-0", "cam-1",</div><div class='add'>+							      "cam-2", "cam-3", "cam-4",</div><div class='add'>+							      "cam-5", "cam-6";</div><div class='add'>+						mediatek,infracfg = &lt;&amp;infracfg&gt;;</div><div class='add'>+						mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					power-domain@MT8183_POWER_DOMAIN_ISP {</div><div class='add'>+						reg = &lt;MT8183_POWER_DOMAIN_ISP&gt;;</div><div class='add'>+						clocks = &lt;&amp;topckgen CLK_TOP_MUX_IMG&gt;,</div><div class='add'>+							 &lt;&amp;imgsys CLK_IMG_LARB5&gt;,</div><div class='add'>+							 &lt;&amp;imgsys CLK_IMG_LARB2&gt;;</div><div class='add'>+						clock-names = "isp", "isp-0", "isp-1";</div><div class='add'>+						mediatek,infracfg = &lt;&amp;infracfg&gt;;</div><div class='add'>+						mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					power-domain@MT8183_POWER_DOMAIN_VDEC {</div><div class='add'>+						reg = &lt;MT8183_POWER_DOMAIN_VDEC&gt;;</div><div class='add'>+						mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					power-domain@MT8183_POWER_DOMAIN_VENC {</div><div class='add'>+						reg = &lt;MT8183_POWER_DOMAIN_VENC&gt;;</div><div class='add'>+						mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					power-domain@MT8183_POWER_DOMAIN_VPU_TOP {</div><div class='add'>+						reg = &lt;MT8183_POWER_DOMAIN_VPU_TOP&gt;;</div><div class='add'>+						clocks = &lt;&amp;topckgen CLK_TOP_MUX_IPU_IF&gt;,</div><div class='add'>+							 &lt;&amp;topckgen CLK_TOP_MUX_DSP&gt;,</div><div class='add'>+							 &lt;&amp;ipu_conn CLK_IPU_CONN_IPU&gt;,</div><div class='add'>+							 &lt;&amp;ipu_conn CLK_IPU_CONN_AHB&gt;,</div><div class='add'>+							 &lt;&amp;ipu_conn CLK_IPU_CONN_AXI&gt;,</div><div class='add'>+							 &lt;&amp;ipu_conn CLK_IPU_CONN_ISP&gt;,</div><div class='add'>+							 &lt;&amp;ipu_conn CLK_IPU_CONN_CAM_ADL&gt;,</div><div class='add'>+							 &lt;&amp;ipu_conn CLK_IPU_CONN_IMG_ADL&gt;;</div><div class='add'>+						clock-names = "vpu", "vpu1", "vpu-0", "vpu-1",</div><div class='add'>+							      "vpu-2", "vpu-3", "vpu-4", "vpu-5";</div><div class='add'>+						mediatek,infracfg = &lt;&amp;infracfg&gt;;</div><div class='add'>+						mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+						#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						power-domain@MT8183_POWER_DOMAIN_VPU_CORE0 {</div><div class='add'>+							reg = &lt;MT8183_POWER_DOMAIN_VPU_CORE0&gt;;</div><div class='add'>+							clocks = &lt;&amp;topckgen CLK_TOP_MUX_DSP1&gt;;</div><div class='add'>+							clock-names = "vpu2";</div><div class='add'>+							mediatek,infracfg = &lt;&amp;infracfg&gt;;</div><div class='add'>+							#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						power-domain@MT8183_POWER_DOMAIN_VPU_CORE1 {</div><div class='add'>+							reg = &lt;MT8183_POWER_DOMAIN_VPU_CORE1&gt;;</div><div class='add'>+							clocks = &lt;&amp;topckgen CLK_TOP_MUX_DSP2&gt;;</div><div class='add'>+							clock-names = "vpu3";</div><div class='add'>+							mediatek,infracfg = &lt;&amp;infracfg&gt;;</div><div class='add'>+							#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		watchdog: watchdog@10007000 {</div><div class='del'>-			compatible = "mediatek,mt8183-wdt",</div><div class='del'>-				     "mediatek,mt6589-wdt";</div><div class='add'>+			compatible = "mediatek,mt8183-wdt";</div><div class='ctx'> 			reg = &lt;0 0x10007000 0 0x100&gt;;</div><div class='ctx'> 			#reset-cells = &lt;1&gt;;</div><div class='ctx'> 		};</div><div class='hunk'>@@ -324,20 +1023,50 @@</div><div class='ctx'> 			clock-names = "spi", "wrap";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		keyboard: keyboard@10010000 {</div><div class='add'>+			compatible = "mediatek,mt8183-keypad",</div><div class='add'>+				     "mediatek,mt6779-keypad";</div><div class='add'>+			reg = &lt;0 0x10010000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 186 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk26m&gt;;</div><div class='add'>+			clock-names = "kpd";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		scp: scp@10500000 {</div><div class='add'>+			compatible = "mediatek,mt8183-scp";</div><div class='add'>+			reg = &lt;0 0x10500000 0 0x80000&gt;,</div><div class='add'>+			      &lt;0 0x105c0000 0 0x19080&gt;;</div><div class='add'>+			reg-names = "sram", "cfg";</div><div class='add'>+			interrupts = &lt;GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_SCPSYS&gt;;</div><div class='add'>+			clock-names = "main";</div><div class='add'>+			memory-region = &lt;&amp;scp_mem_reserved&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		systimer: timer@10017000 {</div><div class='ctx'> 			compatible = "mediatek,mt8183-timer",</div><div class='ctx'> 				     "mediatek,mt6765-timer";</div><div class='ctx'> 			reg = &lt;0 0x10017000 0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;topckgen CLK_TOP_CLK13M&gt;;</div><div class='del'>-			clock-names = "clk13m";</div><div class='add'>+			clocks = &lt;&amp;clk13m&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		iommu: iommu@10205000 {</div><div class='add'>+			compatible = "mediatek,mt8183-m4u";</div><div class='add'>+			reg = &lt;0 0x10205000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 166 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			mediatek,larbs = &lt;&amp;larb0&gt;, &lt;&amp;larb1&gt;, &lt;&amp;larb2&gt;, &lt;&amp;larb3&gt;,</div><div class='add'>+					 &lt;&amp;larb4&gt;, &lt;&amp;larb5&gt;, &lt;&amp;larb6&gt;;</div><div class='add'>+			#iommu-cells = &lt;1&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		gce: mailbox@10238000 {</div><div class='ctx'> 			compatible = "mediatek,mt8183-gce";</div><div class='ctx'> 			reg = &lt;0 0x10238000 0 0x4000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 162 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='del'>-			#mbox-cells = &lt;3&gt;;</div><div class='add'>+			#mbox-cells = &lt;2&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;infracfg CLK_INFRA_GCE&gt;;</div><div class='ctx'> 			clock-names = "gce";</div><div class='ctx'> 		};</div><div class='hunk'>@@ -453,6 +1182,58 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		thermal: thermal-sensor@1100b000 {</div><div class='add'>+			#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+			compatible = "mediatek,mt8183-thermal";</div><div class='add'>+			reg = &lt;0 0x1100b000 0 0xc00&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_THERM&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_AUXADC&gt;;</div><div class='add'>+			clock-names = "therm", "auxadc";</div><div class='add'>+			resets = &lt;&amp;infracfg  MT8183_INFRACFG_AO_THERM_SW_RST&gt;;</div><div class='add'>+			interrupts = &lt;0 76 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			mediatek,auxadc = &lt;&amp;auxadc&gt;;</div><div class='add'>+			mediatek,apmixedsys = &lt;&amp;apmixedsys&gt;;</div><div class='add'>+			nvmem-cells = &lt;&amp;thermal_calibration&gt;;</div><div class='add'>+			nvmem-cell-names = "calibration-data";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		svs: svs@1100bc00 {</div><div class='add'>+			compatible = "mediatek,mt8183-svs";</div><div class='add'>+			reg = &lt;0 0x1100bc00 0 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 127 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_THERM&gt;;</div><div class='add'>+			clock-names = "main";</div><div class='add'>+			nvmem-cells = &lt;&amp;svs_calibration&gt;,</div><div class='add'>+				      &lt;&amp;thermal_calibration&gt;;</div><div class='add'>+			nvmem-cell-names = "svs-calibration-data",</div><div class='add'>+					   "t-calibration-data";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pwm0: pwm@1100e000 {</div><div class='add'>+			compatible = "mediatek,mt8183-disp-pwm";</div><div class='add'>+			reg = &lt;0 0x1100e000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 128 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8183_POWER_DOMAIN_DISP&gt;;</div><div class='add'>+			#pwm-cells = &lt;2&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_MUX_DISP_PWM&gt;,</div><div class='add'>+					&lt;&amp;infracfg CLK_INFRA_DISP_PWM&gt;;</div><div class='add'>+			clock-names = "main", "mm";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pwm1: pwm@11006000 {</div><div class='add'>+			compatible = "mediatek,mt8183-pwm";</div><div class='add'>+			reg = &lt;0 0x11006000 0 0x1000&gt;;</div><div class='add'>+			#pwm-cells = &lt;2&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_PWM&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_PWM_HCLK&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_PWM1&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_PWM2&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_PWM3&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_PWM4&gt;;</div><div class='add'>+			clock-names = "top", "main", "pwm1", "pwm2", "pwm3",</div><div class='add'>+				      "pwm4";</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		i2c3: i2c@1100f000 {</div><div class='ctx'> 			compatible = "mediatek,mt8183-i2c";</div><div class='ctx'> 			reg = &lt;0 0x1100f000 0 0x1000&gt;,</div><div class='hunk'>@@ -634,28 +1415,718 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		audiosys: syscon@11220000 {</div><div class='add'>+		ssusb: usb@11201000 {</div><div class='add'>+			compatible = "mediatek,mt8183-mtu3", "mediatek,mtu3";</div><div class='add'>+			reg = &lt;0 0x11201000 0 0x2e00&gt;,</div><div class='add'>+			      &lt;0 0x11203e00 0 0x0100&gt;;</div><div class='add'>+			reg-names = "mac", "ippc";</div><div class='add'>+			interrupts = &lt;GIC_SPI 72 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			phys = &lt;&amp;u2port0 PHY_TYPE_USB2&gt;,</div><div class='add'>+			       &lt;&amp;u3port0 PHY_TYPE_USB3&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_UNIPRO_SCK&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_USB&gt;;</div><div class='add'>+			clock-names = "sys_ck", "ref_ck";</div><div class='add'>+			mediatek,syscon-wakeup = &lt;&amp;pericfg 0x420 101&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			usb_host: usb@11200000 {</div><div class='add'>+				compatible = "mediatek,mt8183-xhci",</div><div class='add'>+					     "mediatek,mtk-xhci";</div><div class='add'>+				reg = &lt;0 0x11200000 0 0x1000&gt;;</div><div class='add'>+				reg-names = "mac";</div><div class='add'>+				interrupts = &lt;GIC_SPI 73 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+				clocks = &lt;&amp;infracfg CLK_INFRA_UNIPRO_SCK&gt;,</div><div class='add'>+					 &lt;&amp;infracfg CLK_INFRA_USB&gt;;</div><div class='add'>+				clock-names = "sys_ck", "ref_ck";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		audiosys: clock-controller@11220000 {</div><div class='ctx'> 			compatible = "mediatek,mt8183-audiosys", "syscon";</div><div class='ctx'> 			reg = &lt;0 0x11220000 0 0x1000&gt;;</div><div class='ctx'> 			#clock-cells = &lt;1&gt;;</div><div class='add'>+			afe: audio-controller {</div><div class='add'>+				compatible = "mediatek,mt8183-audio";</div><div class='add'>+				interrupts = &lt;GIC_SPI 161 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+				resets = &lt;&amp;watchdog MT8183_TOPRGU_AUDIO_SW_RST&gt;;</div><div class='add'>+				reset-names = "audiosys";</div><div class='add'>+				power-domains =</div><div class='add'>+					&lt;&amp;spm MT8183_POWER_DOMAIN_AUDIO&gt;;</div><div class='add'>+				clocks = &lt;&amp;audiosys CLK_AUDIO_AFE&gt;,</div><div class='add'>+					 &lt;&amp;audiosys CLK_AUDIO_DAC&gt;,</div><div class='add'>+					 &lt;&amp;audiosys CLK_AUDIO_DAC_PREDIS&gt;,</div><div class='add'>+					 &lt;&amp;audiosys CLK_AUDIO_ADC&gt;,</div><div class='add'>+					 &lt;&amp;audiosys CLK_AUDIO_PDN_ADDA6_ADC&gt;,</div><div class='add'>+					 &lt;&amp;audiosys CLK_AUDIO_22M&gt;,</div><div class='add'>+					 &lt;&amp;audiosys CLK_AUDIO_24M&gt;,</div><div class='add'>+					 &lt;&amp;audiosys CLK_AUDIO_APLL_TUNER&gt;,</div><div class='add'>+					 &lt;&amp;audiosys CLK_AUDIO_APLL2_TUNER&gt;,</div><div class='add'>+					 &lt;&amp;audiosys CLK_AUDIO_I2S1&gt;,</div><div class='add'>+					 &lt;&amp;audiosys CLK_AUDIO_I2S2&gt;,</div><div class='add'>+					 &lt;&amp;audiosys CLK_AUDIO_I2S3&gt;,</div><div class='add'>+					 &lt;&amp;audiosys CLK_AUDIO_I2S4&gt;,</div><div class='add'>+					 &lt;&amp;audiosys CLK_AUDIO_TDM&gt;,</div><div class='add'>+					 &lt;&amp;audiosys CLK_AUDIO_TML&gt;,</div><div class='add'>+					 &lt;&amp;infracfg CLK_INFRA_AUDIO&gt;,</div><div class='add'>+					 &lt;&amp;infracfg CLK_INFRA_AUDIO_26M_BCLK&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_MUX_AUDIO&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_MUX_AUD_INTBUS&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_SYSPLL_D2_D4&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_MUX_AUD_1&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_APLL1_CK&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_MUX_AUD_2&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_APLL2_CK&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_MUX_AUD_ENG1&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_APLL1_D8&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_MUX_AUD_ENG2&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_APLL2_D8&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_MUX_APLL_I2S0&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_MUX_APLL_I2S1&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_MUX_APLL_I2S2&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_MUX_APLL_I2S3&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_MUX_APLL_I2S4&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_MUX_APLL_I2S5&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_APLL12_DIV0&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_APLL12_DIV1&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_APLL12_DIV2&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_APLL12_DIV3&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_APLL12_DIV4&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_APLL12_DIVB&gt;,</div><div class='add'>+					 /*&lt;&amp;topckgen CLK_TOP_APLL12_DIV5&gt;,*/</div><div class='add'>+					 &lt;&amp;clk26m&gt;;</div><div class='add'>+				clock-names = "aud_afe_clk",</div><div class='add'>+						  "aud_dac_clk",</div><div class='add'>+						  "aud_dac_predis_clk",</div><div class='add'>+						  "aud_adc_clk",</div><div class='add'>+						  "aud_adc_adda6_clk",</div><div class='add'>+						  "aud_apll22m_clk",</div><div class='add'>+						  "aud_apll24m_clk",</div><div class='add'>+						  "aud_apll1_tuner_clk",</div><div class='add'>+						  "aud_apll2_tuner_clk",</div><div class='add'>+						  "aud_i2s1_bclk_sw",</div><div class='add'>+						  "aud_i2s2_bclk_sw",</div><div class='add'>+						  "aud_i2s3_bclk_sw",</div><div class='add'>+						  "aud_i2s4_bclk_sw",</div><div class='add'>+						  "aud_tdm_clk",</div><div class='add'>+						  "aud_tml_clk",</div><div class='add'>+						  "aud_infra_clk",</div><div class='add'>+						  "mtkaif_26m_clk",</div><div class='add'>+						  "top_mux_audio",</div><div class='add'>+						  "top_mux_aud_intbus",</div><div class='add'>+						  "top_syspll_d2_d4",</div><div class='add'>+						  "top_mux_aud_1",</div><div class='add'>+						  "top_apll1_ck",</div><div class='add'>+						  "top_mux_aud_2",</div><div class='add'>+						  "top_apll2_ck",</div><div class='add'>+						  "top_mux_aud_eng1",</div><div class='add'>+						  "top_apll1_d8",</div><div class='add'>+						  "top_mux_aud_eng2",</div><div class='add'>+						  "top_apll2_d8",</div><div class='add'>+						  "top_i2s0_m_sel",</div><div class='add'>+						  "top_i2s1_m_sel",</div><div class='add'>+						  "top_i2s2_m_sel",</div><div class='add'>+						  "top_i2s3_m_sel",</div><div class='add'>+						  "top_i2s4_m_sel",</div><div class='add'>+						  "top_i2s5_m_sel",</div><div class='add'>+						  "top_apll12_div0",</div><div class='add'>+						  "top_apll12_div1",</div><div class='add'>+						  "top_apll12_div2",</div><div class='add'>+						  "top_apll12_div3",</div><div class='add'>+						  "top_apll12_div4",</div><div class='add'>+						  "top_apll12_divb",</div><div class='add'>+						  /*"top_apll12_div5",*/</div><div class='add'>+						  "top_clk26m_clk";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmc0: mmc@11230000 {</div><div class='add'>+			compatible = "mediatek,mt8183-mmc";</div><div class='add'>+			reg = &lt;0 0x11230000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11f50000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 77 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_MUX_MSDC50_0&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_MSDC0&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_MSDC0_SCK&gt;;</div><div class='add'>+			clock-names = "source", "hclk", "source_cg";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmc1: mmc@11240000 {</div><div class='add'>+			compatible = "mediatek,mt8183-mmc";</div><div class='add'>+			reg = &lt;0 0x11240000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11e10000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 78 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_MUX_MSDC30_1&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_MSDC1&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_MSDC1_SCK&gt;;</div><div class='add'>+			clock-names = "source", "hclk", "source_cg";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mipi_tx0: dsi-phy@11e50000 {</div><div class='add'>+			compatible = "mediatek,mt8183-mipi-tx";</div><div class='add'>+			reg = &lt;0 0x11e50000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;apmixedsys CLK_APMIXED_MIPID0_26M&gt;;</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+			clock-output-names = "mipi_tx0_pll";</div><div class='add'>+			nvmem-cells = &lt;&amp;mipi_tx_calibration&gt;;</div><div class='add'>+			nvmem-cell-names = "calibration-data";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		efuse: efuse@11f10000 {</div><div class='ctx'> 			compatible = "mediatek,mt8183-efuse",</div><div class='ctx'> 				     "mediatek,efuse";</div><div class='ctx'> 			reg = &lt;0 0x11f10000 0 0x1000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			socinfo-data1@4c {</div><div class='add'>+				reg = &lt;0x04c 0x4&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			socinfo-data2@60 {</div><div class='add'>+				reg = &lt;0x060 0x4&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			thermal_calibration: calib@180 {</div><div class='add'>+				reg = &lt;0x180 0xc&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mipi_tx_calibration: calib@190 {</div><div class='add'>+				reg = &lt;0x190 0xc&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			svs_calibration: calib@580 {</div><div class='add'>+				reg = &lt;0x580 0x64&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		u3phy: t-phy@11f40000 {</div><div class='add'>+			compatible = "mediatek,mt8183-tphy",</div><div class='add'>+				     "mediatek,generic-tphy-v2";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges = &lt;0 0 0x11f40000 0x1000&gt;;</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			u2port0: usb-phy@0 {</div><div class='add'>+				reg = &lt;0x0 0x700&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk26m&gt;;</div><div class='add'>+				clock-names = "ref";</div><div class='add'>+				#phy-cells = &lt;1&gt;;</div><div class='add'>+				mediatek,discth = &lt;15&gt;;</div><div class='add'>+				status = "okay";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			u3port0: usb-phy@700 {</div><div class='add'>+				reg = &lt;0x0700 0x900&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk26m&gt;;</div><div class='add'>+				clock-names = "ref";</div><div class='add'>+				#phy-cells = &lt;1&gt;;</div><div class='add'>+				status = "okay";</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		mfgcfg: syscon@13000000 {</div><div class='ctx'> 			compatible = "mediatek,mt8183-mfgcfg", "syscon";</div><div class='ctx'> 			reg = &lt;0 0x13000000 0 0x1000&gt;;</div><div class='ctx'> 			#clock-cells = &lt;1&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8183_POWER_DOMAIN_MFG_ASYNC&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu: gpu@13040000 {</div><div class='add'>+			compatible = "mediatek,mt8183b-mali", "arm,mali-bifrost";</div><div class='add'>+			reg = &lt;0 0x13040000 0 0x4000&gt;;</div><div class='add'>+			interrupts =</div><div class='add'>+				&lt;GIC_SPI 280 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+				&lt;GIC_SPI 279 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+				&lt;GIC_SPI 278 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			interrupt-names = "job", "mmu", "gpu";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;mfgcfg CLK_MFG_BG3D&gt;;</div><div class='add'>+</div><div class='add'>+			power-domains =</div><div class='add'>+				&lt;&amp;spm MT8183_POWER_DOMAIN_MFG_CORE0&gt;,</div><div class='add'>+				&lt;&amp;spm MT8183_POWER_DOMAIN_MFG_CORE1&gt;,</div><div class='add'>+				&lt;&amp;spm MT8183_POWER_DOMAIN_MFG_2D&gt;;</div><div class='add'>+			power-domain-names = "core0", "core1", "core2";</div><div class='add'>+</div><div class='add'>+			operating-points-v2 = &lt;&amp;gpu_opp_table&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		mmsys: syscon@14000000 {</div><div class='ctx'> 			compatible = "mediatek,mt8183-mmsys", "syscon";</div><div class='ctx'> 			reg = &lt;0 0x14000000 0 0x1000&gt;;</div><div class='ctx'> 			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+			mboxes = &lt;&amp;gce 0 CMDQ_THR_PRIO_HIGHEST&gt;,</div><div class='add'>+				 &lt;&amp;gce 1 CMDQ_THR_PRIO_HIGHEST&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1400XXXX 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			port {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				mmsys_ep_main: endpoint@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					remote-endpoint = &lt;&amp;ovl0_in&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				mmsys_ep_ext: endpoint@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					remote-endpoint = &lt;&amp;ovl_2l1_in&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dma-controller0@14001000 {</div><div class='add'>+			compatible = "mediatek,mt8183-mdp3-rdma";</div><div class='add'>+			reg = &lt;0 0x14001000 0 0x1000&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1400XXXX 0x1000 0x1000&gt;;</div><div class='add'>+			mediatek,gce-events = &lt;CMDQ_EVENT_MDP_RDMA0_SOF&gt;,</div><div class='add'>+					      &lt;CMDQ_EVENT_MDP_RDMA0_EOF&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8183_POWER_DOMAIN_DISP&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_MDP_RDMA0&gt;,</div><div class='add'>+				 &lt;&amp;mmsys CLK_MM_MDP_RSZ1&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu M4U_PORT_MDP_RDMA0&gt;;</div><div class='add'>+			mboxes = &lt;&amp;gce 20 CMDQ_THR_PRIO_LOWEST 0&gt;,</div><div class='add'>+				 &lt;&amp;gce 21 CMDQ_THR_PRIO_LOWEST 0&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdp3-rsz0@14003000 {</div><div class='add'>+			compatible = "mediatek,mt8183-mdp3-rsz";</div><div class='add'>+			reg = &lt;0 0x14003000 0 0x1000&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1400XXXX 0x3000 0x1000&gt;;</div><div class='add'>+			mediatek,gce-events = &lt;CMDQ_EVENT_MDP_RSZ0_SOF&gt;,</div><div class='add'>+					      &lt;CMDQ_EVENT_MDP_RSZ0_EOF&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_MDP_RSZ0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdp3-rsz1@14004000 {</div><div class='add'>+			compatible = "mediatek,mt8183-mdp3-rsz";</div><div class='add'>+			reg = &lt;0 0x14004000 0 0x1000&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1400XXXX 0x4000 0x1000&gt;;</div><div class='add'>+			mediatek,gce-events = &lt;CMDQ_EVENT_MDP_RSZ1_SOF&gt;,</div><div class='add'>+					      &lt;CMDQ_EVENT_MDP_RSZ1_EOF&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_MDP_RSZ1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dma-controller@14005000 {</div><div class='add'>+			compatible = "mediatek,mt8183-mdp3-wrot";</div><div class='add'>+			reg = &lt;0 0x14005000 0 0x1000&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1400XXXX 0x5000 0x1000&gt;;</div><div class='add'>+			mediatek,gce-events = &lt;CMDQ_EVENT_MDP_WROT0_SOF&gt;,</div><div class='add'>+					      &lt;CMDQ_EVENT_MDP_WROT0_EOF&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8183_POWER_DOMAIN_DISP&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_MDP_WROT0&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu M4U_PORT_MDP_WROT0&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdp3-wdma@14006000 {</div><div class='add'>+			compatible = "mediatek,mt8183-mdp3-wdma";</div><div class='add'>+			reg = &lt;0 0x14006000 0 0x1000&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1400XXXX 0x6000 0x1000&gt;;</div><div class='add'>+			mediatek,gce-events = &lt;CMDQ_EVENT_MDP_WDMA0_SOF&gt;,</div><div class='add'>+					      &lt;CMDQ_EVENT_MDP_WDMA0_EOF&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8183_POWER_DOMAIN_DISP&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_MDP_WDMA0&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu M4U_PORT_MDP_WDMA0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ovl0: ovl@14008000 {</div><div class='add'>+			compatible = "mediatek,mt8183-disp-ovl";</div><div class='add'>+			reg = &lt;0 0x14008000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 225 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8183_POWER_DOMAIN_DISP&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_OVL0&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu M4U_PORT_DISP_OVL0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1400XXXX 0x8000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					ovl0_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mmsys_ep_main&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					ovl0_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ovl_2l0_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ovl_2l0: ovl@14009000 {</div><div class='add'>+			compatible = "mediatek,mt8183-disp-ovl-2l";</div><div class='add'>+			reg = &lt;0 0x14009000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 226 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8183_POWER_DOMAIN_DISP&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_OVL0_2L&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu M4U_PORT_DISP_2L_OVL0_LARB0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1400XXXX 0x9000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					ovl_2l0_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ovl0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					ovl_2l0_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;rdma0_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ovl_2l1: ovl@1400a000 {</div><div class='add'>+			compatible = "mediatek,mt8183-disp-ovl-2l";</div><div class='add'>+			reg = &lt;0 0x1400a000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 227 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8183_POWER_DOMAIN_DISP&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_OVL1_2L&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu M4U_PORT_DISP_2L_OVL1_LARB0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1400XXXX 0xa000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					ovl_2l1_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mmsys_ep_ext&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					ovl_2l1_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;rdma1_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rdma0: rdma@1400b000 {</div><div class='add'>+			compatible = "mediatek,mt8183-disp-rdma";</div><div class='add'>+			reg = &lt;0 0x1400b000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 228 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8183_POWER_DOMAIN_DISP&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_RDMA0&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu M4U_PORT_DISP_RDMA0&gt;;</div><div class='add'>+			mediatek,rdma-fifo-size = &lt;5120&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1400XXXX 0xb000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					rdma0_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ovl_2l0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					rdma0_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;color0_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rdma1: rdma@1400c000 {</div><div class='add'>+			compatible = "mediatek,mt8183-disp-rdma";</div><div class='add'>+			reg = &lt;0 0x1400c000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 229 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8183_POWER_DOMAIN_DISP&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_RDMA1&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu M4U_PORT_DISP_RDMA1&gt;;</div><div class='add'>+			mediatek,rdma-fifo-size = &lt;2048&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1400XXXX 0xc000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					rdma1_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ovl_2l1_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					rdma1_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dpi_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		color0: color@1400e000 {</div><div class='add'>+			compatible = "mediatek,mt8183-disp-color",</div><div class='add'>+				     "mediatek,mt8173-disp-color";</div><div class='add'>+			reg = &lt;0 0x1400e000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 231 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8183_POWER_DOMAIN_DISP&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_COLOR0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1400XXXX 0xe000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					color0_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;rdma0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					color0_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ccorr0_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ccorr0: ccorr@1400f000 {</div><div class='add'>+			compatible = "mediatek,mt8183-disp-ccorr";</div><div class='add'>+			reg = &lt;0 0x1400f000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 232 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8183_POWER_DOMAIN_DISP&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_CCORR0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1400XXXX 0xf000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					ccorr0_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;color0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					ccorr0_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;aal0_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aal0: aal@14010000 {</div><div class='add'>+			compatible = "mediatek,mt8183-disp-aal";</div><div class='add'>+			reg = &lt;0 0x14010000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 233 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8183_POWER_DOMAIN_DISP&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_AAL0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1401XXXX 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					aal0_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ccorr0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					aal0_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;gamma0_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gamma0: gamma@14011000 {</div><div class='add'>+			compatible = "mediatek,mt8183-disp-gamma";</div><div class='add'>+			reg = &lt;0 0x14011000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 234 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8183_POWER_DOMAIN_DISP&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_GAMMA0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1401XXXX 0x1000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					gamma0_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;aal0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					gamma0_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dither0_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dither0: dither@14012000 {</div><div class='add'>+			compatible = "mediatek,mt8183-disp-dither";</div><div class='add'>+			reg = &lt;0 0x14012000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 235 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8183_POWER_DOMAIN_DISP&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_DITHER0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1401XXXX 0x2000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					dither0_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;gamma0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					dither0_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dsi_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dsi0: dsi@14014000 {</div><div class='add'>+			compatible = "mediatek,mt8183-dsi";</div><div class='add'>+			reg = &lt;0 0x14014000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 236 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8183_POWER_DOMAIN_DISP&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DSI0_MM&gt;,</div><div class='add'>+				 &lt;&amp;mmsys CLK_MM_DSI0_IF&gt;,</div><div class='add'>+				 &lt;&amp;mipi_tx0&gt;;</div><div class='add'>+			clock-names = "engine", "digital", "hs";</div><div class='add'>+			resets = &lt;&amp;mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0&gt;;</div><div class='add'>+			phys = &lt;&amp;mipi_tx0&gt;;</div><div class='add'>+			phy-names = "dphy";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					dsi_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dither0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					dsi_out: endpoint { };</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dpi0: dpi@14015000 {</div><div class='add'>+			compatible = "mediatek,mt8183-dpi";</div><div class='add'>+			reg = &lt;0 0x14015000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 237 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8183_POWER_DOMAIN_DISP&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DPI_IF&gt;,</div><div class='add'>+				 &lt;&amp;mmsys CLK_MM_DPI_MM&gt;,</div><div class='add'>+				 &lt;&amp;apmixedsys CLK_APMIXED_TVDPLL&gt;;</div><div class='add'>+			clock-names = "pixel", "engine", "pll";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					dpi_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;rdma1_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					dpi_out: endpoint { };</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mutex: mutex@14016000 {</div><div class='add'>+			compatible = "mediatek,mt8183-disp-mutex";</div><div class='add'>+			reg = &lt;0 0x14016000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 217 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8183_POWER_DOMAIN_DISP&gt;;</div><div class='add'>+			mediatek,gce-events = &lt;CMDQ_EVENT_MUTEX_STREAM_DONE0&gt;,</div><div class='add'>+					      &lt;CMDQ_EVENT_MUTEX_STREAM_DONE1&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1401XXXX 0x6000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb0: larb@14017000 {</div><div class='add'>+			compatible = "mediatek,mt8183-smi-larb";</div><div class='add'>+			reg = &lt;0 0x14017000 0 0x1000&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_SMI_LARB0&gt;,</div><div class='add'>+				 &lt;&amp;mmsys CLK_MM_SMI_LARB0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8183_POWER_DOMAIN_DISP&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smi_common: smi@14019000 {</div><div class='add'>+			compatible = "mediatek,mt8183-smi-common";</div><div class='add'>+			reg = &lt;0 0x14019000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_SMI_COMMON&gt;,</div><div class='add'>+				 &lt;&amp;mmsys CLK_MM_SMI_COMMON&gt;,</div><div class='add'>+				 &lt;&amp;mmsys CLK_MM_GALS_COMM0&gt;,</div><div class='add'>+				 &lt;&amp;mmsys CLK_MM_GALS_COMM1&gt;;</div><div class='add'>+			clock-names = "apb", "smi", "gals0", "gals1";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8183_POWER_DOMAIN_DISP&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdp3-ccorr@1401c000 {</div><div class='add'>+			compatible = "mediatek,mt8183-mdp3-ccorr";</div><div class='add'>+			reg = &lt;0 0x1401c000 0 0x1000&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1401XXXX 0xc000 0x1000&gt;;</div><div class='add'>+			mediatek,gce-events = &lt;CMDQ_EVENT_MDP_CCORR_SOF&gt;,</div><div class='add'>+					      &lt;CMDQ_EVENT_MDP_CCORR_EOF&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_MDP_CCORR&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		imgsys: syscon@15020000 {</div><div class='hunk'>@@ -664,18 +2135,115 @@</div><div class='ctx'> 			#clock-cells = &lt;1&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		larb5: larb@15021000 {</div><div class='add'>+			compatible = "mediatek,mt8183-smi-larb";</div><div class='add'>+			reg = &lt;0 0x15021000 0 0x1000&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+			clocks = &lt;&amp;imgsys CLK_IMG_LARB5&gt;, &lt;&amp;imgsys CLK_IMG_LARB5&gt;,</div><div class='add'>+				 &lt;&amp;mmsys CLK_MM_GALS_IMG2MM&gt;;</div><div class='add'>+			clock-names = "apb", "smi", "gals";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8183_POWER_DOMAIN_ISP&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb2: larb@1502f000 {</div><div class='add'>+			compatible = "mediatek,mt8183-smi-larb";</div><div class='add'>+			reg = &lt;0 0x1502f000 0 0x1000&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+			clocks = &lt;&amp;imgsys CLK_IMG_LARB2&gt;, &lt;&amp;imgsys CLK_IMG_LARB2&gt;,</div><div class='add'>+				 &lt;&amp;mmsys CLK_MM_GALS_IPU2MM&gt;;</div><div class='add'>+			clock-names = "apb", "smi", "gals";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8183_POWER_DOMAIN_ISP&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		vdecsys: syscon@16000000 {</div><div class='ctx'> 			compatible = "mediatek,mt8183-vdecsys", "syscon";</div><div class='ctx'> 			reg = &lt;0 0x16000000 0 0x1000&gt;;</div><div class='ctx'> 			#clock-cells = &lt;1&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		vcodec_dec: video-codec@16020000 {</div><div class='add'>+			compatible = "mediatek,mt8183-vcodec-dec";</div><div class='add'>+			reg = &lt;0 0x16020000 0 0x1000&gt;,		/* VDEC_MISC */</div><div class='add'>+			      &lt;0 0x16021000 0 0x800&gt;,		/* VDEC_VLD */</div><div class='add'>+			      &lt;0 0x16021800 0 0x800&gt;,		/* VDEC_TOP */</div><div class='add'>+			      &lt;0 0x16022000 0 0x1000&gt;,		/* VDEC_MC */</div><div class='add'>+			      &lt;0 0x16023000 0 0x1000&gt;,		/* VDEC_AVCVLD */</div><div class='add'>+			      &lt;0 0x16024000 0 0x1000&gt;,		/* VDEC_AVCMV */</div><div class='add'>+			      &lt;0 0x16025000 0 0x1000&gt;,		/* VDEC_PP */</div><div class='add'>+			      &lt;0 0x16026800 0 0x800&gt;,		/* VP8_VD */</div><div class='add'>+			      &lt;0 0x16027000 0 0x800&gt;,		/* VP6_VD */</div><div class='add'>+			      &lt;0 0x16027800 0 0x800&gt;,		/* VP8_VL */</div><div class='add'>+			      &lt;0 0x16028400 0 0x400&gt;;		/* VP9_VD */</div><div class='add'>+			reg-names = "misc", "ld", "top", "cm", "ad", "av", "pp",</div><div class='add'>+				    "hwd", "hwq", "hwb", "hwg";</div><div class='add'>+			interrupts = &lt;GIC_SPI 250 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu M4U_PORT_HW_VDEC_MC_EXT&gt;,</div><div class='add'>+				 &lt;&amp;iommu M4U_PORT_HW_VDEC_PP_EXT&gt;,</div><div class='add'>+				 &lt;&amp;iommu M4U_PORT_HW_VDEC_VLD_EXT&gt;,</div><div class='add'>+				 &lt;&amp;iommu M4U_PORT_HW_VDEC_AVC_MV_EXT&gt;,</div><div class='add'>+				 &lt;&amp;iommu M4U_PORT_HW_VDEC_PRED_RD_EXT&gt;,</div><div class='add'>+				 &lt;&amp;iommu M4U_PORT_HW_VDEC_PRED_WR_EXT&gt;,</div><div class='add'>+				 &lt;&amp;iommu M4U_PORT_HW_VDEC_PPWRAP_EXT&gt;;</div><div class='add'>+			mediatek,scp = &lt;&amp;scp&gt;;</div><div class='add'>+			mediatek,vdecsys = &lt;&amp;vdecsys&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8183_POWER_DOMAIN_VDEC&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdecsys CLK_VDEC_VDEC&gt;;</div><div class='add'>+			clock-names = "vdec";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb1: larb@16010000 {</div><div class='add'>+			compatible = "mediatek,mt8183-smi-larb";</div><div class='add'>+			reg = &lt;0 0x16010000 0 0x1000&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdecsys CLK_VDEC_VDEC&gt;, &lt;&amp;vdecsys CLK_VDEC_LARB1&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8183_POWER_DOMAIN_VDEC&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		vencsys: syscon@17000000 {</div><div class='ctx'> 			compatible = "mediatek,mt8183-vencsys", "syscon";</div><div class='ctx'> 			reg = &lt;0 0x17000000 0 0x1000&gt;;</div><div class='ctx'> 			#clock-cells = &lt;1&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		larb4: larb@17010000 {</div><div class='add'>+			compatible = "mediatek,mt8183-smi-larb";</div><div class='add'>+			reg = &lt;0 0x17010000 0 0x1000&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+			clocks = &lt;&amp;vencsys CLK_VENC_LARB&gt;,</div><div class='add'>+				 &lt;&amp;vencsys CLK_VENC_LARB&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8183_POWER_DOMAIN_VENC&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vcodec_enc: vcodec@17020000 {</div><div class='add'>+			compatible = "mediatek,mt8183-vcodec-enc";</div><div class='add'>+			reg = &lt;0 0x17020000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 247 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu M4U_PORT_VENC_REC&gt;,</div><div class='add'>+				 &lt;&amp;iommu M4U_PORT_VENC_BSDMA&gt;,</div><div class='add'>+				 &lt;&amp;iommu M4U_PORT_VENC_RD_COMV&gt;,</div><div class='add'>+				 &lt;&amp;iommu M4U_PORT_VENC_CUR_LUMA&gt;,</div><div class='add'>+				 &lt;&amp;iommu M4U_PORT_VENC_CUR_CHROMA&gt;,</div><div class='add'>+				 &lt;&amp;iommu M4U_PORT_VENC_REF_LUMA&gt;,</div><div class='add'>+				 &lt;&amp;iommu M4U_PORT_VENC_REF_CHROMA&gt;;</div><div class='add'>+			mediatek,scp = &lt;&amp;scp&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8183_POWER_DOMAIN_VENC&gt;;</div><div class='add'>+			clocks = &lt;&amp;vencsys CLK_VENC_VENC&gt;;</div><div class='add'>+			clock-names = "venc_sel";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		venc_jpg: jpeg-encoder@17030000 {</div><div class='add'>+			compatible = "mediatek,mt8183-jpgenc", "mediatek,mtk-jpgenc";</div><div class='add'>+			reg = &lt;0 0x17030000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 249 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu M4U_PORT_JPGENC_RDMA&gt;,</div><div class='add'>+				 &lt;&amp;iommu M4U_PORT_JPGENC_BSDMA&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8183_POWER_DOMAIN_VENC&gt;;</div><div class='add'>+			clocks = &lt;&amp;vencsys CLK_VENC_JPGENC&gt;;</div><div class='add'>+			clock-names = "jpgenc";</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		ipu_conn: syscon@19000000 {</div><div class='ctx'> 			compatible = "mediatek,mt8183-ipu_conn", "syscon";</div><div class='ctx'> 			reg = &lt;0 0x19000000 0 0x1000&gt;;</div><div class='hunk'>@@ -705,5 +2273,214 @@</div><div class='ctx'> 			reg = &lt;0 0x1a000000 0 0x1000&gt;;</div><div class='ctx'> 			#clock-cells = &lt;1&gt;;</div><div class='ctx'> 		};</div><div class='add'>+</div><div class='add'>+		larb6: larb@1a001000 {</div><div class='add'>+			compatible = "mediatek,mt8183-smi-larb";</div><div class='add'>+			reg = &lt;0 0x1a001000 0 0x1000&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+			clocks = &lt;&amp;camsys CLK_CAM_LARB6&gt;, &lt;&amp;camsys CLK_CAM_LARB6&gt;,</div><div class='add'>+				 &lt;&amp;mmsys CLK_MM_GALS_CAM2MM&gt;;</div><div class='add'>+			clock-names = "apb", "smi", "gals";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8183_POWER_DOMAIN_CAM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb3: larb@1a002000 {</div><div class='add'>+			compatible = "mediatek,mt8183-smi-larb";</div><div class='add'>+			reg = &lt;0 0x1a002000 0 0x1000&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+			clocks = &lt;&amp;camsys CLK_CAM_LARB3&gt;, &lt;&amp;camsys CLK_CAM_LARB3&gt;,</div><div class='add'>+				 &lt;&amp;mmsys CLK_MM_GALS_IPU12MM&gt;;</div><div class='add'>+			clock-names = "apb", "smi", "gals";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8183_POWER_DOMAIN_CAM&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	thermal_zones: thermal-zones {</div><div class='add'>+		cpu_thermal: cpu-thermal {</div><div class='add'>+			polling-delay-passive = &lt;100&gt;;</div><div class='add'>+			polling-delay = &lt;500&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;thermal 0&gt;;</div><div class='add'>+			sustainable-power = &lt;5000&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				threshold: trip-point0 {</div><div class='add'>+					temperature = &lt;68000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				target: trip-point1 {</div><div class='add'>+					temperature = &lt;80000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_crit: cpu-crit {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;target&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu0</div><div class='add'>+						THERMAL_NO_LIMIT</div><div class='add'>+						THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu1</div><div class='add'>+						THERMAL_NO_LIMIT</div><div class='add'>+						THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu2</div><div class='add'>+						THERMAL_NO_LIMIT</div><div class='add'>+						THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu3</div><div class='add'>+						THERMAL_NO_LIMIT</div><div class='add'>+						THERMAL_NO_LIMIT&gt;;</div><div class='add'>+					contribution = &lt;3072&gt;;</div><div class='add'>+				};</div><div class='add'>+				map1 {</div><div class='add'>+					trip = &lt;&amp;target&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu4</div><div class='add'>+						THERMAL_NO_LIMIT</div><div class='add'>+						THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu5</div><div class='add'>+						THERMAL_NO_LIMIT</div><div class='add'>+						THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu6</div><div class='add'>+						THERMAL_NO_LIMIT</div><div class='add'>+						THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu7</div><div class='add'>+						THERMAL_NO_LIMIT</div><div class='add'>+						THERMAL_NO_LIMIT&gt;;</div><div class='add'>+					contribution = &lt;1024&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tzts1: soc-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;thermal 1&gt;;</div><div class='add'>+			sustainable-power = &lt;5000&gt;;</div><div class='add'>+			trips {</div><div class='add'>+				soc_alert: trip-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				soc_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tzts2: gpu-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;thermal 2&gt;;</div><div class='add'>+			sustainable-power = &lt;5000&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				gpu_alert: trip-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpu_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tzts3: md1-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;thermal 3&gt;;</div><div class='add'>+			sustainable-power = &lt;5000&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				md1_alert: trip-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				md1_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tzts4: cpu-little-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;thermal 4&gt;;</div><div class='add'>+			sustainable-power = &lt;5000&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpul_alert: trip-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpul_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tzts5: cpu-big-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;thermal 5&gt;;</div><div class='add'>+			sustainable-power = &lt;5000&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpub_alert: trip-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpub_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tztsABB: tsabb-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;thermal 6&gt;;</div><div class='add'>+			sustainable-power = &lt;5000&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				tsabb_alert: trip-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tsabb_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou-sku0.dts b/arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou-sku0.dts<br/>new file mode 100644<br/>index 000000000000..5d012bc4ff0d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou-sku0.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou-sku0.dts</a></div><div class='hunk'>@@ -0,0 +1,18 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8186-corsola-chinchou.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google chinchou CZ1104CM2A/CZ1204CM2A";</div><div class='add'>+	compatible = "google,chinchou-sku0", "google,chinchou-sku2",</div><div class='add'>+			"google,chinchou-sku4", "google,chinchou-sku5",</div><div class='add'>+			"google,chinchou", "mediatek,mt8186";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio_keys {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou-sku1.dts b/arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou-sku1.dts<br/>new file mode 100644<br/>index 000000000000..9d6e62af6944<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou-sku1.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou-sku1.dts</a></div><div class='hunk'>@@ -0,0 +1,35 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8186-corsola-chinchou.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google chinchou CZ1104FM2A/CZ1204FM2A/CZ1104CM2A/CZ1204CM2A";</div><div class='add'>+	compatible = "google,chinchou-sku1", "google,chinchou-sku3",</div><div class='add'>+			"google,chinchou-sku6", "google,chinchou-sku7",</div><div class='add'>+			"google,chinchou-sku17", "google,chinchou-sku20",</div><div class='add'>+			"google,chinchou-sku22", "google,chinchou-sku23",</div><div class='add'>+			"google,chinchou", "mediatek,mt8186";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio_keys {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	i2c-scl-internal-delay-ns = &lt;10000&gt;;</div><div class='add'>+</div><div class='add'>+	touchscreen: touchscreen@41 {</div><div class='add'>+		compatible = "ilitek,ili2901";</div><div class='add'>+		reg = &lt;0x41&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 12 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;touchscreen_pins&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pio 60 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		vccio-supply = &lt;&amp;pp1800_tchscr_report_disable&gt;;</div><div class='add'>+		vcc33-supply = &lt;&amp;pp3300_z2&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou-sku16.dts b/arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou-sku16.dts<br/>new file mode 100644<br/>index 000000000000..eb377de1fcde<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou-sku16.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou-sku16.dts</a></div><div class='hunk'>@@ -0,0 +1,29 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8186-corsola-chinchou.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google chinchou CZ1104FM2A/CZ1204FM2A";</div><div class='add'>+	compatible = "google,chinchou-sku16", "google,chinchou-sku18",</div><div class='add'>+			"google,chinchou-sku19", "google,chinchou-sku21",</div><div class='add'>+			"google,chinchou", "mediatek,mt8186";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	i2c-scl-internal-delay-ns = &lt;10000&gt;;</div><div class='add'>+</div><div class='add'>+	touchscreen: touchscreen@41 {</div><div class='add'>+		compatible = "ilitek,ili2901";</div><div class='add'>+		reg = &lt;0x41&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 12 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;touchscreen_pins&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pio 60 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		vccio-supply = &lt;&amp;pp1800_tchscr_report_disable&gt;;</div><div class='add'>+		vcc33-supply = &lt;&amp;pp3300_z2&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou.dtsi b/arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou.dtsi<br/>new file mode 100644<br/>index 000000000000..800792157021<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou.dtsi</a></div><div class='hunk'>@@ -0,0 +1,321 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8186-corsola.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	/delete-node/ speaker-codec;</div><div class='add'>+</div><div class='add'>+	pp1000_edpbrdg: regulator-pp1000-edpbrdg {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "pp1000_edpbrdg";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;en_pp1000_edpbrdg&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		gpio = &lt;&amp;pio 29 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;pp3300_z2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pp1800_edpbrdg_dx: regulator-pp1800-edpbrdg-dx {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "pp1800_edpbrdg_dx";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;en_pp1800_edpbrdg&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		gpio = &lt;&amp;pio 30 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;mt6366_vio18_reg&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pp3300_edp_dx: regulator-pp3300-edp-dx {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "pp3300_edp_dx";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;en_pp3300_edpbrdg&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		gpio = &lt;&amp;pio 31 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;pp3300_z2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pp1800_tchscr_report_disable: regulator-pp1800-tchscr-report-disable {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "pp1800_tchscr_report_disable";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		pinctrl-0 = &lt;&amp;touch_pin_report&gt;;</div><div class='add'>+		gpio = &lt;&amp;pio 37 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsi_out {</div><div class='add'>+	remote-endpoint = &lt;&amp;anx7625_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+</div><div class='add'>+	anx_bridge: anx7625@58 {</div><div class='add'>+		compatible = "analogix,anx7625";</div><div class='add'>+		reg = &lt;0x58&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;anx7625_pins&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;pio 96 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pio 98 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		vdd10-supply = &lt;&amp;pp1000_edpbrdg&gt;;</div><div class='add'>+		vdd18-supply = &lt;&amp;pp1800_edpbrdg_dx&gt;;</div><div class='add'>+		vdd33-supply = &lt;&amp;pp3300_edp_dx&gt;;</div><div class='add'>+		analogix,lane0-swing = /bits/ 8 &lt;0x70 0x30&gt;;</div><div class='add'>+		analogix,lane1-swing = /bits/ 8 &lt;0x70 0x30&gt;;</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				anx7625_in: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;dsi_out&gt;;</div><div class='add'>+					data-lanes = &lt;0 1 2 3&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				anx7625_out: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;panel_in&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aux-bus {</div><div class='add'>+			panel: panel {</div><div class='add'>+				compatible = "edp-panel";</div><div class='add'>+				power-supply = &lt;&amp;pp3300_disp_x&gt;;</div><div class='add'>+				backlight = &lt;&amp;backlight_lcd0&gt;;</div><div class='add'>+</div><div class='add'>+				port {</div><div class='add'>+					panel_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;anx7625_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	/delete-node/ trackpad@15;</div><div class='add'>+</div><div class='add'>+	touchpad@15 {</div><div class='add'>+		compatible = "hid-over-i2c";</div><div class='add'>+		reg = &lt;0x15&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 11 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		post-power-on-delay-ms = &lt;10&gt;;</div><div class='add'>+		hid-descr-addr = &lt;0x0001&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;pp3300_s3&gt;;</div><div class='add'>+		wakeup-source;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c5 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	/delete-node/ codec@1a;</div><div class='add'>+</div><div class='add'>+	rt5650: rt5650@1a {</div><div class='add'>+		compatible = "realtek,rt5650";</div><div class='add'>+		reg = &lt;0x1a&gt;;</div><div class='add'>+		avdd-supply = &lt;&amp;mt6366_vio18_reg&gt;;</div><div class='add'>+		cpvdd-supply = &lt;&amp;mt6366_vio18_reg&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;speaker_codec_pins_default&gt;;</div><div class='add'>+		cbj-sleeve-gpios = &lt;&amp;pio 150 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;pio&gt;;</div><div class='add'>+		interrupts = &lt;17 IRQ_TYPE_EDGE_BOTH&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		realtek,dmic1-data-pin = &lt;2&gt;;</div><div class='add'>+		realtek,jd-mode = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c_tunnel {</div><div class='add'>+	/delete-node/ sbs-battery@b;</div><div class='add'>+</div><div class='add'>+	battery: sbs-battery@f {</div><div class='add'>+		compatible = "sbs,sbs-battery";</div><div class='add'>+		reg = &lt;0xf&gt;;</div><div class='add'>+		sbs,i2c-retry-count = &lt;2&gt;;</div><div class='add'>+		sbs,poll-retry-count = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;keyboard_controller {</div><div class='add'>+	keypad,num-columns = &lt;15&gt;;</div><div class='add'>+</div><div class='add'>+	function-row-physmap = &lt;</div><div class='add'>+		MATRIX_KEY(0x00, 0x02, 0)        /* T1 */</div><div class='add'>+		MATRIX_KEY(0x03, 0x02, 0)        /* T2 */</div><div class='add'>+		MATRIX_KEY(0x02, 0x02, 0)        /* T3 */</div><div class='add'>+		MATRIX_KEY(0x01, 0x02, 0)        /* T4 */</div><div class='add'>+		MATRIX_KEY(0x03, 0x04, 0)        /* T5 */</div><div class='add'>+		MATRIX_KEY(0x02, 0x04, 0)        /* T6 */</div><div class='add'>+		MATRIX_KEY(0x01, 0x04, 0)        /* T7 */</div><div class='add'>+		MATRIX_KEY(0x02, 0x09, 0)        /* T8 */</div><div class='add'>+		MATRIX_KEY(0x01, 0x09, 0)        /* T9 */</div><div class='add'>+		MATRIX_KEY(0x00, 0x04, 0)        /* T10 */</div><div class='add'>+		MATRIX_KEY(0x00, 0x01, 0)        /* T11 */</div><div class='add'>+		MATRIX_KEY(0x01, 0x05, 0)        /* T12 */</div><div class='add'>+	&gt;;</div><div class='add'>+</div><div class='add'>+	linux,keymap = &lt;</div><div class='add'>+		CROS_STD_MAIN_KEYMAP</div><div class='add'>+		MATRIX_KEY(0x00, 0x02, KEY_BACK)           /* T1 */</div><div class='add'>+		MATRIX_KEY(0x03, 0x02, KEY_REFRESH)        /* T2 */</div><div class='add'>+		MATRIX_KEY(0x02, 0x02, KEY_ZOOM)           /* T3 */</div><div class='add'>+		MATRIX_KEY(0x01, 0x02, KEY_SCALE)          /* T4 */</div><div class='add'>+		MATRIX_KEY(0x03, 0x04, KEY_SYSRQ)          /* T5 */</div><div class='add'>+		MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) /* T6 */</div><div class='add'>+		MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP)   /* T7 */</div><div class='add'>+		MATRIX_KEY(0x02, 0x09, KEY_MUTE)           /* T8 */</div><div class='add'>+		MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)	   /* T9 */</div><div class='add'>+		MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)	   /* T10 */</div><div class='add'>+		MATRIX_KEY(0x00, 0x01, KEY_MICMUTE)        /* T11 */</div><div class='add'>+		MATRIX_KEY(0x01, 0x05, KEY_CONTROLPANEL)   /* T12 */</div><div class='add'>+		MATRIX_KEY(0x03, 0x05, KEY_PREVIOUSSONG)   /* T13 */</div><div class='add'>+		MATRIX_KEY(0x00, 0x09, KEY_PLAYPAUSE)	   /* T14 */</div><div class='add'>+		MATRIX_KEY(0x00, 0x0b, KEY_NEXTSONG)	   /* T15 */</div><div class='add'>+		MATRIX_KEY(0x03, 0x00, KEY_LEFTMETA)	   /* Search*/</div><div class='add'>+		MATRIX_KEY(0x01, 0x0e, KEY_LEFTCTRL)	   /* Left Control*/</div><div class='add'>+		MATRIX_KEY(0x06, 0x0d, KEY_LEFTALT)        /* Left ALT*/</div><div class='add'>+		MATRIX_KEY(0x03, 0x0e, KEY_RIGHTCTRL)      /* Right Control*/</div><div class='add'>+		MATRIX_KEY(0x06, 0x0a, KEY_BACKSLASH)      /* BACKSLASH*/</div><div class='add'>+	&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc1_pins_default {</div><div class='add'>+	pins-clk {</div><div class='add'>+		drive-strength = &lt;8&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pins-cmd-dat {</div><div class='add'>+		drive-strength = &lt;8&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc1_pins_uhs {</div><div class='add'>+	pins-clk {</div><div class='add'>+		drive-strength = &lt;8&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pins-cmd-dat {</div><div class='add'>+		drive-strength = &lt;8&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pen_insert {</div><div class='add'>+	wakeup-event-action = &lt;EV_ACT_ANY&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	anx7625_pins: anx7625-pins {</div><div class='add'>+		pins-int {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO9__FUNC_GPIO9&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-reset {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO98__FUNC_GPIO98&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-power-en {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO96__FUNC_GPIO96&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	en_pp1000_edpbrdg: pp1000-edpbrdg-en-pins {</div><div class='add'>+		pins-vreg-en {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO29__FUNC_GPIO29&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	en_pp1800_edpbrdg: pp1800-edpbrdg-en-pins {</div><div class='add'>+		pins-vreg-en {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO30__FUNC_GPIO30&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	en_pp3300_edpbrdg: pp3300-edpbrdg-en-pins {</div><div class='add'>+		pins-vreg-en {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO31__FUNC_GPIO31&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	touch_pin_report: pin-report-pins {</div><div class='add'>+		pins-touch-en {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO37__FUNC_GPIO37&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sound {</div><div class='add'>+	compatible = "mediatek,mt8186-mt6366-rt5650-sound";</div><div class='add'>+	model = "mt8186_rt5650";</div><div class='add'>+	mediatek,adsp = &lt;&amp;adsp&gt;;</div><div class='add'>+</div><div class='add'>+	audio-routing =</div><div class='add'>+		"Headphone", "HPOL",</div><div class='add'>+		"Headphone", "HPOR",</div><div class='add'>+		"IN1P", "Headset Mic",</div><div class='add'>+		"IN1N", "Headset Mic",</div><div class='add'>+		"Speakers", "SPOL",</div><div class='add'>+		"Speakers", "SPOR",</div><div class='add'>+		"HDMI1", "TX";</div><div class='add'>+</div><div class='add'>+	hs-playback-dai-link {</div><div class='add'>+		codec {</div><div class='add'>+			sound-dai = &lt;&amp;rt5650&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hs-capture-dai-link {</div><div class='add'>+		codec {</div><div class='add'>+			sound-dai = &lt;&amp;rt5650&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spk-share-dai-link {</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spk-hdmi-playback-dai-link {</div><div class='add'>+		codec {</div><div class='add'>+			sound-dai = &lt;&amp;it6505dptx&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;touchscreen_pins {</div><div class='add'>+	/delete-node/ pins-report-sw;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wifi_enable_pin {</div><div class='add'>+	pins-wifi-enable {</div><div class='add'>+		pinmux = &lt;PINMUX_GPIO51__FUNC_GPIO51&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wifi_pwrseq {</div><div class='add'>+	reset-gpios = &lt;&amp;pio 51 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-krabby.dtsi b/arch/arm64/boot/dts/mediatek/mt8186-corsola-krabby.dtsi<br/>new file mode 100644<br/>index 000000000000..72a2a2bff0a9<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8186-corsola-krabby.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8186-corsola-krabby.dtsi</a></div><div class='hunk'>@@ -0,0 +1,129 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8186-corsola.dtsi"</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		i2c4 = &amp;i2c4;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsi_out {</div><div class='add'>+	remote-endpoint = &lt;&amp;ps8640_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+</div><div class='add'>+	edp-bridge@8 {</div><div class='add'>+		compatible = "parade,ps8640";</div><div class='add'>+		reg = &lt;0x8&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;ps8640_pins&gt;;</div><div class='add'>+		powerdown-gpios = &lt;&amp;pio 96 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pio 98 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		vdd12-supply = &lt;&amp;mt6366_vrf12_reg&gt;;</div><div class='add'>+		vdd33-supply = &lt;&amp;mt6366_vcn33_reg&gt;;</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				ps8640_in: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;dsi_out&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				ps8640_out: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;panel_in&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aux-bus {</div><div class='add'>+			panel {</div><div class='add'>+				compatible = "edp-panel";</div><div class='add'>+				power-supply = &lt;&amp;pp3300_disp_x&gt;;</div><div class='add'>+				backlight = &lt;&amp;backlight_lcd0&gt;;</div><div class='add'>+</div><div class='add'>+				port {</div><div class='add'>+					panel_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ps8640_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	i2c-scl-internal-delay-ns = &lt;10000&gt;;</div><div class='add'>+</div><div class='add'>+	touchscreen: touchscreen@10 {</div><div class='add'>+		compatible = "elan,ekth6915";</div><div class='add'>+		reg = &lt;0x10&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 12 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;touchscreen_pins&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pio 60 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		vcc33-supply = &lt;&amp;pp3300_s3&gt;;</div><div class='add'>+		no-reset-on-power-off;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c4_pins&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	proximity@28 {</div><div class='add'>+		compatible = "semtech,sx9324";</div><div class='add'>+		reg = &lt;0x28&gt;;</div><div class='add'>+		#io-channel-cells = &lt;1&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 5 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;sar_sensor_pins&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;mt6366_vio18_reg&gt;;</div><div class='add'>+		svdd-supply = &lt;&amp;mt6366_vio18_reg&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	i2c4_pins: i2c4-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO136__FUNC_SDA4&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO135__FUNC_SCL4&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+			drive-strength = &lt;4&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ps8640_pins: ps8640-pins {</div><div class='add'>+		pins-pwrdn-rst {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO96__FUNC_GPIO96&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO98__FUNC_GPIO98&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sar_sensor_pins: sar-sensor-pins {</div><div class='add'>+		pins-irq {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO5__FUNC_GPIO5&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-magneton-sku393216.dts b/arch/arm64/boot/dts/mediatek/mt8186-corsola-magneton-sku393216.dts<br/>new file mode 100644<br/>index 000000000000..c9673381ad3b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8186-corsola-magneton-sku393216.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8186-corsola-magneton-sku393216.dts</a></div><div class='hunk'>@@ -0,0 +1,39 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8186-corsola-steelix.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google Magneton board";</div><div class='add'>+	compatible = "google,steelix-sku393219", "google,steelix-sku393216",</div><div class='add'>+		     "google,steelix", "mediatek,mt8186";</div><div class='add'>+	chassis-type = "laptop";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio_keys {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	touchscreen@10 {</div><div class='add'>+		compatible = "hid-over-i2c";</div><div class='add'>+		reg = &lt;0x10&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 12 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;touchscreen_pins&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;pp3300_s3&gt;;</div><div class='add'>+		post-power-on-delay-ms = &lt;350&gt;;</div><div class='add'>+		hid-descr-addr = &lt;0x0001&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;touchscreen {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_c1 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-magneton-sku393217.dts b/arch/arm64/boot/dts/mediatek/mt8186-corsola-magneton-sku393217.dts<br/>new file mode 100644<br/>index 000000000000..28e3bbe56421<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8186-corsola-magneton-sku393217.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8186-corsola-magneton-sku393217.dts</a></div><div class='hunk'>@@ -0,0 +1,39 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8186-corsola-steelix.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google Magneton board";</div><div class='add'>+	compatible = "google,steelix-sku393220", "google,steelix-sku393217",</div><div class='add'>+		     "google,steelix", "mediatek,mt8186";</div><div class='add'>+	chassis-type = "laptop";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio_keys {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	touchscreen@40 {</div><div class='add'>+		compatible = "hid-over-i2c";</div><div class='add'>+		reg = &lt;0x40&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 12 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;touchscreen_pins&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;pp3300_s3&gt;;</div><div class='add'>+		post-power-on-delay-ms = &lt;450&gt;;</div><div class='add'>+		hid-descr-addr = &lt;0x0001&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;touchscreen {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_c1 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-magneton-sku393218.dts b/arch/arm64/boot/dts/mediatek/mt8186-corsola-magneton-sku393218.dts<br/>new file mode 100644<br/>index 000000000000..332894218f07<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8186-corsola-magneton-sku393218.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8186-corsola-magneton-sku393218.dts</a></div><div class='hunk'>@@ -0,0 +1,26 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8186-corsola-steelix.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google Magneton board";</div><div class='add'>+	compatible = "google,steelix-sku393221", "google,steelix-sku393218",</div><div class='add'>+		     "google,steelix", "mediatek,mt8186";</div><div class='add'>+	chassis-type = "laptop";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio_keys {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;touchscreen {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_c1 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-ponyta-sku0.dts b/arch/arm64/boot/dts/mediatek/mt8186-corsola-ponyta-sku0.dts<br/>new file mode 100644<br/>index 000000000000..986498af4c70<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8186-corsola-ponyta-sku0.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8186-corsola-ponyta-sku0.dts</a></div><div class='hunk'>@@ -0,0 +1,18 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8186-corsola-ponyta.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google Ponyta sku0 board";</div><div class='add'>+	compatible = "google,ponyta-sku0", "google,ponyta", "mediatek,mt8186";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	trackpad@15 {</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-ponyta-sku1.dts b/arch/arm64/boot/dts/mediatek/mt8186-corsola-ponyta-sku1.dts<br/>new file mode 100644<br/>index 000000000000..ff5eea0ddeb4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8186-corsola-ponyta-sku1.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8186-corsola-ponyta-sku1.dts</a></div><div class='hunk'>@@ -0,0 +1,22 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8186-corsola-ponyta.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google Ponyta sku1 board";</div><div class='add'>+	compatible = "google,ponyta-sku1", "google,ponyta", "mediatek,mt8186";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	trackpad@2c {</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_c1 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-ponyta.dtsi b/arch/arm64/boot/dts/mediatek/mt8186-corsola-ponyta.dtsi<br/>new file mode 100644<br/>index 000000000000..0abf69077089<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8186-corsola-ponyta.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8186-corsola-ponyta.dtsi</a></div><div class='hunk'>@@ -0,0 +1,49 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8186-corsola-steelix.dtsi"</div><div class='add'>+</div><div class='add'>+&amp;keyboard_controller {</div><div class='add'>+	function-row-physmap = &lt;</div><div class='add'>+		MATRIX_KEY(0x00, 0x02, 0)	/* T1 */</div><div class='add'>+		MATRIX_KEY(0x03, 0x02, 0)	/* T2 */</div><div class='add'>+		MATRIX_KEY(0x02, 0x02, 0)	/* T3 */</div><div class='add'>+		MATRIX_KEY(0x01, 0x02, 0)	/* T4 */</div><div class='add'>+		MATRIX_KEY(0x03, 0x04, 0)	/* T5 */</div><div class='add'>+		MATRIX_KEY(0x02, 0x04, 0)	/* T6 */</div><div class='add'>+		MATRIX_KEY(0x01, 0x04, 0)	/* T7 */</div><div class='add'>+		MATRIX_KEY(0x00, 0x04, 0)	/* T8 */</div><div class='add'>+		MATRIX_KEY(0x00, 0x01, 0)	/* T9 */</div><div class='add'>+		MATRIX_KEY(0x02, 0x09, 0)	/* T10 */</div><div class='add'>+		MATRIX_KEY(0x01, 0x09, 0)	/* T11 */</div><div class='add'>+		MATRIX_KEY(0x01, 0x05, 0)	/* T12 */</div><div class='add'>+	&gt;;</div><div class='add'>+</div><div class='add'>+	linux,keymap = &lt;</div><div class='add'>+		CROS_STD_MAIN_KEYMAP</div><div class='add'>+		MATRIX_KEY(0x00, 0x02, KEY_BACK)</div><div class='add'>+		MATRIX_KEY(0x03, 0x02, KEY_REFRESH)</div><div class='add'>+		MATRIX_KEY(0x02, 0x02, KEY_ZOOM)</div><div class='add'>+		MATRIX_KEY(0x01, 0x02, KEY_SCALE)</div><div class='add'>+		MATRIX_KEY(0x03, 0x04, KEY_SYSRQ)</div><div class='add'>+		MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN)</div><div class='add'>+		MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP)</div><div class='add'>+		MATRIX_KEY(0x00, 0x04, KEY_PLAYPAUSE)</div><div class='add'>+		MATRIX_KEY(0x00, 0x01, KEY_MICMUTE)</div><div class='add'>+		MATRIX_KEY(0x02, 0x09, KEY_MUTE)</div><div class='add'>+		MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)</div><div class='add'>+		MATRIX_KEY(0x01, 0x05, KEY_VOLUMEUP)</div><div class='add'>+	&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6366codec {</div><div class='add'>+	mediatek,dmic-mode = &lt;1&gt;; /* one-wire */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sound {</div><div class='add'>+	model = "mt8186_rt1019_rt5682s";</div><div class='add'>+};</div><div class='add'>+</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-rusty-sku196608.dts b/arch/arm64/boot/dts/mediatek/mt8186-corsola-rusty-sku196608.dts<br/>new file mode 100644<br/>index 000000000000..731b0d60228d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8186-corsola-rusty-sku196608.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8186-corsola-rusty-sku196608.dts</a></div><div class='hunk'>@@ -0,0 +1,26 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8186-corsola-steelix.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google Rusty board";</div><div class='add'>+	compatible = "google,steelix-sku196609", "google,steelix-sku196608",</div><div class='add'>+		     "google,steelix", "mediatek,mt8186";</div><div class='add'>+	chassis-type = "laptop";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio_keys {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;touchscreen {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-squirtle.dts b/arch/arm64/boot/dts/mediatek/mt8186-corsola-squirtle.dts<br/>new file mode 100644<br/>index 000000000000..f721ad4e5c97<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8186-corsola-squirtle.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8186-corsola-squirtle.dts</a></div><div class='hunk'>@@ -0,0 +1,107 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8186-corsola-voltorb.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google squirtle board";</div><div class='add'>+	compatible = "google,squirtle", "mediatek,mt8186";</div><div class='add'>+	chassis-type = "convertible";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	touchscreen@10 {</div><div class='add'>+		compatible = "elan,ekth6915";</div><div class='add'>+		reg = &lt;0x10&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 12 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;touchscreen_pins&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pio 60 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		vcc33-supply = &lt;&amp;pp3300_s3&gt;;</div><div class='add'>+		status = "fail-needs-probe";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	touchscreen@16 {</div><div class='add'>+		compatible = "elan,ekth8d18", "elan,ekth6a12nay";</div><div class='add'>+		reg = &lt;0x16&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 12 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;touchscreen_pins&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pio 60 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		vcc33-supply = &lt;&amp;pp3300_s3&gt;;</div><div class='add'>+		status = "fail-needs-probe";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	trackpad@68 {</div><div class='add'>+		compatible = "hid-over-i2c";</div><div class='add'>+		reg = &lt;0x68&gt;;</div><div class='add'>+		hid-descr-addr = &lt;0x20&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 11 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;trackpad_pin&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;pp3300_s3&gt;;</div><div class='add'>+		wakeup-source;</div><div class='add'>+		status = "fail-needs-probe";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c5 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+</div><div class='add'>+	/delete-node/ codec@1a;</div><div class='add'>+</div><div class='add'>+	rt5650: codec@1a {</div><div class='add'>+		compatible = "realtek,rt5650";</div><div class='add'>+		reg = &lt;0x1a&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 17 IRQ_TYPE_EDGE_BOTH&gt;;</div><div class='add'>+		avdd-supply = &lt;&amp;mt6366_vio18_reg&gt;;</div><div class='add'>+		cpvdd-supply = &lt;&amp;mt6366_vio18_reg&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;speaker_codec_pins_default&gt;;</div><div class='add'>+		cbj-sleeve-gpios = &lt;&amp;pio 150 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		realtek,dmic1-data-pin = &lt;2&gt;;</div><div class='add'>+		realtek,jd-mode = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sound {</div><div class='add'>+	compatible = "mediatek,mt8186-mt6366-rt5650-sound";</div><div class='add'>+	model = "mt8186_rt5650";</div><div class='add'>+</div><div class='add'>+	audio-routing =</div><div class='add'>+		"Headphone", "HPOL",</div><div class='add'>+		"Headphone", "HPOR",</div><div class='add'>+		"HDMI1", "TX";</div><div class='add'>+</div><div class='add'>+	hs-playback-dai-link {</div><div class='add'>+		codec {</div><div class='add'>+			sound-dai = &lt;&amp;rt5650&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hs-capture-dai-link {</div><div class='add'>+		codec {</div><div class='add'>+			sound-dai = &lt;&amp;rt5650&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spk-hdmi-playback-dai-link {</div><div class='add'>+		codec {</div><div class='add'>+			sound-dai = &lt;&amp;it6505dptx&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;speaker_codec {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;trackpad_steelix {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-starmie-sku0.dts b/arch/arm64/boot/dts/mediatek/mt8186-corsola-starmie-sku0.dts<br/>new file mode 100644<br/>index 000000000000..23e194579bf2<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8186-corsola-starmie-sku0.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8186-corsola-starmie-sku0.dts</a></div><div class='hunk'>@@ -0,0 +1,31 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8186-corsola-starmie.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google Starmie sku0 board";</div><div class='add'>+	compatible = "google,starmie-sku0", "google,starmie-sku2",</div><div class='add'>+		     "google,starmie-sku3", "google,starmie",</div><div class='add'>+		     "mediatek,mt8186";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;panel {</div><div class='add'>+	compatible = "starry,ili9882t";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	touchscreen: touchscreen@41 {</div><div class='add'>+		compatible = "ilitek,ili9882t";</div><div class='add'>+		reg = &lt;0x41&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 12 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;touchscreen_pins&gt;;</div><div class='add'>+		panel = &lt;&amp;panel&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pio 60 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		vccio-supply = &lt;&amp;mt6366_vio18_reg&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-starmie-sku1.dts b/arch/arm64/boot/dts/mediatek/mt8186-corsola-starmie-sku1.dts<br/>new file mode 100644<br/>index 000000000000..214b972c9357<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8186-corsola-starmie-sku1.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8186-corsola-starmie-sku1.dts</a></div><div class='hunk'>@@ -0,0 +1,31 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8186-corsola-starmie.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google Starmie sku1 board";</div><div class='add'>+	compatible = "google,starmie-sku1", "google,starmie-sku4",</div><div class='add'>+		     "google,starmie", "mediatek,mt8186";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;panel {</div><div class='add'>+	compatible = "starry,himax83102-j02", "himax,hx83102";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	touchscreen_himax: touchscreen@4f {</div><div class='add'>+		compatible = "hid-over-i2c";</div><div class='add'>+		reg = &lt;0x4f&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 12 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;touchscreen_pins&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;mt6366_vio18_reg&gt;;</div><div class='add'>+		panel = &lt;&amp;panel&gt;;</div><div class='add'>+		post-power-on-delay-ms = &lt;450&gt;;</div><div class='add'>+		hid-descr-addr = &lt;0x0001&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-starmie.dtsi b/arch/arm64/boot/dts/mediatek/mt8186-corsola-starmie.dtsi<br/>new file mode 100644<br/>index 000000000000..a8e79c2791ba<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8186-corsola-starmie.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8186-corsola-starmie.dtsi</a></div><div class='hunk'>@@ -0,0 +1,427 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8186-corsola.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	en_pp6000_mipi_disp_150ma: en-pp6000-mipi-disp-150ma {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "en_pp6000_mipi_disp_150ma";</div><div class='add'>+		gpio = &lt;&amp;pio 154 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;en_pp6000_mipi_disp_150ma_fixed_pins&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Starmie does not have 3.3V display regulator. It is replaced</div><div class='add'>+	 * with 6V module for enabling panel, re-using eDP GPIOs.</div><div class='add'>+	 */</div><div class='add'>+	/delete-node/ pp3300_disp_x;</div><div class='add'>+	en_pp6000_mipi_disp: en-regulator-pp6000-mipi-disp {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;edp_panel_fixed_pins&gt;;</div><div class='add'>+		gpios = &lt;&amp;pio 153 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		regulator-name = "en_pp6000_mipi_disp";</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-enable-ramp-delay = &lt;3000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;pp3300_z2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	tboard_thermistor1: thermal-sensor1 {</div><div class='add'>+		compatible = "generic-adc-thermal";</div><div class='add'>+		#thermal-sensor-cells = &lt;0&gt;;</div><div class='add'>+		io-channels = &lt;&amp;auxadc 0&gt;;</div><div class='add'>+		io-channel-names = "sensor-channel";</div><div class='add'>+		temperature-lookup-table = &lt;    (-5000) 1492</div><div class='add'>+						0 1413</div><div class='add'>+						5000 1324</div><div class='add'>+						10000 1227</div><div class='add'>+						15000 1121</div><div class='add'>+						20000 1017</div><div class='add'>+						25000 900</div><div class='add'>+						30000 797</div><div class='add'>+						35000 698</div><div class='add'>+						40000 606</div><div class='add'>+						45000 522</div><div class='add'>+						50000 449</div><div class='add'>+						55000 383</div><div class='add'>+						60000 327</div><div class='add'>+						65000 278</div><div class='add'>+						70000 236</div><div class='add'>+						75000 201</div><div class='add'>+						80000 171</div><div class='add'>+						85000 145</div><div class='add'>+						90000 163</div><div class='add'>+						95000 124</div><div class='add'>+						100000 91</div><div class='add'>+						105000 78</div><div class='add'>+						110000 67</div><div class='add'>+						115000 58</div><div class='add'>+						120000 50</div><div class='add'>+						125000 44&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	tboard_thermistor2: thermal-sensor2 {</div><div class='add'>+		compatible = "generic-adc-thermal";</div><div class='add'>+		#thermal-sensor-cells = &lt;0&gt;;</div><div class='add'>+		io-channels = &lt;&amp;auxadc 1&gt;;</div><div class='add'>+		io-channel-names = "sensor-channel";</div><div class='add'>+		temperature-lookup-table = &lt;    (-5000) 1492</div><div class='add'>+						0 1413</div><div class='add'>+						5000 1324</div><div class='add'>+						10000 1227</div><div class='add'>+						15000 1121</div><div class='add'>+						20000 1017</div><div class='add'>+						25000 900</div><div class='add'>+						30000 797</div><div class='add'>+						35000 698</div><div class='add'>+						40000 606</div><div class='add'>+						45000 522</div><div class='add'>+						50000 449</div><div class='add'>+						55000 383</div><div class='add'>+						60000 327</div><div class='add'>+						65000 278</div><div class='add'>+						70000 236</div><div class='add'>+						75000 201</div><div class='add'>+						80000 171</div><div class='add'>+						85000 145</div><div class='add'>+						90000 163</div><div class='add'>+						95000 124</div><div class='add'>+						100000 91</div><div class='add'>+						105000 78</div><div class='add'>+						110000 67</div><div class='add'>+						115000 58</div><div class='add'>+						120000 50</div><div class='add'>+						125000 44&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Starmie does not have EC keyboard. Remove default keyboard controller</div><div class='add'>+ * and replace it with the driver for side switches.</div><div class='add'>+ */</div><div class='add'>+/delete-node/ &amp;keyboard_controller;</div><div class='add'>+</div><div class='add'>+&amp;cros_ec {</div><div class='add'>+	cbas: cbas {</div><div class='add'>+		compatible = "google,cros-cbas";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	keyboard-controller {</div><div class='add'>+		compatible = "google,cros-ec-keyb-switches";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsi0 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	panel: panel@0 {</div><div class='add'>+		/* compatible will be set in board dts */</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;pio 98 0&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;panel_default_pins&gt;;</div><div class='add'>+		avdd-supply = &lt;&amp;en_pp6000_mipi_disp&gt;;</div><div class='add'>+		avee-supply = &lt;&amp;en_pp6000_mipi_disp_150ma&gt;;</div><div class='add'>+		pp1800-supply = &lt;&amp;mt6366_vio18_reg&gt;;</div><div class='add'>+		backlight = &lt;&amp;backlight_lcd0&gt;;</div><div class='add'>+		rotation = &lt;270&gt;;</div><div class='add'>+		port {</div><div class='add'>+			panel_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;dsi_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsi_out {</div><div class='add'>+	remote-endpoint = &lt;&amp;panel_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c5 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc1_pins_default {</div><div class='add'>+	pins-clk {</div><div class='add'>+		drive-strength = &lt;8&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pins-cmd-dat {</div><div class='add'>+		drive-strength = &lt;8&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc1_pins_uhs {</div><div class='add'>+	pins-clk {</div><div class='add'>+		drive-strength = &lt;8&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pins-cmd-dat {</div><div class='add'>+		drive-strength = &lt;8&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pen_insert {</div><div class='add'>+	wakeup-event-action = &lt;EV_ACT_ANY&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	/* 185 lines */</div><div class='add'>+	gpio-line-names = "TP",</div><div class='add'>+			  "TP",</div><div class='add'>+			  "TP",</div><div class='add'>+			  "I2S0_HP_DI",</div><div class='add'>+			  "I2S3_DP_SPKR_DO",</div><div class='add'>+			  "SAR_INT_ODL",</div><div class='add'>+			  "BT_WAKE_AP_ODL",</div><div class='add'>+			  "WIFI_INT_ODL",</div><div class='add'>+			  "DPBRDG_INT_ODL",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "EC_AP_HPD_OD",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "TCHSCR_INT_1V8_ODL",</div><div class='add'>+			  "EC_AP_INT_ODL",</div><div class='add'>+			  "EC_IN_RW_ODL",</div><div class='add'>+			  "GSC_AP_INT_ODL",</div><div class='add'>+			  /*</div><div class='add'>+			   * AP_FLASH_WP_L is crossystem ABI. Rev1 schematics</div><div class='add'>+			   * call it AP_WP_ODL.</div><div class='add'>+			   */</div><div class='add'>+			  "AP_FLASH_WP_L",</div><div class='add'>+			  "HP_INT_ODL",</div><div class='add'>+			  "PEN_EJECT_OD",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "UCAM_SEN_EN",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "I2S2_DP_SPK_MCK",</div><div class='add'>+			  "I2S2_DP_SPKR_BCK",</div><div class='add'>+			  "I2S2_DP_SPKR_LRCK",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "UART_GSC_TX_AP_RX",</div><div class='add'>+			  "UART_AP_TX_GSC_RX",</div><div class='add'>+			  "UART_DBGCON_TX_ADSP_RX",</div><div class='add'>+			  "UART_ADSP_TX_DBGCON_RX",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "TCHSCR_REPORT_DISABLE",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "EN_PP1800_DPBRDG",</div><div class='add'>+			  "SPI_AP_CLK_EC",</div><div class='add'>+			  "SPI_AP_CS_EC_L",</div><div class='add'>+			  "SPI_AP_DO_EC_DI",</div><div class='add'>+			  "SPI_AP_DI_EC_DO",</div><div class='add'>+			  "SPI_AP_CLK_GSC",</div><div class='add'>+			  "SPI_AP_CS_GSC_L",</div><div class='add'>+			  "SPI_AP_DO_GSC_DI",</div><div class='add'>+			  "SPI_AP_DI_GSC_DO",</div><div class='add'>+			  "UART_DBGCON_TX_SCP_RX",</div><div class='add'>+			  "UART_SCP_TX_DBGCON_RX",</div><div class='add'>+			  "EN_PP1200_CAM_X",</div><div class='add'>+			  "WLAN_MODULE_RST_L",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "I2S1_HP_DO",</div><div class='add'>+			  "I2S1_HP_BCK",</div><div class='add'>+			  "I2S1_HP_LRCK",</div><div class='add'>+			  "I2S1_HP_MCK",</div><div class='add'>+			  "TCHSCR_RST_1V8_L",</div><div class='add'>+			  "SPI_AP_CLK_ROM",</div><div class='add'>+			  "SPI_AP_CS_ROM_L",</div><div class='add'>+			  "SPI_AP_DO_ROM_DI",</div><div class='add'>+			  "SPI_AP_DI_ROM_DO",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "EMMC_STRB",</div><div class='add'>+			  "EMMC_CLK",</div><div class='add'>+			  "EMMC_CMD",</div><div class='add'>+			  "EMMC_RST_L",</div><div class='add'>+			  "EMMC_DATA0",</div><div class='add'>+			  "EMMC_DATA1",</div><div class='add'>+			  "EMMC_DATA2",</div><div class='add'>+			  "EMMC_DATA3",</div><div class='add'>+			  "EMMC_DATA4",</div><div class='add'>+			  "EMMC_DATA5",</div><div class='add'>+			  "EMMC_DATA6",</div><div class='add'>+			  "EMMC_DATA7",</div><div class='add'>+			  "AP_KPCOL0",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "TP",</div><div class='add'>+			  "SDIO_CLK",</div><div class='add'>+			  "SDIO_CMD",</div><div class='add'>+			  "SDIO_DATA0",</div><div class='add'>+			  "SDIO_DATA1",</div><div class='add'>+			  "SDIO_DATA2",</div><div class='add'>+			  "SDIO_DATA3",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "MIPI_BL_PWM_1V8",</div><div class='add'>+			  "DISP_RST_1V8_L",</div><div class='add'>+			  "MIPI_DPI_CLK",</div><div class='add'>+			  "MIPI_DPI_VSYNC",</div><div class='add'>+			  "MIPI_DPI_HSYNC",</div><div class='add'>+			  "MIPI_DPI_DE",</div><div class='add'>+			  "MIPI_DPI_D0",</div><div class='add'>+			  "MIPI_DPI_D1",</div><div class='add'>+			  "MIPI_DPI_D2",</div><div class='add'>+			  "MIPI_DPI_D3",</div><div class='add'>+			  "MIPI_DPI_D4",</div><div class='add'>+			  "MIPI_DPI_D5",</div><div class='add'>+			  "MIPI_DPI_D6",</div><div class='add'>+			  "MIPI_DPI_DA7",</div><div class='add'>+			  "MIPI_DPI_D8",</div><div class='add'>+			  "MIPI_DPI_D9",</div><div class='add'>+			  "MIPI_DPI_D10",</div><div class='add'>+			  "MIPI_DPI_D11",</div><div class='add'>+			  "PCM_BT_CLK",</div><div class='add'>+			  "PCM_BT_SYNC",</div><div class='add'>+			  "PCM_BT_DI",</div><div class='add'>+			  "PCM_BT_DO",</div><div class='add'>+			  "JTAG_TMS_TP",</div><div class='add'>+			  "JTAG_TCK_TP",</div><div class='add'>+			  "JTAG_TDI_TP",</div><div class='add'>+			  "JTAG_TDO_TP",</div><div class='add'>+			  "JTAG_TRSTN_TP",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "UCAM_DET_ODL",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "AP_I2C_TCHSCR_SCL_1V8",</div><div class='add'>+			  "AP_I2C_TCHSCR_SDA_1V8",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "AP_I2C_DPBRDG_SCL_1V8",</div><div class='add'>+			  "AP_I2C_DPBRDG_SDA_1V8",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "AP_I2C_AUD_SCL_1V8",</div><div class='add'>+			  "AP_I2C_AUD_SDA_1V8",</div><div class='add'>+			  "AP_I2C_DISP_SCL_1V8",</div><div class='add'>+			  "AP_I2C_DISP_SDA_1V8",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "SCP_I2C_SENSOR_SCL_1V8",</div><div class='add'>+			  "SCP_I2C_SENSOR_SDA_1V8",</div><div class='add'>+			  "AP_EC_WARM_RST_REQ",</div><div class='add'>+			  "AP_XHCI_INIT_DONE",</div><div class='add'>+			  "USB3_HUB_RST_L",</div><div class='add'>+			  "EN_SPKR",</div><div class='add'>+			  "BEEP_ON",</div><div class='add'>+			  "AP_DISP_BKLTEN",</div><div class='add'>+			  "EN_PP6000_MIPI_DISP",</div><div class='add'>+			  "EN_PP6000_MIPI_DISP_150MA",</div><div class='add'>+			  "BT_KILL_1V8_L",</div><div class='add'>+			  "WIFI_KILL_1V8_L",</div><div class='add'>+			  "PWRAP_SPI0_CSN",</div><div class='add'>+			  "PWRAP_SPI0_CK",</div><div class='add'>+			  "PWRAP_SPI0_MO",</div><div class='add'>+			  "PWRAP_SPI0_MI",</div><div class='add'>+			  "SRCLKENA0",</div><div class='add'>+			  "SRCLKENA1",</div><div class='add'>+			  "SCP_VREQ_VAO",</div><div class='add'>+			  "AP_RTC_CLK32K",</div><div class='add'>+			  "AP_PMIC_WDTRST_L",</div><div class='add'>+			  "AUD_CLK_MOSI",</div><div class='add'>+			  "AUD_SYNC_MOSI",</div><div class='add'>+			  "AUD_DAT_MOSI0",</div><div class='add'>+			  "AUD_DAT_MOSI1",</div><div class='add'>+			  "AUD_CLK_MISO",</div><div class='add'>+			  "AUD_SYNC_MISO",</div><div class='add'>+			  "AUD_DAT_MISO0",</div><div class='add'>+			  "AUD_DAT_MISO1",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "DPBRDG_RST_L",</div><div class='add'>+			  "LTE_W_DISABLE_L",</div><div class='add'>+			  "LTE_SAR_DETECT_L",</div><div class='add'>+			  "EN_PP3300_LTE_X",</div><div class='add'>+			  "LTE_PWR_OFF_L",</div><div class='add'>+			  "LTE_RESET_L",</div><div class='add'>+			  "TP",</div><div class='add'>+			  "TP";</div><div class='add'>+</div><div class='add'>+	en_pp6000_mipi_disp_150ma_fixed_pins: en_pp6000-mipi-disp-150ma-fixed-pins {</div><div class='add'>+		pins-en {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO154__FUNC_GPIO154&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	panel_default_pins: panel-default-pins {</div><div class='add'>+		pins-en {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO98__FUNC_GPIO98&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_c1 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;thermal_zones {</div><div class='add'>+	tboard1-thermal {</div><div class='add'>+		polling-delay = &lt;1000&gt;; /* milliseconds */</div><div class='add'>+		polling-delay-passive = &lt;0&gt;; /* milliseconds */</div><div class='add'>+		thermal-sensors = &lt;&amp;tboard_thermistor1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	tboard2-thermal {</div><div class='add'>+		polling-delay = &lt;1000&gt;; /* milliseconds */</div><div class='add'>+		polling-delay-passive = &lt;0&gt;; /* milliseconds */</div><div class='add'>+		thermal-sensors = &lt;&amp;tboard_thermistor2&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wifi_pwrseq {</div><div class='add'>+	reset-gpios = &lt;&amp;pio 51 1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Battery on Starmie is using a different address than default.</div><div class='add'>+ * Remove old node to reuse "battery" alias.</div><div class='add'>+ */</div><div class='add'>+/delete-node/ &amp;battery;</div><div class='add'>+&amp;i2c_tunnel {</div><div class='add'>+	battery: sbs-battery@f {</div><div class='add'>+		compatible = "sbs,sbs-battery";</div><div class='add'>+		reg = &lt;0xf&gt;;</div><div class='add'>+		sbs,i2c-retry-count = &lt;2&gt;;</div><div class='add'>+		sbs,poll-retry-count = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-steelix-sku131072.dts b/arch/arm64/boot/dts/mediatek/mt8186-corsola-steelix-sku131072.dts<br/>new file mode 100644<br/>index 000000000000..eae17bca8585<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8186-corsola-steelix-sku131072.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8186-corsola-steelix-sku131072.dts</a></div><div class='hunk'>@@ -0,0 +1,18 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8186-corsola-steelix.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google Steelix board";</div><div class='add'>+	compatible = "google,steelix-sku131072", "google,steelix",</div><div class='add'>+		     "mediatek,mt8186";</div><div class='add'>+	chassis-type = "convertible";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6366codec {</div><div class='add'>+	mediatek,dmic-mode = &lt;0&gt;; /* two-wire */</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-steelix-sku131073.dts b/arch/arm64/boot/dts/mediatek/mt8186-corsola-steelix-sku131073.dts<br/>new file mode 100644<br/>index 000000000000..a55375b95d0d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8186-corsola-steelix-sku131073.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8186-corsola-steelix-sku131073.dts</a></div><div class='hunk'>@@ -0,0 +1,18 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8186-corsola-steelix.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google Steelix board";</div><div class='add'>+	compatible = "google,steelix-sku131073", "google,steelix",</div><div class='add'>+		     "mediatek,mt8186";</div><div class='add'>+	chassis-type = "convertible";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6366codec {</div><div class='add'>+	mediatek,dmic-mode = &lt;1&gt;; /* one-wire */</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-steelix.dtsi b/arch/arm64/boot/dts/mediatek/mt8186-corsola-steelix.dtsi<br/>new file mode 100644<br/>index 000000000000..8a196dc9a96b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8186-corsola-steelix.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8186-corsola-steelix.dtsi</a></div><div class='hunk'>@@ -0,0 +1,206 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8186-corsola.dtsi"</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+</div><div class='add'>+/{</div><div class='add'>+	pp1000_edpbrdg: regulator-pp1000-edpbrdg {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "pp1000_edpbrdg";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;en_pp1000_edpbrdg&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		gpio = &lt;&amp;pio 29 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;pp3300_z2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pp1800_edpbrdg_dx: regulator-pp1800-edpbrdg-dx {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "pp1800_edpbrdg_dx";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;en_pp1800_edpbrdg&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		gpio = &lt;&amp;pio 30 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;mt6366_vio18_reg&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pp3300_edp_dx: regulator-pp3300-edp-dx {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "pp3300_edp_dx";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;en_pp3300_edpbrdg&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		gpio = &lt;&amp;pio 31 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;pp3300_z2&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsi_out {</div><div class='add'>+	remote-endpoint = &lt;&amp;anx7625_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+</div><div class='add'>+	anx_bridge: anx7625@58 {</div><div class='add'>+		compatible = "analogix,anx7625";</div><div class='add'>+		reg = &lt;0x58&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;anx7625_pins&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;pio 96 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pio 98 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		vdd10-supply = &lt;&amp;pp1000_edpbrdg&gt;;</div><div class='add'>+		vdd18-supply = &lt;&amp;pp1800_edpbrdg_dx&gt;;</div><div class='add'>+		vdd33-supply = &lt;&amp;pp3300_edp_dx&gt;;</div><div class='add'>+		analogix,lane0-swing = /bits/ 8 &lt;0x70 0x30&gt;;</div><div class='add'>+		analogix,lane1-swing = /bits/ 8 &lt;0x70 0x30&gt;;</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				anx7625_in: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;dsi_out&gt;;</div><div class='add'>+					data-lanes = &lt;0 1 2 3&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				anx7625_out: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;panel_in&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aux-bus {</div><div class='add'>+			panel: panel {</div><div class='add'>+				compatible = "edp-panel";</div><div class='add'>+				power-supply = &lt;&amp;pp3300_disp_x&gt;;</div><div class='add'>+				backlight = &lt;&amp;backlight_lcd0&gt;;</div><div class='add'>+</div><div class='add'>+				port {</div><div class='add'>+					panel_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;anx7625_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	touchscreen: touchscreen@5d {</div><div class='add'>+		compatible = "goodix,gt7375p";</div><div class='add'>+		reg = &lt;0x5d&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 12 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;touchscreen_pins&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pio 60 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;pp3300_s3&gt;;</div><div class='add'>+		goodix,no-reset-during-suspend;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	i2c-scl-internal-delay-ns = &lt;22000&gt;;</div><div class='add'>+</div><div class='add'>+	/* second source component */</div><div class='add'>+	trackpad_steelix: trackpad@2c {</div><div class='add'>+		compatible = "hid-over-i2c";</div><div class='add'>+		reg = &lt;0x2c&gt;;</div><div class='add'>+		hid-descr-addr = &lt;0x20&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 11 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;trackpad_pin&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;pp3300_s3&gt;;</div><div class='add'>+		wakeup-source;</div><div class='add'>+		status = "fail-needs-probe";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;keyboard_controller {</div><div class='add'>+	function-row-physmap = &lt;</div><div class='add'>+		MATRIX_KEY(0x00, 0x02, 0)	/* T1 */</div><div class='add'>+		MATRIX_KEY(0x03, 0x02, 0)	/* T2 */</div><div class='add'>+		MATRIX_KEY(0x02, 0x02, 0)	/* T3 */</div><div class='add'>+		MATRIX_KEY(0x01, 0x02, 0)	/* T4 */</div><div class='add'>+		MATRIX_KEY(0x03, 0x04, 0)	/* T5 */</div><div class='add'>+		MATRIX_KEY(0x02, 0x04, 0)	/* T6 */</div><div class='add'>+		MATRIX_KEY(0x01, 0x04, 0)	/* T7 */</div><div class='add'>+		MATRIX_KEY(0x02, 0x09, 0)	/* T8 */</div><div class='add'>+		MATRIX_KEY(0x01, 0x09, 0)	/* T9 */</div><div class='add'>+		MATRIX_KEY(0x00, 0x04, 0)	/* T10 */</div><div class='add'>+	&gt;;</div><div class='add'>+</div><div class='add'>+	linux,keymap = &lt;</div><div class='add'>+		MATRIX_KEY(0x00, 0x02, KEY_BACK)</div><div class='add'>+		MATRIX_KEY(0x03, 0x02, KEY_REFRESH)</div><div class='add'>+		MATRIX_KEY(0x02, 0x02, KEY_ZOOM)</div><div class='add'>+		MATRIX_KEY(0x01, 0x02, KEY_SCALE)</div><div class='add'>+		MATRIX_KEY(0x03, 0x04, KEY_BRIGHTNESSDOWN)</div><div class='add'>+		MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSUP)</div><div class='add'>+		MATRIX_KEY(0x01, 0x04, KEY_MICMUTE)</div><div class='add'>+		MATRIX_KEY(0x02, 0x09, KEY_MUTE)</div><div class='add'>+		MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)</div><div class='add'>+		MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)</div><div class='add'>+		CROS_STD_MAIN_KEYMAP</div><div class='add'>+	&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	anx7625_pins: anx7625-pins {</div><div class='add'>+		pins-int {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO9__FUNC_GPIO9&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-reset {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO98__FUNC_GPIO98&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-power-en {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO96__FUNC_GPIO96&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	en_pp1000_edpbrdg: pp1000-edpbrdg-en-pins {</div><div class='add'>+		pins-vreg-en {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO29__FUNC_GPIO29&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	en_pp1800_edpbrdg: pp1800-edpbrdg-en-pins {</div><div class='add'>+		pins-vreg-en {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO30__FUNC_GPIO30&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	en_pp3300_edpbrdg: pp3300-edpbrdg-en-pins {</div><div class='add'>+		pins-vreg-en {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO31__FUNC_GPIO31&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;trackpad {</div><div class='add'>+	status = "fail-needs-probe";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacool-sku327681.dts b/arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacool-sku327681.dts<br/>new file mode 100644<br/>index 000000000000..9bb64353ca65<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacool-sku327681.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacool-sku327681.dts</a></div><div class='hunk'>@@ -0,0 +1,57 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8186-corsola-krabby.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google Tentacool board";</div><div class='add'>+	compatible = "google,tentacruel-sku327681", "google,tentacruel", "mediatek,mt8186";</div><div class='add'>+	chassis-type = "laptop";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Tentacool omits the pen. */</div><div class='add'>+&amp;gpio_keys {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Tentacool omits the touchscreen; nothing else is on i2c1. */</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;keyboard_controller {</div><div class='add'>+	function-row-physmap = &lt;</div><div class='add'>+		MATRIX_KEY(0x00, 0x02, 0)	/* T1 */</div><div class='add'>+		MATRIX_KEY(0x03, 0x02, 0)	/* T2 */</div><div class='add'>+		MATRIX_KEY(0x02, 0x02, 0)	/* T3 */</div><div class='add'>+		MATRIX_KEY(0x01, 0x02, 0)	/* T4 */</div><div class='add'>+		MATRIX_KEY(0x03, 0x04, 0)	/* T5 */</div><div class='add'>+		MATRIX_KEY(0x02, 0x04, 0)	/* T6 */</div><div class='add'>+		MATRIX_KEY(0x01, 0x04, 0)	/* T7 */</div><div class='add'>+		MATRIX_KEY(0x02, 0x09, 0)	/* T8 */</div><div class='add'>+		MATRIX_KEY(0x01, 0x09, 0)	/* T9 */</div><div class='add'>+		MATRIX_KEY(0x00, 0x04, 0)	/* T10 */</div><div class='add'>+	&gt;;</div><div class='add'>+</div><div class='add'>+	linux,keymap = &lt;</div><div class='add'>+		MATRIX_KEY(0x00, 0x02, KEY_BACK)</div><div class='add'>+		MATRIX_KEY(0x03, 0x02, KEY_REFRESH)</div><div class='add'>+		MATRIX_KEY(0x02, 0x02, KEY_ZOOM)</div><div class='add'>+		MATRIX_KEY(0x01, 0x02, KEY_SCALE)</div><div class='add'>+		MATRIX_KEY(0x03, 0x04, KEY_SYSRQ)</div><div class='add'>+		MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN)</div><div class='add'>+		MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP)</div><div class='add'>+		MATRIX_KEY(0x02, 0x09, KEY_MUTE)</div><div class='add'>+		MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)</div><div class='add'>+		MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)</div><div class='add'>+		CROS_STD_MAIN_KEYMAP</div><div class='add'>+	&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Tentacool omits the touchscreen. */</div><div class='add'>+&amp;touchscreen {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacool-sku327683.dts b/arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacool-sku327683.dts<br/>new file mode 100644<br/>index 000000000000..4dbf2cb73a81<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacool-sku327683.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacool-sku327683.dts</a></div><div class='hunk'>@@ -0,0 +1,26 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "mt8186-corsola-tentacool-sku327681.dts"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "google,tentacruel-sku327683", "google,tentacruel", "mediatek,mt8186";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* This variant replaces only the trackpad controller. */</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	/delete-node/ trackpad@15;</div><div class='add'>+</div><div class='add'>+	trackpad@15 {</div><div class='add'>+		compatible = "hid-over-i2c";</div><div class='add'>+		reg = &lt;0x15&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 11 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;trackpad_pin&gt;;</div><div class='add'>+		hid-descr-addr = &lt;0x0001&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;pp3300_s3&gt;;</div><div class='add'>+		wakeup-source;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacruel-sku262144.dts b/arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacruel-sku262144.dts<br/>new file mode 100644<br/>index 000000000000..24d9ede63eaa<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacruel-sku262144.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacruel-sku262144.dts</a></div><div class='hunk'>@@ -0,0 +1,48 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8186-corsola-krabby.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google Tentacruel board";</div><div class='add'>+	compatible = "google,tentacruel-sku262147", "google,tentacruel-sku262146",</div><div class='add'>+		     "google,tentacruel-sku262145", "google,tentacruel-sku262144",</div><div class='add'>+		     "google,tentacruel", "mediatek,mt8186";</div><div class='add'>+	chassis-type = "convertible";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;keyboard_controller {</div><div class='add'>+	function-row-physmap = &lt;</div><div class='add'>+		MATRIX_KEY(0x00, 0x02, 0)	/* T1 */</div><div class='add'>+		MATRIX_KEY(0x03, 0x02, 0)	/* T2 */</div><div class='add'>+		MATRIX_KEY(0x02, 0x02, 0)	/* T3 */</div><div class='add'>+		MATRIX_KEY(0x01, 0x02, 0)	/* T4 */</div><div class='add'>+		MATRIX_KEY(0x03, 0x04, 0)	/* T5 */</div><div class='add'>+		MATRIX_KEY(0x02, 0x04, 0)	/* T6 */</div><div class='add'>+		MATRIX_KEY(0x01, 0x04, 0)	/* T7 */</div><div class='add'>+		MATRIX_KEY(0x02, 0x09, 0)	/* T8 */</div><div class='add'>+		MATRIX_KEY(0x01, 0x09, 0)	/* T9 */</div><div class='add'>+		MATRIX_KEY(0x00, 0x04, 0)	/* T10 */</div><div class='add'>+	&gt;;</div><div class='add'>+</div><div class='add'>+	linux,keymap = &lt;</div><div class='add'>+		MATRIX_KEY(0x00, 0x02, KEY_BACK)</div><div class='add'>+		MATRIX_KEY(0x03, 0x02, KEY_REFRESH)</div><div class='add'>+		MATRIX_KEY(0x02, 0x02, KEY_ZOOM)</div><div class='add'>+		MATRIX_KEY(0x01, 0x02, KEY_SCALE)</div><div class='add'>+		MATRIX_KEY(0x03, 0x04, KEY_SYSRQ)</div><div class='add'>+		MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN)</div><div class='add'>+		MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP)</div><div class='add'>+		MATRIX_KEY(0x02, 0x09, KEY_MUTE)</div><div class='add'>+		MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)</div><div class='add'>+		MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)</div><div class='add'>+		CROS_STD_MAIN_KEYMAP</div><div class='add'>+	&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;touchscreen {</div><div class='add'>+	compatible = "elan,ekth6a12nay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacruel-sku262148.dts b/arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacruel-sku262148.dts<br/>new file mode 100644<br/>index 000000000000..ee5bc2cd9e9f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacruel-sku262148.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacruel-sku262148.dts</a></div><div class='hunk'>@@ -0,0 +1,28 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "mt8186-corsola-tentacruel-sku262144.dts"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "google,tentacruel-sku262151", "google,tentacruel-sku262150",</div><div class='add'>+		     "google,tentacruel-sku262149", "google,tentacruel-sku262148",</div><div class='add'>+		     "google,tentacruel", "mediatek,mt8186";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* This variant replaces only the trackpad controller. */</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	/delete-node/ trackpad@15;</div><div class='add'>+</div><div class='add'>+	trackpad@15 {</div><div class='add'>+		compatible = "hid-over-i2c";</div><div class='add'>+		reg = &lt;0x15&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 11 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;trackpad_pin&gt;;</div><div class='add'>+		hid-descr-addr = &lt;0x0001&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;pp3300_s3&gt;;</div><div class='add'>+		wakeup-source;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb.dts b/arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb.dts<br/>new file mode 100644<br/>index 000000000000..cc805408a8b7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb.dts</a></div><div class='hunk'>@@ -0,0 +1,24 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8186-corsola-voltorb.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google Voltorb board";</div><div class='add'>+	compatible = "google,voltorb", "mediatek,mt8186";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	touchscreen@10 {</div><div class='add'>+		compatible = "elan,ekth6915";</div><div class='add'>+		reg = &lt;0x10&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 12 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;touchscreen_pins&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pio 60 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		vcc33-supply = &lt;&amp;pp3300_s3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb.dtsi b/arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb.dtsi<br/>new file mode 100644<br/>index 000000000000..b495a241b443<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb.dtsi</a></div><div class='hunk'>@@ -0,0 +1,92 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Google LLC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/spmi/spmi.h&gt;</div><div class='add'>+</div><div class='add'>+#include "mt8186-corsola-steelix.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	chassis-type = "laptop";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu6 {</div><div class='add'>+	proc-supply = &lt;&amp;mt6319_buck1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu7 {</div><div class='add'>+	proc-supply = &lt;&amp;mt6319_buck1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio_keys {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;keyboard_controller {</div><div class='add'>+	linux,keymap = &lt;</div><div class='add'>+		MATRIX_KEY(0x00, 0x02, KEY_BACK)</div><div class='add'>+		MATRIX_KEY(0x03, 0x02, KEY_REFRESH)</div><div class='add'>+		MATRIX_KEY(0x02, 0x02, KEY_ZOOM)</div><div class='add'>+		MATRIX_KEY(0x01, 0x02, KEY_SCALE)</div><div class='add'>+		MATRIX_KEY(0x03, 0x04, KEY_SYSRQ)</div><div class='add'>+		MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN)</div><div class='add'>+		MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP)</div><div class='add'>+		MATRIX_KEY(0x02, 0x09, KEY_MUTE)</div><div class='add'>+		MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)</div><div class='add'>+		MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)</div><div class='add'>+		CROS_STD_MAIN_KEYMAP</div><div class='add'>+	&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6366_vproc11_reg {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cluster1_opp_14 {</div><div class='add'>+	opp-hz = /bits/ 64 &lt;2050000000&gt;;</div><div class='add'>+	opp-microvolt = &lt;1118750&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cluster1_opp_15 {</div><div class='add'>+	opp-hz = /bits/ 64 &lt;2200000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sound {</div><div class='add'>+	compatible = "mediatek,mt8186-mt6366-rt5682s-max98360-sound";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;speaker_codec {</div><div class='add'>+	compatible = "maxim,max98360a";</div><div class='add'>+	sdmode-gpios = &lt;&amp;pio 150 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	/delete-property/ sdb-gpios;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spmi {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;spmi_pins&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pmic@6 {</div><div class='add'>+		compatible = "mediatek,mt6319-regulator", "mediatek,mt6315-regulator";</div><div class='add'>+		reg = &lt;0x6 SPMI_USID&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			mt6319_buck1: vbuck1 {</div><div class='add'>+					regulator-name = "ppvar_dvdd_proc_bc_mt6319";</div><div class='add'>+					regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+					regulator-max-microvolt = &lt;1193750&gt;;</div><div class='add'>+					regulator-enable-ramp-delay = &lt;256&gt;;</div><div class='add'>+					regulator-allowed-modes = &lt;0 1 2&gt;;</div><div class='add'>+					regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;touchscreen {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi b/arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi<br/>new file mode 100644<br/>index 000000000000..ff20376a44d7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi</a></div><div class='hunk'>@@ -0,0 +1,1725 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2022 MediaTek Inc.</div><div class='add'>+ */</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8186.dtsi"</div><div class='add'>+#include &lt;dt-bindings/pinctrl/mt8186-pinfunc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/gpio-keys.h&gt;</div><div class='add'>+#include &lt;dt-bindings/regulator/mediatek,mt6397-regulator.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		i2c0 = &amp;i2c0;</div><div class='add'>+		i2c1 = &amp;i2c1;</div><div class='add'>+		i2c2 = &amp;i2c2;</div><div class='add'>+		i2c3 = &amp;i2c3;</div><div class='add'>+		i2c5 = &amp;i2c5;</div><div class='add'>+		mmc0 = &amp;mmc0;</div><div class='add'>+		mmc1 = &amp;mmc1;</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		/* The size should be filled in by the bootloader. */</div><div class='add'>+		reg = &lt;0 0x40000000 0 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	backlight_lcd0: backlight-lcd0 {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		pwms = &lt;&amp;pwm0 0 500000&gt;;</div><div class='add'>+		power-supply = &lt;&amp;ppvar_sys&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;pio 152 0&gt;;</div><div class='add'>+		brightness-levels = &lt;0 1023&gt;;</div><div class='add'>+		num-interpolated-steps = &lt;1023&gt;;</div><div class='add'>+		default-brightness-level = &lt;576&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bt-sco {</div><div class='add'>+		compatible = "linux,bt-sco";</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dmic-codec {</div><div class='add'>+		compatible = "dmic-codec";</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		num-channels = &lt;2&gt;;</div><div class='add'>+		wakeup-delay-ms = &lt;50&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio_keys: gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pen_eject&gt;;</div><div class='add'>+</div><div class='add'>+		pen_insert: pen-insert-switch {</div><div class='add'>+			label = "Pen Insert";</div><div class='add'>+			/* Insert = low, eject = high */</div><div class='add'>+			gpios = &lt;&amp;pio 18 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			wakeup-event-action = &lt;EV_ACT_DEASSERTED&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+			linux,code = &lt;SW_PEN_INSERTED&gt;;</div><div class='add'>+			linux,input-type = &lt;EV_SW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pp1800_dpbrdg_dx: regulator-pp1800-dpbrdg-dx {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;en_pp1800_dpbrdg&gt;;</div><div class='add'>+		gpios = &lt;&amp;pio 39 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		regulator-name = "pp1800_dpbrdg_dx";</div><div class='add'>+		enable-active-high;</div><div class='add'>+		vin-supply = &lt;&amp;mt6366_vio18_reg&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pp3300_disp_x: regulator-pp3300-disp-x {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;edp_panel_fixed_pins&gt;;</div><div class='add'>+		gpios = &lt;&amp;pio 153 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		regulator-name = "pp3300_disp_x";</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		vin-supply = &lt;&amp;pp3300_z2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* system wide LDO 3.3V power rail */</div><div class='add'>+	pp3300_z5: regulator-pp3300-ldo-z5 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "pp3300_ldo_z5";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;ppvar_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* separately switched 3.3V power rail */</div><div class='add'>+	pp3300_s3: regulator-pp3300-s3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "pp3300_s3";</div><div class='add'>+		/* automatically sequenced by PMIC EXT_PMIC_EN2 */</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		vin-supply = &lt;&amp;pp3300_z2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* system wide 3.3V power rail */</div><div class='add'>+	pp3300_z2: regulator-pp3300-z2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "pp3300_z2";</div><div class='add'>+		/* EN pin tied to pp4200_z2, which is controlled by EC */</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;ppvar_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* system wide 4.2V power rail */</div><div class='add'>+	pp4200_z2: regulator-pp4200-z2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "pp4200_z2";</div><div class='add'>+		/* controlled by EC */</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-min-microvolt = &lt;4200000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;4200000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;ppvar_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* system wide switching 5.0V power rail */</div><div class='add'>+	pp5000_z2: regulator-pp5000-z2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "pp5000_z2";</div><div class='add'>+		/* controlled by EC */</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;ppvar_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* system wide semi-regulated power rail from battery or USB */</div><div class='add'>+	ppvar_sys: regulator-ppvar-sys {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "ppvar_sys";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved_memory: reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		afe_dma_mem: audio-dma-pool {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			size = &lt;0 0x100000&gt;;</div><div class='add'>+			alignment = &lt;0 0x10&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		adsp_dma_mem: memory@61000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x61000000 0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		adsp_mem: memory@60000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x60000000 0 0x1000000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		scp_mem: memory@50000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x50000000 0 0x10a0000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound: sound {</div><div class='add'>+		compatible = "mediatek,mt8186-mt6366-rt1019-rt5682s-sound";</div><div class='add'>+		pinctrl-names = "aud_clk_mosi_off",</div><div class='add'>+				"aud_clk_mosi_on",</div><div class='add'>+				"aud_clk_miso_off",</div><div class='add'>+				"aud_clk_miso_on",</div><div class='add'>+				"aud_dat_miso_off",</div><div class='add'>+				"aud_dat_miso_on",</div><div class='add'>+				"aud_dat_mosi_off",</div><div class='add'>+				"aud_dat_mosi_on",</div><div class='add'>+				"aud_gpio_i2s0_off",</div><div class='add'>+				"aud_gpio_i2s0_on",</div><div class='add'>+				"aud_gpio_i2s1_off",</div><div class='add'>+				"aud_gpio_i2s1_on",</div><div class='add'>+				"aud_gpio_i2s2_off",</div><div class='add'>+				"aud_gpio_i2s2_on",</div><div class='add'>+				"aud_gpio_i2s3_off",</div><div class='add'>+				"aud_gpio_i2s3_on",</div><div class='add'>+				"aud_gpio_pcm_off",</div><div class='add'>+				"aud_gpio_pcm_on",</div><div class='add'>+				"aud_gpio_dmic_sec";</div><div class='add'>+		pinctrl-0 = &lt;&amp;aud_clk_mosi_off&gt;;</div><div class='add'>+		pinctrl-1 = &lt;&amp;aud_clk_mosi_on&gt;;</div><div class='add'>+		pinctrl-2 = &lt;&amp;aud_clk_miso_off&gt;;</div><div class='add'>+		pinctrl-3 = &lt;&amp;aud_clk_miso_on&gt;;</div><div class='add'>+		pinctrl-4 = &lt;&amp;aud_dat_miso_off&gt;;</div><div class='add'>+		pinctrl-5 = &lt;&amp;aud_dat_miso_on&gt;;</div><div class='add'>+		pinctrl-6 = &lt;&amp;aud_dat_mosi_off&gt;;</div><div class='add'>+		pinctrl-7 = &lt;&amp;aud_dat_mosi_on&gt;;</div><div class='add'>+		pinctrl-8 = &lt;&amp;aud_gpio_i2s0_off&gt;;</div><div class='add'>+		pinctrl-9 = &lt;&amp;aud_gpio_i2s0_on&gt;;</div><div class='add'>+		pinctrl-10 = &lt;&amp;aud_gpio_i2s1_off&gt;;</div><div class='add'>+		pinctrl-11 = &lt;&amp;aud_gpio_i2s1_on&gt;;</div><div class='add'>+		pinctrl-12 = &lt;&amp;aud_gpio_i2s2_off&gt;;</div><div class='add'>+		pinctrl-13 = &lt;&amp;aud_gpio_i2s2_on&gt;;</div><div class='add'>+		pinctrl-14 = &lt;&amp;aud_gpio_i2s3_off&gt;;</div><div class='add'>+		pinctrl-15 = &lt;&amp;aud_gpio_i2s3_on&gt;;</div><div class='add'>+		pinctrl-16 = &lt;&amp;aud_gpio_pcm_off&gt;;</div><div class='add'>+		pinctrl-17 = &lt;&amp;aud_gpio_pcm_on&gt;;</div><div class='add'>+		pinctrl-18 = &lt;&amp;aud_gpio_dmic_sec&gt;;</div><div class='add'>+		mediatek,adsp = &lt;&amp;adsp&gt;;</div><div class='add'>+		mediatek,platform = &lt;&amp;afe&gt;;</div><div class='add'>+</div><div class='add'>+		audio-routing =</div><div class='add'>+			"Headphone", "HPOL",</div><div class='add'>+			"Headphone", "HPOR",</div><div class='add'>+			"IN1P", "Headset Mic",</div><div class='add'>+			"Speakers", "Speaker",</div><div class='add'>+			"HDMI1", "TX";</div><div class='add'>+</div><div class='add'>+		hs-playback-dai-link {</div><div class='add'>+			link-name = "I2S0";</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			mediatek,clk-provider = "cpu";</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;rt5682s 0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		hs-capture-dai-link {</div><div class='add'>+			link-name = "I2S1";</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			mediatek,clk-provider = "cpu";</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;rt5682s 0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spk-share-dai-link {</div><div class='add'>+			link-name = "I2S2";</div><div class='add'>+			mediatek,clk-provider = "cpu";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spk-hdmi-playback-dai-link {</div><div class='add'>+			link-name = "I2S3";</div><div class='add'>+			dai-format = "i2s";</div><div class='add'>+			mediatek,clk-provider = "cpu";</div><div class='add'>+			/* RT1019P and IT6505 connected to the same I2S line */</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;it6505dptx&gt;, &lt;&amp;speaker_codec&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	speaker_codec: speaker-codec {</div><div class='add'>+		compatible = "realtek,rt1019p";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;speaker_codec_pins_default&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		sdb-gpios = &lt;&amp;pio 150 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb_p1_vbus: regulator-usb-p1-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		gpio = &lt;&amp;pio 148 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		regulator-name = "vbus1";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		vin-supply = &lt;&amp;pp5000_z2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wifi_pwrseq: wifi-pwrseq {</div><div class='add'>+		compatible = "mmc-pwrseq-simple";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;wifi_enable_pin&gt;;</div><div class='add'>+		post-power-on-delay-ms = &lt;50&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pio 54 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wifi_wakeup: wifi-wakeup {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;wifi_wakeup_pin&gt;;</div><div class='add'>+</div><div class='add'>+		wowlan-event {</div><div class='add'>+			label = "Wake on WiFi";</div><div class='add'>+			gpios = &lt;&amp;pio 7 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_WAKEUP&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;adsp {</div><div class='add'>+	memory-region = &lt;&amp;adsp_dma_mem&gt;, &lt;&amp;adsp_mem&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;afe {</div><div class='add'>+	memory-region = &lt;&amp;afe_dma_mem&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cci {</div><div class='add'>+	proc-supply = &lt;&amp;mt6366_vproc12_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	proc-supply = &lt;&amp;mt6366_vproc12_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu1 {</div><div class='add'>+	proc-supply = &lt;&amp;mt6366_vproc12_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu2 {</div><div class='add'>+	proc-supply = &lt;&amp;mt6366_vproc12_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu3 {</div><div class='add'>+	proc-supply = &lt;&amp;mt6366_vproc12_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu4 {</div><div class='add'>+	proc-supply = &lt;&amp;mt6366_vproc12_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu5 {</div><div class='add'>+	proc-supply = &lt;&amp;mt6366_vproc12_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu6 {</div><div class='add'>+	proc-supply = &lt;&amp;mt6366_vproc11_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu7 {</div><div class='add'>+	proc-supply = &lt;&amp;mt6366_vproc11_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpi {</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;dpi_pins_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;dpi_pins_sleep&gt;;</div><div class='add'>+	/* TODO Re-enable after DP to Type-C port muxing can be described */</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpi_out {</div><div class='add'>+	remote-endpoint = &lt;&amp;it6505_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsi0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gic {</div><div class='add'>+	mediatek,broken-save-restore-fw;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	mali-supply = &lt;&amp;mt6366_vgpu_reg&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c0_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c1_pins&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	i2c-scl-internal-delay-ns = &lt;8000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c2_pins&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	i2c-scl-internal-delay-ns = &lt;10000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	trackpad: trackpad@15 {</div><div class='add'>+		compatible = "elan,ekth3000";</div><div class='add'>+		reg = &lt;0x15&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 11 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;trackpad_pin&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;pp3300_s3&gt;;</div><div class='add'>+		wakeup-source;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c3_pins&gt;;</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	it6505dptx: dp-bridge@5c {</div><div class='add'>+		compatible = "ite,it6505";</div><div class='add'>+		reg = &lt;0x5c&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 8 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;it6505_pins&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		ovdd-supply = &lt;&amp;mt6366_vsim2_reg&gt;;</div><div class='add'>+		pwr18-supply = &lt;&amp;pp1800_dpbrdg_dx&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pio 177 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		extcon = &lt;&amp;usbc_extcon&gt;;</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				it6505_in: endpoint {</div><div class='add'>+					link-frequencies = /bits/ 64 &lt;150000000&gt;;</div><div class='add'>+					remote-endpoint = &lt;&amp;dpi_out&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c5 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c5_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	rt5682s: codec@1a {</div><div class='add'>+		compatible = "realtek,rt5682s";</div><div class='add'>+		reg = &lt;0x1a&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 17 IRQ_TYPE_EDGE_BOTH&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+		AVDD-supply = &lt;&amp;mt6366_vio18_reg&gt;;</div><div class='add'>+		DBVDD-supply = &lt;&amp;mt6366_vio18_reg&gt;;</div><div class='add'>+		LDO1-IN-supply = &lt;&amp;mt6366_vio18_reg&gt;;</div><div class='add'>+		MICVDD-supply = &lt;&amp;pp3300_z2&gt;;</div><div class='add'>+		realtek,jd-src = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mfg0 {</div><div class='add'>+	domain-supply = &lt;&amp;mt6366_vsram_gpu_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mfg1 {</div><div class='add'>+	domain-supply = &lt;&amp;mt6366_vgpu_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_tx0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc0 {</div><div class='add'>+	pinctrl-names = "default", "state_uhs";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc0_pins_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;mmc0_pins_uhs&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	cap-mmc-highspeed;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	mmc-hs400-1_8v;</div><div class='add'>+	supports-cqe;</div><div class='add'>+	no-sd;</div><div class='add'>+	no-sdio;</div><div class='add'>+	cap-mmc-hw-reset;</div><div class='add'>+	hs400-ds-delay = &lt;0x11814&gt;;</div><div class='add'>+	mediatek,hs400-ds-dly3 = &lt;0x14&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;mt6366_vemc_reg&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;mt6366_vio18_reg&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc1 {</div><div class='add'>+	pinctrl-names = "default", "state_uhs", "state_eint";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc1_pins_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;mmc1_pins_uhs&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;mmc1_pins_eint&gt;;</div><div class='add'>+	/delete-property/ interrupts;</div><div class='add'>+	interrupt-names = "msdc", "sdio_wakeup";</div><div class='add'>+	interrupts-extended = &lt;&amp;gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			      &lt;&amp;pio 87 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	sd-uhs-sdr104;</div><div class='add'>+	sd-uhs-sdr50;</div><div class='add'>+	keep-power-in-suspend;</div><div class='add'>+	wakeup-source;</div><div class='add'>+	cap-sdio-irq;</div><div class='add'>+	no-mmc;</div><div class='add'>+	no-sd;</div><div class='add'>+	vmmc-supply = &lt;&amp;pp3300_s3&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;mt6366_vio18_reg&gt;;</div><div class='add'>+	mmc-pwrseq = &lt;&amp;wifi_pwrseq&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bluetooth@2 {</div><div class='add'>+		compatible = "mediatek,mt7921s-bluetooth";</div><div class='add'>+		reg = &lt;2&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;bt_pins_reset&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pio 155 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;nor_flash {</div><div class='add'>+	assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_MAINPLL_D7_D4&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;nor_pins_default&gt;;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;39000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	/* 185 lines */</div><div class='add'>+	gpio-line-names = "TP",</div><div class='add'>+			  "TP",</div><div class='add'>+			  "TP",</div><div class='add'>+			  "I2S0_HP_DI",</div><div class='add'>+			  "I2S3_DP_SPKR_DO",</div><div class='add'>+			  "SAR_INT_ODL",</div><div class='add'>+			  "BT_WAKE_AP_ODL",</div><div class='add'>+			  "WIFI_INT_ODL",</div><div class='add'>+			  "DPBRDG_INT_ODL",</div><div class='add'>+			  "EDPBRDG_INT_ODL",</div><div class='add'>+			  "EC_AP_HPD_OD",</div><div class='add'>+			  "TCHPAD_INT_ODL",</div><div class='add'>+			  "TCHSCR_INT_1V8_ODL",</div><div class='add'>+			  "EC_AP_INT_ODL",</div><div class='add'>+			  "EC_IN_RW_ODL",</div><div class='add'>+			  "GSC_AP_INT_ODL",</div><div class='add'>+			  /* AP_FLASH_WP_L is crossystem ABI. Rev1 schematics call it AP_WP_ODL. */</div><div class='add'>+			  "AP_FLASH_WP_L",</div><div class='add'>+			  "HP_INT_ODL",</div><div class='add'>+			  "PEN_EJECT_OD",</div><div class='add'>+			  "WCAM_PWDN_L",</div><div class='add'>+			  "WCAM_RST_L",</div><div class='add'>+			  "UCAM_SEN_EN",</div><div class='add'>+			  "UCAM_RST_L",</div><div class='add'>+			  "LTE_RESET_L",</div><div class='add'>+			  "LTE_SAR_DETECT_L",</div><div class='add'>+			  "I2S2_DP_SPK_MCK",</div><div class='add'>+			  "I2S2_DP_SPKR_BCK",</div><div class='add'>+			  "I2S2_DP_SPKR_LRCK",</div><div class='add'>+			  "I2S2_DP_SPKR_DI (TP)",</div><div class='add'>+			  "EN_PP1000_EDPBRDG",</div><div class='add'>+			  "EN_PP1800_EDPBRDG",</div><div class='add'>+			  "EN_PP3300_EDPBRDG",</div><div class='add'>+			  "UART_GSC_TX_AP_RX",</div><div class='add'>+			  "UART_AP_TX_GSC_RX",</div><div class='add'>+			  "UART_DBGCON_TX_ADSP_RX",</div><div class='add'>+			  "UART_ADSP_TX_DBGCON_RX",</div><div class='add'>+			  "EN_PP1000_DPBRDG",</div><div class='add'>+			  "TCHSCR_REPORT_DISABLE",</div><div class='add'>+			  "EN_PP3300_DPBRDG",</div><div class='add'>+			  "EN_PP1800_DPBRDG",</div><div class='add'>+			  "SPI_AP_CLK_EC",</div><div class='add'>+			  "SPI_AP_CS_EC_L",</div><div class='add'>+			  "SPI_AP_DO_EC_DI",</div><div class='add'>+			  "SPI_AP_DI_EC_DO",</div><div class='add'>+			  "SPI_AP_CLK_GSC",</div><div class='add'>+			  "SPI_AP_CS_GSC_L",</div><div class='add'>+			  "SPI_AP_DO_GSC_DI",</div><div class='add'>+			  "SPI_AP_DI_GSC_DO",</div><div class='add'>+			  "UART_DBGCON_TX_SCP_RX",</div><div class='add'>+			  "UART_SCP_TX_DBGCON_RX",</div><div class='add'>+			  "EN_PP1200_CAM_X",</div><div class='add'>+			  "EN_PP2800A_VCM_X",</div><div class='add'>+			  "EN_PP2800A_UCAM_X",</div><div class='add'>+			  "EN_PP2800A_WCAM_X",</div><div class='add'>+			  "WLAN_MODULE_RST_L",</div><div class='add'>+			  "EN_PP1200_UCAM_X",</div><div class='add'>+			  "I2S1_HP_DO",</div><div class='add'>+			  "I2S1_HP_BCK",</div><div class='add'>+			  "I2S1_HP_LRCK",</div><div class='add'>+			  "I2S1_HP_MCK",</div><div class='add'>+			  "TCHSCR_RST_1V8_L",</div><div class='add'>+			  "SPI_AP_CLK_ROM",</div><div class='add'>+			  "SPI_AP_CS_ROM_L",</div><div class='add'>+			  "SPI_AP_DO_ROM_DI",</div><div class='add'>+			  "SPI_AP_DI_ROM_DO",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "EMMC_STRB",</div><div class='add'>+			  "EMMC_CLK",</div><div class='add'>+			  "EMMC_CMD",</div><div class='add'>+			  "EMMC_RST_L",</div><div class='add'>+			  "EMMC_DATA0",</div><div class='add'>+			  "EMMC_DATA1",</div><div class='add'>+			  "EMMC_DATA2",</div><div class='add'>+			  "EMMC_DATA3",</div><div class='add'>+			  "EMMC_DATA4",</div><div class='add'>+			  "EMMC_DATA5",</div><div class='add'>+			  "EMMC_DATA6",</div><div class='add'>+			  "EMMC_DATA7",</div><div class='add'>+			  "AP_KPCOL0",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "TP",</div><div class='add'>+			  "SDIO_CLK",</div><div class='add'>+			  "SDIO_CMD",</div><div class='add'>+			  "SDIO_DATA0",</div><div class='add'>+			  "SDIO_DATA1",</div><div class='add'>+			  "SDIO_DATA2",</div><div class='add'>+			  "SDIO_DATA3",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "EDPBRDG_PWREN",</div><div class='add'>+			  "BL_PWM_1V8",</div><div class='add'>+			  "EDPBRDG_RST_L",</div><div class='add'>+			  "MIPI_DPI_CLK",</div><div class='add'>+			  "MIPI_DPI_VSYNC",</div><div class='add'>+			  "MIPI_DPI_HSYNC",</div><div class='add'>+			  "MIPI_DPI_DE",</div><div class='add'>+			  "MIPI_DPI_D0",</div><div class='add'>+			  "MIPI_DPI_D1",</div><div class='add'>+			  "MIPI_DPI_D2",</div><div class='add'>+			  "MIPI_DPI_D3",</div><div class='add'>+			  "MIPI_DPI_D4",</div><div class='add'>+			  "MIPI_DPI_D5",</div><div class='add'>+			  "MIPI_DPI_D6",</div><div class='add'>+			  "MIPI_DPI_DA7",</div><div class='add'>+			  "MIPI_DPI_D8",</div><div class='add'>+			  "MIPI_DPI_D9",</div><div class='add'>+			  "MIPI_DPI_D10",</div><div class='add'>+			  "MIPI_DPI_D11",</div><div class='add'>+			  "PCM_BT_CLK",</div><div class='add'>+			  "PCM_BT_SYNC",</div><div class='add'>+			  "PCM_BT_DI",</div><div class='add'>+			  "PCM_BT_DO",</div><div class='add'>+			  "JTAG_TMS_TP",</div><div class='add'>+			  "JTAG_TCK_TP",</div><div class='add'>+			  "JTAG_TDI_TP",</div><div class='add'>+			  "JTAG_TDO_TP",</div><div class='add'>+			  "JTAG_TRSTN_TP",</div><div class='add'>+			  "CLK_24M_WCAM",</div><div class='add'>+			  "CLK_24M_UCAM",</div><div class='add'>+			  "UCAM_DET_ODL",</div><div class='add'>+			  "AP_I2C_EDPBRDG_SCL_1V8",</div><div class='add'>+			  "AP_I2C_EDPBRDG_SDA_1V8",</div><div class='add'>+			  "AP_I2C_TCHSCR_SCL_1V8",</div><div class='add'>+			  "AP_I2C_TCHSCR_SDA_1V8",</div><div class='add'>+			  "AP_I2C_TCHPAD_SCL_1V8",</div><div class='add'>+			  "AP_I2C_TCHPAD_SDA_1V8",</div><div class='add'>+			  "AP_I2C_DPBRDG_SCL_1V8",</div><div class='add'>+			  "AP_I2C_DPBRDG_SDA_1V8",</div><div class='add'>+			  "AP_I2C_WLAN_SCL_1V8",</div><div class='add'>+			  "AP_I2C_WLAN_SDA_1V8",</div><div class='add'>+			  "AP_I2C_AUD_SCL_1V8",</div><div class='add'>+			  "AP_I2C_AUD_SDA_1V8",</div><div class='add'>+			  "AP_I2C_TPM_SCL_1V8",</div><div class='add'>+			  "AP_I2C_UCAM_SDA_1V8",</div><div class='add'>+			  "AP_I2C_UCAM_SCL_1V8",</div><div class='add'>+			  "AP_I2C_UCAM_SDA_1V8",</div><div class='add'>+			  "AP_I2C_WCAM_SCL_1V8",</div><div class='add'>+			  "AP_I2C_WCAM_SDA_1V8",</div><div class='add'>+			  "SCP_I2C_SENSOR_SCL_1V8",</div><div class='add'>+			  "SCP_I2C_SENSOR_SDA_1V8",</div><div class='add'>+			  "AP_EC_WARM_RST_REQ",</div><div class='add'>+			  "AP_XHCI_INIT_DONE",</div><div class='add'>+			  "USB3_HUB_RST_L",</div><div class='add'>+			  "EN_SPKR",</div><div class='add'>+			  "BEEP_ON",</div><div class='add'>+			  "AP_EDP_BKLTEN",</div><div class='add'>+			  "EN_PP3300_DISP_X",</div><div class='add'>+			  "EN_PP3300_SDBRDG_X",</div><div class='add'>+			  "BT_KILL_1V8_L",</div><div class='add'>+			  "WIFI_KILL_1V8_L",</div><div class='add'>+			  "PWRAP_SPI0_CSN",</div><div class='add'>+			  "PWRAP_SPI0_CK",</div><div class='add'>+			  "PWRAP_SPI0_MO",</div><div class='add'>+			  "PWRAP_SPI0_MI",</div><div class='add'>+			  "SRCLKENA0",</div><div class='add'>+			  "SRCLKENA1",</div><div class='add'>+			  "SCP_VREQ_VAO",</div><div class='add'>+			  "AP_RTC_CLK32K",</div><div class='add'>+			  "AP_PMIC_WDTRST_L",</div><div class='add'>+			  "AUD_CLK_MOSI",</div><div class='add'>+			  "AUD_SYNC_MOSI",</div><div class='add'>+			  "AUD_DAT_MOSI0",</div><div class='add'>+			  "AUD_DAT_MOSI1",</div><div class='add'>+			  "AUD_CLK_MISO",</div><div class='add'>+			  "AUD_SYNC_MISO",</div><div class='add'>+			  "AUD_DAT_MISO0",</div><div class='add'>+			  "AUD_DAT_MISO1",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "NC",</div><div class='add'>+			  "DPBRDG_PWREN",</div><div class='add'>+			  "DPBRDG_RST_L",</div><div class='add'>+			  "LTE_W_DISABLE_L",</div><div class='add'>+			  "LTE_SAR_DETECT_L",</div><div class='add'>+			  "EN_PP3300_LTE_X",</div><div class='add'>+			  "LTE_PWR_OFF_L",</div><div class='add'>+			  "LTE_RESET_L",</div><div class='add'>+			  "TP",</div><div class='add'>+			  "TP";</div><div class='add'>+</div><div class='add'>+	aud_clk_mosi_off: aud-clk-mosi-off-pins {</div><div class='add'>+		pins-clk-sync {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO166__FUNC_GPIO166&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO167__FUNC_GPIO167&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-down;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_clk_mosi_on: aud-clk-mosi-on-pins {</div><div class='add'>+		pins-clk-sync {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO166__FUNC_AUD_CLK_MOSI&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO167__FUNC_AUD_SYNC_MOSI&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_clk_miso_off: aud-clk-miso-off-pins {</div><div class='add'>+		pins-clk-sync {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO170__FUNC_GPIO170&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO171__FUNC_GPIO171&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-down;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_clk_miso_on: aud-clk-miso-on-pins {</div><div class='add'>+		pins-clk-sync {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO170__FUNC_AUD_CLK_MISO&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO171__FUNC_AUD_SYNC_MISO&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_dat_mosi_off: aud-dat-mosi-off-pins {</div><div class='add'>+		pins-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO168__FUNC_GPIO168&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO169__FUNC_GPIO169&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-down;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_dat_mosi_on: aud-dat-mosi-on-pins {</div><div class='add'>+		pins-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO168__FUNC_AUD_DAT_MOSI0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO169__FUNC_AUD_DAT_MOSI1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_dat_miso_off: aud-dat-miso-off-pins {</div><div class='add'>+		pins-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO172__FUNC_GPIO172&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO173__FUNC_GPIO173&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-down;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_dat_miso_on: aud-dat-miso-on-pins {</div><div class='add'>+		pins-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO172__FUNC_AUD_DAT_MISO0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO173__FUNC_AUD_DAT_MISO1&gt;;</div><div class='add'>+			input-schmitt-enable;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_gpio_i2s0_off: aud-gpio-i2s0-off-pins {</div><div class='add'>+		pins-sdata {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO3__FUNC_GPIO3&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_gpio_i2s0_on: aud-gpio-i2s0-on-pins {</div><div class='add'>+		pins-sdata {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO3__FUNC_I2S0_DI&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_gpio_i2s1_off: aud-gpio-i2s-off-pins {</div><div class='add'>+		pins-clk-sdata {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO56__FUNC_GPIO56&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO57__FUNC_GPIO57&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO58__FUNC_GPIO58&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO59__FUNC_GPIO59&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_gpio_i2s1_on: aud-gpio-i2s1-on-pins {</div><div class='add'>+		pins-clk-sdata {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO56__FUNC_I2S1_DO&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO57__FUNC_I2S1_BCK&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO58__FUNC_I2S1_LRCK&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO59__FUNC_I2S1_MCK&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_gpio_i2s2_off: aud-gpio-i2s2-off-pins {</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO26__FUNC_GPIO26&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO27__FUNC_GPIO27&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_gpio_i2s2_on: aud-gpio-i2s2-on-pins {</div><div class='add'>+		pins-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO26__FUNC_I2S2_BCK&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO27__FUNC_I2S2_LRCK&gt;;</div><div class='add'>+			drive-strength = &lt;4&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_gpio_i2s3_off: aud-gpio-i2s3-off-pins {</div><div class='add'>+		pins-sdata {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO4__FUNC_GPIO4&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_gpio_i2s3_on: aud-gpio-i2s3-on-pins {</div><div class='add'>+		pins-sdata {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO4__FUNC_I2S3_DO&gt;;</div><div class='add'>+			drive-strength = &lt;4&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_gpio_pcm_off: aud-gpio-pcm-off-pins {</div><div class='add'>+		pins-clk-sdata {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO115__FUNC_GPIO115&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO116__FUNC_GPIO116&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO117__FUNC_GPIO117&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO118__FUNC_GPIO118&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_gpio_pcm_on: aud-gpio-pcm-on-pins {</div><div class='add'>+		pins-clk-sdata {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO115__FUNC_PCM_CLK&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO116__FUNC_PCM_SYNC&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO117__FUNC_PCM_DI&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO118__FUNC_PCM_DO&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_gpio_dmic_sec: aud-gpio-dmic-sec-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO23__FUNC_GPIO23&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bt_pins_reset: bt-reset-pins {</div><div class='add'>+		pins-bt-reset {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO155__FUNC_GPIO155&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dpi_pins_sleep: dpi-sleep-pins {</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO103__FUNC_GPIO103&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO104__FUNC_GPIO104&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO105__FUNC_GPIO105&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO106__FUNC_GPIO106&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO107__FUNC_GPIO107&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO108__FUNC_GPIO108&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO109__FUNC_GPIO109&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO110__FUNC_GPIO110&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO111__FUNC_GPIO111&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO112__FUNC_GPIO112&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO113__FUNC_GPIO113&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO114__FUNC_GPIO114&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO101__FUNC_GPIO101&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO100__FUNC_GPIO100&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO102__FUNC_GPIO102&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO99__FUNC_GPIO99&gt;;</div><div class='add'>+			drive-strength = &lt;10&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dpi_pins_default: dpi-default-pins {</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO103__FUNC_DPI_DATA0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO104__FUNC_DPI_DATA1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO105__FUNC_DPI_DATA2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO106__FUNC_DPI_DATA3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO107__FUNC_DPI_DATA4&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO108__FUNC_DPI_DATA5&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO109__FUNC_DPI_DATA6&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO110__FUNC_DPI_DATA7&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO111__FUNC_DPI_DATA8&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO112__FUNC_DPI_DATA9&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO113__FUNC_DPI_DATA10&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO114__FUNC_DPI_DATA11&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO101__FUNC_DPI_HSYNC&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO100__FUNC_DPI_VSYNC&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO102__FUNC_DPI_DE&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO99__FUNC_DPI_PCLK&gt;;</div><div class='add'>+			drive-strength = &lt;10&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ec_ap_int: cros-ec-int-pins {</div><div class='add'>+		pins-ec-ap-int-odl {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO13__FUNC_GPIO13&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	edp_panel_fixed_pins: edp-panel-fixed-pins {</div><div class='add'>+		pins-vreg-en {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO153__FUNC_GPIO153&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	en_pp1800_dpbrdg: en-pp1800-dpbrdg-pins {</div><div class='add'>+		pins-vreg-en {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO39__FUNC_GPIO39&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gsc_int: gsc-int-pins {</div><div class='add'>+		pins-gsc-ap-int-odl {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO15__FUNC_GPIO15&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c0_pins: i2c0-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO128__FUNC_SDA0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO127__FUNC_SCL0&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+			drive-strength = &lt;4&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c1_pins: i2c1-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO130__FUNC_SDA1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO129__FUNC_SCL1&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+			drive-strength = &lt;4&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c2_pins: i2c2-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO132__FUNC_SDA2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO131__FUNC_SCL2&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+			drive-strength = &lt;4&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c3_pins: i2c3-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO134__FUNC_SDA3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO133__FUNC_SCL3&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+			drive-strength = &lt;4&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c5_pins: i2c5-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO138__FUNC_SDA5&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO137__FUNC_SCL5&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+			drive-strength = &lt;4&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	it6505_pins: it6505-pins {</div><div class='add'>+		pins-hpd {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO10__FUNC_GPIO10&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-int {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO8__FUNC_GPIO8&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-reset {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO177__FUNC_GPIO177&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc0_pins_default: mmc0-default-pins {</div><div class='add'>+		pins-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO68__FUNC_MSDC0_CLK&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO71__FUNC_MSDC0_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO72__FUNC_MSDC0_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO73__FUNC_MSDC0_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO74__FUNC_MSDC0_DAT3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO75__FUNC_MSDC0_DAT4&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO76__FUNC_MSDC0_DAT5&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO77__FUNC_MSDC0_DAT6&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO78__FUNC_MSDC0_DAT7&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO69__FUNC_MSDC0_CMD&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-rst {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO70__FUNC_MSDC0_RSTB&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc0_pins_uhs: mmc0-uhs-pins {</div><div class='add'>+		pins-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO68__FUNC_MSDC0_CLK&gt;;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO71__FUNC_MSDC0_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO72__FUNC_MSDC0_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO73__FUNC_MSDC0_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO74__FUNC_MSDC0_DAT3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO75__FUNC_MSDC0_DAT4&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO76__FUNC_MSDC0_DAT5&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO77__FUNC_MSDC0_DAT6&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO78__FUNC_MSDC0_DAT7&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO69__FUNC_MSDC0_CMD&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-ds {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO67__FUNC_MSDC0_DSL&gt;;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-rst {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO70__FUNC_MSDC0_RSTB&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc1_pins_default: mmc1-default-pins {</div><div class='add'>+		pins-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO84__FUNC_MSDC1_CLK&gt;;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO86__FUNC_MSDC1_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO87__FUNC_MSDC1_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO88__FUNC_MSDC1_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO89__FUNC_MSDC1_DAT3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO85__FUNC_MSDC1_CMD&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc1_pins_uhs: mmc1-uhs-pins {</div><div class='add'>+		pins-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO84__FUNC_MSDC1_CLK&gt;;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO86__FUNC_MSDC1_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO87__FUNC_MSDC1_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO88__FUNC_MSDC1_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO89__FUNC_MSDC1_DAT3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO85__FUNC_MSDC1_CMD&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc1_pins_eint: mmc1-eint-pins {</div><div class='add'>+		pins-dat1 {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO87__FUNC_GPIO87&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	nor_pins_default: nor-default-pins {</div><div class='add'>+		pins-clk-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO63__FUNC_SPINOR_IO0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO61__FUNC_SPINOR_CK&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO64__FUNC_SPINOR_IO1&gt;;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-down;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-cs-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO62__FUNC_SPINOR_CS&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO65__FUNC_SPINOR_IO2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO66__FUNC_SPINOR_IO3&gt;;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pen_eject: pen-eject-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO18__FUNC_GPIO18&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			/* External pull-up. */</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pwm0_pin: disp-pwm-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO97__FUNC_DISP_PWM&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	speaker_codec_pins_default: speaker-codec-default-pins {</div><div class='add'>+		pins-sdb {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO150__FUNC_GPIO150&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	scp_pins: scp-default-pins {</div><div class='add'>+		pins-scp-uart {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO48__FUNC_TP_URXD2_AO&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO49__FUNC_TP_UTXD2_AO&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi1_pins: spi1-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO40__FUNC_SPI1_CLK_A&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO41__FUNC_SPI1_CSB_A&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO42__FUNC_SPI1_MO_A&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO43__FUNC_SPI1_MI_A&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi2_pins: spi2-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO44__FUNC_SPI2_CLK_A&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO45__FUNC_GPIO45&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO46__FUNC_SPI2_MO_A&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO47__FUNC_SPI2_MI_A&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spmi_pins: spmi-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO183__FUNC_SPMI_SCL&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO184__FUNC_SPMI_SDA&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	touchscreen_pins: touchscreen-pins {</div><div class='add'>+		pins-irq {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO12__FUNC_GPIO12&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-reset {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO60__FUNC_GPIO60&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-report-sw {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO37__FUNC_GPIO37&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	trackpad_pin: trackpad-default-pins {</div><div class='add'>+		pins-int-n {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO11__FUNC_GPIO11&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-disable; /* pulled externally */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wifi_enable_pin: wifi-enable-pins {</div><div class='add'>+		pins-wifi-enable {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO54__FUNC_GPIO54&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wifi_wakeup_pin: wifi-wakeup-pins {</div><div class='add'>+		pins-wifi-wakeup {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO7__FUNC_GPIO7&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm0_pin&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwrap {</div><div class='add'>+	pmic {</div><div class='add'>+		compatible = "mediatek,mt6366", "mediatek,mt6358";</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 201 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		mt6366codec: audio-codec {</div><div class='add'>+			compatible = "mediatek,mt6366-sound", "mediatek,mt6358-sound";</div><div class='add'>+			Avdd-supply = &lt;&amp;mt6366_vaud28_reg&gt;;</div><div class='add'>+			mediatek,dmic-mode = &lt;1&gt;; /* one-wire */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mt6366_regulators: regulators {</div><div class='add'>+			compatible = "mediatek,mt6366-regulator", "mediatek,mt6358-regulator";</div><div class='add'>+			vsys-ldo1-supply = &lt;&amp;pp4200_z2&gt;;</div><div class='add'>+			vsys-ldo2-supply = &lt;&amp;pp4200_z2&gt;;</div><div class='add'>+			vsys-ldo3-supply = &lt;&amp;pp4200_z2&gt;;</div><div class='add'>+			vsys-vcore-supply = &lt;&amp;pp4200_z2&gt;;</div><div class='add'>+			vsys-vdram1-supply = &lt;&amp;pp4200_z2&gt;;</div><div class='add'>+			vsys-vgpu-supply = &lt;&amp;pp4200_z2&gt;;</div><div class='add'>+			vsys-vmodem-supply = &lt;&amp;pp4200_z2&gt;;</div><div class='add'>+			vsys-vpa-supply = &lt;&amp;pp4200_z2&gt;;</div><div class='add'>+			vsys-vproc11-supply = &lt;&amp;pp4200_z2&gt;;</div><div class='add'>+			vsys-vproc12-supply = &lt;&amp;pp4200_z2&gt;;</div><div class='add'>+			vsys-vs1-supply = &lt;&amp;pp4200_z2&gt;;</div><div class='add'>+			vsys-vs2-supply = &lt;&amp;pp4200_z2&gt;;</div><div class='add'>+			vs1-ldo1-supply = &lt;&amp;mt6366_vs1_reg&gt;;</div><div class='add'>+			vs2-ldo1-supply = &lt;&amp;mt6366_vdram1_reg&gt;;</div><div class='add'>+			vs2-ldo2-supply = &lt;&amp;mt6366_vs2_reg&gt;;</div><div class='add'>+			vs2-ldo3-supply = &lt;&amp;mt6366_vs2_reg&gt;;</div><div class='add'>+</div><div class='add'>+			vcore {</div><div class='add'>+				regulator-name = "pp0750_dvdd_core";</div><div class='add'>+				regulator-min-microvolt = &lt;550000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;6250&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;200&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;MT6397_BUCK_MODE_AUTO</div><div class='add'>+							   MT6397_BUCK_MODE_FORCE_PWM&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6366_vdram1_reg: vdram1 {</div><div class='add'>+				regulator-name = "pp1125_emi_vdd2";</div><div class='add'>+				regulator-min-microvolt = &lt;1125000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1125000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12500&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;0&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;MT6397_BUCK_MODE_AUTO</div><div class='add'>+							   MT6397_BUCK_MODE_FORCE_PWM&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6366_vgpu_reg: vgpu {</div><div class='add'>+				/*</div><div class='add'>+				 * Called "ppvar_dvdd_gpu" in the schematic.</div><div class='add'>+				 * Called "ppvar_dvdd_vgpu" here to match</div><div class='add'>+				 * regulator coupling requirements.</div><div class='add'>+				 */</div><div class='add'>+				regulator-name = "ppvar_dvdd_vgpu";</div><div class='add'>+				regulator-min-microvolt = &lt;500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;950000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;6250&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;200&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;MT6397_BUCK_MODE_AUTO</div><div class='add'>+							   MT6397_BUCK_MODE_FORCE_PWM&gt;;</div><div class='add'>+				regulator-coupled-with = &lt;&amp;mt6366_vsram_gpu_reg&gt;;</div><div class='add'>+				regulator-coupled-max-spread = &lt;100000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6366_vproc11_reg: vproc11 {</div><div class='add'>+				regulator-name = "ppvar_dvdd_proc_bc_mt6366";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;6250&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;200&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;MT6397_BUCK_MODE_AUTO</div><div class='add'>+							   MT6397_BUCK_MODE_FORCE_PWM&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6366_vproc12_reg: vproc12 {</div><div class='add'>+				regulator-name = "ppvar_dvdd_proc_lc";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;6250&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;200&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;MT6397_BUCK_MODE_AUTO</div><div class='add'>+							   MT6397_BUCK_MODE_FORCE_PWM&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6366_vs1_reg: vs1 {</div><div class='add'>+				regulator-name = "pp2000_vs1";</div><div class='add'>+				regulator-min-microvolt = &lt;2000000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2000000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12500&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;0&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6366_vs2_reg: vs2 {</div><div class='add'>+				regulator-name = "pp1350_vs2";</div><div class='add'>+				regulator-min-microvolt = &lt;1350000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1350000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;12500&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;0&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			va12 {</div><div class='add'>+				regulator-name = "pp1200_va12";</div><div class='add'>+				regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;270&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6366_vaud28_reg: vaud28 {</div><div class='add'>+				regulator-name = "pp2800_vaud28";</div><div class='add'>+				regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;270&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6366_vaux18_reg: vaux18 {</div><div class='add'>+				regulator-name = "pp1840_vaux18";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1840000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;270&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6366_vbif28_reg: vbif28 {</div><div class='add'>+				regulator-name = "pp2800_vbif28";</div><div class='add'>+				regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;270&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6366_vcn18_reg: vcn18 {</div><div class='add'>+				regulator-name = "pp1800_vcn18_x";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;270&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6366_vcn28_reg: vcn28 {</div><div class='add'>+				regulator-name = "pp2800_vcn28_x";</div><div class='add'>+				regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;270&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6366_vefuse_reg: vefuse {</div><div class='add'>+				regulator-name = "pp1800_vefuse";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;270&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6366_vfe28_reg: vfe28 {</div><div class='add'>+				regulator-name = "pp2800_vfe28_x";</div><div class='add'>+				regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;270&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6366_vemc_reg: vemc {</div><div class='add'>+				regulator-name = "pp3000_vemc";</div><div class='add'>+				regulator-min-microvolt = &lt;3000000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3000000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;60&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6366_vibr_reg: vibr {</div><div class='add'>+				regulator-name = "pp2800_vibr_x";</div><div class='add'>+				regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;60&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6366_vio18_reg: vio18 {</div><div class='add'>+				regulator-name = "pp1800_vio18_s3";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;2700&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6366_vio28_reg: vio28 {</div><div class='add'>+				regulator-name = "pp2800_vio28_x";</div><div class='add'>+				regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;270&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6366_vm18_reg: vm18 {</div><div class='add'>+				regulator-name = "pp1800_emi_vdd1";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1840000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;325&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6366_vmc_reg: vmc {</div><div class='add'>+				regulator-name = "pp3000_vmc";</div><div class='add'>+				regulator-min-microvolt = &lt;3000000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3000000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;60&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6366_vmddr_reg: vmddr {</div><div class='add'>+				regulator-name = "pm0750_emi_vmddr";</div><div class='add'>+				regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;750000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;325&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6366_vmch_reg: vmch {</div><div class='add'>+				regulator-name = "pp3000_vmch";</div><div class='add'>+				regulator-min-microvolt = &lt;3000000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3000000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;60&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6366_vcn33_reg: vcn33 {</div><div class='add'>+				regulator-name = "pp3300_vcn33_x";</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;270&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vdram2 {</div><div class='add'>+				regulator-name = "pp0600_emi_vddq";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;3300&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6366_vrf12_reg: vrf12 {</div><div class='add'>+				regulator-name = "pp1200_vrf12_x";</div><div class='add'>+				regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;120&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6366_vrf18_reg: vrf18 {</div><div class='add'>+				regulator-name = "pp1800_vrf18_x";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;120&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vsim1 {</div><div class='add'>+				regulator-name = "pp1860_vsim1_x";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1860000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;540&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6366_vsim2_reg: vsim2 {</div><div class='add'>+				regulator-name = "pp2760_vsim2_x";</div><div class='add'>+				regulator-min-microvolt = &lt;2700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2760000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;540&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6366_vsram_gpu_reg: vsram-gpu {</div><div class='add'>+				regulator-name = "pp0900_dvdd_sram_gpu";</div><div class='add'>+				regulator-min-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1050000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;6250&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;240&gt;;</div><div class='add'>+				regulator-coupled-with = &lt;&amp;mt6366_vgpu_reg&gt;;</div><div class='add'>+				regulator-coupled-max-spread = &lt;100000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6366_vsram_others_reg: vsram-others {</div><div class='add'>+				regulator-name = "pp0900_dvdd_sram_core";</div><div class='add'>+				regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;900000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;6250&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;240&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6366_vsram_proc11_reg: vsram-proc11 {</div><div class='add'>+				regulator-name = "pp0900_dvdd_sram_bc";</div><div class='add'>+				regulator-min-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1120000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;6250&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;240&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6366_vsram_proc12_reg: vsram-proc12 {</div><div class='add'>+				regulator-name = "pp0900_dvdd_sram_lc";</div><div class='add'>+				regulator-min-microvolt = &lt;850000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1120000&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;6250&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;240&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vusb {</div><div class='add'>+				regulator-name = "pp3070_vusb";</div><div class='add'>+				regulator-min-microvolt = &lt;3000000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3070000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;270&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vxo22 {</div><div class='add'>+				regulator-name = "pp2240_vxo22";</div><div class='add'>+				regulator-min-microvolt = &lt;2200000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2240000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;120&gt;;</div><div class='add'>+				/* Feeds DCXO internally */</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rtc {</div><div class='add'>+			compatible = "mediatek,mt6366-rtc", "mediatek,mt6358-rtc";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;scp {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;scp_pins&gt;;</div><div class='add'>+	firmware-name = "mediatek/mt8186/scp.img";</div><div class='add'>+	memory-region = &lt;&amp;scp_mem&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	cros-ec-rpmsg {</div><div class='add'>+		compatible = "google,cros-ec-rpmsg";</div><div class='add'>+		mediatek,rpmsg-name = "cros-ec-rpmsg";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;spi1_pins&gt;;</div><div class='add'>+	mediatek,pad-select = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	cros_ec: ec@0 {</div><div class='add'>+		compatible = "google,cros-ec-spi";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 13 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;ec_ap_int&gt;;</div><div class='add'>+		spi-max-frequency = &lt;1000000&gt;;</div><div class='add'>+</div><div class='add'>+		i2c_tunnel: i2c-tunnel {</div><div class='add'>+			compatible = "google,cros-ec-i2c-tunnel";</div><div class='add'>+			google,remote-bus = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		typec {</div><div class='add'>+			compatible = "google,cros-ec-typec";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			usb_c0: connector@0 {</div><div class='add'>+				compatible = "usb-c-connector";</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				label = "left";</div><div class='add'>+				power-role = "dual";</div><div class='add'>+				data-role = "host";</div><div class='add'>+				try-power-role = "source";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			usb_c1: connector@1 {</div><div class='add'>+				compatible = "usb-c-connector";</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				label = "right";</div><div class='add'>+				power-role = "dual";</div><div class='add'>+				data-role = "host";</div><div class='add'>+				try-power-role = "source";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usbc_extcon: extcon0 {</div><div class='add'>+			compatible = "google,extcon-usbc-cros-ec";</div><div class='add'>+			google,usb-port-id = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;spi2_pins&gt;;</div><div class='add'>+	cs-gpios = &lt;&amp;pio 45 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	mediatek,pad-select = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	tpm@0 {</div><div class='add'>+		compatible = "google,cr50";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 15 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;gsc_int&gt;;</div><div class='add'>+		spi-max-frequency = &lt;1000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ssusb0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ssusb1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;u3phy0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;u3phy1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_host0 {</div><div class='add'>+	vbus-supply = &lt;&amp;pp3300_s3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_host1 {</div><div class='add'>+	vbus-supply = &lt;&amp;usb_p1_vbus&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;watchdog {</div><div class='add'>+	mediatek,reset-by-toprgu;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include &lt;arm/cros-ec-keyboard.dtsi&gt;</div><div class='add'>+#include &lt;arm/cros-ec-sbs.dtsi&gt;</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts<br/>new file mode 100644<br/>index 000000000000..2667a7424200<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8186-evb.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8186-evb.dts</a></div><div class='hunk'>@@ -0,0 +1,221 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2022 MediaTek Inc.</div><div class='add'>+ */</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8186.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "MediaTek MT8186 evaluation board";</div><div class='add'>+	chassis-type = "embedded";</div><div class='add'>+	compatible = "mediatek,mt8186-evb", "mediatek,mt8186";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:921600n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0 0x40000000 0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c0_pins&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	i2c-scl-internal-delay-ns = &lt;8000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c1_pins&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	i2c-scl-internal-delay-ns = &lt;10000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c2_pins&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c3_pins&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c4_pins&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c5 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c5_pins&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c6 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c6_pins&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c7 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c7_pins&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c8 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c8_pins&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c9 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c9_pins&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	i2c0_pins: i2c0-default-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO128__FUNC_SDA0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO127__FUNC_SCL0&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+			drive-strength-microamp = &lt;1000&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c1_pins: i2c1-default-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO130__FUNC_SDA1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO129__FUNC_SCL1&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+			drive-strength-microamp = &lt;1000&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c2_pins: i2c2-default-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO132__FUNC_SDA2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO131__FUNC_SCL2&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+			drive-strength-microamp = &lt;1000&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c3_pins: i2c3-default-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO134__FUNC_SDA3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO133__FUNC_SCL3&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+			drive-strength-microamp = &lt;1000&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c4_pins: i2c4-default-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO136__FUNC_SDA4&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO135__FUNC_SCL4&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+			drive-strength-microamp = &lt;1000&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c5_pins: i2c5-default-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO138__FUNC_SDA5&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO137__FUNC_SCL5&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+			drive-strength-microamp = &lt;1000&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c6_pins: i2c6-default-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO140__FUNC_SDA6&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO139__FUNC_SCL6&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PULL_SET_RSEL_001&gt;;</div><div class='add'>+			drive-strength-microamp = &lt;1000&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c7_pins: i2c7-default-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO142__FUNC_SDA7&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO141__FUNC_SCL7&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+			drive-strength-microamp = &lt;1000&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c8_pins: i2c8-default-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO144__FUNC_SDA8&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO143__FUNC_SCL8&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+			drive-strength-microamp = &lt;1000&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c9_pins: i2c9-default-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO146__FUNC_SDA9&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO145__FUNC_SCL9&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PULL_SET_RSEL_001&gt;;</div><div class='add'>+			drive-strength-microamp = &lt;1000&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;u3phy0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;u3phy1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi<br/>new file mode 100644<br/>index 000000000000..b91f88ffae0e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8186.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8186.dtsi</a></div><div class='hunk'>@@ -0,0 +1,2521 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2022 MediaTek Inc.</div><div class='add'>+ * Author: Allen-KH Cheng &lt;allen-kh.cheng@mediatek.com&gt;</div><div class='add'>+ */</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include &lt;dt-bindings/clock/mt8186-clk.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gce/mt8186-gce.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/memory/mt8186-memory-port.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/mt8186-pinfunc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/power/mt8186-power.h&gt;</div><div class='add'>+#include &lt;dt-bindings/phy/phy.h&gt;</div><div class='add'>+#include &lt;dt-bindings/reset/mt8186-resets.h&gt;</div><div class='add'>+#include &lt;dt-bindings/thermal/thermal.h&gt;</div><div class='add'>+#include &lt;dt-bindings/thermal/mediatek,lvts-thermal.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "mediatek,mt8186";</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ovl0 = &amp;ovl0;</div><div class='add'>+		ovl-2l0 = &amp;ovl_2l0;</div><div class='add'>+		rdma0 = &amp;rdma0;</div><div class='add'>+		rdma1 = &amp;rdma1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fhctl: fhctl@1000ce00 {</div><div class='add'>+		compatible = "mediatek,mt8186-fhctl";</div><div class='add'>+		clocks = &lt;&amp;apmixedsys CLK_APMIXED_TVDPLL&gt;;</div><div class='add'>+		reg = &lt;0 0x1000ce00 0 0x200&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cci: cci {</div><div class='add'>+		compatible = "mediatek,mt8186-cci";</div><div class='add'>+		clocks = &lt;&amp;mcusys CLK_MCU_ARMPLL_BUS_SEL&gt;,</div><div class='add'>+			 &lt;&amp;apmixedsys CLK_APMIXED_MAINPLL&gt;;</div><div class='add'>+		clock-names = "cci", "intermediate";</div><div class='add'>+		operating-points-v2 = &lt;&amp;cci_opp&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cci_opp: opp-table-cci {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+		opp-shared;</div><div class='add'>+</div><div class='add'>+		cci_opp_0: opp-500000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;500000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;600000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cci_opp_1: opp-560000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;560000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;675000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cci_opp_2: opp-612000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;612000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;693750&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cci_opp_3: opp-682000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;682000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;718750&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cci_opp_4: opp-752000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;752000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;743750&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cci_opp_5: opp-822000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;822000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;768750&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cci_opp_6: opp-875000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;875000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;781250&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cci_opp_7: opp-927000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;927000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;800000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cci_opp_8: opp-980000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;980000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;818750&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cci_opp_9: opp-1050000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1050000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;843750&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cci_opp_10: opp-1120000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1120000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;862500&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cci_opp_11: opp-1155000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1155000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;887500&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cci_opp_12: opp-1190000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1190000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;906250&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cci_opp_13: opp-1260000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1260000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;950000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cci_opp_14: opp-1330000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1330000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;993750&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cci_opp_15: opp-1400000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1400000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1031250&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cluster0_opp: opp-table-cluster0 {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+		opp-shared;</div><div class='add'>+</div><div class='add'>+		opp-500000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;500000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;600000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;cci_opp_0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-774000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;774000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;675000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;cci_opp_1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-875000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;875000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;700000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;cci_opp_2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-975000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;975000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;725000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;cci_opp_3&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1075000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1075000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;750000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;cci_opp_4&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1175000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1175000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;775000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;cci_opp_5&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1275000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1275000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;800000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;cci_opp_6&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1375000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1375000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;825000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;cci_opp_7&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1500000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1500000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;856250&gt;;</div><div class='add'>+			required-opps = &lt;&amp;cci_opp_8&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1618000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1618000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;875000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;cci_opp_9&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1666000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1666000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;900000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;cci_opp_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1733000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1733000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;925000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;cci_opp_11&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1800000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1800000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;950000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;cci_opp_12&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1866000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1866000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;981250&gt;;</div><div class='add'>+			required-opps = &lt;&amp;cci_opp_13&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1933000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1933000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1006250&gt;;</div><div class='add'>+			required-opps = &lt;&amp;cci_opp_14&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-2000000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2000000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1031250&gt;;</div><div class='add'>+			required-opps = &lt;&amp;cci_opp_15&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cluster1_opp: opp-table-cluster1 {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+		opp-shared;</div><div class='add'>+</div><div class='add'>+		opp-774000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;774000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;675000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;cci_opp_0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-835000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;835000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;693750&gt;;</div><div class='add'>+			required-opps = &lt;&amp;cci_opp_1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-919000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;919000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;718750&gt;;</div><div class='add'>+			required-opps = &lt;&amp;cci_opp_2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1002000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1002000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;743750&gt;;</div><div class='add'>+			required-opps = &lt;&amp;cci_opp_3&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1085000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1085000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;775000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;cci_opp_4&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1169000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1169000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;800000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;cci_opp_5&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1308000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1308000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;843750&gt;;</div><div class='add'>+			required-opps = &lt;&amp;cci_opp_6&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1419000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1419000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;875000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;cci_opp_7&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1530000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1530000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;912500&gt;;</div><div class='add'>+			required-opps = &lt;&amp;cci_opp_8&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1670000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1670000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;956250&gt;;</div><div class='add'>+			required-opps = &lt;&amp;cci_opp_9&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1733000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1733000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;981250&gt;;</div><div class='add'>+			required-opps = &lt;&amp;cci_opp_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1796000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1796000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1012500&gt;;</div><div class='add'>+			required-opps = &lt;&amp;cci_opp_11&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1860000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1860000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1037500&gt;;</div><div class='add'>+			required-opps = &lt;&amp;cci_opp_12&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1923000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1923000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1062500&gt;;</div><div class='add'>+			required-opps = &lt;&amp;cci_opp_13&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cluster1_opp_14: opp-1986000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1986000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1093750&gt;;</div><div class='add'>+			required-opps = &lt;&amp;cci_opp_14&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cluster1_opp_15: opp-2050000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2050000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1118750&gt;;</div><div class='add'>+			required-opps = &lt;&amp;cci_opp_15&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu-map {</div><div class='add'>+			cluster0 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu2&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu3&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core4 {</div><div class='add'>+					cpu = &lt;&amp;cpu4&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core5 {</div><div class='add'>+					cpu = &lt;&amp;cpu5&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core6 {</div><div class='add'>+					cpu = &lt;&amp;cpu6&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core7 {</div><div class='add'>+					cpu = &lt;&amp;cpu7&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x000&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clock-frequency = &lt;2000000000&gt;;</div><div class='add'>+			clocks = &lt;&amp;mcusys CLK_MCU_ARMPLL_LL_SEL&gt;,</div><div class='add'>+				 &lt;&amp;apmixedsys CLK_APMIXED_MAINPLL&gt;;</div><div class='add'>+			clock-names = "cpu", "intermediate";</div><div class='add'>+			operating-points-v2 = &lt;&amp;cluster0_opp&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;84&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;382&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_ret_l &amp;cpu_off_l&gt;;</div><div class='add'>+			i-cache-size = &lt;32768&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;128&gt;;</div><div class='add'>+			d-cache-size = &lt;32768&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			mediatek,cci = &lt;&amp;cci&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@100 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x100&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clock-frequency = &lt;2000000000&gt;;</div><div class='add'>+			clocks = &lt;&amp;mcusys CLK_MCU_ARMPLL_LL_SEL&gt;,</div><div class='add'>+				 &lt;&amp;apmixedsys CLK_APMIXED_MAINPLL&gt;;</div><div class='add'>+			clock-names = "cpu", "intermediate";</div><div class='add'>+			operating-points-v2 = &lt;&amp;cluster0_opp&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;84&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;382&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_ret_l &amp;cpu_off_l&gt;;</div><div class='add'>+			i-cache-size = &lt;32768&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;128&gt;;</div><div class='add'>+			d-cache-size = &lt;32768&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			mediatek,cci = &lt;&amp;cci&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@200 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x200&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clock-frequency = &lt;2000000000&gt;;</div><div class='add'>+			clocks = &lt;&amp;mcusys CLK_MCU_ARMPLL_LL_SEL&gt;,</div><div class='add'>+				 &lt;&amp;apmixedsys CLK_APMIXED_MAINPLL&gt;;</div><div class='add'>+			clock-names = "cpu", "intermediate";</div><div class='add'>+			operating-points-v2 = &lt;&amp;cluster0_opp&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;84&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;382&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_ret_l &amp;cpu_off_l&gt;;</div><div class='add'>+			i-cache-size = &lt;32768&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;128&gt;;</div><div class='add'>+			d-cache-size = &lt;32768&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			mediatek,cci = &lt;&amp;cci&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@300 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x300&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clock-frequency = &lt;2000000000&gt;;</div><div class='add'>+			clocks = &lt;&amp;mcusys CLK_MCU_ARMPLL_LL_SEL&gt;,</div><div class='add'>+				 &lt;&amp;apmixedsys CLK_APMIXED_MAINPLL&gt;;</div><div class='add'>+			clock-names = "cpu", "intermediate";</div><div class='add'>+			operating-points-v2 = &lt;&amp;cluster0_opp&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;84&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;382&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_ret_l &amp;cpu_off_l&gt;;</div><div class='add'>+			i-cache-size = &lt;32768&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;128&gt;;</div><div class='add'>+			d-cache-size = &lt;32768&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			mediatek,cci = &lt;&amp;cci&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu4: cpu@400 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x400&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clock-frequency = &lt;2000000000&gt;;</div><div class='add'>+			clocks = &lt;&amp;mcusys CLK_MCU_ARMPLL_LL_SEL&gt;,</div><div class='add'>+				 &lt;&amp;apmixedsys CLK_APMIXED_MAINPLL&gt;;</div><div class='add'>+			clock-names = "cpu", "intermediate";</div><div class='add'>+			operating-points-v2 = &lt;&amp;cluster0_opp&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;84&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;382&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_ret_l &amp;cpu_off_l&gt;;</div><div class='add'>+			i-cache-size = &lt;32768&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;128&gt;;</div><div class='add'>+			d-cache-size = &lt;32768&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			mediatek,cci = &lt;&amp;cci&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu5: cpu@500 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x500&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clock-frequency = &lt;2000000000&gt;;</div><div class='add'>+			clocks = &lt;&amp;mcusys CLK_MCU_ARMPLL_LL_SEL&gt;,</div><div class='add'>+				 &lt;&amp;apmixedsys CLK_APMIXED_MAINPLL&gt;;</div><div class='add'>+			clock-names = "cpu", "intermediate";</div><div class='add'>+			operating-points-v2 = &lt;&amp;cluster0_opp&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;84&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;382&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_ret_l &amp;cpu_off_l&gt;;</div><div class='add'>+			i-cache-size = &lt;32768&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;128&gt;;</div><div class='add'>+			d-cache-size = &lt;32768&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			mediatek,cci = &lt;&amp;cci&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu6: cpu@600 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a76";</div><div class='add'>+			reg = &lt;0x600&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clock-frequency = &lt;2050000000&gt;;</div><div class='add'>+			clocks = &lt;&amp;mcusys CLK_MCU_ARMPLL_BL_SEL&gt;,</div><div class='add'>+				 &lt;&amp;apmixedsys CLK_APMIXED_MAINPLL&gt;;</div><div class='add'>+			clock-names = "cpu", "intermediate";</div><div class='add'>+			operating-points-v2 = &lt;&amp;cluster1_opp&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;335&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_ret_b &amp;cpu_off_b&gt;;</div><div class='add'>+			i-cache-size = &lt;65536&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;65536&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_1&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			mediatek,cci = &lt;&amp;cci&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu7: cpu@700 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a76";</div><div class='add'>+			reg = &lt;0x700&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clock-frequency = &lt;2050000000&gt;;</div><div class='add'>+			clocks = &lt;&amp;mcusys CLK_MCU_ARMPLL_BL_SEL&gt;,</div><div class='add'>+				 &lt;&amp;apmixedsys CLK_APMIXED_MAINPLL&gt;;</div><div class='add'>+			clock-names = "cpu", "intermediate";</div><div class='add'>+			operating-points-v2 = &lt;&amp;cluster1_opp&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;335&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_ret_b &amp;cpu_off_b&gt;;</div><div class='add'>+			i-cache-size = &lt;65536&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;65536&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_1&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			mediatek,cci = &lt;&amp;cci&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		idle-states {</div><div class='add'>+			entry-method = "psci";</div><div class='add'>+</div><div class='add'>+			cpu_ret_l: cpu-retention-l {</div><div class='add'>+				compatible = "arm,idle-state";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x00010001&gt;;</div><div class='add'>+				local-timer-stop;</div><div class='add'>+				entry-latency-us = &lt;50&gt;;</div><div class='add'>+				exit-latency-us = &lt;100&gt;;</div><div class='add'>+				min-residency-us = &lt;1600&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cpu_ret_b: cpu-retention-b {</div><div class='add'>+				compatible = "arm,idle-state";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x00010001&gt;;</div><div class='add'>+				local-timer-stop;</div><div class='add'>+				entry-latency-us = &lt;50&gt;;</div><div class='add'>+				exit-latency-us = &lt;100&gt;;</div><div class='add'>+				min-residency-us = &lt;1400&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cpu_off_l: cpu-off-l {</div><div class='add'>+				compatible = "arm,idle-state";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x01010001&gt;;</div><div class='add'>+				local-timer-stop;</div><div class='add'>+				entry-latency-us = &lt;100&gt;;</div><div class='add'>+				exit-latency-us = &lt;250&gt;;</div><div class='add'>+				min-residency-us = &lt;2100&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cpu_off_b: cpu-off-b {</div><div class='add'>+				compatible = "arm,idle-state";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x01010001&gt;;</div><div class='add'>+				local-timer-stop;</div><div class='add'>+				entry-latency-us = &lt;100&gt;;</div><div class='add'>+				exit-latency-us = &lt;250&gt;;</div><div class='add'>+				min-residency-us = &lt;1900&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_0: l2-cache0 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-size = &lt;131072&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;512&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l3_0&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_1: l2-cache1 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-size = &lt;262144&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;512&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l3_0&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l3_0: l3-cache {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;3&gt;;</div><div class='add'>+			cache-size = &lt;1048576&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;1024&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk13m: fixed-factor-clock-13m {</div><div class='add'>+		compatible = "fixed-factor-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk26m&gt;;</div><div class='add'>+		clock-div = &lt;2&gt;;</div><div class='add'>+		clock-mult = &lt;1&gt;;</div><div class='add'>+		clock-output-names = "clk13m";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk26m: oscillator-26m {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;26000000&gt;;</div><div class='add'>+		clock-output-names = "clk26m";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk32k: oscillator-32k {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;32768&gt;;</div><div class='add'>+		clock-output-names = "clk32k";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpu_opp_table: opp-table-gpu {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		opp-299000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;299000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;612500&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0xff&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-332000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;332000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;625000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0xff&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-366000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;366000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;637500&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0xff&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-400000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;400000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;643750&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0xff&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-434000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;434000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;656250&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0xff&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-484000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;484000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;668750&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0xff&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-535000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;535000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;687500&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0xff&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-586000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;586000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;700000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0xff&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-637000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;637000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;712500&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0xff&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-690000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;690000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;737500&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0xff&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-743000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;743000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;756250&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0xff&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-796000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;796000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;781250&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0xff&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-850000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;850000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;800000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0xff&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-900000000-3 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;900000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;850000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0xcf&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-900000000-4 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;900000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;837500&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-900000000-5 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;900000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;825000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x20&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-950000000-3 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;950000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;900000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0xcf&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-950000000-4 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;950000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;875000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-950000000-5 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;950000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;850000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x20&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1000000000-3 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1000000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;950000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0xcf&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1000000000-4 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1000000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;912500&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1000000000-5 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1000000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;875000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x20&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu-a55 {</div><div class='add'>+		compatible = "arm,cortex-a55-pmu";</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &amp;ppi_cluster0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu-a76 {</div><div class='add'>+		compatible = "arm,cortex-a76-pmu";</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &amp;ppi_cluster1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-1.0";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		dma-ranges = &lt;0x0 0x0 0x0 0x0 0x4 0x0&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@c000000 {</div><div class='add'>+			compatible = "arm,gic-v3";</div><div class='add'>+			#interrupt-cells = &lt;4&gt;;</div><div class='add'>+			#redistributor-regions = &lt;1&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			reg = &lt;0 0x0c000000 0 0x40000&gt;,</div><div class='add'>+			      &lt;0 0x0c040000 0 0x200000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+</div><div class='add'>+			ppi-partitions {</div><div class='add'>+				ppi_cluster0: interrupt-partition-0 {</div><div class='add'>+					affinity = &lt;&amp;cpu0 &amp;cpu1 &amp;cpu2 &amp;cpu3 &amp;cpu4 &amp;cpu5&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				ppi_cluster1: interrupt-partition-1 {</div><div class='add'>+					affinity = &lt;&amp;cpu6 &amp;cpu7&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mcusys: syscon@c53a000 {</div><div class='add'>+			compatible = "mediatek,mt8186-mcusys", "syscon";</div><div class='add'>+			reg = &lt;0 0xc53a000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		topckgen: syscon@10000000 {</div><div class='add'>+			compatible = "mediatek,mt8186-topckgen", "syscon";</div><div class='add'>+			reg = &lt;0 0x10000000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		infracfg_ao: syscon@10001000 {</div><div class='add'>+			compatible = "mediatek,mt8186-infracfg_ao", "syscon";</div><div class='add'>+			reg = &lt;0 0x10001000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pericfg: syscon@10003000 {</div><div class='add'>+			compatible = "mediatek,mt8186-pericfg", "syscon";</div><div class='add'>+			reg = &lt;0 0x10003000 0 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pio: pinctrl@10005000 {</div><div class='add'>+			compatible = "mediatek,mt8186-pinctrl";</div><div class='add'>+			reg = &lt;0 0x10005000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x10002000 0 0x0200&gt;,</div><div class='add'>+			      &lt;0 0x10002200 0 0x0200&gt;,</div><div class='add'>+			      &lt;0 0x10002400 0 0x0200&gt;,</div><div class='add'>+			      &lt;0 0x10002600 0 0x0200&gt;,</div><div class='add'>+			      &lt;0 0x10002a00 0 0x0200&gt;,</div><div class='add'>+			      &lt;0 0x10002c00 0 0x0200&gt;,</div><div class='add'>+			      &lt;0 0x1000b000 0 0x1000&gt;;</div><div class='add'>+			reg-names = "iocfg0", "iocfg_lt", "iocfg_lm", "iocfg_lb",</div><div class='add'>+				    "iocfg_bl", "iocfg_rb", "iocfg_rt", "eint";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;pio 0 0 185&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			interrupts = &lt;GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		scpsys: syscon@10006000 {</div><div class='add'>+			compatible = "mediatek,mt8186-scpsys", "syscon", "simple-mfd";</div><div class='add'>+			reg = &lt;0 0x10006000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			/* System Power Manager */</div><div class='add'>+			spm: power-controller {</div><div class='add'>+				compatible = "mediatek,mt8186-power-controller";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				/* power domain of the SoC */</div><div class='add'>+				mfg0: power-domain@MT8186_POWER_DOMAIN_MFG0 {</div><div class='add'>+					reg = &lt;MT8186_POWER_DOMAIN_MFG0&gt;;</div><div class='add'>+					clocks = &lt;&amp;topckgen CLK_TOP_MFG&gt;;</div><div class='add'>+					clock-names = "mfg00";</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+					#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					mfg1: power-domain@MT8186_POWER_DOMAIN_MFG1 {</div><div class='add'>+						reg = &lt;MT8186_POWER_DOMAIN_MFG1&gt;;</div><div class='add'>+						mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+						#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						power-domain@MT8186_POWER_DOMAIN_MFG2 {</div><div class='add'>+							reg = &lt;MT8186_POWER_DOMAIN_MFG2&gt;;</div><div class='add'>+							#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						power-domain@MT8186_POWER_DOMAIN_MFG3 {</div><div class='add'>+							reg = &lt;MT8186_POWER_DOMAIN_MFG3&gt;;</div><div class='add'>+							#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				power-domain@MT8186_POWER_DOMAIN_CSIRX_TOP {</div><div class='add'>+					reg = &lt;MT8186_POWER_DOMAIN_CSIRX_TOP&gt;;</div><div class='add'>+					clocks = &lt;&amp;topckgen CLK_TOP_SENINF&gt;,</div><div class='add'>+						 &lt;&amp;topckgen CLK_TOP_SENINF1&gt;;</div><div class='add'>+					clock-names = "subsys-csirx-top0",</div><div class='add'>+						      "subsys-csirx-top1";</div><div class='add'>+					#power-domain-cells = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				power-domain@MT8186_POWER_DOMAIN_SSUSB {</div><div class='add'>+					reg = &lt;MT8186_POWER_DOMAIN_SSUSB&gt;;</div><div class='add'>+					clocks = &lt;&amp;topckgen CLK_TOP_USB_TOP&gt;,</div><div class='add'>+						 &lt;&amp;infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF&gt;;</div><div class='add'>+					clock-names = "sys_ck", "ref_ck";</div><div class='add'>+					#power-domain-cells = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				power-domain@MT8186_POWER_DOMAIN_SSUSB_P1 {</div><div class='add'>+					reg = &lt;MT8186_POWER_DOMAIN_SSUSB_P1&gt;;</div><div class='add'>+					clocks = &lt;&amp;infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS&gt;,</div><div class='add'>+						 &lt;&amp;infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF&gt;;</div><div class='add'>+					clock-names = "sys_ck", "ref_ck";</div><div class='add'>+					#power-domain-cells = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				power-domain@MT8186_POWER_DOMAIN_ADSP_AO {</div><div class='add'>+					reg = &lt;MT8186_POWER_DOMAIN_ADSP_AO&gt;;</div><div class='add'>+					clocks = &lt;&amp;topckgen CLK_TOP_AUDIODSP&gt;,</div><div class='add'>+						 &lt;&amp;topckgen CLK_TOP_ADSP_BUS&gt;;</div><div class='add'>+					clock-names = "audioadsp",</div><div class='add'>+						      "subsys-adsp-bus";</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+					#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					power-domain@MT8186_POWER_DOMAIN_ADSP_INFRA {</div><div class='add'>+						reg = &lt;MT8186_POWER_DOMAIN_ADSP_INFRA&gt;;</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+						#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						power-domain@MT8186_POWER_DOMAIN_ADSP_TOP {</div><div class='add'>+							reg = &lt;MT8186_POWER_DOMAIN_ADSP_TOP&gt;;</div><div class='add'>+							mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+							#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				power-domain@MT8186_POWER_DOMAIN_CONN_ON {</div><div class='add'>+					reg = &lt;MT8186_POWER_DOMAIN_CONN_ON&gt;;</div><div class='add'>+					mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+					#power-domain-cells = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				power-domain@MT8186_POWER_DOMAIN_DIS {</div><div class='add'>+					reg = &lt;MT8186_POWER_DOMAIN_DIS&gt;;</div><div class='add'>+					clocks = &lt;&amp;topckgen CLK_TOP_DISP&gt;,</div><div class='add'>+						 &lt;&amp;topckgen CLK_TOP_MDP&gt;,</div><div class='add'>+						 &lt;&amp;mmsys CLK_MM_SMI_INFRA&gt;,</div><div class='add'>+						 &lt;&amp;mmsys CLK_MM_SMI_COMMON&gt;,</div><div class='add'>+						 &lt;&amp;mmsys CLK_MM_SMI_GALS&gt;,</div><div class='add'>+						 &lt;&amp;mmsys CLK_MM_SMI_IOMMU&gt;;</div><div class='add'>+					clock-names = "disp", "mdp",</div><div class='add'>+						      "subsys-smi-infra",</div><div class='add'>+						      "subsys-smi-common",</div><div class='add'>+						      "subsys-smi-gals",</div><div class='add'>+						      "subsys-smi-iommu";</div><div class='add'>+					mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+					#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					power-domain@MT8186_POWER_DOMAIN_VDEC {</div><div class='add'>+						reg = &lt;MT8186_POWER_DOMAIN_VDEC&gt;;</div><div class='add'>+						clocks = &lt;&amp;topckgen CLK_TOP_VDEC&gt;,</div><div class='add'>+							 &lt;&amp;vdecsys CLK_VDEC_LARB1_CKEN&gt;;</div><div class='add'>+						clock-names = "vdec0", "larb";</div><div class='add'>+						mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					power-domain@MT8186_POWER_DOMAIN_CAM {</div><div class='add'>+						reg = &lt;MT8186_POWER_DOMAIN_CAM&gt;;</div><div class='add'>+						clocks = &lt;&amp;topckgen CLK_TOP_SENINF&gt;,</div><div class='add'>+							 &lt;&amp;topckgen CLK_TOP_SENINF1&gt;,</div><div class='add'>+							 &lt;&amp;topckgen CLK_TOP_SENINF2&gt;,</div><div class='add'>+							 &lt;&amp;topckgen CLK_TOP_SENINF3&gt;,</div><div class='add'>+							 &lt;&amp;camsys CLK_CAM2MM_GALS&gt;,</div><div class='add'>+							 &lt;&amp;topckgen CLK_TOP_CAMTM&gt;,</div><div class='add'>+							 &lt;&amp;topckgen CLK_TOP_CAM&gt;;</div><div class='add'>+						clock-names = "cam0", "cam1", "cam2",</div><div class='add'>+							      "cam3", "gals",</div><div class='add'>+							      "subsys-cam-tm",</div><div class='add'>+							      "subsys-cam-top";</div><div class='add'>+						mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+						#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						power-domain@MT8186_POWER_DOMAIN_CAM_RAWB {</div><div class='add'>+							reg = &lt;MT8186_POWER_DOMAIN_CAM_RAWB&gt;;</div><div class='add'>+							#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						power-domain@MT8186_POWER_DOMAIN_CAM_RAWA {</div><div class='add'>+							reg = &lt;MT8186_POWER_DOMAIN_CAM_RAWA&gt;;</div><div class='add'>+							#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					power-domain@MT8186_POWER_DOMAIN_IMG {</div><div class='add'>+						reg = &lt;MT8186_POWER_DOMAIN_IMG&gt;;</div><div class='add'>+						clocks = &lt;&amp;imgsys1 CLK_IMG1_GALS_IMG1&gt;,</div><div class='add'>+							 &lt;&amp;topckgen CLK_TOP_IMG1&gt;;</div><div class='add'>+						clock-names = "gals", "subsys-img-top";</div><div class='add'>+						mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+						#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						power-domain@MT8186_POWER_DOMAIN_IMG2 {</div><div class='add'>+							reg = &lt;MT8186_POWER_DOMAIN_IMG2&gt;;</div><div class='add'>+							#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					power-domain@MT8186_POWER_DOMAIN_IPE {</div><div class='add'>+						reg = &lt;MT8186_POWER_DOMAIN_IPE&gt;;</div><div class='add'>+						clocks = &lt;&amp;topckgen CLK_TOP_IPE&gt;,</div><div class='add'>+							 &lt;&amp;ipesys CLK_IPE_LARB19&gt;,</div><div class='add'>+							 &lt;&amp;ipesys CLK_IPE_LARB20&gt;,</div><div class='add'>+							 &lt;&amp;ipesys CLK_IPE_SMI_SUBCOM&gt;,</div><div class='add'>+							 &lt;&amp;ipesys CLK_IPE_GALS_IPE&gt;;</div><div class='add'>+						clock-names = "subsys-ipe-top",</div><div class='add'>+							      "subsys-ipe-larb0",</div><div class='add'>+							      "subsys-ipe-larb1",</div><div class='add'>+							      "subsys-ipe-smi",</div><div class='add'>+							      "subsys-ipe-gals";</div><div class='add'>+						mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					power-domain@MT8186_POWER_DOMAIN_VENC {</div><div class='add'>+						reg = &lt;MT8186_POWER_DOMAIN_VENC&gt;;</div><div class='add'>+						clocks = &lt;&amp;topckgen CLK_TOP_VENC&gt;,</div><div class='add'>+							 &lt;&amp;vencsys CLK_VENC_CKE1_VENC&gt;;</div><div class='add'>+						clock-names = "venc0", "subsys-larb";</div><div class='add'>+						mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					power-domain@MT8186_POWER_DOMAIN_WPE {</div><div class='add'>+						reg = &lt;MT8186_POWER_DOMAIN_WPE&gt;;</div><div class='add'>+						clocks = &lt;&amp;topckgen CLK_TOP_WPE&gt;,</div><div class='add'>+							 &lt;&amp;wpesys CLK_WPE_SMI_LARB8_CK_EN&gt;,</div><div class='add'>+							 &lt;&amp;wpesys CLK_WPE_SMI_LARB8_PCLK_EN&gt;;</div><div class='add'>+						clock-names = "wpe0",</div><div class='add'>+							      "subsys-larb-ck",</div><div class='add'>+							      "subsys-larb-pclk";</div><div class='add'>+						mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		watchdog: watchdog@10007000 {</div><div class='add'>+			compatible = "mediatek,mt8186-wdt";</div><div class='add'>+			mediatek,disable-extrst;</div><div class='add'>+			reg = &lt;0 0x10007000 0 0x1000&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		apmixedsys: syscon@1000c000 {</div><div class='add'>+			compatible = "mediatek,mt8186-apmixedsys", "syscon";</div><div class='add'>+			reg = &lt;0 0x1000c000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pwrap: pwrap@1000d000 {</div><div class='add'>+			compatible = "mediatek,mt8186-pwrap", "syscon";</div><div class='add'>+			reg = &lt;0 0x1000d000 0 0x1000&gt;;</div><div class='add'>+			reg-names = "pwrap";</div><div class='add'>+			interrupts = &lt;GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg_ao CLK_INFRA_AO_PMIC_AP&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_PMIC_TMR&gt;;</div><div class='add'>+			clock-names = "spi", "wrap";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spmi: spmi@10015000 {</div><div class='add'>+			compatible = "mediatek,mt8186-spmi", "mediatek,mt8195-spmi";</div><div class='add'>+			reg = &lt;0 0x10015000 0 0x000e00&gt;, &lt;0 0x1001B000 0 0x000100&gt;;</div><div class='add'>+			reg-names = "pmif", "spmimst";</div><div class='add'>+			clocks = &lt;&amp;infracfg_ao CLK_INFRA_AO_PMIC_AP&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_PMIC_TMR&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SPMI_MST&gt;;</div><div class='add'>+			clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux";</div><div class='add'>+			assigned-clocks = &lt;&amp;topckgen CLK_TOP_SPMI_MST&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_ULPOSC1_D10&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+				     &lt;GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		systimer: timer@10017000 {</div><div class='add'>+			compatible = "mediatek,mt8186-timer",</div><div class='add'>+				     "mediatek,mt6765-timer";</div><div class='add'>+			reg = &lt;0 0x10017000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk13m&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gce: mailbox@1022c000 {</div><div class='add'>+			compatible = "mediatek,mt8186-gce";</div><div class='add'>+			reg = &lt;0 0X1022c000 0 0x4000&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg_ao CLK_INFRA_AO_GCE&gt;;</div><div class='add'>+			clock-names = "gce";</div><div class='add'>+			interrupts = &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			#mbox-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		scp: scp@10500000 {</div><div class='add'>+			compatible = "mediatek,mt8186-scp";</div><div class='add'>+			reg = &lt;0 0x10500000 0 0x40000&gt;,</div><div class='add'>+			      &lt;0 0x105c0000 0 0x19080&gt;;</div><div class='add'>+			reg-names = "sram", "cfg";</div><div class='add'>+			interrupts = &lt;GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		adsp: adsp@10680000 {</div><div class='add'>+			compatible = "mediatek,mt8186-dsp";</div><div class='add'>+			reg = &lt;0 0x10680000 0 0x2000&gt;, &lt;0 0x10800000 0 0x100000&gt;,</div><div class='add'>+			      &lt;0 0x1068b000 0 0x100&gt;, &lt;0 0x1068f000 0 0x1000&gt;;</div><div class='add'>+			reg-names = "cfg", "sram", "sec", "bus";</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_AUDIODSP&gt;, &lt;&amp;topckgen CLK_TOP_ADSP_BUS&gt;;</div><div class='add'>+			clock-names = "audiodsp", "adsp_bus";</div><div class='add'>+			assigned-clocks = &lt;&amp;topckgen CLK_TOP_AUDIODSP&gt;,</div><div class='add'>+					  &lt;&amp;topckgen CLK_TOP_ADSP_BUS&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;clk26m&gt;, &lt;&amp;topckgen CLK_TOP_MAINPLL_D2_D2&gt;;</div><div class='add'>+			mbox-names = "rx", "tx";</div><div class='add'>+			mboxes = &lt;&amp;adsp_mailbox0&gt;, &lt;&amp;adsp_mailbox1&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8186_POWER_DOMAIN_ADSP_TOP&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		adsp_mailbox0: mailbox@10686100 {</div><div class='add'>+			compatible = "mediatek,mt8186-adsp-mbox";</div><div class='add'>+			#mbox-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0 0x10686100 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		adsp_mailbox1: mailbox@10687100 {</div><div class='add'>+			compatible = "mediatek,mt8186-adsp-mbox";</div><div class='add'>+			#mbox-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0 0x10687100 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nor_flash: spi@11000000 {</div><div class='add'>+			compatible = "mediatek,mt8186-nor";</div><div class='add'>+			reg = &lt;0 0x11000000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_SPINOR&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_SPINOR&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_FLASHIF_133M&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_FLASHIF_66M&gt;;</div><div class='add'>+			clock-names = "spi", "sf", "axi", "axi_s";</div><div class='add'>+			assigned-clocks = &lt;&amp;topckgen CLK_TOP_SPINOR&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_UNIVPLL_D3_D8&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		auxadc: adc@11001000 {</div><div class='add'>+			compatible = "mediatek,mt8186-auxadc", "mediatek,mt8173-auxadc";</div><div class='add'>+			reg = &lt;0 0x11001000 0 0x1000&gt;;</div><div class='add'>+			#io-channel-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg_ao CLK_INFRA_AO_AUXADC&gt;;</div><div class='add'>+			clock-names = "main";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart0: serial@11002000 {</div><div class='add'>+			compatible = "mediatek,mt8186-uart",</div><div class='add'>+				     "mediatek,mt6577-uart";</div><div class='add'>+			reg = &lt;0 0x11002000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk26m&gt;, &lt;&amp;infracfg_ao CLK_INFRA_AO_UART0&gt;;</div><div class='add'>+			clock-names = "baud", "bus";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart1: serial@11003000 {</div><div class='add'>+			compatible = "mediatek,mt8186-uart",</div><div class='add'>+				     "mediatek,mt6577-uart";</div><div class='add'>+			reg = &lt;0 0x11003000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk26m&gt;, &lt;&amp;infracfg_ao CLK_INFRA_AO_UART1&gt;;</div><div class='add'>+			clock-names = "baud", "bus";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c0: i2c@11007000 {</div><div class='add'>+			compatible = "mediatek,mt8186-i2c";</div><div class='add'>+			reg = &lt;0 0x11007000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x10200100 0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_AP_DMA&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			clock-div = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c1: i2c@11008000 {</div><div class='add'>+			compatible = "mediatek,mt8186-i2c";</div><div class='add'>+			reg = &lt;0 0x11008000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x10200200 0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_AP_DMA&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			clock-div = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c2: i2c@11009000 {</div><div class='add'>+			compatible = "mediatek,mt8186-i2c";</div><div class='add'>+			reg = &lt;0 0x11009000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x10200300 0 0x180&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_AP_DMA&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			clock-div = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c3: i2c@1100f000 {</div><div class='add'>+			compatible = "mediatek,mt8186-i2c";</div><div class='add'>+			reg = &lt;0 0x1100f000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x10200480 0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_AP_DMA&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			clock-div = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c4: i2c@11011000 {</div><div class='add'>+			compatible = "mediatek,mt8186-i2c";</div><div class='add'>+			reg = &lt;0 0x11011000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x10200580 0 0x180&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_AP_DMA&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			clock-div = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c5: i2c@11016000 {</div><div class='add'>+			compatible = "mediatek,mt8186-i2c";</div><div class='add'>+			reg = &lt;0 0x11016000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x10200700 0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_AP_DMA&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			clock-div = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c6: i2c@1100d000 {</div><div class='add'>+			compatible = "mediatek,mt8186-i2c";</div><div class='add'>+			reg = &lt;0 0x1100d000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x10200800 0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_AP_DMA&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			clock-div = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c7: i2c@11004000 {</div><div class='add'>+			compatible = "mediatek,mt8186-i2c";</div><div class='add'>+			reg = &lt;0 0x11004000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x10200900 0 0x180&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_AP_DMA&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			clock-div = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c8: i2c@11005000 {</div><div class='add'>+			compatible = "mediatek,mt8186-i2c";</div><div class='add'>+			reg = &lt;0 0x11005000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x10200A80 0 0x180&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_AP_DMA&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			clock-div = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi0: spi@1100a000 {</div><div class='add'>+			compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0 0x1100a000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_MAINPLL_D5&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SPI&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_SPI0&gt;;</div><div class='add'>+			clock-names = "parent-clk", "sel-clk", "spi-clk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		lvts: thermal-sensor@1100b000 {</div><div class='add'>+			compatible = "mediatek,mt8186-lvts";</div><div class='add'>+			reg = &lt;0 0x1100b000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg_ao CLK_INFRA_AO_THERM&gt;;</div><div class='add'>+			resets = &lt;&amp;infracfg_ao MT8186_INFRA_THERMAL_CTRL_RST&gt;;</div><div class='add'>+			nvmem-cells = &lt;&amp;lvts_efuse_data1 &amp;lvts_efuse_data2&gt;;</div><div class='add'>+			nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";</div><div class='add'>+			#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		svs: svs@1100bc00 {</div><div class='add'>+			compatible = "mediatek,mt8186-svs";</div><div class='add'>+			reg = &lt;0 0x1100bc00 0 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg_ao CLK_INFRA_AO_THERM&gt;;</div><div class='add'>+			clock-names = "main";</div><div class='add'>+			nvmem-cells = &lt;&amp;svs_calibration&gt;, &lt;&amp;lvts_efuse_data1&gt;;</div><div class='add'>+			nvmem-cell-names = "svs-calibration-data", "t-calibration-data";</div><div class='add'>+			resets = &lt;&amp;infracfg_ao MT8186_INFRA_PTP_CTRL_RST&gt;;</div><div class='add'>+			reset-names = "svs_rst";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pwm0: pwm@1100e000 {</div><div class='add'>+			compatible = "mediatek,mt8186-disp-pwm", "mediatek,mt8183-disp-pwm";</div><div class='add'>+			reg = &lt;0 0x1100e000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			#pwm-cells = &lt;2&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_DISP_PWM&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_DISP_PWM&gt;;</div><div class='add'>+			clock-names = "main", "mm";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi1: spi@11010000 {</div><div class='add'>+			compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0 0x11010000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_MAINPLL_D5&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SPI&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_SPI1&gt;;</div><div class='add'>+			clock-names = "parent-clk", "sel-clk", "spi-clk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi2: spi@11012000 {</div><div class='add'>+			compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0 0x11012000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_MAINPLL_D5&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SPI&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_SPI2&gt;;</div><div class='add'>+			clock-names = "parent-clk", "sel-clk", "spi-clk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi3: spi@11013000 {</div><div class='add'>+			compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0 0x11013000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_MAINPLL_D5&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SPI&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_SPI3&gt;;</div><div class='add'>+			clock-names = "parent-clk", "sel-clk", "spi-clk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi4: spi@11014000 {</div><div class='add'>+			compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0 0x11014000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_MAINPLL_D5&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SPI&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_SPI4&gt;;</div><div class='add'>+			clock-names = "parent-clk", "sel-clk", "spi-clk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi5: spi@11015000 {</div><div class='add'>+			compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0 0x11015000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_MAINPLL_D5&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SPI&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_SPI5&gt;;</div><div class='add'>+			clock-names = "parent-clk", "sel-clk", "spi-clk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		imp_iic_wrap: clock-controller@11017000 {</div><div class='add'>+			compatible = "mediatek,mt8186-imp_iic_wrap";</div><div class='add'>+			reg = &lt;0 0x11017000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart2: serial@11018000 {</div><div class='add'>+			compatible = "mediatek,mt8186-uart",</div><div class='add'>+				     "mediatek,mt6577-uart";</div><div class='add'>+			reg = &lt;0 0x11018000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk26m&gt;, &lt;&amp;infracfg_ao CLK_INFRA_AO_UART2&gt;;</div><div class='add'>+			clock-names = "baud", "bus";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c9: i2c@11019000 {</div><div class='add'>+			compatible = "mediatek,mt8186-i2c";</div><div class='add'>+			reg = &lt;0 0x11019000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x10200c00 0 0x180&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_AP_DMA&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			clock-div = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		afe: audio-controller@11210000 {</div><div class='add'>+			compatible = "mediatek,mt8186-sound";</div><div class='add'>+			reg = &lt;0 0x11210000 0 0x2000&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg_ao CLK_INFRA_AO_AUDIO&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_AUDIO_26M_BCLK&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_AUDIO&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_AUD_INTBUS&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_MAINPLL_D2_D4&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_AUD_1&gt;,</div><div class='add'>+				 &lt;&amp;apmixedsys CLK_APMIXED_APLL1&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_AUD_2&gt;,</div><div class='add'>+				 &lt;&amp;apmixedsys CLK_APMIXED_APLL2&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_AUD_ENGEN1&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_APLL1_D8&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_AUD_ENGEN2&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_APLL2_D8&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_APLL_I2S0_MCK_SEL&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_APLL_I2S1_MCK_SEL&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_APLL_I2S2_MCK_SEL&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_APLL_I2S4_MCK_SEL&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_APLL_TDMOUT_MCK_SEL&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_APLL12_CK_DIV0&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_APLL12_CK_DIV1&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_APLL12_CK_DIV2&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_APLL12_CK_DIV4&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_APLL12_CK_DIV_TDMOUT_M&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_AUDIO_H&gt;,</div><div class='add'>+				 &lt;&amp;clk26m&gt;;</div><div class='add'>+			clock-names = "aud_infra_clk",</div><div class='add'>+				      "mtkaif_26m_clk",</div><div class='add'>+				      "top_mux_audio",</div><div class='add'>+				      "top_mux_audio_int",</div><div class='add'>+				      "top_mainpll_d2_d4",</div><div class='add'>+				      "top_mux_aud_1",</div><div class='add'>+				      "top_apll1_ck",</div><div class='add'>+				      "top_mux_aud_2",</div><div class='add'>+				      "top_apll2_ck",</div><div class='add'>+				      "top_mux_aud_eng1",</div><div class='add'>+				      "top_apll1_d8",</div><div class='add'>+				      "top_mux_aud_eng2",</div><div class='add'>+				      "top_apll2_d8",</div><div class='add'>+				      "top_i2s0_m_sel",</div><div class='add'>+				      "top_i2s1_m_sel",</div><div class='add'>+				      "top_i2s2_m_sel",</div><div class='add'>+				      "top_i2s4_m_sel",</div><div class='add'>+				      "top_tdm_m_sel",</div><div class='add'>+				      "top_apll12_div0",</div><div class='add'>+				      "top_apll12_div1",</div><div class='add'>+				      "top_apll12_div2",</div><div class='add'>+				      "top_apll12_div4",</div><div class='add'>+				      "top_apll12_div_tdm",</div><div class='add'>+				      "top_mux_audio_h",</div><div class='add'>+				      "top_clk26m_clk";</div><div class='add'>+			interrupts = &lt;GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			mediatek,apmixedsys = &lt;&amp;apmixedsys&gt;;</div><div class='add'>+			mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+			mediatek,topckgen = &lt;&amp;topckgen&gt;;</div><div class='add'>+			resets = &lt;&amp;watchdog MT8186_TOPRGU_AUDIO_SW_RST&gt;;</div><div class='add'>+			reset-names = "audiosys";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ssusb0: usb@11201000 {</div><div class='add'>+			compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3";</div><div class='add'>+			reg = &lt;0 0x11201000 0 0x2dff&gt;, &lt;0 0x11203e00 0 0x0100&gt;;</div><div class='add'>+			reg-names = "mac", "ippc";</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_USB_TOP&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_ICUSB&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI&gt;;</div><div class='add'>+			clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";</div><div class='add'>+			interrupts = &lt;GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			phys = &lt;&amp;u2port0 PHY_TYPE_USB2&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8186_POWER_DOMAIN_SSUSB&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			wakeup-source;</div><div class='add'>+			mediatek,syscon-wakeup = &lt;&amp;pericfg 0x420 2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			usb_host0: usb@11200000 {</div><div class='add'>+				compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci";</div><div class='add'>+				reg = &lt;0 0x11200000 0 0x1000&gt;;</div><div class='add'>+				reg-names = "mac";</div><div class='add'>+				clocks = &lt;&amp;topckgen CLK_TOP_USB_TOP&gt;,</div><div class='add'>+					 &lt;&amp;infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF&gt;,</div><div class='add'>+					 &lt;&amp;infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK&gt;,</div><div class='add'>+					 &lt;&amp;infracfg_ao CLK_INFRA_AO_ICUSB&gt;,</div><div class='add'>+					 &lt;&amp;infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI&gt;;</div><div class='add'>+				clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";</div><div class='add'>+				interrupts = &lt;GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmc0: mmc@11230000 {</div><div class='add'>+			compatible = "mediatek,mt8186-mmc",</div><div class='add'>+				     "mediatek,mt8183-mmc";</div><div class='add'>+			reg = &lt;0 0x11230000 0 0x10000&gt;,</div><div class='add'>+			      &lt;0 0x11cd0000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_MSDC50_0&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_MSDC0&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_MSDC0_SRC&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_MSDCFDE&gt;;</div><div class='add'>+			clock-names = "source", "hclk", "source_cg", "crypto";</div><div class='add'>+			interrupts = &lt;GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			assigned-clocks = &lt;&amp;topckgen CLK_TOP_MSDC50_0&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;apmixedsys CLK_APMIXED_MSDCPLL&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmc1: mmc@11240000 {</div><div class='add'>+			compatible = "mediatek,mt8186-mmc",</div><div class='add'>+				     "mediatek,mt8183-mmc";</div><div class='add'>+			reg = &lt;0 0x11240000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11c90000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_MSDC30_1&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_MSDC1&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_MSDC1_SRC&gt;;</div><div class='add'>+			clock-names = "source", "hclk", "source_cg";</div><div class='add'>+			interrupts = &lt;GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			assigned-clocks = &lt;&amp;topckgen CLK_TOP_MSDC30_1&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_MSDCPLL_D2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ssusb1: usb@11281000 {</div><div class='add'>+			compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3";</div><div class='add'>+			reg = &lt;0 0x11281000 0 0x2dff&gt;, &lt;0 0x11283e00 0 0x0100&gt;;</div><div class='add'>+			reg-names = "mac", "ippc";</div><div class='add'>+			clocks = &lt;&amp;infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK&gt;,</div><div class='add'>+				 &lt;&amp;clk26m&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI&gt;;</div><div class='add'>+			clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";</div><div class='add'>+			interrupts = &lt;GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			phys = &lt;&amp;u2port1 PHY_TYPE_USB2&gt;, &lt;&amp;u3port1 PHY_TYPE_USB3&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8186_POWER_DOMAIN_SSUSB_P1&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			wakeup-source;</div><div class='add'>+			mediatek,syscon-wakeup = &lt;&amp;pericfg 0x424 2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			usb_host1: usb@11280000 {</div><div class='add'>+				compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci";</div><div class='add'>+				reg = &lt;0 0x11280000 0 0x1000&gt;;</div><div class='add'>+				reg-names = "mac";</div><div class='add'>+				clocks = &lt;&amp;infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS&gt;,</div><div class='add'>+					 &lt;&amp;infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF&gt;,</div><div class='add'>+					 &lt;&amp;infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK&gt;,</div><div class='add'>+					 &lt;&amp;clk26m&gt;,</div><div class='add'>+					 &lt;&amp;infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI&gt;;</div><div class='add'>+				clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck","xhci_ck";</div><div class='add'>+				interrupts = &lt;GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		u3phy0: t-phy@11c80000 {</div><div class='add'>+			compatible = "mediatek,mt8186-tphy",</div><div class='add'>+				     "mediatek,generic-tphy-v2";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges = &lt;0x0 0x0 0x11c80000 0x1000&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			u2port1: usb-phy@0 {</div><div class='add'>+				reg = &lt;0x0 0x700&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk26m&gt;;</div><div class='add'>+				clock-names = "ref";</div><div class='add'>+				#phy-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			u3port1: usb-phy@700 {</div><div class='add'>+				reg = &lt;0x700 0x900&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk26m&gt;;</div><div class='add'>+				clock-names = "ref";</div><div class='add'>+				#phy-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		u3phy1: t-phy@11ca0000 {</div><div class='add'>+			compatible = "mediatek,mt8186-tphy",</div><div class='add'>+				     "mediatek,generic-tphy-v2";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges = &lt;0x0 0x0 0x11ca0000 0x1000&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			u2port0: usb-phy@0 {</div><div class='add'>+				reg = &lt;0x0 0x700&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk26m&gt;;</div><div class='add'>+				clock-names = "ref";</div><div class='add'>+				#phy-cells = &lt;1&gt;;</div><div class='add'>+				mediatek,discth = &lt;0x8&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		efuse: efuse@11cb0000 {</div><div class='add'>+			compatible = "mediatek,mt8186-efuse", "mediatek,efuse";</div><div class='add'>+			reg = &lt;0 0x11cb0000 0 0x1000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			lvts_efuse_data1: lvts1-calib@1cc {</div><div class='add'>+				reg = &lt;0x1cc 0x14&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lvts_efuse_data2: lvts2-calib@2f8 {</div><div class='add'>+				reg = &lt;0x2f8 0x14&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			svs_calibration: calib@550 {</div><div class='add'>+				reg = &lt;0x550 0x50&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gpu_speedbin: gpu-speedbin@59c {</div><div class='add'>+				reg = &lt;0x59c 0x4&gt;;</div><div class='add'>+				bits = &lt;0 3&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			socinfo-data1@7a0 {</div><div class='add'>+				reg = &lt;0x7a0 0x4&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mipi_tx0: dsi-phy@11cc0000 {</div><div class='add'>+			compatible = "mediatek,mt8183-mipi-tx";</div><div class='add'>+			reg = &lt;0 0x11cc0000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk26m&gt;;</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+			clock-output-names = "mipi_tx0_pll";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mfgsys: clock-controller@13000000 {</div><div class='add'>+			compatible = "mediatek,mt8186-mfgsys";</div><div class='add'>+			reg = &lt;0 0x13000000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu: gpu@13040000 {</div><div class='add'>+			compatible = "mediatek,mt8186-mali",</div><div class='add'>+				     "arm,mali-bifrost";</div><div class='add'>+			reg = &lt;0 0x13040000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;mfgsys CLK_MFG_BG3D&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+				     &lt;GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+				     &lt;GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			interrupt-names = "job", "mmu", "gpu";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8186_POWER_DOMAIN_MFG2&gt;,</div><div class='add'>+					&lt;&amp;spm MT8186_POWER_DOMAIN_MFG3&gt;;</div><div class='add'>+			power-domain-names = "core0", "core1";</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			nvmem-cells = &lt;&amp;gpu_speedbin&gt;;</div><div class='add'>+			nvmem-cell-names = "speed-bin";</div><div class='add'>+			operating-points-v2 = &lt;&amp;gpu_opp_table&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;4687&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmsys: syscon@14000000 {</div><div class='add'>+			compatible = "mediatek,mt8186-mmsys", "syscon";</div><div class='add'>+			reg = &lt;0 0x14000000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+			mboxes = &lt;&amp;gce 0 CMDQ_THR_PRIO_HIGHEST&gt;,</div><div class='add'>+				 &lt;&amp;gce 1 CMDQ_THR_PRIO_HIGHEST&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1400XXXX 0 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mutex: mutex@14001000 {</div><div class='add'>+			compatible = "mediatek,mt8186-disp-mutex";</div><div class='add'>+			reg = &lt;0 0x14001000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_MUTEX0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1401XXXX 0x1000 0x1000&gt;;</div><div class='add'>+			mediatek,gce-events = &lt;CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0&gt;,</div><div class='add'>+					      &lt;CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8186_POWER_DOMAIN_DIS&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smi_common: smi@14002000 {</div><div class='add'>+			compatible = "mediatek,mt8186-smi-common";</div><div class='add'>+			reg = &lt;0 0x14002000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_SMI_COMMON&gt;, &lt;&amp;mmsys CLK_MM_SMI_COMMON&gt;,</div><div class='add'>+				 &lt;&amp;mmsys CLK_MM_SMI_GALS&gt;, &lt;&amp;mmsys CLK_MM_SMI_GALS&gt;;</div><div class='add'>+			clock-names = "apb", "smi", "gals0", "gals1";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8186_POWER_DOMAIN_DIS&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb0: smi@14003000 {</div><div class='add'>+			compatible = "mediatek,mt8186-smi-larb";</div><div class='add'>+			reg = &lt;0 0x14003000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_SMI_COMMON&gt;,</div><div class='add'>+				 &lt;&amp;mmsys CLK_MM_SMI_COMMON&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			mediatek,larb-id = &lt;0&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8186_POWER_DOMAIN_DIS&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb1: smi@14004000 {</div><div class='add'>+			compatible = "mediatek,mt8186-smi-larb";</div><div class='add'>+			reg = &lt;0 0x14004000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_SMI_COMMON&gt;,</div><div class='add'>+				 &lt;&amp;mmsys CLK_MM_SMI_COMMON&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			mediatek,larb-id = &lt;1&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8186_POWER_DOMAIN_DIS&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ovl0: ovl@14005000 {</div><div class='add'>+			compatible = "mediatek,mt8186-disp-ovl", "mediatek,mt8192-disp-ovl";</div><div class='add'>+			reg = &lt;0 0x14005000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_OVL0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu_mm IOMMU_PORT_L0_OVL_RDMA0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1400XXXX 0x5000 0x1000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8186_POWER_DOMAIN_DIS&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ovl_2l0: ovl@14006000 {</div><div class='add'>+			compatible = "mediatek,mt8186-disp-ovl-2l", "mediatek,mt8192-disp-ovl-2l";</div><div class='add'>+			reg = &lt;0 0x14006000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_OVL0_2L&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu_mm IOMMU_PORT_L1_OVL_2L_RDMA0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1400XXXX 0x6000 0x1000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8186_POWER_DOMAIN_DIS&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rdma0: rdma@14007000 {</div><div class='add'>+			compatible = "mediatek,mt8186-disp-rdma", "mediatek,mt8183-disp-rdma";</div><div class='add'>+			reg = &lt;0 0x14007000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_RDMA0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu_mm IOMMU_PORT_L1_DISP_RDMA0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1400XXXX 0x7000 0x1000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8186_POWER_DOMAIN_DIS&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		color: color@14009000 {</div><div class='add'>+			compatible = "mediatek,mt8186-disp-color", "mediatek,mt8173-disp-color";</div><div class='add'>+			reg = &lt;0 0x14009000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_COLOR0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1400XXXX 0x8000 0x1000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8186_POWER_DOMAIN_DIS&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dpi: dpi@1400a000 {</div><div class='add'>+			compatible = "mediatek,mt8186-dpi";</div><div class='add'>+			reg = &lt;0 0x1400a000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_DPI&gt;,</div><div class='add'>+				 &lt;&amp;mmsys CLK_MM_DISP_DPI&gt;,</div><div class='add'>+				 &lt;&amp;apmixedsys CLK_APMIXED_TVDPLL&gt;;</div><div class='add'>+			clock-names = "pixel", "engine", "pll";</div><div class='add'>+			assigned-clocks = &lt;&amp;topckgen CLK_TOP_DPI&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_TVDPLL_D2&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 309 IRQ_TYPE_LEVEL_LOW 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8186_POWER_DOMAIN_DIS&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			port {</div><div class='add'>+				dpi_out: endpoint { };</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ccorr: ccorr@1400b000 {</div><div class='add'>+			compatible = "mediatek,mt8186-disp-ccorr", "mediatek,mt8192-disp-ccorr";</div><div class='add'>+			reg = &lt;0 0x1400b000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_CCORR0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1400XXXX 0xb000 0x1000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8186_POWER_DOMAIN_DIS&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aal: aal@1400c000 {</div><div class='add'>+			compatible = "mediatek,mt8186-disp-aal", "mediatek,mt8183-disp-aal";</div><div class='add'>+			reg = &lt;0 0x1400c000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_AAL0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1400XXXX 0xc000 0x1000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8186_POWER_DOMAIN_DIS&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gamma: gamma@1400d000 {</div><div class='add'>+			compatible = "mediatek,mt8186-disp-gamma", "mediatek,mt8183-disp-gamma";</div><div class='add'>+			reg = &lt;0 0x1400d000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_GAMMA0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1400XXXX 0xd000 0x1000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8186_POWER_DOMAIN_DIS&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		postmask: postmask@1400e000 {</div><div class='add'>+			compatible = "mediatek,mt8186-disp-postmask",</div><div class='add'>+				     "mediatek,mt8192-disp-postmask";</div><div class='add'>+			reg = &lt;0 0x1400e000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_POSTMASK0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1400XXXX 0xe000 0x1000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8186_POWER_DOMAIN_DIS&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dither: dither@1400f000 {</div><div class='add'>+			compatible = "mediatek,mt8186-disp-dither", "mediatek,mt8183-disp-dither";</div><div class='add'>+			reg = &lt;0 0x1400f000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_DITHER0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1400XXXX 0xf000 0x1000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8186_POWER_DOMAIN_DIS&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dsi0: dsi@14013000 {</div><div class='add'>+			compatible = "mediatek,mt8186-dsi";</div><div class='add'>+			reg = &lt;0 0x14013000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DSI0&gt;,</div><div class='add'>+				 &lt;&amp;mmsys CLK_MM_DSI0_DSI_CK_DOMAIN&gt;,</div><div class='add'>+				 &lt;&amp;mipi_tx0&gt;;</div><div class='add'>+			clock-names = "engine", "digital", "hs";</div><div class='add'>+			interrupts = &lt;GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8186_POWER_DOMAIN_DIS&gt;;</div><div class='add'>+			resets = &lt;&amp;mmsys MT8186_MMSYS_SW0_RST_B_DISP_DSI0&gt;;</div><div class='add'>+			phys = &lt;&amp;mipi_tx0&gt;;</div><div class='add'>+			phy-names = "dphy";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			port {</div><div class='add'>+				dsi_out: endpoint { };</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		iommu_mm: iommu@14016000 {</div><div class='add'>+			compatible = "mediatek,mt8186-iommu-mm";</div><div class='add'>+			reg = &lt;0 0x14016000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_SMI_IOMMU&gt;;</div><div class='add'>+			clock-names = "bclk";</div><div class='add'>+			interrupts = &lt;GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			mediatek,larbs = &lt;&amp;larb0 &amp;larb1 &amp;larb2 &amp;larb4</div><div class='add'>+					  &amp;larb7 &amp;larb8 &amp;larb9 &amp;larb11</div><div class='add'>+					  &amp;larb13 &amp;larb14 &amp;larb16 &amp;larb17</div><div class='add'>+					  &amp;larb19 &amp;larb20&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8186_POWER_DOMAIN_DIS&gt;;</div><div class='add'>+			#iommu-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rdma1: rdma@1401f000 {</div><div class='add'>+			compatible = "mediatek,mt8186-disp-rdma", "mediatek,mt8183-disp-rdma";</div><div class='add'>+			reg = &lt;0 0x1401f000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_RDMA1&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu_mm IOMMU_PORT_L1_DISP_RDMA1&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1401XXXX 0xf000 0x1000&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8186_POWER_DOMAIN_DIS&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wpesys: clock-controller@14020000 {</div><div class='add'>+			compatible = "mediatek,mt8186-wpesys";</div><div class='add'>+			reg = &lt;0 0x14020000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb8: smi@14023000 {</div><div class='add'>+			compatible = "mediatek,mt8186-smi-larb";</div><div class='add'>+			reg = &lt;0 0x14023000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;wpesys CLK_WPE_SMI_LARB8_CK_EN&gt;,</div><div class='add'>+				 &lt;&amp;wpesys CLK_WPE_SMI_LARB8_CK_EN&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			mediatek,larb-id = &lt;8&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8186_POWER_DOMAIN_WPE&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		imgsys1: clock-controller@15020000 {</div><div class='add'>+			compatible = "mediatek,mt8186-imgsys1";</div><div class='add'>+			reg = &lt;0 0x15020000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb9: smi@1502e000 {</div><div class='add'>+			compatible = "mediatek,mt8186-smi-larb";</div><div class='add'>+			reg = &lt;0 0x1502e000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;imgsys1 CLK_IMG1_GALS_IMG1&gt;,</div><div class='add'>+				 &lt;&amp;imgsys1 CLK_IMG1_LARB9_IMG1&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			mediatek,larb-id = &lt;9&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8186_POWER_DOMAIN_IMG&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		imgsys2: clock-controller@15820000 {</div><div class='add'>+			compatible = "mediatek,mt8186-imgsys2";</div><div class='add'>+			reg = &lt;0 0x15820000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb11: smi@1582e000 {</div><div class='add'>+			compatible = "mediatek,mt8186-smi-larb";</div><div class='add'>+			reg = &lt;0 0x1582e000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;imgsys1 CLK_IMG1_LARB9_IMG1&gt;,</div><div class='add'>+				 &lt;&amp;imgsys2 CLK_IMG2_LARB9_IMG2&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			mediatek,larb-id = &lt;11&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8186_POWER_DOMAIN_IMG2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		video_decoder: video-decoder@16000000 {</div><div class='add'>+			compatible = "mediatek,mt8186-vcodec-dec";</div><div class='add'>+			reg = &lt;0 0x16000000 0 0x1000&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			dma-ranges = &lt;0x1 0x0 0x0 0x40000000 0x0 0xfff00000&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu_mm IOMMU_PORT_L4_HW_VDEC_MC_EXT&gt;;</div><div class='add'>+			mediatek,scp = &lt;&amp;scp&gt;;</div><div class='add'>+</div><div class='add'>+			vcodec_core: video-codec@16025000 {</div><div class='add'>+				compatible = "mediatek,mtk-vcodec-core";</div><div class='add'>+				reg = &lt;0 0x16025000 0 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				iommus = &lt;&amp;iommu_mm IOMMU_PORT_L4_HW_VDEC_MC_EXT&gt;,</div><div class='add'>+					 &lt;&amp;iommu_mm IOMMU_PORT_L4_HW_VDEC_UFO_EXT&gt;,</div><div class='add'>+					 &lt;&amp;iommu_mm IOMMU_PORT_L4_HW_VDEC_PP_EXT&gt;,</div><div class='add'>+					 &lt;&amp;iommu_mm IOMMU_PORT_L4_HW_VDEC_PRED_RD_EXT&gt;,</div><div class='add'>+					 &lt;&amp;iommu_mm IOMMU_PORT_L4_HW_VDEC_PRED_WR_EXT&gt;,</div><div class='add'>+					 &lt;&amp;iommu_mm IOMMU_PORT_L4_HW_VDEC_PPWRAP_EXT&gt;,</div><div class='add'>+					 &lt;&amp;iommu_mm IOMMU_PORT_L4_HW_VDEC_TILE_EXT&gt;,</div><div class='add'>+					 &lt;&amp;iommu_mm IOMMU_PORT_L4_HW_VDEC_VLD_EXT&gt;,</div><div class='add'>+					 &lt;&amp;iommu_mm IOMMU_PORT_L4_HW_VDEC_VLD2_EXT&gt;,</div><div class='add'>+					 &lt;&amp;iommu_mm IOMMU_PORT_L4_HW_VDEC_AVC_MV_EXT&gt;,</div><div class='add'>+					 &lt;&amp;iommu_mm IOMMU_PORT_L4_HW_VDEC_UFO_ENC_EXT&gt;,</div><div class='add'>+					 &lt;&amp;iommu_mm IOMMU_PORT_L4_HW_VDEC_RG_CTRL_DMA_EXT&gt;;</div><div class='add'>+				clocks = &lt;&amp;topckgen CLK_TOP_VDEC&gt;,</div><div class='add'>+					 &lt;&amp;vdecsys CLK_VDEC_CKEN&gt;,</div><div class='add'>+					 &lt;&amp;vdecsys CLK_VDEC_LARB1_CKEN&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_UNIVPLL_D3&gt;;</div><div class='add'>+				clock-names = "vdec-sel", "vdec-soc-vdec", "vdec", "vdec-top";</div><div class='add'>+				assigned-clocks = &lt;&amp;topckgen CLK_TOP_VDEC&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_UNIVPLL_D3&gt;;</div><div class='add'>+				power-domains = &lt;&amp;spm MT8186_POWER_DOMAIN_VDEC&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb4: smi@1602e000 {</div><div class='add'>+			compatible = "mediatek,mt8186-smi-larb";</div><div class='add'>+			reg = &lt;0 0x1602e000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdecsys CLK_VDEC_LARB1_CKEN&gt;,</div><div class='add'>+				 &lt;&amp;vdecsys CLK_VDEC_LARB1_CKEN&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			mediatek,larb-id = &lt;4&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8186_POWER_DOMAIN_VDEC&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdecsys: clock-controller@1602f000 {</div><div class='add'>+			compatible = "mediatek,mt8186-vdecsys";</div><div class='add'>+			reg = &lt;0 0x1602f000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vencsys: clock-controller@17000000 {</div><div class='add'>+			compatible = "mediatek,mt8186-vencsys";</div><div class='add'>+			reg = &lt;0 0x17000000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb7: smi@17010000 {</div><div class='add'>+			compatible = "mediatek,mt8186-smi-larb";</div><div class='add'>+			reg = &lt;0 0x17010000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vencsys CLK_VENC_CKE1_VENC&gt;,</div><div class='add'>+				 &lt;&amp;vencsys CLK_VENC_CKE1_VENC&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			mediatek,larb-id = &lt;7&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8186_POWER_DOMAIN_VENC&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		venc: video-encoder@17020000 {</div><div class='add'>+			compatible = "mediatek,mt8186-vcodec-enc", "mediatek,mt8183-vcodec-enc";</div><div class='add'>+			reg = &lt;0 0x17020000 0 0x2000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu_mm IOMMU_PORT_L7_VENC_RCPU&gt;,</div><div class='add'>+				 &lt;&amp;iommu_mm IOMMU_PORT_L7_VENC_REC&gt;,</div><div class='add'>+				 &lt;&amp;iommu_mm IOMMU_PORT_L7_VENC_BSDMA&gt;,</div><div class='add'>+				 &lt;&amp;iommu_mm IOMMU_PORT_L7_VENC_SV_COMV&gt;,</div><div class='add'>+				 &lt;&amp;iommu_mm IOMMU_PORT_L7_VENC_RD_COMV&gt;,</div><div class='add'>+				 &lt;&amp;iommu_mm IOMMU_PORT_L7_VENC_CUR_LUMA&gt;,</div><div class='add'>+				 &lt;&amp;iommu_mm IOMMU_PORT_L7_VENC_CUR_CHROMA&gt;,</div><div class='add'>+				 &lt;&amp;iommu_mm IOMMU_PORT_L7_VENC_REF_LUMA&gt;,</div><div class='add'>+				 &lt;&amp;iommu_mm IOMMU_PORT_L7_VENC_REF_CHROMA&gt;;</div><div class='add'>+			clocks = &lt;&amp;vencsys CLK_VENC_CKE1_VENC&gt;;</div><div class='add'>+			clock-names = "venc_sel";</div><div class='add'>+			assigned-clocks = &lt;&amp;topckgen CLK_TOP_VENC&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_UNIVPLL_D3&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8186_POWER_DOMAIN_VENC&gt;;</div><div class='add'>+			mediatek,scp = &lt;&amp;scp&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		jpgenc: jpeg-encoder@17030000 {</div><div class='add'>+			compatible = "mediatek,mt8186-jpgenc", "mediatek,mtk-jpgenc";</div><div class='add'>+			reg = &lt;0 0x17030000 0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;vencsys CLK_VENC_CKE2_JPGENC&gt;;</div><div class='add'>+			clock-names = "jpgenc";</div><div class='add'>+			iommus = &lt;&amp;iommu_mm IOMMU_PORT_L7_JPGENC_Y_RDMA&gt;,</div><div class='add'>+				 &lt;&amp;iommu_mm IOMMU_PORT_L7_JPGENC_C_RDMA&gt;,</div><div class='add'>+				 &lt;&amp;iommu_mm IOMMU_PORT_L7_JPGENC_Q_TABLE&gt;,</div><div class='add'>+				 &lt;&amp;iommu_mm IOMMU_PORT_L7_JPGENC_BSDMA&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8186_POWER_DOMAIN_VENC&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		camsys: clock-controller@1a000000 {</div><div class='add'>+			compatible = "mediatek,mt8186-camsys";</div><div class='add'>+			reg = &lt;0 0x1a000000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb13: smi@1a001000 {</div><div class='add'>+			compatible = "mediatek,mt8186-smi-larb";</div><div class='add'>+			reg = &lt;0 0x1a001000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;camsys CLK_CAM2MM_GALS&gt;, &lt;&amp;camsys CLK_CAM_LARB13&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			mediatek,larb-id = &lt;13&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8186_POWER_DOMAIN_CAM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb14: smi@1a002000 {</div><div class='add'>+			compatible = "mediatek,mt8186-smi-larb";</div><div class='add'>+			reg = &lt;0 0x1a002000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;camsys CLK_CAM2MM_GALS&gt;, &lt;&amp;camsys CLK_CAM_LARB14&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			mediatek,larb-id = &lt;14&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8186_POWER_DOMAIN_CAM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb16: smi@1a00f000 {</div><div class='add'>+			compatible = "mediatek,mt8186-smi-larb";</div><div class='add'>+			reg = &lt;0 0x1a00f000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;camsys CLK_CAM_LARB14&gt;,</div><div class='add'>+				 &lt;&amp;camsys_rawa CLK_CAM_RAWA_LARBX_RAWA&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			mediatek,larb-id = &lt;16&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8186_POWER_DOMAIN_CAM_RAWA&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb17: smi@1a010000 {</div><div class='add'>+			compatible = "mediatek,mt8186-smi-larb";</div><div class='add'>+			reg = &lt;0 0x1a010000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;camsys CLK_CAM_LARB13&gt;,</div><div class='add'>+				 &lt;&amp;camsys_rawb CLK_CAM_RAWB_LARBX_RAWB&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			mediatek,larb-id = &lt;17&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8186_POWER_DOMAIN_CAM_RAWB&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		camsys_rawa: clock-controller@1a04f000 {</div><div class='add'>+			compatible = "mediatek,mt8186-camsys_rawa";</div><div class='add'>+			reg = &lt;0 0x1a04f000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		camsys_rawb: clock-controller@1a06f000 {</div><div class='add'>+			compatible = "mediatek,mt8186-camsys_rawb";</div><div class='add'>+			reg = &lt;0 0x1a06f000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdpsys: clock-controller@1b000000 {</div><div class='add'>+			compatible = "mediatek,mt8186-mdpsys";</div><div class='add'>+			reg = &lt;0 0x1b000000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb2: smi@1b002000 {</div><div class='add'>+			compatible = "mediatek,mt8186-smi-larb";</div><div class='add'>+			reg = &lt;0 0x1b002000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;mdpsys CLK_MDP_SMI0&gt;, &lt;&amp;mdpsys CLK_MDP_SMI0&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			mediatek,larb-id = &lt;2&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8186_POWER_DOMAIN_DIS&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ipesys: clock-controller@1c000000 {</div><div class='add'>+			compatible = "mediatek,mt8186-ipesys";</div><div class='add'>+			reg = &lt;0 0x1c000000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb20: smi@1c00f000 {</div><div class='add'>+			compatible = "mediatek,mt8186-smi-larb";</div><div class='add'>+			reg = &lt;0 0x1c00f000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;ipesys CLK_IPE_LARB20&gt;, &lt;&amp;ipesys CLK_IPE_LARB20&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			mediatek,larb-id = &lt;20&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8186_POWER_DOMAIN_IPE&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb19: smi@1c10f000 {</div><div class='add'>+			compatible = "mediatek,mt8186-smi-larb";</div><div class='add'>+			reg = &lt;0 0x1c10f000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;ipesys CLK_IPE_LARB19&gt;, &lt;&amp;ipesys CLK_IPE_LARB19&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			mediatek,larb-id = &lt;19&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8186_POWER_DOMAIN_IPE&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	thermal_zones: thermal-zones {</div><div class='add'>+		cpu-little0-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;150&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts MT8186_LITTLE_CPU0&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu_little0_alert0: trip-alert0 {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_little0_alert1: trip-alert1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_little0_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu_little0_alert0&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu-little1-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;150&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts MT8186_LITTLE_CPU1&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu_little1_alert0: trip-alert0 {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_little1_alert1: trip-alert1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_little1_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu_little1_alert0&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu-little2-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;150&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts MT8186_LITTLE_CPU2&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu_little2_alert0: trip-alert0 {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_little2_alert1: trip-alert1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_little2_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu_little2_alert0&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cam-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts MT8186_CAM&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cam_alert0: trip-alert0 {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cam_alert1: trip-alert1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cam_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nna-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts MT8186_NNA&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				nna_alert0: trip-alert0 {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				nna_alert1: trip-alert1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				nna_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		adsp-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts MT8186_ADSP&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				adsp_alert0: trip-alert0 {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				adsp_alert1: trip-alert1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				adsp_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts MT8186_GPU&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				gpu_alert0: trip-alert0 {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpu_alert1: trip-alert1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpu_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;gpu_alert0&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu-big0-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;100&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts MT8186_BIG_CPU0&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu_big0_alert0: trip-alert0 {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_big0_alert1: trip-alert1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_big0_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu_big0_alert0&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu-big1-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;100&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts MT8186_BIG_CPU1&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu_big1_alert0: trip-alert0 {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_big1_alert1: trip-alert1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_big1_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu_big1_alert0&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8188-evb.dts b/arch/arm64/boot/dts/mediatek/mt8188-evb.dts<br/>new file mode 100644<br/>index 000000000000..f4c207d65b87<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8188-evb.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8188-evb.dts</a></div><div class='hunk'>@@ -0,0 +1,389 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2023 MediaTek Inc.</div><div class='add'>+ */</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8188.dtsi"</div><div class='add'>+#include "mt6359.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "MediaTek MT8188 evaluation board";</div><div class='add'>+	compatible = "mediatek,mt8188-evb", "mediatek,mt8188";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+		i2c0 = &amp;i2c0;</div><div class='add'>+		i2c1 = &amp;i2c1;</div><div class='add'>+		i2c2 = &amp;i2c2;</div><div class='add'>+		i2c3 = &amp;i2c3;</div><div class='add'>+		i2c4 = &amp;i2c4;</div><div class='add'>+		i2c5 = &amp;i2c5;</div><div class='add'>+		i2c6 = &amp;i2c6;</div><div class='add'>+		mmc0 = &amp;mmc0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen: chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0 0x40000000 0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved_memory: reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		scp_mem_reserved: memory@50000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x50000000 0 0x2900000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;auxadc {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c0_pins&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c1_pins&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c2_pins&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c3_pins&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c4_pins&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c5 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c5_pins&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c6 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c6_pins&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc0 {</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	hs400-ds-delay = &lt;0x1481b&gt;;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+</div><div class='add'>+	cap-mmc-highspeed;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	mmc-hs400-1_8v;</div><div class='add'>+	supports-cqe;</div><div class='add'>+	cap-mmc-hw-reset;</div><div class='add'>+	no-sdio;</div><div class='add'>+	no-sd;</div><div class='add'>+	non-removable;</div><div class='add'>+</div><div class='add'>+	vmmc-supply = &lt;&amp;mt6359_vemc_1_ldo_reg&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;mt6359_vufs_ldo_reg&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl-names = "default", "state_uhs";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc0_default_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;mmc0_uhs_pins&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vcore_buck_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vgpu11_buck_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vpu_buck_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vrf12_ldo_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;nor_flash {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;nor_pins_default&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;52000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	adsp_uart_pins: adsp-uart-pins {</div><div class='add'>+		pins-tx-rx {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO35__FUNC_O_ADSP_UTXD0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO36__FUNC_I1_ADSP_URXD0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c0_pins: i2c0-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO56__FUNC_B1_SDA0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO55__FUNC_B1_SCL0&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PULL_SET_RSEL_011&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c1_pins: i2c1-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO58__FUNC_B1_SDA1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO57__FUNC_B1_SCL1&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PULL_SET_RSEL_011&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c2_pins: i2c2-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO60__FUNC_B1_SDA2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO59__FUNC_B1_SCL2&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PULL_SET_RSEL_011&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c3_pins: i2c3-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO62__FUNC_B1_SDA3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO61__FUNC_B1_SCL3&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PULL_SET_RSEL_011&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c4_pins: i2c4-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO64__FUNC_B1_SDA4&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO63__FUNC_B1_SCL4&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PULL_SET_RSEL_011&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c5_pins: i2c5-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO66__FUNC_B1_SDA5&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO65__FUNC_B1_SCL5&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PULL_SET_RSEL_011&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c6_pins: i2c6-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO68__FUNC_B1_SDA6&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO67__FUNC_B1_SCL6&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PULL_SET_RSEL_011&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc0_default_pins: mmc0-default-pins {</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO161__FUNC_B1_MSDC0_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO160__FUNC_B1_MSDC0_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO159__FUNC_B1_MSDC0_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO158__FUNC_B1_MSDC0_DAT3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO154__FUNC_B1_MSDC0_DAT4&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO153__FUNC_B1_MSDC0_DAT5&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO152__FUNC_B1_MSDC0_DAT6&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO151__FUNC_B1_MSDC0_DAT7&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO156__FUNC_B1_MSDC0_CMD&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO157__FUNC_B1_MSDC0_CLK&gt;;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-rst {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO155__FUNC_O_MSDC0_RSTB&gt;;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc0_uhs_pins: mmc0-uhs-pins {</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO161__FUNC_B1_MSDC0_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO160__FUNC_B1_MSDC0_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO159__FUNC_B1_MSDC0_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO158__FUNC_B1_MSDC0_DAT3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO154__FUNC_B1_MSDC0_DAT4&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO153__FUNC_B1_MSDC0_DAT5&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO152__FUNC_B1_MSDC0_DAT6&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO151__FUNC_B1_MSDC0_DAT7&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO156__FUNC_B1_MSDC0_CMD&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-clk-ds {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO157__FUNC_B1_MSDC0_CLK&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO162__FUNC_B0_MSDC0_DSL&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-rst {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO155__FUNC_O_MSDC0_RSTB&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	nor_pins_default: nor-pins {</div><div class='add'>+		pins-io-ck {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO127__FUNC_B0_SPINOR_IO0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO125__FUNC_O_SPINOR_CK&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO128__FUNC_B0_SPINOR_IO1&gt;;</div><div class='add'>+			bias-pull-down;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-io-cs {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO126__FUNC_O_SPINOR_CS&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO129__FUNC_B0_SPINOR_IO2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO130__FUNC_B0_SPINOR_IO3&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi0_pins: spi0-pins {</div><div class='add'>+		pins-spi {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO69__FUNC_O_SPIM0_CSB&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO70__FUNC_O_SPIM0_CLK&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO71__FUNC_B0_SPIM0_MOSI&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO72__FUNC_B0_SPIM0_MISO&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi1_pins: spi1-pins {</div><div class='add'>+		pins-spi {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO75__FUNC_O_SPIM1_CSB&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO76__FUNC_O_SPIM1_CLK&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO77__FUNC_B0_SPIM1_MOSI&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO78__FUNC_B0_SPIM1_MISO&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi2_pins: spi2-pins {</div><div class='add'>+		pins-spi {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO79__FUNC_O_SPIM2_CSB&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO80__FUNC_O_SPIM2_CLK&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO81__FUNC_B0_SPIM2_MOSI&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO82__FUNC_B0_SPIM2_MISO&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart0_pins: uart0-pins {</div><div class='add'>+		pins-rx-tx {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO31__FUNC_O_UTXD0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO32__FUNC_I1_URXD0&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pmic {</div><div class='add'>+	interrupts-extended = &lt;&amp;pio 222 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;scp_cluster {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;scp_c0 {</div><div class='add'>+	memory-region = &lt;&amp;scp_mem_reserved&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;spi0_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;spi1_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;spi2_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;u3phy0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;u3phy1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;u3phy2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart0_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xhci0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xhci1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xhci2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku0.dts b/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku0.dts<br/>new file mode 100644<br/>index 000000000000..79d6d12394b9<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku0.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku0.dts</a></div><div class='hunk'>@@ -0,0 +1,32 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Google LLC</div><div class='add'>+ */</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8188-geralt-ciri.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google Ciri sku0 board";</div><div class='add'>+	compatible = "google,ciri-sku0", "google,ciri", "mediatek,mt8188";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsi_panel {</div><div class='add'>+	compatible = "boe,nv110wum-l60", "himax,hx83102";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sound {</div><div class='add'>+	compatible = "mediatek,mt8188-rt5682s";</div><div class='add'>+	model = "mt8188_m98390_5682";</div><div class='add'>+</div><div class='add'>+	audio-routing =</div><div class='add'>+		"ETDM1_OUT", "ETDM_SPK_PIN",</div><div class='add'>+		"ETDM2_OUT", "ETDM_HP_PIN",</div><div class='add'>+		"ETDM1_IN", "ETDM_SPK_PIN",</div><div class='add'>+		"ETDM2_IN", "ETDM_HP_PIN",</div><div class='add'>+		"ADDA Capture", "MTKAIF_PIN",</div><div class='add'>+		"Headphone Jack", "HPOL",</div><div class='add'>+		"Headphone Jack", "HPOR",</div><div class='add'>+		"IN1P", "Headset Mic",</div><div class='add'>+		"Left Spk", "Front Left BE_OUT",</div><div class='add'>+		"Right Spk", "Front Right BE_OUT";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku1.dts b/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku1.dts<br/>new file mode 100644<br/>index 000000000000..ef5ea9d12b1d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku1.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku1.dts</a></div><div class='hunk'>@@ -0,0 +1,59 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Google LLC</div><div class='add'>+ */</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8188-geralt-ciri.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google Ciri sku1 board";</div><div class='add'>+	compatible = "google,ciri-sku1", "google,ciri", "mediatek,mt8188";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsi_panel {</div><div class='add'>+	compatible = "ivo,t109nw41", "himax,hx83102";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	/delete-node/ audio-codec@1a;</div><div class='add'>+</div><div class='add'>+	es8326: audio-codec@19 {</div><div class='add'>+		compatible = "everest,es8326";</div><div class='add'>+		reg = &lt;0x19&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 108 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;audio_codec_pins&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		everest,jack-pol = [0e];</div><div class='add'>+		everest,interrupt-clk = [00];</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sound {</div><div class='add'>+	compatible = "mediatek,mt8188-es8326";</div><div class='add'>+	model = "mt8188_m98390_8326";</div><div class='add'>+</div><div class='add'>+	audio-routing =</div><div class='add'>+		"ETDM1_OUT", "ETDM_SPK_PIN",</div><div class='add'>+		"ETDM2_OUT", "ETDM_HP_PIN",</div><div class='add'>+		"ETDM1_IN", "ETDM_SPK_PIN",</div><div class='add'>+		"ETDM2_IN", "ETDM_HP_PIN",</div><div class='add'>+		"ADDA Capture", "MTKAIF_PIN",</div><div class='add'>+		"Headphone Jack", "HPOL",</div><div class='add'>+		"Headphone Jack", "HPOR",</div><div class='add'>+		"MIC1", "Headset Mic",</div><div class='add'>+		"Left Spk", "Front Left BE_OUT",</div><div class='add'>+		"Right Spk", "Front Right BE_OUT";</div><div class='add'>+</div><div class='add'>+	dai-link-2 {</div><div class='add'>+		codec {</div><div class='add'>+			sound-dai = &lt;&amp;es8326&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dai-link-3 {</div><div class='add'>+		codec {</div><div class='add'>+			sound-dai = &lt;&amp;es8326&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku2.dts b/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku2.dts<br/>new file mode 100644<br/>index 000000000000..ef56786fc2be<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku2.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku2.dts</a></div><div class='hunk'>@@ -0,0 +1,59 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 Google LLC</div><div class='add'>+ */</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8188-geralt-ciri.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google Ciri sku2 board";</div><div class='add'>+	compatible = "google,ciri-sku2", "google,ciri", "mediatek,mt8188";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsi_panel {</div><div class='add'>+	compatible = "boe,nv110wum-l60", "himax,hx83102";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	/delete-node/ audio-codec@1a;</div><div class='add'>+</div><div class='add'>+	es8326: audio-codec@19 {</div><div class='add'>+		compatible = "everest,es8326";</div><div class='add'>+		reg = &lt;0x19&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 108 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;audio_codec_pins&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		everest,jack-pol = [0e];</div><div class='add'>+		everest,interrupt-clk = [00];</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sound {</div><div class='add'>+	compatible = "mediatek,mt8188-es8326";</div><div class='add'>+	model = "mt8188_m98390_8326";</div><div class='add'>+</div><div class='add'>+	audio-routing =</div><div class='add'>+		"ETDM1_OUT", "ETDM_SPK_PIN",</div><div class='add'>+		"ETDM2_OUT", "ETDM_HP_PIN",</div><div class='add'>+		"ETDM1_IN", "ETDM_SPK_PIN",</div><div class='add'>+		"ETDM2_IN", "ETDM_HP_PIN",</div><div class='add'>+		"ADDA Capture", "MTKAIF_PIN",</div><div class='add'>+		"Headphone Jack", "HPOL",</div><div class='add'>+		"Headphone Jack", "HPOR",</div><div class='add'>+		"MIC1", "Headset Mic",</div><div class='add'>+		"Left Spk", "Front Left BE_OUT",</div><div class='add'>+		"Right Spk", "Front Right BE_OUT";</div><div class='add'>+</div><div class='add'>+	dai-link-2 {</div><div class='add'>+		codec {</div><div class='add'>+			sound-dai = &lt;&amp;es8326&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dai-link-3 {</div><div class='add'>+		codec {</div><div class='add'>+			sound-dai = &lt;&amp;es8326&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku3.dts b/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku3.dts<br/>new file mode 100644<br/>index 000000000000..524f7f0064c1<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku3.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku3.dts</a></div><div class='hunk'>@@ -0,0 +1,32 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 Google LLC</div><div class='add'>+ */</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8188-geralt-ciri.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google Ciri sku3 board";</div><div class='add'>+	compatible = "google,ciri-sku3", "google,ciri", "mediatek,mt8188";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsi_panel {</div><div class='add'>+	compatible = "ivo,t109nw41", "himax,hx83102";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sound {</div><div class='add'>+	compatible = "mediatek,mt8188-rt5682s";</div><div class='add'>+	model = "mt8188_m98390_5682";</div><div class='add'>+</div><div class='add'>+	audio-routing =</div><div class='add'>+		"ETDM1_OUT", "ETDM_SPK_PIN",</div><div class='add'>+		"ETDM2_OUT", "ETDM_HP_PIN",</div><div class='add'>+		"ETDM1_IN", "ETDM_SPK_PIN",</div><div class='add'>+		"ETDM2_IN", "ETDM_HP_PIN",</div><div class='add'>+		"ADDA Capture", "MTKAIF_PIN",</div><div class='add'>+		"Headphone Jack", "HPOL",</div><div class='add'>+		"Headphone Jack", "HPOR",</div><div class='add'>+		"IN1P", "Headset Mic",</div><div class='add'>+		"Left Spk", "Front Left BE_OUT",</div><div class='add'>+		"Right Spk", "Front Right BE_OUT";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku4.dts b/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku4.dts<br/>new file mode 100644<br/>index 000000000000..ea953d7e1543<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku4.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku4.dts</a></div><div class='hunk'>@@ -0,0 +1,48 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 Google LLC</div><div class='add'>+ */</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8188-geralt-ciri.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google Ciri sku4 board (rev4)";</div><div class='add'>+	compatible = "google,ciri-sku4", "google,ciri", "mediatek,mt8188";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsi_panel {</div><div class='add'>+	compatible = "boe,nv110wum-l60", "himax,hx83102";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	/delete-node/ amplifier@38;</div><div class='add'>+	/delete-node/ amplifier@39;</div><div class='add'>+</div><div class='add'>+	tas2563: amplifier@4f {</div><div class='add'>+		compatible = "ti,tas2563", "ti,tas2781";</div><div class='add'>+		reg = &lt;0x4f&gt;, &lt;0x4c&gt;; /* left / right channel */</div><div class='add'>+		reset-gpios = &lt;&amp;pio 118 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sound {</div><div class='add'>+	compatible = "mediatek,mt8188-rt5682s";</div><div class='add'>+	model = "mt8188_tas2563_5682";</div><div class='add'>+</div><div class='add'>+	audio-routing =</div><div class='add'>+		"ETDM1_OUT", "ETDM_SPK_PIN",</div><div class='add'>+		"ETDM2_OUT", "ETDM_HP_PIN",</div><div class='add'>+		"ETDM1_IN", "ETDM_SPK_PIN",</div><div class='add'>+		"ETDM2_IN", "ETDM_HP_PIN",</div><div class='add'>+		"ADDA Capture", "MTKAIF_PIN",</div><div class='add'>+		"Headphone Jack", "HPOL",</div><div class='add'>+		"Headphone Jack", "HPOR",</div><div class='add'>+		"IN1P", "Headset Mic";</div><div class='add'>+</div><div class='add'>+	dai-link-1 {</div><div class='add'>+		codec {</div><div class='add'>+			sound-dai = &lt;&amp;tas2563&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku5.dts b/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku5.dts<br/>new file mode 100644<br/>index 000000000000..bf87201ccf27<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku5.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku5.dts</a></div><div class='hunk'>@@ -0,0 +1,72 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 Google LLC</div><div class='add'>+ */</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8188-geralt-ciri.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google Ciri sku5 board (rev4)";</div><div class='add'>+	compatible = "google,ciri-sku5", "google,ciri", "mediatek,mt8188";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsi_panel {</div><div class='add'>+	compatible = "ivo,t109nw41", "himax,hx83102";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	/delete-node/ audio-codec@1a;</div><div class='add'>+	/delete-node/ amplifier@38;</div><div class='add'>+	/delete-node/ amplifier@39;</div><div class='add'>+</div><div class='add'>+	es8326: audio-codec@19 {</div><div class='add'>+		compatible = "everest,es8326";</div><div class='add'>+		reg = &lt;0x19&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 108 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;audio_codec_pins&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		everest,jack-pol = [0e];</div><div class='add'>+		everest,interrupt-clk = [00];</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	tas2563: amplifier@4f {</div><div class='add'>+		compatible = "ti,tas2563", "ti,tas2781";</div><div class='add'>+		reg = &lt;0x4f&gt;, &lt;0x4c&gt;; /* left / right channel */</div><div class='add'>+		reset-gpios = &lt;&amp;pio 118 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sound {</div><div class='add'>+	compatible = "mediatek,mt8188-es8326";</div><div class='add'>+	model = "mt8188_tas2563_8326";</div><div class='add'>+</div><div class='add'>+	audio-routing =</div><div class='add'>+		"ETDM1_OUT", "ETDM_SPK_PIN",</div><div class='add'>+		"ETDM2_OUT", "ETDM_HP_PIN",</div><div class='add'>+		"ETDM1_IN", "ETDM_SPK_PIN",</div><div class='add'>+		"ETDM2_IN", "ETDM_HP_PIN",</div><div class='add'>+		"ADDA Capture", "MTKAIF_PIN",</div><div class='add'>+		"Headphone Jack", "HPOL",</div><div class='add'>+		"Headphone Jack", "HPOR",</div><div class='add'>+		"MIC1", "Headset Mic";</div><div class='add'>+</div><div class='add'>+	dai-link-1 {</div><div class='add'>+		codec {</div><div class='add'>+			sound-dai = &lt;&amp;tas2563&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dai-link-2 {</div><div class='add'>+		codec {</div><div class='add'>+			sound-dai = &lt;&amp;es8326&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dai-link-3 {</div><div class='add'>+		codec {</div><div class='add'>+			sound-dai = &lt;&amp;es8326&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku6.dts b/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku6.dts<br/>new file mode 100644<br/>index 000000000000..17d7359dfb6a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku6.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku6.dts</a></div><div class='hunk'>@@ -0,0 +1,72 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 Google LLC</div><div class='add'>+ */</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8188-geralt-ciri.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google Ciri sku6 board (rev4)";</div><div class='add'>+	compatible = "google,ciri-sku6", "google,ciri", "mediatek,mt8188";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsi_panel {</div><div class='add'>+	compatible = "boe,nv110wum-l60", "himax,hx83102";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	/delete-node/ audio-codec@1a;</div><div class='add'>+	/delete-node/ amplifier@38;</div><div class='add'>+	/delete-node/ amplifier@39;</div><div class='add'>+</div><div class='add'>+	es8326: audio-codec@19 {</div><div class='add'>+		compatible = "everest,es8326";</div><div class='add'>+		reg = &lt;0x19&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 108 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;audio_codec_pins&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		everest,jack-pol = [0e];</div><div class='add'>+		everest,interrupt-clk = [00];</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	tas2563: amplifier@4f {</div><div class='add'>+		compatible = "ti,tas2563", "ti,tas2781";</div><div class='add'>+		reg = &lt;0x4f&gt;, &lt;0x4c&gt;; /* left / right channel */</div><div class='add'>+		reset-gpios = &lt;&amp;pio 118 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sound {</div><div class='add'>+	compatible = "mediatek,mt8188-es8326";</div><div class='add'>+	model = "mt8188_tas2563_8326";</div><div class='add'>+</div><div class='add'>+	audio-routing =</div><div class='add'>+		"ETDM1_OUT", "ETDM_SPK_PIN",</div><div class='add'>+		"ETDM2_OUT", "ETDM_HP_PIN",</div><div class='add'>+		"ETDM1_IN", "ETDM_SPK_PIN",</div><div class='add'>+		"ETDM2_IN", "ETDM_HP_PIN",</div><div class='add'>+		"ADDA Capture", "MTKAIF_PIN",</div><div class='add'>+		"Headphone Jack", "HPOL",</div><div class='add'>+		"Headphone Jack", "HPOR",</div><div class='add'>+		"MIC1", "Headset Mic";</div><div class='add'>+</div><div class='add'>+	dai-link-1 {</div><div class='add'>+		codec {</div><div class='add'>+			sound-dai = &lt;&amp;tas2563&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dai-link-2 {</div><div class='add'>+		codec {</div><div class='add'>+			sound-dai = &lt;&amp;es8326&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dai-link-3 {</div><div class='add'>+		codec {</div><div class='add'>+			sound-dai = &lt;&amp;es8326&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku7.dts b/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku7.dts<br/>new file mode 100644<br/>index 000000000000..825015b452d5<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku7.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku7.dts</a></div><div class='hunk'>@@ -0,0 +1,48 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 Google LLC</div><div class='add'>+ */</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8188-geralt-ciri.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google Ciri sku7 board (rev4)";</div><div class='add'>+	compatible = "google,ciri-sku7", "google,ciri", "mediatek,mt8188";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsi_panel {</div><div class='add'>+	compatible = "ivo,t109nw41", "himax,hx83102";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	/delete-node/ amplifier@38;</div><div class='add'>+	/delete-node/ amplifier@39;</div><div class='add'>+</div><div class='add'>+	tas2563: amplifier@4f {</div><div class='add'>+		compatible = "ti,tas2563", "ti,tas2781";</div><div class='add'>+		reg = &lt;0x4f&gt;, &lt;0x4c&gt;; /* left / right channel */</div><div class='add'>+		reset-gpios = &lt;&amp;pio 118 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sound {</div><div class='add'>+	compatible = "mediatek,mt8188-rt5682s";</div><div class='add'>+	model = "mt8188_tas2563_5682";</div><div class='add'>+</div><div class='add'>+	audio-routing =</div><div class='add'>+		"ETDM1_OUT", "ETDM_SPK_PIN",</div><div class='add'>+		"ETDM2_OUT", "ETDM_HP_PIN",</div><div class='add'>+		"ETDM1_IN", "ETDM_SPK_PIN",</div><div class='add'>+		"ETDM2_IN", "ETDM_HP_PIN",</div><div class='add'>+		"ADDA Capture", "MTKAIF_PIN",</div><div class='add'>+		"Headphone Jack", "HPOL",</div><div class='add'>+		"Headphone Jack", "HPOR",</div><div class='add'>+		"IN1P", "Headset Mic";</div><div class='add'>+</div><div class='add'>+	dai-link-1 {</div><div class='add'>+		codec {</div><div class='add'>+			sound-dai = &lt;&amp;tas2563&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri.dtsi b/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri.dtsi<br/>new file mode 100644<br/>index 000000000000..6815c435a57e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri.dtsi</a></div><div class='hunk'>@@ -0,0 +1,316 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Google LLC</div><div class='add'>+ */</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8188-geralt.dtsi"</div><div class='add'>+</div><div class='add'>+&amp;aud_etdm_hp_on {</div><div class='add'>+	pins-mclk {</div><div class='add'>+		pinmux = &lt;PINMUX_GPIO114__FUNC_O_I2SO2_MCK&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;aud_etdm_hp_off {</div><div class='add'>+	pins-mclk {</div><div class='add'>+		pinmux = &lt;PINMUX_GPIO114__FUNC_B_GPIO114&gt;;</div><div class='add'>+		bias-pull-down;</div><div class='add'>+		input-enable;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	rt5682s: audio-codec@1a {</div><div class='add'>+		compatible = "realtek,rt5682s";</div><div class='add'>+		reg = &lt;0x1a&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 108 IRQ_TYPE_EDGE_BOTH&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;audio_codec_pins&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		AVDD-supply = &lt;&amp;mt6359_vio18_ldo_reg&gt;;</div><div class='add'>+		DBVDD-supply = &lt;&amp;mt6359_vio18_ldo_reg&gt;;</div><div class='add'>+		LDO1-IN-supply = &lt;&amp;mt6359_vio18_ldo_reg&gt;;</div><div class='add'>+		MICVDD-supply = &lt;&amp;pp3300_s3&gt;;</div><div class='add'>+		realtek,jd-src = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	max98390_38: amplifier@38 {</div><div class='add'>+		compatible = "maxim,max98390";</div><div class='add'>+		reg = &lt;0x38&gt;;</div><div class='add'>+		sound-name-prefix = "Front Right";</div><div class='add'>+		reset-gpios = &lt;&amp;pio 118 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;speaker_en&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	max98390_39: amplifier@39 {</div><div class='add'>+		compatible = "maxim,max98390";</div><div class='add'>+		reg = &lt;0x39&gt;;</div><div class='add'>+		sound-name-prefix = "Front Left";</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c_tunnel {</div><div class='add'>+	/*</div><div class='add'>+	 * The virtual battery I2C addr is 0xf on Ciri, so we describe it</div><div class='add'>+	 * manually instead of including 'arm/cros-ec-sbs.dtsi'.</div><div class='add'>+	 **/</div><div class='add'>+	battery: sbs-battery@f {</div><div class='add'>+		compatible = "sbs,sbs-battery";</div><div class='add'>+		reg = &lt;0xf&gt;;</div><div class='add'>+		sbs,i2c-retry-count = &lt;2&gt;;</div><div class='add'>+		sbs,poll-retry-count = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_tx_config0 {</div><div class='add'>+	drive-strength-microamp = &lt;5200&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vm18_ldo_reg {</div><div class='add'>+	regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;1900000&gt;;</div><div class='add'>+	regulator-microvolt-offset = &lt;100000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sound {</div><div class='add'>+	dai-link-0 {</div><div class='add'>+		link-name = "ETDM1_IN_BE";</div><div class='add'>+		dai-format = "i2s";</div><div class='add'>+		mediatek,clk-provider = "cpu";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dai-link-1 {</div><div class='add'>+		link-name = "ETDM1_OUT_BE";</div><div class='add'>+		dai-format = "i2s";</div><div class='add'>+		mediatek,clk-provider = "cpu";</div><div class='add'>+</div><div class='add'>+		codec {</div><div class='add'>+			sound-dai = &lt;&amp;max98390_38&gt;,</div><div class='add'>+				    &lt;&amp;max98390_39&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dai-link-2 {</div><div class='add'>+		link-name = "ETDM2_IN_BE";</div><div class='add'>+		mediatek,clk-provider = "cpu";</div><div class='add'>+</div><div class='add'>+		codec {</div><div class='add'>+			sound-dai = &lt;&amp;rt5682s 0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dai-link-3 {</div><div class='add'>+		link-name = "ETDM2_OUT_BE";</div><div class='add'>+		mediatek,clk-provider = "cpu";</div><div class='add'>+</div><div class='add'>+		codec {</div><div class='add'>+			sound-dai = &lt;&amp;rt5682s 0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dai-link-4 {</div><div class='add'>+		link-name = "DPTX_BE";</div><div class='add'>+</div><div class='add'>+		codec {</div><div class='add'>+			sound-dai = &lt;&amp;dp_tx&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"GSC_AP_INT_ODL",</div><div class='add'>+		"AP_DISP_BKLTEN",</div><div class='add'>+		"",</div><div class='add'>+		"EN_PPVAR_MIPI_DISP",</div><div class='add'>+		"EN_PPVAR_MIPI_DISP_150MA",</div><div class='add'>+		"TCHSCR_RST_1V8_L",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"I2S_SPKR_DATAOUT",</div><div class='add'>+		"EN_PP3300_WLAN_X",</div><div class='add'>+		"WIFI_KILL_1V8_L",</div><div class='add'>+		"BT_KILL_1V8_L",</div><div class='add'>+		"AP_FLASH_WP_L", /* ... is crossystem ABI. Rev1 schematics call it AP_WP_ODL. */</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"WCAM_PWDN_L",</div><div class='add'>+		"WCAM_RST_L",</div><div class='add'>+		"UCAM_PWDM_L",</div><div class='add'>+		"UCAM_RST_L",</div><div class='add'>+		"WCAM_24M_CLK",</div><div class='add'>+		"UCAM_24M_CLK",</div><div class='add'>+		"MT6319_INT",</div><div class='add'>+		"DISP_RST_1V8_L",</div><div class='add'>+		"DSIO_DSI_TE",</div><div class='add'>+		"",</div><div class='add'>+		"TP",</div><div class='add'>+		"MIPI_BL_PWM_1V8",</div><div class='add'>+		"",</div><div class='add'>+		"UART_AP_TX_GSC_RX",</div><div class='add'>+		"UART_GSC_TX_AP_RX",</div><div class='add'>+		"UART_SSPM_TX_DBGCON_RX",</div><div class='add'>+		"UART_DBGCON_TX_SSPM_RX",</div><div class='add'>+		"UART_ADSP_TX_DBGCON_RX",</div><div class='add'>+		"UART_DBGCON_TX_ADSP_RX",</div><div class='add'>+		"JTAG_AP_TMS",</div><div class='add'>+		"JTAG_AP_TCK",</div><div class='add'>+		"JTAG_AP_TDI",</div><div class='add'>+		"JTAG_AP_TDO",</div><div class='add'>+		"JTAG_AP_TRST",</div><div class='add'>+		"AP_KPCOL0",</div><div class='add'>+		"TP",</div><div class='add'>+		"",</div><div class='add'>+		"TP",</div><div class='add'>+		"EC_AP_HPD_OD",</div><div class='add'>+		"PCIE_WAKE_1V8_ODL",</div><div class='add'>+		"PCIE_RST_1V8_L",</div><div class='add'>+		"PCIE_CLKREQ_1V8_ODL",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"AP_I2C_AUD_SCL_1V8",</div><div class='add'>+		"AP_I2C_AUD_SDA_1V8",</div><div class='add'>+		"AP_I2C_TPM_SCL_1V8",</div><div class='add'>+		"AP_I2C_TPM_SDA_1V8",</div><div class='add'>+		"AP_I2C_TCHSCR_SCL_1V8",</div><div class='add'>+		"AP_I2C_TCHSCR_SDA_1V8",</div><div class='add'>+		"AP_I2C_PMIC_SAR_SCL_1V8",</div><div class='add'>+		"AP_I2C_PMIC_SAR_SDA_1V8",</div><div class='add'>+		"AP_I2C_EC_HID_KB_SCL_1V8",</div><div class='add'>+		"AP_I2C_EC_HID_KB_SDA_1V8",</div><div class='add'>+		"AP_I2C_UCAM_SCL_1V8",</div><div class='add'>+		"AP_I2C_UCAM_SDA_1V8",</div><div class='add'>+		"AP_I2C_WCAM_SCL_1V8",</div><div class='add'>+		"AP_I2C_WCAM_SDA_1V8",</div><div class='add'>+		"SPI_AP_CS_EC_L",</div><div class='add'>+		"SPI_AP_CLK_EC",</div><div class='add'>+		"SPI_AP_DO_EC_DI",</div><div class='add'>+		"SPI_AP_DI_EC_DO",</div><div class='add'>+		"TP",</div><div class='add'>+		"TP",</div><div class='add'>+		"SPI_AP_CS_TCHSCR_L",</div><div class='add'>+		"SPI_AP_CLK_TCHSCR",</div><div class='add'>+		"SPI_AP_DO_TCHSCR_DI",</div><div class='add'>+		"SPI_AP_DI_TCHSCR_DO",</div><div class='add'>+		"TP",</div><div class='add'>+		"TP",</div><div class='add'>+		"TP",</div><div class='add'>+		"TP",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"TP",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"PWRAP_SPI_CS_L",</div><div class='add'>+		"PWRAP_SPI_CK",</div><div class='add'>+		"PWRAP_SPI_MOSI",</div><div class='add'>+		"PWRAP_SPI_MISO",</div><div class='add'>+		"SRCLKENA0",</div><div class='add'>+		"SRCLKENA1",</div><div class='add'>+		"SCP_VREQ_VAO",</div><div class='add'>+		"AP_RTC_CLK32K",</div><div class='add'>+		"AP_PMIC_WDTRST_L",</div><div class='add'>+		"AUD_CLK_MOSI",</div><div class='add'>+		"AUD_SYNC_MOSI",</div><div class='add'>+		"AUD_DAT_MOSI0",</div><div class='add'>+		"AUD_DAT_MOSI1",</div><div class='add'>+		"AUD_DAT_MISO0",</div><div class='add'>+		"AUD_DAT_MISO1",</div><div class='add'>+		"",</div><div class='add'>+		"HP_INT_ODL",</div><div class='add'>+		"SPKR_INT_ODL",</div><div class='add'>+		"I2S_HP_DATAIN",</div><div class='add'>+		"EN_SPKR",</div><div class='add'>+		"I2S_SPKR_MCLK",</div><div class='add'>+		"I2S_SPKR_BCLK",</div><div class='add'>+		"I2S_HP_MCLK",</div><div class='add'>+		"I2S_HP_BCLK",</div><div class='add'>+		"I2S_HP_LRCK",</div><div class='add'>+		"I2S_HP_DATAOUT",</div><div class='add'>+		"RST_SPKR_L",</div><div class='add'>+		"I2S_SPKR_LRCK",</div><div class='add'>+		"I2S_SPKR_DATAIN",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"SPI_AP_CLK_ROM",</div><div class='add'>+		"SPI_AP_CS_ROM_L",</div><div class='add'>+		"SPI_AP_DO_ROM_DI",</div><div class='add'>+		"SPI_AP_DI_ROM_DO",</div><div class='add'>+		"TP",</div><div class='add'>+		"TP",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"EN_PP2800A_UCAM_X",</div><div class='add'>+		"EN_PP1200_UCAM_X",</div><div class='add'>+		"EN_PP2800A_WCAM_X",</div><div class='add'>+		"EN_PP1100_WCAM_X",</div><div class='add'>+		"TCHSCR_INT_1V8_L",</div><div class='add'>+		"",</div><div class='add'>+		"MT7921_PMU_EN_1V8",</div><div class='add'>+		"",</div><div class='add'>+		"AP_EC_WARM_RST_REQ",</div><div class='add'>+		"EC_AP_HID_INT_ODL",</div><div class='add'>+		"EC_AP_INT_ODL",</div><div class='add'>+		"AP_XHCI_INIT_DONE",</div><div class='add'>+		"EMMC_DAT7",</div><div class='add'>+		"EMMC_DAT6",</div><div class='add'>+		"EMMC_DAT5",</div><div class='add'>+		"EMMC_DAT4",</div><div class='add'>+		"EMMC_RST_L",</div><div class='add'>+		"EMMC_CMD",</div><div class='add'>+		"EMMC_CLK",</div><div class='add'>+		"EMMC_DAT3",</div><div class='add'>+		"EMMC_DAT2",</div><div class='add'>+		"EMMC_DAT1",</div><div class='add'>+		"EMMC_DAT0",</div><div class='add'>+		"EMMC_DSL",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"USB3_HUB_RST_L",</div><div class='add'>+		"EC_AP_RSVD0_ODL",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"SPMI_SCL",</div><div class='add'>+		"SPMI_SDA";</div><div class='add'>+</div><div class='add'>+	audio_codec_pins: audio-codec-pins {</div><div class='add'>+		pins-hp-int-odl {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO108__FUNC_B_GPIO108&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	speaker_en: speaker-en-pins {</div><div class='add'>+		pins-en-spkr {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO111__FUNC_B_GPIO111&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi b/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi<br/>new file mode 100644<br/>index 000000000000..7fedbacdac44<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi</a></div><div class='hunk'>@@ -0,0 +1,1340 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2022 MediaTek Inc.</div><div class='add'>+ */</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include "mt8188.dtsi"</div><div class='add'>+#include "mt6359.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		dsi0 = &amp;disp_dsi0;</div><div class='add'>+		i2c0 = &amp;i2c0;</div><div class='add'>+		i2c1 = &amp;i2c1;</div><div class='add'>+		i2c2 = &amp;i2c2;</div><div class='add'>+		i2c3 = &amp;i2c3;</div><div class='add'>+		i2c4 = &amp;i2c4;</div><div class='add'>+		i2c5 = &amp;i2c5;</div><div class='add'>+		i2c6 = &amp;i2c6;</div><div class='add'>+		mmc0 = &amp;mmc0;</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	backlight_lcd0: backlight-lcd0 {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		brightness-levels = &lt;0 1023&gt;;</div><div class='add'>+		default-brightness-level = &lt;576&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;pio 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		num-interpolated-steps = &lt;1023&gt;;</div><div class='add'>+		power-supply = &lt;&amp;ppvar_sys&gt;;</div><div class='add'>+		pwms = &lt;&amp;disp_pwm0 0 500000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dmic-codec {</div><div class='add'>+		compatible = "dmic-codec";</div><div class='add'>+		num-channels = &lt;2&gt;;</div><div class='add'>+		wakeup-delay-ms = &lt;100&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		/* The size will be filled in by the bootloader */</div><div class='add'>+		reg = &lt;0 0x40000000 0 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* system wide LDO 1.8V power rail */</div><div class='add'>+	pp1800_ldo_z1: regulator-pp1800-ldo-z1 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "pp1800_ldo_z1";</div><div class='add'>+		/* controlled by PP3300_Z1 */</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;pp3300_z1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* separately switched 3.3V power rail */</div><div class='add'>+	pp3300_s3: regulator-pp3300-s3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "pp3300_s3";</div><div class='add'>+		/* controlled by PMIC */</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;pp3300_z1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* system wide 3.3V power rail */</div><div class='add'>+	pp3300_z1: regulator-pp3300-z1 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "pp3300_z1";</div><div class='add'>+		/* controlled by PP3300_LDO_Z5 &amp; EN_PWR_Z1 */</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;ppvar_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pp3300_wlan: regulator-pp3300-wlan {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "pp3300_wlan";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;pio 12 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;wlan_en&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		vin-supply = &lt;&amp;pp3300_z1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* system wide 4.2V power rail */</div><div class='add'>+	pp4200_s5: regulator-pp4200-s5 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "pp4200_s5";</div><div class='add'>+		/* controlled by EC */</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-min-microvolt = &lt;4200000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;4200000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;ppvar_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* system wide 5.0V power rail */</div><div class='add'>+	pp5000_z1: regulator-pp5000-z1 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "pp5000_z1";</div><div class='add'>+		/* controlled by EC */</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;ppvar_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pp5000_usb_vbus: regulator-pp5000-usb-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "pp5000_usb_vbus";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;pio 150 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;pp5000_z1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* system wide semi-regulated power rail from battery or USB */</div><div class='add'>+	ppvar_sys: regulator-ppvar-sys {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "ppvar_sys";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ppvar_mipi_disp_avdd: regulator-ppvar-mipi-disp-avdd {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "ppvar_mipi_disp_avdd";</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;pio 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;mipi_disp_avdd_en&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;pp5000_z1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ppvar_mipi_disp_avee: regulator-ppvar-mipi-disp-avee {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "ppvar_mipi_disp_avee";</div><div class='add'>+		regulator-enable-ramp-delay = &lt;10000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;pio 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;mipi_disp_avee_en&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;pp5000_z1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved_memory: reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		scp_mem_reserved: memory@50000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x50000000 0 0x800000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		apu_mem: memory@55000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x55000000 0 0x1400000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		adsp_mem: memory@60000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x60000000 0 0xf00000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		afe_dma_mem: memory@60f00000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x60f00000 0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		adsp_dma_mem: memory@61000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x61000000 0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;adsp {</div><div class='add'>+	memory-region = &lt;&amp;adsp_dma_mem&gt;, &lt;&amp;adsp_mem&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;adsp_uart_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;afe {</div><div class='add'>+	memory-region = &lt;&amp;afe_dma_mem&gt;;</div><div class='add'>+	mediatek,etdm-out1-cowork-source = &lt;0&gt;; /* in1 */</div><div class='add'>+	mediatek,etdm-in2-cowork-source = &lt;3&gt;; /* out2 */</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;auxadc {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cam_vcore {</div><div class='add'>+	domain-supply = &lt;&amp;mt6359_vproc1_buck_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Geralt is the reference design and doesn't have target TDP.</div><div class='add'>+ * Ciri is (currently) the only device following Geralt, and its</div><div class='add'>+ * TDP target is 90 degrees.</div><div class='add'>+ **/</div><div class='add'>+&amp;cpu_little0_alert0 {</div><div class='add'>+	temperature = &lt;90000&gt;;</div><div class='add'>+	hysteresis = &lt;2000&gt;;</div><div class='add'>+	type = "passive";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu_little1_alert0 {</div><div class='add'>+	temperature = &lt;90000&gt;;</div><div class='add'>+	hysteresis = &lt;2000&gt;;</div><div class='add'>+	type = "passive";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu_little2_alert0 {</div><div class='add'>+	temperature = &lt;90000&gt;;</div><div class='add'>+	hysteresis = &lt;2000&gt;;</div><div class='add'>+	type = "passive";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu_little3_alert0 {</div><div class='add'>+	temperature = &lt;90000&gt;;</div><div class='add'>+	hysteresis = &lt;2000&gt;;</div><div class='add'>+	type = "passive";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu_big0_alert0 {</div><div class='add'>+	temperature = &lt;90000&gt;;</div><div class='add'>+	hysteresis = &lt;2000&gt;;</div><div class='add'>+	type = "passive";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu_big1_alert0 {</div><div class='add'>+	temperature = &lt;90000&gt;;</div><div class='add'>+	hysteresis = &lt;2000&gt;;</div><div class='add'>+	type = "passive";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;disp_dsi0 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	dsi_panel: panel@0 {</div><div class='add'>+		/* Compatible string for different panels can be found in each device dts */</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;pio 25 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;mipi_dsi_pins&gt;;</div><div class='add'>+</div><div class='add'>+		backlight = &lt;&amp;backlight_lcd0&gt;;</div><div class='add'>+		avdd-supply = &lt;&amp;ppvar_mipi_disp_avdd&gt;;</div><div class='add'>+		avee-supply = &lt;&amp;ppvar_mipi_disp_avee&gt;;</div><div class='add'>+		pp1800-supply = &lt;&amp;mt6359_vm18_ldo_reg&gt;;</div><div class='add'>+		rotation = &lt;270&gt;;</div><div class='add'>+</div><div class='add'>+		status = "okay";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			dsi_panel_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;dsi0_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		port@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			dsi0_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;dither0_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			dsi0_out: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;dsi_panel_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;disp_pwm0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;disp_pwm0_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;disp_pwm1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;disp_pwm1_pins&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dither0_in {</div><div class='add'>+	remote-endpoint = &lt;&amp;postmask0_out&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dither0_out {</div><div class='add'>+	remote-endpoint = &lt;&amp;dsi0_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethdr0 {</div><div class='add'>+	ports {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		port@0 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			ethdr0_in: endpoint@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				remote-endpoint = &lt;&amp;vdosys1_ep_ext&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@1 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			ethdr0_out: endpoint@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				remote-endpoint = &lt;&amp;merge5_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gamma0_out {</div><div class='add'>+	remote-endpoint = &lt;&amp;postmask0_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dp_intf1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		port@0 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			dp_intf1_in: endpoint@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				remote-endpoint = &lt;&amp;merge5_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@1 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			dp_intf1_out: endpoint@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				remote-endpoint = &lt;&amp;dptx_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dp_tx {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;dp_tx_hpd&gt;;</div><div class='add'>+	#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		port@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			dptx_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;dp_intf1_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			dptx_out: endpoint {</div><div class='add'>+				data-lanes = &lt;0 1 2 3&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	mali-supply = &lt;&amp;mt6359_vproc2_buck_reg&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c0_pins&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c1_pins&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	tpm@50 {</div><div class='add'>+		compatible = "google,cr50";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 0 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;gsc_int&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c2_pins&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c3_pins&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c4_pins&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c5 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c5_pins&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c6 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c6_pins&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;merge5 {</div><div class='add'>+	ports {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		port@0 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			merge5_in: endpoint@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				remote-endpoint = &lt;&amp;ethdr0_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@1 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			merge5_out: endpoint@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				remote-endpoint = &lt;&amp;dp_intf1_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mfg0 {</div><div class='add'>+	domain-supply = &lt;&amp;mt6359_vproc2_buck_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mfg1 {</div><div class='add'>+	domain-supply = &lt;&amp;mt6359_vsram_others_ldo_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_tx_config0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc0 {</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	cap-mmc-highspeed;</div><div class='add'>+	cap-mmc-hw-reset;</div><div class='add'>+	hs400-ds-delay = &lt;0x1481b&gt;;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	mmc-hs400-1_8v;</div><div class='add'>+	mmc-hs400-enhanced-strobe;</div><div class='add'>+	no-sd;</div><div class='add'>+	no-sdio;</div><div class='add'>+	non-removable;</div><div class='add'>+	pinctrl-names = "default", "state_uhs";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc0_pins_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;mmc0_pins_uhs&gt;;</div><div class='add'>+	supports-cqe;</div><div class='add'>+	vmmc-supply = &lt;&amp;mt6359_vemc_1_ldo_reg&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;mt6359_vufs_ldo_reg&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359codec {</div><div class='add'>+	mediatek,dmic-mode = &lt;1&gt;; /* one-wire */</div><div class='add'>+	mediatek,mic-type-0 = &lt;2&gt;; /* DMIC */</div><div class='add'>+	mediatek,mic-type-2 = &lt;2&gt;; /* DMIC */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vcore_buck_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vgpu11_buck_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vgpu11_sshub_buck_reg {</div><div class='add'>+	regulator-min-microvolt = &lt;550000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;550000&gt;;</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vio28_ldo_reg {</div><div class='add'>+	/delete-property/ regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vm18_ldo_reg {</div><div class='add'>+	/delete-property/ regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vmodem_buck_reg {</div><div class='add'>+	regulator-min-microvolt = &lt;775000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;775000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vpa_buck_reg {</div><div class='add'>+	regulator-max-microvolt = &lt;3100000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vproc2_buck_reg {</div><div class='add'>+	/*</div><div class='add'>+	 * Called "ppvar_dvdd_gpu" in the schematic. Renamed to</div><div class='add'>+	 * "ppvar_dvdd_vgpu" here to match mtk-regulator-coupler requirements.</div><div class='add'>+	 */</div><div class='add'>+	regulator-name = "ppvar_dvdd_vgpu";</div><div class='add'>+	regulator-min-microvolt = &lt;550000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;800000&gt;;</div><div class='add'>+	regulator-coupled-with = &lt;&amp;mt6359_vsram_others_ldo_reg&gt;;</div><div class='add'>+	regulator-coupled-max-spread = &lt;6250&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vpu_buck_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vrf12_ldo_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vsram_md_ldo_reg {</div><div class='add'>+	regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;800000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vsram_others_ldo_reg {</div><div class='add'>+	regulator-name = "pp0850_dvdd_sram_gpu";</div><div class='add'>+	regulator-min-microvolt = &lt;750000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;800000&gt;;</div><div class='add'>+	regulator-coupled-with = &lt;&amp;mt6359_vproc2_buck_reg&gt;;</div><div class='add'>+	regulator-coupled-max-spread = &lt;6250&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vufs_ldo_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;nor_flash {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;nor_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;52000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ovl0_in {</div><div class='add'>+	remote-endpoint = &lt;&amp;vdosys0_ep_main&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pcie_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pciephy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"gsc_int",</div><div class='add'>+		"AP_DISP_BKLTEN",</div><div class='add'>+		"",</div><div class='add'>+		"EN_PPVAR_MIPI_DISP",</div><div class='add'>+		"EN_PPVAR_MIPI_DISP_150MA",</div><div class='add'>+		"TCHSCR_RST_1V8_L",</div><div class='add'>+		"TCHSRC_REPORT_DISABLE",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"I2S_SPKR_DATAOUT",</div><div class='add'>+		"EN_PP3300_WLAN_X",</div><div class='add'>+		"WIFI_KILL_1V8_L",</div><div class='add'>+		"BT_KILL_1V8_L",</div><div class='add'>+		"AP_FLASH_WP_L", /* ... is crossystem ABI. Rev1 schematics call it AP_WP_ODL. */</div><div class='add'>+		"",</div><div class='add'>+		"EDP_HPD_1V8",</div><div class='add'>+		"WCAM_PWDN_L",</div><div class='add'>+		"WCAM_RST_L",</div><div class='add'>+		"UCAM_PWDM_L",</div><div class='add'>+		"UCAM_RST_L",</div><div class='add'>+		"WCAM_24M_CLK",</div><div class='add'>+		"UCAM_24M_CLK",</div><div class='add'>+		"MT6319_INT",</div><div class='add'>+		"DISP_RST_1V8_L",</div><div class='add'>+		"DSIO_DSI_TE",</div><div class='add'>+		"EN_PP3300_EDP_DISP_X",</div><div class='add'>+		"TP",</div><div class='add'>+		"MIPI_BL_PWM_1V8",</div><div class='add'>+		"EDP_BL_PWM_1V8",</div><div class='add'>+		"UART_AP_TX_GSC_RX",</div><div class='add'>+		"UART_GSC_TX_AP_RX",</div><div class='add'>+		"UART_SSPM_TX_DBGCON_RX",</div><div class='add'>+		"UART_DBGCON_TX_SSPM_RX",</div><div class='add'>+		"UART_ADSP_TX_DBGCON_RX",</div><div class='add'>+		"UART_DBGCON_TX_ADSP_RX",</div><div class='add'>+		"JTAG_AP_TMS",</div><div class='add'>+		"JTAG_AP_TCK",</div><div class='add'>+		"JTAG_AP_TDI",</div><div class='add'>+		"JTAG_AP_TDO",</div><div class='add'>+		"JTAG_AP_TRST",</div><div class='add'>+		"AP_KPCOL0",</div><div class='add'>+		"TP",</div><div class='add'>+		"BEEP_ON_OD",</div><div class='add'>+		"TP",</div><div class='add'>+		"EC_AP_HPD_OD",</div><div class='add'>+		"PCIE_WAKE_1V8_ODL",</div><div class='add'>+		"PCIE_RST_1V8_L",</div><div class='add'>+		"PCIE_CLKREQ_1V8_ODL",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"AP_I2C_AUD_SCL_1V8",</div><div class='add'>+		"AP_I2C_AUD_SDA_1V8",</div><div class='add'>+		"AP_I2C_TPM_SCL_1V8",</div><div class='add'>+		"AP_I2C_TPM_SDA_1V8",</div><div class='add'>+		"AP_I2C_TCHSCR_SCL_1V8",</div><div class='add'>+		"AP_I2C_TCHSCR_SDA_1V8",</div><div class='add'>+		"AP_I2C_PMIC_SAR_SCL_1V8",</div><div class='add'>+		"AP_I2C_PMIC_SAR_SDA_1V8",</div><div class='add'>+		"AP_I2C_EC_HID_KB_SCL_1V8",</div><div class='add'>+		"AP_I2C_EC_HID_KB_SDA_1V8",</div><div class='add'>+		"AP_I2C_UCAM_SCL_1V8",</div><div class='add'>+		"AP_I2C_UCAM_SDA_1V8",</div><div class='add'>+		"AP_I2C_WCAM_SCL_1V8",</div><div class='add'>+		"AP_I2C_WCAM_SDA_1V8",</div><div class='add'>+		"SPI_AP_CS_EC_L",</div><div class='add'>+		"SPI_AP_CLK_EC",</div><div class='add'>+		"SPI_AP_DO_EC_DI",</div><div class='add'>+		"SPI_AP_DI_EC_DO",</div><div class='add'>+		"TP",</div><div class='add'>+		"TP",</div><div class='add'>+		"SPI_AP_CS_TCHSCR_L",</div><div class='add'>+		"SPI_AP_CLK_TCHSCR",</div><div class='add'>+		"SPI_AP_DO_TCHSCR_DI",</div><div class='add'>+		"SPI_AP_DI_TCHSCR_DO",</div><div class='add'>+		"TP",</div><div class='add'>+		"TP",</div><div class='add'>+		"TP",</div><div class='add'>+		"TP",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"TP",</div><div class='add'>+		"",</div><div class='add'>+		"SAR_INT_ODL",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"PWRAP_SPI_CS_L",</div><div class='add'>+		"PWRAP_SPI_CK",</div><div class='add'>+		"PWRAP_SPI_MOSI",</div><div class='add'>+		"PWRAP_SPI_MISO",</div><div class='add'>+		"SRCLKENA0",</div><div class='add'>+		"SRCLKENA1",</div><div class='add'>+		"SCP_VREQ_VAO",</div><div class='add'>+		"AP_RTC_CLK32K",</div><div class='add'>+		"AP_PMIC_WDTRST_L",</div><div class='add'>+		"AUD_CLK_MOSI",</div><div class='add'>+		"AUD_SYNC_MOSI",</div><div class='add'>+		"AUD_DAT_MOSI0",</div><div class='add'>+		"AUD_DAT_MOSI1",</div><div class='add'>+		"AUD_DAT_MISO0",</div><div class='add'>+		"AUD_DAT_MISO1",</div><div class='add'>+		"SD_CD_ODL",</div><div class='add'>+		"HP_INT_ODL",</div><div class='add'>+		"SPKR_INT_ODL",</div><div class='add'>+		"I2S_HP_DATAIN",</div><div class='add'>+		"EN_SPKR",</div><div class='add'>+		"I2S_SPKR_MCLK",</div><div class='add'>+		"I2S_SPKR_BCLK",</div><div class='add'>+		"I2S_HP_MCLK",</div><div class='add'>+		"I2S_HP_BCLK",</div><div class='add'>+		"I2S_HP_LRCK",</div><div class='add'>+		"I2S_HP_DATAOUT",</div><div class='add'>+		"RST_SPKR_L",</div><div class='add'>+		"I2S_SPKR_LRCK",</div><div class='add'>+		"I2S_SPKR_DATAIN",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"SPI_AP_CLK_ROM",</div><div class='add'>+		"SPI_AP_CS_ROM_L",</div><div class='add'>+		"SPI_AP_DO_ROM_DI",</div><div class='add'>+		"SPI_AP_DI_ROM_DO",</div><div class='add'>+		"TP",</div><div class='add'>+		"TP",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"EN_PP2800A_UCAM_X",</div><div class='add'>+		"EN_PP1200_UCAM_X",</div><div class='add'>+		"EN_PP2800A_WCAM_X",</div><div class='add'>+		"EN_PP1100_WCAM_X",</div><div class='add'>+		"TCHSCR_INT_1V8_L",</div><div class='add'>+		"EN_PP3300_MIPI_TCHSCR_X",</div><div class='add'>+		"MT7921_PMU_EN_1V8",</div><div class='add'>+		"EN_PP3300_EDP_TCHSCR_X",</div><div class='add'>+		"AP_EC_WARM_RST_REQ",</div><div class='add'>+		"EC_AP_HID_INT_ODL",</div><div class='add'>+		"EC_AP_INT_ODL",</div><div class='add'>+		"AP_XHCI_INIT_DONE",</div><div class='add'>+		"EMMC_DAT7",</div><div class='add'>+		"EMMC_DAT6",</div><div class='add'>+		"EMMC_DAT5",</div><div class='add'>+		"EMMC_DAT4",</div><div class='add'>+		"EMMC_RST_L",</div><div class='add'>+		"EMMC_CMD",</div><div class='add'>+		"EMMC_CLK",</div><div class='add'>+		"EMMC_DAT3",</div><div class='add'>+		"EMMC_DAT2",</div><div class='add'>+		"EMMC_DAT1",</div><div class='add'>+		"EMMC_DAT0",</div><div class='add'>+		"EMMC_DSL",</div><div class='add'>+		"SD_CMD",</div><div class='add'>+		"SD_CLK",</div><div class='add'>+		"SD_DAT0",</div><div class='add'>+		"SD_DAT1",</div><div class='add'>+		"SD_DAT2",</div><div class='add'>+		"SD_DAT3",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"USB3_HUB_RST_L",</div><div class='add'>+		"EC_AP_RSVD0_ODL",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"SPMI_SCL",</div><div class='add'>+		"SPMI_SDA";</div><div class='add'>+</div><div class='add'>+	adsp_uart_pins: adsp-uart-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO35__FUNC_O_ADSP_UTXD0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO36__FUNC_I1_ADSP_URXD0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_etdm_hp_on: aud-etdm-hp-on-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO110__FUNC_I0_I2SIN_D0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO115__FUNC_B0_I2SO2_BCK&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO116__FUNC_B0_I2SO2_WS&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO117__FUNC_O_I2SO2_D0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_etdm_hp_off: aud-etdm-hp-off-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO110__FUNC_B_GPIO110&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO115__FUNC_B_GPIO115&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO116__FUNC_B_GPIO116&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO117__FUNC_B_GPIO117&gt;;</div><div class='add'>+			bias-pull-down;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_etdm_spk_on: aud-etdm-spk-on-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO11__FUNC_O_I2SO1_D0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO113__FUNC_B0_TDMIN_BCK&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO119__FUNC_B0_TDMIN_LRCK&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO120__FUNC_I0_TDMIN_DI&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_etdm_spk_off: aud-etdm-spk-off-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO11__FUNC_B_GPIO11&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO113__FUNC_B_GPIO113&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO119__FUNC_B_GPIO119&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO120__FUNC_B_GPIO120&gt;;</div><div class='add'>+			bias-pull-down;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_mtkaif_on: aud-mtkaif-on-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO101__FUNC_O_AUD_CLK_MOSI&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO102__FUNC_O_AUD_SYNC_MOSI&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO103__FUNC_O_AUD_DAT_MOSI0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO104__FUNC_O_AUD_DAT_MOSI1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO105__FUNC_I0_AUD_DAT_MISO0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO106__FUNC_I0_AUD_DAT_MISO1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_mtkaif_off: aud-mtkaif-off-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO101__FUNC_B_GPIO101&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO102__FUNC_B_GPIO102&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO103__FUNC_B_GPIO103&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO104__FUNC_B_GPIO104&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO105__FUNC_B_GPIO105&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO106__FUNC_B_GPIO106&gt;;</div><div class='add'>+			bias-pull-down;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cros_ec_int: cros-ec-int-pins {</div><div class='add'>+		pins-ec-ap-int-odl {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO149__FUNC_B_GPIO149&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	disp_pwm0_pins: disp-pwm0-pins {</div><div class='add'>+		pins-disp-pwm0 {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO29__FUNC_O_DISP_PWM0&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	disp_pwm1_pins: disp-pwm1-pins {</div><div class='add'>+		pins-disp-pwm1 {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO30__FUNC_O_DISP_PWM1&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dp_tx_hpd: dp-tx-hpd-pins {</div><div class='add'>+		pins-dp-tx-hpd {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO46__FUNC_I0_DP_TX_HPD&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gsc_int: gsc-int-pins {</div><div class='add'>+		pins-gsc-ap-int-odl {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO0__FUNC_B_GPIO0&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c0_pins: i2c0-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO56__FUNC_B1_SDA0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO55__FUNC_B1_SCL0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c1_pins: i2c1-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO58__FUNC_B1_SDA1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO57__FUNC_B1_SCL1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c2_pins: i2c2-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO60__FUNC_B1_SDA2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO59__FUNC_B1_SCL2&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+			drive-strength = &lt;12&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c3_pins: i2c3-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO62__FUNC_B1_SDA3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO61__FUNC_B1_SCL3&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c4_pins: i2c4-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO64__FUNC_B1_SDA4&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO63__FUNC_B1_SCL4&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c5_pins: i2c5-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO66__FUNC_B1_SDA5&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO65__FUNC_B1_SCL5&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c6_pins: i2c6-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO68__FUNC_B1_SDA6&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO67__FUNC_B1_SCL6&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mipi_disp_avdd_en: mipi-disp-avdd-en-pins {</div><div class='add'>+		pins-en-ppvar-mipi-disp {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO3__FUNC_B_GPIO3&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mipi_disp_avee_en: mipi-disp-avee-en-pins {</div><div class='add'>+		pins-en-ppvar-mipi-disp-150ma {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO4__FUNC_B_GPIO4&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mipi_dsi_pins: mipi-dsi-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO1__FUNC_B_GPIO1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO25__FUNC_B_GPIO25&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc0_pins_default: mmc0-default-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO161__FUNC_B1_MSDC0_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO160__FUNC_B1_MSDC0_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO159__FUNC_B1_MSDC0_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO158__FUNC_B1_MSDC0_DAT3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO154__FUNC_B1_MSDC0_DAT4&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO153__FUNC_B1_MSDC0_DAT5&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO152__FUNC_B1_MSDC0_DAT6&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO151__FUNC_B1_MSDC0_DAT7&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO156__FUNC_B1_MSDC0_CMD&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO157__FUNC_B1_MSDC0_CLK&gt;;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-rst {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO155__FUNC_O_MSDC0_RSTB&gt;;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc0_pins_uhs: mmc0-uhs-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO161__FUNC_B1_MSDC0_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO160__FUNC_B1_MSDC0_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO159__FUNC_B1_MSDC0_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO158__FUNC_B1_MSDC0_DAT3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO154__FUNC_B1_MSDC0_DAT4&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO153__FUNC_B1_MSDC0_DAT5&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO152__FUNC_B1_MSDC0_DAT6&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO151__FUNC_B1_MSDC0_DAT7&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO156__FUNC_B1_MSDC0_CMD&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO157__FUNC_B1_MSDC0_CLK&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-ds {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO162__FUNC_B0_MSDC0_DSL&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-rst {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO155__FUNC_O_MSDC0_RSTB&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	nor_pins: nor-default-pins {</div><div class='add'>+		pins-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO127__FUNC_B0_SPINOR_IO0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO125__FUNC_O_SPINOR_CK&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO128__FUNC_B0_SPINOR_IO1&gt;;</div><div class='add'>+			bias-pull-down;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-cs {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO126__FUNC_O_SPINOR_CS&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie_pins: pcie-default-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO47__FUNC_I1_WAKEN&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO48__FUNC_O_PERSTN&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO49__FUNC_B1_CLKREQN&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	scp_pins: scp-pins {</div><div class='add'>+		pins-scp-vreq {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO98__FUNC_O_SCP_VREQ_VAO&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi0_pins: spi0-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO69__FUNC_O_SPIM0_CSB&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO70__FUNC_O_SPIM0_CLK&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO71__FUNC_B0_SPIM0_MOSI&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO72__FUNC_B0_SPIM0_MISO&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi1_pins_default: spi1-default-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO75__FUNC_O_SPIM1_CSB&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO76__FUNC_O_SPIM1_CLK&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO77__FUNC_B0_SPIM1_MOSI&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO78__FUNC_B0_SPIM1_MISO&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi1_pins_sleep: spi1-sleep-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO75__FUNC_B_GPIO75&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO76__FUNC_B_GPIO76&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO77__FUNC_B_GPIO77&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO78__FUNC_B_GPIO78&gt;;</div><div class='add'>+			bias-pull-down;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi2_pins: spi2-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO79__FUNC_O_SPIM2_CSB&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO80__FUNC_O_SPIM2_CLK&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO81__FUNC_B0_SPIM2_MOSI&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO82__FUNC_B0_SPIM2_MISO&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart0_pins: uart0-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO31__FUNC_O_UTXD0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO32__FUNC_I1_URXD0&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wlan_en: wlan-en-pins {</div><div class='add'>+		pins-en-pp3300-wlan {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO12__FUNC_B_GPIO12&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pmic {</div><div class='add'>+	interrupts-extended = &lt;&amp;pio 222 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;postmask0_in {</div><div class='add'>+	remote-endpoint = &lt;&amp;gamma0_out&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;postmask0_out {</div><div class='add'>+	remote-endpoint = &lt;&amp;dither0_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;scp_cluster {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;scp_c0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;scp_pins&gt;;</div><div class='add'>+	firmware-name = "mediatek/mt8188/scp.img";</div><div class='add'>+	memory-region = &lt;&amp;scp_mem_reserved&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sound {</div><div class='add'>+	pinctrl-names = "aud_etdm_hp_on", "aud_etdm_hp_off",</div><div class='add'>+			"aud_etdm_spk_on", "aud_etdm_spk_off",</div><div class='add'>+			"aud_mtkaif_on", "aud_mtkaif_off";</div><div class='add'>+	pinctrl-0 = &lt;&amp;aud_etdm_hp_on&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;aud_etdm_hp_off&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;aud_etdm_spk_on&gt;;</div><div class='add'>+	pinctrl-3 = &lt;&amp;aud_etdm_spk_off&gt;;</div><div class='add'>+	pinctrl-4 = &lt;&amp;aud_mtkaif_on&gt;;</div><div class='add'>+	pinctrl-5 = &lt;&amp;aud_mtkaif_off&gt;;</div><div class='add'>+	mediatek,adsp = &lt;&amp;adsp&gt;;</div><div class='add'>+	/* The audio-routing is defined in each board dts */</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;spi0_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	cros_ec: ec@0 {</div><div class='add'>+		compatible = "google,cros-ec-spi";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 149 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;cros_ec_int&gt;;</div><div class='add'>+		spi-max-frequency = &lt;3000000&gt;;</div><div class='add'>+</div><div class='add'>+		i2c_tunnel: i2c-tunnel {</div><div class='add'>+			compatible = "google,cros-ec-i2c-tunnel";</div><div class='add'>+			google,remote-bus = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cbas {</div><div class='add'>+			compatible = "google,cros-cbas";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi1 {</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;spi1_pins_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;spi1_pins_sleep&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;spi2_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart0_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;u3phy0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;u3phy1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;u3phy2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB detachable base */</div><div class='add'>+&amp;ssusb0 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	vusb33-supply = &lt;&amp;pp3300_s3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xhci0 {</div><div class='add'>+	/* controlled by EC */</div><div class='add'>+	vbus-supply = &lt;&amp;pp3300_z1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB3 hub */</div><div class='add'>+&amp;ssusb1 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	vusb33-supply = &lt;&amp;pp3300_s3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xhci1 {</div><div class='add'>+	vusb33-supply = &lt;&amp;pp3300_s3&gt;;</div><div class='add'>+	vbus-supply = &lt;&amp;pp5000_usb_vbus&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB BT */</div><div class='add'>+&amp;ssusb2 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	vusb33-supply = &lt;&amp;pp3300_s3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;vdosys0 {</div><div class='add'>+	port {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		vdosys0_ep_main: endpoint@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			remote-endpoint = &lt;&amp;ovl0_in&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;vdosys1 {</div><div class='add'>+	port {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		vdosys1_ep_ext: endpoint@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			remote-endpoint = &lt;&amp;ethdr0_in&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xhci2 {</div><div class='add'>+	/* no power supply since MT7921's power is controlled by PCIe */</div><div class='add'>+	/* MT7921's USB BT has issues with USB2 LPM */</div><div class='add'>+	usb2-lpm-disable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include &lt;arm/cros-ec-keyboard.dtsi&gt;</div><div class='add'>+</div><div class='add'>+&amp;keyboard_controller {</div><div class='add'>+	function-row-physmap = &lt;</div><div class='add'>+		MATRIX_KEY(0x00, 0x02, 0)	/* T1 */</div><div class='add'>+		MATRIX_KEY(0x03, 0x02, 0)	/* T2 */</div><div class='add'>+		MATRIX_KEY(0x02, 0x02, 0)	/* T3 */</div><div class='add'>+		MATRIX_KEY(0x01, 0x02, 0)	/* T4 */</div><div class='add'>+		MATRIX_KEY(0x03, 0x04, 0)	/* T5 */</div><div class='add'>+		MATRIX_KEY(0x02, 0x04, 0)	/* T6 */</div><div class='add'>+		MATRIX_KEY(0x01, 0x04, 0)	/* T7 */</div><div class='add'>+		MATRIX_KEY(0x02, 0x09, 0)	/* T8 */</div><div class='add'>+		MATRIX_KEY(0x01, 0x09, 0)	/* T9 */</div><div class='add'>+		MATRIX_KEY(0x00, 0x04, 0)	/* T10 */</div><div class='add'>+	&gt;;</div><div class='add'>+</div><div class='add'>+	linux,keymap = &lt;</div><div class='add'>+		MATRIX_KEY(0x00, 0x02, KEY_BACK)</div><div class='add'>+		MATRIX_KEY(0x03, 0x02, KEY_REFRESH)</div><div class='add'>+		MATRIX_KEY(0x02, 0x02, KEY_ZOOM)</div><div class='add'>+		MATRIX_KEY(0x01, 0x02, KEY_SCALE)</div><div class='add'>+		MATRIX_KEY(0x03, 0x04, KEY_BRIGHTNESSDOWN)</div><div class='add'>+		MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSUP)</div><div class='add'>+		MATRIX_KEY(0x01, 0x04, KEY_MICMUTE)</div><div class='add'>+		MATRIX_KEY(0x02, 0x09, KEY_MUTE)</div><div class='add'>+		MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)</div><div class='add'>+		MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)</div><div class='add'>+		CROS_STD_MAIN_KEYMAP</div><div class='add'>+	&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi<br/>new file mode 100644<br/>index 000000000000..90c388f1890f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8188.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8188.dtsi</a></div><div class='hunk'>@@ -0,0 +1,3555 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2023 MediaTek Inc.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include &lt;dt-bindings/clock/mediatek,mt8188-clk.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/mailbox/mediatek,mt8188-gce.h&gt;</div><div class='add'>+#include &lt;dt-bindings/memory/mediatek,mt8188-memory-port.h&gt;</div><div class='add'>+#include &lt;dt-bindings/phy/phy.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/power/mediatek,mt8188-power.h&gt;</div><div class='add'>+#include &lt;dt-bindings/reset/mt8188-resets.h&gt;</div><div class='add'>+#include &lt;dt-bindings/thermal/thermal.h&gt;</div><div class='add'>+#include &lt;dt-bindings/thermal/mediatek,lvts-thermal.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "mediatek,mt8188";</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		dp-intf0 = &amp;dp_intf0;</div><div class='add'>+		dp-intf1 = &amp;dp_intf1;</div><div class='add'>+		dsc0 = &amp;dsc0;</div><div class='add'>+		ethdr0 = &amp;ethdr0;</div><div class='add'>+		gce0 = &amp;gce0;</div><div class='add'>+		gce1 = &amp;gce1;</div><div class='add'>+		merge0 = &amp;merge0;</div><div class='add'>+		merge1 = &amp;merge1;</div><div class='add'>+		merge2 = &amp;merge2;</div><div class='add'>+		merge3 = &amp;merge3;</div><div class='add'>+		merge4 = &amp;merge4;</div><div class='add'>+		merge5 = &amp;merge5;</div><div class='add'>+		mutex0 = &amp;mutex0;</div><div class='add'>+		mutex1 = &amp;mutex1;</div><div class='add'>+		padding0 = &amp;padding0;</div><div class='add'>+		padding1 = &amp;padding1;</div><div class='add'>+		padding2 = &amp;padding2;</div><div class='add'>+		padding3 = &amp;padding3;</div><div class='add'>+		padding4 = &amp;padding4;</div><div class='add'>+		padding5 = &amp;padding5;</div><div class='add'>+		padding6 = &amp;padding6;</div><div class='add'>+		padding7 = &amp;padding7;</div><div class='add'>+		vdo1-rdma0 = &amp;vdo1_rdma0;</div><div class='add'>+		vdo1-rdma1 = &amp;vdo1_rdma1;</div><div class='add'>+		vdo1-rdma2 = &amp;vdo1_rdma2;</div><div class='add'>+		vdo1-rdma3 = &amp;vdo1_rdma3;</div><div class='add'>+		vdo1-rdma4 = &amp;vdo1_rdma4;</div><div class='add'>+		vdo1-rdma5 = &amp;vdo1_rdma5;</div><div class='add'>+		vdo1-rdma6 = &amp;vdo1_rdma6;</div><div class='add'>+		vdo1-rdma7 = &amp;vdo1_rdma7;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x000&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clock-frequency = &lt;2000000000&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;282&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_off_l &amp;cluster_off_l&gt;;</div><div class='add'>+			i-cache-size = &lt;32768&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;128&gt;;</div><div class='add'>+			d-cache-size = &lt;32768&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;performance 0&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@100 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x100&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clock-frequency = &lt;2000000000&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;282&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_off_l &amp;cluster_off_l&gt;;</div><div class='add'>+			i-cache-size = &lt;32768&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;128&gt;;</div><div class='add'>+			d-cache-size = &lt;32768&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;performance 0&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@200 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x200&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clock-frequency = &lt;2000000000&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;282&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_off_l &amp;cluster_off_l&gt;;</div><div class='add'>+			i-cache-size = &lt;32768&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;128&gt;;</div><div class='add'>+			d-cache-size = &lt;32768&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;performance 0&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@300 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x300&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clock-frequency = &lt;2000000000&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;282&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_off_l &amp;cluster_off_l&gt;;</div><div class='add'>+			i-cache-size = &lt;32768&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;128&gt;;</div><div class='add'>+			d-cache-size = &lt;32768&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;performance 0&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu4: cpu@400 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x400&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clock-frequency = &lt;2000000000&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;282&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_off_l &amp;cluster_off_l&gt;;</div><div class='add'>+			i-cache-size = &lt;32768&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;128&gt;;</div><div class='add'>+			d-cache-size = &lt;32768&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;performance 0&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu5: cpu@500 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x500&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clock-frequency = &lt;2000000000&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;282&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_off_l &amp;cluster_off_l&gt;;</div><div class='add'>+			i-cache-size = &lt;32768&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;128&gt;;</div><div class='add'>+			d-cache-size = &lt;32768&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;performance 0&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu6: cpu@600 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a78";</div><div class='add'>+			reg = &lt;0x600&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clock-frequency = &lt;2600000000&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_off_b &amp;cluster_off_b&gt;;</div><div class='add'>+			i-cache-size = &lt;65536&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;65536&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_1&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;performance 1&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu7: cpu@700 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a78";</div><div class='add'>+			reg = &lt;0x700&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clock-frequency = &lt;2600000000&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_off_b &amp;cluster_off_b&gt;;</div><div class='add'>+			i-cache-size = &lt;65536&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;65536&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_1&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;performance 1&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu-map {</div><div class='add'>+			cluster0 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu2&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu3&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core4 {</div><div class='add'>+					cpu = &lt;&amp;cpu4&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core5 {</div><div class='add'>+					cpu = &lt;&amp;cpu5&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core6 {</div><div class='add'>+					cpu = &lt;&amp;cpu6&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core7 {</div><div class='add'>+					cpu = &lt;&amp;cpu7&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		idle-states {</div><div class='add'>+			entry-method = "psci";</div><div class='add'>+</div><div class='add'>+			cpu_off_l: cpu-off-l {</div><div class='add'>+				compatible = "arm,idle-state";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x00010000&gt;;</div><div class='add'>+				local-timer-stop;</div><div class='add'>+				entry-latency-us = &lt;50&gt;;</div><div class='add'>+				exit-latency-us = &lt;95&gt;;</div><div class='add'>+				min-residency-us = &lt;580&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cpu_off_b: cpu-off-b {</div><div class='add'>+				compatible = "arm,idle-state";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x00010000&gt;;</div><div class='add'>+				local-timer-stop;</div><div class='add'>+				entry-latency-us = &lt;45&gt;;</div><div class='add'>+				exit-latency-us = &lt;140&gt;;</div><div class='add'>+				min-residency-us = &lt;740&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cluster_off_l: cluster-off-l {</div><div class='add'>+				compatible = "arm,idle-state";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x01010010&gt;;</div><div class='add'>+				local-timer-stop;</div><div class='add'>+				entry-latency-us = &lt;55&gt;;</div><div class='add'>+				exit-latency-us = &lt;155&gt;;</div><div class='add'>+				min-residency-us = &lt;840&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cluster_off_b: cluster-off-b {</div><div class='add'>+				compatible = "arm,idle-state";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x01010010&gt;;</div><div class='add'>+				local-timer-stop;</div><div class='add'>+				entry-latency-us = &lt;50&gt;;</div><div class='add'>+				exit-latency-us = &lt;200&gt;;</div><div class='add'>+				min-residency-us = &lt;1000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_0: l2-cache0 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-size = &lt;131072&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;512&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l3_0&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_1: l2-cache1 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-size = &lt;262144&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;512&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l3_0&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l3_0: l3-cache {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;3&gt;;</div><div class='add'>+			cache-size = &lt;2097152&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;2048&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk13m: oscillator-13m {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;13000000&gt;;</div><div class='add'>+		clock-output-names = "clk13m";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk26m: oscillator-26m {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;26000000&gt;;</div><div class='add'>+		clock-output-names = "clk26m";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk32k: oscillator-32k {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;32768&gt;;</div><div class='add'>+		clock-output-names = "clk32k";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpu_opp_table: opp-table-gpu {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+		opp-shared;</div><div class='add'>+</div><div class='add'>+		opp-390000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;390000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;575000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0xff&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-431000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;431000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;587500&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0xff&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-473000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;473000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;600000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0xff&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-515000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;515000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;612500&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0xff&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-556000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;556000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;625000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0xff&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-598000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;598000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;637500&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0xff&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-640000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;640000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;650000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0xff&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-670000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;670000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;662500&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0xff&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-700000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;700000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;675000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0xff&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-730000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;730000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;687500&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0xff&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-760000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;760000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;700000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0xff&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-790000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;790000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;712500&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0xff&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-835000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;835000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;731250&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0xff&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-880000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;880000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;750000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0xff&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-915000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;915000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;775000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x8f&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-915000000-5 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;915000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;762500&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x30&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-915000000-6 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;915000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;750000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x70&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-950000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;950000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;800000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x8f&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-950000000-5 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;950000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;775000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x30&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-950000000-6 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;950000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;750000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x70&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu-a55 {</div><div class='add'>+		compatible = "arm,cortex-a55-pmu";</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &amp;ppi_cluster0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu-a78 {</div><div class='add'>+		compatible = "arm,cortex-a78-pmu";</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &amp;ppi_cluster1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-1.0";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound: sound {</div><div class='add'>+		mediatek,platform = &lt;&amp;afe&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	thermal_zones: thermal-zones {</div><div class='add'>+		cpu-little0-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;150&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_mcu MT8188_MCU_LITTLE_CPU0&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu_little0_alert0: trip-alert0 {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_little0_alert1: trip-alert1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_little0_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				cpu_little0_cooling_map0: map0 {</div><div class='add'>+					trip = &lt;&amp;cpu_little0_alert0&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu-little1-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;150&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_mcu MT8188_MCU_LITTLE_CPU1&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu_little1_alert0: trip-alert0 {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_little1_alert1: trip-alert1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_little1_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				cpu_little1_cooling_map0: map0 {</div><div class='add'>+					trip = &lt;&amp;cpu_little1_alert0&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu-little2-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;150&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_mcu MT8188_MCU_LITTLE_CPU2&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu_little2_alert0: trip-alert0 {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_little2_alert1: trip-alert1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_little2_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				cpu_little2_cooling_map0: map0 {</div><div class='add'>+					trip = &lt;&amp;cpu_little2_alert0&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu-little3-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;150&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_mcu MT8188_MCU_LITTLE_CPU3&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu_little3_alert0: trip-alert0 {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_little3_alert1: trip-alert1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_little3_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				cpu_little3_cooling_map0: map0 {</div><div class='add'>+					trip = &lt;&amp;cpu_little3_alert0&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu-big0-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;100&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_mcu MT8188_MCU_BIG_CPU0&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu_big0_alert0: trip-alert0 {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_big0_alert1: trip-alert1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_big0_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu_big0_alert0&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu-big1-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;100&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_mcu MT8188_MCU_BIG_CPU1&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu_big1_alert0: trip-alert0 {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_big1_alert1: trip-alert1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_big1_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu_big1_alert0&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		apu-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_ap MT8188_AP_APU&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				apu_alert0: trip-alert0 {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				apu_alert1: trip-alert1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				apu_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_ap MT8188_AP_GPU0&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				gpu_alert0: trip-alert0 {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpu_alert1: trip-alert1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpu_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;gpu_alert0&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu1-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_ap MT8188_AP_GPU1&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				gpu1_alert0: trip-alert0 {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpu1_alert1: trip-alert1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpu1_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;gpu1_alert0&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		adsp-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_ap MT8188_AP_ADSP&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				soc_alert0: trip-alert0 {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				soc_alert1: trip-alert1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				soc_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdo-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_ap MT8188_AP_VDO&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				soc1_alert0: trip-alert0 {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				soc1_alert1: trip-alert1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				soc1_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		infra-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_ap MT8188_AP_INFRA&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				soc2_alert0: trip-alert0 {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				soc2_alert1: trip-alert1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				soc2_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cam1-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_ap MT8188_AP_CAM1&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cam1_alert0: trip-alert0 {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cam1_alert1: trip-alert1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cam1_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cam2-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_ap MT8188_AP_CAM2&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cam2_alert0: trip-alert0 {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cam2_alert1: trip-alert1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cam2_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer: timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+		clock-frequency = &lt;13000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		dma-ranges = &lt;0x0 0x0 0x0 0x0 0x4 0x0&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		performance: performance-controller@11bc10 {</div><div class='add'>+			compatible = "mediatek,cpufreq-hw";</div><div class='add'>+			reg = &lt;0 0x0011bc10 0 0x120&gt;, &lt;0 0x0011bd30 0 0x120&gt;;</div><div class='add'>+			#performance-domain-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@c000000 {</div><div class='add'>+			compatible = "arm,gic-v3";</div><div class='add'>+			#interrupt-cells = &lt;4&gt;;</div><div class='add'>+			#redistributor-regions = &lt;1&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			reg = &lt;0 0x0c000000 0 0x40000&gt;,</div><div class='add'>+			      &lt;0 0x0c040000 0 0x200000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+</div><div class='add'>+			ppi-partitions {</div><div class='add'>+				ppi_cluster0: interrupt-partition-0 {</div><div class='add'>+					affinity = &lt;&amp;cpu0 &amp;cpu1 &amp;cpu2 &amp;cpu3 &amp;cpu4 &amp;cpu5&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				ppi_cluster1: interrupt-partition-1 {</div><div class='add'>+					affinity = &lt;&amp;cpu6 &amp;cpu7&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		topckgen: syscon@10000000 {</div><div class='add'>+			compatible = "mediatek,mt8188-topckgen", "syscon";</div><div class='add'>+			reg = &lt;0 0x10000000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		infracfg_ao: syscon@10001000 {</div><div class='add'>+			compatible = "mediatek,mt8188-infracfg-ao", "syscon";</div><div class='add'>+			reg = &lt;0 0x10001000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pericfg: syscon@10003000 {</div><div class='add'>+			compatible = "mediatek,mt8188-pericfg", "syscon";</div><div class='add'>+			reg = &lt;0 0x10003000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pio: pinctrl@10005000 {</div><div class='add'>+			compatible = "mediatek,mt8188-pinctrl";</div><div class='add'>+			reg = &lt;0 0x10005000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11c00000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11e10000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11e20000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11ea0000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x1000b000 0 0x1000&gt;;</div><div class='add'>+			reg-names = "iocfg0", "iocfg_rm", "iocfg_lt",</div><div class='add'>+				    "iocfg_lm", "iocfg_rt", "eint";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;pio 0 0 176&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			interrupts = &lt;GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		scpsys: syscon@10006000 {</div><div class='add'>+			compatible = "mediatek,mt8188-scpsys", "syscon", "simple-mfd";</div><div class='add'>+			reg = &lt;0 0x10006000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			/* System Power Manager */</div><div class='add'>+			spm: power-controller {</div><div class='add'>+				compatible = "mediatek,mt8188-power-controller";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				/* power domain of the SoC */</div><div class='add'>+				mfg0: power-domain@MT8188_POWER_DOMAIN_MFG0 {</div><div class='add'>+					reg = &lt;MT8188_POWER_DOMAIN_MFG0&gt;;</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+					#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					mfg1: power-domain@MT8188_POWER_DOMAIN_MFG1 {</div><div class='add'>+						reg = &lt;MT8188_POWER_DOMAIN_MFG1&gt;;</div><div class='add'>+						clocks = &lt;&amp;apmixedsys CLK_APMIXED_MFGPLL&gt;,</div><div class='add'>+							 &lt;&amp;topckgen CLK_TOP_MFG_CORE_TMP&gt;;</div><div class='add'>+						clock-names = "mfg", "alt";</div><div class='add'>+						mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+						#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						power-domain@MT8188_POWER_DOMAIN_MFG2 {</div><div class='add'>+							reg = &lt;MT8188_POWER_DOMAIN_MFG2&gt;;</div><div class='add'>+							#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						power-domain@MT8188_POWER_DOMAIN_MFG3 {</div><div class='add'>+							reg = &lt;MT8188_POWER_DOMAIN_MFG3&gt;;</div><div class='add'>+							#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						power-domain@MT8188_POWER_DOMAIN_MFG4 {</div><div class='add'>+							reg = &lt;MT8188_POWER_DOMAIN_MFG4&gt;;</div><div class='add'>+							#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				power-domain@MT8188_POWER_DOMAIN_VPPSYS0 {</div><div class='add'>+					reg = &lt;MT8188_POWER_DOMAIN_VPPSYS0&gt;;</div><div class='add'>+					clocks = &lt;&amp;topckgen CLK_TOP_VPP&gt;,</div><div class='add'>+						 &lt;&amp;topckgen CLK_TOP_CAM&gt;,</div><div class='add'>+						 &lt;&amp;topckgen CLK_TOP_CCU&gt;,</div><div class='add'>+						 &lt;&amp;topckgen CLK_TOP_IMG&gt;,</div><div class='add'>+						 &lt;&amp;topckgen CLK_TOP_VENC&gt;,</div><div class='add'>+						 &lt;&amp;topckgen CLK_TOP_VDEC&gt;,</div><div class='add'>+						 &lt;&amp;topckgen CLK_TOP_WPE_VPP&gt;,</div><div class='add'>+						 &lt;&amp;topckgen CLK_TOP_CFGREG_CLOCK_EN_VPP0&gt;,</div><div class='add'>+						 &lt;&amp;topckgen CLK_TOP_CFGREG_F26M_VPP0&gt;,</div><div class='add'>+						 &lt;&amp;vppsys0 CLK_VPP0_SMI_COMMON_MMSRAM&gt;,</div><div class='add'>+						 &lt;&amp;vppsys0 CLK_VPP0_GALS_VDO0_LARB0_MMSRAM&gt;,</div><div class='add'>+						 &lt;&amp;vppsys0 CLK_VPP0_GALS_VDO0_LARB1_MMSRAM&gt;,</div><div class='add'>+						 &lt;&amp;vppsys0 CLK_VPP0_GALS_VENCSYS_MMSRAM&gt;,</div><div class='add'>+						 &lt;&amp;vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1_MMSRAM&gt;,</div><div class='add'>+						 &lt;&amp;vppsys0 CLK_VPP0_GALS_INFRA_MMSRAM&gt;,</div><div class='add'>+						 &lt;&amp;vppsys0 CLK_VPP0_GALS_CAMSYS_MMSRAM&gt;,</div><div class='add'>+						 &lt;&amp;vppsys0 CLK_VPP0_GALS_VPP1_LARB5_MMSRAM&gt;,</div><div class='add'>+						 &lt;&amp;vppsys0 CLK_VPP0_GALS_VPP1_LARB6_MMSRAM&gt;,</div><div class='add'>+						 &lt;&amp;vppsys0 CLK_VPP0_SMI_REORDER_MMSRAM&gt;,</div><div class='add'>+						 &lt;&amp;vppsys0 CLK_VPP0_SMI_IOMMU&gt;,</div><div class='add'>+						 &lt;&amp;vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS&gt;,</div><div class='add'>+						 &lt;&amp;vppsys0 CLK_VPP0_GALS_EMI0_EMI1&gt;,</div><div class='add'>+						 &lt;&amp;vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER&gt;,</div><div class='add'>+						 &lt;&amp;vppsys0 CLK_VPP0_SMI_RSI&gt;,</div><div class='add'>+						 &lt;&amp;vppsys0 CLK_VPP0_SMI_COMMON_LARB4&gt;,</div><div class='add'>+						 &lt;&amp;vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1&gt;,</div><div class='add'>+						 &lt;&amp;vppsys0 CLK_VPP0_GALS_VPP1_WPESYS&gt;,</div><div class='add'>+						 &lt;&amp;vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1&gt;;</div><div class='add'>+					clock-names = "top", "cam", "ccu", "img", "venc",</div><div class='add'>+						      "vdec", "wpe", "cfgck", "cfgxo",</div><div class='add'>+						      "ss-sram-cmn", "ss-sram-v0l0", "ss-sram-v0l1",</div><div class='add'>+						      "ss-sram-ve0", "ss-sram-ve1", "ss-sram-ifa",</div><div class='add'>+						      "ss-sram-cam", "ss-sram-v1l5", "ss-sram-v1l6",</div><div class='add'>+						      "ss-sram-rdr", "ss-iommu", "ss-imgcam",</div><div class='add'>+						      "ss-emi", "ss-subcmn-rdr", "ss-rsi",</div><div class='add'>+						      "ss-cmn-l4", "ss-vdec1", "ss-wpe",</div><div class='add'>+						      "ss-cvdo-ve1";</div><div class='add'>+					mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+					#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					power-domain@MT8188_POWER_DOMAIN_VDOSYS0 {</div><div class='add'>+						reg = &lt;MT8188_POWER_DOMAIN_VDOSYS0&gt;;</div><div class='add'>+						clocks = &lt;&amp;topckgen CLK_TOP_CFGREG_CLOCK_EN_VDO0&gt;,</div><div class='add'>+							 &lt;&amp;topckgen CLK_TOP_CFGREG_F26M_VDO0&gt;,</div><div class='add'>+							 &lt;&amp;vdosys0 CLK_VDO0_SMI_GALS&gt;,</div><div class='add'>+							 &lt;&amp;vdosys0 CLK_VDO0_SMI_COMMON&gt;,</div><div class='add'>+							 &lt;&amp;vdosys0 CLK_VDO0_SMI_EMI&gt;,</div><div class='add'>+							 &lt;&amp;vdosys0 CLK_VDO0_SMI_IOMMU&gt;,</div><div class='add'>+							 &lt;&amp;vdosys0 CLK_VDO0_SMI_LARB&gt;,</div><div class='add'>+							 &lt;&amp;vdosys0 CLK_VDO0_SMI_RSI&gt;,</div><div class='add'>+							 &lt;&amp;vdosys0 CLK_VDO0_APB_BUS&gt;;</div><div class='add'>+						clock-names = "cfgck", "cfgxo", "ss-gals",</div><div class='add'>+							      "ss-cmn", "ss-emi", "ss-iommu",</div><div class='add'>+							      "ss-larb", "ss-rsi", "ss-bus";</div><div class='add'>+						mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+						#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						power-domain@MT8188_POWER_DOMAIN_VPPSYS1 {</div><div class='add'>+							reg = &lt;MT8188_POWER_DOMAIN_VPPSYS1&gt;;</div><div class='add'>+							clocks = &lt;&amp;topckgen CLK_TOP_CFGREG_CLOCK_EN_VPP1&gt;,</div><div class='add'>+								 &lt;&amp;topckgen CLK_TOP_CFGREG_F26M_VPP1&gt;,</div><div class='add'>+								 &lt;&amp;vppsys1 CLK_VPP1_GALS5&gt;,</div><div class='add'>+								 &lt;&amp;vppsys1 CLK_VPP1_GALS6&gt;,</div><div class='add'>+								 &lt;&amp;vppsys1 CLK_VPP1_LARB5&gt;,</div><div class='add'>+								 &lt;&amp;vppsys1 CLK_VPP1_LARB6&gt;;</div><div class='add'>+							clock-names = "cfgck", "cfgxo",</div><div class='add'>+								      "ss-vpp1-g5", "ss-vpp1-g6",</div><div class='add'>+								      "ss-vpp1-l5", "ss-vpp1-l6";</div><div class='add'>+							mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+							#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						power-domain@MT8188_POWER_DOMAIN_VDEC0 {</div><div class='add'>+							reg = &lt;MT8188_POWER_DOMAIN_VDEC0&gt;;</div><div class='add'>+							clocks = &lt;&amp;vdecsys_soc CLK_VDEC1_SOC_LARB1&gt;;</div><div class='add'>+							clock-names = "ss-vdec1-soc-l1";</div><div class='add'>+							mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+							#address-cells = &lt;1&gt;;</div><div class='add'>+							#size-cells = &lt;0&gt;;</div><div class='add'>+							#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							power-domain@MT8188_POWER_DOMAIN_VDEC1 {</div><div class='add'>+								reg = &lt;MT8188_POWER_DOMAIN_VDEC1&gt;;</div><div class='add'>+								clocks = &lt;&amp;vdecsys CLK_VDEC2_LARB1&gt;;</div><div class='add'>+								clock-names = "ss-vdec2-l1";</div><div class='add'>+								mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+								#power-domain-cells = &lt;0&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						cam_vcore: power-domain@MT8188_POWER_DOMAIN_CAM_VCORE {</div><div class='add'>+							reg = &lt;MT8188_POWER_DOMAIN_CAM_VCORE&gt;;</div><div class='add'>+							clocks = &lt;&amp;topckgen CLK_TOP_CAM&gt;,</div><div class='add'>+								 &lt;&amp;topckgen CLK_TOP_CCU&gt;,</div><div class='add'>+								 &lt;&amp;topckgen CLK_TOP_CCU_AHB&gt;,</div><div class='add'>+								 &lt;&amp;topckgen CLK_TOP_CFGREG_CLOCK_ISP_AXI_GALS&gt;;</div><div class='add'>+							clock-names = "cam", "ccu", "bus", "cfgck";</div><div class='add'>+							mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+							#address-cells = &lt;1&gt;;</div><div class='add'>+							#size-cells = &lt;0&gt;;</div><div class='add'>+							#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							power-domain@MT8188_POWER_DOMAIN_CAM_MAIN {</div><div class='add'>+								reg = &lt;MT8188_POWER_DOMAIN_CAM_MAIN&gt;;</div><div class='add'>+								clocks = &lt;&amp;camsys CLK_CAM_MAIN_LARB13&gt;,</div><div class='add'>+									 &lt;&amp;camsys CLK_CAM_MAIN_LARB14&gt;,</div><div class='add'>+									 &lt;&amp;camsys CLK_CAM_MAIN_CAM2MM0_GALS&gt;,</div><div class='add'>+									 &lt;&amp;camsys CLK_CAM_MAIN_CAM2MM1_GALS&gt;,</div><div class='add'>+									 &lt;&amp;camsys CLK_CAM_MAIN_CAM2SYS_GALS&gt;;</div><div class='add'>+								clock-names= "ss-cam-l13", "ss-cam-l14",</div><div class='add'>+									     "ss-cam-mm0", "ss-cam-mm1",</div><div class='add'>+									     "ss-camsys";</div><div class='add'>+								mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+								#address-cells = &lt;1&gt;;</div><div class='add'>+								#size-cells = &lt;0&gt;;</div><div class='add'>+								#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+								power-domain@MT8188_POWER_DOMAIN_CAM_SUBB {</div><div class='add'>+									reg = &lt;MT8188_POWER_DOMAIN_CAM_SUBB&gt;;</div><div class='add'>+									clocks = &lt;&amp;camsys CLK_CAM_MAIN_CAM_SUBB&gt;,</div><div class='add'>+										 &lt;&amp;camsys_rawb CLK_CAM_RAWB_LARBX&gt;,</div><div class='add'>+										 &lt;&amp;camsys_yuvb CLK_CAM_YUVB_LARBX&gt;;</div><div class='add'>+									clock-names = "ss-camb-sub",</div><div class='add'>+										      "ss-camb-raw",</div><div class='add'>+										      "ss-camb-yuv";</div><div class='add'>+									#power-domain-cells = &lt;0&gt;;</div><div class='add'>+								};</div><div class='add'>+</div><div class='add'>+								power-domain@MT8188_POWER_DOMAIN_CAM_SUBA {</div><div class='add'>+									reg =&lt;MT8188_POWER_DOMAIN_CAM_SUBA&gt;;</div><div class='add'>+									clocks = &lt;&amp;camsys CLK_CAM_MAIN_CAM_SUBA&gt;,</div><div class='add'>+										 &lt;&amp;camsys_rawa CLK_CAM_RAWA_LARBX&gt;,</div><div class='add'>+										 &lt;&amp;camsys_yuva CLK_CAM_YUVA_LARBX&gt;;</div><div class='add'>+									clock-names = "ss-cama-sub",</div><div class='add'>+										      "ss-cama-raw",</div><div class='add'>+										      "ss-cama-yuv";</div><div class='add'>+									#power-domain-cells = &lt;0&gt;;</div><div class='add'>+								};</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						power-domain@MT8188_POWER_DOMAIN_VDOSYS1 {</div><div class='add'>+							reg = &lt;MT8188_POWER_DOMAIN_VDOSYS1&gt;;</div><div class='add'>+							clocks = &lt;&amp;topckgen CLK_TOP_CFGREG_CLOCK_EN_VDO1&gt;,</div><div class='add'>+								 &lt;&amp;topckgen CLK_TOP_CFGREG_F26M_VDO1&gt;,</div><div class='add'>+								 &lt;&amp;vdosys1 CLK_VDO1_SMI_LARB2&gt;,</div><div class='add'>+								 &lt;&amp;vdosys1 CLK_VDO1_SMI_LARB3&gt;,</div><div class='add'>+								 &lt;&amp;vdosys1 CLK_VDO1_GALS&gt;;</div><div class='add'>+							clock-names = "cfgck", "cfgxo", "ss-larb2",</div><div class='add'>+								      "ss-larb3", "ss-gals";</div><div class='add'>+							mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+							#address-cells = &lt;1&gt;;</div><div class='add'>+							#size-cells = &lt;0&gt;;</div><div class='add'>+							#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							power-domain@MT8188_POWER_DOMAIN_HDMI_TX {</div><div class='add'>+								reg = &lt;MT8188_POWER_DOMAIN_HDMI_TX&gt;;</div><div class='add'>+								clocks = &lt;&amp;topckgen CLK_TOP_HDMI_APB&gt;,</div><div class='add'>+									 &lt;&amp;topckgen CLK_TOP_HDCP_24M&gt;;</div><div class='add'>+								clock-names = "bus", "hdcp";</div><div class='add'>+								mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+								#power-domain-cells = &lt;0&gt;;</div><div class='add'>+							};</div><div class='add'>+</div><div class='add'>+							power-domain@MT8188_POWER_DOMAIN_DP_TX {</div><div class='add'>+								reg = &lt;MT8188_POWER_DOMAIN_DP_TX&gt;;</div><div class='add'>+								mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+								#power-domain-cells = &lt;0&gt;;</div><div class='add'>+							};</div><div class='add'>+</div><div class='add'>+							power-domain@MT8188_POWER_DOMAIN_EDP_TX {</div><div class='add'>+								reg = &lt;MT8188_POWER_DOMAIN_EDP_TX&gt;;</div><div class='add'>+								mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+								#power-domain-cells = &lt;0&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						power-domain@MT8188_POWER_DOMAIN_VENC {</div><div class='add'>+							reg = &lt;MT8188_POWER_DOMAIN_VENC&gt;;</div><div class='add'>+							clocks = &lt;&amp;vencsys CLK_VENC1_LARB&gt;,</div><div class='add'>+								 &lt;&amp;vencsys CLK_VENC1_VENC&gt;,</div><div class='add'>+								 &lt;&amp;vencsys CLK_VENC1_GALS&gt;,</div><div class='add'>+								 &lt;&amp;vencsys CLK_VENC1_GALS_SRAM&gt;;</div><div class='add'>+							clock-names = "ss-ve1-larb", "ss-ve1-core",</div><div class='add'>+								      "ss-ve1-gals", "ss-ve1-sram";</div><div class='add'>+							mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+							#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						power-domain@MT8188_POWER_DOMAIN_WPE {</div><div class='add'>+							reg = &lt;MT8188_POWER_DOMAIN_WPE&gt;;</div><div class='add'>+							clocks = &lt;&amp;wpesys CLK_WPE_TOP_SMI_LARB7&gt;,</div><div class='add'>+								 &lt;&amp;wpesys CLK_WPE_TOP_SMI_LARB7_PCLK_EN&gt;;</div><div class='add'>+							clock-names = "ss-wpe-l7", "ss-wpe-l7pce";</div><div class='add'>+							mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+							#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				power-domain@MT8188_POWER_DOMAIN_PEXTP_MAC_P0 {</div><div class='add'>+					reg = &lt;MT8188_POWER_DOMAIN_PEXTP_MAC_P0&gt;;</div><div class='add'>+					mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+					clocks = &lt;&amp;pericfg_ao CLK_PERI_AO_PCIE_P0_FMEM&gt;;</div><div class='add'>+					clock-names = "ss-pextp-fmem";</div><div class='add'>+					#power-domain-cells = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				power-domain@MT8188_POWER_DOMAIN_CSIRX_TOP {</div><div class='add'>+					reg = &lt;MT8188_POWER_DOMAIN_CSIRX_TOP&gt;;</div><div class='add'>+					clocks = &lt;&amp;topckgen CLK_TOP_SENINF&gt;,</div><div class='add'>+						 &lt;&amp;topckgen CLK_TOP_SENINF1&gt;;</div><div class='add'>+					clock-names = "seninf0", "seninf1";</div><div class='add'>+					#power-domain-cells = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				power-domain@MT8188_POWER_DOMAIN_PEXTP_PHY_TOP {</div><div class='add'>+					reg = &lt;MT8188_POWER_DOMAIN_PEXTP_PHY_TOP&gt;;</div><div class='add'>+					#power-domain-cells = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				power-domain@MT8188_POWER_DOMAIN_ADSP_AO {</div><div class='add'>+					reg = &lt;MT8188_POWER_DOMAIN_ADSP_AO&gt;;</div><div class='add'>+					clocks = &lt;&amp;topckgen CLK_TOP_AUDIO_LOCAL_BUS&gt;,</div><div class='add'>+						 &lt;&amp;topckgen CLK_TOP_ADSP&gt;;</div><div class='add'>+					clock-names = "bus", "main";</div><div class='add'>+					mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+					#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					power-domain@MT8188_POWER_DOMAIN_ADSP_INFRA {</div><div class='add'>+						reg = &lt;MT8188_POWER_DOMAIN_ADSP_INFRA&gt;;</div><div class='add'>+						mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+						#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						power-domain@MT8188_POWER_DOMAIN_AUDIO_ASRC {</div><div class='add'>+							reg = &lt;MT8188_POWER_DOMAIN_AUDIO_ASRC&gt;;</div><div class='add'>+							clocks = &lt;&amp;topckgen CLK_TOP_ASM_H&gt;;</div><div class='add'>+							clock-names = "asm";</div><div class='add'>+							mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+							#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						power-domain@MT8188_POWER_DOMAIN_AUDIO {</div><div class='add'>+							reg = &lt;MT8188_POWER_DOMAIN_AUDIO&gt;;</div><div class='add'>+							clocks = &lt;&amp;topckgen CLK_TOP_A1SYS_HP&gt;,</div><div class='add'>+								 &lt;&amp;topckgen CLK_TOP_AUD_INTBUS&gt;,</div><div class='add'>+								 &lt;&amp;adsp_audio26m CLK_AUDIODSP_AUDIO26M&gt;;</div><div class='add'>+							clock-names = "a1sys", "intbus", "adspck";</div><div class='add'>+							mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+							#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						power-domain@MT8188_POWER_DOMAIN_ADSP {</div><div class='add'>+							reg = &lt;MT8188_POWER_DOMAIN_ADSP&gt;;</div><div class='add'>+							mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+							#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				power-domain@MT8188_POWER_DOMAIN_ETHER {</div><div class='add'>+					reg = &lt;MT8188_POWER_DOMAIN_ETHER&gt;;</div><div class='add'>+					clocks = &lt;&amp;pericfg_ao CLK_PERI_AO_ETHERNET_MAC&gt;;</div><div class='add'>+					clock-names = "ethermac";</div><div class='add'>+					mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+					#power-domain-cells = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		watchdog: watchdog@10007000 {</div><div class='add'>+			compatible = "mediatek,mt8188-wdt";</div><div class='add'>+			reg = &lt;0 0x10007000 0 0x100&gt;;</div><div class='add'>+			mediatek,disable-extrst;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		apmixedsys: syscon@1000c000 {</div><div class='add'>+			compatible = "mediatek,mt8188-apmixedsys", "syscon";</div><div class='add'>+			reg = &lt;0 0x1000c000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		systimer: timer@10017000 {</div><div class='add'>+			compatible = "mediatek,mt8188-timer", "mediatek,mt6765-timer";</div><div class='add'>+			reg = &lt;0 0x10017000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk13m&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pwrap: pwrap@10024000 {</div><div class='add'>+			compatible = "mediatek,mt8188-pwrap", "mediatek,mt8195-pwrap", "syscon";</div><div class='add'>+			reg = &lt;0 0x10024000 0 0x1000&gt;;</div><div class='add'>+			reg-names = "pwrap";</div><div class='add'>+			interrupts = &lt;GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg_ao CLK_INFRA_AO_PMIC_AP&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_PMIC_TMR&gt;;</div><div class='add'>+			clock-names = "spi", "wrap";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spmi: spmi@10027000 {</div><div class='add'>+			compatible = "mediatek,mt8188-spmi", "mediatek,mt8195-spmi";</div><div class='add'>+			reg = &lt;0 0x10027000 0 0xe00&gt;, &lt;0 0x10029000 0 0x100&gt;;</div><div class='add'>+			reg-names = "pmif", "spmimst";</div><div class='add'>+			assigned-clocks = &lt;&amp;topckgen CLK_TOP_SPMI_M_MST&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_ULPOSC1_D10&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg_ao CLK_INFRA_AO_PMIC_AP&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_PMIC_TMR&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SPMI_M_MST&gt;;</div><div class='add'>+			clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		infra_iommu: iommu@10315000 {</div><div class='add'>+			compatible = "mediatek,mt8188-iommu-infra";</div><div class='add'>+			reg = &lt;0 0x10315000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			#iommu-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gce0: mailbox@10320000 {</div><div class='add'>+			compatible = "mediatek,mt8188-gce";</div><div class='add'>+			reg = &lt;0 0x10320000 0 0x4000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			#mbox-cells = &lt;2&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg_ao CLK_INFRA_AO_GCE&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gce1: mailbox@10330000 {</div><div class='add'>+			compatible = "mediatek,mt8188-gce";</div><div class='add'>+			reg = &lt;0 0x10330000 0 0x4000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			#mbox-cells = &lt;2&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg_ao CLK_INFRA_AO_GCE2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		scp_cluster: scp@10720000 {</div><div class='add'>+			compatible = "mediatek,mt8188-scp-dual";</div><div class='add'>+			reg = &lt;0 0x10720000 0 0xe0000&gt;;</div><div class='add'>+			reg-names = "cfg";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges = &lt;0 0 0x10500000 0x100000&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			scp_c0: scp@0 {</div><div class='add'>+				compatible = "mediatek,scp-core";</div><div class='add'>+				reg = &lt;0x0 0xd0000&gt;;</div><div class='add'>+				reg-names = "sram";</div><div class='add'>+				interrupts = &lt;GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			scp_c1: scp@d0000 {</div><div class='add'>+				compatible = "mediatek,scp-core";</div><div class='add'>+				reg = &lt;0xd0000 0x2f000&gt;;</div><div class='add'>+				reg-names = "sram";</div><div class='add'>+				interrupts = &lt;GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		afe: audio-controller@10b10000 {</div><div class='add'>+			compatible = "mediatek,mt8188-afe";</div><div class='add'>+			reg = &lt;0 0x10b10000 0 0x10000&gt;;</div><div class='add'>+			assigned-clocks = &lt;&amp;topckgen CLK_TOP_A1SYS_HP&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_APLL1_D4&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk26m&gt;,</div><div class='add'>+				 &lt;&amp;apmixedsys CLK_APMIXED_APLL1&gt;,</div><div class='add'>+				 &lt;&amp;apmixedsys CLK_APMIXED_APLL2&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_APLL12_CK_DIV0&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_APLL12_CK_DIV1&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_APLL12_CK_DIV2&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_APLL12_CK_DIV3&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_APLL12_CK_DIV9&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_A1SYS_HP&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_AUD_INTBUS&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_AUDIO_H&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_AUDIO_LOCAL_BUS&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_DPTX&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_I2SO1&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_I2SO2&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_I2SI1&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_I2SI2&gt;,</div><div class='add'>+				 &lt;&amp;adsp_audio26m CLK_AUDIODSP_AUDIO26M&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_APLL1_D4&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_APLL2_D4&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_APLL12_CK_DIV4&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_A2SYS&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_AUD_IEC&gt;;</div><div class='add'>+			clock-names = "clk26m",</div><div class='add'>+				      "apll1",</div><div class='add'>+				      "apll2",</div><div class='add'>+				      "apll12_div0",</div><div class='add'>+				      "apll12_div1",</div><div class='add'>+				      "apll12_div2",</div><div class='add'>+				      "apll12_div3",</div><div class='add'>+				      "apll12_div9",</div><div class='add'>+				      "top_a1sys_hp",</div><div class='add'>+				      "top_aud_intbus",</div><div class='add'>+				      "top_audio_h",</div><div class='add'>+				      "top_audio_local_bus",</div><div class='add'>+				      "top_dptx",</div><div class='add'>+				      "top_i2so1",</div><div class='add'>+				      "top_i2so2",</div><div class='add'>+				      "top_i2si1",</div><div class='add'>+				      "top_i2si2",</div><div class='add'>+				      "adsp_audio_26m",</div><div class='add'>+				      "apll1_d4",</div><div class='add'>+				      "apll2_d4",</div><div class='add'>+				      "apll12_div4",</div><div class='add'>+				      "top_a2sys",</div><div class='add'>+				      "top_aud_iec";</div><div class='add'>+			interrupts = &lt;GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_AUDIO&gt;;</div><div class='add'>+			resets = &lt;&amp;watchdog MT8188_TOPRGU_AUDIO_SW_RST&gt;;</div><div class='add'>+			reset-names = "audiosys";</div><div class='add'>+			mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+			mediatek,topckgen = &lt;&amp;topckgen&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		adsp: adsp@10b80000 {</div><div class='add'>+			compatible = "mediatek,mt8188-dsp";</div><div class='add'>+			reg = &lt;0 0x10b80000 0 0x2000&gt;,</div><div class='add'>+			      &lt;0 0x10d00000 0 0x80000&gt;,</div><div class='add'>+			      &lt;0 0x10b8b000 0 0x100&gt;,</div><div class='add'>+			      &lt;0 0x10b8f000 0 0x1000&gt;;</div><div class='add'>+			reg-names = "cfg", "sram", "sec", "bus";</div><div class='add'>+			assigned-clocks = &lt;&amp;topckgen CLK_TOP_ADSP&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_ADSP&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_AUDIO_LOCAL_BUS&gt;;</div><div class='add'>+			clock-names = "audiodsp", "adsp_bus";</div><div class='add'>+			mboxes = &lt;&amp;adsp_mailbox0&gt;, &lt;&amp;adsp_mailbox1&gt;;</div><div class='add'>+			mbox-names = "rx", "tx";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_ADSP&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		adsp_mailbox0: mailbox@10b86100 {</div><div class='add'>+			compatible = "mediatek,mt8188-adsp-mbox", "mediatek,mt8186-adsp-mbox";</div><div class='add'>+			reg = &lt;0 0x10b86100 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			#mbox-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		adsp_mailbox1: mailbox@10b87100 {</div><div class='add'>+			compatible = "mediatek,mt8188-adsp-mbox", "mediatek,mt8186-adsp-mbox";</div><div class='add'>+			reg = &lt;0 0x10b87100 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			#mbox-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		adsp_audio26m: clock-controller@10b91100 {</div><div class='add'>+			compatible = "mediatek,mt8188-adsp-audio26m";</div><div class='add'>+			reg = &lt;0 0x10b91100 0 0x100&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart0: serial@11001100 {</div><div class='add'>+			compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart";</div><div class='add'>+			reg = &lt;0 0x11001100 0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk26m&gt;, &lt;&amp;infracfg_ao CLK_INFRA_AO_UART0&gt;;</div><div class='add'>+			clock-names = "baud", "bus";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart1: serial@11001200 {</div><div class='add'>+			compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart";</div><div class='add'>+			reg = &lt;0 0x11001200 0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk26m&gt;, &lt;&amp;infracfg_ao CLK_INFRA_AO_UART1&gt;;</div><div class='add'>+			clock-names = "baud", "bus";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart2: serial@11001300 {</div><div class='add'>+			compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart";</div><div class='add'>+			reg = &lt;0 0x11001300 0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk26m&gt;, &lt;&amp;infracfg_ao CLK_INFRA_AO_UART2&gt;;</div><div class='add'>+			clock-names = "baud", "bus";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart3: serial@11001400 {</div><div class='add'>+			compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart";</div><div class='add'>+			reg = &lt;0 0x11001400 0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk26m&gt;, &lt;&amp;infracfg_ao CLK_INFRA_AO_UART3&gt;;</div><div class='add'>+			clock-names = "baud", "bus";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		auxadc: adc@11002000 {</div><div class='add'>+			compatible = "mediatek,mt8188-auxadc", "mediatek,mt8173-auxadc";</div><div class='add'>+			reg = &lt;0 0x11002000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg_ao CLK_INFRA_AO_AUXADC&gt;;</div><div class='add'>+			clock-names = "main";</div><div class='add'>+			#io-channel-cells = &lt;1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pericfg_ao: syscon@11003000 {</div><div class='add'>+			compatible = "mediatek,mt8188-pericfg-ao", "syscon";</div><div class='add'>+			reg = &lt;0 0x11003000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi0: spi@1100a000 {</div><div class='add'>+			compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0 0x1100a000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_UNIVPLL_D6_D2&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SPI&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_SPI0&gt;;</div><div class='add'>+			clock-names = "parent-clk", "sel-clk", "spi-clk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		lvts_ap: thermal-sensor@1100b000 {</div><div class='add'>+			compatible = "mediatek,mt8188-lvts-ap";</div><div class='add'>+			reg = &lt;0 0x1100b000 0 0xc00&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg_ao CLK_INFRA_AO_THERM&gt;;</div><div class='add'>+			resets = &lt;&amp;infracfg_ao MT8188_INFRA_RST1_THERMAL_CTRL_RST&gt;;</div><div class='add'>+			nvmem-cells = &lt;&amp;lvts_efuse_data1&gt;;</div><div class='add'>+			nvmem-cell-names = "lvts-calib-data-1";</div><div class='add'>+			#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		disp_pwm0: pwm@1100e000 {</div><div class='add'>+			compatible = "mediatek,mt8188-disp-pwm", "mediatek,mt8183-disp-pwm";</div><div class='add'>+			reg = &lt;0 0x1100e000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_DISP_PWM0&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_DISP_PWM&gt;;</div><div class='add'>+			clock-names = "main", "mm";</div><div class='add'>+			interrupts = &lt;GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			#pwm-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		disp_pwm1: pwm@1100f000 {</div><div class='add'>+			compatible = "mediatek,mt8188-disp-pwm", "mediatek,mt8183-disp-pwm";</div><div class='add'>+			reg = &lt;0 0x1100f000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_DISP_PWM1&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_DISP_PWM1&gt;;</div><div class='add'>+			clock-names = "main", "mm";</div><div class='add'>+			interrupts = &lt;GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			#pwm-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi1: spi@11010000 {</div><div class='add'>+			compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0 0x11010000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_UNIVPLL_D6_D2&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SPI&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_SPI1&gt;;</div><div class='add'>+			clock-names = "parent-clk", "sel-clk", "spi-clk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi2: spi@11012000 {</div><div class='add'>+			compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0 0x11012000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_UNIVPLL_D6_D2&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SPI&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_SPI2&gt;;</div><div class='add'>+			clock-names = "parent-clk", "sel-clk", "spi-clk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi3: spi@11013000 {</div><div class='add'>+			compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0 0x11013000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_UNIVPLL_D6_D2&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SPI&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_SPI3&gt;;</div><div class='add'>+			clock-names = "parent-clk", "sel-clk", "spi-clk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi4: spi@11018000 {</div><div class='add'>+			compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0 0x11018000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_UNIVPLL_D6_D2&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SPI&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_SPI4&gt;;</div><div class='add'>+			clock-names = "parent-clk", "sel-clk", "spi-clk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi5: spi@11019000 {</div><div class='add'>+			compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0 0x11019000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_UNIVPLL_D6_D2&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SPI&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_SPI5&gt;;</div><div class='add'>+			clock-names = "parent-clk", "sel-clk", "spi-clk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ssusb1: usb@11201000 {</div><div class='add'>+			compatible = "mediatek,mt8188-mtu3", "mediatek,mtu3";</div><div class='add'>+			reg = &lt;0 0x11201000 0 0x2dff&gt;, &lt;0 0x11203e00 0 0x0100&gt;;</div><div class='add'>+			reg-names = "mac", "ippc";</div><div class='add'>+			ranges = &lt;0 0 0 0x11200000 0 0x3f00&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			assigned-clocks = &lt;&amp;topckgen CLK_TOP_USB_TOP&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_UNIVPLL_D5_D4&gt;;</div><div class='add'>+			clocks = &lt;&amp;pericfg_ao CLK_PERI_AO_SSUSB_BUS&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SSUSB_TOP_REF&gt;,</div><div class='add'>+				 &lt;&amp;pericfg_ao CLK_PERI_AO_SSUSB_XHCI&gt;;</div><div class='add'>+			clock-names = "sys_ck", "ref_ck", "mcu_ck";</div><div class='add'>+			phys = &lt;&amp;u2port1 PHY_TYPE_USB2&gt;, &lt;&amp;u3port1 PHY_TYPE_USB3&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+			mediatek,syscon-wakeup = &lt;&amp;pericfg 0x468 2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			xhci1: usb@0 {</div><div class='add'>+				compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";</div><div class='add'>+				reg = &lt;0 0 0 0x1000&gt;;</div><div class='add'>+				reg-names = "mac";</div><div class='add'>+				interrupts = &lt;GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				assigned-clocks = &lt;&amp;topckgen CLK_TOP_SSUSB_XHCI&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_UNIVPLL_D5_D4&gt;;</div><div class='add'>+				clocks = &lt;&amp;pericfg_ao CLK_PERI_AO_SSUSB_XHCI&gt;;</div><div class='add'>+				clock-names = "sys_ck";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		eth: ethernet@11021000 {</div><div class='add'>+			compatible = "mediatek,mt8188-gmac", "mediatek,mt8195-gmac",</div><div class='add'>+				     "snps,dwmac-5.10a";</div><div class='add'>+			reg = &lt;0 0x11021000 0 0x4000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			interrupt-names = "macirq";</div><div class='add'>+			clocks = &lt;&amp;pericfg_ao CLK_PERI_AO_ETHERNET&gt;,</div><div class='add'>+				 &lt;&amp;pericfg_ao CLK_PERI_AO_ETHERNET_BUS&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SNPS_ETH_250M&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SNPS_ETH_62P4M_PTP&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SNPS_ETH_50M_RMII&gt;,</div><div class='add'>+				 &lt;&amp;pericfg_ao CLK_PERI_AO_ETHERNET_MAC&gt;;</div><div class='add'>+			clock-names = "axi", "apb", "mac_main", "ptp_ref",</div><div class='add'>+				      "rmii_internal", "mac_cg";</div><div class='add'>+			assigned-clocks = &lt;&amp;topckgen CLK_TOP_SNPS_ETH_250M&gt;,</div><div class='add'>+					  &lt;&amp;topckgen CLK_TOP_SNPS_ETH_62P4M_PTP&gt;,</div><div class='add'>+					  &lt;&amp;topckgen CLK_TOP_SNPS_ETH_50M_RMII&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_ETHPLL_D2&gt;,</div><div class='add'>+						 &lt;&amp;topckgen CLK_TOP_ETHPLL_D8&gt;,</div><div class='add'>+						 &lt;&amp;topckgen CLK_TOP_ETHPLL_D10&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_ETHER&gt;;</div><div class='add'>+			mediatek,pericfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+			snps,axi-config = &lt;&amp;stmmac_axi_setup&gt;;</div><div class='add'>+			snps,mtl-rx-config = &lt;&amp;mtl_rx_setup&gt;;</div><div class='add'>+			snps,mtl-tx-config = &lt;&amp;mtl_tx_setup&gt;;</div><div class='add'>+			snps,txpbl = &lt;16&gt;;</div><div class='add'>+			snps,rxpbl = &lt;16&gt;;</div><div class='add'>+			snps,clk-csr = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			eth_mdio: mdio {</div><div class='add'>+				compatible = "snps,dwmac-mdio";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			stmmac_axi_setup: stmmac-axi-config {</div><div class='add'>+				snps,blen = &lt;0 0 0 0 16 8 4&gt;;</div><div class='add'>+				snps,rd_osr_lmt = &lt;0x7&gt;;</div><div class='add'>+				snps,wr_osr_lmt = &lt;0x7&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mtl_rx_setup: rx-queues-config {</div><div class='add'>+				snps,rx-queues-to-use = &lt;4&gt;;</div><div class='add'>+				snps,rx-sched-sp;</div><div class='add'>+</div><div class='add'>+				queue0 {</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+					snps,map-to-dma-channel = &lt;0x0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				queue1 {</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+					snps,map-to-dma-channel = &lt;0x0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				queue2 {</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+					snps,map-to-dma-channel = &lt;0x0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				queue3 {</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+					snps,map-to-dma-channel = &lt;0x0&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mtl_tx_setup: tx-queues-config {</div><div class='add'>+				snps,tx-queues-to-use = &lt;4&gt;;</div><div class='add'>+				snps,tx-sched-wrr;</div><div class='add'>+</div><div class='add'>+				queue0 {</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+					snps,priority = &lt;0x0&gt;;</div><div class='add'>+					snps,weight = &lt;0x10&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				queue1 {</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+					snps,priority = &lt;0x1&gt;;</div><div class='add'>+					snps,weight = &lt;0x11&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				queue2 {</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+					snps,priority = &lt;0x2&gt;;</div><div class='add'>+					snps,weight = &lt;0x12&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				queue3 {</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+					snps,priority = &lt;0x3&gt;;</div><div class='add'>+					snps,weight = &lt;0x13&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmc0: mmc@11230000 {</div><div class='add'>+			compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc";</div><div class='add'>+			reg = &lt;0 0x11230000 0 0x10000&gt;,</div><div class='add'>+			      &lt;0 0x11f50000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_MSDC50_0&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_MSDC0&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_MSDC0_SRC&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_RG_AES_MSDCFDE_CK_0P&gt;;</div><div class='add'>+			clock-names = "source", "hclk", "source_cg", "crypto_clk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmc1: mmc@11240000 {</div><div class='add'>+			compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc";</div><div class='add'>+			reg = &lt;0 0x11240000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11eb0000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_MSDC30_1&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_MSDC1&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_MSDC1_SRC&gt;;</div><div class='add'>+			clock-names = "source", "hclk", "source_cg";</div><div class='add'>+			assigned-clocks = &lt;&amp;topckgen CLK_TOP_MSDC30_1&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_MSDCPLL_D2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmc2: mmc@11250000 {</div><div class='add'>+			compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc";</div><div class='add'>+			reg = &lt;0 0x11250000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11e60000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_MSDC30_2&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_MSDC2&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_MSDC30_2&gt;;</div><div class='add'>+			clock-names = "source", "hclk", "source_cg";</div><div class='add'>+			assigned-clocks = &lt;&amp;topckgen CLK_TOP_MSDC30_2&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_MSDCPLL_D2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		lvts_mcu: thermal-sensor@11278000 {</div><div class='add'>+			compatible = "mediatek,mt8188-lvts-mcu";</div><div class='add'>+			reg = &lt;0 0x11278000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg_ao CLK_INFRA_AO_THERM&gt;;</div><div class='add'>+			resets = &lt;&amp;infracfg_ao MT8188_INFRA_RST1_THERMAL_MCU_RST&gt;;</div><div class='add'>+			nvmem-cells = &lt;&amp;lvts_efuse_data1&gt;;</div><div class='add'>+			nvmem-cell-names = "lvts-calib-data-1";</div><div class='add'>+			#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c0: i2c@11280000 {</div><div class='add'>+			compatible = "mediatek,mt8188-i2c";</div><div class='add'>+			reg = &lt;0 0x11280000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x10220080 0 0x80&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clock-div = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;imp_iic_wrap_c CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C0&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_APDMA_BCLK&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c2: i2c@11281000 {</div><div class='add'>+			compatible = "mediatek,mt8188-i2c";</div><div class='add'>+			reg = &lt;0 0x11281000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x10220180 0 0x80&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clock-div = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;imp_iic_wrap_c CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C2&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_APDMA_BCLK&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c3: i2c@11282000 {</div><div class='add'>+			compatible = "mediatek,mt8188-i2c";</div><div class='add'>+			reg = &lt;0 0x11282000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x10220280 0 0x80&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clock-div = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;imp_iic_wrap_c CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C3&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_APDMA_BCLK&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		imp_iic_wrap_c: clock-controller@11283000 {</div><div class='add'>+			compatible = "mediatek,mt8188-imp-iic-wrap-c";</div><div class='add'>+			reg = &lt;0 0x11283000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ssusb2: usb@112a1000 {</div><div class='add'>+			compatible = "mediatek,mt8188-mtu3", "mediatek,mtu3";</div><div class='add'>+			reg = &lt;0 0x112a1000 0 0x2dff&gt;, &lt;0 0x112a3e00 0 0x0100&gt;;</div><div class='add'>+			reg-names = "mac", "ippc";</div><div class='add'>+			ranges = &lt;0 0 0 0x112a0000 0 0x3f00&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			assigned-clocks = &lt;&amp;topckgen CLK_TOP_USB_TOP_3P&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_UNIVPLL_D5_D4&gt;;</div><div class='add'>+			clocks = &lt;&amp;pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SSUSB_TOP_P3_REF&gt;,</div><div class='add'>+				 &lt;&amp;pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI&gt;;</div><div class='add'>+			clock-names = "sys_ck", "ref_ck", "mcu_ck";</div><div class='add'>+			phys = &lt;&amp;u2port2 PHY_TYPE_USB2&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+			mediatek,syscon-wakeup = &lt;&amp;pericfg 0x470 2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			xhci2: usb@0 {</div><div class='add'>+				compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";</div><div class='add'>+				reg = &lt;0 0 0 0x1000&gt;;</div><div class='add'>+				reg-names = "mac";</div><div class='add'>+				interrupts = &lt;GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				assigned-clocks = &lt;&amp;topckgen CLK_TOP_SSUSB_XHCI_3P&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_UNIVPLL_D5_D4&gt;;</div><div class='add'>+				clocks = &lt;&amp;pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI&gt;;</div><div class='add'>+				clock-names = "sys_ck";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ssusb0: usb@112b1000 {</div><div class='add'>+			compatible = "mediatek,mt8188-mtu3", "mediatek,mtu3";</div><div class='add'>+			reg = &lt;0 0x112b1000 0 0x2dff&gt;, &lt;0 0x112b3e00 0 0x0100&gt;;</div><div class='add'>+			reg-names = "mac", "ippc";</div><div class='add'>+			ranges = &lt;0 0 0 0x112b0000 0 0x3f00&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			assigned-clocks = &lt;&amp;topckgen CLK_TOP_SSUSB_XHCI_2P&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_UNIVPLL_D5_D4&gt;;</div><div class='add'>+			clocks = &lt;&amp;pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SSUSB_TOP_P2_REF&gt;,</div><div class='add'>+				 &lt;&amp;pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI&gt;;</div><div class='add'>+			clock-names = "sys_ck", "ref_ck", "mcu_ck";</div><div class='add'>+			phys = &lt;&amp;u2port0 PHY_TYPE_USB2&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+			mediatek,syscon-wakeup = &lt;&amp;pericfg 0x460 2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			xhci0: usb@0 {</div><div class='add'>+				compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";</div><div class='add'>+				reg = &lt;0 0 0 0x1000&gt;;</div><div class='add'>+				reg-names = "mac";</div><div class='add'>+				interrupts = &lt;GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				assigned-clocks = &lt;&amp;topckgen CLK_TOP_USB_TOP_2P&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_UNIVPLL_D5_D4&gt;;</div><div class='add'>+				clocks = &lt;&amp;pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI&gt;;</div><div class='add'>+				clock-names = "sys_ck";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie: pcie@112f0000 {</div><div class='add'>+			compatible = "mediatek,mt8188-pcie", "mediatek,mt8192-pcie";</div><div class='add'>+			reg = &lt;0 0x112f0000 0 0x2000&gt;;</div><div class='add'>+			reg-names = "pcie-mac";</div><div class='add'>+			ranges = &lt;0x82000000 0 0x20000000 0 0x20000000 0 0x4000000&gt;;</div><div class='add'>+			bus-range = &lt;0 0xff&gt;;</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			linux,pci-domain = &lt;0&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_PCIE_TL_26M&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_PCIE_TL_96M&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_PCIE_TL_32K&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M&gt;,</div><div class='add'>+				 &lt;&amp;pericfg_ao CLK_PERI_AO_PCIE_P0_FMEM&gt;;</div><div class='add'>+			clock-names = "pl_250m", "tl_26m", "tl_96m", "tl_32k",</div><div class='add'>+				      "peri_26m", "peri_mem";</div><div class='add'>+</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;pcie_intc 0&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;pcie_intc 1&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;pcie_intc 2&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;pcie_intc 3&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='add'>+</div><div class='add'>+			iommu-map = &lt;0 &amp;infra_iommu IFR_IOMMU_PORT_PCIE_0 0xffff&gt;;</div><div class='add'>+			iommu-map-mask = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;pcieport PHY_TYPE_PCIE&gt;;</div><div class='add'>+			phy-names = "pcie-phy";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_PEXTP_MAC_P0&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;watchdog MT8188_TOPRGU_PCIE_SW_RST&gt;;</div><div class='add'>+			reset-names = "mac";</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcie_intc: interrupt-controller {</div><div class='add'>+				#address-cells = &lt;0&gt;;</div><div class='add'>+				#interrupt-cells = &lt;1&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nor_flash: spi@1132c000 {</div><div class='add'>+			compatible = "mediatek,mt8188-nor", "mediatek,mt8186-nor";</div><div class='add'>+			reg = &lt;0 0x1132c000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_SPINOR&gt;,</div><div class='add'>+				 &lt;&amp;pericfg_ao CLK_PERI_AO_FLASHIFLASHCK&gt;,</div><div class='add'>+				 &lt;&amp;pericfg_ao CLK_PERI_AO_FLASHIF_BUS&gt;;</div><div class='add'>+			clock-names = "spi", "sf", "axi";</div><div class='add'>+			assigned-clocks = &lt;&amp;topckgen CLK_TOP_SPINOR&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pciephy: t-phy@11c20700 {</div><div class='add'>+			compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3";</div><div class='add'>+			ranges = &lt;0 0 0x11c20700 0x700&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_PEXTP_PHY_TOP&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcieport: pcie-phy@0 {</div><div class='add'>+				reg = &lt;0 0x700&gt;;</div><div class='add'>+				clocks = &lt;&amp;topckgen CLK_TOP_CFGREG_F_PCIE_PHY_REF&gt;;</div><div class='add'>+				clock-names = "ref";</div><div class='add'>+				#phy-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mipi_tx_config0: dsi-phy@11c80000 {</div><div class='add'>+			compatible = "mediatek,mt8188-mipi-tx", "mediatek,mt8183-mipi-tx";</div><div class='add'>+			reg = &lt;0 0x11c80000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk26m&gt;;</div><div class='add'>+			clock-output-names = "mipi_tx0_pll";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mipi_tx_config1: dsi-phy@11c90000 {</div><div class='add'>+			compatible = "mediatek,mt8188-mipi-tx", "mediatek,mt8183-mipi-tx";</div><div class='add'>+			reg = &lt;0 0x11c90000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk26m&gt;;</div><div class='add'>+			clock-output-names = "mipi_tx0_pll";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c1: i2c@11e00000 {</div><div class='add'>+			compatible = "mediatek,mt8188-i2c";</div><div class='add'>+			reg = &lt;0 0x11e00000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x10220100 0 0x80&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clock-div = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_AP_CLOCK_I2C1&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_APDMA_BCLK&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c4: i2c@11e01000 {</div><div class='add'>+			compatible = "mediatek,mt8188-i2c";</div><div class='add'>+			reg = &lt;0 0x11e01000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x10220380 0 0x80&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clock-div = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_AP_CLOCK_I2C4&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_APDMA_BCLK&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		imp_iic_wrap_w: clock-controller@11e02000 {</div><div class='add'>+			compatible = "mediatek,mt8188-imp-iic-wrap-w";</div><div class='add'>+			reg = &lt;0 0x11e02000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		u3phy0: t-phy@11e30000 {</div><div class='add'>+			compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges = &lt;0x0 0x0 0x11e30000 0x1000&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			u2port0: usb-phy@0 {</div><div class='add'>+				reg = &lt;0x0 0x700&gt;;</div><div class='add'>+				clocks = &lt;&amp;topckgen CLK_TOP_SSUSB_PHY_P2_REF&gt;,</div><div class='add'>+					 &lt;&amp;apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN&gt;;</div><div class='add'>+				clock-names = "ref", "da_ref";</div><div class='add'>+				#phy-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		u3phy1: t-phy@11e40000 {</div><div class='add'>+			compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges = &lt;0x0 0x0 0x11e40000 0x1000&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			u2port1: usb-phy@0 {</div><div class='add'>+				reg = &lt;0x0 0x700&gt;;</div><div class='add'>+				clocks = &lt;&amp;topckgen CLK_TOP_SSUSB_PHY_REF&gt;,</div><div class='add'>+					 &lt;&amp;apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN&gt;;</div><div class='add'>+				clock-names = "ref", "da_ref";</div><div class='add'>+				#phy-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			u3port1: usb-phy@700 {</div><div class='add'>+				reg = &lt;0x700 0x700&gt;;</div><div class='add'>+				clocks = &lt;&amp;apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN&gt;,</div><div class='add'>+					 &lt;&amp;clk26m&gt;;</div><div class='add'>+				clock-names = "ref", "da_ref";</div><div class='add'>+				#phy-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		u3phy2: t-phy@11e80000 {</div><div class='add'>+			compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges = &lt;0x0 0x0 0x11e80000 0x1000&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			u2port2: usb-phy@0 {</div><div class='add'>+				reg = &lt;0x0 0x700&gt;;</div><div class='add'>+				clocks = &lt;&amp;topckgen CLK_TOP_SSUSB_PHY_P3_REF&gt;,</div><div class='add'>+					 &lt;&amp;apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN&gt;;</div><div class='add'>+				clock-names = "ref", "da_ref";</div><div class='add'>+				#phy-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c5: i2c@11ec0000 {</div><div class='add'>+			compatible = "mediatek,mt8188-i2c";</div><div class='add'>+			reg = &lt;0 0x11ec0000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x10220480 0 0x80&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clock-div = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;imp_iic_wrap_en CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C5&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_APDMA_BCLK&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c6: i2c@11ec1000 {</div><div class='add'>+			compatible = "mediatek,mt8188-i2c";</div><div class='add'>+			reg = &lt;0 0x11ec1000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x10220600 0 0x80&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clock-div = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;imp_iic_wrap_en CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C6&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_APDMA_BCLK&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		imp_iic_wrap_en: clock-controller@11ec2000 {</div><div class='add'>+			compatible = "mediatek,mt8188-imp-iic-wrap-en";</div><div class='add'>+			reg = &lt;0 0x11ec2000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		efuse: efuse@11f20000 {</div><div class='add'>+			compatible = "mediatek,mt8188-efuse", "mediatek,mt8186-efuse";</div><div class='add'>+			reg = &lt;0 0x11f20000 0 0x1000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			dp_calib_data: dp-calib@1a0 {</div><div class='add'>+				reg = &lt;0x1a0 0xc&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lvts_efuse_data1: lvts1-calib@1ac {</div><div class='add'>+				reg = &lt;0x1ac 0x40&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gpu_speedbin: gpu-speedbin@581 {</div><div class='add'>+				reg = &lt;0x581 0x1&gt;;</div><div class='add'>+				bits = &lt;0 3&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			socinfo-data1@7a0 {</div><div class='add'>+				reg = &lt;0x7a0 0x4&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			socinfo-data2@7e0 {</div><div class='add'>+				reg = &lt;0x7e0 0x4&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu: gpu@13000000 {</div><div class='add'>+			compatible = "mediatek,mt8188-mali", "arm,mali-valhall-jm";</div><div class='add'>+			reg = &lt;0 0x13000000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;mfgcfg CLK_MFGCFG_BG3D&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+				     &lt;GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+				     &lt;GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			interrupt-names = "job", "mmu", "gpu";</div><div class='add'>+			nvmem-cells = &lt;&amp;gpu_speedbin&gt;;</div><div class='add'>+			nvmem-cell-names = "speed-bin";</div><div class='add'>+			operating-points-v2 = &lt;&amp;gpu_opp_table&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_MFG2&gt;,</div><div class='add'>+					&lt;&amp;spm MT8188_POWER_DOMAIN_MFG3&gt;,</div><div class='add'>+					&lt;&amp;spm MT8188_POWER_DOMAIN_MFG4&gt;;</div><div class='add'>+			power-domain-names = "core0", "core1", "core2";</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mfgcfg: clock-controller@13fbf000 {</div><div class='add'>+			compatible = "mediatek,mt8188-mfgcfg";</div><div class='add'>+			reg = &lt;0 0x13fbf000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vppsys0: syscon@14000000 {</div><div class='add'>+			compatible = "mediatek,mt8188-vppsys0", "syscon";</div><div class='add'>+			reg = &lt;0 0x14000000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dma-controller@14001000 {</div><div class='add'>+			compatible = "mediatek,mt8188-mdp3-rdma";</div><div class='add'>+			reg = &lt;0 0x14001000 0 0x1000&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys0 CLK_VPP0_MDP_RDMA&gt;;</div><div class='add'>+			mboxes = &lt;&amp;gce0 13 CMDQ_THR_PRIO_1&gt;,</div><div class='add'>+				 &lt;&amp;gce0 14 CMDQ_THR_PRIO_1&gt;,</div><div class='add'>+				 &lt;&amp;gce0 16 CMDQ_THR_PRIO_1&gt;,</div><div class='add'>+				 &lt;&amp;gce0 21 CMDQ_THR_PRIO_1&gt;,</div><div class='add'>+				 &lt;&amp;gce0 22 CMDQ_THR_PRIO_1&gt;;</div><div class='add'>+			iommus = &lt;&amp;vpp_iommu M4U_PORT_L4_MDP_RDMA&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VPPSYS0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_1400XXXX 0x1000 0x1000&gt;;</div><div class='add'>+			mediatek,gce-events = &lt;CMDQ_EVENT_VPP0_MDP_RDMA_SOF&gt;,</div><div class='add'>+					      &lt;CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE&gt;;</div><div class='add'>+			mediatek,scp = &lt;&amp;scp_c0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14002000 {</div><div class='add'>+			compatible = "mediatek,mt8188-mdp3-fg", "mediatek,mt8195-mdp3-fg";</div><div class='add'>+			reg = &lt;0 0x14002000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys0 CLK_VPP0_MDP_FG&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_1400XXXX 0x2000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14004000 {</div><div class='add'>+			compatible = "mediatek,mt8188-mdp3-hdr", "mediatek,mt8195-mdp3-hdr";</div><div class='add'>+			reg = &lt;0 0x14004000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys0 CLK_VPP0_MDP_HDR&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_1400XXXX 0x4000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14005000 {</div><div class='add'>+			compatible = "mediatek,mt8188-mdp3-aal", "mediatek,mt8195-mdp3-aal";</div><div class='add'>+			reg = &lt;0 0x14005000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys0 CLK_VPP0_MDP_AAL&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VPPSYS0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_1400XXXX 0x5000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14006000 {</div><div class='add'>+			compatible = "mediatek,mt8188-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";</div><div class='add'>+			reg = &lt;0 0x14006000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys0 CLK_VPP0_MDP_RSZ&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_1400XXXX 0x6000 0x1000&gt;;</div><div class='add'>+			mediatek,gce-events = &lt;CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF&gt;,</div><div class='add'>+					      &lt;CMDQ_EVENT_VPP0_MDP_RSZ_FRAME_DONE&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14007000 {</div><div class='add'>+			compatible = "mediatek,mt8188-mdp3-tdshp", "mediatek,mt8195-mdp3-tdshp";</div><div class='add'>+			reg = &lt;0 0x14007000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys0 CLK_VPP0_MDP_TDSHP&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_1400XXXX 0x7000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14008000 {</div><div class='add'>+			compatible = "mediatek,mt8188-mdp3-color", "mediatek,mt8195-mdp3-color";</div><div class='add'>+			reg = &lt;0 0x14008000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys0 CLK_VPP0_MDP_COLOR&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VPPSYS0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_1400XXXX 0x8000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14009000 {</div><div class='add'>+			compatible = "mediatek,mt8188-mdp3-ovl", "mediatek,mt8195-mdp3-ovl";</div><div class='add'>+			reg = &lt;0 0x14009000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys0 CLK_VPP0_MDP_OVL&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VPPSYS0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_1400XXXX 0x9000 0x1000&gt;;</div><div class='add'>+			iommus = &lt;&amp;vpp_iommu M4U_PORT_L4_MDP_OVL&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@1400a000 {</div><div class='add'>+			compatible = "mediatek,mt8188-mdp3-padding", "mediatek,mt8195-mdp3-padding";</div><div class='add'>+			reg = &lt;0 0x1400a000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys0 CLK_VPP0_PADDING&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VPPSYS0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_1400XXXX 0xa000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@1400b000 {</div><div class='add'>+			compatible = "mediatek,mt8188-mdp3-tcc", "mediatek,mt8195-mdp3-tcc";</div><div class='add'>+			reg = &lt;0 0x1400b000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys0 CLK_VPP0_MDP_TCC&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_1400XXXX 0xb000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@1400c000 {</div><div class='add'>+			compatible = "mediatek,mt8188-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";</div><div class='add'>+			reg = &lt;0 0x1400c000 0 0x1000&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys0 CLK_VPP0_MDP_WROT&gt;;</div><div class='add'>+			iommus = &lt;&amp;vpp_iommu M4U_PORT_L4_MDP_WROT&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VPPSYS0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_1400XXXX 0xc000 0x1000&gt;;</div><div class='add'>+			mediatek,gce-events = &lt;CMDQ_EVENT_VPP0_MDP_WROT_SOF&gt;,</div><div class='add'>+					      &lt;CMDQ_EVENT_VPP0_MDP_WROT_VIDO_WDONE&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mutex@1400f000 {</div><div class='add'>+			compatible = "mediatek,mt8188-vpp-mutex";</div><div class='add'>+			reg = &lt;0 0x1400f000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys0 CLK_VPP0_MUTEX&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VPPSYS0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_1400XXXX 0xf000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vpp_smi_common: smi@14012000 {</div><div class='add'>+			compatible = "mediatek,mt8188-smi-common-vpp";</div><div class='add'>+			reg = &lt;0 0x14012000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys0 CLK_VPP0_SMI_COMMON_LARB4&gt;,</div><div class='add'>+				 &lt;&amp;vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VPPSYS0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb4: smi@14013000 {</div><div class='add'>+			compatible = "mediatek,mt8188-smi-larb";</div><div class='add'>+			reg = &lt;0 0x14013000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys0 CLK_VPP0_SMI_COMMON_LARB4&gt;,</div><div class='add'>+				 &lt;&amp;vppsys0 CLK_VPP0_SMI_COMMON_LARB4&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VPPSYS0&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;SMI_L4_ID&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;vpp_smi_common&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vpp_iommu: iommu@14018000 {</div><div class='add'>+			compatible = "mediatek,mt8188-iommu-vpp";</div><div class='add'>+			reg = &lt;0 0x14018000 0 0x5000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys0 CLK_VPP0_SMI_IOMMU&gt;;</div><div class='add'>+			clock-names = "bclk";</div><div class='add'>+			interrupts = &lt;GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VPPSYS0&gt;;</div><div class='add'>+			#iommu-cells = &lt;1&gt;;</div><div class='add'>+			mediatek,larbs = &lt;&amp;larb1 &amp;larb3 &amp;larb4 &amp;larb6 &amp;larb7 &amp;larb23&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dma-controller@14f09000 {</div><div class='add'>+			compatible = "mediatek,mt8188-mdp3-rdma";</div><div class='add'>+			reg = &lt;0 0x14f09000 0 0x1000&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP2_MDP_RDMA&gt;;</div><div class='add'>+			iommus = &lt;&amp;vdo_iommu M4U_PORT_L5_SVPP2_MDP_RDMA&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VPPSYS1&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f0XXXX 0x9000 0x1000&gt;;</div><div class='add'>+			mediatek,gce-events = &lt;CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_SOF&gt;,</div><div class='add'>+					      &lt;CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_FRAME_DONE&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dma-controller@14f0a000 {</div><div class='add'>+			compatible = "mediatek,mt8188-mdp3-rdma";</div><div class='add'>+			reg = &lt;0 0x14f0a000 0 0x1000&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP3_MDP_RDMA&gt;;</div><div class='add'>+			iommus = &lt;&amp;vpp_iommu M4U_PORT_L6_SVPP3_MDP_RDMA&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VPPSYS1&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f0XXXX 0xa000 0x1000&gt;;</div><div class='add'>+			mediatek,gce-events = &lt;CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_SOF&gt;,</div><div class='add'>+					      &lt;CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_FRAME_DONE&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14f0c000 {</div><div class='add'>+			compatible = "mediatek,mt8188-mdp3-fg", "mediatek,mt8195-mdp3-fg";</div><div class='add'>+			reg = &lt;0 0x14f0c000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP2_MDP_FG&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f0XXXX 0xc000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14f0d000 {</div><div class='add'>+			compatible = "mediatek,mt8188-mdp3-fg", "mediatek,mt8195-mdp3-fg";</div><div class='add'>+			reg = &lt;0 0x14f0d000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP3_MDP_FG&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f0XXXX 0xd000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14f0f000 {</div><div class='add'>+			compatible = "mediatek,mt8188-mdp3-hdr", "mediatek,mt8195-mdp3-hdr";</div><div class='add'>+			reg = &lt;0 0x14f0f000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP2_MDP_HDR&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f0XXXX 0xf000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14f10000 {</div><div class='add'>+			compatible = "mediatek,mt8188-mdp3-hdr", "mediatek,mt8195-mdp3-hdr";</div><div class='add'>+			reg = &lt;0 0x14f10000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP3_MDP_HDR&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f1XXXX 0 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14f12000 {</div><div class='add'>+			compatible = "mediatek,mt8188-mdp3-aal", "mediatek,mt8195-mdp3-aal";</div><div class='add'>+			reg = &lt;0 0x14f12000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP2_MDP_AAL&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VPPSYS1&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f1XXXX 0x2000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14f13000 {</div><div class='add'>+			compatible = "mediatek,mt8188-mdp3-aal", "mediatek,mt8195-mdp3-aal";</div><div class='add'>+			reg = &lt;0 0x14f13000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP3_MDP_AAL&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VPPSYS1&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f1XXXX 0x3000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14f15000 {</div><div class='add'>+			compatible = "mediatek,mt8188-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";</div><div class='add'>+			reg = &lt;0 0x14f15000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP2_MDP_RSZ&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f1XXXX 0x5000 0x1000&gt;;</div><div class='add'>+			mediatek,gce-events = &lt;CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_SOF&gt;,</div><div class='add'>+					      &lt;CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_FRAME_DONE&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14f16000 {</div><div class='add'>+			compatible = "mediatek,mt8188-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";</div><div class='add'>+			reg = &lt;0 0x14f16000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP3_MDP_RSZ&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f1XXXX 0x6000 0x1000&gt;;</div><div class='add'>+			mediatek,gce-events = &lt;CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_SOF&gt;,</div><div class='add'>+					      &lt;CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_FRAME_DONE&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14f18000 {</div><div class='add'>+			compatible = "mediatek,mt8188-mdp3-tdshp", "mediatek,mt8195-mdp3-tdshp";</div><div class='add'>+			reg = &lt;0 0x14f18000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP2_MDP_TDSHP&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f1XXXX 0x8000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14f19000 {</div><div class='add'>+			compatible = "mediatek,mt8188-mdp3-tdshp", "mediatek,mt8195-mdp3-tdshp";</div><div class='add'>+			reg = &lt;0 0x14f19000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP3_MDP_TDSHP&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f1XXXX 0x9000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14f1a000 {</div><div class='add'>+			compatible = "mediatek,mt8188-mdp3-merge", "mediatek,mt8195-mdp3-merge";</div><div class='add'>+			reg = &lt;0 0x14f1a000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP2_VPP_MERGE&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VPPSYS1&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f1XXXX 0xa000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14f1b000 {</div><div class='add'>+			compatible = "mediatek,mt8188-mdp3-merge", "mediatek,mt8195-mdp3-merge";</div><div class='add'>+			reg = &lt;0 0x14f1b000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP3_VPP_MERGE&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VPPSYS1&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f1XXXX 0xb000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14f1d000 {</div><div class='add'>+			compatible = "mediatek,mt8188-mdp3-color", "mediatek,mt8195-mdp3-color";</div><div class='add'>+			reg = &lt;0 0x14f1d000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 629 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP2_MDP_COLOR&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VPPSYS1&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f1XXXX 0xd000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14f1e000 {</div><div class='add'>+			compatible = "mediatek,mt8188-mdp3-color", "mediatek,mt8195-mdp3-color";</div><div class='add'>+			reg = &lt;0 0x14f1e000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP3_MDP_COLOR&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VPPSYS1&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f1XXXX 0xe000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14f21000 {</div><div class='add'>+			compatible = "mediatek,mt8188-mdp3-padding",</div><div class='add'>+				     "mediatek,mt8195-mdp3-padding";</div><div class='add'>+			reg = &lt;0 0x14f21000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP2_VPP_PAD&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VPPSYS1&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f2XXXX 0x1000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14f22000 {</div><div class='add'>+			compatible = "mediatek,mt8188-mdp3-padding",</div><div class='add'>+				     "mediatek,mt8195-mdp3-padding";</div><div class='add'>+			reg = &lt;0 0x14f22000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP3_VPP_PAD&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VPPSYS1&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f2XXXX 0x2000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14f24000 {</div><div class='add'>+			compatible = "mediatek,mt8188-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";</div><div class='add'>+			reg = &lt;0 0x14f24000 0 0x1000&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP2_MDP_WROT&gt;;</div><div class='add'>+			iommus = &lt;&amp;vdo_iommu M4U_PORT_L5_SVPP2_MDP_WROT&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VPPSYS1&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f2XXXX 0x4000 0x1000&gt;;</div><div class='add'>+			mediatek,gce-events = &lt;CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SOF&gt;,</div><div class='add'>+					      &lt;CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_FRAME_DONE&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14f25000 {</div><div class='add'>+			compatible = "mediatek,mt8188-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";</div><div class='add'>+			reg = &lt;0 0x14f25000 0 0x1000&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP3_MDP_WROT&gt;;</div><div class='add'>+			iommus = &lt;&amp;vpp_iommu M4U_PORT_L6_SVPP3_MDP_WROT&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VPPSYS1&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f2XXXX 0x5000 0x1000&gt;;</div><div class='add'>+			mediatek,gce-events = &lt;CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SOF&gt;,</div><div class='add'>+					      &lt;CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_FRAME_DONE&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wpesys: clock-controller@14e00000 {</div><div class='add'>+			compatible = "mediatek,mt8188-wpesys";</div><div class='add'>+			reg = &lt;0 0x14e00000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wpesys_vpp0: clock-controller@14e02000 {</div><div class='add'>+			compatible = "mediatek,mt8188-wpesys-vpp0";</div><div class='add'>+			reg = &lt;0 0x14e02000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb7: smi@14e04000 {</div><div class='add'>+			compatible = "mediatek,mt8188-smi-larb";</div><div class='add'>+			reg = &lt;0 0x14e04000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;wpesys CLK_WPE_TOP_SMI_LARB7&gt;,</div><div class='add'>+				 &lt;&amp;wpesys CLK_WPE_TOP_SMI_LARB7&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_WPE&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;SMI_L7_ID&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;vpp_smi_common&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vppsys1: syscon@14f00000 {</div><div class='add'>+			compatible = "mediatek,mt8188-vppsys1", "syscon";</div><div class='add'>+			reg = &lt;0 0x14f00000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mutex@14f01000 {</div><div class='add'>+			compatible = "mediatek,mt8188-vpp-mutex";</div><div class='add'>+			reg = &lt;0 0x14f01000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_DISP_MUTEX&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VPPSYS1&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f0XXXX 0x1000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb5: smi@14f02000 {</div><div class='add'>+			compatible = "mediatek,mt8188-smi-larb";</div><div class='add'>+			reg = &lt;0 0x14f02000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_GALS5&gt;,</div><div class='add'>+				 &lt;&amp;vppsys1 CLK_VPP1_LARB5&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VPPSYS1&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;SMI_L5_ID&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;vdo_smi_common&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb6: smi@14f03000 {</div><div class='add'>+			compatible = "mediatek,mt8188-smi-larb";</div><div class='add'>+			reg = &lt;0 0x14f03000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_GALS6&gt;,</div><div class='add'>+				 &lt;&amp;vppsys1 CLK_VPP1_LARB6&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VPPSYS1&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;SMI_L6_ID&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;vpp_smi_common&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		imgsys: clock-controller@15000000 {</div><div class='add'>+			compatible = "mediatek,mt8188-imgsys";</div><div class='add'>+			reg = &lt;0 0x15000000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		imgsys1_dip_top: clock-controller@15110000 {</div><div class='add'>+			compatible = "mediatek,mt8188-imgsys1-dip-top";</div><div class='add'>+			reg = &lt;0 0x15110000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		imgsys1_dip_nr: clock-controller@15130000 {</div><div class='add'>+			compatible = "mediatek,mt8188-imgsys1-dip-nr";</div><div class='add'>+			reg = &lt;0 0x15130000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		imgsys_wpe1: clock-controller@15220000 {</div><div class='add'>+			compatible = "mediatek,mt8188-imgsys-wpe1";</div><div class='add'>+			reg = &lt;0 0x15220000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ipesys: clock-controller@15330000 {</div><div class='add'>+			compatible = "mediatek,mt8188-ipesys";</div><div class='add'>+			reg = &lt;0 0x15330000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		imgsys_wpe2: clock-controller@15520000 {</div><div class='add'>+			compatible = "mediatek,mt8188-imgsys-wpe2";</div><div class='add'>+			reg = &lt;0 0x15520000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		imgsys_wpe3: clock-controller@15620000 {</div><div class='add'>+			compatible = "mediatek,mt8188-imgsys-wpe3";</div><div class='add'>+			reg = &lt;0 0x15620000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		camsys: clock-controller@16000000 {</div><div class='add'>+			compatible = "mediatek,mt8188-camsys";</div><div class='add'>+			reg = &lt;0 0x16000000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		camsys_rawa: clock-controller@1604f000 {</div><div class='add'>+			compatible = "mediatek,mt8188-camsys-rawa";</div><div class='add'>+			reg = &lt;0 0x1604f000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		camsys_yuva: clock-controller@1606f000 {</div><div class='add'>+			compatible = "mediatek,mt8188-camsys-yuva";</div><div class='add'>+			reg = &lt;0 0x1606f000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		camsys_rawb: clock-controller@1608f000 {</div><div class='add'>+			compatible = "mediatek,mt8188-camsys-rawb";</div><div class='add'>+			reg = &lt;0 0x1608f000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		camsys_yuvb: clock-controller@160af000 {</div><div class='add'>+			compatible = "mediatek,mt8188-camsys-yuvb";</div><div class='add'>+			reg = &lt;0 0x160af000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ccusys: clock-controller@17200000 {</div><div class='add'>+			compatible = "mediatek,mt8188-ccusys";</div><div class='add'>+			reg = &lt;0 0x17200000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		video_decoder: video-decoder@18000000 {</div><div class='add'>+			compatible = "mediatek,mt8188-vcodec-dec";</div><div class='add'>+			reg = &lt;0 0x18000000 0 0x1000&gt;, &lt;0 0x18004000 0 0x1000&gt;;</div><div class='add'>+			ranges = &lt;0 0 0 0x18000000 0 0x26000&gt;;</div><div class='add'>+			iommus = &lt;&amp;vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			mediatek,scp = &lt;&amp;scp_c0&gt;;</div><div class='add'>+</div><div class='add'>+			video-codec@10000 {</div><div class='add'>+				compatible = "mediatek,mtk-vcodec-lat";</div><div class='add'>+				reg = &lt;0 0x10000 0 0x800&gt;;</div><div class='add'>+				assigned-clocks = &lt;&amp;topckgen CLK_TOP_VDEC&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_UNIVPLL_D6&gt;;</div><div class='add'>+				clocks = &lt;&amp;topckgen CLK_TOP_VDEC&gt;,</div><div class='add'>+					 &lt;&amp;vdecsys_soc CLK_VDEC1_SOC_VDEC&gt;,</div><div class='add'>+					 &lt;&amp;vdecsys_soc CLK_VDEC1_SOC_LAT&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_UNIVPLL_D6&gt;;</div><div class='add'>+				clock-names = "sel", "vdec", "lat", "top";</div><div class='add'>+				interrupts = &lt;GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				iommus = &lt;&amp;vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_VLD_EXT&gt;,</div><div class='add'>+					 &lt;&amp;vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_VLD2_EXT&gt;,</div><div class='add'>+					 &lt;&amp;vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_AVC_MV_EXT&gt;,</div><div class='add'>+					 &lt;&amp;vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_PRED_RD_EXT&gt;,</div><div class='add'>+					 &lt;&amp;vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_TILE_EXT&gt;,</div><div class='add'>+					 &lt;&amp;vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_WDMA_EXT&gt;,</div><div class='add'>+					 &lt;&amp;vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT&gt;,</div><div class='add'>+					 &lt;&amp;vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT_C&gt;,</div><div class='add'>+					 &lt;&amp;vpp_iommu M4U_PORT_L23_HW_VDEC_MC_EXT_C&gt;;</div><div class='add'>+				power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDEC0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			video-codec@25000 {</div><div class='add'>+				compatible = "mediatek,mtk-vcodec-core";</div><div class='add'>+				reg = &lt;0 0x25000 0 0x1000&gt;;</div><div class='add'>+				assigned-clocks = &lt;&amp;topckgen CLK_TOP_VDEC&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_UNIVPLL_D6&gt;;</div><div class='add'>+				clocks = &lt;&amp;topckgen CLK_TOP_VDEC&gt;,</div><div class='add'>+					 &lt;&amp;vdecsys CLK_VDEC2_VDEC&gt;,</div><div class='add'>+					 &lt;&amp;vdecsys CLK_VDEC2_LAT&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_UNIVPLL_D6&gt;;</div><div class='add'>+				clock-names = "sel", "vdec", "lat", "top";</div><div class='add'>+				interrupts = &lt;GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				iommus = &lt;&amp;vdo_iommu M4U_PORT_L21_HW_VDEC_MC_EXT&gt;,</div><div class='add'>+					 &lt;&amp;vdo_iommu M4U_PORT_L21_HW_VDEC_UFO_EXT&gt;,</div><div class='add'>+					 &lt;&amp;vdo_iommu M4U_PORT_L21_HW_VDEC_PP_EXT&gt;,</div><div class='add'>+					 &lt;&amp;vdo_iommu M4U_PORT_L21_HW_VDEC_PRED_RD_EXT&gt;,</div><div class='add'>+					 &lt;&amp;vdo_iommu M4U_PORT_L21_HW_VDEC_PRED_WR_EXT&gt;,</div><div class='add'>+					 &lt;&amp;vdo_iommu M4U_PORT_L21_HW_VDEC_PPWRAP_EXT&gt;,</div><div class='add'>+					 &lt;&amp;vdo_iommu M4U_PORT_L21_HW_VDEC_TILE_EXT&gt;,</div><div class='add'>+					 &lt;&amp;vdo_iommu M4U_PORT_L21_HW_VDEC_VLD_EXT&gt;,</div><div class='add'>+					 &lt;&amp;vdo_iommu M4U_PORT_L21_HW_VDEC_VLD2_EXT&gt;,</div><div class='add'>+					 &lt;&amp;vdo_iommu M4U_PORT_L21_HW_VDEC_AVC_MV_EXT&gt;,</div><div class='add'>+					 &lt;&amp;vdo_iommu M4U_PORT_L21_HW_VDEC_UFO_EXT_C&gt;;</div><div class='add'>+				power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDEC1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb23: smi@1800d000 {</div><div class='add'>+			compatible = "mediatek,mt8188-smi-larb";</div><div class='add'>+			reg = &lt;0 0x1800d000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdecsys_soc CLK_VDEC1_SOC_LARB1&gt;,</div><div class='add'>+				 &lt;&amp;vdecsys_soc CLK_VDEC1_SOC_LARB1&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDEC0&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;SMI_L23_ID&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;vpp_smi_common&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdecsys_soc: clock-controller@1800f000 {</div><div class='add'>+			compatible = "mediatek,mt8188-vdecsys-soc";</div><div class='add'>+			reg = &lt;0 0x1800f000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb21: smi@1802e000 {</div><div class='add'>+			compatible = "mediatek,mt8188-smi-larb";</div><div class='add'>+			reg = &lt;0 0x1802e000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdecsys CLK_VDEC2_LARB1&gt;,</div><div class='add'>+				 &lt;&amp;vdecsys CLK_VDEC2_LARB1&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDEC1&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;SMI_L21_ID&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;vdo_smi_common&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdecsys: clock-controller@1802f000 {</div><div class='add'>+			compatible = "mediatek,mt8188-vdecsys";</div><div class='add'>+			reg = &lt;0 0x1802f000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vencsys: clock-controller@1a000000 {</div><div class='add'>+			compatible = "mediatek,mt8188-vencsys";</div><div class='add'>+			reg = &lt;0 0x1a000000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb19: smi@1a010000 {</div><div class='add'>+			compatible = "mediatek,mt8188-smi-larb";</div><div class='add'>+			reg = &lt;0 0x1a010000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vencsys CLK_VENC1_VENC&gt;,</div><div class='add'>+				 &lt;&amp;vencsys CLK_VENC1_VENC&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VENC&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;SMI_L19_ID&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;vdo_smi_common&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		video_encoder: video-encoder@1a020000 {</div><div class='add'>+			compatible = "mediatek,mt8188-vcodec-enc";</div><div class='add'>+			reg = &lt;0 0x1a020000 0 0x10000&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			assigned-clocks = &lt;&amp;topckgen CLK_TOP_VENC&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_UNIVPLL_D4&gt;;</div><div class='add'>+			clocks = &lt;&amp;vencsys CLK_VENC1_VENC&gt;;</div><div class='add'>+			clock-names = "venc_sel";</div><div class='add'>+			interrupts = &lt;GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			iommus = &lt;&amp;vdo_iommu M4U_PORT_L19_VENC_RCPU&gt;,</div><div class='add'>+				 &lt;&amp;vdo_iommu M4U_PORT_L19_VENC_REC&gt;,</div><div class='add'>+				 &lt;&amp;vdo_iommu M4U_PORT_L19_VENC_BSDMA&gt;,</div><div class='add'>+				 &lt;&amp;vdo_iommu M4U_PORT_L19_VENC_SV_COMV&gt;,</div><div class='add'>+				 &lt;&amp;vdo_iommu M4U_PORT_L19_VENC_RD_COMV&gt;,</div><div class='add'>+				 &lt;&amp;vdo_iommu M4U_PORT_L19_VENC_CUR_LUMA&gt;,</div><div class='add'>+				 &lt;&amp;vdo_iommu M4U_PORT_L19_VENC_CUR_CHROMA&gt;,</div><div class='add'>+				 &lt;&amp;vdo_iommu M4U_PORT_L19_VENC_REF_LUMA&gt;,</div><div class='add'>+				 &lt;&amp;vdo_iommu M4U_PORT_L19_VENC_REF_CHROMA&gt;,</div><div class='add'>+				 &lt;&amp;vdo_iommu M4U_PORT_L19_VENC_SUB_W_LUMA&gt;,</div><div class='add'>+				 &lt;&amp;vdo_iommu M4U_PORT_L19_VENC_SUB_R_LUMA&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VENC&gt;;</div><div class='add'>+			mediatek,scp = &lt;&amp;scp_c0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		jpeg_encoder: jpeg-encoder@1a030000 {</div><div class='add'>+			compatible = "mediatek,mt8188-jpgenc", "mediatek,mtk-jpgenc";</div><div class='add'>+			reg = &lt;0 0x1a030000 0 0x10000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vencsys CLK_VENC1_JPGENC&gt;;</div><div class='add'>+			clock-names = "jpgenc";</div><div class='add'>+			interrupts = &lt;GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			iommus = &lt;&amp;vdo_iommu M4U_PORT_L19_JPGENC_Y_RDMA&gt;,</div><div class='add'>+				 &lt;&amp;vdo_iommu M4U_PORT_L19_JPGENC_C_RDMA&gt;,</div><div class='add'>+				 &lt;&amp;vdo_iommu M4U_PORT_L19_JPGENC_Q_TABLE&gt;,</div><div class='add'>+				 &lt;&amp;vdo_iommu M4U_PORT_L19_JPGENC_BSDMA&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VENC&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		jpeg_decoder: jpeg-decoder@1a040000 {</div><div class='add'>+			compatible = "mediatek,mt8188-jpgdec", "mediatek,mt2701-jpgdec";</div><div class='add'>+			reg = &lt;0 0x1a040000 0 0x10000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vencsys CLK_VENC1_LARB&gt;,</div><div class='add'>+				 &lt;&amp;vencsys CLK_VENC1_JPGDEC&gt;;</div><div class='add'>+			clock-names = "jpgdec-smi", "jpgdec";</div><div class='add'>+			interrupts = &lt;GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			iommus = &lt;&amp;vdo_iommu M4U_PORT_L19_JPGDEC_WDMA_0&gt;,</div><div class='add'>+				 &lt;&amp;vdo_iommu M4U_PORT_L19_JPGDEC_BSDMA_0&gt;,</div><div class='add'>+				 &lt;&amp;vdo_iommu M4U_PORT_L19_JPGDEC_WDMA_1&gt;,</div><div class='add'>+				 &lt;&amp;vdo_iommu M4U_PORT_L19_JPGDEC_BSDMA_1&gt;,</div><div class='add'>+				 &lt;&amp;vdo_iommu M4U_PORT_L19_JPGDEC_HUFF_OFFSET_1&gt;,</div><div class='add'>+				 &lt;&amp;vdo_iommu M4U_PORT_L19_JPGDEC_HUFF_OFFSET_0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDEC0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ovl0: ovl@1c000000 {</div><div class='add'>+			compatible = "mediatek,mt8188-disp-ovl", "mediatek,mt8195-disp-ovl";</div><div class='add'>+			reg = &lt;0 0x1c000000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys0 CLK_VDO0_DISP_OVL0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			iommus = &lt;&amp;vdo_iommu M4U_PORT_L0_DISP_OVL0_RDMA0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDOSYS0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c00XXXX 0x0000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					ovl0_in: endpoint { };</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					ovl0_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;rdma0_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rdma0: rdma@1c002000 {</div><div class='add'>+			compatible = "mediatek,mt8188-disp-rdma", "mediatek,mt8195-disp-rdma";</div><div class='add'>+			reg = &lt;0 0x1c002000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys0 CLK_VDO0_DISP_RDMA0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			iommus = &lt;&amp;vpp_iommu M4U_PORT_L1_DISP_RDMA0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDOSYS0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c00XXXX 0x2000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					rdma0_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ovl0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					rdma0_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;color0_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		color0: color@1c003000 {</div><div class='add'>+			compatible = "mediatek,mt8188-disp-color", "mediatek,mt8173-disp-color";</div><div class='add'>+			reg = &lt;0 0x1c003000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys0 CLK_VDO0_DISP_COLOR0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDOSYS0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c00XXXX 0x3000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					color0_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;rdma0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					color0_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ccorr0_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ccorr0: ccorr@1c004000 {</div><div class='add'>+			compatible = "mediatek,mt8188-disp-ccorr", "mediatek,mt8192-disp-ccorr";</div><div class='add'>+			reg = &lt;0 0x1c004000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys0 CLK_VDO0_DISP_CCORR0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDOSYS0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c00XXXX 0x4000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					ccorr0_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;color0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					ccorr0_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;aal0_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aal0: aal@1c005000 {</div><div class='add'>+			compatible = "mediatek,mt8188-disp-aal", "mediatek,mt8183-disp-aal";</div><div class='add'>+			reg = &lt;0 0x1c005000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys0 CLK_VDO0_DISP_AAL0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDOSYS0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c00XXXX 0x5000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					aal0_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ccorr0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					aal0_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;gamma0_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gamma0: gamma@1c006000 {</div><div class='add'>+			compatible = "mediatek,mt8188-disp-gamma", "mediatek,mt8195-disp-gamma";</div><div class='add'>+			reg = &lt;0 0x1c006000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys0 CLK_VDO0_DISP_GAMMA0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDOSYS0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c00XXXX 0x6000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					gamma0_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;aal0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					gamma0_out: endpoint { };</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dither0: dither@1c007000 {</div><div class='add'>+			compatible = "mediatek,mt8188-disp-dither", "mediatek,mt8183-disp-dither";</div><div class='add'>+			reg = &lt;0 0x1c007000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys0 CLK_VDO0_DISP_DITHER0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDOSYS0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c00XXXX 0x7000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					dither0_in: endpoint { };</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					dither0_out: endpoint { };</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		disp_dsi0: dsi@1c008000 {</div><div class='add'>+			compatible = "mediatek,mt8188-dsi";</div><div class='add'>+			reg = &lt;0 0x1c008000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys0 CLK_VDO0_DSI0&gt;,</div><div class='add'>+				 &lt;&amp;vdosys0 CLK_VDO0_DSI0_DSI&gt;,</div><div class='add'>+				 &lt;&amp;mipi_tx_config0&gt;;</div><div class='add'>+			clock-names = "engine", "digital", "hs";</div><div class='add'>+			interrupts = &lt;GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			phys = &lt;&amp;mipi_tx_config0&gt;;</div><div class='add'>+			phy-names = "dphy";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDOSYS0&gt;;</div><div class='add'>+			resets = &lt;&amp;vdosys0 MT8188_VDO0_RST_DSI0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dsc0: dsc@1c009000 {</div><div class='add'>+			compatible = "mediatek,mt8188-disp-dsc", "mediatek,mt8195-disp-dsc";</div><div class='add'>+			reg = &lt;0 0x1c009000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys0 CLK_VDO0_DSC_WRAP0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDOSYS0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c00XXXX 0x9000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		disp_dsi1: dsi@1c012000 {</div><div class='add'>+			compatible = "mediatek,mt8188-dsi";</div><div class='add'>+			reg = &lt;0 0x1c012000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys0 CLK_VDO0_DSI1&gt;,</div><div class='add'>+				 &lt;&amp;vdosys0 CLK_VDO0_DSI1_DSI&gt;,</div><div class='add'>+				 &lt;&amp;mipi_tx_config1&gt;;</div><div class='add'>+			clock-names = "engine", "digital", "hs";</div><div class='add'>+			interrupts = &lt;GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			phys = &lt;&amp;mipi_tx_config1&gt;;</div><div class='add'>+			phy-names = "dphy";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDOSYS0&gt;;</div><div class='add'>+			resets = &lt;&amp;vdosys0 MT8188_VDO0_RST_DSI1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		merge0: merge0@1c014000 {</div><div class='add'>+			compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge";</div><div class='add'>+			reg = &lt;0 0x1c014000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys0 CLK_VDO0_VPP_MERGE0&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 CLK_VDO1_MERGE_VDO1_DL_ASYNC&gt;;</div><div class='add'>+			clock-names = "merge", "merge_async";</div><div class='add'>+			interrupts = &lt;GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDOSYS0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c01XXXX 0x4000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dp_intf0: dp-intf@1c015000 {</div><div class='add'>+			compatible = "mediatek,mt8188-dp-intf";</div><div class='add'>+			reg = &lt;0 0x1c015000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys0 CLK_VDO0_DP_INTF0_DP_INTF&gt;,</div><div class='add'>+				 &lt;&amp;vdosys0 CLK_VDO0_DP_INTF0&gt;,</div><div class='add'>+				 &lt;&amp;apmixedsys CLK_APMIXED_TVDPLL1&gt;;</div><div class='add'>+			clock-names = "pixel", "engine", "pll";</div><div class='add'>+			interrupts = &lt;GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDOSYS0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mutex0: mutex@1c016000 {</div><div class='add'>+			compatible = "mediatek,mt8188-disp-mutex";</div><div class='add'>+			reg = &lt;0 0x1c016000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys0 CLK_VDO0_DISP_MUTEX0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDOSYS0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c01XXXX 0x6000 0x1000&gt;;</div><div class='add'>+			mediatek,gce-events = &lt;CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		postmask0: postmask@1c01a000 {</div><div class='add'>+			compatible = "mediatek,mt8188-disp-postmask",</div><div class='add'>+				     "mediatek,mt8192-disp-postmask";</div><div class='add'>+			reg = &lt;0 0x1c01a000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys0 CLK_VDO0_DISP_POSTMASK0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDOSYS0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c01XXXX 0xa000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					postmask0_in: endpoint { };</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					postmask0_out: endpoint { };</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdosys0: syscon@1c01d000 {</div><div class='add'>+			compatible = "mediatek,mt8188-vdosys0", "syscon";</div><div class='add'>+			reg = &lt;0 0x1c01d000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+			mboxes = &lt;&amp;gce0 0 CMDQ_THR_PRIO_4&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c01XXXX 0xd000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb0: smi@1c022000 {</div><div class='add'>+			compatible = "mediatek,mt8188-smi-larb";</div><div class='add'>+			reg = &lt;0 0x1c022000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys0 CLK_VDO0_SMI_LARB&gt;,</div><div class='add'>+				 &lt;&amp;vdosys0 CLK_VDO0_SMI_LARB&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDOSYS0&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;SMI_L0_ID&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;vdo_smi_common&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb1: smi@1c023000 {</div><div class='add'>+			compatible = "mediatek,mt8188-smi-larb";</div><div class='add'>+			reg = &lt;0 0x1c023000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys0 CLK_VDO0_SMI_LARB&gt;,</div><div class='add'>+				 &lt;&amp;vdosys0 CLK_VDO0_SMI_LARB&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDOSYS0&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;SMI_L1_ID&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;vpp_smi_common&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdo_smi_common: smi@1c024000 {</div><div class='add'>+			compatible = "mediatek,mt8188-smi-common-vdo";</div><div class='add'>+			reg = &lt;0 0x1c024000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys0 CLK_VDO0_SMI_COMMON&gt;,</div><div class='add'>+				 &lt;&amp;vdosys0 CLK_VDO0_SMI_GALS&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDOSYS0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdo_iommu: iommu@1c028000 {</div><div class='add'>+			compatible = "mediatek,mt8188-iommu-vdo";</div><div class='add'>+			reg = &lt;0 0x1c028000 0 0x5000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys0 CLK_VDO0_SMI_IOMMU&gt;;</div><div class='add'>+			clock-names = "bclk";</div><div class='add'>+			interrupts = &lt;GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDOSYS0&gt;;</div><div class='add'>+			#iommu-cells = &lt;1&gt;;</div><div class='add'>+			mediatek,larbs = &lt;&amp;larb0 &amp;larb2 &amp;larb5 &amp;larb19 &amp;larb21&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdosys1: syscon@1c100000 {</div><div class='add'>+			compatible = "mediatek,mt8188-vdosys1", "syscon";</div><div class='add'>+			reg = &lt;0 0x1c100000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+			mboxes = &lt;&amp;gce0 1 CMDQ_THR_PRIO_4&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c10XXXX 0 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mutex1: mutex@1c101000 {</div><div class='add'>+			compatible = "mediatek,mt8188-disp-mutex";</div><div class='add'>+			reg = &lt;0 0x1c101000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys1 CLK_VDO1_DISP_MUTEX&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDOSYS1&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c10XXXX 0x1000 0x1000&gt;;</div><div class='add'>+			mediatek,gce-events = &lt;CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb2: smi@1c102000 {</div><div class='add'>+			compatible = "mediatek,mt8188-smi-larb";</div><div class='add'>+			reg = &lt;0 0x1c102000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys1 CLK_VDO1_SMI_LARB2&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 CLK_VDO1_SMI_LARB2&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDOSYS1&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;SMI_L2_ID&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;vdo_smi_common&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb3: smi@1c103000 {</div><div class='add'>+			compatible = "mediatek,mt8188-smi-larb";</div><div class='add'>+			reg = &lt;0 0x1c103000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys1 CLK_VDO1_SMI_LARB3&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 CLK_VDO1_SMI_LARB3&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDOSYS1&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;SMI_L3_ID&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;vpp_smi_common&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdo1_rdma0: rdma@1c104000 {</div><div class='add'>+			compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";</div><div class='add'>+			reg = &lt;0 0x1c104000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys1 CLK_VDO1_MDP_RDMA0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			iommus = &lt;&amp;vdo_iommu M4U_PORT_L2_MDP_RDMA0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDOSYS1&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c10XXXX 0x4000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdo1_rdma1: rdma@1c105000 {</div><div class='add'>+			compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";</div><div class='add'>+			reg = &lt;0 0x1c105000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys1 CLK_VDO1_MDP_RDMA1&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			iommus = &lt;&amp;vpp_iommu M4U_PORT_L3_MDP_RDMA1&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDOSYS1&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c10XXXX 0x5000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdo1_rdma2: rdma@1c106000 {</div><div class='add'>+			compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";</div><div class='add'>+			reg = &lt;0 0x1c106000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys1 CLK_VDO1_MDP_RDMA2&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			iommus = &lt;&amp;vdo_iommu M4U_PORT_L2_MDP_RDMA2&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDOSYS1&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c10XXXX 0x6000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdo1_rdma3: rdma@1c107000 {</div><div class='add'>+			compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";</div><div class='add'>+			reg = &lt;0 0x1c107000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys1 CLK_VDO1_MDP_RDMA3&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			iommus = &lt;&amp;vpp_iommu M4U_PORT_L3_MDP_RDMA3&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDOSYS1&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c10XXXX 0x7000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdo1_rdma4: rdma@1c108000 {</div><div class='add'>+			compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";</div><div class='add'>+			reg = &lt;0 0x1c108000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys1 CLK_VDO1_MDP_RDMA4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			iommus = &lt;&amp;vdo_iommu M4U_PORT_L2_MDP_RDMA4&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDOSYS1&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c10XXXX 0x8000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdo1_rdma5: rdma@1c109000 {</div><div class='add'>+			compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";</div><div class='add'>+			reg = &lt;0 0x1c109000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys1 CLK_VDO1_MDP_RDMA5&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			iommus = &lt;&amp;vpp_iommu M4U_PORT_L3_MDP_RDMA5&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDOSYS1&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c10XXXX 0x9000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdo1_rdma6: rdma@1c10a000 {</div><div class='add'>+			compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";</div><div class='add'>+			reg = &lt;0 0x1c10a000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys1 CLK_VDO1_MDP_RDMA6&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			iommus = &lt;&amp;vdo_iommu M4U_PORT_L2_MDP_RDMA6&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDOSYS1&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c10XXXX 0xa000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdo1_rdma7: rdma@1c10b000 {</div><div class='add'>+			compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";</div><div class='add'>+			reg = &lt;0 0x1c10b000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys1 CLK_VDO1_MDP_RDMA7&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			iommus = &lt;&amp;vpp_iommu M4U_PORT_L3_MDP_RDMA7&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDOSYS1&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c10XXXX 0xb000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		merge1: merge@1c10c000 {</div><div class='add'>+			compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge";</div><div class='add'>+			reg = &lt;0 0x1c10c000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys1 CLK_VDO1_VPP_MERGE0&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 CLK_VDO1_MERGE0_DL_ASYNC&gt;;</div><div class='add'>+			clock-names = "merge", "merge_async";</div><div class='add'>+			interrupts = &lt;GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDOSYS1&gt;;</div><div class='add'>+			resets = &lt;&amp;vdosys1 MT8188_VDO1_RST_MERGE0_DL_ASYNC&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c10XXXX 0xc000 0x1000&gt;;</div><div class='add'>+			mediatek,merge-mute;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		merge2: merge@1c10d000 {</div><div class='add'>+			compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge";</div><div class='add'>+			reg = &lt;0 0x1c10d000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys1 CLK_VDO1_VPP_MERGE1&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 CLK_VDO1_MERGE1_DL_ASYNC&gt;;</div><div class='add'>+			clock-names = "merge", "merge_async";</div><div class='add'>+			interrupts = &lt;GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDOSYS1&gt;;</div><div class='add'>+			resets = &lt;&amp;vdosys1 MT8188_VDO1_RST_MERGE1_DL_ASYNC&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c10XXXX 0xd000 0x1000&gt;;</div><div class='add'>+			mediatek,merge-mute;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		merge3: merge@1c10e000 {</div><div class='add'>+			compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge";</div><div class='add'>+			reg = &lt;0 0x1c10e000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys1 CLK_VDO1_VPP_MERGE2&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 CLK_VDO1_MERGE2_DL_ASYNC&gt;;</div><div class='add'>+			clock-names = "merge", "merge_async";</div><div class='add'>+			interrupts = &lt;GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDOSYS1&gt;;</div><div class='add'>+			resets = &lt;&amp;vdosys1 MT8188_VDO1_RST_MERGE2_DL_ASYNC&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c10XXXX 0xe000 0x1000&gt;;</div><div class='add'>+			mediatek,merge-mute;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		merge4: merge@1c10f000 {</div><div class='add'>+			compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge";</div><div class='add'>+			reg = &lt;0 0x1c10f000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys1 CLK_VDO1_VPP_MERGE3&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 CLK_VDO1_MERGE3_DL_ASYNC&gt;;</div><div class='add'>+			clock-names = "merge", "merge_async";</div><div class='add'>+			interrupts = &lt;GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDOSYS1&gt;;</div><div class='add'>+			resets = &lt;&amp;vdosys1 MT8188_VDO1_RST_MERGE3_DL_ASYNC&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c10XXXX 0xf000 0x1000&gt;;</div><div class='add'>+			mediatek,merge-mute;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		merge5: merge@1c110000 {</div><div class='add'>+			compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge";</div><div class='add'>+			reg = &lt;0 0x1c110000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys1 CLK_VDO1_VPP_MERGE4&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 CLK_VDO1_MERGE4_DL_ASYNC&gt;;</div><div class='add'>+			clock-names = "merge", "merge_async";</div><div class='add'>+			interrupts = &lt;GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDOSYS1&gt;;</div><div class='add'>+			resets = &lt;&amp;vdosys1 MT8188_VDO1_RST_MERGE4_DL_ASYNC&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c11XXXX 0x0000 0x1000&gt;;</div><div class='add'>+			mediatek,merge-fifo-en;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dp_intf1: dp-intf@1c113000 {</div><div class='add'>+			compatible = "mediatek,mt8188-dp-intf";</div><div class='add'>+			reg = &lt;0 0x1c113000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys1 CLK_VDO1_DPINTF&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 CLK_VDO1_DP_INTF0_MMCK&gt;,</div><div class='add'>+				 &lt;&amp;apmixedsys CLK_APMIXED_TVDPLL2&gt;;</div><div class='add'>+			clock-names = "pixel", "engine", "pll";</div><div class='add'>+			interrupts = &lt;GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDOSYS1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ethdr0: ethdr@1c114000 {</div><div class='add'>+			compatible = "mediatek,mt8188-disp-ethdr", "mediatek,mt8195-disp-ethdr";</div><div class='add'>+			reg = &lt;0 0x1c114000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x1c115000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x1c117000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x1c119000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x1c11a000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x1c11b000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x1c11c000 0 0x1000&gt;;</div><div class='add'>+			reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",</div><div class='add'>+				    "vdo_be", "adl_ds";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;vdosys1 CLK_VDO1_DISP_MIXER&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 CLK_VDO1_HDR_VDO_FE0&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 CLK_VDO1_HDR_VDO_FE1&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 CLK_VDO1_HDR_GFX_FE0&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 CLK_VDO1_HDR_GFX_FE1&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 CLK_VDO1_HDR_VDO_BE&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 CLK_VDO1_26M_SLOW&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_ETHDR&gt;;</div><div class='add'>+			clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",</div><div class='add'>+				      "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",</div><div class='add'>+				      "gfx_fe0_async", "gfx_fe1_async", "vdo_be_async", "ethdr_top";</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			iommus = &lt;&amp;vpp_iommu M4U_PORT_L3_HDR_DS_SMI&gt;,</div><div class='add'>+				 &lt;&amp;vpp_iommu M4U_PORT_L3_HDR_ADL_SMI&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDOSYS1&gt;;</div><div class='add'>+			resets = &lt;&amp;vdosys1 MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC&gt;;</div><div class='add'>+</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c11XXXX 0x4000 0x1000&gt;,</div><div class='add'>+						  &lt;&amp;gce0 SUBSYS_1c11XXXX 0x5000 0x1000&gt;,</div><div class='add'>+						  &lt;&amp;gce0 SUBSYS_1c11XXXX 0x7000 0x1000&gt;,</div><div class='add'>+						  &lt;&amp;gce0 SUBSYS_1c11XXXX 0x9000 0x1000&gt;,</div><div class='add'>+						  &lt;&amp;gce0 SUBSYS_1c11XXXX 0xa000 0x1000&gt;,</div><div class='add'>+						  &lt;&amp;gce0 SUBSYS_1c11XXXX 0xb000 0x1000&gt;,</div><div class='add'>+						  &lt;&amp;gce0 SUBSYS_1c11XXXX 0xc000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		padding0: padding@1c11d000 {</div><div class='add'>+			compatible = "mediatek,mt8188-disp-padding";</div><div class='add'>+			reg = &lt;0 0x1c11d000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys1 CLK_VDO1_PADDING0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDOSYS1&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c11XXXX 0xd000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		padding1: padding@1c11e000 {</div><div class='add'>+			compatible = "mediatek,mt8188-disp-padding";</div><div class='add'>+			reg = &lt;0 0x1c11e000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys1 CLK_VDO1_PADDING1&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDOSYS1&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c11XXXX 0xe000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		padding2: padding@1c11f000 {</div><div class='add'>+			compatible = "mediatek,mt8188-disp-padding";</div><div class='add'>+			reg = &lt;0 0x1c11f000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys1 CLK_VDO1_PADDING2&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDOSYS1&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c11XXXX 0xf000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		padding3: padding@1c120000 {</div><div class='add'>+			compatible = "mediatek,mt8188-disp-padding";</div><div class='add'>+			reg = &lt;0 0x1c120000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys1 CLK_VDO1_PADDING3&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDOSYS1&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c12XXXX 0x0000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		padding4: padding@1c121000 {</div><div class='add'>+			compatible = "mediatek,mt8188-disp-padding";</div><div class='add'>+			reg = &lt;0 0x1c121000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys1 CLK_VDO1_PADDING4&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDOSYS1&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c12XXXX 0x1000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		padding5: padding@1c122000 {</div><div class='add'>+			compatible = "mediatek,mt8188-disp-padding";</div><div class='add'>+			reg = &lt;0 0x1c122000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys1 CLK_VDO1_PADDING5&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDOSYS1&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c12XXXX 0x2000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		padding6: padding@1c123000 {</div><div class='add'>+			compatible = "mediatek,mt8188-disp-padding";</div><div class='add'>+			reg = &lt;0 0x1c123000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys1 CLK_VDO1_PADDING6&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDOSYS1&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c12XXXX 0x3000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		padding7: padding@1c124000 {</div><div class='add'>+			compatible = "mediatek,mt8188-disp-padding";</div><div class='add'>+			reg = &lt;0 0x1c124000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys1 CLK_VDO1_PADDING7&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_VDOSYS1&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c12XXXX 0x4000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		edp_tx: edp-tx@1c500000 {</div><div class='add'>+			compatible = "mediatek,mt8188-edp-tx";</div><div class='add'>+			reg = &lt;0 0x1c500000 0 0x8000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			nvmem-cells = &lt;&amp;dp_calib_data&gt;;</div><div class='add'>+			nvmem-cell-names = "dp_calibration_data";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_EDP_TX&gt;;</div><div class='add'>+			max-linkrate-mhz = &lt;8100&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dp_tx: dp-tx@1c600000 {</div><div class='add'>+			compatible = "mediatek,mt8188-dp-tx";</div><div class='add'>+			reg = &lt;0 0x1c600000 0 0x8000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			nvmem-cells = &lt;&amp;dp_calib_data&gt;;</div><div class='add'>+			nvmem-cell-names = "dp_calibration_data";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_DP_TX&gt;;</div><div class='add'>+			max-linkrate-mhz = &lt;5400&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts<br/>new file mode 100644<br/>index 000000000000..ac2673e56fb8<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts</a></div><div class='hunk'>@@ -0,0 +1,147 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2020 Google LLC</div><div class='add'>+ */</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8192-asurada.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google Hayato rev1";</div><div class='add'>+	chassis-type = "convertible";</div><div class='add'>+	compatible = "google,hayato-rev1", "google,hayato", "mediatek,mt8192";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;keyboard_controller {</div><div class='add'>+	function-row-physmap = &lt;</div><div class='add'>+		MATRIX_KEY(0x00, 0x02, 0)	/* T1 */</div><div class='add'>+		MATRIX_KEY(0x03, 0x02, 0)	/* T2 */</div><div class='add'>+		MATRIX_KEY(0x02, 0x02, 0)	/* T3 */</div><div class='add'>+		MATRIX_KEY(0x01, 0x02, 0)	/* T4 */</div><div class='add'>+		MATRIX_KEY(0x03, 0x04, 0)	/* T5 */</div><div class='add'>+		MATRIX_KEY(0x02, 0x04, 0)	/* T6 */</div><div class='add'>+		MATRIX_KEY(0x01, 0x04, 0)	/* T7 */</div><div class='add'>+		MATRIX_KEY(0x02, 0x09, 0)	/* T8 */</div><div class='add'>+		MATRIX_KEY(0x01, 0x09, 0)	/* T9 */</div><div class='add'>+		MATRIX_KEY(0x00, 0x04, 0)	/* T10 */</div><div class='add'>+	&gt;;</div><div class='add'>+	linux,keymap = &lt;</div><div class='add'>+		MATRIX_KEY(0x00, 0x02, KEY_BACK)</div><div class='add'>+		MATRIX_KEY(0x03, 0x02, KEY_FORWARD)</div><div class='add'>+		MATRIX_KEY(0x02, 0x02, KEY_REFRESH)</div><div class='add'>+		MATRIX_KEY(0x01, 0x02, KEY_FULL_SCREEN)</div><div class='add'>+		MATRIX_KEY(0x03, 0x04, KEY_SCALE)</div><div class='add'>+		MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN)</div><div class='add'>+		MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP)</div><div class='add'>+		MATRIX_KEY(0x02, 0x09, KEY_MUTE)</div><div class='add'>+		MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)</div><div class='add'>+		MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)</div><div class='add'>+</div><div class='add'>+		CROS_STD_MAIN_KEYMAP</div><div class='add'>+	&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	bt_pins: bt-pins {</div><div class='add'>+		pins-bt-kill {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO144__FUNC_GPIO144&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-bt-wake {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO22__FUNC_GPIO22&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-ap-wake-bt {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO168__FUNC_GPIO168&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart1_pins: uart1-pins {</div><div class='add'>+		pins-rx {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO94__FUNC_URXD1&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-tx {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO95__FUNC_UTXD1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-cts {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO166__FUNC_UCTS1&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-rts {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO167__FUNC_URTS1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart1_pins_sleep: uart1-sleep-pins {</div><div class='add'>+		pins-rx {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO94__FUNC_GPIO94&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-tx {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO95__FUNC_UTXD1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-cts {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO166__FUNC_UCTS1&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-rts {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO167__FUNC_URTS1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;rt5682 {</div><div class='add'>+	compatible = "realtek,rt5682i";</div><div class='add'>+	realtek,btndet-delay = &lt;16&gt;;</div><div class='add'>+	VBAT-supply = &lt;&amp;pp3300_ldo_z&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sound {</div><div class='add'>+	compatible = "mediatek,mt8192_mt6359_rt1015p_rt5682";</div><div class='add'>+</div><div class='add'>+	speaker-codecs {</div><div class='add'>+		sound-dai = &lt;&amp;rt1015p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	headset-codec {</div><div class='add'>+		sound-dai = &lt;&amp;rt5682 0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;touchscreen {</div><div class='add'>+	compatible = "hid-over-i2c";</div><div class='add'>+	post-power-on-delay-ms = &lt;10&gt;;</div><div class='add'>+	hid-descr-addr = &lt;0x0001&gt;;</div><div class='add'>+	vdd-supply = &lt;&amp;pp3300_u&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart1_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;uart1_pins_sleep&gt;;</div><div class='add'>+	/delete-property/ interrupts;</div><div class='add'>+	interrupts-extended = &lt;&amp;gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			      &lt;&amp;pio 94 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "realtek,rtl8822cs-bt";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;bt_pins&gt;;</div><div class='add'>+</div><div class='add'>+		enable-gpios = &lt;&amp;pio 144 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		device-wake-gpios = &lt;&amp;pio 168 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		host-wake-gpios = &lt;&amp;pio 22 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts<br/>new file mode 100644<br/>index 000000000000..163960f58db5<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts</a></div><div class='hunk'>@@ -0,0 +1,99 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021 Google LLC</div><div class='add'>+ */</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8192-asurada.dtsi"</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Google Spherion (rev0 - 3)";</div><div class='add'>+	chassis-type = "laptop";</div><div class='add'>+	compatible = "google,spherion-rev3", "google,spherion-rev2",</div><div class='add'>+		     "google,spherion-rev1", "google,spherion-rev0",</div><div class='add'>+		     "google,spherion", "mediatek,mt8192";</div><div class='add'>+</div><div class='add'>+	pwmleds {</div><div class='add'>+		compatible = "pwm-leds";</div><div class='add'>+</div><div class='add'>+		led {</div><div class='add'>+			function = LED_FUNCTION_KBD_BACKLIGHT;</div><div class='add'>+			color = &lt;LED_COLOR_ID_WHITE&gt;;</div><div class='add'>+			pwms = &lt;&amp;cros_ec_pwm 0&gt;;</div><div class='add'>+			max-brightness = &lt;1023&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cros_ec_pwm {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;keyboard_controller {</div><div class='add'>+	function-row-physmap = &lt;</div><div class='add'>+		MATRIX_KEY(0x00, 0x02, 0)	/* T1 */</div><div class='add'>+		MATRIX_KEY(0x03, 0x02, 0)	/* T2 */</div><div class='add'>+		MATRIX_KEY(0x02, 0x02, 0)	/* T3 */</div><div class='add'>+		MATRIX_KEY(0x01, 0x02, 0)	/* T4 */</div><div class='add'>+		MATRIX_KEY(0x03, 0x04, 0)	/* T5 */</div><div class='add'>+		MATRIX_KEY(0x02, 0x04, 0)	/* T6 */</div><div class='add'>+		MATRIX_KEY(0x01, 0x04, 0)	/* T7 */</div><div class='add'>+		MATRIX_KEY(0x02, 0x09, 0)	/* T8 */</div><div class='add'>+		MATRIX_KEY(0x01, 0x09, 0)	/* T9 */</div><div class='add'>+		MATRIX_KEY(0x00, 0x04, 0)	/* T10 */</div><div class='add'>+	&gt;;</div><div class='add'>+	linux,keymap = &lt;</div><div class='add'>+		MATRIX_KEY(0x00, 0x02, KEY_BACK)</div><div class='add'>+		MATRIX_KEY(0x03, 0x02, KEY_REFRESH)</div><div class='add'>+		MATRIX_KEY(0x02, 0x02, KEY_FULL_SCREEN)</div><div class='add'>+		MATRIX_KEY(0x01, 0x02, KEY_SCALE)</div><div class='add'>+		MATRIX_KEY(0x03, 0x04, KEY_SYSRQ)</div><div class='add'>+		MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN)</div><div class='add'>+		MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP)</div><div class='add'>+		MATRIX_KEY(0x02, 0x09, KEY_MUTE)</div><div class='add'>+		MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)</div><div class='add'>+		MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)</div><div class='add'>+</div><div class='add'>+		CROS_STD_MAIN_KEYMAP</div><div class='add'>+	&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;rt5682 {</div><div class='add'>+	compatible = "realtek,rt5682i";</div><div class='add'>+	realtek,btndet-delay = &lt;16&gt;;</div><div class='add'>+	VBAT-supply = &lt;&amp;pp3300_ldo_z&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sound {</div><div class='add'>+	compatible = "mediatek,mt8192_mt6359_rt1015p_rt5682";</div><div class='add'>+</div><div class='add'>+	speaker-codecs {</div><div class='add'>+		sound-dai = &lt;&amp;rt1015p&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	headset-codec {</div><div class='add'>+		sound-dai = &lt;&amp;rt5682 0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;touchscreen {</div><div class='add'>+	compatible = "elan,ekth3500";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	/* synaptics touchpad */</div><div class='add'>+	trackpad@2c {</div><div class='add'>+		compatible = "hid-over-i2c";</div><div class='add'>+		reg = &lt;0x2c&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;trackpad_pins&gt;;</div><div class='add'>+		hid-descr-addr = &lt;0x20&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 15 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		wakeup-source;</div><div class='add'>+		status = "fail-needs-probe";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;trackpad {</div><div class='add'>+	status = "fail-needs-probe";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi<br/>new file mode 100644<br/>index 000000000000..0b4664f044a1<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi</a></div><div class='hunk'>@@ -0,0 +1,1484 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2020 MediaTek Inc.</div><div class='add'>+ * Author: Seiya Wang &lt;seiya.wang@mediatek.com&gt;</div><div class='add'>+ */</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8192.dtsi"</div><div class='add'>+#include "mt6359.dtsi"</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/spmi/spmi.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		i2c0 = &amp;i2c0;</div><div class='add'>+		i2c1 = &amp;i2c1;</div><div class='add'>+		i2c2 = &amp;i2c2;</div><div class='add'>+		i2c3 = &amp;i2c3;</div><div class='add'>+		i2c7 = &amp;i2c7;</div><div class='add'>+		mmc0 = &amp;mmc0;</div><div class='add'>+		mmc1 = &amp;mmc1;</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0 0x40000000 0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	backlight_lcd0: backlight-lcd0 {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		pwms = &lt;&amp;pwm0 0 500000&gt;;</div><div class='add'>+		power-supply = &lt;&amp;ppvar_sys&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;pio 152 0&gt;;</div><div class='add'>+		brightness-levels = &lt;0 1023&gt;;</div><div class='add'>+		num-interpolated-steps = &lt;1023&gt;;</div><div class='add'>+		default-brightness-level = &lt;576&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dmic_codec: dmic-codec {</div><div class='add'>+		compatible = "dmic-codec";</div><div class='add'>+		num-channels = &lt;2&gt;;</div><div class='add'>+		wakeup-delay-ms = &lt;50&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pp1000_dpbrdg: regulator-1v0-dpbrdg {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "pp1000_dpbrdg";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pp1000_dpbrdg_en_pins&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;1000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		gpio = &lt;&amp;pio 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;mt6359_vs2_buck_reg&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pp1000_mipibrdg: regulator-1v0-mipibrdg {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "pp1000_mipibrdg";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pp1000_mipibrdg_en_pins&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;1000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		gpio = &lt;&amp;pio 129 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;mt6359_vs2_buck_reg&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pp1800_dpbrdg: regulator-1v8-dpbrdg {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "pp1800_dpbrdg";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pp1800_dpbrdg_en_pins&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		gpio = &lt;&amp;pio 126 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;mt6359_vio18_ldo_reg&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* system wide LDO 1.8V power rail */</div><div class='add'>+	pp1800_ldo_g: regulator-1v8-g {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "pp1800_ldo_g";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;pp3300_g&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pp1800_mipibrdg: regulator-1v8-mipibrdg {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "pp1800_mipibrdg";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pp1800_mipibrdg_en_pins&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		gpio = &lt;&amp;pio 128 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;mt6359_vio18_ldo_reg&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pp3300_dpbrdg: regulator-3v3-dpbrdg {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "pp3300_dpbrdg";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pp3300_dpbrdg_en_pins&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		gpio = &lt;&amp;pio 26 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;pp3300_g&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* system wide switching 3.3V power rail */</div><div class='add'>+	pp3300_g: regulator-3v3-g {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "pp3300_g";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;ppvar_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* system wide LDO 3.3V power rail */</div><div class='add'>+	pp3300_ldo_z: regulator-3v3-z {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "pp3300_ldo_z";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;ppvar_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pp3300_mipibrdg: regulator-3v3-mipibrdg {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "pp3300_mipibrdg";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pp3300_mipibrdg_en_pins&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		gpio = &lt;&amp;pio 127 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;pp3300_g&gt;;</div><div class='add'>+		off-on-delay-us = &lt;500000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* separately switched 3.3V power rail */</div><div class='add'>+	pp3300_u: regulator-3v3-u {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "pp3300_u";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		/* enable pin wired to GPIO controlled by EC */</div><div class='add'>+		vin-supply = &lt;&amp;pp3300_g&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pp3300_wlan: regulator-3v3-wlan {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "pp3300_wlan";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pp3300_wlan_pins&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;pio 143 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* system wide switching 5.0V power rail */</div><div class='add'>+	pp5000_a: regulator-5v0-a {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "pp5000_a";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;ppvar_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* system wide semi-regulated power rail from battery or USB */</div><div class='add'>+	ppvar_sys: regulator-var-sys {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "ppvar_sys";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved_memory: reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		afe_dma_mem: audio-dma-pool {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			size = &lt;0 0x100000&gt;;</div><div class='add'>+			alignment = &lt;0 0x10&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		scp_mem_reserved: scp@50000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x50000000 0 0x2900000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wifi_restricted_dma_region: wifi@c0000000 {</div><div class='add'>+			compatible = "restricted-dma-pool";</div><div class='add'>+			reg = &lt;0 0xc0000000 0 0x4000000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rt1015p: audio-codec {</div><div class='add'>+		compatible = "realtek,rt1015p";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;rt1015p_pins&gt;;</div><div class='add'>+		sdb-gpios = &lt;&amp;pio 147 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound: sound {</div><div class='add'>+		mediatek,platform = &lt;&amp;afe&gt;;</div><div class='add'>+		pinctrl-names = "aud_clk_mosi_off",</div><div class='add'>+				"aud_clk_mosi_on",</div><div class='add'>+				"aud_dat_mosi_off",</div><div class='add'>+				"aud_dat_mosi_on",</div><div class='add'>+				"aud_dat_miso_off",</div><div class='add'>+				"aud_dat_miso_on",</div><div class='add'>+				"vow_dat_miso_off",</div><div class='add'>+				"vow_dat_miso_on",</div><div class='add'>+				"vow_clk_miso_off",</div><div class='add'>+				"vow_clk_miso_on",</div><div class='add'>+				"aud_nle_mosi_off",</div><div class='add'>+				"aud_nle_mosi_on",</div><div class='add'>+				"aud_dat_miso2_off",</div><div class='add'>+				"aud_dat_miso2_on",</div><div class='add'>+				"aud_gpio_i2s3_off",</div><div class='add'>+				"aud_gpio_i2s3_on",</div><div class='add'>+				"aud_gpio_i2s8_off",</div><div class='add'>+				"aud_gpio_i2s8_on",</div><div class='add'>+				"aud_gpio_i2s9_off",</div><div class='add'>+				"aud_gpio_i2s9_on",</div><div class='add'>+				"aud_dat_mosi_ch34_off",</div><div class='add'>+				"aud_dat_mosi_ch34_on",</div><div class='add'>+				"aud_dat_miso_ch34_off",</div><div class='add'>+				"aud_dat_miso_ch34_on",</div><div class='add'>+				"aud_gpio_tdm_off",</div><div class='add'>+				"aud_gpio_tdm_on";</div><div class='add'>+		pinctrl-0 = &lt;&amp;aud_clk_mosi_off_pins&gt;;</div><div class='add'>+		pinctrl-1 = &lt;&amp;aud_clk_mosi_on_pins&gt;;</div><div class='add'>+		pinctrl-2 = &lt;&amp;aud_dat_mosi_off_pins&gt;;</div><div class='add'>+		pinctrl-3 = &lt;&amp;aud_dat_mosi_on_pins&gt;;</div><div class='add'>+		pinctrl-4 = &lt;&amp;aud_dat_miso_off_pins&gt;;</div><div class='add'>+		pinctrl-5 = &lt;&amp;aud_dat_miso_on_pins&gt;;</div><div class='add'>+		pinctrl-6 = &lt;&amp;vow_dat_miso_off_pins&gt;;</div><div class='add'>+		pinctrl-7 = &lt;&amp;vow_dat_miso_on_pins&gt;;</div><div class='add'>+		pinctrl-8 = &lt;&amp;vow_clk_miso_off_pins&gt;;</div><div class='add'>+		pinctrl-9 = &lt;&amp;vow_clk_miso_on_pins&gt;;</div><div class='add'>+		pinctrl-10 = &lt;&amp;aud_nle_mosi_off_pins&gt;;</div><div class='add'>+		pinctrl-11 = &lt;&amp;aud_nle_mosi_on_pins&gt;;</div><div class='add'>+		pinctrl-12 = &lt;&amp;aud_dat_miso2_off_pins&gt;;</div><div class='add'>+		pinctrl-13 = &lt;&amp;aud_dat_miso2_on_pins&gt;;</div><div class='add'>+		pinctrl-14 = &lt;&amp;aud_gpio_i2s3_off_pins&gt;;</div><div class='add'>+		pinctrl-15 = &lt;&amp;aud_gpio_i2s3_on_pins&gt;;</div><div class='add'>+		pinctrl-16 = &lt;&amp;aud_gpio_i2s8_off_pins&gt;;</div><div class='add'>+		pinctrl-17 = &lt;&amp;aud_gpio_i2s8_on_pins&gt;;</div><div class='add'>+		pinctrl-18 = &lt;&amp;aud_gpio_i2s9_off_pins&gt;;</div><div class='add'>+		pinctrl-19 = &lt;&amp;aud_gpio_i2s9_on_pins&gt;;</div><div class='add'>+		pinctrl-20 = &lt;&amp;aud_dat_mosi_ch34_off_pins&gt;;</div><div class='add'>+		pinctrl-21 = &lt;&amp;aud_dat_mosi_ch34_on_pins&gt;;</div><div class='add'>+		pinctrl-22 = &lt;&amp;aud_dat_miso_ch34_off_pins&gt;;</div><div class='add'>+		pinctrl-23 = &lt;&amp;aud_dat_miso_ch34_on_pins&gt;;</div><div class='add'>+		pinctrl-24 = &lt;&amp;aud_gpio_tdm_off_pins&gt;;</div><div class='add'>+		pinctrl-25 = &lt;&amp;aud_gpio_tdm_on_pins&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;afe {</div><div class='add'>+	memory-region = &lt;&amp;afe_dma_mem&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsi0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsi_out {</div><div class='add'>+	remote-endpoint = &lt;&amp;anx7625_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gic {</div><div class='add'>+	mediatek,broken-save-restore-fw;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	mali-supply = &lt;&amp;mt6315_7_vbuck1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c0_pins&gt;;</div><div class='add'>+</div><div class='add'>+	touchscreen: touchscreen@10 {</div><div class='add'>+		reg = &lt;0x10&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 21 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;touchscreen_pins&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c1_pins&gt;;</div><div class='add'>+</div><div class='add'>+	rt5682: audio-codec@1a {</div><div class='add'>+		/* Realtek RT5682i or RT5682s, sharing the same configuration */</div><div class='add'>+		reg = &lt;0x1a&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 18 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		realtek,jd-src = &lt;1&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		AVDD-supply = &lt;&amp;mt6359_vio18_ldo_reg&gt;;</div><div class='add'>+		DBVDD-supply = &lt;&amp;mt6359_vio18_ldo_reg&gt;;</div><div class='add'>+		LDO1-IN-supply = &lt;&amp;mt6359_vio18_ldo_reg&gt;;</div><div class='add'>+		MICVDD-supply = &lt;&amp;pp3300_g&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	clock-stretch-ns = &lt;12600&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c2_pins&gt;;</div><div class='add'>+</div><div class='add'>+	trackpad: trackpad@15 {</div><div class='add'>+		compatible = "elan,ekth3000";</div><div class='add'>+		reg = &lt;0x15&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;trackpad_pins&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 15 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;pp3300_u&gt;;</div><div class='add'>+		wakeup-source;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c3_pins&gt;;</div><div class='add'>+</div><div class='add'>+	anx_bridge: anx7625@58 {</div><div class='add'>+		compatible = "analogix,anx7625";</div><div class='add'>+		reg = &lt;0x58&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;anx7625_pins&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;pio 41 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pio 42 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		vdd10-supply = &lt;&amp;pp1000_mipibrdg&gt;;</div><div class='add'>+		vdd18-supply = &lt;&amp;pp1800_mipibrdg&gt;;</div><div class='add'>+		vdd33-supply = &lt;&amp;pp3300_mipibrdg&gt;;</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				anx7625_in: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;dsi_out&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				anx7625_out: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;panel_in&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aux-bus {</div><div class='add'>+			panel: panel {</div><div class='add'>+				compatible = "edp-panel";</div><div class='add'>+				power-supply = &lt;&amp;pp3300_mipibrdg&gt;;</div><div class='add'>+				backlight = &lt;&amp;backlight_lcd0&gt;;</div><div class='add'>+</div><div class='add'>+				port {</div><div class='add'>+					panel_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;anx7625_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c7 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c7_pins&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mfg0 {</div><div class='add'>+	domain-supply = &lt;&amp;mt6315_7_vbuck1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mfg1 {</div><div class='add'>+	domain-supply = &lt;&amp;mt6359_vsram_others_ldo_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_tx0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pinctrl-names = "default", "state_uhs";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc0_default_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;mmc0_uhs_pins&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;mt6359_vemc_1_ldo_reg&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;mt6359_vufs_ldo_reg&gt;;</div><div class='add'>+	cap-mmc-highspeed;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	mmc-hs400-1_8v;</div><div class='add'>+	supports-cqe;</div><div class='add'>+	cap-mmc-hw-reset;</div><div class='add'>+	mmc-hs400-enhanced-strobe;</div><div class='add'>+	hs400-ds-delay = &lt;0x12814&gt;;</div><div class='add'>+	no-sdio;</div><div class='add'>+	no-sd;</div><div class='add'>+	non-removable;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pinctrl-names = "default", "state_uhs";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc1_default_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;mmc1_uhs_pins&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;pio 17 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;mt6360_ldo5_reg&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;mt6360_ldo3_reg&gt;;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	sd-uhs-sdr50;</div><div class='add'>+	sd-uhs-sdr104;</div><div class='add'>+	no-sdio;</div><div class='add'>+	no-mmc;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* for CORE */</div><div class='add'>+&amp;mt6359_vgpu11_buck_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vgpu11_sshub_buck_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+	regulator-min-microvolt = &lt;575000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;575000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vrf12_ldo_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vsram_others_ldo_reg {</div><div class='add'>+	regulator-min-microvolt = &lt;750000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;800000&gt;;</div><div class='add'>+	regulator-coupled-with = &lt;&amp;mt6315_7_vbuck1&gt;;</div><div class='add'>+	regulator-coupled-max-spread = &lt;10000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vufs_ldo_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359codec {</div><div class='add'>+	mediatek,dmic-mode = &lt;1&gt;; /* one-wire */</div><div class='add'>+	mediatek,mic-type-0 = &lt;2&gt;; /* DMIC */</div><div class='add'>+	mediatek,mic-type-2 = &lt;2&gt;; /* DMIC */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;nor_flash {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;nor_flash_pins&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;topckgen CLK_TOP_SFLASH_SEL&gt;;</div><div class='add'>+	assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_UNIVPLL_D6_D8&gt;;</div><div class='add'>+</div><div class='add'>+	flash@0 {</div><div class='add'>+		compatible = "winbond,w25q64jwm", "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;52000000&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;2&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pcie_pins&gt;;</div><div class='add'>+</div><div class='add'>+	pcie0: pcie@0,0 {</div><div class='add'>+		device_type = "pci";</div><div class='add'>+		reg = &lt;0x0000 0 0 0 0&gt;;</div><div class='add'>+		num-lanes = &lt;1&gt;;</div><div class='add'>+		bus-range = &lt;0x1 0x1&gt;;</div><div class='add'>+</div><div class='add'>+		#address-cells = &lt;3&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		wifi: wifi@0,0 {</div><div class='add'>+			reg = &lt;0x10000 0 0 0 0x100000&gt;,</div><div class='add'>+			      &lt;0x10000 0 0x100000 0 0x100000&gt;;</div><div class='add'>+			memory-region = &lt;&amp;wifi_restricted_dma_region&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	/* 220 lines */</div><div class='add'>+	gpio-line-names = "I2S_DP_LRCK",</div><div class='add'>+			  "IS_DP_BCLK",</div><div class='add'>+			  "I2S_DP_MCLK",</div><div class='add'>+			  "I2S_DP_DATAOUT",</div><div class='add'>+			  "SAR0_INT_ODL",</div><div class='add'>+			  "EC_AP_INT_ODL",</div><div class='add'>+			  "EDPBRDG_INT_ODL",</div><div class='add'>+			  "DPBRDG_INT_ODL",</div><div class='add'>+			  "DPBRDG_PWREN",</div><div class='add'>+			  "DPBRDG_RST_ODL",</div><div class='add'>+			  "I2S_HP_MCLK",</div><div class='add'>+			  "I2S_HP_BCK",</div><div class='add'>+			  "I2S_HP_LRCK",</div><div class='add'>+			  "I2S_HP_DATAIN",</div><div class='add'>+			  /*</div><div class='add'>+			   * AP_FLASH_WP_L is crossystem ABI. Schematics</div><div class='add'>+			   * call it AP_FLASH_WP_ODL.</div><div class='add'>+			   */</div><div class='add'>+			  "AP_FLASH_WP_L",</div><div class='add'>+			  "TRACKPAD_INT_ODL",</div><div class='add'>+			  "EC_AP_HPD_OD",</div><div class='add'>+			  "SD_CD_ODL",</div><div class='add'>+			  "HP_INT_ODL_ALC",</div><div class='add'>+			  "EN_PP1000_DPBRDG",</div><div class='add'>+			  "AP_GPIO20",</div><div class='add'>+			  "TOUCH_INT_L_1V8",</div><div class='add'>+			  "UART_BT_WAKE_ODL",</div><div class='add'>+			  "AP_GPIO23",</div><div class='add'>+			  "AP_SPI_FLASH_CS_L",</div><div class='add'>+			  "AP_SPI_FLASH_CLK",</div><div class='add'>+			  "EN_PP3300_DPBRDG_DX",</div><div class='add'>+			  "AP_SPI_FLASH_MOSI",</div><div class='add'>+			  "AP_SPI_FLASH_MISO",</div><div class='add'>+			  "I2S_HP_DATAOUT",</div><div class='add'>+			  "AP_GPIO30",</div><div class='add'>+			  "I2S_SPKR_MCLK",</div><div class='add'>+			  "I2S_SPKR_BCLK",</div><div class='add'>+			  "I2S_SPKR_LRCK",</div><div class='add'>+			  "I2S_SPKR_DATAIN",</div><div class='add'>+			  "I2S_SPKR_DATAOUT",</div><div class='add'>+			  "AP_SPI_H1_TPM_CLK",</div><div class='add'>+			  "AP_SPI_H1_TPM_CS_L",</div><div class='add'>+			  "AP_SPI_H1_TPM_MISO",</div><div class='add'>+			  "AP_SPI_H1_TPM_MOSI",</div><div class='add'>+			  "BL_PWM",</div><div class='add'>+			  "EDPBRDG_PWREN",</div><div class='add'>+			  "EDPBRDG_RST_ODL",</div><div class='add'>+			  "EN_PP3300_HUB",</div><div class='add'>+			  "HUB_RST_L",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "SD_CLK",</div><div class='add'>+			  "SD_CMD",</div><div class='add'>+			  "SD_DATA3",</div><div class='add'>+			  "SD_DATA0",</div><div class='add'>+			  "SD_DATA2",</div><div class='add'>+			  "SD_DATA1",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "PCIE_WAKE_ODL",</div><div class='add'>+			  "PCIE_RST_L",</div><div class='add'>+			  "PCIE_CLKREQ_ODL",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "SPMI_SCL",</div><div class='add'>+			  "SPMI_SDA",</div><div class='add'>+			  "AP_GOOD",</div><div class='add'>+			  "UART_DBG_TX_AP_RX",</div><div class='add'>+			  "UART_AP_TX_DBG_RX",</div><div class='add'>+			  "UART_AP_TX_BT_RX",</div><div class='add'>+			  "UART_BT_TX_AP_RX",</div><div class='add'>+			  "MIPI_DPI_D0_R",</div><div class='add'>+			  "MIPI_DPI_D1_R",</div><div class='add'>+			  "MIPI_DPI_D2_R",</div><div class='add'>+			  "MIPI_DPI_D3_R",</div><div class='add'>+			  "MIPI_DPI_D4_R",</div><div class='add'>+			  "MIPI_DPI_D5_R",</div><div class='add'>+			  "MIPI_DPI_D6_R",</div><div class='add'>+			  "MIPI_DPI_D7_R",</div><div class='add'>+			  "MIPI_DPI_D8_R",</div><div class='add'>+			  "MIPI_DPI_D9_R",</div><div class='add'>+			  "MIPI_DPI_D10_R",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "MIPI_DPI_DE_R",</div><div class='add'>+			  "MIPI_DPI_D11_R",</div><div class='add'>+			  "MIPI_DPI_VSYNC_R",</div><div class='add'>+			  "MIPI_DPI_CLK_R",</div><div class='add'>+			  "MIPI_DPI_HSYNC_R",</div><div class='add'>+			  "PCM_BT_DATAIN",</div><div class='add'>+			  "PCM_BT_SYNC",</div><div class='add'>+			  "PCM_BT_DATAOUT",</div><div class='add'>+			  "PCM_BT_CLK",</div><div class='add'>+			  "AP_I2C_AUDIO_SCL",</div><div class='add'>+			  "AP_I2C_AUDIO_SDA",</div><div class='add'>+			  "SCP_I2C_SCL",</div><div class='add'>+			  "SCP_I2C_SDA",</div><div class='add'>+			  "AP_I2C_WLAN_SCL",</div><div class='add'>+			  "AP_I2C_WLAN_SDA",</div><div class='add'>+			  "AP_I2C_DPBRDG_SCL",</div><div class='add'>+			  "AP_I2C_DPBRDG_SDA",</div><div class='add'>+			  "EN_PP1800_DPBRDG_DX",</div><div class='add'>+			  "EN_PP3300_EDP_DX",</div><div class='add'>+			  "EN_PP1800_EDPBRDG_DX",</div><div class='add'>+			  "EN_PP1000_EDPBRDG",</div><div class='add'>+			  "SCP_JTAG0_TDO",</div><div class='add'>+			  "SCP_JTAG0_TDI",</div><div class='add'>+			  "SCP_JTAG0_TMS",</div><div class='add'>+			  "SCP_JTAG0_TCK",</div><div class='add'>+			  "SCP_JTAG0_TRSTN",</div><div class='add'>+			  "EN_PP3000_VMC_PMU",</div><div class='add'>+			  "EN_PP3300_DISPLAY_DX",</div><div class='add'>+			  "TOUCH_RST_L_1V8",</div><div class='add'>+			  "TOUCH_REPORT_DISABLE",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "AP_I2C_TRACKPAD_SCL_1V8",</div><div class='add'>+			  "AP_I2C_TRACKPAD_SDA_1V8",</div><div class='add'>+			  "EN_PP3300_WLAN",</div><div class='add'>+			  "BT_KILL_L",</div><div class='add'>+			  "WIFI_KILL_L",</div><div class='add'>+			  "SET_VMC_VOLT_AT_1V8",</div><div class='add'>+			  "EN_SPK",</div><div class='add'>+			  "AP_WARM_RST_REQ",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "EN_PP3000_SD_S3",</div><div class='add'>+			  "AP_EDP_BKLTEN",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "AP_SPI_EC_CLK",</div><div class='add'>+			  "AP_SPI_EC_CS_L",</div><div class='add'>+			  "AP_SPI_EC_MISO",</div><div class='add'>+			  "AP_SPI_EC_MOSI",</div><div class='add'>+			  "AP_I2C_EDPBRDG_SCL",</div><div class='add'>+			  "AP_I2C_EDPBRDG_SDA",</div><div class='add'>+			  "MT6315_PROC_INT",</div><div class='add'>+			  "MT6315_GPU_INT",</div><div class='add'>+			  "UART_SERVO_TX_SCP_RX",</div><div class='add'>+			  "UART_SCP_TX_SERVO_RX",</div><div class='add'>+			  "BT_RTS_AP_CTS",</div><div class='add'>+			  "AP_RTS_BT_CTS",</div><div class='add'>+			  "UART_AP_WAKE_BT_ODL",</div><div class='add'>+			  "WLAN_ALERT_ODL",</div><div class='add'>+			  "EC_IN_RW_ODL",</div><div class='add'>+			  "H1_AP_INT_ODL",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "",</div><div class='add'>+			  "MSDC0_CMD",</div><div class='add'>+			  "MSDC0_DAT0",</div><div class='add'>+			  "MSDC0_DAT2",</div><div class='add'>+			  "MSDC0_DAT4",</div><div class='add'>+			  "MSDC0_DAT6",</div><div class='add'>+			  "MSDC0_DAT1",</div><div class='add'>+			  "MSDC0_DAT5",</div><div class='add'>+			  "MSDC0_DAT7",</div><div class='add'>+			  "MSDC0_DSL",</div><div class='add'>+			  "MSDC0_CLK",</div><div class='add'>+			  "MSDC0_DAT3",</div><div class='add'>+			  "MSDC0_RST_L",</div><div class='add'>+			  "SCP_VREQ_VAO",</div><div class='add'>+			  "AUD_DAT_MOSI2",</div><div class='add'>+			  "AUD_NLE_MOSI1",</div><div class='add'>+			  "AUD_NLE_MOSI0",</div><div class='add'>+			  "AUD_DAT_MISO2",</div><div class='add'>+			  "AP_I2C_SAR_SDA",</div><div class='add'>+			  "AP_I2C_SAR_SCL",</div><div class='add'>+			  "AP_I2C_PWR_SCL",</div><div class='add'>+			  "AP_I2C_PWR_SDA",</div><div class='add'>+			  "AP_I2C_TS_SCL_1V8",</div><div class='add'>+			  "AP_I2C_TS_SDA_1V8",</div><div class='add'>+			  "SRCLKENA0",</div><div class='add'>+			  "SRCLKENA1",</div><div class='add'>+			  "AP_EC_WATCHDOG_L",</div><div class='add'>+			  "PWRAP_SPI0_MI",</div><div class='add'>+			  "PWRAP_SPI0_CSN",</div><div class='add'>+			  "PWRAP_SPI0_MO",</div><div class='add'>+			  "PWRAP_SPI0_CK",</div><div class='add'>+			  "AP_RTC_CLK32K",</div><div class='add'>+			  "AUD_CLK_MOSI",</div><div class='add'>+			  "AUD_SYNC_MOSI",</div><div class='add'>+			  "AUD_DAT_MOSI0",</div><div class='add'>+			  "AUD_DAT_MOSI1",</div><div class='add'>+			  "AUD_DAT_MISO0",</div><div class='add'>+			  "AUD_DAT_MISO1";</div><div class='add'>+</div><div class='add'>+	anx7625_pins: anx7625-default-pins {</div><div class='add'>+		pins-out {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO41__FUNC_GPIO41&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO42__FUNC_GPIO42&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-in {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO6__FUNC_GPIO6&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_clk_mosi_off_pins: aud-clk-mosi-off-pins {</div><div class='add'>+		pins-mosi-off {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO214__FUNC_GPIO214&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO215__FUNC_GPIO215&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_clk_mosi_on_pins: aud-clk-mosi-on-pins {</div><div class='add'>+		pins-mosi-on {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO214__FUNC_AUD_CLK_MOSI&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO215__FUNC_AUD_SYNC_MOSI&gt;;</div><div class='add'>+			drive-strength = &lt;10&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_dat_miso_ch34_off_pins: aud-dat-miso-ch34-off-pins {</div><div class='add'>+		pins-miso-off {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO199__FUNC_GPIO199&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_dat_miso_ch34_on_pins: aud-dat-miso-ch34-on-pins {</div><div class='add'>+		pins-miso-on {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO199__FUNC_AUD_DAT_MISO2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_dat_miso_off_pins: aud-dat-miso-off-pins {</div><div class='add'>+		pins-miso-off {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO218__FUNC_GPIO218&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO219__FUNC_GPIO219&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_dat_miso_on_pins: aud-dat-miso-on-pins {</div><div class='add'>+		pins-miso-on {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO218__FUNC_AUD_DAT_MISO0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO219__FUNC_AUD_DAT_MISO1&gt;;</div><div class='add'>+			drive-strength = &lt;10&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_dat_miso2_off_pins: aud-dat-miso2-off-pins {</div><div class='add'>+		pins-miso-off {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO199__FUNC_GPIO199&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_dat_miso2_on_pins: aud-dat-miso2-on-pins {</div><div class='add'>+		pins-miso-on {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO199__FUNC_AUD_DAT_MISO2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_dat_mosi_ch34_off_pins: aud-dat-mosi-ch34-off-pins {</div><div class='add'>+		pins-mosi-off {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO196__FUNC_GPIO196&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_dat_mosi_ch34_on_pins: aud-dat-mosi-ch34-on-pins {</div><div class='add'>+		pins-mosi-on {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO196__FUNC_AUD_DAT_MOSI2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_dat_mosi_off_pins: aud-dat-mosi-off-pins {</div><div class='add'>+		pins-mosi-off {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO216__FUNC_GPIO216&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO217__FUNC_GPIO217&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_dat_mosi_on_pins: aud-dat-mosi-on-pins {</div><div class='add'>+		pins-mosi-on {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO216__FUNC_AUD_DAT_MOSI0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO217__FUNC_AUD_DAT_MOSI1&gt;;</div><div class='add'>+			drive-strength = &lt;10&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_gpio_i2s3_off_pins: aud-gpio-i2s3-off-pins {</div><div class='add'>+		pins-i2s3-off {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO32__FUNC_GPIO32&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO33__FUNC_GPIO33&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO35__FUNC_GPIO35&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_gpio_i2s3_on_pins: aud-gpio-i2s3-on-pins {</div><div class='add'>+		pins-i2s3-on {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO32__FUNC_I2S3_BCK&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO33__FUNC_I2S3_LRCK&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO35__FUNC_I2S3_DO&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_gpio_i2s8_off_pins: aud-gpio-i2s8-off-pins {</div><div class='add'>+		pins-i2s8-off {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO10__FUNC_GPIO10&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO11__FUNC_GPIO11&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO12__FUNC_GPIO12&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO13__FUNC_GPIO13&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_gpio_i2s8_on_pins: aud-gpio-i2s8-on-pins {</div><div class='add'>+		pins-i2s8-on {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO10__FUNC_I2S8_MCK&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO11__FUNC_I2S8_BCK&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO12__FUNC_I2S8_LRCK&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO13__FUNC_I2S8_DI&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_gpio_i2s9_off_pins: aud-gpio-i2s9-off-pins {</div><div class='add'>+		pins-i2s9-off {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO29__FUNC_GPIO29&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_gpio_i2s9_on_pins: aud-gpio-i2s9-on-pins {</div><div class='add'>+		pins-i2s9-on {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO29__FUNC_I2S9_DO&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_gpio_tdm_off_pins: aud-gpio-tdm-off-pins {</div><div class='add'>+		pins-tdm-off {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO0__FUNC_GPIO0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO1__FUNC_GPIO1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO2__FUNC_GPIO2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO3__FUNC_GPIO3&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_gpio_tdm_on_pins: aud-gpio-tdm-on-pins {</div><div class='add'>+		pins-tdm-on {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO0__FUNC_TDM_LRCK&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO1__FUNC_TDM_BCK&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO2__FUNC_TDM_MCK&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO3__FUNC_TDM_DATA0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_nle_mosi_off_pins: aud-nle-mosi-off-pins {</div><div class='add'>+		pins-nle-mosi-off {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO197__FUNC_GPIO197&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO198__FUNC_GPIO198&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_nle_mosi_on_pins: aud-nle-mosi-on-pins {</div><div class='add'>+		pins-nle-mosi-on {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO197__FUNC_AUD_NLE_MOSI1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO198__FUNC_AUD_NLE_MOSI0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cr50_int: cr50-irq-default-pins {</div><div class='add'>+		pins-gsc-ap-int-odl {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO171__FUNC_GPIO171&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cros_ec_int: cros-ec-irq-default-pins {</div><div class='add'>+		pins-ec-ap-int-odl {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO5__FUNC_GPIO5&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c0_pins: i2c0-default-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO204__FUNC_SCL0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO205__FUNC_SDA0&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PULL_SET_RSEL_011&gt;;</div><div class='add'>+			drive-strength-microamp = &lt;1000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c1_pins: i2c1-default-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO118__FUNC_SCL1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO119__FUNC_SDA1&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PULL_SET_RSEL_011&gt;;</div><div class='add'>+			drive-strength-microamp = &lt;1000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c2_pins: i2c2-default-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO141__FUNC_SCL2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO142__FUNC_SDA2&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PULL_SET_RSEL_011&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c3_pins: i2c3-default-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO160__FUNC_SCL3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO161__FUNC_SDA3&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+			drive-strength-microamp = &lt;1000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c7_pins: i2c7-default-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO124__FUNC_SCL7&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO125__FUNC_SDA7&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+			drive-strength-microamp = &lt;1000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc0_default_pins: mmc0-default-pins {</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO184__FUNC_MSDC0_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO188__FUNC_MSDC0_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO185__FUNC_MSDC0_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO193__FUNC_MSDC0_DAT3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO186__FUNC_MSDC0_DAT4&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO189__FUNC_MSDC0_DAT5&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO187__FUNC_MSDC0_DAT6&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO190__FUNC_MSDC0_DAT7&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO183__FUNC_MSDC0_CMD&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO192__FUNC_MSDC0_CLK&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-rst {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO194__FUNC_MSDC0_RSTB&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc0_uhs_pins: mmc0-uhs-pins {</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO184__FUNC_MSDC0_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO188__FUNC_MSDC0_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO185__FUNC_MSDC0_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO193__FUNC_MSDC0_DAT3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO186__FUNC_MSDC0_DAT4&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO189__FUNC_MSDC0_DAT5&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO187__FUNC_MSDC0_DAT6&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO190__FUNC_MSDC0_DAT7&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO183__FUNC_MSDC0_CMD&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;10&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO192__FUNC_MSDC0_CLK&gt;;</div><div class='add'>+			drive-strength = &lt;10&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-rst {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO194__FUNC_MSDC0_RSTB&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-ds {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO191__FUNC_MSDC0_DSL&gt;;</div><div class='add'>+			drive-strength = &lt;10&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc1_default_pins: mmc1-default-pins {</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO54__FUNC_MSDC1_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO56__FUNC_MSDC1_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO55__FUNC_MSDC1_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO53__FUNC_MSDC1_DAT3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO52__FUNC_MSDC1_CMD&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO51__FUNC_MSDC1_CLK&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-insert {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO17__FUNC_GPIO17&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc1_uhs_pins: mmc1-uhs-pins {</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO54__FUNC_MSDC1_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO56__FUNC_MSDC1_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO55__FUNC_MSDC1_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO53__FUNC_MSDC1_DAT3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO52__FUNC_MSDC1_CMD&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO51__FUNC_MSDC1_CLK&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	nor_flash_pins: nor-flash-default-pins {</div><div class='add'>+		pins-cs-io1 {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO24__FUNC_SPINOR_CS&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO28__FUNC_SPINOR_IO1&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+			drive-strength = &lt;10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-io0 {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO27__FUNC_SPINOR_IO0&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+			drive-strength = &lt;10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO25__FUNC_SPINOR_CK&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+			drive-strength = &lt;10&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie_pins: pcie-default-pins {</div><div class='add'>+		pins-pcie-wake {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO63__FUNC_PCIE_WAKE_N&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-pcie-pereset {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO64__FUNC_PCIE_PERESET_N&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-pcie-clkreq {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO65__FUNC_PCIE_CLKREQ_N&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-wifi-kill {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO145__FUNC_GPIO145&gt;; /* WIFI_KILL_L */</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pp1000_dpbrdg_en_pins: pp1000-dpbrdg-en-pins {</div><div class='add'>+		pins-en {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO19__FUNC_GPIO19&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pp1000_mipibrdg_en_pins: pp1000-mipibrdg-en-pins {</div><div class='add'>+		pins-en {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO129__FUNC_GPIO129&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pp1800_dpbrdg_en_pins: pp1800-dpbrdg-en-pins {</div><div class='add'>+		pins-en {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO126__FUNC_GPIO126&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pp1800_mipibrdg_en_pins: pp1800-mipibrd-en-pins {</div><div class='add'>+		pins-en {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO128__FUNC_GPIO128&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pp3300_dpbrdg_en_pins: pp3300-dpbrdg-en-pins {</div><div class='add'>+		pins-en {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO26__FUNC_GPIO26&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pp3300_mipibrdg_en_pins: pp3300-mipibrdg-en-pins {</div><div class='add'>+		pins-en {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO127__FUNC_GPIO127&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pp3300_wlan_pins: pp3300-wlan-pins {</div><div class='add'>+		pins-pcie-en-pp3300-wlan {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO143__FUNC_GPIO143&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pwm0_pins: pwm0-default-pins {</div><div class='add'>+		pins-pwm {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO40__FUNC_DISP_PWM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-inhibit {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO152__FUNC_GPIO152&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rt1015p_pins: rt1015p-default-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO147__FUNC_GPIO147&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	scp_pins: scp-pins {</div><div class='add'>+		pins-vreq-vao {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO195__FUNC_SCP_VREQ_VAO&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi1_pins: spi1-default-pins {</div><div class='add'>+		pins-cs-mosi-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO157__FUNC_SPI1_A_CSB&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO159__FUNC_SPI1_A_MO&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO156__FUNC_SPI1_A_CLK&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-miso {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO158__FUNC_SPI1_A_MI&gt;;</div><div class='add'>+			bias-pull-down;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi5_pins: spi5-default-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO38__FUNC_SPI5_A_MI&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO37__FUNC_GPIO37&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO39__FUNC_SPI5_A_MO&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO36__FUNC_SPI5_A_CLK&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	trackpad_pins: trackpad-default-pins {</div><div class='add'>+		pins-int-n {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO15__FUNC_GPIO15&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_11&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	touchscreen_pins: touchscreen-default-pins {</div><div class='add'>+		pins-irq {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO21__FUNC_GPIO21&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-reset {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO137__FUNC_GPIO137&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-report-sw {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO138__FUNC_GPIO138&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vow_clk_miso_off_pins: vow-clk-miso-off-pins {</div><div class='add'>+		pins-miso-off {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO219__FUNC_GPIO219&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vow_clk_miso_on_pins: vow-clk-miso-on-pins {</div><div class='add'>+		pins-miso-on {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO219__FUNC_VOW_CLK_MISO&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vow_dat_miso_off_pins: vow-dat-miso-off-pins {</div><div class='add'>+		pins-miso-off {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO218__FUNC_GPIO218&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vow_dat_miso_on_pins: vow-dat-miso-on-pins {</div><div class='add'>+		pins-miso-on {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO218__FUNC_VOW_DAT_MISO&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pmic {</div><div class='add'>+	interrupts-extended = &lt;&amp;pio 214 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm0_pins&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;scp {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	firmware-name = "mediatek/mt8192/scp.img";</div><div class='add'>+	memory-region = &lt;&amp;scp_mem_reserved&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;scp_pins&gt;;</div><div class='add'>+</div><div class='add'>+	cros-ec-rpmsg {</div><div class='add'>+		compatible = "google,cros-ec-rpmsg";</div><div class='add'>+		mediatek,rpmsg-name = "cros-ec-rpmsg";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mediatek,pad-select = &lt;0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;spi1_pins&gt;;</div><div class='add'>+</div><div class='add'>+	cros_ec: ec@0 {</div><div class='add'>+		compatible = "google,cros-ec-spi";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 5 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		spi-max-frequency = &lt;3000000&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;cros_ec_int&gt;;</div><div class='add'>+		wakeup-source;</div><div class='add'>+</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cros_ec_pwm: pwm {</div><div class='add'>+			compatible = "google,cros-ec-pwm";</div><div class='add'>+			#pwm-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c_tunnel: i2c-tunnel {</div><div class='add'>+			compatible = "google,cros-ec-i2c-tunnel";</div><div class='add'>+			google,remote-bus = &lt;0&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mt6360_ldo3_reg: regulator@0 {</div><div class='add'>+			compatible = "google,cros-ec-regulator";</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mt6360_ldo5_reg: regulator@1 {</div><div class='add'>+			compatible = "google,cros-ec-regulator";</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		typec {</div><div class='add'>+			compatible = "google,cros-ec-typec";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			usb_c0: connector@0 {</div><div class='add'>+				compatible = "usb-c-connector";</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				label = "left";</div><div class='add'>+				power-role = "dual";</div><div class='add'>+				data-role = "host";</div><div class='add'>+				try-power-role = "source";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			usb_c1: connector@1 {</div><div class='add'>+				compatible = "usb-c-connector";</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				label = "right";</div><div class='add'>+				power-role = "dual";</div><div class='add'>+				data-role = "host";</div><div class='add'>+				try-power-role = "source";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi5 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	cs-gpios = &lt;&amp;pio 37 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	mediatek,pad-select = &lt;0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;spi5_pins&gt;;</div><div class='add'>+</div><div class='add'>+	tpm@0 {</div><div class='add'>+		compatible = "google,cr50";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 171 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+		spi-max-frequency = &lt;1000000&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;cr50_int&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spmi {</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	mt6315_6: pmic@6 {</div><div class='add'>+		compatible = "mediatek,mt6315-regulator";</div><div class='add'>+		reg = &lt;0x6 SPMI_USID&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			mt6315_6_vbuck1: vbuck1 {</div><div class='add'>+				regulator-name = "Vbcpu";</div><div class='add'>+				regulator-min-microvolt = &lt;400000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1193750&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;256&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;0 1 2&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6315_6_vbuck3: vbuck3 {</div><div class='add'>+				regulator-name = "Vlcpu";</div><div class='add'>+				regulator-min-microvolt = &lt;400000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1193750&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;256&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;0 1 2&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mt6315_7: pmic@7 {</div><div class='add'>+		compatible = "mediatek,mt6315-regulator";</div><div class='add'>+		reg = &lt;0x7 SPMI_USID&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			mt6315_7_vbuck1: vbuck1 {</div><div class='add'>+				regulator-name = "Vgpu";</div><div class='add'>+				regulator-min-microvolt = &lt;400000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;800000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;256&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;0 1 2&gt;;</div><div class='add'>+				regulator-coupled-with = &lt;&amp;mt6359_vsram_others_ldo_reg&gt;;</div><div class='add'>+				regulator-coupled-max-spread = &lt;10000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xhci {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	wakeup-source;</div><div class='add'>+	vusb33-supply = &lt;&amp;pp3300_g&gt;;</div><div class='add'>+	vbus-supply = &lt;&amp;pp5000_a&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include &lt;arm/cros-ec-keyboard.dtsi&gt;</div><div class='add'>+#include &lt;arm/cros-ec-sbs.dtsi&gt;</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts<br/>new file mode 100644<br/>index 000000000000..808be492e970<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8192-evb.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8192-evb.dts</a></div><div class='hunk'>@@ -0,0 +1,30 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2020 MediaTek Inc.</div><div class='add'>+ * Author: Seiya Wang &lt;seiya.wang@mediatek.com&gt;</div><div class='add'>+ */</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8192.dtsi"</div><div class='add'>+#include "mt6359.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "MediaTek MT8192 evaluation board";</div><div class='add'>+	compatible = "mediatek,mt8192-evb", "mediatek,mt8192";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:921600n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0 0x40000000 0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi<br/>new file mode 100644<br/>index 000000000000..47dea10dd3b8<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8192.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8192.dtsi</a></div><div class='hunk'>@@ -0,0 +1,2377 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2020 MediaTek Inc.</div><div class='add'>+ * Author: Seiya Wang &lt;seiya.wang@mediatek.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include &lt;dt-bindings/clock/mt8192-clk.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gce/mt8192-gce.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/memory/mt8192-larb-port.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/mt8192-pinfunc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/phy/phy.h&gt;</div><div class='add'>+#include &lt;dt-bindings/power/mt8192-power.h&gt;</div><div class='add'>+#include &lt;dt-bindings/reset/mt8192-resets.h&gt;</div><div class='add'>+#include &lt;dt-bindings/thermal/thermal.h&gt;</div><div class='add'>+#include &lt;dt-bindings/thermal/mediatek,lvts-thermal.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "mediatek,mt8192";</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ovl0 = &amp;ovl0;</div><div class='add'>+		ovl-2l0 = &amp;ovl_2l0;</div><div class='add'>+		ovl-2l2 = &amp;ovl_2l2;</div><div class='add'>+		rdma0 = &amp;rdma0;</div><div class='add'>+		rdma4 = &amp;rdma4;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk13m: fixed-factor-clock-13m {</div><div class='add'>+		compatible = "fixed-factor-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk26m&gt;;</div><div class='add'>+		clock-div = &lt;2&gt;;</div><div class='add'>+		clock-mult = &lt;1&gt;;</div><div class='add'>+		clock-output-names = "clk13m";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk26m: oscillator0 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;26000000&gt;;</div><div class='add'>+		clock-output-names = "clk26m";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk32k: oscillator1 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;32768&gt;;</div><div class='add'>+		clock-output-names = "clk32k";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x000&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clock-frequency = &lt;1701000000&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_ret_l &amp;cpu_off_l&gt;;</div><div class='add'>+			i-cache-size = &lt;32768&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;128&gt;;</div><div class='add'>+			d-cache-size = &lt;32768&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;performance 0&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;427&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@100 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x100&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clock-frequency = &lt;1701000000&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_ret_l &amp;cpu_off_l&gt;;</div><div class='add'>+			i-cache-size = &lt;32768&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;128&gt;;</div><div class='add'>+			d-cache-size = &lt;32768&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;performance 0&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;427&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@200 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x200&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clock-frequency = &lt;1701000000&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_ret_l &amp;cpu_off_l&gt;;</div><div class='add'>+			i-cache-size = &lt;32768&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;128&gt;;</div><div class='add'>+			d-cache-size = &lt;32768&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;performance 0&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;427&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@300 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x300&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clock-frequency = &lt;1701000000&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_ret_l &amp;cpu_off_l&gt;;</div><div class='add'>+			i-cache-size = &lt;32768&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;128&gt;;</div><div class='add'>+			d-cache-size = &lt;32768&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;performance 0&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;427&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu4: cpu@400 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a76";</div><div class='add'>+			reg = &lt;0x400&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clock-frequency = &lt;2171000000&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_ret_b &amp;cpu_off_b&gt;;</div><div class='add'>+			i-cache-size = &lt;65536&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;65536&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_1&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;performance 1&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu5: cpu@500 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a76";</div><div class='add'>+			reg = &lt;0x500&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clock-frequency = &lt;2171000000&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_ret_b &amp;cpu_off_b&gt;;</div><div class='add'>+			i-cache-size = &lt;65536&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;65536&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_1&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;performance 1&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu6: cpu@600 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a76";</div><div class='add'>+			reg = &lt;0x600&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clock-frequency = &lt;2171000000&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_ret_b &amp;cpu_off_b&gt;;</div><div class='add'>+			i-cache-size = &lt;65536&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;65536&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_1&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;performance 1&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu7: cpu@700 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a76";</div><div class='add'>+			reg = &lt;0x700&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			clock-frequency = &lt;2171000000&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_ret_b &amp;cpu_off_b&gt;;</div><div class='add'>+			i-cache-size = &lt;65536&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;65536&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_1&gt;;</div><div class='add'>+			performance-domains = &lt;&amp;performance 1&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu-map {</div><div class='add'>+			cluster0 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu0&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu1&gt;;</div><div class='add'>+				};</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu2&gt;;</div><div class='add'>+				};</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu3&gt;;</div><div class='add'>+				};</div><div class='add'>+				core4 {</div><div class='add'>+					cpu = &lt;&amp;cpu4&gt;;</div><div class='add'>+				};</div><div class='add'>+				core5 {</div><div class='add'>+					cpu = &lt;&amp;cpu5&gt;;</div><div class='add'>+				};</div><div class='add'>+				core6 {</div><div class='add'>+					cpu = &lt;&amp;cpu6&gt;;</div><div class='add'>+				};</div><div class='add'>+				core7 {</div><div class='add'>+					cpu = &lt;&amp;cpu7&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_0: l2-cache0 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-size = &lt;131072&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;512&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l3_0&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_1: l2-cache1 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-size = &lt;262144&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;512&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l3_0&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l3_0: l3-cache {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;3&gt;;</div><div class='add'>+			cache-size = &lt;2097152&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;2048&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		idle-states {</div><div class='add'>+			entry-method = "psci";</div><div class='add'>+			cpu_ret_l: cpu-retention-l {</div><div class='add'>+				compatible = "arm,idle-state";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x00010001&gt;;</div><div class='add'>+				local-timer-stop;</div><div class='add'>+				entry-latency-us = &lt;55&gt;;</div><div class='add'>+				exit-latency-us = &lt;140&gt;;</div><div class='add'>+				min-residency-us = &lt;780&gt;;</div><div class='add'>+			};</div><div class='add'>+			cpu_ret_b: cpu-retention-b {</div><div class='add'>+				compatible = "arm,idle-state";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x00010001&gt;;</div><div class='add'>+				local-timer-stop;</div><div class='add'>+				entry-latency-us = &lt;35&gt;;</div><div class='add'>+				exit-latency-us = &lt;145&gt;;</div><div class='add'>+				min-residency-us = &lt;720&gt;;</div><div class='add'>+			};</div><div class='add'>+			cpu_off_l: cpu-off-l {</div><div class='add'>+				compatible = "arm,idle-state";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x01010002&gt;;</div><div class='add'>+				local-timer-stop;</div><div class='add'>+				entry-latency-us = &lt;60&gt;;</div><div class='add'>+				exit-latency-us = &lt;155&gt;;</div><div class='add'>+				min-residency-us = &lt;860&gt;;</div><div class='add'>+			};</div><div class='add'>+			cpu_off_b: cpu-off-b {</div><div class='add'>+				compatible = "arm,idle-state";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x01010002&gt;;</div><div class='add'>+				local-timer-stop;</div><div class='add'>+				entry-latency-us = &lt;40&gt;;</div><div class='add'>+				exit-latency-us = &lt;155&gt;;</div><div class='add'>+				min-residency-us = &lt;780&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu-a55 {</div><div class='add'>+		compatible = "arm,cortex-a55-pmu";</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &amp;ppi_cluster0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu-a76 {</div><div class='add'>+		compatible = "arm,cortex-a76-pmu";</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &amp;ppi_cluster1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-1.0";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer: timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+		clock-frequency = &lt;13000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpu_opp_table: opp-table-0 {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+		opp-shared;</div><div class='add'>+</div><div class='add'>+		opp-358000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;358000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;606250&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-399000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;399000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;618750&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-440000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;440000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;631250&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-482000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;482000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;643750&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-523000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;523000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;656250&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-564000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;564000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;668750&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-605000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;605000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;681250&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-647000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;647000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;693750&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-688000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;688000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;706250&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-724000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;724000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;725000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-748000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;748000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;737500&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-772000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;772000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;750000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-795000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;795000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;762500&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-819000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;819000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;775000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-843000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;843000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;787500&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-866000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;866000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;800000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		dma-ranges = &lt;0x0 0x0 0x0 0x0 0x4 0x0&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		performance: performance-controller@11bc10 {</div><div class='add'>+			compatible = "mediatek,cpufreq-hw";</div><div class='add'>+			reg = &lt;0 0x0011bc10 0 0x120&gt;, &lt;0 0x0011bd30 0 0x120&gt;;</div><div class='add'>+			#performance-domain-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@c000000 {</div><div class='add'>+			compatible = "arm,gic-v3";</div><div class='add'>+			#interrupt-cells = &lt;4&gt;;</div><div class='add'>+			#redistributor-regions = &lt;1&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			reg = &lt;0 0x0c000000 0 0x40000&gt;,</div><div class='add'>+			      &lt;0 0x0c040000 0 0x200000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+</div><div class='add'>+			ppi-partitions {</div><div class='add'>+				ppi_cluster0: interrupt-partition-0 {</div><div class='add'>+					affinity = &lt;&amp;cpu0 &amp;cpu1 &amp;cpu2 &amp;cpu3&gt;;</div><div class='add'>+				};</div><div class='add'>+				ppi_cluster1: interrupt-partition-1 {</div><div class='add'>+					affinity = &lt;&amp;cpu4 &amp;cpu5 &amp;cpu6 &amp;cpu7&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		topckgen: syscon@10000000 {</div><div class='add'>+			compatible = "mediatek,mt8192-topckgen", "syscon";</div><div class='add'>+			reg = &lt;0 0x10000000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		infracfg: syscon@10001000 {</div><div class='add'>+			compatible = "mediatek,mt8192-infracfg", "syscon";</div><div class='add'>+			reg = &lt;0 0x10001000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pericfg: syscon@10003000 {</div><div class='add'>+			compatible = "mediatek,mt8192-pericfg", "syscon";</div><div class='add'>+			reg = &lt;0 0x10003000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pio: pinctrl@10005000 {</div><div class='add'>+			compatible = "mediatek,mt8192-pinctrl";</div><div class='add'>+			reg = &lt;0 0x10005000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11c20000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11d10000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11d30000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11d40000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11e20000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11e70000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11ea0000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11f20000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11f30000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x1000b000 0 0x1000&gt;;</div><div class='add'>+			reg-names = "iocfg0", "iocfg_rm", "iocfg_bm",</div><div class='add'>+				    "iocfg_bl", "iocfg_br", "iocfg_lm",</div><div class='add'>+				    "iocfg_lb", "iocfg_rt", "iocfg_lt",</div><div class='add'>+				    "iocfg_tl", "eint";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;pio 0 0 220&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			interrupts = &lt;GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		scpsys: syscon@10006000 {</div><div class='add'>+			compatible = "mediatek,mt8192-scpsys", "syscon", "simple-mfd";</div><div class='add'>+			reg = &lt;0 0x10006000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			/* System Power Manager */</div><div class='add'>+			spm: power-controller {</div><div class='add'>+				compatible = "mediatek,mt8192-power-controller";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				/* power domain of the SoC */</div><div class='add'>+				power-domain@MT8192_POWER_DOMAIN_AUDIO {</div><div class='add'>+					reg = &lt;MT8192_POWER_DOMAIN_AUDIO&gt;;</div><div class='add'>+					clocks = &lt;&amp;topckgen CLK_TOP_AUD_INTBUS_SEL&gt;,</div><div class='add'>+						 &lt;&amp;infracfg CLK_INFRA_AUDIO_26M_B&gt;,</div><div class='add'>+						 &lt;&amp;infracfg CLK_INFRA_AUDIO&gt;;</div><div class='add'>+					clock-names = "audio", "audio1", "audio2";</div><div class='add'>+					mediatek,infracfg = &lt;&amp;infracfg&gt;;</div><div class='add'>+					#power-domain-cells = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				power-domain@MT8192_POWER_DOMAIN_CONN {</div><div class='add'>+					reg = &lt;MT8192_POWER_DOMAIN_CONN&gt;;</div><div class='add'>+					clocks = &lt;&amp;infracfg CLK_INFRA_PMIC_CONN&gt;;</div><div class='add'>+					clock-names = "conn";</div><div class='add'>+					mediatek,infracfg = &lt;&amp;infracfg&gt;;</div><div class='add'>+					#power-domain-cells = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				mfg0: power-domain@MT8192_POWER_DOMAIN_MFG0 {</div><div class='add'>+					reg = &lt;MT8192_POWER_DOMAIN_MFG0&gt;;</div><div class='add'>+					clocks = &lt;&amp;topckgen CLK_TOP_MFG_PLL_SEL&gt;,</div><div class='add'>+						 &lt;&amp;topckgen CLK_TOP_MFG_REF_SEL&gt;;</div><div class='add'>+					clock-names = "mfg", "alt";</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+					#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					mfg1: power-domain@MT8192_POWER_DOMAIN_MFG1 {</div><div class='add'>+						reg = &lt;MT8192_POWER_DOMAIN_MFG1&gt;;</div><div class='add'>+						mediatek,infracfg = &lt;&amp;infracfg&gt;;</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+						#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						power-domain@MT8192_POWER_DOMAIN_MFG2 {</div><div class='add'>+							reg = &lt;MT8192_POWER_DOMAIN_MFG2&gt;;</div><div class='add'>+							#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						power-domain@MT8192_POWER_DOMAIN_MFG3 {</div><div class='add'>+							reg = &lt;MT8192_POWER_DOMAIN_MFG3&gt;;</div><div class='add'>+							#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						power-domain@MT8192_POWER_DOMAIN_MFG4 {</div><div class='add'>+							reg = &lt;MT8192_POWER_DOMAIN_MFG4&gt;;</div><div class='add'>+							#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						power-domain@MT8192_POWER_DOMAIN_MFG5 {</div><div class='add'>+							reg = &lt;MT8192_POWER_DOMAIN_MFG5&gt;;</div><div class='add'>+							#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						power-domain@MT8192_POWER_DOMAIN_MFG6 {</div><div class='add'>+							reg = &lt;MT8192_POWER_DOMAIN_MFG6&gt;;</div><div class='add'>+							#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				power-domain@MT8192_POWER_DOMAIN_DISP {</div><div class='add'>+					reg = &lt;MT8192_POWER_DOMAIN_DISP&gt;;</div><div class='add'>+					clocks = &lt;&amp;topckgen CLK_TOP_DISP_SEL&gt;,</div><div class='add'>+						 &lt;&amp;mmsys CLK_MM_SMI_INFRA&gt;,</div><div class='add'>+						 &lt;&amp;mmsys CLK_MM_SMI_COMMON&gt;,</div><div class='add'>+						 &lt;&amp;mmsys CLK_MM_SMI_GALS&gt;,</div><div class='add'>+						 &lt;&amp;mmsys CLK_MM_SMI_IOMMU&gt;;</div><div class='add'>+					clock-names = "disp", "disp-0", "disp-1", "disp-2",</div><div class='add'>+						      "disp-3";</div><div class='add'>+					mediatek,infracfg = &lt;&amp;infracfg&gt;;</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+					#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					power-domain@MT8192_POWER_DOMAIN_IPE {</div><div class='add'>+						reg = &lt;MT8192_POWER_DOMAIN_IPE&gt;;</div><div class='add'>+						clocks = &lt;&amp;topckgen CLK_TOP_IPE_SEL&gt;,</div><div class='add'>+							 &lt;&amp;ipesys CLK_IPE_LARB19&gt;,</div><div class='add'>+							 &lt;&amp;ipesys CLK_IPE_LARB20&gt;,</div><div class='add'>+							 &lt;&amp;ipesys CLK_IPE_SMI_SUBCOM&gt;,</div><div class='add'>+							 &lt;&amp;ipesys CLK_IPE_GALS&gt;;</div><div class='add'>+						clock-names = "ipe", "ipe-0", "ipe-1", "ipe-2",</div><div class='add'>+							      "ipe-3";</div><div class='add'>+						mediatek,infracfg = &lt;&amp;infracfg&gt;;</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					power-domain@MT8192_POWER_DOMAIN_ISP {</div><div class='add'>+						reg = &lt;MT8192_POWER_DOMAIN_ISP&gt;;</div><div class='add'>+						clocks = &lt;&amp;topckgen CLK_TOP_IMG1_SEL&gt;,</div><div class='add'>+							 &lt;&amp;imgsys CLK_IMG_LARB9&gt;,</div><div class='add'>+							 &lt;&amp;imgsys CLK_IMG_GALS&gt;;</div><div class='add'>+						clock-names = "isp", "isp-0", "isp-1";</div><div class='add'>+						mediatek,infracfg = &lt;&amp;infracfg&gt;;</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					power-domain@MT8192_POWER_DOMAIN_ISP2 {</div><div class='add'>+						reg = &lt;MT8192_POWER_DOMAIN_ISP2&gt;;</div><div class='add'>+						clocks = &lt;&amp;topckgen CLK_TOP_IMG2_SEL&gt;,</div><div class='add'>+							 &lt;&amp;imgsys2 CLK_IMG2_LARB11&gt;,</div><div class='add'>+							 &lt;&amp;imgsys2 CLK_IMG2_GALS&gt;;</div><div class='add'>+						clock-names = "isp2", "isp2-0", "isp2-1";</div><div class='add'>+						mediatek,infracfg = &lt;&amp;infracfg&gt;;</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					power-domain@MT8192_POWER_DOMAIN_MDP {</div><div class='add'>+						reg = &lt;MT8192_POWER_DOMAIN_MDP&gt;;</div><div class='add'>+						clocks = &lt;&amp;topckgen CLK_TOP_MDP_SEL&gt;,</div><div class='add'>+							 &lt;&amp;mdpsys CLK_MDP_SMI0&gt;;</div><div class='add'>+						clock-names = "mdp", "mdp-0";</div><div class='add'>+						mediatek,infracfg = &lt;&amp;infracfg&gt;;</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					power-domain@MT8192_POWER_DOMAIN_VENC {</div><div class='add'>+						reg = &lt;MT8192_POWER_DOMAIN_VENC&gt;;</div><div class='add'>+						clocks = &lt;&amp;topckgen CLK_TOP_VENC_SEL&gt;,</div><div class='add'>+							 &lt;&amp;vencsys CLK_VENC_SET1_VENC&gt;;</div><div class='add'>+						clock-names = "venc", "venc-0";</div><div class='add'>+						mediatek,infracfg = &lt;&amp;infracfg&gt;;</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					power-domain@MT8192_POWER_DOMAIN_VDEC {</div><div class='add'>+						reg = &lt;MT8192_POWER_DOMAIN_VDEC&gt;;</div><div class='add'>+						clocks = &lt;&amp;topckgen CLK_TOP_VDEC_SEL&gt;,</div><div class='add'>+							 &lt;&amp;vdecsys_soc CLK_VDEC_SOC_VDEC&gt;,</div><div class='add'>+							 &lt;&amp;vdecsys_soc CLK_VDEC_SOC_LAT&gt;,</div><div class='add'>+							 &lt;&amp;vdecsys_soc CLK_VDEC_SOC_LARB1&gt;;</div><div class='add'>+						clock-names = "vdec", "vdec-0", "vdec-1", "vdec-2";</div><div class='add'>+						mediatek,infracfg = &lt;&amp;infracfg&gt;;</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+						#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						power-domain@MT8192_POWER_DOMAIN_VDEC2 {</div><div class='add'>+							reg = &lt;MT8192_POWER_DOMAIN_VDEC2&gt;;</div><div class='add'>+							clocks = &lt;&amp;vdecsys CLK_VDEC_VDEC&gt;,</div><div class='add'>+								 &lt;&amp;vdecsys CLK_VDEC_LAT&gt;,</div><div class='add'>+								 &lt;&amp;vdecsys CLK_VDEC_LARB1&gt;;</div><div class='add'>+							clock-names = "vdec2-0", "vdec2-1",</div><div class='add'>+								      "vdec2-2";</div><div class='add'>+							#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					power-domain@MT8192_POWER_DOMAIN_CAM {</div><div class='add'>+						reg = &lt;MT8192_POWER_DOMAIN_CAM&gt;;</div><div class='add'>+						clocks = &lt;&amp;topckgen CLK_TOP_CAM_SEL&gt;,</div><div class='add'>+							 &lt;&amp;camsys CLK_CAM_LARB13&gt;,</div><div class='add'>+							 &lt;&amp;camsys CLK_CAM_LARB14&gt;,</div><div class='add'>+							 &lt;&amp;camsys CLK_CAM_CCU_GALS&gt;,</div><div class='add'>+							 &lt;&amp;camsys CLK_CAM_CAM2MM_GALS&gt;;</div><div class='add'>+						clock-names = "cam", "cam-0", "cam-1", "cam-2",</div><div class='add'>+							      "cam-3";</div><div class='add'>+						mediatek,infracfg = &lt;&amp;infracfg&gt;;</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+						#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						power-domain@MT8192_POWER_DOMAIN_CAM_RAWA {</div><div class='add'>+							reg = &lt;MT8192_POWER_DOMAIN_CAM_RAWA&gt;;</div><div class='add'>+							clocks = &lt;&amp;camsys_rawa CLK_CAM_RAWA_LARBX&gt;;</div><div class='add'>+							clock-names = "cam_rawa-0";</div><div class='add'>+							#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						power-domain@MT8192_POWER_DOMAIN_CAM_RAWB {</div><div class='add'>+							reg = &lt;MT8192_POWER_DOMAIN_CAM_RAWB&gt;;</div><div class='add'>+							clocks = &lt;&amp;camsys_rawb CLK_CAM_RAWB_LARBX&gt;;</div><div class='add'>+							clock-names = "cam_rawb-0";</div><div class='add'>+							#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						power-domain@MT8192_POWER_DOMAIN_CAM_RAWC {</div><div class='add'>+							reg = &lt;MT8192_POWER_DOMAIN_CAM_RAWC&gt;;</div><div class='add'>+							clocks = &lt;&amp;camsys_rawc CLK_CAM_RAWC_LARBX&gt;;</div><div class='add'>+							clock-names = "cam_rawc-0";</div><div class='add'>+							#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		watchdog: watchdog@10007000 {</div><div class='add'>+			compatible = "mediatek,mt8192-wdt";</div><div class='add'>+			reg = &lt;0 0x10007000 0 0x100&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		apmixedsys: syscon@1000c000 {</div><div class='add'>+			compatible = "mediatek,mt8192-apmixedsys", "syscon";</div><div class='add'>+			reg = &lt;0 0x1000c000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		systimer: timer@10017000 {</div><div class='add'>+			compatible = "mediatek,mt8192-timer",</div><div class='add'>+				     "mediatek,mt6765-timer";</div><div class='add'>+			reg = &lt;0 0x10017000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk13m&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pwrap: pwrap@10026000 {</div><div class='add'>+			compatible = "mediatek,mt6873-pwrap";</div><div class='add'>+			reg = &lt;0 0x10026000 0 0x1000&gt;;</div><div class='add'>+			reg-names = "pwrap";</div><div class='add'>+			interrupts = &lt;GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_PMIC_AP&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_PMIC_TMR&gt;;</div><div class='add'>+			clock-names = "spi", "wrap";</div><div class='add'>+			assigned-clocks = &lt;&amp;topckgen CLK_TOP_PWRAP_ULPOSC_SEL&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_OSC_D10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spmi: spmi@10027000 {</div><div class='add'>+			compatible = "mediatek,mt6873-spmi";</div><div class='add'>+			reg = &lt;0 0x10027000 0 0x000e00&gt;,</div><div class='add'>+			      &lt;0 0x10029000 0 0x000100&gt;;</div><div class='add'>+			reg-names = "pmif", "spmimst";</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_PMIC_AP&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_PMIC_TMR&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SPMI_MST_SEL&gt;;</div><div class='add'>+			clock-names = "pmif_sys_ck",</div><div class='add'>+				      "pmif_tmr_ck",</div><div class='add'>+				      "spmimst_clk_mux";</div><div class='add'>+			assigned-clocks = &lt;&amp;topckgen CLK_TOP_PWRAP_ULPOSC_SEL&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_OSC_D10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gce: mailbox@10228000 {</div><div class='add'>+			compatible = "mediatek,mt8192-gce";</div><div class='add'>+			reg = &lt;0 0x10228000 0 0x4000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			#mbox-cells = &lt;2&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_GCE&gt;;</div><div class='add'>+			clock-names = "gce";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		scp_adsp: clock-controller@10720000 {</div><div class='add'>+			compatible = "mediatek,mt8192-scp_adsp";</div><div class='add'>+			reg = &lt;0 0x10720000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			/* power domain dependency not upstreamed */</div><div class='add'>+			status = "fail";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart0: serial@11002000 {</div><div class='add'>+			compatible = "mediatek,mt8192-uart",</div><div class='add'>+				     "mediatek,mt6577-uart";</div><div class='add'>+			reg = &lt;0 0x11002000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk26m&gt;, &lt;&amp;infracfg CLK_INFRA_UART0&gt;;</div><div class='add'>+			clock-names = "baud", "bus";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart1: serial@11003000 {</div><div class='add'>+			compatible = "mediatek,mt8192-uart",</div><div class='add'>+				     "mediatek,mt6577-uart";</div><div class='add'>+			reg = &lt;0 0x11003000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk26m&gt;, &lt;&amp;infracfg CLK_INFRA_UART1&gt;;</div><div class='add'>+			clock-names = "baud", "bus";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		imp_iic_wrap_c: clock-controller@11007000 {</div><div class='add'>+			compatible = "mediatek,mt8192-imp_iic_wrap_c";</div><div class='add'>+			reg = &lt;0 0x11007000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi0: spi@1100a000 {</div><div class='add'>+			compatible = "mediatek,mt8192-spi",</div><div class='add'>+				     "mediatek,mt6765-spi";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0 0x1100a000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_MAINPLL_D5_D4&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SPI_SEL&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_SPI0&gt;;</div><div class='add'>+			clock-names = "parent-clk", "sel-clk", "spi-clk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		lvts_ap: thermal-sensor@1100b000 {</div><div class='add'>+			compatible = "mediatek,mt8192-lvts-ap";</div><div class='add'>+			reg = &lt;0 0x1100b000 0 0xc00&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_THERM&gt;;</div><div class='add'>+			resets = &lt;&amp;infracfg MT8192_INFRA_RST0_THERM_CTRL_SWRST&gt;;</div><div class='add'>+			nvmem-cells = &lt;&amp;lvts_e_data1&gt;;</div><div class='add'>+			nvmem-cell-names = "lvts-calib-data-1";</div><div class='add'>+			#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		svs: svs@1100bc00 {</div><div class='add'>+			compatible = "mediatek,mt8192-svs";</div><div class='add'>+			reg = &lt;0 0x1100bc00 0 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_THERM&gt;;</div><div class='add'>+			clock-names = "main";</div><div class='add'>+			nvmem-cells = &lt;&amp;svs_calibration&gt;, &lt;&amp;lvts_e_data1&gt;;</div><div class='add'>+			nvmem-cell-names = "svs-calibration-data", "t-calibration-data";</div><div class='add'>+			resets = &lt;&amp;infracfg MT8192_INFRA_RST3_THERM_CTRL_PTP_SWRST&gt;;</div><div class='add'>+			reset-names = "svs_rst";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pwm0: pwm@1100e000 {</div><div class='add'>+			compatible = "mediatek,mt8183-disp-pwm";</div><div class='add'>+			reg = &lt;0 0x1100e000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			#pwm-cells = &lt;2&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_DISP_PWM_SEL&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_DISP_PWM&gt;;</div><div class='add'>+			clock-names = "main", "mm";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi1: spi@11010000 {</div><div class='add'>+			compatible = "mediatek,mt8192-spi",</div><div class='add'>+				     "mediatek,mt6765-spi";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0 0x11010000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_MAINPLL_D5_D4&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SPI_SEL&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_SPI1&gt;;</div><div class='add'>+			clock-names = "parent-clk", "sel-clk", "spi-clk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi2: spi@11012000 {</div><div class='add'>+			compatible = "mediatek,mt8192-spi",</div><div class='add'>+				     "mediatek,mt6765-spi";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0 0x11012000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_MAINPLL_D5_D4&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SPI_SEL&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_SPI2&gt;;</div><div class='add'>+			clock-names = "parent-clk", "sel-clk", "spi-clk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi3: spi@11013000 {</div><div class='add'>+			compatible = "mediatek,mt8192-spi",</div><div class='add'>+				     "mediatek,mt6765-spi";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0 0x11013000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_MAINPLL_D5_D4&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SPI_SEL&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_SPI3&gt;;</div><div class='add'>+			clock-names = "parent-clk", "sel-clk", "spi-clk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi4: spi@11018000 {</div><div class='add'>+			compatible = "mediatek,mt8192-spi",</div><div class='add'>+				     "mediatek,mt6765-spi";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0 0x11018000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_MAINPLL_D5_D4&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SPI_SEL&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_SPI4&gt;;</div><div class='add'>+			clock-names = "parent-clk", "sel-clk", "spi-clk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi5: spi@11019000 {</div><div class='add'>+			compatible = "mediatek,mt8192-spi",</div><div class='add'>+				     "mediatek,mt6765-spi";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0 0x11019000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_MAINPLL_D5_D4&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SPI_SEL&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_SPI5&gt;;</div><div class='add'>+			clock-names = "parent-clk", "sel-clk", "spi-clk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi6: spi@1101d000 {</div><div class='add'>+			compatible = "mediatek,mt8192-spi",</div><div class='add'>+				     "mediatek,mt6765-spi";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0 0x1101d000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_MAINPLL_D5_D4&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SPI_SEL&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_SPI6&gt;;</div><div class='add'>+			clock-names = "parent-clk", "sel-clk", "spi-clk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi7: spi@1101e000 {</div><div class='add'>+			compatible = "mediatek,mt8192-spi",</div><div class='add'>+				     "mediatek,mt6765-spi";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0 0x1101e000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_MAINPLL_D5_D4&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SPI_SEL&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_SPI7&gt;;</div><div class='add'>+			clock-names = "parent-clk", "sel-clk", "spi-clk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		scp: scp@10500000 {</div><div class='add'>+			compatible = "mediatek,mt8192-scp";</div><div class='add'>+			reg = &lt;0 0x10500000 0 0x100000&gt;,</div><div class='add'>+			      &lt;0 0x10720000 0 0xe0000&gt;,</div><div class='add'>+			      &lt;0 0x10700000 0 0x8000&gt;;</div><div class='add'>+			reg-names = "sram", "cfg", "l1tcm";</div><div class='add'>+			interrupts = &lt;GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_SCPSYS&gt;;</div><div class='add'>+			clock-names = "main";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		xhci: usb@11200000 {</div><div class='add'>+			compatible = "mediatek,mt8192-xhci",</div><div class='add'>+				     "mediatek,mtk-xhci";</div><div class='add'>+			reg = &lt;0 0x11200000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11203e00 0 0x0100&gt;;</div><div class='add'>+			reg-names = "mac", "ippc";</div><div class='add'>+			interrupts-extended = &lt;&amp;gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			interrupt-names = "host";</div><div class='add'>+			phys = &lt;&amp;u2port0 PHY_TYPE_USB2&gt;,</div><div class='add'>+			       &lt;&amp;u3port0 PHY_TYPE_USB3&gt;;</div><div class='add'>+			assigned-clocks = &lt;&amp;topckgen CLK_TOP_USB_TOP_SEL&gt;,</div><div class='add'>+					  &lt;&amp;topckgen CLK_TOP_SSUSB_XHCI_SEL&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_UNIVPLL_D5_D4&gt;,</div><div class='add'>+						 &lt;&amp;topckgen CLK_TOP_UNIVPLL_D5_D4&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_SSUSB&gt;,</div><div class='add'>+				 &lt;&amp;apmixedsys CLK_APMIXED_USBPLL&gt;,</div><div class='add'>+				 &lt;&amp;clk26m&gt;,</div><div class='add'>+				 &lt;&amp;clk26m&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_SSUSB_XHCI&gt;;</div><div class='add'>+			clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",</div><div class='add'>+				      "xhci_ck";</div><div class='add'>+			wakeup-source;</div><div class='add'>+			mediatek,syscon-wakeup = &lt;&amp;pericfg 0x420 102&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		audsys: syscon@11210000 {</div><div class='add'>+			compatible = "mediatek,mt8192-audsys", "syscon";</div><div class='add'>+			reg = &lt;0 0x11210000 0 0x2000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			afe: mt8192-afe-pcm {</div><div class='add'>+				compatible = "mediatek,mt8192-audio";</div><div class='add'>+				interrupts = &lt;GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				resets = &lt;&amp;watchdog 17&gt;;</div><div class='add'>+				reset-names = "audiosys";</div><div class='add'>+				mediatek,apmixedsys = &lt;&amp;apmixedsys&gt;;</div><div class='add'>+				mediatek,infracfg = &lt;&amp;infracfg&gt;;</div><div class='add'>+				mediatek,topckgen = &lt;&amp;topckgen&gt;;</div><div class='add'>+				power-domains = &lt;&amp;spm MT8192_POWER_DOMAIN_AUDIO&gt;;</div><div class='add'>+				clocks = &lt;&amp;audsys CLK_AUD_AFE&gt;,</div><div class='add'>+					 &lt;&amp;audsys CLK_AUD_DAC&gt;,</div><div class='add'>+					 &lt;&amp;audsys CLK_AUD_DAC_PREDIS&gt;,</div><div class='add'>+					 &lt;&amp;audsys CLK_AUD_ADC&gt;,</div><div class='add'>+					 &lt;&amp;audsys CLK_AUD_ADDA6_ADC&gt;,</div><div class='add'>+					 &lt;&amp;audsys CLK_AUD_22M&gt;,</div><div class='add'>+					 &lt;&amp;audsys CLK_AUD_24M&gt;,</div><div class='add'>+					 &lt;&amp;audsys CLK_AUD_APLL_TUNER&gt;,</div><div class='add'>+					 &lt;&amp;audsys CLK_AUD_APLL2_TUNER&gt;,</div><div class='add'>+					 &lt;&amp;audsys CLK_AUD_TDM&gt;,</div><div class='add'>+					 &lt;&amp;audsys CLK_AUD_TML&gt;,</div><div class='add'>+					 &lt;&amp;audsys CLK_AUD_NLE&gt;,</div><div class='add'>+					 &lt;&amp;audsys CLK_AUD_DAC_HIRES&gt;,</div><div class='add'>+					 &lt;&amp;audsys CLK_AUD_ADC_HIRES&gt;,</div><div class='add'>+					 &lt;&amp;audsys CLK_AUD_ADC_HIRES_TML&gt;,</div><div class='add'>+					 &lt;&amp;audsys CLK_AUD_ADDA6_ADC_HIRES&gt;,</div><div class='add'>+					 &lt;&amp;audsys CLK_AUD_3RD_DAC&gt;,</div><div class='add'>+					 &lt;&amp;audsys CLK_AUD_3RD_DAC_PREDIS&gt;,</div><div class='add'>+					 &lt;&amp;audsys CLK_AUD_3RD_DAC_TML&gt;,</div><div class='add'>+					 &lt;&amp;audsys CLK_AUD_3RD_DAC_HIRES&gt;,</div><div class='add'>+					 &lt;&amp;infracfg CLK_INFRA_AUDIO&gt;,</div><div class='add'>+					 &lt;&amp;infracfg CLK_INFRA_AUDIO_26M_B&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_AUDIO_SEL&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_AUD_INTBUS_SEL&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_MAINPLL_D4_D4&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_AUD_1_SEL&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_APLL1&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_AUD_2_SEL&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_APLL2&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_AUD_ENGEN1_SEL&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_APLL1_D4&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_AUD_ENGEN2_SEL&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_APLL2_D4&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_APLL_I2S0_M_SEL&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_APLL_I2S1_M_SEL&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_APLL_I2S2_M_SEL&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_APLL_I2S3_M_SEL&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_APLL_I2S4_M_SEL&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_APLL_I2S5_M_SEL&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_APLL_I2S6_M_SEL&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_APLL_I2S7_M_SEL&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_APLL_I2S8_M_SEL&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_APLL_I2S9_M_SEL&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_APLL12_DIV0&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_APLL12_DIV1&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_APLL12_DIV2&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_APLL12_DIV3&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_APLL12_DIV4&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_APLL12_DIVB&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_APLL12_DIV5&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_APLL12_DIV6&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_APLL12_DIV7&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_APLL12_DIV8&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_APLL12_DIV9&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_AUDIO_H_SEL&gt;,</div><div class='add'>+					 &lt;&amp;clk26m&gt;;</div><div class='add'>+				clock-names = "aud_afe_clk",</div><div class='add'>+					      "aud_dac_clk",</div><div class='add'>+					      "aud_dac_predis_clk",</div><div class='add'>+					      "aud_adc_clk",</div><div class='add'>+					      "aud_adda6_adc_clk",</div><div class='add'>+					      "aud_apll22m_clk",</div><div class='add'>+					      "aud_apll24m_clk",</div><div class='add'>+					      "aud_apll1_tuner_clk",</div><div class='add'>+					      "aud_apll2_tuner_clk",</div><div class='add'>+					      "aud_tdm_clk",</div><div class='add'>+					      "aud_tml_clk",</div><div class='add'>+					      "aud_nle",</div><div class='add'>+					      "aud_dac_hires_clk",</div><div class='add'>+					      "aud_adc_hires_clk",</div><div class='add'>+					      "aud_adc_hires_tml",</div><div class='add'>+					      "aud_adda6_adc_hires_clk",</div><div class='add'>+					      "aud_3rd_dac_clk",</div><div class='add'>+					      "aud_3rd_dac_predis_clk",</div><div class='add'>+					      "aud_3rd_dac_tml",</div><div class='add'>+					      "aud_3rd_dac_hires_clk",</div><div class='add'>+					      "aud_infra_clk",</div><div class='add'>+					      "aud_infra_26m_clk",</div><div class='add'>+					      "top_mux_audio",</div><div class='add'>+					      "top_mux_audio_int",</div><div class='add'>+					      "top_mainpll_d4_d4",</div><div class='add'>+					      "top_mux_aud_1",</div><div class='add'>+					      "top_apll1_ck",</div><div class='add'>+					      "top_mux_aud_2",</div><div class='add'>+					      "top_apll2_ck",</div><div class='add'>+					      "top_mux_aud_eng1",</div><div class='add'>+					      "top_apll1_d4",</div><div class='add'>+					      "top_mux_aud_eng2",</div><div class='add'>+					      "top_apll2_d4",</div><div class='add'>+					      "top_i2s0_m_sel",</div><div class='add'>+					      "top_i2s1_m_sel",</div><div class='add'>+					      "top_i2s2_m_sel",</div><div class='add'>+					      "top_i2s3_m_sel",</div><div class='add'>+					      "top_i2s4_m_sel",</div><div class='add'>+					      "top_i2s5_m_sel",</div><div class='add'>+					      "top_i2s6_m_sel",</div><div class='add'>+					      "top_i2s7_m_sel",</div><div class='add'>+					      "top_i2s8_m_sel",</div><div class='add'>+					      "top_i2s9_m_sel",</div><div class='add'>+					      "top_apll12_div0",</div><div class='add'>+					      "top_apll12_div1",</div><div class='add'>+					      "top_apll12_div2",</div><div class='add'>+					      "top_apll12_div3",</div><div class='add'>+					      "top_apll12_div4",</div><div class='add'>+					      "top_apll12_divb",</div><div class='add'>+					      "top_apll12_div5",</div><div class='add'>+					      "top_apll12_div6",</div><div class='add'>+					      "top_apll12_div7",</div><div class='add'>+					      "top_apll12_div8",</div><div class='add'>+					      "top_apll12_div9",</div><div class='add'>+					      "top_mux_audio_h",</div><div class='add'>+					      "top_clk26m_clk";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie: pcie@11230000 {</div><div class='add'>+			compatible = "mediatek,mt8192-pcie";</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			reg = &lt;0 0x11230000 0 0x2000&gt;;</div><div class='add'>+			reg-names = "pcie-mac";</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_PCIE_PL_P_250M&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_PCIE_TL_26M&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_PCIE_TL_96M&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_PCIE_TL_32K&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_PCIE_PERI_26M&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_PCIE_TOP_H_133M&gt;;</div><div class='add'>+			clock-names = "pl_250m", "tl_26m", "tl_96m",</div><div class='add'>+				      "tl_32k", "peri_26m", "top_133m";</div><div class='add'>+			assigned-clocks = &lt;&amp;topckgen CLK_TOP_TL_SEL&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_MAINPLL_D6_D4&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			bus-range = &lt;0x00 0xff&gt;;</div><div class='add'>+			ranges = &lt;0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000&gt;,</div><div class='add'>+				 &lt;0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000&gt;;</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;pcie_intc0 0&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;pcie_intc0 1&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;pcie_intc0 2&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;pcie_intc0 3&gt;;</div><div class='add'>+</div><div class='add'>+			pcie_intc0: interrupt-controller {</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#address-cells = &lt;0&gt;;</div><div class='add'>+				#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nor_flash: spi@11234000 {</div><div class='add'>+			compatible = "mediatek,mt8192-nor";</div><div class='add'>+			reg = &lt;0 0x11234000 0 0xe0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_SFLASH_SEL&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_FLASHIF_SFLASH&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_FLASHIF_TOP_H_133M&gt;;</div><div class='add'>+			clock-names = "spi", "sf", "axi";</div><div class='add'>+			assigned-clocks = &lt;&amp;topckgen CLK_TOP_SFLASH_SEL&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;clk26m&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		lvts_mcu: thermal-sensor@11278000 {</div><div class='add'>+			compatible = "mediatek,mt8192-lvts-mcu";</div><div class='add'>+			reg = &lt;0 0x11278000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_INFRA_THERM&gt;;</div><div class='add'>+			resets = &lt;&amp;infracfg MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST&gt;;</div><div class='add'>+			nvmem-cells = &lt;&amp;lvts_e_data1&gt;;</div><div class='add'>+			nvmem-cell-names = "lvts-calib-data-1";</div><div class='add'>+			#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		efuse: efuse@11c10000 {</div><div class='add'>+			compatible = "mediatek,mt8192-efuse", "mediatek,efuse";</div><div class='add'>+			reg = &lt;0 0x11c10000 0 0x1000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			socinfo-data1@44 {</div><div class='add'>+				reg = &lt;0x044 0x4&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			socinfo-data2@50 {</div><div class='add'>+				reg = &lt;0x050 0x4&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lvts_e_data1: data1@1c0 {</div><div class='add'>+				reg = &lt;0x1c0 0x58&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			svs_calibration: calib@580 {</div><div class='add'>+				reg = &lt;0x580 0x68&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c3: i2c@11cb0000 {</div><div class='add'>+			compatible = "mediatek,mt8192-i2c";</div><div class='add'>+			reg = &lt;0 0x11cb0000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x10217300 0 0x80&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;imp_iic_wrap_e CLK_IMP_IIC_WRAP_E_I2C3&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_AP_DMA&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			clock-div = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		imp_iic_wrap_e: clock-controller@11cb1000 {</div><div class='add'>+			compatible = "mediatek,mt8192-imp_iic_wrap_e";</div><div class='add'>+			reg = &lt;0 0x11cb1000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c7: i2c@11d00000 {</div><div class='add'>+			compatible = "mediatek,mt8192-i2c";</div><div class='add'>+			reg = &lt;0 0x11d00000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x10217600 0 0x180&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_AP_DMA&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			clock-div = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c8: i2c@11d01000 {</div><div class='add'>+			compatible = "mediatek,mt8192-i2c";</div><div class='add'>+			reg = &lt;0 0x11d01000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x10217780 0 0x180&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C8&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_AP_DMA&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			clock-div = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c9: i2c@11d02000 {</div><div class='add'>+			compatible = "mediatek,mt8192-i2c";</div><div class='add'>+			reg = &lt;0 0x11d02000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x10217900 0 0x180&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C9&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_AP_DMA&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			clock-div = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		imp_iic_wrap_s: clock-controller@11d03000 {</div><div class='add'>+			compatible = "mediatek,mt8192-imp_iic_wrap_s";</div><div class='add'>+			reg = &lt;0 0x11d03000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c1: i2c@11d20000 {</div><div class='add'>+			compatible = "mediatek,mt8192-i2c";</div><div class='add'>+			reg = &lt;0 0x11d20000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x10217100 0 0x80&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C1&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_AP_DMA&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			clock-div = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c2: i2c@11d21000 {</div><div class='add'>+			compatible = "mediatek,mt8192-i2c";</div><div class='add'>+			reg = &lt;0 0x11d21000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x10217180 0 0x180&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C2&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_AP_DMA&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			clock-div = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c4: i2c@11d22000 {</div><div class='add'>+			compatible = "mediatek,mt8192-i2c";</div><div class='add'>+			reg = &lt;0 0x11d22000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x10217380 0 0x180&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C4&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_AP_DMA&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			clock-div = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		imp_iic_wrap_ws: clock-controller@11d23000 {</div><div class='add'>+			compatible = "mediatek,mt8192-imp_iic_wrap_ws";</div><div class='add'>+			reg = &lt;0 0x11d23000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c5: i2c@11e00000 {</div><div class='add'>+			compatible = "mediatek,mt8192-i2c";</div><div class='add'>+			reg = &lt;0 0x11e00000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x10217500 0 0x80&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C5&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_AP_DMA&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			clock-div = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		imp_iic_wrap_w: clock-controller@11e01000 {</div><div class='add'>+			compatible = "mediatek,mt8192-imp_iic_wrap_w";</div><div class='add'>+			reg = &lt;0 0x11e01000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		u3phy0: t-phy@11e40000 {</div><div class='add'>+			compatible = "mediatek,mt8192-tphy",</div><div class='add'>+				     "mediatek,generic-tphy-v2";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges = &lt;0x0 0x0 0x11e40000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			u2port0: usb-phy@0 {</div><div class='add'>+				reg = &lt;0x0 0x700&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk26m&gt;;</div><div class='add'>+				clock-names = "ref";</div><div class='add'>+				#phy-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			u3port0: usb-phy@700 {</div><div class='add'>+				reg = &lt;0x700 0x900&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk26m&gt;;</div><div class='add'>+				clock-names = "ref";</div><div class='add'>+				#phy-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mipi_tx0: dsi-phy@11e50000 {</div><div class='add'>+			compatible = "mediatek,mt8183-mipi-tx";</div><div class='add'>+			reg = &lt;0 0x11e50000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;apmixedsys CLK_APMIXED_MIPID26M&gt;;</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+			clock-output-names = "mipi_tx0_pll";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c0: i2c@11f00000 {</div><div class='add'>+			compatible = "mediatek,mt8192-i2c";</div><div class='add'>+			reg = &lt;0 0x11f00000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x10217080 0 0x80&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C0&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_AP_DMA&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			clock-div = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c6: i2c@11f01000 {</div><div class='add'>+			compatible = "mediatek,mt8192-i2c";</div><div class='add'>+			reg = &lt;0 0x11f01000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x10217580 0 0x80&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C6&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_INFRA_AP_DMA&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			clock-div = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		imp_iic_wrap_n: clock-controller@11f02000 {</div><div class='add'>+			compatible = "mediatek,mt8192-imp_iic_wrap_n";</div><div class='add'>+			reg = &lt;0 0x11f02000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		msdc_top: clock-controller@11f10000 {</div><div class='add'>+			compatible = "mediatek,mt8192-msdc_top";</div><div class='add'>+			reg = &lt;0 0x11f10000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmc0: mmc@11f60000 {</div><div class='add'>+			compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";</div><div class='add'>+			reg = &lt;0 0x11f60000 0 0x1000&gt;, &lt;0 0x11f50000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_MSDC50_0_SEL&gt;,</div><div class='add'>+				 &lt;&amp;msdc_top CLK_MSDC_TOP_H_MST_0P&gt;,</div><div class='add'>+				 &lt;&amp;msdc_top CLK_MSDC_TOP_SRC_0P&gt;,</div><div class='add'>+				 &lt;&amp;msdc_top CLK_MSDC_TOP_P_CFG&gt;,</div><div class='add'>+				 &lt;&amp;msdc_top CLK_MSDC_TOP_P_MSDC0&gt;,</div><div class='add'>+				 &lt;&amp;msdc_top CLK_MSDC_TOP_AXI&gt;,</div><div class='add'>+				 &lt;&amp;msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI&gt;;</div><div class='add'>+			clock-names = "source", "hclk", "source_cg", "sys_cg",</div><div class='add'>+				      "pclk_cg", "axi_cg", "ahb_cg";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmc1: mmc@11f70000 {</div><div class='add'>+			compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";</div><div class='add'>+			reg = &lt;0 0x11f70000 0 0x1000&gt;, &lt;0 0x11c70000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_MSDC30_1_SEL&gt;,</div><div class='add'>+				 &lt;&amp;msdc_top CLK_MSDC_TOP_H_MST_1P&gt;,</div><div class='add'>+				 &lt;&amp;msdc_top CLK_MSDC_TOP_SRC_1P&gt;,</div><div class='add'>+				 &lt;&amp;msdc_top CLK_MSDC_TOP_P_CFG&gt;,</div><div class='add'>+				 &lt;&amp;msdc_top CLK_MSDC_TOP_P_MSDC1&gt;,</div><div class='add'>+				 &lt;&amp;msdc_top CLK_MSDC_TOP_AXI&gt;,</div><div class='add'>+				 &lt;&amp;msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI&gt;;</div><div class='add'>+			clock-names = "source", "hclk", "source_cg", "sys_cg",</div><div class='add'>+				      "pclk_cg", "axi_cg", "ahb_cg";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu: gpu@13000000 {</div><div class='add'>+			compatible = "mediatek,mt8192-mali", "arm,mali-valhall-jm";</div><div class='add'>+			reg = &lt;0 0x13000000 0 0x4000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+				     &lt;GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+				     &lt;GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			interrupt-names = "job", "mmu", "gpu";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;apmixedsys CLK_APMIXED_MFGPLL&gt;;</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;spm MT8192_POWER_DOMAIN_MFG2&gt;,</div><div class='add'>+					&lt;&amp;spm MT8192_POWER_DOMAIN_MFG3&gt;,</div><div class='add'>+					&lt;&amp;spm MT8192_POWER_DOMAIN_MFG4&gt;,</div><div class='add'>+					&lt;&amp;spm MT8192_POWER_DOMAIN_MFG5&gt;,</div><div class='add'>+					&lt;&amp;spm MT8192_POWER_DOMAIN_MFG6&gt;;</div><div class='add'>+			power-domain-names = "core0", "core1", "core2", "core3", "core4";</div><div class='add'>+</div><div class='add'>+			operating-points-v2 = &lt;&amp;gpu_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mfgcfg: clock-controller@13fbf000 {</div><div class='add'>+			compatible = "mediatek,mt8192-mfgcfg";</div><div class='add'>+			reg = &lt;0 0x13fbf000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmsys: syscon@14000000 {</div><div class='add'>+			compatible = "mediatek,mt8192-mmsys", "syscon";</div><div class='add'>+			reg = &lt;0 0x14000000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+			mboxes = &lt;&amp;gce 0 CMDQ_THR_PRIO_HIGHEST&gt;,</div><div class='add'>+				 &lt;&amp;gce 1 CMDQ_THR_PRIO_HIGHEST&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1400XXXX 0 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mutex: mutex@14001000 {</div><div class='add'>+			compatible = "mediatek,mt8192-disp-mutex";</div><div class='add'>+			reg = &lt;0 0x14001000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_MUTEX0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1400XXXX 0x1000 0x1000&gt;;</div><div class='add'>+			mediatek,gce-events = &lt;CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0&gt;,</div><div class='add'>+					      &lt;CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8192_POWER_DOMAIN_DISP&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smi_common: smi@14002000 {</div><div class='add'>+			compatible = "mediatek,mt8192-smi-common";</div><div class='add'>+			reg = &lt;0 0x14002000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_SMI_COMMON&gt;,</div><div class='add'>+				 &lt;&amp;mmsys CLK_MM_SMI_INFRA&gt;,</div><div class='add'>+				 &lt;&amp;mmsys CLK_MM_SMI_GALS&gt;,</div><div class='add'>+				 &lt;&amp;mmsys CLK_MM_SMI_GALS&gt;;</div><div class='add'>+			clock-names = "apb", "smi", "gals0", "gals1";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8192_POWER_DOMAIN_DISP&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb0: larb@14003000 {</div><div class='add'>+			compatible = "mediatek,mt8192-smi-larb";</div><div class='add'>+			reg = &lt;0 0x14003000 0 0x1000&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;0&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk26m&gt;, &lt;&amp;clk26m&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8192_POWER_DOMAIN_DISP&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb1: larb@14004000 {</div><div class='add'>+			compatible = "mediatek,mt8192-smi-larb";</div><div class='add'>+			reg = &lt;0 0x14004000 0 0x1000&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;1&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk26m&gt;, &lt;&amp;clk26m&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8192_POWER_DOMAIN_DISP&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ovl0: ovl@14005000 {</div><div class='add'>+			compatible = "mediatek,mt8192-disp-ovl";</div><div class='add'>+			reg = &lt;0 0x14005000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_OVL0&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu0 M4U_PORT_L0_OVL_RDMA0&gt;,</div><div class='add'>+				 &lt;&amp;iommu0 M4U_PORT_L0_OVL_RDMA0_HDR&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8192_POWER_DOMAIN_DISP&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1400XXXX 0x5000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ovl_2l0: ovl@14006000 {</div><div class='add'>+			compatible = "mediatek,mt8192-disp-ovl-2l";</div><div class='add'>+			reg = &lt;0 0x14006000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8192_POWER_DOMAIN_DISP&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_OVL0_2L&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu0 M4U_PORT_L1_OVL_2L_RDMA0&gt;,</div><div class='add'>+				 &lt;&amp;iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1400XXXX 0x6000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rdma0: rdma@14007000 {</div><div class='add'>+			compatible = "mediatek,mt8192-disp-rdma",</div><div class='add'>+				     "mediatek,mt8183-disp-rdma";</div><div class='add'>+			reg = &lt;0 0x14007000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_RDMA0&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu0 M4U_PORT_L0_DISP_RDMA0&gt;;</div><div class='add'>+			mediatek,rdma-fifo-size = &lt;5120&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8192_POWER_DOMAIN_DISP&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1400XXXX 0x7000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		color0: color@14009000 {</div><div class='add'>+			compatible = "mediatek,mt8192-disp-color",</div><div class='add'>+				     "mediatek,mt8173-disp-color";</div><div class='add'>+			reg = &lt;0 0x14009000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8192_POWER_DOMAIN_DISP&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_COLOR0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1400XXXX 0x9000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ccorr0: ccorr@1400a000 {</div><div class='add'>+			compatible = "mediatek,mt8192-disp-ccorr";</div><div class='add'>+			reg = &lt;0 0x1400a000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8192_POWER_DOMAIN_DISP&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_CCORR0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1400XXXX 0xa000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aal0: aal@1400b000 {</div><div class='add'>+			compatible = "mediatek,mt8192-disp-aal",</div><div class='add'>+				     "mediatek,mt8183-disp-aal";</div><div class='add'>+			reg = &lt;0 0x1400b000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8192_POWER_DOMAIN_DISP&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_AAL0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1400XXXX 0xb000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gamma0: gamma@1400c000 {</div><div class='add'>+			compatible = "mediatek,mt8192-disp-gamma",</div><div class='add'>+				     "mediatek,mt8183-disp-gamma";</div><div class='add'>+			reg = &lt;0 0x1400c000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8192_POWER_DOMAIN_DISP&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_GAMMA0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1400XXXX 0xc000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		postmask0: postmask@1400d000 {</div><div class='add'>+			compatible = "mediatek,mt8192-disp-postmask";</div><div class='add'>+			reg = &lt;0 0x1400d000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8192_POWER_DOMAIN_DISP&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_POSTMASK0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1400XXXX 0xd000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dither0: dither@1400e000 {</div><div class='add'>+			compatible = "mediatek,mt8192-disp-dither",</div><div class='add'>+				     "mediatek,mt8183-disp-dither";</div><div class='add'>+			reg = &lt;0 0x1400e000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8192_POWER_DOMAIN_DISP&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_DITHER0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1400XXXX 0xe000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dsi0: dsi@14010000 {</div><div class='add'>+			compatible = "mediatek,mt8183-dsi";</div><div class='add'>+			reg = &lt;0 0x14010000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DSI0&gt;,</div><div class='add'>+				 &lt;&amp;mmsys CLK_MM_DSI_DSI0&gt;,</div><div class='add'>+				 &lt;&amp;mipi_tx0&gt;;</div><div class='add'>+			clock-names = "engine", "digital", "hs";</div><div class='add'>+			phys = &lt;&amp;mipi_tx0&gt;;</div><div class='add'>+			phy-names = "dphy";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8192_POWER_DOMAIN_DISP&gt;;</div><div class='add'>+			resets = &lt;&amp;mmsys MT8192_MMSYS_SW0_RST_B_DISP_DSI0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			port {</div><div class='add'>+				dsi_out: endpoint { };</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ovl_2l2: ovl@14014000 {</div><div class='add'>+			compatible = "mediatek,mt8192-disp-ovl-2l";</div><div class='add'>+			reg = &lt;0 0x14014000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8192_POWER_DOMAIN_DISP&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_OVL2_2L&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu0 M4U_PORT_L1_OVL_2L_RDMA2&gt;,</div><div class='add'>+				 &lt;&amp;iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1401XXXX 0x4000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rdma4: rdma@14015000 {</div><div class='add'>+			compatible = "mediatek,mt8192-disp-rdma",</div><div class='add'>+				     "mediatek,mt8183-disp-rdma";</div><div class='add'>+			reg = &lt;0 0x14015000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8192_POWER_DOMAIN_DISP&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DISP_RDMA4&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu0 M4U_PORT_L1_DISP_RDMA4&gt;;</div><div class='add'>+			mediatek,rdma-fifo-size = &lt;2048&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce SUBSYS_1401XXXX 0x5000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dpi0: dpi@14016000 {</div><div class='add'>+			compatible = "mediatek,mt8192-dpi";</div><div class='add'>+			reg = &lt;0 0x14016000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DPI_DPI0&gt;,</div><div class='add'>+				 &lt;&amp;mmsys CLK_MM_DISP_DPI0&gt;,</div><div class='add'>+				 &lt;&amp;apmixedsys CLK_APMIXED_TVDPLL&gt;;</div><div class='add'>+			clock-names = "pixel", "engine", "pll";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		iommu0: m4u@1401d000 {</div><div class='add'>+			compatible = "mediatek,mt8192-m4u";</div><div class='add'>+			reg = &lt;0 0x1401d000 0 0x1000&gt;;</div><div class='add'>+			mediatek,larbs = &lt;&amp;larb0&gt;, &lt;&amp;larb1&gt;, &lt;&amp;larb2&gt;,</div><div class='add'>+					 &lt;&amp;larb4&gt;, &lt;&amp;larb5&gt;, &lt;&amp;larb7&gt;,</div><div class='add'>+					 &lt;&amp;larb9&gt;, &lt;&amp;larb11&gt;, &lt;&amp;larb13&gt;,</div><div class='add'>+					 &lt;&amp;larb14&gt;, &lt;&amp;larb16&gt;, &lt;&amp;larb17&gt;,</div><div class='add'>+					 &lt;&amp;larb18&gt;, &lt;&amp;larb19&gt;, &lt;&amp;larb20&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_SMI_IOMMU&gt;;</div><div class='add'>+			clock-names = "bclk";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8192_POWER_DOMAIN_DISP&gt;;</div><div class='add'>+			#iommu-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		imgsys: clock-controller@15020000 {</div><div class='add'>+			compatible = "mediatek,mt8192-imgsys";</div><div class='add'>+			reg = &lt;0 0x15020000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb9: larb@1502e000 {</div><div class='add'>+			compatible = "mediatek,mt8192-smi-larb";</div><div class='add'>+			reg = &lt;0 0x1502e000 0 0x1000&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;9&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+			clocks = &lt;&amp;imgsys CLK_IMG_LARB9&gt;,</div><div class='add'>+				 &lt;&amp;imgsys CLK_IMG_LARB9&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8192_POWER_DOMAIN_ISP&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		imgsys2: clock-controller@15820000 {</div><div class='add'>+			compatible = "mediatek,mt8192-imgsys2";</div><div class='add'>+			reg = &lt;0 0x15820000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb11: larb@1582e000 {</div><div class='add'>+			compatible = "mediatek,mt8192-smi-larb";</div><div class='add'>+			reg = &lt;0 0x1582e000 0 0x1000&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;11&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+			clocks = &lt;&amp;imgsys2 CLK_IMG2_LARB11&gt;,</div><div class='add'>+				 &lt;&amp;imgsys2 CLK_IMG2_LARB11&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8192_POWER_DOMAIN_ISP2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vcodec_dec: video-codec@16000000 {</div><div class='add'>+			compatible = "mediatek,mt8192-vcodec-dec";</div><div class='add'>+			reg = &lt;0 0x16000000 0 0x1000&gt;;</div><div class='add'>+			mediatek,scp = &lt;&amp;scp&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu0 M4U_PORT_L4_VDEC_MC_EXT&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges = &lt;0 0 0 0x16000000 0 0x26000&gt;;</div><div class='add'>+</div><div class='add'>+			video-codec@10000 {</div><div class='add'>+				compatible = "mediatek,mtk-vcodec-lat";</div><div class='add'>+				reg = &lt;0x0 0x10000 0 0x800&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				iommus = &lt;&amp;iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT&gt;,</div><div class='add'>+					 &lt;&amp;iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT&gt;,</div><div class='add'>+					 &lt;&amp;iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT&gt;,</div><div class='add'>+					 &lt;&amp;iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT&gt;,</div><div class='add'>+					 &lt;&amp;iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT&gt;,</div><div class='add'>+					 &lt;&amp;iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT&gt;,</div><div class='add'>+					 &lt;&amp;iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT&gt;,</div><div class='add'>+					 &lt;&amp;iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT&gt;;</div><div class='add'>+				clocks = &lt;&amp;topckgen CLK_TOP_VDEC_SEL&gt;,</div><div class='add'>+					 &lt;&amp;vdecsys_soc CLK_VDEC_SOC_VDEC&gt;,</div><div class='add'>+					 &lt;&amp;vdecsys_soc CLK_VDEC_SOC_LAT&gt;,</div><div class='add'>+					 &lt;&amp;vdecsys_soc CLK_VDEC_SOC_LARB1&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_MAINPLL_D4&gt;;</div><div class='add'>+				clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";</div><div class='add'>+				assigned-clocks = &lt;&amp;topckgen CLK_TOP_VDEC_SEL&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_MAINPLL_D4&gt;;</div><div class='add'>+				power-domains = &lt;&amp;spm MT8192_POWER_DOMAIN_VDEC&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			video-codec@25000 {</div><div class='add'>+				compatible = "mediatek,mtk-vcodec-core";</div><div class='add'>+				reg = &lt;0 0x25000 0 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				iommus = &lt;&amp;iommu0 M4U_PORT_L4_VDEC_MC_EXT&gt;,</div><div class='add'>+					 &lt;&amp;iommu0 M4U_PORT_L4_VDEC_UFO_EXT&gt;,</div><div class='add'>+					 &lt;&amp;iommu0 M4U_PORT_L4_VDEC_PP_EXT&gt;,</div><div class='add'>+					 &lt;&amp;iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT&gt;,</div><div class='add'>+					 &lt;&amp;iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT&gt;,</div><div class='add'>+					 &lt;&amp;iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT&gt;,</div><div class='add'>+					 &lt;&amp;iommu0 M4U_PORT_L4_VDEC_TILE_EXT&gt;,</div><div class='add'>+					 &lt;&amp;iommu0 M4U_PORT_L4_VDEC_VLD_EXT&gt;,</div><div class='add'>+					 &lt;&amp;iommu0 M4U_PORT_L4_VDEC_VLD2_EXT&gt;,</div><div class='add'>+					 &lt;&amp;iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT&gt;,</div><div class='add'>+					 &lt;&amp;iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT&gt;;</div><div class='add'>+				clocks = &lt;&amp;topckgen CLK_TOP_VDEC_SEL&gt;,</div><div class='add'>+					 &lt;&amp;vdecsys CLK_VDEC_VDEC&gt;,</div><div class='add'>+					 &lt;&amp;vdecsys CLK_VDEC_LAT&gt;,</div><div class='add'>+					 &lt;&amp;vdecsys CLK_VDEC_LARB1&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_MAINPLL_D4&gt;;</div><div class='add'>+				clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";</div><div class='add'>+				assigned-clocks = &lt;&amp;topckgen CLK_TOP_VDEC_SEL&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_MAINPLL_D4&gt;;</div><div class='add'>+				power-domains = &lt;&amp;spm MT8192_POWER_DOMAIN_VDEC2&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb5: larb@1600d000 {</div><div class='add'>+			compatible = "mediatek,mt8192-smi-larb";</div><div class='add'>+			reg = &lt;0 0x1600d000 0 0x1000&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;5&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdecsys_soc CLK_VDEC_SOC_LARB1&gt;,</div><div class='add'>+				 &lt;&amp;vdecsys_soc CLK_VDEC_SOC_LARB1&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8192_POWER_DOMAIN_VDEC&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdecsys_soc: clock-controller@1600f000 {</div><div class='add'>+			compatible = "mediatek,mt8192-vdecsys_soc";</div><div class='add'>+			reg = &lt;0 0x1600f000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb4: larb@1602e000 {</div><div class='add'>+			compatible = "mediatek,mt8192-smi-larb";</div><div class='add'>+			reg = &lt;0 0x1602e000 0 0x1000&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;4&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdecsys CLK_VDEC_SOC_LARB1&gt;,</div><div class='add'>+				 &lt;&amp;vdecsys CLK_VDEC_SOC_LARB1&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8192_POWER_DOMAIN_VDEC2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdecsys: clock-controller@1602f000 {</div><div class='add'>+			compatible = "mediatek,mt8192-vdecsys";</div><div class='add'>+			reg = &lt;0 0x1602f000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vencsys: clock-controller@17000000 {</div><div class='add'>+			compatible = "mediatek,mt8192-vencsys";</div><div class='add'>+			reg = &lt;0 0x17000000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb7: larb@17010000 {</div><div class='add'>+			compatible = "mediatek,mt8192-smi-larb";</div><div class='add'>+			reg = &lt;0 0x17010000 0 0x1000&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;7&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+			clocks = &lt;&amp;vencsys CLK_VENC_SET0_LARB&gt;,</div><div class='add'>+				 &lt;&amp;vencsys CLK_VENC_SET1_VENC&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8192_POWER_DOMAIN_VENC&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vcodec_enc: vcodec@17020000 {</div><div class='add'>+			compatible = "mediatek,mt8192-vcodec-enc";</div><div class='add'>+			reg = &lt;0 0x17020000 0 0x2000&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu0 M4U_PORT_L7_VENC_RCPU&gt;,</div><div class='add'>+				 &lt;&amp;iommu0 M4U_PORT_L7_VENC_REC&gt;,</div><div class='add'>+				 &lt;&amp;iommu0 M4U_PORT_L7_VENC_BSDMA&gt;,</div><div class='add'>+				 &lt;&amp;iommu0 M4U_PORT_L7_VENC_SV_COMV&gt;,</div><div class='add'>+				 &lt;&amp;iommu0 M4U_PORT_L7_VENC_RD_COMV&gt;,</div><div class='add'>+				 &lt;&amp;iommu0 M4U_PORT_L7_VENC_CUR_LUMA&gt;,</div><div class='add'>+				 &lt;&amp;iommu0 M4U_PORT_L7_VENC_CUR_CHROMA&gt;,</div><div class='add'>+				 &lt;&amp;iommu0 M4U_PORT_L7_VENC_REF_LUMA&gt;,</div><div class='add'>+				 &lt;&amp;iommu0 M4U_PORT_L7_VENC_REF_CHROMA&gt;,</div><div class='add'>+				 &lt;&amp;iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA&gt;,</div><div class='add'>+				 &lt;&amp;iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			mediatek,scp = &lt;&amp;scp&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8192_POWER_DOMAIN_VENC&gt;;</div><div class='add'>+			clocks = &lt;&amp;vencsys CLK_VENC_SET1_VENC&gt;;</div><div class='add'>+			clock-names = "venc_sel";</div><div class='add'>+			assigned-clocks = &lt;&amp;topckgen CLK_TOP_VENC_SEL&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_UNIVPLL_D4&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		camsys: clock-controller@1a000000 {</div><div class='add'>+			compatible = "mediatek,mt8192-camsys";</div><div class='add'>+			reg = &lt;0 0x1a000000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb13: larb@1a001000 {</div><div class='add'>+			compatible = "mediatek,mt8192-smi-larb";</div><div class='add'>+			reg = &lt;0 0x1a001000 0 0x1000&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;13&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+			clocks = &lt;&amp;camsys CLK_CAM_CAM&gt;,</div><div class='add'>+				 &lt;&amp;camsys CLK_CAM_LARB13&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8192_POWER_DOMAIN_CAM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb14: larb@1a002000 {</div><div class='add'>+			compatible = "mediatek,mt8192-smi-larb";</div><div class='add'>+			reg = &lt;0 0x1a002000 0 0x1000&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;14&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+			clocks = &lt;&amp;camsys CLK_CAM_CAM&gt;,</div><div class='add'>+				 &lt;&amp;camsys CLK_CAM_LARB14&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8192_POWER_DOMAIN_CAM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb16: larb@1a00f000 {</div><div class='add'>+			compatible = "mediatek,mt8192-smi-larb";</div><div class='add'>+			reg = &lt;0 0x1a00f000 0 0x1000&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;16&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+			clocks = &lt;&amp;camsys_rawa CLK_CAM_RAWA_CAM&gt;,</div><div class='add'>+				 &lt;&amp;camsys_rawa CLK_CAM_RAWA_LARBX&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8192_POWER_DOMAIN_CAM_RAWA&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb17: larb@1a010000 {</div><div class='add'>+			compatible = "mediatek,mt8192-smi-larb";</div><div class='add'>+			reg = &lt;0 0x1a010000 0 0x1000&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;17&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+			clocks = &lt;&amp;camsys_rawb CLK_CAM_RAWB_CAM&gt;,</div><div class='add'>+				 &lt;&amp;camsys_rawb CLK_CAM_RAWB_LARBX&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8192_POWER_DOMAIN_CAM_RAWB&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb18: larb@1a011000 {</div><div class='add'>+			compatible = "mediatek,mt8192-smi-larb";</div><div class='add'>+			reg = &lt;0 0x1a011000 0 0x1000&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;18&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+			clocks = &lt;&amp;camsys_rawc CLK_CAM_RAWC_LARBX&gt;,</div><div class='add'>+				 &lt;&amp;camsys_rawc CLK_CAM_RAWC_CAM&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8192_POWER_DOMAIN_CAM_RAWC&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		camsys_rawa: clock-controller@1a04f000 {</div><div class='add'>+			compatible = "mediatek,mt8192-camsys_rawa";</div><div class='add'>+			reg = &lt;0 0x1a04f000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		camsys_rawb: clock-controller@1a06f000 {</div><div class='add'>+			compatible = "mediatek,mt8192-camsys_rawb";</div><div class='add'>+			reg = &lt;0 0x1a06f000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		camsys_rawc: clock-controller@1a08f000 {</div><div class='add'>+			compatible = "mediatek,mt8192-camsys_rawc";</div><div class='add'>+			reg = &lt;0 0x1a08f000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ipesys: clock-controller@1b000000 {</div><div class='add'>+			compatible = "mediatek,mt8192-ipesys";</div><div class='add'>+			reg = &lt;0 0x1b000000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb20: larb@1b00f000 {</div><div class='add'>+			compatible = "mediatek,mt8192-smi-larb";</div><div class='add'>+			reg = &lt;0 0x1b00f000 0 0x1000&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;20&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+			clocks = &lt;&amp;ipesys CLK_IPE_SMI_SUBCOM&gt;,</div><div class='add'>+				 &lt;&amp;ipesys CLK_IPE_LARB20&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8192_POWER_DOMAIN_IPE&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb19: larb@1b10f000 {</div><div class='add'>+			compatible = "mediatek,mt8192-smi-larb";</div><div class='add'>+			reg = &lt;0 0x1b10f000 0 0x1000&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;19&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+			clocks = &lt;&amp;ipesys CLK_IPE_SMI_SUBCOM&gt;,</div><div class='add'>+				 &lt;&amp;ipesys CLK_IPE_LARB19&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8192_POWER_DOMAIN_IPE&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdpsys: clock-controller@1f000000 {</div><div class='add'>+			compatible = "mediatek,mt8192-mdpsys";</div><div class='add'>+			reg = &lt;0 0x1f000000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb2: larb@1f002000 {</div><div class='add'>+			compatible = "mediatek,mt8192-smi-larb";</div><div class='add'>+			reg = &lt;0 0x1f002000 0 0x1000&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;2&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+			clocks = &lt;&amp;mdpsys CLK_MDP_SMI0&gt;,</div><div class='add'>+				 &lt;&amp;mdpsys CLK_MDP_SMI0&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8192_POWER_DOMAIN_MDP&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	thermal_zones: thermal-zones {</div><div class='add'>+		cpu0-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_mcu MT8192_MCU_LITTLE_CPU0&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu0_alert: trip-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu0_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu0_alert&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_mcu MT8192_MCU_LITTLE_CPU1&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu1_alert: trip-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu1_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu1_alert&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_mcu MT8192_MCU_LITTLE_CPU2&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu2_alert: trip-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu2_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu2_alert&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_mcu MT8192_MCU_LITTLE_CPU3&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu3_alert: trip-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu3_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu3_alert&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu4-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_mcu MT8192_MCU_BIG_CPU0&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu4_alert: trip-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu4_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu4_alert&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu5-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_mcu MT8192_MCU_BIG_CPU1&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu5_alert: trip-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu5_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu5_alert&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu6-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_mcu MT8192_MCU_BIG_CPU2&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu6_alert: trip-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu6_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu6_alert&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu7-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_mcu MT8192_MCU_BIG_CPU3&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu7_alert: trip-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu7_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu7_alert&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vpu0-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_ap MT8192_AP_VPU0&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				vpu0_alert: trip-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				vpu0_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vpu1-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_ap MT8192_AP_VPU1&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				vpu1_alert: trip-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				vpu1_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_ap MT8192_AP_GPU0&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				gpu0_alert: trip-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpu0_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu1-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_ap MT8192_AP_GPU1&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				gpu1_alert: trip-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpu1_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		infra-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_ap MT8192_AP_INFRA&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				infra_alert: trip-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				infra_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cam-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_ap MT8192_AP_CAM&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cam_alert: trip-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cam_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		md0-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_ap MT8192_AP_MD0&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				md0_alert: trip-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				md0_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		md1-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_ap MT8192_AP_MD1&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				md1_alert: trip-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				md1_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		md2-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_ap MT8192_AP_MD2&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				md2_alert: trip-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				md2_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry-dojo-r1.dts b/arch/arm64/boot/dts/mediatek/mt8195-cherry-dojo-r1.dts<br/>new file mode 100644<br/>index 000000000000..49664de99b88<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8195-cherry-dojo-r1.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8195-cherry-dojo-r1.dts</a></div><div class='hunk'>@@ -0,0 +1,119 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2022 MediaTek Inc.</div><div class='add'>+ */</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8195-cherry.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "HP Dojo (sku 1, 3, 5, 7) board";</div><div class='add'>+	chassis-type = "convertible";</div><div class='add'>+	compatible = "google,dojo-sku7", "google,dojo-sku5",</div><div class='add'>+		     "google,dojo-sku3", "google,dojo-sku1",</div><div class='add'>+		     "google,dojo", "mediatek,mt8195";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;audio_codec {</div><div class='add'>+	compatible = "realtek,rt5682s";</div><div class='add'>+	realtek,amic-delay-ms = &lt;250&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	spk_r_amp: amplifier@38 {</div><div class='add'>+		compatible = "maxim,max98390";</div><div class='add'>+		reg = &lt;0x38&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pio 100 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		sound-name-prefix = "Right";</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spk_l_amp: amplifier@39 {</div><div class='add'>+		compatible = "maxim,max98390";</div><div class='add'>+		reg = &lt;0x39&gt;;</div><div class='add'>+		sound-name-prefix = "Left";</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	touchscreen@15 {</div><div class='add'>+		compatible = "hid-over-i2c";</div><div class='add'>+		reg = &lt;0x15&gt;;</div><div class='add'>+		hid-descr-addr = &lt;0x0001&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 92 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;touchscreen_pins&gt;;</div><div class='add'>+		post-power-on-delay-ms = &lt;10&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;pp3300_s3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;keyboard_controller {</div><div class='add'>+	linux,keymap = &lt;</div><div class='add'>+		CROS_STD_MAIN_KEYMAP</div><div class='add'>+</div><div class='add'>+		MATRIX_KEY(0x00, 0x02, KEY_BACK)</div><div class='add'>+		MATRIX_KEY(0x03, 0x02, KEY_REFRESH)</div><div class='add'>+		MATRIX_KEY(0x02, 0x02, KEY_ZOOM)</div><div class='add'>+		MATRIX_KEY(0x01, 0x02, KEY_SCALE)</div><div class='add'>+		MATRIX_KEY(0x03, 0x04, KEY_SYSRQ)</div><div class='add'>+		MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN)</div><div class='add'>+		MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP)</div><div class='add'>+		MATRIX_KEY(0x02, 0x09, KEY_KBDILLUMTOGGLE)</div><div class='add'>+		MATRIX_KEY(0x01, 0x09, KEY_PLAYPAUSE)</div><div class='add'>+		MATRIX_KEY(0x00, 0x04, KEY_MICMUTE)</div><div class='add'>+		MATRIX_KEY(0x00, 0x01, KEY_MUTE)</div><div class='add'>+		MATRIX_KEY(0x01, 0x05, KEY_VOLUMEDOWN)</div><div class='add'>+		MATRIX_KEY(0x03, 0x05, KEY_VOLUMEUP)</div><div class='add'>+	&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pcie0_pins_default&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pciephy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio_default {</div><div class='add'>+	pins-low-power-hdmi-disable {</div><div class='add'>+		pinmux = &lt;PINMUX_GPIO31__FUNC_GPIO31&gt;,</div><div class='add'>+			 &lt;PINMUX_GPIO32__FUNC_GPIO32&gt;,</div><div class='add'>+			 &lt;PINMUX_GPIO33__FUNC_GPIO33&gt;;</div><div class='add'>+		input-enable;</div><div class='add'>+		bias-pull-down;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pins-low-power-hdmi-rsel-disable {</div><div class='add'>+		pinmux = &lt;PINMUX_GPIO34__FUNC_GPIO34&gt;,</div><div class='add'>+			 &lt;PINMUX_GPIO35__FUNC_GPIO35&gt;;</div><div class='add'>+		input-enable;</div><div class='add'>+		bias-pull-down = &lt;75000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sound {</div><div class='add'>+	compatible = "mediatek,mt8195_mt6359_max98390_rt5682";</div><div class='add'>+	model = "m8195_m98390_5682s";</div><div class='add'>+</div><div class='add'>+	audio-routing =</div><div class='add'>+		"Headphone", "HPOL",</div><div class='add'>+		"Headphone", "HPOR",</div><div class='add'>+		"IN1P", "Headset Mic",</div><div class='add'>+		"Right Spk", "Right BE_OUT",</div><div class='add'>+		"Left Spk", "Left BE_OUT";</div><div class='add'>+</div><div class='add'>+	spk-playback-dai-link {</div><div class='add'>+		codec {</div><div class='add'>+			sound-dai = &lt;&amp;spk_r_amp&gt;, &lt;&amp;spk_l_amp&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spk_amplifier {</div><div class='add'>+	/* Disable RT1019P, not present on Dojo */</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts<br/>new file mode 100644<br/>index 000000000000..a50b4e8efaba<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts</a></div><div class='hunk'>@@ -0,0 +1,30 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2021 MediaTek Inc.</div><div class='add'>+ */</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8195-cherry.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Acer Tomato (rev1) board";</div><div class='add'>+	compatible = "google,tomato-rev1", "google,tomato", "mediatek,mt8195";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;audio_codec {</div><div class='add'>+	compatible = "realtek,rt5682i";</div><div class='add'>+	realtek,btndet-delay = &lt;16&gt;;</div><div class='add'>+	VBAT-supply = &lt;&amp;pp3300_z5&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sound {</div><div class='add'>+	compatible = "mediatek,mt8195_mt6359_rt1019_rt5682";</div><div class='add'>+	model = "mt8195_r1019_5682";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ts_10 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;watchdog {</div><div class='add'>+	/delete-property/ mediatek,disable-extrst;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts<br/>new file mode 100644<br/>index 000000000000..a8657c0068d5<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts</a></div><div class='hunk'>@@ -0,0 +1,55 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2021 MediaTek Inc.</div><div class='add'>+ */</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8195-cherry.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Acer Tomato (rev2) board";</div><div class='add'>+	compatible = "google,tomato-rev2", "google,tomato", "mediatek,mt8195";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;audio_codec {</div><div class='add'>+	compatible = "realtek,rt5682i";</div><div class='add'>+	realtek,btndet-delay = &lt;16&gt;;</div><div class='add'>+	VBAT-supply = &lt;&amp;pp3300_z5&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio_default {</div><div class='add'>+	pins-low-power-hdmi-disable {</div><div class='add'>+		pinmux = &lt;PINMUX_GPIO31__FUNC_GPIO31&gt;,</div><div class='add'>+			 &lt;PINMUX_GPIO32__FUNC_GPIO32&gt;,</div><div class='add'>+			 &lt;PINMUX_GPIO33__FUNC_GPIO33&gt;;</div><div class='add'>+		input-enable;</div><div class='add'>+		bias-pull-down;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pins-low-power-hdmi-rsel-disable {</div><div class='add'>+		pinmux = &lt;PINMUX_GPIO34__FUNC_GPIO34&gt;,</div><div class='add'>+			 &lt;PINMUX_GPIO35__FUNC_GPIO35&gt;;</div><div class='add'>+		input-enable;</div><div class='add'>+		bias-pull-down = &lt;75000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pins-low-power-pcie0-disable {</div><div class='add'>+		pinmux = &lt;PINMUX_GPIO19__FUNC_GPIO19&gt;,</div><div class='add'>+			 &lt;PINMUX_GPIO20__FUNC_GPIO20&gt;,</div><div class='add'>+			 &lt;PINMUX_GPIO21__FUNC_GPIO21&gt;;</div><div class='add'>+		input-enable;</div><div class='add'>+		bias-pull-down;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sound {</div><div class='add'>+	compatible = "mediatek,mt8195_mt6359_rt1019_rt5682";</div><div class='add'>+	model = "mt8195_r1019_5682";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ts_10 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;watchdog {</div><div class='add'>+	/delete-property/ mediatek,disable-extrst;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r3.dts b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r3.dts<br/>new file mode 100644<br/>index 000000000000..9049d362a5e0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r3.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r3.dts</a></div><div class='hunk'>@@ -0,0 +1,55 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2021 MediaTek Inc.</div><div class='add'>+ */</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8195-cherry.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Acer Tomato (rev3 - 4) board";</div><div class='add'>+	compatible = "google,tomato-rev4", "google,tomato-rev3",</div><div class='add'>+		     "google,tomato", "mediatek,mt8195";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;audio_codec {</div><div class='add'>+	compatible = "realtek,rt5682s";</div><div class='add'>+	realtek,amic-delay-ms = &lt;250&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio_default {</div><div class='add'>+	pins-low-power-hdmi-disable {</div><div class='add'>+		pinmux = &lt;PINMUX_GPIO31__FUNC_GPIO31&gt;,</div><div class='add'>+			 &lt;PINMUX_GPIO32__FUNC_GPIO32&gt;,</div><div class='add'>+			 &lt;PINMUX_GPIO33__FUNC_GPIO33&gt;;</div><div class='add'>+		input-enable;</div><div class='add'>+		bias-pull-down;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pins-low-power-hdmi-rsel-disable {</div><div class='add'>+		pinmux = &lt;PINMUX_GPIO34__FUNC_GPIO34&gt;,</div><div class='add'>+			 &lt;PINMUX_GPIO35__FUNC_GPIO35&gt;;</div><div class='add'>+		input-enable;</div><div class='add'>+		bias-pull-down = &lt;75000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pins-low-power-pcie0-disable {</div><div class='add'>+		pinmux = &lt;PINMUX_GPIO19__FUNC_GPIO19&gt;,</div><div class='add'>+			 &lt;PINMUX_GPIO20__FUNC_GPIO20&gt;,</div><div class='add'>+			 &lt;PINMUX_GPIO21__FUNC_GPIO21&gt;;</div><div class='add'>+		input-enable;</div><div class='add'>+		bias-pull-down;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sound {</div><div class='add'>+	compatible = "mediatek,mt8195_mt6359_rt1019_rt5682";</div><div class='add'>+	model = "m8195_r1019_5682s";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ts_10 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;watchdog {</div><div class='add'>+	/delete-property/ mediatek,disable-extrst;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi<br/>new file mode 100644<br/>index 000000000000..b3761b80cac7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi</a></div><div class='hunk'>@@ -0,0 +1,1625 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2021 MediaTek Inc.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/spmi/spmi.h&gt;</div><div class='add'>+#include "mt8195.dtsi"</div><div class='add'>+#include "mt6359.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		i2c0 = &amp;i2c0;</div><div class='add'>+		i2c1 = &amp;i2c1;</div><div class='add'>+		i2c2 = &amp;i2c2;</div><div class='add'>+		i2c3 = &amp;i2c3;</div><div class='add'>+		i2c4 = &amp;i2c4;</div><div class='add'>+		i2c5 = &amp;i2c5;</div><div class='add'>+		i2c7 = &amp;i2c7;</div><div class='add'>+		mmc0 = &amp;mmc0;</div><div class='add'>+		mmc1 = &amp;mmc1;</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	backlight_lcd0: backlight-lcd0 {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		brightness-levels = &lt;0 1023&gt;;</div><div class='add'>+		default-brightness-level = &lt;576&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;pio 82 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		num-interpolated-steps = &lt;1023&gt;;</div><div class='add'>+		pwms = &lt;&amp;disp_pwm0 0 500000&gt;;</div><div class='add'>+		power-supply = &lt;&amp;ppvar_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dmic-codec {</div><div class='add'>+		compatible = "dmic-codec";</div><div class='add'>+		num-channels = &lt;2&gt;;</div><div class='add'>+		wakeup-delay-ms = &lt;50&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0 0x40000000 0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pp3300_disp_x: regulator-pp3300-disp-x {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "pp3300_disp_x";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-enable-ramp-delay = &lt;2500&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;pio 55 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;panel_fixed_pins&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;pp3300_z2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* system wide LDO 3.3V power rail */</div><div class='add'>+	pp3300_z5: regulator-pp3300-ldo-z5 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "pp3300_ldo_z5";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;ppvar_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* separately switched 3.3V power rail */</div><div class='add'>+	pp3300_s3: regulator-pp3300-s3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "pp3300_s3";</div><div class='add'>+		/* automatically sequenced by PMIC EXT_PMIC_EN2 */</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;pp3300_z2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* system wide 3.3V power rail */</div><div class='add'>+	pp3300_z2: regulator-pp3300-z2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "pp3300_z2";</div><div class='add'>+		/* EN pin tied to pp4200_z2, which is controlled by EC */</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;ppvar_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* system wide 4.2V power rail */</div><div class='add'>+	pp4200_z2: regulator-pp4200-z2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "pp4200_z2";</div><div class='add'>+		/* controlled by EC */</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-min-microvolt = &lt;4200000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;4200000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;ppvar_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* system wide switching 5.0V power rail */</div><div class='add'>+	pp5000_s5: regulator-pp5000-s5 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "pp5000_s5";</div><div class='add'>+		/* controlled by EC */</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;ppvar_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* system wide semi-regulated power rail from battery or USB */</div><div class='add'>+	ppvar_sys: regulator-ppvar-sys {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "ppvar_sys";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Murata NCP03WF104F05RL */</div><div class='add'>+	tboard_thermistor1: thermal-sensor-t1 {</div><div class='add'>+		compatible = "generic-adc-thermal";</div><div class='add'>+		#thermal-sensor-cells = &lt;0&gt;;</div><div class='add'>+		io-channels = &lt;&amp;auxadc 0&gt;;</div><div class='add'>+		io-channel-names = "sensor-channel";</div><div class='add'>+		temperature-lookup-table = &lt;	(-10000) 1553</div><div class='add'>+						(-5000) 1485</div><div class='add'>+						0 1406</div><div class='add'>+						5000 1317</div><div class='add'>+						10000 1219</div><div class='add'>+						15000 1115</div><div class='add'>+						20000 1007</div><div class='add'>+						25000 900</div><div class='add'>+						30000 796</div><div class='add'>+						35000 697</div><div class='add'>+						40000 605</div><div class='add'>+						45000 523</div><div class='add'>+						50000 449</div><div class='add'>+						55000 384</div><div class='add'>+						60000 327</div><div class='add'>+						65000 279</div><div class='add'>+						70000 237</div><div class='add'>+						75000 202</div><div class='add'>+						80000 172</div><div class='add'>+						85000 147</div><div class='add'>+						90000 125</div><div class='add'>+						95000 107</div><div class='add'>+						100000 92</div><div class='add'>+						105000 79</div><div class='add'>+						110000 68</div><div class='add'>+						115000 59</div><div class='add'>+						120000 51</div><div class='add'>+						125000 44&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	tboard_thermistor2: thermal-sensor-t2 {</div><div class='add'>+		compatible = "generic-adc-thermal";</div><div class='add'>+		#thermal-sensor-cells = &lt;0&gt;;</div><div class='add'>+		io-channels = &lt;&amp;auxadc 1&gt;;</div><div class='add'>+		io-channel-names = "sensor-channel";</div><div class='add'>+		temperature-lookup-table = &lt;	(-10000) 1553</div><div class='add'>+						(-5000) 1485</div><div class='add'>+						0 1406</div><div class='add'>+						5000 1317</div><div class='add'>+						10000 1219</div><div class='add'>+						15000 1115</div><div class='add'>+						20000 1007</div><div class='add'>+						25000 900</div><div class='add'>+						30000 796</div><div class='add'>+						35000 697</div><div class='add'>+						40000 605</div><div class='add'>+						45000 523</div><div class='add'>+						50000 449</div><div class='add'>+						55000 384</div><div class='add'>+						60000 327</div><div class='add'>+						65000 279</div><div class='add'>+						70000 237</div><div class='add'>+						75000 202</div><div class='add'>+						80000 172</div><div class='add'>+						85000 147</div><div class='add'>+						90000 125</div><div class='add'>+						95000 107</div><div class='add'>+						100000 92</div><div class='add'>+						105000 79</div><div class='add'>+						110000 68</div><div class='add'>+						115000 59</div><div class='add'>+						120000 51</div><div class='add'>+						125000 44&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb_vbus: regulator-5v0-usb-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "usb-vbus";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved_memory: reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		scp_mem: memory@50000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x50000000 0 0x2900000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		adsp_mem: memory@60000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x60000000 0 0xd80000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		afe_mem: memory@60d80000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x60d80000 0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		adsp_device_mem: memory@60e80000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x60e80000 0 0x280000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spk_amplifier: rt1019p {</div><div class='add'>+		compatible = "realtek,rt1019p";</div><div class='add'>+		label = "rt1019p";</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;rt1019p_pins_default&gt;;</div><div class='add'>+		sdb-gpios = &lt;&amp;pio 100 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;adsp {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	memory-region = &lt;&amp;adsp_device_mem&gt;, &lt;&amp;adsp_mem&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;afe {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mediatek,etdm-in2-cowork-source = &lt;2&gt;;</div><div class='add'>+	mediatek,etdm-out2-cowork-source = &lt;0&gt;;</div><div class='add'>+	memory-region = &lt;&amp;afe_mem&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;auxadc {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	cpu-supply = &lt;&amp;mt6359_vcore_buck_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu1 {</div><div class='add'>+	cpu-supply = &lt;&amp;mt6359_vcore_buck_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu2 {</div><div class='add'>+	cpu-supply = &lt;&amp;mt6359_vcore_buck_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu3 {</div><div class='add'>+	cpu-supply = &lt;&amp;mt6359_vcore_buck_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu4 {</div><div class='add'>+	cpu-supply = &lt;&amp;mt6315_6_vbuck1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu5 {</div><div class='add'>+	cpu-supply = &lt;&amp;mt6315_6_vbuck1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu6 {</div><div class='add'>+	cpu-supply = &lt;&amp;mt6315_6_vbuck1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu7 {</div><div class='add'>+	cpu-supply = &lt;&amp;mt6315_6_vbuck1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dither0_out {</div><div class='add'>+	remote-endpoint = &lt;&amp;dsc0_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dp_intf0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		port@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			dp_intf0_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;merge0_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			dp_intf0_out: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;edp_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dp_intf1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		port@0 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			dp_intf1_in: endpoint@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				remote-endpoint = &lt;&amp;merge5_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@1 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			dp_intf1_out: endpoint@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				remote-endpoint = &lt;&amp;dptx_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsc0 {</div><div class='add'>+	ports {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		port@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			dsc0_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;dither0_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			dsc0_out: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;merge0_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;edp_tx {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;edptx_pins_default&gt;;</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		port@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			edp_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;dp_intf0_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			edp_out: endpoint {</div><div class='add'>+				data-lanes = &lt;0 1 2 3&gt;;</div><div class='add'>+				remote-endpoint = &lt;&amp;panel_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aux-bus {</div><div class='add'>+		panel {</div><div class='add'>+			compatible = "edp-panel";</div><div class='add'>+			power-supply = &lt;&amp;pp3300_disp_x&gt;;</div><div class='add'>+			backlight = &lt;&amp;backlight_lcd0&gt;;</div><div class='add'>+			port {</div><div class='add'>+				panel_in: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;edp_out&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethdr0 {</div><div class='add'>+	ports {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		port@0 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			ethdr0_in: endpoint@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				remote-endpoint = &lt;&amp;vdosys1_ep_ext&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@1 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			ethdr0_out: endpoint@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				remote-endpoint = &lt;&amp;merge5_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;disp_pwm0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;disp_pwm0_pin_default&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dp_tx {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;dptx_pin&gt;;</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		port@0 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			dptx_in: endpoint@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				remote-endpoint = &lt;&amp;dp_intf1_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			dptx_out: endpoint {</div><div class='add'>+				data-lanes = &lt;0 1 2 3&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gic {</div><div class='add'>+	mediatek,broken-save-restore-fw;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	status = "okay";</div><div class='add'>+	mali-supply = &lt;&amp;mt6315_7_vbuck1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c0_pins&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	i2c-scl-internal-delay-ns = &lt;12500&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c1_pins&gt;;</div><div class='add'>+</div><div class='add'>+	trackpad@15 {</div><div class='add'>+		compatible = "elan,ekth3000";</div><div class='add'>+		reg = &lt;0x15&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 6 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;trackpad_pins&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;pp3300_s3&gt;;</div><div class='add'>+		wakeup-source;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c2_pins&gt;;</div><div class='add'>+</div><div class='add'>+	audio_codec: codec@1a {</div><div class='add'>+		/* Realtek RT5682i or RT5682s, sharing the same configuration */</div><div class='add'>+		reg = &lt;0x1a&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 89 IRQ_TYPE_EDGE_BOTH&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+		realtek,jd-src = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		AVDD-supply = &lt;&amp;mt6359_vio18_ldo_reg&gt;;</div><div class='add'>+		DBVDD-supply = &lt;&amp;mt6359_vio18_ldo_reg&gt;;</div><div class='add'>+		MICVDD-supply = &lt;&amp;pp3300_z2&gt;;</div><div class='add'>+		LDO1-IN-supply = &lt;&amp;mt6359_vio18_ldo_reg&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c3_pins&gt;;</div><div class='add'>+</div><div class='add'>+	tpm@50 {</div><div class='add'>+		compatible = "google,cr50";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 88 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;cr50_int&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c4_pins&gt;;</div><div class='add'>+</div><div class='add'>+	ts_10: touchscreen@10 {</div><div class='add'>+		compatible = "hid-over-i2c";</div><div class='add'>+		reg = &lt;0x10&gt;;</div><div class='add'>+		hid-descr-addr = &lt;0x0001&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 92 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;touchscreen_pins&gt;;</div><div class='add'>+		post-power-on-delay-ms = &lt;10&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;pp3300_s3&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c5 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c5_pins&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c7 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c7_pins&gt;;</div><div class='add'>+</div><div class='add'>+	pmic@34 {</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		compatible = "mediatek,mt6360";</div><div class='add'>+		reg = &lt;0x34&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 130 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		interrupt-names = "IRQB";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;subpmic_default&gt;;</div><div class='add'>+		wakeup-source;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;merge0 {</div><div class='add'>+	ports {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		port@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			merge0_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;dsc0_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			merge0_out: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;dp_intf0_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;merge5 {</div><div class='add'>+	ports {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		port@0 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			merge5_in: endpoint@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				remote-endpoint = &lt;&amp;ethdr0_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@1 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			merge5_out: endpoint@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				remote-endpoint = &lt;&amp;dp_intf1_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mfg0 {</div><div class='add'>+	domain-supply = &lt;&amp;mt6315_7_vbuck1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mfg1 {</div><div class='add'>+	domain-supply = &lt;&amp;mt6359_vsram_others_ldo_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	cap-mmc-highspeed;</div><div class='add'>+	cap-mmc-hw-reset;</div><div class='add'>+	hs400-ds-delay = &lt;0x14c11&gt;;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	mmc-hs400-1_8v;</div><div class='add'>+	no-sdio;</div><div class='add'>+	no-sd;</div><div class='add'>+	non-removable;</div><div class='add'>+	pinctrl-names = "default", "state_uhs";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc0_pins_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;mmc0_pins_uhs&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;mt6359_vemc_1_ldo_reg&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;mt6359_vufs_ldo_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	cd-gpios = &lt;&amp;pio 54 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	no-mmc;</div><div class='add'>+	no-sdio;</div><div class='add'>+	pinctrl-names = "default", "state_uhs";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc1_pins_default&gt;, &lt;&amp;mmc1_pins_detect&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;mmc1_pins_default&gt;;</div><div class='add'>+	sd-uhs-sdr50;</div><div class='add'>+	sd-uhs-sdr104;</div><div class='add'>+	vmmc-supply = &lt;&amp;mt_pmic_vmch_ldo_reg&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;mt_pmic_vmc_ldo_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359codec {</div><div class='add'>+	mediatek,dmic-mode = &lt;1&gt;;  /* one-wire */</div><div class='add'>+	mediatek,mic-type-0 = &lt;2&gt;; /* DMIC */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* for CPU-L */</div><div class='add'>+&amp;mt6359_vcore_buck_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* for CORE */</div><div class='add'>+&amp;mt6359_vgpu11_buck_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vgpu11_sshub_buck_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+	regulator-min-microvolt = &lt;550000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;550000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* for CORE SRAM */</div><div class='add'>+&amp;mt6359_vpu_buck_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vrf12_ldo_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* for GPU SRAM */</div><div class='add'>+&amp;mt6359_vsram_others_ldo_reg {</div><div class='add'>+	regulator-min-microvolt = &lt;750000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;750000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vufs_ldo_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;nor_flash {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;nor_pins_default&gt;;</div><div class='add'>+</div><div class='add'>+	flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;52000000&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;2&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ovl0_in {</div><div class='add'>+	remote-endpoint = &lt;&amp;vdosys0_ep_main&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pcie1_pins_default&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	mediatek,rsel-resistance-in-si-unit;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pio_default&gt;;</div><div class='add'>+</div><div class='add'>+	/* 144 lines */</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"I2S_SPKR_MCLK",</div><div class='add'>+		"I2S_SPKR_DATAIN",</div><div class='add'>+		"I2S_SPKR_LRCK",</div><div class='add'>+		"I2S_SPKR_BCLK",</div><div class='add'>+		"EC_AP_INT_ODL",</div><div class='add'>+		/*</div><div class='add'>+		 * AP_FLASH_WP_L is crossystem ABI. Schematics</div><div class='add'>+		 * call it AP_FLASH_WP_ODL.</div><div class='add'>+		 */</div><div class='add'>+		"AP_FLASH_WP_L",</div><div class='add'>+		"TCHPAD_INT_ODL",</div><div class='add'>+		"EDP_HPD_1V8",</div><div class='add'>+		"AP_I2C_CAM_SDA",</div><div class='add'>+		"AP_I2C_CAM_SCL",</div><div class='add'>+		"AP_I2C_TCHPAD_SDA_1V8",</div><div class='add'>+		"AP_I2C_TCHPAD_SCL_1V8",</div><div class='add'>+		"AP_I2C_AUD_SDA",</div><div class='add'>+		"AP_I2C_AUD_SCL",</div><div class='add'>+		"AP_I2C_TPM_SDA_1V8",</div><div class='add'>+		"AP_I2C_TPM_SCL_1V8",</div><div class='add'>+		"AP_I2C_TCHSCR_SDA_1V8",</div><div class='add'>+		"AP_I2C_TCHSCR_SCL_1V8",</div><div class='add'>+		"EC_AP_HPD_OD",</div><div class='add'>+		"",</div><div class='add'>+		"PCIE_NVME_RST_L",</div><div class='add'>+		"PCIE_NVME_CLKREQ_ODL",</div><div class='add'>+		"PCIE_RST_1V8_L",</div><div class='add'>+		"PCIE_CLKREQ_1V8_ODL",</div><div class='add'>+		"PCIE_WAKE_1V8_ODL",</div><div class='add'>+		"CLK_24M_CAM0",</div><div class='add'>+		"CAM1_SEN_EN",</div><div class='add'>+		"AP_I2C_PWR_SCL_1V8",</div><div class='add'>+		"AP_I2C_PWR_SDA_1V8",</div><div class='add'>+		"AP_I2C_MISC_SCL",</div><div class='add'>+		"AP_I2C_MISC_SDA",</div><div class='add'>+		"EN_PP5000_HDMI_X",</div><div class='add'>+		"AP_HDMITX_HTPLG",</div><div class='add'>+		"",</div><div class='add'>+		"AP_HDMITX_SCL_1V8",</div><div class='add'>+		"AP_HDMITX_SDA_1V8",</div><div class='add'>+		"AP_RTC_CLK32K",</div><div class='add'>+		"AP_EC_WATCHDOG_L",</div><div class='add'>+		"SRCLKENA0",</div><div class='add'>+		"SRCLKENA1",</div><div class='add'>+		"PWRAP_SPI0_CS_L",</div><div class='add'>+		"PWRAP_SPI0_CK",</div><div class='add'>+		"PWRAP_SPI0_MOSI",</div><div class='add'>+		"PWRAP_SPI0_MISO",</div><div class='add'>+		"SPMI_SCL",</div><div class='add'>+		"SPMI_SDA",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"I2S_HP_DATAIN",</div><div class='add'>+		"I2S_HP_MCLK",</div><div class='add'>+		"I2S_HP_BCK",</div><div class='add'>+		"I2S_HP_LRCK",</div><div class='add'>+		"I2S_HP_DATAOUT",</div><div class='add'>+		"SD_CD_ODL",</div><div class='add'>+		"EN_PP3300_DISP_X",</div><div class='add'>+		"TCHSCR_RST_1V8_L",</div><div class='add'>+		"TCHSCR_REPORT_DISABLE",</div><div class='add'>+		"EN_PP3300_WLAN_X",</div><div class='add'>+		"BT_KILL_1V8_L",</div><div class='add'>+		"I2S_SPKR_DATAOUT",</div><div class='add'>+		"WIFI_KILL_1V8_L",</div><div class='add'>+		"BEEP_ON",</div><div class='add'>+		"SCP_I2C_SENSOR_SCL_1V8",</div><div class='add'>+		"SCP_I2C_SENSOR_SDA_1V8",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"AUD_CLK_MOSI",</div><div class='add'>+		"AUD_SYNC_MOSI",</div><div class='add'>+		"AUD_DAT_MOSI0",</div><div class='add'>+		"AUD_DAT_MOSI1",</div><div class='add'>+		"AUD_DAT_MISO0",</div><div class='add'>+		"AUD_DAT_MISO1",</div><div class='add'>+		"AUD_DAT_MISO2",</div><div class='add'>+		"SCP_VREQ_VAO",</div><div class='add'>+		"AP_SPI_GSC_TPM_CLK",</div><div class='add'>+		"AP_SPI_GSC_TPM_MOSI",</div><div class='add'>+		"AP_SPI_GSC_TPM_CS_L",</div><div class='add'>+		"AP_SPI_GSC_TPM_MISO",</div><div class='add'>+		"EN_PP1000_CAM_X",</div><div class='add'>+		"AP_EDP_BKLTEN",</div><div class='add'>+		"",</div><div class='add'>+		"USB3_HUB_RST_L",</div><div class='add'>+		"",</div><div class='add'>+		"WLAN_ALERT_ODL",</div><div class='add'>+		"EC_IN_RW_ODL",</div><div class='add'>+		"GSC_AP_INT_ODL",</div><div class='add'>+		"HP_INT_ODL",</div><div class='add'>+		"CAM0_RST_L",</div><div class='add'>+		"CAM1_RST_L",</div><div class='add'>+		"TCHSCR_INT_1V8_L",</div><div class='add'>+		"CAM1_DET_L",</div><div class='add'>+		"RST_ALC1011_L",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"BL_PWM_1V8",</div><div class='add'>+		"UART_AP_TX_DBG_RX",</div><div class='add'>+		"UART_DBG_TX_AP_RX",</div><div class='add'>+		"EN_SPKR",</div><div class='add'>+		"AP_EC_WARM_RST_REQ",</div><div class='add'>+		"UART_SCP_TX_DBGCON_RX",</div><div class='add'>+		"UART_DBGCON_TX_SCP_RX",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"KPCOL0",</div><div class='add'>+		"",</div><div class='add'>+		"MT6315_GPU_INT",</div><div class='add'>+		"MT6315_PROC_BC_INT",</div><div class='add'>+		"SD_CMD",</div><div class='add'>+		"SD_CLK",</div><div class='add'>+		"SD_DAT0",</div><div class='add'>+		"SD_DAT1",</div><div class='add'>+		"SD_DAT2",</div><div class='add'>+		"SD_DAT3",</div><div class='add'>+		"EMMC_DAT7",</div><div class='add'>+		"EMMC_DAT6",</div><div class='add'>+		"EMMC_DAT5",</div><div class='add'>+		"EMMC_DAT4",</div><div class='add'>+		"EMMC_RSTB",</div><div class='add'>+		"EMMC_CMD",</div><div class='add'>+		"EMMC_CLK",</div><div class='add'>+		"EMMC_DAT3",</div><div class='add'>+		"EMMC_DAT2",</div><div class='add'>+		"EMMC_DAT1",</div><div class='add'>+		"EMMC_DAT0",</div><div class='add'>+		"EMMC_DSL",</div><div class='add'>+		"",</div><div class='add'>+		"",</div><div class='add'>+		"MT6360_INT_ODL",</div><div class='add'>+		"SCP_JTAG0_TRSTN",</div><div class='add'>+		"AP_SPI_EC_CS_L",</div><div class='add'>+		"AP_SPI_EC_CLK",</div><div class='add'>+		"AP_SPI_EC_MOSI",</div><div class='add'>+		"AP_SPI_EC_MISO",</div><div class='add'>+		"SCP_JTAG0_TMS",</div><div class='add'>+		"SCP_JTAG0_TCK",</div><div class='add'>+		"SCP_JTAG0_TDO",</div><div class='add'>+		"SCP_JTAG0_TDI",</div><div class='add'>+		"AP_SPI_FLASH_CS_L",</div><div class='add'>+		"AP_SPI_FLASH_CLK",</div><div class='add'>+		"AP_SPI_FLASH_MOSI",</div><div class='add'>+		"AP_SPI_FLASH_MISO";</div><div class='add'>+</div><div class='add'>+	aud_pins_default: audio-default-pins {</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+		    pinmux = &lt;PINMUX_GPIO69__FUNC_AUD_CLK_MOSI&gt;,</div><div class='add'>+			     &lt;PINMUX_GPIO70__FUNC_AUD_SYNC_MOSI&gt;,</div><div class='add'>+			     &lt;PINMUX_GPIO71__FUNC_AUD_DAT_MOSI0&gt;,</div><div class='add'>+			     &lt;PINMUX_GPIO72__FUNC_AUD_DAT_MOSI1&gt;,</div><div class='add'>+			     &lt;PINMUX_GPIO73__FUNC_AUD_DAT_MISO0&gt;,</div><div class='add'>+			     &lt;PINMUX_GPIO74__FUNC_AUD_DAT_MISO1&gt;,</div><div class='add'>+			     &lt;PINMUX_GPIO75__FUNC_AUD_DAT_MISO2&gt;,</div><div class='add'>+			     &lt;PINMUX_GPIO0__FUNC_TDMIN_MCK&gt;,</div><div class='add'>+			     &lt;PINMUX_GPIO1__FUNC_TDMIN_DI&gt;,</div><div class='add'>+			     &lt;PINMUX_GPIO2__FUNC_TDMIN_LRCK&gt;,</div><div class='add'>+			     &lt;PINMUX_GPIO3__FUNC_TDMIN_BCK&gt;,</div><div class='add'>+			     &lt;PINMUX_GPIO60__FUNC_I2SO2_D0&gt;,</div><div class='add'>+			     &lt;PINMUX_GPIO49__FUNC_I2SIN_D0&gt;,</div><div class='add'>+			     &lt;PINMUX_GPIO50__FUNC_I2SO1_MCK&gt;,</div><div class='add'>+			     &lt;PINMUX_GPIO51__FUNC_I2SO1_BCK&gt;,</div><div class='add'>+			     &lt;PINMUX_GPIO52__FUNC_I2SO1_WS&gt;,</div><div class='add'>+			     &lt;PINMUX_GPIO53__FUNC_I2SO1_D0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-hp-jack-int-odl {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO89__FUNC_GPIO89&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cr50_int: cr50-irq-default-pins {</div><div class='add'>+		pins-gsc-ap-int-odl {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO88__FUNC_GPIO88&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cros_ec_int: cros-ec-irq-default-pins {</div><div class='add'>+		pins-ec-ap-int-odl {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO4__FUNC_GPIO4&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	edptx_pins_default: edptx-default-pins {</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO7__FUNC_EDP_TX_HPD&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	disp_pwm0_pin_default: disp-pwm0-default-pins {</div><div class='add'>+		pins-disp-pwm {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO82__FUNC_GPIO82&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO97__FUNC_DISP_PWM0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dptx_pin: dptx-default-pins {</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO18__FUNC_DP_TX_HPD&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c0_pins: i2c0-default-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO8__FUNC_SDA0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO9__FUNC_SCL0&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+			drive-strength-microamp = &lt;1000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c1_pins: i2c1-default-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO10__FUNC_SDA1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO11__FUNC_SCL1&gt;;</div><div class='add'>+			bias-pull-up = &lt;1000&gt;;</div><div class='add'>+			drive-strength-microamp = &lt;1000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c2_pins: i2c2-default-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO12__FUNC_SDA2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO13__FUNC_SCL2&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+			drive-strength-microamp = &lt;1000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c3_pins: i2c3-default-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO14__FUNC_SDA3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO15__FUNC_SCL3&gt;;</div><div class='add'>+			bias-pull-up = &lt;1000&gt;;</div><div class='add'>+			drive-strength-microamp = &lt;1000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c4_pins: i2c4-default-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO16__FUNC_SDA4&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO17__FUNC_SCL4&gt;;</div><div class='add'>+			bias-pull-up = &lt;1000&gt;;</div><div class='add'>+			drive-strength = &lt;4&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c5_pins: i2c5-default-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO29__FUNC_SCL5&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO30__FUNC_SDA5&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+			drive-strength-microamp = &lt;1000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c7_pins: i2c7-default-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO27__FUNC_SCL7&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO28__FUNC_SDA7&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc0_pins_default: mmc0-default-pins {</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO126__FUNC_MSDC0_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO125__FUNC_MSDC0_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO124__FUNC_MSDC0_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO123__FUNC_MSDC0_DAT3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO119__FUNC_MSDC0_DAT4&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO118__FUNC_MSDC0_DAT5&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO117__FUNC_MSDC0_DAT6&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO116__FUNC_MSDC0_DAT7&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO121__FUNC_MSDC0_CMD&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO122__FUNC_MSDC0_CLK&gt;;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-rst {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO120__FUNC_MSDC0_RSTB&gt;;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc0_pins_uhs: mmc0-uhs-pins {</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO126__FUNC_MSDC0_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO125__FUNC_MSDC0_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO124__FUNC_MSDC0_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO123__FUNC_MSDC0_DAT3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO119__FUNC_MSDC0_DAT4&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO118__FUNC_MSDC0_DAT5&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO117__FUNC_MSDC0_DAT6&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO116__FUNC_MSDC0_DAT7&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO121__FUNC_MSDC0_CMD&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO122__FUNC_MSDC0_CLK&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-ds {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO127__FUNC_MSDC0_DSL&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-rst {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO120__FUNC_MSDC0_RSTB&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc1_pins_detect: mmc1-detect-pins {</div><div class='add'>+		pins-insert {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO54__FUNC_GPIO54&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc1_pins_default: mmc1-default-pins {</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO110__FUNC_MSDC1_CMD&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO112__FUNC_MSDC1_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO113__FUNC_MSDC1_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO114__FUNC_MSDC1_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO115__FUNC_MSDC1_DAT3&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO111__FUNC_MSDC1_CLK&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	nor_pins_default: nor-default-pins {</div><div class='add'>+		pins-ck-io {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO142__FUNC_SPINOR_IO0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO141__FUNC_SPINOR_CK&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO143__FUNC_SPINOR_IO1&gt;;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-down;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-cs {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO140__FUNC_SPINOR_CS&gt;;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_pins_default: pcie0-default-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO19__FUNC_WAKEN&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO20__FUNC_PERSTN&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO21__FUNC_CLKREQN&gt;;</div><div class='add'>+				 bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie1_pins_default: pcie1-default-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO22__FUNC_PERSTN_1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO23__FUNC_CLKREQN_1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO24__FUNC_WAKEN_1&gt;;</div><div class='add'>+				 bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	panel_fixed_pins: panel-pwr-default-pins {</div><div class='add'>+		pins-vreg-en {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO55__FUNC_GPIO55&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pio_default: pio-default-pins {</div><div class='add'>+		pins-wifi-enable {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO58__FUNC_GPIO58&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+			drive-strength = &lt;14&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-low-power-pd {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO25__FUNC_GPIO25&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO26__FUNC_GPIO26&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO46__FUNC_GPIO46&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO47__FUNC_GPIO47&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO48__FUNC_GPIO48&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO65__FUNC_GPIO65&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO66__FUNC_GPIO66&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO67__FUNC_GPIO67&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO68__FUNC_GPIO68&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO128__FUNC_GPIO128&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO129__FUNC_GPIO129&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-down;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-low-power-pupd {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO77__FUNC_GPIO77&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO78__FUNC_GPIO78&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO79__FUNC_GPIO79&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO80__FUNC_GPIO80&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO83__FUNC_GPIO83&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO85__FUNC_GPIO85&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO90__FUNC_GPIO90&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO91__FUNC_GPIO91&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO93__FUNC_GPIO93&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO94__FUNC_GPIO94&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO95__FUNC_GPIO95&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO96__FUNC_GPIO96&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO104__FUNC_GPIO104&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO105__FUNC_GPIO105&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO107__FUNC_GPIO107&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rt1019p_pins_default: rt1019p-default-pins {</div><div class='add'>+		pins-amp-sdb {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO100__FUNC_GPIO100&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	scp_pins: scp-default-pins {</div><div class='add'>+		pins-vreq {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO76__FUNC_SCP_VREQ_VAO&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi0_pins: spi0-default-pins {</div><div class='add'>+		pins-cs-mosi-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO132__FUNC_SPIM0_CSB&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO134__FUNC_SPIM0_MO&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO133__FUNC_SPIM0_CLK&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-miso {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO135__FUNC_SPIM0_MI&gt;;</div><div class='add'>+			bias-pull-down;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	subpmic_default: subpmic-default-pins {</div><div class='add'>+		subpmic_pin_irq: pins-subpmic-int-n {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO130__FUNC_GPIO130&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	trackpad_pins: trackpad-default-pins {</div><div class='add'>+		pins-int-n {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO6__FUNC_GPIO6&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	touchscreen_pins: touchscreen-default-pins {</div><div class='add'>+		pins-int-n {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO92__FUNC_GPIO92&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+		pins-rst {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO56__FUNC_GPIO56&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+		pins-report-sw {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO57__FUNC_GPIO57&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pmic {</div><div class='add'>+	interrupts-extended = &lt;&amp;pio 222 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;scp {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	firmware-name = "mediatek/mt8195/scp.img";</div><div class='add'>+	memory-region = &lt;&amp;scp_mem&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;scp_pins&gt;;</div><div class='add'>+</div><div class='add'>+	cros-ec-rpmsg {</div><div class='add'>+		compatible = "google,cros-ec-rpmsg";</div><div class='add'>+		mediatek,rpmsg-name = "cros-ec-rpmsg";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sound {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mediatek,adsp = &lt;&amp;adsp&gt;;</div><div class='add'>+	mediatek,dai-link =</div><div class='add'>+		"DL10_FE", "DPTX_BE", "ETDM1_IN_BE", "ETDM2_IN_BE",</div><div class='add'>+		"ETDM1_OUT_BE", "ETDM2_OUT_BE","UL_SRC1_BE",</div><div class='add'>+		"AFE_SOF_DL2", "AFE_SOF_DL3", "AFE_SOF_UL4", "AFE_SOF_UL5";</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;aud_pins_default&gt;;</div><div class='add'>+</div><div class='add'>+	audio-routing =</div><div class='add'>+		"Headphone", "HPOL",</div><div class='add'>+		"Headphone", "HPOR",</div><div class='add'>+		"IN1P", "Headset Mic",</div><div class='add'>+		"Ext Spk", "Speaker";</div><div class='add'>+</div><div class='add'>+	mm-dai-link {</div><div class='add'>+		link-name = "ETDM1_IN_BE";</div><div class='add'>+		mediatek,clk-provider = "cpu";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hs-playback-dai-link {</div><div class='add'>+		link-name = "ETDM1_OUT_BE";</div><div class='add'>+		mediatek,clk-provider = "cpu";</div><div class='add'>+		codec {</div><div class='add'>+			sound-dai = &lt;&amp;audio_codec 0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hs-capture-dai-link {</div><div class='add'>+		link-name = "ETDM2_IN_BE";</div><div class='add'>+		mediatek,clk-provider = "cpu";</div><div class='add'>+		codec {</div><div class='add'>+			sound-dai = &lt;&amp;audio_codec 0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spk-playback-dai-link {</div><div class='add'>+		link-name = "ETDM2_OUT_BE";</div><div class='add'>+		mediatek,clk-provider = "cpu";</div><div class='add'>+		codec {</div><div class='add'>+			sound-dai = &lt;&amp;spk_amplifier&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	displayport-dai-link {</div><div class='add'>+		link-name = "DPTX_BE";</div><div class='add'>+		codec {</div><div class='add'>+			sound-dai = &lt;&amp;dp_tx&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;spi0_pins&gt;;</div><div class='add'>+	mediatek,pad-select = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	cros_ec: ec@0 {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		compatible = "google,cros-ec-spi";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 4 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;cros_ec_int&gt;;</div><div class='add'>+		spi-max-frequency = &lt;3000000&gt;;</div><div class='add'>+		wakeup-source;</div><div class='add'>+</div><div class='add'>+		i2c_tunnel: i2c-tunnel {</div><div class='add'>+			compatible = "google,cros-ec-i2c-tunnel";</div><div class='add'>+			google,remote-bus = &lt;0&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mt_pmic_vmc_ldo_reg: regulator@0 {</div><div class='add'>+			compatible = "google,cros-ec-regulator";</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			regulator-name = "mt_pmic_vmc_ldo";</div><div class='add'>+			regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;3600000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mt_pmic_vmch_ldo_reg: regulator@1 {</div><div class='add'>+			compatible = "google,cros-ec-regulator";</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			regulator-name = "mt_pmic_vmch_ldo";</div><div class='add'>+			regulator-min-microvolt = &lt;2700000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;3600000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		typec {</div><div class='add'>+			compatible = "google,cros-ec-typec";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			usb_c0: connector@0 {</div><div class='add'>+				compatible = "usb-c-connector";</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				power-role = "dual";</div><div class='add'>+				data-role = "host";</div><div class='add'>+				try-power-role = "source";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			usb_c1: connector@1 {</div><div class='add'>+				compatible = "usb-c-connector";</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				power-role = "dual";</div><div class='add'>+				data-role = "host";</div><div class='add'>+				try-power-role = "source";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spmi {</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	mt6315@6 {</div><div class='add'>+		compatible = "mediatek,mt6315-regulator";</div><div class='add'>+		reg = &lt;0x6 SPMI_USID&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			mt6315_6_vbuck1: vbuck1 {</div><div class='add'>+				regulator-name = "Vbcpu";</div><div class='add'>+				regulator-min-microvolt = &lt;400000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1193750&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;256&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;6250&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;0 1 2&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mt6315@7 {</div><div class='add'>+		compatible = "mediatek,mt6315-regulator";</div><div class='add'>+		reg = &lt;0x7 SPMI_USID&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			mt6315_7_vbuck1: vbuck1 {</div><div class='add'>+				regulator-name = "Vgpu";</div><div class='add'>+				regulator-min-microvolt = &lt;400000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1193750&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;256&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;6250&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;0 1 2&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;thermal_zones {</div><div class='add'>+	soc-area-thermal {</div><div class='add'>+		polling-delay = &lt;1000&gt;;</div><div class='add'>+		polling-delay-passive = &lt;250&gt;;</div><div class='add'>+		thermal-sensors = &lt;&amp;tboard_thermistor1&gt;;</div><div class='add'>+</div><div class='add'>+		trips {</div><div class='add'>+			trip-crit {</div><div class='add'>+				temperature = &lt;84000&gt;;</div><div class='add'>+				hysteresis = &lt;1000&gt;;</div><div class='add'>+				type = "critical";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmic-area-thermal {</div><div class='add'>+		polling-delay = &lt;1000&gt;;</div><div class='add'>+		polling-delay-passive = &lt;0&gt;;</div><div class='add'>+		thermal-sensors = &lt;&amp;tboard_thermistor2&gt;;</div><div class='add'>+</div><div class='add'>+		trips {</div><div class='add'>+			trip-crit {</div><div class='add'>+				temperature = &lt;84000&gt;;</div><div class='add'>+				hysteresis = &lt;1000&gt;;</div><div class='add'>+				type = "critical";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;u3phy0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;u3phy1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;u3phy2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;u3phy3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;vdosys0 {</div><div class='add'>+	port {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		vdosys0_ep_main: endpoint@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			remote-endpoint = &lt;&amp;ovl0_in&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * For the USB Type-C ports the role and alternate modes switching is</div><div class='add'>+ * done by the EC so we set dr_mode to host to avoid interfering.</div><div class='add'>+ */</div><div class='add'>+&amp;ssusb0 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	vusb33-supply = &lt;&amp;mt6359_vusb_ldo_reg&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ssusb2 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	vusb33-supply = &lt;&amp;mt6359_vusb_ldo_reg&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ssusb3 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	vusb33-supply = &lt;&amp;mt6359_vusb_ldo_reg&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;vdosys1 {</div><div class='add'>+	port {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		vdosys1_ep_ext: endpoint@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			remote-endpoint = &lt;&amp;ethdr0_in&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xhci0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	rx-fifo-depth = &lt;3072&gt;;</div><div class='add'>+	vbus-supply = &lt;&amp;usb_vbus&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xhci1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	phys = &lt;&amp;u2port1 PHY_TYPE_USB2&gt;;</div><div class='add'>+	rx-fifo-depth = &lt;3072&gt;;</div><div class='add'>+	vusb33-supply = &lt;&amp;mt6359_vusb_ldo_reg&gt;;</div><div class='add'>+	vbus-supply = &lt;&amp;usb_vbus&gt;;</div><div class='add'>+	mediatek,u3p-dis-msk = &lt;1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xhci2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	vbus-supply = &lt;&amp;usb_vbus&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xhci3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* MT7921's USB Bluetooth has issues with USB2 LPM */</div><div class='add'>+	usb2-lpm-disable;</div><div class='add'>+	vbus-supply = &lt;&amp;usb_vbus&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include &lt;arm/cros-ec-keyboard.dtsi&gt;</div><div class='add'>+#include &lt;arm/cros-ec-sbs.dtsi&gt;</div><div class='add'>+</div><div class='add'>+&amp;keyboard_controller {</div><div class='add'>+	function-row-physmap = &lt;</div><div class='add'>+		MATRIX_KEY(0x00, 0x02, 0)	/* T1 */</div><div class='add'>+		MATRIX_KEY(0x03, 0x02, 0)	/* T2 */</div><div class='add'>+		MATRIX_KEY(0x02, 0x02, 0)	/* T3 */</div><div class='add'>+		MATRIX_KEY(0x01, 0x02, 0)	/* T4 */</div><div class='add'>+		MATRIX_KEY(0x03, 0x04, 0)	/* T5 */</div><div class='add'>+		MATRIX_KEY(0x02, 0x04, 0)	/* T6 */</div><div class='add'>+		MATRIX_KEY(0x01, 0x04, 0)	/* T7 */</div><div class='add'>+		MATRIX_KEY(0x02, 0x09, 0)	/* T8 */</div><div class='add'>+		MATRIX_KEY(0x01, 0x09, 0)	/* T9 */</div><div class='add'>+		MATRIX_KEY(0x00, 0x04, 0)	/* T10 */</div><div class='add'>+</div><div class='add'>+		/* T11 to T13 are present only on Dojo */</div><div class='add'>+		MATRIX_KEY(0x00, 0x01, 0)	/* T11 */</div><div class='add'>+		MATRIX_KEY(0x01, 0x05, 0)	/* T12 */</div><div class='add'>+		MATRIX_KEY(0x03, 0x05, 0)	/* T13 */</div><div class='add'>+	&gt;;</div><div class='add'>+</div><div class='add'>+	linux,keymap = &lt;</div><div class='add'>+		MATRIX_KEY(0x00, 0x02, KEY_BACK)</div><div class='add'>+		MATRIX_KEY(0x03, 0x02, KEY_REFRESH)</div><div class='add'>+		MATRIX_KEY(0x02, 0x02, KEY_ZOOM)</div><div class='add'>+		MATRIX_KEY(0x01, 0x02, KEY_SCALE)</div><div class='add'>+		MATRIX_KEY(0x03, 0x04, KEY_SYSRQ)</div><div class='add'>+		MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN)</div><div class='add'>+		MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP)</div><div class='add'>+		MATRIX_KEY(0x02, 0x09, KEY_MUTE)</div><div class='add'>+		MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)</div><div class='add'>+		MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)</div><div class='add'>+</div><div class='add'>+		CROS_STD_MAIN_KEYMAP</div><div class='add'>+	&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts<br/>new file mode 100644<br/>index 000000000000..1f59b5786b81<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8195-demo.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8195-demo.dts</a></div><div class='hunk'>@@ -0,0 +1,555 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2022 BayLibre, SAS.</div><div class='add'>+ * Author: Fabien Parent &lt;fparent@baylibre.com&gt;</div><div class='add'>+ */</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "mt8195.dtsi"</div><div class='add'>+#include "mt6359.dtsi"</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/mt8195-pinfunc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/regulator/mediatek,mt6360-regulator.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "MediaTek MT8195 demo board";</div><div class='add'>+	compatible = "mediatek,mt8195-demo", "mediatek,mt8195";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:921600n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	firmware {</div><div class='add'>+		optee {</div><div class='add'>+			compatible = "linaro,optee-tz";</div><div class='add'>+			method = "smc";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;gpio_keys_pins&gt;;</div><div class='add'>+</div><div class='add'>+		key-0 {</div><div class='add'>+			gpios = &lt;&amp;pio 106 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			label = "volume_up";</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+			debounce-interval = &lt;15&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0 0x40000000 0x2 0x00000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * 12 MiB reserved for OP-TEE (BL32)</div><div class='add'>+		 * +-----------------------+ 0x43e0_0000</div><div class='add'>+		 * |      SHMEM 2MiB       |</div><div class='add'>+		 * +-----------------------+ 0x43c0_0000</div><div class='add'>+		 * |        | TA_RAM  8MiB |</div><div class='add'>+		 * + TZDRAM +--------------+ 0x4340_0000</div><div class='add'>+		 * |        | TEE_RAM 2MiB |</div><div class='add'>+		 * +-----------------------+ 0x4320_0000</div><div class='add'>+		 */</div><div class='add'>+		optee_reserved: optee@43200000 {</div><div class='add'>+			no-map;</div><div class='add'>+			reg = &lt;0 0x43200000 0 0x00c00000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		scp_mem: memory@50000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x50000000 0 0x2900000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vpu_mem: memory@53000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x53000000 0 0x1400000&gt;; /* 20 MB */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* 2 MiB reserved for ARM Trusted Firmware (BL31) */</div><div class='add'>+		bl31_secmon_mem: memory@54600000 {</div><div class='add'>+			no-map;</div><div class='add'>+			reg = &lt;0 0x54600000 0x0 0x200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		snd_dma_mem: memory@60000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x60000000 0 0x1100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		apu_mem: memory@62000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x62000000 0 0x1400000&gt;; /* 20 MB */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eth {</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethernet_phy0&gt;;</div><div class='add'>+	snps,reset-gpio = &lt;&amp;pio 93 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	snps,reset-delays-us = &lt;0 10000 80000&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;eth_default_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;eth_sleep_pins&gt;;</div><div class='add'>+	mediatek,mac-wol;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		ethernet_phy0: ethernet-phy@1 {</div><div class='add'>+			reg = &lt;0x1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c6 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c6_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mt6360: pmic@34 {</div><div class='add'>+		compatible = "mediatek,mt6360";</div><div class='add'>+		reg = &lt;0x34&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 101 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		interrupt-names = "IRQB";</div><div class='add'>+</div><div class='add'>+		charger {</div><div class='add'>+			compatible = "mediatek,mt6360-chg";</div><div class='add'>+			richtek,vinovp-microvolt = &lt;14500000&gt;;</div><div class='add'>+</div><div class='add'>+			otg_vbus_regulator: usb-otg-vbus-regulator {</div><div class='add'>+				regulator-name = "usb-otg-vbus";</div><div class='add'>+				regulator-min-microvolt = &lt;4425000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;5825000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		regulator {</div><div class='add'>+			compatible = "mediatek,mt6360-regulator";</div><div class='add'>+			LDO_VIN3-supply = &lt;&amp;mt6360_buck2&gt;;</div><div class='add'>+</div><div class='add'>+			mt6360_buck1: buck1 {</div><div class='add'>+				regulator-name = "mt6360,buck1";</div><div class='add'>+				regulator-min-microvolt = &lt;300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;MT6360_OPMODE_NORMAL</div><div class='add'>+							   MT6360_OPMODE_LP</div><div class='add'>+							   MT6360_OPMODE_ULP&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6360_buck2: buck2 {</div><div class='add'>+				regulator-name = "mt6360,buck2";</div><div class='add'>+				regulator-min-microvolt = &lt;300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;MT6360_OPMODE_NORMAL</div><div class='add'>+							   MT6360_OPMODE_LP</div><div class='add'>+							   MT6360_OPMODE_ULP&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6360_ldo1: ldo1 {</div><div class='add'>+				regulator-name = "mt6360,ldo1";</div><div class='add'>+				regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3600000&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;MT6360_OPMODE_NORMAL</div><div class='add'>+							   MT6360_OPMODE_LP&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6360_ldo2: ldo2 {</div><div class='add'>+				regulator-name = "mt6360,ldo2";</div><div class='add'>+				regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3600000&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;MT6360_OPMODE_NORMAL</div><div class='add'>+							   MT6360_OPMODE_LP&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6360_ldo3: ldo3 {</div><div class='add'>+				regulator-name = "mt6360,ldo3";</div><div class='add'>+				regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3600000&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;MT6360_OPMODE_NORMAL</div><div class='add'>+							   MT6360_OPMODE_LP&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6360_ldo5: ldo5 {</div><div class='add'>+				regulator-name = "mt6360,ldo5";</div><div class='add'>+				regulator-min-microvolt = &lt;2700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3600000&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;MT6360_OPMODE_NORMAL</div><div class='add'>+							   MT6360_OPMODE_LP&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6360_ldo6: ldo6 {</div><div class='add'>+				regulator-name = "mt6360,ldo6";</div><div class='add'>+				regulator-min-microvolt = &lt;500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2100000&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;MT6360_OPMODE_NORMAL</div><div class='add'>+							   MT6360_OPMODE_LP&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6360_ldo7: ldo7 {</div><div class='add'>+				regulator-name = "mt6360,ldo7";</div><div class='add'>+				regulator-min-microvolt = &lt;500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2100000&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;MT6360_OPMODE_NORMAL</div><div class='add'>+							   MT6360_OPMODE_LP&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-names = "default", "state_uhs";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc0_default_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;mmc0_uhs_pins&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	cap-mmc-highspeed;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	mmc-hs400-1_8v;</div><div class='add'>+	cap-mmc-hw-reset;</div><div class='add'>+	no-sdio;</div><div class='add'>+	no-sd;</div><div class='add'>+	hs400-ds-delay = &lt;0x14c11&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;mt6359_vemc_1_ldo_reg&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;mt6359_vufs_ldo_reg&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc1 {</div><div class='add'>+	pinctrl-names = "default", "state_uhs";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc1_default_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;mmc1_uhs_pins&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;pio 129 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	sd-uhs-sdr50;</div><div class='add'>+	sd-uhs-sdr104;</div><div class='add'>+	vmmc-supply = &lt;&amp;mt6360_ldo5&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;mt6360_ldo3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vbbck_ldo_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vcore_buck_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vgpu11_buck_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vproc1_buck_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vproc2_buck_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vpu_buck_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vrf12_ldo_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vsram_md_ldo_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vsram_others_ldo_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	eth_default_pins: eth-default-pins {</div><div class='add'>+		pins-txd {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO77__FUNC_GBE_TXD3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO78__FUNC_GBE_TXD2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO79__FUNC_GBE_TXD1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO80__FUNC_GBE_TXD0&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+		};</div><div class='add'>+		pins-cc {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO85__FUNC_GBE_TXC&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO88__FUNC_GBE_TXEN&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO87__FUNC_GBE_RXDV&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO86__FUNC_GBE_RXC&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+		};</div><div class='add'>+		pins-rxd {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO81__FUNC_GBE_RXD3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO82__FUNC_GBE_RXD2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO83__FUNC_GBE_RXD1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO84__FUNC_GBE_RXD0&gt;;</div><div class='add'>+		};</div><div class='add'>+		pins-mdio {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO89__FUNC_GBE_MDC&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO90__FUNC_GBE_MDIO&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+		pins-power {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO91__FUNC_GPIO91&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO92__FUNC_GPIO92&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eth_sleep_pins: eth-sleep-pins {</div><div class='add'>+		pins-txd {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO77__FUNC_GPIO77&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO78__FUNC_GPIO78&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO79__FUNC_GPIO79&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO80__FUNC_GPIO80&gt;;</div><div class='add'>+		};</div><div class='add'>+		pins-cc {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO85__FUNC_GPIO85&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO88__FUNC_GPIO88&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO87__FUNC_GPIO87&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO86__FUNC_GPIO86&gt;;</div><div class='add'>+		};</div><div class='add'>+		pins-rxd {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO81__FUNC_GPIO81&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO82__FUNC_GPIO82&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO83__FUNC_GPIO83&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO84__FUNC_GPIO84&gt;;</div><div class='add'>+		};</div><div class='add'>+		pins-mdio {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO89__FUNC_GPIO89&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO90__FUNC_GPIO90&gt;;</div><div class='add'>+			input-disable;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio_keys_pins: gpio-keys-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO106__FUNC_GPIO106&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c6_pins: i2c6-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO25__FUNC_SDA6&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO26__FUNC_SCL6&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc0_default_pins: mmc0-default-pins {</div><div class='add'>+		pins-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO122__FUNC_MSDC0_CLK&gt;;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO126__FUNC_MSDC0_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO125__FUNC_MSDC0_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO124__FUNC_MSDC0_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO123__FUNC_MSDC0_DAT3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO119__FUNC_MSDC0_DAT4&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO118__FUNC_MSDC0_DAT5&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO117__FUNC_MSDC0_DAT6&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO116__FUNC_MSDC0_DAT7&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO121__FUNC_MSDC0_CMD&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-rst {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO120__FUNC_MSDC0_RSTB&gt;;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc0_uhs_pins: mmc0-uhs-pins {</div><div class='add'>+		pins-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO122__FUNC_MSDC0_CLK&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO126__FUNC_MSDC0_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO125__FUNC_MSDC0_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO124__FUNC_MSDC0_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO123__FUNC_MSDC0_DAT3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO119__FUNC_MSDC0_DAT4&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO118__FUNC_MSDC0_DAT5&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO117__FUNC_MSDC0_DAT6&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO116__FUNC_MSDC0_DAT7&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO121__FUNC_MSDC0_CMD&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-ds {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO127__FUNC_MSDC0_DSL&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-rst {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO120__FUNC_MSDC0_RSTB&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc1_default_pins: mmc1-default-pins {</div><div class='add'>+		pins-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO111__FUNC_MSDC1_CLK&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO110__FUNC_MSDC1_CMD&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO112__FUNC_MSDC1_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO113__FUNC_MSDC1_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO114__FUNC_MSDC1_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO115__FUNC_MSDC1_DAT3&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-insert {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO129__FUNC_GPIO129&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc1_uhs_pins: mmc1-uhs-pins {</div><div class='add'>+		pins-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO111__FUNC_MSDC1_CLK&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO110__FUNC_MSDC1_CMD&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO112__FUNC_MSDC1_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO113__FUNC_MSDC1_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO114__FUNC_MSDC1_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO115__FUNC_MSDC1_DAT3&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart0_pins: uart0-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO98__FUNC_UTXD0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO99__FUNC_URXD0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart1_pins: uart1-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO102__FUNC_UTXD1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO103__FUNC_URXD1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+&amp;pmic {</div><div class='add'>+	interrupts-extended = &lt;&amp;pio 222 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart0_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart1_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;u3phy0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;u3phy1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;u3phy2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;u3phy3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ssusb0 {</div><div class='add'>+	vusb33-supply = &lt;&amp;mt6359_vusb_ldo_reg&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ssusb2 {</div><div class='add'>+	vusb33-supply = &lt;&amp;mt6359_vusb_ldo_reg&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ssusb3 {</div><div class='add'>+	vusb33-supply = &lt;&amp;mt6359_vusb_ldo_reg&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xhci0 {</div><div class='add'>+	vbus-supply = &lt;&amp;otg_vbus_regulator&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xhci1 {</div><div class='add'>+	vusb33-supply = &lt;&amp;mt6359_vusb_ldo_reg&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xhci2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xhci3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts<br/>new file mode 100644<br/>index 000000000000..83456d649ff7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8195-evb.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8195-evb.dts</a></div><div class='hunk'>@@ -0,0 +1,191 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2021 MediaTek Inc.</div><div class='add'>+ * Author: Seiya Wang &lt;seiya.wang@mediatek.com&gt;</div><div class='add'>+ */</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8195.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "MediaTek MT8195 evaluation board";</div><div class='add'>+	compatible = "mediatek,mt8195-evb", "mediatek,mt8195";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:921600n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0 0x40000000 0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;auxadc {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c0_pin&gt;;</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c1_pin&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c4_pin&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c6 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c6_pin&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;nor_flash {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;nor_pins_default&gt;;</div><div class='add'>+</div><div class='add'>+	flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;50000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	i2c0_pin: i2c0-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO8__FUNC_SDA0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO9__FUNC_SCL0&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c1_pin: i2c1-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO10__FUNC_SDA1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO11__FUNC_SCL1&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c4_pin: i2c4-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO16__FUNC_SDA4&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO17__FUNC_SCL4&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+			drive-strength-microamp = &lt;1000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c6_pin: i2c6-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO25__FUNC_SDA6&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO26__FUNC_SCL6&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c7_pin: i2c7-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO27__FUNC_SCL7&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO28__FUNC_SDA7&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	nor_pins_default: nor-pins {</div><div class='add'>+		pins0 {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO142__FUNC_SPINOR_IO0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO141__FUNC_SPINOR_CK&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO143__FUNC_SPINOR_IO1&gt;;</div><div class='add'>+			bias-pull-down;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins1 {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO140__FUNC_SPINOR_CS&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO130__FUNC_SPINOR_IO2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO131__FUNC_SPINOR_IO3&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart0_pin: uart0-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO98__FUNC_UTXD0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO99__FUNC_URXD0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;u3phy0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;u3phy1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;u3phy2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;u3phy3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart0_pin&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ssusb0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ssusb2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ssusb3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xhci0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xhci1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xhci2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xhci3 {</div><div class='add'>+	/* This controller is connected with a BT device.</div><div class='add'>+	 * Disable usb2 lpm to prevent known issues.</div><div class='add'>+	 */</div><div class='add'>+	usb2-lpm-disable;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi<br/>new file mode 100644<br/>index 000000000000..c7adafaa8328<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8195.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8195.dtsi</a></div><div class='hunk'>@@ -0,0 +1,4177 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2021 MediaTek Inc.</div><div class='add'>+ * Author: Seiya Wang &lt;seiya.wang@mediatek.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include &lt;dt-bindings/clock/mt8195-clk.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gce/mt8195-gce.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/memory/mt8195-memory-port.h&gt;</div><div class='add'>+#include &lt;dt-bindings/phy/phy.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/mt8195-pinfunc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/power/mt8195-power.h&gt;</div><div class='add'>+#include &lt;dt-bindings/reset/mt8195-resets.h&gt;</div><div class='add'>+#include &lt;dt-bindings/thermal/thermal.h&gt;</div><div class='add'>+#include &lt;dt-bindings/thermal/mediatek,lvts-thermal.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "mediatek,mt8195";</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		dp-intf0 = &amp;dp_intf0;</div><div class='add'>+		dp-intf1 = &amp;dp_intf1;</div><div class='add'>+		gce0 = &amp;gce0;</div><div class='add'>+		gce1 = &amp;gce1;</div><div class='add'>+		ethdr0 = &amp;ethdr0;</div><div class='add'>+		mutex0 = &amp;mutex;</div><div class='add'>+		mutex1 = &amp;mutex1;</div><div class='add'>+		merge1 = &amp;merge1;</div><div class='add'>+		merge2 = &amp;merge2;</div><div class='add'>+		merge3 = &amp;merge3;</div><div class='add'>+		merge4 = &amp;merge4;</div><div class='add'>+		merge5 = &amp;merge5;</div><div class='add'>+		vdo1-rdma0 = &amp;vdo1_rdma0;</div><div class='add'>+		vdo1-rdma1 = &amp;vdo1_rdma1;</div><div class='add'>+		vdo1-rdma2 = &amp;vdo1_rdma2;</div><div class='add'>+		vdo1-rdma3 = &amp;vdo1_rdma3;</div><div class='add'>+		vdo1-rdma4 = &amp;vdo1_rdma4;</div><div class='add'>+		vdo1-rdma5 = &amp;vdo1_rdma5;</div><div class='add'>+		vdo1-rdma6 = &amp;vdo1_rdma6;</div><div class='add'>+		vdo1-rdma7 = &amp;vdo1_rdma7;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x000&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			performance-domains = &lt;&amp;performance 0&gt;;</div><div class='add'>+			clock-frequency = &lt;1701000000&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;308&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_ret_l &amp;cpu_off_l&gt;;</div><div class='add'>+			i-cache-size = &lt;32768&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;128&gt;;</div><div class='add'>+			d-cache-size = &lt;32768&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@100 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x100&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			performance-domains = &lt;&amp;performance 0&gt;;</div><div class='add'>+			clock-frequency = &lt;1701000000&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;308&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_ret_l &amp;cpu_off_l&gt;;</div><div class='add'>+			i-cache-size = &lt;32768&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;128&gt;;</div><div class='add'>+			d-cache-size = &lt;32768&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@200 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x200&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			performance-domains = &lt;&amp;performance 0&gt;;</div><div class='add'>+			clock-frequency = &lt;1701000000&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;308&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_ret_l &amp;cpu_off_l&gt;;</div><div class='add'>+			i-cache-size = &lt;32768&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;128&gt;;</div><div class='add'>+			d-cache-size = &lt;32768&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@300 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x300&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			performance-domains = &lt;&amp;performance 0&gt;;</div><div class='add'>+			clock-frequency = &lt;1701000000&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;308&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_ret_l &amp;cpu_off_l&gt;;</div><div class='add'>+			i-cache-size = &lt;32768&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;128&gt;;</div><div class='add'>+			d-cache-size = &lt;32768&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;128&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu4: cpu@400 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a78";</div><div class='add'>+			reg = &lt;0x400&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			performance-domains = &lt;&amp;performance 1&gt;;</div><div class='add'>+			clock-frequency = &lt;2171000000&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_ret_b &amp;cpu_off_b&gt;;</div><div class='add'>+			i-cache-size = &lt;65536&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;65536&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_1&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu5: cpu@500 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a78";</div><div class='add'>+			reg = &lt;0x500&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			performance-domains = &lt;&amp;performance 1&gt;;</div><div class='add'>+			clock-frequency = &lt;2171000000&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_ret_b &amp;cpu_off_b&gt;;</div><div class='add'>+			i-cache-size = &lt;65536&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;65536&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_1&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu6: cpu@600 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a78";</div><div class='add'>+			reg = &lt;0x600&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			performance-domains = &lt;&amp;performance 1&gt;;</div><div class='add'>+			clock-frequency = &lt;2171000000&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_ret_b &amp;cpu_off_b&gt;;</div><div class='add'>+			i-cache-size = &lt;65536&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;65536&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_1&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu7: cpu@700 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a78";</div><div class='add'>+			reg = &lt;0x700&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			performance-domains = &lt;&amp;performance 1&gt;;</div><div class='add'>+			clock-frequency = &lt;2171000000&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			cpu-idle-states = &lt;&amp;cpu_ret_b &amp;cpu_off_b&gt;;</div><div class='add'>+			i-cache-size = &lt;65536&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;65536&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_1&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu-map {</div><div class='add'>+			cluster0 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu2&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu3&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core4 {</div><div class='add'>+					cpu = &lt;&amp;cpu4&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core5 {</div><div class='add'>+					cpu = &lt;&amp;cpu5&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core6 {</div><div class='add'>+					cpu = &lt;&amp;cpu6&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core7 {</div><div class='add'>+					cpu = &lt;&amp;cpu7&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		idle-states {</div><div class='add'>+			entry-method = "psci";</div><div class='add'>+</div><div class='add'>+			cpu_ret_l: cpu-retention-l {</div><div class='add'>+				compatible = "arm,idle-state";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x00010001&gt;;</div><div class='add'>+				local-timer-stop;</div><div class='add'>+				entry-latency-us = &lt;50&gt;;</div><div class='add'>+				exit-latency-us = &lt;95&gt;;</div><div class='add'>+				min-residency-us = &lt;580&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cpu_ret_b: cpu-retention-b {</div><div class='add'>+				compatible = "arm,idle-state";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x00010001&gt;;</div><div class='add'>+				local-timer-stop;</div><div class='add'>+				entry-latency-us = &lt;45&gt;;</div><div class='add'>+				exit-latency-us = &lt;140&gt;;</div><div class='add'>+				min-residency-us = &lt;740&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cpu_off_l: cpu-off-l {</div><div class='add'>+				compatible = "arm,idle-state";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x01010002&gt;;</div><div class='add'>+				local-timer-stop;</div><div class='add'>+				entry-latency-us = &lt;55&gt;;</div><div class='add'>+				exit-latency-us = &lt;155&gt;;</div><div class='add'>+				min-residency-us = &lt;840&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cpu_off_b: cpu-off-b {</div><div class='add'>+				compatible = "arm,idle-state";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x01010002&gt;;</div><div class='add'>+				local-timer-stop;</div><div class='add'>+				entry-latency-us = &lt;50&gt;;</div><div class='add'>+				exit-latency-us = &lt;200&gt;;</div><div class='add'>+				min-residency-us = &lt;1000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_0: l2-cache0 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-size = &lt;131072&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;512&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l3_0&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_1: l2-cache1 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-size = &lt;262144&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;512&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l3_0&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l3_0: l3-cache {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;3&gt;;</div><div class='add'>+			cache-size = &lt;2097152&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;2048&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dsu-pmu {</div><div class='add'>+		compatible = "arm,dsu-pmu";</div><div class='add'>+		interrupts = &lt;GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+		cpus = &lt;&amp;cpu0&gt;, &lt;&amp;cpu1&gt;, &lt;&amp;cpu2&gt;, &lt;&amp;cpu3&gt;,</div><div class='add'>+		       &lt;&amp;cpu4&gt;, &lt;&amp;cpu5&gt;, &lt;&amp;cpu6&gt;, &lt;&amp;cpu7&gt;;</div><div class='add'>+		status = "fail";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dmic_codec: dmic-codec {</div><div class='add'>+		compatible = "dmic-codec";</div><div class='add'>+		num-channels = &lt;2&gt;;</div><div class='add'>+		wakeup-delay-ms = &lt;50&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound: mt8195-sound {</div><div class='add'>+		mediatek,platform = &lt;&amp;afe&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk13m: fixed-factor-clock-13m {</div><div class='add'>+		compatible = "fixed-factor-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clocks = &lt;&amp;clk26m&gt;;</div><div class='add'>+		clock-div = &lt;2&gt;;</div><div class='add'>+		clock-mult = &lt;1&gt;;</div><div class='add'>+		clock-output-names = "clk13m";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk26m: oscillator-26m {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;26000000&gt;;</div><div class='add'>+		clock-output-names = "clk26m";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk32k: oscillator-32k {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;32768&gt;;</div><div class='add'>+		clock-output-names = "clk32k";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	performance: performance-controller@11bc10 {</div><div class='add'>+		compatible = "mediatek,cpufreq-hw";</div><div class='add'>+		reg = &lt;0 0x0011bc10 0 0x120&gt;, &lt;0 0x0011bd30 0 0x120&gt;;</div><div class='add'>+		#performance-domain-cells = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpu_opp_table: opp-table-gpu {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+		opp-shared;</div><div class='add'>+</div><div class='add'>+		opp-390000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;390000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;625000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-410000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;410000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;631250&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-431000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;431000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;631250&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-473000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;473000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;637500&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-515000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;515000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;637500&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-556000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;556000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;643750&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-598000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;598000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;650000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-640000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;640000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;650000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-670000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;670000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;662500&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-700000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;700000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;675000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-730000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;730000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;687500&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-760000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;760000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;700000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-790000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;790000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;712500&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-820000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;820000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;725000&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-850000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;850000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;737500&gt;;</div><div class='add'>+		};</div><div class='add'>+		opp-880000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;880000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;750000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu-a55 {</div><div class='add'>+		compatible = "arm,cortex-a55-pmu";</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &amp;ppi_cluster0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu-a78 {</div><div class='add'>+		compatible = "arm,cortex-a78-pmu";</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &amp;ppi_cluster1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-1.0";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer: timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		ranges;</div><div class='add'>+		dma-ranges = &lt;0x0 0x0 0x0 0x0 0x4 0x0&gt;;</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@c000000 {</div><div class='add'>+			compatible = "arm,gic-v3";</div><div class='add'>+			#interrupt-cells = &lt;4&gt;;</div><div class='add'>+			#redistributor-regions = &lt;1&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			reg = &lt;0 0x0c000000 0 0x40000&gt;,</div><div class='add'>+			      &lt;0 0x0c040000 0 0x200000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+</div><div class='add'>+			ppi-partitions {</div><div class='add'>+				ppi_cluster0: interrupt-partition-0 {</div><div class='add'>+					affinity = &lt;&amp;cpu0 &amp;cpu1 &amp;cpu2 &amp;cpu3&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				ppi_cluster1: interrupt-partition-1 {</div><div class='add'>+					affinity = &lt;&amp;cpu4 &amp;cpu5 &amp;cpu6 &amp;cpu7&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		topckgen: syscon@10000000 {</div><div class='add'>+			compatible = "mediatek,mt8195-topckgen", "syscon";</div><div class='add'>+			reg = &lt;0 0x10000000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		infracfg_ao: syscon@10001000 {</div><div class='add'>+			compatible = "mediatek,mt8195-infracfg_ao", "syscon";</div><div class='add'>+			reg = &lt;0 0x10001000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pericfg: syscon@10003000 {</div><div class='add'>+			compatible = "mediatek,mt8195-pericfg", "syscon";</div><div class='add'>+			reg = &lt;0 0x10003000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pio: pinctrl@10005000 {</div><div class='add'>+			compatible = "mediatek,mt8195-pinctrl";</div><div class='add'>+			reg = &lt;0 0x10005000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11d10000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11d30000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11d40000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11e20000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11eb0000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11f40000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x1000b000 0 0x1000&gt;;</div><div class='add'>+			reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",</div><div class='add'>+				    "iocfg_br", "iocfg_lm", "iocfg_rb",</div><div class='add'>+				    "iocfg_tl", "eint";</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;pio 0 0 144&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			interrupts = &lt;GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		scpsys: syscon@10006000 {</div><div class='add'>+			compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd";</div><div class='add'>+			reg = &lt;0 0x10006000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			/* System Power Manager */</div><div class='add'>+			spm: power-controller {</div><div class='add'>+				compatible = "mediatek,mt8195-power-controller";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				/* power domain of the SoC */</div><div class='add'>+				mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 {</div><div class='add'>+					reg = &lt;MT8195_POWER_DOMAIN_MFG0&gt;;</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+					#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					mfg1: power-domain@MT8195_POWER_DOMAIN_MFG1 {</div><div class='add'>+						reg = &lt;MT8195_POWER_DOMAIN_MFG1&gt;;</div><div class='add'>+						clocks = &lt;&amp;apmixedsys CLK_APMIXED_MFGPLL&gt;,</div><div class='add'>+							 &lt;&amp;topckgen CLK_TOP_MFG_CORE_TMP&gt;;</div><div class='add'>+						clock-names = "mfg", "alt";</div><div class='add'>+						mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+						#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						power-domain@MT8195_POWER_DOMAIN_MFG2 {</div><div class='add'>+							reg = &lt;MT8195_POWER_DOMAIN_MFG2&gt;;</div><div class='add'>+							#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						power-domain@MT8195_POWER_DOMAIN_MFG3 {</div><div class='add'>+							reg = &lt;MT8195_POWER_DOMAIN_MFG3&gt;;</div><div class='add'>+							#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						power-domain@MT8195_POWER_DOMAIN_MFG4 {</div><div class='add'>+							reg = &lt;MT8195_POWER_DOMAIN_MFG4&gt;;</div><div class='add'>+							#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						power-domain@MT8195_POWER_DOMAIN_MFG5 {</div><div class='add'>+							reg = &lt;MT8195_POWER_DOMAIN_MFG5&gt;;</div><div class='add'>+							#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						power-domain@MT8195_POWER_DOMAIN_MFG6 {</div><div class='add'>+							reg = &lt;MT8195_POWER_DOMAIN_MFG6&gt;;</div><div class='add'>+							#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				power-domain@MT8195_POWER_DOMAIN_VPPSYS0 {</div><div class='add'>+					reg = &lt;MT8195_POWER_DOMAIN_VPPSYS0&gt;;</div><div class='add'>+					clocks = &lt;&amp;topckgen CLK_TOP_VPP&gt;,</div><div class='add'>+						 &lt;&amp;topckgen CLK_TOP_CAM&gt;,</div><div class='add'>+						 &lt;&amp;topckgen CLK_TOP_CCU&gt;,</div><div class='add'>+						 &lt;&amp;topckgen CLK_TOP_IMG&gt;,</div><div class='add'>+						 &lt;&amp;topckgen CLK_TOP_VENC&gt;,</div><div class='add'>+						 &lt;&amp;topckgen CLK_TOP_VDEC&gt;,</div><div class='add'>+						 &lt;&amp;topckgen CLK_TOP_WPE_VPP&gt;,</div><div class='add'>+						 &lt;&amp;topckgen CLK_TOP_CFG_VPP0&gt;,</div><div class='add'>+						 &lt;&amp;vppsys0 CLK_VPP0_SMI_COMMON&gt;,</div><div class='add'>+						 &lt;&amp;vppsys0 CLK_VPP0_GALS_VDO0_LARB0&gt;,</div><div class='add'>+						 &lt;&amp;vppsys0 CLK_VPP0_GALS_VDO0_LARB1&gt;,</div><div class='add'>+						 &lt;&amp;vppsys0 CLK_VPP0_GALS_VENCSYS&gt;,</div><div class='add'>+						 &lt;&amp;vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1&gt;,</div><div class='add'>+						 &lt;&amp;vppsys0 CLK_VPP0_GALS_INFRA&gt;,</div><div class='add'>+						 &lt;&amp;vppsys0 CLK_VPP0_GALS_CAMSYS&gt;,</div><div class='add'>+						 &lt;&amp;vppsys0 CLK_VPP0_GALS_VPP1_LARB5&gt;,</div><div class='add'>+						 &lt;&amp;vppsys0 CLK_VPP0_GALS_VPP1_LARB6&gt;,</div><div class='add'>+						 &lt;&amp;vppsys0 CLK_VPP0_SMI_REORDER&gt;,</div><div class='add'>+						 &lt;&amp;vppsys0 CLK_VPP0_SMI_IOMMU&gt;,</div><div class='add'>+						 &lt;&amp;vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS&gt;,</div><div class='add'>+						 &lt;&amp;vppsys0 CLK_VPP0_GALS_EMI0_EMI1&gt;,</div><div class='add'>+						 &lt;&amp;vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER&gt;,</div><div class='add'>+						 &lt;&amp;vppsys0 CLK_VPP0_SMI_RSI&gt;,</div><div class='add'>+						 &lt;&amp;vppsys0 CLK_VPP0_SMI_COMMON_LARB4&gt;,</div><div class='add'>+						 &lt;&amp;vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1&gt;,</div><div class='add'>+						 &lt;&amp;vppsys0 CLK_VPP0_GALS_VPP1_WPE&gt;,</div><div class='add'>+						 &lt;&amp;vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1&gt;;</div><div class='add'>+					clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3",</div><div class='add'>+						      "vppsys4", "vppsys5", "vppsys6", "vppsys7",</div><div class='add'>+						      "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3",</div><div class='add'>+						      "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7",</div><div class='add'>+						      "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11",</div><div class='add'>+						      "vppsys0-12", "vppsys0-13", "vppsys0-14",</div><div class='add'>+						      "vppsys0-15", "vppsys0-16", "vppsys0-17",</div><div class='add'>+						      "vppsys0-18";</div><div class='add'>+					mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+					#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					power-domain@MT8195_POWER_DOMAIN_VDOSYS0 {</div><div class='add'>+						reg = &lt;MT8195_POWER_DOMAIN_VDOSYS0&gt;;</div><div class='add'>+						clocks = &lt;&amp;topckgen CLK_TOP_CFG_VDO0&gt;,</div><div class='add'>+							 &lt;&amp;vdosys0 CLK_VDO0_SMI_GALS&gt;,</div><div class='add'>+							 &lt;&amp;vdosys0 CLK_VDO0_SMI_COMMON&gt;,</div><div class='add'>+							 &lt;&amp;vdosys0 CLK_VDO0_SMI_EMI&gt;,</div><div class='add'>+							 &lt;&amp;vdosys0 CLK_VDO0_SMI_IOMMU&gt;,</div><div class='add'>+							 &lt;&amp;vdosys0 CLK_VDO0_SMI_LARB&gt;,</div><div class='add'>+							 &lt;&amp;vdosys0 CLK_VDO0_SMI_RSI&gt;;</div><div class='add'>+						clock-names = "vdosys0", "vdosys0-0", "vdosys0-1",</div><div class='add'>+							      "vdosys0-2", "vdosys0-3",</div><div class='add'>+							      "vdosys0-4", "vdosys0-5";</div><div class='add'>+						mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+						#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						power-domain@MT8195_POWER_DOMAIN_VPPSYS1 {</div><div class='add'>+							reg = &lt;MT8195_POWER_DOMAIN_VPPSYS1&gt;;</div><div class='add'>+							clocks = &lt;&amp;topckgen CLK_TOP_CFG_VPP1&gt;,</div><div class='add'>+								 &lt;&amp;vppsys1 CLK_VPP1_VPPSYS1_GALS&gt;,</div><div class='add'>+								 &lt;&amp;vppsys1 CLK_VPP1_VPPSYS1_LARB&gt;;</div><div class='add'>+							clock-names = "vppsys1", "vppsys1-0",</div><div class='add'>+								      "vppsys1-1";</div><div class='add'>+							mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+							#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						power-domain@MT8195_POWER_DOMAIN_WPESYS {</div><div class='add'>+							reg = &lt;MT8195_POWER_DOMAIN_WPESYS&gt;;</div><div class='add'>+							clocks = &lt;&amp;wpesys CLK_WPE_SMI_LARB7&gt;,</div><div class='add'>+								 &lt;&amp;wpesys CLK_WPE_SMI_LARB8&gt;,</div><div class='add'>+								 &lt;&amp;wpesys CLK_WPE_SMI_LARB7_P&gt;,</div><div class='add'>+								 &lt;&amp;wpesys CLK_WPE_SMI_LARB8_P&gt;;</div><div class='add'>+							clock-names = "wepsys-0", "wepsys-1", "wepsys-2",</div><div class='add'>+								      "wepsys-3";</div><div class='add'>+							mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+							#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						power-domain@MT8195_POWER_DOMAIN_VDEC0 {</div><div class='add'>+							reg = &lt;MT8195_POWER_DOMAIN_VDEC0&gt;;</div><div class='add'>+							clocks = &lt;&amp;vdecsys_soc CLK_VDEC_SOC_LARB1&gt;;</div><div class='add'>+							clock-names = "vdec0-0";</div><div class='add'>+							mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+							#address-cells = &lt;1&gt;;</div><div class='add'>+							#size-cells = &lt;0&gt;;</div><div class='add'>+							#power-domain-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							power-domain@MT8195_POWER_DOMAIN_VDEC1 {</div><div class='add'>+								reg = &lt;MT8195_POWER_DOMAIN_VDEC1&gt;;</div><div class='add'>+								clocks = &lt;&amp;vdecsys CLK_VDEC_LARB1&gt;;</div><div class='add'>+								clock-names = "vdec1-0";</div><div class='add'>+								mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+								#power-domain-cells = &lt;0&gt;;</div><div class='add'>+							};</div><div class='add'>+</div><div class='add'>+							power-domain@MT8195_POWER_DOMAIN_VDEC2 {</div><div class='add'>+								reg = &lt;MT8195_POWER_DOMAIN_VDEC2&gt;;</div><div class='add'>+								clocks = &lt;&amp;vdecsys_core1 CLK_VDEC_CORE1_LARB1&gt;;</div><div class='add'>+								clock-names = "vdec2-0";</div><div class='add'>+								mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+								#power-domain-cells = &lt;0&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						power-domain@MT8195_POWER_DOMAIN_VENC {</div><div class='add'>+							reg = &lt;MT8195_POWER_DOMAIN_VENC&gt;;</div><div class='add'>+							clocks = &lt;&amp;vencsys CLK_VENC_LARB&gt;;</div><div class='add'>+							clock-names = "venc0-larb";</div><div class='add'>+							mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+							#address-cells = &lt;1&gt;;</div><div class='add'>+							#size-cells = &lt;0&gt;;</div><div class='add'>+							#power-domain-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 {</div><div class='add'>+								reg = &lt;MT8195_POWER_DOMAIN_VENC_CORE1&gt;;</div><div class='add'>+								clocks = &lt;&amp;vencsys_core1 CLK_VENC_CORE1_LARB&gt;;</div><div class='add'>+								clock-names = "venc1-larb";</div><div class='add'>+								mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+								#power-domain-cells = &lt;0&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						power-domain@MT8195_POWER_DOMAIN_VDOSYS1 {</div><div class='add'>+							reg = &lt;MT8195_POWER_DOMAIN_VDOSYS1&gt;;</div><div class='add'>+							clocks = &lt;&amp;topckgen CLK_TOP_CFG_VDO1&gt;,</div><div class='add'>+								 &lt;&amp;vdosys1 CLK_VDO1_SMI_LARB2&gt;,</div><div class='add'>+								 &lt;&amp;vdosys1 CLK_VDO1_SMI_LARB3&gt;,</div><div class='add'>+								 &lt;&amp;vdosys1 CLK_VDO1_GALS&gt;;</div><div class='add'>+							clock-names = "vdosys1", "vdosys1-0",</div><div class='add'>+								      "vdosys1-1", "vdosys1-2";</div><div class='add'>+							mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+							#address-cells = &lt;1&gt;;</div><div class='add'>+							#size-cells = &lt;0&gt;;</div><div class='add'>+							#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							power-domain@MT8195_POWER_DOMAIN_DP_TX {</div><div class='add'>+								reg = &lt;MT8195_POWER_DOMAIN_DP_TX&gt;;</div><div class='add'>+								mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+								#power-domain-cells = &lt;0&gt;;</div><div class='add'>+							};</div><div class='add'>+</div><div class='add'>+							power-domain@MT8195_POWER_DOMAIN_EPD_TX {</div><div class='add'>+								reg = &lt;MT8195_POWER_DOMAIN_EPD_TX&gt;;</div><div class='add'>+								mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+								#power-domain-cells = &lt;0&gt;;</div><div class='add'>+							};</div><div class='add'>+</div><div class='add'>+							power-domain@MT8195_POWER_DOMAIN_HDMI_TX {</div><div class='add'>+								reg = &lt;MT8195_POWER_DOMAIN_HDMI_TX&gt;;</div><div class='add'>+								clocks = &lt;&amp;topckgen CLK_TOP_HDMI_APB&gt;;</div><div class='add'>+								clock-names = "hdmi_tx";</div><div class='add'>+								#power-domain-cells = &lt;0&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						power-domain@MT8195_POWER_DOMAIN_IMG {</div><div class='add'>+							reg = &lt;MT8195_POWER_DOMAIN_IMG&gt;;</div><div class='add'>+							clocks = &lt;&amp;imgsys CLK_IMG_LARB9&gt;,</div><div class='add'>+								 &lt;&amp;imgsys CLK_IMG_GALS&gt;;</div><div class='add'>+							clock-names = "img-0", "img-1";</div><div class='add'>+							mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+							#address-cells = &lt;1&gt;;</div><div class='add'>+							#size-cells = &lt;0&gt;;</div><div class='add'>+							#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							power-domain@MT8195_POWER_DOMAIN_DIP {</div><div class='add'>+								reg = &lt;MT8195_POWER_DOMAIN_DIP&gt;;</div><div class='add'>+								#power-domain-cells = &lt;0&gt;;</div><div class='add'>+							};</div><div class='add'>+</div><div class='add'>+							power-domain@MT8195_POWER_DOMAIN_IPE {</div><div class='add'>+								reg = &lt;MT8195_POWER_DOMAIN_IPE&gt;;</div><div class='add'>+								clocks = &lt;&amp;topckgen CLK_TOP_IPE&gt;,</div><div class='add'>+									 &lt;&amp;imgsys CLK_IMG_IPE&gt;,</div><div class='add'>+									 &lt;&amp;ipesys CLK_IPE_SMI_LARB12&gt;;</div><div class='add'>+								clock-names = "ipe", "ipe-0", "ipe-1";</div><div class='add'>+								mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+								#power-domain-cells = &lt;0&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						power-domain@MT8195_POWER_DOMAIN_CAM {</div><div class='add'>+							reg = &lt;MT8195_POWER_DOMAIN_CAM&gt;;</div><div class='add'>+							clocks = &lt;&amp;camsys CLK_CAM_LARB13&gt;,</div><div class='add'>+								 &lt;&amp;camsys CLK_CAM_LARB14&gt;,</div><div class='add'>+								 &lt;&amp;camsys CLK_CAM_CAM2MM0_GALS&gt;,</div><div class='add'>+								 &lt;&amp;camsys CLK_CAM_CAM2MM1_GALS&gt;,</div><div class='add'>+								 &lt;&amp;camsys CLK_CAM_CAM2SYS_GALS&gt;;</div><div class='add'>+							clock-names = "cam-0", "cam-1", "cam-2", "cam-3",</div><div class='add'>+								      "cam-4";</div><div class='add'>+							mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+							#address-cells = &lt;1&gt;;</div><div class='add'>+							#size-cells = &lt;0&gt;;</div><div class='add'>+							#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							power-domain@MT8195_POWER_DOMAIN_CAM_RAWA {</div><div class='add'>+								reg = &lt;MT8195_POWER_DOMAIN_CAM_RAWA&gt;;</div><div class='add'>+								#power-domain-cells = &lt;0&gt;;</div><div class='add'>+							};</div><div class='add'>+</div><div class='add'>+							power-domain@MT8195_POWER_DOMAIN_CAM_RAWB {</div><div class='add'>+								reg = &lt;MT8195_POWER_DOMAIN_CAM_RAWB&gt;;</div><div class='add'>+								#power-domain-cells = &lt;0&gt;;</div><div class='add'>+							};</div><div class='add'>+</div><div class='add'>+							power-domain@MT8195_POWER_DOMAIN_CAM_MRAW {</div><div class='add'>+								reg = &lt;MT8195_POWER_DOMAIN_CAM_MRAW&gt;;</div><div class='add'>+								#power-domain-cells = &lt;0&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 {</div><div class='add'>+					reg = &lt;MT8195_POWER_DOMAIN_PCIE_MAC_P0&gt;;</div><div class='add'>+					mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+					#power-domain-cells = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 {</div><div class='add'>+					reg = &lt;MT8195_POWER_DOMAIN_PCIE_MAC_P1&gt;;</div><div class='add'>+					mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+					#power-domain-cells = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				power-domain@MT8195_POWER_DOMAIN_PCIE_PHY {</div><div class='add'>+					reg = &lt;MT8195_POWER_DOMAIN_PCIE_PHY&gt;;</div><div class='add'>+					#power-domain-cells = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY {</div><div class='add'>+					reg = &lt;MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY&gt;;</div><div class='add'>+					#power-domain-cells = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP {</div><div class='add'>+					reg = &lt;MT8195_POWER_DOMAIN_CSI_RX_TOP&gt;;</div><div class='add'>+					clocks = &lt;&amp;topckgen CLK_TOP_SENINF&gt;,</div><div class='add'>+						 &lt;&amp;topckgen CLK_TOP_SENINF2&gt;;</div><div class='add'>+					clock-names = "csi_rx_top", "csi_rx_top1";</div><div class='add'>+					#power-domain-cells = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				power-domain@MT8195_POWER_DOMAIN_ETHER {</div><div class='add'>+					reg = &lt;MT8195_POWER_DOMAIN_ETHER&gt;;</div><div class='add'>+					clocks = &lt;&amp;pericfg_ao CLK_PERI_AO_ETHERNET_MAC&gt;;</div><div class='add'>+					clock-names = "ether";</div><div class='add'>+					#power-domain-cells = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				power-domain@MT8195_POWER_DOMAIN_ADSP {</div><div class='add'>+					reg = &lt;MT8195_POWER_DOMAIN_ADSP&gt;;</div><div class='add'>+					clocks = &lt;&amp;topckgen CLK_TOP_ADSP&gt;,</div><div class='add'>+						 &lt;&amp;topckgen CLK_TOP_AUDIO_LOCAL_BUS&gt;;</div><div class='add'>+					clock-names = "adsp", "adsp1";</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+					mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+					#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					power-domain@MT8195_POWER_DOMAIN_AUDIO {</div><div class='add'>+						reg = &lt;MT8195_POWER_DOMAIN_AUDIO&gt;;</div><div class='add'>+						clocks = &lt;&amp;topckgen CLK_TOP_A1SYS_HP&gt;,</div><div class='add'>+							 &lt;&amp;topckgen CLK_TOP_AUD_INTBUS&gt;,</div><div class='add'>+							 &lt;&amp;topckgen CLK_TOP_AUDIO_LOCAL_BUS&gt;,</div><div class='add'>+							 &lt;&amp;infracfg_ao CLK_INFRA_AO_AUDIO_26M_B&gt;;</div><div class='add'>+						clock-names = "audio", "audio1", "audio2",</div><div class='add'>+							      "audio3";</div><div class='add'>+						mediatek,infracfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		watchdog: watchdog@10007000 {</div><div class='add'>+			compatible = "mediatek,mt8195-wdt";</div><div class='add'>+			mediatek,disable-extrst;</div><div class='add'>+			reg = &lt;0 0x10007000 0 0x100&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		apmixedsys: syscon@1000c000 {</div><div class='add'>+			compatible = "mediatek,mt8195-apmixedsys", "syscon";</div><div class='add'>+			reg = &lt;0 0x1000c000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		systimer: timer@10017000 {</div><div class='add'>+			compatible = "mediatek,mt8195-timer",</div><div class='add'>+				     "mediatek,mt6765-timer";</div><div class='add'>+			reg = &lt;0 0x10017000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk13m&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pwrap: pwrap@10024000 {</div><div class='add'>+			compatible = "mediatek,mt8195-pwrap", "syscon";</div><div class='add'>+			reg = &lt;0 0x10024000 0 0x1000&gt;;</div><div class='add'>+			reg-names = "pwrap";</div><div class='add'>+			interrupts = &lt;GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg_ao CLK_INFRA_AO_PMIC_AP&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_PMIC_TMR&gt;;</div><div class='add'>+			clock-names = "spi", "wrap";</div><div class='add'>+			assigned-clocks = &lt;&amp;topckgen CLK_TOP_PWRAP_ULPOSC&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_ULPOSC1_D10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spmi: spmi@10027000 {</div><div class='add'>+			compatible = "mediatek,mt8195-spmi";</div><div class='add'>+			reg = &lt;0 0x10027000 0 0x000e00&gt;,</div><div class='add'>+			      &lt;0 0x10029000 0 0x000100&gt;;</div><div class='add'>+			reg-names = "pmif", "spmimst";</div><div class='add'>+			clocks = &lt;&amp;infracfg_ao CLK_INFRA_AO_PMIC_AP&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_PMIC_TMR&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SPMI_M_MST&gt;;</div><div class='add'>+			clock-names = "pmif_sys_ck",</div><div class='add'>+				      "pmif_tmr_ck",</div><div class='add'>+				      "spmimst_clk_mux";</div><div class='add'>+			assigned-clocks = &lt;&amp;topckgen CLK_TOP_PWRAP_ULPOSC&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_ULPOSC1_D10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		iommu_infra: infra-iommu@10315000 {</div><div class='add'>+			compatible = "mediatek,mt8195-iommu-infra";</div><div class='add'>+			reg = &lt;0 0x10315000 0 0x5000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+				     &lt;GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+				     &lt;GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+				     &lt;GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+				     &lt;GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			#iommu-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gce0: mailbox@10320000 {</div><div class='add'>+			compatible = "mediatek,mt8195-gce";</div><div class='add'>+			reg = &lt;0 0x10320000 0 0x4000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			#mbox-cells = &lt;2&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg_ao CLK_INFRA_AO_GCE&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gce1: mailbox@10330000 {</div><div class='add'>+			compatible = "mediatek,mt8195-gce";</div><div class='add'>+			reg = &lt;0 0x10330000 0 0x4000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			#mbox-cells = &lt;2&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg_ao CLK_INFRA_AO_GCE2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		scp: scp@10500000 {</div><div class='add'>+			compatible = "mediatek,mt8195-scp";</div><div class='add'>+			reg = &lt;0 0x10500000 0 0x100000&gt;,</div><div class='add'>+			      &lt;0 0x10720000 0 0xe0000&gt;,</div><div class='add'>+			      &lt;0 0x10700000 0 0x8000&gt;;</div><div class='add'>+			reg-names = "sram", "cfg", "l1tcm";</div><div class='add'>+			interrupts = &lt;GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		scp_adsp: clock-controller@10720000 {</div><div class='add'>+			compatible = "mediatek,mt8195-scp_adsp";</div><div class='add'>+			reg = &lt;0 0x10720000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		adsp: dsp@10803000 {</div><div class='add'>+			compatible = "mediatek,mt8195-dsp";</div><div class='add'>+			reg = &lt;0 0x10803000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x10840000 0 0x40000&gt;;</div><div class='add'>+			reg-names = "cfg", "sram";</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_ADSP&gt;,</div><div class='add'>+				 &lt;&amp;clk26m&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_AUDIO_LOCAL_BUS&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_MAINPLL_D7_D2&gt;,</div><div class='add'>+				 &lt;&amp;scp_adsp CLK_SCP_ADSP_AUDIODSP&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_AUDIO_H&gt;;</div><div class='add'>+			clock-names = "adsp_sel",</div><div class='add'>+				 "clk26m_ck",</div><div class='add'>+				 "audio_local_bus",</div><div class='add'>+				 "mainpll_d7_d2",</div><div class='add'>+				 "scp_adsp_audiodsp",</div><div class='add'>+				 "audio_h";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_ADSP&gt;;</div><div class='add'>+			mbox-names = "rx", "tx";</div><div class='add'>+			mboxes = &lt;&amp;adsp_mailbox0&gt;, &lt;&amp;adsp_mailbox1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		adsp_mailbox0: mailbox@10816000 {</div><div class='add'>+			compatible = "mediatek,mt8195-adsp-mbox";</div><div class='add'>+			#mbox-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0 0x10816000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		adsp_mailbox1: mailbox@10817000 {</div><div class='add'>+			compatible = "mediatek,mt8195-adsp-mbox";</div><div class='add'>+			#mbox-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0 0x10817000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		afe: mt8195-afe-pcm@10890000 {</div><div class='add'>+			compatible = "mediatek,mt8195-audio";</div><div class='add'>+			reg = &lt;0 0x10890000 0 0x10000&gt;;</div><div class='add'>+			mediatek,topckgen = &lt;&amp;topckgen&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_AUDIO&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			resets = &lt;&amp;watchdog 14&gt;;</div><div class='add'>+			reset-names = "audiosys";</div><div class='add'>+			clocks = &lt;&amp;clk26m&gt;,</div><div class='add'>+				&lt;&amp;apmixedsys CLK_APMIXED_APLL1&gt;,</div><div class='add'>+				&lt;&amp;apmixedsys CLK_APMIXED_APLL2&gt;,</div><div class='add'>+				&lt;&amp;topckgen CLK_TOP_APLL12_DIV0&gt;,</div><div class='add'>+				&lt;&amp;topckgen CLK_TOP_APLL12_DIV1&gt;,</div><div class='add'>+				&lt;&amp;topckgen CLK_TOP_APLL12_DIV2&gt;,</div><div class='add'>+				&lt;&amp;topckgen CLK_TOP_APLL12_DIV3&gt;,</div><div class='add'>+				&lt;&amp;topckgen CLK_TOP_APLL12_DIV9&gt;,</div><div class='add'>+				&lt;&amp;topckgen CLK_TOP_A1SYS_HP&gt;,</div><div class='add'>+				&lt;&amp;topckgen CLK_TOP_AUD_INTBUS&gt;,</div><div class='add'>+				&lt;&amp;topckgen CLK_TOP_AUDIO_H&gt;,</div><div class='add'>+				&lt;&amp;topckgen CLK_TOP_AUDIO_LOCAL_BUS&gt;,</div><div class='add'>+				&lt;&amp;topckgen CLK_TOP_DPTX_MCK&gt;,</div><div class='add'>+				&lt;&amp;topckgen CLK_TOP_I2SO1_MCK&gt;,</div><div class='add'>+				&lt;&amp;topckgen CLK_TOP_I2SO2_MCK&gt;,</div><div class='add'>+				&lt;&amp;topckgen CLK_TOP_I2SI1_MCK&gt;,</div><div class='add'>+				&lt;&amp;topckgen CLK_TOP_I2SI2_MCK&gt;,</div><div class='add'>+				&lt;&amp;infracfg_ao CLK_INFRA_AO_AUDIO_26M_B&gt;,</div><div class='add'>+				&lt;&amp;scp_adsp CLK_SCP_ADSP_AUDIODSP&gt;;</div><div class='add'>+			clock-names = "clk26m",</div><div class='add'>+				"apll1_ck",</div><div class='add'>+				"apll2_ck",</div><div class='add'>+				"apll12_div0",</div><div class='add'>+				"apll12_div1",</div><div class='add'>+				"apll12_div2",</div><div class='add'>+				"apll12_div3",</div><div class='add'>+				"apll12_div9",</div><div class='add'>+				"a1sys_hp_sel",</div><div class='add'>+				"aud_intbus_sel",</div><div class='add'>+				"audio_h_sel",</div><div class='add'>+				"audio_local_bus_sel",</div><div class='add'>+				"dptx_m_sel",</div><div class='add'>+				"i2so1_m_sel",</div><div class='add'>+				"i2so2_m_sel",</div><div class='add'>+				"i2si1_m_sel",</div><div class='add'>+				"i2si2_m_sel",</div><div class='add'>+				"infra_ao_audio_26m_b",</div><div class='add'>+				"scp_adsp_audiodsp";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart0: serial@11001100 {</div><div class='add'>+			compatible = "mediatek,mt8195-uart",</div><div class='add'>+				     "mediatek,mt6577-uart";</div><div class='add'>+			reg = &lt;0 0x11001100 0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk26m&gt;, &lt;&amp;infracfg_ao CLK_INFRA_AO_UART0&gt;;</div><div class='add'>+			clock-names = "baud", "bus";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart1: serial@11001200 {</div><div class='add'>+			compatible = "mediatek,mt8195-uart",</div><div class='add'>+				     "mediatek,mt6577-uart";</div><div class='add'>+			reg = &lt;0 0x11001200 0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk26m&gt;, &lt;&amp;infracfg_ao CLK_INFRA_AO_UART1&gt;;</div><div class='add'>+			clock-names = "baud", "bus";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart2: serial@11001300 {</div><div class='add'>+			compatible = "mediatek,mt8195-uart",</div><div class='add'>+				     "mediatek,mt6577-uart";</div><div class='add'>+			reg = &lt;0 0x11001300 0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk26m&gt;, &lt;&amp;infracfg_ao CLK_INFRA_AO_UART2&gt;;</div><div class='add'>+			clock-names = "baud", "bus";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart3: serial@11001400 {</div><div class='add'>+			compatible = "mediatek,mt8195-uart",</div><div class='add'>+				     "mediatek,mt6577-uart";</div><div class='add'>+			reg = &lt;0 0x11001400 0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk26m&gt;, &lt;&amp;infracfg_ao CLK_INFRA_AO_UART3&gt;;</div><div class='add'>+			clock-names = "baud", "bus";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart4: serial@11001500 {</div><div class='add'>+			compatible = "mediatek,mt8195-uart",</div><div class='add'>+				     "mediatek,mt6577-uart";</div><div class='add'>+			reg = &lt;0 0x11001500 0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk26m&gt;, &lt;&amp;infracfg_ao CLK_INFRA_AO_UART4&gt;;</div><div class='add'>+			clock-names = "baud", "bus";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart5: serial@11001600 {</div><div class='add'>+			compatible = "mediatek,mt8195-uart",</div><div class='add'>+				     "mediatek,mt6577-uart";</div><div class='add'>+			reg = &lt;0 0x11001600 0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk26m&gt;, &lt;&amp;infracfg_ao CLK_INFRA_AO_UART5&gt;;</div><div class='add'>+			clock-names = "baud", "bus";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		auxadc: auxadc@11002000 {</div><div class='add'>+			compatible = "mediatek,mt8195-auxadc",</div><div class='add'>+				     "mediatek,mt8173-auxadc";</div><div class='add'>+			reg = &lt;0 0x11002000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg_ao CLK_INFRA_AO_AUXADC&gt;;</div><div class='add'>+			clock-names = "main";</div><div class='add'>+			#io-channel-cells = &lt;1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pericfg_ao: syscon@11003000 {</div><div class='add'>+			compatible = "mediatek,mt8195-pericfg_ao", "syscon";</div><div class='add'>+			reg = &lt;0 0x11003000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi0: spi@1100a000 {</div><div class='add'>+			compatible = "mediatek,mt8195-spi",</div><div class='add'>+				     "mediatek,mt6765-spi";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0 0x1100a000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_UNIVPLL_D6_D2&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SPI&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_SPI0&gt;;</div><div class='add'>+			clock-names = "parent-clk", "sel-clk", "spi-clk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		lvts_ap: thermal-sensor@1100b000 {</div><div class='add'>+			compatible = "mediatek,mt8195-lvts-ap";</div><div class='add'>+			reg = &lt;0 0x1100b000 0 0xc00&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg_ao CLK_INFRA_AO_THERM&gt;;</div><div class='add'>+			resets = &lt;&amp;infracfg_ao MT8195_INFRA_RST0_THERM_CTRL_SWRST&gt;;</div><div class='add'>+			nvmem-cells = &lt;&amp;lvts_efuse_data1 &amp;lvts_efuse_data2&gt;;</div><div class='add'>+			nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";</div><div class='add'>+			#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		svs: svs@1100bc00 {</div><div class='add'>+			compatible = "mediatek,mt8195-svs";</div><div class='add'>+			reg = &lt;0 0x1100bc00 0 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg_ao CLK_INFRA_AO_THERM&gt;;</div><div class='add'>+			clock-names = "main";</div><div class='add'>+			nvmem-cells = &lt;&amp;svs_calib_data &amp;lvts_efuse_data1&gt;;</div><div class='add'>+			nvmem-cell-names = "svs-calibration-data", "t-calibration-data";</div><div class='add'>+			resets = &lt;&amp;infracfg_ao MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST&gt;;</div><div class='add'>+			reset-names = "svs_rst";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		disp_pwm0: pwm@1100e000 {</div><div class='add'>+			compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm";</div><div class='add'>+			reg = &lt;0 0x1100e000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 203 IRQ_TYPE_LEVEL_LOW 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VDOSYS0&gt;;</div><div class='add'>+			#pwm-cells = &lt;2&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_DISP_PWM0&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_DISP_PWM&gt;;</div><div class='add'>+			clock-names = "main", "mm";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		disp_pwm1: pwm@1100f000 {</div><div class='add'>+			compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm";</div><div class='add'>+			reg = &lt;0 0x1100f000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			#pwm-cells = &lt;2&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_DISP_PWM1&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_DISP_PWM1&gt;;</div><div class='add'>+			clock-names = "main", "mm";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi1: spi@11010000 {</div><div class='add'>+			compatible = "mediatek,mt8195-spi",</div><div class='add'>+				     "mediatek,mt6765-spi";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0 0x11010000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_UNIVPLL_D6_D2&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SPI&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_SPI1&gt;;</div><div class='add'>+			clock-names = "parent-clk", "sel-clk", "spi-clk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi2: spi@11012000 {</div><div class='add'>+			compatible = "mediatek,mt8195-spi",</div><div class='add'>+				     "mediatek,mt6765-spi";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0 0x11012000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_UNIVPLL_D6_D2&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SPI&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_SPI2&gt;;</div><div class='add'>+			clock-names = "parent-clk", "sel-clk", "spi-clk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi3: spi@11013000 {</div><div class='add'>+			compatible = "mediatek,mt8195-spi",</div><div class='add'>+				     "mediatek,mt6765-spi";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0 0x11013000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_UNIVPLL_D6_D2&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SPI&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_SPI3&gt;;</div><div class='add'>+			clock-names = "parent-clk", "sel-clk", "spi-clk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi4: spi@11018000 {</div><div class='add'>+			compatible = "mediatek,mt8195-spi",</div><div class='add'>+				     "mediatek,mt6765-spi";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0 0x11018000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_UNIVPLL_D6_D2&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SPI&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_SPI4&gt;;</div><div class='add'>+			clock-names = "parent-clk", "sel-clk", "spi-clk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi5: spi@11019000 {</div><div class='add'>+			compatible = "mediatek,mt8195-spi",</div><div class='add'>+				     "mediatek,mt6765-spi";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0 0x11019000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_UNIVPLL_D6_D2&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SPI&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_SPI5&gt;;</div><div class='add'>+			clock-names = "parent-clk", "sel-clk", "spi-clk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spis0: spi@1101d000 {</div><div class='add'>+			compatible = "mediatek,mt8195-spi-slave";</div><div class='add'>+			reg = &lt;0 0x1101d000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg_ao CLK_INFRA_AO_SPIS0&gt;;</div><div class='add'>+			clock-names = "spi";</div><div class='add'>+			assigned-clocks = &lt;&amp;topckgen CLK_TOP_SPIS&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_UNIVPLL_D6&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spis1: spi@1101e000 {</div><div class='add'>+			compatible = "mediatek,mt8195-spi-slave";</div><div class='add'>+			reg = &lt;0 0x1101e000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg_ao CLK_INFRA_AO_SPIS1&gt;;</div><div class='add'>+			clock-names = "spi";</div><div class='add'>+			assigned-clocks = &lt;&amp;topckgen CLK_TOP_SPIS&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_UNIVPLL_D6&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		eth: ethernet@11021000 {</div><div class='add'>+			compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a";</div><div class='add'>+			reg = &lt;0 0x11021000 0 0x4000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			interrupt-names = "macirq";</div><div class='add'>+			clock-names = "axi",</div><div class='add'>+				      "apb",</div><div class='add'>+				      "mac_main",</div><div class='add'>+				      "ptp_ref",</div><div class='add'>+				      "rmii_internal",</div><div class='add'>+				      "mac_cg";</div><div class='add'>+			clocks = &lt;&amp;pericfg_ao CLK_PERI_AO_ETHERNET&gt;,</div><div class='add'>+				 &lt;&amp;pericfg_ao CLK_PERI_AO_ETHERNET_BUS&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SNPS_ETH_250M&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SNPS_ETH_62P4M_PTP&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SNPS_ETH_50M_RMII&gt;,</div><div class='add'>+				 &lt;&amp;pericfg_ao CLK_PERI_AO_ETHERNET_MAC&gt;;</div><div class='add'>+			assigned-clocks = &lt;&amp;topckgen CLK_TOP_SNPS_ETH_250M&gt;,</div><div class='add'>+					  &lt;&amp;topckgen CLK_TOP_SNPS_ETH_62P4M_PTP&gt;,</div><div class='add'>+					  &lt;&amp;topckgen CLK_TOP_SNPS_ETH_50M_RMII&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_ETHPLL_D2&gt;,</div><div class='add'>+						 &lt;&amp;topckgen CLK_TOP_ETHPLL_D8&gt;,</div><div class='add'>+						 &lt;&amp;topckgen CLK_TOP_ETHPLL_D10&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_ETHER&gt;;</div><div class='add'>+			mediatek,pericfg = &lt;&amp;infracfg_ao&gt;;</div><div class='add'>+			snps,axi-config = &lt;&amp;stmmac_axi_setup&gt;;</div><div class='add'>+			snps,mtl-rx-config = &lt;&amp;mtl_rx_setup&gt;;</div><div class='add'>+			snps,mtl-tx-config = &lt;&amp;mtl_tx_setup&gt;;</div><div class='add'>+			snps,txpbl = &lt;16&gt;;</div><div class='add'>+			snps,rxpbl = &lt;16&gt;;</div><div class='add'>+			snps,clk-csr = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			mdio {</div><div class='add'>+				compatible = "snps,dwmac-mdio";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			stmmac_axi_setup: stmmac-axi-config {</div><div class='add'>+				snps,wr_osr_lmt = &lt;0x7&gt;;</div><div class='add'>+				snps,rd_osr_lmt = &lt;0x7&gt;;</div><div class='add'>+				snps,blen = &lt;0 0 0 0 16 8 4&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mtl_rx_setup: rx-queues-config {</div><div class='add'>+				snps,rx-queues-to-use = &lt;4&gt;;</div><div class='add'>+				snps,rx-sched-sp;</div><div class='add'>+				queue0 {</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+					snps,map-to-dma-channel = &lt;0x0&gt;;</div><div class='add'>+				};</div><div class='add'>+				queue1 {</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+					snps,map-to-dma-channel = &lt;0x0&gt;;</div><div class='add'>+				};</div><div class='add'>+				queue2 {</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+					snps,map-to-dma-channel = &lt;0x0&gt;;</div><div class='add'>+				};</div><div class='add'>+				queue3 {</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+					snps,map-to-dma-channel = &lt;0x0&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mtl_tx_setup: tx-queues-config {</div><div class='add'>+				snps,tx-queues-to-use = &lt;4&gt;;</div><div class='add'>+				snps,tx-sched-wrr;</div><div class='add'>+				queue0 {</div><div class='add'>+					snps,weight = &lt;0x10&gt;;</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+					snps,priority = &lt;0x0&gt;;</div><div class='add'>+				};</div><div class='add'>+				queue1 {</div><div class='add'>+					snps,weight = &lt;0x11&gt;;</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+					snps,priority = &lt;0x1&gt;;</div><div class='add'>+				};</div><div class='add'>+				queue2 {</div><div class='add'>+					snps,weight = &lt;0x12&gt;;</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+					snps,priority = &lt;0x2&gt;;</div><div class='add'>+				};</div><div class='add'>+				queue3 {</div><div class='add'>+					snps,weight = &lt;0x13&gt;;</div><div class='add'>+					snps,dcb-algorithm;</div><div class='add'>+					snps,priority = &lt;0x3&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ssusb0: usb@11201000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mtu3", "mediatek,mtu3";</div><div class='add'>+			reg = &lt;0 0x11201000 0 0x2dff&gt;, &lt;0 0x11203e00 0 0x0100&gt;;</div><div class='add'>+			reg-names = "mac", "ippc";</div><div class='add'>+			ranges = &lt;0 0 0 0x11200000 0 0x3f00&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg_ao CLK_INFRA_AO_SSUSB&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SSUSB_REF&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_SSUSB_XHCI&gt;;</div><div class='add'>+			clock-names = "sys_ck", "ref_ck", "mcu_ck";</div><div class='add'>+			phys = &lt;&amp;u2port0 PHY_TYPE_USB2&gt;, &lt;&amp;u3port0 PHY_TYPE_USB3&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+			mediatek,syscon-wakeup = &lt;&amp;pericfg 0x400 103&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			xhci0: usb@0 {</div><div class='add'>+				compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci";</div><div class='add'>+				reg = &lt;0 0 0 0x1000&gt;;</div><div class='add'>+				reg-names = "mac";</div><div class='add'>+				interrupts = &lt;GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				assigned-clocks = &lt;&amp;topckgen CLK_TOP_USB_TOP&gt;,</div><div class='add'>+						  &lt;&amp;topckgen CLK_TOP_SSUSB_XHCI&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_UNIVPLL_D5_D4&gt;,</div><div class='add'>+							 &lt;&amp;topckgen CLK_TOP_UNIVPLL_D5_D4&gt;;</div><div class='add'>+				clocks = &lt;&amp;infracfg_ao CLK_INFRA_AO_SSUSB&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_SSUSB_REF&gt;,</div><div class='add'>+					 &lt;&amp;apmixedsys CLK_APMIXED_USB1PLL&gt;,</div><div class='add'>+					 &lt;&amp;clk26m&gt;,</div><div class='add'>+					 &lt;&amp;infracfg_ao CLK_INFRA_AO_SSUSB_XHCI&gt;;</div><div class='add'>+				clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmc0: mmc@11230000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mmc",</div><div class='add'>+				     "mediatek,mt8183-mmc";</div><div class='add'>+			reg = &lt;0 0x11230000 0 0x10000&gt;,</div><div class='add'>+			      &lt;0 0x11f50000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_MSDC50_0&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_MSDC0&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_MSDC0_SRC&gt;;</div><div class='add'>+			clock-names = "source", "hclk", "source_cg";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmc1: mmc@11240000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mmc",</div><div class='add'>+				     "mediatek,mt8183-mmc";</div><div class='add'>+			reg = &lt;0 0x11240000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11c70000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_MSDC30_1&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_MSDC1&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_MSDC1_SRC&gt;;</div><div class='add'>+			clock-names = "source", "hclk", "source_cg";</div><div class='add'>+			assigned-clocks = &lt;&amp;topckgen CLK_TOP_MSDC30_1&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_MSDCPLL_D2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmc2: mmc@11250000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mmc",</div><div class='add'>+				     "mediatek,mt8183-mmc";</div><div class='add'>+			reg = &lt;0 0x11250000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11e60000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_MSDC30_2&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_CG1_MSDC2&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_CG3_MSDC2&gt;;</div><div class='add'>+			clock-names = "source", "hclk", "source_cg";</div><div class='add'>+			assigned-clocks = &lt;&amp;topckgen CLK_TOP_MSDC30_2&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_MSDCPLL_D2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ufshci: ufshci@11270000 {</div><div class='add'>+			compatible = "mediatek,mt8195-ufshci";</div><div class='add'>+			reg = &lt;0 0x11270000 0 0x2300&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			phys = &lt;&amp;ufsphy&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg_ao CLK_INFRA_AO_AES_UFSFDE&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_AES&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_UFS_TICK&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_UNIPRO_SYS&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_UNIPRO_TICK&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_UFS_MP_SAP_B&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_UFS_TX_SYMBOL&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_PERI_UFS_MEM_SUB&gt;;</div><div class='add'>+			clock-names = "ufs", "ufs_aes", "ufs_tick",</div><div class='add'>+					"unipro_sysclk", "unipro_tick",</div><div class='add'>+					"unipro_mp_bclk", "ufs_tx_symbol",</div><div class='add'>+					"ufs_mem_sub";</div><div class='add'>+			freq-table-hz = &lt;0 0&gt;, &lt;0 0&gt;, &lt;0 0&gt;,</div><div class='add'>+					&lt;0 0&gt;, &lt;0 0&gt;, &lt;0 0&gt;,</div><div class='add'>+					&lt;0 0&gt;, &lt;0 0&gt;;</div><div class='add'>+</div><div class='add'>+			mediatek,ufs-disable-mcq;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		lvts_mcu: thermal-sensor@11278000 {</div><div class='add'>+			compatible = "mediatek,mt8195-lvts-mcu";</div><div class='add'>+			reg = &lt;0 0x11278000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg_ao CLK_INFRA_AO_THERM&gt;;</div><div class='add'>+			resets = &lt;&amp;infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST&gt;;</div><div class='add'>+			nvmem-cells = &lt;&amp;lvts_efuse_data1 &amp;lvts_efuse_data2&gt;;</div><div class='add'>+			nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";</div><div class='add'>+			#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		xhci1: usb@11290000 {</div><div class='add'>+			compatible = "mediatek,mt8195-xhci",</div><div class='add'>+				     "mediatek,mtk-xhci";</div><div class='add'>+			reg = &lt;0 0x11290000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11293e00 0 0x0100&gt;;</div><div class='add'>+			reg-names = "mac", "ippc";</div><div class='add'>+			interrupts = &lt;GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			phys = &lt;&amp;u2port1 PHY_TYPE_USB2&gt;, &lt;&amp;u3port1 PHY_TYPE_USB3&gt;;</div><div class='add'>+			assigned-clocks = &lt;&amp;topckgen CLK_TOP_USB_TOP_1P&gt;,</div><div class='add'>+					  &lt;&amp;topckgen CLK_TOP_SSUSB_XHCI_1P&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_UNIVPLL_D5_D4&gt;,</div><div class='add'>+						 &lt;&amp;topckgen CLK_TOP_UNIVPLL_D5_D4&gt;;</div><div class='add'>+			clocks = &lt;&amp;pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SSUSB_P1_REF&gt;,</div><div class='add'>+				 &lt;&amp;apmixedsys CLK_APMIXED_USB1PLL&gt;,</div><div class='add'>+				 &lt;&amp;clk26m&gt;,</div><div class='add'>+				 &lt;&amp;pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI&gt;;</div><div class='add'>+			clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",</div><div class='add'>+				      "xhci_ck";</div><div class='add'>+			mediatek,syscon-wakeup = &lt;&amp;pericfg 0x400 104&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ssusb2: usb@112a1000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mtu3", "mediatek,mtu3";</div><div class='add'>+			reg = &lt;0 0x112a1000 0 0x2dff&gt;, &lt;0 0x112a3e00 0 0x0100&gt;;</div><div class='add'>+			reg-names = "mac", "ippc";</div><div class='add'>+			ranges = &lt;0 0 0 0x112a0000 0 0x3f00&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			assigned-clocks = &lt;&amp;topckgen CLK_TOP_USB_TOP_2P&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_UNIVPLL_D5_D4&gt;;</div><div class='add'>+			clocks = &lt;&amp;pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SSUSB_P2_REF&gt;,</div><div class='add'>+				 &lt;&amp;pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI&gt;;</div><div class='add'>+			clock-names = "sys_ck", "ref_ck", "mcu_ck";</div><div class='add'>+			phys = &lt;&amp;u2port2 PHY_TYPE_USB2&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+			mediatek,syscon-wakeup = &lt;&amp;pericfg 0x400 105&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			xhci2: usb@0 {</div><div class='add'>+				compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci";</div><div class='add'>+				reg = &lt;0 0 0 0x1000&gt;;</div><div class='add'>+				reg-names = "mac";</div><div class='add'>+				interrupts = &lt;GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				assigned-clocks = &lt;&amp;topckgen CLK_TOP_SSUSB_XHCI_2P&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_UNIVPLL_D5_D4&gt;;</div><div class='add'>+				clocks = &lt;&amp;pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI&gt;;</div><div class='add'>+				clock-names = "sys_ck";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ssusb3: usb@112b1000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mtu3", "mediatek,mtu3";</div><div class='add'>+			reg = &lt;0 0x112b1000 0 0x2dff&gt;, &lt;0 0x112b3e00 0 0x0100&gt;;</div><div class='add'>+			reg-names = "mac", "ippc";</div><div class='add'>+			ranges = &lt;0 0 0 0x112b0000 0 0x3f00&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			assigned-clocks = &lt;&amp;topckgen CLK_TOP_USB_TOP_3P&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_UNIVPLL_D5_D4&gt;;</div><div class='add'>+			clocks = &lt;&amp;pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SSUSB_P3_REF&gt;,</div><div class='add'>+				 &lt;&amp;pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI&gt;;</div><div class='add'>+			clock-names = "sys_ck", "ref_ck", "mcu_ck";</div><div class='add'>+			phys = &lt;&amp;u2port3 PHY_TYPE_USB2&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+			mediatek,syscon-wakeup = &lt;&amp;pericfg 0x400 106&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			xhci3: usb@0 {</div><div class='add'>+				compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci";</div><div class='add'>+				reg = &lt;0 0 0 0x1000&gt;;</div><div class='add'>+				reg-names = "mac";</div><div class='add'>+				interrupts = &lt;GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				assigned-clocks = &lt;&amp;topckgen CLK_TOP_SSUSB_XHCI_3P&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_UNIVPLL_D5_D4&gt;;</div><div class='add'>+				clocks = &lt;&amp;pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI&gt;;</div><div class='add'>+				clock-names = "sys_ck";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie0: pcie@112f0000 {</div><div class='add'>+			compatible = "mediatek,mt8195-pcie",</div><div class='add'>+				     "mediatek,mt8192-pcie";</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			reg = &lt;0 0x112f0000 0 0x4000&gt;;</div><div class='add'>+			reg-names = "pcie-mac";</div><div class='add'>+			interrupts = &lt;GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			bus-range = &lt;0x00 0xff&gt;;</div><div class='add'>+			ranges = &lt;0x81000000 0 0x20000000</div><div class='add'>+				  0x0 0x20000000 0 0x200000&gt;,</div><div class='add'>+				 &lt;0x82000000 0 0x20200000</div><div class='add'>+				  0x0 0x20200000 0 0x3e00000&gt;;</div><div class='add'>+</div><div class='add'>+			iommu-map = &lt;0 &amp;iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2&gt;;</div><div class='add'>+			iommu-map-mask = &lt;0x0&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_PCIE_TL_26M&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_PCIE_TL_96M&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_PCIE_TL_32K&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M&gt;,</div><div class='add'>+				 &lt;&amp;pericfg_ao CLK_PERI_AO_PCIE_P0_MEM&gt;;</div><div class='add'>+			clock-names = "pl_250m", "tl_26m", "tl_96m",</div><div class='add'>+				      "tl_32k", "peri_26m", "peri_mem";</div><div class='add'>+			assigned-clocks = &lt;&amp;topckgen CLK_TOP_TL&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_MAINPLL_D4_D4&gt;;</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;pciephy&gt;;</div><div class='add'>+			phy-names = "pcie-phy";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_PCIE_MAC_P0&gt;;</div><div class='add'>+</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;pcie_intc0 0&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;pcie_intc0 1&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;pcie_intc0 2&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;pcie_intc0 3&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcie_intc0: interrupt-controller {</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#address-cells = &lt;0&gt;;</div><div class='add'>+				#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie1: pcie@112f8000 {</div><div class='add'>+			compatible = "mediatek,mt8195-pcie",</div><div class='add'>+				     "mediatek,mt8192-pcie";</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			reg = &lt;0 0x112f8000 0 0x4000&gt;;</div><div class='add'>+			reg-names = "pcie-mac";</div><div class='add'>+			interrupts = &lt;GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			bus-range = &lt;0x00 0xff&gt;;</div><div class='add'>+			ranges = &lt;0x81000000 0 0x24000000</div><div class='add'>+				  0x0 0x24000000 0 0x200000&gt;,</div><div class='add'>+				 &lt;0x82000000 0 0x24200000</div><div class='add'>+				  0x0 0x24200000 0 0x3e00000&gt;;</div><div class='add'>+</div><div class='add'>+			iommu-map = &lt;0 &amp;iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2&gt;;</div><div class='add'>+			iommu-map-mask = &lt;0x0&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1&gt;,</div><div class='add'>+				 &lt;&amp;clk26m&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_PCIE_P1_TL_96M&gt;,</div><div class='add'>+				 &lt;&amp;clk26m&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_PCIE_P1_PERI_26M&gt;,</div><div class='add'>+				 /* Designer has connect pcie1 with peri_mem_p0 clock */</div><div class='add'>+				 &lt;&amp;pericfg_ao CLK_PERI_AO_PCIE_P0_MEM&gt;;</div><div class='add'>+			clock-names = "pl_250m", "tl_26m", "tl_96m",</div><div class='add'>+				      "tl_32k", "peri_26m", "peri_mem";</div><div class='add'>+			assigned-clocks = &lt;&amp;topckgen CLK_TOP_TL_P1&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_MAINPLL_D4_D4&gt;;</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;u3port1 PHY_TYPE_PCIE&gt;;</div><div class='add'>+			phy-names = "pcie-phy";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_PCIE_MAC_P1&gt;;</div><div class='add'>+</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;pcie_intc1 0&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;pcie_intc1 1&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;pcie_intc1 2&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;pcie_intc1 3&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcie_intc1: interrupt-controller {</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#address-cells = &lt;0&gt;;</div><div class='add'>+				#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nor_flash: spi@1132c000 {</div><div class='add'>+			compatible = "mediatek,mt8195-nor",</div><div class='add'>+				     "mediatek,mt8173-nor";</div><div class='add'>+			reg = &lt;0 0x1132c000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_SPINOR&gt;,</div><div class='add'>+				 &lt;&amp;pericfg_ao CLK_PERI_AO_FLASHIF_FLASH&gt;,</div><div class='add'>+				 &lt;&amp;pericfg_ao CLK_PERI_AO_FLASHIF_BUS&gt;;</div><div class='add'>+			clock-names = "spi", "sf", "axi";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		efuse: efuse@11c10000 {</div><div class='add'>+			compatible = "mediatek,mt8195-efuse", "mediatek,efuse";</div><div class='add'>+			reg = &lt;0 0x11c10000 0 0x1000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			u3_tx_imp_p0: usb3-tx-imp@184,1 {</div><div class='add'>+				reg = &lt;0x184 0x1&gt;;</div><div class='add'>+				bits = &lt;0 5&gt;;</div><div class='add'>+			};</div><div class='add'>+			u3_rx_imp_p0: usb3-rx-imp@184,2 {</div><div class='add'>+				reg = &lt;0x184 0x2&gt;;</div><div class='add'>+				bits = &lt;5 5&gt;;</div><div class='add'>+			};</div><div class='add'>+			u3_intr_p0: usb3-intr@185 {</div><div class='add'>+				reg = &lt;0x185 0x1&gt;;</div><div class='add'>+				bits = &lt;2 6&gt;;</div><div class='add'>+			};</div><div class='add'>+			comb_tx_imp_p1: usb3-tx-imp@186,1 {</div><div class='add'>+				reg = &lt;0x186 0x1&gt;;</div><div class='add'>+				bits = &lt;0 5&gt;;</div><div class='add'>+			};</div><div class='add'>+			comb_rx_imp_p1: usb3-rx-imp@186,2 {</div><div class='add'>+				reg = &lt;0x186 0x2&gt;;</div><div class='add'>+				bits = &lt;5 5&gt;;</div><div class='add'>+			};</div><div class='add'>+			comb_intr_p1: usb3-intr@187 {</div><div class='add'>+				reg = &lt;0x187 0x1&gt;;</div><div class='add'>+				bits = &lt;2 6&gt;;</div><div class='add'>+			};</div><div class='add'>+			u2_intr_p0: usb2-intr-p0@188,1 {</div><div class='add'>+				reg = &lt;0x188 0x1&gt;;</div><div class='add'>+				bits = &lt;0 5&gt;;</div><div class='add'>+			};</div><div class='add'>+			u2_intr_p1: usb2-intr-p1@188,2 {</div><div class='add'>+				reg = &lt;0x188 0x2&gt;;</div><div class='add'>+				bits = &lt;5 5&gt;;</div><div class='add'>+			};</div><div class='add'>+			u2_intr_p2: usb2-intr-p2@189,1 {</div><div class='add'>+				reg = &lt;0x189 0x1&gt;;</div><div class='add'>+				bits = &lt;2 5&gt;;</div><div class='add'>+			};</div><div class='add'>+			u2_intr_p3: usb2-intr-p3@189,2 {</div><div class='add'>+				reg = &lt;0x189 0x2&gt;;</div><div class='add'>+				bits = &lt;7 5&gt;;</div><div class='add'>+			};</div><div class='add'>+			pciephy_rx_ln1: pciephy-rx-ln1@190,1 {</div><div class='add'>+				reg = &lt;0x190 0x1&gt;;</div><div class='add'>+				bits = &lt;0 4&gt;;</div><div class='add'>+			};</div><div class='add'>+			pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190,2 {</div><div class='add'>+				reg = &lt;0x190 0x1&gt;;</div><div class='add'>+				bits = &lt;4 4&gt;;</div><div class='add'>+			};</div><div class='add'>+			pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191,1 {</div><div class='add'>+				reg = &lt;0x191 0x1&gt;;</div><div class='add'>+				bits = &lt;0 4&gt;;</div><div class='add'>+			};</div><div class='add'>+			pciephy_rx_ln0: pciephy-rx-ln0@191,2 {</div><div class='add'>+				reg = &lt;0x191 0x1&gt;;</div><div class='add'>+				bits = &lt;4 4&gt;;</div><div class='add'>+			};</div><div class='add'>+			pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192,1 {</div><div class='add'>+				reg = &lt;0x192 0x1&gt;;</div><div class='add'>+				bits = &lt;0 4&gt;;</div><div class='add'>+			};</div><div class='add'>+			pciephy_tx_ln0_pmos: pciephy-tx-ln0-pmos@192,2 {</div><div class='add'>+				reg = &lt;0x192 0x1&gt;;</div><div class='add'>+				bits = &lt;4 4&gt;;</div><div class='add'>+			};</div><div class='add'>+			pciephy_glb_intr: pciephy-glb-intr@193 {</div><div class='add'>+				reg = &lt;0x193 0x1&gt;;</div><div class='add'>+				bits = &lt;0 4&gt;;</div><div class='add'>+			};</div><div class='add'>+			dp_calibration: dp-data@1ac {</div><div class='add'>+				reg = &lt;0x1ac 0x10&gt;;</div><div class='add'>+			};</div><div class='add'>+			lvts_efuse_data1: lvts1-calib@1bc {</div><div class='add'>+				reg = &lt;0x1bc 0x14&gt;;</div><div class='add'>+			};</div><div class='add'>+			lvts_efuse_data2: lvts2-calib@1d0 {</div><div class='add'>+				reg = &lt;0x1d0 0x38&gt;;</div><div class='add'>+			};</div><div class='add'>+			svs_calib_data: svs-calib@580 {</div><div class='add'>+				reg = &lt;0x580 0x64&gt;;</div><div class='add'>+			};</div><div class='add'>+			socinfo-data1@7a0 {</div><div class='add'>+				reg = &lt;0x7a0 0x4&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		u3phy2: t-phy@11c40000 {</div><div class='add'>+			compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges = &lt;0 0 0x11c40000 0x700&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			u2port2: usb-phy@0 {</div><div class='add'>+				reg = &lt;0x0 0x700&gt;;</div><div class='add'>+				clocks = &lt;&amp;topckgen CLK_TOP_SSUSB_PHY_P2_REF&gt;;</div><div class='add'>+				clock-names = "ref";</div><div class='add'>+				#phy-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		u3phy3: t-phy@11c50000 {</div><div class='add'>+			compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges = &lt;0 0 0x11c50000 0x700&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			u2port3: usb-phy@0 {</div><div class='add'>+				reg = &lt;0x0 0x700&gt;;</div><div class='add'>+				clocks = &lt;&amp;topckgen CLK_TOP_SSUSB_PHY_P3_REF&gt;;</div><div class='add'>+				clock-names = "ref";</div><div class='add'>+				#phy-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mipi_tx0: dsi-phy@11c80000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mipi-tx", "mediatek,mt8183-mipi-tx";</div><div class='add'>+			reg = &lt;0 0x11c80000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk26m&gt;;</div><div class='add'>+			clock-output-names = "mipi_tx0_pll";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mipi_tx1: dsi-phy@11c90000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mipi-tx", "mediatek,mt8183-mipi-tx";</div><div class='add'>+			reg = &lt;0 0x11c90000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk26m&gt;;</div><div class='add'>+			clock-output-names = "mipi_tx1_pll";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c5: i2c@11d00000 {</div><div class='add'>+			compatible = "mediatek,mt8195-i2c",</div><div class='add'>+				     "mediatek,mt8192-i2c";</div><div class='add'>+			reg = &lt;0 0x11d00000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x10220580 0 0x80&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clock-div = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_APDMA_B&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c6: i2c@11d01000 {</div><div class='add'>+			compatible = "mediatek,mt8195-i2c",</div><div class='add'>+				     "mediatek,mt8192-i2c";</div><div class='add'>+			reg = &lt;0 0x11d01000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x10220600 0 0x80&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clock-div = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C6&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_APDMA_B&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c7: i2c@11d02000 {</div><div class='add'>+			compatible = "mediatek,mt8195-i2c",</div><div class='add'>+				     "mediatek,mt8192-i2c";</div><div class='add'>+			reg = &lt;0 0x11d02000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x10220680 0 0x80&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clock-div = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_APDMA_B&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		imp_iic_wrap_s: clock-controller@11d03000 {</div><div class='add'>+			compatible = "mediatek,mt8195-imp_iic_wrap_s";</div><div class='add'>+			reg = &lt;0 0x11d03000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c0: i2c@11e00000 {</div><div class='add'>+			compatible = "mediatek,mt8195-i2c",</div><div class='add'>+				     "mediatek,mt8192-i2c";</div><div class='add'>+			reg = &lt;0 0x11e00000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x10220080 0 0x80&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clock-div = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_APDMA_B&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c1: i2c@11e01000 {</div><div class='add'>+			compatible = "mediatek,mt8195-i2c",</div><div class='add'>+				     "mediatek,mt8192-i2c";</div><div class='add'>+			reg = &lt;0 0x11e01000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x10220200 0 0x80&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clock-div = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_APDMA_B&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c2: i2c@11e02000 {</div><div class='add'>+			compatible = "mediatek,mt8195-i2c",</div><div class='add'>+				     "mediatek,mt8192-i2c";</div><div class='add'>+			reg = &lt;0 0x11e02000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x10220380 0 0x80&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clock-div = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_APDMA_B&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c3: i2c@11e03000 {</div><div class='add'>+			compatible = "mediatek,mt8195-i2c",</div><div class='add'>+				     "mediatek,mt8192-i2c";</div><div class='add'>+			reg = &lt;0 0x11e03000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x10220480 0 0x80&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clock-div = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_APDMA_B&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c4: i2c@11e04000 {</div><div class='add'>+			compatible = "mediatek,mt8195-i2c",</div><div class='add'>+				     "mediatek,mt8192-i2c";</div><div class='add'>+			reg = &lt;0 0x11e04000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x10220500 0 0x80&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clock-div = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4&gt;,</div><div class='add'>+				 &lt;&amp;infracfg_ao CLK_INFRA_AO_APDMA_B&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		imp_iic_wrap_w: clock-controller@11e05000 {</div><div class='add'>+			compatible = "mediatek,mt8195-imp_iic_wrap_w";</div><div class='add'>+			reg = &lt;0 0x11e05000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		u3phy1: t-phy@11e30000 {</div><div class='add'>+			compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges = &lt;0 0 0x11e30000 0xe00&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			u2port1: usb-phy@0 {</div><div class='add'>+				reg = &lt;0x0 0x700&gt;;</div><div class='add'>+				clocks = &lt;&amp;topckgen CLK_TOP_SSUSB_PHY_P1_REF&gt;,</div><div class='add'>+					 &lt;&amp;clk26m&gt;;</div><div class='add'>+				clock-names = "ref", "da_ref";</div><div class='add'>+				#phy-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			u3port1: usb-phy@700 {</div><div class='add'>+				reg = &lt;0x700 0x700&gt;;</div><div class='add'>+				clocks = &lt;&amp;apmixedsys CLK_APMIXED_PLL_SSUSB26M&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_SSUSB_PHY_P1_REF&gt;;</div><div class='add'>+				clock-names = "ref", "da_ref";</div><div class='add'>+				nvmem-cells = &lt;&amp;comb_intr_p1&gt;,</div><div class='add'>+					      &lt;&amp;comb_rx_imp_p1&gt;,</div><div class='add'>+					      &lt;&amp;comb_tx_imp_p1&gt;;</div><div class='add'>+				nvmem-cell-names = "intr", "rx_imp", "tx_imp";</div><div class='add'>+				#phy-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		u3phy0: t-phy@11e40000 {</div><div class='add'>+			compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges = &lt;0 0 0x11e40000 0xe00&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			u2port0: usb-phy@0 {</div><div class='add'>+				reg = &lt;0x0 0x700&gt;;</div><div class='add'>+				clocks = &lt;&amp;topckgen CLK_TOP_SSUSB_PHY_REF&gt;,</div><div class='add'>+					 &lt;&amp;clk26m&gt;;</div><div class='add'>+				clock-names = "ref", "da_ref";</div><div class='add'>+				#phy-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			u3port0: usb-phy@700 {</div><div class='add'>+				reg = &lt;0x700 0x700&gt;;</div><div class='add'>+				clocks = &lt;&amp;apmixedsys CLK_APMIXED_PLL_SSUSB26M&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_SSUSB_PHY_REF&gt;;</div><div class='add'>+				clock-names = "ref", "da_ref";</div><div class='add'>+				nvmem-cells = &lt;&amp;u3_intr_p0&gt;,</div><div class='add'>+					      &lt;&amp;u3_rx_imp_p0&gt;,</div><div class='add'>+					      &lt;&amp;u3_tx_imp_p0&gt;;</div><div class='add'>+				nvmem-cell-names = "intr", "rx_imp", "tx_imp";</div><div class='add'>+				#phy-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pciephy: phy@11e80000 {</div><div class='add'>+			compatible = "mediatek,mt8195-pcie-phy";</div><div class='add'>+			reg = &lt;0 0x11e80000 0 0x10000&gt;;</div><div class='add'>+			reg-names = "sif";</div><div class='add'>+			nvmem-cells = &lt;&amp;pciephy_glb_intr&gt;, &lt;&amp;pciephy_tx_ln0_pmos&gt;,</div><div class='add'>+				      &lt;&amp;pciephy_tx_ln0_nmos&gt;, &lt;&amp;pciephy_rx_ln0&gt;,</div><div class='add'>+				      &lt;&amp;pciephy_tx_ln1_pmos&gt;, &lt;&amp;pciephy_tx_ln1_nmos&gt;,</div><div class='add'>+				      &lt;&amp;pciephy_rx_ln1&gt;;</div><div class='add'>+			nvmem-cell-names = "glb_intr", "tx_ln0_pmos",</div><div class='add'>+					   "tx_ln0_nmos", "rx_ln0",</div><div class='add'>+					   "tx_ln1_pmos", "tx_ln1_nmos",</div><div class='add'>+					   "rx_ln1";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_PCIE_PHY&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ufsphy: ufs-phy@11fa0000 {</div><div class='add'>+			compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy";</div><div class='add'>+			reg = &lt;0 0x11fa0000 0 0xc000&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk26m&gt;, &lt;&amp;clk26m&gt;;</div><div class='add'>+			clock-names = "unipro", "mp";</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu: gpu@13000000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mali", "mediatek,mt8192-mali",</div><div class='add'>+				     "arm,mali-valhall-jm";</div><div class='add'>+			reg = &lt;0 0x13000000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;mfgcfg CLK_MFG_BG3D&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+				     &lt;GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH 0&gt;,</div><div class='add'>+				     &lt;GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			interrupt-names = "job", "mmu", "gpu";</div><div class='add'>+			operating-points-v2 = &lt;&amp;gpu_opp_table&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_MFG2&gt;,</div><div class='add'>+					&lt;&amp;spm MT8195_POWER_DOMAIN_MFG3&gt;,</div><div class='add'>+					&lt;&amp;spm MT8195_POWER_DOMAIN_MFG4&gt;,</div><div class='add'>+					&lt;&amp;spm MT8195_POWER_DOMAIN_MFG5&gt;,</div><div class='add'>+					&lt;&amp;spm MT8195_POWER_DOMAIN_MFG6&gt;;</div><div class='add'>+			power-domain-names = "core0", "core1", "core2", "core3", "core4";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mfgcfg: clock-controller@13fbf000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mfgcfg";</div><div class='add'>+			reg = &lt;0 0x13fbf000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vppsys0: syscon@14000000 {</div><div class='add'>+			compatible = "mediatek,mt8195-vppsys0", "syscon";</div><div class='add'>+			reg = &lt;0 0x14000000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_1400XXXX 0 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dma-controller@14001000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mdp3-rdma";</div><div class='add'>+			reg = &lt;0 0x14001000 0 0x1000&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_1400XXXX 0x1000 0x1000&gt;;</div><div class='add'>+			mediatek,gce-events = &lt;CMDQ_EVENT_VPP0_MDP_RDMA_SOF&gt;,</div><div class='add'>+					      &lt;CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE&gt;;</div><div class='add'>+			mediatek,scp = &lt;&amp;scp&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VPPSYS0&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu_vpp M4U_PORT_L4_MDP_RDMA&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys0 CLK_VPP0_MDP_RDMA&gt;;</div><div class='add'>+			mboxes = &lt;&amp;gce1 12 CMDQ_THR_PRIO_1&gt;,</div><div class='add'>+				 &lt;&amp;gce1 13 CMDQ_THR_PRIO_1&gt;,</div><div class='add'>+				 &lt;&amp;gce1 14 CMDQ_THR_PRIO_1&gt;,</div><div class='add'>+				 &lt;&amp;gce1 21 CMDQ_THR_PRIO_1&gt;,</div><div class='add'>+				 &lt;&amp;gce1 22 CMDQ_THR_PRIO_1&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14002000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mdp3-fg";</div><div class='add'>+			reg = &lt;0 0x14002000 0 0x1000&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_1400XXXX 0x2000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys0 CLK_VPP0_MDP_FG&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14003000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mdp3-stitch";</div><div class='add'>+			reg = &lt;0 0x14003000 0 0x1000&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_1400XXXX 0x3000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys0 CLK_VPP0_STITCH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14004000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mdp3-hdr";</div><div class='add'>+			reg = &lt;0 0x14004000 0 0x1000&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_1400XXXX 0x4000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys0 CLK_VPP0_MDP_HDR&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14005000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mdp3-aal";</div><div class='add'>+			reg = &lt;0 0x14005000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_1400XXXX 0x5000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys0 CLK_VPP0_MDP_AAL&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VPPSYS0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14006000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";</div><div class='add'>+			reg = &lt;0 0x14006000 0 0x1000&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_1400XXXX 0x6000 0x1000&gt;;</div><div class='add'>+			mediatek,gce-events = &lt;CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF&gt;,</div><div class='add'>+					      &lt;CMDQ_EVENT_VPP0_MDP_RSZ_FRAME_DONE&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys0 CLK_VPP0_MDP_RSZ&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14007000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mdp3-tdshp";</div><div class='add'>+			reg = &lt;0 0x14007000 0 0x1000&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_1400XXXX 0x7000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys0 CLK_VPP0_MDP_TDSHP&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14008000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mdp3-color";</div><div class='add'>+			reg = &lt;0 0x14008000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_1400XXXX 0x8000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys0 CLK_VPP0_MDP_COLOR&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VPPSYS0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14009000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mdp3-ovl";</div><div class='add'>+			reg = &lt;0 0x14009000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_1400XXXX 0x9000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys0 CLK_VPP0_MDP_OVL&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VPPSYS0&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu_vpp M4U_PORT_L4_MDP_OVL&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@1400a000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mdp3-padding";</div><div class='add'>+			reg = &lt;0 0x1400a000 0 0x1000&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_1400XXXX 0xa000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys0 CLK_VPP0_PADDING&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VPPSYS0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@1400b000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mdp3-tcc";</div><div class='add'>+			reg = &lt;0 0x1400b000 0 0x1000&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_1400XXXX 0xb000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys0 CLK_VPP0_MDP_TCC&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dma-controller@1400c000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";</div><div class='add'>+			reg = &lt;0 0x1400c000 0 0x1000&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_1400XXXX 0xc000 0x1000&gt;;</div><div class='add'>+			mediatek,gce-events = &lt;CMDQ_EVENT_VPP0_MDP_WROT_SOF&gt;,</div><div class='add'>+					      &lt;CMDQ_EVENT_VPP0_MDP_WROT_VIDO_WDONE&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys0 CLK_VPP0_MDP_WROT&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu_vpp M4U_PORT_L4_MDP_WROT&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VPPSYS0&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mutex@1400f000 {</div><div class='add'>+			compatible = "mediatek,mt8195-vpp-mutex";</div><div class='add'>+			reg = &lt;0 0x1400f000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_1400XXXX 0xf000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys0 CLK_VPP0_MUTEX&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VPPSYS0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smi_sub_common_vpp0_vpp1_2x1: smi@14010000 {</div><div class='add'>+			compatible = "mediatek,mt8195-smi-sub-common";</div><div class='add'>+			reg = &lt;0 0x14010000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys0 CLK_VPP0_GALS_VPP1_WPE&gt;,</div><div class='add'>+			       &lt;&amp;vppsys0 CLK_VPP0_GALS_VPP1_WPE&gt;,</div><div class='add'>+			       &lt;&amp;vppsys0 CLK_VPP0_GALS_VPP1_WPE&gt;;</div><div class='add'>+			clock-names = "apb", "smi", "gals0";</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common_vpp&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VPPSYS0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smi_sub_common_vdec_vpp0_2x1: smi@14011000 {</div><div class='add'>+			compatible = "mediatek,mt8195-smi-sub-common";</div><div class='add'>+			reg = &lt;0 0x14011000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1&gt;,</div><div class='add'>+				 &lt;&amp;vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1&gt;,</div><div class='add'>+				 &lt;&amp;vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1&gt;;</div><div class='add'>+			clock-names = "apb", "smi", "gals0";</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common_vpp&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VPPSYS0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smi_common_vpp: smi@14012000 {</div><div class='add'>+			compatible = "mediatek,mt8195-smi-common-vpp";</div><div class='add'>+			reg = &lt;0 0x14012000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys0 CLK_VPP0_SMI_COMMON_LARB4&gt;,</div><div class='add'>+			       &lt;&amp;vppsys0 CLK_VPP0_SMI_COMMON_LARB4&gt;,</div><div class='add'>+			       &lt;&amp;vppsys0 CLK_VPP0_SMI_RSI&gt;,</div><div class='add'>+			       &lt;&amp;vppsys0 CLK_VPP0_SMI_RSI&gt;;</div><div class='add'>+			clock-names = "apb", "smi", "gals0", "gals1";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VPPSYS0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb4: larb@14013000 {</div><div class='add'>+			compatible = "mediatek,mt8195-smi-larb";</div><div class='add'>+			reg = &lt;0 0x14013000 0 0x1000&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;4&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_sub_common_vpp0_vpp1_2x1&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys0 CLK_VPP0_GALS_VPP1_WPE&gt;,</div><div class='add'>+			       &lt;&amp;vppsys0 CLK_VPP0_SMI_COMMON_LARB4&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VPPSYS0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		iommu_vpp: iommu@14018000 {</div><div class='add'>+			compatible = "mediatek,mt8195-iommu-vpp";</div><div class='add'>+			reg = &lt;0 0x14018000 0 0x1000&gt;;</div><div class='add'>+			mediatek,larbs = &lt;&amp;larb1 &amp;larb3 &amp;larb4 &amp;larb6 &amp;larb8</div><div class='add'>+					  &amp;larb12 &amp;larb14 &amp;larb16 &amp;larb18</div><div class='add'>+					  &amp;larb20 &amp;larb22 &amp;larb23 &amp;larb26</div><div class='add'>+					  &amp;larb27&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys0 CLK_VPP0_SMI_IOMMU&gt;;</div><div class='add'>+			clock-names = "bclk";</div><div class='add'>+			#iommu-cells = &lt;1&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VPPSYS0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wpesys: clock-controller@14e00000 {</div><div class='add'>+			compatible = "mediatek,mt8195-wpesys";</div><div class='add'>+			reg = &lt;0 0x14e00000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wpesys_vpp0: clock-controller@14e02000 {</div><div class='add'>+			compatible = "mediatek,mt8195-wpesys_vpp0";</div><div class='add'>+			reg = &lt;0 0x14e02000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wpesys_vpp1: clock-controller@14e03000 {</div><div class='add'>+			compatible = "mediatek,mt8195-wpesys_vpp1";</div><div class='add'>+			reg = &lt;0 0x14e03000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb7: larb@14e04000 {</div><div class='add'>+			compatible = "mediatek,mt8195-smi-larb";</div><div class='add'>+			reg = &lt;0 0x14e04000 0 0x1000&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;7&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common_vdo&gt;;</div><div class='add'>+			clocks = &lt;&amp;wpesys CLK_WPE_SMI_LARB7&gt;,</div><div class='add'>+				 &lt;&amp;wpesys CLK_WPE_SMI_LARB7&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_WPESYS&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb8: larb@14e05000 {</div><div class='add'>+			compatible = "mediatek,mt8195-smi-larb";</div><div class='add'>+			reg = &lt;0 0x14e05000 0 0x1000&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;8&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common_vpp&gt;;</div><div class='add'>+			clocks = &lt;&amp;wpesys CLK_WPE_SMI_LARB8&gt;,</div><div class='add'>+			       &lt;&amp;wpesys CLK_WPE_SMI_LARB8&gt;,</div><div class='add'>+			       &lt;&amp;vppsys0 CLK_VPP0_GALS_VPP1_WPE&gt;;</div><div class='add'>+			clock-names = "apb", "smi", "gals";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_WPESYS&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vppsys1: syscon@14f00000 {</div><div class='add'>+			compatible = "mediatek,mt8195-vppsys1", "syscon";</div><div class='add'>+			reg = &lt;0 0x14f00000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f0XXXX 0 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mutex@14f01000 {</div><div class='add'>+			compatible = "mediatek,mt8195-vpp-mutex";</div><div class='add'>+			reg = &lt;0 0x14f01000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f0XXXX 0x1000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_DISP_MUTEX&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VPPSYS1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb5: larb@14f02000 {</div><div class='add'>+			compatible = "mediatek,mt8195-smi-larb";</div><div class='add'>+			reg = &lt;0 0x14f02000 0 0x1000&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;5&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common_vdo&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_VPPSYS1_LARB&gt;,</div><div class='add'>+			       &lt;&amp;vppsys1 CLK_VPP1_VPPSYS1_GALS&gt;,</div><div class='add'>+			       &lt;&amp;vppsys0 CLK_VPP0_GALS_VPP1_LARB5&gt;;</div><div class='add'>+			clock-names = "apb", "smi", "gals";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VPPSYS1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb6: larb@14f03000 {</div><div class='add'>+			compatible = "mediatek,mt8195-smi-larb";</div><div class='add'>+			reg = &lt;0 0x14f03000 0 0x1000&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;6&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_sub_common_vpp0_vpp1_2x1&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_VPPSYS1_LARB&gt;,</div><div class='add'>+			       &lt;&amp;vppsys1 CLK_VPP1_VPPSYS1_GALS&gt;,</div><div class='add'>+			       &lt;&amp;vppsys0 CLK_VPP0_GALS_VPP1_LARB6&gt;;</div><div class='add'>+			clock-names = "apb", "smi", "gals";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VPPSYS1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14f06000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mdp3-split";</div><div class='add'>+			reg = &lt;0 0x14f06000 0 0x1000&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f0XXXX 0x6000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_VPP_SPLIT&gt;,</div><div class='add'>+				 &lt;&amp;vppsys1 CLK_VPP1_HDMI_META&gt;,</div><div class='add'>+				 &lt;&amp;vppsys1 CLK_VPP1_VPP_SPLIT_HDMI&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VPPSYS1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14f07000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mdp3-tcc";</div><div class='add'>+			reg = &lt;0 0x14f07000 0 0x1000&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f0XXXX 0x7000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP1_MDP_TCC&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dma-controller@14f08000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mdp3-rdma";</div><div class='add'>+			reg = &lt;0 0x14f08000 0 0x1000&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f0XXXX 0x8000 0x1000&gt;;</div><div class='add'>+			mediatek,gce-events = &lt;CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_SOF&gt;,</div><div class='add'>+					      &lt;CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_FRAME_DONE&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP1_MDP_RDMA&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu_vdo M4U_PORT_L5_SVPP1_MDP_RDMA&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VPPSYS1&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dma-controller@14f09000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mdp3-rdma";</div><div class='add'>+			reg = &lt;0 0x14f09000 0 0x1000&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f0XXXX 0x9000 0x1000&gt;;</div><div class='add'>+			mediatek,gce-events = &lt;CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_SOF&gt;,</div><div class='add'>+					      &lt;CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_FRAME_DONE&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP2_MDP_RDMA&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu_vdo M4U_PORT_L5_SVPP2_MDP_RDMA&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VPPSYS1&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dma-controller@14f0a000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mdp3-rdma";</div><div class='add'>+			reg = &lt;0 0x14f0a000 0 0x1000&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f0XXXX 0xa000 0x1000&gt;;</div><div class='add'>+			mediatek,gce-events = &lt;CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_SOF&gt;,</div><div class='add'>+					      &lt;CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_FRAME_DONE&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP3_MDP_RDMA&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu_vpp M4U_PORT_L6_SVPP3_MDP_RDMA&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VPPSYS1&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14f0b000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mdp3-fg";</div><div class='add'>+			reg = &lt;0 0x14f0b000 0 0x1000&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f0XXXX 0xb000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP1_MDP_FG&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14f0c000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mdp3-fg";</div><div class='add'>+			reg = &lt;0 0x14f0c000 0 0x1000&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f0XXXX 0xc000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP2_MDP_FG&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14f0d000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mdp3-fg";</div><div class='add'>+			reg = &lt;0 0x14f0d000 0 0x1000&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f0XXXX 0xd000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP3_MDP_FG&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14f0e000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mdp3-hdr";</div><div class='add'>+			reg = &lt;0 0x14f0e000 0 0x1000&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f0XXXX 0xe000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP1_MDP_HDR&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14f0f000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mdp3-hdr";</div><div class='add'>+			reg = &lt;0 0x14f0f000 0 0x1000&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f0XXXX 0xf000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP2_MDP_HDR&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14f10000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mdp3-hdr";</div><div class='add'>+			reg = &lt;0 0x14f10000 0 0x1000&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f1XXXX 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP3_MDP_HDR&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14f11000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mdp3-aal";</div><div class='add'>+			reg = &lt;0 0x14f11000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 617 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f1XXXX 0x1000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP1_MDP_AAL&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VPPSYS1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14f12000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mdp3-aal";</div><div class='add'>+			reg = &lt;0 0x14f12000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f1XXXX 0x2000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP2_MDP_AAL&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VPPSYS1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14f13000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mdp3-aal";</div><div class='add'>+			reg = &lt;0 0x14f13000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f1XXXX 0x3000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP3_MDP_AAL&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VPPSYS1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14f14000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";</div><div class='add'>+			reg = &lt;0 0x14f14000 0 0x1000&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f1XXXX 0x4000 0x1000&gt;;</div><div class='add'>+			mediatek,gce-events = &lt;CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_SOF&gt;,</div><div class='add'>+					      &lt;CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_FRAME_DONE&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP1_MDP_RSZ&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14f15000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";</div><div class='add'>+			reg = &lt;0 0x14f15000 0 0x1000&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f1XXXX 0x5000 0x1000&gt;;</div><div class='add'>+			mediatek,gce-events = &lt;CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_SOF&gt;,</div><div class='add'>+					      &lt;CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_FRAME_DONE&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP2_MDP_RSZ&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14f16000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";</div><div class='add'>+			reg = &lt;0 0x14f16000 0 0x1000&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f1XXXX 0x6000 0x1000&gt;;</div><div class='add'>+			mediatek,gce-events = &lt;CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_SOF&gt;,</div><div class='add'>+					      &lt;CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_FRAME_DONE&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP3_MDP_RSZ&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14f17000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mdp3-tdshp";</div><div class='add'>+			reg = &lt;0 0x14f17000 0 0x1000&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f1XXXX 0x7000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP1_MDP_TDSHP&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14f18000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mdp3-tdshp";</div><div class='add'>+			reg = &lt;0 0x14f18000 0 0x1000&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f1XXXX 0x8000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP2_MDP_TDSHP&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14f19000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mdp3-tdshp";</div><div class='add'>+			reg = &lt;0 0x14f19000 0 0x1000&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f1XXXX 0x9000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP3_MDP_TDSHP&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14f1a000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mdp3-merge";</div><div class='add'>+			reg = &lt;0 0x14f1a000 0 0x1000&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f1XXXX 0xa000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP2_VPP_MERGE&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VPPSYS1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14f1b000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mdp3-merge";</div><div class='add'>+			reg = &lt;0 0x14f1b000 0 0x1000&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f1XXXX 0xb000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP3_VPP_MERGE&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VPPSYS1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14f1c000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mdp3-color";</div><div class='add'>+			reg = &lt;0 0x14f1c000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 628 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f1XXXX 0xc000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP1_MDP_COLOR&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VPPSYS1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14f1d000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mdp3-color";</div><div class='add'>+			reg = &lt;0 0x14f1d000 0 0x1000&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f1XXXX 0xd000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 629 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP2_MDP_COLOR&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VPPSYS1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14f1e000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mdp3-color";</div><div class='add'>+			reg = &lt;0 0x14f1e000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f1XXXX 0xe000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP3_MDP_COLOR&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VPPSYS1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14f1f000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mdp3-ovl";</div><div class='add'>+			reg = &lt;0 0x14f1f000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f1XXXX 0xf000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP1_MDP_OVL&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VPPSYS1&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu_vdo M4U_PORT_L5_SVPP1_MDP_OVL&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14f20000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mdp3-padding";</div><div class='add'>+			reg = &lt;0 0x14f20000 0 0x1000&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f2XXXX 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP1_VPP_PAD&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VPPSYS1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14f21000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mdp3-padding";</div><div class='add'>+			reg = &lt;0 0x14f21000 0 0x1000&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f2XXXX 0x1000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP2_VPP_PAD&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VPPSYS1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display@14f22000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mdp3-padding";</div><div class='add'>+			reg = &lt;0 0x14f22000 0 0x1000&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f2XXXX 0x2000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP3_VPP_PAD&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VPPSYS1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dma-controller@14f23000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";</div><div class='add'>+			reg = &lt;0 0x14f23000 0 0x1000&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f2XXXX 0x3000 0x1000&gt;;</div><div class='add'>+			mediatek,gce-events = &lt;CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_SOF&gt;,</div><div class='add'>+					      &lt;CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_FRAME_DONE&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP1_MDP_WROT&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu_vdo M4U_PORT_L5_SVPP1_MDP_WROT&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VPPSYS1&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dma-controller@14f24000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";</div><div class='add'>+			reg = &lt;0 0x14f24000 0 0x1000&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f2XXXX 0x4000 0x1000&gt;;</div><div class='add'>+			mediatek,gce-events = &lt;CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SOF&gt;,</div><div class='add'>+					&lt;CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_FRAME_DONE&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP2_MDP_WROT&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu_vdo M4U_PORT_L5_SVPP2_MDP_WROT&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VPPSYS1&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dma-controller@14f25000 {</div><div class='add'>+			compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";</div><div class='add'>+			reg = &lt;0 0x14f25000 0 0x1000&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce1 SUBSYS_14f2XXXX 0x5000 0x1000&gt;;</div><div class='add'>+			mediatek,gce-events = &lt;CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SOF&gt;,</div><div class='add'>+					&lt;CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_FRAME_DONE&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys1 CLK_VPP1_SVPP3_MDP_WROT&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu_vpp M4U_PORT_L6_SVPP3_MDP_WROT&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VPPSYS1&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		imgsys: clock-controller@15000000 {</div><div class='add'>+			compatible = "mediatek,mt8195-imgsys";</div><div class='add'>+			reg = &lt;0 0x15000000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb9: larb@15001000 {</div><div class='add'>+			compatible = "mediatek,mt8195-smi-larb";</div><div class='add'>+			reg = &lt;0 0x15001000 0 0x1000&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;9&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_sub_common_img1_3x1&gt;;</div><div class='add'>+			clocks = &lt;&amp;imgsys CLK_IMG_LARB9&gt;,</div><div class='add'>+				 &lt;&amp;imgsys CLK_IMG_LARB9&gt;,</div><div class='add'>+				 &lt;&amp;imgsys CLK_IMG_GALS&gt;;</div><div class='add'>+			clock-names = "apb", "smi", "gals";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_IMG&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smi_sub_common_img0_3x1: smi@15002000 {</div><div class='add'>+			compatible = "mediatek,mt8195-smi-sub-common";</div><div class='add'>+			reg = &lt;0 0x15002000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;imgsys CLK_IMG_IPE&gt;,</div><div class='add'>+				 &lt;&amp;imgsys CLK_IMG_IPE&gt;,</div><div class='add'>+				 &lt;&amp;vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS&gt;;</div><div class='add'>+			clock-names = "apb", "smi", "gals0";</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common_vpp&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_IMG&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smi_sub_common_img1_3x1: smi@15003000 {</div><div class='add'>+			compatible = "mediatek,mt8195-smi-sub-common";</div><div class='add'>+			reg = &lt;0 0x15003000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;imgsys CLK_IMG_LARB9&gt;,</div><div class='add'>+				 &lt;&amp;imgsys CLK_IMG_LARB9&gt;,</div><div class='add'>+				 &lt;&amp;imgsys CLK_IMG_GALS&gt;;</div><div class='add'>+			clock-names = "apb", "smi", "gals0";</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common_vdo&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_IMG&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		imgsys1_dip_top: clock-controller@15110000 {</div><div class='add'>+			compatible = "mediatek,mt8195-imgsys1_dip_top";</div><div class='add'>+			reg = &lt;0 0x15110000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb10: larb@15120000 {</div><div class='add'>+			compatible = "mediatek,mt8195-smi-larb";</div><div class='add'>+			reg = &lt;0 0x15120000 0 0x1000&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;10&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_sub_common_img1_3x1&gt;;</div><div class='add'>+			clocks = &lt;&amp;imgsys CLK_IMG_DIP0&gt;,</div><div class='add'>+			       &lt;&amp;imgsys1_dip_top CLK_IMG1_DIP_TOP_LARB10&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_DIP&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		imgsys1_dip_nr: clock-controller@15130000 {</div><div class='add'>+			compatible = "mediatek,mt8195-imgsys1_dip_nr";</div><div class='add'>+			reg = &lt;0 0x15130000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		imgsys1_wpe: clock-controller@15220000 {</div><div class='add'>+			compatible = "mediatek,mt8195-imgsys1_wpe";</div><div class='add'>+			reg = &lt;0 0x15220000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb11: larb@15230000 {</div><div class='add'>+			compatible = "mediatek,mt8195-smi-larb";</div><div class='add'>+			reg = &lt;0 0x15230000 0 0x1000&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;11&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_sub_common_img1_3x1&gt;;</div><div class='add'>+			clocks = &lt;&amp;imgsys CLK_IMG_WPE0&gt;,</div><div class='add'>+			       &lt;&amp;imgsys1_wpe CLK_IMG1_WPE_LARB11&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_DIP&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ipesys: clock-controller@15330000 {</div><div class='add'>+			compatible = "mediatek,mt8195-ipesys";</div><div class='add'>+			reg = &lt;0 0x15330000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb12: larb@15340000 {</div><div class='add'>+			compatible = "mediatek,mt8195-smi-larb";</div><div class='add'>+			reg = &lt;0 0x15340000 0 0x1000&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;12&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_sub_common_img0_3x1&gt;;</div><div class='add'>+			clocks = &lt;&amp;ipesys CLK_IPE_SMI_LARB12&gt;,</div><div class='add'>+				 &lt;&amp;ipesys CLK_IPE_SMI_LARB12&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_IPE&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		camsys: clock-controller@16000000 {</div><div class='add'>+			compatible = "mediatek,mt8195-camsys";</div><div class='add'>+			reg = &lt;0 0x16000000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb13: larb@16001000 {</div><div class='add'>+			compatible = "mediatek,mt8195-smi-larb";</div><div class='add'>+			reg = &lt;0 0x16001000 0 0x1000&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;13&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_sub_common_cam_4x1&gt;;</div><div class='add'>+			clocks = &lt;&amp;camsys CLK_CAM_LARB13&gt;,</div><div class='add'>+			       &lt;&amp;camsys CLK_CAM_LARB13&gt;,</div><div class='add'>+			       &lt;&amp;camsys CLK_CAM_CAM2MM0_GALS&gt;;</div><div class='add'>+			clock-names = "apb", "smi", "gals";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_CAM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb14: larb@16002000 {</div><div class='add'>+			compatible = "mediatek,mt8195-smi-larb";</div><div class='add'>+			reg = &lt;0 0x16002000 0 0x1000&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;14&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_sub_common_cam_7x1&gt;;</div><div class='add'>+			clocks = &lt;&amp;camsys CLK_CAM_LARB14&gt;,</div><div class='add'>+				 &lt;&amp;camsys CLK_CAM_LARB14&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_CAM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smi_sub_common_cam_4x1: smi@16004000 {</div><div class='add'>+			compatible = "mediatek,mt8195-smi-sub-common";</div><div class='add'>+			reg = &lt;0 0x16004000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;camsys CLK_CAM_LARB13&gt;,</div><div class='add'>+				 &lt;&amp;camsys CLK_CAM_LARB13&gt;,</div><div class='add'>+				 &lt;&amp;camsys CLK_CAM_CAM2MM0_GALS&gt;;</div><div class='add'>+			clock-names = "apb", "smi", "gals0";</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common_vdo&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_CAM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smi_sub_common_cam_7x1: smi@16005000 {</div><div class='add'>+			compatible = "mediatek,mt8195-smi-sub-common";</div><div class='add'>+			reg = &lt;0 0x16005000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;camsys CLK_CAM_LARB14&gt;,</div><div class='add'>+				 &lt;&amp;camsys CLK_CAM_CAM2MM1_GALS&gt;,</div><div class='add'>+				 &lt;&amp;vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS&gt;;</div><div class='add'>+			clock-names = "apb", "smi", "gals0";</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common_vpp&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_CAM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb16: larb@16012000 {</div><div class='add'>+			compatible = "mediatek,mt8195-smi-larb";</div><div class='add'>+			reg = &lt;0 0x16012000 0 0x1000&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;16&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_sub_common_cam_7x1&gt;;</div><div class='add'>+			clocks = &lt;&amp;camsys_rawa CLK_CAM_RAWA_LARBX&gt;,</div><div class='add'>+				 &lt;&amp;camsys_rawa CLK_CAM_RAWA_LARBX&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_CAM_RAWA&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb17: larb@16013000 {</div><div class='add'>+			compatible = "mediatek,mt8195-smi-larb";</div><div class='add'>+			reg = &lt;0 0x16013000 0 0x1000&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;17&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_sub_common_cam_4x1&gt;;</div><div class='add'>+			clocks = &lt;&amp;camsys_yuva CLK_CAM_YUVA_LARBX&gt;,</div><div class='add'>+				 &lt;&amp;camsys_yuva CLK_CAM_YUVA_LARBX&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_CAM_RAWA&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb27: larb@16014000 {</div><div class='add'>+			compatible = "mediatek,mt8195-smi-larb";</div><div class='add'>+			reg = &lt;0 0x16014000 0 0x1000&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;27&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_sub_common_cam_7x1&gt;;</div><div class='add'>+			clocks = &lt;&amp;camsys_rawb CLK_CAM_RAWB_LARBX&gt;,</div><div class='add'>+				 &lt;&amp;camsys_rawb CLK_CAM_RAWB_LARBX&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_CAM_RAWB&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb28: larb@16015000 {</div><div class='add'>+			compatible = "mediatek,mt8195-smi-larb";</div><div class='add'>+			reg = &lt;0 0x16015000 0 0x1000&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;28&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_sub_common_cam_4x1&gt;;</div><div class='add'>+			clocks = &lt;&amp;camsys_yuvb CLK_CAM_YUVB_LARBX&gt;,</div><div class='add'>+				 &lt;&amp;camsys_yuvb CLK_CAM_YUVB_LARBX&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_CAM_RAWB&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		camsys_rawa: clock-controller@1604f000 {</div><div class='add'>+			compatible = "mediatek,mt8195-camsys_rawa";</div><div class='add'>+			reg = &lt;0 0x1604f000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		camsys_yuva: clock-controller@1606f000 {</div><div class='add'>+			compatible = "mediatek,mt8195-camsys_yuva";</div><div class='add'>+			reg = &lt;0 0x1606f000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		camsys_rawb: clock-controller@1608f000 {</div><div class='add'>+			compatible = "mediatek,mt8195-camsys_rawb";</div><div class='add'>+			reg = &lt;0 0x1608f000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		camsys_yuvb: clock-controller@160af000 {</div><div class='add'>+			compatible = "mediatek,mt8195-camsys_yuvb";</div><div class='add'>+			reg = &lt;0 0x160af000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		camsys_mraw: clock-controller@16140000 {</div><div class='add'>+			compatible = "mediatek,mt8195-camsys_mraw";</div><div class='add'>+			reg = &lt;0 0x16140000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb25: larb@16141000 {</div><div class='add'>+			compatible = "mediatek,mt8195-smi-larb";</div><div class='add'>+			reg = &lt;0 0x16141000 0 0x1000&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;25&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_sub_common_cam_4x1&gt;;</div><div class='add'>+			clocks = &lt;&amp;camsys CLK_CAM_LARB13&gt;,</div><div class='add'>+				 &lt;&amp;camsys_mraw CLK_CAM_MRAW_LARBX&gt;,</div><div class='add'>+				 &lt;&amp;camsys CLK_CAM_CAM2MM0_GALS&gt;;</div><div class='add'>+			clock-names = "apb", "smi", "gals";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_CAM_MRAW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb26: larb@16142000 {</div><div class='add'>+			compatible = "mediatek,mt8195-smi-larb";</div><div class='add'>+			reg = &lt;0 0x16142000 0 0x1000&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;26&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_sub_common_cam_7x1&gt;;</div><div class='add'>+			clocks = &lt;&amp;camsys_mraw CLK_CAM_MRAW_LARBX&gt;,</div><div class='add'>+				 &lt;&amp;camsys_mraw CLK_CAM_MRAW_LARBX&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_CAM_MRAW&gt;;</div><div class='add'>+</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ccusys: clock-controller@17200000 {</div><div class='add'>+			compatible = "mediatek,mt8195-ccusys";</div><div class='add'>+			reg = &lt;0 0x17200000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb18: larb@17201000 {</div><div class='add'>+			compatible = "mediatek,mt8195-smi-larb";</div><div class='add'>+			reg = &lt;0 0x17201000 0 0x1000&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;18&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_sub_common_cam_7x1&gt;;</div><div class='add'>+			clocks = &lt;&amp;ccusys CLK_CCU_LARB18&gt;,</div><div class='add'>+				 &lt;&amp;ccusys CLK_CCU_LARB18&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_CAM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		video-codec@18000000 {</div><div class='add'>+			compatible = "mediatek,mt8195-vcodec-dec";</div><div class='add'>+			mediatek,scp = &lt;&amp;scp&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu_vdo M4U_PORT_L21_VDEC_MC_EXT&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			reg = &lt;0 0x18000000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x18004000 0 0x1000&gt;;</div><div class='add'>+			ranges = &lt;0 0 0 0x18000000 0 0x26000&gt;;</div><div class='add'>+</div><div class='add'>+			video-codec@2000 {</div><div class='add'>+				compatible = "mediatek,mtk-vcodec-lat-soc";</div><div class='add'>+				reg = &lt;0 0x2000 0 0x800&gt;;</div><div class='add'>+				iommus = &lt;&amp;iommu_vpp M4U_PORT_L23_VDEC_UFO_ENC_EXT&gt;,</div><div class='add'>+					 &lt;&amp;iommu_vpp M4U_PORT_L23_VDEC_RDMA_EXT&gt;;</div><div class='add'>+				clocks = &lt;&amp;topckgen CLK_TOP_VDEC&gt;,</div><div class='add'>+					 &lt;&amp;vdecsys_soc CLK_VDEC_SOC_VDEC&gt;,</div><div class='add'>+					 &lt;&amp;vdecsys_soc CLK_VDEC_SOC_LAT&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_UNIVPLL_D4&gt;;</div><div class='add'>+				clock-names = "sel", "vdec", "lat", "top";</div><div class='add'>+				assigned-clocks = &lt;&amp;topckgen CLK_TOP_VDEC&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_UNIVPLL_D4&gt;;</div><div class='add'>+				power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VDEC0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			video-codec@10000 {</div><div class='add'>+				compatible = "mediatek,mtk-vcodec-lat";</div><div class='add'>+				reg = &lt;0 0x10000 0 0x800&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				iommus = &lt;&amp;iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD_EXT&gt;,</div><div class='add'>+					 &lt;&amp;iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD2_EXT&gt;,</div><div class='add'>+					 &lt;&amp;iommu_vdo M4U_PORT_L24_VDEC_LAT0_AVC_MC_EXT&gt;,</div><div class='add'>+					 &lt;&amp;iommu_vdo M4U_PORT_L24_VDEC_LAT0_PRED_RD_EXT&gt;,</div><div class='add'>+					 &lt;&amp;iommu_vdo M4U_PORT_L24_VDEC_LAT0_TILE_EXT&gt;,</div><div class='add'>+					 &lt;&amp;iommu_vdo M4U_PORT_L24_VDEC_LAT0_WDMA_EXT&gt;;</div><div class='add'>+				clocks = &lt;&amp;topckgen CLK_TOP_VDEC&gt;,</div><div class='add'>+					 &lt;&amp;vdecsys_soc CLK_VDEC_SOC_VDEC&gt;,</div><div class='add'>+					 &lt;&amp;vdecsys_soc CLK_VDEC_SOC_LAT&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_UNIVPLL_D4&gt;;</div><div class='add'>+				clock-names = "sel", "vdec", "lat", "top";</div><div class='add'>+				assigned-clocks = &lt;&amp;topckgen CLK_TOP_VDEC&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_UNIVPLL_D4&gt;;</div><div class='add'>+				power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VDEC0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			video-codec@25000 {</div><div class='add'>+				compatible = "mediatek,mtk-vcodec-core";</div><div class='add'>+				reg = &lt;0 0x25000 0 0x1000&gt;;		/* VDEC_CORE_MISC */</div><div class='add'>+				interrupts = &lt;GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				iommus = &lt;&amp;iommu_vdo M4U_PORT_L21_VDEC_MC_EXT&gt;,</div><div class='add'>+					 &lt;&amp;iommu_vdo M4U_PORT_L21_VDEC_UFO_EXT&gt;,</div><div class='add'>+					 &lt;&amp;iommu_vdo M4U_PORT_L21_VDEC_PP_EXT&gt;,</div><div class='add'>+					 &lt;&amp;iommu_vdo M4U_PORT_L21_VDEC_PRED_RD_EXT&gt;,</div><div class='add'>+					 &lt;&amp;iommu_vdo M4U_PORT_L21_VDEC_PRED_WR_EXT&gt;,</div><div class='add'>+					 &lt;&amp;iommu_vdo M4U_PORT_L21_VDEC_PPWRAP_EXT&gt;,</div><div class='add'>+					 &lt;&amp;iommu_vdo M4U_PORT_L21_VDEC_TILE_EXT&gt;,</div><div class='add'>+					 &lt;&amp;iommu_vdo M4U_PORT_L21_VDEC_VLD_EXT&gt;,</div><div class='add'>+					 &lt;&amp;iommu_vdo M4U_PORT_L21_VDEC_VLD2_EXT&gt;,</div><div class='add'>+					 &lt;&amp;iommu_vdo M4U_PORT_L21_VDEC_AVC_MV_EXT&gt;;</div><div class='add'>+				clocks = &lt;&amp;topckgen CLK_TOP_VDEC&gt;,</div><div class='add'>+					 &lt;&amp;vdecsys CLK_VDEC_VDEC&gt;,</div><div class='add'>+					 &lt;&amp;vdecsys CLK_VDEC_LAT&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_UNIVPLL_D4&gt;;</div><div class='add'>+				clock-names = "sel", "vdec", "lat", "top";</div><div class='add'>+				assigned-clocks = &lt;&amp;topckgen CLK_TOP_VDEC&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_UNIVPLL_D4&gt;;</div><div class='add'>+				power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VDEC1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb24: larb@1800d000 {</div><div class='add'>+			compatible = "mediatek,mt8195-smi-larb";</div><div class='add'>+			reg = &lt;0 0x1800d000 0 0x1000&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;24&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common_vdo&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdecsys_soc CLK_VDEC_SOC_LARB1&gt;,</div><div class='add'>+				 &lt;&amp;vdecsys_soc CLK_VDEC_SOC_LARB1&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VDEC0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb23: larb@1800e000 {</div><div class='add'>+			compatible = "mediatek,mt8195-smi-larb";</div><div class='add'>+			reg = &lt;0 0x1800e000 0 0x1000&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;23&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_sub_common_vdec_vpp0_2x1&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1&gt;,</div><div class='add'>+				 &lt;&amp;vdecsys_soc CLK_VDEC_SOC_LARB1&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VDEC0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdecsys_soc: clock-controller@1800f000 {</div><div class='add'>+			compatible = "mediatek,mt8195-vdecsys_soc";</div><div class='add'>+			reg = &lt;0 0x1800f000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb21: larb@1802e000 {</div><div class='add'>+			compatible = "mediatek,mt8195-smi-larb";</div><div class='add'>+			reg = &lt;0 0x1802e000 0 0x1000&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;21&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common_vdo&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdecsys CLK_VDEC_LARB1&gt;,</div><div class='add'>+				 &lt;&amp;vdecsys CLK_VDEC_LARB1&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VDEC1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdecsys: clock-controller@1802f000 {</div><div class='add'>+			compatible = "mediatek,mt8195-vdecsys";</div><div class='add'>+			reg = &lt;0 0x1802f000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb22: larb@1803e000 {</div><div class='add'>+			compatible = "mediatek,mt8195-smi-larb";</div><div class='add'>+			reg = &lt;0 0x1803e000 0 0x1000&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;22&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_sub_common_vdec_vpp0_2x1&gt;;</div><div class='add'>+			clocks = &lt;&amp;vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1&gt;,</div><div class='add'>+				 &lt;&amp;vdecsys_core1 CLK_VDEC_CORE1_LARB1&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VDEC2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdecsys_core1: clock-controller@1803f000 {</div><div class='add'>+			compatible = "mediatek,mt8195-vdecsys_core1";</div><div class='add'>+			reg = &lt;0 0x1803f000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		apusys_pll: clock-controller@190f3000 {</div><div class='add'>+			compatible = "mediatek,mt8195-apusys_pll";</div><div class='add'>+			reg = &lt;0 0x190f3000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vencsys: clock-controller@1a000000 {</div><div class='add'>+			compatible = "mediatek,mt8195-vencsys";</div><div class='add'>+			reg = &lt;0 0x1a000000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb19: larb@1a010000 {</div><div class='add'>+			compatible = "mediatek,mt8195-smi-larb";</div><div class='add'>+			reg = &lt;0 0x1a010000 0 0x1000&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;19&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common_vdo&gt;;</div><div class='add'>+			clocks = &lt;&amp;vencsys CLK_VENC_VENC&gt;,</div><div class='add'>+				 &lt;&amp;vencsys CLK_VENC_GALS&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VENC&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		venc: video-codec@1a020000 {</div><div class='add'>+			compatible = "mediatek,mt8195-vcodec-enc";</div><div class='add'>+			reg = &lt;0 0x1a020000 0 0x10000&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu_vdo M4U_PORT_L19_VENC_RCPU&gt;,</div><div class='add'>+				 &lt;&amp;iommu_vdo M4U_PORT_L19_VENC_REC&gt;,</div><div class='add'>+				 &lt;&amp;iommu_vdo M4U_PORT_L19_VENC_BSDMA&gt;,</div><div class='add'>+				 &lt;&amp;iommu_vdo M4U_PORT_L19_VENC_SV_COMV&gt;,</div><div class='add'>+				 &lt;&amp;iommu_vdo M4U_PORT_L19_VENC_RD_COMV&gt;,</div><div class='add'>+				 &lt;&amp;iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA&gt;,</div><div class='add'>+				 &lt;&amp;iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA&gt;,</div><div class='add'>+				 &lt;&amp;iommu_vdo M4U_PORT_L19_VENC_REF_LUMA&gt;,</div><div class='add'>+				 &lt;&amp;iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			mediatek,scp = &lt;&amp;scp&gt;;</div><div class='add'>+			clocks = &lt;&amp;vencsys CLK_VENC_VENC&gt;;</div><div class='add'>+			clock-names = "venc_sel";</div><div class='add'>+			assigned-clocks = &lt;&amp;topckgen CLK_TOP_VENC&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_UNIVPLL_D4&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VENC&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		jpeg-decoder@1a040000 {</div><div class='add'>+			compatible = "mediatek,mt8195-jpgdec";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VDEC1&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0&gt;,</div><div class='add'>+				 &lt;&amp;iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0&gt;,</div><div class='add'>+				 &lt;&amp;iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1&gt;,</div><div class='add'>+				 &lt;&amp;iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1&gt;,</div><div class='add'>+				 &lt;&amp;iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1&gt;,</div><div class='add'>+				 &lt;&amp;iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges = &lt;0 0 0 0x1a040000 0 0x20000&gt;,</div><div class='add'>+				 &lt;1 0 0 0x1b040000 0 0x10000&gt;;</div><div class='add'>+</div><div class='add'>+			jpgdec@0,0 {</div><div class='add'>+				compatible = "mediatek,mt8195-jpgdec-hw";</div><div class='add'>+				reg = &lt;0 0 0 0x10000&gt;;/* JPGDEC_C0 */</div><div class='add'>+				iommus = &lt;&amp;iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0&gt;,</div><div class='add'>+					 &lt;&amp;iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0&gt;,</div><div class='add'>+					 &lt;&amp;iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1&gt;,</div><div class='add'>+					 &lt;&amp;iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1&gt;,</div><div class='add'>+					 &lt;&amp;iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1&gt;,</div><div class='add'>+					 &lt;&amp;iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				clocks = &lt;&amp;vencsys CLK_VENC_JPGDEC&gt;;</div><div class='add'>+				clock-names = "jpgdec";</div><div class='add'>+				power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VDEC0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			jpgdec@0,10000 {</div><div class='add'>+				compatible = "mediatek,mt8195-jpgdec-hw";</div><div class='add'>+				reg = &lt;0 0x10000 0 0x10000&gt;;/* JPGDEC_C1 */</div><div class='add'>+				iommus = &lt;&amp;iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0&gt;,</div><div class='add'>+					 &lt;&amp;iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0&gt;,</div><div class='add'>+					 &lt;&amp;iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1&gt;,</div><div class='add'>+					 &lt;&amp;iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1&gt;,</div><div class='add'>+					 &lt;&amp;iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1&gt;,</div><div class='add'>+					 &lt;&amp;iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				clocks = &lt;&amp;vencsys CLK_VENC_JPGDEC_C1&gt;;</div><div class='add'>+				clock-names = "jpgdec";</div><div class='add'>+				power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VDEC1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			jpgdec@1,0 {</div><div class='add'>+				compatible = "mediatek,mt8195-jpgdec-hw";</div><div class='add'>+				reg = &lt;1 0 0 0x10000&gt;;/* JPGDEC_C2 */</div><div class='add'>+				iommus = &lt;&amp;iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0&gt;,</div><div class='add'>+					 &lt;&amp;iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0&gt;,</div><div class='add'>+					 &lt;&amp;iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1&gt;,</div><div class='add'>+					 &lt;&amp;iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA1&gt;,</div><div class='add'>+					 &lt;&amp;iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET1&gt;,</div><div class='add'>+					 &lt;&amp;iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				clocks = &lt;&amp;vencsys_core1 CLK_VENC_CORE1_JPGDEC&gt;;</div><div class='add'>+				clock-names = "jpgdec";</div><div class='add'>+				power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VDEC2&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vencsys_core1: clock-controller@1b000000 {</div><div class='add'>+			compatible = "mediatek,mt8195-vencsys_core1";</div><div class='add'>+			reg = &lt;0 0x1b000000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdosys0: syscon@1c01a000 {</div><div class='add'>+			compatible = "mediatek,mt8195-vdosys0", "mediatek,mt8195-mmsys", "syscon";</div><div class='add'>+			reg = &lt;0 0x1c01a000 0 0x1000&gt;;</div><div class='add'>+			mboxes = &lt;&amp;gce0 0 CMDQ_THR_PRIO_4&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c01XXXX 0xa000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+		jpeg-encoder@1a030000 {</div><div class='add'>+			compatible = "mediatek,mt8195-jpgenc";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VENC_CORE1&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA&gt;,</div><div class='add'>+					&lt;&amp;iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA&gt;,</div><div class='add'>+					&lt;&amp;iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE&gt;,</div><div class='add'>+					&lt;&amp;iommu_vpp M4U_PORT_L20_JPGENC_BSDMA&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges = &lt;0 0 0 0x1a030000 0 0x10000&gt;,</div><div class='add'>+				 &lt;1 0 0 0x1b030000 0 0x10000&gt;;</div><div class='add'>+</div><div class='add'>+			jpgenc@0,0 {</div><div class='add'>+				compatible = "mediatek,mt8195-jpgenc-hw";</div><div class='add'>+				reg = &lt;0 0 0 0x10000&gt;;</div><div class='add'>+				iommus = &lt;&amp;iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA&gt;,</div><div class='add'>+						&lt;&amp;iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA&gt;,</div><div class='add'>+						&lt;&amp;iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE&gt;,</div><div class='add'>+						&lt;&amp;iommu_vdo M4U_PORT_L19_JPGENC_BSDMA&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				clocks = &lt;&amp;vencsys CLK_VENC_JPGENC&gt;;</div><div class='add'>+				clock-names = "jpgenc";</div><div class='add'>+				power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VENC&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			jpgenc@1,0 {</div><div class='add'>+				compatible = "mediatek,mt8195-jpgenc-hw";</div><div class='add'>+				reg = &lt;1 0 0 0x10000&gt;;</div><div class='add'>+				iommus = &lt;&amp;iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA&gt;,</div><div class='add'>+						&lt;&amp;iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA&gt;,</div><div class='add'>+						&lt;&amp;iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE&gt;,</div><div class='add'>+						&lt;&amp;iommu_vpp M4U_PORT_L20_JPGENC_BSDMA&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+				clocks = &lt;&amp;vencsys_core1 CLK_VENC_CORE1_JPGENC&gt;;</div><div class='add'>+				clock-names = "jpgenc";</div><div class='add'>+				power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VENC_CORE1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb20: larb@1b010000 {</div><div class='add'>+			compatible = "mediatek,mt8195-smi-larb";</div><div class='add'>+			reg = &lt;0 0x1b010000 0 0x1000&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;20&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common_vpp&gt;;</div><div class='add'>+			clocks = &lt;&amp;vencsys_core1 CLK_VENC_CORE1_VENC&gt;,</div><div class='add'>+				 &lt;&amp;vencsys_core1 CLK_VENC_CORE1_GALS&gt;,</div><div class='add'>+				 &lt;&amp;vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1&gt;;</div><div class='add'>+			clock-names = "apb", "smi", "gals";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VENC_CORE1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ovl0: ovl@1c000000 {</div><div class='add'>+			compatible = "mediatek,mt8195-disp-ovl";</div><div class='add'>+			reg = &lt;0 0x1c000000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VDOSYS0&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys0 CLK_VDO0_DISP_OVL0&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c00XXXX 0x0000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					ovl0_in: endpoint { };</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					ovl0_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;rdma0_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rdma0: rdma@1c002000 {</div><div class='add'>+			compatible = "mediatek,mt8195-disp-rdma";</div><div class='add'>+			reg = &lt;0 0x1c002000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VDOSYS0&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys0 CLK_VDO0_DISP_RDMA0&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu_vdo M4U_PORT_L0_DISP_RDMA0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c00XXXX 0x2000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					rdma0_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ovl0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					rdma0_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;color0_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		color0: color@1c003000 {</div><div class='add'>+			compatible = "mediatek,mt8195-disp-color", "mediatek,mt8173-disp-color";</div><div class='add'>+			reg = &lt;0 0x1c003000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VDOSYS0&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys0 CLK_VDO0_DISP_COLOR0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c00XXXX 0x3000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					color0_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;rdma0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					color0_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ccorr0_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ccorr0: ccorr@1c004000 {</div><div class='add'>+			compatible = "mediatek,mt8195-disp-ccorr", "mediatek,mt8192-disp-ccorr";</div><div class='add'>+			reg = &lt;0 0x1c004000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VDOSYS0&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys0 CLK_VDO0_DISP_CCORR0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c00XXXX 0x4000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					ccorr0_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;color0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					ccorr0_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;aal0_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aal0: aal@1c005000 {</div><div class='add'>+			compatible = "mediatek,mt8195-disp-aal", "mediatek,mt8183-disp-aal";</div><div class='add'>+			reg = &lt;0 0x1c005000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VDOSYS0&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys0 CLK_VDO0_DISP_AAL0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c00XXXX 0x5000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					aal0_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ccorr0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					aal0_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;gamma0_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gamma0: gamma@1c006000 {</div><div class='add'>+			compatible = "mediatek,mt8195-disp-gamma", "mediatek,mt8183-disp-gamma";</div><div class='add'>+			reg = &lt;0 0x1c006000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VDOSYS0&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys0 CLK_VDO0_DISP_GAMMA0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c00XXXX 0x6000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					gamma0_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;aal0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					gamma0_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dither0_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dither0: dither@1c007000 {</div><div class='add'>+			compatible = "mediatek,mt8195-disp-dither", "mediatek,mt8183-disp-dither";</div><div class='add'>+			reg = &lt;0 0x1c007000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VDOSYS0&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys0 CLK_VDO0_DISP_DITHER0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c00XXXX 0x7000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					dither0_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;gamma0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					dither0_out: endpoint { };</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dsi0: dsi@1c008000 {</div><div class='add'>+			compatible = "mediatek,mt8195-dsi", "mediatek,mt8183-dsi";</div><div class='add'>+			reg = &lt;0 0x1c008000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VDOSYS0&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys0 CLK_VDO0_DSI0&gt;,</div><div class='add'>+				 &lt;&amp;vdosys0 CLK_VDO0_DSI0_DSI&gt;,</div><div class='add'>+				 &lt;&amp;mipi_tx0&gt;;</div><div class='add'>+			clock-names = "engine", "digital", "hs";</div><div class='add'>+			phys = &lt;&amp;mipi_tx0&gt;;</div><div class='add'>+			phy-names = "dphy";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dsc0: dsc@1c009000 {</div><div class='add'>+			compatible = "mediatek,mt8195-disp-dsc";</div><div class='add'>+			reg = &lt;0 0x1c009000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VDOSYS0&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys0 CLK_VDO0_DSC_WRAP0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c00XXXX 0x9000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dsi1: dsi@1c012000 {</div><div class='add'>+			compatible = "mediatek,mt8195-dsi", "mediatek,mt8183-dsi";</div><div class='add'>+			reg = &lt;0 0x1c012000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VDOSYS0&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys0 CLK_VDO0_DSI1&gt;,</div><div class='add'>+				 &lt;&amp;vdosys0 CLK_VDO0_DSI1_DSI&gt;,</div><div class='add'>+				 &lt;&amp;mipi_tx1&gt;;</div><div class='add'>+			clock-names = "engine", "digital", "hs";</div><div class='add'>+			phys = &lt;&amp;mipi_tx1&gt;;</div><div class='add'>+			phy-names = "dphy";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		merge0: merge@1c014000 {</div><div class='add'>+			compatible = "mediatek,mt8195-disp-merge";</div><div class='add'>+			reg = &lt;0 0x1c014000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VDOSYS0&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys0 CLK_VDO0_VPP_MERGE0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c01XXXX 0x4000 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dp_intf0: dp-intf@1c015000 {</div><div class='add'>+			compatible = "mediatek,mt8195-dp-intf";</div><div class='add'>+			reg = &lt;0 0x1c015000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VDOSYS0&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys0 CLK_VDO0_DP_INTF0_DP_INTF&gt;,</div><div class='add'>+				 &lt;&amp;vdosys0  CLK_VDO0_DP_INTF0&gt;,</div><div class='add'>+				 &lt;&amp;apmixedsys CLK_APMIXED_TVDPLL1&gt;;</div><div class='add'>+			clock-names = "pixel", "engine", "pll";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mutex: mutex@1c016000 {</div><div class='add'>+			compatible = "mediatek,mt8195-disp-mutex";</div><div class='add'>+			reg = &lt;0 0x1c016000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VDOSYS0&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys0 CLK_VDO0_DISP_MUTEX0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c01XXXX 0x6000 0x1000&gt;;</div><div class='add'>+			mediatek,gce-events = &lt;CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb0: larb@1c018000 {</div><div class='add'>+			compatible = "mediatek,mt8195-smi-larb";</div><div class='add'>+			reg = &lt;0 0x1c018000 0 0x1000&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;0&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common_vdo&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys0 CLK_VDO0_SMI_LARB&gt;,</div><div class='add'>+				 &lt;&amp;vdosys0 CLK_VDO0_SMI_LARB&gt;,</div><div class='add'>+				 &lt;&amp;vppsys0 CLK_VPP0_GALS_VDO0_LARB0&gt;;</div><div class='add'>+			clock-names = "apb", "smi", "gals";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VDOSYS0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb1: larb@1c019000 {</div><div class='add'>+			compatible = "mediatek,mt8195-smi-larb";</div><div class='add'>+			reg = &lt;0 0x1c019000 0 0x1000&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;1&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common_vpp&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys0 CLK_VDO0_SMI_LARB&gt;,</div><div class='add'>+				 &lt;&amp;vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1&gt;,</div><div class='add'>+				 &lt;&amp;vppsys0 CLK_VPP0_GALS_VDO0_LARB1&gt;;</div><div class='add'>+			clock-names = "apb", "smi", "gals";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VDOSYS0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdosys1: syscon@1c100000 {</div><div class='add'>+			compatible = "mediatek,mt8195-vdosys1", "syscon";</div><div class='add'>+			reg = &lt;0 0x1c100000 0 0x1000&gt;;</div><div class='add'>+			mboxes = &lt;&amp;gce0 1 CMDQ_THR_PRIO_4&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c10XXXX 0x0000 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smi_common_vdo: smi@1c01b000 {</div><div class='add'>+			compatible = "mediatek,mt8195-smi-common-vdo";</div><div class='add'>+			reg = &lt;0 0x1c01b000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys0 CLK_VDO0_SMI_COMMON&gt;,</div><div class='add'>+				 &lt;&amp;vdosys0 CLK_VDO0_SMI_EMI&gt;,</div><div class='add'>+				 &lt;&amp;vdosys0 CLK_VDO0_SMI_RSI&gt;,</div><div class='add'>+				 &lt;&amp;vdosys0 CLK_VDO0_SMI_GALS&gt;;</div><div class='add'>+			clock-names = "apb", "smi", "gals0", "gals1";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VDOSYS0&gt;;</div><div class='add'>+</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		iommu_vdo: iommu@1c01f000 {</div><div class='add'>+			compatible = "mediatek,mt8195-iommu-vdo";</div><div class='add'>+			reg = &lt;0 0x1c01f000 0 0x1000&gt;;</div><div class='add'>+			mediatek,larbs = &lt;&amp;larb0 &amp;larb2 &amp;larb5 &amp;larb7 &amp;larb9</div><div class='add'>+					  &amp;larb10 &amp;larb11 &amp;larb13 &amp;larb17</div><div class='add'>+					  &amp;larb19 &amp;larb21 &amp;larb24 &amp;larb25</div><div class='add'>+					  &amp;larb28&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			#iommu-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys0 CLK_VDO0_SMI_IOMMU&gt;;</div><div class='add'>+			clock-names = "bclk";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VDOSYS0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mutex1: mutex@1c101000 {</div><div class='add'>+			compatible = "mediatek,mt8195-disp-mutex";</div><div class='add'>+			reg = &lt;0 0x1c101000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VDOSYS1&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys1 CLK_VDO1_DISP_MUTEX&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c10XXXX 0x1000 0x1000&gt;;</div><div class='add'>+			mediatek,gce-events = &lt;CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb2: larb@1c102000 {</div><div class='add'>+			compatible = "mediatek,mt8195-smi-larb";</div><div class='add'>+			reg = &lt;0 0x1c102000 0 0x1000&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;2&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common_vdo&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys1 CLK_VDO1_SMI_LARB2&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 CLK_VDO1_SMI_LARB2&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 CLK_VDO1_GALS&gt;;</div><div class='add'>+			clock-names = "apb", "smi", "gals";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VDOSYS1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb3: larb@1c103000 {</div><div class='add'>+			compatible = "mediatek,mt8195-smi-larb";</div><div class='add'>+			reg = &lt;0 0x1c103000 0 0x1000&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;3&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common_vpp&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys1 CLK_VDO1_SMI_LARB3&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 CLK_VDO1_GALS&gt;,</div><div class='add'>+				 &lt;&amp;vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1&gt;;</div><div class='add'>+			clock-names = "apb", "smi", "gals";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VDOSYS1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdo1_rdma0: dma-controller@1c104000 {</div><div class='add'>+			compatible = "mediatek,mt8195-vdo1-rdma";</div><div class='add'>+			reg = &lt;0 0x1c104000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys1 CLK_VDO1_MDP_RDMA0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VDOSYS1&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu_vdo M4U_PORT_L2_MDP_RDMA0&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c10XXXX 0x4000 0x1000&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdo1_rdma1: dma-controller@1c105000 {</div><div class='add'>+			compatible = "mediatek,mt8195-vdo1-rdma";</div><div class='add'>+			reg = &lt;0 0x1c105000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys1 CLK_VDO1_MDP_RDMA1&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VDOSYS1&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu_vpp M4U_PORT_L3_MDP_RDMA1&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c10XXXX 0x5000 0x1000&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdo1_rdma2: dma-controller@1c106000 {</div><div class='add'>+			compatible = "mediatek,mt8195-vdo1-rdma";</div><div class='add'>+			reg = &lt;0 0x1c106000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys1 CLK_VDO1_MDP_RDMA2&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VDOSYS1&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu_vdo M4U_PORT_L2_MDP_RDMA2&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c10XXXX 0x6000 0x1000&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdo1_rdma3: dma-controller@1c107000 {</div><div class='add'>+			compatible = "mediatek,mt8195-vdo1-rdma";</div><div class='add'>+			reg = &lt;0 0x1c107000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys1 CLK_VDO1_MDP_RDMA3&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VDOSYS1&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu_vpp M4U_PORT_L3_MDP_RDMA3&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c10XXXX 0x7000 0x1000&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdo1_rdma4: dma-controller@1c108000 {</div><div class='add'>+			compatible = "mediatek,mt8195-vdo1-rdma";</div><div class='add'>+			reg = &lt;0 0x1c108000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys1 CLK_VDO1_MDP_RDMA4&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VDOSYS1&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu_vdo M4U_PORT_L2_MDP_RDMA4&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c10XXXX 0x8000 0x1000&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdo1_rdma5: dma-controller@1c109000 {</div><div class='add'>+			compatible = "mediatek,mt8195-vdo1-rdma";</div><div class='add'>+			reg = &lt;0 0x1c109000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys1 CLK_VDO1_MDP_RDMA5&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VDOSYS1&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu_vpp M4U_PORT_L3_MDP_RDMA5&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c10XXXX 0x9000 0x1000&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdo1_rdma6: dma-controller@1c10a000 {</div><div class='add'>+			compatible = "mediatek,mt8195-vdo1-rdma";</div><div class='add'>+			reg = &lt;0 0x1c10a000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys1 CLK_VDO1_MDP_RDMA6&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VDOSYS1&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu_vdo M4U_PORT_L2_MDP_RDMA6&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c10XXXX 0xa000 0x1000&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdo1_rdma7: dma-controller@1c10b000 {</div><div class='add'>+			compatible = "mediatek,mt8195-vdo1-rdma";</div><div class='add'>+			reg = &lt;0 0x1c10b000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys1 CLK_VDO1_MDP_RDMA7&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VDOSYS1&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu_vpp M4U_PORT_L3_MDP_RDMA7&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c10XXXX 0xb000 0x1000&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		merge1: vpp-merge@1c10c000 {</div><div class='add'>+			compatible = "mediatek,mt8195-disp-merge";</div><div class='add'>+			reg = &lt;0 0x1c10c000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys1 CLK_VDO1_VPP_MERGE0&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 CLK_VDO1_MERGE0_DL_ASYNC&gt;;</div><div class='add'>+			clock-names = "merge","merge_async";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VDOSYS1&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c10XXXX 0xc000 0x1000&gt;;</div><div class='add'>+			mediatek,merge-mute;</div><div class='add'>+			resets = &lt;&amp;vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		merge2: vpp-merge@1c10d000 {</div><div class='add'>+			compatible = "mediatek,mt8195-disp-merge";</div><div class='add'>+			reg = &lt;0 0x1c10d000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys1 CLK_VDO1_VPP_MERGE1&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 CLK_VDO1_MERGE1_DL_ASYNC&gt;;</div><div class='add'>+			clock-names = "merge","merge_async";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VDOSYS1&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c10XXXX 0xd000 0x1000&gt;;</div><div class='add'>+			mediatek,merge-mute;</div><div class='add'>+			resets = &lt;&amp;vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		merge3: vpp-merge@1c10e000 {</div><div class='add'>+			compatible = "mediatek,mt8195-disp-merge";</div><div class='add'>+			reg = &lt;0 0x1c10e000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys1 CLK_VDO1_VPP_MERGE2&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 CLK_VDO1_MERGE2_DL_ASYNC&gt;;</div><div class='add'>+			clock-names = "merge","merge_async";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VDOSYS1&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c10XXXX 0xe000 0x1000&gt;;</div><div class='add'>+			mediatek,merge-mute;</div><div class='add'>+			resets = &lt;&amp;vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		merge4: vpp-merge@1c10f000 {</div><div class='add'>+			compatible = "mediatek,mt8195-disp-merge";</div><div class='add'>+			reg = &lt;0 0x1c10f000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys1 CLK_VDO1_VPP_MERGE3&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 CLK_VDO1_MERGE3_DL_ASYNC&gt;;</div><div class='add'>+			clock-names = "merge","merge_async";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VDOSYS1&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c10XXXX 0xf000 0x1000&gt;;</div><div class='add'>+			mediatek,merge-mute;</div><div class='add'>+			resets = &lt;&amp;vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		merge5: vpp-merge@1c110000 {</div><div class='add'>+			compatible = "mediatek,mt8195-disp-merge";</div><div class='add'>+			reg = &lt;0 0x1c110000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys1 CLK_VDO1_VPP_MERGE4&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 CLK_VDO1_MERGE4_DL_ASYNC&gt;;</div><div class='add'>+			clock-names = "merge","merge_async";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VDOSYS1&gt;;</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c11XXXX 0x0000 0x1000&gt;;</div><div class='add'>+			mediatek,merge-fifo-en;</div><div class='add'>+			resets = &lt;&amp;vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dp_intf1: dp-intf@1c113000 {</div><div class='add'>+			compatible = "mediatek,mt8195-dp-intf";</div><div class='add'>+			reg = &lt;0 0x1c113000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VDOSYS1&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys1 CLK_VDO1_DPINTF&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 CLK_VDO1_DP_INTF0_MM&gt;,</div><div class='add'>+				 &lt;&amp;apmixedsys CLK_APMIXED_TVDPLL2&gt;;</div><div class='add'>+			clock-names = "pixel", "engine", "pll";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ethdr0: hdr-engine@1c114000 {</div><div class='add'>+			compatible = "mediatek,mt8195-disp-ethdr";</div><div class='add'>+			reg = &lt;0 0x1c114000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x1c115000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x1c117000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x1c119000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x1c11a000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x1c11b000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x1c11c000 0 0x1000&gt;;</div><div class='add'>+			reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",</div><div class='add'>+				    "vdo_be", "adl_ds";</div><div class='add'>+			mediatek,gce-client-reg = &lt;&amp;gce0 SUBSYS_1c11XXXX 0x4000 0x1000&gt;,</div><div class='add'>+						  &lt;&amp;gce0 SUBSYS_1c11XXXX 0x5000 0x1000&gt;,</div><div class='add'>+						  &lt;&amp;gce0 SUBSYS_1c11XXXX 0x7000 0x1000&gt;,</div><div class='add'>+						  &lt;&amp;gce0 SUBSYS_1c11XXXX 0x9000 0x1000&gt;,</div><div class='add'>+						  &lt;&amp;gce0 SUBSYS_1c11XXXX 0xa000 0x1000&gt;,</div><div class='add'>+						  &lt;&amp;gce0 SUBSYS_1c11XXXX 0xb000 0x1000&gt;,</div><div class='add'>+						  &lt;&amp;gce0 SUBSYS_1c11XXXX 0xc000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdosys1 CLK_VDO1_DISP_MIXER&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 CLK_VDO1_HDR_VDO_FE0&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 CLK_VDO1_HDR_VDO_FE1&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 CLK_VDO1_HDR_GFX_FE0&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 CLK_VDO1_HDR_GFX_FE1&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 CLK_VDO1_HDR_VDO_BE&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 CLK_VDO1_26M_SLOW&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_ETHDR&gt;;</div><div class='add'>+			clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",</div><div class='add'>+				      "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",</div><div class='add'>+				      "gfx_fe0_async", "gfx_fe1_async","vdo_be_async",</div><div class='add'>+				      "ethdr_top";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_VDOSYS1&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu_vpp M4U_PORT_L3_HDR_DS&gt;,</div><div class='add'>+				 &lt;&amp;iommu_vpp M4U_PORT_L3_HDR_ADL&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0&gt;; /* disp mixer */</div><div class='add'>+			resets = &lt;&amp;vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC&gt;,</div><div class='add'>+				 &lt;&amp;vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC&gt;;</div><div class='add'>+			reset-names = "vdo_fe0_async", "vdo_fe1_async", "gfx_fe0_async",</div><div class='add'>+				      "gfx_fe1_async", "vdo_be_async";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		edp_tx: edp-tx@1c500000 {</div><div class='add'>+			compatible = "mediatek,mt8195-edp-tx";</div><div class='add'>+			reg = &lt;0 0x1c500000 0 0x8000&gt;;</div><div class='add'>+			nvmem-cells = &lt;&amp;dp_calibration&gt;;</div><div class='add'>+			nvmem-cell-names = "dp_calibration_data";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_EPD_TX&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			max-linkrate-mhz = &lt;8100&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dp_tx: dp-tx@1c600000 {</div><div class='add'>+			compatible = "mediatek,mt8195-dp-tx";</div><div class='add'>+			reg = &lt;0 0x1c600000 0 0x8000&gt;;</div><div class='add'>+			nvmem-cells = &lt;&amp;dp_calibration&gt;;</div><div class='add'>+			nvmem-cell-names = "dp_calibration_data";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8195_POWER_DOMAIN_DP_TX&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0&gt;;</div><div class='add'>+			max-linkrate-mhz = &lt;8100&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	thermal_zones: thermal-zones {</div><div class='add'>+		cpu0-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_mcu MT8195_MCU_LITTLE_CPU0&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu0_alert: trip-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu0_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu0_alert&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+								&lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+								&lt;&amp;cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+								&lt;&amp;cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_mcu MT8195_MCU_LITTLE_CPU1&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu1_alert: trip-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu1_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu1_alert&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+								&lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+								&lt;&amp;cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+								&lt;&amp;cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_mcu MT8195_MCU_LITTLE_CPU2&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu2_alert: trip-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu2_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu2_alert&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+								&lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+								&lt;&amp;cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+								&lt;&amp;cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_mcu MT8195_MCU_LITTLE_CPU3&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu3_alert: trip-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu3_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu3_alert&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+								&lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+								&lt;&amp;cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+								&lt;&amp;cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu4-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_mcu MT8195_MCU_BIG_CPU0&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu4_alert: trip-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu4_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu4_alert&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+								&lt;&amp;cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+								&lt;&amp;cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+								&lt;&amp;cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu5-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_mcu MT8195_MCU_BIG_CPU1&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu5_alert: trip-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu5_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu5_alert&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+								&lt;&amp;cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+								&lt;&amp;cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+								&lt;&amp;cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu6-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_mcu MT8195_MCU_BIG_CPU2&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu6_alert: trip-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu6_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu6_alert&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+								&lt;&amp;cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+								&lt;&amp;cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+								&lt;&amp;cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu7-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_mcu MT8195_MCU_BIG_CPU3&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu7_alert: trip-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu7_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu7_alert&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+								&lt;&amp;cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+								&lt;&amp;cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+								&lt;&amp;cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vpu0-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_ap MT8195_AP_VPU0&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				vpu0_alert: trip-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				vpu0_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vpu1-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_ap MT8195_AP_VPU1&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				vpu1_alert: trip-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				vpu1_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_ap MT8195_AP_GPU0&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				gpu0_alert: trip-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpu0_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu1-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_ap MT8195_AP_GPU1&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				gpu1_alert: trip-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpu1_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdec-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_ap MT8195_AP_VDEC&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				vdec_alert: trip-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				vdec_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		img-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_ap MT8195_AP_IMG&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				img_alert: trip-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				img_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		infra-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_ap MT8195_AP_INFRA&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				infra_alert: trip-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				infra_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cam0-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_ap MT8195_AP_CAM0&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cam0_alert: trip-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cam0_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cam1-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;lvts_ap MT8195_AP_CAM1&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cam1_alert: trip-alert {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cam1_crit: trip-crit {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8196-gce.h b/arch/arm64/boot/dts/mediatek/mt8196-gce.h<br/>new file mode 100644<br/>index 000000000000..aa909e4f4964<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8196-gce.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8196-gce.h</a></div><div class='hunk'>@@ -0,0 +1,612 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2025 MediaTek Inc.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __DTS_GCE_MT8196_H</div><div class='add'>+#define __DTS_GCE_MT8196_H</div><div class='add'>+</div><div class='add'>+/* GCE Thread Priority</div><div class='add'>+ * The GCE core has multiple GCE threads, each of which can independently</div><div class='add'>+ * execute its own sequence of instructions.</div><div class='add'>+ * However, the GCE threads on the same core cannot run in parallel.</div><div class='add'>+ * Different GCE threads can determine thread priority based on the scenario,</div><div class='add'>+ * thereby serving different user needs.</div><div class='add'>+ *</div><div class='add'>+ * Low priority thread is executed when no high priority thread is active.</div><div class='add'>+ * Same priority thread is scheduled by round robin.</div><div class='add'>+ */</div><div class='add'>+#define CMDQ_THR_PRIO_LOWEST	0</div><div class='add'>+#define CMDQ_THR_PRIO_1		1</div><div class='add'>+#define CMDQ_THR_PRIO_2		2</div><div class='add'>+#define CMDQ_THR_PRIO_3		3</div><div class='add'>+#define CMDQ_THR_PRIO_4		4</div><div class='add'>+#define CMDQ_THR_PRIO_5		5</div><div class='add'>+#define CMDQ_THR_PRIO_6		6</div><div class='add'>+#define CMDQ_THR_PRIO_HIGHEST	7</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * GCE0 Hardware Event IDs</div><div class='add'>+ * Different SoCs will have varying numbers of hardware event signals,</div><div class='add'>+ * which are sent from the corresponding hardware to the GCE.</div><div class='add'>+ * Each hardware event signal corresponds to an event ID in the GCE.</div><div class='add'>+ * The CMDQ driver can use the following event ID definitions to allow</div><div class='add'>+ * the client driver to use wait and clear APIs provided by CMDQ, enabling</div><div class='add'>+ * the GCE to execute operations in the instructions for that event ID.</div><div class='add'>+ *</div><div class='add'>+ * The event IDs of GCE0 are mainly used by display hardware.</div><div class='add'>+ */</div><div class='add'>+/* CMDQ_EVENT_DISP0_STREAM_SOF0 ~ 15: 0 ~ 15 */</div><div class='add'>+#define CMDQ_EVENT_DISP0_STREAM_SOF(n)						(0 + (n))</div><div class='add'>+/* CMDQ_EVENT_DISP0_FRAME_DONE_SEL0 ~ 15: 16 ~ 31 */</div><div class='add'>+#define CMDQ_EVENT_DISP0_FRAME_DONE_SEL(n)					(16 + (n))</div><div class='add'>+#define CMDQ_EVENT_DISP0_DISP_WDMA0_TARGET_LINE_END_ENG_EVENT			32</div><div class='add'>+#define CMDQ_EVENT_DISP0_DISP_WDMA0_SW_RST_DONE_ENG_EVENT			33</div><div class='add'>+#define CMDQ_EVENT_DISP0_DISP_POSTMASK1_RST_DONE_ENG_EVENT			34</div><div class='add'>+#define CMDQ_EVENT_DISP0_DISP_POSTMASK0_RST_DONE_ENG_EVENT			35</div><div class='add'>+#define CMDQ_EVENT_DISP0_DISP_MUTEX0_TIMEOUT_ENG_EVENT				36</div><div class='add'>+/* CMDQ_EVENT_DISP0_DISP_MUTEX0_REG_UPDATE_ENG_EVENT0 ~ 15: 37 ~ 52 */</div><div class='add'>+#define CMDQ_EVENT_DISP0_DISP_MUTEX0_REG_UPDATE_ENG_EVENT(n)			(37 + (n))</div><div class='add'>+#define CMDQ_EVENT_DISP0_DISP_MUTEX0_GET_RELEASE_ENG_EVENT			53</div><div class='add'>+#define CMDQ_EVENT_DISP0_DISP_MDP_RDMA0_SW_RST_DONE_ENG_EVENT			54</div><div class='add'>+/* CMDQ_EVENT_DISP1_STREAM_SOF0 ~ 15: 55 ~ 70 */</div><div class='add'>+#define CMDQ_EVENT_DISP1_STREAM_SOF(n)						(55 + (n))</div><div class='add'>+/* CMDQ_EVENT_DISP1_FRAME_DONE_SEL0 ~ 15: 71 ~ 86 */</div><div class='add'>+#define CMDQ_EVENT_DISP1_FRAME_DONE_SEL(n)					(71 + (n))</div><div class='add'>+/* CMDQ_EVENT_DISP1_STREAM_DONE_ENG_EVENT0 ~ 15: 87 ~ 102 */</div><div class='add'>+#define CMDQ_EVENT_DISP1_STREAM_DONE_ENG_EVENT(n)				(87 + (n))</div><div class='add'>+/* CMDQ_EVENT_DISP1_REG_UPDATE_DONE_ENG_EVENT0 ~ 15: 103 ~ 118 */</div><div class='add'>+#define CMDQ_EVENT_DISP1_REG_UPDATE_DONE_ENG_EVENT(n)				(103 + (n))</div><div class='add'>+#define CMDQ_EVENT_DISP1_OCIP_SUBSYS_SRAM_ISOINT_ENG_EVENT			119</div><div class='add'>+#define CMDQ_EVENT_DISP1_DISP_WDMA4_TARGET_LINE_END_ENG_EVENT			120</div><div class='add'>+#define CMDQ_EVENT_DISP1_DISP_WDMA4_SW_RST_DONE_ENG_EVENT			121</div><div class='add'>+#define CMDQ_EVENT_DISP1_DISP_WDMA3_TARGET_LINE_END_ENG_EVENT			122</div><div class='add'>+#define CMDQ_EVENT_DISP1_DISP_WDMA3_SW_RST_DONE_ENG_EVENT			123</div><div class='add'>+#define CMDQ_EVENT_DISP1_DISP_WDMA2_TARGET_LINE_END_ENG_EVENT			124</div><div class='add'>+#define CMDQ_EVENT_DISP1_DISP_WDMA2_SW_RST_DONE_ENG_EVENT			125</div><div class='add'>+#define CMDQ_EVENT_DISP1_DISP_WDMA1_TARGET_LINE_END_ENG_EVENT			126</div><div class='add'>+#define CMDQ_EVENT_DISP1_DISP_WDMA1_SW_RST_DONE_ENG_EVENT			127</div><div class='add'>+#define CMDQ_EVENT_DISP1_DISP_MUTEX0_TIMEOUT_ENG_EVENT				128</div><div class='add'>+#define CMDQ_EVENT_DISP1_DISP_MUTEX0_GET_RLZ_ENG_EVENT				129</div><div class='add'>+#define CMDQ_EVENT_DISP1_DISP_MDP_RDMA1_SW_RST_DONE_ENG_EVENT			130</div><div class='add'>+#define CMDQ_EVENT_DISP1_DISP_GDMA0_SW_RST_DONE_ENG_EVENT			131</div><div class='add'>+#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_VSYNC_START_ENG_EVENT		132</div><div class='add'>+#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_VSYNC_END_ENG_EVENT		133</div><div class='add'>+#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_VRR_VFP_LAST_SAFE_BLANK_ENG_EVENT	134</div><div class='add'>+#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_VFP_START_ENG_EVENT		135</div><div class='add'>+#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_VFP_LAST_LINE_ENG_EVENT		136</div><div class='add'>+#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_VDE_END_ENG_EVENT			137</div><div class='add'>+#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_TRIGGER_LOOP_CLR_ENG_EVENT	138</div><div class='add'>+#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_TARGET_LINE1_ENG_EVENT		139</div><div class='add'>+#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_TARGET_LINE0_ENG_EVENT		140</div><div class='add'>+#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_EXT_TG_VSYNC_START_ENG_EVENT		141</div><div class='add'>+#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_EXT_TG_VSYNC_END_ENG_EVENT		142</div><div class='add'>+#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_EXT_TG_VDE_START_ENG_EVENT		143</div><div class='add'>+#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_EXT_TG_VDE_END_ENG_EVENT			144</div><div class='add'>+/* CMDQ_EVENT_DISP1_DISP_DSI2_ENG_EVENT0 ~ 10: 145 ~ 155 */</div><div class='add'>+#define CMDQ_EVENT_DISP1_DISP_DSI2_ENG_EVENT(n)					(145 + (n))</div><div class='add'>+/* CMDQ_EVENT_DISP1_DISP_DSI1_ENG_EVENT0 ~ 21: 156 ~ 177 */</div><div class='add'>+#define CMDQ_EVENT_DISP1_DISP_DSI1_ENG_EVENT(n)					(156 + (n))</div><div class='add'>+/* CMDQ_EVENT_DISP1_DISP_DSI0_ENG_EVENT0 ~ 10: 178 ~ 188 */</div><div class='add'>+#define CMDQ_EVENT_DISP1_DISP_DSI0_ENG_EVENT(n)					(178 + (n))</div><div class='add'>+#define CMDQ_EVENT_DISP1_DISP_DP_INTF1_VSYNC_START_ENG_EVENT			189</div><div class='add'>+#define CMDQ_EVENT_DISP1_DISP_DP_INTF1_VSYNC_END_ENG_EVENT			190</div><div class='add'>+#define CMDQ_EVENT_DISP1_DISP_DP_INTF1_VDE_START_ENG_EVENT			191</div><div class='add'>+#define CMDQ_EVENT_DISP1_DISP_DP_INTF1_VDE_END_ENG_EVENT			192</div><div class='add'>+#define CMDQ_EVENT_DISP1_DISP_DP_INTF1_TARGET_LINE_ENG_EVENT			193</div><div class='add'>+#define CMDQ_EVENT_DISP1_DISP_DP_INTF0_VSYNC_START_ENG_EVENT			194</div><div class='add'>+#define CMDQ_EVENT_DISP1_DISP_DP_INTF0_VSYNC_END_ENG_EVENT			195</div><div class='add'>+#define CMDQ_EVENT_DISP1_DISP_DP_INTF0_VDE_START_ENG_EVENT			196</div><div class='add'>+#define CMDQ_EVENT_DISP1_DISP_DP_INTF0_VDE_END_ENG_EVENT			197</div><div class='add'>+#define CMDQ_EVENT_DISP1_DISP_DP_INTF0_TARGET_LINE_ENG_EVENT			198</div><div class='add'>+/* CMDQ_EVENT_DISP1_BUF_UNDERRUN_ENG_EVENT0 ~ 10: 199 ~ 209 */</div><div class='add'>+#define CMDQ_EVENT_DISP1_BUF_UNDERRUN_ENG_EVENT(n)				(199 + (n))</div><div class='add'>+/* CMDQ_EVENT_MML0_STREAM_SOF0 ~ 15: 210 ~ 225 */</div><div class='add'>+#define CMDQ_EVENT_MML0_STREAM_SOF(n)						(210 + (n))</div><div class='add'>+/* CMDQ_EVENT_MML0_FRAME_DONE_SEL0 ~ 15: 226 ~ 241 */</div><div class='add'>+#define CMDQ_EVENT_MML0_FRAME_DONE_SEL(n)					(226 + (n))</div><div class='add'>+/* CMDQ_EVENT_MML0_REG_UPDATE_DONE_ENG_EVENT0 ~ 15: 242 ~ 257 */</div><div class='add'>+#define CMDQ_EVENT_MML0_REG_UPDATE_DONE_ENG_EVENT(n)				(242 + (n))</div><div class='add'>+#define CMDQ_EVENT_MML0_MDP_WROT2_SW_RST_DONE_ENG_EVENT				258</div><div class='add'>+#define CMDQ_EVENT_MML0_MDP_WROT1_SW_RST_DONE_ENG_EVENT				259</div><div class='add'>+#define CMDQ_EVENT_MML0_MDP_WROT0_SW_RST_DONE_ENG_EVENT				260</div><div class='add'>+#define CMDQ_EVENT_MML0_MDP_RROT0_SW_RST_DONE_ENG_EVENT				261</div><div class='add'>+#define CMDQ_EVENT_MML0_MDP_RDMA2_SW_RST_DONE_ENG_EVENT				262</div><div class='add'>+#define CMDQ_EVENT_MML0_MDP_RDMA1_SW_RST_DONE_ENG_EVENT				263</div><div class='add'>+#define CMDQ_EVENT_MML0_MDP_RDMA0_SW_RST_DONE_ENG_EVENT				264</div><div class='add'>+#define CMDQ_EVENT_MML0_MDP_MERGE0_SW_RST_DONE_ENG_EVENT			265</div><div class='add'>+#define CMDQ_EVENT_MML0_DISP_MUTEX0_TIMEOUT_ENG_EVENT				266</div><div class='add'>+#define CMDQ_EVENT_MML0_DISP_MUTEX0_GET_RLZ_ENG_EVENT				267</div><div class='add'>+/* CMDQ_EVENT_MML1_STREAM_SOF0 ~ 15: 268 ~ 283 */</div><div class='add'>+#define CMDQ_EVENT_MML1_STREAM_SOF(n)						(268 + (n))</div><div class='add'>+/* CMDQ_EVENT_MML1_FRAME_DONE_SEL0 ~ 15: 284 ~ 299 */</div><div class='add'>+#define CMDQ_EVENT_MML1_FRAME_DONE_SEL(n)					(284 + (n))</div><div class='add'>+/* CMDQ_EVENT_MML1_REG_UPDATE_DONE_ENG_EVENT0 ~ 15: 300 ~ 315 */</div><div class='add'>+#define CMDQ_EVENT_MML1_REG_UPDATE_DONE_ENG_EVENT(n)				(300 + (n))</div><div class='add'>+#define CMDQ_EVENT_MML1_MDP_WROT2_SW_RST_DONE_ENG_EVENT				316</div><div class='add'>+#define CMDQ_EVENT_MML1_MDP_WROT1_SW_RST_DONE_ENG_EVENT				317</div><div class='add'>+#define CMDQ_EVENT_MML1_MDP_WROT0_SW_RST_DONE_ENG_EVENT				318</div><div class='add'>+#define CMDQ_EVENT_MML1_MDP_RROT0_SW_RST_DONE_ENG_EVENT				319</div><div class='add'>+#define CMDQ_EVENT_MML1_MDP_RDMA2_SW_RST_DONE_ENG_EVENT				320</div><div class='add'>+#define CMDQ_EVENT_MML1_MDP_RDMA1_SW_RST_DONE_ENG_EVENT				321</div><div class='add'>+#define CMDQ_EVENT_MML1_MDP_RDMA0_SW_RST_DONE_ENG_EVENT				322</div><div class='add'>+#define CMDQ_EVENT_MML1_MDP_MERGE0_SW_RST_DONE_ENG_EVENT			323</div><div class='add'>+#define CMDQ_EVENT_MML1_DISP_MUTEX0_TIMEOUT_ENG_EVENT				324</div><div class='add'>+#define CMDQ_EVENT_MML1_DISP_MUTEX0_GET_RLZ_ENG_EVENT				325</div><div class='add'>+/* CMDQ_EVENT_OVL0_STREAM_SOF0 ~ 15: 326 ~ 341 */</div><div class='add'>+#define CMDQ_EVENT_OVL0_STREAM_SOF(n)						(326 + (n))</div><div class='add'>+/* CMDQ_EVENT_OVL0_FRAME_DONE_SEL0 ~ 15: 342 ~ 357 */</div><div class='add'>+#define CMDQ_EVENT_OVL0_FRAME_DONE_SEL(n)					(342 + (n))</div><div class='add'>+#define CMDQ_EVENT_OVL0_OVL_UFBC_WDMA0_TARGET_LINE_END_ENG_EVENT		358</div><div class='add'>+#define CMDQ_EVENT_OVL0_OVL_MUTEX0_TIMEOUT_ENG_EVENT				359</div><div class='add'>+/* CMDQ_EVENT_OVL0_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT0 ~ 15: 360 ~ 375 */</div><div class='add'>+#define CMDQ_EVENT_OVL0_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT(n)			(360 + (n))</div><div class='add'>+#define CMDQ_EVENT_OVL0_OVL_MUTEX0_GET_RELEASE_ENG_EVENT			376</div><div class='add'>+#define CMDQ_EVENT_OVL0_OVL_MDP_RDMA1_SW_RST_DONE_ENG_EVENT			377</div><div class='add'>+#define CMDQ_EVENT_OVL0_OVL_MDP_RDMA0_SW_RST_DONE_ENG_EVENT			378</div><div class='add'>+#define CMDQ_EVENT_OVL0_OVL_EXDMA9_FRAME_RESET_DONE_ENG_EVENT			379</div><div class='add'>+#define CMDQ_EVENT_OVL0_OVL_EXDMA8_FRAME_RESET_DONE_ENG_EVENT			380</div><div class='add'>+#define CMDQ_EVENT_OVL0_OVL_EXDMA7_FRAME_RESET_DONE_ENG_EVENT			381</div><div class='add'>+#define CMDQ_EVENT_OVL0_OVL_EXDMA6_FRAME_RESET_DONE_ENG_EVENT			382</div><div class='add'>+#define CMDQ_EVENT_OVL0_OVL_EXDMA5_FRAME_RESET_DONE_ENG_EVENT			383</div><div class='add'>+#define CMDQ_EVENT_OVL0_OVL_EXDMA4_FRAME_RESET_DONE_ENG_EVENT			384</div><div class='add'>+#define CMDQ_EVENT_OVL0_OVL_EXDMA3_FRAME_RESET_DONE_ENG_EVENT			385</div><div class='add'>+#define CMDQ_EVENT_OVL0_OVL_EXDMA2_FRAME_RESET_DONE_ENG_EVENT			386</div><div class='add'>+#define CMDQ_EVENT_OVL0_OVL_EXDMA1_FRAME_RESET_DONE_ENG_EVENT			387</div><div class='add'>+#define CMDQ_EVENT_OVL0_OVL_EXDMA0_FRAME_RESET_DONE_ENG_EVENT			388</div><div class='add'>+#define CMDQ_EVENT_OVL0_OVL_DISP_WDMA1_TARGET_LINE_END_ENG_EVENT		389</div><div class='add'>+#define CMDQ_EVENT_OVL0_OVL_DISP_WDMA1_SW_RST_DONE_END_ENG_EVENT		390</div><div class='add'>+#define CMDQ_EVENT_OVL0_OVL_DISP_WDMA0_TARGET_LINE_END_ENG_EVENT		391</div><div class='add'>+#define CMDQ_EVENT_OVL0_OVL_DISP_WDMA0_SW_RST_DONE_END_ENG_EVENT		392</div><div class='add'>+#define CMDQ_EVENT_OVL0_OVL_BWM0_FRAME_RESET_DONE_ENG_EVENT			393</div><div class='add'>+/* CMDQ_EVENT_OVL1_STREAM_SOF0 ~ 15: 394 ~ 409 */</div><div class='add'>+#define CMDQ_EVENT_OVL1_STREAM_SOF(n)						(394 + (n))</div><div class='add'>+/* CMDQ_EVENT_OVL1_FRAME_DONE_SEL0 ~ 15: 410 ~ 425 */</div><div class='add'>+#define CMDQ_EVENT_OVL1_FRAME_DONE_SEL(n)					(410 + (n))</div><div class='add'>+#define CMDQ_EVENT_OVL1_OVL_UFBC_WDMA0_TARGET_LINE_END_ENG_EVENT		426</div><div class='add'>+#define CMDQ_EVENT_OVL1_OVL_MUTEX0_TIMEOUT_ENG_EVENT				427</div><div class='add'>+/* CMDQ_EVENT_OVL1_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT0 ~ 15: 428 ~ 443 */</div><div class='add'>+#define CMDQ_EVENT_OVL1_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT(n)			(428 + (n))</div><div class='add'>+#define CMDQ_EVENT_OVL1_OVL_MUTEX0_GET_RELEASE_ENG_EVENT			444</div><div class='add'>+#define CMDQ_EVENT_OVL1_OVL_MDP_RDMA1_SW_RST_DONE_ENG_EVENT			445</div><div class='add'>+#define CMDQ_EVENT_OVL1_OVL_MDP_RDMA0_SW_RST_DONE_ENG_EVENT			446</div><div class='add'>+#define CMDQ_EVENT_OVL1_OVL_EXDMA9_FRAME_RESET_DONE_ENG_EVENT			447</div><div class='add'>+#define CMDQ_EVENT_OVL1_OVL_EXDMA8_FRAME_RESET_DONE_ENG_EVENT			448</div><div class='add'>+#define CMDQ_EVENT_OVL1_OVL_EXDMA7_FRAME_RESET_DONE_ENG_EVENT			449</div><div class='add'>+#define CMDQ_EVENT_OVL1_OVL_EXDMA6_FRAME_RESET_DONE_ENG_EVENT			450</div><div class='add'>+#define CMDQ_EVENT_OVL1_OVL_EXDMA5_FRAME_RESET_DONE_ENG_EVENT			451</div><div class='add'>+#define CMDQ_EVENT_OVL1_OVL_EXDMA4_FRAME_RESET_DONE_ENG_EVENT			452</div><div class='add'>+#define CMDQ_EVENT_OVL1_OVL_EXDMA3_FRAME_RESET_DONE_ENG_EVENT			453</div><div class='add'>+#define CMDQ_EVENT_OVL1_OVL_EXDMA2_FRAME_RESET_DONE_ENG_EVENT			454</div><div class='add'>+#define CMDQ_EVENT_OVL1_OVL_EXDMA1_FRAME_RESET_DONE_ENG_EVENT			455</div><div class='add'>+#define CMDQ_EVENT_OVL1_OVL_EXDMA0_FRAME_RESET_DONE_ENG_EVENT			456</div><div class='add'>+#define CMDQ_EVENT_OVL1_OVL_DISP_WDMA1_TARGET_LINE_END_ENG_EVENT		457</div><div class='add'>+#define CMDQ_EVENT_OVL1_OVL_DISP_WDMA1_SW_RST_DONE_END_ENG_EVENT		458</div><div class='add'>+#define CMDQ_EVENT_OVL1_OVL_DISP_WDMA0_TARGET_LINE_END_ENG_EVENT		459</div><div class='add'>+#define CMDQ_EVENT_OVL1_OVL_DISP_WDMA0_SW_RST_DONE_END_ENG_EVENT		460</div><div class='add'>+#define CMDQ_EVENT_OVL1_OVL_BWM0_FRAME_RESET_DONE_ENG_EVENT			461</div><div class='add'>+#define CMDQ_EVENT_DPC_DT_DONE0							462</div><div class='add'>+#define CMDQ_EVENT_DPC_DT_DONE1							463</div><div class='add'>+#define CMDQ_EVENT_DPC_DT_DONE2_0_MERGE						464</div><div class='add'>+#define CMDQ_EVENT_DPC_DT_DONE2_1_MERGE						465</div><div class='add'>+#define CMDQ_EVENT_DPC_DT_DONE2_2_MERGE						466</div><div class='add'>+#define CMDQ_EVENT_DPC_DT_DONE2_3_MERGE						467</div><div class='add'>+#define CMDQ_EVENT_DPC_DT_DONE3							468</div><div class='add'>+#define CMDQ_EVENT_DPC_DT_DONE4_MERGE						469</div><div class='add'>+#define CMDQ_EVENT_DPC_DT_DONE5							470</div><div class='add'>+#define CMDQ_EVENT_DPC_DT_DONE6_0_MERGE						471</div><div class='add'>+#define CMDQ_EVENT_DPC_DT_DONE6_1_MERGE						472</div><div class='add'>+#define CMDQ_EVENT_DPC_DT_DONE6_2_MERGE						473</div><div class='add'>+#define CMDQ_EVENT_DPC_DT_DONE6_3_MERGE						474</div><div class='add'>+#define CMDQ_EVENT_DPC_DT_DONE7							475</div><div class='add'>+#define CMDQ_EVENT_DPC_DT_DONE32_MERGE						476</div><div class='add'>+#define CMDQ_EVENT_DPC_DT_DONE33						477</div><div class='add'>+#define CMDQ_EVENT_DPC_DT_DONE34_0						478</div><div class='add'>+#define CMDQ_EVENT_DPC_DT_DONE35						479</div><div class='add'>+#define CMDQ_EVENT_DPC_DISP_SSYS_DT_ERR_ON_BEFORE_OFF				480</div><div class='add'>+#define CMDQ_EVENT_DPC_DISP_SSYS_DT_ERR_PRETE_BEFORE_ON				481</div><div class='add'>+#define CMDQ_EVENT_DPC_DISP_DVFS_DT_ERR_ON_BEFORE_OFF				482</div><div class='add'>+#define CMDQ_EVENT_DPC_DISP_DVFS_DT_ERR_PRETE_BEFORE_ON				483</div><div class='add'>+#define CMDQ_EVENT_DPC_DISP_SB_DT_ERR_ON_BEFORE_OFF				484</div><div class='add'>+#define CMDQ_EVENT_DPC_DISP_SB_DT_ERR_PRETE_BEFORE_ON				485</div><div class='add'>+#define CMDQ_EVENT_DPC_DISP_SW_CONFIG_WHEN_MTCMOS_OFF				486</div><div class='add'>+#define CMDQ_EVENT_DPC_MML_SSYS_DT_ERR_ON_BEFORE_OFF				487</div><div class='add'>+#define CMDQ_EVENT_DPC_MML_SSYS_DT_ERR_PRETE_BEFORE_ON				488</div><div class='add'>+#define CMDQ_EVENT_DPC_MML_DVFS_DT_ERR_ON_BEFORE_OFF				489</div><div class='add'>+#define CMDQ_EVENT_DPC_MML_DVFS_DT_ERR_PRETE_BEFORE_ON				490</div><div class='add'>+#define CMDQ_EVENT_DPC_MML_SB_DT_ERR_ON_BEFORE_OFF				491</div><div class='add'>+#define CMDQ_EVENT_DPC_MML_SB_DT_ERR_PRETE_BEFORE_ON				492</div><div class='add'>+#define CMDQ_EVENT_DPC_MML_SW_CONFIG_WHEN_MTCMOS_OFF				493</div><div class='add'>+/* CMDQ_EVENT_DPTX_DPTX_EVENT0 ~ 3: 494 ~ 497 */</div><div class='add'>+#define CMDQ_EVENT_DPTX_DPTX_EVENT(n)						(494 + (n))</div><div class='add'>+/* CMDQ_EVENT_EDPTX_EDPTX_EVENT0 ~ 1: 498 ~ 499 */</div><div class='add'>+#define CMDQ_EVENT_EDPTX_EDPTX_EVENT(n)						(498 + (n))</div><div class='add'>+</div><div class='add'>+#define CMDQ_EVENT_DSI0_TE_I_DSI0_TE_I						898</div><div class='add'>+#define CMDQ_EVENT_DSI1_TE_I_DSI1_TE_I						899</div><div class='add'>+#define CMDQ_EVENT_DSI2_TE_I_DSI2_TE_I						900</div><div class='add'>+/* CMDQ_EVENT_POWEREVENT_GCE_EVENT_SUBSYS_PWR_ACK0 ~ 23: 901 ~ 924 */</div><div class='add'>+#define CMDQ_EVENT_POWEREVENT_GCE_EVENT_SUBSYS_PWR_ACK(n)			(901 + (n))</div><div class='add'>+/* CMDQ_EVENT_GCE_EVENT_DPTX_GCE_EVENT_DPTX0 ~ 1: 925 ~ 926 */</div><div class='add'>+#define CMDQ_EVENT_GCE_EVENT_DPTX_GCE_EVENT_DPTX(n)				(925 + (n))</div><div class='add'>+/* CMDQ_EVENT_GCE_EVENT_DPTX_P1_GCE_EVENT_DPTX_P10 ~ 1: 927 ~ 928 */</div><div class='add'>+#define CMDQ_EVENT_GCE_EVENT_DPTX_P1_GCE_EVENT_DPTX_P1(n)			(927 + (n))</div><div class='add'>+/* CMDQ_EVENT_GCE_EVENT_EDPTX_GCE_EVENT_EDPTX0 ~ 1: 929 ~ 930 */</div><div class='add'>+#define CMDQ_EVENT_GCE_EVENT_EDPTX_GCE_EVENT_EDPTX(n)				(929 + (n))</div><div class='add'>+#define CMDQ_EVENT_DSI3_TE_I_DSI3_TE_I						931</div><div class='add'>+#define CMDQ_EVENT_SPI0_FINISH_EVENT_DSI4_TE_I					932</div><div class='add'>+#define CMDQ_EVENT_SPI0_EVENT_EVENT_DSI5_TE_I					933</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * GCE1 Hardware Event IDs</div><div class='add'>+ * Different SoCs will have varying numbers of hardware event signals,</div><div class='add'>+ * which are sent from the corresponding hardware to the GCE.</div><div class='add'>+ * Each hardware event signal corresponds to an event ID in the GCE.</div><div class='add'>+ * The CMDQ driver can use the following event ID definitions to allow</div><div class='add'>+ * the client driver to use wait and clear APIs provided by CMDQ, enabling</div><div class='add'>+ * the GCE to execute operations in the instructions for that event ID.</div><div class='add'>+ *</div><div class='add'>+ * The event IDs of GCE1 are mainly used by non-display hardware.</div><div class='add'>+ */</div><div class='add'>+#define CMDQ_EVENT_VENC3_VENC_RESERVED						0</div><div class='add'>+#define CMDQ_EVENT_VENC3_VENC_FRAME_DONE					1</div><div class='add'>+#define CMDQ_EVENT_VENC3_VENC_PAUSE_DONE					2</div><div class='add'>+#define CMDQ_EVENT_VENC3_JPGENC_DONE						3</div><div class='add'>+#define CMDQ_EVENT_VENC3_VENC_MB_DONE						4</div><div class='add'>+#define CMDQ_EVENT_VENC3_VENC_128BYTE_DONE					5</div><div class='add'>+#define CMDQ_EVENT_VENC3_JPGDEC_DONE						6</div><div class='add'>+#define CMDQ_EVENT_VENC3_JPGDEC_C1_DONE						7</div><div class='add'>+#define CMDQ_EVENT_VENC3_JPGDEC_INSUFF_DONE					8</div><div class='add'>+#define CMDQ_EVENT_VENC3_JPGDEC_C1_INSUFF_DONE					9</div><div class='add'>+#define CMDQ_EVENT_VENC3_WP_2ND_STAGE_DONE					10</div><div class='add'>+#define CMDQ_EVENT_VENC3_WP_3RD_STAGE_DONE					11</div><div class='add'>+#define CMDQ_EVENT_VENC3_PPS_HEADER_DONE					12</div><div class='add'>+#define CMDQ_EVENT_VENC3_SPS_HEADER_DONE					13</div><div class='add'>+#define CMDQ_EVENT_VENC3_VPS_HEADER_DONE					14</div><div class='add'>+#define CMDQ_EVENT_VENC3_VENC_SLICE_DONE					15</div><div class='add'>+#define CMDQ_EVENT_VENC3_VENC_SOC_SLICE_DONE					16</div><div class='add'>+#define CMDQ_EVENT_VENC3_VENC_SOC_FRAME_DONE					17</div><div class='add'>+</div><div class='add'>+#define CMDQ_EVENT_VENC2_VENC_FRAME_DONE					33</div><div class='add'>+#define CMDQ_EVENT_VENC2_VENC_PAUSE_DONE					34</div><div class='add'>+#define CMDQ_EVENT_VENC2_JPGENC_DONE						35</div><div class='add'>+#define CMDQ_EVENT_VENC2_VENC_MB_DONE						36</div><div class='add'>+#define CMDQ_EVENT_VENC2_VENC_128BYTE_DONE					37</div><div class='add'>+#define CMDQ_EVENT_VENC2_JPGDEC_DONE						38</div><div class='add'>+#define CMDQ_EVENT_VENC2_JPGDEC_C1_DONE						39</div><div class='add'>+#define CMDQ_EVENT_VENC2_JPGDEC_INSUFF_DONE					40</div><div class='add'>+#define CMDQ_EVENT_VENC2_JPGDEC_C1_INSUFF_DONE					41</div><div class='add'>+#define CMDQ_EVENT_VENC2_WP_2ND_STAGE_DONE					42</div><div class='add'>+#define CMDQ_EVENT_VENC2_WP_3RD_STAGE_DONE					43</div><div class='add'>+#define CMDQ_EVENT_VENC2_PPS_HEADER_DONE					44</div><div class='add'>+#define CMDQ_EVENT_VENC2_SPS_HEADER_DONE					45</div><div class='add'>+#define CMDQ_EVENT_VENC2_VPS_HEADER_DONE					46</div><div class='add'>+#define CMDQ_EVENT_VENC2_VENC_SLICE_DONE					47</div><div class='add'>+#define CMDQ_EVENT_VENC2_VENC_SOC_SLICE_DONE					48</div><div class='add'>+#define CMDQ_EVENT_VENC2_VENC_SOC_FRAME_DONE					49</div><div class='add'>+</div><div class='add'>+#define CMDQ_EVENT_VENC1_VENC_FRAME_DONE					65</div><div class='add'>+#define CMDQ_EVENT_VENC1_VENC_PAUSE_DONE					66</div><div class='add'>+#define CMDQ_EVENT_VENC1_JPGENC_DONE						67</div><div class='add'>+#define CMDQ_EVENT_VENC1_VENC_MB_DONE						68</div><div class='add'>+#define CMDQ_EVENT_VENC1_VENC_128BYTE_DONE					69</div><div class='add'>+#define CMDQ_EVENT_VENC1_JPGDEC_DONE						70</div><div class='add'>+#define CMDQ_EVENT_VENC1_JPGDEC_C1_DONE						71</div><div class='add'>+#define CMDQ_EVENT_VENC1_JPGDEC_INSUFF_DONE					72</div><div class='add'>+#define CMDQ_EVENT_VENC1_JPGDEC_C1_INSUFF_DONE					73</div><div class='add'>+#define CMDQ_EVENT_VENC1_WP_2ND_STAGE_DONE					74</div><div class='add'>+#define CMDQ_EVENT_VENC1_WP_3RD_STAGE_DONE					75</div><div class='add'>+#define CMDQ_EVENT_VENC1_PPS_HEADER_DONE					76</div><div class='add'>+#define CMDQ_EVENT_VENC1_SPS_HEADER_DONE					77</div><div class='add'>+#define CMDQ_EVENT_VENC1_VPS_HEADER_DONE					78</div><div class='add'>+#define CMDQ_EVENT_VENC1_VENC_SLICE_DONE					79</div><div class='add'>+#define CMDQ_EVENT_VENC1_VENC_SOC_SLICE_DONE					80</div><div class='add'>+#define CMDQ_EVENT_VENC1_VENC_SOC_FRAME_DONE					81</div><div class='add'>+</div><div class='add'>+#define CMDQ_EVENT_VDEC1_VDEC_LINE_CNT_INT					192</div><div class='add'>+#define CMDQ_EVENT_VDEC1_VDEC_INT						193</div><div class='add'>+#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_2						194</div><div class='add'>+#define CMDQ_EVENT_VDEC1_VDEC_DEC_ERR						195</div><div class='add'>+#define CMDQ_EVENT_VDEC1_VDEC_BUSY_OVERFLOW					196</div><div class='add'>+#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_5						197</div><div class='add'>+#define CMDQ_EVENT_VDEC1_VDEC_INI_FETCH_RDY					198</div><div class='add'>+#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_7						199</div><div class='add'>+#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_8						200</div><div class='add'>+#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_9						201</div><div class='add'>+#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_10						202</div><div class='add'>+#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_11						203</div><div class='add'>+</div><div class='add'>+#define CMDQ_EVENT_VDEC1_VDEC_GCE_CNT_OP_THR					207</div><div class='add'>+</div><div class='add'>+#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_32						224</div><div class='add'>+#define CMDQ_EVENT_VDEC1_VDEC_LAT_INT						225</div><div class='add'>+#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_34						226</div><div class='add'>+#define CMDQ_EVENT_VDEC1_VDEC_LAT_DEC_ERR					227</div><div class='add'>+#define CMDQ_EVENT_VDEC1_VDEC_LAT_BUSY_OVERFLOW					228</div><div class='add'>+#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_37						229</div><div class='add'>+#define CMDQ_EVENT_VDEC1_VDEC_LAT_INI_FETCH_RDY					230</div><div class='add'>+#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_39						231</div><div class='add'>+#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_40						232</div><div class='add'>+#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_41						233</div><div class='add'>+#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_42						234</div><div class='add'>+#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_43						235</div><div class='add'>+</div><div class='add'>+#define CMDQ_EVENT_VDEC1_VDEC_LAT_GCE_CNT_OP_THR				239</div><div class='add'>+</div><div class='add'>+#define CMDQ_EVENT_IMG_IMG_EVENT_0						256</div><div class='add'>+/* CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_0 ~ 5: 257 ~  262 */</div><div class='add'>+#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0(n)				(257 + (n))</div><div class='add'>+#define CMDQ_EVENT_IMG_TRAW0_DMA_ERR_EVENT					263</div><div class='add'>+#define CMDQ_EVENT_IMG_TRAW0_DUMMY_0						264</div><div class='add'>+/* CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_0 ~ 5: 265 ~ 270 */</div><div class='add'>+#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0(n)				(265 + (n))</div><div class='add'>+#define CMDQ_EVENT_IMG_TRAW1_DMA_ERR_EVENT					271</div><div class='add'>+#define CMDQ_EVENT_IMG_ADL_TILE_DONE_EVENT					272</div><div class='add'>+#define CMDQ_EVENT_IMG_ADLWR0_TILE_DONE_EVENT					273</div><div class='add'>+#define CMDQ_EVENT_IMG_ADLWR1_TILE_DONE_EVENT					274</div><div class='add'>+#define CMDQ_EVENT_IMG_IMGSYS_IPE_ME_DONE					275</div><div class='add'>+#define CMDQ_EVENT_IMG_IMGSYS_IPE_MMG_DONE					276</div><div class='add'>+/* CMDQ_EVENT_IMG_QOF_ACK_EVENT0 ~ 19: 277 ~ 296 */</div><div class='add'>+#define CMDQ_EVENT_IMG_QOF_ACK_EVENT(n)						(277 + (n))</div><div class='add'>+/* CMDQ_EVENT_IMG_QOF_ON_EVENT0 ~ 4: 297 ~ 301 */</div><div class='add'>+#define CMDQ_EVENT_IMG_QOF_ON_EVENT(n)						(297 + (n))</div><div class='add'>+/* CMDQ_EVENT_IMG_QOF_OFF_EVENT0 ~ 4: 302 ~ 306 */</div><div class='add'>+#define CMDQ_EVENT_IMG_QOF_OFF_EVENT(n)						(302 + (n))</div><div class='add'>+/* CMDQ_EVENT_IMG_QOF_SAVE_EVENT0 ~ 4: 307 ~ 311 */</div><div class='add'>+#define CMDQ_EVENT_IMG_QOF_SAVE_EVENT(n)					(307 + (n))</div><div class='add'>+/* CMDQ_EVENT_IMG_QOF_RESTORE_EVENT0 ~ 4: 312 ~ 316 */</div><div class='add'>+#define CMDQ_EVENT_IMG_QOF_RESTORE_EVENT(n)					(312 + (n))</div><div class='add'>+/* CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P20~5: 317 ~ 322 */</div><div class='add'>+#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2(n)					(317 + (n))</div><div class='add'>+#define CMDQ_EVENT_IMG_DIP_DMA_ERR_EVENT					323</div><div class='add'>+#define CMDQ_EVENT_IMG_DIP_NR_DMA_ERR_EVENT					324</div><div class='add'>+#define CMDQ_EVENT_IMG_DIP_DUMMY_0						325</div><div class='add'>+#define CMDQ_EVENT_IMG_WPE_EIS_GCE_FRAME_DONE					326</div><div class='add'>+#define CMDQ_EVENT_IMG_WPE_EIS_DONE_SYNC_OUT					327</div><div class='add'>+/* CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_P20 ~ 5: 328 ~ 333 */</div><div class='add'>+#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_P2(n)				(328 + (n))</div><div class='add'>+/* CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P20 ~ 5: 334 ~ 339 */</div><div class='add'>+#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2(n)				(334 + (n))</div><div class='add'>+#define CMDQ_EVENT_IMG_PQA_DMA_ERR_EVENT					340</div><div class='add'>+/* CMDQ_EVENT_IMG_WPE0_DUMMY0~2: 341 ~ 343 */</div><div class='add'>+#define CMDQ_EVENT_IMG_WPE0_DUMMY(n)						(341 + (n))</div><div class='add'>+#define CMDQ_EVENT_IMG_OMC_TNR_GCE_FRAME_DONE					344</div><div class='add'>+#define CMDQ_EVENT_IMG_OMC_TNR_DONE_SYNC_OUT					345</div><div class='add'>+/* CMDQ_EVENT_IMG_OMC_TNR_CQ_THR_DONE_P20 ~ 5: 346 ~ 351 */</div><div class='add'>+#define CMDQ_EVENT_IMG_OMC_TNR_CQ_THR_DONE_P2(n)				(346 + (n))</div><div class='add'>+/* CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P20 ~ 5: 352 ~ 357 */</div><div class='add'>+#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2(n)				(352 + (n))</div><div class='add'>+#define CMDQ_EVENT_IMG_PQB_DMA_ERR_EVENT					358</div><div class='add'>+/* CMDQ_EVENT_IMG_WPE1_DUMMY0 ~ 2: 359 ~ 361 */</div><div class='add'>+#define CMDQ_EVENT_IMG_WPE1_DUMMY(n)						(359 + (n))</div><div class='add'>+#define CMDQ_EVENT_IMG_WPE_LITE_GCE_FRAME_DONE					362</div><div class='add'>+#define CMDQ_EVENT_IMG_WPE_LITE_DONE_SYNC_OUT					363</div><div class='add'>+/* CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_P20 ~ 5: 364 ~ 369 */</div><div class='add'>+#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_P2(n)				(364 + (n))</div><div class='add'>+#define CMDQ_EVENT_IMG_OMC_LITE_GCE_FRAME_DONE					370</div><div class='add'>+#define CMDQ_EVENT_IMG_OMC_LITE_DONE_SYNC_OUT					371</div><div class='add'>+/* CMDQ_EVENT_IMG_OMC_LITE_CQ_THR_DONE_P20 ~ 5: 372 ~ 377 */</div><div class='add'>+#define CMDQ_EVENT_IMG_OMC_LITE_CQ_THR_DONE_P2(n)				(372 + (n))</div><div class='add'>+/* CMDQ_EVENT_IMG_WPE2_DUMMY0 ~ 2: 378 ~ 380 */</div><div class='add'>+#define CMDQ_EVENT_IMG_WPE2_DUMMY(n)						(378 + (n))</div><div class='add'>+#define CMDQ_EVENT_IMG_IMGSYS_IPE_FDVT0_DONE					381</div><div class='add'>+#define CMDQ_EVENT_IMG_IMG_EVENT_126						382</div><div class='add'>+#define CMDQ_EVENT_IMG_IMG_EVENT_127						383</div><div class='add'>+#define CMDQ_EVENT_CAM_CAM_EVENT_0						384</div><div class='add'>+#define CMDQ_EVENT_CAM_CAM_SUBA_SW_PASS1_DONE					385</div><div class='add'>+#define CMDQ_EVENT_CAM_CAM_SUBB_SW_PASS1_DONE					386</div><div class='add'>+#define CMDQ_EVENT_CAM_CAM_SUBC_SW_PASS1_DONE					387</div><div class='add'>+#define CMDQ_EVENT_CAM_CAM_SUBA_TFMR_PASS1_DONE					388</div><div class='add'>+#define CMDQ_EVENT_CAM_CAM_SUBB_TFMR_PASS1_DONE					389</div><div class='add'>+#define CMDQ_EVENT_CAM_CAM_SUBC_TFMR_PASS1_DONE					390</div><div class='add'>+/* CMDQ_EVENT_CAM_CAMSV_A_SW_PASS1_DONE0 ~ 3: 391 ~ 394 */</div><div class='add'>+#define CMDQ_EVENT_CAM_CAMSV_A_SW_PASS1_DONE(n)					(391 + (n))</div><div class='add'>+/* CMDQ_EVENT_CAM_CAMSV_B_SW_PASS1_DONE0 ~ 3: 395 ~ 398 */</div><div class='add'>+#define CMDQ_EVENT_CAM_CAMSV_B_SW_PASS1_DONE(n)					(395 + (n))</div><div class='add'>+/* CMDQ_EVENT_CAM_CAMSV_C_SW_PASS1_DONE0 ~ 3: 399 + 402 */</div><div class='add'>+#define CMDQ_EVENT_CAM_CAMSV_C_SW_PASS1_DONE(n)					(399 + (n))</div><div class='add'>+/* CMDQ_EVENT_CAM_CAMSV_D_SW_PASS1_DONE0 ~ 3: 403 ~ 406 */</div><div class='add'>+#define CMDQ_EVENT_CAM_CAMSV_D_SW_PASS1_DONE(n)					(403 + (n))</div><div class='add'>+/* CMDQ_EVENT_CAM_CAMSV_E_SW_PASS1_DONE0 ~ 3: 407 ~ 409 */</div><div class='add'>+#define CMDQ_EVENT_CAM_CAMSV_E_SW_PASS1_DONE(n)					(407 + (n))</div><div class='add'>+/* CMDQ_EVENT_CAM_CAMSV_F_SW_PASS1_DONE0 ~ 3: 411 ~ 413 */</div><div class='add'>+#define CMDQ_EVENT_CAM_CAMSV_F_SW_PASS1_DONE(n)					(411 + (n))</div><div class='add'>+#define CMDQ_EVENT_CAM_MRAW0_SW_PASS1_DONE					415</div><div class='add'>+#define CMDQ_EVENT_CAM_MRAW1_SW_PASS1_DONE					416</div><div class='add'>+#define CMDQ_EVENT_CAM_MRAW2_SW_PASS1_DONE					417</div><div class='add'>+#define CMDQ_EVENT_CAM_MRAW3_SW_PASS1_DONE					418</div><div class='add'>+#define CMDQ_EVENT_CAM_UISP_SW_PASS1_DONE					419</div><div class='add'>+#define CMDQ_EVENT_CAM_TG_MRAW0_OUT_SOF						420</div><div class='add'>+#define CMDQ_EVENT_CAM_TG_MRAW1_OUT_SOF						421</div><div class='add'>+#define CMDQ_EVENT_CAM_TG_MRAW2_OUT_SOF						422</div><div class='add'>+#define CMDQ_EVENT_CAM_TG_MRAW3_OUT_SOF						423</div><div class='add'>+#define CMDQ_EVENT_CAM_PDA0_IRQO_EVENT_DONE_D1					424</div><div class='add'>+#define CMDQ_EVENT_CAM_PDA1_IRQO_EVENT_DONE_D1					425</div><div class='add'>+#define CMDQ_EVENT_CAM_DPE_DVP_CMQ_EVENT					426</div><div class='add'>+#define CMDQ_EVENT_CAM_DPE_DVS_CMQ_EVENT					427</div><div class='add'>+#define CMDQ_EVENT_CAM_DPE_DVFG_CMQ_EVENT					428</div><div class='add'>+#define CMDQ_EVENT_CAM_CAM_EVENT_45						429</div><div class='add'>+#define CMDQ_EVENT_CAM_CAM_EVENT_46						430</div><div class='add'>+#define CMDQ_EVENT_CAM_CAM_EVENT_47						431</div><div class='add'>+#define CMDQ_EVENT_CAM_CAM_EVENT_48						432</div><div class='add'>+/* CMDQ_EVENT_CAM_CAM_SUBA_TG_INT1 ~ 4: 433 ~ 436 */</div><div class='add'>+#define CMDQ_EVENT_CAM_CAM_SUBA_TG_INT(n)					(433 + (n) - 1)</div><div class='add'>+/* CMDQ_EVENT_CAM_CAM_SUBB_TG_INT1 ~ 4: 437 ~ 440 */</div><div class='add'>+#define CMDQ_EVENT_CAM_CAM_SUBB_TG_INT(n)					(437 + (n) - 1)</div><div class='add'>+/* CMDQ_EVENT_CAM_CAM_SUBC_TG_INT1 ~ 4: 441 ~ 444 */</div><div class='add'>+#define CMDQ_EVENT_CAM_CAM_SUBC_TG_INT(n)					(441 + (n) - 1)</div><div class='add'>+#define CMDQ_EVENT_CAM_RAW_O_SOF_SUBA						445</div><div class='add'>+#define CMDQ_EVENT_CAM_RAW_O_SOF_SUBB						446</div><div class='add'>+#define CMDQ_EVENT_CAM_RAW_O_SOF_SUBC						447</div><div class='add'>+#define CMDQ_EVENT_CAM_TFMR_RAW_O_SOF_SUBA					448</div><div class='add'>+#define CMDQ_EVENT_CAM_TFMR_RAW_O_SOF_SUBB					449</div><div class='add'>+#define CMDQ_EVENT_CAM_TFMR_RAW_O_SOF_SUBC					450</div><div class='add'>+#define CMDQ_EVENT_CAM_RAW_SEL_SOF_UISP						451</div><div class='add'>+#define CMDQ_EVENT_CAM_CAM_SUBA_RING_BUFFER_OVERFLOW_INT_IN			452</div><div class='add'>+#define CMDQ_EVENT_CAM_CAM_SUBB_RING_BUFFER_OVERFLOW_INT_IN			453</div><div class='add'>+#define CMDQ_EVENT_CAM_CAM_SUBC_RING_BUFFER_OVERFLOW_INT_IN			454</div><div class='add'>+#define CMDQ_EVENT_CAM_CAM_EVENT_71						455</div><div class='add'>+#define CMDQ_EVENT_CAM_ADL_WR_FRAME_DONE					456</div><div class='add'>+#define CMDQ_EVENT_CAM_ADL_RD_FRAME_DONE					457</div><div class='add'>+#define CMDQ_EVENT_CAM_QOF_RAWA_POWER_ON_EVENT					458</div><div class='add'>+#define CMDQ_EVENT_CAM_QOF_RAWB_POWER_ON_EVENT					459</div><div class='add'>+#define CMDQ_EVENT_CAM_QOF_RAWC_POWER_ON_EVENT					460</div><div class='add'>+#define CMDQ_EVENT_CAM_QOF_RAWA_POWER_OFF_EVENT					461</div><div class='add'>+#define CMDQ_EVENT_CAM_QOF_RAWB_POWER_OFF_EVENT					462</div><div class='add'>+#define CMDQ_EVENT_CAM_QOF_RAWC_POWER_OFF_EVENT					463</div><div class='add'>+#define CMDQ_EVENT_CAM_QOF_RAWA_SAVE_EVENT					464</div><div class='add'>+#define CMDQ_EVENT_CAM_QOF_RAWB_SAVE_EVENT					465</div><div class='add'>+#define CMDQ_EVENT_CAM_QOF_RAWC_SAVE_EVENT					466</div><div class='add'>+#define CMDQ_EVENT_CAM_QOF_RAWA_RESTORE_EVENT					467</div><div class='add'>+#define CMDQ_EVENT_CAM_QOF_RAWB_RESTORE_EVENT					468</div><div class='add'>+#define CMDQ_EVENT_CAM_QOF_RAWC_RESTORE_EVENT					469</div><div class='add'>+/* CMDQ_EVENT_CAM_QOF_CAM_EVENT0 ~ 11: 470 ~ 481 */</div><div class='add'>+#define CMDQ_EVENT_CAM_QOF_CAM_EVENT(n)						(470 + (n))</div><div class='add'>+/* CMDQ_EVENT_CAM_SENINF_CFG_DONE_EVENT0 ~ 11: 482 ~ 495 */</div><div class='add'>+#define CMDQ_EVENT_CAM_SENINF_CFG_DONE_EVENT(n)					(482 + (n))</div><div class='add'>+#define CMDQ_EVENT_CAM_CCU0_TO_GCE_NON_SEC_IRQ					496</div><div class='add'>+#define CMDQ_EVENT_CAM_CCU0_TO_GCE_SEC_IRQ					497</div><div class='add'>+#define CMDQ_EVENT_CAM_CCU0_TO_GCE_VM_IRQ					498</div><div class='add'>+#define CMDQ_EVENT_CAM_CCU0_TO_GCE_EXCH_VM_IRQ					499</div><div class='add'>+#define CMDQ_EVENT_CAM_CCU1_TO_GCE_NON_SEC_IRQ					500</div><div class='add'>+#define CMDQ_EVENT_CAM_CCU1_TO_GCE_SEC_IRQ					501</div><div class='add'>+#define CMDQ_EVENT_CAM_CCU1_TO_GCE_VM_IRQ					502</div><div class='add'>+#define CMDQ_EVENT_CAM_CCU1_TO_GCE_EXCH_VM_IRQ					503</div><div class='add'>+/* CMDQ_EVENT_CAM_I2C_CH2_EVENT0 ~ 4: 504 ~ 509 */</div><div class='add'>+#define CMDQ_EVENT_CAM_I2C_CH2_EVENT(n)						(504 + (n))</div><div class='add'>+#define CMDQ_EVENT_CAM_CAM_EVENT_125						509</div><div class='add'>+#define CMDQ_EVENT_CAM_CAM_EVENT_126						510</div><div class='add'>+#define CMDQ_EVENT_CAM_CAM_EVENT_127						511</div><div class='add'>+</div><div class='add'>+#define CMDQ_EVENT_SMI_EVENT_MMINFRA_SMI_MMSRAM_COMM_SMIASSER			898</div><div class='add'>+#define CMDQ_EVENT_SMI_EVENT_MMINFRA_SMI_MDP_COMM_SMIASSER			899</div><div class='add'>+#define CMDQ_EVENT_SMI_EVENT_MMINFRA_SMI_DISP_COMM_SMIASSER			900</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * GCE Software Tokens</div><div class='add'>+ * Apart from the event IDs that are already bound to hardware event signals,</div><div class='add'>+ * the remaining event IDs can be used as software tokens.</div><div class='add'>+ * This allows the client driver to name and operate them independently,</div><div class='add'>+ * and their usage is the same as that of hardware events.</div><div class='add'>+ */</div><div class='add'>+/* Begin of GCE0 software token */</div><div class='add'>+/* Config thread notify trigger thread */</div><div class='add'>+#define CMDQ_SYNC_TOKEN_CONFIG_DIRTY			640</div><div class='add'>+/* Trigger thread notify config thread */</div><div class='add'>+#define CMDQ_SYNC_TOKEN_STREAM_EOF			641</div><div class='add'>+/* Block Trigger thread until the ESD check finishes */</div><div class='add'>+#define CMDQ_SYNC_TOKEN_ESD_EOF				642</div><div class='add'>+#define CMDQ_SYNC_TOKEN_STREAM_BLOCK			643</div><div class='add'>+/* Check CABC setup finish */</div><div class='add'>+#define CMDQ_SYNC_TOKEN_CABC_EOF			644</div><div class='add'>+/* VFP period token for Msync */</div><div class='add'>+#define CMDQ_SYNC_TOKEN_VFP_PERIOD			645</div><div class='add'>+/* Software sync token for dual display */</div><div class='add'>+#define CMDQ_SYNC_TOKEN_CONFIG_DIRTY_1			694</div><div class='add'>+#define CMDQ_SYNC_TOKEN_STREAM_EOF_1			695</div><div class='add'>+#define CMDQ_SYNC_TOKEN_ESD_EOF_1			696</div><div class='add'>+#define CMDQ_SYNC_TOKEN_STREAM_BLOCK_1			697</div><div class='add'>+#define CMDQ_SYNC_TOKEN_CABC_EOF_1			698</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * GPR access tokens (for HW register backup)</div><div class='add'>+ * There are 15 32-bit GPR, form 3 GPR as a set</div><div class='add'>+ * (64-bit for address, 32-bit for value)</div><div class='add'>+ *</div><div class='add'>+ * CMDQ_SYNC_TOKEN_GPR_SET0 ~ 4: 700 ~ 704</div><div class='add'>+ */</div><div class='add'>+#define CMDQ_SYNC_TOKEN_GPR_SET(n)			(700 + (n))</div><div class='add'>+#define CMDQ_SYNC_TOKEN_TE_0				705</div><div class='add'>+#define CMDQ_SYNC_TOKEN_PREFETCH_TE_0			706</div><div class='add'>+#define CMDQ_SYNC_TOKEN_VIDLE_POWER_ON			707</div><div class='add'>+#define CMDQ_SYNC_TOKEN_CHECK_TRIGGER_MERGE		708</div><div class='add'>+</div><div class='add'>+/* Resource lock event to control resource in GCE thread */</div><div class='add'>+#define CMDQ_SYNC_RESOURCE_WROT0			710</div><div class='add'>+#define CMDQ_SYNC_RESOURCE_WROT1			711</div><div class='add'>+/* Hardware TRACE software token */</div><div class='add'>+#define CMDQ_SYNC_TOKEN_HW_TRACE_WAIT			712</div><div class='add'>+#define CMDQ_SYNC_TOKEN_HW_TRACE_LOCK			713</div><div class='add'>+/* Software sync token for dual display */</div><div class='add'>+#define CMDQ_SYNC_TOKEN_CONFIG_DIRTY_3			714</div><div class='add'>+#define CMDQ_SYNC_TOKEN_STREAM_EOF_3			715</div><div class='add'>+#define CMDQ_SYNC_TOKEN_ESD_EOF_3			716</div><div class='add'>+#define CMDQ_SYNC_TOKEN_STREAM_BLOCK_3			717</div><div class='add'>+#define CMDQ_SYNC_TOKEN_CABC_EOF_3			718</div><div class='add'>+/* End of GCE0 software token */</div><div class='add'>+</div><div class='add'>+/* Begin of GCE1 software token */</div><div class='add'>+/* CMDQ_SYNC_TOKEN_IMGSYS_POOL0 ~ 300: 512 ~ 812 */</div><div class='add'>+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL(n)			(512 + (n))</div><div class='add'>+/* ISP software token */</div><div class='add'>+#define CMDQ_SYNC_TOKEN_IMGSYS_WPE_EIS			813</div><div class='add'>+#define CMDQ_SYNC_TOKEN_IMGSYS_OMC_TNR			814</div><div class='add'>+#define CMDQ_SYNC_TOKEN_IMGSYS_WPE_LITE			815</div><div class='add'>+#define CMDQ_SYNC_TOKEN_IMGSYS_TRAW			816</div><div class='add'>+#define CMDQ_SYNC_TOKEN_IMGSYS_LTRAW			817</div><div class='add'>+#define CMDQ_SYNC_TOKEN_IMGSYS_XTRAW			818</div><div class='add'>+#define CMDQ_SYNC_TOKEN_IMGSYS_DIP			819</div><div class='add'>+#define CMDQ_SYNC_TOKEN_IMGSYS_PQDIP_A			820</div><div class='add'>+#define CMDQ_SYNC_TOKEN_IMGSYS_PQDIP_B			821</div><div class='add'>+#define CMDQ_SYNC_TOKEN_IPESYS_ME			822</div><div class='add'>+#define CMDQ_SYNC_TOKEN_APUSYS_APU			823</div><div class='add'>+#define CMDQ_SYNC_TOKEN_IMGSYS_VSS_TRAW			824</div><div class='add'>+#define CMDQ_SYNC_TOKEN_IMGSYS_VSS_LTRAW		825</div><div class='add'>+#define CMDQ_SYNC_TOKEN_IMGSYS_VSS_XTRAW		826</div><div class='add'>+#define CMDQ_SYNC_TOKEN_IMGSYS_VSS_DIP			827</div><div class='add'>+#define CMDQ_SYNC_TOKEN_IMGSYS_OMC_LITE			828</div><div class='add'>+/* IMG software token for QoS */</div><div class='add'>+#define CMDQ_SYNC_TOKEN_IMGSYS_QOS_LOCK			829</div><div class='add'>+/* IMG software token for Qof */</div><div class='add'>+#define CMDQ_SYNC_TOKEN_DIP_POWER_CTRL			830</div><div class='add'>+#define CMDQ_SYNC_TOKEN_DIP_TRIG_PWR_ON			831</div><div class='add'>+#define CMDQ_SYNC_TOKEN_DIP_PWR_ON			832</div><div class='add'>+#define CMDQ_SYNC_TOKEN_DIP_TRIG_PWR_OFF		833</div><div class='add'>+#define CMDQ_SYNC_TOKEN_DIP_PWR_OFF			834</div><div class='add'>+#define CMDQ_SYNC_TOKEN_DIP_PWR_HAND_SHAKE		835</div><div class='add'>+#define CMDQ_SYNC_TOKEN_TRAW_POWER_CTRL			836</div><div class='add'>+#define CMDQ_SYNC_TOKEN_TRAW_TRIG_PWR_ON		837</div><div class='add'>+#define CMDQ_SYNC_TOKEN_TRAW_PWR_ON			838</div><div class='add'>+#define CMDQ_SYNC_TOKEN_TRAW_TRIG_PWR_OFF		839</div><div class='add'>+#define CMDQ_SYNC_TOKEN_TRAW_PWR_OFF			840</div><div class='add'>+#define CMDQ_SYNC_TOKEN_TRAW_PWR_HAND_SHAKE		841</div><div class='add'>+/* End of GCE1 software token */</div><div class='add'>+</div><div class='add'>+/* Begin of common software token */</div><div class='add'>+/*</div><div class='add'>+ * Notify normal CMDQ there are some secure task done</div><div class='add'>+ * MUST NOT CHANGE, this token sync with secure world</div><div class='add'>+ */</div><div class='add'>+#define CMDQ_SYNC_SECURE_THR_EOF			940</div><div class='add'>+/* CMDQ use software token */</div><div class='add'>+#define CMDQ_SYNC_TOKEN_USER_0				941</div><div class='add'>+#define CMDQ_SYNC_TOKEN_USER_1				942</div><div class='add'>+#define CMDQ_SYNC_TOKEN_POLL_MONITOR			943</div><div class='add'>+#define CMDQ_SYNC_TOKEN_TPR_LOCK			942</div><div class='add'>+/* TZMP software token */</div><div class='add'>+#define CMDQ_SYNC_TOKEN_TZMP_DISP_WAIT			943</div><div class='add'>+#define CMDQ_SYNC_TOKEN_TZMP_DISP_SET			944</div><div class='add'>+#define CMDQ_SYNC_TOKEN_TZMP_ISP_WAIT			945</div><div class='add'>+#define CMDQ_SYNC_TOKEN_TZMP_ISP_SET			946</div><div class='add'>+#define CMDQ_SYNC_TOKEN_TZMP_AIE_WAIT			947</div><div class='add'>+#define CMDQ_SYNC_TOKEN_TZMP_AIE_SET			948</div><div class='add'>+#define CMDQ_SYNC_TOKEN_TZMP_ADL_WAIT			949</div><div class='add'>+#define CMDQ_SYNC_TOKEN_TZMP_ADL_SET			950</div><div class='add'>+/* PREBUILT software token */</div><div class='add'>+#define CMDQ_SYNC_TOKEN_PREBUILT_MDP_LOCK		951</div><div class='add'>+#define CMDQ_SYNC_TOKEN_PREBUILT_MML_LOCK		952</div><div class='add'>+#define CMDQ_SYNC_TOKEN_PREBUILT_VFMT_LOCK		953</div><div class='add'>+#define CMDQ_SYNC_TOKEN_PREBUILT_DISP_LOCK		954</div><div class='add'>+#define CMDQ_SYNC_TOKEN_DISP_VA_START			955</div><div class='add'>+#define CMDQ_SYNC_TOKEN_DISP_VA_END			956</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Event for GPR timer, used in sleep and poll with timeout</div><div class='add'>+ *</div><div class='add'>+ * CMDQ_TOKEN_GPR_TIMER_R0~15: 994 ~ 1009</div><div class='add'>+ */</div><div class='add'>+#define CMDQ_TOKEN_GPR_TIMER_R(n)			(994 + (n))</div><div class='add'>+/* End of common software token */</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8196-pinfunc.h b/arch/arm64/boot/dts/mediatek/mt8196-pinfunc.h<br/>new file mode 100644<br/>index 000000000000..99535a6d5cba<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8196-pinfunc.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8196-pinfunc.h</a></div><div class='hunk'>@@ -0,0 +1,1574 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2025 MediaTek Inc.</div><div class='add'>+ * Author: Guodong Liu &lt;guodong.liu@mediatek.com&gt;</div><div class='add'>+ *         Lei Xue &lt;lei.xue@mediatek.com&gt;</div><div class='add'>+ *         Cathy Xu &lt;ot_cathy.xu@mediatek.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __MT8196_PINFUNC_H</div><div class='add'>+#define __MT8196_PINFUNC_H</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/pinctrl/mt65xx.h&gt;</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)</div><div class='add'>+#define PINMUX_GPIO0__FUNC_DMIC1_CLK (MTK_PIN_NO(0) | 1)</div><div class='add'>+#define PINMUX_GPIO0__FUNC_SPI3_A_MO (MTK_PIN_NO(0) | 3)</div><div class='add'>+#define PINMUX_GPIO0__FUNC_FMI2S_B_LRCK (MTK_PIN_NO(0) | 4)</div><div class='add'>+#define PINMUX_GPIO0__FUNC_SCP_DMIC1_CLK (MTK_PIN_NO(0) | 5)</div><div class='add'>+#define PINMUX_GPIO0__FUNC_TP_GPIO14_AO (MTK_PIN_NO(0) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)</div><div class='add'>+#define PINMUX_GPIO1__FUNC_DMIC1_DAT (MTK_PIN_NO(1) | 1)</div><div class='add'>+#define PINMUX_GPIO1__FUNC_SRCLKENAI1 (MTK_PIN_NO(1) | 2)</div><div class='add'>+#define PINMUX_GPIO1__FUNC_SPI3_A_MI (MTK_PIN_NO(1) | 3)</div><div class='add'>+#define PINMUX_GPIO1__FUNC_FMI2S_B_DI (MTK_PIN_NO(1) | 4)</div><div class='add'>+#define PINMUX_GPIO1__FUNC_SCP_DMIC1_DAT (MTK_PIN_NO(1) | 5)</div><div class='add'>+#define PINMUX_GPIO1__FUNC_TP_GPIO15_AO (MTK_PIN_NO(1) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)</div><div class='add'>+#define PINMUX_GPIO2__FUNC_PWM_VLP (MTK_PIN_NO(2) | 1)</div><div class='add'>+#define PINMUX_GPIO2__FUNC_DSI_HSYNC (MTK_PIN_NO(2) | 2)</div><div class='add'>+#define PINMUX_GPIO2__FUNC_RG_TSFDC_LDO_EN (MTK_PIN_NO(2) | 5)</div><div class='add'>+#define PINMUX_GPIO2__FUNC_TP_GPIO8_AO (MTK_PIN_NO(2) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)</div><div class='add'>+#define PINMUX_GPIO3__FUNC_MD_INT0 (MTK_PIN_NO(3) | 1)</div><div class='add'>+#define PINMUX_GPIO3__FUNC_DSI1_HSYNC (MTK_PIN_NO(3) | 2)</div><div class='add'>+#define PINMUX_GPIO3__FUNC_DA_TSFDC_LDO_MODE (MTK_PIN_NO(3) | 5)</div><div class='add'>+#define PINMUX_GPIO3__FUNC_TP_GPIO9_AO (MTK_PIN_NO(3) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)</div><div class='add'>+#define PINMUX_GPIO4__FUNC_DISP_PWM1 (MTK_PIN_NO(4) | 1)</div><div class='add'>+#define PINMUX_GPIO4__FUNC_MD32_0_GPIO0 (MTK_PIN_NO(4) | 2)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)</div><div class='add'>+#define PINMUX_GPIO5__FUNC_LCM1_RST (MTK_PIN_NO(5) | 1)</div><div class='add'>+#define PINMUX_GPIO5__FUNC_SPI7_A_CLK (MTK_PIN_NO(5) | 2)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)</div><div class='add'>+#define PINMUX_GPIO6__FUNC_DSI1_TE (MTK_PIN_NO(6) | 1)</div><div class='add'>+#define PINMUX_GPIO6__FUNC_SPI7_A_CSB (MTK_PIN_NO(6) | 2)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)</div><div class='add'>+#define PINMUX_GPIO7__FUNC_SPI7_A_MO (MTK_PIN_NO(7) | 2)</div><div class='add'>+#define PINMUX_GPIO7__FUNC_GPS_PPS0 (MTK_PIN_NO(7) | 3)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)</div><div class='add'>+#define PINMUX_GPIO8__FUNC_SPI7_A_MI (MTK_PIN_NO(8) | 2)</div><div class='add'>+#define PINMUX_GPIO8__FUNC_EDP_TX_HPD (MTK_PIN_NO(8) | 3)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)</div><div class='add'>+#define PINMUX_GPIO9__FUNC_I2SIN1_LRCK (MTK_PIN_NO(9) | 3)</div><div class='add'>+#define PINMUX_GPIO9__FUNC_RG_TSFDC_LDO_REFSEL0 (MTK_PIN_NO(9) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)</div><div class='add'>+#define PINMUX_GPIO10__FUNC_I2SOUT1_DO (MTK_PIN_NO(10) | 3)</div><div class='add'>+#define PINMUX_GPIO10__FUNC_RG_TSFDC_LDO_REFSEL1 (MTK_PIN_NO(10) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)</div><div class='add'>+#define PINMUX_GPIO11__FUNC_FMI2S_B_BCK (MTK_PIN_NO(11) | 4)</div><div class='add'>+#define PINMUX_GPIO11__FUNC_DBG_MON_A30 (MTK_PIN_NO(11) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)</div><div class='add'>+#define PINMUX_GPIO12__FUNC_I2SIN1_DI_B (MTK_PIN_NO(12) | 3)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)</div><div class='add'>+#define PINMUX_GPIO13__FUNC_EDP_TX_HPD (MTK_PIN_NO(13) | 1)</div><div class='add'>+#define PINMUX_GPIO13__FUNC_GPS_PPS1 (MTK_PIN_NO(13) | 2)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)</div><div class='add'>+#define PINMUX_GPIO14__FUNC_SRCLKENA2 (MTK_PIN_NO(14) | 1)</div><div class='add'>+#define PINMUX_GPIO14__FUNC_DSI2_TE (MTK_PIN_NO(14) | 2)</div><div class='add'>+#define PINMUX_GPIO14__FUNC_SPMI_P_TRIG_FLAG (MTK_PIN_NO(14) | 3)</div><div class='add'>+#define PINMUX_GPIO14__FUNC_MD_INT3 (MTK_PIN_NO(14) | 5)</div><div class='add'>+#define PINMUX_GPIO14__FUNC_TP_GPIO8_AO (MTK_PIN_NO(14) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)</div><div class='add'>+#define PINMUX_GPIO15__FUNC_SRCLKENAI0 (MTK_PIN_NO(15) | 1)</div><div class='add'>+#define PINMUX_GPIO15__FUNC_SPMI_M_TRIG_FLAG (MTK_PIN_NO(15) | 2)</div><div class='add'>+#define PINMUX_GPIO15__FUNC_UCTS0 (MTK_PIN_NO(15) | 3)</div><div class='add'>+#define PINMUX_GPIO15__FUNC_MD_INT4 (MTK_PIN_NO(15) | 4)</div><div class='add'>+#define PINMUX_GPIO15__FUNC_I2SOUT2_DO (MTK_PIN_NO(15) | 5)</div><div class='add'>+#define PINMUX_GPIO15__FUNC_TP_GPIO9_AO (MTK_PIN_NO(15) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0)</div><div class='add'>+#define PINMUX_GPIO16__FUNC_SRCLKENAI1 (MTK_PIN_NO(16) | 1)</div><div class='add'>+#define PINMUX_GPIO16__FUNC_DP_TX_HPD (MTK_PIN_NO(16) | 2)</div><div class='add'>+#define PINMUX_GPIO16__FUNC_URTS0 (MTK_PIN_NO(16) | 3)</div><div class='add'>+#define PINMUX_GPIO16__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(16) | 4)</div><div class='add'>+#define PINMUX_GPIO16__FUNC_KPROW2 (MTK_PIN_NO(16) | 5)</div><div class='add'>+#define PINMUX_GPIO16__FUNC_TP_GPIO10_AO (MTK_PIN_NO(16) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0)</div><div class='add'>+#define PINMUX_GPIO17__FUNC_MD_INT0 (MTK_PIN_NO(17) | 1)</div><div class='add'>+#define PINMUX_GPIO17__FUNC_DP_OC_EN (MTK_PIN_NO(17) | 2)</div><div class='add'>+#define PINMUX_GPIO17__FUNC_UCTS1 (MTK_PIN_NO(17) | 3)</div><div class='add'>+#define PINMUX_GPIO17__FUNC_MD_NTN_URXD1 (MTK_PIN_NO(17) | 4)</div><div class='add'>+#define PINMUX_GPIO17__FUNC_KPCOL2 (MTK_PIN_NO(17) | 5)</div><div class='add'>+#define PINMUX_GPIO17__FUNC_TP_GPIO11_AO (MTK_PIN_NO(17) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)</div><div class='add'>+#define PINMUX_GPIO18__FUNC_DMIC1_CLK (MTK_PIN_NO(18) | 1)</div><div class='add'>+#define PINMUX_GPIO18__FUNC_DP_RAUX_SBU1 (MTK_PIN_NO(18) | 2)</div><div class='add'>+#define PINMUX_GPIO18__FUNC_URTS1 (MTK_PIN_NO(18) | 3)</div><div class='add'>+#define PINMUX_GPIO18__FUNC_MD_NTN_UTXD1 (MTK_PIN_NO(18) | 4)</div><div class='add'>+#define PINMUX_GPIO18__FUNC_I2SIN2_DI (MTK_PIN_NO(18) | 5)</div><div class='add'>+#define PINMUX_GPIO18__FUNC_TP_UTXD_GNSS_VLP (MTK_PIN_NO(18) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)</div><div class='add'>+#define PINMUX_GPIO19__FUNC_DMIC1_DAT (MTK_PIN_NO(19) | 1)</div><div class='add'>+#define PINMUX_GPIO19__FUNC_DP_RAUX_SBU2 (MTK_PIN_NO(19) | 2)</div><div class='add'>+#define PINMUX_GPIO19__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(19) | 3)</div><div class='add'>+#define PINMUX_GPIO19__FUNC_CLKM3_A (MTK_PIN_NO(19) | 4)</div><div class='add'>+#define PINMUX_GPIO19__FUNC_I2SIN2_BCK (MTK_PIN_NO(19) | 5)</div><div class='add'>+#define PINMUX_GPIO19__FUNC_TP_URXD_GNSS_VLP (MTK_PIN_NO(19) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)</div><div class='add'>+#define PINMUX_GPIO20__FUNC_IDDIG (MTK_PIN_NO(20) | 1)</div><div class='add'>+#define PINMUX_GPIO20__FUNC_LCM2_RST (MTK_PIN_NO(20) | 2)</div><div class='add'>+#define PINMUX_GPIO20__FUNC_GPS_PPS1 (MTK_PIN_NO(20) | 3)</div><div class='add'>+#define PINMUX_GPIO20__FUNC_CLKM2_A (MTK_PIN_NO(20) | 4)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)</div><div class='add'>+#define PINMUX_GPIO21__FUNC_BPI_BUS11 (MTK_PIN_NO(21) | 1)</div><div class='add'>+#define PINMUX_GPIO21__FUNC_PCIE_PERSTN_1P (MTK_PIN_NO(21) | 2)</div><div class='add'>+#define PINMUX_GPIO21__FUNC_DSI1_TE (MTK_PIN_NO(21) | 3)</div><div class='add'>+#define PINMUX_GPIO21__FUNC_DMIC_CLK (MTK_PIN_NO(21) | 4)</div><div class='add'>+#define PINMUX_GPIO21__FUNC_SCP_DMIC_CLK (MTK_PIN_NO(21) | 5)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)</div><div class='add'>+#define PINMUX_GPIO22__FUNC_BPI_BUS12 (MTK_PIN_NO(22) | 1)</div><div class='add'>+#define PINMUX_GPIO22__FUNC_PCIE_CLKREQN_1P (MTK_PIN_NO(22) | 2)</div><div class='add'>+#define PINMUX_GPIO22__FUNC_DSI2_TE (MTK_PIN_NO(22) | 3)</div><div class='add'>+#define PINMUX_GPIO22__FUNC_DMIC_DAT (MTK_PIN_NO(22) | 4)</div><div class='add'>+#define PINMUX_GPIO22__FUNC_SCP_DMIC_DAT (MTK_PIN_NO(22) | 5)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)</div><div class='add'>+#define PINMUX_GPIO23__FUNC_BPI_BUS13 (MTK_PIN_NO(23) | 1)</div><div class='add'>+#define PINMUX_GPIO23__FUNC_PCIE_WAKEN_1P (MTK_PIN_NO(23) | 2)</div><div class='add'>+#define PINMUX_GPIO23__FUNC_DSI3_TE (MTK_PIN_NO(23) | 3)</div><div class='add'>+#define PINMUX_GPIO23__FUNC_DMIC1_CLK (MTK_PIN_NO(23) | 4)</div><div class='add'>+#define PINMUX_GPIO23__FUNC_SCP_DMIC1_CLK (MTK_PIN_NO(23) | 5)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)</div><div class='add'>+#define PINMUX_GPIO24__FUNC_BPI_BUS14 (MTK_PIN_NO(24) | 1)</div><div class='add'>+#define PINMUX_GPIO24__FUNC_LCM1_RST (MTK_PIN_NO(24) | 2)</div><div class='add'>+#define PINMUX_GPIO24__FUNC_AGPS_SYNC (MTK_PIN_NO(24) | 3)</div><div class='add'>+#define PINMUX_GPIO24__FUNC_DMIC1_DAT (MTK_PIN_NO(24) | 4)</div><div class='add'>+#define PINMUX_GPIO24__FUNC_SCP_DMIC1_DAT (MTK_PIN_NO(24) | 5)</div><div class='add'>+#define PINMUX_GPIO24__FUNC_DISP_PWM1 (MTK_PIN_NO(24) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)</div><div class='add'>+#define PINMUX_GPIO25__FUNC_BPI_BUS15 (MTK_PIN_NO(25) | 1)</div><div class='add'>+#define PINMUX_GPIO25__FUNC_LCM2_RST (MTK_PIN_NO(25) | 2)</div><div class='add'>+#define PINMUX_GPIO25__FUNC_SRCLKENAI1 (MTK_PIN_NO(25) | 3)</div><div class='add'>+#define PINMUX_GPIO25__FUNC_DMIC2_CLK (MTK_PIN_NO(25) | 4)</div><div class='add'>+#define PINMUX_GPIO25__FUNC_DISP_PWM2 (MTK_PIN_NO(25) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)</div><div class='add'>+#define PINMUX_GPIO26__FUNC_BPI_BUS16 (MTK_PIN_NO(26) | 1)</div><div class='add'>+#define PINMUX_GPIO26__FUNC_LCM3_RST (MTK_PIN_NO(26) | 2)</div><div class='add'>+#define PINMUX_GPIO26__FUNC_DMIC2_DAT (MTK_PIN_NO(26) | 4)</div><div class='add'>+#define PINMUX_GPIO26__FUNC_DISP_PWM3 (MTK_PIN_NO(26) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)</div><div class='add'>+#define PINMUX_GPIO27__FUNC_BPI_BUS17 (MTK_PIN_NO(27) | 1)</div><div class='add'>+#define PINMUX_GPIO27__FUNC_UTXD4 (MTK_PIN_NO(27) | 2)</div><div class='add'>+#define PINMUX_GPIO27__FUNC_DISP_PWM4 (MTK_PIN_NO(27) | 6)</div><div class='add'>+#define PINMUX_GPIO27__FUNC_DBG_MON_A20 (MTK_PIN_NO(27) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)</div><div class='add'>+#define PINMUX_GPIO28__FUNC_BPI_BUS18 (MTK_PIN_NO(28) | 1)</div><div class='add'>+#define PINMUX_GPIO28__FUNC_URXD4 (MTK_PIN_NO(28) | 2)</div><div class='add'>+#define PINMUX_GPIO28__FUNC_SPI2_A_MI (MTK_PIN_NO(28) | 3)</div><div class='add'>+#define PINMUX_GPIO28__FUNC_CLKM0_A (MTK_PIN_NO(28) | 4)</div><div class='add'>+#define PINMUX_GPIO28__FUNC_DBG_MON_A21 (MTK_PIN_NO(28) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)</div><div class='add'>+#define PINMUX_GPIO29__FUNC_BPI_BUS19 (MTK_PIN_NO(29) | 1)</div><div class='add'>+#define PINMUX_GPIO29__FUNC_MD_NTN_UTXD1 (MTK_PIN_NO(29) | 2)</div><div class='add'>+#define PINMUX_GPIO29__FUNC_SPI2_A_MO (MTK_PIN_NO(29) | 3)</div><div class='add'>+#define PINMUX_GPIO29__FUNC_CLKM1_A (MTK_PIN_NO(29) | 4)</div><div class='add'>+#define PINMUX_GPIO29__FUNC_UCTS4 (MTK_PIN_NO(29) | 6)</div><div class='add'>+#define PINMUX_GPIO29__FUNC_DBG_MON_A17 (MTK_PIN_NO(29) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0)</div><div class='add'>+#define PINMUX_GPIO30__FUNC_BPI_BUS20 (MTK_PIN_NO(30) | 1)</div><div class='add'>+#define PINMUX_GPIO30__FUNC_MD_NTN_URXD1 (MTK_PIN_NO(30) | 2)</div><div class='add'>+#define PINMUX_GPIO30__FUNC_SPI2_A_CLK (MTK_PIN_NO(30) | 3)</div><div class='add'>+#define PINMUX_GPIO30__FUNC_CLKM2_A (MTK_PIN_NO(30) | 4)</div><div class='add'>+#define PINMUX_GPIO30__FUNC_DSI3_HSYNC (MTK_PIN_NO(30) | 5)</div><div class='add'>+#define PINMUX_GPIO30__FUNC_URTS4 (MTK_PIN_NO(30) | 6)</div><div class='add'>+#define PINMUX_GPIO30__FUNC_DBG_MON_A18 (MTK_PIN_NO(30) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0)</div><div class='add'>+#define PINMUX_GPIO31__FUNC_BPI_BUS21 (MTK_PIN_NO(31) | 1)</div><div class='add'>+#define PINMUX_GPIO31__FUNC_SPI2_A_CSB (MTK_PIN_NO(31) | 3)</div><div class='add'>+#define PINMUX_GPIO31__FUNC_CLKM3_A (MTK_PIN_NO(31) | 4)</div><div class='add'>+#define PINMUX_GPIO31__FUNC_EDP_TX_HPD (MTK_PIN_NO(31) | 6)</div><div class='add'>+#define PINMUX_GPIO31__FUNC_DBG_MON_A19 (MTK_PIN_NO(31) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0)</div><div class='add'>+#define PINMUX_GPIO32__FUNC_LCM4_RST (MTK_PIN_NO(32) | 1)</div><div class='add'>+#define PINMUX_GPIO32__FUNC_DP_TX_HPD (MTK_PIN_NO(32) | 2)</div><div class='add'>+#define PINMUX_GPIO32__FUNC_SSPM_JTAG_TCK_VLP (MTK_PIN_NO(32) | 3)</div><div class='add'>+#define PINMUX_GPIO32__FUNC_ADSP_JTAG0_TCK (MTK_PIN_NO(32) | 4)</div><div class='add'>+#define PINMUX_GPIO32__FUNC_SCP_JTAG0_TCK_VLP (MTK_PIN_NO(32) | 5)</div><div class='add'>+#define PINMUX_GPIO32__FUNC_SPU0_TCK (MTK_PIN_NO(32) | 6)</div><div class='add'>+#define PINMUX_GPIO32__FUNC_IO_JTAG_TCK (MTK_PIN_NO(32) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)</div><div class='add'>+#define PINMUX_GPIO33__FUNC_DSI4_TE (MTK_PIN_NO(33) | 1)</div><div class='add'>+#define PINMUX_GPIO33__FUNC_DP_OC_EN (MTK_PIN_NO(33) | 2)</div><div class='add'>+#define PINMUX_GPIO33__FUNC_SSPM_JTAG_TRSTN_VLP (MTK_PIN_NO(33) | 3)</div><div class='add'>+#define PINMUX_GPIO33__FUNC_ADSP_JTAG0_TRSTN (MTK_PIN_NO(33) | 4)</div><div class='add'>+#define PINMUX_GPIO33__FUNC_SCP_JTAG0_TRSTN_VLP (MTK_PIN_NO(33) | 5)</div><div class='add'>+#define PINMUX_GPIO33__FUNC_SPU0_NTRST (MTK_PIN_NO(33) | 6)</div><div class='add'>+#define PINMUX_GPIO33__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(33) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)</div><div class='add'>+#define PINMUX_GPIO34__FUNC_UCTS5 (MTK_PIN_NO(34) | 1)</div><div class='add'>+#define PINMUX_GPIO34__FUNC_DP_RAUX_SBU1 (MTK_PIN_NO(34) | 2)</div><div class='add'>+#define PINMUX_GPIO34__FUNC_SSPM_JTAG_TDI_VLP (MTK_PIN_NO(34) | 3)</div><div class='add'>+#define PINMUX_GPIO34__FUNC_ADSP_JTAG0_TDI (MTK_PIN_NO(34) | 4)</div><div class='add'>+#define PINMUX_GPIO34__FUNC_SCP_JTAG0_TDI_VLP (MTK_PIN_NO(34) | 5)</div><div class='add'>+#define PINMUX_GPIO34__FUNC_SPU0_TDI (MTK_PIN_NO(34) | 6)</div><div class='add'>+#define PINMUX_GPIO34__FUNC_IO_JTAG_TDI (MTK_PIN_NO(34) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)</div><div class='add'>+#define PINMUX_GPIO35__FUNC_URTS5 (MTK_PIN_NO(35) | 1)</div><div class='add'>+#define PINMUX_GPIO35__FUNC_DP_RAUX_SBU2 (MTK_PIN_NO(35) | 2)</div><div class='add'>+#define PINMUX_GPIO35__FUNC_SSPM_JTAG_TDO_VLP (MTK_PIN_NO(35) | 3)</div><div class='add'>+#define PINMUX_GPIO35__FUNC_ADSP_JTAG0_TDO (MTK_PIN_NO(35) | 4)</div><div class='add'>+#define PINMUX_GPIO35__FUNC_SCP_JTAG0_TDO_VLP (MTK_PIN_NO(35) | 5)</div><div class='add'>+#define PINMUX_GPIO35__FUNC_SPU0_TDO (MTK_PIN_NO(35) | 6)</div><div class='add'>+#define PINMUX_GPIO35__FUNC_IO_JTAG_TDO (MTK_PIN_NO(35) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)</div><div class='add'>+#define PINMUX_GPIO36__FUNC_UTXD5 (MTK_PIN_NO(36) | 1)</div><div class='add'>+#define PINMUX_GPIO36__FUNC_SSPM_JTAG_TMS_VLP (MTK_PIN_NO(36) | 3)</div><div class='add'>+#define PINMUX_GPIO36__FUNC_ADSP_JTAG0_TMS (MTK_PIN_NO(36) | 4)</div><div class='add'>+#define PINMUX_GPIO36__FUNC_SCP_JTAG0_TMS_VLP (MTK_PIN_NO(36) | 5)</div><div class='add'>+#define PINMUX_GPIO36__FUNC_SPU0_TMS (MTK_PIN_NO(36) | 6)</div><div class='add'>+#define PINMUX_GPIO36__FUNC_IO_JTAG_TMS (MTK_PIN_NO(36) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)</div><div class='add'>+#define PINMUX_GPIO37__FUNC_URXD5 (MTK_PIN_NO(37) | 1)</div><div class='add'>+#define PINMUX_GPIO37__FUNC_MD_INT3 (MTK_PIN_NO(37) | 3)</div><div class='add'>+#define PINMUX_GPIO37__FUNC_CLKM0_B (MTK_PIN_NO(37) | 4)</div><div class='add'>+#define PINMUX_GPIO37__FUNC_TP_GPIO5_AO (MTK_PIN_NO(37) | 5)</div><div class='add'>+#define PINMUX_GPIO37__FUNC_SPU0_UTX (MTK_PIN_NO(37) | 6)</div><div class='add'>+#define PINMUX_GPIO37__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(37) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0)</div><div class='add'>+#define PINMUX_GPIO38__FUNC_SPMI_P_TRIG_FLAG (MTK_PIN_NO(38) | 2)</div><div class='add'>+#define PINMUX_GPIO38__FUNC_MD_INT4 (MTK_PIN_NO(38) | 3)</div><div class='add'>+#define PINMUX_GPIO38__FUNC_CLKM1_B (MTK_PIN_NO(38) | 4)</div><div class='add'>+#define PINMUX_GPIO38__FUNC_TP_GPIO6_AO (MTK_PIN_NO(38) | 5)</div><div class='add'>+#define PINMUX_GPIO38__FUNC_SPU0_URX (MTK_PIN_NO(38) | 6)</div><div class='add'>+#define PINMUX_GPIO38__FUNC_DAP_MD32_SWD (MTK_PIN_NO(38) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)</div><div class='add'>+#define PINMUX_GPIO39__FUNC_I2S_MCK0 (MTK_PIN_NO(39) | 1)</div><div class='add'>+#define PINMUX_GPIO39__FUNC_GPS_PPS0 (MTK_PIN_NO(39) | 3)</div><div class='add'>+#define PINMUX_GPIO39__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(39) | 4)</div><div class='add'>+#define PINMUX_GPIO39__FUNC_DBG_MON_B12 (MTK_PIN_NO(39) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)</div><div class='add'>+#define PINMUX_GPIO40__FUNC_I2SIN6_0_BCK (MTK_PIN_NO(40) | 1)</div><div class='add'>+#define PINMUX_GPIO40__FUNC_SPI4_B_CLK (MTK_PIN_NO(40) | 3)</div><div class='add'>+#define PINMUX_GPIO40__FUNC_UCTS2 (MTK_PIN_NO(40) | 4)</div><div class='add'>+#define PINMUX_GPIO40__FUNC_CCU1_UTXD (MTK_PIN_NO(40) | 5)</div><div class='add'>+#define PINMUX_GPIO40__FUNC_DBG_MON_B13 (MTK_PIN_NO(40) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0)</div><div class='add'>+#define PINMUX_GPIO41__FUNC_I2SIN6_0_LRCK (MTK_PIN_NO(41) | 1)</div><div class='add'>+#define PINMUX_GPIO41__FUNC_SPI4_B_CSB (MTK_PIN_NO(41) | 3)</div><div class='add'>+#define PINMUX_GPIO41__FUNC_URTS2 (MTK_PIN_NO(41) | 4)</div><div class='add'>+#define PINMUX_GPIO41__FUNC_CCU1_URXD (MTK_PIN_NO(41) | 5)</div><div class='add'>+#define PINMUX_GPIO41__FUNC_DBG_MON_B14 (MTK_PIN_NO(41) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0)</div><div class='add'>+#define PINMUX_GPIO42__FUNC_I2SIN6_0_DI (MTK_PIN_NO(42) | 1)</div><div class='add'>+#define PINMUX_GPIO42__FUNC_SPI4_B_MI (MTK_PIN_NO(42) | 3)</div><div class='add'>+#define PINMUX_GPIO42__FUNC_URXD2 (MTK_PIN_NO(42) | 4)</div><div class='add'>+#define PINMUX_GPIO42__FUNC_CCU1_URTS (MTK_PIN_NO(42) | 5)</div><div class='add'>+#define PINMUX_GPIO42__FUNC_MD32_0_RXD (MTK_PIN_NO(42) | 6)</div><div class='add'>+#define PINMUX_GPIO42__FUNC_DBG_MON_B15 (MTK_PIN_NO(42) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0)</div><div class='add'>+#define PINMUX_GPIO43__FUNC_I2SOUT6_0_DO (MTK_PIN_NO(43) | 1)</div><div class='add'>+#define PINMUX_GPIO43__FUNC_SPI4_B_MO (MTK_PIN_NO(43) | 3)</div><div class='add'>+#define PINMUX_GPIO43__FUNC_UTXD2 (MTK_PIN_NO(43) | 4)</div><div class='add'>+#define PINMUX_GPIO43__FUNC_CCU1_UCTS (MTK_PIN_NO(43) | 5)</div><div class='add'>+#define PINMUX_GPIO43__FUNC_MD32_0_TXD (MTK_PIN_NO(43) | 6)</div><div class='add'>+#define PINMUX_GPIO43__FUNC_DBG_MON_B16 (MTK_PIN_NO(43) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0)</div><div class='add'>+#define PINMUX_GPIO44__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(44) | 1)</div><div class='add'>+#define PINMUX_GPIO44__FUNC_SPI3_A_CLK (MTK_PIN_NO(44) | 3)</div><div class='add'>+#define PINMUX_GPIO44__FUNC_TP_GPIO10_AO (MTK_PIN_NO(44) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0)</div><div class='add'>+#define PINMUX_GPIO45__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(45) | 1)</div><div class='add'>+#define PINMUX_GPIO45__FUNC_DSI2_HSYNC (MTK_PIN_NO(45) | 2)</div><div class='add'>+#define PINMUX_GPIO45__FUNC_SPI3_A_CSB (MTK_PIN_NO(45) | 3)</div><div class='add'>+#define PINMUX_GPIO45__FUNC_PWM_VLP (MTK_PIN_NO(45) | 4)</div><div class='add'>+#define PINMUX_GPIO45__FUNC_TP_GPIO11_AO (MTK_PIN_NO(45) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0)</div><div class='add'>+#define PINMUX_GPIO46__FUNC_SCP_SCL4 (MTK_PIN_NO(46) | 1)</div><div class='add'>+#define PINMUX_GPIO46__FUNC_PWM_VLP (MTK_PIN_NO(46) | 2)</div><div class='add'>+#define PINMUX_GPIO46__FUNC_SCP_ILDO_DTEST1_VLP (MTK_PIN_NO(46) | 4)</div><div class='add'>+#define PINMUX_GPIO46__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(46) | 5)</div><div class='add'>+#define PINMUX_GPIO46__FUNC_TP_GPIO0_AO (MTK_PIN_NO(46) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0)</div><div class='add'>+#define PINMUX_GPIO47__FUNC_SCP_SDA4 (MTK_PIN_NO(47) | 1)</div><div class='add'>+#define PINMUX_GPIO47__FUNC_SCP_ILDO_DTEST2_VLP (MTK_PIN_NO(47) | 4)</div><div class='add'>+#define PINMUX_GPIO47__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(47) | 5)</div><div class='add'>+#define PINMUX_GPIO47__FUNC_TP_GPIO1_AO (MTK_PIN_NO(47) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0)</div><div class='add'>+#define PINMUX_GPIO48__FUNC_SCP_SCL5 (MTK_PIN_NO(48) | 1)</div><div class='add'>+#define PINMUX_GPIO48__FUNC_PWM_VLP (MTK_PIN_NO(48) | 2)</div><div class='add'>+#define PINMUX_GPIO48__FUNC_CCU0_UTXD (MTK_PIN_NO(48) | 3)</div><div class='add'>+#define PINMUX_GPIO48__FUNC_SCP_ILDO_DTEST3_VLP (MTK_PIN_NO(48) | 4)</div><div class='add'>+#define PINMUX_GPIO48__FUNC_TP_GPIO2_AO (MTK_PIN_NO(48) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0)</div><div class='add'>+#define PINMUX_GPIO49__FUNC_SCP_SDA5 (MTK_PIN_NO(49) | 1)</div><div class='add'>+#define PINMUX_GPIO49__FUNC_CCU0_URXD (MTK_PIN_NO(49) | 3)</div><div class='add'>+#define PINMUX_GPIO49__FUNC_SCP_ILDO_DTEST4_VLP (MTK_PIN_NO(49) | 4)</div><div class='add'>+#define PINMUX_GPIO49__FUNC_TP_GPIO3_AO (MTK_PIN_NO(49) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0)</div><div class='add'>+#define PINMUX_GPIO50__FUNC_SCP_SCL6 (MTK_PIN_NO(50) | 1)</div><div class='add'>+#define PINMUX_GPIO50__FUNC_PWM_VLP (MTK_PIN_NO(50) | 2)</div><div class='add'>+#define PINMUX_GPIO50__FUNC_CCU0_URTS (MTK_PIN_NO(50) | 3)</div><div class='add'>+#define PINMUX_GPIO50__FUNC_DSI_HSYNC (MTK_PIN_NO(50) | 4)</div><div class='add'>+#define PINMUX_GPIO50__FUNC_TP_GPIO4_AO (MTK_PIN_NO(50) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0)</div><div class='add'>+#define PINMUX_GPIO51__FUNC_SCP_SDA6 (MTK_PIN_NO(51) | 1)</div><div class='add'>+#define PINMUX_GPIO51__FUNC_CCU0_UCTS (MTK_PIN_NO(51) | 3)</div><div class='add'>+#define PINMUX_GPIO51__FUNC_DSI1_HSYNC (MTK_PIN_NO(51) | 4)</div><div class='add'>+#define PINMUX_GPIO51__FUNC_TP_GPIO5_AO (MTK_PIN_NO(51) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0)</div><div class='add'>+#define PINMUX_GPIO52__FUNC_SCP_SCL1 (MTK_PIN_NO(52) | 1)</div><div class='add'>+#define PINMUX_GPIO52__FUNC_TDM_DATA2 (MTK_PIN_NO(52) | 3)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0)</div><div class='add'>+#define PINMUX_GPIO53__FUNC_SCP_SDA1 (MTK_PIN_NO(53) | 1)</div><div class='add'>+#define PINMUX_GPIO53__FUNC_TDM_DATA3 (MTK_PIN_NO(53) | 3)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0)</div><div class='add'>+#define PINMUX_GPIO54__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(54) | 1)</div><div class='add'>+#define PINMUX_GPIO54__FUNC_TDM_MCK (MTK_PIN_NO(54) | 3)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0)</div><div class='add'>+#define PINMUX_GPIO55__FUNC_AUD_CLK_MISO (MTK_PIN_NO(55) | 1)</div><div class='add'>+#define PINMUX_GPIO55__FUNC_I2SOUT2_BCK (MTK_PIN_NO(55) | 2)</div><div class='add'>+#define PINMUX_GPIO55__FUNC_TDM_BCK (MTK_PIN_NO(55) | 3)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0)</div><div class='add'>+#define PINMUX_GPIO56__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(56) | 1)</div><div class='add'>+#define PINMUX_GPIO56__FUNC_I2SOUT2_LRCK (MTK_PIN_NO(56) | 2)</div><div class='add'>+#define PINMUX_GPIO56__FUNC_TDM_LRCK (MTK_PIN_NO(56) | 3)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0)</div><div class='add'>+#define PINMUX_GPIO57__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(57) | 1)</div><div class='add'>+#define PINMUX_GPIO57__FUNC_I2SOUT2_DO (MTK_PIN_NO(57) | 2)</div><div class='add'>+#define PINMUX_GPIO57__FUNC_TDM_DATA0 (MTK_PIN_NO(57) | 3)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0)</div><div class='add'>+#define PINMUX_GPIO58__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(58) | 1)</div><div class='add'>+#define PINMUX_GPIO58__FUNC_TDM_DATA1 (MTK_PIN_NO(58) | 3)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0)</div><div class='add'>+#define PINMUX_GPIO59__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(59) | 1)</div><div class='add'>+#define PINMUX_GPIO59__FUNC_I2SIN1_BCK (MTK_PIN_NO(59) | 3)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0)</div><div class='add'>+#define PINMUX_GPIO60__FUNC_KPCOL0 (MTK_PIN_NO(60) | 1)</div><div class='add'>+#define PINMUX_GPIO60__FUNC_TP_GPIO13_AO (MTK_PIN_NO(60) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0)</div><div class='add'>+#define PINMUX_GPIO61__FUNC_MCU_M_PMIC_POC_I (MTK_PIN_NO(61) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0)</div><div class='add'>+#define PINMUX_GPIO62__FUNC_MCU_B_PMIC_POC_I (MTK_PIN_NO(62) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0)</div><div class='add'>+#define PINMUX_GPIO63__FUNC_MFG_PMIC_POC_I (MTK_PIN_NO(63) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0)</div><div class='add'>+#define PINMUX_GPIO64__FUNC_PRE_UVLO (MTK_PIN_NO(64) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0)</div><div class='add'>+#define PINMUX_GPIO65__FUNC_DPM2PMIC (MTK_PIN_NO(65) | 1)</div><div class='add'>+#define PINMUX_GPIO65__FUNC_SRCLKENA1 (MTK_PIN_NO(65) | 2)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0)</div><div class='add'>+#define PINMUX_GPIO66__FUNC_WATCHDOG (MTK_PIN_NO(66) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0)</div><div class='add'>+#define PINMUX_GPIO67__FUNC_SRCLKENA0 (MTK_PIN_NO(67) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0)</div><div class='add'>+#define PINMUX_GPIO68__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(68) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0)</div><div class='add'>+#define PINMUX_GPIO69__FUNC_RTC32K_CK (MTK_PIN_NO(69) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0)</div><div class='add'>+#define PINMUX_GPIO70__FUNC_CMFLASH0 (MTK_PIN_NO(70) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0)</div><div class='add'>+#define PINMUX_GPIO74__FUNC_DCXO_FPM_LPM (MTK_PIN_NO(74) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0)</div><div class='add'>+#define PINMUX_GPIO75__FUNC_SPMI_M_SCL (MTK_PIN_NO(75) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0)</div><div class='add'>+#define PINMUX_GPIO76__FUNC_SPMI_M_SDA (MTK_PIN_NO(76) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0)</div><div class='add'>+#define PINMUX_GPIO77__FUNC_SPMI_P_SCL (MTK_PIN_NO(77) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0)</div><div class='add'>+#define PINMUX_GPIO78__FUNC_SPMI_P_SDA (MTK_PIN_NO(78) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0)</div><div class='add'>+#define PINMUX_GPIO79__FUNC_CMMCLK0 (MTK_PIN_NO(79) | 1)</div><div class='add'>+#define PINMUX_GPIO79__FUNC_MD_INT4 (MTK_PIN_NO(79) | 2)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0)</div><div class='add'>+#define PINMUX_GPIO80__FUNC_CMMCLK1 (MTK_PIN_NO(80) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0)</div><div class='add'>+#define PINMUX_GPIO81__FUNC_SCP_SPI0_CK (MTK_PIN_NO(81) | 1)</div><div class='add'>+#define PINMUX_GPIO81__FUNC_SPI6_B_CLK (MTK_PIN_NO(81) | 2)</div><div class='add'>+#define PINMUX_GPIO81__FUNC_PWM_VLP (MTK_PIN_NO(81) | 3)</div><div class='add'>+#define PINMUX_GPIO81__FUNC_I2SOUT5_BCK (MTK_PIN_NO(81) | 4)</div><div class='add'>+#define PINMUX_GPIO81__FUNC_TP_GPIO0_AO (MTK_PIN_NO(81) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0)</div><div class='add'>+#define PINMUX_GPIO82__FUNC_SCP_SPI0_CS (MTK_PIN_NO(82) | 1)</div><div class='add'>+#define PINMUX_GPIO82__FUNC_SPI6_B_CSB (MTK_PIN_NO(82) | 2)</div><div class='add'>+#define PINMUX_GPIO82__FUNC_I2SOUT5_LRCK (MTK_PIN_NO(82) | 4)</div><div class='add'>+#define PINMUX_GPIO82__FUNC_TP_GPIO1_AO (MTK_PIN_NO(82) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0)</div><div class='add'>+#define PINMUX_GPIO83__FUNC_SCP_SPI0_MO (MTK_PIN_NO(83) | 1)</div><div class='add'>+#define PINMUX_GPIO83__FUNC_SPI6_B_MO (MTK_PIN_NO(83) | 2)</div><div class='add'>+#define PINMUX_GPIO83__FUNC_I2SOUT5_DATA0 (MTK_PIN_NO(83) | 4)</div><div class='add'>+#define PINMUX_GPIO83__FUNC_TP_GPIO2_AO (MTK_PIN_NO(83) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0)</div><div class='add'>+#define PINMUX_GPIO84__FUNC_SCP_SPI0_MI (MTK_PIN_NO(84) | 1)</div><div class='add'>+#define PINMUX_GPIO84__FUNC_SPI6_B_MI (MTK_PIN_NO(84) | 2)</div><div class='add'>+#define PINMUX_GPIO84__FUNC_I2SOUT5_DATA1 (MTK_PIN_NO(84) | 4)</div><div class='add'>+#define PINMUX_GPIO84__FUNC_TP_GPIO3_AO (MTK_PIN_NO(84) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0)</div><div class='add'>+#define PINMUX_GPIO85__FUNC_SCP_SPI1_CK (MTK_PIN_NO(85) | 1)</div><div class='add'>+#define PINMUX_GPIO85__FUNC_SPI7_B_CLK (MTK_PIN_NO(85) | 2)</div><div class='add'>+#define PINMUX_GPIO85__FUNC_I2SIN5_DATA0 (MTK_PIN_NO(85) | 4)</div><div class='add'>+#define PINMUX_GPIO85__FUNC_PWM_VLP (MTK_PIN_NO(85) | 5)</div><div class='add'>+#define PINMUX_GPIO85__FUNC_TP_GPIO4_AO (MTK_PIN_NO(85) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0)</div><div class='add'>+#define PINMUX_GPIO86__FUNC_SCP_SPI1_CS (MTK_PIN_NO(86) | 1)</div><div class='add'>+#define PINMUX_GPIO86__FUNC_SPI7_B_CSB (MTK_PIN_NO(86) | 2)</div><div class='add'>+#define PINMUX_GPIO86__FUNC_I2SIN5_DATA1 (MTK_PIN_NO(86) | 4)</div><div class='add'>+#define PINMUX_GPIO86__FUNC_TP_GPIO5_AO (MTK_PIN_NO(86) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0)</div><div class='add'>+#define PINMUX_GPIO87__FUNC_SCP_SPI1_MO (MTK_PIN_NO(87) | 1)</div><div class='add'>+#define PINMUX_GPIO87__FUNC_SPI7_B_MO (MTK_PIN_NO(87) | 2)</div><div class='add'>+#define PINMUX_GPIO87__FUNC_I2SIN5_BCK (MTK_PIN_NO(87) | 4)</div><div class='add'>+#define PINMUX_GPIO87__FUNC_TP_GPIO6_AO (MTK_PIN_NO(87) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0)</div><div class='add'>+#define PINMUX_GPIO88__FUNC_SCP_SPI1_MI (MTK_PIN_NO(88) | 1)</div><div class='add'>+#define PINMUX_GPIO88__FUNC_SPI7_B_MI (MTK_PIN_NO(88) | 2)</div><div class='add'>+#define PINMUX_GPIO88__FUNC_I2SIN5_LRCK (MTK_PIN_NO(88) | 4)</div><div class='add'>+#define PINMUX_GPIO88__FUNC_TP_GPIO7_AO (MTK_PIN_NO(88) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0)</div><div class='add'>+#define PINMUX_GPIO89__FUNC_DSI_TE (MTK_PIN_NO(89) | 1)</div><div class='add'>+#define PINMUX_GPIO89__FUNC_DSI1_TE (MTK_PIN_NO(89) | 2)</div><div class='add'>+#define PINMUX_GPIO89__FUNC_DBG_MON_B30 (MTK_PIN_NO(89) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0)</div><div class='add'>+#define PINMUX_GPIO90__FUNC_LCM_RST (MTK_PIN_NO(90) | 1)</div><div class='add'>+#define PINMUX_GPIO90__FUNC_LCM1_RST (MTK_PIN_NO(90) | 2)</div><div class='add'>+#define PINMUX_GPIO90__FUNC_DBG_MON_B31 (MTK_PIN_NO(90) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0)</div><div class='add'>+#define PINMUX_GPIO91__FUNC_CMFLASH2 (MTK_PIN_NO(91) | 1)</div><div class='add'>+#define PINMUX_GPIO91__FUNC_SF_D0 (MTK_PIN_NO(91) | 2)</div><div class='add'>+#define PINMUX_GPIO91__FUNC_SRCLKENAI1 (MTK_PIN_NO(91) | 3)</div><div class='add'>+#define PINMUX_GPIO91__FUNC_KPCOL2 (MTK_PIN_NO(91) | 5)</div><div class='add'>+#define PINMUX_GPIO91__FUNC_TP_GPIO11_AO (MTK_PIN_NO(91) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0)</div><div class='add'>+#define PINMUX_GPIO92__FUNC_CMFLASH3 (MTK_PIN_NO(92) | 1)</div><div class='add'>+#define PINMUX_GPIO92__FUNC_SF_D1 (MTK_PIN_NO(92) | 2)</div><div class='add'>+#define PINMUX_GPIO92__FUNC_DISP_PWM1 (MTK_PIN_NO(92) | 4)</div><div class='add'>+#define PINMUX_GPIO92__FUNC_TP_GPIO12_AO (MTK_PIN_NO(92) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0)</div><div class='add'>+#define PINMUX_GPIO93__FUNC_CMFLASH1 (MTK_PIN_NO(93) | 1)</div><div class='add'>+#define PINMUX_GPIO93__FUNC_SF_D2 (MTK_PIN_NO(93) | 2)</div><div class='add'>+#define PINMUX_GPIO93__FUNC_SRCLKENAI0 (MTK_PIN_NO(93) | 3)</div><div class='add'>+#define PINMUX_GPIO93__FUNC_KPROW2 (MTK_PIN_NO(93) | 5)</div><div class='add'>+#define PINMUX_GPIO93__FUNC_TP_GPIO13_AO (MTK_PIN_NO(93) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0)</div><div class='add'>+#define PINMUX_GPIO94__FUNC_I2S_MCK1 (MTK_PIN_NO(94) | 1)</div><div class='add'>+#define PINMUX_GPIO94__FUNC_SF_D3 (MTK_PIN_NO(94) | 2)</div><div class='add'>+#define PINMUX_GPIO94__FUNC_MD32_0_GPIO0 (MTK_PIN_NO(94) | 4)</div><div class='add'>+#define PINMUX_GPIO94__FUNC_CLKM0_A (MTK_PIN_NO(94) | 5)</div><div class='add'>+#define PINMUX_GPIO94__FUNC_TP_GPIO14_AO (MTK_PIN_NO(94) | 6)</div><div class='add'>+#define PINMUX_GPIO94__FUNC_DBG_MON_B18 (MTK_PIN_NO(94) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0)</div><div class='add'>+#define PINMUX_GPIO95__FUNC_I2SIN1_BCK (MTK_PIN_NO(95) | 1)</div><div class='add'>+#define PINMUX_GPIO95__FUNC_I2SIN4_BCK (MTK_PIN_NO(95) | 2)</div><div class='add'>+#define PINMUX_GPIO95__FUNC_SPI6_A_CLK (MTK_PIN_NO(95) | 3)</div><div class='add'>+#define PINMUX_GPIO95__FUNC_MD32_1_GPIO0 (MTK_PIN_NO(95) | 4)</div><div class='add'>+#define PINMUX_GPIO95__FUNC_CLKM1_A (MTK_PIN_NO(95) | 5)</div><div class='add'>+#define PINMUX_GPIO95__FUNC_TP_GPIO15_AO (MTK_PIN_NO(95) | 6)</div><div class='add'>+#define PINMUX_GPIO95__FUNC_DBG_MON_B19 (MTK_PIN_NO(95) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0)</div><div class='add'>+#define PINMUX_GPIO96__FUNC_I2SIN1_LRCK (MTK_PIN_NO(96) | 1)</div><div class='add'>+#define PINMUX_GPIO96__FUNC_I2SIN4_LRCK (MTK_PIN_NO(96) | 2)</div><div class='add'>+#define PINMUX_GPIO96__FUNC_SPI6_A_CSB (MTK_PIN_NO(96) | 3)</div><div class='add'>+#define PINMUX_GPIO96__FUNC_MD32_2_GPIO0 (MTK_PIN_NO(96) | 4)</div><div class='add'>+#define PINMUX_GPIO96__FUNC_CLKM2_A (MTK_PIN_NO(96) | 5)</div><div class='add'>+#define PINMUX_GPIO96__FUNC_DBG_MON_B20 (MTK_PIN_NO(96) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0)</div><div class='add'>+#define PINMUX_GPIO97__FUNC_I2SIN1_DI_A (MTK_PIN_NO(97) | 1)</div><div class='add'>+#define PINMUX_GPIO97__FUNC_I2SIN4_DATA0 (MTK_PIN_NO(97) | 2)</div><div class='add'>+#define PINMUX_GPIO97__FUNC_SPI6_A_MO (MTK_PIN_NO(97) | 3)</div><div class='add'>+#define PINMUX_GPIO97__FUNC_MD32_3_GPIO0 (MTK_PIN_NO(97) | 4)</div><div class='add'>+#define PINMUX_GPIO97__FUNC_CLKM3_A (MTK_PIN_NO(97) | 5)</div><div class='add'>+#define PINMUX_GPIO97__FUNC_DBG_MON_B21 (MTK_PIN_NO(97) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0)</div><div class='add'>+#define PINMUX_GPIO98__FUNC_I2SOUT1_DO (MTK_PIN_NO(98) | 1)</div><div class='add'>+#define PINMUX_GPIO98__FUNC_I2SOUT4_DATA0 (MTK_PIN_NO(98) | 2)</div><div class='add'>+#define PINMUX_GPIO98__FUNC_SPI6_A_MI (MTK_PIN_NO(98) | 3)</div><div class='add'>+#define PINMUX_GPIO98__FUNC_DBG_MON_B22 (MTK_PIN_NO(98) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0)</div><div class='add'>+#define PINMUX_GPIO99__FUNC_SCL0 (MTK_PIN_NO(99) | 1)</div><div class='add'>+#define PINMUX_GPIO99__FUNC_LCM2_RST (MTK_PIN_NO(99) | 2)</div><div class='add'>+#define PINMUX_GPIO99__FUNC_AUD_DAC_26M_CLK (MTK_PIN_NO(99) | 3)</div><div class='add'>+#define PINMUX_GPIO99__FUNC_SPU0_SCL (MTK_PIN_NO(99) | 4)</div><div class='add'>+#define PINMUX_GPIO99__FUNC_DBG_MON_B24 (MTK_PIN_NO(99) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0)</div><div class='add'>+#define PINMUX_GPIO100__FUNC_SDA0 (MTK_PIN_NO(100) | 1)</div><div class='add'>+#define PINMUX_GPIO100__FUNC_DSI2_TE (MTK_PIN_NO(100) | 2)</div><div class='add'>+#define PINMUX_GPIO100__FUNC_SPU0_SDA (MTK_PIN_NO(100) | 4)</div><div class='add'>+#define PINMUX_GPIO100__FUNC_DBG_MON_B25 (MTK_PIN_NO(100) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0)</div><div class='add'>+#define PINMUX_GPIO101__FUNC_SCL10 (MTK_PIN_NO(101) | 1)</div><div class='add'>+#define PINMUX_GPIO101__FUNC_SF_CS (MTK_PIN_NO(101) | 2)</div><div class='add'>+#define PINMUX_GPIO101__FUNC_SCP_DMIC1_CLK (MTK_PIN_NO(101) | 3)</div><div class='add'>+#define PINMUX_GPIO101__FUNC_I2SIN5_DATA2 (MTK_PIN_NO(101) | 4)</div><div class='add'>+#define PINMUX_GPIO101__FUNC_SCP_SCL_OIS (MTK_PIN_NO(101) | 5)</div><div class='add'>+#define PINMUX_GPIO101__FUNC_TP_GPIO10_AO (MTK_PIN_NO(101) | 6)</div><div class='add'>+#define PINMUX_GPIO101__FUNC_DBG_MON_B28 (MTK_PIN_NO(101) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0)</div><div class='add'>+#define PINMUX_GPIO102__FUNC_SDA10 (MTK_PIN_NO(102) | 1)</div><div class='add'>+#define PINMUX_GPIO102__FUNC_SF_CK (MTK_PIN_NO(102) | 2)</div><div class='add'>+#define PINMUX_GPIO102__FUNC_SCP_DMIC1_DAT (MTK_PIN_NO(102) | 3)</div><div class='add'>+#define PINMUX_GPIO102__FUNC_I2SIN5_DATA3 (MTK_PIN_NO(102) | 4)</div><div class='add'>+#define PINMUX_GPIO102__FUNC_SCP_SDA_OIS (MTK_PIN_NO(102) | 5)</div><div class='add'>+#define PINMUX_GPIO102__FUNC_TP_GPIO11_AO (MTK_PIN_NO(102) | 6)</div><div class='add'>+#define PINMUX_GPIO102__FUNC_DBG_MON_B29 (MTK_PIN_NO(102) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0)</div><div class='add'>+#define PINMUX_GPIO103__FUNC_DISP_PWM (MTK_PIN_NO(103) | 1)</div><div class='add'>+#define PINMUX_GPIO103__FUNC_DSI1_TE (MTK_PIN_NO(103) | 2)</div><div class='add'>+#define PINMUX_GPIO103__FUNC_I2S_MCK0 (MTK_PIN_NO(103) | 5)</div><div class='add'>+#define PINMUX_GPIO103__FUNC_DBG_MON_B23 (MTK_PIN_NO(103) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0)</div><div class='add'>+#define PINMUX_GPIO104__FUNC_SCL6 (MTK_PIN_NO(104) | 1)</div><div class='add'>+#define PINMUX_GPIO104__FUNC_SPU1_SCL (MTK_PIN_NO(104) | 2)</div><div class='add'>+#define PINMUX_GPIO104__FUNC_AUD_DAC_26M_CLK (MTK_PIN_NO(104) | 3)</div><div class='add'>+#define PINMUX_GPIO104__FUNC_USB_DRVVBUS_2P (MTK_PIN_NO(104) | 4)</div><div class='add'>+#define PINMUX_GPIO104__FUNC_I2S_MCK1 (MTK_PIN_NO(104) | 5)</div><div class='add'>+#define PINMUX_GPIO104__FUNC_IDDIG_2P (MTK_PIN_NO(104) | 6)</div><div class='add'>+#define PINMUX_GPIO104__FUNC_DBG_MON_B26 (MTK_PIN_NO(104) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0)</div><div class='add'>+#define PINMUX_GPIO105__FUNC_SDA6 (MTK_PIN_NO(105) | 1)</div><div class='add'>+#define PINMUX_GPIO105__FUNC_SPU1_SDA (MTK_PIN_NO(105) | 2)</div><div class='add'>+#define PINMUX_GPIO105__FUNC_DISP_PWM2 (MTK_PIN_NO(105) | 3)</div><div class='add'>+#define PINMUX_GPIO105__FUNC_VBUSVALID_2P (MTK_PIN_NO(105) | 4)</div><div class='add'>+#define PINMUX_GPIO105__FUNC_I2S_MCK2 (MTK_PIN_NO(105) | 5)</div><div class='add'>+#define PINMUX_GPIO105__FUNC_VBUSVALID_3P (MTK_PIN_NO(105) | 6)</div><div class='add'>+#define PINMUX_GPIO105__FUNC_DBG_MON_B27 (MTK_PIN_NO(105) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0)</div><div class='add'>+#define PINMUX_GPIO106__FUNC_SCP_SPI3_CK (MTK_PIN_NO(106) | 1)</div><div class='add'>+#define PINMUX_GPIO106__FUNC_SPI3_B_CLK (MTK_PIN_NO(106) | 2)</div><div class='add'>+#define PINMUX_GPIO106__FUNC_MD_UTXD0 (MTK_PIN_NO(106) | 3)</div><div class='add'>+#define PINMUX_GPIO106__FUNC_TP_UTXD1_VLP (MTK_PIN_NO(106) | 4)</div><div class='add'>+#define PINMUX_GPIO106__FUNC_CONN_BG_GPS_MCU_UART0_TXD (MTK_PIN_NO(106) | 5)</div><div class='add'>+#define PINMUX_GPIO106__FUNC_TP_GPIO6_AO (MTK_PIN_NO(106) | 6)</div><div class='add'>+#define PINMUX_GPIO106__FUNC_DBG_MON_B0 (MTK_PIN_NO(106) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0)</div><div class='add'>+#define PINMUX_GPIO107__FUNC_SCP_SPI3_CS (MTK_PIN_NO(107) | 1)</div><div class='add'>+#define PINMUX_GPIO107__FUNC_SPI3_B_CSB (MTK_PIN_NO(107) | 2)</div><div class='add'>+#define PINMUX_GPIO107__FUNC_MD_URXD0 (MTK_PIN_NO(107) | 3)</div><div class='add'>+#define PINMUX_GPIO107__FUNC_TP_URXD1_VLP (MTK_PIN_NO(107) | 4)</div><div class='add'>+#define PINMUX_GPIO107__FUNC_CONN_BG_GPS_MCU_UART0_RXD (MTK_PIN_NO(107) | 5)</div><div class='add'>+#define PINMUX_GPIO107__FUNC_TP_GPIO7_AO (MTK_PIN_NO(107) | 6)</div><div class='add'>+#define PINMUX_GPIO107__FUNC_DBG_MON_B1 (MTK_PIN_NO(107) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0)</div><div class='add'>+#define PINMUX_GPIO108__FUNC_SCP_SPI3_MO (MTK_PIN_NO(108) | 1)</div><div class='add'>+#define PINMUX_GPIO108__FUNC_SPI3_B_MO (MTK_PIN_NO(108) | 2)</div><div class='add'>+#define PINMUX_GPIO108__FUNC_MD_UTXD1 (MTK_PIN_NO(108) | 3)</div><div class='add'>+#define PINMUX_GPIO108__FUNC_MD32PCM_UTXD_AO_VLP (MTK_PIN_NO(108) | 4)</div><div class='add'>+#define PINMUX_GPIO108__FUNC_CONN_BG_GPS_MCU_UART1_TXD (MTK_PIN_NO(108) | 5)</div><div class='add'>+#define PINMUX_GPIO108__FUNC_TP_GPIO8_AO (MTK_PIN_NO(108) | 6)</div><div class='add'>+#define PINMUX_GPIO108__FUNC_DBG_MON_B2 (MTK_PIN_NO(108) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0)</div><div class='add'>+#define PINMUX_GPIO109__FUNC_SCP_SPI3_MI (MTK_PIN_NO(109) | 1)</div><div class='add'>+#define PINMUX_GPIO109__FUNC_SPI3_B_MI (MTK_PIN_NO(109) | 2)</div><div class='add'>+#define PINMUX_GPIO109__FUNC_MD_URXD1 (MTK_PIN_NO(109) | 3)</div><div class='add'>+#define PINMUX_GPIO109__FUNC_MD32PCM_URXD_AO_VLP (MTK_PIN_NO(109) | 4)</div><div class='add'>+#define PINMUX_GPIO109__FUNC_CONN_BG_GPS_MCU_UART1_RXD (MTK_PIN_NO(109) | 5)</div><div class='add'>+#define PINMUX_GPIO109__FUNC_TP_GPIO9_AO (MTK_PIN_NO(109) | 6)</div><div class='add'>+#define PINMUX_GPIO109__FUNC_DBG_MON_B3 (MTK_PIN_NO(109) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0)</div><div class='add'>+#define PINMUX_GPIO110__FUNC_SPI1_CLK (MTK_PIN_NO(110) | 1)</div><div class='add'>+#define PINMUX_GPIO110__FUNC_PWM_0 (MTK_PIN_NO(110) | 2)</div><div class='add'>+#define PINMUX_GPIO110__FUNC_MD_UCTS0 (MTK_PIN_NO(110) | 3)</div><div class='add'>+#define PINMUX_GPIO110__FUNC_TP_UCTS1_VLP (MTK_PIN_NO(110) | 4)</div><div class='add'>+#define PINMUX_GPIO110__FUNC_SPU0_GPIO_O (MTK_PIN_NO(110) | 6)</div><div class='add'>+#define PINMUX_GPIO110__FUNC_DBG_MON_B4 (MTK_PIN_NO(110) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0)</div><div class='add'>+#define PINMUX_GPIO111__FUNC_SPI1_CSB (MTK_PIN_NO(111) | 1)</div><div class='add'>+#define PINMUX_GPIO111__FUNC_PWM_1 (MTK_PIN_NO(111) | 2)</div><div class='add'>+#define PINMUX_GPIO111__FUNC_MD_URTS0 (MTK_PIN_NO(111) | 3)</div><div class='add'>+#define PINMUX_GPIO111__FUNC_TP_URTS1_VLP (MTK_PIN_NO(111) | 4)</div><div class='add'>+#define PINMUX_GPIO111__FUNC_SPU0_GPIO_I (MTK_PIN_NO(111) | 6)</div><div class='add'>+#define PINMUX_GPIO111__FUNC_DBG_MON_B5 (MTK_PIN_NO(111) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0)</div><div class='add'>+#define PINMUX_GPIO112__FUNC_SPI1_MO (MTK_PIN_NO(112) | 1)</div><div class='add'>+#define PINMUX_GPIO112__FUNC_PWM_2 (MTK_PIN_NO(112) | 2)</div><div class='add'>+#define PINMUX_GPIO112__FUNC_MD_UCTS1 (MTK_PIN_NO(112) | 3)</div><div class='add'>+#define PINMUX_GPIO112__FUNC_SPU1_GPIO_O (MTK_PIN_NO(112) | 6)</div><div class='add'>+#define PINMUX_GPIO112__FUNC_DBG_MON_B6 (MTK_PIN_NO(112) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0)</div><div class='add'>+#define PINMUX_GPIO113__FUNC_SPI1_MI (MTK_PIN_NO(113) | 1)</div><div class='add'>+#define PINMUX_GPIO113__FUNC_PWM_3 (MTK_PIN_NO(113) | 2)</div><div class='add'>+#define PINMUX_GPIO113__FUNC_MD_URTS1 (MTK_PIN_NO(113) | 3)</div><div class='add'>+#define PINMUX_GPIO113__FUNC_SPU1_GPIO_I (MTK_PIN_NO(113) | 6)</div><div class='add'>+#define PINMUX_GPIO113__FUNC_DBG_MON_B7 (MTK_PIN_NO(113) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0)</div><div class='add'>+#define PINMUX_GPIO114__FUNC_SPI0_SPU_CLK (MTK_PIN_NO(114) | 1)</div><div class='add'>+#define PINMUX_GPIO114__FUNC_SPI4_A_CLK (MTK_PIN_NO(114) | 2)</div><div class='add'>+#define PINMUX_GPIO114__FUNC_CONN_BG_GPS_MCU_DBG_UART_TXD (MTK_PIN_NO(114) | 5)</div><div class='add'>+#define PINMUX_GPIO114__FUNC_DBG_MON_B8 (MTK_PIN_NO(114) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0)</div><div class='add'>+#define PINMUX_GPIO115__FUNC_SPI0_SPU_CSB (MTK_PIN_NO(115) | 1)</div><div class='add'>+#define PINMUX_GPIO115__FUNC_SPI4_A_CSB (MTK_PIN_NO(115) | 2)</div><div class='add'>+#define PINMUX_GPIO115__FUNC_DBG_MON_B9 (MTK_PIN_NO(115) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0)</div><div class='add'>+#define PINMUX_GPIO116__FUNC_SPI0_SPU_MO (MTK_PIN_NO(116) | 1)</div><div class='add'>+#define PINMUX_GPIO116__FUNC_SPI4_A_MO (MTK_PIN_NO(116) | 2)</div><div class='add'>+#define PINMUX_GPIO116__FUNC_LCM1_RST (MTK_PIN_NO(116) | 3)</div><div class='add'>+#define PINMUX_GPIO116__FUNC_DBG_MON_B10 (MTK_PIN_NO(116) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0)</div><div class='add'>+#define PINMUX_GPIO117__FUNC_SPI0_SPU_MI (MTK_PIN_NO(117) | 1)</div><div class='add'>+#define PINMUX_GPIO117__FUNC_SPI4_A_MI (MTK_PIN_NO(117) | 2)</div><div class='add'>+#define PINMUX_GPIO117__FUNC_DSI1_TE (MTK_PIN_NO(117) | 3)</div><div class='add'>+#define PINMUX_GPIO117__FUNC_DBG_MON_B11 (MTK_PIN_NO(117) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0)</div><div class='add'>+#define PINMUX_GPIO118__FUNC_SPI5_CLK (MTK_PIN_NO(118) | 1)</div><div class='add'>+#define PINMUX_GPIO118__FUNC_USB_DRVVBUS (MTK_PIN_NO(118) | 2)</div><div class='add'>+#define PINMUX_GPIO118__FUNC_DP_TX_HPD (MTK_PIN_NO(118) | 3)</div><div class='add'>+#define PINMUX_GPIO118__FUNC_AD_ILDO_DTEST0 (MTK_PIN_NO(118) | 4)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0)</div><div class='add'>+#define PINMUX_GPIO119__FUNC_SPI5_CSB (MTK_PIN_NO(119) | 1)</div><div class='add'>+#define PINMUX_GPIO119__FUNC_VBUSVALID (MTK_PIN_NO(119) | 2)</div><div class='add'>+#define PINMUX_GPIO119__FUNC_DP_OC_EN (MTK_PIN_NO(119) | 3)</div><div class='add'>+#define PINMUX_GPIO119__FUNC_AD_ILDO_DTEST1 (MTK_PIN_NO(119) | 4)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0)</div><div class='add'>+#define PINMUX_GPIO120__FUNC_SPI5_MO (MTK_PIN_NO(120) | 1)</div><div class='add'>+#define PINMUX_GPIO120__FUNC_LCM2_RST (MTK_PIN_NO(120) | 2)</div><div class='add'>+#define PINMUX_GPIO120__FUNC_DP_RAUX_SBU1 (MTK_PIN_NO(120) | 3)</div><div class='add'>+#define PINMUX_GPIO120__FUNC_AD_ILDO_DTEST2 (MTK_PIN_NO(120) | 4)</div><div class='add'>+#define PINMUX_GPIO120__FUNC_IDDIG_3P (MTK_PIN_NO(120) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0)</div><div class='add'>+#define PINMUX_GPIO121__FUNC_SPI5_MI (MTK_PIN_NO(121) | 1)</div><div class='add'>+#define PINMUX_GPIO121__FUNC_DSI2_TE (MTK_PIN_NO(121) | 2)</div><div class='add'>+#define PINMUX_GPIO121__FUNC_DP_RAUX_SBU2 (MTK_PIN_NO(121) | 3)</div><div class='add'>+#define PINMUX_GPIO121__FUNC_AD_ILDO_DTEST3 (MTK_PIN_NO(121) | 4)</div><div class='add'>+#define PINMUX_GPIO121__FUNC_USB_DRVVBUS_3P (MTK_PIN_NO(121) | 6)</div><div class='add'>+#define PINMUX_GPIO121__FUNC_DBG_MON_B17 (MTK_PIN_NO(121) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0)</div><div class='add'>+#define PINMUX_GPIO122__FUNC_AP_GOOD (MTK_PIN_NO(122) | 1)</div><div class='add'>+#define PINMUX_GPIO122__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(122) | 2)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0)</div><div class='add'>+#define PINMUX_GPIO123__FUNC_SCL3 (MTK_PIN_NO(123) | 1)</div><div class='add'>+#define PINMUX_GPIO123__FUNC_I2SIN2_LRCK (MTK_PIN_NO(123) | 5)</div><div class='add'>+#define PINMUX_GPIO123__FUNC_TP_UTXD_MD_VCORE (MTK_PIN_NO(123) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0)</div><div class='add'>+#define PINMUX_GPIO124__FUNC_SDA3 (MTK_PIN_NO(124) | 1)</div><div class='add'>+#define PINMUX_GPIO124__FUNC_TP_URXD_MD_VCORE (MTK_PIN_NO(124) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0)</div><div class='add'>+#define PINMUX_GPIO125__FUNC_MSDC1_CLK (MTK_PIN_NO(125) | 1)</div><div class='add'>+#define PINMUX_GPIO125__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(125) | 2)</div><div class='add'>+#define PINMUX_GPIO125__FUNC_HFRP_JTAG0_TCK (MTK_PIN_NO(125) | 3)</div><div class='add'>+#define PINMUX_GPIO125__FUNC_UDI_TCK (MTK_PIN_NO(125) | 4)</div><div class='add'>+#define PINMUX_GPIO125__FUNC_CONN_BGF_DSP_L1_JCK (MTK_PIN_NO(125) | 5)</div><div class='add'>+#define PINMUX_GPIO125__FUNC_SCP_JTAG_LITTLE_TCK_VLP (MTK_PIN_NO(125) | 6)</div><div class='add'>+#define PINMUX_GPIO125__FUNC_JTCK2_SEL1 (MTK_PIN_NO(125) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0)</div><div class='add'>+#define PINMUX_GPIO126__FUNC_MSDC1_CMD (MTK_PIN_NO(126) | 1)</div><div class='add'>+#define PINMUX_GPIO126__FUNC_HFRP_JTAG0_TMS (MTK_PIN_NO(126) | 3)</div><div class='add'>+#define PINMUX_GPIO126__FUNC_UDI_TMS (MTK_PIN_NO(126) | 4)</div><div class='add'>+#define PINMUX_GPIO126__FUNC_CONN_BGF_DSP_L1_JMS (MTK_PIN_NO(126) | 5)</div><div class='add'>+#define PINMUX_GPIO126__FUNC_SCP_JTAG_LITTLE_TMS_VLP (MTK_PIN_NO(126) | 6)</div><div class='add'>+#define PINMUX_GPIO126__FUNC_JTMS2_SEL1 (MTK_PIN_NO(126) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0)</div><div class='add'>+#define PINMUX_GPIO127__FUNC_MSDC1_DAT0 (MTK_PIN_NO(127) | 1)</div><div class='add'>+#define PINMUX_GPIO127__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(127) | 2)</div><div class='add'>+#define PINMUX_GPIO127__FUNC_HFRP_JTAG0_TDI (MTK_PIN_NO(127) | 3)</div><div class='add'>+#define PINMUX_GPIO127__FUNC_UDI_TDI_0 (MTK_PIN_NO(127) | 4)</div><div class='add'>+#define PINMUX_GPIO127__FUNC_CONN_BGF_DSP_L1_JDI (MTK_PIN_NO(127) | 5)</div><div class='add'>+#define PINMUX_GPIO127__FUNC_SCP_JTAG_LITTLE_TDI_VLP (MTK_PIN_NO(127) | 6)</div><div class='add'>+#define PINMUX_GPIO127__FUNC_JTDI2_SEL1 (MTK_PIN_NO(127) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0)</div><div class='add'>+#define PINMUX_GPIO128__FUNC_MSDC1_DAT1 (MTK_PIN_NO(128) | 1)</div><div class='add'>+#define PINMUX_GPIO128__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(128) | 2)</div><div class='add'>+#define PINMUX_GPIO128__FUNC_HFRP_JTAG0_TDO (MTK_PIN_NO(128) | 3)</div><div class='add'>+#define PINMUX_GPIO128__FUNC_UDI_TDO_0 (MTK_PIN_NO(128) | 4)</div><div class='add'>+#define PINMUX_GPIO128__FUNC_CONN_BGF_DSP_L1_JDO (MTK_PIN_NO(128) | 5)</div><div class='add'>+#define PINMUX_GPIO128__FUNC_SCP_JTAG_LITTLE_TDO_VLP (MTK_PIN_NO(128) | 6)</div><div class='add'>+#define PINMUX_GPIO128__FUNC_JTDO2_SEL1 (MTK_PIN_NO(128) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0)</div><div class='add'>+#define PINMUX_GPIO129__FUNC_MSDC1_DAT2 (MTK_PIN_NO(129) | 1)</div><div class='add'>+#define PINMUX_GPIO129__FUNC_DSI2_HSYNC (MTK_PIN_NO(129) | 2)</div><div class='add'>+#define PINMUX_GPIO129__FUNC_HFRP_JTAG0_TRSTN (MTK_PIN_NO(129) | 3)</div><div class='add'>+#define PINMUX_GPIO129__FUNC_UDI_NTRST (MTK_PIN_NO(129) | 4)</div><div class='add'>+#define PINMUX_GPIO129__FUNC_SCP_JTAG_LITTLE_TRSTN_VLP (MTK_PIN_NO(129) | 6)</div><div class='add'>+#define PINMUX_GPIO129__FUNC_JTRSTN2_SEL1 (MTK_PIN_NO(129) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0)</div><div class='add'>+#define PINMUX_GPIO130__FUNC_MSDC1_DAT3 (MTK_PIN_NO(130) | 1)</div><div class='add'>+#define PINMUX_GPIO130__FUNC_DSI3_HSYNC (MTK_PIN_NO(130) | 2)</div><div class='add'>+#define PINMUX_GPIO130__FUNC_CONN_BGF_DSP_L1_JINTP (MTK_PIN_NO(130) | 5)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0)</div><div class='add'>+#define PINMUX_GPIO131__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(131) | 1)</div><div class='add'>+#define PINMUX_GPIO131__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(131) | 2)</div><div class='add'>+#define PINMUX_GPIO131__FUNC_MCUPM_JTAG_TDI (MTK_PIN_NO(131) | 3)</div><div class='add'>+#define PINMUX_GPIO131__FUNC_CLKM0_A (MTK_PIN_NO(131) | 4)</div><div class='add'>+#define PINMUX_GPIO131__FUNC_CONN_BGF_DSP_L5_JDI (MTK_PIN_NO(131) | 5)</div><div class='add'>+#define PINMUX_GPIO131__FUNC_TSFDC_SCK (MTK_PIN_NO(131) | 6)</div><div class='add'>+#define PINMUX_GPIO131__FUNC_SCP_JTAG0_TDI_VCORE (MTK_PIN_NO(131) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0)</div><div class='add'>+#define PINMUX_GPIO132__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(132) | 1)</div><div class='add'>+#define PINMUX_GPIO132__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(132) | 2)</div><div class='add'>+#define PINMUX_GPIO132__FUNC_MCUPM_JTAG_TMS (MTK_PIN_NO(132) | 3)</div><div class='add'>+#define PINMUX_GPIO132__FUNC_CLKM1_B (MTK_PIN_NO(132) | 4)</div><div class='add'>+#define PINMUX_GPIO132__FUNC_CONN_BGF_DSP_L5_JMS (MTK_PIN_NO(132) | 5)</div><div class='add'>+#define PINMUX_GPIO132__FUNC_TSFDC_SDI (MTK_PIN_NO(132) | 6)</div><div class='add'>+#define PINMUX_GPIO132__FUNC_SCP_JTAG0_TMS_VCORE (MTK_PIN_NO(132) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0)</div><div class='add'>+#define PINMUX_GPIO133__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(133) | 1)</div><div class='add'>+#define PINMUX_GPIO133__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(133) | 2)</div><div class='add'>+#define PINMUX_GPIO133__FUNC_MCUPM_JTAG_TDO (MTK_PIN_NO(133) | 3)</div><div class='add'>+#define PINMUX_GPIO133__FUNC_CONN_BGF_DSP_L5_JDO (MTK_PIN_NO(133) | 5)</div><div class='add'>+#define PINMUX_GPIO133__FUNC_TSFDC_SCF (MTK_PIN_NO(133) | 6)</div><div class='add'>+#define PINMUX_GPIO133__FUNC_SCP_JTAG0_TDO_VCORE (MTK_PIN_NO(133) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0)</div><div class='add'>+#define PINMUX_GPIO134__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(134) | 1)</div><div class='add'>+#define PINMUX_GPIO134__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(134) | 2)</div><div class='add'>+#define PINMUX_GPIO134__FUNC_TSFDC_26M (MTK_PIN_NO(134) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0)</div><div class='add'>+#define PINMUX_GPIO135__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(135) | 1)</div><div class='add'>+#define PINMUX_GPIO135__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(135) | 2)</div><div class='add'>+#define PINMUX_GPIO135__FUNC_MCUPM_JTAG_TCK (MTK_PIN_NO(135) | 3)</div><div class='add'>+#define PINMUX_GPIO135__FUNC_CONN_BGF_DSP_L5_JCK (MTK_PIN_NO(135) | 5)</div><div class='add'>+#define PINMUX_GPIO135__FUNC_TSFDC_SDO (MTK_PIN_NO(135) | 6)</div><div class='add'>+#define PINMUX_GPIO135__FUNC_SCP_JTAG0_TCK_VCORE (MTK_PIN_NO(135) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0)</div><div class='add'>+#define PINMUX_GPIO136__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(136) | 1)</div><div class='add'>+#define PINMUX_GPIO136__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(136) | 2)</div><div class='add'>+#define PINMUX_GPIO136__FUNC_MCUPM_JTAG_TRSTN (MTK_PIN_NO(136) | 3)</div><div class='add'>+#define PINMUX_GPIO136__FUNC_CONN_BGF_DSP_L5_JINTP (MTK_PIN_NO(136) | 5)</div><div class='add'>+#define PINMUX_GPIO136__FUNC_TSFDC_FOUT (MTK_PIN_NO(136) | 6)</div><div class='add'>+#define PINMUX_GPIO136__FUNC_SCP_JTAG0_TRSTN_VCORE (MTK_PIN_NO(136) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0)</div><div class='add'>+#define PINMUX_GPIO137__FUNC_MIPI0_D_SCLK (MTK_PIN_NO(137) | 1)</div><div class='add'>+#define PINMUX_GPIO137__FUNC_BPI_BUS16 (MTK_PIN_NO(137) | 2)</div><div class='add'>+#define PINMUX_GPIO137__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(137) | 4)</div><div class='add'>+#define PINMUX_GPIO137__FUNC_SPM_JTAG_TRSTN_VCORE (MTK_PIN_NO(137) | 6)</div><div class='add'>+#define PINMUX_GPIO137__FUNC_DBG_MON_A0 (MTK_PIN_NO(137) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0)</div><div class='add'>+#define PINMUX_GPIO138__FUNC_MIPI0_D_SDATA (MTK_PIN_NO(138) | 1)</div><div class='add'>+#define PINMUX_GPIO138__FUNC_BPI_BUS17 (MTK_PIN_NO(138) | 2)</div><div class='add'>+#define PINMUX_GPIO138__FUNC_PCM0_LRCK (MTK_PIN_NO(138) | 4)</div><div class='add'>+#define PINMUX_GPIO138__FUNC_SPM_JTAG_TCK_VCORE (MTK_PIN_NO(138) | 6)</div><div class='add'>+#define PINMUX_GPIO138__FUNC_DBG_MON_A1 (MTK_PIN_NO(138) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0)</div><div class='add'>+#define PINMUX_GPIO139__FUNC_MIPI1_D_SCLK (MTK_PIN_NO(139) | 1)</div><div class='add'>+#define PINMUX_GPIO139__FUNC_BPI_BUS18 (MTK_PIN_NO(139) | 2)</div><div class='add'>+#define PINMUX_GPIO139__FUNC_MD_GPS_BLANK (MTK_PIN_NO(139) | 4)</div><div class='add'>+#define PINMUX_GPIO139__FUNC_SPM_JTAG_TMS_VCORE (MTK_PIN_NO(139) | 6)</div><div class='add'>+#define PINMUX_GPIO139__FUNC_DBG_MON_A2 (MTK_PIN_NO(139) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0)</div><div class='add'>+#define PINMUX_GPIO140__FUNC_MIPI1_D_SDATA (MTK_PIN_NO(140) | 1)</div><div class='add'>+#define PINMUX_GPIO140__FUNC_BPI_BUS19 (MTK_PIN_NO(140) | 2)</div><div class='add'>+#define PINMUX_GPIO140__FUNC_MD_URXD1_CONN (MTK_PIN_NO(140) | 4)</div><div class='add'>+#define PINMUX_GPIO140__FUNC_SPM_JTAG_TDO_VCORE (MTK_PIN_NO(140) | 6)</div><div class='add'>+#define PINMUX_GPIO140__FUNC_DBG_MON_A3 (MTK_PIN_NO(140) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0)</div><div class='add'>+#define PINMUX_GPIO141__FUNC_MIPI2_D_SCLK (MTK_PIN_NO(141) | 1)</div><div class='add'>+#define PINMUX_GPIO141__FUNC_BPI_BUS20 (MTK_PIN_NO(141) | 2)</div><div class='add'>+#define PINMUX_GPIO141__FUNC_MD_UTXD1_CONN (MTK_PIN_NO(141) | 4)</div><div class='add'>+#define PINMUX_GPIO141__FUNC_SPM_JTAG_TDI_VCORE (MTK_PIN_NO(141) | 6)</div><div class='add'>+#define PINMUX_GPIO141__FUNC_DBG_MON_A4 (MTK_PIN_NO(141) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0)</div><div class='add'>+#define PINMUX_GPIO142__FUNC_MIPI2_D_SDATA (MTK_PIN_NO(142) | 1)</div><div class='add'>+#define PINMUX_GPIO142__FUNC_BPI_BUS21 (MTK_PIN_NO(142) | 2)</div><div class='add'>+#define PINMUX_GPIO142__FUNC_SSPM_JTAG_TRSTN_VCORE (MTK_PIN_NO(142) | 6)</div><div class='add'>+#define PINMUX_GPIO142__FUNC_DBG_MON_A5 (MTK_PIN_NO(142) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0)</div><div class='add'>+#define PINMUX_GPIO143__FUNC_MIPI3_D_SCLK (MTK_PIN_NO(143) | 1)</div><div class='add'>+#define PINMUX_GPIO143__FUNC_BPI_BUS22 (MTK_PIN_NO(143) | 2)</div><div class='add'>+#define PINMUX_GPIO143__FUNC_TP_UTXD_GNSS_VLP (MTK_PIN_NO(143) | 4)</div><div class='add'>+#define PINMUX_GPIO143__FUNC_MD_UTXD1_CONN (MTK_PIN_NO(143) | 5)</div><div class='add'>+#define PINMUX_GPIO143__FUNC_SSPM_JTAG_TCK_VCORE (MTK_PIN_NO(143) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0)</div><div class='add'>+#define PINMUX_GPIO144__FUNC_MIPI3_D_SDATA (MTK_PIN_NO(144) | 1)</div><div class='add'>+#define PINMUX_GPIO144__FUNC_BPI_BUS23 (MTK_PIN_NO(144) | 2)</div><div class='add'>+#define PINMUX_GPIO144__FUNC_TP_URXD_GNSS_VLP (MTK_PIN_NO(144) | 4)</div><div class='add'>+#define PINMUX_GPIO144__FUNC_MD_URXD1_CONN (MTK_PIN_NO(144) | 5)</div><div class='add'>+#define PINMUX_GPIO144__FUNC_SSPM_JTAG_TMS_VCORE (MTK_PIN_NO(144) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0)</div><div class='add'>+#define PINMUX_GPIO145__FUNC_BPI_BUS0 (MTK_PIN_NO(145) | 1)</div><div class='add'>+#define PINMUX_GPIO145__FUNC_PCIE_WAKEN_1P (MTK_PIN_NO(145) | 4)</div><div class='add'>+#define PINMUX_GPIO145__FUNC_SSPM_JTAG_TDO_VCORE (MTK_PIN_NO(145) | 6)</div><div class='add'>+#define PINMUX_GPIO145__FUNC_DBG_MON_A10 (MTK_PIN_NO(145) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0)</div><div class='add'>+#define PINMUX_GPIO146__FUNC_BPI_BUS1 (MTK_PIN_NO(146) | 1)</div><div class='add'>+#define PINMUX_GPIO146__FUNC_PCIE_PERSTN_1P (MTK_PIN_NO(146) | 4)</div><div class='add'>+#define PINMUX_GPIO146__FUNC_SSPM_JTAG_TDI_VCORE (MTK_PIN_NO(146) | 6)</div><div class='add'>+#define PINMUX_GPIO146__FUNC_DBG_MON_A11 (MTK_PIN_NO(146) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0)</div><div class='add'>+#define PINMUX_GPIO147__FUNC_BPI_BUS2 (MTK_PIN_NO(147) | 1)</div><div class='add'>+#define PINMUX_GPIO147__FUNC_AUD_DAC_26M_CLK (MTK_PIN_NO(147) | 2)</div><div class='add'>+#define PINMUX_GPIO147__FUNC_PCIE_CLKREQN_1P (MTK_PIN_NO(147) | 4)</div><div class='add'>+#define PINMUX_GPIO147__FUNC_SCP_JTAG_LITTLE_TRSTN_VCORE (MTK_PIN_NO(147) | 6)</div><div class='add'>+#define PINMUX_GPIO147__FUNC_DBG_MON_A12 (MTK_PIN_NO(147) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0)</div><div class='add'>+#define PINMUX_GPIO148__FUNC_BPI_BUS3 (MTK_PIN_NO(148) | 1)</div><div class='add'>+#define PINMUX_GPIO148__FUNC_AUD_DAC_26M_CLK (MTK_PIN_NO(148) | 2)</div><div class='add'>+#define PINMUX_GPIO148__FUNC_TP_UTXD_MD_VLP (MTK_PIN_NO(148) | 4)</div><div class='add'>+#define PINMUX_GPIO148__FUNC_TP_GPIO0_AO (MTK_PIN_NO(148) | 5)</div><div class='add'>+#define PINMUX_GPIO148__FUNC_SCP_JTAG_LITTLE_TCK_VCORE (MTK_PIN_NO(148) | 6)</div><div class='add'>+#define PINMUX_GPIO148__FUNC_DBG_MON_A13 (MTK_PIN_NO(148) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0)</div><div class='add'>+#define PINMUX_GPIO149__FUNC_BPI_BUS4 (MTK_PIN_NO(149) | 1)</div><div class='add'>+#define PINMUX_GPIO149__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(149) | 2)</div><div class='add'>+#define PINMUX_GPIO149__FUNC_TP_URXD_MD_VLP (MTK_PIN_NO(149) | 4)</div><div class='add'>+#define PINMUX_GPIO149__FUNC_TP_GPIO1_AO (MTK_PIN_NO(149) | 5)</div><div class='add'>+#define PINMUX_GPIO149__FUNC_SCP_JTAG_LITTLE_TMS_VCORE (MTK_PIN_NO(149) | 6)</div><div class='add'>+#define PINMUX_GPIO149__FUNC_DBG_MON_A14 (MTK_PIN_NO(149) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0)</div><div class='add'>+#define PINMUX_GPIO150__FUNC_BPI_BUS5 (MTK_PIN_NO(150) | 1)</div><div class='add'>+#define PINMUX_GPIO150__FUNC_GPS_PPS0 (MTK_PIN_NO(150) | 2)</div><div class='add'>+#define PINMUX_GPIO150__FUNC_TP_GPIO2_AO (MTK_PIN_NO(150) | 5)</div><div class='add'>+#define PINMUX_GPIO150__FUNC_SCP_JTAG_LITTLE_TDO_VCORE (MTK_PIN_NO(150) | 6)</div><div class='add'>+#define PINMUX_GPIO150__FUNC_DBG_MON_A15 (MTK_PIN_NO(150) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0)</div><div class='add'>+#define PINMUX_GPIO151__FUNC_BPI_BUS6 (MTK_PIN_NO(151) | 1)</div><div class='add'>+#define PINMUX_GPIO151__FUNC_GPS_PPS1 (MTK_PIN_NO(151) | 2)</div><div class='add'>+#define PINMUX_GPIO151__FUNC_TP_GPIO3_AO (MTK_PIN_NO(151) | 5)</div><div class='add'>+#define PINMUX_GPIO151__FUNC_SCP_JTAG_LITTLE_TDI_VCORE (MTK_PIN_NO(151) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0)</div><div class='add'>+#define PINMUX_GPIO152__FUNC_BPI_BUS7 (MTK_PIN_NO(152) | 1)</div><div class='add'>+#define PINMUX_GPIO152__FUNC_EDP_TX_HPD (MTK_PIN_NO(152) | 2)</div><div class='add'>+#define PINMUX_GPIO152__FUNC_AGPS_SYNC (MTK_PIN_NO(152) | 5)</div><div class='add'>+#define PINMUX_GPIO152__FUNC_SSPM_UTXD_AO_VCORE (MTK_PIN_NO(152) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0)</div><div class='add'>+#define PINMUX_GPIO153__FUNC_MD_UCNT_A_TGL (MTK_PIN_NO(153) | 1)</div><div class='add'>+#define PINMUX_GPIO153__FUNC_TP_URTS1_VCORE (MTK_PIN_NO(153) | 6)</div><div class='add'>+#define PINMUX_GPIO153__FUNC_DBG_MON_A8 (MTK_PIN_NO(153) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0)</div><div class='add'>+#define PINMUX_GPIO154__FUNC_DIGRF_IRQ (MTK_PIN_NO(154) | 1)</div><div class='add'>+#define PINMUX_GPIO154__FUNC_TP_UCTS1_VCORE (MTK_PIN_NO(154) | 6)</div><div class='add'>+#define PINMUX_GPIO154__FUNC_DBG_MON_A9 (MTK_PIN_NO(154) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0)</div><div class='add'>+#define PINMUX_GPIO155__FUNC_MIPI_M_SCLK (MTK_PIN_NO(155) | 1)</div><div class='add'>+#define PINMUX_GPIO155__FUNC_UCTS2 (MTK_PIN_NO(155) | 4)</div><div class='add'>+#define PINMUX_GPIO155__FUNC_TP_UTXD_CONSYS_VCORE (MTK_PIN_NO(155) | 6)</div><div class='add'>+#define PINMUX_GPIO155__FUNC_DBG_MON_A6 (MTK_PIN_NO(155) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0)</div><div class='add'>+#define PINMUX_GPIO156__FUNC_MIPI_M_SDATA (MTK_PIN_NO(156) | 1)</div><div class='add'>+#define PINMUX_GPIO156__FUNC_URTS2 (MTK_PIN_NO(156) | 4)</div><div class='add'>+#define PINMUX_GPIO156__FUNC_TP_URXD_CONSYS_VCORE (MTK_PIN_NO(156) | 6)</div><div class='add'>+#define PINMUX_GPIO156__FUNC_DBG_MON_A7 (MTK_PIN_NO(156) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0)</div><div class='add'>+#define PINMUX_GPIO157__FUNC_BPI_BUS8 (MTK_PIN_NO(157) | 1)</div><div class='add'>+#define PINMUX_GPIO157__FUNC_UTXD2 (MTK_PIN_NO(157) | 4)</div><div class='add'>+#define PINMUX_GPIO157__FUNC_CLKM0_A (MTK_PIN_NO(157) | 5)</div><div class='add'>+#define PINMUX_GPIO157__FUNC_SSPM_URXD_AO_VCORE (MTK_PIN_NO(157) | 6)</div><div class='add'>+#define PINMUX_GPIO157__FUNC_DBG_MON_A16 (MTK_PIN_NO(157) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0)</div><div class='add'>+#define PINMUX_GPIO158__FUNC_BPI_BUS9 (MTK_PIN_NO(158) | 1)</div><div class='add'>+#define PINMUX_GPIO158__FUNC_URXD2 (MTK_PIN_NO(158) | 4)</div><div class='add'>+#define PINMUX_GPIO158__FUNC_CLKM1_A (MTK_PIN_NO(158) | 5)</div><div class='add'>+#define PINMUX_GPIO158__FUNC_TP_UTXD1_VCORE (MTK_PIN_NO(158) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0)</div><div class='add'>+#define PINMUX_GPIO159__FUNC_BPI_BUS10 (MTK_PIN_NO(159) | 1)</div><div class='add'>+#define PINMUX_GPIO159__FUNC_MD_INT0 (MTK_PIN_NO(159) | 2)</div><div class='add'>+#define PINMUX_GPIO159__FUNC_SRCLKENAI1 (MTK_PIN_NO(159) | 3)</div><div class='add'>+#define PINMUX_GPIO159__FUNC_CLKM2_A (MTK_PIN_NO(159) | 5)</div><div class='add'>+#define PINMUX_GPIO159__FUNC_TP_URXD1_VCORE (MTK_PIN_NO(159) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0)</div><div class='add'>+#define PINMUX_GPIO160__FUNC_UTXD0 (MTK_PIN_NO(160) | 1)</div><div class='add'>+#define PINMUX_GPIO160__FUNC_MD_UTXD1 (MTK_PIN_NO(160) | 2)</div><div class='add'>+#define PINMUX_GPIO160__FUNC_MBISTREADEN_TRIGGER (MTK_PIN_NO(160) | 5)</div><div class='add'>+#define PINMUX_GPIO160__FUNC_CONN_BG_GPS_MCU_DBG_UART_TXD (MTK_PIN_NO(160) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0)</div><div class='add'>+#define PINMUX_GPIO161__FUNC_URXD0 (MTK_PIN_NO(161) | 1)</div><div class='add'>+#define PINMUX_GPIO161__FUNC_MD_URXD1 (MTK_PIN_NO(161) | 2)</div><div class='add'>+#define PINMUX_GPIO161__FUNC_MBISTWRITEEN_TRIGGER (MTK_PIN_NO(161) | 5)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0)</div><div class='add'>+#define PINMUX_GPIO162__FUNC_UTXD1 (MTK_PIN_NO(162) | 1)</div><div class='add'>+#define PINMUX_GPIO162__FUNC_MD_UTXD0 (MTK_PIN_NO(162) | 2)</div><div class='add'>+#define PINMUX_GPIO162__FUNC_TP_UTXD1_VLP (MTK_PIN_NO(162) | 3)</div><div class='add'>+#define PINMUX_GPIO162__FUNC_ADSP_UTXD0 (MTK_PIN_NO(162) | 4)</div><div class='add'>+#define PINMUX_GPIO162__FUNC_SSPM_UTXD_AO_VLP (MTK_PIN_NO(162) | 5)</div><div class='add'>+#define PINMUX_GPIO162__FUNC_HFRP_UTXD1 (MTK_PIN_NO(162) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0)</div><div class='add'>+#define PINMUX_GPIO163__FUNC_URXD1 (MTK_PIN_NO(163) | 1)</div><div class='add'>+#define PINMUX_GPIO163__FUNC_MD_URXD0 (MTK_PIN_NO(163) | 2)</div><div class='add'>+#define PINMUX_GPIO163__FUNC_TP_URXD1_VLP (MTK_PIN_NO(163) | 3)</div><div class='add'>+#define PINMUX_GPIO163__FUNC_ADSP_URXD0 (MTK_PIN_NO(163) | 4)</div><div class='add'>+#define PINMUX_GPIO163__FUNC_SSPM_URXD_AO_VLP (MTK_PIN_NO(163) | 5)</div><div class='add'>+#define PINMUX_GPIO163__FUNC_HFRP_URXD1 (MTK_PIN_NO(163) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0)</div><div class='add'>+#define PINMUX_GPIO164__FUNC_SCP_SCL0 (MTK_PIN_NO(164) | 1)</div><div class='add'>+#define PINMUX_GPIO164__FUNC_TP_GPIO0_AO (MTK_PIN_NO(164) | 6)</div><div class='add'>+#define PINMUX_GPIO164__FUNC_DBG_MON_A22 (MTK_PIN_NO(164) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0)</div><div class='add'>+#define PINMUX_GPIO165__FUNC_SCP_SDA0 (MTK_PIN_NO(165) | 1)</div><div class='add'>+#define PINMUX_GPIO165__FUNC_TP_GPIO1_AO (MTK_PIN_NO(165) | 6)</div><div class='add'>+#define PINMUX_GPIO165__FUNC_DBG_MON_A23 (MTK_PIN_NO(165) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0)</div><div class='add'>+#define PINMUX_GPIO166__FUNC_SCP_SCL2 (MTK_PIN_NO(166) | 1)</div><div class='add'>+#define PINMUX_GPIO166__FUNC_TP_GPIO2_AO (MTK_PIN_NO(166) | 6)</div><div class='add'>+#define PINMUX_GPIO166__FUNC_DBG_MON_A24 (MTK_PIN_NO(166) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0)</div><div class='add'>+#define PINMUX_GPIO167__FUNC_SCP_SDA2 (MTK_PIN_NO(167) | 1)</div><div class='add'>+#define PINMUX_GPIO167__FUNC_TP_GPIO3_AO (MTK_PIN_NO(167) | 6)</div><div class='add'>+#define PINMUX_GPIO167__FUNC_DBG_MON_A25 (MTK_PIN_NO(167) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0)</div><div class='add'>+#define PINMUX_GPIO168__FUNC_SCP_SPI2_CK (MTK_PIN_NO(168) | 1)</div><div class='add'>+#define PINMUX_GPIO168__FUNC_SPI2_B_CLK (MTK_PIN_NO(168) | 2)</div><div class='add'>+#define PINMUX_GPIO168__FUNC_PWM_VLP (MTK_PIN_NO(168) | 3)</div><div class='add'>+#define PINMUX_GPIO168__FUNC_SCP_SCL2 (MTK_PIN_NO(168) | 4)</div><div class='add'>+#define PINMUX_GPIO168__FUNC_DBG_MON_A26 (MTK_PIN_NO(168) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0)</div><div class='add'>+#define PINMUX_GPIO169__FUNC_SCP_SPI2_CS (MTK_PIN_NO(169) | 1)</div><div class='add'>+#define PINMUX_GPIO169__FUNC_SPI2_B_CSB (MTK_PIN_NO(169) | 2)</div><div class='add'>+#define PINMUX_GPIO169__FUNC_DBG_MON_A27 (MTK_PIN_NO(169) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0)</div><div class='add'>+#define PINMUX_GPIO170__FUNC_SCP_SPI2_MO (MTK_PIN_NO(170) | 1)</div><div class='add'>+#define PINMUX_GPIO170__FUNC_SPI2_B_MO (MTK_PIN_NO(170) | 2)</div><div class='add'>+#define PINMUX_GPIO170__FUNC_SCP_SDA2 (MTK_PIN_NO(170) | 4)</div><div class='add'>+#define PINMUX_GPIO170__FUNC_DBG_MON_A28 (MTK_PIN_NO(170) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0)</div><div class='add'>+#define PINMUX_GPIO171__FUNC_SCP_SPI2_MI (MTK_PIN_NO(171) | 1)</div><div class='add'>+#define PINMUX_GPIO171__FUNC_SPI2_B_MI (MTK_PIN_NO(171) | 2)</div><div class='add'>+#define PINMUX_GPIO171__FUNC_DBG_MON_A29 (MTK_PIN_NO(171) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0)</div><div class='add'>+#define PINMUX_GPIO172__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(172) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0)</div><div class='add'>+#define PINMUX_GPIO173__FUNC_CMFLASH3 (MTK_PIN_NO(173) | 1)</div><div class='add'>+#define PINMUX_GPIO173__FUNC_PWM_3 (MTK_PIN_NO(173) | 2)</div><div class='add'>+#define PINMUX_GPIO173__FUNC_MD_GPS_L5_BLANK (MTK_PIN_NO(173) | 3)</div><div class='add'>+#define PINMUX_GPIO173__FUNC_CLKM1_A (MTK_PIN_NO(173) | 4)</div><div class='add'>+#define PINMUX_GPIO173__FUNC_DBG_MON_A31 (MTK_PIN_NO(173) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0)</div><div class='add'>+#define PINMUX_GPIO174__FUNC_CMFLASH0 (MTK_PIN_NO(174) | 1)</div><div class='add'>+#define PINMUX_GPIO174__FUNC_PWM_0 (MTK_PIN_NO(174) | 2)</div><div class='add'>+#define PINMUX_GPIO174__FUNC_VBUSVALID_1P (MTK_PIN_NO(174) | 3)</div><div class='add'>+#define PINMUX_GPIO174__FUNC_MD32_2_RXD (MTK_PIN_NO(174) | 4)</div><div class='add'>+#define PINMUX_GPIO174__FUNC_DISP_PWM3 (MTK_PIN_NO(174) | 5)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0)</div><div class='add'>+#define PINMUX_GPIO175__FUNC_CMFLASH1 (MTK_PIN_NO(175) | 1)</div><div class='add'>+#define PINMUX_GPIO175__FUNC_PWM_1 (MTK_PIN_NO(175) | 2)</div><div class='add'>+#define PINMUX_GPIO175__FUNC_EDP_TX_HPD (MTK_PIN_NO(175) | 3)</div><div class='add'>+#define PINMUX_GPIO175__FUNC_MD32_2_TXD (MTK_PIN_NO(175) | 4)</div><div class='add'>+#define PINMUX_GPIO175__FUNC_DISP_PWM4 (MTK_PIN_NO(175) | 5)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0)</div><div class='add'>+#define PINMUX_GPIO176__FUNC_SCL5 (MTK_PIN_NO(176) | 1)</div><div class='add'>+#define PINMUX_GPIO176__FUNC_LCM3_RST (MTK_PIN_NO(176) | 2)</div><div class='add'>+#define PINMUX_GPIO176__FUNC_MD_URXD1_CONN (MTK_PIN_NO(176) | 4)</div><div class='add'>+#define PINMUX_GPIO176__FUNC_TP_UTXD_GNSS_VCORE (MTK_PIN_NO(176) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0)</div><div class='add'>+#define PINMUX_GPIO177__FUNC_SDA5 (MTK_PIN_NO(177) | 1)</div><div class='add'>+#define PINMUX_GPIO177__FUNC_DSI3_TE (MTK_PIN_NO(177) | 2)</div><div class='add'>+#define PINMUX_GPIO177__FUNC_MD_UTXD1_CONN (MTK_PIN_NO(177) | 4)</div><div class='add'>+#define PINMUX_GPIO177__FUNC_TP_URXD_GNSS_VCORE (MTK_PIN_NO(177) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0)</div><div class='add'>+#define PINMUX_GPIO178__FUNC_DMIC_CLK (MTK_PIN_NO(178) | 1)</div><div class='add'>+#define PINMUX_GPIO178__FUNC_SCP_DMIC_CLK (MTK_PIN_NO(178) | 2)</div><div class='add'>+#define PINMUX_GPIO178__FUNC_SRCLKENAI0 (MTK_PIN_NO(178) | 3)</div><div class='add'>+#define PINMUX_GPIO178__FUNC_CLKM2_B (MTK_PIN_NO(178) | 4)</div><div class='add'>+#define PINMUX_GPIO178__FUNC_TP_GPIO7_AO (MTK_PIN_NO(178) | 5)</div><div class='add'>+#define PINMUX_GPIO178__FUNC_SPU1_UTX (MTK_PIN_NO(178) | 6)</div><div class='add'>+#define PINMUX_GPIO178__FUNC_DAP_SONIC_SWCK (MTK_PIN_NO(178) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0)</div><div class='add'>+#define PINMUX_GPIO179__FUNC_DMIC_DAT (MTK_PIN_NO(179) | 1)</div><div class='add'>+#define PINMUX_GPIO179__FUNC_SCP_DMIC_DAT (MTK_PIN_NO(179) | 2)</div><div class='add'>+#define PINMUX_GPIO179__FUNC_SRCLKENAI1 (MTK_PIN_NO(179) | 3)</div><div class='add'>+#define PINMUX_GPIO179__FUNC_CLKM3_B (MTK_PIN_NO(179) | 4)</div><div class='add'>+#define PINMUX_GPIO179__FUNC_TP_GPIO8_AO (MTK_PIN_NO(179) | 5)</div><div class='add'>+#define PINMUX_GPIO179__FUNC_SPU1_URX (MTK_PIN_NO(179) | 6)</div><div class='add'>+#define PINMUX_GPIO179__FUNC_DAP_SONIC_SWD (MTK_PIN_NO(179) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO180__FUNC_GPIO180 (MTK_PIN_NO(180) | 0)</div><div class='add'>+#define PINMUX_GPIO180__FUNC_IDDIG_1P (MTK_PIN_NO(180) | 1)</div><div class='add'>+#define PINMUX_GPIO180__FUNC_CMVREF0 (MTK_PIN_NO(180) | 2)</div><div class='add'>+#define PINMUX_GPIO180__FUNC_GPS_PPS1 (MTK_PIN_NO(180) | 3)</div><div class='add'>+#define PINMUX_GPIO180__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(180) | 4)</div><div class='add'>+#define PINMUX_GPIO180__FUNC_DISP_PWM1 (MTK_PIN_NO(180) | 5)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO181__FUNC_GPIO181 (MTK_PIN_NO(181) | 0)</div><div class='add'>+#define PINMUX_GPIO181__FUNC_USB_DRVVBUS_1P (MTK_PIN_NO(181) | 1)</div><div class='add'>+#define PINMUX_GPIO181__FUNC_CMVREF1 (MTK_PIN_NO(181) | 2)</div><div class='add'>+#define PINMUX_GPIO181__FUNC_MFG_EB_JTAG_TRSTN (MTK_PIN_NO(181) | 3)</div><div class='add'>+#define PINMUX_GPIO181__FUNC_ADSP_JTAG1_TRSTN (MTK_PIN_NO(181) | 4)</div><div class='add'>+#define PINMUX_GPIO181__FUNC_HFRP_JTAG1_TRSTN (MTK_PIN_NO(181) | 5)</div><div class='add'>+#define PINMUX_GPIO181__FUNC_SPU1_NTRST (MTK_PIN_NO(181) | 6)</div><div class='add'>+#define PINMUX_GPIO181__FUNC_CONN_BG_GPS_MCU_TRST_B (MTK_PIN_NO(181) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO182__FUNC_GPIO182 (MTK_PIN_NO(182) | 0)</div><div class='add'>+#define PINMUX_GPIO182__FUNC_SCL11 (MTK_PIN_NO(182) | 1)</div><div class='add'>+#define PINMUX_GPIO182__FUNC_CMVREF2 (MTK_PIN_NO(182) | 2)</div><div class='add'>+#define PINMUX_GPIO182__FUNC_MFG_EB_JTAG_TCK (MTK_PIN_NO(182) | 3)</div><div class='add'>+#define PINMUX_GPIO182__FUNC_ADSP_JTAG1_TCK (MTK_PIN_NO(182) | 4)</div><div class='add'>+#define PINMUX_GPIO182__FUNC_HFRP_JTAG1_TCK (MTK_PIN_NO(182) | 5)</div><div class='add'>+#define PINMUX_GPIO182__FUNC_SPU1_TCK (MTK_PIN_NO(182) | 6)</div><div class='add'>+#define PINMUX_GPIO182__FUNC_CONN_BG_GPS_MCU_TCK (MTK_PIN_NO(182) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO183__FUNC_GPIO183 (MTK_PIN_NO(183) | 0)</div><div class='add'>+#define PINMUX_GPIO183__FUNC_SDA11 (MTK_PIN_NO(183) | 1)</div><div class='add'>+#define PINMUX_GPIO183__FUNC_CMVREF3 (MTK_PIN_NO(183) | 2)</div><div class='add'>+#define PINMUX_GPIO183__FUNC_MFG_EB_JTAG_TMS (MTK_PIN_NO(183) | 3)</div><div class='add'>+#define PINMUX_GPIO183__FUNC_ADSP_JTAG1_TMS (MTK_PIN_NO(183) | 4)</div><div class='add'>+#define PINMUX_GPIO183__FUNC_HFRP_JTAG1_TMS (MTK_PIN_NO(183) | 5)</div><div class='add'>+#define PINMUX_GPIO183__FUNC_SPU1_TMS (MTK_PIN_NO(183) | 6)</div><div class='add'>+#define PINMUX_GPIO183__FUNC_CONN_BG_GPS_MCU_TMS (MTK_PIN_NO(183) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO184__FUNC_GPIO184 (MTK_PIN_NO(184) | 0)</div><div class='add'>+#define PINMUX_GPIO184__FUNC_SCL12 (MTK_PIN_NO(184) | 1)</div><div class='add'>+#define PINMUX_GPIO184__FUNC_CMVREF4 (MTK_PIN_NO(184) | 2)</div><div class='add'>+#define PINMUX_GPIO184__FUNC_MFG_EB_JTAG_TDO (MTK_PIN_NO(184) | 3)</div><div class='add'>+#define PINMUX_GPIO184__FUNC_ADSP_JTAG1_TDO (MTK_PIN_NO(184) | 4)</div><div class='add'>+#define PINMUX_GPIO184__FUNC_HFRP_JTAG1_TDO (MTK_PIN_NO(184) | 5)</div><div class='add'>+#define PINMUX_GPIO184__FUNC_SPU1_TDO (MTK_PIN_NO(184) | 6)</div><div class='add'>+#define PINMUX_GPIO184__FUNC_CONN_BG_GPS_MCU_TDO (MTK_PIN_NO(184) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO185__FUNC_GPIO185 (MTK_PIN_NO(185) | 0)</div><div class='add'>+#define PINMUX_GPIO185__FUNC_SDA12 (MTK_PIN_NO(185) | 1)</div><div class='add'>+#define PINMUX_GPIO185__FUNC_CMVREF5 (MTK_PIN_NO(185) | 2)</div><div class='add'>+#define PINMUX_GPIO185__FUNC_MFG_EB_JTAG_TDI (MTK_PIN_NO(185) | 3)</div><div class='add'>+#define PINMUX_GPIO185__FUNC_ADSP_JTAG1_TDI (MTK_PIN_NO(185) | 4)</div><div class='add'>+#define PINMUX_GPIO185__FUNC_HFRP_JTAG1_TDI (MTK_PIN_NO(185) | 5)</div><div class='add'>+#define PINMUX_GPIO185__FUNC_SPU1_TDI (MTK_PIN_NO(185) | 6)</div><div class='add'>+#define PINMUX_GPIO185__FUNC_CONN_BG_GPS_MCU_TDI (MTK_PIN_NO(185) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO186__FUNC_GPIO186 (MTK_PIN_NO(186) | 0)</div><div class='add'>+#define PINMUX_GPIO186__FUNC_MD_GPS_L1_BLANK (MTK_PIN_NO(186) | 1)</div><div class='add'>+#define PINMUX_GPIO186__FUNC_PMSR_SMAP (MTK_PIN_NO(186) | 2)</div><div class='add'>+#define PINMUX_GPIO186__FUNC_TP_GPIO2_AO (MTK_PIN_NO(186) | 3)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO187__FUNC_GPIO187 (MTK_PIN_NO(187) | 0)</div><div class='add'>+#define PINMUX_GPIO187__FUNC_MD_GPS_L5_BLANK (MTK_PIN_NO(187) | 1)</div><div class='add'>+#define PINMUX_GPIO187__FUNC_TP_GPIO4_AO (MTK_PIN_NO(187) | 3)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO188__FUNC_GPIO188 (MTK_PIN_NO(188) | 0)</div><div class='add'>+#define PINMUX_GPIO188__FUNC_SCL2 (MTK_PIN_NO(188) | 1)</div><div class='add'>+#define PINMUX_GPIO188__FUNC_SCP_SCL8 (MTK_PIN_NO(188) | 2)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO189__FUNC_GPIO189 (MTK_PIN_NO(189) | 0)</div><div class='add'>+#define PINMUX_GPIO189__FUNC_SDA2 (MTK_PIN_NO(189) | 1)</div><div class='add'>+#define PINMUX_GPIO189__FUNC_SCP_SDA8 (MTK_PIN_NO(189) | 2)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO190__FUNC_GPIO190 (MTK_PIN_NO(190) | 0)</div><div class='add'>+#define PINMUX_GPIO190__FUNC_SCL4 (MTK_PIN_NO(190) | 1)</div><div class='add'>+#define PINMUX_GPIO190__FUNC_SCP_SCL9 (MTK_PIN_NO(190) | 2)</div><div class='add'>+#define PINMUX_GPIO190__FUNC_UDI_TDI_6 (MTK_PIN_NO(190) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO191__FUNC_GPIO191 (MTK_PIN_NO(191) | 0)</div><div class='add'>+#define PINMUX_GPIO191__FUNC_SDA4 (MTK_PIN_NO(191) | 1)</div><div class='add'>+#define PINMUX_GPIO191__FUNC_SCP_SDA9 (MTK_PIN_NO(191) | 2)</div><div class='add'>+#define PINMUX_GPIO191__FUNC_UDI_TDI_7 (MTK_PIN_NO(191) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO192__FUNC_GPIO192 (MTK_PIN_NO(192) | 0)</div><div class='add'>+#define PINMUX_GPIO192__FUNC_CMMCLK2 (MTK_PIN_NO(192) | 1)</div><div class='add'>+#define PINMUX_GPIO192__FUNC_MD32_3_RXD (MTK_PIN_NO(192) | 4)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO193__FUNC_GPIO193 (MTK_PIN_NO(193) | 0)</div><div class='add'>+#define PINMUX_GPIO193__FUNC_CLKM0_B (MTK_PIN_NO(193) | 3)</div><div class='add'>+#define PINMUX_GPIO193__FUNC_MD32_3_TXD (MTK_PIN_NO(193) | 4)</div><div class='add'>+#define PINMUX_GPIO193__FUNC_UDI_TDO_7 (MTK_PIN_NO(193) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO194__FUNC_GPIO194 (MTK_PIN_NO(194) | 0)</div><div class='add'>+#define PINMUX_GPIO194__FUNC_SCL7 (MTK_PIN_NO(194) | 1)</div><div class='add'>+#define PINMUX_GPIO194__FUNC_MD32_3_GPIO0 (MTK_PIN_NO(194) | 2)</div><div class='add'>+#define PINMUX_GPIO194__FUNC_CLKM2_B (MTK_PIN_NO(194) | 3)</div><div class='add'>+#define PINMUX_GPIO194__FUNC_UDI_TDI_2 (MTK_PIN_NO(194) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO195__FUNC_GPIO195 (MTK_PIN_NO(195) | 0)</div><div class='add'>+#define PINMUX_GPIO195__FUNC_SDA7 (MTK_PIN_NO(195) | 1)</div><div class='add'>+#define PINMUX_GPIO195__FUNC_CLKM3_B (MTK_PIN_NO(195) | 3)</div><div class='add'>+#define PINMUX_GPIO195__FUNC_UDI_TDI_3 (MTK_PIN_NO(195) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO196__FUNC_GPIO196 (MTK_PIN_NO(196) | 0)</div><div class='add'>+#define PINMUX_GPIO196__FUNC_CMMCLK3 (MTK_PIN_NO(196) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO197__FUNC_GPIO197 (MTK_PIN_NO(197) | 0)</div><div class='add'>+#define PINMUX_GPIO197__FUNC_CLKM1_B (MTK_PIN_NO(197) | 3)</div><div class='add'>+#define PINMUX_GPIO197__FUNC_UDI_TDI_1 (MTK_PIN_NO(197) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO198__FUNC_GPIO198 (MTK_PIN_NO(198) | 0)</div><div class='add'>+#define PINMUX_GPIO198__FUNC_SCL8 (MTK_PIN_NO(198) | 1)</div><div class='add'>+#define PINMUX_GPIO198__FUNC_UDI_TDI_4 (MTK_PIN_NO(198) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO199__FUNC_GPIO199 (MTK_PIN_NO(199) | 0)</div><div class='add'>+#define PINMUX_GPIO199__FUNC_SDA8 (MTK_PIN_NO(199) | 1)</div><div class='add'>+#define PINMUX_GPIO199__FUNC_UDI_TDI_5 (MTK_PIN_NO(199) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO200__FUNC_GPIO200 (MTK_PIN_NO(200) | 0)</div><div class='add'>+#define PINMUX_GPIO200__FUNC_SCL1 (MTK_PIN_NO(200) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO201__FUNC_GPIO201 (MTK_PIN_NO(201) | 0)</div><div class='add'>+#define PINMUX_GPIO201__FUNC_SDA1 (MTK_PIN_NO(201) | 1)</div><div class='add'>+#define PINMUX_GPIO201__FUNC_TSFDC_BG_COMP (MTK_PIN_NO(201) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO202__FUNC_GPIO202 (MTK_PIN_NO(202) | 0)</div><div class='add'>+#define PINMUX_GPIO202__FUNC_SCL9 (MTK_PIN_NO(202) | 1)</div><div class='add'>+#define PINMUX_GPIO202__FUNC_SCP_SCL7 (MTK_PIN_NO(202) | 2)</div><div class='add'>+#define PINMUX_GPIO202__FUNC_TP_GPIO15_AO (MTK_PIN_NO(202) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO203__FUNC_GPIO203 (MTK_PIN_NO(203) | 0)</div><div class='add'>+#define PINMUX_GPIO203__FUNC_SDA9 (MTK_PIN_NO(203) | 1)</div><div class='add'>+#define PINMUX_GPIO203__FUNC_SCP_SDA7 (MTK_PIN_NO(203) | 2)</div><div class='add'>+#define PINMUX_GPIO203__FUNC_TP_GPIO9_AO (MTK_PIN_NO(203) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO204__FUNC_GPIO204 (MTK_PIN_NO(204) | 0)</div><div class='add'>+#define PINMUX_GPIO204__FUNC_SCL13 (MTK_PIN_NO(204) | 1)</div><div class='add'>+#define PINMUX_GPIO204__FUNC_CMVREF6 (MTK_PIN_NO(204) | 2)</div><div class='add'>+#define PINMUX_GPIO204__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(204) | 3)</div><div class='add'>+#define PINMUX_GPIO204__FUNC_CLKM2_B (MTK_PIN_NO(204) | 5)</div><div class='add'>+#define PINMUX_GPIO204__FUNC_TP_GPIO12_AO (MTK_PIN_NO(204) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO205__FUNC_GPIO205 (MTK_PIN_NO(205) | 0)</div><div class='add'>+#define PINMUX_GPIO205__FUNC_SDA13 (MTK_PIN_NO(205) | 1)</div><div class='add'>+#define PINMUX_GPIO205__FUNC_CMVREF7 (MTK_PIN_NO(205) | 2)</div><div class='add'>+#define PINMUX_GPIO205__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(205) | 3)</div><div class='add'>+#define PINMUX_GPIO205__FUNC_CLKM3_B (MTK_PIN_NO(205) | 5)</div><div class='add'>+#define PINMUX_GPIO205__FUNC_TP_GPIO13_AO (MTK_PIN_NO(205) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO206__FUNC_GPIO206 (MTK_PIN_NO(206) | 0)</div><div class='add'>+#define PINMUX_GPIO206__FUNC_MD32_2_GPIO0 (MTK_PIN_NO(206) | 2)</div><div class='add'>+#define PINMUX_GPIO206__FUNC_VBUSVALID (MTK_PIN_NO(206) | 5)</div><div class='add'>+#define PINMUX_GPIO206__FUNC_UDI_TDO_3 (MTK_PIN_NO(206) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO207__FUNC_GPIO207 (MTK_PIN_NO(207) | 0)</div><div class='add'>+#define PINMUX_GPIO207__FUNC_PCIE_WAKEN_2P (MTK_PIN_NO(207) | 1)</div><div class='add'>+#define PINMUX_GPIO207__FUNC_PMSR_SMAP_MAX (MTK_PIN_NO(207) | 2)</div><div class='add'>+#define PINMUX_GPIO207__FUNC_FMI2S_A_BCK (MTK_PIN_NO(207) | 4)</div><div class='add'>+#define PINMUX_GPIO207__FUNC_UDI_TDO_4 (MTK_PIN_NO(207) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO208__FUNC_GPIO208 (MTK_PIN_NO(208) | 0)</div><div class='add'>+#define PINMUX_GPIO208__FUNC_PCIE_CLKREQN_2P (MTK_PIN_NO(208) | 1)</div><div class='add'>+#define PINMUX_GPIO208__FUNC_PMSR_SMAP_MAX_W (MTK_PIN_NO(208) | 2)</div><div class='add'>+#define PINMUX_GPIO208__FUNC_FMI2S_A_LRCK (MTK_PIN_NO(208) | 4)</div><div class='add'>+#define PINMUX_GPIO208__FUNC_CLKM0_B (MTK_PIN_NO(208) | 5)</div><div class='add'>+#define PINMUX_GPIO208__FUNC_UDI_TDO_5 (MTK_PIN_NO(208) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO209__FUNC_GPIO209 (MTK_PIN_NO(209) | 0)</div><div class='add'>+#define PINMUX_GPIO209__FUNC_PCIE_PERSTN_2P (MTK_PIN_NO(209) | 1)</div><div class='add'>+#define PINMUX_GPIO209__FUNC_PMSR_SMAP (MTK_PIN_NO(209) | 2)</div><div class='add'>+#define PINMUX_GPIO209__FUNC_FMI2S_A_DI (MTK_PIN_NO(209) | 4)</div><div class='add'>+#define PINMUX_GPIO209__FUNC_CLKM1_B (MTK_PIN_NO(209) | 5)</div><div class='add'>+#define PINMUX_GPIO209__FUNC_UDI_TDO_6 (MTK_PIN_NO(209) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO210__FUNC_GPIO210 (MTK_PIN_NO(210) | 0)</div><div class='add'>+#define PINMUX_GPIO210__FUNC_CMMCLK4 (MTK_PIN_NO(210) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO211__FUNC_GPIO211 (MTK_PIN_NO(211) | 0)</div><div class='add'>+#define PINMUX_GPIO211__FUNC_CMMCLK5 (MTK_PIN_NO(211) | 1)</div><div class='add'>+#define PINMUX_GPIO211__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(211) | 2)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO212__FUNC_GPIO212 (MTK_PIN_NO(212) | 0)</div><div class='add'>+#define PINMUX_GPIO212__FUNC_CMMCLK6 (MTK_PIN_NO(212) | 1)</div><div class='add'>+#define PINMUX_GPIO212__FUNC_TP_GPIO10_AO (MTK_PIN_NO(212) | 2)</div><div class='add'>+#define PINMUX_GPIO212__FUNC_IDDIG (MTK_PIN_NO(212) | 5)</div><div class='add'>+#define PINMUX_GPIO212__FUNC_UDI_TDO_1 (MTK_PIN_NO(212) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO213__FUNC_GPIO213 (MTK_PIN_NO(213) | 0)</div><div class='add'>+#define PINMUX_GPIO213__FUNC_CMMCLK7 (MTK_PIN_NO(213) | 1)</div><div class='add'>+#define PINMUX_GPIO213__FUNC_TP_GPIO11_AO (MTK_PIN_NO(213) | 2)</div><div class='add'>+#define PINMUX_GPIO213__FUNC_USB_DRVVBUS (MTK_PIN_NO(213) | 5)</div><div class='add'>+#define PINMUX_GPIO213__FUNC_UDI_TDO_2 (MTK_PIN_NO(213) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO214__FUNC_GPIO214 (MTK_PIN_NO(214) | 0)</div><div class='add'>+#define PINMUX_GPIO214__FUNC_SCP_SCL3 (MTK_PIN_NO(214) | 1)</div><div class='add'>+#define PINMUX_GPIO214__FUNC_SDA14_E1 (MTK_PIN_NO(214) | 2)</div><div class='add'>+#define PINMUX_GPIO214__FUNC_SCL14_E2 (MTK_PIN_NO(214) | 2)</div><div class='add'>+#define PINMUX_GPIO214__FUNC_GBE1_MDC (MTK_PIN_NO(214) | 6)</div><div class='add'>+#define PINMUX_GPIO214__FUNC_GBE0_MDC (MTK_PIN_NO(214) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO215__FUNC_GPIO215 (MTK_PIN_NO(215) | 0)</div><div class='add'>+#define PINMUX_GPIO215__FUNC_SCP_SDA3 (MTK_PIN_NO(215) | 1)</div><div class='add'>+#define PINMUX_GPIO215__FUNC_SCL14_E1 (MTK_PIN_NO(215) | 2)</div><div class='add'>+#define PINMUX_GPIO215__FUNC_SDA14_E2 (MTK_PIN_NO(215) | 2)</div><div class='add'>+#define PINMUX_GPIO215__FUNC_GBE1_MDIO (MTK_PIN_NO(215) | 6)</div><div class='add'>+#define PINMUX_GPIO215__FUNC_GBE0_MDIO (MTK_PIN_NO(215) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO216__FUNC_GPIO216 (MTK_PIN_NO(216) | 0)</div><div class='add'>+#define PINMUX_GPIO216__FUNC_GPS_PPS0 (MTK_PIN_NO(216) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO217__FUNC_GPIO217 (MTK_PIN_NO(217) | 0)</div><div class='add'>+#define PINMUX_GPIO217__FUNC_KPROW0 (MTK_PIN_NO(217) | 1)</div><div class='add'>+#define PINMUX_GPIO217__FUNC_TP_GPIO12_AO (MTK_PIN_NO(217) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO218__FUNC_GPIO218 (MTK_PIN_NO(218) | 0)</div><div class='add'>+#define PINMUX_GPIO218__FUNC_KPROW1 (MTK_PIN_NO(218) | 1)</div><div class='add'>+#define PINMUX_GPIO218__FUNC_SPI0_WP (MTK_PIN_NO(218) | 2)</div><div class='add'>+#define PINMUX_GPIO218__FUNC_MBISTREADEN_TRIGGER (MTK_PIN_NO(218) | 3)</div><div class='add'>+#define PINMUX_GPIO218__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(218) | 5)</div><div class='add'>+#define PINMUX_GPIO218__FUNC_TP_GPIO14_AO (MTK_PIN_NO(218) | 6)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO219__FUNC_GPIO219 (MTK_PIN_NO(219) | 0)</div><div class='add'>+#define PINMUX_GPIO219__FUNC_KPCOL1 (MTK_PIN_NO(219) | 1)</div><div class='add'>+#define PINMUX_GPIO219__FUNC_SPI0_HOLD (MTK_PIN_NO(219) | 2)</div><div class='add'>+#define PINMUX_GPIO219__FUNC_MBISTWRITEEN_TRIGGER (MTK_PIN_NO(219) | 3)</div><div class='add'>+#define PINMUX_GPIO219__FUNC_SPMI_M_TRIG_FLAG (MTK_PIN_NO(219) | 4)</div><div class='add'>+#define PINMUX_GPIO219__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(219) | 5)</div><div class='add'>+#define PINMUX_GPIO219__FUNC_SPM_JTAG_TRSTN_VLP (MTK_PIN_NO(219) | 6)</div><div class='add'>+#define PINMUX_GPIO219__FUNC_JTRSTN_SEL1 (MTK_PIN_NO(219) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO220__FUNC_GPIO220 (MTK_PIN_NO(220) | 0)</div><div class='add'>+#define PINMUX_GPIO220__FUNC_SPI0_CLK (MTK_PIN_NO(220) | 1)</div><div class='add'>+#define PINMUX_GPIO220__FUNC_SPM_JTAG_TCK_VLP (MTK_PIN_NO(220) | 6)</div><div class='add'>+#define PINMUX_GPIO220__FUNC_JTCK_SEL1 (MTK_PIN_NO(220) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO221__FUNC_GPIO221 (MTK_PIN_NO(221) | 0)</div><div class='add'>+#define PINMUX_GPIO221__FUNC_SPI0_CSB (MTK_PIN_NO(221) | 1)</div><div class='add'>+#define PINMUX_GPIO221__FUNC_SPM_JTAG_TMS_VLP (MTK_PIN_NO(221) | 6)</div><div class='add'>+#define PINMUX_GPIO221__FUNC_JTMS_SEL1 (MTK_PIN_NO(221) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO222__FUNC_GPIO222 (MTK_PIN_NO(222) | 0)</div><div class='add'>+#define PINMUX_GPIO222__FUNC_SPI0_MO (MTK_PIN_NO(222) | 1)</div><div class='add'>+#define PINMUX_GPIO222__FUNC_SCP_SCL7 (MTK_PIN_NO(222) | 2)</div><div class='add'>+#define PINMUX_GPIO222__FUNC_SPM_JTAG_TDO_VLP (MTK_PIN_NO(222) | 6)</div><div class='add'>+#define PINMUX_GPIO222__FUNC_JTDO_SEL1 (MTK_PIN_NO(222) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO223__FUNC_GPIO223 (MTK_PIN_NO(223) | 0)</div><div class='add'>+#define PINMUX_GPIO223__FUNC_SPI0_MI (MTK_PIN_NO(223) | 1)</div><div class='add'>+#define PINMUX_GPIO223__FUNC_SCP_SDA7 (MTK_PIN_NO(223) | 2)</div><div class='add'>+#define PINMUX_GPIO223__FUNC_SPM_JTAG_TDI_VLP (MTK_PIN_NO(223) | 6)</div><div class='add'>+#define PINMUX_GPIO223__FUNC_JTDI_SEL1 (MTK_PIN_NO(223) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO224__FUNC_GPIO224 (MTK_PIN_NO(224) | 0)</div><div class='add'>+#define PINMUX_GPIO224__FUNC_MSDC2_CLK (MTK_PIN_NO(224) | 1)</div><div class='add'>+#define PINMUX_GPIO224__FUNC_DMIC2_CLK (MTK_PIN_NO(224) | 2)</div><div class='add'>+#define PINMUX_GPIO224__FUNC_GBE0_AUX_PPS0 (MTK_PIN_NO(224) | 3)</div><div class='add'>+#define PINMUX_GPIO224__FUNC_GBE0_TXER (MTK_PIN_NO(224) | 4)</div><div class='add'>+#define PINMUX_GPIO224__FUNC_GBE1_TXER (MTK_PIN_NO(224) | 5)</div><div class='add'>+#define PINMUX_GPIO224__FUNC_GBE1_AUX_PPS0 (MTK_PIN_NO(224) | 6)</div><div class='add'>+#define PINMUX_GPIO224__FUNC_MD32_1_TXD (MTK_PIN_NO(224) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO225__FUNC_GPIO225 (MTK_PIN_NO(225) | 0)</div><div class='add'>+#define PINMUX_GPIO225__FUNC_MSDC2_CMD (MTK_PIN_NO(225) | 1)</div><div class='add'>+#define PINMUX_GPIO225__FUNC_DMIC2_DAT (MTK_PIN_NO(225) | 2)</div><div class='add'>+#define PINMUX_GPIO225__FUNC_GBE0_AUX_PPS1 (MTK_PIN_NO(225) | 3)</div><div class='add'>+#define PINMUX_GPIO225__FUNC_GBE0_RXER (MTK_PIN_NO(225) | 4)</div><div class='add'>+#define PINMUX_GPIO225__FUNC_GBE1_RXER (MTK_PIN_NO(225) | 5)</div><div class='add'>+#define PINMUX_GPIO225__FUNC_GBE1_AUX_PPS1 (MTK_PIN_NO(225) | 6)</div><div class='add'>+#define PINMUX_GPIO225__FUNC_MD32_1_RXD (MTK_PIN_NO(225) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO226__FUNC_GPIO226 (MTK_PIN_NO(226) | 0)</div><div class='add'>+#define PINMUX_GPIO226__FUNC_MSDC2_DAT0 (MTK_PIN_NO(226) | 1)</div><div class='add'>+#define PINMUX_GPIO226__FUNC_I2SIN3_BCK (MTK_PIN_NO(226) | 2)</div><div class='add'>+#define PINMUX_GPIO226__FUNC_GBE0_AUX_PPS2 (MTK_PIN_NO(226) | 3)</div><div class='add'>+#define PINMUX_GPIO226__FUNC_GBE0_COL (MTK_PIN_NO(226) | 4)</div><div class='add'>+#define PINMUX_GPIO226__FUNC_GBE1_COL (MTK_PIN_NO(226) | 5)</div><div class='add'>+#define PINMUX_GPIO226__FUNC_GBE1_AUX_PPS2 (MTK_PIN_NO(226) | 6)</div><div class='add'>+#define PINMUX_GPIO226__FUNC_GBE1_MDC (MTK_PIN_NO(226) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO227__FUNC_GPIO227 (MTK_PIN_NO(227) | 0)</div><div class='add'>+#define PINMUX_GPIO227__FUNC_MSDC2_DAT1 (MTK_PIN_NO(227) | 1)</div><div class='add'>+#define PINMUX_GPIO227__FUNC_I2SIN3_LRCK (MTK_PIN_NO(227) | 2)</div><div class='add'>+#define PINMUX_GPIO227__FUNC_GBE0_AUX_PPS3 (MTK_PIN_NO(227) | 3)</div><div class='add'>+#define PINMUX_GPIO227__FUNC_GBE0_INTR (MTK_PIN_NO(227) | 4)</div><div class='add'>+#define PINMUX_GPIO227__FUNC_GBE1_INTR (MTK_PIN_NO(227) | 5)</div><div class='add'>+#define PINMUX_GPIO227__FUNC_GBE1_AUX_PPS3 (MTK_PIN_NO(227) | 6)</div><div class='add'>+#define PINMUX_GPIO227__FUNC_GBE1_MDIO (MTK_PIN_NO(227) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO228__FUNC_GPIO228 (MTK_PIN_NO(228) | 0)</div><div class='add'>+#define PINMUX_GPIO228__FUNC_MSDC2_DAT2 (MTK_PIN_NO(228) | 1)</div><div class='add'>+#define PINMUX_GPIO228__FUNC_I2SIN3_DI (MTK_PIN_NO(228) | 2)</div><div class='add'>+#define PINMUX_GPIO228__FUNC_GBE0_MDC (MTK_PIN_NO(228) | 3)</div><div class='add'>+#define PINMUX_GPIO228__FUNC_GBE1_MDC (MTK_PIN_NO(228) | 4)</div><div class='add'>+#define PINMUX_GPIO228__FUNC_CONN_BG_GPS_MCU_AICE_TCKC (MTK_PIN_NO(228) | 5)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO229__FUNC_GPIO229 (MTK_PIN_NO(229) | 0)</div><div class='add'>+#define PINMUX_GPIO229__FUNC_MSDC2_DAT3 (MTK_PIN_NO(229) | 1)</div><div class='add'>+#define PINMUX_GPIO229__FUNC_I2SOUT3_DO (MTK_PIN_NO(229) | 2)</div><div class='add'>+#define PINMUX_GPIO229__FUNC_GBE0_MDIO (MTK_PIN_NO(229) | 3)</div><div class='add'>+#define PINMUX_GPIO229__FUNC_GBE1_MDIO (MTK_PIN_NO(229) | 4)</div><div class='add'>+#define PINMUX_GPIO229__FUNC_CONN_BG_GPS_MCU_AICE_TMSC (MTK_PIN_NO(229) | 5)</div><div class='add'>+#define PINMUX_GPIO229__FUNC_AVB_CLK2 (MTK_PIN_NO(229) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO230__FUNC_GPIO230 (MTK_PIN_NO(230) | 0)</div><div class='add'>+#define PINMUX_GPIO230__FUNC_CONN_TOP_CLK (MTK_PIN_NO(230) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO231__FUNC_GPIO231 (MTK_PIN_NO(231) | 0)</div><div class='add'>+#define PINMUX_GPIO231__FUNC_CONN_TOP_DATA (MTK_PIN_NO(231) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO232__FUNC_GPIO232 (MTK_PIN_NO(232) | 0)</div><div class='add'>+#define PINMUX_GPIO232__FUNC_CONN_HRST_B (MTK_PIN_NO(232) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO233__FUNC_GPIO233 (MTK_PIN_NO(233) | 0)</div><div class='add'>+#define PINMUX_GPIO233__FUNC_I2SIN0_BCK (MTK_PIN_NO(233) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO234__FUNC_GPIO234 (MTK_PIN_NO(234) | 0)</div><div class='add'>+#define PINMUX_GPIO234__FUNC_I2SIN0_LRCK (MTK_PIN_NO(234) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO235__FUNC_GPIO235 (MTK_PIN_NO(235) | 0)</div><div class='add'>+#define PINMUX_GPIO235__FUNC_I2SIN0_DI (MTK_PIN_NO(235) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO236__FUNC_GPIO236 (MTK_PIN_NO(236) | 0)</div><div class='add'>+#define PINMUX_GPIO236__FUNC_I2SOUT0_DO (MTK_PIN_NO(236) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO237__FUNC_GPIO237 (MTK_PIN_NO(237) | 0)</div><div class='add'>+#define PINMUX_GPIO237__FUNC_CONN_UARTHUB_UART_TX (MTK_PIN_NO(237) | 1)</div><div class='add'>+#define PINMUX_GPIO237__FUNC_UTXD3 (MTK_PIN_NO(237) | 3)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO238__FUNC_GPIO238 (MTK_PIN_NO(238) | 0)</div><div class='add'>+#define PINMUX_GPIO238__FUNC_CONN_UARTHUB_UART_RX (MTK_PIN_NO(238) | 1)</div><div class='add'>+#define PINMUX_GPIO238__FUNC_URXD3 (MTK_PIN_NO(238) | 3)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO239__FUNC_GPIO239 (MTK_PIN_NO(239) | 0)</div><div class='add'>+#define PINMUX_GPIO239__FUNC_TP_UTXD_CONSYS_VLP (MTK_PIN_NO(239) | 1)</div><div class='add'>+#define PINMUX_GPIO239__FUNC_TP_URXD_CONSYS_VLP (MTK_PIN_NO(239) | 2)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO240__FUNC_GPIO240 (MTK_PIN_NO(240) | 0)</div><div class='add'>+#define PINMUX_GPIO240__FUNC_TP_URXD_CONSYS_VLP (MTK_PIN_NO(240) | 1)</div><div class='add'>+#define PINMUX_GPIO240__FUNC_TP_UTXD_CONSYS_VLP (MTK_PIN_NO(240) | 2)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO241__FUNC_GPIO241 (MTK_PIN_NO(241) | 0)</div><div class='add'>+#define PINMUX_GPIO241__FUNC_PCIE_PERSTN (MTK_PIN_NO(241) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO242__FUNC_GPIO242 (MTK_PIN_NO(242) | 0)</div><div class='add'>+#define PINMUX_GPIO242__FUNC_PCIE_WAKEN (MTK_PIN_NO(242) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO243__FUNC_GPIO243 (MTK_PIN_NO(243) | 0)</div><div class='add'>+#define PINMUX_GPIO243__FUNC_PCIE_CLKREQN (MTK_PIN_NO(243) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO244__FUNC_GPIO244 (MTK_PIN_NO(244) | 0)</div><div class='add'>+#define PINMUX_GPIO244__FUNC_CONN_RST (MTK_PIN_NO(244) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO245__FUNC_GPIO245 (MTK_PIN_NO(245) | 0)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO246__FUNC_GPIO246 (MTK_PIN_NO(246) | 0)</div><div class='add'>+#define PINMUX_GPIO246__FUNC_CONN_PTA_TXD0 (MTK_PIN_NO(246) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO247__FUNC_GPIO247 (MTK_PIN_NO(247) | 0)</div><div class='add'>+#define PINMUX_GPIO247__FUNC_CONN_PTA_RXD0 (MTK_PIN_NO(247) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO248__FUNC_GPIO248 (MTK_PIN_NO(248) | 0)</div><div class='add'>+#define PINMUX_GPIO248__FUNC_UCTS3 (MTK_PIN_NO(248) | 3)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO249__FUNC_GPIO249 (MTK_PIN_NO(249) | 0)</div><div class='add'>+#define PINMUX_GPIO249__FUNC_URTS3 (MTK_PIN_NO(249) | 3)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO250__FUNC_GPIO250 (MTK_PIN_NO(250) | 0)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO251__FUNC_GPIO251 (MTK_PIN_NO(251) | 0)</div><div class='add'>+#define PINMUX_GPIO251__FUNC_IDDIG_1P (MTK_PIN_NO(251) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO252__FUNC_GPIO252 (MTK_PIN_NO(252) | 0)</div><div class='add'>+#define PINMUX_GPIO252__FUNC_USB_DRVVBUS_1P (MTK_PIN_NO(252) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO253__FUNC_GPIO253 (MTK_PIN_NO(253) | 0)</div><div class='add'>+#define PINMUX_GPIO253__FUNC_VBUSVALID_1P (MTK_PIN_NO(253) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO254__FUNC_GPIO254 (MTK_PIN_NO(254) | 0)</div><div class='add'>+#define PINMUX_GPIO254__FUNC_IDDIG_2P (MTK_PIN_NO(254) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO255__FUNC_GPIO255 (MTK_PIN_NO(255) | 0)</div><div class='add'>+#define PINMUX_GPIO255__FUNC_USB_DRVVBUS_2P (MTK_PIN_NO(255) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO256__FUNC_GPIO256 (MTK_PIN_NO(256) | 0)</div><div class='add'>+#define PINMUX_GPIO256__FUNC_VBUSVALID_2P (MTK_PIN_NO(256) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO257__FUNC_GPIO257 (MTK_PIN_NO(257) | 0)</div><div class='add'>+#define PINMUX_GPIO257__FUNC_VBUSVALID_3P (MTK_PIN_NO(257) | 1)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO258__FUNC_GPIO258 (MTK_PIN_NO(258) | 0)</div><div class='add'>+#define PINMUX_GPIO258__FUNC_AVB_CLK1 (MTK_PIN_NO(258) | 7)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO259__FUNC_GPIO259 (MTK_PIN_NO(259) | 0)</div><div class='add'>+#define PINMUX_GPIO259__FUNC_GBE0_TXD0 (MTK_PIN_NO(259) | 1)</div><div class='add'>+#define PINMUX_GPIO259__FUNC_GBE1_TXD0 (MTK_PIN_NO(259) | 2)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO260__FUNC_GPIO260 (MTK_PIN_NO(260) | 0)</div><div class='add'>+#define PINMUX_GPIO260__FUNC_GBE0_TXD1 (MTK_PIN_NO(260) | 1)</div><div class='add'>+#define PINMUX_GPIO260__FUNC_GBE1_TXD1 (MTK_PIN_NO(260) | 2)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO261__FUNC_GPIO261 (MTK_PIN_NO(261) | 0)</div><div class='add'>+#define PINMUX_GPIO261__FUNC_GBE0_TXC (MTK_PIN_NO(261) | 1)</div><div class='add'>+#define PINMUX_GPIO261__FUNC_GBE1_TXC (MTK_PIN_NO(261) | 2)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO262__FUNC_GPIO262 (MTK_PIN_NO(262) | 0)</div><div class='add'>+#define PINMUX_GPIO262__FUNC_GBE0_TXEN (MTK_PIN_NO(262) | 1)</div><div class='add'>+#define PINMUX_GPIO262__FUNC_GBE1_TXEN (MTK_PIN_NO(262) | 2)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO263__FUNC_GPIO263 (MTK_PIN_NO(263) | 0)</div><div class='add'>+#define PINMUX_GPIO263__FUNC_GBE0_RXD0 (MTK_PIN_NO(263) | 1)</div><div class='add'>+#define PINMUX_GPIO263__FUNC_GBE1_RXD0 (MTK_PIN_NO(263) | 2)</div><div class='add'>+#define PINMUX_GPIO263__FUNC_GBE0_AUX_PPS0 (MTK_PIN_NO(263) | 3)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO264__FUNC_GPIO264 (MTK_PIN_NO(264) | 0)</div><div class='add'>+#define PINMUX_GPIO264__FUNC_GBE0_RXD1 (MTK_PIN_NO(264) | 1)</div><div class='add'>+#define PINMUX_GPIO264__FUNC_GBE1_RXD1 (MTK_PIN_NO(264) | 2)</div><div class='add'>+#define PINMUX_GPIO264__FUNC_GBE0_AUX_PPS1 (MTK_PIN_NO(264) | 3)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO265__FUNC_GPIO265 (MTK_PIN_NO(265) | 0)</div><div class='add'>+#define PINMUX_GPIO265__FUNC_GBE0_RXC (MTK_PIN_NO(265) | 1)</div><div class='add'>+#define PINMUX_GPIO265__FUNC_GBE1_RXC (MTK_PIN_NO(265) | 2)</div><div class='add'>+#define PINMUX_GPIO265__FUNC_GBE0_AUX_PPS2 (MTK_PIN_NO(265) | 3)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO266__FUNC_GPIO266 (MTK_PIN_NO(266) | 0)</div><div class='add'>+#define PINMUX_GPIO266__FUNC_GBE0_RXDV (MTK_PIN_NO(266) | 1)</div><div class='add'>+#define PINMUX_GPIO266__FUNC_GBE1_RXDV (MTK_PIN_NO(266) | 2)</div><div class='add'>+#define PINMUX_GPIO266__FUNC_GBE0_AUX_PPS3 (MTK_PIN_NO(266) | 3)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO267__FUNC_GPIO267 (MTK_PIN_NO(267) | 0)</div><div class='add'>+#define PINMUX_GPIO267__FUNC_GBE0_TXD2 (MTK_PIN_NO(267) | 1)</div><div class='add'>+#define PINMUX_GPIO267__FUNC_GBE1_TXD2 (MTK_PIN_NO(267) | 2)</div><div class='add'>+#define PINMUX_GPIO267__FUNC_GBE0_RXER (MTK_PIN_NO(267) | 3)</div><div class='add'>+#define PINMUX_GPIO267__FUNC_GBE1_RXER (MTK_PIN_NO(267) | 4)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO268__FUNC_GPIO268 (MTK_PIN_NO(268) | 0)</div><div class='add'>+#define PINMUX_GPIO268__FUNC_GBE0_TXD3 (MTK_PIN_NO(268) | 1)</div><div class='add'>+#define PINMUX_GPIO268__FUNC_GBE1_TXD3 (MTK_PIN_NO(268) | 2)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO269__FUNC_GPIO269 (MTK_PIN_NO(269) | 0)</div><div class='add'>+#define PINMUX_GPIO269__FUNC_GBE0_RXD2 (MTK_PIN_NO(269) | 1)</div><div class='add'>+#define PINMUX_GPIO269__FUNC_GBE1_RXD2 (MTK_PIN_NO(269) | 2)</div><div class='add'>+#define PINMUX_GPIO269__FUNC_GBE0_MDC (MTK_PIN_NO(269) | 3)</div><div class='add'>+</div><div class='add'>+#define PINMUX_GPIO270__FUNC_GPIO270 (MTK_PIN_NO(270) | 0)</div><div class='add'>+#define PINMUX_GPIO270__FUNC_GBE0_RXD3 (MTK_PIN_NO(270) | 1)</div><div class='add'>+#define PINMUX_GPIO270__FUNC_GBE1_RXD3 (MTK_PIN_NO(270) | 2)</div><div class='add'>+#define PINMUX_GPIO270__FUNC_GBE0_MDIO (MTK_PIN_NO(270) | 3)</div><div class='add'>+</div><div class='add'>+#endif /* __MT8196_PINFUNC_H */</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts<br/>new file mode 100644<br/>index 000000000000..b5dd5ef9fa11<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8365-evk.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8365-evk.dts</a></div><div class='hunk'>@@ -0,0 +1,797 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2021-2022 BayLibre, SAS.</div><div class='add'>+ * Authors:</div><div class='add'>+ * Fabien Parent &lt;fparent@baylibre.com&gt;</div><div class='add'>+ * Bernhard Rosenkränzer &lt;bero@baylibre.com&gt;</div><div class='add'>+ * Alexandre Mergnat &lt;amergnat@baylibre.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/mt8365-pinfunc.h&gt;</div><div class='add'>+#include "mt8365.dtsi"</div><div class='add'>+#include "mt6357.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "MediaTek MT8365 Open Platform EVK";</div><div class='add'>+	compatible = "mediatek,mt8365-evk", "mediatek,mt8365";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+		ethernet = &amp;ethernet;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:921600n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	connector {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		label = "hdmi";</div><div class='add'>+		type = "d";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			hdmi_connector_in: endpoint@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				remote-endpoint = &lt;&amp;hdmi_connector_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	firmware {</div><div class='add'>+		optee {</div><div class='add'>+			compatible = "linaro,optee-tz";</div><div class='add'>+			method = "smc";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;gpio_keys&gt;;</div><div class='add'>+</div><div class='add'>+		key-volume-up {</div><div class='add'>+			gpios = &lt;&amp;pio 24 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			label = "volume_up";</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+			debounce-interval = &lt;15&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0 0x40000000 0 0xc0000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb_otg_vbus: regulator-0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "otg_vbus";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;pio 16 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_vsys: regulator-vsys {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vsys";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	touch0_fixed_3v3: regulator-vio33tp {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vio33_tp";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;reg_vsys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */</div><div class='add'>+		bl31_secmon_reserved: secmon@43000000 {</div><div class='add'>+			no-map;</div><div class='add'>+			reg = &lt;0 0x43000000 0 0x30000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* 12 MiB reserved for OP-TEE (BL32)</div><div class='add'>+		 * +-----------------------+ 0x43e0_0000</div><div class='add'>+		 * |      SHMEM 2MiB       |</div><div class='add'>+		 * +-----------------------+ 0x43c0_0000</div><div class='add'>+		 * |        | TA_RAM  8MiB |</div><div class='add'>+		 * + TZDRAM +--------------+ 0x4340_0000</div><div class='add'>+		 * |        | TEE_RAM 2MiB |</div><div class='add'>+		 * +-----------------------+ 0x4320_0000</div><div class='add'>+		 */</div><div class='add'>+		optee_reserved: optee@43200000 {</div><div class='add'>+			no-map;</div><div class='add'>+			reg = &lt;0 0x43200000 0 0x00c00000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound: sound {</div><div class='add'>+		compatible = "mediatek,mt8365-mt6357";</div><div class='add'>+		pinctrl-names = "default",</div><div class='add'>+				"dmic",</div><div class='add'>+				"miso_off",</div><div class='add'>+				"miso_on",</div><div class='add'>+				"mosi_off",</div><div class='add'>+				"mosi_on";</div><div class='add'>+		pinctrl-0 = &lt;&amp;aud_default_pins&gt;;</div><div class='add'>+		pinctrl-1 = &lt;&amp;aud_dmic_pins&gt;;</div><div class='add'>+		pinctrl-2 = &lt;&amp;aud_miso_off_pins&gt;;</div><div class='add'>+		pinctrl-3 = &lt;&amp;aud_miso_on_pins&gt;;</div><div class='add'>+		pinctrl-4 = &lt;&amp;aud_mosi_off_pins&gt;;</div><div class='add'>+		pinctrl-5 = &lt;&amp;aud_mosi_on_pins&gt;;</div><div class='add'>+		mediatek,platform = &lt;&amp;afe&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vsys_lcm_reg: regulator-vsys-lcm {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;pio 129 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-name = "vsys_lcm";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;afe {</div><div class='add'>+	mediatek,dmic-mode = &lt;1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	proc-supply = &lt;&amp;mt6357_vproc_reg&gt;;</div><div class='add'>+	sram-supply = &lt;&amp;mt6357_vsram_proc_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu1 {</div><div class='add'>+	proc-supply = &lt;&amp;mt6357_vproc_reg&gt;;</div><div class='add'>+	sram-supply = &lt;&amp;mt6357_vsram_proc_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu2 {</div><div class='add'>+	proc-supply = &lt;&amp;mt6357_vproc_reg&gt;;</div><div class='add'>+	sram-supply = &lt;&amp;mt6357_vsram_proc_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu3 {</div><div class='add'>+	proc-supply = &lt;&amp;mt6357_vproc_reg&gt;;</div><div class='add'>+	sram-supply = &lt;&amp;mt6357_vsram_proc_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dither0_out {</div><div class='add'>+	remote-endpoint = &lt;&amp;dsi0_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dpi0 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;dpi_default_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;dpi_idle_pins&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	/*</div><div class='add'>+	 * Ethernet and HDMI (DPI0) are sharing pins.</div><div class='add'>+	 * Only one can be enabled at a time and require the physical switch</div><div class='add'>+	 * SW2101 to be set on LAN position</div><div class='add'>+	 */</div><div class='add'>+	status = "disabled";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		port@0 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			dpi0_in: endpoint@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				remote-endpoint = &lt;&amp;rdma1_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@1 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			dpi0_out: endpoint@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				remote-endpoint = &lt;&amp;it66121_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsi0 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	panel@0 {</div><div class='add'>+		compatible = "startek,kd070fhfid015";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;pio 67 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pio 20 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		iovcc-supply = &lt;&amp;mt6357_vsim1_reg&gt;;</div><div class='add'>+		power-supply = &lt;&amp;vsys_lcm_reg&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			panel_in: endpoint@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				remote-endpoint = &lt;&amp;dsi0_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+	ports {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		port@0 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			dsi0_in: endpoint@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				remote-endpoint = &lt;&amp;dither0_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@1 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			dsi0_out: endpoint@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				remote-endpoint = &lt;&amp;panel_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethernet {</div><div class='add'>+	pinctrl-0 = &lt;&amp;ethernet_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	phy-handle = &lt;&amp;eth_phy&gt;;</div><div class='add'>+	phy-mode = "rmii";</div><div class='add'>+	/*</div><div class='add'>+	 * Ethernet and HDMI (DPI0) are sharing pins.</div><div class='add'>+	 * Only one can be enabled at a time and require the physical switch</div><div class='add'>+	 * SW2101 to be set on LAN position</div><div class='add'>+	 * mt6357_vibr_reg and mt6357_vsim2_reg are needed to supply ethernet</div><div class='add'>+	 */</div><div class='add'>+	status = "disabled";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		eth_phy: ethernet-phy@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	mali-supply = &lt;&amp;mt6357_vcore_reg&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c0_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	clock-div = &lt;2&gt;;</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c1_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	it66121_hdmi: hdmi@4c {</div><div class='add'>+		compatible = "ite,it66121";</div><div class='add'>+		reg = &lt;0x4c&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;pio&gt;;</div><div class='add'>+		interrupts = &lt;68 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;ite_pins&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		reset-gpios = &lt;&amp;pio 69 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		vcn18-supply = &lt;&amp;mt6357_vsim2_reg&gt;;</div><div class='add'>+		vcn33-supply = &lt;&amp;mt6357_vibr_reg&gt;;</div><div class='add'>+		vrf12-supply = &lt;&amp;mt6357_vrf12_reg&gt;;</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				it66121_in: endpoint@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					bus-width = &lt;12&gt;;</div><div class='add'>+					remote-endpoint = &lt;&amp;dpi0_out&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@1 {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				hdmi_connector_out: endpoint@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					remote-endpoint = &lt;&amp;hdmi_connector_in&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	touchscreen@5d {</div><div class='add'>+		compatible = "goodix,gt9271";</div><div class='add'>+		reg = &lt;0x5d&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 78 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;touch_pins&gt;;</div><div class='add'>+		irq-gpios = &lt;&amp;pio 78 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pio 79 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		AVDD28-supply = &lt;&amp;touch0_fixed_3v3&gt;;</div><div class='add'>+		VDDIO-supply = &lt;&amp;mt6357_vrf12_reg&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mfg {</div><div class='add'>+	domain-supply = &lt;&amp;mt6357_vsram_others_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc0 {</div><div class='add'>+	assigned-clock-parents = &lt;&amp;topckgen CLK_TOP_MSDCPLL&gt;;</div><div class='add'>+	assigned-clocks = &lt;&amp;topckgen CLK_TOP_MSDC50_0_SEL&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	cap-mmc-highspeed;</div><div class='add'>+	cap-mmc-hw-reset;</div><div class='add'>+	hs400-ds-delay = &lt;0x12012&gt;;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	mmc-hs400-1_8v;</div><div class='add'>+	no-sd;</div><div class='add'>+	no-sdio;</div><div class='add'>+	non-removable;</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc0_default_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;mmc0_uhs_pins&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_uhs";</div><div class='add'>+	vmmc-supply = &lt;&amp;mt6357_vemc_reg&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;mt6357_vio18_reg&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc1 {</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	cd-gpios = &lt;&amp;pio 76 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc1_default_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;mmc1_uhs_pins&gt;;</div><div class='add'>+	pinctrl-names = "default", "state_uhs";</div><div class='add'>+	sd-uhs-sdr104;</div><div class='add'>+	sd-uhs-sdr50;</div><div class='add'>+	vmmc-supply = &lt;&amp;mt6357_vmch_reg&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;mt6357_vmc_reg&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6357_pmic {</div><div class='add'>+	interrupts-extended = &lt;&amp;pio 145 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	interrupt-controller;</div><div class='add'>+	#interrupt-cells = &lt;2&gt;;</div><div class='add'>+	mediatek,micbias0-microvolt = &lt;1900000&gt;;</div><div class='add'>+	mediatek,micbias1-microvolt = &lt;1700000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6357_vsim1_reg {</div><div class='add'>+	regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	aud_default_pins: audiodefault-pins {</div><div class='add'>+		clk-dat-pins {</div><div class='add'>+			pinmux = &lt;MT8365_PIN_72_CMDAT4__FUNC_I2S3_BCK&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_73_CMDAT5__FUNC_I2S3_LRCK&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_74_CMDAT6__FUNC_I2S3_MCK&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_75_CMDAT7__FUNC_I2S3_DO&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_dmic_pins: audiodmic-pins {</div><div class='add'>+		clk-dat-pins {</div><div class='add'>+			pinmux = &lt;MT8365_PIN_117_DMIC0_CLK__FUNC_DMIC0_CLK&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_118_DMIC0_DAT0__FUNC_DMIC0_DAT0&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_119_DMIC0_DAT1__FUNC_DMIC0_DAT1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_miso_off_pins: misooff-pins {</div><div class='add'>+		clk-dat-pins {</div><div class='add'>+			pinmux = &lt;MT8365_PIN_53_AUD_CLK_MISO__FUNC_GPIO53&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_54_AUD_SYNC_MISO__FUNC_GPIO54&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_55_AUD_DAT_MISO0__FUNC_GPIO55&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_56_AUD_DAT_MISO1__FUNC_GPIO56&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-down;</div><div class='add'>+			drive-strength = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_miso_on_pins: misoon-pins {</div><div class='add'>+		clk-dat-pins {</div><div class='add'>+			pinmux = &lt;MT8365_PIN_53_AUD_CLK_MISO__FUNC_AUD_CLK_MISO&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_54_AUD_SYNC_MISO__FUNC_AUD_SYNC_MISO&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_55_AUD_DAT_MISO0__FUNC_AUD_DAT_MISO0&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_56_AUD_DAT_MISO1__FUNC_AUD_DAT_MISO1&gt;;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_mosi_off_pins: mosioff-pins {</div><div class='add'>+		clk-dat-pins {</div><div class='add'>+			pinmux = &lt;MT8365_PIN_49_AUD_CLK_MOSI__FUNC_GPIO49&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_GPIO50&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_GPIO51&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_GPIO52&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-down;</div><div class='add'>+			drive-strength = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aud_mosi_on_pins: mosion-pins {</div><div class='add'>+		clk-dat-pins {</div><div class='add'>+			pinmux = &lt;MT8365_PIN_49_AUD_CLK_MOSI__FUNC_AUD_CLK_MOSI&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_AUD_SYNC_MOSI&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_AUD_DAT_MOSI0&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_AUD_DAT_MOSI1&gt;;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dpi_default_pins: dpi-default-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;MT8365_PIN_0_GPIO0__FUNC_DPI_D0&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_1_GPIO1__FUNC_DPI_D1&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_2_GPIO2__FUNC_DPI_D2&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_3_GPIO3__FUNC_DPI_D3&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_4_GPIO4__FUNC_DPI_D4&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_5_GPIO5__FUNC_DPI_D5&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_6_GPIO6__FUNC_DPI_D6&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_7_GPIO7__FUNC_DPI_D7&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_8_GPIO8__FUNC_DPI_D8&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_9_GPIO9__FUNC_DPI_D9&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_10_GPIO10__FUNC_DPI_D10&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_11_GPIO11__FUNC_DPI_D11&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_12_GPIO12__FUNC_DPI_DE&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_13_GPIO13__FUNC_DPI_VSYNC&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_14_GPIO14__FUNC_DPI_CK&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_15_GPIO15__FUNC_DPI_HSYNC&gt;;</div><div class='add'>+			drive-strength = &lt;4&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dpi_idle_pins: dpi-idle-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;MT8365_PIN_0_GPIO0__FUNC_GPIO0&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_1_GPIO1__FUNC_GPIO1&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_2_GPIO2__FUNC_GPIO2&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_3_GPIO3__FUNC_GPIO3&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_4_GPIO4__FUNC_GPIO4&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_5_GPIO5__FUNC_GPIO5&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_6_GPIO6__FUNC_GPIO6&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_7_GPIO7__FUNC_GPIO7&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_8_GPIO8__FUNC_GPIO8&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_9_GPIO9__FUNC_GPIO9&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_10_GPIO10__FUNC_GPIO10&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_11_GPIO11__FUNC_GPIO11&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_12_GPIO12__FUNC_GPIO12&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_13_GPIO13__FUNC_GPIO13&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_14_GPIO14__FUNC_GPIO14&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_15_GPIO15__FUNC_GPIO15&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ethernet_pins: ethernet-pins {</div><div class='add'>+		phy_reset_pins {</div><div class='add'>+			pinmux = &lt;MT8365_PIN_133_TDM_TX_DATA1__FUNC_GPIO133&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rmii_pins {</div><div class='add'>+			pinmux = &lt;MT8365_PIN_0_GPIO0__FUNC_EXT_TXD0&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_1_GPIO1__FUNC_EXT_TXD1&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_2_GPIO2__FUNC_EXT_TXD2&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_3_GPIO3__FUNC_EXT_TXD3&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_4_GPIO4__FUNC_EXT_TXC&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_5_GPIO5__FUNC_EXT_RXER&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_6_GPIO6__FUNC_EXT_RXC&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_7_GPIO7__FUNC_EXT_RXDV&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_8_GPIO8__FUNC_EXT_RXD0&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_9_GPIO9__FUNC_EXT_RXD1&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_10_GPIO10__FUNC_EXT_RXD2&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_11_GPIO11__FUNC_EXT_RXD3&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_12_GPIO12__FUNC_EXT_TXEN&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_13_GPIO13__FUNC_EXT_COL&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_14_GPIO14__FUNC_EXT_MDIO&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_15_GPIO15__FUNC_EXT_MDC&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio_keys: gpio-keys-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;MT8365_PIN_24_KPCOL0__FUNC_KPCOL0&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c0_pins: i2c0-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;MT8365_PIN_57_SDA0__FUNC_SDA0_0&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_58_SCL0__FUNC_SCL0_0&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c1_pins: i2c1-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;MT8365_PIN_59_SDA1__FUNC_SDA1_0&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_60_SCL1__FUNC_SCL1_0&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ite_pins: ite-pins {</div><div class='add'>+		irq_ite_pins {</div><div class='add'>+			pinmux = &lt;MT8365_PIN_68_CMDAT0__FUNC_GPIO68&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pwr_pins {</div><div class='add'>+			pinmux = &lt;MT8365_PIN_70_CMDAT2__FUNC_GPIO70&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_71_CMDAT3__FUNC_GPIO71&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rst_ite_pins {</div><div class='add'>+			pinmux = &lt;MT8365_PIN_69_CMDAT1__FUNC_GPIO69&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc0_default_pins: mmc0-default-pins {</div><div class='add'>+		clk-pins {</div><div class='add'>+			pinmux = &lt;MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK&gt;;</div><div class='add'>+			bias-pull-down;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmd-dat-pins {</div><div class='add'>+			pinmux = &lt;MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rst-pins {</div><div class='add'>+			pinmux = &lt;MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc0_uhs_pins: mmc0-uhs-pins {</div><div class='add'>+		clk-pins {</div><div class='add'>+			pinmux = &lt;MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK&gt;;</div><div class='add'>+			drive-strength = &lt;MTK_DRIVE_10mA&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmd-dat-pins {</div><div class='add'>+			pinmux = &lt;MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;MTK_DRIVE_10mA&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ds-pins {</div><div class='add'>+			pinmux = &lt;MT8365_PIN_104_MSDC0_DSL__FUNC_MSDC0_DSL&gt;;</div><div class='add'>+			drive-strength = &lt;MTK_DRIVE_10mA&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rst-pins {</div><div class='add'>+			pinmux = &lt;MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB&gt;;</div><div class='add'>+			drive-strength = &lt;MTK_DRIVE_10mA&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc1_default_pins: mmc1-default-pins {</div><div class='add'>+		cd-pins {</div><div class='add'>+			pinmux = &lt;MT8365_PIN_76_CMDAT8__FUNC_GPIO76&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		clk-pins {</div><div class='add'>+			pinmux = &lt;MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmd-dat-pins {</div><div class='add'>+			pinmux = &lt;MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc1_uhs_pins: mmc1-uhs-pins {</div><div class='add'>+		clk-pins {</div><div class='add'>+			pinmux = &lt;MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmd-dat-pins {</div><div class='add'>+			pinmux = &lt;MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	touch_pins: touch-pins {</div><div class='add'>+		ctp-int1-pins {</div><div class='add'>+			pinmux = &lt;MT8365_PIN_78_CMHSYNC__FUNC_GPIO78&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rst-pins {</div><div class='add'>+			pinmux = &lt;MT8365_PIN_79_CMVSYNC__FUNC_GPIO79&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart0_pins: uart0-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;MT8365_PIN_35_URXD0__FUNC_URXD0&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_36_UTXD0__FUNC_UTXD0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart1_pins: uart1-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;MT8365_PIN_37_URXD1__FUNC_URXD1&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_38_UTXD1__FUNC_UTXD1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart2_pins: uart2-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;MT8365_PIN_39_URXD2__FUNC_URXD2&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_40_UTXD2__FUNC_UTXD2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb_pins: usb-pins {</div><div class='add'>+		id-pins {</div><div class='add'>+			pinmux = &lt;MT8365_PIN_17_GPIO17__FUNC_GPIO17&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb0-vbus-pins {</div><div class='add'>+			pinmux = &lt;MT8365_PIN_16_GPIO16__FUNC_USB_DRVVBUS&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb1-vbus-pins {</div><div class='add'>+			pinmux = &lt;MT8365_PIN_18_GPIO18__FUNC_GPIO18&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pwm_pins: pwm-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;MT8365_PIN_19_DISP_PWM__FUNC_PWM_A&gt;,</div><div class='add'>+				 &lt;MT8365_PIN_116_I2S_BCK__FUNC_PWM_C&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pwm {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;rdma1_out {</div><div class='add'>+	remote-endpoint = &lt;&amp;dpi0_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ssusb {</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	maximum-speed = "high-speed";</div><div class='add'>+	pinctrl-0 = &lt;&amp;usb_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	vusb33-supply = &lt;&amp;mt6357_vusb33_reg&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	connector {</div><div class='add'>+		compatible = "gpio-usb-b-connector", "usb-b-connector";</div><div class='add'>+		id-gpios = &lt;&amp;pio 17 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		type = "micro";</div><div class='add'>+		vbus-supply = &lt;&amp;usb_otg_vbus&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_host {</div><div class='add'>+	vusb33-supply = &lt;&amp;mt6357_vusb33_reg&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart0_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart1_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart2_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi<br/>new file mode 100644<br/>index 000000000000..a5ca3cda6ef3<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8365.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8365.dtsi</a></div><div class='hunk'>@@ -0,0 +1,1256 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * (C) 2018 MediaTek Inc.</div><div class='add'>+ * Copyright (C) 2022 BayLibre SAS</div><div class='add'>+ * Authors: Fabien Parent &lt;fparent@baylibre.com&gt;</div><div class='add'>+ *	    Bernhard Rosenkränzer &lt;bero@baylibre.com&gt;</div><div class='add'>+ *	    Alexandre Mergnat &lt;amergnat@baylibre.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/mediatek,mt8365-clk.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/memory/mediatek,mt8365-larb-port.h&gt;</div><div class='add'>+#include &lt;dt-bindings/phy/phy.h&gt;</div><div class='add'>+#include &lt;dt-bindings/power/mediatek,mt8365-power.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "mediatek,mt8365";</div><div class='add'>+	interrupt-parent = &lt;&amp;sysirq&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		aal0 = &amp;aal0;</div><div class='add'>+		ccorr0 = &amp;ccorr0;</div><div class='add'>+		color0 = &amp;color0;</div><div class='add'>+		dither0 = &amp;dither0;</div><div class='add'>+		dpi0 = &amp;dpi0;</div><div class='add'>+		dsi0 = &amp;dsi0;</div><div class='add'>+		gamma0 = &amp;gamma0;</div><div class='add'>+		ovl0 = &amp;ovl0;</div><div class='add'>+		rdma0 = &amp;rdma0;</div><div class='add'>+		rdma1 = &amp;rdma1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	cluster0_opp: opp-table-0 {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+		opp-shared;</div><div class='add'>+</div><div class='add'>+		opp-850000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;850000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;650000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-918000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;918000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;668750&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-987000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;987000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;687500&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1056000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1056000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;706250&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1125000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1125000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;725000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1216000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1216000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;750000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1308000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1308000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;775000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1400000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1400000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;800000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1466000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1466000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;825000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1533000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1533000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;850000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1633000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1633000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;887500&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1700000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1700000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;912500&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1767000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1767000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;937500&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1834000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1834000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;962500&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1917000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1917000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;993750&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-2001000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2001000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1025000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+		cpu-map {</div><div class='add'>+			cluster0 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu0&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu1&gt;;</div><div class='add'>+				};</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu2&gt;;</div><div class='add'>+				};</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu3&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x0&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			cpu-idle-states = &lt;&amp;CPU_MCDI &amp;CLUSTER_MCDI &amp;CLUSTER_DPIDLE&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2&gt;;</div><div class='add'>+			clocks = &lt;&amp;mcucfg CLK_MCU_BUS_SEL&gt;,</div><div class='add'>+				 &lt;&amp;apmixedsys CLK_APMIXED_MAINPLL&gt;;</div><div class='add'>+			clock-names = "cpu", "intermediate";</div><div class='add'>+			operating-points-v2 = &lt;&amp;cluster0_opp&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@1 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x1&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			cpu-idle-states = &lt;&amp;CPU_MCDI &amp;CLUSTER_MCDI &amp;CLUSTER_DPIDLE&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2&gt;;</div><div class='add'>+			clocks = &lt;&amp;mcucfg CLK_MCU_BUS_SEL&gt;,</div><div class='add'>+				 &lt;&amp;apmixedsys CLK_APMIXED_MAINPLL&gt;;</div><div class='add'>+			clock-names = "cpu", "intermediate", "armpll";</div><div class='add'>+			operating-points-v2 = &lt;&amp;cluster0_opp&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@2 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x2&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			cpu-idle-states = &lt;&amp;CPU_MCDI &amp;CLUSTER_MCDI &amp;CLUSTER_DPIDLE&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2&gt;;</div><div class='add'>+			clocks = &lt;&amp;mcucfg CLK_MCU_BUS_SEL&gt;,</div><div class='add'>+				 &lt;&amp;apmixedsys CLK_APMIXED_MAINPLL&gt;;</div><div class='add'>+			clock-names = "cpu", "intermediate", "armpll";</div><div class='add'>+			operating-points-v2 = &lt;&amp;cluster0_opp&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@3 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x3&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			cpu-idle-states = &lt;&amp;CPU_MCDI &amp;CLUSTER_MCDI &amp;CLUSTER_DPIDLE&gt;;</div><div class='add'>+			i-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;0x8000&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2&gt;;</div><div class='add'>+			clocks = &lt;&amp;mcucfg CLK_MCU_BUS_SEL&gt;,</div><div class='add'>+				 &lt;&amp;apmixedsys CLK_APMIXED_MAINPLL&gt;;</div><div class='add'>+			clock-names = "cpu", "intermediate", "armpll";</div><div class='add'>+			operating-points-v2 = &lt;&amp;cluster0_opp&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		idle-states {</div><div class='add'>+			entry-method = "psci";</div><div class='add'>+</div><div class='add'>+			CPU_MCDI: cpu-mcdi {</div><div class='add'>+				compatible = "arm,idle-state";</div><div class='add'>+				local-timer-stop;</div><div class='add'>+				arm,psci-suspend-param = &lt;0x00010001&gt;;</div><div class='add'>+				entry-latency-us = &lt;300&gt;;</div><div class='add'>+				exit-latency-us = &lt;200&gt;;</div><div class='add'>+				min-residency-us = &lt;1000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			CLUSTER_MCDI: cluster-mcdi {</div><div class='add'>+				compatible = "arm,idle-state";</div><div class='add'>+				local-timer-stop;</div><div class='add'>+				arm,psci-suspend-param = &lt;0x01010001&gt;;</div><div class='add'>+				entry-latency-us = &lt;350&gt;;</div><div class='add'>+				exit-latency-us = &lt;250&gt;;</div><div class='add'>+				min-residency-us = &lt;1200&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			CLUSTER_DPIDLE: cluster-dpidle {</div><div class='add'>+				compatible = "arm,idle-state";</div><div class='add'>+				local-timer-stop;</div><div class='add'>+				arm,psci-suspend-param = &lt;0x01010004&gt;;</div><div class='add'>+				entry-latency-us = &lt;300&gt;;</div><div class='add'>+				exit-latency-us = &lt;800&gt;;</div><div class='add'>+				min-residency-us = &lt;3300&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2: l2-cache {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-size = &lt;0x80000&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;512&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk26m: oscillator {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;26000000&gt;;</div><div class='add'>+		clock-output-names = "clk26m";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpu_opp_table: opp-table-gpu {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+		opp-shared;</div><div class='add'>+</div><div class='add'>+		opp-450000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;450000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;650000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-560000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;560000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;700000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-800000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;800000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;800000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-1.0";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@c000000 {</div><div class='add'>+			compatible = "arm,gic-v3";</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			reg = &lt;0 0x0c000000 0 0x10000&gt;, /* GICD */</div><div class='add'>+			      &lt;0 0x0c080000 0 0x80000&gt;, /* GICR */</div><div class='add'>+			      &lt;0 0x0c400000 0 0x2000&gt;,  /* GICC */</div><div class='add'>+			      &lt;0 0x0c410000 0 0x1000&gt;,  /* GICH */</div><div class='add'>+			      &lt;0 0x0c420000 0 0x2000&gt;;  /* GICV */</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mfgcfg: syscon@13000000 {</div><div class='add'>+			compatible = "mediatek,mt8365-mfgcfg", "syscon";</div><div class='add'>+			reg = &lt;0 0x13000000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu: gpu@13040000 {</div><div class='add'>+			compatible = "mediatek,mt8365-mali", "arm,mali-bifrost";</div><div class='add'>+			reg = &lt;0 0x13040000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;mfgcfg CLK_MFG_BG3D&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 203 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+				     &lt;GIC_SPI 202 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+				     &lt;GIC_SPI 201 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+				     &lt;GIC_SPI 204 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			interrupt-names = "job", "mmu", "gpu", "event";</div><div class='add'>+			operating-points-v2 = &lt;&amp;gpu_opp_table&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8365_POWER_DOMAIN_MFG&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		topckgen: syscon@10000000 {</div><div class='add'>+			compatible = "mediatek,mt8365-topckgen", "syscon";</div><div class='add'>+			reg = &lt;0 0x10000000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		infracfg: syscon@10001000 {</div><div class='add'>+			compatible = "mediatek,mt8365-infracfg", "syscon";</div><div class='add'>+			reg = &lt;0 0x10001000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pericfg: syscon@10003000 {</div><div class='add'>+			compatible = "mediatek,mt8365-pericfg", "syscon";</div><div class='add'>+			reg = &lt;0 0x10003000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		syscfg_pctl: syscfg-pctl@10005000 {</div><div class='add'>+			compatible = "mediatek,mt8365-syscfg", "syscon";</div><div class='add'>+			reg = &lt;0 0x10005000 0 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		scpsys: syscon@10006000 {</div><div class='add'>+			compatible = "mediatek,mt8365-scpsys", "syscon", "simple-mfd";</div><div class='add'>+			reg = &lt;0 0x10006000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			/* System Power Manager */</div><div class='add'>+			spm: power-controller {</div><div class='add'>+				compatible = "mediatek,mt8365-power-controller";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				/* power domains of the SoC */</div><div class='add'>+				power-domain@MT8365_POWER_DOMAIN_MM {</div><div class='add'>+					reg = &lt;MT8365_POWER_DOMAIN_MM&gt;;</div><div class='add'>+					clocks = &lt;&amp;topckgen CLK_TOP_MM_SEL&gt;,</div><div class='add'>+						 &lt;&amp;mmsys CLK_MM_MM_SMI_COMMON&gt;,</div><div class='add'>+						 &lt;&amp;mmsys CLK_MM_MM_SMI_COMM0&gt;,</div><div class='add'>+						 &lt;&amp;mmsys CLK_MM_MM_SMI_COMM1&gt;,</div><div class='add'>+						 &lt;&amp;mmsys CLK_MM_MM_SMI_LARB0&gt;;</div><div class='add'>+					clock-names = "mm", "mm-0", "mm-1",</div><div class='add'>+						      "mm-2", "mm-3";</div><div class='add'>+					#power-domain-cells = &lt;0&gt;;</div><div class='add'>+					mediatek,infracfg = &lt;&amp;infracfg&gt;;</div><div class='add'>+					mediatek,infracfg-nao = &lt;&amp;infracfg_nao&gt;;</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					power-domain@MT8365_POWER_DOMAIN_CAM {</div><div class='add'>+						reg = &lt;MT8365_POWER_DOMAIN_CAM&gt;;</div><div class='add'>+						clocks = &lt;&amp;camsys CLK_CAM_LARB2&gt;,</div><div class='add'>+							 &lt;&amp;camsys CLK_CAM_SENIF&gt;,</div><div class='add'>+							 &lt;&amp;camsys CLK_CAMSV0&gt;,</div><div class='add'>+							 &lt;&amp;camsys CLK_CAMSV1&gt;,</div><div class='add'>+							 &lt;&amp;camsys CLK_CAM_FDVT&gt;,</div><div class='add'>+							 &lt;&amp;camsys CLK_CAM_WPE&gt;;</div><div class='add'>+						clock-names = "cam-0", "cam-1",</div><div class='add'>+							      "cam-2", "cam-3",</div><div class='add'>+							      "cam-4", "cam-5";</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						mediatek,infracfg = &lt;&amp;infracfg&gt;;</div><div class='add'>+						mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					power-domain@MT8365_POWER_DOMAIN_VDEC {</div><div class='add'>+						reg = &lt;MT8365_POWER_DOMAIN_VDEC&gt;;</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					power-domain@MT8365_POWER_DOMAIN_VENC {</div><div class='add'>+						reg = &lt;MT8365_POWER_DOMAIN_VENC&gt;;</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					power-domain@MT8365_POWER_DOMAIN_APU {</div><div class='add'>+						reg = &lt;MT8365_POWER_DOMAIN_APU&gt;;</div><div class='add'>+						clocks = &lt;&amp;infracfg CLK_IFR_APU_AXI&gt;,</div><div class='add'>+							 &lt;&amp;apu CLK_APU_IPU_CK&gt;,</div><div class='add'>+							 &lt;&amp;apu CLK_APU_AXI&gt;,</div><div class='add'>+							 &lt;&amp;apu CLK_APU_JTAG&gt;,</div><div class='add'>+							 &lt;&amp;apu CLK_APU_IF_CK&gt;,</div><div class='add'>+							 &lt;&amp;apu CLK_APU_EDMA&gt;,</div><div class='add'>+							 &lt;&amp;apu CLK_APU_AHB&gt;;</div><div class='add'>+						clock-names = "apu", "apu-0",</div><div class='add'>+							      "apu-1", "apu-2",</div><div class='add'>+							      "apu-3", "apu-4",</div><div class='add'>+							      "apu-5";</div><div class='add'>+						#power-domain-cells = &lt;0&gt;;</div><div class='add'>+						mediatek,infracfg = &lt;&amp;infracfg&gt;;</div><div class='add'>+						mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				power-domain@MT8365_POWER_DOMAIN_CONN {</div><div class='add'>+					reg = &lt;MT8365_POWER_DOMAIN_CONN&gt;;</div><div class='add'>+					clocks = &lt;&amp;topckgen CLK_TOP_CONN_32K&gt;,</div><div class='add'>+						 &lt;&amp;topckgen CLK_TOP_CONN_26M&gt;;</div><div class='add'>+					clock-names = "conn", "conn1";</div><div class='add'>+					#power-domain-cells = &lt;0&gt;;</div><div class='add'>+					mediatek,infracfg = &lt;&amp;infracfg&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				mfg: power-domain@MT8365_POWER_DOMAIN_MFG {</div><div class='add'>+					reg = &lt;MT8365_POWER_DOMAIN_MFG&gt;;</div><div class='add'>+					clocks = &lt;&amp;topckgen CLK_TOP_MFG_SEL&gt;;</div><div class='add'>+					clock-names = "mfg";</div><div class='add'>+					#power-domain-cells = &lt;0&gt;;</div><div class='add'>+					mediatek,infracfg = &lt;&amp;infracfg&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				power-domain@MT8365_POWER_DOMAIN_AUDIO {</div><div class='add'>+					reg = &lt;MT8365_POWER_DOMAIN_AUDIO&gt;;</div><div class='add'>+					clocks = &lt;&amp;topckgen CLK_TOP_AUD_INTBUS_SEL&gt;,</div><div class='add'>+						 &lt;&amp;infracfg CLK_IFR_AUDIO&gt;,</div><div class='add'>+						 &lt;&amp;infracfg CLK_IFR_AUD_26M_BK&gt;;</div><div class='add'>+					clock-names = "audio", "audio1", "audio2";</div><div class='add'>+					#power-domain-cells = &lt;0&gt;;</div><div class='add'>+					mediatek,infracfg = &lt;&amp;infracfg&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				power-domain@MT8365_POWER_DOMAIN_DSP {</div><div class='add'>+					reg = &lt;MT8365_POWER_DOMAIN_DSP&gt;;</div><div class='add'>+					clocks = &lt;&amp;topckgen CLK_TOP_DSP_SEL&gt;,</div><div class='add'>+						 &lt;&amp;topckgen CLK_TOP_DSP_26M&gt;;</div><div class='add'>+					clock-names = "dsp", "dsp1";</div><div class='add'>+					#power-domain-cells = &lt;0&gt;;</div><div class='add'>+					mediatek,infracfg = &lt;&amp;infracfg&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		watchdog: watchdog@10007000 {</div><div class='add'>+			compatible = "mediatek,mt8365-wdt", "mediatek,mt6589-wdt";</div><div class='add'>+			reg = &lt;0 0x10007000 0 0x100&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pio: pinctrl@1000b000 {</div><div class='add'>+			compatible = "mediatek,mt8365-pinctrl";</div><div class='add'>+			reg = &lt;0 0x1000b000 0 0x1000&gt;;</div><div class='add'>+			mediatek,pctl-regmap = &lt;&amp;syscfg_pctl&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		apmixedsys: syscon@1000c000 {</div><div class='add'>+			compatible = "mediatek,mt8365-apmixedsys", "syscon";</div><div class='add'>+			reg = &lt;0 0x1000c000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pwrap: pwrap@1000d000 {</div><div class='add'>+			compatible = "mediatek,mt8365-pwrap";</div><div class='add'>+			reg = &lt;0 0x1000d000 0 0x1000&gt;;</div><div class='add'>+			reg-names = "pwrap";</div><div class='add'>+			interrupts = &lt;GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_IFR_PWRAP_SPI&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_IFR_PMIC_AP&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_IFR_PWRAP_SYS&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_IFR_PWRAP_TMR&gt;;</div><div class='add'>+			clock-names = "spi", "wrap", "sys", "tmr";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		keypad: keypad@10010000 {</div><div class='add'>+			compatible = "mediatek,mt8365-keypad",</div><div class='add'>+				     "mediatek,mt6779-keypad";</div><div class='add'>+			reg = &lt;0 0x10010000 0 0x1000&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+			interrupts = &lt;GIC_SPI 124 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk26m&gt;;</div><div class='add'>+			clock-names = "kpd";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mcucfg: syscon@10200000 {</div><div class='add'>+			compatible = "mediatek,mt8365-mcucfg", "syscon";</div><div class='add'>+			reg = &lt;0 0x10200000 0 0x2000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sysirq: interrupt-controller@10200a80 {</div><div class='add'>+			compatible = "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq";</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+			reg = &lt;0 0x10200a80 0 0x20&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		iommu: iommu@10205000 {</div><div class='add'>+			compatible = "mediatek,mt8365-m4u";</div><div class='add'>+			reg = &lt;0 0x10205000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 102 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			mediatek,larbs = &lt;&amp;larb0&gt;, &lt;&amp;larb1&gt;, &lt;&amp;larb2&gt;, &lt;&amp;larb3&gt;;</div><div class='add'>+			#iommu-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		infracfg_nao: infracfg@1020e000 {</div><div class='add'>+			compatible = "mediatek,mt8365-infracfg", "syscon";</div><div class='add'>+			reg = &lt;0 0x1020e000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rng: rng@1020f000 {</div><div class='add'>+			compatible = "mediatek,mt8365-rng", "mediatek,mt7623-rng";</div><div class='add'>+			reg = &lt;0 0x1020f000 0 0x100&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_IFR_TRNG&gt;;</div><div class='add'>+			clock-names = "rng";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		apdma: dma-controller@11000280 {</div><div class='add'>+			compatible = "mediatek,mt8365-uart-dma", "mediatek,mt6577-uart-dma";</div><div class='add'>+			reg = &lt;0 0x11000280 0 0x80&gt;,</div><div class='add'>+			      &lt;0 0x11000300 0 0x80&gt;,</div><div class='add'>+			      &lt;0 0x11000380 0 0x80&gt;,</div><div class='add'>+			      &lt;0 0x11000400 0 0x80&gt;,</div><div class='add'>+			      &lt;0 0x11000580 0 0x80&gt;,</div><div class='add'>+			      &lt;0 0x11000600 0 0x80&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 45 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+				     &lt;GIC_SPI 46 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+				     &lt;GIC_SPI 47 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+				     &lt;GIC_SPI 48 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+				     &lt;GIC_SPI 51 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+				     &lt;GIC_SPI 52 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			dma-requests = &lt;6&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_IFR_AP_DMA&gt;;</div><div class='add'>+			clock-names = "apdma";</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart0: serial@11002000 {</div><div class='add'>+			compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart";</div><div class='add'>+			reg = &lt;0 0x11002000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 35 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk26m&gt;, &lt;&amp;infracfg CLK_IFR_UART0&gt;;</div><div class='add'>+			clock-names = "baud", "bus";</div><div class='add'>+			dmas = &lt;&amp;apdma 0&gt;, &lt;&amp;apdma 1&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart1: serial@11003000 {</div><div class='add'>+			compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart";</div><div class='add'>+			reg = &lt;0 0x11003000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 36 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk26m&gt;, &lt;&amp;infracfg CLK_IFR_UART1&gt;;</div><div class='add'>+			clock-names = "baud", "bus";</div><div class='add'>+			dmas = &lt;&amp;apdma 2&gt;, &lt;&amp;apdma 3&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart2: serial@11004000 {</div><div class='add'>+			compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart";</div><div class='add'>+			reg = &lt;0 0x11004000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 37 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk26m&gt;, &lt;&amp;infracfg CLK_IFR_UART2&gt;;</div><div class='add'>+			clock-names = "baud", "bus";</div><div class='add'>+			dmas = &lt;&amp;apdma 4&gt;, &lt;&amp;apdma 5&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pwm: pwm@11006000 {</div><div class='add'>+			compatible = "mediatek,mt8365-pwm";</div><div class='add'>+			reg = &lt;0 0x11006000 0 0x1000&gt;;</div><div class='add'>+			#pwm-cells = &lt;2&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 76 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_IFR_PWM_HCLK&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_IFR_PWM&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_IFR_PWM1&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_IFR_PWM2&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_IFR_PWM3&gt;;</div><div class='add'>+			clock-names = "top", "main", "pwm1", "pwm2", "pwm3";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c0: i2c@11007000 {</div><div class='add'>+			compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";</div><div class='add'>+			reg = &lt;0 0x11007000 0 0xa0&gt;, &lt;0 0x11000080 0 0x80&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 28 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			clock-div = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_IFR_I2C0_AXI&gt;, &lt;&amp;infracfg CLK_IFR_AP_DMA&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c1: i2c@11008000 {</div><div class='add'>+			compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";</div><div class='add'>+			reg = &lt;0 0x11008000 0 0xa0&gt;, &lt;0 0x11000100 0 0x80&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 29 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			clock-div = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_IFR_I2C1_AXI&gt;, &lt;&amp;infracfg CLK_IFR_AP_DMA&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c2: i2c@11009000 {</div><div class='add'>+			compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";</div><div class='add'>+			reg = &lt;0 0x11009000 0 0xa0&gt;, &lt;0 0x11000180 0 0x80&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 30 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			clock-div = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_IFR_I2C2_AXI&gt;, &lt;&amp;infracfg CLK_IFR_AP_DMA&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi: spi@1100a000 {</div><div class='add'>+			compatible = "mediatek,mt8365-spi", "mediatek,mt7622-spi";</div><div class='add'>+			reg = &lt;0 0x1100a000 0 0x100&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 62 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_UNIVPLL2_D4&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_SPI_SEL&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_IFR_SPI0&gt;;</div><div class='add'>+			clock-names = "parent-clk", "sel-clk", "spi-clk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		disp_pwm: pwm@1100e000 {</div><div class='add'>+			compatible = "mediatek,mt8365-disp-pwm", "mediatek,mt8183-disp-pwm";</div><div class='add'>+			reg = &lt;0 0x1100e000 0 0x1000&gt;;</div><div class='add'>+			clock-names = "main", "mm";</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_DISP_PWM_SEL&gt;, &lt;&amp;infracfg CLK_IFR_DISP_PWM&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8365_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			#pwm-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c3: i2c@1100f000 {</div><div class='add'>+			compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";</div><div class='add'>+			reg = &lt;0 0x1100f000 0 0xa0&gt;, &lt;0 0x11000200 0 0x80&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 31 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			clock-div = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;infracfg CLK_IFR_I2C3_AXI&gt;, &lt;&amp;infracfg CLK_IFR_AP_DMA&gt;;</div><div class='add'>+			clock-names = "main", "dma";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ssusb: usb@11201000 {</div><div class='add'>+			compatible = "mediatek,mt8365-mtu3", "mediatek,mtu3";</div><div class='add'>+			reg = &lt;0 0x11201000 0 0x2e00&gt;, &lt;0 0x11203e00 0 0x0100&gt;;</div><div class='add'>+			reg-names = "mac", "ippc";</div><div class='add'>+			interrupts = &lt;GIC_SPI 16 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			phys = &lt;&amp;u2port0 PHY_TYPE_USB2&gt;,</div><div class='add'>+			       &lt;&amp;u2port1 PHY_TYPE_USB2&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_SSUSB_TOP_CK_EN&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_IFR_SSUSB_REF&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_IFR_SSUSB_SYS&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_IFR_ICUSB&gt;;</div><div class='add'>+			clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			usb_host: usb@11200000 {</div><div class='add'>+				compatible = "mediatek,mt8365-xhci", "mediatek,mtk-xhci";</div><div class='add'>+				reg = &lt;0 0x11200000 0 0x1000&gt;;</div><div class='add'>+				reg-names = "mac";</div><div class='add'>+				interrupts = &lt;GIC_SPI 67 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+				clocks = &lt;&amp;topckgen CLK_TOP_SSUSB_TOP_CK_EN&gt;,</div><div class='add'>+					 &lt;&amp;infracfg CLK_IFR_SSUSB_REF&gt;,</div><div class='add'>+					 &lt;&amp;infracfg CLK_IFR_SSUSB_SYS&gt;,</div><div class='add'>+					 &lt;&amp;infracfg CLK_IFR_ICUSB&gt;,</div><div class='add'>+					 &lt;&amp;infracfg CLK_IFR_SSUSB_XHCI&gt;;</div><div class='add'>+				clock-names = "sys_ck", "ref_ck", "mcu_ck",</div><div class='add'>+					      "dma_ck", "xhci_ck";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmc0: mmc@11230000 {</div><div class='add'>+			compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";</div><div class='add'>+			reg = &lt;0 0x11230000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11cd0000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 23 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_MSDC50_0_SEL&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_IFR_MSDC0_HCLK&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_IFR_MSDC0_SRC&gt;;</div><div class='add'>+			clock-names = "source", "hclk", "source_cg";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmc1: mmc@11240000 {</div><div class='add'>+			compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";</div><div class='add'>+			reg = &lt;0 0x11240000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11c90000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 24 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_MSDC30_1_SEL&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_IFR_MSDC1_HCLK&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_IFR_MSDC1_SRC&gt;;</div><div class='add'>+			clock-names = "source", "hclk", "source_cg";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmc2: mmc@11250000 {</div><div class='add'>+			compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";</div><div class='add'>+			reg = &lt;0 0x11250000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x11c60000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 68 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_MSDC50_2_SEL&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_IFR_MSDC2_HCLK&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_IFR_MSDC2_SRC&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_IFR_MSDC2_BK&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_IFR_AP_MSDC0&gt;;</div><div class='add'>+			clock-names = "source", "hclk", "source_cg",</div><div class='add'>+				      "bus_clk", "sys_cg";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ethernet: ethernet@112a0000 {</div><div class='add'>+			compatible = "mediatek,mt8365-eth";</div><div class='add'>+			reg = &lt;0 0x112a0000 0 0x1000&gt;;</div><div class='add'>+			mediatek,pericfg = &lt;&amp;infracfg&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_ETH_SEL&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_IFR_NIC_AXI&gt;,</div><div class='add'>+				 &lt;&amp;infracfg CLK_IFR_NIC_SLV_AXI&gt;;</div><div class='add'>+			clock-names = "core", "reg", "trans";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mipi_tx0: dsi-phy@11c00000 {</div><div class='add'>+			compatible = "mediatek,mt8365-mipi-tx", "mediatek,mt8183-mipi-tx";</div><div class='add'>+			reg = &lt;0 0x11c00000 0 0x800&gt;;</div><div class='add'>+			clock-output-names = "mipi_tx0_pll";</div><div class='add'>+			clocks = &lt;&amp;clk26m&gt;;</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		u3phy: t-phy@11cc0000 {</div><div class='add'>+			compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges = &lt;0 0 0x11cc0000 0x9000&gt;;</div><div class='add'>+</div><div class='add'>+			u2port0: usb-phy@0 {</div><div class='add'>+				reg = &lt;0x0 0x400&gt;;</div><div class='add'>+				clocks = &lt;&amp;topckgen CLK_TOP_SSUSB_PHY_CK_EN&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_USB20_48M_EN&gt;;</div><div class='add'>+				clock-names = "ref", "da_ref";</div><div class='add'>+				#phy-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			u2port1: usb-phy@1000 {</div><div class='add'>+				reg = &lt;0x1000 0x400&gt;;</div><div class='add'>+				clocks = &lt;&amp;topckgen CLK_TOP_SSUSB_PHY_CK_EN&gt;,</div><div class='add'>+					 &lt;&amp;topckgen CLK_TOP_USB20_48M_EN&gt;;</div><div class='add'>+				clock-names = "ref", "da_ref";</div><div class='add'>+				#phy-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmsys: syscon@14000000 {</div><div class='add'>+			compatible = "mediatek,mt8365-mmsys", "syscon";</div><div class='add'>+			reg = &lt;0 0x14000000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			port {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				mmsys_main: endpoint@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					remote-endpoint = &lt;&amp;ovl0_in&gt;;</div><div class='add'>+				};</div><div class='add'>+				mmsys_ext: endpoint@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					remote-endpoint = &lt;&amp;rdma1_in&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mutex: mutex@14001000 {</div><div class='add'>+			compatible =  "mediatek,mt8365-disp-mutex";</div><div class='add'>+			reg = &lt;0 0x14001000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 154 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8365_POWER_DOMAIN_MM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smi_common: smi@14002000 {</div><div class='add'>+			compatible = "mediatek,mt8365-smi-common";</div><div class='add'>+			reg = &lt;0 0x14002000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_MM_SMI_COMMON&gt;,</div><div class='add'>+				 &lt;&amp;mmsys CLK_MM_MM_SMI_COMMON&gt;,</div><div class='add'>+				 &lt;&amp;mmsys CLK_MM_MM_SMI_COMM0&gt;,</div><div class='add'>+				 &lt;&amp;mmsys CLK_MM_MM_SMI_COMM1&gt;;</div><div class='add'>+			clock-names = "apb", "smi", "gals0", "gals1";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8365_POWER_DOMAIN_MM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb0: larb@14003000 {</div><div class='add'>+			compatible = "mediatek,mt8365-smi-larb",</div><div class='add'>+				     "mediatek,mt8186-smi-larb";</div><div class='add'>+			reg = &lt;0 0x14003000 0 0x1000&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_MM_SMI_LARB0&gt;,</div><div class='add'>+				 &lt;&amp;mmsys CLK_MM_MM_SMI_LARB0&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8365_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ovl0: ovl@1400b000 {</div><div class='add'>+			compatible = "mediatek,mt8365-disp-ovl", "mediatek,mt8192-disp-ovl";</div><div class='add'>+			reg = &lt;0 0x1400b000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_MM_DISP_OVL0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 161 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu M4U_PORT_DISP_OVL0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8365_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					ovl0_in: endpoint@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+						remote-endpoint = &lt;&amp;mmsys_main&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					ovl0_out: endpoint@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+						remote-endpoint = &lt;&amp;rdma0_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rdma0: rdma@1400d000 {</div><div class='add'>+			compatible = "mediatek,mt8365-disp-rdma", "mediatek,mt8183-disp-rdma";</div><div class='add'>+			reg = &lt;0 0x1400d000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_MM_DISP_RDMA0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 162 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu M4U_PORT_DISP_RDMA0&gt;;</div><div class='add'>+			mediatek,rdma-fifo-size = &lt;5120&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8365_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					rdma0_in: endpoint@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+						remote-endpoint = &lt;&amp;ovl0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					rdma0_out: endpoint@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+						remote-endpoint = &lt;&amp;color0_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		color0: color@1400f000 {</div><div class='add'>+			compatible = "mediatek,mt8365-disp-color", "mediatek,mt8173-disp-color";</div><div class='add'>+			reg = &lt;0 0x1400f000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_MM_DISP_COLOR0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 164 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8365_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					color0_in: endpoint@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+						remote-endpoint = &lt;&amp;rdma0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					color0_out: endpoint@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+						remote-endpoint = &lt;&amp;ccorr0_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ccorr0: ccorr@14010000 {</div><div class='add'>+			compatible = "mediatek,mt8365-disp-ccorr", "mediatek,mt8183-disp-ccorr";</div><div class='add'>+			reg = &lt;0 0x14010000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_MM_DISP_CCORR0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 165 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8365_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					ccorr0_in: endpoint@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+						remote-endpoint = &lt;&amp;color0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					ccorr0_out: endpoint@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+						remote-endpoint = &lt;&amp;aal0_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aal0: aal@14011000 {</div><div class='add'>+			compatible = "mediatek,mt8365-disp-aal", "mediatek,mt8183-disp-aal";</div><div class='add'>+			reg = &lt;0 0x14011000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_MM_DISP_AAL0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 166 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8365_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					aal0_in: endpoint@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+						remote-endpoint = &lt;&amp;ccorr0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					aal0_out: endpoint@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+						remote-endpoint = &lt;&amp;gamma0_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gamma0: gamma@14012000 {</div><div class='add'>+			compatible = "mediatek,mt8365-disp-gamma", "mediatek,mt8183-disp-gamma";</div><div class='add'>+			reg = &lt;0 0x14012000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_MM_DISP_GAMMA0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 167 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8365_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					gamma0_in: endpoint@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+						remote-endpoint = &lt;&amp;aal0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					gamma0_out: endpoint@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+						remote-endpoint = &lt;&amp;dither0_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dither0: dither@14013000 {</div><div class='add'>+			compatible = "mediatek,mt8365-disp-dither", "mediatek,mt8183-disp-dither";</div><div class='add'>+			reg = &lt;0 0x14013000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_MM_DISP_DITHER0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 168 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8365_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					dither0_in: endpoint@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+						remote-endpoint = &lt;&amp;gamma0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					dither0_out: endpoint@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dsi0: dsi@14014000 {</div><div class='add'>+			compatible = "mediatek,mt8365-dsi", "mediatek,mt8183-dsi";</div><div class='add'>+			reg = &lt;0 0x14014000 0 0x1000&gt;;</div><div class='add'>+			clock-names = "engine", "digital", "hs";</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_MM_DSI0&gt;,</div><div class='add'>+				 &lt;&amp;mmsys CLK_MM_DSI0_DIG_DSI&gt;,</div><div class='add'>+				 &lt;&amp;mipi_tx0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 169 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			phy-names = "dphy";</div><div class='add'>+			phys = &lt;&amp;mipi_tx0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8365_POWER_DOMAIN_MM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rdma1: rdma@14016000 {</div><div class='add'>+			compatible = "mediatek,mt8365-disp-rdma", "mediatek,mt8183-disp-rdma";</div><div class='add'>+			reg = &lt;0 0x14016000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_MM_DISP_RDMA1&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 195 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			iommus = &lt;&amp;iommu M4U_PORT_DISP_RDMA1&gt;;</div><div class='add'>+			mediatek,rdma-fifo-size = &lt;2048&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8365_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					rdma1_in: endpoint@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+						remote-endpoint = &lt;&amp;mmsys_ext&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					rdma1_out: endpoint@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dpi0: dpi@14018000 {</div><div class='add'>+			compatible = "mediatek,mt8365-dpi", "mediatek,mt8192-dpi";</div><div class='add'>+			reg = &lt;0 0x14018000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_DPI0_DPI0&gt;,</div><div class='add'>+				 &lt;&amp;mmsys CLK_MM_MM_DPI0&gt;,</div><div class='add'>+				 &lt;&amp;apmixedsys CLK_APMIXED_LVDSPLL&gt;;</div><div class='add'>+			clock-names = "pixel", "engine", "pll";</div><div class='add'>+			interrupts = &lt;GIC_SPI 197 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8365_POWER_DOMAIN_MM&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		camsys: syscon@15000000 {</div><div class='add'>+			compatible = "mediatek,mt8365-imgsys", "syscon";</div><div class='add'>+			reg = &lt;0 0x15000000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb2: larb@15001000 {</div><div class='add'>+			compatible = "mediatek,mt8365-smi-larb",</div><div class='add'>+				     "mediatek,mt8186-smi-larb";</div><div class='add'>+			reg = &lt;0 0x15001000 0 0x1000&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+			clocks = &lt;&amp;mmsys CLK_MM_MM_SMI_IMG&gt;,</div><div class='add'>+				 &lt;&amp;camsys CLK_CAM_LARB2&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8365_POWER_DOMAIN_CAM&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vdecsys: syscon@16000000 {</div><div class='add'>+			compatible = "mediatek,mt8365-vdecsys", "syscon";</div><div class='add'>+			reg = &lt;0 0x16000000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb3: larb@16010000 {</div><div class='add'>+			compatible = "mediatek,mt8365-smi-larb",</div><div class='add'>+				     "mediatek,mt8186-smi-larb";</div><div class='add'>+			reg = &lt;0 0x16010000 0 0x1000&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+			clocks = &lt;&amp;vdecsys CLK_VDEC_LARB1&gt;,</div><div class='add'>+				 &lt;&amp;vdecsys CLK_VDEC_LARB1&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8365_POWER_DOMAIN_VDEC&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;3&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vencsys: syscon@17000000 {</div><div class='add'>+			compatible = "mediatek,mt8365-vencsys", "syscon";</div><div class='add'>+			reg = &lt;0 0x17000000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		larb1: larb@17010000 {</div><div class='add'>+			compatible = "mediatek,mt8365-smi-larb",</div><div class='add'>+				     "mediatek,mt8186-smi-larb";</div><div class='add'>+			reg = &lt;0 0x17010000 0 0x1000&gt;;</div><div class='add'>+			mediatek,smi = &lt;&amp;smi_common&gt;;</div><div class='add'>+			clocks = &lt;&amp;vencsys CLK_VENC&gt;, &lt;&amp;vencsys CLK_VENC&gt;;</div><div class='add'>+			clock-names = "apb", "smi";</div><div class='add'>+			power-domains = &lt;&amp;spm MT8365_POWER_DOMAIN_VENC&gt;;</div><div class='add'>+			mediatek,larb-id = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		apu: syscon@19020000 {</div><div class='add'>+			compatible = "mediatek,mt8365-apu", "syscon";</div><div class='add'>+			reg = &lt;0 0x19020000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		afe: audio-controller@11220000 {</div><div class='add'>+			compatible = "mediatek,mt8365-afe-pcm";</div><div class='add'>+			reg = &lt;0 0x11220000 0 0x1000&gt;;</div><div class='add'>+			#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk26m&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_AUDIO_SEL&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_AUD_I2S0_M&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_AUD_I2S1_M&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_AUD_I2S2_M&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_AUD_I2S3_M&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_AUD_ENGEN1_SEL&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_AUD_ENGEN2_SEL&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_AUD_1_SEL&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_AUD_2_SEL&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_APLL_I2S0_SEL&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_APLL_I2S1_SEL&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_APLL_I2S2_SEL&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_APLL_I2S3_SEL&gt;;</div><div class='add'>+			clock-names = "top_clk26m_clk",</div><div class='add'>+				      "top_audio_sel",</div><div class='add'>+				      "audio_i2s0_m",</div><div class='add'>+				      "audio_i2s1_m",</div><div class='add'>+				      "audio_i2s2_m",</div><div class='add'>+				      "audio_i2s3_m",</div><div class='add'>+				      "engen1",</div><div class='add'>+				      "engen2",</div><div class='add'>+				      "aud1",</div><div class='add'>+				      "aud2",</div><div class='add'>+				      "i2s0_m_sel",</div><div class='add'>+				      "i2s1_m_sel",</div><div class='add'>+				      "i2s2_m_sel",</div><div class='add'>+				      "i2s3_m_sel";</div><div class='add'>+			interrupts = &lt;GIC_SPI 97 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			power-domains = &lt;&amp;spm MT8365_POWER_DOMAIN_AUDIO&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	system_clk: dummy13m {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		clock-frequency = &lt;13000000&gt;;</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	systimer: timer@10017000 {</div><div class='add'>+		compatible = "mediatek,mt8365-systimer", "mediatek,mt6765-timer";</div><div class='add'>+		reg = &lt;0 0x10017000 0 0x100&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;system_clk&gt;;</div><div class='add'>+		clock-names = "clk13m";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8370-genio-510-evk.dts b/arch/arm64/boot/dts/mediatek/mt8370-genio-510-evk.dts<br/>new file mode 100644<br/>index 000000000000..71a8cbed1df6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8370-genio-510-evk.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8370-genio-510-evk.dts</a></div><div class='hunk'>@@ -0,0 +1,19 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2025 Collabora Ltd.</div><div class='add'>+ * Author: Louis-Alexis Eyraud &lt;louisalexis.eyraud@collabora.com&gt;</div><div class='add'>+ */</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "mt8370.dtsi"</div><div class='add'>+#include "mt8390-genio-common.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "MediaTek Genio-510 EVK";</div><div class='add'>+	compatible = "mediatek,mt8370-evk", "mediatek,mt8370", "mediatek,mt8188";</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0 0x40000000 0x1 0x00000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8370-grinn-genio-510-sbc.dts b/arch/arm64/boot/dts/mediatek/mt8370-grinn-genio-510-sbc.dts<br/>new file mode 100644<br/>index 000000000000..92ff80e60974<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8370-grinn-genio-510-sbc.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8370-grinn-genio-510-sbc.dts</a></div><div class='hunk'>@@ -0,0 +1,20 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2025 Grinn sp. z o.o.</div><div class='add'>+ * Author: Bartosz Bilas &lt;bartosz.bilas@grinn-global.com&gt;</div><div class='add'>+ */</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "mt8370.dtsi"</div><div class='add'>+#include "mt8390-grinn-genio-som.dtsi"</div><div class='add'>+#include "mt8390-grinn-genio-sbc.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Grinn GenioSBC-510";</div><div class='add'>+	compatible = "grinn,genio-510-sbc", "mediatek,mt8370", "mediatek,mt8188";</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0 0x40000000 1 0x00000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8370.dtsi b/arch/arm64/boot/dts/mediatek/mt8370.dtsi<br/>new file mode 100644<br/>index 000000000000..7ac8b8d03494<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8370.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8370.dtsi</a></div><div class='hunk'>@@ -0,0 +1,80 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2025 Collabora Ltd.</div><div class='add'>+ * Author: Louis-Alexis Eyraud &lt;louisalexis.eyraud@collabora.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "mt8188.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "mediatek,mt8370";</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		/delete-node/ cpu@400;</div><div class='add'>+		/delete-node/ cpu@500;</div><div class='add'>+</div><div class='add'>+		cpu-map {</div><div class='add'>+			cluster0 {</div><div class='add'>+				/delete-node/ core4;</div><div class='add'>+				/delete-node/ core5;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu6 {</div><div class='add'>+	clock-frequency = &lt;2200000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu7 {</div><div class='add'>+	clock-frequency = &lt;2200000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu_little0_cooling_map0 {</div><div class='add'>+	cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+				&lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+				&lt;&amp;cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+				&lt;&amp;cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu_little1_cooling_map0 {</div><div class='add'>+	cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+				&lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+				&lt;&amp;cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+				&lt;&amp;cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu_little2_cooling_map0 {</div><div class='add'>+	cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+				&lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+				&lt;&amp;cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+				&lt;&amp;cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu_little3_cooling_map0 {</div><div class='add'>+	cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+				&lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+				&lt;&amp;cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+				&lt;&amp;cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Please note that overriding compatibles is a discouraged practice and is a</div><div class='add'>+ * clear indication of nodes not being, well, compatible!</div><div class='add'>+ *</div><div class='add'>+ * This is a special case, where the GPU is the same as MT8188, but with one</div><div class='add'>+ * of the cores fused out in this lower-binned SoC.</div><div class='add'>+ */</div><div class='add'>+&amp;gpu {</div><div class='add'>+	compatible = "mediatek,mt8370-mali", "arm,mali-valhall-jm";</div><div class='add'>+</div><div class='add'>+	power-domains = &lt;&amp;spm MT8188_POWER_DOMAIN_MFG2&gt;,</div><div class='add'>+			&lt;&amp;spm MT8188_POWER_DOMAIN_MFG3&gt;;</div><div class='add'>+</div><div class='add'>+	power-domain-names = "core0", "core1";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ppi_cluster0 {</div><div class='add'>+	affinity = &lt;&amp;cpu0 &amp;cpu1 &amp;cpu2 &amp;cpu3&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts b/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts<br/>new file mode 100644<br/>index 000000000000..612336713a64<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts</a></div><div class='hunk'>@@ -0,0 +1,23 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2023 MediaTek Inc.</div><div class='add'>+ * Author: Chris Chen &lt;chris-qj.chen@mediatek.com&gt;</div><div class='add'>+ *	   Pablo Sun &lt;pablo.sun@mediatek.com&gt;</div><div class='add'>+ *	   Macpaul Lin &lt;macpaul.lin@mediatek.com&gt;</div><div class='add'>+ */</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "mt8188.dtsi"</div><div class='add'>+#include "mt8390-genio-common.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "MediaTek Genio-700 EVK";</div><div class='add'>+	compatible = "mediatek,mt8390-evk", "mediatek,mt8390",</div><div class='add'>+		     "mediatek,mt8188";</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0 0x40000000 0x2 0x00000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi<br/>new file mode 100644<br/>index 000000000000..a2cdecd2b903<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi</a></div><div class='hunk'>@@ -0,0 +1,1370 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2023 MediaTek Inc.</div><div class='add'>+ * Author: Chris Chen &lt;chris-qj.chen@mediatek.com&gt;</div><div class='add'>+ *         Pablo Sun &lt;pablo.sun@mediatek.com&gt;</div><div class='add'>+ *         Macpaul Lin &lt;macpaul.lin@mediatek.com&gt;</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) 2025 Collabora Ltd.</div><div class='add'>+ *                    Louis-Alexis Eyraud &lt;louisalexis.eyraud@collabora.com&gt;</div><div class='add'>+ *                    AngeloGioacchino Del Regno &lt;angelogioacchino.delregno@collabora.com&gt;   </div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "mt6359.dtsi"</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/regulator/mediatek,mt6360-regulator.h&gt;</div><div class='add'>+#include &lt;dt-bindings/spmi/spmi.h&gt;</div><div class='add'>+#include &lt;dt-bindings/usb/pd.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		dsi0 = &amp;disp_dsi0;</div><div class='add'>+		ethernet0 = &amp;eth;</div><div class='add'>+		i2c0 = &amp;i2c0;</div><div class='add'>+		i2c1 = &amp;i2c1;</div><div class='add'>+		i2c2 = &amp;i2c2;</div><div class='add'>+		i2c3 = &amp;i2c3;</div><div class='add'>+		i2c4 = &amp;i2c4;</div><div class='add'>+		i2c5 = &amp;i2c5;</div><div class='add'>+		i2c6 = &amp;i2c6;</div><div class='add'>+		mmc0 = &amp;mmc0;</div><div class='add'>+		mmc1 = &amp;mmc1;</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	backlight_lcm1: backlight-lcm1 {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		brightness-levels = &lt;0 1023&gt;;</div><div class='add'>+		default-brightness-level = &lt;576&gt;;</div><div class='add'>+		num-interpolated-steps = &lt;1023&gt;;</div><div class='add'>+		power-supply = &lt;&amp;reg_vsys&gt;;</div><div class='add'>+		pwms = &lt;&amp;disp_pwm1 0 500000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:921600n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dmic_codec: dmic-codec {</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		compatible = "dmic-codec";</div><div class='add'>+		num-channels = &lt;2&gt;;</div><div class='add'>+		wakeup-delay-ms = &lt;30&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	firmware {</div><div class='add'>+		optee {</div><div class='add'>+			compatible = "linaro,optee-tz";</div><div class='add'>+			method = "smc";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * 12 MiB reserved for OP-TEE (BL32)</div><div class='add'>+		 * +-----------------------+ 0x43e0_0000</div><div class='add'>+		 * |      SHMEM 2MiB       |</div><div class='add'>+		 * +-----------------------+ 0x43c0_0000</div><div class='add'>+		 * |        | TA_RAM  8MiB |</div><div class='add'>+		 * + TZDRAM +--------------+ 0x4340_0000</div><div class='add'>+		 * |        | TEE_RAM 2MiB |</div><div class='add'>+		 * +-----------------------+ 0x4320_0000</div><div class='add'>+		 */</div><div class='add'>+		optee_reserved: optee@43200000 {</div><div class='add'>+			no-map;</div><div class='add'>+			reg = &lt;0 0x43200000 0 0x00c00000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		scp_mem: memory@50000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x50000000 0 0x2900000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* 2 MiB reserved for ARM Trusted Firmware (BL31) */</div><div class='add'>+		bl31_secmon_reserved: memory@54600000 {</div><div class='add'>+			no-map;</div><div class='add'>+			reg = &lt;0 0x54600000 0x0 0x200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		apu_mem: memory@55000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x55000000 0 0x1400000&gt;; /* 20 MB */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vpu_mem: memory@57000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x57000000 0 0x1400000&gt;; /* 20 MB */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		adsp_mem: memory@60000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x60000000 0 0xf00000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		afe_dma_mem: memory@60f00000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x60f00000 0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		adsp_dma_mem: memory@61000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x61000000 0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	common_fixed_5v: regulator-0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vdd_5v";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;pio 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		vin-supply = &lt;&amp;reg_vsys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	edp_panel_fixed_3v3: regulator-1 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vedp_3v3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;pio 15 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;edp_panel_3v3_en_pins&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;reg_vsys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio_fixed_3v3: regulator-2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "ext_3v3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;pio 9 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		vin-supply = &lt;&amp;reg_vsys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* system wide 4.2V power rail from charger */</div><div class='add'>+	reg_vsys: regulator-vsys {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vsys";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* used by mmc2 */</div><div class='add'>+	sdio_fixed_1v8: regulator-3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vio18_conn";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* used by mmc2 */</div><div class='add'>+	sdio_fixed_3v3: regulator-4 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "wifi_3v3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;pio 74 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		vin-supply = &lt;&amp;reg_vsys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	touch0_fixed_3v3: regulator-5 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vio33_tp1";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;pio 119 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		vin-supply = &lt;&amp;reg_vsys&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;touch_vreg_pins&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb_hub_fixed_3v3: regulator-6 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vhub_3v3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;pio 112 GPIO_ACTIVE_HIGH&gt;; /* HUB_3V3_EN */</div><div class='add'>+		startup-delay-us = &lt;10000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		vin-supply = &lt;&amp;reg_vsys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb_p0_vbus: regulator-7 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vbus_p0";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;pio 84 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		vin-supply = &lt;&amp;reg_vsys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb_p1_vbus: regulator-8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vbus_p1";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;pio 87 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		vin-supply = &lt;&amp;reg_vsys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* used by ssusb2 */</div><div class='add'>+	usb_p2_vbus: regulator-9 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vbus_p2";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lcm1_iovcc: regulator-vio18-lcm1 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vio18_lcm1";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;pio 111 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;dsi0_vreg_en_pins&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;reg_vsys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lcm1_vddp: regulator-vsys-lcm1 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vsys_lcm1";</div><div class='add'>+		regulator-min-microvolt = &lt;4200000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;4200000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		vin-supply = &lt;&amp;reg_vsys&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;adsp {</div><div class='add'>+	memory-region = &lt;&amp;adsp_dma_mem&gt;, &lt;&amp;adsp_mem&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;afe {</div><div class='add'>+	memory-region = &lt;&amp;afe_dma_mem&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;disp_dsi0 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	panel@0 {</div><div class='add'>+		compatible = "startek,kd070fhfid078", "himax,hx8279";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		backlight = &lt;&amp;backlight_lcm1&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;pio 45 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pio 25 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		iovcc-supply = &lt;&amp;lcm1_iovcc&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;lcm1_vddp&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;panel_default_pins&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			dsi_panel_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;dsi0_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		port@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			dsi0_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;dither0_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			dsi0_out: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;dsi_panel_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;disp_pwm1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;disp_pwm1_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dither0_in {</div><div class='add'>+	remote-endpoint = &lt;&amp;postmask0_out&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dither0_out {</div><div class='add'>+	remote-endpoint = &lt;&amp;dsi0_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gamma0_out {</div><div class='add'>+	remote-endpoint = &lt;&amp;postmask0_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	mali-supply = &lt;&amp;mt6359_vproc2_buck_reg&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c0_pins&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	touchscreen@5d {</div><div class='add'>+		compatible = "goodix,gt9271";</div><div class='add'>+		reg = &lt;0x5d&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;pio&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 6 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+		irq-gpios = &lt;&amp;pio 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pio 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		AVDD28-supply = &lt;&amp;touch0_fixed_3v3&gt;;</div><div class='add'>+		VDDIO-supply = &lt;&amp;mt6359_vio18_ldo_reg&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;touch_pins&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c1_pins&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	typec-mux@48 {</div><div class='add'>+		compatible = "ite,it5205";</div><div class='add'>+		reg = &lt;0x48&gt;;</div><div class='add'>+</div><div class='add'>+		mode-switch;</div><div class='add'>+		orientation-switch;</div><div class='add'>+</div><div class='add'>+		vcc-supply = &lt;&amp;mt6359_vcn33_1_bt_ldo_reg&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			it5205_sbu_mux: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;typec_sbu_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c2_pins&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c3_pins&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c4_pins&gt;;</div><div class='add'>+	clock-frequency = &lt;1000000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	rt1715@4e {</div><div class='add'>+		compatible = "richtek,rt1715";</div><div class='add'>+		reg = &lt;0x4e&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 12 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;tcpci_int_pins&gt;;</div><div class='add'>+		vbus-supply = &lt;&amp;usb_p1_vbus&gt;;</div><div class='add'>+</div><div class='add'>+		connector {</div><div class='add'>+			compatible = "usb-c-connector";</div><div class='add'>+			label = "USB-C";</div><div class='add'>+			data-role = "dual";</div><div class='add'>+			op-sink-microwatt = &lt;10000000&gt;;</div><div class='add'>+			power-role = "dual";</div><div class='add'>+			try-power-role  = "sink";</div><div class='add'>+			pd-revision = /bits/ 8 &lt;0x03 0x00 0x01 0x08&gt;;</div><div class='add'>+</div><div class='add'>+			sink-pdos = &lt;PDO_FIXED(5000, 2000,</div><div class='add'>+					       PDO_FIXED_DUAL_ROLE |</div><div class='add'>+					       PDO_FIXED_DATA_SWAP)&gt;;</div><div class='add'>+			source-pdos = &lt;PDO_FIXED(5000, 2000,</div><div class='add'>+						 PDO_FIXED_DUAL_ROLE |</div><div class='add'>+						 PDO_FIXED_DATA_SWAP)&gt;;</div><div class='add'>+</div><div class='add'>+			altmodes {</div><div class='add'>+				displayport {</div><div class='add'>+					svid = /bits/ 16 &lt;0xff01&gt;;</div><div class='add'>+					vdo = &lt;0x001c1c47&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					typec_con_hs: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mtu3_hs1_role_sw&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					typec_con_ss: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;xhci_ss_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@2 {</div><div class='add'>+					reg = &lt;2&gt;;</div><div class='add'>+					typec_sbu_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;it5205_sbu_mux&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c5 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c5_pins&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c6 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c6_pins&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mfg0 {</div><div class='add'>+	domain-supply = &lt;&amp;mt6359_vproc2_buck_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mfg1 {</div><div class='add'>+	domain-supply = &lt;&amp;mt6359_vsram_others_ldo_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_tx_config0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-names = "default", "state_uhs";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc0_default_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;mmc0_uhs_pins&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	cap-mmc-highspeed;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	mmc-hs400-1_8v;</div><div class='add'>+	supports-cqe;</div><div class='add'>+	cap-mmc-hw-reset;</div><div class='add'>+	no-sdio;</div><div class='add'>+	no-sd;</div><div class='add'>+	hs400-ds-delay = &lt;0x1481b&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;mt6359_vemc_1_ldo_reg&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;mt6359_vufs_ldo_reg&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-names = "default", "state_uhs";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc1_default_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;mmc1_uhs_pins&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	sd-uhs-sdr50;</div><div class='add'>+	sd-uhs-sdr104;</div><div class='add'>+	no-mmc;</div><div class='add'>+	no-sdio;</div><div class='add'>+	cd-gpios = &lt;&amp;pio 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;mt6359_vpa_buck_reg&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;mt6359_vsim1_ldo_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vbbck_ldo_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vcn18_ldo_reg {</div><div class='add'>+	regulator-name = "vcn18_pmu";</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vcn33_2_bt_ldo_reg {</div><div class='add'>+	regulator-name = "vcn33_2_pmu";</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vcore_buck_reg {</div><div class='add'>+	regulator-name = "dvdd_proc_l";</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vgpu11_buck_reg {</div><div class='add'>+	regulator-name = "dvdd_core";</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vpa_buck_reg {</div><div class='add'>+	regulator-name = "vpa_pmu";</div><div class='add'>+	regulator-max-microvolt = &lt;3100000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vproc2_buck_reg {</div><div class='add'>+	/* The name "vgpu" is required by mtk-regulator-coupler */</div><div class='add'>+	regulator-name = "vgpu";</div><div class='add'>+	regulator-min-microvolt = &lt;550000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;800000&gt;;</div><div class='add'>+	regulator-coupled-with = &lt;&amp;mt6359_vsram_others_ldo_reg&gt;;</div><div class='add'>+	regulator-coupled-max-spread = &lt;6250&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vpu_buck_reg {</div><div class='add'>+	regulator-name = "dvdd_adsp";</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vrf12_ldo_reg {</div><div class='add'>+	regulator-name = "va12_abb2_pmu";</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vsim1_ldo_reg {</div><div class='add'>+	regulator-name = "vsim1_pmu";</div><div class='add'>+	regulator-enable-ramp-delay = &lt;480&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vsram_others_ldo_reg {</div><div class='add'>+	/* The name "vsram_gpu" is required by mtk-regulator-coupler */</div><div class='add'>+	regulator-name = "vsram_gpu";</div><div class='add'>+	regulator-min-microvolt = &lt;750000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;800000&gt;;</div><div class='add'>+	regulator-coupled-with = &lt;&amp;mt6359_vproc2_buck_reg&gt;;</div><div class='add'>+	regulator-coupled-max-spread = &lt;6250&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vufs_ldo_reg {</div><div class='add'>+	regulator-name = "vufs18_pmu";</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359codec {</div><div class='add'>+	mediatek,mic-type-0 = &lt;1&gt;; /* ACC */</div><div class='add'>+	mediatek,mic-type-1 = &lt;3&gt;; /* DCC */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ovl0_in {</div><div class='add'>+	remote-endpoint = &lt;&amp;vdosys0_ep_main&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pcie_default_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pciephy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	audio_default_pins: audio-default-pins {</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO101__FUNC_O_AUD_CLK_MOSI&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO102__FUNC_O_AUD_SYNC_MOSI&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO103__FUNC_O_AUD_DAT_MOSI0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO104__FUNC_O_AUD_DAT_MOSI1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO105__FUNC_I0_AUD_DAT_MISO0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO106__FUNC_I0_AUD_DAT_MISO1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO107__FUNC_B0_I2SIN_MCK&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO108__FUNC_B0_I2SIN_BCK&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO109__FUNC_B0_I2SIN_WS&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO110__FUNC_I0_I2SIN_D0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO114__FUNC_O_I2SO2_MCK&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO115__FUNC_B0_I2SO2_BCK&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO116__FUNC_B0_I2SO2_WS&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO117__FUNC_O_I2SO2_D0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO118__FUNC_O_I2SO2_D1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO121__FUNC_B0_PCM_CLK&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO122__FUNC_B0_PCM_SYNC&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO124__FUNC_I0_PCM_DI&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO125__FUNC_O_DMIC1_CLK&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO126__FUNC_I0_DMIC1_DAT&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO128__FUNC_O_DMIC2_CLK&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO129__FUNC_I0_DMIC2_DAT&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	disp_pwm1_pins: disp-pwm1-pins {</div><div class='add'>+		pins-pwm {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO30__FUNC_O_DISP_PWM1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dptx_pins: dptx-pins {</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO46__FUNC_I0_DP_TX_HPD&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	edp_panel_3v3_en_pins: edp-panel-3v3-en-pins {</div><div class='add'>+		pins1 {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO15__FUNC_B_GPIO15&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eth_default_pins: eth-default-pins {</div><div class='add'>+		pins-cc {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO139__FUNC_B0_GBE_TXC&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO140__FUNC_I0_GBE_RXC&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO141__FUNC_I0_GBE_RXDV&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO142__FUNC_O_GBE_TXEN&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-mdio {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO143__FUNC_O_GBE_MDC&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO144__FUNC_B1_GBE_MDIO&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-power {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO145__FUNC_B_GPIO145&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO146__FUNC_B_GPIO146&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-rxd {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO135__FUNC_I0_GBE_RXD3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO136__FUNC_I0_GBE_RXD2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO137__FUNC_I0_GBE_RXD1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO138__FUNC_I0_GBE_RXD0&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-txd {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO131__FUNC_O_GBE_TXD3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO132__FUNC_O_GBE_TXD2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO133__FUNC_O_GBE_TXD1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO134__FUNC_O_GBE_TXD0&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eth_sleep_pins: eth-sleep-pins {</div><div class='add'>+		pins-cc {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO139__FUNC_B_GPIO139&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO140__FUNC_B_GPIO140&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO141__FUNC_B_GPIO141&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO142__FUNC_B_GPIO142&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-mdio {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO143__FUNC_B_GPIO143&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO144__FUNC_B_GPIO144&gt;;</div><div class='add'>+			input-disable;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-rxd {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO135__FUNC_B_GPIO135&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO136__FUNC_B_GPIO136&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO137__FUNC_B_GPIO137&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO138__FUNC_B_GPIO138&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-txd {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO131__FUNC_B_GPIO131&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO132__FUNC_B_GPIO132&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO133__FUNC_B_GPIO133&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO134__FUNC_B_GPIO134&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c0_pins: i2c0-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO56__FUNC_B1_SDA0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO55__FUNC_B1_SCL0&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PULL_SET_RSEL_011&gt;;</div><div class='add'>+			drive-strength-microamp = &lt;1000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c1_pins: i2c1-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO58__FUNC_B1_SDA1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO57__FUNC_B1_SCL1&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PULL_SET_RSEL_011&gt;;</div><div class='add'>+			drive-strength-microamp = &lt;1000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c2_pins: i2c2-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO60__FUNC_B1_SDA2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO59__FUNC_B1_SCL2&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PULL_SET_RSEL_011&gt;;</div><div class='add'>+			drive-strength-microamp = &lt;1000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c3_pins: i2c3-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO62__FUNC_B1_SDA3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO61__FUNC_B1_SCL3&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PULL_SET_RSEL_011&gt;;</div><div class='add'>+			drive-strength-microamp = &lt;1000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c4_pins: i2c4-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO64__FUNC_B1_SDA4&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO63__FUNC_B1_SCL4&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PULL_SET_RSEL_011&gt;;</div><div class='add'>+			drive-strength-microamp = &lt;1000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c5_pins: i2c5-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO66__FUNC_B1_SDA5&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO65__FUNC_B1_SCL5&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PULL_SET_RSEL_011&gt;;</div><div class='add'>+			drive-strength-microamp = &lt;1000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c6_pins: i2c6-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO68__FUNC_B1_SDA6&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO67__FUNC_B1_SCL6&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PULL_SET_RSEL_011&gt;;</div><div class='add'>+			drive-strength-microamp = &lt;1000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio_key_pins: gpio-key-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO42__FUNC_B1_KPCOL0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO43__FUNC_B1_KPCOL1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO44__FUNC_B1_KPROW0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc0_default_pins: mmc0-default-pins {</div><div class='add'>+		pins-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO157__FUNC_B1_MSDC0_CLK&gt;;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO161__FUNC_B1_MSDC0_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO160__FUNC_B1_MSDC0_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO159__FUNC_B1_MSDC0_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO158__FUNC_B1_MSDC0_DAT3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO154__FUNC_B1_MSDC0_DAT4&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO153__FUNC_B1_MSDC0_DAT5&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO152__FUNC_B1_MSDC0_DAT6&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO151__FUNC_B1_MSDC0_DAT7&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO156__FUNC_B1_MSDC0_CMD&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-rst {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO155__FUNC_O_MSDC0_RSTB&gt;;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc0_uhs_pins: mmc0-uhs-pins {</div><div class='add'>+		pins-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO157__FUNC_B1_MSDC0_CLK&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO161__FUNC_B1_MSDC0_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO160__FUNC_B1_MSDC0_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO159__FUNC_B1_MSDC0_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO158__FUNC_B1_MSDC0_DAT3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO154__FUNC_B1_MSDC0_DAT4&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO153__FUNC_B1_MSDC0_DAT5&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO152__FUNC_B1_MSDC0_DAT6&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO151__FUNC_B1_MSDC0_DAT7&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO156__FUNC_B1_MSDC0_CMD&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-ds {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO162__FUNC_B0_MSDC0_DSL&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-rst {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO155__FUNC_O_MSDC0_RSTB&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc1_default_pins: mmc1-default-pins {</div><div class='add'>+		pins-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO164__FUNC_B1_MSDC1_CLK&gt;;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO163__FUNC_B1_MSDC1_CMD&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO165__FUNC_B1_MSDC1_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO166__FUNC_B1_MSDC1_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO167__FUNC_B1_MSDC1_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO168__FUNC_B1_MSDC1_DAT3&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-insert {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO2__FUNC_B_GPIO2&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc1_uhs_pins: mmc1-uhs-pins {</div><div class='add'>+		pins-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO164__FUNC_B1_MSDC1_CLK&gt;;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO163__FUNC_B1_MSDC1_CMD&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO165__FUNC_B1_MSDC1_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO166__FUNC_B1_MSDC1_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO167__FUNC_B1_MSDC1_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO168__FUNC_B1_MSDC1_DAT3&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc2_default_pins: mmc2-default-pins {</div><div class='add'>+		pins-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO170__FUNC_B1_MSDC2_CLK&gt;;</div><div class='add'>+			drive-strength = &lt;4&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO169__FUNC_B1_MSDC2_CMD&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO171__FUNC_B1_MSDC2_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO172__FUNC_B1_MSDC2_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO173__FUNC_B1_MSDC2_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO174__FUNC_B1_MSDC2_DAT3&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-pcm {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO123__FUNC_O_PCM_DO&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc2_uhs_pins: mmc2-uhs-pins {</div><div class='add'>+		pins-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO170__FUNC_B1_MSDC2_CLK&gt;;</div><div class='add'>+			drive-strength = &lt;4&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO169__FUNC_B1_MSDC2_CMD&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO171__FUNC_B1_MSDC2_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO172__FUNC_B1_MSDC2_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO173__FUNC_B1_MSDC2_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO174__FUNC_B1_MSDC2_DAT3&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc2_eint_pins: mmc2-eint-pins {</div><div class='add'>+		pins-dat1 {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO172__FUNC_B_GPIO172&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc2_dat1_pins: mmc2-dat1-pins {</div><div class='add'>+		pins-dat1 {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO172__FUNC_B1_MSDC2_DAT1&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dsi0_vreg_en_pins: dsi0-vreg-en-pins {</div><div class='add'>+		pins-pwr-en {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO111__FUNC_B_GPIO111&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	panel_default_pins: panel-default-pins {</div><div class='add'>+		pins-rst {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO25__FUNC_B_GPIO25&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-en {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO45__FUNC_B_GPIO45&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie_default_pins: pcie-default-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO47__FUNC_I1_WAKEN&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO48__FUNC_O_PERSTN&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO49__FUNC_B1_CLKREQN&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rt1715_int_pins: rt1715-int-pins {</div><div class='add'>+		pins_cmd0_dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO12__FUNC_B_GPIO12&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi0_pins: spi0-pins {</div><div class='add'>+		pins-spi {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO69__FUNC_O_SPIM0_CSB&gt;,</div><div class='add'>+				&lt;PINMUX_GPIO70__FUNC_O_SPIM0_CLK&gt;,</div><div class='add'>+				&lt;PINMUX_GPIO71__FUNC_B0_SPIM0_MOSI&gt;,</div><div class='add'>+				&lt;PINMUX_GPIO72__FUNC_B0_SPIM0_MISO&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi1_pins: spi1-pins {</div><div class='add'>+		pins-spi {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO75__FUNC_O_SPIM1_CSB&gt;,</div><div class='add'>+				&lt;PINMUX_GPIO76__FUNC_O_SPIM1_CLK&gt;,</div><div class='add'>+				&lt;PINMUX_GPIO77__FUNC_B0_SPIM1_MOSI&gt;,</div><div class='add'>+				&lt;PINMUX_GPIO78__FUNC_B0_SPIM1_MISO&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi2_pins: spi2-pins {</div><div class='add'>+		pins-spi {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO79__FUNC_O_SPIM2_CSB&gt;,</div><div class='add'>+				&lt;PINMUX_GPIO80__FUNC_O_SPIM2_CLK&gt;,</div><div class='add'>+				&lt;PINMUX_GPIO81__FUNC_B0_SPIM2_MOSI&gt;,</div><div class='add'>+				&lt;PINMUX_GPIO82__FUNC_B0_SPIM2_MISO&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	touch_vreg_pins: touch-avdd-pins {</div><div class='add'>+		pins-power {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO120__FUNC_B_GPIO120&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	touch_pins: touch-pins {</div><div class='add'>+		pins-irq {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO6__FUNC_B_GPIO6&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-reset {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO5__FUNC_B_GPIO5&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	tcpci_int_pins: tcpci-int-pins {</div><div class='add'>+		pins-int-n {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO12__FUNC_B_GPIO12&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart0_pins: uart0-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO31__FUNC_O_UTXD0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO32__FUNC_I1_URXD0&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart1_pins: uart1-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO33__FUNC_O_UTXD1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO34__FUNC_I1_URXD1&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart2_pins: uart2-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO35__FUNC_O_UTXD2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO36__FUNC_I1_URXD2&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb_default_pins: usb-default-pins {</div><div class='add'>+		pins-iddig {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO83__FUNC_B_GPIO83&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-valid {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO85__FUNC_I0_VBUSVALID&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-vbus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO84__FUNC_O_USB_DRVVBUS&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb1_default_pins: usb1-default-pins {</div><div class='add'>+		pins-valid {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO88__FUNC_I0_VBUSVALID_1P&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-usb-hub-3v3-en {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO112__FUNC_B_GPIO112&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb2_default_pins: usb2-default-pins {</div><div class='add'>+		pins-iddig {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO89__FUNC_B_GPIO89&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wifi_pwrseq_pins: wifi-pwrseq-pins {</div><div class='add'>+		pins-wifi-enable {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO127__FUNC_B_GPIO127&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eth {</div><div class='add'>+	phy-mode ="rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethernet_phy0&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;eth_default_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;eth_sleep_pins&gt;;</div><div class='add'>+	mediatek,mac-wol;</div><div class='add'>+	snps,reset-gpio = &lt;&amp;pio 147 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	snps,reset-delays-us = &lt;0 10000 10000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eth_mdio {</div><div class='add'>+	ethernet_phy0: ethernet-phy@1 {</div><div class='add'>+		compatible = "ethernet-phy-id001c.c916";</div><div class='add'>+		reg = &lt;0x1&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pmic {</div><div class='add'>+	interrupt-parent = &lt;&amp;pio&gt;;</div><div class='add'>+	interrupts = &lt;222 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+	mt6359keys: keys {</div><div class='add'>+		compatible = "mediatek,mt6359-keys";</div><div class='add'>+		mediatek,long-press-mode = &lt;1&gt;;</div><div class='add'>+		power-off-time-sec = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		power-key {</div><div class='add'>+			linux,keycodes = &lt;KEY_POWER&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		home {</div><div class='add'>+			linux,keycodes = &lt;KEY_HOME&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;postmask0_in {</div><div class='add'>+	remote-endpoint = &lt;&amp;gamma0_out&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;postmask0_out {</div><div class='add'>+	remote-endpoint = &lt;&amp;dither0_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;scp_cluster {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;scp_c0 {</div><div class='add'>+	memory-region = &lt;&amp;scp_mem&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sound {</div><div class='add'>+	compatible = "mediatek,mt8390-mt6359-evk", "mediatek,mt8188-mt6359-evb";</div><div class='add'>+	model = "mt8390-evk";</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;audio_default_pins&gt;;</div><div class='add'>+	audio-routing =</div><div class='add'>+		"Headphone", "Headphone L",</div><div class='add'>+		"Headphone", "Headphone R",</div><div class='add'>+		"DMIC_INPUT", "AP DMIC",</div><div class='add'>+		"AP DMIC", "AUDGLB",</div><div class='add'>+		"AP DMIC", "MIC_BIAS_0",</div><div class='add'>+		"AP DMIC", "MIC_BIAS_2";</div><div class='add'>+	mediatek,adsp = &lt;&amp;adsp&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	dai-link-0 {</div><div class='add'>+		link-name = "DL_SRC_BE";</div><div class='add'>+</div><div class='add'>+		codec {</div><div class='add'>+			sound-dai = &lt;&amp;pmic 0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dai-link-1 {</div><div class='add'>+		link-name = "DMIC_BE";</div><div class='add'>+</div><div class='add'>+		codec {</div><div class='add'>+			sound-dai = &lt;&amp;dmic_codec&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi2 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;spi2_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	mediatek,pad-select = &lt;0&gt;;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart0_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart1_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart2_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;vdosys0 {</div><div class='add'>+	port {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		vdosys0_ep_main: endpoint@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			remote-endpoint = &lt;&amp;ovl0_in&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;u3phy0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;u3phy1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;u3phy2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ssusb0 {</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	maximum-speed = "high-speed";</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	wakeup-source;</div><div class='add'>+	vusb33-supply = &lt;&amp;mt6359_vusb_ldo_reg&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;usb_default_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	connector {</div><div class='add'>+		compatible = "gpio-usb-b-connector", "usb-b-connector";</div><div class='add'>+		type = "micro";</div><div class='add'>+		id-gpios = &lt;&amp;pio 83 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		vbus-supply = &lt;&amp;usb_p0_vbus&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xhci0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ssusb1 {</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	wakeup-source;</div><div class='add'>+	vusb33-supply = &lt;&amp;mt6359_vusb_ldo_reg&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;usb1_default_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	port {</div><div class='add'>+		mtu3_hs1_role_sw: endpoint {</div><div class='add'>+			remote-endpoint = &lt;&amp;typec_con_hs&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xhci1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	vusb33-supply = &lt;&amp;mt6359_vusb_ldo_reg&gt;;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	hub_2_0: hub@1 {</div><div class='add'>+		compatible = "usb451,8025";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		peer-hub = &lt;&amp;hub_3_0&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pio 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;usb_hub_fixed_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hub_3_0: hub@2 {</div><div class='add'>+		compatible = "usb451,8027";</div><div class='add'>+		reg = &lt;2&gt;;</div><div class='add'>+		peer-hub = &lt;&amp;hub_2_0&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pio 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;usb_hub_fixed_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	port {</div><div class='add'>+		xhci_ss_ep: endpoint {</div><div class='add'>+			remote-endpoint = &lt;&amp;typec_con_ss&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ssusb2 {</div><div class='add'>+	/*</div><div class='add'>+	 * the ssusb2 controller is one but we got two ports : one is routed</div><div class='add'>+	 * to the M.2 slot, the other is on the RPi header who does support</div><div class='add'>+	 * full OTG.</div><div class='add'>+	 * As the controller is shared between them, the role switch default</div><div class='add'>+	 * mode is set to host to make any peripheral inserted in the M.2</div><div class='add'>+	 * slot (i.e BT/WIFI module) be detected when the other port is</div><div class='add'>+	 * unused.</div><div class='add'>+	 */</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	maximum-speed = "high-speed";</div><div class='add'>+	role-switch-default-mode = "host";</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	vusb33-supply = &lt;&amp;mt6359_vusb_ldo_reg&gt;;</div><div class='add'>+	wakeup-source;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;usb2_default_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	connector {</div><div class='add'>+		compatible = "gpio-usb-b-connector", "usb-b-connector";</div><div class='add'>+		type = "micro";</div><div class='add'>+		id-gpios = &lt;&amp;pio 89 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		vbus-supply = &lt;&amp;usb_p2_vbus&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xhci2 {</div><div class='add'>+	vusb33-supply = &lt;&amp;mt6359_vusb_ldo_reg&gt;;</div><div class='add'>+	vbus-supply = &lt;&amp;sdio_fixed_3v3&gt;; /* wifi_3v3 */</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-700-sbc.dts b/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-700-sbc.dts<br/>new file mode 100644<br/>index 000000000000..4931d761bd1f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-700-sbc.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-700-sbc.dts</a></div><div class='hunk'>@@ -0,0 +1,20 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2025 Grinn sp. z o.o.</div><div class='add'>+ * Author: Mateusz Koza &lt;mateusz.koza@grinn-global.com&gt;</div><div class='add'>+ */</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "mt8188.dtsi"</div><div class='add'>+#include "mt8390-grinn-genio-som.dtsi"</div><div class='add'>+#include "mt8390-grinn-genio-sbc.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Grinn GenioSBC-700";</div><div class='add'>+	compatible = "grinn,genio-700-sbc", "mediatek,mt8390", "mediatek,mt8188";</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0 0x40000000 1 0x00000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-sbc.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-sbc.dtsi<br/>new file mode 100644<br/>index 000000000000..888248a75e93<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-sbc.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-sbc.dtsi</a></div><div class='hunk'>@@ -0,0 +1,538 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2025 Grinn sp. z o.o.</div><div class='add'>+ * Author: Mateusz Koza &lt;mateusz.koza@grinn-global.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	chassis-type = "embedded";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;eth;</div><div class='add'>+		i2c0 = &amp;i2c0;</div><div class='add'>+		i2c2 = &amp;i2c2;</div><div class='add'>+		i2c3 = &amp;i2c3;</div><div class='add'>+		i2c5 = &amp;i2c5;</div><div class='add'>+		i2c6 = &amp;i2c6;</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:921600n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	firmware {</div><div class='add'>+		optee {</div><div class='add'>+			compatible = "linaro,optee-tz";</div><div class='add'>+			method = "smc";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * 12 MiB reserved for OP-TEE (BL32)</div><div class='add'>+		 * +-----------------------+ 0x43e0_0000</div><div class='add'>+		 * |      SHMEM 2MiB       |</div><div class='add'>+		 * +-----------------------+ 0x43c0_0000</div><div class='add'>+		 * |        | TA_RAM  8MiB |</div><div class='add'>+		 * + TZDRAM +--------------+ 0x4340_0000</div><div class='add'>+		 * |        | TEE_RAM 2MiB |</div><div class='add'>+		 * +-----------------------+ 0x4320_0000</div><div class='add'>+		 */</div><div class='add'>+		optee_reserved: optee@43200000 {</div><div class='add'>+			no-map;</div><div class='add'>+			reg = &lt;0 0x43200000 0 0x00c00000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		scp_mem: memory@50000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x50000000 0 0x2900000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* 2 MiB reserved for ARM Trusted Firmware (BL31) */</div><div class='add'>+		bl31_secmon_reserved: memory@54600000 {</div><div class='add'>+			no-map;</div><div class='add'>+			reg = &lt;0 0x54600000 0x0 0x200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		apu_mem: memory@55000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x55000000 0 0x1400000&gt;; /* 20 MB */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vpu_mem: memory@57000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x57000000 0 0x1400000&gt;; /* 20 MB */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		adsp_mem: memory@60000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x60000000 0 0xf00000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		afe_dma_mem: memory@60f00000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x60f00000 0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		adsp_dma_mem: memory@61000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x61000000 0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_sbc_vsys: regulator-vsys {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vsys";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_fixed_5v: regulator-0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "fixed-5v0";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		vin-supply = &lt;&amp;reg_sbc_vsys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_fixed_4v2: regulator-1 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "fixed-4v2";</div><div class='add'>+		regulator-min-microvolt = &lt;4200000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;4200000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		vin-supply = &lt;&amp;reg_sbc_vsys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_fixed_3v3: regulator-2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "fixed-3v3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		vin-supply = &lt;&amp;reg_sbc_vsys&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+	/*  0 -  4   */ "RPI_GPIO0", "RPI_GPIO1", "", "", "RPI_GPIO4",</div><div class='add'>+	/*  5 -  9   */ "", "RPI_GPIO6", "", "", "RPI_GPIO9",</div><div class='add'>+	/* 10 - 14   */ "RPI_GPIO10", "RPI_GPIO11", "", "", "",</div><div class='add'>+	/* 15 - 19   */ "", "", "", "", "",</div><div class='add'>+	/* 20 - 24   */ "", "RPI_GPIO21", "", "RPI_GPIO23", "",</div><div class='add'>+	/* 25 - 29   */ "", "", "", "", "",</div><div class='add'>+	/* 30 - 34   */ "RPI_GPIO30", "", "", "", "",</div><div class='add'>+	/* 35 - 39   */ "RPI_GPIO35", "RPI_GPIO36", "", "", "",</div><div class='add'>+	/* 40 - 44   */ "", "", "", "", "",</div><div class='add'>+	/* 45 - 49   */ "", "", "", "", "",</div><div class='add'>+	/* 50 - 54   */ "", "", "", "", "",</div><div class='add'>+	/* 55 - 59   */ "RPI_GPIO55", "RPI_GPIO56", "", "", "RPI_GPIO59",</div><div class='add'>+	/* 60 - 64   */ "RPI_GPIO60", "", "", "", "",</div><div class='add'>+	/* 65 - 69   */ "", "", "", "", "RPI_GPIO69",</div><div class='add'>+	/* 70 - 74   */ "", "", "RPI_GPIO72", "RPI_GPIO73", "RPI_GPIO74",</div><div class='add'>+	/* 75 - 79   */ "", "", "", "", "RPI_GPIO79",</div><div class='add'>+	/* 80 - 84   */ "RPI_GPIO80", "RPI_GPIO81", "RPI_GPIO82", "", "",</div><div class='add'>+	/* 85 - 89   */ "", "", "", "", "",</div><div class='add'>+	/* 90 - 94   */ "", "", "", "", "",</div><div class='add'>+	/* 95 - 99   */ "", "", "", "", "",</div><div class='add'>+	/*100 - 104  */ "", "", "", "", "",</div><div class='add'>+	/*105 - 109  */ "", "", "", "", "",</div><div class='add'>+	/*110 - 114  */ "", "", "", "", "",</div><div class='add'>+	/*115 - 119  */ "", "", "", "", "",</div><div class='add'>+	/*120 - 124  */ "", "RPI_GPIO121", "RPI_GPIO122", "RPI_GPIO123", "RPI_GPIO124";</div><div class='add'>+</div><div class='add'>+	i2c0_pins: i2c0-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO56__FUNC_B1_SDA0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO55__FUNC_B1_SCL0&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PULL_SET_RSEL_011&gt;;</div><div class='add'>+			drive-strength-microamp = &lt;1000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c2_pins: i2c2-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO60__FUNC_B1_SDA2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO59__FUNC_B1_SCL2&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PULL_SET_RSEL_011&gt;;</div><div class='add'>+			drive-strength-microamp = &lt;1000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c3_pins: i2c3-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO62__FUNC_B1_SDA3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO61__FUNC_B1_SCL3&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PULL_SET_RSEL_011&gt;;</div><div class='add'>+			drive-strength-microamp = &lt;1000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c5_pins: i2c5-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO66__FUNC_B1_SDA5&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO65__FUNC_B1_SCL5&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PULL_SET_RSEL_011&gt;;</div><div class='add'>+			drive-strength-microamp = &lt;1000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c6_pins: i2c6-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO68__FUNC_B1_SDA6&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO67__FUNC_B1_SCL6&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PULL_SET_RSEL_011&gt;;</div><div class='add'>+			drive-strength-microamp = &lt;1000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart0_pins: uart0-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO31__FUNC_O_UTXD0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO32__FUNC_I1_URXD0&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart1_pins: uart1-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO86__FUNC_O_UTXD1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO87__FUNC_I1_URXD1&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart2_pins: uart2-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO35__FUNC_O_UTXD2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO36__FUNC_I1_URXD2&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie_pins_default: pcie-default {</div><div class='add'>+		mux {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO47__FUNC_I1_WAKEN&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO48__FUNC_O_PERSTN&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO49__FUNC_B1_CLKREQN&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eth_default_pins: eth-default-pins {</div><div class='add'>+		pins-cc {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO139__FUNC_B0_GBE_TXC&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO140__FUNC_I0_GBE_RXC&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO141__FUNC_I0_GBE_RXDV&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO142__FUNC_O_GBE_TXEN&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-mdio {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO143__FUNC_O_GBE_MDC&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO144__FUNC_B1_GBE_MDIO&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-power {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO145__FUNC_B_GPIO145&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO146__FUNC_B_GPIO146&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-rxd {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO135__FUNC_I0_GBE_RXD3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO136__FUNC_I0_GBE_RXD2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO137__FUNC_I0_GBE_RXD1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO138__FUNC_I0_GBE_RXD0&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-txd {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO131__FUNC_O_GBE_TXD3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO132__FUNC_O_GBE_TXD2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO133__FUNC_O_GBE_TXD1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO134__FUNC_O_GBE_TXD0&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eth_sleep_pins: eth-sleep-pins {</div><div class='add'>+		pins-cc {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO139__FUNC_B_GPIO139&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO140__FUNC_B_GPIO140&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO141__FUNC_B_GPIO141&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO142__FUNC_B_GPIO142&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-mdio {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO143__FUNC_B_GPIO143&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO144__FUNC_B_GPIO144&gt;;</div><div class='add'>+			input-disable;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-rxd {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO135__FUNC_B_GPIO135&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO136__FUNC_B_GPIO136&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO137__FUNC_B_GPIO137&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO138__FUNC_B_GPIO138&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-txd {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO131__FUNC_B_GPIO131&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO132__FUNC_B_GPIO132&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO133__FUNC_B_GPIO133&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO134__FUNC_B_GPIO134&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi2_pins: spi2-pins {</div><div class='add'>+		pins-spi {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO79__FUNC_O_SPIM2_CSB&gt;,</div><div class='add'>+				&lt;PINMUX_GPIO80__FUNC_O_SPIM2_CLK&gt;,</div><div class='add'>+				&lt;PINMUX_GPIO81__FUNC_B0_SPIM2_MOSI&gt;,</div><div class='add'>+				&lt;PINMUX_GPIO82__FUNC_B0_SPIM2_MISO&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	audio_default_pins: audio-default-pins {</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO121__FUNC_B0_PCM_CLK&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO122__FUNC_B0_PCM_SYNC&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO123__FUNC_O_PCM_DO&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO124__FUNC_I0_PCM_DI&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb_default_pins: usb-default-pins {</div><div class='add'>+		pins-valid {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO85__FUNC_I0_VBUSVALID&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eth {</div><div class='add'>+	phy-mode = "rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethernet_phy0&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;eth_default_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;eth_sleep_pins&gt;;</div><div class='add'>+	mediatek,mac-wol;</div><div class='add'>+	mediatek,tx-delay-ps = &lt;30&gt;;</div><div class='add'>+	snps,reset-active-low;</div><div class='add'>+	snps,reset-delays-us = &lt;0 11000 200000&gt;;</div><div class='add'>+	snps,reset-gpio = &lt;&amp;pio 147 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eth_mdio {</div><div class='add'>+	ethernet_phy0: ethernet-phy@3 {</div><div class='add'>+		compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+		reg = &lt;3&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 148 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		eee-broken-1000t;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c0_pins&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c2_pins&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c3_pins&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c5 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c5_pins&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c6 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c6_pins&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart0_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart1_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart2_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pcie_pins_default&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pciephy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;spi2_pins&gt;;</div><div class='add'>+	mediatek,pad-select = &lt;0&gt;;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;u3phy0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;u3phy1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;u3phy2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xhci1 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	vusb33-supply = &lt;&amp;mt6359_vusb_ldo_reg&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	hub_2_0: hub@1 {</div><div class='add'>+		compatible = "usb451,8027";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		peer-hub = &lt;&amp;hub_3_0&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pio 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;reg_fixed_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hub_3_0: hub@2 {</div><div class='add'>+		compatible = "usb451,8025";</div><div class='add'>+		reg = &lt;2&gt;;</div><div class='add'>+		peer-hub = &lt;&amp;hub_2_0&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pio 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;reg_fixed_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xhci2 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	vusb33-supply = &lt;&amp;mt6359_vusb_ldo_reg&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	hub@1 {</div><div class='add'>+		compatible = "microchip,usb2513bi";</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;reg_fixed_3v3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ssusb0 {</div><div class='add'>+	dr_mode = "peripheral";</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;usb_default_pins&gt;;</div><div class='add'>+	vusb33-supply = &lt;&amp;mt6359_vusb_ldo_reg&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ssusb1 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	maximum-speed = "super-speed";</div><div class='add'>+	vusb33-supply = &lt;&amp;mt6359_vusb_ldo_reg&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ssusb2 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	maximum-speed = "high-speed";</div><div class='add'>+	vusb33-supply = &lt;&amp;mt6359_vusb_ldo_reg&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;scp_cluster {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;scp_c0 {</div><div class='add'>+	memory-region = &lt;&amp;scp_mem&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	mali-supply = &lt;&amp;mt6359_vproc2_buck_reg&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;adsp {</div><div class='add'>+	memory-region = &lt;&amp;adsp_dma_mem&gt;, &lt;&amp;adsp_mem&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;afe {</div><div class='add'>+	memory-region = &lt;&amp;afe_dma_mem&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sound {</div><div class='add'>+	compatible = "mediatek,mt8390-mt6359-evk", "mediatek,mt8188-mt6359-evb";</div><div class='add'>+	model = "mt8390-evk";</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;audio_default_pins&gt;;</div><div class='add'>+	audio-routing =</div><div class='add'>+		"Headphone", "Headphone L",</div><div class='add'>+		"Headphone", "Headphone R",</div><div class='add'>+		"AP DMIC", "AUDGLB",</div><div class='add'>+		"AP DMIC", "MIC_BIAS_0",</div><div class='add'>+		"AP DMIC", "MIC_BIAS_2",</div><div class='add'>+		"DMIC_INPUT", "AP DMIC";</div><div class='add'>+</div><div class='add'>+	mediatek,adsp = &lt;&amp;adsp&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-som.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-som.dtsi<br/>new file mode 100644<br/>index 000000000000..8da47c916313<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-som.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-som.dtsi</a></div><div class='hunk'>@@ -0,0 +1,210 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2025 Grinn sp. z o.o.</div><div class='add'>+ * Author: Mateusz Koza &lt;mateusz.koza@grinn-global.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "mt6359.dtsi"</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		i2c1 = &amp;i2c1;</div><div class='add'>+		mmc0 = &amp;mmc0;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c1_pins&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mfg0 {</div><div class='add'>+	domain-supply = &lt;&amp;mt6359_vproc2_buck_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mfg1 {</div><div class='add'>+	domain-supply = &lt;&amp;mt6359_vsram_others_ldo_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-names = "default", "state_uhs";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc0_default_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;mmc0_uhs_pins&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	cap-mmc-highspeed;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	mmc-hs400-1_8v;</div><div class='add'>+	supports-cqe;</div><div class='add'>+	cap-mmc-hw-reset;</div><div class='add'>+	no-sdio;</div><div class='add'>+	no-sd;</div><div class='add'>+	hs400-ds-delay = &lt;0x1481b&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;mt6359_vemc_1_ldo_reg&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;mt6359_vufs_ldo_reg&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vbbck_ldo_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vcn18_ldo_reg {</div><div class='add'>+	regulator-name = "vcn18_pmu";</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vcn33_2_bt_ldo_reg {</div><div class='add'>+	regulator-name = "vcn33_2_pmu";</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vcore_buck_reg {</div><div class='add'>+	regulator-name = "dvdd_proc_l";</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vgpu11_buck_reg {</div><div class='add'>+	regulator-name = "dvdd_core";</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vpa_buck_reg {</div><div class='add'>+	regulator-name = "vpa_pmu";</div><div class='add'>+	regulator-max-microvolt = &lt;3100000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vproc2_buck_reg {</div><div class='add'>+	/* The name "vgpu" is required by mtk-regulator-coupler */</div><div class='add'>+	regulator-name = "vgpu";</div><div class='add'>+	regulator-min-microvolt = &lt;550000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;800000&gt;;</div><div class='add'>+	regulator-coupled-with = &lt;&amp;mt6359_vsram_others_ldo_reg&gt;;</div><div class='add'>+	regulator-coupled-max-spread = &lt;6250&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vpu_buck_reg {</div><div class='add'>+	regulator-name = "dvdd_adsp";</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vrf12_ldo_reg {</div><div class='add'>+	regulator-name = "va12_abb2_pmu";</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vsim1_ldo_reg {</div><div class='add'>+	regulator-name = "vsim1_pmu";</div><div class='add'>+	regulator-enable-ramp-delay = &lt;480&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vsram_others_ldo_reg {</div><div class='add'>+	/* The name "vsram_gpu" is required by mtk-regulator-coupler */</div><div class='add'>+	regulator-name = "vsram_gpu";</div><div class='add'>+	regulator-min-microvolt = &lt;750000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;800000&gt;;</div><div class='add'>+	regulator-coupled-with = &lt;&amp;mt6359_vproc2_buck_reg&gt;;</div><div class='add'>+	regulator-coupled-max-spread = &lt;6250&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vufs_ldo_reg {</div><div class='add'>+	regulator-name = "vufs18_pmu";</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+</div><div class='add'>+	i2c1_pins: i2c1-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO58__FUNC_B1_SDA1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO57__FUNC_B1_SCL1&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PULL_SET_RSEL_011&gt;;</div><div class='add'>+			drive-strength-microamp = &lt;1000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc0_default_pins: mmc0-default-pins {</div><div class='add'>+		pins-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO157__FUNC_B1_MSDC0_CLK&gt;;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO161__FUNC_B1_MSDC0_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO160__FUNC_B1_MSDC0_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO159__FUNC_B1_MSDC0_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO158__FUNC_B1_MSDC0_DAT3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO154__FUNC_B1_MSDC0_DAT4&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO153__FUNC_B1_MSDC0_DAT5&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO152__FUNC_B1_MSDC0_DAT6&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO151__FUNC_B1_MSDC0_DAT7&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO156__FUNC_B1_MSDC0_CMD&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-rst {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO155__FUNC_O_MSDC0_RSTB&gt;;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc0_uhs_pins: mmc0-uhs-pins {</div><div class='add'>+		pins-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO157__FUNC_B1_MSDC0_CLK&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO161__FUNC_B1_MSDC0_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO160__FUNC_B1_MSDC0_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO159__FUNC_B1_MSDC0_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO158__FUNC_B1_MSDC0_DAT3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO154__FUNC_B1_MSDC0_DAT4&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO153__FUNC_B1_MSDC0_DAT5&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO152__FUNC_B1_MSDC0_DAT6&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO151__FUNC_B1_MSDC0_DAT7&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO156__FUNC_B1_MSDC0_CMD&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-ds {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO162__FUNC_B0_MSDC0_DSL&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-rst {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO155__FUNC_O_MSDC0_RSTB&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pmic {</div><div class='add'>+	interrupt-parent = &lt;&amp;pio&gt;;</div><div class='add'>+	interrupts = &lt;222 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	interrupts-extended = &lt;&amp;pio 222 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+	keys {</div><div class='add'>+		compatible = "mediatek,mt6359-keys";</div><div class='add'>+		mediatek,long-press-mode = &lt;1&gt;;</div><div class='add'>+		power-off-time-sec = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		power-key {</div><div class='add'>+			linux,keycodes = &lt;KEY_POWER&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk-ufs.dts b/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk-ufs.dts<br/>new file mode 100644<br/>index 000000000000..e09a3ecd8773<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk-ufs.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk-ufs.dts</a></div><div class='hunk'>@@ -0,0 +1,29 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2025 MediaTek Inc.</div><div class='add'>+ * Author: Ramax Lo &lt;ramax.lo@mediatek.com&gt;</div><div class='add'>+ *         Macpaul Lin &lt;macpaul.lin@mediatek.com&gt;</div><div class='add'>+ */</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "mt8395-genio-common.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "MediaTek Genio 1200 EVK-P1V2-UFS";</div><div class='add'>+	compatible = "mediatek,mt8395-evk-ufs", "mediatek,mt8395",</div><div class='add'>+		     "mediatek,mt8195";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ufshci {</div><div class='add'>+	status = "okay";</div><div class='add'>+	vcc-supply = &lt;&amp;mt6359_vemc_1_ldo_reg&gt;;</div><div class='add'>+	vccq2-supply = &lt;&amp;mt6359_vufs_ldo_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ufsphy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc0 {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts b/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts<br/>new file mode 100644<br/>index 000000000000..68455f28c246<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts</a></div><div class='hunk'>@@ -0,0 +1,15 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2023 MediaTek Inc.</div><div class='add'>+ * Author: Ben Lok &lt;ben.lok@mediatek.com&gt;</div><div class='add'>+ *	   Macpaul Lin &lt;macpaul.lin@mediatek.com&gt;</div><div class='add'>+ */</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "mt8395-genio-common.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "MediaTek Genio 1200 EVK-P1V2-EMMC";</div><div class='add'>+	compatible = "mediatek,mt8395-evk", "mediatek,mt8395",</div><div class='add'>+		     "mediatek,mt8195";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi<br/>new file mode 100644<br/>index 000000000000..2b7167804e71<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi</a></div><div class='hunk'>@@ -0,0 +1,1230 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2023 MediaTek Inc.</div><div class='add'>+ * Author: Ben Lok &lt;ben.lok@mediatek.com&gt;</div><div class='add'>+ *	   Macpaul Lin &lt;macpaul.lin@mediatek.com&gt;</div><div class='add'>+ */</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "mt8195.dtsi"</div><div class='add'>+#include "mt6359.dtsi"</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/mt8195-pinfunc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/regulator/mediatek,mt6360-regulator.h&gt;</div><div class='add'>+#include &lt;dt-bindings/spmi/spmi.h&gt;</div><div class='add'>+#include &lt;dt-bindings/usb/pd.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+		ethernet0 = &amp;eth;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:921600n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	firmware {</div><div class='add'>+		optee {</div><div class='add'>+			compatible = "linaro,optee-tz";</div><div class='add'>+			method = "smc";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0 0x40000000 0x2 0x00000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * 12 MiB reserved for OP-TEE (BL32)</div><div class='add'>+		 * +-----------------------+ 0x43e0_0000</div><div class='add'>+		 * |      SHMEM 2MiB       |</div><div class='add'>+		 * +-----------------------+ 0x43c0_0000</div><div class='add'>+		 * |        | TA_RAM  8MiB |</div><div class='add'>+		 * + TZDRAM +--------------+ 0x4340_0000</div><div class='add'>+		 * |        | TEE_RAM 2MiB |</div><div class='add'>+		 * +-----------------------+ 0x4320_0000</div><div class='add'>+		 */</div><div class='add'>+		optee_reserved: optee@43200000 {</div><div class='add'>+			no-map;</div><div class='add'>+			reg = &lt;0 0x43200000 0 0x00c00000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		scp_mem: memory@50000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x50000000 0 0x2900000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vpu_mem: memory@53000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x53000000 0 0x1400000&gt;; /* 20 MB */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* 2 MiB reserved for ARM Trusted Firmware (BL31) */</div><div class='add'>+		bl31_secmon_mem: memory@54600000 {</div><div class='add'>+			no-map;</div><div class='add'>+			reg = &lt;0 0x54600000 0x0 0x200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		adsp_mem: memory@60000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x60000000 0 0xf00000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		afe_dma_mem: memory@60f00000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x60f00000 0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		adsp_dma_mem: memory@61000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x61000000 0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		apu_mem: memory@62000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x62000000 0 0x1400000&gt;; /* 20 MB */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	backlight_lcm0: backlight-lcm0 {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		brightness-levels = &lt;0 1023&gt;;</div><div class='add'>+		default-brightness-level = &lt;576&gt;;</div><div class='add'>+		num-interpolated-steps = &lt;1023&gt;;</div><div class='add'>+		pwms = &lt;&amp;disp_pwm0 0 500000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	backlight_lcd1: backlight-lcd1 {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		pwms = &lt;&amp;disp_pwm1 0 500000&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;pio 46 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		brightness-levels = &lt;0 1023&gt;;</div><div class='add'>+		num-interpolated-steps = &lt;1023&gt;;</div><div class='add'>+		default-brightness-level = &lt;576&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	can_clk: can-clk {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;20000000&gt;;</div><div class='add'>+		clock-output-names = "can-clk";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	edp_panel_fixed_3v3: regulator-0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "edp_panel_3v3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;pio 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;edp_panel_3v3_en_pins&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	edp_panel_fixed_12v: regulator-1 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "edp_backlight_12v";</div><div class='add'>+		regulator-min-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;12000000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;pio 96 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;edp_panel_12v_en_pins&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	keys: gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		button-volume-up {</div><div class='add'>+			wakeup-source;</div><div class='add'>+			debounce-interval = &lt;100&gt;;</div><div class='add'>+			gpios = &lt;&amp;pio 106 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			label = "volume_up";</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lcm0_iovcc: regulator-vio18-lcm0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vio18_lcm0";</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;pio 47 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;dsi0_vreg_en_pins&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;mt6360_ldo2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lcm0_vddp: regulator-vsys-lcm0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vsys_lcm0";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		vin-supply = &lt;&amp;mt6360_ldo1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wifi_fixed_3v3: regulator-2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "wifi_3v3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;pio 135 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;adsp {</div><div class='add'>+	memory-region = &lt;&amp;adsp_dma_mem&gt;, &lt;&amp;adsp_mem&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;afe {</div><div class='add'>+	memory-region = &lt;&amp;afe_dma_mem&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	cpu-supply = &lt;&amp;mt6359_vcore_buck_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu1 {</div><div class='add'>+	cpu-supply = &lt;&amp;mt6359_vcore_buck_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu2 {</div><div class='add'>+	cpu-supply = &lt;&amp;mt6359_vcore_buck_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu3 {</div><div class='add'>+	cpu-supply = &lt;&amp;mt6359_vcore_buck_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu4 {</div><div class='add'>+	cpu-supply = &lt;&amp;mt6315_6_vbuck1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu5 {</div><div class='add'>+	cpu-supply = &lt;&amp;mt6315_6_vbuck1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu6 {</div><div class='add'>+	cpu-supply = &lt;&amp;mt6315_6_vbuck1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu7 {</div><div class='add'>+	cpu-supply = &lt;&amp;mt6315_6_vbuck1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;disp_pwm0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;disp_pwm0_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dither0_in {</div><div class='add'>+	remote-endpoint = &lt;&amp;gamma0_out&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dither0_out {</div><div class='add'>+	remote-endpoint = &lt;&amp;dsi0_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dmic_codec {</div><div class='add'>+	wakeup-delay-ms = &lt;200&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsi0 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	panel@0 {</div><div class='add'>+		compatible = "startek,kd070fhfid078", "himax,hx8279";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		backlight = &lt;&amp;backlight_lcm0&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;pio 48 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pio 108 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		iovcc-supply = &lt;&amp;lcm0_iovcc&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;lcm0_vddp&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;panel_default_pins&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			dsi_panel_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;dsi0_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		port@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			dsi0_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;dither0_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			dsi0_out: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;dsi_panel_in&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eth {</div><div class='add'>+	phy-mode ="rgmii-rxid";</div><div class='add'>+	phy-handle = &lt;&amp;eth_phy0&gt;;</div><div class='add'>+	snps,reset-gpio = &lt;&amp;pio 93 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	snps,reset-delays-us = &lt;0 10000 10000&gt;;</div><div class='add'>+	mediatek,tx-delay-ps = &lt;2030&gt;;</div><div class='add'>+	mediatek,mac-wol;</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;eth_default_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;eth_sleep_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		eth_phy0: ethernet-phy@1 {</div><div class='add'>+			compatible = "ethernet-phy-id001c.c916";</div><div class='add'>+			reg = &lt;0x1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gamma0_out {</div><div class='add'>+	remote-endpoint = &lt;&amp;dither0_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	mali-supply = &lt;&amp;mt6315_7_vbuck1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c0_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c1_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	touchscreen@5d {</div><div class='add'>+		compatible = "goodix,gt9271";</div><div class='add'>+		reg = &lt;0x5d&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 132 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+		irq-gpios = &lt;&amp;pio 132 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pio 133 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		AVDD28-supply = &lt;&amp;mt6360_ldo1&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;touch_pins&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c2_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	typec-mux@48 {</div><div class='add'>+		compatible = "ite,it5205";</div><div class='add'>+		reg = &lt;0x48&gt;;</div><div class='add'>+		vcc-supply = &lt;&amp;mt6359_vibr_ldo_reg&gt;;</div><div class='add'>+		mode-switch;</div><div class='add'>+		orientation-switch;</div><div class='add'>+		status = "okay";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			it5205_sbu_ep: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;mt6360_ssusb_sbu_ep&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c6 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c6_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mt6360: pmic@34 {</div><div class='add'>+		compatible = "mediatek,mt6360";</div><div class='add'>+		reg = &lt;0x34&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;pio&gt;;</div><div class='add'>+		interrupts = &lt;128 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		interrupt-names = "IRQB";</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;mt6360_pins&gt;;</div><div class='add'>+</div><div class='add'>+		charger {</div><div class='add'>+			compatible = "mediatek,mt6360-chg";</div><div class='add'>+			richtek,vinovp-microvolt = &lt;14500000&gt;;</div><div class='add'>+</div><div class='add'>+			otg_vbus_regulator: usb-otg-vbus-regulator {</div><div class='add'>+				regulator-name = "usb-otg-vbus";</div><div class='add'>+				regulator-min-microvolt = &lt;4425000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;5825000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		regulator {</div><div class='add'>+			compatible = "mediatek,mt6360-regulator";</div><div class='add'>+			LDO_VIN3-supply = &lt;&amp;mt6360_buck2&gt;;</div><div class='add'>+</div><div class='add'>+			mt6360_buck1: buck1 {</div><div class='add'>+				regulator-name = "emi_vdd2";</div><div class='add'>+				regulator-min-microvolt = &lt;300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;MT6360_OPMODE_NORMAL</div><div class='add'>+							   MT6360_OPMODE_LP</div><div class='add'>+							   MT6360_OPMODE_ULP&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6360_buck2: buck2 {</div><div class='add'>+				regulator-name = "emi_vddq";</div><div class='add'>+				regulator-min-microvolt = &lt;300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;MT6360_OPMODE_NORMAL</div><div class='add'>+							   MT6360_OPMODE_LP</div><div class='add'>+							   MT6360_OPMODE_ULP&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6360_ldo1: ldo1 {</div><div class='add'>+				regulator-name = "tp1_p3v0";</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;MT6360_OPMODE_NORMAL</div><div class='add'>+							   MT6360_OPMODE_LP&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6360_ldo2: ldo2 {</div><div class='add'>+				regulator-name = "panel1_p1v8";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;MT6360_OPMODE_NORMAL</div><div class='add'>+							   MT6360_OPMODE_LP&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6360_ldo3: ldo3 {</div><div class='add'>+				regulator-name = "vmc_pmu";</div><div class='add'>+				regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3600000&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;MT6360_OPMODE_NORMAL</div><div class='add'>+							   MT6360_OPMODE_LP&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6360_ldo5: ldo5 {</div><div class='add'>+				regulator-name = "vmch_pmu";</div><div class='add'>+				regulator-min-microvolt = &lt;2700000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3600000&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;MT6360_OPMODE_NORMAL</div><div class='add'>+							   MT6360_OPMODE_LP&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* This is a measure point, which name is mt6360_ldo1 on schematic */</div><div class='add'>+			mt6360_ldo6: ldo6 {</div><div class='add'>+				regulator-name = "mt6360_ldo1";</div><div class='add'>+				regulator-min-microvolt = &lt;500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2100000&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;MT6360_OPMODE_NORMAL</div><div class='add'>+							   MT6360_OPMODE_LP&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6360_ldo7: ldo7 {</div><div class='add'>+				regulator-name = "emi_vmddr_en";</div><div class='add'>+				regulator-min-microvolt = &lt;500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2100000&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;MT6360_OPMODE_NORMAL</div><div class='add'>+							   MT6360_OPMODE_LP&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tcpc {</div><div class='add'>+			compatible = "mediatek,mt6360-tcpc";</div><div class='add'>+			interrupts-extended = &lt;&amp;pio 17 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			interrupt-names = "PD_IRQB";</div><div class='add'>+</div><div class='add'>+			connector {</div><div class='add'>+				compatible = "usb-c-connector";</div><div class='add'>+				label = "USB-C";</div><div class='add'>+				data-role = "dual";</div><div class='add'>+				op-sink-microwatt = &lt;10000000&gt;;</div><div class='add'>+				power-role = "dual";</div><div class='add'>+				try-power-role = "sink";</div><div class='add'>+</div><div class='add'>+				source-pdos = &lt;PDO_FIXED(5000, 1000,</div><div class='add'>+							 PDO_FIXED_DUAL_ROLE |</div><div class='add'>+							 PDO_FIXED_DATA_SWAP)&gt;;</div><div class='add'>+				sink-pdos = &lt;PDO_FIXED(5000, 2000,</div><div class='add'>+						       PDO_FIXED_DUAL_ROLE |</div><div class='add'>+						       PDO_FIXED_DATA_SWAP)&gt;;</div><div class='add'>+</div><div class='add'>+				pd-revision = /bits/ 8 &lt;0x03 0x01 0x01 0x06&gt;;</div><div class='add'>+</div><div class='add'>+				altmodes {</div><div class='add'>+					displayport {</div><div class='add'>+						svid = /bits/ 16 &lt;0xff01&gt;;</div><div class='add'>+						vdo = &lt;0x00001c46&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+						typec_con_hs: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mtu3_hs0_role_sw&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+						typec_con_ss: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mtu3_ss0_role_sw&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@2 {</div><div class='add'>+						reg = &lt;2&gt;;</div><div class='add'>+						mt6360_ssusb_sbu_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;it5205_sbu_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mfg0 {</div><div class='add'>+	domain-supply = &lt;&amp;mt6315_7_vbuck1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mfg1 {</div><div class='add'>+	domain-supply = &lt;&amp;mt6359_vsram_others_ldo_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_tx0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-names = "default", "state_uhs";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc0_default_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;mmc0_uhs_pins&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	cap-mmc-highspeed;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	mmc-hs400-1_8v;</div><div class='add'>+	cap-mmc-hw-reset;</div><div class='add'>+	no-sdio;</div><div class='add'>+	no-sd;</div><div class='add'>+	hs400-ds-delay = &lt;0x14c11&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;mt6359_vemc_1_ldo_reg&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;mt6359_vufs_ldo_reg&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc1 {</div><div class='add'>+	pinctrl-names = "default", "state_uhs";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc1_default_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;mmc1_uhs_pins&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	sd-uhs-sdr50;</div><div class='add'>+	sd-uhs-sdr104;</div><div class='add'>+	no-mmc;</div><div class='add'>+	no-sdio;</div><div class='add'>+	vmmc-supply = &lt;&amp;mt6360_ldo5&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;mt6360_ldo3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+	non-removable;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vaud18_ldo_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vbbck_ldo_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* For USB Hub */</div><div class='add'>+&amp;mt6359_vcamio_ldo_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vcn33_2_bt_ldo_reg {</div><div class='add'>+	regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vcore_buck_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vgpu11_buck_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vpu_buck_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vrf12_ldo_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* for GPU SRAM */</div><div class='add'>+&amp;mt6359_vsram_others_ldo_reg {</div><div class='add'>+	regulator-min-microvolt = &lt;750000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;750000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359codec {</div><div class='add'>+	mediatek,mic-type-0 = &lt;1&gt;; /* ACC */</div><div class='add'>+	mediatek,mic-type-1 = &lt;3&gt;; /* DCC */</div><div class='add'>+	mediatek,mic-type-2 = &lt;1&gt;; /* ACC */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ovl0_in {</div><div class='add'>+	remote-endpoint = &lt;&amp;vdosys0_ep_main&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	pinctrl-names = "default", "idle";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pcie0_default_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pcie0_idle_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pcie1_default_pins&gt;;</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pciephy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	audio_default_pins: audio-default-pins {</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO61__FUNC_DMIC1_CLK&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO62__FUNC_DMIC1_DAT&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO65__FUNC_PCM_DO&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO66__FUNC_PCM_CLK&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO67__FUNC_PCM_DI&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO68__FUNC_PCM_SYNC&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO69__FUNC_AUD_CLK_MOSI&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO70__FUNC_AUD_SYNC_MOSI&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO71__FUNC_AUD_DAT_MOSI0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO72__FUNC_AUD_DAT_MOSI1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO73__FUNC_AUD_DAT_MISO0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO74__FUNC_AUD_DAT_MISO1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO75__FUNC_AUD_DAT_MISO2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	disp_pwm1_default_pins: disp-pwm1-default-pins {</div><div class='add'>+		pins1 {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO104__FUNC_DISP_PWM1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	edp_panel_12v_en_pins: edp-panel-12v-en-pins {</div><div class='add'>+		pins1 {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO96__FUNC_GPIO96&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	edp_panel_3v3_en_pins: edp-panel-3v3-en-pins {</div><div class='add'>+		pins1 {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO6__FUNC_GPIO6&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eth_default_pins: eth-default-pins {</div><div class='add'>+		pins-cc {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO85__FUNC_GBE_TXC&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO86__FUNC_GBE_RXC&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO87__FUNC_GBE_RXDV&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO88__FUNC_GBE_TXEN&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-mdio {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO89__FUNC_GBE_MDC&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO90__FUNC_GBE_MDIO&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-power {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO91__FUNC_GPIO91&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO92__FUNC_GPIO92&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-rxd {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO81__FUNC_GBE_RXD3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO82__FUNC_GBE_RXD2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO83__FUNC_GBE_RXD1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO84__FUNC_GBE_RXD0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-txd {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO77__FUNC_GBE_TXD3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO78__FUNC_GBE_TXD2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO79__FUNC_GBE_TXD1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO80__FUNC_GBE_TXD0&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eth_sleep_pins: eth-sleep-pins {</div><div class='add'>+		pins-cc {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO85__FUNC_GPIO85&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO86__FUNC_GPIO86&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO87__FUNC_GPIO87&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO88__FUNC_GPIO88&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-mdio {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO89__FUNC_GPIO89&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO90__FUNC_GPIO90&gt;;</div><div class='add'>+			input-disable;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-rxd {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO81__FUNC_GPIO81&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO82__FUNC_GPIO82&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO83__FUNC_GPIO83&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO84__FUNC_GPIO84&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-txd {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO77__FUNC_GPIO77&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO78__FUNC_GPIO78&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO79__FUNC_GPIO79&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO80__FUNC_GPIO80&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio_key_pins: gpio-keys-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO106__FUNC_GPIO106&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c0_pins: i2c0-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO8__FUNC_SDA0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO9__FUNC_SCL0&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PULL_SET_RSEL_111&gt;;</div><div class='add'>+			drive-strength-microamp = &lt;1000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c1_pins: i2c1-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO10__FUNC_SDA1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO11__FUNC_SCL1&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PULL_SET_RSEL_111&gt;;</div><div class='add'>+			drive-strength-microamp = &lt;1000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c2_pins: i2c2-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO12__FUNC_SDA2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO13__FUNC_SCL2&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PULL_SET_RSEL_111&gt;;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c6_pins: i2c6-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO25__FUNC_SDA6&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO26__FUNC_SCL6&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc0_default_pins: mmc0-default-pins {</div><div class='add'>+		pins-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO122__FUNC_MSDC0_CLK&gt;;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO126__FUNC_MSDC0_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO125__FUNC_MSDC0_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO124__FUNC_MSDC0_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO123__FUNC_MSDC0_DAT3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO119__FUNC_MSDC0_DAT4&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO118__FUNC_MSDC0_DAT5&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO117__FUNC_MSDC0_DAT6&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO116__FUNC_MSDC0_DAT7&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO121__FUNC_MSDC0_CMD&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-rst {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO120__FUNC_MSDC0_RSTB&gt;;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc0_uhs_pins: mmc0-uhs-pins {</div><div class='add'>+		pins-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO122__FUNC_MSDC0_CLK&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO126__FUNC_MSDC0_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO125__FUNC_MSDC0_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO124__FUNC_MSDC0_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO123__FUNC_MSDC0_DAT3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO119__FUNC_MSDC0_DAT4&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO118__FUNC_MSDC0_DAT5&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO117__FUNC_MSDC0_DAT6&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO116__FUNC_MSDC0_DAT7&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO121__FUNC_MSDC0_CMD&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-ds {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO127__FUNC_MSDC0_DSL&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-rst {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO120__FUNC_MSDC0_RSTB&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc1_default_pins: mmc1-default-pins {</div><div class='add'>+		pins-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO111__FUNC_MSDC1_CLK&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO110__FUNC_MSDC1_CMD&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO112__FUNC_MSDC1_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO113__FUNC_MSDC1_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO114__FUNC_MSDC1_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO115__FUNC_MSDC1_DAT3&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc1_uhs_pins: mmc1-uhs-pins {</div><div class='add'>+		pins-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO111__FUNC_MSDC1_CLK&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO110__FUNC_MSDC1_CMD&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO112__FUNC_MSDC1_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO113__FUNC_MSDC1_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO114__FUNC_MSDC1_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO115__FUNC_MSDC1_DAT3&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mt6360_pins: mt6360-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO17__FUNC_GPIO17&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO128__FUNC_GPIO128&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dsi0_vreg_en_pins: dsi0-vreg-en-pins {</div><div class='add'>+		pins-pwr-en {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO47__FUNC_GPIO47&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	panel_default_pins: panel-default-pins {</div><div class='add'>+		pins-rst {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO108__FUNC_GPIO108&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-en {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO48__FUNC_GPIO48&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_default_pins: pcie0-default-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO19__FUNC_WAKEN&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO20__FUNC_PERSTN&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO21__FUNC_CLKREQN&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_idle_pins: pcie0-idle-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO20__FUNC_GPIO20&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie1_default_pins: pcie1-default-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO22__FUNC_PERSTN_1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO23__FUNC_CLKREQN_1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO24__FUNC_WAKEN_1&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	disp_pwm0_pins: disp-pwm0-pins {</div><div class='add'>+		pins-disp-pwm {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO97__FUNC_DISP_PWM0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi1_pins: spi1-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO136__FUNC_SPIM1_CSB&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO137__FUNC_SPIM1_CLK&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO138__FUNC_SPIM1_MO&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO139__FUNC_SPIM1_MI&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi2_pins: spi-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO140__FUNC_SPIM2_CSB&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO141__FUNC_SPIM2_CLK&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO142__FUNC_SPIM2_MO&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO143__FUNC_SPIM2_MI&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	touch_pins: touch-pins {</div><div class='add'>+		pins-irq {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO132__FUNC_GPIO132&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-reset {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO133__FUNC_GPIO133&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	u3_p0_vbus: u3-p0-vbus-default-pins {</div><div class='add'>+		pins-vbus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO63__FUNC_VBUSVALID&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart0_pins: uart0-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO98__FUNC_UTXD0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO99__FUNC_URXD0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart1_pins: uart1-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO100__FUNC_URTS1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO101__FUNC_UCTS1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO102__FUNC_UTXD1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO103__FUNC_URXD1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pmic {</div><div class='add'>+	interrupts-extended = &lt;&amp;pio 222 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+	mt6359keys: keys {</div><div class='add'>+		compatible = "mediatek,mt6359-keys";</div><div class='add'>+		mediatek,long-press-mode = &lt;1&gt;;</div><div class='add'>+		power-off-time-sec = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		power-key {</div><div class='add'>+			linux,keycodes = &lt;KEY_POWER&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		home {</div><div class='add'>+			linux,keycodes = &lt;KEY_HOME&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;scp {</div><div class='add'>+	memory-region = &lt;&amp;scp_mem&gt;;</div><div class='add'>+	firmware-name = "mediatek/mt8195/scp.img";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sound {</div><div class='add'>+	compatible = "mediatek,mt8195_mt6359";</div><div class='add'>+	model = "mt8395-evk";</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;audio_default_pins&gt;;</div><div class='add'>+	audio-routing =</div><div class='add'>+		"Headphone", "Headphone L",</div><div class='add'>+		"Headphone", "Headphone R";</div><div class='add'>+	mediatek,adsp = &lt;&amp;adsp&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	headphone-dai-link {</div><div class='add'>+		link-name = "DL_SRC_BE";</div><div class='add'>+</div><div class='add'>+		codec {</div><div class='add'>+			sound-dai = &lt;&amp;pmic 0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;spi1_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	mediatek,pad-select = &lt;0&gt;;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+	cs-gpios = &lt;&amp;pio 64 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+	can0: can@0 {</div><div class='add'>+		compatible = "microchip,mcp2518fd";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		clocks = &lt;&amp;can_clk&gt;;</div><div class='add'>+		spi-max-frequency = &lt;20000000&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 16 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;mt6359_vcn33_2_bt_ldo_reg&gt;;</div><div class='add'>+		xceiver-supply = &lt;&amp;mt6359_vcn33_2_bt_ldo_reg&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi2 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;spi2_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	mediatek,pad-select = &lt;0&gt;;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spmi {</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	mt6315_6: pmic@6 {</div><div class='add'>+		compatible = "mediatek,mt6315-regulator";</div><div class='add'>+		reg = &lt;0x6 SPMI_USID&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			mt6315_6_vbuck1: vbuck1 {</div><div class='add'>+				regulator-name = "Vbcpu";</div><div class='add'>+				regulator-min-microvolt = &lt;300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1193750&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;256&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;0 1 2&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mt6315_7: pmic@7 {</div><div class='add'>+		compatible = "mediatek,mt6315-regulator";</div><div class='add'>+		reg = &lt;0x7 SPMI_USID&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			mt6315_7_vbuck1: vbuck1 {</div><div class='add'>+				regulator-name = "Vgpu";</div><div class='add'>+				regulator-min-microvolt = &lt;546000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;787000&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;256&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;0 1 2&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;u3phy0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;u3phy1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	u3port1: usb-phy@700 {</div><div class='add'>+		mediatek,force-mode;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;u3phy2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;u3phy3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart0_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart1_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ufsphy {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ssusb0 {</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;u3_p0_vbus&gt;;</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	vusb33-supply = &lt;&amp;mt6359_vusb_ldo_reg&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		port@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			mtu3_hs0_role_sw: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;typec_con_hs&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			mtu3_ss0_role_sw: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;typec_con_ss&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ssusb2 {</div><div class='add'>+	vusb33-supply = &lt;&amp;mt6359_vusb_ldo_reg&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ssusb3 {</div><div class='add'>+	vusb33-supply = &lt;&amp;mt6359_vusb_ldo_reg&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;vdosys0 {</div><div class='add'>+	port {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		vdosys0_ep_main: endpoint@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			remote-endpoint = &lt;&amp;ovl0_in&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xhci0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xhci1 {</div><div class='add'>+	vusb33-supply = &lt;&amp;mt6359_vusb_ldo_reg&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xhci2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xhci3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8395-kontron-3-5-sbc-i1200.dts b/arch/arm64/boot/dts/mediatek/mt8395-kontron-3-5-sbc-i1200.dts<br/>new file mode 100644<br/>index 000000000000..d16f545cbbb2<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8395-kontron-3-5-sbc-i1200.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8395-kontron-3-5-sbc-i1200.dts</a></div><div class='hunk'>@@ -0,0 +1,1129 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2024 Kontron Europe GmbH</div><div class='add'>+ *</div><div class='add'>+ * Author: Michael Walle &lt;mwalle@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "mt8195.dtsi"</div><div class='add'>+#include "mt6359.dtsi"</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/mt8195-pinfunc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/regulator/mediatek,mt6360-regulator.h&gt;</div><div class='add'>+#include &lt;dt-bindings/spmi/spmi.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Kontron 3.5\"-SBC-i1200";</div><div class='add'>+	compatible = "kontron,3-5-sbc-i1200", "mediatek,mt8395", "mediatek,mt8195";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		mmc0 = &amp;mmc0;</div><div class='add'>+		mmc1 = &amp;mmc1;</div><div class='add'>+		serial0 = &amp;uart1;</div><div class='add'>+		serial1 = &amp;uart2;</div><div class='add'>+		serial2 = &amp;uart3;</div><div class='add'>+		serial3 = &amp;uart4;</div><div class='add'>+		serial4 = &amp;uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	firmware {</div><div class='add'>+		optee {</div><div class='add'>+			compatible = "linaro,optee-tz";</div><div class='add'>+			method = "smc";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;gpio_keys_pins&gt;;</div><div class='add'>+</div><div class='add'>+		key-0 {</div><div class='add'>+			gpios = &lt;&amp;pio 106 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			label = "volume_up";</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+			debounce-interval = &lt;15&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;led_pins&gt;;</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			gpios = &lt;&amp;pio 107 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "keep";</div><div class='add'>+			function = LED_FUNCTION_POWER;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0 0x40000000 0x0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vsys: regulator-vsys {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vsys";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * 12 MiB reserved for OP-TEE (BL32)</div><div class='add'>+		 * +-----------------------+ 0x43e0_0000</div><div class='add'>+		 * |      SHMEM 2MiB       |</div><div class='add'>+		 * +-----------------------+ 0x43c0_0000</div><div class='add'>+		 * |        | TA_RAM  8MiB |</div><div class='add'>+		 * + TZDRAM +--------------+ 0x4340_0000</div><div class='add'>+		 * |        | TEE_RAM 2MiB |</div><div class='add'>+		 * +-----------------------+ 0x4320_0000</div><div class='add'>+		 */</div><div class='add'>+		optee_reserved: optee@43200000 {</div><div class='add'>+			no-map;</div><div class='add'>+			reg = &lt;0 0x43200000 0 0x00c00000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		scp_mem: memory@50000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x50000000 0 0x2900000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vpu_mem: memory@53000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x53000000 0 0x1400000&gt;; /* 20 MB */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* 2 MiB reserved for ARM Trusted Firmware (BL31) */</div><div class='add'>+		bl31_secmon_mem: memory@54600000 {</div><div class='add'>+			no-map;</div><div class='add'>+			reg = &lt;0 0x54600000 0x0 0x200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		snd_dma_mem: memory@60000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x60000000 0 0x1100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		apu_mem: memory@62000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x62000000 0 0x1400000&gt;; /* 20 MB */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	thermal_sensor0: thermal-sensor-0 {</div><div class='add'>+		compatible = "generic-adc-thermal";</div><div class='add'>+		#thermal-sensor-cells = &lt;0&gt;;</div><div class='add'>+		io-channels = &lt;&amp;auxadc 0&gt;;</div><div class='add'>+		io-channel-names = "sensor-channel";</div><div class='add'>+		temperature-lookup-table = &lt;(-25000) 1474</div><div class='add'>+					    (-20000) 1374</div><div class='add'>+					    (-15000) 1260</div><div class='add'>+					    (-10000) 1134</div><div class='add'>+					     (-5000) 1004</div><div class='add'>+						   0 874</div><div class='add'>+						5000 750</div><div class='add'>+					       10000 635</div><div class='add'>+					       15000 532</div><div class='add'>+					       20000 443</div><div class='add'>+					       25000 367</div><div class='add'>+					       30000 303</div><div class='add'>+					       35000 250</div><div class='add'>+					       40000 206</div><div class='add'>+					       45000 170</div><div class='add'>+					       50000 141</div><div class='add'>+					       55000 117</div><div class='add'>+					       60000 97</div><div class='add'>+					       65000 81</div><div class='add'>+					       70000 68</div><div class='add'>+					       75000 57</div><div class='add'>+					       80000 48</div><div class='add'>+					       85000 41</div><div class='add'>+					       90000 35</div><div class='add'>+					       95000 30</div><div class='add'>+					      100000 25</div><div class='add'>+					      105000 22</div><div class='add'>+					      110000 19</div><div class='add'>+					      115000 16</div><div class='add'>+					      120000 14</div><div class='add'>+					      125000 12</div><div class='add'>+					      130000 10</div><div class='add'>+					      135000 9</div><div class='add'>+					      140000 8</div><div class='add'>+					      145000 7</div><div class='add'>+					      150000 6&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	thermal_sensor1: thermal-sensor-1 {</div><div class='add'>+		compatible = "generic-adc-thermal";</div><div class='add'>+		#thermal-sensor-cells = &lt;0&gt;;</div><div class='add'>+		io-channels = &lt;&amp;auxadc 1&gt;;</div><div class='add'>+		io-channel-names = "sensor-channel";</div><div class='add'>+		temperature-lookup-table = &lt;(-25000) 1474</div><div class='add'>+					    (-20000) 1374</div><div class='add'>+					    (-15000) 1260</div><div class='add'>+					    (-10000) 1134</div><div class='add'>+					     (-5000) 1004</div><div class='add'>+						   0 874</div><div class='add'>+						5000 750</div><div class='add'>+					       10000 635</div><div class='add'>+					       15000 532</div><div class='add'>+					       20000 443</div><div class='add'>+					       25000 367</div><div class='add'>+					       30000 303</div><div class='add'>+					       35000 250</div><div class='add'>+					       40000 206</div><div class='add'>+					       45000 170</div><div class='add'>+					       50000 141</div><div class='add'>+					       55000 117</div><div class='add'>+					       60000 97</div><div class='add'>+					       65000 81</div><div class='add'>+					       70000 68</div><div class='add'>+					       75000 57</div><div class='add'>+					       80000 48</div><div class='add'>+					       85000 41</div><div class='add'>+					       90000 35</div><div class='add'>+					       95000 30</div><div class='add'>+					      100000 25</div><div class='add'>+					      105000 22</div><div class='add'>+					      110000 19</div><div class='add'>+					      115000 16</div><div class='add'>+					      120000 14</div><div class='add'>+					      125000 12</div><div class='add'>+					      130000 10</div><div class='add'>+					      135000 9</div><div class='add'>+					      140000 8</div><div class='add'>+					      145000 7</div><div class='add'>+					      150000 6&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	thermal_sensor2: thermal-sensor-2 {</div><div class='add'>+		compatible = "generic-adc-thermal";</div><div class='add'>+		#thermal-sensor-cells = &lt;0&gt;;</div><div class='add'>+		io-channels = &lt;&amp;auxadc 2&gt;;</div><div class='add'>+		io-channel-names = "sensor-channel";</div><div class='add'>+		temperature-lookup-table = &lt;(-25000) 1474</div><div class='add'>+					    (-20000) 1374</div><div class='add'>+					    (-15000) 1260</div><div class='add'>+					    (-10000) 1134</div><div class='add'>+					     (-5000) 1004</div><div class='add'>+						   0 874</div><div class='add'>+						5000 750</div><div class='add'>+					       10000 635</div><div class='add'>+					       15000 532</div><div class='add'>+					       20000 443</div><div class='add'>+					       25000 367</div><div class='add'>+					       30000 303</div><div class='add'>+					       35000 250</div><div class='add'>+					       40000 206</div><div class='add'>+					       45000 170</div><div class='add'>+					       50000 141</div><div class='add'>+					       55000 117</div><div class='add'>+					       60000 97</div><div class='add'>+					       65000 81</div><div class='add'>+					       70000 68</div><div class='add'>+					       75000 57</div><div class='add'>+					       80000 48</div><div class='add'>+					       85000 41</div><div class='add'>+					       90000 35</div><div class='add'>+					       95000 30</div><div class='add'>+					      100000 25</div><div class='add'>+					      105000 22</div><div class='add'>+					      110000 19</div><div class='add'>+					      115000 16</div><div class='add'>+					      120000 14</div><div class='add'>+					      125000 12</div><div class='add'>+					      130000 10</div><div class='add'>+					      135000 9</div><div class='add'>+					      140000 8</div><div class='add'>+					      145000 7</div><div class='add'>+					      150000 6&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;auxadc {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eth {</div><div class='add'>+	phy-mode ="rgmii-id";</div><div class='add'>+	phy-handle = &lt;&amp;ethernet_phy0&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;eth_default_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;eth_sleep_pins&gt;;</div><div class='add'>+	mediatek,mac-wol;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		ethernet_phy0: ethernet-phy@1 {</div><div class='add'>+			compatible = "ethernet-phy-id001c.c916";</div><div class='add'>+			reg = &lt;0x1&gt;;</div><div class='add'>+			interrupts-extended = &lt;&amp;pio 94 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;10000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;80000&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;pio 93 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	status = "okay";</div><div class='add'>+	mali-supply = &lt;&amp;mt6315_7_vbuck1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* CSI1/CSI2 connector */</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c0_pins&gt;;</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* CSI3 connector */</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c1_pins&gt;;</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c2_pins&gt;;</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* LVDS bridge @f */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Touch panel connector */</div><div class='add'>+&amp;i2c3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c3_pins&gt;;</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* B2B connector */</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	clock-frequency = &lt;100000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c4_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c6 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c6_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mt6360: pmic@34 {</div><div class='add'>+		compatible = "mediatek,mt6360";</div><div class='add'>+		reg = &lt;0x34&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 101 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		interrupt-names = "IRQB";</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		regulator {</div><div class='add'>+			compatible = "mediatek,mt6360-regulator";</div><div class='add'>+			LDO_VIN1-supply = &lt;&amp;vsys&gt;;</div><div class='add'>+			LDO_VIN2-supply = &lt;&amp;vsys&gt;;</div><div class='add'>+			LDO_VIN3-supply = &lt;&amp;vsys&gt;;</div><div class='add'>+</div><div class='add'>+			mt6360_buck1: buck1 {</div><div class='add'>+				regulator-name = "emi_vdd2";</div><div class='add'>+				regulator-min-microvolt = &lt;600000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;MT6360_OPMODE_NORMAL</div><div class='add'>+							   MT6360_OPMODE_LP</div><div class='add'>+							   MT6360_OPMODE_ULP&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6360_buck2: buck2 {</div><div class='add'>+				regulator-name = "emi_vddq";</div><div class='add'>+				regulator-min-microvolt = &lt;300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;MT6360_OPMODE_NORMAL</div><div class='add'>+							   MT6360_OPMODE_LP</div><div class='add'>+							   MT6360_OPMODE_ULP&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6360_ldo1: ldo1 {</div><div class='add'>+				regulator-name = "mt6360_ldo1"; /* Test point */</div><div class='add'>+				regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3600000&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;MT6360_OPMODE_NORMAL</div><div class='add'>+							   MT6360_OPMODE_LP&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6360_ldo2: ldo2 {</div><div class='add'>+				regulator-name = "panel1_p1v8";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;MT6360_OPMODE_NORMAL</div><div class='add'>+							   MT6360_OPMODE_LP&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6360_ldo3: ldo3 {</div><div class='add'>+				regulator-name = "vmc_pmu";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;MT6360_OPMODE_NORMAL</div><div class='add'>+							   MT6360_OPMODE_LP&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6360_ldo5: ldo5 {</div><div class='add'>+				regulator-name = "vmch_pmu";</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;MT6360_OPMODE_NORMAL</div><div class='add'>+							   MT6360_OPMODE_LP&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6360_ldo6: ldo6 {</div><div class='add'>+				regulator-name = "mt6360_ldo6"; /* Test point */</div><div class='add'>+				regulator-min-microvolt = &lt;500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2100000&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;MT6360_OPMODE_NORMAL</div><div class='add'>+							   MT6360_OPMODE_LP&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6360_ldo7: ldo7 {</div><div class='add'>+				regulator-name = "emi_vmddr_en";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;MT6360_OPMODE_NORMAL</div><div class='add'>+							   MT6360_OPMODE_LP&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc0 {</div><div class='add'>+	pinctrl-names = "default", "state_uhs";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc0_default_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;mmc0_uhs_pins&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	hs400-ds-delay = &lt;0x14c11&gt;;</div><div class='add'>+	cap-mmc-highspeed;</div><div class='add'>+	cap-mmc-hw-reset;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	mmc-hs400-1_8v;</div><div class='add'>+	no-sdio;</div><div class='add'>+	no-sd;</div><div class='add'>+	non-removable;</div><div class='add'>+	vmmc-supply = &lt;&amp;mt6359_vemc_1_ldo_reg&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;mt6359_vufs_ldo_reg&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmc1 {</div><div class='add'>+	pinctrl-names = "default", "state_uhs";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc1_default_pins&gt;, &lt;&amp;mmc1_detect_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;mmc1_default_pins&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;pio 129 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	sd-uhs-sdr50;</div><div class='add'>+	sd-uhs-sdr104;</div><div class='add'>+	no-mmc;</div><div class='add'>+	vmmc-supply = &lt;&amp;mt6360_ldo5&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;mt6360_ldo3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vbbck_ldo_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vcore_buck_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vgpu11_buck_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vproc1_buck_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vproc2_buck_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vpu_buck_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vrf12_ldo_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vsram_md_ldo_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vsram_others_ldo_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;nor_flash {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;nor_pins_default&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash@0 {</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;52000000&gt;;</div><div class='add'>+		spi-rx-bus-width = &lt;2&gt;;</div><div class='add'>+		spi-tx-bus-width = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pcie0_pins_default&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pcie1_pins_default&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pciephy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	eth_default_pins: eth-default-pins {</div><div class='add'>+		pins-txd {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO77__FUNC_GBE_TXD3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO78__FUNC_GBE_TXD2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO79__FUNC_GBE_TXD1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO80__FUNC_GBE_TXD0&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-rxd {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO81__FUNC_GBE_RXD3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO82__FUNC_GBE_RXD2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO83__FUNC_GBE_RXD1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO84__FUNC_GBE_RXD0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-cc {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO85__FUNC_GBE_TXC&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO86__FUNC_GBE_RXC&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO87__FUNC_GBE_RXDV&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO88__FUNC_GBE_TXEN&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-mdio {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO89__FUNC_GBE_MDC&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO90__FUNC_GBE_MDIO&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-power {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO91__FUNC_GPIO91&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO92__FUNC_GPIO92&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-reset {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO93__FUNC_GPIO93&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-interrupt {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO94__FUNC_GPIO94&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eth_sleep_pins: eth-sleep-pins {</div><div class='add'>+		pins-txd {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO77__FUNC_GPIO77&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO78__FUNC_GPIO78&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO79__FUNC_GPIO79&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO80__FUNC_GPIO80&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-cc {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO85__FUNC_GPIO85&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO88__FUNC_GPIO88&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO87__FUNC_GPIO87&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO86__FUNC_GPIO86&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-rxd {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO81__FUNC_GPIO81&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO82__FUNC_GPIO82&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO83__FUNC_GPIO83&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO84__FUNC_GPIO84&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-mdio {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO89__FUNC_GPIO89&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO90__FUNC_GPIO90&gt;;</div><div class='add'>+			input-disable;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio_keys_pins: gpio-keys-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO106__FUNC_GPIO106&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c0_pins: i2c0-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO8__FUNC_SDA0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO9__FUNC_SCL0&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PULL_SET_RSEL_111&gt;;</div><div class='add'>+			drive-strength-microamp = &lt;1000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c1_pins: i2c1-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO10__FUNC_SDA1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO11__FUNC_SCL1&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PULL_SET_RSEL_111&gt;;</div><div class='add'>+			drive-strength-microamp = &lt;1000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c2_pins: i2c2-default-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO12__FUNC_SDA2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO13__FUNC_SCL2&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PULL_SET_RSEL_111&gt;;</div><div class='add'>+			drive-strength-microamp = &lt;1000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c3_pins: i2c3-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO14__FUNC_SDA3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO15__FUNC_SCL3&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PULL_SET_RSEL_111&gt;;</div><div class='add'>+			drive-strength-microamp = &lt;1000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c4_pins: i2c4-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO16__FUNC_SDA4&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO17__FUNC_SCL4&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PULL_SET_RSEL_111&gt;;</div><div class='add'>+			drive-strength-microamp = &lt;1000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c6_pins: i2c6-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO25__FUNC_SDA6&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO26__FUNC_SCL6&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+			drive-strength-microamp = &lt;1000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc0_default_pins: mmc0-default-pins {</div><div class='add'>+		pins-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO122__FUNC_MSDC0_CLK&gt;;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO126__FUNC_MSDC0_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO125__FUNC_MSDC0_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO124__FUNC_MSDC0_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO123__FUNC_MSDC0_DAT3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO119__FUNC_MSDC0_DAT4&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO118__FUNC_MSDC0_DAT5&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO117__FUNC_MSDC0_DAT6&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO116__FUNC_MSDC0_DAT7&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO121__FUNC_MSDC0_CMD&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-rst {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO120__FUNC_MSDC0_RSTB&gt;;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc0_uhs_pins: mmc0-uhs-pins {</div><div class='add'>+		pins-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO122__FUNC_MSDC0_CLK&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO126__FUNC_MSDC0_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO125__FUNC_MSDC0_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO124__FUNC_MSDC0_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO123__FUNC_MSDC0_DAT3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO119__FUNC_MSDC0_DAT4&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO118__FUNC_MSDC0_DAT5&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO117__FUNC_MSDC0_DAT6&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO116__FUNC_MSDC0_DAT7&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO121__FUNC_MSDC0_CMD&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-ds {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO127__FUNC_MSDC0_DSL&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-rst {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO120__FUNC_MSDC0_RSTB&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc1_default_pins: mmc1-default-pins {</div><div class='add'>+		pins-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO111__FUNC_MSDC1_CLK&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO110__FUNC_MSDC1_CMD&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO112__FUNC_MSDC1_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO113__FUNC_MSDC1_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO114__FUNC_MSDC1_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO115__FUNC_MSDC1_DAT3&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc1_detect_pins: mmc1-detect-pins {</div><div class='add'>+		pins-insert {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO129__FUNC_GPIO129&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	nor_pins_default: nor-default-pins {</div><div class='add'>+		pins-ck-io {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO142__FUNC_SPINOR_IO0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO141__FUNC_SPINOR_CK&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO143__FUNC_SPINOR_IO1&gt;;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-down;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-cs {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO140__FUNC_SPINOR_CS&gt;;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_pins_default: pcie0-default-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO19__FUNC_WAKEN&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO20__FUNC_PERSTN&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO21__FUNC_CLKREQN&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie1_pins_default: pcie1-default-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO0__FUNC_PERSTN_1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO1__FUNC_CLKREQN_1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO2__FUNC_WAKEN_1&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	led_pins: led-pins {</div><div class='add'>+		pins-power-en {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO107__FUNC_GPIO107&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi0_pins: spi0-default-pins {</div><div class='add'>+		pins-cs-mosi-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO132__FUNC_SPIM0_CSB&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO134__FUNC_SPIM0_MO&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO133__FUNC_SPIM0_CLK&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-miso {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO135__FUNC_SPIM0_MI&gt;;</div><div class='add'>+			bias-pull-down;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi1_pins: spi1-default-pins {</div><div class='add'>+		pins-cs-mosi-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO136__FUNC_SPIM1_CSB&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO138__FUNC_SPIM1_MO&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO137__FUNC_SPIM1_CLK&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-miso {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO139__FUNC_SPIM1_MI&gt;;</div><div class='add'>+			bias-pull-down;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart0_pins: uart0-pins {</div><div class='add'>+		pins-rx {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO99__FUNC_URXD0&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-tx {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO98__FUNC_UTXD0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart1_pins: uart1-pins {</div><div class='add'>+		pins-rx {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO103__FUNC_URXD1&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-tx {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO102__FUNC_UTXD1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-rts {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO100__FUNC_URTS1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-cts {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO101__FUNC_UCTS1&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart2_pins: uart2-pins {</div><div class='add'>+		pins-rx {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO68__FUNC_URXD2&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-tx {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO67__FUNC_UTXD2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-rts {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO66__FUNC_URTS2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-cts {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO65__FUNC_UCTS2&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart3_pins: uart3-pins {</div><div class='add'>+		pins-rx {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO5__FUNC_URXD3&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-tx {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO4__FUNC_UTXD3&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart4_pins: uart4-pins {</div><div class='add'>+		pins-rx {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO7__FUNC_URXD4&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-tx {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO6__FUNC_UTXD4&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pmic {</div><div class='add'>+	interrupts-extended = &lt;&amp;pio 222 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;scp {</div><div class='add'>+	memory-region = &lt;&amp;scp_mem&gt;;</div><div class='add'>+	firmware-name = "mediatek/mt8195/scp.img";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spmi {</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	mt6315@6 {</div><div class='add'>+		compatible = "mediatek,mt6315-regulator";</div><div class='add'>+		reg = &lt;0x6 SPMI_USID&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			mt6315_6_vbuck1: vbuck1 {</div><div class='add'>+				regulator-name = "Vbcpu";</div><div class='add'>+				regulator-min-microvolt = &lt;300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1193750&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;256&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;6250&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;0 1 2&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mt6315@7 {</div><div class='add'>+		compatible = "mediatek,mt6315-regulator";</div><div class='add'>+		reg = &lt;0x7 SPMI_USID&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			mt6315_7_vbuck1: vbuck1 {</div><div class='add'>+				regulator-name = "Vgpu";</div><div class='add'>+				regulator-min-microvolt = &lt;625000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1193750&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;256&gt;;</div><div class='add'>+				regulator-ramp-delay = &lt;6250&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;0 1 2&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB3.2 front port */</div><div class='add'>+&amp;ssusb0 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+	vusb33-supply = &lt;&amp;mt6359_vusb_ldo_reg&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB2.0 M.2 Key-E */</div><div class='add'>+&amp;ssusb2 {</div><div class='add'>+	vusb33-supply = &lt;&amp;mt6359_vusb_ldo_reg&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB2.0 to on-board usb hub */</div><div class='add'>+&amp;ssusb3 {</div><div class='add'>+	vusb33-supply = &lt;&amp;mt6359_vusb_ldo_reg&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;spi0_pins&gt;;</div><div class='add'>+	mediatek,pad-select = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	tpm: tpm@0 {</div><div class='add'>+		compatible = "infineon,slb9670", "tcg,tpm_tis-spi";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;18500000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* B2B connector */</div><div class='add'>+&amp;spi1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;spi1_pins&gt;;</div><div class='add'>+	mediatek,pad-select = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;thermal_zones {</div><div class='add'>+	cpu-thermal {</div><div class='add'>+		polling-delay = &lt;1000&gt;; /* milliseconds */</div><div class='add'>+		polling-delay-passive = &lt;0&gt;; /* milliseconds */</div><div class='add'>+		thermal-sensors = &lt;&amp;thermal_sensor0&gt;;</div><div class='add'>+</div><div class='add'>+		trips {</div><div class='add'>+			trip-alert {</div><div class='add'>+				temperature = &lt;85000&gt;;</div><div class='add'>+				hysteresis = &lt;2000&gt;;</div><div class='add'>+				type = "passive";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			trip-crit {</div><div class='add'>+				temperature = &lt;95000&gt;;</div><div class='add'>+				hysteresis = &lt;2000&gt;;</div><div class='add'>+				type = "critical";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcb-top-thermal {</div><div class='add'>+		polling-delay = &lt;1000&gt;; /* milliseconds */</div><div class='add'>+		polling-delay-passive = &lt;0&gt;; /* milliseconds */</div><div class='add'>+		thermal-sensors = &lt;&amp;thermal_sensor1&gt;;</div><div class='add'>+</div><div class='add'>+		trips {</div><div class='add'>+			trip-alert {</div><div class='add'>+				temperature = &lt;75000&gt;;</div><div class='add'>+				hysteresis = &lt;2000&gt;;</div><div class='add'>+				type = "passive";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			trip-crit {</div><div class='add'>+				temperature = &lt;85000&gt;;</div><div class='add'>+				hysteresis = &lt;2000&gt;;</div><div class='add'>+				type = "critical";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcb-bottom-thermal {</div><div class='add'>+		polling-delay = &lt;1000&gt;; /* milliseconds */</div><div class='add'>+		polling-delay-passive = &lt;0&gt;; /* milliseconds */</div><div class='add'>+		thermal-sensors = &lt;&amp;thermal_sensor2&gt;;</div><div class='add'>+</div><div class='add'>+		trips {</div><div class='add'>+			trip-alert {</div><div class='add'>+				temperature = &lt;75000&gt;;</div><div class='add'>+				hysteresis = &lt;2000&gt;;</div><div class='add'>+				type = "passive";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			trip-crit {</div><div class='add'>+				temperature = &lt;85000&gt;;</div><div class='add'>+				hysteresis = &lt;2000&gt;;</div><div class='add'>+				type = "critical";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart0_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart1_pins&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart2_pins&gt;;</div><div class='add'>+	uart-has-rtscts;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart3 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart3_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart4 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart4_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB3 */</div><div class='add'>+&amp;u3phy0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* PCIe1/USB2 */</div><div class='add'>+&amp;u3phy1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB2 */</div><div class='add'>+&amp;u3phy2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB2 */</div><div class='add'>+&amp;u3phy3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB3.2 front port */</div><div class='add'>+&amp;xhci0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB2.0 M.2 Key-B */</div><div class='add'>+&amp;xhci1 {</div><div class='add'>+	phys = &lt;&amp;u2port1 PHY_TYPE_USB2&gt;;</div><div class='add'>+	vusb33-supply = &lt;&amp;mt6359_vusb_ldo_reg&gt;;</div><div class='add'>+	mediatek,u3p-dis-msk = &lt;0x01&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB2.0 M.2 Key-E */</div><div class='add'>+&amp;xhci2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* USB2.0 to on-board usb hub */</div><div class='add'>+&amp;xhci3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l-8-hd-panel.dtso b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l-8-hd-panel.dtso<br/>new file mode 100644<br/>index 000000000000..0389c9cb8581<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l-8-hd-panel.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l-8-hd-panel.dtso</a></div><div class='hunk'>@@ -0,0 +1,84 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Radxa Display 8 HD touchscreen module</div><div class='add'>+ * Copyright (C) 2025 Collabora Ltd.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+</div><div class='add'>+&amp;backlight {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;disp_pwm0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pwm0_default_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsi0 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	panel@0 {</div><div class='add'>+		compatible = "radxa,display-8hd-ad002", "jadard,jd9365da-h3";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		backlight = &lt;&amp;backlight&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;mt6359_vcn33_2_bt_ldo_reg&gt;;</div><div class='add'>+		vccio-supply = &lt;&amp;mt6360_ldo2&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pio 108 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;panel_default_pins&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			dsi_panel_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;dsi0_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsi0_out {</div><div class='add'>+	remote-endpoint = &lt;&amp;dsi_panel_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	touchscreen@14 {</div><div class='add'>+		compatible = "goodix,gt911";</div><div class='add'>+		reg = &lt;0x14&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 132 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+		irq-gpios = &lt;&amp;pio 132 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pio 133 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		VDDIO-supply = &lt;&amp;mt6359_vcn33_2_bt_ldo_reg&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;touch_pins&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mipi_tx0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ovl0_in {</div><div class='add'>+	remote-endpoint = &lt;&amp;vdosys0_ep_main&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;vdosys0 {</div><div class='add'>+	port {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		vdosys0_ep_main: endpoint@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			remote-endpoint = &lt;&amp;ovl0_in&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts<br/>new file mode 100644<br/>index 000000000000..d32f973f5e05<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts</a></div><div class='hunk'>@@ -0,0 +1,1079 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2023 Radxa Limited</div><div class='add'>+ * Copyright (C) 2024 Collabora Ltd.</div><div class='add'>+ *                    AngeloGioacchino Del Regno &lt;angelogioacchino.delregno@collabora.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "mt8195.dtsi"</div><div class='add'>+#include "mt6359.dtsi"</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/mt8195-pinfunc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/regulator/mediatek,mt6360-regulator.h&gt;</div><div class='add'>+#include &lt;dt-bindings/spmi/spmi.h&gt;</div><div class='add'>+#include &lt;dt-bindings/usb/pd.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Radxa NIO 12L";</div><div class='add'>+	chassis-type = "embedded";</div><div class='add'>+	compatible = "radxa,nio-12l", "mediatek,mt8395", "mediatek,mt8195";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		i2c0 = &amp;i2c2;</div><div class='add'>+		i2c1 = &amp;i2c3;</div><div class='add'>+		i2c2 = &amp;i2c4;</div><div class='add'>+		i2c3 = &amp;i2c0;</div><div class='add'>+		i2c4 = &amp;i2c1;</div><div class='add'>+		ethernet0 = &amp;eth;</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+		serial1 = &amp;uart1;</div><div class='add'>+		spi0 = &amp;spi1;</div><div class='add'>+		spi1 = &amp;spi2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:921600n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	firmware {</div><div class='add'>+		optee {</div><div class='add'>+			compatible = "linaro,optee-tz";</div><div class='add'>+			method = "smc";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0 0x40000000 0x1 0x0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	backlight: backlight {</div><div class='add'>+		compatible = "pwm-backlight";</div><div class='add'>+		brightness-levels = &lt;0 1023&gt;;</div><div class='add'>+		default-brightness-level = &lt;576&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;pio 107 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		num-interpolated-steps = &lt;1023&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;dsi0_backlight_pins&gt;;</div><div class='add'>+		pwms = &lt;&amp;disp_pwm0 0 500000&gt;;</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	keys: gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		button-volume-up {</div><div class='add'>+			wakeup-source;</div><div class='add'>+			debounce-interval = &lt;100&gt;;</div><div class='add'>+			gpios = &lt;&amp;pio 106 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			label = "volume_up";</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wifi_vreg: regulator-wifi-3v3-en {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "wifi_3v3_en";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;pio 67 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;wifi_vreg_pins&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vsys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* system wide switching 5.0V power rail */</div><div class='add'>+	vsys: regulator-vsys {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vsys";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vcc5v0_vsys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vsys_buck: regulator-vsys-buck {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vsys_buck";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vcc5v0_vsys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Rail from power-only "TYPE C DC" port */</div><div class='add'>+	vcc5v0_vsys: regulator-vcc5v0-sys {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vcc5v0_sys";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * 12 MiB reserved for OP-TEE (BL32)</div><div class='add'>+		 * +-----------------------+ 0x43e0_0000</div><div class='add'>+		 * |      SHMEM 2MiB       |</div><div class='add'>+		 * +-----------------------+ 0x43c0_0000</div><div class='add'>+		 * |        | TA_RAM  8MiB |</div><div class='add'>+		 * + TZDRAM +--------------+ 0x4340_0000</div><div class='add'>+		 * |        | TEE_RAM 2MiB |</div><div class='add'>+		 * +-----------------------+ 0x4320_0000</div><div class='add'>+		 */</div><div class='add'>+		optee_reserved: optee@43200000 {</div><div class='add'>+			reg = &lt;0 0x43200000 0 0xc00000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		scp_mem: memory@50000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x50000000 0 0x2900000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vpu_mem: memory@53000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x53000000 0 0x1400000&gt;; /* 20 MB */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* 2 MiB reserved for ARM Trusted Firmware (BL31) */</div><div class='add'>+		bl31_secmon_mem: memory@54600000 {</div><div class='add'>+			reg = &lt;0 0x54600000 0x0 0x200000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		adsp_mem: memory@60000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x60000000 0 0xf00000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		afe_dma_mem: memory@60f00000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x60f00000 0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		adsp_dma_mem: memory@61000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x61000000 0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		apu_mem: memory@62000000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0 0x62000000 0 0x1400000&gt;; /* 20 MB */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;adsp {</div><div class='add'>+	memory-region = &lt;&amp;adsp_dma_mem&gt;, &lt;&amp;adsp_mem&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;afe {</div><div class='add'>+	memory-region = &lt;&amp;afe_dma_mem&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	cpu-supply = &lt;&amp;mt6359_vcore_buck_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu1 {</div><div class='add'>+	cpu-supply = &lt;&amp;mt6359_vcore_buck_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu2 {</div><div class='add'>+	cpu-supply = &lt;&amp;mt6359_vcore_buck_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu3 {</div><div class='add'>+	cpu-supply = &lt;&amp;mt6359_vcore_buck_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu4 {</div><div class='add'>+	cpu-supply = &lt;&amp;mt6315_6_vbuck1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu5 {</div><div class='add'>+	cpu-supply = &lt;&amp;mt6315_6_vbuck1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu6 {</div><div class='add'>+	cpu-supply = &lt;&amp;mt6315_6_vbuck1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu7 {</div><div class='add'>+	cpu-supply = &lt;&amp;mt6315_6_vbuck1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dither0_out {</div><div class='add'>+	remote-endpoint = &lt;&amp;dsi0_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dsi0 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		port@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			dsi0_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;dither0_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			dsi0_out: endpoint { };</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;eth {</div><div class='add'>+	phy-mode = "rgmii-rxid";</div><div class='add'>+	phy-handle = &lt;&amp;rgmii_phy&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;eth_default_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;eth_sleep_pins&gt;;</div><div class='add'>+	mediatek,tx-delay-ps = &lt;2030&gt;;</div><div class='add'>+	mediatek,mac-wol;</div><div class='add'>+	snps,reset-gpio = &lt;&amp;pio 93 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	snps,reset-delays-us = &lt;0 20000 100000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		rgmii_phy: ethernet-phy@1 {</div><div class='add'>+			compatible = "ethernet-phy-id001c.c916";</div><div class='add'>+			reg = &lt;0x1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	mali-supply = &lt;&amp;mt6315_7_vbuck1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c2 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c2_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	typec-mux@48 {</div><div class='add'>+		compatible = "ite,it5205";</div><div class='add'>+		reg = &lt;0x48&gt;;</div><div class='add'>+</div><div class='add'>+		mode-switch;</div><div class='add'>+		orientation-switch;</div><div class='add'>+</div><div class='add'>+		vcc-supply = &lt;&amp;mt6359_vibr_ldo_reg&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			it5205_sbu_mux: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;typec_con_mux&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c4 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c4_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* I2C4 exposed at 39-pins MIPI-LCD connector */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c6 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c6_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mt6360: pmic@34 {</div><div class='add'>+		compatible = "mediatek,mt6360";</div><div class='add'>+		reg = &lt;0x34&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;pio 101 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		interrupt-names = "IRQB";</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;mt6360_pins&gt;;</div><div class='add'>+</div><div class='add'>+		charger {</div><div class='add'>+			compatible = "mediatek,mt6360-chg";</div><div class='add'>+			richtek,vinovp-microvolt = &lt;14500000&gt;;</div><div class='add'>+</div><div class='add'>+			otg_vbus_regulator: usb-otg-vbus-regulator {</div><div class='add'>+				regulator-name = "usb-otg-vbus";</div><div class='add'>+				regulator-min-microvolt = &lt;4425000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;5825000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		regulator {</div><div class='add'>+			compatible = "mediatek,mt6360-regulator";</div><div class='add'>+			LDO_VIN1-supply = &lt;&amp;vsys_buck&gt;;</div><div class='add'>+			LDO_VIN3-supply = &lt;&amp;mt6360_buck2&gt;;</div><div class='add'>+</div><div class='add'>+			mt6360_buck1: buck1 {</div><div class='add'>+				regulator-name = "emi_vdd2";</div><div class='add'>+				regulator-min-microvolt = &lt;300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;MT6360_OPMODE_NORMAL</div><div class='add'>+							   MT6360_OPMODE_LP</div><div class='add'>+							   MT6360_OPMODE_ULP&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6360_buck2: buck2 {</div><div class='add'>+				regulator-name = "emi_vddq";</div><div class='add'>+				regulator-min-microvolt = &lt;300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;MT6360_OPMODE_NORMAL</div><div class='add'>+							   MT6360_OPMODE_LP</div><div class='add'>+							   MT6360_OPMODE_ULP&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6360_ldo1: ldo1 {</div><div class='add'>+				regulator-name = "ext_lcd_3v3";</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;MT6360_OPMODE_NORMAL</div><div class='add'>+							   MT6360_OPMODE_LP&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6360_ldo2: ldo2 {</div><div class='add'>+				regulator-name = "panel1_p1v8";</div><div class='add'>+				regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;MT6360_OPMODE_NORMAL</div><div class='add'>+							   MT6360_OPMODE_LP&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6360_ldo3: ldo3 {</div><div class='add'>+				regulator-name = "vmc_pmu";</div><div class='add'>+				regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3600000&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;MT6360_OPMODE_NORMAL</div><div class='add'>+							   MT6360_OPMODE_LP&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6360_ldo5: ldo5 {</div><div class='add'>+				regulator-name = "vmch_pmu";</div><div class='add'>+				regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;MT6360_OPMODE_NORMAL</div><div class='add'>+							   MT6360_OPMODE_LP&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6360_ldo6: ldo6 {</div><div class='add'>+				regulator-name = "mt6360_ldo6"; /* Test point */</div><div class='add'>+				regulator-min-microvolt = &lt;500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2100000&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;MT6360_OPMODE_NORMAL</div><div class='add'>+							   MT6360_OPMODE_LP&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mt6360_ldo7: ldo7 {</div><div class='add'>+				regulator-name = "emi_vmddr_en";</div><div class='add'>+				regulator-min-microvolt = &lt;500000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;2100000&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;MT6360_OPMODE_NORMAL</div><div class='add'>+							   MT6360_OPMODE_LP&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		typec {</div><div class='add'>+			compatible = "mediatek,mt6360-tcpc";</div><div class='add'>+			interrupts-extended = &lt;&amp;pio 100 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			interrupt-names = "PD_IRQB";</div><div class='add'>+</div><div class='add'>+			connector {</div><div class='add'>+				compatible = "usb-c-connector";</div><div class='add'>+				label = "USB-C";</div><div class='add'>+				data-role = "dual";</div><div class='add'>+				op-sink-microwatt = &lt;10000000&gt;;</div><div class='add'>+				power-role = "dual";</div><div class='add'>+				try-power-role = "sink";</div><div class='add'>+</div><div class='add'>+				source-pdos = &lt;PDO_FIXED(5000, 1000,</div><div class='add'>+							 PDO_FIXED_DUAL_ROLE |</div><div class='add'>+							 PDO_FIXED_DATA_SWAP)&gt;;</div><div class='add'>+				sink-pdos = &lt;PDO_FIXED(5000, 3000,</div><div class='add'>+						       PDO_FIXED_DUAL_ROLE |</div><div class='add'>+						       PDO_FIXED_DATA_SWAP)&gt;;</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+						typec_con_hs: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mtu3_hs0_role_sw&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@2 {</div><div class='add'>+						reg = &lt;2&gt;;</div><div class='add'>+						typec_con_mux: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;it5205_sbu_mux&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mfg0 {</div><div class='add'>+	domain-supply = &lt;&amp;mt6315_7_vbuck1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mfg1 {</div><div class='add'>+	domain-supply = &lt;&amp;mt6359_vsram_others_ldo_reg&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* MMC0 Controller: eMMC (HS400). Power lines are shared with UFS! */</div><div class='add'>+&amp;mmc0 {</div><div class='add'>+	pinctrl-names = "default", "state_uhs";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc0_default_pins&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;mmc0_uhs_pins&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	hs400-ds-delay = &lt;0x14c11&gt;;</div><div class='add'>+	cap-mmc-highspeed;</div><div class='add'>+	cap-mmc-hw-reset;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	mmc-hs400-1_8v;</div><div class='add'>+	no-sdio;</div><div class='add'>+	no-sd;</div><div class='add'>+	non-removable;</div><div class='add'>+	vmmc-supply = &lt;&amp;mt6359_vemc_1_ldo_reg&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;mt6359_vufs_ldo_reg&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* MMC1 Controller: MicroSD card slot */</div><div class='add'>+&amp;mmc1 {</div><div class='add'>+	pinctrl-names = "default", "state_uhs";</div><div class='add'>+	pinctrl-0 = &lt;&amp;mmc1_default_pins&gt;, &lt;&amp;mmc1_pins_detect&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;mmc1_default_pins&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	max-frequency = &lt;200000000&gt;;</div><div class='add'>+	cap-sd-highspeed;</div><div class='add'>+	cd-gpios = &lt;&amp;pio 129 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	no-mmc;</div><div class='add'>+	no-sdio;</div><div class='add'>+	sd-uhs-sdr50;</div><div class='add'>+	sd-uhs-sdr104;</div><div class='add'>+	vmmc-supply = &lt;&amp;mt6360_ldo5&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;mt6360_ldo3&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vaud18_ldo_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vbbck_ldo_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* For USB Hub */</div><div class='add'>+&amp;mt6359_vcamio_ldo_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vcn33_2_bt_ldo_reg {</div><div class='add'>+	regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vcore_buck_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vgpu11_buck_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vproc1_buck_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vproc2_buck_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vpu_buck_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vrf12_ldo_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mt6359_vsram_md_ldo_reg {</div><div class='add'>+	regulator-always-on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* for GPU SRAM */</div><div class='add'>+&amp;mt6359_vsram_others_ldo_reg {</div><div class='add'>+	regulator-min-microvolt = &lt;750000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;750000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pio {</div><div class='add'>+	mediatek,rsel-resistance-in-si-unit;</div><div class='add'>+</div><div class='add'>+	audio_default_pins: audio-default-pins {</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO70__FUNC_AUD_SYNC_MOSI&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO69__FUNC_AUD_CLK_MOSI&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO71__FUNC_AUD_DAT_MOSI0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO72__FUNC_AUD_DAT_MOSI1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO73__FUNC_AUD_DAT_MISO0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO74__FUNC_AUD_DAT_MISO1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO75__FUNC_AUD_DAT_MISO2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dsi0_backlight_pins: dsi0-backlight-pins {</div><div class='add'>+		pins-backlight-en {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO107__FUNC_GPIO107&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eth_default_pins: eth-default-pins {</div><div class='add'>+		pins-cc {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO85__FUNC_GBE_TXC&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO86__FUNC_GBE_RXC&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO87__FUNC_GBE_RXDV&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO88__FUNC_GBE_TXEN&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-mdio {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO89__FUNC_GBE_MDC&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO90__FUNC_GBE_MDIO&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-power {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO91__FUNC_GPIO91&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO92__FUNC_GPIO92&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-rst {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO93__FUNC_GPIO93&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-rxd {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO81__FUNC_GBE_RXD3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO82__FUNC_GBE_RXD2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO83__FUNC_GBE_RXD1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO84__FUNC_GBE_RXD0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-txd {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO77__FUNC_GBE_TXD3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO78__FUNC_GBE_TXD2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO79__FUNC_GBE_TXD1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO80__FUNC_GBE_TXD0&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eth_sleep_pins: eth-sleep-pins {</div><div class='add'>+		pins-cc {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO85__FUNC_GPIO85&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO86__FUNC_GPIO86&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO87__FUNC_GPIO87&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO88__FUNC_GPIO88&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-mdio {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO89__FUNC_GPIO89&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO90__FUNC_GPIO90&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+			input-disable;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-rxd {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO81__FUNC_GPIO81&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO82__FUNC_GPIO82&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO83__FUNC_GPIO83&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO84__FUNC_GPIO84&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-txd {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO77__FUNC_GPIO77&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO78__FUNC_GPIO78&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO79__FUNC_GPIO79&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO80__FUNC_GPIO80&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio_key_pins: gpio-keys-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO106__FUNC_GPIO106&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c2_pins: i2c2-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO12__FUNC_SDA2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO13__FUNC_SCL2&gt;;</div><div class='add'>+			bias-pull-up = &lt;1000&gt;;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			drive-strength-microamp = &lt;1000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c4_pins: i2c4-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO16__FUNC_SDA4&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO17__FUNC_SCL4&gt;;</div><div class='add'>+			bias-pull-up = &lt;1000&gt;;</div><div class='add'>+			drive-strength-microamp = &lt;1000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c6_pins: i2c6-pins {</div><div class='add'>+		pins {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO25__FUNC_SDA6&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO26__FUNC_SCL6&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc0_default_pins: mmc0-default-pins {</div><div class='add'>+		pins-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO122__FUNC_MSDC0_CLK&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO126__FUNC_MSDC0_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO125__FUNC_MSDC0_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO124__FUNC_MSDC0_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO123__FUNC_MSDC0_DAT3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO119__FUNC_MSDC0_DAT4&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO118__FUNC_MSDC0_DAT5&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO117__FUNC_MSDC0_DAT6&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO116__FUNC_MSDC0_DAT7&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO121__FUNC_MSDC0_CMD&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-rst {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO120__FUNC_MSDC0_RSTB&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc0_uhs_pins: mmc0-uhs-pins {</div><div class='add'>+		pins-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO122__FUNC_MSDC0_CLK&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO126__FUNC_MSDC0_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO125__FUNC_MSDC0_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO124__FUNC_MSDC0_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO123__FUNC_MSDC0_DAT3&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO119__FUNC_MSDC0_DAT4&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO118__FUNC_MSDC0_DAT5&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO117__FUNC_MSDC0_DAT6&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO116__FUNC_MSDC0_DAT7&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO121__FUNC_MSDC0_CMD&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-ds {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO127__FUNC_MSDC0_DSL&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-rst {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO120__FUNC_MSDC0_RSTB&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc1_default_pins: mmc1-default-pins {</div><div class='add'>+		pins-clk {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO111__FUNC_MSDC1_CLK&gt;;</div><div class='add'>+			bias-pull-down = &lt;MTK_PUPD_SET_R1R0_10&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-cmd-dat {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO110__FUNC_MSDC1_CMD&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO112__FUNC_MSDC1_DAT0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO113__FUNC_MSDC1_DAT1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO114__FUNC_MSDC1_DAT2&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO115__FUNC_MSDC1_DAT3&gt;;</div><div class='add'>+			bias-pull-up = &lt;MTK_PUPD_SET_R1R0_01&gt;;</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc1_pins_detect: mmc1-detect-pins {</div><div class='add'>+		pins-insert {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO129__FUNC_GPIO129&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mt6360_pins: mt6360-pins {</div><div class='add'>+		pins-irq {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO100__FUNC_GPIO100&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO101__FUNC_GPIO101&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	panel_default_pins: panel-pins {</div><div class='add'>+		pins-rst {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO108__FUNC_GPIO108&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_default_pins: pcie0-default-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO19__FUNC_WAKEN&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO20__FUNC_PERSTN&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO21__FUNC_CLKREQN&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie1_default_pins: pcie1-default-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO0__FUNC_PERSTN_1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO1__FUNC_CLKREQN_1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO2__FUNC_WAKEN_1&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pwm0_default_pins: pwm0-pins {</div><div class='add'>+		pins-disp-pwm {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO97__FUNC_DISP_PWM0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi1_pins: spi1-default-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO136__FUNC_SPIM1_CSB&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO137__FUNC_SPIM1_CLK&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO138__FUNC_SPIM1_MO&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO139__FUNC_SPIM1_MI&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi2_pins: spi2-default-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO140__FUNC_SPIM2_CSB&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO141__FUNC_SPIM2_CLK&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO142__FUNC_SPIM2_MO&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO143__FUNC_SPIM2_MI&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	touch_pins: touch-pins {</div><div class='add'>+		pins-touch-int {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO132__FUNC_GPIO132&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-touch-rst {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO133__FUNC_GPIO133&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart0_pins: uart0-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO98__FUNC_UTXD0&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO99__FUNC_URXD0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart1_pins: uart1-pins {</div><div class='add'>+		pins-bus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO102__FUNC_UTXD1&gt;,</div><div class='add'>+				 &lt;PINMUX_GPIO103__FUNC_URXD1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb3_port0_pins: usb3p0-default-pins {</div><div class='add'>+		pins-vbus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO63__FUNC_VBUSVALID&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb2_port0_pins: usb2p0-default-pins {</div><div class='add'>+		pins-iddig {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO130__FUNC_IDDIG_1P&gt;;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-vbus {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO131__FUNC_USB_DRVVBUS_1P&gt;;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wifi_vreg_pins: wifi-vreg-pins {</div><div class='add'>+		pins-wifi-pmu-en {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO65__FUNC_GPIO65&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pins-wifi-vreg-en {</div><div class='add'>+			pinmux = &lt;PINMUX_GPIO67__FUNC_GPIO67&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pcie0_default_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pcie1_default_pins&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pciephy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pmic {</div><div class='add'>+	interrupts-extended = &lt;&amp;pio 222 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+	mt6359keys: keys {</div><div class='add'>+		compatible = "mediatek,mt6359-keys";</div><div class='add'>+		mediatek,long-press-mode = &lt;1&gt;;</div><div class='add'>+		power-off-time-sec = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		power-key {</div><div class='add'>+			linux,keycodes = &lt;KEY_POWER&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		home {</div><div class='add'>+			linux,keycodes = &lt;KEY_HOME&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;scp {</div><div class='add'>+	memory-region = &lt;&amp;scp_mem&gt;;</div><div class='add'>+	firmware-name = "mediatek/mt8195/scp.img";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sound {</div><div class='add'>+	compatible = "mediatek,mt8195_mt6359";</div><div class='add'>+	model = "mt8395-evk";</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;audio_default_pins&gt;;</div><div class='add'>+	audio-routing =</div><div class='add'>+		"Headphone", "Headphone L",</div><div class='add'>+		"Headphone", "Headphone R";</div><div class='add'>+	mediatek,adsp = &lt;&amp;adsp&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	headphone-dai-link {</div><div class='add'>+		link-name = "DL_SRC_BE";</div><div class='add'>+</div><div class='add'>+		codec {</div><div class='add'>+			sound-dai = &lt;&amp;pmic 0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi1 {</div><div class='add'>+	/* Exposed at 40 pin connector */</div><div class='add'>+	pinctrl-0 = &lt;&amp;spi1_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	mediatek,pad-select = &lt;0&gt;;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi2 {</div><div class='add'>+	/* Exposed at 40 pin connector */</div><div class='add'>+	pinctrl-0 = &lt;&amp;spi2_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	mediatek,pad-select = &lt;0&gt;;</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spmi {</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	mt6315_6: pmic@6 {</div><div class='add'>+		compatible = "mediatek,mt6315-regulator";</div><div class='add'>+		reg = &lt;0x6 SPMI_USID&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			mt6315_6_vbuck1: vbuck1 {</div><div class='add'>+				regulator-name = "Vbcpu";</div><div class='add'>+				regulator-min-microvolt = &lt;300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1193750&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;256&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;0 1 2&gt;;</div><div class='add'>+				regulator-always-on;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mt6315_7: pmic@7 {</div><div class='add'>+		compatible = "mediatek,mt6315-regulator";</div><div class='add'>+		reg = &lt;0x7 SPMI_USID&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			mt6315_7_vbuck1: vbuck1 {</div><div class='add'>+				regulator-name = "Vgpu";</div><div class='add'>+				regulator-min-microvolt = &lt;300000&gt;;</div><div class='add'>+				regulator-max-microvolt = &lt;1193750&gt;;</div><div class='add'>+				regulator-enable-ramp-delay = &lt;256&gt;;</div><div class='add'>+				regulator-allowed-modes = &lt;0 1 2&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;u3phy0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;u3phy1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;u3phy2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	/* Exposed at 40 pin connector */</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart0_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	/* Exposed at 40 pin connector */</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart1_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ufshci {</div><div class='add'>+	vcc-supply = &lt;&amp;mt6359_vemc_1_ldo_reg&gt;;</div><div class='add'>+	vccq2-supply = &lt;&amp;mt6359_vufs_ldo_reg&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ufsphy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ssusb0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;usb3_port0_pins&gt;;</div><div class='add'>+	role-switch-default-mode = "host";</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	vusb33-supply = &lt;&amp;mt6359_vusb_ldo_reg&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	port {</div><div class='add'>+		mtu3_hs0_role_sw: endpoint {</div><div class='add'>+			remote-endpoint = &lt;&amp;typec_con_hs&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ssusb2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;usb2_port0_pins&gt;;</div><div class='add'>+	vusb33-supply = &lt;&amp;mt6359_vusb_ldo_reg&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xhci0 {</div><div class='add'>+	vbus-supply = &lt;&amp;otg_vbus_regulator&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xhci1 {</div><div class='add'>+	phys = &lt;&amp;u2port1 PHY_TYPE_USB2&gt;;</div><div class='add'>+	/* MT7921's USB Bluetooth has issues with USB2 LPM */</div><div class='add'>+	usb2-lpm-disable;</div><div class='add'>+	vusb33-supply = &lt;&amp;mt6359_vusb_ldo_reg&gt;;</div><div class='add'>+	vbus-supply = &lt;&amp;vsys&gt;;</div><div class='add'>+	mediatek,u3p-dis-msk = &lt;1&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xhci2 {</div><div class='add'>+	vbus-supply = &lt;&amp;vsys&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8516-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8516-pumpkin.dts<br/>index cce642c53812..3d3db33a64dc 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8516-pumpkin.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8516-pumpkin.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8516-pumpkin.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8516-pumpkin.dts</a></div><div class='hunk'>@@ -11,7 +11,7 @@</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	model = "Pumpkin MT8516";</div><div class='del'>-	compatible = "mediatek,mt8516";</div><div class='add'>+	compatible = "mediatek,mt8516-pumpkin", "mediatek,mt8516";</div><div class='ctx'> </div><div class='ctx'> 	memory@40000000 {</div><div class='ctx'> 		device_type = "memory";</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/mt8516.dtsi b/arch/arm64/boot/dts/mediatek/mt8516.dtsi<br/>index 2f8adf042195..b5e753759465 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8516.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/mt8516.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/mt8516.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/mt8516.dtsi</a></div><div class='hunk'>@@ -144,10 +144,10 @@</div><div class='ctx'> 		#size-cells = &lt;2&gt;;</div><div class='ctx'> 		ranges;</div><div class='ctx'> </div><div class='del'>-		/* 128 KiB reserved for ARM Trusted Firmware (BL31) */</div><div class='add'>+		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */</div><div class='ctx'> 		bl31_secmon_reserved: secmon@43000000 {</div><div class='ctx'> 			no-map;</div><div class='del'>-			reg = &lt;0 0x43000000 0 0x20000&gt;;</div><div class='add'>+			reg = &lt;0 0x43000000 0 0x30000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -165,7 +165,7 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	pmu {</div><div class='del'>-		compatible = "arm,armv8-pmuv3";</div><div class='add'>+		compatible = "arm,cortex-a35-pmu";</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 4 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='ctx'> 			     &lt;GIC_SPI 5 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='ctx'> 			     &lt;GIC_SPI 6 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='hunk'>@@ -191,17 +191,22 @@</div><div class='ctx'> 			#clock-cells = &lt;1&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		pericfg: pericfg@10003050 {</div><div class='add'>+			compatible = "mediatek,mt8516-pericfg", "syscon";</div><div class='add'>+			reg = &lt;0 0x10003050 0 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		apmixedsys: apmixedsys@10018000 {</div><div class='ctx'> 			compatible = "mediatek,mt8516-apmixedsys", "syscon";</div><div class='ctx'> 			reg = &lt;0 0x10018000 0 0x710&gt;;</div><div class='ctx'> 			#clock-cells = &lt;1&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		toprgu: toprgu@10007000 {</div><div class='add'>+		watchdog@10007000 {</div><div class='ctx'> 			compatible = "mediatek,mt8516-wdt",</div><div class='ctx'> 				     "mediatek,mt6589-wdt";</div><div class='ctx'> 			reg = &lt;0 0x10007000 0 0x1000&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 198 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 198 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 			#reset-cells = &lt;1&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -215,6 +220,17 @@</div><div class='ctx'> 			clock-names = "clk13m", "bus";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		keypad: keypad@10002000 {</div><div class='add'>+			compatible = "mediatek,mt8516-keypad",</div><div class='add'>+				     "mediatek,mt6779-keypad";</div><div class='add'>+			reg = &lt;0 0x10002000 0 0x1000&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+			interrupts = &lt;GIC_SPI 149 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk26m&gt;;</div><div class='add'>+			clock-names = "kpd";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		syscfg_pctl: syscfg-pctl@10005000 {</div><div class='ctx'> 			compatible = "syscon";</div><div class='ctx'> 			reg = &lt;0 0x10005000 0 0x1000&gt;;</div><div class='hunk'>@@ -224,7 +240,6 @@</div><div class='ctx'> 			compatible = "mediatek,mt8516-pinctrl";</div><div class='ctx'> 			reg = &lt;0 0x1000b000 0 0x1000&gt;;</div><div class='ctx'> 			mediatek,pctl-regmap = &lt;&amp;syscfg_pctl&gt;;</div><div class='del'>-			pins-are-numbered;</div><div class='ctx'> 			gpio-controller;</div><div class='ctx'> 			#gpio-cells = &lt;2&gt;;</div><div class='ctx'> 			interrupt-controller;</div><div class='hunk'>@@ -232,6 +247,13 @@</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		efuse: efuse@10009000 {</div><div class='add'>+			compatible = "mediatek,mt8516-efuse", "mediatek,efuse";</div><div class='add'>+			reg = &lt;0 0x10009000 0 0x1000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		pwrap: pwrap@1000f000 {</div><div class='ctx'> 			compatible = "mediatek,mt8516-pwrap";</div><div class='ctx'> 			reg = &lt;0 0x1000f000 0 0x1000&gt;;</div><div class='hunk'>@@ -257,13 +279,34 @@</div><div class='ctx'> 			interrupt-parent = &lt;&amp;gic&gt;;</div><div class='ctx'> 			interrupt-controller;</div><div class='ctx'> 			reg = &lt;0 0x10310000 0 0x1000&gt;,</div><div class='del'>-			      &lt;0 0x10320000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x1032f000 0 0x2000&gt;,</div><div class='ctx'> 			      &lt;0 0x10340000 0 0x2000&gt;,</div><div class='ctx'> 			      &lt;0 0x10360000 0 0x2000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_PPI 9</div><div class='ctx'> 				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		apdma: dma-controller@11000480 {</div><div class='add'>+			compatible = "mediatek,mt8516-uart-dma",</div><div class='add'>+				     "mediatek,mt6577-uart-dma";</div><div class='add'>+			reg = &lt;0 0x11000480 0 0x80&gt;,</div><div class='add'>+			      &lt;0 0x11000500 0 0x80&gt;,</div><div class='add'>+			      &lt;0 0x11000580 0 0x80&gt;,</div><div class='add'>+			      &lt;0 0x11000600 0 0x80&gt;,</div><div class='add'>+			      &lt;0 0x11000980 0 0x80&gt;,</div><div class='add'>+			      &lt;0 0x11000a00 0 0x80&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 96 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+				     &lt;GIC_SPI 97 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+				     &lt;GIC_SPI 98 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+				     &lt;GIC_SPI 99 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+				     &lt;GIC_SPI 100 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+				     &lt;GIC_SPI 101 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			dma-requests = &lt;6&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_APDMA&gt;;</div><div class='add'>+			clock-names = "apdma";</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		uart0: serial@11005000 {</div><div class='ctx'> 			compatible = "mediatek,mt8516-uart",</div><div class='ctx'> 				     "mediatek,mt6577-uart";</div><div class='hunk'>@@ -272,6 +315,9 @@</div><div class='ctx'> 			clocks = &lt;&amp;topckgen CLK_TOP_UART0_SEL&gt;,</div><div class='ctx'> 				 &lt;&amp;topckgen CLK_TOP_UART0&gt;;</div><div class='ctx'> 			clock-names = "baud", "bus";</div><div class='add'>+			dmas = &lt;&amp;apdma 0</div><div class='add'>+				&amp;apdma 1&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -283,6 +329,9 @@</div><div class='ctx'> 			clocks = &lt;&amp;topckgen CLK_TOP_UART1_SEL&gt;,</div><div class='ctx'> 				 &lt;&amp;topckgen CLK_TOP_UART1&gt;;</div><div class='ctx'> 			clock-names = "baud", "bus";</div><div class='add'>+			dmas = &lt;&amp;apdma 2</div><div class='add'>+				&amp;apdma 3&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -294,6 +343,9 @@</div><div class='ctx'> 			clocks = &lt;&amp;topckgen CLK_TOP_UART2_SEL&gt;,</div><div class='ctx'> 				 &lt;&amp;topckgen CLK_TOP_UART2&gt;;</div><div class='ctx'> 			clock-names = "baud", "bus";</div><div class='add'>+			dmas = &lt;&amp;apdma 4</div><div class='add'>+				&amp;apdma 5&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -303,14 +355,10 @@</div><div class='ctx'> 			reg = &lt;0 0x11009000 0 0x90&gt;,</div><div class='ctx'> 			      &lt;0 0x11000180 0 0x80&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 80 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='del'>-			clocks = &lt;&amp;topckgen CLK_TOP_AHB_INFRA_D2&gt;,</div><div class='del'>-				 &lt;&amp;infracfg CLK_IFR_I2C0_SEL&gt;,</div><div class='del'>-				 &lt;&amp;topckgen CLK_TOP_I2C0&gt;,</div><div class='add'>+			clock-div = &lt;2&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_I2C0&gt;,</div><div class='ctx'> 				 &lt;&amp;topckgen CLK_TOP_APDMA&gt;;</div><div class='del'>-			clock-names = "main-source",</div><div class='del'>-				      "main-sel",</div><div class='del'>-				      "main",</div><div class='del'>-				      "dma";</div><div class='add'>+			clock-names = "main", "dma";</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='hunk'>@@ -322,14 +370,10 @@</div><div class='ctx'> 			reg = &lt;0 0x1100a000 0 0x90&gt;,</div><div class='ctx'> 			      &lt;0 0x11000200 0 0x80&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 81 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='del'>-			clocks = &lt;&amp;topckgen CLK_TOP_AHB_INFRA_D2&gt;,</div><div class='del'>-				 &lt;&amp;infracfg CLK_IFR_I2C1_SEL&gt;,</div><div class='del'>-				 &lt;&amp;topckgen CLK_TOP_I2C1&gt;,</div><div class='add'>+			clock-div = &lt;2&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_I2C1&gt;,</div><div class='ctx'> 				 &lt;&amp;topckgen CLK_TOP_APDMA&gt;;</div><div class='del'>-			clock-names = "main-source",</div><div class='del'>-				      "main-sel",</div><div class='del'>-				      "main",</div><div class='del'>-				      "dma";</div><div class='add'>+			clock-names = "main", "dma";</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='hunk'>@@ -341,14 +385,10 @@</div><div class='ctx'> 			reg = &lt;0 0x1100b000 0 0x90&gt;,</div><div class='ctx'> 			      &lt;0 0x11000280 0 0x80&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 82 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='del'>-			clocks = &lt;&amp;topckgen CLK_TOP_AHB_INFRA_D2&gt;,</div><div class='del'>-				 &lt;&amp;infracfg CLK_IFR_I2C2_SEL&gt;,</div><div class='del'>-				 &lt;&amp;topckgen CLK_TOP_I2C2&gt;,</div><div class='add'>+			clock-div = &lt;2&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_I2C2&gt;,</div><div class='ctx'> 				 &lt;&amp;topckgen CLK_TOP_APDMA&gt;;</div><div class='del'>-			clock-names = "main-source",</div><div class='del'>-				      "main-sel",</div><div class='del'>-				      "main",</div><div class='del'>-				      "dma";</div><div class='add'>+			clock-names = "main", "dma";</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='hunk'>@@ -401,6 +441,18 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		ethernet: ethernet@11180000 {</div><div class='add'>+			compatible = "mediatek,mt8516-eth";</div><div class='add'>+			reg = &lt;0 0x11180000 0 0x1000&gt;;</div><div class='add'>+			mediatek,pericfg = &lt;&amp;pericfg&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 111 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_RG_ETH&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_66M_ETH&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_133M_ETH&gt;;</div><div class='add'>+			clock-names = "core", "reg", "trans";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		rng: rng@1020c000 {</div><div class='ctx'> 			compatible = "mediatek,mt8516-rng",</div><div class='ctx'> 				     "mediatek,mt7623-rng";</div><div class='hunk'>@@ -426,7 +478,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		usb0: usb@11100000 {</div><div class='del'>-			compatible = "mediatek,mtk-musb";</div><div class='add'>+			compatible = "mediatek,mt8516-musb", "mediatek,mtk-musb";</div><div class='ctx'> 			reg = &lt;0 0x11100000 0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 72 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 			interrupt-names = "mc";</div><div class='hunk'>@@ -438,8 +490,23 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		usb0_phy: usb@11110000 {</div><div class='del'>-			compatible = "mediatek,generic-tphy-v1";</div><div class='add'>+		usb1: usb@11190000 {</div><div class='add'>+			compatible = "mediatek,mt8516-musb", "mediatek,mtk-musb";</div><div class='add'>+			reg = &lt;0 0x11190000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 210 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			interrupt-names = "mc";</div><div class='add'>+			phys = &lt;&amp;usb1_port PHY_TYPE_USB2&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_USB&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_USBIF&gt;,</div><div class='add'>+				 &lt;&amp;topckgen CLK_TOP_USB_1P&gt;;</div><div class='add'>+			clock-names = "main","mcu","univpll";</div><div class='add'>+			dr_mode = "host";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_phy: t-phy@11110000 {</div><div class='add'>+			compatible = "mediatek,mt8516-tphy",</div><div class='add'>+				     "mediatek,generic-tphy-v1";</div><div class='ctx'> 			reg = &lt;0 0x11110000 0 0x800&gt;;</div><div class='ctx'> 			#address-cells = &lt;2&gt;;</div><div class='ctx'> 			#size-cells = &lt;2&gt;;</div><div class='hunk'>@@ -452,6 +519,23 @@</div><div class='ctx'> 				clock-names = "ref";</div><div class='ctx'> 				#phy-cells = &lt;1&gt;;</div><div class='ctx'> 			};</div><div class='add'>+</div><div class='add'>+			usb1_port: usb-phy@11110900 {</div><div class='add'>+				reg = &lt;0 0x11110900 0 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;topckgen CLK_TOP_USB_PHY48M&gt;;</div><div class='add'>+				clock-names = "ref";</div><div class='add'>+				#phy-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		auxadc: adc@11003000 {</div><div class='add'>+			compatible = "mediatek,mt8516-auxadc",</div><div class='add'>+				     "mediatek,mt8173-auxadc";</div><div class='add'>+			reg = &lt;0 0x11003000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;topckgen CLK_TOP_AUX_ADC&gt;;</div><div class='add'>+			clock-names = "main";</div><div class='add'>+			#io-channel-cells = &lt;1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi<br/>index a31093d7142b..805fb82138a8 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi</a></div><div class='hunk'>@@ -9,6 +9,7 @@</div><div class='ctx'> / {</div><div class='ctx'> 	aliases {</div><div class='ctx'> 		serial0 = &amp;uart0;</div><div class='add'>+		ethernet0 = &amp;ethernet;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	chosen {</div><div class='hunk'>@@ -16,7 +17,7 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	firmware {</div><div class='del'>-		optee: optee@4fd00000 {</div><div class='add'>+		optee: optee {</div><div class='ctx'> 			compatible = "linaro,optee-tz";</div><div class='ctx'> 			method = "smc";</div><div class='ctx'> 		};</div><div class='hunk'>@@ -24,11 +25,10 @@</div><div class='ctx'> </div><div class='ctx'> 	gpio-keys {</div><div class='ctx'> 		compatible = "gpio-keys";</div><div class='del'>-		input-name = "gpio-keys";</div><div class='ctx'> 		pinctrl-names = "default";</div><div class='ctx'> 		pinctrl-0 = &lt;&amp;gpio_keys_default&gt;;</div><div class='ctx'> </div><div class='del'>-		volume-up {</div><div class='add'>+		key-volume-up {</div><div class='ctx'> 			gpios = &lt;&amp;pio 42 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 			label = "volume_up";</div><div class='ctx'> 			linux,code = &lt;115&gt;;</div><div class='hunk'>@@ -36,7 +36,7 @@</div><div class='ctx'> 			debounce-interval = &lt;15&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		volume-down {</div><div class='add'>+		key-volume-down {</div><div class='ctx'> 			gpios = &lt;&amp;pio 43 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 			label = "volume_down";</div><div class='ctx'> 			linux,code = &lt;114&gt;;</div><div class='hunk'>@@ -47,7 +47,6 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;i2c0 {</div><div class='del'>-	clock-div = &lt;2&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;i2c0_pins_a&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='hunk'>@@ -55,98 +54,98 @@</div><div class='ctx'> 	tca6416: gpio@20 {</div><div class='ctx'> 		compatible = "ti,tca6416";</div><div class='ctx'> 		reg = &lt;0x20&gt;;</div><div class='del'>-		rst-gpio = &lt;&amp;pio 65 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;pio 65 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 		pinctrl-names = "default";</div><div class='ctx'> 		pinctrl-0 = &lt;&amp;tca6416_pins&gt;;</div><div class='ctx'> </div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='del'>-		eint20_mux_sel0 {</div><div class='add'>+		eint20-mux-sel0-hog {</div><div class='ctx'> 			gpio-hog;</div><div class='ctx'> 			gpios = &lt;0 0&gt;;</div><div class='ctx'> 			input;</div><div class='ctx'> 			line-name = "eint20_mux_sel0";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		expcon_mux_sel1 {</div><div class='add'>+		expcon-mux-sel1-hog {</div><div class='ctx'> 			gpio-hog;</div><div class='ctx'> 			gpios = &lt;1 0&gt;;</div><div class='ctx'> 			input;</div><div class='ctx'> 			line-name = "expcon_mux_sel1";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		mrg_di_mux_sel2 {</div><div class='add'>+		mrg-di-mux-sel2-hog {</div><div class='ctx'> 			gpio-hog;</div><div class='ctx'> 			gpios = &lt;2 0&gt;;</div><div class='ctx'> 			input;</div><div class='ctx'> 			line-name = "mrg_di_mux_sel2";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		sd_sdio_mux_sel3 {</div><div class='add'>+		sd-sdio-mux-sel3-hog {</div><div class='ctx'> 			gpio-hog;</div><div class='ctx'> 			gpios = &lt;3 0&gt;;</div><div class='ctx'> 			input;</div><div class='ctx'> 			line-name = "sd_sdio_mux_sel3";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		sd_sdio_mux_ctrl7 {</div><div class='add'>+		sd-sdio-mux-ctrl7-hog {</div><div class='ctx'> 			gpio-hog;</div><div class='ctx'> 			gpios = &lt;7 0&gt;;</div><div class='ctx'> 			output-low;</div><div class='ctx'> 			line-name = "sd_sdio_mux_ctrl7";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		hw_id0 {</div><div class='add'>+		hw-id0-hog {</div><div class='ctx'> 			gpio-hog;</div><div class='ctx'> 			gpios = &lt;8 0&gt;;</div><div class='ctx'> 			input;</div><div class='ctx'> 			line-name = "hw_id0";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		hw_id1 {</div><div class='add'>+		hw-id1-hog {</div><div class='ctx'> 			gpio-hog;</div><div class='ctx'> 			gpios = &lt;9 0&gt;;</div><div class='ctx'> 			input;</div><div class='ctx'> 			line-name = "hw_id1";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		hw_id2 {</div><div class='add'>+		hw-id2-hog {</div><div class='ctx'> 			gpio-hog;</div><div class='ctx'> 			gpios = &lt;10 0&gt;;</div><div class='ctx'> 			input;</div><div class='ctx'> 			line-name = "hw_id2";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		fg_int_n {</div><div class='add'>+		fg-int-n-hog {</div><div class='ctx'> 			gpio-hog;</div><div class='ctx'> 			gpios = &lt;11 0&gt;;</div><div class='ctx'> 			input;</div><div class='ctx'> 			line-name = "fg_int_n";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		usba_pwr_en {</div><div class='add'>+		usba-pwr-en-hog {</div><div class='ctx'> 			gpio-hog;</div><div class='ctx'> 			gpios = &lt;12 0&gt;;</div><div class='ctx'> 			output-high;</div><div class='ctx'> 			line-name = "usba_pwr_en";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		wifi_3v3_pg {</div><div class='add'>+		wifi-3v3-pg-hog {</div><div class='ctx'> 			gpio-hog;</div><div class='ctx'> 			gpios = &lt;13 0&gt;;</div><div class='ctx'> 			input;</div><div class='ctx'> 			line-name = "wifi_3v3_pg";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		cam_rst {</div><div class='add'>+		cam-rst-hog {</div><div class='ctx'> 			gpio-hog;</div><div class='ctx'> 			gpios = &lt;14 0&gt;;</div><div class='ctx'> 			output-low;</div><div class='ctx'> 			line-name = "cam_rst";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		cam_pwdn {</div><div class='add'>+		cam-pwdn-hog {</div><div class='ctx'> 			gpio-hog;</div><div class='ctx'> 			gpios = &lt;15 0&gt;;</div><div class='ctx'> 			output-low;</div><div class='hunk'>@@ -156,7 +155,6 @@</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;i2c2 {</div><div class='del'>-	clock-div = &lt;2&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;i2c2_pins_a&gt;;</div><div class='ctx'> 	status = "okay";</div><div class='hunk'>@@ -166,9 +164,28 @@</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+&amp;ethernet {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;ethernet_pins_default&gt;;</div><div class='add'>+	phy-handle = &lt;&amp;eth_phy&gt;;</div><div class='add'>+	phy-mode = "rmii";</div><div class='add'>+	mac-address = [00 00 00 00 00 00];</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		eth_phy: ethernet-phy@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> &amp;usb0 {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> 	dr_mode = "peripheral";</div><div class='add'>+	usb-role-switch;</div><div class='ctx'> </div><div class='ctx'> 	usb_con: connector {</div><div class='ctx'> 		compatible = "usb-c-connector";</div><div class='hunk'>@@ -176,13 +193,13 @@</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;usb0_phy {</div><div class='add'>+&amp;usb_phy {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;pio {</div><div class='del'>-	gpio_keys_default: gpiodefault {</div><div class='del'>-		pins_cmd_dat {</div><div class='add'>+	gpio_keys_default: gpio-keys-pins {</div><div class='add'>+		pins-cmd-dat {</div><div class='ctx'> 			pinmux = &lt;MT8516_PIN_42_KPCOL0__FUNC_GPIO42&gt;,</div><div class='ctx'> 				 &lt;MT8516_PIN_43_KPCOL1__FUNC_GPIO43&gt;;</div><div class='ctx'> 			bias-pull-up;</div><div class='hunk'>@@ -190,7 +207,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	i2c0_pins_a: i2c0@0 {</div><div class='add'>+	i2c0_pins_a: i2c0-pins {</div><div class='ctx'> 		pins1 {</div><div class='ctx'> 			pinmux = &lt;MT8516_PIN_58_SDA0__FUNC_SDA0_0&gt;,</div><div class='ctx'> 				 &lt;MT8516_PIN_59_SCL0__FUNC_SCL0_0&gt;;</div><div class='hunk'>@@ -198,7 +215,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	i2c2_pins_a: i2c2@0 {</div><div class='add'>+	i2c2_pins_a: i2c2-pins {</div><div class='ctx'> 		pins1 {</div><div class='ctx'> 			pinmux = &lt;MT8516_PIN_60_SDA2__FUNC_SDA2_0&gt;,</div><div class='ctx'> 				 &lt;MT8516_PIN_61_SCL2__FUNC_SCL2_0&gt;;</div><div class='hunk'>@@ -206,16 +223,31 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	tca6416_pins: pinmux_tca6416_pins {</div><div class='del'>-		gpio_mux_rst_n_pin {</div><div class='add'>+	tca6416_pins: tca6416-pins {</div><div class='add'>+		pins-mux-rstn {</div><div class='ctx'> 			pinmux = &lt;MT8516_PIN_65_UTXD1__FUNC_GPIO65&gt;;</div><div class='ctx'> 			output-high;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		gpio_mux_int_n_pin {</div><div class='add'>+		pins-mux-intn {</div><div class='ctx'> 			pinmux = &lt;MT8516_PIN_64_URXD1__FUNC_GPIO64&gt;;</div><div class='ctx'> 			input-enable;</div><div class='ctx'> 			bias-pull-up;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	ethernet_pins_default: ethernet-pins {</div><div class='add'>+		pins-eth {</div><div class='add'>+			pinmux = &lt;MT8516_PIN_0_EINT0__FUNC_EXT_TXD0&gt;,</div><div class='add'>+				 &lt;MT8516_PIN_1_EINT1__FUNC_EXT_TXD1&gt;,</div><div class='add'>+				 &lt;MT8516_PIN_5_EINT5__FUNC_EXT_RXER&gt;,</div><div class='add'>+				 &lt;MT8516_PIN_6_EINT6__FUNC_EXT_RXC&gt;,</div><div class='add'>+				 &lt;MT8516_PIN_7_EINT7__FUNC_EXT_RXDV&gt;,</div><div class='add'>+				 &lt;MT8516_PIN_8_EINT8__FUNC_EXT_RXD0&gt;,</div><div class='add'>+				 &lt;MT8516_PIN_9_EINT9__FUNC_EXT_RXD1&gt;,</div><div class='add'>+				 &lt;MT8516_PIN_12_EINT12__FUNC_EXT_TXEN&gt;,</div><div class='add'>+				 &lt;MT8516_PIN_38_MRG_DI__FUNC_EXT_MDIO&gt;,</div><div class='add'>+				 &lt;MT8516_PIN_39_MRG_DO__FUNC_EXT_MDC&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/microchip/Makefile b/arch/arm64/boot/dts/microchip/Makefile<br/>new file mode 100644<br/>index 000000000000..c6e0313eea0f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/microchip/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/microchip/Makefile</a></div><div class='hunk'>@@ -0,0 +1,4 @@</div><div class='add'>+# SPDX-License-Identifier: GPL-2.0</div><div class='add'>+dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb125.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb134.dtb sparx5_pcb134_emmc.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb135.dtb sparx5_pcb135_emmc.dtb</div><div class='head'>diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi<br/>new file mode 100644<br/>index 000000000000..c3029e0abacc<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/microchip/sparx5.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/microchip/sparx5.dtsi</a></div><div class='hunk'>@@ -0,0 +1,484 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/microchip,sparx5.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "microchip,sparx5";</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		spi0 = &amp;spi0;</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+		serial1 = &amp;uart1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		cpu-map {</div><div class='add'>+			cluster0 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu0&gt;;</div><div class='add'>+				};</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu1&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='add'>+		};</div><div class='add'>+		cpu1: cpu@1 {</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x1&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='add'>+		};</div><div class='add'>+		L2_0: l2-cache0 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	arm-pmu {</div><div class='add'>+		compatible = "arm,cortex-a53-pmu";</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-affinity = &lt;&amp;cpu0&gt;, &lt;&amp;cpu1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci: psci {</div><div class='add'>+		compatible = "arm,psci-0.2";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lcpll_clk: lcpll-clk {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;2500000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clks: clock-controller@61110000c {</div><div class='add'>+		compatible = "microchip,sparx5-dpll";</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;lcpll_clk&gt;;</div><div class='add'>+		reg = &lt;0x6 0x1110000c 0x24&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ahb_clk: ahb-clk {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;250000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sys_clk: sys-clk {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;625000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	axi: axi@600000000 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@600300000 {</div><div class='add'>+			compatible = "arm,gic-v3";</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			reg = &lt;0x6 0x00300000 0x10000&gt;,	/* GIC Dist */</div><div class='add'>+			      &lt;0x6 0x00340000 0xc0000&gt;,	/* GICR */</div><div class='add'>+			      &lt;0x6 0x00200000 0x2000&gt;,	/* GICC */</div><div class='add'>+			      &lt;0x6 0x00210000 0x2000&gt;,  /* GICV */</div><div class='add'>+			      &lt;0x6 0x00220000 0x2000&gt;;  /* GICH */</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_ctrl: syscon@600000000 {</div><div class='add'>+			compatible = "microchip,sparx5-cpu-syscon", "syscon",</div><div class='add'>+				     "simple-mfd";</div><div class='add'>+			reg = &lt;0x6 0x00000000 0xd0&gt;;</div><div class='add'>+			mux: mux-controller {</div><div class='add'>+				compatible = "mmio-mux";</div><div class='add'>+				#mux-control-cells = &lt;0&gt;;</div><div class='add'>+				/*</div><div class='add'>+				 * SI_OWNER and SI2_OWNER in GENERAL_CTRL</div><div class='add'>+				 * SPI:  value 9 - (SIMC,SIBM) = 0b1001</div><div class='add'>+				 * SPI2: value 6 - (SIBM,SIMC) = 0b0110</div><div class='add'>+				 */</div><div class='add'>+				mux-reg-masks = &lt;0x88 0xf0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		reset: reset-controller@611010008 {</div><div class='add'>+			compatible = "microchip,sparx5-switch-reset";</div><div class='add'>+			reg = &lt;0x6 0x11010008 0x4&gt;;</div><div class='add'>+			reg-names = "gcb";</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+			cpu-syscon = &lt;&amp;cpu_ctrl&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart0: serial@600100000 {</div><div class='add'>+			pinctrl-0 = &lt;&amp;uart_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			compatible = "ns16550a";</div><div class='add'>+			reg = &lt;0x6 0x00100000 0x20&gt;;</div><div class='add'>+			clocks = &lt;&amp;ahb_clk&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+			reg-shift = &lt;2&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart1: serial@600102000 {</div><div class='add'>+			pinctrl-0 = &lt;&amp;uart2_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			compatible = "ns16550a";</div><div class='add'>+			reg = &lt;0x6 0x00102000 0x20&gt;;</div><div class='add'>+			clocks = &lt;&amp;ahb_clk&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+			reg-shift = &lt;2&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi0: spi@600104000 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			compatible = "microchip,sparx5-spi";</div><div class='add'>+			reg = &lt;0x6 0x00104000 0x40&gt;;</div><div class='add'>+			num-cs = &lt;16&gt;;</div><div class='add'>+			reg-io-width = &lt;4&gt;;</div><div class='add'>+			reg-shift = &lt;2&gt;;</div><div class='add'>+			clocks = &lt;&amp;ahb_clk&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		timer1: timer@600105000 {</div><div class='add'>+			compatible = "snps,dw-apb-timer";</div><div class='add'>+			reg = &lt;0x6 0x00105000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;ahb_clk&gt;;</div><div class='add'>+			clock-names = "timer";</div><div class='add'>+			interrupts = &lt;GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sdhci0: mmc@600800000 {</div><div class='add'>+			compatible = "microchip,dw-sparx5-sdhci";</div><div class='add'>+			status = "disabled";</div><div class='add'>+			reg = &lt;0x6 0x00800000 0x1000&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;emmc_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			clocks = &lt;&amp;clks CLK_ID_AUX1&gt;;</div><div class='add'>+			clock-names = "core";</div><div class='add'>+			assigned-clocks = &lt;&amp;clks CLK_ID_AUX1&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;800000000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			bus-width = &lt;8&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpio: pinctrl@6110101e0 {</div><div class='add'>+			compatible = "microchip,sparx5-pinctrl";</div><div class='add'>+			reg = &lt;0x6 0x110101e0 0x90&gt;, &lt;0x6 0x10508010 0x100&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;gpio 0 0 64&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			interrupts = &lt;GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			cs1_pins: cs1-pins {</div><div class='add'>+				pins = "GPIO_16";</div><div class='add'>+				function = "si";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cs2_pins: cs2-pins {</div><div class='add'>+				pins = "GPIO_17";</div><div class='add'>+				function = "si";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cs3_pins: cs3-pins {</div><div class='add'>+				pins = "GPIO_18";</div><div class='add'>+				function = "si";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			si2_pins: si2-pins {</div><div class='add'>+				pins = "GPIO_39", "GPIO_40", "GPIO_41";</div><div class='add'>+				function = "si2";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sgpio0_pins: sgpio-pins {</div><div class='add'>+				pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";</div><div class='add'>+				function = "sg0";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sgpio1_pins: sgpio1-pins {</div><div class='add'>+				pins = "GPIO_4", "GPIO_5", "GPIO_12", "GPIO_13";</div><div class='add'>+				function = "sg1";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sgpio2_pins: sgpio2-pins {</div><div class='add'>+				pins = "GPIO_30", "GPIO_31", "GPIO_32",</div><div class='add'>+				       "GPIO_33";</div><div class='add'>+				function = "sg2";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart_pins: uart-pins {</div><div class='add'>+				pins = "GPIO_10", "GPIO_11";</div><div class='add'>+				function = "uart";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart2_pins: uart2-pins {</div><div class='add'>+				pins = "GPIO_26", "GPIO_27";</div><div class='add'>+				function = "uart2";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c_pins: i2c-pins {</div><div class='add'>+				pins = "GPIO_14", "GPIO_15";</div><div class='add'>+				function = "twi";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c2_pins: i2c2-pins {</div><div class='add'>+				pins = "GPIO_28", "GPIO_29";</div><div class='add'>+				function = "twi2";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			emmc_pins: emmc-pins {</div><div class='add'>+				pins = "GPIO_34", "GPIO_35", "GPIO_36",</div><div class='add'>+					"GPIO_37", "GPIO_38", "GPIO_39",</div><div class='add'>+					"GPIO_40", "GPIO_41", "GPIO_42",</div><div class='add'>+					"GPIO_43", "GPIO_44", "GPIO_45",</div><div class='add'>+					"GPIO_46", "GPIO_47";</div><div class='add'>+				function = "emmc";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			miim1_pins: miim1-pins {</div><div class='add'>+				pins = "GPIO_56", "GPIO_57";</div><div class='add'>+				function = "miim";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			miim2_pins: miim2-pins {</div><div class='add'>+				pins = "GPIO_58", "GPIO_59";</div><div class='add'>+				function = "miim";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			miim3_pins: miim3-pins {</div><div class='add'>+				pins = "GPIO_52", "GPIO_53";</div><div class='add'>+				function = "miim";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sgpio0: gpio@61101036c {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			compatible = "microchip,sparx5-sgpio";</div><div class='add'>+			status = "disabled";</div><div class='add'>+			clocks = &lt;&amp;sys_clk&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;sgpio0_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			resets = &lt;&amp;reset 0&gt;;</div><div class='add'>+			reset-names = "switch";</div><div class='add'>+			reg = &lt;0x6 0x1101036c 0x100&gt;;</div><div class='add'>+			sgpio_in0: gpio@0 {</div><div class='add'>+				compatible = "microchip,sparx5-sgpio-bank";</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+				#gpio-cells = &lt;3&gt;;</div><div class='add'>+				ngpios = &lt;96&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			};</div><div class='add'>+			sgpio_out0: gpio@1 {</div><div class='add'>+				compatible = "microchip,sparx5-sgpio-bank";</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+				#gpio-cells = &lt;3&gt;;</div><div class='add'>+				ngpios = &lt;96&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sgpio1: gpio@611010484 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			compatible = "microchip,sparx5-sgpio";</div><div class='add'>+			status = "disabled";</div><div class='add'>+			clocks = &lt;&amp;sys_clk&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;sgpio1_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			resets = &lt;&amp;reset 0&gt;;</div><div class='add'>+			reset-names = "switch";</div><div class='add'>+			reg = &lt;0x6 0x11010484 0x100&gt;;</div><div class='add'>+			sgpio_in1: gpio@0 {</div><div class='add'>+				compatible = "microchip,sparx5-sgpio-bank";</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+				#gpio-cells = &lt;3&gt;;</div><div class='add'>+				ngpios = &lt;96&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			};</div><div class='add'>+			sgpio_out1: gpio@1 {</div><div class='add'>+				compatible = "microchip,sparx5-sgpio-bank";</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+				#gpio-cells = &lt;3&gt;;</div><div class='add'>+				ngpios = &lt;96&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sgpio2: gpio@61101059c {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			compatible = "microchip,sparx5-sgpio";</div><div class='add'>+			status = "disabled";</div><div class='add'>+			clocks = &lt;&amp;sys_clk&gt;;</div><div class='add'>+			pinctrl-0 = &lt;&amp;sgpio2_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			resets = &lt;&amp;reset 0&gt;;</div><div class='add'>+			reset-names = "switch";</div><div class='add'>+			reg = &lt;0x6 0x1101059c 0x100&gt;;</div><div class='add'>+			sgpio_in2: gpio@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				compatible = "microchip,sparx5-sgpio-bank";</div><div class='add'>+				gpio-controller;</div><div class='add'>+				#gpio-cells = &lt;3&gt;;</div><div class='add'>+				ngpios = &lt;96&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			};</div><div class='add'>+			sgpio_out2: gpio@1 {</div><div class='add'>+				compatible = "microchip,sparx5-sgpio-bank";</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+				#gpio-cells = &lt;3&gt;;</div><div class='add'>+				ngpios = &lt;96&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c0: i2c@600101000 {</div><div class='add'>+			compatible = "snps,designware-i2c";</div><div class='add'>+			status = "disabled";</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			reg = &lt;0x6 0x00101000 0x100&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			i2c-sda-hold-time-ns = &lt;300&gt;;</div><div class='add'>+			clock-frequency = &lt;100000&gt;;</div><div class='add'>+			clocks = &lt;&amp;ahb_clk&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c1: i2c@600103000 {</div><div class='add'>+			compatible = "snps,designware-i2c";</div><div class='add'>+			status = "disabled";</div><div class='add'>+			pinctrl-0 = &lt;&amp;i2c2_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			reg = &lt;0x6 0x00103000 0x100&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			i2c-sda-hold-time-ns = &lt;300&gt;;</div><div class='add'>+			clock-frequency = &lt;100000&gt;;</div><div class='add'>+			clocks = &lt;&amp;ahb_clk&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tmon0: tmon@610508110 {</div><div class='add'>+			compatible = "microchip,sparx5-temp";</div><div class='add'>+			reg = &lt;0x6 0x10508110 0xc&gt;;</div><div class='add'>+			#thermal-sensor-cells = &lt;0&gt;;</div><div class='add'>+			clocks = &lt;&amp;ahb_clk&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio0: mdio@6110102b0 {</div><div class='add'>+			compatible = "mscc,ocelot-miim";</div><div class='add'>+			status = "disabled";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0x6 0x110102b0 0x24&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio1: mdio@6110102d4 {</div><div class='add'>+			compatible = "mscc,ocelot-miim";</div><div class='add'>+			status = "disabled";</div><div class='add'>+			pinctrl-0 = &lt;&amp;miim1_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0x6 0x110102d4 0x24&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio2: mdio@6110102f8 {</div><div class='add'>+			compatible = "mscc,ocelot-miim";</div><div class='add'>+			status = "disabled";</div><div class='add'>+			pinctrl-0 = &lt;&amp;miim2_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0x6 0x110102f8 0x24&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio3: mdio@61101031c {</div><div class='add'>+			compatible = "mscc,ocelot-miim";</div><div class='add'>+			status = "disabled";</div><div class='add'>+			pinctrl-0 = &lt;&amp;miim3_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0x6 0x1101031c 0x24&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		serdes: serdes@610808000 {</div><div class='add'>+			compatible = "microchip,sparx5-serdes";</div><div class='add'>+			#phy-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;sys_clk&gt;;</div><div class='add'>+			reg = &lt;0x6 0x10808000 0x5d0000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		switch: switch@600000000 {</div><div class='add'>+			compatible = "microchip,sparx5-switch";</div><div class='add'>+			reg = &lt;0x6 0 0x401000&gt;,</div><div class='add'>+			      &lt;0x6 0x10004000 0x7fc000&gt;,</div><div class='add'>+			      &lt;0x6 0x11010000 0xaf0000&gt;;</div><div class='add'>+			reg-names = "cpu", "dev", "gcb";</div><div class='add'>+			interrupt-names = "xtr", "fdma", "ptp";</div><div class='add'>+			interrupts = &lt;GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			resets = &lt;&amp;reset 0&gt;;</div><div class='add'>+			reset-names = "switch";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/microchip/sparx5_nand.dtsi b/arch/arm64/boot/dts/microchip/sparx5_nand.dtsi<br/>new file mode 100644<br/>index 000000000000..ce0747fd6444<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/microchip/sparx5_nand.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/microchip/sparx5_nand.dtsi</a></div><div class='hunk'>@@ -0,0 +1,31 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;gpio {</div><div class='add'>+	cs14_pins: cs14-pins {</div><div class='add'>+		pins = "GPIO_44";</div><div class='add'>+		function = "si";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi0 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;si2_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	spi@e {</div><div class='add'>+		compatible = "spi-mux";</div><div class='add'>+		mux-controls = &lt;&amp;mux&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		reg = &lt;14&gt;; /* CS14 */</div><div class='add'>+		flash@6 {</div><div class='add'>+			compatible = "spi-nand";</div><div class='add'>+			pinctrl-0 = &lt;&amp;cs14_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			reg = &lt;0x6&gt;; /* SPI2 */</div><div class='add'>+			spi-max-frequency = &lt;42000000&gt;;</div><div class='add'>+			rx-sample-delay-ns = &lt;7&gt;;  /* Tune for speed */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts<br/>new file mode 100644<br/>index 000000000000..dbf8c1d48a02<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/microchip/sparx5_pcb125.dts</a></div><div class='hunk'>@@ -0,0 +1,79 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "sparx5_pcb_common.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Sparx5 PCB125 Reference Board";</div><div class='add'>+	compatible = "microchip,sparx5-pcb125", "microchip,sparx5";</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x00000000 0x00000000 0x10000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio {</div><div class='add'>+	emmc_pins: emmc-pins {</div><div class='add'>+		/* NB: No "GPIO_35", "GPIO_36", "GPIO_37"</div><div class='add'>+		 * (N/A: CARD_nDETECT, CARD_WP, CARD_LED)</div><div class='add'>+		 */</div><div class='add'>+		pins = "GPIO_34", "GPIO_38", "GPIO_39",</div><div class='add'>+			"GPIO_40", "GPIO_41", "GPIO_42",</div><div class='add'>+			"GPIO_43", "GPIO_44", "GPIO_45",</div><div class='add'>+			"GPIO_46", "GPIO_47";</div><div class='add'>+		drive-strength = &lt;3&gt;;</div><div class='add'>+		function = "emmc";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sdhci0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	pinctrl-0 = &lt;&amp;emmc_pins&gt;;</div><div class='add'>+	max-frequency = &lt;8000000&gt;;</div><div class='add'>+	microchip,clock-delay = &lt;10&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	spi@0 {</div><div class='add'>+		compatible = "spi-mux";</div><div class='add'>+		mux-controls = &lt;&amp;mux&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		reg = &lt;0&gt;;	/* CS0 */</div><div class='add'>+		flash@9 {</div><div class='add'>+			compatible = "jedec,spi-nor";</div><div class='add'>+			spi-max-frequency = &lt;8000000&gt;;</div><div class='add'>+			reg = &lt;0x9&gt;;	/* SPI */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+	spi@1 {</div><div class='add'>+		compatible = "spi-mux";</div><div class='add'>+		mux-controls = &lt;&amp;mux 0&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		reg = &lt;1&gt;; /* CS1 */</div><div class='add'>+		flash@9 {</div><div class='add'>+			compatible = "spi-nand";</div><div class='add'>+			pinctrl-0 = &lt;&amp;cs1_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			spi-max-frequency = &lt;8000000&gt;;</div><div class='add'>+			reg = &lt;0x9&gt;;	/* SPI */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sgpio0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	microchip,sgpio-port-ranges = &lt;0 23&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts<br/>new file mode 100644<br/>index 000000000000..45ca1af7e850<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/microchip/sparx5_pcb134.dts</a></div><div class='hunk'>@@ -0,0 +1,18 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "sparx5_pcb134_board.dtsi"</div><div class='add'>+#include "sparx5_nand.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Sparx5 PCB134 Reference Board (NAND)";</div><div class='add'>+	compatible = "microchip,sparx5-pcb134", "microchip,sparx5";</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x00000000 0x00000000 0x10000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi<br/>new file mode 100644<br/>index 000000000000..e60acc74e822<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi</a></div><div class='hunk'>@@ -0,0 +1,914 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "sparx5_pcb_common.dtsi"</div><div class='add'>+</div><div class='add'>+/{</div><div class='add'>+	gpio-restart {</div><div class='add'>+		compatible = "gpio-restart";</div><div class='add'>+		gpios = &lt;&amp;gpio 37 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		priority = &lt;200&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c0_imux: i2c-mux-0 {</div><div class='add'>+		compatible = "i2c-mux-pinctrl";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		i2c-parent = &lt;&amp;i2c0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c0_emux: i2c-mux-1 {</div><div class='add'>+		compatible = "i2c-mux-gpio";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		i2c-parent = &lt;&amp;i2c0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		led-0 {</div><div class='add'>+			label = "twr0:green";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out0 8 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+		led-1 {</div><div class='add'>+			label = "twr0:yellow";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out0 8 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+		led-2 {</div><div class='add'>+			label = "twr1:green";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out0 9 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+		led-3 {</div><div class='add'>+			label = "twr1:yellow";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out0 9 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+		led-4 {</div><div class='add'>+			label = "twr2:green";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out0 10 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+		led-5 {</div><div class='add'>+			label = "twr2:yellow";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out0 10 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+		led-6 {</div><div class='add'>+			label = "twr3:green";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out0 11 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+		led-7 {</div><div class='add'>+			label = "twr3:yellow";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out0 11 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+		led-8 {</div><div class='add'>+			label = "eth12:green";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out0 12 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+		led-9 {</div><div class='add'>+			label = "eth12:yellow";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out0 12 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+		led-10 {</div><div class='add'>+			label = "eth13:green";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out0 13 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+		led-11 {</div><div class='add'>+			label = "eth13:yellow";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out0 13 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+		led-12 {</div><div class='add'>+			label = "eth14:green";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out0 14 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+		led-13 {</div><div class='add'>+			label = "eth14:yellow";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out0 14 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+		led-14 {</div><div class='add'>+			label = "eth15:green";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out0 15 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+		led-15 {</div><div class='add'>+			label = "eth15:yellow";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out0 15 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+		led-16 {</div><div class='add'>+			label = "eth48:green";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out1 16 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+		led-17 {</div><div class='add'>+			label = "eth48:yellow";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out1 16 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+		led-18 {</div><div class='add'>+			label = "eth49:green";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out1 17 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+		led-19 {</div><div class='add'>+			label = "eth49:yellow";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out1 17 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+		led-20 {</div><div class='add'>+			label = "eth50:green";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out1 18 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+		led-21 {</div><div class='add'>+			label = "eth50:yellow";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out1 18 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+		led-22 {</div><div class='add'>+			label = "eth51:green";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out1 19 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+		led-23 {</div><div class='add'>+			label = "eth51:yellow";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out1 19 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+		led-24 {</div><div class='add'>+			label = "eth52:green";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out1 20 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+		led-25 {</div><div class='add'>+			label = "eth52:yellow";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out1 20 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+		led-26 {</div><div class='add'>+			label = "eth53:green";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out1 21 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+		led-27 {</div><div class='add'>+			label = "eth53:yellow";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out1 21 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+		led-28 {</div><div class='add'>+			label = "eth54:green";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out1 22 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+		led-29 {</div><div class='add'>+			label = "eth54:yellow";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out1 22 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+		led-30 {</div><div class='add'>+			label = "eth55:green";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out1 23 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+		led-31 {</div><div class='add'>+			label = "eth55:yellow";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out1 23 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+		led-32 {</div><div class='add'>+			label = "eth56:green";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out1 24 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+		led-33 {</div><div class='add'>+			label = "eth56:yellow";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out1 24 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+		led-34 {</div><div class='add'>+			label = "eth57:green";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out1 25 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+		led-35 {</div><div class='add'>+			label = "eth57:yellow";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out1 25 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+		led-36 {</div><div class='add'>+			label = "eth58:green";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out1 26 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+		led-37 {</div><div class='add'>+			label = "eth58:yellow";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out1 26 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+		led-38 {</div><div class='add'>+			label = "eth59:green";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out1 27 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+		led-39 {</div><div class='add'>+			label = "eth59:yellow";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out1 27 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+		led-40 {</div><div class='add'>+			label = "eth60:green";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out1 28 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+		led-41 {</div><div class='add'>+			label = "eth60:yellow";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out1 28 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+		led-42 {</div><div class='add'>+			label = "eth61:green";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out1 29 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+		led-43 {</div><div class='add'>+			label = "eth61:yellow";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out1 29 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+		led-44 {</div><div class='add'>+			label = "eth62:green";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out1 30 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+		led-45 {</div><div class='add'>+			label = "eth62:yellow";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out1 30 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+		led-46 {</div><div class='add'>+			label = "eth63:green";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out1 31 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+		led-47 {</div><div class='add'>+			label = "eth63:yellow";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out1 31 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp_eth12: sfp-eth12 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;i2c_sfp1&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;sgpio_out2 11 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;sgpio_in2 11 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;sgpio_in2 11 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;sgpio_in2 12 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp_eth13: sfp-eth13 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;i2c_sfp2&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;sgpio_out2 12 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;sgpio_in2 12 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;sgpio_in2 12 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;sgpio_in2 13 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp_eth14: sfp-eth14 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;i2c_sfp3&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;sgpio_out2 13 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;sgpio_in2 13 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;sgpio_in2 13 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;sgpio_in2 14 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp_eth15: sfp-eth15 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;i2c_sfp4&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;sgpio_out2 14 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;sgpio_in2 14 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;sgpio_in2 14 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;sgpio_in2 15 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp_eth48: sfp-eth48 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;i2c_sfp5&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;sgpio_out2 15 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;sgpio_in2 15 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;sgpio_in2 15 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;sgpio_in2 16 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp_eth49: sfp-eth49 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;i2c_sfp6&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;sgpio_out2 16 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;sgpio_in2 16 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;sgpio_in2 16 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;sgpio_in2 17 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp_eth50: sfp-eth50 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;i2c_sfp7&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;sgpio_out2 17 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;sgpio_in2 17 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;sgpio_in2 17 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;sgpio_in2 18 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp_eth51: sfp-eth51 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;i2c_sfp8&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;sgpio_out2 18 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;sgpio_in2 18 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;sgpio_in2 18 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;sgpio_in2 19 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp_eth52: sfp-eth52 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;i2c_sfp9&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;sgpio_out2 19 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;sgpio_in2 19 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;sgpio_in2 19 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;sgpio_in2 20 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp_eth53: sfp-eth53 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;i2c_sfp10&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;sgpio_out2 20 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;sgpio_in2 20 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;sgpio_in2 20 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;sgpio_in2 21 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp_eth54: sfp-eth54 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;i2c_sfp11&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;sgpio_out2 21 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;sgpio_in2 21 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;sgpio_in2 21 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;sgpio_in2 22 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp_eth55: sfp-eth55 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;i2c_sfp12&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;sgpio_out2 22 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;sgpio_in2 22 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;sgpio_in2 22 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;sgpio_in2 23 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp_eth56: sfp-eth56 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;i2c_sfp13&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;sgpio_out2 23 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;sgpio_in2 23 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;sgpio_in2 23 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;sgpio_in2 24 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp_eth57: sfp-eth57 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;i2c_sfp14&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;sgpio_out2 24 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;sgpio_in2 24 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;sgpio_in2 24 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;sgpio_in2 25 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp_eth58: sfp-eth58 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;i2c_sfp15&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;sgpio_out2 25 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;sgpio_in2 25 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;sgpio_in2 25 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;sgpio_in2 26 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp_eth59: sfp-eth59 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;i2c_sfp16&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;sgpio_out2 26 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;sgpio_in2 26 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;sgpio_in2 26 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;sgpio_in2 27 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp_eth60: sfp-eth60 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;i2c_sfp17&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;sgpio_out2 27 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;sgpio_in2 27 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;sgpio_in2 27 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;sgpio_in2 28 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp_eth61: sfp-eth61 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;i2c_sfp18&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;sgpio_out2 28 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;sgpio_in2 28 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;sgpio_in2 28 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;sgpio_in2 29 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp_eth62: sfp-eth62 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;i2c_sfp19&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;sgpio_out2 29 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;sgpio_in2 29 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;sgpio_in2 29 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;sgpio_in2 30 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp_eth63: sfp-eth63 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;i2c_sfp20&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;sgpio_out2 30 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;sgpio_in2 30 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;sgpio_in2 30 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;sgpio_in2 31 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sgpio0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	microchip,sgpio-port-ranges = &lt;8 15&gt;;</div><div class='add'>+	gpio@0 {</div><div class='add'>+		ngpios = &lt;64&gt;;</div><div class='add'>+	};</div><div class='add'>+	gpio@1 {</div><div class='add'>+		ngpios = &lt;64&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sgpio1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	microchip,sgpio-port-ranges = &lt;24 31&gt;;</div><div class='add'>+	gpio@0 {</div><div class='add'>+		ngpios = &lt;64&gt;;</div><div class='add'>+	};</div><div class='add'>+	gpio@1 {</div><div class='add'>+		ngpios = &lt;64&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	spi@0 {</div><div class='add'>+		compatible = "spi-mux";</div><div class='add'>+		mux-controls = &lt;&amp;mux&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		reg = &lt;0&gt;;	/* CS0 */</div><div class='add'>+		flash@9 {</div><div class='add'>+			compatible = "jedec,spi-nor";</div><div class='add'>+			spi-max-frequency = &lt;8000000&gt;;</div><div class='add'>+			reg = &lt;0x9&gt;;	/* SPI */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sgpio0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	microchip,sgpio-port-ranges = &lt;8 15&gt;;</div><div class='add'>+	gpio@0 {</div><div class='add'>+		ngpios = &lt;64&gt;;</div><div class='add'>+	};</div><div class='add'>+	gpio@1 {</div><div class='add'>+		ngpios = &lt;64&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sgpio1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	microchip,sgpio-port-ranges = &lt;24 31&gt;;</div><div class='add'>+	gpio@0 {</div><div class='add'>+		ngpios = &lt;64&gt;;</div><div class='add'>+	};</div><div class='add'>+	gpio@1 {</div><div class='add'>+		ngpios = &lt;64&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sgpio2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	microchip,sgpio-port-ranges = &lt;0 0&gt;, &lt;11 31&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio {</div><div class='add'>+	i2cmux_pins_i: i2cmux-pins {</div><div class='add'>+	       pins = "GPIO_16", "GPIO_17", "GPIO_18", "GPIO_19",</div><div class='add'>+		      "GPIO_20", "GPIO_22", "GPIO_36", "GPIO_35",</div><div class='add'>+		      "GPIO_50", "GPIO_51", "GPIO_56", "GPIO_57";</div><div class='add'>+		function = "twi_scl_m";</div><div class='add'>+		output-low;</div><div class='add'>+	};</div><div class='add'>+	i2cmux_0: i2cmux-0-pins {</div><div class='add'>+		pins = "GPIO_16";</div><div class='add'>+		function = "twi_scl_m";</div><div class='add'>+		output-high;</div><div class='add'>+	};</div><div class='add'>+	i2cmux_1: i2cmux-1-pins {</div><div class='add'>+		pins = "GPIO_17";</div><div class='add'>+		function = "twi_scl_m";</div><div class='add'>+		output-high;</div><div class='add'>+	};</div><div class='add'>+	i2cmux_2: i2cmux-2-pins {</div><div class='add'>+		pins = "GPIO_18";</div><div class='add'>+		function = "twi_scl_m";</div><div class='add'>+		output-high;</div><div class='add'>+	};</div><div class='add'>+	i2cmux_3: i2cmux-3-pins {</div><div class='add'>+		pins = "GPIO_19";</div><div class='add'>+		function = "twi_scl_m";</div><div class='add'>+		output-high;</div><div class='add'>+	};</div><div class='add'>+	i2cmux_4: i2cmux-4-pins {</div><div class='add'>+		pins = "GPIO_20";</div><div class='add'>+		function = "twi_scl_m";</div><div class='add'>+		output-high;</div><div class='add'>+	};</div><div class='add'>+	i2cmux_5: i2cmux-5-pins {</div><div class='add'>+		pins = "GPIO_22";</div><div class='add'>+		function = "twi_scl_m";</div><div class='add'>+		output-high;</div><div class='add'>+	};</div><div class='add'>+	i2cmux_6: i2cmux-6-pins {</div><div class='add'>+		pins = "GPIO_36";</div><div class='add'>+		function = "twi_scl_m";</div><div class='add'>+		output-high;</div><div class='add'>+	};</div><div class='add'>+	i2cmux_7: i2cmux-7-pins {</div><div class='add'>+		pins = "GPIO_35";</div><div class='add'>+		function = "twi_scl_m";</div><div class='add'>+		output-high;</div><div class='add'>+	};</div><div class='add'>+	i2cmux_8: i2cmux-8-pins {</div><div class='add'>+		pins = "GPIO_50";</div><div class='add'>+		function = "twi_scl_m";</div><div class='add'>+		output-high;</div><div class='add'>+	};</div><div class='add'>+	i2cmux_9: i2cmux-9-pins {</div><div class='add'>+		pins = "GPIO_51";</div><div class='add'>+		function = "twi_scl_m";</div><div class='add'>+		output-high;</div><div class='add'>+	};</div><div class='add'>+	i2cmux_10: i2cmux-10-pins {</div><div class='add'>+		pins = "GPIO_56";</div><div class='add'>+		function = "twi_scl_m";</div><div class='add'>+		output-high;</div><div class='add'>+	};</div><div class='add'>+	i2cmux_11: i2cmux-11-pins {</div><div class='add'>+		pins = "GPIO_57";</div><div class='add'>+		function = "twi_scl_m";</div><div class='add'>+		output-high;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0_imux {</div><div class='add'>+	pinctrl-names =</div><div class='add'>+		"i2c_sfp1", "i2c_sfp2", "i2c_sfp3", "i2c_sfp4",</div><div class='add'>+		"i2c_sfp5", "i2c_sfp6", "i2c_sfp7", "i2c_sfp8",</div><div class='add'>+		"i2c_sfp9", "i2c_sfp10", "i2c_sfp11", "i2c_sfp12", "idle";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2cmux_0&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;i2cmux_1&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;i2cmux_2&gt;;</div><div class='add'>+	pinctrl-3 = &lt;&amp;i2cmux_3&gt;;</div><div class='add'>+	pinctrl-4 = &lt;&amp;i2cmux_4&gt;;</div><div class='add'>+	pinctrl-5 = &lt;&amp;i2cmux_5&gt;;</div><div class='add'>+	pinctrl-6 = &lt;&amp;i2cmux_6&gt;;</div><div class='add'>+	pinctrl-7 = &lt;&amp;i2cmux_7&gt;;</div><div class='add'>+	pinctrl-8 = &lt;&amp;i2cmux_8&gt;;</div><div class='add'>+	pinctrl-9 = &lt;&amp;i2cmux_9&gt;;</div><div class='add'>+	pinctrl-10 = &lt;&amp;i2cmux_10&gt;;</div><div class='add'>+	pinctrl-11 = &lt;&amp;i2cmux_11&gt;;</div><div class='add'>+	pinctrl-12 = &lt;&amp;i2cmux_pins_i&gt;;</div><div class='add'>+	i2c_sfp1: i2c@0 {</div><div class='add'>+		reg = &lt;0x0&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+	i2c_sfp2: i2c@1 {</div><div class='add'>+		reg = &lt;0x1&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+	i2c_sfp3: i2c@2 {</div><div class='add'>+		reg = &lt;0x2&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+	i2c_sfp4: i2c@3 {</div><div class='add'>+		reg = &lt;0x3&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+	i2c_sfp5: i2c@4 {</div><div class='add'>+		reg = &lt;0x4&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+	i2c_sfp6: i2c@5 {</div><div class='add'>+		reg = &lt;0x5&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+	i2c_sfp7: i2c@6 {</div><div class='add'>+		reg = &lt;0x6&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+	i2c_sfp8: i2c@7 {</div><div class='add'>+		reg = &lt;0x7&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+	i2c_sfp9: i2c@8 {</div><div class='add'>+		reg = &lt;0x8&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+	i2c_sfp10: i2c@9 {</div><div class='add'>+		reg = &lt;0x9&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+	i2c_sfp11: i2c@a {</div><div class='add'>+		reg = &lt;0xa&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+	i2c_sfp12: i2c@b {</div><div class='add'>+		reg = &lt;0xb&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0_emux {</div><div class='add'>+	mux-gpios = &lt;&amp;gpio 55 GPIO_ACTIVE_HIGH</div><div class='add'>+		     &amp;gpio 60 GPIO_ACTIVE_HIGH</div><div class='add'>+		     &amp;gpio 61 GPIO_ACTIVE_HIGH</div><div class='add'>+		     &amp;gpio 54 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	idle-state = &lt;0x8&gt;;</div><div class='add'>+	i2c_sfp13: i2c@0 {</div><div class='add'>+		reg = &lt;0x0&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+	i2c_sfp14: i2c@1 {</div><div class='add'>+		reg = &lt;0x1&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+	i2c_sfp15: i2c@2 {</div><div class='add'>+		reg = &lt;0x2&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+	i2c_sfp16: i2c@3 {</div><div class='add'>+		reg = &lt;0x3&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+	i2c_sfp17: i2c@4 {</div><div class='add'>+		reg = &lt;0x4&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+	i2c_sfp18: i2c@5 {</div><div class='add'>+		reg = &lt;0x5&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+	i2c_sfp19: i2c@6 {</div><div class='add'>+		reg = &lt;0x6&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+	i2c_sfp20: i2c@7 {</div><div class='add'>+		reg = &lt;0x7&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdio3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	phy64: ethernet-phy@64 {</div><div class='add'>+		reg = &lt;28&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;switch {</div><div class='add'>+	ethernet-ports {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		/* 10G SFPs */</div><div class='add'>+		port12: port@12 {</div><div class='add'>+			reg = &lt;12&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;10000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 13&gt;;</div><div class='add'>+			phy-mode = "10gbase-r";</div><div class='add'>+			sfp = &lt;&amp;sfp_eth12&gt;;</div><div class='add'>+			microchip,sd-sgpio = &lt;301&gt;;</div><div class='add'>+			managed = "in-band-status";</div><div class='add'>+		};</div><div class='add'>+		port13: port@13 {</div><div class='add'>+			reg = &lt;13&gt;;</div><div class='add'>+			/* Example: CU SFP, 1G speed */</div><div class='add'>+			microchip,bandwidth = &lt;10000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 14&gt;;</div><div class='add'>+			phy-mode = "10gbase-r";</div><div class='add'>+			sfp = &lt;&amp;sfp_eth13&gt;;</div><div class='add'>+			microchip,sd-sgpio = &lt;305&gt;;</div><div class='add'>+			managed = "in-band-status";</div><div class='add'>+		};</div><div class='add'>+		port14: port@14 {</div><div class='add'>+			reg = &lt;14&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;10000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 15&gt;;</div><div class='add'>+			phy-mode = "10gbase-r";</div><div class='add'>+			sfp = &lt;&amp;sfp_eth14&gt;;</div><div class='add'>+			microchip,sd-sgpio = &lt;309&gt;;</div><div class='add'>+			managed = "in-band-status";</div><div class='add'>+		};</div><div class='add'>+		port15: port@15 {</div><div class='add'>+			reg = &lt;15&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;10000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 16&gt;;</div><div class='add'>+			phy-mode = "10gbase-r";</div><div class='add'>+			sfp = &lt;&amp;sfp_eth15&gt;;</div><div class='add'>+			microchip,sd-sgpio = &lt;313&gt;;</div><div class='add'>+			managed = "in-band-status";</div><div class='add'>+		};</div><div class='add'>+		port48: port@48 {</div><div class='add'>+			reg = &lt;48&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;10000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 17&gt;;</div><div class='add'>+			phy-mode = "10gbase-r";</div><div class='add'>+			sfp = &lt;&amp;sfp_eth48&gt;;</div><div class='add'>+			microchip,sd-sgpio = &lt;317&gt;;</div><div class='add'>+			managed = "in-band-status";</div><div class='add'>+		};</div><div class='add'>+		port49: port@49 {</div><div class='add'>+			reg = &lt;49&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;10000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 18&gt;;</div><div class='add'>+			phy-mode = "10gbase-r";</div><div class='add'>+			sfp = &lt;&amp;sfp_eth49&gt;;</div><div class='add'>+			microchip,sd-sgpio = &lt;321&gt;;</div><div class='add'>+			managed = "in-band-status";</div><div class='add'>+		};</div><div class='add'>+		port50: port@50 {</div><div class='add'>+			reg = &lt;50&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;10000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 19&gt;;</div><div class='add'>+			phy-mode = "10gbase-r";</div><div class='add'>+			sfp = &lt;&amp;sfp_eth50&gt;;</div><div class='add'>+			microchip,sd-sgpio = &lt;325&gt;;</div><div class='add'>+			managed = "in-band-status";</div><div class='add'>+		};</div><div class='add'>+		port51: port@51 {</div><div class='add'>+			reg = &lt;51&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;10000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 20&gt;;</div><div class='add'>+			phy-mode = "10gbase-r";</div><div class='add'>+			sfp = &lt;&amp;sfp_eth51&gt;;</div><div class='add'>+			microchip,sd-sgpio = &lt;329&gt;;</div><div class='add'>+			managed = "in-band-status";</div><div class='add'>+		};</div><div class='add'>+		port52: port@52 {</div><div class='add'>+			reg = &lt;52&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;10000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 21&gt;;</div><div class='add'>+			phy-mode = "10gbase-r";</div><div class='add'>+			sfp = &lt;&amp;sfp_eth52&gt;;</div><div class='add'>+			microchip,sd-sgpio = &lt;333&gt;;</div><div class='add'>+			managed = "in-band-status";</div><div class='add'>+		};</div><div class='add'>+		port53: port@53 {</div><div class='add'>+			reg = &lt;53&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;10000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 22&gt;;</div><div class='add'>+			phy-mode = "10gbase-r";</div><div class='add'>+			sfp = &lt;&amp;sfp_eth53&gt;;</div><div class='add'>+			microchip,sd-sgpio = &lt;337&gt;;</div><div class='add'>+			managed = "in-band-status";</div><div class='add'>+		};</div><div class='add'>+		port54: port@54 {</div><div class='add'>+			reg = &lt;54&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;10000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 23&gt;;</div><div class='add'>+			phy-mode = "10gbase-r";</div><div class='add'>+			sfp = &lt;&amp;sfp_eth54&gt;;</div><div class='add'>+			microchip,sd-sgpio = &lt;341&gt;;</div><div class='add'>+			managed = "in-band-status";</div><div class='add'>+		};</div><div class='add'>+		port55: port@55 {</div><div class='add'>+			reg = &lt;55&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;10000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 24&gt;;</div><div class='add'>+			phy-mode = "10gbase-r";</div><div class='add'>+			sfp = &lt;&amp;sfp_eth55&gt;;</div><div class='add'>+			microchip,sd-sgpio = &lt;345&gt;;</div><div class='add'>+			managed = "in-band-status";</div><div class='add'>+		};</div><div class='add'>+		/* 25G SFPs */</div><div class='add'>+		port56: port@56 {</div><div class='add'>+			reg = &lt;56&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;10000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 25&gt;;</div><div class='add'>+			phy-mode = "10gbase-r";</div><div class='add'>+			sfp = &lt;&amp;sfp_eth56&gt;;</div><div class='add'>+			microchip,sd-sgpio = &lt;349&gt;;</div><div class='add'>+			managed = "in-band-status";</div><div class='add'>+		};</div><div class='add'>+		port57: port@57 {</div><div class='add'>+			reg = &lt;57&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;10000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 26&gt;;</div><div class='add'>+			phy-mode = "10gbase-r";</div><div class='add'>+			sfp = &lt;&amp;sfp_eth57&gt;;</div><div class='add'>+			microchip,sd-sgpio = &lt;353&gt;;</div><div class='add'>+			managed = "in-band-status";</div><div class='add'>+		};</div><div class='add'>+		port58: port@58 {</div><div class='add'>+			reg = &lt;58&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;10000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 27&gt;;</div><div class='add'>+			phy-mode = "10gbase-r";</div><div class='add'>+			sfp = &lt;&amp;sfp_eth58&gt;;</div><div class='add'>+			microchip,sd-sgpio = &lt;357&gt;;</div><div class='add'>+			managed = "in-band-status";</div><div class='add'>+		};</div><div class='add'>+		port59: port@59 {</div><div class='add'>+			reg = &lt;59&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;10000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 28&gt;;</div><div class='add'>+			phy-mode = "10gbase-r";</div><div class='add'>+			sfp = &lt;&amp;sfp_eth59&gt;;</div><div class='add'>+			microchip,sd-sgpio = &lt;361&gt;;</div><div class='add'>+			managed = "in-band-status";</div><div class='add'>+		};</div><div class='add'>+		port60: port@60 {</div><div class='add'>+			reg = &lt;60&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;10000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 29&gt;;</div><div class='add'>+			phy-mode = "10gbase-r";</div><div class='add'>+			sfp = &lt;&amp;sfp_eth60&gt;;</div><div class='add'>+			microchip,sd-sgpio = &lt;365&gt;;</div><div class='add'>+			managed = "in-band-status";</div><div class='add'>+		};</div><div class='add'>+		port61: port@61 {</div><div class='add'>+			reg = &lt;61&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;10000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 30&gt;;</div><div class='add'>+			phy-mode = "10gbase-r";</div><div class='add'>+			sfp = &lt;&amp;sfp_eth61&gt;;</div><div class='add'>+			microchip,sd-sgpio = &lt;369&gt;;</div><div class='add'>+			managed = "in-band-status";</div><div class='add'>+		};</div><div class='add'>+		port62: port@62 {</div><div class='add'>+			reg = &lt;62&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;10000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 31&gt;;</div><div class='add'>+			phy-mode = "10gbase-r";</div><div class='add'>+			sfp = &lt;&amp;sfp_eth62&gt;;</div><div class='add'>+			microchip,sd-sgpio = &lt;373&gt;;</div><div class='add'>+			managed = "in-band-status";</div><div class='add'>+		};</div><div class='add'>+		port63: port@63 {</div><div class='add'>+			reg = &lt;63&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;10000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 32&gt;;</div><div class='add'>+			phy-mode = "10gbase-r";</div><div class='add'>+			sfp = &lt;&amp;sfp_eth63&gt;;</div><div class='add'>+			microchip,sd-sgpio = &lt;377&gt;;</div><div class='add'>+			managed = "in-band-status";</div><div class='add'>+		};</div><div class='add'>+		/* Finally the Management interface */</div><div class='add'>+		port64: port@64 {</div><div class='add'>+			reg = &lt;64&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 0&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy64&gt;;</div><div class='add'>+			phy-mode = "sgmii";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts<br/>new file mode 100644<br/>index 000000000000..bbb9852c1f15<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts</a></div><div class='hunk'>@@ -0,0 +1,40 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "sparx5_pcb134_board.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Sparx5 PCB134 Reference Board (eMMC enabled)";</div><div class='add'>+	compatible = "microchip,sparx5-pcb134", "microchip,sparx5";</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x00000000 0x00000000 0x10000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio {</div><div class='add'>+	emmc_pins: emmc-pins {</div><div class='add'>+		/* NB: No "GPIO_35", "GPIO_36", "GPIO_37"</div><div class='add'>+		 * (N/A: CARD_nDETECT, CARD_WP, CARD_LED)</div><div class='add'>+		 */</div><div class='add'>+		pins = "GPIO_34", "GPIO_38", "GPIO_39",</div><div class='add'>+			"GPIO_40", "GPIO_41", "GPIO_42",</div><div class='add'>+			"GPIO_43", "GPIO_44", "GPIO_45",</div><div class='add'>+			"GPIO_46", "GPIO_47";</div><div class='add'>+		drive-strength = &lt;3&gt;;</div><div class='add'>+		function = "emmc";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sdhci0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;emmc_pins&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	max-frequency = &lt;52000000&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	microchip,clock-delay = &lt;10&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts<br/>new file mode 100644<br/>index 000000000000..647cdb38b113<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/microchip/sparx5_pcb135.dts</a></div><div class='hunk'>@@ -0,0 +1,18 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "sparx5_pcb135_board.dtsi"</div><div class='add'>+#include "sparx5_nand.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Sparx5 PCB135 Reference Board (NAND)";</div><div class='add'>+	compatible = "microchip,sparx5-pcb135", "microchip,sparx5";</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x00000000 0x00000000 0x10000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi<br/>new file mode 100644<br/>index 000000000000..196868898f49<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi</a></div><div class='hunk'>@@ -0,0 +1,742 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "sparx5_pcb_common.dtsi"</div><div class='add'>+</div><div class='add'>+/{</div><div class='add'>+	gpio-restart {</div><div class='add'>+		compatible = "gpio-restart";</div><div class='add'>+		gpios = &lt;&amp;gpio 37 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		priority = &lt;200&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c0_imux: i2c-mux {</div><div class='add'>+		compatible = "i2c-mux-pinctrl";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		i2c-parent = &lt;&amp;i2c0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		led-0 {</div><div class='add'>+			label = "eth60:yellow";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out1 28 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+		led-1 {</div><div class='add'>+			label = "eth60:green";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out1 28 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+		led-2 {</div><div class='add'>+			label = "eth61:yellow";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out1 29 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+		led-3 {</div><div class='add'>+			label = "eth61:green";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out1 29 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+		led-4 {</div><div class='add'>+			label = "eth62:yellow";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out1 30 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+		led-5 {</div><div class='add'>+			label = "eth62:green";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out1 30 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+		led-6 {</div><div class='add'>+			label = "eth63:yellow";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out1 31 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+		led-7 {</div><div class='add'>+			label = "eth63:green";</div><div class='add'>+			gpios = &lt;&amp;sgpio_out1 31 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp_eth60: sfp-eth60 {</div><div class='add'>+		compatible	 = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;i2c_sfp1&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;sgpio_out2 28 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		rate-select0-gpios = &lt;&amp;sgpio_out2 28 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;sgpio_in2 28 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;sgpio_in2 28 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;sgpio_in2 28 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp_eth61: sfp-eth61 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;i2c_sfp2&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;sgpio_out2 29 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		rate-select0-gpios = &lt;&amp;sgpio_out2 29 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;sgpio_in2 29 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;sgpio_in2 29 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;sgpio_in2 29 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp_eth62: sfp-eth62 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;i2c_sfp3&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;sgpio_out2 30 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		rate-select0-gpios = &lt;&amp;sgpio_out2 30 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;sgpio_in2 30 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;sgpio_in2 30 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;sgpio_in2 30 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sfp_eth63: sfp-eth63 {</div><div class='add'>+		compatible = "sff,sfp";</div><div class='add'>+		i2c-bus = &lt;&amp;i2c_sfp4&gt;;</div><div class='add'>+		tx-disable-gpios = &lt;&amp;sgpio_out2 31 0 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		rate-select0-gpios = &lt;&amp;sgpio_out2 31 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		los-gpios = &lt;&amp;sgpio_in2 31 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		mod-def0-gpios = &lt;&amp;sgpio_in2 31 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		tx-fault-gpios = &lt;&amp;sgpio_in2 31 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio {</div><div class='add'>+	i2cmux_pins_i: i2cmux-pins {</div><div class='add'>+	       pins = "GPIO_35", "GPIO_36",</div><div class='add'>+		      "GPIO_50", "GPIO_51";</div><div class='add'>+		function = "twi_scl_m";</div><div class='add'>+		output-low;</div><div class='add'>+	};</div><div class='add'>+	i2cmux_s29: i2cmux-0-pins {</div><div class='add'>+		pins = "GPIO_35";</div><div class='add'>+		function = "twi_scl_m";</div><div class='add'>+		output-high;</div><div class='add'>+	};</div><div class='add'>+	i2cmux_s30: i2cmux-1-pins {</div><div class='add'>+		pins = "GPIO_36";</div><div class='add'>+		function = "twi_scl_m";</div><div class='add'>+		output-high;</div><div class='add'>+	};</div><div class='add'>+	i2cmux_s31: i2cmux-2-pins {</div><div class='add'>+		pins = "GPIO_50";</div><div class='add'>+		function = "twi_scl_m";</div><div class='add'>+		output-high;</div><div class='add'>+	};</div><div class='add'>+	i2cmux_s32: i2cmux-3-pins {</div><div class='add'>+		pins = "GPIO_51";</div><div class='add'>+		function = "twi_scl_m";</div><div class='add'>+		output-high;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	spi@0 {</div><div class='add'>+		compatible = "spi-mux";</div><div class='add'>+		mux-controls = &lt;&amp;mux&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		reg = &lt;0&gt;; /* CS0 */</div><div class='add'>+		flash@9 {</div><div class='add'>+			compatible = "jedec,spi-nor";</div><div class='add'>+			spi-max-frequency = &lt;8000000&gt;;</div><div class='add'>+			reg = &lt;0x9&gt;; /* SPI */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sgpio1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	microchip,sgpio-port-ranges = &lt;24 31&gt;;</div><div class='add'>+	gpio@0 {</div><div class='add'>+		ngpios = &lt;64&gt;;</div><div class='add'>+	};</div><div class='add'>+	gpio@1 {</div><div class='add'>+		ngpios = &lt;64&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sgpio2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	microchip,sgpio-port-ranges = &lt;0 0&gt;, &lt;16 18&gt;, &lt;28 31&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0_imux {</div><div class='add'>+	pinctrl-names =</div><div class='add'>+		"i2c_sfp1", "i2c_sfp2", "i2c_sfp3", "i2c_sfp4",</div><div class='add'>+		"idle";</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2cmux_s29&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;i2cmux_s30&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;i2cmux_s31&gt;;</div><div class='add'>+	pinctrl-3 = &lt;&amp;i2cmux_s32&gt;;</div><div class='add'>+	pinctrl-4 = &lt;&amp;i2cmux_pins_i&gt;;</div><div class='add'>+	i2c_sfp1: i2c@0 {</div><div class='add'>+		reg = &lt;0x0&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+	i2c_sfp2: i2c@1 {</div><div class='add'>+		reg = &lt;0x1&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+	i2c_sfp3: i2c@2 {</div><div class='add'>+		reg = &lt;0x2&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+	i2c_sfp4: i2c@3 {</div><div class='add'>+		reg = &lt;0x3&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdio0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	phy0: ethernet-phy@0 {</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+	phy1: ethernet-phy@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+	phy2: ethernet-phy@2 {</div><div class='add'>+		reg = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+	phy3: ethernet-phy@3 {</div><div class='add'>+		reg = &lt;3&gt;;</div><div class='add'>+	};</div><div class='add'>+	phy4: ethernet-phy@4 {</div><div class='add'>+		reg = &lt;4&gt;;</div><div class='add'>+	};</div><div class='add'>+	phy5: ethernet-phy@5 {</div><div class='add'>+		reg = &lt;5&gt;;</div><div class='add'>+	};</div><div class='add'>+	phy6: ethernet-phy@6 {</div><div class='add'>+		reg = &lt;6&gt;;</div><div class='add'>+	};</div><div class='add'>+	phy7: ethernet-phy@7 {</div><div class='add'>+		reg = &lt;7&gt;;</div><div class='add'>+	};</div><div class='add'>+	phy8: ethernet-phy@8 {</div><div class='add'>+		reg = &lt;8&gt;;</div><div class='add'>+	};</div><div class='add'>+	phy9: ethernet-phy@9 {</div><div class='add'>+		reg = &lt;9&gt;;</div><div class='add'>+	};</div><div class='add'>+	phy10: ethernet-phy@10 {</div><div class='add'>+		reg = &lt;10&gt;;</div><div class='add'>+	};</div><div class='add'>+	phy11: ethernet-phy@11 {</div><div class='add'>+		reg = &lt;11&gt;;</div><div class='add'>+	};</div><div class='add'>+	phy12: ethernet-phy@12 {</div><div class='add'>+		reg = &lt;12&gt;;</div><div class='add'>+	};</div><div class='add'>+	phy13: ethernet-phy@13 {</div><div class='add'>+		reg = &lt;13&gt;;</div><div class='add'>+	};</div><div class='add'>+	phy14: ethernet-phy@14 {</div><div class='add'>+		reg = &lt;14&gt;;</div><div class='add'>+	};</div><div class='add'>+	phy15: ethernet-phy@15 {</div><div class='add'>+		reg = &lt;15&gt;;</div><div class='add'>+	};</div><div class='add'>+	phy16: ethernet-phy@16 {</div><div class='add'>+		reg = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+	phy17: ethernet-phy@17 {</div><div class='add'>+		reg = &lt;17&gt;;</div><div class='add'>+	};</div><div class='add'>+	phy18: ethernet-phy@18 {</div><div class='add'>+		reg = &lt;18&gt;;</div><div class='add'>+	};</div><div class='add'>+	phy19: ethernet-phy@19 {</div><div class='add'>+		reg = &lt;19&gt;;</div><div class='add'>+	};</div><div class='add'>+	phy20: ethernet-phy@20 {</div><div class='add'>+		reg = &lt;20&gt;;</div><div class='add'>+	};</div><div class='add'>+	phy21: ethernet-phy@21 {</div><div class='add'>+		reg = &lt;21&gt;;</div><div class='add'>+	};</div><div class='add'>+	phy22: ethernet-phy@22 {</div><div class='add'>+		reg = &lt;22&gt;;</div><div class='add'>+	};</div><div class='add'>+	phy23: ethernet-phy@23 {</div><div class='add'>+		reg = &lt;23&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdio1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	phy24: ethernet-phy@24 {</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+	phy25: ethernet-phy@25 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+	phy26: ethernet-phy@26 {</div><div class='add'>+		reg = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+	phy27: ethernet-phy@27 {</div><div class='add'>+		reg = &lt;3&gt;;</div><div class='add'>+	};</div><div class='add'>+	phy28: ethernet-phy@28 {</div><div class='add'>+		reg = &lt;4&gt;;</div><div class='add'>+	};</div><div class='add'>+	phy29: ethernet-phy@29 {</div><div class='add'>+		reg = &lt;5&gt;;</div><div class='add'>+	};</div><div class='add'>+	phy30: ethernet-phy@30 {</div><div class='add'>+		reg = &lt;6&gt;;</div><div class='add'>+	};</div><div class='add'>+	phy31: ethernet-phy@31 {</div><div class='add'>+		reg = &lt;7&gt;;</div><div class='add'>+	};</div><div class='add'>+	phy32: ethernet-phy@32 {</div><div class='add'>+		reg = &lt;8&gt;;</div><div class='add'>+	};</div><div class='add'>+	phy33: ethernet-phy@33 {</div><div class='add'>+		reg = &lt;9&gt;;</div><div class='add'>+	};</div><div class='add'>+	phy34: ethernet-phy@34 {</div><div class='add'>+		reg = &lt;10&gt;;</div><div class='add'>+	};</div><div class='add'>+	phy35: ethernet-phy@35 {</div><div class='add'>+		reg = &lt;11&gt;;</div><div class='add'>+	};</div><div class='add'>+	phy36: ethernet-phy@36 {</div><div class='add'>+		reg = &lt;12&gt;;</div><div class='add'>+	};</div><div class='add'>+	phy37: ethernet-phy@37 {</div><div class='add'>+		reg = &lt;13&gt;;</div><div class='add'>+	};</div><div class='add'>+	phy38: ethernet-phy@38 {</div><div class='add'>+		reg = &lt;14&gt;;</div><div class='add'>+	};</div><div class='add'>+	phy39: ethernet-phy@39 {</div><div class='add'>+		reg = &lt;15&gt;;</div><div class='add'>+	};</div><div class='add'>+	phy40: ethernet-phy@40 {</div><div class='add'>+		reg = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+	phy41: ethernet-phy@41 {</div><div class='add'>+		reg = &lt;17&gt;;</div><div class='add'>+	};</div><div class='add'>+	phy42: ethernet-phy@42 {</div><div class='add'>+		reg = &lt;18&gt;;</div><div class='add'>+	};</div><div class='add'>+	phy43: ethernet-phy@43 {</div><div class='add'>+		reg = &lt;19&gt;;</div><div class='add'>+	};</div><div class='add'>+	phy44: ethernet-phy@44 {</div><div class='add'>+		reg = &lt;20&gt;;</div><div class='add'>+	};</div><div class='add'>+	phy45: ethernet-phy@45 {</div><div class='add'>+		reg = &lt;21&gt;;</div><div class='add'>+	};</div><div class='add'>+	phy46: ethernet-phy@46 {</div><div class='add'>+		reg = &lt;22&gt;;</div><div class='add'>+	};</div><div class='add'>+	phy47: ethernet-phy@47 {</div><div class='add'>+		reg = &lt;23&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdio3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	phy64: ethernet-phy@64 {</div><div class='add'>+		reg = &lt;28&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;switch {</div><div class='add'>+	ethernet-ports {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		port0: port@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 13&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy0&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		port1: port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 13&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy1&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		port2: port@2 {</div><div class='add'>+			reg = &lt;2&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 13&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy2&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		port3: port@3 {</div><div class='add'>+			reg = &lt;3&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 13&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy3&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		port4: port@4 {</div><div class='add'>+			reg = &lt;4&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 14&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy4&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		port5: port@5 {</div><div class='add'>+			reg = &lt;5&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 14&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy5&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		port6: port@6 {</div><div class='add'>+			reg = &lt;6&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 14&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy6&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		port7: port@7 {</div><div class='add'>+			reg = &lt;7&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 14&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy7&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		port8: port@8 {</div><div class='add'>+			reg = &lt;8&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 15&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy8&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		port9: port@9 {</div><div class='add'>+			reg = &lt;9&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 15&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy9&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		port10: port@10 {</div><div class='add'>+			reg = &lt;10&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 15&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy10&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		port11: port@11 {</div><div class='add'>+			reg = &lt;11&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 15&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy11&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		port12: port@12 {</div><div class='add'>+			reg = &lt;12&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 16&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy12&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		port13: port@13 {</div><div class='add'>+			reg = &lt;13&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 16&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy13&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		port14: port@14 {</div><div class='add'>+			reg = &lt;14&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 16&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy14&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		port15: port@15 {</div><div class='add'>+			reg = &lt;15&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 16&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy15&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		port16: port@16 {</div><div class='add'>+			reg = &lt;16&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 17&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy16&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		port17: port@17 {</div><div class='add'>+			reg = &lt;17&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 17&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy17&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		port18: port@18 {</div><div class='add'>+			reg = &lt;18&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 17&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy18&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		port19: port@19 {</div><div class='add'>+			reg = &lt;19&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 17&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy19&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		port20: port@20 {</div><div class='add'>+			reg = &lt;20&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 18&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy20&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		port21: port@21 {</div><div class='add'>+			reg = &lt;21&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 18&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy21&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		port22: port@22 {</div><div class='add'>+			reg = &lt;22&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 18&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy22&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		port23: port@23 {</div><div class='add'>+			reg = &lt;23&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 18&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy23&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		port24: port@24 {</div><div class='add'>+			reg = &lt;24&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 19&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy24&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		port25: port@25 {</div><div class='add'>+			reg = &lt;25&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 19&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy25&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		port26: port@26 {</div><div class='add'>+			reg = &lt;26&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 19&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy26&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		port27: port@27 {</div><div class='add'>+			reg = &lt;27&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 19&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy27&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		port28: port@28 {</div><div class='add'>+			reg = &lt;28&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 20&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy28&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		port29: port@29 {</div><div class='add'>+			reg = &lt;29&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 20&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy29&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		port30: port@30 {</div><div class='add'>+			reg = &lt;30&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 20&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy30&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		port31: port@31 {</div><div class='add'>+			reg = &lt;31&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 20&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy31&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		port32: port@32 {</div><div class='add'>+			reg = &lt;32&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 21&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy32&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		port33: port@33 {</div><div class='add'>+			reg = &lt;33&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 21&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy33&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		port34: port@34 {</div><div class='add'>+			reg = &lt;34&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 21&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy34&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		port35: port@35 {</div><div class='add'>+			reg = &lt;35&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 21&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy35&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		port36: port@36 {</div><div class='add'>+			reg = &lt;36&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 22&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy36&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		port37: port@37 {</div><div class='add'>+			reg = &lt;37&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 22&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy37&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		port38: port@38 {</div><div class='add'>+			reg = &lt;38&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 22&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy38&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		port39: port@39 {</div><div class='add'>+			reg = &lt;39&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 22&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy39&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		port40: port@40 {</div><div class='add'>+			reg = &lt;40&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 23&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy40&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		port41: port@41 {</div><div class='add'>+			reg = &lt;41&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 23&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy41&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		port42: port@42 {</div><div class='add'>+			reg = &lt;42&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 23&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy42&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		port43: port@43 {</div><div class='add'>+			reg = &lt;43&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 23&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy43&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		port44: port@44 {</div><div class='add'>+			reg = &lt;44&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 24&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy44&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		port45: port@45 {</div><div class='add'>+			reg = &lt;45&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 24&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy45&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		port46: port@46 {</div><div class='add'>+			reg = &lt;46&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 24&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy46&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		port47: port@47 {</div><div class='add'>+			reg = &lt;47&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 24&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy47&gt;;</div><div class='add'>+			phy-mode = "qsgmii";</div><div class='add'>+		};</div><div class='add'>+		/* Then the 25G interfaces */</div><div class='add'>+		port60: port@60 {</div><div class='add'>+			reg = &lt;60&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;25000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 29&gt;;</div><div class='add'>+			phy-mode = "10gbase-r";</div><div class='add'>+			sfp = &lt;&amp;sfp_eth60&gt;;</div><div class='add'>+			managed = "in-band-status";</div><div class='add'>+		};</div><div class='add'>+		port61: port@61 {</div><div class='add'>+			reg = &lt;61&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;25000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 30&gt;;</div><div class='add'>+			phy-mode = "10gbase-r";</div><div class='add'>+			sfp = &lt;&amp;sfp_eth61&gt;;</div><div class='add'>+			managed = "in-band-status";</div><div class='add'>+		};</div><div class='add'>+		port62: port@62 {</div><div class='add'>+			reg = &lt;62&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;25000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 31&gt;;</div><div class='add'>+			phy-mode = "10gbase-r";</div><div class='add'>+			sfp = &lt;&amp;sfp_eth62&gt;;</div><div class='add'>+			managed = "in-band-status";</div><div class='add'>+		};</div><div class='add'>+		port63: port@63 {</div><div class='add'>+			reg = &lt;63&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;25000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 32&gt;;</div><div class='add'>+			phy-mode = "10gbase-r";</div><div class='add'>+			sfp = &lt;&amp;sfp_eth63&gt;;</div><div class='add'>+			managed = "in-band-status";</div><div class='add'>+		};</div><div class='add'>+		/* Finally the Management interface */</div><div class='add'>+		port64: port@64 {</div><div class='add'>+			reg = &lt;64&gt;;</div><div class='add'>+			microchip,bandwidth = &lt;1000&gt;;</div><div class='add'>+			phys = &lt;&amp;serdes 0&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy64&gt;;</div><div class='add'>+			phy-mode = "sgmii";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts<br/>new file mode 100644<br/>index 000000000000..f82266fe2ad4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts</a></div><div class='hunk'>@@ -0,0 +1,40 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "sparx5_pcb135_board.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Sparx5 PCB135 Reference Board (eMMC enabled)";</div><div class='add'>+	compatible = "microchip,sparx5-pcb135", "microchip,sparx5";</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x00000000 0x00000000 0x10000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpio {</div><div class='add'>+	emmc_pins: emmc-pins {</div><div class='add'>+		/* NB: No "GPIO_35", "GPIO_36", "GPIO_37"</div><div class='add'>+		 * (N/A: CARD_nDETECT, CARD_WP, CARD_LED)</div><div class='add'>+		 */</div><div class='add'>+		pins = "GPIO_34", "GPIO_38", "GPIO_39",</div><div class='add'>+			"GPIO_40", "GPIO_41", "GPIO_42",</div><div class='add'>+			"GPIO_43", "GPIO_44", "GPIO_45",</div><div class='add'>+			"GPIO_46", "GPIO_47";</div><div class='add'>+		drive-strength = &lt;3&gt;;</div><div class='add'>+		function = "emmc";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sdhci0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;emmc_pins&gt;;</div><div class='add'>+	non-removable;</div><div class='add'>+	max-frequency = &lt;52000000&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	microchip,clock-delay = &lt;10&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi<br/>new file mode 100644<br/>index 000000000000..83bf5c81b5f7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi</a></div><div class='hunk'>@@ -0,0 +1,33 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "sparx5.dtsi"</div><div class='add'>+</div><div class='add'>+&amp;psci {</div><div class='add'>+	status = "disabled";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	enable-method = "spin-table";</div><div class='add'>+	cpu-release-addr = /bits/ 64 &lt;0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu1 {</div><div class='add'>+	enable-method = "spin-table";</div><div class='add'>+	cpu-release-addr = /bits/ 64 &lt;0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/nuvoton/Makefile b/arch/arm64/boot/dts/nuvoton/Makefile<br/>new file mode 100644<br/>index 000000000000..3bc9787801a5<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nuvoton/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nuvoton/Makefile</a></div><div class='hunk'>@@ -0,0 +1,4 @@</div><div class='add'>+# SPDX-License-Identifier: GPL-2.0</div><div class='add'>+dtb-$(CONFIG_ARCH_MA35) += ma35d1-iot-512m.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_MA35) += ma35d1-som-256m.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_NPCM) += nuvoton-npcm845-evb.dtb</div><div class='head'>diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts b/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts<br/>new file mode 100644<br/>index 000000000000..9482bec1aa57<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts</a></div><div class='hunk'>@@ -0,0 +1,128 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2023 Nuvoton Technology Corp.</div><div class='add'>+ * Author: Shan-Chun Hung &lt;schung@nuvoton.com&gt;</div><div class='add'>+ *         Jacky huang &lt;ychuang3@nuvoton.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "ma35d1.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Nuvoton MA35D1-IoT";</div><div class='add'>+	compatible = "nuvoton,ma35d1-iot", "nuvoton,ma35d1";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+		serial10 = &amp;uart10;</div><div class='add'>+		serial12 = &amp;uart12;</div><div class='add'>+		serial13 = &amp;uart13;</div><div class='add'>+		serial14 = &amp;uart14;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mem: memory@80000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x00000000 0x80000000 0 0x20000000&gt;; /* 512M DRAM */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_hxt: clock-hxt {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+		clock-output-names = "clk_hxt";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;clk {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk CAPLL&gt;,</div><div class='add'>+			  &lt;&amp;clk DDRPLL&gt;,</div><div class='add'>+			  &lt;&amp;clk APLL&gt;,</div><div class='add'>+			  &lt;&amp;clk EPLL&gt;,</div><div class='add'>+			  &lt;&amp;clk VPLL&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;800000000&gt;,</div><div class='add'>+			       &lt;266000000&gt;,</div><div class='add'>+			       &lt;180000000&gt;,</div><div class='add'>+			       &lt;500000000&gt;,</div><div class='add'>+			       &lt;102000000&gt;;</div><div class='add'>+	nuvoton,pll-mode = "integer",</div><div class='add'>+			   "fractional",</div><div class='add'>+			   "integer",</div><div class='add'>+			   "integer",</div><div class='add'>+			   "integer";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl {</div><div class='add'>+	uart-grp {</div><div class='add'>+		pinctrl_uart0: uart0-pins {</div><div class='add'>+			nuvoton,pins = &lt;4 14 1&gt;,</div><div class='add'>+				       &lt;4 15 1&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+			power-source = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_uart10: uart10-pins {</div><div class='add'>+			nuvoton,pins = &lt;7 4 2&gt;,</div><div class='add'>+				       &lt;7 5 2&gt;,</div><div class='add'>+				       &lt;7 6 2&gt;,</div><div class='add'>+				       &lt;7 7 2&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+			power-source = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_uart12: uart12-pins {</div><div class='add'>+			nuvoton,pins = &lt;2 13 2&gt;,</div><div class='add'>+				       &lt;2 14 2&gt;,</div><div class='add'>+				       &lt;2 15 2&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+			power-source = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_uart13: uart13-pins {</div><div class='add'>+			nuvoton,pins = &lt;7 12 3&gt;,</div><div class='add'>+				       &lt;7 13 3&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+			power-source = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_uart14: uart14-pins {</div><div class='add'>+			nuvoton,pins = &lt;7 14 2&gt;,</div><div class='add'>+				       &lt;7 15 2&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+			power-source = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart10 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart10&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart12 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart12&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart13 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart13&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart14 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart14&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts b/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts<br/>new file mode 100644<br/>index 000000000000..f6f20a17e501<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts</a></div><div class='hunk'>@@ -0,0 +1,131 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2023 Nuvoton Technology Corp.</div><div class='add'>+ * Author: Shan-Chun Hung &lt;schung@nuvoton.com&gt;</div><div class='add'>+ *         Jacky huang &lt;ychuang3@nuvoton.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "ma35d1.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Nuvoton MA35D1-SOM";</div><div class='add'>+	compatible = "nuvoton,ma35d1-som", "nuvoton,ma35d1";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart0;</div><div class='add'>+		serial11 = &amp;uart11;</div><div class='add'>+		serial12 = &amp;uart12;</div><div class='add'>+		serial14 = &amp;uart14;</div><div class='add'>+		serial16 = &amp;uart16;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mem: memory@80000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x00000000 0x80000000 0 0x10000000&gt;; /* 256M DRAM */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_hxt: clock-hxt {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;24000000&gt;;</div><div class='add'>+		clock-output-names = "clk_hxt";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;clk {</div><div class='add'>+	assigned-clocks = &lt;&amp;clk CAPLL&gt;,</div><div class='add'>+			  &lt;&amp;clk DDRPLL&gt;,</div><div class='add'>+			  &lt;&amp;clk APLL&gt;,</div><div class='add'>+			  &lt;&amp;clk EPLL&gt;,</div><div class='add'>+			  &lt;&amp;clk VPLL&gt;;</div><div class='add'>+	assigned-clock-rates = &lt;800000000&gt;,</div><div class='add'>+			       &lt;266000000&gt;,</div><div class='add'>+			       &lt;180000000&gt;,</div><div class='add'>+			       &lt;500000000&gt;,</div><div class='add'>+			       &lt;102000000&gt;;</div><div class='add'>+	nuvoton,pll-mode = "integer",</div><div class='add'>+			   "fractional",</div><div class='add'>+			   "integer",</div><div class='add'>+			   "integer",</div><div class='add'>+			   "integer";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pinctrl {</div><div class='add'>+	uart-grp {</div><div class='add'>+		pinctrl_uart0: uart0-pins {</div><div class='add'>+			nuvoton,pins = &lt;4 14 1&gt;,</div><div class='add'>+				       &lt;4 15 1&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+			power-source = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_uart11: uart11-pins {</div><div class='add'>+			nuvoton,pins = &lt;11 0 2&gt;,</div><div class='add'>+				       &lt;11 1 2&gt;,</div><div class='add'>+				       &lt;11 2 2&gt;,</div><div class='add'>+				       &lt;11 3 2&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+			power-source = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_uart12: uart12-pins {</div><div class='add'>+			nuvoton,pins = &lt;8 1 2&gt;,</div><div class='add'>+				       &lt;8 2 2&gt;,</div><div class='add'>+				       &lt;8 3 2&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+			power-source = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_uart14: uart14-pins {</div><div class='add'>+			nuvoton,pins = &lt;8 5 2&gt;,</div><div class='add'>+				       &lt;8 6 2&gt;,</div><div class='add'>+				       &lt;8 7 2&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+			power-source = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl_uart16: uart16-pins {</div><div class='add'>+			nuvoton,pins = &lt;10 0 2&gt;,</div><div class='add'>+				       &lt;10 1 2&gt;,</div><div class='add'>+				       &lt;10 2 2&gt;,</div><div class='add'>+				       &lt;10 3 2&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+			power-source = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart0&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart11 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart11&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart12 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart12&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart14 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart14&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart16 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_uart16&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi<br/>new file mode 100644<br/>index 000000000000..e51b98f5bdce<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nuvoton/ma35d1.dtsi</a></div><div class='hunk'>@@ -0,0 +1,383 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2023 Nuvoton Technology Corp.</div><div class='add'>+ * Author: Shan-Chun Hung &lt;schung@nuvoton.com&gt;</div><div class='add'>+ *         Jacky huang &lt;ychuang3@nuvoton.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/nuvoton,ma35d1-clk.h&gt;</div><div class='add'>+#include &lt;dt-bindings/reset/nuvoton,ma35d1-reset.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "nuvoton,ma35d1";</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a35";</div><div class='add'>+			reg = &lt;0x0 0x0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@1 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a35";</div><div class='add'>+			reg = &lt;0x0 0x1&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		L2_0: l2-cache {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;0x80000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-0.2";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gic: interrupt-controller@50801000 {</div><div class='add'>+		compatible = "arm,gic-400";</div><div class='add'>+		reg = &lt;0x0 0x50801000 0 0x1000&gt;, /* GICD */</div><div class='add'>+		      &lt;0x0 0x50802000 0 0x2000&gt;, /* GICC */</div><div class='add'>+		      &lt;0x0 0x50804000 0 0x2000&gt;, /* GICH */</div><div class='add'>+		      &lt;0x0 0x50806000 0 0x2000&gt;; /* GICV */</div><div class='add'>+		#interrupt-cells = &lt;3&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		interrupts = &lt;GIC_PPI 9 (GIC_CPU_MASK_RAW(0x13) |</div><div class='add'>+			      IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |</div><div class='add'>+			      IRQ_TYPE_LEVEL_LOW)&gt;, /* Physical Secure */</div><div class='add'>+			     &lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |</div><div class='add'>+			      IRQ_TYPE_LEVEL_LOW)&gt;, /* Physical Non-Secure */</div><div class='add'>+			     &lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |</div><div class='add'>+			      IRQ_TYPE_LEVEL_LOW)&gt;, /* Virtual */</div><div class='add'>+			     &lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |</div><div class='add'>+			      IRQ_TYPE_LEVEL_LOW)&gt;; /* Hypervisor */</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		sys: system-management@40460000 {</div><div class='add'>+			compatible = "nuvoton,ma35d1-reset", "syscon";</div><div class='add'>+			reg = &lt;0x0 0x40460000 0x0 0x200&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		clk: clock-controller@40460200 {</div><div class='add'>+			compatible = "nuvoton,ma35d1-clk";</div><div class='add'>+			reg = &lt;0x00000000 0x40460200 0x0 0x100&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk_hxt&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinctrl: pinctrl@40040000 {</div><div class='add'>+			compatible = "nuvoton,ma35d1-pinctrl";</div><div class='add'>+			reg = &lt;0x0 0x40040000 0x0 0xc00&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			nuvoton,sys = &lt;&amp;sys&gt;;</div><div class='add'>+			ranges = &lt;0x0 0x0 0x40040000 0x400&gt;;</div><div class='add'>+</div><div class='add'>+			gpioa: gpio@0 {</div><div class='add'>+				reg = &lt;0x0 0x40&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk GPA_GATE&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gpiob: gpio@40 {</div><div class='add'>+				reg = &lt;0x40 0x40&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk GPB_GATE&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gpioc: gpio@80 {</div><div class='add'>+				reg = &lt;0x80 0x40&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk GPC_GATE&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gpiod: gpio@c0 {</div><div class='add'>+				reg = &lt;0xc0 0x40&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk GPD_GATE&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gpioe: gpio@100 {</div><div class='add'>+				reg = &lt;0x100 0x40&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk GPE_GATE&gt;;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gpiof: gpio@140 {</div><div class='add'>+				reg = &lt;0x140 0x40&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk GPF_GATE&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gpiog: gpio@180 {</div><div class='add'>+				reg = &lt;0x180 0x40&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk GPG_GATE&gt;;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gpioh: gpio@1c0 {</div><div class='add'>+				reg = &lt;0x1c0 0x40&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk GPH_GATE&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gpioi: gpio@200 {</div><div class='add'>+				reg = &lt;0x200 0x40&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk GPI_GATE&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gpioj: gpio@240 {</div><div class='add'>+				reg = &lt;0x240 0x40&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk GPJ_GATE&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gpiok: gpio@280 {</div><div class='add'>+				reg = &lt;0x280 0x40&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk GPK_GATE&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gpiol: gpio@2c0 {</div><div class='add'>+				reg = &lt;0x2c0 0x40&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk GPL_GATE&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gpiom: gpio@300 {</div><div class='add'>+				reg = &lt;0x300 0x40&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk GPM_GATE&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gpion: gpio@340 {</div><div class='add'>+				reg = &lt;0x340 0x40&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk GPN_GATE&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart0: serial@40700000 {</div><div class='add'>+			compatible = "nuvoton,ma35d1-uart";</div><div class='add'>+			reg = &lt;0x0 0x40700000 0x0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk UART0_GATE&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart1: serial@40710000 {</div><div class='add'>+			compatible = "nuvoton,ma35d1-uart";</div><div class='add'>+			reg = &lt;0x0 0x40710000 0x0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk UART1_GATE&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart2: serial@40720000 {</div><div class='add'>+			compatible = "nuvoton,ma35d1-uart";</div><div class='add'>+			reg = &lt;0x0 0x40720000 0x0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk UART2_GATE&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart3: serial@40730000 {</div><div class='add'>+			compatible = "nuvoton,ma35d1-uart";</div><div class='add'>+			reg = &lt;0x0 0x40730000 0x0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk UART3_GATE&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart4: serial@40740000 {</div><div class='add'>+			compatible = "nuvoton,ma35d1-uart";</div><div class='add'>+			reg = &lt;0x0 0x40740000 0x0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk UART4_GATE&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart5: serial@40750000 {</div><div class='add'>+			compatible = "nuvoton,ma35d1-uart";</div><div class='add'>+			reg = &lt;0x0 0x40750000 0x0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk UART5_GATE&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart6: serial@40760000 {</div><div class='add'>+			compatible = "nuvoton,ma35d1-uart";</div><div class='add'>+			reg = &lt;0x0 0x40760000 0x0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk UART6_GATE&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart7: serial@40770000 {</div><div class='add'>+			compatible = "nuvoton,ma35d1-uart";</div><div class='add'>+			reg = &lt;0x0 0x40770000 0x0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk UART7_GATE&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart8: serial@40780000 {</div><div class='add'>+			compatible = "nuvoton,ma35d1-uart";</div><div class='add'>+			reg = &lt;0x0 0x40780000 0x0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk UART8_GATE&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart9: serial@40790000 {</div><div class='add'>+			compatible = "nuvoton,ma35d1-uart";</div><div class='add'>+			reg = &lt;0x0 0x40790000 0x0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk UART9_GATE&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart10: serial@407a0000 {</div><div class='add'>+			compatible = "nuvoton,ma35d1-uart";</div><div class='add'>+			reg = &lt;0x0 0x407a0000 0x0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk UART10_GATE&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart11: serial@407b0000 {</div><div class='add'>+			compatible = "nuvoton,ma35d1-uart";</div><div class='add'>+			reg = &lt;0x0 0x407b0000 0x0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk UART11_GATE&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart12: serial@407c0000 {</div><div class='add'>+			compatible = "nuvoton,ma35d1-uart";</div><div class='add'>+			reg = &lt;0x0 0x407c0000 0x0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk UART12_GATE&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart13: serial@407d0000 {</div><div class='add'>+			compatible = "nuvoton,ma35d1-uart";</div><div class='add'>+			reg = &lt;0x0 0x407d0000 0x0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk UART13_GATE&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart14: serial@407e0000 {</div><div class='add'>+			compatible = "nuvoton,ma35d1-uart";</div><div class='add'>+			reg = &lt;0x0 0x407e0000 0x0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk UART14_GATE&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart15: serial@407f0000 {</div><div class='add'>+			compatible = "nuvoton,ma35d1-uart";</div><div class='add'>+			reg = &lt;0x0 0x407f0000 0x0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk UART15_GATE&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart16: serial@40880000 {</div><div class='add'>+			compatible = "nuvoton,ma35d1-uart";</div><div class='add'>+			reg = &lt;0x0 0x40880000 0x0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;clk UART16_GATE&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi<br/>new file mode 100644<br/>index 000000000000..24133528b8e9<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi</a></div><div class='hunk'>@@ -0,0 +1,884 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+// Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/nuvoton,npcm845-clk.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+</div><div class='add'>+	soc {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		gcr: system-controller@f0800000 {</div><div class='add'>+			compatible = "nuvoton,npcm845-gcr", "syscon";</div><div class='add'>+			reg = &lt;0x0 0xf0800000 0x0 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@dfff9000 {</div><div class='add'>+			compatible = "arm,gic-400";</div><div class='add'>+			reg = &lt;0x0 0xdfff9000 0x0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0xdfffa000 0x0 0x2000&gt;,</div><div class='add'>+			      &lt;0x0 0xdfffc000 0x0 0x2000&gt;,</div><div class='add'>+			      &lt;0x0 0xdfffe000 0x0 0x2000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#address-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ahb {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		clk: rstc: reset-controller@f0801000 {</div><div class='add'>+			compatible = "nuvoton,npcm845-reset";</div><div class='add'>+			reg = &lt;0x0 0xf0801000 0x0 0xC4&gt;;</div><div class='add'>+			nuvoton,sysgcr = &lt;&amp;gcr&gt;;</div><div class='add'>+			#reset-cells = &lt;2&gt;;</div><div class='add'>+			clocks = &lt;&amp;refclk&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		apb {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			compatible = "simple-bus";</div><div class='add'>+			interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+			ranges = &lt;0x0 0x0 0xf0000000 0x00300000&gt;,</div><div class='add'>+				&lt;0xfff00000 0x0 0xfff00000 0x00016000&gt;;</div><div class='add'>+</div><div class='add'>+			peci: peci-controller@100000 {</div><div class='add'>+				compatible = "nuvoton,npcm845-peci";</div><div class='add'>+				reg = &lt;0x100000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk NPCM8XX_CLK_APB3&gt;;</div><div class='add'>+				cmd-timeout-ms = &lt;1000&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			timer0: timer@8000 {</div><div class='add'>+				compatible = "nuvoton,npcm845-timer";</div><div class='add'>+				interrupts = &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				reg = &lt;0x8000 0x1C&gt;;</div><div class='add'>+				clocks = &lt;&amp;refclk&gt;;</div><div class='add'>+				clock-names = "refclk";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial0: serial@0 {</div><div class='add'>+				compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";</div><div class='add'>+				reg = &lt;0x0 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk NPCM8XX_CLK_UART&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				reg-shift = &lt;2&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial1: serial@1000 {</div><div class='add'>+				compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";</div><div class='add'>+				reg = &lt;0x1000 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk NPCM8XX_CLK_UART&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				reg-shift = &lt;2&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial2: serial@2000 {</div><div class='add'>+				compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";</div><div class='add'>+				reg = &lt;0x2000 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk NPCM8XX_CLK_UART&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				reg-shift = &lt;2&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial3: serial@3000 {</div><div class='add'>+				compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";</div><div class='add'>+				reg = &lt;0x3000 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk NPCM8XX_CLK_UART&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				reg-shift = &lt;2&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial4: serial@4000 {</div><div class='add'>+				compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";</div><div class='add'>+				reg = &lt;0x4000 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk NPCM8XX_CLK_UART&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				reg-shift = &lt;2&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial5: serial@5000 {</div><div class='add'>+				compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";</div><div class='add'>+				reg = &lt;0x5000 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk NPCM8XX_CLK_UART&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				reg-shift = &lt;2&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			serial6: serial@6000 {</div><div class='add'>+				compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";</div><div class='add'>+				reg = &lt;0x6000 0x1000&gt;;</div><div class='add'>+				clocks = &lt;&amp;clk NPCM8XX_CLK_UART&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				reg-shift = &lt;2&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			watchdog0: watchdog@801c {</div><div class='add'>+				compatible = "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt";</div><div class='add'>+				interrupts = &lt;GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				reg = &lt;0x801c 0x4&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+				clocks = &lt;&amp;refclk&gt;;</div><div class='add'>+				syscon = &lt;&amp;gcr&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			watchdog1: watchdog@901c {</div><div class='add'>+				compatible = "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt";</div><div class='add'>+				interrupts = &lt;GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				reg = &lt;0x901c 0x4&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+				clocks = &lt;&amp;refclk&gt;;</div><div class='add'>+				syscon = &lt;&amp;gcr&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			watchdog2: watchdog@a01c {</div><div class='add'>+				compatible = "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt";</div><div class='add'>+				interrupts = &lt;GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				reg = &lt;0xa01c 0x4&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+				clocks = &lt;&amp;refclk&gt;;</div><div class='add'>+				syscon = &lt;&amp;gcr&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl: pinctrl@f0010000 {</div><div class='add'>+		compatible = "nuvoton,npcm845-pinctrl";</div><div class='add'>+		ranges = &lt;0x0 0x0 0xf0010000 0x8000&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		nuvoton,sysgcr = &lt;&amp;gcr&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+		gpio0: gpio@f0010000 {</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			reg = &lt;0x0 0xB0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;pinctrl 0 0 32&gt;;</div><div class='add'>+		};</div><div class='add'>+		gpio1: gpio@f0011000 {</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			reg = &lt;0x1000 0xB0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;pinctrl 0 32 32&gt;;</div><div class='add'>+		};</div><div class='add'>+		gpio2: gpio@f0012000 {</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			reg = &lt;0x2000 0xB0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;pinctrl 0 64 32&gt;;</div><div class='add'>+		};</div><div class='add'>+		gpio3: gpio@f0013000 {</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			reg = &lt;0x3000 0xB0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;pinctrl 0 96 32&gt;;</div><div class='add'>+		};</div><div class='add'>+		gpio4: gpio@f0014000 {</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			reg = &lt;0x4000 0xB0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;pinctrl 0 128 32&gt;;</div><div class='add'>+		};</div><div class='add'>+		gpio5: gpio@f0015000 {</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			reg = &lt;0x5000 0xB0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;pinctrl 0 160 32&gt;;</div><div class='add'>+		};</div><div class='add'>+		gpio6: gpio@f0016000 {</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			reg = &lt;0x6000 0xB0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;pinctrl 0 192 32&gt;;</div><div class='add'>+		};</div><div class='add'>+		gpio7: gpio@f0017000 {</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			reg = &lt;0x7000 0xB0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;pinctrl 0 224 32&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		iox1_pins: iox1-mux {</div><div class='add'>+			groups = "iox1";</div><div class='add'>+			function = "iox1";</div><div class='add'>+		};</div><div class='add'>+		iox2_pins: iox2-mux {</div><div class='add'>+			groups = "iox2";</div><div class='add'>+			function = "iox2";</div><div class='add'>+		};</div><div class='add'>+		smb1d_pins: smb1d-mux {</div><div class='add'>+			groups = "smb1d";</div><div class='add'>+			function = "smb1d";</div><div class='add'>+		};</div><div class='add'>+		smb2d_pins: smb2d-mux {</div><div class='add'>+			groups = "smb2d";</div><div class='add'>+			function = "smb2d";</div><div class='add'>+		};</div><div class='add'>+		lkgpo1_pins: lkgpo1-mux {</div><div class='add'>+			groups = "lkgpo1";</div><div class='add'>+			function = "lkgpo1";</div><div class='add'>+		};</div><div class='add'>+		lkgpo2_pins: lkgpo2-mux {</div><div class='add'>+			groups = "lkgpo2";</div><div class='add'>+			function = "lkgpo2";</div><div class='add'>+		};</div><div class='add'>+		ioxh_pins: ioxh-mux {</div><div class='add'>+			groups = "ioxh";</div><div class='add'>+			function = "ioxh";</div><div class='add'>+		};</div><div class='add'>+		gspi_pins: gspi-mux {</div><div class='add'>+			groups = "gspi";</div><div class='add'>+			function = "gspi";</div><div class='add'>+		};</div><div class='add'>+		smb5b_pins: smb5b-mux {</div><div class='add'>+			groups = "smb5b";</div><div class='add'>+			function = "smb5b";</div><div class='add'>+		};</div><div class='add'>+		smb5c_pins: smb5c-mux {</div><div class='add'>+			groups = "smb5c";</div><div class='add'>+			function = "smb5c";</div><div class='add'>+		};</div><div class='add'>+		lkgpo0_pins: lkgpo0-mux {</div><div class='add'>+			groups = "lkgpo0";</div><div class='add'>+			function = "lkgpo0";</div><div class='add'>+		};</div><div class='add'>+		pspi_pins: pspi-mux {</div><div class='add'>+			groups = "pspi";</div><div class='add'>+			function = "pspi";</div><div class='add'>+		};</div><div class='add'>+		jm1_pins: jm1-mux {</div><div class='add'>+			groups = "jm1";</div><div class='add'>+			function = "jm1";</div><div class='add'>+		};</div><div class='add'>+		jm2_pins: jm2-mux {</div><div class='add'>+			groups = "jm2";</div><div class='add'>+			function = "jm2";</div><div class='add'>+		};</div><div class='add'>+		smb4b_pins: smb4b-mux {</div><div class='add'>+			groups = "smb4b";</div><div class='add'>+			function = "smb4b";</div><div class='add'>+		};</div><div class='add'>+		smb4c_pins: smb4c-mux {</div><div class='add'>+			groups = "smb4c";</div><div class='add'>+			function = "smb4c";</div><div class='add'>+		};</div><div class='add'>+		smb15_pins: smb15-mux {</div><div class='add'>+			groups = "smb15";</div><div class='add'>+			function = "smb15";</div><div class='add'>+		};</div><div class='add'>+		smb16_pins: smb16-mux {</div><div class='add'>+			groups = "smb16";</div><div class='add'>+			function = "smb16";</div><div class='add'>+		};</div><div class='add'>+		smb17_pins: smb17-mux {</div><div class='add'>+			groups = "smb17";</div><div class='add'>+			function = "smb17";</div><div class='add'>+		};</div><div class='add'>+		smb18_pins: smb18-mux {</div><div class='add'>+			groups = "smb18";</div><div class='add'>+			function = "smb18";</div><div class='add'>+		};</div><div class='add'>+		smb19_pins: smb19-mux {</div><div class='add'>+			groups = "smb19";</div><div class='add'>+			function = "smb19";</div><div class='add'>+		};</div><div class='add'>+		smb20_pins: smb20-mux {</div><div class='add'>+			groups = "smb20";</div><div class='add'>+			function = "smb20";</div><div class='add'>+		};</div><div class='add'>+		smb21_pins: smb21-mux {</div><div class='add'>+			groups = "smb21";</div><div class='add'>+			function = "smb21";</div><div class='add'>+		};</div><div class='add'>+		smb22_pins: smb22-mux {</div><div class='add'>+			groups = "smb22";</div><div class='add'>+			function = "smb22";</div><div class='add'>+		};</div><div class='add'>+		smb23_pins: smb23-mux {</div><div class='add'>+			groups = "smb23";</div><div class='add'>+			function = "smb23";</div><div class='add'>+		};</div><div class='add'>+		smb23b_pins: smb23b-mux {</div><div class='add'>+			groups = "smb23b";</div><div class='add'>+			function = "smb23b";</div><div class='add'>+		};</div><div class='add'>+		smb4d_pins: smb4d-mux {</div><div class='add'>+			groups = "smb4d";</div><div class='add'>+			function = "smb4d";</div><div class='add'>+		};</div><div class='add'>+		smb14_pins: smb14-mux {</div><div class='add'>+			groups = "smb14";</div><div class='add'>+			function = "smb14";</div><div class='add'>+		};</div><div class='add'>+		smb5_pins: smb5-mux {</div><div class='add'>+			groups = "smb5";</div><div class='add'>+			function = "smb5";</div><div class='add'>+		};</div><div class='add'>+		smb4_pins: smb4-mux {</div><div class='add'>+			groups = "smb4";</div><div class='add'>+			function = "smb4";</div><div class='add'>+		};</div><div class='add'>+		smb3_pins: smb3-mux {</div><div class='add'>+			groups = "smb3";</div><div class='add'>+			function = "smb3";</div><div class='add'>+		};</div><div class='add'>+		spi0cs1_pins: spi0cs1-mux {</div><div class='add'>+			groups = "spi0cs1";</div><div class='add'>+			function = "spi0cs1";</div><div class='add'>+		};</div><div class='add'>+		spi1cs0_pins: spi1cs0-mux {</div><div class='add'>+			groups = "spi1cs0";</div><div class='add'>+			function = "spi1cs0";</div><div class='add'>+		};</div><div class='add'>+		spi1cs1_pins: spi1cs1-mux {</div><div class='add'>+			groups = "spi1cs1";</div><div class='add'>+			function = "spi1cs1";</div><div class='add'>+		};</div><div class='add'>+		spi1cs2_pins: spi1cs2-mux {</div><div class='add'>+			groups = "spi1cs2";</div><div class='add'>+			function = "spi1cs2";</div><div class='add'>+		};</div><div class='add'>+		spi1cs3_pins: spi1cs3-mux {</div><div class='add'>+			groups = "spi1cs3";</div><div class='add'>+			function = "spi1cs3";</div><div class='add'>+		};</div><div class='add'>+		smb3c_pins: smb3c-mux {</div><div class='add'>+			groups = "smb3c";</div><div class='add'>+			function = "smb3c";</div><div class='add'>+		};</div><div class='add'>+		smb3b_pins: smb3b-mux {</div><div class='add'>+			groups = "smb3b";</div><div class='add'>+			function = "smb3b";</div><div class='add'>+		};</div><div class='add'>+		bmcuart0a_pins: bmcuart0a-mux {</div><div class='add'>+			groups = "bmcuart0a";</div><div class='add'>+			function = "bmcuart0a";</div><div class='add'>+		};</div><div class='add'>+		uart1_pins: uart1-mux {</div><div class='add'>+			groups = "uart1";</div><div class='add'>+			function = "uart1";</div><div class='add'>+		};</div><div class='add'>+		jtag2_pins: jtag2-mux {</div><div class='add'>+			groups = "jtag2";</div><div class='add'>+			function = "jtag2";</div><div class='add'>+		};</div><div class='add'>+		bmcuart1_pins: bmcuart1-mux {</div><div class='add'>+			groups = "bmcuart1";</div><div class='add'>+			function = "bmcuart1";</div><div class='add'>+		};</div><div class='add'>+		uart2_pins: uart2-mux {</div><div class='add'>+			groups = "uart2";</div><div class='add'>+			function = "uart2";</div><div class='add'>+		};</div><div class='add'>+		bmcuart0b_pins: bmcuart0b-mux {</div><div class='add'>+			groups = "bmcuart0b";</div><div class='add'>+			function = "bmcuart0b";</div><div class='add'>+		};</div><div class='add'>+		r1err_pins: r1err-mux {</div><div class='add'>+			groups = "r1err";</div><div class='add'>+			function = "r1err";</div><div class='add'>+		};</div><div class='add'>+		r1md_pins: r1md-mux {</div><div class='add'>+			groups = "r1md";</div><div class='add'>+			function = "r1md";</div><div class='add'>+		};</div><div class='add'>+		r1oen_pins: r1oen-mux {</div><div class='add'>+			groups = "r1oen";</div><div class='add'>+			function = "r1oen";</div><div class='add'>+		};</div><div class='add'>+		r2oen_pins: r2oen-mux {</div><div class='add'>+			groups = "r2oen";</div><div class='add'>+			function = "r2oen";</div><div class='add'>+		};</div><div class='add'>+		rmii3_pins: rmii3-mux {</div><div class='add'>+			groups = "rmii3";</div><div class='add'>+			function = "rmii3";</div><div class='add'>+		};</div><div class='add'>+		r3oen_pins: r3oen-mux {</div><div class='add'>+			groups = "r3oen";</div><div class='add'>+			function = "r3oen";</div><div class='add'>+		};</div><div class='add'>+		smb3d_pins: smb3d-mux {</div><div class='add'>+			groups = "smb3d";</div><div class='add'>+			function = "smb3d";</div><div class='add'>+		};</div><div class='add'>+		fanin0_pins: fanin0-mux {</div><div class='add'>+			groups = "fanin0";</div><div class='add'>+			function = "fanin0";</div><div class='add'>+		};</div><div class='add'>+		fanin1_pins: fanin1-mux {</div><div class='add'>+			groups = "fanin1";</div><div class='add'>+			function = "fanin1";</div><div class='add'>+		};</div><div class='add'>+		fanin2_pins: fanin2-mux {</div><div class='add'>+			groups = "fanin2";</div><div class='add'>+			function = "fanin2";</div><div class='add'>+		};</div><div class='add'>+		fanin3_pins: fanin3-mux {</div><div class='add'>+			groups = "fanin3";</div><div class='add'>+			function = "fanin3";</div><div class='add'>+		};</div><div class='add'>+		fanin4_pins: fanin4-mux {</div><div class='add'>+			groups = "fanin4";</div><div class='add'>+			function = "fanin4";</div><div class='add'>+		};</div><div class='add'>+		fanin5_pins: fanin5-mux {</div><div class='add'>+			groups = "fanin5";</div><div class='add'>+			function = "fanin5";</div><div class='add'>+		};</div><div class='add'>+		fanin6_pins: fanin6-mux {</div><div class='add'>+			groups = "fanin6";</div><div class='add'>+			function = "fanin6";</div><div class='add'>+		};</div><div class='add'>+		fanin7_pins: fanin7-mux {</div><div class='add'>+			groups = "fanin7";</div><div class='add'>+			function = "fanin7";</div><div class='add'>+		};</div><div class='add'>+		fanin8_pins: fanin8-mux {</div><div class='add'>+			groups = "fanin8";</div><div class='add'>+			function = "fanin8";</div><div class='add'>+		};</div><div class='add'>+		fanin9_pins: fanin9-mux {</div><div class='add'>+			groups = "fanin9";</div><div class='add'>+			function = "fanin9";</div><div class='add'>+		};</div><div class='add'>+		fanin10_pins: fanin10-mux {</div><div class='add'>+			groups = "fanin10";</div><div class='add'>+			function = "fanin10";</div><div class='add'>+		};</div><div class='add'>+		fanin11_pins: fanin11-mux {</div><div class='add'>+			groups = "fanin11";</div><div class='add'>+			function = "fanin11";</div><div class='add'>+		};</div><div class='add'>+		fanin12_pins: fanin12-mux {</div><div class='add'>+			groups = "fanin12";</div><div class='add'>+			function = "fanin12";</div><div class='add'>+		};</div><div class='add'>+		fanin13_pins: fanin13-mux {</div><div class='add'>+			groups = "fanin13";</div><div class='add'>+			function = "fanin13";</div><div class='add'>+		};</div><div class='add'>+		fanin14_pins: fanin14-mux {</div><div class='add'>+			groups = "fanin14";</div><div class='add'>+			function = "fanin14";</div><div class='add'>+		};</div><div class='add'>+		fanin15_pins: fanin15-mux {</div><div class='add'>+			groups = "fanin15";</div><div class='add'>+			function = "fanin15";</div><div class='add'>+		};</div><div class='add'>+		pwm0_pins: pwm0-mux {</div><div class='add'>+			groups = "pwm0";</div><div class='add'>+			function = "pwm0";</div><div class='add'>+		};</div><div class='add'>+		pwm1_pins: pwm1-mux {</div><div class='add'>+			groups = "pwm1";</div><div class='add'>+			function = "pwm1";</div><div class='add'>+		};</div><div class='add'>+		pwm2_pins: pwm2-mux {</div><div class='add'>+			groups = "pwm2";</div><div class='add'>+			function = "pwm2";</div><div class='add'>+		};</div><div class='add'>+		pwm3_pins: pwm3-mux {</div><div class='add'>+			groups = "pwm3";</div><div class='add'>+			function = "pwm3";</div><div class='add'>+		};</div><div class='add'>+		r2_pins: r2-mux {</div><div class='add'>+			groups = "r2";</div><div class='add'>+			function = "r2";</div><div class='add'>+		};</div><div class='add'>+		r2err_pins: r2err-mux {</div><div class='add'>+			groups = "r2err";</div><div class='add'>+			function = "r2err";</div><div class='add'>+		};</div><div class='add'>+		r2md_pins: r2md-mux {</div><div class='add'>+			groups = "r2md";</div><div class='add'>+			function = "r2md";</div><div class='add'>+		};</div><div class='add'>+		r3rxer_pins: r3rxer-mux {</div><div class='add'>+			groups = "r3rxer";</div><div class='add'>+			function = "r3rxer";</div><div class='add'>+		};</div><div class='add'>+		ga20kbc_pins: ga20kbc-mux {</div><div class='add'>+			groups = "ga20kbc";</div><div class='add'>+			function = "ga20kbc";</div><div class='add'>+		};</div><div class='add'>+		smb5d_pins: smb5d-mux {</div><div class='add'>+			groups = "smb5d";</div><div class='add'>+			function = "smb5d";</div><div class='add'>+		};</div><div class='add'>+		lpc_pins: lpc-mux {</div><div class='add'>+			groups = "lpc";</div><div class='add'>+			function = "lpc";</div><div class='add'>+		};</div><div class='add'>+		espi_pins: espi-mux {</div><div class='add'>+			groups = "espi";</div><div class='add'>+			function = "espi";</div><div class='add'>+		};</div><div class='add'>+		sg1mdio_pins: sg1mdio-mux {</div><div class='add'>+			groups = "sg1mdio";</div><div class='add'>+			function = "sg1mdio";</div><div class='add'>+		};</div><div class='add'>+		rg2_pins: rg2-mux {</div><div class='add'>+			groups = "rg2";</div><div class='add'>+			function = "rg2";</div><div class='add'>+		};</div><div class='add'>+		ddr_pins: ddr-mux {</div><div class='add'>+			groups = "ddr";</div><div class='add'>+			function = "ddr";</div><div class='add'>+		};</div><div class='add'>+		i3c0_pins: i3c0-mux {</div><div class='add'>+			groups = "i3c0";</div><div class='add'>+			function = "i3c0";</div><div class='add'>+		};</div><div class='add'>+		i3c1_pins: i3c1-mux {</div><div class='add'>+			groups = "i3c1";</div><div class='add'>+			function = "i3c1";</div><div class='add'>+		};</div><div class='add'>+		i3c2_pins: i3c2-mux {</div><div class='add'>+			groups = "i3c2";</div><div class='add'>+			function = "i3c2";</div><div class='add'>+		};</div><div class='add'>+		i3c3_pins: i3c3-mux {</div><div class='add'>+			groups = "i3c3";</div><div class='add'>+			function = "i3c3";</div><div class='add'>+		};</div><div class='add'>+		i3c4_pins: i3c4-mux {</div><div class='add'>+			groups = "i3c4";</div><div class='add'>+			function = "i3c4";</div><div class='add'>+		};</div><div class='add'>+		i3c5_pins: i3c5-mux {</div><div class='add'>+			groups = "i3c5";</div><div class='add'>+			function = "i3c5";</div><div class='add'>+		};</div><div class='add'>+		smb0_pins: smb0-mux {</div><div class='add'>+			groups = "smb0";</div><div class='add'>+			function = "smb0";</div><div class='add'>+		};</div><div class='add'>+		smb1_pins: smb1-mux {</div><div class='add'>+			groups = "smb1";</div><div class='add'>+			function = "smb1";</div><div class='add'>+		};</div><div class='add'>+		smb2_pins: smb2-mux {</div><div class='add'>+			groups = "smb2";</div><div class='add'>+			function = "smb2";</div><div class='add'>+		};</div><div class='add'>+		smb2c_pins: smb2c-mux {</div><div class='add'>+			groups = "smb2c";</div><div class='add'>+			function = "smb2c";</div><div class='add'>+		};</div><div class='add'>+		smb2b_pins: smb2b-mux {</div><div class='add'>+			groups = "smb2b";</div><div class='add'>+			function = "smb2b";</div><div class='add'>+		};</div><div class='add'>+		smb1c_pins: smb1c-mux {</div><div class='add'>+			groups = "smb1c";</div><div class='add'>+			function = "smb1c";</div><div class='add'>+		};</div><div class='add'>+		smb1b_pins: smb1b-mux {</div><div class='add'>+			groups = "smb1b";</div><div class='add'>+			function = "smb1b";</div><div class='add'>+		};</div><div class='add'>+		smb8_pins: smb8-mux {</div><div class='add'>+			groups = "smb8";</div><div class='add'>+			function = "smb8";</div><div class='add'>+		};</div><div class='add'>+		smb9_pins: smb9-mux {</div><div class='add'>+			groups = "smb9";</div><div class='add'>+			function = "smb9";</div><div class='add'>+		};</div><div class='add'>+		smb10_pins: smb10-mux {</div><div class='add'>+			groups = "smb10";</div><div class='add'>+			function = "smb10";</div><div class='add'>+		};</div><div class='add'>+		smb11_pins: smb11-mux {</div><div class='add'>+			groups = "smb11";</div><div class='add'>+			function = "smb11";</div><div class='add'>+		};</div><div class='add'>+		sd1_pins: sd1-mux {</div><div class='add'>+			groups = "sd1";</div><div class='add'>+			function = "sd1";</div><div class='add'>+		};</div><div class='add'>+		sd1pwr_pins: sd1pwr-mux {</div><div class='add'>+			groups = "sd1pwr";</div><div class='add'>+			function = "sd1pwr";</div><div class='add'>+		};</div><div class='add'>+		pwm4_pins: pwm4-mux {</div><div class='add'>+			groups = "pwm4";</div><div class='add'>+			function = "pwm4";</div><div class='add'>+		};</div><div class='add'>+		pwm5_pins: pwm5-mux {</div><div class='add'>+			groups = "pwm5";</div><div class='add'>+			function = "pwm5";</div><div class='add'>+		};</div><div class='add'>+		pwm6_pins: pwm6-mux {</div><div class='add'>+			groups = "pwm6";</div><div class='add'>+			function = "pwm6";</div><div class='add'>+		};</div><div class='add'>+		pwm7_pins: pwm7-mux {</div><div class='add'>+			groups = "pwm7";</div><div class='add'>+			function = "pwm7";</div><div class='add'>+		};</div><div class='add'>+		pwm8_pins: pwm8-mux {</div><div class='add'>+			groups = "pwm8";</div><div class='add'>+			function = "pwm8";</div><div class='add'>+		};</div><div class='add'>+		pwm9_pins: pwm9-mux {</div><div class='add'>+			groups = "pwm9";</div><div class='add'>+			function = "pwm9";</div><div class='add'>+		};</div><div class='add'>+		pwm10_pins: pwm10-mux {</div><div class='add'>+			groups = "pwm10";</div><div class='add'>+			function = "pwm10";</div><div class='add'>+		};</div><div class='add'>+		pwm11_pins: pwm11-mux {</div><div class='add'>+			groups = "pwm11";</div><div class='add'>+			function = "pwm11";</div><div class='add'>+		};</div><div class='add'>+		mmc8_pins: mmc8-mux {</div><div class='add'>+			groups = "mmc8";</div><div class='add'>+			function = "mmc8";</div><div class='add'>+		};</div><div class='add'>+		mmc_pins: mmc-mux {</div><div class='add'>+			groups = "mmc";</div><div class='add'>+			function = "mmc";</div><div class='add'>+		};</div><div class='add'>+		mmcwp_pins: mmcwp-mux {</div><div class='add'>+			groups = "mmcwp";</div><div class='add'>+			function = "mmcwp";</div><div class='add'>+		};</div><div class='add'>+		mmccd_pins: mmccd-mux {</div><div class='add'>+			groups = "mmccd";</div><div class='add'>+			function = "mmccd";</div><div class='add'>+		};</div><div class='add'>+		mmcrst_pins: mmcrst-mux {</div><div class='add'>+			groups = "mmcrst";</div><div class='add'>+			function = "mmcrst";</div><div class='add'>+		};</div><div class='add'>+		clkout_pins: clkout-mux {</div><div class='add'>+			groups = "clkout";</div><div class='add'>+			function = "clkout";</div><div class='add'>+		};</div><div class='add'>+		serirq_pins: serirq-mux {</div><div class='add'>+			groups = "serirq";</div><div class='add'>+			function = "serirq";</div><div class='add'>+		};</div><div class='add'>+		scipme_pins: scipme-mux {</div><div class='add'>+			groups = "scipme";</div><div class='add'>+			function = "scipme";</div><div class='add'>+		};</div><div class='add'>+		smb6_pins: smb6-mux {</div><div class='add'>+			groups = "smb6";</div><div class='add'>+			function = "smb6";</div><div class='add'>+		};</div><div class='add'>+		smb6b_pins: smb6b-mux {</div><div class='add'>+			groups = "smb6b";</div><div class='add'>+			function = "smb6b";</div><div class='add'>+		};</div><div class='add'>+		smb6c_pins: smb6c-mux {</div><div class='add'>+			groups = "smb6c";</div><div class='add'>+			function = "smb6c";</div><div class='add'>+		};</div><div class='add'>+		smb6d_pins: smb6d-mux {</div><div class='add'>+			groups = "smb6d";</div><div class='add'>+			function = "smb6d";</div><div class='add'>+		};</div><div class='add'>+		smb7_pins: smb7-mux {</div><div class='add'>+			groups = "smb7";</div><div class='add'>+			function = "smb7";</div><div class='add'>+		};</div><div class='add'>+		smb7b_pins: smb7b-mux {</div><div class='add'>+			groups = "smb7b";</div><div class='add'>+			function = "smb7b";</div><div class='add'>+		};</div><div class='add'>+		smb7c_pins: smb7c-mux {</div><div class='add'>+			groups = "smb7c";</div><div class='add'>+			function = "smb7c";</div><div class='add'>+		};</div><div class='add'>+		smb7d_pins: smb7d-mux {</div><div class='add'>+			groups = "smb7d";</div><div class='add'>+			function = "smb7d";</div><div class='add'>+		};</div><div class='add'>+		spi1_pins: spi1-mux {</div><div class='add'>+			groups = "spi1";</div><div class='add'>+			function = "spi1";</div><div class='add'>+		};</div><div class='add'>+		faninx_pins: faninx-mux {</div><div class='add'>+			groups = "faninx";</div><div class='add'>+			function = "faninx";</div><div class='add'>+		};</div><div class='add'>+		r1_pins: r1-mux {</div><div class='add'>+			groups = "r1";</div><div class='add'>+			function = "r1";</div><div class='add'>+		};</div><div class='add'>+		spi3_pins: spi3-mux {</div><div class='add'>+			groups = "spi3";</div><div class='add'>+			function = "spi3";</div><div class='add'>+		};</div><div class='add'>+		spi3cs1_pins: spi3cs1-mux {</div><div class='add'>+			groups = "spi3cs1";</div><div class='add'>+			function = "spi3cs1";</div><div class='add'>+		};</div><div class='add'>+		spi3quad_pins: spi3quad-mux {</div><div class='add'>+			groups = "spi3quad";</div><div class='add'>+			function = "spi3quad";</div><div class='add'>+		};</div><div class='add'>+		spi3cs2_pins: spi3cs2-mux {</div><div class='add'>+			groups = "spi3cs2";</div><div class='add'>+			function = "spi3cs2";</div><div class='add'>+		};</div><div class='add'>+		spi3cs3_pins: spi3cs3-mux {</div><div class='add'>+			groups = "spi3cs3";</div><div class='add'>+			function = "spi3cs3";</div><div class='add'>+		};</div><div class='add'>+		nprd_smi_pins: nprd-smi-mux {</div><div class='add'>+			groups = "nprd_smi";</div><div class='add'>+			function = "nprd_smi";</div><div class='add'>+		};</div><div class='add'>+		smi_pins: smi-mux {</div><div class='add'>+			groups = "smi";</div><div class='add'>+			function = "smi";</div><div class='add'>+		};</div><div class='add'>+		smb0b_pins: smb0b-mux {</div><div class='add'>+			groups = "smb0b";</div><div class='add'>+			function = "smb0b";</div><div class='add'>+		};</div><div class='add'>+		smb0c_pins: smb0c-mux {</div><div class='add'>+			groups = "smb0c";</div><div class='add'>+			function = "smb0c";</div><div class='add'>+		};</div><div class='add'>+		smb0den_pins: smb0den-mux {</div><div class='add'>+			groups = "smb0den";</div><div class='add'>+			function = "smb0den";</div><div class='add'>+		};</div><div class='add'>+		smb0d_pins: smb0d-mux {</div><div class='add'>+			groups = "smb0d";</div><div class='add'>+			function = "smb0d";</div><div class='add'>+		};</div><div class='add'>+		ddc_pins: ddc-mux {</div><div class='add'>+			groups = "ddc";</div><div class='add'>+			function = "ddc";</div><div class='add'>+		};</div><div class='add'>+		rg2mdio_pins: rg2mdio-mux {</div><div class='add'>+			groups = "rg2mdio";</div><div class='add'>+			function = "rg2mdio";</div><div class='add'>+		};</div><div class='add'>+		wdog1_pins: wdog1-mux {</div><div class='add'>+			groups = "wdog1";</div><div class='add'>+			function = "wdog1";</div><div class='add'>+		};</div><div class='add'>+		wdog2_pins: wdog2-mux {</div><div class='add'>+			groups = "wdog2";</div><div class='add'>+			function = "wdog2";</div><div class='add'>+		};</div><div class='add'>+		smb12_pins: smb12-mux {</div><div class='add'>+			groups = "smb12";</div><div class='add'>+			function = "smb12";</div><div class='add'>+		};</div><div class='add'>+		smb13_pins: smb13-mux {</div><div class='add'>+			groups = "smb13";</div><div class='add'>+			function = "smb13";</div><div class='add'>+		};</div><div class='add'>+		spix_pins: spix-mux {</div><div class='add'>+			groups = "spix";</div><div class='add'>+			function = "spix";</div><div class='add'>+		};</div><div class='add'>+		spixcs1_pins: spixcs1-mux {</div><div class='add'>+			groups = "spixcs1";</div><div class='add'>+			function = "spixcs1";</div><div class='add'>+		};</div><div class='add'>+		clkreq_pins: clkreq-mux {</div><div class='add'>+			groups = "clkreq";</div><div class='add'>+			function = "clkreq";</div><div class='add'>+		};</div><div class='add'>+		hgpio0_pins: hgpio0-mux {</div><div class='add'>+			groups = "hgpio0";</div><div class='add'>+			function = "hgpio0";</div><div class='add'>+		};</div><div class='add'>+		hgpio1_pins: hgpio1-mux {</div><div class='add'>+			groups = "hgpio1";</div><div class='add'>+			function = "hgpio1";</div><div class='add'>+		};</div><div class='add'>+		hgpio2_pins: hgpio2-mux {</div><div class='add'>+			groups = "hgpio2";</div><div class='add'>+			function = "hgpio2";</div><div class='add'>+		};</div><div class='add'>+		hgpio3_pins: hgpio3-mux {</div><div class='add'>+			groups = "hgpio3";</div><div class='add'>+			function = "hgpio3";</div><div class='add'>+		};</div><div class='add'>+		hgpio4_pins: hgpio4-mux {</div><div class='add'>+			groups = "hgpio4";</div><div class='add'>+			function = "hgpio4";</div><div class='add'>+		};</div><div class='add'>+		hgpio5_pins: hgpio5-mux {</div><div class='add'>+			groups = "hgpio5";</div><div class='add'>+			function = "hgpio5";</div><div class='add'>+		};</div><div class='add'>+		hgpio6_pins: hgpio6-mux {</div><div class='add'>+			groups = "hgpio6";</div><div class='add'>+			function = "hgpio6";</div><div class='add'>+		};</div><div class='add'>+		hgpio7_pins: hgpio7-mux {</div><div class='add'>+			groups = "hgpio7";</div><div class='add'>+			function = "hgpio7";</div><div class='add'>+		};</div><div class='add'>+		bu4_pins: bu4-mux {</div><div class='add'>+			groups = "bu4";</div><div class='add'>+			function = "bu4";</div><div class='add'>+		};</div><div class='add'>+		bu4b_pins: bu4b-mux {</div><div class='add'>+			groups = "bu4b";</div><div class='add'>+			function = "bu4b";</div><div class='add'>+		};</div><div class='add'>+		bu5_pins: bu5-mux {</div><div class='add'>+			groups = "bu5";</div><div class='add'>+			function = "bu5";</div><div class='add'>+		};</div><div class='add'>+		bu5b_pins: bu5b-mux {</div><div class='add'>+			groups = "bu5b";</div><div class='add'>+			function = "bu5b";</div><div class='add'>+		};</div><div class='add'>+		bu6_pins: bu6-mux {</div><div class='add'>+			groups = "bu6";</div><div class='add'>+			function = "bu6";</div><div class='add'>+		};</div><div class='add'>+		gpo187_pins: gpo187-mux {</div><div class='add'>+			groups = "gpo187";</div><div class='add'>+			function = "gpo187";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts<br/>new file mode 100644<br/>index 000000000000..2638ee1c3846<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts</a></div><div class='hunk'>@@ -0,0 +1,36 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+// Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+#include "nuvoton-npcm845.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Nuvoton npcm845 Development Board (Device Tree)";</div><div class='add'>+	compatible = "nuvoton,npcm845-evb", "nuvoton,npcm845";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;serial0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = &amp;serial0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@0 {</div><div class='add'>+		reg = &lt;0x0 0x0 0x0 0x40000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	refclk: refclk-25mhz {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		clock-frequency = &lt;25000000&gt;;</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;serial0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;watchdog1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi<br/>new file mode 100644<br/>index 000000000000..383938dcd3ce<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi</a></div><div class='hunk'>@@ -0,0 +1,78 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+// Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com</div><div class='add'>+</div><div class='add'>+#include "nuvoton-common-npcm8xx.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a35";</div><div class='add'>+			clocks = &lt;&amp;clk NPCM8XX_CLK_CPU&gt;;</div><div class='add'>+			reg = &lt;0x0 0x0&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@1 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a35";</div><div class='add'>+			clocks = &lt;&amp;clk NPCM8XX_CLK_CPU&gt;;</div><div class='add'>+			reg = &lt;0x0 0x1&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@2 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a35";</div><div class='add'>+			clocks = &lt;&amp;clk NPCM8XX_CLK_CPU&gt;;</div><div class='add'>+			reg = &lt;0x0 0x2&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@3 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a35";</div><div class='add'>+			clocks = &lt;&amp;clk NPCM8XX_CLK_CPU&gt;;</div><div class='add'>+			reg = &lt;0x0 0x3&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2: l2-cache {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	arm-pmu {</div><div class='add'>+		compatible = "arm,cortex-a35-pmu";</div><div class='add'>+		interrupts = &lt;GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-affinity = &lt;&amp;cpu0&gt;, &lt;&amp;cpu1&gt;, &lt;&amp;cpu2&gt;, &lt;&amp;cpu3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible      = "arm,psci-1.0";</div><div class='add'>+		method          = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/Makefile b/arch/arm64/boot/dts/nvidia/Makefile<br/>index bcd018c3162b..b139cbd14442 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/Makefile?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/Makefile</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/Makefile</a></div><div class='hunk'>@@ -1,10 +1,37 @@</div><div class='ctx'> # SPDX-License-Identifier: GPL-2.0</div><div class='add'>+</div><div class='add'>+# Enables support for device-tree overlays</div><div class='add'>+DTC_FLAGS_tegra210-p2371-2180 := -@</div><div class='add'>+DTC_FLAGS_tegra210-p3450-0000 := -@</div><div class='add'>+DTC_FLAGS_tegra210-p3541-0000 := -@</div><div class='add'>+DTC_FLAGS_tegra186-p2771-0000 := -@</div><div class='add'>+DTC_FLAGS_tegra186-p3509-0000+p3636-0001 := -@</div><div class='add'>+DTC_FLAGS_tegra194-p2972-0000 := -@</div><div class='add'>+DTC_FLAGS_tegra194-p3509-0000+p3668-0000 := -@</div><div class='add'>+DTC_FLAGS_tegra194-p3509-0000+p3668-0001 := -@</div><div class='add'>+DTC_FLAGS_tegra234-p3737-0000+p3701-0000 := -@</div><div class='add'>+DTC_FLAGS_tegra234-p3740-0002+p3701-0008 := -@</div><div class='add'>+DTC_FLAGS_tegra234-p3768-0000+p3767-0000 := -@</div><div class='add'>+DTC_FLAGS_tegra234-p3768-0000+p3767-0005 := -@</div><div class='add'>+DTC_FLAGS_tegra264-p3971-0089+p3834-0008 := -@</div><div class='add'>+</div><div class='ctx'> dtb-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra132-norrin.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-0000.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-2180.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2571.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p3450-0000.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p3541-0000.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-smaug.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2894-0050-a08.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-p2771-0000.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-p3509-0000+p3636-0001.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p2972-0000.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p3509-0000+p3668-0000.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p3509-0000+p3668-0001.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-sim-vdk.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3737-0000+p3701-0000.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3737-0000+p3701-0008.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3740-0002+p3701-0008.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3768-0000+p3767-0000.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3768-0000+p3767-0005.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_TEGRA_264_SOC) += tegra264-p3971-0089+p3834-0008.dtb</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts<br/>index a0385a386a3f..683ac124523b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra132-norrin.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/tegra132-norrin.dts</a></div><div class='hunk'>@@ -9,8 +9,8 @@</div><div class='ctx'> 	compatible = "nvidia,norrin", "nvidia,tegra132", "nvidia,tegra124";</div><div class='ctx'> </div><div class='ctx'> 	aliases {</div><div class='del'>-		rtc0 = "/i2c@7000d000/as3722@40";</div><div class='del'>-		rtc1 = "/rtc@7000e000";</div><div class='add'>+		rtc0 = &amp;as3722;</div><div class='add'>+		rtc1 = &amp;tegra_rtc;</div><div class='ctx'> 		serial0 = &amp;uarta;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -18,7 +18,7 @@</div><div class='ctx'> 		stdout-path = "serial0:115200n8";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	memory {</div><div class='add'>+	memory@80000000 {</div><div class='ctx'> 		device_type = "memory";</div><div class='ctx'> 		reg = &lt;0x0 0x80000000 0x0 0x80000000&gt;;</div><div class='ctx'> 	};</div><div class='hunk'>@@ -39,6 +39,9 @@</div><div class='ctx'> 		sor@54540000 {</div><div class='ctx'> 			status = "okay";</div><div class='ctx'> </div><div class='add'>+			avdd-io-hdmi-dp-supply = &lt;&amp;vdd_3v3_hdmi&gt;;</div><div class='add'>+			vdd-hdmi-dp-pll-supply = &lt;&amp;vdd_hdmi_pll&gt;;</div><div class='add'>+</div><div class='ctx'> 			nvidia,dpaux = &lt;&amp;dpaux&gt;;</div><div class='ctx'> 			nvidia,panel = &lt;&amp;panel&gt;;</div><div class='ctx'> 		};</div><div class='hunk'>@@ -59,7 +62,7 @@</div><div class='ctx'> 		pinctrl-names = "default";</div><div class='ctx'> 		pinctrl-0 = &lt;&amp;pinmux_default&gt;;</div><div class='ctx'> </div><div class='del'>-		pinmux_default: pinmux@0 {</div><div class='add'>+		pinmux_default: pinmux {</div><div class='ctx'> 			dap_mclk1_pw4 {</div><div class='ctx'> 				nvidia,pins = "dap_mclk1_pw4";</div><div class='ctx'> 				nvidia,function = "extperiph1";</div><div class='hunk'>@@ -528,6 +531,8 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	serial@70006000 {</div><div class='add'>+		/delete-property/ dmas;</div><div class='add'>+		/delete-property/ dma-names;</div><div class='ctx'> 		status = "okay";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -561,7 +566,7 @@</div><div class='ctx'> 			pinctrl-names = "default";</div><div class='ctx'> 			pinctrl-0 = &lt;&amp;as3722_default&gt;;</div><div class='ctx'> </div><div class='del'>-			as3722_default: pinmux@0 {</div><div class='add'>+			as3722_default: pinmux {</div><div class='ctx'> 				gpio0 {</div><div class='ctx'> 					pins = "gpio0";</div><div class='ctx'> 					function = "gpio";</div><div class='hunk'>@@ -671,7 +676,7 @@</div><div class='ctx'> 					regulator-boot-on;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				ldo0 {</div><div class='add'>+				avdd_1v05_run: ldo0 {</div><div class='ctx'> 					regulator-name = "+1.05_RUN_AVDD";</div><div class='ctx'> 					regulator-min-microvolt = &lt;1050000&gt;;</div><div class='ctx'> 					regulator-max-microvolt = &lt;1050000&gt;;</div><div class='hunk'>@@ -757,6 +762,7 @@</div><div class='ctx'> 			interrupt-parent = &lt;&amp;gpio&gt;;</div><div class='ctx'> 			interrupts = &lt;TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 			reg = &lt;0&gt;;</div><div class='add'>+			wakeup-source;</div><div class='ctx'> </div><div class='ctx'> 			google,cros-ec-spi-msg-delay = &lt;2000&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -767,7 +773,7 @@</div><div class='ctx'> </div><div class='ctx'> 				google,remote-bus = &lt;0&gt;;</div><div class='ctx'> </div><div class='del'>-				charger: bq24735 {</div><div class='add'>+				charger: bq24735@9 {</div><div class='ctx'> 					compatible = "ti,bq24735";</div><div class='ctx'> 					reg = &lt;0x9&gt;;</div><div class='ctx'> 					interrupt-parent = &lt;&amp;gpio&gt;;</div><div class='hunk'>@@ -778,10 +784,9 @@</div><div class='ctx'> 							GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				battery: smart-battery {</div><div class='add'>+				battery: smart-battery@b {</div><div class='ctx'> 					compatible = "sbs,sbs-battery";</div><div class='ctx'> 					reg = &lt;0xb&gt;;</div><div class='del'>-					battery-name = "battery";</div><div class='ctx'> 					sbs,i2c-retry-count = &lt;2&gt;;</div><div class='ctx'> 					sbs,poll-retry-count = &lt;10&gt;;</div><div class='ctx'> 				/*	power-supplies = &lt;&amp;charger&gt;; */</div><div class='hunk'>@@ -883,23 +888,116 @@</div><div class='ctx'> 	pmc@7000e400 {</div><div class='ctx'> 		nvidia,invert-interrupt;</div><div class='ctx'> 		nvidia,suspend-mode = &lt;0&gt;;</div><div class='del'>-		#wake-cells = &lt;3&gt;;</div><div class='ctx'> 		nvidia,cpu-pwr-good-time = &lt;500&gt;;</div><div class='ctx'> 		nvidia,cpu-pwr-off-time = &lt;300&gt;;</div><div class='ctx'> 		nvidia,core-pwr-good-time = &lt;641 3845&gt;;</div><div class='ctx'> 		nvidia,core-pwr-off-time = &lt;61036&gt;;</div><div class='ctx'> 		nvidia,core-power-req-active-high;</div><div class='ctx'> 		nvidia,sys-clock-req-active-high;</div><div class='del'>-		nvidia,reset-gpio = &lt;&amp;gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb@70090000 {</div><div class='add'>+		phys = &lt;&amp;{/padctl@7009f000/pads/usb2/lanes/usb2-0}&gt;, /* 1st USB A */</div><div class='add'>+		       &lt;&amp;{/padctl@7009f000/pads/usb2/lanes/usb2-1}&gt;, /* Internal USB */</div><div class='add'>+		       &lt;&amp;{/padctl@7009f000/pads/usb2/lanes/usb2-2}&gt;, /* 2nd USB A */</div><div class='add'>+		       &lt;&amp;{/padctl@7009f000/pads/pcie/lanes/pcie-0}&gt;, /* 1st USB A */</div><div class='add'>+		       &lt;&amp;{/padctl@7009f000/pads/pcie/lanes/pcie-1}&gt;; /* 2nd USB A */</div><div class='add'>+		phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0", "usb3-1";</div><div class='add'>+</div><div class='add'>+		avddio-pex-supply = &lt;&amp;vdd_1v05_run&gt;;</div><div class='add'>+		dvddio-pex-supply = &lt;&amp;vdd_1v05_run&gt;;</div><div class='add'>+		avdd-usb-supply = &lt;&amp;vdd_3v3_lp0&gt;;</div><div class='add'>+		hvdd-usb-ss-supply = &lt;&amp;vdd_3v3_lp0&gt;;</div><div class='add'>+</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	padctl@7009f000 {</div><div class='add'>+		avdd-pll-utmip-supply = &lt;&amp;vddio_1v8&gt;;</div><div class='add'>+		avdd-pll-erefe-supply = &lt;&amp;avdd_1v05_run&gt;;</div><div class='add'>+		avdd-pex-pll-supply = &lt;&amp;vdd_1v05_run&gt;;</div><div class='add'>+		hvdd-pex-pll-e-supply = &lt;&amp;vdd_3v3_lp0&gt;;</div><div class='add'>+</div><div class='add'>+		pads {</div><div class='add'>+			usb2 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				lanes {</div><div class='add'>+					usb2-0 {</div><div class='add'>+						nvidia,function = "xusb";</div><div class='add'>+						status = "okay";</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					usb2-1 {</div><div class='add'>+						nvidia,function = "xusb";</div><div class='add'>+						status = "okay";</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					usb2-2 {</div><div class='add'>+						nvidia,function = "xusb";</div><div class='add'>+						status = "okay";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pcie {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				lanes {</div><div class='add'>+					pcie-0 {</div><div class='add'>+						nvidia,function = "usb3-ss";</div><div class='add'>+						status = "okay";</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					pcie-1 {</div><div class='add'>+						nvidia,function = "usb3-ss";</div><div class='add'>+						status = "okay";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			usb2-0 {</div><div class='add'>+				status = "okay";</div><div class='add'>+				mode = "otg";</div><div class='add'>+</div><div class='add'>+				vbus-supply = &lt;&amp;vdd_usb1_vbus&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			usb2-1 {</div><div class='add'>+				status = "okay";</div><div class='add'>+				mode = "host";</div><div class='add'>+</div><div class='add'>+				vbus-supply = &lt;&amp;vdd_run_cam&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			usb2-2 {</div><div class='add'>+				status = "okay";</div><div class='add'>+				mode = "host";</div><div class='add'>+</div><div class='add'>+				vbus-supply = &lt;&amp;vdd_usb3_vbus&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			usb3-0 {</div><div class='add'>+				nvidia,usb2-companion = &lt;0&gt;;</div><div class='add'>+				status = "okay";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			usb3-1 {</div><div class='add'>+				nvidia,usb2-companion = &lt;2&gt;;</div><div class='add'>+				status = "okay";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	/* WIFI/BT module */</div><div class='del'>-	sdhci@700b0000 {</div><div class='add'>+	mmc@700b0000 {</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	/* external SD/MMC */</div><div class='del'>-	sdhci@700b0400 {</div><div class='add'>+	mmc@700b0400 {</div><div class='ctx'> 		cd-gpios = &lt;&amp;gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 		power-gpios = &lt;&amp;gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 		wp-gpios = &lt;&amp;gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH&gt;;</div><div class='hunk'>@@ -909,39 +1007,12 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	/* EMMC 4.51 */</div><div class='del'>-	sdhci@700b0600 {</div><div class='add'>+	mmc@700b0600 {</div><div class='ctx'> 		status = "okay";</div><div class='ctx'> 		bus-width = &lt;8&gt;;</div><div class='ctx'> 		non-removable;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	usb@7d000000 {</div><div class='del'>-		status = "okay";</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	usb-phy@7d000000 {</div><div class='del'>-		status = "okay";</div><div class='del'>-		vbus-supply = &lt;&amp;vdd_usb1_vbus&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	usb@7d004000 {</div><div class='del'>-		status = "okay";</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	usb-phy@7d004000 {</div><div class='del'>-		status = "okay";</div><div class='del'>-		vbus-supply = &lt;&amp;vdd_run_cam&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	usb@7d008000 {</div><div class='del'>-		status = "okay";</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	usb-phy@7d008000 {</div><div class='del'>-		status = "okay";</div><div class='del'>-		vbus-supply = &lt;&amp;vdd_usb3_vbus&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='ctx'> 	backlight: backlight {</div><div class='ctx'> 		compatible = "pwm-backlight";</div><div class='ctx'> </div><div class='hunk'>@@ -951,27 +1022,26 @@</div><div class='ctx'> </div><div class='ctx'> 		brightness-levels = &lt;0 4 8 16 32 64 128 255&gt;;</div><div class='ctx'> 		default-brightness-level = &lt;6&gt;;</div><div class='del'>-</div><div class='del'>-		backlight-boot-off;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	clocks {</div><div class='del'>-		compatible = "simple-bus";</div><div class='del'>-		#address-cells = &lt;1&gt;;</div><div class='del'>-		#size-cells = &lt;0&gt;;</div><div class='del'>-</div><div class='del'>-		clk32k_in: clock@0 {</div><div class='del'>-			compatible = "fixed-clock";</div><div class='del'>-			reg=&lt;0&gt;;</div><div class='del'>-			#clock-cells = &lt;0&gt;;</div><div class='del'>-			clock-frequency = &lt;32768&gt;;</div><div class='del'>-		};</div><div class='add'>+	clk32k_in: clock-32k {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		clock-frequency = &lt;32768&gt;;</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	gpio-keys {</div><div class='ctx'> 		compatible = "gpio-keys";</div><div class='ctx'> </div><div class='del'>-		lid {</div><div class='add'>+		key-power {</div><div class='add'>+			label = "Power";</div><div class='add'>+			gpios = &lt;&amp;gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+			debounce-interval = &lt;10&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		switch-lid {</div><div class='ctx'> 			label = "Lid";</div><div class='ctx'> 			gpios = &lt;&amp;gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 			linux,input-type = &lt;5&gt;;</div><div class='hunk'>@@ -979,158 +1049,148 @@</div><div class='ctx'> 			debounce-interval = &lt;1&gt;;</div><div class='ctx'> 			wakeup-source;</div><div class='ctx'> 		};</div><div class='del'>-</div><div class='del'>-		power {</div><div class='del'>-			label = "Power";</div><div class='del'>-			gpios = &lt;&amp;gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-			linux,code = &lt;KEY_POWER&gt;;</div><div class='del'>-			debounce-interval = &lt;10&gt;;</div><div class='del'>-			wakeup-source;</div><div class='del'>-		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	panel: panel {</div><div class='del'>-		compatible = "innolux,n116bge", "simple-panel";</div><div class='add'>+		compatible = "innolux,n116bge";</div><div class='add'>+		power-supply = &lt;&amp;vdd_3v3_panel&gt;;</div><div class='ctx'> 		backlight = &lt;&amp;backlight&gt;;</div><div class='ctx'> 		ddc-i2c-bus = &lt;&amp;dpaux&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	regulators {</div><div class='del'>-		compatible = "simple-bus";</div><div class='del'>-		#address-cells = &lt;1&gt;;</div><div class='del'>-		#size-cells = &lt;0&gt;;</div><div class='add'>+	vdd_mux: regulator-vdd-mux {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "+VDD_MUX";</div><div class='add'>+		regulator-min-microvolt = &lt;19000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;19000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		vdd_mux: regulator@0 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;0&gt;;</div><div class='del'>-			regulator-name = "+VDD_MUX";</div><div class='del'>-			regulator-min-microvolt = &lt;19000000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;19000000&gt;;</div><div class='del'>-			regulator-always-on;</div><div class='del'>-			regulator-boot-on;</div><div class='del'>-		};</div><div class='add'>+	vdd_5v0_sys: regulator-vdd-5v0-sys {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "+5V_SYS";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		vin-supply = &lt;&amp;vdd_mux&gt;;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		vdd_5v0_sys: regulator@1 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;1&gt;;</div><div class='del'>-			regulator-name = "+5V_SYS";</div><div class='del'>-			regulator-min-microvolt = &lt;5000000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;5000000&gt;;</div><div class='del'>-			regulator-always-on;</div><div class='del'>-			regulator-boot-on;</div><div class='del'>-			vin-supply = &lt;&amp;vdd_mux&gt;;</div><div class='del'>-		};</div><div class='add'>+	vdd_3v3_sys: regulator-vdd-3v3-sys {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "+3.3V_SYS";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		vin-supply = &lt;&amp;vdd_mux&gt;;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		vdd_3v3_sys: regulator@2 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;2&gt;;</div><div class='del'>-			regulator-name = "+3.3V_SYS";</div><div class='del'>-			regulator-min-microvolt = &lt;3300000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;3300000&gt;;</div><div class='del'>-			regulator-always-on;</div><div class='del'>-			regulator-boot-on;</div><div class='del'>-			vin-supply = &lt;&amp;vdd_mux&gt;;</div><div class='del'>-		};</div><div class='add'>+	vdd_3v3_run: regulator-vdd-3v3-run {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "+3.3V_RUN";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		gpio = &lt;&amp;as3722 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		vin-supply = &lt;&amp;vdd_3v3_sys&gt;;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		vdd_3v3_run: regulator@3 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;3&gt;;</div><div class='del'>-			regulator-name = "+3.3V_RUN";</div><div class='del'>-			regulator-min-microvolt = &lt;3300000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;3300000&gt;;</div><div class='del'>-			regulator-always-on;</div><div class='del'>-			regulator-boot-on;</div><div class='del'>-			gpio = &lt;&amp;as3722 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			enable-active-high;</div><div class='del'>-			vin-supply = &lt;&amp;vdd_3v3_sys&gt;;</div><div class='del'>-		};</div><div class='add'>+	vdd_3v3_hdmi: regulator-vdd-3v3-hdmi {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vdd_3v3_run&gt;;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		vdd_3v3_hdmi: regulator@4 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;4&gt;;</div><div class='del'>-			regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";</div><div class='del'>-			regulator-min-microvolt = &lt;3300000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;3300000&gt;;</div><div class='del'>-			vin-supply = &lt;&amp;vdd_3v3_run&gt;;</div><div class='del'>-		};</div><div class='add'>+	vdd_led: regulator-vdd-led {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "+VDD_LED";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		vin-supply = &lt;&amp;vdd_mux&gt;;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		vdd_led: regulator@5 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;5&gt;;</div><div class='del'>-			regulator-name = "+VDD_LED";</div><div class='del'>-			regulator-min-microvolt = &lt;3300000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;3300000&gt;;</div><div class='del'>-			gpio = &lt;&amp;gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			enable-active-high;</div><div class='del'>-			vin-supply = &lt;&amp;vdd_mux&gt;;</div><div class='del'>-		};</div><div class='add'>+	vdd_usb1_vbus: regulator-vdd-usb1-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "+5V_USB_HS";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio-open-drain;</div><div class='add'>+		vin-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		vdd_usb1_vbus: regulator@6 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;6&gt;;</div><div class='del'>-			regulator-name = "+5V_USB_HS";</div><div class='del'>-			regulator-min-microvolt = &lt;5000000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;5000000&gt;;</div><div class='del'>-			gpio = &lt;&amp;gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			enable-active-high;</div><div class='del'>-			gpio-open-drain;</div><div class='del'>-			vin-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='del'>-		};</div><div class='add'>+	vdd_usb3_vbus: regulator-vdd-usb3-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "+5V_USB_SS";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio-open-drain;</div><div class='add'>+		vin-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		vdd_usb3_vbus: regulator@7 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;7&gt;;</div><div class='del'>-			regulator-name = "+5V_USB_SS";</div><div class='del'>-			regulator-min-microvolt = &lt;5000000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;5000000&gt;;</div><div class='del'>-			gpio = &lt;&amp;gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			enable-active-high;</div><div class='del'>-			gpio-open-drain;</div><div class='del'>-			vin-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='del'>-		};</div><div class='add'>+	vdd_3v3_panel: regulator-vdd-3v3-panel {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "+3.3V_PANEL";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;as3722 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		vin-supply = &lt;&amp;vdd_3v3_sys&gt;;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		vdd_3v3_panel: regulator@8 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;8&gt;;</div><div class='del'>-			regulator-name = "+3.3V_PANEL";</div><div class='del'>-			regulator-min-microvolt = &lt;3300000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;3300000&gt;;</div><div class='del'>-			gpio = &lt;&amp;as3722 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			enable-active-high;</div><div class='del'>-			vin-supply = &lt;&amp;vdd_3v3_sys&gt;;</div><div class='del'>-		};</div><div class='add'>+	vdd_hdmi_pll: regulator-vdd-hdmi-pll {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL_AP_GATE";</div><div class='add'>+		regulator-min-microvolt = &lt;1050000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1050000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vdd_1v05_run&gt;;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		vdd_hdmi_pll: regulator@9 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;9&gt;;</div><div class='del'>-			regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL_AP_GATE";</div><div class='del'>-			regulator-min-microvolt = &lt;1050000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;1050000&gt;;</div><div class='del'>-			gpio = &lt;&amp;gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-			vin-supply = &lt;&amp;vdd_1v05_run&gt;;</div><div class='del'>-		};</div><div class='add'>+	vdd_5v0_hdmi: regulator-vdd-5v0-hdmi {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "+5V_HDMI_CON";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		vin-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		vdd_5v0_hdmi: regulator@10 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;10&gt;;</div><div class='del'>-			regulator-name = "+5V_HDMI_CON";</div><div class='del'>-			regulator-min-microvolt = &lt;5000000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;5000000&gt;;</div><div class='del'>-			gpio = &lt;&amp;gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			enable-active-high;</div><div class='del'>-			vin-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='del'>-		};</div><div class='add'>+	vdd_5v0_ts: regulator-vdd-5v0-ts {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "+5V_VDD_TS";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		gpio = &lt;&amp;gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		vdd_5v0_ts: regulator@11 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;11&gt;;</div><div class='del'>-			regulator-name = "+5V_VDD_TS";</div><div class='del'>-			regulator-min-microvolt = &lt;5000000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;5000000&gt;;</div><div class='del'>-			regulator-always-on;</div><div class='del'>-			regulator-boot-on;</div><div class='del'>-			gpio = &lt;&amp;gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			enable-active-high;</div><div class='del'>-		};</div><div class='add'>+	vdd_3v3_lp0: regulator-vdd-3v3-lp0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "+3.3V_LP0";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		/*</div><div class='add'>+		 * TODO: find a way to wire this up with the USB EHCI</div><div class='add'>+		 * controllers so that it can be enabled on demand.</div><div class='add'>+		 */</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		gpio = &lt;&amp;as3722 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		vin-supply = &lt;&amp;vdd_3v3_sys&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/tegra132-peripherals-opp.dtsi b/arch/arm64/boot/dts/nvidia/tegra132-peripherals-opp.dtsi<br/>new file mode 100644<br/>index 000000000000..66ffb7f8aaa7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra132-peripherals-opp.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/tegra132-peripherals-opp.dtsi</a></div><div class='hunk'>@@ -0,0 +1,426 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	/* EMC DVFS OPP table */</div><div class='add'>+	emc_icc_dvfs_opp_table: opp-table-dvfs0 {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		opp-12750000-800 {</div><div class='add'>+			opp-microvolt = &lt;800000 800000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;12750000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0003&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-12750000-950 {</div><div class='add'>+			opp-microvolt = &lt;950000 950000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;12750000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0008&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-12750000-1050 {</div><div class='add'>+			opp-microvolt = &lt;1050000 1050000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;12750000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0010&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-12750000-1110 {</div><div class='add'>+			opp-microvolt = &lt;1110000 1110000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;12750000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0004&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-20400000-800 {</div><div class='add'>+			opp-microvolt = &lt;800000 800000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;20400000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0003&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-20400000-950 {</div><div class='add'>+			opp-microvolt = &lt;950000 950000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;20400000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0008&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-20400000-1050 {</div><div class='add'>+			opp-microvolt = &lt;1050000 1050000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;20400000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0010&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-20400000-1110 {</div><div class='add'>+			opp-microvolt = &lt;1110000 1110000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;20400000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0004&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-40800000-800 {</div><div class='add'>+			opp-microvolt = &lt;800000 800000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;40800000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0003&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-40800000-950 {</div><div class='add'>+			opp-microvolt = &lt;950000 950000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;40800000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0008&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-40800000-1050 {</div><div class='add'>+			opp-microvolt = &lt;1050000 1050000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;40800000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0010&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-40800000-1110 {</div><div class='add'>+			opp-microvolt = &lt;1110000 1110000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;40800000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0004&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-68000000-800 {</div><div class='add'>+			opp-microvolt = &lt;800000 800000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;68000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0003&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-68000000-950 {</div><div class='add'>+			opp-microvolt = &lt;950000 950000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;68000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0008&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-68000000-1050 {</div><div class='add'>+			opp-microvolt = &lt;1050000 1050000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;68000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0010&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-68000000-1110 {</div><div class='add'>+			opp-microvolt = &lt;1110000 1110000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;68000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0004&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-102000000-800 {</div><div class='add'>+			opp-microvolt = &lt;800000 800000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;102000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0003&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-102000000-950 {</div><div class='add'>+			opp-microvolt = &lt;950000 950000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;102000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0008&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-102000000-1050 {</div><div class='add'>+			opp-microvolt = &lt;1050000 1050000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;102000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0010&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-102000000-1110 {</div><div class='add'>+			opp-microvolt = &lt;1110000 1110000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;102000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0004&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-204000000-800 {</div><div class='add'>+			opp-microvolt = &lt;800000 800000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;204000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0003&gt;;</div><div class='add'>+			opp-suspend;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-204000000-950 {</div><div class='add'>+			opp-microvolt = &lt;950000 950000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;204000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0008&gt;;</div><div class='add'>+			opp-suspend;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-204000000-1050 {</div><div class='add'>+			opp-microvolt = &lt;1050000 1050000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;204000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0010&gt;;</div><div class='add'>+			opp-suspend;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-204000000-1110 {</div><div class='add'>+			opp-microvolt = &lt;1110000 1110000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;204000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0004&gt;;</div><div class='add'>+			opp-suspend;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-264000000-800 {</div><div class='add'>+			opp-microvolt = &lt;800000 800000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;264000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0003&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-264000000-950 {</div><div class='add'>+			opp-microvolt = &lt;950000 950000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;264000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0008&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-264000000-1050 {</div><div class='add'>+			opp-microvolt = &lt;1050000 1050000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;264000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0010&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-264000000-1110 {</div><div class='add'>+			opp-microvolt = &lt;1110000 1110000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;264000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0004&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-300000000-850 {</div><div class='add'>+			opp-microvolt = &lt;850000 850000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;300000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0003&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-300000000-950 {</div><div class='add'>+			opp-microvolt = &lt;950000 950000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;300000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0008&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-300000000-1050 {</div><div class='add'>+			opp-microvolt = &lt;1050000 1050000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;300000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0010&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-300000000-1110 {</div><div class='add'>+			opp-microvolt = &lt;1110000 1110000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;300000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0004&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-348000000-850 {</div><div class='add'>+			opp-microvolt = &lt;850000 850000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;348000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0003&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-348000000-950 {</div><div class='add'>+			opp-microvolt = &lt;950000 950000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;348000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0008&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-348000000-1050 {</div><div class='add'>+			opp-microvolt = &lt;1050000 1050000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;348000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0010&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-348000000-1110 {</div><div class='add'>+			opp-microvolt = &lt;1110000 1110000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;348000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0004&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-396000000-950 {</div><div class='add'>+			opp-microvolt = &lt;950000 950000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;396000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0008&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-396000000-1000 {</div><div class='add'>+			opp-microvolt = &lt;1000000 1000000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;396000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0003&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-396000000-1050 {</div><div class='add'>+			opp-microvolt = &lt;1050000 1050000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;396000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0010&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-396000000-1110 {</div><div class='add'>+			opp-microvolt = &lt;1110000 1110000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;396000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0004&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-528000000-950 {</div><div class='add'>+			opp-microvolt = &lt;950000 950000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;528000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0008&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-528000000-1000 {</div><div class='add'>+			opp-microvolt = &lt;1000000 1000000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;528000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0003&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-528000000-1050 {</div><div class='add'>+			opp-microvolt = &lt;1050000 1050000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;528000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0010&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-528000000-1110 {</div><div class='add'>+			opp-microvolt = &lt;1110000 1110000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;528000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0004&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-600000000-950 {</div><div class='add'>+			opp-microvolt = &lt;950000 950000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;600000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0008&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-600000000-1000 {</div><div class='add'>+			opp-microvolt = &lt;1000000 1000000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;600000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0003&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-600000000-1050 {</div><div class='add'>+			opp-microvolt = &lt;1050000 1050000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;600000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0010&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-600000000-1110 {</div><div class='add'>+			opp-microvolt = &lt;1110000 1110000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;600000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0004&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-792000000-1000 {</div><div class='add'>+			opp-microvolt = &lt;1000000 1000000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;792000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x000B&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-792000000-1050 {</div><div class='add'>+			opp-microvolt = &lt;1050000 1050000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;792000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0010&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-792000000-1110 {</div><div class='add'>+			opp-microvolt = &lt;1110000 1110000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;792000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0004&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-924000000-1100 {</div><div class='add'>+			opp-microvolt = &lt;1100000 1100000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;924000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0013&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1200000000-1100 {</div><div class='add'>+			opp-microvolt = &lt;1100000 1100000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1200000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0003&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* EMC bandwidth OPP table */</div><div class='add'>+	emc_bw_dfs_opp_table: opp-table-dvfs1 {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		opp-12750000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;12750000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x001F&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;204000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-20400000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;20400000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x001F&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;326400&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-40800000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;40800000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x001F&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;652800&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-68000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;68000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x001F&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;1088000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-102000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;102000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x001F&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;1632000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-204000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;204000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x001F&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;3264000&gt;;</div><div class='add'>+			opp-suspend;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-264000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;264000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x001F&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;4224000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-300000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;300000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x001F&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;4800000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-348000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;348000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x001F&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;5568000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-396000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;396000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x001F&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;6336000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-528000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;528000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x001F&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;8448000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-600000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;600000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x001F&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;9600000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-792000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;792000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x001F&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;12672000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-924000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;924000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0013&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;14784000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1200000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1200000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0003&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;19200000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi<br/>index 11a1bb428595..26cd11a8a4a1 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra132.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra132.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra132.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/tegra132.dtsi</a></div><div class='hunk'>@@ -8,6 +8,8 @@</div><div class='ctx'> #include &lt;dt-bindings/thermal/tegra124-soctherm.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/soc/tegra-pmc.h&gt;</div><div class='ctx'> </div><div class='add'>+#include "tegra132-peripherals-opp.dtsi"</div><div class='add'>+</div><div class='ctx'> / {</div><div class='ctx'> 	compatible = "nvidia,tegra132", "nvidia,tegra124";</div><div class='ctx'> 	interrupt-parent = &lt;&amp;lic&gt;;</div><div class='hunk'>@@ -17,9 +19,9 @@</div><div class='ctx'> 	pcie@1003000 {</div><div class='ctx'> 		compatible = "nvidia,tegra124-pcie";</div><div class='ctx'> 		device_type = "pci";</div><div class='del'>-		reg = &lt;0x0 0x01003000 0x0 0x00000800   /* PADS registers */</div><div class='del'>-		       0x0 0x01003800 0x0 0x00000800   /* AFI registers */</div><div class='del'>-		       0x0 0x02000000 0x0 0x10000000&gt;; /* configuration space */</div><div class='add'>+		reg = &lt;0x0 0x01003000 0x0 0x00000800&gt;, /* PADS registers */</div><div class='add'>+		      &lt;0x0 0x01003800 0x0 0x00000800&gt;, /* AFI registers */</div><div class='add'>+		      &lt;0x0 0x02000000 0x0 0x10000000&gt;; /* configuration space */</div><div class='ctx'> 		reg-names = "pads", "afi", "cs";</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH&gt;, /* controller interrupt */</div><div class='ctx'> 			     &lt;GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH&gt;; /* MSI interrupt */</div><div class='hunk'>@@ -33,11 +35,11 @@</div><div class='ctx'> 		#address-cells = &lt;3&gt;;</div><div class='ctx'> 		#size-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='del'>-		ranges = &lt;0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000   /* port 0 configuration space */</div><div class='del'>-			  0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000   /* port 1 configuration space */</div><div class='del'>-			  0x81000000 0 0x0        0x0 0x12000000 0 0x00010000   /* downstream I/O (64 KiB) */</div><div class='del'>-			  0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000   /* non-prefetchable memory (208 MiB) */</div><div class='del'>-			  0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000&gt;; /* prefetchable memory (512 MiB) */</div><div class='add'>+		ranges = &lt;0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000&gt;, /* port 0 configuration space */</div><div class='add'>+			 &lt;0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000&gt;, /* port 1 configuration space */</div><div class='add'>+			 &lt;0x01000000 0 0x0        0x0 0x12000000 0 0x00010000&gt;, /* downstream I/O (64 KiB) */</div><div class='add'>+			 &lt;0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000&gt;, /* non-prefetchable memory (208 MiB) */</div><div class='add'>+			 &lt;0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000&gt;; /* prefetchable memory (512 MiB) */</div><div class='ctx'> </div><div class='ctx'> 		clocks = &lt;&amp;tegra_car TEGRA124_CLK_PCIE&gt;,</div><div class='ctx'> 			 &lt;&amp;tegra_car TEGRA124_CLK_AFI&gt;,</div><div class='hunk'>@@ -50,9 +52,6 @@</div><div class='ctx'> 		reset-names = "pex", "afi", "pcie_x";</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> </div><div class='del'>-		phys = &lt;&amp;padctl TEGRA_XUSB_PADCTL_PCIE&gt;;</div><div class='del'>-		phy-names = "pcie";</div><div class='del'>-</div><div class='ctx'> 		pci@1,0 {</div><div class='ctx'> 			device_type = "pci";</div><div class='ctx'> 			assigned-addresses = &lt;0x82000800 0 0x01000000 0 0x1000&gt;;</div><div class='hunk'>@@ -83,15 +82,19 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	host1x@50000000 {</div><div class='del'>-		compatible = "nvidia,tegra124-host1x", "simple-bus";</div><div class='add'>+		compatible = "nvidia,tegra132-host1x",</div><div class='add'>+			     "nvidia,tegra124-host1x";</div><div class='ctx'> 		reg = &lt;0x0 0x50000000 0x0 0x00034000&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH&gt;, /* syncpt */</div><div class='ctx'> 			     &lt;GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH&gt;; /* general */</div><div class='add'>+		interrupt-names = "syncpt", "host1x";</div><div class='ctx'> 		clocks = &lt;&amp;tegra_car TEGRA124_CLK_HOST1X&gt;;</div><div class='ctx'> 		clock-names = "host1x";</div><div class='ctx'> 		resets = &lt;&amp;tegra_car 28&gt;;</div><div class='ctx'> 		reset-names = "host1x";</div><div class='ctx'> </div><div class='add'>+		iommus = &lt;&amp;mc TEGRA_SWGROUP_HC&gt;;</div><div class='add'>+</div><div class='ctx'> 		#address-cells = &lt;2&gt;;</div><div class='ctx'> 		#size-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -101,9 +104,8 @@</div><div class='ctx'> 			compatible = "nvidia,tegra124-dc";</div><div class='ctx'> 			reg = &lt;0x0 0x54200000 0x0 0x00040000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;tegra_car TEGRA124_CLK_DISP1&gt;,</div><div class='del'>-				 &lt;&amp;tegra_car TEGRA124_CLK_PLL_P&gt;;</div><div class='del'>-			clock-names = "dc", "parent";</div><div class='add'>+			clocks = &lt;&amp;tegra_car TEGRA124_CLK_DISP1&gt;;</div><div class='add'>+			clock-names = "dc";</div><div class='ctx'> 			resets = &lt;&amp;tegra_car 27&gt;;</div><div class='ctx'> 			reset-names = "dc";</div><div class='ctx'> </div><div class='hunk'>@@ -116,9 +118,8 @@</div><div class='ctx'> 			compatible = "nvidia,tegra124-dc";</div><div class='ctx'> 			reg = &lt;0x0 0x54240000 0x0 0x00040000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;tegra_car TEGRA124_CLK_DISP2&gt;,</div><div class='del'>-				 &lt;&amp;tegra_car TEGRA124_CLK_PLL_P&gt;;</div><div class='del'>-			clock-names = "dc", "parent";</div><div class='add'>+			clocks = &lt;&amp;tegra_car TEGRA124_CLK_DISP2&gt;;</div><div class='add'>+			clock-names = "dc";</div><div class='ctx'> 			resets = &lt;&amp;tegra_car 26&gt;;</div><div class='ctx'> 			reset-names = "dc";</div><div class='ctx'> </div><div class='hunk'>@@ -144,10 +145,11 @@</div><div class='ctx'> 			reg = &lt;0x0 0x54540000 0x0 0x00040000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;tegra_car TEGRA124_CLK_SOR0&gt;,</div><div class='add'>+				 &lt;&amp;tegra_car TEGRA124_CLK_SOR0_OUT&gt;,</div><div class='ctx'> 				 &lt;&amp;tegra_car TEGRA124_CLK_PLL_D_OUT0&gt;,</div><div class='ctx'> 				 &lt;&amp;tegra_car TEGRA124_CLK_PLL_DP&gt;,</div><div class='ctx'> 				 &lt;&amp;tegra_car TEGRA124_CLK_CLK_M&gt;;</div><div class='del'>-			clock-names = "sor", "parent", "dp", "safe";</div><div class='add'>+			clock-names = "sor", "out", "parent", "dp", "safe";</div><div class='ctx'> 			resets = &lt;&amp;tegra_car 182&gt;;</div><div class='ctx'> 			reset-names = "sor";</div><div class='ctx'> 			status = "disabled";</div><div class='hunk'>@@ -163,11 +165,17 @@</div><div class='ctx'> 			resets = &lt;&amp;tegra_car 181&gt;;</div><div class='ctx'> 			reset-names = "dpaux";</div><div class='ctx'> 			status = "disabled";</div><div class='add'>+</div><div class='add'>+			i2c-bus {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	gic: interrupt-controller@50041000 {</div><div class='ctx'> 		compatible = "arm,cortex-a15-gic";</div><div class='add'>+		#address-cells = &lt;0&gt;;</div><div class='ctx'> 		#interrupt-cells = &lt;3&gt;;</div><div class='ctx'> 		interrupt-controller;</div><div class='ctx'> 		reg = &lt;0x0 0x50041000 0x0 0x1000&gt;,</div><div class='hunk'>@@ -207,7 +215,7 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	timer@60005000 {</div><div class='del'>-		compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";</div><div class='add'>+		compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer";</div><div class='ctx'> 		reg = &lt;0x0 0x60005000 0x0 0x400&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 			     &lt;GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='hunk'>@@ -241,6 +249,10 @@</div><div class='ctx'> 		clock-names = "actmon", "emc";</div><div class='ctx'> 		resets = &lt;&amp;tegra_car 119&gt;;</div><div class='ctx'> 		reset-names = "actmon";</div><div class='add'>+		operating-points-v2 = &lt;&amp;emc_bw_dfs_opp_table&gt;;</div><div class='add'>+		interconnects = &lt;&amp;mc TEGRA124_MC_MPCORER &amp;emc&gt;;</div><div class='add'>+		interconnect-names = "cpu-read";</div><div class='add'>+		#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	gpio: gpio@6000d000 {</div><div class='hunk'>@@ -260,7 +272,7 @@</div><div class='ctx'> 		interrupt-controller;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	apbdma: dma@60020000 {</div><div class='add'>+	apbdma: dma-controller@60020000 {</div><div class='ctx'> 		compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";</div><div class='ctx'> 		reg = &lt;0x0 0x60020000 0x0 0x1400&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='hunk'>@@ -329,9 +341,7 @@</div><div class='ctx'> 		reg-shift = &lt;2&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		clocks = &lt;&amp;tegra_car TEGRA124_CLK_UARTA&gt;;</div><div class='del'>-		clock-names = "serial";</div><div class='ctx'> 		resets = &lt;&amp;tegra_car 6&gt;;</div><div class='del'>-		reset-names = "serial";</div><div class='ctx'> 		dmas = &lt;&amp;apbdma 8&gt;, &lt;&amp;apbdma 8&gt;;</div><div class='ctx'> 		dma-names = "rx", "tx";</div><div class='ctx'> 		status = "disabled";</div><div class='hunk'>@@ -343,9 +353,7 @@</div><div class='ctx'> 		reg-shift = &lt;2&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		clocks = &lt;&amp;tegra_car TEGRA124_CLK_UARTB&gt;;</div><div class='del'>-		clock-names = "serial";</div><div class='ctx'> 		resets = &lt;&amp;tegra_car 7&gt;;</div><div class='del'>-		reset-names = "serial";</div><div class='ctx'> 		dmas = &lt;&amp;apbdma 9&gt;, &lt;&amp;apbdma 9&gt;;</div><div class='ctx'> 		dma-names = "rx", "tx";</div><div class='ctx'> 		status = "disabled";</div><div class='hunk'>@@ -357,9 +365,7 @@</div><div class='ctx'> 		reg-shift = &lt;2&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		clocks = &lt;&amp;tegra_car TEGRA124_CLK_UARTC&gt;;</div><div class='del'>-		clock-names = "serial";</div><div class='ctx'> 		resets = &lt;&amp;tegra_car 55&gt;;</div><div class='del'>-		reset-names = "serial";</div><div class='ctx'> 		dmas = &lt;&amp;apbdma 10&gt;, &lt;&amp;apbdma 10&gt;;</div><div class='ctx'> 		dma-names = "rx", "tx";</div><div class='ctx'> 		status = "disabled";</div><div class='hunk'>@@ -371,9 +377,7 @@</div><div class='ctx'> 		reg-shift = &lt;2&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		clocks = &lt;&amp;tegra_car TEGRA124_CLK_UARTD&gt;;</div><div class='del'>-		clock-names = "serial";</div><div class='ctx'> 		resets = &lt;&amp;tegra_car 65&gt;;</div><div class='del'>-		reset-names = "serial";</div><div class='ctx'> 		dmas = &lt;&amp;apbdma 19&gt;, &lt;&amp;apbdma 19&gt;;</div><div class='ctx'> 		dma-names = "rx", "tx";</div><div class='ctx'> 		status = "disabled";</div><div class='hunk'>@@ -384,14 +388,13 @@</div><div class='ctx'> 		reg = &lt;0x0 0x7000a000 0x0 0x100&gt;;</div><div class='ctx'> 		#pwm-cells = &lt;2&gt;;</div><div class='ctx'> 		clocks = &lt;&amp;tegra_car TEGRA124_CLK_PWM&gt;;</div><div class='del'>-		clock-names = "pwm";</div><div class='ctx'> 		resets = &lt;&amp;tegra_car 17&gt;;</div><div class='ctx'> 		reset-names = "pwm";</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	i2c@7000c000 {</div><div class='del'>-		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";</div><div class='add'>+		compatible = "nvidia,tegra124-i2c";</div><div class='ctx'> 		reg = &lt;0x0 0x7000c000 0x0 0x100&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='hunk'>@@ -406,7 +409,7 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	i2c@7000c400 {</div><div class='del'>-		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";</div><div class='add'>+		compatible = "nvidia,tegra124-i2c";</div><div class='ctx'> 		reg = &lt;0x0 0x7000c400 0x0 0x100&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='hunk'>@@ -421,7 +424,7 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	i2c@7000c500 {</div><div class='del'>-		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";</div><div class='add'>+		compatible = "nvidia,tegra124-i2c";</div><div class='ctx'> 		reg = &lt;0x0 0x7000c500 0x0 0x100&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='hunk'>@@ -436,7 +439,7 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	i2c@7000c700 {</div><div class='del'>-		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";</div><div class='add'>+		compatible = "nvidia,tegra124-i2c";</div><div class='ctx'> 		reg = &lt;0x0 0x7000c700 0x0 0x100&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='hunk'>@@ -451,7 +454,7 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	i2c@7000d000 {</div><div class='del'>-		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";</div><div class='add'>+		compatible = "nvidia,tegra124-i2c";</div><div class='ctx'> 		reg = &lt;0x0 0x7000d000 0x0 0x100&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='hunk'>@@ -466,7 +469,7 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	i2c@7000d100 {</div><div class='del'>-		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";</div><div class='add'>+		compatible = "nvidia,tegra124-i2c";</div><div class='ctx'> 		reg = &lt;0x0 0x7000d100 0x0 0x100&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='hunk'>@@ -570,7 +573,7 @@</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	rtc@7000e000 {</div><div class='add'>+	tegra_rtc: rtc@7000e000 {</div><div class='ctx'> 		compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";</div><div class='ctx'> 		reg = &lt;0x0 0x7000e000 0x0 0x100&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='hunk'>@@ -604,6 +607,8 @@</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> </div><div class='ctx'> 		#iommu-cells = &lt;1&gt;;</div><div class='add'>+		#reset-cells = &lt;1&gt;;</div><div class='add'>+		#interconnect-cells = &lt;1&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	emc: external-memory-controller@7001b000 {</div><div class='hunk'>@@ -613,6 +618,9 @@</div><div class='ctx'> 		clock-names = "emc";</div><div class='ctx'> </div><div class='ctx'> 		nvidia,memory-controller = &lt;&amp;mc&gt;;</div><div class='add'>+		operating-points-v2 = &lt;&amp;emc_icc_dvfs_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+		#interconnect-cells = &lt;0&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	sata@70020000 {</div><div class='hunk'>@@ -621,16 +629,12 @@</div><div class='ctx'> 		      &lt;0x0 0x70020000 0x0 0x7000&gt;; /* SATA */</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		clocks = &lt;&amp;tegra_car TEGRA124_CLK_SATA&gt;,</div><div class='del'>-			 &lt;&amp;tegra_car TEGRA124_CLK_SATA_OOB&gt;,</div><div class='del'>-			 &lt;&amp;tegra_car TEGRA124_CLK_CML1&gt;,</div><div class='del'>-			 &lt;&amp;tegra_car TEGRA124_CLK_PLL_E&gt;;</div><div class='del'>-		clock-names = "sata", "sata-oob", "cml1", "pll_e";</div><div class='add'>+			 &lt;&amp;tegra_car TEGRA124_CLK_SATA_OOB&gt;;</div><div class='add'>+		clock-names = "sata", "sata-oob";</div><div class='ctx'> 		resets = &lt;&amp;tegra_car 124&gt;,</div><div class='del'>-			 &lt;&amp;tegra_car 123&gt;,</div><div class='del'>-			 &lt;&amp;tegra_car 129&gt;;</div><div class='del'>-		reset-names = "sata", "sata-oob", "sata-cold";</div><div class='del'>-		phys = &lt;&amp;padctl TEGRA_XUSB_PADCTL_SATA&gt;;</div><div class='del'>-		phy-names = "sata-phy";</div><div class='add'>+			 &lt;&amp;tegra_car 129&gt;,</div><div class='add'>+			 &lt;&amp;tegra_car 123&gt;;</div><div class='add'>+		reset-names = "sata", "sata-cold", "sata-oob";</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -650,6 +654,41 @@</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	usb@70090000 {</div><div class='add'>+		compatible = "nvidia,tegra132-xusb", "nvidia,tegra124-xusb";</div><div class='add'>+		reg = &lt;0x0 0x70090000 0x0 0x8000&gt;,</div><div class='add'>+		      &lt;0x0 0x70098000 0x0 0x1000&gt;,</div><div class='add'>+		      &lt;0x0 0x70099000 0x0 0x1000&gt;;</div><div class='add'>+		reg-names = "hcd", "fpci", "ipfs";</div><div class='add'>+</div><div class='add'>+		interrupts = &lt;GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;tegra_car TEGRA124_CLK_XUSB_HOST&gt;,</div><div class='add'>+			 &lt;&amp;tegra_car TEGRA124_CLK_XUSB_HOST_SRC&gt;,</div><div class='add'>+			 &lt;&amp;tegra_car TEGRA124_CLK_XUSB_FALCON_SRC&gt;,</div><div class='add'>+			 &lt;&amp;tegra_car TEGRA124_CLK_XUSB_SS&gt;,</div><div class='add'>+			 &lt;&amp;tegra_car TEGRA124_CLK_XUSB_SS_DIV2&gt;,</div><div class='add'>+			 &lt;&amp;tegra_car TEGRA124_CLK_XUSB_SS_SRC&gt;,</div><div class='add'>+			 &lt;&amp;tegra_car TEGRA124_CLK_XUSB_HS_SRC&gt;,</div><div class='add'>+			 &lt;&amp;tegra_car TEGRA124_CLK_XUSB_FS_SRC&gt;,</div><div class='add'>+			 &lt;&amp;tegra_car TEGRA124_CLK_PLL_U_480M&gt;,</div><div class='add'>+			 &lt;&amp;tegra_car TEGRA124_CLK_CLK_M&gt;,</div><div class='add'>+			 &lt;&amp;tegra_car TEGRA124_CLK_PLL_E&gt;;</div><div class='add'>+		clock-names = "xusb_host", "xusb_host_src",</div><div class='add'>+			      "xusb_falcon_src", "xusb_ss",</div><div class='add'>+			      "xusb_ss_div2", "xusb_ss_src",</div><div class='add'>+			      "xusb_hs_src", "xusb_fs_src",</div><div class='add'>+			      "pll_u_480m", "clk_m", "pll_e";</div><div class='add'>+		resets = &lt;&amp;tegra_car 89&gt;, &lt;&amp;tegra_car 156&gt;,</div><div class='add'>+			 &lt;&amp;tegra_car 143&gt;;</div><div class='add'>+		reset-names = "xusb_host", "xusb_ss", "xusb_src";</div><div class='add'>+</div><div class='add'>+		nvidia,xusb-padctl = &lt;&amp;padctl&gt;;</div><div class='add'>+</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	padctl: padctl@7009f000 {</div><div class='ctx'> 		compatible = "nvidia,tegra132-xusb-padctl",</div><div class='ctx'> 			     "nvidia,tegra124-xusb-padctl";</div><div class='hunk'>@@ -657,40 +696,130 @@</div><div class='ctx'> 		resets = &lt;&amp;tegra_car 142&gt;;</div><div class='ctx'> 		reset-names = "padctl";</div><div class='ctx'> </div><div class='del'>-		#phy-cells = &lt;1&gt;;</div><div class='add'>+		pads {</div><div class='add'>+			usb2 {</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				lanes {</div><div class='add'>+					usb2-0 {</div><div class='add'>+						status = "disabled";</div><div class='add'>+						#phy-cells = &lt;0&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					usb2-1 {</div><div class='add'>+						status = "disabled";</div><div class='add'>+						#phy-cells = &lt;0&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					usb2-2 {</div><div class='add'>+						status = "disabled";</div><div class='add'>+						#phy-cells = &lt;0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='ctx'> </div><div class='del'>-		phys {</div><div class='del'>-			pcie-0 {</div><div class='add'>+			ulpi {</div><div class='ctx'> 				status = "disabled";</div><div class='add'>+</div><div class='add'>+				lanes {</div><div class='add'>+					ulpi-0 {</div><div class='add'>+						status = "disabled";</div><div class='add'>+						#phy-cells = &lt;0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			sata-0 {</div><div class='add'>+			hsic {</div><div class='ctx'> 				status = "disabled";</div><div class='add'>+</div><div class='add'>+				lanes {</div><div class='add'>+					hsic-0 {</div><div class='add'>+						status = "disabled";</div><div class='add'>+						#phy-cells = &lt;0&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					hsic-1 {</div><div class='add'>+						status = "disabled";</div><div class='add'>+						#phy-cells = &lt;0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			usb3-0 {</div><div class='add'>+			pcie {</div><div class='ctx'> 				status = "disabled";</div><div class='add'>+</div><div class='add'>+				lanes {</div><div class='add'>+					pcie-0 {</div><div class='add'>+						status = "disabled";</div><div class='add'>+						#phy-cells = &lt;0&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					pcie-1 {</div><div class='add'>+						status = "disabled";</div><div class='add'>+						#phy-cells = &lt;0&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					pcie-2 {</div><div class='add'>+						status = "disabled";</div><div class='add'>+						#phy-cells = &lt;0&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					pcie-3 {</div><div class='add'>+						status = "disabled";</div><div class='add'>+						#phy-cells = &lt;0&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					pcie-4 {</div><div class='add'>+						status = "disabled";</div><div class='add'>+						#phy-cells = &lt;0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			usb3-1 {</div><div class='add'>+			sata {</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				lanes {</div><div class='add'>+					sata-0 {</div><div class='add'>+						status = "disabled";</div><div class='add'>+						#phy-cells = &lt;0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			usb2-0 {</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			usb2-1 {</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			usb2-2 {</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			hsic-0 {</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			utmi-0 {</div><div class='add'>+			hsic-1 {</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			utmi-1 {</div><div class='add'>+			usb3-0 {</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			utmi-2 {</div><div class='add'>+			usb3-1 {</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sdhci@700b0000 {</div><div class='add'>+	mmc@700b0000 {</div><div class='ctx'> 		compatible = "nvidia,tegra124-sdhci";</div><div class='ctx'> 		reg = &lt;0x0 0x700b0000 0x0 0x200&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='hunk'>@@ -701,7 +830,7 @@</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sdhci@700b0200 {</div><div class='add'>+	mmc@700b0200 {</div><div class='ctx'> 		compatible = "nvidia,tegra124-sdhci";</div><div class='ctx'> 		reg = &lt;0x0 0x700b0200 0x0 0x200&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='hunk'>@@ -712,7 +841,7 @@</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sdhci@700b0400 {</div><div class='add'>+	mmc@700b0400 {</div><div class='ctx'> 		compatible = "nvidia,tegra124-sdhci";</div><div class='ctx'> 		reg = &lt;0x0 0x700b0400 0x0 0x200&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='hunk'>@@ -723,7 +852,7 @@</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sdhci@700b0600 {</div><div class='add'>+	mmc@700b0600 {</div><div class='ctx'> 		compatible = "nvidia,tegra124-sdhci";</div><div class='ctx'> 		reg = &lt;0x0 0x700b0600 0x0 0x200&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='hunk'>@@ -736,12 +865,14 @@</div><div class='ctx'> </div><div class='ctx'> 	soctherm: thermal-sensor@700e2000 {</div><div class='ctx'> 		compatible = "nvidia,tegra132-soctherm";</div><div class='del'>-		reg = &lt;0x0 0x700e2000 0x0 0x600 /* 0: SOC_THERM reg_base */</div><div class='del'>-			0x0 0x70040000 0x0 0x200&gt;; /* 2: CCROC reg_base */</div><div class='add'>+		reg = &lt;0x0 0x700e2000 0x0 0x600&gt;, /* 0: SOC_THERM reg_base */</div><div class='add'>+		      &lt;0x0 0x70040000 0x0 0x200&gt;; /* 2: CCROC reg_base */</div><div class='ctx'> 		reg-names = "soctherm-reg", "ccroc-reg";</div><div class='del'>-		interrupts = &lt;GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-names = "thermal", "edp";</div><div class='ctx'> 		clocks = &lt;&amp;tegra_car TEGRA124_CLK_TSENSOR&gt;,</div><div class='del'>-			&lt;&amp;tegra_car TEGRA124_CLK_SOC_THERM&gt;;</div><div class='add'>+		         &lt;&amp;tegra_car TEGRA124_CLK_SOC_THERM&gt;;</div><div class='ctx'> 		clock-names = "tsensor", "soctherm";</div><div class='ctx'> 		resets = &lt;&amp;tegra_car 78&gt;;</div><div class='ctx'> 		reset-names = "soctherm";</div><div class='hunk'>@@ -757,109 +888,6 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	thermal-zones {</div><div class='del'>-		cpu {</div><div class='del'>-			polling-delay-passive = &lt;1000&gt;;</div><div class='del'>-			polling-delay = &lt;0&gt;;</div><div class='del'>-</div><div class='del'>-			thermal-sensors =</div><div class='del'>-				&lt;&amp;soctherm TEGRA124_SOCTHERM_SENSOR_CPU&gt;;</div><div class='del'>-</div><div class='del'>-			trips {</div><div class='del'>-				cpu_shutdown_trip {</div><div class='del'>-					temperature = &lt;105000&gt;;</div><div class='del'>-					hysteresis = &lt;1000&gt;;</div><div class='del'>-					type = "critical";</div><div class='del'>-				};</div><div class='del'>-</div><div class='del'>-				cpu_throttle_trip: throttle-trip {</div><div class='del'>-					temperature = &lt;102000&gt;;</div><div class='del'>-					hysteresis = &lt;1000&gt;;</div><div class='del'>-					type = "hot";</div><div class='del'>-				};</div><div class='del'>-			};</div><div class='del'>-</div><div class='del'>-			cooling-maps {</div><div class='del'>-				map0 {</div><div class='del'>-					trip = &lt;&amp;cpu_throttle_trip&gt;;</div><div class='del'>-					cooling-device = &lt;&amp;throttle_heavy 1 1&gt;;</div><div class='del'>-				};</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-		mem {</div><div class='del'>-			polling-delay-passive = &lt;0&gt;;</div><div class='del'>-			polling-delay = &lt;0&gt;;</div><div class='del'>-</div><div class='del'>-			thermal-sensors =</div><div class='del'>-				&lt;&amp;soctherm TEGRA124_SOCTHERM_SENSOR_MEM&gt;;</div><div class='del'>-</div><div class='del'>-			trips {</div><div class='del'>-				mem_shutdown_trip {</div><div class='del'>-					temperature = &lt;101000&gt;;</div><div class='del'>-					hysteresis = &lt;1000&gt;;</div><div class='del'>-					type = "critical";</div><div class='del'>-				};</div><div class='del'>-			};</div><div class='del'>-</div><div class='del'>-			cooling-maps {</div><div class='del'>-				/*</div><div class='del'>-				 * There are currently no cooling maps,</div><div class='del'>-				 * because there are no cooling devices.</div><div class='del'>-				 */</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-		gpu {</div><div class='del'>-			polling-delay-passive = &lt;1000&gt;;</div><div class='del'>-			polling-delay = &lt;0&gt;;</div><div class='del'>-</div><div class='del'>-			thermal-sensors =</div><div class='del'>-				&lt;&amp;soctherm TEGRA124_SOCTHERM_SENSOR_GPU&gt;;</div><div class='del'>-</div><div class='del'>-			trips {</div><div class='del'>-				gpu_shutdown_trip {</div><div class='del'>-					temperature = &lt;101000&gt;;</div><div class='del'>-					hysteresis = &lt;1000&gt;;</div><div class='del'>-					type = "critical";</div><div class='del'>-				};</div><div class='del'>-</div><div class='del'>-				gpu_throttle_trip: throttle-trip {</div><div class='del'>-					temperature = &lt;99000&gt;;</div><div class='del'>-					hysteresis = &lt;1000&gt;;</div><div class='del'>-					type = "hot";</div><div class='del'>-				};</div><div class='del'>-			};</div><div class='del'>-</div><div class='del'>-			cooling-maps {</div><div class='del'>-				map0 {</div><div class='del'>-					trip = &lt;&amp;gpu_throttle_trip&gt;;</div><div class='del'>-					cooling-device = &lt;&amp;throttle_heavy 1 1&gt;;</div><div class='del'>-				};</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-		pllx {</div><div class='del'>-			polling-delay-passive = &lt;0&gt;;</div><div class='del'>-			polling-delay = &lt;0&gt;;</div><div class='del'>-</div><div class='del'>-			thermal-sensors =</div><div class='del'>-				&lt;&amp;soctherm TEGRA124_SOCTHERM_SENSOR_PLLX&gt;;</div><div class='del'>-</div><div class='del'>-			trips {</div><div class='del'>-				pllx_shutdown_trip {</div><div class='del'>-					temperature = &lt;105000&gt;;</div><div class='del'>-					hysteresis = &lt;1000&gt;;</div><div class='del'>-					type = "critical";</div><div class='del'>-				};</div><div class='del'>-			};</div><div class='del'>-</div><div class='del'>-			cooling-maps {</div><div class='del'>-				/*</div><div class='del'>-				 * There are currently no cooling maps,</div><div class='del'>-				 * because there are no cooling devices.</div><div class='del'>-				 */</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='ctx'> 	ahub@70300000 {</div><div class='ctx'> 		compatible = "nvidia,tegra124-ahub";</div><div class='ctx'> 		reg = &lt;0x0 0x70300000 0x0 0x200&gt;,</div><div class='hunk'>@@ -969,7 +997,7 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	usb@7d000000 {</div><div class='del'>-		compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";</div><div class='add'>+		compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";</div><div class='ctx'> 		reg = &lt;0x0 0x7d000000 0x0 0x4000&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		phy_type = "utmi";</div><div class='hunk'>@@ -985,6 +1013,7 @@</div><div class='ctx'> 		compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";</div><div class='ctx'> 		reg = &lt;0x0 0x7d000000 0x0 0x4000&gt;,</div><div class='ctx'> 		      &lt;0x0 0x7d000000 0x0 0x4000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		phy_type = "utmi";</div><div class='ctx'> 		clocks = &lt;&amp;tegra_car TEGRA124_CLK_USBD&gt;,</div><div class='ctx'> 			 &lt;&amp;tegra_car TEGRA124_CLK_PLL_U&gt;,</div><div class='hunk'>@@ -992,6 +1021,7 @@</div><div class='ctx'> 		clock-names = "reg", "pll_u", "utmi-pads";</div><div class='ctx'> 		resets = &lt;&amp;tegra_car 22&gt;, &lt;&amp;tegra_car 22&gt;;</div><div class='ctx'> 		reset-names = "usb", "utmi-pads";</div><div class='add'>+		#phy-cells = &lt;0&gt;;</div><div class='ctx'> 		nvidia,hssync-start-delay = &lt;0&gt;;</div><div class='ctx'> 		nvidia,idle-wait-delay = &lt;17&gt;;</div><div class='ctx'> 		nvidia,elastic-limit = &lt;16&gt;;</div><div class='hunk'>@@ -1003,11 +1033,12 @@</div><div class='ctx'> 		nvidia,hsdiscon-level = &lt;5&gt;;</div><div class='ctx'> 		nvidia,xcvr-hsslew = &lt;12&gt;;</div><div class='ctx'> 		nvidia,has-utmi-pad-registers;</div><div class='add'>+		nvidia,pmc = &lt;&amp;tegra_pmc 0&gt;;</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	usb@7d004000 {</div><div class='del'>-		compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";</div><div class='add'>+		compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";</div><div class='ctx'> 		reg = &lt;0x0 0x7d004000 0x0 0x4000&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		phy_type = "utmi";</div><div class='hunk'>@@ -1023,6 +1054,7 @@</div><div class='ctx'> 		compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";</div><div class='ctx'> 		reg = &lt;0x0 0x7d004000 0x0 0x4000&gt;,</div><div class='ctx'> 		      &lt;0x0 0x7d000000 0x0 0x4000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		phy_type = "utmi";</div><div class='ctx'> 		clocks = &lt;&amp;tegra_car TEGRA124_CLK_USB2&gt;,</div><div class='ctx'> 			 &lt;&amp;tegra_car TEGRA124_CLK_PLL_U&gt;,</div><div class='hunk'>@@ -1030,6 +1062,7 @@</div><div class='ctx'> 		clock-names = "reg", "pll_u", "utmi-pads";</div><div class='ctx'> 		resets = &lt;&amp;tegra_car 58&gt;, &lt;&amp;tegra_car 22&gt;;</div><div class='ctx'> 		reset-names = "usb", "utmi-pads";</div><div class='add'>+		#phy-cells = &lt;0&gt;;</div><div class='ctx'> 		nvidia,hssync-start-delay = &lt;0&gt;;</div><div class='ctx'> 		nvidia,idle-wait-delay = &lt;17&gt;;</div><div class='ctx'> 		nvidia,elastic-limit = &lt;16&gt;;</div><div class='hunk'>@@ -1040,11 +1073,12 @@</div><div class='ctx'> 		nvidia,hssquelch-level = &lt;2&gt;;</div><div class='ctx'> 		nvidia,hsdiscon-level = &lt;5&gt;;</div><div class='ctx'> 		nvidia,xcvr-hsslew = &lt;12&gt;;</div><div class='add'>+		nvidia,pmc = &lt;&amp;tegra_pmc 1&gt;;</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	usb@7d008000 {</div><div class='del'>-		compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";</div><div class='add'>+		compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";</div><div class='ctx'> 		reg = &lt;0x0 0x7d008000 0x0 0x4000&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		phy_type = "utmi";</div><div class='hunk'>@@ -1060,6 +1094,7 @@</div><div class='ctx'> 		compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";</div><div class='ctx'> 		reg = &lt;0x0 0x7d008000 0x0 0x4000&gt;,</div><div class='ctx'> 		      &lt;0x0 0x7d000000 0x0 0x4000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		phy_type = "utmi";</div><div class='ctx'> 		clocks = &lt;&amp;tegra_car TEGRA124_CLK_USB3&gt;,</div><div class='ctx'> 			 &lt;&amp;tegra_car TEGRA124_CLK_PLL_U&gt;,</div><div class='hunk'>@@ -1067,6 +1102,7 @@</div><div class='ctx'> 		clock-names = "reg", "pll_u", "utmi-pads";</div><div class='ctx'> 		resets = &lt;&amp;tegra_car 59&gt;, &lt;&amp;tegra_car 22&gt;;</div><div class='ctx'> 		reset-names = "usb", "utmi-pads";</div><div class='add'>+		#phy-cells = &lt;0&gt;;</div><div class='ctx'> 		nvidia,hssync-start-delay = &lt;0&gt;;</div><div class='ctx'> 		nvidia,idle-wait-delay = &lt;17&gt;;</div><div class='ctx'> 		nvidia,elastic-limit = &lt;16&gt;;</div><div class='hunk'>@@ -1077,6 +1113,7 @@</div><div class='ctx'> 		nvidia,hssquelch-level = &lt;2&gt;;</div><div class='ctx'> 		nvidia,hsdiscon-level = &lt;5&gt;;</div><div class='ctx'> 		nvidia,xcvr-hsslew = &lt;12&gt;;</div><div class='add'>+		nvidia,pmc = &lt;&amp;tegra_pmc 2&gt;;</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -1086,17 +1123,133 @@</div><div class='ctx'> </div><div class='ctx'> 		cpu@0 {</div><div class='ctx'> 			device_type = "cpu";</div><div class='del'>-			compatible = "nvidia,denver";</div><div class='add'>+			compatible = "nvidia,tegra132-denver";</div><div class='ctx'> 			reg = &lt;0&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cpu@1 {</div><div class='ctx'> 			device_type = "cpu";</div><div class='del'>-			compatible = "nvidia,denver";</div><div class='add'>+			compatible = "nvidia,tegra132-denver";</div><div class='ctx'> 			reg = &lt;1&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	thermal-zones {</div><div class='add'>+		cpu-thermal {</div><div class='add'>+			polling-delay-passive = &lt;1000&gt;;</div><div class='add'>+			polling-delay = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors =</div><div class='add'>+				&lt;&amp;soctherm TEGRA124_SOCTHERM_SENSOR_CPU&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu_shutdown_trip {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_throttle_trip: throttle-trip {</div><div class='add'>+					temperature = &lt;102000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu_throttle_trip&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;throttle_heavy 1 1&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mem-thermal {</div><div class='add'>+			polling-delay-passive = &lt;0&gt;;</div><div class='add'>+			polling-delay = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors =</div><div class='add'>+				&lt;&amp;soctherm TEGRA124_SOCTHERM_SENSOR_MEM&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				mem_shutdown_trip {</div><div class='add'>+					temperature = &lt;101000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+				mem_throttle_trip {</div><div class='add'>+					temperature = &lt;99000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				/*</div><div class='add'>+				 * There are currently no cooling maps,</div><div class='add'>+				 * because there are no cooling devices.</div><div class='add'>+				 */</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu-thermal {</div><div class='add'>+			polling-delay-passive = &lt;1000&gt;;</div><div class='add'>+			polling-delay = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors =</div><div class='add'>+				&lt;&amp;soctherm TEGRA124_SOCTHERM_SENSOR_GPU&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				gpu_shutdown_trip {</div><div class='add'>+					temperature = &lt;101000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpu_throttle_trip: throttle-trip {</div><div class='add'>+					temperature = &lt;99000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;gpu_throttle_trip&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;throttle_heavy 1 1&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pllx-thermal {</div><div class='add'>+			polling-delay-passive = &lt;0&gt;;</div><div class='add'>+			polling-delay = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors =</div><div class='add'>+				&lt;&amp;soctherm TEGRA124_SOCTHERM_SENSOR_PLLX&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				pllx_shutdown_trip {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+				pllx_throttle_trip {</div><div class='add'>+					temperature = &lt;99000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				/*</div><div class='add'>+				 * There are currently no cooling maps,</div><div class='add'>+				 * because there are no cooling devices.</div><div class='add'>+				 */</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	timer {</div><div class='ctx'> 		compatible = "arm,armv7-timer";</div><div class='ctx'> 		interrupts = &lt;GIC_PPI 13</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts<br/>index 1af7f9ffb7b6..8b3736cee323 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts</a></div><div class='hunk'>@@ -10,9 +10,2183 @@</div><div class='ctx'> 	model = "NVIDIA Jetson TX2 Developer Kit";</div><div class='ctx'> 	compatible = "nvidia,p2771-0000", "nvidia,tegra186";</div><div class='ctx'> </div><div class='del'>-	aconnect {</div><div class='add'>+	aconnect@2900000 {</div><div class='ctx'> 		status = "okay";</div><div class='ctx'> </div><div class='add'>+		ahub@2900800 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			i2s@2901000 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						i2s1_cif_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_i2s1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					i2s1_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						i2s1_dap_ep: endpoint {</div><div class='add'>+							dai-format = "i2s";</div><div class='add'>+							/* Placeholder for external Codec */</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2s@2901100 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						i2s2_cif_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_i2s2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					i2s2_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						i2s2_dap_ep: endpoint {</div><div class='add'>+							dai-format = "i2s";</div><div class='add'>+							/* Placeholder for external Codec */</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2s@2901200 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						i2s3_cif_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_i2s3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					i2s3_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						i2s3_dap_ep: endpoint {</div><div class='add'>+							dai-format = "i2s";</div><div class='add'>+							/* Placeholder for external Codec */</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2s@2901300 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						i2s4_cif_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_i2s4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					i2s4_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						i2s4_dap_ep: endpoint {</div><div class='add'>+							dai-format = "i2s";</div><div class='add'>+							/* Placeholder for external Codec */</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2s@2901400 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						i2s5_cif_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_i2s5_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					i2s5_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						i2s5_dap_ep: endpoint {</div><div class='add'>+							dai-format = "i2s";</div><div class='add'>+							/* Placeholder for external Codec */</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2s@2901500 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						i2s6_cif_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_i2s6_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					i2s6_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						i2s6_dap_ep: endpoint {</div><div class='add'>+							dai-format = "i2s";</div><div class='add'>+							/* Placeholder for external Codec */</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sfc@2902000 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						sfc1_cif_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_sfc1_in_ep&gt;;</div><div class='add'>+							convert-rate = &lt;44100&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					sfc1_out_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						sfc1_cif_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_sfc1_out_ep&gt;;</div><div class='add'>+							convert-rate = &lt;48000&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sfc@2902200 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						sfc2_cif_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_sfc2_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					sfc2_out_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						sfc2_cif_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_sfc2_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sfc@2902400 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						sfc3_cif_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_sfc3_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					sfc3_out_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						sfc3_cif_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_sfc3_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sfc@2902600 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						sfc4_cif_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_sfc4_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					sfc4_out_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						sfc4_cif_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_sfc4_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			amx@2903000 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						amx1_in1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_amx1_in1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						amx1_in2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_amx1_in2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@2 {</div><div class='add'>+						reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+						amx1_in3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_amx1_in3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@3 {</div><div class='add'>+						reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+						amx1_in4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_amx1_in4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					amx1_out_port: port@4 {</div><div class='add'>+						reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+						amx1_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_amx1_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			amx@2903100 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						amx2_in1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_amx2_in1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						amx2_in2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_amx2_in2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					amx2_in3_port: port@2 {</div><div class='add'>+						reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+						amx2_in3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_amx2_in3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					amx2_in4_port: port@3 {</div><div class='add'>+						reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+						amx2_in4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_amx2_in4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					amx2_out_port: port@4 {</div><div class='add'>+						reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+						amx2_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_amx2_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			amx@2903200 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						amx3_in1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_amx3_in1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						amx3_in2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_amx3_in2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@2 {</div><div class='add'>+						reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+						amx3_in3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_amx3_in3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@3 {</div><div class='add'>+						reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+						amx3_in4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_amx3_in4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					amx3_out_port: port@4 {</div><div class='add'>+						reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+						amx3_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_amx3_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			amx@2903300 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						amx4_in1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_amx4_in1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						amx4_in2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_amx4_in2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@2 {</div><div class='add'>+						reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+						amx4_in3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_amx4_in3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@3 {</div><div class='add'>+						reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+						amx4_in4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_amx4_in4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					amx4_out_port: port@4 {</div><div class='add'>+						reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+						amx4_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_amx4_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			adx@2903800 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						adx1_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_adx1_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					adx1_out1_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						adx1_out1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_adx1_out1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					adx1_out2_port: port@2 {</div><div class='add'>+						reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+						adx1_out2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_adx1_out2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					adx1_out3_port: port@3 {</div><div class='add'>+						reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+						adx1_out3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_adx1_out3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					adx1_out4_port: port@4 {</div><div class='add'>+						reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+						adx1_out4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_adx1_out4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			adx@2903900 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						adx2_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_adx2_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					adx2_out1_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						adx2_out1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_adx2_out1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					adx2_out2_port: port@2 {</div><div class='add'>+						reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+						adx2_out2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_adx2_out2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					adx2_out3_port: port@3 {</div><div class='add'>+						reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+						adx2_out3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_adx2_out3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					adx2_out4_port: port@4 {</div><div class='add'>+						reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+						adx2_out4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_adx2_out4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			adx@2903a00 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						adx3_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_adx3_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					adx3_out1_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						adx3_out1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_adx3_out1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					adx3_out2_port: port@2 {</div><div class='add'>+						reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+						adx3_out2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_adx3_out2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					adx3_out3_port: port@3 {</div><div class='add'>+						reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+						adx3_out3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_adx3_out3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					adx3_out4_port: port@4 {</div><div class='add'>+						reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+						adx3_out4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_adx3_out4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			adx@2903b00 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						adx4_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_adx4_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					adx4_out1_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						adx4_out1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_adx4_out1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					adx4_out2_port: port@2 {</div><div class='add'>+						reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+						adx4_out2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_adx4_out2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					adx4_out3_port: port@3 {</div><div class='add'>+						reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+						adx4_out3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_adx4_out3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					adx4_out4_port: port@4 {</div><div class='add'>+						reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+						adx4_out4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_adx4_out4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			dmic@2904000 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						dmic1_cif_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_dmic1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					dmic1_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						dmic1_dap_ep: endpoint {</div><div class='add'>+							/* Place holder for external Codec */</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			dmic@2904100 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						dmic2_cif_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_dmic2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					dmic2_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						dmic2_dap_ep: endpoint {</div><div class='add'>+							/* Place holder for external Codec */</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			dmic@2904200 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						dmic3_cif_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_dmic3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					dmic3_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						dmic3_dap_ep: endpoint {</div><div class='add'>+							/* Place holder for external Codec */</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			dspk@2905000 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						dspk1_cif_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_dspk1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					dspk1_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						dspk1_dap_ep: endpoint {</div><div class='add'>+							/* Place holder for external Codec */</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			dspk@2905100 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						dspk2_cif_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_dspk2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					dspk2_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						dspk2_dap_ep: endpoint {</div><div class='add'>+							/* Place holder for external Codec */</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			processing-engine@2908000 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0x0&gt;;</div><div class='add'>+</div><div class='add'>+						ope1_cif_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_ope1_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					ope1_out_port: port@1 {</div><div class='add'>+						reg = &lt;0x1&gt;;</div><div class='add'>+</div><div class='add'>+						ope1_cif_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_ope1_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mvc@290a000 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						mvc1_cif_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mvc1_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					mvc1_out_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						mvc1_cif_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mvc1_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mvc@290a200 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						mvc2_cif_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mvc2_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					mvc2_out_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						mvc2_cif_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mvc2_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			amixer@290bb00 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0x0&gt;;</div><div class='add'>+</div><div class='add'>+						mixer_in1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mixer_in1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;0x1&gt;;</div><div class='add'>+</div><div class='add'>+						mixer_in2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mixer_in2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@2 {</div><div class='add'>+						reg = &lt;0x2&gt;;</div><div class='add'>+</div><div class='add'>+						mixer_in3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mixer_in3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@3 {</div><div class='add'>+						reg = &lt;0x3&gt;;</div><div class='add'>+</div><div class='add'>+						mixer_in4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mixer_in4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@4 {</div><div class='add'>+						reg = &lt;0x4&gt;;</div><div class='add'>+</div><div class='add'>+						mixer_in5_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mixer_in5_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@5 {</div><div class='add'>+						reg = &lt;0x5&gt;;</div><div class='add'>+</div><div class='add'>+						mixer_in6_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mixer_in6_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@6 {</div><div class='add'>+						reg = &lt;0x6&gt;;</div><div class='add'>+</div><div class='add'>+						mixer_in7_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mixer_in7_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@7 {</div><div class='add'>+						reg = &lt;0x7&gt;;</div><div class='add'>+</div><div class='add'>+						mixer_in8_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mixer_in8_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@8 {</div><div class='add'>+						reg = &lt;0x8&gt;;</div><div class='add'>+</div><div class='add'>+						mixer_in9_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mixer_in9_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@9 {</div><div class='add'>+						reg = &lt;0x9&gt;;</div><div class='add'>+</div><div class='add'>+						mixer_in10_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mixer_in10_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					mixer_out1_port: port@a {</div><div class='add'>+						reg = &lt;0xa&gt;;</div><div class='add'>+</div><div class='add'>+						mixer_out1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mixer_out1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					mixer_out2_port: port@b {</div><div class='add'>+						reg = &lt;0xb&gt;;</div><div class='add'>+</div><div class='add'>+						mixer_out2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mixer_out2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					mixer_out3_port: port@c {</div><div class='add'>+						reg = &lt;0xc&gt;;</div><div class='add'>+</div><div class='add'>+						mixer_out3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mixer_out3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					mixer_out4_port: port@d {</div><div class='add'>+						reg = &lt;0xd&gt;;</div><div class='add'>+</div><div class='add'>+						mixer_out4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mixer_out4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					mixer_out5_port: port@e {</div><div class='add'>+						reg = &lt;0xe&gt;;</div><div class='add'>+</div><div class='add'>+						mixer_out5_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mixer_out5_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			admaif@290f000 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					admaif0_port: port@0 {</div><div class='add'>+						reg = &lt;0x0&gt;;</div><div class='add'>+</div><div class='add'>+						admaif0_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif0_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					admaif1_port: port@1 {</div><div class='add'>+						reg = &lt;0x1&gt;;</div><div class='add'>+</div><div class='add'>+						admaif1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					admaif2_port: port@2 {</div><div class='add'>+						reg = &lt;0x2&gt;;</div><div class='add'>+</div><div class='add'>+						admaif2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					admaif3_port: port@3 {</div><div class='add'>+						reg = &lt;0x3&gt;;</div><div class='add'>+</div><div class='add'>+						admaif3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					admaif4_port: port@4 {</div><div class='add'>+						reg = &lt;0x4&gt;;</div><div class='add'>+</div><div class='add'>+						admaif4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					admaif5_port: port@5 {</div><div class='add'>+						reg = &lt;0x5&gt;;</div><div class='add'>+</div><div class='add'>+						admaif5_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif5_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					admaif6_port: port@6 {</div><div class='add'>+						reg = &lt;0x6&gt;;</div><div class='add'>+</div><div class='add'>+						admaif6_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif6_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					admaif7_port: port@7 {</div><div class='add'>+						reg = &lt;0x7&gt;;</div><div class='add'>+</div><div class='add'>+						admaif7_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif7_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					admaif8_port: port@8 {</div><div class='add'>+						reg = &lt;0x8&gt;;</div><div class='add'>+</div><div class='add'>+						admaif8_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif8_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					admaif9_port: port@9 {</div><div class='add'>+						reg = &lt;0x9&gt;;</div><div class='add'>+</div><div class='add'>+						admaif9_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif9_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					admaif10_port: port@a {</div><div class='add'>+						reg = &lt;0xa&gt;;</div><div class='add'>+</div><div class='add'>+						admaif10_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif10_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					admaif11_port: port@b {</div><div class='add'>+						reg = &lt;0xb&gt;;</div><div class='add'>+</div><div class='add'>+						admaif11_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif11_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					admaif12_port: port@c {</div><div class='add'>+						reg = &lt;0xc&gt;;</div><div class='add'>+</div><div class='add'>+						admaif12_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif12_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					admaif13_port: port@d {</div><div class='add'>+						reg = &lt;0xd&gt;;</div><div class='add'>+</div><div class='add'>+						admaif13_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif13_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					admaif14_port: port@e {</div><div class='add'>+						reg = &lt;0xe&gt;;</div><div class='add'>+</div><div class='add'>+						admaif14_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif14_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					admaif15_port: port@f {</div><div class='add'>+						reg = &lt;0xf&gt;;</div><div class='add'>+</div><div class='add'>+						admaif15_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif15_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					admaif16_port: port@10 {</div><div class='add'>+						reg = &lt;0x10&gt;;</div><div class='add'>+</div><div class='add'>+						admaif16_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif16_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					admaif17_port: port@11 {</div><div class='add'>+						reg = &lt;0x11&gt;;</div><div class='add'>+</div><div class='add'>+						admaif17_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif17_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					admaif18_port: port@12 {</div><div class='add'>+						reg = &lt;0x12&gt;;</div><div class='add'>+</div><div class='add'>+						admaif18_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif18_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					admaif19_port: port@13 {</div><div class='add'>+						reg = &lt;0x13&gt;;</div><div class='add'>+</div><div class='add'>+						admaif19_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif19_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			asrc@2910000 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0x0&gt;;</div><div class='add'>+</div><div class='add'>+						asrc_in1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_asrc_in1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;0x1&gt;;</div><div class='add'>+</div><div class='add'>+						asrc_in2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_asrc_in2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@2 {</div><div class='add'>+						reg = &lt;0x2&gt;;</div><div class='add'>+</div><div class='add'>+						asrc_in3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_asrc_in3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@3 {</div><div class='add'>+						reg = &lt;0x3&gt;;</div><div class='add'>+</div><div class='add'>+						asrc_in4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_asrc_in4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@4 {</div><div class='add'>+						reg = &lt;0x4&gt;;</div><div class='add'>+</div><div class='add'>+						asrc_in5_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_asrc_in5_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@5 {</div><div class='add'>+						reg = &lt;0x5&gt;;</div><div class='add'>+</div><div class='add'>+						asrc_in6_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_asrc_in6_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@6 {</div><div class='add'>+						reg = &lt;0x6&gt;;</div><div class='add'>+</div><div class='add'>+						asrc_in7_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_asrc_in7_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					asrc_out1_port: port@7 {</div><div class='add'>+						reg = &lt;0x7&gt;;</div><div class='add'>+</div><div class='add'>+						asrc_out1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_asrc_out1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					asrc_out2_port: port@8 {</div><div class='add'>+						reg = &lt;0x8&gt;;</div><div class='add'>+</div><div class='add'>+						asrc_out2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_asrc_out2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					asrc_out3_port: port@9 {</div><div class='add'>+						reg = &lt;0x9&gt;;</div><div class='add'>+</div><div class='add'>+						asrc_out3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_asrc_out3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					asrc_out4_port: port@a {</div><div class='add'>+						reg = &lt;0xa&gt;;</div><div class='add'>+</div><div class='add'>+						asrc_out4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_asrc_out4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					asrc_out5_port: port@b {</div><div class='add'>+						reg = &lt;0xb&gt;;</div><div class='add'>+</div><div class='add'>+						asrc_out5_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_asrc_out5_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					asrc_out6_port: port@c {</div><div class='add'>+						reg = &lt;0xc&gt;;</div><div class='add'>+</div><div class='add'>+						asrc_out6_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_asrc_out6_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0x0&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif0_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif0_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;0x1&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif1_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif1_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@2 {</div><div class='add'>+					reg = &lt;0x2&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif2_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif2_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@3 {</div><div class='add'>+					reg = &lt;0x3&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif3_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif3_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@4 {</div><div class='add'>+					reg = &lt;0x4&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif4_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif4_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@5 {</div><div class='add'>+					reg = &lt;0x5&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif5_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif5_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@6 {</div><div class='add'>+					reg = &lt;0x6&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif6_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif6_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@7 {</div><div class='add'>+					reg = &lt;0x7&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif7_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif7_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@8 {</div><div class='add'>+					reg = &lt;0x8&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif8_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif8_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@9 {</div><div class='add'>+					reg = &lt;0x9&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif9_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif9_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@a {</div><div class='add'>+					reg = &lt;0xa&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif10_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif10_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@b {</div><div class='add'>+					reg = &lt;0xb&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif11_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif11_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@c {</div><div class='add'>+					reg = &lt;0xc&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif12_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif12_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@d {</div><div class='add'>+					reg = &lt;0xd&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif13_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif13_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@e {</div><div class='add'>+					reg = &lt;0xe&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif14_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif14_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@f {</div><div class='add'>+					reg = &lt;0xf&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif15_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif15_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@10 {</div><div class='add'>+					reg = &lt;0x10&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif16_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif16_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@11 {</div><div class='add'>+					reg = &lt;0x11&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif17_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif17_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@12 {</div><div class='add'>+					reg = &lt;0x12&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif18_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif18_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@13 {</div><div class='add'>+					reg = &lt;0x13&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif19_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif19_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_i2s1_port: port@14 {</div><div class='add'>+					reg = &lt;0x14&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_i2s1_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;i2s1_cif_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_i2s2_port: port@15 {</div><div class='add'>+					reg = &lt;0x15&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_i2s2_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;i2s2_cif_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_i2s3_port: port@16 {</div><div class='add'>+					reg = &lt;0x16&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_i2s3_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;i2s3_cif_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_i2s4_port: port@17 {</div><div class='add'>+					reg = &lt;0x17&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_i2s4_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;i2s4_cif_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_i2s5_port: port@18 {</div><div class='add'>+					reg = &lt;0x18&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_i2s5_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;i2s5_cif_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_i2s6_port: port@19 {</div><div class='add'>+					reg = &lt;0x19&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_i2s6_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;i2s6_cif_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_dmic1_port: port@1a {</div><div class='add'>+					reg = &lt;0x1a&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_dmic1_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dmic1_cif_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_dmic2_port: port@1b {</div><div class='add'>+					reg = &lt;0x1b&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_dmic2_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dmic2_cif_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_dmic3_port: port@1c {</div><div class='add'>+					reg = &lt;0x1c&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_dmic3_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dmic3_cif_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_dspk1_port: port@1e {</div><div class='add'>+					reg = &lt;0x1e&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_dspk1_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dspk1_cif_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_dspk2_port: port@1f {</div><div class='add'>+					reg = &lt;0x1f&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_dspk2_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dspk2_cif_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_sfc1_in_port: port@20 {</div><div class='add'>+					reg = &lt;0x20&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_sfc1_in_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;sfc1_cif_in_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@21 {</div><div class='add'>+					reg = &lt;0x21&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_sfc1_out_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;sfc1_cif_out_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_sfc2_in_port: port@22 {</div><div class='add'>+					reg = &lt;0x22&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_sfc2_in_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;sfc2_cif_in_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@23 {</div><div class='add'>+					reg = &lt;0x23&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_sfc2_out_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;sfc2_cif_out_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_sfc3_in_port: port@24 {</div><div class='add'>+					reg = &lt;0x24&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_sfc3_in_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;sfc3_cif_in_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@25 {</div><div class='add'>+					reg = &lt;0x25&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_sfc3_out_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;sfc3_cif_out_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_sfc4_in_port: port@26 {</div><div class='add'>+					reg = &lt;0x26&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_sfc4_in_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;sfc4_cif_in_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@27 {</div><div class='add'>+					reg = &lt;0x27&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_sfc4_out_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;sfc4_cif_out_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_mvc1_in_port: port@28 {</div><div class='add'>+					reg = &lt;0x28&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mvc1_in_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mvc1_cif_in_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@29 {</div><div class='add'>+					reg = &lt;0x29&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mvc1_out_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mvc1_cif_out_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_mvc2_in_port: port@2a {</div><div class='add'>+					reg = &lt;0x2a&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mvc2_in_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mvc2_cif_in_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@2b {</div><div class='add'>+					reg = &lt;0x2b&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mvc2_out_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mvc2_cif_out_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_amx1_in1_port: port@2c {</div><div class='add'>+					reg = &lt;0x2c&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_amx1_in1_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;amx1_in1_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_amx1_in2_port: port@2d {</div><div class='add'>+					reg = &lt;0x2d&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_amx1_in2_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;amx1_in2_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_amx1_in3_port: port@2e {</div><div class='add'>+					reg = &lt;0x2e&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_amx1_in3_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;amx1_in3_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_amx1_in4_port: port@2f {</div><div class='add'>+					reg = &lt;0x2f&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_amx1_in4_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;amx1_in4_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@30 {</div><div class='add'>+					reg = &lt;0x30&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_amx1_out_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;amx1_out_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_amx2_in1_port: port@31 {</div><div class='add'>+					reg = &lt;0x31&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_amx2_in1_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;amx2_in1_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_amx2_in2_port: port@32 {</div><div class='add'>+					reg = &lt;0x32&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_amx2_in2_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;amx2_in2_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_amx2_in3_port: port@33 {</div><div class='add'>+					reg = &lt;0x33&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_amx2_in3_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;amx2_in3_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_amx2_in4_port: port@34 {</div><div class='add'>+					reg = &lt;0x34&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_amx2_in4_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;amx2_in4_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@35 {</div><div class='add'>+					reg = &lt;0x35&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_amx2_out_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;amx2_out_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_amx3_in1_port: port@36 {</div><div class='add'>+					reg = &lt;0x36&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_amx3_in1_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;amx3_in1_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_amx3_in2_port: port@37 {</div><div class='add'>+					reg = &lt;0x37&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_amx3_in2_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;amx3_in2_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_amx3_in3_port: port@38 {</div><div class='add'>+					reg = &lt;0x38&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_amx3_in3_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;amx3_in3_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_amx3_in4_port: port@39 {</div><div class='add'>+					reg = &lt;0x39&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_amx3_in4_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;amx3_in4_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@3a {</div><div class='add'>+					reg = &lt;0x3a&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_amx3_out_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;amx3_out_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_amx4_in1_port: port@3b {</div><div class='add'>+					reg = &lt;0x3b&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_amx4_in1_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;amx4_in1_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_amx4_in2_port: port@3c {</div><div class='add'>+					reg = &lt;0x3c&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_amx4_in2_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;amx4_in2_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_amx4_in3_port: port@3d {</div><div class='add'>+					reg = &lt;0x3d&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_amx4_in3_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;amx4_in3_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_amx4_in4_port: port@3e {</div><div class='add'>+					reg = &lt;0x3e&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_amx4_in4_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;amx4_in4_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@3f {</div><div class='add'>+					reg = &lt;0x3f&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_amx4_out_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;amx4_out_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_adx1_in_port: port@40 {</div><div class='add'>+					reg = &lt;0x40&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_adx1_in_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;adx1_in_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@41 {</div><div class='add'>+					reg = &lt;0x41&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_adx1_out1_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;adx1_out1_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@42 {</div><div class='add'>+					reg = &lt;0x42&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_adx1_out2_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;adx1_out2_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@43 {</div><div class='add'>+					reg = &lt;0x43&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_adx1_out3_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;adx1_out3_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@44 {</div><div class='add'>+					reg = &lt;0x44&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_adx1_out4_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;adx1_out4_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_adx2_in_port: port@45 {</div><div class='add'>+					reg = &lt;0x45&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_adx2_in_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;adx2_in_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@46 {</div><div class='add'>+					reg = &lt;0x46&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_adx2_out1_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;adx2_out1_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@47 {</div><div class='add'>+					reg = &lt;0x47&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_adx2_out2_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;adx2_out2_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@48 {</div><div class='add'>+					reg = &lt;0x48&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_adx2_out3_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;adx2_out3_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@49 {</div><div class='add'>+					reg = &lt;0x49&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_adx2_out4_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;adx2_out4_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_adx3_in_port: port@4a {</div><div class='add'>+					reg = &lt;0x4a&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_adx3_in_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;adx3_in_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@4b {</div><div class='add'>+					reg = &lt;0x4b&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_adx3_out1_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;adx3_out1_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@4c {</div><div class='add'>+					reg = &lt;0x4c&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_adx3_out2_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;adx3_out2_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@4d {</div><div class='add'>+					reg = &lt;0x4d&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_adx3_out3_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;adx3_out3_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@4e {</div><div class='add'>+					reg = &lt;0x4e&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_adx3_out4_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;adx3_out4_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_adx4_in_port: port@4f {</div><div class='add'>+					reg = &lt;0x4f&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_adx4_in_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;adx4_in_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@50 {</div><div class='add'>+					reg = &lt;0x50&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_adx4_out1_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;adx4_out1_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@51 {</div><div class='add'>+					reg = &lt;0x51&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_adx4_out2_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;adx4_out2_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@52 {</div><div class='add'>+					reg = &lt;0x52&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_adx4_out3_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;adx4_out3_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@53 {</div><div class='add'>+					reg = &lt;0x53&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_adx4_out4_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;adx4_out4_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_mixer_in1_port: port@54 {</div><div class='add'>+					reg = &lt;0x54&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in1_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mixer_in1_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_mixer_in2_port: port@55 {</div><div class='add'>+					reg = &lt;0x55&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in2_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mixer_in2_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_mixer_in3_port: port@56 {</div><div class='add'>+					reg = &lt;0x56&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in3_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mixer_in3_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_mixer_in4_port: port@57 {</div><div class='add'>+					reg = &lt;0x57&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in4_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mixer_in4_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_mixer_in5_port: port@58 {</div><div class='add'>+					reg = &lt;0x58&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in5_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mixer_in5_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_mixer_in6_port: port@59 {</div><div class='add'>+					reg = &lt;0x59&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in6_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mixer_in6_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_mixer_in7_port: port@5a {</div><div class='add'>+					reg = &lt;0x5a&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in7_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mixer_in7_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_mixer_in8_port: port@5b {</div><div class='add'>+					reg = &lt;0x5b&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in8_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mixer_in8_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_mixer_in9_port: port@5c {</div><div class='add'>+					reg = &lt;0x5c&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in9_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mixer_in9_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_mixer_in10_port: port@5d {</div><div class='add'>+					reg = &lt;0x5d&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in10_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mixer_in10_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@5e {</div><div class='add'>+					reg = &lt;0x5e&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mixer_out1_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mixer_out1_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@5f {</div><div class='add'>+					reg = &lt;0x5f&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mixer_out2_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mixer_out2_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@60 {</div><div class='add'>+					reg = &lt;0x60&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mixer_out3_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mixer_out3_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@61 {</div><div class='add'>+					reg = &lt;0x61&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mixer_out4_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mixer_out4_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@62 {</div><div class='add'>+					reg = &lt;0x62&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mixer_out5_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mixer_out5_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_asrc_in1_port: port@63 {</div><div class='add'>+					reg = &lt;0x63&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_asrc_in1_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;asrc_in1_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@64 {</div><div class='add'>+					reg = &lt;0x64&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_asrc_out1_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;asrc_out1_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_asrc_in2_port: port@65 {</div><div class='add'>+					reg = &lt;0x65&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_asrc_in2_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;asrc_in2_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@66 {</div><div class='add'>+					reg = &lt;0x66&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_asrc_out2_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;asrc_out2_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_asrc_in3_port: port@67 {</div><div class='add'>+					reg = &lt;0x67&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_asrc_in3_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;asrc_in3_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@68 {</div><div class='add'>+					reg = &lt;0x68&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_asrc_out3_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;asrc_out3_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_asrc_in4_port: port@69 {</div><div class='add'>+					reg = &lt;0x69&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_asrc_in4_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;asrc_in4_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@6a {</div><div class='add'>+					reg = &lt;0x6a&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_asrc_out4_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;asrc_out4_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_asrc_in5_port: port@6b {</div><div class='add'>+					reg = &lt;0x6b&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_asrc_in5_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;asrc_in5_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@6c {</div><div class='add'>+					reg = &lt;0x6c&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_asrc_out5_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;asrc_out5_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_asrc_in6_port: port@6d {</div><div class='add'>+					reg = &lt;0x6d&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_asrc_in6_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;asrc_in6_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@6e {</div><div class='add'>+					reg = &lt;0x6e&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_asrc_out6_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;asrc_out6_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_asrc_in7_port: port@6f {</div><div class='add'>+					reg = &lt;0x6f&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_asrc_in7_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;asrc_in7_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_ope1_in_port: port@70 {</div><div class='add'>+					reg = &lt;0x70&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_ope1_in_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ope1_cif_in_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@71 {</div><div class='add'>+					reg = &lt;0x71&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_ope1_out_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ope1_cif_out_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		dma-controller@2930000 {</div><div class='ctx'> 			status = "okay";</div><div class='ctx'> 		};</div><div class='hunk'>@@ -29,19 +2203,19 @@</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> </div><div class='del'>-			channel@0 {</div><div class='add'>+			input@0 {</div><div class='ctx'> 				reg = &lt;0x0&gt;;</div><div class='ctx'> 				label = "VDD_MUX";</div><div class='ctx'> 				shunt-resistor-micro-ohms = &lt;20000&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			channel@1 {</div><div class='add'>+			input@1 {</div><div class='ctx'> 				reg = &lt;0x1&gt;;</div><div class='ctx'> 				label = "VDD_5V0_IO_SYS";</div><div class='ctx'> 				shunt-resistor-micro-ohms = &lt;5000&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			channel@2 {</div><div class='add'>+			input@2 {</div><div class='ctx'> 				reg = &lt;0x2&gt;;</div><div class='ctx'> 				label = "VDD_3V3_SYS";</div><div class='ctx'> 				shunt-resistor-micro-ohms = &lt;10000&gt;;</div><div class='hunk'>@@ -54,19 +2228,19 @@</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> </div><div class='del'>-			channel@0 {</div><div class='add'>+			input@0 {</div><div class='ctx'> 				reg = &lt;0x0&gt;;</div><div class='ctx'> 				label = "VDD_3V3_IO_SLP";</div><div class='ctx'> 				shunt-resistor-micro-ohms = &lt;10000&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			channel@1 {</div><div class='add'>+			input@1 {</div><div class='ctx'> 				reg = &lt;0x1&gt;;</div><div class='ctx'> 				label = "VDD_1V8_IO";</div><div class='ctx'> 				shunt-resistor-micro-ohms = &lt;10000&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			channel@2 {</div><div class='add'>+			input@2 {</div><div class='ctx'> 				reg = &lt;0x2&gt;;</div><div class='ctx'> 				label = "VDD_M2_IN";</div><div class='ctx'> 				shunt-resistor-micro-ohms = &lt;10000&gt;;</div><div class='hunk'>@@ -103,14 +2277,18 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	/* SDMMC1 (SD/MMC) */</div><div class='del'>-	sdhci@3400000 {</div><div class='add'>+	mmc@3400000 {</div><div class='ctx'> 		status = "okay";</div><div class='ctx'> </div><div class='ctx'> 		vmmc-supply = &lt;&amp;vdd_sd&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	sata@3507000 {</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	hda@3510000 {</div><div class='del'>-		nvidia,model = "jetson-tx2-hda";</div><div class='add'>+		nvidia,model = "NVIDIA Jetson TX2 HDA";</div><div class='ctx'> 		status = "okay";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -119,10 +2297,6 @@</div><div class='ctx'> </div><div class='ctx'> 		avdd-pll-erefeut-supply = &lt;&amp;vdd_1v8_pll&gt;;</div><div class='ctx'> 		avdd-usb-supply = &lt;&amp;vdd_3v3_sys&gt;;</div><div class='del'>-		dvdd-pex-supply = &lt;&amp;vdd_pex&gt;;</div><div class='del'>-		dvdd-pex-pll-supply = &lt;&amp;vdd_pex&gt;;</div><div class='del'>-		hvdd-pex-supply = &lt;&amp;vdd_1v8&gt;;</div><div class='del'>-		hvdd-pex-pll-supply = &lt;&amp;vdd_1v8&gt;;</div><div class='ctx'> 		vclamp-usb-supply = &lt;&amp;vdd_1v8&gt;;</div><div class='ctx'> 		vddio-hsic-supply = &lt;&amp;gnd&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -175,19 +2349,18 @@</div><div class='ctx'> 				status = "okay";</div><div class='ctx'> 				mode = "otg";</div><div class='ctx'> 				vbus-supply = &lt;&amp;vdd_usb0&gt;;</div><div class='del'>-</div><div class='ctx'> 				usb-role-switch;</div><div class='add'>+</div><div class='ctx'> 				connector {</div><div class='del'>-					compatible = "usb-b-connector",</div><div class='del'>-						     "gpio-usb-b-connector";</div><div class='add'>+					compatible = "gpio-usb-b-connector",</div><div class='add'>+						     "usb-b-connector";</div><div class='ctx'> 					label = "micro-USB";</div><div class='ctx'> 					type = "micro";</div><div class='del'>-					vbus-gpio = &lt;&amp;gpio</div><div class='del'>-						     TEGRA186_MAIN_GPIO(X, 7)</div><div class='del'>-						     GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-					id-gpio = &lt;&amp;pmic 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+					vbus-gpios = &lt;&amp;gpio</div><div class='add'>+						      TEGRA186_MAIN_GPIO(X, 7)</div><div class='add'>+						      GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+					id-gpios = &lt;&amp;pmic 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 				};</div><div class='del'>-</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			usb2-1 {</div><div class='hunk'>@@ -199,6 +2372,7 @@</div><div class='ctx'> </div><div class='ctx'> 			usb3-0 {</div><div class='ctx'> 				nvidia,usb2-companion = &lt;1&gt;;</div><div class='add'>+				vbus-supply = &lt;&amp;vdd_usb1&gt;;</div><div class='ctx'> 				status = "okay";</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='hunk'>@@ -220,20 +2394,31 @@</div><div class='ctx'> 		phy-names = "usb2-0";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	cec@3960000 {</div><div class='add'>+		status = "okay";</div><div class='add'>+</div><div class='add'>+		hdmi-phandle = &lt;&amp;sor1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	i2c@c250000 {</div><div class='ctx'> 		/* carrier board ID EEPROM */</div><div class='ctx'> 		eeprom@57 {</div><div class='ctx'> 			compatible = "atmel,24c02";</div><div class='ctx'> 			reg = &lt;0x57&gt;;</div><div class='ctx'> </div><div class='add'>+			label = "system";</div><div class='ctx'> 			vcc-supply = &lt;&amp;vdd_1v8&gt;;</div><div class='del'>-			address-bits = &lt;8&gt;;</div><div class='del'>-			page-size = &lt;8&gt;;</div><div class='add'>+			address-width = &lt;8&gt;;</div><div class='add'>+			pagesize = &lt;8&gt;;</div><div class='ctx'> 			size = &lt;256&gt;;</div><div class='ctx'> 			read-only;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	pwm@c340000 {</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	pcie@10003000 {</div><div class='ctx'> 		status = "okay";</div><div class='ctx'> </div><div class='hunk'>@@ -286,8 +2471,8 @@</div><div class='ctx'> 		sor@15580000 {</div><div class='ctx'> 			status = "okay";</div><div class='ctx'> </div><div class='del'>-			avdd-io-supply = &lt;&amp;vdd_hdmi_1v05&gt;;</div><div class='del'>-			vdd-pll-supply = &lt;&amp;vdd_1v8_ap&gt;;</div><div class='add'>+			avdd-io-hdmi-dp-supply = &lt;&amp;vdd_hdmi_1v05&gt;;</div><div class='add'>+			vdd-hdmi-dp-pll-supply = &lt;&amp;vdd_1v8_ap&gt;;</div><div class='ctx'> 			hdmi-supply = &lt;&amp;vdd_hdmi&gt;;</div><div class='ctx'> </div><div class='ctx'> 			nvidia,ddc-i2c-bus = &lt;&amp;ddc&gt;;</div><div class='hunk'>@@ -303,7 +2488,7 @@</div><div class='ctx'> 	gpio-keys {</div><div class='ctx'> 		compatible = "gpio-keys";</div><div class='ctx'> </div><div class='del'>-		power {</div><div class='add'>+		key-power {</div><div class='ctx'> 			label = "Power";</div><div class='ctx'> 			gpios = &lt;&amp;gpio_aon TEGRA186_AON_GPIO(FF, 0)</div><div class='ctx'> 					   GPIO_ACTIVE_LOW&gt;;</div><div class='hunk'>@@ -314,81 +2499,241 @@</div><div class='ctx'> 			wakeup-source;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		volume-up {</div><div class='del'>-			label = "Volume Up";</div><div class='del'>-			gpios = &lt;&amp;gpio_aon TEGRA186_AON_GPIO(FF, 1)</div><div class='add'>+		key-volume-down {</div><div class='add'>+			label = "Volume Down";</div><div class='add'>+			gpios = &lt;&amp;gpio_aon TEGRA186_AON_GPIO(FF, 2)</div><div class='ctx'> 					   GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 			linux,input-type = &lt;EV_KEY&gt;;</div><div class='del'>-			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='ctx'> 			debounce-interval = &lt;10&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		volume-down {</div><div class='del'>-			label = "Volume Down";</div><div class='del'>-			gpios = &lt;&amp;gpio_aon TEGRA186_AON_GPIO(FF, 2)</div><div class='add'>+		key-volume-up {</div><div class='add'>+			label = "Volume Up";</div><div class='add'>+			gpios = &lt;&amp;gpio_aon TEGRA186_AON_GPIO(FF, 1)</div><div class='ctx'> 					   GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 			linux,input-type = &lt;EV_KEY&gt;;</div><div class='del'>-			linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='ctx'> 			debounce-interval = &lt;10&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	regulators {</div><div class='del'>-		vdd_sd: regulator@100 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;100&gt;;</div><div class='add'>+	fan: pwm-fan {</div><div class='add'>+		compatible = "pwm-fan";</div><div class='add'>+		pwms = &lt;&amp;pwm4 0 45334&gt;;</div><div class='add'>+		fan-supply = &lt;&amp;vdd_fan&gt;;</div><div class='ctx'> </div><div class='del'>-			regulator-name = "SD_CARD_SW_PWR";</div><div class='del'>-			regulator-min-microvolt = &lt;3300000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		/* cooling level (0, 1, 2, 3) - pwm inverted */</div><div class='add'>+		cooling-levels = &lt;255 128 64 0&gt;;</div><div class='add'>+		#cooling-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-			gpio = &lt;&amp;gpio TEGRA186_MAIN_GPIO(P, 6)</div><div class='del'>-				      GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			enable-active-high;</div><div class='add'>+	vdd_sd: regulator-vdd-sd {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "SD_CARD_SW_PWR";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='ctx'> </div><div class='del'>-			vin-supply = &lt;&amp;vdd_3v3_sys&gt;;</div><div class='del'>-		};</div><div class='add'>+		gpio = &lt;&amp;gpio TEGRA186_MAIN_GPIO(P, 6) GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='ctx'> </div><div class='del'>-		vdd_hdmi: regulator@101 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;101&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vdd_3v3_sys&gt;;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-			regulator-name = "VDD_HDMI_5V0";</div><div class='del'>-			regulator-min-microvolt = &lt;5000000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+	vdd_hdmi: regulator-vdd-hdmi {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_HDMI_5V0";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='ctx'> </div><div class='del'>-			gpio = &lt;&amp;exp1 14 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;exp1 14 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='ctx'> </div><div class='del'>-			vin-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='del'>-		};</div><div class='add'>+		vin-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_usb0: regulator-vdd-usb0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_USB0";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;gpio TEGRA186_MAIN_GPIO(L, 4) GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+</div><div class='add'>+		vin-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_usb1: regulator-vdd-usb1 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_USB1";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='ctx'> </div><div class='del'>-		vdd_usb0: regulator@102 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;102&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio TEGRA186_MAIN_GPIO(L, 5) GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+</div><div class='add'>+		vin-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-			regulator-name = "VDD_USB0";</div><div class='del'>-			regulator-min-microvolt = &lt;5000000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+	vdd_fan: regulator-vdd-fan {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_FAN";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='ctx'> </div><div class='del'>-			gpio = &lt;&amp;gpio TEGRA186_MAIN_GPIO(L, 4) GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;exp1 4 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> </div><div class='del'>-			vin-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "nvidia,tegra186-audio-graph-card";</div><div class='add'>+		status = "okay";</div><div class='add'>+</div><div class='add'>+		dais = /* FE */</div><div class='add'>+		       &lt;&amp;admaif0_port&gt;, &lt;&amp;admaif1_port&gt;, &lt;&amp;admaif2_port&gt;, &lt;&amp;admaif3_port&gt;,</div><div class='add'>+		       &lt;&amp;admaif4_port&gt;, &lt;&amp;admaif5_port&gt;, &lt;&amp;admaif6_port&gt;, &lt;&amp;admaif7_port&gt;,</div><div class='add'>+		       &lt;&amp;admaif8_port&gt;, &lt;&amp;admaif9_port&gt;, &lt;&amp;admaif10_port&gt;, &lt;&amp;admaif11_port&gt;,</div><div class='add'>+		       &lt;&amp;admaif12_port&gt;, &lt;&amp;admaif13_port&gt;, &lt;&amp;admaif14_port&gt;, &lt;&amp;admaif15_port&gt;,</div><div class='add'>+		       &lt;&amp;admaif16_port&gt;, &lt;&amp;admaif17_port&gt;, &lt;&amp;admaif18_port&gt;, &lt;&amp;admaif19_port&gt;,</div><div class='add'>+		       /* Router */</div><div class='add'>+		       &lt;&amp;xbar_i2s1_port&gt;, &lt;&amp;xbar_i2s2_port&gt;, &lt;&amp;xbar_i2s3_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_i2s4_port&gt;, &lt;&amp;xbar_i2s5_port&gt;, &lt;&amp;xbar_i2s6_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_dmic1_port&gt;, &lt;&amp;xbar_dmic2_port&gt;, &lt;&amp;xbar_dmic3_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_dspk1_port&gt;, &lt;&amp;xbar_dspk2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_sfc1_in_port&gt;, &lt;&amp;xbar_sfc2_in_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_sfc3_in_port&gt;, &lt;&amp;xbar_sfc4_in_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mvc1_in_port&gt;, &lt;&amp;xbar_mvc2_in_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx1_in1_port&gt;, &lt;&amp;xbar_amx1_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx1_in3_port&gt;, &lt;&amp;xbar_amx1_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx2_in1_port&gt;, &lt;&amp;xbar_amx2_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx2_in3_port&gt;, &lt;&amp;xbar_amx2_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx3_in1_port&gt;, &lt;&amp;xbar_amx3_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx3_in3_port&gt;, &lt;&amp;xbar_amx3_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx4_in1_port&gt;, &lt;&amp;xbar_amx4_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx4_in3_port&gt;, &lt;&amp;xbar_amx4_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_adx1_in_port&gt;, &lt;&amp;xbar_adx2_in_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_adx3_in_port&gt;, &lt;&amp;xbar_adx4_in_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mixer_in1_port&gt;, &lt;&amp;xbar_mixer_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mixer_in3_port&gt;, &lt;&amp;xbar_mixer_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mixer_in5_port&gt;, &lt;&amp;xbar_mixer_in6_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mixer_in7_port&gt;, &lt;&amp;xbar_mixer_in8_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mixer_in9_port&gt;, &lt;&amp;xbar_mixer_in10_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_asrc_in1_port&gt;, &lt;&amp;xbar_asrc_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_asrc_in3_port&gt;, &lt;&amp;xbar_asrc_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_asrc_in5_port&gt;, &lt;&amp;xbar_asrc_in6_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_asrc_in7_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_ope1_in_port&gt;,</div><div class='add'>+		       /* HW accelerators */</div><div class='add'>+		       &lt;&amp;sfc1_out_port&gt;, &lt;&amp;sfc2_out_port&gt;,</div><div class='add'>+		       &lt;&amp;sfc3_out_port&gt;, &lt;&amp;sfc4_out_port&gt;,</div><div class='add'>+		       &lt;&amp;mvc1_out_port&gt;, &lt;&amp;mvc2_out_port&gt;,</div><div class='add'>+		       &lt;&amp;amx1_out_port&gt;, &lt;&amp;amx2_out_port&gt;,</div><div class='add'>+		       &lt;&amp;amx3_out_port&gt;, &lt;&amp;amx4_out_port&gt;,</div><div class='add'>+		       &lt;&amp;adx1_out1_port&gt;, &lt;&amp;adx1_out2_port&gt;,</div><div class='add'>+		       &lt;&amp;adx1_out3_port&gt;, &lt;&amp;adx1_out4_port&gt;,</div><div class='add'>+		       &lt;&amp;adx2_out1_port&gt;, &lt;&amp;adx2_out2_port&gt;,</div><div class='add'>+		       &lt;&amp;adx2_out3_port&gt;, &lt;&amp;adx2_out4_port&gt;,</div><div class='add'>+		       &lt;&amp;adx3_out1_port&gt;, &lt;&amp;adx3_out2_port&gt;,</div><div class='add'>+		       &lt;&amp;adx3_out3_port&gt;, &lt;&amp;adx3_out4_port&gt;,</div><div class='add'>+		       &lt;&amp;adx4_out1_port&gt;, &lt;&amp;adx4_out2_port&gt;,</div><div class='add'>+		       &lt;&amp;adx4_out3_port&gt;, &lt;&amp;adx4_out4_port&gt;,</div><div class='add'>+		       &lt;&amp;mixer_out1_port&gt;, &lt;&amp;mixer_out2_port&gt;,</div><div class='add'>+		       &lt;&amp;mixer_out3_port&gt;, &lt;&amp;mixer_out4_port&gt;,</div><div class='add'>+		       &lt;&amp;mixer_out5_port&gt;,</div><div class='add'>+		       &lt;&amp;asrc_out1_port&gt;, &lt;&amp;asrc_out2_port&gt;, &lt;&amp;asrc_out3_port&gt;,</div><div class='add'>+		       &lt;&amp;asrc_out4_port&gt;, &lt;&amp;asrc_out5_port&gt;, &lt;&amp;asrc_out6_port&gt;,</div><div class='add'>+		       &lt;&amp;ope1_out_port&gt;,</div><div class='add'>+		       /* I/O */</div><div class='add'>+		       &lt;&amp;i2s1_port&gt;, &lt;&amp;i2s2_port&gt;, &lt;&amp;i2s3_port&gt;, &lt;&amp;i2s4_port&gt;,</div><div class='add'>+		       &lt;&amp;i2s5_port&gt;, &lt;&amp;i2s6_port&gt;, &lt;&amp;dmic1_port&gt;, &lt;&amp;dmic2_port&gt;,</div><div class='add'>+		       &lt;&amp;dmic3_port&gt;, &lt;&amp;dspk1_port&gt;, &lt;&amp;dspk2_port&gt;;</div><div class='add'>+</div><div class='add'>+		label = "NVIDIA Jetson TX2 APE";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	thermal-zones {</div><div class='add'>+		cpu-thermal {</div><div class='add'>+			polling-delay = &lt;0&gt;;</div><div class='add'>+			polling-delay-passive = &lt;500&gt;;</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu_trip_critical: critical {</div><div class='add'>+					temperature = &lt;96500&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_trip_hot: hot {</div><div class='add'>+					temperature = &lt;79000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_trip_active: active {</div><div class='add'>+					temperature = &lt;62000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "active";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_trip_passive: passive {</div><div class='add'>+					temperature = &lt;45000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					cooling-device = &lt;&amp;fan 3 3&gt;;</div><div class='add'>+					trip = &lt;&amp;cpu_trip_critical&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				map1 {</div><div class='add'>+					cooling-device = &lt;&amp;fan 2 2&gt;;</div><div class='add'>+					trip = &lt;&amp;cpu_trip_hot&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				map2 {</div><div class='add'>+					cooling-device = &lt;&amp;fan 1 1&gt;;</div><div class='add'>+					trip = &lt;&amp;cpu_trip_active&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				map3 {</div><div class='add'>+					cooling-device = &lt;&amp;fan 0 0&gt;;</div><div class='add'>+					trip = &lt;&amp;cpu_trip_passive&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		vdd_usb1: regulator@103 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;103&gt;;</div><div class='add'>+		aux-thermal {</div><div class='add'>+			polling-delay = &lt;0&gt;;</div><div class='add'>+			polling-delay-passive = &lt;500&gt;;</div><div class='add'>+			status = "okay";</div><div class='ctx'> </div><div class='del'>-			regulator-name = "VDD_USB1";</div><div class='del'>-			regulator-min-microvolt = &lt;5000000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+			trips {</div><div class='add'>+				aux_alert0: critical {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='ctx'> </div><div class='del'>-			gpio = &lt;&amp;gpio TEGRA186_MAIN_GPIO(L, 5) GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			enable-active-high;</div><div class='add'>+		gpu-thermal {</div><div class='add'>+			polling-delay = &lt;0&gt;;</div><div class='add'>+			polling-delay-passive = &lt;500&gt;;</div><div class='add'>+			status = "okay";</div><div class='ctx'> </div><div class='del'>-			vin-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+			trips {</div><div class='add'>+				gpu_alert0: critical {</div><div class='add'>+					temperature = &lt;99000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi<br/>index da96de04d003..970ce5a03540 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi</a></div><div class='hunk'>@@ -9,9 +9,6 @@</div><div class='ctx'> </div><div class='ctx'> 	aliases {</div><div class='ctx'> 		ethernet0 = "/ethernet@2490000";</div><div class='del'>-		sdhci0 = "/sdhci@3460000";</div><div class='del'>-		sdhci1 = "/sdhci@3400000";</div><div class='del'>-		serial0 = &amp;uarta;</div><div class='ctx'> 		i2c0 = "/bpmp/i2c";</div><div class='ctx'> 		i2c1 = "/i2c@3160000";</div><div class='ctx'> 		i2c2 = "/i2c@c240000";</div><div class='hunk'>@@ -20,14 +17,17 @@</div><div class='ctx'> 		i2c5 = "/i2c@31c0000";</div><div class='ctx'> 		i2c6 = "/i2c@c250000";</div><div class='ctx'> 		i2c7 = "/i2c@31e0000";</div><div class='add'>+		mmc0 = "/mmc@3460000";</div><div class='add'>+		mmc1 = "/mmc@3400000";</div><div class='add'>+		serial0 = &amp;uarta;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	chosen {</div><div class='del'>-		bootargs = "earlycon console=ttyS0,115200n8";</div><div class='add'>+		bootargs = "earlycon console=ttyS0,115200n8 fw_devlink=on";</div><div class='ctx'> 		stdout-path = "serial0:115200n8";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	memory {</div><div class='add'>+	memory@80000000 {</div><div class='ctx'> 		device_type = "memory";</div><div class='ctx'> 		reg = &lt;0x0 0x80000000 0x2 0x00000000&gt;;</div><div class='ctx'> 	};</div><div class='hunk'>@@ -44,12 +44,14 @@</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> </div><div class='del'>-			phy: phy@0 {</div><div class='add'>+			phy: ethernet-phy@0 {</div><div class='ctx'> 				compatible = "ethernet-phy-ieee802.3-c22";</div><div class='ctx'> 				reg = &lt;0x0&gt;;</div><div class='ctx'> 				interrupt-parent = &lt;&amp;gpio&gt;;</div><div class='ctx'> 				interrupts = &lt;TEGRA186_MAIN_GPIO(M, 5)</div><div class='ctx'> 					      IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+				#phy-cells = &lt;0&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='hunk'>@@ -59,6 +61,8 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	serial@3100000 {</div><div class='add'>+		/delete-property/ dmas;</div><div class='add'>+		/delete-property/ dma-names;</div><div class='ctx'> 		status = "okay";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -71,19 +75,19 @@</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> </div><div class='del'>-			channel@0 {</div><div class='add'>+			input@0 {</div><div class='ctx'> 				reg = &lt;0x0&gt;;</div><div class='ctx'> 				label = "VDD_SYS_GPU";</div><div class='ctx'> 				shunt-resistor-micro-ohms = &lt;10000&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			channel@1 {</div><div class='add'>+			input@1 {</div><div class='ctx'> 				reg = &lt;0x1&gt;;</div><div class='ctx'> 				label = "VDD_SYS_SOC";</div><div class='ctx'> 				shunt-resistor-micro-ohms = &lt;10000&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			channel@2 {</div><div class='add'>+			input@2 {</div><div class='ctx'> 				reg = &lt;0x2&gt;;</div><div class='ctx'> 				label = "VDD_3V8_WIFI";</div><div class='ctx'> 				shunt-resistor-micro-ohms = &lt;10000&gt;;</div><div class='hunk'>@@ -96,19 +100,19 @@</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> </div><div class='del'>-			channel@0 {</div><div class='add'>+			input@0 {</div><div class='ctx'> 				reg = &lt;0x0&gt;;</div><div class='ctx'> 				label = "VDD_IN";</div><div class='ctx'> 				shunt-resistor-micro-ohms = &lt;5000&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			channel@1 {</div><div class='add'>+			input@1 {</div><div class='ctx'> 				reg = &lt;0x1&gt;;</div><div class='ctx'> 				label = "VDD_SYS_CPU";</div><div class='ctx'> 				shunt-resistor-micro-ohms = &lt;10000&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			channel@2 {</div><div class='add'>+			input@2 {</div><div class='ctx'> 				reg = &lt;0x2&gt;;</div><div class='ctx'> 				label = "VDD_5V0_DDR";</div><div class='ctx'> 				shunt-resistor-micro-ohms = &lt;10000&gt;;</div><div class='hunk'>@@ -133,7 +137,7 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	/* SDMMC1 (SD/MMC) */</div><div class='del'>-	sdhci@3400000 {</div><div class='add'>+	mmc@3400000 {</div><div class='ctx'> 		cd-gpios = &lt;&amp;gpio TEGRA186_MAIN_GPIO(P, 5) GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 		wp-gpios = &lt;&amp;gpio TEGRA186_MAIN_GPIO(P, 4) GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -141,12 +145,13 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	/* SDMMC3 (SDIO) */</div><div class='del'>-	sdhci@3440000 {</div><div class='add'>+	mmc@3440000 {</div><div class='ctx'> 		status = "okay";</div><div class='add'>+		vqmmc-supply = &lt;&amp;vddio_sdmmc3&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	/* SDMMC4 (eMMC) */</div><div class='del'>-	sdhci@3460000 {</div><div class='add'>+	mmc@3460000 {</div><div class='ctx'> 		status = "okay";</div><div class='ctx'> 		bus-width = &lt;8&gt;;</div><div class='ctx'> 		non-removable;</div><div class='hunk'>@@ -171,9 +176,10 @@</div><div class='ctx'> 			compatible = "atmel,24c02";</div><div class='ctx'> 			reg = &lt;0x50&gt;;</div><div class='ctx'> </div><div class='add'>+			label = "module";</div><div class='ctx'> 			vcc-supply = &lt;&amp;vdd_1v8&gt;;</div><div class='del'>-			address-bits = &lt;8&gt;;</div><div class='del'>-			page-size = &lt;8&gt;;</div><div class='add'>+			address-width = &lt;8&gt;;</div><div class='add'>+			pagesize = &lt;8&gt;;</div><div class='ctx'> 			size = &lt;256&gt;;</div><div class='ctx'> 			read-only;</div><div class='ctx'> 		};</div><div class='hunk'>@@ -187,30 +193,8 @@</div><div class='ctx'> 		nvidia,invert-interrupt;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	cpus {</div><div class='del'>-		cpu@0 {</div><div class='del'>-			enable-method = "psci";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		cpu@1 {</div><div class='del'>-			enable-method = "psci";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		cpu@2 {</div><div class='del'>-			enable-method = "psci";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		cpu@3 {</div><div class='del'>-			enable-method = "psci";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		cpu@4 {</div><div class='del'>-			enable-method = "psci";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		cpu@5 {</div><div class='del'>-			enable-method = "psci";</div><div class='del'>-		};</div><div class='add'>+	gpu@17000000 {</div><div class='add'>+		status = "okay";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	bpmp {</div><div class='hunk'>@@ -221,7 +205,8 @@</div><div class='ctx'> 				compatible = "maxim,max77620";</div><div class='ctx'> 				reg = &lt;0x3c&gt;;</div><div class='ctx'> </div><div class='del'>-				interrupts = &lt;GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				interrupt-parent = &lt;&amp;pmc&gt;;</div><div class='add'>+				interrupts = &lt;24 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 				#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 				interrupt-controller;</div><div class='ctx'> </div><div class='hunk'>@@ -231,6 +216,23 @@</div><div class='ctx'> 				pinctrl-names = "default";</div><div class='ctx'> 				pinctrl-0 = &lt;&amp;max77620_default&gt;;</div><div class='ctx'> </div><div class='add'>+				fps {</div><div class='add'>+					fps0 {</div><div class='add'>+						maxim,fps-event-source = &lt;MAX77620_FPS_EVENT_SRC_EN0&gt;;</div><div class='add'>+						maxim,shutdown-fps-time-period-us = &lt;640&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					fps1 {</div><div class='add'>+						maxim,fps-event-source = &lt;MAX77620_FPS_EVENT_SRC_EN1&gt;;</div><div class='add'>+						maxim,shutdown-fps-time-period-us = &lt;640&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					fps2 {</div><div class='add'>+						maxim,fps-event-source = &lt;MAX77620_FPS_EVENT_SRC_EN0&gt;;</div><div class='add'>+						maxim,shutdown-fps-time-period-us = &lt;640&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='ctx'> 				max77620_default: pinmux {</div><div class='ctx'> 					gpio0 {</div><div class='ctx'> 						pins = "gpio0";</div><div class='hunk'>@@ -280,23 +282,6 @@</div><div class='ctx'> 					};</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				fps {</div><div class='del'>-					fps0 {</div><div class='del'>-						maxim,fps-event-source = &lt;MAX77620_FPS_EVENT_SRC_EN0&gt;;</div><div class='del'>-						maxim,shutdown-fps-time-period-us = &lt;640&gt;;</div><div class='del'>-					};</div><div class='del'>-</div><div class='del'>-					fps1 {</div><div class='del'>-						maxim,fps-event-source = &lt;MAX77620_FPS_EVENT_SRC_EN1&gt;;</div><div class='del'>-						maxim,shutdown-fps-time-period-us = &lt;640&gt;;</div><div class='del'>-					};</div><div class='del'>-</div><div class='del'>-					fps2 {</div><div class='del'>-						maxim,fps-event-source = &lt;MAX77620_FPS_EVENT_SRC_EN0&gt;;</div><div class='del'>-						maxim,shutdown-fps-time-period-us = &lt;640&gt;;</div><div class='del'>-					};</div><div class='del'>-				};</div><div class='del'>-</div><div class='ctx'> 				regulators {</div><div class='ctx'> 					in-sd0-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='ctx'> 					in-sd1-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='hunk'>@@ -383,51 +368,65 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	psci {</div><div class='del'>-		compatible = "arm,psci-1.0";</div><div class='del'>-		status = "okay";</div><div class='del'>-		method = "smc";</div><div class='del'>-	};</div><div class='add'>+	cpus {</div><div class='add'>+		cpu@0 {</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='ctx'> </div><div class='del'>-	regulators {</div><div class='del'>-		compatible = "simple-bus";</div><div class='del'>-		#address-cells = &lt;1&gt;;</div><div class='del'>-		#size-cells = &lt;0&gt;;</div><div class='add'>+		cpu@1 {</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='ctx'> </div><div class='del'>-		gnd: regulator@0 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;0&gt;;</div><div class='add'>+		cpu@2 {</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='ctx'> </div><div class='del'>-			regulator-name = "GND";</div><div class='del'>-			regulator-min-microvolt = &lt;0&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;0&gt;;</div><div class='del'>-			regulator-always-on;</div><div class='del'>-			regulator-boot-on;</div><div class='add'>+		cpu@3 {</div><div class='add'>+			enable-method = "psci";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		vdd_5v0_sys: regulator@1 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;1&gt;;</div><div class='add'>+		cpu@4 {</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='ctx'> </div><div class='del'>-			regulator-name = "VDD_5V0_SYS";</div><div class='del'>-			regulator-min-microvolt = &lt;5000000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;5000000&gt;;</div><div class='del'>-			regulator-always-on;</div><div class='del'>-			regulator-boot-on;</div><div class='add'>+		cpu@5 {</div><div class='add'>+			enable-method = "psci";</div><div class='ctx'> 		};</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		vdd_1v8_ap: regulator@2 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;2&gt;;</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-1.0";</div><div class='add'>+		status = "okay";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-			regulator-name = "VDD_1V8_AP";</div><div class='del'>-			regulator-min-microvolt = &lt;1800000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	gnd: regulator-gnd {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "GND";</div><div class='add'>+		regulator-min-microvolt = &lt;0&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;0&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-			gpio = &lt;&amp;pmic 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			enable-active-high;</div><div class='add'>+	vdd_5v0_sys: regulator-vdd-5v0-sys {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_5V0_SYS";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-			vin-supply = &lt;&amp;vdd_1v8&gt;;</div><div class='del'>-		};</div><div class='add'>+	vdd_1v8_ap: regulator-vdd-1v8-ap {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_1V8_AP";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;pmic 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+</div><div class='add'>+		vin-supply = &lt;&amp;vdd_1v8&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts b/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts<br/>new file mode 100644<br/>index 000000000000..d9aafe053112<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts</a></div><div class='hunk'>@@ -0,0 +1,1229 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/input/linux-event-codes.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/gpio-keys.h&gt;</div><div class='add'>+#include &lt;dt-bindings/mfd/max77620.h&gt;</div><div class='add'>+</div><div class='add'>+#include "tegra186.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "NVIDIA Jetson TX2 NX Developer Kit";</div><div class='add'>+	compatible = "nvidia,p3509-0000+p3636-0001", "nvidia,tegra186";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = "/ethernet@2490000";</div><div class='add'>+		i2c0 = "/bpmp/i2c";</div><div class='add'>+		i2c1 = "/i2c@3160000";</div><div class='add'>+		i2c2 = "/i2c@c240000";</div><div class='add'>+		i2c3 = "/i2c@3180000";</div><div class='add'>+		i2c4 = "/i2c@3190000";</div><div class='add'>+		i2c5 = "/i2c@31c0000";</div><div class='add'>+		i2c6 = "/i2c@c250000";</div><div class='add'>+		i2c7 = "/i2c@31e0000";</div><div class='add'>+		mmc0 = "/mmc@3460000";</div><div class='add'>+		serial0 = &amp;uarta;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		bootargs = "earlycon console=ttyS0,115200n8";</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@80000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x80000000 0x0 0x70000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ethernet@2490000 {</div><div class='add'>+		status = "okay";</div><div class='add'>+</div><div class='add'>+		phy-reset-gpios = &lt;&amp;gpio_aon TEGRA186_AON_GPIO(AA, 6) GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		phy-handle = &lt;&amp;phy&gt;;</div><div class='add'>+		phy-mode = "rgmii-id";</div><div class='add'>+</div><div class='add'>+		mdio {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			phy: ethernet-phy@0 {</div><div class='add'>+				compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+				reg = &lt;0x0&gt;;</div><div class='add'>+				interrupt-parent = &lt;&amp;gpio_aon&gt;;</div><div class='add'>+				interrupts = &lt;TEGRA186_AON_GPIO(AA, 7) IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+				#phy-cells = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aconnect@2900000 {</div><div class='add'>+		status = "okay";</div><div class='add'>+</div><div class='add'>+		ahub@2900800 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			i2s@2901000 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						i2s1_cif_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_i2s1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					i2s1_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						i2s1_dap_ep: endpoint {</div><div class='add'>+							dai-format = "i2s";</div><div class='add'>+							/* Placeholder for external Codec */</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2s@2901200 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						i2s3_cif_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_i2s3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					i2s3_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						i2s3_dap_ep: endpoint {</div><div class='add'>+							dai-format = "i2s";</div><div class='add'>+							/* Placeholder for external Codec */</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			dmic@2904000 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						dmic1_cif_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_dmic1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					dmic1_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						dmic1_dap_ep: endpoint {</div><div class='add'>+							/* Place holder for external Codec */</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			dmic@2904100 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						dmic2_cif_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_dmic2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					dmic2_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						dmic2_dap_ep: endpoint {</div><div class='add'>+							/* Place holder for external Codec */</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			admaif@290f000 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					admaif0_port: port@0 {</div><div class='add'>+						reg = &lt;0x0&gt;;</div><div class='add'>+</div><div class='add'>+						admaif0_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif0_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					admaif1_port: port@1 {</div><div class='add'>+						reg = &lt;0x1&gt;;</div><div class='add'>+</div><div class='add'>+						admaif1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					admaif2_port: port@2 {</div><div class='add'>+						reg = &lt;0x2&gt;;</div><div class='add'>+</div><div class='add'>+						admaif2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					admaif3_port: port@3 {</div><div class='add'>+						reg = &lt;0x3&gt;;</div><div class='add'>+</div><div class='add'>+						admaif3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					admaif4_port: port@4 {</div><div class='add'>+						reg = &lt;0x4&gt;;</div><div class='add'>+</div><div class='add'>+						admaif4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					admaif5_port: port@5 {</div><div class='add'>+						reg = &lt;0x5&gt;;</div><div class='add'>+</div><div class='add'>+						admaif5_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif5_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					admaif6_port: port@6 {</div><div class='add'>+						reg = &lt;0x6&gt;;</div><div class='add'>+</div><div class='add'>+						admaif6_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif6_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					admaif7_port: port@7 {</div><div class='add'>+						reg = &lt;0x7&gt;;</div><div class='add'>+</div><div class='add'>+						admaif7_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif7_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					admaif8_port: port@8 {</div><div class='add'>+						reg = &lt;0x8&gt;;</div><div class='add'>+</div><div class='add'>+						admaif8_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif8_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					admaif9_port: port@9 {</div><div class='add'>+						reg = &lt;0x9&gt;;</div><div class='add'>+</div><div class='add'>+						admaif9_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif9_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					admaif10_port: port@a {</div><div class='add'>+						reg = &lt;0xa&gt;;</div><div class='add'>+</div><div class='add'>+						admaif10_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif10_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					admaif11_port: port@b {</div><div class='add'>+						reg = &lt;0xb&gt;;</div><div class='add'>+</div><div class='add'>+						admaif11_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif11_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					admaif12_port: port@c {</div><div class='add'>+						reg = &lt;0xc&gt;;</div><div class='add'>+</div><div class='add'>+						admaif12_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif12_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					admaif13_port: port@d {</div><div class='add'>+						reg = &lt;0xd&gt;;</div><div class='add'>+</div><div class='add'>+						admaif13_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif13_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					admaif14_port: port@e {</div><div class='add'>+						reg = &lt;0xe&gt;;</div><div class='add'>+</div><div class='add'>+						admaif14_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif14_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					admaif15_port: port@f {</div><div class='add'>+						reg = &lt;0xf&gt;;</div><div class='add'>+</div><div class='add'>+						admaif15_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif15_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					admaif16_port: port@10 {</div><div class='add'>+						reg = &lt;0x10&gt;;</div><div class='add'>+</div><div class='add'>+						admaif16_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif16_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					admaif17_port: port@11 {</div><div class='add'>+						reg = &lt;0x11&gt;;</div><div class='add'>+</div><div class='add'>+						admaif17_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif17_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					admaif18_port: port@12 {</div><div class='add'>+						reg = &lt;0x12&gt;;</div><div class='add'>+</div><div class='add'>+						admaif18_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif18_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					admaif19_port: port@13 {</div><div class='add'>+						reg = &lt;0x13&gt;;</div><div class='add'>+</div><div class='add'>+						admaif19_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif19_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0x0&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif0_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif0_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;0x1&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif1_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif1_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@2 {</div><div class='add'>+					reg = &lt;0x2&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif2_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif2_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@3 {</div><div class='add'>+					reg = &lt;0x3&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif3_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif3_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@4 {</div><div class='add'>+					reg = &lt;0x4&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif4_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif4_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@5 {</div><div class='add'>+					reg = &lt;0x5&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif5_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif5_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@6 {</div><div class='add'>+					reg = &lt;0x6&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif6_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif6_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@7 {</div><div class='add'>+					reg = &lt;0x7&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif7_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif7_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@8 {</div><div class='add'>+					reg = &lt;0x8&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif8_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif8_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@9 {</div><div class='add'>+					reg = &lt;0x9&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif9_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif9_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@a {</div><div class='add'>+					reg = &lt;0xa&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif10_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif10_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@b {</div><div class='add'>+					reg = &lt;0xb&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif11_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif11_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@c {</div><div class='add'>+					reg = &lt;0xc&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif12_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif12_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@d {</div><div class='add'>+					reg = &lt;0xd&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif13_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif13_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@e {</div><div class='add'>+					reg = &lt;0xe&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif14_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif14_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@f {</div><div class='add'>+					reg = &lt;0xf&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif15_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif15_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@10 {</div><div class='add'>+					reg = &lt;0x10&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif16_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif16_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@11 {</div><div class='add'>+					reg = &lt;0x11&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif17_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif17_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@12 {</div><div class='add'>+					reg = &lt;0x12&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif18_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif18_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@13 {</div><div class='add'>+					reg = &lt;0x13&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif19_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif19_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_i2s1_port: port@14 {</div><div class='add'>+					reg = &lt;0x14&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_i2s1_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;i2s1_cif_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_i2s3_port: port@16 {</div><div class='add'>+					reg = &lt;0x16&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_i2s3_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;i2s3_cif_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_dmic1_port: port@1a {</div><div class='add'>+					reg = &lt;0x1a&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_dmic1_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dmic1_cif_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_dmic2_port: port@1b {</div><div class='add'>+					reg = &lt;0x1b&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_dmic2_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dmic2_cif_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dma-controller@2930000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		interrupt-controller@2a40000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory-controller@2c00000 {</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer@3010000 {</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	serial@3100000 {</div><div class='add'>+		/delete-property/ dmas;</div><div class='add'>+		/delete-property/ dma-names;</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c@3160000 {</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c@3180000 {</div><div class='add'>+		status = "okay";</div><div class='add'>+</div><div class='add'>+		power-monitor@40 {</div><div class='add'>+			compatible = "ti,ina3221";</div><div class='add'>+			reg = &lt;0x40&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			input@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				label = "VDD_IN";</div><div class='add'>+				shunt-resistor-micro-ohms = &lt;5&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			input@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				label = "VDD_CPU_GPU";</div><div class='add'>+				shunt-resistor-micro-ohms = &lt;5&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			input@2 {</div><div class='add'>+				reg = &lt;2&gt;;</div><div class='add'>+				label = "VDD_SOC";</div><div class='add'>+				shunt-resistor-micro-ohms = &lt;5&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ddc: i2c@3190000 {</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c@31c0000 {</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c@31e0000 {</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SDMMC4 (eMMC) */</div><div class='add'>+	mmc@3460000 {</div><div class='add'>+		status = "okay";</div><div class='add'>+		bus-width = &lt;8&gt;;</div><div class='add'>+		non-removable;</div><div class='add'>+</div><div class='add'>+		vqmmc-supply = &lt;&amp;vdd_1v8_ap&gt;;</div><div class='add'>+		vmmc-supply = &lt;&amp;vdd_3v3_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hda@3510000 {</div><div class='add'>+		nvidia,model = "NVIDIA Jetson TX2 NX HDA";</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	padctl@3520000 {</div><div class='add'>+		status = "okay";</div><div class='add'>+</div><div class='add'>+		avdd-pll-erefeut-supply = &lt;&amp;vdd_1v8_pll&gt;;</div><div class='add'>+		avdd-usb-supply = &lt;&amp;vdd_3v3_sys&gt;;</div><div class='add'>+		vclamp-usb-supply = &lt;&amp;vdd_1v8&gt;;</div><div class='add'>+		vddio-hsic-supply = &lt;&amp;gnd&gt;;</div><div class='add'>+</div><div class='add'>+		pads {</div><div class='add'>+			usb2 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				lanes {</div><div class='add'>+					micro_b: usb2-0 {</div><div class='add'>+						nvidia,function = "xusb";</div><div class='add'>+						status = "okay";</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					usb2-1 {</div><div class='add'>+						nvidia,function = "xusb";</div><div class='add'>+						status = "okay";</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					usb2-2 {</div><div class='add'>+						nvidia,function = "xusb";</div><div class='add'>+						status = "okay";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			usb3 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				lanes {</div><div class='add'>+					usb3-1 {</div><div class='add'>+						nvidia,function = "xusb";</div><div class='add'>+						status = "okay";</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			usb2-0 {</div><div class='add'>+				status = "okay";</div><div class='add'>+				mode = "otg";</div><div class='add'>+				vbus-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+				usb-role-switch;</div><div class='add'>+</div><div class='add'>+				connector {</div><div class='add'>+					compatible = "gpio-usb-b-connector",</div><div class='add'>+						     "usb-b-connector";</div><div class='add'>+					label = "micro-USB";</div><div class='add'>+					type = "micro";</div><div class='add'>+					vbus-gpios = &lt;&amp;gpio</div><div class='add'>+						      TEGRA186_MAIN_GPIO(L, 4)</div><div class='add'>+						      GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			usb2-1 {</div><div class='add'>+				status = "okay";</div><div class='add'>+				mode = "host";</div><div class='add'>+</div><div class='add'>+				vbus-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			usb2-2 {</div><div class='add'>+				status = "okay";</div><div class='add'>+				mode = "host";</div><div class='add'>+</div><div class='add'>+				vbus-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			usb3-1 {</div><div class='add'>+				nvidia,usb2-companion = &lt;1&gt;;</div><div class='add'>+				vbus-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+				status = "okay";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb@3530000 {</div><div class='add'>+		status = "okay";</div><div class='add'>+</div><div class='add'>+		phys = &lt;&amp;{/padctl@3520000/pads/usb2/lanes/usb2-0}&gt;,</div><div class='add'>+		       &lt;&amp;{/padctl@3520000/pads/usb2/lanes/usb2-1}&gt;,</div><div class='add'>+		       &lt;&amp;{/padctl@3520000/pads/usb2/lanes/usb2-2}&gt;,</div><div class='add'>+		       &lt;&amp;{/padctl@3520000/pads/usb3/lanes/usb3-1}&gt;;</div><div class='add'>+		phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-1";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb@3550000 {</div><div class='add'>+		status = "okay";</div><div class='add'>+</div><div class='add'>+		phys = &lt;&amp;micro_b&gt;;</div><div class='add'>+		phy-names = "usb2-0";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cec@3960000 {</div><div class='add'>+		status = "okay";</div><div class='add'>+</div><div class='add'>+		hdmi-phandle = &lt;&amp;sor1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hsp@3c00000 {</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c@c240000 {</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c@c250000 {</div><div class='add'>+		status = "okay";</div><div class='add'>+</div><div class='add'>+		/* module ID EEPROM */</div><div class='add'>+		eeprom@50 {</div><div class='add'>+			compatible = "atmel,24c02";</div><div class='add'>+			reg = &lt;0x50&gt;;</div><div class='add'>+</div><div class='add'>+			label = "module";</div><div class='add'>+			vcc-supply = &lt;&amp;vdd_1v8&gt;;</div><div class='add'>+			address-width = &lt;8&gt;;</div><div class='add'>+			pagesize = &lt;8&gt;;</div><div class='add'>+			size = &lt;256&gt;;</div><div class='add'>+			read-only;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* carrier board ID EEPROM */</div><div class='add'>+		eeprom@57 {</div><div class='add'>+			compatible = "atmel,24c02";</div><div class='add'>+			reg = &lt;0x57&gt;;</div><div class='add'>+</div><div class='add'>+			label = "system";</div><div class='add'>+			vcc-supply = &lt;&amp;vdd_1v8&gt;;</div><div class='add'>+			address-width = &lt;8&gt;;</div><div class='add'>+			pagesize = &lt;8&gt;;</div><div class='add'>+			size = &lt;256&gt;;</div><div class='add'>+			read-only;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rtc@c2a0000 {</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pwm@c340000 {</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmc@c360000 {</div><div class='add'>+		nvidia,invert-interrupt;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie@10003000 {</div><div class='add'>+		status = "okay";</div><div class='add'>+</div><div class='add'>+		dvdd-pex-supply = &lt;&amp;vdd_pex&gt;;</div><div class='add'>+		hvdd-pex-pll-supply = &lt;&amp;vdd_1v8&gt;;</div><div class='add'>+		hvdd-pex-supply = &lt;&amp;vdd_1v8&gt;;</div><div class='add'>+		vddio-pexctl-aud-supply = &lt;&amp;vdd_1v8&gt;;</div><div class='add'>+</div><div class='add'>+		pci@1,0 {</div><div class='add'>+			nvidia,num-lanes = &lt;2&gt;;</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pci@2,0 {</div><div class='add'>+			nvidia,num-lanes = &lt;1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pci@3,0 {</div><div class='add'>+			nvidia,num-lanes = &lt;1&gt;;</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	host1x@13e00000 {</div><div class='add'>+		status = "okay";</div><div class='add'>+</div><div class='add'>+		dpaux@15040000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		display-hub@15200000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dsi@15300000 {</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* DP */</div><div class='add'>+		sor@15540000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			avdd-io-hdmi-dp-supply = &lt;&amp;vdd_hdmi_1v05&gt;;</div><div class='add'>+			vdd-hdmi-dp-pll-supply = &lt;&amp;vdd_1v8_ap&gt;;</div><div class='add'>+</div><div class='add'>+			nvidia,dpaux = &lt;&amp;dpaux&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* HDMI */</div><div class='add'>+		sor@15580000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			avdd-io-hdmi-dp-supply = &lt;&amp;vdd_hdmi_1v05&gt;;</div><div class='add'>+			vdd-hdmi-dp-pll-supply = &lt;&amp;vdd_1v8_ap&gt;;</div><div class='add'>+			hdmi-supply = &lt;&amp;vdd_hdmi&gt;;</div><div class='add'>+</div><div class='add'>+			nvidia,ddc-i2c-bus = &lt;&amp;ddc&gt;;</div><div class='add'>+			nvidia,hpd-gpio = &lt;&amp;gpio TEGRA186_MAIN_GPIO(P, 1)</div><div class='add'>+						 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dpaux@155c0000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpu@17000000 {</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bpmp {</div><div class='add'>+		i2c {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			pmic: pmic@3c {</div><div class='add'>+				compatible = "maxim,max77620";</div><div class='add'>+				reg = &lt;0x3c&gt;;</div><div class='add'>+</div><div class='add'>+				interrupt-parent = &lt;&amp;pmc&gt;;</div><div class='add'>+				interrupts = &lt;24 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+				#interrupt-cells = &lt;2&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;max77620_default&gt;;</div><div class='add'>+</div><div class='add'>+				fps {</div><div class='add'>+					fps0 {</div><div class='add'>+						maxim,fps-event-source = &lt;MAX77620_FPS_EVENT_SRC_EN0&gt;;</div><div class='add'>+						maxim,shutdown-fps-time-period-us = &lt;640&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					fps1 {</div><div class='add'>+						maxim,fps-event-source = &lt;MAX77620_FPS_EVENT_SRC_EN1&gt;;</div><div class='add'>+						maxim,shutdown-fps-time-period-us = &lt;640&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					fps2 {</div><div class='add'>+						maxim,fps-event-source = &lt;MAX77620_FPS_EVENT_SRC_EN0&gt;;</div><div class='add'>+						maxim,shutdown-fps-time-period-us = &lt;640&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				max77620_default: pinmux {</div><div class='add'>+					gpio0 {</div><div class='add'>+						pins = "gpio0";</div><div class='add'>+						function = "gpio";</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					gpio1 {</div><div class='add'>+						pins = "gpio1";</div><div class='add'>+						function = "fps-out";</div><div class='add'>+						maxim,active-fps-source = &lt;MAX77620_FPS_SRC_0&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					gpio2 {</div><div class='add'>+						pins = "gpio2";</div><div class='add'>+						function = "fps-out";</div><div class='add'>+						maxim,active-fps-source = &lt;MAX77620_FPS_SRC_1&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					gpio3 {</div><div class='add'>+						pins = "gpio3";</div><div class='add'>+						function = "fps-out";</div><div class='add'>+						maxim,active-fps-source = &lt;MAX77620_FPS_SRC_1&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					gpio4 {</div><div class='add'>+						pins = "gpio4";</div><div class='add'>+						function = "32k-out1";</div><div class='add'>+						drive-push-pull = &lt;1&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					gpio5 {</div><div class='add'>+						pins = "gpio5";</div><div class='add'>+						function = "gpio";</div><div class='add'>+						drive-push-pull = &lt;0&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					gpio6 {</div><div class='add'>+						pins = "gpio6";</div><div class='add'>+						function = "gpio";</div><div class='add'>+						drive-push-pull = &lt;1&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					gpio7 {</div><div class='add'>+						pins = "gpio7";</div><div class='add'>+						function = "gpio";</div><div class='add'>+						drive-push-pull = &lt;1&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				regulators {</div><div class='add'>+					in-sd0-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+					in-sd1-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+					in-sd2-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+					in-sd3-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+</div><div class='add'>+					in-ldo0-1-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+					in-ldo2-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+					in-ldo3-5-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+					in-ldo4-6-supply = &lt;&amp;vdd_1v8&gt;;</div><div class='add'>+					in-ldo7-8-supply = &lt;&amp;avdd_dsi_csi&gt;;</div><div class='add'>+</div><div class='add'>+					sd0 {</div><div class='add'>+						regulator-name = "VDD_DDR_1V1_PMIC";</div><div class='add'>+						regulator-min-microvolt = &lt;1100000&gt;;</div><div class='add'>+						regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+						regulator-always-on;</div><div class='add'>+						regulator-boot-on;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					avdd_dsi_csi: sd1 {</div><div class='add'>+						regulator-name = "AVDD_DSI_CSI_1V2";</div><div class='add'>+						regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+						regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					vdd_1v8: sd2 {</div><div class='add'>+						regulator-name = "VDD_1V8";</div><div class='add'>+						regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+						regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					vdd_3v3_sys: sd3 {</div><div class='add'>+						regulator-name = "VDD_3V3_SYS";</div><div class='add'>+						regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+						regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					vdd_1v8_pll: ldo0 {</div><div class='add'>+						regulator-name = "VDD_1V8_AP_PLL";</div><div class='add'>+						regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+						regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					ldo2 {</div><div class='add'>+						regulator-name = "VDDIO_3V3_AOHV";</div><div class='add'>+						regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+						regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+						regulator-always-on;</div><div class='add'>+						regulator-boot-on;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					vddio_sdmmc1: ldo3 {</div><div class='add'>+						regulator-name = "VDDIO_SDMMC1_AP";</div><div class='add'>+						regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+						regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					ldo4 {</div><div class='add'>+						regulator-name = "VDD_RTC";</div><div class='add'>+						regulator-min-microvolt = &lt;1000000&gt;;</div><div class='add'>+						regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					vddio_sdmmc3: ldo5 {</div><div class='add'>+						regulator-name = "VDDIO_SDMMC3_AP";</div><div class='add'>+						regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+						regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					vdd_hdmi_1v05: ldo7 {</div><div class='add'>+						regulator-name = "VDD_HDMI_1V05";</div><div class='add'>+						regulator-min-microvolt = &lt;1050000&gt;;</div><div class='add'>+						regulator-max-microvolt = &lt;1050000&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					vdd_pex: ldo8 {</div><div class='add'>+						regulator-name = "VDD_PEX_1V05";</div><div class='add'>+						regulator-min-microvolt = &lt;1050000&gt;;</div><div class='add'>+						regulator-max-microvolt = &lt;1050000&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		cpu@0 {</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu@1 {</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu@2 {</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu@3 {</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu@4 {</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu@5 {</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		key-power {</div><div class='add'>+			label = "Power";</div><div class='add'>+			gpios = &lt;&amp;gpio_aon TEGRA186_AON_GPIO(FF, 0)</div><div class='add'>+					   GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,input-type = &lt;EV_KEY&gt;;</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+			debounce-interval = &lt;10&gt;;</div><div class='add'>+			wakeup-event-action = &lt;EV_ACT_ASSERTED&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-volume-down {</div><div class='add'>+			label = "Volume Down";</div><div class='add'>+			gpios = &lt;&amp;gpio_aon TEGRA186_AON_GPIO(FF, 2)</div><div class='add'>+					   GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,input-type = &lt;EV_KEY&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+			debounce-interval = &lt;10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-volume-up {</div><div class='add'>+			label = "Volume Up";</div><div class='add'>+			gpios = &lt;&amp;gpio_aon TEGRA186_AON_GPIO(FF, 1)</div><div class='add'>+					   GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,input-type = &lt;EV_KEY&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+			debounce-interval = &lt;10&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-1.0";</div><div class='add'>+		status = "okay";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fan: pwm-fan {</div><div class='add'>+		compatible = "pwm-fan";</div><div class='add'>+		pwms = &lt;&amp;pwm4 0 45334&gt;;</div><div class='add'>+</div><div class='add'>+		cooling-levels = &lt;0 64 128 255&gt;;</div><div class='add'>+		#cooling-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gnd: regulator-gnd {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "GND";</div><div class='add'>+		regulator-min-microvolt = &lt;0&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;0&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_5v0_sys: regulator-vdd-5v0-sys {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_5V0_SYS";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_1v8_ap: regulator-vdd-1v8-ap {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_1V8_AP";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;pmic 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+</div><div class='add'>+		vin-supply = &lt;&amp;vdd_1v8&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_hdmi: regulator-vdd-hdmi {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_5V0_HDMI_CON";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+</div><div class='add'>+		vin-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "nvidia,tegra186-audio-graph-card";</div><div class='add'>+		status = "okay";</div><div class='add'>+</div><div class='add'>+		dais = /* FE */</div><div class='add'>+		       &lt;&amp;admaif0_port&gt;, &lt;&amp;admaif1_port&gt;, &lt;&amp;admaif2_port&gt;, &lt;&amp;admaif3_port&gt;,</div><div class='add'>+		       &lt;&amp;admaif4_port&gt;, &lt;&amp;admaif5_port&gt;, &lt;&amp;admaif6_port&gt;, &lt;&amp;admaif7_port&gt;,</div><div class='add'>+		       &lt;&amp;admaif8_port&gt;, &lt;&amp;admaif9_port&gt;, &lt;&amp;admaif10_port&gt;, &lt;&amp;admaif11_port&gt;,</div><div class='add'>+		       &lt;&amp;admaif12_port&gt;, &lt;&amp;admaif13_port&gt;, &lt;&amp;admaif14_port&gt;, &lt;&amp;admaif15_port&gt;,</div><div class='add'>+		       &lt;&amp;admaif16_port&gt;, &lt;&amp;admaif17_port&gt;, &lt;&amp;admaif18_port&gt;, &lt;&amp;admaif19_port&gt;,</div><div class='add'>+		       /* Router */</div><div class='add'>+		       &lt;&amp;xbar_i2s1_port&gt;, &lt;&amp;xbar_i2s3_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_dmic1_port&gt;, &lt;&amp;xbar_dmic2_port&gt;,</div><div class='add'>+		       /* I/O */</div><div class='add'>+		       &lt;&amp;i2s1_port&gt;, &lt;&amp;i2s3_port&gt;,</div><div class='add'>+		       &lt;&amp;dmic1_port&gt;, &lt;&amp;dmic2_port&gt;;</div><div class='add'>+</div><div class='add'>+		label = "NVIDIA Jetson TX2 NX APE";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	thermal-zones {</div><div class='add'>+		cpu-thermal {</div><div class='add'>+			polling-delay = &lt;0&gt;;</div><div class='add'>+			polling-delay-passive = &lt;500&gt;;</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu_trip_critical: critical {</div><div class='add'>+					temperature = &lt;96500&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_trip_hot: hot {</div><div class='add'>+					temperature = &lt;79000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_trip_active: active {</div><div class='add'>+					temperature = &lt;62000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "active";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_trip_passive: passive {</div><div class='add'>+					temperature = &lt;45000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				cpu-critical {</div><div class='add'>+					cooling-device = &lt;&amp;fan 3 3&gt;;</div><div class='add'>+					trip = &lt;&amp;cpu_trip_critical&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu-hot {</div><div class='add'>+					cooling-device = &lt;&amp;fan 2 2&gt;;</div><div class='add'>+					trip = &lt;&amp;cpu_trip_hot&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu-active {</div><div class='add'>+					cooling-device = &lt;&amp;fan 1 1&gt;;</div><div class='add'>+					trip = &lt;&amp;cpu_trip_active&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu-passive {</div><div class='add'>+					cooling-device = &lt;&amp;fan 0 0&gt;;</div><div class='add'>+					trip = &lt;&amp;cpu_trip_passive&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aux-thermal {</div><div class='add'>+			polling-delay = &lt;0&gt;;</div><div class='add'>+			polling-delay-passive = &lt;500&gt;;</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				aux_alert0: critical {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu-thermal {</div><div class='add'>+			polling-delay = &lt;0&gt;;</div><div class='add'>+			polling-delay-passive = &lt;500&gt;;</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				gpu_alert0: critical {</div><div class='add'>+					temperature = &lt;99000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi<br/>index 58100fb9cd8b..b00630451909 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra186.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra186.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra186.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/tegra186.dtsi</a></div><div class='hunk'>@@ -36,6 +36,12 @@</div><div class='ctx'> 		interrupt-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='ctx'> 		gpio-controller;</div><div class='add'>+		gpio-ranges = &lt;&amp;pinmux 0 0 140&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinmux: pinmux@2430000 {</div><div class='add'>+		compatible = "nvidia,tegra186-pinmux";</div><div class='add'>+		reg = &lt;0x0 0x2430000 0x0 0x15000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	ethernet@2490000 {</div><div class='hunk'>@@ -60,6 +66,9 @@</div><div class='ctx'> 		clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";</div><div class='ctx'> 		resets = &lt;&amp;bpmp TEGRA186_RESET_EQOS&gt;;</div><div class='ctx'> 		reset-names = "eqos";</div><div class='add'>+		interconnects = &lt;&amp;mc TEGRA186_MEMORY_CLIENT_EQOSR &amp;emc&gt;,</div><div class='add'>+				&lt;&amp;mc TEGRA186_MEMORY_CLIENT_EQOSW &amp;emc&gt;;</div><div class='add'>+		interconnect-names = "dma-mem", "write";</div><div class='ctx'> 		iommus = &lt;&amp;smmu TEGRA186_SID_EQOS&gt;;</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> </div><div class='hunk'>@@ -70,21 +79,431 @@</div><div class='ctx'> 		snps,rxpbl = &lt;8&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	aconnect {</div><div class='add'>+	gpcdma: dma-controller@2600000 {</div><div class='add'>+		compatible = "nvidia,tegra186-gpcdma";</div><div class='add'>+		reg = &lt;0x0 0x2600000 0x0 0x210000&gt;;</div><div class='add'>+		resets = &lt;&amp;bpmp TEGRA186_RESET_GPCDMA&gt;;</div><div class='add'>+		reset-names = "gpcdma";</div><div class='add'>+		interrupts = &lt;GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		#dma-cells = &lt;1&gt;;</div><div class='add'>+		iommus = &lt;&amp;smmu TEGRA186_SID_GPCDMA_0&gt;;</div><div class='add'>+		dma-coherent;</div><div class='add'>+		dma-channel-mask = &lt;0xfffffffe&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aconnect@2900000 {</div><div class='ctx'> 		compatible = "nvidia,tegra186-aconnect",</div><div class='ctx'> 			     "nvidia,tegra210-aconnect";</div><div class='ctx'> 		clocks = &lt;&amp;bpmp TEGRA186_CLK_APE&gt;,</div><div class='ctx'> 			 &lt;&amp;bpmp TEGRA186_CLK_APB2APE&gt;;</div><div class='ctx'> 		clock-names = "ape", "apb2ape";</div><div class='ctx'> 		power-domains = &lt;&amp;bpmp TEGRA186_POWER_DOMAIN_AUD&gt;;</div><div class='del'>-		#address-cells = &lt;1&gt;;</div><div class='del'>-		#size-cells = &lt;1&gt;;</div><div class='del'>-		ranges = &lt;0x02900000 0x0 0x02900000 0x200000&gt;;</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges = &lt;0x0 0x02900000 0x0 0x02900000 0x0 0x200000&gt;;</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> </div><div class='del'>-		dma-controller@2930000 {</div><div class='add'>+		tegra_ahub: ahub@2900800 {</div><div class='add'>+			compatible = "nvidia,tegra186-ahub";</div><div class='add'>+			reg = &lt;0x0 0x02900800 0x0 0x800&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA186_CLK_AHUB&gt;;</div><div class='add'>+			clock-names = "ahub";</div><div class='add'>+			assigned-clocks = &lt;&amp;bpmp TEGRA186_CLK_AHUB&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;bpmp TEGRA186_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;81600000&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges = &lt;0x0 0x02900800 0x0 0x02900800 0x0 0x11800&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			tegra_i2s1: i2s@2901000 {</div><div class='add'>+				compatible = "nvidia,tegra186-i2s",</div><div class='add'>+					     "nvidia,tegra210-i2s";</div><div class='add'>+				reg = &lt;0x0 0x2901000 0x0 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;bpmp TEGRA186_CLK_I2S1&gt;,</div><div class='add'>+					 &lt;&amp;bpmp TEGRA186_CLK_I2S1_SYNC_INPUT&gt;;</div><div class='add'>+				clock-names = "i2s", "sync_input";</div><div class='add'>+				assigned-clocks = &lt;&amp;bpmp TEGRA186_CLK_I2S1&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;bpmp TEGRA186_CLK_PLL_A_OUT0&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;1536000&gt;;</div><div class='add'>+				sound-name-prefix = "I2S1";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_i2s2: i2s@2901100 {</div><div class='add'>+				compatible = "nvidia,tegra186-i2s",</div><div class='add'>+					     "nvidia,tegra210-i2s";</div><div class='add'>+				reg = &lt;0x0 0x2901100 0x0 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;bpmp TEGRA186_CLK_I2S2&gt;,</div><div class='add'>+					 &lt;&amp;bpmp TEGRA186_CLK_I2S2_SYNC_INPUT&gt;;</div><div class='add'>+				clock-names = "i2s", "sync_input";</div><div class='add'>+				assigned-clocks = &lt;&amp;bpmp TEGRA186_CLK_I2S2&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;bpmp TEGRA186_CLK_PLL_A_OUT0&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;1536000&gt;;</div><div class='add'>+				sound-name-prefix = "I2S2";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_i2s3: i2s@2901200 {</div><div class='add'>+				compatible = "nvidia,tegra186-i2s",</div><div class='add'>+					     "nvidia,tegra210-i2s";</div><div class='add'>+				reg = &lt;0x0 0x2901200 0x0 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;bpmp TEGRA186_CLK_I2S3&gt;,</div><div class='add'>+					 &lt;&amp;bpmp TEGRA186_CLK_I2S3_SYNC_INPUT&gt;;</div><div class='add'>+				clock-names = "i2s", "sync_input";</div><div class='add'>+				assigned-clocks = &lt;&amp;bpmp TEGRA186_CLK_I2S3&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;bpmp TEGRA186_CLK_PLL_A_OUT0&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;1536000&gt;;</div><div class='add'>+				sound-name-prefix = "I2S3";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_i2s4: i2s@2901300 {</div><div class='add'>+				compatible = "nvidia,tegra186-i2s",</div><div class='add'>+					     "nvidia,tegra210-i2s";</div><div class='add'>+				reg = &lt;0x0 0x2901300 0x0 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;bpmp TEGRA186_CLK_I2S4&gt;,</div><div class='add'>+					 &lt;&amp;bpmp TEGRA186_CLK_I2S4_SYNC_INPUT&gt;;</div><div class='add'>+				clock-names = "i2s", "sync_input";</div><div class='add'>+				assigned-clocks = &lt;&amp;bpmp TEGRA186_CLK_I2S4&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;bpmp TEGRA186_CLK_PLL_A_OUT0&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;1536000&gt;;</div><div class='add'>+				sound-name-prefix = "I2S4";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_i2s5: i2s@2901400 {</div><div class='add'>+				compatible = "nvidia,tegra186-i2s",</div><div class='add'>+					     "nvidia,tegra210-i2s";</div><div class='add'>+				reg = &lt;0x0 0x2901400 0x0 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;bpmp TEGRA186_CLK_I2S5&gt;,</div><div class='add'>+					 &lt;&amp;bpmp TEGRA186_CLK_I2S5_SYNC_INPUT&gt;;</div><div class='add'>+				clock-names = "i2s", "sync_input";</div><div class='add'>+				assigned-clocks = &lt;&amp;bpmp TEGRA186_CLK_I2S5&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;bpmp TEGRA186_CLK_PLL_A_OUT0&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;1536000&gt;;</div><div class='add'>+				sound-name-prefix = "I2S5";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_i2s6: i2s@2901500 {</div><div class='add'>+				compatible = "nvidia,tegra186-i2s",</div><div class='add'>+					     "nvidia,tegra210-i2s";</div><div class='add'>+				reg = &lt;0x0 0x2901500 0x0 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;bpmp TEGRA186_CLK_I2S6&gt;,</div><div class='add'>+					 &lt;&amp;bpmp TEGRA186_CLK_I2S6_SYNC_INPUT&gt;;</div><div class='add'>+				clock-names = "i2s", "sync_input";</div><div class='add'>+				assigned-clocks = &lt;&amp;bpmp TEGRA186_CLK_I2S6&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;bpmp TEGRA186_CLK_PLL_A_OUT0&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;1536000&gt;;</div><div class='add'>+				sound-name-prefix = "I2S6";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_sfc1: sfc@2902000 {</div><div class='add'>+				compatible = "nvidia,tegra186-sfc",</div><div class='add'>+					     "nvidia,tegra210-sfc";</div><div class='add'>+				reg = &lt;0x0 0x2902000 0x0 0x200&gt;;</div><div class='add'>+				sound-name-prefix = "SFC1";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_sfc2: sfc@2902200 {</div><div class='add'>+				compatible = "nvidia,tegra186-sfc",</div><div class='add'>+					     "nvidia,tegra210-sfc";</div><div class='add'>+				reg = &lt;0x0 0x2902200 0x0 0x200&gt;;</div><div class='add'>+				sound-name-prefix = "SFC2";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_sfc3: sfc@2902400 {</div><div class='add'>+				compatible = "nvidia,tegra186-sfc",</div><div class='add'>+					     "nvidia,tegra210-sfc";</div><div class='add'>+				reg = &lt;0x0 0x2902400 0x0 0x200&gt;;</div><div class='add'>+				sound-name-prefix = "SFC3";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_sfc4: sfc@2902600 {</div><div class='add'>+				compatible = "nvidia,tegra186-sfc",</div><div class='add'>+					     "nvidia,tegra210-sfc";</div><div class='add'>+				reg = &lt;0x0 0x2902600 0x0 0x200&gt;;</div><div class='add'>+				sound-name-prefix = "SFC4";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_amx1: amx@2903000 {</div><div class='add'>+				compatible = "nvidia,tegra186-amx",</div><div class='add'>+					     "nvidia,tegra210-amx";</div><div class='add'>+				reg = &lt;0x0 0x2903000 0x0 0x100&gt;;</div><div class='add'>+				sound-name-prefix = "AMX1";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_amx2: amx@2903100 {</div><div class='add'>+				compatible = "nvidia,tegra186-amx",</div><div class='add'>+					     "nvidia,tegra210-amx";</div><div class='add'>+				reg = &lt;0x0 0x2903100 0x0 0x100&gt;;</div><div class='add'>+				sound-name-prefix = "AMX2";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_amx3: amx@2903200 {</div><div class='add'>+				compatible = "nvidia,tegra186-amx",</div><div class='add'>+					     "nvidia,tegra210-amx";</div><div class='add'>+				reg = &lt;0x0 0x2903200 0x0 0x100&gt;;</div><div class='add'>+				sound-name-prefix = "AMX3";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_amx4: amx@2903300 {</div><div class='add'>+				compatible = "nvidia,tegra186-amx",</div><div class='add'>+					     "nvidia,tegra210-amx";</div><div class='add'>+				reg = &lt;0x0 0x2903300 0x0 0x100&gt;;</div><div class='add'>+				sound-name-prefix = "AMX4";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_adx1: adx@2903800 {</div><div class='add'>+				compatible = "nvidia,tegra186-adx",</div><div class='add'>+					     "nvidia,tegra210-adx";</div><div class='add'>+				reg = &lt;0x0 0x2903800 0x0 0x100&gt;;</div><div class='add'>+				sound-name-prefix = "ADX1";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_adx2: adx@2903900 {</div><div class='add'>+				compatible = "nvidia,tegra186-adx",</div><div class='add'>+					     "nvidia,tegra210-adx";</div><div class='add'>+				reg = &lt;0x0 0x2903900 0x0 0x100&gt;;</div><div class='add'>+				sound-name-prefix = "ADX2";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_adx3: adx@2903a00 {</div><div class='add'>+				compatible = "nvidia,tegra186-adx",</div><div class='add'>+					     "nvidia,tegra210-adx";</div><div class='add'>+				reg = &lt;0x0 0x2903a00 0x0 0x100&gt;;</div><div class='add'>+				sound-name-prefix = "ADX3";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_adx4: adx@2903b00 {</div><div class='add'>+				compatible = "nvidia,tegra186-adx",</div><div class='add'>+					     "nvidia,tegra210-adx";</div><div class='add'>+				reg = &lt;0x0 0x2903b00 0x0 0x100&gt;;</div><div class='add'>+				sound-name-prefix = "ADX4";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_dmic1: dmic@2904000 {</div><div class='add'>+				compatible = "nvidia,tegra210-dmic";</div><div class='add'>+				reg = &lt;0x0 0x2904000 0x0 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;bpmp TEGRA186_CLK_DMIC1&gt;;</div><div class='add'>+				clock-names = "dmic";</div><div class='add'>+				assigned-clocks = &lt;&amp;bpmp TEGRA186_CLK_DMIC1&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;bpmp TEGRA186_CLK_PLL_A_OUT0&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;3072000&gt;;</div><div class='add'>+				sound-name-prefix = "DMIC1";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_dmic2: dmic@2904100 {</div><div class='add'>+				compatible = "nvidia,tegra210-dmic";</div><div class='add'>+				reg = &lt;0x0 0x2904100 0x0 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;bpmp TEGRA186_CLK_DMIC2&gt;;</div><div class='add'>+				clock-names = "dmic";</div><div class='add'>+				assigned-clocks = &lt;&amp;bpmp TEGRA186_CLK_DMIC2&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;bpmp TEGRA186_CLK_PLL_A_OUT0&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;3072000&gt;;</div><div class='add'>+				sound-name-prefix = "DMIC2";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_dmic3: dmic@2904200 {</div><div class='add'>+				compatible = "nvidia,tegra210-dmic";</div><div class='add'>+				reg = &lt;0x0 0x2904200 0x0 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;bpmp TEGRA186_CLK_DMIC3&gt;;</div><div class='add'>+				clock-names = "dmic";</div><div class='add'>+				assigned-clocks = &lt;&amp;bpmp TEGRA186_CLK_DMIC3&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;bpmp TEGRA186_CLK_PLL_A_OUT0&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;3072000&gt;;</div><div class='add'>+				sound-name-prefix = "DMIC3";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_dmic4: dmic@2904300 {</div><div class='add'>+				compatible = "nvidia,tegra210-dmic";</div><div class='add'>+				reg = &lt;0x0 0x2904300 0x0 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;bpmp TEGRA186_CLK_DMIC4&gt;;</div><div class='add'>+				clock-names = "dmic";</div><div class='add'>+				assigned-clocks = &lt;&amp;bpmp TEGRA186_CLK_DMIC4&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;bpmp TEGRA186_CLK_PLL_A_OUT0&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;3072000&gt;;</div><div class='add'>+				sound-name-prefix = "DMIC4";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_dspk1: dspk@2905000 {</div><div class='add'>+				compatible = "nvidia,tegra186-dspk";</div><div class='add'>+				reg = &lt;0x0 0x2905000 0x0 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;bpmp TEGRA186_CLK_DSPK1&gt;;</div><div class='add'>+				clock-names = "dspk";</div><div class='add'>+				assigned-clocks = &lt;&amp;bpmp TEGRA186_CLK_DSPK1&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;bpmp TEGRA186_CLK_PLL_A_OUT0&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;12288000&gt;;</div><div class='add'>+				sound-name-prefix = "DSPK1";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_dspk2: dspk@2905100 {</div><div class='add'>+				compatible = "nvidia,tegra186-dspk";</div><div class='add'>+				reg = &lt;0x0 0x2905100 0x0 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;bpmp TEGRA186_CLK_DSPK2&gt;;</div><div class='add'>+				clock-names = "dspk";</div><div class='add'>+				assigned-clocks = &lt;&amp;bpmp TEGRA186_CLK_DSPK2&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;bpmp TEGRA186_CLK_PLL_A_OUT0&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;12288000&gt;;</div><div class='add'>+				sound-name-prefix = "DSPK2";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_ope1: processing-engine@2908000 {</div><div class='add'>+				compatible = "nvidia,tegra186-ope",</div><div class='add'>+					     "nvidia,tegra210-ope";</div><div class='add'>+				reg = &lt;0x0 0x2908000 0x0 0x100&gt;;</div><div class='add'>+				#address-cells = &lt;2&gt;;</div><div class='add'>+				#size-cells = &lt;2&gt;;</div><div class='add'>+				ranges;</div><div class='add'>+				sound-name-prefix = "OPE1";</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				equalizer@2908100 {</div><div class='add'>+					compatible = "nvidia,tegra186-peq",</div><div class='add'>+						     "nvidia,tegra210-peq";</div><div class='add'>+					reg = &lt;0x0 0x2908100 0x0 0x100&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				dynamic-range-compressor@2908200 {</div><div class='add'>+					compatible = "nvidia,tegra186-mbdrc",</div><div class='add'>+						     "nvidia,tegra210-mbdrc";</div><div class='add'>+					reg = &lt;0x0 0x2908200 0x0 0x200&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_mvc1: mvc@290a000 {</div><div class='add'>+				compatible = "nvidia,tegra186-mvc",</div><div class='add'>+					     "nvidia,tegra210-mvc";</div><div class='add'>+				reg = &lt;0x0 0x290a000 0x0 0x200&gt;;</div><div class='add'>+				sound-name-prefix = "MVC1";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_mvc2: mvc@290a200 {</div><div class='add'>+				compatible = "nvidia,tegra186-mvc",</div><div class='add'>+					     "nvidia,tegra210-mvc";</div><div class='add'>+				reg = &lt;0x0 0x290a200 0x0 0x200&gt;;</div><div class='add'>+				sound-name-prefix = "MVC2";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_amixer: amixer@290bb00 {</div><div class='add'>+				compatible = "nvidia,tegra186-amixer",</div><div class='add'>+					     "nvidia,tegra210-amixer";</div><div class='add'>+				reg = &lt;0x0 0x290bb00 0x0 0x800&gt;;</div><div class='add'>+				sound-name-prefix = "MIXER1";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_admaif: admaif@290f000 {</div><div class='add'>+				compatible = "nvidia,tegra186-admaif";</div><div class='add'>+				reg = &lt;0x0 0x0290f000 0x0 0x1000&gt;;</div><div class='add'>+				dmas = &lt;&amp;adma 1&gt;, &lt;&amp;adma 1&gt;,</div><div class='add'>+				       &lt;&amp;adma 2&gt;, &lt;&amp;adma 2&gt;,</div><div class='add'>+				       &lt;&amp;adma 3&gt;, &lt;&amp;adma 3&gt;,</div><div class='add'>+				       &lt;&amp;adma 4&gt;, &lt;&amp;adma 4&gt;,</div><div class='add'>+				       &lt;&amp;adma 5&gt;, &lt;&amp;adma 5&gt;,</div><div class='add'>+				       &lt;&amp;adma 6&gt;, &lt;&amp;adma 6&gt;,</div><div class='add'>+				       &lt;&amp;adma 7&gt;, &lt;&amp;adma 7&gt;,</div><div class='add'>+				       &lt;&amp;adma 8&gt;, &lt;&amp;adma 8&gt;,</div><div class='add'>+				       &lt;&amp;adma 9&gt;, &lt;&amp;adma 9&gt;,</div><div class='add'>+				       &lt;&amp;adma 10&gt;, &lt;&amp;adma 10&gt;,</div><div class='add'>+				       &lt;&amp;adma 11&gt;, &lt;&amp;adma 11&gt;,</div><div class='add'>+				       &lt;&amp;adma 12&gt;, &lt;&amp;adma 12&gt;,</div><div class='add'>+				       &lt;&amp;adma 13&gt;, &lt;&amp;adma 13&gt;,</div><div class='add'>+				       &lt;&amp;adma 14&gt;, &lt;&amp;adma 14&gt;,</div><div class='add'>+				       &lt;&amp;adma 15&gt;, &lt;&amp;adma 15&gt;,</div><div class='add'>+				       &lt;&amp;adma 16&gt;, &lt;&amp;adma 16&gt;,</div><div class='add'>+				       &lt;&amp;adma 17&gt;, &lt;&amp;adma 17&gt;,</div><div class='add'>+				       &lt;&amp;adma 18&gt;, &lt;&amp;adma 18&gt;,</div><div class='add'>+				       &lt;&amp;adma 19&gt;, &lt;&amp;adma 19&gt;,</div><div class='add'>+				       &lt;&amp;adma 20&gt;, &lt;&amp;adma 20&gt;;</div><div class='add'>+				dma-names = "rx1", "tx1",</div><div class='add'>+					    "rx2", "tx2",</div><div class='add'>+					    "rx3", "tx3",</div><div class='add'>+					    "rx4", "tx4",</div><div class='add'>+					    "rx5", "tx5",</div><div class='add'>+					    "rx6", "tx6",</div><div class='add'>+					    "rx7", "tx7",</div><div class='add'>+					    "rx8", "tx8",</div><div class='add'>+					    "rx9", "tx9",</div><div class='add'>+					    "rx10", "tx10",</div><div class='add'>+					    "rx11", "tx11",</div><div class='add'>+					    "rx12", "tx12",</div><div class='add'>+					    "rx13", "tx13",</div><div class='add'>+					    "rx14", "tx14",</div><div class='add'>+					    "rx15", "tx15",</div><div class='add'>+					    "rx16", "tx16",</div><div class='add'>+					    "rx17", "tx17",</div><div class='add'>+					    "rx18", "tx18",</div><div class='add'>+					    "rx19", "tx19",</div><div class='add'>+					    "rx20", "tx20";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_asrc: asrc@2910000 {</div><div class='add'>+				compatible = "nvidia,tegra186-asrc";</div><div class='add'>+				reg = &lt;0x0 0x2910000 0x0 0x2000&gt;;</div><div class='add'>+				sound-name-prefix = "ASRC1";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		adma: dma-controller@2930000 {</div><div class='ctx'> 			compatible = "nvidia,tegra186-adma";</div><div class='del'>-			reg = &lt;0x02930000 0x20000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x02930000 0x0 0x20000&gt;;</div><div class='ctx'> 			interrupt-parent = &lt;&amp;agic&gt;;</div><div class='ctx'> 			interrupts =  &lt;GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 				      &lt;GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='hunk'>@@ -129,8 +548,8 @@</div><div class='ctx'> 				     "nvidia,tegra210-agic";</div><div class='ctx'> 			#interrupt-cells = &lt;3&gt;;</div><div class='ctx'> 			interrupt-controller;</div><div class='del'>-			reg = &lt;0x02a41000 0x1000&gt;,</div><div class='del'>-			      &lt;0x02a42000 0x2000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x02a41000 0x0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0x02a42000 0x0 0x2000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 145</div><div class='ctx'> 				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;bpmp TEGRA186_CLK_APE&gt;;</div><div class='hunk'>@@ -139,12 +558,19 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	memory-controller@2c00000 {</div><div class='add'>+	mc: memory-controller@2c00000 {</div><div class='ctx'> 		compatible = "nvidia,tegra186-mc";</div><div class='del'>-		reg = &lt;0x0 0x02c00000 0x0 0xb0000&gt;;</div><div class='add'>+		reg = &lt;0x0 0x02c00000 0x0 0x10000&gt;,    /* MC-SID */</div><div class='add'>+		      &lt;0x0 0x02c10000 0x0 0x10000&gt;,    /* Broadcast channel */</div><div class='add'>+		      &lt;0x0 0x02c20000 0x0 0x10000&gt;,    /* MC0 */</div><div class='add'>+		      &lt;0x0 0x02c30000 0x0 0x10000&gt;,    /* MC1 */</div><div class='add'>+		      &lt;0x0 0x02c40000 0x0 0x10000&gt;,    /* MC2 */</div><div class='add'>+		      &lt;0x0 0x02c50000 0x0 0x10000&gt;;    /* MC3 */</div><div class='add'>+		reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3";</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> </div><div class='add'>+		#interconnect-cells = &lt;1&gt;;</div><div class='ctx'> 		#address-cells = &lt;2&gt;;</div><div class='ctx'> 		#size-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -163,19 +589,37 @@</div><div class='ctx'> 			clocks = &lt;&amp;bpmp TEGRA186_CLK_EMC&gt;;</div><div class='ctx'> 			clock-names = "emc";</div><div class='ctx'> </div><div class='add'>+			#interconnect-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='ctx'> 			nvidia,bpmp = &lt;&amp;bpmp&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	timer@3010000 {</div><div class='add'>+		compatible = "nvidia,tegra186-timer";</div><div class='add'>+		reg = &lt;0x0 0x03010000 0x0 0x000e0000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	uarta: serial@3100000 {</div><div class='ctx'> 		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";</div><div class='ctx'> 		reg = &lt;0x0 0x03100000 0x0 0x40&gt;;</div><div class='ctx'> 		reg-shift = &lt;2&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		clocks = &lt;&amp;bpmp TEGRA186_CLK_UARTA&gt;;</div><div class='del'>-		clock-names = "serial";</div><div class='ctx'> 		resets = &lt;&amp;bpmp TEGRA186_RESET_UARTA&gt;;</div><div class='del'>-		reset-names = "serial";</div><div class='add'>+		dmas = &lt;&amp;gpcdma 8&gt;, &lt;&amp;gpcdma 8&gt;;</div><div class='add'>+		dma-names = "rx", "tx";</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -185,9 +629,9 @@</div><div class='ctx'> 		reg-shift = &lt;2&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		clocks = &lt;&amp;bpmp TEGRA186_CLK_UARTB&gt;;</div><div class='del'>-		clock-names = "serial";</div><div class='ctx'> 		resets = &lt;&amp;bpmp TEGRA186_RESET_UARTB&gt;;</div><div class='del'>-		reset-names = "serial";</div><div class='add'>+		dmas = &lt;&amp;gpcdma 9&gt;, &lt;&amp;gpcdma 9&gt;;</div><div class='add'>+		dma-names = "rx", "tx";</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -197,9 +641,9 @@</div><div class='ctx'> 		reg-shift = &lt;2&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		clocks = &lt;&amp;bpmp TEGRA186_CLK_UARTD&gt;;</div><div class='del'>-		clock-names = "serial";</div><div class='ctx'> 		resets = &lt;&amp;bpmp TEGRA186_RESET_UARTD&gt;;</div><div class='del'>-		reset-names = "serial";</div><div class='add'>+		dmas = &lt;&amp;gpcdma 19&gt;, &lt;&amp;gpcdma 19&gt;;</div><div class='add'>+		dma-names = "rx", "tx";</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -209,9 +653,9 @@</div><div class='ctx'> 		reg-shift = &lt;2&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		clocks = &lt;&amp;bpmp TEGRA186_CLK_UARTE&gt;;</div><div class='del'>-		clock-names = "serial";</div><div class='ctx'> 		resets = &lt;&amp;bpmp TEGRA186_RESET_UARTE&gt;;</div><div class='del'>-		reset-names = "serial";</div><div class='add'>+		dmas = &lt;&amp;gpcdma 20&gt;, &lt;&amp;gpcdma 20&gt;;</div><div class='add'>+		dma-names = "rx", "tx";</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -221,14 +665,14 @@</div><div class='ctx'> 		reg-shift = &lt;2&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		clocks = &lt;&amp;bpmp TEGRA186_CLK_UARTF&gt;;</div><div class='del'>-		clock-names = "serial";</div><div class='ctx'> 		resets = &lt;&amp;bpmp TEGRA186_RESET_UARTF&gt;;</div><div class='del'>-		reset-names = "serial";</div><div class='add'>+		dmas = &lt;&amp;gpcdma 12&gt;, &lt;&amp;gpcdma 12&gt;;</div><div class='add'>+		dma-names = "rx", "tx";</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	gen1_i2c: i2c@3160000 {</div><div class='del'>-		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";</div><div class='add'>+		compatible = "nvidia,tegra186-i2c";</div><div class='ctx'> 		reg = &lt;0x0 0x03160000 0x0 0x10000&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='hunk'>@@ -237,11 +681,13 @@</div><div class='ctx'> 		clock-names = "div-clk";</div><div class='ctx'> 		resets = &lt;&amp;bpmp TEGRA186_RESET_I2C1&gt;;</div><div class='ctx'> 		reset-names = "i2c";</div><div class='add'>+		dmas = &lt;&amp;gpcdma 21&gt;, &lt;&amp;gpcdma 21&gt;;</div><div class='add'>+		dma-names = "rx", "tx";</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	cam_i2c: i2c@3180000 {</div><div class='del'>-		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";</div><div class='add'>+		compatible = "nvidia,tegra186-i2c";</div><div class='ctx'> 		reg = &lt;0x0 0x03180000 0x0 0x10000&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='hunk'>@@ -250,12 +696,14 @@</div><div class='ctx'> 		clock-names = "div-clk";</div><div class='ctx'> 		resets = &lt;&amp;bpmp TEGRA186_RESET_I2C3&gt;;</div><div class='ctx'> 		reset-names = "i2c";</div><div class='add'>+		dmas = &lt;&amp;gpcdma 23&gt;, &lt;&amp;gpcdma 23&gt;;</div><div class='add'>+		dma-names = "rx", "tx";</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	/* shares pads with dpaux1 */</div><div class='ctx'> 	dp_aux_ch1_i2c: i2c@3190000 {</div><div class='del'>-		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";</div><div class='add'>+		compatible = "nvidia,tegra186-i2c";</div><div class='ctx'> 		reg = &lt;0x0 0x03190000 0x0 0x10000&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='hunk'>@@ -267,12 +715,14 @@</div><div class='ctx'> 		pinctrl-names = "default", "idle";</div><div class='ctx'> 		pinctrl-0 = &lt;&amp;state_dpaux1_i2c&gt;;</div><div class='ctx'> 		pinctrl-1 = &lt;&amp;state_dpaux1_off&gt;;</div><div class='add'>+		dmas = &lt;&amp;gpcdma 26&gt;, &lt;&amp;gpcdma 26&gt;;</div><div class='add'>+		dma-names = "rx", "tx";</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	/* controlled by BPMP, should not be enabled */</div><div class='ctx'> 	pwr_i2c: i2c@31a0000 {</div><div class='del'>-		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";</div><div class='add'>+		compatible = "nvidia,tegra186-i2c";</div><div class='ctx'> 		reg = &lt;0x0 0x031a0000 0x0 0x10000&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='hunk'>@@ -286,7 +736,7 @@</div><div class='ctx'> </div><div class='ctx'> 	/* shares pads with dpaux0 */</div><div class='ctx'> 	dp_aux_ch0_i2c: i2c@31b0000 {</div><div class='del'>-		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";</div><div class='add'>+		compatible = "nvidia,tegra186-i2c";</div><div class='ctx'> 		reg = &lt;0x0 0x031b0000 0x0 0x10000&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='hunk'>@@ -298,11 +748,13 @@</div><div class='ctx'> 		pinctrl-names = "default", "idle";</div><div class='ctx'> 		pinctrl-0 = &lt;&amp;state_dpaux_i2c&gt;;</div><div class='ctx'> 		pinctrl-1 = &lt;&amp;state_dpaux_off&gt;;</div><div class='add'>+		dmas = &lt;&amp;gpcdma 30&gt;, &lt;&amp;gpcdma 30&gt;;</div><div class='add'>+		dma-names = "rx", "tx";</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	gen7_i2c: i2c@31c0000 {</div><div class='del'>-		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";</div><div class='add'>+		compatible = "nvidia,tegra186-i2c";</div><div class='ctx'> 		reg = &lt;0x0 0x031c0000 0x0 0x10000&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='hunk'>@@ -311,11 +763,13 @@</div><div class='ctx'> 		clock-names = "div-clk";</div><div class='ctx'> 		resets = &lt;&amp;bpmp TEGRA186_RESET_I2C7&gt;;</div><div class='ctx'> 		reset-names = "i2c";</div><div class='add'>+		dmas = &lt;&amp;gpcdma 27&gt;, &lt;&amp;gpcdma 27&gt;;</div><div class='add'>+		dma-names = "rx", "tx";</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	gen9_i2c: i2c@31e0000 {</div><div class='del'>-		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";</div><div class='add'>+		compatible = "nvidia,tegra186-i2c";</div><div class='ctx'> 		reg = &lt;0x0 0x031e0000 0x0 0x10000&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='hunk'>@@ -324,17 +778,93 @@</div><div class='ctx'> 		clock-names = "div-clk";</div><div class='ctx'> 		resets = &lt;&amp;bpmp TEGRA186_RESET_I2C9&gt;;</div><div class='ctx'> 		reset-names = "i2c";</div><div class='add'>+		dmas = &lt;&amp;gpcdma 31&gt;, &lt;&amp;gpcdma 31&gt;;</div><div class='add'>+		dma-names = "rx", "tx";</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pwm1: pwm@3280000 {</div><div class='add'>+		compatible = "nvidia,tegra186-pwm";</div><div class='add'>+		reg = &lt;0x0 0x3280000 0x0 0x10000&gt;;</div><div class='add'>+		clocks = &lt;&amp;bpmp TEGRA186_CLK_PWM1&gt;;</div><div class='add'>+		resets = &lt;&amp;bpmp TEGRA186_RESET_PWM1&gt;;</div><div class='add'>+		reset-names = "pwm";</div><div class='add'>+		status = "disabled";</div><div class='add'>+		#pwm-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pwm2: pwm@3290000 {</div><div class='add'>+		compatible = "nvidia,tegra186-pwm";</div><div class='add'>+		reg = &lt;0x0 0x3290000 0x0 0x10000&gt;;</div><div class='add'>+		clocks = &lt;&amp;bpmp TEGRA186_CLK_PWM2&gt;;</div><div class='add'>+		resets = &lt;&amp;bpmp TEGRA186_RESET_PWM2&gt;;</div><div class='add'>+		reset-names = "pwm";</div><div class='add'>+		status = "disabled";</div><div class='add'>+		#pwm-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pwm3: pwm@32a0000 {</div><div class='add'>+		compatible = "nvidia,tegra186-pwm";</div><div class='add'>+		reg = &lt;0x0 0x32a0000 0x0 0x10000&gt;;</div><div class='add'>+		clocks = &lt;&amp;bpmp TEGRA186_CLK_PWM3&gt;;</div><div class='add'>+		resets = &lt;&amp;bpmp TEGRA186_RESET_PWM3&gt;;</div><div class='add'>+		reset-names = "pwm";</div><div class='ctx'> 		status = "disabled";</div><div class='add'>+		#pwm-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sdmmc1: sdhci@3400000 {</div><div class='add'>+	pwm5: pwm@32c0000 {</div><div class='add'>+		compatible = "nvidia,tegra186-pwm";</div><div class='add'>+		reg = &lt;0x0 0x32c0000 0x0 0x10000&gt;;</div><div class='add'>+		clocks = &lt;&amp;bpmp TEGRA186_CLK_PWM5&gt;;</div><div class='add'>+		resets = &lt;&amp;bpmp TEGRA186_RESET_PWM5&gt;;</div><div class='add'>+		reset-names = "pwm";</div><div class='add'>+		status = "disabled";</div><div class='add'>+		#pwm-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pwm6: pwm@32d0000 {</div><div class='add'>+		compatible = "nvidia,tegra186-pwm";</div><div class='add'>+		reg = &lt;0x0 0x32d0000 0x0 0x10000&gt;;</div><div class='add'>+		clocks = &lt;&amp;bpmp TEGRA186_CLK_PWM6&gt;;</div><div class='add'>+		resets = &lt;&amp;bpmp TEGRA186_RESET_PWM6&gt;;</div><div class='add'>+		reset-names = "pwm";</div><div class='add'>+		status = "disabled";</div><div class='add'>+		#pwm-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pwm7: pwm@32e0000 {</div><div class='add'>+		compatible = "nvidia,tegra186-pwm";</div><div class='add'>+		reg = &lt;0x0 0x32e0000 0x0 0x10000&gt;;</div><div class='add'>+		clocks = &lt;&amp;bpmp TEGRA186_CLK_PWM7&gt;;</div><div class='add'>+		resets = &lt;&amp;bpmp TEGRA186_RESET_PWM7&gt;;</div><div class='add'>+		reset-names = "pwm";</div><div class='add'>+		status = "disabled";</div><div class='add'>+		#pwm-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pwm8: pwm@32f0000 {</div><div class='add'>+		compatible = "nvidia,tegra186-pwm";</div><div class='add'>+		reg = &lt;0x0 0x32f0000 0x0 0x10000&gt;;</div><div class='add'>+		clocks = &lt;&amp;bpmp TEGRA186_CLK_PWM8&gt;;</div><div class='add'>+		resets = &lt;&amp;bpmp TEGRA186_RESET_PWM8&gt;;</div><div class='add'>+		reset-names = "pwm";</div><div class='add'>+		status = "disabled";</div><div class='add'>+		#pwm-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdmmc1: mmc@3400000 {</div><div class='ctx'> 		compatible = "nvidia,tegra186-sdhci";</div><div class='ctx'> 		reg = &lt;0x0 0x03400000 0x0 0x10000&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-		clocks = &lt;&amp;bpmp TEGRA186_CLK_SDMMC1&gt;;</div><div class='del'>-		clock-names = "sdhci";</div><div class='add'>+		clocks = &lt;&amp;bpmp TEGRA186_CLK_SDMMC1&gt;,</div><div class='add'>+			 &lt;&amp;bpmp TEGRA186_CLK_SDMMC_LEGACY_TM&gt;;</div><div class='add'>+		clock-names = "sdhci", "tmclk";</div><div class='ctx'> 		resets = &lt;&amp;bpmp TEGRA186_RESET_SDMMC1&gt;;</div><div class='ctx'> 		reset-names = "sdhci";</div><div class='add'>+		interconnects = &lt;&amp;mc TEGRA186_MEMORY_CLIENT_SDMMCRA &amp;emc&gt;,</div><div class='add'>+				&lt;&amp;mc TEGRA186_MEMORY_CLIENT_SDMMCWA &amp;emc&gt;;</div><div class='add'>+		interconnect-names = "dma-mem", "write";</div><div class='ctx'> 		iommus = &lt;&amp;smmu TEGRA186_SID_SDMMC1&gt;;</div><div class='ctx'> 		pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";</div><div class='ctx'> 		pinctrl-0 = &lt;&amp;sdmmc1_3v3&gt;;</div><div class='hunk'>@@ -353,14 +883,18 @@</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sdmmc2: sdhci@3420000 {</div><div class='add'>+	sdmmc2: mmc@3420000 {</div><div class='ctx'> 		compatible = "nvidia,tegra186-sdhci";</div><div class='ctx'> 		reg = &lt;0x0 0x03420000 0x0 0x10000&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-		clocks = &lt;&amp;bpmp TEGRA186_CLK_SDMMC2&gt;;</div><div class='del'>-		clock-names = "sdhci";</div><div class='add'>+		clocks = &lt;&amp;bpmp TEGRA186_CLK_SDMMC2&gt;,</div><div class='add'>+			 &lt;&amp;bpmp TEGRA186_CLK_SDMMC_LEGACY_TM&gt;;</div><div class='add'>+		clock-names = "sdhci", "tmclk";</div><div class='ctx'> 		resets = &lt;&amp;bpmp TEGRA186_RESET_SDMMC2&gt;;</div><div class='ctx'> 		reset-names = "sdhci";</div><div class='add'>+		interconnects = &lt;&amp;mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &amp;emc&gt;,</div><div class='add'>+				&lt;&amp;mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &amp;emc&gt;;</div><div class='add'>+		interconnect-names = "dma-mem", "write";</div><div class='ctx'> 		iommus = &lt;&amp;smmu TEGRA186_SID_SDMMC2&gt;;</div><div class='ctx'> 		pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";</div><div class='ctx'> 		pinctrl-0 = &lt;&amp;sdmmc2_3v3&gt;;</div><div class='hunk'>@@ -374,14 +908,18 @@</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sdmmc3: sdhci@3440000 {</div><div class='add'>+	sdmmc3: mmc@3440000 {</div><div class='ctx'> 		compatible = "nvidia,tegra186-sdhci";</div><div class='ctx'> 		reg = &lt;0x0 0x03440000 0x0 0x10000&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-		clocks = &lt;&amp;bpmp TEGRA186_CLK_SDMMC3&gt;;</div><div class='del'>-		clock-names = "sdhci";</div><div class='add'>+		clocks = &lt;&amp;bpmp TEGRA186_CLK_SDMMC3&gt;,</div><div class='add'>+			 &lt;&amp;bpmp TEGRA186_CLK_SDMMC_LEGACY_TM&gt;;</div><div class='add'>+		clock-names = "sdhci", "tmclk";</div><div class='ctx'> 		resets = &lt;&amp;bpmp TEGRA186_RESET_SDMMC3&gt;;</div><div class='ctx'> 		reset-names = "sdhci";</div><div class='add'>+		interconnects = &lt;&amp;mc TEGRA186_MEMORY_CLIENT_SDMMCR &amp;emc&gt;,</div><div class='add'>+				&lt;&amp;mc TEGRA186_MEMORY_CLIENT_SDMMCW &amp;emc&gt;;</div><div class='add'>+		interconnect-names = "dma-mem", "write";</div><div class='ctx'> 		iommus = &lt;&amp;smmu TEGRA186_SID_SDMMC3&gt;;</div><div class='ctx'> 		pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";</div><div class='ctx'> 		pinctrl-0 = &lt;&amp;sdmmc3_3v3&gt;;</div><div class='hunk'>@@ -397,17 +935,21 @@</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sdmmc4: sdhci@3460000 {</div><div class='add'>+	sdmmc4: mmc@3460000 {</div><div class='ctx'> 		compatible = "nvidia,tegra186-sdhci";</div><div class='ctx'> 		reg = &lt;0x0 0x03460000 0x0 0x10000&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-		clocks = &lt;&amp;bpmp TEGRA186_CLK_SDMMC4&gt;;</div><div class='del'>-		clock-names = "sdhci";</div><div class='add'>+		clocks = &lt;&amp;bpmp TEGRA186_CLK_SDMMC4&gt;,</div><div class='add'>+			 &lt;&amp;bpmp TEGRA186_CLK_SDMMC_LEGACY_TM&gt;;</div><div class='add'>+		clock-names = "sdhci", "tmclk";</div><div class='ctx'> 		assigned-clocks = &lt;&amp;bpmp TEGRA186_CLK_SDMMC4&gt;,</div><div class='ctx'> 				  &lt;&amp;bpmp TEGRA186_CLK_PLLC4_VCO&gt;;</div><div class='ctx'> 		assigned-clock-parents = &lt;&amp;bpmp TEGRA186_CLK_PLLC4_VCO&gt;;</div><div class='ctx'> 		resets = &lt;&amp;bpmp TEGRA186_RESET_SDMMC4&gt;;</div><div class='ctx'> 		reset-names = "sdhci";</div><div class='add'>+		interconnects = &lt;&amp;mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &amp;emc&gt;,</div><div class='add'>+				&lt;&amp;mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &amp;emc&gt;;</div><div class='add'>+		interconnect-names = "dma-mem", "write";</div><div class='ctx'> 		iommus = &lt;&amp;smmu TEGRA186_SID_SDMMC4&gt;;</div><div class='ctx'> 		nvidia,pad-autocal-pull-up-offset-hs400 = &lt;0x05&gt;;</div><div class='ctx'> 		nvidia,pad-autocal-pull-down-offset-hs400 = &lt;0x05&gt;;</div><div class='hunk'>@@ -423,6 +965,34 @@</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	sata@3507000 {</div><div class='add'>+		compatible = "nvidia,tegra186-ahci";</div><div class='add'>+		reg = &lt;0x0 0x03507000 0x0 0x00002000&gt;, /* AHCI */</div><div class='add'>+		      &lt;0x0 0x03500000 0x0 0x00007000&gt;, /* SATA */</div><div class='add'>+		      &lt;0x0 0x03A90000 0x0 0x00010000&gt;; /* SATA AUX */</div><div class='add'>+		interrupts = &lt;GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+		power-domains = &lt;&amp;bpmp TEGRA186_POWER_DOMAIN_SAX&gt;;</div><div class='add'>+		interconnects = &lt;&amp;mc TEGRA186_MEMORY_CLIENT_SATAR &amp;emc&gt;,</div><div class='add'>+				&lt;&amp;mc TEGRA186_MEMORY_CLIENT_SATAW &amp;emc&gt;;</div><div class='add'>+		interconnect-names = "dma-mem", "write";</div><div class='add'>+		iommus = &lt;&amp;smmu TEGRA186_SID_SATA&gt;;</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;bpmp TEGRA186_CLK_SATA&gt;,</div><div class='add'>+			 &lt;&amp;bpmp TEGRA186_CLK_SATA_OOB&gt;;</div><div class='add'>+		clock-names = "sata", "sata-oob";</div><div class='add'>+		assigned-clocks = &lt;&amp;bpmp TEGRA186_CLK_SATA&gt;,</div><div class='add'>+				  &lt;&amp;bpmp TEGRA186_CLK_SATA_OOB&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;&amp;bpmp TEGRA186_CLK_PLLP_OUT0&gt;,</div><div class='add'>+					 &lt;&amp;bpmp TEGRA186_CLK_PLLP&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;102000000&gt;,</div><div class='add'>+				       &lt;204000000&gt;;</div><div class='add'>+		resets = &lt;&amp;bpmp TEGRA186_RESET_SATA&gt;,</div><div class='add'>+			&lt;&amp;bpmp TEGRA186_RESET_SATACOLD&gt;;</div><div class='add'>+		reset-names = "sata", "sata-cold";</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	hda@3510000 {</div><div class='ctx'> 		compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda";</div><div class='ctx'> 		reg = &lt;0x0 0x03510000 0x0 0x10000&gt;;</div><div class='hunk'>@@ -436,6 +1006,9 @@</div><div class='ctx'> 			 &lt;&amp;bpmp TEGRA186_RESET_HDA2CODEC_2X&gt;;</div><div class='ctx'> 		reset-names = "hda", "hda2hdmi", "hda2codec_2x";</div><div class='ctx'> 		power-domains = &lt;&amp;bpmp TEGRA186_POWER_DOMAIN_DISP&gt;;</div><div class='add'>+		interconnects = &lt;&amp;mc TEGRA186_MEMORY_CLIENT_HDAR &amp;emc&gt;,</div><div class='add'>+				&lt;&amp;mc TEGRA186_MEMORY_CLIENT_HDAW &amp;emc&gt;;</div><div class='add'>+		interconnect-names = "dma-mem", "write";</div><div class='ctx'> 		iommus = &lt;&amp;smmu TEGRA186_SID_HDA&gt;;</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='hunk'>@@ -445,6 +1018,7 @@</div><div class='ctx'> 		reg = &lt;0x0 0x03520000 0x0 0x1000&gt;,</div><div class='ctx'> 		      &lt;0x0 0x03540000 0x0 0x1000&gt;;</div><div class='ctx'> 		reg-names = "padctl", "ao";</div><div class='add'>+		interrupts = &lt;GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> </div><div class='ctx'> 		resets = &lt;&amp;bpmp TEGRA186_RESET_XUSB_PADCTL&gt;;</div><div class='ctx'> 		reset-names = "padctl";</div><div class='hunk'>@@ -547,8 +1121,7 @@</div><div class='ctx'> 		      &lt;0x0 0x03538000 0x0 0x1000&gt;;</div><div class='ctx'> 		reg-names = "hcd", "fpci";</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-			     &lt;GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-			     &lt;GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			     &lt;GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		clocks = &lt;&amp;bpmp TEGRA186_CLK_XUSB_HOST&gt;,</div><div class='ctx'> 			 &lt;&amp;bpmp TEGRA186_CLK_XUSB_FALCON&gt;,</div><div class='ctx'> 			 &lt;&amp;bpmp TEGRA186_CLK_XUSB_SS&gt;,</div><div class='hunk'>@@ -564,6 +1137,9 @@</div><div class='ctx'> 		power-domains = &lt;&amp;bpmp TEGRA186_POWER_DOMAIN_XUSBC&gt;,</div><div class='ctx'> 				&lt;&amp;bpmp TEGRA186_POWER_DOMAIN_XUSBA&gt;;</div><div class='ctx'> 		power-domain-names = "xusb_host", "xusb_ss";</div><div class='add'>+		interconnects = &lt;&amp;mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &amp;emc&gt;,</div><div class='add'>+				&lt;&amp;mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &amp;emc&gt;;</div><div class='add'>+		interconnect-names = "dma-mem", "write";</div><div class='ctx'> 		iommus = &lt;&amp;smmu TEGRA186_SID_XUSB_HOST&gt;;</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;0&gt;;</div><div class='hunk'>@@ -583,6 +1159,9 @@</div><div class='ctx'> 			 &lt;&amp;bpmp TEGRA186_CLK_XUSB_CORE_SS&gt;,</div><div class='ctx'> 			 &lt;&amp;bpmp TEGRA186_CLK_XUSB_FS&gt;;</div><div class='ctx'> 		clock-names = "dev", "ss", "ss_src", "fs_src";</div><div class='add'>+		interconnects = &lt;&amp;mc TEGRA186_MEMORY_CLIENT_XUSB_DEVR &amp;emc&gt;,</div><div class='add'>+				&lt;&amp;mc TEGRA186_MEMORY_CLIENT_XUSB_DEVW &amp;emc&gt;;</div><div class='add'>+		interconnect-names = "dma-mem", "write";</div><div class='ctx'> 		iommus = &lt;&amp;smmu TEGRA186_SID_XUSB_DEV&gt;;</div><div class='ctx'> 		power-domains = &lt;&amp;bpmp TEGRA186_POWER_DOMAIN_XUSBB&gt;,</div><div class='ctx'> 				&lt;&amp;bpmp TEGRA186_POWER_DOMAIN_XUSBA&gt;;</div><div class='hunk'>@@ -600,17 +1179,20 @@</div><div class='ctx'> </div><div class='ctx'> 	gic: interrupt-controller@3881000 {</div><div class='ctx'> 		compatible = "arm,gic-400";</div><div class='add'>+		#address-cells = &lt;0&gt;;</div><div class='ctx'> 		#interrupt-cells = &lt;3&gt;;</div><div class='ctx'> 		interrupt-controller;</div><div class='ctx'> 		reg = &lt;0x0 0x03881000 0x0 0x1000&gt;,</div><div class='del'>-		      &lt;0x0 0x03882000 0x0 0x2000&gt;;</div><div class='add'>+		      &lt;0x0 0x03882000 0x0 0x2000&gt;,</div><div class='add'>+		      &lt;0x0 0x03884000 0x0 0x2000&gt;,</div><div class='add'>+		      &lt;0x0 0x03886000 0x0 0x2000&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_PPI 9</div><div class='ctx'> 			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='ctx'> 		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	cec@3960000 {</div><div class='del'>-		compatible = "nvidia,tegra186-cec";</div><div class='add'>+		compatible = "nvidia,tegra186-cec", "nvidia,tegra210-cec";</div><div class='ctx'> 		reg = &lt;0x0 0x03960000 0x0 0x10000&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		clocks = &lt;&amp;bpmp TEGRA186_CLK_CEC&gt;;</div><div class='hunk'>@@ -628,7 +1210,7 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	gen2_i2c: i2c@c240000 {</div><div class='del'>-		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";</div><div class='add'>+		compatible = "nvidia,tegra186-i2c";</div><div class='ctx'> 		reg = &lt;0x0 0x0c240000 0x0 0x10000&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='hunk'>@@ -637,11 +1219,13 @@</div><div class='ctx'> 		clock-names = "div-clk";</div><div class='ctx'> 		resets = &lt;&amp;bpmp TEGRA186_RESET_I2C2&gt;;</div><div class='ctx'> 		reset-names = "i2c";</div><div class='add'>+		dmas = &lt;&amp;gpcdma 22&gt;, &lt;&amp;gpcdma 22&gt;;</div><div class='add'>+		dma-names = "rx", "tx";</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	gen8_i2c: i2c@c250000 {</div><div class='del'>-		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";</div><div class='add'>+		compatible = "nvidia,tegra186-i2c";</div><div class='ctx'> 		reg = &lt;0x0 0x0c250000 0x0 0x10000&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='hunk'>@@ -650,6 +1234,8 @@</div><div class='ctx'> 		clock-names = "div-clk";</div><div class='ctx'> 		resets = &lt;&amp;bpmp TEGRA186_RESET_I2C8&gt;;</div><div class='ctx'> 		reset-names = "i2c";</div><div class='add'>+		dmas = &lt;&amp;gpcdma 0&gt;, &lt;&amp;gpcdma 0&gt;;</div><div class='add'>+		dma-names = "rx", "tx";</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -659,9 +1245,9 @@</div><div class='ctx'> 		reg-shift = &lt;2&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		clocks = &lt;&amp;bpmp TEGRA186_CLK_UARTC&gt;;</div><div class='del'>-		clock-names = "serial";</div><div class='ctx'> 		resets = &lt;&amp;bpmp TEGRA186_RESET_UARTC&gt;;</div><div class='del'>-		reset-names = "serial";</div><div class='add'>+		dmas = &lt;&amp;gpcdma 3&gt;, &lt;&amp;gpcdma 3&gt;;</div><div class='add'>+		dma-names = "rx", "tx";</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -671,9 +1257,9 @@</div><div class='ctx'> 		reg-shift = &lt;2&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		clocks = &lt;&amp;bpmp TEGRA186_CLK_UARTG&gt;;</div><div class='del'>-		clock-names = "serial";</div><div class='ctx'> 		resets = &lt;&amp;bpmp TEGRA186_RESET_UARTG&gt;;</div><div class='del'>-		reset-names = "serial";</div><div class='add'>+		dmas = &lt;&amp;gpcdma 2&gt;, &lt;&amp;gpcdma 2&gt;;</div><div class='add'>+		dma-names = "rx", "tx";</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -695,10 +1281,26 @@</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		gpio-controller;</div><div class='ctx'> 		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-ranges = &lt;&amp;pinmux_aon 0 0 47&gt;;</div><div class='ctx'> 		interrupt-controller;</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	pinmux_aon: pinmux@c300000 {</div><div class='add'>+		compatible = "nvidia,tegra186-pinmux-aon";</div><div class='add'>+		reg = &lt;0x0 0xc300000 0x0 0x4000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pwm4: pwm@c340000 {</div><div class='add'>+		compatible = "nvidia,tegra186-pwm";</div><div class='add'>+		reg = &lt;0x0 0xc340000 0x0 0x10000&gt;;</div><div class='add'>+		clocks = &lt;&amp;bpmp TEGRA186_CLK_PWM4&gt;;</div><div class='add'>+		resets = &lt;&amp;bpmp TEGRA186_RESET_PWM4&gt;;</div><div class='add'>+		reset-names = "pwm";</div><div class='add'>+		status = "disabled";</div><div class='add'>+		#pwm-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	pmc: pmc@c360000 {</div><div class='ctx'> 		compatible = "nvidia,tegra186-pmc";</div><div class='ctx'> 		reg = &lt;0 0x0c360000 0 0x10000&gt;,</div><div class='hunk'>@@ -710,18 +1312,13 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 		interrupt-controller;</div><div class='ctx'> </div><div class='del'>-		sdmmc1_3v3: sdmmc1-3v3 {</div><div class='del'>-			pins = "sdmmc1-hv";</div><div class='del'>-			power-source = &lt;TEGRA_IO_PAD_VOLTAGE_3V3&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='ctx'> 		sdmmc1_1v8: sdmmc1-1v8 {</div><div class='ctx'> 			pins = "sdmmc1-hv";</div><div class='ctx'> 			power-source = &lt;TEGRA_IO_PAD_VOLTAGE_1V8&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		sdmmc2_3v3: sdmmc2-3v3 {</div><div class='del'>-			pins = "sdmmc2-hv";</div><div class='add'>+		sdmmc1_3v3: sdmmc1-3v3 {</div><div class='add'>+			pins = "sdmmc1-hv";</div><div class='ctx'> 			power-source = &lt;TEGRA_IO_PAD_VOLTAGE_3V3&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -730,8 +1327,8 @@</div><div class='ctx'> 			power-source = &lt;TEGRA_IO_PAD_VOLTAGE_1V8&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		sdmmc3_3v3: sdmmc3-3v3 {</div><div class='del'>-			pins = "sdmmc3-hv";</div><div class='add'>+		sdmmc2_3v3: sdmmc2-3v3 {</div><div class='add'>+			pins = "sdmmc2-hv";</div><div class='ctx'> 			power-source = &lt;TEGRA_IO_PAD_VOLTAGE_3V3&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -739,11 +1336,16 @@</div><div class='ctx'> 			pins = "sdmmc3-hv";</div><div class='ctx'> 			power-source = &lt;TEGRA_IO_PAD_VOLTAGE_1V8&gt;;</div><div class='ctx'> 		};</div><div class='add'>+</div><div class='add'>+		sdmmc3_3v3: sdmmc3-3v3 {</div><div class='add'>+			pins = "sdmmc3-hv";</div><div class='add'>+			power-source = &lt;TEGRA_IO_PAD_VOLTAGE_3V3&gt;;</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	ccplex@e000000 {</div><div class='ctx'> 		compatible = "nvidia,tegra186-ccplex-cluster";</div><div class='del'>-		reg = &lt;0x0 0x0e000000 0x0 0x3fffff&gt;;</div><div class='add'>+		reg = &lt;0x0 0x0e000000 0x0 0x400000&gt;;</div><div class='ctx'> </div><div class='ctx'> 		nvidia,bpmp = &lt;&amp;bpmp&gt;;</div><div class='ctx'> 	};</div><div class='hunk'>@@ -752,9 +1354,9 @@</div><div class='ctx'> 		compatible = "nvidia,tegra186-pcie";</div><div class='ctx'> 		power-domains = &lt;&amp;bpmp TEGRA186_POWER_DOMAIN_PCX&gt;;</div><div class='ctx'> 		device_type = "pci";</div><div class='del'>-		reg = &lt;0x0 0x10003000 0x0 0x00000800   /* PADS registers */</div><div class='del'>-		       0x0 0x10003800 0x0 0x00000800   /* AFI registers */</div><div class='del'>-		       0x0 0x40000000 0x0 0x10000000&gt;; /* configuration space */</div><div class='add'>+		reg = &lt;0x0 0x10003000 0x0 0x00000800&gt;, /* PADS registers */</div><div class='add'>+		      &lt;0x0 0x10003800 0x0 0x00000800&gt;, /* AFI registers */</div><div class='add'>+		      &lt;0x0 0x40000000 0x0 0x10000000&gt;; /* configuration space */</div><div class='ctx'> 		reg-names = "pads", "afi", "cs";</div><div class='ctx'> </div><div class='ctx'> 		interrupts = &lt;GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH&gt;, /* controller interrupt */</div><div class='hunk'>@@ -769,22 +1371,26 @@</div><div class='ctx'> 		#address-cells = &lt;3&gt;;</div><div class='ctx'> 		#size-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='del'>-		ranges = &lt;0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000   /* port 0 configuration space */</div><div class='del'>-			  0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000   /* port 1 configuration space */</div><div class='del'>-			  0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000   /* port 2 configuration space */</div><div class='del'>-			  0x81000000 0 0x0        0x0 0x50000000 0 0x00010000   /* downstream I/O (64 KiB) */</div><div class='del'>-			  0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000   /* non-prefetchable memory (127 MiB) */</div><div class='del'>-			  0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000&gt;; /* prefetchable memory (640 MiB) */</div><div class='add'>+		ranges = &lt;0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000&gt;, /* port 0 configuration space */</div><div class='add'>+			 &lt;0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000&gt;,/* port 1 configuration space */</div><div class='add'>+			 &lt;0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000&gt;, /* port 2 configuration space */</div><div class='add'>+			 &lt;0x01000000 0 0x0        0x0 0x50000000 0 0x00010000&gt;, /* downstream I/O (64 KiB) */</div><div class='add'>+			 &lt;0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000&gt;, /* non-prefetchable memory (127 MiB) */</div><div class='add'>+			 &lt;0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000&gt;; /* prefetchable memory (640 MiB) */</div><div class='ctx'> </div><div class='del'>-		clocks = &lt;&amp;bpmp TEGRA186_CLK_AFI&gt;,</div><div class='del'>-			 &lt;&amp;bpmp TEGRA186_CLK_PCIE&gt;,</div><div class='add'>+		clocks = &lt;&amp;bpmp TEGRA186_CLK_PCIE&gt;,</div><div class='add'>+			 &lt;&amp;bpmp TEGRA186_CLK_AFI&gt;,</div><div class='ctx'> 			 &lt;&amp;bpmp TEGRA186_CLK_PLLE&gt;;</div><div class='del'>-		clock-names = "afi", "pex", "pll_e";</div><div class='add'>+		clock-names = "pex", "afi", "pll_e";</div><div class='ctx'> </div><div class='del'>-		resets = &lt;&amp;bpmp TEGRA186_RESET_AFI&gt;,</div><div class='del'>-			 &lt;&amp;bpmp TEGRA186_RESET_PCIE&gt;,</div><div class='add'>+		resets = &lt;&amp;bpmp TEGRA186_RESET_PCIE&gt;,</div><div class='add'>+			 &lt;&amp;bpmp TEGRA186_RESET_AFI&gt;,</div><div class='ctx'> 			 &lt;&amp;bpmp TEGRA186_RESET_PCIEXCLK&gt;;</div><div class='del'>-		reset-names = "afi", "pex", "pcie_x";</div><div class='add'>+		reset-names = "pex", "afi", "pcie_x";</div><div class='add'>+</div><div class='add'>+		interconnects = &lt;&amp;mc TEGRA186_MEMORY_CLIENT_AFIR &amp;emc&gt;,</div><div class='add'>+				&lt;&amp;mc TEGRA186_MEMORY_CLIENT_AFIW &amp;emc&gt;;</div><div class='add'>+		interconnect-names = "dma-mem", "write";</div><div class='ctx'> </div><div class='ctx'> 		iommus = &lt;&amp;smmu TEGRA186_SID_AFI&gt;;</div><div class='ctx'> 		iommu-map = &lt;0x0 &amp;smmu TEGRA186_SID_AFI 0x1000&gt;;</div><div class='hunk'>@@ -833,7 +1439,7 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	smmu: iommu@12000000 {</div><div class='del'>-		compatible = "arm,mmu-500";</div><div class='add'>+		compatible = "nvidia,tegra186-smmu", "nvidia,smmu-500";</div><div class='ctx'> 		reg = &lt;0 0x12000000 0 0x800000&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 			     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='hunk'>@@ -903,29 +1509,46 @@</div><div class='ctx'> 		stream-match-mask = &lt;0x7f80&gt;;</div><div class='ctx'> 		#global-interrupts = &lt;1&gt;;</div><div class='ctx'> 		#iommu-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		nvidia,memory-controller = &lt;&amp;mc&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	host1x@13e00000 {</div><div class='del'>-		compatible = "nvidia,tegra186-host1x", "simple-bus";</div><div class='add'>+		compatible = "nvidia,tegra186-host1x";</div><div class='ctx'> 		reg = &lt;0x0 0x13e00000 0x0 0x10000&gt;,</div><div class='ctx'> 		      &lt;0x0 0x13e10000 0x0 0x10000&gt;;</div><div class='ctx'> 		reg-names = "hypervisor", "vm";</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 		             &lt;GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-names = "syncpt", "host1x";</div><div class='ctx'> 		clocks = &lt;&amp;bpmp TEGRA186_CLK_HOST1X&gt;;</div><div class='ctx'> 		clock-names = "host1x";</div><div class='ctx'> 		resets = &lt;&amp;bpmp TEGRA186_RESET_HOST1X&gt;;</div><div class='ctx'> 		reset-names = "host1x";</div><div class='ctx'> </div><div class='del'>-		#address-cells = &lt;1&gt;;</div><div class='del'>-		#size-cells = &lt;1&gt;;</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		ranges = &lt;0x0 0x15000000 0x0 0x15000000 0x0 0x01000000&gt;;</div><div class='add'>+</div><div class='add'>+		interconnects = &lt;&amp;mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &amp;emc&gt;;</div><div class='add'>+		interconnect-names = "dma-mem";</div><div class='ctx'> </div><div class='del'>-		ranges = &lt;0x15000000 0x0 0x15000000 0x01000000&gt;;</div><div class='ctx'> 		iommus = &lt;&amp;smmu TEGRA186_SID_HOST1X&gt;;</div><div class='ctx'> </div><div class='add'>+		/* Context isolation domains */</div><div class='add'>+		iommu-map = &lt;0 &amp;smmu TEGRA186_SID_HOST1X_CTX0 1&gt;,</div><div class='add'>+			    &lt;1 &amp;smmu TEGRA186_SID_HOST1X_CTX1 1&gt;,</div><div class='add'>+			    &lt;2 &amp;smmu TEGRA186_SID_HOST1X_CTX2 1&gt;,</div><div class='add'>+			    &lt;3 &amp;smmu TEGRA186_SID_HOST1X_CTX3 1&gt;,</div><div class='add'>+			    &lt;4 &amp;smmu TEGRA186_SID_HOST1X_CTX4 1&gt;,</div><div class='add'>+			    &lt;5 &amp;smmu TEGRA186_SID_HOST1X_CTX5 1&gt;,</div><div class='add'>+			    &lt;6 &amp;smmu TEGRA186_SID_HOST1X_CTX6 1&gt;,</div><div class='add'>+			    &lt;7 &amp;smmu TEGRA186_SID_HOST1X_CTX7 1&gt;;</div><div class='add'>+</div><div class='ctx'> 		dpaux1: dpaux@15040000 {</div><div class='ctx'> 			compatible = "nvidia,tegra186-dpaux";</div><div class='del'>-			reg = &lt;0x15040000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x15040000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;bpmp TEGRA186_CLK_DPAUX1&gt;,</div><div class='ctx'> 				 &lt;&amp;bpmp TEGRA186_CLK_PLLDP&gt;;</div><div class='hunk'>@@ -958,8 +1581,8 @@</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		display-hub@15200000 {</div><div class='del'>-			compatible = "nvidia,tegra186-display", "simple-bus";</div><div class='del'>-			reg = &lt;0x15200000 0x00040000&gt;;</div><div class='add'>+			compatible = "nvidia,tegra186-display";</div><div class='add'>+			reg = &lt;0x0 0x15200000 0x0 0x00040000&gt;;</div><div class='ctx'> 			resets = &lt;&amp;bpmp TEGRA186_RESET_NVDISPLAY0_MISC&gt;,</div><div class='ctx'> 				 &lt;&amp;bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0&gt;,</div><div class='ctx'> 				 &lt;&amp;bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1&gt;,</div><div class='hunk'>@@ -977,14 +1600,14 @@</div><div class='ctx'> </div><div class='ctx'> 			power-domains = &lt;&amp;bpmp TEGRA186_POWER_DOMAIN_DISP&gt;;</div><div class='ctx'> </div><div class='del'>-			#address-cells = &lt;1&gt;;</div><div class='del'>-			#size-cells = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='del'>-			ranges = &lt;0x15200000 0x15200000 0x40000&gt;;</div><div class='add'>+			ranges = &lt;0x0 0x15200000 0x0 0x15200000 0x0 0x40000&gt;;</div><div class='ctx'> </div><div class='ctx'> 			display@15200000 {</div><div class='ctx'> 				compatible = "nvidia,tegra186-dc";</div><div class='del'>-				reg = &lt;0x15200000 0x10000&gt;;</div><div class='add'>+				reg = &lt;0x0 0x15200000 0x0 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;bpmp TEGRA186_CLK_NVDISPLAY_P0&gt;;</div><div class='ctx'> 				clock-names = "dc";</div><div class='hunk'>@@ -992,6 +1615,9 @@</div><div class='ctx'> 				reset-names = "dc";</div><div class='ctx'> </div><div class='ctx'> 				power-domains = &lt;&amp;bpmp TEGRA186_POWER_DOMAIN_DISP&gt;;</div><div class='add'>+				interconnects = &lt;&amp;mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &amp;emc&gt;,</div><div class='add'>+						&lt;&amp;mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &amp;emc&gt;;</div><div class='add'>+				interconnect-names = "dma-mem", "read-1";</div><div class='ctx'> 				iommus = &lt;&amp;smmu TEGRA186_SID_NVDISPLAY&gt;;</div><div class='ctx'> </div><div class='ctx'> 				nvidia,outputs = &lt;&amp;dsia &amp;dsib &amp;sor0 &amp;sor1&gt;;</div><div class='hunk'>@@ -1000,7 +1626,7 @@</div><div class='ctx'> </div><div class='ctx'> 			display@15210000 {</div><div class='ctx'> 				compatible = "nvidia,tegra186-dc";</div><div class='del'>-				reg = &lt;0x15210000 0x10000&gt;;</div><div class='add'>+				reg = &lt;0x0 0x15210000 0x0 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;bpmp TEGRA186_CLK_NVDISPLAY_P1&gt;;</div><div class='ctx'> 				clock-names = "dc";</div><div class='hunk'>@@ -1008,6 +1634,9 @@</div><div class='ctx'> 				reset-names = "dc";</div><div class='ctx'> </div><div class='ctx'> 				power-domains = &lt;&amp;bpmp TEGRA186_POWER_DOMAIN_DISPB&gt;;</div><div class='add'>+				interconnects = &lt;&amp;mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &amp;emc&gt;,</div><div class='add'>+						&lt;&amp;mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &amp;emc&gt;;</div><div class='add'>+				interconnect-names = "dma-mem", "read-1";</div><div class='ctx'> 				iommus = &lt;&amp;smmu TEGRA186_SID_NVDISPLAY&gt;;</div><div class='ctx'> </div><div class='ctx'> 				nvidia,outputs = &lt;&amp;dsia &amp;dsib &amp;sor0 &amp;sor1&gt;;</div><div class='hunk'>@@ -1016,7 +1645,7 @@</div><div class='ctx'> </div><div class='ctx'> 			display@15220000 {</div><div class='ctx'> 				compatible = "nvidia,tegra186-dc";</div><div class='del'>-				reg = &lt;0x15220000 0x10000&gt;;</div><div class='add'>+				reg = &lt;0x0 0x15220000 0x0 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;bpmp TEGRA186_CLK_NVDISPLAY_P2&gt;;</div><div class='ctx'> 				clock-names = "dc";</div><div class='hunk'>@@ -1024,6 +1653,9 @@</div><div class='ctx'> 				reset-names = "dc";</div><div class='ctx'> </div><div class='ctx'> 				power-domains = &lt;&amp;bpmp TEGRA186_POWER_DOMAIN_DISPC&gt;;</div><div class='add'>+				interconnects = &lt;&amp;mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &amp;emc&gt;,</div><div class='add'>+						&lt;&amp;mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &amp;emc&gt;;</div><div class='add'>+				interconnect-names = "dma-mem", "read-1";</div><div class='ctx'> 				iommus = &lt;&amp;smmu TEGRA186_SID_NVDISPLAY&gt;;</div><div class='ctx'> </div><div class='ctx'> 				nvidia,outputs = &lt;&amp;sor0 &amp;sor1&gt;;</div><div class='hunk'>@@ -1033,7 +1665,7 @@</div><div class='ctx'> </div><div class='ctx'> 		dsia: dsi@15300000 {</div><div class='ctx'> 			compatible = "nvidia,tegra186-dsi";</div><div class='del'>-			reg = &lt;0x15300000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x15300000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;bpmp TEGRA186_CLK_DSI&gt;,</div><div class='ctx'> 				 &lt;&amp;bpmp TEGRA186_CLK_DSIA_LP&gt;,</div><div class='hunk'>@@ -1048,7 +1680,7 @@</div><div class='ctx'> </div><div class='ctx'> 		vic@15340000 {</div><div class='ctx'> 			compatible = "nvidia,tegra186-vic";</div><div class='del'>-			reg = &lt;0x15340000 0x40000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x15340000 0x0 0x40000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;bpmp TEGRA186_CLK_VIC&gt;;</div><div class='ctx'> 			clock-names = "vic";</div><div class='hunk'>@@ -1056,12 +1688,30 @@</div><div class='ctx'> 			reset-names = "vic";</div><div class='ctx'> </div><div class='ctx'> 			power-domains = &lt;&amp;bpmp TEGRA186_POWER_DOMAIN_VIC&gt;;</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA186_MEMORY_CLIENT_VICSRD &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA186_MEMORY_CLIENT_VICSWR &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem", "write";</div><div class='ctx'> 			iommus = &lt;&amp;smmu TEGRA186_SID_VIC&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		nvjpg@15380000 {</div><div class='add'>+			compatible = "nvidia,tegra186-nvjpg";</div><div class='add'>+			reg = &lt;0x0 0x15380000 0x0 0x40000&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA186_CLK_NVJPG&gt;;</div><div class='add'>+			clock-names = "nvjpg";</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA186_RESET_NVJPG&gt;;</div><div class='add'>+			reset-names = "nvjpg";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;bpmp TEGRA186_POWER_DOMAIN_NVJPG&gt;;</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem", "write";</div><div class='add'>+			iommus = &lt;&amp;smmu TEGRA186_SID_NVJPG&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		dsib: dsi@15400000 {</div><div class='ctx'> 			compatible = "nvidia,tegra186-dsi";</div><div class='del'>-			reg = &lt;0x15400000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x15400000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;bpmp TEGRA186_CLK_DSIB&gt;,</div><div class='ctx'> 				 &lt;&amp;bpmp TEGRA186_CLK_DSIB_LP&gt;,</div><div class='hunk'>@@ -1074,9 +1724,40 @@</div><div class='ctx'> 			power-domains = &lt;&amp;bpmp TEGRA186_POWER_DOMAIN_DISP&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		nvdec@15480000 {</div><div class='add'>+			compatible = "nvidia,tegra186-nvdec";</div><div class='add'>+			reg = &lt;0x0 0x15480000 0x0 0x40000&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA186_CLK_NVDEC&gt;;</div><div class='add'>+			clock-names = "nvdec";</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA186_RESET_NVDEC&gt;;</div><div class='add'>+			reset-names = "nvdec";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;bpmp TEGRA186_POWER_DOMAIN_NVDEC&gt;;</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA186_MEMORY_CLIENT_NVDECSRD &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA186_MEMORY_CLIENT_NVDECSRD1 &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA186_MEMORY_CLIENT_NVDECSWR &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem", "read-1", "write";</div><div class='add'>+			iommus = &lt;&amp;smmu TEGRA186_SID_NVDEC&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nvenc@154c0000 {</div><div class='add'>+			compatible = "nvidia,tegra186-nvenc";</div><div class='add'>+			reg = &lt;0x0 0x154c0000 0x0 0x40000&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA186_CLK_NVENC&gt;;</div><div class='add'>+			clock-names = "nvenc";</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA186_RESET_NVENC&gt;;</div><div class='add'>+			reset-names = "nvenc";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;bpmp TEGRA186_POWER_DOMAIN_MPE&gt;;</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA186_MEMORY_CLIENT_NVENCSRD &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA186_MEMORY_CLIENT_NVENCSWR &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem", "write";</div><div class='add'>+			iommus = &lt;&amp;smmu TEGRA186_SID_NVENC&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		sor0: sor@15540000 {</div><div class='ctx'> 			compatible = "nvidia,tegra186-sor";</div><div class='del'>-			reg = &lt;0x15540000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x15540000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;bpmp TEGRA186_CLK_SOR0&gt;,</div><div class='ctx'> 				 &lt;&amp;bpmp TEGRA186_CLK_SOR0_OUT&gt;,</div><div class='hunk'>@@ -1100,7 +1781,7 @@</div><div class='ctx'> </div><div class='ctx'> 		sor1: sor@15580000 {</div><div class='ctx'> 			compatible = "nvidia,tegra186-sor";</div><div class='del'>-			reg = &lt;0x15580000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x15580000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;bpmp TEGRA186_CLK_SOR1&gt;,</div><div class='ctx'> 				 &lt;&amp;bpmp TEGRA186_CLK_SOR1_OUT&gt;,</div><div class='hunk'>@@ -1124,7 +1805,7 @@</div><div class='ctx'> </div><div class='ctx'> 		dpaux: dpaux@155c0000 {</div><div class='ctx'> 			compatible = "nvidia,tegra186-dpaux";</div><div class='del'>-			reg = &lt;0x155c0000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x155c0000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;bpmp TEGRA186_CLK_DPAUX&gt;,</div><div class='ctx'> 				 &lt;&amp;bpmp TEGRA186_CLK_PLLDP&gt;;</div><div class='hunk'>@@ -1158,7 +1839,7 @@</div><div class='ctx'> </div><div class='ctx'> 		padctl@15880000 {</div><div class='ctx'> 			compatible = "nvidia,tegra186-dsi-padctl";</div><div class='del'>-			reg = &lt;0x15880000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x15880000 0x0 0x10000&gt;;</div><div class='ctx'> 			resets = &lt;&amp;bpmp TEGRA186_RESET_DSI&gt;;</div><div class='ctx'> 			reset-names = "dsi";</div><div class='ctx'> 			status = "disabled";</div><div class='hunk'>@@ -1166,7 +1847,7 @@</div><div class='ctx'> </div><div class='ctx'> 		dsic: dsi@15900000 {</div><div class='ctx'> 			compatible = "nvidia,tegra186-dsi";</div><div class='del'>-			reg = &lt;0x15900000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x15900000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;bpmp TEGRA186_CLK_DSIC&gt;,</div><div class='ctx'> 				 &lt;&amp;bpmp TEGRA186_CLK_DSIC_LP&gt;,</div><div class='hunk'>@@ -1181,7 +1862,7 @@</div><div class='ctx'> </div><div class='ctx'> 		dsid: dsi@15940000 {</div><div class='ctx'> 			compatible = "nvidia,tegra186-dsi";</div><div class='del'>-			reg = &lt;0x15940000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x15940000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;bpmp TEGRA186_CLK_DSID&gt;,</div><div class='ctx'> 				 &lt;&amp;bpmp TEGRA186_CLK_DSID_LP&gt;,</div><div class='hunk'>@@ -1199,8 +1880,8 @@</div><div class='ctx'> 		compatible = "nvidia,gp10b";</div><div class='ctx'> 		reg = &lt;0x0 0x17000000 0x0 0x1000000&gt;,</div><div class='ctx'> 		      &lt;0x0 0x18000000 0x0 0x1000000&gt;;</div><div class='del'>-		interrupts = &lt;GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH</div><div class='del'>-			      GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		interrupt-names = "stall", "nonstall";</div><div class='ctx'> </div><div class='ctx'> 		clocks = &lt;&amp;bpmp TEGRA186_CLK_GPCCLK&gt;,</div><div class='hunk'>@@ -1211,25 +1892,29 @@</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> </div><div class='ctx'> 		power-domains = &lt;&amp;bpmp TEGRA186_POWER_DOMAIN_GPU&gt;;</div><div class='add'>+		interconnects = &lt;&amp;mc TEGRA186_MEMORY_CLIENT_GPUSRD &amp;emc&gt;,</div><div class='add'>+				&lt;&amp;mc TEGRA186_MEMORY_CLIENT_GPUSWR &amp;emc&gt;,</div><div class='add'>+				&lt;&amp;mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &amp;emc&gt;,</div><div class='add'>+				&lt;&amp;mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &amp;emc&gt;;</div><div class='add'>+		interconnect-names = "dma-mem", "write-0", "read-1", "write-1";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sysram@30000000 {</div><div class='add'>+	sram@30000000 {</div><div class='ctx'> 		compatible = "nvidia,tegra186-sysram", "mmio-sram";</div><div class='ctx'> 		reg = &lt;0x0 0x30000000 0x0 0x50000&gt;;</div><div class='del'>-		#address-cells = &lt;2&gt;;</div><div class='del'>-		#size-cells = &lt;2&gt;;</div><div class='del'>-		ranges = &lt;0 0x0 0x0 0x30000000 0x0 0x50000&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges = &lt;0x0 0x0 0x30000000 0x50000&gt;;</div><div class='add'>+		no-memory-wc;</div><div class='ctx'> </div><div class='del'>-		cpu_bpmp_tx: shmem@4e000 {</div><div class='del'>-			compatible = "nvidia,tegra186-bpmp-shmem";</div><div class='del'>-			reg = &lt;0x0 0x4e000 0x0 0x1000&gt;;</div><div class='add'>+		cpu_bpmp_tx: sram@4e000 {</div><div class='add'>+			reg = &lt;0x4e000 0x1000&gt;;</div><div class='ctx'> 			label = "cpu-bpmp-tx";</div><div class='ctx'> 			pool;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		cpu_bpmp_rx: shmem@4f000 {</div><div class='del'>-			compatible = "nvidia,tegra186-bpmp-shmem";</div><div class='del'>-			reg = &lt;0x0 0x4f000 0x0 0x1000&gt;;</div><div class='add'>+		cpu_bpmp_rx: sram@4f000 {</div><div class='add'>+			reg = &lt;0x4f000 0x1000&gt;;</div><div class='ctx'> 			label = "cpu-bpmp-rx";</div><div class='ctx'> 			pool;</div><div class='ctx'> 		};</div><div class='hunk'>@@ -1237,10 +1922,15 @@</div><div class='ctx'> </div><div class='ctx'> 	bpmp: bpmp {</div><div class='ctx'> 		compatible = "nvidia,tegra186-bpmp";</div><div class='add'>+		interconnects = &lt;&amp;mc TEGRA186_MEMORY_CLIENT_BPMPR &amp;emc&gt;,</div><div class='add'>+				&lt;&amp;mc TEGRA186_MEMORY_CLIENT_BPMPW &amp;emc&gt;,</div><div class='add'>+				&lt;&amp;mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &amp;emc&gt;,</div><div class='add'>+				&lt;&amp;mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &amp;emc&gt;;</div><div class='add'>+		interconnect-names = "read", "write", "dma-mem", "dma-write";</div><div class='ctx'> 		iommus = &lt;&amp;smmu TEGRA186_SID_BPMP&gt;;</div><div class='ctx'> 		mboxes = &lt;&amp;hsp_top0 TEGRA_HSP_MBOX_TYPE_DB</div><div class='ctx'> 				    TEGRA_HSP_DB_MASTER_BPMP&gt;;</div><div class='del'>-		shmem = &lt;&amp;cpu_bpmp_tx &amp;cpu_bpmp_rx&gt;;</div><div class='add'>+		shmem = &lt;&amp;cpu_bpmp_tx&gt;, &lt;&amp;cpu_bpmp_rx&gt;;</div><div class='ctx'> 		#clock-cells = &lt;1&gt;;</div><div class='ctx'> 		#reset-cells = &lt;1&gt;;</div><div class='ctx'> 		#power-domain-cells = &lt;1&gt;;</div><div class='hunk'>@@ -1263,7 +1953,7 @@</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;0&gt;;</div><div class='ctx'> </div><div class='del'>-		cpu@0 {</div><div class='add'>+		denver_0: cpu@0 {</div><div class='ctx'> 			compatible = "nvidia,tegra186-denver";</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			i-cache-size = &lt;0x20000&gt;;</div><div class='hunk'>@@ -1276,7 +1966,7 @@</div><div class='ctx'> 			reg = &lt;0x000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		cpu@1 {</div><div class='add'>+		denver_1: cpu@1 {</div><div class='ctx'> 			compatible = "nvidia,tegra186-denver";</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			i-cache-size = &lt;0x20000&gt;;</div><div class='hunk'>@@ -1289,7 +1979,7 @@</div><div class='ctx'> 			reg = &lt;0x001&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		cpu@2 {</div><div class='add'>+		ca57_0: cpu@2 {</div><div class='ctx'> 			compatible = "arm,cortex-a57";</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			i-cache-size = &lt;0xC000&gt;;</div><div class='hunk'>@@ -1302,7 +1992,7 @@</div><div class='ctx'> 			reg = &lt;0x100&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		cpu@3 {</div><div class='add'>+		ca57_1: cpu@3 {</div><div class='ctx'> 			compatible = "arm,cortex-a57";</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			i-cache-size = &lt;0xC000&gt;;</div><div class='hunk'>@@ -1315,7 +2005,7 @@</div><div class='ctx'> 			reg = &lt;0x101&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		cpu@4 {</div><div class='add'>+		ca57_2: cpu@4 {</div><div class='ctx'> 			compatible = "arm,cortex-a57";</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			i-cache-size = &lt;0xC000&gt;;</div><div class='hunk'>@@ -1328,7 +2018,7 @@</div><div class='ctx'> 			reg = &lt;0x102&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		cpu@5 {</div><div class='add'>+		ca57_3: cpu@5 {</div><div class='ctx'> 			compatible = "arm,cortex-a57";</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			i-cache-size = &lt;0xC000&gt;;</div><div class='hunk'>@@ -1360,13 +2050,51 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	pmu-a57 {</div><div class='add'>+		compatible = "arm,cortex-a57-pmu";</div><div class='add'>+		interrupts = &lt;GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-affinity = &lt;&amp;ca57_0 &amp;ca57_1 &amp;ca57_2 &amp;ca57_3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu-denver {</div><div class='add'>+		compatible = "nvidia,denver-pmu";</div><div class='add'>+		interrupts = &lt;GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-affinity = &lt;&amp;denver_0 &amp;denver_1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		status = "disabled";</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;bpmp TEGRA186_CLK_PLLA&gt;,</div><div class='add'>+			 &lt;&amp;bpmp TEGRA186_CLK_PLL_A_OUT0&gt;;</div><div class='add'>+		clock-names = "pll_a", "plla_out0";</div><div class='add'>+		assigned-clocks = &lt;&amp;bpmp TEGRA186_CLK_PLLA&gt;,</div><div class='add'>+				  &lt;&amp;bpmp TEGRA186_CLK_PLL_A_OUT0&gt;,</div><div class='add'>+				  &lt;&amp;bpmp TEGRA186_CLK_AUD_MCLK&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;,</div><div class='add'>+					 &lt;&amp;bpmp TEGRA186_CLK_PLLA&gt;,</div><div class='add'>+					 &lt;&amp;bpmp TEGRA186_CLK_PLL_A_OUT0&gt;;</div><div class='add'>+		/*</div><div class='add'>+		 * PLLA supports dynamic ramp. Below initial rate is chosen</div><div class='add'>+		 * for this to work and oscillate between base rates required</div><div class='add'>+		 * for 8x and 11.025x sample rate streams.</div><div class='add'>+		 */</div><div class='add'>+		assigned-clock-rates = &lt;258000000&gt;;</div><div class='add'>+</div><div class='add'>+		iommus = &lt;&amp;smmu TEGRA186_SID_APE&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	thermal-zones {</div><div class='del'>-		a57 {</div><div class='add'>+		/* Cortex-A57 cluster */</div><div class='add'>+		cpu-thermal {</div><div class='ctx'> 			polling-delay = &lt;0&gt;;</div><div class='ctx'> 			polling-delay-passive = &lt;1000&gt;;</div><div class='ctx'> </div><div class='del'>-			thermal-sensors =</div><div class='del'>-				&lt;&amp;bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU&gt;;</div><div class='ctx'> </div><div class='ctx'> 			trips {</div><div class='ctx'> 				critical {</div><div class='hunk'>@@ -1380,12 +2108,12 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		denver {</div><div class='add'>+		/* Denver cluster */</div><div class='add'>+		aux-thermal {</div><div class='ctx'> 			polling-delay = &lt;0&gt;;</div><div class='ctx'> 			polling-delay-passive = &lt;1000&gt;;</div><div class='ctx'> </div><div class='del'>-			thermal-sensors =</div><div class='del'>-				&lt;&amp;bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX&gt;;</div><div class='ctx'> </div><div class='ctx'> 			trips {</div><div class='ctx'> 				critical {</div><div class='hunk'>@@ -1399,12 +2127,11 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		gpu {</div><div class='add'>+		gpu-thermal {</div><div class='ctx'> 			polling-delay = &lt;0&gt;;</div><div class='ctx'> 			polling-delay-passive = &lt;1000&gt;;</div><div class='ctx'> </div><div class='del'>-			thermal-sensors =</div><div class='del'>-				&lt;&amp;bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU&gt;;</div><div class='ctx'> </div><div class='ctx'> 			trips {</div><div class='ctx'> 				critical {</div><div class='hunk'>@@ -1418,12 +2145,11 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		pll {</div><div class='add'>+		pll-thermal {</div><div class='ctx'> 			polling-delay = &lt;0&gt;;</div><div class='ctx'> 			polling-delay-passive = &lt;1000&gt;;</div><div class='ctx'> </div><div class='del'>-			thermal-sensors =</div><div class='del'>-				&lt;&amp;bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX&gt;;</div><div class='ctx'> </div><div class='ctx'> 			trips {</div><div class='ctx'> 				critical {</div><div class='hunk'>@@ -1437,12 +2163,11 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		always_on {</div><div class='add'>+		ao-thermal {</div><div class='ctx'> 			polling-delay = &lt;0&gt;;</div><div class='ctx'> 			polling-delay-passive = &lt;1000&gt;;</div><div class='ctx'> </div><div class='del'>-			thermal-sensors =</div><div class='del'>-				&lt;&amp;bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO&gt;;</div><div class='ctx'> </div><div class='ctx'> 			trips {</div><div class='ctx'> 				critical {</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi<br/>index 623f7d7d216b..43942db6eac9 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi</a></div><div class='hunk'>@@ -8,42 +8,43 @@</div><div class='ctx'> 	compatible = "nvidia,p2888", "nvidia,tegra194";</div><div class='ctx'> </div><div class='ctx'> 	aliases {</div><div class='del'>-		ethernet0 = "/cbb@0/ethernet@2490000";</div><div class='del'>-		sdhci0 = "/cbb@0/sdhci@3460000";</div><div class='del'>-		sdhci1 = "/cbb@0/sdhci@3400000";</div><div class='del'>-		serial0 = &amp;tcu;</div><div class='add'>+		ethernet0 = "/bus@0/ethernet@2490000";</div><div class='ctx'> 		i2c0 = "/bpmp/i2c";</div><div class='del'>-		i2c1 = "/cbb@0/i2c@3160000";</div><div class='del'>-		i2c2 = "/cbb@0/i2c@c240000";</div><div class='del'>-		i2c3 = "/cbb@0/i2c@3180000";</div><div class='del'>-		i2c4 = "/cbb@0/i2c@3190000";</div><div class='del'>-		i2c5 = "/cbb@0/i2c@31c0000";</div><div class='del'>-		i2c6 = "/cbb@0/i2c@c250000";</div><div class='del'>-		i2c7 = "/cbb@0/i2c@31e0000";</div><div class='add'>+		i2c1 = "/bus@0/i2c@3160000";</div><div class='add'>+		i2c2 = "/bus@0/i2c@c240000";</div><div class='add'>+		i2c3 = "/bus@0/i2c@3180000";</div><div class='add'>+		i2c4 = "/bus@0/i2c@3190000";</div><div class='add'>+		i2c5 = "/bus@0/i2c@31c0000";</div><div class='add'>+		i2c6 = "/bus@0/i2c@c250000";</div><div class='add'>+		i2c7 = "/bus@0/i2c@31e0000";</div><div class='add'>+		mmc0 = "/bus@0/mmc@3460000";</div><div class='add'>+		mmc1 = "/bus@0/mmc@3400000";</div><div class='add'>+		serial0 = &amp;tcu;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	chosen {</div><div class='del'>-		bootargs = "console=ttyS0,115200n8";</div><div class='add'>+		bootargs = "console=ttyTCU0,115200n8";</div><div class='ctx'> 		stdout-path = "serial0:115200n8";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	cbb@0 {</div><div class='add'>+	bus@0 {</div><div class='ctx'> 		ethernet@2490000 {</div><div class='ctx'> 			status = "okay";</div><div class='ctx'> </div><div class='ctx'> 			phy-reset-gpios = &lt;&amp;gpio TEGRA194_MAIN_GPIO(G, 5) GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 			phy-handle = &lt;&amp;phy&gt;;</div><div class='del'>-			phy-mode = "rgmii";</div><div class='add'>+			phy-mode = "rgmii-id";</div><div class='ctx'> </div><div class='ctx'> 			mdio {</div><div class='ctx'> 				#address-cells = &lt;1&gt;;</div><div class='ctx'> 				#size-cells = &lt;0&gt;;</div><div class='ctx'> </div><div class='del'>-				phy: phy@0 {</div><div class='add'>+				phy: ethernet-phy@0 {</div><div class='ctx'> 					compatible = "ethernet-phy-ieee802.3-c22";</div><div class='ctx'> 					reg = &lt;0x0&gt;;</div><div class='ctx'> 					interrupt-parent = &lt;&amp;gpio&gt;;</div><div class='ctx'> 					interrupts = &lt;TEGRA194_MAIN_GPIO(G, 4) IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+					#phy-cells = &lt;0&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='hunk'>@@ -52,17 +53,85 @@</div><div class='ctx'> 			status = "okay";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		i2c@c240000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			power-sensor@40 {</div><div class='add'>+				compatible = "ti,ina3221";</div><div class='add'>+				reg = &lt;0x40&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				input@0 {</div><div class='add'>+					reg = &lt;0x0&gt;;</div><div class='add'>+					label = "GPU";</div><div class='add'>+					shunt-resistor-micro-ohms = &lt;5000&gt;;</div><div class='add'>+				};</div><div class='add'>+				input@1 {</div><div class='add'>+					reg = &lt;0x1&gt;;</div><div class='add'>+					label = "CPU";</div><div class='add'>+					shunt-resistor-micro-ohms = &lt;5000&gt;;</div><div class='add'>+				};</div><div class='add'>+				input@2 {</div><div class='add'>+					reg = &lt;0x2&gt;;</div><div class='add'>+					label = "SOC";</div><div class='add'>+					shunt-resistor-micro-ohms = &lt;5000&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			power-sensor@41 {</div><div class='add'>+				compatible = "ti,ina3221";</div><div class='add'>+				reg = &lt;0x41&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				input@0 {</div><div class='add'>+					reg = &lt;0x0&gt;;</div><div class='add'>+					label = "CV";</div><div class='add'>+					shunt-resistor-micro-ohms = &lt;5000&gt;;</div><div class='add'>+				};</div><div class='add'>+				input@1 {</div><div class='add'>+					reg = &lt;0x1&gt;;</div><div class='add'>+					label = "VDDRQ";</div><div class='add'>+					shunt-resistor-micro-ohms = &lt;5000&gt;;</div><div class='add'>+				};</div><div class='add'>+				input@2 {</div><div class='add'>+					reg = &lt;0x2&gt;;</div><div class='add'>+					label = "SYS5V";</div><div class='add'>+					shunt-resistor-micro-ohms = &lt;5000&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		serial@3110000 {</div><div class='add'>+			/delete-property/ dmas;</div><div class='add'>+			/delete-property/ dma-names;</div><div class='ctx'> 			status = "okay";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		i2c@3160000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			eeprom@50 {</div><div class='add'>+				compatible = "atmel,24c02";</div><div class='add'>+				reg = &lt;0x50&gt;;</div><div class='add'>+</div><div class='add'>+				label = "module";</div><div class='add'>+				vcc-supply = &lt;&amp;vdd_1v8ls&gt;;</div><div class='add'>+				address-width = &lt;8&gt;;</div><div class='add'>+				pagesize = &lt;8&gt;;</div><div class='add'>+				size = &lt;256&gt;;</div><div class='add'>+				read-only;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		/* SDMMC1 (SD/MMC) */</div><div class='del'>-		sdhci@3400000 {</div><div class='del'>-			cd-gpios = &lt;&amp;gpio TEGRA194_MAIN_GPIO(A, 0) GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		mmc@3400000 {</div><div class='add'>+			cd-gpios = &lt;&amp;gpio TEGRA194_MAIN_GPIO(G, 7) GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		/* SDMMC4 (eMMC) */</div><div class='del'>-		sdhci@3460000 {</div><div class='add'>+		mmc@3460000 {</div><div class='ctx'> 			status = "okay";</div><div class='ctx'> 			bus-width = &lt;8&gt;;</div><div class='ctx'> 			non-removable;</div><div class='hunk'>@@ -76,6 +145,10 @@</div><div class='ctx'> 			vclamp-usb-supply = &lt;&amp;vdd_1v8ao&gt;;</div><div class='ctx'> </div><div class='ctx'> 			ports {</div><div class='add'>+				usb2-0 {</div><div class='add'>+					vbus-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='ctx'> 				usb2-1 {</div><div class='ctx'> 					vbus-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='ctx'> 				};</div><div class='hunk'>@@ -88,6 +161,10 @@</div><div class='ctx'> 					vbus-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='add'>+				usb3-2 {</div><div class='add'>+					vbus-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='ctx'> 				usb3-3 {</div><div class='ctx'> 					vbus-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='ctx'> 				};</div><div class='hunk'>@@ -111,7 +188,8 @@</div><div class='ctx'> 				compatible = "maxim,max20024";</div><div class='ctx'> 				reg = &lt;0x3c&gt;;</div><div class='ctx'> </div><div class='del'>-				interrupts = &lt;GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				interrupt-parent = &lt;&amp;pmc&gt;;</div><div class='add'>+				interrupts = &lt;24 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> 				#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 				interrupt-controller;</div><div class='ctx'> </div><div class='hunk'>@@ -121,6 +199,24 @@</div><div class='ctx'> 				pinctrl-names = "default";</div><div class='ctx'> 				pinctrl-0 = &lt;&amp;max20024_default&gt;;</div><div class='ctx'> </div><div class='add'>+				fps {</div><div class='add'>+					fps0 {</div><div class='add'>+						maxim,fps-event-source = &lt;MAX77620_FPS_EVENT_SRC_EN0&gt;;</div><div class='add'>+						maxim,shutdown-fps-time-period-us = &lt;640&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					fps1 {</div><div class='add'>+						maxim,fps-event-source = &lt;MAX77620_FPS_EVENT_SRC_EN1&gt;;</div><div class='add'>+						maxim,shutdown-fps-time-period-us = &lt;640&gt;;</div><div class='add'>+						maxim,device-state-on-disabled-event = &lt;MAX77620_FPS_INACTIVE_STATE_SLEEP&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					fps2 {</div><div class='add'>+						maxim,fps-event-source = &lt;MAX77620_FPS_EVENT_SRC_EN0&gt;;</div><div class='add'>+						maxim,shutdown-fps-time-period-us = &lt;640&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='ctx'> 				max20024_default: pinmux {</div><div class='ctx'> 					gpio0 {</div><div class='ctx'> 						pins = "gpio0";</div><div class='hunk'>@@ -164,24 +260,6 @@</div><div class='ctx'> 					};</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				fps {</div><div class='del'>-					fps0 {</div><div class='del'>-						maxim,fps-event-source = &lt;MAX77620_FPS_EVENT_SRC_EN0&gt;;</div><div class='del'>-						maxim,shutdown-fps-time-period-us = &lt;640&gt;;</div><div class='del'>-					};</div><div class='del'>-</div><div class='del'>-					fps1 {</div><div class='del'>-						maxim,fps-event-source = &lt;MAX77620_FPS_EVENT_SRC_EN1&gt;;</div><div class='del'>-						maxim,shutdown-fps-time-period-us = &lt;640&gt;;</div><div class='del'>-						maxim,device-state-on-disabled-event = &lt;MAX77620_FPS_INACTIVE_STATE_SLEEP&gt;;</div><div class='del'>-					};</div><div class='del'>-</div><div class='del'>-					fps2 {</div><div class='del'>-						maxim,fps-event-source = &lt;MAX77620_FPS_EVENT_SRC_EN0&gt;;</div><div class='del'>-						maxim,shutdown-fps-time-period-us = &lt;640&gt;;</div><div class='del'>-					};</div><div class='del'>-				};</div><div class='del'>-</div><div class='ctx'> 				regulators {</div><div class='ctx'> 					in-sd0-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='ctx'> 					in-sd1-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='hunk'>@@ -283,7 +361,7 @@</div><div class='ctx'> </div><div class='ctx'> 				interrupt-parent = &lt;&amp;gpio&gt;;</div><div class='ctx'> 				interrupts = &lt;TEGRA194_MAIN_GPIO(H, 2)</div><div class='del'>-					      IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+					      IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='ctx'> 				vcc-supply = &lt;&amp;vdd_1v8ls&gt;;</div><div class='ctx'> </div><div class='ctx'> 				#thermal-sensor-cells = &lt;1&gt;;</div><div class='hunk'>@@ -291,65 +369,49 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	regulators {</div><div class='del'>-		compatible = "simple-bus";</div><div class='del'>-		#address-cells = &lt;1&gt;;</div><div class='del'>-		#size-cells = &lt;0&gt;;</div><div class='del'>-</div><div class='del'>-		vdd_5v0_sys: regulator@0 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;0&gt;;</div><div class='del'>-</div><div class='del'>-			regulator-name = "VIN_SYS_5V0";</div><div class='del'>-			regulator-min-microvolt = &lt;5000000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;5000000&gt;;</div><div class='del'>-			regulator-always-on;</div><div class='del'>-			regulator-boot-on;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		vdd_hdmi: regulator@1 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;1&gt;;</div><div class='del'>-</div><div class='del'>-			regulator-name = "VDD_5V0_HDMI_CON";</div><div class='del'>-			regulator-min-microvolt = &lt;5000000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;5000000&gt;;</div><div class='del'>-			gpio = &lt;&amp;gpio TEGRA194_MAIN_GPIO(A, 3) GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			enable-active-high;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		vdd_3v3_pcie: regulator@2 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;2&gt;;</div><div class='del'>-</div><div class='del'>-			regulator-name = "PEX_3V3";</div><div class='del'>-			regulator-min-microvolt = &lt;3300000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;3300000&gt;;</div><div class='del'>-			gpio = &lt;&amp;gpio TEGRA194_MAIN_GPIO(Z, 2) GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			regulator-boot-on;</div><div class='del'>-			enable-active-high;</div><div class='del'>-		};</div><div class='add'>+	vdd_5v0_sys: regulator-vdd-5v0-sys {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VIN_SYS_5V0";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		vdd_12v_pcie: regulator@3 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;3&gt;;</div><div class='add'>+	vdd_hdmi: regulator-vdd-hdmi {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_5V0_HDMI_CON";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio TEGRA194_MAIN_GPIO(A, 3) GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-			regulator-name = "VDD_12V";</div><div class='del'>-			regulator-min-microvolt = &lt;1200000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;1200000&gt;;</div><div class='del'>-			gpio = &lt;&amp;gpio TEGRA194_MAIN_GPIO(A, 1) GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			regulator-boot-on;</div><div class='del'>-		};</div><div class='add'>+	vdd_3v3_pcie: regulator-vdd-3v3-pcie {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "PEX_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio TEGRA194_MAIN_GPIO(Z, 2) GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		vdd_5v_sata: regulator@4 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;4&gt;;</div><div class='add'>+	vdd_12v_pcie: regulator-vdd-12v-pcie {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_12V";</div><div class='add'>+		regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio TEGRA194_MAIN_GPIO(A, 1) GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-			regulator-name = "VDD_5V_SATA";</div><div class='del'>-			regulator-min-microvolt = &lt;5000000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;5000000&gt;;</div><div class='del'>-			gpio = &lt;&amp;gpio TEGRA194_MAIN_GPIO(Z, 1) GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			enable-active-high;</div><div class='del'>-		};</div><div class='add'>+	vdd_5v_sata: regulator-vdd-5v0-sata {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_5V_SATA";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio TEGRA194_MAIN_GPIO(Z, 1) GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts<br/>index e15d1eac05f5..ea6f397a2792 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts</a></div><div class='hunk'>@@ -10,10 +10,1982 @@</div><div class='ctx'> 	model = "NVIDIA Jetson AGX Xavier Developer Kit";</div><div class='ctx'> 	compatible = "nvidia,p2972-0000", "nvidia,tegra194";</div><div class='ctx'> </div><div class='del'>-	cbb@0 {</div><div class='add'>+	bus@0 {</div><div class='ctx'> 		aconnect@2900000 {</div><div class='ctx'> 			status = "okay";</div><div class='ctx'> </div><div class='add'>+			ahub@2900800 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				i2s@2901000 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							i2s1_cif_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_i2s1_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						i2s1_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							i2s1_dap_ep: endpoint {</div><div class='add'>+								dai-format = "i2s";</div><div class='add'>+								remote-endpoint = &lt;&amp;rt5658_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				i2s@2901100 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							i2s2_cif_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_i2s2_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						i2s2_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							i2s2_dap_ep: endpoint {</div><div class='add'>+								dai-format = "i2s";</div><div class='add'>+								/* Place holder for external Codec */</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				i2s@2901300 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							i2s4_cif_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_i2s4_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						i2s4_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							i2s4_dap_ep: endpoint {</div><div class='add'>+								dai-format = "i2s";</div><div class='add'>+								/* Place holder for external Codec */</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				i2s@2901500 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							i2s6_cif_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_i2s6_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						i2s6_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							i2s6_dap_ep: endpoint {</div><div class='add'>+								dai-format = "i2s";</div><div class='add'>+								/* Place holder for external Codec */</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				sfc@2902000 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							sfc1_cif_in_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_sfc1_in_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						sfc1_out_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							sfc1_cif_out_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_sfc1_out_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				sfc@2902200 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							sfc2_cif_in_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_sfc2_in_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						sfc2_out_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							sfc2_cif_out_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_sfc2_out_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				sfc@2902400 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							sfc3_cif_in_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_sfc3_in_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						sfc3_out_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							sfc3_cif_out_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_sfc3_out_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				sfc@2902600 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							sfc4_cif_in_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_sfc4_in_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						sfc4_out_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							sfc4_cif_out_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_sfc4_out_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				amx@2903000 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							amx1_in1_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx1_in1_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							amx1_in2_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx1_in2_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@2 {</div><div class='add'>+							reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+							amx1_in3_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx1_in3_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@3 {</div><div class='add'>+							reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+							amx1_in4_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx1_in4_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						amx1_out_port: port@4 {</div><div class='add'>+							reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+							amx1_out_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx1_out_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				amx@2903100 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							amx2_in1_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx2_in1_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							amx2_in2_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx2_in2_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						amx2_in3_port: port@2 {</div><div class='add'>+							reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+							amx2_in3_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx2_in3_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						amx2_in4_port: port@3 {</div><div class='add'>+							reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+							amx2_in4_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx2_in4_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						amx2_out_port: port@4 {</div><div class='add'>+							reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+							amx2_out_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx2_out_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				amx@2903200 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							amx3_in1_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx3_in1_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							amx3_in2_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx3_in2_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@2 {</div><div class='add'>+							reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+							amx3_in3_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx3_in3_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@3 {</div><div class='add'>+							reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+							amx3_in4_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx3_in4_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						amx3_out_port: port@4 {</div><div class='add'>+							reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+							amx3_out_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx3_out_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				amx@2903300 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							amx4_in1_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx4_in1_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							amx4_in2_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx4_in2_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@2 {</div><div class='add'>+							reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+							amx4_in3_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx4_in3_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@3 {</div><div class='add'>+							reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+							amx4_in4_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx4_in4_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						amx4_out_port: port@4 {</div><div class='add'>+							reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+							amx4_out_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx4_out_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				adx@2903800 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							adx1_in_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx1_in_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx1_out1_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							adx1_out1_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx1_out1_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx1_out2_port: port@2 {</div><div class='add'>+							reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+							adx1_out2_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx1_out2_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx1_out3_port: port@3 {</div><div class='add'>+							reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+							adx1_out3_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx1_out3_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx1_out4_port: port@4 {</div><div class='add'>+							reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+							adx1_out4_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx1_out4_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				adx@2903900 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							adx2_in_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx2_in_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx2_out1_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							adx2_out1_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx2_out1_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx2_out2_port: port@2 {</div><div class='add'>+							reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+							adx2_out2_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx2_out2_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx2_out3_port: port@3 {</div><div class='add'>+							reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+							adx2_out3_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx2_out3_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx2_out4_port: port@4 {</div><div class='add'>+							reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+							adx2_out4_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx2_out4_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				adx@2903a00 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							adx3_in_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx3_in_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx3_out1_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							adx3_out1_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx3_out1_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx3_out2_port: port@2 {</div><div class='add'>+							reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+							adx3_out2_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx3_out2_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx3_out3_port: port@3 {</div><div class='add'>+							reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+							adx3_out3_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx3_out3_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx3_out4_port: port@4 {</div><div class='add'>+							reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+							adx3_out4_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx3_out4_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				adx@2903b00 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							adx4_in_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx4_in_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx4_out1_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							adx4_out1_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx4_out1_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx4_out2_port: port@2 {</div><div class='add'>+							reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+							adx4_out2_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx4_out2_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx4_out3_port: port@3 {</div><div class='add'>+							reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+							adx4_out3_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx4_out3_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx4_out4_port: port@4 {</div><div class='add'>+							reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+							adx4_out4_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx4_out4_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				dmic@2904200 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							dmic3_cif_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_dmic3_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						dmic3_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							dmic3_dap_ep: endpoint {</div><div class='add'>+								/* Place holder for external Codec */</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				processing-engine@2908000 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0x0&gt;;</div><div class='add'>+</div><div class='add'>+							ope1_cif_in_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_ope1_in_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						ope1_out_port: port@1 {</div><div class='add'>+							reg = &lt;0x1&gt;;</div><div class='add'>+</div><div class='add'>+							ope1_cif_out_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_ope1_out_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				mvc@290a000 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							mvc1_cif_in_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mvc1_in_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						mvc1_out_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							mvc1_cif_out_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mvc1_out_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				mvc@290a200 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							mvc2_cif_in_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mvc2_in_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						mvc2_out_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							mvc2_cif_out_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mvc2_out_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				amixer@290bb00 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0x0&gt;;</div><div class='add'>+</div><div class='add'>+							mixer_in1_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mixer_in1_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@1 {</div><div class='add'>+							reg = &lt;0x1&gt;;</div><div class='add'>+</div><div class='add'>+							mixer_in2_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mixer_in2_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@2 {</div><div class='add'>+							reg = &lt;0x2&gt;;</div><div class='add'>+</div><div class='add'>+							mixer_in3_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mixer_in3_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@3 {</div><div class='add'>+							reg = &lt;0x3&gt;;</div><div class='add'>+</div><div class='add'>+							mixer_in4_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mixer_in4_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@4 {</div><div class='add'>+							reg = &lt;0x4&gt;;</div><div class='add'>+</div><div class='add'>+							mixer_in5_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mixer_in5_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@5 {</div><div class='add'>+							reg = &lt;0x5&gt;;</div><div class='add'>+</div><div class='add'>+							mixer_in6_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mixer_in6_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@6 {</div><div class='add'>+							reg = &lt;0x6&gt;;</div><div class='add'>+</div><div class='add'>+							mixer_in7_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mixer_in7_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@7 {</div><div class='add'>+							reg = &lt;0x7&gt;;</div><div class='add'>+</div><div class='add'>+							mixer_in8_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mixer_in8_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@8 {</div><div class='add'>+							reg = &lt;0x8&gt;;</div><div class='add'>+</div><div class='add'>+							mixer_in9_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mixer_in9_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@9 {</div><div class='add'>+							reg = &lt;0x9&gt;;</div><div class='add'>+</div><div class='add'>+							mixer_in10_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mixer_in10_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						mixer_out1_port: port@a {</div><div class='add'>+							reg = &lt;0xa&gt;;</div><div class='add'>+</div><div class='add'>+							mixer_out1_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mixer_out1_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						mixer_out2_port: port@b {</div><div class='add'>+							reg = &lt;0xb&gt;;</div><div class='add'>+</div><div class='add'>+							mixer_out2_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mixer_out2_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						mixer_out3_port: port@c {</div><div class='add'>+							reg = &lt;0xc&gt;;</div><div class='add'>+</div><div class='add'>+							mixer_out3_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mixer_out3_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						mixer_out4_port: port@d {</div><div class='add'>+							reg = &lt;0xd&gt;;</div><div class='add'>+</div><div class='add'>+							mixer_out4_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mixer_out4_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						mixer_out5_port: port@e {</div><div class='add'>+							reg = &lt;0xe&gt;;</div><div class='add'>+</div><div class='add'>+							mixer_out5_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mixer_out5_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				admaif@290f000 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						admaif0_port: port@0 {</div><div class='add'>+							reg = &lt;0x0&gt;;</div><div class='add'>+</div><div class='add'>+							admaif0_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif0_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif1_port: port@1 {</div><div class='add'>+							reg = &lt;0x1&gt;;</div><div class='add'>+</div><div class='add'>+							admaif1_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif1_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif2_port: port@2 {</div><div class='add'>+							reg = &lt;0x2&gt;;</div><div class='add'>+</div><div class='add'>+							admaif2_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif2_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif3_port: port@3 {</div><div class='add'>+							reg = &lt;0x3&gt;;</div><div class='add'>+</div><div class='add'>+							admaif3_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif3_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif4_port: port@4 {</div><div class='add'>+							reg = &lt;0x4&gt;;</div><div class='add'>+</div><div class='add'>+							admaif4_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif4_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif5_port: port@5 {</div><div class='add'>+							reg = &lt;0x5&gt;;</div><div class='add'>+</div><div class='add'>+							admaif5_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif5_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif6_port: port@6 {</div><div class='add'>+							reg = &lt;0x6&gt;;</div><div class='add'>+</div><div class='add'>+							admaif6_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif6_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif7_port: port@7 {</div><div class='add'>+							reg = &lt;0x7&gt;;</div><div class='add'>+</div><div class='add'>+							admaif7_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif7_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif8_port: port@8 {</div><div class='add'>+							reg = &lt;0x8&gt;;</div><div class='add'>+</div><div class='add'>+							admaif8_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif8_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif9_port: port@9 {</div><div class='add'>+							reg = &lt;0x9&gt;;</div><div class='add'>+</div><div class='add'>+							admaif9_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif9_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif10_port: port@a {</div><div class='add'>+							reg = &lt;0xa&gt;;</div><div class='add'>+</div><div class='add'>+							admaif10_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif10_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif11_port: port@b {</div><div class='add'>+							reg = &lt;0xb&gt;;</div><div class='add'>+</div><div class='add'>+							admaif11_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif11_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif12_port: port@c {</div><div class='add'>+							reg = &lt;0xc&gt;;</div><div class='add'>+</div><div class='add'>+							admaif12_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif12_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif13_port: port@d {</div><div class='add'>+							reg = &lt;0xd&gt;;</div><div class='add'>+</div><div class='add'>+							admaif13_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif13_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif14_port: port@e {</div><div class='add'>+							reg = &lt;0xe&gt;;</div><div class='add'>+</div><div class='add'>+							admaif14_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif14_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif15_port: port@f {</div><div class='add'>+							reg = &lt;0xf&gt;;</div><div class='add'>+</div><div class='add'>+							admaif15_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif15_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif16_port: port@10 {</div><div class='add'>+							reg = &lt;0x10&gt;;</div><div class='add'>+</div><div class='add'>+							admaif16_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif16_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif17_port: port@11 {</div><div class='add'>+							reg = &lt;0x11&gt;;</div><div class='add'>+</div><div class='add'>+							admaif17_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif17_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif18_port: port@12 {</div><div class='add'>+							reg = &lt;0x12&gt;;</div><div class='add'>+</div><div class='add'>+							admaif18_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif18_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif19_port: port@13 {</div><div class='add'>+							reg = &lt;0x13&gt;;</div><div class='add'>+</div><div class='add'>+							admaif19_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif19_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				asrc@2910000 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0x0&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_in1_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_asrc_in1_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@1 {</div><div class='add'>+							reg = &lt;0x1&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_in2_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_asrc_in2_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@2 {</div><div class='add'>+							reg = &lt;0x2&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_in3_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_asrc_in3_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@3 {</div><div class='add'>+							reg = &lt;0x3&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_in4_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_asrc_in4_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@4 {</div><div class='add'>+							reg = &lt;0x4&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_in5_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_asrc_in5_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@5 {</div><div class='add'>+							reg = &lt;0x5&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_in6_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_asrc_in6_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@6 {</div><div class='add'>+							reg = &lt;0x6&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_in7_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_asrc_in7_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						asrc_out1_port: port@7 {</div><div class='add'>+							reg = &lt;0x7&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_out1_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_asrc_out1_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						asrc_out2_port: port@8 {</div><div class='add'>+							reg = &lt;0x8&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_out2_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_asrc_out2_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						asrc_out3_port: port@9 {</div><div class='add'>+							reg = &lt;0x9&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_out3_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_asrc_out3_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						asrc_out4_port: port@a {</div><div class='add'>+							reg = &lt;0xa&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_out4_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_asrc_out4_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						asrc_out5_port: port@b {</div><div class='add'>+							reg = &lt;0xb&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_out5_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_asrc_out5_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						asrc_out6_port: port@c {</div><div class='add'>+							reg = &lt;0xc&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_out6_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_asrc_out6_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0x0&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif0_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif0_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;0x1&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@2 {</div><div class='add'>+						reg = &lt;0x2&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@3 {</div><div class='add'>+						reg = &lt;0x3&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@4 {</div><div class='add'>+						reg = &lt;0x4&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@5 {</div><div class='add'>+						reg = &lt;0x5&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif5_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif5_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@6 {</div><div class='add'>+						reg = &lt;0x6&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif6_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif6_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@7 {</div><div class='add'>+						reg = &lt;0x7&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif7_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif7_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@8 {</div><div class='add'>+						reg = &lt;0x8&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif8_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif8_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@9 {</div><div class='add'>+						reg = &lt;0x9&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif9_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif9_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@a {</div><div class='add'>+						reg = &lt;0xa&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif10_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif10_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@b {</div><div class='add'>+						reg = &lt;0xb&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif11_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif11_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@c {</div><div class='add'>+						reg = &lt;0xc&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif12_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif12_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@d {</div><div class='add'>+						reg = &lt;0xd&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif13_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif13_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@e {</div><div class='add'>+						reg = &lt;0xe&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif14_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif14_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@f {</div><div class='add'>+						reg = &lt;0xf&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif15_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif15_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@10 {</div><div class='add'>+						reg = &lt;0x10&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif16_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif16_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@11 {</div><div class='add'>+						reg = &lt;0x11&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif17_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif17_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@12 {</div><div class='add'>+						reg = &lt;0x12&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif18_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif18_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@13 {</div><div class='add'>+						reg = &lt;0x13&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif19_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif19_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_i2s1_port: port@14 {</div><div class='add'>+						reg = &lt;0x14&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_i2s1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;i2s1_cif_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_i2s2_port: port@15 {</div><div class='add'>+						reg = &lt;0x15&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_i2s2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;i2s2_cif_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_i2s4_port: port@17 {</div><div class='add'>+						reg = &lt;0x17&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_i2s4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;i2s4_cif_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_i2s6_port: port@19 {</div><div class='add'>+						reg = &lt;0x19&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_i2s6_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;i2s6_cif_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_dmic3_port: port@1c {</div><div class='add'>+						reg = &lt;0x1c&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_dmic3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;dmic3_cif_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_sfc1_in_port: port@20 {</div><div class='add'>+						reg = &lt;0x20&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_sfc1_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;sfc1_cif_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@21 {</div><div class='add'>+						reg = &lt;0x21&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_sfc1_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;sfc1_cif_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_sfc2_in_port: port@22 {</div><div class='add'>+						reg = &lt;0x22&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_sfc2_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;sfc2_cif_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@23 {</div><div class='add'>+						reg = &lt;0x23&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_sfc2_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;sfc2_cif_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_sfc3_in_port: port@24 {</div><div class='add'>+						reg = &lt;0x24&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_sfc3_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;sfc3_cif_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@25 {</div><div class='add'>+						reg = &lt;0x25&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_sfc3_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;sfc3_cif_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_sfc4_in_port: port@26 {</div><div class='add'>+						reg = &lt;0x26&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_sfc4_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;sfc4_cif_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@27 {</div><div class='add'>+						reg = &lt;0x27&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_sfc4_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;sfc4_cif_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mvc1_in_port: port@28 {</div><div class='add'>+						reg = &lt;0x28&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mvc1_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mvc1_cif_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@29 {</div><div class='add'>+						reg = &lt;0x29&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mvc1_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mvc1_cif_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mvc2_in_port: port@2a {</div><div class='add'>+						reg = &lt;0x2a&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mvc2_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mvc2_cif_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@2b {</div><div class='add'>+						reg = &lt;0x2b&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mvc2_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mvc2_cif_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx1_in1_port: port@2c {</div><div class='add'>+						reg = &lt;0x2c&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx1_in1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx1_in1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx1_in2_port: port@2d {</div><div class='add'>+						reg = &lt;0x2d&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx1_in2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx1_in2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx1_in3_port: port@2e {</div><div class='add'>+						reg = &lt;0x2e&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx1_in3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx1_in3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx1_in4_port: port@2f {</div><div class='add'>+						reg = &lt;0x2f&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx1_in4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx1_in4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@30 {</div><div class='add'>+						reg = &lt;0x30&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx1_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx1_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx2_in1_port: port@31 {</div><div class='add'>+						reg = &lt;0x31&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx2_in1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx2_in1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx2_in2_port: port@32 {</div><div class='add'>+						reg = &lt;0x32&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx2_in2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx2_in2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx2_in3_port: port@33 {</div><div class='add'>+						reg = &lt;0x33&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx2_in3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx2_in3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx2_in4_port: port@34 {</div><div class='add'>+						reg = &lt;0x34&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx2_in4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx2_in4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@35 {</div><div class='add'>+						reg = &lt;0x35&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx2_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx2_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx3_in1_port: port@36 {</div><div class='add'>+						reg = &lt;0x36&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx3_in1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx3_in1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx3_in2_port: port@37 {</div><div class='add'>+						reg = &lt;0x37&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx3_in2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx3_in2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx3_in3_port: port@38 {</div><div class='add'>+						reg = &lt;0x38&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx3_in3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx3_in3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx3_in4_port: port@39 {</div><div class='add'>+						reg = &lt;0x39&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx3_in4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx3_in4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@3a {</div><div class='add'>+						reg = &lt;0x3a&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx3_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx3_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx4_in1_port: port@3b {</div><div class='add'>+						reg = &lt;0x3b&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx4_in1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx4_in1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx4_in2_port: port@3c {</div><div class='add'>+						reg = &lt;0x3c&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx4_in2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx4_in2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx4_in3_port: port@3d {</div><div class='add'>+						reg = &lt;0x3d&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx4_in3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx4_in3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx4_in4_port: port@3e {</div><div class='add'>+						reg = &lt;0x3e&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx4_in4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx4_in4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@3f {</div><div class='add'>+						reg = &lt;0x3f&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx4_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx4_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_adx1_in_port: port@40 {</div><div class='add'>+						reg = &lt;0x40&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx1_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx1_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@41 {</div><div class='add'>+						reg = &lt;0x41&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx1_out1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx1_out1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@42 {</div><div class='add'>+						reg = &lt;0x42&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx1_out2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx1_out2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@43 {</div><div class='add'>+						reg = &lt;0x43&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx1_out3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx1_out3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@44 {</div><div class='add'>+						reg = &lt;0x44&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx1_out4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx1_out4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_adx2_in_port: port@45 {</div><div class='add'>+						reg = &lt;0x45&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx2_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx2_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@46 {</div><div class='add'>+						reg = &lt;0x46&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx2_out1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx2_out1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@47 {</div><div class='add'>+						reg = &lt;0x47&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx2_out2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx2_out2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@48 {</div><div class='add'>+						reg = &lt;0x48&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx2_out3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx2_out3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@49 {</div><div class='add'>+						reg = &lt;0x49&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx2_out4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx2_out4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_adx3_in_port: port@4a {</div><div class='add'>+						reg = &lt;0x4a&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx3_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx3_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@4b {</div><div class='add'>+						reg = &lt;0x4b&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx3_out1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx3_out1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@4c {</div><div class='add'>+						reg = &lt;0x4c&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx3_out2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx3_out2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@4d {</div><div class='add'>+						reg = &lt;0x4d&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx3_out3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx3_out3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@4e {</div><div class='add'>+						reg = &lt;0x4e&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx3_out4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx3_out4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_adx4_in_port: port@4f {</div><div class='add'>+						reg = &lt;0x4f&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx4_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx4_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@50 {</div><div class='add'>+						reg = &lt;0x50&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx4_out1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx4_out1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@51 {</div><div class='add'>+						reg = &lt;0x51&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx4_out2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx4_out2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@52 {</div><div class='add'>+						reg = &lt;0x52&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx4_out3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx4_out3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@53 {</div><div class='add'>+						reg = &lt;0x53&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx4_out4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx4_out4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in1_port: port@54 {</div><div class='add'>+						reg = &lt;0x54&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mixer_in1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mixer_in1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in2_port: port@55 {</div><div class='add'>+						reg = &lt;0x55&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mixer_in2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mixer_in2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in3_port: port@56 {</div><div class='add'>+						reg = &lt;0x56&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mixer_in3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mixer_in3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in4_port: port@57 {</div><div class='add'>+						reg = &lt;0x57&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mixer_in4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mixer_in4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in5_port: port@58 {</div><div class='add'>+						reg = &lt;0x58&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mixer_in5_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mixer_in5_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in6_port: port@59 {</div><div class='add'>+						reg = &lt;0x59&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mixer_in6_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mixer_in6_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in7_port: port@5a {</div><div class='add'>+						reg = &lt;0x5a&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mixer_in7_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mixer_in7_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in8_port: port@5b {</div><div class='add'>+						reg = &lt;0x5b&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mixer_in8_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mixer_in8_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in9_port: port@5c {</div><div class='add'>+						reg = &lt;0x5c&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mixer_in9_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mixer_in9_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in10_port: port@5d {</div><div class='add'>+						reg = &lt;0x5d&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mixer_in10_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mixer_in10_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@5e {</div><div class='add'>+						reg = &lt;0x5e&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mixer_out1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mixer_out1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@5f {</div><div class='add'>+						reg = &lt;0x5f&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mixer_out2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mixer_out2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@60 {</div><div class='add'>+						reg = &lt;0x60&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mixer_out3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mixer_out3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@61 {</div><div class='add'>+						reg = &lt;0x61&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mixer_out4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mixer_out4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@62 {</div><div class='add'>+						reg = &lt;0x62&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mixer_out5_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mixer_out5_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_asrc_in1_port: port@63 {</div><div class='add'>+						reg = &lt;0x63&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_in1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_in1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@64 {</div><div class='add'>+						reg = &lt;0x64&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_out1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_out1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_asrc_in2_port: port@65 {</div><div class='add'>+						reg = &lt;0x65&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_in2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_in2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@66 {</div><div class='add'>+						reg = &lt;0x66&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_out2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_out2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_asrc_in3_port: port@67 {</div><div class='add'>+						reg = &lt;0x67&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_in3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_in3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@68 {</div><div class='add'>+						reg = &lt;0x68&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_out3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_out3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_asrc_in4_port: port@69 {</div><div class='add'>+						reg = &lt;0x69&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_in4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_in4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@6a {</div><div class='add'>+						reg = &lt;0x6a&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_out4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_out4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_asrc_in5_port: port@6b {</div><div class='add'>+						reg = &lt;0x6b&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_in5_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_in5_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@6c {</div><div class='add'>+						reg = &lt;0x6c&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_out5_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_out5_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_asrc_in6_port: port@6d {</div><div class='add'>+						reg = &lt;0x6d&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_in6_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_in6_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@6e {</div><div class='add'>+						reg = &lt;0x6e&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_out6_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_out6_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_asrc_in7_port: port@6f {</div><div class='add'>+						reg = &lt;0x6f&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_in7_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_in7_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_ope1_in_port: port@70 {</div><div class='add'>+						reg = &lt;0x70&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_ope1_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;ope1_cif_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@71 {</div><div class='add'>+						reg = &lt;0x71&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_ope1_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;ope1_cif_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='ctx'> 			dma-controller@2930000 {</div><div class='ctx'> 				status = "okay";</div><div class='ctx'> 			};</div><div class='hunk'>@@ -23,17 +1995,31 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		i2c@3160000 {</div><div class='add'>+			eeprom@56 {</div><div class='add'>+				compatible = "atmel,24c02";</div><div class='add'>+				reg = &lt;0x56&gt;;</div><div class='add'>+</div><div class='add'>+				label = "system";</div><div class='add'>+				vcc-supply = &lt;&amp;vdd_1v8ls&gt;;</div><div class='add'>+				address-width = &lt;8&gt;;</div><div class='add'>+				pagesize = &lt;8&gt;;</div><div class='add'>+				size = &lt;256&gt;;</div><div class='add'>+				read-only;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		ddc: i2c@31c0000 {</div><div class='ctx'> 			status = "okay";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		/* SDMMC1 (SD/MMC) */</div><div class='del'>-		sdhci@3400000 {</div><div class='add'>+		mmc@3400000 {</div><div class='ctx'> 			status = "okay";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		hda@3510000 {</div><div class='del'>-			nvidia,model = "jetson-xavier-hda";</div><div class='add'>+			nvidia,model = "NVIDIA Jetson AGX Xavier HDA";</div><div class='ctx'> 			status = "okay";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -43,6 +2029,10 @@</div><div class='ctx'> 			pads {</div><div class='ctx'> 				usb2 {</div><div class='ctx'> 					lanes {</div><div class='add'>+						usb2-0 {</div><div class='add'>+							status = "okay";</div><div class='add'>+						};</div><div class='add'>+</div><div class='ctx'> 						usb2-1 {</div><div class='ctx'> 							status = "okay";</div><div class='ctx'> 						};</div><div class='hunk'>@@ -59,6 +2049,10 @@</div><div class='ctx'> 							status = "okay";</div><div class='ctx'> 						};</div><div class='ctx'> </div><div class='add'>+						usb3-2 {</div><div class='add'>+							status = "okay";</div><div class='add'>+						};</div><div class='add'>+</div><div class='ctx'> 						usb3-3 {</div><div class='ctx'> 							status = "okay";</div><div class='ctx'> 						};</div><div class='hunk'>@@ -67,6 +2061,18 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			ports {</div><div class='add'>+				usb2-0 {</div><div class='add'>+					mode = "otg";</div><div class='add'>+					usb-role-switch;</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					port {</div><div class='add'>+						hs_typec_p0: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;hs_ucsi_ccg_p0&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='ctx'> 				usb2-1 {</div><div class='ctx'> 					mode = "host";</div><div class='ctx'> 					status = "okay";</div><div class='hunk'>@@ -82,6 +2088,11 @@</div><div class='ctx'> 					status = "okay";</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='add'>+				usb3-2 {</div><div class='add'>+					nvidia,usb2-companion = &lt;0&gt;;</div><div class='add'>+					status = "okay";</div><div class='add'>+				};</div><div class='add'>+</div><div class='ctx'> 				usb3-3 {</div><div class='ctx'> 					nvidia,usb2-companion = &lt;3&gt;;</div><div class='ctx'> 					maximum-speed = "super-speed";</div><div class='hunk'>@@ -90,14 +2101,88 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		usb@3550000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}&gt;,</div><div class='add'>+			       &lt;&amp;{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-2}&gt;;</div><div class='add'>+			phy-names = "usb2-0", "usb3-0";</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		usb@3610000 {</div><div class='ctx'> 			status = "okay";</div><div class='ctx'> </div><div class='del'>-			phys =	&lt;&amp;{/cbb@0/padctl@3520000/pads/usb2/lanes/usb2-1}&gt;,</div><div class='del'>-				&lt;&amp;{/cbb@0/padctl@3520000/pads/usb2/lanes/usb2-3}&gt;,</div><div class='del'>-				&lt;&amp;{/cbb@0/padctl@3520000/pads/usb3/lanes/usb3-0}&gt;,</div><div class='del'>-				&lt;&amp;{/cbb@0/padctl@3520000/pads/usb3/lanes/usb3-3}&gt;;</div><div class='del'>-			phy-names = "usb2-1", "usb2-3", "usb3-0", "usb3-3";</div><div class='add'>+			phys =	&lt;&amp;{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}&gt;,</div><div class='add'>+				&lt;&amp;{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}&gt;,</div><div class='add'>+				&lt;&amp;{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-3}&gt;,</div><div class='add'>+				&lt;&amp;{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-0}&gt;,</div><div class='add'>+				&lt;&amp;{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-2}&gt;,</div><div class='add'>+				&lt;&amp;{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-3}&gt;;</div><div class='add'>+			phy-names = "usb2-0", "usb2-1", "usb2-3", "usb3-0", "usb3-2", "usb3-3";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cec@3960000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			hdmi-phandle = &lt;&amp;sor2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@c240000 {</div><div class='add'>+			typec@8 {</div><div class='add'>+				compatible = "cypress,cypd4226";</div><div class='add'>+				reg = &lt;0x08&gt;;</div><div class='add'>+				interrupt-parent = &lt;&amp;gpio_aon&gt;;</div><div class='add'>+				interrupts = &lt;TEGRA194_AON_GPIO(BB, 2) IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+				firmware-name = "nvidia,jetson-agx-xavier";</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				ccg_typec_con0: connector@0 {</div><div class='add'>+					compatible = "usb-c-connector";</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					label = "USB-C";</div><div class='add'>+					data-role = "dual";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							hs_ucsi_ccg_p0: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;hs_typec_p0&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@c250000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			rt5658: audio-codec@1a {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				compatible = "realtek,rt5658";</div><div class='add'>+				reg = &lt;0x1a&gt;;</div><div class='add'>+				interrupt-parent = &lt;&amp;gpio&gt;;</div><div class='add'>+				interrupts = &lt;TEGRA194_MAIN_GPIO(S, 5) GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;bpmp TEGRA194_CLK_AUD_MCLK&gt;;</div><div class='add'>+				clock-names = "mclk";</div><div class='add'>+				realtek,jd-src = &lt;2&gt;;</div><div class='add'>+				sound-name-prefix = "CVB-RT";</div><div class='add'>+</div><div class='add'>+				port {</div><div class='add'>+					rt5658_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;i2s1_dap_ep&gt;;</div><div class='add'>+						mclk-fs = &lt;256&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		pwm@c340000 {</div><div class='hunk'>@@ -145,8 +2230,8 @@</div><div class='ctx'> 			sor@15b80000 {</div><div class='ctx'> 				status = "okay";</div><div class='ctx'> </div><div class='del'>-				avdd-io-supply = &lt;&amp;vdd_1v0&gt;;</div><div class='del'>-				vdd-pll-supply = &lt;&amp;vdd_1v8hs&gt;;</div><div class='add'>+				avdd-io-hdmi-dp-supply = &lt;&amp;vdd_1v0&gt;;</div><div class='add'>+				vdd-hdmi-dp-pll-supply = &lt;&amp;vdd_1v8hs&gt;;</div><div class='ctx'> 				hdmi-supply = &lt;&amp;vdd_hdmi&gt;;</div><div class='ctx'> </div><div class='ctx'> 				nvidia,ddc-i2c-bus = &lt;&amp;ddc&gt;;</div><div class='hunk'>@@ -154,81 +2239,73 @@</div><div class='ctx'> 							 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	pcie@14100000 {</div><div class='del'>-		status = "okay";</div><div class='ctx'> </div><div class='del'>-		vddio-pex-ctl-supply = &lt;&amp;vdd_1v8ao&gt;;</div><div class='del'>-</div><div class='del'>-		phys = &lt;&amp;p2u_hsio_0&gt;;</div><div class='del'>-		phy-names = "p2u-0";</div><div class='del'>-	};</div><div class='add'>+		pcie@14100000 {</div><div class='add'>+			status = "okay";</div><div class='ctx'> </div><div class='del'>-	pcie@14140000 {</div><div class='del'>-		status = "okay";</div><div class='add'>+			vddio-pex-ctl-supply = &lt;&amp;vdd_1v8ao&gt;;</div><div class='ctx'> </div><div class='del'>-		vddio-pex-ctl-supply = &lt;&amp;vdd_1v8ao&gt;;</div><div class='add'>+			phys = &lt;&amp;p2u_hsio_0&gt;;</div><div class='add'>+			phy-names = "p2u-0";</div><div class='add'>+		};</div><div class='ctx'> </div><div class='del'>-		phys = &lt;&amp;p2u_hsio_7&gt;;</div><div class='del'>-		phy-names = "p2u-0";</div><div class='del'>-	};</div><div class='add'>+		pcie@14140000 {</div><div class='add'>+			status = "okay";</div><div class='ctx'> </div><div class='del'>-	pcie@14180000 {</div><div class='del'>-		status = "okay";</div><div class='add'>+			vddio-pex-ctl-supply = &lt;&amp;vdd_1v8ao&gt;;</div><div class='ctx'> </div><div class='del'>-		vddio-pex-ctl-supply = &lt;&amp;vdd_1v8ao&gt;;</div><div class='add'>+			phys = &lt;&amp;p2u_hsio_7&gt;;</div><div class='add'>+			phy-names = "p2u-0";</div><div class='add'>+		};</div><div class='ctx'> </div><div class='del'>-		phys = &lt;&amp;p2u_hsio_2&gt;, &lt;&amp;p2u_hsio_3&gt;, &lt;&amp;p2u_hsio_4&gt;,</div><div class='del'>-		       &lt;&amp;p2u_hsio_5&gt;;</div><div class='del'>-		phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";</div><div class='del'>-	};</div><div class='add'>+		pcie@14180000 {</div><div class='add'>+			status = "okay";</div><div class='ctx'> </div><div class='del'>-	pcie@141a0000 {</div><div class='del'>-		status = "okay";</div><div class='add'>+			vddio-pex-ctl-supply = &lt;&amp;vdd_1v8ao&gt;;</div><div class='ctx'> </div><div class='del'>-		vddio-pex-ctl-supply = &lt;&amp;vdd_1v8ao&gt;;</div><div class='del'>-		vpcie3v3-supply = &lt;&amp;vdd_3v3_pcie&gt;;</div><div class='del'>-		vpcie12v-supply = &lt;&amp;vdd_12v_pcie&gt;;</div><div class='add'>+			phys = &lt;&amp;p2u_hsio_2&gt;, &lt;&amp;p2u_hsio_3&gt;, &lt;&amp;p2u_hsio_4&gt;,</div><div class='add'>+			       &lt;&amp;p2u_hsio_5&gt;;</div><div class='add'>+			phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";</div><div class='add'>+		};</div><div class='ctx'> </div><div class='del'>-		phys = &lt;&amp;p2u_nvhs_0&gt;, &lt;&amp;p2u_nvhs_1&gt;, &lt;&amp;p2u_nvhs_2&gt;,</div><div class='del'>-		       &lt;&amp;p2u_nvhs_3&gt;, &lt;&amp;p2u_nvhs_4&gt;, &lt;&amp;p2u_nvhs_5&gt;,</div><div class='del'>-		       &lt;&amp;p2u_nvhs_6&gt;, &lt;&amp;p2u_nvhs_7&gt;;</div><div class='add'>+		pcie@141a0000 {</div><div class='add'>+			status = "okay";</div><div class='ctx'> </div><div class='del'>-		phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",</div><div class='del'>-			    "p2u-5", "p2u-6", "p2u-7";</div><div class='del'>-	};</div><div class='add'>+			vddio-pex-ctl-supply = &lt;&amp;vdd_1v8ao&gt;;</div><div class='add'>+			vpcie3v3-supply = &lt;&amp;vdd_3v3_pcie&gt;;</div><div class='add'>+			vpcie12v-supply = &lt;&amp;vdd_12v_pcie&gt;;</div><div class='ctx'> </div><div class='del'>-	pcie_ep@141a0000 {</div><div class='del'>-		status = "disabled";</div><div class='add'>+			phys = &lt;&amp;p2u_nvhs_0&gt;, &lt;&amp;p2u_nvhs_1&gt;, &lt;&amp;p2u_nvhs_2&gt;,</div><div class='add'>+			       &lt;&amp;p2u_nvhs_3&gt;, &lt;&amp;p2u_nvhs_4&gt;, &lt;&amp;p2u_nvhs_5&gt;,</div><div class='add'>+			       &lt;&amp;p2u_nvhs_6&gt;, &lt;&amp;p2u_nvhs_7&gt;;</div><div class='ctx'> </div><div class='del'>-		vddio-pex-ctl-supply = &lt;&amp;vdd_1v8ao&gt;;</div><div class='add'>+			phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",</div><div class='add'>+				    "p2u-5", "p2u-6", "p2u-7";</div><div class='add'>+		};</div><div class='ctx'> </div><div class='del'>-		reset-gpios = &lt;&amp;gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		pcie-ep@141a0000 {</div><div class='add'>+			status = "disabled";</div><div class='ctx'> </div><div class='del'>-		nvidia,refclk-select-gpios = &lt;&amp;gpio_aon TEGRA194_AON_GPIO(AA, 5)</div><div class='del'>-					      GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			vddio-pex-ctl-supply = &lt;&amp;vdd_1v8ao&gt;;</div><div class='ctx'> </div><div class='del'>-		phys = &lt;&amp;p2u_nvhs_0&gt;, &lt;&amp;p2u_nvhs_1&gt;, &lt;&amp;p2u_nvhs_2&gt;,</div><div class='del'>-		       &lt;&amp;p2u_nvhs_3&gt;, &lt;&amp;p2u_nvhs_4&gt;, &lt;&amp;p2u_nvhs_5&gt;,</div><div class='del'>-		       &lt;&amp;p2u_nvhs_6&gt;, &lt;&amp;p2u_nvhs_7&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> </div><div class='del'>-		phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",</div><div class='del'>-			    "p2u-5", "p2u-6", "p2u-7";</div><div class='del'>-	};</div><div class='add'>+			nvidia,refclk-select-gpios = &lt;&amp;gpio_aon TEGRA194_AON_GPIO(AA, 5)</div><div class='add'>+						      GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> </div><div class='del'>-	fan: fan {</div><div class='del'>-		compatible = "pwm-fan";</div><div class='del'>-		pwms = &lt;&amp;pwm4 0 45334&gt;;</div><div class='add'>+			phys = &lt;&amp;p2u_nvhs_0&gt;, &lt;&amp;p2u_nvhs_1&gt;, &lt;&amp;p2u_nvhs_2&gt;,</div><div class='add'>+			       &lt;&amp;p2u_nvhs_3&gt;, &lt;&amp;p2u_nvhs_4&gt;, &lt;&amp;p2u_nvhs_5&gt;,</div><div class='add'>+			       &lt;&amp;p2u_nvhs_6&gt;, &lt;&amp;p2u_nvhs_7&gt;;</div><div class='ctx'> </div><div class='del'>-		cooling-levels = &lt;0 64 128 255&gt;;</div><div class='del'>-		#cooling-cells = &lt;2&gt;;</div><div class='add'>+			phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",</div><div class='add'>+				    "p2u-5", "p2u-6", "p2u-7";</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	gpio-keys {</div><div class='ctx'> 		compatible = "gpio-keys";</div><div class='ctx'> </div><div class='del'>-		force-recovery {</div><div class='add'>+		key-force-recovery {</div><div class='ctx'> 			label = "Force Recovery";</div><div class='ctx'> 			gpios = &lt;&amp;gpio TEGRA194_MAIN_GPIO(G, 0)</div><div class='ctx'> 				       GPIO_ACTIVE_LOW&gt;;</div><div class='hunk'>@@ -237,7 +2314,7 @@</div><div class='ctx'> 			debounce-interval = &lt;10&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		power {</div><div class='add'>+		key-power {</div><div class='ctx'> 			label = "Power";</div><div class='ctx'> 			gpios = &lt;&amp;gpio_aon TEGRA194_AON_GPIO(EE, 4)</div><div class='ctx'> 					   GPIO_ACTIVE_LOW&gt;;</div><div class='hunk'>@@ -249,8 +2326,99 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	fan: pwm-fan {</div><div class='add'>+		compatible = "pwm-fan";</div><div class='add'>+		pwms = &lt;&amp;pwm4 0 45334&gt;;</div><div class='add'>+</div><div class='add'>+		cooling-levels = &lt;0 64 128 255&gt;;</div><div class='add'>+		#cooling-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "nvidia,tegra186-audio-graph-card";</div><div class='add'>+		status = "okay";</div><div class='add'>+</div><div class='add'>+		dais = /* ADMAIF (FE) Ports */</div><div class='add'>+		       &lt;&amp;admaif0_port&gt;, &lt;&amp;admaif1_port&gt;, &lt;&amp;admaif2_port&gt;, &lt;&amp;admaif3_port&gt;,</div><div class='add'>+		       &lt;&amp;admaif4_port&gt;, &lt;&amp;admaif5_port&gt;, &lt;&amp;admaif6_port&gt;, &lt;&amp;admaif7_port&gt;,</div><div class='add'>+		       &lt;&amp;admaif8_port&gt;, &lt;&amp;admaif9_port&gt;, &lt;&amp;admaif10_port&gt;, &lt;&amp;admaif11_port&gt;,</div><div class='add'>+		       &lt;&amp;admaif12_port&gt;, &lt;&amp;admaif13_port&gt;, &lt;&amp;admaif14_port&gt;, &lt;&amp;admaif15_port&gt;,</div><div class='add'>+		       &lt;&amp;admaif16_port&gt;, &lt;&amp;admaif17_port&gt;, &lt;&amp;admaif18_port&gt;, &lt;&amp;admaif19_port&gt;,</div><div class='add'>+		       /* XBAR Ports */</div><div class='add'>+		       &lt;&amp;xbar_i2s1_port&gt;, &lt;&amp;xbar_i2s2_port&gt;, &lt;&amp;xbar_i2s4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_i2s6_port&gt;, &lt;&amp;xbar_dmic3_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_sfc1_in_port&gt;, &lt;&amp;xbar_sfc2_in_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_sfc3_in_port&gt;, &lt;&amp;xbar_sfc4_in_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mvc1_in_port&gt;, &lt;&amp;xbar_mvc2_in_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx1_in1_port&gt;, &lt;&amp;xbar_amx1_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx1_in3_port&gt;, &lt;&amp;xbar_amx1_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx2_in1_port&gt;, &lt;&amp;xbar_amx2_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx2_in3_port&gt;, &lt;&amp;xbar_amx2_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx3_in1_port&gt;, &lt;&amp;xbar_amx3_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx3_in3_port&gt;, &lt;&amp;xbar_amx3_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx4_in1_port&gt;, &lt;&amp;xbar_amx4_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx4_in3_port&gt;, &lt;&amp;xbar_amx4_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_adx1_in_port&gt;, &lt;&amp;xbar_adx2_in_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_adx3_in_port&gt;, &lt;&amp;xbar_adx4_in_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mixer_in1_port&gt;, &lt;&amp;xbar_mixer_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mixer_in3_port&gt;, &lt;&amp;xbar_mixer_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mixer_in5_port&gt;, &lt;&amp;xbar_mixer_in6_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mixer_in7_port&gt;, &lt;&amp;xbar_mixer_in8_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mixer_in9_port&gt;, &lt;&amp;xbar_mixer_in10_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_asrc_in1_port&gt;, &lt;&amp;xbar_asrc_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_asrc_in3_port&gt;, &lt;&amp;xbar_asrc_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_asrc_in5_port&gt;, &lt;&amp;xbar_asrc_in6_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_asrc_in7_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_ope1_in_port&gt;,</div><div class='add'>+		       /* HW accelerators */</div><div class='add'>+		       &lt;&amp;sfc1_out_port&gt;, &lt;&amp;sfc2_out_port&gt;,</div><div class='add'>+		       &lt;&amp;sfc3_out_port&gt;, &lt;&amp;sfc4_out_port&gt;,</div><div class='add'>+		       &lt;&amp;mvc1_out_port&gt;, &lt;&amp;mvc2_out_port&gt;,</div><div class='add'>+		       &lt;&amp;amx1_out_port&gt;, &lt;&amp;amx2_out_port&gt;,</div><div class='add'>+		       &lt;&amp;amx3_out_port&gt;, &lt;&amp;amx4_out_port&gt;,</div><div class='add'>+		       &lt;&amp;adx1_out1_port&gt;, &lt;&amp;adx1_out2_port&gt;,</div><div class='add'>+		       &lt;&amp;adx1_out3_port&gt;, &lt;&amp;adx1_out4_port&gt;,</div><div class='add'>+		       &lt;&amp;adx2_out1_port&gt;, &lt;&amp;adx2_out2_port&gt;,</div><div class='add'>+		       &lt;&amp;adx2_out3_port&gt;, &lt;&amp;adx2_out4_port&gt;,</div><div class='add'>+		       &lt;&amp;adx3_out1_port&gt;, &lt;&amp;adx3_out2_port&gt;,</div><div class='add'>+		       &lt;&amp;adx3_out3_port&gt;, &lt;&amp;adx3_out4_port&gt;,</div><div class='add'>+		       &lt;&amp;adx4_out1_port&gt;, &lt;&amp;adx4_out2_port&gt;,</div><div class='add'>+		       &lt;&amp;adx4_out3_port&gt;, &lt;&amp;adx4_out4_port&gt;,</div><div class='add'>+		       &lt;&amp;mixer_out1_port&gt;, &lt;&amp;mixer_out2_port&gt;, &lt;&amp;mixer_out3_port&gt;,</div><div class='add'>+		       &lt;&amp;mixer_out4_port&gt;, &lt;&amp;mixer_out5_port&gt;,</div><div class='add'>+		       &lt;&amp;asrc_out1_port&gt;, &lt;&amp;asrc_out2_port&gt;, &lt;&amp;asrc_out3_port&gt;,</div><div class='add'>+		       &lt;&amp;asrc_out4_port&gt;, &lt;&amp;asrc_out5_port&gt;, &lt;&amp;asrc_out6_port&gt;,</div><div class='add'>+		       &lt;&amp;ope1_out_port&gt;,</div><div class='add'>+		       /* BE I/O Ports */</div><div class='add'>+		       &lt;&amp;i2s1_port&gt;, &lt;&amp;i2s2_port&gt;, &lt;&amp;i2s4_port&gt;, &lt;&amp;i2s6_port&gt;,</div><div class='add'>+		       &lt;&amp;dmic3_port&gt;;</div><div class='add'>+</div><div class='add'>+		label = "NVIDIA Jetson AGX Xavier APE";</div><div class='add'>+</div><div class='add'>+		widgets =</div><div class='add'>+			"Microphone",	"CVB-RT MIC Jack",</div><div class='add'>+			"Microphone",	"CVB-RT MIC",</div><div class='add'>+			"Headphone",	"CVB-RT HP Jack",</div><div class='add'>+			"Speaker",	"CVB-RT SPK";</div><div class='add'>+</div><div class='add'>+		routing =</div><div class='add'>+			/* I2S1 &lt;-&gt; RT5658 */</div><div class='add'>+			"CVB-RT AIF1 Playback",	"I2S1 DAP-Playback",</div><div class='add'>+			"I2S1 DAP-Capture",	"CVB-RT AIF1 Capture",</div><div class='add'>+			/* RT5658 Codec controls */</div><div class='add'>+			"CVB-RT HP Jack",	"CVB-RT HPO L Playback",</div><div class='add'>+			"CVB-RT HP Jack",	"CVB-RT HPO R Playback",</div><div class='add'>+			"CVB-RT IN1P",		"CVB-RT MIC Jack",</div><div class='add'>+			"CVB-RT IN2P",		"CVB-RT MIC Jack",</div><div class='add'>+			"CVB-RT SPK",		"CVB-RT SPO Playback",</div><div class='add'>+			"CVB-RT DMIC L1",	"CVB-RT MIC",</div><div class='add'>+			"CVB-RT DMIC L2",	"CVB-RT MIC",</div><div class='add'>+			"CVB-RT DMIC R1",	"CVB-RT MIC",</div><div class='add'>+			"CVB-RT DMIC R2",	"CVB-RT MIC";</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	thermal-zones {</div><div class='del'>-		cpu {</div><div class='add'>+		cpu-thermal {</div><div class='ctx'> 			polling-delay = &lt;0&gt;;</div><div class='ctx'> 			polling-delay-passive = &lt;500&gt;;</div><div class='ctx'> 			status = "okay";</div><div class='hunk'>@@ -304,7 +2472,7 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		gpu {</div><div class='add'>+		gpu-thermal {</div><div class='ctx'> 			polling-delay = &lt;0&gt;;</div><div class='ctx'> 			polling-delay-passive = &lt;500&gt;;</div><div class='ctx'> 			status = "okay";</div><div class='hunk'>@@ -318,7 +2486,7 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		aux {</div><div class='add'>+		aux-thermal {</div><div class='ctx'> 			polling-delay = &lt;0&gt;;</div><div class='ctx'> 			polling-delay-passive = &lt;500&gt;;</div><div class='ctx'> 			status = "okay";</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0000.dts<br/>new file mode 100644<br/>index 000000000000..1c3874b677c0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0000.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0000.dts</a></div><div class='hunk'>@@ -0,0 +1,10 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "tegra194-p3668-0000.dtsi"</div><div class='add'>+#include "tegra194-p3509-0000.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "NVIDIA Jetson Xavier NX Developer Kit (SD-card)";</div><div class='add'>+	compatible = "nvidia,p3509-0000+p3668-0000", "nvidia,tegra194";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0001.dts b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0001.dts<br/>new file mode 100644<br/>index 000000000000..238fd98e8e45<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0001.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0001.dts</a></div><div class='hunk'>@@ -0,0 +1,10 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "tegra194-p3668-0001.dtsi"</div><div class='add'>+#include "tegra194-p3509-0000.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "NVIDIA Jetson Xavier NX Developer Kit (eMMC)";</div><div class='add'>+	compatible = "nvidia,p3509-0000+p3668-0001", "nvidia,tegra194";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi<br/>new file mode 100644<br/>index 000000000000..16cf4414de59<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi</a></div><div class='hunk'>@@ -0,0 +1,2486 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/tegra194-gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/linux-event-codes.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/gpio-keys.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	bus@0 {</div><div class='add'>+		aconnect@2900000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			ahub@2900800 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				i2s@2901200 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							i2s3_cif_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_i2s3_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						i2s3_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							i2s3_dap_ep: endpoint {</div><div class='add'>+								dai-format = "i2s";</div><div class='add'>+								/* Place holder for external Codec */</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				i2s@2901400 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							i2s5_cif_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_i2s5_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						i2s5_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							i2s5_dap_ep: endpoint {</div><div class='add'>+								dai-format = "i2s";</div><div class='add'>+								/* Place holder for external Codec */</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				sfc@2902000 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							sfc1_cif_in_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_sfc1_in_ep&gt;;</div><div class='add'>+								convert-rate = &lt;44100&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						sfc1_out_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							sfc1_cif_out_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_sfc1_out_ep&gt;;</div><div class='add'>+								convert-rate = &lt;48000&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				sfc@2902200 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							sfc2_cif_in_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_sfc2_in_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						sfc2_out_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							sfc2_cif_out_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_sfc2_out_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				sfc@2902400 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							sfc3_cif_in_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_sfc3_in_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						sfc3_out_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							sfc3_cif_out_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_sfc3_out_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				sfc@2902600 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							sfc4_cif_in_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_sfc4_in_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						sfc4_out_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							sfc4_cif_out_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_sfc4_out_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				amx@2903000 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							amx1_in1_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx1_in1_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							amx1_in2_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx1_in2_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@2 {</div><div class='add'>+							reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+							amx1_in3_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx1_in3_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@3 {</div><div class='add'>+							reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+							amx1_in4_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx1_in4_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						amx1_out_port: port@4 {</div><div class='add'>+							reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+							amx1_out_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx1_out_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				amx@2903100 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							amx2_in1_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx2_in1_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							amx2_in2_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx2_in2_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						amx2_in3_port: port@2 {</div><div class='add'>+							reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+							amx2_in3_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx2_in3_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						amx2_in4_port: port@3 {</div><div class='add'>+							reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+							amx2_in4_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx2_in4_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						amx2_out_port: port@4 {</div><div class='add'>+							reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+							amx2_out_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx2_out_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				amx@2903200 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							amx3_in1_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx3_in1_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							amx3_in2_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx3_in2_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@2 {</div><div class='add'>+							reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+							amx3_in3_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx3_in3_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@3 {</div><div class='add'>+							reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+							amx3_in4_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx3_in4_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						amx3_out_port: port@4 {</div><div class='add'>+							reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+							amx3_out_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx3_out_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				amx@2903300 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							amx4_in1_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx4_in1_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							amx4_in2_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx4_in2_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@2 {</div><div class='add'>+							reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+							amx4_in3_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx4_in3_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@3 {</div><div class='add'>+							reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+							amx4_in4_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx4_in4_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						amx4_out_port: port@4 {</div><div class='add'>+							reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+							amx4_out_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx4_out_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				adx@2903800 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							adx1_in_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx1_in_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx1_out1_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							adx1_out1_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx1_out1_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx1_out2_port: port@2 {</div><div class='add'>+							reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+							adx1_out2_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx1_out2_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx1_out3_port: port@3 {</div><div class='add'>+							reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+							adx1_out3_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx1_out3_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx1_out4_port: port@4 {</div><div class='add'>+							reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+							adx1_out4_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx1_out4_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				adx@2903900 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							adx2_in_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx2_in_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx2_out1_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							adx2_out1_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx2_out1_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx2_out2_port: port@2 {</div><div class='add'>+							reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+							adx2_out2_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx2_out2_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx2_out3_port: port@3 {</div><div class='add'>+							reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+							adx2_out3_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx2_out3_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx2_out4_port: port@4 {</div><div class='add'>+							reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+							adx2_out4_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx2_out4_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				adx@2903a00 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							adx3_in_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx3_in_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx3_out1_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							adx3_out1_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx3_out1_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx3_out2_port: port@2 {</div><div class='add'>+							reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+							adx3_out2_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx3_out2_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx3_out3_port: port@3 {</div><div class='add'>+							reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+							adx3_out3_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx3_out3_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx3_out4_port: port@4 {</div><div class='add'>+							reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+							adx3_out4_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx3_out4_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				adx@2903b00 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							adx4_in_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx4_in_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx4_out1_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							adx4_out1_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx4_out1_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx4_out2_port: port@2 {</div><div class='add'>+							reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+							adx4_out2_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx4_out2_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx4_out3_port: port@3 {</div><div class='add'>+							reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+							adx4_out3_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx4_out3_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx4_out4_port: port@4 {</div><div class='add'>+							reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+							adx4_out4_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx4_out4_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				dmic@2904000 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							dmic1_cif_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_dmic1_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						dmic1_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							dmic1_dap_ep: endpoint {</div><div class='add'>+								/* Place holder for external Codec */</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				dmic@2904100 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							dmic2_cif_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_dmic2_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						dmic2_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							dmic2_dap_ep: endpoint {</div><div class='add'>+								/* Place holder for external Codec */</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				dmic@2904300 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							dmic4_cif_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_dmic4_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						dmic4_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							dmic4_dap_ep: endpoint {</div><div class='add'>+								/* Place holder for external Codec */</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				dspk@2905000 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							dspk1_cif_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_dspk1_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						dspk1_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							dspk1_dap_ep: endpoint {</div><div class='add'>+								/* Place holder for external Codec */</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				dspk@2905100 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							dspk2_cif_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_dspk2_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						dspk2_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							dspk2_dap_ep: endpoint {</div><div class='add'>+								/* Place holder for external Codec */</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				processing-engine@2908000 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0x0&gt;;</div><div class='add'>+</div><div class='add'>+							ope1_cif_in_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_ope1_in_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						ope1_out_port: port@1 {</div><div class='add'>+							reg = &lt;0x1&gt;;</div><div class='add'>+</div><div class='add'>+							ope1_cif_out_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_ope1_out_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				mvc@290a000 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							mvc1_cif_in_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mvc1_in_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						mvc1_out_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							mvc1_cif_out_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mvc1_out_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				mvc@290a200 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							mvc2_cif_in_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mvc2_in_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						mvc2_out_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							mvc2_cif_out_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mvc2_out_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				amixer@290bb00 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0x0&gt;;</div><div class='add'>+</div><div class='add'>+							mixer_in1_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mixer_in1_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@1 {</div><div class='add'>+							reg = &lt;0x1&gt;;</div><div class='add'>+</div><div class='add'>+							mixer_in2_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mixer_in2_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@2 {</div><div class='add'>+							reg = &lt;0x2&gt;;</div><div class='add'>+</div><div class='add'>+							mixer_in3_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mixer_in3_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@3 {</div><div class='add'>+							reg = &lt;0x3&gt;;</div><div class='add'>+</div><div class='add'>+							mixer_in4_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mixer_in4_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@4 {</div><div class='add'>+							reg = &lt;0x4&gt;;</div><div class='add'>+</div><div class='add'>+							mixer_in5_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mixer_in5_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@5 {</div><div class='add'>+							reg = &lt;0x5&gt;;</div><div class='add'>+</div><div class='add'>+							mixer_in6_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mixer_in6_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@6 {</div><div class='add'>+							reg = &lt;0x6&gt;;</div><div class='add'>+</div><div class='add'>+							mixer_in7_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mixer_in7_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@7 {</div><div class='add'>+							reg = &lt;0x7&gt;;</div><div class='add'>+</div><div class='add'>+							mixer_in8_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mixer_in8_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@8 {</div><div class='add'>+							reg = &lt;0x8&gt;;</div><div class='add'>+</div><div class='add'>+							mixer_in9_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mixer_in9_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@9 {</div><div class='add'>+							reg = &lt;0x9&gt;;</div><div class='add'>+</div><div class='add'>+							mixer_in10_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mixer_in10_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						mixer_out1_port: port@a {</div><div class='add'>+							reg = &lt;0xa&gt;;</div><div class='add'>+</div><div class='add'>+							mixer_out1_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mixer_out1_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						mixer_out2_port: port@b {</div><div class='add'>+							reg = &lt;0xb&gt;;</div><div class='add'>+</div><div class='add'>+							mixer_out2_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mixer_out2_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						mixer_out3_port: port@c {</div><div class='add'>+							reg = &lt;0xc&gt;;</div><div class='add'>+</div><div class='add'>+							mixer_out3_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mixer_out3_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						mixer_out4_port: port@d {</div><div class='add'>+							reg = &lt;0xd&gt;;</div><div class='add'>+</div><div class='add'>+							mixer_out4_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mixer_out4_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						mixer_out5_port: port@e {</div><div class='add'>+							reg = &lt;0xe&gt;;</div><div class='add'>+</div><div class='add'>+							mixer_out5_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mixer_out5_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				admaif@290f000 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						admaif0_port: port@0 {</div><div class='add'>+							reg = &lt;0x0&gt;;</div><div class='add'>+</div><div class='add'>+							admaif0_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif0_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif1_port: port@1 {</div><div class='add'>+							reg = &lt;0x1&gt;;</div><div class='add'>+</div><div class='add'>+							admaif1_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif1_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif2_port: port@2 {</div><div class='add'>+							reg = &lt;0x2&gt;;</div><div class='add'>+</div><div class='add'>+							admaif2_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif2_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif3_port: port@3 {</div><div class='add'>+							reg = &lt;0x3&gt;;</div><div class='add'>+</div><div class='add'>+							admaif3_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif3_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif4_port: port@4 {</div><div class='add'>+							reg = &lt;0x4&gt;;</div><div class='add'>+</div><div class='add'>+							admaif4_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif4_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif5_port: port@5 {</div><div class='add'>+							reg = &lt;0x5&gt;;</div><div class='add'>+</div><div class='add'>+							admaif5_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif5_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif6_port: port@6 {</div><div class='add'>+							reg = &lt;0x6&gt;;</div><div class='add'>+</div><div class='add'>+							admaif6_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif6_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif7_port: port@7 {</div><div class='add'>+							reg = &lt;0x7&gt;;</div><div class='add'>+</div><div class='add'>+							admaif7_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif7_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif8_port: port@8 {</div><div class='add'>+							reg = &lt;0x8&gt;;</div><div class='add'>+</div><div class='add'>+							admaif8_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif8_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif9_port: port@9 {</div><div class='add'>+							reg = &lt;0x9&gt;;</div><div class='add'>+</div><div class='add'>+							admaif9_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif9_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif10_port: port@a {</div><div class='add'>+							reg = &lt;0xa&gt;;</div><div class='add'>+</div><div class='add'>+							admaif10_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif10_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif11_port: port@b {</div><div class='add'>+							reg = &lt;0xb&gt;;</div><div class='add'>+</div><div class='add'>+							admaif11_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif11_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif12_port: port@c {</div><div class='add'>+							reg = &lt;0xc&gt;;</div><div class='add'>+</div><div class='add'>+							admaif12_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif12_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif13_port: port@d {</div><div class='add'>+							reg = &lt;0xd&gt;;</div><div class='add'>+</div><div class='add'>+							admaif13_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif13_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif14_port: port@e {</div><div class='add'>+							reg = &lt;0xe&gt;;</div><div class='add'>+</div><div class='add'>+							admaif14_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif14_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif15_port: port@f {</div><div class='add'>+							reg = &lt;0xf&gt;;</div><div class='add'>+</div><div class='add'>+							admaif15_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif15_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif16_port: port@10 {</div><div class='add'>+							reg = &lt;0x10&gt;;</div><div class='add'>+</div><div class='add'>+							admaif16_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif16_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif17_port: port@11 {</div><div class='add'>+							reg = &lt;0x11&gt;;</div><div class='add'>+</div><div class='add'>+							admaif17_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif17_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif18_port: port@12 {</div><div class='add'>+							reg = &lt;0x12&gt;;</div><div class='add'>+</div><div class='add'>+							admaif18_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif18_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif19_port: port@13 {</div><div class='add'>+							reg = &lt;0x13&gt;;</div><div class='add'>+</div><div class='add'>+							admaif19_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif19_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				asrc@2910000 {</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0x0&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_in1_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_asrc_in1_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@1 {</div><div class='add'>+							reg = &lt;0x1&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_in2_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_asrc_in2_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@2 {</div><div class='add'>+							reg = &lt;0x2&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_in3_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_asrc_in3_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@3 {</div><div class='add'>+							reg = &lt;0x3&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_in4_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_asrc_in4_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@4 {</div><div class='add'>+							reg = &lt;0x4&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_in5_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_asrc_in5_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@5 {</div><div class='add'>+							reg = &lt;0x5&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_in6_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_asrc_in6_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@6 {</div><div class='add'>+							reg = &lt;0x6&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_in7_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_asrc_in7_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						asrc_out1_port: port@7 {</div><div class='add'>+							reg = &lt;0x7&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_out1_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_asrc_out1_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						asrc_out2_port: port@8 {</div><div class='add'>+							reg = &lt;0x8&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_out2_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_asrc_out2_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						asrc_out3_port: port@9 {</div><div class='add'>+							reg = &lt;0x9&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_out3_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_asrc_out3_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						asrc_out4_port: port@a {</div><div class='add'>+							reg = &lt;0xa&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_out4_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_asrc_out4_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						asrc_out5_port: port@b {</div><div class='add'>+							reg = &lt;0xb&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_out5_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_asrc_out5_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						asrc_out6_port:	port@c {</div><div class='add'>+							reg = &lt;0xc&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_out6_ep: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_asrc_out6_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0x0&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif0_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif0_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;0x1&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@2 {</div><div class='add'>+						reg = &lt;0x2&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@3 {</div><div class='add'>+						reg = &lt;0x3&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@4 {</div><div class='add'>+						reg = &lt;0x4&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@5 {</div><div class='add'>+						reg = &lt;0x5&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif5_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif5_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@6 {</div><div class='add'>+						reg = &lt;0x6&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif6_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif6_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@7 {</div><div class='add'>+						reg = &lt;0x7&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif7_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif7_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@8 {</div><div class='add'>+						reg = &lt;0x8&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif8_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif8_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@9 {</div><div class='add'>+						reg = &lt;0x9&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif9_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif9_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@a {</div><div class='add'>+						reg = &lt;0xa&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif10_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif10_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@b {</div><div class='add'>+						reg = &lt;0xb&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif11_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif11_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@c {</div><div class='add'>+						reg = &lt;0xc&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif12_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif12_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@d {</div><div class='add'>+						reg = &lt;0xd&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif13_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif13_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@e {</div><div class='add'>+						reg = &lt;0xe&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif14_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif14_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@f {</div><div class='add'>+						reg = &lt;0xf&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif15_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif15_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@10 {</div><div class='add'>+						reg = &lt;0x10&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif16_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif16_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@11 {</div><div class='add'>+						reg = &lt;0x11&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif17_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif17_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@12 {</div><div class='add'>+						reg = &lt;0x12&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif18_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif18_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@13 {</div><div class='add'>+						reg = &lt;0x13&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif19_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif19_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_i2s3_port: port@16 {</div><div class='add'>+						reg = &lt;0x16&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_i2s3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;i2s3_cif_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_i2s5_port: port@18 {</div><div class='add'>+						reg = &lt;0x18&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_i2s5_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;i2s5_cif_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_dmic1_port: port@1a {</div><div class='add'>+						reg = &lt;0x1a&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_dmic1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;dmic1_cif_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_dmic2_port: port@1b {</div><div class='add'>+						reg = &lt;0x1b&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_dmic2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;dmic2_cif_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_dmic4_port: port@1d {</div><div class='add'>+						reg = &lt;0x1d&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_dmic4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;dmic4_cif_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_dspk1_port: port@1e {</div><div class='add'>+						reg = &lt;0x1e&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_dspk1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;dspk1_cif_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_dspk2_port: port@1f {</div><div class='add'>+						reg = &lt;0x1f&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_dspk2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;dspk2_cif_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_sfc1_in_port: port@20 {</div><div class='add'>+						reg = &lt;0x20&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_sfc1_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;sfc1_cif_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@21 {</div><div class='add'>+						reg = &lt;0x21&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_sfc1_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;sfc1_cif_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_sfc2_in_port: port@22 {</div><div class='add'>+						reg = &lt;0x22&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_sfc2_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;sfc2_cif_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@23 {</div><div class='add'>+						reg = &lt;0x23&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_sfc2_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;sfc2_cif_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_sfc3_in_port: port@24 {</div><div class='add'>+						reg = &lt;0x24&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_sfc3_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;sfc3_cif_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@25 {</div><div class='add'>+						reg = &lt;0x25&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_sfc3_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;sfc3_cif_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_sfc4_in_port: port@26 {</div><div class='add'>+						reg = &lt;0x26&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_sfc4_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;sfc4_cif_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@27 {</div><div class='add'>+						reg = &lt;0x27&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_sfc4_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;sfc4_cif_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mvc1_in_port: port@28 {</div><div class='add'>+						reg = &lt;0x28&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mvc1_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mvc1_cif_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@29 {</div><div class='add'>+						reg = &lt;0x29&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mvc1_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mvc1_cif_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mvc2_in_port: port@2a {</div><div class='add'>+						reg = &lt;0x2a&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mvc2_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mvc2_cif_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@2b {</div><div class='add'>+						reg = &lt;0x2b&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mvc2_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mvc2_cif_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx1_in1_port: port@2c {</div><div class='add'>+						reg = &lt;0x2c&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx1_in1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx1_in1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx1_in2_port: port@2d {</div><div class='add'>+						reg = &lt;0x2d&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx1_in2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx1_in2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx1_in3_port: port@2e {</div><div class='add'>+						reg = &lt;0x2e&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx1_in3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx1_in3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx1_in4_port: port@2f {</div><div class='add'>+						reg = &lt;0x2f&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx1_in4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx1_in4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@30 {</div><div class='add'>+						reg = &lt;0x30&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx1_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx1_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx2_in1_port: port@31 {</div><div class='add'>+						reg = &lt;0x31&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx2_in1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx2_in1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx2_in2_port: port@32 {</div><div class='add'>+						reg = &lt;0x32&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx2_in2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx2_in2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx2_in3_port: port@33 {</div><div class='add'>+						reg = &lt;0x33&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx2_in3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx2_in3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx2_in4_port: port@34 {</div><div class='add'>+						reg = &lt;0x34&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx2_in4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx2_in4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@35 {</div><div class='add'>+						reg = &lt;0x35&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx2_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx2_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx3_in1_port: port@36 {</div><div class='add'>+						reg = &lt;0x36&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx3_in1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx3_in1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx3_in2_port: port@37 {</div><div class='add'>+						reg = &lt;0x37&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx3_in2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx3_in2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx3_in3_port: port@38 {</div><div class='add'>+						reg = &lt;0x38&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx3_in3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx3_in3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx3_in4_port: port@39 {</div><div class='add'>+						reg = &lt;0x39&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx3_in4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx3_in4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@3a {</div><div class='add'>+						reg = &lt;0x3a&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx3_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx3_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx4_in1_port: port@3b {</div><div class='add'>+						reg = &lt;0x3b&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx4_in1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx4_in1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx4_in2_port: port@3c {</div><div class='add'>+						reg = &lt;0x3c&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx4_in2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx4_in2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx4_in3_port: port@3d {</div><div class='add'>+						reg = &lt;0x3d&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx4_in3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx4_in3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx4_in4_port: port@3e {</div><div class='add'>+						reg = &lt;0x3e&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx4_in4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx4_in4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@3f {</div><div class='add'>+						reg = &lt;0x3f&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx4_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx4_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_adx1_in_port: port@40 {</div><div class='add'>+						reg = &lt;0x40&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx1_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx1_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@41 {</div><div class='add'>+						reg = &lt;0x41&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx1_out1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx1_out1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@42 {</div><div class='add'>+						reg = &lt;0x42&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx1_out2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx1_out2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@43 {</div><div class='add'>+						reg = &lt;0x43&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx1_out3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx1_out3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@44 {</div><div class='add'>+						reg = &lt;0x44&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx1_out4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx1_out4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_adx2_in_port: port@45 {</div><div class='add'>+						reg = &lt;0x45&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx2_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx2_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@46 {</div><div class='add'>+						reg = &lt;0x46&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx2_out1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx2_out1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@47 {</div><div class='add'>+						reg = &lt;0x47&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx2_out2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx2_out2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@48 {</div><div class='add'>+						reg = &lt;0x48&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx2_out3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx2_out3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@49 {</div><div class='add'>+						reg = &lt;0x49&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx2_out4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx2_out4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_adx3_in_port: port@4a {</div><div class='add'>+						reg = &lt;0x4a&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx3_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx3_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@4b {</div><div class='add'>+						reg = &lt;0x4b&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx3_out1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx3_out1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@4c {</div><div class='add'>+						reg = &lt;0x4c&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx3_out2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx3_out2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@4d {</div><div class='add'>+						reg = &lt;0x4d&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx3_out3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx3_out3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@4e {</div><div class='add'>+						reg = &lt;0x4e&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx3_out4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx3_out4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_adx4_in_port: port@4f {</div><div class='add'>+						reg = &lt;0x4f&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx4_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx4_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@50 {</div><div class='add'>+						reg = &lt;0x50&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx4_out1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx4_out1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@51 {</div><div class='add'>+						reg = &lt;0x51&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx4_out2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx4_out2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@52 {</div><div class='add'>+						reg = &lt;0x52&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx4_out3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx4_out3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@53 {</div><div class='add'>+						reg = &lt;0x53&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx4_out4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx4_out4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in1_port: port@54 {</div><div class='add'>+						reg = &lt;0x54&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mixer_in1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mixer_in1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in2_port: port@55 {</div><div class='add'>+						reg = &lt;0x55&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mixer_in2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mixer_in2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in3_port: port@56 {</div><div class='add'>+						reg = &lt;0x56&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mixer_in3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mixer_in3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in4_port: port@57 {</div><div class='add'>+						reg = &lt;0x57&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mixer_in4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mixer_in4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in5_port: port@58 {</div><div class='add'>+						reg = &lt;0x58&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mixer_in5_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mixer_in5_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in6_port: port@59 {</div><div class='add'>+						reg = &lt;0x59&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mixer_in6_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mixer_in6_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in7_port: port@5a {</div><div class='add'>+						reg = &lt;0x5a&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mixer_in7_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mixer_in7_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in8_port: port@5b {</div><div class='add'>+						reg = &lt;0x5b&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mixer_in8_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mixer_in8_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in9_port: port@5c {</div><div class='add'>+						reg = &lt;0x5c&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mixer_in9_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mixer_in9_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in10_port: port@5d {</div><div class='add'>+						reg = &lt;0x5d&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mixer_in10_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mixer_in10_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@5e {</div><div class='add'>+						reg = &lt;0x5e&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mixer_out1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mixer_out1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@5f {</div><div class='add'>+						reg = &lt;0x5f&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mixer_out2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mixer_out2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@60 {</div><div class='add'>+						reg = &lt;0x60&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mixer_out3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mixer_out3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@61 {</div><div class='add'>+						reg = &lt;0x61&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mixer_out4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mixer_out4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@62 {</div><div class='add'>+						reg = &lt;0x62&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mixer_out5_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mixer_out5_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_asrc_in1_port: port@63 {</div><div class='add'>+						reg = &lt;0x63&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_in1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_in1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@64 {</div><div class='add'>+						reg = &lt;0x64&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_out1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_out1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_asrc_in2_port: port@65 {</div><div class='add'>+						reg = &lt;0x65&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_in2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_in2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@66 {</div><div class='add'>+						reg = &lt;0x66&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_out2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_out2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_asrc_in3_port: port@67 {</div><div class='add'>+						reg = &lt;0x67&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_in3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_in3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@68 {</div><div class='add'>+						reg = &lt;0x68&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_out3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_out3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_asrc_in4_port: port@69 {</div><div class='add'>+						reg = &lt;0x69&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_in4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_in4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@6a {</div><div class='add'>+						reg = &lt;0x6a&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_out4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_out4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_asrc_in5_port: port@6b {</div><div class='add'>+						reg = &lt;0x6b&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_in5_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_in5_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@6c {</div><div class='add'>+						reg = &lt;0x6c&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_out5_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_out5_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_asrc_in6_port: port@6d {</div><div class='add'>+						reg = &lt;0x6d&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_in6_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_in6_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@6e {</div><div class='add'>+						reg = &lt;0x6e&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_out6_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_out6_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_asrc_in7_port: port@6f {</div><div class='add'>+						reg = &lt;0x6f&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_in7_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_in7_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_ope1_in_port: port@70 {</div><div class='add'>+						reg = &lt;0x70&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_ope1_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;ope1_cif_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@71 {</div><div class='add'>+						reg = &lt;0x71&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_ope1_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;ope1_cif_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			dma-controller@2930000 {</div><div class='add'>+				status = "okay";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			interrupt-controller@2a40000 {</div><div class='add'>+				status = "okay";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@3160000 {</div><div class='add'>+			eeprom@57 {</div><div class='add'>+				compatible = "atmel,24c02";</div><div class='add'>+				reg = &lt;0x57&gt;;</div><div class='add'>+</div><div class='add'>+				label = "system";</div><div class='add'>+				vcc-supply = &lt;&amp;vdd_1v8&gt;;</div><div class='add'>+				address-width = &lt;8&gt;;</div><div class='add'>+				pagesize = &lt;8&gt;;</div><div class='add'>+				size = &lt;256&gt;;</div><div class='add'>+				read-only;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ddc: i2c@3190000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi@3270000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			flash@0 {</div><div class='add'>+				compatible = "jedec,spi-nor";</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				spi-max-frequency = &lt;102000000&gt;;</div><div class='add'>+				spi-tx-bus-width = &lt;4&gt;;</div><div class='add'>+				spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pwm@32d0000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		hda@3510000 {</div><div class='add'>+			nvidia,model = "NVIDIA Jetson Xavier NX HDA";</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		padctl@3520000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			pads {</div><div class='add'>+				usb2 {</div><div class='add'>+					lanes {</div><div class='add'>+						usb2-0 {</div><div class='add'>+							status = "okay";</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						usb2-1 {</div><div class='add'>+							status = "okay";</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						usb2-2 {</div><div class='add'>+							status = "okay";</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usb3 {</div><div class='add'>+					lanes {</div><div class='add'>+						usb3-2 {</div><div class='add'>+							status = "okay";</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				usb2-0 {</div><div class='add'>+					mode = "otg";</div><div class='add'>+					status = "okay";</div><div class='add'>+					usb-role-switch;</div><div class='add'>+					connector {</div><div class='add'>+						compatible = "gpio-usb-b-connector",</div><div class='add'>+							"usb-b-connector";</div><div class='add'>+						label = "micro-USB";</div><div class='add'>+						type = "micro";</div><div class='add'>+						vbus-gpios = &lt;&amp;gpio TEGRA194_MAIN_GPIO(Z, 1)</div><div class='add'>+								    GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usb2-1 {</div><div class='add'>+					mode = "host";</div><div class='add'>+					status = "okay";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usb2-2 {</div><div class='add'>+					mode = "host";</div><div class='add'>+					vbus-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+					status = "okay";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usb3-2 {</div><div class='add'>+					nvidia,usb2-companion = &lt;1&gt;;</div><div class='add'>+					vbus-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+					status = "okay";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb@3550000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}&gt;;</div><div class='add'>+			phy-names = "usb2-0";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb@3610000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			phys =	&lt;&amp;{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}&gt;,</div><div class='add'>+				&lt;&amp;{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-2}&gt;,</div><div class='add'>+				&lt;&amp;{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-2}&gt;;</div><div class='add'>+			phy-names = "usb2-1", "usb2-2", "usb3-2";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cec@3960000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			hdmi-phandle = &lt;&amp;sor1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		host1x@13e00000 {</div><div class='add'>+			display-hub@15200000 {</div><div class='add'>+				status = "okay";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			dpaux@155c0000 {</div><div class='add'>+				status = "okay";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			dpaux@155d0000 {</div><div class='add'>+				status = "okay";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* DP0 */</div><div class='add'>+			sor@15b00000 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				avdd-io-hdmi-dp-supply = &lt;&amp;vdd_1v0&gt;;</div><div class='add'>+				vdd-hdmi-dp-pll-supply = &lt;&amp;vdd_1v8hs&gt;;</div><div class='add'>+</div><div class='add'>+				nvidia,dpaux = &lt;&amp;dpaux0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* HDMI */</div><div class='add'>+			sor@15b40000 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				avdd-io-hdmi-dp-supply = &lt;&amp;vdd_1v0&gt;;</div><div class='add'>+				vdd-hdmi-dp-pll-supply = &lt;&amp;vdd_1v8hs&gt;;</div><div class='add'>+				hdmi-supply = &lt;&amp;vdd_hdmi&gt;;</div><div class='add'>+</div><div class='add'>+				nvidia,ddc-i2c-bus = &lt;&amp;ddc&gt;;</div><div class='add'>+				nvidia,hpd-gpio = &lt;&amp;gpio TEGRA194_MAIN_GPIO(M, 1)</div><div class='add'>+							 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie@14160000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			vddio-pex-ctl-supply = &lt;&amp;vdd_1v8ao&gt;;</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;p2u_hsio_11&gt;;</div><div class='add'>+			phy-names = "p2u-0";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie@141a0000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			vddio-pex-ctl-supply = &lt;&amp;vdd_1v8ao&gt;;</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;p2u_nvhs_0&gt;, &lt;&amp;p2u_nvhs_1&gt;, &lt;&amp;p2u_nvhs_2&gt;,</div><div class='add'>+			       &lt;&amp;p2u_nvhs_3&gt;, &lt;&amp;p2u_nvhs_4&gt;, &lt;&amp;p2u_nvhs_5&gt;,</div><div class='add'>+			       &lt;&amp;p2u_nvhs_6&gt;, &lt;&amp;p2u_nvhs_7&gt;;</div><div class='add'>+</div><div class='add'>+			phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",</div><div class='add'>+				    "p2u-5", "p2u-6", "p2u-7";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie-ep@141a0000 {</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			vddio-pex-ctl-supply = &lt;&amp;vdd_1v8ao&gt;;</div><div class='add'>+</div><div class='add'>+			reset-gpios = &lt;&amp;gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+			nvidia,refclk-select-gpios = &lt;&amp;gpio_aon TEGRA194_AON_GPIO(AA, 5)</div><div class='add'>+						      GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;p2u_nvhs_0&gt;, &lt;&amp;p2u_nvhs_1&gt;, &lt;&amp;p2u_nvhs_2&gt;,</div><div class='add'>+			       &lt;&amp;p2u_nvhs_3&gt;, &lt;&amp;p2u_nvhs_4&gt;, &lt;&amp;p2u_nvhs_5&gt;,</div><div class='add'>+			       &lt;&amp;p2u_nvhs_6&gt;, &lt;&amp;p2u_nvhs_7&gt;;</div><div class='add'>+</div><div class='add'>+			phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",</div><div class='add'>+				    "p2u-5", "p2u-6", "p2u-7";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		key-force-recovery {</div><div class='add'>+			label = "Force Recovery";</div><div class='add'>+			gpios = &lt;&amp;gpio TEGRA194_MAIN_GPIO(G, 0)</div><div class='add'>+				       GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,input-type = &lt;EV_KEY&gt;;</div><div class='add'>+			linux,code = &lt;KEY_SLEEP&gt;;</div><div class='add'>+			debounce-interval = &lt;10&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-power {</div><div class='add'>+			label = "Power";</div><div class='add'>+			gpios = &lt;&amp;gpio_aon TEGRA194_AON_GPIO(EE, 4)</div><div class='add'>+					   GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,input-type = &lt;EV_KEY&gt;;</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+			debounce-interval = &lt;10&gt;;</div><div class='add'>+			wakeup-event-action = &lt;EV_ACT_ASSERTED&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fan: pwm-fan {</div><div class='add'>+		compatible = "pwm-fan";</div><div class='add'>+		pwms = &lt;&amp;pwm6 0 45334&gt;;</div><div class='add'>+</div><div class='add'>+		cooling-levels = &lt;0 64 128 255&gt;;</div><div class='add'>+		#cooling-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_5v0_sys: regulator-vdd-5v0-sys {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_5V_SYS";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_3v3_sys: regulator-vdd-3v3-sys {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_3V3_SYS";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_3v3_ao: regulator-vdd-3v3-ao {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_3V3_AO";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_1v8: regulator-vdd-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_1V8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_hdmi: regulator-vdd-hdmi {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_5V0_HDMI_CON";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "nvidia,tegra186-audio-graph-card";</div><div class='add'>+		status = "okay";</div><div class='add'>+</div><div class='add'>+		dais = /* ADMAIF (FE) Ports */</div><div class='add'>+		       &lt;&amp;admaif0_port&gt;, &lt;&amp;admaif1_port&gt;, &lt;&amp;admaif2_port&gt;, &lt;&amp;admaif3_port&gt;,</div><div class='add'>+		       &lt;&amp;admaif4_port&gt;, &lt;&amp;admaif5_port&gt;, &lt;&amp;admaif6_port&gt;, &lt;&amp;admaif7_port&gt;,</div><div class='add'>+		       &lt;&amp;admaif8_port&gt;, &lt;&amp;admaif9_port&gt;, &lt;&amp;admaif10_port&gt;, &lt;&amp;admaif11_port&gt;,</div><div class='add'>+		       &lt;&amp;admaif12_port&gt;, &lt;&amp;admaif13_port&gt;, &lt;&amp;admaif14_port&gt;, &lt;&amp;admaif15_port&gt;,</div><div class='add'>+		       &lt;&amp;admaif16_port&gt;, &lt;&amp;admaif17_port&gt;, &lt;&amp;admaif18_port&gt;, &lt;&amp;admaif19_port&gt;,</div><div class='add'>+		       /* XBAR Ports */</div><div class='add'>+		       &lt;&amp;xbar_i2s3_port&gt;, &lt;&amp;xbar_i2s5_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_dmic1_port&gt;, &lt;&amp;xbar_dmic2_port&gt;, &lt;&amp;xbar_dmic4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_dspk1_port&gt;, &lt;&amp;xbar_dspk2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_sfc1_in_port&gt;, &lt;&amp;xbar_sfc2_in_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_sfc3_in_port&gt;, &lt;&amp;xbar_sfc4_in_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mvc1_in_port&gt;, &lt;&amp;xbar_mvc2_in_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx1_in1_port&gt;, &lt;&amp;xbar_amx1_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx1_in3_port&gt;, &lt;&amp;xbar_amx1_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx2_in1_port&gt;, &lt;&amp;xbar_amx2_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx2_in3_port&gt;, &lt;&amp;xbar_amx2_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx3_in1_port&gt;, &lt;&amp;xbar_amx3_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx3_in3_port&gt;, &lt;&amp;xbar_amx3_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx4_in1_port&gt;, &lt;&amp;xbar_amx4_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx4_in3_port&gt;, &lt;&amp;xbar_amx4_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_adx1_in_port&gt;, &lt;&amp;xbar_adx2_in_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_adx3_in_port&gt;, &lt;&amp;xbar_adx4_in_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mixer_in1_port&gt;, &lt;&amp;xbar_mixer_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mixer_in3_port&gt;, &lt;&amp;xbar_mixer_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mixer_in5_port&gt;, &lt;&amp;xbar_mixer_in6_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mixer_in7_port&gt;, &lt;&amp;xbar_mixer_in8_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mixer_in9_port&gt;, &lt;&amp;xbar_mixer_in10_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_asrc_in1_port&gt;, &lt;&amp;xbar_asrc_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_asrc_in3_port&gt;, &lt;&amp;xbar_asrc_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_asrc_in5_port&gt;, &lt;&amp;xbar_asrc_in6_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_asrc_in7_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_ope1_in_port&gt;,</div><div class='add'>+		       /* HW accelerators */</div><div class='add'>+		       &lt;&amp;sfc1_out_port&gt;, &lt;&amp;sfc2_out_port&gt;,</div><div class='add'>+		       &lt;&amp;sfc3_out_port&gt;, &lt;&amp;sfc4_out_port&gt;,</div><div class='add'>+		       &lt;&amp;mvc1_out_port&gt;, &lt;&amp;mvc2_out_port&gt;,</div><div class='add'>+		       &lt;&amp;amx1_out_port&gt;, &lt;&amp;amx2_out_port&gt;,</div><div class='add'>+		       &lt;&amp;amx3_out_port&gt;, &lt;&amp;amx4_out_port&gt;,</div><div class='add'>+		       &lt;&amp;adx1_out1_port&gt;, &lt;&amp;adx1_out2_port&gt;,</div><div class='add'>+		       &lt;&amp;adx1_out3_port&gt;, &lt;&amp;adx1_out4_port&gt;,</div><div class='add'>+		       &lt;&amp;adx2_out1_port&gt;, &lt;&amp;adx2_out2_port&gt;,</div><div class='add'>+		       &lt;&amp;adx2_out3_port&gt;, &lt;&amp;adx2_out4_port&gt;,</div><div class='add'>+		       &lt;&amp;adx3_out1_port&gt;, &lt;&amp;adx3_out2_port&gt;,</div><div class='add'>+		       &lt;&amp;adx3_out3_port&gt;, &lt;&amp;adx3_out4_port&gt;,</div><div class='add'>+		       &lt;&amp;adx4_out1_port&gt;, &lt;&amp;adx4_out2_port&gt;,</div><div class='add'>+		       &lt;&amp;adx4_out3_port&gt;, &lt;&amp;adx4_out4_port&gt;,</div><div class='add'>+		       &lt;&amp;mixer_out1_port&gt;, &lt;&amp;mixer_out2_port&gt;,</div><div class='add'>+		       &lt;&amp;mixer_out3_port&gt;, &lt;&amp;mixer_out4_port&gt;,</div><div class='add'>+		       &lt;&amp;mixer_out5_port&gt;,</div><div class='add'>+		       &lt;&amp;asrc_out1_port&gt;, &lt;&amp;asrc_out2_port&gt;, &lt;&amp;asrc_out3_port&gt;,</div><div class='add'>+		       &lt;&amp;asrc_out4_port&gt;, &lt;&amp;asrc_out5_port&gt;, &lt;&amp;asrc_out6_port&gt;,</div><div class='add'>+		       &lt;&amp;ope1_out_port&gt;,</div><div class='add'>+		       /* BE I/O Ports */</div><div class='add'>+		       &lt;&amp;i2s3_port&gt;, &lt;&amp;i2s5_port&gt;,</div><div class='add'>+		       &lt;&amp;dmic1_port&gt;, &lt;&amp;dmic2_port&gt;, &lt;&amp;dmic4_port&gt;,</div><div class='add'>+		       &lt;&amp;dspk1_port&gt;, &lt;&amp;dspk2_port&gt;;</div><div class='add'>+</div><div class='add'>+		label = "NVIDIA Jetson Xavier NX APE";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	thermal-zones {</div><div class='add'>+		cpu-thermal {</div><div class='add'>+			polling-delay = &lt;0&gt;;</div><div class='add'>+			polling-delay-passive = &lt;500&gt;;</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu_trip_critical: critical {</div><div class='add'>+					temperature = &lt;96500&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_trip_hot: hot {</div><div class='add'>+					temperature = &lt;70000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_trip_active: active {</div><div class='add'>+					temperature = &lt;50000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "active";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_trip_passive: passive {</div><div class='add'>+					temperature = &lt;30000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				cpu-critical {</div><div class='add'>+					cooling-device = &lt;&amp;fan 3 3&gt;;</div><div class='add'>+					trip = &lt;&amp;cpu_trip_critical&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu-hot {</div><div class='add'>+					cooling-device = &lt;&amp;fan 2 2&gt;;</div><div class='add'>+					trip = &lt;&amp;cpu_trip_hot&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu-active {</div><div class='add'>+					cooling-device = &lt;&amp;fan 1 1&gt;;</div><div class='add'>+					trip = &lt;&amp;cpu_trip_active&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu-passive {</div><div class='add'>+					cooling-device = &lt;&amp;fan 0 0&gt;;</div><div class='add'>+					trip = &lt;&amp;cpu_trip_passive&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu-thermal {</div><div class='add'>+			polling-delay = &lt;0&gt;;</div><div class='add'>+			polling-delay-passive = &lt;500&gt;;</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				gpu_alert0: critical {</div><div class='add'>+					temperature = &lt;99000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aux-thermal {</div><div class='add'>+			polling-delay = &lt;0&gt;;</div><div class='add'>+			polling-delay-passive = &lt;500&gt;;</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				aux_alert0: critical {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3668-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3668-0000.dtsi<br/>new file mode 100644<br/>index 000000000000..8c2c709dd54c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra194-p3668-0000.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/tegra194-p3668-0000.dtsi</a></div><div class='hunk'>@@ -0,0 +1,32 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+#include "tegra194-p3668.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "NVIDIA Jetson Xavier NX (SD-card)";</div><div class='add'>+	compatible = "nvidia,p3668-0000", "nvidia,tegra194";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		mmc0 = "/bus@0/mmc@3400000";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bus@0 {</div><div class='add'>+		/* SDMMC1 (SD/MMC) */</div><div class='add'>+		mmc@3400000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+			bus-width = &lt;4&gt;;</div><div class='add'>+			cd-gpios = &lt;&amp;gpio TEGRA194_MAIN_GPIO(G, 7) GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			disable-wp;</div><div class='add'>+			vmmc-supply = &lt;&amp;vdd_3v3_sd&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_3v3_sd: regulator-vdd-3v3-sd {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_3V3_SD";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio TEGRA194_MAIN_GPIO(G, 2) GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3668-0001.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3668-0001.dtsi<br/>new file mode 100644<br/>index 000000000000..f5a9ebbfb12f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra194-p3668-0001.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/tegra194-p3668-0001.dtsi</a></div><div class='hunk'>@@ -0,0 +1,23 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+#include "tegra194-p3668.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "NVIDIA Jetson Xavier NX (eMMC)";</div><div class='add'>+	compatible = "nvidia,p3668-0001", "nvidia,tegra194";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		mmc0 = "/bus@0/mmc@3460000";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bus@0 {</div><div class='add'>+		/* SDMMC4 (eMMC) */</div><div class='add'>+		mmc@3460000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+			bus-width = &lt;8&gt;;</div><div class='add'>+			non-removable;</div><div class='add'>+</div><div class='add'>+			vqmmc-supply = &lt;&amp;vdd_1v8ls&gt;;</div><div class='add'>+			vmmc-supply = &lt;&amp;vdd_emmc_3v3&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi<br/>new file mode 100644<br/>index 000000000000..c0f17f8189fa<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi</a></div><div class='hunk'>@@ -0,0 +1,313 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+#include "tegra194.dtsi"</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/mfd/max77620.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = "/bus@0/ethernet@2490000";</div><div class='add'>+		i2c0 = "/bpmp/i2c";</div><div class='add'>+		i2c1 = "/bus@0/i2c@3160000";</div><div class='add'>+		i2c2 = "/bus@0/i2c@c240000";</div><div class='add'>+		i2c3 = "/bus@0/i2c@3180000";</div><div class='add'>+		i2c4 = "/bus@0/i2c@3190000";</div><div class='add'>+		i2c5 = "/bus@0/i2c@31c0000";</div><div class='add'>+		i2c6 = "/bus@0/i2c@c250000";</div><div class='add'>+		i2c7 = "/bus@0/i2c@31e0000";</div><div class='add'>+		rtc0 = "/bpmp/i2c/pmic@3c";</div><div class='add'>+		rtc1 = "/bus@0/rtc@c2a0000";</div><div class='add'>+		serial0 = &amp;tcu;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		bootargs = "console=ttyTCU0,115200n8";</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bus@0 {</div><div class='add'>+		ethernet@2490000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			phy-reset-gpios = &lt;&amp;gpio TEGRA194_MAIN_GPIO(R, 1) GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			phy-handle = &lt;&amp;phy&gt;;</div><div class='add'>+			phy-mode = "rgmii-id";</div><div class='add'>+</div><div class='add'>+			mdio {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				phy: ethernet-phy@0 {</div><div class='add'>+					compatible = "ethernet-phy-ieee802.3-c22";</div><div class='add'>+					reg = &lt;0x0&gt;;</div><div class='add'>+					interrupt-parent = &lt;&amp;gpio&gt;;</div><div class='add'>+					interrupts = &lt;TEGRA194_MAIN_GPIO(G, 4) IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+					#phy-cells = &lt;0&gt;;</div><div class='add'>+					wakeup-source;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		memory-controller@2c00000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@c250000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			power-sensor@40 {</div><div class='add'>+				compatible = "ti,ina3221";</div><div class='add'>+				reg = &lt;0x40&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				input@0 {</div><div class='add'>+					reg = &lt;0x0&gt;;</div><div class='add'>+					label = "VDD_IN";</div><div class='add'>+					shunt-resistor-micro-ohms = &lt;5000&gt;;</div><div class='add'>+				};</div><div class='add'>+				input@1 {</div><div class='add'>+					reg = &lt;0x1&gt;;</div><div class='add'>+					label = "VDD_CPU_GPU_CV";</div><div class='add'>+					shunt-resistor-micro-ohms = &lt;5000&gt;;</div><div class='add'>+				};</div><div class='add'>+				input@2 {</div><div class='add'>+					reg = &lt;0x2&gt;;</div><div class='add'>+					label = "VDD_SOC";</div><div class='add'>+					shunt-resistor-micro-ohms = &lt;5000&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		serial@3100000 {</div><div class='add'>+			/delete-property/ dmas;</div><div class='add'>+			/delete-property/ dma-names;</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@3160000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			eeprom@50 {</div><div class='add'>+				compatible = "atmel,24c02";</div><div class='add'>+				reg = &lt;0x50&gt;;</div><div class='add'>+</div><div class='add'>+				label = "module";</div><div class='add'>+				vcc-supply = &lt;&amp;vdd_1v8ls&gt;;</div><div class='add'>+				address-width = &lt;8&gt;;</div><div class='add'>+				pagesize = &lt;8&gt;;</div><div class='add'>+				size = &lt;256&gt;;</div><div class='add'>+				read-only;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		padctl@3520000 {</div><div class='add'>+			avdd-usb-supply = &lt;&amp;vdd_usb_3v3&gt;;</div><div class='add'>+			vclamp-usb-supply = &lt;&amp;vdd_1v8ao&gt;;</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				usb2-1 {</div><div class='add'>+					vbus-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usb2-3 {</div><div class='add'>+					vbus-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usb3-0 {</div><div class='add'>+					vbus-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usb3-3 {</div><div class='add'>+					vbus-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rtc@c2a0000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmc@c360000 {</div><div class='add'>+			nvidia,invert-interrupt;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bpmp {</div><div class='add'>+		i2c {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			pmic: pmic@3c {</div><div class='add'>+				compatible = "maxim,max20024";</div><div class='add'>+				reg = &lt;0x3c&gt;;</div><div class='add'>+</div><div class='add'>+				interrupt-parent = &lt;&amp;pmc&gt;;</div><div class='add'>+				interrupts = &lt;24 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+				#interrupt-cells = &lt;2&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+</div><div class='add'>+				#gpio-cells = &lt;2&gt;;</div><div class='add'>+				gpio-controller;</div><div class='add'>+</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;max20024_default&gt;;</div><div class='add'>+</div><div class='add'>+				fps {</div><div class='add'>+					fps0 {</div><div class='add'>+						maxim,fps-event-source = &lt;MAX77620_FPS_EVENT_SRC_EN0&gt;;</div><div class='add'>+						maxim,shutdown-fps-time-period-us = &lt;640&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					fps1 {</div><div class='add'>+						maxim,fps-event-source = &lt;MAX77620_FPS_EVENT_SRC_EN1&gt;;</div><div class='add'>+						maxim,shutdown-fps-time-period-us = &lt;640&gt;;</div><div class='add'>+						maxim,device-state-on-disabled-event = &lt;MAX77620_FPS_INACTIVE_STATE_SLEEP&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					fps2 {</div><div class='add'>+						maxim,fps-event-source = &lt;MAX77620_FPS_EVENT_SRC_EN0&gt;;</div><div class='add'>+						maxim,shutdown-fps-time-period-us = &lt;640&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				max20024_default: pinmux {</div><div class='add'>+					gpio0 {</div><div class='add'>+						pins = "gpio0";</div><div class='add'>+						function = "gpio";</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					gpio1 {</div><div class='add'>+						pins = "gpio1";</div><div class='add'>+						function = "fps-out";</div><div class='add'>+						maxim,active-fps-source = &lt;MAX77620_FPS_SRC_DEF&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					gpio2 {</div><div class='add'>+						pins = "gpio2";</div><div class='add'>+						function = "fps-out";</div><div class='add'>+						maxim,active-fps-source = &lt;MAX77620_FPS_SRC_DEF&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					gpio3 {</div><div class='add'>+						pins = "gpio3";</div><div class='add'>+						function = "fps-out";</div><div class='add'>+						maxim,active-fps-source = &lt;MAX77620_FPS_SRC_DEF&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					gpio4 {</div><div class='add'>+						pins = "gpio4";</div><div class='add'>+						function = "32k-out1";</div><div class='add'>+						drive-push-pull = &lt;1&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					gpio6 {</div><div class='add'>+						pins = "gpio6";</div><div class='add'>+						function = "gpio";</div><div class='add'>+						drive-push-pull = &lt;1&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					gpio7 {</div><div class='add'>+						pins = "gpio7";</div><div class='add'>+						function = "gpio";</div><div class='add'>+						drive-push-pull = &lt;0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				regulators {</div><div class='add'>+					in-sd0-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+					in-sd1-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+					in-sd2-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+					in-sd3-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+					in-sd4-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+</div><div class='add'>+					in-ldo0-1-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+					in-ldo2-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+					in-ldo3-5-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+					in-ldo4-6-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+					in-ldo7-8-supply = &lt;&amp;vdd_1v8ls&gt;;</div><div class='add'>+</div><div class='add'>+					vdd_1v0: sd0 {</div><div class='add'>+						regulator-name = "VDDIO_SYS_1V0";</div><div class='add'>+						regulator-min-microvolt = &lt;1000000&gt;;</div><div class='add'>+						regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+						regulator-always-on;</div><div class='add'>+						regulator-boot-on;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					vdd_1v8hs: sd1 {</div><div class='add'>+						regulator-name = "VDDIO_SYS_1V8HS";</div><div class='add'>+						regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+						regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+						regulator-always-on;</div><div class='add'>+						regulator-boot-on;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					vdd_1v8ls: sd2 {</div><div class='add'>+						regulator-name = "VDDIO_SYS_1V8LS";</div><div class='add'>+						regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+						regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+						regulator-always-on;</div><div class='add'>+						regulator-boot-on;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					vdd_1v8ao: sd3 {</div><div class='add'>+						regulator-name = "VDDIO_AO_1V8";</div><div class='add'>+						regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+						regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+						regulator-always-on;</div><div class='add'>+						regulator-boot-on;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					sd4 {</div><div class='add'>+						regulator-name = "VDD_DDR_1V1";</div><div class='add'>+						regulator-min-microvolt = &lt;1100000&gt;;</div><div class='add'>+						regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+						regulator-always-on;</div><div class='add'>+						regulator-boot-on;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					ldo0 {</div><div class='add'>+						regulator-name = "VDD_RTC";</div><div class='add'>+						regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+						regulator-max-microvolt = &lt;800000&gt;;</div><div class='add'>+						regulator-always-on;</div><div class='add'>+						regulator-boot-on;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					ldo2 {</div><div class='add'>+						regulator-name = "VDDIO_AO_3V3";</div><div class='add'>+						regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+						regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+						regulator-always-on;</div><div class='add'>+						regulator-boot-on;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					vdd_emmc_3v3: ldo3 {</div><div class='add'>+						regulator-name = "VDD_EMMC_3V3";</div><div class='add'>+						regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+						regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					vdd_usb_3v3: ldo5 {</div><div class='add'>+						regulator-name = "VDD_USB_3V3";</div><div class='add'>+						regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+						regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+						regulator-always-on;</div><div class='add'>+						regulator-boot-on;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					ldo6 {</div><div class='add'>+						regulator-name = "VDD_SDIO_3V3";</div><div class='add'>+						regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+						regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					ldo7 {</div><div class='add'>+						regulator-name = "AVDD_CSI_1V2";</div><div class='add'>+						regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+						regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi<br/>index f4ede86e32b4..b782f8db1288 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra194.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra194.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra194.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/tegra194.dtsi</a></div><div class='hunk'>@@ -3,6 +3,7 @@</div><div class='ctx'> #include &lt;dt-bindings/gpio/tegra194-gpio.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/mailbox/tegra186-hsp.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/pinctrl-tegra-io-pad.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/pinctrl/pinctrl-tegra.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/power/tegra194-powergate.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/reset/tegra194-reset.h&gt;</div><div class='hunk'>@@ -16,40 +17,133 @@</div><div class='ctx'> 	#size-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='ctx'> 	/* control backbone */</div><div class='del'>-	cbb@0 {</div><div class='add'>+	bus@0 {</div><div class='ctx'> 		compatible = "simple-bus";</div><div class='del'>-		#address-cells = &lt;1&gt;;</div><div class='del'>-		#size-cells = &lt;1&gt;;</div><div class='del'>-		ranges = &lt;0x0 0x0 0x0 0x40000000&gt;;</div><div class='ctx'> </div><div class='del'>-		misc@100000 {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges = &lt;0x0 0x0 0x0 0x0 0x100 0x0&gt;;</div><div class='add'>+</div><div class='add'>+		apbmisc: misc@100000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-misc";</div><div class='del'>-			reg = &lt;0x00100000 0xf000&gt;,</div><div class='del'>-			      &lt;0x0010f000 0x1000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x00100000 0x0 0xf000&gt;,</div><div class='add'>+			      &lt;0x0 0x0010f000 0x0 0x1000&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		gpio: gpio@2200000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-gpio";</div><div class='ctx'> 			reg-names = "security", "gpio";</div><div class='del'>-			reg = &lt;0x2200000 0x10000&gt;,</div><div class='del'>-			      &lt;0x2210000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x2200000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0x2210000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 				     &lt;GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 				     &lt;GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 				     &lt;GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 				     &lt;GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				     &lt;GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				     &lt;GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 			interrupt-controller;</div><div class='ctx'> 			#gpio-cells = &lt;2&gt;;</div><div class='ctx'> 			gpio-controller;</div><div class='add'>+			gpio-ranges = &lt;&amp;pinmux 0 0 169&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cbb-noc@2300000 {</div><div class='add'>+			compatible = "nvidia,tegra194-cbb-noc";</div><div class='add'>+			reg = &lt;0x0 0x02300000 0x0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			nvidia,axi2apb = &lt;&amp;axi2apb&gt;;</div><div class='add'>+			nvidia,apbmisc = &lt;&amp;apbmisc&gt;;</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		axi2apb: axi2apb@2390000 {</div><div class='add'>+			compatible = "nvidia,tegra194-axi2apb";</div><div class='add'>+			reg = &lt;0x0 0x2390000 0x0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0x23a0000 0x0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0x23b0000 0x0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0x23c0000 0x0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0x23d0000 0x0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0x23e0000 0x0 0x1000&gt;;</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinmux: pinmux@2430000 {</div><div class='add'>+			compatible = "nvidia,tegra194-pinmux";</div><div class='add'>+			reg = &lt;0x0 0x2430000 0x0 0x17000&gt;;</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			pex_clkreq_c5_bi_dir_state: pinmux-pex-clkreq-c5-bi-dir {</div><div class='add'>+				clkreq {</div><div class='add'>+					nvidia,pins = "pex_l5_clkreq_n_pgg0";</div><div class='add'>+					nvidia,schmitt = &lt;TEGRA_PIN_DISABLE&gt;;</div><div class='add'>+					nvidia,enable-input = &lt;TEGRA_PIN_ENABLE&gt;;</div><div class='add'>+					nvidia,io-hv = &lt;TEGRA_PIN_ENABLE&gt;;</div><div class='add'>+					nvidia,tristate = &lt;TEGRA_PIN_DISABLE&gt;;</div><div class='add'>+					nvidia,pull = &lt;TEGRA_PIN_PULL_NONE&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pex_rst_c5_out_state: pinmux-pex-rst-c5-out {</div><div class='add'>+				pex_rst {</div><div class='add'>+					nvidia,pins = "pex_l5_rst_n_pgg1";</div><div class='add'>+					nvidia,schmitt = &lt;TEGRA_PIN_DISABLE&gt;;</div><div class='add'>+					nvidia,enable-input = &lt;TEGRA_PIN_DISABLE&gt;;</div><div class='add'>+					nvidia,io-hv = &lt;TEGRA_PIN_ENABLE&gt;;</div><div class='add'>+					nvidia,tristate = &lt;TEGRA_PIN_DISABLE&gt;;</div><div class='add'>+					nvidia,pull = &lt;TEGRA_PIN_PULL_NONE&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		ethernet@2490000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-eqos",</div><div class='ctx'> 				     "nvidia,tegra186-eqos",</div><div class='ctx'> 				     "snps,dwc-qos-ethernet-4.10";</div><div class='del'>-			reg = &lt;0x02490000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x02490000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;bpmp TEGRA194_CLK_AXI_CBB&gt;,</div><div class='ctx'> 				 &lt;&amp;bpmp TEGRA194_CLK_EQOS_AXI&gt;,</div><div class='hunk'>@@ -59,6 +153,10 @@</div><div class='ctx'> 			clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";</div><div class='ctx'> 			resets = &lt;&amp;bpmp TEGRA194_RESET_EQOS&gt;;</div><div class='ctx'> 			reset-names = "eqos";</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA194_MEMORY_CLIENT_EQOSR &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA194_MEMORY_CLIENT_EQOSW &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem", "write";</div><div class='add'>+			iommus = &lt;&amp;smmu TEGRA194_SID_EQOS&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> </div><div class='ctx'> 			snps,write-requests = &lt;1&gt;;</div><div class='hunk'>@@ -68,6 +166,51 @@</div><div class='ctx'> 			snps,rxpbl = &lt;8&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		gpcdma: dma-controller@2600000 {</div><div class='add'>+			compatible = "nvidia,tegra194-gpcdma",</div><div class='add'>+				     "nvidia,tegra186-gpcdma";</div><div class='add'>+			reg = &lt;0x0 0x2600000 0x0 0x210000&gt;;</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA194_RESET_GPCDMA&gt;;</div><div class='add'>+			reset-names = "gpcdma";</div><div class='add'>+			interrupts = &lt;GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+			iommus = &lt;&amp;smmu TEGRA194_SID_GPCDMA_0&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+			dma-channel-mask = &lt;0xfffffffe&gt;;</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		aconnect@2900000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-aconnect",</div><div class='ctx'> 				     "nvidia,tegra210-aconnect";</div><div class='hunk'>@@ -75,15 +218,393 @@</div><div class='ctx'> 				 &lt;&amp;bpmp TEGRA194_CLK_APB2APE&gt;;</div><div class='ctx'> 			clock-names = "ape", "apb2ape";</div><div class='ctx'> 			power-domains = &lt;&amp;bpmp TEGRA194_POWER_DOMAIN_AUD&gt;;</div><div class='del'>-			#address-cells = &lt;1&gt;;</div><div class='del'>-			#size-cells = &lt;1&gt;;</div><div class='del'>-			ranges = &lt;0x02900000 0x02900000 0x200000&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> </div><div class='del'>-			dma-controller@2930000 {</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges = &lt;0x0 0x02900000 0x0 0x02900000 0x0 0x200000&gt;;</div><div class='add'>+</div><div class='add'>+			tegra_ahub: ahub@2900800 {</div><div class='add'>+				compatible = "nvidia,tegra194-ahub",</div><div class='add'>+					     "nvidia,tegra186-ahub";</div><div class='add'>+				reg = &lt;0x0 0x02900800 0x0 0x800&gt;;</div><div class='add'>+				clocks = &lt;&amp;bpmp TEGRA194_CLK_AHUB&gt;;</div><div class='add'>+				clock-names = "ahub";</div><div class='add'>+				assigned-clocks = &lt;&amp;bpmp TEGRA194_CLK_AHUB&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;bpmp TEGRA194_CLK_PLLP_OUT0&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;81600000&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;2&gt;;</div><div class='add'>+				#size-cells = &lt;2&gt;;</div><div class='add'>+				ranges = &lt;0x0 0x02900800 0x0 0x02900800 0x0 0x11800&gt;;</div><div class='add'>+</div><div class='add'>+				tegra_i2s1: i2s@2901000 {</div><div class='add'>+					compatible = "nvidia,tegra194-i2s",</div><div class='add'>+						     "nvidia,tegra210-i2s";</div><div class='add'>+					reg = &lt;0x0 0x2901000 0x0 0x100&gt;;</div><div class='add'>+					clocks = &lt;&amp;bpmp TEGRA194_CLK_I2S1&gt;,</div><div class='add'>+						 &lt;&amp;bpmp TEGRA194_CLK_I2S1_SYNC_INPUT&gt;;</div><div class='add'>+					clock-names = "i2s", "sync_input";</div><div class='add'>+					assigned-clocks = &lt;&amp;bpmp TEGRA194_CLK_I2S1&gt;;</div><div class='add'>+					assigned-clock-parents = &lt;&amp;bpmp TEGRA194_CLK_PLLA_OUT0&gt;;</div><div class='add'>+					assigned-clock-rates = &lt;1536000&gt;;</div><div class='add'>+					sound-name-prefix = "I2S1";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_i2s2: i2s@2901100 {</div><div class='add'>+					compatible = "nvidia,tegra194-i2s",</div><div class='add'>+						     "nvidia,tegra210-i2s";</div><div class='add'>+					reg = &lt;0x0 0x2901100 0x0 0x100&gt;;</div><div class='add'>+					clocks = &lt;&amp;bpmp TEGRA194_CLK_I2S2&gt;,</div><div class='add'>+						 &lt;&amp;bpmp TEGRA194_CLK_I2S2_SYNC_INPUT&gt;;</div><div class='add'>+					clock-names = "i2s", "sync_input";</div><div class='add'>+					assigned-clocks = &lt;&amp;bpmp TEGRA194_CLK_I2S2&gt;;</div><div class='add'>+					assigned-clock-parents = &lt;&amp;bpmp TEGRA194_CLK_PLLA_OUT0&gt;;</div><div class='add'>+					assigned-clock-rates = &lt;1536000&gt;;</div><div class='add'>+					sound-name-prefix = "I2S2";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_i2s3: i2s@2901200 {</div><div class='add'>+					compatible = "nvidia,tegra194-i2s",</div><div class='add'>+						     "nvidia,tegra210-i2s";</div><div class='add'>+					reg = &lt;0x0 0x2901200 0x0 0x100&gt;;</div><div class='add'>+					clocks = &lt;&amp;bpmp TEGRA194_CLK_I2S3&gt;,</div><div class='add'>+						 &lt;&amp;bpmp TEGRA194_CLK_I2S3_SYNC_INPUT&gt;;</div><div class='add'>+					clock-names = "i2s", "sync_input";</div><div class='add'>+					assigned-clocks = &lt;&amp;bpmp TEGRA194_CLK_I2S3&gt;;</div><div class='add'>+					assigned-clock-parents = &lt;&amp;bpmp TEGRA194_CLK_PLLA_OUT0&gt;;</div><div class='add'>+					assigned-clock-rates = &lt;1536000&gt;;</div><div class='add'>+					sound-name-prefix = "I2S3";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_i2s4: i2s@2901300 {</div><div class='add'>+					compatible = "nvidia,tegra194-i2s",</div><div class='add'>+						     "nvidia,tegra210-i2s";</div><div class='add'>+					reg = &lt;0x0 0x2901300 0x0 0x100&gt;;</div><div class='add'>+					clocks = &lt;&amp;bpmp TEGRA194_CLK_I2S4&gt;,</div><div class='add'>+						 &lt;&amp;bpmp TEGRA194_CLK_I2S4_SYNC_INPUT&gt;;</div><div class='add'>+					clock-names = "i2s", "sync_input";</div><div class='add'>+					assigned-clocks = &lt;&amp;bpmp TEGRA194_CLK_I2S4&gt;;</div><div class='add'>+					assigned-clock-parents = &lt;&amp;bpmp TEGRA194_CLK_PLLA_OUT0&gt;;</div><div class='add'>+					assigned-clock-rates = &lt;1536000&gt;;</div><div class='add'>+					sound-name-prefix = "I2S4";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_i2s5: i2s@2901400 {</div><div class='add'>+					compatible = "nvidia,tegra194-i2s",</div><div class='add'>+						     "nvidia,tegra210-i2s";</div><div class='add'>+					reg = &lt;0x0 0x2901400 0x0 0x100&gt;;</div><div class='add'>+					clocks = &lt;&amp;bpmp TEGRA194_CLK_I2S5&gt;,</div><div class='add'>+						 &lt;&amp;bpmp TEGRA194_CLK_I2S5_SYNC_INPUT&gt;;</div><div class='add'>+					clock-names = "i2s", "sync_input";</div><div class='add'>+					assigned-clocks = &lt;&amp;bpmp TEGRA194_CLK_I2S5&gt;;</div><div class='add'>+					assigned-clock-parents = &lt;&amp;bpmp TEGRA194_CLK_PLLA_OUT0&gt;;</div><div class='add'>+					assigned-clock-rates = &lt;1536000&gt;;</div><div class='add'>+					sound-name-prefix = "I2S5";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_i2s6: i2s@2901500 {</div><div class='add'>+					compatible = "nvidia,tegra194-i2s",</div><div class='add'>+						     "nvidia,tegra210-i2s";</div><div class='add'>+					reg = &lt;0x0 0x2901500 0x0 0x100&gt;;</div><div class='add'>+					clocks = &lt;&amp;bpmp TEGRA194_CLK_I2S6&gt;,</div><div class='add'>+						 &lt;&amp;bpmp TEGRA194_CLK_I2S6_SYNC_INPUT&gt;;</div><div class='add'>+					clock-names = "i2s", "sync_input";</div><div class='add'>+					assigned-clocks = &lt;&amp;bpmp TEGRA194_CLK_I2S6&gt;;</div><div class='add'>+					assigned-clock-parents = &lt;&amp;bpmp TEGRA194_CLK_PLLA_OUT0&gt;;</div><div class='add'>+					assigned-clock-rates = &lt;1536000&gt;;</div><div class='add'>+					sound-name-prefix = "I2S6";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_sfc1: sfc@2902000 {</div><div class='add'>+					compatible = "nvidia,tegra194-sfc",</div><div class='add'>+						     "nvidia,tegra210-sfc";</div><div class='add'>+					reg = &lt;0x0 0x2902000 0x0 0x200&gt;;</div><div class='add'>+					sound-name-prefix = "SFC1";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_sfc2: sfc@2902200 {</div><div class='add'>+					compatible = "nvidia,tegra194-sfc",</div><div class='add'>+						     "nvidia,tegra210-sfc";</div><div class='add'>+					reg = &lt;0x0 0x2902200 0x0 0x200&gt;;</div><div class='add'>+					sound-name-prefix = "SFC2";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_sfc3: sfc@2902400 {</div><div class='add'>+					compatible = "nvidia,tegra194-sfc",</div><div class='add'>+						     "nvidia,tegra210-sfc";</div><div class='add'>+					reg = &lt;0x0 0x2902400 0x0 0x200&gt;;</div><div class='add'>+					sound-name-prefix = "SFC3";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_sfc4: sfc@2902600 {</div><div class='add'>+					compatible = "nvidia,tegra194-sfc",</div><div class='add'>+						     "nvidia,tegra210-sfc";</div><div class='add'>+					reg = &lt;0x0 0x2902600 0x0 0x200&gt;;</div><div class='add'>+					sound-name-prefix = "SFC4";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_amx1: amx@2903000 {</div><div class='add'>+					compatible = "nvidia,tegra194-amx";</div><div class='add'>+					reg = &lt;0x0 0x2903000 0x0 0x100&gt;;</div><div class='add'>+					sound-name-prefix = "AMX1";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_amx2: amx@2903100 {</div><div class='add'>+					compatible = "nvidia,tegra194-amx";</div><div class='add'>+					reg = &lt;0x0 0x2903100 0x0 0x100&gt;;</div><div class='add'>+					sound-name-prefix = "AMX2";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_amx3: amx@2903200 {</div><div class='add'>+					compatible = "nvidia,tegra194-amx";</div><div class='add'>+					reg = &lt;0x0 0x2903200 0x0 0x100&gt;;</div><div class='add'>+					sound-name-prefix = "AMX3";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_amx4: amx@2903300 {</div><div class='add'>+					compatible = "nvidia,tegra194-amx";</div><div class='add'>+					reg = &lt;0x0 0x2903300 0x0 0x100&gt;;</div><div class='add'>+					sound-name-prefix = "AMX4";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_adx1: adx@2903800 {</div><div class='add'>+					compatible = "nvidia,tegra194-adx",</div><div class='add'>+						     "nvidia,tegra210-adx";</div><div class='add'>+					reg = &lt;0x0 0x2903800 0x0 0x100&gt;;</div><div class='add'>+					sound-name-prefix = "ADX1";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_adx2: adx@2903900 {</div><div class='add'>+					compatible = "nvidia,tegra194-adx",</div><div class='add'>+						     "nvidia,tegra210-adx";</div><div class='add'>+					reg = &lt;0x0 0x2903900 0x0 0x100&gt;;</div><div class='add'>+					sound-name-prefix = "ADX2";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_adx3: adx@2903a00 {</div><div class='add'>+					compatible = "nvidia,tegra194-adx",</div><div class='add'>+						     "nvidia,tegra210-adx";</div><div class='add'>+					reg = &lt;0x0 0x2903a00 0x0 0x100&gt;;</div><div class='add'>+					sound-name-prefix = "ADX3";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_adx4: adx@2903b00 {</div><div class='add'>+					compatible = "nvidia,tegra194-adx",</div><div class='add'>+						     "nvidia,tegra210-adx";</div><div class='add'>+					reg = &lt;0x0 0x2903b00 0x0 0x100&gt;;</div><div class='add'>+					sound-name-prefix = "ADX4";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_dmic1: dmic@2904000 {</div><div class='add'>+					compatible = "nvidia,tegra194-dmic",</div><div class='add'>+						     "nvidia,tegra210-dmic";</div><div class='add'>+					reg = &lt;0x0 0x2904000 0x0 0x100&gt;;</div><div class='add'>+					clocks = &lt;&amp;bpmp TEGRA194_CLK_DMIC1&gt;;</div><div class='add'>+					clock-names = "dmic";</div><div class='add'>+					assigned-clocks = &lt;&amp;bpmp TEGRA194_CLK_DMIC1&gt;;</div><div class='add'>+					assigned-clock-parents = &lt;&amp;bpmp TEGRA194_CLK_PLLA_OUT0&gt;;</div><div class='add'>+					assigned-clock-rates = &lt;3072000&gt;;</div><div class='add'>+					sound-name-prefix = "DMIC1";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_dmic2: dmic@2904100 {</div><div class='add'>+					compatible = "nvidia,tegra194-dmic",</div><div class='add'>+						     "nvidia,tegra210-dmic";</div><div class='add'>+					reg = &lt;0x0 0x2904100 0x0 0x100&gt;;</div><div class='add'>+					clocks = &lt;&amp;bpmp TEGRA194_CLK_DMIC2&gt;;</div><div class='add'>+					clock-names = "dmic";</div><div class='add'>+					assigned-clocks = &lt;&amp;bpmp TEGRA194_CLK_DMIC2&gt;;</div><div class='add'>+					assigned-clock-parents = &lt;&amp;bpmp TEGRA194_CLK_PLLA_OUT0&gt;;</div><div class='add'>+					assigned-clock-rates = &lt;3072000&gt;;</div><div class='add'>+					sound-name-prefix = "DMIC2";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_dmic3: dmic@2904200 {</div><div class='add'>+					compatible = "nvidia,tegra194-dmic",</div><div class='add'>+						     "nvidia,tegra210-dmic";</div><div class='add'>+					reg = &lt;0x0 0x2904200 0x0 0x100&gt;;</div><div class='add'>+					clocks = &lt;&amp;bpmp TEGRA194_CLK_DMIC3&gt;;</div><div class='add'>+					clock-names = "dmic";</div><div class='add'>+					assigned-clocks = &lt;&amp;bpmp TEGRA194_CLK_DMIC3&gt;;</div><div class='add'>+					assigned-clock-parents = &lt;&amp;bpmp TEGRA194_CLK_PLLA_OUT0&gt;;</div><div class='add'>+					assigned-clock-rates = &lt;3072000&gt;;</div><div class='add'>+					sound-name-prefix = "DMIC3";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_dmic4: dmic@2904300 {</div><div class='add'>+					compatible = "nvidia,tegra194-dmic",</div><div class='add'>+						     "nvidia,tegra210-dmic";</div><div class='add'>+					reg = &lt;0x0 0x2904300 0x0 0x100&gt;;</div><div class='add'>+					clocks = &lt;&amp;bpmp TEGRA194_CLK_DMIC4&gt;;</div><div class='add'>+					clock-names = "dmic";</div><div class='add'>+					assigned-clocks = &lt;&amp;bpmp TEGRA194_CLK_DMIC4&gt;;</div><div class='add'>+					assigned-clock-parents = &lt;&amp;bpmp TEGRA194_CLK_PLLA_OUT0&gt;;</div><div class='add'>+					assigned-clock-rates = &lt;3072000&gt;;</div><div class='add'>+					sound-name-prefix = "DMIC4";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_dspk1: dspk@2905000 {</div><div class='add'>+					compatible = "nvidia,tegra194-dspk",</div><div class='add'>+						     "nvidia,tegra186-dspk";</div><div class='add'>+					reg = &lt;0x0 0x2905000 0x0 0x100&gt;;</div><div class='add'>+					clocks = &lt;&amp;bpmp TEGRA194_CLK_DSPK1&gt;;</div><div class='add'>+					clock-names = "dspk";</div><div class='add'>+					assigned-clocks = &lt;&amp;bpmp TEGRA194_CLK_DSPK1&gt;;</div><div class='add'>+					assigned-clock-parents = &lt;&amp;bpmp TEGRA194_CLK_PLLA_OUT0&gt;;</div><div class='add'>+					assigned-clock-rates = &lt;12288000&gt;;</div><div class='add'>+					sound-name-prefix = "DSPK1";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_dspk2: dspk@2905100 {</div><div class='add'>+					compatible = "nvidia,tegra194-dspk",</div><div class='add'>+						     "nvidia,tegra186-dspk";</div><div class='add'>+					reg = &lt;0x0 0x2905100 0x0 0x100&gt;;</div><div class='add'>+					clocks = &lt;&amp;bpmp TEGRA194_CLK_DSPK2&gt;;</div><div class='add'>+					clock-names = "dspk";</div><div class='add'>+					assigned-clocks = &lt;&amp;bpmp TEGRA194_CLK_DSPK2&gt;;</div><div class='add'>+					assigned-clock-parents = &lt;&amp;bpmp TEGRA194_CLK_PLLA_OUT0&gt;;</div><div class='add'>+					assigned-clock-rates = &lt;12288000&gt;;</div><div class='add'>+					sound-name-prefix = "DSPK2";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_ope1: processing-engine@2908000 {</div><div class='add'>+					compatible = "nvidia,tegra194-ope",</div><div class='add'>+						     "nvidia,tegra210-ope";</div><div class='add'>+					reg = &lt;0x0 0x2908000 0x0 0x100&gt;;</div><div class='add'>+					sound-name-prefix = "OPE1";</div><div class='add'>+					status = "disabled";</div><div class='add'>+</div><div class='add'>+					#address-cells = &lt;2&gt;;</div><div class='add'>+					#size-cells = &lt;2&gt;;</div><div class='add'>+					ranges;</div><div class='add'>+</div><div class='add'>+					equalizer@2908100 {</div><div class='add'>+						compatible = "nvidia,tegra194-peq",</div><div class='add'>+							     "nvidia,tegra210-peq";</div><div class='add'>+						reg = &lt;0x0 0x2908100 0x0 0x100&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					dynamic-range-compressor@2908200 {</div><div class='add'>+						compatible = "nvidia,tegra194-mbdrc",</div><div class='add'>+							     "nvidia,tegra210-mbdrc";</div><div class='add'>+						reg = &lt;0x0 0x2908200 0x0 0x200&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_mvc1: mvc@290a000 {</div><div class='add'>+					compatible = "nvidia,tegra194-mvc",</div><div class='add'>+						     "nvidia,tegra210-mvc";</div><div class='add'>+					reg = &lt;0x0 0x290a000 0x0 0x200&gt;;</div><div class='add'>+					sound-name-prefix = "MVC1";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_mvc2: mvc@290a200 {</div><div class='add'>+					compatible = "nvidia,tegra194-mvc",</div><div class='add'>+						     "nvidia,tegra210-mvc";</div><div class='add'>+					reg = &lt;0x0 0x290a200 0x0 0x200&gt;;</div><div class='add'>+					sound-name-prefix = "MVC2";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_amixer: amixer@290bb00 {</div><div class='add'>+					compatible = "nvidia,tegra194-amixer",</div><div class='add'>+						     "nvidia,tegra210-amixer";</div><div class='add'>+					reg = &lt;0x0 0x290bb00 0x0 0x800&gt;;</div><div class='add'>+					sound-name-prefix = "MIXER1";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_admaif: admaif@290f000 {</div><div class='add'>+					compatible = "nvidia,tegra194-admaif",</div><div class='add'>+						     "nvidia,tegra186-admaif";</div><div class='add'>+					reg = &lt;0x0 0x0290f000 0x0 0x1000&gt;;</div><div class='add'>+					dmas = &lt;&amp;adma 1&gt;, &lt;&amp;adma 1&gt;,</div><div class='add'>+					       &lt;&amp;adma 2&gt;, &lt;&amp;adma 2&gt;,</div><div class='add'>+					       &lt;&amp;adma 3&gt;, &lt;&amp;adma 3&gt;,</div><div class='add'>+					       &lt;&amp;adma 4&gt;, &lt;&amp;adma 4&gt;,</div><div class='add'>+					       &lt;&amp;adma 5&gt;, &lt;&amp;adma 5&gt;,</div><div class='add'>+					       &lt;&amp;adma 6&gt;, &lt;&amp;adma 6&gt;,</div><div class='add'>+					       &lt;&amp;adma 7&gt;, &lt;&amp;adma 7&gt;,</div><div class='add'>+					       &lt;&amp;adma 8&gt;, &lt;&amp;adma 8&gt;,</div><div class='add'>+					       &lt;&amp;adma 9&gt;, &lt;&amp;adma 9&gt;,</div><div class='add'>+					       &lt;&amp;adma 10&gt;, &lt;&amp;adma 10&gt;,</div><div class='add'>+					       &lt;&amp;adma 11&gt;, &lt;&amp;adma 11&gt;,</div><div class='add'>+					       &lt;&amp;adma 12&gt;, &lt;&amp;adma 12&gt;,</div><div class='add'>+					       &lt;&amp;adma 13&gt;, &lt;&amp;adma 13&gt;,</div><div class='add'>+					       &lt;&amp;adma 14&gt;, &lt;&amp;adma 14&gt;,</div><div class='add'>+					       &lt;&amp;adma 15&gt;, &lt;&amp;adma 15&gt;,</div><div class='add'>+					       &lt;&amp;adma 16&gt;, &lt;&amp;adma 16&gt;,</div><div class='add'>+					       &lt;&amp;adma 17&gt;, &lt;&amp;adma 17&gt;,</div><div class='add'>+					       &lt;&amp;adma 18&gt;, &lt;&amp;adma 18&gt;,</div><div class='add'>+					       &lt;&amp;adma 19&gt;, &lt;&amp;adma 19&gt;,</div><div class='add'>+					       &lt;&amp;adma 20&gt;, &lt;&amp;adma 20&gt;;</div><div class='add'>+					dma-names = "rx1", "tx1",</div><div class='add'>+						    "rx2", "tx2",</div><div class='add'>+						    "rx3", "tx3",</div><div class='add'>+						    "rx4", "tx4",</div><div class='add'>+						    "rx5", "tx5",</div><div class='add'>+						    "rx6", "tx6",</div><div class='add'>+						    "rx7", "tx7",</div><div class='add'>+						    "rx8", "tx8",</div><div class='add'>+						    "rx9", "tx9",</div><div class='add'>+						    "rx10", "tx10",</div><div class='add'>+						    "rx11", "tx11",</div><div class='add'>+						    "rx12", "tx12",</div><div class='add'>+						    "rx13", "tx13",</div><div class='add'>+						    "rx14", "tx14",</div><div class='add'>+						    "rx15", "tx15",</div><div class='add'>+						    "rx16", "tx16",</div><div class='add'>+						    "rx17", "tx17",</div><div class='add'>+						    "rx18", "tx18",</div><div class='add'>+						    "rx19", "tx19",</div><div class='add'>+						    "rx20", "tx20";</div><div class='add'>+					status = "disabled";</div><div class='add'>+					interconnects = &lt;&amp;mc TEGRA194_MEMORY_CLIENT_APEDMAR &amp;emc&gt;,</div><div class='add'>+							&lt;&amp;mc TEGRA194_MEMORY_CLIENT_APEDMAW &amp;emc&gt;;</div><div class='add'>+					interconnect-names = "dma-mem", "write";</div><div class='add'>+					iommus = &lt;&amp;smmu TEGRA194_SID_APE&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_asrc: asrc@2910000 {</div><div class='add'>+					compatible = "nvidia,tegra194-asrc",</div><div class='add'>+						     "nvidia,tegra186-asrc";</div><div class='add'>+					reg = &lt;0x0 0x2910000 0x0 0x2000&gt;;</div><div class='add'>+					sound-name-prefix = "ASRC1";</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			adma: dma-controller@2930000 {</div><div class='ctx'> 				compatible = "nvidia,tegra194-adma",</div><div class='ctx'> 					     "nvidia,tegra186-adma";</div><div class='del'>-				reg = &lt;0x02930000 0x20000&gt;;</div><div class='add'>+				reg = &lt;0x0 0x02930000 0x0 0x20000&gt;;</div><div class='ctx'> 				interrupt-parent = &lt;&amp;agic&gt;;</div><div class='ctx'> 				interrupts =  &lt;GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 					      &lt;GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='hunk'>@@ -128,8 +649,8 @@</div><div class='ctx'> 					     "nvidia,tegra210-agic";</div><div class='ctx'> 				#interrupt-cells = &lt;3&gt;;</div><div class='ctx'> 				interrupt-controller;</div><div class='del'>-				reg = &lt;0x02a41000 0x1000&gt;,</div><div class='del'>-				      &lt;0x02a42000 0x2000&gt;;</div><div class='add'>+				reg = &lt;0x0 0x02a41000 0x0 0x1000&gt;,</div><div class='add'>+				      &lt;0x0 0x02a42000 0x0 0x2000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 145</div><div class='ctx'> 					      (GIC_CPU_MASK_SIMPLE(4) |</div><div class='ctx'> 					       IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='hunk'>@@ -139,51 +660,38 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		pinmux: pinmux@2430000 {</div><div class='del'>-			compatible = "nvidia,tegra194-pinmux";</div><div class='del'>-			reg = &lt;0x2430000 0x17000</div><div class='del'>-			       0xc300000 0x4000&gt;;</div><div class='del'>-</div><div class='del'>-			status = "okay";</div><div class='del'>-</div><div class='del'>-			pex_rst_c5_out_state: pex_rst_c5_out {</div><div class='del'>-				pex_rst {</div><div class='del'>-					nvidia,pins = "pex_l5_rst_n_pgg1";</div><div class='del'>-					nvidia,schmitt = &lt;TEGRA_PIN_DISABLE&gt;;</div><div class='del'>-					nvidia,lpdr = &lt;TEGRA_PIN_ENABLE&gt;;</div><div class='del'>-					nvidia,enable-input = &lt;TEGRA_PIN_DISABLE&gt;;</div><div class='del'>-					nvidia,io-high-voltage = &lt;TEGRA_PIN_ENABLE&gt;;</div><div class='del'>-					nvidia,tristate = &lt;TEGRA_PIN_DISABLE&gt;;</div><div class='del'>-					nvidia,pull = &lt;TEGRA_PIN_PULL_NONE&gt;;</div><div class='del'>-				};</div><div class='del'>-			};</div><div class='del'>-</div><div class='del'>-			clkreq_c5_bi_dir_state: clkreq_c5_bi_dir {</div><div class='del'>-				clkreq {</div><div class='del'>-					nvidia,pins = "pex_l5_clkreq_n_pgg0";</div><div class='del'>-					nvidia,schmitt = &lt;TEGRA_PIN_DISABLE&gt;;</div><div class='del'>-					nvidia,lpdr = &lt;TEGRA_PIN_ENABLE&gt;;</div><div class='del'>-					nvidia,enable-input = &lt;TEGRA_PIN_ENABLE&gt;;</div><div class='del'>-					nvidia,io-high-voltage = &lt;TEGRA_PIN_ENABLE&gt;;</div><div class='del'>-					nvidia,tristate = &lt;TEGRA_PIN_DISABLE&gt;;</div><div class='del'>-					nvidia,pull = &lt;TEGRA_PIN_PULL_NONE&gt;;</div><div class='del'>-				};</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-</div><div class='ctx'> 		mc: memory-controller@2c00000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-mc";</div><div class='del'>-			reg = &lt;0x02c00000 0x100000&gt;,</div><div class='del'>-			      &lt;0x02b80000 0x040000&gt;,</div><div class='del'>-			      &lt;0x01700000 0x100000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x02c00000 0x0 0x10000&gt;,   /* MC-SID */</div><div class='add'>+			      &lt;0x0 0x02c10000 0x0 0x10000&gt;,   /* MC Broadcast*/</div><div class='add'>+			      &lt;0x0 0x02c20000 0x0 0x10000&gt;,   /* MC0 */</div><div class='add'>+			      &lt;0x0 0x02c30000 0x0 0x10000&gt;,   /* MC1 */</div><div class='add'>+			      &lt;0x0 0x02c40000 0x0 0x10000&gt;,   /* MC2 */</div><div class='add'>+			      &lt;0x0 0x02c50000 0x0 0x10000&gt;,   /* MC3 */</div><div class='add'>+			      &lt;0x0 0x02b80000 0x0 0x10000&gt;,   /* MC4 */</div><div class='add'>+			      &lt;0x0 0x02b90000 0x0 0x10000&gt;,   /* MC5 */</div><div class='add'>+			      &lt;0x0 0x02ba0000 0x0 0x10000&gt;,   /* MC6 */</div><div class='add'>+			      &lt;0x0 0x02bb0000 0x0 0x10000&gt;,   /* MC7 */</div><div class='add'>+			      &lt;0x0 0x01700000 0x0 0x10000&gt;,   /* MC8 */</div><div class='add'>+			      &lt;0x0 0x01710000 0x0 0x10000&gt;,   /* MC9 */</div><div class='add'>+			      &lt;0x0 0x01720000 0x0 0x10000&gt;,   /* MC10 */</div><div class='add'>+			      &lt;0x0 0x01730000 0x0 0x10000&gt;,   /* MC11 */</div><div class='add'>+			      &lt;0x0 0x01740000 0x0 0x10000&gt;,   /* MC12 */</div><div class='add'>+			      &lt;0x0 0x01750000 0x0 0x10000&gt;,   /* MC13 */</div><div class='add'>+			      &lt;0x0 0x01760000 0x0 0x10000&gt;,   /* MC14 */</div><div class='add'>+			      &lt;0x0 0x01770000 0x0 0x10000&gt;;   /* MC15 */</div><div class='add'>+			reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3",</div><div class='add'>+				    "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10",</div><div class='add'>+				    "ch11", "ch12", "ch13", "ch14", "ch15";</div><div class='add'>+			interrupts = &lt;GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#interconnect-cells = &lt;1&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> </div><div class='ctx'> 			#address-cells = &lt;2&gt;;</div><div class='ctx'> 			#size-cells = &lt;2&gt;;</div><div class='del'>-</div><div class='del'>-			ranges = &lt;0x01700000 0x0 0x01700000 0x0 0x100000&gt;,</div><div class='del'>-				 &lt;0x02b80000 0x0 0x02b80000 0x0 0x040000&gt;,</div><div class='del'>-				 &lt;0x02c00000 0x0 0x02c00000 0x0 0x100000&gt;;</div><div class='add'>+			ranges = &lt;0x0 0x01700000 0x0 0x01700000 0x0 0x100000&gt;,</div><div class='add'>+				 &lt;0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000&gt;,</div><div class='add'>+				 &lt;0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000&gt;;</div><div class='ctx'> </div><div class='ctx'> 			/*</div><div class='ctx'> 			 * Bit 39 of addresses passing through the memory</div><div class='hunk'>@@ -200,82 +708,101 @@</div><div class='ctx'> 			 *</div><div class='ctx'> 			 * Limit the DMA range for memory clients to [38:0].</div><div class='ctx'> 			 */</div><div class='del'>-			dma-ranges = &lt;0x0 0x0 0x0 0x80 0x0&gt;;</div><div class='add'>+			dma-ranges = &lt;0x0 0x0 0x0 0x0 0x80 0x0&gt;;</div><div class='ctx'> </div><div class='ctx'> 			emc: external-memory-controller@2c60000 {</div><div class='ctx'> 				compatible = "nvidia,tegra194-emc";</div><div class='ctx'> 				reg = &lt;0x0 0x02c60000 0x0 0x90000&gt;,</div><div class='ctx'> 				      &lt;0x0 0x01780000 0x0 0x80000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;bpmp TEGRA194_CLK_EMC&gt;;</div><div class='ctx'> 				clock-names = "emc";</div><div class='ctx'> </div><div class='add'>+				#interconnect-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='ctx'> 				nvidia,bpmp = &lt;&amp;bpmp&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		timer@3010000 {</div><div class='add'>+			compatible = "nvidia,tegra186-timer";</div><div class='add'>+			reg = &lt;0x0 0x03010000 0x0 0x000e0000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		uarta: serial@3100000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";</div><div class='del'>-			reg = &lt;0x03100000 0x40&gt;;</div><div class='add'>+			reg = &lt;0x0 0x03100000 0x0 0x40&gt;;</div><div class='ctx'> 			reg-shift = &lt;2&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;bpmp TEGRA194_CLK_UARTA&gt;;</div><div class='del'>-			clock-names = "serial";</div><div class='ctx'> 			resets = &lt;&amp;bpmp TEGRA194_RESET_UARTA&gt;;</div><div class='del'>-			reset-names = "serial";</div><div class='add'>+			dmas = &lt;&amp;gpcdma 8&gt;, &lt;&amp;gpcdma 8&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		uartb: serial@3110000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";</div><div class='del'>-			reg = &lt;0x03110000 0x40&gt;;</div><div class='add'>+			reg = &lt;0x0 0x03110000 0x0 0x40&gt;;</div><div class='ctx'> 			reg-shift = &lt;2&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;bpmp TEGRA194_CLK_UARTB&gt;;</div><div class='del'>-			clock-names = "serial";</div><div class='ctx'> 			resets = &lt;&amp;bpmp TEGRA194_RESET_UARTB&gt;;</div><div class='del'>-			reset-names = "serial";</div><div class='add'>+			dmas = &lt;&amp;gpcdma 9&gt;, &lt;&amp;gpcdma 9&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		uartd: serial@3130000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";</div><div class='del'>-			reg = &lt;0x03130000 0x40&gt;;</div><div class='add'>+			reg = &lt;0x0 0x03130000 0x0 0x40&gt;;</div><div class='ctx'> 			reg-shift = &lt;2&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;bpmp TEGRA194_CLK_UARTD&gt;;</div><div class='del'>-			clock-names = "serial";</div><div class='ctx'> 			resets = &lt;&amp;bpmp TEGRA194_RESET_UARTD&gt;;</div><div class='del'>-			reset-names = "serial";</div><div class='add'>+			dmas = &lt;&amp;gpcdma 19&gt;, &lt;&amp;gpcdma 19&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		uarte: serial@3140000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";</div><div class='del'>-			reg = &lt;0x03140000 0x40&gt;;</div><div class='add'>+			reg = &lt;0x0 0x03140000 0x0 0x40&gt;;</div><div class='ctx'> 			reg-shift = &lt;2&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;bpmp TEGRA194_CLK_UARTE&gt;;</div><div class='del'>-			clock-names = "serial";</div><div class='ctx'> 			resets = &lt;&amp;bpmp TEGRA194_RESET_UARTE&gt;;</div><div class='del'>-			reset-names = "serial";</div><div class='add'>+			dmas = &lt;&amp;gpcdma 20&gt;, &lt;&amp;gpcdma 20&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		uartf: serial@3150000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";</div><div class='del'>-			reg = &lt;0x03150000 0x40&gt;;</div><div class='add'>+			reg = &lt;0x0 0x03150000 0x0 0x40&gt;;</div><div class='ctx'> 			reg-shift = &lt;2&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;bpmp TEGRA194_CLK_UARTF&gt;;</div><div class='del'>-			clock-names = "serial";</div><div class='ctx'> 			resets = &lt;&amp;bpmp TEGRA194_RESET_UARTF&gt;;</div><div class='del'>-			reset-names = "serial";</div><div class='add'>+			dmas = &lt;&amp;gpcdma 12&gt;, &lt;&amp;gpcdma 12&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		gen1_i2c: i2c@3160000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-i2c";</div><div class='del'>-			reg = &lt;0x03160000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x03160000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='hunk'>@@ -283,24 +810,26 @@</div><div class='ctx'> 			clock-names = "div-clk";</div><div class='ctx'> 			resets = &lt;&amp;bpmp TEGRA194_RESET_I2C1&gt;;</div><div class='ctx'> 			reset-names = "i2c";</div><div class='add'>+			dmas = &lt;&amp;gpcdma 21&gt;, &lt;&amp;gpcdma 21&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		uarth: serial@3170000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";</div><div class='del'>-			reg = &lt;0x03170000 0x40&gt;;</div><div class='add'>+			reg = &lt;0x0 0x03170000 0x0 0x40&gt;;</div><div class='ctx'> 			reg-shift = &lt;2&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;bpmp TEGRA194_CLK_UARTH&gt;;</div><div class='del'>-			clock-names = "serial";</div><div class='ctx'> 			resets = &lt;&amp;bpmp TEGRA194_RESET_UARTH&gt;;</div><div class='del'>-			reset-names = "serial";</div><div class='add'>+			dmas = &lt;&amp;gpcdma 13&gt;, &lt;&amp;gpcdma 13&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cam_i2c: i2c@3180000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-i2c";</div><div class='del'>-			reg = &lt;0x03180000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x03180000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='hunk'>@@ -308,13 +837,15 @@</div><div class='ctx'> 			clock-names = "div-clk";</div><div class='ctx'> 			resets = &lt;&amp;bpmp TEGRA194_RESET_I2C3&gt;;</div><div class='ctx'> 			reset-names = "i2c";</div><div class='add'>+			dmas = &lt;&amp;gpcdma 23&gt;, &lt;&amp;gpcdma 23&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		/* shares pads with dpaux1 */</div><div class='ctx'> 		dp_aux_ch1_i2c: i2c@3190000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-i2c";</div><div class='del'>-			reg = &lt;0x03190000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x03190000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='hunk'>@@ -322,13 +853,18 @@</div><div class='ctx'> 			clock-names = "div-clk";</div><div class='ctx'> 			resets = &lt;&amp;bpmp TEGRA194_RESET_I2C4&gt;;</div><div class='ctx'> 			reset-names = "i2c";</div><div class='add'>+			pinctrl-0 = &lt;&amp;state_dpaux1_i2c&gt;;</div><div class='add'>+			pinctrl-1 = &lt;&amp;state_dpaux1_off&gt;;</div><div class='add'>+			pinctrl-names = "default", "idle";</div><div class='add'>+			dmas = &lt;&amp;gpcdma 26&gt;, &lt;&amp;gpcdma 26&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		/* shares pads with dpaux0 */</div><div class='ctx'> 		dp_aux_ch0_i2c: i2c@31b0000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-i2c";</div><div class='del'>-			reg = &lt;0x031b0000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x031b0000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='hunk'>@@ -336,12 +872,18 @@</div><div class='ctx'> 			clock-names = "div-clk";</div><div class='ctx'> 			resets = &lt;&amp;bpmp TEGRA194_RESET_I2C6&gt;;</div><div class='ctx'> 			reset-names = "i2c";</div><div class='add'>+			pinctrl-0 = &lt;&amp;state_dpaux0_i2c&gt;;</div><div class='add'>+			pinctrl-1 = &lt;&amp;state_dpaux0_off&gt;;</div><div class='add'>+			pinctrl-names = "default", "idle";</div><div class='add'>+			dmas = &lt;&amp;gpcdma 30&gt;, &lt;&amp;gpcdma 30&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		gen7_i2c: i2c@31c0000 {</div><div class='add'>+		/* shares pads with dpaux2 */</div><div class='add'>+		dp_aux_ch2_i2c: i2c@31c0000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-i2c";</div><div class='del'>-			reg = &lt;0x031c0000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x031c0000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='hunk'>@@ -349,12 +891,18 @@</div><div class='ctx'> 			clock-names = "div-clk";</div><div class='ctx'> 			resets = &lt;&amp;bpmp TEGRA194_RESET_I2C7&gt;;</div><div class='ctx'> 			reset-names = "i2c";</div><div class='add'>+			pinctrl-0 = &lt;&amp;state_dpaux2_i2c&gt;;</div><div class='add'>+			pinctrl-1 = &lt;&amp;state_dpaux2_off&gt;;</div><div class='add'>+			pinctrl-names = "default", "idle";</div><div class='add'>+			dmas = &lt;&amp;gpcdma 27&gt;, &lt;&amp;gpcdma 27&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		gen9_i2c: i2c@31e0000 {</div><div class='add'>+		/* shares pads with dpaux3 */</div><div class='add'>+		dp_aux_ch3_i2c: i2c@31e0000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-i2c";</div><div class='del'>-			reg = &lt;0x031e0000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x031e0000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='hunk'>@@ -362,15 +910,32 @@</div><div class='ctx'> 			clock-names = "div-clk";</div><div class='ctx'> 			resets = &lt;&amp;bpmp TEGRA194_RESET_I2C9&gt;;</div><div class='ctx'> 			reset-names = "i2c";</div><div class='add'>+			pinctrl-0 = &lt;&amp;state_dpaux3_i2c&gt;;</div><div class='add'>+			pinctrl-1 = &lt;&amp;state_dpaux3_off&gt;;</div><div class='add'>+			pinctrl-names = "default", "idle";</div><div class='add'>+			dmas = &lt;&amp;gpcdma 31&gt;, &lt;&amp;gpcdma 31&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi@3270000 {</div><div class='add'>+			compatible = "nvidia,tegra194-qspi";</div><div class='add'>+			reg = &lt;0x0 0x3270000 0x0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA194_CLK_QSPI0&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA194_CLK_QSPI0_PM&gt;;</div><div class='add'>+			clock-names = "qspi", "qspi_out";</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA194_RESET_QSPI0&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		pwm1: pwm@3280000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-pwm",</div><div class='ctx'> 				     "nvidia,tegra186-pwm";</div><div class='del'>-			reg = &lt;0x3280000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x3280000 0x0 0x10000&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;bpmp TEGRA194_CLK_PWM1&gt;;</div><div class='del'>-			clock-names = "pwm";</div><div class='ctx'> 			resets = &lt;&amp;bpmp TEGRA194_RESET_PWM1&gt;;</div><div class='ctx'> 			reset-names = "pwm";</div><div class='ctx'> 			status = "disabled";</div><div class='hunk'>@@ -380,9 +945,8 @@</div><div class='ctx'> 		pwm2: pwm@3290000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-pwm",</div><div class='ctx'> 				     "nvidia,tegra186-pwm";</div><div class='del'>-			reg = &lt;0x3290000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x3290000 0x0 0x10000&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;bpmp TEGRA194_CLK_PWM2&gt;;</div><div class='del'>-			clock-names = "pwm";</div><div class='ctx'> 			resets = &lt;&amp;bpmp TEGRA194_RESET_PWM2&gt;;</div><div class='ctx'> 			reset-names = "pwm";</div><div class='ctx'> 			status = "disabled";</div><div class='hunk'>@@ -392,9 +956,8 @@</div><div class='ctx'> 		pwm3: pwm@32a0000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-pwm",</div><div class='ctx'> 				     "nvidia,tegra186-pwm";</div><div class='del'>-			reg = &lt;0x32a0000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x32a0000 0x0 0x10000&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;bpmp TEGRA194_CLK_PWM3&gt;;</div><div class='del'>-			clock-names = "pwm";</div><div class='ctx'> 			resets = &lt;&amp;bpmp TEGRA194_RESET_PWM3&gt;;</div><div class='ctx'> 			reset-names = "pwm";</div><div class='ctx'> 			status = "disabled";</div><div class='hunk'>@@ -404,9 +967,8 @@</div><div class='ctx'> 		pwm5: pwm@32c0000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-pwm",</div><div class='ctx'> 				     "nvidia,tegra186-pwm";</div><div class='del'>-			reg = &lt;0x32c0000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x32c0000 0x0 0x10000&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;bpmp TEGRA194_CLK_PWM5&gt;;</div><div class='del'>-			clock-names = "pwm";</div><div class='ctx'> 			resets = &lt;&amp;bpmp TEGRA194_RESET_PWM5&gt;;</div><div class='ctx'> 			reset-names = "pwm";</div><div class='ctx'> 			status = "disabled";</div><div class='hunk'>@@ -416,9 +978,8 @@</div><div class='ctx'> 		pwm6: pwm@32d0000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-pwm",</div><div class='ctx'> 				     "nvidia,tegra186-pwm";</div><div class='del'>-			reg = &lt;0x32d0000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x32d0000 0x0 0x10000&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;bpmp TEGRA194_CLK_PWM6&gt;;</div><div class='del'>-			clock-names = "pwm";</div><div class='ctx'> 			resets = &lt;&amp;bpmp TEGRA194_RESET_PWM6&gt;;</div><div class='ctx'> 			reset-names = "pwm";</div><div class='ctx'> 			status = "disabled";</div><div class='hunk'>@@ -428,9 +989,8 @@</div><div class='ctx'> 		pwm7: pwm@32e0000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-pwm",</div><div class='ctx'> 				     "nvidia,tegra186-pwm";</div><div class='del'>-			reg = &lt;0x32e0000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x32e0000 0x0 0x10000&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;bpmp TEGRA194_CLK_PWM7&gt;;</div><div class='del'>-			clock-names = "pwm";</div><div class='ctx'> 			resets = &lt;&amp;bpmp TEGRA194_RESET_PWM7&gt;;</div><div class='ctx'> 			reset-names = "pwm";</div><div class='ctx'> 			status = "disabled";</div><div class='hunk'>@@ -440,23 +1000,48 @@</div><div class='ctx'> 		pwm8: pwm@32f0000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-pwm",</div><div class='ctx'> 				     "nvidia,tegra186-pwm";</div><div class='del'>-			reg = &lt;0x32f0000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x32f0000 0x0 0x10000&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;bpmp TEGRA194_CLK_PWM8&gt;;</div><div class='del'>-			clock-names = "pwm";</div><div class='ctx'> 			resets = &lt;&amp;bpmp TEGRA194_RESET_PWM8&gt;;</div><div class='ctx'> 			reset-names = "pwm";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 			#pwm-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		sdmmc1: sdhci@3400000 {</div><div class='del'>-			compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";</div><div class='del'>-			reg = &lt;0x03400000 0x10000&gt;;</div><div class='add'>+		spi@3300000 {</div><div class='add'>+			compatible = "nvidia,tegra194-qspi";</div><div class='add'>+			reg = &lt;0x0 0x3300000 0x0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA194_CLK_QSPI1&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA194_CLK_QSPI1_PM&gt;;</div><div class='add'>+			clock-names = "qspi", "qspi_out";</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA194_RESET_QSPI1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sdmmc1: mmc@3400000 {</div><div class='add'>+			compatible = "nvidia,tegra194-sdhci";</div><div class='add'>+			reg = &lt;0x0 0x03400000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;bpmp TEGRA194_CLK_SDMMC1&gt;;</div><div class='del'>-			clock-names = "sdhci";</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA194_CLK_SDMMC1&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA194_CLK_SDMMC_LEGACY_TM&gt;;</div><div class='add'>+			clock-names = "sdhci", "tmclk";</div><div class='add'>+			assigned-clocks = &lt;&amp;bpmp TEGRA194_CLK_SDMMC1&gt;,</div><div class='add'>+					  &lt;&amp;bpmp TEGRA194_CLK_PLLC4_MUXED&gt;;</div><div class='add'>+			assigned-clock-parents =</div><div class='add'>+					  &lt;&amp;bpmp TEGRA194_CLK_PLLC4_MUXED&gt;,</div><div class='add'>+					  &lt;&amp;bpmp TEGRA194_CLK_PLLC4_VCO_DIV2&gt;;</div><div class='ctx'> 			resets = &lt;&amp;bpmp TEGRA194_RESET_SDMMC1&gt;;</div><div class='ctx'> 			reset-names = "sdhci";</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA194_MEMORY_CLIENT_SDMMCRA &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA194_MEMORY_CLIENT_SDMMCWA &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem", "write";</div><div class='add'>+			iommus = &lt;&amp;smmu TEGRA194_SID_SDMMC1&gt;;</div><div class='add'>+			pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";</div><div class='add'>+			pinctrl-0 = &lt;&amp;sdmmc1_3v3&gt;;</div><div class='add'>+			pinctrl-1 = &lt;&amp;sdmmc1_1v8&gt;;</div><div class='ctx'> 			nvidia,pad-autocal-pull-up-offset-3v3-timeout =</div><div class='ctx'> 									&lt;0x07&gt;;</div><div class='ctx'> 			nvidia,pad-autocal-pull-down-offset-3v3-timeout =</div><div class='hunk'>@@ -468,17 +1053,34 @@</div><div class='ctx'> 			nvidia,pad-autocal-pull-down-offset-sdr104 = &lt;0x00&gt;;</div><div class='ctx'> 			nvidia,default-tap = &lt;0x9&gt;;</div><div class='ctx'> 			nvidia,default-trim = &lt;0x5&gt;;</div><div class='add'>+			sd-uhs-sdr25;</div><div class='add'>+			sd-uhs-sdr50;</div><div class='add'>+			sd-uhs-ddr50;</div><div class='add'>+			sd-uhs-sdr104;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		sdmmc3: sdhci@3440000 {</div><div class='del'>-			compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";</div><div class='del'>-			reg = &lt;0x03440000 0x10000&gt;;</div><div class='add'>+		sdmmc3: mmc@3440000 {</div><div class='add'>+			compatible = "nvidia,tegra194-sdhci";</div><div class='add'>+			reg = &lt;0x0 0x03440000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;bpmp TEGRA194_CLK_SDMMC3&gt;;</div><div class='del'>-			clock-names = "sdhci";</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA194_CLK_SDMMC3&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA194_CLK_SDMMC_LEGACY_TM&gt;;</div><div class='add'>+			clock-names = "sdhci", "tmclk";</div><div class='add'>+			assigned-clocks = &lt;&amp;bpmp TEGRA194_CLK_SDMMC3&gt;,</div><div class='add'>+					  &lt;&amp;bpmp TEGRA194_CLK_PLLC4_MUXED&gt;;</div><div class='add'>+			assigned-clock-parents =</div><div class='add'>+					  &lt;&amp;bpmp TEGRA194_CLK_PLLC4_MUXED&gt;,</div><div class='add'>+					  &lt;&amp;bpmp TEGRA194_CLK_PLLC4_VCO_DIV2&gt;;</div><div class='ctx'> 			resets = &lt;&amp;bpmp TEGRA194_RESET_SDMMC3&gt;;</div><div class='ctx'> 			reset-names = "sdhci";</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA194_MEMORY_CLIENT_SDMMCR &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA194_MEMORY_CLIENT_SDMMCW &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem", "write";</div><div class='add'>+			iommus = &lt;&amp;smmu TEGRA194_SID_SDMMC3&gt;;</div><div class='add'>+			pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";</div><div class='add'>+			pinctrl-0 = &lt;&amp;sdmmc3_3v3&gt;;</div><div class='add'>+			pinctrl-1 = &lt;&amp;sdmmc3_1v8&gt;;</div><div class='ctx'> 			nvidia,pad-autocal-pull-up-offset-1v8 = &lt;0x00&gt;;</div><div class='ctx'> 			nvidia,pad-autocal-pull-down-offset-1v8 = &lt;0x7a&gt;;</div><div class='ctx'> 			nvidia,pad-autocal-pull-up-offset-3v3-timeout = &lt;0x07&gt;;</div><div class='hunk'>@@ -491,21 +1093,30 @@</div><div class='ctx'> 			nvidia,pad-autocal-pull-down-offset-sdr104 = &lt;0x00&gt;;</div><div class='ctx'> 			nvidia,default-tap = &lt;0x9&gt;;</div><div class='ctx'> 			nvidia,default-trim = &lt;0x5&gt;;</div><div class='add'>+			sd-uhs-sdr25;</div><div class='add'>+			sd-uhs-sdr50;</div><div class='add'>+			sd-uhs-ddr50;</div><div class='add'>+			sd-uhs-sdr104;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		sdmmc4: sdhci@3460000 {</div><div class='del'>-			compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";</div><div class='del'>-			reg = &lt;0x03460000 0x10000&gt;;</div><div class='add'>+		sdmmc4: mmc@3460000 {</div><div class='add'>+			compatible = "nvidia,tegra194-sdhci";</div><div class='add'>+			reg = &lt;0x0 0x03460000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;bpmp TEGRA194_CLK_SDMMC4&gt;;</div><div class='del'>-			clock-names = "sdhci";</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA194_CLK_SDMMC4&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA194_CLK_SDMMC_LEGACY_TM&gt;;</div><div class='add'>+			clock-names = "sdhci", "tmclk";</div><div class='ctx'> 			assigned-clocks = &lt;&amp;bpmp TEGRA194_CLK_SDMMC4&gt;,</div><div class='ctx'> 					  &lt;&amp;bpmp TEGRA194_CLK_PLLC4&gt;;</div><div class='ctx'> 			assigned-clock-parents =</div><div class='ctx'> 					  &lt;&amp;bpmp TEGRA194_CLK_PLLC4&gt;;</div><div class='ctx'> 			resets = &lt;&amp;bpmp TEGRA194_RESET_SDMMC4&gt;;</div><div class='ctx'> 			reset-names = "sdhci";</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem", "write";</div><div class='add'>+			iommus = &lt;&amp;smmu TEGRA194_SID_SDMMC4&gt;;</div><div class='ctx'> 			nvidia,pad-autocal-pull-up-offset-hs400 = &lt;0x00&gt;;</div><div class='ctx'> 			nvidia,pad-autocal-pull-down-offset-hs400 = &lt;0x00&gt;;</div><div class='ctx'> 			nvidia,pad-autocal-pull-up-offset-1v8-timeout = &lt;0x0a&gt;;</div><div class='hunk'>@@ -517,31 +1128,40 @@</div><div class='ctx'> 			nvidia,default-tap = &lt;0x8&gt;;</div><div class='ctx'> 			nvidia,default-trim = &lt;0x14&gt;;</div><div class='ctx'> 			nvidia,dqs-trim = &lt;40&gt;;</div><div class='add'>+			cap-mmc-highspeed;</div><div class='add'>+			mmc-ddr-1_8v;</div><div class='add'>+			mmc-hs200-1_8v;</div><div class='add'>+			mmc-hs400-1_8v;</div><div class='add'>+			mmc-hs400-enhanced-strobe;</div><div class='ctx'> 			supports-cqe;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		hda@3510000 {</div><div class='del'>-			compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda";</div><div class='del'>-			reg = &lt;0x3510000 0x10000&gt;;</div><div class='add'>+			compatible = "nvidia,tegra194-hda";</div><div class='add'>+			reg = &lt;0x0 0x3510000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;bpmp TEGRA194_CLK_HDA&gt;,</div><div class='del'>-				 &lt;&amp;bpmp TEGRA194_CLK_HDA2CODEC_2X&gt;,</div><div class='del'>-				 &lt;&amp;bpmp TEGRA194_CLK_HDA2HDMICODEC&gt;;</div><div class='del'>-			clock-names = "hda", "hda2codec_2x", "hda2hdmi";</div><div class='add'>+				 &lt;&amp;bpmp TEGRA194_CLK_HDA2HDMICODEC&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA194_CLK_HDA2CODEC_2X&gt;;</div><div class='add'>+			clock-names = "hda", "hda2hdmi", "hda2codec_2x";</div><div class='ctx'> 			resets = &lt;&amp;bpmp TEGRA194_RESET_HDA&gt;,</div><div class='del'>-				 &lt;&amp;bpmp TEGRA194_RESET_HDA2CODEC_2X&gt;,</div><div class='ctx'> 				 &lt;&amp;bpmp TEGRA194_RESET_HDA2HDMICODEC&gt;;</div><div class='del'>-			reset-names = "hda", "hda2codec_2x", "hda2hdmi";</div><div class='add'>+			reset-names = "hda", "hda2hdmi";</div><div class='ctx'> 			power-domains = &lt;&amp;bpmp TEGRA194_POWER_DOMAIN_DISP&gt;;</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA194_MEMORY_CLIENT_HDAR &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA194_MEMORY_CLIENT_HDAW &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem", "write";</div><div class='add'>+			iommus = &lt;&amp;smmu TEGRA194_SID_HDA&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		xusb_padctl: padctl@3520000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-xusb-padctl";</div><div class='del'>-			reg = &lt;0x03520000 0x1000&gt;,</div><div class='del'>-			      &lt;0x03540000 0x1000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x03520000 0x0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0x03540000 0x0 0x1000&gt;;</div><div class='ctx'> 			reg-names = "padctl", "ao";</div><div class='add'>+			interrupts = &lt;GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> </div><div class='ctx'> 			resets = &lt;&amp;bpmp TEGRA194_RESET_XUSB_PADCTL&gt;;</div><div class='ctx'> 			reset-names = "padctl";</div><div class='hunk'>@@ -644,15 +1264,37 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		usb@3550000 {</div><div class='add'>+			compatible = "nvidia,tegra194-xudc";</div><div class='add'>+			reg = &lt;0x0 0x03550000 0x0 0x8000&gt;,</div><div class='add'>+			      &lt;0x0 0x03558000 0x0 0x1000&gt;;</div><div class='add'>+			reg-names = "base", "fpci";</div><div class='add'>+			interrupts = &lt;GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA194_CLK_XUSB_CORE_DEV&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA194_CLK_XUSB_CORE_SS&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA194_CLK_XUSB_SS&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA194_CLK_XUSB_FS&gt;;</div><div class='add'>+			clock-names = "dev", "ss", "ss_src", "fs_src";</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem", "write";</div><div class='add'>+			iommus = &lt;&amp;smmu TEGRA194_SID_XUSB_DEV&gt;;</div><div class='add'>+			power-domains = &lt;&amp;bpmp TEGRA194_POWER_DOMAIN_XUSBB&gt;,</div><div class='add'>+					&lt;&amp;bpmp TEGRA194_POWER_DOMAIN_XUSBA&gt;;</div><div class='add'>+			power-domain-names = "dev", "ss";</div><div class='add'>+			nvidia,xusb-padctl = &lt;&amp;xusb_padctl&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		usb@3610000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-xusb";</div><div class='del'>-			reg = &lt;0x03610000 0x40000&gt;,</div><div class='del'>-			      &lt;0x03600000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x03610000 0x0 0x40000&gt;,</div><div class='add'>+			      &lt;0x0 0x03600000 0x0 0x10000&gt;;</div><div class='ctx'> 			reg-names = "hcd", "fpci";</div><div class='ctx'> </div><div class='ctx'> 			interrupts = &lt;GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				     &lt;GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-				     &lt;GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				     &lt;GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> </div><div class='ctx'> 			clocks = &lt;&amp;bpmp TEGRA194_CLK_XUSB_CORE_HOST&gt;,</div><div class='ctx'> 				 &lt;&amp;bpmp TEGRA194_CLK_XUSB_FALCON&gt;,</div><div class='hunk'>@@ -667,6 +1309,10 @@</div><div class='ctx'> 				      "xusb_ss", "xusb_ss_src", "xusb_hs_src",</div><div class='ctx'> 				      "xusb_fs_src", "pll_u_480m", "clk_m",</div><div class='ctx'> 				      "pll_e";</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem", "write";</div><div class='add'>+			iommus = &lt;&amp;smmu TEGRA194_SID_XUSB_HOST&gt;;</div><div class='ctx'> </div><div class='ctx'> 			power-domains = &lt;&amp;bpmp TEGRA194_POWER_DOMAIN_XUSBC&gt;,</div><div class='ctx'> 					&lt;&amp;bpmp TEGRA194_POWER_DOMAIN_XUSBA&gt;;</div><div class='hunk'>@@ -678,36 +1324,47 @@</div><div class='ctx'> </div><div class='ctx'> 		fuse@3820000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-efuse";</div><div class='del'>-			reg = &lt;0x03820000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x03820000 0x0 0x10000&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;bpmp TEGRA194_CLK_FUSE&gt;;</div><div class='ctx'> 			clock-names = "fuse";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		gic: interrupt-controller@3881000 {</div><div class='ctx'> 			compatible = "arm,gic-400";</div><div class='add'>+			#address-cells = &lt;0&gt;;</div><div class='ctx'> 			#interrupt-cells = &lt;3&gt;;</div><div class='ctx'> 			interrupt-controller;</div><div class='del'>-			reg = &lt;0x03881000 0x1000&gt;,</div><div class='del'>-			      &lt;0x03882000 0x2000&gt;,</div><div class='del'>-			      &lt;0x03884000 0x2000&gt;,</div><div class='del'>-			      &lt;0x03886000 0x2000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x03881000 0x0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0x03882000 0x0 0x2000&gt;,</div><div class='add'>+			      &lt;0x0 0x03884000 0x0 0x2000&gt;,</div><div class='add'>+			      &lt;0x0 0x03886000 0x0 0x2000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_PPI 9</div><div class='ctx'> 				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='ctx'> 			interrupt-parent = &lt;&amp;gic&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		cec@3960000 {</div><div class='del'>-			compatible = "nvidia,tegra194-cec";</div><div class='del'>-			reg = &lt;0x03960000 0x10000&gt;;</div><div class='add'>+			compatible = "nvidia,tegra194-cec", "nvidia,tegra210-cec";</div><div class='add'>+			reg = &lt;0x0 0x03960000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;bpmp TEGRA194_CLK_CEC&gt;;</div><div class='ctx'> 			clock-names = "cec";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		hte_lic: hardware-timestamp@3aa0000 {</div><div class='add'>+			compatible = "nvidia,tegra194-gte-lic";</div><div class='add'>+			reg = &lt;0x0 0x3aa0000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			nvidia,int-threshold = &lt;1&gt;;</div><div class='add'>+			nvidia,slices = &lt;11&gt;;</div><div class='add'>+			#timestamp-cells = &lt;1&gt;;</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		hsp_top0: hsp@3c00000 {</div><div class='del'>-			compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";</div><div class='del'>-			reg = &lt;0x03c00000 0xa0000&gt;;</div><div class='add'>+			compatible = "nvidia,tegra194-hsp";</div><div class='add'>+			reg = &lt;0x0 0x03c00000 0x0 0xa0000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 			             &lt;GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 			             &lt;GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='hunk'>@@ -725,7 +1382,7 @@</div><div class='ctx'> </div><div class='ctx'> 		p2u_hsio_0: phy@3e10000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-p2u";</div><div class='del'>-			reg = &lt;0x03e10000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x03e10000 0x0 0x10000&gt;;</div><div class='ctx'> 			reg-names = "ctl";</div><div class='ctx'> </div><div class='ctx'> 			#phy-cells = &lt;0&gt;;</div><div class='hunk'>@@ -733,7 +1390,7 @@</div><div class='ctx'> </div><div class='ctx'> 		p2u_hsio_1: phy@3e20000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-p2u";</div><div class='del'>-			reg = &lt;0x03e20000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x03e20000 0x0 0x10000&gt;;</div><div class='ctx'> 			reg-names = "ctl";</div><div class='ctx'> </div><div class='ctx'> 			#phy-cells = &lt;0&gt;;</div><div class='hunk'>@@ -741,7 +1398,7 @@</div><div class='ctx'> </div><div class='ctx'> 		p2u_hsio_2: phy@3e30000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-p2u";</div><div class='del'>-			reg = &lt;0x03e30000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x03e30000 0x0 0x10000&gt;;</div><div class='ctx'> 			reg-names = "ctl";</div><div class='ctx'> </div><div class='ctx'> 			#phy-cells = &lt;0&gt;;</div><div class='hunk'>@@ -749,7 +1406,7 @@</div><div class='ctx'> </div><div class='ctx'> 		p2u_hsio_3: phy@3e40000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-p2u";</div><div class='del'>-			reg = &lt;0x03e40000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x03e40000 0x0 0x10000&gt;;</div><div class='ctx'> 			reg-names = "ctl";</div><div class='ctx'> </div><div class='ctx'> 			#phy-cells = &lt;0&gt;;</div><div class='hunk'>@@ -757,7 +1414,7 @@</div><div class='ctx'> </div><div class='ctx'> 		p2u_hsio_4: phy@3e50000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-p2u";</div><div class='del'>-			reg = &lt;0x03e50000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x03e50000 0x0 0x10000&gt;;</div><div class='ctx'> 			reg-names = "ctl";</div><div class='ctx'> </div><div class='ctx'> 			#phy-cells = &lt;0&gt;;</div><div class='hunk'>@@ -765,7 +1422,7 @@</div><div class='ctx'> </div><div class='ctx'> 		p2u_hsio_5: phy@3e60000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-p2u";</div><div class='del'>-			reg = &lt;0x03e60000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x03e60000 0x0 0x10000&gt;;</div><div class='ctx'> 			reg-names = "ctl";</div><div class='ctx'> </div><div class='ctx'> 			#phy-cells = &lt;0&gt;;</div><div class='hunk'>@@ -773,7 +1430,7 @@</div><div class='ctx'> </div><div class='ctx'> 		p2u_hsio_6: phy@3e70000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-p2u";</div><div class='del'>-			reg = &lt;0x03e70000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x03e70000 0x0 0x10000&gt;;</div><div class='ctx'> 			reg-names = "ctl";</div><div class='ctx'> </div><div class='ctx'> 			#phy-cells = &lt;0&gt;;</div><div class='hunk'>@@ -781,7 +1438,7 @@</div><div class='ctx'> </div><div class='ctx'> 		p2u_hsio_7: phy@3e80000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-p2u";</div><div class='del'>-			reg = &lt;0x03e80000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x03e80000 0x0 0x10000&gt;;</div><div class='ctx'> 			reg-names = "ctl";</div><div class='ctx'> </div><div class='ctx'> 			#phy-cells = &lt;0&gt;;</div><div class='hunk'>@@ -789,7 +1446,7 @@</div><div class='ctx'> </div><div class='ctx'> 		p2u_hsio_8: phy@3e90000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-p2u";</div><div class='del'>-			reg = &lt;0x03e90000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x03e90000 0x0 0x10000&gt;;</div><div class='ctx'> 			reg-names = "ctl";</div><div class='ctx'> </div><div class='ctx'> 			#phy-cells = &lt;0&gt;;</div><div class='hunk'>@@ -797,7 +1454,7 @@</div><div class='ctx'> </div><div class='ctx'> 		p2u_hsio_9: phy@3ea0000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-p2u";</div><div class='del'>-			reg = &lt;0x03ea0000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x03ea0000 0x0 0x10000&gt;;</div><div class='ctx'> 			reg-names = "ctl";</div><div class='ctx'> </div><div class='ctx'> 			#phy-cells = &lt;0&gt;;</div><div class='hunk'>@@ -805,7 +1462,7 @@</div><div class='ctx'> </div><div class='ctx'> 		p2u_nvhs_0: phy@3eb0000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-p2u";</div><div class='del'>-			reg = &lt;0x03eb0000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x03eb0000 0x0 0x10000&gt;;</div><div class='ctx'> 			reg-names = "ctl";</div><div class='ctx'> </div><div class='ctx'> 			#phy-cells = &lt;0&gt;;</div><div class='hunk'>@@ -813,7 +1470,7 @@</div><div class='ctx'> </div><div class='ctx'> 		p2u_nvhs_1: phy@3ec0000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-p2u";</div><div class='del'>-			reg = &lt;0x03ec0000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x03ec0000 0x0 0x10000&gt;;</div><div class='ctx'> 			reg-names = "ctl";</div><div class='ctx'> </div><div class='ctx'> 			#phy-cells = &lt;0&gt;;</div><div class='hunk'>@@ -821,7 +1478,7 @@</div><div class='ctx'> </div><div class='ctx'> 		p2u_nvhs_2: phy@3ed0000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-p2u";</div><div class='del'>-			reg = &lt;0x03ed0000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x03ed0000 0x0 0x10000&gt;;</div><div class='ctx'> 			reg-names = "ctl";</div><div class='ctx'> </div><div class='ctx'> 			#phy-cells = &lt;0&gt;;</div><div class='hunk'>@@ -829,7 +1486,7 @@</div><div class='ctx'> </div><div class='ctx'> 		p2u_nvhs_3: phy@3ee0000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-p2u";</div><div class='del'>-			reg = &lt;0x03ee0000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x03ee0000 0x0 0x10000&gt;;</div><div class='ctx'> 			reg-names = "ctl";</div><div class='ctx'> </div><div class='ctx'> 			#phy-cells = &lt;0&gt;;</div><div class='hunk'>@@ -837,7 +1494,7 @@</div><div class='ctx'> </div><div class='ctx'> 		p2u_nvhs_4: phy@3ef0000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-p2u";</div><div class='del'>-			reg = &lt;0x03ef0000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x03ef0000 0x0 0x10000&gt;;</div><div class='ctx'> 			reg-names = "ctl";</div><div class='ctx'> </div><div class='ctx'> 			#phy-cells = &lt;0&gt;;</div><div class='hunk'>@@ -845,7 +1502,7 @@</div><div class='ctx'> </div><div class='ctx'> 		p2u_nvhs_5: phy@3f00000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-p2u";</div><div class='del'>-			reg = &lt;0x03f00000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x03f00000 0x0 0x10000&gt;;</div><div class='ctx'> 			reg-names = "ctl";</div><div class='ctx'> </div><div class='ctx'> 			#phy-cells = &lt;0&gt;;</div><div class='hunk'>@@ -853,7 +1510,7 @@</div><div class='ctx'> </div><div class='ctx'> 		p2u_nvhs_6: phy@3f10000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-p2u";</div><div class='del'>-			reg = &lt;0x03f10000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x03f10000 0x0 0x10000&gt;;</div><div class='ctx'> 			reg-names = "ctl";</div><div class='ctx'> </div><div class='ctx'> 			#phy-cells = &lt;0&gt;;</div><div class='hunk'>@@ -861,7 +1518,7 @@</div><div class='ctx'> </div><div class='ctx'> 		p2u_nvhs_7: phy@3f20000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-p2u";</div><div class='del'>-			reg = &lt;0x03f20000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x03f20000 0x0 0x10000&gt;;</div><div class='ctx'> 			reg-names = "ctl";</div><div class='ctx'> </div><div class='ctx'> 			#phy-cells = &lt;0&gt;;</div><div class='hunk'>@@ -869,7 +1526,7 @@</div><div class='ctx'> </div><div class='ctx'> 		p2u_hsio_10: phy@3f30000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-p2u";</div><div class='del'>-			reg = &lt;0x03f30000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x03f30000 0x0 0x10000&gt;;</div><div class='ctx'> 			reg-names = "ctl";</div><div class='ctx'> </div><div class='ctx'> 			#phy-cells = &lt;0&gt;;</div><div class='hunk'>@@ -877,15 +1534,35 @@</div><div class='ctx'> </div><div class='ctx'> 		p2u_hsio_11: phy@3f40000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-p2u";</div><div class='del'>-			reg = &lt;0x03f40000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x03f40000 0x0 0x10000&gt;;</div><div class='ctx'> 			reg-names = "ctl";</div><div class='ctx'> </div><div class='ctx'> 			#phy-cells = &lt;0&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		sce-noc@b600000 {</div><div class='add'>+			compatible = "nvidia,tegra194-sce-noc";</div><div class='add'>+			reg = &lt;0x0 0xb600000 0x0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			nvidia,axi2apb = &lt;&amp;axi2apb&gt;;</div><div class='add'>+			nvidia,apbmisc = &lt;&amp;apbmisc&gt;;</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rce-noc@be00000 {</div><div class='add'>+			compatible = "nvidia,tegra194-rce-noc";</div><div class='add'>+			reg = &lt;0x0 0xbe00000 0x0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			nvidia,axi2apb = &lt;&amp;axi2apb&gt;;</div><div class='add'>+			nvidia,apbmisc = &lt;&amp;apbmisc&gt;;</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		hsp_aon: hsp@c150000 {</div><div class='del'>-			compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";</div><div class='del'>-			reg = &lt;0x0c150000 0xa0000&gt;;</div><div class='add'>+			compatible = "nvidia,tegra194-hsp";</div><div class='add'>+			reg = &lt;0x0 0x0c150000 0x0 0x90000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 			             &lt;GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 			             &lt;GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='hunk'>@@ -898,9 +1575,19 @@</div><div class='ctx'> 			#mbox-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		hte_aon: hardware-timestamp@c1e0000 {</div><div class='add'>+			compatible = "nvidia,tegra194-gte-aon";</div><div class='add'>+			reg = &lt;0x0 0xc1e0000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			nvidia,int-threshold = &lt;1&gt;;</div><div class='add'>+			nvidia,slices = &lt;3&gt;;</div><div class='add'>+			#timestamp-cells = &lt;1&gt;;</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		gen2_i2c: i2c@c240000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-i2c";</div><div class='del'>-			reg = &lt;0x0c240000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x0c240000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='hunk'>@@ -908,12 +1595,14 @@</div><div class='ctx'> 			clock-names = "div-clk";</div><div class='ctx'> 			resets = &lt;&amp;bpmp TEGRA194_RESET_I2C2&gt;;</div><div class='ctx'> 			reset-names = "i2c";</div><div class='add'>+			dmas = &lt;&amp;gpcdma 22&gt;, &lt;&amp;gpcdma 22&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		gen8_i2c: i2c@c250000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-i2c";</div><div class='del'>-			reg = &lt;0x0c250000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x0c250000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='hunk'>@@ -921,36 +1610,38 @@</div><div class='ctx'> 			clock-names = "div-clk";</div><div class='ctx'> 			resets = &lt;&amp;bpmp TEGRA194_RESET_I2C8&gt;;</div><div class='ctx'> 			reset-names = "i2c";</div><div class='add'>+			dmas = &lt;&amp;gpcdma 0&gt;, &lt;&amp;gpcdma 0&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		uartc: serial@c280000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";</div><div class='del'>-			reg = &lt;0x0c280000 0x40&gt;;</div><div class='add'>+			reg = &lt;0x0 0x0c280000 0x0 0x40&gt;;</div><div class='ctx'> 			reg-shift = &lt;2&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;bpmp TEGRA194_CLK_UARTC&gt;;</div><div class='del'>-			clock-names = "serial";</div><div class='ctx'> 			resets = &lt;&amp;bpmp TEGRA194_RESET_UARTC&gt;;</div><div class='del'>-			reset-names = "serial";</div><div class='add'>+			dmas = &lt;&amp;gpcdma 3&gt;, &lt;&amp;gpcdma 3&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		uartg: serial@c290000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";</div><div class='del'>-			reg = &lt;0x0c290000 0x40&gt;;</div><div class='add'>+			reg = &lt;0x0 0x0c290000 0x0 0x40&gt;;</div><div class='ctx'> 			reg-shift = &lt;2&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;bpmp TEGRA194_CLK_UARTG&gt;;</div><div class='del'>-			clock-names = "serial";</div><div class='ctx'> 			resets = &lt;&amp;bpmp TEGRA194_RESET_UARTG&gt;;</div><div class='del'>-			reset-names = "serial";</div><div class='add'>+			dmas = &lt;&amp;gpcdma 2&gt;, &lt;&amp;gpcdma 2&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		rtc: rtc@c2a0000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc";</div><div class='del'>-			reg = &lt;0x0c2a0000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x0c2a0000 0x0 0x10000&gt;;</div><div class='ctx'> 			interrupt-parent = &lt;&amp;pmc&gt;;</div><div class='ctx'> 			interrupts = &lt;73 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;bpmp TEGRA194_CLK_CLK_32K&gt;;</div><div class='hunk'>@@ -961,8 +1652,8 @@</div><div class='ctx'> 		gpio_aon: gpio@c2f0000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-gpio-aon";</div><div class='ctx'> 			reg-names = "security", "gpio";</div><div class='del'>-			reg = &lt;0xc2f0000 0x1000&gt;,</div><div class='del'>-			      &lt;0xc2f1000 0x1000&gt;;</div><div class='add'>+			reg = &lt;0x0 0xc2f0000 0x0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0xc2f1000 0x0 0x1000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 				     &lt;GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 				     &lt;GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='hunk'>@@ -971,14 +1662,21 @@</div><div class='ctx'> 			#gpio-cells = &lt;2&gt;;</div><div class='ctx'> 			interrupt-controller;</div><div class='ctx'> 			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;pinmux_aon 0 0 30&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinmux_aon: pinmux@c300000 {</div><div class='add'>+			compatible = "nvidia,tegra194-pinmux-aon";</div><div class='add'>+			reg = &lt;0x0 0xc300000 0x0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+			status = "okay";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		pwm4: pwm@c340000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-pwm",</div><div class='ctx'> 				     "nvidia,tegra186-pwm";</div><div class='del'>-			reg = &lt;0xc340000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0xc340000 0x0 0x10000&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;bpmp TEGRA194_CLK_PWM4&gt;;</div><div class='del'>-			clock-names = "pwm";</div><div class='ctx'> 			resets = &lt;&amp;bpmp TEGRA194_RESET_PWM4&gt;;</div><div class='ctx'> 			reset-names = "pwm";</div><div class='ctx'> 			status = "disabled";</div><div class='hunk'>@@ -987,37 +1685,264 @@</div><div class='ctx'> </div><div class='ctx'> 		pmc: pmc@c360000 {</div><div class='ctx'> 			compatible = "nvidia,tegra194-pmc";</div><div class='del'>-			reg = &lt;0x0c360000 0x10000&gt;,</div><div class='del'>-			      &lt;0x0c370000 0x10000&gt;,</div><div class='del'>-			      &lt;0x0c380000 0x10000&gt;,</div><div class='del'>-			      &lt;0x0c390000 0x10000&gt;,</div><div class='del'>-			      &lt;0x0c3a0000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x0c360000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0x0c370000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0x0c380000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0x0c390000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0x0c3a0000 0x0 0x10000&gt;;</div><div class='ctx'> 			reg-names = "pmc", "wake", "aotag", "scratch", "misc";</div><div class='ctx'> </div><div class='ctx'> 			#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 			interrupt-controller;</div><div class='add'>+</div><div class='add'>+			sdmmc1_1v8: sdmmc1-1v8 {</div><div class='add'>+				pins = "sdmmc1-hv";</div><div class='add'>+				power-source = &lt;TEGRA_IO_PAD_VOLTAGE_1V8&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sdmmc1_3v3: sdmmc1-3v3 {</div><div class='add'>+				pins = "sdmmc1-hv";</div><div class='add'>+				power-source = &lt;TEGRA_IO_PAD_VOLTAGE_3V3&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sdmmc3_1v8: sdmmc3-1v8 {</div><div class='add'>+				pins = "sdmmc3-hv";</div><div class='add'>+				power-source = &lt;TEGRA_IO_PAD_VOLTAGE_1V8&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sdmmc3_3v3: sdmmc3-3v3 {</div><div class='add'>+				pins = "sdmmc3-hv";</div><div class='add'>+				power-source = &lt;TEGRA_IO_PAD_VOLTAGE_3V3&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aon-noc@c600000 {</div><div class='add'>+			compatible = "nvidia,tegra194-aon-noc";</div><div class='add'>+			reg = &lt;0x0 0xc600000 0x0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			nvidia,apbmisc = &lt;&amp;apbmisc&gt;;</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		bpmp-noc@d600000 {</div><div class='add'>+			compatible = "nvidia,tegra194-bpmp-noc";</div><div class='add'>+			reg = &lt;0x0 0xd600000 0x0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			nvidia,axi2apb = &lt;&amp;axi2apb&gt;;</div><div class='add'>+			nvidia,apbmisc = &lt;&amp;apbmisc&gt;;</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		iommu@10000000 {</div><div class='add'>+			compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500";</div><div class='add'>+			reg = &lt;0x0 0x10000000 0x0 0x800000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			stream-match-mask = &lt;0x7f80&gt;;</div><div class='add'>+			#global-interrupts = &lt;1&gt;;</div><div class='add'>+			#iommu-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			nvidia,memory-controller = &lt;&amp;mc&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smmu: iommu@12000000 {</div><div class='add'>+			compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500";</div><div class='add'>+			reg = &lt;0x0 0x12000000 0x0 0x800000&gt;,</div><div class='add'>+			      &lt;0x0 0x11000000 0x0 0x800000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			stream-match-mask = &lt;0x7f80&gt;;</div><div class='add'>+			#global-interrupts = &lt;2&gt;;</div><div class='add'>+			#iommu-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			nvidia,memory-controller = &lt;&amp;mc&gt;;</div><div class='add'>+			status = "okay";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		host1x@13e00000 {</div><div class='del'>-			compatible = "nvidia,tegra194-host1x", "simple-bus";</div><div class='del'>-			reg = &lt;0x13e00000 0x10000&gt;,</div><div class='del'>-			      &lt;0x13e10000 0x10000&gt;;</div><div class='add'>+			compatible = "nvidia,tegra194-host1x";</div><div class='add'>+			reg = &lt;0x0 0x13e00000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0x13e10000 0x0 0x10000&gt;;</div><div class='ctx'> 			reg-names = "hypervisor", "vm";</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 				     &lt;GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "syncpt", "host1x";</div><div class='ctx'> 			clocks = &lt;&amp;bpmp TEGRA194_CLK_HOST1X&gt;;</div><div class='ctx'> 			clock-names = "host1x";</div><div class='ctx'> 			resets = &lt;&amp;bpmp TEGRA194_RESET_HOST1X&gt;;</div><div class='ctx'> 			reset-names = "host1x";</div><div class='ctx'> </div><div class='del'>-			#address-cells = &lt;1&gt;;</div><div class='del'>-			#size-cells = &lt;1&gt;;</div><div class='del'>-</div><div class='del'>-			ranges = &lt;0x15000000 0x15000000 0x01000000&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges = &lt;0x0 0x14800000 0x0 0x14800000 0x0 0x02800000&gt;;</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem";</div><div class='add'>+			iommus = &lt;&amp;smmu TEGRA194_SID_HOST1X&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+</div><div class='add'>+			/* Context isolation domains */</div><div class='add'>+			iommu-map = &lt;0 &amp;smmu TEGRA194_SID_HOST1X_CTX0 1&gt;,</div><div class='add'>+				    &lt;1 &amp;smmu TEGRA194_SID_HOST1X_CTX1 1&gt;,</div><div class='add'>+				    &lt;2 &amp;smmu TEGRA194_SID_HOST1X_CTX2 1&gt;,</div><div class='add'>+				    &lt;3 &amp;smmu TEGRA194_SID_HOST1X_CTX3 1&gt;,</div><div class='add'>+				    &lt;4 &amp;smmu TEGRA194_SID_HOST1X_CTX4 1&gt;,</div><div class='add'>+				    &lt;5 &amp;smmu TEGRA194_SID_HOST1X_CTX5 1&gt;,</div><div class='add'>+				    &lt;6 &amp;smmu TEGRA194_SID_HOST1X_CTX6 1&gt;,</div><div class='add'>+				    &lt;7 &amp;smmu TEGRA194_SID_HOST1X_CTX7 1&gt;;</div><div class='add'>+</div><div class='add'>+			nvdec@15140000 {</div><div class='add'>+				compatible = "nvidia,tegra194-nvdec";</div><div class='add'>+				reg = &lt;0x0 0x15140000 0x0 0x00040000&gt;;</div><div class='add'>+				clocks = &lt;&amp;bpmp TEGRA194_CLK_NVDEC1&gt;;</div><div class='add'>+				clock-names = "nvdec";</div><div class='add'>+				resets = &lt;&amp;bpmp TEGRA194_RESET_NVDEC1&gt;;</div><div class='add'>+				reset-names = "nvdec";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;bpmp TEGRA194_POWER_DOMAIN_NVDECB&gt;;</div><div class='add'>+				interconnects = &lt;&amp;mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &amp;emc&gt;,</div><div class='add'>+						&lt;&amp;mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &amp;emc&gt;,</div><div class='add'>+						&lt;&amp;mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &amp;emc&gt;;</div><div class='add'>+				interconnect-names = "dma-mem", "read-1", "write";</div><div class='add'>+				iommus = &lt;&amp;smmu TEGRA194_SID_NVDEC1&gt;;</div><div class='add'>+				dma-coherent;</div><div class='add'>+</div><div class='add'>+				nvidia,host1x-class = &lt;0xf5&gt;;</div><div class='add'>+			};</div><div class='ctx'> </div><div class='ctx'> 			display-hub@15200000 {</div><div class='del'>-				compatible = "nvidia,tegra194-display", "simple-bus";</div><div class='del'>-				reg = &lt;0x15200000 0x00040000&gt;;</div><div class='add'>+				compatible = "nvidia,tegra194-display";</div><div class='add'>+				reg = &lt;0x0 0x15200000 0x0 0x00040000&gt;;</div><div class='ctx'> 				resets = &lt;&amp;bpmp TEGRA194_RESET_NVDISPLAY0_MISC&gt;,</div><div class='ctx'> 					 &lt;&amp;bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0&gt;,</div><div class='ctx'> 					 &lt;&amp;bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1&gt;,</div><div class='hunk'>@@ -1034,14 +1959,13 @@</div><div class='ctx'> </div><div class='ctx'> 				power-domains = &lt;&amp;bpmp TEGRA194_POWER_DOMAIN_DISP&gt;;</div><div class='ctx'> </div><div class='del'>-				#address-cells = &lt;1&gt;;</div><div class='del'>-				#size-cells = &lt;1&gt;;</div><div class='del'>-</div><div class='del'>-				ranges = &lt;0x15200000 0x15200000 0x40000&gt;;</div><div class='add'>+				#address-cells = &lt;2&gt;;</div><div class='add'>+				#size-cells = &lt;2&gt;;</div><div class='add'>+				ranges = &lt;0x0 0x15200000 0x0 0x15200000 0x0 0x40000&gt;;</div><div class='ctx'> </div><div class='ctx'> 				display@15200000 {</div><div class='ctx'> 					compatible = "nvidia,tegra194-dc";</div><div class='del'>-					reg = &lt;0x15200000 0x10000&gt;;</div><div class='add'>+					reg = &lt;0x0 0x15200000 0x0 0x10000&gt;;</div><div class='ctx'> 					interrupts = &lt;GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 					clocks = &lt;&amp;bpmp TEGRA194_CLK_NVDISPLAY_P0&gt;;</div><div class='ctx'> 					clock-names = "dc";</div><div class='hunk'>@@ -1049,6 +1973,9 @@</div><div class='ctx'> 					reset-names = "dc";</div><div class='ctx'> </div><div class='ctx'> 					power-domains = &lt;&amp;bpmp TEGRA194_POWER_DOMAIN_DISP&gt;;</div><div class='add'>+					interconnects = &lt;&amp;mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &amp;emc&gt;,</div><div class='add'>+							&lt;&amp;mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &amp;emc&gt;;</div><div class='add'>+					interconnect-names = "dma-mem", "read-1";</div><div class='ctx'> </div><div class='ctx'> 					nvidia,outputs = &lt;&amp;sor0 &amp;sor1 &amp;sor2 &amp;sor3&gt;;</div><div class='ctx'> 					nvidia,head = &lt;0&gt;;</div><div class='hunk'>@@ -1056,7 +1983,7 @@</div><div class='ctx'> </div><div class='ctx'> 				display@15210000 {</div><div class='ctx'> 					compatible = "nvidia,tegra194-dc";</div><div class='del'>-					reg = &lt;0x15210000 0x10000&gt;;</div><div class='add'>+					reg = &lt;0x0 0x15210000 0x0 0x10000&gt;;</div><div class='ctx'> 					interrupts = &lt;GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 					clocks = &lt;&amp;bpmp TEGRA194_CLK_NVDISPLAY_P1&gt;;</div><div class='ctx'> 					clock-names = "dc";</div><div class='hunk'>@@ -1064,6 +1991,9 @@</div><div class='ctx'> 					reset-names = "dc";</div><div class='ctx'> </div><div class='ctx'> 					power-domains = &lt;&amp;bpmp TEGRA194_POWER_DOMAIN_DISPB&gt;;</div><div class='add'>+					interconnects = &lt;&amp;mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &amp;emc&gt;,</div><div class='add'>+							&lt;&amp;mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &amp;emc&gt;;</div><div class='add'>+					interconnect-names = "dma-mem", "read-1";</div><div class='ctx'> </div><div class='ctx'> 					nvidia,outputs = &lt;&amp;sor0 &amp;sor1 &amp;sor2 &amp;sor3&gt;;</div><div class='ctx'> 					nvidia,head = &lt;1&gt;;</div><div class='hunk'>@@ -1071,7 +2001,7 @@</div><div class='ctx'> </div><div class='ctx'> 				display@15220000 {</div><div class='ctx'> 					compatible = "nvidia,tegra194-dc";</div><div class='del'>-					reg = &lt;0x15220000 0x10000&gt;;</div><div class='add'>+					reg = &lt;0x0 0x15220000 0x0 0x10000&gt;;</div><div class='ctx'> 					interrupts = &lt;GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 					clocks = &lt;&amp;bpmp TEGRA194_CLK_NVDISPLAY_P2&gt;;</div><div class='ctx'> 					clock-names = "dc";</div><div class='hunk'>@@ -1079,6 +2009,9 @@</div><div class='ctx'> 					reset-names = "dc";</div><div class='ctx'> </div><div class='ctx'> 					power-domains = &lt;&amp;bpmp TEGRA194_POWER_DOMAIN_DISPC&gt;;</div><div class='add'>+					interconnects = &lt;&amp;mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &amp;emc&gt;,</div><div class='add'>+							&lt;&amp;mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &amp;emc&gt;;</div><div class='add'>+					interconnect-names = "dma-mem", "read-1";</div><div class='ctx'> </div><div class='ctx'> 					nvidia,outputs = &lt;&amp;sor0 &amp;sor1 &amp;sor2 &amp;sor3&gt;;</div><div class='ctx'> 					nvidia,head = &lt;2&gt;;</div><div class='hunk'>@@ -1086,7 +2019,7 @@</div><div class='ctx'> </div><div class='ctx'> 				display@15230000 {</div><div class='ctx'> 					compatible = "nvidia,tegra194-dc";</div><div class='del'>-					reg = &lt;0x15230000 0x10000&gt;;</div><div class='add'>+					reg = &lt;0x0 0x15230000 0x0 0x10000&gt;;</div><div class='ctx'> 					interrupts = &lt;GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 					clocks = &lt;&amp;bpmp TEGRA194_CLK_NVDISPLAY_P3&gt;;</div><div class='ctx'> 					clock-names = "dc";</div><div class='hunk'>@@ -1094,6 +2027,9 @@</div><div class='ctx'> 					reset-names = "dc";</div><div class='ctx'> </div><div class='ctx'> 					power-domains = &lt;&amp;bpmp TEGRA194_POWER_DOMAIN_DISPC&gt;;</div><div class='add'>+					interconnects = &lt;&amp;mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &amp;emc&gt;,</div><div class='add'>+							&lt;&amp;mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &amp;emc&gt;;</div><div class='add'>+					interconnect-names = "dma-mem", "read-1";</div><div class='ctx'> </div><div class='ctx'> 					nvidia,outputs = &lt;&amp;sor0 &amp;sor1 &amp;sor2 &amp;sor3&gt;;</div><div class='ctx'> 					nvidia,head = &lt;3&gt;;</div><div class='hunk'>@@ -1102,7 +2038,7 @@</div><div class='ctx'> </div><div class='ctx'> 			vic@15340000 {</div><div class='ctx'> 				compatible = "nvidia,tegra194-vic";</div><div class='del'>-				reg = &lt;0x15340000 0x00040000&gt;;</div><div class='add'>+				reg = &lt;0x0 0x15340000 0x0 0x00040000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;bpmp TEGRA194_CLK_VIC&gt;;</div><div class='ctx'> 				clock-names = "vic";</div><div class='hunk'>@@ -1110,11 +2046,70 @@</div><div class='ctx'> 				reset-names = "vic";</div><div class='ctx'> </div><div class='ctx'> 				power-domains = &lt;&amp;bpmp TEGRA194_POWER_DOMAIN_VIC&gt;;</div><div class='add'>+				interconnects = &lt;&amp;mc TEGRA194_MEMORY_CLIENT_VICSRD &amp;emc&gt;,</div><div class='add'>+						&lt;&amp;mc TEGRA194_MEMORY_CLIENT_VICSWR &amp;emc&gt;;</div><div class='add'>+				interconnect-names = "dma-mem", "write";</div><div class='add'>+				iommus = &lt;&amp;smmu TEGRA194_SID_VIC&gt;;</div><div class='add'>+				dma-coherent;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			nvjpg@15380000 {</div><div class='add'>+				compatible = "nvidia,tegra194-nvjpg";</div><div class='add'>+				reg = &lt;0x0 0x15380000 0x0 0x40000&gt;;</div><div class='add'>+				clocks = &lt;&amp;bpmp TEGRA194_CLK_NVJPG&gt;;</div><div class='add'>+				clock-names = "nvjpg";</div><div class='add'>+				resets = &lt;&amp;bpmp TEGRA194_RESET_NVJPG&gt;;</div><div class='add'>+				reset-names = "nvjpg";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;bpmp TEGRA194_POWER_DOMAIN_NVJPG&gt;;</div><div class='add'>+				interconnects = &lt;&amp;mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &amp;emc&gt;,</div><div class='add'>+						&lt;&amp;mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &amp;emc&gt;;</div><div class='add'>+				interconnect-names = "dma-mem", "write";</div><div class='add'>+				iommus = &lt;&amp;smmu TEGRA194_SID_NVJPG&gt;;</div><div class='add'>+				dma-coherent;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			nvdec@15480000 {</div><div class='add'>+				compatible = "nvidia,tegra194-nvdec";</div><div class='add'>+				reg = &lt;0x0 0x15480000 0x0 0x00040000&gt;;</div><div class='add'>+				clocks = &lt;&amp;bpmp TEGRA194_CLK_NVDEC&gt;;</div><div class='add'>+				clock-names = "nvdec";</div><div class='add'>+				resets = &lt;&amp;bpmp TEGRA194_RESET_NVDEC&gt;;</div><div class='add'>+				reset-names = "nvdec";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;bpmp TEGRA194_POWER_DOMAIN_NVDECA&gt;;</div><div class='add'>+				interconnects = &lt;&amp;mc TEGRA194_MEMORY_CLIENT_NVDECSRD &amp;emc&gt;,</div><div class='add'>+						&lt;&amp;mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &amp;emc&gt;,</div><div class='add'>+						&lt;&amp;mc TEGRA194_MEMORY_CLIENT_NVDECSWR &amp;emc&gt;;</div><div class='add'>+				interconnect-names = "dma-mem", "read-1", "write";</div><div class='add'>+				iommus = &lt;&amp;smmu TEGRA194_SID_NVDEC&gt;;</div><div class='add'>+				dma-coherent;</div><div class='add'>+</div><div class='add'>+				nvidia,host1x-class = &lt;0xf0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			nvenc@154c0000 {</div><div class='add'>+				compatible = "nvidia,tegra194-nvenc";</div><div class='add'>+				reg = &lt;0x0 0x154c0000 0x0 0x40000&gt;;</div><div class='add'>+				clocks = &lt;&amp;bpmp TEGRA194_CLK_NVENC&gt;;</div><div class='add'>+				clock-names = "nvenc";</div><div class='add'>+				resets = &lt;&amp;bpmp TEGRA194_RESET_NVENC&gt;;</div><div class='add'>+				reset-names = "nvenc";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;bpmp TEGRA194_POWER_DOMAIN_NVENCA&gt;;</div><div class='add'>+				interconnects = &lt;&amp;mc TEGRA194_MEMORY_CLIENT_NVENCSRD &amp;emc&gt;,</div><div class='add'>+						&lt;&amp;mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &amp;emc&gt;,</div><div class='add'>+						&lt;&amp;mc TEGRA194_MEMORY_CLIENT_NVENCSWR &amp;emc&gt;;</div><div class='add'>+				interconnect-names = "dma-mem", "read-1", "write";</div><div class='add'>+				iommus = &lt;&amp;smmu TEGRA194_SID_NVENC&gt;;</div><div class='add'>+				dma-coherent;</div><div class='add'>+</div><div class='add'>+				nvidia,host1x-class = &lt;0x21&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			dpaux0: dpaux@155c0000 {</div><div class='ctx'> 				compatible = "nvidia,tegra194-dpaux";</div><div class='del'>-				reg = &lt;0x155c0000 0x10000&gt;;</div><div class='add'>+				reg = &lt;0x0 0x155c0000 0x0 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;bpmp TEGRA194_CLK_DPAUX&gt;,</div><div class='ctx'> 					 &lt;&amp;bpmp TEGRA194_CLK_PLLDP&gt;;</div><div class='hunk'>@@ -1148,7 +2143,7 @@</div><div class='ctx'> </div><div class='ctx'> 			dpaux1: dpaux@155d0000 {</div><div class='ctx'> 				compatible = "nvidia,tegra194-dpaux";</div><div class='del'>-				reg = &lt;0x155d0000 0x10000&gt;;</div><div class='add'>+				reg = &lt;0x0 0x155d0000 0x0 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;bpmp TEGRA194_CLK_DPAUX1&gt;,</div><div class='ctx'> 					 &lt;&amp;bpmp TEGRA194_CLK_PLLDP&gt;;</div><div class='hunk'>@@ -1182,7 +2177,7 @@</div><div class='ctx'> </div><div class='ctx'> 			dpaux2: dpaux@155e0000 {</div><div class='ctx'> 				compatible = "nvidia,tegra194-dpaux";</div><div class='del'>-				reg = &lt;0x155e0000 0x10000&gt;;</div><div class='add'>+				reg = &lt;0x0 0x155e0000 0x0 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;bpmp TEGRA194_CLK_DPAUX2&gt;,</div><div class='ctx'> 					 &lt;&amp;bpmp TEGRA194_CLK_PLLDP&gt;;</div><div class='hunk'>@@ -1216,7 +2211,7 @@</div><div class='ctx'> </div><div class='ctx'> 			dpaux3: dpaux@155f0000 {</div><div class='ctx'> 				compatible = "nvidia,tegra194-dpaux";</div><div class='del'>-				reg = &lt;0x155f0000 0x10000&gt;;</div><div class='add'>+				reg = &lt;0x0 0x155f0000 0x0 0x10000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;bpmp TEGRA194_CLK_DPAUX3&gt;,</div><div class='ctx'> 					 &lt;&amp;bpmp TEGRA194_CLK_PLLDP&gt;;</div><div class='hunk'>@@ -1248,9 +2243,28 @@</div><div class='ctx'> 				};</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='add'>+			nvenc@15a80000 {</div><div class='add'>+				compatible = "nvidia,tegra194-nvenc";</div><div class='add'>+				reg = &lt;0x0 0x15a80000 0x0 0x00040000&gt;;</div><div class='add'>+				clocks = &lt;&amp;bpmp TEGRA194_CLK_NVENC1&gt;;</div><div class='add'>+				clock-names = "nvenc";</div><div class='add'>+				resets = &lt;&amp;bpmp TEGRA194_RESET_NVENC1&gt;;</div><div class='add'>+				reset-names = "nvenc";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;bpmp TEGRA194_POWER_DOMAIN_NVENCB&gt;;</div><div class='add'>+				interconnects = &lt;&amp;mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &amp;emc&gt;,</div><div class='add'>+						&lt;&amp;mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &amp;emc&gt;,</div><div class='add'>+						&lt;&amp;mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &amp;emc&gt;;</div><div class='add'>+				interconnect-names = "dma-mem", "read-1", "write";</div><div class='add'>+				iommus = &lt;&amp;smmu TEGRA194_SID_NVENC1&gt;;</div><div class='add'>+				dma-coherent;</div><div class='add'>+</div><div class='add'>+				nvidia,host1x-class = &lt;0x22&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='ctx'> 			sor0: sor@15b00000 {</div><div class='ctx'> 				compatible = "nvidia,tegra194-sor";</div><div class='del'>-				reg = &lt;0x15b00000 0x40000&gt;;</div><div class='add'>+				reg = &lt;0x0 0x15b00000 0x0 0x40000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;bpmp TEGRA194_CLK_SOR0_REF&gt;,</div><div class='ctx'> 					 &lt;&amp;bpmp TEGRA194_CLK_SOR0_OUT&gt;,</div><div class='hunk'>@@ -1274,7 +2288,7 @@</div><div class='ctx'> </div><div class='ctx'> 			sor1: sor@15b40000 {</div><div class='ctx'> 				compatible = "nvidia,tegra194-sor";</div><div class='del'>-				reg = &lt;0x15b40000 0x40000&gt;;</div><div class='add'>+				reg = &lt;0x0 0x15b40000 0x0 0x40000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;bpmp TEGRA194_CLK_SOR1_REF&gt;,</div><div class='ctx'> 					 &lt;&amp;bpmp TEGRA194_CLK_SOR1_OUT&gt;,</div><div class='hunk'>@@ -1298,7 +2312,7 @@</div><div class='ctx'> </div><div class='ctx'> 			sor2: sor@15b80000 {</div><div class='ctx'> 				compatible = "nvidia,tegra194-sor";</div><div class='del'>-				reg = &lt;0x15b80000 0x40000&gt;;</div><div class='add'>+				reg = &lt;0x0 0x15b80000 0x0 0x40000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;bpmp TEGRA194_CLK_SOR2_REF&gt;,</div><div class='ctx'> 					 &lt;&amp;bpmp TEGRA194_CLK_SOR2_OUT&gt;,</div><div class='hunk'>@@ -1322,7 +2336,7 @@</div><div class='ctx'> </div><div class='ctx'> 			sor3: sor@15bc0000 {</div><div class='ctx'> 				compatible = "nvidia,tegra194-sor";</div><div class='del'>-				reg = &lt;0x15bc0000 0x40000&gt;;</div><div class='add'>+				reg = &lt;0x0 0x15bc0000 0x0 0x40000&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 				clocks = &lt;&amp;bpmp TEGRA194_CLK_SOR3_REF&gt;,</div><div class='ctx'> 					 &lt;&amp;bpmp TEGRA194_CLK_SOR3_OUT&gt;,</div><div class='hunk'>@@ -1344,397 +2358,494 @@</div><div class='ctx'> 				nvidia,interface = &lt;3&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='del'>-	};</div><div class='ctx'> </div><div class='del'>-	pcie@14100000 {</div><div class='del'>-		compatible = "nvidia,tegra194-pcie";</div><div class='del'>-		power-domains = &lt;&amp;bpmp TEGRA194_POWER_DOMAIN_PCIEX1A&gt;;</div><div class='del'>-		reg = &lt;0x00 0x14100000 0x0 0x00020000   /* appl registers (128K)      */</div><div class='del'>-		       0x00 0x30000000 0x0 0x00040000   /* configuration space (256K) */</div><div class='del'>-		       0x00 0x30040000 0x0 0x00040000   /* iATU_DMA reg space (256K)  */</div><div class='del'>-		       0x00 0x30080000 0x0 0x00040000&gt;; /* DBI reg space (256K)       */</div><div class='del'>-		reg-names = "appl", "config", "atu_dma", "dbi";</div><div class='add'>+		pcie@14100000 {</div><div class='add'>+			compatible = "nvidia,tegra194-pcie";</div><div class='add'>+			power-domains = &lt;&amp;bpmp TEGRA194_POWER_DOMAIN_PCIEX1A&gt;;</div><div class='add'>+			reg = &lt;0x00 0x14100000 0x0 0x00020000&gt;, /* appl registers (128K)      */</div><div class='add'>+			      &lt;0x00 0x30000000 0x0 0x00040000&gt;, /* configuration space (256K) */</div><div class='add'>+			      &lt;0x00 0x30040000 0x0 0x00040000&gt;, /* iATU_DMA reg space (256K)  */</div><div class='add'>+			      &lt;0x00 0x30080000 0x0 0x00040000&gt;; /* DBI reg space (256K)       */</div><div class='add'>+			reg-names = "appl", "config", "atu_dma", "dbi";</div><div class='ctx'> </div><div class='del'>-		status = "disabled";</div><div class='add'>+			status = "disabled";</div><div class='ctx'> </div><div class='del'>-		#address-cells = &lt;3&gt;;</div><div class='del'>-		#size-cells = &lt;2&gt;;</div><div class='del'>-		device_type = "pci";</div><div class='del'>-		num-lanes = &lt;1&gt;;</div><div class='del'>-		num-viewport = &lt;8&gt;;</div><div class='del'>-		linux,pci-domain = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			num-lanes = &lt;1&gt;;</div><div class='add'>+			linux,pci-domain = &lt;1&gt;;</div><div class='ctx'> </div><div class='del'>-		clocks = &lt;&amp;bpmp TEGRA194_CLK_PEX0_CORE_1&gt;;</div><div class='del'>-		clock-names = "core";</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA194_CLK_PEX0_CORE_1&gt;;</div><div class='add'>+			clock-names = "core";</div><div class='ctx'> </div><div class='del'>-		resets = &lt;&amp;bpmp TEGRA194_RESET_PEX0_CORE_1_APB&gt;,</div><div class='del'>-			 &lt;&amp;bpmp TEGRA194_RESET_PEX0_CORE_1&gt;;</div><div class='del'>-		reset-names = "apb", "core";</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA194_RESET_PEX0_CORE_1_APB&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA194_RESET_PEX0_CORE_1&gt;;</div><div class='add'>+			reset-names = "apb", "core";</div><div class='ctx'> </div><div class='del'>-		interrupts = &lt;GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH&gt;,	/* controller interrupt */</div><div class='del'>-			     &lt;GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH&gt;;	/* MSI interrupt */</div><div class='del'>-		interrupt-names = "intr", "msi";</div><div class='add'>+			interrupts = &lt;GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH&gt;, /* controller interrupt */</div><div class='add'>+				     &lt;GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH&gt;; /* MSI interrupt */</div><div class='add'>+			interrupt-names = "intr", "msi";</div><div class='ctx'> </div><div class='del'>-		#interrupt-cells = &lt;1&gt;;</div><div class='del'>-		interrupt-map-mask = &lt;0 0 0 0&gt;;</div><div class='del'>-		interrupt-map = &lt;0 0 0 0 &amp;gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 0 &amp;gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> </div><div class='del'>-		nvidia,bpmp = &lt;&amp;bpmp 1&gt;;</div><div class='add'>+			nvidia,bpmp = &lt;&amp;bpmp 1&gt;;</div><div class='ctx'> </div><div class='del'>-		nvidia,aspm-cmrt-us = &lt;60&gt;;</div><div class='del'>-		nvidia,aspm-pwr-on-t-us = &lt;20&gt;;</div><div class='del'>-		nvidia,aspm-l0s-entrance-latency-us = &lt;3&gt;;</div><div class='add'>+			nvidia,aspm-cmrt-us = &lt;60&gt;;</div><div class='add'>+			nvidia,aspm-pwr-on-t-us = &lt;20&gt;;</div><div class='add'>+			nvidia,aspm-l0s-entrance-latency-us = &lt;3&gt;;</div><div class='ctx'> </div><div class='del'>-		bus-range = &lt;0x0 0xff&gt;;</div><div class='del'>-		ranges = &lt;0x81000000 0x0  0x30100000 0x0  0x30100000 0x0 0x00100000   /* downstream I/O (1MB) */</div><div class='del'>-			  0xc2000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000   /* prefetchable memory (768MB) */</div><div class='del'>-			  0x82000000 0x0  0x40000000 0x12 0x30000000 0x0 0x10000000&gt;; /* non-prefetchable memory (256MB) */</div><div class='del'>-	};</div><div class='add'>+			bus-range = &lt;0x0 0xff&gt;;</div><div class='ctx'> </div><div class='del'>-	pcie@14120000 {</div><div class='del'>-		compatible = "nvidia,tegra194-pcie";</div><div class='del'>-		power-domains = &lt;&amp;bpmp TEGRA194_POWER_DOMAIN_PCIEX1A&gt;;</div><div class='del'>-		reg = &lt;0x00 0x14120000 0x0 0x00020000   /* appl registers (128K)      */</div><div class='del'>-		       0x00 0x32000000 0x0 0x00040000   /* configuration space (256K) */</div><div class='del'>-		       0x00 0x32040000 0x0 0x00040000   /* iATU_DMA reg space (256K)  */</div><div class='del'>-		       0x00 0x32080000 0x0 0x00040000&gt;; /* DBI reg space (256K)       */</div><div class='del'>-		reg-names = "appl", "config", "atu_dma", "dbi";</div><div class='add'>+			ranges = &lt;0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000&gt;, /* prefetchable memory (768 MiB) */</div><div class='add'>+				 &lt;0x02000000 0x0  0x40000000 0x12 0x30000000 0x0 0x0fff0000&gt;, /* non-prefetchable memory (256 MiB - 64 KiB) */</div><div class='add'>+				 &lt;0x01000000 0x0  0x00000000 0x12 0x3fff0000 0x0 0x00010000&gt;; /* downstream I/O (64 KiB) */</div><div class='ctx'> </div><div class='del'>-		status = "disabled";</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA194_MEMORY_CLIENT_PCIE1R &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA194_MEMORY_CLIENT_PCIE1W &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem", "write";</div><div class='add'>+			iommu-map = &lt;0x0 &amp;smmu TEGRA194_SID_PCIE1 0x1000&gt;;</div><div class='add'>+			iommu-map-mask = &lt;0x0&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+		};</div><div class='ctx'> </div><div class='del'>-		#address-cells = &lt;3&gt;;</div><div class='del'>-		#size-cells = &lt;2&gt;;</div><div class='del'>-		device_type = "pci";</div><div class='del'>-		num-lanes = &lt;1&gt;;</div><div class='del'>-		num-viewport = &lt;8&gt;;</div><div class='del'>-		linux,pci-domain = &lt;2&gt;;</div><div class='add'>+		pcie@14120000 {</div><div class='add'>+			compatible = "nvidia,tegra194-pcie";</div><div class='add'>+			power-domains = &lt;&amp;bpmp TEGRA194_POWER_DOMAIN_PCIEX1A&gt;;</div><div class='add'>+			reg = &lt;0x00 0x14120000 0x0 0x00020000&gt;, /* appl registers (128K)      */</div><div class='add'>+			      &lt;0x00 0x32000000 0x0 0x00040000&gt;, /* configuration space (256K) */</div><div class='add'>+			      &lt;0x00 0x32040000 0x0 0x00040000&gt;, /* iATU_DMA reg space (256K)  */</div><div class='add'>+			      &lt;0x00 0x32080000 0x0 0x00040000&gt;; /* DBI reg space (256K)       */</div><div class='add'>+			reg-names = "appl", "config", "atu_dma", "dbi";</div><div class='ctx'> </div><div class='del'>-		clocks = &lt;&amp;bpmp TEGRA194_CLK_PEX0_CORE_2&gt;;</div><div class='del'>-		clock-names = "core";</div><div class='add'>+			status = "disabled";</div><div class='ctx'> </div><div class='del'>-		resets = &lt;&amp;bpmp TEGRA194_RESET_PEX0_CORE_2_APB&gt;,</div><div class='del'>-			 &lt;&amp;bpmp TEGRA194_RESET_PEX0_CORE_2&gt;;</div><div class='del'>-		reset-names = "apb", "core";</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			num-lanes = &lt;1&gt;;</div><div class='add'>+			linux,pci-domain = &lt;2&gt;;</div><div class='ctx'> </div><div class='del'>-		interrupts = &lt;GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH&gt;,	/* controller interrupt */</div><div class='del'>-			     &lt;GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH&gt;;	/* MSI interrupt */</div><div class='del'>-		interrupt-names = "intr", "msi";</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA194_CLK_PEX0_CORE_2&gt;;</div><div class='add'>+			clock-names = "core";</div><div class='ctx'> </div><div class='del'>-		#interrupt-cells = &lt;1&gt;;</div><div class='del'>-		interrupt-map-mask = &lt;0 0 0 0&gt;;</div><div class='del'>-		interrupt-map = &lt;0 0 0 0 &amp;gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA194_RESET_PEX0_CORE_2_APB&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA194_RESET_PEX0_CORE_2&gt;;</div><div class='add'>+			reset-names = "apb", "core";</div><div class='ctx'> </div><div class='del'>-		nvidia,bpmp = &lt;&amp;bpmp 2&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH&gt;, /* controller interrupt */</div><div class='add'>+				     &lt;GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH&gt;; /* MSI interrupt */</div><div class='add'>+			interrupt-names = "intr", "msi";</div><div class='ctx'> </div><div class='del'>-		nvidia,aspm-cmrt-us = &lt;60&gt;;</div><div class='del'>-		nvidia,aspm-pwr-on-t-us = &lt;20&gt;;</div><div class='del'>-		nvidia,aspm-l0s-entrance-latency-us = &lt;3&gt;;</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 0 &amp;gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> </div><div class='del'>-		bus-range = &lt;0x0 0xff&gt;;</div><div class='del'>-		ranges = &lt;0x81000000 0x0  0x32100000 0x0  0x32100000 0x0 0x00100000   /* downstream I/O (1MB) */</div><div class='del'>-			  0xc2000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000   /* prefetchable memory (768MB) */</div><div class='del'>-			  0x82000000 0x0  0x40000000 0x12 0x70000000 0x0 0x10000000&gt;; /* non-prefetchable memory (256MB) */</div><div class='del'>-	};</div><div class='add'>+			nvidia,bpmp = &lt;&amp;bpmp 2&gt;;</div><div class='ctx'> </div><div class='del'>-	pcie@14140000 {</div><div class='del'>-		compatible = "nvidia,tegra194-pcie";</div><div class='del'>-		power-domains = &lt;&amp;bpmp TEGRA194_POWER_DOMAIN_PCIEX1A&gt;;</div><div class='del'>-		reg = &lt;0x00 0x14140000 0x0 0x00020000   /* appl registers (128K)      */</div><div class='del'>-		       0x00 0x34000000 0x0 0x00040000   /* configuration space (256K) */</div><div class='del'>-		       0x00 0x34040000 0x0 0x00040000   /* iATU_DMA reg space (256K)  */</div><div class='del'>-		       0x00 0x34080000 0x0 0x00040000&gt;; /* DBI reg space (256K)       */</div><div class='del'>-		reg-names = "appl", "config", "atu_dma", "dbi";</div><div class='add'>+			nvidia,aspm-cmrt-us = &lt;60&gt;;</div><div class='add'>+			nvidia,aspm-pwr-on-t-us = &lt;20&gt;;</div><div class='add'>+			nvidia,aspm-l0s-entrance-latency-us = &lt;3&gt;;</div><div class='ctx'> </div><div class='del'>-		status = "disabled";</div><div class='add'>+			bus-range = &lt;0x0 0xff&gt;;</div><div class='ctx'> </div><div class='del'>-		#address-cells = &lt;3&gt;;</div><div class='del'>-		#size-cells = &lt;2&gt;;</div><div class='del'>-		device_type = "pci";</div><div class='del'>-		num-lanes = &lt;1&gt;;</div><div class='del'>-		num-viewport = &lt;8&gt;;</div><div class='del'>-		linux,pci-domain = &lt;3&gt;;</div><div class='add'>+			ranges = &lt;0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000&gt;, /* prefetchable memory (768 MiB) */</div><div class='add'>+				 &lt;0x02000000 0x0  0x40000000 0x12 0x70000000 0x0 0x0fff0000&gt;, /* non-prefetchable memory (256 MiB - 64 KiB) */</div><div class='add'>+				 &lt;0x01000000 0x0  0x00000000 0x12 0x7fff0000 0x0 0x00010000&gt;; /* downstream I/O (64 KiB) */</div><div class='ctx'> </div><div class='del'>-		clocks = &lt;&amp;bpmp TEGRA194_CLK_PEX0_CORE_3&gt;;</div><div class='del'>-		clock-names = "core";</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA194_MEMORY_CLIENT_PCIE2AR &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA194_MEMORY_CLIENT_PCIE2AW &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem", "write";</div><div class='add'>+			iommu-map = &lt;0x0 &amp;smmu TEGRA194_SID_PCIE2 0x1000&gt;;</div><div class='add'>+			iommu-map-mask = &lt;0x0&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+		};</div><div class='ctx'> </div><div class='del'>-		resets = &lt;&amp;bpmp TEGRA194_RESET_PEX0_CORE_3_APB&gt;,</div><div class='del'>-			 &lt;&amp;bpmp TEGRA194_RESET_PEX0_CORE_3&gt;;</div><div class='del'>-		reset-names = "apb", "core";</div><div class='add'>+		pcie@14140000 {</div><div class='add'>+			compatible = "nvidia,tegra194-pcie";</div><div class='add'>+			power-domains = &lt;&amp;bpmp TEGRA194_POWER_DOMAIN_PCIEX1A&gt;;</div><div class='add'>+			reg = &lt;0x00 0x14140000 0x0 0x00020000&gt;, /* appl registers (128K)      */</div><div class='add'>+			      &lt;0x00 0x34000000 0x0 0x00040000&gt;, /* configuration space (256K) */</div><div class='add'>+			      &lt;0x00 0x34040000 0x0 0x00040000&gt;, /* iATU_DMA reg space (256K)  */</div><div class='add'>+			      &lt;0x00 0x34080000 0x0 0x00040000&gt;; /* DBI reg space (256K)       */</div><div class='add'>+			reg-names = "appl", "config", "atu_dma", "dbi";</div><div class='ctx'> </div><div class='del'>-		interrupts = &lt;GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH&gt;,	/* controller interrupt */</div><div class='del'>-			     &lt;GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH&gt;;	/* MSI interrupt */</div><div class='del'>-		interrupt-names = "intr", "msi";</div><div class='add'>+			status = "disabled";</div><div class='ctx'> </div><div class='del'>-		#interrupt-cells = &lt;1&gt;;</div><div class='del'>-		interrupt-map-mask = &lt;0 0 0 0&gt;;</div><div class='del'>-		interrupt-map = &lt;0 0 0 0 &amp;gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			num-lanes = &lt;1&gt;;</div><div class='add'>+			linux,pci-domain = &lt;3&gt;;</div><div class='ctx'> </div><div class='del'>-		nvidia,bpmp = &lt;&amp;bpmp 3&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA194_CLK_PEX0_CORE_3&gt;;</div><div class='add'>+			clock-names = "core";</div><div class='ctx'> </div><div class='del'>-		nvidia,aspm-cmrt-us = &lt;60&gt;;</div><div class='del'>-		nvidia,aspm-pwr-on-t-us = &lt;20&gt;;</div><div class='del'>-		nvidia,aspm-l0s-entrance-latency-us = &lt;3&gt;;</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA194_RESET_PEX0_CORE_3_APB&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA194_RESET_PEX0_CORE_3&gt;;</div><div class='add'>+			reset-names = "apb", "core";</div><div class='ctx'> </div><div class='del'>-		bus-range = &lt;0x0 0xff&gt;;</div><div class='del'>-		ranges = &lt;0x81000000 0x0  0x34100000 0x0  0x34100000 0x0 0x00100000   /* downstream I/O (1MB) */</div><div class='del'>-			  0xc2000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000   /* prefetchable memory (768MB) */</div><div class='del'>-			  0x82000000 0x0  0x40000000 0x12 0xb0000000 0x0 0x10000000&gt;; /* non-prefetchable memory (256MB) */</div><div class='del'>-	};</div><div class='add'>+			interrupts = &lt;GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH&gt;, /* controller interrupt */</div><div class='add'>+				     &lt;GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH&gt;; /* MSI interrupt */</div><div class='add'>+			interrupt-names = "intr", "msi";</div><div class='ctx'> </div><div class='del'>-	pcie@14160000 {</div><div class='del'>-		compatible = "nvidia,tegra194-pcie";</div><div class='del'>-		power-domains = &lt;&amp;bpmp TEGRA194_POWER_DOMAIN_PCIEX4A&gt;;</div><div class='del'>-		reg = &lt;0x00 0x14160000 0x0 0x00020000   /* appl registers (128K)      */</div><div class='del'>-		       0x00 0x36000000 0x0 0x00040000   /* configuration space (256K) */</div><div class='del'>-		       0x00 0x36040000 0x0 0x00040000   /* iATU_DMA reg space (256K)  */</div><div class='del'>-		       0x00 0x36080000 0x0 0x00040000&gt;; /* DBI reg space (256K)       */</div><div class='del'>-		reg-names = "appl", "config", "atu_dma", "dbi";</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 0 &amp;gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> </div><div class='del'>-		status = "disabled";</div><div class='add'>+			nvidia,bpmp = &lt;&amp;bpmp 3&gt;;</div><div class='ctx'> </div><div class='del'>-		#address-cells = &lt;3&gt;;</div><div class='del'>-		#size-cells = &lt;2&gt;;</div><div class='del'>-		device_type = "pci";</div><div class='del'>-		num-lanes = &lt;4&gt;;</div><div class='del'>-		num-viewport = &lt;8&gt;;</div><div class='del'>-		linux,pci-domain = &lt;4&gt;;</div><div class='add'>+			nvidia,aspm-cmrt-us = &lt;60&gt;;</div><div class='add'>+			nvidia,aspm-pwr-on-t-us = &lt;20&gt;;</div><div class='add'>+			nvidia,aspm-l0s-entrance-latency-us = &lt;3&gt;;</div><div class='ctx'> </div><div class='del'>-		clocks = &lt;&amp;bpmp TEGRA194_CLK_PEX0_CORE_4&gt;;</div><div class='del'>-		clock-names = "core";</div><div class='add'>+			bus-range = &lt;0x0 0xff&gt;;</div><div class='ctx'> </div><div class='del'>-		resets = &lt;&amp;bpmp TEGRA194_RESET_PEX0_CORE_4_APB&gt;,</div><div class='del'>-			 &lt;&amp;bpmp TEGRA194_RESET_PEX0_CORE_4&gt;;</div><div class='del'>-		reset-names = "apb", "core";</div><div class='add'>+			ranges = &lt;0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000&gt;, /* prefetchable memory (768 MiB) */</div><div class='add'>+				 &lt;0x02000000 0x0  0x40000000 0x12 0xb0000000 0x0 0x0fff0000&gt;, /* non-prefetchable memory (256 MiB + 64 KiB) */</div><div class='add'>+				 &lt;0x01000000 0x0  0x00000000 0x12 0xbfff0000 0x0 0x00010000&gt;; /* downstream I/O (64 KiB) */</div><div class='ctx'> </div><div class='del'>-		interrupts = &lt;GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH&gt;,	/* controller interrupt */</div><div class='del'>-			     &lt;GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH&gt;;	/* MSI interrupt */</div><div class='del'>-		interrupt-names = "intr", "msi";</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA194_MEMORY_CLIENT_PCIE3R &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA194_MEMORY_CLIENT_PCIE3W &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem", "write";</div><div class='add'>+			iommu-map = &lt;0x0 &amp;smmu TEGRA194_SID_PCIE3 0x1000&gt;;</div><div class='add'>+			iommu-map-mask = &lt;0x0&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+		};</div><div class='ctx'> </div><div class='del'>-		#interrupt-cells = &lt;1&gt;;</div><div class='del'>-		interrupt-map-mask = &lt;0 0 0 0&gt;;</div><div class='del'>-		interrupt-map = &lt;0 0 0 0 &amp;gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		pcie@14160000 {</div><div class='add'>+			compatible = "nvidia,tegra194-pcie";</div><div class='add'>+			power-domains = &lt;&amp;bpmp TEGRA194_POWER_DOMAIN_PCIEX4A&gt;;</div><div class='add'>+			reg = &lt;0x00 0x14160000 0x0 0x00020000&gt;, /* appl registers (128K)      */</div><div class='add'>+			      &lt;0x00 0x36000000 0x0 0x00040000&gt;, /* configuration space (256K) */</div><div class='add'>+			      &lt;0x00 0x36040000 0x0 0x00040000&gt;, /* iATU_DMA reg space (256K)  */</div><div class='add'>+			      &lt;0x00 0x36080000 0x0 0x00040000&gt;; /* DBI reg space (256K)       */</div><div class='add'>+			reg-names = "appl", "config", "atu_dma", "dbi";</div><div class='ctx'> </div><div class='del'>-		nvidia,bpmp = &lt;&amp;bpmp 4&gt;;</div><div class='add'>+			status = "disabled";</div><div class='ctx'> </div><div class='del'>-		nvidia,aspm-cmrt-us = &lt;60&gt;;</div><div class='del'>-		nvidia,aspm-pwr-on-t-us = &lt;20&gt;;</div><div class='del'>-		nvidia,aspm-l0s-entrance-latency-us = &lt;3&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			num-lanes = &lt;4&gt;;</div><div class='add'>+			linux,pci-domain = &lt;4&gt;;</div><div class='ctx'> </div><div class='del'>-		bus-range = &lt;0x0 0xff&gt;;</div><div class='del'>-		ranges = &lt;0x81000000 0x0  0x36100000 0x0  0x36100000 0x0 0x00100000   /* downstream I/O (1MB) */</div><div class='del'>-			  0xc2000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000   /* prefetchable memory (13GB) */</div><div class='del'>-			  0x82000000 0x0  0x40000000 0x17 0x40000000 0x0 0xc0000000&gt;; /* non-prefetchable memory (3GB) */</div><div class='del'>-	};</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA194_CLK_PEX0_CORE_4&gt;;</div><div class='add'>+			clock-names = "core";</div><div class='ctx'> </div><div class='del'>-	pcie@14180000 {</div><div class='del'>-		compatible = "nvidia,tegra194-pcie";</div><div class='del'>-		power-domains = &lt;&amp;bpmp TEGRA194_POWER_DOMAIN_PCIEX8B&gt;;</div><div class='del'>-		reg = &lt;0x00 0x14180000 0x0 0x00020000   /* appl registers (128K)      */</div><div class='del'>-		       0x00 0x38000000 0x0 0x00040000   /* configuration space (256K) */</div><div class='del'>-		       0x00 0x38040000 0x0 0x00040000   /* iATU_DMA reg space (256K)  */</div><div class='del'>-		       0x00 0x38080000 0x0 0x00040000&gt;; /* DBI reg space (256K)       */</div><div class='del'>-		reg-names = "appl", "config", "atu_dma", "dbi";</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA194_RESET_PEX0_CORE_4_APB&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA194_RESET_PEX0_CORE_4&gt;;</div><div class='add'>+			reset-names = "apb", "core";</div><div class='ctx'> </div><div class='del'>-		status = "disabled";</div><div class='add'>+			interrupts = &lt;GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH&gt;, /* controller interrupt */</div><div class='add'>+				     &lt;GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH&gt;; /* MSI interrupt */</div><div class='add'>+			interrupt-names = "intr", "msi";</div><div class='ctx'> </div><div class='del'>-		#address-cells = &lt;3&gt;;</div><div class='del'>-		#size-cells = &lt;2&gt;;</div><div class='del'>-		device_type = "pci";</div><div class='del'>-		num-lanes = &lt;8&gt;;</div><div class='del'>-		num-viewport = &lt;8&gt;;</div><div class='del'>-		linux,pci-domain = &lt;0&gt;;</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 0 &amp;gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> </div><div class='del'>-		clocks = &lt;&amp;bpmp TEGRA194_CLK_PEX0_CORE_0&gt;;</div><div class='del'>-		clock-names = "core";</div><div class='add'>+			nvidia,bpmp = &lt;&amp;bpmp 4&gt;;</div><div class='ctx'> </div><div class='del'>-		resets = &lt;&amp;bpmp TEGRA194_RESET_PEX0_CORE_0_APB&gt;,</div><div class='del'>-			 &lt;&amp;bpmp TEGRA194_RESET_PEX0_CORE_0&gt;;</div><div class='del'>-		reset-names = "apb", "core";</div><div class='add'>+			nvidia,aspm-cmrt-us = &lt;60&gt;;</div><div class='add'>+			nvidia,aspm-pwr-on-t-us = &lt;20&gt;;</div><div class='add'>+			nvidia,aspm-l0s-entrance-latency-us = &lt;3&gt;;</div><div class='ctx'> </div><div class='del'>-		interrupts = &lt;GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH&gt;,	/* controller interrupt */</div><div class='del'>-			     &lt;GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH&gt;;	/* MSI interrupt */</div><div class='del'>-		interrupt-names = "intr", "msi";</div><div class='add'>+			bus-range = &lt;0x0 0xff&gt;;</div><div class='ctx'> </div><div class='del'>-		#interrupt-cells = &lt;1&gt;;</div><div class='del'>-		interrupt-map-mask = &lt;0 0 0 0&gt;;</div><div class='del'>-		interrupt-map = &lt;0 0 0 0 &amp;gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			ranges = &lt;0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000&gt;, /* prefetchable memory (13 GiB) */</div><div class='add'>+				 &lt;0x02000000 0x0  0x40000000 0x17 0x40000000 0x0 0xbfff0000&gt;, /* non-prefetchable memory (3 GiB - 64 KiB) */</div><div class='add'>+				 &lt;0x01000000 0x0  0x00000000 0x17 0xffff0000 0x0 0x00010000&gt;; /* downstream I/O (64 KiB) */</div><div class='ctx'> </div><div class='del'>-		nvidia,bpmp = &lt;&amp;bpmp 0&gt;;</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA194_MEMORY_CLIENT_PCIE4R &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA194_MEMORY_CLIENT_PCIE4W &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem", "write";</div><div class='add'>+			iommu-map = &lt;0x0 &amp;smmu TEGRA194_SID_PCIE4 0x1000&gt;;</div><div class='add'>+			iommu-map-mask = &lt;0x0&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+		};</div><div class='ctx'> </div><div class='del'>-		nvidia,aspm-cmrt-us = &lt;60&gt;;</div><div class='del'>-		nvidia,aspm-pwr-on-t-us = &lt;20&gt;;</div><div class='del'>-		nvidia,aspm-l0s-entrance-latency-us = &lt;3&gt;;</div><div class='add'>+		pcie-ep@14160000 {</div><div class='add'>+			compatible = "nvidia,tegra194-pcie-ep";</div><div class='add'>+			power-domains = &lt;&amp;bpmp TEGRA194_POWER_DOMAIN_PCIEX4A&gt;;</div><div class='add'>+			reg = &lt;0x00 0x14160000 0x0 0x00020000&gt;, /* appl registers (128K)      */</div><div class='add'>+			      &lt;0x00 0x36040000 0x0 0x00040000&gt;, /* iATU_DMA reg space (256K)  */</div><div class='add'>+			      &lt;0x00 0x36080000 0x0 0x00040000&gt;, /* DBI reg space (256K)       */</div><div class='add'>+			      &lt;0x14 0x00000000 0x4 0x00000000&gt;; /* Address Space (16G)        */</div><div class='add'>+			reg-names = "appl", "atu_dma", "dbi", "addr_space";</div><div class='ctx'> </div><div class='del'>-		bus-range = &lt;0x0 0xff&gt;;</div><div class='del'>-		ranges = &lt;0x81000000 0x0  0x38100000 0x0  0x38100000 0x0 0x00100000   /* downstream I/O (1MB) */</div><div class='del'>-			  0xc2000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000   /* prefetchable memory (13GB) */</div><div class='del'>-			  0x82000000 0x0  0x40000000 0x1b 0x40000000 0x0 0xc0000000&gt;; /* non-prefetchable memory (3GB) */</div><div class='del'>-	};</div><div class='add'>+			status = "disabled";</div><div class='ctx'> </div><div class='del'>-	pcie@141a0000 {</div><div class='del'>-		compatible = "nvidia,tegra194-pcie";</div><div class='del'>-		power-domains = &lt;&amp;bpmp TEGRA194_POWER_DOMAIN_PCIEX8A&gt;;</div><div class='del'>-		reg = &lt;0x00 0x141a0000 0x0 0x00020000   /* appl registers (128K)      */</div><div class='del'>-		       0x00 0x3a000000 0x0 0x00040000   /* configuration space (256K) */</div><div class='del'>-		       0x00 0x3a040000 0x0 0x00040000   /* iATU_DMA reg space (256K)  */</div><div class='del'>-		       0x00 0x3a080000 0x0 0x00040000&gt;; /* DBI reg space (256K)       */</div><div class='del'>-		reg-names = "appl", "config", "atu_dma", "dbi";</div><div class='add'>+			num-lanes = &lt;4&gt;;</div><div class='add'>+			num-ib-windows = &lt;2&gt;;</div><div class='add'>+			num-ob-windows = &lt;8&gt;;</div><div class='ctx'> </div><div class='del'>-		status = "disabled";</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA194_CLK_PEX0_CORE_4&gt;;</div><div class='add'>+			clock-names = "core";</div><div class='ctx'> </div><div class='del'>-		#address-cells = &lt;3&gt;;</div><div class='del'>-		#size-cells = &lt;2&gt;;</div><div class='del'>-		device_type = "pci";</div><div class='del'>-		num-lanes = &lt;8&gt;;</div><div class='del'>-		num-viewport = &lt;8&gt;;</div><div class='del'>-		linux,pci-domain = &lt;5&gt;;</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA194_RESET_PEX0_CORE_4_APB&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA194_RESET_PEX0_CORE_4&gt;;</div><div class='add'>+			reset-names = "apb", "core";</div><div class='ctx'> </div><div class='del'>-		pinctrl-names = "default";</div><div class='del'>-		pinctrl-0 = &lt;&amp;pex_rst_c5_out_state&gt;, &lt;&amp;clkreq_c5_bi_dir_state&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH&gt;;	/* controller interrupt */</div><div class='add'>+			interrupt-names = "intr";</div><div class='ctx'> </div><div class='del'>-		clocks = &lt;&amp;bpmp TEGRA194_CLK_PEX1_CORE_5&gt;,</div><div class='del'>-			&lt;&amp;bpmp TEGRA194_CLK_PEX1_CORE_5M&gt;;</div><div class='del'>-		clock-names = "core", "core_m";</div><div class='add'>+			nvidia,bpmp = &lt;&amp;bpmp 4&gt;;</div><div class='ctx'> </div><div class='del'>-		resets = &lt;&amp;bpmp TEGRA194_RESET_PEX1_CORE_5_APB&gt;,</div><div class='del'>-			 &lt;&amp;bpmp TEGRA194_RESET_PEX1_CORE_5&gt;;</div><div class='del'>-		reset-names = "apb", "core";</div><div class='add'>+			nvidia,aspm-cmrt-us = &lt;60&gt;;</div><div class='add'>+			nvidia,aspm-pwr-on-t-us = &lt;20&gt;;</div><div class='add'>+			nvidia,aspm-l0s-entrance-latency-us = &lt;3&gt;;</div><div class='ctx'> </div><div class='del'>-		interrupts = &lt;GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH&gt;,	/* controller interrupt */</div><div class='del'>-			     &lt;GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH&gt;;	/* MSI interrupt */</div><div class='del'>-		interrupt-names = "intr", "msi";</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA194_MEMORY_CLIENT_PCIE4R &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA194_MEMORY_CLIENT_PCIE4W &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem", "write";</div><div class='add'>+			iommu-map = &lt;0x0 &amp;smmu TEGRA194_SID_PCIE4 0x1000&gt;;</div><div class='add'>+			iommu-map-mask = &lt;0x0&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+		};</div><div class='ctx'> </div><div class='del'>-		nvidia,bpmp = &lt;&amp;bpmp 5&gt;;</div><div class='add'>+		pcie@14180000 {</div><div class='add'>+			compatible = "nvidia,tegra194-pcie";</div><div class='add'>+			power-domains = &lt;&amp;bpmp TEGRA194_POWER_DOMAIN_PCIEX8B&gt;;</div><div class='add'>+			reg = &lt;0x00 0x14180000 0x0 0x00020000&gt;, /* appl registers (128K)      */</div><div class='add'>+			      &lt;0x00 0x38000000 0x0 0x00040000&gt;, /* configuration space (256K) */</div><div class='add'>+			      &lt;0x00 0x38040000 0x0 0x00040000&gt;, /* iATU_DMA reg space (256K)  */</div><div class='add'>+			      &lt;0x00 0x38080000 0x0 0x00040000&gt;; /* DBI reg space (256K)       */</div><div class='add'>+			reg-names = "appl", "config", "atu_dma", "dbi";</div><div class='ctx'> </div><div class='del'>-		#interrupt-cells = &lt;1&gt;;</div><div class='del'>-		interrupt-map-mask = &lt;0 0 0 0&gt;;</div><div class='del'>-		interrupt-map = &lt;0 0 0 0 &amp;gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			status = "disabled";</div><div class='ctx'> </div><div class='del'>-		nvidia,aspm-cmrt-us = &lt;60&gt;;</div><div class='del'>-		nvidia,aspm-pwr-on-t-us = &lt;20&gt;;</div><div class='del'>-		nvidia,aspm-l0s-entrance-latency-us = &lt;3&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			num-lanes = &lt;8&gt;;</div><div class='add'>+			linux,pci-domain = &lt;0&gt;;</div><div class='ctx'> </div><div class='del'>-		bus-range = &lt;0x0 0xff&gt;;</div><div class='del'>-		ranges = &lt;0x81000000 0x0  0x3a100000 0x0  0x3a100000 0x0 0x00100000   /* downstream I/O (1MB) */</div><div class='del'>-			  0xc2000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000   /* prefetchable memory (13GB) */</div><div class='del'>-			  0x82000000 0x0  0x40000000 0x1f 0x40000000 0x0 0xc0000000&gt;; /* non-prefetchable memory (3GB) */</div><div class='del'>-	};</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA194_CLK_PEX0_CORE_0&gt;;</div><div class='add'>+			clock-names = "core";</div><div class='ctx'> </div><div class='del'>-	pcie_ep@14160000 {</div><div class='del'>-		compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";</div><div class='del'>-		power-domains = &lt;&amp;bpmp TEGRA194_POWER_DOMAIN_PCIEX4A&gt;;</div><div class='del'>-		reg = &lt;0x00 0x14160000 0x0 0x00020000   /* appl registers (128K)      */</div><div class='del'>-		       0x00 0x36040000 0x0 0x00040000   /* iATU_DMA reg space (256K)  */</div><div class='del'>-		       0x00 0x36080000 0x0 0x00040000   /* DBI reg space (256K)       */</div><div class='del'>-		       0x14 0x00000000 0x4 0x00000000&gt;; /* Address Space (16G)        */</div><div class='del'>-		reg-names = "appl", "atu_dma", "dbi", "addr_space";</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA194_RESET_PEX0_CORE_0_APB&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA194_RESET_PEX0_CORE_0&gt;;</div><div class='add'>+			reset-names = "apb", "core";</div><div class='ctx'> </div><div class='del'>-		status = "disabled";</div><div class='add'>+			interrupts = &lt;GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH&gt;, /* controller interrupt */</div><div class='add'>+				     &lt;GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH&gt;; /* MSI interrupt */</div><div class='add'>+			interrupt-names = "intr", "msi";</div><div class='ctx'> </div><div class='del'>-		num-lanes = &lt;4&gt;;</div><div class='del'>-		num-ib-windows = &lt;2&gt;;</div><div class='del'>-		num-ob-windows = &lt;8&gt;;</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 0 &amp;gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> </div><div class='del'>-		clocks = &lt;&amp;bpmp TEGRA194_CLK_PEX0_CORE_4&gt;;</div><div class='del'>-		clock-names = "core";</div><div class='add'>+			nvidia,bpmp = &lt;&amp;bpmp 0&gt;;</div><div class='ctx'> </div><div class='del'>-		resets = &lt;&amp;bpmp TEGRA194_RESET_PEX0_CORE_4_APB&gt;,</div><div class='del'>-			 &lt;&amp;bpmp TEGRA194_RESET_PEX0_CORE_4&gt;;</div><div class='del'>-		reset-names = "apb", "core";</div><div class='add'>+			nvidia,aspm-cmrt-us = &lt;60&gt;;</div><div class='add'>+			nvidia,aspm-pwr-on-t-us = &lt;20&gt;;</div><div class='add'>+			nvidia,aspm-l0s-entrance-latency-us = &lt;3&gt;;</div><div class='ctx'> </div><div class='del'>-		interrupts = &lt;GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH&gt;;	/* controller interrupt */</div><div class='del'>-		interrupt-names = "intr";</div><div class='add'>+			bus-range = &lt;0x0 0xff&gt;;</div><div class='ctx'> </div><div class='del'>-		nvidia,bpmp = &lt;&amp;bpmp 4&gt;;</div><div class='add'>+			ranges = &lt;0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000&gt;, /* prefetchable memory (13 GiB) */</div><div class='add'>+				 &lt;0x02000000 0x0  0x40000000 0x1b 0x40000000 0x0 0xbfff0000&gt;, /* non-prefetchable memory (3 GiB - 64 KiB) */</div><div class='add'>+				 &lt;0x01000000 0x0  0x00000000 0x1b 0xffff0000 0x0 0x00010000&gt;; /* downstream I/O (64 KiB) */</div><div class='ctx'> </div><div class='del'>-		nvidia,aspm-cmrt-us = &lt;60&gt;;</div><div class='del'>-		nvidia,aspm-pwr-on-t-us = &lt;20&gt;;</div><div class='del'>-		nvidia,aspm-l0s-entrance-latency-us = &lt;3&gt;;</div><div class='del'>-	};</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA194_MEMORY_CLIENT_PCIE0R &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA194_MEMORY_CLIENT_PCIE0W &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem", "write";</div><div class='add'>+			iommu-map = &lt;0x0 &amp;smmu TEGRA194_SID_PCIE0 0x1000&gt;;</div><div class='add'>+			iommu-map-mask = &lt;0x0&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+		};</div><div class='ctx'> </div><div class='del'>-	pcie_ep@14180000 {</div><div class='del'>-		compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";</div><div class='del'>-		power-domains = &lt;&amp;bpmp TEGRA194_POWER_DOMAIN_PCIEX8B&gt;;</div><div class='del'>-		reg = &lt;0x00 0x14180000 0x0 0x00020000   /* appl registers (128K)      */</div><div class='del'>-		       0x00 0x38040000 0x0 0x00040000   /* iATU_DMA reg space (256K)  */</div><div class='del'>-		       0x00 0x38080000 0x0 0x00040000   /* DBI reg space (256K)       */</div><div class='del'>-		       0x18 0x00000000 0x4 0x00000000&gt;; /* Address Space (16G)        */</div><div class='del'>-		reg-names = "appl", "atu_dma", "dbi", "addr_space";</div><div class='add'>+		pcie-ep@14180000 {</div><div class='add'>+			compatible = "nvidia,tegra194-pcie-ep";</div><div class='add'>+			power-domains = &lt;&amp;bpmp TEGRA194_POWER_DOMAIN_PCIEX8B&gt;;</div><div class='add'>+			reg = &lt;0x00 0x14180000 0x0 0x00020000&gt;, /* appl registers (128K)      */</div><div class='add'>+			      &lt;0x00 0x38040000 0x0 0x00040000&gt;, /* iATU_DMA reg space (256K)  */</div><div class='add'>+			      &lt;0x00 0x38080000 0x0 0x00040000&gt;, /* DBI reg space (256K)       */</div><div class='add'>+			      &lt;0x18 0x00000000 0x4 0x00000000&gt;; /* Address Space (16G)        */</div><div class='add'>+			reg-names = "appl", "atu_dma", "dbi", "addr_space";</div><div class='ctx'> </div><div class='del'>-		status = "disabled";</div><div class='add'>+			status = "disabled";</div><div class='ctx'> </div><div class='del'>-		num-lanes = &lt;8&gt;;</div><div class='del'>-		num-ib-windows = &lt;2&gt;;</div><div class='del'>-		num-ob-windows = &lt;8&gt;;</div><div class='add'>+			num-lanes = &lt;8&gt;;</div><div class='add'>+			num-ib-windows = &lt;2&gt;;</div><div class='add'>+			num-ob-windows = &lt;8&gt;;</div><div class='ctx'> </div><div class='del'>-		clocks = &lt;&amp;bpmp TEGRA194_CLK_PEX0_CORE_0&gt;;</div><div class='del'>-		clock-names = "core";</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA194_CLK_PEX0_CORE_0&gt;;</div><div class='add'>+			clock-names = "core";</div><div class='ctx'> </div><div class='del'>-		resets = &lt;&amp;bpmp TEGRA194_RESET_PEX0_CORE_0_APB&gt;,</div><div class='del'>-			 &lt;&amp;bpmp TEGRA194_RESET_PEX0_CORE_0&gt;;</div><div class='del'>-		reset-names = "apb", "core";</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA194_RESET_PEX0_CORE_0_APB&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA194_RESET_PEX0_CORE_0&gt;;</div><div class='add'>+			reset-names = "apb", "core";</div><div class='ctx'> </div><div class='del'>-		interrupts = &lt;GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH&gt;;	/* controller interrupt */</div><div class='del'>-		interrupt-names = "intr";</div><div class='add'>+			interrupts = &lt;GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH&gt;;	/* controller interrupt */</div><div class='add'>+			interrupt-names = "intr";</div><div class='ctx'> </div><div class='del'>-		nvidia,bpmp = &lt;&amp;bpmp 0&gt;;</div><div class='add'>+			nvidia,bpmp = &lt;&amp;bpmp 0&gt;;</div><div class='ctx'> </div><div class='del'>-		nvidia,aspm-cmrt-us = &lt;60&gt;;</div><div class='del'>-		nvidia,aspm-pwr-on-t-us = &lt;20&gt;;</div><div class='del'>-		nvidia,aspm-l0s-entrance-latency-us = &lt;3&gt;;</div><div class='del'>-	};</div><div class='add'>+			nvidia,aspm-cmrt-us = &lt;60&gt;;</div><div class='add'>+			nvidia,aspm-pwr-on-t-us = &lt;20&gt;;</div><div class='add'>+			nvidia,aspm-l0s-entrance-latency-us = &lt;3&gt;;</div><div class='ctx'> </div><div class='del'>-	pcie_ep@141a0000 {</div><div class='del'>-		compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";</div><div class='del'>-		power-domains = &lt;&amp;bpmp TEGRA194_POWER_DOMAIN_PCIEX8A&gt;;</div><div class='del'>-		reg = &lt;0x00 0x141a0000 0x0 0x00020000   /* appl registers (128K)      */</div><div class='del'>-		       0x00 0x3a040000 0x0 0x00040000   /* iATU_DMA reg space (256K)  */</div><div class='del'>-		       0x00 0x3a080000 0x0 0x00040000   /* DBI reg space (256K)       */</div><div class='del'>-		       0x1c 0x00000000 0x4 0x00000000&gt;; /* Address Space (16G)        */</div><div class='del'>-		reg-names = "appl", "atu_dma", "dbi", "addr_space";</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA194_MEMORY_CLIENT_PCIE0R &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA194_MEMORY_CLIENT_PCIE0W &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem", "write";</div><div class='add'>+			iommu-map = &lt;0x0 &amp;smmu TEGRA194_SID_PCIE0 0x1000&gt;;</div><div class='add'>+			iommu-map-mask = &lt;0x0&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+		};</div><div class='ctx'> </div><div class='del'>-		status = "disabled";</div><div class='add'>+		pcie@141a0000 {</div><div class='add'>+			compatible = "nvidia,tegra194-pcie";</div><div class='add'>+			power-domains = &lt;&amp;bpmp TEGRA194_POWER_DOMAIN_PCIEX8A&gt;;</div><div class='add'>+			reg = &lt;0x00 0x141a0000 0x0 0x00020000&gt;, /* appl registers (128K)      */</div><div class='add'>+			      &lt;0x00 0x3a000000 0x0 0x00040000&gt;, /* configuration space (256K) */</div><div class='add'>+			      &lt;0x00 0x3a040000 0x0 0x00040000&gt;, /* iATU_DMA reg space (256K)  */</div><div class='add'>+			      &lt;0x00 0x3a080000 0x0 0x00040000&gt;; /* DBI reg space (256K)       */</div><div class='add'>+			reg-names = "appl", "config", "atu_dma", "dbi";</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='ctx'> </div><div class='del'>-		num-lanes = &lt;8&gt;;</div><div class='del'>-		num-ib-windows = &lt;2&gt;;</div><div class='del'>-		num-ob-windows = &lt;8&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			num-lanes = &lt;8&gt;;</div><div class='add'>+			linux,pci-domain = &lt;5&gt;;</div><div class='ctx'> </div><div class='del'>-		pinctrl-names = "default";</div><div class='del'>-		pinctrl-0 = &lt;&amp;clkreq_c5_bi_dir_state&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;pex_rst_c5_out_state&gt;, &lt;&amp;pex_clkreq_c5_bi_dir_state&gt;;</div><div class='ctx'> </div><div class='del'>-		clocks = &lt;&amp;bpmp TEGRA194_CLK_PEX1_CORE_5&gt;;</div><div class='del'>-		clock-names = "core";</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA194_CLK_PEX1_CORE_5&gt;;</div><div class='add'>+			clock-names = "core";</div><div class='ctx'> </div><div class='del'>-		resets = &lt;&amp;bpmp TEGRA194_RESET_PEX1_CORE_5_APB&gt;,</div><div class='del'>-			 &lt;&amp;bpmp TEGRA194_RESET_PEX1_CORE_5&gt;;</div><div class='del'>-		reset-names = "apb", "core";</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA194_RESET_PEX1_CORE_5_APB&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA194_RESET_PEX1_CORE_5&gt;;</div><div class='add'>+			reset-names = "apb", "core";</div><div class='ctx'> </div><div class='del'>-		interrupts = &lt;GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH&gt;;	/* controller interrupt */</div><div class='del'>-		interrupt-names = "intr";</div><div class='add'>+			interrupts = &lt;GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH&gt;, /* controller interrupt */</div><div class='add'>+				     &lt;GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH&gt;; /* MSI interrupt */</div><div class='add'>+			interrupt-names = "intr", "msi";</div><div class='ctx'> </div><div class='del'>-		nvidia,bpmp = &lt;&amp;bpmp 5&gt;;</div><div class='add'>+			nvidia,bpmp = &lt;&amp;bpmp 5&gt;;</div><div class='ctx'> </div><div class='del'>-		nvidia,aspm-cmrt-us = &lt;60&gt;;</div><div class='del'>-		nvidia,aspm-pwr-on-t-us = &lt;20&gt;;</div><div class='del'>-		nvidia,aspm-l0s-entrance-latency-us = &lt;3&gt;;</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 0 &amp;gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			nvidia,aspm-cmrt-us = &lt;60&gt;;</div><div class='add'>+			nvidia,aspm-pwr-on-t-us = &lt;20&gt;;</div><div class='add'>+			nvidia,aspm-l0s-entrance-latency-us = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+			bus-range = &lt;0x0 0xff&gt;;</div><div class='add'>+</div><div class='add'>+			ranges = &lt;0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000&gt;, /* prefetchable memory (13 GiB) */</div><div class='add'>+				 &lt;0x02000000 0x0  0x40000000 0x1f 0x40000000 0x0 0xbfff0000&gt;, /* non-prefetchable memory (3 GiB - 64 KiB) */</div><div class='add'>+				 &lt;0x01000000 0x0  0x00000000 0x1f 0xffff0000 0x0 0x00010000&gt;; /* downstream I/O (64 KiB) */</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA194_MEMORY_CLIENT_PCIE5R &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA194_MEMORY_CLIENT_PCIE5W &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem", "write";</div><div class='add'>+			iommu-map = &lt;0x0 &amp;smmu TEGRA194_SID_PCIE5 0x1000&gt;;</div><div class='add'>+			iommu-map-mask = &lt;0x0&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie-ep@141a0000 {</div><div class='add'>+			compatible = "nvidia,tegra194-pcie-ep";</div><div class='add'>+			power-domains = &lt;&amp;bpmp TEGRA194_POWER_DOMAIN_PCIEX8A&gt;;</div><div class='add'>+			reg = &lt;0x00 0x141a0000 0x0 0x00020000&gt;, /* appl registers (128K)      */</div><div class='add'>+			      &lt;0x00 0x3a040000 0x0 0x00040000&gt;, /* iATU_DMA reg space (256K)  */</div><div class='add'>+			      &lt;0x00 0x3a080000 0x0 0x00040000&gt;, /* DBI reg space (256K)       */</div><div class='add'>+			      &lt;0x1c 0x00000000 0x4 0x00000000&gt;; /* Address Space (16G)        */</div><div class='add'>+			reg-names = "appl", "atu_dma", "dbi", "addr_space";</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			num-lanes = &lt;8&gt;;</div><div class='add'>+			num-ib-windows = &lt;2&gt;;</div><div class='add'>+			num-ob-windows = &lt;8&gt;;</div><div class='add'>+</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;pex_clkreq_c5_bi_dir_state&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA194_CLK_PEX1_CORE_5&gt;;</div><div class='add'>+			clock-names = "core";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA194_RESET_PEX1_CORE_5_APB&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA194_RESET_PEX1_CORE_5&gt;;</div><div class='add'>+			reset-names = "apb", "core";</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH&gt;;	/* controller interrupt */</div><div class='add'>+			interrupt-names = "intr";</div><div class='add'>+</div><div class='add'>+			nvidia,bpmp = &lt;&amp;bpmp 5&gt;;</div><div class='add'>+</div><div class='add'>+			nvidia,aspm-cmrt-us = &lt;60&gt;;</div><div class='add'>+			nvidia,aspm-pwr-on-t-us = &lt;20&gt;;</div><div class='add'>+			nvidia,aspm-l0s-entrance-latency-us = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA194_MEMORY_CLIENT_PCIE5R &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA194_MEMORY_CLIENT_PCIE5W &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem", "write";</div><div class='add'>+			iommu-map = &lt;0x0 &amp;smmu TEGRA194_SID_PCIE5 0x1000&gt;;</div><div class='add'>+			iommu-map-mask = &lt;0x0&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu@17000000 {</div><div class='add'>+			compatible = "nvidia,gv11b";</div><div class='add'>+			reg = &lt;0x0 0x17000000 0x0 0x1000000&gt;,</div><div class='add'>+			      &lt;0x0 0x18000000 0x0 0x1000000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "stall", "nonstall";</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA194_CLK_GPCCLK&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA194_CLK_GPU_PWR&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA194_CLK_FUSE&gt;;</div><div class='add'>+			clock-names = "gpu", "pwr", "fuse";</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA194_RESET_GPU&gt;;</div><div class='add'>+			reset-names = "gpu";</div><div class='add'>+			dma-coherent;</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;bpmp TEGRA194_POWER_DOMAIN_GPU&gt;;</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA194_MEMORY_CLIENT_NVL1R &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA194_MEMORY_CLIENT_NVL1RHP &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA194_MEMORY_CLIENT_NVL1W &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA194_MEMORY_CLIENT_NVL2R &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA194_MEMORY_CLIENT_NVL2RHP &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA194_MEMORY_CLIENT_NVL2W &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA194_MEMORY_CLIENT_NVL3R &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA194_MEMORY_CLIENT_NVL3RHP &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA194_MEMORY_CLIENT_NVL3W &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA194_MEMORY_CLIENT_NVL4R &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA194_MEMORY_CLIENT_NVL4RHP &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA194_MEMORY_CLIENT_NVL4W &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem", "read-0-hp", "write-0",</div><div class='add'>+					     "read-1", "read-1-hp", "write-1",</div><div class='add'>+					     "read-2", "read-2-hp", "write-2",</div><div class='add'>+					     "read-3", "read-3-hp", "write-3";</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sysram@40000000 {</div><div class='add'>+	sram@40000000 {</div><div class='ctx'> 		compatible = "nvidia,tegra194-sysram", "mmio-sram";</div><div class='ctx'> 		reg = &lt;0x0 0x40000000 0x0 0x50000&gt;;</div><div class='add'>+</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;1&gt;;</div><div class='ctx'> 		ranges = &lt;0x0 0x0 0x40000000 0x50000&gt;;</div><div class='ctx'> </div><div class='del'>-		cpu_bpmp_tx: shmem@4e000 {</div><div class='del'>-			compatible = "nvidia,tegra194-bpmp-shmem";</div><div class='add'>+		no-memory-wc;</div><div class='add'>+</div><div class='add'>+		cpu_bpmp_tx: sram@4e000 {</div><div class='ctx'> 			reg = &lt;0x4e000 0x1000&gt;;</div><div class='ctx'> 			label = "cpu-bpmp-tx";</div><div class='ctx'> 			pool;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		cpu_bpmp_rx: shmem@4f000 {</div><div class='del'>-			compatible = "nvidia,tegra194-bpmp-shmem";</div><div class='add'>+		cpu_bpmp_rx: sram@4f000 {</div><div class='ctx'> 			reg = &lt;0x4f000 0x1000&gt;;</div><div class='ctx'> 			label = "cpu-bpmp-rx";</div><div class='ctx'> 			pool;</div><div class='hunk'>@@ -1745,10 +2856,16 @@</div><div class='ctx'> 		compatible = "nvidia,tegra186-bpmp";</div><div class='ctx'> 		mboxes = &lt;&amp;hsp_top0 TEGRA_HSP_MBOX_TYPE_DB</div><div class='ctx'> 				    TEGRA_HSP_DB_MASTER_BPMP&gt;;</div><div class='del'>-		shmem = &lt;&amp;cpu_bpmp_tx &amp;cpu_bpmp_rx&gt;;</div><div class='add'>+		shmem = &lt;&amp;cpu_bpmp_tx&gt;, &lt;&amp;cpu_bpmp_rx&gt;;</div><div class='ctx'> 		#clock-cells = &lt;1&gt;;</div><div class='ctx'> 		#reset-cells = &lt;1&gt;;</div><div class='ctx'> 		#power-domain-cells = &lt;1&gt;;</div><div class='add'>+		interconnects = &lt;&amp;mc TEGRA194_MEMORY_CLIENT_BPMPR &amp;emc&gt;,</div><div class='add'>+				&lt;&amp;mc TEGRA194_MEMORY_CLIENT_BPMPW &amp;emc&gt;,</div><div class='add'>+				&lt;&amp;mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &amp;emc&gt;,</div><div class='add'>+				&lt;&amp;mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &amp;emc&gt;;</div><div class='add'>+		interconnect-names = "read", "write", "dma-mem", "dma-write";</div><div class='add'>+		iommus = &lt;&amp;smmu TEGRA194_SID_BPMP&gt;;</div><div class='ctx'> </div><div class='ctx'> 		bpmp_i2c: i2c {</div><div class='ctx'> 			compatible = "nvidia,tegra186-bpmp-i2c";</div><div class='hunk'>@@ -1764,6 +2881,8 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	cpus {</div><div class='add'>+		compatible = "nvidia,tegra194-ccplex";</div><div class='add'>+		nvidia,bpmp = &lt;&amp;bpmp&gt;;</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;0&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -1922,87 +3041,130 @@</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		l2c_0: l2-cache0 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-unified;</div><div class='ctx'> 			cache-size = &lt;2097152&gt;;</div><div class='ctx'> 			cache-line-size = &lt;64&gt;;</div><div class='ctx'> 			cache-sets = &lt;2048&gt;;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;l3c&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		l2c_1: l2-cache1 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-unified;</div><div class='ctx'> 			cache-size = &lt;2097152&gt;;</div><div class='ctx'> 			cache-line-size = &lt;64&gt;;</div><div class='ctx'> 			cache-sets = &lt;2048&gt;;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;l3c&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		l2c_2: l2-cache2 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-unified;</div><div class='ctx'> 			cache-size = &lt;2097152&gt;;</div><div class='ctx'> 			cache-line-size = &lt;64&gt;;</div><div class='ctx'> 			cache-sets = &lt;2048&gt;;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;l3c&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		l2c_3: l2-cache3 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-unified;</div><div class='ctx'> 			cache-size = &lt;2097152&gt;;</div><div class='ctx'> 			cache-line-size = &lt;64&gt;;</div><div class='ctx'> 			cache-sets = &lt;2048&gt;;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='ctx'> 			next-level-cache = &lt;&amp;l3c&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		l3c: l3-cache {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-unified;</div><div class='ctx'> 			cache-size = &lt;4194304&gt;;</div><div class='ctx'> 			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-level = &lt;3&gt;;</div><div class='ctx'> 			cache-sets = &lt;4096&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	pmu {</div><div class='add'>+		compatible = "nvidia,carmel-pmu";</div><div class='add'>+		interrupts = &lt;GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-affinity = &lt;&amp;cpu0_0 &amp;cpu0_1 &amp;cpu1_0 &amp;cpu1_1</div><div class='add'>+				      &amp;cpu2_0 &amp;cpu2_1 &amp;cpu3_0 &amp;cpu3_1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	psci {</div><div class='ctx'> 		compatible = "arm,psci-1.0";</div><div class='ctx'> 		status = "okay";</div><div class='ctx'> 		method = "smc";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	tcu: tcu {</div><div class='add'>+	tcu: serial {</div><div class='ctx'> 		compatible = "nvidia,tegra194-tcu";</div><div class='ctx'> 		mboxes = &lt;&amp;hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)&gt;,</div><div class='del'>-		         &lt;&amp;hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)&gt;;</div><div class='add'>+			 &lt;&amp;hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)&gt;;</div><div class='ctx'> 		mbox-names = "rx", "tx";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	sound {</div><div class='add'>+		status = "disabled";</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;bpmp TEGRA194_CLK_PLLA&gt;,</div><div class='add'>+			 &lt;&amp;bpmp TEGRA194_CLK_PLLA_OUT0&gt;;</div><div class='add'>+		clock-names = "pll_a", "plla_out0";</div><div class='add'>+		assigned-clocks = &lt;&amp;bpmp TEGRA194_CLK_PLLA&gt;,</div><div class='add'>+				  &lt;&amp;bpmp TEGRA194_CLK_PLLA_OUT0&gt;,</div><div class='add'>+				  &lt;&amp;bpmp TEGRA194_CLK_AUD_MCLK&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;,</div><div class='add'>+					 &lt;&amp;bpmp TEGRA194_CLK_PLLA&gt;,</div><div class='add'>+					 &lt;&amp;bpmp TEGRA194_CLK_PLLA_OUT0&gt;;</div><div class='add'>+		/*</div><div class='add'>+		 * PLLA supports dynamic ramp. Below initial rate is chosen</div><div class='add'>+		 * for this to work and oscillate between base rates required</div><div class='add'>+		 * for 8x and 11.025x sample rate streams.</div><div class='add'>+		 */</div><div class='add'>+		assigned-clock-rates = &lt;258000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	thermal-zones {</div><div class='del'>-		cpu {</div><div class='del'>-			thermal-sensors = &lt;&amp;{/bpmp/thermal}</div><div class='del'>-					   TEGRA194_BPMP_THERMAL_ZONE_CPU&gt;;</div><div class='add'>+		cpu-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		gpu {</div><div class='del'>-			thermal-sensors = &lt;&amp;{/bpmp/thermal}</div><div class='del'>-					   TEGRA194_BPMP_THERMAL_ZONE_GPU&gt;;</div><div class='add'>+		gpu-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		aux {</div><div class='del'>-			thermal-sensors = &lt;&amp;{/bpmp/thermal}</div><div class='del'>-					   TEGRA194_BPMP_THERMAL_ZONE_AUX&gt;;</div><div class='add'>+		aux-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		pllx {</div><div class='del'>-			thermal-sensors = &lt;&amp;{/bpmp/thermal}</div><div class='del'>-					   TEGRA194_BPMP_THERMAL_ZONE_PLLX&gt;;</div><div class='add'>+		pllx-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		ao {</div><div class='del'>-			thermal-sensors = &lt;&amp;{/bpmp/thermal}</div><div class='del'>-					   TEGRA194_BPMP_THERMAL_ZONE_AO&gt;;</div><div class='add'>+		ao-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		tj {</div><div class='del'>-			thermal-sensors = &lt;&amp;{/bpmp/thermal}</div><div class='del'>-					   TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX&gt;;</div><div class='add'>+		tj-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi<br/>index f87d2437d11c..9ee7952af799 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi</a></div><div class='hunk'>@@ -11,26 +11,111 @@</div><div class='ctx'> 		rtc0 = "/i2c@7000d000/pmic@3c";</div><div class='ctx'> 		rtc1 = "/rtc@7000e000";</div><div class='ctx'> 		serial0 = &amp;uarta;</div><div class='add'>+		serial3 = &amp;uartd;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	chosen {</div><div class='ctx'> 		stdout-path = "serial0:115200n8";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	memory {</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@80000000 {</div><div class='ctx'> 		device_type = "memory";</div><div class='ctx'> 		reg = &lt;0x0 0x80000000 0x1 0x0&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	gpu@57000000 {</div><div class='ctx'> 		vdd-supply = &lt;&amp;vdd_gpu&gt;;</div><div class='add'>+		status = "okay";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	/* debug port */</div><div class='ctx'> 	serial@70006000 {</div><div class='add'>+		/delete-property/ dmas;</div><div class='add'>+		/delete-property/ dma-names;</div><div class='ctx'> 		status = "okay";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	serial@70006300 {</div><div class='add'>+		/delete-property/ reg-shift;</div><div class='add'>+		status = "okay";</div><div class='add'>+		compatible = "nvidia,tegra30-hsuart";</div><div class='add'>+		reset-names = "serial";</div><div class='add'>+</div><div class='add'>+		bluetooth {</div><div class='add'>+			compatible = "brcm,bcm43540-bt";</div><div class='add'>+			device-wakeup-gpios = &lt;&amp;gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			shutdown-gpios = &lt;&amp;gpio TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio&gt;;</div><div class='add'>+			interrupts = &lt;TEGRA_GPIO(H, 5) IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			interrupt-names = "host-wakeup";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c@7000c000 {</div><div class='add'>+		status = "okay";</div><div class='add'>+</div><div class='add'>+		tmp451: temperature-sensor@4c {</div><div class='add'>+			compatible = "ti,tmp451";</div><div class='add'>+			reg = &lt;0x4c&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio&gt;;</div><div class='add'>+			interrupts = &lt;TEGRA_GPIO(X, 4) IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			vcc-supply = &lt;&amp;vdd_1v8&gt;;</div><div class='add'>+			#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c@7000c400 {</div><div class='add'>+		status = "okay";</div><div class='add'>+</div><div class='add'>+		power-sensor@40 {</div><div class='add'>+			compatible = "ti,ina3221";</div><div class='add'>+			reg = &lt;0x40&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			input@0 {</div><div class='add'>+				reg = &lt;0x0&gt;;</div><div class='add'>+				label = "VDD_IN";</div><div class='add'>+				shunt-resistor-micro-ohms = &lt;20000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			input@1 {</div><div class='add'>+				reg = &lt;0x1&gt;;</div><div class='add'>+				label = "VDD_GPU";</div><div class='add'>+				shunt-resistor-micro-ohms = &lt;10000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			input@2 {</div><div class='add'>+				reg = &lt;0x2&gt;;</div><div class='add'>+				label = "VDD_CPU";</div><div class='add'>+				shunt-resistor-micro-ohms = &lt;10000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c@7000c500 {</div><div class='add'>+		status = "okay";</div><div class='add'>+</div><div class='add'>+		/* module ID EEPROM */</div><div class='add'>+		eeprom@50 {</div><div class='add'>+			compatible = "atmel,24c02";</div><div class='add'>+			reg = &lt;0x50&gt;;</div><div class='add'>+</div><div class='add'>+			label = "module";</div><div class='add'>+			vcc-supply = &lt;&amp;vdd_1v8&gt;;</div><div class='add'>+			address-width = &lt;8&gt;;</div><div class='add'>+			pagesize = &lt;8&gt;;</div><div class='add'>+			size = &lt;256&gt;;</div><div class='add'>+			read-only;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	i2c@7000d000 {</div><div class='ctx'> 		status = "okay";</div><div class='ctx'> 		clock-frequency = &lt;400000&gt;;</div><div class='hunk'>@@ -38,7 +123,8 @@</div><div class='ctx'> 		pmic: pmic@3c {</div><div class='ctx'> 			compatible = "maxim,max77620";</div><div class='ctx'> 			reg = &lt;0x3c&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;tegra_pmc&gt;;</div><div class='add'>+			interrupts = &lt;51 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> </div><div class='ctx'> 			#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 			interrupt-controller;</div><div class='hunk'>@@ -49,6 +135,22 @@</div><div class='ctx'> 			pinctrl-names = "default";</div><div class='ctx'> 			pinctrl-0 = &lt;&amp;max77620_default&gt;;</div><div class='ctx'> </div><div class='add'>+			fps {</div><div class='add'>+				fps0 {</div><div class='add'>+					maxim,fps-event-source = &lt;MAX77620_FPS_EVENT_SRC_EN0&gt;;</div><div class='add'>+					maxim,suspend-fps-time-period-us = &lt;1280&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				fps1 {</div><div class='add'>+					maxim,fps-event-source = &lt;MAX77620_FPS_EVENT_SRC_EN1&gt;;</div><div class='add'>+					maxim,suspend-fps-time-period-us = &lt;1280&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				fps2 {</div><div class='add'>+					maxim,fps-event-source = &lt;MAX77620_FPS_EVENT_SRC_EN0&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='ctx'> 			max77620_default: pinmux {</div><div class='ctx'> 				gpio0 {</div><div class='ctx'> 					pins = "gpio0";</div><div class='hunk'>@@ -83,22 +185,6 @@</div><div class='ctx'> 				};</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			fps {</div><div class='del'>-				fps0 {</div><div class='del'>-					maxim,fps-event-source = &lt;MAX77620_FPS_EVENT_SRC_EN0&gt;;</div><div class='del'>-					maxim,suspend-fps-time-period-us = &lt;1280&gt;;</div><div class='del'>-				};</div><div class='del'>-</div><div class='del'>-				fps1 {</div><div class='del'>-					maxim,fps-event-source = &lt;MAX77620_FPS_EVENT_SRC_EN1&gt;;</div><div class='del'>-					maxim,suspend-fps-time-period-us = &lt;1280&gt;;</div><div class='del'>-				};</div><div class='del'>-</div><div class='del'>-				fps2 {</div><div class='del'>-					maxim,fps-event-source = &lt;MAX77620_FPS_EVENT_SRC_EN0&gt;;</div><div class='del'>-				};</div><div class='del'>-			};</div><div class='del'>-</div><div class='ctx'> 			regulators {</div><div class='ctx'> 				in-ldo0-1-supply = &lt;&amp;vdd_pre&gt;;</div><div class='ctx'> 				in-ldo7-8-supply = &lt;&amp;vdd_pre&gt;;</div><div class='hunk'>@@ -264,22 +350,6 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	i2c@7000c500 {</div><div class='del'>-		status = "okay";</div><div class='del'>-</div><div class='del'>-		/* module ID EEPROM */</div><div class='del'>-		eeprom@50 {</div><div class='del'>-			compatible = "atmel,24c02";</div><div class='del'>-			reg = &lt;0x50&gt;;</div><div class='del'>-</div><div class='del'>-			vcc-supply = &lt;&amp;vdd_1v8&gt;;</div><div class='del'>-			address-bits = &lt;8&gt;;</div><div class='del'>-			page-size = &lt;8&gt;;</div><div class='del'>-			size = &lt;256&gt;;</div><div class='del'>-			read-only;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='ctx'> 	pmc@7000e400 {</div><div class='ctx'> 		nvidia,invert-interrupt;</div><div class='ctx'> 		nvidia,suspend-mode = &lt;0&gt;;</div><div class='hunk'>@@ -291,27 +361,39 @@</div><div class='ctx'> 		nvidia,sys-clock-req-active-high;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	/* eMMC */</div><div class='del'>-	sdhci@700b0600 {</div><div class='add'>+	mmc@700b0200 {</div><div class='ctx'> 		status = "okay";</div><div class='del'>-		bus-width = &lt;8&gt;;</div><div class='add'>+		bus-width = &lt;4&gt;;</div><div class='ctx'> 		non-removable;</div><div class='add'>+		power-gpios = &lt;&amp;gpio TEGRA_GPIO(H, 0) GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 		vqmmc-supply = &lt;&amp;vdd_1v8&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	clocks {</div><div class='del'>-		compatible = "simple-bus";</div><div class='add'>+		vmmc-supply = &lt;&amp;vdd_3v3_sys&gt;;</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;0&gt;;</div><div class='ctx'> </div><div class='del'>-		clk32k_in: clock@0 {</div><div class='del'>-			compatible = "fixed-clock";</div><div class='del'>-			reg = &lt;0&gt;;</div><div class='del'>-			#clock-cells = &lt;0&gt;;</div><div class='del'>-			clock-frequency = &lt;32768&gt;;</div><div class='add'>+		wifi@1 {</div><div class='add'>+			compatible = "brcm,bcm4354-fmac", "brcm,bcm4329-fmac";</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio&gt;;</div><div class='add'>+			interrupts = &lt;TEGRA_GPIO(H, 2) IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "host-wake";</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	/* eMMC */</div><div class='add'>+	mmc@700b0600 {</div><div class='add'>+		status = "okay";</div><div class='add'>+		bus-width = &lt;8&gt;;</div><div class='add'>+		non-removable;</div><div class='add'>+		vqmmc-supply = &lt;&amp;vdd_1v8&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk32k_in: clock-32k {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		clock-frequency = &lt;32768&gt;;</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	cpus {</div><div class='ctx'> 		cpu@0 {</div><div class='ctx'> 			enable-method = "psci";</div><div class='hunk'>@@ -341,18 +423,15 @@</div><div class='ctx'> 		method = "smc";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	regulators {</div><div class='del'>-		vdd_gpu: regulator@100 {</div><div class='del'>-			compatible = "pwm-regulator";</div><div class='del'>-			reg = &lt;100&gt;;</div><div class='del'>-			pwms = &lt;&amp;pwm 1 4880&gt;;</div><div class='del'>-			regulator-name = "VDD_GPU";</div><div class='del'>-			regulator-min-microvolt = &lt;710000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;1320000&gt;;</div><div class='del'>-			enable-gpios = &lt;&amp;pmic 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			regulator-ramp-delay = &lt;80&gt;;</div><div class='del'>-			regulator-enable-ramp-delay = &lt;2000&gt;;</div><div class='del'>-			regulator-settling-time-us = &lt;160&gt;;</div><div class='del'>-		};</div><div class='add'>+	vdd_gpu: regulator-vdd-gpu {</div><div class='add'>+		compatible = "pwm-regulator";</div><div class='add'>+		pwms = &lt;&amp;pwm 1 8000&gt;;</div><div class='add'>+		regulator-name = "VDD_GPU";</div><div class='add'>+		regulator-min-microvolt = &lt;710000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1320000&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;pmic 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		regulator-ramp-delay = &lt;80&gt;;</div><div class='add'>+		regulator-enable-ramp-delay = &lt;2000&gt;;</div><div class='add'>+		regulator-settling-time-us = &lt;160&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts<br/>index ea0e1efa6973..627abf51a5a4 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts</a></div><div class='hunk'>@@ -11,11 +11,8 @@</div><div class='ctx'> 	pcie@1003000 {</div><div class='ctx'> 		status = "okay";</div><div class='ctx'> </div><div class='del'>-		avdd-pll-uerefe-supply = &lt;&amp;avdd_1v05_pll&gt;;</div><div class='ctx'> 		hvddio-pex-supply = &lt;&amp;vdd_1v8&gt;;</div><div class='ctx'> 		dvddio-pex-supply = &lt;&amp;vdd_pex_1v05&gt;;</div><div class='del'>-		dvdd-pex-pll-supply = &lt;&amp;vdd_pex_1v05&gt;;</div><div class='del'>-		hvdd-pex-pll-e-supply = &lt;&amp;vdd_1v8&gt;;</div><div class='ctx'> 		vddio-pex-ctl-supply = &lt;&amp;vdd_1v8&gt;;</div><div class='ctx'> </div><div class='ctx'> 		pci@1,0 {</div><div class='hunk'>@@ -61,22 +58,20 @@</div><div class='ctx'> 			dev-ctrl = /bits/ 8 &lt;0x80&gt;;</div><div class='ctx'> 			init-brt = /bits/ 8 &lt;0xff&gt;;</div><div class='ctx'> </div><div class='del'>-			pwm-period = &lt;29334&gt;;</div><div class='del'>-</div><div class='ctx'> 			pwms = &lt;&amp;pwm 0 29334&gt;;</div><div class='ctx'> 			pwm-names = "lp8557";</div><div class='ctx'> </div><div class='del'>-			/* 3 LED string */</div><div class='del'>-			rom_14h {</div><div class='del'>-				rom-addr = /bits/ 8 &lt;0x14&gt;;</div><div class='del'>-				rom-val = /bits/ 8 &lt;0x87&gt;;</div><div class='del'>-			};</div><div class='del'>-</div><div class='ctx'> 			/* boost frequency 1 MHz */</div><div class='del'>-			rom_13h {</div><div class='add'>+			rom-13h {</div><div class='ctx'> 				rom-addr = /bits/ 8 &lt;0x13&gt;;</div><div class='ctx'> 				rom-val = /bits/ 8 &lt;0x01&gt;;</div><div class='ctx'> 			};</div><div class='add'>+</div><div class='add'>+			/* 3 LED string */</div><div class='add'>+			rom-14h {</div><div class='add'>+				rom-addr = /bits/ 8 &lt;0x14&gt;;</div><div class='add'>+				rom-val = /bits/ 8 &lt;0x87&gt;;</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -86,14 +81,21 @@</div><div class='ctx'> 			compatible = "atmel,24c02";</div><div class='ctx'> 			reg = &lt;0x57&gt;;</div><div class='ctx'> </div><div class='add'>+			label = "system";</div><div class='ctx'> 			vcc-supply = &lt;&amp;vdd_1v8&gt;;</div><div class='del'>-			address-bits = &lt;8&gt;;</div><div class='del'>-			page-size = &lt;8&gt;;</div><div class='add'>+			address-width = &lt;8&gt;;</div><div class='add'>+			pagesize = &lt;8&gt;;</div><div class='ctx'> 			size = &lt;256&gt;;</div><div class='ctx'> 			read-only;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	cec@70015000 {</div><div class='add'>+		status = "okay";</div><div class='add'>+</div><div class='add'>+		hdmi-phandle = &lt;&amp;sor1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	clock@70110000 {</div><div class='ctx'> 		status = "okay";</div><div class='ctx'> </div><div class='hunk'>@@ -118,12 +120,1271 @@</div><div class='ctx'> 	aconnect@702c0000 {</div><div class='ctx'> 		status = "okay";</div><div class='ctx'> </div><div class='del'>-		dma@702e2000 {</div><div class='add'>+		ahub@702d0800 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			admaif@702d0000 {</div><div class='add'>+				status = "okay";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2s@702d1000 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						i2s1_cif_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_i2s1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					i2s1_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						i2s1_dap_ep: endpoint {</div><div class='add'>+							dai-format = "i2s";</div><div class='add'>+							/* Placeholder for external Codec */</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2s@702d1100 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						i2s2_cif_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_i2s2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					i2s2_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						i2s2_dap_ep: endpoint {</div><div class='add'>+							dai-format = "i2s";</div><div class='add'>+							/* Placeholder for external Codec */</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2s@702d1200 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						i2s3_cif_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_i2s3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					i2s3_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						i2s3_dap_ep: endpoint {</div><div class='add'>+							dai-format = "i2s";</div><div class='add'>+							/* Placeholder for external Codec */</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2s@702d1300 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						i2s4_cif_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_i2s4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					i2s4_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						i2s4_dap_ep: endpoint {</div><div class='add'>+							dai-format = "i2s";</div><div class='add'>+							/* Placeholder for external Codec */</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2s@702d1400 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						i2s5_cif_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_i2s5_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					i2s5_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						i2s5_dap_ep: endpoint {</div><div class='add'>+							dai-format = "i2s";</div><div class='add'>+							/* Placeholder for external Codec */</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sfc@702d2000 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						sfc1_cif_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_sfc1_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					sfc1_out_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						sfc1_cif_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_sfc1_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sfc@702d2200 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						sfc2_cif_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_sfc2_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					sfc2_out_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						sfc2_cif_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_sfc2_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sfc@702d2400 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						sfc3_cif_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_sfc3_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					sfc3_out_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						sfc3_cif_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_sfc3_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sfc@702d2600 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						sfc4_cif_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_sfc4_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					sfc4_out_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						sfc4_cif_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_sfc4_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			amx@702d3000 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						amx1_in1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_amx1_in1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						amx1_in2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_amx1_in2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@2 {</div><div class='add'>+						reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+						amx1_in3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_amx1_in3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@3 {</div><div class='add'>+						reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+						amx1_in4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_amx1_in4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					amx1_out_port: port@4 {</div><div class='add'>+						reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+						amx1_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_amx1_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			amx@702d3100 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						amx2_in1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_amx2_in1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						amx2_in2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_amx2_in2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					amx2_in3_port: port@2 {</div><div class='add'>+						reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+						amx2_in3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_amx2_in3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					amx2_in4_port: port@3 {</div><div class='add'>+						reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+						amx2_in4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_amx2_in4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					amx2_out_port: port@4 {</div><div class='add'>+						reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+						amx2_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_amx2_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			adx@702d3800 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						adx1_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_adx1_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					adx1_out1_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						adx1_out1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_adx1_out1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					adx1_out2_port: port@2 {</div><div class='add'>+						reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+						adx1_out2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_adx1_out2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					adx1_out3_port: port@3 {</div><div class='add'>+						reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+						adx1_out3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_adx1_out3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					adx1_out4_port: port@4 {</div><div class='add'>+						reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+						adx1_out4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_adx1_out4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			adx@702d3900 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						adx2_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_adx2_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					adx2_out1_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						adx2_out1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_adx2_out1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					adx2_out2_port: port@2 {</div><div class='add'>+						reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+						adx2_out2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_adx2_out2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					adx2_out3_port: port@3 {</div><div class='add'>+						reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+						adx2_out3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_adx2_out3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					adx2_out4_port: port@4 {</div><div class='add'>+						reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+						adx2_out4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_adx2_out4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			dmic@702d4000 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						dmic1_cif_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_dmic1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					dmic1_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						dmic1_dap_ep: endpoint {</div><div class='add'>+							/* Placeholder for external Codec */</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			dmic@702d4100 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						dmic2_cif_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_dmic2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					dmic2_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						dmic2_dap_ep: endpoint {</div><div class='add'>+							/* Placeholder for external Codec */</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			dmic@702d4200 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						dmic3_cif_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_dmic3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					dmic3_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						dmic3_dap_ep: endpoint {</div><div class='add'>+							/* Placeholder for external Codec */</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			processing-engine@702d8000 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0x0&gt;;</div><div class='add'>+</div><div class='add'>+						ope1_cif_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_ope1_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					ope1_out_port: port@1 {</div><div class='add'>+						reg = &lt;0x1&gt;;</div><div class='add'>+</div><div class='add'>+						ope1_cif_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_ope1_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			processing-engine@702d8400 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0x0&gt;;</div><div class='add'>+</div><div class='add'>+						ope2_cif_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_ope2_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					ope2_out_port: port@1 {</div><div class='add'>+						reg = &lt;0x1&gt;;</div><div class='add'>+</div><div class='add'>+						ope2_cif_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_ope2_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mvc@702da000 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						mvc1_cif_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mvc1_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					mvc1_out_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						mvc1_cif_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mvc1_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mvc@702da200 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						mvc2_cif_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mvc2_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					mvc2_out_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						mvc2_cif_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mvc2_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			amixer@702dbb00 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0x0&gt;;</div><div class='add'>+</div><div class='add'>+						mixer_in1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mixer_in1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;0x1&gt;;</div><div class='add'>+</div><div class='add'>+						mixer_in2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mixer_in2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@2 {</div><div class='add'>+						reg = &lt;0x2&gt;;</div><div class='add'>+</div><div class='add'>+						mixer_in3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mixer_in3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@3 {</div><div class='add'>+						reg = &lt;0x3&gt;;</div><div class='add'>+</div><div class='add'>+						mixer_in4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mixer_in4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@4 {</div><div class='add'>+						reg = &lt;0x4&gt;;</div><div class='add'>+</div><div class='add'>+						mixer_in5_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mixer_in5_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@5 {</div><div class='add'>+						reg = &lt;0x5&gt;;</div><div class='add'>+</div><div class='add'>+						mixer_in6_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mixer_in6_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@6 {</div><div class='add'>+						reg = &lt;0x6&gt;;</div><div class='add'>+</div><div class='add'>+						mixer_in7_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mixer_in7_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@7 {</div><div class='add'>+						reg = &lt;0x7&gt;;</div><div class='add'>+</div><div class='add'>+						mixer_in8_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mixer_in8_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@8 {</div><div class='add'>+						reg = &lt;0x8&gt;;</div><div class='add'>+</div><div class='add'>+						mixer_in9_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mixer_in9_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@9 {</div><div class='add'>+						reg = &lt;0x9&gt;;</div><div class='add'>+</div><div class='add'>+						mixer_in10_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mixer_in10_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					mixer_out1_port: port@a {</div><div class='add'>+						reg = &lt;0xa&gt;;</div><div class='add'>+</div><div class='add'>+						mixer_out1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mixer_out1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					mixer_out2_port: port@b {</div><div class='add'>+						reg = &lt;0xb&gt;;</div><div class='add'>+</div><div class='add'>+						mixer_out2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mixer_out2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					mixer_out3_port: port@c {</div><div class='add'>+						reg = &lt;0xc&gt;;</div><div class='add'>+</div><div class='add'>+						mixer_out3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mixer_out3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					mixer_out4_port: port@d {</div><div class='add'>+						reg = &lt;0xd&gt;;</div><div class='add'>+</div><div class='add'>+						mixer_out4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mixer_out4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					mixer_out5_port: port@e {</div><div class='add'>+						reg = &lt;0xe&gt;;</div><div class='add'>+</div><div class='add'>+						mixer_out5_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mixer_out5_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				xbar_i2s1_port: port@a {</div><div class='add'>+					reg = &lt;0xa&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_i2s1_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;i2s1_cif_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_i2s2_port: port@b {</div><div class='add'>+					reg = &lt;0xb&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_i2s2_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;i2s2_cif_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_i2s3_port: port@c {</div><div class='add'>+					reg = &lt;0xc&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_i2s3_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;i2s3_cif_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_i2s4_port: port@d {</div><div class='add'>+					reg = &lt;0xd&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_i2s4_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;i2s4_cif_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_i2s5_port: port@e {</div><div class='add'>+					reg = &lt;0xe&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_i2s5_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;i2s5_cif_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_dmic1_port: port@f {</div><div class='add'>+					reg = &lt;0xf&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_dmic1_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dmic1_cif_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_dmic2_port: port@10 {</div><div class='add'>+					reg = &lt;0x10&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_dmic2_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dmic2_cif_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_dmic3_port: port@11 {</div><div class='add'>+					reg = &lt;0x11&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_dmic3_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dmic3_cif_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_sfc1_in_port: port@12 {</div><div class='add'>+					reg = &lt;0x12&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_sfc1_in_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;sfc1_cif_in_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@13 {</div><div class='add'>+					reg = &lt;0x13&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_sfc1_out_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;sfc1_cif_out_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_sfc2_in_port: port@14 {</div><div class='add'>+					reg = &lt;0x14&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_sfc2_in_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;sfc2_cif_in_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@15 {</div><div class='add'>+					reg = &lt;0x15&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_sfc2_out_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;sfc2_cif_out_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_sfc3_in_port: port@16 {</div><div class='add'>+					reg = &lt;0x16&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_sfc3_in_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;sfc3_cif_in_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@17 {</div><div class='add'>+					reg = &lt;0x17&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_sfc3_out_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;sfc3_cif_out_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_sfc4_in_port: port@18 {</div><div class='add'>+					reg = &lt;0x18&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_sfc4_in_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;sfc4_cif_in_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@19 {</div><div class='add'>+					reg = &lt;0x19&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_sfc4_out_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;sfc4_cif_out_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_mvc1_in_port: port@1a {</div><div class='add'>+					reg = &lt;0x1a&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mvc1_in_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mvc1_cif_in_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1b {</div><div class='add'>+					reg = &lt;0x1b&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mvc1_out_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mvc1_cif_out_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_mvc2_in_port: port@1c {</div><div class='add'>+					reg = &lt;0x1c&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mvc2_in_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mvc2_cif_in_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1d {</div><div class='add'>+					reg = &lt;0x1d&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mvc2_out_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mvc2_cif_out_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_amx1_in1_port: port@1e {</div><div class='add'>+					reg = &lt;0x1e&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_amx1_in1_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;amx1_in1_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_amx1_in2_port: port@1f {</div><div class='add'>+					reg = &lt;0x1f&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_amx1_in2_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;amx1_in2_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_amx1_in3_port: port@20 {</div><div class='add'>+					reg = &lt;0x20&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_amx1_in3_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;amx1_in3_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_amx1_in4_port: port@21 {</div><div class='add'>+					reg = &lt;0x21&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_amx1_in4_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;amx1_in4_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@22 {</div><div class='add'>+					reg = &lt;0x22&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_amx1_out_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;amx1_out_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_amx2_in1_port: port@23 {</div><div class='add'>+					reg = &lt;0x23&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_amx2_in1_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;amx2_in1_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_amx2_in2_port: port@24 {</div><div class='add'>+					reg = &lt;0x24&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_amx2_in2_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;amx2_in2_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_amx2_in3_port: port@25 {</div><div class='add'>+					reg = &lt;0x25&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_amx2_in3_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;amx2_in3_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_amx2_in4_port: port@26 {</div><div class='add'>+					reg = &lt;0x26&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_amx2_in4_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;amx2_in4_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@27 {</div><div class='add'>+					reg = &lt;0x27&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_amx2_out_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;amx2_out_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_adx1_in_port: port@28 {</div><div class='add'>+					reg = &lt;0x28&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_adx1_in_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;adx1_in_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@29 {</div><div class='add'>+					reg = &lt;0x29&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_adx1_out1_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;adx1_out1_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@2a {</div><div class='add'>+					reg = &lt;0x2a&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_adx1_out2_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;adx1_out2_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@2b {</div><div class='add'>+					reg = &lt;0x2b&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_adx1_out3_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;adx1_out3_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@2c {</div><div class='add'>+					reg = &lt;0x2c&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_adx1_out4_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;adx1_out4_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_adx2_in_port: port@2d {</div><div class='add'>+					reg = &lt;0x2d&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_adx2_in_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;adx2_in_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@2e {</div><div class='add'>+					reg = &lt;0x2e&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_adx2_out1_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;adx2_out1_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@2f {</div><div class='add'>+					reg = &lt;0x2f&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_adx2_out2_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;adx2_out2_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@30 {</div><div class='add'>+					reg = &lt;0x30&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_adx2_out3_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;adx2_out3_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@31 {</div><div class='add'>+					reg = &lt;0x31&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_adx2_out4_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;adx2_out4_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_mixer_in1_port: port@32 {</div><div class='add'>+					reg = &lt;0x32&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in1_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mixer_in1_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_mixer_in2_port: port@33 {</div><div class='add'>+					reg = &lt;0x33&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in2_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mixer_in2_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_mixer_in3_port: port@34 {</div><div class='add'>+					reg = &lt;0x34&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in3_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mixer_in3_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_mixer_in4_port: port@35 {</div><div class='add'>+					reg = &lt;0x35&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in4_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mixer_in4_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_mixer_in5_port: port@36 {</div><div class='add'>+					reg = &lt;0x36&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in5_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mixer_in5_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_mixer_in6_port: port@37 {</div><div class='add'>+					reg = &lt;0x37&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in6_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mixer_in6_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_mixer_in7_port: port@38 {</div><div class='add'>+					reg = &lt;0x38&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in7_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mixer_in7_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_mixer_in8_port: port@39 {</div><div class='add'>+					reg = &lt;0x39&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in8_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mixer_in8_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_mixer_in9_port: port@3a {</div><div class='add'>+					reg = &lt;0x3a&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in9_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mixer_in9_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_mixer_in10_port: port@3b {</div><div class='add'>+					reg = &lt;0x3b&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in10_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mixer_in10_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@3c {</div><div class='add'>+					reg = &lt;0x3c&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mixer_out1_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mixer_out1_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@3d {</div><div class='add'>+					reg = &lt;0x3d&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mixer_out2_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mixer_out2_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@3e {</div><div class='add'>+					reg = &lt;0x3e&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mixer_out3_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mixer_out3_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@3f {</div><div class='add'>+					reg = &lt;0x3f&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mixer_out4_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mixer_out4_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@40 {</div><div class='add'>+					reg = &lt;0x40&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mixer_out5_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mixer_out5_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_ope1_in_port: port@41 {</div><div class='add'>+					reg = &lt;0x41&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_ope1_in_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ope1_cif_in_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@42 {</div><div class='add'>+					reg = &lt;0x42&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_ope1_out_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ope1_cif_out_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_ope2_in_port: port@43 {</div><div class='add'>+					reg = &lt;0x43&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_ope2_in_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ope2_cif_in_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@44 {</div><div class='add'>+					reg = &lt;0x44&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_ope2_out_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ope2_cif_out_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dma-controller@702e2000 {</div><div class='ctx'> 			status = "okay";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		agic@702f9000 {</div><div class='add'>+		interrupt-controller@702f9000 {</div><div class='ctx'> 			status = "okay";</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "nvidia,tegra210-audio-graph-card";</div><div class='add'>+		status = "okay";</div><div class='add'>+</div><div class='add'>+		dais = /* FE */</div><div class='add'>+		       &lt;&amp;admaif1_port&gt;, &lt;&amp;admaif2_port&gt;, &lt;&amp;admaif3_port&gt;,</div><div class='add'>+		       &lt;&amp;admaif4_port&gt;, &lt;&amp;admaif5_port&gt;, &lt;&amp;admaif6_port&gt;,</div><div class='add'>+		       &lt;&amp;admaif7_port&gt;, &lt;&amp;admaif8_port&gt;, &lt;&amp;admaif9_port&gt;,</div><div class='add'>+		       &lt;&amp;admaif10_port&gt;,</div><div class='add'>+		       /* Router */</div><div class='add'>+		       &lt;&amp;xbar_i2s1_port&gt;, &lt;&amp;xbar_i2s2_port&gt;, &lt;&amp;xbar_i2s3_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_i2s4_port&gt;, &lt;&amp;xbar_i2s5_port&gt;, &lt;&amp;xbar_dmic1_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_dmic2_port&gt;, &lt;&amp;xbar_dmic3_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_sfc1_in_port&gt;, &lt;&amp;xbar_sfc2_in_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_sfc3_in_port&gt;, &lt;&amp;xbar_sfc4_in_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mvc1_in_port&gt;, &lt;&amp;xbar_mvc2_in_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx1_in1_port&gt;, &lt;&amp;xbar_amx1_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx1_in3_port&gt;, &lt;&amp;xbar_amx1_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx2_in1_port&gt;, &lt;&amp;xbar_amx2_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx2_in3_port&gt;, &lt;&amp;xbar_amx2_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_adx1_in_port&gt;, &lt;&amp;xbar_adx2_in_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mixer_in1_port&gt;, &lt;&amp;xbar_mixer_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mixer_in3_port&gt;, &lt;&amp;xbar_mixer_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mixer_in5_port&gt;, &lt;&amp;xbar_mixer_in6_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mixer_in7_port&gt;, &lt;&amp;xbar_mixer_in8_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mixer_in9_port&gt;, &lt;&amp;xbar_mixer_in10_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_ope1_in_port&gt;, &lt;&amp;xbar_ope2_in_port&gt;,</div><div class='add'>+		       /* HW accelerators */</div><div class='add'>+		       &lt;&amp;sfc1_out_port&gt;, &lt;&amp;sfc2_out_port&gt;,</div><div class='add'>+		       &lt;&amp;sfc3_out_port&gt;, &lt;&amp;sfc4_out_port&gt;,</div><div class='add'>+		       &lt;&amp;mvc1_out_port&gt;, &lt;&amp;mvc2_out_port&gt;,</div><div class='add'>+		       &lt;&amp;amx1_out_port&gt;, &lt;&amp;amx2_out_port&gt;,</div><div class='add'>+		       &lt;&amp;adx1_out1_port&gt;, &lt;&amp;adx1_out2_port&gt;,</div><div class='add'>+		       &lt;&amp;adx1_out3_port&gt;, &lt;&amp;adx1_out4_port&gt;,</div><div class='add'>+		       &lt;&amp;adx2_out1_port&gt;, &lt;&amp;adx2_out2_port&gt;,</div><div class='add'>+		       &lt;&amp;adx2_out3_port&gt;, &lt;&amp;adx2_out4_port&gt;,</div><div class='add'>+		       &lt;&amp;mixer_out1_port&gt;, &lt;&amp;mixer_out2_port&gt;,</div><div class='add'>+		       &lt;&amp;mixer_out3_port&gt;, &lt;&amp;mixer_out4_port&gt;,</div><div class='add'>+		       &lt;&amp;mixer_out5_port&gt;,</div><div class='add'>+		       &lt;&amp;ope1_out_port&gt;, &lt;&amp;ope2_out_port&gt;,</div><div class='add'>+		       /* I/O DAP Ports */</div><div class='add'>+		       &lt;&amp;i2s1_port&gt;, &lt;&amp;i2s2_port&gt;, &lt;&amp;i2s3_port&gt;, &lt;&amp;i2s4_port&gt;,</div><div class='add'>+		       &lt;&amp;i2s5_port&gt;, &lt;&amp;dmic1_port&gt;, &lt;&amp;dmic2_port&gt;, &lt;&amp;dmic3_port&gt;;</div><div class='add'>+</div><div class='add'>+		label = "NVIDIA Jetson TX1 APE";</div><div class='add'>+	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi<br/>index d0dc03923723..f0d53f0b4117 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi</a></div><div class='hunk'>@@ -14,13 +14,15 @@</div><div class='ctx'> 		stdout-path = "serial0:115200n8";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	memory {</div><div class='add'>+	memory@80000000 {</div><div class='ctx'> 		device_type = "memory";</div><div class='ctx'> 		reg = &lt;0x0 0x80000000 0x0 0xc0000000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	/* debug port */</div><div class='ctx'> 	serial@70006000 {</div><div class='add'>+		/delete-property/ dmas;</div><div class='add'>+		/delete-property/ dma-names;</div><div class='ctx'> 		status = "okay";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -34,23 +36,16 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	/* eMMC */</div><div class='del'>-	sdhci@700b0600 {</div><div class='add'>+	mmc@700b0600 {</div><div class='ctx'> 		status = "okay";</div><div class='ctx'> 		bus-width = &lt;8&gt;;</div><div class='ctx'> 		non-removable;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	clocks {</div><div class='del'>-		compatible = "simple-bus";</div><div class='del'>-		#address-cells = &lt;1&gt;;</div><div class='del'>-		#size-cells = &lt;0&gt;;</div><div class='del'>-</div><div class='del'>-		clk32k_in: clock@0 {</div><div class='del'>-			compatible = "fixed-clock";</div><div class='del'>-			reg = &lt;0&gt;;</div><div class='del'>-			#clock-cells = &lt;0&gt;;</div><div class='del'>-			clock-frequency = &lt;32768&gt;;</div><div class='del'>-		};</div><div class='add'>+	clk32k_in: clock-32k {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		clock-frequency = &lt;32768&gt;;</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	cpus {</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2595.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2595.dtsi<br/>index 6ae292da7294..65181da730fa 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra210-p2595.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra210-p2595.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra210-p2595.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/tegra210-p2595.dtsi</a></div><div class='hunk'>@@ -1,4 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: GPL-2.0</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/pinctrl/pinctrl-tegra.h&gt;</div><div class='add'>+</div><div class='ctx'> / {</div><div class='ctx'> 	model = "NVIDIA Tegra210 P2595 I/O board";</div><div class='ctx'> 	compatible = "nvidia,p2595", "nvidia,tegra210";</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi<br/>index 313a4c29d37a..4a64fe510f03 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi</a></div><div class='hunk'>@@ -1,5 +1,8 @@</div><div class='ctx'> // SPDX-License-Identifier: GPL-2.0</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/tegra-gpio.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/pinctrl-tegra.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	model = "NVIDIA Tegra210 P2597 I/O board";</div><div class='hunk'>@@ -14,11 +17,21 @@</div><div class='ctx'> 			status = "okay";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		vi@54080000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			csi@838 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				avdd-dsi-csi-supply = &lt;&amp;vdd_dsi_csi&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		sor@54580000 {</div><div class='ctx'> 			status = "okay";</div><div class='ctx'> </div><div class='del'>-			avdd-io-supply = &lt;&amp;avdd_1v05&gt;;</div><div class='del'>-			vdd-pll-supply = &lt;&amp;vdd_1v8&gt;;</div><div class='add'>+			avdd-io-hdmi-dp-supply = &lt;&amp;avdd_1v05&gt;;</div><div class='add'>+			vdd-hdmi-dp-pll-supply = &lt;&amp;vdd_1v8&gt;;</div><div class='ctx'> 			hdmi-supply = &lt;&amp;vdd_hdmi&gt;;</div><div class='ctx'> </div><div class='ctx'> 			nvidia,ddc-i2c-bus = &lt;&amp;hdmi_ddc&gt;;</div><div class='hunk'>@@ -1283,14 +1296,14 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		dvfs_pwm_active_state: dvfs_pwm_active {</div><div class='add'>+		dvfs_pwm_active_state: pinmux-dvfs-pwm-active {</div><div class='ctx'> 			dvfs_pwm_pbb1 {</div><div class='ctx'> 				nvidia,pins = "dvfs_pwm_pbb1";</div><div class='ctx'> 				nvidia,tristate = &lt;TEGRA_PIN_DISABLE&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		dvfs_pwm_inactive_state: dvfs_pwm_inactive {</div><div class='add'>+		dvfs_pwm_inactive_state: pinmux-dvfs-pwm-inactive {</div><div class='ctx'> 			dvfs_pwm_pbb1 {</div><div class='ctx'> 				nvidia,pins = "dvfs_pwm_pbb1";</div><div class='ctx'> 				nvidia,tristate = &lt;TEGRA_PIN_ENABLE&gt;;</div><div class='hunk'>@@ -1306,12 +1319,88 @@</div><div class='ctx'> 		status = "okay";</div><div class='ctx'> 		clock-frequency = &lt;100000&gt;;</div><div class='ctx'> </div><div class='add'>+		power-sensor@42 {</div><div class='add'>+			compatible = "ti,ina3221";</div><div class='add'>+			reg = &lt;0x42&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			input@0 {</div><div class='add'>+				reg = &lt;0x0&gt;;</div><div class='add'>+				label = "VDD_MUX";</div><div class='add'>+				shunt-resistor-micro-ohms = &lt;20000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			input@1 {</div><div class='add'>+				reg = &lt;0x1&gt;;</div><div class='add'>+				label = "VDD_5V_IO_SYS";</div><div class='add'>+				shunt-resistor-micro-ohms = &lt;5000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			input@2 {</div><div class='add'>+				reg = &lt;0x2&gt;;</div><div class='add'>+				label = "VDD_3V3_SYS";</div><div class='add'>+				shunt-resistor-micro-ohms = &lt;10000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		power-sensor@43 {</div><div class='add'>+			compatible = "ti,ina3221";</div><div class='add'>+			reg = &lt;0x43&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			input@0 {</div><div class='add'>+				reg = &lt;0x0&gt;;</div><div class='add'>+				label = "VDD_3V3_IO";</div><div class='add'>+				shunt-resistor-micro-ohms = &lt;10000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			input@1 {</div><div class='add'>+				reg = &lt;0x1&gt;;</div><div class='add'>+				label = "VDD_1V8_IO";</div><div class='add'>+				shunt-resistor-micro-ohms = &lt;10000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			input@2 {</div><div class='add'>+				reg = &lt;0x2&gt;;</div><div class='add'>+				label = "VDD_M2_IN";</div><div class='add'>+				shunt-resistor-micro-ohms = &lt;10000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		exp1: gpio@74 {</div><div class='ctx'> 			compatible = "ti,tca9539";</div><div class='ctx'> 			reg = &lt;0x74&gt;;</div><div class='ctx'> </div><div class='ctx'> 			#gpio-cells = &lt;2&gt;;</div><div class='ctx'> 			gpio-controller;</div><div class='add'>+</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio&gt;;</div><div class='add'>+			interrupts = &lt;TEGRA_GPIO(L, 1) IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;gpio_1v8&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		exp2: gpio@77 {</div><div class='add'>+			compatible = "ti,tca9539";</div><div class='add'>+			reg = &lt;0x77&gt;;</div><div class='add'>+</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio&gt;;</div><div class='add'>+			interrupts = &lt;TEGRA_GPIO(Z, 2) IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;gpio_1v8&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -1327,7 +1416,7 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	hda@70030000 {</div><div class='del'>-		nvidia,model = "jetson-tx1-hda";</div><div class='add'>+		nvidia,model = "NVIDIA Jetson TX1 HDA";</div><div class='ctx'> 		status = "okay";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -1343,11 +1432,6 @@</div><div class='ctx'> 		dvddio-pex-supply = &lt;&amp;vdd_pex_1v05&gt;;</div><div class='ctx'> 		hvddio-pex-supply = &lt;&amp;vdd_1v8&gt;;</div><div class='ctx'> 		avdd-usb-supply = &lt;&amp;vdd_3v3_sys&gt;;</div><div class='del'>-		/* XXX what are these? */</div><div class='del'>-		avdd-pll-utmip-supply = &lt;&amp;vdd_1v8&gt;;</div><div class='del'>-		avdd-pll-uerefe-supply = &lt;&amp;vdd_pex_1v05&gt;;</div><div class='del'>-		dvdd-usb-ss-pll-supply = &lt;&amp;vdd_pex_1v05&gt;;</div><div class='del'>-		hvdd-usb-ss-pll-e-supply = &lt;&amp;vdd_1v8&gt;;</div><div class='ctx'> </div><div class='ctx'> 		status = "okay";</div><div class='ctx'> </div><div class='hunk'>@@ -1355,6 +1439,7 @@</div><div class='ctx'> 		#size-cells = &lt;0&gt;;</div><div class='ctx'> </div><div class='ctx'> 		ethernet@1 {</div><div class='add'>+			compatible = "usb955,9ff";</div><div class='ctx'> 			reg = &lt;1&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='hunk'>@@ -1451,17 +1536,17 @@</div><div class='ctx'> 			usb2-0 {</div><div class='ctx'> 				status = "okay";</div><div class='ctx'> 				vbus-supply = &lt;&amp;vdd_usb_vbus_otg&gt;;</div><div class='add'>+				usb-role-switch;</div><div class='ctx'> 				mode = "otg";</div><div class='ctx'> </div><div class='del'>-				usb-role-switch;</div><div class='ctx'> 				connector {</div><div class='del'>-					compatible = "usb-b-connector",</div><div class='del'>-						     "gpio-usb-b-connector";</div><div class='add'>+					compatible = "gpio-usb-b-connector",</div><div class='add'>+						     "usb-b-connector";</div><div class='ctx'> 					label = "micro-USB";</div><div class='ctx'> 					type = "micro";</div><div class='del'>-					vbus-gpio = &lt;&amp;gpio TEGRA_GPIO(Z, 0)</div><div class='del'>-						     GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-					id-gpio = &lt;&amp;pmic 0 0&gt;;</div><div class='add'>+					vbus-gpios = &lt;&amp;gpio TEGRA_GPIO(Z, 0)</div><div class='add'>+						      GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+					id-gpios = &lt;&amp;pmic 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -1495,11 +1580,12 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	/* MMC/SD */</div><div class='del'>-	sdhci@700b0000 {</div><div class='add'>+	mmc@700b0000 {</div><div class='ctx'> 		status = "okay";</div><div class='ctx'> 		bus-width = &lt;4&gt;;</div><div class='ctx'> </div><div class='ctx'> 		cd-gpios = &lt;&amp;gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		wp-gpios = &lt;&amp;gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> </div><div class='ctx'> 		vqmmc-supply = &lt;&amp;vddio_sdmmc&gt;;</div><div class='ctx'> 		vmmc-supply = &lt;&amp;vdd_3v3_sd&gt;;</div><div class='hunk'>@@ -1513,173 +1599,258 @@</div><div class='ctx'> 		hvdd-usb-supply = &lt;&amp;vdd_1v8&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	regulators {</div><div class='del'>-		compatible = "simple-bus";</div><div class='del'>-		#address-cells = &lt;1&gt;;</div><div class='del'>-		#size-cells = &lt;0&gt;;</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		label = "gpio-keys";</div><div class='ctx'> </div><div class='del'>-		vdd_sys_mux: regulator@0 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;0&gt;;</div><div class='del'>-			regulator-name = "VDD_SYS_MUX";</div><div class='del'>-			regulator-min-microvolt = &lt;5000000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;5000000&gt;;</div><div class='del'>-			regulator-always-on;</div><div class='del'>-			regulator-boot-on;</div><div class='add'>+		key-power {</div><div class='add'>+			label = "Power";</div><div class='add'>+			gpios = &lt;&amp;gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+			wakeup-source;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		vdd_5v0_sys: regulator@1 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;1&gt;;</div><div class='del'>-			regulator-name = "VDD_5V0_SYS";</div><div class='del'>-			regulator-min-microvolt = &lt;5000000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;5000000&gt;;</div><div class='del'>-			regulator-always-on;</div><div class='del'>-			regulator-boot-on;</div><div class='del'>-			gpio = &lt;&amp;pmic 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			enable-active-high;</div><div class='del'>-			vin-supply = &lt;&amp;vdd_sys_mux&gt;;</div><div class='add'>+		key-volume-down {</div><div class='add'>+			label = "Volume Down";</div><div class='add'>+			gpios = &lt;&amp;gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		vdd_3v3_sys: regulator@2 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;2&gt;;</div><div class='del'>-			regulator-name = "VDD_3V3_SYS";</div><div class='del'>-			regulator-min-microvolt = &lt;3300000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;3300000&gt;;</div><div class='del'>-			regulator-always-on;</div><div class='del'>-			regulator-boot-on;</div><div class='del'>-			gpio = &lt;&amp;pmic 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			enable-active-high;</div><div class='del'>-			vin-supply = &lt;&amp;vdd_sys_mux&gt;;</div><div class='del'>-</div><div class='del'>-			regulator-enable-ramp-delay = &lt;160&gt;;</div><div class='del'>-			regulator-disable-ramp-delay = &lt;10000&gt;;</div><div class='add'>+		key-volume-up {</div><div class='add'>+			label = "Volume Up";</div><div class='add'>+			gpios = &lt;&amp;gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='ctx'> 		};</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		vdd_5v0_io: regulator@3 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;3&gt;;</div><div class='del'>-			regulator-name = "VDD_5V0_IO_SYS";</div><div class='del'>-			regulator-min-microvolt = &lt;5000000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;5000000&gt;;</div><div class='del'>-			regulator-always-on;</div><div class='del'>-			regulator-boot-on;</div><div class='del'>-		};</div><div class='add'>+	fan: pwm-fan {</div><div class='add'>+		compatible = "pwm-fan";</div><div class='add'>+		pwms = &lt;&amp;pwm 3 45334&gt;;</div><div class='add'>+		fan-supply = &lt;&amp;vdd_fan&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gpio&gt;;</div><div class='add'>+		interrupts = &lt;TEGRA_GPIO(K, 7) IRQ_TYPE_EDGE_RISING&gt;;</div><div class='ctx'> </div><div class='del'>-		vdd_3v3_sd: regulator@4 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;4&gt;;</div><div class='del'>-			regulator-name = "VDD_3V3_SD";</div><div class='del'>-			regulator-min-microvolt = &lt;3300000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;3300000&gt;;</div><div class='del'>-			gpio = &lt;&amp;gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			enable-active-high;</div><div class='del'>-			vin-supply = &lt;&amp;vdd_3v3_sys&gt;;</div><div class='del'>-</div><div class='del'>-			regulator-enable-ramp-delay = &lt;472&gt;;</div><div class='del'>-			regulator-disable-ramp-delay = &lt;4880&gt;;</div><div class='del'>-		};</div><div class='add'>+		/* cooling level (0, 1, 2, 3) - pwm inverted */</div><div class='add'>+		cooling-levels = &lt;255 128 64 0&gt;;</div><div class='add'>+		#cooling-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		vdd_dsi_csi: regulator@5 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;5&gt;;</div><div class='del'>-			regulator-name = "AVDD_DSI_CSI_1V2";</div><div class='del'>-			regulator-min-microvolt = &lt;1200000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;1200000&gt;;</div><div class='del'>-			vin-supply = &lt;&amp;vdd_sys_1v2&gt;;</div><div class='del'>-		};</div><div class='add'>+	vdd_sys_mux: regulator-vdd-sys-mux {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_SYS_MUX";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		vdd_3v3_dis: regulator@6 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;6&gt;;</div><div class='del'>-			regulator-name = "VDD_DIS_3V3_LCD";</div><div class='del'>-			regulator-min-microvolt = &lt;3300000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;3300000&gt;;</div><div class='del'>-			regulator-always-on;</div><div class='del'>-			gpio = &lt;&amp;exp1 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			enable-active-high;</div><div class='del'>-			vin-supply = &lt;&amp;vdd_3v3_sys&gt;;</div><div class='del'>-		};</div><div class='add'>+	vdd_5v0_sys: regulator-vdd-5v0-sys {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_5V0_SYS";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		gpio = &lt;&amp;pmic 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		vin-supply = &lt;&amp;vdd_sys_mux&gt;;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		vdd_1v8_dis: regulator@7 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;7&gt;;</div><div class='del'>-			regulator-name = "VDD_LCD_1V8_DIS";</div><div class='del'>-			regulator-min-microvolt = &lt;1800000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;1800000&gt;;</div><div class='del'>-			regulator-always-on;</div><div class='del'>-			gpio = &lt;&amp;exp1 14 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			enable-active-high;</div><div class='del'>-			vin-supply = &lt;&amp;vdd_1v8&gt;;</div><div class='del'>-		};</div><div class='add'>+	vdd_3v3_sys: regulator-vdd-3v3-sys {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_3V3_SYS";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		gpio = &lt;&amp;pmic 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		vin-supply = &lt;&amp;vdd_sys_mux&gt;;</div><div class='add'>+</div><div class='add'>+		regulator-enable-ramp-delay = &lt;160&gt;;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		vdd_5v0_rtl: regulator@8 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;8&gt;;</div><div class='del'>-			regulator-name = "RTL_5V";</div><div class='del'>-			regulator-min-microvolt = &lt;5000000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;5000000&gt;;</div><div class='del'>-			gpio = &lt;&amp;gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			enable-active-high;</div><div class='del'>-			vin-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='del'>-		};</div><div class='add'>+	vdd_5v0_io: regulator-vdd-5v0-io {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_5V0_IO_SYS";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		vdd_usb_vbus: regulator@9 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;9&gt;;</div><div class='del'>-			regulator-name = "USB_VBUS_EN1";</div><div class='del'>-			regulator-min-microvolt = &lt;5000000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;5000000&gt;;</div><div class='del'>-			gpio = &lt;&amp;gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			enable-active-high;</div><div class='del'>-			vin-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='del'>-		};</div><div class='add'>+	vdd_3v3_sd: regulator-vdd-3v3-sd {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_3V3_SD";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		vin-supply = &lt;&amp;vdd_3v3_sys&gt;;</div><div class='ctx'> </div><div class='del'>-		vdd_usb_vbus_otg: regulator@11 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;9&gt;;</div><div class='del'>-			regulator-name = "USB_VBUS_EN0";</div><div class='del'>-			regulator-min-microvolt = &lt;5000000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;5000000&gt;;</div><div class='del'>-			gpio = &lt;&amp;gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			enable-active-high;</div><div class='del'>-			vin-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='del'>-		};</div><div class='add'>+		regulator-enable-ramp-delay = &lt;472&gt;;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		vdd_hdmi: regulator@10 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;10&gt;;</div><div class='del'>-			regulator-name = "VDD_HDMI_5V0";</div><div class='del'>-			regulator-min-microvolt = &lt;5000000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;5000000&gt;;</div><div class='del'>-			gpio = &lt;&amp;exp1 12 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			enable-active-high;</div><div class='del'>-			vin-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='del'>-		};</div><div class='add'>+	vdd_dsi_csi: regulator-vdd-dsi-csi {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "AVDD_DSI_CSI_1V2";</div><div class='add'>+		regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vdd_sys_1v2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpio-keys {</div><div class='del'>-		compatible = "gpio-keys";</div><div class='del'>-		label = "gpio-keys";</div><div class='add'>+	vdd_3v3_dis: regulator-vdd-3v3-dis {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_DIS_3V3_LCD";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		gpio = &lt;&amp;exp1 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		vin-supply = &lt;&amp;vdd_3v3_sys&gt;;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		power {</div><div class='del'>-			label = "Power";</div><div class='del'>-			gpios = &lt;&amp;gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-			linux,code = &lt;KEY_POWER&gt;;</div><div class='del'>-			wakeup-source;</div><div class='del'>-		};</div><div class='add'>+	vdd_1v8_dis: regulator-vdd-1v8-dis {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_LCD_1V8_DIS";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		gpio = &lt;&amp;exp1 9 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		vin-supply = &lt;&amp;vdd_1v8&gt;;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		volume_down {</div><div class='del'>-			label = "Volume Down";</div><div class='del'>-			gpios = &lt;&amp;gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-			linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='del'>-		};</div><div class='add'>+	vdd_5v0_rtl: regulator-vdd-5v0-rtl {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "RTL_5V";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		vin-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		volume_up {</div><div class='del'>-			label = "Volume Up";</div><div class='del'>-			gpios = &lt;&amp;gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+	vdd_usb_vbus: regulator-vdd-usb-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "USB_VBUS_EN1";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		vin-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_hdmi: regulator-vdd-hdmi {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_HDMI_5V0";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;exp1 12 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		vin-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_cam_1v2: regulator-vdd-cam-1v2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vdd-cam-1v2";</div><div class='add'>+		regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+		gpio = &lt;&amp;exp2 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		vin-supply = &lt;&amp;vdd_3v3_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_cam_2v8: regulator-vdd-cam-2v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vdd-cam-2v8";</div><div class='add'>+		regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+		gpio = &lt;&amp;exp1 13 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		vin-supply = &lt;&amp;vdd_3v3_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_cam_1v8: regulator-vdd-cam-1v8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vdd-cam-1v8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		gpio = &lt;&amp;exp2 9 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		vin-supply = &lt;&amp;vdd_3v3_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_usb_vbus_otg: regulator-vdd-usb-vbus-otg {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "USB_VBUS_EN0";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		vin-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_fan: regulator-vdd-fan {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_FAN";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;exp1 4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+</div><div class='add'>+		regulator-enable-ramp-delay = &lt;284&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	thermal-zones {</div><div class='add'>+		cpu-thermal {</div><div class='add'>+			trips {</div><div class='add'>+				cpu_trip_critical: critical {</div><div class='add'>+					temperature = &lt;96500&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_trip_hot: hot {</div><div class='add'>+					temperature = &lt;70000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_trip_active: active {</div><div class='add'>+					temperature = &lt;50000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "active";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_trip_passive: passive {</div><div class='add'>+					temperature = &lt;30000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					cooling-device = &lt;&amp;fan 3 3&gt;;</div><div class='add'>+					trip = &lt;&amp;cpu_trip_critical&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				map1 {</div><div class='add'>+					cooling-device = &lt;&amp;fan 2 2&gt;;</div><div class='add'>+					trip = &lt;&amp;cpu_trip_hot&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				map2 {</div><div class='add'>+					cooling-device = &lt;&amp;fan 1 1&gt;;</div><div class='add'>+					trip = &lt;&amp;cpu_trip_active&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				map3 {</div><div class='add'>+					cooling-device = &lt;&amp;fan 0 0&gt;;</div><div class='add'>+					trip = &lt;&amp;cpu_trip_passive&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi<br/>index 88a4b9333d84..b84a8e39b404 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi</a></div><div class='hunk'>@@ -16,7 +16,7 @@</div><div class='ctx'> 		stdout-path = "serial0:115200n8";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	memory {</div><div class='add'>+	memory@80000000 {</div><div class='ctx'> 		device_type = "memory";</div><div class='ctx'> 		reg = &lt;0x0 0x80000000 0x0 0xc0000000&gt;;</div><div class='ctx'> 	};</div><div class='hunk'>@@ -1321,6 +1321,8 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	serial@70006000 {</div><div class='add'>+		/delete-property/ dmas;</div><div class='add'>+		/delete-property/ dma-names;</div><div class='ctx'> 		status = "okay";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -1328,7 +1330,7 @@</div><div class='ctx'> 		status = "okay";</div><div class='ctx'> 		clock-frequency = &lt;400000&gt;;</div><div class='ctx'> </div><div class='del'>-		max77620: max77620@3c {</div><div class='add'>+		pmic: pmic@3c {</div><div class='ctx'> 			compatible = "maxim,max77620";</div><div class='ctx'> 			reg = &lt;0x3c&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='hunk'>@@ -1342,13 +1344,41 @@</div><div class='ctx'> 			pinctrl-names = "default";</div><div class='ctx'> 			pinctrl-0 = &lt;&amp;max77620_default&gt;;</div><div class='ctx'> </div><div class='del'>-			max77620_default: pinmux@0 {</div><div class='del'>-				pin_gpio0 {</div><div class='add'>+			fps {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				fps0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					maxim,fps-event-source = &lt;MAX77620_FPS_EVENT_SRC_EN0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				fps1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					maxim,fps-event-source = &lt;MAX77620_FPS_EVENT_SRC_EN1&gt;;</div><div class='add'>+					maxim,device-state-on-disabled-event = &lt;MAX77620_FPS_INACTIVE_STATE_SLEEP&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				fps2 {</div><div class='add'>+					reg = &lt;2&gt;;</div><div class='add'>+					maxim,fps-event-source = &lt;MAX77620_FPS_EVENT_SRC_EN0&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			max77620-hog {</div><div class='add'>+				gpio-hog;</div><div class='add'>+				output-high;</div><div class='add'>+				gpios = &lt;2 GPIO_ACTIVE_HIGH&gt;,</div><div class='add'>+					&lt;7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			max77620_default: pinmux {</div><div class='add'>+				gpio0 {</div><div class='ctx'> 					pins = "gpio0";</div><div class='ctx'> 					function = "gpio";</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				pin_gpio1 {</div><div class='add'>+				gpio1 {</div><div class='ctx'> 					pins = "gpio1";</div><div class='ctx'> 					function = "fps-out";</div><div class='ctx'> 					drive-push-pull = &lt;1&gt;;</div><div class='hunk'>@@ -1357,58 +1387,30 @@</div><div class='ctx'> 					maxim,active-fps-power-down-slot = &lt;0&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				pin_gpio2_3 {</div><div class='del'>-					pins = "gpio2", "gpio3";</div><div class='add'>+				gpio2 {</div><div class='add'>+					pins = "gpio2";</div><div class='add'>+					function = "fps-out";</div><div class='add'>+					drive-open-drain = &lt;1&gt;;</div><div class='add'>+					maxim,active-fps-source = &lt;MAX77620_FPS_SRC_0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpio3 {</div><div class='add'>+					pins = "gpio3";</div><div class='ctx'> 					function = "fps-out";</div><div class='ctx'> 					drive-open-drain = &lt;1&gt;;</div><div class='ctx'> 					maxim,active-fps-source = &lt;MAX77620_FPS_SRC_0&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				pin_gpio4 {</div><div class='add'>+				gpio4 {</div><div class='ctx'> 					pins = "gpio4";</div><div class='ctx'> 					function = "32k-out1";</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				pin_gpio5_6_7 {</div><div class='add'>+				gpio5_6_7 {</div><div class='ctx'> 					pins = "gpio5", "gpio6", "gpio7";</div><div class='ctx'> 					function = "gpio";</div><div class='ctx'> 					drive-push-pull = &lt;1&gt;;</div><div class='ctx'> 				};</div><div class='del'>-</div><div class='del'>-				pin_gpio2 {</div><div class='del'>-					maxim,active-fps-source = &lt;MAX77620_FPS_SRC_0&gt;;</div><div class='del'>-				};</div><div class='del'>-</div><div class='del'>-				pin_gpio3 {</div><div class='del'>-					maxim,active-fps-source = &lt;MAX77620_FPS_SRC_0&gt;;</div><div class='del'>-				};</div><div class='del'>-			};</div><div class='del'>-</div><div class='del'>-			spmic-default-output-high {</div><div class='del'>-				gpio-hog;</div><div class='del'>-				output-high;</div><div class='del'>-				gpios = &lt;2 GPIO_ACTIVE_HIGH 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			};</div><div class='del'>-</div><div class='del'>-			fps {</div><div class='del'>-				#address-cells = &lt;1&gt;;</div><div class='del'>-				#size-cells = &lt;0&gt;;</div><div class='del'>-</div><div class='del'>-				fps0 {</div><div class='del'>-					reg = &lt;0&gt;;</div><div class='del'>-					maxim,fps-event-source = &lt;MAX77620_FPS_EVENT_SRC_EN0&gt;;</div><div class='del'>-				};</div><div class='del'>-</div><div class='del'>-				fps1 {</div><div class='del'>-					reg = &lt;1&gt;;</div><div class='del'>-					maxim,fps-event-source = &lt;MAX77620_FPS_EVENT_SRC_EN1&gt;;</div><div class='del'>-					maxim,device-state-on-disabled-event = &lt;MAX77620_FPS_INACTIVE_STATE_SLEEP&gt;;</div><div class='del'>-				};</div><div class='del'>-</div><div class='del'>-				fps2 {</div><div class='del'>-					reg = &lt;2&gt;;</div><div class='del'>-					maxim,fps-event-source = &lt;MAX77620_FPS_EVENT_SRC_EN0&gt;;</div><div class='del'>-				};</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			regulators {</div><div class='hunk'>@@ -1580,37 +1582,16 @@</div><div class='ctx'> 		status = "okay";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sdhci@700b0600 {</div><div class='add'>+	mmc@700b0600 {</div><div class='ctx'> 		bus-width = &lt;8&gt;;</div><div class='ctx'> 		non-removable;</div><div class='ctx'> 		status = "okay";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	clocks {</div><div class='del'>-		compatible = "simple-bus";</div><div class='del'>-		#address-cells = &lt;1&gt;;</div><div class='del'>-		#size-cells = &lt;0&gt;;</div><div class='del'>-</div><div class='del'>-		clk32k_in: clock@0 {</div><div class='del'>-			compatible = "fixed-clock";</div><div class='del'>-			reg = &lt;0&gt;;</div><div class='del'>-			#clock-cells = &lt;0&gt;;</div><div class='del'>-			clock-frequency = &lt;32768&gt;;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	gpio-keys {</div><div class='del'>-		compatible = "gpio-keys";</div><div class='del'>-		status = "okay";</div><div class='del'>-</div><div class='del'>-		power {</div><div class='del'>-			debounce-interval = &lt;30&gt;;</div><div class='del'>-			gpios = &lt;&amp;gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-			label = "Power";</div><div class='del'>-			linux,code = &lt;KEY_POWER&gt;;</div><div class='del'>-			wakeup-event-action = &lt;EV_ACT_ASSERTED&gt;;</div><div class='del'>-			wakeup-source;</div><div class='del'>-		};</div><div class='add'>+	clk32k_in: clock-32k {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		clock-frequency = &lt;32768&gt;;</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	cpus {</div><div class='hunk'>@@ -1637,228 +1618,217 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		status = "okay";</div><div class='add'>+</div><div class='add'>+		key-power {</div><div class='add'>+			debounce-interval = &lt;30&gt;;</div><div class='add'>+			gpios = &lt;&amp;gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			label = "Power";</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+			wakeup-event-action = &lt;EV_ACT_ASSERTED&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	psci {</div><div class='ctx'> 		compatible = "arm,psci-1.0";</div><div class='ctx'> 		method = "smc";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	regulators {</div><div class='del'>-		compatible = "simple-bus";</div><div class='del'>-		device_type = "fixed-regulators";</div><div class='del'>-		#address-cells = &lt;1&gt;;</div><div class='del'>-		#size-cells = &lt;0&gt;;</div><div class='del'>-</div><div class='del'>-		battery_reg: regulator@0 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;0&gt;;</div><div class='del'>-			regulator-name = "vdd-ac-bat";</div><div class='del'>-			regulator-min-microvolt = &lt;5000000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;5000000&gt;;</div><div class='del'>-			regulator-always-on;</div><div class='del'>-		};</div><div class='add'>+	battery_reg: regulator-vdd-ac-bat {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vdd-ac-bat";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		vdd_3v3: regulator@1 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;1&gt;;</div><div class='del'>-			regulator-name = "vdd-3v3";</div><div class='del'>-			regulator-enable-ramp-delay = &lt;160&gt;;</div><div class='del'>-			regulator-min-microvolt = &lt;3300000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;3300000&gt;;</div><div class='del'>-			regulator-always-on;</div><div class='del'>-</div><div class='del'>-			gpio = &lt;&amp;max77620 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			enable-active-high;</div><div class='del'>-		};</div><div class='add'>+	vdd_3v3: regulator-vdd-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vdd-3v3";</div><div class='add'>+		regulator-enable-ramp-delay = &lt;160&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='ctx'> </div><div class='del'>-		max77620_gpio7: regulator@2 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;2&gt;;</div><div class='del'>-			regulator-name = "max77620-gpio7";</div><div class='del'>-			regulator-enable-ramp-delay = &lt;240&gt;;</div><div class='del'>-			regulator-min-microvolt = &lt;1200000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;1200000&gt;;</div><div class='del'>-			vin-supply = &lt;&amp;max77620_ldo0&gt;;</div><div class='del'>-			regulator-always-on;</div><div class='del'>-			regulator-boot-on;</div><div class='del'>-</div><div class='del'>-			gpio = &lt;&amp;max77620 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			enable-active-high;</div><div class='del'>-		};</div><div class='add'>+		gpio = &lt;&amp;pmic 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		lcd_bl_en: regulator@3 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;3&gt;;</div><div class='del'>-			regulator-name = "lcd-bl-en";</div><div class='del'>-			regulator-min-microvolt = &lt;1800000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;1800000&gt;;</div><div class='del'>-			regulator-boot-on;</div><div class='add'>+	max77620_gpio7: regulator-max77620-gpio7 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "max77620-gpio7";</div><div class='add'>+		regulator-enable-ramp-delay = &lt;240&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;max77620_ldo0&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;pmic 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-			gpio = &lt;&amp;gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			enable-active-high;</div><div class='del'>-		};</div><div class='add'>+	lcd_bl_en: regulator-lcd-bl-en {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "lcd-bl-en";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='ctx'> </div><div class='del'>-		en_vdd_sd: regulator@4 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;4&gt;;</div><div class='del'>-			regulator-name = "en-vdd-sd";</div><div class='del'>-			regulator-enable-ramp-delay = &lt;472&gt;;</div><div class='del'>-			regulator-min-microvolt = &lt;3300000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;3300000&gt;;</div><div class='del'>-			vin-supply = &lt;&amp;vdd_3v3&gt;;</div><div class='del'>-</div><div class='del'>-			gpio = &lt;&amp;gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			enable-active-high;</div><div class='del'>-		};</div><div class='add'>+		gpio = &lt;&amp;gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		en_vdd_cam: regulator@5 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;5&gt;;</div><div class='del'>-			regulator-name = "en-vdd-cam";</div><div class='del'>-			regulator-min-microvolt = &lt;1800000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	en_vdd_sd: regulator-vdd-sd {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "en-vdd-sd";</div><div class='add'>+		regulator-enable-ramp-delay = &lt;472&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vdd_3v3&gt;;</div><div class='ctx'> </div><div class='del'>-			gpio = &lt;&amp;gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			enable-active-high;</div><div class='del'>-		};</div><div class='add'>+		gpio = &lt;&amp;gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		vdd_sys_boost: regulator@6 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;6&gt;;</div><div class='del'>-			regulator-name = "vdd-sys-boost";</div><div class='del'>-			regulator-enable-ramp-delay = &lt;3090&gt;;</div><div class='del'>-			regulator-min-microvolt = &lt;5000000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;5000000&gt;;</div><div class='del'>-			regulator-always-on;</div><div class='del'>-</div><div class='del'>-			gpio = &lt;&amp;max77620 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			enable-active-high;</div><div class='del'>-		};</div><div class='add'>+	en_vdd_cam: regulator-vdd-cam {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "en-vdd-cam";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='ctx'> </div><div class='del'>-		vdd_hdmi: regulator@7 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;7&gt;;</div><div class='del'>-			regulator-name = "vdd-hdmi";</div><div class='del'>-			regulator-enable-ramp-delay = &lt;468&gt;;</div><div class='del'>-			regulator-min-microvolt = &lt;5000000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;5000000&gt;;</div><div class='del'>-			vin-supply = &lt;&amp;vdd_sys_boost&gt;;</div><div class='del'>-			regulator-boot-on;</div><div class='del'>-</div><div class='del'>-			gpio = &lt;&amp;gpio TEGRA_GPIO(CC, 7) GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			enable-active-high;</div><div class='del'>-		};</div><div class='add'>+		gpio = &lt;&amp;gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		en_vdd_cpu_fixed: regulator@8 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;8&gt;;</div><div class='del'>-			regulator-name = "vdd-cpu-fixed";</div><div class='del'>-			regulator-min-microvolt = &lt;1000000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;1000000&gt;;</div><div class='del'>-		};</div><div class='add'>+	vdd_sys_boost: regulator-vdd-sys-boost {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vdd-sys-boost";</div><div class='add'>+		regulator-enable-ramp-delay = &lt;3090&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='ctx'> </div><div class='del'>-		vdd_aux_3v3: regulator@9 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;9&gt;;</div><div class='del'>-			regulator-name = "aux-3v3";</div><div class='del'>-			regulator-min-microvolt = &lt;3300000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;3300000&gt;;</div><div class='del'>-		};</div><div class='add'>+		gpio = &lt;&amp;pmic 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		vdd_snsr_pm: regulator@10 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;10&gt;;</div><div class='del'>-			regulator-name = "snsr_pm";</div><div class='del'>-			regulator-min-microvolt = &lt;3300000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	vdd_hdmi: regulator-vdd-hdmi {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vdd-hdmi";</div><div class='add'>+		regulator-enable-ramp-delay = &lt;468&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vdd_sys_boost&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;gpio TEGRA_GPIO(CC, 7) GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-			enable-active-high;</div><div class='del'>-		};</div><div class='add'>+	en_vdd_cpu_fixed: regulator-vdd-cpu-fixed {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vdd-cpu-fixed";</div><div class='add'>+		regulator-min-microvolt = &lt;1000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_aux_3v3: regulator-vdd-aux-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "aux-3v3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		vdd_usb_5v0: regulator@11 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;11&gt;;</div><div class='del'>-			status = "disabled";</div><div class='del'>-			regulator-name = "vdd-usb-5v0";</div><div class='del'>-			regulator-min-microvolt = &lt;5000000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;5000000&gt;;</div><div class='del'>-			vin-supply = &lt;&amp;vdd_3v3&gt;;</div><div class='add'>+	vdd_snsr_pm: regulator-vdd-snsr-pm {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "snsr_pm";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='ctx'> </div><div class='del'>-			enable-active-high;</div><div class='del'>-		};</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		vdd_cdc_1v2_aud: regulator@101 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;101&gt;;</div><div class='del'>-			status = "disabled";</div><div class='del'>-			regulator-name = "vdd_cdc_1v2_aud";</div><div class='del'>-			regulator-min-microvolt = &lt;1200000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;1200000&gt;;</div><div class='del'>-			startup-delay-us = &lt;250000&gt;;</div><div class='add'>+	vdd_usb_5v0: regulator-vdd-usb-5v0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		status = "disabled";</div><div class='add'>+		regulator-name = "vdd-usb-5v0";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vdd_3v3&gt;;</div><div class='ctx'> </div><div class='del'>-			enable-active-high;</div><div class='del'>-		};</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		vdd_disp_3v0: regulator@12 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;12&gt;;</div><div class='del'>-			regulator-name = "vdd-disp-3v0";</div><div class='del'>-			regulator-enable-ramp-delay = &lt;232&gt;;</div><div class='del'>-			regulator-min-microvolt = &lt;3000000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;3000000&gt;;</div><div class='del'>-			regulator-always-on;</div><div class='del'>-</div><div class='del'>-			gpio = &lt;&amp;gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			enable-active-high;</div><div class='del'>-		};</div><div class='add'>+	vdd_cdc_1v2_aud: regulator-vdd-cdc-1v2-aud {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		status = "disabled";</div><div class='add'>+		regulator-name = "vdd_cdc_1v2_aud";</div><div class='add'>+		regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+		startup-delay-us = &lt;250000&gt;;</div><div class='ctx'> </div><div class='del'>-		vdd_fan: regulator@13 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;13&gt;;</div><div class='del'>-			regulator-name = "vdd-fan";</div><div class='del'>-			regulator-enable-ramp-delay = &lt;284&gt;;</div><div class='del'>-			regulator-min-microvolt = &lt;5000000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-			gpio = &lt;&amp;gpio TEGRA_GPIO(E, 4) GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			enable-active-high;</div><div class='del'>-		};</div><div class='add'>+	vdd_disp_3v0: regulator-vdd-disp-3v0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vdd-disp-3v0";</div><div class='add'>+		regulator-enable-ramp-delay = &lt;232&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;3000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='ctx'> </div><div class='del'>-		usb_vbus1: regulator@14 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;14&gt;;</div><div class='del'>-			regulator-name = "usb-vbus1";</div><div class='del'>-			regulator-min-microvolt = &lt;5000000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-			gpio = &lt;&amp;gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			enable-active-high;</div><div class='del'>-			gpio-open-drain;</div><div class='del'>-		};</div><div class='add'>+	vdd_fan: regulator-vdd-fan {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vdd-fan";</div><div class='add'>+		regulator-enable-ramp-delay = &lt;284&gt;;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='ctx'> </div><div class='del'>-		usb_vbus2: regulator@15 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;15&gt;;</div><div class='del'>-			regulator-name = "usb-vbus2";</div><div class='del'>-			regulator-min-microvolt = &lt;5000000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio TEGRA_GPIO(E, 4) GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-			gpio = &lt;&amp;gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			enable-active-high;</div><div class='del'>-			gpio-open-drain;</div><div class='del'>-		};</div><div class='add'>+	usb_vbus1: regulator-usb-vbus1 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "usb-vbus1";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='ctx'> </div><div class='del'>-		vdd_3v3_eth: regulator@16 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;16&gt;;</div><div class='del'>-			regulator-name = "vdd-3v3-eth-a02";</div><div class='del'>-			regulator-min-microvolt = &lt;3300000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;3300000&gt;;</div><div class='del'>-			regulator-always-on;</div><div class='del'>-			regulator-boot-on;</div><div class='del'>-</div><div class='del'>-			gpio = &lt;&amp;gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			enable-active-high;</div><div class='del'>-			gpio-open-drain;</div><div class='del'>-		};</div><div class='add'>+		gpio = &lt;&amp;gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio-open-drain;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb_vbus2: regulator-usb-vbus2 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "usb-vbus2";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio-open-drain;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_3v3_eth: regulator-vdd-3v3-eth {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vdd-3v3-eth-a02";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio-open-drain;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts<br/>index 21ed1756b889..d78b9bd45df6 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts</a></div><div class='hunk'>@@ -22,7 +22,13 @@</div><div class='ctx'> 		stdout-path = "serial0:115200n8";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	memory {</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@80000000 {</div><div class='ctx'> 		device_type = "memory";</div><div class='ctx'> 		reg = &lt;0x0 0x80000000 0x1 0x0&gt;;</div><div class='ctx'> 	};</div><div class='hunk'>@@ -30,11 +36,8 @@</div><div class='ctx'> 	pcie@1003000 {</div><div class='ctx'> 		status = "okay";</div><div class='ctx'> </div><div class='del'>-		avdd-pll-uerefe-supply = &lt;&amp;vdd_pex_1v05&gt;;</div><div class='ctx'> 		hvddio-pex-supply = &lt;&amp;vdd_1v8&gt;;</div><div class='ctx'> 		dvddio-pex-supply = &lt;&amp;vdd_pex_1v05&gt;;</div><div class='del'>-		dvdd-pex-pll-supply = &lt;&amp;vdd_pex_1v05&gt;;</div><div class='del'>-		hvdd-pex-pll-e-supply = &lt;&amp;vdd_1v8&gt;;</div><div class='ctx'> 		vddio-pex-ctl-supply = &lt;&amp;vdd_1v8&gt;;</div><div class='ctx'> </div><div class='ctx'> 		pci@1,0 {</div><div class='hunk'>@@ -64,6 +67,16 @@</div><div class='ctx'> 			status = "okay";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		vi@54080000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			csi@838 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				avdd-dsi-csi-supply = &lt;&amp;vdd_sys_1v2&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		sor@54540000 {</div><div class='ctx'> 			status = "okay";</div><div class='ctx'> </div><div class='hunk'>@@ -77,8 +90,8 @@</div><div class='ctx'> 		sor@54580000 {</div><div class='ctx'> 			status = "okay";</div><div class='ctx'> </div><div class='del'>-			avdd-io-supply = &lt;&amp;avdd_1v05&gt;;</div><div class='del'>-			vdd-pll-supply = &lt;&amp;vdd_1v8&gt;;</div><div class='add'>+			avdd-io-hdmi-dp-supply = &lt;&amp;avdd_1v05&gt;;</div><div class='add'>+			vdd-hdmi-dp-pll-supply = &lt;&amp;vdd_1v8&gt;;</div><div class='ctx'> 			hdmi-supply = &lt;&amp;vdd_hdmi&gt;;</div><div class='ctx'> </div><div class='ctx'> 			nvidia,ddc-i2c-bus = &lt;&amp;hdmi_ddc&gt;;</div><div class='hunk'>@@ -90,6 +103,10 @@</div><div class='ctx'> 		dpaux@545c0000 {</div><div class='ctx'> 			status = "okay";</div><div class='ctx'> 		};</div><div class='add'>+</div><div class='add'>+		i2c@546c0000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	gpu@57000000 {</div><div class='hunk'>@@ -97,8 +114,26 @@</div><div class='ctx'> 		status = "okay";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	pinmux@700008d4 {</div><div class='add'>+		dvfs_pwm_active_state: pinmux-dvfs-pwm-active {</div><div class='add'>+			dvfs_pwm_pbb1 {</div><div class='add'>+				nvidia,pins = "dvfs_pwm_pbb1";</div><div class='add'>+				nvidia,tristate = &lt;TEGRA_PIN_DISABLE&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dvfs_pwm_inactive_state: pinmux-dvfs-pwm-inactive {</div><div class='add'>+			dvfs_pwm_pbb1 {</div><div class='add'>+				nvidia,pins = "dvfs_pwm_pbb1";</div><div class='add'>+				nvidia,tristate = &lt;TEGRA_PIN_ENABLE&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	/* debug port */</div><div class='ctx'> 	serial@70006000 {</div><div class='add'>+		/delete-property/ dmas;</div><div class='add'>+		/delete-property/ dma-names;</div><div class='ctx'> 		status = "okay";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -114,9 +149,10 @@</div><div class='ctx'> 			compatible = "atmel,24c02";</div><div class='ctx'> 			reg = &lt;0x50&gt;;</div><div class='ctx'> </div><div class='add'>+			label = "module";</div><div class='ctx'> 			vcc-supply = &lt;&amp;vdd_1v8&gt;;</div><div class='del'>-			address-bits = &lt;8&gt;;</div><div class='del'>-			page-size = &lt;8&gt;;</div><div class='add'>+			address-width = &lt;8&gt;;</div><div class='add'>+			pagesize = &lt;8&gt;;</div><div class='ctx'> 			size = &lt;256&gt;;</div><div class='ctx'> 			read-only;</div><div class='ctx'> 		};</div><div class='hunk'>@@ -125,9 +161,10 @@</div><div class='ctx'> 			compatible = "atmel,24c02";</div><div class='ctx'> 			reg = &lt;0x57&gt;;</div><div class='ctx'> </div><div class='add'>+			label = "system";</div><div class='ctx'> 			vcc-supply = &lt;&amp;vdd_1v8&gt;;</div><div class='del'>-			address-bits = &lt;8&gt;;</div><div class='del'>-			page-size = &lt;8&gt;;</div><div class='add'>+			address-width = &lt;8&gt;;</div><div class='add'>+			pagesize = &lt;8&gt;;</div><div class='ctx'> 			size = &lt;256&gt;;</div><div class='ctx'> 			read-only;</div><div class='ctx'> 		};</div><div class='hunk'>@@ -145,7 +182,8 @@</div><div class='ctx'> 		pmic: pmic@3c {</div><div class='ctx'> 			compatible = "maxim,max77620";</div><div class='ctx'> 			reg = &lt;0x3c&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;tegra_pmc&gt;;</div><div class='add'>+			interrupts = &lt;51 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='ctx'> </div><div class='ctx'> 			#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 			interrupt-controller;</div><div class='hunk'>@@ -156,6 +194,22 @@</div><div class='ctx'> 			pinctrl-names = "default";</div><div class='ctx'> 			pinctrl-0 = &lt;&amp;max77620_default&gt;;</div><div class='ctx'> </div><div class='add'>+			fps {</div><div class='add'>+				fps0 {</div><div class='add'>+					maxim,fps-event-source = &lt;MAX77620_FPS_EVENT_SRC_EN0&gt;;</div><div class='add'>+					maxim,suspend-fps-time-period-us = &lt;5120&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				fps1 {</div><div class='add'>+					maxim,fps-event-source = &lt;MAX77620_FPS_EVENT_SRC_EN1&gt;;</div><div class='add'>+					maxim,suspend-fps-time-period-us = &lt;5120&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				fps2 {</div><div class='add'>+					maxim,fps-event-source = &lt;MAX77620_FPS_EVENT_SRC_EN0&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='ctx'> 			max77620_default: pinmux {</div><div class='ctx'> 				gpio0 {</div><div class='ctx'> 					pins = "gpio0";</div><div class='hunk'>@@ -201,22 +255,6 @@</div><div class='ctx'> 				};</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			fps {</div><div class='del'>-				fps0 {</div><div class='del'>-					maxim,fps-event-source = &lt;MAX77620_FPS_EVENT_SRC_EN0&gt;;</div><div class='del'>-					maxim,suspend-fps-time-period-us = &lt;5120&gt;;</div><div class='del'>-				};</div><div class='del'>-</div><div class='del'>-				fps1 {</div><div class='del'>-					maxim,fps-event-source = &lt;MAX77620_FPS_EVENT_SRC_EN1&gt;;</div><div class='del'>-					maxim,suspend-fps-time-period-us = &lt;5120&gt;;</div><div class='del'>-				};</div><div class='del'>-</div><div class='del'>-				fps2 {</div><div class='del'>-					maxim,fps-event-source = &lt;MAX77620_FPS_EVENT_SRC_EN0&gt;;</div><div class='del'>-				};</div><div class='del'>-			};</div><div class='del'>-</div><div class='ctx'> 			regulators {</div><div class='ctx'> 				in-ldo0-1-supply = &lt;&amp;vdd_pre&gt;;</div><div class='ctx'> 				in-ldo2-supply = &lt;&amp;vdd_3v3_sys&gt;;</div><div class='hunk'>@@ -233,9 +271,7 @@</div><div class='ctx'> 					regulator-min-microvolt = &lt;1000000&gt;;</div><div class='ctx'> 					regulator-max-microvolt = &lt;1170000&gt;;</div><div class='ctx'> 					regulator-enable-ramp-delay = &lt;146&gt;;</div><div class='del'>-					regulator-disable-ramp-delay = &lt;4080&gt;;</div><div class='ctx'> 					regulator-ramp-delay = &lt;27500&gt;;</div><div class='del'>-					regulator-ramp-delay-scale = &lt;300&gt;;</div><div class='ctx'> 					regulator-always-on;</div><div class='ctx'> 					regulator-boot-on;</div><div class='ctx'> </div><div class='hunk'>@@ -249,9 +285,7 @@</div><div class='ctx'> 					regulator-min-microvolt = &lt;1150000&gt;;</div><div class='ctx'> 					regulator-max-microvolt = &lt;1150000&gt;;</div><div class='ctx'> 					regulator-enable-ramp-delay = &lt;176&gt;;</div><div class='del'>-					regulator-disable-ramp-delay = &lt;145800&gt;;</div><div class='ctx'> 					regulator-ramp-delay = &lt;27500&gt;;</div><div class='del'>-					regulator-ramp-delay-scale = &lt;300&gt;;</div><div class='ctx'> 					regulator-always-on;</div><div class='ctx'> 					regulator-boot-on;</div><div class='ctx'> </div><div class='hunk'>@@ -265,9 +299,7 @@</div><div class='ctx'> 					regulator-min-microvolt = &lt;1350000&gt;;</div><div class='ctx'> 					regulator-max-microvolt = &lt;1350000&gt;;</div><div class='ctx'> 					regulator-enable-ramp-delay = &lt;176&gt;;</div><div class='del'>-					regulator-disable-ramp-delay = &lt;32000&gt;;</div><div class='ctx'> 					regulator-ramp-delay = &lt;27500&gt;;</div><div class='del'>-					regulator-ramp-delay-scale = &lt;350&gt;;</div><div class='ctx'> 					regulator-always-on;</div><div class='ctx'> 					regulator-boot-on;</div><div class='ctx'> </div><div class='hunk'>@@ -281,9 +313,7 @@</div><div class='ctx'> 					regulator-min-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 					regulator-max-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 					regulator-enable-ramp-delay = &lt;242&gt;;</div><div class='del'>-					regulator-disable-ramp-delay = &lt;118000&gt;;</div><div class='ctx'> 					regulator-ramp-delay = &lt;27500&gt;;</div><div class='del'>-					regulator-ramp-delay-scale = &lt;360&gt;;</div><div class='ctx'> 					regulator-always-on;</div><div class='ctx'> 					regulator-boot-on;</div><div class='ctx'> </div><div class='hunk'>@@ -297,9 +327,7 @@</div><div class='ctx'> 					regulator-min-microvolt = &lt;1200000&gt;;</div><div class='ctx'> 					regulator-max-microvolt = &lt;1200000&gt;;</div><div class='ctx'> 					regulator-enable-ramp-delay = &lt;26&gt;;</div><div class='del'>-					regulator-disable-ramp-delay = &lt;626&gt;;</div><div class='ctx'> 					regulator-ramp-delay = &lt;100000&gt;;</div><div class='del'>-					regulator-ramp-delay-scale = &lt;200&gt;;</div><div class='ctx'> 					regulator-always-on;</div><div class='ctx'> 					regulator-boot-on;</div><div class='ctx'> </div><div class='hunk'>@@ -313,9 +341,7 @@</div><div class='ctx'> 					regulator-min-microvolt = &lt;1050000&gt;;</div><div class='ctx'> 					regulator-max-microvolt = &lt;1050000&gt;;</div><div class='ctx'> 					regulator-enable-ramp-delay = &lt;22&gt;;</div><div class='del'>-					regulator-disable-ramp-delay = &lt;650&gt;;</div><div class='ctx'> 					regulator-ramp-delay = &lt;100000&gt;;</div><div class='del'>-					regulator-ramp-delay-scale = &lt;200&gt;;</div><div class='ctx'> </div><div class='ctx'> 					maxim,active-fps-source = &lt;MAX77620_FPS_SRC_NONE&gt;;</div><div class='ctx'> 					maxim,active-fps-power-up-slot = &lt;0&gt;;</div><div class='hunk'>@@ -327,9 +353,7 @@</div><div class='ctx'> 					regulator-min-microvolt = &lt;1800000&gt;;</div><div class='ctx'> 					regulator-max-microvolt = &lt;3300000&gt;;</div><div class='ctx'> 					regulator-enable-ramp-delay = &lt;62&gt;;</div><div class='del'>-					regulator-disable-ramp-delay = &lt;650&gt;;</div><div class='ctx'> 					regulator-ramp-delay = &lt;100000&gt;;</div><div class='del'>-					regulator-ramp-delay-scale = &lt;200&gt;;</div><div class='ctx'> </div><div class='ctx'> 					maxim,active-fps-source = &lt;MAX77620_FPS_SRC_NONE&gt;;</div><div class='ctx'> 					maxim,active-fps-power-up-slot = &lt;0&gt;;</div><div class='hunk'>@@ -345,9 +369,7 @@</div><div class='ctx'> 					regulator-min-microvolt = &lt;850000&gt;;</div><div class='ctx'> 					regulator-max-microvolt = &lt;1100000&gt;;</div><div class='ctx'> 					regulator-enable-ramp-delay = &lt;22&gt;;</div><div class='del'>-					regulator-disable-ramp-delay = &lt;610&gt;;</div><div class='ctx'> 					regulator-ramp-delay = &lt;100000&gt;;</div><div class='del'>-					regulator-ramp-delay-scale = &lt;200&gt;;</div><div class='ctx'> 					regulator-disable-active-discharge;</div><div class='ctx'> 					regulator-always-on;</div><div class='ctx'> 					regulator-boot-on;</div><div class='hunk'>@@ -370,9 +392,7 @@</div><div class='ctx'> 					regulator-min-microvolt = &lt;1050000&gt;;</div><div class='ctx'> 					regulator-max-microvolt = &lt;1050000&gt;;</div><div class='ctx'> 					regulator-enable-ramp-delay = &lt;24&gt;;</div><div class='del'>-					regulator-disable-ramp-delay = &lt;2768&gt;;</div><div class='ctx'> 					regulator-ramp-delay = &lt;100000&gt;;</div><div class='del'>-					regulator-ramp-delay-scale = &lt;200&gt;;</div><div class='ctx'> </div><div class='ctx'> 					maxim,active-fps-source = &lt;MAX77620_FPS_SRC_1&gt;;</div><div class='ctx'> 					maxim,active-fps-power-up-slot = &lt;3&gt;;</div><div class='hunk'>@@ -384,9 +404,7 @@</div><div class='ctx'> 					regulator-min-microvolt = &lt;1050000&gt;;</div><div class='ctx'> 					regulator-max-microvolt = &lt;1050000&gt;;</div><div class='ctx'> 					regulator-enable-ramp-delay = &lt;22&gt;;</div><div class='del'>-					regulator-disable-ramp-delay = &lt;1160&gt;;</div><div class='ctx'> 					regulator-ramp-delay = &lt;100000&gt;;</div><div class='del'>-					regulator-ramp-delay-scale = &lt;200&gt;;</div><div class='ctx'> </div><div class='ctx'> 					maxim,active-fps-source = &lt;MAX77620_FPS_SRC_1&gt;;</div><div class='ctx'> 					maxim,active-fps-power-up-slot = &lt;6&gt;;</div><div class='hunk'>@@ -407,8 +425,14 @@</div><div class='ctx'> 		nvidia,sys-clock-req-active-high;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	cec@70015000 {</div><div class='add'>+		status = "okay";</div><div class='add'>+</div><div class='add'>+		hdmi-phandle = &lt;&amp;sor1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	hda@70030000 {</div><div class='del'>-		nvidia,model = "jetson-nano-hda";</div><div class='add'>+		nvidia,model = "NVIDIA Jetson Nano HDA";</div><div class='ctx'> </div><div class='ctx'> 		status = "okay";</div><div class='ctx'> 	};</div><div class='hunk'>@@ -423,11 +447,6 @@</div><div class='ctx'> 		avdd-usb-supply = &lt;&amp;vdd_3v3_sys&gt;;</div><div class='ctx'> 		dvddio-pex-supply = &lt;&amp;vdd_pex_1v05&gt;;</div><div class='ctx'> 		hvddio-pex-supply = &lt;&amp;vdd_1v8&gt;;</div><div class='del'>-		/* these really belong to the XUSB pad controller */</div><div class='del'>-		avdd-pll-utmip-supply = &lt;&amp;vdd_1v8&gt;;</div><div class='del'>-		avdd-pll-uerefe-supply = &lt;&amp;vdd_pex_1v05&gt;;</div><div class='del'>-		dvdd-usb-ss-pll-supply = &lt;&amp;vdd_pex_1v05&gt;;</div><div class='del'>-		hvdd-usb-ss-pll-e-supply = &lt;&amp;vdd_1v8&gt;;</div><div class='ctx'> </div><div class='ctx'> 		status = "okay";</div><div class='ctx'> 	};</div><div class='hunk'>@@ -507,16 +526,18 @@</div><div class='ctx'> 		ports {</div><div class='ctx'> 			usb2-0 {</div><div class='ctx'> 				status = "okay";</div><div class='del'>-				mode = "peripheral";</div><div class='del'>-</div><div class='add'>+				mode = "otg";</div><div class='ctx'> 				usb-role-switch;</div><div class='add'>+</div><div class='add'>+				vbus-supply = &lt;&amp;vdd_5v0_usb&gt;;</div><div class='add'>+</div><div class='ctx'> 				connector {</div><div class='del'>-					compatible = "usb-b-connector",</div><div class='del'>-						     "gpio-usb-b-connector";</div><div class='add'>+					compatible = "gpio-usb-b-connector",</div><div class='add'>+						     "usb-b-connector";</div><div class='ctx'> 					label = "micro-USB";</div><div class='ctx'> 					type = "micro";</div><div class='del'>-					vbus-gpio = &lt;&amp;gpio TEGRA_GPIO(CC, 4)</div><div class='del'>-						     GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+					vbus-gpios = &lt;&amp;gpio TEGRA_GPIO(CC, 4)</div><div class='add'>+						      GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -538,16 +559,30 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sdhci@700b0000 {</div><div class='add'>+	mmc@700b0000 {</div><div class='ctx'> 		status = "okay";</div><div class='ctx'> 		bus-width = &lt;4&gt;;</div><div class='ctx'> </div><div class='ctx'> 		cd-gpios = &lt;&amp;gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		disable-wp;</div><div class='ctx'> </div><div class='ctx'> 		vqmmc-supply = &lt;&amp;vddio_sdmmc&gt;;</div><div class='ctx'> 		vmmc-supply = &lt;&amp;vdd_3v3_sd&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	mmc@700b0400 {</div><div class='add'>+		status = "okay";</div><div class='add'>+		bus-width = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+		vqmmc-supply = &lt;&amp;vdd_1v8&gt;;</div><div class='add'>+		vmmc-supply = &lt;&amp;vdd_3v3_sys&gt;;</div><div class='add'>+</div><div class='add'>+		non-removable;</div><div class='add'>+		cap-sdio-irq;</div><div class='add'>+		keep-power-in-suspend;</div><div class='add'>+		wakeup-source;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	usb@700d0000 {</div><div class='ctx'> 		status = "okay";</div><div class='ctx'> 		phys = &lt;&amp;micro_b&gt;;</div><div class='hunk'>@@ -556,32 +591,1134 @@</div><div class='ctx'> 		hvdd-usb-supply = &lt;&amp;vdd_1v8&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sdhci@700b0400 {</div><div class='add'>+	clock@70110000 {</div><div class='ctx'> 		status = "okay";</div><div class='del'>-		bus-width = &lt;4&gt;;</div><div class='ctx'> </div><div class='del'>-		vqmmc-supply = &lt;&amp;vdd_1v8&gt;;</div><div class='del'>-		vmmc-supply = &lt;&amp;vdd_3v3_sys&gt;;</div><div class='add'>+		nvidia,cf = &lt;6&gt;;</div><div class='add'>+		nvidia,ci = &lt;0&gt;;</div><div class='add'>+		nvidia,cg = &lt;2&gt;;</div><div class='add'>+		nvidia,droop-ctrl = &lt;0x00000f00&gt;;</div><div class='add'>+		nvidia,force-mode = &lt;1&gt;;</div><div class='add'>+		nvidia,sample-rate = &lt;25000&gt;;</div><div class='add'>+</div><div class='add'>+		nvidia,pwm-min-microvolts = &lt;708000&gt;;</div><div class='add'>+		nvidia,pwm-period-nanoseconds = &lt;2500&gt;; /* 2.5us */</div><div class='add'>+		nvidia,pwm-to-pmic;</div><div class='add'>+		nvidia,pwm-tristate-microvolts = &lt;1000000&gt;;</div><div class='add'>+		nvidia,pwm-voltage-step-microvolts = &lt;19200&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable";</div><div class='add'>+		pinctrl-0 = &lt;&amp;dvfs_pwm_active_state&gt;;</div><div class='add'>+		pinctrl-1 = &lt;&amp;dvfs_pwm_inactive_state&gt;;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		non-removable;</div><div class='del'>-		cap-sdio-irq;</div><div class='del'>-		keep-power-in-suspend;</div><div class='del'>-		wakeup-source;</div><div class='add'>+	aconnect@702c0000 {</div><div class='add'>+		status = "okay";</div><div class='add'>+</div><div class='add'>+		ahub@702d0800 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			admaif@702d0000 {</div><div class='add'>+				status = "okay";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2s@702d1200 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						i2s3_cif_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_i2s3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					i2s3_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						i2s3_dap_ep: endpoint {</div><div class='add'>+							dai-format = "i2s";</div><div class='add'>+							/* Placeholder for external Codec */</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2s@702d1300 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						i2s4_cif_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_i2s4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					i2s4_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						i2s4_dap_ep: endpoint {</div><div class='add'>+							dai-format = "i2s";</div><div class='add'>+							/* Placeholder for external Codec */</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sfc@702d2000 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						sfc1_cif_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_sfc1_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					sfc1_out_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						sfc1_cif_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_sfc1_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sfc@702d2200 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						sfc2_cif_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_sfc2_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					sfc2_out_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						sfc2_cif_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_sfc2_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sfc@702d2400 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						sfc3_cif_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_sfc3_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					sfc3_out_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						sfc3_cif_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_sfc3_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sfc@702d2600 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						sfc4_cif_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_sfc4_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					sfc4_out_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						sfc4_cif_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_sfc4_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			amx@702d3000 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						amx1_in1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_amx1_in1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						amx1_in2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_amx1_in2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@2 {</div><div class='add'>+						reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+						amx1_in3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_amx1_in3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@3 {</div><div class='add'>+						reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+						amx1_in4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_amx1_in4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					amx1_out_port: port@4 {</div><div class='add'>+						reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+						amx1_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_amx1_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			amx@702d3100 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						amx2_in1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_amx2_in1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						amx2_in2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_amx2_in2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					amx2_in3_port: port@2 {</div><div class='add'>+						reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+						amx2_in3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_amx2_in3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					amx2_in4_port: port@3 {</div><div class='add'>+						reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+						amx2_in4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_amx2_in4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					amx2_out_port: port@4 {</div><div class='add'>+						reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+						amx2_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_amx2_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			adx@702d3800 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						adx1_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_adx1_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					adx1_out1_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						adx1_out1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_adx1_out1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					adx1_out2_port: port@2 {</div><div class='add'>+						reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+						adx1_out2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_adx1_out2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					adx1_out3_port: port@3 {</div><div class='add'>+						reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+						adx1_out3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_adx1_out3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					adx1_out4_port: port@4 {</div><div class='add'>+						reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+						adx1_out4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_adx1_out4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			adx@702d3900 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						adx2_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_adx2_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					adx2_out1_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						adx2_out1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_adx2_out1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					adx2_out2_port: port@2 {</div><div class='add'>+						reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+						adx2_out2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_adx2_out2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					adx2_out3_port: port@3 {</div><div class='add'>+						reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+						adx2_out3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_adx2_out3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					adx2_out4_port: port@4 {</div><div class='add'>+						reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+						adx2_out4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_adx2_out4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			dmic@702d4000 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						dmic1_cif_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_dmic1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					dmic1_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						dmic1_dap_ep: endpoint {</div><div class='add'>+							/* Placeholder for external Codec */</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			dmic@702d4100 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						dmic2_cif_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_dmic2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					dmic2_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						dmic2_dap_ep: endpoint {</div><div class='add'>+							/* Placeholder for external Codec */</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			processing-engine@702d8000 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0x0&gt;;</div><div class='add'>+</div><div class='add'>+						ope1_cif_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_ope1_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					ope1_out_port: port@1 {</div><div class='add'>+						reg = &lt;0x1&gt;;</div><div class='add'>+</div><div class='add'>+						ope1_cif_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_ope1_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			processing-engine@702d8400 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0x0&gt;;</div><div class='add'>+</div><div class='add'>+						ope2_cif_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_ope2_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					ope2_out_port: port@1 {</div><div class='add'>+						reg = &lt;0x1&gt;;</div><div class='add'>+</div><div class='add'>+						ope2_cif_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_ope2_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mvc@702da000 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						mvc1_cif_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mvc1_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					mvc1_out_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						mvc1_cif_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mvc1_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mvc@702da200 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						mvc2_cif_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mvc2_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					mvc2_out_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						mvc2_cif_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mvc2_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			amixer@702dbb00 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0x0&gt;;</div><div class='add'>+</div><div class='add'>+						mixer_in1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mixer_in1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;0x1&gt;;</div><div class='add'>+</div><div class='add'>+						mixer_in2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mixer_in2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@2 {</div><div class='add'>+						reg = &lt;0x2&gt;;</div><div class='add'>+</div><div class='add'>+						mixer_in3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mixer_in3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@3 {</div><div class='add'>+						reg = &lt;0x3&gt;;</div><div class='add'>+</div><div class='add'>+						mixer_in4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mixer_in4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@4 {</div><div class='add'>+						reg = &lt;0x4&gt;;</div><div class='add'>+</div><div class='add'>+						mixer_in5_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mixer_in5_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@5 {</div><div class='add'>+						reg = &lt;0x5&gt;;</div><div class='add'>+</div><div class='add'>+						mixer_in6_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mixer_in6_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@6 {</div><div class='add'>+						reg = &lt;0x6&gt;;</div><div class='add'>+</div><div class='add'>+						mixer_in7_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mixer_in7_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@7 {</div><div class='add'>+						reg = &lt;0x7&gt;;</div><div class='add'>+</div><div class='add'>+						mixer_in8_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mixer_in8_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@8 {</div><div class='add'>+						reg = &lt;0x8&gt;;</div><div class='add'>+</div><div class='add'>+						mixer_in9_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mixer_in9_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@9 {</div><div class='add'>+						reg = &lt;0x9&gt;;</div><div class='add'>+</div><div class='add'>+						mixer_in10_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mixer_in10_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					mixer_out1_port: port@a {</div><div class='add'>+						reg = &lt;0xa&gt;;</div><div class='add'>+</div><div class='add'>+						mixer_out1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mixer_out1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					mixer_out2_port: port@b {</div><div class='add'>+						reg = &lt;0xb&gt;;</div><div class='add'>+</div><div class='add'>+						mixer_out2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mixer_out2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					mixer_out3_port: port@c {</div><div class='add'>+						reg = &lt;0xc&gt;;</div><div class='add'>+</div><div class='add'>+						mixer_out3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mixer_out3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					mixer_out4_port: port@d {</div><div class='add'>+						reg = &lt;0xd&gt;;</div><div class='add'>+</div><div class='add'>+						mixer_out4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mixer_out4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					mixer_out5_port: port@e {</div><div class='add'>+						reg = &lt;0xe&gt;;</div><div class='add'>+</div><div class='add'>+						mixer_out5_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_mixer_out5_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				xbar_i2s3_port: port@c {</div><div class='add'>+					reg = &lt;0xc&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_i2s3_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;i2s3_cif_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_i2s4_port: port@d {</div><div class='add'>+					reg = &lt;0xd&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_i2s4_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;i2s4_cif_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_dmic1_port: port@f {</div><div class='add'>+					reg = &lt;0xf&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_dmic1_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dmic1_cif_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_dmic2_port: port@10 {</div><div class='add'>+					reg = &lt;0x10&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_dmic2_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dmic2_cif_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_sfc1_in_port: port@12 {</div><div class='add'>+					reg = &lt;0x12&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_sfc1_in_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;sfc1_cif_in_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@13 {</div><div class='add'>+					reg = &lt;0x13&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_sfc1_out_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;sfc1_cif_out_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_sfc2_in_port: port@14 {</div><div class='add'>+					reg = &lt;0x14&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_sfc2_in_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;sfc2_cif_in_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@15 {</div><div class='add'>+					reg = &lt;0x15&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_sfc2_out_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;sfc2_cif_out_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_sfc3_in_port: port@16 {</div><div class='add'>+					reg = &lt;0x16&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_sfc3_in_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;sfc3_cif_in_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@17 {</div><div class='add'>+					reg = &lt;0x17&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_sfc3_out_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;sfc3_cif_out_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_sfc4_in_port: port@18 {</div><div class='add'>+					reg = &lt;0x18&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_sfc4_in_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;sfc4_cif_in_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@19 {</div><div class='add'>+					reg = &lt;0x19&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_sfc4_out_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;sfc4_cif_out_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_mvc1_in_port: port@1a {</div><div class='add'>+					reg = &lt;0x1a&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mvc1_in_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mvc1_cif_in_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1b {</div><div class='add'>+					reg = &lt;0x1b&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mvc1_out_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mvc1_cif_out_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_mvc2_in_port: port@1c {</div><div class='add'>+					reg = &lt;0x1c&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mvc2_in_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mvc2_cif_in_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1d {</div><div class='add'>+					reg = &lt;0x1d&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mvc2_out_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mvc2_cif_out_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_amx1_in1_port: port@1e {</div><div class='add'>+					reg = &lt;0x1e&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_amx1_in1_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;amx1_in1_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_amx1_in2_port: port@1f {</div><div class='add'>+					reg = &lt;0x1f&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_amx1_in2_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;amx1_in2_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_amx1_in3_port: port@20 {</div><div class='add'>+					reg = &lt;0x20&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_amx1_in3_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;amx1_in3_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_amx1_in4_port: port@21 {</div><div class='add'>+					reg = &lt;0x21&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_amx1_in4_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;amx1_in4_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@22 {</div><div class='add'>+					reg = &lt;0x22&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_amx1_out_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;amx1_out_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_amx2_in1_port: port@23 {</div><div class='add'>+					reg = &lt;0x23&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_amx2_in1_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;amx2_in1_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_amx2_in2_port: port@24 {</div><div class='add'>+					reg = &lt;0x24&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_amx2_in2_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;amx2_in2_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_amx2_in3_port: port@25 {</div><div class='add'>+					reg = &lt;0x25&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_amx2_in3_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;amx2_in3_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_amx2_in4_port: port@26 {</div><div class='add'>+					reg = &lt;0x26&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_amx2_in4_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;amx2_in4_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@27 {</div><div class='add'>+					reg = &lt;0x27&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_amx2_out_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;amx2_out_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_adx1_in_port: port@28 {</div><div class='add'>+					reg = &lt;0x28&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_adx1_in_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;adx1_in_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@29 {</div><div class='add'>+					reg = &lt;0x29&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_adx1_out1_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;adx1_out1_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@2a {</div><div class='add'>+					reg = &lt;0x2a&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_adx1_out2_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;adx1_out2_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@2b {</div><div class='add'>+					reg = &lt;0x2b&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_adx1_out3_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;adx1_out3_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@2c {</div><div class='add'>+					reg = &lt;0x2c&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_adx1_out4_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;adx1_out4_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_adx2_in_port: port@2d {</div><div class='add'>+					reg = &lt;0x2d&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_adx2_in_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;adx2_in_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@2e {</div><div class='add'>+					reg = &lt;0x2e&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_adx2_out1_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;adx2_out1_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@2f {</div><div class='add'>+					reg = &lt;0x2f&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_adx2_out2_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;adx2_out2_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@30 {</div><div class='add'>+					reg = &lt;0x30&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_adx2_out3_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;adx2_out3_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@31 {</div><div class='add'>+					reg = &lt;0x31&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_adx2_out4_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;adx2_out4_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_mixer_in1_port: port@32 {</div><div class='add'>+					reg = &lt;0x32&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in1_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mixer_in1_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_mixer_in2_port: port@33 {</div><div class='add'>+					reg = &lt;0x33&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in2_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mixer_in2_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_mixer_in3_port: port@34 {</div><div class='add'>+					reg = &lt;0x34&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in3_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mixer_in3_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_mixer_in4_port: port@35 {</div><div class='add'>+					reg = &lt;0x35&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in4_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mixer_in4_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_mixer_in5_port: port@36 {</div><div class='add'>+					reg = &lt;0x36&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in5_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mixer_in5_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_mixer_in6_port: port@37 {</div><div class='add'>+					reg = &lt;0x37&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in6_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mixer_in6_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_mixer_in7_port: port@38 {</div><div class='add'>+					reg = &lt;0x38&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in7_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mixer_in7_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_mixer_in8_port: port@39 {</div><div class='add'>+					reg = &lt;0x39&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in8_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mixer_in8_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_mixer_in9_port: port@3a {</div><div class='add'>+					reg = &lt;0x3a&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in9_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mixer_in9_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_mixer_in10_port: port@3b {</div><div class='add'>+					reg = &lt;0x3b&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mixer_in10_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mixer_in10_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@3c {</div><div class='add'>+					reg = &lt;0x3c&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mixer_out1_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mixer_out1_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@3d {</div><div class='add'>+					reg = &lt;0x3d&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mixer_out2_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mixer_out2_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@3e {</div><div class='add'>+					reg = &lt;0x3e&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mixer_out3_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mixer_out3_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@3f {</div><div class='add'>+					reg = &lt;0x3f&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mixer_out4_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mixer_out4_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@40 {</div><div class='add'>+					reg = &lt;0x40&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_mixer_out5_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mixer_out5_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_ope1_in_port: port@41 {</div><div class='add'>+					reg = &lt;0x41&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_ope1_in_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ope1_cif_in_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@42 {</div><div class='add'>+					reg = &lt;0x42&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_ope1_out_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ope1_cif_out_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xbar_ope2_in_port: port@43 {</div><div class='add'>+					reg = &lt;0x43&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_ope2_in_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ope2_cif_in_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@44 {</div><div class='add'>+					reg = &lt;0x44&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_ope2_out_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ope2_cif_out_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dma-controller@702e2000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		interrupt-controller@702f9000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	clocks {</div><div class='del'>-		compatible = "simple-bus";</div><div class='del'>-		#address-cells = &lt;1&gt;;</div><div class='del'>-		#size-cells = &lt;0&gt;;</div><div class='add'>+	spi@70410000 {</div><div class='add'>+		status = "okay";</div><div class='ctx'> </div><div class='del'>-		clk32k_in: clock@0 {</div><div class='del'>-			compatible = "fixed-clock";</div><div class='add'>+		flash@0 {</div><div class='add'>+			compatible = "jedec,spi-nor";</div><div class='ctx'> 			reg = &lt;0&gt;;</div><div class='del'>-			#clock-cells = &lt;0&gt;;</div><div class='del'>-			clock-frequency = &lt;32768&gt;;</div><div class='add'>+			spi-max-frequency = &lt;104000000&gt;;</div><div class='add'>+			spi-tx-bus-width = &lt;2&gt;;</div><div class='add'>+			spi-rx-bus-width = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	clk32k_in: clock-32k {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		clock-frequency = &lt;32768&gt;;</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	cpus {</div><div class='ctx'> 		cpu@0 {</div><div class='ctx'> 			enable-method = "psci";</div><div class='hunk'>@@ -606,7 +1743,34 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	fan: fan {</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		key-force-recovery {</div><div class='add'>+			label = "Force Recovery";</div><div class='add'>+			gpios = &lt;&amp;gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,input-type = &lt;EV_KEY&gt;;</div><div class='add'>+			linux,code = &lt;BTN_1&gt;;</div><div class='add'>+			debounce-interval = &lt;30&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-power {</div><div class='add'>+			label = "Power";</div><div class='add'>+			gpios = &lt;&amp;gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,input-type = &lt;EV_KEY&gt;;</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+			debounce-interval = &lt;30&gt;;</div><div class='add'>+			wakeup-event-action = &lt;EV_ACT_ASSERTED&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-1.0";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fan: pwm-fan {</div><div class='ctx'> 		compatible = "pwm-fan";</div><div class='ctx'> 		pwms = &lt;&amp;pwm 3 45334&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -614,8 +1778,169 @@</div><div class='ctx'> 		#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	vdd_5v0_sys: regulator-vdd-5v0-sys {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+</div><div class='add'>+		regulator-name = "VDD_5V0_SYS";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_3v3_sys: regulator-vdd-3v3-sys {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+</div><div class='add'>+		regulator-name = "VDD_3V3_SYS";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-enable-ramp-delay = &lt;240&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;pmic 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+</div><div class='add'>+		vin-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_3v3_sd: regulator-vdd-3v3-sd {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+</div><div class='add'>+		regulator-name = "VDD_3V3_SD";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+</div><div class='add'>+		vin-supply = &lt;&amp;vdd_3v3_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_hdmi: regulator-vdd-hdmi-5v0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+</div><div class='add'>+		regulator-name = "VDD_HDMI_5V0";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+</div><div class='add'>+		vin-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_hub_3v3: regulator-vdd-hub-3v3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+</div><div class='add'>+		regulator-name = "VDD_HUB_3V3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;gpio TEGRA_GPIO(A, 6) GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+</div><div class='add'>+		vin-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_cpu: regulator-vdd-cpu {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+</div><div class='add'>+		regulator-name = "VDD_CPU";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;pmic 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+</div><div class='add'>+		vin-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_gpu: regulator-vdd-gpu {</div><div class='add'>+		compatible = "pwm-regulator";</div><div class='add'>+		pwms = &lt;&amp;pwm 1 8000&gt;;</div><div class='add'>+</div><div class='add'>+		regulator-name = "VDD_GPU";</div><div class='add'>+		regulator-min-microvolt = &lt;710000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1320000&gt;;</div><div class='add'>+		regulator-ramp-delay = &lt;80&gt;;</div><div class='add'>+		regulator-enable-ramp-delay = &lt;2000&gt;;</div><div class='add'>+		regulator-settling-time-us = &lt;160&gt;;</div><div class='add'>+</div><div class='add'>+		enable-gpios = &lt;&amp;pmic 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	avdd_io_edp_1v05: regulator-avdd-io-epd-1v05 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+</div><div class='add'>+		regulator-name = "AVDD_IO_EDP_1V05";</div><div class='add'>+		regulator-min-microvolt = &lt;1050000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1050000&gt;;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;pmic 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+</div><div class='add'>+		vin-supply = &lt;&amp;avdd_1v05_pll&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_5v0_usb: regulator-vdd-5v-usb {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+</div><div class='add'>+		regulator-name = "VDD_5V_USB";</div><div class='add'>+		regulator-min-microvolt = &lt;50000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;50000000&gt;;</div><div class='add'>+</div><div class='add'>+		vin-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "nvidia,tegra210-audio-graph-card";</div><div class='add'>+		status = "okay";</div><div class='add'>+</div><div class='add'>+		dais = /* FE */</div><div class='add'>+		       &lt;&amp;admaif1_port&gt;, &lt;&amp;admaif2_port&gt;, &lt;&amp;admaif3_port&gt;,</div><div class='add'>+		       &lt;&amp;admaif4_port&gt;, &lt;&amp;admaif5_port&gt;, &lt;&amp;admaif6_port&gt;,</div><div class='add'>+		       &lt;&amp;admaif7_port&gt;, &lt;&amp;admaif8_port&gt;, &lt;&amp;admaif9_port&gt;,</div><div class='add'>+		       &lt;&amp;admaif10_port&gt;,</div><div class='add'>+		       /* Router */</div><div class='add'>+		       &lt;&amp;xbar_i2s3_port&gt;, &lt;&amp;xbar_i2s4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_dmic1_port&gt;, &lt;&amp;xbar_dmic2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_sfc1_in_port&gt;, &lt;&amp;xbar_sfc2_in_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_sfc3_in_port&gt;, &lt;&amp;xbar_sfc4_in_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mvc1_in_port&gt;, &lt;&amp;xbar_mvc2_in_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx1_in1_port&gt;, &lt;&amp;xbar_amx1_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx1_in3_port&gt;, &lt;&amp;xbar_amx1_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx2_in1_port&gt;, &lt;&amp;xbar_amx2_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx2_in3_port&gt;, &lt;&amp;xbar_amx2_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_adx1_in_port&gt;, &lt;&amp;xbar_adx2_in_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mixer_in1_port&gt;, &lt;&amp;xbar_mixer_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mixer_in3_port&gt;, &lt;&amp;xbar_mixer_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mixer_in5_port&gt;, &lt;&amp;xbar_mixer_in6_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mixer_in7_port&gt;, &lt;&amp;xbar_mixer_in8_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mixer_in9_port&gt;, &lt;&amp;xbar_mixer_in10_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_ope1_in_port&gt;, &lt;&amp;xbar_ope2_in_port&gt;,</div><div class='add'>+		       /* HW accelerators */</div><div class='add'>+		       &lt;&amp;sfc1_out_port&gt;, &lt;&amp;sfc2_out_port&gt;,</div><div class='add'>+		       &lt;&amp;sfc3_out_port&gt;, &lt;&amp;sfc4_out_port&gt;,</div><div class='add'>+		       &lt;&amp;mvc1_out_port&gt;, &lt;&amp;mvc2_out_port&gt;,</div><div class='add'>+		       &lt;&amp;amx1_out_port&gt;, &lt;&amp;amx2_out_port&gt;,</div><div class='add'>+		       &lt;&amp;adx1_out1_port&gt;, &lt;&amp;adx1_out2_port&gt;,</div><div class='add'>+		       &lt;&amp;adx1_out3_port&gt;, &lt;&amp;adx1_out4_port&gt;,</div><div class='add'>+		       &lt;&amp;adx2_out1_port&gt;, &lt;&amp;adx2_out2_port&gt;,</div><div class='add'>+		       &lt;&amp;adx2_out3_port&gt;, &lt;&amp;adx2_out4_port&gt;,</div><div class='add'>+		       &lt;&amp;mixer_out1_port&gt;, &lt;&amp;mixer_out2_port&gt;,</div><div class='add'>+		       &lt;&amp;mixer_out3_port&gt;, &lt;&amp;mixer_out4_port&gt;,</div><div class='add'>+		       &lt;&amp;mixer_out5_port&gt;,</div><div class='add'>+		       &lt;&amp;ope1_out_port&gt;, &lt;&amp;ope2_out_port&gt;,</div><div class='add'>+		       /* I/O DAP Ports */</div><div class='add'>+		       &lt;&amp;i2s3_port&gt;, &lt;&amp;i2s4_port&gt;,</div><div class='add'>+		       &lt;&amp;dmic1_port&gt;, &lt;&amp;dmic2_port&gt;;</div><div class='add'>+</div><div class='add'>+		label = "NVIDIA Jetson Nano APE";</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	thermal-zones {</div><div class='del'>-		cpu {</div><div class='add'>+		cpu-thermal {</div><div class='ctx'> 			trips {</div><div class='ctx'> 				cpu_trip_critical: critical {</div><div class='ctx'> 					temperature = &lt;96500&gt;;</div><div class='hunk'>@@ -665,148 +1990,4 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='del'>-</div><div class='del'>-	gpio-keys {</div><div class='del'>-		compatible = "gpio-keys";</div><div class='del'>-</div><div class='del'>-		power {</div><div class='del'>-			label = "Power";</div><div class='del'>-			gpios = &lt;&amp;gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-			linux,input-type = &lt;EV_KEY&gt;;</div><div class='del'>-			linux,code = &lt;KEY_POWER&gt;;</div><div class='del'>-			debounce-interval = &lt;30&gt;;</div><div class='del'>-			wakeup-event-action = &lt;EV_ACT_ASSERTED&gt;;</div><div class='del'>-			wakeup-source;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		force-recovery {</div><div class='del'>-			label = "Force Recovery";</div><div class='del'>-			gpios = &lt;&amp;gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-			linux,input-type = &lt;EV_KEY&gt;;</div><div class='del'>-			linux,code = &lt;BTN_1&gt;;</div><div class='del'>-			debounce-interval = &lt;30&gt;;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	psci {</div><div class='del'>-		compatible = "arm,psci-1.0";</div><div class='del'>-		method = "smc";</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	regulators {</div><div class='del'>-		compatible = "simple-bus";</div><div class='del'>-		#address-cells = &lt;1&gt;;</div><div class='del'>-		#size-cells = &lt;0&gt;;</div><div class='del'>-</div><div class='del'>-		vdd_5v0_sys: regulator@0 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;0&gt;;</div><div class='del'>-</div><div class='del'>-			regulator-name = "VDD_5V0_SYS";</div><div class='del'>-			regulator-min-microvolt = &lt;5000000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;5000000&gt;;</div><div class='del'>-			regulator-always-on;</div><div class='del'>-			regulator-boot-on;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		vdd_3v3_sys: regulator@1 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;1&gt;;</div><div class='del'>-			regulator-name = "VDD_3V3_SYS";</div><div class='del'>-			regulator-min-microvolt = &lt;3300000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;3300000&gt;;</div><div class='del'>-			regulator-enable-ramp-delay = &lt;240&gt;;</div><div class='del'>-			regulator-disable-ramp-delay = &lt;11340&gt;;</div><div class='del'>-			regulator-always-on;</div><div class='del'>-			regulator-boot-on;</div><div class='del'>-</div><div class='del'>-			gpio = &lt;&amp;pmic 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			enable-active-high;</div><div class='del'>-</div><div class='del'>-			vin-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		vdd_3v3_sd: regulator@2 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;2&gt;;</div><div class='del'>-</div><div class='del'>-			regulator-name = "VDD_3V3_SD";</div><div class='del'>-			regulator-min-microvolt = &lt;3300000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;3300000&gt;;</div><div class='del'>-</div><div class='del'>-			gpio = &lt;&amp;gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			enable-active-high;</div><div class='del'>-</div><div class='del'>-			vin-supply = &lt;&amp;vdd_3v3_sys&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		vdd_hdmi: regulator@3 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;3&gt;;</div><div class='del'>-</div><div class='del'>-			regulator-name = "VDD_HDMI_5V0";</div><div class='del'>-			regulator-min-microvolt = &lt;5000000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;5000000&gt;;</div><div class='del'>-</div><div class='del'>-			vin-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		vdd_hub_3v3: regulator@4 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;4&gt;;</div><div class='del'>-</div><div class='del'>-			regulator-name = "VDD_HUB_3V3";</div><div class='del'>-			regulator-min-microvolt = &lt;3300000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;3300000&gt;;</div><div class='del'>-</div><div class='del'>-			gpio = &lt;&amp;gpio TEGRA_GPIO(A, 6) GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			enable-active-high;</div><div class='del'>-</div><div class='del'>-			vin-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		vdd_cpu: regulator@5 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;5&gt;;</div><div class='del'>-</div><div class='del'>-			regulator-name = "VDD_CPU";</div><div class='del'>-			regulator-min-microvolt = &lt;5000000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;5000000&gt;;</div><div class='del'>-			regulator-always-on;</div><div class='del'>-			regulator-boot-on;</div><div class='del'>-</div><div class='del'>-			gpio = &lt;&amp;pmic 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			enable-active-high;</div><div class='del'>-</div><div class='del'>-			vin-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		vdd_gpu: regulator@6 {</div><div class='del'>-			compatible = "pwm-regulator";</div><div class='del'>-			reg = &lt;6&gt;;</div><div class='del'>-			pwms = &lt;&amp;pwm 1 4880&gt;;</div><div class='del'>-			regulator-name = "VDD_GPU";</div><div class='del'>-			regulator-min-microvolt = &lt;710000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;1320000&gt;;</div><div class='del'>-			regulator-ramp-delay = &lt;80&gt;;</div><div class='del'>-			regulator-enable-ramp-delay = &lt;2000&gt;;</div><div class='del'>-			regulator-settling-time-us = &lt;160&gt;;</div><div class='del'>-			enable-gpios = &lt;&amp;pmic 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			vin-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		avdd_io_edp_1v05: regulator@7 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;7&gt;;</div><div class='del'>-</div><div class='del'>-			regulator-name = "AVDD_IO_EDP_1V05";</div><div class='del'>-			regulator-min-microvolt = &lt;1050000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;1050000&gt;;</div><div class='del'>-</div><div class='del'>-			gpio = &lt;&amp;pmic 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-			enable-active-high;</div><div class='del'>-</div><div class='del'>-			vin-supply = &lt;&amp;avdd_1v05_pll&gt;;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3541-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3541-0000.dts<br/>new file mode 100644<br/>index 000000000000..b86e271dde0b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra210-p3541-0000.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/tegra210-p3541-0000.dts</a></div><div class='hunk'>@@ -0,0 +1,59 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "tegra210-p3450-0000.dts"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "NVIDIA Jetson Nano 2GB Developer Kit";</div><div class='add'>+	compatible = "nvidia,p3541-0000", "nvidia,p3450-0000", "nvidia,tegra210";</div><div class='add'>+</div><div class='add'>+	memory@80000000 {</div><div class='add'>+		reg = &lt;0x0 0x80000000 0x0 0x80000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	host1x@50000000 {</div><div class='add'>+		sor@54540000 {</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dpaux@545c0000 {</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	padctl@7009f000 {</div><div class='add'>+		ports {</div><div class='add'>+			usb2-1 {</div><div class='add'>+				vbus-supply = &lt;&amp;vdd_hub_5v0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			usb2-2 {</div><div class='add'>+				vbus-supply = &lt;&amp;vdd_hub_5v0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			usb3-0 {</div><div class='add'>+				/delete-property/ vbus-supply;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	regulator-vdd-hdmi-5v0 {</div><div class='add'>+		gpio = &lt;&amp;gpio TEGRA_GPIO(A, 6) GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/delete-node/ regulator-vdd-hub-3v3;</div><div class='add'>+</div><div class='add'>+	vdd_hub_5v0: regulator-vdd-hub-5v0 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+</div><div class='add'>+		regulator-name = "VDD_HUB_5V0";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;gpio TEGRA_GPIO(I, 2) GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+</div><div class='add'>+		vin-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/tegra210-peripherals-opp.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-peripherals-opp.dtsi<br/>new file mode 100644<br/>index 000000000000..bf2527d73793<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra210-peripherals-opp.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/tegra210-peripherals-opp.dtsi</a></div><div class='hunk'>@@ -0,0 +1,135 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	/* EMC DVFS OPP table */</div><div class='add'>+	emc_icc_dvfs_opp_table: opp-table-dvfs0 {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		opp-40800000-800 {</div><div class='add'>+			opp-microvolt = &lt;800000 800000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;40800000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0003&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-68000000-800 {</div><div class='add'>+			opp-microvolt = &lt;800000 800000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;68000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0003&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-102000000-800 {</div><div class='add'>+			opp-microvolt = &lt;800000 800000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;102000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0003&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-204000000-800 {</div><div class='add'>+			opp-microvolt = &lt;800000 800000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;204000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0007&gt;;</div><div class='add'>+			opp-suspend;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-408000000-812 {</div><div class='add'>+			opp-microvolt = &lt;812000 812000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;408000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0003&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-665600000-825 {</div><div class='add'>+			opp-microvolt = &lt;825000 825000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;665600000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0003&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-800000000-825 {</div><div class='add'>+			opp-microvolt = &lt;825000 825000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;800000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0003&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1065600000-837 {</div><div class='add'>+			opp-microvolt = &lt;837000 837000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1065600000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0003&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1331200000-850 {</div><div class='add'>+			opp-microvolt = &lt;850000 850000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1331200000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0003&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1600000000-887 {</div><div class='add'>+			opp-microvolt = &lt;887000 887000 1150000&gt;;</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1600000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0007&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* EMC bandwidth OPP table */</div><div class='add'>+	emc_bw_dfs_opp_table: opp-table-dvfs1 {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		opp-40800000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;40800000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0003&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;652800&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-68000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;68000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0003&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;1088000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-102000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;102000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0003&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;1632000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-204000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;204000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0007&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;3264000&gt;;</div><div class='add'>+			opp-suspend;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-408000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;408000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0003&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;6528000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-665600000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;665600000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0003&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;10649600&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-800000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;800000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x001F&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;12800000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1065600000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1065600000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0003&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;17049600&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1331200000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1331200000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0003&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;21299200&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1600000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1600000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x0007&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;25600000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts<br/>index 2faab6390552..5aa6afd56cbc 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra210-smaug.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/tegra210-smaug.dts</a></div><div class='hunk'>@@ -17,6 +17,7 @@</div><div class='ctx'> </div><div class='ctx'> 	aliases {</div><div class='ctx'> 		serial0 = &amp;uarta;</div><div class='add'>+		serial3 = &amp;uartd;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	chosen {</div><div class='hunk'>@@ -24,17 +25,49 @@</div><div class='ctx'> 		stdout-path = "serial0:115200n8";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	memory {</div><div class='add'>+	memory@80000000 {</div><div class='ctx'> 		device_type = "memory";</div><div class='ctx'> 		reg = &lt;0x0 0x80000000 0x0 0xc0000000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	host1x@50000000 {</div><div class='add'>+		dsia: dsi@54300000 {</div><div class='add'>+			avdd-dsi-csi-supply = &lt;&amp;vdd_dsi_csi&gt;;</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			link2: panel@0 {</div><div class='add'>+				compatible = "jdi,lpm102a188a";</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dsib: dsi@54400000 {</div><div class='add'>+			avdd-dsi-csi-supply = &lt;&amp;vdd_dsi_csi&gt;;</div><div class='add'>+			nvidia,ganged-mode = &lt;&amp;dsia&gt;;</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			link1: panel@0 {</div><div class='add'>+				compatible = "jdi,lpm102a188a";</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				power-supply = &lt;&amp;pplcd_vdd&gt;;</div><div class='add'>+				ddi-supply = &lt;&amp;pp1800_lcdio&gt;;</div><div class='add'>+				enable-gpios = &lt;&amp;gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+				reset-gpios = &lt;&amp;gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+				link2 = &lt;&amp;link2&gt;;</div><div class='add'>+				backlight = &lt;&amp;backlight&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		dpaux: dpaux@545c0000 {</div><div class='ctx'> 			status = "okay";</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	gpu@57000000 {</div><div class='add'>+		vdd-supply = &lt;&amp;max77621_gpu&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	pinmux: pinmux@700008d4 {</div><div class='ctx'> 		pinctrl-names = "boot";</div><div class='ctx'> 		pinctrl-0 = &lt;&amp;state_boot&gt;;</div><div class='hunk'>@@ -1306,9 +1339,42 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	serial@70006000 {</div><div class='add'>+		/delete-property/ dmas;</div><div class='add'>+		/delete-property/ dma-names;</div><div class='ctx'> 		status = "okay";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	uartd: serial@70006300 {</div><div class='add'>+		compatible = "nvidia,tegra30-hsuart";</div><div class='add'>+		reset-names = "serial";</div><div class='add'>+		/delete-property/ reg-shift;</div><div class='add'>+		status = "okay";</div><div class='add'>+</div><div class='add'>+		bluetooth {</div><div class='add'>+			compatible = "brcm,bcm43540-bt";</div><div class='add'>+			max-speed = &lt;4000000&gt;;</div><div class='add'>+			brcm,bt-pcm-int-params = [01 02 00 01 01];</div><div class='add'>+			device-wakeup-gpios = &lt;&amp;gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			shutdown-gpios = &lt;&amp;gpio TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio&gt;;</div><div class='add'>+			interrupts = &lt;TEGRA_GPIO(H, 5) IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			interrupt-names = "host-wakeup";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c@7000c000 {</div><div class='add'>+		status = "okay";</div><div class='add'>+		clock-frequency = &lt;1000000&gt;;</div><div class='add'>+</div><div class='add'>+		touchscreen: i2c-hid-dev@20 {</div><div class='add'>+				compatible = "hid-over-i2c";</div><div class='add'>+				reg = &lt;0x20&gt;;</div><div class='add'>+				hid-descr-addr = &lt;0x0020&gt;;</div><div class='add'>+				interrupt-parent = &lt;&amp;gpio&gt;;</div><div class='add'>+				interrupts = &lt;TEGRA_GPIO(X, 1) IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	i2c@7000c400 {</div><div class='ctx'> 		status = "okay";</div><div class='ctx'> 		clock-frequency = &lt;1000000&gt;;</div><div class='hunk'>@@ -1330,9 +1396,13 @@</div><div class='ctx'> 				battery: bq27742@55 {</div><div class='ctx'> 					compatible = "ti,bq27742";</div><div class='ctx'> 					reg = &lt;0x55&gt;;</div><div class='del'>-					battery-name = "battery";</div><div class='ctx'> 				};</div><div class='ctx'> 			};</div><div class='add'>+</div><div class='add'>+			usbc_extcon0: extcon0 {</div><div class='add'>+				compatible = "google,extcon-usbc-cros-ec";</div><div class='add'>+				google,usb-port-id = &lt;0&gt;;</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -1354,12 +1424,27 @@</div><div class='ctx'> 			maxim,dvs-default-state = &lt;1&gt;;</div><div class='ctx'> 			maxim,enable-active-discharge;</div><div class='ctx'> 			maxim,enable-bias-control;</div><div class='del'>-			maxim,enable-etr;</div><div class='del'>-			maxim,enable-gpio = &lt;&amp;max77620 5 0&gt;;</div><div class='add'>+			maxim,enable-gpio = &lt;&amp;pmic 5 0&gt;;</div><div class='add'>+			maxim,externally-enable;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		max77621_gpu: regulator@1c {</div><div class='add'>+			compatible = "maxim,max77621";</div><div class='add'>+			reg = &lt;0x1c&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio&gt;;</div><div class='add'>+			interrupts = &lt;TEGRA_GPIO(A, 6) IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			regulator-min-microvolt = &lt;840000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1150000&gt;;</div><div class='add'>+			regulator-name = "PPVAR_GPU";</div><div class='add'>+			regulator-ramp-delay = &lt;12500&gt;;</div><div class='add'>+			maxim,dvs-default-state = &lt;1&gt;;</div><div class='add'>+			maxim,enable-active-discharge;</div><div class='add'>+			maxim,enable-bias-control;</div><div class='add'>+			maxim,enable-gpio = &lt;&amp;pmic 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 			maxim,externally-enable;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		max77620: max77620@3c {</div><div class='add'>+		pmic: pmic@3c {</div><div class='ctx'> 			compatible = "maxim,max77620";</div><div class='ctx'> 			reg = &lt;0x3c&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='hunk'>@@ -1373,8 +1458,25 @@</div><div class='ctx'> 			pinctrl-names = "default";</div><div class='ctx'> 			pinctrl-0 = &lt;&amp;max77620_default&gt;;</div><div class='ctx'> </div><div class='del'>-			max77620_default: pinmux@0 {</div><div class='del'>-				pin_gpio {</div><div class='add'>+			fps {</div><div class='add'>+				fps0 {</div><div class='add'>+					maxim,shutdown-fps-time-period-us = &lt;5120&gt;;</div><div class='add'>+					maxim,fps-event-source = &lt;MAX77620_FPS_EVENT_SRC_EN0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				fps1 {</div><div class='add'>+					maxim,shutdown-fps-time-period-us = &lt;5120&gt;;</div><div class='add'>+					maxim,fps-event-source = &lt;MAX77620_FPS_EVENT_SRC_EN1&gt;;</div><div class='add'>+					maxim,device-state-on-disabled-event = &lt;MAX77620_FPS_INACTIVE_STATE_SLEEP&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				fps2 {</div><div class='add'>+					maxim,fps-event-source = &lt;MAX77620_FPS_EVENT_SRC_EN0&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			max77620_default: pinmux {</div><div class='add'>+				gpio0_1_2_7 {</div><div class='ctx'> 					pins = "gpio0", "gpio1", "gpio2", "gpio7";</div><div class='ctx'> 					function = "gpio";</div><div class='ctx'> 				};</div><div class='hunk'>@@ -1384,7 +1486,7 @@</div><div class='ctx'> 				 * sequence, So it must be sequenced up (automatically</div><div class='ctx'> 				 * set by OTP) and down properly.</div><div class='ctx'> 				 */</div><div class='del'>-				pin_gpio3 {</div><div class='add'>+				gpio3 {</div><div class='ctx'> 					pins = "gpio3";</div><div class='ctx'> 					function = "fps-out";</div><div class='ctx'> 					drive-open-drain = &lt;1&gt;;</div><div class='hunk'>@@ -1393,32 +1495,15 @@</div><div class='ctx'> 					maxim,active-fps-power-down-slot = &lt;2&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> </div><div class='del'>-				pin_gpio5_6 {</div><div class='del'>-					pins = "gpio5", "gpio6";</div><div class='del'>-					function = "gpio";</div><div class='del'>-					drive-push-pull = &lt;1&gt;;</div><div class='del'>-				};</div><div class='del'>-</div><div class='del'>-				pin_32k {</div><div class='add'>+				gpio4 {</div><div class='ctx'> 					pins = "gpio4";</div><div class='ctx'> 					function = "32k-out1";</div><div class='ctx'> 				};</div><div class='del'>-			};</div><div class='del'>-</div><div class='del'>-			fps {</div><div class='del'>-				fps0 {</div><div class='del'>-					maxim,shutdown-fps-time-period-us = &lt;5120&gt;;</div><div class='del'>-					maxim,fps-event-source = &lt;MAX77620_FPS_EVENT_SRC_EN0&gt;;</div><div class='del'>-				};</div><div class='ctx'> </div><div class='del'>-				fps1 {</div><div class='del'>-					maxim,shutdown-fps-time-period-us = &lt;5120&gt;;</div><div class='del'>-					maxim,fps-event-source = &lt;MAX77620_FPS_EVENT_SRC_EN1&gt;;</div><div class='del'>-					maxim,device-state-on-disabled-event = &lt;MAX77620_FPS_INACTIVE_STATE_SLEEP&gt;;</div><div class='del'>-				};</div><div class='del'>-</div><div class='del'>-				fps2 {</div><div class='del'>-					maxim,fps-event-source = &lt;MAX77620_FPS_EVENT_SRC_EN0&gt;;</div><div class='add'>+				gpio5_6 {</div><div class='add'>+					pins = "gpio5", "gpio6";</div><div class='add'>+					function = "gpio";</div><div class='add'>+					drive-push-pull = &lt;1&gt;;</div><div class='ctx'> 				};</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -1611,6 +1696,37 @@</div><div class='ctx'> 			status = "okay";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		backlight: backlight@2c {</div><div class='add'>+			compatible = "ti,lp8557";</div><div class='add'>+			reg = &lt;0x2c&gt;;</div><div class='add'>+			power-supply = &lt;&amp;pplcd_vdd&gt;;</div><div class='add'>+			enable-supply = &lt;&amp;pp1800_lcdio&gt;;</div><div class='add'>+			bl-name = "lp8557-backlight";</div><div class='add'>+			dev-ctrl = /bits/ 8 &lt;0x01&gt;;</div><div class='add'>+			init-brt = /bits/ 8 &lt;0x80&gt;;</div><div class='add'>+</div><div class='add'>+			/* Full scale current, 20mA */</div><div class='add'>+			rom-11h {</div><div class='add'>+				rom-addr = /bits/ 8 &lt;0x11&gt;;</div><div class='add'>+				rom-val = /bits/ 8 &lt;0x05&gt;;</div><div class='add'>+			};</div><div class='add'>+			/* Frequency = 4.9kHz, magic undocumented val */</div><div class='add'>+			rom-12h {</div><div class='add'>+				rom-addr = /bits/ 8 &lt;0x12&gt;;</div><div class='add'>+				rom-val = /bits/ 8 &lt;0x29&gt;;</div><div class='add'>+			};</div><div class='add'>+			/* Boost freq = 1MHz, BComp option = 1 */</div><div class='add'>+			rom-13h {</div><div class='add'>+				rom-addr = /bits/ 8 &lt;0x13&gt;;</div><div class='add'>+				rom-val = /bits/ 8 &lt;0x03&gt;;</div><div class='add'>+			};</div><div class='add'>+			/* 4V OV, 6 output LED string enabled */</div><div class='add'>+			rom-14h {</div><div class='add'>+				rom-addr = /bits/ 8 &lt;0x14&gt;;</div><div class='add'>+				rom-val = /bits/ 8 &lt;0xbf&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		audio-codec@2d {</div><div class='ctx'> 			compatible = "realtek,rt5677";</div><div class='ctx'> 			reg = &lt;0x2d&gt;;</div><div class='hunk'>@@ -1621,6 +1737,15 @@</div><div class='ctx'> 			#gpio-cells = &lt;2&gt;;</div><div class='ctx'> 			status = "okay";</div><div class='ctx'> 		};</div><div class='add'>+</div><div class='add'>+		tmp451: temperature-sensor@4c {</div><div class='add'>+			compatible = "ti,tmp451";</div><div class='add'>+			reg = &lt;0x4c&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio&gt;;</div><div class='add'>+			interrupts = &lt;TEGRA_GPIO(X, 4) IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			vcc-supply = &lt;&amp;pp1800&gt;;</div><div class='add'>+			#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	pmc@7000e400 {</div><div class='hunk'>@@ -1643,10 +1768,6 @@</div><div class='ctx'> 		dvddio-pex-supply = &lt;&amp;avddio_1v05&gt;;</div><div class='ctx'> 		hvddio-pex-supply = &lt;&amp;pp1800&gt;;</div><div class='ctx'> 		avdd-usb-supply = &lt;&amp;pp3300&gt;;</div><div class='del'>-		avdd-pll-utmip-supply = &lt;&amp;pp1800&gt;;</div><div class='del'>-		avdd-pll-uerefe-supply = &lt;&amp;pp1050_avdd&gt;;</div><div class='del'>-		dvdd-pex-pll-supply = &lt;&amp;avddio_1v05&gt;;</div><div class='del'>-		hvdd-pex-pll-e-supply = &lt;&amp;pp1800&gt;;</div><div class='ctx'> </div><div class='ctx'> 		status = "okay";</div><div class='ctx'> 	};</div><div class='hunk'>@@ -1697,7 +1818,26 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sdhci@700b0600 {</div><div class='add'>+	mmc@700b0200 {</div><div class='add'>+		power-gpios = &lt;&amp;gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		bus-width = &lt;4&gt;;</div><div class='add'>+		non-removable;</div><div class='add'>+		vqmmc-supply = &lt;&amp;pp1800&gt;;</div><div class='add'>+		vmmc-supply = &lt;&amp;pp3300&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+</div><div class='add'>+		wifi@1 {</div><div class='add'>+			compatible = "brcm,bcm4354-fmac", "brcm,bcm4329-fmac";</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;gpio&gt;;</div><div class='add'>+			interrupts = &lt;TEGRA_GPIO(H, 2) IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "host-wake";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmc@700b0600 {</div><div class='ctx'> 		bus-width = &lt;8&gt;;</div><div class='ctx'> 		non-removable;</div><div class='ctx'> 		status = "okay";</div><div class='hunk'>@@ -1718,26 +1858,19 @@</div><div class='ctx'> 	aconnect@702c0000 {</div><div class='ctx'> 		status = "okay";</div><div class='ctx'> </div><div class='del'>-		dma@702e2000 {</div><div class='add'>+		dma-controller@702e2000 {</div><div class='ctx'> 			status = "okay";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		agic@702f9000 {</div><div class='add'>+		interrupt-controller@702f9000 {</div><div class='ctx'> 			status = "okay";</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	clocks {</div><div class='del'>-		compatible = "simple-bus";</div><div class='del'>-		#address-cells = &lt;1&gt;;</div><div class='del'>-		#size-cells = &lt;0&gt;;</div><div class='del'>-</div><div class='del'>-		clk32k_in: clock@0 {</div><div class='del'>-			compatible = "fixed-clock";</div><div class='del'>-			reg = &lt;0&gt;;</div><div class='del'>-			#clock-cells = &lt;0&gt;;</div><div class='del'>-			clock-frequency = &lt;32768&gt;;</div><div class='del'>-		};</div><div class='add'>+	clk32k_in: clock-32k {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		clock-frequency = &lt;32768&gt;;</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	cpus {</div><div class='hunk'>@@ -1768,7 +1901,7 @@</div><div class='ctx'> 	gpio-keys {</div><div class='ctx'> 		compatible = "gpio-keys";</div><div class='ctx'> </div><div class='del'>-		power {</div><div class='add'>+		key-power {</div><div class='ctx'> 			label = "Power";</div><div class='ctx'> 			gpios = &lt;&amp;gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 			linux,code = &lt;KEY_POWER&gt;;</div><div class='hunk'>@@ -1776,7 +1909,19 @@</div><div class='ctx'> 			wakeup-source;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		lid {</div><div class='add'>+		key-volume-down {</div><div class='add'>+			label = "Volume Down";</div><div class='add'>+			gpios = &lt;&amp;gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-volume-up {</div><div class='add'>+			label = "Volume Up";</div><div class='add'>+			gpios = &lt;&amp;gpio TEGRA_GPIO(M, 4) GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		switch-lid {</div><div class='ctx'> 			label = "Lid";</div><div class='ctx'> 			gpios = &lt;&amp;gpio TEGRA_GPIO(B, 4) GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> 			linux,input-type = &lt;EV_SW&gt;;</div><div class='hunk'>@@ -1784,25 +1929,13 @@</div><div class='ctx'> 			wakeup-source;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		tablet_mode {</div><div class='add'>+		switch-tablet-mode {</div><div class='ctx'> 			label = "Tablet Mode";</div><div class='ctx'> 			gpios = &lt;&amp;gpio TEGRA_GPIO(Z, 2) GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> 			linux,input-type = &lt;EV_SW&gt;;</div><div class='ctx'> 			linux,code = &lt;SW_TABLET_MODE&gt;;</div><div class='ctx'> 			wakeup-source;</div><div class='ctx'> 		};</div><div class='del'>-</div><div class='del'>-		volume_down {</div><div class='del'>-			label = "Volume Down";</div><div class='del'>-			gpios = &lt;&amp;gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-			linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		volume_up {</div><div class='del'>-			label = "Volume Up";</div><div class='del'>-			gpios = &lt;&amp;gpio TEGRA_GPIO(M, 4) GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='del'>-		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	max98357a {</div><div class='hunk'>@@ -1815,88 +1948,81 @@</div><div class='ctx'> 		method = "smc";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	regulators {</div><div class='del'>-		compatible = "simple-bus";</div><div class='del'>-		device_type = "fixed-regulators";</div><div class='del'>-		#address-cells = &lt;1&gt;;</div><div class='del'>-		#size-cells = &lt;0&gt;;</div><div class='add'>+	ppvar_sys: regulator-ppvar-sys {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "PPVAR_SYS";</div><div class='add'>+		regulator-min-microvolt = &lt;4400000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;4400000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		ppvar_sys: regulator@0 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;0&gt;;</div><div class='del'>-			regulator-name = "PPVAR_SYS";</div><div class='del'>-			regulator-min-microvolt = &lt;4400000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;4400000&gt;;</div><div class='del'>-			regulator-always-on;</div><div class='del'>-		};</div><div class='add'>+	pplcd_vdd: regulator-pplcd-vdd {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "PPLCD_VDD";</div><div class='add'>+		regulator-min-microvolt = &lt;4400000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;4400000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio TEGRA_GPIO(V, 4) 0&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		pplcd_vdd: regulator@1 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;1&gt;;</div><div class='del'>-			regulator-name = "PPLCD_VDD";</div><div class='del'>-			regulator-min-microvolt = &lt;4400000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;4400000&gt;;</div><div class='del'>-			gpio = &lt;&amp;gpio TEGRA_GPIO(V, 4) 0&gt;;</div><div class='del'>-			enable-active-high;</div><div class='del'>-			regulator-boot-on;</div><div class='del'>-		};</div><div class='add'>+	pp3000_always: regulator-pp3000-always {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "PP3000_ALWAYS";</div><div class='add'>+		regulator-min-microvolt = &lt;3000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		pp3000_always: regulator@2 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;2&gt;;</div><div class='del'>-			regulator-name = "PP3000_ALWAYS";</div><div class='del'>-			regulator-min-microvolt = &lt;3000000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;3000000&gt;;</div><div class='del'>-			regulator-always-on;</div><div class='del'>-		};</div><div class='add'>+	pp3300: regulator-pp3000 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "PP3300";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		pp3300: regulator@3 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;3&gt;;</div><div class='del'>-			regulator-name = "PP3300";</div><div class='del'>-			regulator-min-microvolt = &lt;3300000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;3300000&gt;;</div><div class='del'>-			regulator-boot-on;</div><div class='del'>-			regulator-always-on;</div><div class='del'>-			enable-active-high;</div><div class='del'>-		};</div><div class='add'>+	pp5000: regulator-pp5000 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "PP5000";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		pp5000: regulator@4 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;4&gt;;</div><div class='del'>-			regulator-name = "PP5000";</div><div class='del'>-			regulator-min-microvolt = &lt;5000000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;5000000&gt;;</div><div class='del'>-			regulator-always-on;</div><div class='del'>-		};</div><div class='add'>+	pp1800_lcdio: regulator-pp1800-lcdio {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "PP1800_LCDIO";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio TEGRA_GPIO(V, 3) 0&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		pp1800_lcdio: regulator@5 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;5&gt;;</div><div class='del'>-			regulator-name = "PP1800_LCDIO";</div><div class='del'>-			regulator-min-microvolt = &lt;1800000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;1800000&gt;;</div><div class='del'>-			gpio = &lt;&amp;gpio TEGRA_GPIO(V, 3) 0&gt;;</div><div class='del'>-			enable-active-high;</div><div class='del'>-			regulator-boot-on;</div><div class='del'>-		};</div><div class='add'>+	pp1800_cam: regulator-pp1800-cam {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "PP1800_CAM";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio TEGRA_GPIO(K, 3) 0&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		pp1800_cam: regulator@6 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg= &lt;6&gt;;</div><div class='del'>-			regulator-name = "PP1800_CAM";</div><div class='del'>-			regulator-min-microvolt = &lt;1800000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;1800000&gt;;</div><div class='del'>-			gpio = &lt;&amp;gpio TEGRA_GPIO(K, 3) 0&gt;;</div><div class='del'>-			enable-active-high;</div><div class='del'>-		};</div><div class='add'>+	usbc_vbus: regulator-usbc-vbus {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "USBC_VBUS";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		usbc_vbus: regulator@7 {</div><div class='del'>-			compatible = "regulator-fixed";</div><div class='del'>-			reg = &lt;7&gt;;</div><div class='del'>-			regulator-name = "USBC_VBUS";</div><div class='del'>-			regulator-min-microvolt = &lt;5000000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;5000000&gt;;</div><div class='del'>-		};</div><div class='add'>+	vdd_dsi_csi: regulator-vdd-dsi-csi {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "AVDD_DSI_CSI_1V2";</div><div class='add'>+		regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;pp1200_avdd&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi<br/>index 64c46ce3849d..709da31d5785 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra210.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/nvidia/tegra210.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra210.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/tegra210.dtsi</a></div><div class='hunk'>@@ -9,6 +9,8 @@</div><div class='ctx'> #include &lt;dt-bindings/thermal/tegra124-soctherm.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/soc/tegra-pmc.h&gt;</div><div class='ctx'> </div><div class='add'>+#include "tegra210-peripherals-opp.dtsi"</div><div class='add'>+</div><div class='ctx'> / {</div><div class='ctx'> 	compatible = "nvidia,tegra210";</div><div class='ctx'> 	interrupt-parent = &lt;&amp;lic&gt;;</div><div class='hunk'>@@ -18,9 +20,9 @@</div><div class='ctx'> 	pcie@1003000 {</div><div class='ctx'> 		compatible = "nvidia,tegra210-pcie";</div><div class='ctx'> 		device_type = "pci";</div><div class='del'>-		reg = &lt;0x0 0x01003000 0x0 0x00000800   /* PADS registers */</div><div class='del'>-		       0x0 0x01003800 0x0 0x00000800   /* AFI registers */</div><div class='del'>-		       0x0 0x02000000 0x0 0x10000000&gt;; /* configuration space */</div><div class='add'>+		reg = &lt;0x0 0x01003000 0x0 0x00000800&gt;, /* PADS registers */</div><div class='add'>+		      &lt;0x0 0x01003800 0x0 0x00000800&gt;, /* AFI registers */</div><div class='add'>+		      &lt;0x0 0x02000000 0x0 0x10000000&gt;; /* configuration space */</div><div class='ctx'> 		reg-names = "pads", "afi", "cs";</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH&gt;, /* controller interrupt */</div><div class='ctx'> 			     &lt;GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH&gt;; /* MSI interrupt */</div><div class='hunk'>@@ -34,11 +36,11 @@</div><div class='ctx'> 		#address-cells = &lt;3&gt;;</div><div class='ctx'> 		#size-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='del'>-		ranges = &lt;0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000   /* port 0 configuration space */</div><div class='del'>-			  0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000   /* port 1 configuration space */</div><div class='del'>-			  0x81000000 0 0x0        0x0 0x12000000 0 0x00010000   /* downstream I/O (64 KiB) */</div><div class='del'>-			  0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000   /* non-prefetchable memory (208 MiB) */</div><div class='del'>-			  0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000&gt;; /* prefetchable memory (512 MiB) */</div><div class='add'>+		ranges = &lt;0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000&gt;, /* port 0 configuration space */</div><div class='add'>+			 &lt;0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000&gt;, /* port 1 configuration space */</div><div class='add'>+			 &lt;0x01000000 0 0x0        0x0 0x12000000 0 0x00010000&gt;, /* downstream I/O (64 KiB) */</div><div class='add'>+			 &lt;0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000&gt;, /* non-prefetchable memory (208 MiB) */</div><div class='add'>+			 &lt;0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000&gt;; /* prefetchable memory (512 MiB) */</div><div class='ctx'> </div><div class='ctx'> 		clocks = &lt;&amp;tegra_car TEGRA210_CLK_PCIE&gt;,</div><div class='ctx'> 			 &lt;&amp;tegra_car TEGRA210_CLK_AFI&gt;,</div><div class='hunk'>@@ -86,14 +88,15 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	host1x@50000000 {</div><div class='del'>-		compatible = "nvidia,tegra210-host1x", "simple-bus";</div><div class='add'>+		compatible = "nvidia,tegra210-host1x";</div><div class='ctx'> 		reg = &lt;0x0 0x50000000 0x0 0x00034000&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH&gt;, /* syncpt */</div><div class='ctx'> 			     &lt;GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH&gt;; /* general */</div><div class='add'>+		interrupt-names = "syncpt", "host1x";</div><div class='ctx'> 		clocks = &lt;&amp;tegra_car TEGRA210_CLK_HOST1X&gt;;</div><div class='ctx'> 		clock-names = "host1x";</div><div class='del'>-		resets = &lt;&amp;tegra_car 28&gt;;</div><div class='del'>-		reset-names = "host1x";</div><div class='add'>+		resets = &lt;&amp;tegra_car 28&gt;, &lt;&amp;mc TEGRA210_MC_RESET_HC&gt;;</div><div class='add'>+		reset-names = "host1x", "mc";</div><div class='ctx'> </div><div class='ctx'> 		#address-cells = &lt;2&gt;;</div><div class='ctx'> 		#size-cells = &lt;2&gt;;</div><div class='hunk'>@@ -137,47 +140,108 @@</div><div class='ctx'> </div><div class='ctx'> 		vi@54080000 {</div><div class='ctx'> 			compatible = "nvidia,tegra210-vi";</div><div class='del'>-			reg = &lt;0x0 0x54080000 0x0 0x00040000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x54080000 0x0 0x700&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='add'>+			assigned-clocks = &lt;&amp;tegra_car TEGRA210_CLK_VI&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;tegra_car TEGRA210_CLK_PLL_C4_OUT0&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;tegra_car TEGRA210_CLK_VI&gt;;</div><div class='add'>+			power-domains = &lt;&amp;pd_venc&gt;;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			ranges = &lt;0x0 0x0 0x54080000 0x2000&gt;;</div><div class='add'>+</div><div class='add'>+			csi@838 {</div><div class='add'>+				compatible = "nvidia,tegra210-csi";</div><div class='add'>+				reg = &lt;0x838 0x1300&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+				assigned-clocks = &lt;&amp;tegra_car TEGRA210_CLK_CILAB&gt;,</div><div class='add'>+						  &lt;&amp;tegra_car TEGRA210_CLK_CILCD&gt;,</div><div class='add'>+						  &lt;&amp;tegra_car TEGRA210_CLK_CILE&gt;,</div><div class='add'>+						  &lt;&amp;tegra_car TEGRA210_CLK_CSI_TPG&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;tegra_car TEGRA210_CLK_PLL_P&gt;,</div><div class='add'>+							 &lt;&amp;tegra_car TEGRA210_CLK_PLL_P&gt;,</div><div class='add'>+							 &lt;&amp;tegra_car TEGRA210_CLK_PLL_P&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;102000000&gt;,</div><div class='add'>+						       &lt;102000000&gt;,</div><div class='add'>+						       &lt;102000000&gt;,</div><div class='add'>+						       &lt;972000000&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;tegra_car TEGRA210_CLK_CSI&gt;,</div><div class='add'>+					 &lt;&amp;tegra_car TEGRA210_CLK_CILAB&gt;,</div><div class='add'>+					 &lt;&amp;tegra_car TEGRA210_CLK_CILCD&gt;,</div><div class='add'>+					 &lt;&amp;tegra_car TEGRA210_CLK_CILE&gt;,</div><div class='add'>+					 &lt;&amp;tegra_car TEGRA210_CLK_CSI_TPG&gt;;</div><div class='add'>+				clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";</div><div class='add'>+				power-domains = &lt;&amp;pd_sor&gt;;</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		tsec@54100000 {</div><div class='ctx'> 			compatible = "nvidia,tegra210-tsec";</div><div class='ctx'> 			reg = &lt;0x0 0x54100000 0x0 0x00040000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;tegra_car TEGRA210_CLK_TSEC&gt;;</div><div class='add'>+			resets = &lt;&amp;tegra_car 83&gt;;</div><div class='add'>+			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		dc@54200000 {</div><div class='ctx'> 			compatible = "nvidia,tegra210-dc";</div><div class='ctx'> 			reg = &lt;0x0 0x54200000 0x0 0x00040000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;tegra_car TEGRA210_CLK_DISP1&gt;,</div><div class='del'>-				 &lt;&amp;tegra_car TEGRA210_CLK_PLL_P&gt;;</div><div class='del'>-			clock-names = "dc", "parent";</div><div class='add'>+			clocks = &lt;&amp;tegra_car TEGRA210_CLK_DISP1&gt;;</div><div class='add'>+			clock-names = "dc";</div><div class='ctx'> 			resets = &lt;&amp;tegra_car 27&gt;;</div><div class='ctx'> 			reset-names = "dc";</div><div class='ctx'> </div><div class='ctx'> 			iommus = &lt;&amp;mc TEGRA_SWGROUP_DC&gt;;</div><div class='ctx'> </div><div class='add'>+			nvidia,outputs = &lt;&amp;dsia &amp;dsib &amp;sor0 &amp;sor1&gt;;</div><div class='ctx'> 			nvidia,head = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA210_MC_DISPLAY0A &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA210_MC_DISPLAY0B &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA210_MC_DISPLAY0C &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA210_MC_DISPLAYHC &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA210_MC_DISPLAYD &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA210_MC_DISPLAYT &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "wina",</div><div class='add'>+					     "winb",</div><div class='add'>+					     "winc",</div><div class='add'>+					     "cursor",</div><div class='add'>+					     "wind",</div><div class='add'>+					     "wint";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		dc@54240000 {</div><div class='ctx'> 			compatible = "nvidia,tegra210-dc";</div><div class='ctx'> 			reg = &lt;0x0 0x54240000 0x0 0x00040000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;tegra_car TEGRA210_CLK_DISP2&gt;,</div><div class='del'>-				 &lt;&amp;tegra_car TEGRA210_CLK_PLL_P&gt;;</div><div class='del'>-			clock-names = "dc", "parent";</div><div class='add'>+			clocks = &lt;&amp;tegra_car TEGRA210_CLK_DISP2&gt;;</div><div class='add'>+			clock-names = "dc";</div><div class='ctx'> 			resets = &lt;&amp;tegra_car 26&gt;;</div><div class='ctx'> 			reset-names = "dc";</div><div class='ctx'> </div><div class='ctx'> 			iommus = &lt;&amp;mc TEGRA_SWGROUP_DCB&gt;;</div><div class='ctx'> </div><div class='add'>+			nvidia,outputs = &lt;&amp;dsia &amp;dsib &amp;sor0 &amp;sor1&gt;;</div><div class='ctx'> 			nvidia,head = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA210_MC_DISPLAY0AB &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA210_MC_DISPLAY0BB &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA210_MC_DISPLAY0CB &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA210_MC_DISPLAYHCB &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "wina",</div><div class='add'>+					     "winb",</div><div class='add'>+					     "winc",</div><div class='add'>+					     "cursor";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		dsi@54300000 {</div><div class='add'>+		dsia: dsi@54300000 {</div><div class='ctx'> 			compatible = "nvidia,tegra210-dsi";</div><div class='ctx'> 			reg = &lt;0x0 0x54300000 0x0 0x00040000&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;tegra_car TEGRA210_CLK_DSIA&gt;,</div><div class='hunk'>@@ -211,10 +275,16 @@</div><div class='ctx'> 		nvjpg@54380000 {</div><div class='ctx'> 			compatible = "nvidia,tegra210-nvjpg";</div><div class='ctx'> 			reg = &lt;0x0 0x54380000 0x0 0x00040000&gt;;</div><div class='del'>-			status = "disabled";</div><div class='add'>+			clocks = &lt;&amp;tegra_car TEGRA210_CLK_NVJPG&gt;;</div><div class='add'>+			clock-names = "nvjpg";</div><div class='add'>+			resets = &lt;&amp;tegra_car 195&gt;;</div><div class='add'>+			reset-names = "nvjpg";</div><div class='add'>+</div><div class='add'>+			iommus = &lt;&amp;mc TEGRA_SWGROUP_NVJPG&gt;;</div><div class='add'>+			power-domains = &lt;&amp;pd_nvjpg&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		dsi@54400000 {</div><div class='add'>+		dsib: dsi@54400000 {</div><div class='ctx'> 			compatible = "nvidia,tegra210-dsi";</div><div class='ctx'> 			reg = &lt;0x0 0x54400000 0x0 0x00040000&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;tegra_car TEGRA210_CLK_DSIB&gt;,</div><div class='hunk'>@@ -235,22 +305,39 @@</div><div class='ctx'> 		nvdec@54480000 {</div><div class='ctx'> 			compatible = "nvidia,tegra210-nvdec";</div><div class='ctx'> 			reg = &lt;0x0 0x54480000 0x0 0x00040000&gt;;</div><div class='del'>-			status = "disabled";</div><div class='add'>+			clocks = &lt;&amp;tegra_car TEGRA210_CLK_NVDEC&gt;;</div><div class='add'>+			clock-names = "nvdec";</div><div class='add'>+			resets = &lt;&amp;tegra_car 194&gt;;</div><div class='add'>+			reset-names = "nvdec";</div><div class='add'>+</div><div class='add'>+			iommus = &lt;&amp;mc TEGRA_SWGROUP_NVDEC&gt;;</div><div class='add'>+			power-domains = &lt;&amp;pd_nvdec&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		nvenc@544c0000 {</div><div class='ctx'> 			compatible = "nvidia,tegra210-nvenc";</div><div class='ctx'> 			reg = &lt;0x0 0x544c0000 0x0 0x00040000&gt;;</div><div class='del'>-			status = "disabled";</div><div class='add'>+			clocks = &lt;&amp;tegra_car TEGRA210_CLK_NVENC&gt;;</div><div class='add'>+			clock-names = "nvenc";</div><div class='add'>+			resets = &lt;&amp;tegra_car 219&gt;;</div><div class='add'>+			reset-names = "nvenc";</div><div class='add'>+</div><div class='add'>+			iommus = &lt;&amp;mc TEGRA_SWGROUP_NVENC&gt;;</div><div class='add'>+			power-domains = &lt;&amp;pd_nvenc&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		tsec@54500000 {</div><div class='ctx'> 			compatible = "nvidia,tegra210-tsec";</div><div class='ctx'> 			reg = &lt;0x0 0x54500000 0x0 0x00040000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;tegra_car TEGRA210_CLK_TSECB&gt;;</div><div class='add'>+			clock-names = "tsec";</div><div class='add'>+			resets = &lt;&amp;tegra_car 206&gt;;</div><div class='add'>+			reset-names = "tsec";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		sor@54540000 {</div><div class='add'>+		sor0: sor@54540000 {</div><div class='ctx'> 			compatible = "nvidia,tegra210-sor";</div><div class='ctx'> 			reg = &lt;0x0 0x54540000 0x0 0x00040000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='hunk'>@@ -270,7 +357,7 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		sor@54580000 {</div><div class='add'>+		sor1: sor@54580000 {</div><div class='ctx'> 			compatible = "nvidia,tegra210-sor1";</div><div class='ctx'> 			reg = &lt;0x0 0x54580000 0x0 0x00040000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='hunk'>@@ -291,7 +378,7 @@</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		dpaux: dpaux@545c0000 {</div><div class='del'>-			compatible = "nvidia,tegra124-dpaux";</div><div class='add'>+			compatible = "nvidia,tegra210-dpaux";</div><div class='ctx'> 			reg = &lt;0x0 0x545c0000 0x0 0x00040000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;tegra_car TEGRA210_CLK_DPAUX&gt;,</div><div class='hunk'>@@ -327,6 +414,9 @@</div><div class='ctx'> 			compatible = "nvidia,tegra210-isp";</div><div class='ctx'> 			reg = &lt;0x0 0x54600000 0x0 0x00040000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;tegra_car TEGRA210_CLK_ISPA&gt;;</div><div class='add'>+			resets = &lt;&amp;tegra_car 23&gt;;</div><div class='add'>+			reset-names = "isp";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -334,6 +424,9 @@</div><div class='ctx'> 			compatible = "nvidia,tegra210-isp";</div><div class='ctx'> 			reg = &lt;0x0 0x54680000 0x0 0x00040000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;tegra_car TEGRA210_CLK_ISPB&gt;;</div><div class='add'>+			resets = &lt;&amp;tegra_car 3&gt;;</div><div class='add'>+			reset-names = "isp";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='hunk'>@@ -341,12 +434,22 @@</div><div class='ctx'> 			compatible = "nvidia,tegra210-i2c-vi";</div><div class='ctx'> 			reg = &lt;0x0 0x546c0000 0x0 0x00040000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;tegra_car TEGRA210_CLK_VI_I2C&gt;,</div><div class='add'>+				 &lt;&amp;tegra_car TEGRA210_CLK_I2CSLOW&gt;;</div><div class='add'>+			clock-names = "div-clk", "slow";</div><div class='add'>+			resets = &lt;&amp;tegra_car 208&gt;;</div><div class='add'>+			reset-names = "i2c";</div><div class='add'>+			power-domains = &lt;&amp;pd_venc&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	gic: interrupt-controller@50041000 {</div><div class='ctx'> 		compatible = "arm,gic-400";</div><div class='add'>+		#address-cells = &lt;0&gt;;</div><div class='ctx'> 		#interrupt-cells = &lt;3&gt;;</div><div class='ctx'> 		interrupt-controller;</div><div class='ctx'> 		reg = &lt;0x0 0x50041000 0x0 0x1000&gt;,</div><div class='hunk'>@@ -423,6 +526,21 @@</div><div class='ctx'> 		reg = &lt;0x0 0x60007000 0x0 0x1000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	actmon@6000c800 {</div><div class='add'>+		compatible = "nvidia,tegra210-actmon", "nvidia,tegra124-actmon";</div><div class='add'>+		reg = &lt;0x0 0x6000c800 0x0 0x400&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;tegra_car TEGRA210_CLK_ACTMON&gt;,</div><div class='add'>+			 &lt;&amp;tegra_car TEGRA210_CLK_EMC&gt;;</div><div class='add'>+		clock-names = "actmon", "emc";</div><div class='add'>+		resets = &lt;&amp;tegra_car 119&gt;;</div><div class='add'>+		reset-names = "actmon";</div><div class='add'>+		operating-points-v2 = &lt;&amp;emc_bw_dfs_opp_table&gt;;</div><div class='add'>+		interconnects = &lt;&amp;mc TEGRA210_MC_MPCORER &amp;emc&gt;;</div><div class='add'>+		interconnect-names = "cpu-read";</div><div class='add'>+		#cooling-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	gpio: gpio@6000d000 {</div><div class='ctx'> 		compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio";</div><div class='ctx'> 		reg = &lt;0x0 0x6000d000 0x0 0x1000&gt;;</div><div class='hunk'>@@ -440,7 +558,7 @@</div><div class='ctx'> 		interrupt-controller;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	apbdma: dma@60020000 {</div><div class='add'>+	apbdma: dma-controller@60020000 {</div><div class='ctx'> 		compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma";</div><div class='ctx'> 		reg = &lt;0x0 0x60020000 0x0 0x1400&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='hunk'>@@ -492,42 +610,48 @@</div><div class='ctx'> 		compatible = "nvidia,tegra210-pinmux";</div><div class='ctx'> 		reg = &lt;0x0 0x700008d4 0x0 0x29c&gt;, /* Pad control registers */</div><div class='ctx'> 		      &lt;0x0 0x70003000 0x0 0x294&gt;; /* Mux registers */</div><div class='del'>-		sdmmc1_3v3_drv: sdmmc1-3v3-drv {</div><div class='add'>+</div><div class='add'>+		sdmmc1_1v8_drv: pinmux-sdmmc1-1v8-drv {</div><div class='ctx'> 			sdmmc1 {</div><div class='ctx'> 				nvidia,pins = "drive_sdmmc1";</div><div class='del'>-				nvidia,pull-down-strength = &lt;0x8&gt;;</div><div class='del'>-				nvidia,pull-up-strength = &lt;0x8&gt;;</div><div class='add'>+				nvidia,pull-down-strength = &lt;0x4&gt;;</div><div class='add'>+				nvidia,pull-up-strength = &lt;0x3&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='del'>-		sdmmc1_1v8_drv: sdmmc1-1v8-drv {</div><div class='add'>+</div><div class='add'>+		sdmmc1_3v3_drv: pinmux-sdmmc1-3v3-drv {</div><div class='ctx'> 			sdmmc1 {</div><div class='ctx'> 				nvidia,pins = "drive_sdmmc1";</div><div class='del'>-				nvidia,pull-down-strength = &lt;0x4&gt;;</div><div class='del'>-				nvidia,pull-up-strength = &lt;0x3&gt;;</div><div class='add'>+				nvidia,pull-down-strength = &lt;0x8&gt;;</div><div class='add'>+				nvidia,pull-up-strength = &lt;0x8&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='del'>-		sdmmc2_1v8_drv: sdmmc2-1v8-drv {</div><div class='add'>+</div><div class='add'>+		sdmmc2_1v8_drv: pinmux-sdmmc2-1v8-drv {</div><div class='ctx'> 			sdmmc2 {</div><div class='ctx'> 				nvidia,pins = "drive_sdmmc2";</div><div class='ctx'> 				nvidia,pull-down-strength = &lt;0x10&gt;;</div><div class='ctx'> 				nvidia,pull-up-strength = &lt;0x10&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='del'>-		sdmmc3_3v3_drv: sdmmc3-3v3-drv {</div><div class='add'>+</div><div class='add'>+		sdmmc3_1v8_drv: pinmux-sdmmc3-1v8-drv {</div><div class='ctx'> 			sdmmc3 {</div><div class='ctx'> 				nvidia,pins = "drive_sdmmc3";</div><div class='del'>-				nvidia,pull-down-strength = &lt;0x8&gt;;</div><div class='del'>-				nvidia,pull-up-strength = &lt;0x8&gt;;</div><div class='add'>+				nvidia,pull-down-strength = &lt;0x4&gt;;</div><div class='add'>+				nvidia,pull-up-strength = &lt;0x3&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='del'>-		sdmmc3_1v8_drv: sdmmc3-1v8-drv {</div><div class='add'>+</div><div class='add'>+		sdmmc3_3v3_drv: pinmux-sdmmc3-3v3-drv {</div><div class='ctx'> 			sdmmc3 {</div><div class='ctx'> 				nvidia,pins = "drive_sdmmc3";</div><div class='del'>-				nvidia,pull-down-strength = &lt;0x4&gt;;</div><div class='del'>-				nvidia,pull-up-strength = &lt;0x3&gt;;</div><div class='add'>+				nvidia,pull-down-strength = &lt;0x8&gt;;</div><div class='add'>+				nvidia,pull-up-strength = &lt;0x8&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='del'>-		sdmmc4_1v8_drv: sdmmc4-1v8-drv {</div><div class='add'>+</div><div class='add'>+		sdmmc4_1v8_drv: pinmux-sdmmc4-1v8-drv {</div><div class='ctx'> 			sdmmc4 {</div><div class='ctx'> 				nvidia,pins = "drive_sdmmc4";</div><div class='ctx'> 				nvidia,pull-down-strength = &lt;0x10&gt;;</div><div class='hunk'>@@ -550,9 +674,7 @@</div><div class='ctx'> 		reg-shift = &lt;2&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		clocks = &lt;&amp;tegra_car TEGRA210_CLK_UARTA&gt;;</div><div class='del'>-		clock-names = "serial";</div><div class='ctx'> 		resets = &lt;&amp;tegra_car 6&gt;;</div><div class='del'>-		reset-names = "serial";</div><div class='ctx'> 		dmas = &lt;&amp;apbdma 8&gt;, &lt;&amp;apbdma 8&gt;;</div><div class='ctx'> 		dma-names = "rx", "tx";</div><div class='ctx'> 		status = "disabled";</div><div class='hunk'>@@ -564,9 +686,7 @@</div><div class='ctx'> 		reg-shift = &lt;2&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		clocks = &lt;&amp;tegra_car TEGRA210_CLK_UARTB&gt;;</div><div class='del'>-		clock-names = "serial";</div><div class='ctx'> 		resets = &lt;&amp;tegra_car 7&gt;;</div><div class='del'>-		reset-names = "serial";</div><div class='ctx'> 		dmas = &lt;&amp;apbdma 9&gt;, &lt;&amp;apbdma 9&gt;;</div><div class='ctx'> 		dma-names = "rx", "tx";</div><div class='ctx'> 		status = "disabled";</div><div class='hunk'>@@ -578,9 +698,7 @@</div><div class='ctx'> 		reg-shift = &lt;2&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		clocks = &lt;&amp;tegra_car TEGRA210_CLK_UARTC&gt;;</div><div class='del'>-		clock-names = "serial";</div><div class='ctx'> 		resets = &lt;&amp;tegra_car 55&gt;;</div><div class='del'>-		reset-names = "serial";</div><div class='ctx'> 		dmas = &lt;&amp;apbdma 10&gt;, &lt;&amp;apbdma 10&gt;;</div><div class='ctx'> 		dma-names = "rx", "tx";</div><div class='ctx'> 		status = "disabled";</div><div class='hunk'>@@ -592,9 +710,7 @@</div><div class='ctx'> 		reg-shift = &lt;2&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		clocks = &lt;&amp;tegra_car TEGRA210_CLK_UARTD&gt;;</div><div class='del'>-		clock-names = "serial";</div><div class='ctx'> 		resets = &lt;&amp;tegra_car 65&gt;;</div><div class='del'>-		reset-names = "serial";</div><div class='ctx'> 		dmas = &lt;&amp;apbdma 19&gt;, &lt;&amp;apbdma 19&gt;;</div><div class='ctx'> 		dma-names = "rx", "tx";</div><div class='ctx'> 		status = "disabled";</div><div class='hunk'>@@ -605,7 +721,6 @@</div><div class='ctx'> 		reg = &lt;0x0 0x7000a000 0x0 0x100&gt;;</div><div class='ctx'> 		#pwm-cells = &lt;2&gt;;</div><div class='ctx'> 		clocks = &lt;&amp;tegra_car TEGRA210_CLK_PWM&gt;;</div><div class='del'>-		clock-names = "pwm";</div><div class='ctx'> 		resets = &lt;&amp;tegra_car 17&gt;;</div><div class='ctx'> 		reset-names = "pwm";</div><div class='ctx'> 		status = "disabled";</div><div class='hunk'>@@ -785,6 +900,48 @@</div><div class='ctx'> 		#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> 		interrupt-controller;</div><div class='ctx'> </div><div class='add'>+		pinmux {</div><div class='add'>+			pex_dpd_disable: pex-dpd-disable {</div><div class='add'>+				pins = "pex-bias", "pex-clk1", "pex-clk2";</div><div class='add'>+				low-power-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pex_dpd_enable: pex-dpd-enable {</div><div class='add'>+				pins = "pex-bias", "pex-clk1", "pex-clk2";</div><div class='add'>+				low-power-enable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sdmmc1_1v8: sdmmc1-1v8 {</div><div class='add'>+				pins = "sdmmc1";</div><div class='add'>+				power-source = &lt;TEGRA_IO_PAD_VOLTAGE_1V8&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sdmmc1_3v3: sdmmc1-3v3 {</div><div class='add'>+				pins = "sdmmc1";</div><div class='add'>+				power-source = &lt;TEGRA_IO_PAD_VOLTAGE_3V3&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sdmmc3_1v8: sdmmc3-1v8 {</div><div class='add'>+				pins = "sdmmc3";</div><div class='add'>+				power-source = &lt;TEGRA_IO_PAD_VOLTAGE_1V8&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sdmmc3_3v3: sdmmc3-3v3 {</div><div class='add'>+				pins = "sdmmc3";</div><div class='add'>+				power-source = &lt;TEGRA_IO_PAD_VOLTAGE_3V3&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gpio_1v8: gpio-1v8 {</div><div class='add'>+				pins = "gpio";</div><div class='add'>+				power-source = &lt;TEGRA_IO_PAD_VOLTAGE_1V8&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gpio_3v3: gpio-3v3 {</div><div class='add'>+				pins = "gpio";</div><div class='add'>+				power-source = &lt;TEGRA_IO_PAD_VOLTAGE_3V3&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		powergates {</div><div class='ctx'> 			pd_audio: aud {</div><div class='ctx'> 				clocks = &lt;&amp;tegra_car TEGRA210_CLK_APE&gt;,</div><div class='hunk'>@@ -793,10 +950,24 @@</div><div class='ctx'> 				#power-domain-cells = &lt;0&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='add'>+			pd_nvenc: mpe {</div><div class='add'>+				clocks = &lt;&amp;tegra_car TEGRA210_CLK_NVENC&gt;;</div><div class='add'>+				resets = &lt;&amp;tegra_car 219&gt;;</div><div class='add'>+				#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pd_nvdec: nvdec {</div><div class='add'>+				clocks = &lt;&amp;tegra_car TEGRA210_CLK_NVDEC&gt;;</div><div class='add'>+				resets = &lt;&amp;tegra_car 194&gt;;</div><div class='add'>+				#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='ctx'> 			pd_sor: sor {</div><div class='ctx'> 				clocks = &lt;&amp;tegra_car TEGRA210_CLK_SOR0&gt;,</div><div class='ctx'> 					 &lt;&amp;tegra_car TEGRA210_CLK_SOR1&gt;,</div><div class='del'>-					 &lt;&amp;tegra_car TEGRA210_CLK_CSI&gt;,</div><div class='add'>+					 &lt;&amp;tegra_car TEGRA210_CLK_CILAB&gt;,</div><div class='add'>+					 &lt;&amp;tegra_car TEGRA210_CLK_CILCD&gt;,</div><div class='add'>+					 &lt;&amp;tegra_car TEGRA210_CLK_CILE&gt;,</div><div class='ctx'> 					 &lt;&amp;tegra_car TEGRA210_CLK_DSIA&gt;,</div><div class='ctx'> 					 &lt;&amp;tegra_car TEGRA210_CLK_DSIB&gt;,</div><div class='ctx'> 					 &lt;&amp;tegra_car TEGRA210_CLK_DPAUX&gt;,</div><div class='hunk'>@@ -804,7 +975,6 @@</div><div class='ctx'> 					 &lt;&amp;tegra_car TEGRA210_CLK_MIPI_CAL&gt;;</div><div class='ctx'> 				resets = &lt;&amp;tegra_car TEGRA210_CLK_SOR0&gt;,</div><div class='ctx'> 					 &lt;&amp;tegra_car TEGRA210_CLK_SOR1&gt;,</div><div class='del'>-					 &lt;&amp;tegra_car TEGRA210_CLK_CSI&gt;,</div><div class='ctx'> 					 &lt;&amp;tegra_car TEGRA210_CLK_DSIA&gt;,</div><div class='ctx'> 					 &lt;&amp;tegra_car TEGRA210_CLK_DSIB&gt;,</div><div class='ctx'> 					 &lt;&amp;tegra_car TEGRA210_CLK_DPAUX&gt;,</div><div class='hunk'>@@ -813,6 +983,21 @@</div><div class='ctx'> 				#power-domain-cells = &lt;0&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='add'>+			pd_venc: venc {</div><div class='add'>+				clocks = &lt;&amp;tegra_car TEGRA210_CLK_VI&gt;,</div><div class='add'>+					 &lt;&amp;tegra_car TEGRA210_CLK_CSI&gt;;</div><div class='add'>+				resets = &lt;&amp;mc TEGRA210_MC_RESET_VI&gt;,</div><div class='add'>+					 &lt;&amp;tegra_car 20&gt;,</div><div class='add'>+					 &lt;&amp;tegra_car 52&gt;;</div><div class='add'>+				#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pd_vic: vic {</div><div class='add'>+				clocks = &lt;&amp;tegra_car TEGRA210_CLK_VIC03&gt;;</div><div class='add'>+				resets = &lt;&amp;tegra_car 178&gt;;</div><div class='add'>+				#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='ctx'> 			pd_xusbss: xusba {</div><div class='ctx'> 				clocks = &lt;&amp;tegra_car TEGRA210_CLK_XUSB_SS&gt;;</div><div class='ctx'> 				resets = &lt;&amp;tegra_car TEGRA210_CLK_XUSB_SS&gt;;</div><div class='hunk'>@@ -831,48 +1016,12 @@</div><div class='ctx'> 				#power-domain-cells = &lt;0&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			pd_vic: vic {</div><div class='del'>-				clocks = &lt;&amp;tegra_car TEGRA210_CLK_VIC03&gt;;</div><div class='del'>-				clock-names = "vic";</div><div class='del'>-				resets = &lt;&amp;tegra_car 178&gt;;</div><div class='del'>-				reset-names = "vic";</div><div class='add'>+			pd_nvjpg: nvjpg {</div><div class='add'>+				clocks = &lt;&amp;tegra_car TEGRA210_CLK_NVJPG&gt;;</div><div class='add'>+				resets = &lt;&amp;tegra_car 195&gt;;</div><div class='ctx'> 				#power-domain-cells = &lt;0&gt;;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='del'>-</div><div class='del'>-		sdmmc1_3v3: sdmmc1-3v3 {</div><div class='del'>-			pins = "sdmmc1";</div><div class='del'>-			power-source = &lt;TEGRA_IO_PAD_VOLTAGE_3V3&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		sdmmc1_1v8: sdmmc1-1v8 {</div><div class='del'>-			pins = "sdmmc1";</div><div class='del'>-			power-source = &lt;TEGRA_IO_PAD_VOLTAGE_1V8&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		sdmmc3_3v3: sdmmc3-3v3 {</div><div class='del'>-			pins = "sdmmc3";</div><div class='del'>-			power-source = &lt;TEGRA_IO_PAD_VOLTAGE_3V3&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		sdmmc3_1v8: sdmmc3-1v8 {</div><div class='del'>-			pins = "sdmmc3";</div><div class='del'>-			power-source = &lt;TEGRA_IO_PAD_VOLTAGE_1V8&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		pex_dpd_disable: pex_en {</div><div class='del'>-			pex-dpd-disable {</div><div class='del'>-				pins = "pex-bias", "pex-clk1", "pex-clk2";</div><div class='del'>-				low-power-disable;</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		pex_dpd_enable: pex_dis {</div><div class='del'>-			pex-dpd-enable {</div><div class='del'>-				pins = "pex-bias", "pex-clk1", "pex-clk2";</div><div class='del'>-				low-power-enable;</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	fuse@7000f800 {</div><div class='hunk'>@@ -884,6 +1033,15 @@</div><div class='ctx'> 		reset-names = "fuse";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	cec@70015000 {</div><div class='add'>+		compatible = "nvidia,tegra210-cec";</div><div class='add'>+		reg = &lt;0x0 0x070015000 0x0 0x1000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		clocks = &lt;&amp;tegra_car TEGRA210_CLK_CEC&gt;;</div><div class='add'>+		clock-names = "cec";</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	mc: memory-controller@70019000 {</div><div class='ctx'> 		compatible = "nvidia,tegra210-mc";</div><div class='ctx'> 		reg = &lt;0x0 0x70019000 0x0 0x1000&gt;;</div><div class='hunk'>@@ -893,6 +1051,23 @@</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> </div><div class='ctx'> 		#iommu-cells = &lt;1&gt;;</div><div class='add'>+		#reset-cells = &lt;1&gt;;</div><div class='add'>+		#interconnect-cells = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	emc: external-memory-controller@7001b000 {</div><div class='add'>+		compatible = "nvidia,tegra210-emc";</div><div class='add'>+		reg = &lt;0x0 0x7001b000 0x0 0x1000&gt;,</div><div class='add'>+		      &lt;0x0 0x7001e000 0x0 0x1000&gt;,</div><div class='add'>+		      &lt;0x0 0x7001f000 0x0 0x1000&gt;;</div><div class='add'>+		clocks = &lt;&amp;tegra_car TEGRA210_CLK_EMC&gt;;</div><div class='add'>+		clock-names = "emc";</div><div class='add'>+		interrupts = &lt;GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		nvidia,memory-controller = &lt;&amp;mc&gt;;</div><div class='add'>+		operating-points-v2 = &lt;&amp;emc_icc_dvfs_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+		#interconnect-cells = &lt;0&gt;;</div><div class='add'>+		#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	sata@70020000 {</div><div class='hunk'>@@ -905,9 +1080,9 @@</div><div class='ctx'> 			 &lt;&amp;tegra_car TEGRA210_CLK_SATA_OOB&gt;;</div><div class='ctx'> 		clock-names = "sata", "sata-oob";</div><div class='ctx'> 		resets = &lt;&amp;tegra_car 124&gt;,</div><div class='del'>-			 &lt;&amp;tegra_car 123&gt;,</div><div class='del'>-			 &lt;&amp;tegra_car 129&gt;;</div><div class='del'>-		reset-names = "sata", "sata-oob", "sata-cold";</div><div class='add'>+			 &lt;&amp;tegra_car 129&gt;,</div><div class='add'>+			 &lt;&amp;tegra_car 123&gt;;</div><div class='add'>+		reset-names = "sata", "sata-cold", "sata-oob";</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -923,6 +1098,7 @@</div><div class='ctx'> 			 &lt;&amp;tegra_car 128&gt;, /* hda2hdmi */</div><div class='ctx'> 			 &lt;&amp;tegra_car 111&gt;; /* hda2codec_2x */</div><div class='ctx'> 		reset-names = "hda", "hda2hdmi", "hda2codec_2x";</div><div class='add'>+		power-domains = &lt;&amp;pd_sor&gt;;</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='hunk'>@@ -966,8 +1142,10 @@</div><div class='ctx'> 	padctl: padctl@7009f000 {</div><div class='ctx'> 		compatible = "nvidia,tegra210-xusb-padctl";</div><div class='ctx'> 		reg = &lt;0x0 0x7009f000 0x0 0x1000&gt;;</div><div class='add'>+		interrupts = &lt;GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		resets = &lt;&amp;tegra_car 142&gt;;</div><div class='ctx'> 		reset-names = "padctl";</div><div class='add'>+		nvidia,pmc = &lt;&amp;tegra_pmc&gt;;</div><div class='ctx'> </div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> </div><div class='hunk'>@@ -1118,12 +1296,13 @@</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sdhci@700b0000 {</div><div class='del'>-		compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";</div><div class='add'>+	mmc@700b0000 {</div><div class='add'>+		compatible = "nvidia,tegra210-sdhci";</div><div class='ctx'> 		reg = &lt;0x0 0x700b0000 0x0 0x200&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-		clocks = &lt;&amp;tegra_car TEGRA210_CLK_SDMMC1&gt;;</div><div class='del'>-		clock-names = "sdhci";</div><div class='add'>+		clocks = &lt;&amp;tegra_car TEGRA210_CLK_SDMMC1&gt;,</div><div class='add'>+			 &lt;&amp;tegra_car TEGRA210_CLK_SDMMC_LEGACY&gt;;</div><div class='add'>+		clock-names = "sdhci", "tmclk";</div><div class='ctx'> 		resets = &lt;&amp;tegra_car 14&gt;;</div><div class='ctx'> 		reset-names = "sdhci";</div><div class='ctx'> 		pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",</div><div class='hunk'>@@ -1136,6 +1315,8 @@</div><div class='ctx'> 		nvidia,pad-autocal-pull-down-offset-3v3 = &lt;0x7d&gt;;</div><div class='ctx'> 		nvidia,pad-autocal-pull-up-offset-1v8 = &lt;0x7b&gt;;</div><div class='ctx'> 		nvidia,pad-autocal-pull-down-offset-1v8 = &lt;0x7b&gt;;</div><div class='add'>+		nvidia,pad-autocal-pull-up-offset-sdr104 = &lt;0x0&gt;;</div><div class='add'>+		nvidia,pad-autocal-pull-down-offset-sdr104 = &lt;0x0&gt;;</div><div class='ctx'> 		nvidia,default-tap = &lt;0x2&gt;;</div><div class='ctx'> 		nvidia,default-trim = &lt;0x4&gt;;</div><div class='ctx'> 		assigned-clocks = &lt;&amp;tegra_car TEGRA210_CLK_SDMMC4&gt;,</div><div class='hunk'>@@ -1146,12 +1327,13 @@</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sdhci@700b0200 {</div><div class='del'>-		compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";</div><div class='add'>+	mmc@700b0200 {</div><div class='add'>+		compatible = "nvidia,tegra210-sdhci";</div><div class='ctx'> 		reg = &lt;0x0 0x700b0200 0x0 0x200&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-		clocks = &lt;&amp;tegra_car TEGRA210_CLK_SDMMC2&gt;;</div><div class='del'>-		clock-names = "sdhci";</div><div class='add'>+		clocks = &lt;&amp;tegra_car TEGRA210_CLK_SDMMC2&gt;,</div><div class='add'>+			 &lt;&amp;tegra_car TEGRA210_CLK_SDMMC_LEGACY&gt;;</div><div class='add'>+		clock-names = "sdhci", "tmclk";</div><div class='ctx'> 		resets = &lt;&amp;tegra_car 9&gt;;</div><div class='ctx'> 		reset-names = "sdhci";</div><div class='ctx'> 		pinctrl-names = "sdmmc-1v8-drv";</div><div class='hunk'>@@ -1163,12 +1345,13 @@</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sdhci@700b0400 {</div><div class='del'>-		compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";</div><div class='add'>+	mmc@700b0400 {</div><div class='add'>+		compatible = "nvidia,tegra210-sdhci";</div><div class='ctx'> 		reg = &lt;0x0 0x700b0400 0x0 0x200&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-		clocks = &lt;&amp;tegra_car TEGRA210_CLK_SDMMC3&gt;;</div><div class='del'>-		clock-names = "sdhci";</div><div class='add'>+		clocks = &lt;&amp;tegra_car TEGRA210_CLK_SDMMC3&gt;,</div><div class='add'>+			 &lt;&amp;tegra_car TEGRA210_CLK_SDMMC_LEGACY&gt;;</div><div class='add'>+		clock-names = "sdhci", "tmclk";</div><div class='ctx'> 		resets = &lt;&amp;tegra_car 69&gt;;</div><div class='ctx'> 		reset-names = "sdhci";</div><div class='ctx'> 		pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",</div><div class='hunk'>@@ -1186,12 +1369,13 @@</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	sdhci@700b0600 {</div><div class='del'>-		compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";</div><div class='add'>+	mmc@700b0600 {</div><div class='add'>+		compatible = "nvidia,tegra210-sdhci";</div><div class='ctx'> 		reg = &lt;0x0 0x700b0600 0x0 0x200&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-		clocks = &lt;&amp;tegra_car TEGRA210_CLK_SDMMC4&gt;;</div><div class='del'>-		clock-names = "sdhci";</div><div class='add'>+		clocks = &lt;&amp;tegra_car TEGRA210_CLK_SDMMC4&gt;,</div><div class='add'>+			 &lt;&amp;tegra_car TEGRA210_CLK_SDMMC_LEGACY&gt;;</div><div class='add'>+		clock-names = "sdhci", "tmclk";</div><div class='ctx'> 		resets = &lt;&amp;tegra_car 15&gt;;</div><div class='ctx'> 		reset-names = "sdhci";</div><div class='ctx'> 		pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv";</div><div class='hunk'>@@ -1228,6 +1412,32 @@</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	soctherm: thermal-sensor@700e2000 {</div><div class='add'>+		compatible = "nvidia,tegra210-soctherm";</div><div class='add'>+		reg = &lt;0x0 0x700e2000 0x0 0x600&gt;, /* SOC_THERM reg_base */</div><div class='add'>+		      &lt;0x0 0x60006000 0x0 0x400&gt;; /* CAR reg_base */</div><div class='add'>+		reg-names = "soctherm-reg", "car-reg";</div><div class='add'>+		interrupts = &lt;GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-names = "thermal", "edp";</div><div class='add'>+		clocks = &lt;&amp;tegra_car TEGRA210_CLK_TSENSOR&gt;,</div><div class='add'>+			&lt;&amp;tegra_car TEGRA210_CLK_SOC_THERM&gt;;</div><div class='add'>+		clock-names = "tsensor", "soctherm";</div><div class='add'>+		resets = &lt;&amp;tegra_car 78&gt;;</div><div class='add'>+		reset-names = "soctherm";</div><div class='add'>+		#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		throttle-cfgs {</div><div class='add'>+			throttle_heavy: heavy {</div><div class='add'>+				nvidia,priority = &lt;100&gt;;</div><div class='add'>+				nvidia,cpu-throt-percent = &lt;85&gt;;</div><div class='add'>+				nvidia,gpu-throt-level = &lt;TEGRA_SOCTHERM_THROT_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				#cooling-cells = &lt;2&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	mipi: mipi@700e3000 {</div><div class='ctx'> 		compatible = "nvidia,tegra210-mipi";</div><div class='ctx'> 		reg = &lt;0x0 0x700e3000 0x0 0x100&gt;;</div><div class='hunk'>@@ -1248,8 +1458,9 @@</div><div class='ctx'> 			 &lt;&amp;tegra_car TEGRA210_CLK_DFLL_REF&gt;,</div><div class='ctx'> 			 &lt;&amp;tegra_car TEGRA210_CLK_I2C5&gt;;</div><div class='ctx'> 		clock-names = "soc", "ref", "i2c";</div><div class='del'>-		resets = &lt;&amp;tegra_car TEGRA210_RST_DFLL_DVCO&gt;;</div><div class='del'>-		reset-names = "dvco";</div><div class='add'>+		resets = &lt;&amp;tegra_car TEGRA210_RST_DFLL_DVCO&gt;,</div><div class='add'>+			 &lt;&amp;tegra_car 155&gt;;</div><div class='add'>+		reset-names = "dvco", "dfll";</div><div class='ctx'> 		#clock-cells = &lt;0&gt;;</div><div class='ctx'> 		clock-output-names = "dfllCPU_out";</div><div class='ctx'> 		status = "disabled";</div><div class='hunk'>@@ -1266,7 +1477,433 @@</div><div class='ctx'> 		ranges = &lt;0x702c0000 0x0 0x702c0000 0x00040000&gt;;</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> </div><div class='del'>-		adma: dma@702e2000 {</div><div class='add'>+		tegra_ahub: ahub@702d0800 {</div><div class='add'>+			compatible = "nvidia,tegra210-ahub";</div><div class='add'>+			reg = &lt;0x702d0800 0x800&gt;;</div><div class='add'>+			clocks = &lt;&amp;tegra_car TEGRA210_CLK_D_AUDIO&gt;;</div><div class='add'>+			clock-names = "ahub";</div><div class='add'>+			assigned-clocks = &lt;&amp;tegra_car TEGRA210_CLK_D_AUDIO&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;tegra_car TEGRA210_CLK_PLL_P&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;81600000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges = &lt;0x702d0000 0x702d0000 0x0000e400&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			tegra_admaif: admaif@702d0000 {</div><div class='add'>+				compatible = "nvidia,tegra210-admaif";</div><div class='add'>+				reg = &lt;0x702d0000 0x800&gt;;</div><div class='add'>+				dmas = &lt;&amp;adma 1&gt;,  &lt;&amp;adma 1&gt;,</div><div class='add'>+				       &lt;&amp;adma 2&gt;,  &lt;&amp;adma 2&gt;,</div><div class='add'>+				       &lt;&amp;adma 3&gt;,  &lt;&amp;adma 3&gt;,</div><div class='add'>+				       &lt;&amp;adma 4&gt;,  &lt;&amp;adma 4&gt;,</div><div class='add'>+				       &lt;&amp;adma 5&gt;,  &lt;&amp;adma 5&gt;,</div><div class='add'>+				       &lt;&amp;adma 6&gt;,  &lt;&amp;adma 6&gt;,</div><div class='add'>+				       &lt;&amp;adma 7&gt;,  &lt;&amp;adma 7&gt;,</div><div class='add'>+				       &lt;&amp;adma 8&gt;,  &lt;&amp;adma 8&gt;,</div><div class='add'>+				       &lt;&amp;adma 9&gt;,  &lt;&amp;adma 9&gt;,</div><div class='add'>+				       &lt;&amp;adma 10&gt;, &lt;&amp;adma 10&gt;;</div><div class='add'>+				dma-names = "rx1",  "tx1",</div><div class='add'>+					    "rx2",  "tx2",</div><div class='add'>+					    "rx3",  "tx3",</div><div class='add'>+					    "rx4",  "tx4",</div><div class='add'>+					    "rx5",  "tx5",</div><div class='add'>+					    "rx6",  "tx6",</div><div class='add'>+					    "rx7",  "tx7",</div><div class='add'>+					    "rx8",  "tx8",</div><div class='add'>+					    "rx9",  "tx9",</div><div class='add'>+					    "rx10", "tx10";</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					admaif1_port: port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						admaif1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					admaif2_port: port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						admaif2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					admaif3_port: port@2 {</div><div class='add'>+						reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+						admaif3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					admaif4_port: port@3 {</div><div class='add'>+						reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+						admaif4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					admaif5_port: port@4 {</div><div class='add'>+						reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+						admaif5_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif5_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					admaif6_port: port@5 {</div><div class='add'>+						reg = &lt;5&gt;;</div><div class='add'>+</div><div class='add'>+						admaif6_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif6_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					admaif7_port: port@6 {</div><div class='add'>+						reg = &lt;6&gt;;</div><div class='add'>+</div><div class='add'>+						admaif7_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif7_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					admaif8_port: port@7 {</div><div class='add'>+						reg = &lt;7&gt;;</div><div class='add'>+</div><div class='add'>+						admaif8_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif8_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					admaif9_port: port@8 {</div><div class='add'>+						reg = &lt;8&gt;;</div><div class='add'>+</div><div class='add'>+						admaif9_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif9_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					admaif10_port: port@9 {</div><div class='add'>+						reg = &lt;9&gt;;</div><div class='add'>+</div><div class='add'>+						admaif10_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;xbar_admaif10_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_i2s1: i2s@702d1000 {</div><div class='add'>+				compatible = "nvidia,tegra210-i2s";</div><div class='add'>+				reg = &lt;0x702d1000 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;tegra_car TEGRA210_CLK_I2S0&gt;,</div><div class='add'>+					 &lt;&amp;tegra_car TEGRA210_CLK_I2S0_SYNC&gt;;</div><div class='add'>+				clock-names = "i2s", "sync_input";</div><div class='add'>+				assigned-clocks = &lt;&amp;tegra_car TEGRA210_CLK_I2S0&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;tegra_car TEGRA210_CLK_PLL_A_OUT0&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;1536000&gt;;</div><div class='add'>+				sound-name-prefix = "I2S1";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_i2s2: i2s@702d1100 {</div><div class='add'>+				compatible = "nvidia,tegra210-i2s";</div><div class='add'>+				reg = &lt;0x702d1100 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;tegra_car TEGRA210_CLK_I2S1&gt;,</div><div class='add'>+					 &lt;&amp;tegra_car TEGRA210_CLK_I2S1_SYNC&gt;;</div><div class='add'>+				clock-names = "i2s", "sync_input";</div><div class='add'>+				assigned-clocks = &lt;&amp;tegra_car TEGRA210_CLK_I2S1&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;tegra_car TEGRA210_CLK_PLL_A_OUT0&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;1536000&gt;;</div><div class='add'>+				sound-name-prefix = "I2S2";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_i2s3: i2s@702d1200 {</div><div class='add'>+				compatible = "nvidia,tegra210-i2s";</div><div class='add'>+				reg = &lt;0x702d1200 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;tegra_car TEGRA210_CLK_I2S2&gt;,</div><div class='add'>+					 &lt;&amp;tegra_car TEGRA210_CLK_I2S2_SYNC&gt;;</div><div class='add'>+				clock-names = "i2s", "sync_input";</div><div class='add'>+				assigned-clocks = &lt;&amp;tegra_car TEGRA210_CLK_I2S2&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;tegra_car TEGRA210_CLK_PLL_A_OUT0&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;1536000&gt;;</div><div class='add'>+				sound-name-prefix = "I2S3";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_i2s4: i2s@702d1300 {</div><div class='add'>+				compatible = "nvidia,tegra210-i2s";</div><div class='add'>+				reg = &lt;0x702d1300 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;tegra_car TEGRA210_CLK_I2S3&gt;,</div><div class='add'>+					 &lt;&amp;tegra_car TEGRA210_CLK_I2S3_SYNC&gt;;</div><div class='add'>+				clock-names = "i2s", "sync_input";</div><div class='add'>+				assigned-clocks = &lt;&amp;tegra_car TEGRA210_CLK_I2S3&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;tegra_car TEGRA210_CLK_PLL_A_OUT0&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;1536000&gt;;</div><div class='add'>+				sound-name-prefix = "I2S4";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_i2s5: i2s@702d1400 {</div><div class='add'>+				compatible = "nvidia,tegra210-i2s";</div><div class='add'>+				reg = &lt;0x702d1400 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;tegra_car TEGRA210_CLK_I2S4&gt;,</div><div class='add'>+					 &lt;&amp;tegra_car TEGRA210_CLK_I2S4_SYNC&gt;;</div><div class='add'>+				clock-names = "i2s", "sync_input";</div><div class='add'>+				assigned-clocks = &lt;&amp;tegra_car TEGRA210_CLK_I2S4&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;tegra_car TEGRA210_CLK_PLL_A_OUT0&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;1536000&gt;;</div><div class='add'>+				sound-name-prefix = "I2S5";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_sfc1: sfc@702d2000 {</div><div class='add'>+				compatible = "nvidia,tegra210-sfc";</div><div class='add'>+				reg = &lt;0x702d2000 0x200&gt;;</div><div class='add'>+				sound-name-prefix = "SFC1";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_sfc2: sfc@702d2200 {</div><div class='add'>+				compatible = "nvidia,tegra210-sfc";</div><div class='add'>+				reg = &lt;0x702d2200 0x200&gt;;</div><div class='add'>+				sound-name-prefix = "SFC2";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_sfc3: sfc@702d2400 {</div><div class='add'>+				compatible = "nvidia,tegra210-sfc";</div><div class='add'>+				reg = &lt;0x702d2400 0x200&gt;;</div><div class='add'>+				sound-name-prefix = "SFC3";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_sfc4: sfc@702d2600 {</div><div class='add'>+				compatible = "nvidia,tegra210-sfc";</div><div class='add'>+				reg = &lt;0x702d2600 0x200&gt;;</div><div class='add'>+				sound-name-prefix = "SFC4";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_amx1: amx@702d3000 {</div><div class='add'>+				compatible = "nvidia,tegra210-amx";</div><div class='add'>+				reg = &lt;0x702d3000 0x100&gt;;</div><div class='add'>+				sound-name-prefix = "AMX1";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_amx2: amx@702d3100 {</div><div class='add'>+				compatible = "nvidia,tegra210-amx";</div><div class='add'>+				reg = &lt;0x702d3100 0x100&gt;;</div><div class='add'>+				sound-name-prefix = "AMX2";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_adx1: adx@702d3800 {</div><div class='add'>+				compatible = "nvidia,tegra210-adx";</div><div class='add'>+				reg = &lt;0x702d3800 0x100&gt;;</div><div class='add'>+				sound-name-prefix = "ADX1";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_adx2: adx@702d3900 {</div><div class='add'>+				compatible = "nvidia,tegra210-adx";</div><div class='add'>+				reg = &lt;0x702d3900 0x100&gt;;</div><div class='add'>+				sound-name-prefix = "ADX2";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_dmic1: dmic@702d4000 {</div><div class='add'>+				compatible = "nvidia,tegra210-dmic";</div><div class='add'>+				reg = &lt;0x702d4000 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;tegra_car TEGRA210_CLK_DMIC1&gt;;</div><div class='add'>+				clock-names = "dmic";</div><div class='add'>+				assigned-clocks = &lt;&amp;tegra_car TEGRA210_CLK_DMIC1&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;tegra_car TEGRA210_CLK_PLL_A_OUT0&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;3072000&gt;;</div><div class='add'>+				sound-name-prefix = "DMIC1";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_dmic2: dmic@702d4100 {</div><div class='add'>+				compatible = "nvidia,tegra210-dmic";</div><div class='add'>+				reg = &lt;0x702d4100 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;tegra_car TEGRA210_CLK_DMIC2&gt;;</div><div class='add'>+				clock-names = "dmic";</div><div class='add'>+				assigned-clocks = &lt;&amp;tegra_car TEGRA210_CLK_DMIC2&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;tegra_car TEGRA210_CLK_PLL_A_OUT0&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;3072000&gt;;</div><div class='add'>+				sound-name-prefix = "DMIC2";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_dmic3: dmic@702d4200 {</div><div class='add'>+				compatible = "nvidia,tegra210-dmic";</div><div class='add'>+				reg = &lt;0x702d4200 0x100&gt;;</div><div class='add'>+				clocks = &lt;&amp;tegra_car TEGRA210_CLK_DMIC3&gt;;</div><div class='add'>+				clock-names = "dmic";</div><div class='add'>+				assigned-clocks = &lt;&amp;tegra_car TEGRA210_CLK_DMIC3&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;tegra_car TEGRA210_CLK_PLL_A_OUT0&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;3072000&gt;;</div><div class='add'>+				sound-name-prefix = "DMIC3";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_ope1: processing-engine@702d8000 {</div><div class='add'>+				compatible = "nvidia,tegra210-ope";</div><div class='add'>+				reg = &lt;0x702d8000 0x100&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;1&gt;;</div><div class='add'>+				ranges;</div><div class='add'>+				sound-name-prefix = "OPE1";</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				equalizer@702d8100 {</div><div class='add'>+					compatible = "nvidia,tegra210-peq";</div><div class='add'>+					reg = &lt;0x702d8100 0x100&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				dynamic-range-compressor@702d8200 {</div><div class='add'>+					compatible = "nvidia,tegra210-mbdrc";</div><div class='add'>+					reg = &lt;0x702d8200 0x200&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_ope2: processing-engine@702d8400 {</div><div class='add'>+				compatible = "nvidia,tegra210-ope";</div><div class='add'>+				reg = &lt;0x702d8400 0x100&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;1&gt;;</div><div class='add'>+				ranges;</div><div class='add'>+				sound-name-prefix = "OPE2";</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				equalizer@702d8500 {</div><div class='add'>+					compatible = "nvidia,tegra210-peq";</div><div class='add'>+					reg = &lt;0x702d8500 0x100&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				dynamic-range-compressor@702d8600 {</div><div class='add'>+					compatible = "nvidia,tegra210-mbdrc";</div><div class='add'>+					reg = &lt;0x702d8600 0x200&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_mvc1: mvc@702da000 {</div><div class='add'>+				compatible = "nvidia,tegra210-mvc";</div><div class='add'>+				reg = &lt;0x702da000 0x200&gt;;</div><div class='add'>+				sound-name-prefix = "MVC1";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_mvc2: mvc@702da200 {</div><div class='add'>+				compatible = "nvidia,tegra210-mvc";</div><div class='add'>+				reg = &lt;0x702da200 0x200&gt;;</div><div class='add'>+				sound-name-prefix = "MVC2";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_amixer: amixer@702dbb00 {</div><div class='add'>+				compatible = "nvidia,tegra210-amixer";</div><div class='add'>+				reg = &lt;0x702dbb00 0x800&gt;;</div><div class='add'>+				sound-name-prefix = "MIXER1";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0x0&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif1_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif1_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;0x1&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif2_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif2_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@2 {</div><div class='add'>+					reg = &lt;0x2&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif3_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif3_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@3 {</div><div class='add'>+					reg = &lt;0x3&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif4_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif4_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@4 {</div><div class='add'>+					reg = &lt;0x4&gt;;</div><div class='add'>+					xbar_admaif5_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif5_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+				port@5 {</div><div class='add'>+					reg = &lt;0x5&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif6_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif6_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@6 {</div><div class='add'>+					reg = &lt;0x6&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif7_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif7_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@7 {</div><div class='add'>+					reg = &lt;0x7&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif8_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif8_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@8 {</div><div class='add'>+					reg = &lt;0x8&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif9_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif9_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@9 {</div><div class='add'>+					reg = &lt;0x9&gt;;</div><div class='add'>+</div><div class='add'>+					xbar_admaif10_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;admaif10_ep&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		adma: dma-controller@702e2000 {</div><div class='ctx'> 			compatible = "nvidia,tegra210-adma";</div><div class='ctx'> 			reg = &lt;0x702e2000 0x2000&gt;;</div><div class='ctx'> 			interrupt-parent = &lt;&amp;agic&gt;;</div><div class='hunk'>@@ -1298,7 +1935,7 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		agic: agic@702f9000 {</div><div class='add'>+		agic: interrupt-controller@702f9000 {</div><div class='ctx'> 			compatible = "nvidia,tegra210-agic";</div><div class='ctx'> 			#interrupt-cells = &lt;3&gt;;</div><div class='ctx'> 			interrupt-controller;</div><div class='hunk'>@@ -1317,17 +1954,17 @@</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;0&gt;;</div><div class='del'>-		clocks = &lt;&amp;tegra_car TEGRA210_CLK_QSPI&gt;;</div><div class='del'>-		clock-names = "qspi";</div><div class='add'>+		clocks = &lt;&amp;tegra_car TEGRA210_CLK_QSPI&gt;,</div><div class='add'>+			 &lt;&amp;tegra_car TEGRA210_CLK_QSPI_PM&gt;;</div><div class='add'>+		clock-names = "qspi", "qspi_out";</div><div class='ctx'> 		resets = &lt;&amp;tegra_car 211&gt;;</div><div class='del'>-		reset-names = "qspi";</div><div class='ctx'> 		dmas = &lt;&amp;apbdma 5&gt;, &lt;&amp;apbdma 5&gt;;</div><div class='ctx'> 		dma-names = "rx", "tx";</div><div class='ctx'> 		status = "disabled";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	usb@7d000000 {</div><div class='del'>-		compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";</div><div class='add'>+		compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci";</div><div class='ctx'> 		reg = &lt;0x0 0x7d000000 0x0 0x4000&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		phy_type = "utmi";</div><div class='hunk'>@@ -1365,7 +2002,7 @@</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	usb@7d004000 {</div><div class='del'>-		compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";</div><div class='add'>+		compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci";</div><div class='ctx'> 		reg = &lt;0x0 0x7d004000 0x0 0x4000&gt;;</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 		phy_type = "utmi";</div><div class='hunk'>@@ -1460,11 +2097,13 @@</div><div class='ctx'> </div><div class='ctx'> 		L2: l2-cache {</div><div class='ctx'> 			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	pmu {</div><div class='del'>-		compatible = "arm,armv8-pmuv3";</div><div class='add'>+		compatible = "arm,cortex-a57-pmu";</div><div class='ctx'> 		interrupts = &lt;GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 			     &lt;GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='ctx'> 			     &lt;GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='hunk'>@@ -1473,47 +2112,22 @@</div><div class='ctx'> 				      &amp;{/cpus/cpu@2} &amp;{/cpus/cpu@3}&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	timer {</div><div class='del'>-		compatible = "arm,armv8-timer";</div><div class='del'>-		interrupts = &lt;GIC_PPI 13</div><div class='del'>-				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='del'>-			     &lt;GIC_PPI 14</div><div class='del'>-				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='del'>-			     &lt;GIC_PPI 11</div><div class='del'>-				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='del'>-			     &lt;GIC_PPI 10</div><div class='del'>-				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='del'>-		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='del'>-		arm,no-tick-in-suspend;</div><div class='del'>-	};</div><div class='add'>+	sound {</div><div class='add'>+		status = "disabled";</div><div class='ctx'> </div><div class='del'>-	soctherm: thermal-sensor@700e2000 {</div><div class='del'>-		compatible = "nvidia,tegra210-soctherm";</div><div class='del'>-		reg = &lt;0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */</div><div class='del'>-			0x0 0x60006000 0x0 0x400&gt;; /* CAR reg_base */</div><div class='del'>-		reg-names = "soctherm-reg", "car-reg";</div><div class='del'>-		interrupts = &lt;GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-			     &lt;GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-		interrupt-names = "thermal", "edp";</div><div class='del'>-		clocks = &lt;&amp;tegra_car TEGRA210_CLK_TSENSOR&gt;,</div><div class='del'>-			&lt;&amp;tegra_car TEGRA210_CLK_SOC_THERM&gt;;</div><div class='del'>-		clock-names = "tsensor", "soctherm";</div><div class='del'>-		resets = &lt;&amp;tegra_car 78&gt;;</div><div class='del'>-		reset-names = "soctherm";</div><div class='del'>-		#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+		clocks = &lt;&amp;tegra_car TEGRA210_CLK_PLL_A&gt;,</div><div class='add'>+			 &lt;&amp;tegra_car TEGRA210_CLK_PLL_A_OUT0&gt;;</div><div class='add'>+		clock-names = "pll_a", "plla_out0";</div><div class='ctx'> </div><div class='del'>-		throttle-cfgs {</div><div class='del'>-			throttle_heavy: heavy {</div><div class='del'>-				nvidia,priority = &lt;100&gt;;</div><div class='del'>-				nvidia,cpu-throt-percent = &lt;85&gt;;</div><div class='del'>-</div><div class='del'>-				#cooling-cells = &lt;2&gt;;</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='add'>+		assigned-clocks = &lt;&amp;tegra_car TEGRA210_CLK_PLL_A&gt;,</div><div class='add'>+				  &lt;&amp;tegra_car TEGRA210_CLK_PLL_A_OUT0&gt;,</div><div class='add'>+				  &lt;&amp;tegra_car TEGRA210_CLK_EXTERN1&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;, &lt;0&gt;, &lt;&amp;tegra_car TEGRA210_CLK_PLL_A_OUT0&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;368640000&gt;, &lt;49152000&gt;, &lt;12288000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	thermal-zones {</div><div class='del'>-		cpu {</div><div class='add'>+		cpu-thermal {</div><div class='ctx'> 			polling-delay-passive = &lt;1000&gt;;</div><div class='ctx'> 			polling-delay = &lt;0&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -1542,7 +2156,7 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		mem {</div><div class='add'>+		mem-thermal {</div><div class='ctx'> 			polling-delay-passive = &lt;0&gt;;</div><div class='ctx'> 			polling-delay = &lt;0&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -1550,6 +2164,24 @@</div><div class='ctx'> 				&lt;&amp;soctherm TEGRA124_SOCTHERM_SENSOR_MEM&gt;;</div><div class='ctx'> </div><div class='ctx'> 			trips {</div><div class='add'>+				dram_nominal: mem-nominal-trip {</div><div class='add'>+					temperature = &lt;50000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				dram_throttle: mem-throttle-trip {</div><div class='add'>+					temperature = &lt;70000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "active";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				mem-hot-trip {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='ctx'> 				mem-shutdown-trip {</div><div class='ctx'> 					temperature = &lt;103000&gt;;</div><div class='ctx'> 					hysteresis = &lt;0&gt;;</div><div class='hunk'>@@ -1558,14 +2190,19 @@</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			cooling-maps {</div><div class='del'>-				/*</div><div class='del'>-				 * There are currently no cooling maps,</div><div class='del'>-				 * because there are no cooling devices.</div><div class='del'>-				 */</div><div class='add'>+				dram-passive {</div><div class='add'>+					cooling-device = &lt;&amp;emc 0 0&gt;;</div><div class='add'>+					trip = &lt;&amp;dram_nominal&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				dram-active {</div><div class='add'>+					cooling-device = &lt;&amp;emc 1 1&gt;;</div><div class='add'>+					trip = &lt;&amp;dram_throttle&gt;;</div><div class='add'>+				};</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		gpu {</div><div class='add'>+		gpu-thermal {</div><div class='ctx'> 			polling-delay-passive = &lt;1000&gt;;</div><div class='ctx'> 			polling-delay = &lt;0&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -1594,7 +2231,7 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		pllx {</div><div class='add'>+		pllx-thermal {</div><div class='ctx'> 			polling-delay-passive = &lt;0&gt;;</div><div class='ctx'> 			polling-delay = &lt;0&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -1607,6 +2244,12 @@</div><div class='ctx'> 					hysteresis = &lt;0&gt;;</div><div class='ctx'> 					type = "critical";</div><div class='ctx'> 				};</div><div class='add'>+</div><div class='add'>+				pllx-throttle-trip {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='ctx'> 			cooling-maps {</div><div class='hunk'>@@ -1617,4 +2260,18 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13</div><div class='add'>+				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14</div><div class='add'>+				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11</div><div class='add'>+				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10</div><div class='add'>+				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		arm,no-tick-in-suspend;</div><div class='add'>+	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi<br/>new file mode 100644<br/>index 000000000000..d977f4901c09<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi</a></div><div class='hunk'>@@ -0,0 +1,30 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+</div><div class='add'>+#include "tegra234-p3701.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "NVIDIA Jetson AGX Orin";</div><div class='add'>+	compatible = "nvidia,p3701-0000", "nvidia,tegra234";</div><div class='add'>+</div><div class='add'>+	thermal-zones {</div><div class='add'>+		tj-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;1000&gt;;</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				tj_trip_active0: active-0 {</div><div class='add'>+					temperature = &lt;75000&gt;;</div><div class='add'>+					hysteresis = &lt;4000&gt;;</div><div class='add'>+					type = "active";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tj_trip_active1: active-1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;4000&gt;;</div><div class='add'>+					type = "active";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0008.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0008.dtsi<br/>new file mode 100644<br/>index 000000000000..0809634e5732<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra234-p3701-0008.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/tegra234-p3701-0008.dtsi</a></div><div class='hunk'>@@ -0,0 +1,29 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+</div><div class='add'>+#include "tegra234-p3701.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "nvidia,p3701-0008", "nvidia,tegra234";</div><div class='add'>+</div><div class='add'>+	thermal-zones {</div><div class='add'>+		tj-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;1000&gt;;</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				tj_trip_active0: active-0 {</div><div class='add'>+					temperature = &lt;85000&gt;;</div><div class='add'>+					hysteresis = &lt;4000&gt;;</div><div class='add'>+					type = "active";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tj_trip_active1: active-1 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;4000&gt;;</div><div class='add'>+					type = "active";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3701.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3701.dtsi<br/>new file mode 100644<br/>index 000000000000..58bf55c0e414<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra234-p3701.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/tegra234-p3701.dtsi</a></div><div class='hunk'>@@ -0,0 +1,237 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+</div><div class='add'>+#include "tegra234.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "nvidia,p3701", "nvidia,tegra234";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		mmc0 = "/bus@0/mmc@3460000";</div><div class='add'>+		mmc1 = "/bus@0/mmc@3400000";</div><div class='add'>+		rtc0 = "/bpmp/i2c/pmic@3c";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bus@0 {</div><div class='add'>+		aconnect@2900000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			ahub@2900800 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				i2s@2901000 {</div><div class='add'>+					status = "okay";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				i2s@2901100 {</div><div class='add'>+					status = "okay";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				i2s@2901300 {</div><div class='add'>+					status = "okay";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				i2s@2901500 {</div><div class='add'>+					status = "okay";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				dmic@2904200 {</div><div class='add'>+					status = "okay";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			dma-controller@2930000 {</div><div class='add'>+				status = "okay";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			interrupt-controller@2a40000 {</div><div class='add'>+				status = "okay";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@3160000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			eeprom@50 {</div><div class='add'>+				compatible = "atmel,24c02";</div><div class='add'>+				reg = &lt;0x50&gt;;</div><div class='add'>+</div><div class='add'>+				label = "module";</div><div class='add'>+				vcc-supply = &lt;&amp;vdd_1v8_hs&gt;;</div><div class='add'>+				address-width = &lt;8&gt;;</div><div class='add'>+				pagesize = &lt;8&gt;;</div><div class='add'>+				size = &lt;256&gt;;</div><div class='add'>+				read-only;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi@3270000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			flash@0 {</div><div class='add'>+				compatible = "jedec,spi-nor";</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				spi-max-frequency = &lt;102000000&gt;;</div><div class='add'>+				spi-tx-bus-width = &lt;4&gt;;</div><div class='add'>+				spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmc@3460000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+			bus-width = &lt;8&gt;;</div><div class='add'>+			non-removable;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		padctl@3520000 {</div><div class='add'>+			vclamp-usb-supply = &lt;&amp;vdd_1v8_ao&gt;;</div><div class='add'>+			avdd-usb-supply = &lt;&amp;vdd_3v3_ao&gt;;</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				usb2-0 {</div><div class='add'>+					vbus-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usb2-1 {</div><div class='add'>+					vbus-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usb2-2 {</div><div class='add'>+					vbus-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usb2-3 {</div><div class='add'>+					vbus-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@c240000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			power-sensor@40 {</div><div class='add'>+				compatible = "ti,ina3221";</div><div class='add'>+				reg = &lt;0x40&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				input@0 {</div><div class='add'>+					reg = &lt;0x0&gt;;</div><div class='add'>+					label = "VDD_GPU_SOC";</div><div class='add'>+					shunt-resistor-micro-ohms = &lt;2000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				input@1 {</div><div class='add'>+					reg = &lt;0x1&gt;;</div><div class='add'>+					label = "VDD_CPU_CV";</div><div class='add'>+					shunt-resistor-micro-ohms = &lt;2000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				input@2 {</div><div class='add'>+					reg = &lt;0x2&gt;;</div><div class='add'>+					label = "VIN_SYS_5V0";</div><div class='add'>+					shunt-resistor-micro-ohms = &lt;2000&gt;;</div><div class='add'>+					ti,summation-disable;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			power-sensor@41 {</div><div class='add'>+				compatible = "ti,ina3221";</div><div class='add'>+				reg = &lt;0x41&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				input@0 {</div><div class='add'>+					reg = &lt;0x0&gt;;</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				input@1 {</div><div class='add'>+					reg = &lt;0x1&gt;;</div><div class='add'>+					label = "VDDQ_VDD2_1V8AO";</div><div class='add'>+					shunt-resistor-micro-ohms = &lt;2000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				input@2 {</div><div class='add'>+					reg = &lt;0x2&gt;;</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rtc@c2a0000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmc@c360000 {</div><div class='add'>+			nvidia,invert-interrupt;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bpmp {</div><div class='add'>+		i2c {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			pmic@3c {</div><div class='add'>+				compatible = "nvidia,vrs-10";</div><div class='add'>+				reg = &lt;0x3c&gt;;</div><div class='add'>+				interrupt-parent = &lt;&amp;pmc&gt;;</div><div class='add'>+				/* VRS Wake ID is 24 */</div><div class='add'>+				interrupts = &lt;24 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			thermal-sensor@4c {</div><div class='add'>+				compatible = "ti,tmp451";</div><div class='add'>+				status = "okay";</div><div class='add'>+				reg = &lt;0x4c&gt;;</div><div class='add'>+				vcc-supply = &lt;&amp;vdd_1v8_ao&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		thermal {</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_1v8_ao: regulator-vdd-1v8-ao {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_1V8_AO";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_1v8_hs: regulator-vdd-1v8-hs {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_1V8_HS";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_1v8_ls: regulator-vdd-1v8-ls {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_1V8_LS";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_3v3_ao: regulator-vdd-3v3-ao {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_3V3_AO";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_5v0_sys: regulator-vdd-5v0-sys {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VIN_SYS_5V0";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts<br/>new file mode 100644<br/>index 000000000000..4c0e96f9d493<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts</a></div><div class='hunk'>@@ -0,0 +1,11 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+// Module files must be included first</div><div class='add'>+#include "tegra234-p3701-0000.dtsi"</div><div class='add'>+#include "tegra234-p3737-0000+p3701.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "NVIDIA Jetson AGX Orin Developer Kit";</div><div class='add'>+	compatible = "nvidia,p3737-0000+p3701-0000", "nvidia,p3701-0000", "nvidia,tegra234";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0008.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0008.dts<br/>new file mode 100644<br/>index 000000000000..979f085691a1<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0008.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0008.dts</a></div><div class='hunk'>@@ -0,0 +1,11 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+// Module files must be included first</div><div class='add'>+#include "tegra234-p3701-0008.dtsi"</div><div class='add'>+#include "tegra234-p3737-0000+p3701.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "NVIDIA Jetson AGX Orin Developer Kit";</div><div class='add'>+	compatible = "nvidia,p3737-0000+p3701-0008", "nvidia,p3701-0008", "nvidia,tegra234";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701.dtsi<br/>new file mode 100644<br/>index 000000000000..f6cad29355e6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701.dtsi</a></div><div class='hunk'>@@ -0,0 +1,547 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/tegra234-clock.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/tegra234-gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/linux-event-codes.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/gpio-keys.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/rt5640.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;tcu;</div><div class='add'>+		serial1 = &amp;uarta;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		bootargs = "console=ttyTCU0,115200n8";</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bus@0 {</div><div class='add'>+		aconnect@2900000 {</div><div class='add'>+			ahub@2900800 {</div><div class='add'>+				i2s@2901000 {</div><div class='add'>+					ports {</div><div class='add'>+						port@1 {</div><div class='add'>+							endpoint {</div><div class='add'>+								dai-format = "i2s";</div><div class='add'>+								remote-endpoint = &lt;&amp;rt5640_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		serial@3100000 {</div><div class='add'>+			compatible = "nvidia,tegra194-hsuart";</div><div class='add'>+			reset-names = "serial";</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@3160000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			eeprom@56 {</div><div class='add'>+				compatible = "atmel,24c02";</div><div class='add'>+				reg = &lt;0x56&gt;;</div><div class='add'>+</div><div class='add'>+				label = "system";</div><div class='add'>+				vcc-supply = &lt;&amp;vdd_1v8_sys&gt;;</div><div class='add'>+				address-width = &lt;8&gt;;</div><div class='add'>+				pagesize = &lt;8&gt;;</div><div class='add'>+				size = &lt;256&gt;;</div><div class='add'>+				read-only;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		serial@31d0000 {</div><div class='add'>+			current-speed = &lt;115200&gt;;</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@31e0000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			audio-codec@1c {</div><div class='add'>+				compatible = "realtek,rt5640";</div><div class='add'>+				reg = &lt;0x1c&gt;;</div><div class='add'>+				interrupt-parent = &lt;&amp;gpio&gt;;</div><div class='add'>+				interrupts = &lt;TEGRA234_MAIN_GPIO(AC, 5) GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;bpmp TEGRA234_CLK_AUD_MCLK&gt;;</div><div class='add'>+				clock-names = "mclk";</div><div class='add'>+				realtek,dmic1-data-pin = &lt;RT5640_DMIC1_DATA_PIN_NONE&gt;;</div><div class='add'>+				realtek,dmic2-data-pin = &lt;RT5640_DMIC2_DATA_PIN_NONE&gt;;</div><div class='add'>+				realtek,jack-detect-source = &lt;RT5640_JD_SRC_HDA_HEADER&gt;;</div><div class='add'>+				sound-name-prefix = "CVB-RT";</div><div class='add'>+</div><div class='add'>+				port {</div><div class='add'>+					rt5640_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;i2s1_dap&gt;;</div><div class='add'>+						mclk-fs = &lt;256&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pwm@3280000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pwm@32a0000 {</div><div class='add'>+			assigned-clocks = &lt;&amp;bpmp TEGRA234_CLK_PWM3&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;bpmp TEGRA234_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pwm@32c0000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pwm@32f0000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmc@3400000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+			bus-width = &lt;4&gt;;</div><div class='add'>+			cd-gpios = &lt;&amp;gpio TEGRA234_MAIN_GPIO(G, 7) GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			disable-wp;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		hda@3510000 {</div><div class='add'>+			nvidia,model = "NVIDIA Jetson AGX Orin HDA";</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		padctl@3520000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			pads {</div><div class='add'>+				usb2 {</div><div class='add'>+					lanes {</div><div class='add'>+						usb2-0 {</div><div class='add'>+							status = "okay";</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						usb2-1 {</div><div class='add'>+							status = "okay";</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						usb2-2 {</div><div class='add'>+							status = "okay";</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						usb2-3 {</div><div class='add'>+							status = "okay";</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usb3 {</div><div class='add'>+					lanes {</div><div class='add'>+						usb3-0 {</div><div class='add'>+							status = "okay";</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						usb3-1 {</div><div class='add'>+							status = "okay";</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						usb3-2 {</div><div class='add'>+							status = "okay";</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				usb2-0 {</div><div class='add'>+					mode = "otg";</div><div class='add'>+					usb-role-switch;</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					port {</div><div class='add'>+						hs_typec_p1: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;hs_ucsi_ccg_p1&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usb2-1 {</div><div class='add'>+					mode = "host";</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					port {</div><div class='add'>+						hs_typec_p0: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;hs_ucsi_ccg_p0&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usb2-2 {</div><div class='add'>+					mode = "host";</div><div class='add'>+					status = "okay";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usb2-3 {</div><div class='add'>+					mode = "host";</div><div class='add'>+					status = "okay";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usb3-0 {</div><div class='add'>+					nvidia,usb2-companion = &lt;1&gt;;</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					port {</div><div class='add'>+						ss_typec_p0: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;ss_ucsi_ccg_p0&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usb3-1 {</div><div class='add'>+					nvidia,usb2-companion = &lt;0&gt;;</div><div class='add'>+					status = "okay";</div><div class='add'>+</div><div class='add'>+					port {</div><div class='add'>+						ss_typec_p1: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;ss_ucsi_ccg_p1&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usb3-2 {</div><div class='add'>+					nvidia,usb2-companion = &lt;3&gt;;</div><div class='add'>+					status = "okay";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb@3550000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}&gt;,</div><div class='add'>+			       &lt;&amp;{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}&gt;;</div><div class='add'>+			phy-names = "usb2-0", "usb3-0";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb@3610000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}&gt;,</div><div class='add'>+			       &lt;&amp;{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}&gt;,</div><div class='add'>+			       &lt;&amp;{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-2}&gt;,</div><div class='add'>+			       &lt;&amp;{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-3}&gt;,</div><div class='add'>+			       &lt;&amp;{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-0}&gt;,</div><div class='add'>+			       &lt;&amp;{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}&gt;,</div><div class='add'>+			       &lt;&amp;{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-2}&gt;;</div><div class='add'>+			phy-names = "usb2-0", "usb2-1", "usb2-2", "usb2-3",</div><div class='add'>+				    "usb3-0", "usb3-1", "usb3-2";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ethernet@6800000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			phy-handle = &lt;&amp;mgbe0_phy&gt;;</div><div class='add'>+			phy-mode = "10gbase-r";</div><div class='add'>+</div><div class='add'>+			mdio {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				mgbe0_phy: phy@0 {</div><div class='add'>+					compatible = "ethernet-phy-ieee802.3-c45";</div><div class='add'>+					reg = &lt;0x0&gt;;</div><div class='add'>+</div><div class='add'>+					#phy-cells = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@c240000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			typec@8 {</div><div class='add'>+				compatible = "cypress,cypd4226";</div><div class='add'>+				reg = &lt;0x08&gt;;</div><div class='add'>+				interrupt-parent = &lt;&amp;gpio&gt;;</div><div class='add'>+				interrupts = &lt;TEGRA234_MAIN_GPIO(Y, 4) IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+				firmware-name = "nvidia,jetson-agx-xavier";</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				ccg_typec_con0: connector@0 {</div><div class='add'>+					compatible = "usb-c-connector";</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					label = "USB-C";</div><div class='add'>+					data-role = "host";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							hs_ucsi_ccg_p0: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;hs_typec_p0&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							ss_ucsi_ccg_p0: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;ss_typec_p0&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				ccg_typec_con1: connector@1 {</div><div class='add'>+					compatible = "usb-c-connector";</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					label = "USB-C";</div><div class='add'>+					data-role = "dual";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							hs_ucsi_ccg_p1: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;hs_typec_p1&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							ss_ucsi_ccg_p1: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;ss_typec_p1&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie@14100000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			vddio-pex-ctl-supply = &lt;&amp;vdd_1v8_ao&gt;;</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;p2u_hsio_3&gt;;</div><div class='add'>+			phy-names = "p2u-0";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie@14160000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			vddio-pex-ctl-supply = &lt;&amp;vdd_1v8_ao&gt;;</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;p2u_hsio_4&gt;, &lt;&amp;p2u_hsio_5&gt;, &lt;&amp;p2u_hsio_6&gt;,</div><div class='add'>+			       &lt;&amp;p2u_hsio_7&gt;;</div><div class='add'>+			phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie@141a0000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			vddio-pex-ctl-supply = &lt;&amp;vdd_1v8_ls&gt;;</div><div class='add'>+			vpcie3v3-supply = &lt;&amp;vdd_3v3_pcie&gt;;</div><div class='add'>+			vpcie12v-supply = &lt;&amp;vdd_12v_pcie&gt;;</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;p2u_nvhs_0&gt;, &lt;&amp;p2u_nvhs_1&gt;, &lt;&amp;p2u_nvhs_2&gt;,</div><div class='add'>+			       &lt;&amp;p2u_nvhs_3&gt;, &lt;&amp;p2u_nvhs_4&gt;, &lt;&amp;p2u_nvhs_5&gt;,</div><div class='add'>+			       &lt;&amp;p2u_nvhs_6&gt;, &lt;&amp;p2u_nvhs_7&gt;;</div><div class='add'>+			phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",</div><div class='add'>+				    "p2u-5", "p2u-6", "p2u-7";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie-ep@141a0000 {</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			vddio-pex-ctl-supply = &lt;&amp;vdd_1v8_ls&gt;;</div><div class='add'>+</div><div class='add'>+			reset-gpios = &lt;&amp;gpio TEGRA234_MAIN_GPIO(AF, 1) GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+			nvidia,refclk-select-gpios = &lt;&amp;gpio_aon</div><div class='add'>+						      TEGRA234_AON_GPIO(AA, 4)</div><div class='add'>+						      GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;p2u_nvhs_0&gt;, &lt;&amp;p2u_nvhs_1&gt;, &lt;&amp;p2u_nvhs_2&gt;,</div><div class='add'>+			       &lt;&amp;p2u_nvhs_3&gt;, &lt;&amp;p2u_nvhs_4&gt;, &lt;&amp;p2u_nvhs_5&gt;,</div><div class='add'>+			       &lt;&amp;p2u_nvhs_6&gt;, &lt;&amp;p2u_nvhs_7&gt;;</div><div class='add'>+			phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",</div><div class='add'>+				    "p2u-5", "p2u-6", "p2u-7";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		status = "okay";</div><div class='add'>+</div><div class='add'>+		key-force-recovery {</div><div class='add'>+			label = "Force Recovery";</div><div class='add'>+			gpios = &lt;&amp;gpio TEGRA234_MAIN_GPIO(G, 0) GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,input-type = &lt;EV_KEY&gt;;</div><div class='add'>+			linux,code = &lt;BTN_1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-power {</div><div class='add'>+			label = "Power";</div><div class='add'>+			gpios = &lt;&amp;gpio_aon TEGRA234_AON_GPIO(EE, 4) GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,input-type = &lt;EV_KEY&gt;;</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+			wakeup-event-action = &lt;EV_ACT_ASSERTED&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-suspend {</div><div class='add'>+			label = "Suspend";</div><div class='add'>+			gpios = &lt;&amp;gpio TEGRA234_MAIN_GPIO(G, 2) GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,input-type = &lt;EV_KEY&gt;;</div><div class='add'>+			linux,code = &lt;KEY_SLEEP&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fan: pwm-fan {</div><div class='add'>+		compatible = "pwm-fan";</div><div class='add'>+		cooling-levels = &lt;66 215 255&gt;;</div><div class='add'>+		pwms = &lt;&amp;pwm3 0 45334&gt;;</div><div class='add'>+		#cooling-cells = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	serial {</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "nvidia,tegra186-audio-graph-card";</div><div class='add'>+		status = "okay";</div><div class='add'>+</div><div class='add'>+		dais = /* ADMAIF (FE) Ports */</div><div class='add'>+		       &lt;&amp;admaif0_port&gt;, &lt;&amp;admaif1_port&gt;, &lt;&amp;admaif2_port&gt;, &lt;&amp;admaif3_port&gt;,</div><div class='add'>+		       &lt;&amp;admaif4_port&gt;, &lt;&amp;admaif5_port&gt;, &lt;&amp;admaif6_port&gt;, &lt;&amp;admaif7_port&gt;,</div><div class='add'>+		       &lt;&amp;admaif8_port&gt;, &lt;&amp;admaif9_port&gt;, &lt;&amp;admaif10_port&gt;, &lt;&amp;admaif11_port&gt;,</div><div class='add'>+		       &lt;&amp;admaif12_port&gt;, &lt;&amp;admaif13_port&gt;, &lt;&amp;admaif14_port&gt;, &lt;&amp;admaif15_port&gt;,</div><div class='add'>+		       &lt;&amp;admaif16_port&gt;, &lt;&amp;admaif17_port&gt;, &lt;&amp;admaif18_port&gt;, &lt;&amp;admaif19_port&gt;,</div><div class='add'>+		       /* XBAR Ports */</div><div class='add'>+		       &lt;&amp;xbar_i2s1_port&gt;, &lt;&amp;xbar_i2s2_port&gt;, &lt;&amp;xbar_i2s4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_i2s6_port&gt;, &lt;&amp;xbar_dmic3_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_sfc1_in_port&gt;, &lt;&amp;xbar_sfc2_in_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_sfc3_in_port&gt;, &lt;&amp;xbar_sfc4_in_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mvc1_in_port&gt;, &lt;&amp;xbar_mvc2_in_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx1_in1_port&gt;, &lt;&amp;xbar_amx1_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx1_in3_port&gt;, &lt;&amp;xbar_amx1_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx2_in1_port&gt;, &lt;&amp;xbar_amx2_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx2_in3_port&gt;, &lt;&amp;xbar_amx2_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx3_in1_port&gt;, &lt;&amp;xbar_amx3_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx3_in3_port&gt;, &lt;&amp;xbar_amx3_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx4_in1_port&gt;, &lt;&amp;xbar_amx4_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx4_in3_port&gt;, &lt;&amp;xbar_amx4_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_adx1_in_port&gt;, &lt;&amp;xbar_adx2_in_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_adx3_in_port&gt;, &lt;&amp;xbar_adx4_in_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mix_in1_port&gt;, &lt;&amp;xbar_mix_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mix_in3_port&gt;, &lt;&amp;xbar_mix_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mix_in5_port&gt;, &lt;&amp;xbar_mix_in6_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mix_in7_port&gt;, &lt;&amp;xbar_mix_in8_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mix_in9_port&gt;, &lt;&amp;xbar_mix_in10_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_asrc_in1_port&gt;, &lt;&amp;xbar_asrc_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_asrc_in3_port&gt;, &lt;&amp;xbar_asrc_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_asrc_in5_port&gt;, &lt;&amp;xbar_asrc_in6_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_asrc_in7_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_ope1_in_port&gt;,</div><div class='add'>+		       /* HW accelerators */</div><div class='add'>+		       &lt;&amp;sfc1_out_port&gt;, &lt;&amp;sfc2_out_port&gt;,</div><div class='add'>+		       &lt;&amp;sfc3_out_port&gt;, &lt;&amp;sfc4_out_port&gt;,</div><div class='add'>+		       &lt;&amp;mvc1_out_port&gt;, &lt;&amp;mvc2_out_port&gt;,</div><div class='add'>+		       &lt;&amp;amx1_out_port&gt;, &lt;&amp;amx2_out_port&gt;,</div><div class='add'>+		       &lt;&amp;amx3_out_port&gt;, &lt;&amp;amx4_out_port&gt;,</div><div class='add'>+		       &lt;&amp;adx1_out1_port&gt;, &lt;&amp;adx1_out2_port&gt;,</div><div class='add'>+		       &lt;&amp;adx1_out3_port&gt;, &lt;&amp;adx1_out4_port&gt;,</div><div class='add'>+		       &lt;&amp;adx2_out1_port&gt;, &lt;&amp;adx2_out2_port&gt;,</div><div class='add'>+		       &lt;&amp;adx2_out3_port&gt;, &lt;&amp;adx2_out4_port&gt;,</div><div class='add'>+		       &lt;&amp;adx3_out1_port&gt;, &lt;&amp;adx3_out2_port&gt;,</div><div class='add'>+		       &lt;&amp;adx3_out3_port&gt;, &lt;&amp;adx3_out4_port&gt;,</div><div class='add'>+		       &lt;&amp;adx4_out1_port&gt;, &lt;&amp;adx4_out2_port&gt;,</div><div class='add'>+		       &lt;&amp;adx4_out3_port&gt;, &lt;&amp;adx4_out4_port&gt;,</div><div class='add'>+		       &lt;&amp;mix_out1_port&gt;, &lt;&amp;mix_out2_port&gt;, &lt;&amp;mix_out3_port&gt;,</div><div class='add'>+		       &lt;&amp;mix_out4_port&gt;, &lt;&amp;mix_out5_port&gt;,</div><div class='add'>+		       &lt;&amp;asrc_out1_port&gt;, &lt;&amp;asrc_out2_port&gt;, &lt;&amp;asrc_out3_port&gt;,</div><div class='add'>+		       &lt;&amp;asrc_out4_port&gt;, &lt;&amp;asrc_out5_port&gt;, &lt;&amp;asrc_out6_port&gt;,</div><div class='add'>+		       &lt;&amp;ope1_out_port&gt;,</div><div class='add'>+		       /* BE I/O Ports */</div><div class='add'>+		       &lt;&amp;i2s1_port&gt;, &lt;&amp;i2s2_port&gt;, &lt;&amp;i2s4_port&gt;, &lt;&amp;i2s6_port&gt;,</div><div class='add'>+		       &lt;&amp;dmic3_port&gt;;</div><div class='add'>+</div><div class='add'>+		label = "NVIDIA Jetson AGX Orin APE";</div><div class='add'>+</div><div class='add'>+		widgets = "Microphone",	"CVB-RT MIC Jack",</div><div class='add'>+			  "Microphone",	"CVB-RT MIC",</div><div class='add'>+			  "Headphone",	"CVB-RT HP Jack",</div><div class='add'>+			  "Speaker",	"CVB-RT SPK";</div><div class='add'>+</div><div class='add'>+		routing = /* I2S1 &lt;-&gt; RT5640 */</div><div class='add'>+			  "CVB-RT AIF1 Playback",	"I2S1 DAP-Playback",</div><div class='add'>+			  "I2S1 DAP-Capture",		"CVB-RT AIF1 Capture",</div><div class='add'>+			  /* RT5640 codec controls */</div><div class='add'>+			  "CVB-RT HP Jack",		"CVB-RT HPOL",</div><div class='add'>+			  "CVB-RT HP Jack",		"CVB-RT HPOR",</div><div class='add'>+			  "CVB-RT IN1P",		"CVB-RT MIC Jack",</div><div class='add'>+			  "CVB-RT IN2P",		"CVB-RT MIC Jack",</div><div class='add'>+			  "CVB-RT SPK",			"CVB-RT SPOLP",</div><div class='add'>+			  "CVB-RT SPK",			"CVB-RT SPORP",</div><div class='add'>+			  "CVB-RT DMIC1",		"CVB-RT MIC",</div><div class='add'>+			  "CVB-RT DMIC2",		"CVB-RT MIC";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	thermal-zones {</div><div class='add'>+		tj-thermal {</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map-active-0 {</div><div class='add'>+					cooling-device = &lt;&amp;fan 0 1&gt;;</div><div class='add'>+					trip = &lt;&amp;tj_trip_active0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				map-active-1 {</div><div class='add'>+					cooling-device = &lt;&amp;fan 1 2&gt;;</div><div class='add'>+					trip = &lt;&amp;tj_trip_active1&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_1v8_sys: regulator-vdd-1v8-sys {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_1V8_SYS";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_3v3_pcie: regulator-vdd-3v3-pcie {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_3V3_PCIE";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio TEGRA234_MAIN_GPIO(H, 4) GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_12v_pcie: regulator-vdd-12v-pcie {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_12V_PCIE";</div><div class='add'>+		regulator-min-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;12000000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio TEGRA234_MAIN_GPIO(A, 1) GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts<br/>new file mode 100644<br/>index 000000000000..9ce55b4d2de8<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts</a></div><div class='hunk'>@@ -0,0 +1,476 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/input/linux-event-codes.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/gpio-keys.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/rt5640.h&gt;</div><div class='add'>+#include "tegra234-p3701-0008.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "NVIDIA IGX Orin Development Kit";</div><div class='add'>+	compatible = "nvidia,p3740-0002+p3701-0008", "nvidia,p3701-0008", "nvidia,tegra234";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;tcu;</div><div class='add'>+		serial1 = &amp;uarta;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bus@0 {</div><div class='add'>+		aconnect@2900000 {</div><div class='add'>+			ahub@2900800 {</div><div class='add'>+				i2s@2901300 {</div><div class='add'>+					ports {</div><div class='add'>+						port@1 {</div><div class='add'>+							endpoint {</div><div class='add'>+								dai-format = "i2s";</div><div class='add'>+								remote-endpoint = &lt;&amp;rt5640_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				i2s@2901500 {</div><div class='add'>+					ports {</div><div class='add'>+						port@1 {</div><div class='add'>+							endpoint {</div><div class='add'>+								bitclock-master;</div><div class='add'>+								frame-master;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		serial@3100000 {</div><div class='add'>+			compatible = "nvidia,tegra194-hsuart";</div><div class='add'>+			reset-names = "serial";</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@3160000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@3180000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@3190000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@31b0000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@31c0000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			rt5640: audio-codec@1c {</div><div class='add'>+				compatible = "realtek,rt5640";</div><div class='add'>+				reg = &lt;0x1c&gt;;</div><div class='add'>+				interrupt-parent = &lt;&amp;gpio&gt;;</div><div class='add'>+				interrupts = &lt;TEGRA234_MAIN_GPIO(F, 3) GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;bpmp TEGRA234_CLK_AUD_MCLK&gt;;</div><div class='add'>+				clock-names = "mclk";</div><div class='add'>+</div><div class='add'>+				realtek,dmic1-data-pin = &lt;RT5640_DMIC1_DATA_PIN_NONE&gt;;</div><div class='add'>+				realtek,dmic2-data-pin = &lt;RT5640_DMIC2_DATA_PIN_NONE&gt;;</div><div class='add'>+				realtek,jack-detect-source = &lt;RT5640_JD_SRC_HDA_HEADER&gt;;</div><div class='add'>+</div><div class='add'>+				sound-name-prefix = "CVB-RT";</div><div class='add'>+</div><div class='add'>+				port {</div><div class='add'>+					rt5640_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;i2s4_dap&gt;;</div><div class='add'>+						mclk-fs = &lt;256&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			/* carrier board ID EEPROM */</div><div class='add'>+			eeprom@55 {</div><div class='add'>+				compatible = "atmel,24c02";</div><div class='add'>+				reg = &lt;0x55&gt;;</div><div class='add'>+</div><div class='add'>+				label = "system";</div><div class='add'>+				vcc-supply = &lt;&amp;vdd_1v8_ls&gt;;</div><div class='add'>+				address-width = &lt;8&gt;;</div><div class='add'>+				pagesize = &lt;8&gt;;</div><div class='add'>+				size = &lt;256&gt;;</div><div class='add'>+				read-only;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@31e0000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi@3270000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		hda@3510000 {</div><div class='add'>+			nvidia,model = "NVIDIA IGX Orin HDA";</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		padctl@3520000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			pads {</div><div class='add'>+				usb2 {</div><div class='add'>+					lanes {</div><div class='add'>+						usb2-0 {</div><div class='add'>+							nvidia,function = "xusb";</div><div class='add'>+							status = "okay";</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						usb2-1 {</div><div class='add'>+							nvidia,function = "xusb";</div><div class='add'>+							status = "okay";</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						usb2-2 {</div><div class='add'>+							nvidia,function = "xusb";</div><div class='add'>+							status = "okay";</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						usb2-3 {</div><div class='add'>+							nvidia,function = "xusb";</div><div class='add'>+							status = "okay";</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usb3 {</div><div class='add'>+					lanes {</div><div class='add'>+						usb3-0 {</div><div class='add'>+							nvidia,function = "xusb";</div><div class='add'>+							status = "okay";</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						usb3-1 {</div><div class='add'>+							nvidia,function = "xusb";</div><div class='add'>+							status = "okay";</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						usb3-2 {</div><div class='add'>+							nvidia,function = "xusb";</div><div class='add'>+							status = "okay";</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				usb2-0 {</div><div class='add'>+					mode = "otg";</div><div class='add'>+					usb-role-switch;</div><div class='add'>+					status = "okay";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usb2-1 {</div><div class='add'>+					mode = "host";</div><div class='add'>+					status = "okay";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usb2-2 {</div><div class='add'>+					mode = "host";</div><div class='add'>+					status = "okay";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usb2-3 {</div><div class='add'>+					mode = "host";</div><div class='add'>+					status = "okay";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usb3-0 {</div><div class='add'>+					nvidia,usb2-companion = &lt;2&gt;;</div><div class='add'>+					status = "okay";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usb3-1 {</div><div class='add'>+					nvidia,usb2-companion = &lt;0&gt;;</div><div class='add'>+					status = "okay";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usb3-2 {</div><div class='add'>+					nvidia,usb2-companion = &lt;1&gt;;</div><div class='add'>+					status = "okay";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb@3550000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}&gt;,</div><div class='add'>+				&lt;&amp;{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}&gt;;</div><div class='add'>+			phy-names = "usb2-0", "usb3-0";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb@3610000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			phys =	&lt;&amp;{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}&gt;,</div><div class='add'>+				&lt;&amp;{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}&gt;,</div><div class='add'>+				&lt;&amp;{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-2}&gt;,</div><div class='add'>+				&lt;&amp;{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-3}&gt;,</div><div class='add'>+				&lt;&amp;{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-0}&gt;,</div><div class='add'>+				&lt;&amp;{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}&gt;,</div><div class='add'>+				&lt;&amp;{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-2}&gt;;</div><div class='add'>+			phy-names = "usb2-0", "usb2-1", "usb2-2", "usb2-3",</div><div class='add'>+				"usb3-0", "usb3-1", "usb3-2";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		fuse@3810000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@c240000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@c250000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			power-sensor@41 {</div><div class='add'>+				compatible = "ti,ina3221";</div><div class='add'>+				reg = &lt;0x41&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				input@0 {</div><div class='add'>+					reg = &lt;0x0&gt;;</div><div class='add'>+					label = "CVB_ATX_12V";</div><div class='add'>+					shunt-resistor-micro-ohms = &lt;2000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				input@1 {</div><div class='add'>+					reg = &lt;0x1&gt;;</div><div class='add'>+					label = "CVB_ATX_3V3";</div><div class='add'>+					shunt-resistor-micro-ohms = &lt;2000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				input@2 {</div><div class='add'>+					reg = &lt;0x2&gt;;</div><div class='add'>+					label = "CVB_ATX_5V";</div><div class='add'>+					shunt-resistor-micro-ohms = &lt;2000&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			power-sensor@44 {</div><div class='add'>+				compatible = "ti,ina219";</div><div class='add'>+				reg = &lt;0x44&gt;;</div><div class='add'>+				shunt-resistor = &lt;2000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		host1x@13e00000 {</div><div class='add'>+			nvdec@15480000 {</div><div class='add'>+				status = "okay";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie@140e0000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+			vddio-pex-ctl-supply = &lt;&amp;vdd_1v8_ls&gt;;</div><div class='add'>+			phys = &lt;&amp;p2u_gbe_4&gt;, &lt;&amp;p2u_gbe_5&gt;;</div><div class='add'>+			phy-names = "p2u-0", "p2u-1";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie@14100000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+			vddio-pex-ctl-supply = &lt;&amp;vdd_1v8_ao&gt;;</div><div class='add'>+			vpcie3v3-supply = &lt;&amp;vdd_3v3_wifi&gt;;</div><div class='add'>+			phys = &lt;&amp;p2u_hsio_3&gt;;</div><div class='add'>+			phy-names = "p2u-0";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie@14160000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+			vddio-pex-ctl-supply = &lt;&amp;vdd_1v8_ao&gt;;</div><div class='add'>+			phys = &lt;&amp;p2u_hsio_7&gt;, &lt;&amp;p2u_hsio_6&gt;, &lt;&amp;p2u_hsio_5&gt;,</div><div class='add'>+			       &lt;&amp;p2u_hsio_4&gt;;</div><div class='add'>+			phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie@141a0000 {</div><div class='add'>+			reg = &lt;0x00 0x141a0000 0x0 0x00020000   /* appl registers (128K)      */</div><div class='add'>+			       0x00 0x3a000000 0x0 0x00040000   /* configuration space (256K) */</div><div class='add'>+			       0x00 0x3a040000 0x0 0x00040000   /* iATU_DMA reg space (256K)  */</div><div class='add'>+			       0x00 0x3a080000 0x0 0x00040000   /* DBI reg space (256K)       */</div><div class='add'>+			       0x2e 0x20000000 0x0 0x10000000&gt;; /* ECAM (256MB)               */</div><div class='add'>+</div><div class='add'>+			ranges = &lt;0x81000000 0x00 0x3a100000 0x00 0x3a100000 0x0 0x00100000      /* downstream I/O (1MB) */</div><div class='add'>+				  0x82000000 0x00 0x40000000 0x2e 0x30000000 0x0 0x08000000      /* non-prefetchable memory (128MB) */</div><div class='add'>+				  0xc3000000 0x28 0x00000000 0x28 0x00000000 0x6 0x20000000&gt;;    /* prefetchable memory (25088MB) */</div><div class='add'>+</div><div class='add'>+			status = "okay";</div><div class='add'>+			vddio-pex-ctl-supply = &lt;&amp;vdd_1v8_ls&gt;;</div><div class='add'>+			phys = &lt;&amp;p2u_nvhs_0&gt;, &lt;&amp;p2u_nvhs_1&gt;, &lt;&amp;p2u_nvhs_2&gt;,</div><div class='add'>+				&lt;&amp;p2u_nvhs_3&gt;, &lt;&amp;p2u_nvhs_4&gt;, &lt;&amp;p2u_nvhs_5&gt;,</div><div class='add'>+				&lt;&amp;p2u_nvhs_6&gt;, &lt;&amp;p2u_nvhs_7&gt;;</div><div class='add'>+			phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",</div><div class='add'>+				    "p2u-5", "p2u-6", "p2u-7";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie@141e0000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+			vddio-pex-ctl-supply = &lt;&amp;vdd_1v8_ls&gt;;</div><div class='add'>+			phys = &lt;&amp;p2u_gbe_0&gt;, &lt;&amp;p2u_gbe_1&gt;;</div><div class='add'>+			phy-names = "p2u-0", "p2u-1";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		status = "okay";</div><div class='add'>+</div><div class='add'>+		key-force-recovery {</div><div class='add'>+			label = "Force Recovery";</div><div class='add'>+			gpios = &lt;&amp;gpio TEGRA234_MAIN_GPIO(G, 0) GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,input-type = &lt;EV_KEY&gt;;</div><div class='add'>+			linux,code = &lt;BTN_1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-power {</div><div class='add'>+			label = "Power";</div><div class='add'>+			gpios = &lt;&amp;gpio_aon TEGRA234_AON_GPIO(EE, 4) GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,input-type = &lt;EV_KEY&gt;;</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+			wakeup-event-action = &lt;EV_ACT_ASSERTED&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-suspend {</div><div class='add'>+			label = "Suspend";</div><div class='add'>+			gpios = &lt;&amp;gpio TEGRA234_MAIN_GPIO(G, 2) GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,input-type = &lt;EV_KEY&gt;;</div><div class='add'>+			linux,code = &lt;KEY_SLEEP&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	serial {</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		status = "okay";</div><div class='add'>+</div><div class='add'>+		compatible = "nvidia,tegra186-audio-graph-card";</div><div class='add'>+</div><div class='add'>+		dais = /* ADMAIF (FE) Ports */</div><div class='add'>+		       &lt;&amp;admaif0_port&gt;, &lt;&amp;admaif1_port&gt;, &lt;&amp;admaif2_port&gt;, &lt;&amp;admaif3_port&gt;,</div><div class='add'>+		       &lt;&amp;admaif4_port&gt;, &lt;&amp;admaif5_port&gt;, &lt;&amp;admaif6_port&gt;, &lt;&amp;admaif7_port&gt;,</div><div class='add'>+		       &lt;&amp;admaif8_port&gt;, &lt;&amp;admaif9_port&gt;, &lt;&amp;admaif10_port&gt;, &lt;&amp;admaif11_port&gt;,</div><div class='add'>+		       &lt;&amp;admaif12_port&gt;, &lt;&amp;admaif13_port&gt;, &lt;&amp;admaif14_port&gt;, &lt;&amp;admaif15_port&gt;,</div><div class='add'>+		       &lt;&amp;admaif16_port&gt;, &lt;&amp;admaif17_port&gt;, &lt;&amp;admaif18_port&gt;, &lt;&amp;admaif19_port&gt;,</div><div class='add'>+		       /* XBAR Ports */</div><div class='add'>+		       &lt;&amp;xbar_i2s1_port&gt;, &lt;&amp;xbar_i2s2_port&gt;, &lt;&amp;xbar_i2s4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_i2s6_port&gt;, &lt;&amp;xbar_dmic3_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_sfc1_in_port&gt;, &lt;&amp;xbar_sfc2_in_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_sfc3_in_port&gt;, &lt;&amp;xbar_sfc4_in_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mvc1_in_port&gt;, &lt;&amp;xbar_mvc2_in_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx1_in1_port&gt;, &lt;&amp;xbar_amx1_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx1_in3_port&gt;, &lt;&amp;xbar_amx1_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx2_in1_port&gt;, &lt;&amp;xbar_amx2_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx2_in3_port&gt;, &lt;&amp;xbar_amx2_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx3_in1_port&gt;, &lt;&amp;xbar_amx3_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx3_in3_port&gt;, &lt;&amp;xbar_amx3_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx4_in1_port&gt;, &lt;&amp;xbar_amx4_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx4_in3_port&gt;, &lt;&amp;xbar_amx4_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_adx1_in_port&gt;, &lt;&amp;xbar_adx2_in_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_adx3_in_port&gt;, &lt;&amp;xbar_adx4_in_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mix_in1_port&gt;, &lt;&amp;xbar_mix_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mix_in3_port&gt;, &lt;&amp;xbar_mix_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mix_in5_port&gt;, &lt;&amp;xbar_mix_in6_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mix_in7_port&gt;, &lt;&amp;xbar_mix_in8_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mix_in9_port&gt;, &lt;&amp;xbar_mix_in10_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_asrc_in1_port&gt;, &lt;&amp;xbar_asrc_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_asrc_in3_port&gt;, &lt;&amp;xbar_asrc_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_asrc_in5_port&gt;, &lt;&amp;xbar_asrc_in6_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_asrc_in7_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_ope1_in_port&gt;,</div><div class='add'>+		       /* HW accelerators */</div><div class='add'>+		       &lt;&amp;sfc1_out_port&gt;, &lt;&amp;sfc2_out_port&gt;,</div><div class='add'>+		       &lt;&amp;sfc3_out_port&gt;, &lt;&amp;sfc4_out_port&gt;,</div><div class='add'>+		       &lt;&amp;mvc1_out_port&gt;, &lt;&amp;mvc2_out_port&gt;,</div><div class='add'>+		       &lt;&amp;amx1_out_port&gt;, &lt;&amp;amx2_out_port&gt;,</div><div class='add'>+		       &lt;&amp;amx3_out_port&gt;, &lt;&amp;amx4_out_port&gt;,</div><div class='add'>+		       &lt;&amp;adx1_out1_port&gt;, &lt;&amp;adx1_out2_port&gt;,</div><div class='add'>+		       &lt;&amp;adx1_out3_port&gt;, &lt;&amp;adx1_out4_port&gt;,</div><div class='add'>+		       &lt;&amp;adx2_out1_port&gt;, &lt;&amp;adx2_out2_port&gt;,</div><div class='add'>+		       &lt;&amp;adx2_out3_port&gt;, &lt;&amp;adx2_out4_port&gt;,</div><div class='add'>+		       &lt;&amp;adx3_out1_port&gt;, &lt;&amp;adx3_out2_port&gt;,</div><div class='add'>+		       &lt;&amp;adx3_out3_port&gt;, &lt;&amp;adx3_out4_port&gt;,</div><div class='add'>+		       &lt;&amp;adx4_out1_port&gt;, &lt;&amp;adx4_out2_port&gt;,</div><div class='add'>+		       &lt;&amp;adx4_out3_port&gt;, &lt;&amp;adx4_out4_port&gt;,</div><div class='add'>+		       &lt;&amp;mix_out1_port&gt;, &lt;&amp;mix_out2_port&gt;, &lt;&amp;mix_out3_port&gt;,</div><div class='add'>+		       &lt;&amp;mix_out4_port&gt;, &lt;&amp;mix_out5_port&gt;,</div><div class='add'>+		       &lt;&amp;asrc_out1_port&gt;, &lt;&amp;asrc_out2_port&gt;, &lt;&amp;asrc_out3_port&gt;,</div><div class='add'>+		       &lt;&amp;asrc_out4_port&gt;, &lt;&amp;asrc_out5_port&gt;, &lt;&amp;asrc_out6_port&gt;,</div><div class='add'>+		       &lt;&amp;ope1_out_port&gt;,</div><div class='add'>+		       /* BE I/O Ports */</div><div class='add'>+		       &lt;&amp;i2s1_port&gt;, &lt;&amp;i2s2_port&gt;, &lt;&amp;i2s4_port&gt;, &lt;&amp;i2s6_port&gt;,</div><div class='add'>+		       &lt;&amp;dmic3_port&gt;;</div><div class='add'>+</div><div class='add'>+		label = "NVIDIA IGX Orin APE";</div><div class='add'>+</div><div class='add'>+		widgets = "Microphone",	"CVB-RT MIC Jack",</div><div class='add'>+			  "Microphone",	"CVB-RT MIC",</div><div class='add'>+			  "Headphone",	"CVB-RT HP Jack",</div><div class='add'>+			  "Speaker",	"CVB-RT SPK";</div><div class='add'>+</div><div class='add'>+		routing = /* I2S4 &lt;-&gt; RT5640 */</div><div class='add'>+			  "CVB-RT AIF1 Playback",	"I2S4 DAP-Playback",</div><div class='add'>+			  "I2S4 DAP-Capture",		"CVB-RT AIF1 Capture",</div><div class='add'>+			  /* RT5640 codec controls */</div><div class='add'>+			  "CVB-RT HP Jack",		"CVB-RT HPOL",</div><div class='add'>+			  "CVB-RT HP Jack",		"CVB-RT HPOR",</div><div class='add'>+			  "CVB-RT IN1P",		"CVB-RT MIC Jack",</div><div class='add'>+			  "CVB-RT IN2P",		"CVB-RT MIC Jack",</div><div class='add'>+			  "CVB-RT IN2N",		"CVB-RT MIC Jack",</div><div class='add'>+			  "CVB-RT IN3P",		"CVB-RT MIC Jack",</div><div class='add'>+			  "CVB-RT SPK",			"CVB-RT SPOLP",</div><div class='add'>+			  "CVB-RT SPK",			"CVB-RT SPORP",</div><div class='add'>+			  "CVB-RT SPK",			"CVB-RT LOUTL",</div><div class='add'>+			  "CVB-RT SPK",			"CVB-RT LOUTR",</div><div class='add'>+			  "CVB-RT DMIC1",		"CVB-RT MIC",</div><div class='add'>+			  "CVB-RT DMIC2",		"CVB-RT MIC";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_3v3_dp: regulator-vdd-3v3-dp {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_3V3_DP";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vdd_3v3_sys&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio TEGRA234_MAIN_GPIO(H, 6) 0&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_3v3_sys: regulator-vdd-3v3-sys {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_3V3_SYS";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_3v3_wifi: regulator-vdd-3v3-wifi {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_3V3_WIFI";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio TEGRA234_MAIN_GPIO(G, 3) GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi<br/>new file mode 100644<br/>index 000000000000..ab391a71c3d3<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi</a></div><div class='hunk'>@@ -0,0 +1,258 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+</div><div class='add'>+#include "tegra234.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "nvidia,p3767", "nvidia,tegra234";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		mmc0 = "/bus@0/mmc@3400000";</div><div class='add'>+		rtc0 = "/bpmp/i2c/pmic@3c";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bus@0 {</div><div class='add'>+		aconnect@2900000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			ahub@2900800 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				i2s@2901100 {</div><div class='add'>+					status = "okay";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				i2s@2901300 {</div><div class='add'>+					status = "okay";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			dma-controller@2930000 {</div><div class='add'>+				status = "okay";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			interrupt-controller@2a40000 {</div><div class='add'>+				status = "okay";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@3160000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			eeprom@50 {</div><div class='add'>+				compatible = "atmel,24c02";</div><div class='add'>+				reg = &lt;0x50&gt;;</div><div class='add'>+</div><div class='add'>+				label = "module";</div><div class='add'>+				vcc-supply = &lt;&amp;vdd_1v8_hs&gt;;</div><div class='add'>+				address-width = &lt;8&gt;;</div><div class='add'>+				pagesize = &lt;8&gt;;</div><div class='add'>+				size = &lt;256&gt;;</div><div class='add'>+				read-only;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi@3270000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			flash@0 {</div><div class='add'>+				compatible = "jedec,spi-nor";</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				spi-max-frequency = &lt;102000000&gt;;</div><div class='add'>+				spi-tx-bus-width = &lt;4&gt;;</div><div class='add'>+				spi-rx-bus-width = &lt;4&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * This only exists on Jetson Orin Nano Developer Kit (SKU 5)</div><div class='add'>+		 * but UEFI needs this and will remove it on devices where it</div><div class='add'>+		 * doesn't exist.</div><div class='add'>+		 */</div><div class='add'>+		mmc@3400000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+			bus-width = &lt;4&gt;;</div><div class='add'>+			cd-gpios = &lt;&amp;gpio TEGRA234_MAIN_GPIO(G, 7) GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			disable-wp;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		hda@3510000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		padctl@3520000 {</div><div class='add'>+			vclamp-usb-supply = &lt;&amp;vdd_1v8_ao&gt;;</div><div class='add'>+			avdd-usb-supply = &lt;&amp;vdd_3v3_ao&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@c240000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			power-sensor@40 {</div><div class='add'>+				compatible = "ti,ina3221";</div><div class='add'>+				reg = &lt;0x40&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				input@0 {</div><div class='add'>+					reg = &lt;0x0&gt;;</div><div class='add'>+					label = "VDD_IN";</div><div class='add'>+					shunt-resistor-micro-ohms = &lt;5000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				input@1 {</div><div class='add'>+					reg = &lt;0x1&gt;;</div><div class='add'>+					label = "VDD_CPU_GPU_CV";</div><div class='add'>+					shunt-resistor-micro-ohms = &lt;5000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				input@2 {</div><div class='add'>+					reg = &lt;0x2&gt;;</div><div class='add'>+					label = "VDD_SOC";</div><div class='add'>+					shunt-resistor-micro-ohms = &lt;5000&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rtc@c2a0000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmc@c360000 {</div><div class='add'>+			nvidia,invert-interrupt;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bpmp {</div><div class='add'>+		i2c {</div><div class='add'>+			pmic@3c {</div><div class='add'>+				compatible = "nvidia,vrs-10";</div><div class='add'>+				reg = &lt;0x3c&gt;;</div><div class='add'>+				interrupt-parent = &lt;&amp;pmc&gt;;</div><div class='add'>+				/* VRS Wake ID is 24 */</div><div class='add'>+				interrupts = &lt;24 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_5v0_sys: regulator-vdd-5v0-sys {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_5V0_SYS";</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_1v8_hs: regulator-vdd-1v8-hs {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_1V8_HS";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_1v8_ao: regulator-vdd-1v8-ao {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_1V8_AO";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		vin-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_3v3_ao: regulator-vdd-3v3-ao {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_3V3_AO";</div><div class='add'>+		regulator-min-microvolt = &lt;33000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;33000000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		vin-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "nvidia,tegra186-audio-graph-card";</div><div class='add'>+		status = "okay";</div><div class='add'>+</div><div class='add'>+		dais = /* ADMAIF (FE) Ports */</div><div class='add'>+		       &lt;&amp;admaif0_port&gt;, &lt;&amp;admaif1_port&gt;, &lt;&amp;admaif2_port&gt;, &lt;&amp;admaif3_port&gt;,</div><div class='add'>+		       &lt;&amp;admaif4_port&gt;, &lt;&amp;admaif5_port&gt;, &lt;&amp;admaif6_port&gt;, &lt;&amp;admaif7_port&gt;,</div><div class='add'>+		       &lt;&amp;admaif8_port&gt;, &lt;&amp;admaif9_port&gt;, &lt;&amp;admaif10_port&gt;, &lt;&amp;admaif11_port&gt;,</div><div class='add'>+		       &lt;&amp;admaif12_port&gt;, &lt;&amp;admaif13_port&gt;, &lt;&amp;admaif14_port&gt;, &lt;&amp;admaif15_port&gt;,</div><div class='add'>+		       &lt;&amp;admaif16_port&gt;, &lt;&amp;admaif17_port&gt;, &lt;&amp;admaif18_port&gt;, &lt;&amp;admaif19_port&gt;,</div><div class='add'>+		       /* XBAR Ports */</div><div class='add'>+		       &lt;&amp;xbar_i2s2_port&gt;, &lt;&amp;xbar_i2s4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_sfc1_in_port&gt;, &lt;&amp;xbar_sfc2_in_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_sfc3_in_port&gt;, &lt;&amp;xbar_sfc4_in_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mvc1_in_port&gt;, &lt;&amp;xbar_mvc2_in_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx1_in1_port&gt;, &lt;&amp;xbar_amx1_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx1_in3_port&gt;, &lt;&amp;xbar_amx1_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx2_in1_port&gt;, &lt;&amp;xbar_amx2_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx2_in3_port&gt;, &lt;&amp;xbar_amx2_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx3_in1_port&gt;, &lt;&amp;xbar_amx3_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx3_in3_port&gt;, &lt;&amp;xbar_amx3_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx4_in1_port&gt;, &lt;&amp;xbar_amx4_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx4_in3_port&gt;, &lt;&amp;xbar_amx4_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_adx1_in_port&gt;, &lt;&amp;xbar_adx2_in_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_adx3_in_port&gt;, &lt;&amp;xbar_adx4_in_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mix_in1_port&gt;, &lt;&amp;xbar_mix_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mix_in3_port&gt;, &lt;&amp;xbar_mix_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mix_in5_port&gt;, &lt;&amp;xbar_mix_in6_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mix_in7_port&gt;, &lt;&amp;xbar_mix_in8_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mix_in9_port&gt;, &lt;&amp;xbar_mix_in10_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_asrc_in1_port&gt;, &lt;&amp;xbar_asrc_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_asrc_in3_port&gt;, &lt;&amp;xbar_asrc_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_asrc_in5_port&gt;, &lt;&amp;xbar_asrc_in6_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_asrc_in7_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_ope1_in_port&gt;,</div><div class='add'>+		       /* HW accelerators */</div><div class='add'>+		       &lt;&amp;sfc1_out_port&gt;, &lt;&amp;sfc2_out_port&gt;,</div><div class='add'>+		       &lt;&amp;sfc3_out_port&gt;, &lt;&amp;sfc4_out_port&gt;,</div><div class='add'>+		       &lt;&amp;mvc1_out_port&gt;, &lt;&amp;mvc2_out_port&gt;,</div><div class='add'>+		       &lt;&amp;amx1_out_port&gt;, &lt;&amp;amx2_out_port&gt;,</div><div class='add'>+		       &lt;&amp;amx3_out_port&gt;, &lt;&amp;amx4_out_port&gt;,</div><div class='add'>+		       &lt;&amp;adx1_out1_port&gt;, &lt;&amp;adx1_out2_port&gt;,</div><div class='add'>+		       &lt;&amp;adx1_out3_port&gt;, &lt;&amp;adx1_out4_port&gt;,</div><div class='add'>+		       &lt;&amp;adx2_out1_port&gt;, &lt;&amp;adx2_out2_port&gt;,</div><div class='add'>+		       &lt;&amp;adx2_out3_port&gt;, &lt;&amp;adx2_out4_port&gt;,</div><div class='add'>+		       &lt;&amp;adx3_out1_port&gt;, &lt;&amp;adx3_out2_port&gt;,</div><div class='add'>+		       &lt;&amp;adx3_out3_port&gt;, &lt;&amp;adx3_out4_port&gt;,</div><div class='add'>+		       &lt;&amp;adx4_out1_port&gt;, &lt;&amp;adx4_out2_port&gt;,</div><div class='add'>+		       &lt;&amp;adx4_out3_port&gt;, &lt;&amp;adx4_out4_port&gt;,</div><div class='add'>+		       &lt;&amp;mix_out1_port&gt;, &lt;&amp;mix_out2_port&gt;, &lt;&amp;mix_out3_port&gt;,</div><div class='add'>+		       &lt;&amp;mix_out4_port&gt;, &lt;&amp;mix_out5_port&gt;,</div><div class='add'>+		       &lt;&amp;asrc_out1_port&gt;, &lt;&amp;asrc_out2_port&gt;, &lt;&amp;asrc_out3_port&gt;,</div><div class='add'>+		       &lt;&amp;asrc_out4_port&gt;, &lt;&amp;asrc_out5_port&gt;, &lt;&amp;asrc_out6_port&gt;,</div><div class='add'>+		       &lt;&amp;ope1_out_port&gt;,</div><div class='add'>+		       /* BE I/O Ports */</div><div class='add'>+		       &lt;&amp;i2s2_port&gt;, &lt;&amp;i2s4_port&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	thermal-zones {</div><div class='add'>+		tj-thermal {</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			polling-delay-passive = &lt;1000&gt;;</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				tj_trip_active0: active-0 {</div><div class='add'>+					temperature = &lt;35000&gt;;</div><div class='add'>+					hysteresis = &lt;4000&gt;;</div><div class='add'>+					type = "active";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tj_trip_active1: active-1 {</div><div class='add'>+					temperature = &lt;74000&gt;;</div><div class='add'>+					hysteresis = &lt;4000&gt;;</div><div class='add'>+					type = "active";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tj_trip_active2: active-2 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;4000&gt;;</div><div class='add'>+					type = "active";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0000.dts<br/>new file mode 100644<br/>index 000000000000..5dc974bb360c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0000.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0000.dts</a></div><div class='hunk'>@@ -0,0 +1,19 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "tegra234-p3768-0000+p3767.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "nvidia,p3768-0000+p3767-0000", "nvidia,p3767-0000", "nvidia,tegra234";</div><div class='add'>+	model = "NVIDIA Jetson Orin NX Engineering Reference Developer Kit";</div><div class='add'>+</div><div class='add'>+	bus@0 {</div><div class='add'>+		hda@3510000 {</div><div class='add'>+			nvidia,model = "NVIDIA Jetson Orin NX HDA";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		label = "NVIDIA Jetson Orin NX APE";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0005.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0005.dts<br/>new file mode 100644<br/>index 000000000000..9f5e07012b87<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0005.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0005.dts</a></div><div class='hunk'>@@ -0,0 +1,19 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "tegra234-p3768-0000+p3767.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "nvidia,p3768-0000+p3767-0005", "nvidia,p3767-0005", "nvidia,tegra234";</div><div class='add'>+	model = "NVIDIA Jetson Orin Nano Developer Kit";</div><div class='add'>+</div><div class='add'>+	bus@0 {</div><div class='add'>+		hda@3510000 {</div><div class='add'>+			nvidia,model = "NVIDIA Jetson Orin Nano HDA";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		label = "NVIDIA Jetson Orin Nano APE";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767.dtsi<br/>new file mode 100644<br/>index 000000000000..41821354bbda<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767.dtsi</a></div><div class='hunk'>@@ -0,0 +1,289 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/input/linux-event-codes.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/gpio-keys.h&gt;</div><div class='add'>+</div><div class='add'>+#include "tegra234-p3767.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;tcu;</div><div class='add'>+		serial1 = &amp;uarta;</div><div class='add'>+		serial2 = &amp;uarte;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bus@0 {</div><div class='add'>+		serial@3100000 {</div><div class='add'>+			compatible = "nvidia,tegra194-hsuart";</div><div class='add'>+			reset-names = "serial";</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		serial@3140000 {</div><div class='add'>+			compatible = "nvidia,tegra194-hsuart";</div><div class='add'>+			reset-names = "serial";</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@3160000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			eeprom@57 {</div><div class='add'>+				compatible = "atmel,24c02";</div><div class='add'>+				reg = &lt;0x57&gt;;</div><div class='add'>+</div><div class='add'>+				label = "system";</div><div class='add'>+				vcc-supply = &lt;&amp;vdd_1v8_sys&gt;;</div><div class='add'>+				address-width = &lt;8&gt;;</div><div class='add'>+				pagesize = &lt;8&gt;;</div><div class='add'>+				size = &lt;256&gt;;</div><div class='add'>+				read-only;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		serial@31d0000 {</div><div class='add'>+			current-speed = &lt;115200&gt;;</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pwm@32a0000 {</div><div class='add'>+			assigned-clocks = &lt;&amp;bpmp TEGRA234_CLK_PWM3&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;bpmp TEGRA234_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		padctl@3520000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			pads {</div><div class='add'>+				usb2 {</div><div class='add'>+					lanes {</div><div class='add'>+						usb2-0 {</div><div class='add'>+							nvidia,function = "xusb";</div><div class='add'>+							status = "okay";</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						usb2-1 {</div><div class='add'>+							nvidia,function = "xusb";</div><div class='add'>+							status = "okay";</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						usb2-2 {</div><div class='add'>+							nvidia,function = "xusb";</div><div class='add'>+							status = "okay";</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usb3 {</div><div class='add'>+					lanes {</div><div class='add'>+						usb3-0 {</div><div class='add'>+							nvidia,function = "xusb";</div><div class='add'>+							status = "okay";</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						usb3-1 {</div><div class='add'>+							nvidia,function = "xusb";</div><div class='add'>+							status = "okay";</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				/* recovery port */</div><div class='add'>+				usb2-0 {</div><div class='add'>+					mode = "otg";</div><div class='add'>+					vbus-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+					status = "okay";</div><div class='add'>+					usb-role-switch;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				/* hub */</div><div class='add'>+				usb2-1 {</div><div class='add'>+					mode = "host";</div><div class='add'>+					vbus-supply = &lt;&amp;vdd_1v1_hub&gt;;</div><div class='add'>+					status = "okay";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				/* M.2 Key-E */</div><div class='add'>+				usb2-2 {</div><div class='add'>+					mode = "host";</div><div class='add'>+					vbus-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+					status = "okay";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				/* hub */</div><div class='add'>+				usb3-0 {</div><div class='add'>+					nvidia,usb2-companion = &lt;1&gt;;</div><div class='add'>+					status = "okay";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				/* J5 */</div><div class='add'>+				usb3-1 {</div><div class='add'>+					nvidia,usb2-companion = &lt;0&gt;;</div><div class='add'>+					status = "okay";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb@3550000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}&gt;,</div><div class='add'>+			       &lt;&amp;{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}&gt;;</div><div class='add'>+			phy-names = "usb2-0", "usb3-0";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb@3610000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}&gt;,</div><div class='add'>+			       &lt;&amp;{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}&gt;,</div><div class='add'>+			       &lt;&amp;{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-2}&gt;,</div><div class='add'>+			       &lt;&amp;{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-0}&gt;,</div><div class='add'>+			       &lt;&amp;{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}&gt;;</div><div class='add'>+			phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0",</div><div class='add'>+				    "usb3-1";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* C8 - Ethernet */</div><div class='add'>+		pcie@140a0000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			num-lanes = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;p2u_gbe_2&gt;, &lt;&amp;p2u_gbe_3&gt;;</div><div class='add'>+			phy-names = "p2u-0", "p2u-1";</div><div class='add'>+</div><div class='add'>+			vddio-pex-ctl-supply = &lt;&amp;vdd_1v8_ao&gt;;</div><div class='add'>+			vpcie3v3-supply = &lt;&amp;vdd_3v3_pcie&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* C1 - M.2 Key-E */</div><div class='add'>+		pcie@14100000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			vddio-pex-ctl-supply = &lt;&amp;vdd_1v8_ao&gt;;</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;p2u_hsio_3&gt;;</div><div class='add'>+			phy-names = "p2u-0";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* C4 - M.2 Key-M */</div><div class='add'>+		pcie@14160000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			vddio-pex-ctl-supply = &lt;&amp;vdd_1v8_ao&gt;;</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;p2u_hsio_4&gt;, &lt;&amp;p2u_hsio_5&gt;, &lt;&amp;p2u_hsio_6&gt;,</div><div class='add'>+			       &lt;&amp;p2u_hsio_7&gt;;</div><div class='add'>+			phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie-ep@14160000 {/* C4 - End Point */</div><div class='add'>+			phys = &lt;&amp;p2u_hsio_4&gt;, &lt;&amp;p2u_hsio_5&gt;, &lt;&amp;p2u_hsio_6&gt;,</div><div class='add'>+					&lt;&amp;p2u_hsio_7&gt;;</div><div class='add'>+			phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";</div><div class='add'>+			reset-gpios = &lt;&amp;gpio</div><div class='add'>+					TEGRA234_MAIN_GPIO(L, 1)</div><div class='add'>+					GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			nvidia,refclk-select-gpios = &lt;&amp;gpio_aon</div><div class='add'>+							TEGRA234_AON_GPIO(AA, 4)</div><div class='add'>+							GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* C7 - M.2 Key-M */</div><div class='add'>+		pcie@141e0000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			vddio-pex-ctl-supply = &lt;&amp;vdd_1v8_ao&gt;;</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;p2u_gbe_0&gt;, &lt;&amp;p2u_gbe_1&gt;;</div><div class='add'>+			phy-names = "p2u-0", "p2u-1";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		key-force-recovery {</div><div class='add'>+			label = "Force Recovery";</div><div class='add'>+			gpios = &lt;&amp;gpio TEGRA234_MAIN_GPIO(G, 0) GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,input-type = &lt;EV_KEY&gt;;</div><div class='add'>+			linux,code = &lt;BTN_1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		key-power {</div><div class='add'>+			label = "Power";</div><div class='add'>+			gpios = &lt;&amp;gpio_aon TEGRA234_AON_GPIO(EE, 4) GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,input-type = &lt;EV_KEY&gt;;</div><div class='add'>+			linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+			wakeup-event-action = &lt;EV_ACT_ASSERTED&gt;;</div><div class='add'>+			wakeup-source;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	fan: pwm-fan {</div><div class='add'>+		compatible = "pwm-fan";</div><div class='add'>+		pwms = &lt;&amp;pwm3 0 45334&gt;;</div><div class='add'>+		#cooling-cells = &lt;2&gt;;</div><div class='add'>+		cooling-levels = &lt;0 88 187 255&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_1v8_sys: regulator-vdd-1v8-sys {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_1V8_SYS";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_1v1_hub: regulator-vdd-1v1-hub {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_AV10_HUB";</div><div class='add'>+		regulator-min-microvolt = &lt;1100000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+		vin-supply = &lt;&amp;vdd_5v0_sys&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vdd_3v3_pcie: regulator-vdd-3v3-pcie {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VDD_3V3_PCIE";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		gpio = &lt;&amp;gpio_aon TEGRA234_AON_GPIO(AA, 5) GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	serial {</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	thermal-zones {</div><div class='add'>+		tj-thermal {</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map-active-0 {</div><div class='add'>+					cooling-device = &lt;&amp;fan 0 1&gt;;</div><div class='add'>+					trip = &lt;&amp;tj_trip_active0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				map-active-1 {</div><div class='add'>+					cooling-device = &lt;&amp;fan 1 2&gt;;</div><div class='add'>+					trip = &lt;&amp;tj_trip_active1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				map-active-2 {</div><div class='add'>+					cooling-device = &lt;&amp;fan 2 3&gt;;</div><div class='add'>+					trip = &lt;&amp;tj_trip_active2&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts b/arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts<br/>new file mode 100644<br/>index 000000000000..292e28376eec<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts</a></div><div class='hunk'>@@ -0,0 +1,40 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "tegra234.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "NVIDIA Tegra234 VDK";</div><div class='add'>+	compatible = "nvidia,tegra234-vdk", "nvidia,tegra234";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uarta;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		bootargs = "console=ttyS0,115200n8 earlycon=uart8250,mmio32,0x03100000";</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bus@0 {</div><div class='add'>+		serial@3100000 {</div><div class='add'>+			/delete-property/ dmas;</div><div class='add'>+			/delete-property/ dma-names;</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmc@3460000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+			bus-width = &lt;8&gt;;</div><div class='add'>+			non-removable;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rtc@c2a0000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmc@c360000 {</div><div class='add'>+			nvidia,invert-interrupt;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi<br/>new file mode 100644<br/>index 000000000000..827dbb420826<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra234.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/tegra234.dtsi</a></div><div class='hunk'>@@ -0,0 +1,6344 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/tegra234-clock.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/tegra234-gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/mailbox/tegra186-hsp.h&gt;</div><div class='add'>+#include &lt;dt-bindings/memory/tegra234-mc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/pinctrl-tegra-io-pad.h&gt;</div><div class='add'>+#include &lt;dt-bindings/power/tegra234-powergate.h&gt;</div><div class='add'>+#include &lt;dt-bindings/reset/tegra234-reset.h&gt;</div><div class='add'>+#include &lt;dt-bindings/thermal/tegra234-bpmp-thermal.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/pinctrl-tegra.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "nvidia,tegra234";</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		i2c0 = &amp;gen1_i2c;</div><div class='add'>+		i2c1 = &amp;gen2_i2c;</div><div class='add'>+		i2c2 = &amp;cam_i2c;</div><div class='add'>+		i2c3 = &amp;dp_aux_ch1_i2c;</div><div class='add'>+		i2c4 = &amp;bpmp_i2c;</div><div class='add'>+		i2c5 = &amp;dp_aux_ch0_i2c;</div><div class='add'>+		i2c6 = &amp;dp_aux_ch2_i2c;</div><div class='add'>+		i2c7 = &amp;gen8_i2c;</div><div class='add'>+		i2c8 = &amp;dp_aux_ch3_i2c;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bus@0 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges = &lt;0x0 0x0 0x0 0x0 0x100 0x0&gt;;</div><div class='add'>+</div><div class='add'>+		misc@100000 {</div><div class='add'>+			compatible = "nvidia,tegra234-misc";</div><div class='add'>+			reg = &lt;0x0 0x00100000 0x0 0xf000&gt;,</div><div class='add'>+			      &lt;0x0 0x0010f000 0x0 0x1000&gt;;</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		timer@2080000 {</div><div class='add'>+			compatible = "nvidia,tegra234-timer";</div><div class='add'>+			reg = &lt;0x0 0x02080000 0x0 0x00121000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpio: gpio@2200000 {</div><div class='add'>+			compatible = "nvidia,tegra234-gpio";</div><div class='add'>+			reg-names = "security", "gpio";</div><div class='add'>+			reg = &lt;0x0 0x02200000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0x02210000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			gpio-ranges = &lt;&amp;pinmux 0 0 164&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinmux: pinmux@2430000 {</div><div class='add'>+			compatible = "nvidia,tegra234-pinmux";</div><div class='add'>+			reg = &lt;0x0 0x2430000 0x0 0x19100&gt;;</div><div class='add'>+</div><div class='add'>+			pex_rst_c4_in_state: pinmux-pex-rst-c4-in {</div><div class='add'>+				pex_rst {</div><div class='add'>+					nvidia,pins = "pex_l4_rst_n_pl1";</div><div class='add'>+					nvidia,function = "rsvd1";</div><div class='add'>+					nvidia,pull = &lt;TEGRA_PIN_PULL_NONE&gt;;</div><div class='add'>+					nvidia,tristate = &lt;TEGRA_PIN_ENABLE&gt;;</div><div class='add'>+					nvidia,enable-input = &lt;TEGRA_PIN_ENABLE&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pex_rst_c5_in_state: pinmux-pex-rst-c5-in {</div><div class='add'>+				pex_rst {</div><div class='add'>+					nvidia,pins = "pex_l5_rst_n_paf1";</div><div class='add'>+					nvidia,function = "rsvd1";</div><div class='add'>+					nvidia,pull = &lt;TEGRA_PIN_PULL_NONE&gt;;</div><div class='add'>+					nvidia,tristate = &lt;TEGRA_PIN_ENABLE&gt;;</div><div class='add'>+					nvidia,enable-input = &lt;TEGRA_PIN_ENABLE&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pex_rst_c6_in_state: pinmux-pex-rst-c6-in {</div><div class='add'>+				pex_rst {</div><div class='add'>+					nvidia,pins = "pex_l6_rst_n_paf3";</div><div class='add'>+					nvidia,function = "rsvd1";</div><div class='add'>+					nvidia,pull = &lt;TEGRA_PIN_PULL_NONE&gt;;</div><div class='add'>+					nvidia,tristate = &lt;TEGRA_PIN_ENABLE&gt;;</div><div class='add'>+					nvidia,enable-input = &lt;TEGRA_PIN_ENABLE&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pex_rst_c7_in_state: pinmux-pex-rst-c7-in {</div><div class='add'>+				pex_rst {</div><div class='add'>+					nvidia,pins = "pex_l7_rst_n_pag1";</div><div class='add'>+					nvidia,function = "rsvd1";</div><div class='add'>+					nvidia,pull = &lt;TEGRA_PIN_PULL_NONE&gt;;</div><div class='add'>+					nvidia,tristate = &lt;TEGRA_PIN_ENABLE&gt;;</div><div class='add'>+					nvidia,enable-input = &lt;TEGRA_PIN_ENABLE&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pex_rst_c10_in_state: pinmux-pex-rst-c10-in {</div><div class='add'>+				pex_rst {</div><div class='add'>+					nvidia,pins = "pex_l10_rst_n_pag7";</div><div class='add'>+					nvidia,function = "rsvd1";</div><div class='add'>+					nvidia,pull = &lt;TEGRA_PIN_PULL_NONE&gt;;</div><div class='add'>+					nvidia,tristate = &lt;TEGRA_PIN_ENABLE&gt;;</div><div class='add'>+					nvidia,enable-input = &lt;TEGRA_PIN_ENABLE&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpcdma: dma-controller@2600000 {</div><div class='add'>+			compatible = "nvidia,tegra234-gpcdma",</div><div class='add'>+				     "nvidia,tegra186-gpcdma";</div><div class='add'>+			reg = &lt;0x0 0x2600000 0x0 0x210000&gt;;</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_GPCDMA&gt;;</div><div class='add'>+			reset-names = "gpcdma";</div><div class='add'>+			interrupts = &lt;GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+			iommus = &lt;&amp;smmu_niso0 TEGRA234_SID_GPCDMA&gt;;</div><div class='add'>+			dma-channel-mask = &lt;0xfffffffe&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aconnect@2900000 {</div><div class='add'>+			compatible = "nvidia,tegra234-aconnect",</div><div class='add'>+				     "nvidia,tegra210-aconnect";</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_APE&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_APB2APE&gt;;</div><div class='add'>+			clock-names = "ape", "apb2ape";</div><div class='add'>+			power-domains = &lt;&amp;bpmp TEGRA234_POWER_DOMAIN_AUD&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges = &lt;0x0 0x02900000 0x0 0x02900000 0x0 0x200000&gt;;</div><div class='add'>+</div><div class='add'>+			tegra_ahub: ahub@2900800 {</div><div class='add'>+				compatible = "nvidia,tegra234-ahub";</div><div class='add'>+				reg = &lt;0x0 0x02900800 0x0 0x800&gt;;</div><div class='add'>+				clocks = &lt;&amp;bpmp TEGRA234_CLK_AHUB&gt;;</div><div class='add'>+				clock-names = "ahub";</div><div class='add'>+				assigned-clocks = &lt;&amp;bpmp TEGRA234_CLK_AHUB&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;bpmp TEGRA234_CLK_PLLP_OUT0&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;81600000&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;2&gt;;</div><div class='add'>+				#size-cells = &lt;2&gt;;</div><div class='add'>+				ranges = &lt;0x0 0x02900800 0x0 0x02900800 0x0 0x11800&gt;;</div><div class='add'>+</div><div class='add'>+				tegra_i2s1: i2s@2901000 {</div><div class='add'>+					compatible = "nvidia,tegra234-i2s",</div><div class='add'>+						     "nvidia,tegra210-i2s";</div><div class='add'>+					reg = &lt;0x0 0x2901000 0x0 0x100&gt;;</div><div class='add'>+					clocks = &lt;&amp;bpmp TEGRA234_CLK_I2S1&gt;,</div><div class='add'>+						 &lt;&amp;bpmp TEGRA234_CLK_I2S1_SYNC_INPUT&gt;;</div><div class='add'>+					clock-names = "i2s", "sync_input";</div><div class='add'>+					assigned-clocks = &lt;&amp;bpmp TEGRA234_CLK_I2S1&gt;;</div><div class='add'>+					assigned-clock-parents = &lt;&amp;bpmp TEGRA234_CLK_PLLA_OUT0&gt;;</div><div class='add'>+					assigned-clock-rates = &lt;1536000&gt;;</div><div class='add'>+					sound-name-prefix = "I2S1";</div><div class='add'>+					status = "disabled";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							i2s1_cif: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_i2s1&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						i2s1_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							i2s1_dap: endpoint {</div><div class='add'>+								dai-format = "i2s";</div><div class='add'>+								/* placeholder for external codec */</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_i2s2: i2s@2901100 {</div><div class='add'>+					compatible = "nvidia,tegra234-i2s",</div><div class='add'>+						     "nvidia,tegra210-i2s";</div><div class='add'>+					reg = &lt;0x0 0x2901100 0x0 0x100&gt;;</div><div class='add'>+					clocks = &lt;&amp;bpmp TEGRA234_CLK_I2S2&gt;,</div><div class='add'>+						 &lt;&amp;bpmp TEGRA234_CLK_I2S2_SYNC_INPUT&gt;;</div><div class='add'>+					clock-names = "i2s", "sync_input";</div><div class='add'>+					assigned-clocks = &lt;&amp;bpmp TEGRA234_CLK_I2S2&gt;;</div><div class='add'>+					assigned-clock-parents = &lt;&amp;bpmp TEGRA234_CLK_PLLA_OUT0&gt;;</div><div class='add'>+					assigned-clock-rates = &lt;1536000&gt;;</div><div class='add'>+					sound-name-prefix = "I2S2";</div><div class='add'>+					status = "disabled";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							i2s2_cif: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_i2s2&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						i2s2_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							i2s2_dap: endpoint {</div><div class='add'>+								dai-format = "i2s";</div><div class='add'>+								/* placeholder for external codec */</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_i2s3: i2s@2901200 {</div><div class='add'>+					compatible = "nvidia,tegra234-i2s",</div><div class='add'>+						     "nvidia,tegra210-i2s";</div><div class='add'>+					reg = &lt;0x0 0x2901200 0x0 0x100&gt;;</div><div class='add'>+					clocks = &lt;&amp;bpmp TEGRA234_CLK_I2S3&gt;,</div><div class='add'>+						 &lt;&amp;bpmp TEGRA234_CLK_I2S3_SYNC_INPUT&gt;;</div><div class='add'>+					clock-names = "i2s", "sync_input";</div><div class='add'>+					assigned-clocks = &lt;&amp;bpmp TEGRA234_CLK_I2S3&gt;;</div><div class='add'>+					assigned-clock-parents = &lt;&amp;bpmp TEGRA234_CLK_PLLA_OUT0&gt;;</div><div class='add'>+					assigned-clock-rates = &lt;1536000&gt;;</div><div class='add'>+					sound-name-prefix = "I2S3";</div><div class='add'>+					status = "disabled";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							i2s3_cif: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_i2s3&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						i2s3_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							i2s3_dap: endpoint {</div><div class='add'>+								dai-format = "i2s";</div><div class='add'>+								/* placeholder for external codec */</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_i2s4: i2s@2901300 {</div><div class='add'>+					compatible = "nvidia,tegra234-i2s",</div><div class='add'>+						     "nvidia,tegra210-i2s";</div><div class='add'>+					reg = &lt;0x0 0x2901300 0x0 0x100&gt;;</div><div class='add'>+					clocks = &lt;&amp;bpmp TEGRA234_CLK_I2S4&gt;,</div><div class='add'>+						 &lt;&amp;bpmp TEGRA234_CLK_I2S4_SYNC_INPUT&gt;;</div><div class='add'>+					clock-names = "i2s", "sync_input";</div><div class='add'>+					assigned-clocks = &lt;&amp;bpmp TEGRA234_CLK_I2S4&gt;;</div><div class='add'>+					assigned-clock-parents = &lt;&amp;bpmp TEGRA234_CLK_PLLA_OUT0&gt;;</div><div class='add'>+					assigned-clock-rates = &lt;1536000&gt;;</div><div class='add'>+					sound-name-prefix = "I2S4";</div><div class='add'>+					status = "disabled";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							i2s4_cif: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_i2s4&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						i2s4_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							i2s4_dap: endpoint {</div><div class='add'>+								dai-format = "i2s";</div><div class='add'>+								/* placeholder for external codec */</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_i2s5: i2s@2901400 {</div><div class='add'>+					compatible = "nvidia,tegra234-i2s",</div><div class='add'>+						     "nvidia,tegra210-i2s";</div><div class='add'>+					reg = &lt;0x0 0x2901400 0x0 0x100&gt;;</div><div class='add'>+					clocks = &lt;&amp;bpmp TEGRA234_CLK_I2S5&gt;,</div><div class='add'>+						 &lt;&amp;bpmp TEGRA234_CLK_I2S5_SYNC_INPUT&gt;;</div><div class='add'>+					clock-names = "i2s", "sync_input";</div><div class='add'>+					assigned-clocks = &lt;&amp;bpmp TEGRA234_CLK_I2S5&gt;;</div><div class='add'>+					assigned-clock-parents = &lt;&amp;bpmp TEGRA234_CLK_PLLA_OUT0&gt;;</div><div class='add'>+					assigned-clock-rates = &lt;1536000&gt;;</div><div class='add'>+					sound-name-prefix = "I2S5";</div><div class='add'>+					status = "disabled";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							i2s5_cif: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_i2s5&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						i2s5_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							i2s5_dap: endpoint {</div><div class='add'>+								dai-format = "i2s";</div><div class='add'>+								/* placeholder for external codec */</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_i2s6: i2s@2901500 {</div><div class='add'>+					compatible = "nvidia,tegra234-i2s",</div><div class='add'>+						     "nvidia,tegra210-i2s";</div><div class='add'>+					reg = &lt;0x0 0x2901500 0x0 0x100&gt;;</div><div class='add'>+					clocks = &lt;&amp;bpmp TEGRA234_CLK_I2S6&gt;,</div><div class='add'>+						 &lt;&amp;bpmp TEGRA234_CLK_I2S6_SYNC_INPUT&gt;;</div><div class='add'>+					clock-names = "i2s", "sync_input";</div><div class='add'>+					assigned-clocks = &lt;&amp;bpmp TEGRA234_CLK_I2S6&gt;;</div><div class='add'>+					assigned-clock-parents = &lt;&amp;bpmp TEGRA234_CLK_PLLA_OUT0&gt;;</div><div class='add'>+					assigned-clock-rates = &lt;1536000&gt;;</div><div class='add'>+					sound-name-prefix = "I2S6";</div><div class='add'>+					status = "disabled";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							i2s6_cif: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_i2s6&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						i2s6_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							i2s6_dap: endpoint {</div><div class='add'>+								dai-format = "i2s";</div><div class='add'>+								/* placeholder for external codec */</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_sfc1: sfc@2902000 {</div><div class='add'>+					compatible = "nvidia,tegra234-sfc",</div><div class='add'>+						     "nvidia,tegra210-sfc";</div><div class='add'>+					reg = &lt;0x0 0x2902000 0x0 0x200&gt;;</div><div class='add'>+					sound-name-prefix = "SFC1";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							sfc1_cif_in: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_sfc1_in&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						sfc1_out_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							sfc1_cif_out: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_sfc1_out&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_sfc2: sfc@2902200 {</div><div class='add'>+					compatible = "nvidia,tegra234-sfc",</div><div class='add'>+						     "nvidia,tegra210-sfc";</div><div class='add'>+					reg = &lt;0x0 0x2902200 0x0 0x200&gt;;</div><div class='add'>+					sound-name-prefix = "SFC2";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							sfc2_cif_in: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_sfc2_in&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						sfc2_out_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							sfc2_cif_out: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_sfc2_out&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_sfc3: sfc@2902400 {</div><div class='add'>+					compatible = "nvidia,tegra234-sfc",</div><div class='add'>+						     "nvidia,tegra210-sfc";</div><div class='add'>+					reg = &lt;0x0 0x2902400 0x0 0x200&gt;;</div><div class='add'>+					sound-name-prefix = "SFC3";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							sfc3_cif_in: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_sfc3_in&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						sfc3_out_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							sfc3_cif_out: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_sfc3_out&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_sfc4: sfc@2902600 {</div><div class='add'>+					compatible = "nvidia,tegra234-sfc",</div><div class='add'>+						     "nvidia,tegra210-sfc";</div><div class='add'>+					reg = &lt;0x0 0x2902600 0x0 0x200&gt;;</div><div class='add'>+					sound-name-prefix = "SFC4";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							sfc4_cif_in: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_sfc4_in&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						sfc4_out_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							sfc4_cif_out: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_sfc4_out&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_amx1: amx@2903000 {</div><div class='add'>+					compatible = "nvidia,tegra234-amx",</div><div class='add'>+						     "nvidia,tegra194-amx";</div><div class='add'>+					reg = &lt;0x0 0x2903000 0x0 0x100&gt;;</div><div class='add'>+					sound-name-prefix = "AMX1";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							amx1_in1: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx1_in1&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							amx1_in2: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx1_in2&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@2 {</div><div class='add'>+							reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+							amx1_in3: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx1_in3&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@3 {</div><div class='add'>+							reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+							amx1_in4: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx1_in4&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						amx1_out_port: port@4 {</div><div class='add'>+							reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+							amx1_out: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx1_out&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_amx2: amx@2903100 {</div><div class='add'>+					compatible = "nvidia,tegra234-amx",</div><div class='add'>+						     "nvidia,tegra194-amx";</div><div class='add'>+					reg = &lt;0x0 0x2903100 0x0 0x100&gt;;</div><div class='add'>+					sound-name-prefix = "AMX2";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							amx2_in1: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx2_in1&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							amx2_in2: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx2_in2&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@2 {</div><div class='add'>+							reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+							amx2_in3: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx2_in3&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@3 {</div><div class='add'>+							reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+							amx2_in4: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx2_in4&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						amx2_out_port: port@4 {</div><div class='add'>+							reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+							amx2_out: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx2_out&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_amx3: amx@2903200 {</div><div class='add'>+					compatible = "nvidia,tegra234-amx",</div><div class='add'>+						     "nvidia,tegra194-amx";</div><div class='add'>+					reg = &lt;0x0 0x2903200 0x0 0x100&gt;;</div><div class='add'>+					sound-name-prefix = "AMX3";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							amx3_in1: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx3_in1&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							amx3_in2: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx3_in2&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@2 {</div><div class='add'>+							reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+							amx3_in3: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx3_in3&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@3 {</div><div class='add'>+							reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+							amx3_in4: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx3_in4&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						amx3_out_port: port@4 {</div><div class='add'>+							reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+							amx3_out: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx3_out&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_amx4: amx@2903300 {</div><div class='add'>+					compatible = "nvidia,tegra234-amx",</div><div class='add'>+						     "nvidia,tegra194-amx";</div><div class='add'>+					reg = &lt;0x0 0x2903300 0x0 0x100&gt;;</div><div class='add'>+					sound-name-prefix = "AMX4";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							amx4_in1: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx4_in1&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							amx4_in2: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx4_in2&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@2 {</div><div class='add'>+							reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+							amx4_in3: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx4_in3&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@3 {</div><div class='add'>+							reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+							amx4_in4: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx4_in4&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						amx4_out_port: port@4 {</div><div class='add'>+							reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+							amx4_out: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx4_out&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_adx1: adx@2903800 {</div><div class='add'>+					compatible = "nvidia,tegra234-adx",</div><div class='add'>+						     "nvidia,tegra210-adx";</div><div class='add'>+					reg = &lt;0x0 0x2903800 0x0 0x100&gt;;</div><div class='add'>+					sound-name-prefix = "ADX1";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							adx1_in: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx1_in&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx1_out1_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							adx1_out1: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx1_out1&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx1_out2_port: port@2 {</div><div class='add'>+							reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+							adx1_out2: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx1_out2&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx1_out3_port: port@3 {</div><div class='add'>+							reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+							adx1_out3: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx1_out3&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx1_out4_port: port@4 {</div><div class='add'>+							reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+							adx1_out4: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx1_out4&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_adx2: adx@2903900 {</div><div class='add'>+					compatible = "nvidia,tegra234-adx",</div><div class='add'>+						     "nvidia,tegra210-adx";</div><div class='add'>+					reg = &lt;0x0 0x2903900 0x0 0x100&gt;;</div><div class='add'>+					sound-name-prefix = "ADX2";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							adx2_in: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx2_in&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx2_out1_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							adx2_out1: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx2_out1&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx2_out2_port: port@2 {</div><div class='add'>+							reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+							adx2_out2: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx2_out2&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx2_out3_port: port@3 {</div><div class='add'>+							reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+							adx2_out3: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx2_out3&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx2_out4_port: port@4 {</div><div class='add'>+							reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+							adx2_out4: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx2_out4&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_adx3: adx@2903a00 {</div><div class='add'>+					compatible = "nvidia,tegra234-adx",</div><div class='add'>+						     "nvidia,tegra210-adx";</div><div class='add'>+					reg = &lt;0x0 0x2903a00 0x0 0x100&gt;;</div><div class='add'>+					sound-name-prefix = "ADX3";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							adx3_in: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx3_in&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx3_out1_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							adx3_out1: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx3_out1&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx3_out2_port: port@2 {</div><div class='add'>+							reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+							adx3_out2: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx3_out2&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx3_out3_port: port@3 {</div><div class='add'>+							reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+							adx3_out3: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx3_out3&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx3_out4_port: port@4 {</div><div class='add'>+							reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+							adx3_out4: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx3_out4&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_adx4: adx@2903b00 {</div><div class='add'>+					compatible = "nvidia,tegra234-adx",</div><div class='add'>+						     "nvidia,tegra210-adx";</div><div class='add'>+					reg = &lt;0x0 0x2903b00 0x0 0x100&gt;;</div><div class='add'>+					sound-name-prefix = "ADX4";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							adx4_in: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx4_in&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx4_out1_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							adx4_out1: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx4_out1&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx4_out2_port: port@2 {</div><div class='add'>+							reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+							adx4_out2: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx4_out2&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx4_out3_port: port@3 {</div><div class='add'>+							reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+							adx4_out3: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx4_out3&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx4_out4_port: port@4 {</div><div class='add'>+							reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+							adx4_out4: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx4_out4&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+				tegra_dmic1: dmic@2904000 {</div><div class='add'>+					compatible = "nvidia,tegra234-dmic",</div><div class='add'>+						     "nvidia,tegra210-dmic";</div><div class='add'>+					reg = &lt;0x0 0x2904000 0x0 0x100&gt;;</div><div class='add'>+					clocks = &lt;&amp;bpmp TEGRA234_CLK_DMIC1&gt;;</div><div class='add'>+					clock-names = "dmic";</div><div class='add'>+					assigned-clocks = &lt;&amp;bpmp TEGRA234_CLK_DMIC1&gt;;</div><div class='add'>+					assigned-clock-parents = &lt;&amp;bpmp TEGRA234_CLK_PLLA_OUT0&gt;;</div><div class='add'>+					assigned-clock-rates = &lt;3072000&gt;;</div><div class='add'>+					sound-name-prefix = "DMIC1";</div><div class='add'>+					status = "disabled";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							dmic1_cif: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_dmic1&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						dmic1_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							dmic1_dap: endpoint {</div><div class='add'>+								/* placeholder for external codec */</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_dmic2: dmic@2904100 {</div><div class='add'>+					compatible = "nvidia,tegra234-dmic",</div><div class='add'>+						     "nvidia,tegra210-dmic";</div><div class='add'>+					reg = &lt;0x0 0x2904100 0x0 0x100&gt;;</div><div class='add'>+					clocks = &lt;&amp;bpmp TEGRA234_CLK_DMIC2&gt;;</div><div class='add'>+					clock-names = "dmic";</div><div class='add'>+					assigned-clocks = &lt;&amp;bpmp TEGRA234_CLK_DMIC2&gt;;</div><div class='add'>+					assigned-clock-parents = &lt;&amp;bpmp TEGRA234_CLK_PLLA_OUT0&gt;;</div><div class='add'>+					assigned-clock-rates = &lt;3072000&gt;;</div><div class='add'>+					sound-name-prefix = "DMIC2";</div><div class='add'>+					status = "disabled";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							dmic2_cif: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_dmic2&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						dmic2_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							dmic2_dap: endpoint {</div><div class='add'>+								/* placeholder for external codec */</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_dmic3: dmic@2904200 {</div><div class='add'>+					compatible = "nvidia,tegra234-dmic",</div><div class='add'>+						     "nvidia,tegra210-dmic";</div><div class='add'>+					reg = &lt;0x0 0x2904200 0x0 0x100&gt;;</div><div class='add'>+					clocks = &lt;&amp;bpmp TEGRA234_CLK_DMIC3&gt;;</div><div class='add'>+					clock-names = "dmic";</div><div class='add'>+					assigned-clocks = &lt;&amp;bpmp TEGRA234_CLK_DMIC3&gt;;</div><div class='add'>+					assigned-clock-parents = &lt;&amp;bpmp TEGRA234_CLK_PLLA_OUT0&gt;;</div><div class='add'>+					assigned-clock-rates = &lt;3072000&gt;;</div><div class='add'>+					sound-name-prefix = "DMIC3";</div><div class='add'>+					status = "disabled";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							dmic3_cif: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_dmic3&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						dmic3_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							dmic3_dap: endpoint {</div><div class='add'>+								/* placeholder for external codec */</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_dmic4: dmic@2904300 {</div><div class='add'>+					compatible = "nvidia,tegra234-dmic",</div><div class='add'>+						     "nvidia,tegra210-dmic";</div><div class='add'>+					reg = &lt;0x0 0x2904300 0x0 0x100&gt;;</div><div class='add'>+					clocks = &lt;&amp;bpmp TEGRA234_CLK_DMIC4&gt;;</div><div class='add'>+					clock-names = "dmic";</div><div class='add'>+					assigned-clocks = &lt;&amp;bpmp TEGRA234_CLK_DMIC4&gt;;</div><div class='add'>+					assigned-clock-parents = &lt;&amp;bpmp TEGRA234_CLK_PLLA_OUT0&gt;;</div><div class='add'>+					assigned-clock-rates = &lt;3072000&gt;;</div><div class='add'>+					sound-name-prefix = "DMIC4";</div><div class='add'>+					status = "disabled";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							dmic4_cif: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_dmic4&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						dmic4_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							dmic4_dap: endpoint {</div><div class='add'>+								/* placeholder for external codec */</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_dspk1: dspk@2905000 {</div><div class='add'>+					compatible = "nvidia,tegra234-dspk",</div><div class='add'>+						     "nvidia,tegra186-dspk";</div><div class='add'>+					reg = &lt;0x0 0x2905000 0x0 0x100&gt;;</div><div class='add'>+					clocks = &lt;&amp;bpmp TEGRA234_CLK_DSPK1&gt;;</div><div class='add'>+					clock-names = "dspk";</div><div class='add'>+					assigned-clocks = &lt;&amp;bpmp TEGRA234_CLK_DSPK1&gt;;</div><div class='add'>+					assigned-clock-parents = &lt;&amp;bpmp TEGRA234_CLK_PLLA_OUT0&gt;;</div><div class='add'>+					assigned-clock-rates = &lt;12288000&gt;;</div><div class='add'>+					sound-name-prefix = "DSPK1";</div><div class='add'>+					status = "disabled";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							dspk1_cif: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_dspk1&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						dspk1_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							dspk1_dap: endpoint {</div><div class='add'>+								/* placeholder for external codec */</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_dspk2: dspk@2905100 {</div><div class='add'>+					compatible = "nvidia,tegra234-dspk",</div><div class='add'>+						     "nvidia,tegra186-dspk";</div><div class='add'>+					reg = &lt;0x0 0x2905100 0x0 0x100&gt;;</div><div class='add'>+					clocks = &lt;&amp;bpmp TEGRA234_CLK_DSPK2&gt;;</div><div class='add'>+					clock-names = "dspk";</div><div class='add'>+					assigned-clocks = &lt;&amp;bpmp TEGRA234_CLK_DSPK2&gt;;</div><div class='add'>+					assigned-clock-parents = &lt;&amp;bpmp TEGRA234_CLK_PLLA_OUT0&gt;;</div><div class='add'>+					assigned-clock-rates = &lt;12288000&gt;;</div><div class='add'>+					sound-name-prefix = "DSPK2";</div><div class='add'>+					status = "disabled";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							dspk2_cif: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_dspk2&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						dspk2_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							dspk2_dap: endpoint {</div><div class='add'>+								/* placeholder for external codec */</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_ope1: processing-engine@2908000 {</div><div class='add'>+					compatible = "nvidia,tegra234-ope",</div><div class='add'>+						     "nvidia,tegra210-ope";</div><div class='add'>+					reg = &lt;0x0 0x2908000 0x0 0x100&gt;;</div><div class='add'>+					sound-name-prefix = "OPE1";</div><div class='add'>+</div><div class='add'>+					#address-cells = &lt;2&gt;;</div><div class='add'>+					#size-cells = &lt;2&gt;;</div><div class='add'>+					ranges;</div><div class='add'>+</div><div class='add'>+					equalizer@2908100 {</div><div class='add'>+						compatible = "nvidia,tegra234-peq",</div><div class='add'>+							     "nvidia,tegra210-peq";</div><div class='add'>+						reg = &lt;0x0 0x2908100 0x0 0x100&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					dynamic-range-compressor@2908200 {</div><div class='add'>+						compatible = "nvidia,tegra234-mbdrc",</div><div class='add'>+							     "nvidia,tegra210-mbdrc";</div><div class='add'>+						reg = &lt;0x0 0x2908200 0x0 0x200&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0x0&gt;;</div><div class='add'>+</div><div class='add'>+							ope1_cif_in_ep: endpoint {</div><div class='add'>+								remote-endpoint =</div><div class='add'>+									&lt;&amp;xbar_ope1_in_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						ope1_out_port: port@1 {</div><div class='add'>+							reg = &lt;0x1&gt;;</div><div class='add'>+</div><div class='add'>+							ope1_cif_out_ep: endpoint {</div><div class='add'>+								remote-endpoint =</div><div class='add'>+									&lt;&amp;xbar_ope1_out_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_mvc1: mvc@290a000 {</div><div class='add'>+					compatible = "nvidia,tegra234-mvc",</div><div class='add'>+						     "nvidia,tegra210-mvc";</div><div class='add'>+					reg = &lt;0x0 0x290a000 0x0 0x200&gt;;</div><div class='add'>+					sound-name-prefix = "MVC1";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							mvc1_cif_in: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mvc1_in&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						mvc1_out_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							mvc1_cif_out: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mvc1_out&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_mvc2: mvc@290a200 {</div><div class='add'>+					compatible = "nvidia,tegra234-mvc",</div><div class='add'>+						     "nvidia,tegra210-mvc";</div><div class='add'>+					reg = &lt;0x0 0x290a200 0x0 0x200&gt;;</div><div class='add'>+					sound-name-prefix = "MVC2";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							mvc2_cif_in: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mvc2_in&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						mvc2_out_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							mvc2_cif_out: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mvc2_out&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_amixer: amixer@290bb00 {</div><div class='add'>+					compatible = "nvidia,tegra234-amixer",</div><div class='add'>+						     "nvidia,tegra210-amixer";</div><div class='add'>+					reg = &lt;0x0 0x290bb00 0x0 0x800&gt;;</div><div class='add'>+					sound-name-prefix = "MIXER1";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0x0&gt;;</div><div class='add'>+</div><div class='add'>+							mix_in1: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mix_in1&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@1 {</div><div class='add'>+							reg = &lt;0x1&gt;;</div><div class='add'>+</div><div class='add'>+							mix_in2: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mix_in2&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@2 {</div><div class='add'>+							reg = &lt;0x2&gt;;</div><div class='add'>+</div><div class='add'>+							mix_in3: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mix_in3&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@3 {</div><div class='add'>+							reg = &lt;0x3&gt;;</div><div class='add'>+</div><div class='add'>+							mix_in4: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mix_in4&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@4 {</div><div class='add'>+							reg = &lt;0x4&gt;;</div><div class='add'>+</div><div class='add'>+							mix_in5: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mix_in5&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@5 {</div><div class='add'>+							reg = &lt;0x5&gt;;</div><div class='add'>+</div><div class='add'>+							mix_in6: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mix_in6&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@6 {</div><div class='add'>+							reg = &lt;0x6&gt;;</div><div class='add'>+</div><div class='add'>+							mix_in7: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mix_in7&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@7 {</div><div class='add'>+							reg = &lt;0x7&gt;;</div><div class='add'>+</div><div class='add'>+							mix_in8: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mix_in8&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@8 {</div><div class='add'>+							reg = &lt;0x8&gt;;</div><div class='add'>+</div><div class='add'>+							mix_in9: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mix_in9&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@9 {</div><div class='add'>+							reg = &lt;0x9&gt;;</div><div class='add'>+</div><div class='add'>+							mix_in10: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mix_in10&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						mix_out1_port: port@a {</div><div class='add'>+							reg = &lt;0xa&gt;;</div><div class='add'>+</div><div class='add'>+							mix_out1: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mix_out1&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						mix_out2_port: port@b {</div><div class='add'>+							reg = &lt;0xb&gt;;</div><div class='add'>+</div><div class='add'>+							mix_out2: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mix_out2&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						mix_out3_port: port@c {</div><div class='add'>+							reg = &lt;0xc&gt;;</div><div class='add'>+</div><div class='add'>+							mix_out3: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mix_out3&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						mix_out4_port: port@d {</div><div class='add'>+							reg = &lt;0xd&gt;;</div><div class='add'>+</div><div class='add'>+							mix_out4: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mix_out4&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						mix_out5_port: port@e {</div><div class='add'>+							reg = &lt;0xe&gt;;</div><div class='add'>+</div><div class='add'>+							mix_out5: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mix_out5&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_admaif: admaif@290f000 {</div><div class='add'>+					compatible = "nvidia,tegra234-admaif",</div><div class='add'>+						     "nvidia,tegra186-admaif";</div><div class='add'>+					reg = &lt;0x0 0x0290f000 0x0 0x1000&gt;;</div><div class='add'>+					dmas = &lt;&amp;adma 1&gt;, &lt;&amp;adma 1&gt;,</div><div class='add'>+					       &lt;&amp;adma 2&gt;, &lt;&amp;adma 2&gt;,</div><div class='add'>+					       &lt;&amp;adma 3&gt;, &lt;&amp;adma 3&gt;,</div><div class='add'>+					       &lt;&amp;adma 4&gt;, &lt;&amp;adma 4&gt;,</div><div class='add'>+					       &lt;&amp;adma 5&gt;, &lt;&amp;adma 5&gt;,</div><div class='add'>+					       &lt;&amp;adma 6&gt;, &lt;&amp;adma 6&gt;,</div><div class='add'>+					       &lt;&amp;adma 7&gt;, &lt;&amp;adma 7&gt;,</div><div class='add'>+					       &lt;&amp;adma 8&gt;, &lt;&amp;adma 8&gt;,</div><div class='add'>+					       &lt;&amp;adma 9&gt;, &lt;&amp;adma 9&gt;,</div><div class='add'>+					       &lt;&amp;adma 10&gt;, &lt;&amp;adma 10&gt;,</div><div class='add'>+					       &lt;&amp;adma 11&gt;, &lt;&amp;adma 11&gt;,</div><div class='add'>+					       &lt;&amp;adma 12&gt;, &lt;&amp;adma 12&gt;,</div><div class='add'>+					       &lt;&amp;adma 13&gt;, &lt;&amp;adma 13&gt;,</div><div class='add'>+					       &lt;&amp;adma 14&gt;, &lt;&amp;adma 14&gt;,</div><div class='add'>+					       &lt;&amp;adma 15&gt;, &lt;&amp;adma 15&gt;,</div><div class='add'>+					       &lt;&amp;adma 16&gt;, &lt;&amp;adma 16&gt;,</div><div class='add'>+					       &lt;&amp;adma 17&gt;, &lt;&amp;adma 17&gt;,</div><div class='add'>+					       &lt;&amp;adma 18&gt;, &lt;&amp;adma 18&gt;,</div><div class='add'>+					       &lt;&amp;adma 19&gt;, &lt;&amp;adma 19&gt;,</div><div class='add'>+					       &lt;&amp;adma 20&gt;, &lt;&amp;adma 20&gt;;</div><div class='add'>+					dma-names = "rx1", "tx1",</div><div class='add'>+						    "rx2", "tx2",</div><div class='add'>+						    "rx3", "tx3",</div><div class='add'>+						    "rx4", "tx4",</div><div class='add'>+						    "rx5", "tx5",</div><div class='add'>+						    "rx6", "tx6",</div><div class='add'>+						    "rx7", "tx7",</div><div class='add'>+						    "rx8", "tx8",</div><div class='add'>+						    "rx9", "tx9",</div><div class='add'>+						    "rx10", "tx10",</div><div class='add'>+						    "rx11", "tx11",</div><div class='add'>+						    "rx12", "tx12",</div><div class='add'>+						    "rx13", "tx13",</div><div class='add'>+						    "rx14", "tx14",</div><div class='add'>+						    "rx15", "tx15",</div><div class='add'>+						    "rx16", "tx16",</div><div class='add'>+						    "rx17", "tx17",</div><div class='add'>+						    "rx18", "tx18",</div><div class='add'>+						    "rx19", "tx19",</div><div class='add'>+						    "rx20", "tx20";</div><div class='add'>+					interconnects = &lt;&amp;mc TEGRA234_MEMORY_CLIENT_APEDMAR &amp;emc&gt;,</div><div class='add'>+							&lt;&amp;mc TEGRA234_MEMORY_CLIENT_APEDMAW &amp;emc&gt;;</div><div class='add'>+					interconnect-names = "dma-mem", "write";</div><div class='add'>+					iommus = &lt;&amp;smmu_niso0 TEGRA234_SID_APE&gt;;</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						admaif0_port: port@0 {</div><div class='add'>+							reg = &lt;0x0&gt;;</div><div class='add'>+</div><div class='add'>+							admaif0: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif0&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif1_port: port@1 {</div><div class='add'>+							reg = &lt;0x1&gt;;</div><div class='add'>+</div><div class='add'>+							admaif1: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif1&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif2_port: port@2 {</div><div class='add'>+							reg = &lt;0x2&gt;;</div><div class='add'>+</div><div class='add'>+							admaif2: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif2&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif3_port: port@3 {</div><div class='add'>+							reg = &lt;0x3&gt;;</div><div class='add'>+</div><div class='add'>+							admaif3: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif3&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif4_port: port@4 {</div><div class='add'>+							reg = &lt;0x4&gt;;</div><div class='add'>+</div><div class='add'>+							admaif4: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif4&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif5_port: port@5 {</div><div class='add'>+							reg = &lt;0x5&gt;;</div><div class='add'>+</div><div class='add'>+							admaif5: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif5&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif6_port: port@6 {</div><div class='add'>+							reg = &lt;0x6&gt;;</div><div class='add'>+</div><div class='add'>+							admaif6: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif6&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif7_port: port@7 {</div><div class='add'>+							reg = &lt;0x7&gt;;</div><div class='add'>+</div><div class='add'>+							admaif7: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif7&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif8_port: port@8 {</div><div class='add'>+							reg = &lt;0x8&gt;;</div><div class='add'>+</div><div class='add'>+							admaif8: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif8&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif9_port: port@9 {</div><div class='add'>+							reg = &lt;0x9&gt;;</div><div class='add'>+</div><div class='add'>+							admaif9: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif9&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif10_port: port@a {</div><div class='add'>+							reg = &lt;0xa&gt;;</div><div class='add'>+</div><div class='add'>+							admaif10: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif10&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif11_port: port@b {</div><div class='add'>+							reg = &lt;0xb&gt;;</div><div class='add'>+</div><div class='add'>+							admaif11: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif11&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif12_port: port@c {</div><div class='add'>+							reg = &lt;0xc&gt;;</div><div class='add'>+</div><div class='add'>+							admaif12: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif12&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif13_port: port@d {</div><div class='add'>+							reg = &lt;0xd&gt;;</div><div class='add'>+</div><div class='add'>+							admaif13: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif13&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif14_port: port@e {</div><div class='add'>+							reg = &lt;0xe&gt;;</div><div class='add'>+</div><div class='add'>+							admaif14: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif14&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif15_port: port@f {</div><div class='add'>+							reg = &lt;0xf&gt;;</div><div class='add'>+</div><div class='add'>+							admaif15: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif15&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif16_port: port@10 {</div><div class='add'>+							reg = &lt;0x10&gt;;</div><div class='add'>+</div><div class='add'>+							admaif16: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif16&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif17_port: port@11 {</div><div class='add'>+							reg = &lt;0x11&gt;;</div><div class='add'>+</div><div class='add'>+							admaif17: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif17&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif18_port: port@12 {</div><div class='add'>+							reg = &lt;0x12&gt;;</div><div class='add'>+</div><div class='add'>+							admaif18: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif18&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif19_port: port@13 {</div><div class='add'>+							reg = &lt;0x13&gt;;</div><div class='add'>+</div><div class='add'>+							admaif19: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif19&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_asrc: asrc@2910000 {</div><div class='add'>+					compatible = "nvidia,tegra234-asrc",</div><div class='add'>+						     "nvidia,tegra186-asrc";</div><div class='add'>+					reg = &lt;0x0 0x2910000 0x0 0x2000&gt;;</div><div class='add'>+					sound-name-prefix = "ASRC1";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0x0&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_in1_ep: endpoint {</div><div class='add'>+								remote-endpoint =</div><div class='add'>+									&lt;&amp;xbar_asrc_in1_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@1 {</div><div class='add'>+							reg = &lt;0x1&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_in2_ep: endpoint {</div><div class='add'>+								remote-endpoint =</div><div class='add'>+									&lt;&amp;xbar_asrc_in2_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@2 {</div><div class='add'>+							reg = &lt;0x2&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_in3_ep: endpoint {</div><div class='add'>+								remote-endpoint =</div><div class='add'>+									&lt;&amp;xbar_asrc_in3_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@3 {</div><div class='add'>+							reg = &lt;0x3&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_in4_ep: endpoint {</div><div class='add'>+								remote-endpoint =</div><div class='add'>+									&lt;&amp;xbar_asrc_in4_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@4 {</div><div class='add'>+							reg = &lt;0x4&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_in5_ep: endpoint {</div><div class='add'>+								remote-endpoint =</div><div class='add'>+									&lt;&amp;xbar_asrc_in5_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@5 {</div><div class='add'>+							reg = &lt;0x5&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_in6_ep: endpoint {</div><div class='add'>+								remote-endpoint =</div><div class='add'>+									&lt;&amp;xbar_asrc_in6_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@6 {</div><div class='add'>+							reg = &lt;0x6&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_in7_ep: endpoint {</div><div class='add'>+								remote-endpoint =</div><div class='add'>+									&lt;&amp;xbar_asrc_in7_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						asrc_out1_port: port@7 {</div><div class='add'>+							reg = &lt;0x7&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_out1_ep: endpoint {</div><div class='add'>+								remote-endpoint =</div><div class='add'>+									&lt;&amp;xbar_asrc_out1_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						asrc_out2_port: port@8 {</div><div class='add'>+							reg = &lt;0x8&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_out2_ep: endpoint {</div><div class='add'>+								remote-endpoint =</div><div class='add'>+									&lt;&amp;xbar_asrc_out2_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						asrc_out3_port: port@9 {</div><div class='add'>+							reg = &lt;0x9&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_out3_ep: endpoint {</div><div class='add'>+								remote-endpoint =</div><div class='add'>+									&lt;&amp;xbar_asrc_out3_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						asrc_out4_port: port@a {</div><div class='add'>+							reg = &lt;0xa&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_out4_ep: endpoint {</div><div class='add'>+								remote-endpoint =</div><div class='add'>+									&lt;&amp;xbar_asrc_out4_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						asrc_out5_port: port@b {</div><div class='add'>+							reg = &lt;0xb&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_out5_ep: endpoint {</div><div class='add'>+								remote-endpoint =</div><div class='add'>+									&lt;&amp;xbar_asrc_out5_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						asrc_out6_port:	port@c {</div><div class='add'>+							reg = &lt;0xc&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_out6_ep: endpoint {</div><div class='add'>+								remote-endpoint =</div><div class='add'>+									&lt;&amp;xbar_asrc_out6_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0x0&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif0: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif0&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;0x1&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif1: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif1&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@2 {</div><div class='add'>+						reg = &lt;0x2&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif2: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif2&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@3 {</div><div class='add'>+						reg = &lt;0x3&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif3: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif3&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@4 {</div><div class='add'>+						reg = &lt;0x4&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif4: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif4&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@5 {</div><div class='add'>+						reg = &lt;0x5&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif5: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif5&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@6 {</div><div class='add'>+						reg = &lt;0x6&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif6: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif6&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@7 {</div><div class='add'>+						reg = &lt;0x7&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif7: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif7&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@8 {</div><div class='add'>+						reg = &lt;0x8&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif8: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif8&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@9 {</div><div class='add'>+						reg = &lt;0x9&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif9: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif9&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@a {</div><div class='add'>+						reg = &lt;0xa&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif10: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif10&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@b {</div><div class='add'>+						reg = &lt;0xb&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif11: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif11&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@c {</div><div class='add'>+						reg = &lt;0xc&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif12: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif12&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@d {</div><div class='add'>+						reg = &lt;0xd&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif13: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif13&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@e {</div><div class='add'>+						reg = &lt;0xe&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif14: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif14&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@f {</div><div class='add'>+						reg = &lt;0xf&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif15: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif15&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@10 {</div><div class='add'>+						reg = &lt;0x10&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif16: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif16&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@11 {</div><div class='add'>+						reg = &lt;0x11&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif17: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif17&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@12 {</div><div class='add'>+						reg = &lt;0x12&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif18: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif18&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@13 {</div><div class='add'>+						reg = &lt;0x13&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif19: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif19&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_i2s1_port: port@14 {</div><div class='add'>+						reg = &lt;0x14&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_i2s1: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;i2s1_cif&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_i2s2_port: port@15 {</div><div class='add'>+						reg = &lt;0x15&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_i2s2: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;i2s2_cif&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_i2s3_port: port@16 {</div><div class='add'>+						reg = &lt;0x16&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_i2s3: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;i2s3_cif&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_i2s4_port: port@17 {</div><div class='add'>+						reg = &lt;0x17&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_i2s4: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;i2s4_cif&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_i2s5_port: port@18 {</div><div class='add'>+						reg = &lt;0x18&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_i2s5: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;i2s5_cif&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_i2s6_port: port@19 {</div><div class='add'>+						reg = &lt;0x19&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_i2s6: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;i2s6_cif&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_dmic1_port: port@1a {</div><div class='add'>+						reg = &lt;0x1a&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_dmic1: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;dmic1_cif&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_dmic2_port: port@1b {</div><div class='add'>+						reg = &lt;0x1b&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_dmic2: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;dmic2_cif&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_dmic3_port: port@1c {</div><div class='add'>+						reg = &lt;0x1c&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_dmic3: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;dmic3_cif&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_dmic4_port: port@1d {</div><div class='add'>+						reg = &lt;0x1d&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_dmic4: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;dmic4_cif&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_dspk1_port: port@1e {</div><div class='add'>+						reg = &lt;0x1e&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_dspk1: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;dspk1_cif&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_dspk2_port: port@1f {</div><div class='add'>+						reg = &lt;0x1f&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_dspk2: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;dspk2_cif&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_sfc1_in_port: port@20 {</div><div class='add'>+						reg = &lt;0x20&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_sfc1_in: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;sfc1_cif_in&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@21 {</div><div class='add'>+						reg = &lt;0x21&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_sfc1_out: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;sfc1_cif_out&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_sfc2_in_port: port@22 {</div><div class='add'>+						reg = &lt;0x22&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_sfc2_in: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;sfc2_cif_in&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@23 {</div><div class='add'>+						reg = &lt;0x23&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_sfc2_out: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;sfc2_cif_out&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_sfc3_in_port: port@24 {</div><div class='add'>+						reg = &lt;0x24&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_sfc3_in: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;sfc3_cif_in&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@25 {</div><div class='add'>+						reg = &lt;0x25&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_sfc3_out: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;sfc3_cif_out&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_sfc4_in_port: port@26 {</div><div class='add'>+						reg = &lt;0x26&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_sfc4_in: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;sfc4_cif_in&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@27 {</div><div class='add'>+						reg = &lt;0x27&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_sfc4_out: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;sfc4_cif_out&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mvc1_in_port: port@28 {</div><div class='add'>+						reg = &lt;0x28&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mvc1_in: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mvc1_cif_in&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@29 {</div><div class='add'>+						reg = &lt;0x29&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mvc1_out: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mvc1_cif_out&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mvc2_in_port: port@2a {</div><div class='add'>+						reg = &lt;0x2a&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mvc2_in: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mvc2_cif_in&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@2b {</div><div class='add'>+						reg = &lt;0x2b&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mvc2_out: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mvc2_cif_out&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx1_in1_port: port@2c {</div><div class='add'>+						reg = &lt;0x2c&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx1_in1: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx1_in1&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx1_in2_port: port@2d {</div><div class='add'>+						reg = &lt;0x2d&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx1_in2: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx1_in2&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx1_in3_port: port@2e {</div><div class='add'>+						reg = &lt;0x2e&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx1_in3: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx1_in3&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx1_in4_port: port@2f {</div><div class='add'>+						reg = &lt;0x2f&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx1_in4: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx1_in4&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@30 {</div><div class='add'>+						reg = &lt;0x30&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx1_out: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx1_out&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx2_in1_port: port@31 {</div><div class='add'>+						reg = &lt;0x31&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx2_in1: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx2_in1&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx2_in2_port: port@32 {</div><div class='add'>+						reg = &lt;0x32&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx2_in2: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx2_in2&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx2_in3_port: port@33 {</div><div class='add'>+						reg = &lt;0x33&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx2_in3: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx2_in3&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx2_in4_port: port@34 {</div><div class='add'>+						reg = &lt;0x34&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx2_in4: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx2_in4&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@35 {</div><div class='add'>+						reg = &lt;0x35&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx2_out: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx2_out&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx3_in1_port: port@36 {</div><div class='add'>+						reg = &lt;0x36&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx3_in1: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx3_in1&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx3_in2_port: port@37 {</div><div class='add'>+						reg = &lt;0x37&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx3_in2: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx3_in2&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx3_in3_port: port@38 {</div><div class='add'>+						reg = &lt;0x38&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx3_in3: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx3_in3&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx3_in4_port: port@39 {</div><div class='add'>+						reg = &lt;0x39&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx3_in4: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx3_in4&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@3a {</div><div class='add'>+						reg = &lt;0x3a&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx3_out: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx3_out&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx4_in1_port: port@3b {</div><div class='add'>+						reg = &lt;0x3b&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx4_in1: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx4_in1&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx4_in2_port: port@3c {</div><div class='add'>+						reg = &lt;0x3c&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx4_in2: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx4_in2&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx4_in3_port: port@3d {</div><div class='add'>+						reg = &lt;0x3d&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx4_in3: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx4_in3&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx4_in4_port: port@3e {</div><div class='add'>+						reg = &lt;0x3e&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx4_in4: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx4_in4&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@3f {</div><div class='add'>+						reg = &lt;0x3f&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx4_out: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx4_out&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_adx1_in_port: port@40 {</div><div class='add'>+						reg = &lt;0x40&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx1_in: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx1_in&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@41 {</div><div class='add'>+						reg = &lt;0x41&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx1_out1: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx1_out1&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@42 {</div><div class='add'>+						reg = &lt;0x42&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx1_out2: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx1_out2&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@43 {</div><div class='add'>+						reg = &lt;0x43&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx1_out3: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx1_out3&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@44 {</div><div class='add'>+						reg = &lt;0x44&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx1_out4: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx1_out4&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_adx2_in_port: port@45 {</div><div class='add'>+						reg = &lt;0x45&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx2_in: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx2_in&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@46 {</div><div class='add'>+						reg = &lt;0x46&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx2_out1: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx2_out1&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@47 {</div><div class='add'>+						reg = &lt;0x47&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx2_out2: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx2_out2&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@48 {</div><div class='add'>+						reg = &lt;0x48&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx2_out3: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx2_out3&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@49 {</div><div class='add'>+						reg = &lt;0x49&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx2_out4: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx2_out4&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_adx3_in_port: port@4a {</div><div class='add'>+						reg = &lt;0x4a&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx3_in: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx3_in&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@4b {</div><div class='add'>+						reg = &lt;0x4b&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx3_out1: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx3_out1&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@4c {</div><div class='add'>+						reg = &lt;0x4c&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx3_out2: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx3_out2&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@4d {</div><div class='add'>+						reg = &lt;0x4d&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx3_out3: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx3_out3&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@4e {</div><div class='add'>+						reg = &lt;0x4e&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx3_out4: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx3_out4&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_adx4_in_port: port@4f {</div><div class='add'>+						reg = &lt;0x4f&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx4_in: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx4_in&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@50 {</div><div class='add'>+						reg = &lt;0x50&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx4_out1: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx4_out1&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@51 {</div><div class='add'>+						reg = &lt;0x51&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx4_out2: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx4_out2&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@52 {</div><div class='add'>+						reg = &lt;0x52&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx4_out3: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx4_out3&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@53 {</div><div class='add'>+						reg = &lt;0x53&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx4_out4: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx4_out4&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mix_in1_port: port@54 {</div><div class='add'>+						reg = &lt;0x54&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mix_in1: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mix_in1&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mix_in2_port: port@55 {</div><div class='add'>+						reg = &lt;0x55&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mix_in2: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mix_in2&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mix_in3_port: port@56 {</div><div class='add'>+						reg = &lt;0x56&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mix_in3: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mix_in3&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mix_in4_port: port@57 {</div><div class='add'>+						reg = &lt;0x57&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mix_in4: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mix_in4&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mix_in5_port: port@58 {</div><div class='add'>+						reg = &lt;0x58&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mix_in5: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mix_in5&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mix_in6_port: port@59 {</div><div class='add'>+						reg = &lt;0x59&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mix_in6: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mix_in6&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mix_in7_port: port@5a {</div><div class='add'>+						reg = &lt;0x5a&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mix_in7: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mix_in7&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mix_in8_port: port@5b {</div><div class='add'>+						reg = &lt;0x5b&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mix_in8: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mix_in8&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mix_in9_port: port@5c {</div><div class='add'>+						reg = &lt;0x5c&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mix_in9: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mix_in9&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mix_in10_port: port@5d {</div><div class='add'>+						reg = &lt;0x5d&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mix_in10: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mix_in10&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@5e {</div><div class='add'>+						reg = &lt;0x5e&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mix_out1: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mix_out1&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@5f {</div><div class='add'>+						reg = &lt;0x5f&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mix_out2: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mix_out2&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@60 {</div><div class='add'>+						reg = &lt;0x60&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mix_out3: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mix_out3&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@61 {</div><div class='add'>+						reg = &lt;0x61&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mix_out4: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mix_out4&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@62 {</div><div class='add'>+						reg = &lt;0x62&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mix_out5: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mix_out5&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_asrc_in1_port: port@63 {</div><div class='add'>+						reg = &lt;0x63&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_in1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_in1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@64 {</div><div class='add'>+						reg = &lt;0x64&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_out1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_out1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_asrc_in2_port: port@65 {</div><div class='add'>+						reg = &lt;0x65&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_in2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_in2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@66 {</div><div class='add'>+						reg = &lt;0x66&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_out2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_out2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_asrc_in3_port: port@67 {</div><div class='add'>+						reg = &lt;0x67&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_in3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_in3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@68 {</div><div class='add'>+						reg = &lt;0x68&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_out3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_out3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_asrc_in4_port: port@69 {</div><div class='add'>+						reg = &lt;0x69&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_in4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_in4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@6a {</div><div class='add'>+						reg = &lt;0x6a&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_out4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_out4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_asrc_in5_port: port@6b {</div><div class='add'>+						reg = &lt;0x6b&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_in5_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_in5_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@6c {</div><div class='add'>+						reg = &lt;0x6c&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_out5_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_out5_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_asrc_in6_port: port@6d {</div><div class='add'>+						reg = &lt;0x6d&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_in6_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_in6_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@6e {</div><div class='add'>+						reg = &lt;0x6e&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_out6_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_out6_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_asrc_in7_port: port@6f {</div><div class='add'>+						reg = &lt;0x6f&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_in7_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_in7_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_ope1_in_port: port@70 {</div><div class='add'>+						reg = &lt;0x70&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_ope1_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;ope1_cif_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@71 {</div><div class='add'>+						reg = &lt;0x71&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_ope1_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;ope1_cif_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			adma: dma-controller@2930000 {</div><div class='add'>+				compatible = "nvidia,tegra234-adma",</div><div class='add'>+					     "nvidia,tegra186-adma";</div><div class='add'>+				reg = &lt;0x0 0x02930000 0x0 0x20000&gt;;</div><div class='add'>+				interrupt-parent = &lt;&amp;agic&gt;;</div><div class='add'>+				interrupts =  &lt;GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#dma-cells = &lt;1&gt;;</div><div class='add'>+				clocks = &lt;&amp;bpmp TEGRA234_CLK_AHUB&gt;;</div><div class='add'>+				clock-names = "d_audio";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			agic: interrupt-controller@2a40000 {</div><div class='add'>+				compatible = "nvidia,tegra234-agic",</div><div class='add'>+					     "nvidia,tegra210-agic";</div><div class='add'>+				#interrupt-cells = &lt;3&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				reg = &lt;0x0 0x02a41000 0x0 0x1000&gt;,</div><div class='add'>+				      &lt;0x0 0x02a42000 0x0 0x2000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 145</div><div class='add'>+					      (GIC_CPU_MASK_SIMPLE(4) |</div><div class='add'>+					       IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='add'>+				clocks = &lt;&amp;bpmp TEGRA234_CLK_APE&gt;;</div><div class='add'>+				clock-names = "clk";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mc: memory-controller@2c00000 {</div><div class='add'>+			compatible = "nvidia,tegra234-mc";</div><div class='add'>+			reg = &lt;0x0 0x02c00000 0x0 0x10000&gt;,   /* MC-SID */</div><div class='add'>+			      &lt;0x0 0x02c10000 0x0 0x10000&gt;,   /* MC Broadcast*/</div><div class='add'>+			      &lt;0x0 0x02c20000 0x0 0x10000&gt;,   /* MC0 */</div><div class='add'>+			      &lt;0x0 0x02c30000 0x0 0x10000&gt;,   /* MC1 */</div><div class='add'>+			      &lt;0x0 0x02c40000 0x0 0x10000&gt;,   /* MC2 */</div><div class='add'>+			      &lt;0x0 0x02c50000 0x0 0x10000&gt;,   /* MC3 */</div><div class='add'>+			      &lt;0x0 0x02b80000 0x0 0x10000&gt;,   /* MC4 */</div><div class='add'>+			      &lt;0x0 0x02b90000 0x0 0x10000&gt;,   /* MC5 */</div><div class='add'>+			      &lt;0x0 0x02ba0000 0x0 0x10000&gt;,   /* MC6 */</div><div class='add'>+			      &lt;0x0 0x02bb0000 0x0 0x10000&gt;,   /* MC7 */</div><div class='add'>+			      &lt;0x0 0x01700000 0x0 0x10000&gt;,   /* MC8 */</div><div class='add'>+			      &lt;0x0 0x01710000 0x0 0x10000&gt;,   /* MC9 */</div><div class='add'>+			      &lt;0x0 0x01720000 0x0 0x10000&gt;,   /* MC10 */</div><div class='add'>+			      &lt;0x0 0x01730000 0x0 0x10000&gt;,   /* MC11 */</div><div class='add'>+			      &lt;0x0 0x01740000 0x0 0x10000&gt;,   /* MC12 */</div><div class='add'>+			      &lt;0x0 0x01750000 0x0 0x10000&gt;,   /* MC13 */</div><div class='add'>+			      &lt;0x0 0x01760000 0x0 0x10000&gt;,   /* MC14 */</div><div class='add'>+			      &lt;0x0 0x01770000 0x0 0x10000&gt;;   /* MC15 */</div><div class='add'>+			reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3",</div><div class='add'>+				    "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10",</div><div class='add'>+				    "ch11", "ch12", "ch13", "ch14", "ch15";</div><div class='add'>+			interrupts = &lt;GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#interconnect-cells = &lt;1&gt;;</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges = &lt;0x0 0x01700000 0x0 0x01700000 0x0 0x100000&gt;,</div><div class='add'>+				 &lt;0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000&gt;,</div><div class='add'>+				 &lt;0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000&gt;;</div><div class='add'>+</div><div class='add'>+			/*</div><div class='add'>+			 * Bit 39 of addresses passing through the memory</div><div class='add'>+			 * controller selects the XBAR format used when memory</div><div class='add'>+			 * is accessed. This is used to transparently access</div><div class='add'>+			 * memory in the XBAR format used by the discrete GPU</div><div class='add'>+			 * (bit 39 set) or Tegra (bit 39 clear).</div><div class='add'>+			 *</div><div class='add'>+			 * As a consequence, the operating system must ensure</div><div class='add'>+			 * that bit 39 is never used implicitly, for example</div><div class='add'>+			 * via an I/O virtual address mapping of an IOMMU. If</div><div class='add'>+			 * devices require access to the XBAR switch, their</div><div class='add'>+			 * drivers must set this bit explicitly.</div><div class='add'>+			 *</div><div class='add'>+			 * Limit the DMA range for memory clients to [38:0].</div><div class='add'>+			 */</div><div class='add'>+			dma-ranges = &lt;0x0 0x0 0x0 0x0 0x80 0x0&gt;;</div><div class='add'>+</div><div class='add'>+			emc: external-memory-controller@2c60000 {</div><div class='add'>+				compatible = "nvidia,tegra234-emc";</div><div class='add'>+				reg = &lt;0x0 0x02c60000 0x0 0x90000&gt;,</div><div class='add'>+				      &lt;0x0 0x01780000 0x0 0x80000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;bpmp TEGRA234_CLK_EMC&gt;;</div><div class='add'>+				clock-names = "emc";</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				#interconnect-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				nvidia,bpmp = &lt;&amp;bpmp&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uarta: serial@3100000 {</div><div class='add'>+			compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart";</div><div class='add'>+			reg = &lt;0x0 0x03100000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_UARTA&gt;;</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_UARTA&gt;;</div><div class='add'>+			dmas = &lt;&amp;gpcdma 8&gt;, &lt;&amp;gpcdma 8&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uarte: serial@3140000 {</div><div class='add'>+			compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart";</div><div class='add'>+			reg = &lt;0x0 0x03140000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_UARTE&gt;;</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_UARTE&gt;;</div><div class='add'>+			dmas = &lt;&amp;gpcdma 20&gt;, &lt;&amp;gpcdma 20&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gen1_i2c: i2c@3160000 {</div><div class='add'>+			compatible = "nvidia,tegra194-i2c";</div><div class='add'>+			reg = &lt;0x0 0x3160000 0x0 0x100&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+			interrupts = &lt;GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			clock-frequency = &lt;400000&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_I2C1&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			assigned-clocks = &lt;&amp;bpmp TEGRA234_CLK_I2C1&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;bpmp TEGRA234_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			clock-names = "div-clk", "parent";</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_I2C1&gt;;</div><div class='add'>+			reset-names = "i2c";</div><div class='add'>+			dmas = &lt;&amp;gpcdma 21&gt;, &lt;&amp;gpcdma 21&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cam_i2c: i2c@3180000 {</div><div class='add'>+			compatible = "nvidia,tegra194-i2c";</div><div class='add'>+			reg = &lt;0x0 0x3180000 0x0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+			clock-frequency = &lt;400000&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_I2C3&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			assigned-clocks = &lt;&amp;bpmp TEGRA234_CLK_I2C3&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;bpmp TEGRA234_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			clock-names = "div-clk", "parent";</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_I2C3&gt;;</div><div class='add'>+			reset-names = "i2c";</div><div class='add'>+			dmas = &lt;&amp;gpcdma 23&gt;, &lt;&amp;gpcdma 23&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dp_aux_ch1_i2c: i2c@3190000 {</div><div class='add'>+			compatible = "nvidia,tegra194-i2c";</div><div class='add'>+			reg = &lt;0x0 0x3190000 0x0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+			clock-frequency = &lt;100000&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_I2C4&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			assigned-clocks = &lt;&amp;bpmp TEGRA234_CLK_I2C4&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;bpmp TEGRA234_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			clock-names = "div-clk", "parent";</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_I2C4&gt;;</div><div class='add'>+			reset-names = "i2c";</div><div class='add'>+			dmas = &lt;&amp;gpcdma 26&gt;, &lt;&amp;gpcdma 26&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dp_aux_ch0_i2c: i2c@31b0000 {</div><div class='add'>+			compatible = "nvidia,tegra194-i2c";</div><div class='add'>+			reg = &lt;0x0 0x31b0000 0x0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+			clock-frequency = &lt;100000&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_I2C6&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			assigned-clocks = &lt;&amp;bpmp TEGRA234_CLK_I2C6&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;bpmp TEGRA234_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			clock-names = "div-clk", "parent";</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_I2C6&gt;;</div><div class='add'>+			reset-names = "i2c";</div><div class='add'>+			dmas = &lt;&amp;gpcdma 30&gt;, &lt;&amp;gpcdma 30&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dp_aux_ch2_i2c: i2c@31c0000 {</div><div class='add'>+			compatible = "nvidia,tegra194-i2c";</div><div class='add'>+			reg = &lt;0x0 0x31c0000 0x0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+			clock-frequency = &lt;100000&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_I2C7&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			assigned-clocks = &lt;&amp;bpmp TEGRA234_CLK_I2C7&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;bpmp TEGRA234_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			clock-names = "div-clk", "parent";</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_I2C7&gt;;</div><div class='add'>+			reset-names = "i2c";</div><div class='add'>+			dmas = &lt;&amp;gpcdma 27&gt;, &lt;&amp;gpcdma 27&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uarti: serial@31d0000 {</div><div class='add'>+			compatible = "arm,sbsa-uart";</div><div class='add'>+			reg = &lt;0x0 0x31d0000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dp_aux_ch3_i2c: i2c@31e0000 {</div><div class='add'>+			compatible = "nvidia,tegra194-i2c";</div><div class='add'>+			reg = &lt;0x0 0x31e0000 0x0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+			clock-frequency = &lt;100000&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_I2C9&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			assigned-clocks = &lt;&amp;bpmp TEGRA234_CLK_I2C9&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;bpmp TEGRA234_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			clock-names = "div-clk", "parent";</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_I2C9&gt;;</div><div class='add'>+			reset-names = "i2c";</div><div class='add'>+			dmas = &lt;&amp;gpcdma 31&gt;, &lt;&amp;gpcdma 31&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi@3210000 {</div><div class='add'>+			compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";</div><div class='add'>+			reg = &lt;0x0 0x03210000 0x0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_SPI1&gt;;</div><div class='add'>+			assigned-clocks = &lt;&amp;bpmp TEGRA234_CLK_SPI1&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;bpmp TEGRA234_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			clock-names = "spi";</div><div class='add'>+			iommus = &lt;&amp;smmu_niso0 TEGRA234_SID_GPCDMA&gt;;</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_SPI1&gt;;</div><div class='add'>+			reset-names = "spi";</div><div class='add'>+			dmas = &lt;&amp;gpcdma 15&gt;, &lt;&amp;gpcdma 15&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+			dma-coherent;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi@3230000 {</div><div class='add'>+			compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";</div><div class='add'>+			reg = &lt;0x0 0x03230000 0x0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_SPI3&gt;;</div><div class='add'>+			clock-names = "spi";</div><div class='add'>+			iommus = &lt;&amp;smmu_niso0 TEGRA234_SID_GPCDMA&gt;;</div><div class='add'>+			assigned-clocks = &lt;&amp;bpmp TEGRA234_CLK_SPI3&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;bpmp TEGRA234_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_SPI3&gt;;</div><div class='add'>+			reset-names = "spi";</div><div class='add'>+			dmas = &lt;&amp;gpcdma 17&gt;, &lt;&amp;gpcdma 17&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+			dma-coherent;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi@3270000 {</div><div class='add'>+			compatible = "nvidia,tegra234-qspi";</div><div class='add'>+			reg = &lt;0x0 0x3270000 0x0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_QSPI0_2X_PM&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_QSPI0_PM&gt;;</div><div class='add'>+			clock-names = "qspi", "qspi_out";</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_QSPI0&gt;;</div><div class='add'>+			iommus = &lt;&amp;smmu_niso1 TEGRA234_SID_QSPI0&gt;;</div><div class='add'>+			assigned-clocks = &lt;&amp;bpmp TEGRA234_CLK_QSPI0_2X_PM&gt;,</div><div class='add'>+					  &lt;&amp;bpmp TEGRA234_CLK_QSPI0_PM&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;199999999 99999999&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;bpmp TEGRA234_CLK_PLLC&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pwm1: pwm@3280000 {</div><div class='add'>+			compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";</div><div class='add'>+			reg = &lt;0x0 0x3280000 0x0 0x10000&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_PWM1&gt;;</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_PWM1&gt;;</div><div class='add'>+			reset-names = "pwm";</div><div class='add'>+			status = "disabled";</div><div class='add'>+			#pwm-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pwm2: pwm@3290000 {</div><div class='add'>+			compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";</div><div class='add'>+			reg = &lt;0x0 0x3290000 0x0 0x10000&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_PWM2&gt;;</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_PWM2&gt;;</div><div class='add'>+			reset-names = "pwm";</div><div class='add'>+			status = "disabled";</div><div class='add'>+			#pwm-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pwm3: pwm@32a0000 {</div><div class='add'>+			compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";</div><div class='add'>+			reg = &lt;0x0 0x32a0000 0x0 0x10000&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_PWM3&gt;;</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_PWM3&gt;;</div><div class='add'>+			reset-names = "pwm";</div><div class='add'>+			status = "disabled";</div><div class='add'>+			#pwm-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pwm5: pwm@32c0000 {</div><div class='add'>+			compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";</div><div class='add'>+			reg = &lt;0x0 0x32c0000 0x0 0x10000&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_PWM5&gt;;</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_PWM5&gt;;</div><div class='add'>+			reset-names = "pwm";</div><div class='add'>+			status = "disabled";</div><div class='add'>+			#pwm-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pwm6: pwm@32d0000 {</div><div class='add'>+			compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";</div><div class='add'>+			reg = &lt;0x0 0x32d0000 0x0 0x10000&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_PWM6&gt;;</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_PWM6&gt;;</div><div class='add'>+			reset-names = "pwm";</div><div class='add'>+			status = "disabled";</div><div class='add'>+			#pwm-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pwm7: pwm@32e0000 {</div><div class='add'>+			compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";</div><div class='add'>+			reg = &lt;0x0 0x32e0000 0x0 0x10000&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_PWM7&gt;;</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_PWM7&gt;;</div><div class='add'>+			reset-names = "pwm";</div><div class='add'>+			status = "disabled";</div><div class='add'>+			#pwm-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pwm8: pwm@32f0000 {</div><div class='add'>+			compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";</div><div class='add'>+			reg = &lt;0x0 0x32f0000 0x0 0x10000&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_PWM8&gt;;</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_PWM8&gt;;</div><div class='add'>+			reset-names = "pwm";</div><div class='add'>+			status = "disabled";</div><div class='add'>+			#pwm-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi@3300000 {</div><div class='add'>+			compatible = "nvidia,tegra234-qspi";</div><div class='add'>+			reg = &lt;0x0 0x3300000 0x0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_QSPI1_2X_PM&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_QSPI1_PM&gt;;</div><div class='add'>+			clock-names = "qspi", "qspi_out";</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_QSPI1&gt;;</div><div class='add'>+			iommus = &lt;&amp;smmu_niso1 TEGRA234_SID_QSPI1&gt;;</div><div class='add'>+			assigned-clocks = &lt;&amp;bpmp TEGRA234_CLK_QSPI1_2X_PM&gt;,</div><div class='add'>+					  &lt;&amp;bpmp TEGRA234_CLK_QSPI1_PM&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;199999999 99999999&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;bpmp TEGRA234_CLK_PLLC&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmc@3400000 {</div><div class='add'>+			compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci";</div><div class='add'>+			reg = &lt;0x0 0x03400000 0x0 0x20000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_SDMMC1&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_SDMMC_LEGACY_TM&gt;;</div><div class='add'>+			clock-names = "sdhci", "tmclk";</div><div class='add'>+			assigned-clocks = &lt;&amp;bpmp TEGRA234_CLK_SDMMC1&gt;,</div><div class='add'>+					  &lt;&amp;bpmp TEGRA234_CLK_PLLC4_MUXED&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;bpmp TEGRA234_CLK_PLLC4_MUXED&gt;,</div><div class='add'>+						 &lt;&amp;bpmp TEGRA234_CLK_PLLC4_VCO_DIV2&gt;;</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_SDMMC1&gt;;</div><div class='add'>+			reset-names = "sdhci";</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA234_MEMORY_CLIENT_SDMMCRA &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA234_MEMORY_CLIENT_SDMMCWA &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem", "write";</div><div class='add'>+			iommus = &lt;&amp;smmu_niso1 TEGRA234_SID_SDMMC1A&gt;;</div><div class='add'>+			pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";</div><div class='add'>+			pinctrl-0 = &lt;&amp;sdmmc1_3v3&gt;;</div><div class='add'>+			pinctrl-1 = &lt;&amp;sdmmc1_1v8&gt;;</div><div class='add'>+			nvidia,pad-autocal-pull-up-offset-3v3-timeout = &lt;0x07&gt;;</div><div class='add'>+			nvidia,pad-autocal-pull-down-offset-3v3-timeout = &lt;0x07&gt;;</div><div class='add'>+			nvidia,pad-autocal-pull-up-offset-1v8-timeout = &lt;0x06&gt;;</div><div class='add'>+			nvidia,pad-autocal-pull-down-offset-1v8-timeout = &lt;0x07&gt;;</div><div class='add'>+			nvidia,pad-autocal-pull-up-offset-sdr104 = &lt;0x00&gt;;</div><div class='add'>+			nvidia,pad-autocal-pull-down-offset-sdr104 = &lt;0x00&gt;;</div><div class='add'>+			nvidia,default-tap = &lt;14&gt;;</div><div class='add'>+			nvidia,default-trim = &lt;0x8&gt;;</div><div class='add'>+			sd-uhs-sdr25;</div><div class='add'>+			sd-uhs-sdr50;</div><div class='add'>+			sd-uhs-ddr50;</div><div class='add'>+			sd-uhs-sdr104;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmc@3460000 {</div><div class='add'>+			compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci";</div><div class='add'>+			reg = &lt;0x0 0x03460000 0x0 0x20000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_SDMMC4&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_SDMMC_LEGACY_TM&gt;;</div><div class='add'>+			clock-names = "sdhci", "tmclk";</div><div class='add'>+			assigned-clocks = &lt;&amp;bpmp TEGRA234_CLK_SDMMC4&gt;,</div><div class='add'>+					  &lt;&amp;bpmp TEGRA234_CLK_PLLC4&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;bpmp TEGRA234_CLK_PLLC4&gt;;</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_SDMMC4&gt;;</div><div class='add'>+			reset-names = "sdhci";</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem", "write";</div><div class='add'>+			iommus = &lt;&amp;smmu_niso1 TEGRA234_SID_SDMMC4&gt;;</div><div class='add'>+			nvidia,pad-autocal-pull-up-offset-hs400 = &lt;0x00&gt;;</div><div class='add'>+			nvidia,pad-autocal-pull-down-offset-hs400 = &lt;0x00&gt;;</div><div class='add'>+			nvidia,pad-autocal-pull-up-offset-1v8-timeout = &lt;0x0a&gt;;</div><div class='add'>+			nvidia,pad-autocal-pull-down-offset-1v8-timeout = &lt;0x0a&gt;;</div><div class='add'>+			nvidia,pad-autocal-pull-up-offset-3v3-timeout = &lt;0x0a&gt;;</div><div class='add'>+			nvidia,pad-autocal-pull-down-offset-3v3-timeout = &lt;0x0a&gt;;</div><div class='add'>+			nvidia,default-tap = &lt;0x8&gt;;</div><div class='add'>+			nvidia,default-trim = &lt;0x14&gt;;</div><div class='add'>+			nvidia,dqs-trim = &lt;40&gt;;</div><div class='add'>+			supports-cqe;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		hda@3510000 {</div><div class='add'>+			compatible = "nvidia,tegra234-hda";</div><div class='add'>+			reg = &lt;0x0 0x3510000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_AZA_BIT&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_AZA_2XBIT&gt;;</div><div class='add'>+			clock-names = "hda", "hda2codec_2x";</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_HDA&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_RESET_HDACODEC&gt;;</div><div class='add'>+			reset-names = "hda", "hda2codec_2x";</div><div class='add'>+			power-domains = &lt;&amp;bpmp TEGRA234_POWER_DOMAIN_DISP&gt;;</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA234_MEMORY_CLIENT_HDAR &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA234_MEMORY_CLIENT_HDAW &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem", "write";</div><div class='add'>+			iommus = &lt;&amp;smmu_niso0 TEGRA234_SID_HDA&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		xusb_padctl: padctl@3520000 {</div><div class='add'>+			compatible = "nvidia,tegra234-xusb-padctl";</div><div class='add'>+			reg = &lt;0x0 0x03520000 0x0 0x20000&gt;,</div><div class='add'>+			      &lt;0x0 0x03540000 0x0 0x10000&gt;;</div><div class='add'>+			reg-names = "padctl", "ao";</div><div class='add'>+			interrupts = &lt;GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_XUSB_PADCTL&gt;;</div><div class='add'>+			reset-names = "padctl";</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pads {</div><div class='add'>+				usb2 {</div><div class='add'>+					clocks = &lt;&amp;bpmp TEGRA234_CLK_USB2_TRK&gt;;</div><div class='add'>+					clock-names = "trk";</div><div class='add'>+</div><div class='add'>+					lanes {</div><div class='add'>+						usb2-0 {</div><div class='add'>+							nvidia,function = "xusb";</div><div class='add'>+							status = "disabled";</div><div class='add'>+							#phy-cells = &lt;0&gt;;</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						usb2-1 {</div><div class='add'>+							nvidia,function = "xusb";</div><div class='add'>+							status = "disabled";</div><div class='add'>+							#phy-cells = &lt;0&gt;;</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						usb2-2 {</div><div class='add'>+							nvidia,function = "xusb";</div><div class='add'>+							status = "disabled";</div><div class='add'>+							#phy-cells = &lt;0&gt;;</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						usb2-3 {</div><div class='add'>+							nvidia,function = "xusb";</div><div class='add'>+							status = "disabled";</div><div class='add'>+							#phy-cells = &lt;0&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usb3 {</div><div class='add'>+					lanes {</div><div class='add'>+						usb3-0 {</div><div class='add'>+							nvidia,function = "xusb";</div><div class='add'>+							status = "disabled";</div><div class='add'>+							#phy-cells = &lt;0&gt;;</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						usb3-1 {</div><div class='add'>+							nvidia,function = "xusb";</div><div class='add'>+							status = "disabled";</div><div class='add'>+							#phy-cells = &lt;0&gt;;</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						usb3-2 {</div><div class='add'>+							nvidia,function = "xusb";</div><div class='add'>+							status = "disabled";</div><div class='add'>+							#phy-cells = &lt;0&gt;;</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						usb3-3 {</div><div class='add'>+							nvidia,function = "xusb";</div><div class='add'>+							status = "disabled";</div><div class='add'>+							#phy-cells = &lt;0&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				usb2-0 {</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usb2-1 {</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usb2-2 {</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usb2-3 {</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usb3-0 {</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usb3-1 {</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usb3-2 {</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				usb3-3 {</div><div class='add'>+					status = "disabled";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb@3550000 {</div><div class='add'>+			compatible = "nvidia,tegra234-xudc";</div><div class='add'>+			reg = &lt;0x0 0x03550000 0x0 0x8000&gt;,</div><div class='add'>+			      &lt;0x0 0x03558000 0x0 0x8000&gt;;</div><div class='add'>+			reg-names = "base", "fpci";</div><div class='add'>+			interrupts = &lt;GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_XUSB_CORE_DEV&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_XUSB_CORE_SS&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_XUSB_SS&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_XUSB_FS&gt;;</div><div class='add'>+			clock-names = "dev", "ss", "ss_src", "fs_src";</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA234_MEMORY_CLIENT_XUSB_DEVR &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA234_MEMORY_CLIENT_XUSB_DEVW &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem", "write";</div><div class='add'>+			iommus = &lt;&amp;smmu_niso1 TEGRA234_SID_XUSB_DEV&gt;;</div><div class='add'>+			power-domains = &lt;&amp;bpmp TEGRA234_POWER_DOMAIN_XUSBB&gt;,</div><div class='add'>+					&lt;&amp;bpmp TEGRA234_POWER_DOMAIN_XUSBA&gt;;</div><div class='add'>+			power-domain-names = "dev", "ss";</div><div class='add'>+			nvidia,xusb-padctl = &lt;&amp;xusb_padctl&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb@3610000 {</div><div class='add'>+			compatible = "nvidia,tegra234-xusb";</div><div class='add'>+			reg = &lt;0x0 0x03610000 0x0 0x40000&gt;,</div><div class='add'>+			      &lt;0x0 0x03600000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0x03650000 0x0 0x10000&gt;;</div><div class='add'>+			reg-names = "hcd", "fpci", "bar2";</div><div class='add'>+</div><div class='add'>+			interrupts-extended = &lt;&amp;gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;pmc 76 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;pmc 77 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;pmc 78 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;pmc 79 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;pmc 80 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;pmc 81 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;pmc 82 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_XUSB_CORE_HOST&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_XUSB_FALCON&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_XUSB_CORE_SS&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_XUSB_SS&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_CLK_M&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_XUSB_FS&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_UTMIP_PLL&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_CLK_M&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_PLLE&gt;;</div><div class='add'>+			clock-names = "xusb_host", "xusb_falcon_src",</div><div class='add'>+				      "xusb_ss", "xusb_ss_src", "xusb_hs_src",</div><div class='add'>+				      "xusb_fs_src", "pll_u_480m", "clk_m",</div><div class='add'>+				      "pll_e";</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTR &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTW &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem", "write";</div><div class='add'>+			iommus = &lt;&amp;smmu_niso1 TEGRA234_SID_XUSB_HOST&gt;;</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;bpmp TEGRA234_POWER_DOMAIN_XUSBC&gt;,</div><div class='add'>+					&lt;&amp;bpmp TEGRA234_POWER_DOMAIN_XUSBA&gt;;</div><div class='add'>+			power-domain-names = "xusb_host", "xusb_ss";</div><div class='add'>+</div><div class='add'>+			nvidia,xusb-padctl = &lt;&amp;xusb_padctl&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		fuse@3810000 {</div><div class='add'>+			compatible = "nvidia,tegra234-efuse";</div><div class='add'>+			reg = &lt;0x0 0x03810000 0x0 0x10000&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_FUSE&gt;;</div><div class='add'>+			clock-names = "fuse";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		hte_lic: hardware-timestamp@3aa0000 {</div><div class='add'>+			compatible = "nvidia,tegra234-gte-lic";</div><div class='add'>+			reg = &lt;0x0 0x3aa0000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			nvidia,int-threshold = &lt;1&gt;;</div><div class='add'>+			#timestamp-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		hsp_top0: hsp@3c00000 {</div><div class='add'>+			compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";</div><div class='add'>+			reg = &lt;0x0 0x03c00000 0x0 0xa0000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "doorbell", "shared0", "shared1", "shared2",</div><div class='add'>+					  "shared3", "shared4", "shared5", "shared6",</div><div class='add'>+					  "shared7";</div><div class='add'>+			#mbox-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		p2u_hsio_0: phy@3e00000 {</div><div class='add'>+			compatible = "nvidia,tegra234-p2u";</div><div class='add'>+			reg = &lt;0x0 0x03e00000 0x0 0x10000&gt;;</div><div class='add'>+			reg-names = "ctl";</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		p2u_hsio_1: phy@3e10000 {</div><div class='add'>+			compatible = "nvidia,tegra234-p2u";</div><div class='add'>+			reg = &lt;0x0 0x03e10000 0x0 0x10000&gt;;</div><div class='add'>+			reg-names = "ctl";</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		p2u_hsio_2: phy@3e20000 {</div><div class='add'>+			compatible = "nvidia,tegra234-p2u";</div><div class='add'>+			reg = &lt;0x0 0x03e20000 0x0 0x10000&gt;;</div><div class='add'>+			reg-names = "ctl";</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		p2u_hsio_3: phy@3e30000 {</div><div class='add'>+			compatible = "nvidia,tegra234-p2u";</div><div class='add'>+			reg = &lt;0x0 0x03e30000 0x0 0x10000&gt;;</div><div class='add'>+			reg-names = "ctl";</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		p2u_hsio_4: phy@3e40000 {</div><div class='add'>+			compatible = "nvidia,tegra234-p2u";</div><div class='add'>+			reg = &lt;0x0 0x03e40000 0x0 0x10000&gt;;</div><div class='add'>+			reg-names = "ctl";</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		p2u_hsio_5: phy@3e50000 {</div><div class='add'>+			compatible = "nvidia,tegra234-p2u";</div><div class='add'>+			reg = &lt;0x0 0x03e50000 0x0 0x10000&gt;;</div><div class='add'>+			reg-names = "ctl";</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		p2u_hsio_6: phy@3e60000 {</div><div class='add'>+			compatible = "nvidia,tegra234-p2u";</div><div class='add'>+			reg = &lt;0x0 0x03e60000 0x0 0x10000&gt;;</div><div class='add'>+			reg-names = "ctl";</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		p2u_hsio_7: phy@3e70000 {</div><div class='add'>+			compatible = "nvidia,tegra234-p2u";</div><div class='add'>+			reg = &lt;0x0 0x03e70000 0x0 0x10000&gt;;</div><div class='add'>+			reg-names = "ctl";</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		p2u_nvhs_0: phy@3e90000 {</div><div class='add'>+			compatible = "nvidia,tegra234-p2u";</div><div class='add'>+			reg = &lt;0x0 0x03e90000 0x0 0x10000&gt;;</div><div class='add'>+			reg-names = "ctl";</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		p2u_nvhs_1: phy@3ea0000 {</div><div class='add'>+			compatible = "nvidia,tegra234-p2u";</div><div class='add'>+			reg = &lt;0x0 0x03ea0000 0x0 0x10000&gt;;</div><div class='add'>+			reg-names = "ctl";</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		p2u_nvhs_2: phy@3eb0000 {</div><div class='add'>+			compatible = "nvidia,tegra234-p2u";</div><div class='add'>+			reg = &lt;0x0 0x03eb0000 0x0 0x10000&gt;;</div><div class='add'>+			reg-names = "ctl";</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		p2u_nvhs_3: phy@3ec0000 {</div><div class='add'>+			compatible = "nvidia,tegra234-p2u";</div><div class='add'>+			reg = &lt;0x0 0x03ec0000 0x0 0x10000&gt;;</div><div class='add'>+			reg-names = "ctl";</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		p2u_nvhs_4: phy@3ed0000 {</div><div class='add'>+			compatible = "nvidia,tegra234-p2u";</div><div class='add'>+			reg = &lt;0x0 0x03ed0000 0x0 0x10000&gt;;</div><div class='add'>+			reg-names = "ctl";</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		p2u_nvhs_5: phy@3ee0000 {</div><div class='add'>+			compatible = "nvidia,tegra234-p2u";</div><div class='add'>+			reg = &lt;0x0 0x03ee0000 0x0 0x10000&gt;;</div><div class='add'>+			reg-names = "ctl";</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		p2u_nvhs_6: phy@3ef0000 {</div><div class='add'>+			compatible = "nvidia,tegra234-p2u";</div><div class='add'>+			reg = &lt;0x0 0x03ef0000 0x0 0x10000&gt;;</div><div class='add'>+			reg-names = "ctl";</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		p2u_nvhs_7: phy@3f00000 {</div><div class='add'>+			compatible = "nvidia,tegra234-p2u";</div><div class='add'>+			reg = &lt;0x0 0x03f00000 0x0 0x10000&gt;;</div><div class='add'>+			reg-names = "ctl";</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		p2u_gbe_0: phy@3f20000 {</div><div class='add'>+			compatible = "nvidia,tegra234-p2u";</div><div class='add'>+			reg = &lt;0x0 0x03f20000 0x0 0x10000&gt;;</div><div class='add'>+			reg-names = "ctl";</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		p2u_gbe_1: phy@3f30000 {</div><div class='add'>+			compatible = "nvidia,tegra234-p2u";</div><div class='add'>+			reg = &lt;0x0 0x03f30000 0x0 0x10000&gt;;</div><div class='add'>+			reg-names = "ctl";</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		p2u_gbe_2: phy@3f40000 {</div><div class='add'>+			compatible = "nvidia,tegra234-p2u";</div><div class='add'>+			reg = &lt;0x0 0x03f40000 0x0 0x10000&gt;;</div><div class='add'>+			reg-names = "ctl";</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		p2u_gbe_3: phy@3f50000 {</div><div class='add'>+			compatible = "nvidia,tegra234-p2u";</div><div class='add'>+			reg = &lt;0x0 0x03f50000 0x0 0x10000&gt;;</div><div class='add'>+			reg-names = "ctl";</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		p2u_gbe_4: phy@3f60000 {</div><div class='add'>+			compatible = "nvidia,tegra234-p2u";</div><div class='add'>+			reg = &lt;0x0 0x03f60000 0x0 0x10000&gt;;</div><div class='add'>+			reg-names = "ctl";</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		p2u_gbe_5: phy@3f70000 {</div><div class='add'>+			compatible = "nvidia,tegra234-p2u";</div><div class='add'>+			reg = &lt;0x0 0x03f70000 0x0 0x10000&gt;;</div><div class='add'>+			reg-names = "ctl";</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		p2u_gbe_6: phy@3f80000 {</div><div class='add'>+			compatible = "nvidia,tegra234-p2u";</div><div class='add'>+			reg = &lt;0x0 0x03f80000 0x0 0x10000&gt;;</div><div class='add'>+			reg-names = "ctl";</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		p2u_gbe_7: phy@3f90000 {</div><div class='add'>+			compatible = "nvidia,tegra234-p2u";</div><div class='add'>+			reg = &lt;0x0 0x03f90000 0x0 0x10000&gt;;</div><div class='add'>+			reg-names = "ctl";</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ethernet@6800000 {</div><div class='add'>+			compatible = "nvidia,tegra234-mgbe";</div><div class='add'>+			reg = &lt;0x0 0x06800000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0x06810000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0x068a0000 0x0 0x10000&gt;;</div><div class='add'>+			reg-names = "hypervisor", "mac", "xpcs";</div><div class='add'>+			interrupts = &lt;GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "common";</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_MGBE0_APP&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_MGBE0_MAC&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_MGBE0_PTP_REF&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_MGBE0_RX_INPUT&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_MGBE0_TX&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_MGBE0_EEE_PCS&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_MGBE0_RX_PCS_M&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_MGBE0_RX_PCS&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_MGBE0_TX_PCS&gt;;</div><div class='add'>+			clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",</div><div class='add'>+				      "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",</div><div class='add'>+				      "rx-pcs", "tx-pcs";</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_MGBE0_MAC&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_RESET_MGBE0_PCS&gt;;</div><div class='add'>+			reset-names = "mac", "pcs";</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA234_MEMORY_CLIENT_MGBEARD &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA234_MEMORY_CLIENT_MGBEAWR &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem", "write";</div><div class='add'>+			iommus = &lt;&amp;smmu_niso0 TEGRA234_SID_MGBE&gt;;</div><div class='add'>+			power-domains = &lt;&amp;bpmp TEGRA234_POWER_DOMAIN_MGBEB&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			snps,axi-config = &lt;&amp;mgbe0_axi_setup&gt;;</div><div class='add'>+</div><div class='add'>+			mgbe0_axi_setup: stmmac-axi-config {</div><div class='add'>+				snps,blen = &lt;256 128 64 32&gt;;</div><div class='add'>+				snps,rd_osr_lmt = &lt;63&gt;;</div><div class='add'>+				snps,wr_osr_lmt = &lt;63&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ethernet@6900000 {</div><div class='add'>+			compatible = "nvidia,tegra234-mgbe";</div><div class='add'>+			reg = &lt;0x0 0x06900000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0x06910000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0x069a0000 0x0 0x10000&gt;;</div><div class='add'>+			reg-names = "hypervisor", "mac", "xpcs";</div><div class='add'>+			interrupts = &lt;GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "common";</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_MGBE1_APP&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_MGBE1_MAC&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_MGBE1_MAC_DIVIDER&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_MGBE1_PTP_REF&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_MGBE1_RX_INPUT_M&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_MGBE1_RX_INPUT&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_MGBE1_TX&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_MGBE1_EEE_PCS&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_MGBE1_RX_PCS_INPUT&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_MGBE1_RX_PCS_M&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_MGBE1_RX_PCS&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_MGBE1_TX_PCS&gt;;</div><div class='add'>+			clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",</div><div class='add'>+				      "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",</div><div class='add'>+				      "rx-pcs", "tx-pcs";</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_MGBE1_MAC&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_RESET_MGBE1_PCS&gt;;</div><div class='add'>+			reset-names = "mac", "pcs";</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA234_MEMORY_CLIENT_MGBEBRD &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA234_MEMORY_CLIENT_MGBEBWR &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem", "write";</div><div class='add'>+			iommus = &lt;&amp;smmu_niso0 TEGRA234_SID_MGBE_VF1&gt;;</div><div class='add'>+			power-domains = &lt;&amp;bpmp TEGRA234_POWER_DOMAIN_MGBEC&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			snps,axi-config = &lt;&amp;mgbe1_axi_setup&gt;;</div><div class='add'>+</div><div class='add'>+			mgbe1_axi_setup: stmmac-axi-config {</div><div class='add'>+				snps,blen = &lt;256 128 64 32&gt;;</div><div class='add'>+				snps,rd_osr_lmt = &lt;63&gt;;</div><div class='add'>+				snps,wr_osr_lmt = &lt;63&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ethernet@6a00000 {</div><div class='add'>+			compatible = "nvidia,tegra234-mgbe";</div><div class='add'>+			reg = &lt;0x0 0x06a00000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0x06a10000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0x06aa0000 0x0 0x10000&gt;;</div><div class='add'>+			reg-names = "hypervisor", "mac", "xpcs";</div><div class='add'>+			interrupts = &lt;GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "common";</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_MGBE2_APP&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_MGBE2_MAC&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_MGBE2_MAC_DIVIDER&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_MGBE2_PTP_REF&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_MGBE2_RX_INPUT_M&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_MGBE2_RX_INPUT&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_MGBE2_TX&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_MGBE2_EEE_PCS&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_MGBE2_RX_PCS_INPUT&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_MGBE2_RX_PCS_M&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_MGBE2_RX_PCS&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_MGBE2_TX_PCS&gt;;</div><div class='add'>+			clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",</div><div class='add'>+				      "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",</div><div class='add'>+				      "rx-pcs", "tx-pcs";</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_MGBE2_MAC&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_RESET_MGBE2_PCS&gt;;</div><div class='add'>+			reset-names = "mac", "pcs";</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA234_MEMORY_CLIENT_MGBECRD &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA234_MEMORY_CLIENT_MGBECWR &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem", "write";</div><div class='add'>+			iommus = &lt;&amp;smmu_niso0 TEGRA234_SID_MGBE_VF2&gt;;</div><div class='add'>+			power-domains = &lt;&amp;bpmp TEGRA234_POWER_DOMAIN_MGBED&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			snps,axi-config = &lt;&amp;mgbe2_axi_setup&gt;;</div><div class='add'>+</div><div class='add'>+			mgbe2_axi_setup: stmmac-axi-config {</div><div class='add'>+				snps,blen = &lt;256 128 64 32&gt;;</div><div class='add'>+				snps,rd_osr_lmt = &lt;63&gt;;</div><div class='add'>+				snps,wr_osr_lmt = &lt;63&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ethernet@6b00000 {</div><div class='add'>+			compatible = "nvidia,tegra234-mgbe";</div><div class='add'>+			reg = &lt;0x0 0x06b00000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0x06b10000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0x06ba0000 0x0 0x10000&gt;;</div><div class='add'>+			reg-names = "hypervisor", "mac", "xpcs";</div><div class='add'>+			interrupts = &lt;GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "common";</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_MGBE3_APP&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_MGBE3_MAC&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_MGBE3_MAC_DIVIDER&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_MGBE3_PTP_REF&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_MGBE3_RX_INPUT_M&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_MGBE3_RX_INPUT&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_MGBE3_TX&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_MGBE3_EEE_PCS&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_MGBE3_RX_PCS_INPUT&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_MGBE3_RX_PCS_M&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_MGBE3_RX_PCS&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_MGBE3_TX_PCS&gt;;</div><div class='add'>+			clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",</div><div class='add'>+				      "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",</div><div class='add'>+				      "rx-pcs", "tx-pcs";</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_MGBE3_MAC&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_RESET_MGBE3_PCS&gt;;</div><div class='add'>+			reset-names = "mac", "pcs";</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA234_MEMORY_CLIENT_MGBEDRD &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA234_MEMORY_CLIENT_MGBEDWR &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem", "write";</div><div class='add'>+			iommus = &lt;&amp;smmu_niso0 TEGRA234_SID_MGBE_VF3&gt;;</div><div class='add'>+			power-domains = &lt;&amp;bpmp TEGRA234_POWER_DOMAIN_MGBED&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smmu_niso1: iommu@8000000 {</div><div class='add'>+			compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";</div><div class='add'>+			reg = &lt;0x0 0x8000000 0x0 0x1000000&gt;,</div><div class='add'>+			      &lt;0x0 0x7000000 0x0 0x1000000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			stream-match-mask = &lt;0x7f80&gt;;</div><div class='add'>+			#global-interrupts = &lt;2&gt;;</div><div class='add'>+			#iommu-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			nvidia,memory-controller = &lt;&amp;mc&gt;;</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sce-fabric@b600000 {</div><div class='add'>+			compatible = "nvidia,tegra234-sce-fabric";</div><div class='add'>+			reg = &lt;0x0 0xb600000 0x0 0x40000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rce-fabric@be00000 {</div><div class='add'>+			compatible = "nvidia,tegra234-rce-fabric";</div><div class='add'>+			reg = &lt;0x0 0xbe00000 0x0 0x40000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		hsp_aon: hsp@c150000 {</div><div class='add'>+			compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";</div><div class='add'>+			reg = &lt;0x0 0x0c150000 0x0 0x90000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			/*</div><div class='add'>+			 * Shared interrupt 0 is routed only to AON/SPE, so</div><div class='add'>+			 * we only have 4 shared interrupts for the CCPLEX.</div><div class='add'>+			 */</div><div class='add'>+			interrupt-names = "shared1", "shared2", "shared3", "shared4";</div><div class='add'>+			#mbox-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		hte_aon: hardware-timestamp@c1e0000 {</div><div class='add'>+			compatible = "nvidia,tegra234-gte-aon";</div><div class='add'>+			reg = &lt;0x0 0xc1e0000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			nvidia,int-threshold = &lt;1&gt;;</div><div class='add'>+			nvidia,gpio-controller = &lt;&amp;gpio_aon&gt;;</div><div class='add'>+			#timestamp-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gen2_i2c: i2c@c240000 {</div><div class='add'>+			compatible = "nvidia,tegra194-i2c";</div><div class='add'>+			reg = &lt;0x0 0xc240000 0x0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+			clock-frequency = &lt;100000&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_I2C2&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			clock-names = "div-clk", "parent";</div><div class='add'>+			assigned-clocks = &lt;&amp;bpmp TEGRA234_CLK_I2C2&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;bpmp TEGRA234_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_I2C2&gt;;</div><div class='add'>+			reset-names = "i2c";</div><div class='add'>+			dmas = &lt;&amp;gpcdma 22&gt;, &lt;&amp;gpcdma 22&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gen8_i2c: i2c@c250000 {</div><div class='add'>+			compatible = "nvidia,tegra194-i2c";</div><div class='add'>+			reg = &lt;0x0 0xc250000 0x0 0x100&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+			clock-frequency = &lt;400000&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_I2C8&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			clock-names = "div-clk", "parent";</div><div class='add'>+			assigned-clocks = &lt;&amp;bpmp TEGRA234_CLK_I2C8&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;bpmp TEGRA234_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_I2C8&gt;;</div><div class='add'>+			reset-names = "i2c";</div><div class='add'>+			dmas = &lt;&amp;gpcdma 0&gt;, &lt;&amp;gpcdma 0&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spi@c260000 {</div><div class='add'>+			compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";</div><div class='add'>+			reg = &lt;0x0 0x0c260000 0x0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_SPI2&gt;;</div><div class='add'>+			clock-names = "spi";</div><div class='add'>+			iommus = &lt;&amp;smmu_niso0 TEGRA234_SID_GPCDMA&gt;;</div><div class='add'>+			assigned-clocks = &lt;&amp;bpmp TEGRA234_CLK_SPI2&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;bpmp TEGRA234_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_SPI2&gt;;</div><div class='add'>+			reset-names = "spi";</div><div class='add'>+			dmas = &lt;&amp;gpcdma 16&gt;, &lt;&amp;gpcdma 16&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+			dma-coherent;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rtc@c2a0000 {</div><div class='add'>+			compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc";</div><div class='add'>+			reg = &lt;0x0 0x0c2a0000 0x0 0x10000&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;pmc&gt;;</div><div class='add'>+			interrupts = &lt;73 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_CLK_32K&gt;;</div><div class='add'>+			clock-names = "rtc";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpio_aon: gpio@c2f0000 {</div><div class='add'>+			compatible = "nvidia,tegra234-gpio-aon";</div><div class='add'>+			reg-names = "security", "gpio";</div><div class='add'>+			reg = &lt;0x0 0x0c2f0000 0x0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0x0c2f1000 0x0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			gpio-ranges = &lt;&amp;pinmux_aon 0 0 32&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pinmux_aon: pinmux@c300000 {</div><div class='add'>+			compatible = "nvidia,tegra234-pinmux-aon";</div><div class='add'>+			reg = &lt;0x0 0xc300000 0x0 0x4000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pwm4: pwm@c340000 {</div><div class='add'>+			compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";</div><div class='add'>+			reg = &lt;0x0 0xc340000 0x0 0x10000&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_PWM4&gt;;</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_PWM4&gt;;</div><div class='add'>+			reset-names = "pwm";</div><div class='add'>+			status = "disabled";</div><div class='add'>+			#pwm-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmc: pmc@c360000 {</div><div class='add'>+			compatible = "nvidia,tegra234-pmc";</div><div class='add'>+			reg = &lt;0x0 0x0c360000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0x0c370000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0x0c380000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0x0c390000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0x0c3a0000 0x0 0x10000&gt;;</div><div class='add'>+			reg-names = "pmc", "wake", "aotag", "scratch", "misc";</div><div class='add'>+</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+</div><div class='add'>+			sdmmc1_1v8: sdmmc1-1v8 {</div><div class='add'>+				pins = "sdmmc1-hv";</div><div class='add'>+				power-source = &lt;TEGRA_IO_PAD_VOLTAGE_1V8&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sdmmc1_3v3: sdmmc1-3v3 {</div><div class='add'>+				pins = "sdmmc1-hv";</div><div class='add'>+				power-source = &lt;TEGRA_IO_PAD_VOLTAGE_3V3&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sdmmc3_1v8: sdmmc3-1v8 {</div><div class='add'>+				pins = "sdmmc3-hv";</div><div class='add'>+				power-source = &lt;TEGRA_IO_PAD_VOLTAGE_1V8&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sdmmc3_3v3: sdmmc3-3v3 {</div><div class='add'>+				pins = "sdmmc3-hv";</div><div class='add'>+				power-source = &lt;TEGRA_IO_PAD_VOLTAGE_3V3&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aon-fabric@c600000 {</div><div class='add'>+			compatible = "nvidia,tegra234-aon-fabric";</div><div class='add'>+			reg = &lt;0x0 0xc600000 0x0 0x40000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		bpmp-fabric@d600000 {</div><div class='add'>+			compatible = "nvidia,tegra234-bpmp-fabric";</div><div class='add'>+			reg = &lt;0x0 0xd600000 0x0 0x40000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dce-fabric@de00000 {</div><div class='add'>+			compatible = "nvidia,tegra234-dce-fabric";</div><div class='add'>+			reg = &lt;0x0 0xde00000 0x0 0x40000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ccplex@e000000 {</div><div class='add'>+			compatible = "nvidia,tegra234-ccplex-cluster";</div><div class='add'>+			reg = &lt;0x0 0x0e000000 0x0 0x5ffff&gt;;</div><div class='add'>+			nvidia,bpmp = &lt;&amp;bpmp&gt;;</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@f400000 {</div><div class='add'>+			compatible = "arm,gic-v3";</div><div class='add'>+			reg = &lt;0x0 0x0f400000 0x0 0x010000&gt;, /* GICD */</div><div class='add'>+			      &lt;0x0 0x0f440000 0x0 0x200000&gt;; /* GICR */</div><div class='add'>+			interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='add'>+</div><div class='add'>+			#redistributor-regions = &lt;1&gt;;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smmu_iso: iommu@10000000 {</div><div class='add'>+			compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";</div><div class='add'>+			reg = &lt;0x0 0x10000000 0x0 0x1000000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			stream-match-mask = &lt;0x7f80&gt;;</div><div class='add'>+			#global-interrupts = &lt;1&gt;;</div><div class='add'>+			#iommu-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			nvidia,memory-controller = &lt;&amp;mc&gt;;</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smmu_niso0: iommu@12000000 {</div><div class='add'>+			compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";</div><div class='add'>+			reg = &lt;0x0 0x12000000 0x0 0x1000000&gt;,</div><div class='add'>+			      &lt;0x0 0x11000000 0x0 0x1000000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			stream-match-mask = &lt;0x7f80&gt;;</div><div class='add'>+			#global-interrupts = &lt;2&gt;;</div><div class='add'>+			#iommu-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			nvidia,memory-controller = &lt;&amp;mc&gt;;</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cbb-fabric@13a00000 {</div><div class='add'>+			compatible = "nvidia,tegra234-cbb-fabric";</div><div class='add'>+			reg = &lt;0x0 0x13a00000 0x0 0x400000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		host1x@13e00000 {</div><div class='add'>+			compatible = "nvidia,tegra234-host1x";</div><div class='add'>+			reg = &lt;0x0 0x13e00000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0x13e10000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0x13e40000 0x0 0x10000&gt;;</div><div class='add'>+			reg-names = "common", "hypervisor", "vm";</div><div class='add'>+			interrupts = &lt;GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4",</div><div class='add'>+					  "syncpt5", "syncpt6", "syncpt7", "host1x";</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_HOST1X&gt;;</div><div class='add'>+			clock-names = "host1x";</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges = &lt;0x0 0x14800000 0x0 0x14800000 0x0 0x02000000&gt;;</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem";</div><div class='add'>+			iommus = &lt;&amp;smmu_niso1 TEGRA234_SID_HOST1X&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+</div><div class='add'>+			/* Context isolation domains */</div><div class='add'>+			iommu-map = &lt;0 &amp;smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1&gt;,</div><div class='add'>+				    &lt;1 &amp;smmu_niso0 TEGRA234_SID_HOST1X_CTX1 1&gt;,</div><div class='add'>+				    &lt;2 &amp;smmu_niso0 TEGRA234_SID_HOST1X_CTX2 1&gt;,</div><div class='add'>+				    &lt;3 &amp;smmu_niso0 TEGRA234_SID_HOST1X_CTX3 1&gt;,</div><div class='add'>+				    &lt;4 &amp;smmu_niso0 TEGRA234_SID_HOST1X_CTX4 1&gt;,</div><div class='add'>+				    &lt;5 &amp;smmu_niso0 TEGRA234_SID_HOST1X_CTX5 1&gt;,</div><div class='add'>+				    &lt;6 &amp;smmu_niso0 TEGRA234_SID_HOST1X_CTX6 1&gt;,</div><div class='add'>+				    &lt;7 &amp;smmu_niso0 TEGRA234_SID_HOST1X_CTX7 1&gt;,</div><div class='add'>+				    &lt;8 &amp;smmu_niso1 TEGRA234_SID_HOST1X_CTX0 1&gt;,</div><div class='add'>+				    &lt;9 &amp;smmu_niso1 TEGRA234_SID_HOST1X_CTX1 1&gt;,</div><div class='add'>+				    &lt;10 &amp;smmu_niso1 TEGRA234_SID_HOST1X_CTX2 1&gt;,</div><div class='add'>+				    &lt;11 &amp;smmu_niso1 TEGRA234_SID_HOST1X_CTX3 1&gt;,</div><div class='add'>+				    &lt;12 &amp;smmu_niso1 TEGRA234_SID_HOST1X_CTX4 1&gt;,</div><div class='add'>+				    &lt;13 &amp;smmu_niso1 TEGRA234_SID_HOST1X_CTX5 1&gt;,</div><div class='add'>+				    &lt;14 &amp;smmu_niso1 TEGRA234_SID_HOST1X_CTX6 1&gt;,</div><div class='add'>+				    &lt;15 &amp;smmu_niso1 TEGRA234_SID_HOST1X_CTX7 1&gt;;</div><div class='add'>+</div><div class='add'>+			vic@15340000 {</div><div class='add'>+				compatible = "nvidia,tegra234-vic";</div><div class='add'>+				reg = &lt;0x0 0x15340000 0x0 0x00040000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;bpmp TEGRA234_CLK_VIC&gt;;</div><div class='add'>+				clock-names = "vic";</div><div class='add'>+				resets = &lt;&amp;bpmp TEGRA234_RESET_VIC&gt;;</div><div class='add'>+				reset-names = "vic";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;bpmp TEGRA234_POWER_DOMAIN_VIC&gt;;</div><div class='add'>+				interconnects = &lt;&amp;mc TEGRA234_MEMORY_CLIENT_VICSRD &amp;emc&gt;,</div><div class='add'>+						&lt;&amp;mc TEGRA234_MEMORY_CLIENT_VICSWR &amp;emc&gt;;</div><div class='add'>+				interconnect-names = "dma-mem", "write";</div><div class='add'>+				iommus = &lt;&amp;smmu_niso1 TEGRA234_SID_VIC&gt;;</div><div class='add'>+				dma-coherent;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			nvdec@15480000 {</div><div class='add'>+				compatible = "nvidia,tegra234-nvdec";</div><div class='add'>+				reg = &lt;0x0 0x15480000 0x0 0x00040000&gt;;</div><div class='add'>+				clocks = &lt;&amp;bpmp TEGRA234_CLK_NVDEC&gt;,</div><div class='add'>+					 &lt;&amp;bpmp TEGRA234_CLK_FUSE&gt;,</div><div class='add'>+					 &lt;&amp;bpmp TEGRA234_CLK_TSEC_PKA&gt;;</div><div class='add'>+				clock-names = "nvdec", "fuse", "tsec_pka";</div><div class='add'>+				resets = &lt;&amp;bpmp TEGRA234_RESET_NVDEC&gt;;</div><div class='add'>+				reset-names = "nvdec";</div><div class='add'>+				power-domains = &lt;&amp;bpmp TEGRA234_POWER_DOMAIN_NVDEC&gt;;</div><div class='add'>+				interconnects = &lt;&amp;mc TEGRA234_MEMORY_CLIENT_NVDECSRD &amp;emc&gt;,</div><div class='add'>+						&lt;&amp;mc TEGRA234_MEMORY_CLIENT_NVDECSWR &amp;emc&gt;;</div><div class='add'>+				interconnect-names = "dma-mem", "write";</div><div class='add'>+				iommus = &lt;&amp;smmu_niso1 TEGRA234_SID_NVDEC&gt;;</div><div class='add'>+				dma-coherent;</div><div class='add'>+</div><div class='add'>+				nvidia,memory-controller = &lt;&amp;mc&gt;;</div><div class='add'>+</div><div class='add'>+				/*</div><div class='add'>+				 * Placeholder values that firmware needs to update with the real</div><div class='add'>+				 * offsets parsed from the microcode headers.</div><div class='add'>+				 */</div><div class='add'>+				nvidia,bl-manifest-offset = &lt;0&gt;;</div><div class='add'>+				nvidia,bl-data-offset = &lt;0&gt;;</div><div class='add'>+				nvidia,bl-code-offset = &lt;0&gt;;</div><div class='add'>+				nvidia,os-manifest-offset = &lt;0&gt;;</div><div class='add'>+				nvidia,os-data-offset = &lt;0&gt;;</div><div class='add'>+				nvidia,os-code-offset = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				/*</div><div class='add'>+				 * Firmware needs to set this to "okay" once the above values have</div><div class='add'>+				 * been updated.</div><div class='add'>+				 */</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			crypto@15820000 {</div><div class='add'>+				compatible = "nvidia,tegra234-se-aes";</div><div class='add'>+				reg = &lt;0x00 0x15820000 0x00 0x10000&gt;;</div><div class='add'>+				clocks = &lt;&amp;bpmp TEGRA234_CLK_SE&gt;;</div><div class='add'>+				iommus = &lt;&amp;smmu_niso1 TEGRA234_SID_SES_SE1&gt;;</div><div class='add'>+				dma-coherent;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			crypto@15840000 {</div><div class='add'>+				compatible = "nvidia,tegra234-se-hash";</div><div class='add'>+				reg = &lt;0x00 0x15840000 0x00 0x10000&gt;;</div><div class='add'>+				clocks = &lt;&amp;bpmp TEGRA234_CLK_SE&gt;;</div><div class='add'>+				iommus = &lt;&amp;smmu_niso1 TEGRA234_SID_SES_SE2&gt;;</div><div class='add'>+				dma-coherent;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie@140a0000 {</div><div class='add'>+			compatible = "nvidia,tegra234-pcie";</div><div class='add'>+			power-domains = &lt;&amp;bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA&gt;;</div><div class='add'>+			reg = &lt;0x00 0x140a0000 0x0 0x00020000&gt;, /* appl registers (128K)      */</div><div class='add'>+			      &lt;0x00 0x2a000000 0x0 0x00040000&gt;, /* configuration space (256K) */</div><div class='add'>+			      &lt;0x00 0x2a040000 0x0 0x00040000&gt;, /* iATU_DMA reg space (256K)  */</div><div class='add'>+			      &lt;0x00 0x2a080000 0x0 0x00040000&gt;, /* DBI reg space (256K)       */</div><div class='add'>+			      &lt;0x35 0x30000000 0x0 0x10000000&gt;; /* ECAM (256MB)               */</div><div class='add'>+			reg-names = "appl", "config", "atu_dma", "dbi", "ecam";</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			num-lanes = &lt;4&gt;;</div><div class='add'>+			num-viewport = &lt;8&gt;;</div><div class='add'>+			linux,pci-domain = &lt;8&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_PEX2_C8_CORE&gt;;</div><div class='add'>+			clock-names = "core";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_PEX2_CORE_8_APB&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_RESET_PEX2_CORE_8&gt;;</div><div class='add'>+			reset-names = "apb", "core";</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH&gt;, /* controller interrupt */</div><div class='add'>+				     &lt;GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH&gt;; /* MSI interrupt */</div><div class='add'>+			interrupt-names = "intr", "msi";</div><div class='add'>+</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 0 &amp;gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			nvidia,bpmp = &lt;&amp;bpmp 8&gt;;</div><div class='add'>+</div><div class='add'>+			nvidia,aspm-cmrt-us = &lt;60&gt;;</div><div class='add'>+			nvidia,aspm-pwr-on-t-us = &lt;20&gt;;</div><div class='add'>+			nvidia,aspm-l0s-entrance-latency-us = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+			bus-range = &lt;0x0 0xff&gt;;</div><div class='add'>+</div><div class='add'>+			ranges = &lt;0x43000000 0x32 0x40000000 0x32 0x40000000 0x2 0xe8000000&gt;, /* prefetchable memory (11904 MB) */</div><div class='add'>+				 &lt;0x02000000 0x0  0x40000000 0x35 0x28000000 0x0 0x08000000&gt;, /* non-prefetchable memory (128 MB) */</div><div class='add'>+				 &lt;0x01000000 0x0  0x2a100000 0x00 0x2a100000 0x0 0x00100000&gt;; /* downstream I/O (1 MB) */</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA234_MEMORY_CLIENT_PCIE8AR &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA234_MEMORY_CLIENT_PCIE8AW &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem", "write";</div><div class='add'>+			iommu-map = &lt;0x0 &amp;smmu_niso1 TEGRA234_SID_PCIE8 0x1000&gt;;</div><div class='add'>+			iommu-map-mask = &lt;0x0&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie@140c0000 {</div><div class='add'>+			compatible = "nvidia,tegra234-pcie";</div><div class='add'>+			power-domains = &lt;&amp;bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB&gt;;</div><div class='add'>+			reg = &lt;0x00 0x140c0000 0x0 0x00020000&gt;, /* appl registers (128K)      */</div><div class='add'>+			      &lt;0x00 0x2c000000 0x0 0x00040000&gt;, /* configuration space (256K) */</div><div class='add'>+			      &lt;0x00 0x2c040000 0x0 0x00040000&gt;, /* iATU_DMA reg space (256K)  */</div><div class='add'>+			      &lt;0x00 0x2c080000 0x0 0x00040000&gt;, /* DBI reg space (256K)       */</div><div class='add'>+			      &lt;0x38 0x30000000 0x0 0x10000000&gt;; /* ECAM (256MB)               */</div><div class='add'>+			reg-names = "appl", "config", "atu_dma", "dbi", "ecam";</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			num-lanes = &lt;4&gt;;</div><div class='add'>+			num-viewport = &lt;8&gt;;</div><div class='add'>+			linux,pci-domain = &lt;9&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_PEX2_C9_CORE&gt;;</div><div class='add'>+			clock-names = "core";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_PEX2_CORE_9_APB&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_RESET_PEX2_CORE_9&gt;;</div><div class='add'>+			reset-names = "apb", "core";</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH&gt;, /* controller interrupt */</div><div class='add'>+				     &lt;GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH&gt;; /* MSI interrupt */</div><div class='add'>+			interrupt-names = "intr", "msi";</div><div class='add'>+</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 0 &amp;gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			nvidia,bpmp = &lt;&amp;bpmp 9&gt;;</div><div class='add'>+</div><div class='add'>+			nvidia,aspm-cmrt-us = &lt;60&gt;;</div><div class='add'>+			nvidia,aspm-pwr-on-t-us = &lt;20&gt;;</div><div class='add'>+			nvidia,aspm-l0s-entrance-latency-us = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+			bus-range = &lt;0x0 0xff&gt;;</div><div class='add'>+</div><div class='add'>+			ranges = &lt;0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xc0000000&gt;, /* prefetchable memory (11264 MB) */</div><div class='add'>+				 &lt;0x02000000 0x0  0x40000000 0x38 0x28000000 0x0 0x08000000&gt;, /* non-prefetchable memory (128 MB) */</div><div class='add'>+				 &lt;0x01000000 0x0  0x2c100000 0x00 0x2c100000 0x0 0x00100000&gt;; /* downstream I/O (1 MB) */</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA234_MEMORY_CLIENT_PCIE9AR &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA234_MEMORY_CLIENT_PCIE9AW &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem", "write";</div><div class='add'>+			iommu-map = &lt;0x0 &amp;smmu_niso0 TEGRA234_SID_PCIE9 0x1000&gt;;</div><div class='add'>+			iommu-map-mask = &lt;0x0&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie@140e0000 {</div><div class='add'>+			compatible = "nvidia,tegra234-pcie";</div><div class='add'>+			power-domains = &lt;&amp;bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC&gt;;</div><div class='add'>+			reg = &lt;0x00 0x140e0000 0x0 0x00020000&gt;, /* appl registers (128K)      */</div><div class='add'>+			      &lt;0x00 0x2e000000 0x0 0x00040000&gt;, /* configuration space (256K) */</div><div class='add'>+			      &lt;0x00 0x2e040000 0x0 0x00040000&gt;, /* iATU_DMA reg space (256K)  */</div><div class='add'>+			      &lt;0x00 0x2e080000 0x0 0x00040000&gt;, /* DBI reg space (256K)       */</div><div class='add'>+			      &lt;0x3b 0x30000000 0x0 0x10000000&gt;; /* ECAM (256MB)               */</div><div class='add'>+			reg-names = "appl", "config", "atu_dma", "dbi", "ecam";</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			num-lanes = &lt;4&gt;;</div><div class='add'>+			num-viewport = &lt;8&gt;;</div><div class='add'>+			linux,pci-domain = &lt;10&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_PEX2_C10_CORE&gt;;</div><div class='add'>+			clock-names = "core";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_PEX2_CORE_10_APB&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_RESET_PEX2_CORE_10&gt;;</div><div class='add'>+			reset-names = "apb", "core";</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH&gt;, /* controller interrupt */</div><div class='add'>+				     &lt;GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH&gt;; /* MSI interrupt */</div><div class='add'>+			interrupt-names = "intr", "msi";</div><div class='add'>+</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 0 &amp;gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			nvidia,bpmp = &lt;&amp;bpmp 10&gt;;</div><div class='add'>+</div><div class='add'>+			nvidia,aspm-cmrt-us = &lt;60&gt;;</div><div class='add'>+			nvidia,aspm-pwr-on-t-us = &lt;20&gt;;</div><div class='add'>+			nvidia,aspm-l0s-entrance-latency-us = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+			bus-range = &lt;0x0 0xff&gt;;</div><div class='add'>+</div><div class='add'>+			ranges = &lt;0x43000000 0x38 0x40000000 0x38 0x40000000 0x2 0xe8000000&gt;, /* prefetchable memory (11904 MB) */</div><div class='add'>+				 &lt;0x02000000 0x0  0x40000000 0x3b 0x28000000 0x0 0x08000000&gt;, /* non-prefetchable memory (128 MB) */</div><div class='add'>+				 &lt;0x01000000 0x0  0x2e100000 0x00 0x2e100000 0x0 0x00100000&gt;; /* downstream I/O (1 MB) */</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA234_MEMORY_CLIENT_PCIE10AR &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA234_MEMORY_CLIENT_PCIE10AW &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem", "write";</div><div class='add'>+			iommu-map = &lt;0x0 &amp;smmu_niso1 TEGRA234_SID_PCIE10 0x1000&gt;;</div><div class='add'>+			iommu-map-mask = &lt;0x0&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie-ep@140e0000 {</div><div class='add'>+			compatible = "nvidia,tegra234-pcie-ep";</div><div class='add'>+			power-domains = &lt;&amp;bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC&gt;;</div><div class='add'>+			reg = &lt;0x00 0x140e0000 0x0 0x00020000&gt;, /* appl registers (128K)      */</div><div class='add'>+			      &lt;0x00 0x2e040000 0x0 0x00040000&gt;, /* iATU_DMA reg space (256K)  */</div><div class='add'>+			      &lt;0x00 0x2e080000 0x0 0x00040000&gt;, /* DBI space (256K)           */</div><div class='add'>+			      &lt;0x38 0x40000000 0x3 0x00000000&gt;; /* Address Space (12G)        */</div><div class='add'>+			reg-names = "appl", "atu_dma", "dbi", "addr_space";</div><div class='add'>+</div><div class='add'>+			num-lanes = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_PEX2_C10_CORE&gt;;</div><div class='add'>+			clock-names = "core";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_PEX2_CORE_10_APB&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_RESET_PEX2_CORE_10&gt;;</div><div class='add'>+			reset-names = "apb", "core";</div><div class='add'>+</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;pex_rst_c10_in_state&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH&gt;;	/* controller interrupt */</div><div class='add'>+			interrupt-names = "intr";</div><div class='add'>+</div><div class='add'>+			nvidia,bpmp = &lt;&amp;bpmp 10&gt;;</div><div class='add'>+</div><div class='add'>+			nvidia,enable-ext-refclk;</div><div class='add'>+			nvidia,aspm-cmrt-us = &lt;60&gt;;</div><div class='add'>+			nvidia,aspm-pwr-on-t-us = &lt;20&gt;;</div><div class='add'>+			nvidia,aspm-l0s-entrance-latency-us = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA234_MEMORY_CLIENT_PCIE10AR &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA234_MEMORY_CLIENT_PCIE10AW &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem", "write";</div><div class='add'>+			iommu-map = &lt;0x0 &amp;smmu_niso1 TEGRA234_SID_PCIE10 0x1000&gt;;</div><div class='add'>+			iommu-map-mask = &lt;0x0&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie@14100000 {</div><div class='add'>+			compatible = "nvidia,tegra234-pcie";</div><div class='add'>+			power-domains = &lt;&amp;bpmp TEGRA234_POWER_DOMAIN_PCIEX1A&gt;;</div><div class='add'>+			reg = &lt;0x00 0x14100000 0x0 0x00020000&gt;, /* appl registers (128K)      */</div><div class='add'>+			      &lt;0x00 0x30000000 0x0 0x00040000&gt;, /* configuration space (256K) */</div><div class='add'>+			      &lt;0x00 0x30040000 0x0 0x00040000&gt;, /* iATU_DMA reg space (256K)  */</div><div class='add'>+			      &lt;0x00 0x30080000 0x0 0x00040000&gt;, /* DBI reg space (256K)       */</div><div class='add'>+			      &lt;0x20 0xb0000000 0x0 0x10000000&gt;; /* ECAM (256MB)               */</div><div class='add'>+			reg-names = "appl", "config", "atu_dma", "dbi", "ecam";</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			num-lanes = &lt;1&gt;;</div><div class='add'>+			num-viewport = &lt;8&gt;;</div><div class='add'>+			linux,pci-domain = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_PEX0_C1_CORE&gt;;</div><div class='add'>+			clock-names = "core";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_PEX0_CORE_1_APB&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_RESET_PEX0_CORE_1&gt;;</div><div class='add'>+			reset-names = "apb", "core";</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH&gt;, /* controller interrupt */</div><div class='add'>+				     &lt;GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH&gt;; /* MSI interrupt */</div><div class='add'>+			interrupt-names = "intr", "msi";</div><div class='add'>+</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 0 &amp;gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			nvidia,bpmp = &lt;&amp;bpmp 1&gt;;</div><div class='add'>+</div><div class='add'>+			nvidia,aspm-cmrt-us = &lt;60&gt;;</div><div class='add'>+			nvidia,aspm-pwr-on-t-us = &lt;20&gt;;</div><div class='add'>+			nvidia,aspm-l0s-entrance-latency-us = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+			bus-range = &lt;0x0 0xff&gt;;</div><div class='add'>+</div><div class='add'>+			ranges = &lt;0x43000000 0x20 0x80000000 0x20 0x80000000 0x0 0x28000000&gt;, /* prefetchable memory (640 MB) */</div><div class='add'>+				 &lt;0x02000000 0x0  0x40000000 0x20 0xa8000000 0x0 0x08000000&gt;, /* non-prefetchable memory (128 MB) */</div><div class='add'>+				 &lt;0x01000000 0x0  0x30100000 0x00 0x30100000 0x0 0x00100000&gt;; /* downstream I/O (1 MB) */</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA234_MEMORY_CLIENT_PCIE1R &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA234_MEMORY_CLIENT_PCIE1W &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem", "write";</div><div class='add'>+			iommu-map = &lt;0x0 &amp;smmu_niso1 TEGRA234_SID_PCIE1 0x1000&gt;;</div><div class='add'>+			iommu-map-mask = &lt;0x0&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie@14120000 {</div><div class='add'>+			compatible = "nvidia,tegra234-pcie";</div><div class='add'>+			power-domains = &lt;&amp;bpmp TEGRA234_POWER_DOMAIN_PCIEX1A&gt;;</div><div class='add'>+			reg = &lt;0x00 0x14120000 0x0 0x00020000&gt;, /* appl registers (128K)      */</div><div class='add'>+			      &lt;0x00 0x32000000 0x0 0x00040000&gt;, /* configuration space (256K) */</div><div class='add'>+			      &lt;0x00 0x32040000 0x0 0x00040000&gt;, /* iATU_DMA reg space (256K)  */</div><div class='add'>+			      &lt;0x00 0x32080000 0x0 0x00040000&gt;, /* DBI reg space (256K)       */</div><div class='add'>+			      &lt;0x20 0xf0000000 0x0 0x10000000&gt;; /* ECAM (256MB)               */</div><div class='add'>+			reg-names = "appl", "config", "atu_dma", "dbi", "ecam";</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			num-lanes = &lt;1&gt;;</div><div class='add'>+			num-viewport = &lt;8&gt;;</div><div class='add'>+			linux,pci-domain = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_PEX0_C2_CORE&gt;;</div><div class='add'>+			clock-names = "core";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_PEX0_CORE_2_APB&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_RESET_PEX0_CORE_2&gt;;</div><div class='add'>+			reset-names = "apb", "core";</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH&gt;, /* controller interrupt */</div><div class='add'>+				     &lt;GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH&gt;; /* MSI interrupt */</div><div class='add'>+			interrupt-names = "intr", "msi";</div><div class='add'>+</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 0 &amp;gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			nvidia,bpmp = &lt;&amp;bpmp 2&gt;;</div><div class='add'>+</div><div class='add'>+			nvidia,aspm-cmrt-us = &lt;60&gt;;</div><div class='add'>+			nvidia,aspm-pwr-on-t-us = &lt;20&gt;;</div><div class='add'>+			nvidia,aspm-l0s-entrance-latency-us = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+			bus-range = &lt;0x0 0xff&gt;;</div><div class='add'>+</div><div class='add'>+			ranges = &lt;0x43000000 0x20 0xc0000000 0x20 0xc0000000 0x0 0x28000000&gt;, /* prefetchable memory (640 MB) */</div><div class='add'>+				 &lt;0x02000000 0x0  0x40000000 0x20 0xe8000000 0x0 0x08000000&gt;, /* non-prefetchable memory (128 MB) */</div><div class='add'>+				 &lt;0x01000000 0x0  0x32100000 0x00 0x32100000 0x0 0x00100000&gt;; /* downstream I/O (1 MB) */</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA234_MEMORY_CLIENT_PCIE2AR &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA234_MEMORY_CLIENT_PCIE2AW &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem", "write";</div><div class='add'>+			iommu-map = &lt;0x0 &amp;smmu_niso1 TEGRA234_SID_PCIE2 0x1000&gt;;</div><div class='add'>+			iommu-map-mask = &lt;0x0&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie@14140000 {</div><div class='add'>+			compatible = "nvidia,tegra234-pcie";</div><div class='add'>+			power-domains = &lt;&amp;bpmp TEGRA234_POWER_DOMAIN_PCIEX1A&gt;;</div><div class='add'>+			reg = &lt;0x00 0x14140000 0x0 0x00020000&gt;, /* appl registers (128K)      */</div><div class='add'>+			      &lt;0x00 0x34000000 0x0 0x00040000&gt;, /* configuration space (256K) */</div><div class='add'>+			      &lt;0x00 0x34040000 0x0 0x00040000&gt;, /* iATU_DMA reg space (256K)  */</div><div class='add'>+			      &lt;0x00 0x34080000 0x0 0x00040000&gt;, /* DBI reg space (256K)       */</div><div class='add'>+			      &lt;0x21 0x30000000 0x0 0x10000000&gt;; /* ECAM (256MB)               */</div><div class='add'>+			reg-names = "appl", "config", "atu_dma", "dbi", "ecam";</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			num-lanes = &lt;1&gt;;</div><div class='add'>+			num-viewport = &lt;8&gt;;</div><div class='add'>+			linux,pci-domain = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_PEX0_C3_CORE&gt;;</div><div class='add'>+			clock-names = "core";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_PEX0_CORE_3_APB&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_RESET_PEX0_CORE_3&gt;;</div><div class='add'>+			reset-names = "apb", "core";</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH&gt;, /* controller interrupt */</div><div class='add'>+				     &lt;GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH&gt;; /* MSI interrupt */</div><div class='add'>+			interrupt-names = "intr", "msi";</div><div class='add'>+</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 0 &amp;gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			nvidia,bpmp = &lt;&amp;bpmp 3&gt;;</div><div class='add'>+</div><div class='add'>+			nvidia,aspm-cmrt-us = &lt;60&gt;;</div><div class='add'>+			nvidia,aspm-pwr-on-t-us = &lt;20&gt;;</div><div class='add'>+			nvidia,aspm-l0s-entrance-latency-us = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+			bus-range = &lt;0x0 0xff&gt;;</div><div class='add'>+</div><div class='add'>+			ranges = &lt;0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000&gt;, /* prefetchable memory (640 MB) */</div><div class='add'>+				 &lt;0x02000000 0x0  0x40000000 0x21 0x28000000 0x0 0x08000000&gt;, /* non-prefetchable memory (128 MB) */</div><div class='add'>+				 &lt;0x01000000 0x0  0x34100000 0x00 0x34100000 0x0 0x00100000&gt;; /* downstream I/O (1 MB) */</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA234_MEMORY_CLIENT_PCIE3R &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA234_MEMORY_CLIENT_PCIE3W &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem", "write";</div><div class='add'>+			iommu-map = &lt;0x0 &amp;smmu_niso1 TEGRA234_SID_PCIE3 0x1000&gt;;</div><div class='add'>+			iommu-map-mask = &lt;0x0&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie@14160000 {</div><div class='add'>+			compatible = "nvidia,tegra234-pcie";</div><div class='add'>+			power-domains = &lt;&amp;bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB&gt;;</div><div class='add'>+			reg = &lt;0x00 0x14160000 0x0 0x00020000&gt;, /* appl registers (128K)      */</div><div class='add'>+			      &lt;0x00 0x36000000 0x0 0x00040000&gt;, /* configuration space (256K) */</div><div class='add'>+			      &lt;0x00 0x36040000 0x0 0x00040000&gt;, /* iATU_DMA reg space (256K)  */</div><div class='add'>+			      &lt;0x00 0x36080000 0x0 0x00040000&gt;, /* DBI reg space (256K)       */</div><div class='add'>+			      &lt;0x24 0x30000000 0x0 0x10000000&gt;; /* ECAM (256MB)               */</div><div class='add'>+			reg-names = "appl", "config", "atu_dma", "dbi", "ecam";</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			num-lanes = &lt;4&gt;;</div><div class='add'>+			num-viewport = &lt;8&gt;;</div><div class='add'>+			linux,pci-domain = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_PEX0_C4_CORE&gt;;</div><div class='add'>+			clock-names = "core";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_PEX0_CORE_4_APB&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_RESET_PEX0_CORE_4&gt;;</div><div class='add'>+			reset-names = "apb", "core";</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH&gt;, /* controller interrupt */</div><div class='add'>+				     &lt;GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH&gt;; /* MSI interrupt */</div><div class='add'>+			interrupt-names = "intr", "msi";</div><div class='add'>+</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 0 &amp;gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			nvidia,bpmp = &lt;&amp;bpmp 4&gt;;</div><div class='add'>+</div><div class='add'>+			nvidia,aspm-cmrt-us = &lt;60&gt;;</div><div class='add'>+			nvidia,aspm-pwr-on-t-us = &lt;20&gt;;</div><div class='add'>+			nvidia,aspm-l0s-entrance-latency-us = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+			bus-range = &lt;0x0 0xff&gt;;</div><div class='add'>+</div><div class='add'>+			ranges = &lt;0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000&gt;, /* prefetchable memory (11904 MB) */</div><div class='add'>+				 &lt;0x02000000 0x0  0x40000000 0x24 0x28000000 0x0 0x08000000&gt;, /* non-prefetchable memory (128 MB) */</div><div class='add'>+				 &lt;0x01000000 0x0  0x36100000 0x00 0x36100000 0x0 0x00100000&gt;; /* downstream I/O (1 MB) */</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA234_MEMORY_CLIENT_PCIE4R &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA234_MEMORY_CLIENT_PCIE4W &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem", "write";</div><div class='add'>+			iommu-map = &lt;0x0 &amp;smmu_niso0 TEGRA234_SID_PCIE4 0x1000&gt;;</div><div class='add'>+			iommu-map-mask = &lt;0x0&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie-ep@14160000 {</div><div class='add'>+			compatible = "nvidia,tegra234-pcie-ep";</div><div class='add'>+			power-domains = &lt;&amp;bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB&gt;;</div><div class='add'>+			reg = &lt;0x00 0x14160000 0x0 0x00020000     /* appl registers (128K)      */</div><div class='add'>+				0x00 0x36040000 0x0 0x00040000    /* iATU_DMA reg space (256K)  */</div><div class='add'>+				0x00 0x36080000 0x0 0x00040000    /* DBI space (256K)           */</div><div class='add'>+				0x21 0x40000000 0x3 0x00000000&gt;;  /* Address Space (12G)        */</div><div class='add'>+			reg-names = "appl", "atu_dma", "dbi", "addr_space";</div><div class='add'>+			num-lanes = &lt;4&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_PEX0_C4_CORE&gt;;</div><div class='add'>+			clock-names = "core";</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_PEX0_CORE_4_APB&gt;,</div><div class='add'>+			       &lt;&amp;bpmp TEGRA234_RESET_PEX0_CORE_4&gt;;</div><div class='add'>+			reset-names = "apb", "core";</div><div class='add'>+</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;pex_rst_c4_in_state&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH&gt;;  /* controller interrupt */</div><div class='add'>+			interrupt-names = "intr";</div><div class='add'>+			nvidia,bpmp = &lt;&amp;bpmp 4&gt;;</div><div class='add'>+			nvidia,enable-ext-refclk;</div><div class='add'>+			nvidia,aspm-cmrt-us = &lt;60&gt;;</div><div class='add'>+			nvidia,aspm-pwr-on-t-us = &lt;20&gt;;</div><div class='add'>+			nvidia,aspm-l0s-entrance-latency-us = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA234_MEMORY_CLIENT_PCIE4R &amp;emc&gt;,</div><div class='add'>+				      &lt;&amp;mc TEGRA234_MEMORY_CLIENT_PCIE4W &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem", "write";</div><div class='add'>+			iommus = &lt;&amp;smmu_niso0 TEGRA234_SID_PCIE4&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie@14180000 {</div><div class='add'>+			compatible = "nvidia,tegra234-pcie";</div><div class='add'>+			power-domains = &lt;&amp;bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA&gt;;</div><div class='add'>+			reg = &lt;0x00 0x14180000 0x0 0x00020000&gt;, /* appl registers (128K)      */</div><div class='add'>+			      &lt;0x00 0x38000000 0x0 0x00040000&gt;, /* configuration space (256K) */</div><div class='add'>+			      &lt;0x00 0x38040000 0x0 0x00040000&gt;, /* iATU_DMA reg space (256K)  */</div><div class='add'>+			      &lt;0x00 0x38080000 0x0 0x00040000&gt;, /* DBI reg space (256K)       */</div><div class='add'>+			      &lt;0x27 0x30000000 0x0 0x10000000&gt;; /* ECAM (256MB)               */</div><div class='add'>+			reg-names = "appl", "config", "atu_dma", "dbi", "ecam";</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			num-lanes = &lt;4&gt;;</div><div class='add'>+			num-viewport = &lt;8&gt;;</div><div class='add'>+			linux,pci-domain = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_PEX0_C0_CORE&gt;;</div><div class='add'>+			clock-names = "core";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_PEX0_CORE_0_APB&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_RESET_PEX0_CORE_0&gt;;</div><div class='add'>+			reset-names = "apb", "core";</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH&gt;, /* controller interrupt */</div><div class='add'>+				     &lt;GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH&gt;; /* MSI interrupt */</div><div class='add'>+			interrupt-names = "intr", "msi";</div><div class='add'>+</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 0 &amp;gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			nvidia,bpmp = &lt;&amp;bpmp 0&gt;;</div><div class='add'>+</div><div class='add'>+			nvidia,aspm-cmrt-us = &lt;60&gt;;</div><div class='add'>+			nvidia,aspm-pwr-on-t-us = &lt;20&gt;;</div><div class='add'>+			nvidia,aspm-l0s-entrance-latency-us = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+			bus-range = &lt;0x0 0xff&gt;;</div><div class='add'>+</div><div class='add'>+			ranges = &lt;0x43000000 0x24 0x40000000 0x24 0x40000000 0x2 0xe8000000&gt;, /* prefetchable memory (11904 MB) */</div><div class='add'>+				 &lt;0x02000000 0x0  0x40000000 0x27 0x28000000 0x0 0x08000000&gt;, /* non-prefetchable memory (128 MB) */</div><div class='add'>+				 &lt;0x01000000 0x0  0x38100000 0x00 0x38100000 0x0 0x00100000&gt;; /* downstream I/O (1 MB) */</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA234_MEMORY_CLIENT_PCIE0R &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA234_MEMORY_CLIENT_PCIE0W &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem", "write";</div><div class='add'>+			iommu-map = &lt;0x0 &amp;smmu_niso0 TEGRA234_SID_PCIE0 0x1000&gt;;</div><div class='add'>+			iommu-map-mask = &lt;0x0&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie@141a0000 {</div><div class='add'>+			compatible = "nvidia,tegra234-pcie";</div><div class='add'>+			power-domains = &lt;&amp;bpmp TEGRA234_POWER_DOMAIN_PCIEX8A&gt;;</div><div class='add'>+			reg = &lt;0x00 0x141a0000 0x0 0x00020000&gt;, /* appl registers (128K)      */</div><div class='add'>+			      &lt;0x00 0x3a000000 0x0 0x00040000&gt;, /* configuration space (256K) */</div><div class='add'>+			      &lt;0x00 0x3a040000 0x0 0x00040000&gt;, /* iATU_DMA reg space (256K)  */</div><div class='add'>+			      &lt;0x00 0x3a080000 0x0 0x00040000&gt;, /* DBI reg space (256K)       */</div><div class='add'>+			      &lt;0x2b 0x30000000 0x0 0x10000000&gt;; /* ECAM (256MB)               */</div><div class='add'>+			reg-names = "appl", "config", "atu_dma", "dbi", "ecam";</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			num-lanes = &lt;8&gt;;</div><div class='add'>+			num-viewport = &lt;8&gt;;</div><div class='add'>+			linux,pci-domain = &lt;5&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_PEX1_C5_CORE&gt;;</div><div class='add'>+			clock-names = "core";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_PEX1_CORE_5_APB&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_RESET_PEX1_CORE_5&gt;;</div><div class='add'>+			reset-names = "apb", "core";</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH&gt;, /* controller interrupt */</div><div class='add'>+				     &lt;GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH&gt;; /* MSI interrupt */</div><div class='add'>+			interrupt-names = "intr", "msi";</div><div class='add'>+</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 0 &amp;gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			nvidia,bpmp = &lt;&amp;bpmp 5&gt;;</div><div class='add'>+</div><div class='add'>+			nvidia,aspm-cmrt-us = &lt;60&gt;;</div><div class='add'>+			nvidia,aspm-pwr-on-t-us = &lt;20&gt;;</div><div class='add'>+			nvidia,aspm-l0s-entrance-latency-us = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+			bus-range = &lt;0x0 0xff&gt;;</div><div class='add'>+</div><div class='add'>+			ranges = &lt;0x43000000 0x28 0x00000000 0x28 0x00000000 0x3 0x28000000&gt;, /* prefetchable memory (12928 MB) */</div><div class='add'>+				 &lt;0x02000000 0x0  0x40000000 0x2b 0x28000000 0x0 0x08000000&gt;, /* non-prefetchable memory (128 MB) */</div><div class='add'>+				 &lt;0x01000000 0x0  0x3a100000 0x00 0x3a100000 0x0 0x00100000&gt;; /* downstream I/O (1 MB) */</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA234_MEMORY_CLIENT_PCIE5R &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA234_MEMORY_CLIENT_PCIE5W &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem", "write";</div><div class='add'>+			iommu-map = &lt;0x0 &amp;smmu_niso0 TEGRA234_SID_PCIE5 0x1000&gt;;</div><div class='add'>+			iommu-map-mask = &lt;0x0&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie-ep@141a0000 {</div><div class='add'>+			compatible = "nvidia,tegra234-pcie-ep";</div><div class='add'>+			power-domains = &lt;&amp;bpmp TEGRA234_POWER_DOMAIN_PCIEX8A&gt;;</div><div class='add'>+			reg = &lt;0x00 0x141a0000 0x0 0x00020000&gt;, /* appl registers (128K)      */</div><div class='add'>+			      &lt;0x00 0x3a040000 0x0 0x00040000&gt;, /* iATU_DMA reg space (256K)  */</div><div class='add'>+			      &lt;0x00 0x3a080000 0x0 0x00040000&gt;, /* DBI reg space (256K)       */</div><div class='add'>+			      &lt;0x27 0x40000000 0x4 0x00000000&gt;; /* Address Space (16G)        */</div><div class='add'>+			reg-names = "appl", "atu_dma", "dbi", "addr_space";</div><div class='add'>+</div><div class='add'>+			num-lanes = &lt;8&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_PEX1_C5_CORE&gt;;</div><div class='add'>+			clock-names = "core";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_PEX1_CORE_5_APB&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_RESET_PEX1_CORE_5&gt;;</div><div class='add'>+			reset-names = "apb", "core";</div><div class='add'>+</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;pex_rst_c5_in_state&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH&gt;;	/* controller interrupt */</div><div class='add'>+			interrupt-names = "intr";</div><div class='add'>+</div><div class='add'>+			nvidia,bpmp = &lt;&amp;bpmp 5&gt;;</div><div class='add'>+</div><div class='add'>+			nvidia,enable-ext-refclk;</div><div class='add'>+			nvidia,aspm-cmrt-us = &lt;60&gt;;</div><div class='add'>+			nvidia,aspm-pwr-on-t-us = &lt;20&gt;;</div><div class='add'>+			nvidia,aspm-l0s-entrance-latency-us = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA234_MEMORY_CLIENT_PCIE5R &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA234_MEMORY_CLIENT_PCIE5W &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem", "write";</div><div class='add'>+			iommu-map = &lt;0x0 &amp;smmu_niso0 TEGRA234_SID_PCIE5 0x1000&gt;;</div><div class='add'>+			iommu-map-mask = &lt;0x0&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie@141c0000 {</div><div class='add'>+			compatible = "nvidia,tegra234-pcie";</div><div class='add'>+			power-domains = &lt;&amp;bpmp TEGRA234_POWER_DOMAIN_PCIEX4A&gt;;</div><div class='add'>+			reg = &lt;0x00 0x141c0000 0x0 0x00020000&gt;, /* appl registers (128K)      */</div><div class='add'>+			      &lt;0x00 0x3c000000 0x0 0x00040000&gt;, /* configuration space (256K) */</div><div class='add'>+			      &lt;0x00 0x3c040000 0x0 0x00040000&gt;, /* iATU_DMA reg space (256K)  */</div><div class='add'>+			      &lt;0x00 0x3c080000 0x0 0x00040000&gt;, /* DBI reg space (256K)       */</div><div class='add'>+			      &lt;0x2e 0x30000000 0x0 0x10000000&gt;; /* ECAM (256MB)               */</div><div class='add'>+			reg-names = "appl", "config", "atu_dma", "dbi", "ecam";</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			num-lanes = &lt;4&gt;;</div><div class='add'>+			num-viewport = &lt;8&gt;;</div><div class='add'>+			linux,pci-domain = &lt;6&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_PEX1_C6_CORE&gt;;</div><div class='add'>+			clock-names = "core";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_PEX1_CORE_6_APB&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_RESET_PEX1_CORE_6&gt;;</div><div class='add'>+			reset-names = "apb", "core";</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH&gt;, /* controller interrupt */</div><div class='add'>+				     &lt;GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH&gt;; /* MSI interrupt */</div><div class='add'>+			interrupt-names = "intr", "msi";</div><div class='add'>+</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 0 &amp;gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			nvidia,bpmp = &lt;&amp;bpmp 6&gt;;</div><div class='add'>+</div><div class='add'>+			nvidia,aspm-cmrt-us = &lt;60&gt;;</div><div class='add'>+			nvidia,aspm-pwr-on-t-us = &lt;20&gt;;</div><div class='add'>+			nvidia,aspm-l0s-entrance-latency-us = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+			bus-range = &lt;0x0 0xff&gt;;</div><div class='add'>+</div><div class='add'>+			ranges = &lt;0x43000000 0x2b 0x40000000 0x2b 0x40000000 0x2 0xe8000000&gt;, /* prefetchable memory (11904 MB) */</div><div class='add'>+				 &lt;0x02000000 0x0  0x40000000 0x2e 0x28000000 0x0 0x08000000&gt;, /* non-prefetchable memory (128 MB) */</div><div class='add'>+				 &lt;0x01000000 0x0  0x3c100000 0x00 0x3c100000 0x0 0x00100000&gt;; /* downstream I/O (1 MB) */</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA234_MEMORY_CLIENT_PCIE6AR &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA234_MEMORY_CLIENT_PCIE6AW &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem", "write";</div><div class='add'>+			iommu-map = &lt;0x0 &amp;smmu_niso0 TEGRA234_SID_PCIE6 0x1000&gt;;</div><div class='add'>+			iommu-map-mask = &lt;0x0&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie-ep@141c0000 {</div><div class='add'>+			compatible = "nvidia,tegra234-pcie-ep";</div><div class='add'>+			power-domains = &lt;&amp;bpmp TEGRA234_POWER_DOMAIN_PCIEX4A&gt;;</div><div class='add'>+			reg = &lt;0x00 0x141c0000 0x0 0x00020000&gt;, /* appl registers (128K)      */</div><div class='add'>+			      &lt;0x00 0x3c040000 0x0 0x00040000&gt;, /* iATU_DMA reg space (256K)  */</div><div class='add'>+			      &lt;0x00 0x3c080000 0x0 0x00040000&gt;, /* DBI space (256K)           */</div><div class='add'>+			      &lt;0x2b 0x40000000 0x3 0x00000000&gt;; /* Address Space (12G)        */</div><div class='add'>+			reg-names = "appl", "atu_dma", "dbi", "addr_space";</div><div class='add'>+</div><div class='add'>+			num-lanes = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_PEX1_C6_CORE&gt;;</div><div class='add'>+			clock-names = "core";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_PEX1_CORE_6_APB&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_RESET_PEX1_CORE_6&gt;;</div><div class='add'>+			reset-names = "apb", "core";</div><div class='add'>+</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;pex_rst_c6_in_state&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH&gt;;	/* controller interrupt */</div><div class='add'>+			interrupt-names = "intr";</div><div class='add'>+</div><div class='add'>+			nvidia,bpmp = &lt;&amp;bpmp 6&gt;;</div><div class='add'>+</div><div class='add'>+			nvidia,enable-ext-refclk;</div><div class='add'>+			nvidia,aspm-cmrt-us = &lt;60&gt;;</div><div class='add'>+			nvidia,aspm-pwr-on-t-us = &lt;20&gt;;</div><div class='add'>+			nvidia,aspm-l0s-entrance-latency-us = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA234_MEMORY_CLIENT_PCIE6AR &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA234_MEMORY_CLIENT_PCIE6AW &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem", "write";</div><div class='add'>+			iommu-map = &lt;0x0 &amp;smmu_niso0 TEGRA234_SID_PCIE6 0x1000&gt;;</div><div class='add'>+			iommu-map-mask = &lt;0x0&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie@141e0000 {</div><div class='add'>+			compatible = "nvidia,tegra234-pcie";</div><div class='add'>+			power-domains = &lt;&amp;bpmp TEGRA234_POWER_DOMAIN_PCIEX8B&gt;;</div><div class='add'>+			reg = &lt;0x00 0x141e0000 0x0 0x00020000&gt;, /* appl registers (128K)      */</div><div class='add'>+			      &lt;0x00 0x3e000000 0x0 0x00040000&gt;, /* configuration space (256K) */</div><div class='add'>+			      &lt;0x00 0x3e040000 0x0 0x00040000&gt;, /* iATU_DMA reg space (256K)  */</div><div class='add'>+			      &lt;0x00 0x3e080000 0x0 0x00040000&gt;, /* DBI reg space (256K)       */</div><div class='add'>+			      &lt;0x32 0x30000000 0x0 0x10000000&gt;; /* ECAM (256MB)               */</div><div class='add'>+			reg-names = "appl", "config", "atu_dma", "dbi", "ecam";</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			num-lanes = &lt;8&gt;;</div><div class='add'>+			num-viewport = &lt;8&gt;;</div><div class='add'>+			linux,pci-domain = &lt;7&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_PEX2_C7_CORE&gt;;</div><div class='add'>+			clock-names = "core";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_PEX2_CORE_7_APB&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_RESET_PEX2_CORE_7&gt;;</div><div class='add'>+			reset-names = "apb", "core";</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH&gt;, /* controller interrupt */</div><div class='add'>+				     &lt;GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH&gt;; /* MSI interrupt */</div><div class='add'>+			interrupt-names = "intr", "msi";</div><div class='add'>+</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 0 &amp;gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			nvidia,bpmp = &lt;&amp;bpmp 7&gt;;</div><div class='add'>+</div><div class='add'>+			nvidia,aspm-cmrt-us = &lt;60&gt;;</div><div class='add'>+			nvidia,aspm-pwr-on-t-us = &lt;20&gt;;</div><div class='add'>+			nvidia,aspm-l0s-entrance-latency-us = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+			bus-range = &lt;0x0 0xff&gt;;</div><div class='add'>+</div><div class='add'>+			ranges = &lt;0x43000000 0x30 0x00000000 0x30 0x00000000 0x2 0x28000000&gt;, /* prefetchable memory (8832 MB) */</div><div class='add'>+				 &lt;0x02000000 0x0  0x40000000 0x32 0x28000000 0x0 0x08000000&gt;, /* non-prefetchable memory (128 MB) */</div><div class='add'>+				 &lt;0x01000000 0x0  0x3e100000 0x00 0x3e100000 0x0 0x00100000&gt;; /* downstream I/O (1 MB) */</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA234_MEMORY_CLIENT_PCIE7AR &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA234_MEMORY_CLIENT_PCIE7AW &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem", "write";</div><div class='add'>+			iommu-map = &lt;0x0 &amp;smmu_niso1 TEGRA234_SID_PCIE7 0x1000&gt;;</div><div class='add'>+			iommu-map-mask = &lt;0x0&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie-ep@141e0000 {</div><div class='add'>+			compatible = "nvidia,tegra234-pcie-ep";</div><div class='add'>+			power-domains = &lt;&amp;bpmp TEGRA234_POWER_DOMAIN_PCIEX8B&gt;;</div><div class='add'>+			reg = &lt;0x00 0x141e0000 0x0 0x00020000&gt;, /* appl registers (128K)      */</div><div class='add'>+			      &lt;0x00 0x3e040000 0x0 0x00040000&gt;, /* iATU_DMA reg space (256K)  */</div><div class='add'>+			      &lt;0x00 0x3e080000 0x0 0x00040000&gt;, /* DBI space (256K)           */</div><div class='add'>+			      &lt;0x2e 0x40000000 0x4 0x00000000&gt;; /* Address Space (16G)        */</div><div class='add'>+			reg-names = "appl", "atu_dma", "dbi", "addr_space";</div><div class='add'>+</div><div class='add'>+			num-lanes = &lt;8&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA234_CLK_PEX2_C7_CORE&gt;;</div><div class='add'>+			clock-names = "core";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA234_RESET_PEX2_CORE_7_APB&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA234_RESET_PEX2_CORE_7&gt;;</div><div class='add'>+			reset-names = "apb", "core";</div><div class='add'>+</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;pex_rst_c7_in_state&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH&gt;;	/* controller interrupt */</div><div class='add'>+			interrupt-names = "intr";</div><div class='add'>+</div><div class='add'>+			nvidia,bpmp = &lt;&amp;bpmp 7&gt;;</div><div class='add'>+</div><div class='add'>+			nvidia,enable-ext-refclk;</div><div class='add'>+			nvidia,aspm-cmrt-us = &lt;60&gt;;</div><div class='add'>+			nvidia,aspm-pwr-on-t-us = &lt;20&gt;;</div><div class='add'>+			nvidia,aspm-l0s-entrance-latency-us = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA234_MEMORY_CLIENT_PCIE7AR &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA234_MEMORY_CLIENT_PCIE7AW &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem", "write";</div><div class='add'>+			iommu-map = &lt;0x0 &amp;smmu_niso1 TEGRA234_SID_PCIE7 0x1000&gt;;</div><div class='add'>+			iommu-map-mask = &lt;0x0&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sram@40000000 {</div><div class='add'>+		compatible = "nvidia,tegra234-sysram", "mmio-sram";</div><div class='add'>+		reg = &lt;0x0 0x40000000 0x0 0x80000&gt;;</div><div class='add'>+</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges = &lt;0x0 0x0 0x40000000 0x80000&gt;;</div><div class='add'>+</div><div class='add'>+		no-memory-wc;</div><div class='add'>+</div><div class='add'>+		cpu_bpmp_tx: sram@70000 {</div><div class='add'>+			reg = &lt;0x70000 0x1000&gt;;</div><div class='add'>+			label = "cpu-bpmp-tx";</div><div class='add'>+			pool;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_bpmp_rx: sram@71000 {</div><div class='add'>+			reg = &lt;0x71000 0x1000&gt;;</div><div class='add'>+			label = "cpu-bpmp-rx";</div><div class='add'>+			pool;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bpmp: bpmp {</div><div class='add'>+		compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp";</div><div class='add'>+		mboxes = &lt;&amp;hsp_top0 TEGRA_HSP_MBOX_TYPE_DB</div><div class='add'>+				    TEGRA_HSP_DB_MASTER_BPMP&gt;;</div><div class='add'>+		shmem = &lt;&amp;cpu_bpmp_tx&gt;, &lt;&amp;cpu_bpmp_rx&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		#reset-cells = &lt;1&gt;;</div><div class='add'>+		#power-domain-cells = &lt;1&gt;;</div><div class='add'>+		interconnects = &lt;&amp;mc TEGRA234_MEMORY_CLIENT_BPMPR &amp;emc&gt;,</div><div class='add'>+				&lt;&amp;mc TEGRA234_MEMORY_CLIENT_BPMPW &amp;emc&gt;,</div><div class='add'>+				&lt;&amp;mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &amp;emc&gt;,</div><div class='add'>+				&lt;&amp;mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &amp;emc&gt;;</div><div class='add'>+		interconnect-names = "read", "write", "dma-mem", "dma-write";</div><div class='add'>+		iommus = &lt;&amp;smmu_niso1 TEGRA234_SID_BPMP&gt;;</div><div class='add'>+</div><div class='add'>+		bpmp_i2c: i2c {</div><div class='add'>+			compatible = "nvidia,tegra186-bpmp-i2c";</div><div class='add'>+			nvidia,bpmp-bus-id = &lt;5&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		bpmp_thermal: thermal {</div><div class='add'>+			compatible = "nvidia,tegra186-bpmp-thermal";</div><div class='add'>+			#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu0_0: cpu@0 {</div><div class='add'>+			compatible = "arm,cortex-a78";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x00000&gt;;</div><div class='add'>+</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+</div><div class='add'>+			operating-points-v2 = &lt;&amp;cl0_opp_tbl&gt;;</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA_ICC_MC_CPU_CLUSTER0 &amp;emc&gt;;</div><div class='add'>+</div><div class='add'>+			i-cache-size = &lt;65536&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;65536&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2c0_0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu0_1: cpu@100 {</div><div class='add'>+			compatible = "arm,cortex-a78";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x00100&gt;;</div><div class='add'>+</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+</div><div class='add'>+			operating-points-v2 = &lt;&amp;cl0_opp_tbl&gt;;</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA_ICC_MC_CPU_CLUSTER0 &amp;emc&gt;;</div><div class='add'>+</div><div class='add'>+			i-cache-size = &lt;65536&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;65536&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2c0_1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu0_2: cpu@200 {</div><div class='add'>+			compatible = "arm,cortex-a78";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x00200&gt;;</div><div class='add'>+</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+</div><div class='add'>+			operating-points-v2 = &lt;&amp;cl0_opp_tbl&gt;;</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA_ICC_MC_CPU_CLUSTER0 &amp;emc&gt;;</div><div class='add'>+</div><div class='add'>+			i-cache-size = &lt;65536&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;65536&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2c0_2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu0_3: cpu@300 {</div><div class='add'>+			compatible = "arm,cortex-a78";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x00300&gt;;</div><div class='add'>+</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+</div><div class='add'>+			operating-points-v2 = &lt;&amp;cl0_opp_tbl&gt;;</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA_ICC_MC_CPU_CLUSTER0 &amp;emc&gt;;</div><div class='add'>+</div><div class='add'>+			i-cache-size = &lt;65536&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;65536&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2c0_3&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1_0: cpu@10000 {</div><div class='add'>+			compatible = "arm,cortex-a78";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x10000&gt;;</div><div class='add'>+</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+</div><div class='add'>+			operating-points-v2 = &lt;&amp;cl1_opp_tbl&gt;;</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA_ICC_MC_CPU_CLUSTER1 &amp;emc&gt;;</div><div class='add'>+</div><div class='add'>+			i-cache-size = &lt;65536&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;65536&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2c1_0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1_1: cpu@10100 {</div><div class='add'>+			compatible = "arm,cortex-a78";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x10100&gt;;</div><div class='add'>+</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+</div><div class='add'>+			operating-points-v2 = &lt;&amp;cl1_opp_tbl&gt;;</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA_ICC_MC_CPU_CLUSTER1 &amp;emc&gt;;</div><div class='add'>+</div><div class='add'>+			i-cache-size = &lt;65536&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;65536&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2c1_1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1_2: cpu@10200 {</div><div class='add'>+			compatible = "arm,cortex-a78";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x10200&gt;;</div><div class='add'>+</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+</div><div class='add'>+			operating-points-v2 = &lt;&amp;cl1_opp_tbl&gt;;</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA_ICC_MC_CPU_CLUSTER1 &amp;emc&gt;;</div><div class='add'>+</div><div class='add'>+			i-cache-size = &lt;65536&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;65536&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2c1_2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1_3: cpu@10300 {</div><div class='add'>+			compatible = "arm,cortex-a78";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x10300&gt;;</div><div class='add'>+</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+</div><div class='add'>+			operating-points-v2 = &lt;&amp;cl1_opp_tbl&gt;;</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA_ICC_MC_CPU_CLUSTER1 &amp;emc&gt;;</div><div class='add'>+</div><div class='add'>+			i-cache-size = &lt;65536&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;65536&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2c1_3&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2_0: cpu@20000 {</div><div class='add'>+			compatible = "arm,cortex-a78";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x20000&gt;;</div><div class='add'>+</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+</div><div class='add'>+			operating-points-v2 = &lt;&amp;cl2_opp_tbl&gt;;</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA_ICC_MC_CPU_CLUSTER2 &amp;emc&gt;;</div><div class='add'>+</div><div class='add'>+			i-cache-size = &lt;65536&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;65536&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2c2_0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2_1: cpu@20100 {</div><div class='add'>+			compatible = "arm,cortex-a78";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x20100&gt;;</div><div class='add'>+</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+</div><div class='add'>+			operating-points-v2 = &lt;&amp;cl2_opp_tbl&gt;;</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA_ICC_MC_CPU_CLUSTER2 &amp;emc&gt;;</div><div class='add'>+</div><div class='add'>+			i-cache-size = &lt;65536&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;65536&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2c2_1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2_2: cpu@20200 {</div><div class='add'>+			compatible = "arm,cortex-a78";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x20200&gt;;</div><div class='add'>+</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+</div><div class='add'>+			operating-points-v2 = &lt;&amp;cl2_opp_tbl&gt;;</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA_ICC_MC_CPU_CLUSTER2 &amp;emc&gt;;</div><div class='add'>+</div><div class='add'>+			i-cache-size = &lt;65536&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;65536&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2c2_2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2_3: cpu@20300 {</div><div class='add'>+			compatible = "arm,cortex-a78";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x20300&gt;;</div><div class='add'>+</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+</div><div class='add'>+			operating-points-v2 = &lt;&amp;cl2_opp_tbl&gt;;</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA_ICC_MC_CPU_CLUSTER2 &amp;emc&gt;;</div><div class='add'>+</div><div class='add'>+			i-cache-size = &lt;65536&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;65536&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2c2_3&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu-map {</div><div class='add'>+			cluster0 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu0_0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu0_1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu0_2&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu0_3&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cluster1 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu1_0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu1_1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu1_2&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu1_3&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cluster2 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu2_0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu2_1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu2_2&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu2_3&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2c0_0: l2-cache00 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-size = &lt;262144&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;512&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l3c0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2c0_1: l2-cache01 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-size = &lt;262144&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;512&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l3c0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2c0_2: l2-cache02 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-size = &lt;262144&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;512&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l3c0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2c0_3: l2-cache03 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-size = &lt;262144&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;512&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l3c0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2c1_0: l2-cache10 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-size = &lt;262144&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;512&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l3c1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2c1_1: l2-cache11 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-size = &lt;262144&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;512&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l3c1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2c1_2: l2-cache12 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-size = &lt;262144&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;512&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l3c1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2c1_3: l2-cache13 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-size = &lt;262144&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;512&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l3c1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2c2_0: l2-cache20 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-size = &lt;262144&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;512&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l3c2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2c2_1: l2-cache21 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-size = &lt;262144&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;512&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l3c2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2c2_2: l2-cache22 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-size = &lt;262144&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;512&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l3c2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2c2_3: l2-cache23 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-size = &lt;262144&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;512&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l3c2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l3c0: l3-cache0 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;2097152&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;2048&gt;;</div><div class='add'>+			cache-level = &lt;3&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l3c1: l3-cache1 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;2097152&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;2048&gt;;</div><div class='add'>+			cache-level = &lt;3&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l3c2: l3-cache2 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-unified;</div><div class='add'>+			cache-size = &lt;2097152&gt;;</div><div class='add'>+			cache-line-size = &lt;64&gt;;</div><div class='add'>+			cache-sets = &lt;2048&gt;;</div><div class='add'>+			cache-level = &lt;3&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dsu-pmu0 {</div><div class='add'>+		compatible = "arm,dsu-pmu";</div><div class='add'>+		interrupts = &lt;GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		cpus = &lt;&amp;cpu0_0&gt;, &lt;&amp;cpu0_1&gt;, &lt;&amp;cpu0_2&gt;, &lt;&amp;cpu0_3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dsu-pmu1 {</div><div class='add'>+		compatible = "arm,dsu-pmu";</div><div class='add'>+		interrupts = &lt;GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		cpus = &lt;&amp;cpu1_0&gt;, &lt;&amp;cpu1_1&gt;, &lt;&amp;cpu1_2&gt;, &lt;&amp;cpu1_3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dsu-pmu2 {</div><div class='add'>+		compatible = "arm,dsu-pmu";</div><div class='add'>+		interrupts = &lt;GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		cpus = &lt;&amp;cpu2_0&gt;, &lt;&amp;cpu2_1&gt;, &lt;&amp;cpu2_2&gt;, &lt;&amp;cpu2_3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu {</div><div class='add'>+		compatible = "arm,cortex-a78-pmu";</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-1.0";</div><div class='add'>+		status = "okay";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	tcu: serial {</div><div class='add'>+		compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu";</div><div class='add'>+		mboxes = &lt;&amp;hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)&gt;,</div><div class='add'>+			 &lt;&amp;hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)&gt;;</div><div class='add'>+		mbox-names = "rx", "tx";</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		status = "disabled";</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;bpmp TEGRA234_CLK_PLLA&gt;,</div><div class='add'>+			 &lt;&amp;bpmp TEGRA234_CLK_PLLA_OUT0&gt;;</div><div class='add'>+		clock-names = "pll_a", "plla_out0";</div><div class='add'>+		assigned-clocks = &lt;&amp;bpmp TEGRA234_CLK_PLLA&gt;,</div><div class='add'>+				  &lt;&amp;bpmp TEGRA234_CLK_PLLA_OUT0&gt;,</div><div class='add'>+				  &lt;&amp;bpmp TEGRA234_CLK_AUD_MCLK&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;,</div><div class='add'>+					 &lt;&amp;bpmp TEGRA234_CLK_PLLA&gt;,</div><div class='add'>+					 &lt;&amp;bpmp TEGRA234_CLK_PLLA_OUT0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	thermal-zones {</div><div class='add'>+		cpu-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CPU&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_GPU&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cv0-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cv1-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cv2-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		soc0-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		soc1-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		soc2-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tj-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_TJ_MAX&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+		always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cl0_opp_tbl: opp-table-cluster0 {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+		opp-shared;</div><div class='add'>+</div><div class='add'>+		cl0_ch1_opp1: opp-115200000 {</div><div class='add'>+			  opp-hz = /bits/ 64 &lt;115200000&gt;;</div><div class='add'>+			  opp-peak-kBps = &lt;816000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl0_ch1_opp2: opp-192000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;192000000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;816000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl0_ch1_opp3: opp-268800000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;268800000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;816000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl0_ch1_opp4: opp-345600000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;345600000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;816000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl0_ch1_opp5: opp-422400000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;422400000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;816000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl0_ch1_opp6: opp-499200000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;499200000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;816000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl0_ch1_opp7: opp-576000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;576000000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;816000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl0_ch1_opp8: opp-652800000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;652800000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;816000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl0_ch1_opp9: opp-729600000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;729600000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;816000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl0_ch1_opp10: opp-806400000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;806400000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;816000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl0_ch1_opp11: opp-883200000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;883200000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;816000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl0_ch1_opp12: opp-960000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;960000000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;816000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl0_ch1_opp13: opp-1036800000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1036800000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;816000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl0_ch1_opp14: opp-1113600000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1113600000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;1632000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl0_ch1_opp15: opp-1190400000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1190400000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;1632000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl0_ch1_opp16: opp-1267200000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1267200000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;1632000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl0_ch1_opp17: opp-1344000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1344000000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;1632000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl0_ch1_opp18: opp-1420800000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1420800000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;1632000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl0_ch1_opp19: opp-1497600000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1497600000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;3200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl0_ch1_opp20: opp-1574400000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1574400000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;3200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl0_ch1_opp21: opp-1651200000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1651200000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;3200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl0_ch1_opp22: opp-1728000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1728000000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;3200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl0_ch1_opp23: opp-1804800000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1804800000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;3200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl0_ch1_opp24: opp-1881600000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1881600000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;3200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl0_ch1_opp25: opp-1958400000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1958400000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;3200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl0_ch1_opp26: opp-2035200000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2035200000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;3200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl0_ch1_opp27: opp-2112000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2112000000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;6400000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl0_ch1_opp28: opp-2188800000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2188800000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;6400000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl0_ch1_opp29: opp-2201600000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2201600000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;6400000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cl1_opp_tbl: opp-table-cluster1 {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+		opp-shared;</div><div class='add'>+</div><div class='add'>+		cl1_ch1_opp1: opp-115200000 {</div><div class='add'>+			  opp-hz = /bits/ 64 &lt;115200000&gt;;</div><div class='add'>+			  opp-peak-kBps = &lt;816000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl1_ch1_opp2: opp-192000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;192000000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;816000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl1_ch1_opp3: opp-268800000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;268800000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;816000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl1_ch1_opp4: opp-345600000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;345600000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;816000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl1_ch1_opp5: opp-422400000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;422400000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;816000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl1_ch1_opp6: opp-499200000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;499200000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;816000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl1_ch1_opp7: opp-576000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;576000000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;816000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl1_ch1_opp8: opp-652800000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;652800000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;816000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl1_ch1_opp9: opp-729600000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;729600000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;816000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl1_ch1_opp10: opp-806400000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;806400000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;816000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl1_ch1_opp11: opp-883200000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;883200000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;816000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl1_ch1_opp12: opp-960000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;960000000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;816000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl1_ch1_opp13: opp-1036800000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1036800000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;816000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl1_ch1_opp14: opp-1113600000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1113600000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;1632000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl1_ch1_opp15: opp-1190400000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1190400000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;1632000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl1_ch1_opp16: opp-1267200000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1267200000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;1632000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl1_ch1_opp17: opp-1344000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1344000000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;1632000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl1_ch1_opp18: opp-1420800000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1420800000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;1632000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl1_ch1_opp19: opp-1497600000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1497600000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;3200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl1_ch1_opp20: opp-1574400000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1574400000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;3200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl1_ch1_opp21: opp-1651200000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1651200000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;3200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl1_ch1_opp22: opp-1728000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1728000000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;3200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl1_ch1_opp23: opp-1804800000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1804800000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;3200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl1_ch1_opp24: opp-1881600000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1881600000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;3200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl1_ch1_opp25: opp-1958400000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1958400000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;3200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl1_ch1_opp26: opp-2035200000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2035200000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;3200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl1_ch1_opp27: opp-2112000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2112000000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;6400000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl1_ch1_opp28: opp-2188800000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2188800000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;6400000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl1_ch1_opp29: opp-2201600000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2201600000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;6400000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cl2_opp_tbl: opp-table-cluster2 {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+		opp-shared;</div><div class='add'>+</div><div class='add'>+		cl2_ch1_opp1: opp-115200000 {</div><div class='add'>+			  opp-hz = /bits/ 64 &lt;115200000&gt;;</div><div class='add'>+			  opp-peak-kBps = &lt;816000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl2_ch1_opp2: opp-192000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;192000000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;816000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl2_ch1_opp3: opp-268800000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;268800000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;816000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl2_ch1_opp4: opp-345600000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;345600000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;816000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl2_ch1_opp5: opp-422400000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;422400000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;816000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl2_ch1_opp6: opp-499200000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;499200000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;816000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl2_ch1_opp7: opp-576000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;576000000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;816000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl2_ch1_opp8: opp-652800000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;652800000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;816000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl2_ch1_opp9: opp-729600000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;729600000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;816000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl2_ch1_opp10: opp-806400000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;806400000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;816000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl2_ch1_opp11: opp-883200000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;883200000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;816000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl2_ch1_opp12: opp-960000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;960000000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;816000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl2_ch1_opp13: opp-1036800000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1036800000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;816000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl2_ch1_opp14: opp-1113600000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1113600000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;1632000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl2_ch1_opp15: opp-1190400000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1190400000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;1632000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl2_ch1_opp16: opp-1267200000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1267200000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;1632000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl2_ch1_opp17: opp-1344000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1344000000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;1632000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl2_ch1_opp18: opp-1420800000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1420800000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;1632000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl2_ch1_opp19: opp-1497600000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1497600000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;3200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl2_ch1_opp20: opp-1574400000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1574400000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;3200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl2_ch1_opp21: opp-1651200000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1651200000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;3200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl2_ch1_opp22: opp-1728000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1728000000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;3200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl2_ch1_opp23: opp-1804800000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1804800000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;3200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl2_ch1_opp24: opp-1881600000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1881600000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;3200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl2_ch1_opp25: opp-1958400000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1958400000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;3200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl2_ch1_opp26: opp-2035200000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2035200000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;3200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl2_ch1_opp27: opp-2112000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2112000000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;6400000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl2_ch1_opp28: opp-2188800000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2188800000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;6400000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cl2_ch1_opp29: opp-2201600000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2201600000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;6400000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/tegra264-p3834-0008.dtsi b/arch/arm64/boot/dts/nvidia/tegra264-p3834-0008.dtsi<br/>new file mode 100644<br/>index 000000000000..94ace6784749<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra264-p3834-0008.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/tegra264-p3834-0008.dtsi</a></div><div class='hunk'>@@ -0,0 +1,7 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause</div><div class='add'>+</div><div class='add'>+#include "tegra264-p3834.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "nvidia,p3834-0008", "nvidia,tegra264";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi b/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi<br/>new file mode 100644<br/>index 000000000000..06795c82427a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi</a></div><div class='hunk'>@@ -0,0 +1,30 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause</div><div class='add'>+</div><div class='add'>+#include "tegra264.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "nvidia,p3834", "nvidia,tegra264";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bus@0 {</div><div class='add'>+		serial@c4e0000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		serial@c5a0000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bus@8100000000 {</div><div class='add'>+		iommu@5000000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		iommu@6000000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/tegra264-p3971-0089+p3834-0008.dts b/arch/arm64/boot/dts/nvidia/tegra264-p3971-0089+p3834-0008.dts<br/>new file mode 100644<br/>index 000000000000..3a6f4b7e6b75<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra264-p3971-0089+p3834-0008.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/tegra264-p3971-0089+p3834-0008.dts</a></div><div class='hunk'>@@ -0,0 +1,11 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+// module files must be included first</div><div class='add'>+#include "tegra264-p3834-0008.dtsi"</div><div class='add'>+#include "tegra264-p3971-0089+p3834.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "NVIDIA P3971-0089+P3834-0008 Engineering Reference Platform";</div><div class='add'>+	compatible = "nvidia,p3971-0089+p3834-0008", "nvidia,p3834-0008", "nvidia,tegra264";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/tegra264-p3971-0089+p3834.dtsi b/arch/arm64/boot/dts/nvidia/tegra264-p3971-0089+p3834.dtsi<br/>new file mode 100644<br/>index 000000000000..46cfa8f1da1c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra264-p3971-0089+p3834.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/tegra264-p3971-0089+p3834.dtsi</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause</div><div class='add'>+</div><div class='add'>+#include "tegra264-p3971-0089.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;{/bus@0/serial@c4e0000};</div><div class='add'>+		serial1 = &amp;{/bus@0/serial@c5a0000};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/tegra264-p3971-0089.dtsi b/arch/arm64/boot/dts/nvidia/tegra264-p3971-0089.dtsi<br/>new file mode 100644<br/>index 000000000000..e8576cf2a0b6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra264-p3971-0089.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/tegra264-p3971-0089.dtsi</a></div><div class='hunk'>@@ -0,0 +1,3 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause</div><div class='add'>+</div><div class='add'>+#include "tegra264-p3971.dtsi"</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/tegra264-p3971.dtsi b/arch/arm64/boot/dts/nvidia/tegra264-p3971.dtsi<br/>new file mode 100644<br/>index 000000000000..b1bd4ee7aee3<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra264-p3971.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/tegra264-p3971.dtsi</a></div><div class='hunk'>@@ -0,0 +1,112 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	bus@0 {</div><div class='add'>+		aconnect@9000000 {</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			dma-controller@9440000 {</div><div class='add'>+				status = "okay";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			ahub@9630000 {</div><div class='add'>+				status = "okay";</div><div class='add'>+</div><div class='add'>+				i2s@9280000 {</div><div class='add'>+					status = "okay";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				i2s@9290000 {</div><div class='add'>+					status = "okay";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				i2s@92b0000 {</div><div class='add'>+					status = "okay";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			interrupt-controller@9960000 {</div><div class='add'>+				status = "okay";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bus@8800000000 {</div><div class='add'>+		hda@90b0000 {</div><div class='add'>+			nvidia,model = "NVIDIA Jetson Thor AGX HDA";</div><div class='add'>+			status = "okay";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		status = "okay";</div><div class='add'>+</div><div class='add'>+		dais = /* ADMAIF (FE) Ports */</div><div class='add'>+		       &lt;&amp;admaif0_port&gt;, &lt;&amp;admaif1_port&gt;, &lt;&amp;admaif2_port&gt;, &lt;&amp;admaif3_port&gt;,</div><div class='add'>+		       &lt;&amp;admaif4_port&gt;, &lt;&amp;admaif5_port&gt;, &lt;&amp;admaif6_port&gt;, &lt;&amp;admaif7_port&gt;,</div><div class='add'>+		       &lt;&amp;admaif8_port&gt;, &lt;&amp;admaif9_port&gt;, &lt;&amp;admaif10_port&gt;, &lt;&amp;admaif11_port&gt;,</div><div class='add'>+		       &lt;&amp;admaif12_port&gt;, &lt;&amp;admaif13_port&gt;, &lt;&amp;admaif14_port&gt;, &lt;&amp;admaif15_port&gt;,</div><div class='add'>+		       &lt;&amp;admaif16_port&gt;, &lt;&amp;admaif17_port&gt;, &lt;&amp;admaif18_port&gt;, &lt;&amp;admaif19_port&gt;,</div><div class='add'>+		       &lt;&amp;admaif20_port&gt;, &lt;&amp;admaif21_port&gt;, &lt;&amp;admaif22_port&gt;, &lt;&amp;admaif23_port&gt;,</div><div class='add'>+		       &lt;&amp;admaif24_port&gt;, &lt;&amp;admaif25_port&gt;, &lt;&amp;admaif26_port&gt;, &lt;&amp;admaif27_port&gt;,</div><div class='add'>+		       &lt;&amp;admaif28_port&gt;, &lt;&amp;admaif29_port&gt;, &lt;&amp;admaif30_port&gt;, &lt;&amp;admaif31_port&gt;,</div><div class='add'>+		       /* XBAR Ports */</div><div class='add'>+		       &lt;&amp;xbar_i2s1_port&gt;, &lt;&amp;xbar_i2s2_port&gt;, &lt;&amp;xbar_i2s4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_sfc1_in_port&gt;, &lt;&amp;xbar_sfc2_in_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_sfc3_in_port&gt;, &lt;&amp;xbar_sfc4_in_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mvc1_in_port&gt;, &lt;&amp;xbar_mvc2_in_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx1_in1_port&gt;, &lt;&amp;xbar_amx1_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx1_in3_port&gt;, &lt;&amp;xbar_amx1_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx2_in1_port&gt;, &lt;&amp;xbar_amx2_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx2_in3_port&gt;, &lt;&amp;xbar_amx2_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx3_in1_port&gt;, &lt;&amp;xbar_amx3_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx3_in3_port&gt;, &lt;&amp;xbar_amx3_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx4_in1_port&gt;, &lt;&amp;xbar_amx4_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx4_in3_port&gt;, &lt;&amp;xbar_amx4_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx5_in1_port&gt;, &lt;&amp;xbar_amx5_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx5_in3_port&gt;, &lt;&amp;xbar_amx5_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx6_in1_port&gt;, &lt;&amp;xbar_amx6_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_amx6_in3_port&gt;, &lt;&amp;xbar_amx6_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_adx1_in_port&gt;, &lt;&amp;xbar_adx2_in_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_adx3_in_port&gt;, &lt;&amp;xbar_adx4_in_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_adx5_in_port&gt;, &lt;&amp;xbar_adx6_in_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mix_in1_port&gt;, &lt;&amp;xbar_mix_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mix_in3_port&gt;, &lt;&amp;xbar_mix_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mix_in5_port&gt;, &lt;&amp;xbar_mix_in6_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mix_in7_port&gt;, &lt;&amp;xbar_mix_in8_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_mix_in9_port&gt;, &lt;&amp;xbar_mix_in10_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_asrc_in1_port&gt;, &lt;&amp;xbar_asrc_in2_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_asrc_in3_port&gt;, &lt;&amp;xbar_asrc_in4_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_asrc_in5_port&gt;, &lt;&amp;xbar_asrc_in6_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_asrc_in7_port&gt;,</div><div class='add'>+		       &lt;&amp;xbar_ope1_in_port&gt;,</div><div class='add'>+		       /* HW accelerators */</div><div class='add'>+		       &lt;&amp;sfc1_out_port&gt;, &lt;&amp;sfc2_out_port&gt;,</div><div class='add'>+		       &lt;&amp;sfc3_out_port&gt;, &lt;&amp;sfc4_out_port&gt;,</div><div class='add'>+		       &lt;&amp;mvc1_out_port&gt;, &lt;&amp;mvc2_out_port&gt;,</div><div class='add'>+		       &lt;&amp;amx1_out_port&gt;, &lt;&amp;amx2_out_port&gt;,</div><div class='add'>+		       &lt;&amp;amx3_out_port&gt;, &lt;&amp;amx4_out_port&gt;,</div><div class='add'>+		       &lt;&amp;amx5_out_port&gt;, &lt;&amp;amx6_out_port&gt;,</div><div class='add'>+		       &lt;&amp;adx1_out1_port&gt;, &lt;&amp;adx1_out2_port&gt;,</div><div class='add'>+		       &lt;&amp;adx1_out3_port&gt;, &lt;&amp;adx1_out4_port&gt;,</div><div class='add'>+		       &lt;&amp;adx2_out1_port&gt;, &lt;&amp;adx2_out2_port&gt;,</div><div class='add'>+		       &lt;&amp;adx2_out3_port&gt;, &lt;&amp;adx2_out4_port&gt;,</div><div class='add'>+		       &lt;&amp;adx3_out1_port&gt;, &lt;&amp;adx3_out2_port&gt;,</div><div class='add'>+		       &lt;&amp;adx3_out3_port&gt;, &lt;&amp;adx3_out4_port&gt;,</div><div class='add'>+		       &lt;&amp;adx4_out1_port&gt;, &lt;&amp;adx4_out2_port&gt;,</div><div class='add'>+		       &lt;&amp;adx4_out3_port&gt;, &lt;&amp;adx4_out4_port&gt;,</div><div class='add'>+		       &lt;&amp;adx5_out1_port&gt;, &lt;&amp;adx5_out2_port&gt;,</div><div class='add'>+		       &lt;&amp;adx5_out3_port&gt;, &lt;&amp;adx5_out4_port&gt;,</div><div class='add'>+		       &lt;&amp;adx6_out1_port&gt;, &lt;&amp;adx6_out2_port&gt;,</div><div class='add'>+		       &lt;&amp;adx6_out3_port&gt;, &lt;&amp;adx6_out4_port&gt;,</div><div class='add'>+		       &lt;&amp;mix_out1_port&gt;, &lt;&amp;mix_out2_port&gt;, &lt;&amp;mix_out3_port&gt;,</div><div class='add'>+		       &lt;&amp;mix_out4_port&gt;, &lt;&amp;mix_out5_port&gt;,</div><div class='add'>+		       &lt;&amp;asrc_out1_port&gt;, &lt;&amp;asrc_out2_port&gt;, &lt;&amp;asrc_out3_port&gt;,</div><div class='add'>+		       &lt;&amp;asrc_out4_port&gt;, &lt;&amp;asrc_out5_port&gt;, &lt;&amp;asrc_out6_port&gt;,</div><div class='add'>+		       &lt;&amp;ope1_out_port&gt;,</div><div class='add'>+		       /* BE I/O Ports */</div><div class='add'>+		       &lt;&amp;i2s1_port&gt;, &lt;&amp;i2s2_port&gt;, &lt;&amp;i2s4_port&gt;;</div><div class='add'>+</div><div class='add'>+		label = "NVIDIA Jetson Thor AGX APE";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi<br/>new file mode 100644<br/>index 000000000000..f137565da804<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/nvidia/tegra264.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/nvidia/tegra264.dtsi</a></div><div class='hunk'>@@ -0,0 +1,3827 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/nvidia,tegra264.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/mailbox/tegra186-hsp.h&gt;</div><div class='add'>+#include &lt;dt-bindings/memory/nvidia,tegra264.h&gt;</div><div class='add'>+#include &lt;dt-bindings/power/nvidia,tegra264-bpmp.h&gt;</div><div class='add'>+#include &lt;dt-bindings/reset/nvidia,tegra264.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	compatible = "nvidia,tegra264";</div><div class='add'>+	interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		shmem_bpmp: shmem@86070000 {</div><div class='add'>+			compatible = "nvidia,tegra264-bpmp-shmem";</div><div class='add'>+			reg = &lt;0x0 0x86070000 0x0 0x2000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* SYSTEM MMIO */</div><div class='add'>+	bus@0 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		ranges = &lt;0x00 0x00000000 0x00 0x00000000 0x01 0x00000000&gt;;</div><div class='add'>+</div><div class='add'>+		misc@100000 {</div><div class='add'>+			compatible = "nvidia,tegra234-misc";</div><div class='add'>+			reg = &lt;0x0 0x00100000 0x0 0x0f000&gt;,</div><div class='add'>+			      &lt;0x0 0x0c140000 0x0 0x10000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		timer@8000000 {</div><div class='add'>+			compatible = "nvidia,tegra234-timer";</div><div class='add'>+			reg = &lt;0x0 0x08000000 0x0 0x140000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 776 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aconnect@9000000 {</div><div class='add'>+			compatible = "nvidia,tegra264-aconnect",</div><div class='add'>+					"nvidia,tegra210-aconnect";</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA264_CLK_APE&gt;,</div><div class='add'>+				&lt;&amp;bpmp TEGRA264_CLK_ADSP&gt;;</div><div class='add'>+			clock-names = "ape", "apb2ape";</div><div class='add'>+			power-domains = &lt;&amp;bpmp TEGRA264_POWER_DOMAIN_AUD&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges = &lt;0x0 0x9000000 0x0 0x9000000 0x0 0x2000000&gt;;</div><div class='add'>+</div><div class='add'>+			adma: dma-controller@9440000 {</div><div class='add'>+				compatible = "nvidia,tegra264-adma";</div><div class='add'>+				reg = &lt;0x0 0x9440000 0x0 0xb0000&gt;;</div><div class='add'>+				interrupt-parent = &lt;&amp;agic_page0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 0x90 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0x91 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0x92 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0x93 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0x94 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0x95 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0x96 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0x97 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0x98 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0x99 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0x9a IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0x9b IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0x9c IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0x9d IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0x9e IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0x9f IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xa0 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xa1 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xa2 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xa3 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xa4 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xa5 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xa6 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xa7 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xa8 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xa9 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xaa IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xab IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xac IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xad IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xae IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xaf IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xb0 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xb1 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xb2 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xb3 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xb4 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xb5 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xb6 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xb7 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xb8 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xb9 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xba IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xbb IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xbc IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xbd IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xbe IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xbf IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xc0 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xc1 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xc2 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xc3 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xc4 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xc5 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xc6 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xc7 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xc8 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xc9 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xca IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xcb IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xcc IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xcd IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xce IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					   &lt;GIC_SPI 0xcf IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#dma-cells = &lt;1&gt;;</div><div class='add'>+				clocks = &lt;&amp;bpmp TEGRA264_CLK_AHUB&gt;;</div><div class='add'>+				clock-names = "d_audio";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tegra_ahub: ahub@9630000 {</div><div class='add'>+				compatible = "nvidia,tegra264-ahub";</div><div class='add'>+				reg = &lt;0x0 0x9630000 0x0 0x10000&gt;;</div><div class='add'>+				clocks = &lt;&amp;bpmp TEGRA264_CLK_AHUB&gt;;</div><div class='add'>+				clock-names = "ahub";</div><div class='add'>+				assigned-clocks = &lt;&amp;bpmp TEGRA264_CLK_AHUB&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;bpmp TEGRA264_CLK_PLLAON_APE&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;2&gt;;</div><div class='add'>+				#size-cells = &lt;2&gt;;</div><div class='add'>+				/* ADMA is under AHUB range, its excluded in the defined range */</div><div class='add'>+				ranges = &lt;0x0 0x9280000 0x0 0x9280000 0x0 0x1c0000&gt;,</div><div class='add'>+					&lt;0x0 0x9510000 0x0 0x9510000 0x0 0x370000&gt;;</div><div class='add'>+</div><div class='add'>+				tegra_i2s1: i2s@9280000 {</div><div class='add'>+					compatible = "nvidia,tegra264-i2s";</div><div class='add'>+					reg = &lt;0x0 0x9280000 0x0 0x10000&gt;;</div><div class='add'>+					clocks = &lt;&amp;bpmp TEGRA264_CLK_I2S1&gt;,</div><div class='add'>+					       &lt;&amp;bpmp TEGRA264_CLK_I2S1_SCLK_IN&gt;;</div><div class='add'>+					clock-names = "i2s", "sync_input";</div><div class='add'>+					assigned-clocks = &lt;&amp;bpmp TEGRA264_CLK_I2S1&gt;;</div><div class='add'>+					assigned-clock-parents = &lt;&amp;bpmp TEGRA264_CLK_PLLA1_OUT1&gt;;</div><div class='add'>+					assigned-clock-rates = &lt;1536000&gt;;</div><div class='add'>+					sound-name-prefix = "I2S1";</div><div class='add'>+					status = "disabled";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							i2s1_cif: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_i2s1&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						i2s1_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							i2s1_dap: endpoint {</div><div class='add'>+								dai-format = "i2s";</div><div class='add'>+								/* placeholder for external codec */</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_i2s2: i2s@9290000 {</div><div class='add'>+					compatible = "nvidia,tegra264-i2s";</div><div class='add'>+					reg = &lt;0x0 0x9290000 0x0 0x10000&gt;;</div><div class='add'>+					clocks = &lt;&amp;bpmp TEGRA264_CLK_I2S2&gt;,</div><div class='add'>+						 &lt;&amp;bpmp TEGRA264_CLK_I2S2_SCLK_IN&gt;;</div><div class='add'>+					clock-names = "i2s", "sync_input";</div><div class='add'>+					assigned-clocks = &lt;&amp;bpmp TEGRA264_CLK_I2S2&gt;;</div><div class='add'>+					assigned-clock-parents = &lt;&amp;bpmp TEGRA264_CLK_PLLA1_OUT1&gt;;</div><div class='add'>+					assigned-clock-rates = &lt;1536000&gt;;</div><div class='add'>+					sound-name-prefix = "I2S2";</div><div class='add'>+					status = "disabled";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							i2s2_cif: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_i2s2&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						i2s2_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							i2s2_dap: endpoint {</div><div class='add'>+								dai-format = "i2s";</div><div class='add'>+								/* placeholder for external codec */</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_i2s3: i2s@92a0000 {</div><div class='add'>+					compatible = "nvidia,tegra264-i2s";</div><div class='add'>+					reg = &lt;0x0 0x92a0000 0x0 0x10000&gt;;</div><div class='add'>+					clocks = &lt;&amp;bpmp TEGRA264_CLK_I2S3&gt;,</div><div class='add'>+					       &lt;&amp;bpmp TEGRA264_CLK_I2S3_SCLK_IN&gt;;</div><div class='add'>+					clock-names = "i2s", "sync_input";</div><div class='add'>+					assigned-clocks = &lt;&amp;bpmp TEGRA264_CLK_I2S3&gt;;</div><div class='add'>+					assigned-clock-parents = &lt;&amp;bpmp TEGRA264_CLK_PLLA1_OUT1&gt;;</div><div class='add'>+					assigned-clock-rates = &lt;1536000&gt;;</div><div class='add'>+					sound-name-prefix = "I2S3";</div><div class='add'>+					status = "disabled";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							i2s3_cif: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_i2s3&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						i2s3_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							i2s3_dap: endpoint {</div><div class='add'>+								dai-format = "i2s";</div><div class='add'>+								/* placeholder for external codec */</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_i2s4: i2s@92b0000 {</div><div class='add'>+					compatible = "nvidia,tegra264-i2s";</div><div class='add'>+					reg = &lt;0x0 0x92b0000 0x0 0x10000&gt;;</div><div class='add'>+					clocks = &lt;&amp;bpmp TEGRA264_CLK_I2S4&gt;,</div><div class='add'>+					       &lt;&amp;bpmp TEGRA264_CLK_I2S4_SCLK_IN&gt;;</div><div class='add'>+					clock-names = "i2s", "sync_input";</div><div class='add'>+					assigned-clocks = &lt;&amp;bpmp TEGRA264_CLK_I2S4&gt;;</div><div class='add'>+					assigned-clock-parents = &lt;&amp;bpmp TEGRA264_CLK_PLLA1_OUT1&gt;;</div><div class='add'>+					assigned-clock-rates = &lt;1536000&gt;;</div><div class='add'>+					sound-name-prefix = "I2S4";</div><div class='add'>+					status = "disabled";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							i2s4_cif: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_i2s4&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						i2s4_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							i2s4_dap: endpoint {</div><div class='add'>+								dai-format = "i2s";</div><div class='add'>+								/* placeholder for external codec */</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_i2s5: i2s@92c0000 {</div><div class='add'>+					compatible = "nvidia,tegra264-i2s";</div><div class='add'>+					reg = &lt;0x0 0x92c0000 0x0 0x10000&gt;;</div><div class='add'>+					clocks = &lt;&amp;bpmp TEGRA264_CLK_I2S5&gt;,</div><div class='add'>+					       &lt;&amp;bpmp TEGRA264_CLK_I2S5_SCLK_IN&gt;;</div><div class='add'>+					clock-names = "i2s", "sync_input";</div><div class='add'>+					assigned-clocks = &lt;&amp;bpmp TEGRA264_CLK_I2S5&gt;;</div><div class='add'>+					assigned-clock-parents = &lt;&amp;bpmp TEGRA264_CLK_PLLA1_OUT1&gt;;</div><div class='add'>+					assigned-clock-rates = &lt;1536000&gt;;</div><div class='add'>+					sound-name-prefix = "I2S5";</div><div class='add'>+					status = "disabled";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							i2s5_cif: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_i2s5&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						i2s5_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							i2s5_dap: endpoint {</div><div class='add'>+								dai-format = "i2s";</div><div class='add'>+								/* placeholder for external codec */</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_i2s6: i2s@92d0000 {</div><div class='add'>+					compatible = "nvidia,tegra264-i2s";</div><div class='add'>+					reg = &lt;0x0 0x92d0000 0x0 0x10000&gt;;</div><div class='add'>+					clocks = &lt;&amp;bpmp TEGRA264_CLK_I2S6&gt;,</div><div class='add'>+					       &lt;&amp;bpmp TEGRA264_CLK_I2S6_SCLK_IN&gt;;</div><div class='add'>+					clock-names = "i2s", "sync_input";</div><div class='add'>+					assigned-clocks = &lt;&amp;bpmp TEGRA264_CLK_I2S6&gt;;</div><div class='add'>+					assigned-clock-parents = &lt;&amp;bpmp TEGRA264_CLK_PLLA1_OUT1&gt;;</div><div class='add'>+					assigned-clock-rates = &lt;1536000&gt;;</div><div class='add'>+					sound-name-prefix = "I2S6";</div><div class='add'>+					status = "disabled";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							i2s6_cif: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_i2s6&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						i2s6_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							i2s6_dap: endpoint {</div><div class='add'>+								dai-format = "i2s";</div><div class='add'>+								/* placeholder for external codec */</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_i2s7: i2s@92e0000 {</div><div class='add'>+					compatible = "nvidia,tegra264-i2s";</div><div class='add'>+					reg = &lt;0x0 0x92e0000 0x0 0x10000&gt;;</div><div class='add'>+					clocks = &lt;&amp;bpmp TEGRA264_CLK_I2S7&gt;,</div><div class='add'>+					       &lt;&amp;bpmp TEGRA264_CLK_I2S7_SCLK_IN&gt;;</div><div class='add'>+					clock-names = "i2s", "sync_input";</div><div class='add'>+					assigned-clocks = &lt;&amp;bpmp TEGRA264_CLK_I2S7&gt;;</div><div class='add'>+					assigned-clock-parents = &lt;&amp;bpmp TEGRA264_CLK_PLLA1_OUT1&gt;;</div><div class='add'>+					assigned-clock-rates = &lt;1536000&gt;;</div><div class='add'>+					sound-name-prefix = "I2S7";</div><div class='add'>+					status = "disabled";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							i2s7_cif: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_i2s7&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						i2s7_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							i2s7_dap: endpoint {</div><div class='add'>+								dai-format = "i2s";</div><div class='add'>+								/* placeholder for external codec */</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_i2s8: i2s@92f0000 {</div><div class='add'>+					compatible = "nvidia,tegra264-i2s";</div><div class='add'>+					reg = &lt;0x0 0x92f0000 0x0 0x10000&gt;;</div><div class='add'>+					clocks = &lt;&amp;bpmp TEGRA264_CLK_I2S8&gt;,</div><div class='add'>+					       &lt;&amp;bpmp TEGRA264_CLK_I2S8_SCLK_IN&gt;;</div><div class='add'>+					clock-names = "i2s", "sync_input";</div><div class='add'>+					assigned-clocks = &lt;&amp;bpmp TEGRA264_CLK_I2S8&gt;;</div><div class='add'>+					assigned-clock-parents = &lt;&amp;bpmp TEGRA264_CLK_PLLA1_OUT1&gt;;</div><div class='add'>+					assigned-clock-rates = &lt;1536000&gt;;</div><div class='add'>+					sound-name-prefix = "I2S8";</div><div class='add'>+					status = "disabled";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							i2s8_cif: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_i2s8&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						i2s8_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							i2s8_dap: endpoint {</div><div class='add'>+								dai-format = "i2s";</div><div class='add'>+								/* placeholder for external codec */</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_dmic1: dmic@9300000 {</div><div class='add'>+					compatible = "nvidia,tegra264-dmic",</div><div class='add'>+							"nvidia,tegra210-dmic";</div><div class='add'>+					reg = &lt;0x0 0x9300000 0x0 0x10000&gt;;</div><div class='add'>+					clocks = &lt;&amp;bpmp TEGRA264_CLK_DMIC1&gt;;</div><div class='add'>+					clock-names = "dmic";</div><div class='add'>+					assigned-clocks = &lt;&amp;bpmp TEGRA264_CLK_DMIC1&gt;;</div><div class='add'>+					assigned-clock-parents = &lt;&amp;bpmp TEGRA264_CLK_PLLA1_OUT1&gt;;</div><div class='add'>+					assigned-clock-rates = &lt;3072000&gt;;</div><div class='add'>+					sound-name-prefix = "DMIC1";</div><div class='add'>+					status = "disabled";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							dmic1_cif: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_dmic1&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						dmic1_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							dmic1_dap: endpoint {</div><div class='add'>+								/* placeholder for external codec */</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_dmic2: dmic@9310000 {</div><div class='add'>+					compatible = "nvidia,tegra264-dmic",</div><div class='add'>+						   "nvidia,tegra210-dmic";</div><div class='add'>+					reg = &lt;0x0 0x9310000 0x0 0x10000&gt;;</div><div class='add'>+					clocks = &lt;&amp;bpmp TEGRA264_CLK_DMIC1&gt;;</div><div class='add'>+					clock-names = "dmic";</div><div class='add'>+					assigned-clocks = &lt;&amp;bpmp TEGRA264_CLK_DMIC1&gt;;</div><div class='add'>+					assigned-clock-parents = &lt;&amp;bpmp TEGRA264_CLK_PLLA1_OUT1&gt;;</div><div class='add'>+					assigned-clock-rates = &lt;3072000&gt;;</div><div class='add'>+					sound-name-prefix = "DMIC2";</div><div class='add'>+					status = "disabled";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							dmic2_cif: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_dmic2&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						dmic2_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							dmic2_dap: endpoint {</div><div class='add'>+								/* placeholder for external codec */</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_dspk1: dspk@9380000 {</div><div class='add'>+					compatible = "nvidia,tegra264-dspk",</div><div class='add'>+							"nvidia,tegra186-dspk";</div><div class='add'>+					reg = &lt;0x0 0x9380000 0x0 0x10000&gt;;</div><div class='add'>+					clocks = &lt;&amp;bpmp TEGRA264_CLK_DSPK1&gt;;</div><div class='add'>+					clock-names = "dspk";</div><div class='add'>+					assigned-clocks = &lt;&amp;bpmp TEGRA264_CLK_DSPK1&gt;;</div><div class='add'>+					assigned-clock-parents = &lt;&amp;bpmp TEGRA264_CLK_PLLA1_OUT1&gt;;</div><div class='add'>+					assigned-clock-rates = &lt;12288000&gt;;</div><div class='add'>+					sound-name-prefix = "DSPK1";</div><div class='add'>+					status = "disabled";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							dspk1_cif: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_dspk1&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						dspk1_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							dspk1_dap: endpoint {</div><div class='add'>+								/* placeholder for external codec */</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_amx1: amx@9510000 {</div><div class='add'>+					compatible = "nvidia,tegra264-amx";</div><div class='add'>+					reg = &lt;0x0 0x9510000 0x0 0x10000&gt;;</div><div class='add'>+					sound-name-prefix = "AMX1";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							amx1_in1: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx1_in1&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							amx1_in2: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx1_in2&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@2 {</div><div class='add'>+							reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+							amx1_in3: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx1_in3&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@3 {</div><div class='add'>+							reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+							amx1_in4: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx1_in4&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						amx1_out_port: port@4 {</div><div class='add'>+							reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+							amx1_out: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx1_out&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_amx2: amx@9520000 {</div><div class='add'>+					compatible = "nvidia,tegra264-amx";</div><div class='add'>+					reg = &lt;0x0 0x9520000 0x0 0x10000&gt;;</div><div class='add'>+					sound-name-prefix = "AMX2";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							amx2_in1: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx2_in1&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							amx2_in2: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx2_in2&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@2 {</div><div class='add'>+							reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+							amx2_in3: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx2_in3&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@3 {</div><div class='add'>+							reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+							amx2_in4: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx2_in4&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						amx2_out_port: port@4 {</div><div class='add'>+							reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+							amx2_out: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx2_out&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_amx3: amx@9530000 {</div><div class='add'>+					compatible = "nvidia,tegra264-amx";</div><div class='add'>+					reg = &lt;0x0 0x9530000 0x0 0x10000&gt;;</div><div class='add'>+					sound-name-prefix = "AMX3";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							amx3_in1: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx3_in1&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							amx3_in2: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx3_in2&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@2 {</div><div class='add'>+							reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+							amx3_in3: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx3_in3&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@3 {</div><div class='add'>+							reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+							amx3_in4: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx3_in4&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						amx3_out_port: port@4 {</div><div class='add'>+							reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+							amx3_out: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx3_out&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_amx4: amx@9540000 {</div><div class='add'>+					compatible = "nvidia,tegra264-amx";</div><div class='add'>+					reg = &lt;0x0 0x9540000 0x0 0x10000&gt;;</div><div class='add'>+					sound-name-prefix = "AMX4";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							amx4_in1: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx4_in1&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							amx4_in2: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx4_in2&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@2 {</div><div class='add'>+							reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+							amx4_in3: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx4_in3&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@3 {</div><div class='add'>+							reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+							amx4_in4: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx4_in4&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						amx4_out_port: port@4 {</div><div class='add'>+							reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+							amx4_out: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx4_out&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_amx5: amx@9550000 {</div><div class='add'>+					compatible = "nvidia,tegra264-amx";</div><div class='add'>+					reg = &lt;0x0 0x9550000 0x0 0x10000&gt;;</div><div class='add'>+					sound-name-prefix = "AMX5";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							amx5_in1: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx5_in1&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							amx5_in2: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx5_in2&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@2 {</div><div class='add'>+							reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+							amx5_in3: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx5_in3&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@3 {</div><div class='add'>+							reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+							amx5_in4: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx5_in4&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						amx5_out_port: port@4 {</div><div class='add'>+							reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+							amx5_out: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx5_out&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_amx6: amx@9560000 {</div><div class='add'>+					compatible = "nvidia,tegra264-amx";</div><div class='add'>+					reg = &lt;0x0 0x9560000 0x0 0x10000&gt;;</div><div class='add'>+					sound-name-prefix = "AMX6";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							amx6_in1: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx6_in1&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							amx6_in2: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx6_in2&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@2 {</div><div class='add'>+							reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+							amx6_in3: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx6_in3&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@3 {</div><div class='add'>+							reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+							amx6_in4: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx6_in4&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						amx6_out_port: port@4 {</div><div class='add'>+							reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+							amx6_out: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_amx6_out&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_adx1: adx@9590000 {</div><div class='add'>+					compatible = "nvidia,tegra264-adx";</div><div class='add'>+					reg = &lt;0x0 0x9590000 0x0 0x10000&gt;;</div><div class='add'>+					sound-name-prefix = "ADX1";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							adx1_in: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx1_in&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx1_out1_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							adx1_out1: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx1_out1&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx1_out2_port: port@2 {</div><div class='add'>+							reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+							adx1_out2: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx1_out2&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx1_out3_port: port@3 {</div><div class='add'>+							reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+							adx1_out3: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx1_out3&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx1_out4_port: port@4 {</div><div class='add'>+							reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+							adx1_out4: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx1_out4&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_adx2: adx@95a0000 {</div><div class='add'>+					compatible = "nvidia,tegra264-adx";</div><div class='add'>+					reg = &lt;0x0 0x95a0000 0x0 0x10000&gt;;</div><div class='add'>+					sound-name-prefix = "ADX2";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							adx2_in: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx2_in&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx2_out1_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							adx2_out1: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx2_out1&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx2_out2_port: port@2 {</div><div class='add'>+							reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+							adx2_out2: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx2_out2&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx2_out3_port: port@3 {</div><div class='add'>+							reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+							adx2_out3: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx2_out3&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx2_out4_port: port@4 {</div><div class='add'>+							reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+							adx2_out4: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx2_out4&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_adx3: adx@95b0000 {</div><div class='add'>+					compatible = "nvidia,tegra264-adx";</div><div class='add'>+					reg = &lt;0x0 0x95b0000 0x0 0x10000&gt;;</div><div class='add'>+					sound-name-prefix = "ADX3";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							adx3_in: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx3_in&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx3_out1_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							adx3_out1: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx3_out1&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx3_out2_port: port@2 {</div><div class='add'>+							reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+							adx3_out2: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx3_out2&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx3_out3_port: port@3 {</div><div class='add'>+							reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+							adx3_out3: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx3_out3&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx3_out4_port: port@4 {</div><div class='add'>+							reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+							adx3_out4: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx3_out4&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_adx4: adx@95c0000 {</div><div class='add'>+					compatible = "nvidia,tegra264-adx";</div><div class='add'>+					reg = &lt;0x0 0x95c0000 0x0 0x10000&gt;;</div><div class='add'>+					sound-name-prefix = "ADX4";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							adx4_in: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx4_in&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx4_out1_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							adx4_out1: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx4_out1&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx4_out2_port: port@2 {</div><div class='add'>+							reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+							adx4_out2: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx4_out2&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx4_out3_port: port@3 {</div><div class='add'>+							reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+							adx4_out3: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx4_out3&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx4_out4_port: port@4 {</div><div class='add'>+							reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+							adx4_out4: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx4_out4&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_adx5: adx@95d0000 {</div><div class='add'>+					compatible = "nvidia,tegra264-adx";</div><div class='add'>+					reg = &lt;0x0 0x95d0000 0x0 0x10000&gt;;</div><div class='add'>+					sound-name-prefix = "ADX5";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							adx5_in: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx5_in&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx5_out1_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							adx5_out1: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx5_out1&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx5_out2_port: port@2 {</div><div class='add'>+							reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+							adx5_out2: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx5_out2&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx5_out3_port: port@3 {</div><div class='add'>+							reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+							adx5_out3: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx5_out3&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx5_out4_port: port@4 {</div><div class='add'>+							reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+							adx5_out4: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx5_out4&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_adx6: adx@95e0000 {</div><div class='add'>+					compatible = "nvidia,tegra264-adx";</div><div class='add'>+					reg = &lt;0x0 0x95e0000 0x0 0x10000&gt;;</div><div class='add'>+					sound-name-prefix = "ADX6";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							adx6_in: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx6_in&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx6_out1_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							adx6_out1: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx6_out1&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx6_out2_port: port@2 {</div><div class='add'>+							reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+							adx6_out2: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx6_out2&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx6_out3_port: port@3 {</div><div class='add'>+							reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+							adx6_out3: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx6_out3&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						adx6_out4_port: port@4 {</div><div class='add'>+							reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+							adx6_out4: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_adx6_out4&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_admaif: admaif@9610000 {</div><div class='add'>+					compatible = "nvidia,tegra264-admaif";</div><div class='add'>+					reg = &lt;0x0 0x9610000 0x0 0x10000&gt;;</div><div class='add'>+					dmas = &lt;&amp;adma 1&gt;, &lt;&amp;adma 1&gt;,</div><div class='add'>+					     &lt;&amp;adma 2&gt;, &lt;&amp;adma 2&gt;,</div><div class='add'>+					     &lt;&amp;adma 3&gt;, &lt;&amp;adma 3&gt;,</div><div class='add'>+					     &lt;&amp;adma 4&gt;, &lt;&amp;adma 4&gt;,</div><div class='add'>+					     &lt;&amp;adma 5&gt;, &lt;&amp;adma 5&gt;,</div><div class='add'>+					     &lt;&amp;adma 6&gt;, &lt;&amp;adma 6&gt;,</div><div class='add'>+					     &lt;&amp;adma 7&gt;, &lt;&amp;adma 7&gt;,</div><div class='add'>+					     &lt;&amp;adma 8&gt;, &lt;&amp;adma 8&gt;,</div><div class='add'>+					     &lt;&amp;adma 9&gt;, &lt;&amp;adma 9&gt;,</div><div class='add'>+					     &lt;&amp;adma 10&gt;, &lt;&amp;adma 10&gt;,</div><div class='add'>+					     &lt;&amp;adma 11&gt;, &lt;&amp;adma 11&gt;,</div><div class='add'>+					     &lt;&amp;adma 12&gt;, &lt;&amp;adma 12&gt;,</div><div class='add'>+					     &lt;&amp;adma 13&gt;, &lt;&amp;adma 13&gt;,</div><div class='add'>+					     &lt;&amp;adma 14&gt;, &lt;&amp;adma 14&gt;,</div><div class='add'>+					     &lt;&amp;adma 15&gt;, &lt;&amp;adma 15&gt;,</div><div class='add'>+					     &lt;&amp;adma 16&gt;, &lt;&amp;adma 16&gt;,</div><div class='add'>+					     &lt;&amp;adma 17&gt;, &lt;&amp;adma 17&gt;,</div><div class='add'>+					     &lt;&amp;adma 18&gt;, &lt;&amp;adma 18&gt;,</div><div class='add'>+					     &lt;&amp;adma 19&gt;, &lt;&amp;adma 19&gt;,</div><div class='add'>+					     &lt;&amp;adma 20&gt;, &lt;&amp;adma 20&gt;,</div><div class='add'>+					     &lt;&amp;adma 21&gt;, &lt;&amp;adma 21&gt;,</div><div class='add'>+					     &lt;&amp;adma 22&gt;, &lt;&amp;adma 22&gt;,</div><div class='add'>+					     &lt;&amp;adma 23&gt;, &lt;&amp;adma 23&gt;,</div><div class='add'>+					     &lt;&amp;adma 24&gt;, &lt;&amp;adma 24&gt;,</div><div class='add'>+					     &lt;&amp;adma 25&gt;, &lt;&amp;adma 25&gt;,</div><div class='add'>+					     &lt;&amp;adma 26&gt;, &lt;&amp;adma 26&gt;,</div><div class='add'>+					     &lt;&amp;adma 27&gt;, &lt;&amp;adma 27&gt;,</div><div class='add'>+					     &lt;&amp;adma 28&gt;, &lt;&amp;adma 28&gt;,</div><div class='add'>+					     &lt;&amp;adma 29&gt;, &lt;&amp;adma 29&gt;,</div><div class='add'>+					     &lt;&amp;adma 30&gt;, &lt;&amp;adma 30&gt;,</div><div class='add'>+					     &lt;&amp;adma 31&gt;, &lt;&amp;adma 31&gt;,</div><div class='add'>+					     &lt;&amp;adma 32&gt;, &lt;&amp;adma 32&gt;;</div><div class='add'>+					dma-names = "rx1", "tx1",</div><div class='add'>+						"rx2", "tx2",</div><div class='add'>+						"rx3", "tx3",</div><div class='add'>+						"rx4", "tx4",</div><div class='add'>+						"rx5", "tx5",</div><div class='add'>+						"rx6", "tx6",</div><div class='add'>+						"rx7", "tx7",</div><div class='add'>+						"rx8", "tx8",</div><div class='add'>+						"rx9", "tx9",</div><div class='add'>+						"rx10", "tx10",</div><div class='add'>+						"rx11", "tx11",</div><div class='add'>+						"rx12", "tx12",</div><div class='add'>+						"rx13", "tx13",</div><div class='add'>+						"rx14", "tx14",</div><div class='add'>+						"rx15", "tx15",</div><div class='add'>+						"rx16", "tx16",</div><div class='add'>+						"rx17", "tx17",</div><div class='add'>+						"rx18", "tx18",</div><div class='add'>+						"rx19", "tx19",</div><div class='add'>+						"rx20", "tx20",</div><div class='add'>+						"rx21", "tx21",</div><div class='add'>+						"rx22", "tx22",</div><div class='add'>+						"rx23", "tx23",</div><div class='add'>+						"rx24", "tx24",</div><div class='add'>+						"rx25", "tx25",</div><div class='add'>+						"rx26", "tx26",</div><div class='add'>+						"rx27", "tx27",</div><div class='add'>+						"rx28", "tx28",</div><div class='add'>+						"rx29", "tx29",</div><div class='add'>+						"rx30", "tx30",</div><div class='add'>+						"rx31", "tx31",</div><div class='add'>+						"rx32", "tx32";</div><div class='add'>+</div><div class='add'>+					 interconnects =</div><div class='add'>+						&lt;&amp;mc TEGRA264_MEMORY_CLIENT_APEDMAR &amp;emc&gt;,</div><div class='add'>+						&lt;&amp;mc TEGRA264_MEMORY_CLIENT_APEDMAW &amp;emc&gt;;</div><div class='add'>+						interconnect-names = "dma-mem", "write";</div><div class='add'>+</div><div class='add'>+					iommus = &lt;&amp;smmu1 TEGRA264_SID_APE&gt;;</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						admaif0_port: port@0 {</div><div class='add'>+							reg = &lt;0x0&gt;;</div><div class='add'>+</div><div class='add'>+							admaif0: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif0&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif1_port: port@1 {</div><div class='add'>+							reg = &lt;0x1&gt;;</div><div class='add'>+</div><div class='add'>+							admaif1: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif1&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif2_port: port@2 {</div><div class='add'>+							reg = &lt;0x2&gt;;</div><div class='add'>+</div><div class='add'>+							admaif2: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif2&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif3_port: port@3 {</div><div class='add'>+							reg = &lt;0x3&gt;;</div><div class='add'>+</div><div class='add'>+							admaif3: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif3&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif4_port: port@4 {</div><div class='add'>+							reg = &lt;0x4&gt;;</div><div class='add'>+</div><div class='add'>+							admaif4: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif4&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif5_port: port@5 {</div><div class='add'>+							reg = &lt;0x5&gt;;</div><div class='add'>+</div><div class='add'>+							admaif5: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif5&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif6_port: port@6 {</div><div class='add'>+							reg = &lt;0x6&gt;;</div><div class='add'>+</div><div class='add'>+							admaif6: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif6&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif7_port: port@7 {</div><div class='add'>+							reg = &lt;0x7&gt;;</div><div class='add'>+</div><div class='add'>+							admaif7: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif7&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif8_port: port@8 {</div><div class='add'>+							reg = &lt;0x8&gt;;</div><div class='add'>+</div><div class='add'>+							admaif8: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif8&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif9_port: port@9 {</div><div class='add'>+							reg = &lt;0x9&gt;;</div><div class='add'>+</div><div class='add'>+							admaif9: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif9&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif10_port: port@a {</div><div class='add'>+							reg = &lt;0xa&gt;;</div><div class='add'>+</div><div class='add'>+							admaif10: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif10&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif11_port: port@b {</div><div class='add'>+							reg = &lt;0xb&gt;;</div><div class='add'>+</div><div class='add'>+							admaif11: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif11&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif12_port: port@c {</div><div class='add'>+							reg = &lt;0xc&gt;;</div><div class='add'>+</div><div class='add'>+							admaif12: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif12&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif13_port: port@d {</div><div class='add'>+							reg = &lt;0xd&gt;;</div><div class='add'>+</div><div class='add'>+							admaif13: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif13&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif14_port: port@e {</div><div class='add'>+							reg = &lt;0xe&gt;;</div><div class='add'>+</div><div class='add'>+							admaif14: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif14&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif15_port: port@f {</div><div class='add'>+							reg = &lt;0xf&gt;;</div><div class='add'>+</div><div class='add'>+							admaif15: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif15&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif16_port: port@10 {</div><div class='add'>+							reg = &lt;0x10&gt;;</div><div class='add'>+</div><div class='add'>+							admaif16: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif16&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif17_port: port@11 {</div><div class='add'>+							reg = &lt;0x11&gt;;</div><div class='add'>+</div><div class='add'>+							admaif17: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif17&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif18_port: port@12 {</div><div class='add'>+							reg = &lt;0x12&gt;;</div><div class='add'>+</div><div class='add'>+							admaif18: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif18&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif19_port: port@13 {</div><div class='add'>+							reg = &lt;0x13&gt;;</div><div class='add'>+</div><div class='add'>+							admaif19: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif19&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif20_port: port@14 {</div><div class='add'>+							reg = &lt;0x14&gt;;</div><div class='add'>+</div><div class='add'>+							admaif20: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif20&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif21_port: port@15 {</div><div class='add'>+							reg = &lt;0x15&gt;;</div><div class='add'>+</div><div class='add'>+							admaif21: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif21&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif22_port: port@16 {</div><div class='add'>+							reg = &lt;0x16&gt;;</div><div class='add'>+</div><div class='add'>+							admaif22: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif22&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif23_port: port@17 {</div><div class='add'>+							reg = &lt;0x17&gt;;</div><div class='add'>+</div><div class='add'>+							admaif23: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif23&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif24_port: port@18 {</div><div class='add'>+							reg = &lt;0x18&gt;;</div><div class='add'>+</div><div class='add'>+							admaif24: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif24&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif25_port: port@19 {</div><div class='add'>+							reg = &lt;0x19&gt;;</div><div class='add'>+</div><div class='add'>+							admaif25: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif25&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif26_port: port@1a {</div><div class='add'>+							reg = &lt;0x1a&gt;;</div><div class='add'>+</div><div class='add'>+							admaif26: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif26&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif27_port: port@1b {</div><div class='add'>+							reg = &lt;0x1b&gt;;</div><div class='add'>+</div><div class='add'>+							admaif27: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif27&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif28_port: port@1c {</div><div class='add'>+							reg = &lt;0x1c&gt;;</div><div class='add'>+</div><div class='add'>+							admaif28: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif28&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif29_port: port@1d {</div><div class='add'>+							reg = &lt;0x1d&gt;;</div><div class='add'>+</div><div class='add'>+							admaif29: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif29&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif30_port: port@1e {</div><div class='add'>+							reg = &lt;0x1e&gt;;</div><div class='add'>+</div><div class='add'>+							admaif30: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif30&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						admaif31_port: port@1f {</div><div class='add'>+							reg = &lt;0x1f&gt;;</div><div class='add'>+</div><div class='add'>+							admaif31: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_admaif31&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_sfc1: sfc@9700000 {</div><div class='add'>+					compatible = "nvidia,tegra264-sfc",</div><div class='add'>+							"nvidia,tegra210-sfc";</div><div class='add'>+					reg = &lt;0x0 0x9700000 0x0 0x10000&gt;;</div><div class='add'>+					sound-name-prefix = "SFC1";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							sfc1_cif_in: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_sfc1_in&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						sfc1_out_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							sfc1_cif_out: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_sfc1_out&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_sfc2: sfc@9710000 {</div><div class='add'>+					compatible = "nvidia,tegra264-sfc",</div><div class='add'>+							"nvidia,tegra210-sfc";</div><div class='add'>+					reg = &lt;0x0 0x9710000 0x0 0x10000&gt;;</div><div class='add'>+					sound-name-prefix = "SFC2";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							sfc2_cif_in: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_sfc2_in&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						sfc2_out_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							sfc2_cif_out: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_sfc2_out&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_sfc3: sfc@9720000 {</div><div class='add'>+					compatible = "nvidia,tegra264-sfc",</div><div class='add'>+							"nvidia,tegra210-sfc";</div><div class='add'>+					reg = &lt;0x0 0x9720000 0x0 0x10000&gt;;</div><div class='add'>+					sound-name-prefix = "SFC3";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							sfc3_cif_in: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_sfc3_in&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						sfc3_out_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							sfc3_cif_out: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_sfc3_out&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_sfc4: sfc@9730000 {</div><div class='add'>+					compatible = "nvidia,tegra264-sfc",</div><div class='add'>+							"nvidia,tegra210-sfc";</div><div class='add'>+					reg = &lt;0x0 0x9730000 0x0 0x10000&gt;;</div><div class='add'>+					sound-name-prefix = "SFC4";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							sfc4_cif_in: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_sfc4_in&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						sfc4_out_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							sfc4_cif_out: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_sfc4_out&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_ope1: processing-engine@9780000 {</div><div class='add'>+					compatible = "nvidia,tegra264-ope",</div><div class='add'>+							"nvidia,tegra210-ope";</div><div class='add'>+					reg = &lt;0x0 0x9780000 0x0 0x10000&gt;;</div><div class='add'>+					#address-cells = &lt;2&gt;;</div><div class='add'>+					#size-cells = &lt;2&gt;;</div><div class='add'>+					ranges = &lt;0x0 0x9780000 0x0 0x9780000 0x0 0x30000&gt;;</div><div class='add'>+					sound-name-prefix = "OPE1";</div><div class='add'>+</div><div class='add'>+					equalizer@9790000 {</div><div class='add'>+						compatible = "nvidia,tegra264-peq",</div><div class='add'>+								"nvidia,tegra210-peq";</div><div class='add'>+						reg = &lt;0x0 0x9790000 0x0 0x10000&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					dynamic-range-compressor@97a0000 {</div><div class='add'>+						compatible = "nvidia,tegra264-mbdrc",</div><div class='add'>+								"nvidia,tegra210-mbdrc";</div><div class='add'>+						reg = &lt;0x0 0x97a0000 0x0 0x10000&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0x0&gt;;</div><div class='add'>+</div><div class='add'>+							ope1_cif_in_ep: endpoint {</div><div class='add'>+								remote-endpoint =</div><div class='add'>+									&lt;&amp;xbar_ope1_in_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						ope1_out_port: port@1 {</div><div class='add'>+							reg = &lt;0x1&gt;;</div><div class='add'>+</div><div class='add'>+							ope1_cif_out_ep: endpoint {</div><div class='add'>+								remote-endpoint =</div><div class='add'>+									&lt;&amp;xbar_ope1_out_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_mvc1: mvc@9800000 {</div><div class='add'>+					compatible = "nvidia,tegra264-mvc",</div><div class='add'>+							"nvidia,tegra210-mvc";</div><div class='add'>+					reg = &lt;0x0 0x9800000 0x0 0x10000&gt;;</div><div class='add'>+					sound-name-prefix = "MVC1";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							mvc1_cif_in: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mvc1_in&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						mvc1_out_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							mvc1_cif_out: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mvc1_out&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_mvc2: mvc@9810000 {</div><div class='add'>+					compatible = "nvidia,tegra264-mvc",</div><div class='add'>+							"nvidia,tegra210-mvc";</div><div class='add'>+					reg = &lt;0x0 0x9810000 0x0 0x10000&gt;;</div><div class='add'>+					sound-name-prefix = "MVC2";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+							mvc2_cif_in: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mvc2_in&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						mvc2_out_port: port@1 {</div><div class='add'>+							reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+							mvc2_cif_out: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mvc2_out&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_amixer: amixer@9820000 {</div><div class='add'>+					compatible = "nvidia,tegra264-amixer",</div><div class='add'>+							"nvidia,tegra210-amixer";</div><div class='add'>+					reg = &lt;0x0 0x9820000 0x0 0x10000&gt;;</div><div class='add'>+					sound-name-prefix = "MIXER1";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0x0&gt;;</div><div class='add'>+</div><div class='add'>+							mix_in1: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mix_in1&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@1 {</div><div class='add'>+							reg = &lt;0x1&gt;;</div><div class='add'>+</div><div class='add'>+							mix_in2: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mix_in2&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@2 {</div><div class='add'>+							reg = &lt;0x2&gt;;</div><div class='add'>+</div><div class='add'>+							mix_in3: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mix_in3&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@3 {</div><div class='add'>+							reg = &lt;0x3&gt;;</div><div class='add'>+</div><div class='add'>+							mix_in4: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mix_in4&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@4 {</div><div class='add'>+							reg = &lt;0x4&gt;;</div><div class='add'>+</div><div class='add'>+							mix_in5: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mix_in5&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@5 {</div><div class='add'>+							reg = &lt;0x5&gt;;</div><div class='add'>+</div><div class='add'>+							mix_in6: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mix_in6&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@6 {</div><div class='add'>+							reg = &lt;0x6&gt;;</div><div class='add'>+</div><div class='add'>+							mix_in7: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mix_in7&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@7 {</div><div class='add'>+							reg = &lt;0x7&gt;;</div><div class='add'>+</div><div class='add'>+							mix_in8: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mix_in8&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@8 {</div><div class='add'>+							reg = &lt;0x8&gt;;</div><div class='add'>+</div><div class='add'>+							mix_in9: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mix_in9&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@9 {</div><div class='add'>+							reg = &lt;0x9&gt;;</div><div class='add'>+</div><div class='add'>+							mix_in10: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mix_in10&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						mix_out1_port: port@a {</div><div class='add'>+							reg = &lt;0xa&gt;;</div><div class='add'>+</div><div class='add'>+							mix_out1: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mix_out1&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						mix_out2_port: port@b {</div><div class='add'>+							reg = &lt;0xb&gt;;</div><div class='add'>+</div><div class='add'>+							mix_out2: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mix_out2&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						mix_out3_port: port@c {</div><div class='add'>+							reg = &lt;0xc&gt;;</div><div class='add'>+</div><div class='add'>+							mix_out3: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mix_out3&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						mix_out4_port: port@d {</div><div class='add'>+							reg = &lt;0xd&gt;;</div><div class='add'>+</div><div class='add'>+							mix_out4: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mix_out4&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						mix_out5_port: port@e {</div><div class='add'>+							reg = &lt;0xe&gt;;</div><div class='add'>+</div><div class='add'>+							mix_out5: endpoint {</div><div class='add'>+								remote-endpoint = &lt;&amp;xbar_mix_out5&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tegra_asrc: asrc@9850000 {</div><div class='add'>+					compatible = "nvidia,tegra264-asrc";</div><div class='add'>+					reg = &lt;0x0 0x9850000 0x0 0x10000&gt;;</div><div class='add'>+					sound-name-prefix = "ASRC1";</div><div class='add'>+</div><div class='add'>+					ports {</div><div class='add'>+						#address-cells = &lt;1&gt;;</div><div class='add'>+						#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						port@0 {</div><div class='add'>+							reg = &lt;0x0&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_in1_ep: endpoint {</div><div class='add'>+								remote-endpoint =</div><div class='add'>+									&lt;&amp;xbar_asrc_in1_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@1 {</div><div class='add'>+							reg = &lt;0x1&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_in2_ep: endpoint {</div><div class='add'>+								remote-endpoint =</div><div class='add'>+									&lt;&amp;xbar_asrc_in2_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@2 {</div><div class='add'>+							reg = &lt;0x2&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_in3_ep: endpoint {</div><div class='add'>+								remote-endpoint =</div><div class='add'>+									&lt;&amp;xbar_asrc_in3_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@3 {</div><div class='add'>+							reg = &lt;0x3&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_in4_ep: endpoint {</div><div class='add'>+								remote-endpoint =</div><div class='add'>+									&lt;&amp;xbar_asrc_in4_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@4 {</div><div class='add'>+							reg = &lt;0x4&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_in5_ep: endpoint {</div><div class='add'>+								remote-endpoint =</div><div class='add'>+									&lt;&amp;xbar_asrc_in5_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@5 {</div><div class='add'>+							reg = &lt;0x5&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_in6_ep: endpoint {</div><div class='add'>+								remote-endpoint =</div><div class='add'>+									&lt;&amp;xbar_asrc_in6_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						port@6 {</div><div class='add'>+							reg = &lt;0x6&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_in7_ep: endpoint {</div><div class='add'>+								remote-endpoint =</div><div class='add'>+									&lt;&amp;xbar_asrc_in7_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						asrc_out1_port: port@7 {</div><div class='add'>+							reg = &lt;0x7&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_out1_ep: endpoint {</div><div class='add'>+								remote-endpoint =</div><div class='add'>+									&lt;&amp;xbar_asrc_out1_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						asrc_out2_port: port@8 {</div><div class='add'>+							reg = &lt;0x8&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_out2_ep: endpoint {</div><div class='add'>+								remote-endpoint =</div><div class='add'>+									&lt;&amp;xbar_asrc_out2_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						asrc_out3_port: port@9 {</div><div class='add'>+							reg = &lt;0x9&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_out3_ep: endpoint {</div><div class='add'>+								remote-endpoint =</div><div class='add'>+									&lt;&amp;xbar_asrc_out3_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						asrc_out4_port: port@a {</div><div class='add'>+							reg = &lt;0xa&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_out4_ep: endpoint {</div><div class='add'>+								remote-endpoint =</div><div class='add'>+									&lt;&amp;xbar_asrc_out4_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						asrc_out5_port: port@b {</div><div class='add'>+							reg = &lt;0xb&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_out5_ep: endpoint {</div><div class='add'>+								remote-endpoint =</div><div class='add'>+									&lt;&amp;xbar_asrc_out5_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						asrc_out6_port:	port@c {</div><div class='add'>+							reg = &lt;0xc&gt;;</div><div class='add'>+</div><div class='add'>+							asrc_out6_ep: endpoint {</div><div class='add'>+								remote-endpoint =</div><div class='add'>+									&lt;&amp;xbar_asrc_out6_ep&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0x0&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif0: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif0&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;0x1&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif1: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif1&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@2 {</div><div class='add'>+						reg = &lt;0x2&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif2: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif2&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@3 {</div><div class='add'>+						reg = &lt;0x3&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif3: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif3&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@4 {</div><div class='add'>+						reg = &lt;0x4&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif4: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif4&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@5 {</div><div class='add'>+						reg = &lt;0x5&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif5: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif5&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@6 {</div><div class='add'>+						reg = &lt;0x6&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif6: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif6&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@7 {</div><div class='add'>+						reg = &lt;0x7&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif7: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif7&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@8 {</div><div class='add'>+						reg = &lt;0x8&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif8: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif8&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@9 {</div><div class='add'>+						reg = &lt;0x9&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif9: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif9&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@a {</div><div class='add'>+						reg = &lt;0xa&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif10: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif10&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@b {</div><div class='add'>+						reg = &lt;0xb&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif11: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif11&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@c {</div><div class='add'>+						reg = &lt;0xc&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif12: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif12&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@d {</div><div class='add'>+						reg = &lt;0xd&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif13: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif13&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@e {</div><div class='add'>+						reg = &lt;0xe&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif14: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif14&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@f {</div><div class='add'>+						reg = &lt;0xf&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif15: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif15&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@10 {</div><div class='add'>+						reg = &lt;0x10&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif16: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif16&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@11 {</div><div class='add'>+						reg = &lt;0x11&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif17: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif17&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@12 {</div><div class='add'>+						reg = &lt;0x12&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif18: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif18&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@13 {</div><div class='add'>+						reg = &lt;0x13&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif19: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif19&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@14 {</div><div class='add'>+						reg = &lt;0x14&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif20: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif20&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@15 {</div><div class='add'>+						reg = &lt;0x15&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif21: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif21&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@16 {</div><div class='add'>+						reg = &lt;0x16&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif22: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif22&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@17 {</div><div class='add'>+						reg = &lt;0x17&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif23: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif23&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@18 {</div><div class='add'>+						reg = &lt;0x18&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif24: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif24&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@19 {</div><div class='add'>+						reg = &lt;0x19&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif25: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif25&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1a {</div><div class='add'>+						reg = &lt;0x1a&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif26: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif26&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1b {</div><div class='add'>+						reg = &lt;0x1b&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif27: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif27&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1c {</div><div class='add'>+						reg = &lt;0x1c&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif28: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif28&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1d {</div><div class='add'>+						reg = &lt;0x1d&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif29: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif29&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1e {</div><div class='add'>+						reg = &lt;0x1e&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif30: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif30&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1f {</div><div class='add'>+						reg = &lt;0x1f&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_admaif31: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;admaif31&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_i2s1_port: port@20 {</div><div class='add'>+						reg = &lt;0x20&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_i2s1: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;i2s1_cif&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_i2s2_port: port@21 {</div><div class='add'>+						reg = &lt;0x21&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_i2s2: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;i2s2_cif&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_i2s3_port: port@22 {</div><div class='add'>+						reg = &lt;0x22&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_i2s3: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;i2s3_cif&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_i2s4_port: port@23 {</div><div class='add'>+						reg = &lt;0x23&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_i2s4: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;i2s4_cif&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_i2s5_port: port@24 {</div><div class='add'>+						reg = &lt;0x24&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_i2s5: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;i2s5_cif&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_i2s6_port: port@25 {</div><div class='add'>+						reg = &lt;0x25&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_i2s6: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;i2s6_cif&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_i2s7_port: port@26 {</div><div class='add'>+						reg = &lt;0x26&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_i2s7: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;i2s7_cif&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_i2s8_port: port@27 {</div><div class='add'>+						reg = &lt;0x27&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_i2s8: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;i2s8_cif&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_dmic1_port: port@28 {</div><div class='add'>+						reg = &lt;0x28&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_dmic1: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;dmic1_cif&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_dmic2_port: port@29 {</div><div class='add'>+						reg = &lt;0x29&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_dmic2: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;dmic2_cif&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_dspk1_port: port@2a {</div><div class='add'>+						reg = &lt;0x2a&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_dspk1: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;dspk1_cif&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_sfc1_in_port: port@2b {</div><div class='add'>+						reg = &lt;0x2b&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_sfc1_in: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;sfc1_cif_in&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@2c {</div><div class='add'>+						reg = &lt;0x2c&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_sfc1_out: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;sfc1_cif_out&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_sfc2_in_port: port@2d {</div><div class='add'>+						reg = &lt;0x2d&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_sfc2_in: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;sfc2_cif_in&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@2e {</div><div class='add'>+						reg = &lt;0x2e&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_sfc2_out: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;sfc2_cif_out&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_sfc3_in_port: port@2f {</div><div class='add'>+						reg = &lt;0x2f&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_sfc3_in: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;sfc3_cif_in&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@30 {</div><div class='add'>+						reg = &lt;0x30&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_sfc3_out: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;sfc3_cif_out&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_sfc4_in_port: port@31 {</div><div class='add'>+						reg = &lt;0x31&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_sfc4_in: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;sfc4_cif_in&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@32 {</div><div class='add'>+						reg = &lt;0x32&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_sfc4_out: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;sfc4_cif_out&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mvc1_in_port: port@33 {</div><div class='add'>+						reg = &lt;0x33&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mvc1_in: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mvc1_cif_in&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@34 {</div><div class='add'>+						reg = &lt;0x34&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mvc1_out: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mvc1_cif_out&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mvc2_in_port: port@35 {</div><div class='add'>+						reg = &lt;0x35&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mvc2_in: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mvc2_cif_in&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@36 {</div><div class='add'>+						reg = &lt;0x36&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mvc2_out: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mvc2_cif_out&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx1_in1_port: port@37 {</div><div class='add'>+						reg = &lt;0x37&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx1_in1: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx1_in1&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx1_in2_port: port@38 {</div><div class='add'>+						reg = &lt;0x38&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx1_in2: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx1_in2&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx1_in3_port: port@39 {</div><div class='add'>+						reg = &lt;0x39&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx1_in3: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx1_in3&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx1_in4_port: port@3a {</div><div class='add'>+						reg = &lt;0x3a&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx1_in4: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx1_in4&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@3b {</div><div class='add'>+						reg = &lt;0x3b&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx1_out: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx1_out&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx2_in1_port: port@3c {</div><div class='add'>+						reg = &lt;0x3c&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx2_in1: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx2_in1&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx2_in2_port: port@3d {</div><div class='add'>+						reg = &lt;0x3d&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx2_in2: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx2_in2&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx2_in3_port: port@3e {</div><div class='add'>+						reg = &lt;0x3e&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx2_in3: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx2_in3&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx2_in4_port: port@3f {</div><div class='add'>+						reg = &lt;0x3f&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx2_in4: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx2_in4&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@40 {</div><div class='add'>+						reg = &lt;0x40&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx2_out: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx2_out&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx3_in1_port: port@41 {</div><div class='add'>+						reg = &lt;0x41&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx3_in1: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx3_in1&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx3_in2_port: port@42 {</div><div class='add'>+						reg = &lt;0x42&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx3_in2: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx3_in2&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx3_in3_port: port@43 {</div><div class='add'>+						reg = &lt;0x43&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx3_in3: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx3_in3&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx3_in4_port: port@44 {</div><div class='add'>+						reg = &lt;0x44&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx3_in4: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx3_in4&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@45 {</div><div class='add'>+						reg = &lt;0x45&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx3_out: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx3_out&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx4_in1_port: port@46 {</div><div class='add'>+						reg = &lt;0x46&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx4_in1: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx4_in1&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx4_in2_port: port@47 {</div><div class='add'>+						reg = &lt;0x47&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx4_in2: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx4_in2&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx4_in3_port: port@48 {</div><div class='add'>+						reg = &lt;0x48&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx4_in3: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx4_in3&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx4_in4_port: port@49 {</div><div class='add'>+						reg = &lt;0x49&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx4_in4: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx4_in4&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@4a {</div><div class='add'>+						reg = &lt;0x4a&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx4_out: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx4_out&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx5_in1_port: port@4b {</div><div class='add'>+						reg = &lt;0x4b&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx5_in1: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx5_in1&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx5_in2_port: port@4c {</div><div class='add'>+						reg = &lt;0x4c&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx5_in2: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx5_in2&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx5_in3_port: port@4d {</div><div class='add'>+						reg = &lt;0x4d&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx5_in3: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx5_in3&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx5_in4_port: port@4e {</div><div class='add'>+						reg = &lt;0x4e&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx5_in4: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx5_in4&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@4f {</div><div class='add'>+						reg = &lt;0x4f&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx5_out: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx5_out&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx6_in1_port: port@50 {</div><div class='add'>+						reg = &lt;0x50&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx6_in1: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx6_in1&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx6_in2_port: port@51 {</div><div class='add'>+						reg = &lt;0x51&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx6_in2: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx6_in2&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx6_in3_port: port@52 {</div><div class='add'>+						reg = &lt;0x52&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx6_in3: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx6_in3&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_amx6_in4_port: port@53 {</div><div class='add'>+						reg = &lt;0x53&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx6_in4: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx6_in4&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@54 {</div><div class='add'>+						reg = &lt;0x54&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_amx6_out: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;amx6_out&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_adx1_in_port: port@55 {</div><div class='add'>+						reg = &lt;0x55&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx1_in: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx1_in&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@56 {</div><div class='add'>+						reg = &lt;0x56&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx1_out1: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx1_out1&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@57 {</div><div class='add'>+						reg = &lt;0x57&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx1_out2: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx1_out2&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@58 {</div><div class='add'>+						reg = &lt;0x58&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx1_out3: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx1_out3&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@59 {</div><div class='add'>+						reg = &lt;0x59&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx1_out4: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx1_out4&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_adx2_in_port: port@5a {</div><div class='add'>+						reg = &lt;0x5a&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx2_in: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx2_in&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@5b {</div><div class='add'>+						reg = &lt;0x5b&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx2_out1: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx2_out1&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@5c {</div><div class='add'>+						reg = &lt;0x5c&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx2_out2: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx2_out2&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@5d {</div><div class='add'>+						reg = &lt;0x5d&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx2_out3: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx2_out3&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@5e {</div><div class='add'>+						reg = &lt;0x5e&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx2_out4: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx2_out4&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_adx3_in_port: port@5f {</div><div class='add'>+						reg = &lt;0x5f&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx3_in: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx3_in&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@60 {</div><div class='add'>+						reg = &lt;0x60&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx3_out1: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx3_out1&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@61 {</div><div class='add'>+						reg = &lt;0x61&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx3_out2: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx3_out2&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@62 {</div><div class='add'>+						reg = &lt;0x62&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx3_out3: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx3_out3&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@63 {</div><div class='add'>+						reg = &lt;0x63&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx3_out4: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx3_out4&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_adx4_in_port: port@64 {</div><div class='add'>+						reg = &lt;0x64&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx4_in: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx4_in&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@65 {</div><div class='add'>+						reg = &lt;0x65&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx4_out1: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx4_out1&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@66 {</div><div class='add'>+						reg = &lt;0x66&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx4_out2: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx4_out2&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@67 {</div><div class='add'>+						reg = &lt;0x67&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx4_out3: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx4_out3&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@68 {</div><div class='add'>+						reg = &lt;0x68&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx4_out4: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx4_out4&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_adx5_in_port: port@69 {</div><div class='add'>+						reg = &lt;0x69&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx5_in: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx5_in&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@6a {</div><div class='add'>+						reg = &lt;0x6a&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx5_out1: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx5_out1&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@6b {</div><div class='add'>+						reg = &lt;0x6b&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx5_out2: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx5_out2&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@6c {</div><div class='add'>+						reg = &lt;0x6c&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx5_out3: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx5_out3&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@6d {</div><div class='add'>+						reg = &lt;0x6d&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx5_out4: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx5_out4&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_adx6_in_port: port@6e {</div><div class='add'>+						reg = &lt;0x6e&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx6_in: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx6_in&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@6f {</div><div class='add'>+						reg = &lt;0x6f&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx6_out1: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx6_out1&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@70 {</div><div class='add'>+						reg = &lt;0x70&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx6_out2: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx6_out2&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@71 {</div><div class='add'>+						reg = &lt;0x71&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx6_out3: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx6_out3&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@72 {</div><div class='add'>+						reg = &lt;0x72&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_adx6_out4: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;adx6_out4&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mix_in1_port: port@73 {</div><div class='add'>+						reg = &lt;0x73&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mix_in1: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mix_in1&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mix_in2_port: port@74 {</div><div class='add'>+						reg = &lt;0x74&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mix_in2: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mix_in2&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mix_in3_port: port@75 {</div><div class='add'>+						reg = &lt;0x75&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mix_in3: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mix_in3&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mix_in4_port: port@76 {</div><div class='add'>+						reg = &lt;0x76&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mix_in4: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mix_in4&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mix_in5_port: port@77 {</div><div class='add'>+						reg = &lt;0x77&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mix_in5: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mix_in5&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mix_in6_port: port@78 {</div><div class='add'>+						reg = &lt;0x78&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mix_in6: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mix_in6&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mix_in7_port: port@79 {</div><div class='add'>+						reg = &lt;0x79&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mix_in7: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mix_in7&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mix_in8_port: port@7a {</div><div class='add'>+						reg = &lt;0x7a&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mix_in8: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mix_in8&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mix_in9_port: port@7b {</div><div class='add'>+						reg = &lt;0x7b&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mix_in9: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mix_in9&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_mix_in10_port: port@7c {</div><div class='add'>+						reg = &lt;0x7c&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mix_in10: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mix_in10&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@7d {</div><div class='add'>+						reg = &lt;0x7d&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mix_out1: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mix_out1&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@7e {</div><div class='add'>+						reg = &lt;0x7e&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mix_out2: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mix_out2&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@7f {</div><div class='add'>+						reg = &lt;0x7f&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mix_out3: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mix_out3&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@80 {</div><div class='add'>+						reg = &lt;0x80&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mix_out4: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mix_out4&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@81 {</div><div class='add'>+						reg = &lt;0x81&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_mix_out5: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mix_out5&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_asrc_in1_port: port@82 {</div><div class='add'>+						reg = &lt;0x82&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_in1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_in1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@83 {</div><div class='add'>+						reg = &lt;0x83&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_out1_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_out1_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_asrc_in2_port: port@84 {</div><div class='add'>+						reg = &lt;0x84&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_in2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_in2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@85 {</div><div class='add'>+						reg = &lt;0x85&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_out2_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_out2_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_asrc_in3_port: port@86 {</div><div class='add'>+						reg = &lt;0x86&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_in3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_in3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@87 {</div><div class='add'>+						reg = &lt;0x87&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_out3_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_out3_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_asrc_in4_port: port@88 {</div><div class='add'>+						reg = &lt;0x88&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_in4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_in4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@89 {</div><div class='add'>+						reg = &lt;0x89&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_out4_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_out4_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_asrc_in5_port: port@8a {</div><div class='add'>+						reg = &lt;0x8a&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_in5_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_in5_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@8b {</div><div class='add'>+						reg = &lt;0x8b&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_out5_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_out5_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_asrc_in6_port: port@8c {</div><div class='add'>+						reg = &lt;0x8c&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_in6_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_in6_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@8d {</div><div class='add'>+						reg = &lt;0x8d&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_out6_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_out6_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_asrc_in7_port: port@8e {</div><div class='add'>+						reg = &lt;0x8e&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_asrc_in7_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;asrc_in7_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					xbar_ope1_in_port: port@8f {</div><div class='add'>+						reg = &lt;0x8f&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_ope1_in_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;ope1_cif_in_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@90 {</div><div class='add'>+						reg = &lt;0x90&gt;;</div><div class='add'>+</div><div class='add'>+						xbar_ope1_out_ep: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;ope1_cif_out_ep&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			agic_page0: interrupt-controller@9960000 {</div><div class='add'>+				compatible = "nvidia,tegra264-agic",</div><div class='add'>+						"nvidia,tegra210-agic";</div><div class='add'>+				#interrupt-cells = &lt;3&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				reg = &lt;0x0 0x9961000 0x0 0x1000&gt;,</div><div class='add'>+					&lt;0x0 0x9962000 0x0 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 0x230</div><div class='add'>+					(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='add'>+				clocks = &lt;&amp;bpmp TEGRA264_CLK_ADSP&gt;;</div><div class='add'>+				clock-names = "clk";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			agic_page1: interrupt-controller@9970000 {</div><div class='add'>+				compatible = "nvidia,tegra264-agic",</div><div class='add'>+					   "nvidia,tegra210-agic";</div><div class='add'>+				#interrupt-cells = &lt;3&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				reg = &lt;0x0 0x9971000 0x0 0x1000&gt;,</div><div class='add'>+					&lt;0x0 0x9972000 0x0 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 0x231</div><div class='add'>+					(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='add'>+				clocks = &lt;&amp;bpmp TEGRA264_CLK_ADSP&gt;;</div><div class='add'>+				clock-names = "clk";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			agic_page2: interrupt-controller@9980000 {</div><div class='add'>+				compatible = "nvidia,tegra264-agic",</div><div class='add'>+						"nvidia,tegra210-agic";</div><div class='add'>+				#interrupt-cells = &lt;3&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				reg = &lt;0x0 0x9981000 0x0 0x1000&gt;,</div><div class='add'>+					&lt;0x0 0x9982000 0x0 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 0x232</div><div class='add'>+					(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='add'>+				clocks = &lt;&amp;bpmp TEGRA264_CLK_ADSP&gt;;</div><div class='add'>+				clock-names = "clk";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			agic_page3: interrupt-controller@9990000 {</div><div class='add'>+				compatible = "nvidia,tegra264-agic",</div><div class='add'>+						"nvidia,tegra210-agic";</div><div class='add'>+				#interrupt-cells = &lt;3&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				reg = &lt;0x0 0x9991000 0x0 0x1000&gt;,</div><div class='add'>+					&lt;0x0 0x9992000 0x0 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 0x233</div><div class='add'>+					(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='add'>+				clocks = &lt;&amp;bpmp TEGRA264_CLK_ADSP&gt;;</div><div class='add'>+				clock-names = "clk";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			agic_page4: interrupt-controller@99a0000 {</div><div class='add'>+				compatible = "nvidia,tegra264-agic",</div><div class='add'>+						"nvidia,tegra210-agic";</div><div class='add'>+				#interrupt-cells = &lt;3&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				reg = &lt;0x0 0x99a1000 0x0 0x1000&gt;,</div><div class='add'>+					&lt;0x0 0x99a2000 0x0 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 0x234</div><div class='add'>+					(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='add'>+				clocks = &lt;&amp;bpmp TEGRA264_CLK_ADSP&gt;;</div><div class='add'>+				clock-names = "clk";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			agic_page5: interrupt-controller@99b0000 {</div><div class='add'>+				compatible = "nvidia,tegra264-agic",</div><div class='add'>+						"nvidia,tegra210-agic";</div><div class='add'>+				#interrupt-cells = &lt;3&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				reg = &lt;0x0 0x99b1000 0x0 0x1000&gt;,</div><div class='add'>+					&lt;0x0 0x99b2000 0x0 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 0x235</div><div class='add'>+					(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='add'>+				clocks = &lt;&amp;bpmp TEGRA264_CLK_ADSP&gt;;</div><div class='add'>+				clock-names = "clk";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpcdma: dma-controller@8400000 {</div><div class='add'>+			compatible = "nvidia,tegra264-gpcdma", "nvidia,tegra186-gpcdma";</div><div class='add'>+			reg = &lt;0x0 0x08400000 0x0 0x210000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 615 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+			iommus = &lt;&amp;smmu1 0x00000800&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+			dma-channel-mask = &lt;0xfffffffe&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		hsp_top: hsp@8800000 {</div><div class='add'>+			compatible = "nvidia,tegra264-hsp";</div><div class='add'>+			reg = &lt;0x0 0x08800000 0x0 0xd0000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 622 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 623 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 624 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 626 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "doorbell", "shared0", "shared1", "shared2",</div><div class='add'>+					  "shared3", "shared4", "shared5", "shared6",</div><div class='add'>+					  "shared7";</div><div class='add'>+			#mbox-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rtc: rtc@c2c0000 {</div><div class='add'>+			compatible = "nvidia,tegra264-rtc", "nvidia,tegra20-rtc";</div><div class='add'>+			reg = &lt;0x0 0x0c2c0000 0x0 0x10000&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;pmc&gt;;</div><div class='add'>+			interrupts = &lt;65 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA264_CLK_CLK_S&gt;;</div><div class='add'>+			clock-names = "rtc";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		serial@c4e0000 {</div><div class='add'>+			compatible = "nvidia,tegra264-utc";</div><div class='add'>+			reg = &lt;0x0 0x0c4e0000 0x0 0x8000&gt;,</div><div class='add'>+			      &lt;0x0 0x0c4e8000 0x0 0x8000&gt;;</div><div class='add'>+			reg-names = "tx", "rx";</div><div class='add'>+			interrupts = &lt;GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			rx-threshold = &lt;4&gt;;</div><div class='add'>+			tx-threshold = &lt;4&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		serial@c5a0000 {</div><div class='add'>+			compatible = "nvidia,tegra264-utc";</div><div class='add'>+			reg = &lt;0x0 0x0c5a0000 0x0 0x8000&gt;,</div><div class='add'>+			      &lt;0x0 0x0c5a8000 0x0 0x8000&gt;;</div><div class='add'>+			reg-names = "tx", "rx";</div><div class='add'>+			interrupts = &lt;GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			rx-threshold = &lt;4&gt;;</div><div class='add'>+			tx-threshold = &lt;4&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uart0: serial@c5f0000 {</div><div class='add'>+			compatible = "arm,sbsa-uart";</div><div class='add'>+			reg = &lt;0x0 0x0c5f0000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c2: i2c@c600000 {</div><div class='add'>+			compatible = "nvidia,tegra264-i2c";</div><div class='add'>+			reg = &lt;0x0 0x0c600000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clock-frequency = &lt;400000&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA264_CLK_AON_I2C&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA264_CLK_PLLAON&gt;;</div><div class='add'>+			clock-names = "div-clk", "parent";</div><div class='add'>+			assigned-clocks = &lt;&amp;bpmp TEGRA264_CLK_AON_I2C&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;bpmp TEGRA264_CLK_PLLAON&gt;;</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA264_RESET_I2C2&gt;;</div><div class='add'>+			reset-names = "i2c";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c3: i2c@c610000 {</div><div class='add'>+			compatible = "nvidia,tegra264-i2c";</div><div class='add'>+			reg = &lt;0x0 0x0c610000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clock-frequency = &lt;400000&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA264_CLK_AON_I2C&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA264_CLK_PLLAON&gt;;</div><div class='add'>+			clock-names = "div-clk", "parent";</div><div class='add'>+			assigned-clocks = &lt;&amp;bpmp TEGRA264_CLK_AON_I2C&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;bpmp TEGRA264_CLK_PLLAON&gt;;</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA264_RESET_I2C3&gt;;</div><div class='add'>+			reset-names = "i2c";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmc: pmc@c800000 {</div><div class='add'>+			compatible = "nvidia,tegra264-pmc";</div><div class='add'>+			reg = &lt;0x0 0x0c800000 0x0 0x100000&gt;,</div><div class='add'>+			      &lt;0x0 0x0c990000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0x0ca00000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0x0c980000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0x0c9c0000 0x0 0x40000&gt;;</div><div class='add'>+			reg-names = "pmc", "wake", "aotag", "scratch", "misc";</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* TOP_MMIO */</div><div class='add'>+	bus@8100000000 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		ranges = &lt;0x00 0x00000000 0x81 0x00000000 0x01 0x00000000&gt;, /* MMIO */</div><div class='add'>+			 &lt;0x01 0x00000000 0x00 0x20000000 0x00 0x40000000&gt;, /* non-prefetchable memory (32-bit) */</div><div class='add'>+			 &lt;0x02 0x00000000 0xd0 0x00000000 0x08 0x80000000&gt;; /* ECAM, prefetchable memory, I/O */</div><div class='add'>+</div><div class='add'>+		smmu1: iommu@5000000 {</div><div class='add'>+			compatible = "arm,smmu-v3";</div><div class='add'>+			reg = &lt;0x00 0x5000000 0x0 0x200000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 12 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 13 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			interrupt-names = "eventq", "gerror";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			#iommu-cells = &lt;1&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smmu2: iommu@6000000 {</div><div class='add'>+			compatible = "arm,smmu-v3";</div><div class='add'>+			reg = &lt;0x00 0x6000000 0x0 0x200000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 1 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 2 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			interrupt-names = "eventq", "gerror";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			#iommu-cells = &lt;1&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mc: memory-controller@8020000 {</div><div class='add'>+			compatible = "nvidia,tegra264-mc";</div><div class='add'>+			reg = &lt;0x00 0x8020000 0x0 0x20000&gt;, /* MC broadcast */</div><div class='add'>+			      &lt;0x00 0x8040000 0x0 0x20000&gt;, /* MC  0 */</div><div class='add'>+			      &lt;0x00 0x8060000 0x0 0x20000&gt;, /* MC  1 */</div><div class='add'>+			      &lt;0x00 0x8080000 0x0 0x20000&gt;, /* MC  2 */</div><div class='add'>+			      &lt;0x00 0x80a0000 0x0 0x20000&gt;, /* MC  3 */</div><div class='add'>+			      &lt;0x00 0x80c0000 0x0 0x20000&gt;, /* MC  4 */</div><div class='add'>+			      &lt;0x00 0x80e0000 0x0 0x20000&gt;, /* MC  5 */</div><div class='add'>+			      &lt;0x00 0x8100000 0x0 0x20000&gt;, /* MC  6 */</div><div class='add'>+			      &lt;0x00 0x8120000 0x0 0x20000&gt;, /* MC  7 */</div><div class='add'>+			      &lt;0x00 0x8140000 0x0 0x20000&gt;, /* MC  8 */</div><div class='add'>+			      &lt;0x00 0x8160000 0x0 0x20000&gt;, /* MC  9 */</div><div class='add'>+			      &lt;0x00 0x8180000 0x0 0x20000&gt;, /* MC 10 */</div><div class='add'>+			      &lt;0x00 0x81a0000 0x0 0x20000&gt;, /* MC 11 */</div><div class='add'>+			      &lt;0x00 0x81c0000 0x0 0x20000&gt;, /* MC 12 */</div><div class='add'>+			      &lt;0x00 0x81e0000 0x0 0x20000&gt;, /* MC 13 */</div><div class='add'>+			      &lt;0x00 0x8200000 0x0 0x20000&gt;, /* MC 14 */</div><div class='add'>+			      &lt;0x00 0x8220000 0x0 0x20000&gt;; /* MC 15 */</div><div class='add'>+			reg-names = "broadcast", "ch0", "ch1", "ch2", "ch3",</div><div class='add'>+				    "ch4", "ch5", "ch6", "ch7", "ch8", "ch9",</div><div class='add'>+				    "ch10", "ch11", "ch12", "ch13", "ch14",</div><div class='add'>+				    "ch15";</div><div class='add'>+			interrupts = &lt;GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#interconnect-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			/* limit the DMA range for memory clients to [39:0] */</div><div class='add'>+			dma-ranges = &lt;0x0 0x0 0x0 0x0 0x100 0x0&gt;;</div><div class='add'>+</div><div class='add'>+			emc: external-memory-controller@8800000 {</div><div class='add'>+				compatible = "nvidia,tegra264-emc";</div><div class='add'>+				reg = &lt;0x00 0x8800000 0x0 0x20000&gt;,</div><div class='add'>+				      &lt;0x00 0x8890000 0x0 0x20000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;bpmp TEGRA264_CLK_EMC&gt;;</div><div class='add'>+				clock-names = "emc";</div><div class='add'>+</div><div class='add'>+				#interconnect-cells = &lt;0&gt;;</div><div class='add'>+				nvidia,bpmp = &lt;&amp;bpmp&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smmu0: iommu@a000000 {</div><div class='add'>+			compatible = "arm,smmu-v3";</div><div class='add'>+			reg = &lt;0x00 0xa000000 0x0 0x200000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 21 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 22 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			interrupt-names = "eventq", "gerror";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			#iommu-cells = &lt;1&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smmu4: iommu@b000000 {</div><div class='add'>+			compatible = "arm,smmu-v3";</div><div class='add'>+			reg = &lt;0x00 0xb000000 0x0 0x200000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 30 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 31 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			interrupt-names = "eventq", "gerror";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			#iommu-cells = &lt;1&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c14: i2c@c410000 {</div><div class='add'>+			compatible = "nvidia,tegra264-i2c";</div><div class='add'>+			reg = &lt;0x00 0x0c410000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clock-frequency = &lt;400000&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA264_CLK_TOP_I2C&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA264_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			clock-names = "div-clk", "parent";</div><div class='add'>+			assigned-clocks = &lt;&amp;bpmp TEGRA264_CLK_TOP_I2C&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;bpmp TEGRA264_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA264_RESET_I2C14&gt;;</div><div class='add'>+			reset-names = "i2c";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c15: i2c@c420000 {</div><div class='add'>+			compatible = "nvidia,tegra264-i2c";</div><div class='add'>+			reg = &lt;0x00 0x0c420000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clock-frequency = &lt;400000&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA264_CLK_TOP_I2C&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA264_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			clock-names = "div-clk", "parent";</div><div class='add'>+			assigned-clocks = &lt;&amp;bpmp TEGRA264_CLK_TOP_I2C&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;bpmp TEGRA264_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA264_RESET_I2C15&gt;;</div><div class='add'>+			reset-names = "i2c";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c16: i2c@c430000 {</div><div class='add'>+			compatible = "nvidia,tegra264-i2c";</div><div class='add'>+			reg = &lt;0x00 0x0c430000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clock-frequency = &lt;400000&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA264_CLK_TOP_I2C&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA264_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			clock-names = "div-clk", "parent";</div><div class='add'>+			assigned-clocks = &lt;&amp;bpmp TEGRA264_CLK_TOP_I2C&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;bpmp TEGRA264_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA264_RESET_I2C16&gt;;</div><div class='add'>+			reset-names = "i2c";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c0: i2c@c630000 {</div><div class='add'>+			compatible = "nvidia,tegra264-i2c";</div><div class='add'>+			reg = &lt;0x00 0x0c630000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clock-frequency = &lt;400000&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA264_CLK_TOP_I2C&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA264_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			clock-names = "div-clk", "parent";</div><div class='add'>+			assigned-clocks = &lt;&amp;bpmp TEGRA264_CLK_TOP_I2C&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;bpmp TEGRA264_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA264_RESET_I2C0&gt;;</div><div class='add'>+			reset-names = "i2c";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c1: i2c@c640000 {</div><div class='add'>+			compatible = "nvidia,tegra264-i2c";</div><div class='add'>+			reg = &lt;0x00 0x0c640000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clock-frequency = &lt;400000&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA264_CLK_TOP_I2C&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA264_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			clock-names = "div-clk", "parent";</div><div class='add'>+			assigned-clocks = &lt;&amp;bpmp TEGRA264_CLK_TOP_I2C&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;bpmp TEGRA264_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA264_RESET_I2C1&gt;;</div><div class='add'>+			reset-names = "i2c";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c4: i2c@c650000 {</div><div class='add'>+			compatible = "nvidia,tegra264-i2c";</div><div class='add'>+			reg = &lt;0x00 0x0c650000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clock-frequency = &lt;400000&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA264_CLK_TOP_I2C&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA264_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			clock-names = "div-clk", "parent";</div><div class='add'>+			assigned-clocks = &lt;&amp;bpmp TEGRA264_CLK_TOP_I2C&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;bpmp TEGRA264_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA264_RESET_I2C4&gt;;</div><div class='add'>+			reset-names = "i2c";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c6: i2c@c670000 {</div><div class='add'>+			compatible = "nvidia,tegra264-i2c";</div><div class='add'>+			reg = &lt;0x00 0x0c670000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clock-frequency = &lt;400000&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA264_CLK_TOP_I2C&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA264_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			clock-names = "div-clk", "parent";</div><div class='add'>+			assigned-clocks = &lt;&amp;bpmp TEGRA264_CLK_TOP_I2C&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;bpmp TEGRA264_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA264_RESET_I2C6&gt;;</div><div class='add'>+			reset-names = "i2c";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c7: i2c@c680000 {</div><div class='add'>+			compatible = "nvidia,tegra264-i2c";</div><div class='add'>+			reg = &lt;0x00 0x0c680000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clock-frequency = &lt;400000&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA264_CLK_TOP_I2C&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA264_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			clock-names = "div-clk", "parent";</div><div class='add'>+			assigned-clocks = &lt;&amp;bpmp TEGRA264_CLK_TOP_I2C&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;bpmp TEGRA264_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA264_RESET_I2C7&gt;;</div><div class='add'>+			reset-names = "i2c";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c8: i2c@c690000 {</div><div class='add'>+			compatible = "nvidia,tegra264-i2c";</div><div class='add'>+			reg = &lt;0x00 0x0c690000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clock-frequency = &lt;400000&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA264_CLK_TOP_I2C&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA264_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			clock-names = "div-clk", "parent";</div><div class='add'>+			assigned-clocks = &lt;&amp;bpmp TEGRA264_CLK_TOP_I2C&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;bpmp TEGRA264_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA264_RESET_I2C8&gt;;</div><div class='add'>+			reset-names = "i2c";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c9: i2c@c6a0000 {</div><div class='add'>+			compatible = "nvidia,tegra264-i2c";</div><div class='add'>+			reg = &lt;0x00 0x0c6a0000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clock-frequency = &lt;400000&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA264_CLK_TOP_I2C&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA264_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			clock-names = "div-clk", "parent";</div><div class='add'>+			assigned-clocks = &lt;&amp;bpmp TEGRA264_CLK_TOP_I2C&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;bpmp TEGRA264_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA264_RESET_I2C9&gt;;</div><div class='add'>+			reset-names = "i2c";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c10: i2c@c6b0000 {</div><div class='add'>+			compatible = "nvidia,tegra264-i2c";</div><div class='add'>+			reg = &lt;0x00 0x0c6b0000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clock-frequency = &lt;400000&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA264_CLK_TOP_I2C&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA264_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			clock-names = "div-clk", "parent";</div><div class='add'>+			assigned-clocks = &lt;&amp;bpmp TEGRA264_CLK_TOP_I2C&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;bpmp TEGRA264_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA264_RESET_I2C10&gt;;</div><div class='add'>+			reset-names = "i2c";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c11: i2c@c6c0000 {</div><div class='add'>+			compatible = "nvidia,tegra264-i2c";</div><div class='add'>+			reg = &lt;0x00 0x0c6c0000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clock-frequency = &lt;400000&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA264_CLK_TOP_I2C&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA264_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			clock-names = "div-clk", "parent";</div><div class='add'>+			assigned-clocks = &lt;&amp;bpmp TEGRA264_CLK_TOP_I2C&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;bpmp TEGRA264_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA264_RESET_I2C11&gt;;</div><div class='add'>+			reset-names = "i2c";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c12: i2c@c6d0000 {</div><div class='add'>+			compatible = "nvidia,tegra264-i2c";</div><div class='add'>+			reg = &lt;0x00 0x0c6d0000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clock-frequency = &lt;400000&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA264_CLK_TOP_I2C&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA264_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			clock-names = "div-clk", "parent";</div><div class='add'>+			assigned-clocks = &lt;&amp;bpmp TEGRA264_CLK_TOP_I2C&gt;;</div><div class='add'>+			assigned-clock-parents = &lt;&amp;bpmp TEGRA264_CLK_PLLP_OUT0&gt;;</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA264_RESET_I2C12&gt;;</div><div class='add'>+			reset-names = "i2c";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gic: interrupt-controller@46000000 {</div><div class='add'>+			compatible = "arm,gic-v3";</div><div class='add'>+			reg = &lt;0x00 0x46000000 0x0 0x010000&gt;, /* GICD */</div><div class='add'>+			      &lt;0x00 0x46080000 0x0 0x400000&gt;; /* GICR */</div><div class='add'>+			interrupt-parent = &lt;&amp;gic&gt;;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+			redistributor-stride = &lt;0x0 0x40000&gt;;</div><div class='add'>+			#redistributor-regions = &lt;1&gt;;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			ranges = &lt;0x0 0x0 0x00 0x46000000 0x0 0x1000000&gt;;</div><div class='add'>+</div><div class='add'>+			its: msi-controller@40000 {</div><div class='add'>+				compatible = "arm,gic-v3-its";</div><div class='add'>+				reg = &lt;0x0 0x40000 0x0 0x40000&gt;;</div><div class='add'>+				#msi-cells = &lt;1&gt;;</div><div class='add'>+				msi-controller;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* DISP_USB MMIO */</div><div class='add'>+	bus@8800000000 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		ranges = &lt;0x00 0x00000000 0x88 0x00000000 0x01 0x00000000&gt;;</div><div class='add'>+</div><div class='add'>+		smmu3: iommu@6000000 {</div><div class='add'>+			compatible = "arm,smmu-v3";</div><div class='add'>+			reg = &lt;0x00 0x6000000 0x0 0x200000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 225 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 226 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			interrupt-names = "eventq", "gerror";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			#iommu-cells = &lt;1&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		hda@90b0000 {</div><div class='add'>+			compatible = "nvidia,tegra264-hda";</div><div class='add'>+			reg = &lt;0x0 0x90b0000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;bpmp TEGRA264_CLK_AZA_2XBIT&gt;;</div><div class='add'>+			clock-names = "hda";</div><div class='add'>+			resets = &lt;&amp;bpmp TEGRA264_RESET_HDA&gt;,</div><div class='add'>+				 &lt;&amp;bpmp TEGRA264_RESET_HDACODEC&gt;;</div><div class='add'>+			reset-names = "hda", "hda2codec_2x";</div><div class='add'>+			interconnects = &lt;&amp;mc TEGRA264_MEMORY_CLIENT_HDAR &amp;emc&gt;,</div><div class='add'>+					&lt;&amp;mc TEGRA264_MEMORY_CLIENT_HDAW &amp;emc&gt;;</div><div class='add'>+			interconnect-names = "dma-mem", "write";</div><div class='add'>+			iommus = &lt;&amp;smmu3 TEGRA264_SID_HDA&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* UPHY MMIO */</div><div class='add'>+	bus@a800000000 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		ranges = &lt;0x00 0x00000000 0xa8 0x00000000 0x40 0x00000000&gt;, /* MMIO, ECAM, prefetchable memory, I/O */</div><div class='add'>+			 &lt;0x80 0x00000000 0x00 0x20000000 0x00 0x40000000&gt;; /* non-prefetchable memory (32-bit) */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			compatible = "arm,armv8";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x00000&gt;;</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+</div><div class='add'>+			i-cache-size = &lt;65536&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;65536&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@1 {</div><div class='add'>+			compatible = "arm,armv8";</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			reg = &lt;0x10000&gt;;</div><div class='add'>+			status = "okay";</div><div class='add'>+</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+</div><div class='add'>+			i-cache-size = &lt;65536&gt;;</div><div class='add'>+			i-cache-line-size = &lt;64&gt;;</div><div class='add'>+			i-cache-sets = &lt;256&gt;;</div><div class='add'>+			d-cache-size = &lt;65536&gt;;</div><div class='add'>+			d-cache-line-size = &lt;64&gt;;</div><div class='add'>+			d-cache-sets = &lt;256&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bpmp: bpmp {</div><div class='add'>+		compatible = "nvidia,tegra264-bpmp", "nvidia,tegra186-bpmp";</div><div class='add'>+		mboxes = &lt;&amp;hsp_top TEGRA_HSP_MBOX_TYPE_DB</div><div class='add'>+				   TEGRA_HSP_DB_MASTER_BPMP&gt;;</div><div class='add'>+		memory-region = &lt;&amp;shmem_bpmp&gt;;</div><div class='add'>+		#clock-cells = &lt;1&gt;;</div><div class='add'>+		#reset-cells = &lt;1&gt;;</div><div class='add'>+		#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		i2c {</div><div class='add'>+			compatible = "nvidia,tegra186-bpmp-i2c";</div><div class='add'>+			nvidia,bpmp-bus-id = &lt;5&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		thermal {</div><div class='add'>+			compatible = "nvidia,tegra186-bpmp-thermal";</div><div class='add'>+			#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu {</div><div class='add'>+		compatible = "arm,armv8-pmuv3";</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-1.0";</div><div class='add'>+		status = "okay";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "nvidia,tegra264-audio-graph-card";</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;bpmp TEGRA264_CLK_PLLA1&gt;,</div><div class='add'>+				&lt;&amp;bpmp TEGRA264_CLK_PLLA1_OUT1&gt;;</div><div class='add'>+		clock-names = "pll_a", "plla_out0";</div><div class='add'>+		assigned-clocks = &lt;&amp;bpmp TEGRA264_CLK_PLLA1&gt;,</div><div class='add'>+			&lt;&amp;bpmp TEGRA264_CLK_PLLA1_OUT1&gt;,</div><div class='add'>+			&lt;&amp;bpmp TEGRA264_CLK_AUD_MCLK&gt;;</div><div class='add'>+		assigned-clock-parents = &lt;0&gt;,</div><div class='add'>+			&lt;&amp;bpmp TEGRA264_CLK_PLLA1&gt;,</div><div class='add'>+			&lt;&amp;bpmp TEGRA264_CLK_PLLA1_OUT1&gt;;</div><div class='add'>+</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 12 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		status = "okay";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile<br/>index cc103f7020fd..6f34d5ed331c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/Makefile?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/Makefile</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/Makefile</a></div><div class='hunk'>@@ -1,28 +1,364 @@</div><div class='ctx'> # SPDX-License-Identifier: GPL-2.0</div><div class='ctx'> dtb-$(CONFIG_ARCH_QCOM)	+= apq8016-sbc.dtb</div><div class='add'>+</div><div class='add'>+apq8016-sbc-d3-camera-mezzanine-dtbs	:= apq8016-sbc.dtb apq8016-sbc-d3-camera-mezzanine.dtbo</div><div class='add'>+apq8016-sbc-usb-host-dtbs		:= apq8016-sbc.dtb apq8016-sbc-usb-host.dtbo</div><div class='add'>+</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM) += sar2130p-qar2130p.dtb</div><div class='add'>+</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= apq8016-sbc-d3-camera-mezzanine.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= apq8016-sbc-usb-host.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= apq8016-schneider-hmibsc.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= apq8039-t2.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= apq8094-sony-xperia-kitakami-karin_windy.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_QCOM)	+= apq8096-db820c.dtb</div><div class='del'>-dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= apq8096-ifc6640.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= hamoa-iot-evk.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= ipq5018-rdp432-c2.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= ipq5018-tplink-archer-ax55-v1.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= ipq5332-rdp441.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= ipq5332-rdp442.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= ipq5332-rdp468.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= ipq5332-rdp474.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= ipq5424-rdp466.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_QCOM)	+= ipq6018-cp01-c1.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk01.dtb</div><div class='del'>-dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-mtp.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk10-c1.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk10-c2.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= ipq9574-rdp418.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= ipq9574-rdp433.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= ipq9574-rdp449.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= ipq9574-rdp453.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= ipq9574-rdp454.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= lemans-evk.dtb</div><div class='add'>+</div><div class='add'>+lemans-evk-camera-csi1-imx577-dtbs	:= lemans-evk.dtb lemans-evk-camera-csi1-imx577.dtbo</div><div class='add'>+lemans-evk-camera-dtbs	:= lemans-evk.dtb lemans-evk-camera.dtbo</div><div class='add'>+</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= lemans-evk-camera-csi1-imx577.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= lemans-evk-camera.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= monaco-evk.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8216-samsung-fortuna3g.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-acer-a1-724.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-alcatel-idol347.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-asus-z00l.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-gplus-fl8005a.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-huawei-g7.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-lg-c50.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-lg-m216.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-longcheer-l8150.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-longcheer-l8910.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-motorola-harpia.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-motorola-osprey.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-motorola-surnia.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-mtp.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-samsung-a3u-eur.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-samsung-a5u-eur.dtb</div><div class='del'>-dtb-$(CONFIG_ARCH_QCOM)	+= msm8992-bullhead-rev-101.dtb</div><div class='del'>-dtb-$(CONFIG_ARCH_QCOM)	+= msm8994-angler-rev-101.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-samsung-e5.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-samsung-e7.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-samsung-gprimeltecan.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-samsung-grandmax.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-samsung-grandprimelte.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-samsung-gt510.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-samsung-gt58.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-samsung-j3ltetw.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-samsung-j5.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-samsung-j5x.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-samsung-rossa.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-samsung-serranove.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-thwc-uf896.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-thwc-ufi001c.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-wingtech-wt86518.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-wingtech-wt86528.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-wingtech-wt88047.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-yiming-uz801v3.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8917-xiaomi-riva.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8929-wingtech-wt82918hd.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8937-xiaomi-land.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8939-asus-z00t.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8939-huawei-kiwi.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8939-longcheer-l9100.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8939-samsung-a7.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8939-sony-xperia-kanuti-tulip.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8939-wingtech-wt82918.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8939-wingtech-wt82918hd.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8953-flipkart-rimob.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8953-motorola-potter.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8953-xiaomi-daisy.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8953-xiaomi-mido.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8953-xiaomi-tissot.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8953-xiaomi-vince.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8956-sony-xperia-loire-kugo.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8956-sony-xperia-loire-suzu.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8976-longcheer-l9360.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8992-lg-bullhead-rev-10.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8992-lg-bullhead-rev-101.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8992-lg-h815.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8992-msft-lumia-octagon-talkman.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8992-xiaomi-libra.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8994-huawei-angler-rev-101.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8994-msft-lumia-octagon-cityman.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8994-sony-xperia-kitakami-ivy.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8994-sony-xperia-kitakami-karin.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8994-sony-xperia-kitakami-satsuki.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8994-sony-xperia-kitakami-sumire.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8994-sony-xperia-kitakami-suzuran.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_QCOM)	+= msm8996-mtp.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8996-oneplus3.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8996-oneplus3t.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8996-sony-xperia-tone-dora.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8996-sony-xperia-tone-kagura.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8996-sony-xperia-tone-keyaki.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8996-xiaomi-gemini.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8996pro-xiaomi-natrium.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8996pro-xiaomi-scorpio.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_QCOM)	+= msm8998-asus-novago-tp370ql.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8998-fxtec-pro1.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_QCOM)	+= msm8998-hp-envy-x2.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_QCOM)	+= msm8998-lenovo-miix-630.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_QCOM)	+= msm8998-mtp.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8998-oneplus-cheeseburger.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8998-oneplus-dumpling.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8998-sony-xperia-yoshino-lilac.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8998-sony-xperia-yoshino-maple.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8998-sony-xperia-yoshino-poplar.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= msm8998-xiaomi-sagit.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= qcm6490-fairphone-fp5.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= qcm6490-idp.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= qcm6490-particle-tachyon.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= qcm6490-shift-otter.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= qcs404-evb-1000.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= qcs404-evb-4000.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= qcs615-ride.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= qcs6490-radxa-dragon-q6a.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= qcs6490-rb3gen2.dtb</div><div class='add'>+</div><div class='add'>+qcs6490-rb3gen2-vision-mezzanine-dtbs := qcs6490-rb3gen2.dtb qcs6490-rb3gen2-vision-mezzanine.dtbo</div><div class='add'>+qcs6490-rb3gen2-industrial-mezzanine-dtbs := qcs6490-rb3gen2.dtb qcs6490-rb3gen2-industrial-mezzanine.dtbo</div><div class='add'>+</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= qcs6490-rb3gen2-industrial-mezzanine.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= qcs6490-rb3gen2-vision-mezzanine.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= qcs8300-ride.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= qcs8550-aim300-aiot.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= qcs9100-ride.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= qcs9100-ride-r3.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= qdu1000-idp.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= qrb2210-rb1.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= qrb4210-rb2.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= qrb5165-rb5.dtb</div><div class='add'>+</div><div class='add'>+qrb5165-rb5-vision-mezzanine-dtbs	:= qrb5165-rb5.dtb qrb5165-rb5-vision-mezzanine.dtbo</div><div class='add'>+</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= qrb5165-rb5-vision-mezzanine.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= qru1000-idp.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sa8155p-adp.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sa8295p-adp.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sa8540p-ride.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sa8775p-ride.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sa8775p-ride-r3.dtb</div><div class='add'>+sc7180-acer-aspire1-el2-dtbs	:= sc7180-acer-aspire1.dtb sc7180-el2.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-acer-aspire1.dtb sc7180-acer-aspire1-el2.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-idp.dtb</div><div class='del'>-dtb-$(CONFIG_ARCH_QCOM)	+= sdm845-cheza-r1.dtb</div><div class='del'>-dtb-$(CONFIG_ARCH_QCOM)	+= sdm845-cheza-r2.dtb</div><div class='del'>-dtb-$(CONFIG_ARCH_QCOM)	+= sdm845-cheza-r3.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-coachz-r1.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-coachz-r1-lte.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-coachz-r3.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-coachz-r3-lte.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-homestar-r2.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-homestar-r3.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-homestar-r4.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-kingoftown.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-lazor-r1.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-lazor-r1-kb.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-lazor-r1-lte.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-lazor-r3.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-lazor-r3-kb.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-lazor-r3-lte.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-lazor-r9.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-lazor-r9-kb.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-lazor-r9-lte.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-lazor-r10.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-lazor-r10-kb.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-lazor-r10-lte.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-lazor-limozeen-r4.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-lazor-limozeen-r9.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-lazor-limozeen-r10.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-lazor-limozeen-nots-r4.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-lazor-limozeen-nots-r5.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-lazor-limozeen-nots-r9.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-lazor-limozeen-nots-r10.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-pazquel-lte-parade.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-pazquel-lte-ti.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-pazquel-parade.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-pazquel-ti.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-pazquel360-lte.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-pazquel360-wifi.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-pompom-r1.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-pompom-r1-lte.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-pompom-r2.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-pompom-r2-lte.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-pompom-r3.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-pompom-r3-lte.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-quackingstick-r0.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-quackingstick-r0-lte.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-wormdingler-rev1-boe.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-wormdingler-rev1-inx.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-wormdingler-rev1-inx-rt5682s.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-wormdingler-rev1-boe-rt5682s.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-r1.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-r1-lte.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7280-herobrine-crd.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7280-herobrine-crd-pro.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7280-herobrine-evoker.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7280-herobrine-evoker-lte.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7280-herobrine-herobrine-r1.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7280-herobrine-villager-r0.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7280-herobrine-villager-r1.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7280-herobrine-villager-r1-lte.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7280-herobrine-zombie.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7280-herobrine-zombie-lte.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7280-herobrine-zombie-nvme.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7280-herobrine-zombie-nvme-lte.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7280-idp.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7280-idp2.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc7280-crd-r3.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc8180x-lenovo-flex-5g.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc8180x-primus.dtb</div><div class='add'>+sc8280xp-crd-el2-dtbs	:= sc8280xp-crd.dtb sc8280xp-el2.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc8280xp-crd.dtb sc8280xp-crd-el2.dtb</div><div class='add'>+sc8280xp-huawei-gaokun3-el2-dtbs	:= sc8280xp-huawei-gaokun3.dtb sc8280xp-el2.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc8280xp-huawei-gaokun3.dtb sc8280xp-huawei-gaokun3-el2.dtb</div><div class='add'>+sc8280xp-lenovo-thinkpad-x13s-el2-dtbs	:= sc8280xp-lenovo-thinkpad-x13s.dtb sc8280xp-el2.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc8280xp-lenovo-thinkpad-x13s.dtb sc8280xp-lenovo-thinkpad-x13s-el2.dtb</div><div class='add'>+sc8280xp-microsoft-arcata-el2-dtbs	:= sc8280xp-microsoft-arcata.dtb sc8280xp-el2.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc8280xp-microsoft-arcata.dtb sc8280xp-microsoft-arcata-el2.dtb</div><div class='add'>+sc8280xp-microsoft-blackrock-el2-dtbs	:= sc8280xp-microsoft-blackrock.dtb sc8280xp-el2.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sc8280xp-microsoft-blackrock.dtb sc8280xp-microsoft-blackrock-el2.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sda660-inforce-ifc6560.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sdm450-lenovo-tbx605f.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sdm450-motorola-ali.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sdm630-sony-xperia-ganges-kirin.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sdm630-sony-xperia-nile-discovery.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sdm630-sony-xperia-nile-pioneer.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sdm630-sony-xperia-nile-voyager.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sdm632-fairphone-fp3.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sdm632-motorola-ocean.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sdm636-sony-xperia-ganges-mermaid.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sdm660-xiaomi-lavender.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sdm670-google-sargo.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_QCOM)	+= sdm845-db845c.dtb</div><div class='add'>+</div><div class='add'>+sdm845-db845c-navigation-mezzanine-dtbs	:= sdm845-db845c.dtb sdm845-db845c-navigation-mezzanine.dtbo</div><div class='add'>+</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sdm845-db845c-navigation-mezzanine.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sdm845-lg-judyln.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sdm845-lg-judyp.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_QCOM)	+= sdm845-mtp.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sdm845-oneplus-enchilada.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sdm845-oneplus-fajita.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sdm845-samsung-starqltechn.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sdm845-sony-xperia-tama-akari.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sdm845-sony-xperia-tama-akatsuki.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sdm845-sony-xperia-tama-apollo.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sdm845-xiaomi-beryllium-ebbg.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sdm845-xiaomi-beryllium-tianma.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sdm845-xiaomi-polaris.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sdm845-shift-axolotl.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sdm850-huawei-matebook-e-2019.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_QCOM)	+= sdm850-lenovo-yoga-c630.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sdm850-samsung-w737.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sdx75-idp.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sm4250-oneplus-billie2.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sm4450-qrd.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sm6115-fxtec-pro1x.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sm6115p-lenovo-j606f.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sm6125-sony-xperia-seine-pdx201.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM) += sm6125-xiaomi-ginkgo.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sm6125-xiaomi-laurel-sprout.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sm6350-sony-xperia-lena-pdx213.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sm6375-sony-xperia-murray-pdx225.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sm7125-xiaomi-curtana.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sm7125-xiaomi-joyeuse.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sm7225-fairphone-fp4.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sm7325-nothing-spacewar.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sm8150-hdk.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sm8150-microsoft-surface-duo.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_QCOM)	+= sm8150-mtp.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sm8150-sony-xperia-kumano-bahamut.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sm8150-sony-xperia-kumano-griffin.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sm8250-hdk.dtb</div><div class='ctx'> dtb-$(CONFIG_ARCH_QCOM)	+= sm8250-mtp.dtb</div><div class='del'>-dtb-$(CONFIG_ARCH_QCOM)	+= qcs404-evb-1000.dtb</div><div class='del'>-dtb-$(CONFIG_ARCH_QCOM)	+= qcs404-evb-4000.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sm8250-samsung-r8q.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sm8250-samsung-x1q.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sm8250-sony-xperia-edo-pdx203.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sm8250-sony-xperia-edo-pdx206.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sm8250-xiaomi-elish-boe.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sm8250-xiaomi-elish-csot.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sm8250-xiaomi-pipa.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sm8350-hdk.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sm8350-microsoft-surface-duo2.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sm8350-mtp.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sm8350-sony-xperia-sagami-pdx214.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sm8350-sony-xperia-sagami-pdx215.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sm8450-hdk.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sm8450-qrd.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sm8450-samsung-r0q.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sm8450-sony-xperia-nagara-pdx223.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sm8450-sony-xperia-nagara-pdx224.dtb</div><div class='add'>+</div><div class='add'>+sm8550-hdk-rear-camera-card-dtbs	:= sm8550-hdk.dtb sm8550-hdk-rear-camera-card.dtbo</div><div class='add'>+</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sm8550-hdk-rear-camera-card.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sm8550-hdk.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sm8550-mtp.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sm8550-qrd.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sm8550-samsung-q5q.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sm8550-sony-xperia-yodo-pdx234.dtb</div><div class='add'>+</div><div class='add'>+sm8650-hdk-display-card-dtbs	:= sm8650-hdk.dtb sm8650-hdk-display-card.dtbo</div><div class='add'>+</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sm8650-hdk-display-card.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sm8650-hdk.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sm8650-mtp.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sm8650-qrd.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sm8750-mtp.dtb</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= sm8750-qrd.dtb</div><div class='add'>+x1e001de-devkit-el2-dtbs	:= x1e001de-devkit.dtb x1-el2.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= x1e001de-devkit.dtb x1e001de-devkit-el2.dtb</div><div class='add'>+x1e78100-lenovo-thinkpad-t14s-el2-dtbs	:= x1e78100-lenovo-thinkpad-t14s.dtb x1-el2.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= x1e78100-lenovo-thinkpad-t14s.dtb x1e78100-lenovo-thinkpad-t14s-el2.dtb</div><div class='add'>+x1e78100-lenovo-thinkpad-t14s-oled-el2-dtbs	:= x1e78100-lenovo-thinkpad-t14s-oled.dtb x1-el2.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= x1e78100-lenovo-thinkpad-t14s-oled.dtb x1e78100-lenovo-thinkpad-t14s-oled-el2.dtb</div><div class='add'>+x1e80100-asus-vivobook-s15-el2-dtbs	:= x1e80100-asus-vivobook-s15.dtb x1-el2.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= x1e80100-asus-vivobook-s15.dtb x1e80100-asus-vivobook-s15-el2.dtb</div><div class='add'>+x1e80100-asus-zenbook-a14-el2-dtbs	:= x1e80100-asus-zenbook-a14.dtb x1-el2.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= x1e80100-asus-zenbook-a14.dtb x1e80100-asus-zenbook-a14-el2.dtb</div><div class='add'>+x1e80100-crd-el2-dtbs	:= x1e80100-crd.dtb x1-el2.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= x1e80100-crd.dtb x1e80100-crd-el2.dtb</div><div class='add'>+x1e80100-dell-inspiron-14-plus-7441-el2-dtbs	:= x1e80100-dell-inspiron-14-plus-7441.dtb x1-el2.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= x1e80100-dell-inspiron-14-plus-7441.dtb x1e80100-dell-inspiron-14-plus-7441-el2.dtb</div><div class='add'>+x1e80100-dell-latitude-7455-el2-dtbs	:= x1e80100-dell-latitude-7455.dtb x1-el2.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= x1e80100-dell-latitude-7455.dtb x1e80100-dell-latitude-7455-el2.dtb</div><div class='add'>+x1e80100-dell-xps13-9345-el2-dtbs	:= x1e80100-dell-xps13-9345.dtb x1-el2.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= x1e80100-dell-xps13-9345.dtb x1e80100-dell-xps13-9345-el2.dtb</div><div class='add'>+x1e80100-hp-elitebook-ultra-g1q-el2-dtbs := x1e80100-hp-elitebook-ultra-g1q.dtb x1-el2.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= x1e80100-hp-elitebook-ultra-g1q.dtb x1e80100-hp-elitebook-ultra-g1q-el2.dtb</div><div class='add'>+x1e80100-hp-omnibook-x14-el2-dtbs	:= x1e80100-hp-omnibook-x14.dtb x1-el2.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= x1e80100-hp-omnibook-x14.dtb x1e80100-hp-omnibook-x14-el2.dtb</div><div class='add'>+x1e80100-lenovo-yoga-slim7x-el2-dtbs	:= x1e80100-lenovo-yoga-slim7x.dtb x1-el2.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= x1e80100-lenovo-yoga-slim7x.dtb x1e80100-lenovo-yoga-slim7x-el2.dtb</div><div class='add'>+x1e80100-microsoft-romulus13-el2-dtbs	:= x1e80100-microsoft-romulus13.dtb x1-el2.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= x1e80100-microsoft-romulus13.dtb x1e80100-microsoft-romulus13-el2.dtb</div><div class='add'>+x1e80100-microsoft-romulus15-el2-dtbs	:= x1e80100-microsoft-romulus15.dtb x1-el2.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= x1e80100-microsoft-romulus15.dtb x1e80100-microsoft-romulus15-el2.dtb</div><div class='add'>+x1e80100-qcp-el2-dtbs	:= x1e80100-qcp.dtb x1-el2.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= x1e80100-qcp.dtb x1e80100-qcp-el2.dtb</div><div class='add'>+x1p42100-asus-zenbook-a14-el2-dtbs	:= x1p42100-asus-zenbook-a14.dtb x1-el2.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= x1p42100-asus-zenbook-a14.dtb x1p42100-asus-zenbook-a14-el2.dtb</div><div class='add'>+x1p42100-asus-zenbook-a14-lcd-el2-dtbs	:= x1p42100-asus-zenbook-a14-lcd.dtb x1-el2.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= x1p42100-asus-zenbook-a14-lcd.dtb x1p42100-asus-zenbook-a14-lcd-el2.dtb</div><div class='add'>+x1p42100-crd-el2-dtbs	:= x1p42100-crd.dtb x1-el2.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= x1p42100-crd.dtb x1p42100-crd-el2.dtb</div><div class='add'>+x1p42100-hp-omnibook-x14-el2-dtbs := x1p42100-hp-omnibook-x14.dtb x1-el2.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= x1p42100-hp-omnibook-x14.dtb x1p42100-hp-omnibook-x14-el2.dtb</div><div class='add'>+x1p42100-lenovo-thinkbook-16-el2-dtbs	:= x1p42100-lenovo-thinkbook-16.dtb x1-el2.dtbo</div><div class='add'>+dtb-$(CONFIG_ARCH_QCOM)	+= x1p42100-lenovo-thinkbook-16.dtb x1p42100-lenovo-thinkbook-16-el2.dtb</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/agatti.dtsi b/arch/arm64/boot/dts/qcom/agatti.dtsi<br/>new file mode 100644<br/>index 000000000000..8bf5c5583fc2<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/agatti.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/agatti.dtsi</a></div><div class='hunk'>@@ -0,0 +1,2750 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2023, Linaro Ltd</div><div class='add'>+ *</div><div class='add'>+ * Based on sm6115.dtsi and previous efforts by Shawn Guo &amp; Loic Poulain.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,dispcc-qcm2290.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,dsi-phy-28nm.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,gcc-qcm2290.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,qcm2290-gpucc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,rpmcc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/dma/qcom-gpi.h&gt;</div><div class='add'>+#include &lt;dt-bindings/firmware/qcom,scm.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interconnect/qcom,qcm2290.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interconnect/qcom,rpm-icc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/power/qcom-rpmpd.h&gt;</div><div class='add'>+#include &lt;dt-bindings/soc/qcom,apr.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/qcom,q6asm.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/qcom,q6dsp-lpass-ports.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	interrupt-parent = &lt;&amp;intc&gt;;</div><div class='add'>+</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	chosen { };</div><div class='add'>+</div><div class='add'>+	clocks {</div><div class='add'>+		xo_board: xo-board {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sleep_clk: sleep-clk {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			clock-frequency = &lt;32764&gt;;</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x0 0x0&gt;;</div><div class='add'>+			clocks = &lt;&amp;cpufreq_hw 0&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;100&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			qcom,freq-domain = &lt;&amp;cpufreq_hw 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cpu_pd0&gt;;</div><div class='add'>+			power-domain-names = "psci";</div><div class='add'>+			l2_0: l2-cache {</div><div class='add'>+				compatible = "cache";</div><div class='add'>+				cache-level = &lt;2&gt;;</div><div class='add'>+				cache-unified;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@1 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x0 0x1&gt;;</div><div class='add'>+			clocks = &lt;&amp;cpufreq_hw 0&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;100&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			qcom,freq-domain = &lt;&amp;cpufreq_hw 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cpu_pd1&gt;;</div><div class='add'>+			power-domain-names = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@2 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x0 0x2&gt;;</div><div class='add'>+			clocks = &lt;&amp;cpufreq_hw 0&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;100&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			qcom,freq-domain = &lt;&amp;cpufreq_hw 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cpu_pd2&gt;;</div><div class='add'>+			power-domain-names = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@3 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x0 0x3&gt;;</div><div class='add'>+			clocks = &lt;&amp;cpufreq_hw 0&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;100&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			qcom,freq-domain = &lt;&amp;cpufreq_hw 0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cpu_pd3&gt;;</div><div class='add'>+			power-domain-names = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu-map {</div><div class='add'>+			cluster0 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu2&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu3&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		domain-idle-states {</div><div class='add'>+			cluster_sleep: cluster-sleep-0 {</div><div class='add'>+				compatible = "domain-idle-state";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x41000043&gt;;</div><div class='add'>+				entry-latency-us = &lt;800&gt;;</div><div class='add'>+				exit-latency-us = &lt;2118&gt;;</div><div class='add'>+				min-residency-us = &lt;7376&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		idle-states {</div><div class='add'>+			entry-method = "psci";</div><div class='add'>+</div><div class='add'>+			cpu_sleep: cpu-sleep-0 {</div><div class='add'>+				compatible = "arm,idle-state";</div><div class='add'>+				idle-state-name = "power-collapse";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x40000003&gt;;</div><div class='add'>+				entry-latency-us = &lt;290&gt;;</div><div class='add'>+				exit-latency-us = &lt;376&gt;;</div><div class='add'>+				min-residency-us = &lt;1182&gt;;</div><div class='add'>+				local-timer-stop;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	firmware {</div><div class='add'>+		scm: scm {</div><div class='add'>+			compatible = "qcom,scm-qcm2290", "qcom,scm";</div><div class='add'>+			clocks = &lt;&amp;rpmcc RPM_SMD_CE1_CLK&gt;;</div><div class='add'>+			clock-names = "core";</div><div class='add'>+			qcom,dload-mode = &lt;&amp;tcsr_regs 0x13000&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+			interconnects = &lt;&amp;system_noc MASTER_CRYPTO_CORE0 RPM_ALWAYS_TAG</div><div class='add'>+					 &amp;bimc SLAVE_EBI1 RPM_ALWAYS_TAG&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		/* We expect the bootloader to fill in the size */</div><div class='add'>+		reg = &lt;0 0x40000000 0 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu {</div><div class='add'>+		compatible = "arm,cortex-a53-pmu";</div><div class='add'>+		interrupts = &lt;GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-1.0";</div><div class='add'>+		method = "smc";</div><div class='add'>+</div><div class='add'>+		cpu_pd0: power-domain-cpu0 {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cluster_pd&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;cpu_sleep&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_pd1: power-domain-cpu1 {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cluster_pd&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;cpu_sleep&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_pd2: power-domain-cpu2 {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cluster_pd&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;cpu_sleep&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_pd3: power-domain-cpu3 {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cluster_pd&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;cpu_sleep&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cluster_pd: power-domain-cpu-cluster {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;mpm&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;cluster_sleep&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rpm: remoteproc {</div><div class='add'>+		compatible = "qcom,qcm2290-rpm-proc", "qcom,rpm-proc";</div><div class='add'>+</div><div class='add'>+		glink-edge {</div><div class='add'>+			compatible = "qcom,glink-rpm";</div><div class='add'>+			interrupts = &lt;GIC_SPI 194 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			qcom,rpm-msg-ram = &lt;&amp;rpm_msg_ram&gt;;</div><div class='add'>+			mboxes = &lt;&amp;apcs_glb 0&gt;;</div><div class='add'>+</div><div class='add'>+			rpm_requests: rpm-requests {</div><div class='add'>+				compatible = "qcom,rpm-qcm2290", "qcom,glink-smd-rpm";</div><div class='add'>+				qcom,glink-channels = "rpm_requests";</div><div class='add'>+</div><div class='add'>+				rpmcc: clock-controller {</div><div class='add'>+					compatible = "qcom,rpmcc-qcm2290", "qcom,rpmcc";</div><div class='add'>+					clocks = &lt;&amp;xo_board&gt;;</div><div class='add'>+					clock-names = "xo";</div><div class='add'>+					#clock-cells = &lt;1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				rpmpd: power-controller {</div><div class='add'>+					compatible = "qcom,qcm2290-rpmpd";</div><div class='add'>+					#power-domain-cells = &lt;1&gt;;</div><div class='add'>+					operating-points-v2 = &lt;&amp;rpmpd_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+					rpmpd_opp_table: opp-table {</div><div class='add'>+						compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+						rpmpd_opp_min_svs: opp1 {</div><div class='add'>+							opp-level = &lt;RPM_SMD_LEVEL_MIN_SVS&gt;;</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						rpmpd_opp_low_svs: opp2 {</div><div class='add'>+							opp-level = &lt;RPM_SMD_LEVEL_LOW_SVS&gt;;</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						rpmpd_opp_svs: opp3 {</div><div class='add'>+							opp-level = &lt;RPM_SMD_LEVEL_SVS&gt;;</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						rpmpd_opp_svs_plus: opp4 {</div><div class='add'>+							opp-level = &lt;RPM_SMD_LEVEL_SVS_PLUS&gt;;</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						rpmpd_opp_nom: opp5 {</div><div class='add'>+							opp-level = &lt;RPM_SMD_LEVEL_NOM&gt;;</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						rpmpd_opp_nom_plus: opp6 {</div><div class='add'>+							opp-level = &lt;RPM_SMD_LEVEL_NOM_PLUS&gt;;</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						rpmpd_opp_turbo: opp7 {</div><div class='add'>+							opp-level = &lt;RPM_SMD_LEVEL_TURBO&gt;;</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						rpmpd_opp_turbo_plus: opp8 {</div><div class='add'>+							opp-level = &lt;RPM_SMD_LEVEL_TURBO_NO_CPR&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mpm: interrupt-controller {</div><div class='add'>+			compatible = "qcom,mpm";</div><div class='add'>+			qcom,rpm-msg-ram = &lt;&amp;apss_mpm&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 197 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			mboxes = &lt;&amp;apcs_glb 1&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;intc&gt;;</div><div class='add'>+			qcom,mpm-pin-count = &lt;96&gt;;</div><div class='add'>+			qcom,mpm-pin-map = &lt;2 275&gt;,  /* TSENS0 uplow */</div><div class='add'>+					   &lt;5 296&gt;,  /* Soundwire master_irq */</div><div class='add'>+					   &lt;12 422&gt;, /* DWC3 ss_phy_irq */</div><div class='add'>+					   &lt;24 79&gt;,  /* Soundwire wake_irq */</div><div class='add'>+					   &lt;86 183&gt;, /* MPM wake, SPMI */</div><div class='add'>+					   &lt;90 260&gt;; /* QUSB2_PHY DP+DM */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved_memory: reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		hyp_mem: hyp@45700000 {</div><div class='add'>+			reg = &lt;0x0 0x45700000 0x0 0x600000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		xbl_aop_mem: xbl-aop@45e00000 {</div><div class='add'>+			reg = &lt;0x0 0x45e00000 0x0 0x140000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sec_apps_mem: sec-apps@45fff000 {</div><div class='add'>+			reg = &lt;0x0 0x45fff000 0x0 0x1000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smem_mem: smem@46000000 {</div><div class='add'>+			compatible = "qcom,smem";</div><div class='add'>+			reg = &lt;0x0 0x46000000 0x0 0x200000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+</div><div class='add'>+			hwlocks = &lt;&amp;tcsr_mutex 3&gt;;</div><div class='add'>+			qcom,rpm-msg-ram = &lt;&amp;rpm_msg_ram&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pil_modem_mem: modem@4ab00000 {</div><div class='add'>+			reg = &lt;0x0 0x4ab00000 0x0 0x6900000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pil_video_mem: video@51400000 {</div><div class='add'>+			reg = &lt;0x0 0x51400000 0x0 0x500000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wlan_msa_mem: wlan-msa@51900000 {</div><div class='add'>+			reg = &lt;0x0 0x51900000 0x0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pil_adsp_mem: adsp@51a00000 {</div><div class='add'>+			reg = &lt;0x0 0x51a00000 0x0 0x1c00000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pil_ipa_fw_mem: ipa-fw@53600000 {</div><div class='add'>+			reg = &lt;0x0 0x53600000 0x0 0x10000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pil_ipa_gsi_mem: ipa-gsi@53610000 {</div><div class='add'>+			reg = &lt;0x0 0x53610000 0x0 0x5000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pil_gpu_mem: zap@53615000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0x0 0x53615000 0x0 0x2000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cont_splash_memory: framebuffer@5c000000 {</div><div class='add'>+			reg = &lt;0x0 0x5c000000 0x0 0x00f00000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dfps_data_memory: dpfs-data@5cf00000 {</div><div class='add'>+			reg = &lt;0x0 0x5cf00000 0x0 0x0100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		removed_mem: reserved@60000000 {</div><div class='add'>+			reg = &lt;0x0 0x60000000 0x0 0x3900000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rmtfs_mem: memory@89b01000 {</div><div class='add'>+			compatible = "qcom,rmtfs-mem";</div><div class='add'>+			reg = &lt;0x0 0x89b01000 0x0 0x200000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+</div><div class='add'>+			qcom,client-id = &lt;1&gt;;</div><div class='add'>+			qcom,vmid = &lt;QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	smp2p-adsp {</div><div class='add'>+		compatible = "qcom,smp2p";</div><div class='add'>+		qcom,smem = &lt;443&gt;, &lt;429&gt;;</div><div class='add'>+</div><div class='add'>+		interrupts = &lt;GIC_SPI 279 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+</div><div class='add'>+		mboxes = &lt;&amp;apcs_glb 10&gt;;</div><div class='add'>+</div><div class='add'>+		qcom,local-pid = &lt;0&gt;;</div><div class='add'>+		qcom,remote-pid = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		adsp_smp2p_out: master-kernel {</div><div class='add'>+			qcom,entry-name = "master-kernel";</div><div class='add'>+			#qcom,smem-state-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		adsp_smp2p_in: slave-kernel {</div><div class='add'>+			qcom,entry-name = "slave-kernel";</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	smp2p-mpss {</div><div class='add'>+		compatible = "qcom,smp2p";</div><div class='add'>+		qcom,smem = &lt;435&gt;, &lt;428&gt;;</div><div class='add'>+</div><div class='add'>+		interrupts = &lt;GIC_SPI 70 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+</div><div class='add'>+		mboxes = &lt;&amp;apcs_glb 14&gt;;</div><div class='add'>+</div><div class='add'>+		qcom,local-pid = &lt;0&gt;;</div><div class='add'>+		qcom,remote-pid = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		modem_smp2p_out: master-kernel {</div><div class='add'>+			qcom,entry-name = "master-kernel";</div><div class='add'>+			#qcom,smem-state-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		modem_smp2p_in: slave-kernel {</div><div class='add'>+			qcom,entry-name = "slave-kernel";</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wlan_smp2p_in: wlan-wpss-to-ap {</div><div class='add'>+			qcom,entry-name = "wlan";</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc: soc@0 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges = &lt;0 0 0 0 0x10 0&gt;;</div><div class='add'>+		dma-ranges = &lt;0 0 0 0 0x10 0&gt;;</div><div class='add'>+</div><div class='add'>+		tcsr_mutex: hwlock@340000 {</div><div class='add'>+			compatible = "qcom,tcsr-mutex";</div><div class='add'>+			reg = &lt;0x0 0x00340000 0x0 0x20000&gt;;</div><div class='add'>+			#hwlock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tcsr_regs: syscon@3c0000 {</div><div class='add'>+			compatible = "qcom,qcm2290-tcsr", "syscon";</div><div class='add'>+			reg = &lt;0x0 0x003c0000 0x0 0x40000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tlmm: pinctrl@500000 {</div><div class='add'>+			compatible = "qcom,qcm2290-tlmm";</div><div class='add'>+			reg = &lt;0x0 0x00500000 0x0 0x300000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			gpio-ranges = &lt;&amp;tlmm 0 0 127&gt;;</div><div class='add'>+			wakeup-parent = &lt;&amp;mpm&gt;;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			qup_i2c0_default: qup-i2c0-default-state {</div><div class='add'>+				pins = "gpio0", "gpio1";</div><div class='add'>+				function = "qup0";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c1_default: qup-i2c1-default-state {</div><div class='add'>+				pins = "gpio4", "gpio5";</div><div class='add'>+				function = "qup1";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c2_default: qup-i2c2-default-state {</div><div class='add'>+				pins = "gpio6", "gpio7";</div><div class='add'>+				function = "qup2";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c3_default: qup-i2c3-default-state {</div><div class='add'>+				pins = "gpio8", "gpio9";</div><div class='add'>+				function = "qup3";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c4_default: qup-i2c4-default-state {</div><div class='add'>+				pins = "gpio12", "gpio13";</div><div class='add'>+				function = "qup4";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c5_default: qup-i2c5-default-state {</div><div class='add'>+				pins = "gpio14", "gpio15";</div><div class='add'>+				function = "qup5";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi0_default: qup-spi0-default-state {</div><div class='add'>+				pins = "gpio0", "gpio1","gpio2", "gpio3";</div><div class='add'>+				function = "qup0";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi1_default: qup-spi1-default-state {</div><div class='add'>+				pins = "gpio4", "gpio5", "gpio69", "gpio70";</div><div class='add'>+				function = "qup1";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi2_default: qup-spi2-default-state {</div><div class='add'>+				pins = "gpio6", "gpio7", "gpio71", "gpio80";</div><div class='add'>+				function = "qup2";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi3_default: qup-spi3-default-state {</div><div class='add'>+				pins = "gpio8", "gpio9", "gpio10", "gpio11";</div><div class='add'>+				function = "qup3";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi4_default: qup-spi4-default-state {</div><div class='add'>+				pins = "gpio12", "gpio13", "gpio96", "gpio97";</div><div class='add'>+				function = "qup4";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi5_default: qup-spi5-default-state {</div><div class='add'>+				pins = "gpio14", "gpio15", "gpio16", "gpio17";</div><div class='add'>+				function = "qup5";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart0_default: qup-uart0-default-state {</div><div class='add'>+				pins = "gpio0", "gpio1", "gpio2", "gpio3";</div><div class='add'>+				function = "qup0";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart1_default: qup-uart1-default-state {</div><div class='add'>+				pins = "gpio4", "gpio5", "gpio69", "gpio70";</div><div class='add'>+				function = "qup1";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart3_default: qup-uart3-default-state {</div><div class='add'>+				pins = "gpio8", "gpio9", "gpio10", "gpio11";</div><div class='add'>+				function = "qup3";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart4_default: qup-uart4-default-state {</div><div class='add'>+				pins = "gpio12", "gpio13";</div><div class='add'>+				function = "qup4";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart5_default: qup-uart5-default-state {</div><div class='add'>+				pins = "gpio14", "gpio15", "gpio16", "gpio17";</div><div class='add'>+				function = "qup5";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cci0_default: cci0-default-state {</div><div class='add'>+				pins = "gpio22", "gpio23";</div><div class='add'>+				function = "cci_i2c";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cci1_default: cci1-default-state {</div><div class='add'>+				pins = "gpio29", "gpio30";</div><div class='add'>+				function = "cci_i2c";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sdc1_state_on: sdc1-on-state {</div><div class='add'>+				clk-pins {</div><div class='add'>+					pins = "sdc1_clk";</div><div class='add'>+					drive-strength = &lt;16&gt;;</div><div class='add'>+					bias-disable;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cmd-pins {</div><div class='add'>+					pins = "sdc1_cmd";</div><div class='add'>+					drive-strength = &lt;10&gt;;</div><div class='add'>+					bias-pull-up;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				data-pins {</div><div class='add'>+					pins = "sdc1_data";</div><div class='add'>+					drive-strength = &lt;10&gt;;</div><div class='add'>+					bias-pull-up;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				rclk-pins {</div><div class='add'>+					pins = "sdc1_rclk";</div><div class='add'>+					bias-pull-down;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sdc1_state_off: sdc1-off-state {</div><div class='add'>+				clk-pins {</div><div class='add'>+					pins = "sdc1_clk";</div><div class='add'>+					drive-strength = &lt;2&gt;;</div><div class='add'>+					bias-disable;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cmd-pins {</div><div class='add'>+					pins = "sdc1_cmd";</div><div class='add'>+					drive-strength = &lt;2&gt;;</div><div class='add'>+					bias-pull-up;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				data-pins {</div><div class='add'>+					pins = "sdc1_data";</div><div class='add'>+					drive-strength = &lt;2&gt;;</div><div class='add'>+					bias-pull-up;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				rclk-pins {</div><div class='add'>+					pins = "sdc1_rclk";</div><div class='add'>+					bias-pull-down;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sdc2_state_on: sdc2-on-state {</div><div class='add'>+				clk-pins {</div><div class='add'>+					pins = "sdc2_clk";</div><div class='add'>+					drive-strength = &lt;16&gt;;</div><div class='add'>+					bias-disable;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cmd-pins {</div><div class='add'>+					pins = "sdc2_cmd";</div><div class='add'>+					drive-strength = &lt;10&gt;;</div><div class='add'>+					bias-pull-up;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				data-pins {</div><div class='add'>+					pins = "sdc2_data";</div><div class='add'>+					drive-strength = &lt;10&gt;;</div><div class='add'>+					bias-pull-up;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sdc2_state_off: sdc2-off-state {</div><div class='add'>+				clk-pins {</div><div class='add'>+					pins = "sdc2_clk";</div><div class='add'>+					drive-strength = &lt;2&gt;;</div><div class='add'>+					bias-disable;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cmd-pins {</div><div class='add'>+					pins = "sdc2_cmd";</div><div class='add'>+					drive-strength = &lt;2&gt;;</div><div class='add'>+					bias-pull-up;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				data-pins {</div><div class='add'>+					pins = "sdc2_data";</div><div class='add'>+					drive-strength = &lt;2&gt;;</div><div class='add'>+					bias-pull-up;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		lpass_tlmm: pinctrl@a7c0000 {</div><div class='add'>+			compatible = "qcom,qcm2290-lpass-lpi-pinctrl",</div><div class='add'>+				     "qcom,sm6115-lpass-lpi-pinctrl";</div><div class='add'>+			reg = &lt;0x0 0x0a7c0000 0x0 0x20000&gt;,</div><div class='add'>+			      &lt;0x0 0x0a950000 0x0 0x10000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO&gt;;</div><div class='add'>+			clock-names = "audio";</div><div class='add'>+</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;lpass_tlmm 0 0 19&gt;;</div><div class='add'>+</div><div class='add'>+			lpi_i2s2_active: lpi-i2s2-active-state {</div><div class='add'>+				sck-pins {</div><div class='add'>+					pins = "gpio10";</div><div class='add'>+					function = "i2s2_clk";</div><div class='add'>+					bias-disable;</div><div class='add'>+					drive-strength = &lt;8&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				ws-pins {</div><div class='add'>+					pins = "gpio11";</div><div class='add'>+					function = "i2s2_ws";</div><div class='add'>+					bias-disable;</div><div class='add'>+					drive-strength = &lt;8&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				data-pins {</div><div class='add'>+					pins = "gpio12";</div><div class='add'>+					function = "i2s2_data";</div><div class='add'>+					bias-disable;</div><div class='add'>+					drive-strength = &lt;8&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gcc: clock-controller@1400000 {</div><div class='add'>+			compatible = "qcom,gcc-qcm2290";</div><div class='add'>+			reg = &lt;0x0 0x01400000 0x0 0x1f0000&gt;;</div><div class='add'>+			clocks = &lt;&amp;rpmcc RPM_SMD_XO_CLK_SRC&gt;, &lt;&amp;sleep_clk&gt;;</div><div class='add'>+			clock-names = "bi_tcxo", "sleep_clk";</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_hsphy: phy@1613000 {</div><div class='add'>+			compatible = "qcom,qcm2290-qusb2-phy";</div><div class='add'>+			reg = &lt;0x0 0x01613000 0x0 0x180&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_AHB2PHY_USB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;rpmcc RPM_SMD_XO_CLK_SRC&gt;;</div><div class='add'>+			clock-names = "cfg_ahb", "ref";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_QUSB2PHY_PRIM_BCR&gt;;</div><div class='add'>+			nvmem-cells = &lt;&amp;qusb2_hstx_trim&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_qmpphy: phy@1615000 {</div><div class='add'>+			compatible = "qcom,qcm2290-qmp-usb3-phy";</div><div class='add'>+			reg = &lt;0x0 0x01615000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_AHB2PHY_USB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB3_PRIM_CLKREF_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB3_PRIM_PHY_PIPE_CLK&gt;;</div><div class='add'>+			clock-names = "cfg_ahb",</div><div class='add'>+				      "ref",</div><div class='add'>+				      "com_aux",</div><div class='add'>+				      "pipe";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_USB3_PHY_PRIM_SP0_BCR&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR&gt;;</div><div class='add'>+			reset-names = "phy",</div><div class='add'>+				      "phy_phy";</div><div class='add'>+</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-output-names = "usb3_phy_pipe_clk_src";</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+			orientation-switch;</div><div class='add'>+</div><div class='add'>+			qcom,tcsr-reg = &lt;&amp;tcsr_regs 0xb244&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					usb_qmpphy_out: endpoint {</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					usb_qmpphy_usb_ss_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;usb_dwc3_ss&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		system_noc: interconnect@1880000 {</div><div class='add'>+			compatible = "qcom,qcm2290-snoc";</div><div class='add'>+			reg = &lt;0x0 0x01880000 0x0 0x60200&gt;;</div><div class='add'>+			#interconnect-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			qup_virt: interconnect-qup {</div><div class='add'>+				compatible = "qcom,qcm2290-qup-virt";</div><div class='add'>+				#interconnect-cells = &lt;2&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mmnrt_virt: interconnect-mmnrt {</div><div class='add'>+				compatible = "qcom,qcm2290-mmnrt-virt";</div><div class='add'>+				#interconnect-cells = &lt;2&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mmrt_virt: interconnect-mmrt {</div><div class='add'>+				compatible = "qcom,qcm2290-mmrt-virt";</div><div class='add'>+				#interconnect-cells = &lt;2&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		config_noc: interconnect@1900000 {</div><div class='add'>+			compatible = "qcom,qcm2290-cnoc";</div><div class='add'>+			reg = &lt;0x0 0x01900000 0x0 0x8200&gt;;</div><div class='add'>+			#interconnect-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cryptobam: dma-controller@1b04000 {</div><div class='add'>+			compatible = "qcom,bam-v1.7.0";</div><div class='add'>+			reg = &lt;0x0 0x01b04000 0x0 0x24000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;rpmcc RPM_SMD_CE1_CLK&gt;;</div><div class='add'>+			clock-names = "bam_clk";</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+			qcom,ee = &lt;0&gt;;</div><div class='add'>+			qcom,controlled-remotely;</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x0084 0x11&gt;,</div><div class='add'>+				 &lt;&amp;apps_smmu 0x0086 0x11&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		crypto: crypto@1b3a000 {</div><div class='add'>+			compatible = "qcom,qcm2290-qce", "qcom,ipq4019-qce", "qcom,qce";</div><div class='add'>+			reg = &lt;0x0 0x01b3a000 0x0 0x6000&gt;;</div><div class='add'>+			clocks = &lt;&amp;rpmcc RPM_SMD_CE1_CLK&gt;;</div><div class='add'>+			clock-names = "core";</div><div class='add'>+			dmas = &lt;&amp;cryptobam 6&gt;, &lt;&amp;cryptobam 7&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x0084 0x11&gt;,</div><div class='add'>+				 &lt;&amp;apps_smmu 0x0086 0x11&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qfprom@1b44000 {</div><div class='add'>+			compatible = "qcom,qcm2290-qfprom", "qcom,qfprom";</div><div class='add'>+			reg = &lt;0x0 0x01b44000 0x0 0x3000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			qusb2_hstx_trim: hstx-trim@25b {</div><div class='add'>+				reg = &lt;0x25b 0x1&gt;;</div><div class='add'>+				bits = &lt;1 4&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gpu_speed_bin: gpu-speed-bin@2006 {</div><div class='add'>+				reg = &lt;0x2006 0x2&gt;;</div><div class='add'>+				bits = &lt;5 8&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmu@1b8e300 {</div><div class='add'>+			compatible = "qcom,qcm2290-cpu-bwmon", "qcom,sdm845-bwmon";</div><div class='add'>+			reg = &lt;0x0 0x01b8e300 0x0 0x600&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu_bwmon_opp_table&gt;;</div><div class='add'>+			interconnects = &lt;&amp;bimc MASTER_APPSS_PROC RPM_ACTIVE_TAG</div><div class='add'>+					 &amp;bimc SLAVE_EBI1 RPM_ACTIVE_TAG&gt;;</div><div class='add'>+</div><div class='add'>+			cpu_bwmon_opp_table: opp-table {</div><div class='add'>+				compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+				opp-0 {</div><div class='add'>+					opp-peak-kBps = &lt;(200 * 4 * 1000)&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-1 {</div><div class='add'>+					opp-peak-kBps = &lt;(300 * 4 * 1000)&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-2 {</div><div class='add'>+					opp-peak-kBps = &lt;(451 * 4 * 1000)&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-3 {</div><div class='add'>+					opp-peak-kBps = &lt;(547 * 4 * 1000)&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-4 {</div><div class='add'>+					opp-peak-kBps = &lt;(681 * 4 * 1000)&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-5 {</div><div class='add'>+					opp-peak-kBps = &lt;(768 * 4 * 1000)&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-6 {</div><div class='add'>+					opp-peak-kBps = &lt;(1017 * 4 * 1000)&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-7 {</div><div class='add'>+					opp-peak-kBps = &lt;(1353 * 4 * 1000)&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-8 {</div><div class='add'>+					opp-peak-kBps = &lt;(1555 * 4 * 1000)&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-9 {</div><div class='add'>+					opp-peak-kBps = &lt;(1804 * 4 * 1000)&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spmi_bus: spmi@1c40000 {</div><div class='add'>+			compatible = "qcom,spmi-pmic-arb";</div><div class='add'>+			reg = &lt;0x0 0x01c40000 0x0 0x1100&gt;,</div><div class='add'>+			      &lt;0x0 0x01e00000 0x0 0x2000000&gt;,</div><div class='add'>+			      &lt;0x0 0x03e00000 0x0 0x100000&gt;,</div><div class='add'>+			      &lt;0x0 0x03f00000 0x0 0xa0000&gt;,</div><div class='add'>+			      &lt;0x0 0x01c0a000 0x0 0x26000&gt;;</div><div class='add'>+			reg-names = "core",</div><div class='add'>+				    "chnls",</div><div class='add'>+				    "obsrvr",</div><div class='add'>+				    "intr",</div><div class='add'>+				    "cnfg";</div><div class='add'>+			interrupts-extended = &lt;&amp;mpm 86 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "periph_irq";</div><div class='add'>+			qcom,ee = &lt;0&gt;;</div><div class='add'>+			qcom,channel = &lt;0&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;4&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tsens0: thermal-sensor@4411000 {</div><div class='add'>+			compatible = "qcom,qcm2290-tsens", "qcom,tsens-v2";</div><div class='add'>+			reg = &lt;0x0 0x04411000 0x0 0x1ff&gt;,</div><div class='add'>+			      &lt;0x0 0x04410000 0x0 0x8&gt;;</div><div class='add'>+			#qcom,sensors = &lt;10&gt;;</div><div class='add'>+			interrupts-extended = &lt;&amp;mpm 2 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;intc GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "uplow", "critical";</div><div class='add'>+			#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rng: rng@4453000 {</div><div class='add'>+			compatible = "qcom,prng-ee";</div><div class='add'>+			reg = &lt;0x0 0x04453000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;rpmcc RPM_SMD_HWKM_CLK&gt;;</div><div class='add'>+			clock-names = "core";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		bimc: interconnect@4480000 {</div><div class='add'>+			compatible = "qcom,qcm2290-bimc";</div><div class='add'>+			reg = &lt;0x0 0x04480000 0x0 0x80000&gt;;</div><div class='add'>+			#interconnect-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rpm_msg_ram: sram@45f0000 {</div><div class='add'>+			compatible = "qcom,rpm-msg-ram", "mmio-sram";</div><div class='add'>+			reg = &lt;0x0 0x045f0000 0x0 0x7000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges = &lt;0 0x0 0x045f0000 0x7000&gt;;</div><div class='add'>+</div><div class='add'>+			apss_mpm: sram@1b8 {</div><div class='add'>+				reg = &lt;0x1b8 0x48&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sram@4690000 {</div><div class='add'>+			compatible = "qcom,rpm-stats";</div><div class='add'>+			reg = &lt;0x0 0x04690000 0x0 0x10000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sdhc_1: mmc@4744000 {</div><div class='add'>+			compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5";</div><div class='add'>+			reg = &lt;0x0 0x04744000 0x0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0x04745000 0x0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0x04748000 0x0 0x8000&gt;;</div><div class='add'>+			reg-names = "hc",</div><div class='add'>+				    "cqhci",</div><div class='add'>+				    "ice";</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "hc_irq", "pwr_irq";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_SDCC1_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_SDCC1_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;rpmcc RPM_SMD_XO_CLK_SRC&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_SDCC1_ICE_CORE_CLK&gt;;</div><div class='add'>+			clock-names = "iface",</div><div class='add'>+				      "core",</div><div class='add'>+				      "xo",</div><div class='add'>+				      "ice";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_SDCC1_BCR&gt;;</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;rpmpd QCM2290_VDDCX&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;sdhc1_opp_table&gt;;</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0xc0 0x0&gt;;</div><div class='add'>+			interconnects = &lt;&amp;system_noc MASTER_SDCC_1 RPM_ALWAYS_TAG</div><div class='add'>+					 &amp;bimc SLAVE_EBI1 RPM_ALWAYS_TAG&gt;,</div><div class='add'>+					&lt;&amp;bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG</div><div class='add'>+					 &amp;config_noc SLAVE_SDCC_1 RPM_ALWAYS_TAG&gt;;</div><div class='add'>+			interconnect-names = "sdhc-ddr",</div><div class='add'>+					     "cpu-sdhc";</div><div class='add'>+</div><div class='add'>+			qcom,dll-config = &lt;0x000f642c&gt;;</div><div class='add'>+			qcom,ddr-config = &lt;0x80040868&gt;;</div><div class='add'>+			bus-width = &lt;8&gt;;</div><div class='add'>+</div><div class='add'>+			mmc-ddr-1_8v;</div><div class='add'>+			mmc-hs200-1_8v;</div><div class='add'>+			mmc-hs400-1_8v;</div><div class='add'>+			mmc-hs400-enhanced-strobe;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			sdhc1_opp_table: opp-table {</div><div class='add'>+				compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+				opp-100000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;100000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmpd_opp_low_svs&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;250000 133320&gt;;</div><div class='add'>+					opp-avg-kBps = &lt;102400 65000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-192000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;192000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmpd_opp_low_svs&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;800000 300000&gt;;</div><div class='add'>+					opp-avg-kBps = &lt;204800 200000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-384000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;384000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmpd_opp_svs_plus&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;800000 300000&gt;;</div><div class='add'>+					opp-avg-kBps = &lt;204800 200000&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sdhc_2: mmc@4784000 {</div><div class='add'>+			compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5";</div><div class='add'>+			reg = &lt;0x0 0x04784000 0x0 0x1000&gt;;</div><div class='add'>+			reg-names = "hc";</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "hc_irq", "pwr_irq";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_SDCC2_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_SDCC2_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;rpmcc RPM_SMD_XO_CLK_SRC&gt;;</div><div class='add'>+			clock-names = "iface",</div><div class='add'>+				      "core",</div><div class='add'>+				      "xo";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_SDCC2_BCR&gt;;</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;rpmpd QCM2290_VDDCX&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;sdhc2_opp_table&gt;;</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0xa0 0x0&gt;;</div><div class='add'>+			interconnects = &lt;&amp;system_noc MASTER_SDCC_2 RPM_ALWAYS_TAG</div><div class='add'>+					 &amp;bimc SLAVE_EBI1 RPM_ALWAYS_TAG&gt;,</div><div class='add'>+					&lt;&amp;bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG</div><div class='add'>+					 &amp;config_noc SLAVE_SDCC_2 RPM_ALWAYS_TAG&gt;;</div><div class='add'>+			interconnect-names = "sdhc-ddr",</div><div class='add'>+					     "cpu-sdhc";</div><div class='add'>+</div><div class='add'>+			qcom,dll-config = &lt;0x0007642c&gt;;</div><div class='add'>+			qcom,ddr-config = &lt;0x80040868&gt;;</div><div class='add'>+			bus-width = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			sdhc2_opp_table: opp-table {</div><div class='add'>+				compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+				opp-100000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;100000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmpd_opp_low_svs&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;250000 133320&gt;;</div><div class='add'>+					opp-avg-kBps = &lt;261438 150000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-202000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;202000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmpd_opp_svs_plus&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;800000 300000&gt;;</div><div class='add'>+					opp-avg-kBps = &lt;261438 300000&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpi_dma0: dma-controller@4a00000 {</div><div class='add'>+			compatible = "qcom,qcm2290-gpi-dma", "qcom,sm6350-gpi-dma";</div><div class='add'>+			reg = &lt;0x0 0x04a00000 0x0 0x60000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			dma-channels = &lt;10&gt;;</div><div class='add'>+			dma-channel-mask = &lt;0x1f&gt;;</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0xf6 0x0&gt;;</div><div class='add'>+			#dma-cells = &lt;3&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qupv3_id_0: geniqup@4ac0000 {</div><div class='add'>+			compatible = "qcom,geni-se-qup";</div><div class='add'>+			reg = &lt;0x0 0x04ac0000 0x0 0x2000&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_QUPV3_WRAP_0_M_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_QUPV3_WRAP_0_S_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "m-ahb", "s-ahb";</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0xe3 0x0&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			i2c0: i2c@4a80000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0x0 0x04a80000 0x0 0x4000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S0_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c0_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 0 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 0 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				interconnects = &lt;&amp;qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG</div><div class='add'>+						 &amp;qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG&gt;,</div><div class='add'>+						&lt;&amp;bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG&gt;,</div><div class='add'>+						&lt;&amp;system_noc MASTER_QUP_0 RPM_ALWAYS_TAG</div><div class='add'>+						 &amp;bimc SLAVE_EBI1 RPM_ALWAYS_TAG&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi0: spi@4a80000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0x0 0x04a80000 0x0 0x4000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S0_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi0_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 0 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 0 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				interconnects = &lt;&amp;qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG</div><div class='add'>+						 &amp;qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG&gt;,</div><div class='add'>+						&lt;&amp;bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart0: serial@4a80000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0x0 0x04a80000 0x0 0x4000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S0_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart0_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG</div><div class='add'>+						 &amp;qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG&gt;,</div><div class='add'>+						&lt;&amp;bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c1: i2c@4a84000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0x0 0x04a84000 0x0 0x4000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S1_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c1_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 1 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 1 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				interconnects = &lt;&amp;qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG</div><div class='add'>+						 &amp;qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG&gt;,</div><div class='add'>+						&lt;&amp;bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG&gt;,</div><div class='add'>+						&lt;&amp;system_noc MASTER_QUP_0 RPM_ALWAYS_TAG</div><div class='add'>+						 &amp;bimc SLAVE_EBI1 RPM_ALWAYS_TAG&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi1: spi@4a84000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0x0 0x04a84000 0x0 0x4000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S1_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi1_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 1 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 1 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				interconnects = &lt;&amp;qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG</div><div class='add'>+						 &amp;qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG&gt;,</div><div class='add'>+						&lt;&amp;bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart1: serial@4a84000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0x0 0x04a84000 0x0 0x4000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S1_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart1_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG</div><div class='add'>+						 &amp;qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG&gt;,</div><div class='add'>+						&lt;&amp;bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c2: i2c@4a88000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0x0 0x04a88000 0x0 0x4000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S2_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c2_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 2 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 2 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				interconnects = &lt;&amp;qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG</div><div class='add'>+						 &amp;qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG&gt;,</div><div class='add'>+						&lt;&amp;bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG&gt;,</div><div class='add'>+						&lt;&amp;system_noc MASTER_QUP_0 RPM_ALWAYS_TAG</div><div class='add'>+						 &amp;bimc SLAVE_EBI1 RPM_ALWAYS_TAG&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi2: spi@4a88000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0x0 0x04a88000 0x0 0x4000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S2_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi2_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 2 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 2 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				interconnects = &lt;&amp;qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG</div><div class='add'>+						 &amp;qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG&gt;,</div><div class='add'>+						&lt;&amp;bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c3: i2c@4a8c000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0x0 0x04a8c000 0x0 0x4000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S3_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c3_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 3 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 3 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				interconnects = &lt;&amp;qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG</div><div class='add'>+						 &amp;qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG&gt;,</div><div class='add'>+						&lt;&amp;bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG&gt;,</div><div class='add'>+						&lt;&amp;system_noc MASTER_QUP_0 RPM_ALWAYS_TAG</div><div class='add'>+						 &amp;bimc SLAVE_EBI1 RPM_ALWAYS_TAG&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi3: spi@4a8c000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0x0 0x04a8c000 0x0 0x4000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S3_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi3_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 3 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 3 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				interconnects = &lt;&amp;qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG</div><div class='add'>+						 &amp;qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG&gt;,</div><div class='add'>+						&lt;&amp;bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart3: serial@4a8c000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0x0 0x04a8c000 0x0 0x4000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S3_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart3_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG</div><div class='add'>+						 &amp;qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG&gt;,</div><div class='add'>+						&lt;&amp;bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c4: i2c@4a90000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0x0 0x04a90000 0x0 0x4000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S4_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c4_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 4 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 4 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				interconnects = &lt;&amp;qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG</div><div class='add'>+						 &amp;qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG&gt;,</div><div class='add'>+						&lt;&amp;bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG&gt;,</div><div class='add'>+						&lt;&amp;system_noc MASTER_QUP_0 RPM_ALWAYS_TAG</div><div class='add'>+						 &amp;bimc SLAVE_EBI1 RPM_ALWAYS_TAG&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi4: spi@4a90000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0x0 0x04a90000 0x0 0x4000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S4_CLK&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi4_default&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 4 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 4 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				interconnects = &lt;&amp;qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG</div><div class='add'>+						 &amp;qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG&gt;,</div><div class='add'>+						&lt;&amp;bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart4: serial@4a90000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0x0 0x04a90000 0x0 0x4000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S4_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart4_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG</div><div class='add'>+						 &amp;qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG&gt;,</div><div class='add'>+						&lt;&amp;bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c5: i2c@4a94000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0x0 0x04a94000 0x0 0x4000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S5_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c5_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 5 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 5 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				interconnects = &lt;&amp;qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG</div><div class='add'>+						 &amp;qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG&gt;,</div><div class='add'>+						&lt;&amp;bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG&gt;,</div><div class='add'>+						&lt;&amp;system_noc MASTER_QUP_0 RPM_ALWAYS_TAG</div><div class='add'>+						 &amp;bimc SLAVE_EBI1 RPM_ALWAYS_TAG&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi5: spi@4a94000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0x0 0x04a94000 0x0 0x4000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S5_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi5_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 5 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 5 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				interconnects = &lt;&amp;qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG</div><div class='add'>+						 &amp;qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG&gt;,</div><div class='add'>+						&lt;&amp;bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart5: serial@4a94000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0x0 0x04a94000 0x0 0x4000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S5_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart5_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG</div><div class='add'>+						 &amp;qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG&gt;,</div><div class='add'>+						&lt;&amp;bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb: usb@4ef8800 {</div><div class='add'>+			compatible = "qcom,qcm2290-dwc3", "qcom,dwc3";</div><div class='add'>+			reg = &lt;0x0 0x04ef8800 0x0 0x400&gt;;</div><div class='add'>+			interrupts-extended = &lt;&amp;intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;mpm 12 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "hs_phy_irq",</div><div class='add'>+					  "ss_phy_irq";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB30_PRIM_MASTER_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB30_PRIM_SLEEP_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB30_PRIM_MOCK_UTMI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB3_PRIM_CLKREF_CLK&gt;;</div><div class='add'>+			clock-names = "cfg_noc",</div><div class='add'>+				      "core",</div><div class='add'>+				      "iface",</div><div class='add'>+				      "sleep",</div><div class='add'>+				      "mock_utmi",</div><div class='add'>+				      "xo";</div><div class='add'>+</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_USB30_PRIM_MOCK_UTMI_CLK&gt;,</div><div class='add'>+					  &lt;&amp;gcc GCC_USB30_PRIM_MASTER_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;19200000&gt;, &lt;133333333&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_USB30_PRIM_BCR&gt;;</div><div class='add'>+			power-domains = &lt;&amp;gcc GCC_USB30_PRIM_GDSC&gt;;</div><div class='add'>+			/* TODO: USB&lt;-&gt;IPA path */</div><div class='add'>+			interconnects = &lt;&amp;system_noc MASTER_USB3_0 RPM_ALWAYS_TAG</div><div class='add'>+					 &amp;bimc SLAVE_EBI1 RPM_ALWAYS_TAG&gt;,</div><div class='add'>+					&lt;&amp;bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG</div><div class='add'>+					 &amp;config_noc SLAVE_USB3 RPM_ALWAYS_TAG&gt;;</div><div class='add'>+			interconnect-names = "usb-ddr",</div><div class='add'>+					     "apps-usb";</div><div class='add'>+			wakeup-source;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			usb_dwc3: usb@4e00000 {</div><div class='add'>+				compatible = "snps,dwc3";</div><div class='add'>+				reg = &lt;0x0 0x04e00000 0x0 0xcd00&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				phys = &lt;&amp;usb_hsphy&gt;, &lt;&amp;usb_qmpphy&gt;;</div><div class='add'>+				phy-names = "usb2-phy", "usb3-phy";</div><div class='add'>+				iommus = &lt;&amp;apps_smmu 0x120 0x0&gt;;</div><div class='add'>+				snps,dis_u2_susphy_quirk;</div><div class='add'>+				snps,dis_enblslpm_quirk;</div><div class='add'>+				snps,has-lpm-erratum;</div><div class='add'>+				snps,hird-threshold = /bits/ 8 &lt;0x10&gt;;</div><div class='add'>+				snps,usb3_lpm_capable;</div><div class='add'>+				snps,parkmode-disable-ss-quirk;</div><div class='add'>+				maximum-speed = "super-speed";</div><div class='add'>+				dr_mode = "otg";</div><div class='add'>+				usb-role-switch;</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						usb_dwc3_hs: endpoint {</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						usb_dwc3_ss: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;usb_qmpphy_usb_ss_in&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu: gpu@5900000 {</div><div class='add'>+			compatible = "qcom,adreno-07000200", "qcom,adreno";</div><div class='add'>+			reg = &lt;0x0 0x05900000 0x0 0x40000&gt;;</div><div class='add'>+			reg-names = "kgsl_3d0_reg_memory";</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gpucc GPU_CC_GX_GFX3D_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gpucc GPU_CC_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_BIMC_GPU_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_GPU_MEMNOC_GFX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gpucc GPU_CC_CX_GMU_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gpucc GPU_CC_CXO_CLK&gt;;</div><div class='add'>+			clock-names = "core",</div><div class='add'>+				      "iface",</div><div class='add'>+				      "mem_iface",</div><div class='add'>+				      "alt_mem_iface",</div><div class='add'>+				      "gmu",</div><div class='add'>+				      "xo";</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;bimc MASTER_GFX3D RPM_ALWAYS_TAG</div><div class='add'>+					 &amp;bimc SLAVE_EBI1 RPM_ALWAYS_TAG&gt;;</div><div class='add'>+			interconnect-names = "gfx-mem";</div><div class='add'>+</div><div class='add'>+			iommus = &lt;&amp;adreno_smmu 0 1&gt;,</div><div class='add'>+				 &lt;&amp;adreno_smmu 2 0&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;gpu_opp_table&gt;;</div><div class='add'>+			power-domains = &lt;&amp;rpmpd QCM2290_VDDCX&gt;;</div><div class='add'>+			qcom,gmu = &lt;&amp;gmu_wrapper&gt;;</div><div class='add'>+</div><div class='add'>+			nvmem-cells = &lt;&amp;gpu_speed_bin&gt;;</div><div class='add'>+			nvmem-cell-names = "speed_bin";</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			gpu_zap_shader: zap-shader {</div><div class='add'>+				memory-region = &lt;&amp;pil_gpu_mem&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gpu_opp_table: opp-table {</div><div class='add'>+				compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+				/* TODO: Scale RPM_SMD_BIMC_GPU_CLK w/ turbo freqs */</div><div class='add'>+				opp-1123200000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;1123200000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmpd_opp_turbo_plus&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;6881000&gt;;</div><div class='add'>+					opp-supported-hw = &lt;0x3&gt;;</div><div class='add'>+					turbo-mode;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-1017600000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;1017600000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmpd_opp_turbo&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;6881000&gt;;</div><div class='add'>+					opp-supported-hw = &lt;0x3&gt;;</div><div class='add'>+					turbo-mode;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-921600000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;921600000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmpd_opp_nom_plus&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;6881000&gt;;</div><div class='add'>+					opp-supported-hw = &lt;0x3&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-844800000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;844800000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmpd_opp_nom&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;6881000&gt;;</div><div class='add'>+					opp-supported-hw = &lt;0x7&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-672000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;672000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmpd_opp_svs_plus&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;3879000&gt;;</div><div class='add'>+					opp-supported-hw = &lt;0xf&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-537600000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;537600000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmpd_opp_svs&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;2929000&gt;;</div><div class='add'>+					opp-supported-hw = &lt;0xf&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-355200000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;355200000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmpd_opp_low_svs&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;1720000&gt;;</div><div class='add'>+					opp-supported-hw = &lt;0xf&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gmu_wrapper: gmu@596a000 {</div><div class='add'>+			compatible = "qcom,adreno-gmu-wrapper";</div><div class='add'>+			reg = &lt;0x0 0x0596a000 0x0 0x30000&gt;;</div><div class='add'>+			reg-names = "gmu";</div><div class='add'>+			power-domains = &lt;&amp;gpucc GPU_CX_GDSC&gt;,</div><div class='add'>+					&lt;&amp;gpucc GPU_GX_GDSC&gt;;</div><div class='add'>+			power-domain-names = "cx",</div><div class='add'>+					     "gx";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpucc: clock-controller@5990000 {</div><div class='add'>+			compatible = "qcom,qcm2290-gpucc";</div><div class='add'>+			reg = &lt;0x0 0x05990000 0x0 0x9000&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_GPU_CFG_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;rpmcc RPM_SMD_XO_CLK_SRC&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_GPU_GPLL0_CLK_SRC&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_GPU_GPLL0_DIV_CLK_SRC&gt;;</div><div class='add'>+			power-domains = &lt;&amp;rpmpd QCM2290_VDDCX&gt;;</div><div class='add'>+			required-opps = &lt;&amp;rpmpd_opp_low_svs&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		adreno_smmu: iommu@59a0000 {</div><div class='add'>+			compatible = "qcom,qcm2290-smmu-500", "qcom,adreno-smmu",</div><div class='add'>+				     "qcom,smmu-500", "arm,mmu-500";</div><div class='add'>+			reg = &lt;0x0 0x059a0000 0x0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_GPU_MEMNOC_GFX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_GPU_SNOC_DVM_GFX_CLK&gt;;</div><div class='add'>+			clock-names = "mem",</div><div class='add'>+				      "hlos",</div><div class='add'>+				      "iface";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;gpucc GPU_CX_GDSC&gt;;</div><div class='add'>+</div><div class='add'>+			#global-interrupts = &lt;1&gt;;</div><div class='add'>+			#iommu-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cci: cci@5c1b000 {</div><div class='add'>+			compatible = "qcom,qcm2290-cci", "qcom,msm8996-cci";</div><div class='add'>+			reg = &lt;0x0 0x5c1b000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 206 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_CAMSS_TOP_AHB_CLK&gt;, &lt;&amp;gcc GCC_CAMSS_CCI_0_CLK&gt;;</div><div class='add'>+			clock-names = "ahb", "cci";</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_CAMSS_CCI_0_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;37500000&gt;;</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;gcc GCC_CAMSS_TOP_GDSC&gt;;</div><div class='add'>+</div><div class='add'>+			pinctrl-0 = &lt;&amp;cci0_default &amp;cci1_default&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			cci_i2c0: i2c-bus@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				clock-frequency = &lt;400000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cci_i2c1: i2c-bus@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				clock-frequency = &lt;400000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		camss: camss@5c11000 {</div><div class='add'>+			compatible = "qcom,qcm2290-camss";</div><div class='add'>+</div><div class='add'>+			reg = &lt;0x0 0x5c11000 0x0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0x5c6e000 0x0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0x5c75000 0x0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0x5c52000 0x0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0x5c53000 0x0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0x5c66000 0x0 0x400&gt;,</div><div class='add'>+			      &lt;0x0 0x5c68000 0x0 0x400&gt;,</div><div class='add'>+			      &lt;0x0 0x5c6f000 0x0 0x4000&gt;,</div><div class='add'>+			      &lt;0x0 0x5c76000 0x0 0x4000&gt;;</div><div class='add'>+			reg-names = "top",</div><div class='add'>+				    "csid0",</div><div class='add'>+				    "csid1",</div><div class='add'>+				    "csiphy0",</div><div class='add'>+				    "csiphy1",</div><div class='add'>+				    "csitpg0",</div><div class='add'>+				    "csitpg1",</div><div class='add'>+				    "vfe0",</div><div class='add'>+				    "vfe1";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_CAMERA_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_CAMSS_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_CAMSS_NRT_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_CAMSS_RT_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_CAMSS_TFE_0_CSID_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_CAMSS_TFE_1_CSID_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_CAMSS_CPHY_0_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_CAMSS_CSI0PHYTIMER_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_CAMSS_CPHY_1_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_CAMSS_CSI1PHYTIMER_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_CAMSS_TOP_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_CAMSS_TFE_0_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_CAMSS_TFE_1_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK&gt; ;</div><div class='add'>+			clock-names = "ahb",</div><div class='add'>+				      "axi",</div><div class='add'>+				      "camnoc_nrt_axi",</div><div class='add'>+				      "camnoc_rt_axi",</div><div class='add'>+				      "csi0",</div><div class='add'>+				      "csi1",</div><div class='add'>+				      "csiphy0",</div><div class='add'>+				      "csiphy0_timer",</div><div class='add'>+				      "csiphy1",</div><div class='add'>+				      "csiphy1_timer",</div><div class='add'>+				      "top_ahb",</div><div class='add'>+				      "vfe0",</div><div class='add'>+				      "vfe0_cphy_rx",</div><div class='add'>+				      "vfe1",</div><div class='add'>+				      "vfe1_cphy_rx";</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 210 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 212 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 72 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 73 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 309 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 310 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 211 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 213 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			interrupt-names = "csid0",</div><div class='add'>+					  "csid1",</div><div class='add'>+					  "csiphy0",</div><div class='add'>+					  "csiphy1",</div><div class='add'>+					  "csitpg0",</div><div class='add'>+					  "csitpg1",</div><div class='add'>+					  "vfe0",</div><div class='add'>+					  "vfe1";</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;bimc MASTER_APPSS_PROC RPM_ACTIVE_TAG</div><div class='add'>+					 &amp;config_noc SLAVE_CAMERA_CFG RPM_ACTIVE_TAG&gt;,</div><div class='add'>+					&lt;&amp;mmrt_virt MASTER_CAMNOC_HF RPM_ALWAYS_TAG</div><div class='add'>+					 &amp;bimc SLAVE_EBI1 RPM_ALWAYS_TAG&gt;,</div><div class='add'>+					&lt;&amp;mmnrt_virt MASTER_CAMNOC_SF RPM_ALWAYS_TAG</div><div class='add'>+					 &amp;bimc SLAVE_EBI1 RPM_ALWAYS_TAG&gt;;</div><div class='add'>+			interconnect-names = "ahb",</div><div class='add'>+					     "hf_mnoc",</div><div class='add'>+					     "sf_mnoc";</div><div class='add'>+</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x400 0x0&gt;,</div><div class='add'>+				 &lt;&amp;apps_smmu 0x800 0x0&gt;,</div><div class='add'>+				 &lt;&amp;apps_smmu 0x820 0x0&gt;,</div><div class='add'>+				 &lt;&amp;apps_smmu 0x840 0x0&gt;;</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;gcc GCC_CAMSS_TOP_GDSC&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdss: display-subsystem@5e00000 {</div><div class='add'>+			compatible = "qcom,qcm2290-mdss";</div><div class='add'>+			reg = &lt;0x0 0x05e00000 0x0 0x1000&gt;;</div><div class='add'>+			reg-names = "mdss";</div><div class='add'>+			interrupts = &lt;GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_DISP_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_DISP_HF_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;dispcc DISP_CC_MDSS_MDP_CLK&gt;;</div><div class='add'>+			clock-names = "iface",</div><div class='add'>+				      "bus",</div><div class='add'>+				      "core";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;dispcc DISP_CC_MDSS_CORE_BCR&gt;;</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;dispcc MDSS_GDSC&gt;;</div><div class='add'>+</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x420 0x2&gt;,</div><div class='add'>+				 &lt;&amp;apps_smmu 0x421 0x0&gt;;</div><div class='add'>+			interconnects = &lt;&amp;mmrt_virt MASTER_MDP0 RPM_ALWAYS_TAG</div><div class='add'>+					 &amp;bimc SLAVE_EBI1 RPM_ALWAYS_TAG&gt;,</div><div class='add'>+					&lt;&amp;bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG</div><div class='add'>+					 &amp;config_noc SLAVE_DISPLAY_CFG RPM_ALWAYS_TAG&gt;;</div><div class='add'>+			interconnect-names = "mdp0-mem",</div><div class='add'>+					     "cpu-cfg";</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			mdp: display-controller@5e01000 {</div><div class='add'>+				compatible = "qcom,qcm2290-dpu";</div><div class='add'>+				reg = &lt;0x0 0x05e01000 0x0 0x8f000&gt;,</div><div class='add'>+				      &lt;0x0 0x05eb0000 0x0 0x3000&gt;;</div><div class='add'>+				reg-names = "mdp",</div><div class='add'>+					    "vbif";</div><div class='add'>+</div><div class='add'>+				interrupt-parent = &lt;&amp;mdss&gt;;</div><div class='add'>+				interrupts = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_DISP_HF_AXI_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc DISP_CC_MDSS_AHB_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc DISP_CC_MDSS_MDP_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc DISP_CC_MDSS_MDP_LUT_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc DISP_CC_MDSS_VSYNC_CLK&gt;;</div><div class='add'>+				clock-names = "bus",</div><div class='add'>+					      "iface",</div><div class='add'>+					      "core",</div><div class='add'>+					      "lut",</div><div class='add'>+					      "vsync";</div><div class='add'>+</div><div class='add'>+				operating-points-v2 = &lt;&amp;mdp_opp_table&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmpd QCM2290_VDDCX&gt;;</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+						dpu_intf1_out: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mdss_dsi0_in&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				mdp_opp_table: opp-table {</div><div class='add'>+					compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+					opp-19200000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;19200000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmpd_opp_min_svs&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					opp-192000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;192000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmpd_opp_low_svs&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					opp-256000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;256000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmpd_opp_svs&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					opp-307200000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;307200000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmpd_opp_svs_plus&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					opp-384000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;384000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmpd_opp_nom&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mdss_dsi0: dsi@5e94000 {</div><div class='add'>+				compatible = "qcom,qcm2290-dsi-ctrl", "qcom,mdss-dsi-ctrl";</div><div class='add'>+				reg = &lt;0x0 0x05e94000 0x0 0x400&gt;;</div><div class='add'>+				reg-names = "dsi_ctrl";</div><div class='add'>+</div><div class='add'>+				interrupt-parent = &lt;&amp;mdss&gt;;</div><div class='add'>+				interrupts = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;dispcc DISP_CC_MDSS_BYTE0_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc DISP_CC_MDSS_BYTE0_INTF_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc DISP_CC_MDSS_PCLK0_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc DISP_CC_MDSS_ESC0_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc DISP_CC_MDSS_AHB_CLK&gt;,</div><div class='add'>+					 &lt;&amp;gcc GCC_DISP_HF_AXI_CLK&gt;;</div><div class='add'>+				clock-names = "byte",</div><div class='add'>+					      "byte_intf",</div><div class='add'>+					      "pixel",</div><div class='add'>+					      "core",</div><div class='add'>+					      "iface",</div><div class='add'>+					      "bus";</div><div class='add'>+</div><div class='add'>+				assigned-clocks = &lt;&amp;dispcc DISP_CC_MDSS_BYTE0_CLK_SRC&gt;,</div><div class='add'>+						  &lt;&amp;dispcc DISP_CC_MDSS_PCLK0_CLK_SRC&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;mdss_dsi0_phy DSI_BYTE_PLL_CLK&gt;,</div><div class='add'>+							 &lt;&amp;mdss_dsi0_phy DSI_PIXEL_PLL_CLK&gt;;</div><div class='add'>+</div><div class='add'>+				operating-points-v2 = &lt;&amp;dsi_opp_table&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmpd QCM2290_VDDCX&gt;;</div><div class='add'>+				phys = &lt;&amp;mdss_dsi0_phy&gt;;</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				dsi_opp_table: opp-table {</div><div class='add'>+					compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+					opp-19200000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;19200000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmpd_opp_min_svs&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					opp-164000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;164000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmpd_opp_low_svs&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					opp-187500000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;187500000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmpd_opp_svs&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						mdss_dsi0_in: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;dpu_intf1_out&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						mdss_dsi0_out: endpoint {</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mdss_dsi0_phy: phy@5e94400 {</div><div class='add'>+				compatible = "qcom,dsi-phy-14nm-2290";</div><div class='add'>+				reg = &lt;0x0 0x05e94400 0x0 0x100&gt;,</div><div class='add'>+				      &lt;0x0 0x05e94500 0x0 0x300&gt;,</div><div class='add'>+				      &lt;0x0 0x05e94800 0x0 0x188&gt;;</div><div class='add'>+				reg-names = "dsi_phy",</div><div class='add'>+					    "dsi_phy_lane",</div><div class='add'>+					    "dsi_pll";</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;dispcc DISP_CC_MDSS_AHB_CLK&gt;,</div><div class='add'>+					 &lt;&amp;rpmcc RPM_SMD_XO_CLK_SRC&gt;;</div><div class='add'>+				clock-names = "iface",</div><div class='add'>+					      "ref";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmpd QCM2290_VDDMX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmpd_opp_nom&gt;;</div><div class='add'>+</div><div class='add'>+				#clock-cells = &lt;1&gt;;</div><div class='add'>+				#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dispcc: clock-controller@5f00000 {</div><div class='add'>+			compatible = "qcom,qcm2290-dispcc";</div><div class='add'>+			reg = &lt;0x0 0x05f00000 0x0 0x20000&gt;;</div><div class='add'>+			clocks = &lt;&amp;rpmcc RPM_SMD_XO_CLK_SRC&gt;,</div><div class='add'>+				 &lt;&amp;rpmcc RPM_SMD_XO_A_CLK_SRC&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_DISP_GPLL0_CLK_SRC&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_DISP_GPLL0_DIV_CLK_SRC&gt;,</div><div class='add'>+				 &lt;&amp;mdss_dsi0_phy DSI_BYTE_PLL_CLK&gt;,</div><div class='add'>+				 &lt;&amp;mdss_dsi0_phy DSI_PIXEL_PLL_CLK&gt;;</div><div class='add'>+			clock-names = "bi_tcxo",</div><div class='add'>+				      "bi_tcxo_ao",</div><div class='add'>+				      "gcc_disp_gpll0_clk_src",</div><div class='add'>+				      "gcc_disp_gpll0_div_clk_src",</div><div class='add'>+				      "dsi0_phy_pll_out_byteclk",</div><div class='add'>+				      "dsi0_phy_pll_out_dsiclk";</div><div class='add'>+			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		remoteproc_mpss: remoteproc@6080000 {</div><div class='add'>+			compatible = "qcom,qcm2290-mpss-pas", "qcom,sm6115-mpss-pas";</div><div class='add'>+			reg = &lt;0x0 0x06080000 0x0 0x100&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts-extended = &lt;&amp;intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			interrupt-names = "wdog",</div><div class='add'>+					  "fatal",</div><div class='add'>+					  "ready",</div><div class='add'>+					  "handover",</div><div class='add'>+					  "stop-ack",</div><div class='add'>+					  "shutdown-ack";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;rpmcc RPM_SMD_XO_CLK_SRC&gt;;</div><div class='add'>+			clock-names = "xo";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;rpmpd QCM2290_VDDCX&gt;;</div><div class='add'>+</div><div class='add'>+			memory-region = &lt;&amp;pil_modem_mem&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,smem-states = &lt;&amp;modem_smp2p_out 0&gt;;</div><div class='add'>+			qcom,smem-state-names = "stop";</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			glink-edge {</div><div class='add'>+				interrupts = &lt;GIC_SPI 68 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				label = "mpss";</div><div class='add'>+				qcom,remote-pid = &lt;1&gt;;</div><div class='add'>+				mboxes = &lt;&amp;apcs_glb 12&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		remoteproc_adsp: remoteproc@ab00000 {</div><div class='add'>+			compatible = "qcom,qcm2290-adsp-pas", "qcom,sm6115-adsp-pas";</div><div class='add'>+			reg = &lt;0x0 0x0ab00000 0x0 0x100&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts-extended = &lt;&amp;intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			interrupt-names = "wdog",</div><div class='add'>+					  "fatal",</div><div class='add'>+					  "ready",</div><div class='add'>+					  "handover",</div><div class='add'>+					  "stop-ack";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;rpmcc RPM_SMD_XO_CLK_SRC&gt;;</div><div class='add'>+			clock-names = "xo";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;rpmpd QCM2290_VDD_LPI_CX&gt;,</div><div class='add'>+					&lt;&amp;rpmpd QCM2290_VDD_LPI_MX&gt;;</div><div class='add'>+</div><div class='add'>+			memory-region = &lt;&amp;pil_adsp_mem&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,smem-states = &lt;&amp;adsp_smp2p_out 0&gt;;</div><div class='add'>+			qcom,smem-state-names = "stop";</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			glink-edge {</div><div class='add'>+				interrupts = &lt;GIC_SPI 277 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				label = "lpass";</div><div class='add'>+				qcom,remote-pid = &lt;2&gt;;</div><div class='add'>+				mboxes = &lt;&amp;apcs_glb 8&gt;;</div><div class='add'>+</div><div class='add'>+				apr {</div><div class='add'>+					compatible = "qcom,apr-v2";</div><div class='add'>+					qcom,glink-channels = "apr_audio_svc";</div><div class='add'>+					qcom,domain = &lt;APR_DOMAIN_ADSP&gt;;</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					service@3 {</div><div class='add'>+						reg = &lt;APR_SVC_ADSP_CORE&gt;;</div><div class='add'>+						compatible = "qcom,q6core";</div><div class='add'>+						qcom,protection-domain = "avs/audio",</div><div class='add'>+									 "msm/adsp/audio_pd";</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					q6afe: service@4 {</div><div class='add'>+						compatible = "qcom,q6afe";</div><div class='add'>+						reg = &lt;APR_SVC_AFE&gt;;</div><div class='add'>+						qcom,protection-domain = "avs/audio",</div><div class='add'>+									 "msm/adsp/audio_pd";</div><div class='add'>+						q6afedai: dais {</div><div class='add'>+							compatible = "qcom,q6afe-dais";</div><div class='add'>+							#address-cells = &lt;1&gt;;</div><div class='add'>+							#size-cells = &lt;0&gt;;</div><div class='add'>+							#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						q6afecc: clock-controller {</div><div class='add'>+							compatible = "qcom,q6afe-clocks";</div><div class='add'>+							#clock-cells = &lt;2&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					q6asm: service@7 {</div><div class='add'>+						compatible = "qcom,q6asm";</div><div class='add'>+						reg = &lt;APR_SVC_ASM&gt;;</div><div class='add'>+						qcom,protection-domain = "avs/audio",</div><div class='add'>+									 "msm/adsp/audio_pd";</div><div class='add'>+						q6asmdai: dais {</div><div class='add'>+							compatible = "qcom,q6asm-dais";</div><div class='add'>+							#address-cells = &lt;1&gt;;</div><div class='add'>+							#size-cells = &lt;0&gt;;</div><div class='add'>+							#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+							iommus = &lt;&amp;apps_smmu 0x1c1 0x0&gt;;</div><div class='add'>+</div><div class='add'>+							dai@0 {</div><div class='add'>+								reg = &lt;MSM_FRONTEND_DAI_MULTIMEDIA1&gt;;</div><div class='add'>+							};</div><div class='add'>+</div><div class='add'>+							dai@1 {</div><div class='add'>+								reg = &lt;MSM_FRONTEND_DAI_MULTIMEDIA2&gt;;</div><div class='add'>+							};</div><div class='add'>+</div><div class='add'>+							dai@2 {</div><div class='add'>+								reg = &lt;MSM_FRONTEND_DAI_MULTIMEDIA3&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					q6adm: service@8 {</div><div class='add'>+						compatible = "qcom,q6adm";</div><div class='add'>+						reg = &lt;APR_SVC_ADM&gt;;</div><div class='add'>+						qcom,protection-domain = "avs/audio",</div><div class='add'>+									 "msm/adsp/audio_pd";</div><div class='add'>+						q6routing: routing {</div><div class='add'>+							compatible = "qcom,q6adm-routing";</div><div class='add'>+							#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		apps_smmu: iommu@c600000 {</div><div class='add'>+			compatible = "qcom,qcm2290-smmu-500", "qcom,smmu-500", "arm,mmu-500";</div><div class='add'>+			reg = &lt;0x0 0x0c600000 0x0 0x80000&gt;;</div><div class='add'>+			#iommu-cells = &lt;2&gt;;</div><div class='add'>+			#global-interrupts = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		venus: video-codec@5a00000 {</div><div class='add'>+			compatible = "qcom,qcm2290-venus";</div><div class='add'>+			reg = &lt;0 0x5a00000 0 0xf0000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;gcc GCC_VENUS_GDSC&gt;,</div><div class='add'>+					&lt;&amp;gcc GCC_VCODEC0_GDSC&gt;,</div><div class='add'>+					&lt;&amp;rpmpd QCM2290_VDDCX&gt;;</div><div class='add'>+			power-domain-names = "venus",</div><div class='add'>+					     "vcodec0",</div><div class='add'>+					     "cx";</div><div class='add'>+			operating-points-v2 = &lt;&amp;venus_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_VIDEO_VENUS_CTL_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_VIDEO_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_VENUS_CTL_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_VIDEO_THROTTLE_CORE_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_VIDEO_VCODEC0_SYS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_VCODEC0_AXI_CLK&gt;;</div><div class='add'>+			clock-names = "core",</div><div class='add'>+				      "iface",</div><div class='add'>+				      "bus",</div><div class='add'>+				      "throttle",</div><div class='add'>+				      "vcodec0_core",</div><div class='add'>+				      "vcodec0_bus";</div><div class='add'>+</div><div class='add'>+			memory-region = &lt;&amp;pil_video_mem&gt;;</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x860 0x0&gt;,</div><div class='add'>+				 &lt;&amp;apps_smmu 0x880 0x0&gt;,</div><div class='add'>+				 &lt;&amp;apps_smmu 0x861 0x04&gt;,</div><div class='add'>+				 &lt;&amp;apps_smmu 0x863 0x0&gt;,</div><div class='add'>+				 &lt;&amp;apps_smmu 0x804 0xe0&gt;;</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;mmnrt_virt MASTER_VIDEO_P0 RPM_ALWAYS_TAG</div><div class='add'>+					 &amp;bimc SLAVE_EBI1 RPM_ALWAYS_TAG&gt;,</div><div class='add'>+					&lt;&amp;bimc MASTER_APPSS_PROC RPM_ACTIVE_TAG</div><div class='add'>+					 &amp;config_noc SLAVE_VENUS_CFG RPM_ACTIVE_TAG&gt;;</div><div class='add'>+			interconnect-names = "video-mem",</div><div class='add'>+					     "cpu-cfg";</div><div class='add'>+</div><div class='add'>+			venus_opp_table: opp-table {</div><div class='add'>+				compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+				opp-133333333 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;133333333&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmpd_opp_low_svs&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-240000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;240000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmpd_opp_svs&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wifi: wifi@c800000 {</div><div class='add'>+			compatible = "qcom,wcn3990-wifi";</div><div class='add'>+			reg = &lt;0x0 0x0c800000 0x0 0x800000&gt;;</div><div class='add'>+			reg-names = "membase";</div><div class='add'>+			memory-region = &lt;&amp;wlan_msa_mem&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x1a0 0x1&gt;;</div><div class='add'>+			qcom,msa-fixed-perm;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		watchdog@f017000 {</div><div class='add'>+			compatible = "qcom,apss-wdt-qcm2290", "qcom,kpss-wdt";</div><div class='add'>+			reg = &lt;0x0 0x0f017000 0x0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 3 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;sleep_clk&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		apcs_glb: mailbox@f111000 {</div><div class='add'>+			compatible = "qcom,qcm2290-apcs-hmss-global";</div><div class='add'>+			reg = &lt;0x0 0x0f111000 0x0 0x1000&gt;;</div><div class='add'>+			#mbox-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		timer@f120000 {</div><div class='add'>+			compatible = "arm,armv7-timer-mem";</div><div class='add'>+			reg = &lt;0x0 0x0f120000 0x0 0x1000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges = &lt;0 0x0 0x0f121000 0x8000&gt;;</div><div class='add'>+</div><div class='add'>+			frame@0 {</div><div class='add'>+				reg = &lt;0x0 0x1000&gt;,</div><div class='add'>+				      &lt;0x1000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				frame-number = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@2000 {</div><div class='add'>+				reg = &lt;0x2000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				frame-number = &lt;1&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@3000 {</div><div class='add'>+				reg = &lt;0x3000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				frame-number = &lt;2&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@4000 {</div><div class='add'>+				reg = &lt;0x4000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				frame-number = &lt;3&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@5000 {</div><div class='add'>+				reg = &lt;0x5000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				frame-number = &lt;4&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@6000 {</div><div class='add'>+				reg = &lt;0x6000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				frame-number = &lt;5&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@7000 {</div><div class='add'>+				reg = &lt;0x7000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				frame-number = &lt;6&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		intc: interrupt-controller@f200000 {</div><div class='add'>+			compatible = "arm,gic-v3";</div><div class='add'>+			reg = &lt;0x0 0x0f200000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0x0f300000 0x0 0x100000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			interrupt-parent = &lt;&amp;intc&gt;;</div><div class='add'>+			#redistributor-regions = &lt;1&gt;;</div><div class='add'>+			redistributor-stride = &lt;0x0 0x20000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpufreq_hw: cpufreq@f521000 {</div><div class='add'>+			compatible = "qcom,qcm2290-cpufreq-hw", "qcom,cpufreq-hw";</div><div class='add'>+			reg = &lt;0x0 0x0f521000 0x0 0x1000&gt;;</div><div class='add'>+			reg-names = "freq-domain0";</div><div class='add'>+			interrupts-extended = &lt;&amp;lmh_cluster 0&gt;;</div><div class='add'>+			interrupt-names = "dcvsh-irq-0";</div><div class='add'>+			clocks = &lt;&amp;rpmcc RPM_SMD_XO_CLK_SRC&gt;, &lt;&amp;gcc GPLL0&gt;;</div><div class='add'>+			clock-names = "xo", "alternate";</div><div class='add'>+</div><div class='add'>+			#freq-domain-cells = &lt;1&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		lmh_cluster: lmh@f550800 {</div><div class='add'>+			compatible = "qcom,qcm2290-lmh", "qcom,sm8150-lmh";</div><div class='add'>+			reg = &lt;0x0 0x0f550800 0x0 0x400&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			cpus = &lt;&amp;cpu0&gt;;</div><div class='add'>+			qcom,lmh-temp-arm-millicelsius = &lt;65000&gt;;</div><div class='add'>+			qcom,lmh-temp-low-millicelsius = &lt;94500&gt;;</div><div class='add'>+			qcom,lmh-temp-high-millicelsius = &lt;95000&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	thermal-zones {</div><div class='add'>+		mapss-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 0&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				mapss_alert0: trip-point0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				mapss_alert1: trip-point1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				mapss_crit: mapss-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		video-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 1&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				video_alert0: trip-point0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				video_alert1: trip-point1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				video_crit: video-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wlan-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 2&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				wlan_alert0: trip-point0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				wlan_alert1: trip-point1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				wlan_crit: wlan-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpuss0-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 3&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpuss0_alert0: trip-point0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpuss0_alert1: trip-point1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpuss0_crit: cpuss0-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpuss1-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 4&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpuss1_alert0: trip-point0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpuss1_alert1: trip-point1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpuss1_crit: cpuss1-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdm0-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 5&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				mdm0_alert0: trip-point0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				mdm0_alert1: trip-point1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				mdm0_crit: mdm0-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdm1-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 6&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				mdm1_alert0: trip-point0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				mdm1_alert1: trip-point1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				mdm1_crit: mdm1-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 7&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				gpu_alert0: trip-point0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpu_alert1: trip-point1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpu_crit: gpu-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		hm-center-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 8&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				hm_center_alert0: trip-point0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				hm_center_alert1: trip-point1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				hm_center_crit: hm-center-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		camera-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 9&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				camera_alert0: trip-point0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				camera_alert1: trip-point1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				camera_crit: camera-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc-d3-camera-mezzanine.dtso b/arch/arm64/boot/dts/qcom/apq8016-sbc-d3-camera-mezzanine.dtso<br/>new file mode 100644<br/>index 000000000000..d739ece6b44f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/apq8016-sbc-d3-camera-mezzanine.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/apq8016-sbc-d3-camera-mezzanine.dtso</a></div><div class='hunk'>@@ -0,0 +1,89 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2023, Linaro Ltd.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,gcc-msm8916.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+</div><div class='add'>+&amp;{/} {</div><div class='add'>+	camera_vdddo_1v8: regulator-camera-vdddo {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "camera_vdddo";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	camera_vdda_2v8: regulator-camera-vdda {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "camera_vdda";</div><div class='add'>+		regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	camera_vddd_1v5: regulator-camera-vddd {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "camera_vddd";</div><div class='add'>+		regulator-min-microvolt = &lt;1500000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1500000&gt;;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;camss {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		port@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			csiphy0_ep: endpoint {</div><div class='add'>+				data-lanes = &lt;0 2&gt;;</div><div class='add'>+				remote-endpoint = &lt;&amp;ov5640_ep&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cci {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cci_i2c0 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	camera@3b {</div><div class='add'>+		compatible = "ovti,ov5640";</div><div class='add'>+		reg = &lt;0x3b&gt;;</div><div class='add'>+</div><div class='add'>+		powerdown-gpios = &lt;&amp;tlmm 34 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;tlmm 35 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;camera_rear_default&gt;;</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;gcc GCC_CAMSS_MCLK0_CLK&gt;;</div><div class='add'>+		clock-names = "xclk";</div><div class='add'>+		assigned-clocks = &lt;&amp;gcc GCC_CAMSS_MCLK0_CLK&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;23880000&gt;;</div><div class='add'>+</div><div class='add'>+		DOVDD-supply = &lt;&amp;camera_vdddo_1v8&gt;;</div><div class='add'>+		AVDD-supply = &lt;&amp;camera_vdda_2v8&gt;;</div><div class='add'>+		DVDD-supply = &lt;&amp;camera_vddd_1v5&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			ov5640_ep: endpoint {</div><div class='add'>+				data-lanes = &lt;1 2&gt;;</div><div class='add'>+				remote-endpoint = &lt;&amp;csiphy0_ep&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi<br/>deleted file mode 100644<br/>index aff218c1b7b6..000000000000<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi</a><br/>+++ /dev/null</div><div class='hunk'>@@ -1,74 +0,0 @@</div><div class='del'>-// SPDX-License-Identifier: GPL-2.0</div><div class='del'>-#include &lt;dt-bindings/pinctrl/qcom,pmic-gpio.h&gt;</div><div class='del'>-#include &lt;dt-bindings/pinctrl/qcom,pmic-mpp.h&gt;</div><div class='del'>-</div><div class='del'>-&amp;pm8916_gpios {</div><div class='del'>-</div><div class='del'>-	usb_hub_reset_pm: usb_hub_reset_pm {</div><div class='del'>-		pinconf {</div><div class='del'>-			pins = "gpio3";</div><div class='del'>-			function = PMIC_GPIO_FUNC_NORMAL;</div><div class='del'>-			input-disable;</div><div class='del'>-			output-high;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	usb_hub_reset_pm_device: usb_hub_reset_pm_device {</div><div class='del'>-		pinconf {</div><div class='del'>-			pins = "gpio3";</div><div class='del'>-			function = PMIC_GPIO_FUNC_NORMAL;</div><div class='del'>-			output-low;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	usb_sw_sel_pm: usb_sw_sel_pm {</div><div class='del'>-		pinconf {</div><div class='del'>-			pins = "gpio4";</div><div class='del'>-			function = PMIC_GPIO_FUNC_NORMAL;</div><div class='del'>-			power-source = &lt;PM8916_GPIO_VPH&gt;;</div><div class='del'>-			input-disable;</div><div class='del'>-			output-high;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	usb_sw_sel_pm_device: usb_sw_sel_pm_device {</div><div class='del'>-		pinconf {</div><div class='del'>-			pins = "gpio4";</div><div class='del'>-			function = PMIC_GPIO_FUNC_NORMAL;</div><div class='del'>-			power-source = &lt;PM8916_GPIO_VPH&gt;;</div><div class='del'>-			input-disable;</div><div class='del'>-			output-low;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	pm8916_gpios_leds: pm8916_gpios_leds {</div><div class='del'>-		pinconf {</div><div class='del'>-			pins = "gpio1", "gpio2";</div><div class='del'>-			function = PMIC_GPIO_FUNC_NORMAL;</div><div class='del'>-			output-low;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;pm8916_mpps {</div><div class='del'>-</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-	pinctrl-0 = &lt;&amp;ls_exp_gpio_f&gt;;</div><div class='del'>-</div><div class='del'>-	ls_exp_gpio_f: pm8916_mpp4 {</div><div class='del'>-		pinconf {</div><div class='del'>-			pins = "mpp4";</div><div class='del'>-			function = "digital";</div><div class='del'>-			output-low;</div><div class='del'>-			power-source = &lt;PM8916_MPP_L5&gt;;	// 1.8V</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	pm8916_mpps_leds: pm8916_mpps_leds {</div><div class='del'>-		pinconf {</div><div class='del'>-			pins = "mpp2", "mpp3";</div><div class='del'>-			function = "digital";</div><div class='del'>-			output-low;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi<br/>deleted file mode 100644<br/>index 21d0822f1ca6..000000000000<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi</a><br/>+++ /dev/null</div><div class='hunk'>@@ -1,89 +0,0 @@</div><div class='del'>-// SPDX-License-Identifier: GPL-2.0</div><div class='del'>-</div><div class='del'>-#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='del'>-</div><div class='del'>-&amp;msmgpio {</div><div class='del'>-</div><div class='del'>-	msmgpio_leds: msmgpio_leds {</div><div class='del'>-		pinconf {</div><div class='del'>-			pins = "gpio21", "gpio120";</div><div class='del'>-			function = "gpio";</div><div class='del'>-			output-low;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	usb_id_default: usb-id-default {</div><div class='del'>-		pinmux {</div><div class='del'>-			function = "gpio";</div><div class='del'>-			pins = "gpio121";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		pinconf {</div><div class='del'>-			pins = "gpio121";</div><div class='del'>-			drive-strength = &lt;8&gt;;</div><div class='del'>-			input-enable;</div><div class='del'>-			bias-pull-up;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	adv7533_int_active: adv533_int_active {</div><div class='del'>-		pinmux {</div><div class='del'>-			function = "gpio";</div><div class='del'>-			pins = "gpio31";</div><div class='del'>-		};</div><div class='del'>-		pinconf {</div><div class='del'>-			pins = "gpio31";</div><div class='del'>-			drive-strength = &lt;16&gt;;</div><div class='del'>-			bias-disable;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	adv7533_int_suspend: adv7533_int_suspend {</div><div class='del'>-		pinmux {</div><div class='del'>-			function = "gpio";</div><div class='del'>-			pins = "gpio31";</div><div class='del'>-		};</div><div class='del'>-		pinconf {</div><div class='del'>-			pins = "gpio31";</div><div class='del'>-			drive-strength = &lt;2&gt;;</div><div class='del'>-			bias-disable;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	adv7533_switch_active: adv7533_switch_active {</div><div class='del'>-		pinmux {</div><div class='del'>-			function = "gpio";</div><div class='del'>-			pins = "gpio32";</div><div class='del'>-		};</div><div class='del'>-		pinconf {</div><div class='del'>-			pins = "gpio32";</div><div class='del'>-			drive-strength = &lt;16&gt;;</div><div class='del'>-			bias-disable;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	adv7533_switch_suspend: adv7533_switch_suspend {</div><div class='del'>-		pinmux {</div><div class='del'>-			function = "gpio";</div><div class='del'>-			pins = "gpio32";</div><div class='del'>-		};</div><div class='del'>-		pinconf {</div><div class='del'>-			pins = "gpio32";</div><div class='del'>-			drive-strength = &lt;2&gt;;</div><div class='del'>-			bias-disable;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	msm_key_volp_n_default: msm_key_volp_n_default {</div><div class='del'>-		pinmux {</div><div class='del'>-			function = "gpio";</div><div class='del'>-			pins = "gpio107";</div><div class='del'>-		};</div><div class='del'>-		pinconf {</div><div class='del'>-			pins = "gpio107";</div><div class='del'>-			drive-strength = &lt;8&gt;;</div><div class='del'>-			input-enable;</div><div class='del'>-			bias-pull-up;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc-usb-host.dtso b/arch/arm64/boot/dts/qcom/apq8016-sbc-usb-host.dtso<br/>new file mode 100644<br/>index 000000000000..a82c26b7eae8<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/apq8016-sbc-usb-host.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/apq8016-sbc-usb-host.dtso</a></div><div class='hunk'>@@ -0,0 +1,8 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+&amp;usb {</div><div class='add'>+         dr_mode = "host";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts<br/>index 48bd1c2874de..ba6ccf0db16a 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/apq8016-sbc.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/apq8016-sbc.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/apq8016-sbc.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/apq8016-sbc.dts</a></div><div class='hunk'>@@ -5,9 +5,744 @@</div><div class='ctx'> </div><div class='ctx'> /dts-v1/;</div><div class='ctx'> </div><div class='del'>-#include "apq8016-sbc.dtsi"</div><div class='add'>+#include "msm8916-pm8916.dtsi"</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/qcom,pmic-gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/qcom,pmic-mpp.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/apq8016-lpass.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	model = "Qualcomm Technologies, Inc. APQ 8016 SBC";</div><div class='del'>-	compatible = "qcom,apq8016-sbc", "qcom,apq8016", "qcom,sbc";</div><div class='add'>+	compatible = "qcom,apq8016-sbc", "qcom,apq8016";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		mmc0 = &amp;sdhc_1; /* eMMC */</div><div class='add'>+		mmc1 = &amp;sdhc_2; /* SD card */</div><div class='add'>+		serial0 = &amp;blsp_uart2;</div><div class='add'>+		serial1 = &amp;blsp_uart1;</div><div class='add'>+		usid0 = &amp;pm8916_0;</div><div class='add'>+		i2c0 = &amp;blsp_i2c2;</div><div class='add'>+		i2c1 = &amp;blsp_i2c6;</div><div class='add'>+		i2c3 = &amp;blsp_i2c4;</div><div class='add'>+		spi0 = &amp;blsp_spi5;</div><div class='add'>+		spi1 = &amp;blsp_spi3;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		ramoops@bff00000 {</div><div class='add'>+			compatible = "ramoops";</div><div class='add'>+			reg = &lt;0x0 0xbff00000 0x0 0x100000&gt;;</div><div class='add'>+</div><div class='add'>+			record-size = &lt;0x20000&gt;;</div><div class='add'>+			console-size = &lt;0x20000&gt;;</div><div class='add'>+			ftrace-size = &lt;0x20000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb2513 {</div><div class='add'>+		compatible = "smsc,usb3503";</div><div class='add'>+		reset-gpios = &lt;&amp;pm8916_gpios 3 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		initial-mode = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb_id: usb-id {</div><div class='add'>+		compatible = "linux,extcon-usb-gpio";</div><div class='add'>+		id-gpios = &lt;&amp;tlmm 121 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;usb_id_default&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdmi-out {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		type = "a";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			hdmi_con: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;adv7533_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		autorepeat;</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;msm_key_volp_n_default&gt;;</div><div class='add'>+</div><div class='add'>+		button {</div><div class='add'>+			label = "Volume Up";</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+			gpios = &lt;&amp;tlmm 107 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;tlmm_leds&gt;,</div><div class='add'>+			    &lt;&amp;pm8916_gpios_leds&gt;,</div><div class='add'>+			    &lt;&amp;pm8916_mpps_leds&gt;;</div><div class='add'>+</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			label = "apq8016-sbc:green:user1";</div><div class='add'>+			function = LED_FUNCTION_HEARTBEAT;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			gpios = &lt;&amp;tlmm 21 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "heartbeat";</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-2 {</div><div class='add'>+			label = "apq8016-sbc:green:user2";</div><div class='add'>+			function = LED_FUNCTION_DISK_ACTIVITY;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			gpios = &lt;&amp;tlmm 120 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "mmc0";</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-3 {</div><div class='add'>+			label = "apq8016-sbc:green:user3";</div><div class='add'>+			function = LED_FUNCTION_DISK_ACTIVITY;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			gpios = &lt;&amp;pm8916_gpios 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "mmc1";</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-4 {</div><div class='add'>+			label = "apq8016-sbc:green:user4";</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			gpios = &lt;&amp;pm8916_gpios 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "none";</div><div class='add'>+			panic-indicator;</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-5 {</div><div class='add'>+			label = "apq8016-sbc:yellow:wlan";</div><div class='add'>+			function = LED_FUNCTION_WLAN;</div><div class='add'>+			color = &lt;LED_COLOR_ID_YELLOW&gt;;</div><div class='add'>+			gpios = &lt;&amp;pm8916_mpps 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "phy0tx";</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-6 {</div><div class='add'>+			label = "apq8016-sbc:blue:bt";</div><div class='add'>+			function = LED_FUNCTION_BLUETOOTH;</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			gpios = &lt;&amp;pm8916_mpps 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "bluetooth-power";</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_i2c2 {</div><div class='add'>+	/* On Low speed expansion: LS-I2C0 */</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_i2c4 {</div><div class='add'>+	/* On High speed expansion: HS-I2C2 */</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	adv_bridge: bridge@39 {</div><div class='add'>+		compatible = "adi,adv7533";</div><div class='add'>+		reg = &lt;0x39&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-parent = &lt;&amp;tlmm&gt;;</div><div class='add'>+		interrupts = &lt;31 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+</div><div class='add'>+		adi,dsi-lanes = &lt;4&gt;;</div><div class='add'>+		clocks = &lt;&amp;rpmcc RPM_SMD_BB_CLK2&gt;;</div><div class='add'>+		clock-names = "cec";</div><div class='add'>+</div><div class='add'>+		pd-gpios = &lt;&amp;tlmm 32 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+		avdd-supply = &lt;&amp;pm8916_l6&gt;;</div><div class='add'>+		a2vdd-supply = &lt;&amp;pm8916_l6&gt;;</div><div class='add'>+		dvdd-supply = &lt;&amp;pm8916_l6&gt;;</div><div class='add'>+		pvdd-supply = &lt;&amp;pm8916_l6&gt;;</div><div class='add'>+		v1p2-supply = &lt;&amp;pm8916_l6&gt;;</div><div class='add'>+		v3p3-supply = &lt;&amp;pm8916_l17&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default","sleep";</div><div class='add'>+		pinctrl-0 = &lt;&amp;adv7533_int_active &amp;adv7533_switch_active&gt;;</div><div class='add'>+		pinctrl-1 = &lt;&amp;adv7533_int_suspend &amp;adv7533_switch_suspend&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				adv7533_in: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;mdss_dsi0_out&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				adv7533_out: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;hdmi_con&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_i2c6 {</div><div class='add'>+	/* On Low speed expansion: LS-I2C1 */</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_spi3 {</div><div class='add'>+	/* On High speed expansion: HS-SPI1 */</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_spi5 {</div><div class='add'>+	/* On Low speed expansion: LS-SPI0 */</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_uart1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	label = "LS-UART0";</div><div class='add'>+	pinctrl-0 = &lt;&amp;blsp_uart1_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;blsp_uart1_sleep&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_uart2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	label = "LS-UART1";</div><div class='add'>+	pinctrl-0 = &lt;&amp;blsp_uart2_console_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;blsp_uart2_console_sleep&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;camss {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpass {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpass_codec {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mba_mem {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdss {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdss_dsi0_out {</div><div class='add'>+	data-lanes = &lt;0 1 2 3&gt;;</div><div class='add'>+	remote-endpoint = &lt;&amp;adv7533_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mpss {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	firmware-name = "qcom/apq8016/mba.mbn", "qcom/apq8016/modem.mbn";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mpss_mem {</div><div class='add'>+	status = "okay";</div><div class='add'>+	reg = &lt;0x0 0x86800000 0x0 0x2b00000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8916_codec {</div><div class='add'>+	status = "okay";</div><div class='add'>+	qcom,mbhc-vthreshold-low = &lt;75 150 237 450 500&gt;;</div><div class='add'>+	qcom,mbhc-vthreshold-high = &lt;75 150 237 450 500&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8916_resin {</div><div class='add'>+	status = "okay";</div><div class='add'>+	linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8916_rpm_regulators {</div><div class='add'>+	/*</div><div class='add'>+	 * The 96Boards specification expects a 1.8V power rail on the low-speed</div><div class='add'>+	 * expansion connector that is able to provide at least 0.18W / 100 mA.</div><div class='add'>+	 * L15/L16 are connected in parallel to provide 55 mA each. A minimum load</div><div class='add'>+	 * must be specified to ensure the regulators are not put in LPM where they</div><div class='add'>+	 * would only provide 5 mA.</div><div class='add'>+	 */</div><div class='add'>+	pm8916_l15: l15 {</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-system-load = &lt;50000&gt;;</div><div class='add'>+		regulator-allow-set-load;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+	pm8916_l16: l16 {</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-system-load = &lt;50000&gt;;</div><div class='add'>+		regulator-allow-set-load;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pm8916_l17: l17 {</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sdhc_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sdhc_2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdc2_default &amp;sdc2_cd_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;sdc2_sleep &amp;sdc2_cd_default&gt;;</div><div class='add'>+</div><div class='add'>+	cd-gpios = &lt;&amp;tlmm 38 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sound {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pinctrl-0 = &lt;&amp;cdc_pdm_default &amp;sec_mi2s_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;cdc_pdm_sleep &amp;sec_mi2s_sleep&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	model = "DB410c";</div><div class='add'>+	audio-routing =</div><div class='add'>+		"AMIC2", "MIC BIAS Internal2",</div><div class='add'>+		"AMIC3", "MIC BIAS External1";</div><div class='add'>+</div><div class='add'>+	quaternary-dai-link {</div><div class='add'>+		link-name = "ADV7533";</div><div class='add'>+		cpu {</div><div class='add'>+			sound-dai = &lt;&amp;lpass MI2S_QUATERNARY&gt;;</div><div class='add'>+		};</div><div class='add'>+		codec {</div><div class='add'>+			sound-dai = &lt;&amp;adv_bridge&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	primary-dai-link {</div><div class='add'>+		link-name = "WCD";</div><div class='add'>+		cpu {</div><div class='add'>+			sound-dai = &lt;&amp;lpass MI2S_PRIMARY&gt;;</div><div class='add'>+		};</div><div class='add'>+		codec {</div><div class='add'>+			sound-dai = &lt;&amp;lpass_codec 0&gt;, &lt;&amp;pm8916_codec 0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	tertiary-dai-link {</div><div class='add'>+		link-name = "WCD-Capture";</div><div class='add'>+		cpu {</div><div class='add'>+			sound-dai = &lt;&amp;lpass MI2S_TERTIARY&gt;;</div><div class='add'>+		};</div><div class='add'>+		codec {</div><div class='add'>+			sound-dai = &lt;&amp;lpass_codec 1&gt;, &lt;&amp;pm8916_codec 1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb {</div><div class='add'>+	status = "okay";</div><div class='add'>+	extcon = &lt;&amp;usb_id&gt;, &lt;&amp;usb_id&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl-names = "default", "device";</div><div class='add'>+	pinctrl-0 = &lt;&amp;usb_sw_sel_pm &amp;usb_hub_reset_pm&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;usb_sw_sel_pm_device &amp;usb_hub_reset_pm_device&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_hs_phy {</div><div class='add'>+	extcon = &lt;&amp;usb_id&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;venus {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;venus_mem {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wcnss {</div><div class='add'>+	status = "okay";</div><div class='add'>+	firmware-name = "qcom/apq8016/wcnss.mbn";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wcnss_ctrl {</div><div class='add'>+	firmware-name = "qcom/apq8016/WCNSS_qcom_wlan_nv_sbc.bin";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wcnss_iris {</div><div class='add'>+	compatible = "qcom,wcn3620";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wcnss_mem {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Enable CoreSight */</div><div class='add'>+&amp;cti0 { status = "okay"; };</div><div class='add'>+&amp;cti1 { status = "okay"; };</div><div class='add'>+&amp;cti12 { status = "okay"; };</div><div class='add'>+&amp;cti13 { status = "okay"; };</div><div class='add'>+&amp;cti14 { status = "okay"; };</div><div class='add'>+&amp;cti15 { status = "okay"; };</div><div class='add'>+&amp;debug0 { status = "okay"; };</div><div class='add'>+&amp;debug1 { status = "okay"; };</div><div class='add'>+&amp;debug2 { status = "okay"; };</div><div class='add'>+&amp;debug3 { status = "okay"; };</div><div class='add'>+&amp;etf { status = "okay"; };</div><div class='add'>+&amp;etm0 { status = "okay"; };</div><div class='add'>+&amp;etm1 { status = "okay"; };</div><div class='add'>+&amp;etm2 { status = "okay"; };</div><div class='add'>+&amp;etm3 { status = "okay"; };</div><div class='add'>+&amp;etr { status = "okay"; };</div><div class='add'>+&amp;funnel0 { status = "okay"; };</div><div class='add'>+&amp;funnel1 { status = "okay"; };</div><div class='add'>+&amp;replicator { status = "okay"; };</div><div class='add'>+&amp;stm { status = "okay"; };</div><div class='add'>+&amp;tpiu { status = "okay"; };</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * 2mA drive strength is not enough when connecting multiple</div><div class='add'>+ * I2C devices with different pull up resistors.</div><div class='add'>+ */</div><div class='add'>+&amp;blsp_i2c2_default {</div><div class='add'>+	drive-strength = &lt;16&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_i2c4_default {</div><div class='add'>+	drive-strength = &lt;16&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_i2c6_default {</div><div class='add'>+	drive-strength = &lt;16&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * GPIO name legend: proper name = the GPIO line is used as GPIO</div><div class='add'>+ *         NC = not connected (pin out but not routed from the chip to</div><div class='add'>+ *              anything the board)</div><div class='add'>+ *         "[PER]" = pin is muxed for [peripheral] (not GPIO)</div><div class='add'>+ *         LSEC = Low Speed External Connector</div><div class='add'>+ *         HSEC = High Speed External Connector</div><div class='add'>+ *</div><div class='add'>+ * Line names are taken from the schematic "DragonBoard410c"</div><div class='add'>+ * dated monday, august 31, 2015. Page 5 in particular.</div><div class='add'>+ *</div><div class='add'>+ * For the lines routed to the external connectors the</div><div class='add'>+ * lines are named after the 96Boards CE Specification 1.0,</div><div class='add'>+ * Appendix "Expansion Connector Signal Description".</div><div class='add'>+ *</div><div class='add'>+ * When the 96Board naming of a line and the schematic name of</div><div class='add'>+ * the same line are in conflict, the 96Board specification</div><div class='add'>+ * takes precedence, which means that the external UART on the</div><div class='add'>+ * LSEC is named UART0 while the schematic and SoC names this</div><div class='add'>+ * UART3. This is only for the informational lines i.e. "[FOO]",</div><div class='add'>+ * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only</div><div class='add'>+ * ones actually used for GPIO.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+&amp;tlmm {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"[UART0_TX]", /* GPIO_0, LSEC pin 5 */</div><div class='add'>+		"[UART0_RX]", /* GPIO_1, LSEC pin 7 */</div><div class='add'>+		"[UART0_CTS_N]", /* GPIO_2, LSEC pin 3 */</div><div class='add'>+		"[UART0_RTS_N]", /* GPIO_3, LSEC pin 9 */</div><div class='add'>+		"[UART1_TX]", /* GPIO_4, LSEC pin 11 */</div><div class='add'>+		"[UART1_RX]", /* GPIO_5, LSEC pin 13 */</div><div class='add'>+		"[I2C0_SDA]", /* GPIO_8, LSEC pin 17 */</div><div class='add'>+		"[I2C0_SCL]", /* GPIO_7, LSEC pin 15 */</div><div class='add'>+		"[SPI1_DOUT]", /* SPI1_MOSI, HSEC pin 1 */</div><div class='add'>+		"[SPI1_DIN]", /* SPI1_MISO, HSEC pin 11 */</div><div class='add'>+		"[SPI1_CS]", /* SPI1_CS_N, HSEC pin 7 */</div><div class='add'>+		"[SPI1_SCLK]", /* SPI1_CLK, HSEC pin 9 */</div><div class='add'>+		"GPIO-B", /* LS_EXP_GPIO_B, LSEC pin 24 */</div><div class='add'>+		"GPIO-C", /* LS_EXP_GPIO_C, LSEC pin 25 */</div><div class='add'>+		"[I2C3_SDA]", /* HSEC pin 38 */</div><div class='add'>+		"[I2C3_SCL]", /* HSEC pin 36 */</div><div class='add'>+		"[SPI0_MOSI]", /* LSEC pin 14 */</div><div class='add'>+		"[SPI0_MISO]", /* LSEC pin 10 */</div><div class='add'>+		"[SPI0_CS_N]", /* LSEC pin 12 */</div><div class='add'>+		"[SPI0_CLK]", /* LSEC pin 8 */</div><div class='add'>+		"HDMI_HPD_N", /* GPIO 20 */</div><div class='add'>+		"USR_LED_1_CTRL",</div><div class='add'>+		"[I2C1_SDA]", /* GPIO_22, LSEC pin 21 */</div><div class='add'>+		"[I2C1_SCL]", /* GPIO_23, LSEC pin 19 */</div><div class='add'>+		"GPIO-G", /* LS_EXP_GPIO_G, LSEC pin 29 */</div><div class='add'>+		"GPIO-H", /* LS_EXP_GPIO_H, LSEC pin 30 */</div><div class='add'>+		"[CSI0_MCLK]", /* HSEC pin 15 */</div><div class='add'>+		"[CSI1_MCLK]", /* HSEC pin 17 */</div><div class='add'>+		"GPIO-K", /* LS_EXP_GPIO_K, LSEC pin 33 */</div><div class='add'>+		"[I2C2_SDA]", /* HSEC pin 34 */</div><div class='add'>+		"[I2C2_SCL]", /* HSEC pin 32 */</div><div class='add'>+		"DSI2HDMI_INT_N",</div><div class='add'>+		"DSI_SW_SEL_APQ",</div><div class='add'>+		"GPIO-L", /* LS_EXP_GPIO_L, LSEC pin 34 */</div><div class='add'>+		"GPIO-J", /* LS_EXP_GPIO_J, LSEC pin 32 */</div><div class='add'>+		"GPIO-I", /* LS_EXP_GPIO_I, LSEC pin 31 */</div><div class='add'>+		"GPIO-A", /* LS_EXP_GPIO_A, LSEC pin 23 */</div><div class='add'>+		"FORCED_USB_BOOT",</div><div class='add'>+		"SD_CARD_DET_N",</div><div class='add'>+		"[WCSS_BT_SSBI]",</div><div class='add'>+		"[WCSS_WLAN_DATA_2]", /* GPIO 40 */</div><div class='add'>+		"[WCSS_WLAN_DATA_1]",</div><div class='add'>+		"[WCSS_WLAN_DATA_0]",</div><div class='add'>+		"[WCSS_WLAN_SET]",</div><div class='add'>+		"[WCSS_WLAN_CLK]",</div><div class='add'>+		"[WCSS_FM_SSBI]",</div><div class='add'>+		"[WCSS_FM_SDI]",</div><div class='add'>+		"[WCSS_BT_DAT_CTL]",</div><div class='add'>+		"[WCSS_BT_DAT_STB]",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC", /* GPIO 50 */</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC", /* GPIO 60 */</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"[CDC_PDM0_CLK]",</div><div class='add'>+		"[CDC_PDM0_SYNC]",</div><div class='add'>+		"[CDC_PDM0_TX0]",</div><div class='add'>+		"[CDC_PDM0_RX0]",</div><div class='add'>+		"[CDC_PDM0_RX1]",</div><div class='add'>+		"[CDC_PDM0_RX2]",</div><div class='add'>+		"GPIO-D", /* LS_EXP_GPIO_D, LSEC pin 26 */</div><div class='add'>+		"NC", /* GPIO 70 */</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC", /* GPIO 74 */</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"BOOT_CONFIG_0", /* GPIO 80 */</div><div class='add'>+		"BOOT_CONFIG_1",</div><div class='add'>+		"BOOT_CONFIG_2",</div><div class='add'>+		"BOOT_CONFIG_3",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"BOOT_CONFIG_5",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC", /* GPIO 90 */</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC", /* GPIO 100 */</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"SSBI_GPS",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"KEY_VOLP_N",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"[LS_EXP_MI2S_WS]", /* GPIO 110 */</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"[LS_EXP_MI2S_SCK]",</div><div class='add'>+		"[LS_EXP_MI2S_DATA0]",</div><div class='add'>+		"GPIO-E", /* LS_EXP_GPIO_E, LSEC pin 27 */</div><div class='add'>+		"NC",</div><div class='add'>+		"[DSI2HDMI_MI2S_WS]",</div><div class='add'>+		"[DSI2HDMI_MI2S_SCK]",</div><div class='add'>+		"[DSI2HDMI_MI2S_DATA0]",</div><div class='add'>+		"USR_LED_2_CTRL", /* GPIO 120 */</div><div class='add'>+		"SB_HS_ID";</div><div class='add'>+</div><div class='add'>+	blsp_uart1_default: blsp-uart1-default-state {</div><div class='add'>+		/* TX, RX, CTS_N, RTS_N */</div><div class='add'>+		pins = "gpio0", "gpio1", "gpio2", "gpio3";</div><div class='add'>+		function = "blsp_uart1";</div><div class='add'>+		drive-strength = &lt;16&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	blsp_uart1_sleep: blsp-uart1-sleep-state {</div><div class='add'>+		pins = "gpio0", "gpio1", "gpio2", "gpio3";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-pull-down;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdc2_cd_default: sdc2-cd-default-state {</div><div class='add'>+		pins = "gpio38";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	tlmm_leds: tlmm-leds-state {</div><div class='add'>+		pins = "gpio21", "gpio120";</div><div class='add'>+		function = "gpio";</div><div class='add'>+</div><div class='add'>+		output-low;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb_id_default: usb-id-default-state {</div><div class='add'>+		pins = "gpio121";</div><div class='add'>+		function = "gpio";</div><div class='add'>+</div><div class='add'>+		drive-strength = &lt;8&gt;;</div><div class='add'>+		bias-pull-up;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	adv7533_int_active: adv533-int-active-state {</div><div class='add'>+		pins = "gpio31";</div><div class='add'>+		function = "gpio";</div><div class='add'>+</div><div class='add'>+		drive-strength = &lt;16&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	adv7533_int_suspend: adv7533-int-suspend-state {</div><div class='add'>+		pins = "gpio31";</div><div class='add'>+		function = "gpio";</div><div class='add'>+</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	adv7533_switch_active: adv7533-switch-active-state {</div><div class='add'>+		pins = "gpio32";</div><div class='add'>+		function = "gpio";</div><div class='add'>+</div><div class='add'>+		drive-strength = &lt;16&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	adv7533_switch_suspend: adv7533-switch-suspend-state {</div><div class='add'>+		pins = "gpio32";</div><div class='add'>+		function = "gpio";</div><div class='add'>+</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	msm_key_volp_n_default: msm-key-volp-n-default-state {</div><div class='add'>+		pins = "gpio107";</div><div class='add'>+		function = "gpio";</div><div class='add'>+</div><div class='add'>+		drive-strength = &lt;8&gt;;</div><div class='add'>+		bias-pull-up;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8916_gpios {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"USR_LED_3_CTRL",</div><div class='add'>+		"USR_LED_4_CTRL",</div><div class='add'>+		"USB_HUB_RESET_N_PM",</div><div class='add'>+		"USB_SW_SEL_PM";</div><div class='add'>+</div><div class='add'>+	usb_hub_reset_pm: usb-hub-reset-pm-state {</div><div class='add'>+		pins = "gpio3";</div><div class='add'>+		function = PMIC_GPIO_FUNC_NORMAL;</div><div class='add'>+</div><div class='add'>+		input-disable;</div><div class='add'>+		output-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb_hub_reset_pm_device: usb-hub-reset-pm-device-state {</div><div class='add'>+		pins = "gpio3";</div><div class='add'>+		function = PMIC_GPIO_FUNC_NORMAL;</div><div class='add'>+</div><div class='add'>+		output-low;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb_sw_sel_pm: usb-sw-sel-pm-state {</div><div class='add'>+		pins = "gpio4";</div><div class='add'>+		function = PMIC_GPIO_FUNC_NORMAL;</div><div class='add'>+</div><div class='add'>+		power-source = &lt;PM8916_GPIO_VPH&gt;;</div><div class='add'>+		input-disable;</div><div class='add'>+		output-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb_sw_sel_pm_device: usb-sw-sel-pm-device-state {</div><div class='add'>+		pins = "gpio4";</div><div class='add'>+		function = PMIC_GPIO_FUNC_NORMAL;</div><div class='add'>+</div><div class='add'>+		power-source = &lt;PM8916_GPIO_VPH&gt;;</div><div class='add'>+		input-disable;</div><div class='add'>+		output-low;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pm8916_gpios_leds: pm8916-gpios-leds-state {</div><div class='add'>+		pins = "gpio1", "gpio2";</div><div class='add'>+		function = PMIC_GPIO_FUNC_NORMAL;</div><div class='add'>+</div><div class='add'>+		output-low;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8916_mpps {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"VDD_PX_BIAS",</div><div class='add'>+		"WLAN_LED_CTRL",</div><div class='add'>+		"BT_LED_CTRL",</div><div class='add'>+		"GPIO-F"; /* LS_EXP_GPIO_F, LSEC pin 28 */</div><div class='add'>+</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;ls_exp_gpio_f&gt;;</div><div class='add'>+</div><div class='add'>+	ls_exp_gpio_f: pm8916-mpp4-state {</div><div class='add'>+		pins = "mpp4";</div><div class='add'>+		function = "digital";</div><div class='add'>+</div><div class='add'>+		output-low;</div><div class='add'>+		power-source = &lt;PM8916_MPP_L5&gt;;	/* 1.8V */</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pm8916_mpps_leds: pm8916-mpps-state {</div><div class='add'>+		pins = "mpp2", "mpp3";</div><div class='add'>+		function = "digital";</div><div class='add'>+</div><div class='add'>+		output-low;</div><div class='add'>+	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi<br/>deleted file mode 100644<br/>index 06aab44d798c..000000000000<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi</a><br/>+++ /dev/null</div><div class='hunk'>@@ -1,682 +0,0 @@</div><div class='del'>-// SPDX-License-Identifier: GPL-2.0-only</div><div class='del'>-/*</div><div class='del'>- * Copyright (c) 2015, The Linux Foundation. All rights reserved.</div><div class='del'>- */</div><div class='del'>-</div><div class='del'>-#include "msm8916.dtsi"</div><div class='del'>-#include "pm8916.dtsi"</div><div class='del'>-#include "apq8016-sbc-soc-pins.dtsi"</div><div class='del'>-#include "apq8016-sbc-pmic-pins.dtsi"</div><div class='del'>-#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='del'>-#include &lt;dt-bindings/input/input.h&gt;</div><div class='del'>-#include &lt;dt-bindings/sound/apq8016-lpass.h&gt;</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * GPIO name legend: proper name = the GPIO line is used as GPIO</div><div class='del'>- *         NC = not connected (pin out but not routed from the chip to</div><div class='del'>- *              anything the board)</div><div class='del'>- *         "[PER]" = pin is muxed for [peripheral] (not GPIO)</div><div class='del'>- *         LSEC = Low Speed External Connector</div><div class='del'>- *         HSEC = High Speed External Connector</div><div class='del'>- *</div><div class='del'>- * Line names are taken from the schematic "DragonBoard410c"</div><div class='del'>- * dated monday, august 31, 2015. Page 5 in particular.</div><div class='del'>- *</div><div class='del'>- * For the lines routed to the external connectors the</div><div class='del'>- * lines are named after the 96Boards CE Specification 1.0,</div><div class='del'>- * Appendix "Expansion Connector Signal Description".</div><div class='del'>- *</div><div class='del'>- * When the 96Board naming of a line and the schematic name of</div><div class='del'>- * the same line are in conflict, the 96Board specification</div><div class='del'>- * takes precedence, which means that the external UART on the</div><div class='del'>- * LSEC is named UART0 while the schematic and SoC names this</div><div class='del'>- * UART3. This is only for the informational lines i.e. "[FOO]",</div><div class='del'>- * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only</div><div class='del'>- * ones actually used for GPIO.</div><div class='del'>- */</div><div class='del'>-</div><div class='del'>-/ {</div><div class='del'>-	aliases {</div><div class='del'>-		serial0 = &amp;blsp1_uart2;</div><div class='del'>-		serial1 = &amp;blsp1_uart1;</div><div class='del'>-		usid0 = &amp;pm8916_0;</div><div class='del'>-		i2c0	= &amp;blsp_i2c2;</div><div class='del'>-		i2c1	= &amp;blsp_i2c6;</div><div class='del'>-		i2c3	= &amp;blsp_i2c4;</div><div class='del'>-		spi0	= &amp;blsp_spi5;</div><div class='del'>-		spi1	= &amp;blsp_spi3;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	chosen {</div><div class='del'>-		stdout-path = "serial0";</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	reserved-memory {</div><div class='del'>-		ramoops@bff00000{</div><div class='del'>-			compatible = "ramoops";</div><div class='del'>-			reg = &lt;0x0 0xbff00000 0x0 0x100000&gt;;</div><div class='del'>-</div><div class='del'>-			record-size = &lt;0x20000&gt;;</div><div class='del'>-			console-size = &lt;0x20000&gt;;</div><div class='del'>-			ftrace-size = &lt;0x20000&gt;;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	soc {</div><div class='del'>-		pinctrl@1000000 {</div><div class='del'>-			gpio-line-names =</div><div class='del'>-				"[UART0_TX]", /* GPIO_0, LSEC pin 5 */</div><div class='del'>-				"[UART0_RX]", /* GPIO_1, LSEC pin 7 */</div><div class='del'>-				"[UART0_CTS_N]", /* GPIO_2, LSEC pin 3 */</div><div class='del'>-				"[UART0_RTS_N]", /* GPIO_3, LSEC pin 9 */</div><div class='del'>-				"[UART1_TX]", /* GPIO_4, LSEC pin 11 */</div><div class='del'>-				"[UART1_RX]", /* GPIO_5, LSEC pin 13 */</div><div class='del'>-				"[I2C0_SDA]", /* GPIO_8, LSEC pin 17 */</div><div class='del'>-				"[I2C0_SCL]", /* GPIO_7, LSEC pin 15 */</div><div class='del'>-				"[SPI1_DOUT]", /* SPI1_MOSI, HSEC pin 1 */</div><div class='del'>-				"[SPI1_DIN]", /* SPI1_MISO, HSEC pin 11 */</div><div class='del'>-				"[SPI1_CS]", /* SPI1_CS_N, HSEC pin 7 */</div><div class='del'>-				"[SPI1_SCLK]", /* SPI1_CLK, HSEC pin 9 */</div><div class='del'>-				"GPIO-B", /* LS_EXP_GPIO_B, LSEC pin 24 */</div><div class='del'>-				"GPIO-C", /* LS_EXP_GPIO_C, LSEC pin 25 */</div><div class='del'>-				"[I2C3_SDA]", /* HSEC pin 38 */</div><div class='del'>-				"[I2C3_SCL]", /* HSEC pin 36 */</div><div class='del'>-				"[SPI0_MOSI]", /* LSEC pin 14 */</div><div class='del'>-				"[SPI0_MISO]", /* LSEC pin 10 */</div><div class='del'>-				"[SPI0_CS_N]", /* LSEC pin 12 */</div><div class='del'>-				"[SPI0_CLK]", /* LSEC pin 8 */</div><div class='del'>-				"HDMI_HPD_N", /* GPIO 20 */</div><div class='del'>-				"USR_LED_1_CTRL",</div><div class='del'>-				"[I2C1_SDA]", /* GPIO_22, LSEC pin 21 */</div><div class='del'>-				"[I2C1_SCL]", /* GPIO_23, LSEC pin 19 */</div><div class='del'>-				"GPIO-G", /* LS_EXP_GPIO_G, LSEC pin 29 */</div><div class='del'>-				"GPIO-H", /* LS_EXP_GPIO_H, LSEC pin 30 */</div><div class='del'>-				"[CSI0_MCLK]", /* HSEC pin 15 */</div><div class='del'>-				"[CSI1_MCLK]", /* HSEC pin 17 */</div><div class='del'>-				"GPIO-K", /* LS_EXP_GPIO_K, LSEC pin 33 */</div><div class='del'>-				"[I2C2_SDA]", /* HSEC pin 34 */</div><div class='del'>-				"[I2C2_SCL]", /* HSEC pin 32 */</div><div class='del'>-				"DSI2HDMI_INT_N",</div><div class='del'>-				"DSI_SW_SEL_APQ",</div><div class='del'>-				"GPIO-L", /* LS_EXP_GPIO_L, LSEC pin 34 */</div><div class='del'>-				"GPIO-J", /* LS_EXP_GPIO_J, LSEC pin 32 */</div><div class='del'>-				"GPIO-I", /* LS_EXP_GPIO_I, LSEC pin 31 */</div><div class='del'>-				"GPIO-A", /* LS_EXP_GPIO_A, LSEC pin 23 */</div><div class='del'>-				"FORCED_USB_BOOT",</div><div class='del'>-				"SD_CARD_DET_N",</div><div class='del'>-				"[WCSS_BT_SSBI]",</div><div class='del'>-				"[WCSS_WLAN_DATA_2]", /* GPIO 40 */</div><div class='del'>-				"[WCSS_WLAN_DATA_1]",</div><div class='del'>-				"[WCSS_WLAN_DATA_0]",</div><div class='del'>-				"[WCSS_WLAN_SET]",</div><div class='del'>-				"[WCSS_WLAN_CLK]",</div><div class='del'>-				"[WCSS_FM_SSBI]",</div><div class='del'>-				"[WCSS_FM_SDI]",</div><div class='del'>-				"[WCSS_BT_DAT_CTL]",</div><div class='del'>-				"[WCSS_BT_DAT_STB]",</div><div class='del'>-				"NC",</div><div class='del'>-				"NC", /* GPIO 50 */</div><div class='del'>-				"NC",</div><div class='del'>-				"NC",</div><div class='del'>-				"NC",</div><div class='del'>-				"NC",</div><div class='del'>-				"NC",</div><div class='del'>-				"NC",</div><div class='del'>-				"NC",</div><div class='del'>-				"NC",</div><div class='del'>-				"NC",</div><div class='del'>-				"NC", /* GPIO 60 */</div><div class='del'>-				"NC",</div><div class='del'>-				"NC",</div><div class='del'>-				"[CDC_PDM0_CLK]",</div><div class='del'>-				"[CDC_PDM0_SYNC]",</div><div class='del'>-				"[CDC_PDM0_TX0]",</div><div class='del'>-				"[CDC_PDM0_RX0]",</div><div class='del'>-				"[CDC_PDM0_RX1]",</div><div class='del'>-				"[CDC_PDM0_RX2]",</div><div class='del'>-				"GPIO-D", /* LS_EXP_GPIO_D, LSEC pin 26 */</div><div class='del'>-				"NC", /* GPIO 70 */</div><div class='del'>-				"NC",</div><div class='del'>-				"NC",</div><div class='del'>-				"NC",</div><div class='del'>-				"NC", /* GPIO 74 */</div><div class='del'>-				"NC",</div><div class='del'>-				"NC",</div><div class='del'>-				"NC",</div><div class='del'>-				"NC",</div><div class='del'>-				"NC",</div><div class='del'>-				"BOOT_CONFIG_0", /* GPIO 80 */</div><div class='del'>-				"BOOT_CONFIG_1",</div><div class='del'>-				"BOOT_CONFIG_2",</div><div class='del'>-				"BOOT_CONFIG_3",</div><div class='del'>-				"NC",</div><div class='del'>-				"NC",</div><div class='del'>-				"BOOT_CONFIG_5",</div><div class='del'>-				"NC",</div><div class='del'>-				"NC",</div><div class='del'>-				"NC",</div><div class='del'>-				"NC", /* GPIO 90 */</div><div class='del'>-				"NC",</div><div class='del'>-				"NC",</div><div class='del'>-				"NC",</div><div class='del'>-				"NC",</div><div class='del'>-				"NC",</div><div class='del'>-				"NC",</div><div class='del'>-				"NC",</div><div class='del'>-				"NC",</div><div class='del'>-				"NC",</div><div class='del'>-				"NC", /* GPIO 100 */</div><div class='del'>-				"NC",</div><div class='del'>-				"NC",</div><div class='del'>-				"NC",</div><div class='del'>-				"SSBI_GPS",</div><div class='del'>-				"NC",</div><div class='del'>-				"NC",</div><div class='del'>-				"KEY_VOLP_N",</div><div class='del'>-				"NC",</div><div class='del'>-				"NC",</div><div class='del'>-				"[LS_EXP_MI2S_WS]", /* GPIO 110 */</div><div class='del'>-				"NC",</div><div class='del'>-				"NC",</div><div class='del'>-				"[LS_EXP_MI2S_SCK]",</div><div class='del'>-				"[LS_EXP_MI2S_DATA0]",</div><div class='del'>-				"GPIO-E", /* LS_EXP_GPIO_E, LSEC pin 27 */</div><div class='del'>-				"NC",</div><div class='del'>-				"[DSI2HDMI_MI2S_WS]",</div><div class='del'>-				"[DSI2HDMI_MI2S_SCK]",</div><div class='del'>-				"[DSI2HDMI_MI2S_DATA0]",</div><div class='del'>-				"USR_LED_2_CTRL", /* GPIO 120 */</div><div class='del'>-				"SB_HS_ID";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		dma@7884000 {</div><div class='del'>-			status = "okay";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		serial@78af000 {</div><div class='del'>-			label = "LS-UART0";</div><div class='del'>-			status = "okay";</div><div class='del'>-			pinctrl-names = "default", "sleep";</div><div class='del'>-			pinctrl-0 = &lt;&amp;blsp1_uart1_default&gt;;</div><div class='del'>-			pinctrl-1 = &lt;&amp;blsp1_uart1_sleep&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		serial@78b0000 {</div><div class='del'>-			label = "LS-UART1";</div><div class='del'>-			status = "okay";</div><div class='del'>-			pinctrl-names = "default", "sleep";</div><div class='del'>-			pinctrl-0 = &lt;&amp;blsp1_uart2_default&gt;;</div><div class='del'>-			pinctrl-1 = &lt;&amp;blsp1_uart2_sleep&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		i2c@78b6000 {</div><div class='del'>-		/* On Low speed expansion */</div><div class='del'>-			label = "LS-I2C0";</div><div class='del'>-			status = "okay";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		i2c@78b8000 {</div><div class='del'>-		/* On High speed expansion */</div><div class='del'>-			label = "HS-I2C2";</div><div class='del'>-			status = "okay";</div><div class='del'>-</div><div class='del'>-			adv_bridge: bridge@39 {</div><div class='del'>-				status = "okay";</div><div class='del'>-</div><div class='del'>-				compatible = "adi,adv7533";</div><div class='del'>-				reg = &lt;0x39&gt;;</div><div class='del'>-</div><div class='del'>-				interrupt-parent = &lt;&amp;msmgpio&gt;;</div><div class='del'>-				interrupts = &lt;31 2&gt;;</div><div class='del'>-</div><div class='del'>-				adi,dsi-lanes = &lt;4&gt;;</div><div class='del'>-				clocks = &lt;&amp;rpmcc RPM_SMD_BB_CLK2&gt;;</div><div class='del'>-				clock-names = "cec";</div><div class='del'>-</div><div class='del'>-				pd-gpios = &lt;&amp;msmgpio 32 0&gt;;</div><div class='del'>-</div><div class='del'>-				avdd-supply = &lt;&amp;pm8916_l6&gt;;</div><div class='del'>-				v1p2-supply = &lt;&amp;pm8916_l6&gt;;</div><div class='del'>-				v3p3-supply = &lt;&amp;pm8916_l17&gt;;</div><div class='del'>-</div><div class='del'>-				pinctrl-names = "default","sleep";</div><div class='del'>-				pinctrl-0 = &lt;&amp;adv7533_int_active &amp;adv7533_switch_active&gt;;</div><div class='del'>-				pinctrl-1 = &lt;&amp;adv7533_int_suspend &amp;adv7533_switch_suspend&gt;;</div><div class='del'>-				#sound-dai-cells = &lt;1&gt;;</div><div class='del'>-</div><div class='del'>-				ports {</div><div class='del'>-					#address-cells = &lt;1&gt;;</div><div class='del'>-					#size-cells = &lt;0&gt;;</div><div class='del'>-</div><div class='del'>-					port@0 {</div><div class='del'>-						reg = &lt;0&gt;;</div><div class='del'>-						adv7533_in: endpoint {</div><div class='del'>-							remote-endpoint = &lt;&amp;dsi0_out&gt;;</div><div class='del'>-						};</div><div class='del'>-					};</div><div class='del'>-</div><div class='del'>-					port@1 {</div><div class='del'>-						reg = &lt;1&gt;;</div><div class='del'>-						adv7533_out: endpoint {</div><div class='del'>-							remote-endpoint = &lt;&amp;hdmi_con&gt;;</div><div class='del'>-						};</div><div class='del'>-					};</div><div class='del'>-				};</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		i2c@78ba000 {</div><div class='del'>-		/* On Low speed expansion */</div><div class='del'>-			label = "LS-I2C1";</div><div class='del'>-			status = "okay";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		spi@78b7000 {</div><div class='del'>-		/* On High speed expansion */</div><div class='del'>-			label = "HS-SPI1";</div><div class='del'>-			status = "okay";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		spi@78b9000 {</div><div class='del'>-		/* On Low speed expansion */</div><div class='del'>-			label = "LS-SPI0";</div><div class='del'>-			status = "okay";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		leds {</div><div class='del'>-			pinctrl-names = "default";</div><div class='del'>-			pinctrl-0 = &lt;&amp;msmgpio_leds&gt;,</div><div class='del'>-				    &lt;&amp;pm8916_gpios_leds&gt;,</div><div class='del'>-				    &lt;&amp;pm8916_mpps_leds&gt;;</div><div class='del'>-</div><div class='del'>-			compatible = "gpio-leds";</div><div class='del'>-</div><div class='del'>-			led@1 {</div><div class='del'>-				label = "apq8016-sbc:green:user1";</div><div class='del'>-				gpios = &lt;&amp;msmgpio 21 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-				linux,default-trigger = "heartbeat";</div><div class='del'>-				default-state = "off";</div><div class='del'>-			};</div><div class='del'>-</div><div class='del'>-			led@2 {</div><div class='del'>-				label = "apq8016-sbc:green:user2";</div><div class='del'>-				gpios = &lt;&amp;msmgpio 120 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-				linux,default-trigger = "mmc0";</div><div class='del'>-				default-state = "off";</div><div class='del'>-			};</div><div class='del'>-</div><div class='del'>-			led@3 {</div><div class='del'>-				label = "apq8016-sbc:green:user3";</div><div class='del'>-				gpios = &lt;&amp;pm8916_gpios 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-				linux,default-trigger = "mmc1";</div><div class='del'>-				default-state = "off";</div><div class='del'>-			};</div><div class='del'>-</div><div class='del'>-			led@4 {</div><div class='del'>-				label = "apq8016-sbc:green:user4";</div><div class='del'>-				gpios = &lt;&amp;pm8916_gpios 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-				linux,default-trigger = "none";</div><div class='del'>-				panic-indicator;</div><div class='del'>-				default-state = "off";</div><div class='del'>-			};</div><div class='del'>-</div><div class='del'>-			led@5 {</div><div class='del'>-				label = "apq8016-sbc:yellow:wlan";</div><div class='del'>-				gpios = &lt;&amp;pm8916_mpps 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-				linux,default-trigger = "phy0tx";</div><div class='del'>-				default-state = "off";</div><div class='del'>-			};</div><div class='del'>-</div><div class='del'>-			led@6 {</div><div class='del'>-				label = "apq8016-sbc:blue:bt";</div><div class='del'>-				gpios = &lt;&amp;pm8916_mpps 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-				linux,default-trigger = "bluetooth-power";</div><div class='del'>-				default-state = "off";</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		sdhci@7824000 {</div><div class='del'>-			vmmc-supply = &lt;&amp;pm8916_l8&gt;;</div><div class='del'>-			vqmmc-supply = &lt;&amp;pm8916_l5&gt;;</div><div class='del'>-</div><div class='del'>-			pinctrl-names = "default", "sleep";</div><div class='del'>-			pinctrl-0 = &lt;&amp;sdc1_clk_on &amp;sdc1_cmd_on &amp;sdc1_data_on&gt;;</div><div class='del'>-			pinctrl-1 = &lt;&amp;sdc1_clk_off &amp;sdc1_cmd_off &amp;sdc1_data_off&gt;;</div><div class='del'>-			status = "okay";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		sdhci@7864000 {</div><div class='del'>-			vmmc-supply = &lt;&amp;pm8916_l11&gt;;</div><div class='del'>-			vqmmc-supply = &lt;&amp;pm8916_l12&gt;;</div><div class='del'>-</div><div class='del'>-			pinctrl-names = "default", "sleep";</div><div class='del'>-			pinctrl-0 = &lt;&amp;sdc2_clk_on &amp;sdc2_cmd_on &amp;sdc2_data_on &amp;sdc2_cd_on&gt;;</div><div class='del'>-			pinctrl-1 = &lt;&amp;sdc2_clk_off &amp;sdc2_cmd_off &amp;sdc2_data_off &amp;sdc2_cd_off&gt;;</div><div class='del'>-</div><div class='del'>-			cd-gpios = &lt;&amp;msmgpio 38 0x1&gt;;</div><div class='del'>-			status = "okay";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		usb@78d9000 {</div><div class='del'>-			extcon = &lt;&amp;usb_id&gt;, &lt;&amp;usb_id&gt;;</div><div class='del'>-			status = "okay";</div><div class='del'>-			adp-disable;</div><div class='del'>-			hnp-disable;</div><div class='del'>-			srp-disable;</div><div class='del'>-			dr_mode = "otg";</div><div class='del'>-			pinctrl-names = "default", "device";</div><div class='del'>-			pinctrl-0 = &lt;&amp;usb_sw_sel_pm &amp;usb_hub_reset_pm&gt;;</div><div class='del'>-			pinctrl-1 = &lt;&amp;usb_sw_sel_pm_device &amp;usb_hub_reset_pm_device&gt;;</div><div class='del'>-			ulpi {</div><div class='del'>-				phy {</div><div class='del'>-					v1p8-supply = &lt;&amp;pm8916_l7&gt;;</div><div class='del'>-					v3p3-supply = &lt;&amp;pm8916_l13&gt;;</div><div class='del'>-					extcon = &lt;&amp;usb_id&gt;;</div><div class='del'>-				};</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		lpass@7708000 {</div><div class='del'>-			status = "okay";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		mdss@1a00000 {</div><div class='del'>-			status = "okay";</div><div class='del'>-</div><div class='del'>-			mdp@1a01000 {</div><div class='del'>-				status = "okay";</div><div class='del'>-			};</div><div class='del'>-</div><div class='del'>-			dsi@1a98000 {</div><div class='del'>-				status = "okay";</div><div class='del'>-</div><div class='del'>-				vdda-supply = &lt;&amp;pm8916_l2&gt;;</div><div class='del'>-				vddio-supply = &lt;&amp;pm8916_l6&gt;;</div><div class='del'>-</div><div class='del'>-				ports {</div><div class='del'>-					port@1 {</div><div class='del'>-						endpoint {</div><div class='del'>-							remote-endpoint = &lt;&amp;adv7533_in&gt;;</div><div class='del'>-							data-lanes = &lt;0 1 2 3&gt;;</div><div class='del'>-						};</div><div class='del'>-					};</div><div class='del'>-				};</div><div class='del'>-			};</div><div class='del'>-</div><div class='del'>-			dsi-phy@1a98300 {</div><div class='del'>-				status = "okay";</div><div class='del'>-</div><div class='del'>-				vddio-supply = &lt;&amp;pm8916_l6&gt;;</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		lpass_codec: codec{</div><div class='del'>-			status = "okay";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		/*</div><div class='del'>-		Internal Codec</div><div class='del'>-			playback - Primary MI2S</div><div class='del'>-			capture - Ter MI2S</div><div class='del'>-</div><div class='del'>-		External Primary:</div><div class='del'>-			playback - secondary MI2S</div><div class='del'>-			capture - Quat MI2S</div><div class='del'>-</div><div class='del'>-		External Secondary:</div><div class='del'>-			playback - Quat MI2S</div><div class='del'>-			capture - Quat MI2S</div><div class='del'>-</div><div class='del'>-		*/</div><div class='del'>-</div><div class='del'>-                sound: sound {</div><div class='del'>-                        compatible = "qcom,apq8016-sbc-sndcard";</div><div class='del'>-                        reg = &lt;0x07702000 0x4&gt;, &lt;0x07702004 0x4&gt;;</div><div class='del'>-                        reg-names = "mic-iomux", "spkr-iomux";</div><div class='del'>-</div><div class='del'>-                        status = "okay";</div><div class='del'>-                        pinctrl-0 = &lt;&amp;cdc_pdm_lines_act &amp;ext_sec_tlmm_lines_act &amp;ext_mclk_tlmm_lines_act&gt;;</div><div class='del'>-                        pinctrl-1 = &lt;&amp;cdc_pdm_lines_sus &amp;ext_sec_tlmm_lines_sus &amp;ext_mclk_tlmm_lines_sus&gt;;</div><div class='del'>-                        pinctrl-names = "default", "sleep";</div><div class='del'>-                        qcom,model = "DB410c";</div><div class='del'>-                        qcom,audio-routing =</div><div class='del'>-                                "AMIC2", "MIC BIAS Internal2",</div><div class='del'>-                                "AMIC3", "MIC BIAS External1";</div><div class='del'>-			external-dai-link@0 {</div><div class='del'>-				link-name = "ADV7533";</div><div class='del'>-				cpu { /* QUAT */</div><div class='del'>-					sound-dai = &lt;&amp;lpass MI2S_QUATERNARY&gt;;</div><div class='del'>-				};</div><div class='del'>-				codec {</div><div class='del'>-					sound-dai = &lt;&amp;adv_bridge 0&gt;;</div><div class='del'>-				};</div><div class='del'>-			};</div><div class='del'>-</div><div class='del'>-                        internal-codec-playback-dai-link@0 {            /* I2S - Internal codec */</div><div class='del'>-                                link-name = "WCD";</div><div class='del'>-                                cpu { /* PRIMARY */</div><div class='del'>-                                        sound-dai = &lt;&amp;lpass MI2S_PRIMARY&gt;;</div><div class='del'>-                                };</div><div class='del'>-                                codec {</div><div class='del'>-                                        sound-dai = &lt;&amp;lpass_codec 0&gt;, &lt;&amp;wcd_codec 0&gt;;</div><div class='del'>-                                };</div><div class='del'>-                        };</div><div class='del'>-</div><div class='del'>-                        internal-codec-capture-dai-link@0 {             /* I2S - Internal codec */</div><div class='del'>-                                link-name = "WCD-Capture";</div><div class='del'>-                                cpu { /* PRIMARY */</div><div class='del'>-                                        sound-dai = &lt;&amp;lpass MI2S_TERTIARY&gt;;</div><div class='del'>-                                };</div><div class='del'>-                                codec {</div><div class='del'>-                                        sound-dai = &lt;&amp;lpass_codec 1&gt;, &lt;&amp;wcd_codec 1&gt;;</div><div class='del'>-                                };</div><div class='del'>-                        };</div><div class='del'>-                };</div><div class='del'>-</div><div class='del'>-		spmi@200f000 {</div><div class='del'>-			pm8916@0 {</div><div class='del'>-				gpios@c000 {</div><div class='del'>-					gpio-line-names =</div><div class='del'>-						"USR_LED_3_CTRL",</div><div class='del'>-						"USR_LED_4_CTRL",</div><div class='del'>-						"USB_HUB_RESET_N_PM",</div><div class='del'>-						"USB_SW_SEL_PM";</div><div class='del'>-				};</div><div class='del'>-				mpps@a000 {</div><div class='del'>-					gpio-line-names =</div><div class='del'>-						"VDD_PX_BIAS",</div><div class='del'>-						"WLAN_LED_CTRL",</div><div class='del'>-						"BT_LED_CTRL",</div><div class='del'>-						"GPIO-F"; /* LS_EXP_GPIO_F, LSEC pin 28 */</div><div class='del'>-				};</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		wcnss@a21b000 {</div><div class='del'>-			status = "okay";</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	usb2513 {</div><div class='del'>-		compatible = "smsc,usb3503";</div><div class='del'>-		reset-gpios = &lt;&amp;pm8916_gpios 3 GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-		initial-mode = &lt;1&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	usb_id: usb-id {</div><div class='del'>-		compatible = "linux,extcon-usb-gpio";</div><div class='del'>-		id-gpio = &lt;&amp;msmgpio 121 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-		pinctrl-names = "default";</div><div class='del'>-		pinctrl-0 = &lt;&amp;usb_id_default&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	hdmi-out {</div><div class='del'>-		compatible = "hdmi-connector";</div><div class='del'>-		type = "a";</div><div class='del'>-</div><div class='del'>-		port {</div><div class='del'>-			hdmi_con: endpoint {</div><div class='del'>-				remote-endpoint = &lt;&amp;adv7533_out&gt;;</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	gpio_keys {</div><div class='del'>-		compatible = "gpio-keys";</div><div class='del'>-		#address-cells = &lt;1&gt;;</div><div class='del'>-		#size-cells = &lt;0&gt;;</div><div class='del'>-		autorepeat;</div><div class='del'>-</div><div class='del'>-		pinctrl-names = "default";</div><div class='del'>-		pinctrl-0 = &lt;&amp;msm_key_volp_n_default&gt;;</div><div class='del'>-</div><div class='del'>-		button@0 {</div><div class='del'>-			label = "Volume Up";</div><div class='del'>-			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='del'>-			gpios = &lt;&amp;msmgpio 107 GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;spmi_bus {</div><div class='del'>-	pm8916_0: pm8916@0 {</div><div class='del'>-		pon@800 {</div><div class='del'>-			resin {</div><div class='del'>-				compatible = "qcom,pm8941-resin";</div><div class='del'>-				interrupts = &lt;0x0 0x8 1 IRQ_TYPE_EDGE_BOTH&gt;;</div><div class='del'>-				debounce = &lt;15625&gt;;</div><div class='del'>-				bias-pull-up;</div><div class='del'>-				linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;wcd_codec {</div><div class='del'>-        status = "okay";</div><div class='del'>-        clocks = &lt;&amp;gcc GCC_CODEC_DIGCODEC_CLK&gt;;</div><div class='del'>-        clock-names = "mclk";</div><div class='del'>-	qcom,mbhc-vthreshold-low = &lt;75 150 237 450 500&gt;;</div><div class='del'>-	qcom,mbhc-vthreshold-high = &lt;75 150 237 450 500&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;smd_rpm_regulators {</div><div class='del'>-	vdd_l1_l2_l3-supply = &lt;&amp;pm8916_s3&gt;;</div><div class='del'>-	vdd_l4_l5_l6-supply = &lt;&amp;pm8916_s4&gt;;</div><div class='del'>-	vdd_l7-supply = &lt;&amp;pm8916_s4&gt;;</div><div class='del'>-</div><div class='del'>-	s1 {</div><div class='del'>-		regulator-min-microvolt = &lt;375000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;1562000&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	s3 {</div><div class='del'>-		regulator-min-microvolt = &lt;375000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;1562000&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	s4 {</div><div class='del'>-		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='del'>-</div><div class='del'>-		regulator-always-on;</div><div class='del'>-		regulator-boot-on;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	l1 {</div><div class='del'>-		regulator-min-microvolt = &lt;375000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;1525000&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	l2 {</div><div class='del'>-		regulator-min-microvolt = &lt;1200000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;1200000&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	l3 {</div><div class='del'>-		regulator-min-microvolt = &lt;375000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;1525000&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	l4 {</div><div class='del'>-		regulator-min-microvolt = &lt;1750000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;3337000&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	l5 {</div><div class='del'>-		regulator-min-microvolt = &lt;1750000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;3337000&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	l6 {</div><div class='del'>-		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	l7 {</div><div class='del'>-		regulator-min-microvolt = &lt;1750000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;3337000&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	l8 {</div><div class='del'>-		regulator-min-microvolt = &lt;1750000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;3337000&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	l9 {</div><div class='del'>-		regulator-min-microvolt = &lt;1750000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;3337000&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	l10 {</div><div class='del'>-		regulator-min-microvolt = &lt;1750000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;3337000&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	l11 {</div><div class='del'>-		regulator-min-microvolt = &lt;1750000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;3337000&gt;;</div><div class='del'>-		regulator-allow-set-load;</div><div class='del'>-		regulator-system-load = &lt;200000&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	l12 {</div><div class='del'>-		regulator-min-microvolt = &lt;1750000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;3337000&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	l13 {</div><div class='del'>-		regulator-min-microvolt = &lt;1750000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;3337000&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	l14 {</div><div class='del'>-		regulator-min-microvolt = &lt;1750000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;3337000&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	/**</div><div class='del'>-	 * 1.8v required on LS expansion</div><div class='del'>-	 * for mezzanine boards</div><div class='del'>-	 */</div><div class='del'>-	l15 {</div><div class='del'>-		regulator-min-microvolt = &lt;1750000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;3337000&gt;;</div><div class='del'>-		regulator-always-on;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	l16 {</div><div class='del'>-		regulator-min-microvolt = &lt;1750000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;3337000&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	l17 {</div><div class='del'>-		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	l18 {</div><div class='del'>-		regulator-min-microvolt = &lt;1750000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;3337000&gt;;</div><div class='del'>-	};</div><div class='del'>-};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/apq8016-schneider-hmibsc.dts b/arch/arm64/boot/dts/qcom/apq8016-schneider-hmibsc.dts<br/>new file mode 100644<br/>index 000000000000..ce75046ffdac<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/apq8016-schneider-hmibsc.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/apq8016-schneider-hmibsc.dts</a></div><div class='hunk'>@@ -0,0 +1,524 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2024, Linaro Ltd.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "msm8916-pm8916.dtsi"</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/qcom,pmic-gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/qcom,pmic-mpp.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/apq8016-lpass.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Schneider Electric HMIBSC Board";</div><div class='add'>+	compatible = "schneider,apq8016-hmibsc", "qcom,apq8016";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		i2c1 = &amp;blsp_i2c6;</div><div class='add'>+		i2c3 = &amp;blsp_i2c4;</div><div class='add'>+		i2c4 = &amp;blsp_i2c3;</div><div class='add'>+		mmc0 = &amp;sdhc_1; /* eMMC */</div><div class='add'>+		mmc1 = &amp;sdhc_2; /* SD card */</div><div class='add'>+		serial0 = &amp;blsp_uart1;</div><div class='add'>+		serial1 = &amp;blsp_uart2;</div><div class='add'>+		spi0 = &amp;blsp_spi5;</div><div class='add'>+		usid0 = &amp;pm8916_0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdmi-out {</div><div class='add'>+		compatible = "hdmi-connector";</div><div class='add'>+		type = "a";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			hdmi_con: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;adv7533_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		autorepeat;</div><div class='add'>+		pinctrl-0 = &lt;&amp;msm_key_volp_n_default&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		button {</div><div class='add'>+			label = "Volume Up";</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+			gpios = &lt;&amp;tlmm 107 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pm8916_mpps_leds&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			function = LED_FUNCTION_WLAN;</div><div class='add'>+			color = &lt;LED_COLOR_ID_YELLOW&gt;;</div><div class='add'>+			gpios = &lt;&amp;pm8916_mpps 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "phy0tx";</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-2 {</div><div class='add'>+			function = LED_FUNCTION_BLUETOOTH;</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			gpios = &lt;&amp;pm8916_mpps 3 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "bluetooth-power";</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@80000000 {</div><div class='add'>+		reg = &lt;0 0x80000000 0 0x40000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		ramoops@bff00000 {</div><div class='add'>+			compatible = "ramoops";</div><div class='add'>+			reg = &lt;0x0 0xbff00000 0x0 0x100000&gt;;</div><div class='add'>+			record-size = &lt;0x20000&gt;;</div><div class='add'>+			console-size = &lt;0x20000&gt;;</div><div class='add'>+			ftrace-size = &lt;0x20000&gt;;</div><div class='add'>+			ecc-size = &lt;16&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb-hub {</div><div class='add'>+		compatible = "smsc,usb3503";</div><div class='add'>+		reset-gpios = &lt;&amp;pm8916_gpios 1 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		initial-mode = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb_id: usb-id {</div><div class='add'>+		compatible = "linux,extcon-usb-gpio";</div><div class='add'>+		id-gpios = &lt;&amp;tlmm 110 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;usb_id_default&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_i2c3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	eeprom@50 {</div><div class='add'>+		compatible = "atmel,24c32";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_i2c4 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	adv_bridge: bridge@39 {</div><div class='add'>+		compatible = "adi,adv7533";</div><div class='add'>+		reg = &lt;0x39&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;tlmm 31 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+</div><div class='add'>+		adi,dsi-lanes = &lt;4&gt;;</div><div class='add'>+		clocks = &lt;&amp;rpmcc RPM_SMD_BB_CLK2&gt;;</div><div class='add'>+		clock-names = "cec";</div><div class='add'>+		pd-gpios = &lt;&amp;tlmm 32 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+		avdd-supply = &lt;&amp;pm8916_l6&gt;;</div><div class='add'>+		a2vdd-supply = &lt;&amp;pm8916_l6&gt;;</div><div class='add'>+		dvdd-supply = &lt;&amp;pm8916_l6&gt;;</div><div class='add'>+		pvdd-supply = &lt;&amp;pm8916_l6&gt;;</div><div class='add'>+		v1p2-supply = &lt;&amp;pm8916_l6&gt;;</div><div class='add'>+		v3p3-supply = &lt;&amp;pm8916_l17&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;adv7533_int_active &amp;adv7533_switch_active&gt;;</div><div class='add'>+		pinctrl-1 = &lt;&amp;adv7533_int_suspend &amp;adv7533_switch_suspend&gt;;</div><div class='add'>+		pinctrl-names = "default","sleep";</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				adv7533_in: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;mdss_dsi0_out&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				adv7533_out: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;hdmi_con&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_i2c6 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	rtc@30 {</div><div class='add'>+		compatible = "sii,s35390a";</div><div class='add'>+		reg = &lt;0x30&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@50 {</div><div class='add'>+		compatible = "atmel,24c256";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_spi5 {</div><div class='add'>+	cs-gpios = &lt;&amp;tlmm 18 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	tpm@0 {</div><div class='add'>+		compatible = "infineon,slb9670", "tcg,tpm_tis-spi";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;500000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_uart1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;blsp_uart1_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;blsp_uart1_sleep&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	label = "UART0";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_uart2 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;blsp_uart2_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;blsp_uart2_sleep&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	label = "UART1";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpass {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdss {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdss_dsi0_out {</div><div class='add'>+	data-lanes = &lt;0 1 2 3&gt;;</div><div class='add'>+	remote-endpoint = &lt;&amp;adv7533_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8916_codec {</div><div class='add'>+	qcom,mbhc-vthreshold-low = &lt;75 150 237 450 500&gt;;</div><div class='add'>+	qcom,mbhc-vthreshold-high = &lt;75 150 237 450 500&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8916_gpios {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"USB_HUB_RESET_N_PM",</div><div class='add'>+		"USB_SW_SEL_PM",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC";</div><div class='add'>+</div><div class='add'>+	usb_hub_reset_pm: usb-hub-reset-pm-state {</div><div class='add'>+		pins = "gpio1";</div><div class='add'>+		function = PMIC_GPIO_FUNC_NORMAL;</div><div class='add'>+		input-disable;</div><div class='add'>+		output-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb_hub_reset_pm_device: usb-hub-reset-pm-device-state {</div><div class='add'>+		pins = "gpio1";</div><div class='add'>+		function = PMIC_GPIO_FUNC_NORMAL;</div><div class='add'>+		input-disable;</div><div class='add'>+		output-low;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb_sw_sel_pm: usb-sw-sel-pm-state {</div><div class='add'>+		pins = "gpio2";</div><div class='add'>+		function = PMIC_GPIO_FUNC_NORMAL;</div><div class='add'>+		power-source = &lt;PM8916_GPIO_VPH&gt;;</div><div class='add'>+		input-disable;</div><div class='add'>+		output-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb_sw_sel_pm_device: usb-sw-sel-pm-device-state {</div><div class='add'>+		pins = "gpio2";</div><div class='add'>+		function = PMIC_GPIO_FUNC_NORMAL;</div><div class='add'>+		power-source = &lt;PM8916_GPIO_VPH&gt;;</div><div class='add'>+		input-disable;</div><div class='add'>+		output-low;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8916_mpps {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"NC",</div><div class='add'>+		"WLAN_LED_CTRL",</div><div class='add'>+		"BT_LED_CTRL",</div><div class='add'>+		"NC";</div><div class='add'>+</div><div class='add'>+	pm8916_mpps_leds: pm8916-mpps-state {</div><div class='add'>+		pins = "mpp2", "mpp3";</div><div class='add'>+		function = "digital";</div><div class='add'>+		output-low;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8916_resin {</div><div class='add'>+	linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8916_rpm_regulators {</div><div class='add'>+	pm8916_l17: l17 {</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sdhc_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sdhc_2 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdc2_default &amp;sdc2_cd_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;sdc2_sleep &amp;sdc2_cd_default&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	cd-gpios = &lt;&amp;tlmm 38 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sound {</div><div class='add'>+	pinctrl-0 = &lt;&amp;cdc_pdm_default &amp;sec_mi2s_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;cdc_pdm_sleep &amp;sec_mi2s_sleep&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	model = "HMIBSC";</div><div class='add'>+	audio-routing =</div><div class='add'>+		"AMIC2", "MIC BIAS Internal2",</div><div class='add'>+		"AMIC3", "MIC BIAS External1";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	quaternary-dai-link {</div><div class='add'>+		link-name = "ADV7533";</div><div class='add'>+		cpu {</div><div class='add'>+			sound-dai = &lt;&amp;lpass MI2S_QUATERNARY&gt;;</div><div class='add'>+		};</div><div class='add'>+		codec {</div><div class='add'>+			sound-dai = &lt;&amp;adv_bridge 0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	primary-dai-link {</div><div class='add'>+		link-name = "WCD";</div><div class='add'>+		cpu {</div><div class='add'>+			sound-dai = &lt;&amp;lpass MI2S_PRIMARY&gt;;</div><div class='add'>+		};</div><div class='add'>+		codec {</div><div class='add'>+			sound-dai = &lt;&amp;lpass_codec 0&gt;, &lt;&amp;pm8916_codec 0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	tertiary-dai-link {</div><div class='add'>+		link-name = "WCD-Capture";</div><div class='add'>+		cpu {</div><div class='add'>+			sound-dai = &lt;&amp;lpass MI2S_TERTIARY&gt;;</div><div class='add'>+		};</div><div class='add'>+		codec {</div><div class='add'>+			sound-dai = &lt;&amp;lpass_codec 1&gt;, &lt;&amp;pm8916_codec 1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tlmm {</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart1_mux0_rs232_high &amp;uart1_mux1_rs232_low&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	adv7533_int_active: adv533-int-active-state {</div><div class='add'>+		pins = "gpio31";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;16&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	adv7533_int_suspend: adv7533-int-suspend-state {</div><div class='add'>+		pins = "gpio31";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	adv7533_switch_active: adv7533-switch-active-state {</div><div class='add'>+		pins = "gpio32";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;16&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	adv7533_switch_suspend: adv7533-switch-suspend-state {</div><div class='add'>+		pins = "gpio32";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	blsp_uart1_default: blsp-uart1-default-state {</div><div class='add'>+		/* TX, RX, CTS_N, RTS_N */</div><div class='add'>+		pins = "gpio0", "gpio1", "gpio2", "gpio3";</div><div class='add'>+		function = "blsp_uart1";</div><div class='add'>+		drive-strength = &lt;16&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+		bootph-all;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	blsp_uart1_sleep: blsp-uart1-sleep-state {</div><div class='add'>+		pins = "gpio0", "gpio1", "gpio2", "gpio3";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-pull-down;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	blsp_uart2_default: blsp-uart2-default-state {</div><div class='add'>+		/* TX, RX */</div><div class='add'>+		pins = "gpio4", "gpio5";</div><div class='add'>+		function = "blsp_uart2";</div><div class='add'>+		drive-strength = &lt;16&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	blsp_uart2_sleep: blsp-uart2-sleep-state {</div><div class='add'>+		pins = "gpio4", "gpio5";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-pull-down;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	msm_key_volp_n_default: msm-key-volp-n-default-state {</div><div class='add'>+		pins = "gpio107";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;8&gt;;</div><div class='add'>+		bias-pull-up;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdc2_cd_default: sdc2-cd-default-state {</div><div class='add'>+		pins = "gpio38";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * UART1 being the debug console supports various modes of</div><div class='add'>+	 * operation (RS-232/485/422) controlled via GPIOs configured</div><div class='add'>+	 * mux as follows:</div><div class='add'>+	 *</div><div class='add'>+	 *   gpio100    gpio99    UART mode</div><div class='add'>+	 *   0          0         loopback</div><div class='add'>+	 *   0          1         RS-232</div><div class='add'>+	 *   1          0         RS-485</div><div class='add'>+	 *   1          1         RS-422</div><div class='add'>+	 *</div><div class='add'>+	 * The default mode configured here is RS-232 mode.</div><div class='add'>+	 */</div><div class='add'>+	uart1_mux0_rs232_high: uart1-mux0-rs232-state {</div><div class='add'>+		bootph-all;</div><div class='add'>+		pins = "gpio99";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;16&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+		output-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart1_mux1_rs232_low: uart1-mux1-rs232-state {</div><div class='add'>+		bootph-all;</div><div class='add'>+		pins = "gpio100";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;16&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+		output-low;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb_id_default: usb-id-default-state {</div><div class='add'>+		pins = "gpio110";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;8&gt;;</div><div class='add'>+		bias-pull-up;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb {</div><div class='add'>+	extcon = &lt;&amp;usb_id&gt;, &lt;&amp;usb_id&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;usb_sw_sel_pm &amp;usb_hub_reset_pm&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;usb_sw_sel_pm_device &amp;usb_hub_reset_pm_device&gt;;</div><div class='add'>+	pinctrl-names = "default", "device";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_hs_phy {</div><div class='add'>+	extcon = &lt;&amp;usb_id&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wcnss {</div><div class='add'>+	firmware-name = "qcom/apq8016/wcnss.mbn";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wcnss_ctrl {</div><div class='add'>+	firmware-name = "qcom/apq8016/WCNSS_qcom_wlan_nv_sbc.bin";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wcnss_iris {</div><div class='add'>+	compatible = "qcom,wcn3620";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wcnss_mem {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* PINCTRL - additions to nodes defined in msm8916.dtsi */</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * 2mA drive strength is not enough when connecting multiple</div><div class='add'>+ * I2C devices with different pull up resistors.</div><div class='add'>+ */</div><div class='add'>+&amp;blsp_i2c4_default {</div><div class='add'>+	drive-strength = &lt;16&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_i2c6_default {</div><div class='add'>+	drive-strength = &lt;16&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Enable CoreSight */</div><div class='add'>+&amp;cti0 { status = "okay"; };</div><div class='add'>+&amp;cti1 { status = "okay"; };</div><div class='add'>+&amp;cti12 { status = "okay"; };</div><div class='add'>+&amp;cti13 { status = "okay"; };</div><div class='add'>+&amp;cti14 { status = "okay"; };</div><div class='add'>+&amp;cti15 { status = "okay"; };</div><div class='add'>+&amp;debug0 { status = "okay"; };</div><div class='add'>+&amp;debug1 { status = "okay"; };</div><div class='add'>+&amp;debug2 { status = "okay"; };</div><div class='add'>+&amp;debug3 { status = "okay"; };</div><div class='add'>+&amp;etf { status = "okay"; };</div><div class='add'>+&amp;etm0 { status = "okay"; };</div><div class='add'>+&amp;etm1 { status = "okay"; };</div><div class='add'>+&amp;etm2 { status = "okay"; };</div><div class='add'>+&amp;etm3 { status = "okay"; };</div><div class='add'>+&amp;etr { status = "okay"; };</div><div class='add'>+&amp;funnel0 { status = "okay"; };</div><div class='add'>+&amp;funnel1 { status = "okay"; };</div><div class='add'>+&amp;replicator { status = "okay"; };</div><div class='add'>+&amp;stm { status = "okay"; };</div><div class='add'>+&amp;tpiu { status = "okay"; };</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/apq8039-t2.dts b/arch/arm64/boot/dts/qcom/apq8039-t2.dts<br/>new file mode 100644<br/>index 000000000000..38c281f0fe65<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/apq8039-t2.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/apq8039-t2.dts</a></div><div class='hunk'>@@ -0,0 +1,413 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2020-2023, Linaro Ltd.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "msm8939.dtsi"</div><div class='add'>+#include "msm8939-pm8916.dtsi"</div><div class='add'>+#include &lt;dt-bindings/arm/qcom,ids.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/qcom,pmic-gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/apq8016-lpass.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Square, Inc. T2 Devkit";</div><div class='add'>+	compatible = "square,apq8039-t2", "qcom,msm8939";</div><div class='add'>+</div><div class='add'>+	qcom,board-id = &lt;0x53 0x54&gt;;</div><div class='add'>+	qcom,msm-id = &lt;QCOM_ID_APQ8039 0x30000&gt;;</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		mmc0 = &amp;sdhc_1;</div><div class='add'>+		mmc1 = &amp;sdhc_2;</div><div class='add'>+		serial0 = &amp;blsp_uart1;</div><div class='add'>+		serial1 = &amp;blsp_uart2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bl: backlight {</div><div class='add'>+		compatible = "gpio-backlight";</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_backlight&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		gpios = &lt;&amp;tlmm 98 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial1:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vreg_lcd_avdd_reg: lcd-avdd-regulator {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "lcd_avdd";</div><div class='add'>+		regulator-min-microvolt = &lt;5600000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5600000&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_lcd_avdd_reg&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		gpio = &lt;&amp;tlmm 86 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		startup-delay-us = &lt;300&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vreg_lcd_avee_reg: lcd-avee-regulator {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "lcd_avee";</div><div class='add'>+		regulator-min-microvolt = &lt;5600000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5600000&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_lcd_avee_reg&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		gpio = &lt;&amp;tlmm 87 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		startup-delay-us = &lt;300&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vreg_lcd_iovcc_reg: lcd-iovcc-regulator {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "lcd_iovcc";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;pinctrl_lcd_iovcc_reg&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		gpio = &lt;&amp;tlmm 9 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		startup-delay-us = &lt;300&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_i2c1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_i2c2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_i2c3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	typec_pd: usb-pd@38 {</div><div class='add'>+		compatible = "ti,tps6598x";</div><div class='add'>+		reg = &lt;0x38&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-parent = &lt;&amp;tlmm&gt;;</div><div class='add'>+		interrupts = &lt;107 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		interrupt-names = "irq";</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;typec_irq&gt;;</div><div class='add'>+</div><div class='add'>+		typec_con: connector {</div><div class='add'>+			compatible = "usb-c-connector";</div><div class='add'>+			label = "USB-C";</div><div class='add'>+</div><div class='add'>+			port {</div><div class='add'>+				typec_ep: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;otg_ep&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_i2c5 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_uart1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;blsp_uart1_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;blsp_uart1_sleep&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_uart2 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;blsp_uart2_console_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;blsp_uart2_console_sleep&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpass {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpass_codec {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdss {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8916_codec {</div><div class='add'>+	qcom,hphl-jack-type-normally-open;</div><div class='add'>+	qcom,mbhc-vthreshold-low = &lt;75 150 237 450 500&gt;;</div><div class='add'>+	qcom,mbhc-vthreshold-high = &lt;75 150 237 450 500&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8916_gpios {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"PM_GPIO1",     /* WIFI_GPIO1_PRE */</div><div class='add'>+		"PM_GPIO2",     /* WIFI_GPIO2_PRE */</div><div class='add'>+		"PM_GPIO3",</div><div class='add'>+		"PM_GPIO4";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sdhc_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sound {</div><div class='add'>+	model = "apq8039-square-sndcard";</div><div class='add'>+	audio-routing = "AMIC2", "MIC BIAS Internal2";</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;cdc_pdm_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;cdc_pdm_sleep&gt;;</div><div class='add'>+</div><div class='add'>+	internal-codec-playback-dai-link {</div><div class='add'>+		link-name = "WCD";</div><div class='add'>+		cpu {</div><div class='add'>+			sound-dai = &lt;&amp;lpass MI2S_PRIMARY&gt;;</div><div class='add'>+		};</div><div class='add'>+		codec {</div><div class='add'>+			sound-dai = &lt;&amp;lpass_codec 0&gt;, &lt;&amp;pm8916_codec 0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	internal-codec-capture-dai-link {</div><div class='add'>+		link-name = "WCD-Capture";</div><div class='add'>+		cpu {</div><div class='add'>+			sound-dai = &lt;&amp;lpass MI2S_TERTIARY&gt;;</div><div class='add'>+		};</div><div class='add'>+		codec {</div><div class='add'>+			sound-dai = &lt;&amp;lpass_codec 1&gt;, &lt;&amp;pm8916_codec 1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Line names are taken from the schematic of T2, Ver X03.</div><div class='add'>+ * July 14, 2018. Page 4 in particular.</div><div class='add'>+ */</div><div class='add'>+&amp;tlmm {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"APQ_UART1_TX",		/* GPIO_0 */</div><div class='add'>+		"APQ_UART1_RX",</div><div class='add'>+		"APQ_I2C1_SDA",</div><div class='add'>+		"APQ_I2C1_SCL",</div><div class='add'>+		"APQ_UART2_TX_1V8",</div><div class='add'>+		"APQ_UART2_RX_1V8",</div><div class='add'>+		"APQ_I2C2_SDA",</div><div class='add'>+		"APQ_I2C2_SCL",</div><div class='add'>+		"NC",</div><div class='add'>+		"APQ_LCD_IOVCC_EN",</div><div class='add'>+		"APQ_I2C3_SDA",		/* GPIO_10 */</div><div class='add'>+		"APQ_I2C3_SCL",</div><div class='add'>+		"TOUCH_RST_1V8_L",</div><div class='add'>+		"NC",</div><div class='add'>+		"APQ_I2C4_SDA",</div><div class='add'>+		"APQ_I2C4_SCL",</div><div class='add'>+		"APQ_ID5",</div><div class='add'>+		"USB_DISCONNECT",</div><div class='add'>+		"APQ_I2C5_SDA",</div><div class='add'>+		"APQ_I2C5_SCL",</div><div class='add'>+		"APQ_USBC_SPI_MOSI",	/* GPIO_20 */</div><div class='add'>+		"APQ_USBC_SPI_MISO",</div><div class='add'>+		"APQ_USBC_SPI_SS_L",</div><div class='add'>+		"APQ_USBC_SPI_CLK",</div><div class='add'>+		"APQ_LCD_TE0",</div><div class='add'>+		"APQ_LCD_RST_L",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"ACCELEROMETER_INT1",</div><div class='add'>+		"APQ_CAM_I2C0_SDA",</div><div class='add'>+		"APQ_CAM_I2C0_SCL",	/* GPIO_30 */</div><div class='add'>+		"ACCELEROMETER_INT2",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"APQ_K21_RST_1V8_L",</div><div class='add'>+		"NC",</div><div class='add'>+		"APQ_EDL_1V8",</div><div class='add'>+		"TP145",</div><div class='add'>+		"BT_SSBI",</div><div class='add'>+		"NC",			/* GPIO_40 */</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"BT_CTRL",</div><div class='add'>+		"BT_DAT",</div><div class='add'>+		"PWR_GPIO_IN",</div><div class='add'>+		"PWR_GPIO_OUT",		/* GPIO_50 */</div><div class='add'>+		"CARD_DET_MLB_L",</div><div class='add'>+		"HALL_SENSOR",</div><div class='add'>+		"TP63",</div><div class='add'>+		"TP64",</div><div class='add'>+		"TP65",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",			/* GPIO_60 */</div><div class='add'>+		"NC",</div><div class='add'>+		"APQ_K21_GPIO0_1V8",</div><div class='add'>+		"CDC_PDM_CLK",</div><div class='add'>+		"CDC_PDM_SYNC",</div><div class='add'>+		"CDC_PDM_TX",</div><div class='add'>+		"CDC_PDM_RX0",</div><div class='add'>+		"CDC_PDM_RX1",</div><div class='add'>+		"CDC_PDM_RX2",</div><div class='add'>+		"APQ_K21_GPIO1_1V8",</div><div class='add'>+		"NC",			/* GPIO_70 */</div><div class='add'>+		"APQ_HUB_SEL_1V8",</div><div class='add'>+		"APQ_K21_GPIO2_1V8",</div><div class='add'>+		"APQ_K21_GPIO3_1V8",</div><div class='add'>+		"APQ_ID0",</div><div class='add'>+		"APQ_ID1",</div><div class='add'>+		"APQ_ID2",</div><div class='add'>+		"APQ_ID3",</div><div class='add'>+		"APQ_ID4",</div><div class='add'>+		"APQ_HUB_SUSP_IND",</div><div class='add'>+		"BOOT_CONFIG_0",	/* GPIO_80 */</div><div class='add'>+		"BOOT_CONFIG_1",</div><div class='add'>+		"BOOT_CONFIG_2",</div><div class='add'>+		"BOOT_CONFIG_3",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"APQ_LCD_AVDD_EN",</div><div class='add'>+		"APQ_LCD_AVEE_EN",</div><div class='add'>+		"TP70",</div><div class='add'>+		"NC",</div><div class='add'>+		"APQ_DEBUG0",		/* GPIO_90 */</div><div class='add'>+		"APQ_DEBUG1",</div><div class='add'>+		"APQ_DEBUG2",</div><div class='add'>+		"APQ_DEBUG3",</div><div class='add'>+		"TP165",</div><div class='add'>+		"NC",</div><div class='add'>+		"APQ_LNA_PWR_EN",</div><div class='add'>+		"NC",</div><div class='add'>+		"APQ_LCD_BL_EN",</div><div class='add'>+		"NC",</div><div class='add'>+		"APQ_LCD_ID0",		/* GPIO_100 */</div><div class='add'>+		"APQ_LCD_ID1",</div><div class='add'>+		"USBC_GPIO5_1V8",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"APQ_HUB_RST_1V8_L",</div><div class='add'>+		"USBC_I2C_IRQ_1V8_L",</div><div class='add'>+		"SPE_PWR_EN",</div><div class='add'>+		"NC",</div><div class='add'>+		"APQ_USB_ID",		/* GPIO_110 */</div><div class='add'>+		"APQ_EXT_BUCK_VSEL",</div><div class='add'>+		"APQ_USB_ID_OUT",</div><div class='add'>+		"NC",</div><div class='add'>+		"PRNT_RST_L",</div><div class='add'>+		"APQ_CRQ_I2C_RDY_1V8",</div><div class='add'>+		"TYPEC_RST_1V8_H",</div><div class='add'>+		"CHG_BACKPWR_EN",</div><div class='add'>+		"CHG_PROCHOT_L",</div><div class='add'>+		"NC",</div><div class='add'>+		"USBC_GPIO7_1V8",	/* GPIO_120 */</div><div class='add'>+		"NC";</div><div class='add'>+</div><div class='add'>+	blsp_uart1_default: blsp-uart1-default-state {</div><div class='add'>+		pins = "gpio0", "gpio1";</div><div class='add'>+		function = "blsp_uart1";</div><div class='add'>+		drive-strength = &lt;16&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	blsp_uart1_sleep: blsp-uart1-sleep-state {</div><div class='add'>+		pins = "gpio0", "gpio1";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-pull-down;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_backlight: backlight-state {</div><div class='add'>+		pins = "gpio98";</div><div class='add'>+		function = "gpio";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lcd_avdd_reg: lcd-avdd-reg-state {</div><div class='add'>+		pins = "gpio86";</div><div class='add'>+		function = "gpio";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lcd_avee_reg: lcd-avee-reg-state {</div><div class='add'>+		pins = "gpio87";</div><div class='add'>+		function = "gpio";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lcd_iovcc_reg: lcd-iovcc-reg-state {</div><div class='add'>+		pins = "gpio9";</div><div class='add'>+		function = "gpio";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_lcd_rst: lcd-rst-state {</div><div class='add'>+		pins = "gpio25";</div><div class='add'>+		function = "gpio";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_otg_default: otg-default-state {</div><div class='add'>+		function = "gpio";</div><div class='add'>+		pins = "gpio17";</div><div class='add'>+		output-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_otg_device: otg-device-state {</div><div class='add'>+		function = "gpio";</div><div class='add'>+		pins = "gpio17";</div><div class='add'>+		output-low;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pinctrl_otg_host: otg-host-state {</div><div class='add'>+		function = "gpio";</div><div class='add'>+		pins = "gpio17";</div><div class='add'>+		output-low;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	typec_irq: typec-irq-state {</div><div class='add'>+		function = "gpio";</div><div class='add'>+		pins = "gpio107";</div><div class='add'>+		bias-pull-up;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb {</div><div class='add'>+	pinctrl-names = "default", "host", "device";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pinctrl_otg_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;pinctrl_otg_host&gt;;</div><div class='add'>+	pinctrl-2 = &lt;&amp;pinctrl_otg_device&gt;;</div><div class='add'>+	usb-role-switch;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	port {</div><div class='add'>+		otg_ep: endpoint {</div><div class='add'>+			remote-endpoint = &lt;&amp;typec_ep&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wcnss {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wcnss_iris {</div><div class='add'>+	compatible = "qcom,wcn3680";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wcnss_mem {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/apq8094-sony-xperia-kitakami-karin_windy.dts b/arch/arm64/boot/dts/qcom/apq8094-sony-xperia-kitakami-karin_windy.dts<br/>new file mode 100644<br/>index 000000000000..314d2dc4726a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/apq8094-sony-xperia-kitakami-karin_windy.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/apq8094-sony-xperia-kitakami-karin_windy.dts</a></div><div class='hunk'>@@ -0,0 +1,24 @@</div><div class='add'>+// SPDX-License-Identifier: BSD-3-Clause</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2020, Konrad Dybcio &lt;konrad.dybcio@somainline.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+/* As the names may imply, there is quite a bunch of duplication there. */</div><div class='add'>+#include "msm8994-sony-xperia-kitakami-karin.dts"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Sony Xperia Z4 Tablet (Wi-Fi)";</div><div class='add'>+	compatible = "sony,karin_windy", "qcom,apq8094";</div><div class='add'>+	chassis-type = "tablet";</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * This model uses the APQ variant of MSM8994 (APQ8094).</div><div class='add'>+	 * The v1/v2/v2.1 story (from kitakami.dtsi) also applies here.</div><div class='add'>+	 */</div><div class='add'>+	qcom,msm-id = &lt;253 0x20000&gt;, &lt;253 0x20001&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/delete-node/ &amp;pm8994_l1;</div><div class='add'>+/delete-node/ &amp;pm8994_l19;</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts<br/>index 757afa27424d..9fa70ff6887b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/apq8096-db820c.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/apq8096-db820c.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/apq8096-db820c.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/apq8096-db820c.dts</a></div><div class='hunk'>@@ -5,9 +5,1134 @@</div><div class='ctx'> </div><div class='ctx'> /dts-v1/;</div><div class='ctx'> </div><div class='del'>-#include "apq8096-db820c.dtsi"</div><div class='add'>+#include "msm8996.dtsi"</div><div class='add'>+#include "pm8994.dtsi"</div><div class='add'>+#include "pmi8994.dtsi"</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/qcom,pmic-gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/qcom,q6afe.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/qcom,q6asm.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/qcom,wcd9335.h&gt;</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * GPIO name legend: proper name = the GPIO line is used as GPIO</div><div class='add'>+ *         NC      = not connected (pin out but not routed from the chip to</div><div class='add'>+ *                   anything the board)</div><div class='add'>+ *         "[PER]" = pin is muxed for [peripheral] (not GPIO)</div><div class='add'>+ *         LSEC    = Low Speed External Connector</div><div class='add'>+ *         P HSEC  = Primary High Speed External Connector</div><div class='add'>+ *         S HSEC  = Secondary High Speed External Connector</div><div class='add'>+ *         J14     = Camera Connector</div><div class='add'>+ *         TP      = Test Points</div><div class='add'>+ *</div><div class='add'>+ * Line names are taken from the schematic "DragonBoard 820c",</div><div class='add'>+ * drawing no: LM25-P2751-1</div><div class='add'>+ *</div><div class='add'>+ * For the lines routed to the external connectors the</div><div class='add'>+ * lines are named after the 96Boards CE Specification 1.0,</div><div class='add'>+ * Appendix "Expansion Connector Signal Description".</div><div class='add'>+ *</div><div class='add'>+ * When the 96Board naming of a line and the schematic name of</div><div class='add'>+ * the same line are in conflict, the 96Board specification</div><div class='add'>+ * takes precedence, which means that the external UART on the</div><div class='add'>+ * LSEC is named UART0 while the schematic and SoC names this</div><div class='add'>+ * UART3. This is only for the informational lines i.e. "[FOO]",</div><div class='add'>+ * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only</div><div class='add'>+ * ones actually used for GPIO.</div><div class='add'>+ */</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	model = "Qualcomm Technologies, Inc. DB820c";</div><div class='ctx'> 	compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc", "qcom,apq8096";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;blsp2_uart2;</div><div class='add'>+		serial1 = &amp;blsp2_uart3;</div><div class='add'>+		serial2 = &amp;blsp1_uart2;</div><div class='add'>+		i2c0 = &amp;blsp1_i2c3;</div><div class='add'>+		i2c1 = &amp;blsp2_i2c1;</div><div class='add'>+		i2c2 = &amp;blsp2_i2c1;</div><div class='add'>+		spi0 = &amp;blsp1_spi1;</div><div class='add'>+		spi1 = &amp;blsp2_spi6;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	div1_mclk: divclk1 {</div><div class='add'>+		compatible = "gpio-gate-clock";</div><div class='add'>+		pinctrl-0 = &lt;&amp;audio_mclk&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		clocks = &lt;&amp;rpmcc RPM_SMD_DIV_CLK1&gt;;</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;pm8994_gpios 15 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	divclk4: divclk4 {</div><div class='add'>+		compatible = "fixed-clock";</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-frequency = &lt;32768&gt;;</div><div class='add'>+		clock-output-names = "divclk4";</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;divclk4_pin_a&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		autorepeat;</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;volume_up_gpio&gt;;</div><div class='add'>+</div><div class='add'>+		button {</div><div class='add'>+			label = "Volume Up";</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+			gpios = &lt;&amp;pm8994_gpios 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb2_id: usb2-id {</div><div class='add'>+		compatible = "linux,extcon-usb-gpio";</div><div class='add'>+		id-gpios = &lt;&amp;pmi8994_gpios 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;usb2_vbus_det_gpio&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb3_id: usb3-id {</div><div class='add'>+		compatible = "linux,extcon-usb-gpio";</div><div class='add'>+		id-gpios = &lt;&amp;pm8994_gpios 22 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;usb3_vbus_det_gpio&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vph_pwr: vph-pwr-regulator {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vph_pwr";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+</div><div class='add'>+		regulator-min-microvolt = &lt;3700000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3700000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wlan_en: wlan-en-1-8v {</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;wlan_en_gpios&gt;;</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "wlan-en-regulator";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;pm8994_gpios 8 0&gt;;</div><div class='add'>+</div><div class='add'>+		/* WLAN card specific delay */</div><div class='add'>+		startup-delay-us = &lt;70000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp1_i2c3 {</div><div class='add'>+	/* On Low speed expansion: LS-I2C0 */</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp1_spi1 {</div><div class='add'>+	/* On Low speed expansion */</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp1_uart2 {</div><div class='add'>+	label = "BT-UART";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "qcom,qca6174-bt";</div><div class='add'>+</div><div class='add'>+		/* bt_disable_n gpio */</div><div class='add'>+		enable-gpios = &lt;&amp;pm8994_gpios 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;divclk4&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;adsp_pil {</div><div class='add'>+	status = "okay";</div><div class='add'>+	firmware-name = "qcom/apq8096/adsp.mbn";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp2_i2c1 {</div><div class='add'>+	/* On High speed expansion: HS-I2C2 */</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp2_i2c1 {</div><div class='add'>+	/* On Low speed expansion: LS-I2C1 */</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp2_spi6 {</div><div class='add'>+	/* On High speed expansion */</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp2_uart2 {</div><div class='add'>+	label = "LS-UART1";</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;blsp2_uart2_2pins_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;blsp2_uart2_2pins_sleep&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp2_uart3 {</div><div class='add'>+	label = "LS-UART0";</div><div class='add'>+	status = "disabled";</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;blsp2_uart3_4pins_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;blsp2_uart3_4pins_sleep&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;camss {</div><div class='add'>+	vdda-supply = &lt;&amp;vreg_l2a_1p25&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu_zap_shader {</div><div class='add'>+	firmware-name = "qcom/apq8096/a530_zap.mbn";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hsusb_phy1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	vdd-supply = &lt;&amp;vreg_l28a_0p925&gt;;</div><div class='add'>+	vdda-pll-supply = &lt;&amp;vreg_l12a_1p8&gt;;</div><div class='add'>+	vdda-phy-dpdm-supply = &lt;&amp;vreg_l24a_3p075&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;hsusb_phy2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	vdd-supply = &lt;&amp;vreg_l28a_0p925&gt;;</div><div class='add'>+	vdda-pll-supply = &lt;&amp;vreg_l12a_1p8&gt;;</div><div class='add'>+	vdda-phy-dpdm-supply = &lt;&amp;vreg_l24a_3p075&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdp {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdss {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdss_hdmi {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;hdmi_hpd_active &amp;hdmi_ddc_active&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;hdmi_hpd_suspend &amp;hdmi_ddc_suspend&gt;;</div><div class='add'>+</div><div class='add'>+	core-vdda-supply = &lt;&amp;vreg_l12a_1p8&gt;;</div><div class='add'>+	core-vcc-supply = &lt;&amp;vreg_s4a_1p8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdss_hdmi_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	vddio-supply = &lt;&amp;vreg_l12a_1p8&gt;;</div><div class='add'>+	vcca-supply = &lt;&amp;vreg_l28a_0p925&gt;;</div><div class='add'>+	#phy-cells = &lt;0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mmcc {</div><div class='add'>+	vdd-gfx-supply = &lt;&amp;vdd_gfx&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mss_pil {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pll-supply = &lt;&amp;vreg_l12a_1p8&gt;;</div><div class='add'>+	firmware-name = "qcom/apq8096/mba.mbn", "qcom/apq8096/modem.mbn";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8994_resin {</div><div class='add'>+	status = "okay";</div><div class='add'>+	linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tlmm {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"[SPI0_DOUT]", /* GPIO_0, BLSP1_SPI_MOSI, LSEC pin 14 */</div><div class='add'>+		"[SPI0_DIN]", /* GPIO_1, BLSP1_SPI_MISO, LSEC pin 10 */</div><div class='add'>+		"[SPI0_CS]", /* GPIO_2, BLSP1_SPI_CS_N, LSEC pin 12 */</div><div class='add'>+		"[SPI0_SCLK]", /* GPIO_3, BLSP1_SPI_CLK, LSEC pin 8 */</div><div class='add'>+		"[UART1_TxD]", /* GPIO_4, BLSP8_UART_TX, LSEC pin 11 */</div><div class='add'>+		"[UART1_RxD]", /* GPIO_5, BLSP8_UART_RX, LSEC pin 13 */</div><div class='add'>+		"[I2C1_SDA]", /* GPIO_6, BLSP8_I2C_SDA, LSEC pin 21 */</div><div class='add'>+		"[I2C1_SCL]", /* GPIO_7, BLSP8_I2C_SCL, LSEC pin 19 */</div><div class='add'>+		"GPIO-H", /* GPIO_8, LCD0_RESET_N, LSEC pin 30 */</div><div class='add'>+		"TP93", /* GPIO_9 */</div><div class='add'>+		"GPIO-G", /* GPIO_10, MDP_VSYNC_P, LSEC pin 29 */</div><div class='add'>+		"[MDP_VSYNC_S]", /* GPIO_11, S HSEC pin 55 */</div><div class='add'>+		"NC", /* GPIO_12 */</div><div class='add'>+		"[CSI0_MCLK]", /* GPIO_13, CAM_MCLK0, P HSEC pin 15 */</div><div class='add'>+		"[CAM_MCLK1]", /* GPIO_14, J14 pin 11 */</div><div class='add'>+		"[CSI1_MCLK]", /* GPIO_15, CAM_MCLK2, P HSEC pin 17 */</div><div class='add'>+		"TP99", /* GPIO_16 */</div><div class='add'>+		"[I2C2_SDA]", /* GPIO_17, CCI_I2C_SDA0, P HSEC pin 34 */</div><div class='add'>+		"[I2C2_SCL]", /* GPIO_18, CCI_I2C_SCL0, P HSEC pin 32 */</div><div class='add'>+		"[CCI_I2C_SDA1]", /* GPIO_19, S HSEC pin 38 */</div><div class='add'>+		"[CCI_I2C_SCL1]", /* GPIO_20, S HSEC pin 36 */</div><div class='add'>+		"FLASH_STROBE_EN", /* GPIO_21, S HSEC pin 5 */</div><div class='add'>+		"FLASH_STROBE_TRIG", /* GPIO_22, S HSEC pin 1 */</div><div class='add'>+		"GPIO-K", /* GPIO_23, CAM2_RST_N, LSEC pin 33 */</div><div class='add'>+		"GPIO-D", /* GPIO_24, LSEC pin 26 */</div><div class='add'>+		"GPIO-I", /* GPIO_25, CAM0_RST_N, LSEC pin 31 */</div><div class='add'>+		"GPIO-J", /* GPIO_26, CAM0_STANDBY_N, LSEC pin 32 */</div><div class='add'>+		"BLSP6_I2C_SDA", /* GPIO_27 */</div><div class='add'>+		"BLSP6_I2C_SCL", /* GPIO_28 */</div><div class='add'>+		"GPIO-B", /* GPIO_29, TS0_RESET_N, LSEC pin 24 */</div><div class='add'>+		"GPIO30", /* GPIO_30, S HSEC pin 4 */</div><div class='add'>+		"HDMI_CEC", /* GPIO_31 */</div><div class='add'>+		"HDMI_DDC_CLOCK", /* GPIO_32 */</div><div class='add'>+		"HDMI_DDC_DATA", /* GPIO_33 */</div><div class='add'>+		"HDMI_HOT_PLUG_DETECT", /* GPIO_34 */</div><div class='add'>+		"PCIE0_RST_N", /* GPIO_35 */</div><div class='add'>+		"PCIE0_CLKREQ_N", /* GPIO_36 */</div><div class='add'>+		"PCIE0_WAKE", /* GPIO_37 */</div><div class='add'>+		"SD_CARD_DET_N", /* GPIO_38 */</div><div class='add'>+		"TSIF1_SYNC", /* GPIO_39, S HSEC pin 48 */</div><div class='add'>+		"W_DISABLE_N", /* GPIO_40 */</div><div class='add'>+		"[BLSP9_UART_TX]", /* GPIO_41 */</div><div class='add'>+		"[BLSP9_UART_RX]", /* GPIO_42 */</div><div class='add'>+		"[BLSP2_UART_CTS_N]", /* GPIO_43 */</div><div class='add'>+		"[BLSP2_UART_RFR_N]", /* GPIO_44 */</div><div class='add'>+		"[BLSP3_UART_TX]", /* GPIO_45 */</div><div class='add'>+		"[BLSP3_UART_RX]", /* GPIO_46 */</div><div class='add'>+		"[I2C0_SDA]", /* GPIO_47, LS_I2C0_SDA, LSEC pin 17 */</div><div class='add'>+		"[I2C0_SCL]", /* GPIO_48, LS_I2C0_SCL, LSEC pin 15 */</div><div class='add'>+		"[UART0_TxD]", /* GPIO_49, BLSP9_UART_TX, LSEC pin 5 */</div><div class='add'>+		"[UART0_RxD]", /* GPIO_50, BLSP9_UART_RX, LSEC pin 7 */</div><div class='add'>+		"[UART0_CTS]", /* GPIO_51, BLSP9_UART_CTS_N, LSEC pin 3 */</div><div class='add'>+		"[UART0_RTS]", /* GPIO_52, BLSP9_UART_RFR_N, LSEC pin 9 */</div><div class='add'>+		"[CODEC_INT1_N]", /* GPIO_53 */</div><div class='add'>+		"[CODEC_INT2_N]", /* GPIO_54 */</div><div class='add'>+		"[BLSP7_I2C_SDA]", /* GPIO_55 */</div><div class='add'>+		"[BLSP7_I2C_SCL]", /* GPIO_56 */</div><div class='add'>+		"MI2S_MCLK", /* GPIO_57, S HSEC pin 3 */</div><div class='add'>+		"[PCM_CLK]", /* GPIO_58, QUA_MI2S_SCK, LSEC pin 18 */</div><div class='add'>+		"[PCM_FS]", /* GPIO_59, QUA_MI2S_WS, LSEC pin 16 */</div><div class='add'>+		"[PCM_DO]", /* GPIO_60, QUA_MI2S_DATA0, LSEC pin 20 */</div><div class='add'>+		"[PCM_DI]", /* GPIO_61, QUA_MI2S_DATA1, LSEC pin 22 */</div><div class='add'>+		"GPIO-E", /* GPIO_62, LSEC pin 27 */</div><div class='add'>+		"TP87", /* GPIO_63 */</div><div class='add'>+		"[CODEC_RST_N]", /* GPIO_64 */</div><div class='add'>+		"[PCM1_CLK]", /* GPIO_65 */</div><div class='add'>+		"[PCM1_SYNC]", /* GPIO_66 */</div><div class='add'>+		"[PCM1_DIN]", /* GPIO_67 */</div><div class='add'>+		"[PCM1_DOUT]", /* GPIO_68 */</div><div class='add'>+		"AUDIO_REF_CLK", /* GPIO_69 */</div><div class='add'>+		"SLIMBUS_CLK", /* GPIO_70 */</div><div class='add'>+		"SLIMBUS_DATA0", /* GPIO_71 */</div><div class='add'>+		"SLIMBUS_DATA1", /* GPIO_72 */</div><div class='add'>+		"NC", /* GPIO_73 */</div><div class='add'>+		"NC", /* GPIO_74 */</div><div class='add'>+		"NC", /* GPIO_75 */</div><div class='add'>+		"NC", /* GPIO_76 */</div><div class='add'>+		"TP94", /* GPIO_77 */</div><div class='add'>+		"NC", /* GPIO_78 */</div><div class='add'>+		"TP95", /* GPIO_79 */</div><div class='add'>+		"GPIO-A", /* GPIO_80, MEMS_RESET_N, LSEC pin 23 */</div><div class='add'>+		"TP88", /* GPIO_81 */</div><div class='add'>+		"TP89", /* GPIO_82 */</div><div class='add'>+		"TP90", /* GPIO_83 */</div><div class='add'>+		"TP91", /* GPIO_84 */</div><div class='add'>+		"[SD_DAT0]", /* GPIO_85, BLSP12_SPI_MOSI, P HSEC pin 1 */</div><div class='add'>+		"[SD_CMD]", /* GPIO_86, BLSP12_SPI_MISO, P HSEC pin 11 */</div><div class='add'>+		"[SD_DAT3]", /* GPIO_87, BLSP12_SPI_CS_N, P HSEC pin 7 */</div><div class='add'>+		"[SD_SCLK]", /* GPIO_88, BLSP12_SPI_CLK, P HSEC pin 9 */</div><div class='add'>+		"TSIF1_CLK", /* GPIO_89, S HSEC pin 42 */</div><div class='add'>+		"TSIF1_EN", /* GPIO_90, S HSEC pin 46 */</div><div class='add'>+		"TSIF1_DATA", /* GPIO_91, S HSEC pin 44 */</div><div class='add'>+		"NC", /* GPIO_92 */</div><div class='add'>+		"TSIF2_CLK", /* GPIO_93, S HSEC pin 52 */</div><div class='add'>+		"TSIF2_EN", /* GPIO_94, S HSEC pin 56 */</div><div class='add'>+		"TSIF2_DATA", /* GPIO_95, S HSEC pin 54 */</div><div class='add'>+		"TSIF2_SYNC", /* GPIO_96, S HSEC pin 58 */</div><div class='add'>+		"NC", /* GPIO_97 */</div><div class='add'>+		"CAM1_STANDBY_N", /* GPIO_98 */</div><div class='add'>+		"NC", /* GPIO_99 */</div><div class='add'>+		"NC", /* GPIO_100 */</div><div class='add'>+		"[LCD1_RESET_N]", /* GPIO_101, S HSEC pin 51 */</div><div class='add'>+		"BOOT_CONFIG1", /* GPIO_102 */</div><div class='add'>+		"USB_HUB_RESET", /* GPIO_103 */</div><div class='add'>+		"CAM1_RST_N", /* GPIO_104 */</div><div class='add'>+		"NC", /* GPIO_105 */</div><div class='add'>+		"NC", /* GPIO_106 */</div><div class='add'>+		"NC", /* GPIO_107 */</div><div class='add'>+		"NC", /* GPIO_108 */</div><div class='add'>+		"NC", /* GPIO_109 */</div><div class='add'>+		"NC", /* GPIO_110 */</div><div class='add'>+		"NC", /* GPIO_111 */</div><div class='add'>+		"NC", /* GPIO_112 */</div><div class='add'>+		"PMI8994_BUA", /* GPIO_113 */</div><div class='add'>+		"PCIE2_RST_N", /* GPIO_114 */</div><div class='add'>+		"PCIE2_CLKREQ_N", /* GPIO_115 */</div><div class='add'>+		"PCIE2_WAKE", /* GPIO_116 */</div><div class='add'>+		"SSC_IRQ_0", /* GPIO_117 */</div><div class='add'>+		"SSC_IRQ_1", /* GPIO_118 */</div><div class='add'>+		"SSC_IRQ_2", /* GPIO_119 */</div><div class='add'>+		"NC", /* GPIO_120 */</div><div class='add'>+		"GPIO121", /* GPIO_121, S HSEC pin 2 */</div><div class='add'>+		"NC", /* GPIO_122 */</div><div class='add'>+		"SSC_IRQ_6", /* GPIO_123 */</div><div class='add'>+		"SSC_IRQ_7", /* GPIO_124 */</div><div class='add'>+		"GPIO-C", /* GPIO_125, TS_INT0, LSEC pin 25 */</div><div class='add'>+		"BOOT_CONFIG5", /* GPIO_126 */</div><div class='add'>+		"NC", /* GPIO_127 */</div><div class='add'>+		"NC", /* GPIO_128 */</div><div class='add'>+		"BOOT_CONFIG7", /* GPIO_129 */</div><div class='add'>+		"PCIE1_RST_N", /* GPIO_130 */</div><div class='add'>+		"PCIE1_CLKREQ_N", /* GPIO_131 */</div><div class='add'>+		"PCIE1_WAKE", /* GPIO_132 */</div><div class='add'>+		"GPIO-L", /* GPIO_133, CAM2_STANDBY_N, LSEC pin 34 */</div><div class='add'>+		"NC", /* GPIO_134 */</div><div class='add'>+		"NC", /* GPIO_135 */</div><div class='add'>+		"BOOT_CONFIG8", /* GPIO_136 */</div><div class='add'>+		"NC", /* GPIO_137 */</div><div class='add'>+		"NC", /* GPIO_138 */</div><div class='add'>+		"GPS_SSBI2", /* GPIO_139 */</div><div class='add'>+		"GPS_SSBI1", /* GPIO_140 */</div><div class='add'>+		"NC", /* GPIO_141 */</div><div class='add'>+		"NC", /* GPIO_142 */</div><div class='add'>+		"NC", /* GPIO_143 */</div><div class='add'>+		"BOOT_CONFIG6", /* GPIO_144 */</div><div class='add'>+		"NC", /* GPIO_145 */</div><div class='add'>+		"NC", /* GPIO_146 */</div><div class='add'>+		"NC", /* GPIO_147 */</div><div class='add'>+		"NC", /* GPIO_148 */</div><div class='add'>+		"NC"; /* GPIO_149 */</div><div class='add'>+</div><div class='add'>+	sdc2_cd_on: sdc2-cd-on-state {</div><div class='add'>+		pins = "gpio38";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		bias-pull-up;</div><div class='add'>+		drive-strength = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdc2_cd_off: sdc2-cd-off-state {</div><div class='add'>+		pins = "gpio38";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		bias-pull-up;</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdmi_hpd_active: hdmi-hpd-active-state {</div><div class='add'>+		pins = "gpio34";</div><div class='add'>+		function = "hdmi_hot";</div><div class='add'>+		bias-pull-down;</div><div class='add'>+		drive-strength = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdmi_hpd_suspend: hdmi-hpd-suspend-state {</div><div class='add'>+		pins = "gpio34";</div><div class='add'>+		function = "hdmi_hot";</div><div class='add'>+		bias-pull-down;</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdmi_ddc_active: hdmi-ddc-active-state {</div><div class='add'>+		pins = "gpio32", "gpio33";</div><div class='add'>+		function = "hdmi_ddc";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-pull-up;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdmi_ddc_suspend: hdmi-ddc-suspend-state {</div><div class='add'>+		pins = "gpio32", "gpio33";</div><div class='add'>+		function = "hdmi_ddc";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-pull-down;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	perst-gpios = &lt;&amp;tlmm 35 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vddpe-3v3-supply = &lt;&amp;wlan_en&gt;;</div><div class='add'>+	vdda-supply = &lt;&amp;vreg_l28a_0p925&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	perst-gpios = &lt;&amp;tlmm 130 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vdda-supply = &lt;&amp;vreg_l28a_0p925&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	perst-gpios = &lt;&amp;tlmm 114 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vdda-supply = &lt;&amp;vreg_l28a_0p925&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	vdda-phy-supply = &lt;&amp;vreg_l28a_0p925&gt;;</div><div class='add'>+	vdda-pll-supply = &lt;&amp;vreg_l12a_1p8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8994_gpios {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"NC",</div><div class='add'>+		"KEY_VOLP_N",</div><div class='add'>+		"NC",</div><div class='add'>+		"BL1_PWM",</div><div class='add'>+		"GPIO-F", /* BL0_PWM, LSEC pin 28 */</div><div class='add'>+		"BL1_EN",</div><div class='add'>+		"NC",</div><div class='add'>+		"WLAN_EN",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"DIVCLK1",</div><div class='add'>+		"DIVCLK2",</div><div class='add'>+		"DIVCLK3",</div><div class='add'>+		"DIVCLK4",</div><div class='add'>+		"BT_EN",</div><div class='add'>+		"PMIC_SLB",</div><div class='add'>+		"PMIC_BUA",</div><div class='add'>+		"USB_VBUS_DET";</div><div class='add'>+</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;ls_exp_gpio_f &amp;bt_en_gpios&gt;;</div><div class='add'>+</div><div class='add'>+	ls_exp_gpio_f: pm8994-gpio5-state {</div><div class='add'>+		pinconf {</div><div class='add'>+			pins = "gpio5";</div><div class='add'>+			function = PMIC_GPIO_FUNC_NORMAL;</div><div class='add'>+			output-low;</div><div class='add'>+			power-source = &lt;PM8994_GPIO_S4&gt;; /* 1.8V */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bt_en_gpios: bt-en-pios-state {</div><div class='add'>+		pinconf {</div><div class='add'>+			pins = "gpio19";</div><div class='add'>+			function = PMIC_GPIO_FUNC_NORMAL;</div><div class='add'>+			output-low;</div><div class='add'>+			power-source = &lt;PM8994_GPIO_S4&gt;; /* 1.8V */</div><div class='add'>+			qcom,drive-strength = &lt;PMIC_GPIO_STRENGTH_LOW&gt;;</div><div class='add'>+			bias-pull-down;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wlan_en_gpios: wlan-en-gpios-state {</div><div class='add'>+		pinconf {</div><div class='add'>+			pins = "gpio8";</div><div class='add'>+			function = PMIC_GPIO_FUNC_NORMAL;</div><div class='add'>+			output-low;</div><div class='add'>+			power-source = &lt;PM8994_GPIO_S4&gt;; /* 1.8V */</div><div class='add'>+			qcom,drive-strength = &lt;PMIC_GPIO_STRENGTH_LOW&gt;;</div><div class='add'>+			bias-pull-down;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	audio_mclk: clk-div1-state {</div><div class='add'>+		pinconf {</div><div class='add'>+			pins = "gpio15";</div><div class='add'>+			function = "func1";</div><div class='add'>+			power-source = &lt;PM8994_GPIO_S4&gt;; /* 1.8V */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	volume_up_gpio: pm8996-gpio2-state {</div><div class='add'>+		pinconf {</div><div class='add'>+			pins = "gpio2";</div><div class='add'>+			function = "normal";</div><div class='add'>+			input-enable;</div><div class='add'>+			drive-push-pull;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+			qcom,drive-strength = &lt;PMIC_GPIO_STRENGTH_NO&gt;;</div><div class='add'>+			power-source = &lt;PM8994_GPIO_S4&gt;; /* 1.8V */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	divclk4_pin_a: divclk4-state {</div><div class='add'>+		pinconf {</div><div class='add'>+			pins = "gpio18";</div><div class='add'>+			function = PMIC_GPIO_FUNC_FUNC2;</div><div class='add'>+</div><div class='add'>+			bias-disable;</div><div class='add'>+			power-source = &lt;PM8994_GPIO_S4&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb3_vbus_det_gpio: pm8996-gpio22-state {</div><div class='add'>+		pinconf {</div><div class='add'>+			pins = "gpio22";</div><div class='add'>+			function = PMIC_GPIO_FUNC_NORMAL;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-down;</div><div class='add'>+			qcom,drive-strength = &lt;PMIC_GPIO_STRENGTH_NO&gt;;</div><div class='add'>+			power-source = &lt;PM8994_GPIO_S4&gt;; /* 1.8V */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8994_mpps {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"VDDPX_BIAS",</div><div class='add'>+		"WIFI_LED",</div><div class='add'>+		"NC",</div><div class='add'>+		"BT_LED",</div><div class='add'>+		"PM_MPP05",</div><div class='add'>+		"PM_MPP06",</div><div class='add'>+		"PM_MPP07",</div><div class='add'>+		"NC";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8994_spmi_regulators {</div><div class='add'>+	qcom,saw-reg = &lt;&amp;saw3&gt;;</div><div class='add'>+	vdd_s11-supply = &lt;&amp;vph_pwr&gt;;</div><div class='add'>+</div><div class='add'>+	s9 {</div><div class='add'>+		qcom,saw-slave;</div><div class='add'>+	};</div><div class='add'>+	s10 {</div><div class='add'>+		qcom,saw-slave;</div><div class='add'>+	};</div><div class='add'>+	s11 {</div><div class='add'>+		qcom,saw-leader;</div><div class='add'>+		regulator-name = "VDD_APCC";</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-min-microvolt = &lt;980000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;980000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pmi8994_gpios {</div><div class='add'>+	gpio-line-names =</div><div class='add'>+		"NC",</div><div class='add'>+		"SPKR_AMP_EN1",</div><div class='add'>+		"SPKR_AMP_EN2",</div><div class='add'>+		"TP61",</div><div class='add'>+		"NC",</div><div class='add'>+		"USB2_VBUS_DET",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC",</div><div class='add'>+		"NC";</div><div class='add'>+</div><div class='add'>+	usb2_vbus_det_gpio: pmi8996-gpio6-state {</div><div class='add'>+		pinconf {</div><div class='add'>+			pins = "gpio6";</div><div class='add'>+			function = PMIC_GPIO_FUNC_NORMAL;</div><div class='add'>+			input-enable;</div><div class='add'>+			bias-pull-down;</div><div class='add'>+			qcom,drive-strength = &lt;PMIC_GPIO_STRENGTH_NO&gt;;</div><div class='add'>+			power-source = &lt;PM8994_GPIO_S4&gt;; /* 1.8V */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pmi8994_lpg {</div><div class='add'>+	qcom,power-source = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pmi8994_mpp2_userled4&gt;;</div><div class='add'>+</div><div class='add'>+	qcom,dtest = &lt;0 0&gt;,</div><div class='add'>+		     &lt;0 0&gt;,</div><div class='add'>+		     &lt;0 0&gt;,</div><div class='add'>+		     &lt;4 1&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	led@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+		function = LED_FUNCTION_HEARTBEAT;</div><div class='add'>+		function-enumerator = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		linux,default-trigger = "heartbeat";</div><div class='add'>+		default-state = "on";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	led@2 {</div><div class='add'>+		reg = &lt;2&gt;;</div><div class='add'>+		color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+		function = LED_FUNCTION_HEARTBEAT;</div><div class='add'>+		function-enumerator = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	led@3 {</div><div class='add'>+		reg = &lt;3&gt;;</div><div class='add'>+		color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+		function = LED_FUNCTION_HEARTBEAT;</div><div class='add'>+		function-enumerator = &lt;2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	led@4 {</div><div class='add'>+		reg = &lt;4&gt;;</div><div class='add'>+		color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+		function = LED_FUNCTION_HEARTBEAT;</div><div class='add'>+		function-enumerator = &lt;3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pmi8994_mpps {</div><div class='add'>+	pmi8994_mpp2_userled4: mpp2-userled4-state {</div><div class='add'>+		pins = "mpp2";</div><div class='add'>+		function = "sink";</div><div class='add'>+</div><div class='add'>+		output-low;</div><div class='add'>+		qcom,dtest = &lt;4&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pmi8994_spmi_regulators {</div><div class='add'>+	vdd_s2-supply = &lt;&amp;vph_pwr&gt;;</div><div class='add'>+</div><div class='add'>+	vdd_gfx: s2 {</div><div class='add'>+		regulator-name = "VDD_GFX";</div><div class='add'>+		regulator-min-microvolt = &lt;980000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;980000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;rpm_requests {</div><div class='add'>+	regulators-0 {</div><div class='add'>+		compatible = "qcom,rpm-pm8994-regulators";</div><div class='add'>+</div><div class='add'>+		vdd_s1-supply = &lt;&amp;vph_pwr&gt;;</div><div class='add'>+		vdd_s2-supply = &lt;&amp;vph_pwr&gt;;</div><div class='add'>+		vdd_s3-supply = &lt;&amp;vph_pwr&gt;;</div><div class='add'>+		vdd_s4-supply = &lt;&amp;vph_pwr&gt;;</div><div class='add'>+		vdd_s5-supply = &lt;&amp;vph_pwr&gt;;</div><div class='add'>+		vdd_s6-supply = &lt;&amp;vph_pwr&gt;;</div><div class='add'>+		vdd_s7-supply = &lt;&amp;vph_pwr&gt;;</div><div class='add'>+		vdd_s8-supply = &lt;&amp;vph_pwr&gt;;</div><div class='add'>+		vdd_s9-supply = &lt;&amp;vph_pwr&gt;;</div><div class='add'>+		vdd_s10-supply = &lt;&amp;vph_pwr&gt;;</div><div class='add'>+		vdd_s11-supply = &lt;&amp;vph_pwr&gt;;</div><div class='add'>+		vdd_s12-supply = &lt;&amp;vph_pwr&gt;;</div><div class='add'>+		vdd_l1-supply = &lt;&amp;vreg_s1b_1p025&gt;;</div><div class='add'>+		vdd_l2_l26_l28-supply = &lt;&amp;vreg_s3a_1p3&gt;;</div><div class='add'>+		vdd_l3_l11-supply = &lt;&amp;vreg_s3a_1p3&gt;;</div><div class='add'>+		vdd_l4_l27_l31-supply = &lt;&amp;vreg_s3a_1p3&gt;;</div><div class='add'>+		vdd_l5_l7-supply = &lt;&amp;vreg_s5a_2p15&gt;;</div><div class='add'>+		vdd_l6_l12_l32-supply = &lt;&amp;vreg_s5a_2p15&gt;;</div><div class='add'>+		vdd_l8_l16_l30-supply = &lt;&amp;vph_pwr&gt;;</div><div class='add'>+		vdd_l9_l10_l18_l22-supply = &lt;&amp;vph_pwr_bbyp&gt;;</div><div class='add'>+		vdd_l13_l19_l23_l24-supply = &lt;&amp;vph_pwr_bbyp&gt;;</div><div class='add'>+		vdd_l14_l15-supply = &lt;&amp;vreg_s5a_2p15&gt;;</div><div class='add'>+		vdd_l17_l29-supply = &lt;&amp;vph_pwr_bbyp&gt;;</div><div class='add'>+		vdd_l20_l21-supply = &lt;&amp;vph_pwr_bbyp&gt;;</div><div class='add'>+		vdd_l25-supply = &lt;&amp;vreg_s3a_1p3&gt;;</div><div class='add'>+		vdd_lvs1_2-supply = &lt;&amp;vreg_s4a_1p8&gt;;</div><div class='add'>+</div><div class='add'>+		vreg_s3a_1p3: s3 {</div><div class='add'>+			regulator-name = "vreg_s3a_1p3";</div><div class='add'>+			regulator-min-microvolt = &lt;1300000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/**</div><div class='add'>+		 * 1.8v required on LS expansion</div><div class='add'>+		 * for mezzanine boards</div><div class='add'>+		 */</div><div class='add'>+		vreg_s4a_1p8: s4 {</div><div class='add'>+			regulator-name = "vreg_s4a_1p8";</div><div class='add'>+			regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+			regulator-always-on;</div><div class='add'>+		};</div><div class='add'>+		vreg_s5a_2p15: s5 {</div><div class='add'>+			regulator-name = "vreg_s5a_2p15";</div><div class='add'>+			regulator-min-microvolt = &lt;2150000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;2150000&gt;;</div><div class='add'>+		};</div><div class='add'>+		vreg_s7a_1p0: s7 {</div><div class='add'>+			regulator-name = "vreg_s7a_1p0";</div><div class='add'>+			regulator-min-microvolt = &lt;800000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;800000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l1a_1p0: l1 {</div><div class='add'>+			regulator-name = "vreg_l1a_1p0";</div><div class='add'>+			regulator-min-microvolt = &lt;1000000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+		};</div><div class='add'>+		vreg_l2a_1p25: l2 {</div><div class='add'>+			regulator-name = "vreg_l2a_1p25";</div><div class='add'>+			regulator-min-microvolt = &lt;1250000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1250000&gt;;</div><div class='add'>+		};</div><div class='add'>+		vreg_l3a_0p875: l3 {</div><div class='add'>+			regulator-name = "vreg_l3a_0p875";</div><div class='add'>+			regulator-min-microvolt = &lt;850000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;850000&gt;;</div><div class='add'>+		};</div><div class='add'>+		vreg_l4a_1p225: l4 {</div><div class='add'>+			regulator-name = "vreg_l4a_1p225";</div><div class='add'>+			regulator-min-microvolt = &lt;1225000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1225000&gt;;</div><div class='add'>+		};</div><div class='add'>+		vreg_l6a_1p2: l6 {</div><div class='add'>+			regulator-name = "vreg_l6a_1p2";</div><div class='add'>+			regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+		};</div><div class='add'>+		vreg_l8a_1p8: l8 {</div><div class='add'>+			regulator-name = "vreg_l8a_1p8";</div><div class='add'>+			regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		};</div><div class='add'>+		vreg_l9a_1p8: l9 {</div><div class='add'>+			regulator-name = "vreg_l9a_1p8";</div><div class='add'>+			regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		};</div><div class='add'>+		vreg_l10a_1p8: l10 {</div><div class='add'>+			regulator-name = "vreg_l10a_1p8";</div><div class='add'>+			regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		};</div><div class='add'>+		vreg_l11a_1p15: l11 {</div><div class='add'>+			regulator-name = "vreg_l11a_1p15";</div><div class='add'>+			regulator-min-microvolt = &lt;1150000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1150000&gt;;</div><div class='add'>+		};</div><div class='add'>+		vreg_l12a_1p8: l12 {</div><div class='add'>+			regulator-name = "vreg_l12a_1p8";</div><div class='add'>+			regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		};</div><div class='add'>+		vreg_l13a_2p95: l13 {</div><div class='add'>+			regulator-name = "vreg_l13a_2p95";</div><div class='add'>+			regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;2950000&gt;;</div><div class='add'>+		};</div><div class='add'>+		vreg_l14a_1p8: l14 {</div><div class='add'>+			regulator-name = "vreg_l14a_1p8";</div><div class='add'>+			regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		};</div><div class='add'>+		vreg_l15a_1p8: l15 {</div><div class='add'>+			regulator-name = "vreg_l15a_1p8";</div><div class='add'>+			regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		};</div><div class='add'>+		vreg_l16a_2p7: l16 {</div><div class='add'>+			regulator-name = "vreg_l16a_2p7";</div><div class='add'>+			regulator-min-microvolt = &lt;2700000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;2700000&gt;;</div><div class='add'>+		};</div><div class='add'>+		vreg_l17a_2p8: l17 {</div><div class='add'>+			regulator-name = "vreg_l17a_2p8";</div><div class='add'>+			regulator-min-microvolt = &lt;2500000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;2500000&gt;;</div><div class='add'>+		};</div><div class='add'>+		vreg_l18a_2p85: l18 {</div><div class='add'>+			regulator-name = "vreg_l18a_2p85";</div><div class='add'>+			regulator-min-microvolt = &lt;2700000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;2900000&gt;;</div><div class='add'>+		};</div><div class='add'>+		vreg_l19a_2p8: l19 {</div><div class='add'>+			regulator-name = "vreg_l19a_2p8";</div><div class='add'>+			regulator-min-microvolt = &lt;3000000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;3000000&gt;;</div><div class='add'>+		};</div><div class='add'>+		vreg_l20a_2p95: l20 {</div><div class='add'>+			regulator-name = "vreg_l20a_2p95";</div><div class='add'>+			regulator-min-microvolt = &lt;2950000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;2950000&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+		};</div><div class='add'>+		vreg_l21a_2p95: l21 {</div><div class='add'>+			regulator-name = "vreg_l21a_2p95";</div><div class='add'>+			regulator-min-microvolt = &lt;2950000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;2950000&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+			regulator-system-load = &lt;200000&gt;;</div><div class='add'>+		};</div><div class='add'>+		vreg_l22a_3p0: l22 {</div><div class='add'>+			regulator-name = "vreg_l22a_3p0";</div><div class='add'>+			regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		};</div><div class='add'>+		vreg_l23a_2p8: l23 {</div><div class='add'>+			regulator-name = "vreg_l23a_2p8";</div><div class='add'>+			regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+		};</div><div class='add'>+		vreg_l24a_3p075: l24 {</div><div class='add'>+			regulator-name = "vreg_l24a_3p075";</div><div class='add'>+			regulator-min-microvolt = &lt;3075000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;3075000&gt;;</div><div class='add'>+		};</div><div class='add'>+		vreg_l25a_1p2: l25 {</div><div class='add'>+			regulator-name = "vreg_l25a_1p2";</div><div class='add'>+			regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+		};</div><div class='add'>+		vreg_l26a_0p8: l27 {</div><div class='add'>+			regulator-name = "vreg_l26a_0p8";</div><div class='add'>+			regulator-min-microvolt = &lt;1000000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+		};</div><div class='add'>+		vreg_l28a_0p925: l28 {</div><div class='add'>+			regulator-name = "vreg_l28a_0p925";</div><div class='add'>+			regulator-min-microvolt = &lt;925000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;925000&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+		};</div><div class='add'>+		vreg_l29a_2p8: l29 {</div><div class='add'>+			regulator-name = "vreg_l29a_2p8";</div><div class='add'>+			regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+		};</div><div class='add'>+		vreg_l30a_1p8: l30 {</div><div class='add'>+			regulator-name = "vreg_l30a_1p8";</div><div class='add'>+			regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		};</div><div class='add'>+		vreg_l32a_1p8: l32 {</div><div class='add'>+			regulator-name = "vreg_l32a_1p8";</div><div class='add'>+			regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_lvs1a_1p8: lvs1 {</div><div class='add'>+			regulator-name = "vreg_lvs1a_1p8";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_lvs2a_1p8: lvs2 {</div><div class='add'>+			regulator-name = "vreg_lvs2a_1p8";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	regulators-1 {</div><div class='add'>+		compatible = "qcom,rpm-pmi8994-regulators";</div><div class='add'>+</div><div class='add'>+		vdd_s1-supply = &lt;&amp;vph_pwr&gt;;</div><div class='add'>+		vdd_s2-supply = &lt;&amp;vph_pwr&gt;;</div><div class='add'>+		vdd_s3-supply = &lt;&amp;vph_pwr&gt;;</div><div class='add'>+		vdd_bst_byp-supply = &lt;&amp;vph_pwr&gt;;</div><div class='add'>+</div><div class='add'>+		vph_pwr_bbyp: boost-bypass {</div><div class='add'>+			regulator-name = "vph_pwr_bbyp";</div><div class='add'>+			regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_s1b_1p025: s1 {</div><div class='add'>+			regulator-name = "vreg_s1b_1p025";</div><div class='add'>+			regulator-min-microvolt = &lt;1025000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1025000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sdhc2 {</div><div class='add'>+	/* External SD card */</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdc2_state_on &amp;sdc2_cd_on&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;sdc2_state_off &amp;sdc2_cd_off&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;tlmm 38 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vmmc-supply = &lt;&amp;vreg_l21a_2p95&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;vreg_l13a_2p95&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;q6asmdai {</div><div class='add'>+	dai@0 {</div><div class='add'>+		reg = &lt;MSM_FRONTEND_DAI_MULTIMEDIA1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dai@1 {</div><div class='add'>+		reg = &lt;MSM_FRONTEND_DAI_MULTIMEDIA2&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dai@2 {</div><div class='add'>+		reg = &lt;MSM_FRONTEND_DAI_MULTIMEDIA3&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;slim_msm {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	slim@1 {</div><div class='add'>+		reg = &lt;1&gt;;</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		tasha_ifd: tas-ifd@0,0 {</div><div class='add'>+			compatible = "slim217,1a0";</div><div class='add'>+			reg = &lt;0 0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wcd9335: codec@1,0 {</div><div class='add'>+			compatible = "slim217,1a0";</div><div class='add'>+			reg = &lt;1 0&gt;;</div><div class='add'>+</div><div class='add'>+			clock-names = "mclk", "slimbus";</div><div class='add'>+			clocks = &lt;&amp;div1_mclk&gt;,</div><div class='add'>+				 &lt;&amp;rpmcc RPM_SMD_BB_CLK1&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;tlmm&gt;;</div><div class='add'>+			interrupts = &lt;54 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;53 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "intr1", "intr2";</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			pinctrl-0 = &lt;&amp;cdc_reset_active &amp;wcd_intr_default&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+			reset-gpios = &lt;&amp;tlmm 64 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			slim-ifc-dev = &lt;&amp;tasha_ifd&gt;;</div><div class='add'>+</div><div class='add'>+			#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			vdd-buck-supply = &lt;&amp;vreg_s4a_1p8&gt;;</div><div class='add'>+			vdd-buck-sido-supply = &lt;&amp;vreg_s4a_1p8&gt;;</div><div class='add'>+			vdd-tx-supply = &lt;&amp;vreg_s4a_1p8&gt;;</div><div class='add'>+			vdd-rx-supply = &lt;&amp;vreg_s4a_1p8&gt;;</div><div class='add'>+			vdd-io-supply = &lt;&amp;vreg_s4a_1p8&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sound {</div><div class='add'>+	compatible = "qcom,apq8096-sndcard";</div><div class='add'>+	model = "DB820c";</div><div class='add'>+	audio-routing = "RX_BIAS", "MCLK";</div><div class='add'>+</div><div class='add'>+	mm1-dai-link {</div><div class='add'>+		link-name = "MultiMedia1";</div><div class='add'>+		cpu {</div><div class='add'>+			sound-dai = &lt;&amp;q6asmdai  MSM_FRONTEND_DAI_MULTIMEDIA1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mm2-dai-link {</div><div class='add'>+		link-name = "MultiMedia2";</div><div class='add'>+		cpu {</div><div class='add'>+			sound-dai = &lt;&amp;q6asmdai  MSM_FRONTEND_DAI_MULTIMEDIA2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mm3-dai-link {</div><div class='add'>+		link-name = "MultiMedia3";</div><div class='add'>+		cpu {</div><div class='add'>+			sound-dai = &lt;&amp;q6asmdai  MSM_FRONTEND_DAI_MULTIMEDIA3&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdmi-dai-link {</div><div class='add'>+		link-name = "HDMI";</div><div class='add'>+		cpu {</div><div class='add'>+			sound-dai = &lt;&amp;q6afedai HDMI_RX&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		platform {</div><div class='add'>+			sound-dai = &lt;&amp;q6routing&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		codec {</div><div class='add'>+			sound-dai = &lt;&amp;mdss_hdmi 0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	slim-dai-link {</div><div class='add'>+		link-name = "SLIM Playback";</div><div class='add'>+		cpu {</div><div class='add'>+			sound-dai = &lt;&amp;q6afedai SLIMBUS_6_RX&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		platform {</div><div class='add'>+			sound-dai = &lt;&amp;q6routing&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		codec {</div><div class='add'>+			sound-dai = &lt;&amp;wcd9335 AIF4_PB&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	slimcap-dai-link {</div><div class='add'>+		link-name = "SLIM Capture";</div><div class='add'>+		cpu {</div><div class='add'>+			sound-dai = &lt;&amp;q6afedai SLIMBUS_0_TX&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		platform {</div><div class='add'>+			sound-dai = &lt;&amp;q6routing&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		codec {</div><div class='add'>+			sound-dai = &lt;&amp;wcd9335 AIF1_CAP&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ufsphy {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	vdda-phy-supply = &lt;&amp;vreg_l28a_0p925&gt;;</div><div class='add'>+	vdda-pll-supply = &lt;&amp;vreg_l12a_1p8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ufshc {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	vcc-supply = &lt;&amp;vreg_l20a_2p95&gt;;</div><div class='add'>+	vccq-supply = &lt;&amp;vreg_l25a_1p2&gt;;</div><div class='add'>+	vccq2-supply = &lt;&amp;vreg_s4a_1p8&gt;;</div><div class='add'>+	vdd-hba-supply = &lt;&amp;vreg_l25a_1p2&gt;;</div><div class='add'>+</div><div class='add'>+	vcc-max-microamp = &lt;600000&gt;;</div><div class='add'>+	vccq-max-microamp = &lt;450000&gt;;</div><div class='add'>+	vccq2-max-microamp = &lt;450000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	extcon = &lt;&amp;usb2_id&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb2_dwc3 {</div><div class='add'>+	extcon = &lt;&amp;usb2_id&gt;;</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	maximum-speed = "high-speed";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	extcon = &lt;&amp;usb3_id&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3_dwc3 {</div><div class='add'>+	extcon = &lt;&amp;usb3_id&gt;;</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	vdda-phy-supply = &lt;&amp;vreg_l28a_0p925&gt;;</div><div class='add'>+	vdda-pll-supply = &lt;&amp;vreg_l12a_1p8&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;venus {</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi<br/>deleted file mode 100644<br/>index af87350b5547..000000000000<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi</a><br/>+++ /dev/null</div><div class='hunk'>@@ -1,1056 +0,0 @@</div><div class='del'>-// SPDX-License-Identifier: GPL-2.0-only</div><div class='del'>-/*</div><div class='del'>- * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.</div><div class='del'>- */</div><div class='del'>-</div><div class='del'>-#include "msm8996.dtsi"</div><div class='del'>-#include "pm8994.dtsi"</div><div class='del'>-#include "pmi8994.dtsi"</div><div class='del'>-#include &lt;dt-bindings/input/input.h&gt;</div><div class='del'>-#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='del'>-#include &lt;dt-bindings/pinctrl/qcom,pmic-gpio.h&gt;</div><div class='del'>-#include &lt;dt-bindings/sound/qcom,q6afe.h&gt;</div><div class='del'>-#include &lt;dt-bindings/sound/qcom,q6asm.h&gt;</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * GPIO name legend: proper name = the GPIO line is used as GPIO</div><div class='del'>- *         NC      = not connected (pin out but not routed from the chip to</div><div class='del'>- *                   anything the board)</div><div class='del'>- *         "[PER]" = pin is muxed for [peripheral] (not GPIO)</div><div class='del'>- *         LSEC    = Low Speed External Connector</div><div class='del'>- *         P HSEC  = Primary High Speed External Connector</div><div class='del'>- *         S HSEC  = Secondary High Speed External Connector</div><div class='del'>- *         J14     = Camera Connector</div><div class='del'>- *         TP      = Test Points</div><div class='del'>- *</div><div class='del'>- * Line names are taken from the schematic "DragonBoard 820c",</div><div class='del'>- * drawing no: LM25-P2751-1</div><div class='del'>- *</div><div class='del'>- * For the lines routed to the external connectors the</div><div class='del'>- * lines are named after the 96Boards CE Specification 1.0,</div><div class='del'>- * Appendix "Expansion Connector Signal Description".</div><div class='del'>- *</div><div class='del'>- * When the 96Board naming of a line and the schematic name of</div><div class='del'>- * the same line are in conflict, the 96Board specification</div><div class='del'>- * takes precedence, which means that the external UART on the</div><div class='del'>- * LSEC is named UART0 while the schematic and SoC names this</div><div class='del'>- * UART3. This is only for the informational lines i.e. "[FOO]",</div><div class='del'>- * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only</div><div class='del'>- * ones actually used for GPIO.</div><div class='del'>- */</div><div class='del'>-</div><div class='del'>-/ {</div><div class='del'>-	aliases {</div><div class='del'>-		serial0 = &amp;blsp2_uart1;</div><div class='del'>-		serial1 = &amp;blsp2_uart2;</div><div class='del'>-		serial2 = &amp;blsp1_uart1;</div><div class='del'>-		i2c0	= &amp;blsp1_i2c2;</div><div class='del'>-		i2c1	= &amp;blsp2_i2c1;</div><div class='del'>-		i2c2	= &amp;blsp2_i2c0;</div><div class='del'>-		spi0	= &amp;blsp1_spi0;</div><div class='del'>-		spi1	= &amp;blsp2_spi5;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	chosen {</div><div class='del'>-		stdout-path = "serial0:115200n8";</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	clocks {</div><div class='del'>-		compatible = "simple-bus";</div><div class='del'>-		divclk4: divclk4 {</div><div class='del'>-			compatible = "fixed-clock";</div><div class='del'>-			#clock-cells = &lt;0&gt;;</div><div class='del'>-			clock-frequency = &lt;32768&gt;;</div><div class='del'>-			clock-output-names = "divclk4";</div><div class='del'>-</div><div class='del'>-			pinctrl-names = "default";</div><div class='del'>-			pinctrl-0 = &lt;&amp;divclk4_pin_a&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		div1_mclk: divclk1 {</div><div class='del'>-			compatible = "gpio-gate-clock";</div><div class='del'>-			pinctrl-0 = &lt;&amp;audio_mclk&gt;;</div><div class='del'>-			pinctrl-names = "default";</div><div class='del'>-			clocks = &lt;&amp;rpmcc RPM_SMD_DIV_CLK1&gt;;</div><div class='del'>-			#clock-cells = &lt;0&gt;;</div><div class='del'>-			enable-gpios = &lt;&amp;pm8994_gpios 15 0&gt;;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	gpio_keys {</div><div class='del'>-		compatible = "gpio-keys";</div><div class='del'>-		#address-cells = &lt;1&gt;;</div><div class='del'>-		#size-cells = &lt;0&gt;;</div><div class='del'>-		autorepeat;</div><div class='del'>-</div><div class='del'>-		pinctrl-names = "default";</div><div class='del'>-		pinctrl-0 = &lt;&amp;volume_up_gpio&gt;;</div><div class='del'>-</div><div class='del'>-		button@0 {</div><div class='del'>-			label = "Volume Up";</div><div class='del'>-			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='del'>-			gpios = &lt;&amp;pm8994_gpios 2 GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	usb2_id: usb2-id {</div><div class='del'>-		compatible = "linux,extcon-usb-gpio";</div><div class='del'>-		id-gpio = &lt;&amp;pmi8994_gpios 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-		pinctrl-names = "default";</div><div class='del'>-		pinctrl-0 = &lt;&amp;usb2_vbus_det_gpio&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	usb3_id: usb3-id {</div><div class='del'>-		compatible = "linux,extcon-usb-gpio";</div><div class='del'>-		id-gpio = &lt;&amp;pm8994_gpios 22 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-		pinctrl-names = "default";</div><div class='del'>-		pinctrl-0 = &lt;&amp;usb3_vbus_det_gpio&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	vph_pwr: vph-pwr-regulator {</div><div class='del'>-		compatible = "regulator-fixed";</div><div class='del'>-		regulator-name = "vph_pwr";</div><div class='del'>-		regulator-always-on;</div><div class='del'>-		regulator-boot-on;</div><div class='del'>-</div><div class='del'>-		regulator-min-microvolt = &lt;3700000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;3700000&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	vreg_s8a_l3a_input: vreg-s8a-l3a-input {</div><div class='del'>-		compatible = "regulator-fixed";</div><div class='del'>-		regulator-name = "vreg_s8a_l3a_input";</div><div class='del'>-		regulator-always-on;</div><div class='del'>-		regulator-boot-on;</div><div class='del'>-</div><div class='del'>-		regulator-min-microvolt = &lt;0&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;0&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	wlan_en: wlan-en-1-8v {</div><div class='del'>-		pinctrl-names = "default";</div><div class='del'>-		pinctrl-0 = &lt;&amp;wlan_en_gpios&gt;;</div><div class='del'>-		compatible = "regulator-fixed";</div><div class='del'>-		regulator-name = "wlan-en-regulator";</div><div class='del'>-		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='del'>-</div><div class='del'>-		gpio = &lt;&amp;pm8994_gpios 8 0&gt;;</div><div class='del'>-</div><div class='del'>-		/* WLAN card specific delay */</div><div class='del'>-		startup-delay-us = &lt;70000&gt;;</div><div class='del'>-		enable-active-high;</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;blsp1_i2c2 {</div><div class='del'>-	/* On Low speed expansion */</div><div class='del'>-	label = "LS-I2C0";</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;blsp1_spi0 {</div><div class='del'>-	/* On Low speed expansion */</div><div class='del'>-	label = "LS-SPI0";</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;blsp1_uart1 {</div><div class='del'>-	label = "BT-UART";</div><div class='del'>-	status = "okay";</div><div class='del'>-	pinctrl-names = "default", "sleep";</div><div class='del'>-	pinctrl-0 = &lt;&amp;blsp1_uart1_default&gt;;</div><div class='del'>-	pinctrl-1 = &lt;&amp;blsp1_uart1_sleep&gt;;</div><div class='del'>-</div><div class='del'>-	bluetooth {</div><div class='del'>-		compatible = "qcom,qca6174-bt";</div><div class='del'>-</div><div class='del'>-		/* bt_disable_n gpio */</div><div class='del'>-		enable-gpios = &lt;&amp;pm8994_gpios 19 GPIO_ACTIVE_HIGH&gt;;</div><div class='del'>-</div><div class='del'>-		clocks = &lt;&amp;divclk4&gt;;</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;blsp2_i2c0 {</div><div class='del'>-	/* On High speed expansion */</div><div class='del'>-	label = "HS-I2C2";</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;blsp2_i2c1 {</div><div class='del'>-	/* On Low speed expansion */</div><div class='del'>-	label = "LS-I2C1";</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;blsp2_spi5 {</div><div class='del'>-	/* On High speed expansion */</div><div class='del'>-	label = "HS-SPI1";</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;blsp2_uart1 {</div><div class='del'>-	label = "LS-UART1";</div><div class='del'>-	status = "okay";</div><div class='del'>-	pinctrl-names = "default", "sleep";</div><div class='del'>-	pinctrl-0 = &lt;&amp;blsp2_uart1_2pins_default&gt;;</div><div class='del'>-	pinctrl-1 = &lt;&amp;blsp2_uart1_2pins_sleep&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;blsp2_uart2 {</div><div class='del'>-	label = "LS-UART0";</div><div class='del'>-	status = "disabled";</div><div class='del'>-	pinctrl-names = "default", "sleep";</div><div class='del'>-	pinctrl-0 = &lt;&amp;blsp2_uart2_4pins_default&gt;;</div><div class='del'>-	pinctrl-1 = &lt;&amp;blsp2_uart2_4pins_sleep&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;camss {</div><div class='del'>-	vdda-supply = &lt;&amp;vreg_l2a_1p25&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;hdmi {</div><div class='del'>-	status = "okay";</div><div class='del'>-</div><div class='del'>-	pinctrl-names = "default", "sleep";</div><div class='del'>-	pinctrl-0 = &lt;&amp;hdmi_hpd_active &amp;hdmi_ddc_active&gt;;</div><div class='del'>-	pinctrl-1 = &lt;&amp;hdmi_hpd_suspend &amp;hdmi_ddc_suspend&gt;;</div><div class='del'>-</div><div class='del'>-	core-vdda-supply = &lt;&amp;vreg_l12a_1p8&gt;;</div><div class='del'>-	core-vcc-supply = &lt;&amp;vreg_s4a_1p8&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;hdmi_phy {</div><div class='del'>-	status = "okay";</div><div class='del'>-</div><div class='del'>-	vddio-supply = &lt;&amp;vreg_l12a_1p8&gt;;</div><div class='del'>-	vcca-supply = &lt;&amp;vreg_l28a_0p925&gt;;</div><div class='del'>-	#phy-cells = &lt;0&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;hsusb_phy1 {</div><div class='del'>-	status = "okay";</div><div class='del'>-</div><div class='del'>-	vdda-pll-supply = &lt;&amp;vreg_l12a_1p8&gt;;</div><div class='del'>-	vdda-phy-dpdm-supply = &lt;&amp;vreg_l24a_3p075&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;hsusb_phy2 {</div><div class='del'>-	status = "okay";</div><div class='del'>-</div><div class='del'>-	vdda-pll-supply = &lt;&amp;vreg_l12a_1p8&gt;;</div><div class='del'>-	vdda-phy-dpdm-supply = &lt;&amp;vreg_l24a_3p075&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;mdp {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;mdss {</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;msmgpio {</div><div class='del'>-	gpio-line-names =</div><div class='del'>-		"[SPI0_DOUT]", /* GPIO_0, BLSP1_SPI_MOSI, LSEC pin 14 */</div><div class='del'>-		"[SPI0_DIN]", /* GPIO_1, BLSP1_SPI_MISO, LSEC pin 10 */</div><div class='del'>-		"[SPI0_CS]", /* GPIO_2, BLSP1_SPI_CS_N, LSEC pin 12 */</div><div class='del'>-		"[SPI0_SCLK]", /* GPIO_3, BLSP1_SPI_CLK, LSEC pin 8 */</div><div class='del'>-		"[UART1_TxD]", /* GPIO_4, BLSP8_UART_TX, LSEC pin 11 */</div><div class='del'>-		"[UART1_RxD]", /* GPIO_5, BLSP8_UART_RX, LSEC pin 13 */</div><div class='del'>-		"[I2C1_SDA]", /* GPIO_6, BLSP8_I2C_SDA, LSEC pin 21 */</div><div class='del'>-		"[I2C1_SCL]", /* GPIO_7, BLSP8_I2C_SCL, LSEC pin 19 */</div><div class='del'>-		"GPIO-H", /* GPIO_8, LCD0_RESET_N, LSEC pin 30 */</div><div class='del'>-		"TP93", /* GPIO_9 */</div><div class='del'>-		"GPIO-G", /* GPIO_10, MDP_VSYNC_P, LSEC pin 29 */</div><div class='del'>-		"[MDP_VSYNC_S]", /* GPIO_11, S HSEC pin 55 */</div><div class='del'>-		"NC", /* GPIO_12 */</div><div class='del'>-		"[CSI0_MCLK]", /* GPIO_13, CAM_MCLK0, P HSEC pin 15 */</div><div class='del'>-		"[CAM_MCLK1]", /* GPIO_14, J14 pin 11 */</div><div class='del'>-		"[CSI1_MCLK]", /* GPIO_15, CAM_MCLK2, P HSEC pin 17 */</div><div class='del'>-		"TP99", /* GPIO_16 */</div><div class='del'>-		"[I2C2_SDA]", /* GPIO_17, CCI_I2C_SDA0, P HSEC pin 34 */</div><div class='del'>-		"[I2C2_SCL]", /* GPIO_18, CCI_I2C_SCL0, P HSEC pin 32 */</div><div class='del'>-		"[CCI_I2C_SDA1]", /* GPIO_19, S HSEC pin 38 */</div><div class='del'>-		"[CCI_I2C_SCL1]", /* GPIO_20, S HSEC pin 36 */</div><div class='del'>-		"FLASH_STROBE_EN", /* GPIO_21, S HSEC pin 5 */</div><div class='del'>-		"FLASH_STROBE_TRIG", /* GPIO_22, S HSEC pin 1 */</div><div class='del'>-		"GPIO-K", /* GPIO_23, CAM2_RST_N, LSEC pin 33 */</div><div class='del'>-		"GPIO-D", /* GPIO_24, LSEC pin 26 */</div><div class='del'>-		"GPIO-I", /* GPIO_25, CAM0_RST_N, LSEC pin 31 */</div><div class='del'>-		"GPIO-J", /* GPIO_26, CAM0_STANDBY_N, LSEC pin 32 */</div><div class='del'>-		"BLSP6_I2C_SDA", /* GPIO_27 */</div><div class='del'>-		"BLSP6_I2C_SCL", /* GPIO_28 */</div><div class='del'>-		"GPIO-B", /* GPIO_29, TS0_RESET_N, LSEC pin 24 */</div><div class='del'>-		"GPIO30", /* GPIO_30, S HSEC pin 4 */</div><div class='del'>-		"HDMI_CEC", /* GPIO_31 */</div><div class='del'>-		"HDMI_DDC_CLOCK", /* GPIO_32 */</div><div class='del'>-		"HDMI_DDC_DATA", /* GPIO_33 */</div><div class='del'>-		"HDMI_HOT_PLUG_DETECT", /* GPIO_34 */</div><div class='del'>-		"PCIE0_RST_N", /* GPIO_35 */</div><div class='del'>-		"PCIE0_CLKREQ_N", /* GPIO_36 */</div><div class='del'>-		"PCIE0_WAKE", /* GPIO_37 */</div><div class='del'>-		"SD_CARD_DET_N", /* GPIO_38 */</div><div class='del'>-		"TSIF1_SYNC", /* GPIO_39, S HSEC pin 48 */</div><div class='del'>-		"W_DISABLE_N", /* GPIO_40 */</div><div class='del'>-		"[BLSP9_UART_TX]", /* GPIO_41 */</div><div class='del'>-		"[BLSP9_UART_RX]", /* GPIO_42 */</div><div class='del'>-		"[BLSP2_UART_CTS_N]", /* GPIO_43 */</div><div class='del'>-		"[BLSP2_UART_RFR_N]", /* GPIO_44 */</div><div class='del'>-		"[BLSP3_UART_TX]", /* GPIO_45 */</div><div class='del'>-		"[BLSP3_UART_RX]", /* GPIO_46 */</div><div class='del'>-		"[I2C0_SDA]", /* GPIO_47, LS_I2C0_SDA, LSEC pin 17 */</div><div class='del'>-		"[I2C0_SCL]", /* GPIO_48, LS_I2C0_SCL, LSEC pin 15 */</div><div class='del'>-		"[UART0_TxD]", /* GPIO_49, BLSP9_UART_TX, LSEC pin 5 */</div><div class='del'>-		"[UART0_RxD]", /* GPIO_50, BLSP9_UART_RX, LSEC pin 7 */</div><div class='del'>-		"[UART0_CTS]", /* GPIO_51, BLSP9_UART_CTS_N, LSEC pin 3 */</div><div class='del'>-		"[UART0_RTS]", /* GPIO_52, BLSP9_UART_RFR_N, LSEC pin 9 */</div><div class='del'>-		"[CODEC_INT1_N]", /* GPIO_53 */</div><div class='del'>-		"[CODEC_INT2_N]", /* GPIO_54 */</div><div class='del'>-		"[BLSP7_I2C_SDA]", /* GPIO_55 */</div><div class='del'>-		"[BLSP7_I2C_SCL]", /* GPIO_56 */</div><div class='del'>-		"MI2S_MCLK", /* GPIO_57, S HSEC pin 3 */</div><div class='del'>-		"[PCM_CLK]", /* GPIO_58, QUA_MI2S_SCK, LSEC pin 18 */</div><div class='del'>-		"[PCM_FS]", /* GPIO_59, QUA_MI2S_WS, LSEC pin 16 */</div><div class='del'>-		"[PCM_DO]", /* GPIO_60, QUA_MI2S_DATA0, LSEC pin 20 */</div><div class='del'>-		"[PCM_DI]", /* GPIO_61, QUA_MI2S_DATA1, LSEC pin 22 */</div><div class='del'>-		"GPIO-E", /* GPIO_62, LSEC pin 27 */</div><div class='del'>-		"TP87", /* GPIO_63 */</div><div class='del'>-		"[CODEC_RST_N]", /* GPIO_64 */</div><div class='del'>-		"[PCM1_CLK]", /* GPIO_65 */</div><div class='del'>-		"[PCM1_SYNC]", /* GPIO_66 */</div><div class='del'>-		"[PCM1_DIN]", /* GPIO_67 */</div><div class='del'>-		"[PCM1_DOUT]", /* GPIO_68 */</div><div class='del'>-		"AUDIO_REF_CLK", /* GPIO_69 */</div><div class='del'>-		"SLIMBUS_CLK", /* GPIO_70 */</div><div class='del'>-		"SLIMBUS_DATA0", /* GPIO_71 */</div><div class='del'>-		"SLIMBUS_DATA1", /* GPIO_72 */</div><div class='del'>-		"NC", /* GPIO_73 */</div><div class='del'>-		"NC", /* GPIO_74 */</div><div class='del'>-		"NC", /* GPIO_75 */</div><div class='del'>-		"NC", /* GPIO_76 */</div><div class='del'>-		"TP94", /* GPIO_77 */</div><div class='del'>-		"NC", /* GPIO_78 */</div><div class='del'>-		"TP95", /* GPIO_79 */</div><div class='del'>-		"GPIO-A", /* GPIO_80, MEMS_RESET_N, LSEC pin 23 */</div><div class='del'>-		"TP88", /* GPIO_81 */</div><div class='del'>-		"TP89", /* GPIO_82 */</div><div class='del'>-		"TP90", /* GPIO_83 */</div><div class='del'>-		"TP91", /* GPIO_84 */</div><div class='del'>-		"[SD_DAT0]", /* GPIO_85, BLSP12_SPI_MOSI, P HSEC pin 1 */</div><div class='del'>-		"[SD_CMD]", /* GPIO_86, BLSP12_SPI_MISO, P HSEC pin 11 */</div><div class='del'>-		"[SD_DAT3]", /* GPIO_87, BLSP12_SPI_CS_N, P HSEC pin 7 */</div><div class='del'>-		"[SD_SCLK]", /* GPIO_88, BLSP12_SPI_CLK, P HSEC pin 9 */</div><div class='del'>-		"TSIF1_CLK", /* GPIO_89, S HSEC pin 42 */</div><div class='del'>-		"TSIF1_EN", /* GPIO_90, S HSEC pin 46 */</div><div class='del'>-		"TSIF1_DATA", /* GPIO_91, S HSEC pin 44 */</div><div class='del'>-		"NC", /* GPIO_92 */</div><div class='del'>-		"TSIF2_CLK", /* GPIO_93, S HSEC pin 52 */</div><div class='del'>-		"TSIF2_EN", /* GPIO_94, S HSEC pin 56 */</div><div class='del'>-		"TSIF2_DATA", /* GPIO_95, S HSEC pin 54 */</div><div class='del'>-		"TSIF2_SYNC", /* GPIO_96, S HSEC pin 58 */</div><div class='del'>-		"NC", /* GPIO_97 */</div><div class='del'>-		"CAM1_STANDBY_N", /* GPIO_98 */</div><div class='del'>-		"NC", /* GPIO_99 */</div><div class='del'>-		"NC", /* GPIO_100 */</div><div class='del'>-		"[LCD1_RESET_N]", /* GPIO_101, S HSEC pin 51 */</div><div class='del'>-		"BOOT_CONFIG1", /* GPIO_102 */</div><div class='del'>-		"USB_HUB_RESET", /* GPIO_103 */</div><div class='del'>-		"CAM1_RST_N", /* GPIO_104 */</div><div class='del'>-		"NC", /* GPIO_105 */</div><div class='del'>-		"NC", /* GPIO_106 */</div><div class='del'>-		"NC", /* GPIO_107 */</div><div class='del'>-		"NC", /* GPIO_108 */</div><div class='del'>-		"NC", /* GPIO_109 */</div><div class='del'>-		"NC", /* GPIO_110 */</div><div class='del'>-		"NC", /* GPIO_111 */</div><div class='del'>-		"NC", /* GPIO_112 */</div><div class='del'>-		"PMI8994_BUA", /* GPIO_113 */</div><div class='del'>-		"PCIE2_RST_N", /* GPIO_114 */</div><div class='del'>-		"PCIE2_CLKREQ_N", /* GPIO_115 */</div><div class='del'>-		"PCIE2_WAKE", /* GPIO_116 */</div><div class='del'>-		"SSC_IRQ_0", /* GPIO_117 */</div><div class='del'>-		"SSC_IRQ_1", /* GPIO_118 */</div><div class='del'>-		"SSC_IRQ_2", /* GPIO_119 */</div><div class='del'>-		"NC", /* GPIO_120 */</div><div class='del'>-		"GPIO121", /* GPIO_121, S HSEC pin 2 */</div><div class='del'>-		"NC", /* GPIO_122 */</div><div class='del'>-		"SSC_IRQ_6", /* GPIO_123 */</div><div class='del'>-		"SSC_IRQ_7", /* GPIO_124 */</div><div class='del'>-		"GPIO-C", /* GPIO_125, TS_INT0, LSEC pin 25 */</div><div class='del'>-		"BOOT_CONFIG5", /* GPIO_126 */</div><div class='del'>-		"NC", /* GPIO_127 */</div><div class='del'>-		"NC", /* GPIO_128 */</div><div class='del'>-		"BOOT_CONFIG7", /* GPIO_129 */</div><div class='del'>-		"PCIE1_RST_N", /* GPIO_130 */</div><div class='del'>-		"PCIE1_CLKREQ_N", /* GPIO_131 */</div><div class='del'>-		"PCIE1_WAKE", /* GPIO_132 */</div><div class='del'>-		"GPIO-L", /* GPIO_133, CAM2_STANDBY_N, LSEC pin 34 */</div><div class='del'>-		"NC", /* GPIO_134 */</div><div class='del'>-		"NC", /* GPIO_135 */</div><div class='del'>-		"BOOT_CONFIG8", /* GPIO_136 */</div><div class='del'>-		"NC", /* GPIO_137 */</div><div class='del'>-		"NC", /* GPIO_138 */</div><div class='del'>-		"GPS_SSBI2", /* GPIO_139 */</div><div class='del'>-		"GPS_SSBI1", /* GPIO_140 */</div><div class='del'>-		"NC", /* GPIO_141 */</div><div class='del'>-		"NC", /* GPIO_142 */</div><div class='del'>-		"NC", /* GPIO_143 */</div><div class='del'>-		"BOOT_CONFIG6", /* GPIO_144 */</div><div class='del'>-		"NC", /* GPIO_145 */</div><div class='del'>-		"NC", /* GPIO_146 */</div><div class='del'>-		"NC", /* GPIO_147 */</div><div class='del'>-		"NC", /* GPIO_148 */</div><div class='del'>-		"NC"; /* GPIO_149 */</div><div class='del'>-</div><div class='del'>-	sdc2_cd_on: sdc2_cd_on {</div><div class='del'>-		mux {</div><div class='del'>-			pins = "gpio38";</div><div class='del'>-			function = "gpio";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		config {</div><div class='del'>-			pins = "gpio38";</div><div class='del'>-			bias-pull-up;		/* pull up */</div><div class='del'>-			drive-strength = &lt;16&gt;;	/* 16 MA */</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	sdc2_cd_off: sdc2_cd_off {</div><div class='del'>-		mux {</div><div class='del'>-			pins = "gpio38";</div><div class='del'>-			function = "gpio";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		config {</div><div class='del'>-			pins = "gpio38";</div><div class='del'>-			bias-pull-up;		/* pull up */</div><div class='del'>-			drive-strength = &lt;2&gt;;	/* 2 MA */</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	blsp1_uart1_default: blsp1_uart1_default {</div><div class='del'>-		mux {</div><div class='del'>-			pins = "gpio41", "gpio42", "gpio43", "gpio44";</div><div class='del'>-			function = "blsp_uart2";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		config {</div><div class='del'>-			pins = "gpio41", "gpio42", "gpio43", "gpio44";</div><div class='del'>-			drive-strength = &lt;16&gt;;</div><div class='del'>-			bias-disable;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	blsp1_uart1_sleep: blsp1_uart1_sleep {</div><div class='del'>-		mux {</div><div class='del'>-			pins = "gpio41", "gpio42", "gpio43", "gpio44";</div><div class='del'>-			function = "gpio";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		config {</div><div class='del'>-			pins = "gpio41", "gpio42", "gpio43", "gpio44";</div><div class='del'>-			drive-strength = &lt;2&gt;;</div><div class='del'>-			bias-disable;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	hdmi_hpd_active: hdmi_hpd_active {</div><div class='del'>-		mux {</div><div class='del'>-			pins = "gpio34";</div><div class='del'>-			function = "hdmi_hot";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		config {</div><div class='del'>-			pins = "gpio34";</div><div class='del'>-			bias-pull-down;</div><div class='del'>-			drive-strength = &lt;16&gt;;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	hdmi_hpd_suspend: hdmi_hpd_suspend {</div><div class='del'>-		mux {</div><div class='del'>-			pins = "gpio34";</div><div class='del'>-			function = "hdmi_hot";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		config {</div><div class='del'>-			pins = "gpio34";</div><div class='del'>-			bias-pull-down;</div><div class='del'>-			drive-strength = &lt;2&gt;;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	hdmi_ddc_active: hdmi_ddc_active {</div><div class='del'>-		mux {</div><div class='del'>-			pins = "gpio32", "gpio33";</div><div class='del'>-			function = "hdmi_ddc";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		config {</div><div class='del'>-			pins = "gpio32", "gpio33";</div><div class='del'>-			drive-strength = &lt;2&gt;;</div><div class='del'>-			bias-pull-up;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	hdmi_ddc_suspend: hdmi_ddc_suspend {</div><div class='del'>-		mux {</div><div class='del'>-			pins = "gpio32", "gpio33";</div><div class='del'>-			function = "hdmi_ddc";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		config {</div><div class='del'>-			pins = "gpio32", "gpio33";</div><div class='del'>-			drive-strength = &lt;2&gt;;</div><div class='del'>-			bias-pull-down;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;pcie0 {</div><div class='del'>-	status = "okay";</div><div class='del'>-	perst-gpio = &lt;&amp;msmgpio 35 GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-	vddpe-3v3-supply = &lt;&amp;wlan_en&gt;;</div><div class='del'>-	vdda-supply = &lt;&amp;vreg_l28a_0p925&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;pcie1 {</div><div class='del'>-	status = "okay";</div><div class='del'>-	perst-gpio = &lt;&amp;msmgpio 130 GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-	vdda-supply = &lt;&amp;vreg_l28a_0p925&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;pcie2 {</div><div class='del'>-	status = "okay";</div><div class='del'>-	perst-gpio = &lt;&amp;msmgpio 114 GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-	vdda-supply = &lt;&amp;vreg_l28a_0p925&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;pcie_phy {</div><div class='del'>-	status = "okay";</div><div class='del'>-</div><div class='del'>-	vdda-phy-supply = &lt;&amp;vreg_l28a_0p925&gt;;</div><div class='del'>-	vdda-pll-supply = &lt;&amp;vreg_l12a_1p8&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;pm8994_gpios {</div><div class='del'>-	gpio-line-names =</div><div class='del'>-		"NC",</div><div class='del'>-		"KEY_VOLP_N",</div><div class='del'>-		"NC",</div><div class='del'>-		"BL1_PWM",</div><div class='del'>-		"GPIO-F", /* BL0_PWM, LSEC pin 28 */</div><div class='del'>-		"BL1_EN",</div><div class='del'>-		"NC",</div><div class='del'>-		"WLAN_EN",</div><div class='del'>-		"NC",</div><div class='del'>-		"NC",</div><div class='del'>-		"NC",</div><div class='del'>-		"NC",</div><div class='del'>-		"NC",</div><div class='del'>-		"NC",</div><div class='del'>-		"DIVCLK1",</div><div class='del'>-		"DIVCLK2",</div><div class='del'>-		"DIVCLK3",</div><div class='del'>-		"DIVCLK4",</div><div class='del'>-		"BT_EN",</div><div class='del'>-		"PMIC_SLB",</div><div class='del'>-		"PMIC_BUA",</div><div class='del'>-		"USB_VBUS_DET";</div><div class='del'>-</div><div class='del'>-	pinctrl-names = "default";</div><div class='del'>-	pinctrl-0 = &lt;&amp;ls_exp_gpio_f &amp;bt_en_gpios&gt;;</div><div class='del'>-</div><div class='del'>-	ls_exp_gpio_f: pm8994_gpio5 {</div><div class='del'>-		pinconf {</div><div class='del'>-			pins = "gpio5";</div><div class='del'>-			output-low;</div><div class='del'>-			power-source = &lt;2&gt;; // PM8994_GPIO_S4, 1.8V</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	bt_en_gpios: bt_en_gpios {</div><div class='del'>-		pinconf {</div><div class='del'>-			pins = "gpio19";</div><div class='del'>-			function = PMIC_GPIO_FUNC_NORMAL;</div><div class='del'>-			output-low;</div><div class='del'>-			power-source = &lt;PM8994_GPIO_S4&gt;; // 1.8V</div><div class='del'>-			qcom,drive-strength = &lt;PMIC_GPIO_STRENGTH_LOW&gt;;</div><div class='del'>-			bias-pull-down;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	wlan_en_gpios: wlan_en_gpios {</div><div class='del'>-		pinconf {</div><div class='del'>-			pins = "gpio8";</div><div class='del'>-			function = PMIC_GPIO_FUNC_NORMAL;</div><div class='del'>-			output-low;</div><div class='del'>-			power-source = &lt;PM8994_GPIO_S4&gt;; // 1.8V</div><div class='del'>-			qcom,drive-strength = &lt;PMIC_GPIO_STRENGTH_LOW&gt;;</div><div class='del'>-			bias-pull-down;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	audio_mclk: clk_div1 {</div><div class='del'>-		pinconf {</div><div class='del'>-			pins = "gpio15";</div><div class='del'>-			function = "func1";</div><div class='del'>-			power-source = &lt;PM8994_GPIO_S4&gt;; // 1.8V</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	volume_up_gpio: pm8996_gpio2 {</div><div class='del'>-		pinconf {</div><div class='del'>-			pins = "gpio2";</div><div class='del'>-			function = "normal";</div><div class='del'>-			input-enable;</div><div class='del'>-			drive-push-pull;</div><div class='del'>-			bias-pull-up;</div><div class='del'>-			qcom,drive-strength = &lt;PMIC_GPIO_STRENGTH_NO&gt;;</div><div class='del'>-			power-source = &lt;PM8994_GPIO_S4&gt;; // 1.8V</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	divclk4_pin_a: divclk4 {</div><div class='del'>-		pinconf {</div><div class='del'>-			pins = "gpio18";</div><div class='del'>-			function = PMIC_GPIO_FUNC_FUNC2;</div><div class='del'>-</div><div class='del'>-			bias-disable;</div><div class='del'>-			power-source = &lt;PM8994_GPIO_S4&gt;;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	usb3_vbus_det_gpio: pm8996_gpio22 {</div><div class='del'>-		pinconf {</div><div class='del'>-			pins = "gpio22";</div><div class='del'>-			function = PMIC_GPIO_FUNC_NORMAL;</div><div class='del'>-			input-enable;</div><div class='del'>-			bias-pull-down;</div><div class='del'>-			qcom,drive-strength = &lt;PMIC_GPIO_STRENGTH_NO&gt;;</div><div class='del'>-			power-source = &lt;PM8994_GPIO_S4&gt;; // 1.8V</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;pm8994_mpps {</div><div class='del'>-	gpio-line-names =</div><div class='del'>-		"VDDPX_BIAS",</div><div class='del'>-		"WIFI_LED",</div><div class='del'>-		"NC",</div><div class='del'>-		"BT_LED",</div><div class='del'>-		"PM_MPP05",</div><div class='del'>-		"PM_MPP06",</div><div class='del'>-		"PM_MPP07",</div><div class='del'>-		"NC";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;pm8994_spmi_regulators {</div><div class='del'>-	qcom,saw-reg = &lt;&amp;saw3&gt;;</div><div class='del'>-	s9 {</div><div class='del'>-		qcom,saw-slave;</div><div class='del'>-	};</div><div class='del'>-	s10 {</div><div class='del'>-		qcom,saw-slave;</div><div class='del'>-	};</div><div class='del'>-	s11 {</div><div class='del'>-		qcom,saw-leader;</div><div class='del'>-		regulator-always-on;</div><div class='del'>-		regulator-min-microvolt = &lt;1230000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;1230000&gt;;</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;pmi8994_gpios {</div><div class='del'>-	gpio-line-names =</div><div class='del'>-		"NC",</div><div class='del'>-		"SPKR_AMP_EN1",</div><div class='del'>-		"SPKR_AMP_EN2",</div><div class='del'>-		"TP61",</div><div class='del'>-		"NC",</div><div class='del'>-		"USB2_VBUS_DET",</div><div class='del'>-		"NC",</div><div class='del'>-		"NC",</div><div class='del'>-		"NC",</div><div class='del'>-		"NC";</div><div class='del'>-</div><div class='del'>-	usb2_vbus_det_gpio: pmi8996_gpio6 {</div><div class='del'>-		pinconf {</div><div class='del'>-			pins = "gpio6";</div><div class='del'>-			function = PMIC_GPIO_FUNC_NORMAL;</div><div class='del'>-			input-enable;</div><div class='del'>-			bias-pull-down;</div><div class='del'>-			qcom,drive-strength = &lt;PMIC_GPIO_STRENGTH_NO&gt;;</div><div class='del'>-			power-source = &lt;PM8994_GPIO_S4&gt;; // 1.8V</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;rpm_requests {</div><div class='del'>-	pm8994-regulators {</div><div class='del'>-		compatible = "qcom,rpm-pm8994-regulators";</div><div class='del'>-</div><div class='del'>-		vdd_s1-supply = &lt;&amp;vph_pwr&gt;;</div><div class='del'>-		vdd_s2-supply = &lt;&amp;vph_pwr&gt;;</div><div class='del'>-		vdd_s3-supply = &lt;&amp;vph_pwr&gt;;</div><div class='del'>-		vdd_s4-supply = &lt;&amp;vph_pwr&gt;;</div><div class='del'>-		vdd_s5-supply = &lt;&amp;vph_pwr&gt;;</div><div class='del'>-		vdd_s6-supply = &lt;&amp;vph_pwr&gt;;</div><div class='del'>-		vdd_s7-supply = &lt;&amp;vph_pwr&gt;;</div><div class='del'>-		vdd_s8-supply = &lt;&amp;vph_pwr&gt;;</div><div class='del'>-		vdd_s9-supply = &lt;&amp;vph_pwr&gt;;</div><div class='del'>-		vdd_s10-supply = &lt;&amp;vph_pwr&gt;;</div><div class='del'>-		vdd_s11-supply = &lt;&amp;vph_pwr&gt;;</div><div class='del'>-		vdd_s12-supply = &lt;&amp;vph_pwr&gt;;</div><div class='del'>-		vdd_l2_l26_l28-supply = &lt;&amp;vreg_s3a_1p3&gt;;</div><div class='del'>-		vdd_l3_l11-supply = &lt;&amp;vreg_s8a_l3a_input&gt;;</div><div class='del'>-		vdd_l4_l27_l31-supply = &lt;&amp;vreg_s3a_1p3&gt;;</div><div class='del'>-		vdd_l5_l7-supply = &lt;&amp;vreg_s5a_2p15&gt;;</div><div class='del'>-		vdd_l6_l12_l32-supply = &lt;&amp;vreg_s5a_2p15&gt;;</div><div class='del'>-		vdd_l8_l16_l30-supply = &lt;&amp;vph_pwr&gt;;</div><div class='del'>-		vdd_l14_l15-supply = &lt;&amp;vreg_s5a_2p15&gt;;</div><div class='del'>-		vdd_l25-supply = &lt;&amp;vreg_s3a_1p3&gt;;</div><div class='del'>-		vdd_lvs1_2-supply = &lt;&amp;vreg_s4a_1p8&gt;;</div><div class='del'>-</div><div class='del'>-		vreg_s3a_1p3: s3 {</div><div class='del'>-			regulator-name = "vreg_s3a_1p3";</div><div class='del'>-			regulator-min-microvolt = &lt;1300000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;1300000&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		/**</div><div class='del'>-		 * 1.8v required on LS expansion</div><div class='del'>-		 * for mezzanine boards</div><div class='del'>-		 */</div><div class='del'>-		vreg_s4a_1p8: s4 {</div><div class='del'>-			regulator-name = "vreg_s4a_1p8";</div><div class='del'>-			regulator-min-microvolt = &lt;1800000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;1800000&gt;;</div><div class='del'>-			regulator-always-on;</div><div class='del'>-		};</div><div class='del'>-		vreg_s5a_2p15: s5 {</div><div class='del'>-			regulator-name = "vreg_s5a_2p15";</div><div class='del'>-			regulator-min-microvolt = &lt;2150000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;2150000&gt;;</div><div class='del'>-		};</div><div class='del'>-		vreg_s7a_1p0: s7 {</div><div class='del'>-			regulator-name = "vreg_s7a_1p0";</div><div class='del'>-			regulator-min-microvolt = &lt;800000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;800000&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		vreg_l1a_1p0: l1 {</div><div class='del'>-			regulator-name = "vreg_l1a_1p0";</div><div class='del'>-			regulator-min-microvolt = &lt;1000000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;1000000&gt;;</div><div class='del'>-		};</div><div class='del'>-		vreg_l2a_1p25: l2 {</div><div class='del'>-			regulator-name = "vreg_l2a_1p25";</div><div class='del'>-			regulator-min-microvolt = &lt;1250000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;1250000&gt;;</div><div class='del'>-		};</div><div class='del'>-		vreg_l3a_0p875: l3 {</div><div class='del'>-			regulator-name = "vreg_l3a_0p875";</div><div class='del'>-			regulator-min-microvolt = &lt;850000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;850000&gt;;</div><div class='del'>-		};</div><div class='del'>-		vreg_l4a_1p225: l4 {</div><div class='del'>-			regulator-name = "vreg_l4a_1p225";</div><div class='del'>-			regulator-min-microvolt = &lt;1225000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;1225000&gt;;</div><div class='del'>-		};</div><div class='del'>-		vreg_l6a_1p2: l6 {</div><div class='del'>-			regulator-name = "vreg_l6a_1p2";</div><div class='del'>-			regulator-min-microvolt = &lt;1200000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;1200000&gt;;</div><div class='del'>-		};</div><div class='del'>-		vreg_l8a_1p8: l8 {</div><div class='del'>-			regulator-name = "vreg_l8a_1p8";</div><div class='del'>-			regulator-min-microvolt = &lt;1800000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;1800000&gt;;</div><div class='del'>-		};</div><div class='del'>-		vreg_l9a_1p8: l9 {</div><div class='del'>-			regulator-name = "vreg_l9a_1p8";</div><div class='del'>-			regulator-min-microvolt = &lt;1800000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;1800000&gt;;</div><div class='del'>-		};</div><div class='del'>-		vreg_l10a_1p8: l10 {</div><div class='del'>-			regulator-name = "vreg_l10a_1p8";</div><div class='del'>-			regulator-min-microvolt = &lt;1800000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;1800000&gt;;</div><div class='del'>-		};</div><div class='del'>-		vreg_l11a_1p15: l11 {</div><div class='del'>-			regulator-name = "vreg_l11a_1p15";</div><div class='del'>-			regulator-min-microvolt = &lt;1150000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;1150000&gt;;</div><div class='del'>-		};</div><div class='del'>-		vreg_l12a_1p8: l12 {</div><div class='del'>-			regulator-name = "vreg_l12a_1p8";</div><div class='del'>-			regulator-min-microvolt = &lt;1800000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;1800000&gt;;</div><div class='del'>-		};</div><div class='del'>-		vreg_l13a_2p95: l13 {</div><div class='del'>-			regulator-name = "vreg_l13a_2p95";</div><div class='del'>-			regulator-min-microvolt = &lt;1800000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;2950000&gt;;</div><div class='del'>-		};</div><div class='del'>-		vreg_l14a_1p8: l14 {</div><div class='del'>-			regulator-name = "vreg_l14a_1p8";</div><div class='del'>-			regulator-min-microvolt = &lt;1800000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;1800000&gt;;</div><div class='del'>-		};</div><div class='del'>-		vreg_l15a_1p8: l15 {</div><div class='del'>-			regulator-name = "vreg_l15a_1p8";</div><div class='del'>-			regulator-min-microvolt = &lt;1800000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;1800000&gt;;</div><div class='del'>-		};</div><div class='del'>-		vreg_l16a_2p7: l16 {</div><div class='del'>-			regulator-name = "vreg_l16a_2p7";</div><div class='del'>-			regulator-min-microvolt = &lt;2700000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;2700000&gt;;</div><div class='del'>-		};</div><div class='del'>-		vreg_l17a_2p8: l17 {</div><div class='del'>-			regulator-name = "vreg_l17a_2p8";</div><div class='del'>-			regulator-min-microvolt = &lt;2500000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;2500000&gt;;</div><div class='del'>-		};</div><div class='del'>-		vreg_l18a_2p85: l18 {</div><div class='del'>-			regulator-name = "vreg_l18a_2p85";</div><div class='del'>-			regulator-min-microvolt = &lt;2700000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;2900000&gt;;</div><div class='del'>-		};</div><div class='del'>-		vreg_l19a_2p8: l19 {</div><div class='del'>-			regulator-name = "vreg_l19a_2p8";</div><div class='del'>-			regulator-min-microvolt = &lt;3000000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;3000000&gt;;</div><div class='del'>-		};</div><div class='del'>-		vreg_l20a_2p95: l20 {</div><div class='del'>-			regulator-name = "vreg_l20a_2p95";</div><div class='del'>-			regulator-min-microvolt = &lt;2950000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;2950000&gt;;</div><div class='del'>-			regulator-allow-set-load;</div><div class='del'>-		};</div><div class='del'>-		vreg_l21a_2p95: l21 {</div><div class='del'>-			regulator-name = "vreg_l21a_2p95";</div><div class='del'>-			regulator-min-microvolt = &lt;2950000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;2950000&gt;;</div><div class='del'>-			regulator-allow-set-load;</div><div class='del'>-			regulator-system-load = &lt;200000&gt;;</div><div class='del'>-		};</div><div class='del'>-		vreg_l22a_3p0: l22 {</div><div class='del'>-			regulator-name = "vreg_l22a_3p0";</div><div class='del'>-			regulator-min-microvolt = &lt;3300000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;3300000&gt;;</div><div class='del'>-		};</div><div class='del'>-		vreg_l23a_2p8: l23 {</div><div class='del'>-			regulator-name = "vreg_l23a_2p8";</div><div class='del'>-			regulator-min-microvolt = &lt;2800000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;2800000&gt;;</div><div class='del'>-		};</div><div class='del'>-		vreg_l24a_3p075: l24 {</div><div class='del'>-			regulator-name = "vreg_l24a_3p075";</div><div class='del'>-			regulator-min-microvolt = &lt;3075000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;3075000&gt;;</div><div class='del'>-		};</div><div class='del'>-		vreg_l25a_1p2: l25 {</div><div class='del'>-			regulator-name = "vreg_l25a_1p2";</div><div class='del'>-			regulator-min-microvolt = &lt;1200000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;1200000&gt;;</div><div class='del'>-			regulator-allow-set-load;</div><div class='del'>-		};</div><div class='del'>-		vreg_l26a_0p8: l27 {</div><div class='del'>-			regulator-name = "vreg_l26a_0p8";</div><div class='del'>-			regulator-min-microvolt = &lt;1000000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;1000000&gt;;</div><div class='del'>-		};</div><div class='del'>-		vreg_l28a_0p925: l28 {</div><div class='del'>-			regulator-name = "vreg_l28a_0p925";</div><div class='del'>-			regulator-min-microvolt = &lt;925000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;925000&gt;;</div><div class='del'>-			regulator-allow-set-load;</div><div class='del'>-		};</div><div class='del'>-		vreg_l29a_2p8: l29 {</div><div class='del'>-			regulator-name = "vreg_l29a_2p8";</div><div class='del'>-			regulator-min-microvolt = &lt;2800000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;2800000&gt;;</div><div class='del'>-		};</div><div class='del'>-		vreg_l30a_1p8: l30 {</div><div class='del'>-			regulator-name = "vreg_l30a_1p8";</div><div class='del'>-			regulator-min-microvolt = &lt;1800000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;1800000&gt;;</div><div class='del'>-		};</div><div class='del'>-		vreg_l32a_1p8: l32 {</div><div class='del'>-			regulator-name = "vreg_l32a_1p8";</div><div class='del'>-			regulator-min-microvolt = &lt;1800000&gt;;</div><div class='del'>-			regulator-max-microvolt = &lt;1800000&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		vreg_lvs1a_1p8: lvs1 {</div><div class='del'>-			regulator-name = "vreg_lvs1a_1p8";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		vreg_lvs2a_1p8: lvs2 {</div><div class='del'>-			regulator-name = "vreg_lvs2a_1p8";</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;sdhc2 {</div><div class='del'>-	/* External SD card */</div><div class='del'>-	pinctrl-names = "default", "sleep";</div><div class='del'>-	pinctrl-0 = &lt;&amp;sdc2_clk_on &amp;sdc2_cmd_on &amp;sdc2_data_on &amp;sdc2_cd_on&gt;;</div><div class='del'>-	pinctrl-1 = &lt;&amp;sdc2_clk_off &amp;sdc2_cmd_off &amp;sdc2_data_off &amp;sdc2_cd_off&gt;;</div><div class='del'>-	cd-gpios = &lt;&amp;msmgpio 38 0x1&gt;;</div><div class='del'>-	vmmc-supply = &lt;&amp;vreg_l21a_2p95&gt;;</div><div class='del'>-	vqmmc-supply = &lt;&amp;vreg_l13a_2p95&gt;;</div><div class='del'>-	status = "okay";</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;sound {</div><div class='del'>-	compatible = "qcom,apq8096-sndcard";</div><div class='del'>-	model = "DB820c";</div><div class='del'>-	audio-routing =	"RX_BIAS", "MCLK";</div><div class='del'>-</div><div class='del'>-	mm1-dai-link {</div><div class='del'>-		link-name = "MultiMedia1";</div><div class='del'>-		cpu {</div><div class='del'>-			sound-dai = &lt;&amp;q6asmdai  MSM_FRONTEND_DAI_MULTIMEDIA1&gt;;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	mm2-dai-link {</div><div class='del'>-		link-name = "MultiMedia2";</div><div class='del'>-		cpu {</div><div class='del'>-			sound-dai = &lt;&amp;q6asmdai  MSM_FRONTEND_DAI_MULTIMEDIA2&gt;;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	mm3-dai-link {</div><div class='del'>-		link-name = "MultiMedia3";</div><div class='del'>-		cpu {</div><div class='del'>-			sound-dai = &lt;&amp;q6asmdai  MSM_FRONTEND_DAI_MULTIMEDIA3&gt;;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	hdmi-dai-link {</div><div class='del'>-		link-name = "HDMI";</div><div class='del'>-		cpu {</div><div class='del'>-			sound-dai = &lt;&amp;q6afedai HDMI_RX&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		platform {</div><div class='del'>-			sound-dai = &lt;&amp;q6routing&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		codec {</div><div class='del'>-			sound-dai = &lt;&amp;hdmi 0&gt;;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	slim-dai-link {</div><div class='del'>-		link-name = "SLIM Playback";</div><div class='del'>-		cpu {</div><div class='del'>-			sound-dai = &lt;&amp;q6afedai SLIMBUS_6_RX&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		platform {</div><div class='del'>-			sound-dai = &lt;&amp;q6routing&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-		codec {</div><div class='del'>-			sound-dai = &lt;&amp;wcd9335 6&gt;;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	slimcap-dai-link {</div><div class='del'>-		link-name = "SLIM Capture";</div><div class='del'>-		cpu {</div><div class='del'>-			sound-dai = &lt;&amp;q6afedai SLIMBUS_0_TX&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		platform {</div><div class='del'>-			sound-dai = &lt;&amp;q6routing&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		codec {</div><div class='del'>-			sound-dai = &lt;&amp;wcd9335 1&gt;;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;spmi_bus {</div><div class='del'>-	pmic@0 {</div><div class='del'>-		pon@800 {</div><div class='del'>-			resin {</div><div class='del'>-				compatible = "qcom,pm8941-resin";</div><div class='del'>-				interrupts = &lt;0x0 0x8 1 IRQ_TYPE_EDGE_BOTH&gt;;</div><div class='del'>-				debounce = &lt;15625&gt;;</div><div class='del'>-				bias-pull-up;</div><div class='del'>-				linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;ufsphy {</div><div class='del'>-	status = "okay";</div><div class='del'>-</div><div class='del'>-	vdda-phy-supply = &lt;&amp;vreg_l28a_0p925&gt;;</div><div class='del'>-	vdda-pll-supply = &lt;&amp;vreg_l12a_1p8&gt;;</div><div class='del'>-	vddp-ref-clk-supply = &lt;&amp;vreg_l25a_1p2&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;ufshc {</div><div class='del'>-	status = "okay";</div><div class='del'>-</div><div class='del'>-	vcc-supply = &lt;&amp;vreg_l20a_2p95&gt;;</div><div class='del'>-	vccq-supply = &lt;&amp;vreg_l25a_1p2&gt;;</div><div class='del'>-	vccq2-supply = &lt;&amp;vreg_s4a_1p8&gt;;</div><div class='del'>-</div><div class='del'>-	vcc-max-microamp = &lt;600000&gt;;</div><div class='del'>-	vccq-max-microamp = &lt;450000&gt;;</div><div class='del'>-	vccq2-max-microamp = &lt;450000&gt;;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;usb2 {</div><div class='del'>-	status = "okay";</div><div class='del'>-	extcon = &lt;&amp;usb2_id&gt;;</div><div class='del'>-</div><div class='del'>-	dwc3@7600000 {</div><div class='del'>-		extcon = &lt;&amp;usb2_id&gt;;</div><div class='del'>-		dr_mode = "otg";</div><div class='del'>-		maximum-speed = "high-speed";</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;usb3 {</div><div class='del'>-	status = "okay";</div><div class='del'>-	extcon = &lt;&amp;usb3_id&gt;;</div><div class='del'>-</div><div class='del'>-	dwc3@6a00000 {</div><div class='del'>-		extcon = &lt;&amp;usb3_id&gt;;</div><div class='del'>-		dr_mode = "otg";</div><div class='del'>-	};</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;usb3phy {</div><div class='del'>-	status = "okay";</div><div class='del'>-</div><div class='del'>-	vdda-phy-supply = &lt;&amp;vreg_l28a_0p925&gt;;</div><div class='del'>-	vdda-pll-supply = &lt;&amp;vreg_l12a_1p8&gt;;</div><div class='del'>-</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-&amp;wcd9335 {</div><div class='del'>-	clock-names = "mclk", "slimbus";</div><div class='del'>-	clocks = &lt;&amp;div1_mclk&gt;,</div><div class='del'>-		 &lt;&amp;rpmcc RPM_SMD_BB_CLK1&gt;;</div><div class='del'>-</div><div class='del'>-	vdd-buck-supply = &lt;&amp;vreg_s4a_1p8&gt;;</div><div class='del'>-	vdd-buck-sido-supply = &lt;&amp;vreg_s4a_1p8&gt;;</div><div class='del'>-	vdd-tx-supply = &lt;&amp;vreg_s4a_1p8&gt;;</div><div class='del'>-	vdd-rx-supply = &lt;&amp;vreg_s4a_1p8&gt;;</div><div class='del'>-	vdd-io-supply = &lt;&amp;vreg_s4a_1p8&gt;;</div><div class='del'>-};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts b/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts<br/>index f6ddf17ada81..ac6471d1db1f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts</a></div><div class='hunk'>@@ -17,7 +17,7 @@</div><div class='ctx'> 	qcom,board-id = &lt;0x00010018 0&gt;;</div><div class='ctx'> </div><div class='ctx'> 	aliases {</div><div class='del'>-		serial0 = &amp;blsp2_uart1;</div><div class='add'>+		serial0 = &amp;blsp2_uart2;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	chosen {</div><div class='hunk'>@@ -26,7 +26,7 @@</div><div class='ctx'> </div><div class='ctx'> 	v1p05: v1p05-regulator {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='del'>-		reglator-name = "v1p05";</div><div class='add'>+		regulator-name = "v1p05";</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 		regulator-boot-on;</div><div class='ctx'> </div><div class='hunk'>@@ -38,7 +38,7 @@</div><div class='ctx'> </div><div class='ctx'> 	v12_poe: v12-poe-regulator {</div><div class='ctx'> 		compatible = "regulator-fixed";</div><div class='del'>-		reglator-name = "v12_poe";</div><div class='add'>+		regulator-name = "v12_poe";</div><div class='ctx'> 		regulator-always-on;</div><div class='ctx'> 		regulator-boot-on;</div><div class='ctx'> </div><div class='hunk'>@@ -81,72 +81,50 @@</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;blsp2_uart1 {</div><div class='add'>+&amp;blsp2_uart2 {</div><div class='ctx'> 	status = "okay";</div><div class='ctx'> 	pinctrl-names = "default", "sleep";</div><div class='del'>-	pinctrl-0 = &lt;&amp;blsp2_uart1_2pins_default&gt;;</div><div class='del'>-	pinctrl-1 = &lt;&amp;blsp2_uart1_2pins_sleep&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;blsp2_uart2_2pins_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;blsp2_uart2_2pins_sleep&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;msmgpio {</div><div class='del'>-	sdc2_pins_default: sdc2-pins-default {</div><div class='del'>-		clk {</div><div class='del'>-			pins = "sdc2_clk";</div><div class='del'>-			bias-disable;</div><div class='del'>-			drive-strength = &lt;16&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		cmd {</div><div class='del'>-			pins = "sdc2_cmd";</div><div class='del'>-			bias-pull-up;</div><div class='del'>-			drive-strength = &lt;10&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		data {</div><div class='del'>-			pins = "sdc2_data";</div><div class='del'>-			bias-pull-up;</div><div class='del'>-			drive-strength = &lt;10&gt;;</div><div class='del'>-		};</div><div class='add'>+&amp;gpu {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='ctx'> </div><div class='del'>-		cd {</div><div class='del'>-			pins = "gpio38";</div><div class='del'>-			function = "gpio";</div><div class='add'>+&amp;mdss {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='ctx'> </div><div class='del'>-			bias-pull-up;</div><div class='del'>-			drive-strength = &lt;16&gt;;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='add'>+&amp;mdss_hdmi {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='ctx'> </div><div class='del'>-	sdc2_pins_sleep: sdc2-pins-sleep {</div><div class='del'>-		clk {</div><div class='del'>-			pins = "sdc2_clk";</div><div class='del'>-			bias-disable;</div><div class='del'>-			drive-strength = &lt;2&gt;;</div><div class='del'>-		};</div><div class='add'>+&amp;mdss_hdmi_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='ctx'> </div><div class='del'>-		cmd {</div><div class='del'>-			pins = "sdc2_cmd";</div><div class='del'>-			bias-pull-up;</div><div class='del'>-			drive-strength = &lt;2&gt;;</div><div class='del'>-		};</div><div class='add'>+&amp;sdc2_state_on {</div><div class='add'>+	cd-pins {</div><div class='add'>+		pins = "gpio38";</div><div class='add'>+		function = "gpio";</div><div class='ctx'> </div><div class='del'>-		data {</div><div class='del'>-			pins = "sdc2_data";</div><div class='del'>-			bias-pull-up;</div><div class='del'>-			drive-strength = &lt;2&gt;;</div><div class='del'>-		};</div><div class='add'>+		bias-pull-up;</div><div class='add'>+		drive-strength = &lt;16&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='ctx'> </div><div class='del'>-		cd {</div><div class='del'>-			pins = "gpio38";</div><div class='del'>-			function = "gpio";</div><div class='del'>-			bias-pull-up;</div><div class='del'>-			drive-strength = &lt;2&gt;;</div><div class='del'>-		};</div><div class='add'>+&amp;sdc2_state_off {</div><div class='add'>+	cd-pins {</div><div class='add'>+		pins = "gpio38";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		bias-pull-up;</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;rpm_requests {</div><div class='del'>-	pm8994-regulators {</div><div class='add'>+	regulators-0 {</div><div class='ctx'> 		compatible = "qcom,rpm-pm8994-regulators";</div><div class='ctx'> </div><div class='ctx'> 		vdd_s1-supply = &lt;&amp;vph_pwr&gt;;</div><div class='hunk'>@@ -352,14 +330,10 @@</div><div class='ctx'> </div><div class='ctx'> 	bus-width = &lt;4&gt;;</div><div class='ctx'> </div><div class='del'>-	cd-gpios = &lt;&amp;msmgpio 38 0x1&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;tlmm 38 GPIO_ACTIVE_LOW&gt;;</div><div class='ctx'> </div><div class='ctx'> 	vmmc-supply = &lt;&amp;vreg_l21a_2p95&gt;;</div><div class='ctx'> 	vqmmc-supply = &lt;&amp;vreg_l13a_2p95&gt;;</div><div class='del'>-</div><div class='del'>-	pinctrl-names = "default", "sleep";</div><div class='del'>-	pinctrl-0 = &lt;&amp;sdc2_pins_default&gt;;</div><div class='del'>-	pinctrl-1 = &lt;&amp;sdc2_pins_sleep&gt;;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;ufshc {</div><div class='hunk'>@@ -379,7 +353,8 @@</div><div class='ctx'> </div><div class='ctx'> 	vdda-phy-supply = &lt;&amp;vreg_l28a_0p925&gt;;</div><div class='ctx'> 	vdda-pll-supply = &lt;&amp;vreg_l12a_1p8&gt;;</div><div class='add'>+};</div><div class='ctx'> </div><div class='del'>-	vdda-phy-max-microamp = &lt;18380&gt;;</div><div class='del'>-	vdda-pll-max-microamp = &lt;9440&gt;;</div><div class='add'>+&amp;venus {</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts<br/>new file mode 100644<br/>index 000000000000..36dd6599402b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts</a></div><div class='hunk'>@@ -0,0 +1,1242 @@</div><div class='add'>+// SPDX-License-Identifier: BSD-3-Clause</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "hamoa-iot-som.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Qualcomm Technologies, Inc. Hamoa IoT EVK";</div><div class='add'>+	compatible = "qcom,hamoa-iot-evk", "qcom,hamoa-iot-som", "qcom,x1e80100";</div><div class='add'>+	chassis-type = "embedded";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart21;</div><div class='add'>+		serial1 = &amp;uart14;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wcd938x: audio-codec {</div><div class='add'>+		compatible = "qcom,wcd9385-codec";</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;wcd_default&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		reset-gpios = &lt;&amp;tlmm 191 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		qcom,micbias1-microvolt = &lt;1800000&gt;;</div><div class='add'>+		qcom,micbias2-microvolt = &lt;1800000&gt;;</div><div class='add'>+		qcom,micbias3-microvolt = &lt;1800000&gt;;</div><div class='add'>+		qcom,micbias4-microvolt = &lt;1800000&gt;;</div><div class='add'>+		qcom,mbhc-buttons-vthreshold-microvolt = &lt;75000 150000 237000 500000</div><div class='add'>+							 500000 500000 500000 500000&gt;;</div><div class='add'>+		qcom,mbhc-headset-vthreshold-microvolt = &lt;1700000&gt;;</div><div class='add'>+		qcom,mbhc-headphone-vthreshold-microvolt = &lt;50000&gt;;</div><div class='add'>+		qcom,rx-device = &lt;&amp;wcd_rx&gt;;</div><div class='add'>+		qcom,tx-device = &lt;&amp;wcd_tx&gt;;</div><div class='add'>+</div><div class='add'>+		vdd-buck-supply = &lt;&amp;vreg_l15b_1p8&gt;;</div><div class='add'>+		vdd-rxtx-supply = &lt;&amp;vreg_l15b_1p8&gt;;</div><div class='add'>+		vdd-io-supply = &lt;&amp;vreg_l15b_1p8&gt;;</div><div class='add'>+		vdd-mic-bias-supply = &lt;&amp;vreg_bob1&gt;;</div><div class='add'>+</div><div class='add'>+		#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmic-glink {</div><div class='add'>+		compatible = "qcom,x1e80100-pmic-glink",</div><div class='add'>+			     "qcom,sm8550-pmic-glink",</div><div class='add'>+			     "qcom,pmic-glink";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		orientation-gpios = &lt;&amp;tlmm 121 GPIO_ACTIVE_HIGH&gt;,</div><div class='add'>+				    &lt;&amp;tlmm 123 GPIO_ACTIVE_HIGH&gt;,</div><div class='add'>+				    &lt;&amp;tlmm 125 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+		connector@0 {</div><div class='add'>+			compatible = "usb-c-connector";</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			power-role = "dual";</div><div class='add'>+			data-role = "dual";</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					pmic_glink_ss0_hs_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;usb_1_ss0_dwc3_hs&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					pmic_glink_ss0_ss_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;usb_1_ss0_qmpphy_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@2 {</div><div class='add'>+					reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+					pmic_glink_ss0_sbu: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;usb_1_ss0_sbu_mux&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		connector@1 {</div><div class='add'>+			compatible = "usb-c-connector";</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			power-role = "dual";</div><div class='add'>+			data-role = "dual";</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					pmic_glink_ss1_hs_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;usb_1_ss1_dwc3_hs&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					pmic_glink_ss1_ss_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;retimer_ss1_ss_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@2 {</div><div class='add'>+					reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+					pmic_glink_ss1_con_sbu_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;retimer_ss1_con_sbu_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		connector@2 {</div><div class='add'>+			compatible = "usb-c-connector";</div><div class='add'>+			reg = &lt;2&gt;;</div><div class='add'>+			power-role = "dual";</div><div class='add'>+			data-role = "dual";</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					pmic_glink_ss2_hs_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;usb_1_ss2_dwc3_hs&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					pmic_glink_ss2_ss_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;retimer_ss2_ss_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@2 {</div><div class='add'>+					reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+					pmic_glink_ss2_con_sbu_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;retimer_ss2_con_sbu_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vreg_edp_3p3: regulator-edp-3p3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+</div><div class='add'>+		regulator-name = "VREG_EDP_3P3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;tlmm 70 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;edp_reg_en&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vreg_nvme: regulator-nvme {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+</div><div class='add'>+		regulator-name = "VREG_NVME_3P3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;tlmm 18 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;nvme_reg_en&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Left unused as the retimer is not used on this board. */</div><div class='add'>+	vreg_rtmr0_1p15: regulator-rtmr0-1p15 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+</div><div class='add'>+		regulator-name = "VREG_RTMR0_1P15";</div><div class='add'>+		regulator-min-microvolt = &lt;1150000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1150000&gt;;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;usb0_pwr_1p15_reg_en&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vreg_rtmr0_1p8: regulator-rtmr0-1p8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+</div><div class='add'>+		regulator-name = "VREG_RTMR0_1P8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;usb0_1p8_reg_en&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vreg_rtmr0_3p3: regulator-rtmr0-3p3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+</div><div class='add'>+		regulator-name = "VREG_RTMR0_3P3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;pm8550_gpios 11 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;usb0_3p3_reg_en&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vreg_rtmr1_1p15: regulator-rtmr1-1p15 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+</div><div class='add'>+		regulator-name = "VREG_RTMR1_1P15";</div><div class='add'>+		regulator-min-microvolt = &lt;1150000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1150000&gt;;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;tlmm 188 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;usb1_pwr_1p15_reg_en&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vreg_rtmr1_1p8: regulator-rtmr1-1p8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+</div><div class='add'>+		regulator-name = "VREG_RTMR1_1P8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;tlmm 175 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;usb1_pwr_1p8_reg_en&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vreg_rtmr1_3p3: regulator-rtmr1-3p3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+</div><div class='add'>+		regulator-name = "VREG_RTMR1_3P3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;tlmm 186 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;usb1_pwr_3p3_reg_en&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vreg_rtmr2_1p15: regulator-rtmr2-1p15 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+</div><div class='add'>+		regulator-name = "VREG_RTMR2_1P15";</div><div class='add'>+		regulator-min-microvolt = &lt;1150000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1150000&gt;;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;tlmm 189 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;usb2_pwr_1p15_reg_en&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vreg_rtmr2_1p8: regulator-rtmr2-1p8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+</div><div class='add'>+		regulator-name = "VREG_RTMR2_1P8";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;tlmm 126 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;usb2_pwr_1p8_reg_en&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vreg_rtmr2_3p3: regulator-rtmr2-3p3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+</div><div class='add'>+		regulator-name = "VREG_RTMR2_3P3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;tlmm 187 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;usb2_pwr_3p3_reg_en&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vph_pwr: regulator-vph-pwr {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+</div><div class='add'>+		regulator-name = "vph_pwr";</div><div class='add'>+		regulator-min-microvolt = &lt;3700000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3700000&gt;;</div><div class='add'>+</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * TODO: These two regulators are actually part of the removable M.2</div><div class='add'>+	 * card and not the EVK mainboard. Need to describe this differently.</div><div class='add'>+	 * Functionally it works correctly, because all we need to do is to</div><div class='add'>+	 * turn on the actual 3.3V supply above.</div><div class='add'>+	 */</div><div class='add'>+	vreg_wcn_0p95: regulator-wcn-0p95 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+</div><div class='add'>+		regulator-name = "VREG_WCN_0P95";</div><div class='add'>+		regulator-min-microvolt = &lt;950000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;950000&gt;;</div><div class='add'>+</div><div class='add'>+		vin-supply = &lt;&amp;vreg_wcn_3p3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vreg_wcn_1p9: regulator-wcn-1p9 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+</div><div class='add'>+		regulator-name = "VREG_WCN_1P9";</div><div class='add'>+		regulator-min-microvolt = &lt;1900000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1900000&gt;;</div><div class='add'>+</div><div class='add'>+		vin-supply = &lt;&amp;vreg_wcn_3p3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vreg_wcn_3p3: regulator-wcn-3p3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+</div><div class='add'>+		regulator-name = "VREG_WCN_3P3";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;tlmm 214 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;wcn_sw_en&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vreg_wwan: regulator-wwan {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+</div><div class='add'>+		regulator-name = "SDX_VPH_PWR";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;tlmm 221 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;wwan_sw_en&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "qcom,x1e80100-sndcard";</div><div class='add'>+		model = "X1E80100-EVK";</div><div class='add'>+		audio-routing = "WooferLeft IN", "WSA WSA_SPK1 OUT",</div><div class='add'>+				"TweeterLeft IN", "WSA WSA_SPK2 OUT",</div><div class='add'>+				"WooferRight IN", "WSA2 WSA_SPK2 OUT",</div><div class='add'>+				"TweeterRight IN", "WSA2 WSA_SPK2 OUT",</div><div class='add'>+				"IN1_HPHL", "HPHL_OUT",</div><div class='add'>+				"IN2_HPHR", "HPHR_OUT",</div><div class='add'>+				"AMIC2", "MIC BIAS2",</div><div class='add'>+				"VA DMIC0", "MIC BIAS3",</div><div class='add'>+				"VA DMIC1", "MIC BIAS3",</div><div class='add'>+				"VA DMIC2", "MIC BIAS1",</div><div class='add'>+				"VA DMIC3", "MIC BIAS1",</div><div class='add'>+				"TX SWR_INPUT1", "ADC2_OUTPUT";</div><div class='add'>+</div><div class='add'>+		wcd-playback-dai-link {</div><div class='add'>+			link-name = "WCD Playback";</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;wcd938x 0&gt;, &lt;&amp;swr1 0&gt;, &lt;&amp;lpass_rxmacro 0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cpu {</div><div class='add'>+				sound-dai = &lt;&amp;q6apmbedai RX_CODEC_DMA_RX_0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			platform {</div><div class='add'>+				sound-dai = &lt;&amp;q6apm&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wcd-capture-dai-link {</div><div class='add'>+			link-name = "WCD Capture";</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;wcd938x 1&gt;, &lt;&amp;swr2 1&gt;, &lt;&amp;lpass_txmacro 0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cpu {</div><div class='add'>+				sound-dai = &lt;&amp;q6apmbedai TX_CODEC_DMA_TX_3&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			platform {</div><div class='add'>+				sound-dai = &lt;&amp;q6apm&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wsa-dai-link {</div><div class='add'>+			link-name = "WSA Playback";</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;left_woofer&gt;,</div><div class='add'>+					    &lt;&amp;left_tweeter&gt;,</div><div class='add'>+					    &lt;&amp;swr0 0&gt;,</div><div class='add'>+					    &lt;&amp;lpass_wsamacro 0&gt;,</div><div class='add'>+					    &lt;&amp;right_woofer&gt;,</div><div class='add'>+					    &lt;&amp;right_tweeter&gt;,</div><div class='add'>+					    &lt;&amp;swr3 0&gt;,</div><div class='add'>+					    &lt;&amp;lpass_wsa2macro 0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cpu {</div><div class='add'>+				sound-dai = &lt;&amp;q6apmbedai WSA_CODEC_DMA_RX_0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			platform {</div><div class='add'>+				sound-dai = &lt;&amp;q6apm&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		va-dai-link {</div><div class='add'>+			link-name = "VA Capture";</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;lpass_vamacro 0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cpu {</div><div class='add'>+				sound-dai = &lt;&amp;q6apmbedai VA_CODEC_DMA_TX_0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			platform {</div><div class='add'>+				sound-dai = &lt;&amp;q6apm&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb-1-ss0-sbu-mux {</div><div class='add'>+		compatible = "onnn,fsusb42", "gpio-sbu-mux";</div><div class='add'>+</div><div class='add'>+		enable-gpios = &lt;&amp;tlmm 168 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		select-gpios = &lt;&amp;tlmm 167 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;usb_1_ss0_sbu_default&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		mode-switch;</div><div class='add'>+		orientation-switch;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			usb_1_ss0_sbu_mux: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;pmic_glink_ss0_sbu&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wcn7850-pmu {</div><div class='add'>+		compatible = "qcom,wcn7850-pmu";</div><div class='add'>+</div><div class='add'>+		vdd-supply = &lt;&amp;vreg_wcn_0p95&gt;;</div><div class='add'>+		vddio-supply = &lt;&amp;vreg_l15b_1p8&gt;;</div><div class='add'>+		vddaon-supply = &lt;&amp;vreg_wcn_0p95&gt;;</div><div class='add'>+		vdddig-supply = &lt;&amp;vreg_wcn_0p95&gt;;</div><div class='add'>+		vddrfa1p2-supply = &lt;&amp;vreg_wcn_1p9&gt;;</div><div class='add'>+		vddrfa1p8-supply = &lt;&amp;vreg_wcn_1p9&gt;;</div><div class='add'>+</div><div class='add'>+		bt-enable-gpios = &lt;&amp;tlmm 116 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		wlan-enable-gpios = &lt;&amp;tlmm 117 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;wcn_bt_en&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			vreg_pmu_rfa_cmn: ldo0 {</div><div class='add'>+				regulator-name = "vreg_pmu_rfa_cmn";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vreg_pmu_aon_0p59: ldo1 {</div><div class='add'>+				regulator-name = "vreg_pmu_aon_0p59";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vreg_pmu_wlcx_0p8: ldo2 {</div><div class='add'>+				regulator-name = "vreg_pmu_wlcx_0p8";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vreg_pmu_wlmx_0p85: ldo3 {</div><div class='add'>+				regulator-name = "vreg_pmu_wlmx_0p85";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vreg_pmu_btcmx_0p85: ldo4 {</div><div class='add'>+				regulator-name = "vreg_pmu_btcmx_0p85";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vreg_pmu_rfa_0p8: ldo5 {</div><div class='add'>+				regulator-name = "vreg_pmu_rfa_0p8";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vreg_pmu_rfa_1p2: ldo6 {</div><div class='add'>+				regulator-name = "vreg_pmu_rfa_1p2";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vreg_pmu_rfa_1p8: ldo7 {</div><div class='add'>+				regulator-name = "vreg_pmu_rfa_1p8";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vreg_pmu_pcie_0p9: ldo8 {</div><div class='add'>+				regulator-name = "vreg_pmu_pcie_0p9";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vreg_pmu_pcie_1p8: ldo9 {</div><div class='add'>+				regulator-name = "vreg_pmu_pcie_1p8";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	typec-mux@8 {</div><div class='add'>+		compatible = "parade,ps8830";</div><div class='add'>+		reg = &lt;0x08&gt;;</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;rpmhcc RPMH_RF_CLK5&gt;;</div><div class='add'>+</div><div class='add'>+		vdd-supply = &lt;&amp;vreg_rtmr2_1p15&gt;;</div><div class='add'>+		vdd33-supply = &lt;&amp;vreg_rtmr2_3p3&gt;;</div><div class='add'>+		vdd33-cap-supply = &lt;&amp;vreg_rtmr2_3p3&gt;;</div><div class='add'>+		vddar-supply = &lt;&amp;vreg_rtmr2_1p15&gt;;</div><div class='add'>+		vddat-supply = &lt;&amp;vreg_rtmr2_1p15&gt;;</div><div class='add'>+		vddio-supply = &lt;&amp;vreg_rtmr2_1p8&gt;;</div><div class='add'>+</div><div class='add'>+		reset-gpios = &lt;&amp;tlmm 185 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;rtmr2_default&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		orientation-switch;</div><div class='add'>+		retimer-switch;</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				retimer_ss2_ss_out: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;pmic_glink_ss2_ss_in&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				retimer_ss2_ss_in: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;usb_1_ss2_qmpphy_out&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@2 {</div><div class='add'>+				reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+				retimer_ss2_con_sbu_out: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;pmic_glink_ss2_con_sbu_in&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c5 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	eusb3_repeater: redriver@47 {</div><div class='add'>+		compatible = "nxp,ptn3222";</div><div class='add'>+		reg = &lt;0x47&gt;;</div><div class='add'>+		#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		vdd3v3-supply = &lt;&amp;vreg_l13b_3p0&gt;;</div><div class='add'>+		vdd1v8-supply = &lt;&amp;vreg_l4b_1p8&gt;;</div><div class='add'>+</div><div class='add'>+		reset-gpios = &lt;&amp;tlmm 6 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;eusb3_reset_n&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eusb5_repeater: redriver@43 {</div><div class='add'>+		compatible = "nxp,ptn3222";</div><div class='add'>+		reg = &lt;0x43&gt;;</div><div class='add'>+		#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		vdd3v3-supply = &lt;&amp;vreg_l13b_3p0&gt;;</div><div class='add'>+		vdd1v8-supply = &lt;&amp;vreg_l4b_1p8&gt;;</div><div class='add'>+</div><div class='add'>+		reset-gpios = &lt;&amp;tlmm 7 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;eusb5_reset_n&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eusb6_repeater: redriver@4f {</div><div class='add'>+		compatible = "nxp,ptn3222";</div><div class='add'>+		reg = &lt;0x4f&gt;;</div><div class='add'>+		#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		vdd3v3-supply = &lt;&amp;vreg_l13b_3p0&gt;;</div><div class='add'>+		vdd1v8-supply = &lt;&amp;vreg_l4b_1p8&gt;;</div><div class='add'>+</div><div class='add'>+		reset-gpios = &lt;&amp;tlmm 184 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;eusb6_reset_n&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c7 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	typec-mux@8 {</div><div class='add'>+		compatible = "parade,ps8830";</div><div class='add'>+		reg = &lt;0x8&gt;;</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;rpmhcc RPMH_RF_CLK4&gt;;</div><div class='add'>+</div><div class='add'>+		vdd-supply = &lt;&amp;vreg_rtmr1_1p15&gt;;</div><div class='add'>+		vdd33-supply = &lt;&amp;vreg_rtmr1_3p3&gt;;</div><div class='add'>+		vdd33-cap-supply = &lt;&amp;vreg_rtmr1_3p3&gt;;</div><div class='add'>+		vddar-supply = &lt;&amp;vreg_rtmr1_1p15&gt;;</div><div class='add'>+		vddat-supply = &lt;&amp;vreg_rtmr1_1p15&gt;;</div><div class='add'>+		vddio-supply = &lt;&amp;vreg_rtmr1_1p8&gt;;</div><div class='add'>+</div><div class='add'>+		reset-gpios = &lt;&amp;tlmm 176 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;rtmr1_default&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		retimer-switch;</div><div class='add'>+		orientation-switch;</div><div class='add'>+</div><div class='add'>+		ports {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			port@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				retimer_ss1_ss_out: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;pmic_glink_ss1_ss_in&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				retimer_ss1_ss_in: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;usb_1_ss1_qmpphy_out&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			port@2 {</div><div class='add'>+				reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+				retimer_ss1_con_sbu_out: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;pmic_glink_ss1_con_sbu_in&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpass_tlmm {</div><div class='add'>+	spkr_0_sd_n_active: spkr-0-sd-n-active-state {</div><div class='add'>+		pins = "gpio12";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;16&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spkr_1_sd_n_active: spkr-1-sd-n-active-state {</div><div class='add'>+		pins = "gpio13";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;16&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spkr_2_sd_n_active: spkr-2-sd-n-active-state {</div><div class='add'>+		pins = "gpio17";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;16&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spkr_3_sd_n_active: spkr-3-sd-n-active-state {</div><div class='add'>+		pins = "gpio18";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;16&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpass_vamacro {</div><div class='add'>+	pinctrl-0 = &lt;&amp;dmic01_default&gt;, &lt;&amp;dmic23_default&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	vdd-micb-supply = &lt;&amp;vreg_l1b_1p8&gt;;</div><div class='add'>+	qcom,dmic-sample-rate = &lt;4800000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdss {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdss_dp0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdss_dp0_out {</div><div class='add'>+	link-frequencies = /bits/ 64 &lt;1620000000 2700000000 5400000000 8100000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdss_dp1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdss_dp1_out {</div><div class='add'>+	link-frequencies = /bits/ 64 &lt;1620000000 2700000000 5400000000 8100000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdss_dp2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdss_dp2_out {</div><div class='add'>+	link-frequencies = /bits/ 64 &lt;1620000000 2700000000 5400000000 8100000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdss_dp3 {</div><div class='add'>+	/delete-property/ #sound-dai-cells;</div><div class='add'>+</div><div class='add'>+	pinctrl-0 = &lt;&amp;edp0_hpd_default&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	aux-bus {</div><div class='add'>+		panel {</div><div class='add'>+			compatible = "edp-panel";</div><div class='add'>+			power-supply = &lt;&amp;vreg_edp_3p3&gt;;</div><div class='add'>+</div><div class='add'>+			port {</div><div class='add'>+				edp_panel_in: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;mdss_dp3_out&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdss_dp3_out {</div><div class='add'>+	data-lanes = &lt;0 1 2 3&gt;;</div><div class='add'>+	link-frequencies = /bits/ 64 &lt;1620000000 2700000000 5400000000 8100000000&gt;;</div><div class='add'>+</div><div class='add'>+	remote-endpoint = &lt;&amp;edp_panel_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdss_dp3_phy {</div><div class='add'>+	vdda-phy-supply = &lt;&amp;vreg_l3j_0p8&gt;;</div><div class='add'>+	vdda-pll-supply = &lt;&amp;vreg_l2j_1p2&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie6a {</div><div class='add'>+	vddpe-3v3-supply = &lt;&amp;vreg_nvme&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8550_gpios {</div><div class='add'>+	rtmr0_default: rtmr0-reset-n-active-state {</div><div class='add'>+		pins = "gpio10";</div><div class='add'>+		function = "normal";</div><div class='add'>+		power-source = &lt;1&gt;; /* 1.8V */</div><div class='add'>+		bias-disable;</div><div class='add'>+		input-disable;</div><div class='add'>+		output-enable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb0_3p3_reg_en: usb0-3p3-reg-en-state {</div><div class='add'>+		pins = "gpio11";</div><div class='add'>+		function = "normal";</div><div class='add'>+		power-source = &lt;1&gt;; /* 1.8V */</div><div class='add'>+		bias-disable;</div><div class='add'>+		input-disable;</div><div class='add'>+		output-enable;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8550ve_9_gpios {</div><div class='add'>+	usb0_1p8_reg_en: usb0-1p8-reg-en-state {</div><div class='add'>+		pins = "gpio8";</div><div class='add'>+		function = "normal";</div><div class='add'>+		power-source = &lt;1&gt;; /* 1.8V */</div><div class='add'>+		bias-disable;</div><div class='add'>+		input-disable;</div><div class='add'>+		output-enable;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pmc8380_5_gpios {</div><div class='add'>+	usb0_pwr_1p15_reg_en: usb0-pwr-1p15-reg-en-state {</div><div class='add'>+		pins = "gpio8";</div><div class='add'>+		function = "normal";</div><div class='add'>+		power-source = &lt;1&gt;; /* 1.8V */</div><div class='add'>+		bias-disable;</div><div class='add'>+		input-disable;</div><div class='add'>+		output-enable;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;smb2360_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;smb2360_0_eusb2_repeater {</div><div class='add'>+	vdd18-supply = &lt;&amp;vreg_l3d_1p8&gt;;</div><div class='add'>+	vdd3-supply = &lt;&amp;vreg_l2b_3p0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;smb2360_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;smb2360_1_eusb2_repeater {</div><div class='add'>+	vdd18-supply = &lt;&amp;vreg_l3d_1p8&gt;;</div><div class='add'>+	vdd3-supply = &lt;&amp;vreg_l14b_3p0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;smb2360_2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;smb2360_2_eusb2_repeater {</div><div class='add'>+	vdd18-supply = &lt;&amp;vreg_l3d_1p8&gt;;</div><div class='add'>+	vdd3-supply = &lt;&amp;vreg_l8b_3p0&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;swr0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pinctrl-0 = &lt;&amp;wsa_swr_active&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	/* WSA8845, Left Woofer */</div><div class='add'>+	left_woofer: speaker@0,0 {</div><div class='add'>+		compatible = "sdw20217020400";</div><div class='add'>+		pinctrl-0 = &lt;&amp;spkr_0_sd_n_active&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		reg = &lt;0 0&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;lpass_tlmm 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		sound-name-prefix = "WooferLeft";</div><div class='add'>+		vdd-1p8-supply = &lt;&amp;vreg_l15b_1p8&gt;;</div><div class='add'>+		vdd-io-supply = &lt;&amp;vreg_l12b_1p2&gt;;</div><div class='add'>+		qcom,port-mapping = &lt;1 2 3 7 10 13&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* WSA8845, Left Tweeter */</div><div class='add'>+	left_tweeter: speaker@0,1 {</div><div class='add'>+		compatible = "sdw20217020400";</div><div class='add'>+		pinctrl-0 = &lt;&amp;spkr_1_sd_n_active&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		reg = &lt;0 1&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;lpass_tlmm 13 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		sound-name-prefix = "TweeterLeft";</div><div class='add'>+		vdd-1p8-supply = &lt;&amp;vreg_l15b_1p8&gt;;</div><div class='add'>+		vdd-io-supply = &lt;&amp;vreg_l12b_1p2&gt;;</div><div class='add'>+		qcom,port-mapping = &lt;4 5 6 7 11 13&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;swr1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* WCD9385 RX */</div><div class='add'>+	wcd_rx: codec@0,4 {</div><div class='add'>+		compatible = "sdw20217010d00";</div><div class='add'>+		reg = &lt;0 4&gt;;</div><div class='add'>+		qcom,rx-port-mapping = &lt;1 2 3 4 5&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;swr2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	/* WCD9385 TX */</div><div class='add'>+	wcd_tx: codec@0,3 {</div><div class='add'>+		compatible = "sdw20217010d00";</div><div class='add'>+		reg = &lt;0 3&gt;;</div><div class='add'>+		qcom,tx-port-mapping = &lt;2 2 3 4&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;swr3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pinctrl-0 = &lt;&amp;wsa2_swr_active&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	/* WSA8845, Right Woofer */</div><div class='add'>+	right_woofer: speaker@0,0 {</div><div class='add'>+		compatible = "sdw20217020400";</div><div class='add'>+		pinctrl-0 = &lt;&amp;spkr_2_sd_n_active&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		reg = &lt;0 0&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;lpass_tlmm 17 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		sound-name-prefix = "WooferRight";</div><div class='add'>+		vdd-1p8-supply = &lt;&amp;vreg_l15b_1p8&gt;;</div><div class='add'>+		vdd-io-supply = &lt;&amp;vreg_l12b_1p2&gt;;</div><div class='add'>+		qcom,port-mapping = &lt;1 2 3 7 10 13&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* WSA8845, Right Tweeter */</div><div class='add'>+	right_tweeter: speaker@0,1 {</div><div class='add'>+		compatible = "sdw20217020400";</div><div class='add'>+		pinctrl-0 = &lt;&amp;spkr_3_sd_n_active&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		reg = &lt;0 1&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;lpass_tlmm 18 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		sound-name-prefix = "TweeterRight";</div><div class='add'>+		vdd-1p8-supply = &lt;&amp;vreg_l15b_1p8&gt;;</div><div class='add'>+		vdd-io-supply = &lt;&amp;vreg_l12b_1p2&gt;;</div><div class='add'>+		qcom,port-mapping = &lt;4 5 6 7 11 13&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tlmm {</div><div class='add'>+	edp_reg_en: edp-reg-en-state {</div><div class='add'>+		pins = "gpio70";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;16&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eusb3_reset_n: eusb3-reset-n-state {</div><div class='add'>+		pins = "gpio6";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+		output-low;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eusb5_reset_n: eusb5-reset-n-state {</div><div class='add'>+		pins = "gpio7";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-pull-up;</div><div class='add'>+		output-low;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eusb6_reset_n: eusb6-reset-n-state {</div><div class='add'>+		pins = "gpio184";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-pull-up;</div><div class='add'>+		output-low;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	nvme_reg_en: nvme-reg-en-state {</div><div class='add'>+		pins = "gpio18";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rtmr1_default: rtmr1-reset-n-active-state {</div><div class='add'>+		pins = "gpio176";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rtmr2_default: rtmr2-reset-n-active-state {</div><div class='add'>+		pins = "gpio185";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb1_pwr_1p15_reg_en: usb1-pwr-1p15-reg-en-state {</div><div class='add'>+		pins = "gpio188";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb1_pwr_1p8_reg_en: usb1-pwr-1p8-reg-en-state {</div><div class='add'>+		pins = "gpio175";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb1_pwr_3p3_reg_en: usb1-pwr-3p3-reg-en-state {</div><div class='add'>+		pins = "gpio186";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb2_pwr_1p15_reg_en: usb2-pwr-1p15-reg-en-state {</div><div class='add'>+		pins = "gpio189";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb2_pwr_1p8_reg_en: usb2-pwr-1p8-reg-en-state {</div><div class='add'>+		pins = "gpio126";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb2_pwr_3p3_reg_en: usb2-pwr-3p3-reg-en-state {</div><div class='add'>+		pins = "gpio187";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb_1_ss0_sbu_default: usb-1-ss0-sbu-state {</div><div class='add'>+		mode-pins {</div><div class='add'>+			pins = "gpio166";</div><div class='add'>+			function = "gpio";</div><div class='add'>+			bias-disable;</div><div class='add'>+			drive-strength = &lt;2&gt;;</div><div class='add'>+			output-high;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		oe-n-pins {</div><div class='add'>+			pins = "gpio168";</div><div class='add'>+			function = "gpio";</div><div class='add'>+			bias-disable;</div><div class='add'>+			drive-strength = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sel-pins {</div><div class='add'>+			pins = "gpio167";</div><div class='add'>+			function = "gpio";</div><div class='add'>+			bias-disable;</div><div class='add'>+			drive-strength = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wcd_default: wcd-reset-n-active-state {</div><div class='add'>+		pins = "gpio191";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;16&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+		output-low;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wcn_bt_en: wcn-bt-en-state {</div><div class='add'>+		pins = "gpio116";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wwan_sw_en: wwan-sw-en-state {</div><div class='add'>+		pins = "gpio221";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;4&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wcn_sw_en: wcn-sw-en-state {</div><div class='add'>+		pins = "gpio214";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Switches USB signal routing between the USB connector and the Wi-Fi card. */</div><div class='add'>+	wcn_usb_sw_n: wcn-usb-sw-n-state {</div><div class='add'>+		pins = "gpio225";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+		output-high;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart14 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "qcom,wcn7850-bt";</div><div class='add'>+		max-speed = &lt;3200000&gt;;</div><div class='add'>+</div><div class='add'>+		vddaon-supply = &lt;&amp;vreg_pmu_aon_0p59&gt;;</div><div class='add'>+		vddwlcx-supply = &lt;&amp;vreg_pmu_wlcx_0p8&gt;;</div><div class='add'>+		vddwlmx-supply = &lt;&amp;vreg_pmu_wlmx_0p85&gt;;</div><div class='add'>+		vddrfacmn-supply = &lt;&amp;vreg_pmu_rfa_cmn&gt;;</div><div class='add'>+		vddrfa0p8-supply = &lt;&amp;vreg_pmu_rfa_0p8&gt;;</div><div class='add'>+		vddrfa1p2-supply = &lt;&amp;vreg_pmu_rfa_1p2&gt;;</div><div class='add'>+		vddrfa1p8-supply = &lt;&amp;vreg_pmu_rfa_1p8&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart21 {</div><div class='add'>+	compatible = "qcom,geni-debug-uart";</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_1_ss0_dwc3_hs {</div><div class='add'>+	remote-endpoint = &lt;&amp;pmic_glink_ss0_hs_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_1_ss0_hsphy {</div><div class='add'>+	phys = &lt;&amp;smb2360_0_eusb2_repeater&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_1_ss0_qmpphy_out {</div><div class='add'>+	remote-endpoint = &lt;&amp;pmic_glink_ss0_ss_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_1_ss1_dwc3_hs {</div><div class='add'>+	remote-endpoint = &lt;&amp;pmic_glink_ss1_hs_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_1_ss1_hsphy {</div><div class='add'>+	phys = &lt;&amp;smb2360_1_eusb2_repeater&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_1_ss1_qmpphy_out {</div><div class='add'>+	remote-endpoint = &lt;&amp;retimer_ss1_ss_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_1_ss2_dwc3_hs {</div><div class='add'>+	remote-endpoint = &lt;&amp;pmic_glink_ss2_hs_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_1_ss2_hsphy {</div><div class='add'>+	phys = &lt;&amp;smb2360_2_eusb2_repeater&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_1_ss2_qmpphy_out {</div><div class='add'>+	remote-endpoint = &lt;&amp;retimer_ss2_ss_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_2_hsphy {</div><div class='add'>+	phys = &lt;&amp;eusb5_repeater&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl-0 = &lt;&amp;wcn_usb_sw_n&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_mp_hsphy0 {</div><div class='add'>+	phys = &lt;&amp;eusb3_repeater&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_mp_hsphy1 {</div><div class='add'>+	phys = &lt;&amp;eusb6_repeater&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi<br/>new file mode 100644<br/>index 000000000000..4a69852e9176<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi</a></div><div class='hunk'>@@ -0,0 +1,618 @@</div><div class='add'>+// SPDX-License-Identifier: BSD-3-Clause</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "hamoa.dtsi"</div><div class='add'>+#include "hamoa-pmics.dtsi"</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/regulator/qcom,rpmh-regulator.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	reserved-memory {</div><div class='add'>+		linux,cma {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			size = &lt;0x0 0x8000000&gt;;</div><div class='add'>+			reusable;</div><div class='add'>+			linux,cma-default;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;apps_rsc {</div><div class='add'>+	/* PMC8380C_B */</div><div class='add'>+	regulators-0 {</div><div class='add'>+		compatible = "qcom,pm8550-rpmh-regulators";</div><div class='add'>+		qcom,pmic-id = "b";</div><div class='add'>+</div><div class='add'>+		vdd-bob1-supply = &lt;&amp;vph_pwr&gt;;</div><div class='add'>+		vdd-bob2-supply = &lt;&amp;vph_pwr&gt;;</div><div class='add'>+		vdd-l1-l4-l10-supply = &lt;&amp;vreg_s4c_1p8&gt;;</div><div class='add'>+		vdd-l2-l13-l14-supply = &lt;&amp;vreg_bob1&gt;;</div><div class='add'>+		vdd-l5-l16-supply = &lt;&amp;vreg_bob1&gt;;</div><div class='add'>+		vdd-l6-l7-supply = &lt;&amp;vreg_bob2&gt;;</div><div class='add'>+		vdd-l8-l9-supply = &lt;&amp;vreg_bob1&gt;;</div><div class='add'>+		vdd-l12-supply = &lt;&amp;vreg_s5j_1p2&gt;;</div><div class='add'>+		vdd-l15-supply = &lt;&amp;vreg_s4c_1p8&gt;;</div><div class='add'>+		vdd-l17-supply = &lt;&amp;vreg_bob2&gt;;</div><div class='add'>+</div><div class='add'>+		vreg_bob1: bob1 {</div><div class='add'>+			regulator-name = "vreg_bob1";</div><div class='add'>+			regulator-min-microvolt = &lt;3008000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;3960000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_bob2: bob2 {</div><div class='add'>+			regulator-name = "vreg_bob2";</div><div class='add'>+			regulator-min-microvolt = &lt;2504000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;3008000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l1b_1p8: ldo1 {</div><div class='add'>+			regulator-name = "vreg_l1b_1p8";</div><div class='add'>+			regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l2b_3p0: ldo2 {</div><div class='add'>+			regulator-name = "vreg_l2b_3p0";</div><div class='add'>+			regulator-min-microvolt = &lt;3072000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;3100000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l4b_1p8: ldo4 {</div><div class='add'>+			regulator-name = "vreg_l4b_1p8";</div><div class='add'>+			regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l5b_3p0: ldo5 {</div><div class='add'>+			regulator-name = "vreg_l5b_3p0";</div><div class='add'>+			regulator-min-microvolt = &lt;3000000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;3000000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l6b_1p8: ldo6 {</div><div class='add'>+			regulator-name = "vreg_l6b_1p8";</div><div class='add'>+			regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;2960000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l7b_2p8: ldo7 {</div><div class='add'>+			regulator-name = "vreg_l7b_2p8";</div><div class='add'>+			regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;2800000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l8b_3p0: ldo8 {</div><div class='add'>+			regulator-name = "vreg_l8b_3p0";</div><div class='add'>+			regulator-min-microvolt = &lt;3072000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;3072000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l9b_2p9: ldo9 {</div><div class='add'>+			regulator-name = "vreg_l9b_2p9";</div><div class='add'>+			regulator-min-microvolt = &lt;2960000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;2960000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l10b_1p8: ldo10 {</div><div class='add'>+			regulator-name = "vreg_l10b_1p8";</div><div class='add'>+			regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l12b_1p2: ldo12 {</div><div class='add'>+			regulator-name = "vreg_l12b_1p2";</div><div class='add'>+			regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-always-on;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l13b_3p0: ldo13 {</div><div class='add'>+			regulator-name = "vreg_l13b_3p0";</div><div class='add'>+			regulator-min-microvolt = &lt;3072000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;3100000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l14b_3p0: ldo14 {</div><div class='add'>+			regulator-name = "vreg_l14b_3p0";</div><div class='add'>+			regulator-min-microvolt = &lt;3072000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;3072000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l15b_1p8: ldo15 {</div><div class='add'>+			regulator-name = "vreg_l15b_1p8";</div><div class='add'>+			regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-always-on;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l16b_2p9: ldo16 {</div><div class='add'>+			regulator-name = "vreg_l16b_2p9";</div><div class='add'>+			regulator-min-microvolt = &lt;2912000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;2912000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l17b_2p5: ldo17 {</div><div class='add'>+			regulator-name = "vreg_l17b_2p5";</div><div class='add'>+			regulator-min-microvolt = &lt;2504000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;2504000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PMC8380VE_C */</div><div class='add'>+	regulators-1 {</div><div class='add'>+		compatible = "qcom,pm8550ve-rpmh-regulators";</div><div class='add'>+		qcom,pmic-id = "c";</div><div class='add'>+</div><div class='add'>+		vdd-l1-supply = &lt;&amp;vreg_s5j_1p2&gt;;</div><div class='add'>+		vdd-l2-supply = &lt;&amp;vreg_s1f_0p7&gt;;</div><div class='add'>+		vdd-l3-supply = &lt;&amp;vreg_s1f_0p7&gt;;</div><div class='add'>+		vdd-s4-supply = &lt;&amp;vph_pwr&gt;;</div><div class='add'>+</div><div class='add'>+		vreg_s4c_1p8: smps4 {</div><div class='add'>+			regulator-name = "vreg_s4c_1p8";</div><div class='add'>+			regulator-min-microvolt = &lt;1856000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;2000000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l1c_1p2: ldo1 {</div><div class='add'>+			regulator-name = "vreg_l1c_1p2";</div><div class='add'>+			regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l2c_0p8: ldo2 {</div><div class='add'>+			regulator-name = "vreg_l2c_0p8";</div><div class='add'>+			regulator-min-microvolt = &lt;880000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;920000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l3c_0p8: ldo3 {</div><div class='add'>+			regulator-name = "vreg_l3c_0p8";</div><div class='add'>+			regulator-min-microvolt = &lt;880000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;920000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PMC8380_D */</div><div class='add'>+	regulators-2 {</div><div class='add'>+		compatible = "qcom,pmc8380-rpmh-regulators";</div><div class='add'>+		qcom,pmic-id = "d";</div><div class='add'>+</div><div class='add'>+		vdd-l1-supply = &lt;&amp;vreg_s1f_0p7&gt;;</div><div class='add'>+		vdd-l2-supply = &lt;&amp;vreg_s1f_0p7&gt;;</div><div class='add'>+		vdd-l3-supply = &lt;&amp;vreg_s4c_1p8&gt;;</div><div class='add'>+		vdd-s1-supply = &lt;&amp;vph_pwr&gt;;</div><div class='add'>+</div><div class='add'>+		vreg_l1d_0p8: ldo1 {</div><div class='add'>+			regulator-name = "vreg_l1d_0p8";</div><div class='add'>+			regulator-min-microvolt = &lt;880000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;920000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l2d_0p9: ldo2 {</div><div class='add'>+			regulator-name = "vreg_l2d_0p9";</div><div class='add'>+			regulator-min-microvolt = &lt;912000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;920000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l3d_1p8: ldo3 {</div><div class='add'>+			regulator-name = "vreg_l3d_1p8";</div><div class='add'>+			regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PMC8380_E */</div><div class='add'>+	regulators-3 {</div><div class='add'>+		compatible = "qcom,pmc8380-rpmh-regulators";</div><div class='add'>+		qcom,pmic-id = "e";</div><div class='add'>+</div><div class='add'>+		vdd-l2-supply = &lt;&amp;vreg_s1f_0p7&gt;;</div><div class='add'>+		vdd-l3-supply = &lt;&amp;vreg_s5j_1p2&gt;;</div><div class='add'>+</div><div class='add'>+		vreg_l2e_0p8: ldo2 {</div><div class='add'>+			regulator-name = "vreg_l2e_0p8";</div><div class='add'>+			regulator-min-microvolt = &lt;880000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;920000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l3e_1p2: ldo3 {</div><div class='add'>+			regulator-name = "vreg_l3e_1p2";</div><div class='add'>+			regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PMC8380_F */</div><div class='add'>+	regulators-4 {</div><div class='add'>+		compatible = "qcom,pmc8380-rpmh-regulators";</div><div class='add'>+		qcom,pmic-id = "f";</div><div class='add'>+</div><div class='add'>+		vdd-l1-supply = &lt;&amp;vreg_s5j_1p2&gt;;</div><div class='add'>+		vdd-l2-supply = &lt;&amp;vreg_s5j_1p2&gt;;</div><div class='add'>+		vdd-l3-supply = &lt;&amp;vreg_s5j_1p2&gt;;</div><div class='add'>+		vdd-s1-supply = &lt;&amp;vph_pwr&gt;;</div><div class='add'>+</div><div class='add'>+		vreg_s1f_0p7: smps1 {</div><div class='add'>+			regulator-name = "vreg_s1f_0p7";</div><div class='add'>+			regulator-min-microvolt = &lt;700000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l1f_1p0: ldo1 {</div><div class='add'>+			regulator-name = "vreg_l1f_1p0";</div><div class='add'>+			regulator-min-microvolt = &lt;1024000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1024000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l2f_1p0: ldo2 {</div><div class='add'>+			regulator-name = "vreg_l2f_1p0";</div><div class='add'>+			regulator-min-microvolt = &lt;1024000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1024000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l3f_1p0: ldo3 {</div><div class='add'>+			regulator-name = "vreg_l3f_1p0";</div><div class='add'>+			regulator-min-microvolt = &lt;1024000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1024000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PMC8380VE_I */</div><div class='add'>+	regulators-6 {</div><div class='add'>+		compatible = "qcom,pm8550ve-rpmh-regulators";</div><div class='add'>+		qcom,pmic-id = "i";</div><div class='add'>+</div><div class='add'>+		vdd-l1-supply = &lt;&amp;vreg_s4c_1p8&gt;;</div><div class='add'>+		vdd-l2-supply = &lt;&amp;vreg_s5j_1p2&gt;;</div><div class='add'>+		vdd-l3-supply = &lt;&amp;vreg_s1f_0p7&gt;;</div><div class='add'>+		vdd-s1-supply = &lt;&amp;vph_pwr&gt;;</div><div class='add'>+		vdd-s2-supply = &lt;&amp;vph_pwr&gt;;</div><div class='add'>+</div><div class='add'>+		vreg_s1i_0p9: smps1 {</div><div class='add'>+			regulator-name = "vreg_s1i_0p9";</div><div class='add'>+			regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;920000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_s2i_1p0: smps2 {</div><div class='add'>+			regulator-name = "vreg_s2i_1p0";</div><div class='add'>+			regulator-min-microvolt = &lt;1000000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l1i_1p8: ldo1 {</div><div class='add'>+			regulator-name = "vreg_l1i_1p8";</div><div class='add'>+			regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l2i_1p2: ldo2 {</div><div class='add'>+			regulator-name = "vreg_l2i_1p2";</div><div class='add'>+			regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l3i_0p8: ldo3 {</div><div class='add'>+			regulator-name = "vreg_l3i_0p8";</div><div class='add'>+			regulator-min-microvolt = &lt;880000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;920000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PMC8380VE_J */</div><div class='add'>+	regulators-7 {</div><div class='add'>+		compatible = "qcom,pm8550ve-rpmh-regulators";</div><div class='add'>+		qcom,pmic-id = "j";</div><div class='add'>+</div><div class='add'>+		vdd-l1-supply = &lt;&amp;vreg_s1f_0p7&gt;;</div><div class='add'>+		vdd-l2-supply = &lt;&amp;vreg_s5j_1p2&gt;;</div><div class='add'>+		vdd-l3-supply = &lt;&amp;vreg_s1f_0p7&gt;;</div><div class='add'>+		vdd-s5-supply = &lt;&amp;vph_pwr&gt;;</div><div class='add'>+</div><div class='add'>+		vreg_s5j_1p2: smps5 {</div><div class='add'>+			regulator-name = "vreg_s5j_1p2";</div><div class='add'>+			regulator-min-microvolt = &lt;1256000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1304000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l1j_0p8: ldo1 {</div><div class='add'>+			regulator-name = "vreg_l1j_0p8";</div><div class='add'>+			regulator-min-microvolt = &lt;880000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;920000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l2j_1p2: ldo2 {</div><div class='add'>+			regulator-name = "vreg_l2j_1p2";</div><div class='add'>+			regulator-min-microvolt = &lt;1256000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1256000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l3j_0p8: ldo3 {</div><div class='add'>+			regulator-name = "vreg_l3j_0p8";</div><div class='add'>+			regulator-min-microvolt = &lt;880000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;920000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iris {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu_zap_shader {</div><div class='add'>+	firmware-name = "qcom/x1e80100/gen70500_zap.mbn";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie4 {</div><div class='add'>+	perst-gpios = &lt;&amp;tlmm 146 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	wake-gpios = &lt;&amp;tlmm 148 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl-0 = &lt;&amp;pcie4_default&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie4_phy {</div><div class='add'>+	vdda-phy-supply = &lt;&amp;vreg_l3i_0p8&gt;;</div><div class='add'>+	vdda-pll-supply = &lt;&amp;vreg_l3e_1p2&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie6a {</div><div class='add'>+	perst-gpios = &lt;&amp;tlmm 152 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	wake-gpios = &lt;&amp;tlmm 154 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl-0 = &lt;&amp;pcie6a_default&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie6a_phy {</div><div class='add'>+	vdda-phy-supply = &lt;&amp;vreg_l1d_0p8&gt;;</div><div class='add'>+	vdda-pll-supply = &lt;&amp;vreg_l2j_1p2&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qupv3_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qupv3_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qupv3_2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;remoteproc_adsp {</div><div class='add'>+	firmware-name = "qcom/x1e80100/adsp.mbn",</div><div class='add'>+			"qcom/x1e80100/adsp_dtb.mbn";</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;remoteproc_cdsp {</div><div class='add'>+	firmware-name = "qcom/x1e80100/cdsp.mbn",</div><div class='add'>+			"qcom/x1e80100/cdsp_dtb.mbn";</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tlmm {</div><div class='add'>+	gpio-reserved-ranges = &lt;34 2&gt;; /* TPM LP &amp; INT */</div><div class='add'>+</div><div class='add'>+	pcie4_default: pcie4-default-state {</div><div class='add'>+		clkreq-n-pins {</div><div class='add'>+			pins = "gpio147";</div><div class='add'>+			function = "pcie4_clk";</div><div class='add'>+			drive-strength = &lt;2&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		perst-n-pins {</div><div class='add'>+			pins = "gpio146";</div><div class='add'>+			function = "gpio";</div><div class='add'>+			drive-strength = &lt;2&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wake-n-pins {</div><div class='add'>+			pins = "gpio148";</div><div class='add'>+			function = "gpio";</div><div class='add'>+			drive-strength = &lt;2&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie6a_default: pcie6a-default-state {</div><div class='add'>+		clkreq-n-pins {</div><div class='add'>+			pins = "gpio153";</div><div class='add'>+			function = "pcie6a_clk";</div><div class='add'>+			drive-strength = &lt;2&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		perst-n-pins {</div><div class='add'>+			pins = "gpio152";</div><div class='add'>+			function = "gpio";</div><div class='add'>+			drive-strength = &lt;2&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wake-n-pins {</div><div class='add'>+			pins = "gpio154";</div><div class='add'>+			function = "gpio";</div><div class='add'>+			drive-strength = &lt;2&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_1_ss0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_1_ss0_dwc3 {</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	usb-role-switch;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_1_ss0_hsphy {</div><div class='add'>+	vdd-supply = &lt;&amp;vreg_l3j_0p8&gt;;</div><div class='add'>+	vdda12-supply = &lt;&amp;vreg_l2j_1p2&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_1_ss0_qmpphy {</div><div class='add'>+	vdda-phy-supply = &lt;&amp;vreg_l2j_1p2&gt;;</div><div class='add'>+	vdda-pll-supply = &lt;&amp;vreg_l1j_0p8&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_1_ss1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_1_ss1_dwc3 {</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	usb-role-switch;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_1_ss1_hsphy {</div><div class='add'>+	vdd-supply = &lt;&amp;vreg_l3j_0p8&gt;;</div><div class='add'>+	vdda12-supply = &lt;&amp;vreg_l2j_1p2&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_1_ss1_qmpphy {</div><div class='add'>+	vdda-phy-supply = &lt;&amp;vreg_l2j_1p2&gt;;</div><div class='add'>+	vdda-pll-supply = &lt;&amp;vreg_l2d_0p9&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_1_ss2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_1_ss2_dwc3 {</div><div class='add'>+	dr_mode = "otg";</div><div class='add'>+	usb-role-switch;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_1_ss2_hsphy {</div><div class='add'>+	vdd-supply = &lt;&amp;vreg_l3j_0p8&gt;;</div><div class='add'>+	vdda12-supply = &lt;&amp;vreg_l2j_1p2&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_1_ss2_qmpphy {</div><div class='add'>+	vdda-phy-supply = &lt;&amp;vreg_l2j_1p2&gt;;</div><div class='add'>+	vdda-pll-supply = &lt;&amp;vreg_l2d_0p9&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_2_dwc3 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_2_hsphy {</div><div class='add'>+	vdd-supply = &lt;&amp;vreg_l2e_0p8&gt;;</div><div class='add'>+	vdda12-supply = &lt;&amp;vreg_l3e_1p2&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_mp {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_mp_hsphy0 {</div><div class='add'>+	vdd-supply = &lt;&amp;vreg_l2e_0p8&gt;;</div><div class='add'>+	vdda12-supply = &lt;&amp;vreg_l3e_1p2&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_mp_hsphy1 {</div><div class='add'>+	vdd-supply = &lt;&amp;vreg_l2e_0p8&gt;;</div><div class='add'>+	vdda12-supply = &lt;&amp;vreg_l3e_1p2&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_mp_qmpphy0 {</div><div class='add'>+	vdda-phy-supply = &lt;&amp;vreg_l3e_1p2&gt;;</div><div class='add'>+	vdda-pll-supply = &lt;&amp;vreg_l3c_0p8&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_mp_qmpphy1 {</div><div class='add'>+	vdda-phy-supply = &lt;&amp;vreg_l3e_1p2&gt;;</div><div class='add'>+	vdda-pll-supply = &lt;&amp;vreg_l3c_0p8&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi b/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi<br/>new file mode 100644<br/>index 000000000000..6a31a0adf8be<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi</a></div><div class='hunk'>@@ -0,0 +1,569 @@</div><div class='add'>+// SPDX-License-Identifier: BSD-3-Clause</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2024, Linaro Limited</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/linux-event-codes.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/spmi/spmi.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	thermal-zones {</div><div class='add'>+		pm8550-thermal {</div><div class='add'>+			polling-delay-passive = &lt;100&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;pm8550_temp_alarm&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip0 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pm8550ve-2-thermal {</div><div class='add'>+			polling-delay-passive = &lt;100&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;pm8550ve_2_temp_alarm&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip0 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmc8380-3-thermal {</div><div class='add'>+			polling-delay-passive = &lt;100&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;pmc8380_3_temp_alarm&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip0 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmc8380-4-thermal {</div><div class='add'>+			polling-delay-passive = &lt;100&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;pmc8380_4_temp_alarm&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip0 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmc8380-5-thermal {</div><div class='add'>+			polling-delay-passive = &lt;100&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;pmc8380_5_temp_alarm&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip0 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmc8380_6_thermal: pmc8380-6-thermal {</div><div class='add'>+			polling-delay-passive = &lt;100&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;pmc8380_6_temp_alarm&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip0 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pm8550ve-8-thermal {</div><div class='add'>+			polling-delay-passive = &lt;100&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;pm8550ve_8_temp_alarm&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip0 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pm8550ve-9-thermal {</div><div class='add'>+			polling-delay-passive = &lt;100&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;pm8550ve_9_temp_alarm&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip0 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pm8010-thermal {</div><div class='add'>+			polling-delay-passive = &lt;100&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;pm8010_temp_alarm&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip0 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spmi_bus0 {</div><div class='add'>+	/* PMK8380 */</div><div class='add'>+	pmk8550: pmic@0 {</div><div class='add'>+		compatible = "qcom,pm8550", "qcom,spmi-pmic";</div><div class='add'>+		reg = &lt;0x0 SPMI_USID&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		pmk8550_pon: pon@1300 {</div><div class='add'>+			compatible = "qcom,pmk8350-pon";</div><div class='add'>+			reg = &lt;0x1300&gt;, &lt;0x800&gt;;</div><div class='add'>+			reg-names = "hlos", "pbs";</div><div class='add'>+</div><div class='add'>+			pon_pwrkey: pwrkey {</div><div class='add'>+				compatible = "qcom,pmk8350-pwrkey";</div><div class='add'>+				interrupts = &lt;0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH&gt;;</div><div class='add'>+				linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pon_resin: resin {</div><div class='add'>+				compatible = "qcom,pmk8350-resin";</div><div class='add'>+				interrupts = &lt;0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmk8550_rtc: rtc@6100 {</div><div class='add'>+			compatible = "qcom,pmk8350-rtc";</div><div class='add'>+			reg = &lt;0x6100&gt;, &lt;0x6200&gt;;</div><div class='add'>+			reg-names = "rtc", "alarm";</div><div class='add'>+			interrupts = &lt;0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			qcom,no-alarm; /* alarm owned by ADSP */</div><div class='add'>+			qcom,uefi-rtc-info;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmk8550_sdam_2: nvram@7100 {</div><div class='add'>+			compatible = "qcom,spmi-sdam";</div><div class='add'>+			reg = &lt;0x7100&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges = &lt;0 0x7100 0x100&gt;;</div><div class='add'>+</div><div class='add'>+			reboot_reason: reboot-reason@48 {</div><div class='add'>+				reg = &lt;0x48 0x1&gt;;</div><div class='add'>+				bits = &lt;1 7&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmk8550_sdam_15: nvram@7e00 {</div><div class='add'>+			compatible = "qcom,spmi-sdam";</div><div class='add'>+			reg = &lt;0x7e00&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges = &lt;0 0x7e00 0x100&gt;;</div><div class='add'>+</div><div class='add'>+			charge_limit_en: charge-limit-en@73 {</div><div class='add'>+				reg = &lt;0x73 0x1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			charge_limit_end: charge-limit-end@75 {</div><div class='add'>+				reg = &lt;0x75 0x1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			charge_limit_delta: charge-limit-delta@76 {</div><div class='add'>+				reg = &lt;0x76 0x1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmk8550_gpios: gpio@8800 {</div><div class='add'>+			compatible = "qcom,pmk8550-gpio", "qcom,spmi-gpio";</div><div class='add'>+			reg = &lt;0xb800&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			gpio-ranges = &lt;&amp;pmk8550_gpios 0 0 6&gt;;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmk8550_pwm: pwm {</div><div class='add'>+			compatible = "qcom,pmk8550-pwm";</div><div class='add'>+</div><div class='add'>+			#pwm-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PMC8380C */</div><div class='add'>+	pm8550: pmic@1 {</div><div class='add'>+		compatible = "qcom,pm8550", "qcom,spmi-pmic";</div><div class='add'>+		reg = &lt;0x1 SPMI_USID&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		pm8550_temp_alarm: temp-alarm@a00 {</div><div class='add'>+			compatible = "qcom,spmi-temp-alarm";</div><div class='add'>+			reg = &lt;0xa00&gt;;</div><div class='add'>+			interrupts = &lt;0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH&gt;;</div><div class='add'>+			#thermal-sensor-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pm8550_gpios: gpio@8800 {</div><div class='add'>+			compatible = "qcom,pm8550-gpio", "qcom,spmi-gpio";</div><div class='add'>+			reg = &lt;0x8800&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			gpio-ranges = &lt;&amp;pm8550_gpios 0 0 12&gt;;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pm8550_flash: led-controller@ee00 {</div><div class='add'>+			compatible = "qcom,pm8550-flash-led", "qcom,spmi-flash-led";</div><div class='add'>+			reg = &lt;0xee00&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pm8550_pwm: pwm {</div><div class='add'>+			compatible = "qcom,pm8550-pwm", "qcom,pm8350c-pwm";</div><div class='add'>+			#pwm-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PMC8380VE */</div><div class='add'>+	pm8550ve_2: pmic@2 {</div><div class='add'>+		compatible = "qcom,pm8550", "qcom,spmi-pmic";</div><div class='add'>+		reg = &lt;0x2 SPMI_USID&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		pm8550ve_2_temp_alarm: temp-alarm@a00 {</div><div class='add'>+			compatible = "qcom,spmi-temp-alarm";</div><div class='add'>+			reg = &lt;0xa00&gt;;</div><div class='add'>+			interrupts = &lt;0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH&gt;;</div><div class='add'>+			#thermal-sensor-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pm8550ve_2_gpios: gpio@8800 {</div><div class='add'>+			compatible = "qcom,pm8550ve-gpio", "qcom,spmi-gpio";</div><div class='add'>+			reg = &lt;0x8800&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			gpio-ranges = &lt;&amp;pm8550ve_2_gpios 0 0 8&gt;;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PMC8380 is actually not a PM8550 series rebrand */</div><div class='add'>+	pmc8380_3: pmic@3 {</div><div class='add'>+		compatible = "qcom,pmc8380", "qcom,spmi-pmic";</div><div class='add'>+		reg = &lt;0x3 SPMI_USID&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		pmc8380_3_temp_alarm: temp-alarm@a00 {</div><div class='add'>+			compatible = "qcom,spmi-temp-alarm";</div><div class='add'>+			reg = &lt;0xa00&gt;;</div><div class='add'>+			interrupts = &lt;0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH&gt;;</div><div class='add'>+			#thermal-sensor-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmc8380_3_gpios: gpio@8800 {</div><div class='add'>+			compatible = "qcom,pmc8380-gpio", "qcom,spmi-gpio";</div><div class='add'>+			reg = &lt;0x8800&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			gpio-ranges = &lt;&amp;pmc8380_3_gpios 0 0 10&gt;;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmc8380_4: pmic@4 {</div><div class='add'>+		compatible = "qcom,pmc8380", "qcom,spmi-pmic";</div><div class='add'>+		reg = &lt;0x4 SPMI_USID&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		pmc8380_4_temp_alarm: temp-alarm@a00 {</div><div class='add'>+			compatible = "qcom,spmi-temp-alarm";</div><div class='add'>+			reg = &lt;0xa00&gt;;</div><div class='add'>+			interrupts = &lt;0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH&gt;;</div><div class='add'>+			#thermal-sensor-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmc8380_4_gpios: gpio@8800 {</div><div class='add'>+			compatible = "qcom,pmc8380-gpio", "qcom,spmi-gpio";</div><div class='add'>+			reg = &lt;0x8800&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			gpio-ranges = &lt;&amp;pmc8380_4_gpios 0 0 10&gt;;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmc8380_5: pmic@5 {</div><div class='add'>+		compatible = "qcom,pmc8380", "qcom,spmi-pmic";</div><div class='add'>+		reg = &lt;0x5 SPMI_USID&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		pmc8380_5_temp_alarm: temp-alarm@a00 {</div><div class='add'>+			compatible = "qcom,spmi-temp-alarm";</div><div class='add'>+			reg = &lt;0xa00&gt;;</div><div class='add'>+			interrupts = &lt;0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH&gt;;</div><div class='add'>+			#thermal-sensor-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmc8380_5_gpios: gpio@8800 {</div><div class='add'>+			compatible = "qcom,pmc8380-gpio", "qcom,spmi-gpio";</div><div class='add'>+			reg = &lt;0x8800&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			gpio-ranges = &lt;&amp;pmc8380_5_gpios 0 0 10&gt;;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmc8380_6: pmic@6 {</div><div class='add'>+		compatible = "qcom,pmc8380", "qcom,spmi-pmic";</div><div class='add'>+		reg = &lt;0x6 SPMI_USID&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		pmc8380_6_temp_alarm: temp-alarm@a00 {</div><div class='add'>+			compatible = "qcom,spmi-temp-alarm";</div><div class='add'>+			reg = &lt;0xa00&gt;;</div><div class='add'>+			interrupts = &lt;0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH&gt;;</div><div class='add'>+			#thermal-sensor-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmc8380_6_gpios: gpio@8800 {</div><div class='add'>+			compatible = "qcom,pmc8380-gpio", "qcom,spmi-gpio";</div><div class='add'>+			reg = &lt;0x8800&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			gpio-ranges = &lt;&amp;pmc8380_6_gpios 0 0 10&gt;;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PMC8380VE */</div><div class='add'>+	pm8550ve_8: pmic@8 {</div><div class='add'>+		compatible = "qcom,pm8550", "qcom,spmi-pmic";</div><div class='add'>+		reg = &lt;0x8 SPMI_USID&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		pm8550ve_8_temp_alarm: temp-alarm@a00 {</div><div class='add'>+			compatible = "qcom,spmi-temp-alarm";</div><div class='add'>+			reg = &lt;0xa00&gt;;</div><div class='add'>+			interrupts = &lt;0x8 0xa 0x0 IRQ_TYPE_EDGE_BOTH&gt;;</div><div class='add'>+			#thermal-sensor-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pm8550ve_8_gpios: gpio@8800 {</div><div class='add'>+			compatible = "qcom,pm8550ve-gpio", "qcom,spmi-gpio";</div><div class='add'>+			reg = &lt;0x8800&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			gpio-ranges = &lt;&amp;pm8550ve_8_gpios 0 0 8&gt;;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* PMC8380VE */</div><div class='add'>+	pm8550ve_9: pmic@9 {</div><div class='add'>+		compatible = "qcom,pm8550", "qcom,spmi-pmic";</div><div class='add'>+		reg = &lt;0x9 SPMI_USID&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		pm8550ve_9_temp_alarm: temp-alarm@a00 {</div><div class='add'>+			compatible = "qcom,spmi-temp-alarm";</div><div class='add'>+			reg = &lt;0xa00&gt;;</div><div class='add'>+			interrupts = &lt;0x9 0xa 0x0 IRQ_TYPE_EDGE_BOTH&gt;;</div><div class='add'>+			#thermal-sensor-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pm8550ve_9_gpios: gpio@8800 {</div><div class='add'>+			compatible = "qcom,pm8550ve-gpio", "qcom,spmi-gpio";</div><div class='add'>+			reg = &lt;0x8800&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			gpio-ranges = &lt;&amp;pm8550ve_9_gpios 0 0 8&gt;;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pm8010: pmic@c {</div><div class='add'>+		compatible = "qcom,pm8010", "qcom,spmi-pmic";</div><div class='add'>+		reg = &lt;0xc SPMI_USID&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		status = "disabled";</div><div class='add'>+</div><div class='add'>+		pm8010_temp_alarm: temp-alarm@2400 {</div><div class='add'>+			compatible = "qcom,spmi-temp-alarm";</div><div class='add'>+			reg = &lt;0x2400&gt;;</div><div class='add'>+			interrupts = &lt;0xc 0x24 0x0 IRQ_TYPE_EDGE_BOTH&gt;;</div><div class='add'>+			#thermal-sensor-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spmi_bus1 {</div><div class='add'>+	smb2360_0: pmic@7 {</div><div class='add'>+		compatible = "qcom,smb2360", "qcom,spmi-pmic";</div><div class='add'>+		reg = &lt;0x7 SPMI_USID&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		status = "disabled";</div><div class='add'>+</div><div class='add'>+		smb2360_0_eusb2_repeater: phy@fd00 {</div><div class='add'>+			compatible = "qcom,smb2360-eusb2-repeater";</div><div class='add'>+			reg = &lt;0xfd00&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	smb2360_1: pmic@a {</div><div class='add'>+		compatible = "qcom,smb2360", "qcom,spmi-pmic";</div><div class='add'>+		reg = &lt;0xa SPMI_USID&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		status = "disabled";</div><div class='add'>+</div><div class='add'>+		smb2360_1_eusb2_repeater: phy@fd00 {</div><div class='add'>+			compatible = "qcom,smb2360-eusb2-repeater";</div><div class='add'>+			reg = &lt;0xfd00&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	smb2360_2: pmic@b {</div><div class='add'>+		compatible = "qcom,smb2360", "qcom,spmi-pmic";</div><div class='add'>+		reg = &lt;0xb SPMI_USID&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		status = "disabled";</div><div class='add'>+</div><div class='add'>+		smb2360_2_eusb2_repeater: phy@fd00 {</div><div class='add'>+			compatible = "qcom,smb2360-eusb2-repeater";</div><div class='add'>+			reg = &lt;0xfd00&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	smb2360_3: pmic@c {</div><div class='add'>+		compatible = "qcom,smb2360", "qcom,spmi-pmic";</div><div class='add'>+		reg = &lt;0xc SPMI_USID&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		status = "disabled";</div><div class='add'>+</div><div class='add'>+		smb2360_3_eusb2_repeater: phy@fd00 {</div><div class='add'>+			compatible = "qcom,smb2360-eusb2-repeater";</div><div class='add'>+			reg = &lt;0xfd00&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi<br/>new file mode 100644<br/>index 000000000000..a17900eacb20<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/hamoa.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/hamoa.dtsi</a></div><div class='hunk'>@@ -0,0 +1,9629 @@</div><div class='add'>+// SPDX-License-Identifier: BSD-3-Clause</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,rpmh.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,sc8280xp-lpasscc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,sm8450-videocc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,x1e80100-dispcc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,x1e80100-gcc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,x1e80100-gpucc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,x1e80100-tcsr.h&gt;</div><div class='add'>+#include &lt;dt-bindings/dma/qcom-gpi.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interconnect/qcom,icc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interconnect/qcom,x1e80100-rpmh.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/mailbox/qcom-ipcc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/phy/phy-qcom-qmp.h&gt;</div><div class='add'>+#include &lt;dt-bindings/power/qcom,rpmhpd.h&gt;</div><div class='add'>+#include &lt;dt-bindings/power/qcom-rpmpd.h&gt;</div><div class='add'>+#include &lt;dt-bindings/soc/qcom,gpr.h&gt;</div><div class='add'>+#include &lt;dt-bindings/soc/qcom,rpmh-rsc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/qcom,q6dsp-lpass-ports.h&gt;</div><div class='add'>+#include &lt;dt-bindings/thermal/thermal.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	interrupt-parent = &lt;&amp;intc&gt;;</div><div class='add'>+</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	chosen { };</div><div class='add'>+</div><div class='add'>+	clocks {</div><div class='add'>+		xo_board: xo-board {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			clock-frequency = &lt;76800000&gt;;</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sleep_clk: sleep-clk {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			clock-frequency = &lt;32764&gt;;</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		bi_tcxo_div2: bi-tcxo-div2-clk {</div><div class='add'>+			compatible = "fixed-factor-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;;</div><div class='add'>+			clock-mult = &lt;1&gt;;</div><div class='add'>+			clock-div = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {</div><div class='add'>+			compatible = "fixed-factor-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_CXO_CLK_A&gt;;</div><div class='add'>+			clock-mult = &lt;1&gt;;</div><div class='add'>+			clock-div = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "qcom,oryon";</div><div class='add'>+			reg = &lt;0x0 0x0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cpu_pd0&gt;, &lt;&amp;scmi_dvfs 0&gt;;</div><div class='add'>+			power-domain-names = "psci", "perf";</div><div class='add'>+</div><div class='add'>+			l2_0: l2-cache {</div><div class='add'>+				compatible = "cache";</div><div class='add'>+				cache-level = &lt;2&gt;;</div><div class='add'>+				cache-unified;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@100 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "qcom,oryon";</div><div class='add'>+			reg = &lt;0x0 0x100&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cpu_pd1&gt;, &lt;&amp;scmi_dvfs 0&gt;;</div><div class='add'>+			power-domain-names = "psci", "perf";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@200 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "qcom,oryon";</div><div class='add'>+			reg = &lt;0x0 0x200&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cpu_pd2&gt;, &lt;&amp;scmi_dvfs 0&gt;;</div><div class='add'>+			power-domain-names = "psci", "perf";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@300 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "qcom,oryon";</div><div class='add'>+			reg = &lt;0x0 0x300&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cpu_pd3&gt;, &lt;&amp;scmi_dvfs 0&gt;;</div><div class='add'>+			power-domain-names = "psci", "perf";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu4: cpu@10000 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "qcom,oryon";</div><div class='add'>+			reg = &lt;0x0 0x10000&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_1&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cpu_pd4&gt;, &lt;&amp;scmi_dvfs 1&gt;;</div><div class='add'>+			power-domain-names = "psci", "perf";</div><div class='add'>+</div><div class='add'>+			l2_1: l2-cache {</div><div class='add'>+				compatible = "cache";</div><div class='add'>+				cache-level = &lt;2&gt;;</div><div class='add'>+				cache-unified;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu5: cpu@10100 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "qcom,oryon";</div><div class='add'>+			reg = &lt;0x0 0x10100&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_1&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cpu_pd5&gt;, &lt;&amp;scmi_dvfs 1&gt;;</div><div class='add'>+			power-domain-names = "psci", "perf";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu6: cpu@10200 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "qcom,oryon";</div><div class='add'>+			reg = &lt;0x0 0x10200&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_1&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cpu_pd6&gt;, &lt;&amp;scmi_dvfs 1&gt;;</div><div class='add'>+			power-domain-names = "psci", "perf";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu7: cpu@10300 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "qcom,oryon";</div><div class='add'>+			reg = &lt;0x0 0x10300&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_1&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cpu_pd7&gt;, &lt;&amp;scmi_dvfs 1&gt;;</div><div class='add'>+			power-domain-names = "psci", "perf";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu8: cpu@20000 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "qcom,oryon";</div><div class='add'>+			reg = &lt;0x0 0x20000&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_2&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cpu_pd8&gt;, &lt;&amp;scmi_dvfs 2&gt;;</div><div class='add'>+			power-domain-names = "psci", "perf";</div><div class='add'>+</div><div class='add'>+			l2_2: l2-cache {</div><div class='add'>+				compatible = "cache";</div><div class='add'>+				cache-level = &lt;2&gt;;</div><div class='add'>+				cache-unified;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu9: cpu@20100 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "qcom,oryon";</div><div class='add'>+			reg = &lt;0x0 0x20100&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_2&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cpu_pd9&gt;, &lt;&amp;scmi_dvfs 2&gt;;</div><div class='add'>+			power-domain-names = "psci", "perf";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu10: cpu@20200 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "qcom,oryon";</div><div class='add'>+			reg = &lt;0x0 0x20200&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_2&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cpu_pd10&gt;, &lt;&amp;scmi_dvfs 2&gt;;</div><div class='add'>+			power-domain-names = "psci", "perf";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu11: cpu@20300 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "qcom,oryon";</div><div class='add'>+			reg = &lt;0x0 0x20300&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_2&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cpu_pd11&gt;, &lt;&amp;scmi_dvfs 2&gt;;</div><div class='add'>+			power-domain-names = "psci", "perf";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu-map {</div><div class='add'>+			cluster0 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu2&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu3&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cluster1 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu4&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu5&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu6&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu7&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cpu_map_cluster2: cluster2 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu8&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu9&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu10&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu11&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		idle-states {</div><div class='add'>+			entry-method = "psci";</div><div class='add'>+</div><div class='add'>+			cluster_c4: cpu-sleep-0 {</div><div class='add'>+				compatible = "arm,idle-state";</div><div class='add'>+				idle-state-name = "ret";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x00000004&gt;;</div><div class='add'>+				entry-latency-us = &lt;180&gt;;</div><div class='add'>+				exit-latency-us = &lt;500&gt;;</div><div class='add'>+				min-residency-us = &lt;600&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		domain-idle-states {</div><div class='add'>+			cluster_cl4: cluster-sleep-0 {</div><div class='add'>+				compatible = "domain-idle-state";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x01000044&gt;;</div><div class='add'>+				entry-latency-us = &lt;350&gt;;</div><div class='add'>+				exit-latency-us = &lt;500&gt;;</div><div class='add'>+				min-residency-us = &lt;2500&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cluster_cl5: cluster-sleep-1 {</div><div class='add'>+				compatible = "domain-idle-state";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x01000054&gt;;</div><div class='add'>+				entry-latency-us = &lt;2200&gt;;</div><div class='add'>+				exit-latency-us = &lt;4000&gt;;</div><div class='add'>+				min-residency-us = &lt;7000&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dummy-sink {</div><div class='add'>+		compatible = "arm,coresight-dummy-sink";</div><div class='add'>+</div><div class='add'>+		in-ports {</div><div class='add'>+			port {</div><div class='add'>+				eud_in: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;swao_rep_out1&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	firmware {</div><div class='add'>+		scm: scm {</div><div class='add'>+			compatible = "qcom,scm-x1e80100", "qcom,scm";</div><div class='add'>+			interconnects = &lt;&amp;aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+			qcom,dload-mode = &lt;&amp;tcsr 0x19000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		scmi {</div><div class='add'>+			compatible = "arm,scmi";</div><div class='add'>+			mboxes = &lt;&amp;cpucp_mbox 0&gt;, &lt;&amp;cpucp_mbox 2&gt;;</div><div class='add'>+			mbox-names = "tx", "rx";</div><div class='add'>+			shmem = &lt;&amp;cpu_scp_lpri0&gt;, &lt;&amp;cpu_scp_lpri1&gt;;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			scmi_dvfs: protocol@13 {</div><div class='add'>+				reg = &lt;0x13&gt;;</div><div class='add'>+				#power-domain-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_virt: interconnect-0 {</div><div class='add'>+		compatible = "qcom,x1e80100-clk-virt";</div><div class='add'>+		#interconnect-cells = &lt;2&gt;;</div><div class='add'>+		qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mc_virt: interconnect-1 {</div><div class='add'>+		compatible = "qcom,x1e80100-mc-virt";</div><div class='add'>+		#interconnect-cells = &lt;2&gt;;</div><div class='add'>+		qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@80000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		/* We expect the bootloader to fill in the size */</div><div class='add'>+		reg = &lt;0 0x80000000 0 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu {</div><div class='add'>+		compatible = "arm,armv8-pmuv3";</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-1.0";</div><div class='add'>+		method = "smc";</div><div class='add'>+</div><div class='add'>+		cpu_pd0: power-domain-cpu0 {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cluster_pd0&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;cluster_c4&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_pd1: power-domain-cpu1 {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cluster_pd0&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;cluster_c4&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_pd2: power-domain-cpu2 {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cluster_pd0&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;cluster_c4&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_pd3: power-domain-cpu3 {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cluster_pd0&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;cluster_c4&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_pd4: power-domain-cpu4 {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cluster_pd1&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;cluster_c4&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_pd5: power-domain-cpu5 {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cluster_pd1&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;cluster_c4&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_pd6: power-domain-cpu6 {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cluster_pd1&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;cluster_c4&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_pd7: power-domain-cpu7 {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cluster_pd1&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;cluster_c4&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_pd8: power-domain-cpu8 {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cluster_pd2&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;cluster_c4&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_pd9: power-domain-cpu9 {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cluster_pd2&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;cluster_c4&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_pd10: power-domain-cpu10 {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cluster_pd2&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;cluster_c4&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_pd11: power-domain-cpu11 {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cluster_pd2&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;cluster_c4&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cluster_pd0: power-domain-cpu-cluster0 {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;cluster_cl4&gt;, &lt;&amp;cluster_cl5&gt;;</div><div class='add'>+			power-domains = &lt;&amp;system_pd&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cluster_pd1: power-domain-cpu-cluster1 {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;cluster_cl4&gt;, &lt;&amp;cluster_cl5&gt;;</div><div class='add'>+			power-domains = &lt;&amp;system_pd&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cluster_pd2: power-domain-cpu-cluster2 {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;cluster_cl4&gt;, &lt;&amp;cluster_cl5&gt;;</div><div class='add'>+			power-domains = &lt;&amp;system_pd&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		system_pd: power-domain-system {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			/* TODO: system-wide idle states */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		gunyah_hyp_mem: gunyah-hyp@80000000 {</div><div class='add'>+			reg = &lt;0x0 0x80000000 0x0 0x800000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		hyp_elf_package_mem: hyp-elf-package@80800000 {</div><div class='add'>+			reg = &lt;0x0 0x80800000 0x0 0x200000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ncc_mem: ncc@80a00000 {</div><div class='add'>+			reg = &lt;0x0 0x80a00000 0x0 0x400000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpucp_log_mem: cpucp-log@80e00000 {</div><div class='add'>+			reg = &lt;0x0 0x80e00000 0x0 0x40000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpucp_mem: cpucp@80e40000 {</div><div class='add'>+			reg = &lt;0x0 0x80e40000 0x0 0x540000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		reserved-region@81380000 {</div><div class='add'>+			reg = &lt;0x0 0x81380000 0x0 0x80000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tags_mem: tags-region@81400000 {</div><div class='add'>+			reg = &lt;0x0 0x81400000 0x0 0x1a0000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		xbl_dtlog_mem: xbl-dtlog@81a00000 {</div><div class='add'>+			reg = &lt;0x0 0x81a00000 0x0 0x40000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		xbl_ramdump_mem: xbl-ramdump@81a40000 {</div><div class='add'>+			reg = &lt;0x0 0x81a40000 0x0 0x1c0000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aop_image_mem: aop-image@81c00000 {</div><div class='add'>+			reg = &lt;0x0 0x81c00000 0x0 0x60000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aop_cmd_db_mem: aop-cmd-db@81c60000 {</div><div class='add'>+			compatible = "qcom,cmd-db";</div><div class='add'>+			reg = &lt;0x0 0x81c60000 0x0 0x20000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aop_config_mem: aop-config@81c80000 {</div><div class='add'>+			reg = &lt;0x0 0x81c80000 0x0 0x20000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tme_crash_dump_mem: tme-crash-dump@81ca0000 {</div><div class='add'>+			reg = &lt;0x0 0x81ca0000 0x0 0x40000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tme_log_mem: tme-log@81ce0000 {</div><div class='add'>+			reg = &lt;0x0 0x81ce0000 0x0 0x4000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uefi_log_mem: uefi-log@81ce4000 {</div><div class='add'>+			reg = &lt;0x0 0x81ce4000 0x0 0x10000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		secdata_apss_mem: secdata-apss@81cff000 {</div><div class='add'>+			reg = &lt;0x0 0x81cff000 0x0 0x1000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pdp_ns_shared_mem: pdp-ns-shared@81e00000 {</div><div class='add'>+			reg = &lt;0x0 0x81e00000 0x0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu_prr_mem: gpu-prr@81f00000 {</div><div class='add'>+			reg = &lt;0x0 0x81f00000 0x0 0x10000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpm_control_mem: tpm-control@81f10000 {</div><div class='add'>+			reg = &lt;0x0 0x81f10000 0x0 0x10000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_ucsi_shared_mem: usb-ucsi-shared@81f20000 {</div><div class='add'>+			reg = &lt;0x0 0x81f20000 0x0 0x10000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pld_pep_mem: pld-pep@81f30000 {</div><div class='add'>+			reg = &lt;0x0 0x81f30000 0x0 0x6000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pld_gmu_mem: pld-gmu@81f36000 {</div><div class='add'>+			reg = &lt;0x0 0x81f36000 0x0 0x1000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pld_pdp_mem: pld-pdp@81f37000 {</div><div class='add'>+			reg = &lt;0x0 0x81f37000 0x0 0x1000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tz_stat_mem: tz-stat@82700000 {</div><div class='add'>+			reg = &lt;0x0 0x82700000 0x0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		xbl_tmp_buffer_mem: xbl-tmp-buffer@82800000 {</div><div class='add'>+			reg = &lt;0x0 0x82800000 0x0 0xc00000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@84b00000 {</div><div class='add'>+			reg = &lt;0x0 0x84b00000 0x0 0x800000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spu_secure_shared_memory_mem: spu-secure-shared-memory@85300000 {</div><div class='add'>+			reg = &lt;0x0 0x85300000 0x0 0x80000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		adsp_boot_dtb_mem: adsp-boot-dtb@866c0000 {</div><div class='add'>+			reg = &lt;0x0 0x866c0000 0x0 0x40000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spss_region_mem: spss-region@86700000 {</div><div class='add'>+			reg = &lt;0x0 0x86700000 0x0 0x400000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		adsp_boot_mem: adsp-boot@86b00000 {</div><div class='add'>+			reg = &lt;0x0 0x86b00000 0x0 0xc00000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		video_mem: video@87700000 {</div><div class='add'>+			reg = &lt;0x0 0x87700000 0x0 0x700000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		adspslpi_mem: adspslpi@87e00000 {</div><div class='add'>+			reg = &lt;0x0 0x87e00000 0x0 0x3a00000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		q6_adsp_dtb_mem: q6-adsp-dtb@8b800000 {</div><div class='add'>+			reg = &lt;0x0 0x8b800000 0x0 0x80000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cdsp_mem: cdsp@8b900000 {</div><div class='add'>+			reg = &lt;0x0 0x8b900000 0x0 0x2000000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		q6_cdsp_dtb_mem: q6-cdsp-dtb@8d900000 {</div><div class='add'>+			reg = &lt;0x0 0x8d900000 0x0 0x80000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu_microcode_mem: gpu-microcode@8d9fe000 {</div><div class='add'>+			reg = &lt;0x0 0x8d9fe000 0x0 0x2000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cvp_mem: cvp@8da00000 {</div><div class='add'>+			reg = &lt;0x0 0x8da00000 0x0 0x700000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		camera_mem: camera@8e100000 {</div><div class='add'>+			reg = &lt;0x0 0x8e100000 0x0 0x800000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		av1_encoder_mem: av1-encoder@8e900000 {</div><div class='add'>+			reg = &lt;0x0 0x8e900000 0x0 0x700000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		reserved-region@8f000000 {</div><div class='add'>+			reg = &lt;0x0 0x8f000000 0x0 0xa00000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wpss_mem: wpss@8fa00000 {</div><div class='add'>+			reg = &lt;0x0 0x8fa00000 0x0 0x1900000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		q6_wpss_dtb_mem: q6-wpss-dtb@91300000 {</div><div class='add'>+			reg = &lt;0x0 0x91300000 0x0 0x80000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		xbl_sc_mem: xbl-sc@d8000000 {</div><div class='add'>+			reg = &lt;0x0 0xd8000000 0x0 0x40000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		reserved-region@d8040000 {</div><div class='add'>+			reg = &lt;0x0 0xd8040000 0x0 0xa0000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qtee_mem: qtee@d80e0000 {</div><div class='add'>+			reg = &lt;0x0 0xd80e0000 0x0 0x520000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ta_mem: ta@d8600000 {</div><div class='add'>+			reg = &lt;0x0 0xd8600000 0x0 0x8a00000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tags_mem1: tags@e1000000 {</div><div class='add'>+			reg = &lt;0x0 0xe1000000 0x0 0x26a0000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		llcc_lpi_mem: llcc-lpi@ff800000 {</div><div class='add'>+			reg = &lt;0x0 0xff800000 0x0 0x600000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smem_mem: smem@ffe00000 {</div><div class='add'>+			compatible = "qcom,smem";</div><div class='add'>+			reg = &lt;0x0 0xffe00000 0x0 0x200000&gt;;</div><div class='add'>+			hwlocks = &lt;&amp;tcsr_mutex 3&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	qup_opp_table_100mhz: opp-table-qup100mhz {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		opp-75000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;75000000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-100000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;100000000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;rpmhpd_opp_svs&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	qup_opp_table_120mhz: opp-table-qup120mhz {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		opp-75000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;75000000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-120000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;120000000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;rpmhpd_opp_svs&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	smp2p-adsp {</div><div class='add'>+		compatible = "qcom,smp2p";</div><div class='add'>+</div><div class='add'>+		interrupts-extended = &lt;&amp;ipcc IPCC_CLIENT_LPASS</div><div class='add'>+					     IPCC_MPROC_SIGNAL_SMP2P</div><div class='add'>+					     IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+</div><div class='add'>+		mboxes = &lt;&amp;ipcc IPCC_CLIENT_LPASS</div><div class='add'>+				IPCC_MPROC_SIGNAL_SMP2P&gt;;</div><div class='add'>+</div><div class='add'>+		qcom,smem = &lt;443&gt;, &lt;429&gt;;</div><div class='add'>+		qcom,local-pid = &lt;0&gt;;</div><div class='add'>+		qcom,remote-pid = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		smp2p_adsp_out: master-kernel {</div><div class='add'>+			qcom,entry-name = "master-kernel";</div><div class='add'>+			#qcom,smem-state-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smp2p_adsp_in: slave-kernel {</div><div class='add'>+			qcom,entry-name = "slave-kernel";</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	smp2p-cdsp {</div><div class='add'>+		compatible = "qcom,smp2p";</div><div class='add'>+</div><div class='add'>+		interrupts-extended = &lt;&amp;ipcc IPCC_CLIENT_CDSP</div><div class='add'>+					     IPCC_MPROC_SIGNAL_SMP2P</div><div class='add'>+					     IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+</div><div class='add'>+		mboxes = &lt;&amp;ipcc IPCC_CLIENT_CDSP</div><div class='add'>+				IPCC_MPROC_SIGNAL_SMP2P&gt;;</div><div class='add'>+</div><div class='add'>+		qcom,smem = &lt;94&gt;, &lt;432&gt;;</div><div class='add'>+		qcom,local-pid = &lt;0&gt;;</div><div class='add'>+		qcom,remote-pid = &lt;5&gt;;</div><div class='add'>+</div><div class='add'>+		smp2p_cdsp_out: master-kernel {</div><div class='add'>+			qcom,entry-name = "master-kernel";</div><div class='add'>+			#qcom,smem-state-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smp2p_cdsp_in: slave-kernel {</div><div class='add'>+			qcom,entry-name = "slave-kernel";</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc: soc@0 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		dma-ranges = &lt;0 0 0 0 0x10 0&gt;;</div><div class='add'>+		ranges = &lt;0 0 0 0 0x10 0&gt;;</div><div class='add'>+</div><div class='add'>+		gcc: clock-controller@100000 {</div><div class='add'>+			compatible = "qcom,x1e80100-gcc";</div><div class='add'>+			reg = &lt;0 0x00100000 0 0x200000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;bi_tcxo_div2&gt;,</div><div class='add'>+				 &lt;&amp;sleep_clk&gt;,</div><div class='add'>+				 &lt;&amp;pcie3_phy&gt;,</div><div class='add'>+				 &lt;&amp;pcie4_phy&gt;,</div><div class='add'>+				 &lt;&amp;pcie5_phy&gt;,</div><div class='add'>+				 &lt;&amp;pcie6a_phy&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;&amp;usb_1_ss0_qmpphy QMP_USB43DP_USB3_PIPE_CLK&gt;,</div><div class='add'>+				 &lt;&amp;usb_1_ss1_qmpphy QMP_USB43DP_USB3_PIPE_CLK&gt;,</div><div class='add'>+				 &lt;&amp;usb_1_ss2_qmpphy QMP_USB43DP_USB3_PIPE_CLK&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ipcc: mailbox@408000 {</div><div class='add'>+			compatible = "qcom,x1e80100-ipcc", "qcom,ipcc";</div><div class='add'>+			reg = &lt;0 0x00408000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+			#mbox-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpi_dma2: dma-controller@800000 {</div><div class='add'>+			compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";</div><div class='add'>+			reg = &lt;0 0x00800000 0 0x60000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			dma-channels = &lt;12&gt;;</div><div class='add'>+			dma-channel-mask = &lt;0x3e&gt;;</div><div class='add'>+			#dma-cells = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x436 0x0&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qupv3_2: geniqup@8c0000 {</div><div class='add'>+			compatible = "qcom,geni-se-qup";</div><div class='add'>+			reg = &lt;0 0x008c0000 0 0x2000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_QUPV3_WRAP_2_M_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_QUPV3_WRAP_2_S_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "m-ahb",</div><div class='add'>+				      "s-ahb";</div><div class='add'>+</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x423 0x0&gt;;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			i2c16: i2c@880000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0 0x00880000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP2_S0_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma2 0 0 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma2 1 0 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c16_data_clk&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi16: spi@880000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0 0x00880000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP2_S0_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table_120mhz&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma2 0 0 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma2 1 0 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi16_data_clk&gt;, &lt;&amp;qup_spi16_cs&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c17: i2c@884000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0 0x00884000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP2_S1_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma2 0 1 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma2 1 1 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c17_data_clk&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi17: spi@884000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0 0x00884000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP2_S1_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table_120mhz&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma2 0 1 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma2 1 1 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi17_data_clk&gt;, &lt;&amp;qup_spi17_cs&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c18: i2c@888000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0 0x00888000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP2_S2_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma2 0 2 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma2 1 2 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c18_data_clk&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi18: spi@888000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0 0x00888000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP2_S2_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table_100mhz&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma2 0 2 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma2 1 2 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi18_data_clk&gt;, &lt;&amp;qup_spi18_cs&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c19: i2c@88c000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0 0x0088c000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP2_S3_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma2 0 3 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma2 1 3 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c19_data_clk&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi19: spi@88c000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0 0x0088c000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP2_S3_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table_100mhz&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma2 0 3 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma2 1 3 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi19_data_clk&gt;, &lt;&amp;qup_spi19_cs&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c20: i2c@890000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0 0x00890000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP2_S4_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma2 0 4 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma2 1 4 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c20_data_clk&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi20: spi@890000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0 0x00890000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP2_S4_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table_100mhz&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma2 0 4 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma2 1 4 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi20_data_clk&gt;, &lt;&amp;qup_spi20_cs&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c21: i2c@894000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0 0x00894000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP2_S5_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma2 0 5 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma2 1 5 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c21_data_clk&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi21: spi@894000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0 0x00894000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP2_S5_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table_100mhz&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma2 0 5 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma2 1 5 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi21_data_clk&gt;, &lt;&amp;qup_spi21_cs&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart21: serial@894000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0 0x00894000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP2_S5_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table_100mhz&gt;;</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart21_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c22: i2c@898000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0 0x00898000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP2_S6_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma2 0 6 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma2 1 6 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c22_data_clk&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi22: spi@898000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0 0x00898000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP2_S6_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table_100mhz&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma2 0 6 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma2 1 6 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi22_data_clk&gt;, &lt;&amp;qup_spi22_cs&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c23: i2c@89c000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0 0x0089c000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP2_S7_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma2 0 7 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma2 1 7 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c23_data_clk&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi23: spi@89c000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0 0x0089c000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP2_S7_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table_100mhz&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma2 0 7 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma2 1 7 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi23_data_clk&gt;, &lt;&amp;qup_spi23_cs&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpi_dma1: dma-controller@a00000 {</div><div class='add'>+			compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";</div><div class='add'>+			reg = &lt;0 0x00a00000 0 0x60000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 776 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 777 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 778 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 779 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			dma-channels = &lt;12&gt;;</div><div class='add'>+			dma-channel-mask = &lt;0x3e&gt;;</div><div class='add'>+			#dma-cells = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x136 0x0&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qupv3_1: geniqup@ac0000 {</div><div class='add'>+			compatible = "qcom,geni-se-qup";</div><div class='add'>+			reg = &lt;0 0x00ac0000 0 0x2000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_QUPV3_WRAP_1_M_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_QUPV3_WRAP_1_S_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "m-ahb",</div><div class='add'>+				      "s-ahb";</div><div class='add'>+</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x123 0x0&gt;;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			i2c8: i2c@a80000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0 0x00a80000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S0_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 0 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 0 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c8_data_clk&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi8: spi@a80000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0 0x00a80000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S0_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table_120mhz&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 0 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 0 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi8_data_clk&gt;, &lt;&amp;qup_spi8_cs&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c9: i2c@a84000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0 0x00a84000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S1_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 1 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 1 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c9_data_clk&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi9: spi@a84000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0 0x00a84000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S1_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table_120mhz&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 1 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 1 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi9_data_clk&gt;, &lt;&amp;qup_spi9_cs&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c10: i2c@a88000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0 0x00a88000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S2_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 2 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 2 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c10_data_clk&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi10: spi@a88000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0 0x00a88000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S2_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table_100mhz&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 2 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 2 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi10_data_clk&gt;, &lt;&amp;qup_spi10_cs&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c11: i2c@a8c000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0 0x00a8c000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S3_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 3 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 3 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c11_data_clk&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi11: spi@a8c000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0 0x00a8c000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S3_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table_100mhz&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 3 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 3 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi11_data_clk&gt;, &lt;&amp;qup_spi11_cs&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c12: i2c@a90000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0 0x00a90000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S4_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 4 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 4 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c12_data_clk&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi12: spi@a90000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0 0x00a90000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S4_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table_100mhz&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 4 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 4 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi12_data_clk&gt;, &lt;&amp;qup_spi12_cs&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c13: i2c@a94000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0 0x00a94000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S5_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 5 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 5 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c13_data_clk&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi13: spi@a94000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0 0x00a94000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S5_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table_100mhz&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 5 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 5 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi13_data_clk&gt;, &lt;&amp;qup_spi13_cs&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c14: i2c@a98000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0 0x00a98000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S6_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 6 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 6 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c14_data_clk&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi14: spi@a98000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0 0x00a98000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S6_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table_100mhz&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 6 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 6 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi14_data_clk&gt;, &lt;&amp;qup_spi14_cs&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart14: serial@a98000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0 0x00a98000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S6_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table_100mhz&gt;;</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart14_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c15: i2c@a9c000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0 0x00a9c000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S7_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 7 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 7 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c15_data_clk&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi15: spi@a9c000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0 0x00a9c000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S7_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table_100mhz&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 7 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 7 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi15_data_clk&gt;, &lt;&amp;qup_spi15_cs&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpi_dma0: dma-controller@b00000  {</div><div class='add'>+			compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";</div><div class='add'>+			reg = &lt;0 0x00b00000 0 0x60000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			dma-channels = &lt;12&gt;;</div><div class='add'>+			dma-channel-mask = &lt;0x3e&gt;;</div><div class='add'>+			#dma-cells = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x456 0x0&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qupv3_0: geniqup@bc0000 {</div><div class='add'>+			compatible = "qcom,geni-se-qup";</div><div class='add'>+			reg = &lt;0 0x00bc0000 0 0x2000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_QUPV3_WRAP_0_M_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_QUPV3_WRAP_0_S_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "m-ahb",</div><div class='add'>+				      "s-ahb";</div><div class='add'>+</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x443 0x0&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			i2c0: i2c@b80000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0 0x00b80000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S0_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 0 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 0 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c0_data_clk&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi0: spi@b80000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0 0x00b80000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S0_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table_120mhz&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 0 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 0 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi0_data_clk&gt;, &lt;&amp;qup_spi0_cs&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c1: i2c@b84000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0 0x00b84000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S1_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 1 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 1 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c1_data_clk&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi1: spi@b84000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0 0x00b84000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S1_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table_120mhz&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 1 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 1 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi1_data_clk&gt;, &lt;&amp;qup_spi1_cs&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c2: i2c@b88000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0 0x00b88000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S2_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 2 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 2 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c2_data_clk&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart2: serial@b88000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0 0x00b88000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S2_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table_100mhz&gt;;</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart2_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi2: spi@b88000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0 0x00b88000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S2_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table_100mhz&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 2 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 2 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi2_data_clk&gt;, &lt;&amp;qup_spi2_cs&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c3: i2c@b8c000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0 0x00b8c000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S3_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 3 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 3 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c3_data_clk&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi3: spi@b8c000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0 0x00b8c000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S3_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table_100mhz&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 3 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 3 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi3_data_clk&gt;, &lt;&amp;qup_spi3_cs&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c4: i2c@b90000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0 0x00b90000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S4_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 4 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 4 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c4_data_clk&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi4: spi@b90000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0 0x00b90000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S4_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table_100mhz&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 4 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 4 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi4_data_clk&gt;, &lt;&amp;qup_spi4_cs&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c5: i2c@b94000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0 0x00b94000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S5_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 5 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 5 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c5_data_clk&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi5: spi@b94000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0 0x00b94000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S5_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table_100mhz&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 5 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 5 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi5_data_clk&gt;, &lt;&amp;qup_spi5_cs&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c6: i2c@b98000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0 0x00b98000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S6_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 6 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 6 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c6_data_clk&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi6: spi@b98000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0 0x00b98000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S6_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table_100mhz&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 6 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 6 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi6_data_clk&gt;, &lt;&amp;qup_spi6_cs&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c7: i2c@b9c000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0 0x00b9c000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S7_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 7 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 7 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c7_data_clk&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi7: spi@b9c000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0 0x00b9c000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S7_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table_100mhz&gt;;</div><div class='add'>+</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 7 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 7 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi7_data_clk&gt;, &lt;&amp;qup_spi7_cs&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tsens0: thermal-sensor@c271000 {</div><div class='add'>+			compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";</div><div class='add'>+			reg = &lt;0 0x0c271000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x0c222000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts-extended = &lt;&amp;pdc 26 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;intc GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "uplow",</div><div class='add'>+					  "critical";</div><div class='add'>+</div><div class='add'>+			#qcom,sensors = &lt;16&gt;;</div><div class='add'>+</div><div class='add'>+			#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tsens1: thermal-sensor@c272000 {</div><div class='add'>+			compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";</div><div class='add'>+			reg = &lt;0 0x0c272000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x0c223000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts-extended = &lt;&amp;pdc 27 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;intc GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "uplow",</div><div class='add'>+					  "critical";</div><div class='add'>+</div><div class='add'>+			#qcom,sensors = &lt;16&gt;;</div><div class='add'>+</div><div class='add'>+			#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tsens2: thermal-sensor@c273000 {</div><div class='add'>+			compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";</div><div class='add'>+			reg = &lt;0 0x0c273000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x0c224000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts-extended = &lt;&amp;pdc 28 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;intc GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "uplow",</div><div class='add'>+					  "critical";</div><div class='add'>+</div><div class='add'>+			#qcom,sensors = &lt;16&gt;;</div><div class='add'>+</div><div class='add'>+			#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tsens3: thermal-sensor@c274000 {</div><div class='add'>+			compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";</div><div class='add'>+			reg = &lt;0 0x0c274000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x0c225000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts-extended = &lt;&amp;pdc 29 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;intc GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "uplow",</div><div class='add'>+					  "critical";</div><div class='add'>+</div><div class='add'>+			#qcom,sensors = &lt;16&gt;;</div><div class='add'>+</div><div class='add'>+			#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_1_ss0_hsphy: phy@fd3000 {</div><div class='add'>+			compatible = "qcom,x1e80100-snps-eusb2-phy",</div><div class='add'>+				     "qcom,sm8550-snps-eusb2-phy";</div><div class='add'>+			reg = &lt;0 0x00fd3000 0 0x154&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;tcsr TCSR_USB2_1_CLKREF_EN&gt;;</div><div class='add'>+			clock-names = "ref";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_QUSB2PHY_PRIM_BCR&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_1_ss0_qmpphy: phy@fd5000 {</div><div class='add'>+			compatible = "qcom,x1e80100-qmp-usb3-dp-phy";</div><div class='add'>+			reg = &lt;0 0x00fd5000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_USB3_PRIM_PHY_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB3_PRIM_PHY_PIPE_CLK&gt;;</div><div class='add'>+			clock-names = "aux",</div><div class='add'>+				      "ref",</div><div class='add'>+				      "com_aux",</div><div class='add'>+				      "usb3_pipe";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;gcc GCC_USB_0_PHY_GDSC&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_USB3_PHY_PRIM_BCR&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB4_0_DP0_PHY_PRIM_BCR&gt;;</div><div class='add'>+			reset-names = "phy",</div><div class='add'>+				      "common";</div><div class='add'>+</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#phy-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			mode-switch;</div><div class='add'>+			orientation-switch;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					usb_1_ss0_qmpphy_out: endpoint {</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					usb_1_ss0_qmpphy_usb_ss_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;usb_1_ss0_dwc3_ss&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@2 {</div><div class='add'>+					reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+					usb_1_ss0_qmpphy_dp_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mdss_dp0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_1_ss1_hsphy: phy@fd9000 {</div><div class='add'>+			compatible = "qcom,x1e80100-snps-eusb2-phy",</div><div class='add'>+				     "qcom,sm8550-snps-eusb2-phy";</div><div class='add'>+			reg = &lt;0 0x00fd9000 0 0x154&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;tcsr TCSR_USB2_1_CLKREF_EN&gt;;</div><div class='add'>+			clock-names = "ref";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_QUSB2PHY_SEC_BCR&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_1_ss1_qmpphy: phy@fda000 {</div><div class='add'>+			compatible = "qcom,x1e80100-qmp-usb3-dp-phy";</div><div class='add'>+			reg = &lt;0 0x00fda000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_USB3_SEC_PHY_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB3_SEC_PHY_COM_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB3_SEC_PHY_PIPE_CLK&gt;;</div><div class='add'>+			clock-names = "aux",</div><div class='add'>+				      "ref",</div><div class='add'>+				      "com_aux",</div><div class='add'>+				      "usb3_pipe";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;gcc GCC_USB_1_PHY_GDSC&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_USB3_PHY_SEC_BCR&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB4_1_DP0_PHY_SEC_BCR&gt;;</div><div class='add'>+			reset-names = "phy",</div><div class='add'>+				      "common";</div><div class='add'>+</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#phy-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			mode-switch;</div><div class='add'>+			orientation-switch;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					usb_1_ss1_qmpphy_out: endpoint {</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					usb_1_ss1_qmpphy_usb_ss_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;usb_1_ss1_dwc3_ss&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@2 {</div><div class='add'>+					reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+					usb_1_ss1_qmpphy_dp_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mdss_dp1_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_1_ss2_hsphy: phy@fde000 {</div><div class='add'>+			compatible = "qcom,x1e80100-snps-eusb2-phy",</div><div class='add'>+				     "qcom,sm8550-snps-eusb2-phy";</div><div class='add'>+			reg = &lt;0 0x00fde000 0 0x154&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;tcsr TCSR_USB2_1_CLKREF_EN&gt;;</div><div class='add'>+			clock-names = "ref";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_QUSB2PHY_TERT_BCR&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_1_ss2_qmpphy: phy@fdf000 {</div><div class='add'>+			compatible = "qcom,x1e80100-qmp-usb3-dp-phy";</div><div class='add'>+			reg = &lt;0 0x00fdf000 0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_USB3_TERT_PHY_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB3_TERT_PHY_COM_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB3_TERT_PHY_PIPE_CLK&gt;;</div><div class='add'>+			clock-names = "aux",</div><div class='add'>+				      "ref",</div><div class='add'>+				      "com_aux",</div><div class='add'>+				      "usb3_pipe";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;gcc GCC_USB_2_PHY_GDSC&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_USB3_PHY_TERT_BCR&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB4_2_DP0_PHY_TERT_BCR&gt;;</div><div class='add'>+			reset-names = "phy",</div><div class='add'>+				      "common";</div><div class='add'>+</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#phy-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			mode-switch;</div><div class='add'>+			orientation-switch;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					usb_1_ss2_qmpphy_out: endpoint {</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					usb_1_ss2_qmpphy_usb_ss_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;usb_1_ss2_dwc3_ss&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@2 {</div><div class='add'>+					reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+					usb_1_ss2_qmpphy_dp_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mdss_dp2_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cnoc_main: interconnect@1500000 {</div><div class='add'>+			compatible = "qcom,x1e80100-cnoc-main";</div><div class='add'>+			reg = &lt;0 0x01500000 0 0x14400&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+</div><div class='add'>+			#interconnect-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		config_noc: interconnect@1600000 {</div><div class='add'>+			compatible = "qcom,x1e80100-cnoc-cfg";</div><div class='add'>+			reg = &lt;0 0x01600000 0 0x6600&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+</div><div class='add'>+			#interconnect-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		system_noc: interconnect@1680000 {</div><div class='add'>+			compatible = "qcom,x1e80100-system-noc";</div><div class='add'>+			reg = &lt;0 0x01680000 0 0x1c080&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+</div><div class='add'>+			#interconnect-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie_south_anoc: interconnect@16c0000 {</div><div class='add'>+			compatible = "qcom,x1e80100-pcie-south-anoc";</div><div class='add'>+			reg = &lt;0 0x016c0000 0 0xd080&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+</div><div class='add'>+			#interconnect-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie_center_anoc: interconnect@16d0000 {</div><div class='add'>+			compatible = "qcom,x1e80100-pcie-center-anoc";</div><div class='add'>+			reg = &lt;0 0x016d0000 0 0x7000&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+</div><div class='add'>+			#interconnect-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aggre1_noc: interconnect@16e0000 {</div><div class='add'>+			compatible = "qcom,x1e80100-aggre1-noc";</div><div class='add'>+			reg = &lt;0 0x016e0000 0 0x14400&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+</div><div class='add'>+			#interconnect-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aggre2_noc: interconnect@1700000 {</div><div class='add'>+			compatible = "qcom,x1e80100-aggre2-noc";</div><div class='add'>+			reg = &lt;0 0x01700000 0 0x1c400&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+</div><div class='add'>+			#interconnect-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie_north_anoc: interconnect@1740000 {</div><div class='add'>+			compatible = "qcom,x1e80100-pcie-north-anoc";</div><div class='add'>+			reg = &lt;0 0x01740000 0 0x9080&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+</div><div class='add'>+			#interconnect-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_center_anoc: interconnect@1750000 {</div><div class='add'>+			compatible = "qcom,x1e80100-usb-center-anoc";</div><div class='add'>+			reg = &lt;0 0x01750000 0 0x8800&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+</div><div class='add'>+			#interconnect-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_north_anoc: interconnect@1760000 {</div><div class='add'>+			compatible = "qcom,x1e80100-usb-north-anoc";</div><div class='add'>+			reg = &lt;0 0x01760000 0 0x7080&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+</div><div class='add'>+			#interconnect-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_south_anoc: interconnect@1770000 {</div><div class='add'>+			compatible = "qcom,x1e80100-usb-south-anoc";</div><div class='add'>+			reg = &lt;0 0x01770000 0 0xf080&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+</div><div class='add'>+			#interconnect-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmss_noc: interconnect@1780000 {</div><div class='add'>+			compatible = "qcom,x1e80100-mmss-noc";</div><div class='add'>+			reg = &lt;0 0x01780000 0 0x5B800&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+</div><div class='add'>+			#interconnect-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie3: pcie@1bd0000 {</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			compatible = "qcom,pcie-x1e80100";</div><div class='add'>+			reg = &lt;0x0 0x01bd0000 0x0 0x3000&gt;,</div><div class='add'>+			      &lt;0x0 0x78000000 0x0 0xf20&gt;,</div><div class='add'>+			      &lt;0x0 0x78000f40 0x0 0xa8&gt;,</div><div class='add'>+			      &lt;0x0 0x78001000 0x0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0x78100000 0x0 0x100000&gt;,</div><div class='add'>+			      &lt;0x0 0x01bd3000 0x0 0x1000&gt;;</div><div class='add'>+			reg-names = "parf",</div><div class='add'>+				    "dbi",</div><div class='add'>+				    "elbi",</div><div class='add'>+				    "atu",</div><div class='add'>+				    "config",</div><div class='add'>+				    "mhi";</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges = &lt;0x01000000 0x0 0x00000000 0x0 0x78200000 0x0 0x100000&gt;,</div><div class='add'>+				 &lt;0x02000000 0x0 0x78300000 0x0 0x78300000 0x0 0x3d00000&gt;,</div><div class='add'>+				 &lt;0x03000000 0x7 0x40000000 0x7 0x40000000 0x0 0x40000000&gt;;</div><div class='add'>+			bus-range = &lt;0x00 0xff&gt;;</div><div class='add'>+</div><div class='add'>+			dma-coherent;</div><div class='add'>+</div><div class='add'>+			linux,pci-domain = &lt;3&gt;;</div><div class='add'>+			num-lanes = &lt;8&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "msi0",</div><div class='add'>+					  "msi1",</div><div class='add'>+					  "msi2",</div><div class='add'>+					  "msi3",</div><div class='add'>+					  "msi4",</div><div class='add'>+					  "msi5",</div><div class='add'>+					  "msi6",</div><div class='add'>+					  "msi7",</div><div class='add'>+					  "global";</div><div class='add'>+</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0x7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;intc 0 0 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;intc 0 0 GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;intc 0 0 GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;intc 0 0 GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_PCIE_3_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_3_CFG_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_3_MSTR_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_3_SLV_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK&gt;;</div><div class='add'>+			clock-names = "aux",</div><div class='add'>+				      "cfg",</div><div class='add'>+				      "bus_master",</div><div class='add'>+				      "bus_slave",</div><div class='add'>+				      "slave_q2a",</div><div class='add'>+				      "noc_aggr",</div><div class='add'>+				      "cnoc_sf_axi";</div><div class='add'>+</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_PCIE_3_AUX_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;19200000&gt;;</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;pcie_north_anoc MASTER_PCIE_3 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+					&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;cnoc_main SLAVE_PCIE_3 QCOM_ICC_TAG_ACTIVE_ONLY&gt;;</div><div class='add'>+			interconnect-names = "pcie-mem",</div><div class='add'>+					     "cpu-pcie";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_PCIE_3_BCR&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_3_LINK_DOWN_BCR&gt;;</div><div class='add'>+			reset-names = "pci",</div><div class='add'>+				      "link_down";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;gcc GCC_PCIE_3_GDSC&gt;;</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;pcie3_phy&gt;;</div><div class='add'>+			phy-names = "pciephy";</div><div class='add'>+</div><div class='add'>+			eq-presets-8gts = /bits/ 16 &lt;0x5555 0x5555 0x5555 0x5555</div><div class='add'>+						     0x5555 0x5555 0x5555 0x5555&gt;;</div><div class='add'>+			eq-presets-16gts = /bits/ 8 &lt;0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55&gt;;</div><div class='add'>+</div><div class='add'>+			operating-points-v2 = &lt;&amp;pcie3_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcie3_opp_table: opp-table {</div><div class='add'>+				compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+				/* 2.5GT/s x1 */</div><div class='add'>+				opp-2500000-1 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;2500000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;250000 1&gt;;</div><div class='add'>+					opp-level = &lt;1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				/* 2.5 GT/s x2 */</div><div class='add'>+				opp-5000000-1 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;5000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;500000 1&gt;;</div><div class='add'>+					opp-level = &lt;1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				/* 2.5 GT/s x4 */</div><div class='add'>+				opp-10000000-1 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;10000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;1000000 1&gt;;</div><div class='add'>+					opp-level = &lt;1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				/* 2.5 GT/s x8 */</div><div class='add'>+				opp-20000000-1 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;20000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;2000000 1&gt;;</div><div class='add'>+					opp-level = &lt;1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				/* 5 GT/s x1 */</div><div class='add'>+				opp-5000000-2 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;5000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;500000 1&gt;;</div><div class='add'>+					opp-level = &lt;2&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				/* 5 GT/s x2 */</div><div class='add'>+				opp-10000000-2 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;10000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;1000000 1&gt;;</div><div class='add'>+					opp-level = &lt;2&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				/* 5 GT/s x4 */</div><div class='add'>+				opp-20000000-2 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;20000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;2000000 1&gt;;</div><div class='add'>+					opp-level = &lt;2&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				/* 5 GT/s x8 */</div><div class='add'>+				opp-40000000-2 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;40000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;4000000 1&gt;;</div><div class='add'>+					opp-level = &lt;2&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				/* 8 GT/s x1 */</div><div class='add'>+				opp-8000000-3 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;8000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_svs&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;984500 1&gt;;</div><div class='add'>+					opp-level = &lt;3&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				/* 8 GT/s x2 */</div><div class='add'>+				opp-16000000-3 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;16000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_svs&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;1969000 1&gt;;</div><div class='add'>+					opp-level = &lt;3&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				/* 8 GT/s x4 */</div><div class='add'>+				opp-32000000-3 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;32000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_svs&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;3938000 1&gt;;</div><div class='add'>+					opp-level = &lt;3&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				/* 8 GT/s x8 */</div><div class='add'>+				opp-64000000-3 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;64000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_svs&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;7876000 1&gt;;</div><div class='add'>+					opp-level = &lt;3&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				/* 16 GT/s x1 */</div><div class='add'>+				opp-16000000-4 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;16000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_svs&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;1969000 1&gt;;</div><div class='add'>+					opp-level = &lt;4&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				/* 16 GT/s x2 */</div><div class='add'>+				opp-32000000-4 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;32000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_svs&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;3938000 1&gt;;</div><div class='add'>+					opp-level = &lt;4&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				/* 16 GT/s x4 */</div><div class='add'>+				opp-64000000-4 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;64000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_svs&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;7876000 1&gt;;</div><div class='add'>+					opp-level = &lt;4&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				/* 16 GT/s x8 */</div><div class='add'>+				opp-128000000-4 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;128000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_svs&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;15753000 1&gt;;</div><div class='add'>+					opp-level = &lt;4&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pcie3_port: pcie@0 {</div><div class='add'>+				device_type = "pci";</div><div class='add'>+				compatible = "pciclass,0604";</div><div class='add'>+				reg = &lt;0x0 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+				bus-range = &lt;0x01 0xff&gt;;</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;3&gt;;</div><div class='add'>+				#size-cells = &lt;2&gt;;</div><div class='add'>+				ranges;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie3_phy: phy@1be0000 {</div><div class='add'>+			compatible = "qcom,x1e80100-qmp-gen4x8-pcie-phy";</div><div class='add'>+			reg = &lt;0 0x01be0000 0 0x10000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_PCIE_3_PHY_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_3_CFG_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;tcsr TCSR_PCIE_8L_CLKREF_EN&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_3_PHY_RCHNG_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_3_PIPE_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_3_PIPEDIV2_CLK&gt;;</div><div class='add'>+			clock-names = "aux",</div><div class='add'>+				      "cfg_ahb",</div><div class='add'>+				      "ref",</div><div class='add'>+				      "rchng",</div><div class='add'>+				      "pipe",</div><div class='add'>+				      "pipediv2";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_PCIE_3_PHY_BCR&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_3_NOCSR_COM_PHY_BCR&gt;;</div><div class='add'>+			reset-names = "phy",</div><div class='add'>+				      "phy_nocsr";</div><div class='add'>+</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_PCIE_3_PHY_RCHNG_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;100000000&gt;;</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;gcc GCC_PCIE_3_PHY_GDSC&gt;;</div><div class='add'>+</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-output-names = "pcie3_pipe_clk";</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie6a: pci@1bf8000 {</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			compatible = "qcom,pcie-x1e80100";</div><div class='add'>+			reg = &lt;0 0x01bf8000 0 0x3000&gt;,</div><div class='add'>+			      &lt;0 0x70000000 0 0xf20&gt;,</div><div class='add'>+			      &lt;0 0x70000f40 0 0xa8&gt;,</div><div class='add'>+			      &lt;0 0x70001000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x70100000 0 0x100000&gt;,</div><div class='add'>+			      &lt;0 0x01bfb000 0 0x1000&gt;;</div><div class='add'>+			reg-names = "parf",</div><div class='add'>+				    "dbi",</div><div class='add'>+				    "elbi",</div><div class='add'>+				    "atu",</div><div class='add'>+				    "config",</div><div class='add'>+				    "mhi";</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges = &lt;0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x100000&gt;,</div><div class='add'>+				 &lt;0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000&gt;;</div><div class='add'>+			bus-range = &lt;0x00 0xff&gt;;</div><div class='add'>+</div><div class='add'>+			dma-coherent;</div><div class='add'>+</div><div class='add'>+			linux,pci-domain = &lt;6&gt;;</div><div class='add'>+			num-lanes = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+			msi-map = &lt;0x0 &amp;gic_its 0xe0000 0x10000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "msi0",</div><div class='add'>+					  "msi1",</div><div class='add'>+					  "msi2",</div><div class='add'>+					  "msi3",</div><div class='add'>+					  "msi4",</div><div class='add'>+					  "msi5",</div><div class='add'>+					  "msi6",</div><div class='add'>+					  "msi7",</div><div class='add'>+					  "global";</div><div class='add'>+</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0x7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;intc 0 0 GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;intc 0 0 GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;intc 0 0 GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;intc 0 0 GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_PCIE_6A_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_6A_CFG_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_6A_MSTR_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_6A_SLV_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_6A_SLV_Q2A_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK&gt;;</div><div class='add'>+			clock-names = "aux",</div><div class='add'>+				      "cfg",</div><div class='add'>+				      "bus_master",</div><div class='add'>+				      "bus_slave",</div><div class='add'>+				      "slave_q2a",</div><div class='add'>+				      "noc_aggr",</div><div class='add'>+				      "cnoc_sf_axi";</div><div class='add'>+</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_PCIE_6A_AUX_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;19200000&gt;;</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;pcie_south_anoc MASTER_PCIE_6A QCOM_ICC_TAG_ALWAYS</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+					&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;cnoc_main SLAVE_PCIE_6A QCOM_ICC_TAG_ACTIVE_ONLY&gt;;</div><div class='add'>+			interconnect-names = "pcie-mem",</div><div class='add'>+					     "cpu-pcie";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_PCIE_6A_BCR&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_6A_LINK_DOWN_BCR&gt;;</div><div class='add'>+			reset-names = "pci",</div><div class='add'>+				      "link_down";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;gcc GCC_PCIE_6A_GDSC&gt;;</div><div class='add'>+			required-opps = &lt;&amp;rpmhpd_opp_nom&gt;;</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;pcie6a_phy&gt;;</div><div class='add'>+			phy-names = "pciephy";</div><div class='add'>+</div><div class='add'>+			eq-presets-8gts = /bits/ 16 &lt;0x5555 0x5555 0x5555 0x5555&gt;;</div><div class='add'>+			eq-presets-16gts = /bits/ 8 &lt;0x55 0x55 0x55 0x55&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie6a_phy: phy@1bfc000 {</div><div class='add'>+			compatible = "qcom,x1e80100-qmp-gen4x4-pcie-phy";</div><div class='add'>+			reg = &lt;0 0x01bfc000 0 0x2000&gt;,</div><div class='add'>+			      &lt;0 0x01bfe000 0 0x2000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_PCIE_6A_PHY_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_6A_CFG_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;tcsr TCSR_PCIE_4L_CLKREF_EN&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_6A_PHY_RCHNG_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_6A_PIPE_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_6A_PIPEDIV2_CLK&gt;;</div><div class='add'>+			clock-names = "aux",</div><div class='add'>+				      "cfg_ahb",</div><div class='add'>+				      "ref",</div><div class='add'>+				      "rchng",</div><div class='add'>+				      "pipe",</div><div class='add'>+				      "pipediv2";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_PCIE_6A_PHY_BCR&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_6A_NOCSR_COM_PHY_BCR&gt;;</div><div class='add'>+			reset-names = "phy",</div><div class='add'>+				      "phy_nocsr";</div><div class='add'>+</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_PCIE_6A_PHY_RCHNG_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;100000000&gt;;</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;gcc GCC_PCIE_6_PHY_GDSC&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,4ln-config-sel = &lt;&amp;tcsr 0x1a000 0&gt;;</div><div class='add'>+</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-output-names = "pcie6a_pipe_clk";</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie5: pci@1c00000 {</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			compatible = "qcom,pcie-x1e80100";</div><div class='add'>+			reg = &lt;0 0x01c00000 0 0x3000&gt;,</div><div class='add'>+			      &lt;0 0x7e000000 0 0xf1d&gt;,</div><div class='add'>+			      &lt;0 0x7e000f40 0 0xa8&gt;,</div><div class='add'>+			      &lt;0 0x7e001000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x7e100000 0 0x100000&gt;,</div><div class='add'>+			      &lt;0 0x01c03000 0 0x1000&gt;;</div><div class='add'>+			reg-names = "parf",</div><div class='add'>+				    "dbi",</div><div class='add'>+				    "elbi",</div><div class='add'>+				    "atu",</div><div class='add'>+				    "config",</div><div class='add'>+				    "mhi";</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges = &lt;0x01000000 0x0 0x00000000 0x0 0x7e200000 0x0 0x100000&gt;,</div><div class='add'>+				 &lt;0x02000000 0x0 0x7e300000 0x0 0x7e300000 0x0 0x1d00000&gt;;</div><div class='add'>+			bus-range = &lt;0x00 0xff&gt;;</div><div class='add'>+</div><div class='add'>+			dma-coherent;</div><div class='add'>+</div><div class='add'>+			linux,pci-domain = &lt;5&gt;;</div><div class='add'>+			num-lanes = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "msi0",</div><div class='add'>+					  "msi1",</div><div class='add'>+					  "msi2",</div><div class='add'>+					  "msi3",</div><div class='add'>+					  "msi4",</div><div class='add'>+					  "msi5",</div><div class='add'>+					  "msi6",</div><div class='add'>+					  "msi7",</div><div class='add'>+					  "global";</div><div class='add'>+</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0x7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;intc 0 0 GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;intc 0 0 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;intc 0 0 GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;intc 0 0 GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_PCIE_5_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_5_CFG_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_5_MSTR_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_5_SLV_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_5_SLV_Q2A_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK&gt;;</div><div class='add'>+			clock-names = "aux",</div><div class='add'>+				      "cfg",</div><div class='add'>+				      "bus_master",</div><div class='add'>+				      "bus_slave",</div><div class='add'>+				      "slave_q2a",</div><div class='add'>+				      "noc_aggr",</div><div class='add'>+				      "cnoc_sf_axi";</div><div class='add'>+</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_PCIE_5_AUX_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;19200000&gt;;</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;pcie_north_anoc MASTER_PCIE_5 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+					&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;cnoc_main SLAVE_PCIE_5 QCOM_ICC_TAG_ACTIVE_ONLY&gt;;</div><div class='add'>+			interconnect-names = "pcie-mem",</div><div class='add'>+					     "cpu-pcie";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_PCIE_5_BCR&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_5_LINK_DOWN_BCR&gt;;</div><div class='add'>+			reset-names = "pci",</div><div class='add'>+				      "link_down";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;gcc GCC_PCIE_5_GDSC&gt;;</div><div class='add'>+			required-opps = &lt;&amp;rpmhpd_opp_nom&gt;;</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;pcie5_phy&gt;;</div><div class='add'>+			phy-names = "pciephy";</div><div class='add'>+</div><div class='add'>+			eq-presets-8gts = /bits/ 16 &lt;0x5555 0x5555&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie5_phy: phy@1c06000 {</div><div class='add'>+			compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy";</div><div class='add'>+			reg = &lt;0 0x01c06000 0 0x2000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_PCIE_5_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_5_CFG_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;tcsr TCSR_PCIE_2L_5_CLKREF_EN&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_5_PHY_RCHNG_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_5_PIPE_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_5_PIPEDIV2_CLK&gt;;</div><div class='add'>+			clock-names = "aux",</div><div class='add'>+				      "cfg_ahb",</div><div class='add'>+				      "ref",</div><div class='add'>+				      "rchng",</div><div class='add'>+				      "pipe",</div><div class='add'>+				      "pipediv2";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_PCIE_5_PHY_BCR&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_5_NOCSR_COM_PHY_BCR&gt;;</div><div class='add'>+			reset-names = "phy",</div><div class='add'>+				      "phy_nocsr";</div><div class='add'>+</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_PCIE_5_PHY_RCHNG_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;100000000&gt;;</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;gcc GCC_PCIE_5_PHY_GDSC&gt;;</div><div class='add'>+</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-output-names = "pcie5_pipe_clk";</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie4: pci@1c08000 {</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			compatible = "qcom,pcie-x1e80100";</div><div class='add'>+			reg = &lt;0 0x01c08000 0 0x3000&gt;,</div><div class='add'>+			      &lt;0 0x7c000000 0 0xf1d&gt;,</div><div class='add'>+			      &lt;0 0x7c000f40 0 0xa8&gt;,</div><div class='add'>+			      &lt;0 0x7c001000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x7c100000 0 0x100000&gt;,</div><div class='add'>+			      &lt;0 0x01c0b000 0 0x1000&gt;;</div><div class='add'>+			reg-names = "parf",</div><div class='add'>+			            "dbi",</div><div class='add'>+				    "elbi",</div><div class='add'>+				    "atu",</div><div class='add'>+				    "config",</div><div class='add'>+				    "mhi";</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges = &lt;0x01000000 0x0 0x00000000 0x0 0x7c200000 0x0 0x100000&gt;,</div><div class='add'>+				 &lt;0x02000000 0x0 0x7c300000 0x0 0x7c300000 0x0 0x1d00000&gt;;</div><div class='add'>+			bus-range = &lt;0x00 0xff&gt;;</div><div class='add'>+</div><div class='add'>+			dma-coherent;</div><div class='add'>+</div><div class='add'>+			linux,pci-domain = &lt;4&gt;;</div><div class='add'>+			num-lanes = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			msi-map = &lt;0x0 &amp;gic_its 0xc0000 0x10000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "msi0",</div><div class='add'>+					  "msi1",</div><div class='add'>+					  "msi2",</div><div class='add'>+					  "msi3",</div><div class='add'>+					  "msi4",</div><div class='add'>+					  "msi5",</div><div class='add'>+					  "msi6",</div><div class='add'>+					  "msi7",</div><div class='add'>+					  "global";</div><div class='add'>+</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0x7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_PCIE_4_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_4_CFG_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_4_MSTR_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_4_SLV_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK&gt;;</div><div class='add'>+			clock-names = "aux",</div><div class='add'>+				      "cfg",</div><div class='add'>+				      "bus_master",</div><div class='add'>+				      "bus_slave",</div><div class='add'>+				      "slave_q2a",</div><div class='add'>+				      "noc_aggr",</div><div class='add'>+				      "cnoc_sf_axi";</div><div class='add'>+</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_PCIE_4_AUX_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;19200000&gt;;</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;pcie_north_anoc MASTER_PCIE_4 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+					&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;cnoc_main SLAVE_PCIE_4 QCOM_ICC_TAG_ACTIVE_ONLY&gt;;</div><div class='add'>+			interconnect-names = "pcie-mem",</div><div class='add'>+					     "cpu-pcie";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_PCIE_4_BCR&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_4_LINK_DOWN_BCR&gt;;</div><div class='add'>+			reset-names = "pci",</div><div class='add'>+				      "link_down";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;gcc GCC_PCIE_4_GDSC&gt;;</div><div class='add'>+			required-opps = &lt;&amp;rpmhpd_opp_nom&gt;;</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;pcie4_phy&gt;;</div><div class='add'>+			phy-names = "pciephy";</div><div class='add'>+</div><div class='add'>+			eq-presets-8gts = /bits/ 16 &lt;0x5555 0x5555&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcie4_port0: pcie@0 {</div><div class='add'>+				device_type = "pci";</div><div class='add'>+				reg = &lt;0x0 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+				bus-range = &lt;0x01 0xff&gt;;</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;3&gt;;</div><div class='add'>+				#size-cells = &lt;2&gt;;</div><div class='add'>+				ranges;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie4_phy: phy@1c0e000 {</div><div class='add'>+			compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy";</div><div class='add'>+			reg = &lt;0 0x01c0e000 0 0x2000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_PCIE_4_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_4_CFG_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;tcsr TCSR_PCIE_2L_4_CLKREF_EN&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_4_PHY_RCHNG_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_4_PIPE_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_4_PIPEDIV2_CLK&gt;;</div><div class='add'>+			clock-names = "aux",</div><div class='add'>+				      "cfg_ahb",</div><div class='add'>+				      "ref",</div><div class='add'>+				      "rchng",</div><div class='add'>+				      "pipe",</div><div class='add'>+				      "pipediv2";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_PCIE_4_PHY_BCR&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_4_NOCSR_COM_PHY_BCR&gt;;</div><div class='add'>+			reset-names = "phy",</div><div class='add'>+				      "phy_nocsr";</div><div class='add'>+</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_PCIE_4_PHY_RCHNG_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;100000000&gt;;</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;gcc GCC_PCIE_4_PHY_GDSC&gt;;</div><div class='add'>+</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-output-names = "pcie4_pipe_clk";</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tcsr_mutex: hwlock@1f40000 {</div><div class='add'>+			compatible = "qcom,tcsr-mutex";</div><div class='add'>+			reg = &lt;0 0x01f40000 0 0x20000&gt;;</div><div class='add'>+			#hwlock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tcsr: clock-controller@1fc0000 {</div><div class='add'>+			compatible = "qcom,x1e80100-tcsr", "syscon";</div><div class='add'>+			reg = &lt;0 0x01fc0000 0 0x30000&gt;;</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu: gpu@3d00000 {</div><div class='add'>+			compatible = "qcom,adreno-43050c01", "qcom,adreno";</div><div class='add'>+			reg = &lt;0x0 0x03d00000 0x0 0x40000&gt;,</div><div class='add'>+			      &lt;0x0 0x03d9e000 0x0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0x03d61000 0x0 0x800&gt;;</div><div class='add'>+</div><div class='add'>+			reg-names = "kgsl_3d0_reg_memory",</div><div class='add'>+				    "cx_mem",</div><div class='add'>+				    "cx_dbgc";</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			iommus = &lt;&amp;adreno_smmu 0 0x0&gt;,</div><div class='add'>+				 &lt;&amp;adreno_smmu 1 0x0&gt;;</div><div class='add'>+</div><div class='add'>+			operating-points-v2 = &lt;&amp;gpu_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,gmu = &lt;&amp;gmu&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			nvmem-cells = &lt;&amp;gpu_speed_bin&gt;;</div><div class='add'>+			nvmem-cell-names = "speed_bin";</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;gem_noc MASTER_GFX3D 0 &amp;mc_virt SLAVE_EBI1 0&gt;;</div><div class='add'>+			interconnect-names = "gfx-mem";</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			gpu_zap_shader: zap-shader {</div><div class='add'>+				memory-region = &lt;&amp;gpu_microcode_mem&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gpu_opp_table: opp-table {</div><div class='add'>+				compatible = "operating-points-v2-adreno", "operating-points-v2";</div><div class='add'>+</div><div class='add'>+				opp-1500000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;1500000000&gt;;</div><div class='add'>+					opp-level = &lt;RPMH_REGULATOR_LEVEL_TURBO_L5&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;16500000&gt;;</div><div class='add'>+					qcom,opp-acd-level = &lt;0xa82a5ffd&gt;;</div><div class='add'>+					opp-supported-hw = &lt;0x03&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-1375000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;1375000000&gt;;</div><div class='add'>+					opp-level = &lt;RPMH_REGULATOR_LEVEL_TURBO_L4&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;16500000&gt;;</div><div class='add'>+					qcom,opp-acd-level = &lt;0xa82a5ffd&gt;;</div><div class='add'>+					opp-supported-hw = &lt;0x03&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-1250000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;1250000000&gt;;</div><div class='add'>+					opp-level = &lt;RPMH_REGULATOR_LEVEL_TURBO_L3&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;16500000&gt;;</div><div class='add'>+					qcom,opp-acd-level = &lt;0xa82a5ffd&gt;;</div><div class='add'>+					opp-supported-hw = &lt;0x07&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-1175000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;1175000000&gt;;</div><div class='add'>+					opp-level = &lt;RPMH_REGULATOR_LEVEL_TURBO_L2&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;14398438&gt;;</div><div class='add'>+					qcom,opp-acd-level = &lt;0xa82a5ffd&gt;;</div><div class='add'>+					opp-supported-hw = &lt;0x07&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-1100000000-0 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;1100000000&gt;;</div><div class='add'>+					opp-level = &lt;RPMH_REGULATOR_LEVEL_TURBO_L1&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;14398438&gt;;</div><div class='add'>+					qcom,opp-acd-level = &lt;0xa82a5ffd&gt;;</div><div class='add'>+					opp-supported-hw = &lt;0x07&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				/* Only applicable for SKUs which has 1100Mhz as Fmax */</div><div class='add'>+				opp-1100000000-1 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;1100000000&gt;;</div><div class='add'>+					opp-level = &lt;RPMH_REGULATOR_LEVEL_TURBO_L1&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;16500000&gt;;</div><div class='add'>+					qcom,opp-acd-level = &lt;0xa82a5ffd&gt;;</div><div class='add'>+					opp-supported-hw = &lt;0x08&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-1000000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;1000000000&gt;;</div><div class='add'>+					opp-level = &lt;RPMH_REGULATOR_LEVEL_TURBO&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;14398438&gt;;</div><div class='add'>+					qcom,opp-acd-level = &lt;0xa82b5ffd&gt;;</div><div class='add'>+					opp-supported-hw = &lt;0x0f&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-925000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;925000000&gt;;</div><div class='add'>+					opp-level = &lt;RPMH_REGULATOR_LEVEL_NOM_L1&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;14398438&gt;;</div><div class='add'>+					qcom,opp-acd-level = &lt;0xa82b5ffd&gt;;</div><div class='add'>+					opp-supported-hw = &lt;0x0f&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-800000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;800000000&gt;;</div><div class='add'>+					opp-level = &lt;RPMH_REGULATOR_LEVEL_NOM&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;12449219&gt;;</div><div class='add'>+					qcom,opp-acd-level = &lt;0xa82c5ffd&gt;;</div><div class='add'>+					opp-supported-hw = &lt;0x0f&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-744000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;744000000&gt;;</div><div class='add'>+					opp-level = &lt;RPMH_REGULATOR_LEVEL_SVS_L2&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;10687500&gt;;</div><div class='add'>+					qcom,opp-acd-level = &lt;0x882e5ffd&gt;;</div><div class='add'>+					opp-supported-hw = &lt;0x0f&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-687000000-0 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;687000000&gt;;</div><div class='add'>+					opp-level = &lt;RPMH_REGULATOR_LEVEL_SVS_L1&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;8171875&gt;;</div><div class='add'>+					qcom,opp-acd-level = &lt;0x882e5ffd&gt;;</div><div class='add'>+					opp-supported-hw = &lt;0x0f&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				/* Only applicable for SKUs which has 687Mhz as Fmax */</div><div class='add'>+				opp-687000000-1 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;687000000&gt;;</div><div class='add'>+					opp-level = &lt;RPMH_REGULATOR_LEVEL_SVS_L1&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;16500000&gt;;</div><div class='add'>+					qcom,opp-acd-level = &lt;0x882e5ffd&gt;;</div><div class='add'>+					opp-supported-hw = &lt;0x10&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-550000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;550000000&gt;;</div><div class='add'>+					opp-level = &lt;RPMH_REGULATOR_LEVEL_SVS&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;6074219&gt;;</div><div class='add'>+					qcom,opp-acd-level = &lt;0xc0285ffd&gt;;</div><div class='add'>+					opp-supported-hw = &lt;0x1f&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-390000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;390000000&gt;;</div><div class='add'>+					opp-level = &lt;RPMH_REGULATOR_LEVEL_LOW_SVS&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;3000000&gt;;</div><div class='add'>+					qcom,opp-acd-level = &lt;0xc0285ffd&gt;;</div><div class='add'>+					opp-supported-hw = &lt;0x1f&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-300000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;300000000&gt;;</div><div class='add'>+					opp-level = &lt;RPMH_REGULATOR_LEVEL_LOW_SVS_D1&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;2136719&gt;;</div><div class='add'>+					qcom,opp-acd-level = &lt;0xc02b5ffd&gt;;</div><div class='add'>+					opp-supported-hw = &lt;0x1f&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gmu: gmu@3d6a000 {</div><div class='add'>+			compatible = "qcom,adreno-gmu-x185.1", "qcom,adreno-gmu";</div><div class='add'>+			reg = &lt;0x0 0x03d6a000 0x0 0x35000&gt;,</div><div class='add'>+			      &lt;0x0 0x03d50000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0x0b280000 0x0 0x10000&gt;;</div><div class='add'>+			reg-names = "gmu", "rscc", "gmu_pdc";</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "hfi", "gmu";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gpucc GPU_CC_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gpucc GPU_CC_CX_GMU_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gpucc GPU_CC_CXO_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_DDRSS_GPU_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_GPU_MEMNOC_GFX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gpucc GPU_CC_HUB_CX_INT_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gpucc GPU_CC_DEMET_CLK&gt;;</div><div class='add'>+			clock-names = "ahb",</div><div class='add'>+				      "gmu",</div><div class='add'>+				      "cxo",</div><div class='add'>+				      "axi",</div><div class='add'>+				      "memnoc",</div><div class='add'>+				      "hub",</div><div class='add'>+				      "demet";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;gpucc GPU_CX_GDSC&gt;,</div><div class='add'>+					&lt;&amp;gpucc GPU_GX_GDSC&gt;;</div><div class='add'>+			power-domain-names = "cx",</div><div class='add'>+					     "gx";</div><div class='add'>+</div><div class='add'>+			iommus = &lt;&amp;adreno_smmu 5 0x0&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,qmp = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+</div><div class='add'>+			operating-points-v2 = &lt;&amp;gmu_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+			gmu_opp_table: opp-table {</div><div class='add'>+				compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+				opp-550000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;550000000&gt;;</div><div class='add'>+					opp-level = &lt;RPMH_REGULATOR_LEVEL_SVS&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-220000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;220000000&gt;;</div><div class='add'>+					opp-level = &lt;RPMH_REGULATOR_LEVEL_LOW_SVS&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpucc: clock-controller@3d90000 {</div><div class='add'>+			compatible = "qcom,x1e80100-gpucc";</div><div class='add'>+			reg = &lt;0 0x03d90000 0 0xa000&gt;;</div><div class='add'>+			clocks = &lt;&amp;bi_tcxo_div2&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_GPU_GPLL0_CPH_CLK_SRC&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_GPU_GPLL0_DIV_CPH_CLK_SRC&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		adreno_smmu: iommu@3da0000 {</div><div class='add'>+			compatible = "qcom,x1e80100-smmu-500", "qcom,adreno-smmu",</div><div class='add'>+				     "qcom,smmu-500", "arm,mmu-500";</div><div class='add'>+			reg = &lt;0x0 0x03da0000 0x0 0x40000&gt;;</div><div class='add'>+			#iommu-cells = &lt;2&gt;;</div><div class='add'>+			#global-interrupts = &lt;1&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_GPU_MEMNOC_GFX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_GPU_SNOC_DVM_GFX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gpucc GPU_CC_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "hlos",</div><div class='add'>+				      "bus",</div><div class='add'>+				      "iface",</div><div class='add'>+				      "ahb";</div><div class='add'>+			power-domains = &lt;&amp;gpucc GPU_CX_GDSC&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gem_noc: interconnect@26400000 {</div><div class='add'>+			compatible = "qcom,x1e80100-gem-noc";</div><div class='add'>+			reg = &lt;0 0x26400000 0 0x311200&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+</div><div class='add'>+			#interconnect-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nsp_noc: interconnect@320c0000 {</div><div class='add'>+			compatible = "qcom,x1e80100-nsp-noc";</div><div class='add'>+			reg = &lt;0 0x320C0000 0 0xe080&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+</div><div class='add'>+			#interconnect-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		remoteproc_adsp: remoteproc@6800000 {</div><div class='add'>+			compatible = "qcom,x1e80100-adsp-pas";</div><div class='add'>+			reg = &lt;0x0 0x06800000 0x0 0x10000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts-extended = &lt;&amp;pdc 6 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			interrupt-names = "wdog",</div><div class='add'>+					  "fatal",</div><div class='add'>+					  "ready",</div><div class='add'>+					  "handover",</div><div class='add'>+					  "stop-ack";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;;</div><div class='add'>+			clock-names = "xo";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;rpmhpd RPMHPD_LCX&gt;,</div><div class='add'>+					&lt;&amp;rpmhpd RPMHPD_LMX&gt;;</div><div class='add'>+			power-domain-names = "lcx",</div><div class='add'>+					     "lmx";</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+</div><div class='add'>+			memory-region = &lt;&amp;adspslpi_mem&gt;,</div><div class='add'>+					&lt;&amp;q6_adsp_dtb_mem&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,qmp = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,smem-states = &lt;&amp;smp2p_adsp_out 0&gt;;</div><div class='add'>+			qcom,smem-state-names = "stop";</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			glink-edge {</div><div class='add'>+				interrupts-extended = &lt;&amp;ipcc IPCC_CLIENT_LPASS</div><div class='add'>+							     IPCC_MPROC_SIGNAL_GLINK_QMP</div><div class='add'>+							     IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				mboxes = &lt;&amp;ipcc IPCC_CLIENT_LPASS</div><div class='add'>+						IPCC_MPROC_SIGNAL_GLINK_QMP&gt;;</div><div class='add'>+</div><div class='add'>+				label = "lpass";</div><div class='add'>+				qcom,remote-pid = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+				fastrpc {</div><div class='add'>+					compatible = "qcom,fastrpc";</div><div class='add'>+					qcom,glink-channels = "fastrpcglink-apps-dsp";</div><div class='add'>+					label = "adsp";</div><div class='add'>+					qcom,non-secure-domain;</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					compute-cb@3 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;3&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x1003 0x80&gt;,</div><div class='add'>+							 &lt;&amp;apps_smmu 0x1063 0x0&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@4 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;4&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x1004 0x80&gt;,</div><div class='add'>+							 &lt;&amp;apps_smmu 0x1064 0x0&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@5 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;5&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x1005 0x80&gt;,</div><div class='add'>+							 &lt;&amp;apps_smmu 0x1065 0x0&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@6 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;6&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x1006 0x80&gt;,</div><div class='add'>+							 &lt;&amp;apps_smmu 0x1066 0x0&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@7 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;7&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x1007 0x80&gt;,</div><div class='add'>+							 &lt;&amp;apps_smmu 0x1067 0x0&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpr {</div><div class='add'>+					compatible = "qcom,gpr";</div><div class='add'>+					qcom,glink-channels = "adsp_apps";</div><div class='add'>+					qcom,domain = &lt;GPR_DOMAIN_ID_ADSP&gt;;</div><div class='add'>+					qcom,intents = &lt;512 20&gt;;</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					q6apm: service@1 {</div><div class='add'>+						compatible = "qcom,q6apm";</div><div class='add'>+						reg = &lt;GPR_APM_MODULE_IID&gt;;</div><div class='add'>+						#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+						qcom,protection-domain = "avs/audio",</div><div class='add'>+									 "msm/adsp/audio_pd";</div><div class='add'>+</div><div class='add'>+						q6apmbedai: bedais {</div><div class='add'>+							compatible = "qcom,q6apm-lpass-dais";</div><div class='add'>+							#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						q6apmdai: dais {</div><div class='add'>+							compatible = "qcom,q6apm-dais";</div><div class='add'>+							iommus = &lt;&amp;apps_smmu 0x1001 0x80&gt;,</div><div class='add'>+								 &lt;&amp;apps_smmu 0x1061 0x0&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					q6prm: service@2 {</div><div class='add'>+						compatible = "qcom,q6prm";</div><div class='add'>+						reg = &lt;GPR_PRM_MODULE_IID&gt;;</div><div class='add'>+						qcom,protection-domain = "avs/audio",</div><div class='add'>+									 "msm/adsp/audio_pd";</div><div class='add'>+</div><div class='add'>+						q6prmcc: clock-controller {</div><div class='add'>+							compatible = "qcom,q6prm-lpass-clocks";</div><div class='add'>+							#clock-cells = &lt;2&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		lpass_wsa2macro: codec@6aa0000 {</div><div class='add'>+			compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";</div><div class='add'>+			reg = &lt;0 0x06aa0000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO&gt;,</div><div class='add'>+				 &lt;&amp;q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO&gt;,</div><div class='add'>+				 &lt;&amp;q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO&gt;,</div><div class='add'>+				 &lt;&amp;lpass_vamacro&gt;;</div><div class='add'>+			clock-names = "mclk",</div><div class='add'>+				      "macro",</div><div class='add'>+				      "dcodec",</div><div class='add'>+				      "fsgen";</div><div class='add'>+</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-output-names = "wsa2-mclk";</div><div class='add'>+			#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+			sound-name-prefix = "WSA2";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		swr3: soundwire@6ab0000 {</div><div class='add'>+			compatible = "qcom,soundwire-v2.0.0";</div><div class='add'>+			reg = &lt;0 0x06ab0000 0 0x10000&gt;;</div><div class='add'>+			clocks = &lt;&amp;lpass_wsa2macro&gt;;</div><div class='add'>+			clock-names = "iface";</div><div class='add'>+			interrupts = &lt;GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			label = "WSA2";</div><div class='add'>+</div><div class='add'>+			pinctrl-0 = &lt;&amp;wsa2_swr_active&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			resets = &lt;&amp;lpass_audiocc LPASS_AUDIO_SWR_WSA2_CGCR&gt;;</div><div class='add'>+			reset-names = "swr_audio_cgcr";</div><div class='add'>+</div><div class='add'>+			qcom,din-ports = &lt;4&gt;;</div><div class='add'>+			qcom,dout-ports = &lt;9&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,ports-sinterval =		/bits/ 16 &lt;0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x31f&gt;;</div><div class='add'>+			qcom,ports-offset1 =		/bits/ 8 &lt;0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00&gt;;</div><div class='add'>+			qcom,ports-offset2 =		/bits/ 8 &lt;0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff&gt;;</div><div class='add'>+			qcom,ports-hstart =		/bits/ 8 &lt;0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f&gt;;</div><div class='add'>+			qcom,ports-hstop =		/bits/ 8 &lt;0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f&gt;;</div><div class='add'>+			qcom,ports-word-length =	/bits/ 8 &lt;0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18&gt;;</div><div class='add'>+			qcom,ports-block-pack-mode =	/bits/ 8 &lt;0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00&gt;;</div><div class='add'>+			qcom,ports-block-group-count =	/bits/ 8 &lt;0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff&gt;;</div><div class='add'>+			qcom,ports-lane-control =	/bits/ 8 &lt;0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff&gt;;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		lpass_rxmacro: codec@6ac0000 {</div><div class='add'>+			compatible = "qcom,x1e80100-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro";</div><div class='add'>+			reg = &lt;0 0x06ac0000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO&gt;,</div><div class='add'>+				 &lt;&amp;q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO&gt;,</div><div class='add'>+				 &lt;&amp;q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO&gt;,</div><div class='add'>+				 &lt;&amp;lpass_vamacro&gt;;</div><div class='add'>+			clock-names = "mclk",</div><div class='add'>+				      "macro",</div><div class='add'>+				      "dcodec",</div><div class='add'>+				      "fsgen";</div><div class='add'>+</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-output-names = "mclk";</div><div class='add'>+			#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		swr1: soundwire@6ad0000 {</div><div class='add'>+			compatible = "qcom,soundwire-v2.0.0";</div><div class='add'>+			reg = &lt;0 0x06ad0000 0 0x10000&gt;;</div><div class='add'>+			clocks = &lt;&amp;lpass_rxmacro&gt;;</div><div class='add'>+			clock-names = "iface";</div><div class='add'>+			interrupts = &lt;GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			label = "RX";</div><div class='add'>+</div><div class='add'>+			pinctrl-0 = &lt;&amp;rx_swr_active&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR&gt;;</div><div class='add'>+			reset-names = "swr_audio_cgcr";</div><div class='add'>+			qcom,din-ports = &lt;1&gt;;</div><div class='add'>+			qcom,dout-ports = &lt;11&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,ports-sinterval =		/bits/ 16 &lt;0x03 0x1f 0x1f 0x07 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff&gt;;</div><div class='add'>+			qcom,ports-offset1 =		/bits/ 8 &lt;0x00 0x00 0x0b 0x01 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff&gt;;</div><div class='add'>+			qcom,ports-offset2 =		/bits/ 8 &lt;0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff&gt;;</div><div class='add'>+			qcom,ports-hstart =		/bits/ 8 &lt;0xff 0x03 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff&gt;;</div><div class='add'>+			qcom,ports-hstop =		/bits/ 8 &lt;0xff 0x06 0x0f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff&gt;;</div><div class='add'>+			qcom,ports-word-length =	/bits/ 8 &lt;0x01 0x07 0x04 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff&gt;;</div><div class='add'>+			qcom,ports-block-pack-mode =	/bits/ 8 &lt;0xff 0xff 0x01 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff&gt;;</div><div class='add'>+			qcom,ports-block-group-count =	/bits/ 8 &lt;0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff&gt;;</div><div class='add'>+			qcom,ports-lane-control =	/bits/ 8 &lt;0x01 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff&gt;;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		lpass_txmacro: codec@6ae0000 {</div><div class='add'>+			compatible = "qcom,x1e80100-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro";</div><div class='add'>+			reg = &lt;0 0x06ae0000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO&gt;,</div><div class='add'>+				 &lt;&amp;q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO&gt;,</div><div class='add'>+				 &lt;&amp;q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO&gt;,</div><div class='add'>+				 &lt;&amp;lpass_vamacro&gt;;</div><div class='add'>+			clock-names = "mclk",</div><div class='add'>+				      "macro",</div><div class='add'>+				      "dcodec",</div><div class='add'>+				      "fsgen";</div><div class='add'>+</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-output-names = "mclk";</div><div class='add'>+			#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		lpass_wsamacro: codec@6b00000 {</div><div class='add'>+			compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";</div><div class='add'>+			reg = &lt;0 0x06b00000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO&gt;,</div><div class='add'>+				 &lt;&amp;q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO&gt;,</div><div class='add'>+				 &lt;&amp;q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO&gt;,</div><div class='add'>+				 &lt;&amp;lpass_vamacro&gt;;</div><div class='add'>+			clock-names = "mclk",</div><div class='add'>+				      "macro",</div><div class='add'>+				      "dcodec",</div><div class='add'>+				      "fsgen";</div><div class='add'>+</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-output-names = "mclk";</div><div class='add'>+			#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+			sound-name-prefix = "WSA";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		swr0: soundwire@6b10000 {</div><div class='add'>+			compatible = "qcom,soundwire-v2.0.0";</div><div class='add'>+			reg = &lt;0 0x06b10000 0 0x10000&gt;;</div><div class='add'>+			clocks = &lt;&amp;lpass_wsamacro&gt;;</div><div class='add'>+			clock-names = "iface";</div><div class='add'>+			interrupts = &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			label = "WSA";</div><div class='add'>+</div><div class='add'>+			pinctrl-0 = &lt;&amp;wsa_swr_active&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			resets = &lt;&amp;lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR&gt;;</div><div class='add'>+			reset-names = "swr_audio_cgcr";</div><div class='add'>+</div><div class='add'>+			qcom,din-ports = &lt;4&gt;;</div><div class='add'>+			qcom,dout-ports = &lt;9&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,ports-sinterval =		/bits/ 16 &lt;0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x31f&gt;;</div><div class='add'>+			qcom,ports-offset1 =		/bits/ 8 &lt;0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00&gt;;</div><div class='add'>+			qcom,ports-offset2 =		/bits/ 8 &lt;0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff&gt;;</div><div class='add'>+			qcom,ports-hstart =		/bits/ 8 &lt;0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f&gt;;</div><div class='add'>+			qcom,ports-hstop =		/bits/ 8 &lt;0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f&gt;;</div><div class='add'>+			qcom,ports-word-length =	/bits/ 8 &lt;0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18&gt;;</div><div class='add'>+			qcom,ports-block-pack-mode =	/bits/ 8 &lt;0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00&gt;;</div><div class='add'>+			qcom,ports-block-group-count =	/bits/ 8 &lt;0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff&gt;;</div><div class='add'>+			qcom,ports-lane-control =	/bits/ 8 &lt;0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff&gt;;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		lpass_audiocc: clock-controller@6b6c000 {</div><div class='add'>+			compatible = "qcom,x1e80100-lpassaudiocc", "qcom,sc8280xp-lpassaudiocc";</div><div class='add'>+			reg = &lt;0 0x06b6c000 0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		swr2: soundwire@6d30000 {</div><div class='add'>+			compatible = "qcom,soundwire-v2.0.0";</div><div class='add'>+			reg = &lt;0 0x06d30000 0 0x10000&gt;;</div><div class='add'>+			clocks = &lt;&amp;lpass_txmacro&gt;;</div><div class='add'>+			clock-names = "iface";</div><div class='add'>+			interrupts = &lt;GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "core", "wakeup";</div><div class='add'>+			label = "TX";</div><div class='add'>+			resets = &lt;&amp;lpasscc LPASS_AUDIO_SWR_TX_CGCR&gt;;</div><div class='add'>+			reset-names = "swr_audio_cgcr";</div><div class='add'>+</div><div class='add'>+			pinctrl-0 = &lt;&amp;tx_swr_active&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+			qcom,din-ports = &lt;4&gt;;</div><div class='add'>+			qcom,dout-ports = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,ports-sinterval-low =	/bits/ 8 &lt;0x00 0x01 0x03 0x03 0x00&gt;;</div><div class='add'>+			qcom,ports-offset1 =		/bits/ 8 &lt;0x00 0x01 0x02 0x00 0x00&gt;;</div><div class='add'>+			qcom,ports-offset2 =		/bits/ 8 &lt;0x00 0x00 0x00 0x00 0xff&gt;;</div><div class='add'>+			qcom,ports-hstart =		/bits/ 8 &lt;0xff 0xff 0xff 0xff 0xff&gt;;</div><div class='add'>+			qcom,ports-hstop =		/bits/ 8 &lt;0xff 0xff 0xff 0xff 0xff&gt;;</div><div class='add'>+			qcom,ports-word-length =	/bits/ 8 &lt;0xff 0xff 0xff 0xff 0xff&gt;;</div><div class='add'>+			qcom,ports-block-pack-mode =	/bits/ 8 &lt;0xff 0xff 0xff 0xff 0xff&gt;;</div><div class='add'>+			qcom,ports-block-group-count =	/bits/ 8 &lt;0xff 0xff 0xff 0xff 0xff&gt;;</div><div class='add'>+			qcom,ports-lane-control =	/bits/ 8 &lt;0xff 0x00 0x00 0x01 0xff&gt;;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		lpass_vamacro: codec@6d44000 {</div><div class='add'>+			compatible = "qcom,x1e80100-lpass-va-macro", "qcom,sm8550-lpass-va-macro";</div><div class='add'>+			reg = &lt;0 0x06d44000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO&gt;,</div><div class='add'>+				 &lt;&amp;q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO&gt;,</div><div class='add'>+				 &lt;&amp;q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO&gt;;</div><div class='add'>+			clock-names = "mclk",</div><div class='add'>+				      "macro",</div><div class='add'>+				      "dcodec";</div><div class='add'>+</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-output-names = "fsgen";</div><div class='add'>+			#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		lpass_tlmm: pinctrl@6e80000 {</div><div class='add'>+			compatible = "qcom,x1e80100-lpass-lpi-pinctrl", "qcom,sm8550-lpass-lpi-pinctrl";</div><div class='add'>+			reg = &lt;0 0x06e80000 0 0x20000&gt;,</div><div class='add'>+			      &lt;0 0x07250000 0 0x10000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO&gt;,</div><div class='add'>+				 &lt;&amp;q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO&gt;;</div><div class='add'>+			clock-names = "core", "audio";</div><div class='add'>+</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;lpass_tlmm 0 0 23&gt;;</div><div class='add'>+</div><div class='add'>+			tx_swr_active: tx-swr-active-state {</div><div class='add'>+				clk-pins {</div><div class='add'>+					pins = "gpio0";</div><div class='add'>+					function = "swr_tx_clk";</div><div class='add'>+					drive-strength = &lt;2&gt;;</div><div class='add'>+					slew-rate = &lt;1&gt;;</div><div class='add'>+					bias-disable;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				data-pins {</div><div class='add'>+					pins = "gpio1", "gpio2";</div><div class='add'>+					function = "swr_tx_data";</div><div class='add'>+					drive-strength = &lt;2&gt;;</div><div class='add'>+					slew-rate = &lt;1&gt;;</div><div class='add'>+					bias-bus-hold;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			rx_swr_active: rx-swr-active-state {</div><div class='add'>+				clk-pins {</div><div class='add'>+					pins = "gpio3";</div><div class='add'>+					function = "swr_rx_clk";</div><div class='add'>+					drive-strength = &lt;2&gt;;</div><div class='add'>+					slew-rate = &lt;1&gt;;</div><div class='add'>+					bias-disable;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				data-pins {</div><div class='add'>+					pins = "gpio4", "gpio5";</div><div class='add'>+					function = "swr_rx_data";</div><div class='add'>+					drive-strength = &lt;2&gt;;</div><div class='add'>+					slew-rate = &lt;1&gt;;</div><div class='add'>+					bias-bus-hold;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			dmic01_default: dmic01-default-state {</div><div class='add'>+				clk-pins {</div><div class='add'>+					pins = "gpio6";</div><div class='add'>+					function = "dmic1_clk";</div><div class='add'>+					drive-strength = &lt;8&gt;;</div><div class='add'>+					output-high;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				data-pins {</div><div class='add'>+					pins = "gpio7";</div><div class='add'>+					function = "dmic1_data";</div><div class='add'>+					drive-strength = &lt;8&gt;;</div><div class='add'>+					input-enable;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			dmic23_default: dmic23-default-state {</div><div class='add'>+				clk-pins {</div><div class='add'>+					pins = "gpio8";</div><div class='add'>+					function = "dmic2_clk";</div><div class='add'>+					drive-strength = &lt;8&gt;;</div><div class='add'>+					output-high;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				data-pins {</div><div class='add'>+					pins = "gpio9";</div><div class='add'>+					function = "dmic2_data";</div><div class='add'>+					drive-strength = &lt;8&gt;;</div><div class='add'>+					input-enable;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			wsa_swr_active: wsa-swr-active-state {</div><div class='add'>+				clk-pins {</div><div class='add'>+					pins = "gpio10";</div><div class='add'>+					function = "wsa_swr_clk";</div><div class='add'>+					drive-strength = &lt;2&gt;;</div><div class='add'>+					slew-rate = &lt;1&gt;;</div><div class='add'>+					bias-disable;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				data-pins {</div><div class='add'>+					pins = "gpio11";</div><div class='add'>+					function = "wsa_swr_data";</div><div class='add'>+					drive-strength = &lt;2&gt;;</div><div class='add'>+					slew-rate = &lt;1&gt;;</div><div class='add'>+					bias-bus-hold;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			wsa2_swr_active: wsa2-swr-active-state {</div><div class='add'>+				clk-pins {</div><div class='add'>+					pins = "gpio15";</div><div class='add'>+					function = "wsa2_swr_clk";</div><div class='add'>+					drive-strength = &lt;2&gt;;</div><div class='add'>+					slew-rate = &lt;1&gt;;</div><div class='add'>+					bias-disable;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				data-pins {</div><div class='add'>+					pins = "gpio16";</div><div class='add'>+					function = "wsa2_swr_data";</div><div class='add'>+					drive-strength = &lt;2&gt;;</div><div class='add'>+					slew-rate = &lt;1&gt;;</div><div class='add'>+					bias-bus-hold;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		lpasscc: clock-controller@6ea0000 {</div><div class='add'>+			compatible = "qcom,x1e80100-lpasscc", "qcom,sc8280xp-lpasscc";</div><div class='add'>+			reg = &lt;0 0x06ea0000 0 0x12000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		lpass_ag_noc: interconnect@7e40000 {</div><div class='add'>+			compatible = "qcom,x1e80100-lpass-ag-noc";</div><div class='add'>+			reg = &lt;0 0x07e40000 0 0xe080&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+</div><div class='add'>+			#interconnect-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		lpass_lpiaon_noc: interconnect@7400000 {</div><div class='add'>+			compatible = "qcom,x1e80100-lpass-lpiaon-noc";</div><div class='add'>+			reg = &lt;0 0x07400000 0 0x19080&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+</div><div class='add'>+			#interconnect-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		lpass_lpicx_noc: interconnect@7430000 {</div><div class='add'>+			compatible = "qcom,x1e80100-lpass-lpicx-noc";</div><div class='add'>+			reg = &lt;0 0x07430000 0 0x3A200&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+</div><div class='add'>+			#interconnect-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sdhc_2: mmc@8804000 {</div><div class='add'>+			compatible = "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5";</div><div class='add'>+			reg = &lt;0 0x08804000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "hc_irq", "pwr_irq";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_SDCC2_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_SDCC2_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;;</div><div class='add'>+			clock-names = "iface", "core", "xo";</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x520 0&gt;;</div><div class='add'>+			qcom,dll-config = &lt;0x0007642c&gt;;</div><div class='add'>+			qcom,ddr-config = &lt;0x80040868&gt;;</div><div class='add'>+			power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;sdhc2_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+					&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY&gt;;</div><div class='add'>+			interconnect-names = "sdhc-ddr", "cpu-sdhc";</div><div class='add'>+			bus-width = &lt;4&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			sdhc2_opp_table: opp-table {</div><div class='add'>+				compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+				opp-19200000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;19200000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_min_svs&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-50000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;50000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-100000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;100000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_svs&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-202000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;202000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_svs_l1&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sdhc_4: mmc@8844000 {</div><div class='add'>+			compatible = "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5";</div><div class='add'>+			reg = &lt;0 0x08844000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "hc_irq", "pwr_irq";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_SDCC4_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_SDCC4_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;;</div><div class='add'>+			clock-names = "iface", "core", "xo";</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x160 0&gt;;</div><div class='add'>+			qcom,dll-config = &lt;0x0007642c&gt;;</div><div class='add'>+			qcom,ddr-config = &lt;0x80040868&gt;;</div><div class='add'>+			power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;sdhc4_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;aggre2_noc MASTER_SDCC_4 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+					&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;config_noc SLAVE_SDCC_4 QCOM_ICC_TAG_ACTIVE_ONLY&gt;;</div><div class='add'>+			interconnect-names = "sdhc-ddr", "cpu-sdhc";</div><div class='add'>+			bus-width = &lt;4&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			sdhc4_opp_table: opp-table {</div><div class='add'>+				compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+				opp-19200000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;19200000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_min_svs&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-50000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;50000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-100000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;100000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_svs&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-202000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;202000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_svs_l1&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_2_hsphy: phy@88e0000 {</div><div class='add'>+			compatible = "qcom,x1e80100-snps-eusb2-phy",</div><div class='add'>+				     "qcom,sm8550-snps-eusb2-phy";</div><div class='add'>+			reg = &lt;0 0x088e0000 0 0x154&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;tcsr TCSR_USB2_2_CLKREF_EN&gt;;</div><div class='add'>+			clock-names = "ref";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_QUSB2PHY_USB20_HS_BCR&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_mp_hsphy0: phy@88e1000 {</div><div class='add'>+			compatible = "qcom,x1e80100-snps-eusb2-phy",</div><div class='add'>+				     "qcom,sm8550-snps-eusb2-phy";</div><div class='add'>+			reg = &lt;0 0x088e1000 0 0x154&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;tcsr TCSR_USB3_MP0_CLKREF_EN&gt;;</div><div class='add'>+			clock-names = "ref";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_QUSB2PHY_HS0_MP_BCR&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_mp_hsphy1: phy@88e2000 {</div><div class='add'>+			compatible = "qcom,x1e80100-snps-eusb2-phy",</div><div class='add'>+				     "qcom,sm8550-snps-eusb2-phy";</div><div class='add'>+			reg = &lt;0 0x088e2000 0 0x154&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;tcsr TCSR_USB3_MP1_CLKREF_EN&gt;;</div><div class='add'>+			clock-names = "ref";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_QUSB2PHY_HS1_MP_BCR&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_mp_qmpphy0: phy@88e3000 {</div><div class='add'>+			compatible = "qcom,x1e80100-qmp-usb3-uni-phy";</div><div class='add'>+			reg = &lt;0 0x088e3000 0 0x2000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_USB3_MP_PHY_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB3_MP_PHY_COM_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB3_MP_PHY_PIPE_0_CLK&gt;;</div><div class='add'>+			clock-names = "aux",</div><div class='add'>+				      "ref",</div><div class='add'>+				      "com_aux",</div><div class='add'>+				      "pipe";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_USB3_UNIPHY_MP0_BCR&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB3UNIPHY_PHY_MP0_BCR&gt;;</div><div class='add'>+			reset-names = "phy",</div><div class='add'>+				      "phy_phy";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;gcc GCC_USB3_MP_SS0_PHY_GDSC&gt;;</div><div class='add'>+</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-output-names = "usb_mp_phy0_pipe_clk";</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_mp_qmpphy1: phy@88e5000 {</div><div class='add'>+			compatible = "qcom,x1e80100-qmp-usb3-uni-phy";</div><div class='add'>+			reg = &lt;0 0x088e5000 0 0x2000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_USB3_MP_PHY_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB3_MP_PHY_COM_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB3_MP_PHY_PIPE_1_CLK&gt;;</div><div class='add'>+			clock-names = "aux",</div><div class='add'>+				      "ref",</div><div class='add'>+				      "com_aux",</div><div class='add'>+				      "pipe";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_USB3_UNIPHY_MP1_BCR&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB3UNIPHY_PHY_MP1_BCR&gt;;</div><div class='add'>+			reset-names = "phy",</div><div class='add'>+				      "phy_phy";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;gcc GCC_USB3_MP_SS1_PHY_GDSC&gt;;</div><div class='add'>+</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-output-names = "usb_mp_phy1_pipe_clk";</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_1_ss2: usb@a0f8800 {</div><div class='add'>+			compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";</div><div class='add'>+			reg = &lt;0 0x0a0f8800 0 0x400&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB30_TERT_MASTER_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_AGGRE_USB3_TERT_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB30_TERT_SLEEP_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB30_TERT_MOCK_UTMI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_AGGRE_USB_NOC_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_SYS_NOC_USB_AXI_CLK&gt;;</div><div class='add'>+			clock-names = "cfg_noc",</div><div class='add'>+				      "core",</div><div class='add'>+				      "iface",</div><div class='add'>+				      "sleep",</div><div class='add'>+				      "mock_utmi",</div><div class='add'>+				      "noc_aggr",</div><div class='add'>+				      "noc_aggr_north",</div><div class='add'>+				      "noc_aggr_south",</div><div class='add'>+				      "noc_sys";</div><div class='add'>+</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_USB30_TERT_MOCK_UTMI_CLK&gt;,</div><div class='add'>+					  &lt;&amp;gcc GCC_USB30_TERT_MASTER_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;19200000&gt;,</div><div class='add'>+					       &lt;200000000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts-extended = &lt;&amp;intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;pdc 58 IRQ_TYPE_EDGE_BOTH&gt;,</div><div class='add'>+					      &lt;&amp;pdc 57 IRQ_TYPE_EDGE_BOTH&gt;,</div><div class='add'>+					      &lt;&amp;pdc 10 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "pwr_event",</div><div class='add'>+					  "dp_hs_phy_irq",</div><div class='add'>+					  "dm_hs_phy_irq",</div><div class='add'>+					  "ss_phy_irq";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;gcc GCC_USB30_TERT_GDSC&gt;;</div><div class='add'>+			required-opps = &lt;&amp;rpmhpd_opp_nom&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_USB30_TERT_BCR&gt;;</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;usb_south_anoc MASTER_USB3_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+					&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;config_noc SLAVE_USB3_2 QCOM_ICC_TAG_ACTIVE_ONLY&gt;;</div><div class='add'>+			interconnect-names = "usb-ddr",</div><div class='add'>+					     "apps-usb";</div><div class='add'>+</div><div class='add'>+			wakeup-source;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			usb_1_ss2_dwc3: usb@a000000 {</div><div class='add'>+				compatible = "snps,dwc3";</div><div class='add'>+				reg = &lt;0 0x0a000000 0 0xcd00&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				iommus = &lt;&amp;apps_smmu 0x14a0 0x0&gt;;</div><div class='add'>+</div><div class='add'>+				phys = &lt;&amp;usb_1_ss2_hsphy&gt;,</div><div class='add'>+				       &lt;&amp;usb_1_ss2_qmpphy QMP_USB43DP_USB3_PHY&gt;;</div><div class='add'>+				phy-names = "usb2-phy",</div><div class='add'>+				            "usb3-phy";</div><div class='add'>+</div><div class='add'>+				snps,dis_u2_susphy_quirk;</div><div class='add'>+				snps,dis_enblslpm_quirk;</div><div class='add'>+				snps,usb3_lpm_capable;</div><div class='add'>+				snps,dis-u1-entry-quirk;</div><div class='add'>+				snps,dis-u2-entry-quirk;</div><div class='add'>+</div><div class='add'>+				dma-coherent;</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						usb_1_ss2_dwc3_hs: endpoint {</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						usb_1_ss2_dwc3_ss: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;usb_1_ss2_qmpphy_usb_ss_in&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_2: usb@a2f8800 {</div><div class='add'>+			compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";</div><div class='add'>+			reg = &lt;0 0x0a2f8800 0 0x400&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB20_MASTER_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_AGGRE_USB2_PRIM_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB20_SLEEP_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB20_MOCK_UTMI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_AGGRE_USB_NOC_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_SYS_NOC_USB_AXI_CLK&gt;;</div><div class='add'>+			clock-names = "cfg_noc",</div><div class='add'>+				      "core",</div><div class='add'>+				      "iface",</div><div class='add'>+				      "sleep",</div><div class='add'>+				      "mock_utmi",</div><div class='add'>+				      "noc_aggr",</div><div class='add'>+				      "noc_aggr_north",</div><div class='add'>+				      "noc_aggr_south",</div><div class='add'>+				      "noc_sys";</div><div class='add'>+</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_USB20_MOCK_UTMI_CLK&gt;,</div><div class='add'>+					  &lt;&amp;gcc GCC_USB20_MASTER_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;19200000&gt;, &lt;200000000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts-extended = &lt;&amp;intc GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;pdc 50 IRQ_TYPE_EDGE_BOTH&gt;,</div><div class='add'>+					      &lt;&amp;pdc 49 IRQ_TYPE_EDGE_BOTH&gt;;</div><div class='add'>+			interrupt-names = "pwr_event",</div><div class='add'>+					  "dp_hs_phy_irq",</div><div class='add'>+					  "dm_hs_phy_irq";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;gcc GCC_USB20_PRIM_GDSC&gt;;</div><div class='add'>+			required-opps = &lt;&amp;rpmhpd_opp_nom&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_USB20_PRIM_BCR&gt;;</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;usb_north_anoc MASTER_USB2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+					&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;config_noc SLAVE_USB2 QCOM_ICC_TAG_ACTIVE_ONLY&gt;;</div><div class='add'>+			interconnect-names = "usb-ddr",</div><div class='add'>+					     "apps-usb";</div><div class='add'>+</div><div class='add'>+			qcom,select-utmi-as-pipe-clk;</div><div class='add'>+			wakeup-source;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			usb_2_dwc3: usb@a200000 {</div><div class='add'>+				compatible = "snps,dwc3";</div><div class='add'>+				reg = &lt;0 0x0a200000 0 0xcd00&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				iommus = &lt;&amp;apps_smmu 0x14e0 0x0&gt;;</div><div class='add'>+				phys = &lt;&amp;usb_2_hsphy&gt;;</div><div class='add'>+				phy-names = "usb2-phy";</div><div class='add'>+				maximum-speed = "high-speed";</div><div class='add'>+				snps,dis-u1-entry-quirk;</div><div class='add'>+				snps,dis-u2-entry-quirk;</div><div class='add'>+</div><div class='add'>+				dma-coherent;</div><div class='add'>+</div><div class='add'>+				port {</div><div class='add'>+					usb_2_dwc3_hs: endpoint {</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_mp: usb@a4f8800 {</div><div class='add'>+			compatible = "qcom,x1e80100-dwc3-mp", "qcom,dwc3";</div><div class='add'>+			reg = &lt;0 0x0a4f8800 0 0x400&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_CFG_NOC_USB3_MP_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB30_MP_MASTER_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_AGGRE_USB3_MP_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB30_MP_SLEEP_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB30_MP_MOCK_UTMI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_AGGRE_USB_NOC_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_SYS_NOC_USB_AXI_CLK&gt;;</div><div class='add'>+			clock-names = "cfg_noc",</div><div class='add'>+				      "core",</div><div class='add'>+				      "iface",</div><div class='add'>+				      "sleep",</div><div class='add'>+				      "mock_utmi",</div><div class='add'>+				      "noc_aggr",</div><div class='add'>+				      "noc_aggr_north",</div><div class='add'>+				      "noc_aggr_south",</div><div class='add'>+				      "noc_sys";</div><div class='add'>+</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_USB30_MP_MOCK_UTMI_CLK&gt;,</div><div class='add'>+					  &lt;&amp;gcc GCC_USB30_MP_MASTER_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;19200000&gt;,</div><div class='add'>+					       &lt;200000000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts-extended = &lt;&amp;intc GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;intc GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;intc GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;intc GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;pdc 52 IRQ_TYPE_EDGE_BOTH&gt;,</div><div class='add'>+					      &lt;&amp;pdc 51 IRQ_TYPE_EDGE_BOTH&gt;,</div><div class='add'>+					      &lt;&amp;pdc 54 IRQ_TYPE_EDGE_BOTH&gt;,</div><div class='add'>+					      &lt;&amp;pdc 53 IRQ_TYPE_EDGE_BOTH&gt;,</div><div class='add'>+					      &lt;&amp;pdc 55 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;pdc 56 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "pwr_event_1", "pwr_event_2",</div><div class='add'>+					  "hs_phy_1",	 "hs_phy_2",</div><div class='add'>+					  "dp_hs_phy_1", "dm_hs_phy_1",</div><div class='add'>+					  "dp_hs_phy_2", "dm_hs_phy_2",</div><div class='add'>+					  "ss_phy_1",	 "ss_phy_2";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;gcc GCC_USB30_MP_GDSC&gt;;</div><div class='add'>+			required-opps = &lt;&amp;rpmhpd_opp_nom&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_USB30_MP_BCR&gt;;</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;usb_north_anoc MASTER_USB3_MP QCOM_ICC_TAG_ALWAYS</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+					&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;config_noc SLAVE_USB3_MP QCOM_ICC_TAG_ACTIVE_ONLY&gt;;</div><div class='add'>+			interconnect-names = "usb-ddr",</div><div class='add'>+					     "apps-usb";</div><div class='add'>+</div><div class='add'>+			wakeup-source;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			usb_mp_dwc3: usb@a400000 {</div><div class='add'>+				compatible = "snps,dwc3";</div><div class='add'>+				reg = &lt;0 0x0a400000 0 0xcd00&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				iommus = &lt;&amp;apps_smmu 0x1400 0x0&gt;;</div><div class='add'>+</div><div class='add'>+				phys = &lt;&amp;usb_mp_hsphy0&gt;, &lt;&amp;usb_mp_qmpphy0&gt;,</div><div class='add'>+				       &lt;&amp;usb_mp_hsphy1&gt;, &lt;&amp;usb_mp_qmpphy1&gt;;</div><div class='add'>+				phy-names = "usb2-0", "usb3-0",</div><div class='add'>+					    "usb2-1", "usb3-1";</div><div class='add'>+				dr_mode = "host";</div><div class='add'>+</div><div class='add'>+				snps,dis_u2_susphy_quirk;</div><div class='add'>+				snps,dis_enblslpm_quirk;</div><div class='add'>+				snps,usb3_lpm_capable;</div><div class='add'>+				snps,dis-u1-entry-quirk;</div><div class='add'>+				snps,dis-u2-entry-quirk;</div><div class='add'>+</div><div class='add'>+				dma-coherent;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_1_ss0: usb@a6f8800 {</div><div class='add'>+			compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";</div><div class='add'>+			reg = &lt;0 0x0a6f8800 0 0x400&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB30_PRIM_MASTER_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_AGGRE_USB3_PRIM_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB30_PRIM_SLEEP_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB30_PRIM_MOCK_UTMI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_AGGRE_USB_NOC_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_CFG_NOC_USB_ANOC_NORTH_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_SYS_NOC_USB_AXI_CLK&gt;;</div><div class='add'>+			clock-names = "cfg_noc",</div><div class='add'>+				      "core",</div><div class='add'>+				      "iface",</div><div class='add'>+				      "sleep",</div><div class='add'>+				      "mock_utmi",</div><div class='add'>+				      "noc_aggr",</div><div class='add'>+				      "noc_aggr_north",</div><div class='add'>+				      "noc_aggr_south",</div><div class='add'>+				      "noc_sys";</div><div class='add'>+</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_USB30_PRIM_MOCK_UTMI_CLK&gt;,</div><div class='add'>+					  &lt;&amp;gcc GCC_USB30_PRIM_MASTER_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;19200000&gt;,</div><div class='add'>+					       &lt;200000000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts-extended = &lt;&amp;intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;pdc 61 IRQ_TYPE_EDGE_BOTH&gt;,</div><div class='add'>+					      &lt;&amp;pdc 15 IRQ_TYPE_EDGE_BOTH&gt;,</div><div class='add'>+					      &lt;&amp;pdc 17 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "pwr_event",</div><div class='add'>+					  "dp_hs_phy_irq",</div><div class='add'>+					  "dm_hs_phy_irq",</div><div class='add'>+					  "ss_phy_irq";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;gcc GCC_USB30_PRIM_GDSC&gt;;</div><div class='add'>+			required-opps = &lt;&amp;rpmhpd_opp_nom&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_USB30_PRIM_BCR&gt;;</div><div class='add'>+</div><div class='add'>+			wakeup-source;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			usb_1_ss0_dwc3: usb@a600000 {</div><div class='add'>+				compatible = "snps,dwc3";</div><div class='add'>+				reg = &lt;0 0x0a600000 0 0xcd00&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				iommus = &lt;&amp;apps_smmu 0x1420 0x0&gt;;</div><div class='add'>+</div><div class='add'>+				phys = &lt;&amp;usb_1_ss0_hsphy&gt;,</div><div class='add'>+				       &lt;&amp;usb_1_ss0_qmpphy QMP_USB43DP_USB3_PHY&gt;;</div><div class='add'>+				phy-names = "usb2-phy",</div><div class='add'>+					    "usb3-phy";</div><div class='add'>+</div><div class='add'>+				snps,dis_u2_susphy_quirk;</div><div class='add'>+				snps,dis_enblslpm_quirk;</div><div class='add'>+				snps,usb3_lpm_capable;</div><div class='add'>+				snps,dis-u1-entry-quirk;</div><div class='add'>+				snps,dis-u2-entry-quirk;</div><div class='add'>+</div><div class='add'>+				dma-coherent;</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						usb_1_ss0_dwc3_hs: endpoint {</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						usb_1_ss0_dwc3_ss: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;usb_1_ss0_qmpphy_usb_ss_in&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_1_ss1: usb@a8f8800 {</div><div class='add'>+			compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";</div><div class='add'>+			reg = &lt;0 0x0a8f8800 0 0x400&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB30_SEC_MASTER_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_AGGRE_USB3_SEC_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB30_SEC_SLEEP_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB30_SEC_MOCK_UTMI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_AGGRE_USB_NOC_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_SYS_NOC_USB_AXI_CLK&gt;;</div><div class='add'>+			clock-names = "cfg_noc",</div><div class='add'>+				      "core",</div><div class='add'>+				      "iface",</div><div class='add'>+				      "sleep",</div><div class='add'>+				      "mock_utmi",</div><div class='add'>+				      "noc_aggr",</div><div class='add'>+				      "noc_aggr_north",</div><div class='add'>+				      "noc_aggr_south",</div><div class='add'>+				      "noc_sys";</div><div class='add'>+</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_USB30_SEC_MOCK_UTMI_CLK&gt;,</div><div class='add'>+					  &lt;&amp;gcc GCC_USB30_SEC_MASTER_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;19200000&gt;,</div><div class='add'>+					       &lt;200000000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts-extended = &lt;&amp;intc GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;pdc 60 IRQ_TYPE_EDGE_BOTH&gt;,</div><div class='add'>+					      &lt;&amp;pdc 11 IRQ_TYPE_EDGE_BOTH&gt;,</div><div class='add'>+					      &lt;&amp;pdc 47 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "pwr_event",</div><div class='add'>+					  "dp_hs_phy_irq",</div><div class='add'>+					  "dm_hs_phy_irq",</div><div class='add'>+					  "ss_phy_irq";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;gcc GCC_USB30_SEC_GDSC&gt;;</div><div class='add'>+			required-opps = &lt;&amp;rpmhpd_opp_nom&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_USB30_SEC_BCR&gt;;</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;usb_south_anoc MASTER_USB3_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+					&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;config_noc SLAVE_USB3_1 QCOM_ICC_TAG_ACTIVE_ONLY&gt;;</div><div class='add'>+			interconnect-names = "usb-ddr",</div><div class='add'>+					     "apps-usb";</div><div class='add'>+</div><div class='add'>+			wakeup-source;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			usb_1_ss1_dwc3: usb@a800000 {</div><div class='add'>+				compatible = "snps,dwc3";</div><div class='add'>+				reg = &lt;0 0x0a800000 0 0xcd00&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				iommus = &lt;&amp;apps_smmu 0x1460 0x0&gt;;</div><div class='add'>+</div><div class='add'>+				phys = &lt;&amp;usb_1_ss1_hsphy&gt;,</div><div class='add'>+				       &lt;&amp;usb_1_ss1_qmpphy QMP_USB43DP_USB3_PHY&gt;;</div><div class='add'>+				phy-names = "usb2-phy",</div><div class='add'>+					    "usb3-phy";</div><div class='add'>+</div><div class='add'>+				snps,dis_u2_susphy_quirk;</div><div class='add'>+				snps,dis_enblslpm_quirk;</div><div class='add'>+				snps,usb3_lpm_capable;</div><div class='add'>+				snps,dis-u1-entry-quirk;</div><div class='add'>+				snps,dis-u2-entry-quirk;</div><div class='add'>+</div><div class='add'>+				dma-coherent;</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						usb_1_ss1_dwc3_hs: endpoint {</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						usb_1_ss1_dwc3_ss: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;usb_1_ss1_qmpphy_usb_ss_in&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		iris: video-codec@aa00000 {</div><div class='add'>+			compatible = "qcom,x1e80100-iris", "qcom,sm8550-iris";</div><div class='add'>+</div><div class='add'>+			reg = &lt;0 0x0aa00000 0 0xf0000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;videocc VIDEO_CC_MVS0C_GDSC&gt;,</div><div class='add'>+					&lt;&amp;videocc VIDEO_CC_MVS0_GDSC&gt;,</div><div class='add'>+					&lt;&amp;rpmhpd RPMHPD_MXC&gt;,</div><div class='add'>+					&lt;&amp;rpmhpd RPMHPD_MMCX&gt;;</div><div class='add'>+			power-domain-names = "venus",</div><div class='add'>+					     "vcodec0",</div><div class='add'>+					     "mxc",</div><div class='add'>+					     "mmcx";</div><div class='add'>+			operating-points-v2 = &lt;&amp;iris_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_VIDEO_AXI0_CLK&gt;,</div><div class='add'>+				 &lt;&amp;videocc VIDEO_CC_MVS0C_CLK&gt;,</div><div class='add'>+				 &lt;&amp;videocc VIDEO_CC_MVS0_CLK&gt;;</div><div class='add'>+			clock-names = "iface",</div><div class='add'>+				      "core",</div><div class='add'>+				      "vcodec0_core";</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+					&lt;&amp;mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+			interconnect-names = "cpu-cfg",</div><div class='add'>+					     "video-mem";</div><div class='add'>+</div><div class='add'>+			memory-region = &lt;&amp;video_mem&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_VIDEO_AXI0_CLK_ARES&gt;;</div><div class='add'>+			reset-names = "bus";</div><div class='add'>+</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x1940 0&gt;,</div><div class='add'>+				 &lt;&amp;apps_smmu 0x1947 0&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+</div><div class='add'>+			/*</div><div class='add'>+			 * IRIS firmware is signed by vendors, only</div><div class='add'>+			 * enable on boards where the proper signed firmware</div><div class='add'>+			 * is available.</div><div class='add'>+			 */</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			iris_opp_table: opp-table {</div><div class='add'>+				compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+				opp-192000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;192000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_low_svs_d1&gt;,</div><div class='add'>+							&lt;&amp;rpmhpd_opp_low_svs_d1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-240000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;240000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_svs&gt;,</div><div class='add'>+							&lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-338000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;338000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_svs&gt;,</div><div class='add'>+							&lt;&amp;rpmhpd_opp_svs&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-366000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;366000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_svs_l1&gt;,</div><div class='add'>+							&lt;&amp;rpmhpd_opp_svs_l1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-444000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;444000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_nom&gt;,</div><div class='add'>+							&lt;&amp;rpmhpd_opp_nom&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-481000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;481000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_turbo&gt;,</div><div class='add'>+							&lt;&amp;rpmhpd_opp_turbo&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		videocc: clock-controller@aaf0000 {</div><div class='add'>+			compatible = "qcom,x1e80100-videocc";</div><div class='add'>+			reg = &lt;0 0x0aaf0000 0 0x10000&gt;;</div><div class='add'>+			clocks = &lt;&amp;bi_tcxo_div2&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_VIDEO_AHB_CLK&gt;;</div><div class='add'>+			power-domains = &lt;&amp;rpmhpd RPMHPD_MMCX&gt;,</div><div class='add'>+					&lt;&amp;rpmhpd RPMHPD_MXC&gt;;</div><div class='add'>+			required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;,</div><div class='add'>+					&lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdss: display-subsystem@ae00000 {</div><div class='add'>+			compatible = "qcom,x1e80100-mdss";</div><div class='add'>+			reg = &lt;0 0x0ae00000 0 0x1000&gt;;</div><div class='add'>+			reg-names = "mdss";</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;dispcc DISP_CC_MDSS_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_DISP_HF_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;dispcc DISP_CC_MDSS_MDP_CLK&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;dispcc DISP_CC_MDSS_CORE_BCR&gt;;</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS</div><div class='add'>+					 &amp;gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+					&lt;&amp;mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+					&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY&gt;;</div><div class='add'>+			interconnect-names = "mdp0-mem",</div><div class='add'>+					     "mdp1-mem",</div><div class='add'>+					     "cpu-cfg";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;dispcc MDSS_GDSC&gt;;</div><div class='add'>+</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x1c00 0x2&gt;;</div><div class='add'>+</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			mdss_mdp: display-controller@ae01000 {</div><div class='add'>+				compatible = "qcom,x1e80100-dpu";</div><div class='add'>+				reg = &lt;0 0x0ae01000 0 0x8f000&gt;,</div><div class='add'>+				      &lt;0 0x0aeb0000 0 0x2008&gt;;</div><div class='add'>+				reg-names = "mdp",</div><div class='add'>+					    "vbif";</div><div class='add'>+</div><div class='add'>+				interrupts-extended = &lt;&amp;mdss 0&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_DISP_HF_AXI_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc DISP_CC_MDSS_AHB_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc DISP_CC_MDSS_MDP_LUT_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc DISP_CC_MDSS_MDP_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc DISP_CC_MDSS_VSYNC_CLK&gt;;</div><div class='add'>+				clock-names = "nrt_bus",</div><div class='add'>+					      "iface",</div><div class='add'>+					      "lut",</div><div class='add'>+					      "core",</div><div class='add'>+					      "vsync";</div><div class='add'>+</div><div class='add'>+				operating-points-v2 = &lt;&amp;mdp_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_MMCX&gt;;</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						mdss_intf0_out: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mdss_dp0_in&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@4 {</div><div class='add'>+						reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+						mdss_intf4_out: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mdss_dp1_in&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@5 {</div><div class='add'>+						reg = &lt;5&gt;;</div><div class='add'>+</div><div class='add'>+						mdss_intf5_out: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mdss_dp3_in&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@6 {</div><div class='add'>+						reg = &lt;6&gt;;</div><div class='add'>+</div><div class='add'>+						mdss_intf6_out: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mdss_dp2_in&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				mdp_opp_table: opp-table {</div><div class='add'>+					compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+					opp-200000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;200000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					opp-325000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;325000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_svs&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					opp-375000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;375000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_svs_l1&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					opp-514000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;514000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_nom&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					opp-575000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;575000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_nom_l1&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mdss_dp0: displayport-controller@ae90000 {</div><div class='add'>+				compatible = "qcom,x1e80100-dp";</div><div class='add'>+				reg = &lt;0 0x0ae90000 0 0x200&gt;,</div><div class='add'>+				      &lt;0 0x0ae90200 0 0x200&gt;,</div><div class='add'>+				      &lt;0 0x0ae90400 0 0xc00&gt;,</div><div class='add'>+				      &lt;0 0x0ae91000 0 0x400&gt;,</div><div class='add'>+				      &lt;0 0x0ae91400 0 0x400&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts-extended = &lt;&amp;mdss 12&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;dispcc DISP_CC_MDSS_AHB_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc DISP_CC_MDSS_DPTX0_AUX_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc DISP_CC_MDSS_DPTX0_LINK_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK&gt;;</div><div class='add'>+				clock-names = "core_iface",</div><div class='add'>+					      "core_aux",</div><div class='add'>+					      "ctrl_link",</div><div class='add'>+					      "ctrl_link_iface",</div><div class='add'>+					      "stream_pixel",</div><div class='add'>+					      "stream_1_pixel";</div><div class='add'>+</div><div class='add'>+				assigned-clocks = &lt;&amp;dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC&gt;,</div><div class='add'>+						  &lt;&amp;dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC&gt;,</div><div class='add'>+						  &lt;&amp;dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK&gt;,</div><div class='add'>+							 &lt;&amp;usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK&gt;,</div><div class='add'>+							 &lt;&amp;usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK&gt;;</div><div class='add'>+</div><div class='add'>+				operating-points-v2 = &lt;&amp;mdss_dp0_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_MMCX&gt;;</div><div class='add'>+</div><div class='add'>+				phys = &lt;&amp;usb_1_ss0_qmpphy QMP_USB43DP_DP_PHY&gt;;</div><div class='add'>+				phy-names = "dp";</div><div class='add'>+</div><div class='add'>+				#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						mdss_dp0_in: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mdss_intf0_out&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						mdss_dp0_out: endpoint {</div><div class='add'>+							data-lanes = &lt;0 1 2 3&gt;;</div><div class='add'>+							remote-endpoint = &lt;&amp;usb_1_ss0_qmpphy_dp_in&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				mdss_dp0_opp_table: opp-table {</div><div class='add'>+					compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+					opp-160000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;160000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					opp-270000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;270000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_svs&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					opp-540000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;540000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_svs_l1&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					opp-810000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;810000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_nom&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mdss_dp1: displayport-controller@ae98000 {</div><div class='add'>+				compatible = "qcom,x1e80100-dp";</div><div class='add'>+				reg = &lt;0 0x0ae98000 0 0x200&gt;,</div><div class='add'>+				      &lt;0 0x0ae98200 0 0x200&gt;,</div><div class='add'>+				      &lt;0 0x0ae98400 0 0xc00&gt;,</div><div class='add'>+				      &lt;0 0x0ae99000 0 0x400&gt;,</div><div class='add'>+				      &lt;0 0x0ae99400 0 0x400&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts-extended = &lt;&amp;mdss 13&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;dispcc DISP_CC_MDSS_AHB_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc DISP_CC_MDSS_DPTX1_AUX_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc DISP_CC_MDSS_DPTX1_LINK_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK&gt;;</div><div class='add'>+				clock-names = "core_iface",</div><div class='add'>+					      "core_aux",</div><div class='add'>+					      "ctrl_link",</div><div class='add'>+					      "ctrl_link_iface",</div><div class='add'>+					      "stream_pixel",</div><div class='add'>+					      "stream_1_pixel";</div><div class='add'>+</div><div class='add'>+				assigned-clocks = &lt;&amp;dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC&gt;,</div><div class='add'>+						  &lt;&amp;dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC&gt;,</div><div class='add'>+						  &lt;&amp;dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK&gt;,</div><div class='add'>+							 &lt;&amp;usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK&gt;,</div><div class='add'>+							 &lt;&amp;usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK&gt;;</div><div class='add'>+</div><div class='add'>+				operating-points-v2 = &lt;&amp;mdss_dp1_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_MMCX&gt;;</div><div class='add'>+</div><div class='add'>+				phys = &lt;&amp;usb_1_ss1_qmpphy QMP_USB43DP_DP_PHY&gt;;</div><div class='add'>+				phy-names = "dp";</div><div class='add'>+</div><div class='add'>+				#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						mdss_dp1_in: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mdss_intf4_out&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						mdss_dp1_out: endpoint {</div><div class='add'>+							data-lanes = &lt;0 1 2 3&gt;;</div><div class='add'>+							remote-endpoint = &lt;&amp;usb_1_ss1_qmpphy_dp_in&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				mdss_dp1_opp_table: opp-table {</div><div class='add'>+					compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+					opp-160000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;160000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					opp-270000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;270000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_svs&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					opp-540000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;540000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_svs_l1&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					opp-810000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;810000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_nom&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mdss_dp2: displayport-controller@ae9a000 {</div><div class='add'>+				compatible = "qcom,x1e80100-dp";</div><div class='add'>+				reg = &lt;0 0x0ae9a000 0 0x200&gt;,</div><div class='add'>+				      &lt;0 0x0ae9a200 0 0x200&gt;,</div><div class='add'>+				      &lt;0 0x0ae9a400 0 0xc00&gt;,</div><div class='add'>+				      &lt;0 0x0ae9b000 0 0x400&gt;,</div><div class='add'>+				      &lt;0 0x0ae9b400 0 0x400&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts-extended = &lt;&amp;mdss 14&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;dispcc DISP_CC_MDSS_AHB_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc DISP_CC_MDSS_DPTX2_AUX_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc DISP_CC_MDSS_DPTX2_LINK_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK&gt;;</div><div class='add'>+				clock-names = "core_iface",</div><div class='add'>+					      "core_aux",</div><div class='add'>+					      "ctrl_link",</div><div class='add'>+					      "ctrl_link_iface",</div><div class='add'>+					      "stream_pixel",</div><div class='add'>+					      "stream_1_pixel";</div><div class='add'>+</div><div class='add'>+				assigned-clocks = &lt;&amp;dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC&gt;,</div><div class='add'>+						  &lt;&amp;dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC&gt;,</div><div class='add'>+						  &lt;&amp;dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK&gt;,</div><div class='add'>+							 &lt;&amp;usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK&gt;,</div><div class='add'>+							 &lt;&amp;usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK&gt;;</div><div class='add'>+</div><div class='add'>+				operating-points-v2 = &lt;&amp;mdss_dp2_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_MMCX&gt;;</div><div class='add'>+</div><div class='add'>+				phys = &lt;&amp;usb_1_ss2_qmpphy QMP_USB43DP_DP_PHY&gt;;</div><div class='add'>+				phy-names = "dp";</div><div class='add'>+</div><div class='add'>+				#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+						mdss_dp2_in: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mdss_intf6_out&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						mdss_dp2_out: endpoint {</div><div class='add'>+							data-lanes = &lt;0 1 2 3&gt;;</div><div class='add'>+							remote-endpoint = &lt;&amp;usb_1_ss2_qmpphy_dp_in&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				mdss_dp2_opp_table: opp-table {</div><div class='add'>+					compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+					opp-160000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;160000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					opp-270000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;270000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_svs&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					opp-540000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;540000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_svs_l1&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					opp-810000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;810000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_nom&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mdss_dp3: displayport-controller@aea0000 {</div><div class='add'>+				compatible = "qcom,x1e80100-dp";</div><div class='add'>+				reg = &lt;0 0x0aea0000 0 0x200&gt;,</div><div class='add'>+				      &lt;0 0x0aea0200 0 0x200&gt;,</div><div class='add'>+				      &lt;0 0x0aea0400 0 0xc00&gt;,</div><div class='add'>+				      &lt;0 0x0aea1000 0 0x400&gt;,</div><div class='add'>+				      &lt;0 0x0aea1400 0 0x400&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts-extended = &lt;&amp;mdss 15&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;dispcc DISP_CC_MDSS_AHB_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc DISP_CC_MDSS_DPTX3_AUX_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc DISP_CC_MDSS_DPTX3_LINK_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc DISP_CC_MDSS_DPTX3_LINK_INTF_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK&gt;;</div><div class='add'>+				clock-names = "core_iface",</div><div class='add'>+					      "core_aux",</div><div class='add'>+					      "ctrl_link",</div><div class='add'>+					      "ctrl_link_iface",</div><div class='add'>+					      "stream_pixel";</div><div class='add'>+</div><div class='add'>+				assigned-clocks = &lt;&amp;dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC&gt;,</div><div class='add'>+						  &lt;&amp;dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;mdss_dp3_phy 0&gt;,</div><div class='add'>+							 &lt;&amp;mdss_dp3_phy 1&gt;;</div><div class='add'>+</div><div class='add'>+				operating-points-v2 = &lt;&amp;mdss_dp3_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_MMCX&gt;;</div><div class='add'>+</div><div class='add'>+				phys = &lt;&amp;mdss_dp3_phy&gt;;</div><div class='add'>+				phy-names = "dp";</div><div class='add'>+</div><div class='add'>+				#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						mdss_dp3_in: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mdss_intf5_out&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						mdss_dp3_out: endpoint {</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				mdss_dp3_opp_table: opp-table {</div><div class='add'>+					compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+					opp-160000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;160000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					opp-270000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;270000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_svs&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					opp-540000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;540000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_svs_l1&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					opp-810000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;810000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_nom&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdss_dp2_phy: phy@aec2a00 {</div><div class='add'>+			compatible = "qcom,x1e80100-dp-phy";</div><div class='add'>+			reg = &lt;0 0x0aec2a00 0 0x19c&gt;,</div><div class='add'>+			      &lt;0 0x0aec2200 0 0xec&gt;,</div><div class='add'>+			      &lt;0 0x0aec2600 0 0xec&gt;,</div><div class='add'>+			      &lt;0 0x0aec2000 0 0x1c8&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;dispcc DISP_CC_MDSS_DPTX2_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;dispcc DISP_CC_MDSS_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "aux",</div><div class='add'>+				      "cfg_ahb";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;rpmhpd RPMHPD_MX&gt;;</div><div class='add'>+</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdss_dp3_phy: phy@aec5a00 {</div><div class='add'>+			compatible = "qcom,x1e80100-dp-phy";</div><div class='add'>+			reg = &lt;0 0x0aec5a00 0 0x19c&gt;,</div><div class='add'>+			      &lt;0 0x0aec5200 0 0xec&gt;,</div><div class='add'>+			      &lt;0 0x0aec5600 0 0xec&gt;,</div><div class='add'>+			      &lt;0 0x0aec5000 0 0x1c8&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;dispcc DISP_CC_MDSS_DPTX3_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;dispcc DISP_CC_MDSS_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "aux",</div><div class='add'>+				      "cfg_ahb";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;rpmhpd RPMHPD_MX&gt;;</div><div class='add'>+</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dispcc: clock-controller@af00000 {</div><div class='add'>+			compatible = "qcom,x1e80100-dispcc";</div><div class='add'>+			reg = &lt;0 0x0af00000 0 0x20000&gt;;</div><div class='add'>+			clocks = &lt;&amp;bi_tcxo_div2&gt;,</div><div class='add'>+				 &lt;&amp;bi_tcxo_ao_div2&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_DISP_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;sleep_clk&gt;,</div><div class='add'>+				 &lt;0&gt;, /* dsi0 */</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;, /* dsi1 */</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;&amp;usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK&gt;, /* dp0 */</div><div class='add'>+				 &lt;&amp;usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK&gt;,</div><div class='add'>+				 &lt;&amp;usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK&gt;, /* dp1 */</div><div class='add'>+				 &lt;&amp;usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK&gt;,</div><div class='add'>+				 &lt;&amp;usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK&gt;, /* dp2 */</div><div class='add'>+				 &lt;&amp;usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK&gt;,</div><div class='add'>+				 &lt;&amp;mdss_dp3_phy 0&gt;, /* dp3 */</div><div class='add'>+				 &lt;&amp;mdss_dp3_phy 1&gt;;</div><div class='add'>+			power-domains = &lt;&amp;rpmhpd RPMHPD_MMCX&gt;;</div><div class='add'>+			required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pdc: interrupt-controller@b220000 {</div><div class='add'>+			compatible = "qcom,x1e80100-pdc", "qcom,pdc";</div><div class='add'>+			reg = &lt;0 0x0b220000 0 0x30000&gt;, &lt;0 0x174000f0 0 0x64&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,pdc-ranges = &lt;0 480 42&gt;, &lt;42 251 5&gt;,</div><div class='add'>+					  &lt;47 522 52&gt;, &lt;99 609 32&gt;,</div><div class='add'>+					  &lt;131 717 12&gt;, &lt;143 816 19&gt;;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;intc&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aoss_qmp: power-management@c300000 {</div><div class='add'>+			compatible = "qcom,x1e80100-aoss-qmp", "qcom,aoss-qmp";</div><div class='add'>+			reg = &lt;0 0x0c300000 0 0x400&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;ipcc&gt;;</div><div class='add'>+			interrupts-extended = &lt;&amp;ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP</div><div class='add'>+						     IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			mboxes = &lt;&amp;ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP&gt;;</div><div class='add'>+</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sram@c3f0000 {</div><div class='add'>+			compatible = "qcom,rpmh-stats";</div><div class='add'>+			reg = &lt;0 0x0c3f0000 0 0x400&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spmi: arbiter@c400000 {</div><div class='add'>+			compatible = "qcom,x1e80100-spmi-pmic-arb";</div><div class='add'>+			reg = &lt;0 0x0c400000 0 0x3000&gt;,</div><div class='add'>+			      &lt;0 0x0c500000 0 0x400000&gt;,</div><div class='add'>+			      &lt;0 0x0c440000 0 0x80000&gt;;</div><div class='add'>+			reg-names = "core", "chnls", "obsrvr";</div><div class='add'>+</div><div class='add'>+			qcom,ee = &lt;0&gt;;</div><div class='add'>+			qcom,channel = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			spmi_bus0: spmi@c42d000 {</div><div class='add'>+				reg = &lt;0 0x0c42d000 0 0x4000&gt;,</div><div class='add'>+				      &lt;0 0x0c4c0000 0 0x10000&gt;;</div><div class='add'>+				reg-names = "cnfg", "intr";</div><div class='add'>+</div><div class='add'>+				interrupt-names = "periph_irq";</div><div class='add'>+				interrupts-extended = &lt;&amp;pdc 1 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;2&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spmi_bus1: spmi@c432000 {</div><div class='add'>+				reg = &lt;0 0x0c432000 0 0x4000&gt;,</div><div class='add'>+				      &lt;0 0x0c4d0000 0 0x10000&gt;;</div><div class='add'>+				reg-names = "cnfg", "intr";</div><div class='add'>+</div><div class='add'>+				interrupt-names = "periph_irq";</div><div class='add'>+				interrupts-extended = &lt;&amp;pdc 3 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				interrupt-controller;</div><div class='add'>+				#interrupt-cells = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;2&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tlmm: pinctrl@f100000 {</div><div class='add'>+			compatible = "qcom,x1e80100-tlmm";</div><div class='add'>+			reg = &lt;0 0x0f100000 0 0xf00000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			gpio-ranges = &lt;&amp;tlmm 0 0 239&gt;;</div><div class='add'>+			wakeup-parent = &lt;&amp;pdc&gt;;</div><div class='add'>+</div><div class='add'>+			edp0_hpd_default: edp0-hpd-default-state {</div><div class='add'>+				pins = "gpio119";</div><div class='add'>+				function = "edp0_hot";</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c0_data_clk: qup-i2c0-data-clk-state {</div><div class='add'>+				/* SDA, SCL */</div><div class='add'>+				pins = "gpio0", "gpio1";</div><div class='add'>+				function = "qup0_se0";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up = &lt;2200&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c1_data_clk: qup-i2c1-data-clk-state {</div><div class='add'>+				/* SDA, SCL */</div><div class='add'>+				pins = "gpio4", "gpio5";</div><div class='add'>+				function = "qup0_se1";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up = &lt;2200&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c2_data_clk: qup-i2c2-data-clk-state {</div><div class='add'>+				/* SDA, SCL */</div><div class='add'>+				pins = "gpio8", "gpio9";</div><div class='add'>+				function = "qup0_se2";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up = &lt;2200&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c3_data_clk: qup-i2c3-data-clk-state {</div><div class='add'>+				/* SDA, SCL */</div><div class='add'>+				pins = "gpio12", "gpio13";</div><div class='add'>+				function = "qup0_se3";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up = &lt;2200&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c4_data_clk: qup-i2c4-data-clk-state {</div><div class='add'>+				/* SDA, SCL */</div><div class='add'>+				pins = "gpio16", "gpio17";</div><div class='add'>+				function = "qup0_se4";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up = &lt;2200&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c5_data_clk: qup-i2c5-data-clk-state {</div><div class='add'>+				/* SDA, SCL */</div><div class='add'>+				pins = "gpio20", "gpio21";</div><div class='add'>+				function = "qup0_se5";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up = &lt;2200&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c6_data_clk: qup-i2c6-data-clk-state {</div><div class='add'>+				/* SDA, SCL */</div><div class='add'>+				pins = "gpio24", "gpio25";</div><div class='add'>+				function = "qup0_se6";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up = &lt;2200&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c7_data_clk: qup-i2c7-data-clk-state {</div><div class='add'>+				/* SDA, SCL */</div><div class='add'>+				pins = "gpio14", "gpio15";</div><div class='add'>+				function = "qup0_se7";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up = &lt;2200&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c8_data_clk: qup-i2c8-data-clk-state {</div><div class='add'>+				/* SDA, SCL */</div><div class='add'>+				pins = "gpio32", "gpio33";</div><div class='add'>+				function = "qup1_se0";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up = &lt;2200&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c9_data_clk: qup-i2c9-data-clk-state {</div><div class='add'>+				/* SDA, SCL */</div><div class='add'>+				pins = "gpio36", "gpio37";</div><div class='add'>+				function = "qup1_se1";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up = &lt;2200&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c10_data_clk: qup-i2c10-data-clk-state {</div><div class='add'>+				/* SDA, SCL */</div><div class='add'>+				pins = "gpio40", "gpio41";</div><div class='add'>+				function = "qup1_se2";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up = &lt;2200&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c11_data_clk: qup-i2c11-data-clk-state {</div><div class='add'>+				/* SDA, SCL */</div><div class='add'>+				pins = "gpio44", "gpio45";</div><div class='add'>+				function = "qup1_se3";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up = &lt;2200&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c12_data_clk: qup-i2c12-data-clk-state {</div><div class='add'>+				/* SDA, SCL */</div><div class='add'>+				pins = "gpio48", "gpio49";</div><div class='add'>+				function = "qup1_se4";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up = &lt;2200&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c13_data_clk: qup-i2c13-data-clk-state {</div><div class='add'>+				/* SDA, SCL */</div><div class='add'>+				pins = "gpio52", "gpio53";</div><div class='add'>+				function = "qup1_se5";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up = &lt;2200&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c14_data_clk: qup-i2c14-data-clk-state {</div><div class='add'>+				/* SDA, SCL */</div><div class='add'>+				pins = "gpio56", "gpio57";</div><div class='add'>+				function = "qup1_se6";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up = &lt;2200&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c15_data_clk: qup-i2c15-data-clk-state {</div><div class='add'>+				/* SDA, SCL */</div><div class='add'>+				pins = "gpio54", "gpio55";</div><div class='add'>+				function = "qup1_se7";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up = &lt;2200&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c16_data_clk: qup-i2c16-data-clk-state {</div><div class='add'>+				/* SDA, SCL */</div><div class='add'>+				pins = "gpio64", "gpio65";</div><div class='add'>+				function = "qup2_se0";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up = &lt;2200&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c17_data_clk: qup-i2c17-data-clk-state {</div><div class='add'>+				/* SDA, SCL */</div><div class='add'>+				pins = "gpio68", "gpio69";</div><div class='add'>+				function = "qup2_se1";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up = &lt;2200&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c18_data_clk: qup-i2c18-data-clk-state {</div><div class='add'>+				/* SDA, SCL */</div><div class='add'>+				pins = "gpio72", "gpio73";</div><div class='add'>+				function = "qup2_se2";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up = &lt;2200&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c19_data_clk: qup-i2c19-data-clk-state {</div><div class='add'>+				/* SDA, SCL */</div><div class='add'>+				pins = "gpio76", "gpio77";</div><div class='add'>+				function = "qup2_se3";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up = &lt;2200&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c20_data_clk: qup-i2c20-data-clk-state {</div><div class='add'>+				/* SDA, SCL */</div><div class='add'>+				pins = "gpio80", "gpio81";</div><div class='add'>+				function = "qup2_se4";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up = &lt;2200&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c21_data_clk: qup-i2c21-data-clk-state {</div><div class='add'>+				/* SDA, SCL */</div><div class='add'>+				pins = "gpio84", "gpio85";</div><div class='add'>+				function = "qup2_se5";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up = &lt;2200&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c22_data_clk: qup-i2c22-data-clk-state {</div><div class='add'>+				/* SDA, SCL */</div><div class='add'>+				pins = "gpio88", "gpio89";</div><div class='add'>+				function = "qup2_se6";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up = &lt;2200&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c23_data_clk: qup-i2c23-data-clk-state {</div><div class='add'>+				/* SDA, SCL */</div><div class='add'>+				pins = "gpio86", "gpio87";</div><div class='add'>+				function = "qup2_se7";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up = &lt;2200&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi0_cs: qup-spi0-cs-state {</div><div class='add'>+				pins = "gpio3";</div><div class='add'>+				function = "qup0_se0";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi0_data_clk: qup-spi0-data-clk-state {</div><div class='add'>+				/* MISO, MOSI, CLK */</div><div class='add'>+				pins = "gpio0", "gpio1", "gpio2";</div><div class='add'>+				function = "qup0_se0";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi1_cs: qup-spi1-cs-state {</div><div class='add'>+				pins = "gpio7";</div><div class='add'>+				function = "qup0_se1";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi1_data_clk: qup-spi1-data-clk-state {</div><div class='add'>+				/* MISO, MOSI, CLK */</div><div class='add'>+				pins = "gpio4", "gpio5", "gpio6";</div><div class='add'>+				function = "qup0_se1";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi2_cs: qup-spi2-cs-state {</div><div class='add'>+				pins = "gpio11";</div><div class='add'>+				function = "qup0_se2";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi2_data_clk: qup-spi2-data-clk-state {</div><div class='add'>+				/* MISO, MOSI, CLK */</div><div class='add'>+				pins = "gpio8", "gpio9", "gpio10";</div><div class='add'>+				function = "qup0_se2";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi3_cs: qup-spi3-cs-state {</div><div class='add'>+				pins = "gpio15";</div><div class='add'>+				function = "qup0_se3";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi3_data_clk: qup-spi3-data-clk-state {</div><div class='add'>+				/* MISO, MOSI, CLK */</div><div class='add'>+				pins = "gpio12", "gpio13", "gpio14";</div><div class='add'>+				function = "qup0_se3";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi4_cs: qup-spi4-cs-state {</div><div class='add'>+				pins = "gpio19";</div><div class='add'>+				function = "qup0_se4";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi4_data_clk: qup-spi4-data-clk-state {</div><div class='add'>+				/* MISO, MOSI, CLK */</div><div class='add'>+				pins = "gpio16", "gpio17", "gpio18";</div><div class='add'>+				function = "qup0_se4";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi5_cs: qup-spi5-cs-state {</div><div class='add'>+				pins = "gpio23";</div><div class='add'>+				function = "qup0_se5";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi5_data_clk: qup-spi5-data-clk-state {</div><div class='add'>+				/* MISO, MOSI, CLK */</div><div class='add'>+				pins = "gpio20", "gpio21", "gpio22";</div><div class='add'>+				function = "qup0_se5";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi6_cs: qup-spi6-cs-state {</div><div class='add'>+				pins = "gpio27";</div><div class='add'>+				function = "qup0_se6";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi6_data_clk: qup-spi6-data-clk-state {</div><div class='add'>+				/* MISO, MOSI, CLK */</div><div class='add'>+				pins = "gpio24", "gpio25", "gpio26";</div><div class='add'>+				function = "qup0_se6";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi7_cs: qup-spi7-cs-state {</div><div class='add'>+				pins = "gpio13";</div><div class='add'>+				function = "qup0_se7";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi7_data_clk: qup-spi7-data-clk-state {</div><div class='add'>+				/* MISO, MOSI, CLK */</div><div class='add'>+				pins = "gpio14", "gpio15", "gpio12";</div><div class='add'>+				function = "qup0_se7";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi8_cs: qup-spi8-cs-state {</div><div class='add'>+				pins = "gpio35";</div><div class='add'>+				function = "qup1_se0";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi8_data_clk: qup-spi8-data-clk-state {</div><div class='add'>+				/* MISO, MOSI, CLK */</div><div class='add'>+				pins = "gpio32", "gpio33", "gpio34";</div><div class='add'>+				function = "qup1_se0";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi9_cs: qup-spi9-cs-state {</div><div class='add'>+				pins = "gpio39";</div><div class='add'>+				function = "qup1_se1";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi9_data_clk: qup-spi9-data-clk-state {</div><div class='add'>+				/* MISO, MOSI, CLK */</div><div class='add'>+				pins = "gpio36", "gpio37", "gpio38";</div><div class='add'>+				function = "qup1_se1";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi10_cs: qup-spi10-cs-state {</div><div class='add'>+				pins = "gpio43";</div><div class='add'>+				function = "qup1_se2";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi10_data_clk: qup-spi10-data-clk-state {</div><div class='add'>+				/* MISO, MOSI, CLK */</div><div class='add'>+				pins = "gpio40", "gpio41", "gpio42";</div><div class='add'>+				function = "qup1_se2";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi11_cs: qup-spi11-cs-state {</div><div class='add'>+				pins = "gpio47";</div><div class='add'>+				function = "qup1_se3";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi11_data_clk: qup-spi11-data-clk-state {</div><div class='add'>+				/* MISO, MOSI, CLK */</div><div class='add'>+				pins = "gpio44", "gpio45", "gpio46";</div><div class='add'>+				function = "qup1_se3";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi12_cs: qup-spi12-cs-state {</div><div class='add'>+				pins = "gpio51";</div><div class='add'>+				function = "qup1_se4";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi12_data_clk: qup-spi12-data-clk-state {</div><div class='add'>+				/* MISO, MOSI, CLK */</div><div class='add'>+				pins = "gpio48", "gpio49", "gpio50";</div><div class='add'>+				function = "qup1_se4";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi13_cs: qup-spi13-cs-state {</div><div class='add'>+				pins = "gpio55";</div><div class='add'>+				function = "qup1_se5";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi13_data_clk: qup-spi13-data-clk-state {</div><div class='add'>+				/* MISO, MOSI, CLK */</div><div class='add'>+				pins = "gpio52", "gpio53", "gpio54";</div><div class='add'>+				function = "qup1_se5";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi14_cs: qup-spi14-cs-state {</div><div class='add'>+				pins = "gpio59";</div><div class='add'>+				function = "qup1_se6";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi14_data_clk: qup-spi14-data-clk-state {</div><div class='add'>+				/* MISO, MOSI, CLK */</div><div class='add'>+				pins = "gpio56", "gpio57", "gpio58";</div><div class='add'>+				function = "qup1_se6";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi15_cs: qup-spi15-cs-state {</div><div class='add'>+				pins = "gpio53";</div><div class='add'>+				function = "qup1_se7";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi15_data_clk: qup-spi15-data-clk-state {</div><div class='add'>+				/* MISO, MOSI, CLK */</div><div class='add'>+				pins = "gpio54", "gpio55", "gpio52";</div><div class='add'>+				function = "qup1_se7";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi16_cs: qup-spi16-cs-state {</div><div class='add'>+				pins = "gpio67";</div><div class='add'>+				function = "qup2_se0";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi16_data_clk: qup-spi16-data-clk-state {</div><div class='add'>+				/* MISO, MOSI, CLK */</div><div class='add'>+				pins = "gpio64", "gpio65", "gpio66";</div><div class='add'>+				function = "qup2_se0";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi17_cs: qup-spi17-cs-state {</div><div class='add'>+				pins = "gpio71";</div><div class='add'>+				function = "qup2_se1";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi17_data_clk: qup-spi17-data-clk-state {</div><div class='add'>+				/* MISO, MOSI, CLK */</div><div class='add'>+				pins = "gpio68", "gpio69", "gpio70";</div><div class='add'>+				function = "qup2_se1";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi18_cs: qup-spi18-cs-state {</div><div class='add'>+				pins = "gpio75";</div><div class='add'>+				function = "qup2_se2";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi18_data_clk: qup-spi18-data-clk-state {</div><div class='add'>+				/* MISO, MOSI, CLK */</div><div class='add'>+				pins = "gpio72", "gpio73", "gpio74";</div><div class='add'>+				function = "qup2_se2";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi19_cs: qup-spi19-cs-state {</div><div class='add'>+				pins = "gpio79";</div><div class='add'>+				function = "qup2_se3";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi19_data_clk: qup-spi19-data-clk-state {</div><div class='add'>+				/* MISO, MOSI, CLK */</div><div class='add'>+				pins = "gpio76", "gpio77", "gpio78";</div><div class='add'>+				function = "qup2_se3";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi20_cs: qup-spi20-cs-state {</div><div class='add'>+				pins = "gpio83";</div><div class='add'>+				function = "qup2_se4";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi20_data_clk: qup-spi20-data-clk-state {</div><div class='add'>+				/* MISO, MOSI, CLK */</div><div class='add'>+				pins = "gpio80", "gpio81", "gpio82";</div><div class='add'>+				function = "qup2_se4";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi21_cs: qup-spi21-cs-state {</div><div class='add'>+				pins = "gpio87";</div><div class='add'>+				function = "qup2_se5";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi21_data_clk: qup-spi21-data-clk-state {</div><div class='add'>+				/* MISO, MOSI, CLK */</div><div class='add'>+				pins = "gpio84", "gpio85", "gpio86";</div><div class='add'>+				function = "qup2_se5";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi22_cs: qup-spi22-cs-state {</div><div class='add'>+				pins = "gpio91";</div><div class='add'>+				function = "qup2_se6";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi22_data_clk: qup-spi22-data-clk-state {</div><div class='add'>+				/* MISO, MOSI, CLK */</div><div class='add'>+				pins = "gpio88", "gpio89", "gpio90";</div><div class='add'>+				function = "qup2_se6";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi23_cs: qup-spi23-cs-state {</div><div class='add'>+				pins = "gpio85";</div><div class='add'>+				function = "qup2_se7";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi23_data_clk: qup-spi23-data-clk-state {</div><div class='add'>+				/* MISO, MOSI, CLK */</div><div class='add'>+				pins = "gpio86", "gpio87", "gpio84";</div><div class='add'>+				function = "qup2_se7";</div><div class='add'>+				drive-strength = &lt;6&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart2_default: qup-uart2-default-state {</div><div class='add'>+				cts-pins {</div><div class='add'>+					pins = "gpio8";</div><div class='add'>+					function = "qup0_se2";</div><div class='add'>+					drive-strength = &lt;2&gt;;</div><div class='add'>+					bias-disable;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				rts-pins {</div><div class='add'>+					pins = "gpio9";</div><div class='add'>+					function = "qup0_se2";</div><div class='add'>+					drive-strength = &lt;2&gt;;</div><div class='add'>+					bias-disable;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tx-pins {</div><div class='add'>+					pins = "gpio10";</div><div class='add'>+					function = "qup0_se2";</div><div class='add'>+					drive-strength = &lt;2&gt;;</div><div class='add'>+					bias-disable;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				rx-pins {</div><div class='add'>+					pins = "gpio11";</div><div class='add'>+					function = "qup0_se2";</div><div class='add'>+					drive-strength = &lt;2&gt;;</div><div class='add'>+					bias-disable;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart14_default: qup-uart14-default-state {</div><div class='add'>+				cts-pins {</div><div class='add'>+					pins = "gpio56";</div><div class='add'>+					function = "qup1_se6";</div><div class='add'>+					bias-bus-hold;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				rts-pins {</div><div class='add'>+					pins = "gpio57";</div><div class='add'>+					function = "qup1_se6";</div><div class='add'>+					drive-strength = &lt;2&gt;;</div><div class='add'>+					bias-disable;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				tx-pins {</div><div class='add'>+					pins = "gpio58";</div><div class='add'>+					function = "qup1_se6";</div><div class='add'>+					drive-strength = &lt;2&gt;;</div><div class='add'>+					bias-disable;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				rx-pins {</div><div class='add'>+					pins = "gpio59";</div><div class='add'>+					function = "qup1_se6";</div><div class='add'>+					bias-pull-up;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart21_default: qup-uart21-default-state {</div><div class='add'>+				tx-pins {</div><div class='add'>+					pins = "gpio86";</div><div class='add'>+					function = "qup2_se5";</div><div class='add'>+					drive-strength = &lt;2&gt;;</div><div class='add'>+					bias-disable;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				rx-pins {</div><div class='add'>+					pins = "gpio87";</div><div class='add'>+					function = "qup2_se5";</div><div class='add'>+					drive-strength = &lt;2&gt;;</div><div class='add'>+					bias-disable;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sdc2_default: sdc2-default-state {</div><div class='add'>+				clk-pins {</div><div class='add'>+					pins = "sdc2_clk";</div><div class='add'>+					drive-strength = &lt;16&gt;;</div><div class='add'>+					bias-disable;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cmd-pins {</div><div class='add'>+					pins = "sdc2_cmd";</div><div class='add'>+					drive-strength = &lt;10&gt;;</div><div class='add'>+					bias-pull-up;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				data-pins {</div><div class='add'>+					pins = "sdc2_data";</div><div class='add'>+					drive-strength = &lt;10&gt;;</div><div class='add'>+					bias-pull-up;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sdc2_sleep: sdc2-sleep-state {</div><div class='add'>+				clk-pins {</div><div class='add'>+					pins = "sdc2_clk";</div><div class='add'>+					drive-strength = &lt;2&gt;;</div><div class='add'>+					bias-disable;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cmd-pins {</div><div class='add'>+					pins = "sdc2_cmd";</div><div class='add'>+					drive-strength = &lt;2&gt;;</div><div class='add'>+					bias-pull-up;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				data-pins {</div><div class='add'>+					pins = "sdc2_data";</div><div class='add'>+					drive-strength = &lt;2&gt;;</div><div class='add'>+					bias-pull-up;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		stm@10002000 {</div><div class='add'>+			compatible = "arm,coresight-stm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10002000 0x0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0x16280000 0x0 0x180000&gt;;</div><div class='add'>+			reg-names = "stm-base",</div><div class='add'>+				    "stm-stimulus-base";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					stm_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;funnel0_in7&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@10003000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10003000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,cmb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,cmb-msrs-num = &lt;32&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					dcc_tpdm_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;qdss_tpda_in0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpda@10004000 {</div><div class='add'>+			compatible = "qcom,coresight-tpda", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10004000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					qdss_tpda_in0: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dcc_tpdm_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					qdss_tpda_in1: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;qdss_tpdm_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					qdss_tpda_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;funnel0_in6&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@1000f000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x1000f000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,cmb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,cmb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					qdss_tpdm_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;qdss_tpda_in1&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		funnel@10041000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10041000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@6 {</div><div class='add'>+					reg = &lt;6&gt;;</div><div class='add'>+</div><div class='add'>+					funnel0_in6: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;qdss_tpda_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@7 {</div><div class='add'>+					reg = &lt;7&gt;;</div><div class='add'>+</div><div class='add'>+					funnel0_in7: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;stm_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					funnel0_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;qdss_funnel_in0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		funnel@10042000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10042000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@2 {</div><div class='add'>+					reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+					funnel1_in2: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;tmess_funnel_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@5 {</div><div class='add'>+					reg = &lt;5&gt;;</div><div class='add'>+</div><div class='add'>+					funnel1_in5: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlst_funnel_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@6 {</div><div class='add'>+					reg = &lt;6&gt;;</div><div class='add'>+</div><div class='add'>+					funnel1_in6: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlct1_funnel_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					funnel1_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;qdss_funnel_in1&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		funnel@10045000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10045000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					qdss_funnel_in0: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;funnel0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					qdss_funnel_in1: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;funnel1_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					qdss_funnel_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;aoss_funnel_in7&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@10800000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10800000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,cmb-element-bits = &lt;64&gt;;</div><div class='add'>+			qcom,cmb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					mxa_tpdm_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlct2_tpda_in15&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@1082c000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x1082c000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,dsb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,dsb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					gcc_tpdm_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlct1_tpda_in21&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@10841000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10841000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,cmb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,cmb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					prng_tpdm_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlct1_tpda_in19&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@10844000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10844000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,dsb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,dsb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					lpass_cx_tpdm_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;lpass_cx_funnel_in0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		funnel@10846000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10846000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				port {</div><div class='add'>+					lpass_cx_funnel_in0: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;lpass_cx_tpdm_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					lpass_cx_funnel_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlct1_tpda_in4&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cti@1098b000 {</div><div class='add'>+			compatible = "arm,coresight-cti", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x1098b000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@109d0000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x109d0000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,dsb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,dsb-msrs-num = &lt;32&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					qm_tpdm_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlct1_tpda_in20&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@10ac0000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10ac0000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,dsb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,dsb-msrs-num = &lt;32&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					dlst_tpdm0_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlst_tpda_in8&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@10ac1000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10ac1000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,cmb-element-bits = &lt;64&gt;;</div><div class='add'>+			qcom,cmb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					dlst_tpdm1_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlst_tpda_in9&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpda@10ac4000 {</div><div class='add'>+			compatible = "qcom,coresight-tpda", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10ac4000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@8 {</div><div class='add'>+					reg = &lt;8&gt;;</div><div class='add'>+</div><div class='add'>+					dlst_tpda_in8: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlst_tpdm0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@9 {</div><div class='add'>+					reg = &lt;9&gt;;</div><div class='add'>+</div><div class='add'>+					dlst_tpda_in9: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlst_tpdm1_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					dlst_tpda_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlst_funnel_in0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		funnel@10ac5000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10ac5000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				port {</div><div class='add'>+					dlst_funnel_in0: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlst_tpda_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					dlst_funnel_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;funnel1_in5&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		funnel@10b04000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10b04000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@3 {</div><div class='add'>+					reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+					aoss_funnel_in3: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ddr_lpi_funnel_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@6 {</div><div class='add'>+					reg = &lt;6&gt;;</div><div class='add'>+</div><div class='add'>+					aoss_funnel_in6: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;aoss_tpda_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@7 {</div><div class='add'>+					reg = &lt;7&gt;;</div><div class='add'>+</div><div class='add'>+					aoss_funnel_in7: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;qdss_funnel_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					aoss_funnel_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;etf0_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		etf0: tmc@10b05000 {</div><div class='add'>+			compatible = "arm,coresight-tmc", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10b05000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				port {</div><div class='add'>+					etf0_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;aoss_funnel_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					etf0_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;swao_rep_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		replicator@10b06000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10b06000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				port {</div><div class='add'>+					swao_rep_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;etf0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					swao_rep_out1: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;eud_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpda@10b08000 {</div><div class='add'>+			compatible = "qcom,coresight-tpda", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10b08000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					aoss_tpda_in0: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;aoss_tpdm0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					aoss_tpda_in1: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;aoss_tpdm1_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@2 {</div><div class='add'>+					reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+					aoss_tpda_in2: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;aoss_tpdm2_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@3 {</div><div class='add'>+					reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+					aoss_tpda_in3: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;aoss_tpdm3_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@4 {</div><div class='add'>+					reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+					aoss_tpda_in4: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;aoss_tpdm4_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					aoss_tpda_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;aoss_funnel_in6&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@10b09000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10b09000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,cmb-element-bits = &lt;64&gt;;</div><div class='add'>+			qcom,cmb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					aoss_tpdm0_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;aoss_tpda_in0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@10b0a000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10b0a000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,cmb-element-bits = &lt;64&gt;;</div><div class='add'>+			qcom,cmb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					aoss_tpdm1_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;aoss_tpda_in1&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@10b0b000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10b0b000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,cmb-element-bits = &lt;64&gt;;</div><div class='add'>+			qcom,cmb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					aoss_tpdm2_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;aoss_tpda_in2&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@10b0c000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10b0c000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,cmb-element-bits = &lt;64&gt;;</div><div class='add'>+			qcom,cmb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					aoss_tpdm3_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;aoss_tpda_in3&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@10b0d000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10b0d000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,dsb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,dsb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					aoss_tpdm4_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;aoss_tpda_in4&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@10b20000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10b20000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,dsb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,dsb-msrs-num = &lt;32&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					lpicc_tpdm_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ddr_lpi_tpda_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpda@10b23000 {</div><div class='add'>+			compatible = "qcom,coresight-tpda", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10b23000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				port {</div><div class='add'>+					ddr_lpi_tpda_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;lpicc_tpdm_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					ddr_lpi_tpda_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ddr_lpi_funnel_in0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		funnel@10b24000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10b24000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				port {</div><div class='add'>+					ddr_lpi_funnel_in0: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ddr_lpi_tpda_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					ddr_lpi_funnel_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;aoss_funnel_in3&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@10c08000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10c08000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,dsb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,dsb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					mm_tpdm_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mm_funnel_in4&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		funnel@10c0b000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10c0b000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@4 {</div><div class='add'>+					reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+					mm_funnel_in4: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mm_tpdm_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					mm_funnel_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlct2_tpda_in4&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@10c28000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10c28000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,dsb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,dsb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					dlct1_tpdm_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlct1_tpda_in26&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@10c29000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10c29000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,cmb-element-bits = &lt;64&gt;;</div><div class='add'>+			qcom,cmb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					ipcc_tpdm_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlct1_tpda_in27&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpda@10c2b000 {</div><div class='add'>+			compatible = "qcom,coresight-tpda", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10c2b000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@4 {</div><div class='add'>+					reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+					dlct1_tpda_in4: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;lpass_cx_funnel_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@13 {</div><div class='add'>+					reg = &lt;19&gt;;</div><div class='add'>+</div><div class='add'>+					dlct1_tpda_in19: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;prng_tpdm_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@14 {</div><div class='add'>+					reg = &lt;20&gt;;</div><div class='add'>+</div><div class='add'>+					dlct1_tpda_in20: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;qm_tpdm_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@15 {</div><div class='add'>+					reg = &lt;21&gt;;</div><div class='add'>+</div><div class='add'>+					dlct1_tpda_in21: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;gcc_tpdm_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1a {</div><div class='add'>+					reg = &lt;26&gt;;</div><div class='add'>+</div><div class='add'>+					dlct1_tpda_in26: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlct1_tpdm_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1b {</div><div class='add'>+					reg = &lt;27&gt;;</div><div class='add'>+</div><div class='add'>+					dlct1_tpda_in27: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ipcc_tpdm_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					dlct1_tpda_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlct1_funnel_in0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		funnel@10c2c000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10c2c000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					dlct1_funnel_in0: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlct1_tpda_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@4 {</div><div class='add'>+					reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+					dlct1_funnel_in4: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlct2_funnel_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@5 {</div><div class='add'>+					reg = &lt;5&gt;;</div><div class='add'>+</div><div class='add'>+					dlct1_funnel_in5: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ddr_funnel0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					dlct1_funnel_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;funnel1_in6&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@10c38000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10c38000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,cmb-element-bits = &lt;64&gt;;</div><div class='add'>+			qcom,cmb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					dlct2_tpdm0_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlct2_tpda_in16&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@10c39000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10c39000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,cmb-element-bits = &lt;64&gt;;</div><div class='add'>+			qcom,cmb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					dlct2_tpdm1_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlct2_tpda_in17&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpda@10c3c000 {</div><div class='add'>+			compatible = "qcom,coresight-tpda", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10c3c000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@4 {</div><div class='add'>+					reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+					dlct2_tpda_in4: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mm_funnel_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@f {</div><div class='add'>+					reg = &lt;15&gt;;</div><div class='add'>+</div><div class='add'>+					dlct2_tpda_in15: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mxa_tpdm_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@10 {</div><div class='add'>+					reg = &lt;16&gt;;</div><div class='add'>+</div><div class='add'>+					dlct2_tpda_in16: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlct2_tpdm0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@11 {</div><div class='add'>+					reg = &lt;17&gt;;</div><div class='add'>+</div><div class='add'>+					dlct2_tpda_in17: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlct2_tpdm1_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					dlct2_tpda_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlct2_funnel_in0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		funnel@10c3d000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10c3d000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				port {</div><div class='add'>+					dlct2_funnel_in0: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlct2_tpda_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					dlct2_funnel_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlct1_funnel_in4&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@10cc1000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10cc1000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,cmb-element-bits = &lt;64&gt;;</div><div class='add'>+			qcom,cmb-msrs-num = &lt;32&gt;;</div><div class='add'>+			qcom,dsb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,dsb-msrs-num = &lt;32&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					tmess_tpdm1_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;tmess_tpda_in2&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpda@10cc4000 {</div><div class='add'>+			compatible = "qcom,coresight-tpda", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10cc4000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@2 {</div><div class='add'>+					reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+					tmess_tpda_in2: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;tmess_tpdm1_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					tmess_tpda_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;tmess_funnel_in0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		funnel@10cc5000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10cc5000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				port {</div><div class='add'>+					tmess_funnel_in0: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;tmess_tpda_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					tmess_funnel_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;funnel1_in2&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		funnel@10d04000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10d04000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@6 {</div><div class='add'>+					reg = &lt;6&gt;;</div><div class='add'>+</div><div class='add'>+					ddr_funnel0_in6: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ddr_funnel1_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					ddr_funnel0_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlct1_funnel_in5&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@10d08000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10d08000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,cmb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,cmb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					llcc0_tpdm_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;llcc_tpda_in0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@10d09000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10d09000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,cmb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,cmb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					llcc1_tpdm_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;llcc_tpda_in1&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@10d0a000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10d0a000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,cmb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,cmb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					llcc2_tpdm_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;llcc_tpda_in2&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@10d0b000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10d0b000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,cmb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,cmb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					llcc3_tpdm_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;llcc_tpda_in3&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@10d0c000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10d0c000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,cmb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,cmb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					llcc4_tpdm_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;llcc_tpda_in4&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@10d0d000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10d0d000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,cmb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,cmb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					llcc5_tpdm_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;llcc_tpda_in5&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@10d0e000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10d0e000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,cmb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,cmb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					llcc6_tpdm_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;llcc_tpda_in6&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@10d0f000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10d0f000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,cmb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,cmb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					llcc7_tpdm_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;llcc_tpda_in7&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpda@10d12000 {</div><div class='add'>+			compatible = "qcom,coresight-tpda", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10d12000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					llcc_tpda_in0: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;llcc0_tpdm_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					llcc_tpda_in1: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;llcc1_tpdm_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@2 {</div><div class='add'>+					reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+					llcc_tpda_in2: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;llcc2_tpdm_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@3 {</div><div class='add'>+					reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+					llcc_tpda_in3: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;llcc3_tpdm_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@4 {</div><div class='add'>+					reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+					llcc_tpda_in4: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;llcc4_tpdm_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@5 {</div><div class='add'>+					reg = &lt;5&gt;;</div><div class='add'>+</div><div class='add'>+					llcc_tpda_in5: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;llcc5_tpdm_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@6 {</div><div class='add'>+					reg = &lt;6&gt;;</div><div class='add'>+</div><div class='add'>+					llcc_tpda_in6: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;llcc6_tpdm_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@7 {</div><div class='add'>+					reg = &lt;7&gt;;</div><div class='add'>+</div><div class='add'>+					llcc_tpda_in7: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;llcc7_tpdm_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					llcc_tpda_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ddr_funnel1_in0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		funnel@10d13000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x10d13000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				port {</div><div class='add'>+					ddr_funnel1_in0: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;llcc_tpda_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					ddr_funnel1_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ddr_funnel0_in6&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		apps_smmu: iommu@15000000 {</div><div class='add'>+			compatible = "qcom,x1e80100-smmu-500", "qcom,smmu-500", "arm,mmu-500";</div><div class='add'>+			reg = &lt;0 0x15000000 0 0x100000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			#iommu-cells = &lt;2&gt;;</div><div class='add'>+			#global-interrupts = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			dma-coherent;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie_smmu: iommu@15400000 {</div><div class='add'>+			compatible = "arm,smmu-v3";</div><div class='add'>+			reg = &lt;0 0x15400000 0 0x80000&gt;;</div><div class='add'>+			#iommu-cells = &lt;1&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 138 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 134 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 136 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			interrupt-names = "eventq",</div><div class='add'>+					  "gerror",</div><div class='add'>+					  "cmdq-sync";</div><div class='add'>+			dma-coherent;</div><div class='add'>+			status = "reserved"; /* Controlled by Gunyah. */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		intc: interrupt-controller@17000000 {</div><div class='add'>+			compatible = "arm,gic-v3";</div><div class='add'>+			reg = &lt;0 0x17000000 0 0x10000&gt;,     /* GICD */</div><div class='add'>+			      &lt;0 0x17080000 0 0x300000&gt;;    /* GICR * 12 */</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+</div><div class='add'>+			#redistributor-regions = &lt;1&gt;;</div><div class='add'>+			redistributor-stride = &lt;0x0 0x40000&gt;;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			gic_its: msi-controller@17040000 {</div><div class='add'>+				compatible = "arm,gic-v3-its";</div><div class='add'>+				reg = &lt;0 0x17040000 0 0x40000&gt;;</div><div class='add'>+</div><div class='add'>+				msi-controller;</div><div class='add'>+				#msi-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpucp_mbox: mailbox@17430000 {</div><div class='add'>+			compatible = "qcom,x1e80100-cpucp-mbox";</div><div class='add'>+			reg = &lt;0 0x17430000 0 0x10000&gt;, &lt;0 0x18830000 0 0x10000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#mbox-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		apps_rsc: rsc@17500000 {</div><div class='add'>+			compatible = "qcom,rpmh-rsc";</div><div class='add'>+			reg = &lt;0 0x17500000 0 0x10000&gt;,</div><div class='add'>+			      &lt;0 0x17510000 0 0x10000&gt;,</div><div class='add'>+			      &lt;0 0x17520000 0 0x10000&gt;;</div><div class='add'>+			reg-names = "drv-0", "drv-1", "drv-2";</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			qcom,tcs-offset = &lt;0xd00&gt;;</div><div class='add'>+			qcom,drv-id = &lt;2&gt;;</div><div class='add'>+			qcom,tcs-config = &lt;ACTIVE_TCS    3&gt;, &lt;SLEEP_TCS     2&gt;,</div><div class='add'>+					  &lt;WAKE_TCS      2&gt;, &lt;CONTROL_TCS   0&gt;;</div><div class='add'>+</div><div class='add'>+			label = "apps_rsc";</div><div class='add'>+			power-domains = &lt;&amp;system_pd&gt;;</div><div class='add'>+</div><div class='add'>+			apps_bcm_voter: bcm-voter {</div><div class='add'>+				compatible = "qcom,bcm-voter";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			rpmhcc: clock-controller {</div><div class='add'>+				compatible = "qcom,x1e80100-rpmh-clk";</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;xo_board&gt;;</div><div class='add'>+				clock-names = "xo";</div><div class='add'>+</div><div class='add'>+				#clock-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			rpmhpd: power-controller {</div><div class='add'>+				compatible = "qcom,x1e80100-rpmhpd";</div><div class='add'>+</div><div class='add'>+				operating-points-v2 = &lt;&amp;rpmhpd_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+				#power-domain-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				rpmhpd_opp_table: opp-table {</div><div class='add'>+					compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+					rpmhpd_opp_ret: opp-16 {</div><div class='add'>+						opp-level = &lt;RPMH_REGULATOR_LEVEL_RETENTION&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					rpmhpd_opp_min_svs: opp-48 {</div><div class='add'>+						opp-level = &lt;RPMH_REGULATOR_LEVEL_MIN_SVS&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					rpmhpd_opp_low_svs_d2: opp-52 {</div><div class='add'>+						opp-level = &lt;RPMH_REGULATOR_LEVEL_LOW_SVS_D2&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					rpmhpd_opp_low_svs_d1: opp-56 {</div><div class='add'>+						opp-level = &lt;RPMH_REGULATOR_LEVEL_LOW_SVS_D1&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					rpmhpd_opp_low_svs_d0: opp-60 {</div><div class='add'>+						opp-level = &lt;RPMH_REGULATOR_LEVEL_LOW_SVS_D0&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					rpmhpd_opp_low_svs: opp-64 {</div><div class='add'>+						opp-level = &lt;RPMH_REGULATOR_LEVEL_LOW_SVS&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					rpmhpd_opp_low_svs_l1: opp-80 {</div><div class='add'>+						opp-level = &lt;RPMH_REGULATOR_LEVEL_LOW_SVS_L1&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					rpmhpd_opp_svs: opp-128 {</div><div class='add'>+						opp-level = &lt;RPMH_REGULATOR_LEVEL_SVS&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					rpmhpd_opp_svs_l0: opp-144 {</div><div class='add'>+						opp-level = &lt;RPMH_REGULATOR_LEVEL_SVS_L0&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					rpmhpd_opp_svs_l1: opp-192 {</div><div class='add'>+						opp-level = &lt;RPMH_REGULATOR_LEVEL_SVS_L1&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					rpmhpd_opp_nom: opp-256 {</div><div class='add'>+						opp-level = &lt;RPMH_REGULATOR_LEVEL_NOM&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					rpmhpd_opp_nom_l1: opp-320 {</div><div class='add'>+						opp-level = &lt;RPMH_REGULATOR_LEVEL_NOM_L1&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					rpmhpd_opp_nom_l2: opp-336 {</div><div class='add'>+						opp-level = &lt;RPMH_REGULATOR_LEVEL_NOM_L2&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					rpmhpd_opp_turbo: opp-384 {</div><div class='add'>+						opp-level = &lt;RPMH_REGULATOR_LEVEL_TURBO&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					rpmhpd_opp_turbo_l1: opp-416 {</div><div class='add'>+						opp-level = &lt;RPMH_REGULATOR_LEVEL_TURBO_L1&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		timer@17800000 {</div><div class='add'>+			compatible = "arm,armv7-timer-mem";</div><div class='add'>+			reg = &lt;0 0x17800000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges = &lt;0 0 0 0 0x20000000&gt;;</div><div class='add'>+</div><div class='add'>+			frame@17801000 {</div><div class='add'>+				reg = &lt;0 0x17801000 0x1000&gt;,</div><div class='add'>+				      &lt;0 0x17802000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				frame-number = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@17803000 {</div><div class='add'>+				reg = &lt;0 0x17803000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				frame-number = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@17805000 {</div><div class='add'>+				reg = &lt;0 0x17805000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				frame-number = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@17807000 {</div><div class='add'>+				reg = &lt;0 0x17807000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				frame-number = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@17809000 {</div><div class='add'>+				reg = &lt;0 0x17809000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				frame-number = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@1780b000 {</div><div class='add'>+				reg = &lt;0 0x1780b000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				frame-number = &lt;5&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@1780d000 {</div><div class='add'>+				reg = &lt;0 0x1780d000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+				interrupts = &lt;GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+				frame-number = &lt;6&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sram: sram@18b4e000 {</div><div class='add'>+			compatible = "mmio-sram";</div><div class='add'>+			reg = &lt;0x0 0x18b4e000 0x0 0x400&gt;;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges = &lt;0x0 0x0 0x18b4e000 0x400&gt;;</div><div class='add'>+</div><div class='add'>+			cpu_scp_lpri0: scp-sram-section@0 {</div><div class='add'>+				compatible = "arm,scmi-shmem";</div><div class='add'>+				reg = &lt;0x0 0x200&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cpu_scp_lpri1: scp-sram-section@200 {</div><div class='add'>+				compatible = "arm,scmi-shmem";</div><div class='add'>+				reg = &lt;0x200 0x200&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sbsa_watchdog: watchdog@1c840000 {</div><div class='add'>+			compatible = "arm,sbsa-gwdt";</div><div class='add'>+			reg = &lt;0 0x1c840000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x1c850000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qfprom: efuse@221c8000 {</div><div class='add'>+			compatible = "qcom,x1e80100-qfprom", "qcom,qfprom";</div><div class='add'>+			reg = &lt;0 0x221c8000 0 0x1000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			gpu_speed_bin: gpu-speed-bin@119 {</div><div class='add'>+				reg = &lt;0x119 0x2&gt;;</div><div class='add'>+				bits = &lt;7 8&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmu@24091000 {</div><div class='add'>+			compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon";</div><div class='add'>+			reg = &lt;0 0x24091000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY&gt;;</div><div class='add'>+</div><div class='add'>+			operating-points-v2 = &lt;&amp;llcc_bwmon_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+			llcc_bwmon_opp_table: opp-table {</div><div class='add'>+				compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+				opp-0 {</div><div class='add'>+					opp-peak-kBps = &lt;800000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-1 {</div><div class='add'>+					opp-peak-kBps = &lt;2188000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-2 {</div><div class='add'>+					opp-peak-kBps = &lt;3072000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-3 {</div><div class='add'>+					opp-peak-kBps = &lt;6220800&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-4 {</div><div class='add'>+					opp-peak-kBps = &lt;6835200&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-5 {</div><div class='add'>+					opp-peak-kBps = &lt;8371200&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-6 {</div><div class='add'>+					opp-peak-kBps = &lt;10944000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-7 {</div><div class='add'>+					opp-peak-kBps = &lt;12748800&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-8 {</div><div class='add'>+					opp-peak-kBps = &lt;14745600&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-9 {</div><div class='add'>+					opp-peak-kBps = &lt;16896000&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* cluster0 */</div><div class='add'>+		bwmon_cluster0: pmu@240b3400 {</div><div class='add'>+			compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";</div><div class='add'>+			reg = &lt;0 0x240b3400 0 0x600&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY&gt;;</div><div class='add'>+</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu_bwmon_opp_table&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* cluster2 */</div><div class='add'>+		bwmon_cluster2: pmu@240b5400 {</div><div class='add'>+			compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";</div><div class='add'>+			reg = &lt;0 0x240b5400 0 0x600&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY&gt;;</div><div class='add'>+</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu_bwmon_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+			cpu_bwmon_opp_table: opp-table {</div><div class='add'>+				compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+				opp-0 {</div><div class='add'>+					opp-peak-kBps = &lt;4800000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-1 {</div><div class='add'>+					opp-peak-kBps = &lt;7464000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-2 {</div><div class='add'>+					opp-peak-kBps = &lt;9600000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-3 {</div><div class='add'>+					opp-peak-kBps = &lt;12896000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-4 {</div><div class='add'>+					opp-peak-kBps = &lt;14928000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-5 {</div><div class='add'>+					opp-peak-kBps = &lt;17064000&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* cluster1 */</div><div class='add'>+		pmu@240b6400 {</div><div class='add'>+			compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";</div><div class='add'>+			reg = &lt;0 0x240b6400 0 0x600&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY&gt;;</div><div class='add'>+</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu_bwmon_opp_table&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		system-cache-controller@25000000 {</div><div class='add'>+			compatible = "qcom,x1e80100-llcc";</div><div class='add'>+			reg = &lt;0 0x25000000 0 0x200000&gt;,</div><div class='add'>+			      &lt;0 0x25200000 0 0x200000&gt;,</div><div class='add'>+			      &lt;0 0x25400000 0 0x200000&gt;,</div><div class='add'>+			      &lt;0 0x25600000 0 0x200000&gt;,</div><div class='add'>+			      &lt;0 0x25800000 0 0x200000&gt;,</div><div class='add'>+			      &lt;0 0x25a00000 0 0x200000&gt;,</div><div class='add'>+			      &lt;0 0x25c00000 0 0x200000&gt;,</div><div class='add'>+			      &lt;0 0x25e00000 0 0x200000&gt;,</div><div class='add'>+			      &lt;0 0x26000000 0 0x200000&gt;,</div><div class='add'>+			      &lt;0 0x26200000 0 0x200000&gt;;</div><div class='add'>+			reg-names = "llcc0_base",</div><div class='add'>+				    "llcc1_base",</div><div class='add'>+				    "llcc2_base",</div><div class='add'>+				    "llcc3_base",</div><div class='add'>+				    "llcc4_base",</div><div class='add'>+				    "llcc5_base",</div><div class='add'>+				    "llcc6_base",</div><div class='add'>+				    "llcc7_base",</div><div class='add'>+				    "llcc_broadcast_base",</div><div class='add'>+				    "llcc_broadcast_and_base";</div><div class='add'>+			interrupts = &lt;GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		remoteproc_cdsp: remoteproc@32300000 {</div><div class='add'>+			compatible = "qcom,x1e80100-cdsp-pas";</div><div class='add'>+			reg = &lt;0x0 0x32300000 0x0 0x10000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts-extended = &lt;&amp;intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			interrupt-names = "wdog",</div><div class='add'>+					  "fatal",</div><div class='add'>+					  "ready",</div><div class='add'>+					  "handover",</div><div class='add'>+					  "stop-ack";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;;</div><div class='add'>+			clock-names = "xo";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;,</div><div class='add'>+					&lt;&amp;rpmhpd RPMHPD_MXC&gt;,</div><div class='add'>+					&lt;&amp;rpmhpd RPMHPD_NSP&gt;;</div><div class='add'>+			power-domain-names = "cx",</div><div class='add'>+					     "mxc",</div><div class='add'>+					     "nsp";</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+</div><div class='add'>+			memory-region = &lt;&amp;cdsp_mem&gt;,</div><div class='add'>+					&lt;&amp;q6_cdsp_dtb_mem&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,qmp = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,smem-states = &lt;&amp;smp2p_cdsp_out 0&gt;;</div><div class='add'>+			qcom,smem-state-names = "stop";</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			glink-edge {</div><div class='add'>+				interrupts-extended = &lt;&amp;ipcc IPCC_CLIENT_CDSP</div><div class='add'>+							     IPCC_MPROC_SIGNAL_GLINK_QMP</div><div class='add'>+							     IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				mboxes = &lt;&amp;ipcc IPCC_CLIENT_CDSP</div><div class='add'>+						IPCC_MPROC_SIGNAL_GLINK_QMP&gt;;</div><div class='add'>+</div><div class='add'>+				label = "cdsp";</div><div class='add'>+				qcom,remote-pid = &lt;5&gt;;</div><div class='add'>+</div><div class='add'>+				fastrpc {</div><div class='add'>+					compatible = "qcom,fastrpc";</div><div class='add'>+					qcom,glink-channels = "fastrpcglink-apps-dsp";</div><div class='add'>+					label = "cdsp";</div><div class='add'>+					qcom,non-secure-domain;</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					compute-cb@1 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x0c01 0x20&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@2 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;2&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x0c02 0x20&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@3 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;3&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x0c03 0x20&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@4 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;4&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x0c04 0x20&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@5 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;5&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x0c05 0x20&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@6 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;6&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x0c06 0x20&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@7 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;7&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x0c07 0x20&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@8 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;8&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x0c08 0x20&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					/* note: compute-cb@9 is secure */</div><div class='add'>+</div><div class='add'>+					compute-cb@10 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;10&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x0c0c 0x20&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@11 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;11&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x0c0d 0x20&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@12 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;12&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x0c0e 0x20&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@13 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;13&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x0c0f 0x20&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	thermal_zones: thermal-zones {</div><div class='add'>+		aoss0-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 0&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				aoss0-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu0-0-top-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 1&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu0-0-btm-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 2&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu0-1-top-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 3&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu0-1-btm-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 4&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu0-2-top-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 5&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu0-2-btm-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 6&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu0-3-top-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 7&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu0-3-btm-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 8&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpuss0-top-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 9&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpuss2-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpuss0-btm-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 10&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpuss2-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mem-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 11&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				mem-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		video-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 12&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				video-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aoss1-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens1 0&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				aoss0-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1-0-top-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens1 1&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1-0-btm-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens1 2&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1-1-top-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens1 3&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1-1-btm-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens1 4&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1-2-top-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens1 5&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1-2-btm-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens1 6&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1-3-top-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens1 7&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1-3-btm-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens1 8&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpuss1-top-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens1 9&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpuss2-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpuss1-btm-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens1 10&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpuss2-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aoss2-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens2 0&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				aoss0-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2-0-top-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens2 1&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2-0-btm-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens2 2&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2-1-top-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens2 3&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2-1-btm-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens2 4&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2-2-top-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens2 5&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2-2-btm-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens2 6&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2-3-top-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens2 7&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2-3-btm-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens2 8&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpuss2-top-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens2 9&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpuss2-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpuss2-btm-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens2 10&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpuss2-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aoss3-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens3 0&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				aoss0-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nsp0-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens3 1&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				nsp0-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nsp1-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens3 2&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				nsp1-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nsp2-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens3 3&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				nsp2-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nsp3-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens3 4&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				nsp3-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpuss-0-thermal {</div><div class='add'>+			polling-delay-passive = &lt;200&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens3 5&gt;;</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;gpuss0_alert0&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				gpuss0_alert0: trip-point0 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpu-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpuss-1-thermal {</div><div class='add'>+			polling-delay-passive = &lt;200&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens3 6&gt;;</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;gpuss1_alert0&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				gpuss1_alert0: trip-point0 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpu-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpuss-2-thermal {</div><div class='add'>+			polling-delay-passive = &lt;200&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens3 7&gt;;</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;gpuss2_alert0&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				gpuss2_alert0: trip-point0 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpu-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpuss-3-thermal {</div><div class='add'>+			polling-delay-passive = &lt;200&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens3 8&gt;;</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;gpuss3_alert0&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				gpuss3_alert0: trip-point0 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpu-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpuss-4-thermal {</div><div class='add'>+			polling-delay-passive = &lt;200&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens3 9&gt;;</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;gpuss4_alert0&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				gpuss4_alert0: trip-point0 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpu-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpuss-5-thermal {</div><div class='add'>+			polling-delay-passive = &lt;200&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens3 10&gt;;</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;gpuss5_alert0&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				gpuss5_alert0: trip-point0 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpu-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpuss-6-thermal {</div><div class='add'>+			polling-delay-passive = &lt;200&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens3 11&gt;;</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;gpuss6_alert0&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				gpuss6_alert0: trip-point0 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpu-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpuss-7-thermal {</div><div class='add'>+			polling-delay-passive = &lt;200&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens3 12&gt;;</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;gpuss7_alert0&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				gpuss7_alert0: trip-point0 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpu-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		camera0-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens3 13&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				camera0-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		camera1-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens3 14&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				camera0-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts<br/>new file mode 100644<br/>index 000000000000..df3cbb7c79c4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts</a></div><div class='hunk'>@@ -0,0 +1,125 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause</div><div class='add'>+/*</div><div class='add'>+ * IPQ5018 MP03.1-C2 board device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2023 The Linux Foundation. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "ipq5018.dtsi"</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Qualcomm Technologies, Inc. IPQ5018/AP-RDP432.1-C2";</div><div class='add'>+	compatible = "qcom,ipq5018-rdp432-c2", "qcom,ipq5018";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;blsp1_uart1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp1_uart1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart1_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pcie0_default&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	perst-gpios = &lt;&amp;tlmm 15 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	wake-gpios = &lt;&amp;tlmm 16 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sdhc_1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdc_default_state&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	mmc-ddr-1_8v;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	max-frequency = &lt;192000000&gt;;</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sleep_clk {</div><div class='add'>+	clock-frequency = &lt;32000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tlmm {</div><div class='add'>+	pcie0_default: pcie0-default-state {</div><div class='add'>+		clkreq-n-pins {</div><div class='add'>+			pins = "gpio14";</div><div class='add'>+			function = "pcie0_clk";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		perst-n-pins {</div><div class='add'>+			pins = "gpio15";</div><div class='add'>+			function = "gpio";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wake-n-pins {</div><div class='add'>+			pins = "gpio16";</div><div class='add'>+			function = "pcie0_wake";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdc_default_state: sdc-default-state {</div><div class='add'>+		clk-pins {</div><div class='add'>+			pins = "gpio9";</div><div class='add'>+			function = "sdc1_clk";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmd-pins {</div><div class='add'>+			pins = "gpio8";</div><div class='add'>+			function = "sdc1_cmd";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		data-pins {</div><div class='add'>+			pins = "gpio4", "gpio5", "gpio6", "gpio7";</div><div class='add'>+			function = "sdc1_data";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbphy0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xo_board_clk {</div><div class='add'>+	clock-div = &lt;4&gt;;</div><div class='add'>+	clock-mult = &lt;1&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts b/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts<br/>new file mode 100644<br/>index 000000000000..7a25af57749c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts</a></div><div class='hunk'>@@ -0,0 +1,129 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+#include "ipq5018.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "TP-Link Archer AX55 v1";</div><div class='add'>+	compatible = "tplink,archer-ax55-v1", "qcom,ipq5018";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;blsp1_uart1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-0 = &lt;&amp;led_pins&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_LAN;</div><div class='add'>+			gpios = &lt;&amp;tlmm 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_WAN_ONLINE;</div><div class='add'>+			gpios = &lt;&amp;tlmm 11 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-2 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_WLAN_2GHZ;</div><div class='add'>+			gpios = &lt;&amp;tlmm 13 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-3 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_POWER;</div><div class='add'>+			gpios = &lt;&amp;tlmm 18 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-4 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_ORANGE&gt;;</div><div class='add'>+			function = LED_FUNCTION_WAN;</div><div class='add'>+			gpios = &lt;&amp;tlmm 22 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-5 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_USB;</div><div class='add'>+			gpios = &lt;&amp;tlmm 38 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-6 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_WLAN_5GHZ;</div><div class='add'>+			gpios = &lt;&amp;tlmm 39 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	buttons {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		pinctrl-0 = &lt;&amp;button_pins&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		button-reset {</div><div class='add'>+			debounce-interval = &lt;60&gt;;</div><div class='add'>+			gpios = &lt;&amp;tlmm 25 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			label = "reset";</div><div class='add'>+			linux,code = &lt;KEY_RESTART&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-wps {</div><div class='add'>+			debounce-interval = &lt;60&gt;;</div><div class='add'>+			gpios = &lt;&amp;tlmm 31 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			label = "wps";</div><div class='add'>+			linux,code = &lt;KEY_WPS_BUTTON&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp1_uart1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sleep_clk {</div><div class='add'>+	clock-frequency = &lt;32000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tlmm {</div><div class='add'>+	button_pins: button-pins-state {</div><div class='add'>+		pins = "gpio25", "gpio31";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;8&gt;;</div><div class='add'>+		bias-pull-up;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	led_pins: led-pins-state {</div><div class='add'>+		pins = "gpio10", "gpio11", "gpio13", "gpio18", "gpio22",</div><div class='add'>+		       "gpio38", "gpio39";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart_pins: uart-pins-state {</div><div class='add'>+		pins = "gpio20", "gpio21";</div><div class='add'>+		function = "blsp0_uart0";</div><div class='add'>+		drive-strength = &lt;8&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xo_board_clk {</div><div class='add'>+	clock-div = &lt;4&gt;;</div><div class='add'>+	clock-mult = &lt;1&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi<br/>new file mode 100644<br/>index 000000000000..f024b3cba33f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/ipq5018.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/ipq5018.dtsi</a></div><div class='hunk'>@@ -0,0 +1,994 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause</div><div class='add'>+/*</div><div class='add'>+ * IPQ5018 SoC device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2023-2025 The Linux Foundation. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,apss-ipq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,gcc-ipq5018.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,ipq5018-cmn-pll.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/reset/qcom,gcc-ipq5018.h&gt;</div><div class='add'>+#include &lt;dt-bindings/thermal/thermal.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	interrupt-parent = &lt;&amp;intc&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	clocks {</div><div class='add'>+		gephy_rx_clk: gephy-rx-clk {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			clock-frequency = &lt;125000000&gt;;</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gephy_tx_clk: gephy-tx-clk {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			clock-frequency = &lt;125000000&gt;;</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ref_96mhz_clk: ref-96mhz-clk {</div><div class='add'>+			compatible = "fixed-factor-clock";</div><div class='add'>+			clocks = &lt;&amp;xo_clk&gt;;</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-div = &lt;1&gt;;</div><div class='add'>+			clock-mult = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sleep_clk: sleep-clk {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		xo_board_clk: xo-board-clk {</div><div class='add'>+			compatible = "fixed-factor-clock";</div><div class='add'>+			clocks = &lt;&amp;ref_96mhz_clk&gt;;</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		xo_clk: xo-clk {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-frequency = &lt;48000000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			clocks = &lt;&amp;apcs_glb APCS_ALIAS0_CORE_CLK&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@1 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x1&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			clocks = &lt;&amp;apcs_glb APCS_ALIAS0_CORE_CLK&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_0: l2-cache {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-size = &lt;0x80000&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpu_opp_table: opp-table-cpu {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+		opp-shared;</div><div class='add'>+</div><div class='add'>+		opp-800000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;800000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1100000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1008000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1008000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1100000&gt;;</div><div class='add'>+			clock-latency-ns = &lt;200000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	firmware {</div><div class='add'>+		scm {</div><div class='add'>+			compatible = "qcom,scm-ipq5018", "qcom,scm";</div><div class='add'>+			qcom,dload-mode = &lt;&amp;tcsr 0x6100&gt;;</div><div class='add'>+			qcom,sdi-enabled;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		/* We expect the bootloader to fill in the size */</div><div class='add'>+		reg = &lt;0x0 0x40000000 0x0 0x0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu {</div><div class='add'>+		compatible = "arm,cortex-a53-pmu";</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-1.0";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		bootloader@4a800000 {</div><div class='add'>+			reg = &lt;0x0 0x4a800000 0x0 0x200000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sbl@4aa00000 {</div><div class='add'>+			reg = &lt;0x0 0x4aa00000 0x0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smem@4ab00000 {</div><div class='add'>+			compatible = "qcom,smem";</div><div class='add'>+			reg = &lt;0x0 0x4ab00000 0x0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+</div><div class='add'>+			hwlocks = &lt;&amp;tcsr_mutex 3&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tz_region: tz@4ac00000 {</div><div class='add'>+			reg = &lt;0x0 0x4ac00000 0x0 0x200000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc: soc@0 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges = &lt;0 0 0 0xffffffff&gt;;</div><div class='add'>+</div><div class='add'>+		usbphy0: phy@5b000 {</div><div class='add'>+			compatible = "qcom,ipq5018-usb-hsphy";</div><div class='add'>+			reg = &lt;0x0005b000 0x120&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_USB0_PHY_CFG_AHB_CLK&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_QUSB2_0_PHY_BCR&gt;;</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie1_phy: phy@7e000 {</div><div class='add'>+			compatible = "qcom,ipq5018-uniphy-pcie-phy";</div><div class='add'>+			reg = &lt;0x0007e000 0x800&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_PCIE1_PIPE_CLK&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_PCIE1_PHY_BCR&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1PHY_PHY_BCR&gt;;</div><div class='add'>+</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			num-lanes = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie0_phy: phy@86000 {</div><div class='add'>+			compatible = "qcom,ipq5018-uniphy-pcie-phy";</div><div class='add'>+			reg = &lt;0x00086000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_PCIE0_PIPE_CLK&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_PCIE0_PHY_BCR&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0PHY_PHY_BCR&gt;;</div><div class='add'>+</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			num-lanes = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio0: mdio@88000 {</div><div class='add'>+			compatible = "qcom,ipq5018-mdio";</div><div class='add'>+			reg = &lt;0x00088000 0x64&gt;,</div><div class='add'>+			      &lt;0x019475c4 0x4&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_MDIO0_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "gcc_mdio_ahb_clk";</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			ge_phy: ethernet-phy@7 {</div><div class='add'>+				compatible = "ethernet-phy-id004d.d0c0";</div><div class='add'>+				reg = &lt;7&gt;;</div><div class='add'>+</div><div class='add'>+				resets = &lt;&amp;gcc GCC_GEPHY_MISC_ARES&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio1: mdio@90000 {</div><div class='add'>+			compatible = "qcom,ipq5018-mdio";</div><div class='add'>+			reg = &lt;0x00090000 0x64&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_MDIO1_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "gcc_mdio_ahb_clk";</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmn_pll: clock-controller@9b000 {</div><div class='add'>+			compatible = "qcom,ipq5018-cmn-pll";</div><div class='add'>+			reg = &lt;0x0009b000 0x800&gt;;</div><div class='add'>+			clocks = &lt;&amp;ref_96mhz_clk&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_CMN_BLK_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_CMN_BLK_SYS_CLK&gt;;</div><div class='add'>+			clock-names = "ref",</div><div class='add'>+				      "ahb",</div><div class='add'>+				      "sys";</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			assigned-clocks = &lt;&amp;cmn_pll IPQ5018_CMN_PLL_CLK&gt;;</div><div class='add'>+			assigned-clock-rates-u64 = /bits/ 64 &lt;9600000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qfprom: qfprom@a0000 {</div><div class='add'>+			compatible = "qcom,ipq5018-qfprom", "qcom,qfprom";</div><div class='add'>+			reg = &lt;0x000a0000 0x1000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			tsens_mode: mode@249 {</div><div class='add'>+				reg = &lt;0x249 0x1&gt;;</div><div class='add'>+				bits = &lt;0 3&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tsens_base1: base1@249 {</div><div class='add'>+				reg = &lt;0x249 0x2&gt;;</div><div class='add'>+				bits = &lt;3 8&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tsens_base2: base2@24a {</div><div class='add'>+				reg = &lt;0x24a 0x2&gt;;</div><div class='add'>+				bits = &lt;3 8&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tsens_s0_p1: s0-p1@24b {</div><div class='add'>+				reg = &lt;0x24b 0x2&gt;;</div><div class='add'>+				bits = &lt;2 6&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tsens_s0_p2: s0-p2@24c {</div><div class='add'>+				reg = &lt;0x24c 0x1&gt;;</div><div class='add'>+				bits = &lt;1 6&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tsens_s1_p1: s1-p1@24c {</div><div class='add'>+				reg = &lt;0x24c 0x2&gt;;</div><div class='add'>+				bits = &lt;7 6&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tsens_s1_p2: s1-p2@24d {</div><div class='add'>+				reg = &lt;0x24d 0x2&gt;;</div><div class='add'>+				bits = &lt;5 6&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tsens_s2_p1: s2-p1@24e {</div><div class='add'>+				reg = &lt;0x24e 0x2&gt;;</div><div class='add'>+				bits = &lt;3 6&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tsens_s2_p2: s2-p2@24f {</div><div class='add'>+				reg = &lt;0x24f 0x1&gt;;</div><div class='add'>+				bits = &lt;1 6&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tsens_s3_p1: s3-p1@24f {</div><div class='add'>+				reg = &lt;0x24f 0x2&gt;;</div><div class='add'>+				bits = &lt;7 6&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tsens_s3_p2: s3-p2@250 {</div><div class='add'>+				reg = &lt;0x250 0x2&gt;;</div><div class='add'>+				bits = &lt;5 6&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tsens_s4_p1: s4-p1@251 {</div><div class='add'>+				reg = &lt;0x251 0x2&gt;;</div><div class='add'>+				bits = &lt;3 6&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tsens_s4_p2: s4-p2@254 {</div><div class='add'>+				reg = &lt;0x254 0x1&gt;;</div><div class='add'>+				bits = &lt;0 6&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		prng: rng@e3000 {</div><div class='add'>+			compatible = "qcom,prng-ee";</div><div class='add'>+			reg = &lt;0x000e3000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_PRNG_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "core";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tsens: thermal-sensor@4a9000 {</div><div class='add'>+			compatible = "qcom,ipq5018-tsens", "qcom,tsens-v1";</div><div class='add'>+			reg = &lt;0x004a9000 0x1000&gt;,</div><div class='add'>+			      &lt;0x004a8000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			nvmem-cells = &lt;&amp;tsens_mode&gt;,</div><div class='add'>+				      &lt;&amp;tsens_base1&gt;,</div><div class='add'>+				      &lt;&amp;tsens_base2&gt;,</div><div class='add'>+				      &lt;&amp;tsens_s0_p1&gt;,</div><div class='add'>+				      &lt;&amp;tsens_s0_p2&gt;,</div><div class='add'>+				      &lt;&amp;tsens_s1_p1&gt;,</div><div class='add'>+				      &lt;&amp;tsens_s1_p2&gt;,</div><div class='add'>+				      &lt;&amp;tsens_s2_p1&gt;,</div><div class='add'>+				      &lt;&amp;tsens_s2_p2&gt;,</div><div class='add'>+				      &lt;&amp;tsens_s3_p1&gt;,</div><div class='add'>+				      &lt;&amp;tsens_s3_p2&gt;,</div><div class='add'>+				      &lt;&amp;tsens_s4_p1&gt;,</div><div class='add'>+				      &lt;&amp;tsens_s4_p2&gt;;</div><div class='add'>+</div><div class='add'>+			nvmem-cell-names = "mode",</div><div class='add'>+					   "base1",</div><div class='add'>+					   "base2",</div><div class='add'>+					   "s0_p1",</div><div class='add'>+					   "s0_p2",</div><div class='add'>+					   "s1_p1",</div><div class='add'>+					   "s1_p2",</div><div class='add'>+					   "s2_p1",</div><div class='add'>+					   "s2_p2",</div><div class='add'>+					   "s3_p1",</div><div class='add'>+					   "s3_p2",</div><div class='add'>+					   "s4_p1",</div><div class='add'>+					   "s4_p2";</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 184 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			interrupt-names = "uplow";</div><div class='add'>+			#qcom,sensors = &lt;5&gt;;</div><div class='add'>+			#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cryptobam: dma-controller@704000 {</div><div class='add'>+			compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";</div><div class='add'>+			reg = &lt;0x00704000 0x20000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_CRYPTO_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "bam_clk";</div><div class='add'>+</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+			qcom,ee = &lt;1&gt;;</div><div class='add'>+			qcom,controlled-remotely;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		crypto: crypto@73a000 {</div><div class='add'>+			compatible = "qcom,crypto-v5.1";</div><div class='add'>+			reg = &lt;0x0073a000 0x6000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_CRYPTO_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_CRYPTO_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_CRYPTO_CLK&gt;;</div><div class='add'>+			clock-names = "iface",</div><div class='add'>+				      "bus",</div><div class='add'>+				      "core";</div><div class='add'>+</div><div class='add'>+			dmas = &lt;&amp;cryptobam 2&gt;,</div><div class='add'>+			       &lt;&amp;cryptobam 3&gt;;</div><div class='add'>+			dma-names = "rx",</div><div class='add'>+				    "tx";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tlmm: pinctrl@1000000 {</div><div class='add'>+			compatible = "qcom,ipq5018-tlmm";</div><div class='add'>+			reg = &lt;0x01000000 0x300000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;tlmm 0 0 47&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			uart1_pins: uart1-state {</div><div class='add'>+				pins = "gpio31", "gpio32", "gpio33", "gpio34";</div><div class='add'>+				function = "blsp1_uart1";</div><div class='add'>+				drive-strength = &lt;8&gt;;</div><div class='add'>+				bias-pull-down;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gcc: clock-controller@1800000 {</div><div class='add'>+			compatible = "qcom,gcc-ipq5018";</div><div class='add'>+			reg = &lt;0x01800000 0x80000&gt;;</div><div class='add'>+			clocks = &lt;&amp;xo_board_clk&gt;,</div><div class='add'>+				 &lt;&amp;sleep_clk&gt;,</div><div class='add'>+				 &lt;&amp;pcie0_phy&gt;,</div><div class='add'>+				 &lt;&amp;pcie1_phy&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;&amp;gephy_rx_clk&gt;,</div><div class='add'>+				 &lt;&amp;gephy_tx_clk&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tcsr_mutex: hwlock@1905000 {</div><div class='add'>+			compatible = "qcom,tcsr-mutex";</div><div class='add'>+			reg = &lt;0x01905000 0x20000&gt;;</div><div class='add'>+			#hwlock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tcsr: syscon@1937000 {</div><div class='add'>+			compatible = "qcom,tcsr-ipq5018", "syscon";</div><div class='add'>+			reg = &lt;0x01937000 0x21000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sdhc_1: mmc@7804000 {</div><div class='add'>+			compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5";</div><div class='add'>+			reg = &lt;0x7804000 0x1000&gt;;</div><div class='add'>+			reg-names = "hc";</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "hc_irq", "pwr_irq";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_SDCC1_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_SDCC1_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;xo_board_clk&gt;;</div><div class='add'>+			clock-names = "iface", "core", "xo";</div><div class='add'>+			non-removable;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		blsp_dma: dma-controller@7884000 {</div><div class='add'>+			compatible = "qcom,bam-v1.7.0";</div><div class='add'>+			reg = &lt;0x07884000 0x1d000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "bam_clk";</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+			qcom,ee = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		blsp1_uart1: serial@78af000 {</div><div class='add'>+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";</div><div class='add'>+			reg = &lt;0x078af000 0x200&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_BLSP1_UART1_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "core", "iface";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		blsp1_uart2: serial@78b0000 {</div><div class='add'>+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";</div><div class='add'>+			reg = &lt;0x078b0000 0x200&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_BLSP1_UART2_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "core", "iface";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		blsp1_spi1: spi@78b5000 {</div><div class='add'>+			compatible = "qcom,spi-qup-v2.2.1";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0x078b5000 0x600&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_BLSP1_QUP1_SPI_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "core", "iface";</div><div class='add'>+			dmas = &lt;&amp;blsp_dma 4&gt;, &lt;&amp;blsp_dma 5&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		blsp1_i2c3: i2c@78b7000 {</div><div class='add'>+			compatible = "qcom,i2c-qup-v2.2.1";</div><div class='add'>+			reg = &lt;0x078b7000 0x600&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_BLSP1_QUP3_I2C_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "core", "iface";</div><div class='add'>+			clock-frequency = &lt;400000&gt;;</div><div class='add'>+			dmas = &lt;&amp;blsp_dma 9&gt;, &lt;&amp;blsp_dma 8&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qpic_bam: dma-controller@7984000 {</div><div class='add'>+			compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";</div><div class='add'>+			reg = &lt;0x07984000 0x1c000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_QPIC_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "bam_clk";</div><div class='add'>+</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+			qcom,ee = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qpic_nand: spi@79b0000 {</div><div class='add'>+			compatible = "qcom,ipq5018-snand", "qcom,ipq9574-snand";</div><div class='add'>+			reg = &lt;0x079b0000 0x10000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_QPIC_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_QPIC_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_QPIC_IO_MACRO_CLK&gt;;</div><div class='add'>+			clock-names = "core",</div><div class='add'>+				      "aon",</div><div class='add'>+				      "iom";</div><div class='add'>+</div><div class='add'>+			dmas = &lt;&amp;qpic_bam 0&gt;,</div><div class='add'>+			       &lt;&amp;qpic_bam 1&gt;,</div><div class='add'>+			       &lt;&amp;qpic_bam 2&gt;;</div><div class='add'>+			dma-names = "tx",</div><div class='add'>+				    "rx",</div><div class='add'>+				    "cmd";</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb: usb@8af8800 {</div><div class='add'>+			compatible = "qcom,ipq5018-dwc3", "qcom,dwc3";</div><div class='add'>+			reg = &lt;0x08af8800 0x400&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "hs_phy_irq";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_USB0_MASTER_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_SYS_NOC_USB0_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB0_SLEEP_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB0_MOCK_UTMI_CLK&gt;;</div><div class='add'>+			clock-names = "core",</div><div class='add'>+				      "iface",</div><div class='add'>+				      "sleep",</div><div class='add'>+				      "mock_utmi";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_USB0_BCR&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,select-utmi-as-pipe-clk;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			usb_dwc: usb@8a00000 {</div><div class='add'>+				compatible = "snps,dwc3";</div><div class='add'>+				reg = &lt;0x08a00000 0xe000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_USB0_MOCK_UTMI_CLK&gt;;</div><div class='add'>+				clock-names = "ref";</div><div class='add'>+				interrupts = &lt;GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				phy-names = "usb2-phy";</div><div class='add'>+				phys = &lt;&amp;usbphy0&gt;;</div><div class='add'>+				tx-fifo-resize;</div><div class='add'>+				snps,is-utmi-l1-suspend;</div><div class='add'>+				snps,hird-threshold = /bits/ 8 &lt;0x0&gt;;</div><div class='add'>+				snps,dis_u2_susphy_quirk;</div><div class='add'>+				snps,dis_u3_susphy_quirk;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		intc: interrupt-controller@b000000 {</div><div class='add'>+			compatible = "qcom,msm-qgic2";</div><div class='add'>+			reg = &lt;0x0b000000 0x1000&gt;,  /* GICD */</div><div class='add'>+			      &lt;0x0b002000 0x2000&gt;,  /* GICC */</div><div class='add'>+			      &lt;0x0b001000 0x1000&gt;,  /* GICH */</div><div class='add'>+			      &lt;0x0b004000 0x2000&gt;;  /* GICV */</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges = &lt;0 0x0b00a000 0x1ffa&gt;;</div><div class='add'>+</div><div class='add'>+			v2m0: v2m@0 {</div><div class='add'>+				compatible = "arm,gic-v2m-frame";</div><div class='add'>+				reg = &lt;0x00000000 0xff8&gt;;</div><div class='add'>+				msi-controller;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			v2m1: v2m@1000 {</div><div class='add'>+				compatible = "arm,gic-v2m-frame";</div><div class='add'>+				reg = &lt;0x00001000 0xff8&gt;;</div><div class='add'>+				msi-controller;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		watchdog: watchdog@b017000 {</div><div class='add'>+			compatible = "qcom,apss-wdt-ipq5018", "qcom,kpss-wdt";</div><div class='add'>+			reg = &lt;0x0b017000 0x40&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 3 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			clocks = &lt;&amp;sleep_clk&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		apcs_glb: mailbox@b111000 {</div><div class='add'>+			compatible = "qcom,ipq5018-apcs-apps-global",</div><div class='add'>+				     "qcom,ipq6018-apcs-apps-global";</div><div class='add'>+			reg = &lt;0x0b111000 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;a53pll&gt;, &lt;&amp;xo_board_clk&gt;, &lt;&amp;gcc GPLL0&gt;;</div><div class='add'>+			clock-names = "pll", "xo", "gpll0";</div><div class='add'>+			#mbox-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		a53pll: clock@b116000 {</div><div class='add'>+			compatible = "qcom,ipq5018-a53pll";</div><div class='add'>+			reg = &lt;0x0b116000 0x40&gt;;</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clocks = &lt;&amp;xo_board_clk&gt;;</div><div class='add'>+			clock-names = "xo";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		timer@b120000 {</div><div class='add'>+			compatible = "arm,armv7-timer-mem";</div><div class='add'>+			reg = &lt;0x0b120000 0x1000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			frame@b120000 {</div><div class='add'>+				reg = &lt;0x0b121000 0x1000&gt;,</div><div class='add'>+				      &lt;0x0b122000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				frame-number = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@b123000 {</div><div class='add'>+				reg = &lt;0xb123000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				frame-number = &lt;1&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@b124000 {</div><div class='add'>+				frame-number = &lt;2&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				reg = &lt;0x0b124000 0x1000&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@b125000 {</div><div class='add'>+				reg = &lt;0x0b125000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				frame-number = &lt;3&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@b126000 {</div><div class='add'>+				reg = &lt;0x0b126000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				frame-number = &lt;4&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@b127000 {</div><div class='add'>+				reg = &lt;0x0b127000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				frame-number = &lt;5&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@b128000 {</div><div class='add'>+				reg = &lt;0x0b128000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				frame-number = &lt;6&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie1: pcie@80000000 {</div><div class='add'>+			compatible = "qcom,pcie-ipq5018";</div><div class='add'>+			reg = &lt;0x80000000 0xf1d&gt;,</div><div class='add'>+			      &lt;0x80000f20 0xa8&gt;,</div><div class='add'>+			      &lt;0x80001000 0x1000&gt;,</div><div class='add'>+			      &lt;0x00078000 0x3000&gt;,</div><div class='add'>+			      &lt;0x80100000 0x1000&gt;,</div><div class='add'>+			      &lt;0x0007b000 0x1000&gt;;</div><div class='add'>+			reg-names = "dbi",</div><div class='add'>+				    "elbi",</div><div class='add'>+				    "atu",</div><div class='add'>+				    "parf",</div><div class='add'>+				    "config",</div><div class='add'>+				    "mhi";</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			linux,pci-domain = &lt;1&gt;;</div><div class='add'>+			bus-range = &lt;0x00 0xff&gt;;</div><div class='add'>+			num-lanes = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			/* The controller supports Gen3, but the connected PHY is Gen2-capable */</div><div class='add'>+			max-link-speed = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;pcie1_phy&gt;;</div><div class='add'>+			phy-names = "pciephy";</div><div class='add'>+</div><div class='add'>+			ranges = &lt;0x01000000 0 0x00000000 0x80200000 0 0x00100000&gt;,</div><div class='add'>+				 &lt;0x02000000 0 0x80300000 0x80300000 0 0x10000000&gt;;</div><div class='add'>+</div><div class='add'>+			msi-map = &lt;0x0 &amp;v2m0 0x0 0xff8&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "msi0",</div><div class='add'>+					  "msi1",</div><div class='add'>+					  "msi2",</div><div class='add'>+					  "msi3",</div><div class='add'>+					  "msi4",</div><div class='add'>+					  "msi5",</div><div class='add'>+					  "msi6",</div><div class='add'>+					  "msi7",</div><div class='add'>+					  "global";</div><div class='add'>+</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0x7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;intc 0 GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;intc 0 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;intc 0 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;intc 0 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_SYS_NOC_PCIE1_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_AXI_M_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_AXI_S_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_AXI_S_BRIDGE_CLK&gt;;</div><div class='add'>+			clock-names = "iface",</div><div class='add'>+				      "axi_m",</div><div class='add'>+				      "axi_s",</div><div class='add'>+				      "ahb",</div><div class='add'>+				      "aux",</div><div class='add'>+				      "axi_bridge";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_PCIE1_PIPE_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_SLEEP_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_CORE_STICKY_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_AXI_MASTER_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_AXI_SLAVE_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_AHB_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_AXI_SLAVE_STICKY_ARES&gt;;</div><div class='add'>+			reset-names = "pipe",</div><div class='add'>+				      "sleep",</div><div class='add'>+				      "sticky",</div><div class='add'>+				      "axi_m",</div><div class='add'>+				      "axi_s",</div><div class='add'>+				      "ahb",</div><div class='add'>+				      "axi_m_sticky",</div><div class='add'>+				      "axi_s_sticky";</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcie@0 {</div><div class='add'>+				device_type = "pci";</div><div class='add'>+				reg = &lt;0x0 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+				bus-range = &lt;0x01 0xff&gt;;</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;3&gt;;</div><div class='add'>+				#size-cells = &lt;2&gt;;</div><div class='add'>+				ranges;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie0: pcie@a0000000 {</div><div class='add'>+			compatible = "qcom,pcie-ipq5018";</div><div class='add'>+			reg = &lt;0xa0000000 0xf1d&gt;,</div><div class='add'>+			      &lt;0xa0000f20 0xa8&gt;,</div><div class='add'>+			      &lt;0xa0001000 0x1000&gt;,</div><div class='add'>+			      &lt;0x00080000 0x3000&gt;,</div><div class='add'>+			      &lt;0xa0100000 0x1000&gt;,</div><div class='add'>+			      &lt;0x00083000 0x1000&gt;;</div><div class='add'>+			reg-names = "dbi",</div><div class='add'>+				    "elbi",</div><div class='add'>+				    "atu",</div><div class='add'>+				    "parf",</div><div class='add'>+				    "config",</div><div class='add'>+				    "mhi";</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			linux,pci-domain = &lt;0&gt;;</div><div class='add'>+			bus-range = &lt;0x00 0xff&gt;;</div><div class='add'>+			num-lanes = &lt;2&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			/* The controller supports Gen3, but the connected PHY is Gen2-capable */</div><div class='add'>+			max-link-speed = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;pcie0_phy&gt;;</div><div class='add'>+			phy-names = "pciephy";</div><div class='add'>+</div><div class='add'>+			ranges = &lt;0x01000000 0 0x00000000 0xa0200000 0 0x00100000&gt;,</div><div class='add'>+				 &lt;0x02000000 0 0xa0300000 0xa0300000 0 0x10000000&gt;;</div><div class='add'>+</div><div class='add'>+			msi-map = &lt;0x0 &amp;v2m0 0x0 0xff8&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "msi0",</div><div class='add'>+					  "msi1",</div><div class='add'>+					  "msi2",</div><div class='add'>+					  "msi3",</div><div class='add'>+					  "msi4",</div><div class='add'>+					  "msi5",</div><div class='add'>+					  "msi6",</div><div class='add'>+					  "msi7",</div><div class='add'>+					  "global";</div><div class='add'>+</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0x7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;intc 0 GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;intc 0 GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;intc 0 GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;intc 0 GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_SYS_NOC_PCIE0_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AXI_M_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AXI_S_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AXI_S_BRIDGE_CLK&gt;;</div><div class='add'>+			clock-names = "iface",</div><div class='add'>+				      "axi_m",</div><div class='add'>+				      "axi_s",</div><div class='add'>+				      "ahb",</div><div class='add'>+				      "aux",</div><div class='add'>+				      "axi_bridge";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_PCIE0_PIPE_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_SLEEP_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_CORE_STICKY_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AXI_MASTER_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AXI_SLAVE_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AHB_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES&gt;;</div><div class='add'>+			reset-names = "pipe",</div><div class='add'>+				      "sleep",</div><div class='add'>+				      "sticky",</div><div class='add'>+				      "axi_m",</div><div class='add'>+				      "axi_s",</div><div class='add'>+				      "ahb",</div><div class='add'>+				      "axi_m_sticky",</div><div class='add'>+				      "axi_s_sticky";</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcie@0 {</div><div class='add'>+				device_type = "pci";</div><div class='add'>+				reg = &lt;0x0 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+				bus-range = &lt;0x01 0xff&gt;;</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;3&gt;;</div><div class='add'>+				#size-cells = &lt;2&gt;;</div><div class='add'>+				ranges;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	thermal-zones {</div><div class='add'>+		cpu-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 2&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu-critical {</div><div class='add'>+					temperature = &lt;120000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_alert: cpu-passive {</div><div class='add'>+					temperature = &lt;100000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu_alert&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gephy-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 4&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				gephy-critical {</div><div class='add'>+					temperature = &lt;120000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		top-glue-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 3&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				top-glue-critical {</div><div class='add'>+					temperature = &lt;120000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ubi32-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 1&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				ubi32-critical {</div><div class='add'>+					temperature = &lt;120000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi<br/>new file mode 100644<br/>index 000000000000..b37ae7749083<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi</a></div><div class='hunk'>@@ -0,0 +1,81 @@</div><div class='add'>+// SPDX-License-Identifier: BSD-3-Clause</div><div class='add'>+/*</div><div class='add'>+ * IPQ5332 RDP board common device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include "ipq5332.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;blsp1_uart0;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		pinctrl-0 = &lt;&amp;gpio_keys_default&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		button-wps {</div><div class='add'>+			label = "wps";</div><div class='add'>+			linux,code = &lt;KEY_WPS_BUTTON&gt;;</div><div class='add'>+			gpios = &lt;&amp;tlmm 35 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			debounce-interval = &lt;60&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-0 = &lt;&amp;gpio_leds_default&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_WLAN;</div><div class='add'>+			gpios = &lt;&amp;tlmm 36 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "phy0tx";</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp1_uart0 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;serial_0_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sleep_clk {</div><div class='add'>+	clock-frequency = &lt;32000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xo_board {</div><div class='add'>+	clock-frequency = &lt;24000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* PINCTRL */</div><div class='add'>+&amp;tlmm {</div><div class='add'>+	gpio_keys_default: gpio-keys-default-state {</div><div class='add'>+		pins = "gpio35";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;8&gt;;</div><div class='add'>+		bias-pull-up;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio_leds_default: gpio-leds-default-state {</div><div class='add'>+		pins = "gpio36";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;8&gt;;</div><div class='add'>+		bias-pull-down;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts<br/>new file mode 100644<br/>index 000000000000..79ec77cfe552<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts</a></div><div class='hunk'>@@ -0,0 +1,141 @@</div><div class='add'>+// SPDX-License-Identifier: BSD-3-Clause</div><div class='add'>+/*</div><div class='add'>+ * IPQ5332 AP-MI01.2 board device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "ipq5332-rdp-common.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Qualcomm Technologies, Inc. IPQ5332 MI01.2";</div><div class='add'>+	compatible = "qcom,ipq5332-ap-mi01.2", "qcom,ipq5332";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp1_i2c1 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c_1_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sdhc {</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	max-frequency = &lt;192000000&gt;;</div><div class='add'>+	mmc-ddr-1_8v;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	non-removable;</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdc_default_state&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pcie0_default&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	perst-gpios = &lt;&amp;tlmm 38 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	wake-gpios = &lt;&amp;tlmm 39 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pcie1_default&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	perst-gpios = &lt;&amp;tlmm 47 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	wake-gpios = &lt;&amp;tlmm 48 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie1_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tlmm {</div><div class='add'>+	i2c_1_pins: i2c-1-state {</div><div class='add'>+		pins = "gpio29", "gpio30";</div><div class='add'>+		function = "blsp1_i2c0";</div><div class='add'>+		drive-strength = &lt;8&gt;;</div><div class='add'>+		bias-pull-up;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_default: pcie0-default-state {</div><div class='add'>+		clkreq-n-pins {</div><div class='add'>+			pins = "gpio37";</div><div class='add'>+			function = "pcie0_clk";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		perst-n-pins {</div><div class='add'>+			pins = "gpio38";</div><div class='add'>+			function = "gpio";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wake-n-pins {</div><div class='add'>+			pins = "gpio39";</div><div class='add'>+			function = "pcie0_wake";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie1_default: pcie1-default-state {</div><div class='add'>+		clkreq-n-pins {</div><div class='add'>+			pins = "gpio46";</div><div class='add'>+			function = "pcie1_clk";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		perst-n-pins {</div><div class='add'>+			pins = "gpio47";</div><div class='add'>+			function = "gpio";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wake-n-pins {</div><div class='add'>+			pins = "gpio48";</div><div class='add'>+			function = "pcie1_wake";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdc_default_state: sdc-default-state {</div><div class='add'>+		clk-pins {</div><div class='add'>+			pins = "gpio13";</div><div class='add'>+			function = "sdc_clk";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmd-pins {</div><div class='add'>+			pins = "gpio12";</div><div class='add'>+			function = "sdc_cmd";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		data-pins {</div><div class='add'>+			pins = "gpio8", "gpio9", "gpio10", "gpio11";</div><div class='add'>+			function = "sdc_data";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts<br/>new file mode 100644<br/>index 000000000000..ed8a54eb95c0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts</a></div><div class='hunk'>@@ -0,0 +1,93 @@</div><div class='add'>+// SPDX-License-Identifier: BSD-3-Clause</div><div class='add'>+/*</div><div class='add'>+ * IPQ5332 RDP442 board device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "ipq5332-rdp-common.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Qualcomm Technologies, Inc. IPQ5332 MI01.3";</div><div class='add'>+	compatible = "qcom,ipq5332-ap-mi01.3", "qcom,ipq5332";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp1_i2c1 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c_1_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp1_spi0 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;spi_0_data_clk_pins &amp;spi_0_cs_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash@0 {</div><div class='add'>+		compatible = "micron,n25q128a11", "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		spi-max-frequency = &lt;50000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sdhc {</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	max-frequency = &lt;192000000&gt;;</div><div class='add'>+	mmc-ddr-1_8v;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	non-removable;</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdc_default_state&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tlmm {</div><div class='add'>+	i2c_1_pins: i2c-1-state {</div><div class='add'>+		pins = "gpio29", "gpio30";</div><div class='add'>+		function = "blsp1_i2c0";</div><div class='add'>+		drive-strength = &lt;8&gt;;</div><div class='add'>+		bias-pull-up;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdc_default_state: sdc-default-state {</div><div class='add'>+		clk-pins {</div><div class='add'>+			pins = "gpio13";</div><div class='add'>+			function = "sdc_clk";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmd-pins {</div><div class='add'>+			pins = "gpio12";</div><div class='add'>+			function = "sdc_cmd";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		data-pins {</div><div class='add'>+			pins = "gpio8", "gpio9", "gpio10", "gpio11";</div><div class='add'>+			function = "sdc_data";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi_0_data_clk_pins: spi-0-data-clk-state {</div><div class='add'>+		pins = "gpio14", "gpio15", "gpio16";</div><div class='add'>+		function = "blsp0_spi";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-pull-down;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi_0_cs_pins: spi-0-cs-state {</div><div class='add'>+		pins = "gpio17";</div><div class='add'>+		function = "blsp0_spi";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-pull-up;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts<br/>new file mode 100644<br/>index 000000000000..c224ffc65b08<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts</a></div><div class='hunk'>@@ -0,0 +1,104 @@</div><div class='add'>+// SPDX-License-Identifier: BSD-3-Clause</div><div class='add'>+/*</div><div class='add'>+ * IPQ5332 RDP468 board device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "ipq5332-rdp-common.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Qualcomm Technologies, Inc. IPQ5332 MI01.6";</div><div class='add'>+	compatible = "qcom,ipq5332-ap-mi01.6", "qcom,ipq5332";</div><div class='add'>+</div><div class='add'>+	regulator_fixed_5p0: regulator-s0500 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-min-microvolt = &lt;500000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;500000&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-name = "fixed_5p0";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp1_spi0 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;spi_0_data_clk_pins &amp;spi_0_cs_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash@0 {</div><div class='add'>+		compatible = "micron,n25q128a11", "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		spi-max-frequency = &lt;50000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sdhc {</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	max-frequency = &lt;192000000&gt;;</div><div class='add'>+	mmc-ddr-1_8v;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	non-removable;</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdc_default_state&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* PINCTRL */</div><div class='add'>+</div><div class='add'>+&amp;tlmm {</div><div class='add'>+	sdc_default_state: sdc-default-state {</div><div class='add'>+		clk-pins {</div><div class='add'>+			pins = "gpio13";</div><div class='add'>+			function = "sdc_clk";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmd-pins {</div><div class='add'>+			pins = "gpio12";</div><div class='add'>+			function = "sdc_cmd";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		data-pins {</div><div class='add'>+			pins = "gpio8", "gpio9", "gpio10", "gpio11";</div><div class='add'>+			function = "sdc_data";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi_0_data_clk_pins: spi-0-data-clk-state {</div><div class='add'>+		pins = "gpio14", "gpio15", "gpio16";</div><div class='add'>+		function = "blsp0_spi";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-pull-down;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi_0_cs_pins: spi-0-cs-state {</div><div class='add'>+		pins = "gpio17";</div><div class='add'>+		function = "blsp0_spi";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-pull-up;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_dwc {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usbphy0 {</div><div class='add'>+	vdd-supply = &lt;&amp;regulator_fixed_5p0&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp474.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp474.dts<br/>new file mode 100644<br/>index 000000000000..d5f99e741ae5<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/ipq5332-rdp474.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/ipq5332-rdp474.dts</a></div><div class='hunk'>@@ -0,0 +1,67 @@</div><div class='add'>+// SPDX-License-Identifier: BSD-3-Clause</div><div class='add'>+/*</div><div class='add'>+ * IPQ5332 RDP474 board device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "ipq5332-rdp-common.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Qualcomm Technologies, Inc. IPQ5332 MI01.9";</div><div class='add'>+	compatible = "qcom,ipq5332-ap-mi01.9", "qcom,ipq5332";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp1_i2c1 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	pinctrl-0 = &lt;&amp;i2c_1_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sdhc {</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	max-frequency = &lt;192000000&gt;;</div><div class='add'>+	mmc-ddr-1_8v;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	non-removable;</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdc_default_state&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* PINCTRL */</div><div class='add'>+</div><div class='add'>+&amp;tlmm {</div><div class='add'>+	i2c_1_pins: i2c-1-state {</div><div class='add'>+		pins = "gpio29", "gpio30";</div><div class='add'>+		function = "blsp1_i2c0";</div><div class='add'>+		drive-strength = &lt;8&gt;;</div><div class='add'>+		bias-pull-up;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdc_default_state: sdc-default-state {</div><div class='add'>+		clk-pins {</div><div class='add'>+			pins = "gpio13";</div><div class='add'>+			function = "sdc_clk";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmd-pins {</div><div class='add'>+			pins = "gpio12";</div><div class='add'>+			function = "sdc_cmd";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		data-pins {</div><div class='add'>+			pins = "gpio8", "gpio9", "gpio10", "gpio11";</div><div class='add'>+			function = "sdc_data";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi<br/>new file mode 100644<br/>index 000000000000..45fc512a3bab<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/ipq5332.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/ipq5332.dtsi</a></div><div class='hunk'>@@ -0,0 +1,874 @@</div><div class='add'>+// SPDX-License-Identifier: BSD-3-Clause</div><div class='add'>+/*</div><div class='add'>+ * IPQ5332 device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,apss-ipq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,ipq5332-gcc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interconnect/qcom,ipq5332.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	interrupt-parent = &lt;&amp;intc&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	clocks {</div><div class='add'>+		sleep_clk: sleep-clk {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		xo_board: xo-board-clk {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			clocks = &lt;&amp;apcs_glb APCS_ALIAS0_CORE_CLK&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@1 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x1&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			clocks = &lt;&amp;apcs_glb APCS_ALIAS0_CORE_CLK&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@2 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x2&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			clocks = &lt;&amp;apcs_glb APCS_ALIAS0_CORE_CLK&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@3 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x3&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			clocks = &lt;&amp;apcs_glb APCS_ALIAS0_CORE_CLK&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_0: l2-cache {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	firmware {</div><div class='add'>+		scm {</div><div class='add'>+			compatible = "qcom,scm-ipq5332", "qcom,scm";</div><div class='add'>+			qcom,dload-mode = &lt;&amp;tcsr 0x6100&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		/* We expect the bootloader to fill in the size */</div><div class='add'>+		reg = &lt;0x0 0x40000000 0x0 0x0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpu_opp_table: opp-table-cpu {</div><div class='add'>+		compatible = "operating-points-v2-kryo-cpu";</div><div class='add'>+		opp-shared;</div><div class='add'>+		nvmem-cells = &lt;&amp;cpu_speed_bin&gt;;</div><div class='add'>+</div><div class='add'>+		opp-1100000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1100000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x7&gt;;</div><div class='add'>+			clock-latency-ns = &lt;200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1500000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1500000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x3&gt;;</div><div class='add'>+			clock-latency-ns = &lt;200000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu {</div><div class='add'>+		compatible = "arm,cortex-a53-pmu";</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-1.0";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		bootloader@4a100000 {</div><div class='add'>+			reg = &lt;0x0 0x4a100000 0x0 0x400000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sbl@4a500000 {</div><div class='add'>+			reg = &lt;0x0 0x4a500000 0x0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tz_mem: tz@4a600000 {</div><div class='add'>+			reg = &lt;0x0 0x4a600000 0x0 0x200000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smem@4a800000 {</div><div class='add'>+			compatible = "qcom,smem";</div><div class='add'>+			reg = &lt;0x0 0x4a800000 0x0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+</div><div class='add'>+			hwlocks = &lt;&amp;tcsr_mutex 3&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc@0 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges = &lt;0 0 0 0xffffffff&gt;;</div><div class='add'>+</div><div class='add'>+		usbphy0: phy@7b000 {</div><div class='add'>+			compatible = "qcom,ipq5332-usb-hsphy";</div><div class='add'>+			reg = &lt;0x0007b000 0x12c&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_USB0_PHY_CFG_AHB_CLK&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_QUSB2_0_PHY_BCR&gt;;</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qfprom: efuse@a4000 {</div><div class='add'>+			compatible = "qcom,ipq5332-qfprom", "qcom,qfprom";</div><div class='add'>+			reg = &lt;0x000a4000 0x721&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			cpu_speed_bin: cpu-speed-bin@1d {</div><div class='add'>+				reg = &lt;0x1d 0x2&gt;;</div><div class='add'>+				bits = &lt;7 2&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tsens_sens11_off: s11@3a5 {</div><div class='add'>+				reg = &lt;0x3a5 0x1&gt;;</div><div class='add'>+				bits = &lt;4 4&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tsens_sens12_off: s12@3a6 {</div><div class='add'>+				reg = &lt;0x3a6 0x1&gt;;</div><div class='add'>+				bits = &lt;0 4&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tsens_sens13_off: s13@3a6 {</div><div class='add'>+				reg = &lt;0x3a6 0x1&gt;;</div><div class='add'>+				bits = &lt;4 4&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tsens_sens14_off: s14@3ad {</div><div class='add'>+				reg = &lt;0x3ad 0x2&gt;;</div><div class='add'>+				bits = &lt;7 4&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tsens_sens15_off: s15@3ae {</div><div class='add'>+				reg = &lt;0x3ae 0x1&gt;;</div><div class='add'>+				bits = &lt;3 4&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tsens_mode: mode@3e1 {</div><div class='add'>+				reg = &lt;0x3e1 0x1&gt;;</div><div class='add'>+				bits = &lt;0 3&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tsens_base0: base0@3e1 {</div><div class='add'>+				reg = &lt;0x3e1 0x2&gt;;</div><div class='add'>+				bits = &lt;3 10&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tsens_base1: base1@3e2 {</div><div class='add'>+				reg = &lt;0x3e2 0x2&gt;;</div><div class='add'>+				bits = &lt;5 10&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rng: rng@e3000 {</div><div class='add'>+			compatible = "qcom,ipq5332-trng", "qcom,trng";</div><div class='add'>+			reg = &lt;0x000e3000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_PRNG_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "core";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tsens: thermal-sensor@4a9000 {</div><div class='add'>+			compatible = "qcom,ipq5332-tsens";</div><div class='add'>+			reg = &lt;0x004a9000 0x1000&gt;,</div><div class='add'>+			      &lt;0x004a8000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "combined";</div><div class='add'>+			nvmem-cells = &lt;&amp;tsens_mode&gt;,</div><div class='add'>+				      &lt;&amp;tsens_base0&gt;,</div><div class='add'>+				      &lt;&amp;tsens_base1&gt;,</div><div class='add'>+				      &lt;&amp;tsens_sens11_off&gt;,</div><div class='add'>+				      &lt;&amp;tsens_sens12_off&gt;,</div><div class='add'>+				      &lt;&amp;tsens_sens13_off&gt;,</div><div class='add'>+				      &lt;&amp;tsens_sens14_off&gt;,</div><div class='add'>+				      &lt;&amp;tsens_sens15_off&gt;;</div><div class='add'>+			nvmem-cell-names = "mode",</div><div class='add'>+					   "base0",</div><div class='add'>+					   "base1",</div><div class='add'>+					   "tsens_sens11_off",</div><div class='add'>+					   "tsens_sens12_off",</div><div class='add'>+					   "tsens_sens13_off",</div><div class='add'>+					   "tsens_sens14_off",</div><div class='add'>+					   "tsens_sens15_off";</div><div class='add'>+			#qcom,sensors = &lt;5&gt;;</div><div class='add'>+			#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie0_phy: phy@4b0000 {</div><div class='add'>+			compatible = "qcom,ipq5332-uniphy-pcie-phy";</div><div class='add'>+			reg = &lt;0x004b0000 0x800&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_PCIE3X1_0_PIPE_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3X1_PHY_AHB_CLK&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_PCIE3X1_0_PHY_BCR&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3X1_PHY_AHB_CLK_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3X1_0_PHY_PHY_BCR&gt;;</div><div class='add'>+</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			num-lanes = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie1_phy: phy@4b1000 {</div><div class='add'>+			compatible = "qcom,ipq5332-uniphy-pcie-phy";</div><div class='add'>+			reg = &lt;0x004b1000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_PCIE3X2_PIPE_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3X2_PHY_AHB_CLK&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_PCIE3X2_PHY_BCR&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3X2_PHY_AHB_CLK_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3X2PHY_PHY_BCR&gt;;</div><div class='add'>+</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			num-lanes = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tlmm: pinctrl@1000000 {</div><div class='add'>+			compatible = "qcom,ipq5332-tlmm";</div><div class='add'>+			reg = &lt;0x01000000 0x300000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;tlmm 0 0 53&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			serial_0_pins: serial0-state {</div><div class='add'>+				pins = "gpio18", "gpio19";</div><div class='add'>+				function = "blsp0_uart0";</div><div class='add'>+				drive-strength = &lt;8&gt;;</div><div class='add'>+				bias-pull-up;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gcc: clock-controller@1800000 {</div><div class='add'>+			compatible = "qcom,ipq5332-gcc";</div><div class='add'>+			reg = &lt;0x01800000 0x80000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+			#interconnect-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;xo_board&gt;,</div><div class='add'>+				 &lt;&amp;sleep_clk&gt;,</div><div class='add'>+				 &lt;&amp;pcie1_phy&gt;,</div><div class='add'>+				 &lt;&amp;pcie0_phy&gt;,</div><div class='add'>+				 &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tcsr_mutex: hwlock@1905000 {</div><div class='add'>+			compatible = "qcom,tcsr-mutex";</div><div class='add'>+			reg = &lt;0x01905000 0x20000&gt;;</div><div class='add'>+			#hwlock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tcsr: syscon@1937000 {</div><div class='add'>+			compatible = "qcom,tcsr-ipq5332", "syscon";</div><div class='add'>+			reg = &lt;0x01937000 0x21000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sdhc: mmc@7804000 {</div><div class='add'>+			compatible = "qcom,ipq5332-sdhci", "qcom,sdhci-msm-v5";</div><div class='add'>+			reg = &lt;0x07804000 0x1000&gt;, &lt;0x07805000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "hc_irq", "pwr_irq";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_SDCC1_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_SDCC1_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;xo_board&gt;;</div><div class='add'>+			clock-names = "iface", "core", "xo";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		blsp_dma: dma-controller@7884000 {</div><div class='add'>+			compatible = "qcom,bam-v1.7.0";</div><div class='add'>+			reg = &lt;0x07884000 0x1d000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "bam_clk";</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+			qcom,ee = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		blsp1_uart0: serial@78af000 {</div><div class='add'>+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";</div><div class='add'>+			reg = &lt;0x078af000 0x200&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_BLSP1_UART1_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "core", "iface";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		blsp1_uart1: serial@78b0000 {</div><div class='add'>+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";</div><div class='add'>+			reg = &lt;0x078b0000 0x200&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_BLSP1_UART2_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "core", "iface";</div><div class='add'>+			dmas = &lt;&amp;blsp_dma 2&gt;, &lt;&amp;blsp_dma 3&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		blsp1_spi0: spi@78b5000 {</div><div class='add'>+			compatible = "qcom,spi-qup-v2.2.1";</div><div class='add'>+			reg = &lt;0x078b5000 0x600&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_BLSP1_QUP1_SPI_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "core", "iface";</div><div class='add'>+			dmas = &lt;&amp;blsp_dma 4&gt;, &lt;&amp;blsp_dma 5&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		blsp1_i2c1: i2c@78b6000 {</div><div class='add'>+			compatible = "qcom,i2c-qup-v2.2.1";</div><div class='add'>+			reg = &lt;0x078b6000 0x600&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_BLSP1_QUP2_I2C_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "core", "iface";</div><div class='add'>+			dmas = &lt;&amp;blsp_dma 6&gt;, &lt;&amp;blsp_dma 7&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		blsp1_spi2: spi@78b7000 {</div><div class='add'>+			compatible = "qcom,spi-qup-v2.2.1";</div><div class='add'>+			reg = &lt;0x078b7000 0x600&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_BLSP1_QUP3_SPI_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "core", "iface";</div><div class='add'>+			dmas = &lt;&amp;blsp_dma 8&gt;, &lt;&amp;blsp_dma 9&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb: usb@8af8800 {</div><div class='add'>+			compatible = "qcom,ipq5332-dwc3", "qcom,dwc3";</div><div class='add'>+			reg = &lt;0x08af8800 0x400&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "pwr_event",</div><div class='add'>+					  "dp_hs_phy_irq",</div><div class='add'>+					  "dm_hs_phy_irq";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_USB0_MASTER_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB0_SLEEP_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB0_MOCK_UTMI_CLK&gt;;</div><div class='add'>+			clock-names = "core",</div><div class='add'>+				      "sleep",</div><div class='add'>+				      "mock_utmi";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_USB_BCR&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,select-utmi-as-pipe-clk;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			interconnects = &lt;&amp;gcc MASTER_SNOC_USB &amp;gcc SLAVE_SNOC_USB&gt;,</div><div class='add'>+					&lt;&amp;gcc MASTER_SNOC_USB &amp;gcc SLAVE_SNOC_USB&gt;;</div><div class='add'>+			interconnect-names = "usb-ddr", "apps-usb";</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			usb_dwc: usb@8a00000 {</div><div class='add'>+				compatible = "snps,dwc3";</div><div class='add'>+				reg = &lt;0x08a00000 0xe000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_USB0_MOCK_UTMI_CLK&gt;;</div><div class='add'>+				clock-names = "ref";</div><div class='add'>+				interrupts = &lt;GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				phy-names = "usb2-phy";</div><div class='add'>+				phys = &lt;&amp;usbphy0&gt;;</div><div class='add'>+				tx-fifo-resize;</div><div class='add'>+				snps,is-utmi-l1-suspend;</div><div class='add'>+				snps,hird-threshold = /bits/ 8 &lt;0x0&gt;;</div><div class='add'>+				snps,dis_u2_susphy_quirk;</div><div class='add'>+				snps,dis_u3_susphy_quirk;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		intc: interrupt-controller@b000000 {</div><div class='add'>+			compatible = "qcom,msm-qgic2";</div><div class='add'>+			reg = &lt;0x0b000000 0x1000&gt;,	/* GICD */</div><div class='add'>+			      &lt;0x0b002000 0x1000&gt;,	/* GICC */</div><div class='add'>+			      &lt;0x0b001000 0x1000&gt;,	/* GICH */</div><div class='add'>+			      &lt;0x0b004000 0x1000&gt;;	/* GICV */</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges = &lt;0 0x0b00c000 0x3000&gt;;</div><div class='add'>+</div><div class='add'>+			v2m0: v2m@0 {</div><div class='add'>+				compatible = "arm,gic-v2m-frame";</div><div class='add'>+				reg = &lt;0x00000000 0xffd&gt;;</div><div class='add'>+				msi-controller;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			v2m1: v2m@1000 {</div><div class='add'>+				compatible = "arm,gic-v2m-frame";</div><div class='add'>+				reg = &lt;0x00001000 0xffd&gt;;</div><div class='add'>+				msi-controller;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			v2m2: v2m@2000 {</div><div class='add'>+				compatible = "arm,gic-v2m-frame";</div><div class='add'>+				reg = &lt;0x00002000 0xffd&gt;;</div><div class='add'>+				msi-controller;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		watchdog: watchdog@b017000 {</div><div class='add'>+			compatible = "qcom,apss-wdt-ipq5332", "qcom,kpss-wdt";</div><div class='add'>+			reg = &lt;0x0b017000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 3 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			clocks = &lt;&amp;sleep_clk&gt;;</div><div class='add'>+			timeout-sec = &lt;30&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		apcs_glb: mailbox@b111000 {</div><div class='add'>+			compatible = "qcom,ipq5332-apcs-apps-global",</div><div class='add'>+				     "qcom,ipq6018-apcs-apps-global";</div><div class='add'>+			reg = &lt;0x0b111000 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;a53pll&gt;, &lt;&amp;xo_board&gt;, &lt;&amp;gcc GPLL0&gt;;</div><div class='add'>+			clock-names = "pll", "xo", "gpll0";</div><div class='add'>+			#mbox-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		a53pll: clock@b116000 {</div><div class='add'>+			compatible = "qcom,ipq5332-a53pll";</div><div class='add'>+			reg = &lt;0x0b116000 0x40&gt;;</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clocks = &lt;&amp;xo_board&gt;;</div><div class='add'>+			clock-names = "xo";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		timer@b120000 {</div><div class='add'>+			compatible = "arm,armv7-timer-mem";</div><div class='add'>+			reg = &lt;0x0b120000 0x1000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			frame@b120000 {</div><div class='add'>+				reg = &lt;0x0b121000 0x1000&gt;,</div><div class='add'>+				      &lt;0x0b122000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				frame-number = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@b123000 {</div><div class='add'>+				reg = &lt;0x0b123000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				frame-number = &lt;1&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@b124000 {</div><div class='add'>+				reg = &lt;0x0b124000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				frame-number = &lt;2&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@b125000 {</div><div class='add'>+				reg = &lt;0x0b125000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				frame-number = &lt;3&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@b126000 {</div><div class='add'>+				reg = &lt;0x0b126000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				frame-number = &lt;4&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@b127000 {</div><div class='add'>+				reg = &lt;0x0b127000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				frame-number = &lt;5&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@b128000 {</div><div class='add'>+				reg = &lt;0x0b128000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				frame-number = &lt;6&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie1: pcie@18000000 {</div><div class='add'>+			compatible = "qcom,pcie-ipq5332", "qcom,pcie-ipq9574";</div><div class='add'>+			reg = &lt;0x18000000 0xf1c&gt;,</div><div class='add'>+			      &lt;0x18000f20 0xa8&gt;,</div><div class='add'>+			      &lt;0x18001000 0x1000&gt;,</div><div class='add'>+			      &lt;0x00088000 0x3000&gt;,</div><div class='add'>+			      &lt;0x18100000 0x1000&gt;,</div><div class='add'>+			      &lt;0x0008b000 0x1000&gt;;</div><div class='add'>+			reg-names = "dbi",</div><div class='add'>+				    "elbi",</div><div class='add'>+				    "atu",</div><div class='add'>+				    "parf",</div><div class='add'>+				    "config",</div><div class='add'>+				    "mhi";</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			linux,pci-domain = &lt;1&gt;;</div><div class='add'>+			num-lanes = &lt;2&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			ranges = &lt;0x01000000 0x0 0x00000000 0x18200000 0x0 0x00100000&gt;,</div><div class='add'>+				 &lt;0x02000000 0x0 0x18300000 0x18300000 0x0 0x07d00000&gt;;</div><div class='add'>+</div><div class='add'>+			msi-map = &lt;0x0 &amp;v2m0 0x0 0xffd&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "msi0",</div><div class='add'>+					  "msi1",</div><div class='add'>+					  "msi2",</div><div class='add'>+					  "msi3",</div><div class='add'>+					  "msi4",</div><div class='add'>+					  "msi5",</div><div class='add'>+					  "msi6",</div><div class='add'>+					  "msi7",</div><div class='add'>+					  "global";</div><div class='add'>+</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0x7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;intc 0 GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;intc 0 GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;intc 0 GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;intc 0 GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_PCIE3X2_AXI_M_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3X2_AXI_S_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3X2_AXI_S_BRIDGE_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3X2_RCHG_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3X2_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3X2_AUX_CLK&gt;;</div><div class='add'>+			clock-names = "axi_m",</div><div class='add'>+				      "axi_s",</div><div class='add'>+				      "axi_bridge",</div><div class='add'>+				      "rchng",</div><div class='add'>+				      "ahb",</div><div class='add'>+				      "aux";</div><div class='add'>+</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_PCIE3X2_AUX_CLK&gt;;</div><div class='add'>+</div><div class='add'>+			assigned-clock-rates = &lt;2000000&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_PCIE3X2_PIPE_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3X2_CORE_STICKY_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3X2_AXI_S_STICKY_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3X2_AXI_S_CLK_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3X2_AXI_M_STICKY_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3X2_AXI_M_CLK_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3X2_AUX_CLK_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3X2_AHB_CLK_ARES&gt;;</div><div class='add'>+			reset-names = "pipe",</div><div class='add'>+				      "sticky",</div><div class='add'>+				      "axi_s_sticky",</div><div class='add'>+				      "axi_s",</div><div class='add'>+				      "axi_m_sticky",</div><div class='add'>+				      "axi_m",</div><div class='add'>+				      "aux",</div><div class='add'>+				      "ahb";</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;pcie1_phy&gt;;</div><div class='add'>+			phy-names = "pciephy";</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;gcc MASTER_SNOC_PCIE3_2_M &amp;gcc SLAVE_SNOC_PCIE3_2_M&gt;,</div><div class='add'>+					&lt;&amp;gcc MASTER_ANOC_PCIE3_2_S &amp;gcc SLAVE_ANOC_PCIE3_2_S&gt;;</div><div class='add'>+			interconnect-names = "pcie-mem", "cpu-pcie";</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcie@0 {</div><div class='add'>+				device_type = "pci";</div><div class='add'>+				reg = &lt;0x0 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;3&gt;;</div><div class='add'>+				#size-cells = &lt;2&gt;;</div><div class='add'>+				ranges;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie0: pcie@20000000 {</div><div class='add'>+			compatible = "qcom,pcie-ipq5332", "qcom,pcie-ipq9574";</div><div class='add'>+			reg = &lt;0x20000000 0xf1c&gt;,</div><div class='add'>+			      &lt;0x20000f20 0xa8&gt;,</div><div class='add'>+			      &lt;0x20001000 0x1000&gt;,</div><div class='add'>+			      &lt;0x00080000 0x3000&gt;,</div><div class='add'>+			      &lt;0x20100000 0x1000&gt;,</div><div class='add'>+			      &lt;0x00083000 0x1000&gt;;</div><div class='add'>+			reg-names = "dbi",</div><div class='add'>+				    "elbi",</div><div class='add'>+				    "atu",</div><div class='add'>+				    "parf",</div><div class='add'>+				    "config",</div><div class='add'>+				    "mhi";</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			linux,pci-domain = &lt;0&gt;;</div><div class='add'>+			num-lanes = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			ranges = &lt;0x01000000 0x0 0x00000000 0x20200000 0x0 0x00100000&gt;,</div><div class='add'>+				 &lt;0x02000000 0x0 0x20300000 0x20300000 0x0 0x0fd00000&gt;;</div><div class='add'>+</div><div class='add'>+			msi-map = &lt;0x0 &amp;v2m0 0x0 0xffd&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "msi0",</div><div class='add'>+					  "msi1",</div><div class='add'>+					  "msi2",</div><div class='add'>+					  "msi3",</div><div class='add'>+					  "msi4",</div><div class='add'>+					  "msi5",</div><div class='add'>+					  "msi6",</div><div class='add'>+					  "msi7",</div><div class='add'>+					  "global";</div><div class='add'>+</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0x7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;intc 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;intc 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;intc 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;intc 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_PCIE3X1_0_AXI_M_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3X1_0_AXI_S_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3X1_0_RCHG_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3X1_0_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3X1_0_AUX_CLK&gt;;</div><div class='add'>+			clock-names = "axi_m",</div><div class='add'>+				      "axi_s",</div><div class='add'>+				      "axi_bridge",</div><div class='add'>+				      "rchng",</div><div class='add'>+				      "ahb",</div><div class='add'>+				      "aux";</div><div class='add'>+</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_PCIE3X1_0_AUX_CLK&gt;;</div><div class='add'>+</div><div class='add'>+			assigned-clock-rates = &lt;2000000&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_PCIE3X1_0_PIPE_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3X1_0_CORE_STICKY_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3X1_0_AXI_S_STICKY_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3X1_0_AXI_S_CLK_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3X1_0_AXI_M_STICKY_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3X1_0_AXI_M_CLK_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3X1_0_AUX_CLK_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3X1_0_AHB_CLK_ARES&gt;;</div><div class='add'>+			reset-names = "pipe",</div><div class='add'>+				      "sticky",</div><div class='add'>+				      "axi_s_sticky",</div><div class='add'>+				      "axi_s",</div><div class='add'>+				      "axi_m_sticky",</div><div class='add'>+				      "axi_m",</div><div class='add'>+				      "aux",</div><div class='add'>+				      "ahb";</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;pcie0_phy&gt;;</div><div class='add'>+			phy-names = "pciephy";</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;gcc MASTER_SNOC_PCIE3_1_M &amp;gcc SLAVE_SNOC_PCIE3_1_M&gt;,</div><div class='add'>+					&lt;&amp;gcc MASTER_ANOC_PCIE3_1_S &amp;gcc SLAVE_ANOC_PCIE3_1_S&gt;;</div><div class='add'>+			interconnect-names = "pcie-mem", "cpu-pcie";</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcie@0 {</div><div class='add'>+				device_type = "pci";</div><div class='add'>+				reg = &lt;0x0 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;3&gt;;</div><div class='add'>+				#size-cells = &lt;2&gt;;</div><div class='add'>+				ranges;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	thermal-zones {</div><div class='add'>+		rfa-0-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 11&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				rfa-0-critical {</div><div class='add'>+					temperature = &lt;125000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rfa-1-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 12&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				rfa-1-critical {</div><div class='add'>+					temperature = &lt;125000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		misc-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 13&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				misc-critical {</div><div class='add'>+					temperature = &lt;125000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu-top-thermal {</div><div class='add'>+			polling-delay-passive = &lt;100&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 14&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu-top-critical {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu-passive {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		top-glue-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 15&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				top-glue-critical {</div><div class='add'>+					temperature = &lt;125000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts<br/>new file mode 100644<br/>index 000000000000..738618551203<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts</a></div><div class='hunk'>@@ -0,0 +1,296 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause</div><div class='add'>+/*</div><div class='add'>+ * IPQ5424 RDP466 board device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2024-2025 The Linux Foundation. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include "ipq5424.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Qualcomm Technologies, Inc. IPQ5424 RDP466";</div><div class='add'>+	compatible = "qcom,ipq5424-rdp466", "qcom,ipq5424";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;uart1;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		pinctrl-0 = &lt;&amp;gpio_keys_default&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		button-wps {</div><div class='add'>+			label = "wps";</div><div class='add'>+			linux,code = &lt;KEY_WPS_BUTTON&gt;;</div><div class='add'>+			gpios = &lt;&amp;tlmm 19 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			debounce-interval = &lt;60&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-0 = &lt;&amp;gpio_leds_default&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_WLAN;</div><div class='add'>+			gpios = &lt;&amp;tlmm 42 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "phy0tx";</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vreg_misc_3p3: regulator-usb-3p3 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-name = "usb_hs_vdda_3p3";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vreg_misc_1p8: regulator-usb-1p8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-name = "vdda_1p8_usb";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vreg_misc_0p925: regulator-usb-0p925 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-min-microvolt = &lt;925000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;925000&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-name = "vdd_core_usb";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dwc_0 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;dwc_1 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie2 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pcie2_default_state&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	perst-gpios = &lt;&amp;tlmm 31 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie2_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie3 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pcie3_default_state&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	perst-gpios = &lt;&amp;tlmm 34 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie3_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qusb_phy_0 {</div><div class='add'>+	vdd-supply = &lt;&amp;vreg_misc_0p925&gt;;</div><div class='add'>+	vdda-pll-supply = &lt;&amp;vreg_misc_1p8&gt;;</div><div class='add'>+	vdda-phy-dpdm-supply = &lt;&amp;vreg_misc_3p3&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qusb_phy_1 {</div><div class='add'>+	vdd-supply = &lt;&amp;vreg_misc_0p925&gt;;</div><div class='add'>+	vdda-pll-supply = &lt;&amp;vreg_misc_1p8&gt;;</div><div class='add'>+	vdda-phy-dpdm-supply = &lt;&amp;vreg_misc_3p3&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sdhc {</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdc_default_state&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sleep_clk {</div><div class='add'>+	clock-frequency = &lt;32000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi0 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;spi0_default_state&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash@0 {</div><div class='add'>+		compatible = "micron,n25q128a11", "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		spi-max-frequency = &lt;50000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ssphy_0 {</div><div class='add'>+	vdda-pll-supply = &lt;&amp;vreg_misc_1p8&gt;;</div><div class='add'>+	vdda-phy-supply = &lt;&amp;vreg_misc_0p925&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tlmm {</div><div class='add'>+	gpio_keys_default: gpio-keys-default-state {</div><div class='add'>+		pins = "gpio19";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;8&gt;;</div><div class='add'>+		bias-pull-up;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio_leds_default: gpio-leds-default-state {</div><div class='add'>+		pins = "gpio42";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;8&gt;;</div><div class='add'>+		bias-pull-down;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi0_default_state: spi0-default-state {</div><div class='add'>+		clk-pins {</div><div class='add'>+			pins = "gpio6";</div><div class='add'>+			function = "spi0_clk";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-down;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cs-pins {</div><div class='add'>+			pins = "gpio7";</div><div class='add'>+			function = "spi0_cs";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		miso-pins {</div><div class='add'>+			pins = "gpio8";</div><div class='add'>+			function = "spi0_miso";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-down;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mosi-pins {</div><div class='add'>+			pins = "gpio9";</div><div class='add'>+			function = "spi0_mosi";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-down;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdc_default_state: sdc-default-state {</div><div class='add'>+		clk-pins {</div><div class='add'>+			pins = "gpio5";</div><div class='add'>+			function = "sdc_clk";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmd-pins {</div><div class='add'>+			pins = "gpio4";</div><div class='add'>+			function = "sdc_cmd";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		data-pins {</div><div class='add'>+			pins = "gpio0", "gpio1", "gpio2", "gpio3";</div><div class='add'>+			function = "sdc_data";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	uart0_pins: uart0-default-state {</div><div class='add'>+		pins = "gpio10", "gpio11", "gpio12", "gpio13";</div><div class='add'>+		function = "uart0";</div><div class='add'>+		drive-strength = &lt;8&gt;;</div><div class='add'>+		bias-pull-down;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie2_default_state: pcie2-default-state {</div><div class='add'>+		pins = "gpio31";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;8&gt;;</div><div class='add'>+		bias-pull-up;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie3_default_state: pcie3-default-state {</div><div class='add'>+		pins = "gpio34";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;8&gt;;</div><div class='add'>+		bias-pull-up;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart0 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart0_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	/*</div><div class='add'>+	 * The required initialization for this SE is not handled by the</div><div class='add'>+	 * bootloader. Therefore, keep the device in "reserved" state until</div><div class='add'>+	 * linux gains support for configuring the SE.</div><div class='add'>+	 */</div><div class='add'>+	status = "reserved";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart1_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * The bootstrap pins for the board select the XO clock frequency that</div><div class='add'>+ * supports 48 MHZ, 96 MHZ or 192 MHZ. This setting automatically</div><div class='add'>+ * enables the right dividers, to ensure the reference clock output</div><div class='add'>+ * from WiFi to the CMN PLL is 48 MHZ.</div><div class='add'>+ */</div><div class='add'>+&amp;ref_48mhz_clk {</div><div class='add'>+	clock-div = &lt;1&gt;;</div><div class='add'>+	clock-mult = &lt;1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * The frequency of xo_board is fixed to 24 MHZ, which is routed</div><div class='add'>+ * from WiFi output clock 48 MHZ divided by 2.</div><div class='add'>+ */</div><div class='add'>+&amp;xo_board {</div><div class='add'>+	clock-div = &lt;2&gt;;</div><div class='add'>+	clock-mult = &lt;1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xo_clk {</div><div class='add'>+	clock-frequency = &lt;48000000&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi<br/>new file mode 100644<br/>index 000000000000..eb393f3fd728<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/ipq5424.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/ipq5424.dtsi</a></div><div class='hunk'>@@ -0,0 +1,1429 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)</div><div class='add'>+/*</div><div class='add'>+ * IPQ5424 device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,apss-ipq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,ipq5424-cmn-pll.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,ipq5424-gcc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/reset/qcom,ipq5424-gcc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interconnect/qcom,ipq5424.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/thermal/thermal.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+	interrupt-parent = &lt;&amp;intc&gt;;</div><div class='add'>+</div><div class='add'>+	clocks {</div><div class='add'>+		ref_48mhz_clk: ref-48mhz-clk {</div><div class='add'>+			compatible = "fixed-factor-clock";</div><div class='add'>+			clocks = &lt;&amp;xo_clk&gt;;</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sleep_clk: sleep-clk {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		xo_board: xo-board-clk {</div><div class='add'>+			compatible = "fixed-factor-clock";</div><div class='add'>+			clocks = &lt;&amp;ref_48mhz_clk&gt;;</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		xo_clk: xo-clk {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus: cpus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			clocks = &lt;&amp;apss_clk APSS_SILVER_CORE_CLK&gt;;</div><div class='add'>+			clock-names = "cpu";</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+			interconnects = &lt;&amp;apss_clk MASTER_CPU &amp;apss_clk SLAVE_L3&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			l2_0: l2-cache {</div><div class='add'>+				compatible = "cache";</div><div class='add'>+				cache-level = &lt;2&gt;;</div><div class='add'>+				cache-unified;</div><div class='add'>+				next-level-cache = &lt;&amp;l3_0&gt;;</div><div class='add'>+</div><div class='add'>+				l3_0: l3-cache {</div><div class='add'>+					compatible = "cache";</div><div class='add'>+					cache-level = &lt;3&gt;;</div><div class='add'>+					cache-unified;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@100 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			reg = &lt;0x100&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_100&gt;;</div><div class='add'>+			clocks = &lt;&amp;apss_clk APSS_SILVER_CORE_CLK&gt;;</div><div class='add'>+			clock-names = "cpu";</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+			interconnects = &lt;&amp;apss_clk MASTER_CPU &amp;apss_clk SLAVE_L3&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			l2_100: l2-cache {</div><div class='add'>+				compatible = "cache";</div><div class='add'>+				cache-level = &lt;2&gt;;</div><div class='add'>+				cache-unified;</div><div class='add'>+				next-level-cache = &lt;&amp;l3_0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@200 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			reg = &lt;0x200&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_200&gt;;</div><div class='add'>+			clocks = &lt;&amp;apss_clk APSS_SILVER_CORE_CLK&gt;;</div><div class='add'>+			clock-names = "cpu";</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+			interconnects = &lt;&amp;apss_clk MASTER_CPU &amp;apss_clk SLAVE_L3&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			l2_200: l2-cache {</div><div class='add'>+				compatible = "cache";</div><div class='add'>+				cache-level = &lt;2&gt;;</div><div class='add'>+				cache-unified;</div><div class='add'>+				next-level-cache = &lt;&amp;l3_0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@300 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			reg = &lt;0x300&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_300&gt;;</div><div class='add'>+			clocks = &lt;&amp;apss_clk APSS_SILVER_CORE_CLK&gt;;</div><div class='add'>+			clock-names = "cpu";</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+			interconnects = &lt;&amp;apss_clk MASTER_CPU &amp;apss_clk SLAVE_L3&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			l2_300: l2-cache {</div><div class='add'>+				compatible = "cache";</div><div class='add'>+				cache-level = &lt;2&gt;;</div><div class='add'>+				cache-unified;</div><div class='add'>+				next-level-cache = &lt;&amp;l3_0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	firmware {</div><div class='add'>+		scm {</div><div class='add'>+			compatible = "qcom,scm-ipq5424", "qcom,scm";</div><div class='add'>+			qcom,dload-mode = &lt;&amp;tcsr 0x25100&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpu_opp_table: opp-table-cpu {</div><div class='add'>+		compatible = "operating-points-v2-kryo-cpu";</div><div class='add'>+		opp-shared;</div><div class='add'>+		nvmem-cells = &lt;&amp;cpu_speed_bin&gt;;</div><div class='add'>+</div><div class='add'>+		opp-816000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;816000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;850000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x3&gt;;</div><div class='add'>+			clock-latency-ns = &lt;200000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;816000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1416000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1416000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;850000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x3&gt;;</div><div class='add'>+			clock-latency-ns = &lt;200000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;984000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1800000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1800000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1000000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x1&gt;;</div><div class='add'>+			clock-latency-ns = &lt;200000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;1272000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@80000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		/* We expect the bootloader to fill in the size */</div><div class='add'>+		reg = &lt;0x0 0x80000000 0x0 0x0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu-a55 {</div><div class='add'>+		compatible = "arm,cortex-a55-pmu";</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu-dsu {</div><div class='add'>+		compatible = "arm,dsu-pmu";</div><div class='add'>+		interrupts = &lt;GIC_SPI 50 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+		cpus = &lt;&amp;cpu0&gt;, &lt;&amp;cpu1&gt;, &lt;&amp;cpu2&gt;, &lt;&amp;cpu3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-1.0";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		bootloader@8a200000 {</div><div class='add'>+			reg = &lt;0x0 0x8a200000 0x0 0x400000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tz@8a600000 {</div><div class='add'>+			reg = &lt;0x0 0x8a600000 0x0 0x200000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smem@8a800000 {</div><div class='add'>+			compatible = "qcom,smem";</div><div class='add'>+			reg = &lt;0x0 0x8a800000 0x0 0x32000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+</div><div class='add'>+			hwlocks = &lt;&amp;tcsr_mutex 3&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tfa@8a832000 {</div><div class='add'>+			reg = &lt;0x0 0x8a832000 0x0 0x80000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc@0 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges = &lt;0 0 0 0 0x10 0&gt;;</div><div class='add'>+</div><div class='add'>+		pcie0_phy: phy@84000 {</div><div class='add'>+			compatible = "qcom,ipq5424-qmp-gen3x1-pcie-phy",</div><div class='add'>+				     "qcom,ipq9574-qmp-gen3x1-pcie-phy";</div><div class='add'>+			reg = &lt;0x0 0x00084000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_PCIE0_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_PIPE_CLK&gt;;</div><div class='add'>+			clock-names = "aux",</div><div class='add'>+				      "cfg_ahb",</div><div class='add'>+				      "pipe";</div><div class='add'>+</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_PCIE0_AUX_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;20000000&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_PCIE0_PHY_BCR&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0PHY_PHY_BCR&gt;;</div><div class='add'>+			reset-names = "phy",</div><div class='add'>+				      "common";</div><div class='add'>+</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-output-names = "gcc_pcie0_pipe_clk_src";</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie1_phy: phy@8c000 {</div><div class='add'>+			compatible = "qcom,ipq5424-qmp-gen3x1-pcie-phy",</div><div class='add'>+				     "qcom,ipq9574-qmp-gen3x1-pcie-phy";</div><div class='add'>+			reg = &lt;0x0 0x0008c000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_PCIE1_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_PIPE_CLK&gt;;</div><div class='add'>+			clock-names = "aux",</div><div class='add'>+				      "cfg_ahb",</div><div class='add'>+				      "pipe";</div><div class='add'>+</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_PCIE1_AUX_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;20000000&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_PCIE1_PHY_BCR&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1PHY_PHY_BCR&gt;;</div><div class='add'>+			reset-names = "phy",</div><div class='add'>+				      "common";</div><div class='add'>+</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-output-names = "gcc_pcie1_pipe_clk_src";</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmn_pll: clock-controller@9b000 {</div><div class='add'>+			compatible = "qcom,ipq5424-cmn-pll";</div><div class='add'>+			reg = &lt;0 0x0009b000 0 0x800&gt;;</div><div class='add'>+			clocks = &lt;&amp;ref_48mhz_clk&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_CMN_12GPLL_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_CMN_12GPLL_SYS_CLK&gt;;</div><div class='add'>+			clock-names = "ref", "ahb", "sys";</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			assigned-clocks = &lt;&amp;cmn_pll IPQ5424_CMN_PLL_CLK&gt;;</div><div class='add'>+			assigned-clock-rates-u64 = /bits/ 64 &lt;12000000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		efuse@a4000 {</div><div class='add'>+			compatible = "qcom,ipq5424-qfprom", "qcom,qfprom";</div><div class='add'>+			reg = &lt;0 0x000a4000 0 0x741&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			tsens_sens9_off: s9@3dc {</div><div class='add'>+				reg = &lt;0x3dc 0x1&gt;;</div><div class='add'>+				bits = &lt;4 4&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tsens_sens10_off: s10@3dd {</div><div class='add'>+				reg = &lt;0x3dd 0x1&gt;;</div><div class='add'>+				bits = &lt;0 4&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tsens_sens11_off: s11@3dd {</div><div class='add'>+				reg = &lt;0x3dd 0x1&gt;;</div><div class='add'>+				bits = &lt;4 4&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tsens_sens12_off: s12@3de {</div><div class='add'>+				reg = &lt;0x3de 0x1&gt;;</div><div class='add'>+				bits = &lt;0 4&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tsens_sens13_off: s13@3de {</div><div class='add'>+				reg = &lt;0x3de 0x1&gt;;</div><div class='add'>+				bits = &lt;4 4&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tsens_sens14_off: s14@3e5 {</div><div class='add'>+				reg = &lt;0x3e5 0x2&gt;;</div><div class='add'>+				bits = &lt;7 4&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tsens_sens15_off: s15@3e6 {</div><div class='add'>+				reg = &lt;0x3e6 0x1&gt;;</div><div class='add'>+				bits = &lt;3 4&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tsens_mode: mode@419 {</div><div class='add'>+				reg = &lt;0x419 0x1&gt;;</div><div class='add'>+				bits = &lt;0 3&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tsens_base0: base0@419 {</div><div class='add'>+				reg = &lt;0x419 0x2&gt;;</div><div class='add'>+				bits = &lt;3 10&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			tsens_base1: base1@41a {</div><div class='add'>+				reg = &lt;0x41a 0x2&gt;;</div><div class='add'>+				bits = &lt;5 10&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie2_phy: phy@f4000 {</div><div class='add'>+			compatible = "qcom,ipq5424-qmp-gen3x2-pcie-phy",</div><div class='add'>+				     "qcom,ipq9574-qmp-gen3x2-pcie-phy";</div><div class='add'>+			reg = &lt;0x0 0x000f4000 0x0 0x2000&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_PCIE2_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE2_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE2_PIPE_CLK&gt;;</div><div class='add'>+			clock-names = "aux",</div><div class='add'>+				      "cfg_ahb",</div><div class='add'>+				      "pipe";</div><div class='add'>+</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_PCIE2_AUX_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;20000000&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_PCIE2_PHY_BCR&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE2PHY_PHY_BCR&gt;;</div><div class='add'>+			reset-names = "phy",</div><div class='add'>+				      "common";</div><div class='add'>+</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-output-names = "gcc_pcie2_pipe_clk_src";</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie3_phy: phy@fc000 {</div><div class='add'>+			compatible = "qcom,ipq5424-qmp-gen3x2-pcie-phy",</div><div class='add'>+				     "qcom,ipq9574-qmp-gen3x2-pcie-phy";</div><div class='add'>+			reg = &lt;0x0 0x000fc000 0x0 0x2000&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_PCIE3_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3_PIPE_CLK&gt;;</div><div class='add'>+			clock-names = "aux",</div><div class='add'>+				      "cfg_ahb",</div><div class='add'>+				      "pipe";</div><div class='add'>+</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_PCIE3_AUX_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;20000000&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_PCIE3_PHY_BCR&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3PHY_PHY_BCR&gt;;</div><div class='add'>+			reset-names = "phy",</div><div class='add'>+				      "common";</div><div class='add'>+</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-output-names = "gcc_pcie3_pipe_clk_src";</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tsens: thermal-sensor@4a9000 {</div><div class='add'>+			compatible = "qcom,ipq5424-tsens";</div><div class='add'>+			reg = &lt;0 0x004a9000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x004a8000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 105 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			interrupt-names = "combined";</div><div class='add'>+			nvmem-cells = &lt;&amp;tsens_mode&gt;,</div><div class='add'>+				      &lt;&amp;tsens_base0&gt;,</div><div class='add'>+				      &lt;&amp;tsens_base1&gt;,</div><div class='add'>+				      &lt;&amp;tsens_sens9_off&gt;,</div><div class='add'>+				      &lt;&amp;tsens_sens10_off&gt;,</div><div class='add'>+				      &lt;&amp;tsens_sens11_off&gt;,</div><div class='add'>+				      &lt;&amp;tsens_sens12_off&gt;,</div><div class='add'>+				      &lt;&amp;tsens_sens13_off&gt;,</div><div class='add'>+				      &lt;&amp;tsens_sens14_off&gt;,</div><div class='add'>+				      &lt;&amp;tsens_sens15_off&gt;;</div><div class='add'>+			nvmem-cell-names = "mode",</div><div class='add'>+					   "base0",</div><div class='add'>+					   "base1",</div><div class='add'>+					   "tsens_sens9_off",</div><div class='add'>+					   "tsens_sens10_off",</div><div class='add'>+					   "tsens_sens11_off",</div><div class='add'>+					   "tsens_sens12_off",</div><div class='add'>+					   "tsens_sens13_off",</div><div class='add'>+					   "tsens_sens14_off",</div><div class='add'>+					   "tsens_sens15_off";</div><div class='add'>+			#qcom,sensors = &lt;7&gt;;</div><div class='add'>+			#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rng: rng@4c3000 {</div><div class='add'>+			compatible = "qcom,ipq5424-trng", "qcom,trng";</div><div class='add'>+			reg = &lt;0 0x004c3000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_PRNG_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "core";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		system-cache-controller@800000 {</div><div class='add'>+			compatible = "qcom,ipq5424-llcc";</div><div class='add'>+			reg = &lt;0 0x00800000 0 0x200000&gt;;</div><div class='add'>+			reg-names = "llcc0_base";</div><div class='add'>+			interrupts = &lt;GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qfprom@a6000 {</div><div class='add'>+			compatible = "qcom,ipq5424-qfprom", "qcom,qfprom";</div><div class='add'>+			reg = &lt;0x0 0x000a6000 0x0 0x1000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			cpu_speed_bin: cpu-speed-bin@234 {</div><div class='add'>+				reg = &lt;0x234 0x1&gt;;</div><div class='add'>+				bits = &lt;0 8&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tlmm: pinctrl@1000000 {</div><div class='add'>+			compatible = "qcom,ipq5424-tlmm";</div><div class='add'>+			reg = &lt;0 0x01000000 0 0x300000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;tlmm 0 0 50&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			uart1_pins: uart1-state {</div><div class='add'>+				pins = "gpio43", "gpio44";</div><div class='add'>+				function = "uart1";</div><div class='add'>+				drive-strength = &lt;8&gt;;</div><div class='add'>+				bias-pull-up;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gcc: clock-controller@1800000 {</div><div class='add'>+			compatible = "qcom,ipq5424-gcc";</div><div class='add'>+			reg = &lt;0 0x01800000 0 0x40000&gt;;</div><div class='add'>+			clocks = &lt;&amp;xo_board&gt;,</div><div class='add'>+				 &lt;&amp;sleep_clk&gt;,</div><div class='add'>+				 &lt;&amp;pcie0_phy&gt;,</div><div class='add'>+				 &lt;&amp;pcie1_phy&gt;,</div><div class='add'>+				 &lt;&amp;pcie2_phy&gt;,</div><div class='add'>+				 &lt;&amp;pcie3_phy&gt;,</div><div class='add'>+				 &lt;0&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+			#interconnect-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tcsr_mutex: hwlock@1905000 {</div><div class='add'>+			compatible = "qcom,tcsr-mutex";</div><div class='add'>+			reg = &lt;0 0x01905000 0 0x20000&gt;;</div><div class='add'>+			#hwlock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tcsr: syscon@1937000 {</div><div class='add'>+			compatible = "qcom,tcsr-ipq5424", "syscon";</div><div class='add'>+			reg = &lt;0 0x01937000 0 0x2a000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qupv3: geniqup@1ac0000 {</div><div class='add'>+			compatible = "qcom,geni-se-qup";</div><div class='add'>+			reg = &lt;0 0x01ac0000 0 0x2000&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_QUPV3_AHB_MST_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_QUPV3_AHB_SLV_CLK&gt;;</div><div class='add'>+			clock-names = "m-ahb", "s-ahb";</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			uart0: serial@1a80000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0 0x01a80000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_UART0_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				interrupts = &lt;GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart1: serial@1a84000 {</div><div class='add'>+				compatible = "qcom,geni-debug-uart";</div><div class='add'>+				reg = &lt;0 0x01a84000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_UART1_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				interrupts = &lt;GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi0: spi@1a90000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0 0x01a90000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_SPI0_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				interrupts = &lt;GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi1: spi@1a94000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0 0x01a94000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_SPI1_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				interrupts = &lt;GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sdhc: mmc@7804000 {</div><div class='add'>+			compatible = "qcom,ipq5424-sdhci", "qcom,sdhci-msm-v5";</div><div class='add'>+			reg = &lt;0 0x07804000 0 0x1000&gt;, &lt;0 0x07805000 0 0x1000&gt;;</div><div class='add'>+			reg-names = "hc", "cqhci";</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "hc_irq", "pwr_irq";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_SDCC1_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_SDCC1_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;xo_board&gt;;</div><div class='add'>+			clock-names = "iface", "core", "xo";</div><div class='add'>+</div><div class='add'>+			supports-cqe;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		intc: interrupt-controller@f200000 {</div><div class='add'>+			compatible = "arm,gic-v3";</div><div class='add'>+			reg = &lt;0 0xf200000 0 0x10000&gt;, /* GICD */</div><div class='add'>+			      &lt;0 0xf240000 0 0x80000&gt;; /* GICR * 4 regions */</div><div class='add'>+			#address-cells = &lt;0&gt;;</div><div class='add'>+			#interrupt-cells = &lt;0x3&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#redistributor-regions = &lt;1&gt;;</div><div class='add'>+			redistributor-stride = &lt;0x0 0x20000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			mbi-ranges = &lt;672 128&gt;;</div><div class='add'>+			msi-controller;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		watchdog@f410000 {</div><div class='add'>+			compatible = "qcom,apss-wdt-ipq5424", "qcom,kpss-wdt";</div><div class='add'>+			reg = &lt;0 0x0f410000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 0 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			clocks = &lt;&amp;sleep_clk&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qusb_phy_1: phy@71000 {</div><div class='add'>+			compatible = "qcom,ipq5424-qusb2-phy";</div><div class='add'>+			reg = &lt;0 0x00071000 0 0x180&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_USB1_PHY_CFG_AHB_CLK&gt;,</div><div class='add'>+				&lt;&amp;xo_board&gt;;</div><div class='add'>+			clock-names = "cfg_ahb", "ref";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_QUSB2_1_PHY_BCR&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb2: usb2@1e00000 {</div><div class='add'>+			compatible = "qcom,ipq5424-dwc3", "qcom,dwc3";</div><div class='add'>+			reg = &lt;0 0x01ef8800 0 0x400&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_USB1_MASTER_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB1_SLEEP_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB1_MOCK_UTMI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB1_PHY_CFG_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_CNOC_USB_CLK&gt;;</div><div class='add'>+</div><div class='add'>+			clock-names = "core",</div><div class='add'>+				      "sleep",</div><div class='add'>+				      "mock_utmi",</div><div class='add'>+				      "iface",</div><div class='add'>+				      "cfg_noc";</div><div class='add'>+</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_USB1_MASTER_CLK&gt;,</div><div class='add'>+					  &lt;&amp;gcc GCC_USB1_MOCK_UTMI_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;200000000&gt;,</div><div class='add'>+					       &lt;24000000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts-extended = &lt;&amp;intc GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;intc GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;intc GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;intc GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "pwr_event",</div><div class='add'>+					  "qusb2_phy",</div><div class='add'>+					  "dm_hs_phy_irq",</div><div class='add'>+					  "dp_hs_phy_irq";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_USB1_BCR&gt;;</div><div class='add'>+			qcom,select-utmi-as-pipe-clk;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			dwc_1: usb@1e00000 {</div><div class='add'>+				compatible = "snps,dwc3";</div><div class='add'>+				reg = &lt;0 0x01e00000 0 0xe000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_USB1_MOCK_UTMI_CLK&gt;;</div><div class='add'>+				clock-names = "ref";</div><div class='add'>+				interrupts = &lt;GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				phys = &lt;&amp;qusb_phy_1&gt;;</div><div class='add'>+				phy-names = "usb2-phy";</div><div class='add'>+				tx-fifo-resize;</div><div class='add'>+				snps,is-utmi-l1-suspend;</div><div class='add'>+				snps,hird-threshold = /bits/ 8 &lt;0x0&gt;;</div><div class='add'>+				snps,dis_u2_susphy_quirk;</div><div class='add'>+				snps,dis_u3_susphy_quirk;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qusb_phy_0: phy@7b000 {</div><div class='add'>+			compatible = "qcom,ipq5424-qusb2-phy";</div><div class='add'>+			reg = &lt;0 0x0007b000 0 0x180&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_USB0_PHY_CFG_AHB_CLK&gt;,</div><div class='add'>+				&lt;&amp;xo_board&gt;;</div><div class='add'>+			clock-names = "cfg_ahb", "ref";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_QUSB2_0_PHY_BCR&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ssphy_0: phy@7d000 {</div><div class='add'>+			compatible = "qcom,ipq5424-qmp-usb3-phy";</div><div class='add'>+			reg = &lt;0 0x0007d000 0 0xa00&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_USB0_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;xo_board&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB0_PHY_CFG_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB0_PIPE_CLK&gt;;</div><div class='add'>+			clock-names = "aux",</div><div class='add'>+				      "ref",</div><div class='add'>+				      "cfg_ahb",</div><div class='add'>+				      "pipe";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_USB0_PHY_BCR&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB3PHY_0_PHY_BCR&gt;;</div><div class='add'>+			reset-names = "phy",</div><div class='add'>+				      "phy_phy";</div><div class='add'>+</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-output-names = "usb0_pipe_clk";</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb3: usb3@8a00000 {</div><div class='add'>+			compatible = "qcom,ipq5424-dwc3", "qcom,dwc3";</div><div class='add'>+			reg = &lt;0 0x08af8800 0 0x400&gt;;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_USB0_MASTER_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB0_SLEEP_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB0_MOCK_UTMI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB0_PHY_CFG_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_CNOC_USB_CLK&gt;;</div><div class='add'>+</div><div class='add'>+			clock-names = "core",</div><div class='add'>+				      "sleep",</div><div class='add'>+				      "mock_utmi",</div><div class='add'>+				      "iface",</div><div class='add'>+				      "cfg_noc";</div><div class='add'>+</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_USB0_MASTER_CLK&gt;,</div><div class='add'>+					  &lt;&amp;gcc GCC_USB0_MOCK_UTMI_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;200000000&gt;,</div><div class='add'>+					       &lt;24000000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts-extended = &lt;&amp;intc GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;intc GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;intc GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;intc GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "pwr_event",</div><div class='add'>+					  "qusb2_phy",</div><div class='add'>+					  "dm_hs_phy_irq",</div><div class='add'>+					  "dp_hs_phy_irq";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_USB_BCR&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			dwc_0: usb@8a00000 {</div><div class='add'>+				compatible = "snps,dwc3";</div><div class='add'>+				reg = &lt;0 0x08a00000 0 0xcd00&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_USB0_MOCK_UTMI_CLK&gt;;</div><div class='add'>+				clock-names = "ref";</div><div class='add'>+				interrupts = &lt;GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				phys = &lt;&amp;qusb_phy_0&gt;, &lt;&amp;ssphy_0&gt;;</div><div class='add'>+				phy-names = "usb2-phy", "usb3-phy";</div><div class='add'>+				tx-fifo-resize;</div><div class='add'>+				snps,is-utmi-l1-suspend;</div><div class='add'>+				snps,hird-threshold = /bits/ 8 &lt;0x0&gt;;</div><div class='add'>+				snps,dis_u2_susphy_quirk;</div><div class='add'>+				snps,dis_u3_susphy_quirk;</div><div class='add'>+				snps,dis-u1-entry-quirk;</div><div class='add'>+				snps,dis-u2-entry-quirk;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		timer@f420000 {</div><div class='add'>+			compatible = "arm,armv7-timer-mem";</div><div class='add'>+			reg = &lt;0 0xf420000 0 0x1000&gt;;</div><div class='add'>+			ranges = &lt;0 0 0 0x10000000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			frame@f421000 {</div><div class='add'>+				reg = &lt;0xf421000 0x1000&gt;,</div><div class='add'>+				      &lt;0xf422000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				frame-number = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@f423000 {</div><div class='add'>+				reg = &lt;0xf423000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				frame-number = &lt;1&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@f425000 {</div><div class='add'>+				reg = &lt;0xf425000 0x1000&gt;,</div><div class='add'>+				      &lt;0xf426000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				frame-number = &lt;2&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@f427000 {</div><div class='add'>+				reg = &lt;0xf427000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				frame-number = &lt;3&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@f429000 {</div><div class='add'>+				reg = &lt;0xf429000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				frame-number = &lt;4&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@f42b000 {</div><div class='add'>+				reg = &lt;0xf42b000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				frame-number = &lt;5&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@f42d000 {</div><div class='add'>+				reg = &lt;0xf42d000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				frame-number = &lt;6&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		apss_clk: clock-controller@fa80000 {</div><div class='add'>+			compatible = "qcom,ipq5424-apss-clk";</div><div class='add'>+			reg = &lt;0x0 0x0fa80000 0x0 0x20000&gt;;</div><div class='add'>+			clocks = &lt;&amp;xo_board&gt;,</div><div class='add'>+				 &lt;&amp;gcc GPLL0&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#interconnect-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		clock-controller@39b00000 {</div><div class='add'>+			compatible = "qcom,ipq5424-nsscc";</div><div class='add'>+			reg = &lt;0 0x39b00000 0 0x100000&gt;;</div><div class='add'>+			clocks = &lt;&amp;cmn_pll IPQ5424_XO_24MHZ_CLK&gt;,</div><div class='add'>+				 &lt;&amp;cmn_pll IPQ5424_NSS_300MHZ_CLK&gt;,</div><div class='add'>+				 &lt;&amp;cmn_pll IPQ5424_PPE_375MHZ_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GPLL0_OUT_AUX&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_NSSCC_CLK&gt;;</div><div class='add'>+			clock-names = "xo",</div><div class='add'>+				      "nss",</div><div class='add'>+				      "ppe",</div><div class='add'>+				      "gpll0_out",</div><div class='add'>+				      "uniphy0_rx",</div><div class='add'>+				      "uniphy0_tx",</div><div class='add'>+				      "uniphy1_rx",</div><div class='add'>+				      "uniphy1_tx",</div><div class='add'>+				      "uniphy2_rx",</div><div class='add'>+				      "uniphy2_tx",</div><div class='add'>+				      "bus";</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+			#interconnect-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie3: pcie@40000000 {</div><div class='add'>+			compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574";</div><div class='add'>+			reg = &lt;0x0 0x40000000 0x0 0xf1c&gt;,</div><div class='add'>+			      &lt;0x0 0x40000f20 0x0 0xa8&gt;,</div><div class='add'>+			      &lt;0x0 0x40001000 0x0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0x000f8000 0x0 0x3000&gt;,</div><div class='add'>+			      &lt;0x0 0x40100000 0x0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0x000fe000 0x0 0x1000&gt;;</div><div class='add'>+			reg-names = "dbi",</div><div class='add'>+				    "elbi",</div><div class='add'>+				    "atu",</div><div class='add'>+				    "parf",</div><div class='add'>+				    "config",</div><div class='add'>+				    "mhi";</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			linux,pci-domain = &lt;3&gt;;</div><div class='add'>+			num-lanes = &lt;2&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			ranges = &lt;0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x00100000&gt;,</div><div class='add'>+				 &lt;0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x0fd00000&gt;;</div><div class='add'>+</div><div class='add'>+			msi-map = &lt;0x0 &amp;intc 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			interrupt-names = "msi0",</div><div class='add'>+					  "msi1",</div><div class='add'>+					  "msi2",</div><div class='add'>+					  "msi3",</div><div class='add'>+					  "msi4",</div><div class='add'>+					  "msi5",</div><div class='add'>+					  "msi6",</div><div class='add'>+					  "msi7",</div><div class='add'>+					  "global";</div><div class='add'>+</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0x0 0x0 0x0 0x7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;intc GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;intc GIC_SPI 480 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;intc GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;intc GIC_SPI 482 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_PCIE3_AXI_M_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3_AXI_S_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3_AXI_S_BRIDGE_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3_RCHNG_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3_AUX_CLK&gt;;</div><div class='add'>+			clock-names = "axi_m",</div><div class='add'>+				      "axi_s",</div><div class='add'>+				      "axi_bridge",</div><div class='add'>+				      "rchng",</div><div class='add'>+				      "ahb",</div><div class='add'>+				      "aux";</div><div class='add'>+</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_PCIE3_RCHNG_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;100000000&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_PCIE3_PIPE_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3_CORE_STICKY_RESET&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3_AXI_S_STICKY_RESET&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3_AXI_S_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3_AXI_M_STICKY_RESET&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3_AXI_M_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3_AUX_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3_AHB_ARES&gt;;</div><div class='add'>+			reset-names = "pipe",</div><div class='add'>+				      "sticky",</div><div class='add'>+				      "axi_s_sticky",</div><div class='add'>+				      "axi_s",</div><div class='add'>+				      "axi_m_sticky",</div><div class='add'>+				      "axi_m",</div><div class='add'>+				      "aux",</div><div class='add'>+				      "ahb";</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;pcie3_phy&gt;;</div><div class='add'>+			phy-names = "pciephy";</div><div class='add'>+			interconnects = &lt;&amp;gcc MASTER_ANOC_PCIE3 &amp;gcc SLAVE_ANOC_PCIE3&gt;,</div><div class='add'>+					&lt;&amp;gcc MASTER_CNOC_PCIE3 &amp;gcc SLAVE_CNOC_PCIE3&gt;;</div><div class='add'>+			interconnect-names = "pcie-mem", "cpu-pcie";</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcie@0 {</div><div class='add'>+				device_type = "pci";</div><div class='add'>+				reg = &lt;0x0 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+				bus-range = &lt;0x01 0xff&gt;;</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;3&gt;;</div><div class='add'>+				#size-cells = &lt;2&gt;;</div><div class='add'>+				ranges;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie2: pcie@50000000 {</div><div class='add'>+			compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574";</div><div class='add'>+			reg = &lt;0x0 0x50000000 0x0 0xf1c&gt;,</div><div class='add'>+			      &lt;0x0 0x50000f20 0x0 0xa8&gt;,</div><div class='add'>+			      &lt;0x0 0x50001000 0x0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0x000f0000 0x0 0x3000&gt;,</div><div class='add'>+			      &lt;0x0 0x50100000 0x0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0x000f6000 0x0 0x1000&gt;;</div><div class='add'>+			reg-names = "dbi",</div><div class='add'>+				    "elbi",</div><div class='add'>+				    "atu",</div><div class='add'>+				    "parf",</div><div class='add'>+				    "config",</div><div class='add'>+				    "mhi";</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			linux,pci-domain = &lt;2&gt;;</div><div class='add'>+			num-lanes = &lt;2&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			ranges = &lt;0x01000000 0x0 0x00000000 0x0 0x50200000 0x0 0x00100000&gt;,</div><div class='add'>+				 &lt;0x02000000 0x0 0x50300000 0x0 0x50300000 0x0 0x0fd00000&gt;;</div><div class='add'>+</div><div class='add'>+			msi-map = &lt;0x0 &amp;intc 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "msi0",</div><div class='add'>+					  "msi1",</div><div class='add'>+					  "msi2",</div><div class='add'>+					  "msi3",</div><div class='add'>+					  "msi4",</div><div class='add'>+					  "msi5",</div><div class='add'>+					  "msi6",</div><div class='add'>+					  "msi7",</div><div class='add'>+					  "global";</div><div class='add'>+</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0x0 0x0 0x0 0x7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;intc GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;intc GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;intc GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;intc GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_PCIE2_AXI_M_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE2_AXI_S_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE2_AXI_S_BRIDGE_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE2_RCHNG_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE2_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE2_AUX_CLK&gt;;</div><div class='add'>+			clock-names = "axi_m",</div><div class='add'>+				      "axi_s",</div><div class='add'>+				      "axi_bridge",</div><div class='add'>+				      "rchng",</div><div class='add'>+				      "ahb",</div><div class='add'>+				      "aux";</div><div class='add'>+</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_PCIE2_RCHNG_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;100000000&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_PCIE2_PIPE_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE2_CORE_STICKY_RESET&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE2_AXI_S_STICKY_RESET&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE2_AXI_S_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE2_AXI_M_STICKY_RESET&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE2_AXI_M_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE2_AUX_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE2_AHB_ARES&gt;;</div><div class='add'>+			reset-names = "pipe",</div><div class='add'>+				      "sticky",</div><div class='add'>+				      "axi_s_sticky",</div><div class='add'>+				      "axi_s",</div><div class='add'>+				      "axi_m_sticky",</div><div class='add'>+				      "axi_m",</div><div class='add'>+				      "aux",</div><div class='add'>+				      "ahb";</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;pcie2_phy&gt;;</div><div class='add'>+			phy-names = "pciephy";</div><div class='add'>+			interconnects = &lt;&amp;gcc MASTER_ANOC_PCIE2 &amp;gcc SLAVE_ANOC_PCIE2&gt;,</div><div class='add'>+					&lt;&amp;gcc MASTER_CNOC_PCIE2 &amp;gcc SLAVE_CNOC_PCIE2&gt;;</div><div class='add'>+			interconnect-names = "pcie-mem", "cpu-pcie";</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcie@0 {</div><div class='add'>+				device_type = "pci";</div><div class='add'>+				reg = &lt;0x0 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+				bus-range = &lt;0x01 0xff&gt;;</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;3&gt;;</div><div class='add'>+				#size-cells = &lt;2&gt;;</div><div class='add'>+				ranges;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie1: pcie@60000000 {</div><div class='add'>+			compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574";</div><div class='add'>+			reg = &lt;0x0 0x60000000 0x0 0xf1c&gt;,</div><div class='add'>+			      &lt;0x0 0x60000f20 0x0 0xa8&gt;,</div><div class='add'>+			      &lt;0x0 0x60001000 0x0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0x00088000 0x0 0x3000&gt;,</div><div class='add'>+			      &lt;0x0 0x60100000 0x0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0x0008e000 0x0 0x1000&gt;;</div><div class='add'>+			reg-names = "dbi",</div><div class='add'>+				    "elbi",</div><div class='add'>+				    "atu",</div><div class='add'>+				    "parf",</div><div class='add'>+				    "config",</div><div class='add'>+				    "mhi";</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			linux,pci-domain = &lt;1&gt;;</div><div class='add'>+			num-lanes = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			ranges = &lt;0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x00100000&gt;,</div><div class='add'>+				 &lt;0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x0fd00000&gt;;</div><div class='add'>+</div><div class='add'>+			msi-map = &lt;0x0 &amp;intc 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "msi0",</div><div class='add'>+					  "msi1",</div><div class='add'>+					  "msi2",</div><div class='add'>+					  "msi3",</div><div class='add'>+					  "msi4",</div><div class='add'>+					  "msi5",</div><div class='add'>+					  "msi6",</div><div class='add'>+					  "msi7",</div><div class='add'>+					  "global";</div><div class='add'>+</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0x0 0x0 0x0 0x7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;intc GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;intc GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;intc GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;intc GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_PCIE1_AXI_M_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_AXI_S_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_AXI_S_BRIDGE_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_RCHNG_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_AUX_CLK&gt;;</div><div class='add'>+			clock-names = "axi_m",</div><div class='add'>+				      "axi_s",</div><div class='add'>+				      "axi_bridge",</div><div class='add'>+				      "rchng",</div><div class='add'>+				      "ahb",</div><div class='add'>+				      "aux";</div><div class='add'>+</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_PCIE1_RCHNG_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;100000000&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_PCIE1_PIPE_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_CORE_STICKY_RESET&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_AXI_S_STICKY_RESET&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_AXI_S_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_AXI_M_STICKY_RESET&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_AXI_M_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_AUX_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_AHB_ARES&gt;;</div><div class='add'>+			reset-names = "pipe",</div><div class='add'>+				      "sticky",</div><div class='add'>+				      "axi_s_sticky",</div><div class='add'>+				      "axi_s",</div><div class='add'>+				      "axi_m_sticky",</div><div class='add'>+				      "axi_m",</div><div class='add'>+				      "aux",</div><div class='add'>+				      "ahb";</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;pcie1_phy&gt;;</div><div class='add'>+			phy-names = "pciephy";</div><div class='add'>+			interconnects = &lt;&amp;gcc MASTER_ANOC_PCIE1	&amp;gcc SLAVE_ANOC_PCIE1&gt;,</div><div class='add'>+					&lt;&amp;gcc MASTER_CNOC_PCIE1	&amp;gcc SLAVE_CNOC_PCIE1&gt;;</div><div class='add'>+			interconnect-names = "pcie-mem", "cpu-pcie";</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcie@0 {</div><div class='add'>+				device_type = "pci";</div><div class='add'>+				reg = &lt;0x0 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+				bus-range = &lt;0x01 0xff&gt;;</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;3&gt;;</div><div class='add'>+				#size-cells = &lt;2&gt;;</div><div class='add'>+				ranges;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie0: pcie@70000000 {</div><div class='add'>+			compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574";</div><div class='add'>+			reg = &lt;0x0 0x70000000 0x0 0xf1c&gt;,</div><div class='add'>+			      &lt;0x0 0x70000f20 0x0 0xa8&gt;,</div><div class='add'>+			      &lt;0x0 0x70001000 0x0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0x00080000 0x0 0x3000&gt;,</div><div class='add'>+			      &lt;0x0 0x70100000 0x0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0x00086000 0x0 0x1000&gt;;</div><div class='add'>+			reg-names = "dbi",</div><div class='add'>+				    "elbi",</div><div class='add'>+				    "atu",</div><div class='add'>+				    "parf",</div><div class='add'>+				    "config",</div><div class='add'>+				    "mhi";</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			linux,pci-domain = &lt;0&gt;;</div><div class='add'>+			num-lanes = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			ranges = &lt;0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x00100000&gt;,</div><div class='add'>+				 &lt;0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x0fd00000&gt;;</div><div class='add'>+</div><div class='add'>+			msi-map = &lt;0x0 &amp;intc 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "msi0",</div><div class='add'>+					  "msi1",</div><div class='add'>+					  "msi2",</div><div class='add'>+					  "msi3",</div><div class='add'>+					  "msi4",</div><div class='add'>+					  "msi5",</div><div class='add'>+					  "msi6",</div><div class='add'>+					  "msi7",</div><div class='add'>+					  "global";</div><div class='add'>+</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0x0 0x0 0x0 0x7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;intc GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;intc GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_PCIE0_AXI_M_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AXI_S_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AXI_S_BRIDGE_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_RCHNG_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AUX_CLK&gt;;</div><div class='add'>+			clock-names = "axi_m",</div><div class='add'>+				      "axi_s",</div><div class='add'>+				      "axi_bridge",</div><div class='add'>+				      "rchng",</div><div class='add'>+				      "ahb",</div><div class='add'>+				      "aux";</div><div class='add'>+</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_PCIE0_RCHNG_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;100000000&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_PCIE0_PIPE_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_CORE_STICKY_RESET&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AXI_S_STICKY_RESET&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AXI_S_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AXI_M_STICKY_RESET&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AXI_M_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AUX_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AHB_ARES&gt;;</div><div class='add'>+			reset-names = "pipe",</div><div class='add'>+				      "sticky",</div><div class='add'>+				      "axi_s_sticky",</div><div class='add'>+				      "axi_s",</div><div class='add'>+				      "axi_m_sticky",</div><div class='add'>+				      "axi_m",</div><div class='add'>+				      "aux",</div><div class='add'>+				      "ahb";</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;pcie0_phy&gt;;</div><div class='add'>+			phy-names = "pciephy";</div><div class='add'>+			interconnects = &lt;&amp;gcc MASTER_ANOC_PCIE0 &amp;gcc SLAVE_ANOC_PCIE0&gt;,</div><div class='add'>+					&lt;&amp;gcc MASTER_CNOC_PCIE0	&amp;gcc SLAVE_CNOC_PCIE0&gt;;</div><div class='add'>+			interconnect-names = "pcie-mem", "cpu-pcie";</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcie@0 {</div><div class='add'>+				device_type = "pci";</div><div class='add'>+				reg = &lt;0x0 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+				bus-range = &lt;0x01 0xff&gt;;</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;3&gt;;</div><div class='add'>+				#size-cells = &lt;2&gt;;</div><div class='add'>+				ranges;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	thermal_zones: thermal-zones {</div><div class='add'>+		cpu0-thermal {</div><div class='add'>+			polling-delay-passive = &lt;100&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 14&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu0_crit: cpu-critical {</div><div class='add'>+					temperature = &lt;120000&gt;;</div><div class='add'>+					hysteresis = &lt;9000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu0_alert: cpu-passive {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;9000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu0_alert&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1-thermal {</div><div class='add'>+			polling-delay-passive = &lt;100&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 12&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu1_crit: cpu-critical {</div><div class='add'>+					temperature = &lt;120000&gt;;</div><div class='add'>+					hysteresis = &lt;9000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu1_alert: cpu-passive {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;9000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu1_alert&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2-thermal {</div><div class='add'>+			polling-delay-passive = &lt;100&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 11&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu2_crit: cpu-critical {</div><div class='add'>+					temperature = &lt;120000&gt;;</div><div class='add'>+					hysteresis = &lt;9000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu2_alert: cpu-passive {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;9000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu2_alert&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3-thermal {</div><div class='add'>+			polling-delay-passive = &lt;100&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 13&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu3_crit: cpu-critical {</div><div class='add'>+					temperature = &lt;120000&gt;;</div><div class='add'>+					hysteresis = &lt;9000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu3_alert: cpu-passive {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;9000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu3_alert&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wcss-tile2-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 9&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				wcss-tile2-critical {</div><div class='add'>+					temperature = &lt;125000&gt;;</div><div class='add'>+					hysteresis = &lt;9000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wcss-tile3-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 10&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				wcss-tile3-critical {</div><div class='add'>+					temperature = &lt;125000&gt;;</div><div class='add'>+					hysteresis = &lt;9000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		top-glue-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 15&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				top-glue-critical {</div><div class='add'>+					temperature = &lt;125000&gt;;</div><div class='add'>+					hysteresis = &lt;9000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 12 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts<br/>index b31117a93995..9c69d3027b43 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts</a></div><div class='hunk'>@@ -7,7 +7,7 @@</div><div class='ctx'> </div><div class='ctx'> /dts-v1/;</div><div class='ctx'> </div><div class='del'>-#include "ipq6018.dtsi"</div><div class='add'>+#include "ipq6018-mp5496.dtsi"</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	model = "Qualcomm Technologies, Inc. IPQ6018/AP-CP01-C1";</div><div class='hunk'>@@ -19,46 +19,70 @@</div><div class='ctx'> </div><div class='ctx'> 	chosen {</div><div class='ctx'> 		stdout-path = "serial0:115200n8";</div><div class='del'>-		bootargs-append = " swiotlb=1";</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;blsp1_uart3 {</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;serial_3_pins&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;i2c_1 {</div><div class='add'>+&amp;blsp1_i2c3 {</div><div class='ctx'> 	pinctrl-0 = &lt;&amp;i2c_1_pins&gt;;</div><div class='ctx'> 	pinctrl-names = "default";</div><div class='del'>-	status = "ok";</div><div class='add'>+	status = "okay";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;spi_0 {</div><div class='del'>-	cs-select = &lt;0&gt;;</div><div class='del'>-	status = "ok";</div><div class='add'>+&amp;blsp1_spi1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;spi_0_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='ctx'> </div><div class='del'>-	m25p80@0 {</div><div class='add'>+	flash@0 {</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;1&gt;;</div><div class='ctx'> 		reg = &lt;0&gt;;</div><div class='del'>-		compatible = "n25q128a11";</div><div class='add'>+		compatible = "micron,n25q128a11", "jedec,spi-nor";</div><div class='ctx'> 		spi-max-frequency = &lt;50000000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> &amp;tlmm {</div><div class='del'>-	i2c_1_pins: i2c-1-pins {</div><div class='add'>+	i2c_1_pins: i2c-1-state {</div><div class='ctx'> 		pins = "gpio42", "gpio43";</div><div class='ctx'> 		function = "blsp2_i2c";</div><div class='ctx'> 		drive-strength = &lt;8&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	spi_0_pins: spi-0-pins {</div><div class='add'>+	spi_0_pins: spi-0-state {</div><div class='ctx'> 		pins = "gpio38", "gpio39", "gpio40", "gpio41";</div><div class='ctx'> 		function = "blsp0_spi";</div><div class='ctx'> 		drive-strength = &lt;8&gt;;</div><div class='ctx'> 		bias-pull-down;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='add'>+</div><div class='add'>+&amp;qpic_bam {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qpic_nand {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	nand@0 {</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		nand-ecc-strength = &lt;4&gt;;</div><div class='add'>+		nand-ecc-step-size = &lt;512&gt;;</div><div class='add'>+		nand-bus-width = &lt;8&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qusb_phy_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi b/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi<br/>new file mode 100644<br/>index 000000000000..d6b111a77f79<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi</a></div><div class='hunk'>@@ -0,0 +1,44 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)</div><div class='add'>+/*</div><div class='add'>+ * ipq6018-mp5496.dtsi describes common properties (e.g. regulators) that</div><div class='add'>+ * apply to most devices that make use of the IPQ6018 SoC and MP5496 PMIC.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "ipq6018.dtsi"</div><div class='add'>+</div><div class='add'>+&amp;cpu0 {</div><div class='add'>+	cpu-supply = &lt;&amp;mp5496_s2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu1 {</div><div class='add'>+	cpu-supply = &lt;&amp;mp5496_s2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu2 {</div><div class='add'>+	cpu-supply = &lt;&amp;mp5496_s2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cpu3 {</div><div class='add'>+	cpu-supply = &lt;&amp;mp5496_s2&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;rpm_requests {</div><div class='add'>+	regulators {</div><div class='add'>+		compatible = "qcom,rpm-mp5496-regulators";</div><div class='add'>+</div><div class='add'>+		mp5496_s2: s2 {</div><div class='add'>+			regulator-min-microvolt = &lt;725000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1062500&gt;;</div><div class='add'>+			regulator-always-on;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mp5496_l2: l2 {</div><div class='add'>+			regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sdhc {</div><div class='add'>+	vqmmc-supply = &lt;&amp;mp5496_l2&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi<br/>index 1aa8d8579463..40f1c262126e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/ipq6018.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/ipq6018.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/ipq6018.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/ipq6018.dtsi</a></div><div class='hunk'>@@ -8,6 +8,8 @@</div><div class='ctx'> #include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/clock/qcom,gcc-ipq6018.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/reset/qcom,gcc-ipq6018.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,apss-ipq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/thermal/thermal.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	#address-cells = &lt;2&gt;;</div><div class='hunk'>@@ -32,60 +34,133 @@</div><div class='ctx'> 		#address-cells = &lt;1&gt;;</div><div class='ctx'> 		#size-cells = &lt;0&gt;;</div><div class='ctx'> </div><div class='del'>-		CPU0: cpu@0 {</div><div class='add'>+		cpu0: cpu@0 {</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			reg = &lt;0x0&gt;;</div><div class='ctx'> 			enable-method = "psci";</div><div class='del'>-			next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			clocks = &lt;&amp;apcs_glb APCS_ALIAS0_CORE_CLK&gt;;</div><div class='add'>+			clock-names = "cpu";</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		CPU1: cpu@1 {</div><div class='add'>+		cpu1: cpu@1 {</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			reg = &lt;0x1&gt;;</div><div class='del'>-			next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			clocks = &lt;&amp;apcs_glb APCS_ALIAS0_CORE_CLK&gt;;</div><div class='add'>+			clock-names = "cpu";</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		CPU2: cpu@2 {</div><div class='add'>+		cpu2: cpu@2 {</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			reg = &lt;0x2&gt;;</div><div class='del'>-			next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			clocks = &lt;&amp;apcs_glb APCS_ALIAS0_CORE_CLK&gt;;</div><div class='add'>+			clock-names = "cpu";</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		CPU3: cpu@3 {</div><div class='add'>+		cpu3: cpu@3 {</div><div class='ctx'> 			device_type = "cpu";</div><div class='ctx'> 			compatible = "arm,cortex-a53";</div><div class='ctx'> 			enable-method = "psci";</div><div class='ctx'> 			reg = &lt;0x3&gt;;</div><div class='del'>-			next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			clocks = &lt;&amp;apcs_glb APCS_ALIAS0_CORE_CLK&gt;;</div><div class='add'>+			clock-names = "cpu";</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		L2_0: l2-cache {</div><div class='add'>+		l2_0: l2-cache {</div><div class='ctx'> 			compatible = "cache";</div><div class='del'>-			cache-level = &lt;0x2&gt;;</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	firmware {</div><div class='ctx'> 		scm {</div><div class='del'>-			compatible = "qcom,scm";</div><div class='add'>+			compatible = "qcom,scm-ipq6018", "qcom,scm";</div><div class='add'>+			qcom,dload-mode = &lt;&amp;tcsr 0x6100&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	tcsr_mutex: hwlock {</div><div class='del'>-		compatible = "qcom,tcsr-mutex";</div><div class='del'>-		syscon = &lt;&amp;tcsr_mutex_regs 0 0x80&gt;;</div><div class='del'>-		#hwlock-cells = &lt;1&gt;;</div><div class='add'>+	cpu_opp_table: opp-table-cpu {</div><div class='add'>+		compatible = "operating-points-v2-kryo-cpu";</div><div class='add'>+		nvmem-cells = &lt;&amp;cpu_speed_bin&gt;;</div><div class='add'>+		opp-shared;</div><div class='add'>+</div><div class='add'>+		opp-864000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;864000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;725000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0xf&gt;;</div><div class='add'>+			clock-latency-ns = &lt;200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1056000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1056000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;787500&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0xf&gt;;</div><div class='add'>+			clock-latency-ns = &lt;200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1200000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1200000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;850000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x4&gt;;</div><div class='add'>+			clock-latency-ns = &lt;200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1320000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1320000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;862500&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x3&gt;;</div><div class='add'>+			clock-latency-ns = &lt;200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1440000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1440000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;925000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x3&gt;;</div><div class='add'>+			clock-latency-ns = &lt;200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1512000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1512000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;937500&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x2&gt;;</div><div class='add'>+			clock-latency-ns = &lt;200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1608000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1608000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;987500&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x1&gt;;</div><div class='add'>+			clock-latency-ns = &lt;200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1800000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1800000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1062500&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x1&gt;;</div><div class='add'>+			clock-latency-ns = &lt;200000&gt;;</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	pmuv8: pmu {</div><div class='ctx'> 		compatible = "arm,cortex-a53-pmu";</div><div class='del'>-		interrupts = &lt;GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |</div><div class='del'>-					 IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	psci: psci {</div><div class='hunk'>@@ -93,65 +168,197 @@</div><div class='ctx'> 		method = "smc";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	rpm: remoteproc {</div><div class='add'>+		compatible = "qcom,ipq6018-rpm-proc", "qcom,rpm-proc";</div><div class='add'>+</div><div class='add'>+		glink-edge {</div><div class='add'>+			compatible = "qcom,glink-rpm";</div><div class='add'>+			interrupts = &lt;GIC_SPI 168 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			qcom,rpm-msg-ram = &lt;&amp;rpm_msg_ram&gt;;</div><div class='add'>+			mboxes = &lt;&amp;apcs_glb 0&gt;;</div><div class='add'>+</div><div class='add'>+			rpm_requests: rpm-requests {</div><div class='add'>+				compatible = "qcom,rpm-ipq6018", "qcom,glink-smd-rpm";</div><div class='add'>+				qcom,glink-channels = "rpm_requests";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='ctx'> 	reserved-memory {</div><div class='ctx'> 		#address-cells = &lt;2&gt;;</div><div class='ctx'> 		#size-cells = &lt;2&gt;;</div><div class='ctx'> 		ranges;</div><div class='ctx'> </div><div class='del'>-		tz: tz@48500000 {</div><div class='del'>-			reg = &lt;0x0 0x48500000 0x0 0x00200000&gt;;</div><div class='add'>+		rpm_msg_ram: memory@60000 {</div><div class='add'>+			reg = &lt;0x0 0x00060000 0x0 0x6000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		bootloader@4a100000 {</div><div class='add'>+			reg = &lt;0x0 0x4a100000 0x0 0x400000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sbl@4a500000 {</div><div class='add'>+			reg = &lt;0x0 0x4a500000 0x0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tz: memory@4a600000 {</div><div class='add'>+			reg = &lt;0x0 0x4a600000 0x0 0x400000&gt;;</div><div class='ctx'> 			no-map;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		smem_region: memory@4aa00000 {</div><div class='del'>-			reg = &lt;0x0 0x4aa00000 0x0 0x00100000&gt;;</div><div class='add'>+			compatible = "qcom,smem";</div><div class='add'>+			reg = &lt;0x0 0x4aa00000 0x0 0x100000&gt;;</div><div class='ctx'> 			no-map;</div><div class='add'>+</div><div class='add'>+			hwlocks = &lt;&amp;tcsr_mutex 3&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		q6_region: memory@4ab00000 {</div><div class='del'>-			reg = &lt;0x0 0x4ab00000 0x0 0x02800000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x4ab00000 0x0 0x5500000&gt;;</div><div class='ctx'> 			no-map;</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	smem {</div><div class='del'>-		compatible = "qcom,smem";</div><div class='del'>-		memory-region = &lt;&amp;smem_region&gt;;</div><div class='del'>-		hwlocks = &lt;&amp;tcsr_mutex 0&gt;;</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	soc: soc {</div><div class='del'>-		#address-cells = &lt;1&gt;;</div><div class='del'>-		#size-cells = &lt;1&gt;;</div><div class='del'>-		ranges = &lt;0 0 0 0xffffffff&gt;;</div><div class='add'>+	soc: soc@0 {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges = &lt;0 0 0 0 0x0 0xffffffff&gt;;</div><div class='ctx'> 		dma-ranges;</div><div class='ctx'> 		compatible = "simple-bus";</div><div class='ctx'> </div><div class='del'>-		prng: qrng@e1000 {</div><div class='add'>+		qusb_phy_1: qusb@59000 {</div><div class='add'>+			compatible = "qcom,ipq6018-qusb2-phy";</div><div class='add'>+			reg = &lt;0x0 0x00059000 0x0 0x180&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_USB1_PHY_CFG_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;xo&gt;;</div><div class='add'>+			clock-names = "cfg_ahb", "ref";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_QUSB2_1_PHY_BCR&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ssphy_0: ssphy@78000 {</div><div class='add'>+			compatible = "qcom,ipq6018-qmp-usb3-phy";</div><div class='add'>+			reg = &lt;0x0 0x00078000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_USB0_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;xo&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB0_PHY_CFG_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB0_PIPE_CLK&gt;;</div><div class='add'>+			clock-names = "aux",</div><div class='add'>+				      "ref",</div><div class='add'>+				      "cfg_ahb",</div><div class='add'>+				      "pipe";</div><div class='add'>+			clock-output-names = "gcc_usb0_pipe_clk_src";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_USB0_PHY_BCR&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB3PHY_0_PHY_BCR&gt;;</div><div class='add'>+			reset-names = "phy",</div><div class='add'>+				      "phy_phy";</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qusb_phy_0: qusb@79000 {</div><div class='add'>+			compatible = "qcom,ipq6018-qusb2-phy";</div><div class='add'>+			reg = &lt;0x0 0x00079000 0x0 0x180&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_USB0_PHY_CFG_AHB_CLK&gt;,</div><div class='add'>+				&lt;&amp;xo&gt;;</div><div class='add'>+			clock-names = "cfg_ahb", "ref";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_QUSB2_0_PHY_BCR&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie_phy: phy@84000 {</div><div class='add'>+			compatible = "qcom,ipq6018-qmp-pcie-phy";</div><div class='add'>+			reg = &lt;0x0 0x00084000 0x0 0x1000&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_PCIE0_AUX_CLK&gt;,</div><div class='add'>+				&lt;&amp;gcc GCC_PCIE0_AHB_CLK&gt;,</div><div class='add'>+				&lt;&amp;gcc GCC_PCIE0_PIPE_CLK&gt;;</div><div class='add'>+			clock-names = "aux",</div><div class='add'>+				      "cfg_ahb",</div><div class='add'>+				      "pipe";</div><div class='add'>+</div><div class='add'>+			clock-output-names = "gcc_pcie0_pipe_clk_src";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_PCIE0_PHY_BCR&gt;,</div><div class='add'>+				&lt;&amp;gcc GCC_PCIE0PHY_PHY_BCR&gt;;</div><div class='add'>+			reset-names = "phy",</div><div class='add'>+				      "common";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio: mdio@90000 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio";</div><div class='add'>+			reg = &lt;0x0 0x00090000 0x0 0x64&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_MDIO_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "gcc_mdio_ahb_clk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qfprom: efuse@a4000 {</div><div class='add'>+			compatible = "qcom,ipq6018-qfprom", "qcom,qfprom";</div><div class='add'>+			reg = &lt;0x0 0x000a4000 0x0 0x2000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			cpu_speed_bin: cpu-speed-bin@135 {</div><div class='add'>+				reg = &lt;0x135 0x1&gt;;</div><div class='add'>+				bits = &lt;7 1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		prng: qrng@e3000 {</div><div class='ctx'> 			compatible = "qcom,prng-ee";</div><div class='del'>-			reg = &lt;0xe3000 0x1000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x000e3000 0x0 0x1000&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;gcc GCC_PRNG_AHB_CLK&gt;;</div><div class='ctx'> 			clock-names = "core";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		cryptobam: dma@704000 {</div><div class='add'>+		tsens: thermal-sensor@4a9000 {</div><div class='add'>+			compatible = "qcom,ipq6018-tsens", "qcom,ipq8074-tsens";</div><div class='add'>+			reg = &lt;0x0 0x004a9000 0x0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0x004a8000 0x0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "combined";</div><div class='add'>+			#qcom,sensors = &lt;16&gt;;</div><div class='add'>+			#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cryptobam: dma-controller@704000 {</div><div class='ctx'> 			compatible = "qcom,bam-v1.7.0";</div><div class='del'>-			reg = &lt;0x00704000 0x20000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x00704000 0x0 0x20000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;gcc GCC_CRYPTO_AHB_CLK&gt;;</div><div class='ctx'> 			clock-names = "bam_clk";</div><div class='ctx'> 			#dma-cells = &lt;1&gt;;</div><div class='ctx'> 			qcom,ee = &lt;1&gt;;</div><div class='del'>-			qcom,controlled-remotely = &lt;1&gt;;</div><div class='del'>-			qcom,config-pipe-trust-reg = &lt;0&gt;;</div><div class='add'>+			qcom,controlled-remotely;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		crypto: crypto@73a000 {</div><div class='ctx'> 			compatible = "qcom,crypto-v5.1";</div><div class='del'>-			reg = &lt;0x0073a000 0x6000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x0073a000 0x0 0x6000&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;gcc GCC_CRYPTO_AHB_CLK&gt;,</div><div class='del'>-				&lt;&amp;gcc GCC_CRYPTO_AXI_CLK&gt;,</div><div class='del'>-				&lt;&amp;gcc GCC_CRYPTO_CLK&gt;;</div><div class='add'>+				 &lt;&amp;gcc GCC_CRYPTO_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_CRYPTO_CLK&gt;;</div><div class='ctx'> 			clock-names = "iface", "bus", "core";</div><div class='ctx'> 			dmas = &lt;&amp;cryptobam 2&gt;, &lt;&amp;cryptobam 3&gt;;</div><div class='ctx'> 			dma-names = "rx", "tx";</div><div class='hunk'>@@ -159,44 +366,116 @@</div><div class='ctx'> </div><div class='ctx'> 		tlmm: pinctrl@1000000 {</div><div class='ctx'> 			compatible = "qcom,ipq6018-pinctrl";</div><div class='del'>-			reg = &lt;0x01000000 0x300000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x01000000 0x0 0x300000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			gpio-controller;</div><div class='ctx'> 			#gpio-cells = &lt;2&gt;;</div><div class='del'>-			gpio-ranges = &lt;&amp;tlmm 0 80&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;tlmm 0 0 80&gt;;</div><div class='ctx'> 			interrupt-controller;</div><div class='ctx'> 			#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='del'>-			serial_3_pins: serial3-pinmux {</div><div class='add'>+			serial_3_pins: serial3-state {</div><div class='ctx'> 				pins = "gpio44", "gpio45";</div><div class='ctx'> 				function = "blsp2_uart";</div><div class='ctx'> 				drive-strength = &lt;8&gt;;</div><div class='ctx'> 				bias-pull-down;</div><div class='ctx'> 			};</div><div class='add'>+</div><div class='add'>+			qpic_pins: qpic-state {</div><div class='add'>+				pins = "gpio1", "gpio3", "gpio4",</div><div class='add'>+					"gpio5", "gpio6", "gpio7",</div><div class='add'>+					"gpio8", "gpio10", "gpio11",</div><div class='add'>+					"gpio12", "gpio13", "gpio14",</div><div class='add'>+					"gpio15", "gpio17";</div><div class='add'>+				function = "qpic_pad";</div><div class='add'>+				drive-strength = &lt;8&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		gcc: gcc@1800000 {</div><div class='add'>+		gcc: clock-controller@1800000 {</div><div class='ctx'> 			compatible = "qcom,gcc-ipq6018";</div><div class='del'>-			reg = &lt;0x01800000 0x80000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x01800000 0x0 0x80000&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;xo&gt;, &lt;&amp;sleep_clk&gt;;</div><div class='ctx'> 			clock-names = "xo", "sleep_clk";</div><div class='ctx'> 			#clock-cells = &lt;1&gt;;</div><div class='ctx'> 			#reset-cells = &lt;1&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		tcsr_mutex_regs: syscon@1905000 {</div><div class='del'>-			compatible = "syscon";</div><div class='del'>-			reg = &lt;0x01905000 0x8000&gt;;</div><div class='add'>+		tcsr_mutex: hwlock@1905000 {</div><div class='add'>+			compatible = "qcom,ipq6018-tcsr-mutex", "qcom,tcsr-mutex";</div><div class='add'>+			reg = &lt;0x0 0x01905000 0x0 0x20000&gt;;</div><div class='add'>+			#hwlock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tcsr: syscon@1937000 {</div><div class='add'>+			compatible = "qcom,tcsr-ipq6018", "syscon";</div><div class='add'>+			reg = &lt;0x0 0x01937000 0x0 0x21000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb2: usb@70f8800 {</div><div class='add'>+			compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";</div><div class='add'>+			reg = &lt;0x0 0x070f8800 0x0 0x400&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_USB1_MASTER_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB1_SLEEP_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB1_MOCK_UTMI_CLK&gt;;</div><div class='add'>+			clock-names = "core",</div><div class='add'>+				      "sleep",</div><div class='add'>+				      "mock_utmi";</div><div class='add'>+</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_USB1_MASTER_CLK&gt;,</div><div class='add'>+					  &lt;&amp;gcc GCC_USB1_MOCK_UTMI_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;133330000&gt;,</div><div class='add'>+					       &lt;24000000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "pwr_event",</div><div class='add'>+					  "qusb2_phy";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_USB1_BCR&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			dwc_1: usb@7000000 {</div><div class='add'>+				compatible = "snps,dwc3";</div><div class='add'>+				reg = &lt;0x0 0x07000000 0x0 0xcd00&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				phys = &lt;&amp;qusb_phy_1&gt;;</div><div class='add'>+				phy-names = "usb2-phy";</div><div class='add'>+				tx-fifo-resize;</div><div class='add'>+				snps,is-utmi-l1-suspend;</div><div class='add'>+				snps,hird-threshold = /bits/ 8 &lt;0x0&gt;;</div><div class='add'>+				snps,dis_u2_susphy_quirk;</div><div class='add'>+				snps,dis_u3_susphy_quirk;</div><div class='add'>+				dr_mode = "host";</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		tcsr_q6: syscon@1945000 {</div><div class='del'>-			compatible = "syscon";</div><div class='del'>-			reg = &lt;0x01945000 0xe000&gt;;</div><div class='add'>+		sdhc: mmc@7804000 {</div><div class='add'>+			compatible = "qcom,ipq6018-sdhci", "qcom,sdhci-msm-v5";</div><div class='add'>+			reg = &lt;0x0 0x07804000 0x0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0x07805000 0x0 0x1000&gt;;</div><div class='add'>+			reg-names = "hc", "cqhci";</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "hc_irq", "pwr_irq";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_SDCC1_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_SDCC1_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;xo&gt;;</div><div class='add'>+			clock-names = "iface", "core", "xo";</div><div class='add'>+			resets = &lt;&amp;gcc GCC_SDCC1_BCR&gt;;</div><div class='add'>+			max-frequency = &lt;192000000&gt;;</div><div class='add'>+			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		blsp_dma: dma@7884000 {</div><div class='add'>+		blsp_dma: dma-controller@7884000 {</div><div class='ctx'> 			compatible = "qcom,bam-v1.7.0";</div><div class='del'>-			reg = &lt;0x07884000 0x2b000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x07884000 0x0 0x2b000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='ctx'> 			clock-names = "bam_clk";</div><div class='hunk'>@@ -204,117 +483,284 @@</div><div class='ctx'> 			qcom,ee = &lt;0&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		blsp1_uart1: serial@78af000 {</div><div class='add'>+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";</div><div class='add'>+			reg = &lt;0x0 0x78af000 0x0 0x200&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_BLSP1_UART1_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "core", "iface";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		blsp1_uart2: serial@78b0000 {</div><div class='add'>+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";</div><div class='add'>+			reg = &lt;0x0 0x78b0000 0x0 0x200&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_BLSP1_UART2_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "core", "iface";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		blsp1_uart3: serial@78b1000 {</div><div class='ctx'> 			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";</div><div class='del'>-			reg = &lt;0x078b1000 0x200&gt;;</div><div class='add'>+			reg = &lt;0x0 0x078b1000 0x0 0x200&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;gcc GCC_BLSP1_UART3_APPS_CLK&gt;,</div><div class='del'>-				&lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='add'>+				 &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "core", "iface";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		blsp1_uart4: serial@78b2000 {</div><div class='add'>+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";</div><div class='add'>+			reg = &lt;0x0 0x078b2000 0x0 0x200&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_BLSP1_UART4_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='ctx'> 			clock-names = "core", "iface";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		spi_0: spi@78b5000 {</div><div class='add'>+		blsp1_uart5: serial@78b3000 {</div><div class='add'>+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";</div><div class='add'>+			reg = &lt;0x0 0x78b3000 0x0 0x200&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_BLSP1_UART5_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "core", "iface";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		blsp1_uart6: serial@78b4000 {</div><div class='add'>+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";</div><div class='add'>+			reg = &lt;0x0 0x078b4000 0x0 0x200&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_BLSP1_UART6_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "core", "iface";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		blsp1_spi1: spi@78b5000 {</div><div class='ctx'> 			compatible = "qcom,spi-qup-v2.2.1";</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='del'>-			reg = &lt;0x078b5000 0x600&gt;;</div><div class='add'>+			reg = &lt;0x0 0x078b5000 0x0 0x600&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			spi-max-frequency = &lt;50000000&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;gcc GCC_BLSP1_QUP1_SPI_APPS_CLK&gt;,</div><div class='del'>-				&lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='add'>+				 &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='ctx'> 			clock-names = "core", "iface";</div><div class='ctx'> 			dmas = &lt;&amp;blsp_dma 12&gt;, &lt;&amp;blsp_dma 13&gt;;</div><div class='ctx'> 			dma-names = "tx", "rx";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		spi_1: spi@78b6000 {</div><div class='add'>+		blsp1_spi2: spi@78b6000 {</div><div class='ctx'> 			compatible = "qcom,spi-qup-v2.2.1";</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='del'>-			reg = &lt;0x078b6000 0x600&gt;;</div><div class='add'>+			reg = &lt;0x0 0x078b6000 0x0 0x600&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			spi-max-frequency = &lt;50000000&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;gcc GCC_BLSP1_QUP2_SPI_APPS_CLK&gt;,</div><div class='del'>-				&lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='add'>+				 &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='ctx'> 			clock-names = "core", "iface";</div><div class='ctx'> 			dmas = &lt;&amp;blsp_dma 14&gt;, &lt;&amp;blsp_dma 15&gt;;</div><div class='ctx'> 			dma-names = "tx", "rx";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		i2c_0: i2c@78b6000 {</div><div class='add'>+		blsp1_spi5: spi@78b9000 {</div><div class='add'>+			compatible = "qcom,spi-qup-v2.2.1";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0x0 0x078b9000 0x0 0x600&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_BLSP1_QUP5_SPI_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "core", "iface";</div><div class='add'>+			dmas = &lt;&amp;blsp_dma 20&gt;, &lt;&amp;blsp_dma 21&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		blsp1_i2c2: i2c@78b6000 {</div><div class='ctx'> 			compatible = "qcom,i2c-qup-v2.2.1";</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='del'>-			reg = &lt;0x078b6000 0x600&gt;;</div><div class='add'>+			reg = &lt;0x0 0x078b6000 0x0 0x600&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;,</div><div class='del'>-				&lt;&amp;gcc GCC_BLSP1_QUP2_I2C_APPS_CLK&gt;;</div><div class='del'>-			clock-names = "iface", "core";</div><div class='del'>-			clock-frequency  = &lt;400000&gt;;</div><div class='del'>-			dmas = &lt;&amp;blsp_dma 15&gt;, &lt;&amp;blsp_dma 14&gt;;</div><div class='del'>-			dma-names = "rx", "tx";</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_BLSP1_QUP2_I2C_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "core", "iface";</div><div class='add'>+			clock-frequency = &lt;400000&gt;;</div><div class='add'>+			dmas = &lt;&amp;blsp_dma 14&gt;, &lt;&amp;blsp_dma 15&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		i2c_1: i2c@78b7000 { /* BLSP1 QUP2 */</div><div class='add'>+		blsp1_i2c3: i2c@78b7000 {</div><div class='ctx'> 			compatible = "qcom,i2c-qup-v2.2.1";</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='del'>-			reg = &lt;0x078b7000 0x600&gt;;</div><div class='add'>+			reg = &lt;0x0 0x078b7000 0x0 0x600&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;,</div><div class='del'>-				&lt;&amp;gcc GCC_BLSP1_QUP3_I2C_APPS_CLK&gt;;</div><div class='del'>-			clock-names = "iface", "core";</div><div class='del'>-			clock-frequency  = &lt;400000&gt;;</div><div class='del'>-			dmas = &lt;&amp;blsp_dma 17&gt;, &lt;&amp;blsp_dma 16&gt;;</div><div class='del'>-			dma-names = "rx", "tx";</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_BLSP1_QUP3_I2C_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "core", "iface";</div><div class='add'>+			clock-frequency = &lt;400000&gt;;</div><div class='add'>+			dmas = &lt;&amp;blsp_dma 16&gt;, &lt;&amp;blsp_dma 17&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		blsp1_i2c6: i2c@78ba000 {</div><div class='add'>+			compatible = "qcom,i2c-qup-v2.2.1";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0x0 0x078ba000 0x0 0x600&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_BLSP1_QUP6_I2C_APPS_CLK&gt;,</div><div class='add'>+			       &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "core", "iface";</div><div class='add'>+			clock-frequency = &lt;400000&gt;;</div><div class='add'>+			dmas = &lt;&amp;blsp_dma 22&gt;, &lt;&amp;blsp_dma 23&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qpic_bam: dma-controller@7984000 {</div><div class='add'>+			compatible = "qcom,bam-v1.7.0";</div><div class='add'>+			reg = &lt;0x0 0x07984000 0x0 0x1a000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_QPIC_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "bam_clk";</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+			qcom,ee = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qpic_nand: nand-controller@79b0000 {</div><div class='add'>+			compatible = "qcom,ipq6018-nand";</div><div class='add'>+			reg = &lt;0x0 0x079b0000 0x0 0x10000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_QPIC_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_QPIC_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "core", "aon";</div><div class='add'>+</div><div class='add'>+			dmas = &lt;&amp;qpic_bam 0&gt;,</div><div class='add'>+			       &lt;&amp;qpic_bam 1&gt;,</div><div class='add'>+			       &lt;&amp;qpic_bam 2&gt;;</div><div class='add'>+			dma-names = "tx", "rx", "cmd";</div><div class='add'>+			pinctrl-0 = &lt;&amp;qpic_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb3: usb@8af8800 {</div><div class='add'>+			compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";</div><div class='add'>+			reg = &lt;0x0 0x08af8800 0x0 0x400&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_SYS_NOC_USB0_AXI_CLK&gt;,</div><div class='add'>+				&lt;&amp;gcc GCC_USB0_MASTER_CLK&gt;,</div><div class='add'>+				&lt;&amp;gcc GCC_USB0_SLEEP_CLK&gt;,</div><div class='add'>+				&lt;&amp;gcc GCC_USB0_MOCK_UTMI_CLK&gt;;</div><div class='add'>+			clock-names = "cfg_noc",</div><div class='add'>+				"core",</div><div class='add'>+				"sleep",</div><div class='add'>+				"mock_utmi";</div><div class='add'>+</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_SYS_NOC_USB0_AXI_CLK&gt;,</div><div class='add'>+					  &lt;&amp;gcc GCC_USB0_MASTER_CLK&gt;,</div><div class='add'>+					  &lt;&amp;gcc GCC_USB0_MOCK_UTMI_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;133330000&gt;,</div><div class='add'>+					       &lt;133330000&gt;,</div><div class='add'>+					       &lt;24000000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "pwr_event",</div><div class='add'>+					  "qusb2_phy",</div><div class='add'>+					  "ss_phy_irq";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_USB0_BCR&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='add'>+</div><div class='add'>+			dwc_0: usb@8a00000 {</div><div class='add'>+				compatible = "snps,dwc3";</div><div class='add'>+				reg = &lt;0x0 0x08a00000 0x0 0xcd00&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				phys = &lt;&amp;qusb_phy_0&gt;, &lt;&amp;ssphy_0&gt;;</div><div class='add'>+				phy-names = "usb2-phy", "usb3-phy";</div><div class='add'>+				clocks = &lt;&amp;xo&gt;;</div><div class='add'>+				clock-names = "ref";</div><div class='add'>+				tx-fifo-resize;</div><div class='add'>+				snps,parkmode-disable-ss-quirk;</div><div class='add'>+				snps,is-utmi-l1-suspend;</div><div class='add'>+				snps,hird-threshold = /bits/ 8 &lt;0x0&gt;;</div><div class='add'>+				snps,dis_u2_susphy_quirk;</div><div class='add'>+				snps,dis_u3_susphy_quirk;</div><div class='add'>+				dr_mode = "host";</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		intc: interrupt-controller@b000000 {</div><div class='ctx'> 			compatible = "qcom,msm-qgic2";</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='ctx'> 			interrupt-controller;</div><div class='del'>-			#interrupt-cells = &lt;0x3&gt;;</div><div class='del'>-			reg =   &lt;0x0b000000 0x1000&gt;,  /*GICD*/</div><div class='del'>-				&lt;0x0b002000 0x1000&gt;,  /*GICC*/</div><div class='del'>-				&lt;0x0b001000 0x1000&gt;,  /*GICH*/</div><div class='del'>-				&lt;0x0b004000 0x1000&gt;;  /*GICV*/</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			reg = &lt;0x0 0x0b000000 0x0 0x1000&gt;,  /*GICD*/</div><div class='add'>+			      &lt;0x0 0x0b002000 0x0 0x1000&gt;,  /*GICC*/</div><div class='add'>+			      &lt;0x0 0x0b001000 0x0 0x1000&gt;,  /*GICH*/</div><div class='add'>+			      &lt;0x0 0x0b004000 0x0 0x1000&gt;;  /*GICV*/</div><div class='ctx'> 			interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			ranges = &lt;0 0 0 0xb00a000 0 0xffd&gt;;</div><div class='add'>+</div><div class='add'>+			v2m@0 {</div><div class='add'>+				compatible = "arm,gic-v2m-frame";</div><div class='add'>+				msi-controller;</div><div class='add'>+				reg = &lt;0x0 0x0 0x0 0xffd&gt;;</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		watchdog@b017000 {</div><div class='ctx'> 			compatible = "qcom,kpss-wdt";</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 3 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='del'>-			reg = &lt;0x0b017000 0x40&gt;;</div><div class='add'>+			reg = &lt;0x0 0x0b017000 0x0 0x40&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;sleep_clk&gt;;</div><div class='ctx'> 			timeout-sec = &lt;10&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		apcs_glb: mailbox@b111000 {</div><div class='del'>-			compatible = "qcom,ipq8074-apcs-apps-global";</div><div class='del'>-			reg = &lt;0x0b111000 0xc&gt;;</div><div class='del'>-</div><div class='add'>+			compatible = "qcom,ipq6018-apcs-apps-global";</div><div class='add'>+			reg = &lt;0x0 0x0b111000 0x0 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;a53pll&gt;, &lt;&amp;xo&gt;, &lt;&amp;gcc GPLL0&gt;;</div><div class='add'>+			clock-names = "pll", "xo", "gpll0";</div><div class='ctx'> 			#mbox-cells = &lt;1&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		timer {</div><div class='del'>-			compatible = "arm,armv8-timer";</div><div class='del'>-			interrupts = &lt;GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='del'>-				     &lt;GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='del'>-				     &lt;GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='del'>-				     &lt;GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+		a53pll: clock@b116000 {</div><div class='add'>+			compatible = "qcom,ipq6018-a53pll";</div><div class='add'>+			reg = &lt;0x0 0x0b116000 0x0 0x40&gt;;</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clocks = &lt;&amp;xo&gt;;</div><div class='add'>+			clock-names = "xo";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		timer@b120000 {</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;1&gt;;</div><div class='del'>-			ranges;</div><div class='add'>+			ranges = &lt;0 0 0 0x10000000&gt;;</div><div class='ctx'> 			compatible = "arm,armv7-timer-mem";</div><div class='del'>-			reg = &lt;0x0b120000 0x1000&gt;;</div><div class='del'>-			clock-frequency = &lt;19200000&gt;;</div><div class='add'>+			reg = &lt;0x0 0x0b120000 0x0 0x1000&gt;;</div><div class='ctx'> </div><div class='ctx'> 			frame@b120000 {</div><div class='ctx'> 				frame-number = &lt;0&gt;;</div><div class='hunk'>@@ -327,7 +773,7 @@</div><div class='ctx'> 			frame@b123000 {</div><div class='ctx'> 				frame-number = &lt;1&gt;;</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-				reg = &lt;0xb123000 0x1000&gt;;</div><div class='add'>+				reg = &lt;0x0b123000 0x1000&gt;;</div><div class='ctx'> 				status = "disabled";</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='hunk'>@@ -368,9 +814,9 @@</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='ctx'> 		q6v5_wcss: remoteproc@cd00000 {</div><div class='del'>-			compatible = "qcom,ipq8074-wcss-pil";</div><div class='del'>-			reg = &lt;0x0cd00000 0x4040&gt;,</div><div class='del'>-				&lt;0x004ab000 0x20&gt;;</div><div class='add'>+			compatible = "qcom,ipq6018-wcss-pil";</div><div class='add'>+			reg = &lt;0x0 0x0cd00000 0x0 0x4040&gt;,</div><div class='add'>+			      &lt;0x0 0x004ab000 0x0 0x20&gt;;</div><div class='ctx'> 			reg-names = "qdsp6",</div><div class='ctx'> 				    "rmb";</div><div class='ctx'> 			interrupts-extended = &lt;&amp;intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='hunk'>@@ -395,7 +841,7 @@</div><div class='ctx'> 			clocks = &lt;&amp;gcc GCC_PRNG_AHB_CLK&gt;;</div><div class='ctx'> 			clock-names = "prng";</div><div class='ctx'> </div><div class='del'>-			qcom,halt-regs = &lt;&amp;tcsr_q6 0xa000 0xd000 0x0&gt;;</div><div class='add'>+			qcom,halt-regs = &lt;&amp;tcsr 0x18000 0x1b000 0xe000&gt;;</div><div class='ctx'> </div><div class='ctx'> 			qcom,smem-states = &lt;&amp;wcss_smp2p_out 0&gt;,</div><div class='ctx'> 					   &lt;&amp;wcss_smp2p_out 1&gt;;</div><div class='hunk'>@@ -406,6 +852,7 @@</div><div class='ctx'> </div><div class='ctx'> 			glink-edge {</div><div class='ctx'> 				interrupts = &lt;GIC_SPI 321 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				label = "rtr";</div><div class='ctx'> 				qcom,remote-pid = &lt;1&gt;;</div><div class='ctx'> 				mboxes = &lt;&amp;apcs_glb 8&gt;;</div><div class='ctx'> </div><div class='hunk'>@@ -415,6 +862,213 @@</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		pcie0: pcie@20000000 {</div><div class='add'>+			compatible = "qcom,pcie-ipq6018";</div><div class='add'>+			reg = &lt;0x0 0x20000000 0x0 0xf1d&gt;,</div><div class='add'>+			      &lt;0x0 0x20000f20 0x0 0xa8&gt;,</div><div class='add'>+			      &lt;0x0 0x20001000 0x0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0x80000 0x0 0x4000&gt;,</div><div class='add'>+			      &lt;0x0 0x20100000 0x0 0x1000&gt;;</div><div class='add'>+			reg-names = "dbi", "elbi", "atu", "parf", "config";</div><div class='add'>+</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			linux,pci-domain = &lt;0&gt;;</div><div class='add'>+			bus-range = &lt;0x00 0xff&gt;;</div><div class='add'>+			num-lanes = &lt;1&gt;;</div><div class='add'>+			max-link-speed = &lt;3&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;pcie_phy&gt;;</div><div class='add'>+			phy-names = "pciephy";</div><div class='add'>+</div><div class='add'>+			ranges = &lt;0x81000000 0x0 0x00000000 0x0 0x20200000 0x0 0x10000&gt;,</div><div class='add'>+				 &lt;0x82000000 0x0 0x20220000 0x0 0x20220000 0x0 0xfde0000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "msi0",</div><div class='add'>+					  "msi1",</div><div class='add'>+					  "msi2",</div><div class='add'>+					  "msi3",</div><div class='add'>+					  "msi4",</div><div class='add'>+					  "msi5",</div><div class='add'>+					  "msi6",</div><div class='add'>+					  "msi7",</div><div class='add'>+					  "global";</div><div class='add'>+</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0x7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;intc 0 0 GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH&gt;, /* int_a */</div><div class='add'>+					&lt;0 0 0 2 &amp;intc 0 0 GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH&gt;, /* int_b */</div><div class='add'>+					&lt;0 0 0 3 &amp;intc 0 0 GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH&gt;, /* int_c */</div><div class='add'>+					&lt;0 0 0 4 &amp;intc 0 0 GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH&gt;; /* int_d */</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_SYS_NOC_PCIE0_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AXI_M_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AXI_S_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AXI_S_BRIDGE_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc PCIE0_RCHNG_CLK&gt;;</div><div class='add'>+			clock-names = "iface",</div><div class='add'>+				      "axi_m",</div><div class='add'>+				      "axi_s",</div><div class='add'>+				      "axi_bridge",</div><div class='add'>+				      "rchng";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_PCIE0_PIPE_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_SLEEP_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_CORE_STICKY_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AXI_MASTER_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AXI_SLAVE_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AHB_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES&gt;;</div><div class='add'>+			reset-names = "pipe",</div><div class='add'>+				      "sleep",</div><div class='add'>+				      "sticky",</div><div class='add'>+				      "axi_m",</div><div class='add'>+				      "axi_s",</div><div class='add'>+				      "ahb",</div><div class='add'>+				      "axi_m_sticky",</div><div class='add'>+				      "axi_s_sticky";</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcie@0 {</div><div class='add'>+				device_type = "pci";</div><div class='add'>+				reg = &lt;0x0 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+				bus-range = &lt;0x01 0xff&gt;;</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;3&gt;;</div><div class='add'>+				#size-cells = &lt;2&gt;;</div><div class='add'>+				ranges;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	thermal-zones {</div><div class='add'>+		nss-top-thermal {</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 4&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				nss-top-critical {</div><div class='add'>+					temperature = &lt;125000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nss-thermal {</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 5&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				nss-critical {</div><div class='add'>+					temperature = &lt;125000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wcss-phya0-thermal {</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 7&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				wcss-phya0-critical {</div><div class='add'>+					temperature = &lt;125000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wcss-phya1-thermal {</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			polling-delay = &lt;1000&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 8&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				wcss-phya1-critical {</div><div class='add'>+					temperature = &lt;125000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu-thermal {</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 13&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu-critical {</div><div class='add'>+					temperature = &lt;125000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu_alert: cpu-passive {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu_alert&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		lpass-thermal {</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 14&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				lpass-critical {</div><div class='add'>+					temperature = &lt;125000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ddrss-top-thermal {</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 15&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				ddrss-top-critical {</div><div class='add'>+					temperature = &lt;125000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	wcss: wcss-smp2p {</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts<br/>index 70be3f95209b..5cf07caf4103 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/ipq8074-hk01.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/ipq8074-hk01.dts</a></div><div class='hunk'>@@ -1,15 +1,15 @@</div><div class='ctx'> // SPDX-License-Identifier: GPL-2.0-only</div><div class='ctx'> /dts-v1/;</div><div class='del'>-/* Copyright (c) 2017, The Linux Foundation. All rights reserved.</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> #include "ipq8074.dtsi"</div><div class='add'>+#include "pmp8074.dtsi"</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='del'>-	#address-cells = &lt;0x2&gt;;</div><div class='del'>-	#size-cells = &lt;0x2&gt;;</div><div class='ctx'> 	model = "Qualcomm Technologies, Inc. IPQ8074-HK01";</div><div class='ctx'> 	compatible = "qcom,ipq8074-hk01", "qcom,ipq8074";</div><div class='del'>-	interrupt-parent = &lt;&amp;intc&gt;;</div><div class='ctx'> </div><div class='ctx'> 	aliases {</div><div class='ctx'> 		serial0 = &amp;blsp1_uart5;</div><div class='hunk'>@@ -20,67 +20,100 @@</div><div class='ctx'> 		stdout-path = "serial0";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	memory {</div><div class='add'>+	memory@40000000 {</div><div class='ctx'> 		device_type = "memory";</div><div class='ctx'> 		reg = &lt;0x0 0x40000000 0x0 0x20000000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	soc {</div><div class='del'>-		serial@78b3000 {</div><div class='del'>-			status = "ok";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		spi@78b5000 {</div><div class='del'>-			status = "ok";</div><div class='del'>-</div><div class='del'>-			m25p80@0 {</div><div class='del'>-				  #address-cells = &lt;1&gt;;</div><div class='del'>-				  #size-cells = &lt;1&gt;;</div><div class='del'>-				  compatible = "jedec,spi-nor";</div><div class='del'>-				  reg = &lt;0&gt;;</div><div class='del'>-				  spi-max-frequency = &lt;50000000&gt;;</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		serial@78b1000 {</div><div class='del'>-			 status = "ok";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		i2c@78b6000 {</div><div class='del'>-			 status = "ok";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		dma@7984000 {</div><div class='del'>-			 status = "ok";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		nand@79b0000 {</div><div class='del'>-			status = "ok";</div><div class='del'>-</div><div class='del'>-			nand@0 {</div><div class='del'>-				reg = &lt;0&gt;;</div><div class='del'>-				nand-ecc-strength = &lt;4&gt;;</div><div class='del'>-				nand-ecc-step-size = &lt;512&gt;;</div><div class='del'>-				nand-bus-width = &lt;8&gt;;</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		phy@86000 {</div><div class='del'>-			status = "ok";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		phy@8e000 {</div><div class='del'>-			status = "ok";</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		pci@20000000 {</div><div class='del'>-			status = "ok";</div><div class='del'>-			perst-gpio = &lt;&amp;tlmm 58 0x1&gt;;</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		pci@10000000 {</div><div class='del'>-			status = "ok";</div><div class='del'>-			perst-gpio = &lt;&amp;tlmm 61 0x1&gt;;</div><div class='del'>-		};</div><div class='add'>+	vreg_dummy: regulator-dummy { };</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp1_i2c2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp1_spi1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash@0 {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;50000000&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='add'>+</div><div class='add'>+&amp;blsp1_uart3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp1_uart5 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	perst-gpios = &lt;&amp;tlmm 61 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	perst-gpios = &lt;&amp;tlmm 58 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_qmp0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_qmp1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qpic_bam {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qpic_nand {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	nand@0 {</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		nand-ecc-strength = &lt;4&gt;;</div><div class='add'>+		nand-ecc-step-size = &lt;512&gt;;</div><div class='add'>+		nand-bus-width = &lt;8&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sdhc_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	vqmmc-supply = &lt;&amp;l11&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qusb_phy_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qusb_phy_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ssphy_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	vdda-phy-supply = &lt;&amp;vreg_dummy&gt;;</div><div class='add'>+	vdda-pll-supply = &lt;&amp;vreg_dummy&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ssphy_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	vdda-phy-supply = &lt;&amp;vreg_dummy&gt;;</div><div class='add'>+	vdda-pll-supply = &lt;&amp;vreg_dummy&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts<br/>new file mode 100644<br/>index 000000000000..cc1992ca0519<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts</a></div><div class='hunk'>@@ -0,0 +1,12 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2020 The Linux Foundation. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "ipq8074-hk10.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Qualcomm Technologies, Inc. IPQ8074/AP-HK10-C1";</div><div class='add'>+	compatible = "qcom,ipq8074-hk10-c1", "qcom,ipq8074";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts<br/>new file mode 100644<br/>index 000000000000..d7f0efda6b8e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts</a></div><div class='hunk'>@@ -0,0 +1,11 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/dts-v1/;</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2020 The Linux Foundation. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+#include "ipq8074-hk10.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Qualcomm Technologies, Inc. IPQ8074/AP-HK10-C2";</div><div class='add'>+	compatible = "qcom,ipq8074-hk10-c2", "qcom,ipq8074";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi<br/>new file mode 100644<br/>index 000000000000..34e2f80514a3<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi</a></div><div class='hunk'>@@ -0,0 +1,72 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "ipq8074.dtsi"</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;blsp1_uart5;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x40000000 0x0 0x20000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp1_spi1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash@0 {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		compatible = "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		spi-max-frequency = &lt;50000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp1_uart5 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	perst-gpios = &lt;&amp;tlmm 58 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	perst-gpios = &lt;&amp;tlmm 61 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_qmp0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie_qmp1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qpic_bam {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qpic_nand {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	nand@0 {</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		nand-ecc-strength = &lt;4&gt;;</div><div class='add'>+		nand-ecc-step-size = &lt;512&gt;;</div><div class='add'>+		nand-bus-width = &lt;8&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi<br/>index 2b31823d3ccd..256e12cf6d54 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/ipq8074.dtsi?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/ipq8074.dtsi</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/ipq8074.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/ipq8074.dtsi</a></div><div class='hunk'>@@ -7,161 +7,433 @@</div><div class='ctx'> #include &lt;dt-bindings/clock/qcom,gcc-ipq8074.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='ctx'> 	model = "Qualcomm Technologies, Inc. IPQ8074";</div><div class='ctx'> 	compatible = "qcom,ipq8074";</div><div class='add'>+	interrupt-parent = &lt;&amp;intc&gt;;</div><div class='add'>+</div><div class='add'>+	clocks {</div><div class='add'>+		sleep_clk: sleep_clk {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			clock-frequency = &lt;32768&gt;;</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		xo: xo {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			clock-frequency = &lt;19200000&gt;;</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			reg = &lt;0x0&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@1 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			reg = &lt;0x1&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@2 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			reg = &lt;0x2&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@3 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a53";</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			reg = &lt;0x3&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_0: l2-cache {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu {</div><div class='add'>+		compatible = "arm,cortex-a53-pmu";</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-1.0";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		bootloader@4a600000 {</div><div class='add'>+			reg = &lt;0x0 0x4a600000 0x0 0x400000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sbl@4aa00000 {</div><div class='add'>+			reg = &lt;0x0 0x4aa00000 0x0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smem@4ab00000 {</div><div class='add'>+			compatible = "qcom,smem";</div><div class='add'>+			reg = &lt;0x0 0x4ab00000 0x0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+</div><div class='add'>+			hwlocks = &lt;&amp;tcsr_mutex 3&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		memory@4ac00000 {</div><div class='add'>+			reg = &lt;0x0 0x4ac00000 0x0 0x400000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	firmware {</div><div class='add'>+		scm {</div><div class='add'>+			compatible = "qcom,scm-ipq8074", "qcom,scm";</div><div class='add'>+			qcom,dload-mode = &lt;&amp;tcsr 0x6100&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-	soc: soc {</div><div class='del'>-		#address-cells = &lt;0x1&gt;;</div><div class='del'>-		#size-cells = &lt;0x1&gt;;</div><div class='add'>+	soc: soc@0 {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='ctx'> 		ranges = &lt;0 0 0 0xffffffff&gt;;</div><div class='ctx'> 		compatible = "simple-bus";</div><div class='ctx'> </div><div class='add'>+		ssphy_1: phy@58000 {</div><div class='add'>+			compatible = "qcom,ipq8074-qmp-usb3-phy";</div><div class='add'>+			reg = &lt;0x00058000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_USB1_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;xo&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB1_PHY_CFG_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB1_PIPE_CLK&gt;;</div><div class='add'>+			clock-names = "aux",</div><div class='add'>+				      "ref",</div><div class='add'>+				      "cfg_ahb",</div><div class='add'>+				      "pipe";</div><div class='add'>+			clock-output-names = "usb3phy_1_cc_pipe_clk";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_USB1_PHY_BCR&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB3PHY_1_PHY_BCR&gt;;</div><div class='add'>+			reset-names = "phy",</div><div class='add'>+				      "phy_phy";</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qusb_phy_1: phy@59000 {</div><div class='add'>+			compatible = "qcom,ipq8074-qusb2-phy";</div><div class='add'>+			reg = &lt;0x00059000 0x180&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_USB1_PHY_CFG_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;xo&gt;;</div><div class='add'>+			clock-names = "cfg_ahb", "ref";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_QUSB2_1_PHY_BCR&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ssphy_0: phy@78000 {</div><div class='add'>+			compatible = "qcom,ipq8074-qmp-usb3-phy";</div><div class='add'>+			reg = &lt;0x00078000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_USB0_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;xo&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB0_PHY_CFG_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB0_PIPE_CLK&gt;;</div><div class='add'>+			clock-names = "aux",</div><div class='add'>+				      "ref",</div><div class='add'>+				      "cfg_ahb",</div><div class='add'>+				      "pipe";</div><div class='add'>+			clock-output-names = "usb3phy_0_cc_pipe_clk";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_USB0_PHY_BCR&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB3PHY_0_PHY_BCR&gt;;</div><div class='add'>+			reset-names = "phy",</div><div class='add'>+				      "phy_phy";</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qusb_phy_0: phy@79000 {</div><div class='add'>+			compatible = "qcom,ipq8074-qusb2-phy";</div><div class='add'>+			reg = &lt;0x00079000 0x180&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_USB0_PHY_CFG_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;xo&gt;;</div><div class='add'>+			clock-names = "cfg_ahb", "ref";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_QUSB2_0_PHY_BCR&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie_qmp0: phy@84000 {</div><div class='add'>+			compatible = "qcom,ipq8074-qmp-gen3-pcie-phy";</div><div class='add'>+			reg = &lt;0x00084000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_PCIE0_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_PIPE_CLK&gt;;</div><div class='add'>+			clock-names = "aux",</div><div class='add'>+				      "cfg_ahb",</div><div class='add'>+				      "pipe";</div><div class='add'>+</div><div class='add'>+			clock-output-names = "pcie20_phy0_pipe_clk";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_PCIE0_PHY_BCR&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0PHY_PHY_BCR&gt;;</div><div class='add'>+			reset-names = "phy",</div><div class='add'>+				      "common";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie_qmp1: phy@8e000 {</div><div class='add'>+			compatible = "qcom,ipq8074-qmp-pcie-phy";</div><div class='add'>+			reg = &lt;0x0008e000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_PCIE1_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_PIPE_CLK&gt;;</div><div class='add'>+			clock-names = "aux",</div><div class='add'>+				      "cfg_ahb",</div><div class='add'>+				      "pipe";</div><div class='add'>+</div><div class='add'>+			clock-output-names = "pcie20_phy1_pipe_clk";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_PCIE1_PHY_BCR&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1PHY_PHY_BCR&gt;;</div><div class='add'>+			reset-names = "phy",</div><div class='add'>+				      "common";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio: mdio@90000 {</div><div class='add'>+			compatible = "qcom,ipq8074-mdio", "qcom,ipq4019-mdio";</div><div class='add'>+			reg = &lt;0x00090000 0x64&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_MDIO_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "gcc_mdio_ahb_clk";</div><div class='add'>+</div><div class='add'>+			clock-frequency = &lt;6250000&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qfprom: efuse@a4000 {</div><div class='add'>+			compatible = "qcom,ipq8074-qfprom", "qcom,qfprom";</div><div class='add'>+			reg = &lt;0x000a4000 0x2000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		prng: rng@e3000 {</div><div class='add'>+			compatible = "qcom,prng-ee";</div><div class='add'>+			reg = &lt;0x000e3000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_PRNG_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "core";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tsens: thermal-sensor@4a9000 {</div><div class='add'>+			compatible = "qcom,ipq8074-tsens";</div><div class='add'>+			reg = &lt;0x4a9000 0x1000&gt;, /* TM */</div><div class='add'>+			      &lt;0x4a8000 0x1000&gt;; /* SROT */</div><div class='add'>+			interrupts = &lt;GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "combined";</div><div class='add'>+			#qcom,sensors = &lt;16&gt;;</div><div class='add'>+			#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cryptobam: dma-controller@704000 {</div><div class='add'>+			compatible = "qcom,bam-v1.7.0";</div><div class='add'>+			reg = &lt;0x00704000 0x20000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_CRYPTO_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "bam_clk";</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+			qcom,ee = &lt;1&gt;;</div><div class='add'>+			qcom,controlled-remotely;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		crypto: crypto@73a000 {</div><div class='add'>+			compatible = "qcom,crypto-v5.1";</div><div class='add'>+			reg = &lt;0x0073a000 0x6000&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_CRYPTO_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_CRYPTO_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_CRYPTO_CLK&gt;;</div><div class='add'>+			clock-names = "iface", "bus", "core";</div><div class='add'>+			dmas = &lt;&amp;cryptobam 2&gt;, &lt;&amp;cryptobam 3&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		tlmm: pinctrl@1000000 {</div><div class='ctx'> 			compatible = "qcom,ipq8074-pinctrl";</div><div class='del'>-			reg = &lt;0x1000000 0x300000&gt;;</div><div class='add'>+			reg = &lt;0x01000000 0x300000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			gpio-controller;</div><div class='ctx'> 			gpio-ranges = &lt;&amp;tlmm 0 0 70&gt;;</div><div class='del'>-			#gpio-cells = &lt;0x2&gt;;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='ctx'> 			interrupt-controller;</div><div class='del'>-			#interrupt-cells = &lt;0x2&gt;;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='del'>-			serial_4_pins: serial4-pinmux {</div><div class='add'>+			serial_4_pins: serial4-state {</div><div class='ctx'> 				pins = "gpio23", "gpio24";</div><div class='ctx'> 				function = "blsp4_uart1";</div><div class='ctx'> 				drive-strength = &lt;8&gt;;</div><div class='ctx'> 				bias-disable;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			i2c_0_pins: i2c-0-pinmux {</div><div class='add'>+			serial_5_pins: serial5-state {</div><div class='add'>+				pins = "gpio9", "gpio16";</div><div class='add'>+				function = "blsp5_uart";</div><div class='add'>+				drive-strength = &lt;8&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c_0_pins: i2c-0-state {</div><div class='ctx'> 				pins = "gpio42", "gpio43";</div><div class='ctx'> 				function = "blsp1_i2c";</div><div class='ctx'> 				drive-strength = &lt;8&gt;;</div><div class='ctx'> 				bias-disable;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			spi_0_pins: spi-0-pins {</div><div class='add'>+			spi_0_pins: spi-0-state {</div><div class='ctx'> 				pins = "gpio38", "gpio39", "gpio40", "gpio41";</div><div class='ctx'> 				function = "blsp0_spi";</div><div class='ctx'> 				drive-strength = &lt;8&gt;;</div><div class='ctx'> 				bias-disable;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			hsuart_pins: hsuart-pins {</div><div class='add'>+			hsuart_pins: hsuart-state {</div><div class='ctx'> 				pins = "gpio46", "gpio47", "gpio48", "gpio49";</div><div class='ctx'> 				function = "blsp2_uart";</div><div class='ctx'> 				drive-strength = &lt;8&gt;;</div><div class='ctx'> 				bias-disable;</div><div class='ctx'> 			};</div><div class='ctx'> </div><div class='del'>-			qpic_pins: qpic-pins {</div><div class='add'>+			qpic_pins: qpic-state {</div><div class='ctx'> 				pins = "gpio1", "gpio3", "gpio4",</div><div class='ctx'> 				       "gpio5", "gpio6", "gpio7",</div><div class='ctx'> 				       "gpio8", "gpio10", "gpio11",</div><div class='ctx'> 				       "gpio12", "gpio13", "gpio14",</div><div class='del'>-				       "gpio15", "gpio16", "gpio17";</div><div class='add'>+				       "gpio15", "gpio17";</div><div class='ctx'> 				function = "qpic";</div><div class='ctx'> 				drive-strength = &lt;8&gt;;</div><div class='ctx'> 				bias-disable;</div><div class='ctx'> 			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		intc: interrupt-controller@b000000 {</div><div class='del'>-			compatible = "qcom,msm-qgic2";</div><div class='del'>-			interrupt-controller;</div><div class='del'>-			#interrupt-cells = &lt;0x3&gt;;</div><div class='del'>-			reg = &lt;0xb000000 0x1000&gt;, &lt;0xb002000 0x1000&gt;;</div><div class='add'>+		gcc: clock-controller@1800000 {</div><div class='add'>+			compatible = "qcom,gcc-ipq8074";</div><div class='add'>+			reg = &lt;0x01800000 0x80000&gt;;</div><div class='add'>+			clocks = &lt;&amp;xo&gt;,</div><div class='add'>+				 &lt;&amp;sleep_clk&gt;,</div><div class='add'>+				 &lt;&amp;pcie_qmp0&gt;,</div><div class='add'>+				 &lt;&amp;pcie_qmp1&gt;;</div><div class='add'>+			clock-names = "xo",</div><div class='add'>+				      "sleep_clk",</div><div class='add'>+				      "pcie0_pipe",</div><div class='add'>+				      "pcie1_pipe";</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		timer {</div><div class='del'>-			compatible = "arm,armv8-timer";</div><div class='del'>-			interrupts = &lt;GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='del'>-				     &lt;GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='del'>-				     &lt;GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='del'>-				     &lt;GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+		tcsr_mutex: hwlock@1905000 {</div><div class='add'>+			compatible = "qcom,tcsr-mutex";</div><div class='add'>+			reg = &lt;0x01905000 0x20000&gt;;</div><div class='add'>+			#hwlock-cells = &lt;1&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		timer@b120000 {</div><div class='del'>-			#address-cells = &lt;1&gt;;</div><div class='del'>-			#size-cells = &lt;1&gt;;</div><div class='del'>-			ranges;</div><div class='del'>-			compatible = "arm,armv7-timer-mem";</div><div class='del'>-			reg = &lt;0xb120000 0x1000&gt;;</div><div class='del'>-			clock-frequency = &lt;19200000&gt;;</div><div class='del'>-</div><div class='del'>-			frame@b120000 {</div><div class='del'>-				frame-number = &lt;0&gt;;</div><div class='del'>-				interrupts = &lt;GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='del'>-					     &lt;GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-				reg = &lt;0xb121000 0x1000&gt;,</div><div class='del'>-				      &lt;0xb122000 0x1000&gt;;</div><div class='del'>-			};</div><div class='del'>-</div><div class='del'>-			frame@b123000 {</div><div class='del'>-				frame-number = &lt;1&gt;;</div><div class='del'>-				interrupts = &lt;GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-				reg = &lt;0xb123000 0x1000&gt;;</div><div class='del'>-				status = "disabled";</div><div class='del'>-			};</div><div class='del'>-</div><div class='del'>-			frame@b124000 {</div><div class='del'>-				frame-number = &lt;2&gt;;</div><div class='del'>-				interrupts = &lt;GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-				reg = &lt;0xb124000 0x1000&gt;;</div><div class='del'>-				status = "disabled";</div><div class='del'>-			};</div><div class='del'>-</div><div class='del'>-			frame@b125000 {</div><div class='del'>-				frame-number = &lt;3&gt;;</div><div class='del'>-				interrupts = &lt;GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-				reg = &lt;0xb125000 0x1000&gt;;</div><div class='del'>-				status = "disabled";</div><div class='del'>-			};</div><div class='add'>+		tcsr: syscon@1937000 {</div><div class='add'>+			compatible = "qcom,tcsr-ipq8074", "syscon";</div><div class='add'>+			reg = &lt;0x01937000 0x21000&gt;;</div><div class='add'>+		};</div><div class='ctx'> </div><div class='del'>-			frame@b126000 {</div><div class='del'>-				frame-number = &lt;4&gt;;</div><div class='del'>-				interrupts = &lt;GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-				reg = &lt;0xb126000 0x1000&gt;;</div><div class='del'>-				status = "disabled";</div><div class='del'>-			};</div><div class='add'>+		spmi_bus: spmi@200f000 {</div><div class='add'>+			compatible = "qcom,spmi-pmic-arb";</div><div class='add'>+			reg = &lt;0x0200f000 0x001000&gt;,</div><div class='add'>+			      &lt;0x02400000 0x800000&gt;,</div><div class='add'>+			      &lt;0x02c00000 0x800000&gt;,</div><div class='add'>+			      &lt;0x03800000 0x200000&gt;,</div><div class='add'>+			      &lt;0x0200a000 0x000700&gt;;</div><div class='add'>+			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";</div><div class='add'>+			interrupts = &lt;GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "periph_irq";</div><div class='add'>+			qcom,ee = &lt;0&gt;;</div><div class='add'>+			qcom,channel = &lt;0&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;4&gt;;</div><div class='add'>+		};</div><div class='ctx'> </div><div class='del'>-			frame@b127000 {</div><div class='del'>-				frame-number = &lt;5&gt;;</div><div class='del'>-				interrupts = &lt;GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-				reg = &lt;0xb127000 0x1000&gt;;</div><div class='del'>-				status = "disabled";</div><div class='del'>-			};</div><div class='add'>+		sdhc_1: mmc@7824900 {</div><div class='add'>+			compatible = "qcom,ipq8074-sdhci", "qcom,sdhci-msm-v4";</div><div class='add'>+			reg = &lt;0x7824900 0x500&gt;, &lt;0x7824000 0x800&gt;;</div><div class='add'>+			reg-names = "hc", "core";</div><div class='ctx'> </div><div class='del'>-			frame@b128000 {</div><div class='del'>-				frame-number = &lt;6&gt;;</div><div class='del'>-				interrupts = &lt;GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-				reg = &lt;0xb128000 0x1000&gt;;</div><div class='del'>-				status = "disabled";</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='add'>+			interrupts = &lt;GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "hc_irq", "pwr_irq";</div><div class='ctx'> </div><div class='del'>-		gcc: gcc@1800000 {</div><div class='del'>-			compatible = "qcom,gcc-ipq8074";</div><div class='del'>-			reg = &lt;0x1800000 0x80000&gt;;</div><div class='del'>-			#clock-cells = &lt;0x1&gt;;</div><div class='del'>-			#reset-cells = &lt;0x1&gt;;</div><div class='del'>-		};</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_SDCC1_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_SDCC1_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;xo&gt;;</div><div class='add'>+			clock-names = "iface", "core", "xo";</div><div class='add'>+			resets = &lt;&amp;gcc GCC_SDCC1_BCR&gt;;</div><div class='add'>+			max-frequency = &lt;384000000&gt;;</div><div class='add'>+			mmc-ddr-1_8v;</div><div class='add'>+			mmc-hs200-1_8v;</div><div class='add'>+			mmc-hs400-1_8v;</div><div class='add'>+			bus-width = &lt;8&gt;;</div><div class='ctx'> </div><div class='del'>-		blsp1_uart5: serial@78b3000 {</div><div class='del'>-			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";</div><div class='del'>-			reg = &lt;0x78b3000 0x200&gt;;</div><div class='del'>-			interrupts = &lt;GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;gcc GCC_BLSP1_UART5_APPS_CLK&gt;,</div><div class='del'>-				 &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='del'>-			clock-names = "core", "iface";</div><div class='del'>-			pinctrl-0 = &lt;&amp;serial_4_pins&gt;;</div><div class='del'>-			pinctrl-names = "default";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		blsp_dma: dma@7884000 {</div><div class='add'>+		blsp_dma: dma-controller@7884000 {</div><div class='ctx'> 			compatible = "qcom,bam-v1.7.0";</div><div class='del'>-			reg = &lt;0x7884000 0x2b000&gt;;</div><div class='add'>+			reg = &lt;0x07884000 0x2b000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='ctx'> 			clock-names = "bam_clk";</div><div class='hunk'>@@ -171,7 +443,7 @@</div><div class='ctx'> </div><div class='ctx'> 		blsp1_uart1: serial@78af000 {</div><div class='ctx'> 			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";</div><div class='del'>-			reg = &lt;0x78af000 0x200&gt;;</div><div class='add'>+			reg = &lt;0x078af000 0x200&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;gcc GCC_BLSP1_UART1_APPS_CLK&gt;,</div><div class='ctx'> 				 &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='hunk'>@@ -181,7 +453,7 @@</div><div class='ctx'> </div><div class='ctx'> 		blsp1_uart3: serial@78b1000 {</div><div class='ctx'> 			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";</div><div class='del'>-			reg = &lt;0x78b1000 0x200&gt;;</div><div class='add'>+			reg = &lt;0x078b1000 0x200&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;gcc GCC_BLSP1_UART3_APPS_CLK&gt;,</div><div class='ctx'> 				&lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='hunk'>@@ -194,13 +466,36 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		blsp1_uart5: serial@78b3000 {</div><div class='add'>+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";</div><div class='add'>+			reg = &lt;0x078b3000 0x200&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_BLSP1_UART5_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "core", "iface";</div><div class='add'>+			pinctrl-0 = &lt;&amp;serial_4_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		blsp1_uart6: serial@78b4000 {</div><div class='add'>+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";</div><div class='add'>+			reg = &lt;0x078b4000 0x200&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_BLSP1_UART6_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "core", "iface";</div><div class='add'>+			pinctrl-0 = &lt;&amp;serial_5_pins&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='ctx'> 		blsp1_spi1: spi@78b5000 {</div><div class='ctx'> 			compatible = "qcom,spi-qup-v2.2.1";</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='del'>-			reg = &lt;0x78b5000 0x600&gt;;</div><div class='add'>+			reg = &lt;0x078b5000 0x600&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			spi-max-frequency = &lt;50000000&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;gcc GCC_BLSP1_QUP1_SPI_APPS_CLK&gt;,</div><div class='ctx'> 				&lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='ctx'> 			clock-names = "core", "iface";</div><div class='hunk'>@@ -215,14 +510,14 @@</div><div class='ctx'> 			compatible = "qcom,i2c-qup-v2.2.1";</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='del'>-			reg = &lt;0x78b6000 0x600&gt;;</div><div class='add'>+			reg = &lt;0x078b6000 0x600&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;,</div><div class='del'>-				&lt;&amp;gcc GCC_BLSP1_QUP2_I2C_APPS_CLK&gt;;</div><div class='del'>-			clock-names = "iface", "core";</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_BLSP1_QUP2_I2C_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "core", "iface";</div><div class='ctx'> 			clock-frequency = &lt;400000&gt;;</div><div class='del'>-			dmas = &lt;&amp;blsp_dma 15&gt;, &lt;&amp;blsp_dma 14&gt;;</div><div class='del'>-			dma-names = "rx", "tx";</div><div class='add'>+			dmas = &lt;&amp;blsp_dma 14&gt;, &lt;&amp;blsp_dma 15&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='ctx'> 			pinctrl-0 = &lt;&amp;i2c_0_pins&gt;;</div><div class='ctx'> 			pinctrl-names = "default";</div><div class='ctx'> 			status = "disabled";</div><div class='hunk'>@@ -232,20 +527,78 @@</div><div class='ctx'> 			compatible = "qcom,i2c-qup-v2.2.1";</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='del'>-			reg = &lt;0x78b7000 0x600&gt;;</div><div class='add'>+			reg = &lt;0x078b7000 0x600&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			clocks = &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;,</div><div class='del'>-				&lt;&amp;gcc GCC_BLSP1_QUP3_I2C_APPS_CLK&gt;;</div><div class='del'>-			clock-names = "iface", "core";</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_BLSP1_QUP3_I2C_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "core", "iface";</div><div class='ctx'> 			clock-frequency = &lt;100000&gt;;</div><div class='del'>-			dmas = &lt;&amp;blsp_dma 17&gt;, &lt;&amp;blsp_dma 16&gt;;</div><div class='del'>-			dma-names = "rx", "tx";</div><div class='add'>+			dmas = &lt;&amp;blsp_dma 16&gt;, &lt;&amp;blsp_dma 17&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		blsp1_spi4: spi@78b8000 {</div><div class='add'>+			compatible = "qcom,spi-qup-v2.2.1";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0x78b8000 0x600&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_BLSP1_QUP4_SPI_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "core", "iface";</div><div class='add'>+			dmas = &lt;&amp;blsp_dma 18&gt;, &lt;&amp;blsp_dma 19&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		qpic_bam: dma@7984000 {</div><div class='add'>+		blsp1_i2c5: i2c@78b9000 {</div><div class='add'>+			compatible = "qcom,i2c-qup-v2.2.1";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0x78b9000 0x600&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_BLSP1_QUP5_I2C_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "core", "iface";</div><div class='add'>+			clock-frequency = &lt;400000&gt;;</div><div class='add'>+			dmas = &lt;&amp;blsp_dma 20&gt;, &lt;&amp;blsp_dma 21&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		blsp1_spi5: spi@78b9000 {</div><div class='add'>+			compatible = "qcom,spi-qup-v2.2.1";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0x78b9000 0x600&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_BLSP1_QUP5_SPI_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "core", "iface";</div><div class='add'>+			dmas = &lt;&amp;blsp_dma 20&gt;, &lt;&amp;blsp_dma 21&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		blsp1_i2c6: i2c@78ba000 {</div><div class='add'>+			compatible = "qcom,i2c-qup-v2.2.1";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			reg = &lt;0x078ba000 0x600&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_BLSP1_QUP6_I2C_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "core", "iface";</div><div class='add'>+			clock-frequency = &lt;100000&gt;;</div><div class='add'>+			dmas = &lt;&amp;blsp_dma 22&gt;, &lt;&amp;blsp_dma 23&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qpic_bam: dma-controller@7984000 {</div><div class='ctx'> 			compatible = "qcom,bam-v1.7.0";</div><div class='del'>-			reg = &lt;0x7984000 0x1a000&gt;;</div><div class='add'>+			reg = &lt;0x07984000 0x1a000&gt;;</div><div class='ctx'> 			interrupts = &lt;GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;gcc GCC_QPIC_AHB_CLK&gt;;</div><div class='ctx'> 			clock-names = "bam_clk";</div><div class='hunk'>@@ -254,9 +607,9 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		qpic_nand: nand@79b0000 {</div><div class='add'>+		qpic_nand: nand-controller@79b0000 {</div><div class='ctx'> 			compatible = "qcom,ipq8074-nand";</div><div class='del'>-			reg = &lt;0x79b0000 0x10000&gt;;</div><div class='add'>+			reg = &lt;0x079b0000 0x10000&gt;;</div><div class='ctx'> 			#address-cells = &lt;1&gt;;</div><div class='ctx'> 			#size-cells = &lt;0&gt;;</div><div class='ctx'> 			clocks = &lt;&amp;gcc GCC_QPIC_CLK&gt;,</div><div class='hunk'>@@ -272,74 +625,274 @@</div><div class='ctx'> 			status = "disabled";</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		pcie_phy0: phy@86000 {</div><div class='del'>-			compatible = "qcom,ipq8074-qmp-pcie-phy";</div><div class='del'>-			reg = &lt;0x86000 0x1000&gt;;</div><div class='del'>-			#phy-cells = &lt;0&gt;;</div><div class='del'>-			clocks = &lt;&amp;gcc GCC_PCIE0_PIPE_CLK&gt;;</div><div class='del'>-			clock-names = "pipe_clk";</div><div class='del'>-			clock-output-names = "pcie20_phy0_pipe_clk";</div><div class='add'>+		usb_0: usb@8af8800 {</div><div class='add'>+			compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";</div><div class='add'>+			reg = &lt;0x08af8800 0x400&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='ctx'> </div><div class='del'>-			resets = &lt;&amp;gcc GCC_PCIE0_PHY_BCR&gt;,</div><div class='del'>-				&lt;&amp;gcc GCC_PCIE0PHY_PHY_BCR&gt;;</div><div class='del'>-			reset-names = "phy",</div><div class='del'>-				      "common";</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_SYS_NOC_USB0_AXI_CLK&gt;,</div><div class='add'>+				&lt;&amp;gcc GCC_USB0_MASTER_CLK&gt;,</div><div class='add'>+				&lt;&amp;gcc GCC_USB0_SLEEP_CLK&gt;,</div><div class='add'>+				&lt;&amp;gcc GCC_USB0_MOCK_UTMI_CLK&gt;;</div><div class='add'>+			clock-names = "cfg_noc",</div><div class='add'>+				"core",</div><div class='add'>+				"sleep",</div><div class='add'>+				"mock_utmi";</div><div class='add'>+</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_SYS_NOC_USB0_AXI_CLK&gt;,</div><div class='add'>+					  &lt;&amp;gcc GCC_USB0_MASTER_CLK&gt;,</div><div class='add'>+					  &lt;&amp;gcc GCC_USB0_MOCK_UTMI_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;133330000&gt;,</div><div class='add'>+						&lt;133330000&gt;,</div><div class='add'>+						&lt;19200000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "pwr_event",</div><div class='add'>+					  "qusb2_phy",</div><div class='add'>+					  "ss_phy_irq";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;gcc USB0_GDSC&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_USB0_BCR&gt;;</div><div class='ctx'> 			status = "disabled";</div><div class='add'>+</div><div class='add'>+			dwc_0: usb@8a00000 {</div><div class='add'>+				compatible = "snps,dwc3";</div><div class='add'>+				reg = &lt;0x8a00000 0xcd00&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				phys = &lt;&amp;qusb_phy_0&gt;, &lt;&amp;ssphy_0&gt;;</div><div class='add'>+				phy-names = "usb2-phy", "usb3-phy";</div><div class='add'>+				snps,parkmode-disable-ss-quirk;</div><div class='add'>+				snps,is-utmi-l1-suspend;</div><div class='add'>+				snps,hird-threshold = /bits/ 8 &lt;0x0&gt;;</div><div class='add'>+				snps,dis_u2_susphy_quirk;</div><div class='add'>+				snps,dis_u3_susphy_quirk;</div><div class='add'>+				dr_mode = "host";</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		pcie0: pci@20000000 {</div><div class='add'>+		usb_1: usb@8cf8800 {</div><div class='add'>+			compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";</div><div class='add'>+			reg = &lt;0x08cf8800 0x400&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_SYS_NOC_USB1_AXI_CLK&gt;,</div><div class='add'>+				&lt;&amp;gcc GCC_USB1_MASTER_CLK&gt;,</div><div class='add'>+				&lt;&amp;gcc GCC_USB1_SLEEP_CLK&gt;,</div><div class='add'>+				&lt;&amp;gcc GCC_USB1_MOCK_UTMI_CLK&gt;;</div><div class='add'>+			clock-names = "cfg_noc",</div><div class='add'>+				"core",</div><div class='add'>+				"sleep",</div><div class='add'>+				"mock_utmi";</div><div class='add'>+</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_SYS_NOC_USB1_AXI_CLK&gt;,</div><div class='add'>+					  &lt;&amp;gcc GCC_USB1_MASTER_CLK&gt;,</div><div class='add'>+					  &lt;&amp;gcc GCC_USB1_MOCK_UTMI_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;133330000&gt;,</div><div class='add'>+						&lt;133330000&gt;,</div><div class='add'>+						&lt;19200000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "pwr_event",</div><div class='add'>+					  "qusb2_phy",</div><div class='add'>+					  "ss_phy_irq";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;gcc USB1_GDSC&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_USB1_BCR&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			dwc_1: usb@8c00000 {</div><div class='add'>+				compatible = "snps,dwc3";</div><div class='add'>+				reg = &lt;0x8c00000 0xcd00&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				phys = &lt;&amp;qusb_phy_1&gt;, &lt;&amp;ssphy_1&gt;;</div><div class='add'>+				phy-names = "usb2-phy", "usb3-phy";</div><div class='add'>+				snps,parkmode-disable-ss-quirk;</div><div class='add'>+				snps,is-utmi-l1-suspend;</div><div class='add'>+				snps,hird-threshold = /bits/ 8 &lt;0x0&gt;;</div><div class='add'>+				snps,dis_u2_susphy_quirk;</div><div class='add'>+				snps,dis_u3_susphy_quirk;</div><div class='add'>+				dr_mode = "host";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		intc: interrupt-controller@b000000 {</div><div class='add'>+			compatible = "qcom,msm-qgic2";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			reg = &lt;0x0b000000 0x1000&gt;, &lt;0x0b002000 0x1000&gt;;</div><div class='add'>+			ranges = &lt;0 0xb00a000 0xffd&gt;;</div><div class='add'>+</div><div class='add'>+			v2m@0 {</div><div class='add'>+				compatible = "arm,gic-v2m-frame";</div><div class='add'>+				msi-controller;</div><div class='add'>+				reg = &lt;0x0 0xffd&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		watchdog: watchdog@b017000 {</div><div class='add'>+			compatible = "qcom,kpss-wdt";</div><div class='add'>+			reg = &lt;0xb017000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 3 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			clocks = &lt;&amp;sleep_clk&gt;;</div><div class='add'>+			timeout-sec = &lt;30&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		apcs_glb: mailbox@b111000 {</div><div class='add'>+			compatible = "qcom,ipq8074-apcs-apps-global",</div><div class='add'>+				     "qcom,ipq6018-apcs-apps-global";</div><div class='add'>+			reg = &lt;0x0b111000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;a53pll&gt;, &lt;&amp;xo&gt;, &lt;&amp;gcc GPLL0&gt;;</div><div class='add'>+			clock-names = "pll", "xo", "gpll0";</div><div class='add'>+</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#mbox-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		a53pll: clock@b116000 {</div><div class='add'>+			compatible = "qcom,ipq8074-a53pll";</div><div class='add'>+			reg = &lt;0x0b116000 0x40&gt;;</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clocks = &lt;&amp;xo&gt;;</div><div class='add'>+			clock-names = "xo";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		timer@b120000 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			compatible = "arm,armv7-timer-mem";</div><div class='add'>+			reg = &lt;0x0b120000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			frame@b120000 {</div><div class='add'>+				frame-number = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				reg = &lt;0x0b121000 0x1000&gt;,</div><div class='add'>+				      &lt;0x0b122000 0x1000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@b123000 {</div><div class='add'>+				frame-number = &lt;1&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				reg = &lt;0x0b123000 0x1000&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@b124000 {</div><div class='add'>+				frame-number = &lt;2&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				reg = &lt;0x0b124000 0x1000&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@b125000 {</div><div class='add'>+				frame-number = &lt;3&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				reg = &lt;0x0b125000 0x1000&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@b126000 {</div><div class='add'>+				frame-number = &lt;4&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				reg = &lt;0x0b126000 0x1000&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@b127000 {</div><div class='add'>+				frame-number = &lt;5&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				reg = &lt;0x0b127000 0x1000&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@b128000 {</div><div class='add'>+				frame-number = &lt;6&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				reg = &lt;0x0b128000 0x1000&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie1: pcie@10000000 {</div><div class='ctx'> 			compatible = "qcom,pcie-ipq8074";</div><div class='del'>-			reg =  &lt;0x20000000 0xf1d</div><div class='del'>-				0x20000f20 0xa8</div><div class='del'>-				0x80000 0x2000</div><div class='del'>-				0x20100000 0x1000&gt;;</div><div class='add'>+			reg = &lt;0x10000000 0xf1d&gt;,</div><div class='add'>+			      &lt;0x10000f20 0xa8&gt;,</div><div class='add'>+			      &lt;0x00088000 0x2000&gt;,</div><div class='add'>+			      &lt;0x10100000 0x1000&gt;;</div><div class='ctx'> 			reg-names = "dbi", "elbi", "parf", "config";</div><div class='ctx'> 			device_type = "pci";</div><div class='del'>-			linux,pci-domain = &lt;0&gt;;</div><div class='add'>+			linux,pci-domain = &lt;1&gt;;</div><div class='ctx'> 			bus-range = &lt;0x00 0xff&gt;;</div><div class='ctx'> 			num-lanes = &lt;1&gt;;</div><div class='add'>+			max-link-speed = &lt;2&gt;;</div><div class='ctx'> 			#address-cells = &lt;3&gt;;</div><div class='ctx'> 			#size-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='del'>-			phys = &lt;&amp;pcie_phy0&gt;;</div><div class='add'>+			phys = &lt;&amp;pcie_qmp1&gt;;</div><div class='ctx'> 			phy-names = "pciephy";</div><div class='ctx'> </div><div class='del'>-			ranges = &lt;0x81000000 0 0x20200000 0x20200000</div><div class='del'>-				  0 0x100000   /* downstream I/O */</div><div class='del'>-				  0x82000000 0 0x20300000 0x20300000</div><div class='del'>-				  0 0xd00000&gt;; /* non-prefetchable memory */</div><div class='add'>+			ranges = &lt;0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000&gt;,   /* I/O */</div><div class='add'>+				 &lt;0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000&gt;; /* MEM */</div><div class='ctx'> </div><div class='del'>-			interrupts = &lt;GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			interrupt-names = "msi";</div><div class='add'>+			interrupts = &lt;GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "msi0",</div><div class='add'>+					  "msi1",</div><div class='add'>+					  "msi2",</div><div class='add'>+					  "msi3",</div><div class='add'>+					  "msi4",</div><div class='add'>+					  "msi5",</div><div class='add'>+					  "msi6",</div><div class='add'>+					  "msi7",</div><div class='add'>+					  "global";</div><div class='ctx'> 			#interrupt-cells = &lt;1&gt;;</div><div class='ctx'> 			interrupt-map-mask = &lt;0 0 0 0x7&gt;;</div><div class='del'>-			interrupt-map = &lt;0 0 0 1 &amp;intc 0 75</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;intc 0 GIC_SPI 142</div><div class='ctx'> 					 IRQ_TYPE_LEVEL_HIGH&gt;, /* int_a */</div><div class='del'>-					&lt;0 0 0 2 &amp;intc 0 78</div><div class='add'>+					&lt;0 0 0 2 &amp;intc 0 GIC_SPI 143</div><div class='ctx'> 					 IRQ_TYPE_LEVEL_HIGH&gt;, /* int_b */</div><div class='del'>-					&lt;0 0 0 3 &amp;intc 0 79</div><div class='add'>+					&lt;0 0 0 3 &amp;intc 0 GIC_SPI 144</div><div class='ctx'> 					 IRQ_TYPE_LEVEL_HIGH&gt;, /* int_c */</div><div class='del'>-					&lt;0 0 0 4 &amp;intc 0 83</div><div class='add'>+					&lt;0 0 0 4 &amp;intc 0 GIC_SPI 145</div><div class='ctx'> 					 IRQ_TYPE_LEVEL_HIGH&gt;; /* int_d */</div><div class='ctx'> </div><div class='del'>-			clocks = &lt;&amp;gcc GCC_SYS_NOC_PCIE0_AXI_CLK&gt;,</div><div class='del'>-				 &lt;&amp;gcc GCC_PCIE0_AXI_M_CLK&gt;,</div><div class='del'>-				 &lt;&amp;gcc GCC_PCIE0_AXI_S_CLK&gt;,</div><div class='del'>-				 &lt;&amp;gcc GCC_PCIE0_AHB_CLK&gt;,</div><div class='del'>-				 &lt;&amp;gcc GCC_PCIE0_AUX_CLK&gt;;</div><div class='del'>-</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_SYS_NOC_PCIE1_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_AXI_M_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_AXI_S_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_AUX_CLK&gt;;</div><div class='ctx'> 			clock-names = "iface",</div><div class='ctx'> 				      "axi_m",</div><div class='ctx'> 				      "axi_s",</div><div class='ctx'> 				      "ahb",</div><div class='ctx'> 				      "aux";</div><div class='del'>-			resets = &lt;&amp;gcc GCC_PCIE0_PIPE_ARES&gt;,</div><div class='del'>-				 &lt;&amp;gcc GCC_PCIE0_SLEEP_ARES&gt;,</div><div class='del'>-				 &lt;&amp;gcc GCC_PCIE0_CORE_STICKY_ARES&gt;,</div><div class='del'>-				 &lt;&amp;gcc GCC_PCIE0_AXI_MASTER_ARES&gt;,</div><div class='del'>-				 &lt;&amp;gcc GCC_PCIE0_AXI_SLAVE_ARES&gt;,</div><div class='del'>-				 &lt;&amp;gcc GCC_PCIE0_AHB_ARES&gt;,</div><div class='del'>-				 &lt;&amp;gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES&gt;;</div><div class='add'>+			resets = &lt;&amp;gcc GCC_PCIE1_PIPE_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_SLEEP_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_CORE_STICKY_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_AXI_MASTER_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_AXI_SLAVE_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_AHB_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES&gt;;</div><div class='ctx'> 			reset-names = "pipe",</div><div class='ctx'> 				      "sleep",</div><div class='ctx'> 				      "sticky",</div><div class='hunk'>@@ -348,149 +901,285 @@</div><div class='ctx'> 				      "ahb",</div><div class='ctx'> 				      "axi_m_sticky";</div><div class='ctx'> 			status = "disabled";</div><div class='del'>-		};</div><div class='ctx'> </div><div class='del'>-		pcie_phy1: phy@8e000 {</div><div class='del'>-			compatible = "qcom,ipq8074-qmp-pcie-phy";</div><div class='del'>-			reg = &lt;0x8e000 0x1000&gt;;</div><div class='del'>-			#phy-cells = &lt;0&gt;;</div><div class='del'>-			clocks = &lt;&amp;gcc GCC_PCIE1_PIPE_CLK&gt;;</div><div class='del'>-			clock-names = "pipe_clk";</div><div class='del'>-			clock-output-names = "pcie20_phy1_pipe_clk";</div><div class='add'>+			pcie@0 {</div><div class='add'>+				device_type = "pci";</div><div class='add'>+				reg = &lt;0x0 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+				bus-range = &lt;0x01 0xff&gt;;</div><div class='ctx'> </div><div class='del'>-			resets = &lt;&amp;gcc GCC_PCIE1_PHY_BCR&gt;,</div><div class='del'>-				&lt;&amp;gcc GCC_PCIE1PHY_PHY_BCR&gt;;</div><div class='del'>-			reset-names = "phy",</div><div class='del'>-				      "common";</div><div class='del'>-			status = "disabled";</div><div class='add'>+				#address-cells = &lt;3&gt;;</div><div class='add'>+				#size-cells = &lt;2&gt;;</div><div class='add'>+				ranges;</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		pcie1: pci@10000000 {</div><div class='del'>-			compatible = "qcom,pcie-ipq8074";</div><div class='del'>-			reg =  &lt;0x10000000 0xf1d</div><div class='del'>-				0x10000f20 0xa8</div><div class='del'>-				0x88000 0x2000</div><div class='del'>-				0x10100000 0x1000&gt;;</div><div class='del'>-			reg-names = "dbi", "elbi", "parf", "config";</div><div class='add'>+		pcie0: pcie@20000000 {</div><div class='add'>+			compatible = "qcom,pcie-ipq8074-gen3";</div><div class='add'>+			reg = &lt;0x20000000 0xf1d&gt;,</div><div class='add'>+			      &lt;0x20000f20 0xa8&gt;,</div><div class='add'>+			      &lt;0x20001000 0x1000&gt;,</div><div class='add'>+			      &lt;0x00080000 0x4000&gt;,</div><div class='add'>+			      &lt;0x20100000 0x1000&gt;;</div><div class='add'>+			reg-names = "dbi", "elbi", "atu", "parf", "config";</div><div class='ctx'> 			device_type = "pci";</div><div class='del'>-			linux,pci-domain = &lt;1&gt;;</div><div class='add'>+			linux,pci-domain = &lt;0&gt;;</div><div class='ctx'> 			bus-range = &lt;0x00 0xff&gt;;</div><div class='ctx'> 			num-lanes = &lt;1&gt;;</div><div class='add'>+			max-link-speed = &lt;3&gt;;</div><div class='ctx'> 			#address-cells = &lt;3&gt;;</div><div class='ctx'> 			#size-cells = &lt;2&gt;;</div><div class='ctx'> </div><div class='del'>-			phys = &lt;&amp;pcie_phy1&gt;;</div><div class='add'>+			phys = &lt;&amp;pcie_qmp0&gt;;</div><div class='ctx'> 			phy-names = "pciephy";</div><div class='ctx'> </div><div class='del'>-			ranges = &lt;0x81000000 0 0x10200000 0x10200000</div><div class='del'>-				  0 0x100000   /* downstream I/O */</div><div class='del'>-				  0x82000000 0 0x10300000 0x10300000</div><div class='del'>-				  0 0xd00000&gt;; /* non-prefetchable memory */</div><div class='add'>+			ranges = &lt;0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000&gt;,   /* I/O */</div><div class='add'>+				 &lt;0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000&gt;; /* MEM */</div><div class='ctx'> </div><div class='del'>-			interrupts = &lt;GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='del'>-			interrupt-names = "msi";</div><div class='add'>+			interrupts = &lt;GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "msi0",</div><div class='add'>+					  "msi1",</div><div class='add'>+					  "msi2",</div><div class='add'>+					  "msi3",</div><div class='add'>+					  "msi4",</div><div class='add'>+					  "msi5",</div><div class='add'>+					  "msi6",</div><div class='add'>+					  "msi7",</div><div class='add'>+					  "global";</div><div class='ctx'> 			#interrupt-cells = &lt;1&gt;;</div><div class='ctx'> 			interrupt-map-mask = &lt;0 0 0 0x7&gt;;</div><div class='del'>-			interrupt-map = &lt;0 0 0 1 &amp;intc 0 142</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;intc 0 GIC_SPI 75</div><div class='ctx'> 					 IRQ_TYPE_LEVEL_HIGH&gt;, /* int_a */</div><div class='del'>-					&lt;0 0 0 2 &amp;intc 0 143</div><div class='add'>+					&lt;0 0 0 2 &amp;intc 0 GIC_SPI 78</div><div class='ctx'> 					 IRQ_TYPE_LEVEL_HIGH&gt;, /* int_b */</div><div class='del'>-					&lt;0 0 0 3 &amp;intc 0 144</div><div class='add'>+					&lt;0 0 0 3 &amp;intc 0 GIC_SPI 79</div><div class='ctx'> 					 IRQ_TYPE_LEVEL_HIGH&gt;, /* int_c */</div><div class='del'>-					&lt;0 0 0 4 &amp;intc 0 145</div><div class='add'>+					&lt;0 0 0 4 &amp;intc 0 GIC_SPI 83</div><div class='ctx'> 					 IRQ_TYPE_LEVEL_HIGH&gt;; /* int_d */</div><div class='ctx'> </div><div class='del'>-			clocks = &lt;&amp;gcc GCC_SYS_NOC_PCIE1_AXI_CLK&gt;,</div><div class='del'>-				 &lt;&amp;gcc GCC_PCIE1_AXI_M_CLK&gt;,</div><div class='del'>-				 &lt;&amp;gcc GCC_PCIE1_AXI_S_CLK&gt;,</div><div class='del'>-				 &lt;&amp;gcc GCC_PCIE1_AHB_CLK&gt;,</div><div class='del'>-				 &lt;&amp;gcc GCC_PCIE1_AUX_CLK&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_SYS_NOC_PCIE0_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AXI_M_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AXI_S_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AXI_S_BRIDGE_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_RCHNG_CLK&gt;;</div><div class='ctx'> 			clock-names = "iface",</div><div class='ctx'> 				      "axi_m",</div><div class='ctx'> 				      "axi_s",</div><div class='del'>-				      "ahb",</div><div class='del'>-				      "aux";</div><div class='del'>-			resets = &lt;&amp;gcc GCC_PCIE1_PIPE_ARES&gt;,</div><div class='del'>-				 &lt;&amp;gcc GCC_PCIE1_SLEEP_ARES&gt;,</div><div class='del'>-				 &lt;&amp;gcc GCC_PCIE1_CORE_STICKY_ARES&gt;,</div><div class='del'>-				 &lt;&amp;gcc GCC_PCIE1_AXI_MASTER_ARES&gt;,</div><div class='del'>-				 &lt;&amp;gcc GCC_PCIE1_AXI_SLAVE_ARES&gt;,</div><div class='del'>-				 &lt;&amp;gcc GCC_PCIE1_AHB_ARES&gt;,</div><div class='del'>-				 &lt;&amp;gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES&gt;;</div><div class='add'>+				      "axi_bridge",</div><div class='add'>+				      "rchng";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_PCIE0_PIPE_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_SLEEP_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_CORE_STICKY_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AXI_MASTER_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AXI_SLAVE_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AHB_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES&gt;;</div><div class='ctx'> 			reset-names = "pipe",</div><div class='ctx'> 				      "sleep",</div><div class='ctx'> 				      "sticky",</div><div class='ctx'> 				      "axi_m",</div><div class='ctx'> 				      "axi_s",</div><div class='ctx'> 				      "ahb",</div><div class='del'>-				      "axi_m_sticky";</div><div class='add'>+				      "axi_m_sticky",</div><div class='add'>+				      "axi_s_sticky";</div><div class='ctx'> 			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcie@0 {</div><div class='add'>+				device_type = "pci";</div><div class='add'>+				reg = &lt;0x0 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+				bus-range = &lt;0x01 0xff&gt;;</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;3&gt;;</div><div class='add'>+				#size-cells = &lt;2&gt;;</div><div class='add'>+				ranges;</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	cpus {</div><div class='del'>-		#address-cells = &lt;0x1&gt;;</div><div class='del'>-		#size-cells = &lt;0x0&gt;;</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		CPU0: cpu@0 {</div><div class='del'>-			device_type = "cpu";</div><div class='del'>-			compatible = "arm,cortex-a53";</div><div class='del'>-			reg = &lt;0x0&gt;;</div><div class='del'>-			next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='del'>-			enable-method = "psci";</div><div class='add'>+	thermal-zones {</div><div class='add'>+		nss-top-thermal {</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 4&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				nss-top-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		CPU1: cpu@1 {</div><div class='del'>-			device_type = "cpu";</div><div class='del'>-			compatible = "arm,cortex-a53";</div><div class='del'>-			enable-method = "psci";</div><div class='del'>-			reg = &lt;0x1&gt;;</div><div class='del'>-			next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='add'>+		nss0-thermal {</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 5&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				nss-0-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		CPU2: cpu@2 {</div><div class='del'>-			device_type = "cpu";</div><div class='del'>-			compatible = "arm,cortex-a53";</div><div class='del'>-			enable-method = "psci";</div><div class='del'>-			reg = &lt;0x2&gt;;</div><div class='del'>-			next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='add'>+		nss1-thermal {</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 6&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				nss-1-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		CPU3: cpu@3 {</div><div class='del'>-			device_type = "cpu";</div><div class='del'>-			compatible = "arm,cortex-a53";</div><div class='del'>-			enable-method = "psci";</div><div class='del'>-			reg = &lt;0x3&gt;;</div><div class='del'>-			next-level-cache = &lt;&amp;L2_0&gt;;</div><div class='add'>+		wcss-phya0-thermal {</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 7&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				wcss-phya0-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		L2_0: l2-cache {</div><div class='del'>-			compatible = "cache";</div><div class='del'>-			cache-level = &lt;0x2&gt;;</div><div class='add'>+		wcss-phya1-thermal {</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 8&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				wcss-phya1-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='del'>-	};</div><div class='ctx'> </div><div class='del'>-	psci {</div><div class='del'>-		compatible = "arm,psci-1.0";</div><div class='del'>-		method = "smc";</div><div class='del'>-	};</div><div class='add'>+		cpu0_thermal: cpu0-thermal {</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='ctx'> </div><div class='del'>-	pmu {</div><div class='del'>-		compatible = "arm,armv8-pmuv3";</div><div class='del'>-		interrupts = &lt;GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='del'>-	};</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 9&gt;;</div><div class='ctx'> </div><div class='del'>-	clocks {</div><div class='del'>-		sleep_clk: sleep_clk {</div><div class='del'>-			compatible = "fixed-clock";</div><div class='del'>-			clock-frequency = &lt;32000&gt;;</div><div class='del'>-			#clock-cells = &lt;0&gt;;</div><div class='add'>+			trips {</div><div class='add'>+				cpu0-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		xo: xo {</div><div class='del'>-			compatible = "fixed-clock";</div><div class='del'>-			clock-frequency = &lt;19200000&gt;;</div><div class='del'>-			#clock-cells = &lt;0&gt;;</div><div class='add'>+		cpu1_thermal: cpu1-thermal {</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 10&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu1-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2_thermal: cpu2-thermal {</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 11&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu2-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3_thermal: cpu3-thermal {</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 12&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu3-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cluster_thermal: cluster-thermal {</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 13&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cluster-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wcss-phyb0-thermal {</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 14&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				wcss-phyb0-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wcss-phyb1-thermal {</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 15&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				wcss-phyb1-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi<br/>new file mode 100644<br/>index 000000000000..bdb396afb992<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi</a></div><div class='hunk'>@@ -0,0 +1,240 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)</div><div class='add'>+/*</div><div class='add'>+ * IPQ9574 RDP board common device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include "ipq9574.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		serial0 = &amp;blsp1_uart2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	regulator_fixed_3p3: s3300 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-name = "fixed_3p3";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	regulator_fixed_0p925: s0925 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-min-microvolt = &lt;925000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;925000&gt;;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-name = "fixed_0p925";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+		pinctrl-0 = &lt;&amp;gpio_keys_default&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		button-wps {</div><div class='add'>+			label = "wps";</div><div class='add'>+			linux,code = &lt;KEY_WPS_BUTTON&gt;;</div><div class='add'>+			gpios = &lt;&amp;tlmm 37 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			debounce-interval = &lt;60&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+		pinctrl-0 = &lt;&amp;gpio_leds_default&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			function = LED_FUNCTION_WLAN;</div><div class='add'>+			gpios = &lt;&amp;tlmm 64 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,default-trigger = "phy0tx";</div><div class='add'>+			default-state = "off";</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp1_spi0 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;spi_0_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash@0 {</div><div class='add'>+		compatible = "micron,n25q128a11", "jedec,spi-nor";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		spi-max-frequency = &lt;50000000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp1_uart2 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;uart2_pins&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;rpm_requests {</div><div class='add'>+	regulators {</div><div class='add'>+		compatible = "qcom,rpm-mp5496-regulators";</div><div class='add'>+</div><div class='add'>+		ipq9574_s1: s1 {</div><div class='add'>+		/*</div><div class='add'>+		 * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.</div><div class='add'>+		 * During regulator registration, kernel not knowing the initial voltage,</div><div class='add'>+		 * considers it as zero and brings up the regulators with minimum supported voltage.</div><div class='add'>+		 * Update the regulator-min-microvolt with SVS voltage of 725mV so that</div><div class='add'>+		 * the regulators are brought up with 725mV which is sufficient for all the</div><div class='add'>+		 * corner parts to operate at 800MHz</div><div class='add'>+		 */</div><div class='add'>+			regulator-min-microvolt = &lt;725000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1075000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mp5496_l2: l2 {</div><div class='add'>+			regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+			regulator-always-on;</div><div class='add'>+			regulator-boot-on;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mp5496_l5: l5 {</div><div class='add'>+			regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+			regulator-always-on;</div><div class='add'>+			regulator-boot-on;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sleep_clk {</div><div class='add'>+	clock-frequency = &lt;32000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tlmm {</div><div class='add'>+	spi_0_pins: spi-0-state {</div><div class='add'>+		pins = "gpio11", "gpio12", "gpio13", "gpio14";</div><div class='add'>+		function = "blsp0_spi";</div><div class='add'>+		drive-strength = &lt;8&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio_keys_default: gpio-keys-default-state {</div><div class='add'>+		pins = "gpio37";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;8&gt;;</div><div class='add'>+		bias-pull-up;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio_leds_default: gpio-leds-default-state {</div><div class='add'>+		pins = "gpio64";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;8&gt;;</div><div class='add'>+		bias-pull-up;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	qpic_snand_default_state: qpic-snand-default-state {</div><div class='add'>+		clock-pins {</div><div class='add'>+			pins = "gpio5";</div><div class='add'>+			function = "qspi_clk";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cs-pins {</div><div class='add'>+			pins = "gpio4";</div><div class='add'>+			function = "qspi_cs";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		data-pins {</div><div class='add'>+			pins = "gpio0", "gpio1", "gpio2", "gpio3";</div><div class='add'>+			function = "qspi_data";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qpic_bam {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qpic_nand {</div><div class='add'>+	pinctrl-0 = &lt;&amp;qpic_snand_default_state&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	flash@0 {</div><div class='add'>+		compatible = "spi-nand";</div><div class='add'>+		reg = &lt;0&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		nand-ecc-engine = &lt;&amp;qpic_nand&gt;;</div><div class='add'>+		nand-ecc-strength = &lt;4&gt;;</div><div class='add'>+		nand-ecc-step-size = &lt;512&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_0_dwc3 {</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_0_qmpphy {</div><div class='add'>+	vdda-pll-supply = &lt;&amp;mp5496_l5&gt;;</div><div class='add'>+	vdda-phy-supply = &lt;&amp;regulator_fixed_0p925&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_0_qusbphy {</div><div class='add'>+	vdd-supply = &lt;&amp;regulator_fixed_0p925&gt;;</div><div class='add'>+	vdda-pll-supply = &lt;&amp;mp5496_l5&gt;;</div><div class='add'>+	vdda-phy-dpdm-supply = &lt;&amp;regulator_fixed_3p3&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * The bootstrap pins for the board select the XO clock frequency</div><div class='add'>+ * (48 MHZ or 96 MHZ used for different RDP type board). This setting</div><div class='add'>+ * automatically enables the right dividers, to ensure the reference</div><div class='add'>+ * clock output from WiFi to the CMN PLL is 48 MHZ.</div><div class='add'>+ */</div><div class='add'>+&amp;ref_48mhz_clk {</div><div class='add'>+	clock-div = &lt;1&gt;;</div><div class='add'>+	clock-mult = &lt;1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * The frequency of xo_board_clk is fixed to 24 MHZ, which is routed</div><div class='add'>+ * from WiFi output clock 48 MHZ divided by 2.</div><div class='add'>+ */</div><div class='add'>+&amp;xo_board_clk {</div><div class='add'>+	clock-div = &lt;2&gt;;</div><div class='add'>+	clock-mult = &lt;1&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xo_clk {</div><div class='add'>+	clock-frequency = &lt;48000000&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts<br/>new file mode 100644<br/>index 000000000000..f4f9199d4ab1<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts</a></div><div class='hunk'>@@ -0,0 +1,63 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)</div><div class='add'>+/*</div><div class='add'>+ * IPQ9574 RDP418 board device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "ipq9574-rdp-common.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C2";</div><div class='add'>+	compatible = "qcom,ipq9574-ap-al02-c2", "qcom,ipq9574";</div><div class='add'>+</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sdhc_1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdc_default_state&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	mmc-ddr-1_8v;</div><div class='add'>+	mmc-hs200-1_8v;</div><div class='add'>+	mmc-hs400-1_8v;</div><div class='add'>+	mmc-hs400-enhanced-strobe;</div><div class='add'>+	max-frequency = &lt;384000000&gt;;</div><div class='add'>+	bus-width = &lt;8&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tlmm {</div><div class='add'>+	sdc_default_state: sdc-default-state {</div><div class='add'>+		clk-pins {</div><div class='add'>+			pins = "gpio5";</div><div class='add'>+			function = "sdc_clk";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmd-pins {</div><div class='add'>+			pins = "gpio4";</div><div class='add'>+			function = "sdc_cmd";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		data-pins {</div><div class='add'>+			pins = "gpio0", "gpio1", "gpio2",</div><div class='add'>+			       "gpio3", "gpio6", "gpio7",</div><div class='add'>+			       "gpio8", "gpio9";</div><div class='add'>+			function = "sdc_data";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rclk-pins {</div><div class='add'>+			pins = "gpio10";</div><div class='add'>+			function = "sdc_rclk";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-down;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts<br/>new file mode 100644<br/>index 000000000000..5a546a14998b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts</a></div><div class='hunk'>@@ -0,0 +1,131 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)</div><div class='add'>+/*</div><div class='add'>+ * IPQ9574 RDP433 board device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include "ipq9574-rdp-common.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7";</div><div class='add'>+	compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie1_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pcie1_default&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	perst-gpios = &lt;&amp;tlmm 26 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	wake-gpios = &lt;&amp;tlmm 27 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie2_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie2 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pcie2_default&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	perst-gpios = &lt;&amp;tlmm 29 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	wake-gpios = &lt;&amp;tlmm 30 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie3_phy {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie3 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;pcie3_default&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	perst-gpios = &lt;&amp;tlmm 32 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	wake-gpios = &lt;&amp;tlmm 33 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tlmm {</div><div class='add'>+</div><div class='add'>+	pcie1_default: pcie1-default-state {</div><div class='add'>+		clkreq-n-pins {</div><div class='add'>+			pins = "gpio25";</div><div class='add'>+			function = "pcie1_clk";</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		perst-n-pins {</div><div class='add'>+			pins = "gpio26";</div><div class='add'>+			function = "gpio";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-down;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wake-n-pins {</div><div class='add'>+			pins = "gpio27";</div><div class='add'>+			function = "pcie1_wake";</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie2_default: pcie2-default-state {</div><div class='add'>+		clkreq-n-pins {</div><div class='add'>+			pins = "gpio28";</div><div class='add'>+			function = "pcie2_clk";</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		perst-n-pins {</div><div class='add'>+			pins = "gpio29";</div><div class='add'>+			function = "gpio";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-down;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wake-n-pins {</div><div class='add'>+			pins = "gpio30";</div><div class='add'>+			function = "pcie2_wake";</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie3_default: pcie3-default-state {</div><div class='add'>+		clkreq-n-pins {</div><div class='add'>+			pins = "gpio31";</div><div class='add'>+			function = "pcie3_clk";</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		perst-n-pins {</div><div class='add'>+			pins = "gpio32";</div><div class='add'>+			function = "gpio";</div><div class='add'>+			drive-strength = &lt;8&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+			output-low;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wake-n-pins {</div><div class='add'>+			pins = "gpio33";</div><div class='add'>+			function = "pcie3_wake";</div><div class='add'>+			drive-strength = &lt;6&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp449.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp449.dts<br/>new file mode 100644<br/>index 000000000000..d36d1078763e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/ipq9574-rdp449.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/ipq9574-rdp449.dts</a></div><div class='hunk'>@@ -0,0 +1,17 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)</div><div class='add'>+/*</div><div class='add'>+ * IPQ9574 RDP449 board device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "ipq9574-rdp-common.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C6";</div><div class='add'>+	compatible = "qcom,ipq9574-ap-al02-c6", "qcom,ipq9574";</div><div class='add'>+</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts<br/>new file mode 100644<br/>index 000000000000..c30c9fbedf26<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts</a></div><div class='hunk'>@@ -0,0 +1,17 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)</div><div class='add'>+/*</div><div class='add'>+ * IPQ9574 RDP453 board device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "ipq9574-rdp-common.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C8";</div><div class='add'>+	compatible = "qcom,ipq9574-ap-al02-c8", "qcom,ipq9574";</div><div class='add'>+</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts<br/>new file mode 100644<br/>index 000000000000..0dc382f5d5ec<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts</a></div><div class='hunk'>@@ -0,0 +1,16 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)</div><div class='add'>+/*</div><div class='add'>+ * IPQ9574 RDP454 board device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "ipq9574-rdp-common.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C9";</div><div class='add'>+	compatible = "qcom,ipq9574-ap-al02-c9", "qcom,ipq9574";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi<br/>new file mode 100644<br/>index 000000000000..86c9cb9fffc9<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/ipq9574.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/ipq9574.dtsi</a></div><div class='hunk'>@@ -0,0 +1,1509 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)</div><div class='add'>+/*</div><div class='add'>+ * IPQ9574 SoC device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,apss-ipq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,ipq-cmn-pll.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,ipq9574-gcc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interconnect/qcom,ipq9574.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/reset/qcom,ipq9574-gcc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/thermal/thermal.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	interrupt-parent = &lt;&amp;intc&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	clocks {</div><div class='add'>+		ref_48mhz_clk: ref-48mhz-clk {</div><div class='add'>+			compatible = "fixed-factor-clock";</div><div class='add'>+			clocks = &lt;&amp;xo_clk&gt;;</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sleep_clk: sleep-clk {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		xo_board_clk: xo-board-clk {</div><div class='add'>+			compatible = "fixed-factor-clock";</div><div class='add'>+			clocks = &lt;&amp;ref_48mhz_clk&gt;;</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		xo_clk: xo-clk {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a73";</div><div class='add'>+			reg = &lt;0x0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			clocks = &lt;&amp;apcs_glb APCS_ALIAS0_CORE_CLK&gt;;</div><div class='add'>+			clock-names = "cpu";</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+			cpu-supply = &lt;&amp;ipq9574_s1&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@1 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a73";</div><div class='add'>+			reg = &lt;0x1&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			clocks = &lt;&amp;apcs_glb APCS_ALIAS0_CORE_CLK&gt;;</div><div class='add'>+			clock-names = "cpu";</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+			cpu-supply = &lt;&amp;ipq9574_s1&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@2 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a73";</div><div class='add'>+			reg = &lt;0x2&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			clocks = &lt;&amp;apcs_glb APCS_ALIAS0_CORE_CLK&gt;;</div><div class='add'>+			clock-names = "cpu";</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+			cpu-supply = &lt;&amp;ipq9574_s1&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@3 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a73";</div><div class='add'>+			reg = &lt;0x3&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			clocks = &lt;&amp;apcs_glb APCS_ALIAS0_CORE_CLK&gt;;</div><div class='add'>+			clock-names = "cpu";</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;</div><div class='add'>+			cpu-supply = &lt;&amp;ipq9574_s1&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l2_0: l2-cache {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;2&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	firmware {</div><div class='add'>+		scm {</div><div class='add'>+			compatible = "qcom,scm-ipq9574", "qcom,scm";</div><div class='add'>+			qcom,dload-mode = &lt;&amp;tcsr 0x6100&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@40000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		/* We expect the bootloader to fill in the size */</div><div class='add'>+		reg = &lt;0x0 0x40000000 0x0 0x0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpu_opp_table: opp-table-cpu {</div><div class='add'>+		compatible = "operating-points-v2-kryo-cpu";</div><div class='add'>+		opp-shared;</div><div class='add'>+		nvmem-cells = &lt;&amp;cpu_speed_bin&gt;;</div><div class='add'>+</div><div class='add'>+		opp-936000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;936000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;725000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0xf&gt;;</div><div class='add'>+			clock-latency-ns = &lt;200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1104000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1104000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;787500&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0xf&gt;;</div><div class='add'>+			clock-latency-ns = &lt;200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1200000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1200000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;862500&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0xf&gt;;</div><div class='add'>+			clock-latency-ns = &lt;200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1416000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1416000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;862500&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x7&gt;;</div><div class='add'>+			clock-latency-ns = &lt;200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1488000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1488000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;925000&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x7&gt;;</div><div class='add'>+			clock-latency-ns = &lt;200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1800000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1800000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;987500&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x5&gt;;</div><div class='add'>+			clock-latency-ns = &lt;200000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-2208000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2208000000&gt;;</div><div class='add'>+			opp-microvolt = &lt;1062500&gt;;</div><div class='add'>+			opp-supported-hw = &lt;0x1&gt;;</div><div class='add'>+			clock-latency-ns = &lt;200000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu {</div><div class='add'>+		compatible = "arm,cortex-a73-pmu";</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-1.0";</div><div class='add'>+		method = "smc";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rpm: remoteproc {</div><div class='add'>+		compatible = "qcom,ipq9574-rpm-proc", "qcom,rpm-proc";</div><div class='add'>+</div><div class='add'>+		glink-edge {</div><div class='add'>+			compatible = "qcom,glink-rpm";</div><div class='add'>+			interrupts = &lt;GIC_SPI 168 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			qcom,rpm-msg-ram = &lt;&amp;rpm_msg_ram&gt;;</div><div class='add'>+			mboxes = &lt;&amp;apcs_glb 0&gt;;</div><div class='add'>+</div><div class='add'>+			rpm_requests: rpm-requests {</div><div class='add'>+				compatible = "qcom,rpm-ipq9574", "qcom,glink-smd-rpm";</div><div class='add'>+				qcom,glink-channels = "rpm_requests";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		bootloader@4a100000 {</div><div class='add'>+			reg = &lt;0x0 0x4a100000 0x0 0x400000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sbl@4a500000 {</div><div class='add'>+			reg = &lt;0x0 0x4a500000 0x0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tz_region: tz@4a600000 {</div><div class='add'>+			reg = &lt;0x0 0x4a600000 0x0 0x400000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smem@4aa00000 {</div><div class='add'>+			compatible = "qcom,smem";</div><div class='add'>+			reg = &lt;0x0 0x4aa00000 0x0 0x100000&gt;;</div><div class='add'>+			hwlocks = &lt;&amp;tcsr_mutex 3&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc: soc@0 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;1&gt;;</div><div class='add'>+		ranges = &lt;0 0 0 0xffffffff&gt;;</div><div class='add'>+</div><div class='add'>+		rpm_msg_ram: sram@60000 {</div><div class='add'>+			compatible = "qcom,rpm-msg-ram";</div><div class='add'>+			reg = &lt;0x00060000 0x6000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie0_phy: phy@84000 {</div><div class='add'>+			compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";</div><div class='add'>+			reg = &lt;0x00084000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_PCIE0_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_PIPE_CLK&gt;;</div><div class='add'>+			clock-names = "aux", "cfg_ahb", "pipe";</div><div class='add'>+</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_PCIE0_AUX_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;20000000&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_PCIE0_PHY_BCR&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0PHY_PHY_BCR&gt;;</div><div class='add'>+			reset-names = "phy", "common";</div><div class='add'>+</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-output-names = "gcc_pcie0_pipe_clk_src";</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie2_phy: phy@8c000 {</div><div class='add'>+			compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy";</div><div class='add'>+			reg = &lt;0x0008c000 0x2000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_PCIE2_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE2_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE2_PIPE_CLK&gt;;</div><div class='add'>+			clock-names = "aux", "cfg_ahb", "pipe";</div><div class='add'>+</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_PCIE2_AUX_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;20000000&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_PCIE2_PHY_BCR&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE2PHY_PHY_BCR&gt;;</div><div class='add'>+			reset-names = "phy", "common";</div><div class='add'>+</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-output-names = "gcc_pcie2_pipe_clk_src";</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rng: rng@e3000 {</div><div class='add'>+			compatible = "qcom,ipq9574-trng", "qcom,trng";</div><div class='add'>+			reg = &lt;0x000e3000 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_PRNG_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "core";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdio: mdio@90000 {</div><div class='add'>+			compatible = "qcom,ipq9574-mdio", "qcom,ipq4019-mdio";</div><div class='add'>+			reg = &lt;0x00090000 0x64&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_MDIO_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "gcc_mdio_ahb_clk";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie3_phy: phy@f4000 {</div><div class='add'>+			compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy";</div><div class='add'>+			reg = &lt;0x000f4000 0x2000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_PCIE3_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3_PIPE_CLK&gt;;</div><div class='add'>+			clock-names = "aux", "cfg_ahb", "pipe";</div><div class='add'>+</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_PCIE3_AUX_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;20000000&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_PCIE3_PHY_BCR&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3PHY_PHY_BCR&gt;;</div><div class='add'>+			reset-names = "phy", "common";</div><div class='add'>+</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-output-names = "gcc_pcie3_pipe_clk_src";</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie1_phy: phy@fc000 {</div><div class='add'>+			compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";</div><div class='add'>+			reg = &lt;0x000fc000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_PCIE1_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_PIPE_CLK&gt;;</div><div class='add'>+			clock-names = "aux", "cfg_ahb", "pipe";</div><div class='add'>+</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_PCIE1_AUX_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;20000000&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_PCIE1_PHY_BCR&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1PHY_PHY_BCR&gt;;</div><div class='add'>+			reset-names = "phy", "common";</div><div class='add'>+</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-output-names = "gcc_pcie1_pipe_clk_src";</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cmn_pll: clock-controller@9b000 {</div><div class='add'>+			compatible = "qcom,ipq9574-cmn-pll";</div><div class='add'>+			reg = &lt;0x0009b000 0x800&gt;;</div><div class='add'>+			clocks = &lt;&amp;ref_48mhz_clk&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_CMN_12GPLL_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_CMN_12GPLL_SYS_CLK&gt;;</div><div class='add'>+			clock-names = "ref", "ahb", "sys";</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			assigned-clocks = &lt;&amp;cmn_pll CMN_PLL_CLK&gt;;</div><div class='add'>+			assigned-clock-rates-u64 = /bits/ 64 &lt;12000000000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qfprom: efuse@a4000 {</div><div class='add'>+			compatible = "qcom,ipq9574-qfprom", "qcom,qfprom";</div><div class='add'>+			reg = &lt;0x000a4000 0x5a1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			cpu_speed_bin: cpu-speed-bin@15 {</div><div class='add'>+				reg = &lt;0x15 0x2&gt;;</div><div class='add'>+				bits = &lt;7 2&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cryptobam: dma-controller@704000 {</div><div class='add'>+			compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";</div><div class='add'>+			reg = &lt;0x00704000 0x20000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+			qcom,ee = &lt;1&gt;;</div><div class='add'>+			qcom,num-ees = &lt;4&gt;;</div><div class='add'>+			num-channels = &lt;16&gt;;</div><div class='add'>+			qcom,controlled-remotely;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		crypto: crypto@73a000 {</div><div class='add'>+			compatible = "qcom,ipq9574-qce", "qcom,ipq4019-qce", "qcom,qce";</div><div class='add'>+			reg = &lt;0x0073a000 0x6000&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_CRYPTO_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_CRYPTO_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_CRYPTO_CLK&gt;;</div><div class='add'>+			clock-names = "iface", "bus", "core";</div><div class='add'>+			dmas = &lt;&amp;cryptobam 2&gt;, &lt;&amp;cryptobam 3&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tsens: thermal-sensor@4a9000 {</div><div class='add'>+			compatible = "qcom,ipq9574-tsens", "qcom,ipq8074-tsens";</div><div class='add'>+			reg = &lt;0x004a9000 0x1000&gt;,</div><div class='add'>+			      &lt;0x004a8000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "combined";</div><div class='add'>+			#qcom,sensors = &lt;16&gt;;</div><div class='add'>+			#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tlmm: pinctrl@1000000 {</div><div class='add'>+			compatible = "qcom,ipq9574-tlmm";</div><div class='add'>+			reg = &lt;0x01000000 0x300000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;tlmm 0 0 65&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			uart2_pins: uart2-state {</div><div class='add'>+				pins = "gpio34", "gpio35";</div><div class='add'>+				function = "blsp2_uart";</div><div class='add'>+				drive-strength = &lt;8&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gcc: clock-controller@1800000 {</div><div class='add'>+			compatible = "qcom,ipq9574-gcc";</div><div class='add'>+			reg = &lt;0x01800000 0x80000&gt;;</div><div class='add'>+			clocks = &lt;&amp;xo_board_clk&gt;,</div><div class='add'>+				 &lt;&amp;sleep_clk&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;&amp;pcie0_phy&gt;,</div><div class='add'>+				 &lt;&amp;pcie1_phy&gt;,</div><div class='add'>+				 &lt;&amp;pcie2_phy&gt;,</div><div class='add'>+				 &lt;&amp;pcie3_phy&gt;,</div><div class='add'>+				 &lt;0&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+			#interconnect-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tcsr_mutex: hwlock@1905000 {</div><div class='add'>+			compatible = "qcom,tcsr-mutex";</div><div class='add'>+			reg = &lt;0x01905000 0x20000&gt;;</div><div class='add'>+			#hwlock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tcsr: syscon@1937000 {</div><div class='add'>+			compatible = "qcom,tcsr-ipq9574", "syscon";</div><div class='add'>+			reg = &lt;0x01937000 0x21000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sdhc_1: mmc@7804000 {</div><div class='add'>+			compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5";</div><div class='add'>+			reg = &lt;0x07804000 0x1000&gt;,</div><div class='add'>+			      &lt;0x07805000 0x1000&gt;,</div><div class='add'>+			      &lt;0x07808000 0x2000&gt;;</div><div class='add'>+			reg-names = "hc", "cqhci", "ice";</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "hc_irq", "pwr_irq";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_SDCC1_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_SDCC1_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;xo_board_clk&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_SDCC1_ICE_CORE_CLK&gt;;</div><div class='add'>+			clock-names = "iface", "core", "xo", "ice";</div><div class='add'>+			non-removable;</div><div class='add'>+			supports-cqe;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		blsp_dma: dma-controller@7884000 {</div><div class='add'>+			compatible = "qcom,bam-v1.7.0";</div><div class='add'>+			reg = &lt;0x07884000 0x2b000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "bam_clk";</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+			qcom,ee = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		blsp1_uart0: serial@78af000 {</div><div class='add'>+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";</div><div class='add'>+			reg = &lt;0x078af000 0x200&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_BLSP1_UART1_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "core", "iface";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		blsp1_uart1: serial@78b0000 {</div><div class='add'>+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";</div><div class='add'>+			reg = &lt;0x078b0000 0x200&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_BLSP1_UART2_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "core", "iface";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		blsp1_uart2: serial@78b1000 {</div><div class='add'>+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";</div><div class='add'>+			reg = &lt;0x078b1000 0x200&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_BLSP1_UART3_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "core", "iface";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		blsp1_uart3: serial@78b2000 {</div><div class='add'>+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";</div><div class='add'>+			reg = &lt;0x078b2000 0x200&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_BLSP1_UART4_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "core", "iface";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		blsp1_uart4: serial@78b3000 {</div><div class='add'>+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";</div><div class='add'>+			reg = &lt;0x078b3000 0x200&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_BLSP1_UART5_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "core", "iface";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		blsp1_uart5: serial@78b4000 {</div><div class='add'>+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";</div><div class='add'>+			reg = &lt;0x078b4000 0x200&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_BLSP1_UART6_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "core", "iface";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		blsp1_spi0: spi@78b5000 {</div><div class='add'>+			compatible = "qcom,spi-qup-v2.2.1";</div><div class='add'>+			reg = &lt;0x078b5000 0x600&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_BLSP1_QUP1_SPI_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "core", "iface";</div><div class='add'>+			dmas = &lt;&amp;blsp_dma 12&gt;, &lt;&amp;blsp_dma 13&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		blsp1_i2c1: i2c@78b6000 {</div><div class='add'>+			compatible = "qcom,i2c-qup-v2.2.1";</div><div class='add'>+			reg = &lt;0x078b6000 0x600&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_BLSP1_QUP2_I2C_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "core", "iface";</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_BLSP1_QUP2_I2C_APPS_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;50000000&gt;;</div><div class='add'>+			dmas = &lt;&amp;blsp_dma 14&gt;, &lt;&amp;blsp_dma 15&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		blsp1_spi1: spi@78b6000 {</div><div class='add'>+			compatible = "qcom,spi-qup-v2.2.1";</div><div class='add'>+			reg = &lt;0x078b6000 0x600&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_BLSP1_QUP2_SPI_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "core", "iface";</div><div class='add'>+			dmas = &lt;&amp;blsp_dma 14&gt;, &lt;&amp;blsp_dma 15&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		blsp1_i2c2: i2c@78b7000 {</div><div class='add'>+			compatible = "qcom,i2c-qup-v2.2.1";</div><div class='add'>+			reg = &lt;0x078b7000 0x600&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_BLSP1_QUP3_I2C_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "core", "iface";</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_BLSP1_QUP3_I2C_APPS_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;50000000&gt;;</div><div class='add'>+			dmas = &lt;&amp;blsp_dma 16&gt;, &lt;&amp;blsp_dma 17&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		blsp1_spi2: spi@78b7000 {</div><div class='add'>+			compatible = "qcom,spi-qup-v2.2.1";</div><div class='add'>+			reg = &lt;0x078b7000 0x600&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_BLSP1_QUP3_SPI_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "core", "iface";</div><div class='add'>+			dmas = &lt;&amp;blsp_dma 16&gt;, &lt;&amp;blsp_dma 17&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		blsp1_i2c3: i2c@78b8000 {</div><div class='add'>+			compatible = "qcom,i2c-qup-v2.2.1";</div><div class='add'>+			reg = &lt;0x078b8000 0x600&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_BLSP1_QUP4_I2C_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "core", "iface";</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_BLSP1_QUP4_I2C_APPS_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;50000000&gt;;</div><div class='add'>+			dmas = &lt;&amp;blsp_dma 18&gt;, &lt;&amp;blsp_dma 19&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		blsp1_spi3: spi@78b8000 {</div><div class='add'>+			compatible = "qcom,spi-qup-v2.2.1";</div><div class='add'>+			reg = &lt;0x078b8000 0x600&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			spi-max-frequency = &lt;50000000&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_BLSP1_QUP4_SPI_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "core", "iface";</div><div class='add'>+			dmas = &lt;&amp;blsp_dma 18&gt;, &lt;&amp;blsp_dma 19&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		blsp1_i2c4: i2c@78b9000 {</div><div class='add'>+			compatible = "qcom,i2c-qup-v2.2.1";</div><div class='add'>+			reg = &lt;0x078b9000 0x600&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_BLSP1_QUP5_I2C_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "core", "iface";</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_BLSP1_QUP5_I2C_APPS_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;50000000&gt;;</div><div class='add'>+			dmas = &lt;&amp;blsp_dma 20&gt;, &lt;&amp;blsp_dma 21&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		blsp1_spi4: spi@78b9000 {</div><div class='add'>+			compatible = "qcom,spi-qup-v2.2.1";</div><div class='add'>+			reg = &lt;0x078b9000 0x600&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_BLSP1_QUP5_SPI_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_BLSP1_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "core", "iface";</div><div class='add'>+			dmas = &lt;&amp;blsp_dma 20&gt;, &lt;&amp;blsp_dma 21&gt;;</div><div class='add'>+			dma-names = "tx", "rx";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qpic_bam: dma-controller@7984000 {</div><div class='add'>+			compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";</div><div class='add'>+			reg = &lt;0x07984000 0x1c000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_QPIC_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "bam_clk";</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+			qcom,ee = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qpic_nand: spi@79b0000 {</div><div class='add'>+			compatible = "qcom,ipq9574-snand";</div><div class='add'>+			reg = &lt;0x079b0000 0x10000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_QPIC_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_QPIC_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_QPIC_IO_MACRO_CLK&gt;;</div><div class='add'>+			clock-names = "core", "aon", "iom";</div><div class='add'>+			dmas = &lt;&amp;qpic_bam 0&gt;,</div><div class='add'>+			       &lt;&amp;qpic_bam 1&gt;,</div><div class='add'>+			       &lt;&amp;qpic_bam 2&gt;;</div><div class='add'>+			dma-names = "tx", "rx", "cmd";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_0_qusbphy: phy@7b000 {</div><div class='add'>+			compatible = "qcom,ipq9574-qusb2-phy";</div><div class='add'>+			reg = &lt;0x0007b000 0x180&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_USB0_PHY_CFG_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;xo_board_clk&gt;;</div><div class='add'>+			clock-names = "cfg_ahb",</div><div class='add'>+				      "ref";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_QUSB2_0_PHY_BCR&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_0_qmpphy: phy@7d000 {</div><div class='add'>+			compatible = "qcom,ipq9574-qmp-usb3-phy";</div><div class='add'>+			reg = &lt;0x0007d000 0xa00&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_USB0_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;xo_board_clk&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB0_PHY_CFG_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB0_PIPE_CLK&gt;;</div><div class='add'>+			clock-names = "aux",</div><div class='add'>+				      "ref",</div><div class='add'>+				      "cfg_ahb",</div><div class='add'>+				      "pipe";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_USB0_PHY_BCR&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB3PHY_0_PHY_BCR&gt;;</div><div class='add'>+			reset-names = "phy",</div><div class='add'>+				      "phy_phy";</div><div class='add'>+</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-output-names = "usb0_pipe_clk";</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb3: usb@8af8800 {</div><div class='add'>+			compatible = "qcom,ipq9574-dwc3", "qcom,dwc3";</div><div class='add'>+			reg = &lt;0x08af8800 0x400&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_SNOC_USB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB0_MASTER_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_ANOC_USB_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB0_SLEEP_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB0_MOCK_UTMI_CLK&gt;;</div><div class='add'>+</div><div class='add'>+			clock-names = "cfg_noc",</div><div class='add'>+				      "core",</div><div class='add'>+				      "iface",</div><div class='add'>+				      "sleep",</div><div class='add'>+				      "mock_utmi";</div><div class='add'>+</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_USB0_MASTER_CLK&gt;,</div><div class='add'>+					  &lt;&amp;gcc GCC_USB0_MOCK_UTMI_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;200000000&gt;,</div><div class='add'>+					       &lt;24000000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts-extended = &lt;&amp;intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "pwr_event";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_USB_BCR&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			usb_0_dwc3: usb@8a00000 {</div><div class='add'>+				compatible = "snps,dwc3";</div><div class='add'>+				reg = &lt;0x8a00000 0xcd00&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_USB0_MOCK_UTMI_CLK&gt;;</div><div class='add'>+				clock-names = "ref";</div><div class='add'>+				interrupts = &lt;GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				phys = &lt;&amp;usb_0_qusbphy&gt;, &lt;&amp;usb_0_qmpphy&gt;;</div><div class='add'>+				phy-names = "usb2-phy", "usb3-phy";</div><div class='add'>+				tx-fifo-resize;</div><div class='add'>+				snps,is-utmi-l1-suspend;</div><div class='add'>+				snps,hird-threshold = /bits/ 8 &lt;0x0&gt;;</div><div class='add'>+				snps,dis_u2_susphy_quirk;</div><div class='add'>+				snps,dis_u3_susphy_quirk;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		intc: interrupt-controller@b000000 {</div><div class='add'>+			compatible = "qcom,msm-qgic2";</div><div class='add'>+			reg = &lt;0x0b000000 0x1000&gt;,  /* GICD */</div><div class='add'>+			      &lt;0x0b002000 0x2000&gt;,  /* GICC */</div><div class='add'>+			      &lt;0x0b001000 0x1000&gt;,  /* GICH */</div><div class='add'>+			      &lt;0x0b004000 0x2000&gt;;  /* GICV */</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)&gt;;</div><div class='add'>+			ranges = &lt;0 0x0b00c000 0x3000&gt;;</div><div class='add'>+</div><div class='add'>+			v2m0: v2m@0 {</div><div class='add'>+				compatible = "arm,gic-v2m-frame";</div><div class='add'>+				reg = &lt;0x00000000 0xffd&gt;;</div><div class='add'>+				msi-controller;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			v2m1: v2m@1000 {</div><div class='add'>+				compatible = "arm,gic-v2m-frame";</div><div class='add'>+				reg = &lt;0x00001000 0xffd&gt;;</div><div class='add'>+				msi-controller;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			v2m2: v2m@2000 {</div><div class='add'>+				compatible = "arm,gic-v2m-frame";</div><div class='add'>+				reg = &lt;0x00002000 0xffd&gt;;</div><div class='add'>+				msi-controller;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		watchdog: watchdog@b017000 {</div><div class='add'>+			compatible = "qcom,apss-wdt-ipq9574", "qcom,kpss-wdt";</div><div class='add'>+			reg = &lt;0x0b017000 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 3 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			clocks = &lt;&amp;sleep_clk&gt;;</div><div class='add'>+			timeout-sec = &lt;30&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		apcs_glb: mailbox@b111000 {</div><div class='add'>+			compatible = "qcom,ipq9574-apcs-apps-global",</div><div class='add'>+				     "qcom,ipq6018-apcs-apps-global";</div><div class='add'>+			reg = &lt;0x0b111000 0x1000&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;a73pll&gt;, &lt;&amp;xo_board_clk&gt;, &lt;&amp;gcc GPLL0&gt;;</div><div class='add'>+			clock-names = "pll", "xo", "gpll0";</div><div class='add'>+			#mbox-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		a73pll: clock@b116000 {</div><div class='add'>+			compatible = "qcom,ipq9574-a73pll";</div><div class='add'>+			reg = &lt;0x0b116000 0x40&gt;;</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clocks = &lt;&amp;xo_board_clk&gt;;</div><div class='add'>+			clock-names = "xo";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		timer@b120000 {</div><div class='add'>+			compatible = "arm,armv7-timer-mem";</div><div class='add'>+			reg = &lt;0x0b120000 0x1000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			frame@b120000 {</div><div class='add'>+				reg = &lt;0x0b121000 0x1000&gt;,</div><div class='add'>+				      &lt;0x0b122000 0x1000&gt;;</div><div class='add'>+				frame-number = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@b123000 {</div><div class='add'>+				reg = &lt;0x0b123000 0x1000&gt;;</div><div class='add'>+				frame-number = &lt;1&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@b124000 {</div><div class='add'>+				reg = &lt;0x0b124000 0x1000&gt;;</div><div class='add'>+				frame-number = &lt;2&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@b125000 {</div><div class='add'>+				reg = &lt;0x0b125000 0x1000&gt;;</div><div class='add'>+				frame-number = &lt;3&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@b126000 {</div><div class='add'>+				reg = &lt;0x0b126000 0x1000&gt;;</div><div class='add'>+				frame-number = &lt;4&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@b127000 {</div><div class='add'>+				reg = &lt;0x0b127000 0x1000&gt;;</div><div class='add'>+				frame-number = &lt;5&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@b128000 {</div><div class='add'>+				reg = &lt;0x0b128000 0x1000&gt;;</div><div class='add'>+				frame-number = &lt;6&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie1: pcie@10000000 {</div><div class='add'>+			compatible = "qcom,pcie-ipq9574";</div><div class='add'>+			reg = &lt;0x10000000 0xf1d&gt;,</div><div class='add'>+			      &lt;0x10000f20 0xa8&gt;,</div><div class='add'>+			      &lt;0x10001000 0x1000&gt;,</div><div class='add'>+			      &lt;0x000f8000 0x4000&gt;,</div><div class='add'>+			      &lt;0x10100000 0x1000&gt;,</div><div class='add'>+			      &lt;0x000fe000 0x1000&gt;;</div><div class='add'>+			reg-names = "dbi",</div><div class='add'>+				    "elbi",</div><div class='add'>+				    "atu",</div><div class='add'>+				    "parf",</div><div class='add'>+				    "config",</div><div class='add'>+				    "mhi";</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			linux,pci-domain = &lt;1&gt;;</div><div class='add'>+			bus-range = &lt;0x00 0xff&gt;;</div><div class='add'>+			num-lanes = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			ranges = &lt;0x01000000 0x0 0x00000000 0x10200000 0x0 0x100000&gt;,</div><div class='add'>+				 &lt;0x02000000 0x0 0x10300000 0x10300000 0x0 0x7d00000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "msi0",</div><div class='add'>+					  "msi1",</div><div class='add'>+					  "msi2",</div><div class='add'>+					  "msi3",</div><div class='add'>+					  "msi4",</div><div class='add'>+					  "msi5",</div><div class='add'>+					  "msi6",</div><div class='add'>+					  "msi7";</div><div class='add'>+</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0x7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;intc 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;intc 0 GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;intc 0 GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;intc 0 GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_PCIE1_AXI_M_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_AXI_S_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_AXI_S_BRIDGE_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_RCHNG_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_AUX_CLK&gt;;</div><div class='add'>+			clock-names = "axi_m",</div><div class='add'>+				      "axi_s",</div><div class='add'>+				      "axi_bridge",</div><div class='add'>+				      "rchng",</div><div class='add'>+				      "ahb",</div><div class='add'>+				      "aux";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_PCIE1_PIPE_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_CORE_STICKY_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_AXI_S_STICKY_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_AXI_S_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_AXI_M_STICKY_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_AXI_M_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_AUX_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_AHB_ARES&gt;;</div><div class='add'>+			reset-names = "pipe",</div><div class='add'>+				      "sticky",</div><div class='add'>+				      "axi_s_sticky",</div><div class='add'>+				      "axi_s",</div><div class='add'>+				      "axi_m_sticky",</div><div class='add'>+				      "axi_m",</div><div class='add'>+				      "aux",</div><div class='add'>+				      "ahb";</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;pcie1_phy&gt;;</div><div class='add'>+			phy-names = "pciephy";</div><div class='add'>+			interconnects = &lt;&amp;gcc MASTER_ANOC_PCIE1 &amp;gcc SLAVE_ANOC_PCIE1&gt;,</div><div class='add'>+					&lt;&amp;gcc MASTER_SNOC_PCIE1 &amp;gcc SLAVE_SNOC_PCIE1&gt;;</div><div class='add'>+			interconnect-names = "pcie-mem", "cpu-pcie";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie3: pcie@18000000 {</div><div class='add'>+			compatible = "qcom,pcie-ipq9574";</div><div class='add'>+			reg = &lt;0x18000000 0xf1d&gt;,</div><div class='add'>+			      &lt;0x18000f20 0xa8&gt;,</div><div class='add'>+			      &lt;0x18001000 0x1000&gt;,</div><div class='add'>+			      &lt;0x000f0000 0x4000&gt;,</div><div class='add'>+			      &lt;0x18100000 0x1000&gt;,</div><div class='add'>+			      &lt;0x000f6000 0x1000&gt;;</div><div class='add'>+			reg-names = "dbi",</div><div class='add'>+				    "elbi",</div><div class='add'>+				    "atu",</div><div class='add'>+				    "parf",</div><div class='add'>+				    "config",</div><div class='add'>+				    "mhi";</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			linux,pci-domain = &lt;3&gt;;</div><div class='add'>+			bus-range = &lt;0x00 0xff&gt;;</div><div class='add'>+			num-lanes = &lt;2&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			ranges = &lt;0x01000000 0x0 0x00000000 0x18200000 0x0 0x100000&gt;,</div><div class='add'>+				 &lt;0x02000000 0x0 0x18300000 0x18300000 0x0 0x7d00000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "msi0",</div><div class='add'>+					  "msi1",</div><div class='add'>+					  "msi2",</div><div class='add'>+					  "msi3",</div><div class='add'>+					  "msi4",</div><div class='add'>+					  "msi5",</div><div class='add'>+					  "msi6",</div><div class='add'>+					  "msi7";</div><div class='add'>+</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0x7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;intc 0 GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;intc 0 GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;intc 0 GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;intc 0 GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_PCIE3_AXI_M_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3_AXI_S_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3_AXI_S_BRIDGE_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3_RCHNG_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3_AUX_CLK&gt;;</div><div class='add'>+			clock-names = "axi_m",</div><div class='add'>+				      "axi_s",</div><div class='add'>+				      "axi_bridge",</div><div class='add'>+				      "rchng",</div><div class='add'>+				      "ahb",</div><div class='add'>+				      "aux";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_PCIE3_PIPE_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3_CORE_STICKY_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3_AXI_S_STICKY_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3_AXI_S_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3_AXI_M_STICKY_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3_AXI_M_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3_AUX_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE3_AHB_ARES&gt;;</div><div class='add'>+			reset-names = "pipe",</div><div class='add'>+				      "sticky",</div><div class='add'>+				      "axi_s_sticky",</div><div class='add'>+				      "axi_s",</div><div class='add'>+				      "axi_m_sticky",</div><div class='add'>+				      "axi_m",</div><div class='add'>+				      "aux",</div><div class='add'>+				      "ahb";</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;pcie3_phy&gt;;</div><div class='add'>+			phy-names = "pciephy";</div><div class='add'>+			interconnects = &lt;&amp;gcc MASTER_ANOC_PCIE3 &amp;gcc SLAVE_ANOC_PCIE3&gt;,</div><div class='add'>+					&lt;&amp;gcc MASTER_SNOC_PCIE3 &amp;gcc SLAVE_SNOC_PCIE3&gt;;</div><div class='add'>+			interconnect-names = "pcie-mem", "cpu-pcie";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie2: pcie@20000000 {</div><div class='add'>+			compatible = "qcom,pcie-ipq9574";</div><div class='add'>+			reg = &lt;0x20000000 0xf1d&gt;,</div><div class='add'>+			      &lt;0x20000f20 0xa8&gt;,</div><div class='add'>+			      &lt;0x20001000 0x1000&gt;,</div><div class='add'>+			      &lt;0x00088000 0x4000&gt;,</div><div class='add'>+			      &lt;0x20100000 0x1000&gt;,</div><div class='add'>+			      &lt;0x0008e000 0x1000&gt;;</div><div class='add'>+			reg-names = "dbi",</div><div class='add'>+				    "elbi",</div><div class='add'>+				    "atu",</div><div class='add'>+				    "parf",</div><div class='add'>+				    "config",</div><div class='add'>+				    "mhi";</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			linux,pci-domain = &lt;2&gt;;</div><div class='add'>+			bus-range = &lt;0x00 0xff&gt;;</div><div class='add'>+			num-lanes = &lt;2&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			ranges = &lt;0x01000000 0x0 0x00000000 0x20200000 0x0 0x100000&gt;,</div><div class='add'>+				 &lt;0x02000000 0x0 0x20300000 0x20300000 0x0 0x7d00000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "msi0",</div><div class='add'>+					  "msi1",</div><div class='add'>+					  "msi2",</div><div class='add'>+					  "msi3",</div><div class='add'>+					  "msi4",</div><div class='add'>+					  "msi5",</div><div class='add'>+					  "msi6",</div><div class='add'>+					  "msi7";</div><div class='add'>+</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0x7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;intc 0 GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;intc 0 GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;intc 0 GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;intc 0 GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_PCIE2_AXI_M_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE2_AXI_S_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE2_AXI_S_BRIDGE_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE2_RCHNG_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE2_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE2_AUX_CLK&gt;;</div><div class='add'>+			clock-names = "axi_m",</div><div class='add'>+				      "axi_s",</div><div class='add'>+				      "axi_bridge",</div><div class='add'>+				      "rchng",</div><div class='add'>+				      "ahb",</div><div class='add'>+				      "aux";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_PCIE2_PIPE_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE2_CORE_STICKY_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE2_AXI_S_STICKY_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE2_AXI_S_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE2_AXI_M_STICKY_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE2_AXI_M_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE2_AUX_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE2_AHB_ARES&gt;;</div><div class='add'>+			reset-names = "pipe",</div><div class='add'>+				      "sticky",</div><div class='add'>+				      "axi_s_sticky",</div><div class='add'>+				      "axi_s",</div><div class='add'>+				      "axi_m_sticky",</div><div class='add'>+				      "axi_m",</div><div class='add'>+				      "aux",</div><div class='add'>+				      "ahb";</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;pcie2_phy&gt;;</div><div class='add'>+			phy-names = "pciephy";</div><div class='add'>+			interconnects = &lt;&amp;gcc MASTER_ANOC_PCIE2 &amp;gcc SLAVE_ANOC_PCIE2&gt;,</div><div class='add'>+					&lt;&amp;gcc MASTER_SNOC_PCIE2 &amp;gcc SLAVE_SNOC_PCIE2&gt;;</div><div class='add'>+			interconnect-names = "pcie-mem", "cpu-pcie";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie0: pcie@28000000 {</div><div class='add'>+			compatible = "qcom,pcie-ipq9574";</div><div class='add'>+			reg = &lt;0x28000000 0xf1d&gt;,</div><div class='add'>+			      &lt;0x28000f20 0xa8&gt;,</div><div class='add'>+			      &lt;0x28001000 0x1000&gt;,</div><div class='add'>+			      &lt;0x00080000 0x4000&gt;,</div><div class='add'>+			      &lt;0x28100000 0x1000&gt;,</div><div class='add'>+			      &lt;0x00086000 0x1000&gt;;</div><div class='add'>+			reg-names = "dbi",</div><div class='add'>+				    "elbi",</div><div class='add'>+				    "atu",</div><div class='add'>+				    "parf",</div><div class='add'>+				    "config",</div><div class='add'>+				    "mhi";</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			linux,pci-domain = &lt;0&gt;;</div><div class='add'>+			bus-range = &lt;0x00 0xff&gt;;</div><div class='add'>+			num-lanes = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			ranges = &lt;0x01000000 0x0 0x00000000 0x28200000 0x0 0x100000&gt;,</div><div class='add'>+				 &lt;0x02000000 0x0 0x28300000 0x28300000 0x0 0x7d00000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "msi0",</div><div class='add'>+					  "msi1",</div><div class='add'>+					  "msi2",</div><div class='add'>+					  "msi3",</div><div class='add'>+					  "msi4",</div><div class='add'>+					  "msi5",</div><div class='add'>+					  "msi6",</div><div class='add'>+					  "msi7";</div><div class='add'>+</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0x7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;intc 0 GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;intc 0 GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;intc 0 GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;intc 0 GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_PCIE0_AXI_M_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AXI_S_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AXI_S_BRIDGE_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_RCHNG_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AUX_CLK&gt;;</div><div class='add'>+			clock-names = "axi_m",</div><div class='add'>+				      "axi_s",</div><div class='add'>+				      "axi_bridge",</div><div class='add'>+				      "rchng",</div><div class='add'>+				      "ahb",</div><div class='add'>+				      "aux";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_PCIE0_PIPE_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_CORE_STICKY_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AXI_S_STICKY_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AXI_S_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AXI_M_STICKY_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AXI_M_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AUX_ARES&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_AHB_ARES&gt;;</div><div class='add'>+			reset-names = "pipe",</div><div class='add'>+				      "sticky",</div><div class='add'>+				      "axi_s_sticky",</div><div class='add'>+				      "axi_s",</div><div class='add'>+				      "axi_m_sticky",</div><div class='add'>+				      "axi_m",</div><div class='add'>+				      "aux",</div><div class='add'>+				      "ahb";</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;pcie0_phy&gt;;</div><div class='add'>+			phy-names = "pciephy";</div><div class='add'>+			interconnects = &lt;&amp;gcc MASTER_ANOC_PCIE0 &amp;gcc SLAVE_ANOC_PCIE0&gt;,</div><div class='add'>+					&lt;&amp;gcc MASTER_SNOC_PCIE0 &amp;gcc SLAVE_SNOC_PCIE0&gt;;</div><div class='add'>+			interconnect-names = "pcie-mem", "cpu-pcie";</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nsscc: clock-controller@39b00000 {</div><div class='add'>+			compatible = "qcom,ipq9574-nsscc";</div><div class='add'>+			reg = &lt;0x39b00000 0x80000&gt;;</div><div class='add'>+			clocks = &lt;&amp;xo_board_clk&gt;,</div><div class='add'>+				 &lt;&amp;cmn_pll NSS_1200MHZ_CLK&gt;,</div><div class='add'>+				 &lt;&amp;cmn_pll PPE_353MHZ_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GPLL0_OUT_AUX&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_NSSCC_CLK&gt;;</div><div class='add'>+			clock-names = "xo",</div><div class='add'>+				      "nss_1200",</div><div class='add'>+				      "ppe_353",</div><div class='add'>+				      "gpll0_out",</div><div class='add'>+				      "uniphy0_rx",</div><div class='add'>+				      "uniphy0_tx",</div><div class='add'>+				      "uniphy1_rx",</div><div class='add'>+				      "uniphy1_tx",</div><div class='add'>+				      "uniphy2_rx",</div><div class='add'>+				      "uniphy2_tx",</div><div class='add'>+				      "bus";</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+			#interconnect-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	thermal-zones {</div><div class='add'>+		nss-top-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 3&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				nss-top-critical {</div><div class='add'>+					temperature = &lt;125000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ubi-0-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 4&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				ubi_0-critical {</div><div class='add'>+					temperature = &lt;125000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ubi-1-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 5&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				ubi_1-critical {</div><div class='add'>+					temperature = &lt;125000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ubi-2-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 6&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				ubi_2-critical {</div><div class='add'>+					temperature = &lt;125000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ubi-3-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 7&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				ubi_3-critical {</div><div class='add'>+					temperature = &lt;125000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpuss0-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 8&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu-critical {</div><div class='add'>+					temperature = &lt;125000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpuss1-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 9&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu-critical {</div><div class='add'>+					temperature = &lt;125000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu0-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 10&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu0_crit: cpu-critical {</div><div class='add'>+					temperature = &lt;120000&gt;;</div><div class='add'>+					hysteresis = &lt;10000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu0_alert: cpu-passive {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu0_alert&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 11&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu1_crit: cpu-critical {</div><div class='add'>+					temperature = &lt;120000&gt;;</div><div class='add'>+					hysteresis = &lt;10000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu1_alert: cpu-passive {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu1_alert&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 12&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu2_crit: cpu-critical {</div><div class='add'>+					temperature = &lt;120000&gt;;</div><div class='add'>+					hysteresis = &lt;10000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu2_alert: cpu-passive {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu2_alert&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 13&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu3_crit: cpu-critical {</div><div class='add'>+					temperature = &lt;120000&gt;;</div><div class='add'>+					hysteresis = &lt;10000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu3_alert: cpu-passive {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu3_alert&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wcss-phyb-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 14&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				wcss_phyb-critical {</div><div class='add'>+					temperature = &lt;125000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		top-glue-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens 15&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				top_glue-critical {</div><div class='add'>+					temperature = &lt;125000&gt;;</div><div class='add'>+					hysteresis = &lt;1000&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi<br/>new file mode 100644<br/>index 000000000000..c2ccbb67f800<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/kodiak.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/kodiak.dtsi</a></div><div class='hunk'>@@ -0,0 +1,7750 @@</div><div class='add'>+// SPDX-License-Identifier: BSD-3-Clause</div><div class='add'>+/*</div><div class='add'>+ * sc7280 SoC device tree source</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,camcc-sc7280.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,dispcc-sc7280.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,dsi-phy-28nm.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,gcc-sc7280.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,gpucc-sc7280.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,lpassaudiocc-sc7280.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,lpasscorecc-sc7280.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,rpmh.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,videocc-sc7280.h&gt;</div><div class='add'>+#include &lt;dt-bindings/dma/qcom-gpi.h&gt;</div><div class='add'>+#include &lt;dt-bindings/firmware/qcom,scm.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interconnect/qcom,icc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interconnect/qcom,osm-l3.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interconnect/qcom,sc7280.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/mailbox/qcom-ipcc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/phy/phy-qcom-qmp.h&gt;</div><div class='add'>+#include &lt;dt-bindings/power/qcom-rpmpd.h&gt;</div><div class='add'>+#include &lt;dt-bindings/reset/qcom,sdm845-aoss.h&gt;</div><div class='add'>+#include &lt;dt-bindings/reset/qcom,sdm845-pdc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/soc/qcom,apr.h&gt;</div><div class='add'>+#include &lt;dt-bindings/soc/qcom,rpmh-rsc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/qcom,lpass.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/qcom,q6afe.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/qcom,q6asm.h&gt;</div><div class='add'>+#include &lt;dt-bindings/thermal/thermal.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	interrupt-parent = &lt;&amp;intc&gt;;</div><div class='add'>+</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	chosen { };</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		i2c0 = &amp;i2c0;</div><div class='add'>+		i2c1 = &amp;i2c1;</div><div class='add'>+		i2c2 = &amp;i2c2;</div><div class='add'>+		i2c3 = &amp;i2c3;</div><div class='add'>+		i2c4 = &amp;i2c4;</div><div class='add'>+		i2c5 = &amp;i2c5;</div><div class='add'>+		i2c6 = &amp;i2c6;</div><div class='add'>+		i2c7 = &amp;i2c7;</div><div class='add'>+		i2c8 = &amp;i2c8;</div><div class='add'>+		i2c9 = &amp;i2c9;</div><div class='add'>+		i2c10 = &amp;i2c10;</div><div class='add'>+		i2c11 = &amp;i2c11;</div><div class='add'>+		i2c12 = &amp;i2c12;</div><div class='add'>+		i2c13 = &amp;i2c13;</div><div class='add'>+		i2c14 = &amp;i2c14;</div><div class='add'>+		i2c15 = &amp;i2c15;</div><div class='add'>+		mmc1 = &amp;sdhc_1;</div><div class='add'>+		mmc2 = &amp;sdhc_2;</div><div class='add'>+		spi0 = &amp;spi0;</div><div class='add'>+		spi1 = &amp;spi1;</div><div class='add'>+		spi2 = &amp;spi2;</div><div class='add'>+		spi3 = &amp;spi3;</div><div class='add'>+		spi4 = &amp;spi4;</div><div class='add'>+		spi5 = &amp;spi5;</div><div class='add'>+		spi6 = &amp;spi6;</div><div class='add'>+		spi7 = &amp;spi7;</div><div class='add'>+		spi8 = &amp;spi8;</div><div class='add'>+		spi9 = &amp;spi9;</div><div class='add'>+		spi10 = &amp;spi10;</div><div class='add'>+		spi11 = &amp;spi11;</div><div class='add'>+		spi12 = &amp;spi12;</div><div class='add'>+		spi13 = &amp;spi13;</div><div class='add'>+		spi14 = &amp;spi14;</div><div class='add'>+		spi15 = &amp;spi15;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clocks {</div><div class='add'>+		xo_board: xo-board {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			clock-frequency = &lt;76800000&gt;;</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sleep_clk: sleep-clk {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			clock-frequency = &lt;32764&gt;;</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		wlan_ce_mem: wlan-ce@4cd000 {</div><div class='add'>+			no-map;</div><div class='add'>+			reg = &lt;0x0 0x004cd000 0x0 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		hyp_mem: hyp@80000000 {</div><div class='add'>+			reg = &lt;0x0 0x80000000 0x0 0x600000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		xbl_mem: xbl@80600000 {</div><div class='add'>+			reg = &lt;0x0 0x80600000 0x0 0x200000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aop_mem: aop@80800000 {</div><div class='add'>+			reg = &lt;0x0 0x80800000 0x0 0x60000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aop_cmd_db_mem: aop-cmd-db@80860000 {</div><div class='add'>+			reg = &lt;0x0 0x80860000 0x0 0x20000&gt;;</div><div class='add'>+			compatible = "qcom,cmd-db";</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		reserved_xbl_uefi_log: xbl-uefi-res@80880000 {</div><div class='add'>+			reg = &lt;0x0 0x80884000 0x0 0x10000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sec_apps_mem: sec-apps@808ff000 {</div><div class='add'>+			reg = &lt;0x0 0x808ff000 0x0 0x1000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smem_mem: smem@80900000 {</div><div class='add'>+			reg = &lt;0x0 0x80900000 0x0 0x200000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpucp_mem: cpucp@80b00000 {</div><div class='add'>+			no-map;</div><div class='add'>+			reg = &lt;0x0 0x80b00000 0x0 0x100000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wlan_fw_mem: wlan-fw@80c00000 {</div><div class='add'>+			reg = &lt;0x0 0x80c00000 0x0 0xc00000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		adsp_mem: adsp@86700000 {</div><div class='add'>+			reg = &lt;0x0 0x86700000 0x0 0x2800000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		video_mem: video@8b200000 {</div><div class='add'>+			reg = &lt;0x0 0x8b200000 0x0 0x500000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cdsp_mem: cdsp@88f00000 {</div><div class='add'>+			reg = &lt;0x0 0x88f00000 0x0 0x1e00000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ipa_fw_mem: ipa-fw@8b700000 {</div><div class='add'>+			reg = &lt;0 0x8b700000 0 0x10000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu_zap_mem: zap@8b71a000 {</div><div class='add'>+			reg = &lt;0 0x8b71a000 0 0x2000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mpss_mem: mpss@8b800000 {</div><div class='add'>+			reg = &lt;0x0 0x8b800000 0x0 0xf600000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wpss_mem: wpss@9ae00000 {</div><div class='add'>+			reg = &lt;0x0 0x9ae00000 0x0 0x1900000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rmtfs_mem: rmtfs@9c900000 {</div><div class='add'>+			compatible = "qcom,rmtfs-mem";</div><div class='add'>+			reg = &lt;0x0 0x9c900000 0x0 0x280000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+</div><div class='add'>+			qcom,client-id = &lt;1&gt;;</div><div class='add'>+			qcom,vmid = &lt;QCOM_SCM_VMID_MSS_MSA&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "qcom,kryo";</div><div class='add'>+			reg = &lt;0x0 0x0&gt;;</div><div class='add'>+			clocks = &lt;&amp;cpufreq_hw 0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			power-domains = &lt;&amp;cpu_pd0&gt;;</div><div class='add'>+			power-domain-names = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu0_opp_table&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;100&gt;;</div><div class='add'>+			interconnects = &lt;&amp;gem_noc MASTER_APPSS_PROC 3 &amp;mc_virt SLAVE_EBI1 3&gt;,</div><div class='add'>+					&lt;&amp;epss_l3 MASTER_EPSS_L3_APPS &amp;epss_l3 SLAVE_EPSS_L3_SHARED&gt;;</div><div class='add'>+			qcom,freq-domain = &lt;&amp;cpufreq_hw 0&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			l2_0: l2-cache {</div><div class='add'>+				compatible = "cache";</div><div class='add'>+				cache-level = &lt;2&gt;;</div><div class='add'>+				cache-unified;</div><div class='add'>+				next-level-cache = &lt;&amp;l3_0&gt;;</div><div class='add'>+				l3_0: l3-cache {</div><div class='add'>+					compatible = "cache";</div><div class='add'>+					cache-level = &lt;3&gt;;</div><div class='add'>+					cache-unified;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@100 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "qcom,kryo";</div><div class='add'>+			reg = &lt;0x0 0x100&gt;;</div><div class='add'>+			clocks = &lt;&amp;cpufreq_hw 0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			power-domains = &lt;&amp;cpu_pd1&gt;;</div><div class='add'>+			power-domain-names = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_100&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu0_opp_table&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;100&gt;;</div><div class='add'>+			interconnects = &lt;&amp;gem_noc MASTER_APPSS_PROC 3 &amp;mc_virt SLAVE_EBI1 3&gt;,</div><div class='add'>+					&lt;&amp;epss_l3 MASTER_EPSS_L3_APPS &amp;epss_l3 SLAVE_EPSS_L3_SHARED&gt;;</div><div class='add'>+			qcom,freq-domain = &lt;&amp;cpufreq_hw 0&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			l2_100: l2-cache {</div><div class='add'>+				compatible = "cache";</div><div class='add'>+				cache-level = &lt;2&gt;;</div><div class='add'>+				cache-unified;</div><div class='add'>+				next-level-cache = &lt;&amp;l3_0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@200 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "qcom,kryo";</div><div class='add'>+			reg = &lt;0x0 0x200&gt;;</div><div class='add'>+			clocks = &lt;&amp;cpufreq_hw 0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			power-domains = &lt;&amp;cpu_pd2&gt;;</div><div class='add'>+			power-domain-names = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_200&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu0_opp_table&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;100&gt;;</div><div class='add'>+			interconnects = &lt;&amp;gem_noc MASTER_APPSS_PROC 3 &amp;mc_virt SLAVE_EBI1 3&gt;,</div><div class='add'>+					&lt;&amp;epss_l3 MASTER_EPSS_L3_APPS &amp;epss_l3 SLAVE_EPSS_L3_SHARED&gt;;</div><div class='add'>+			qcom,freq-domain = &lt;&amp;cpufreq_hw 0&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			l2_200: l2-cache {</div><div class='add'>+				compatible = "cache";</div><div class='add'>+				cache-level = &lt;2&gt;;</div><div class='add'>+				cache-unified;</div><div class='add'>+				next-level-cache = &lt;&amp;l3_0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@300 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "qcom,kryo";</div><div class='add'>+			reg = &lt;0x0 0x300&gt;;</div><div class='add'>+			clocks = &lt;&amp;cpufreq_hw 0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			power-domains = &lt;&amp;cpu_pd3&gt;;</div><div class='add'>+			power-domain-names = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_300&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu0_opp_table&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;100&gt;;</div><div class='add'>+			interconnects = &lt;&amp;gem_noc MASTER_APPSS_PROC 3 &amp;mc_virt SLAVE_EBI1 3&gt;,</div><div class='add'>+					&lt;&amp;epss_l3 MASTER_EPSS_L3_APPS &amp;epss_l3 SLAVE_EPSS_L3_SHARED&gt;;</div><div class='add'>+			qcom,freq-domain = &lt;&amp;cpufreq_hw 0&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			l2_300: l2-cache {</div><div class='add'>+				compatible = "cache";</div><div class='add'>+				cache-level = &lt;2&gt;;</div><div class='add'>+				cache-unified;</div><div class='add'>+				next-level-cache = &lt;&amp;l3_0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu4: cpu@400 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "qcom,kryo";</div><div class='add'>+			reg = &lt;0x0 0x400&gt;;</div><div class='add'>+			clocks = &lt;&amp;cpufreq_hw 1&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			power-domains = &lt;&amp;cpu_pd4&gt;;</div><div class='add'>+			power-domain-names = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_400&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu4_opp_table&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1946&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;520&gt;;</div><div class='add'>+			interconnects = &lt;&amp;gem_noc MASTER_APPSS_PROC 3 &amp;mc_virt SLAVE_EBI1 3&gt;,</div><div class='add'>+					&lt;&amp;epss_l3 MASTER_EPSS_L3_APPS &amp;epss_l3 SLAVE_EPSS_L3_SHARED&gt;;</div><div class='add'>+			qcom,freq-domain = &lt;&amp;cpufreq_hw 1&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			l2_400: l2-cache {</div><div class='add'>+				compatible = "cache";</div><div class='add'>+				cache-level = &lt;2&gt;;</div><div class='add'>+				cache-unified;</div><div class='add'>+				next-level-cache = &lt;&amp;l3_0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu5: cpu@500 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "qcom,kryo";</div><div class='add'>+			reg = &lt;0x0 0x500&gt;;</div><div class='add'>+			clocks = &lt;&amp;cpufreq_hw 1&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			power-domains = &lt;&amp;cpu_pd5&gt;;</div><div class='add'>+			power-domain-names = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_500&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu4_opp_table&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1946&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;520&gt;;</div><div class='add'>+			interconnects = &lt;&amp;gem_noc MASTER_APPSS_PROC 3 &amp;mc_virt SLAVE_EBI1 3&gt;,</div><div class='add'>+					&lt;&amp;epss_l3 MASTER_EPSS_L3_APPS &amp;epss_l3 SLAVE_EPSS_L3_SHARED&gt;;</div><div class='add'>+			qcom,freq-domain = &lt;&amp;cpufreq_hw 1&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			l2_500: l2-cache {</div><div class='add'>+				compatible = "cache";</div><div class='add'>+				cache-level = &lt;2&gt;;</div><div class='add'>+				cache-unified;</div><div class='add'>+				next-level-cache = &lt;&amp;l3_0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu6: cpu@600 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "qcom,kryo";</div><div class='add'>+			reg = &lt;0x0 0x600&gt;;</div><div class='add'>+			clocks = &lt;&amp;cpufreq_hw 1&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			power-domains = &lt;&amp;cpu_pd6&gt;;</div><div class='add'>+			power-domain-names = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_600&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu4_opp_table&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1946&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;520&gt;;</div><div class='add'>+			interconnects = &lt;&amp;gem_noc MASTER_APPSS_PROC 3 &amp;mc_virt SLAVE_EBI1 3&gt;,</div><div class='add'>+					&lt;&amp;epss_l3 MASTER_EPSS_L3_APPS &amp;epss_l3 SLAVE_EPSS_L3_SHARED&gt;;</div><div class='add'>+			qcom,freq-domain = &lt;&amp;cpufreq_hw 1&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			l2_600: l2-cache {</div><div class='add'>+				compatible = "cache";</div><div class='add'>+				cache-level = &lt;2&gt;;</div><div class='add'>+				cache-unified;</div><div class='add'>+				next-level-cache = &lt;&amp;l3_0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu7: cpu@700 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "qcom,kryo";</div><div class='add'>+			reg = &lt;0x0 0x700&gt;;</div><div class='add'>+			clocks = &lt;&amp;cpufreq_hw 2&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			power-domains = &lt;&amp;cpu_pd7&gt;;</div><div class='add'>+			power-domain-names = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_700&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu7_opp_table&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1985&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;552&gt;;</div><div class='add'>+			interconnects = &lt;&amp;gem_noc MASTER_APPSS_PROC 3 &amp;mc_virt SLAVE_EBI1 3&gt;,</div><div class='add'>+					&lt;&amp;epss_l3 MASTER_EPSS_L3_APPS &amp;epss_l3 SLAVE_EPSS_L3_SHARED&gt;;</div><div class='add'>+			qcom,freq-domain = &lt;&amp;cpufreq_hw 2&gt;;</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+			l2_700: l2-cache {</div><div class='add'>+				compatible = "cache";</div><div class='add'>+				cache-level = &lt;2&gt;;</div><div class='add'>+				cache-unified;</div><div class='add'>+				next-level-cache = &lt;&amp;l3_0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu-map {</div><div class='add'>+			cluster0 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu2&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu3&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core4 {</div><div class='add'>+					cpu = &lt;&amp;cpu4&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core5 {</div><div class='add'>+					cpu = &lt;&amp;cpu5&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core6 {</div><div class='add'>+					cpu = &lt;&amp;cpu6&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core7 {</div><div class='add'>+					cpu = &lt;&amp;cpu7&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		idle-states {</div><div class='add'>+			entry-method = "psci";</div><div class='add'>+</div><div class='add'>+			little_cpu_sleep_0: cpu-sleep-0-0 {</div><div class='add'>+				compatible = "arm,idle-state";</div><div class='add'>+				idle-state-name = "little-power-down";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x40000003&gt;;</div><div class='add'>+				entry-latency-us = &lt;549&gt;;</div><div class='add'>+				exit-latency-us = &lt;901&gt;;</div><div class='add'>+				min-residency-us = &lt;1774&gt;;</div><div class='add'>+				local-timer-stop;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			little_cpu_sleep_1: cpu-sleep-0-1 {</div><div class='add'>+				compatible = "arm,idle-state";</div><div class='add'>+				idle-state-name = "little-rail-power-down";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x40000004&gt;;</div><div class='add'>+				entry-latency-us = &lt;702&gt;;</div><div class='add'>+				exit-latency-us = &lt;915&gt;;</div><div class='add'>+				min-residency-us = &lt;4001&gt;;</div><div class='add'>+				local-timer-stop;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			big_cpu_sleep_0: cpu-sleep-1-0 {</div><div class='add'>+				compatible = "arm,idle-state";</div><div class='add'>+				idle-state-name = "big-power-down";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x40000003&gt;;</div><div class='add'>+				entry-latency-us = &lt;523&gt;;</div><div class='add'>+				exit-latency-us = &lt;1244&gt;;</div><div class='add'>+				min-residency-us = &lt;2207&gt;;</div><div class='add'>+				local-timer-stop;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			big_cpu_sleep_1: cpu-sleep-1-1 {</div><div class='add'>+				compatible = "arm,idle-state";</div><div class='add'>+				idle-state-name = "big-rail-power-down";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x40000004&gt;;</div><div class='add'>+				entry-latency-us = &lt;526&gt;;</div><div class='add'>+				exit-latency-us = &lt;1854&gt;;</div><div class='add'>+				min-residency-us = &lt;5555&gt;;</div><div class='add'>+				local-timer-stop;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		domain_idle_states: domain-idle-states {</div><div class='add'>+			cluster_sleep_apss_off: cluster-sleep-0 {</div><div class='add'>+				compatible = "domain-idle-state";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x41000044&gt;;</div><div class='add'>+				entry-latency-us = &lt;2752&gt;;</div><div class='add'>+				exit-latency-us = &lt;3048&gt;;</div><div class='add'>+				min-residency-us = &lt;6118&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cluster_sleep_cx_ret: cluster-sleep-1 {</div><div class='add'>+				compatible = "domain-idle-state";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x41001344&gt;;</div><div class='add'>+				entry-latency-us = &lt;3263&gt;;</div><div class='add'>+				exit-latency-us = &lt;4562&gt;;</div><div class='add'>+				min-residency-us = &lt;8467&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cluster_sleep_llcc_off: cluster-sleep-2 {</div><div class='add'>+				compatible = "domain-idle-state";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x4100b344&gt;;</div><div class='add'>+				entry-latency-us = &lt;3638&gt;;</div><div class='add'>+				exit-latency-us = &lt;6562&gt;;</div><div class='add'>+				min-residency-us = &lt;9826&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpu0_opp_table: opp-table-cpu0 {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+		opp-shared;</div><div class='add'>+</div><div class='add'>+		cpu0_opp_300mhz: opp-300000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;300000000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;800000 9600000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu0_opp_691mhz: opp-691200000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;691200000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;800000 17817600&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu0_opp_806mhz: opp-806400000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;806400000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;800000 20889600&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu0_opp_941mhz: opp-940800000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;940800000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;1804000 24576000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu0_opp_1152mhz: opp-1152000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1152000000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;2188000 27033600&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu0_opp_1325mhz: opp-1324800000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1324800000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;2188000 33792000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu0_opp_1517mhz: opp-1516800000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1516800000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;3072000 38092800&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu0_opp_1651mhz: opp-1651200000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1651200000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;3072000 41779200&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu0_opp_1805mhz: opp-1804800000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1804800000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;4068000 48537600&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu0_opp_1958mhz: opp-1958400000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1958400000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;4068000 48537600&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu0_opp_2016mhz: opp-2016000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2016000000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;6220000 48537600&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpu4_opp_table: opp-table-cpu4 {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+		opp-shared;</div><div class='add'>+</div><div class='add'>+		cpu4_opp_691mhz: opp-691200000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;691200000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;1804000 9600000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu4_opp_941mhz: opp-940800000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;940800000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;2188000 17817600&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu4_opp_1229mhz: opp-1228800000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1228800000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;4068000 24576000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu4_opp_1344mhz: opp-1344000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1344000000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;4068000 24576000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu4_opp_1517mhz: opp-1516800000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1516800000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;4068000 24576000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu4_opp_1651mhz: opp-1651200000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1651200000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;6220000 38092800&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu4_opp_1901mhz: opp-1900800000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1900800000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;6220000 44851200&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu4_opp_2054mhz: opp-2054400000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2054400000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;6220000 44851200&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu4_opp_2112mhz: opp-2112000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2112000000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;6220000 44851200&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu4_opp_2131mhz: opp-2131200000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2131200000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;6220000 44851200&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu4_opp_2208mhz: opp-2208000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2208000000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;6220000 44851200&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu4_opp_2400mhz: opp-2400000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2400000000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;12787200 48537600&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu4_opp_2611mhz: opp-2611200000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2611200000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;12787200 48537600&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpu7_opp_table: opp-table-cpu7 {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+		opp-shared;</div><div class='add'>+</div><div class='add'>+		cpu7_opp_806mhz: opp-806400000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;806400000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;1804000 9600000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu7_opp_1056mhz: opp-1056000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1056000000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;2188000 17817600&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu7_opp_1325mhz: opp-1324800000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1324800000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;4068000 24576000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu7_opp_1517mhz: opp-1516800000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1516800000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;4068000 24576000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu7_opp_1766mhz: opp-1766400000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1766400000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;6220000 38092800&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu7_opp_1862mhz: opp-1862400000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1862400000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;6220000 38092800&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu7_opp_2035mhz: opp-2035200000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2035200000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;6220000 38092800&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu7_opp_2112mhz: opp-2112000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2112000000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;6220000 44851200&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu7_opp_2208mhz: opp-2208000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2208000000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;6220000 44851200&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu7_opp_2381mhz: opp-2380800000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2380800000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;6832000 44851200&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu7_opp_2400mhz: opp-2400000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2400000000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;12787200 48537600&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu7_opp_2515mhz: opp-2515200000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2515200000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;12787200 48537600&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu7_opp_2707mhz: opp-2707200000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2707200000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;12787200 48537600&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu7_opp_3014mhz: opp-3014400000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;3014400000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;12787200 48537600&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@80000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		/* We expect the bootloader to fill in the size */</div><div class='add'>+		reg = &lt;0 0x80000000 0 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	firmware {</div><div class='add'>+		scm: scm {</div><div class='add'>+			compatible = "qcom,scm-sc7280", "qcom,scm";</div><div class='add'>+			qcom,dload-mode = &lt;&amp;tcsr_2 0x13000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_virt: interconnect {</div><div class='add'>+		compatible = "qcom,sc7280-clk-virt";</div><div class='add'>+		#interconnect-cells = &lt;2&gt;;</div><div class='add'>+		qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	smem {</div><div class='add'>+		compatible = "qcom,smem";</div><div class='add'>+		memory-region = &lt;&amp;smem_mem&gt;;</div><div class='add'>+		hwlocks = &lt;&amp;tcsr_mutex 3&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	smp2p-adsp {</div><div class='add'>+		compatible = "qcom,smp2p";</div><div class='add'>+		qcom,smem = &lt;443&gt;, &lt;429&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;ipcc IPCC_CLIENT_LPASS</div><div class='add'>+					     IPCC_MPROC_SIGNAL_SMP2P</div><div class='add'>+					     IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+		mboxes = &lt;&amp;ipcc IPCC_CLIENT_LPASS</div><div class='add'>+				IPCC_MPROC_SIGNAL_SMP2P&gt;;</div><div class='add'>+</div><div class='add'>+		qcom,local-pid = &lt;0&gt;;</div><div class='add'>+		qcom,remote-pid = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		adsp_smp2p_out: master-kernel {</div><div class='add'>+			qcom,entry-name = "master-kernel";</div><div class='add'>+			#qcom,smem-state-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		adsp_smp2p_in: slave-kernel {</div><div class='add'>+			qcom,entry-name = "slave-kernel";</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	smp2p-cdsp {</div><div class='add'>+		compatible = "qcom,smp2p";</div><div class='add'>+		qcom,smem = &lt;94&gt;, &lt;432&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;ipcc IPCC_CLIENT_CDSP</div><div class='add'>+					     IPCC_MPROC_SIGNAL_SMP2P</div><div class='add'>+					     IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+		mboxes = &lt;&amp;ipcc IPCC_CLIENT_CDSP</div><div class='add'>+				IPCC_MPROC_SIGNAL_SMP2P&gt;;</div><div class='add'>+</div><div class='add'>+		qcom,local-pid = &lt;0&gt;;</div><div class='add'>+		qcom,remote-pid = &lt;5&gt;;</div><div class='add'>+</div><div class='add'>+		cdsp_smp2p_out: master-kernel {</div><div class='add'>+			qcom,entry-name = "master-kernel";</div><div class='add'>+			#qcom,smem-state-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cdsp_smp2p_in: slave-kernel {</div><div class='add'>+			qcom,entry-name = "slave-kernel";</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	smp2p-mpss {</div><div class='add'>+		compatible = "qcom,smp2p";</div><div class='add'>+		qcom,smem = &lt;435&gt;, &lt;428&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;ipcc IPCC_CLIENT_MPSS</div><div class='add'>+					     IPCC_MPROC_SIGNAL_SMP2P</div><div class='add'>+					     IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+		mboxes = &lt;&amp;ipcc IPCC_CLIENT_MPSS</div><div class='add'>+				IPCC_MPROC_SIGNAL_SMP2P&gt;;</div><div class='add'>+</div><div class='add'>+		qcom,local-pid = &lt;0&gt;;</div><div class='add'>+		qcom,remote-pid = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		modem_smp2p_out: master-kernel {</div><div class='add'>+			qcom,entry-name = "master-kernel";</div><div class='add'>+			#qcom,smem-state-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		modem_smp2p_in: slave-kernel {</div><div class='add'>+			qcom,entry-name = "slave-kernel";</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ipa_smp2p_out: ipa-ap-to-modem {</div><div class='add'>+			qcom,entry-name = "ipa";</div><div class='add'>+			#qcom,smem-state-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ipa_smp2p_in: ipa-modem-to-ap {</div><div class='add'>+			qcom,entry-name = "ipa";</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	smp2p-wpss {</div><div class='add'>+		compatible = "qcom,smp2p";</div><div class='add'>+		qcom,smem = &lt;617&gt;, &lt;616&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;ipcc IPCC_CLIENT_WPSS</div><div class='add'>+					     IPCC_MPROC_SIGNAL_SMP2P</div><div class='add'>+					     IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+		mboxes = &lt;&amp;ipcc IPCC_CLIENT_WPSS</div><div class='add'>+				IPCC_MPROC_SIGNAL_SMP2P&gt;;</div><div class='add'>+</div><div class='add'>+		qcom,local-pid = &lt;0&gt;;</div><div class='add'>+		qcom,remote-pid = &lt;13&gt;;</div><div class='add'>+</div><div class='add'>+		wpss_smp2p_out: master-kernel {</div><div class='add'>+			qcom,entry-name = "master-kernel";</div><div class='add'>+			#qcom,smem-state-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wpss_smp2p_in: slave-kernel {</div><div class='add'>+			qcom,entry-name = "slave-kernel";</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wlan_smp2p_out: wlan-ap-to-wpss {</div><div class='add'>+			qcom,entry-name = "wlan";</div><div class='add'>+			#qcom,smem-state-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wlan_smp2p_in: wlan-wpss-to-ap {</div><div class='add'>+			qcom,entry-name = "wlan";</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu-a55 {</div><div class='add'>+		compatible = "arm,cortex-a55-pmu";</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu-a78 {</div><div class='add'>+		compatible = "arm,cortex-a78-pmu";</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-1.0";</div><div class='add'>+		method = "smc";</div><div class='add'>+</div><div class='add'>+		cpu_pd0: power-domain-cpu0 {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cluster_pd&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;little_cpu_sleep_0 &amp;little_cpu_sleep_1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_pd1: power-domain-cpu1 {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cluster_pd&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;little_cpu_sleep_0 &amp;little_cpu_sleep_1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_pd2: power-domain-cpu2 {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cluster_pd&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;little_cpu_sleep_0 &amp;little_cpu_sleep_1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_pd3: power-domain-cpu3 {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cluster_pd&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;little_cpu_sleep_0 &amp;little_cpu_sleep_1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_pd4: power-domain-cpu4 {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cluster_pd&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;big_cpu_sleep_0 &amp;big_cpu_sleep_1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_pd5: power-domain-cpu5 {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cluster_pd&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;big_cpu_sleep_0 &amp;big_cpu_sleep_1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_pd6: power-domain-cpu6 {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cluster_pd&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;big_cpu_sleep_0 &amp;big_cpu_sleep_1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_pd7: power-domain-cpu7 {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cluster_pd&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;big_cpu_sleep_0 &amp;big_cpu_sleep_1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cluster_pd: power-domain-cluster {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;cluster_sleep_apss_off &amp;cluster_sleep_cx_ret &amp;cluster_sleep_llcc_off&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	qspi_opp_table: opp-table-qspi {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		opp-75000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;75000000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-150000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;150000000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;rpmhpd_opp_svs&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-200000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;200000000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;rpmhpd_opp_svs_l1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-300000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;300000000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;rpmhpd_opp_nom&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	qup_opp_table: opp-table-qup {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		opp-75000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;75000000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-100000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;100000000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;rpmhpd_opp_svs&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-128000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;128000000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;rpmhpd_opp_nom&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc: soc@0 {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges = &lt;0 0 0 0 0x10 0&gt;;</div><div class='add'>+		dma-ranges = &lt;0 0 0 0 0x10 0&gt;;</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+</div><div class='add'>+		gcc: clock-controller@100000 {</div><div class='add'>+			compatible = "qcom,gcc-sc7280";</div><div class='add'>+			reg = &lt;0 0x00100000 0 0x1f0000&gt;;</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;,</div><div class='add'>+				 &lt;&amp;rpmhcc RPMH_CXO_CLK_A&gt;, &lt;&amp;sleep_clk&gt;,</div><div class='add'>+				 &lt;0&gt;, &lt;&amp;pcie1_phy&gt;,</div><div class='add'>+				 &lt;&amp;ufs_mem_phy 0&gt;, &lt;&amp;ufs_mem_phy 1&gt;, &lt;&amp;ufs_mem_phy 2&gt;,</div><div class='add'>+				 &lt;&amp;usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK&gt;;</div><div class='add'>+			clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",</div><div class='add'>+				      "pcie_0_pipe_clk", "pcie_1_pipe_clk",</div><div class='add'>+				      "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk",</div><div class='add'>+				      "ufs_phy_tx_symbol_0_clk",</div><div class='add'>+				      "usb3_phy_wrapper_gcc_usb30_pipe_clk";</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+			power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ipcc: mailbox@408000 {</div><div class='add'>+			compatible = "qcom,sc7280-ipcc", "qcom,ipcc";</div><div class='add'>+			reg = &lt;0 0x00408000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			#mbox-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qfprom: efuse@784000 {</div><div class='add'>+			compatible = "qcom,sc7280-qfprom", "qcom,qfprom";</div><div class='add'>+			reg = &lt;0 0x00784000 0 0xa20&gt;,</div><div class='add'>+			      &lt;0 0x00780000 0 0xa20&gt;,</div><div class='add'>+			      &lt;0 0x00782000 0 0x120&gt;,</div><div class='add'>+			      &lt;0 0x00786000 0 0x1fff&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_SEC_CTRL_CLK_SRC&gt;;</div><div class='add'>+			clock-names = "core";</div><div class='add'>+			power-domains = &lt;&amp;rpmhpd SC7280_MX&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			gpu_speed_bin: gpu-speed-bin@1e9 {</div><div class='add'>+				reg = &lt;0x1e9 0x2&gt;;</div><div class='add'>+				bits = &lt;5 8&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sdhc_1: mmc@7c4000 {</div><div class='add'>+			compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";</div><div class='add'>+			pinctrl-names = "default", "sleep";</div><div class='add'>+			pinctrl-0 = &lt;&amp;sdc1_clk&gt;, &lt;&amp;sdc1_cmd&gt;, &lt;&amp;sdc1_data&gt;, &lt;&amp;sdc1_rclk&gt;;</div><div class='add'>+			pinctrl-1 = &lt;&amp;sdc1_clk_sleep&gt;, &lt;&amp;sdc1_cmd_sleep&gt;, &lt;&amp;sdc1_data_sleep&gt;, &lt;&amp;sdc1_rclk_sleep&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			reg = &lt;0 0x007c4000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x007c5000 0 0x1000&gt;;</div><div class='add'>+			reg-names = "hc", "cqhci";</div><div class='add'>+</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0xc0 0x0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "hc_irq", "pwr_irq";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_SDCC1_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_SDCC1_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;;</div><div class='add'>+			clock-names = "iface", "core", "xo";</div><div class='add'>+			interconnects = &lt;&amp;aggre1_noc MASTER_SDCC_1 0 &amp;mc_virt SLAVE_EBI1 0&gt;,</div><div class='add'>+					&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_SDCC_1 0&gt;;</div><div class='add'>+			interconnect-names = "sdhc-ddr","cpu-sdhc";</div><div class='add'>+			power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;sdhc1_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+			bus-width = &lt;8&gt;;</div><div class='add'>+			supports-cqe;</div><div class='add'>+			dma-coherent;</div><div class='add'>+</div><div class='add'>+			qcom,dll-config = &lt;0x0007642c&gt;;</div><div class='add'>+			qcom,ddr-config = &lt;0x80040868&gt;;</div><div class='add'>+</div><div class='add'>+			mmc-ddr-1_8v;</div><div class='add'>+			mmc-hs200-1_8v;</div><div class='add'>+			mmc-hs400-1_8v;</div><div class='add'>+			mmc-hs400-enhanced-strobe;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_SDCC1_BCR&gt;;</div><div class='add'>+</div><div class='add'>+			sdhc1_opp_table: opp-table {</div><div class='add'>+				compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+				opp-100000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;100000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;1800000 400000&gt;;</div><div class='add'>+					opp-avg-kBps = &lt;100000 0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-384000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;384000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_nom&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;5400000 1600000&gt;;</div><div class='add'>+					opp-avg-kBps = &lt;390000 0&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpi_dma0: dma-controller@900000 {</div><div class='add'>+			#dma-cells = &lt;3&gt;;</div><div class='add'>+			compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma";</div><div class='add'>+			reg = &lt;0 0x00900000 0 0x60000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			dma-channels = &lt;12&gt;;</div><div class='add'>+			dma-channel-mask = &lt;0x7f&gt;;</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x0136 0x0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qupv3_id_0: geniqup@9c0000 {</div><div class='add'>+			compatible = "qcom,geni-se-qup";</div><div class='add'>+			reg = &lt;0 0x009c0000 0 0x2000&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_QUPV3_WRAP_0_M_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_QUPV3_WRAP_0_S_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "m-ahb", "s-ahb";</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x123 0x0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			i2c0: i2c@980000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0 0x00980000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S0_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c0_data_clk&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 0 &amp;clk_virt SLAVE_QUP_CORE_0 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_0 0&gt;,</div><div class='add'>+						&lt;&amp;aggre1_noc MASTER_QUP_0 0 &amp;mc_virt SLAVE_EBI1 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config",</div><div class='add'>+							"qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 0 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 0 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi0: spi@980000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0 0x00980000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S0_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi0_data_clk&gt;, &lt;&amp;qup_spi0_cs&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 0 &amp;clk_virt SLAVE_QUP_CORE_0 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_0 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 0 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 0 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart0: serial@980000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0 0x00980000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S0_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart0_cts&gt;, &lt;&amp;qup_uart0_rts&gt;, &lt;&amp;qup_uart0_tx&gt;, &lt;&amp;qup_uart0_rx&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 0 &amp;clk_virt SLAVE_QUP_CORE_0 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_0 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c1: i2c@984000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0 0x00984000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S1_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c1_data_clk&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 0 &amp;clk_virt SLAVE_QUP_CORE_0 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_0 0&gt;,</div><div class='add'>+						&lt;&amp;aggre1_noc MASTER_QUP_0 0 &amp;mc_virt SLAVE_EBI1 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config",</div><div class='add'>+							"qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 1 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 1 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi1: spi@984000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0 0x00984000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S1_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi1_data_clk&gt;, &lt;&amp;qup_spi1_cs&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 0 &amp;clk_virt SLAVE_QUP_CORE_0 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_0 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 1 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 1 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart1: serial@984000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0 0x00984000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S1_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart1_cts&gt;, &lt;&amp;qup_uart1_rts&gt;, &lt;&amp;qup_uart1_tx&gt;, &lt;&amp;qup_uart1_rx&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 0 &amp;clk_virt SLAVE_QUP_CORE_0 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_0 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c2: i2c@988000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0 0x00988000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S2_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c2_data_clk&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 0 &amp;clk_virt SLAVE_QUP_CORE_0 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_0 0&gt;,</div><div class='add'>+						&lt;&amp;aggre1_noc MASTER_QUP_0 0 &amp;mc_virt SLAVE_EBI1 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config",</div><div class='add'>+							"qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 2 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 2 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi2: spi@988000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0 0x00988000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S2_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi2_data_clk&gt;, &lt;&amp;qup_spi2_cs&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 0 &amp;clk_virt SLAVE_QUP_CORE_0 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_0 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 2 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 2 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart2: serial@988000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0 0x00988000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S2_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart2_cts&gt;, &lt;&amp;qup_uart2_rts&gt;, &lt;&amp;qup_uart2_tx&gt;, &lt;&amp;qup_uart2_rx&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 0 &amp;clk_virt SLAVE_QUP_CORE_0 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_0 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c3: i2c@98c000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0 0x0098c000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S3_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c3_data_clk&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 0 &amp;clk_virt SLAVE_QUP_CORE_0 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_0 0&gt;,</div><div class='add'>+						&lt;&amp;aggre1_noc MASTER_QUP_0 0 &amp;mc_virt SLAVE_EBI1 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config",</div><div class='add'>+							"qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 3 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 3 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi3: spi@98c000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0 0x0098c000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S3_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi3_data_clk&gt;, &lt;&amp;qup_spi3_cs&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 0 &amp;clk_virt SLAVE_QUP_CORE_0 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_0 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 3 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 3 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart3: serial@98c000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0 0x0098c000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S3_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart3_cts&gt;, &lt;&amp;qup_uart3_rts&gt;, &lt;&amp;qup_uart3_tx&gt;, &lt;&amp;qup_uart3_rx&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 0 &amp;clk_virt SLAVE_QUP_CORE_0 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_0 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c4: i2c@990000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0 0x00990000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S4_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c4_data_clk&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 0 &amp;clk_virt SLAVE_QUP_CORE_0 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_0 0&gt;,</div><div class='add'>+						&lt;&amp;aggre1_noc MASTER_QUP_0 0 &amp;mc_virt SLAVE_EBI1 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config",</div><div class='add'>+							"qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 4 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 4 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi4: spi@990000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0 0x00990000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S4_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi4_data_clk&gt;, &lt;&amp;qup_spi4_cs&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 0 &amp;clk_virt SLAVE_QUP_CORE_0 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_0 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 4 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 4 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart4: serial@990000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0 0x00990000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S4_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart4_cts&gt;, &lt;&amp;qup_uart4_rts&gt;, &lt;&amp;qup_uart4_tx&gt;, &lt;&amp;qup_uart4_rx&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 0 &amp;clk_virt SLAVE_QUP_CORE_0 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_0 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c5: i2c@994000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0 0x00994000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S5_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c5_data_clk&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 0 &amp;clk_virt SLAVE_QUP_CORE_0 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_0 0&gt;,</div><div class='add'>+						&lt;&amp;aggre1_noc MASTER_QUP_0 0 &amp;mc_virt SLAVE_EBI1 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config",</div><div class='add'>+							"qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 5 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 5 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi5: spi@994000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0 0x00994000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S5_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi5_data_clk&gt;, &lt;&amp;qup_spi5_cs&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 0 &amp;clk_virt SLAVE_QUP_CORE_0 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_0 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 5 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 5 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart5: serial@994000 {</div><div class='add'>+				compatible = "qcom,geni-debug-uart";</div><div class='add'>+				reg = &lt;0 0x00994000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S5_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart5_tx&gt;, &lt;&amp;qup_uart5_rx&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 0 &amp;clk_virt SLAVE_QUP_CORE_0 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_0 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c6: i2c@998000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0 0x00998000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S6_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c6_data_clk&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 0 &amp;clk_virt SLAVE_QUP_CORE_0 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_0 0&gt;,</div><div class='add'>+						&lt;&amp;aggre1_noc MASTER_QUP_0 0 &amp;mc_virt SLAVE_EBI1 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config",</div><div class='add'>+							"qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 6 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 6 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi6: spi@998000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0 0x00998000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S6_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi6_data_clk&gt;, &lt;&amp;qup_spi6_cs&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 0 &amp;clk_virt SLAVE_QUP_CORE_0 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_0 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 6 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 6 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart6: serial@998000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0 0x00998000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S6_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart6_cts&gt;, &lt;&amp;qup_uart6_rts&gt;, &lt;&amp;qup_uart6_tx&gt;, &lt;&amp;qup_uart6_rx&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 0 &amp;clk_virt SLAVE_QUP_CORE_0 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_0 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c7: i2c@99c000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0 0x0099c000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S7_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c7_data_clk&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 0 &amp;clk_virt SLAVE_QUP_CORE_0 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_0 0&gt;,</div><div class='add'>+						&lt;&amp;aggre1_noc MASTER_QUP_0 0 &amp;mc_virt SLAVE_EBI1 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config",</div><div class='add'>+							"qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 7 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 7 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi7: spi@99c000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0 0x0099c000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S7_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi7_data_clk&gt;, &lt;&amp;qup_spi7_cs&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 0 &amp;clk_virt SLAVE_QUP_CORE_0 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_0 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 7 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 7 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart7: serial@99c000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0 0x0099c000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S7_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart7_cts&gt;, &lt;&amp;qup_uart7_rts&gt;, &lt;&amp;qup_uart7_tx&gt;, &lt;&amp;qup_uart7_rx&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 0 &amp;clk_virt SLAVE_QUP_CORE_0 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_0 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpi_dma1: dma-controller@a00000 {</div><div class='add'>+			#dma-cells = &lt;3&gt;;</div><div class='add'>+			compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma";</div><div class='add'>+			reg = &lt;0 0x00a00000 0 0x60000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			dma-channels = &lt;12&gt;;</div><div class='add'>+			dma-channel-mask = &lt;0x1e&gt;;</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x56 0x0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qupv3_id_1: geniqup@ac0000 {</div><div class='add'>+			compatible = "qcom,geni-se-qup";</div><div class='add'>+			reg = &lt;0 0x00ac0000 0 0x2000&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_QUPV3_WRAP_1_M_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_QUPV3_WRAP_1_S_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "m-ahb", "s-ahb";</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x43 0x0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			i2c8: i2c@a80000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0 0x00a80000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S0_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c8_data_clk&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 0 &amp;clk_virt SLAVE_QUP_CORE_1 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_1 0&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_1 0 &amp;mc_virt SLAVE_EBI1 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config",</div><div class='add'>+							"qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 0 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 0 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi8: spi@a80000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0 0x00a80000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S0_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi8_data_clk&gt;, &lt;&amp;qup_spi8_cs&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 0 &amp;clk_virt SLAVE_QUP_CORE_1 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_1 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 0 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 0 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart8: serial@a80000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0 0x00a80000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S0_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart8_cts&gt;, &lt;&amp;qup_uart8_rts&gt;, &lt;&amp;qup_uart8_tx&gt;, &lt;&amp;qup_uart8_rx&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 0 &amp;clk_virt SLAVE_QUP_CORE_1 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_1 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c9: i2c@a84000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0 0x00a84000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S1_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c9_data_clk&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 0 &amp;clk_virt SLAVE_QUP_CORE_1 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_1 0&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_1 0 &amp;mc_virt SLAVE_EBI1 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config",</div><div class='add'>+							"qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 1 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 1 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi9: spi@a84000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0 0x00a84000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S1_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi9_data_clk&gt;, &lt;&amp;qup_spi9_cs&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 0 &amp;clk_virt SLAVE_QUP_CORE_1 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_1 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 1 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 1 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart9: serial@a84000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0 0x00a84000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S1_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart9_cts&gt;, &lt;&amp;qup_uart9_rts&gt;, &lt;&amp;qup_uart9_tx&gt;, &lt;&amp;qup_uart9_rx&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 0 &amp;clk_virt SLAVE_QUP_CORE_1 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_1 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c10: i2c@a88000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0 0x00a88000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S2_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c10_data_clk&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 0 &amp;clk_virt SLAVE_QUP_CORE_1 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_1 0&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_1 0 &amp;mc_virt SLAVE_EBI1 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config",</div><div class='add'>+							"qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 2 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 2 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi10: spi@a88000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0 0x00a88000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S2_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi10_data_clk&gt;, &lt;&amp;qup_spi10_cs&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 0 &amp;clk_virt SLAVE_QUP_CORE_1 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_1 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 2 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 2 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart10: serial@a88000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0 0x00a88000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S2_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart10_cts&gt;, &lt;&amp;qup_uart10_rts&gt;, &lt;&amp;qup_uart10_tx&gt;, &lt;&amp;qup_uart10_rx&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 0 &amp;clk_virt SLAVE_QUP_CORE_1 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_1 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c11: i2c@a8c000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0 0x00a8c000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S3_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c11_data_clk&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 0 &amp;clk_virt SLAVE_QUP_CORE_1 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_1 0&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_1 0 &amp;mc_virt SLAVE_EBI1 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config",</div><div class='add'>+							"qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 3 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 3 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi11: spi@a8c000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0 0x00a8c000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S3_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi11_data_clk&gt;, &lt;&amp;qup_spi11_cs&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 0 &amp;clk_virt SLAVE_QUP_CORE_1 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_1 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 3 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 3 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart11: serial@a8c000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0 0x00a8c000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S3_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart11_cts&gt;, &lt;&amp;qup_uart11_rts&gt;, &lt;&amp;qup_uart11_tx&gt;, &lt;&amp;qup_uart11_rx&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 0 &amp;clk_virt SLAVE_QUP_CORE_1 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_1 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c12: i2c@a90000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0 0x00a90000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S4_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c12_data_clk&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 0 &amp;clk_virt SLAVE_QUP_CORE_1 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_1 0&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_1 0 &amp;mc_virt SLAVE_EBI1 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config",</div><div class='add'>+							"qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 4 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 4 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi12: spi@a90000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0 0x00a90000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S4_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi12_data_clk&gt;, &lt;&amp;qup_spi12_cs&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 0 &amp;clk_virt SLAVE_QUP_CORE_1 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_1 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 4 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 4 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart12: serial@a90000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0 0x00a90000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S4_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart12_cts&gt;, &lt;&amp;qup_uart12_rts&gt;, &lt;&amp;qup_uart12_tx&gt;, &lt;&amp;qup_uart12_rx&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 0 &amp;clk_virt SLAVE_QUP_CORE_1 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_1 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c13: i2c@a94000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0 0x00a94000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S5_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c13_data_clk&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 0 &amp;clk_virt SLAVE_QUP_CORE_1 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_1 0&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_1 0 &amp;mc_virt SLAVE_EBI1 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config",</div><div class='add'>+							"qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 5 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 5 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi13: spi@a94000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0 0x00a94000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S5_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi13_data_clk&gt;, &lt;&amp;qup_spi13_cs&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 0 &amp;clk_virt SLAVE_QUP_CORE_1 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_1 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 5 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 5 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart13: serial@a94000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0 0x00a94000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S5_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart13_cts&gt;, &lt;&amp;qup_uart13_rts&gt;, &lt;&amp;qup_uart13_tx&gt;, &lt;&amp;qup_uart13_rx&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 0 &amp;clk_virt SLAVE_QUP_CORE_1 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_1 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c14: i2c@a98000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0 0x00a98000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S6_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c14_data_clk&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 0 &amp;clk_virt SLAVE_QUP_CORE_1 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_1 0&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_1 0 &amp;mc_virt SLAVE_EBI1 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config",</div><div class='add'>+							"qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 6 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 6 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi14: spi@a98000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0 0x00a98000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S6_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi14_data_clk&gt;, &lt;&amp;qup_spi14_cs&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 0 &amp;clk_virt SLAVE_QUP_CORE_1 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_1 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 6 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 6 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart14: serial@a98000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0 0x00a98000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S6_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart14_cts&gt;, &lt;&amp;qup_uart14_rts&gt;, &lt;&amp;qup_uart14_tx&gt;, &lt;&amp;qup_uart14_rx&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 0 &amp;clk_virt SLAVE_QUP_CORE_1 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_1 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c15: i2c@a9c000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0 0x00a9c000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S7_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c15_data_clk&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 0 &amp;clk_virt SLAVE_QUP_CORE_1 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_1 0&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_1 0 &amp;mc_virt SLAVE_EBI1 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config",</div><div class='add'>+							"qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 7 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 7 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi15: spi@a9c000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0 0x00a9c000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S7_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi15_data_clk&gt;, &lt;&amp;qup_spi15_cs&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 0 &amp;clk_virt SLAVE_QUP_CORE_1 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_1 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 7 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 7 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx", "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart15: serial@a9c000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0 0x00a9c000 0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S7_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart15_cts&gt;, &lt;&amp;qup_uart15_rts&gt;, &lt;&amp;qup_uart15_tx&gt;, &lt;&amp;qup_uart15_rx&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 0 &amp;clk_virt SLAVE_QUP_CORE_1 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_QUP_1 0&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rng: rng@10d3000 {</div><div class='add'>+			compatible = "qcom,sc7280-trng", "qcom,trng";</div><div class='add'>+			reg = &lt;0 0x010d3000 0 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cnoc2: interconnect@1500000 {</div><div class='add'>+			reg = &lt;0 0x01500000 0 0x1000&gt;;</div><div class='add'>+			compatible = "qcom,sc7280-cnoc2";</div><div class='add'>+			#interconnect-cells = &lt;2&gt;;</div><div class='add'>+			qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cnoc3: interconnect@1502000 {</div><div class='add'>+			reg = &lt;0 0x01502000 0 0x1000&gt;;</div><div class='add'>+			compatible = "qcom,sc7280-cnoc3";</div><div class='add'>+			#interconnect-cells = &lt;2&gt;;</div><div class='add'>+			qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mc_virt: interconnect@1580000 {</div><div class='add'>+			reg = &lt;0 0x01580000 0 0x4&gt;;</div><div class='add'>+			compatible = "qcom,sc7280-mc-virt";</div><div class='add'>+			#interconnect-cells = &lt;2&gt;;</div><div class='add'>+			qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		system_noc: interconnect@1680000 {</div><div class='add'>+			reg = &lt;0 0x01680000 0 0x15480&gt;;</div><div class='add'>+			compatible = "qcom,sc7280-system-noc";</div><div class='add'>+			#interconnect-cells = &lt;2&gt;;</div><div class='add'>+			qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aggre1_noc: interconnect@16e0000 {</div><div class='add'>+			compatible = "qcom,sc7280-aggre1-noc";</div><div class='add'>+			reg = &lt;0 0x016e0000 0 0x1c080&gt;;</div><div class='add'>+			#interconnect-cells = &lt;2&gt;;</div><div class='add'>+			qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_AGGRE_UFS_PHY_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_AGGRE_USB3_PRIM_AXI_CLK&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aggre2_noc: interconnect@1700000 {</div><div class='add'>+			reg = &lt;0 0x01700000 0 0x2b080&gt;;</div><div class='add'>+			compatible = "qcom,sc7280-aggre2-noc";</div><div class='add'>+			#interconnect-cells = &lt;2&gt;;</div><div class='add'>+			qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_IPA_CLK&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmss_noc: interconnect@1740000 {</div><div class='add'>+			reg = &lt;0 0x01740000 0 0x1e080&gt;;</div><div class='add'>+			compatible = "qcom,sc7280-mmss-noc";</div><div class='add'>+			#interconnect-cells = &lt;2&gt;;</div><div class='add'>+			qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wifi: wifi@17a10040 {</div><div class='add'>+			compatible = "qcom,wcn6750-wifi";</div><div class='add'>+			reg = &lt;0 0x17a10040 0 0x0&gt;;</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x1c00 0x1&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 768 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 769 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 770 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 771 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 772 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 773 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 774 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 775 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 776 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 777 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 778 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 779 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 780 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 781 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 782 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 783 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 784 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 785 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 786 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 787 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 788 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 789 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 790 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 791 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 792 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 793 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 794 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 795 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 796 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 797 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 798 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 799 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			qcom,rproc = &lt;&amp;remoteproc_wpss&gt;;</div><div class='add'>+			memory-region = &lt;&amp;wlan_fw_mem&gt;, &lt;&amp;wlan_ce_mem&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+			qcom,smem-states = &lt;&amp;wlan_smp2p_out 0&gt;;</div><div class='add'>+			qcom,smem-state-names = "wlan-smp2p-out";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie0: pcie@1c00000 {</div><div class='add'>+			compatible = "qcom,pcie-sc7280";</div><div class='add'>+			reg = &lt;0 0x01c00000 0 0x3000&gt;,</div><div class='add'>+			      &lt;0 0x60000000 0 0xf1d&gt;,</div><div class='add'>+			      &lt;0 0x60000f20 0 0xa8&gt;,</div><div class='add'>+			      &lt;0 0x60001000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x60100000 0 0x100000&gt;,</div><div class='add'>+			      &lt;0 0x01c03000 0 0x1000&gt;;</div><div class='add'>+			reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			linux,pci-domain = &lt;0&gt;;</div><div class='add'>+			bus-range = &lt;0x00 0xff&gt;;</div><div class='add'>+			num-lanes = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			ranges = &lt;0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000&gt;,</div><div class='add'>+				 &lt;0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "msi0",</div><div class='add'>+					  "msi1",</div><div class='add'>+					  "msi2",</div><div class='add'>+					  "msi3",</div><div class='add'>+					  "msi4",</div><div class='add'>+					  "msi5",</div><div class='add'>+					  "msi6",</div><div class='add'>+					  "msi7",</div><div class='add'>+					  "global";</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0x7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_PCIE_0_PIPE_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_0_PIPE_CLK_SRC&gt;,</div><div class='add'>+				 &lt;&amp;pcie0_phy&gt;,</div><div class='add'>+				 &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_0_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_0_CFG_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_0_MSTR_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_0_SLV_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_AGGRE_NOC_PCIE_TBU_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_DDRSS_PCIE_SF_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK&gt;;</div><div class='add'>+			clock-names = "pipe",</div><div class='add'>+				      "pipe_mux",</div><div class='add'>+				      "phy_pipe",</div><div class='add'>+				      "ref",</div><div class='add'>+				      "aux",</div><div class='add'>+				      "cfg",</div><div class='add'>+				      "bus_master",</div><div class='add'>+				      "bus_slave",</div><div class='add'>+				      "slave_q2a",</div><div class='add'>+				      "tbu",</div><div class='add'>+				      "ddrss_sf_tbu",</div><div class='add'>+				      "aggre0",</div><div class='add'>+				      "aggre1";</div><div class='add'>+</div><div class='add'>+			iommu-map = &lt;0x0   &amp;apps_smmu 0x1c00 0x1&gt;,</div><div class='add'>+				    &lt;0x100 &amp;apps_smmu 0x1c01 0x1&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_PCIE_0_BCR&gt;;</div><div class='add'>+			reset-names = "pci";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;gcc GCC_PCIE_0_GDSC&gt;;</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;pcie0_phy&gt;;</div><div class='add'>+			phy-names = "pciephy";</div><div class='add'>+</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;pcie0_clkreq_n&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcie0_port: pcie@0 {</div><div class='add'>+				device_type = "pci";</div><div class='add'>+				reg = &lt;0x0 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+				bus-range = &lt;0x01 0xff&gt;;</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;3&gt;;</div><div class='add'>+				#size-cells = &lt;2&gt;;</div><div class='add'>+				ranges;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie0_phy: phy@1c06000 {</div><div class='add'>+			compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";</div><div class='add'>+			reg = &lt;0 0x01c06000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_PCIE_0_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_0_CFG_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_CLKREF_EN&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE0_PHY_RCHNG_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_0_PIPE_CLK&gt;;</div><div class='add'>+			clock-names = "aux",</div><div class='add'>+				      "cfg_ahb",</div><div class='add'>+				      "ref",</div><div class='add'>+				      "refgen",</div><div class='add'>+				      "pipe";</div><div class='add'>+</div><div class='add'>+			clock-output-names = "pcie_0_pipe_clk";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_PCIE_0_PHY_BCR&gt;;</div><div class='add'>+			reset-names = "phy";</div><div class='add'>+</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_PCIE0_PHY_RCHNG_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;100000000&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie1: pcie@1c08000 {</div><div class='add'>+			compatible = "qcom,pcie-sc7280";</div><div class='add'>+			reg = &lt;0 0x01c08000 0 0x3000&gt;,</div><div class='add'>+			      &lt;0 0x40000000 0 0xf1d&gt;,</div><div class='add'>+			      &lt;0 0x40000f20 0 0xa8&gt;,</div><div class='add'>+			      &lt;0 0x40001000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x40100000 0 0x100000&gt;;</div><div class='add'>+</div><div class='add'>+			reg-names = "parf", "dbi", "elbi", "atu", "config";</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			linux,pci-domain = &lt;1&gt;;</div><div class='add'>+			bus-range = &lt;0x00 0xff&gt;;</div><div class='add'>+			num-lanes = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			ranges = &lt;0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000&gt;,</div><div class='add'>+				 &lt;0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "msi0",</div><div class='add'>+					  "msi1",</div><div class='add'>+					  "msi2",</div><div class='add'>+					  "msi3",</div><div class='add'>+					  "msi4",</div><div class='add'>+					  "msi5",</div><div class='add'>+					  "msi6",</div><div class='add'>+					  "msi7",</div><div class='add'>+					  "global";</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+			interrupt-map-mask = &lt;0 0 0 0x7&gt;;</div><div class='add'>+			interrupt-map = &lt;0 0 0 1 &amp;intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 2 &amp;intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 3 &amp;intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;0 0 0 4 &amp;intc 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_PCIE_1_PIPE_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_1_PIPE_CLK_SRC&gt;,</div><div class='add'>+				 &lt;&amp;pcie1_phy&gt;,</div><div class='add'>+				 &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_1_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_1_CFG_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_1_MSTR_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_1_SLV_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_AGGRE_NOC_PCIE_TBU_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_DDRSS_PCIE_SF_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK&gt;;</div><div class='add'>+</div><div class='add'>+			clock-names = "pipe",</div><div class='add'>+				      "pipe_mux",</div><div class='add'>+				      "phy_pipe",</div><div class='add'>+				      "ref",</div><div class='add'>+				      "aux",</div><div class='add'>+				      "cfg",</div><div class='add'>+				      "bus_master",</div><div class='add'>+				      "bus_slave",</div><div class='add'>+				      "slave_q2a",</div><div class='add'>+				      "tbu",</div><div class='add'>+				      "ddrss_sf_tbu",</div><div class='add'>+				      "aggre0",</div><div class='add'>+				      "aggre1";</div><div class='add'>+</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_PCIE_1_AUX_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;19200000&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_PCIE_1_BCR&gt;;</div><div class='add'>+			reset-names = "pci";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;gcc GCC_PCIE_1_GDSC&gt;;</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;pcie1_phy&gt;;</div><div class='add'>+			phy-names = "pciephy";</div><div class='add'>+</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;pcie1_clkreq_n&gt;;</div><div class='add'>+</div><div class='add'>+			dma-coherent;</div><div class='add'>+</div><div class='add'>+			iommu-map = &lt;0x0 &amp;apps_smmu 0x1c80 0x1&gt;,</div><div class='add'>+				    &lt;0x100 &amp;apps_smmu 0x1c81 0x1&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			pcie@0 {</div><div class='add'>+				device_type = "pci";</div><div class='add'>+				reg = &lt;0x0 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+				bus-range = &lt;0x01 0xff&gt;;</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;3&gt;;</div><div class='add'>+				#size-cells = &lt;2&gt;;</div><div class='add'>+				ranges;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie1_phy: phy@1c0e000 {</div><div class='add'>+			compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";</div><div class='add'>+			reg = &lt;0 0x01c0e000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_PCIE_1_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_1_CFG_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_CLKREF_EN&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE1_PHY_RCHNG_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_PCIE_1_PIPE_CLK&gt;;</div><div class='add'>+			clock-names = "aux",</div><div class='add'>+				      "cfg_ahb",</div><div class='add'>+				      "ref",</div><div class='add'>+				      "refgen",</div><div class='add'>+				      "pipe";</div><div class='add'>+</div><div class='add'>+			clock-output-names = "pcie_1_pipe_clk";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_PCIE_1_PHY_BCR&gt;;</div><div class='add'>+			reset-names = "phy";</div><div class='add'>+</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_PCIE1_PHY_RCHNG_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;100000000&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ufs_mem_hc: ufshc@1d84000 {</div><div class='add'>+			compatible = "qcom,sc7280-ufshc", "qcom,ufshc",</div><div class='add'>+				     "jedec,ufs-2.0";</div><div class='add'>+			reg = &lt;0x0 0x01d84000 0x0 0x3000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			phys = &lt;&amp;ufs_mem_phy&gt;;</div><div class='add'>+			phy-names = "ufsphy";</div><div class='add'>+			lanes-per-direction = &lt;2&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+			resets = &lt;&amp;gcc GCC_UFS_PHY_BCR&gt;;</div><div class='add'>+			reset-names = "rst";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;gcc GCC_UFS_PHY_GDSC&gt;;</div><div class='add'>+			required-opps = &lt;&amp;rpmhpd_opp_nom&gt;;</div><div class='add'>+</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x80 0x0&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+					&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+					 &amp;cnoc2 SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+			interconnect-names = "ufs-ddr", "cpu-ufs";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_UFS_PHY_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_AGGRE_UFS_PHY_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_UFS_PHY_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_UFS_PHY_UNIPRO_CORE_CLK&gt;,</div><div class='add'>+				 &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK&gt;;</div><div class='add'>+			clock-names = "core_clk",</div><div class='add'>+				      "bus_aggr_clk",</div><div class='add'>+				      "iface_clk",</div><div class='add'>+				      "core_clk_unipro",</div><div class='add'>+				      "ref_clk",</div><div class='add'>+				      "tx_lane0_sync_clk",</div><div class='add'>+				      "rx_lane0_sync_clk",</div><div class='add'>+				      "rx_lane1_sync_clk";</div><div class='add'>+</div><div class='add'>+			operating-points-v2 = &lt;&amp;ufs_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,ice = &lt;&amp;ice&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			ufs_opp_table: opp-table {</div><div class='add'>+				compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+				opp-75000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;75000000&gt;,</div><div class='add'>+						 /bits/ 64 &lt;0&gt;,</div><div class='add'>+						 /bits/ 64 &lt;0&gt;,</div><div class='add'>+						 /bits/ 64 &lt;75000000&gt;,</div><div class='add'>+						 /bits/ 64 &lt;0&gt;,</div><div class='add'>+						 /bits/ 64 &lt;0&gt;,</div><div class='add'>+						 /bits/ 64 &lt;0&gt;,</div><div class='add'>+						 /bits/ 64 &lt;0&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-150000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;150000000&gt;,</div><div class='add'>+						 /bits/ 64 &lt;0&gt;,</div><div class='add'>+						 /bits/ 64 &lt;0&gt;,</div><div class='add'>+						 /bits/ 64 &lt;150000000&gt;,</div><div class='add'>+						 /bits/ 64 &lt;0&gt;,</div><div class='add'>+						 /bits/ 64 &lt;0&gt;,</div><div class='add'>+						 /bits/ 64 &lt;0&gt;,</div><div class='add'>+						 /bits/ 64 &lt;0&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_svs&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-300000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;300000000&gt;,</div><div class='add'>+						 /bits/ 64 &lt;0&gt;,</div><div class='add'>+						 /bits/ 64 &lt;0&gt;,</div><div class='add'>+						 /bits/ 64 &lt;300000000&gt;,</div><div class='add'>+						 /bits/ 64 &lt;0&gt;,</div><div class='add'>+						 /bits/ 64 &lt;0&gt;,</div><div class='add'>+						 /bits/ 64 &lt;0&gt;,</div><div class='add'>+						 /bits/ 64 &lt;0&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_nom&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ufs_mem_phy: phy@1d87000 {</div><div class='add'>+			compatible = "qcom,sc7280-qmp-ufs-phy";</div><div class='add'>+			reg = &lt;0x0 0x01d87000 0x0 0xe00&gt;;</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_UFS_PHY_PHY_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_UFS_1_CLKREF_EN&gt;;</div><div class='add'>+			clock-names = "ref", "ref_aux", "qref";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;rpmhpd SC7280_MX&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;ufs_mem_hc 0&gt;;</div><div class='add'>+			reset-names = "ufsphy";</div><div class='add'>+</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ice: crypto@1d88000 {</div><div class='add'>+			compatible = "qcom,sc7280-inline-crypto-engine",</div><div class='add'>+				     "qcom,inline-crypto-engine";</div><div class='add'>+			reg = &lt;0 0x01d88000 0 0x8000&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_UFS_PHY_ICE_CORE_CLK&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cryptobam: dma-controller@1dc4000 {</div><div class='add'>+			compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";</div><div class='add'>+			reg = &lt;0x0 0x01dc4000 0x0 0x28000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x4e4 0x0011&gt;,</div><div class='add'>+				 &lt;&amp;apps_smmu 0x4e6 0x0011&gt;;</div><div class='add'>+			qcom,ee = &lt;0&gt;;</div><div class='add'>+			qcom,controlled-remotely;</div><div class='add'>+			num-channels = &lt;16&gt;;</div><div class='add'>+			qcom,num-ees = &lt;4&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		crypto: crypto@1dfa000 {</div><div class='add'>+			compatible = "qcom,sc7280-qce", "qcom,sm8150-qce", "qcom,qce";</div><div class='add'>+			reg = &lt;0x0 0x01dfa000 0x0 0x6000&gt;;</div><div class='add'>+			dmas = &lt;&amp;cryptobam 4&gt;, &lt;&amp;cryptobam 5&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x4e4 0x0011&gt;,</div><div class='add'>+				 &lt;&amp;apps_smmu 0x4e4 0x0011&gt;;</div><div class='add'>+			interconnects = &lt;&amp;aggre2_noc MASTER_CRYPTO 0 &amp;mc_virt SLAVE_EBI1 0&gt;;</div><div class='add'>+			interconnect-names = "memory";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ipa: ipa@1e40000 {</div><div class='add'>+			compatible = "qcom,sc7280-ipa";</div><div class='add'>+</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x480 0x0&gt;,</div><div class='add'>+				 &lt;&amp;apps_smmu 0x482 0x0&gt;;</div><div class='add'>+			reg = &lt;0 0x01e40000 0 0x8000&gt;,</div><div class='add'>+			      &lt;0 0x01e50000 0 0x4ad0&gt;,</div><div class='add'>+			      &lt;0 0x01e04000 0 0x23000&gt;;</div><div class='add'>+			reg-names = "ipa-reg",</div><div class='add'>+				    "ipa-shared",</div><div class='add'>+				    "gsi";</div><div class='add'>+</div><div class='add'>+			interrupts-extended = &lt;&amp;intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			interrupt-names = "ipa",</div><div class='add'>+					  "gsi",</div><div class='add'>+					  "ipa-clock-query",</div><div class='add'>+					  "ipa-setup-ready";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_IPA_CLK&gt;;</div><div class='add'>+			clock-names = "core";</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;aggre2_noc MASTER_IPA 0 &amp;mc_virt SLAVE_EBI1 0&gt;,</div><div class='add'>+					&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_IPA_CFG 0&gt;;</div><div class='add'>+			interconnect-names = "memory",</div><div class='add'>+					     "config";</div><div class='add'>+</div><div class='add'>+			qcom,qmp = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,smem-states = &lt;&amp;ipa_smp2p_out 0&gt;,</div><div class='add'>+					   &lt;&amp;ipa_smp2p_out 1&gt;;</div><div class='add'>+			qcom,smem-state-names = "ipa-clock-enabled-valid",</div><div class='add'>+						"ipa-clock-enabled";</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tcsr_mutex: hwlock@1f40000 {</div><div class='add'>+			compatible = "qcom,tcsr-mutex";</div><div class='add'>+			reg = &lt;0 0x01f40000 0 0x20000&gt;;</div><div class='add'>+			#hwlock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tcsr_1: syscon@1f60000 {</div><div class='add'>+			compatible = "qcom,sc7280-tcsr", "syscon";</div><div class='add'>+			reg = &lt;0 0x01f60000 0 0x20000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tcsr_2: syscon@1fc0000 {</div><div class='add'>+			compatible = "qcom,sc7280-tcsr", "syscon";</div><div class='add'>+			reg = &lt;0 0x01fc0000 0 0x30000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		lpasscc: lpasscc@3000000 {</div><div class='add'>+			compatible = "qcom,sc7280-lpasscc";</div><div class='add'>+			reg = &lt;0 0x03000000 0 0x40&gt;,</div><div class='add'>+			      &lt;0 0x03c04000 0 0x4&gt;;</div><div class='add'>+			reg-names = "qdsp6ss", "top_cc";</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_CFG_NOC_LPASS_CLK&gt;;</div><div class='add'>+			clock-names = "iface";</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			status = "reserved"; /* Owned by ADSP firmware */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		lpass_rx_macro: codec@3200000 {</div><div class='add'>+			compatible = "qcom,sc7280-lpass-rx-macro";</div><div class='add'>+			reg = &lt;0 0x03200000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;lpass_rx_swr_clk&gt;, &lt;&amp;lpass_rx_swr_data&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;lpass_aon LPASS_AON_CC_TX_MCLK_CLK&gt;,</div><div class='add'>+				 &lt;&amp;lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK&gt;,</div><div class='add'>+				 &lt;&amp;lpass_va_macro&gt;;</div><div class='add'>+			clock-names = "mclk", "npl", "fsgen";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC&gt;,</div><div class='add'>+					&lt;&amp;lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC&gt;;</div><div class='add'>+			power-domain-names = "macro", "dcodec";</div><div class='add'>+</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		swr0: soundwire@3210000 {</div><div class='add'>+			compatible = "qcom,soundwire-v1.6.0";</div><div class='add'>+			reg = &lt;0 0x03210000 0 0x2000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;lpass_rx_macro&gt;;</div><div class='add'>+			clock-names = "iface";</div><div class='add'>+</div><div class='add'>+			qcom,din-ports = &lt;0&gt;;</div><div class='add'>+			qcom,dout-ports = &lt;5&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR&gt;;</div><div class='add'>+			reset-names = "swr_audio_cgcr";</div><div class='add'>+</div><div class='add'>+			qcom,ports-word-length =	/bits/ 8 &lt;0x01 0x07 0x04 0xff 0xff&gt;;</div><div class='add'>+			qcom,ports-sinterval-low =	/bits/ 8 &lt;0x03 0x3f 0x1f 0x03 0x03&gt;;</div><div class='add'>+			qcom,ports-offset1 =		/bits/ 8 &lt;0x00 0x00 0x0b 0x01 0x01&gt;;</div><div class='add'>+			qcom,ports-offset2 =		/bits/ 8 &lt;0x00 0x00 0x0b 0x00 0x00&gt;;</div><div class='add'>+			qcom,ports-lane-control =	/bits/ 8 &lt;0x01 0x00 0x00 0x00 0x00&gt;;</div><div class='add'>+			qcom,ports-block-pack-mode =	/bits/ 8 &lt;0xff 0x00 0x01 0xff 0xff&gt;;</div><div class='add'>+			qcom,ports-hstart =		/bits/ 8 &lt;0xff 0x03 0xff 0xff 0xff&gt;;</div><div class='add'>+			qcom,ports-hstop =		/bits/ 8 &lt;0xff 0x06 0xff 0xff 0xff&gt;;</div><div class='add'>+			qcom,ports-block-group-count =	/bits/ 8 &lt;0xff 0xff 0xff 0xff 0x00&gt;;</div><div class='add'>+</div><div class='add'>+			#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		lpass_tx_macro: codec@3220000 {</div><div class='add'>+			compatible = "qcom,sc7280-lpass-tx-macro";</div><div class='add'>+			reg = &lt;0 0x03220000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;lpass_tx_swr_clk&gt;, &lt;&amp;lpass_tx_swr_data&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;lpass_aon LPASS_AON_CC_TX_MCLK_CLK&gt;,</div><div class='add'>+				 &lt;&amp;lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK&gt;,</div><div class='add'>+				 &lt;&amp;lpass_va_macro&gt;;</div><div class='add'>+			clock-names = "mclk", "npl", "fsgen";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC&gt;,</div><div class='add'>+					&lt;&amp;lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC&gt;;</div><div class='add'>+			power-domain-names = "macro", "dcodec";</div><div class='add'>+</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		swr1: soundwire@3230000 {</div><div class='add'>+			compatible = "qcom,soundwire-v1.6.0";</div><div class='add'>+			reg = &lt;0 0x03230000 0 0x2000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts-extended = &lt;&amp;intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;pdc 130 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;lpass_tx_macro&gt;;</div><div class='add'>+			clock-names = "iface";</div><div class='add'>+</div><div class='add'>+			qcom,din-ports = &lt;3&gt;;</div><div class='add'>+			qcom,dout-ports = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR&gt;;</div><div class='add'>+			reset-names = "swr_audio_cgcr";</div><div class='add'>+</div><div class='add'>+			qcom,ports-sinterval-low =	/bits/ 8 &lt;0x01 0x03 0x03&gt;;</div><div class='add'>+			qcom,ports-offset1 =		/bits/ 8 &lt;0x01 0x00 0x02&gt;;</div><div class='add'>+			qcom,ports-offset2 =		/bits/ 8 &lt;0x00 0x00 0x00&gt;;</div><div class='add'>+			qcom,ports-hstart =		/bits/ 8 &lt;0xff 0xff 0xff&gt;;</div><div class='add'>+			qcom,ports-hstop =		/bits/ 8 &lt;0xff 0xff 0xff&gt;;</div><div class='add'>+			qcom,ports-word-length =	/bits/ 8 &lt;0xff 0x00 0xff&gt;;</div><div class='add'>+			qcom,ports-block-pack-mode =	/bits/ 8 &lt;0xff 0xff 0xff&gt;;</div><div class='add'>+			qcom,ports-block-group-count =	/bits/ 8 &lt;0xff 0xff 0xff&gt;;</div><div class='add'>+			qcom,ports-lane-control =	/bits/ 8 &lt;0x00 0x01 0x00&gt;;</div><div class='add'>+</div><div class='add'>+			#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		lpass_wsa_macro: codec@3240000 {</div><div class='add'>+			compatible = "qcom,sc7280-lpass-wsa-macro";</div><div class='add'>+			reg = &lt;0x0 0x03240000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;lpass_aon LPASS_AON_CC_TX_MCLK_CLK&gt;,</div><div class='add'>+				 &lt;&amp;lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK&gt;,</div><div class='add'>+				 &lt;&amp;q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO&gt;,</div><div class='add'>+				 &lt;&amp;q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO&gt;,</div><div class='add'>+				 &lt;&amp;lpass_va_macro&gt;;</div><div class='add'>+			clock-names = "mclk",</div><div class='add'>+				      "npl",</div><div class='add'>+				      "macro",</div><div class='add'>+				      "dcodec",</div><div class='add'>+				      "fsgen";</div><div class='add'>+</div><div class='add'>+			pinctrl-0 = &lt;&amp;lpass_wsa_swr_clk&gt;, &lt;&amp;lpass_wsa_swr_data&gt;;</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-output-names = "mclk";</div><div class='add'>+			#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		swr2: soundwire@3250000 {</div><div class='add'>+			compatible = "qcom,soundwire-v1.6.0";</div><div class='add'>+			reg = &lt;0x0 0x03250000 0x0 0x2000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;lpass_wsa_macro&gt;;</div><div class='add'>+			clock-names = "iface";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR&gt;;</div><div class='add'>+			reset-names = "swr_audio_cgcr";</div><div class='add'>+</div><div class='add'>+			qcom,din-ports = &lt;2&gt;;</div><div class='add'>+			qcom,dout-ports = &lt;6&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,ports-sinterval-low = /bits/ 8 &lt;0x07 0x1f 0x3f 0x07</div><div class='add'>+								0x1f 0x3f 0x0f 0x0f&gt;;</div><div class='add'>+			qcom,ports-offset1 = /bits/ 8 &lt;0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a&gt;;</div><div class='add'>+			qcom,ports-offset2 = /bits/ 8 &lt;0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00&gt;;</div><div class='add'>+			qcom,ports-hstart = /bits/ 8 &lt;0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff&gt;;</div><div class='add'>+			qcom,ports-hstop = /bits/ 8 &lt;0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff&gt;;</div><div class='add'>+			qcom,ports-word-length = /bits/ 8 &lt;0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff&gt;;</div><div class='add'>+			qcom,ports-block-pack-mode = /bits/ 8 &lt;0xff 0xff 0x01 0xff 0xff 0x01</div><div class='add'>+							       0xff 0xff&gt;;</div><div class='add'>+			qcom,ports-block-group-count = /bits/ 8 &lt;0xff 0xff 0xff 0xff 0xff 0xff</div><div class='add'>+								0xff 0xff&gt;;</div><div class='add'>+			qcom,ports-lane-control = /bits/ 8 &lt;0xff 0xff 0xff 0xff 0xff 0xff</div><div class='add'>+							    0xff 0xff&gt;;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		lpass_audiocc: clock-controller@3300000 {</div><div class='add'>+			compatible = "qcom,sc7280-lpassaudiocc";</div><div class='add'>+			reg = &lt;0 0x03300000 0 0x30000&gt;,</div><div class='add'>+			      &lt;0 0x032a9000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;,</div><div class='add'>+			       &lt;&amp;lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC&gt;;</div><div class='add'>+			clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src";</div><div class='add'>+			power-domains = &lt;&amp;lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		lpass_va_macro: codec@3370000 {</div><div class='add'>+			compatible = "qcom,sc7280-lpass-va-macro";</div><div class='add'>+			reg = &lt;0 0x03370000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;lpass_aon LPASS_AON_CC_TX_MCLK_CLK&gt;;</div><div class='add'>+			clock-names = "mclk";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC&gt;,</div><div class='add'>+					&lt;&amp;lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC&gt;;</div><div class='add'>+			power-domain-names = "macro", "dcodec";</div><div class='add'>+</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		lpass_aon: clock-controller@3380000 {</div><div class='add'>+			compatible = "qcom,sc7280-lpassaoncc";</div><div class='add'>+			reg = &lt;0 0x03380000 0 0x30000&gt;;</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;,</div><div class='add'>+			       &lt;&amp;rpmhcc RPMH_CXO_CLK_A&gt;,</div><div class='add'>+			       &lt;&amp;lpass_core LPASS_CORE_CC_CORE_CLK&gt;;</div><div class='add'>+			clock-names = "bi_tcxo", "bi_tcxo_ao", "iface";</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+			status = "reserved"; /* Owned by ADSP firmware */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		lpass_core: clock-controller@3900000 {</div><div class='add'>+			compatible = "qcom,sc7280-lpasscorecc";</div><div class='add'>+			reg = &lt;0 0x03900000 0 0x50000&gt;;</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;;</div><div class='add'>+			clock-names = "bi_tcxo";</div><div class='add'>+			power-domains = &lt;&amp;lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+			status = "reserved"; /* Owned by ADSP firmware */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		lpass_cpu: audio@3987000 {</div><div class='add'>+			compatible = "qcom,sc7280-lpass-cpu";</div><div class='add'>+</div><div class='add'>+			reg = &lt;0 0x03987000 0 0x68000&gt;,</div><div class='add'>+			      &lt;0 0x03b00000 0 0x29000&gt;,</div><div class='add'>+			      &lt;0 0x03260000 0 0xc000&gt;,</div><div class='add'>+			      &lt;0 0x03280000 0 0x29000&gt;,</div><div class='add'>+			      &lt;0 0x03340000 0 0x29000&gt;,</div><div class='add'>+			      &lt;0 0x0336c000 0 0x3000&gt;;</div><div class='add'>+			reg-names = "lpass-hdmiif",</div><div class='add'>+				    "lpass-lpaif",</div><div class='add'>+				    "lpass-rxtx-cdc-dma-lpm",</div><div class='add'>+				    "lpass-rxtx-lpaif",</div><div class='add'>+				    "lpass-va-lpaif",</div><div class='add'>+				    "lpass-va-cdc-dma-lpm";</div><div class='add'>+</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x1820 0&gt;,</div><div class='add'>+				 &lt;&amp;apps_smmu 0x1821 0&gt;,</div><div class='add'>+				 &lt;&amp;apps_smmu 0x1832 0&gt;;</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;rpmhpd SC7280_LCX&gt;;</div><div class='add'>+			power-domain-names = "lcx";</div><div class='add'>+			required-opps = &lt;&amp;rpmhpd_opp_nom&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK&gt;,</div><div class='add'>+				 &lt;&amp;lpass_core LPASS_CORE_CC_EXT_MCLK0_CLK&gt;,</div><div class='add'>+				 &lt;&amp;lpass_core LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK&gt;,</div><div class='add'>+				 &lt;&amp;lpass_core LPASS_CORE_CC_EXT_IF0_IBIT_CLK&gt;,</div><div class='add'>+				 &lt;&amp;lpass_core LPASS_CORE_CC_EXT_IF1_IBIT_CLK&gt;,</div><div class='add'>+				 &lt;&amp;lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK&gt;,</div><div class='add'>+				 &lt;&amp;lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK&gt;,</div><div class='add'>+				 &lt;&amp;lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK&gt;,</div><div class='add'>+				 &lt;&amp;lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK&gt;,</div><div class='add'>+				 &lt;&amp;lpass_aon LPASS_AON_CC_VA_MEM0_CLK&gt;;</div><div class='add'>+			clock-names = "aon_cc_audio_hm_h",</div><div class='add'>+				      "audio_cc_ext_mclk0",</div><div class='add'>+				      "core_cc_sysnoc_mport_core",</div><div class='add'>+				      "core_cc_ext_if0_ibit",</div><div class='add'>+				      "core_cc_ext_if1_ibit",</div><div class='add'>+				      "audio_cc_codec_mem",</div><div class='add'>+				      "audio_cc_codec_mem0",</div><div class='add'>+				      "audio_cc_codec_mem1",</div><div class='add'>+				      "audio_cc_codec_mem2",</div><div class='add'>+				      "aon_cc_va_mem0";</div><div class='add'>+</div><div class='add'>+			#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "lpass-irq-lpaif",</div><div class='add'>+					  "lpass-irq-hdmi",</div><div class='add'>+					  "lpass-irq-vaif",</div><div class='add'>+					  "lpass-irq-rxtxif";</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		slimbam: dma-controller@3a84000 {</div><div class='add'>+			compatible = "qcom,bam-v1.7.0";</div><div class='add'>+			reg = &lt;0 0x03a84000 0 0x20000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+			qcom,controlled-remotely;</div><div class='add'>+			num-channels = &lt;31&gt;;</div><div class='add'>+			qcom,ee = &lt;1&gt;;</div><div class='add'>+			qcom,num-ees = &lt;2&gt;;</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x1826 0x0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		slim: slim-ngd@3ac0000 {</div><div class='add'>+			compatible = "qcom,slim-ngd-v1.5.0";</div><div class='add'>+			reg = &lt;0 0x03ac0000 0 0x2c000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			dmas = &lt;&amp;slimbam 3&gt;, &lt;&amp;slimbam 4&gt;;</div><div class='add'>+			dma-names = "rx", "tx";</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x1826 0x0&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		lpass_hm: clock-controller@3c00000 {</div><div class='add'>+			compatible = "qcom,sc7280-lpasshm";</div><div class='add'>+			reg = &lt;0 0x03c00000 0 0x28&gt;;</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;;</div><div class='add'>+			clock-names = "bi_tcxo";</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+			status = "reserved"; /* Owned by ADSP firmware */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		lpass_ag_noc: interconnect@3c40000 {</div><div class='add'>+			reg = &lt;0 0x03c40000 0 0xf080&gt;;</div><div class='add'>+			compatible = "qcom,sc7280-lpass-ag-noc";</div><div class='add'>+			#interconnect-cells = &lt;2&gt;;</div><div class='add'>+			qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		lpass_tlmm: pinctrl@33c0000 {</div><div class='add'>+			compatible = "qcom,sc7280-lpass-lpi-pinctrl";</div><div class='add'>+			reg = &lt;0 0x033c0000 0x0 0x20000&gt;,</div><div class='add'>+				&lt;0 0x03550000 0x0 0x10000&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;lpass_tlmm 0 0 15&gt;;</div><div class='add'>+</div><div class='add'>+			lpass_dmic01_clk: dmic01-clk-state {</div><div class='add'>+				pins = "gpio6";</div><div class='add'>+				function = "dmic1_clk";</div><div class='add'>+				drive-strength = &lt;8&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpass_dmic01_data: dmic01-data-state {</div><div class='add'>+				pins = "gpio7";</div><div class='add'>+				function = "dmic1_data";</div><div class='add'>+				drive-strength = &lt;8&gt;;</div><div class='add'>+				bias-pull-down;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpass_dmic23_clk: dmic23-clk-state {</div><div class='add'>+				pins = "gpio8";</div><div class='add'>+				function = "dmic2_clk";</div><div class='add'>+				drive-strength = &lt;8&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpass_dmic23_data: dmic23-data-state {</div><div class='add'>+				pins = "gpio9";</div><div class='add'>+				function = "dmic2_data";</div><div class='add'>+				drive-strength = &lt;8&gt;;</div><div class='add'>+				bias-pull-down;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpass_rx_swr_clk: rx-swr-clk-state {</div><div class='add'>+				pins = "gpio3";</div><div class='add'>+				function = "swr_rx_clk";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				slew-rate = &lt;1&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpass_rx_swr_data: rx-swr-data-state {</div><div class='add'>+				pins = "gpio4", "gpio5";</div><div class='add'>+				function = "swr_rx_data";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				slew-rate = &lt;1&gt;;</div><div class='add'>+				bias-bus-hold;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpass_tx_swr_clk: tx-swr-clk-state {</div><div class='add'>+				pins = "gpio0";</div><div class='add'>+				function = "swr_tx_clk";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				slew-rate = &lt;1&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpass_tx_swr_data: tx-swr-data-state {</div><div class='add'>+				pins = "gpio1", "gpio2", "gpio14";</div><div class='add'>+				function = "swr_tx_data";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				slew-rate = &lt;1&gt;;</div><div class='add'>+				bias-bus-hold;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpass_wsa_swr_clk: wsa-swr-clk-state {</div><div class='add'>+				pins = "gpio10";</div><div class='add'>+				function = "wsa_swr_clk";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				slew-rate = &lt;1&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			lpass_wsa_swr_data: wsa-swr-data-state {</div><div class='add'>+				pins = "gpio11";</div><div class='add'>+				function = "wsa_swr_data";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				slew-rate = &lt;1&gt;;</div><div class='add'>+				bias-bus-hold;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu: gpu@3d00000 {</div><div class='add'>+			compatible = "qcom,adreno-635.0", "qcom,adreno";</div><div class='add'>+			reg = &lt;0 0x03d00000 0 0x40000&gt;,</div><div class='add'>+			      &lt;0 0x03d9e000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x03d61000 0 0x800&gt;;</div><div class='add'>+			reg-names = "kgsl_3d0_reg_memory",</div><div class='add'>+				    "cx_mem",</div><div class='add'>+				    "cx_dbgc";</div><div class='add'>+			interrupts = &lt;GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			iommus = &lt;&amp;adreno_smmu 0 0x400&gt;,</div><div class='add'>+				 &lt;&amp;adreno_smmu 1 0x400&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;gpu_opp_table&gt;;</div><div class='add'>+			qcom,gmu = &lt;&amp;gmu&gt;;</div><div class='add'>+			interconnects = &lt;&amp;gem_noc MASTER_GFX3D 0 &amp;mc_virt SLAVE_EBI1 0&gt;;</div><div class='add'>+			interconnect-names = "gfx-mem";</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			nvmem-cells = &lt;&amp;gpu_speed_bin&gt;;</div><div class='add'>+			nvmem-cell-names = "speed_bin";</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			gpu_zap_shader: zap-shader {</div><div class='add'>+				memory-region = &lt;&amp;gpu_zap_mem&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gpu_opp_table: opp-table {</div><div class='add'>+				compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+				opp-315000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;315000000&gt;;</div><div class='add'>+					opp-level = &lt;RPMH_REGULATOR_LEVEL_LOW_SVS&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;1804000&gt;;</div><div class='add'>+					opp-supported-hw = &lt;0x17&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-450000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;450000000&gt;;</div><div class='add'>+					opp-level = &lt;RPMH_REGULATOR_LEVEL_SVS&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;4068000&gt;;</div><div class='add'>+					opp-supported-hw = &lt;0x17&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				/* Only applicable for SKUs which has 550Mhz as Fmax */</div><div class='add'>+				opp-550000000-0 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;550000000&gt;;</div><div class='add'>+					opp-level = &lt;RPMH_REGULATOR_LEVEL_SVS_L1&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;8368000&gt;;</div><div class='add'>+					opp-supported-hw = &lt;0x01&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-550000000-1 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;550000000&gt;;</div><div class='add'>+					opp-level = &lt;RPMH_REGULATOR_LEVEL_SVS_L1&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;6832000&gt;;</div><div class='add'>+					opp-supported-hw = &lt;0x16&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-608000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;608000000&gt;;</div><div class='add'>+					opp-level = &lt;RPMH_REGULATOR_LEVEL_SVS_L2&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;8368000&gt;;</div><div class='add'>+					opp-supported-hw = &lt;0x16&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-700000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;700000000&gt;;</div><div class='add'>+					opp-level = &lt;RPMH_REGULATOR_LEVEL_NOM&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;8532000&gt;;</div><div class='add'>+					opp-supported-hw = &lt;0x06&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-812000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;812000000&gt;;</div><div class='add'>+					opp-level = &lt;RPMH_REGULATOR_LEVEL_NOM_L1&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;8532000&gt;;</div><div class='add'>+					opp-supported-hw = &lt;0x06&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-840000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;840000000&gt;;</div><div class='add'>+					opp-level = &lt;RPMH_REGULATOR_LEVEL_TURBO&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;8532000&gt;;</div><div class='add'>+					opp-supported-hw = &lt;0x02&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-900000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;900000000&gt;;</div><div class='add'>+					opp-level = &lt;RPMH_REGULATOR_LEVEL_TURBO_L1&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;8532000&gt;;</div><div class='add'>+					opp-supported-hw = &lt;0x02&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gmu: gmu@3d6a000 {</div><div class='add'>+			compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu";</div><div class='add'>+			reg = &lt;0 0x03d6a000 0 0x34000&gt;,</div><div class='add'>+				&lt;0 0x3de0000 0 0x10000&gt;,</div><div class='add'>+				&lt;0 0x0b290000 0 0x10000&gt;;</div><div class='add'>+			reg-names = "gmu", "rscc", "gmu_pdc";</div><div class='add'>+			interrupts = &lt;GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "hfi", "gmu";</div><div class='add'>+			clocks = &lt;&amp;gpucc GPU_CC_CX_GMU_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gpucc GPU_CC_CXO_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_DDRSS_GPU_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_GPU_MEMNOC_GFX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gpucc GPU_CC_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gpucc GPU_CC_HUB_CX_INT_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK&gt;;</div><div class='add'>+			clock-names = "gmu",</div><div class='add'>+				      "cxo",</div><div class='add'>+				      "axi",</div><div class='add'>+				      "memnoc",</div><div class='add'>+				      "ahb",</div><div class='add'>+				      "hub",</div><div class='add'>+				      "smmu_vote";</div><div class='add'>+			power-domains = &lt;&amp;gpucc GPU_CC_CX_GDSC&gt;,</div><div class='add'>+					&lt;&amp;gpucc GPU_CC_GX_GDSC&gt;;</div><div class='add'>+			power-domain-names = "cx",</div><div class='add'>+					     "gx";</div><div class='add'>+			iommus = &lt;&amp;adreno_smmu 5 0x400&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;gmu_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+			gmu_opp_table: opp-table {</div><div class='add'>+				compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+				opp-200000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;200000000&gt;;</div><div class='add'>+					opp-level = &lt;RPMH_REGULATOR_LEVEL_MIN_SVS&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpucc: clock-controller@3d90000 {</div><div class='add'>+			compatible = "qcom,sc7280-gpucc";</div><div class='add'>+			reg = &lt;0 0x03d90000 0 0x9000&gt;;</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_GPU_GPLL0_CLK_SRC&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_GPU_GPLL0_DIV_CLK_SRC&gt;;</div><div class='add'>+			clock-names = "bi_tcxo",</div><div class='add'>+				      "gcc_gpu_gpll0_clk_src",</div><div class='add'>+				      "gcc_gpu_gpll0_div_clk_src";</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dma@117f000 {</div><div class='add'>+			compatible = "qcom,sc7280-dcc", "qcom,dcc";</div><div class='add'>+			reg = &lt;0x0 0x0117f000 0x0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0x01112000 0x0 0x6000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		adreno_smmu: iommu@3da0000 {</div><div class='add'>+			compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu",</div><div class='add'>+				     "qcom,smmu-500", "arm,mmu-500";</div><div class='add'>+			reg = &lt;0 0x03da0000 0 0x20000&gt;;</div><div class='add'>+			#iommu-cells = &lt;2&gt;;</div><div class='add'>+			#global-interrupts = &lt;2&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					&lt;GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_GPU_MEMNOC_GFX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_GPU_SNOC_DVM_GFX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gpucc GPU_CC_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gpucc GPU_CC_CX_GMU_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gpucc GPU_CC_HUB_CX_INT_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gpucc GPU_CC_HUB_AON_CLK&gt;;</div><div class='add'>+			clock-names = "gcc_gpu_memnoc_gfx_clk",</div><div class='add'>+					"gcc_gpu_snoc_dvm_gfx_clk",</div><div class='add'>+					"gpu_cc_ahb_clk",</div><div class='add'>+					"gpu_cc_hlos1_vote_gpu_smmu_clk",</div><div class='add'>+					"gpu_cc_cx_gmu_clk",</div><div class='add'>+					"gpu_cc_hub_cx_int_clk",</div><div class='add'>+					"gpu_cc_hub_aon_clk";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;gpucc GPU_CC_CX_GDSC&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gfx_0_tbu: tbu@3dd9000 {</div><div class='add'>+			compatible = "qcom,sc7280-tbu";</div><div class='add'>+			reg = &lt;0x0 0x3dd9000 0x0 0x1000&gt;;</div><div class='add'>+			qcom,stream-id-range = &lt;&amp;adreno_smmu 0x0 0x400&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gfx_1_tbu: tbu@3ddd000 {</div><div class='add'>+			compatible = "qcom,sc7280-tbu";</div><div class='add'>+			reg = &lt;0x0 0x3ddd000 0x0 0x1000&gt;;</div><div class='add'>+			qcom,stream-id-range = &lt;&amp;adreno_smmu 0x400 0x400&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		remoteproc_mpss: remoteproc@4080000 {</div><div class='add'>+			compatible = "qcom,sc7280-mpss-pas";</div><div class='add'>+			reg = &lt;0 0x04080000 0 0x10000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts-extended = &lt;&amp;intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			interrupt-names = "wdog", "fatal", "ready", "handover",</div><div class='add'>+					  "stop-ack", "shutdown-ack";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;;</div><div class='add'>+			clock-names = "xo";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;,</div><div class='add'>+					&lt;&amp;rpmhpd SC7280_MSS&gt;;</div><div class='add'>+			power-domain-names = "cx", "mss";</div><div class='add'>+</div><div class='add'>+			memory-region = &lt;&amp;mpss_mem&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,qmp = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,smem-states = &lt;&amp;modem_smp2p_out 0&gt;;</div><div class='add'>+			qcom,smem-state-names = "stop";</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			glink-edge {</div><div class='add'>+				interrupts-extended = &lt;&amp;ipcc IPCC_CLIENT_MPSS</div><div class='add'>+							     IPCC_MPROC_SIGNAL_GLINK_QMP</div><div class='add'>+							     IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				mboxes = &lt;&amp;ipcc IPCC_CLIENT_MPSS</div><div class='add'>+						IPCC_MPROC_SIGNAL_GLINK_QMP&gt;;</div><div class='add'>+				label = "modem";</div><div class='add'>+				qcom,remote-pid = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		stm@6002000 {</div><div class='add'>+			compatible = "arm,coresight-stm", "arm,primecell";</div><div class='add'>+			reg = &lt;0 0x06002000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x16280000 0 0x180000&gt;;</div><div class='add'>+			reg-names = "stm-base", "stm-stimulus-base";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					stm_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;funnel0_in7&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpda@6004000 {</div><div class='add'>+			compatible = "qcom,coresight-tpda", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x06004000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@1c {</div><div class='add'>+					reg = &lt;0x1c&gt;;</div><div class='add'>+</div><div class='add'>+					qdss_tpda_in28: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;spdm_tpdm_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					qdss_tpda_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;qdss_dl_funnel_in0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		funnel@6005000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x06005000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				port {</div><div class='add'>+					qdss_dl_funnel_in0: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;qdss_tpda_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					qdss_dl_funnel_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;funnel0_in6&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@600f000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x0600f000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,cmb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,cmb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					spdm_tpdm_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;qdss_tpda_in28&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cti@6010000 {</div><div class='add'>+			compatible = "arm,coresight-cti", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x06010000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		funnel@6041000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";</div><div class='add'>+			reg = &lt;0 0x06041000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					funnel0_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;merge_funnel_in0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@6 {</div><div class='add'>+					reg = &lt;6&gt;;</div><div class='add'>+</div><div class='add'>+					funnel0_in6: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;qdss_dl_funnel_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@7 {</div><div class='add'>+					reg = &lt;7&gt;;</div><div class='add'>+					funnel0_in7: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;stm_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		funnel@6042000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";</div><div class='add'>+			reg = &lt;0 0x06042000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					funnel1_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;merge_funnel_in1&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@4 {</div><div class='add'>+					reg = &lt;4&gt;;</div><div class='add'>+					funnel1_in4: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;apss_merge_funnel_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		funnel@6045000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";</div><div class='add'>+			reg = &lt;0 0x06045000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					merge_funnel_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;swao_funnel_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					merge_funnel_in0: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;funnel0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					merge_funnel_in1: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;funnel1_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		replicator@6046000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";</div><div class='add'>+			reg = &lt;0 0x06046000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					replicator_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;etr_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				port {</div><div class='add'>+					replicator_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;swao_replicator_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		etr@6048000 {</div><div class='add'>+			compatible = "arm,coresight-tmc", "arm,primecell";</div><div class='add'>+			reg = &lt;0 0x06048000 0 0x1000&gt;;</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x04c0 0&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			arm,scatter-gather;</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				port {</div><div class='add'>+					etr_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;replicator_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cti@6b00000 {</div><div class='add'>+			compatible = "arm,coresight-cti", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x06b00000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cti@6b01000 {</div><div class='add'>+			compatible = "arm,coresight-cti", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x06b01000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cti@6b02000 {</div><div class='add'>+			compatible = "arm,coresight-cti", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x06b02000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cti@6b03000 {</div><div class='add'>+			compatible = "arm,coresight-cti", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x06b03000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		funnel@6b04000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";</div><div class='add'>+			reg = &lt;0 0x06b04000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					swao_funnel_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;etf_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@6 {</div><div class='add'>+					reg = &lt;6&gt;;</div><div class='add'>+</div><div class='add'>+					swao_funnel_in6: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;aoss_tpda_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@7 {</div><div class='add'>+					reg = &lt;7&gt;;</div><div class='add'>+					swao_funnel_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;merge_funnel_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		etf@6b05000 {</div><div class='add'>+			compatible = "arm,coresight-tmc", "arm,primecell";</div><div class='add'>+			reg = &lt;0 0x06b05000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					etf_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;swao_replicator_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				port {</div><div class='add'>+					etf_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;swao_funnel_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		replicator@6b06000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";</div><div class='add'>+			reg = &lt;0 0x06b06000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			qcom,replicator-loses-context;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					swao_replicator_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;replicator_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				port {</div><div class='add'>+					swao_replicator_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;etf_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpda@6b08000 {</div><div class='add'>+			compatible = "qcom,coresight-tpda", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x06b08000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					aoss_tpda_in0: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;swao_prio0_tpdm_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					aoss_tpda_in1: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;swao_prio1_tpdm_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@2 {</div><div class='add'>+					reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+					aoss_tpda_in2: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;swao_prio2_tpdm_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@3 {</div><div class='add'>+					reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+					aoss_tpda_in3: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;swao_prio3_tpdm_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@4 {</div><div class='add'>+					reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+					aoss_tpda_in4: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;swao_tpdm_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					aoss_tpda_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;swao_funnel_in6&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@6b09000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x06b09000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,cmb-element-bits = &lt;64&gt;;</div><div class='add'>+			qcom,cmb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					swao_prio0_tpdm_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;aoss_tpda_in0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@6b0a000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x06b0a000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,cmb-element-bits = &lt;64&gt;;</div><div class='add'>+			qcom,cmb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					swao_prio1_tpdm_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;aoss_tpda_in1&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@6b0b000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x06b0b000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,cmb-element-bits = &lt;64&gt;;</div><div class='add'>+			qcom,cmb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					swao_prio2_tpdm_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;aoss_tpda_in2&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@6b0c000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x06b0c000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,cmb-element-bits = &lt;64&gt;;</div><div class='add'>+			qcom,cmb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					swao_prio3_tpdm_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;aoss_tpda_in3&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@6b0d000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x06b0d000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,dsb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,dsb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					swao_tpdm_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;aoss_tpda_in4&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cti@6b11000 {</div><div class='add'>+			compatible = "arm,coresight-cti", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x06b11000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		etm@7040000 {</div><div class='add'>+			compatible = "arm,coresight-etm4x", "arm,primecell";</div><div class='add'>+			reg = &lt;0 0x07040000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			cpu = &lt;&amp;cpu0&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			arm,coresight-loses-context-with-cpu;</div><div class='add'>+			qcom,skip-power-up;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					etm0_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;apss_funnel_in0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		etm@7140000 {</div><div class='add'>+			compatible = "arm,coresight-etm4x", "arm,primecell";</div><div class='add'>+			reg = &lt;0 0x07140000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			cpu = &lt;&amp;cpu1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			arm,coresight-loses-context-with-cpu;</div><div class='add'>+			qcom,skip-power-up;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					etm1_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;apss_funnel_in1&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		etm@7240000 {</div><div class='add'>+			compatible = "arm,coresight-etm4x", "arm,primecell";</div><div class='add'>+			reg = &lt;0 0x07240000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			cpu = &lt;&amp;cpu2&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			arm,coresight-loses-context-with-cpu;</div><div class='add'>+			qcom,skip-power-up;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					etm2_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;apss_funnel_in2&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		etm@7340000 {</div><div class='add'>+			compatible = "arm,coresight-etm4x", "arm,primecell";</div><div class='add'>+			reg = &lt;0 0x07340000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			cpu = &lt;&amp;cpu3&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			arm,coresight-loses-context-with-cpu;</div><div class='add'>+			qcom,skip-power-up;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					etm3_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;apss_funnel_in3&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		etm@7440000 {</div><div class='add'>+			compatible = "arm,coresight-etm4x", "arm,primecell";</div><div class='add'>+			reg = &lt;0 0x07440000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			cpu = &lt;&amp;cpu4&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			arm,coresight-loses-context-with-cpu;</div><div class='add'>+			qcom,skip-power-up;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					etm4_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;apss_funnel_in4&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		etm@7540000 {</div><div class='add'>+			compatible = "arm,coresight-etm4x", "arm,primecell";</div><div class='add'>+			reg = &lt;0 0x07540000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			cpu = &lt;&amp;cpu5&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			arm,coresight-loses-context-with-cpu;</div><div class='add'>+			qcom,skip-power-up;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					etm5_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;apss_funnel_in5&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		etm@7640000 {</div><div class='add'>+			compatible = "arm,coresight-etm4x", "arm,primecell";</div><div class='add'>+			reg = &lt;0 0x07640000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			cpu = &lt;&amp;cpu6&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			arm,coresight-loses-context-with-cpu;</div><div class='add'>+			qcom,skip-power-up;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					etm6_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;apss_funnel_in6&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		etm@7740000 {</div><div class='add'>+			compatible = "arm,coresight-etm4x", "arm,primecell";</div><div class='add'>+			reg = &lt;0 0x07740000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			cpu = &lt;&amp;cpu7&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			arm,coresight-loses-context-with-cpu;</div><div class='add'>+			qcom,skip-power-up;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					etm7_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;apss_funnel_in7&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		funnel@7800000 { /* APSS Funnel */</div><div class='add'>+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";</div><div class='add'>+			reg = &lt;0 0x07800000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					apss_funnel_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;apss_merge_funnel_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					apss_funnel_in0: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;etm0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					apss_funnel_in1: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;etm1_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@2 {</div><div class='add'>+					reg = &lt;2&gt;;</div><div class='add'>+					apss_funnel_in2: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;etm2_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@3 {</div><div class='add'>+					reg = &lt;3&gt;;</div><div class='add'>+					apss_funnel_in3: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;etm3_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@4 {</div><div class='add'>+					reg = &lt;4&gt;;</div><div class='add'>+					apss_funnel_in4: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;etm4_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@5 {</div><div class='add'>+					reg = &lt;5&gt;;</div><div class='add'>+					apss_funnel_in5: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;etm5_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@6 {</div><div class='add'>+					reg = &lt;6&gt;;</div><div class='add'>+					apss_funnel_in6: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;etm6_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@7 {</div><div class='add'>+					reg = &lt;7&gt;;</div><div class='add'>+					apss_funnel_in7: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;etm7_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		funnel@7810000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";</div><div class='add'>+			reg = &lt;0 0x07810000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					apss_merge_funnel_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;funnel1_in4&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				port {</div><div class='add'>+					apss_merge_funnel_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;apss_funnel_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sdhc_2: mmc@8804000 {</div><div class='add'>+			compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";</div><div class='add'>+			pinctrl-names = "default", "sleep";</div><div class='add'>+			pinctrl-0 = &lt;&amp;sdc2_clk&gt;, &lt;&amp;sdc2_cmd&gt;, &lt;&amp;sdc2_data&gt;;</div><div class='add'>+			pinctrl-1 = &lt;&amp;sdc2_clk_sleep&gt;, &lt;&amp;sdc2_cmd_sleep&gt;, &lt;&amp;sdc2_data_sleep&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			reg = &lt;0 0x08804000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x100 0x0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "hc_irq", "pwr_irq";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_SDCC2_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_SDCC2_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;;</div><div class='add'>+			clock-names = "iface", "core", "xo";</div><div class='add'>+			interconnects = &lt;&amp;aggre1_noc MASTER_SDCC_2 0 &amp;mc_virt SLAVE_EBI1 0&gt;,</div><div class='add'>+					&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_SDCC_2 0&gt;;</div><div class='add'>+			interconnect-names = "sdhc-ddr","cpu-sdhc";</div><div class='add'>+			power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;sdhc2_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+			bus-width = &lt;4&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+</div><div class='add'>+			qcom,dll-config = &lt;0x0007642c&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_SDCC2_BCR&gt;;</div><div class='add'>+</div><div class='add'>+			sdhc2_opp_table: opp-table {</div><div class='add'>+				compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+				opp-100000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;100000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;1800000 400000&gt;;</div><div class='add'>+					opp-avg-kBps = &lt;100000 0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-202000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;202000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_nom&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;5400000 1600000&gt;;</div><div class='add'>+					opp-avg-kBps = &lt;200000 0&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_1_hsphy: phy@88e3000 {</div><div class='add'>+			compatible = "qcom,sc7280-usb-hs-phy",</div><div class='add'>+				     "qcom,usb-snps-hs-7nm-phy";</div><div class='add'>+			reg = &lt;0 0x088e3000 0 0x400&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;;</div><div class='add'>+			clock-names = "ref";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_QUSB2PHY_PRIM_BCR&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_2_hsphy: phy@88e4000 {</div><div class='add'>+			compatible = "qcom,sc7280-usb-hs-phy",</div><div class='add'>+				     "qcom,usb-snps-hs-7nm-phy";</div><div class='add'>+			reg = &lt;0 0x088e4000 0 0x400&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;;</div><div class='add'>+			clock-names = "ref";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_QUSB2PHY_SEC_BCR&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		refgen: regulator@88e7000 {</div><div class='add'>+			compatible = "qcom,sc7280-refgen-regulator",</div><div class='add'>+				     "qcom,sm8250-refgen-regulator";</div><div class='add'>+			reg = &lt;0x0 0x088e7000 0x0 0x84&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_1_qmpphy: phy@88e8000 {</div><div class='add'>+			compatible = "qcom,sc7280-qmp-usb3-dp-phy";</div><div class='add'>+			reg = &lt;0 0x088e8000 0 0x3000&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_USB3_PRIM_PHY_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB3_PRIM_PHY_PIPE_CLK&gt;;</div><div class='add'>+			clock-names = "aux",</div><div class='add'>+				      "ref",</div><div class='add'>+				      "com_aux",</div><div class='add'>+				      "usb3_pipe";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_USB3_DP_PHY_PRIM_BCR&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB3_PHY_PRIM_BCR&gt;;</div><div class='add'>+			reset-names = "phy", "common";</div><div class='add'>+</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#phy-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			orientation-switch;</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					usb_dp_qmpphy_out: endpoint {</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					usb_dp_qmpphy_usb_ss_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;usb_1_dwc3_ss&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@2 {</div><div class='add'>+					reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+					usb_dp_qmpphy_dp_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;mdss_dp_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_2: usb@8c00000 {</div><div class='add'>+			compatible = "qcom,sc7280-dwc3", "qcom,snps-dwc3";</div><div class='add'>+			reg = &lt;0 0x08c00000 0 0xfc100&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB30_SEC_MASTER_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_AGGRE_USB3_SEC_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB30_SEC_SLEEP_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB30_SEC_MOCK_UTMI_CLK&gt;;</div><div class='add'>+			clock-names = "cfg_noc",</div><div class='add'>+				      "core",</div><div class='add'>+				      "iface",</div><div class='add'>+				      "sleep",</div><div class='add'>+				      "mock_utmi";</div><div class='add'>+</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_USB30_SEC_MOCK_UTMI_CLK&gt;,</div><div class='add'>+					  &lt;&amp;gcc GCC_USB30_SEC_MASTER_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;19200000&gt;, &lt;200000000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts-extended = &lt;&amp;intc GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;intc GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;pdc 12 IRQ_TYPE_EDGE_BOTH&gt;,</div><div class='add'>+					      &lt;&amp;pdc 13 IRQ_TYPE_EDGE_BOTH&gt;;</div><div class='add'>+			interrupt-names = "dwc_usb3",</div><div class='add'>+					  "pwr_event",</div><div class='add'>+					  "hs_phy_irq",</div><div class='add'>+					  "dp_hs_phy_irq",</div><div class='add'>+					  "dm_hs_phy_irq";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;gcc GCC_USB30_SEC_GDSC&gt;;</div><div class='add'>+			required-opps = &lt;&amp;rpmhpd_opp_nom&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_USB30_SEC_BCR&gt;;</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;aggre1_noc MASTER_USB2 0 &amp;mc_virt SLAVE_EBI1 0&gt;,</div><div class='add'>+					&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_USB2 0&gt;;</div><div class='add'>+			interconnect-names = "usb-ddr", "apps-usb";</div><div class='add'>+</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0xa0 0x0&gt;;</div><div class='add'>+			snps,dis_u2_susphy_quirk;</div><div class='add'>+			snps,dis_enblslpm_quirk;</div><div class='add'>+			snps,dis-u1-entry-quirk;</div><div class='add'>+			snps,dis-u2-entry-quirk;</div><div class='add'>+			phys = &lt;&amp;usb_2_hsphy&gt;;</div><div class='add'>+			phy-names = "usb2-phy";</div><div class='add'>+			maximum-speed = "high-speed";</div><div class='add'>+			usb-role-switch;</div><div class='add'>+</div><div class='add'>+			port {</div><div class='add'>+				usb2_role_switch: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;eud_ep&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qspi: spi@88dc000 {</div><div class='add'>+			compatible = "qcom,sc7280-qspi", "qcom,qspi-v1";</div><div class='add'>+			reg = &lt;0 0x088dc000 0 0x1000&gt;;</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x20 0x0&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_QSPI_CORE_CLK&gt;;</div><div class='add'>+			clock-names = "iface", "core";</div><div class='add'>+			interconnects = &lt;&amp;gem_noc MASTER_APPSS_PROC 0</div><div class='add'>+					&amp;cnoc2 SLAVE_QSPI_0 0&gt;;</div><div class='add'>+			interconnect-names = "qspi-config";</div><div class='add'>+			power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;qspi_opp_table&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		remoteproc_adsp: remoteproc@3700000 {</div><div class='add'>+			compatible = "qcom,sc7280-adsp-pas";</div><div class='add'>+			reg = &lt;0 0x03700000 0 0x100&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts-extended = &lt;&amp;pdc 6 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;adsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			interrupt-names = "wdog", "fatal", "ready", "handover",</div><div class='add'>+					  "stop-ack", "shutdown-ack";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;;</div><div class='add'>+			clock-names = "xo";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;rpmhpd SC7280_LCX&gt;,</div><div class='add'>+					&lt;&amp;rpmhpd SC7280_LMX&gt;;</div><div class='add'>+			power-domain-names = "lcx", "lmx";</div><div class='add'>+</div><div class='add'>+			memory-region = &lt;&amp;adsp_mem&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,qmp = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,smem-states = &lt;&amp;adsp_smp2p_out 0&gt;;</div><div class='add'>+			qcom,smem-state-names = "stop";</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			remoteproc_adsp_glink: glink-edge {</div><div class='add'>+				interrupts-extended = &lt;&amp;ipcc IPCC_CLIENT_LPASS</div><div class='add'>+							     IPCC_MPROC_SIGNAL_GLINK_QMP</div><div class='add'>+							     IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+</div><div class='add'>+				mboxes = &lt;&amp;ipcc IPCC_CLIENT_LPASS</div><div class='add'>+						IPCC_MPROC_SIGNAL_GLINK_QMP&gt;;</div><div class='add'>+</div><div class='add'>+				label = "lpass";</div><div class='add'>+				qcom,remote-pid = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+				apr {</div><div class='add'>+					compatible = "qcom,apr-v2";</div><div class='add'>+					qcom,glink-channels = "apr_audio_svc";</div><div class='add'>+					qcom,domain = &lt;APR_DOMAIN_ADSP&gt;;</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					service@3 {</div><div class='add'>+						reg = &lt;APR_SVC_ADSP_CORE&gt;;</div><div class='add'>+						compatible = "qcom,q6core";</div><div class='add'>+						qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					q6afe: service@4 {</div><div class='add'>+						compatible = "qcom,q6afe";</div><div class='add'>+						reg = &lt;APR_SVC_AFE&gt;;</div><div class='add'>+						qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";</div><div class='add'>+</div><div class='add'>+						q6afedai: dais {</div><div class='add'>+							compatible = "qcom,q6afe-dais";</div><div class='add'>+							#address-cells = &lt;1&gt;;</div><div class='add'>+							#size-cells = &lt;0&gt;;</div><div class='add'>+							#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						q6afecc: clock-controller {</div><div class='add'>+							compatible = "qcom,q6afe-clocks";</div><div class='add'>+							#clock-cells = &lt;2&gt;;</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						q6usbdai: usbd {</div><div class='add'>+							compatible = "qcom,q6usb";</div><div class='add'>+							iommus = &lt;&amp;apps_smmu 0x180f 0x0&gt;;</div><div class='add'>+							#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+							qcom,usb-audio-intr-idx = /bits/ 16 &lt;2&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					q6asm: service@7 {</div><div class='add'>+						compatible = "qcom,q6asm";</div><div class='add'>+						reg = &lt;APR_SVC_ASM&gt;;</div><div class='add'>+						qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";</div><div class='add'>+</div><div class='add'>+						q6asmdai: dais {</div><div class='add'>+							compatible = "qcom,q6asm-dais";</div><div class='add'>+							#address-cells = &lt;1&gt;;</div><div class='add'>+							#size-cells = &lt;0&gt;;</div><div class='add'>+							#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+							iommus = &lt;&amp;apps_smmu 0x1801 0x0&gt;;</div><div class='add'>+</div><div class='add'>+							dai@0 {</div><div class='add'>+								reg = &lt;MSM_FRONTEND_DAI_MULTIMEDIA1&gt;;</div><div class='add'>+							};</div><div class='add'>+</div><div class='add'>+							dai@1 {</div><div class='add'>+								reg = &lt;MSM_FRONTEND_DAI_MULTIMEDIA2&gt;;</div><div class='add'>+							};</div><div class='add'>+</div><div class='add'>+							dai@2 {</div><div class='add'>+								reg = &lt;MSM_FRONTEND_DAI_MULTIMEDIA3&gt;;</div><div class='add'>+							};</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					q6adm: service@8 {</div><div class='add'>+						compatible = "qcom,q6adm";</div><div class='add'>+						reg = &lt;APR_SVC_ADM&gt;;</div><div class='add'>+						qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";</div><div class='add'>+</div><div class='add'>+						q6routing: routing {</div><div class='add'>+							compatible = "qcom,q6adm-routing";</div><div class='add'>+							#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				fastrpc {</div><div class='add'>+					compatible = "qcom,fastrpc";</div><div class='add'>+					qcom,glink-channels = "fastrpcglink-apps-dsp";</div><div class='add'>+					label = "adsp";</div><div class='add'>+					qcom,non-secure-domain;</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					compute-cb@3 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;3&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x1803 0x0&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@4 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;4&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x1804 0x0&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@5 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;5&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x1805 0x0&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		remoteproc_wpss: remoteproc@8a00000 {</div><div class='add'>+			compatible = "qcom,sc7280-wpss-pas";</div><div class='add'>+			reg = &lt;0 0x08a00000 0 0x10000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts-extended = &lt;&amp;intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			interrupt-names = "wdog", "fatal", "ready", "handover",</div><div class='add'>+					  "stop-ack", "shutdown-ack";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;;</div><div class='add'>+			clock-names = "xo";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;,</div><div class='add'>+					&lt;&amp;rpmhpd SC7280_MX&gt;;</div><div class='add'>+			power-domain-names = "cx", "mx";</div><div class='add'>+</div><div class='add'>+			memory-region = &lt;&amp;wpss_mem&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,qmp = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,smem-states = &lt;&amp;wpss_smp2p_out 0&gt;;</div><div class='add'>+			qcom,smem-state-names = "stop";</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			glink-edge {</div><div class='add'>+				interrupts-extended = &lt;&amp;ipcc IPCC_CLIENT_WPSS</div><div class='add'>+							     IPCC_MPROC_SIGNAL_GLINK_QMP</div><div class='add'>+							     IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				mboxes = &lt;&amp;ipcc IPCC_CLIENT_WPSS</div><div class='add'>+						IPCC_MPROC_SIGNAL_GLINK_QMP&gt;;</div><div class='add'>+</div><div class='add'>+				label = "wpss";</div><div class='add'>+				qcom,remote-pid = &lt;13&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmu@9091000 {</div><div class='add'>+			compatible = "qcom,sc7280-llcc-bwmon";</div><div class='add'>+			reg = &lt;0 0x09091000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;mc_virt MASTER_LLCC 3 &amp;mc_virt SLAVE_EBI1 3&gt;;</div><div class='add'>+</div><div class='add'>+			operating-points-v2 = &lt;&amp;llcc_bwmon_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+			llcc_bwmon_opp_table: opp-table {</div><div class='add'>+				compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+				opp-0 {</div><div class='add'>+					opp-peak-kBps = &lt;800000&gt;;</div><div class='add'>+				};</div><div class='add'>+				opp-1 {</div><div class='add'>+					opp-peak-kBps = &lt;1804000&gt;;</div><div class='add'>+				};</div><div class='add'>+				opp-2 {</div><div class='add'>+					opp-peak-kBps = &lt;2188000&gt;;</div><div class='add'>+				};</div><div class='add'>+				opp-3 {</div><div class='add'>+					opp-peak-kBps = &lt;3072000&gt;;</div><div class='add'>+				};</div><div class='add'>+				opp-4 {</div><div class='add'>+					opp-peak-kBps = &lt;4068000&gt;;</div><div class='add'>+				};</div><div class='add'>+				opp-5 {</div><div class='add'>+					opp-peak-kBps = &lt;6220000&gt;;</div><div class='add'>+				};</div><div class='add'>+				opp-6 {</div><div class='add'>+					opp-peak-kBps = &lt;6832000&gt;;</div><div class='add'>+				};</div><div class='add'>+				opp-7 {</div><div class='add'>+					opp-peak-kBps = &lt;8532000&gt;;</div><div class='add'>+				};</div><div class='add'>+				opp-8 {</div><div class='add'>+					opp-peak-kBps = &lt;10944000&gt;;</div><div class='add'>+				};</div><div class='add'>+				opp-9 {</div><div class='add'>+					opp-peak-kBps = &lt;12787200&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmu@90b6400 {</div><div class='add'>+			compatible = "qcom,sc7280-cpu-bwmon", "qcom,sdm845-bwmon";</div><div class='add'>+			reg = &lt;0 0x090b6400 0 0x600&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;gem_noc MASTER_APPSS_PROC 3 &amp;gem_noc SLAVE_LLCC 3&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu_bwmon_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+			cpu_bwmon_opp_table: opp-table {</div><div class='add'>+				compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+				opp-0 {</div><div class='add'>+					opp-peak-kBps = &lt;2400000&gt;;</div><div class='add'>+				};</div><div class='add'>+				opp-1 {</div><div class='add'>+					opp-peak-kBps = &lt;4800000&gt;;</div><div class='add'>+				};</div><div class='add'>+				opp-2 {</div><div class='add'>+					opp-peak-kBps = &lt;7456000&gt;;</div><div class='add'>+				};</div><div class='add'>+				opp-3 {</div><div class='add'>+					opp-peak-kBps = &lt;9600000&gt;;</div><div class='add'>+				};</div><div class='add'>+				opp-4 {</div><div class='add'>+					opp-peak-kBps = &lt;12896000&gt;;</div><div class='add'>+				};</div><div class='add'>+				opp-5 {</div><div class='add'>+					opp-peak-kBps = &lt;14928000&gt;;</div><div class='add'>+				};</div><div class='add'>+				opp-6 {</div><div class='add'>+					opp-peak-kBps = &lt;17056000&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dc_noc: interconnect@90e0000 {</div><div class='add'>+			reg = &lt;0 0x090e0000 0 0x5080&gt;;</div><div class='add'>+			compatible = "qcom,sc7280-dc-noc";</div><div class='add'>+			#interconnect-cells = &lt;2&gt;;</div><div class='add'>+			qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gem_noc: interconnect@9100000 {</div><div class='add'>+			reg = &lt;0 0x09100000 0 0xe2200&gt;;</div><div class='add'>+			compatible = "qcom,sc7280-gem-noc";</div><div class='add'>+			#interconnect-cells = &lt;2&gt;;</div><div class='add'>+			qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		system-cache-controller@9200000 {</div><div class='add'>+			compatible = "qcom,sc7280-llcc";</div><div class='add'>+			reg = &lt;0 0x09200000 0 0x58000&gt;, &lt;0 0x09280000 0 0x58000&gt;,</div><div class='add'>+			      &lt;0 0x09600000 0 0x58000&gt;;</div><div class='add'>+			reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base";</div><div class='add'>+			interrupts = &lt;GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		eud: eud@88e0000 {</div><div class='add'>+			compatible = "qcom,sc7280-eud", "qcom,eud";</div><div class='add'>+			reg = &lt;0 0x88e0000 0 0x2000&gt;,</div><div class='add'>+			      &lt;0 0x88e2000 0 0x1000&gt;;</div><div class='add'>+			interrupts-extended = &lt;&amp;pdc 11 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					eud_ep: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;usb2_role_switch&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nsp_noc: interconnect@a0c0000 {</div><div class='add'>+			reg = &lt;0 0x0a0c0000 0 0x10000&gt;;</div><div class='add'>+			compatible = "qcom,sc7280-nsp-noc";</div><div class='add'>+			#interconnect-cells = &lt;2&gt;;</div><div class='add'>+			qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		remoteproc_cdsp: remoteproc@a300000 {</div><div class='add'>+			compatible = "qcom,sc7280-cdsp-pas";</div><div class='add'>+			reg = &lt;0 0x0a300000 0 0x10000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts-extended = &lt;&amp;intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;cdsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			interrupt-names = "wdog", "fatal", "ready", "handover",</div><div class='add'>+					  "stop-ack", "shutdown-ack";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;;</div><div class='add'>+			clock-names = "xo";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;,</div><div class='add'>+					&lt;&amp;rpmhpd SC7280_MX&gt;;</div><div class='add'>+			power-domain-names = "cx", "mx";</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;nsp_noc MASTER_CDSP_PROC 0 &amp;mc_virt SLAVE_EBI1 0&gt;;</div><div class='add'>+</div><div class='add'>+			memory-region = &lt;&amp;cdsp_mem&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,qmp = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,smem-states = &lt;&amp;cdsp_smp2p_out 0&gt;;</div><div class='add'>+			qcom,smem-state-names = "stop";</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			glink-edge {</div><div class='add'>+				interrupts-extended = &lt;&amp;ipcc IPCC_CLIENT_CDSP</div><div class='add'>+							     IPCC_MPROC_SIGNAL_GLINK_QMP</div><div class='add'>+							     IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				mboxes = &lt;&amp;ipcc IPCC_CLIENT_CDSP</div><div class='add'>+						IPCC_MPROC_SIGNAL_GLINK_QMP&gt;;</div><div class='add'>+</div><div class='add'>+				label = "cdsp";</div><div class='add'>+				qcom,remote-pid = &lt;5&gt;;</div><div class='add'>+</div><div class='add'>+				fastrpc {</div><div class='add'>+					compatible = "qcom,fastrpc";</div><div class='add'>+					qcom,glink-channels = "fastrpcglink-apps-dsp";</div><div class='add'>+					label = "cdsp";</div><div class='add'>+					qcom,non-secure-domain;</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					compute-cb@1 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x11a1 0x0420&gt;,</div><div class='add'>+							 &lt;&amp;apps_smmu 0x1181 0x0420&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@2 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;2&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x11a2 0x0420&gt;,</div><div class='add'>+							 &lt;&amp;apps_smmu 0x1182 0x0420&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@3 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;3&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x11a3 0x0420&gt;,</div><div class='add'>+							 &lt;&amp;apps_smmu 0x1183 0x0420&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@4 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;4&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x11a4 0x0420&gt;,</div><div class='add'>+							 &lt;&amp;apps_smmu 0x1184 0x0420&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@5 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;5&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x11a5 0x0420&gt;,</div><div class='add'>+							 &lt;&amp;apps_smmu 0x1185 0x0420&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@6 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;6&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x11a6 0x0420&gt;,</div><div class='add'>+							 &lt;&amp;apps_smmu 0x1186 0x0420&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@7 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;7&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x11a7 0x0420&gt;,</div><div class='add'>+							 &lt;&amp;apps_smmu 0x1187 0x0420&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@8 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;8&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x11a8 0x0420&gt;,</div><div class='add'>+							 &lt;&amp;apps_smmu 0x1188 0x0420&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					/* note: secure cb9 in downstream */</div><div class='add'>+</div><div class='add'>+					compute-cb@11 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;11&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x11ab 0x0420&gt;,</div><div class='add'>+							 &lt;&amp;apps_smmu 0x118b 0x0420&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@12 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;12&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x11ac 0x0420&gt;,</div><div class='add'>+							 &lt;&amp;apps_smmu 0x118c 0x0420&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@13 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;13&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x11ad 0x0420&gt;,</div><div class='add'>+							 &lt;&amp;apps_smmu 0x118d 0x0420&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@14 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;14&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x11ae 0x0420&gt;,</div><div class='add'>+							 &lt;&amp;apps_smmu 0x118e 0x0420&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_1: usb@a600000 {</div><div class='add'>+			compatible = "qcom,sc7280-dwc3", "qcom,snps-dwc3";</div><div class='add'>+			reg = &lt;0 0x0a600000 0 0xfc100&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB30_PRIM_MASTER_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_AGGRE_USB3_PRIM_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB30_PRIM_SLEEP_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB30_PRIM_MOCK_UTMI_CLK&gt;;</div><div class='add'>+			clock-names = "cfg_noc",</div><div class='add'>+				      "core",</div><div class='add'>+				      "iface",</div><div class='add'>+				      "sleep",</div><div class='add'>+				      "mock_utmi";</div><div class='add'>+</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_USB30_PRIM_MOCK_UTMI_CLK&gt;,</div><div class='add'>+					  &lt;&amp;gcc GCC_USB30_PRIM_MASTER_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;19200000&gt;, &lt;200000000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts-extended = &lt;&amp;intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;pdc 14 IRQ_TYPE_EDGE_BOTH&gt;,</div><div class='add'>+					      &lt;&amp;pdc 15 IRQ_TYPE_EDGE_BOTH&gt;,</div><div class='add'>+					      &lt;&amp;pdc 17 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "dwc_usb3",</div><div class='add'>+					  "pwr_event",</div><div class='add'>+					  "hs_phy_irq",</div><div class='add'>+					  "dp_hs_phy_irq",</div><div class='add'>+					  "dm_hs_phy_irq",</div><div class='add'>+					  "ss_phy_irq";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;gcc GCC_USB30_PRIM_GDSC&gt;;</div><div class='add'>+			required-opps = &lt;&amp;rpmhpd_opp_nom&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_USB30_PRIM_BCR&gt;;</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;aggre1_noc MASTER_USB3_0 0 &amp;mc_virt SLAVE_EBI1 0&gt;,</div><div class='add'>+					&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_USB3_0 0&gt;;</div><div class='add'>+			interconnect-names = "usb-ddr", "apps-usb";</div><div class='add'>+</div><div class='add'>+			wakeup-source;</div><div class='add'>+</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0xe0 0x0&gt;;</div><div class='add'>+			snps,dis_u2_susphy_quirk;</div><div class='add'>+			snps,dis_enblslpm_quirk;</div><div class='add'>+			snps,parkmode-disable-ss-quirk;</div><div class='add'>+			snps,dis-u1-entry-quirk;</div><div class='add'>+			snps,dis-u2-entry-quirk;</div><div class='add'>+			num-hc-interrupters = /bits/ 16 &lt;3&gt;;</div><div class='add'>+			phys = &lt;&amp;usb_1_hsphy&gt;, &lt;&amp;usb_1_qmpphy QMP_USB43DP_USB3_PHY&gt;;</div><div class='add'>+			phy-names = "usb2-phy", "usb3-phy";</div><div class='add'>+			maximum-speed = "super-speed";</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					usb_1_dwc3_hs: endpoint {</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					usb_1_dwc3_ss: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;usb_dp_qmpphy_usb_ss_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		venus: video-codec@aa00000 {</div><div class='add'>+			compatible = "qcom,sc7280-venus";</div><div class='add'>+			reg = &lt;0 0x0aa00000 0 0xd0600&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;videocc VIDEO_CC_MVSC_CORE_CLK&gt;,</div><div class='add'>+				 &lt;&amp;videocc VIDEO_CC_MVSC_CTL_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;videocc VIDEO_CC_VENUS_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;videocc VIDEO_CC_MVS0_CORE_CLK&gt;,</div><div class='add'>+				 &lt;&amp;videocc VIDEO_CC_MVS0_AXI_CLK&gt;;</div><div class='add'>+			clock-names = "core", "bus", "iface",</div><div class='add'>+				      "vcodec_core", "vcodec_bus";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;videocc MVSC_GDSC&gt;,</div><div class='add'>+					&lt;&amp;videocc MVS0_GDSC&gt;,</div><div class='add'>+					&lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+			power-domain-names = "venus", "vcodec0", "cx";</div><div class='add'>+			operating-points-v2 = &lt;&amp;venus_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;cnoc2 SLAVE_VENUS_CFG 0&gt;,</div><div class='add'>+					&lt;&amp;mmss_noc MASTER_VIDEO_P0 0 &amp;mc_virt SLAVE_EBI1 0&gt;;</div><div class='add'>+			interconnect-names = "cpu-cfg", "video-mem";</div><div class='add'>+</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x2180 0x20&gt;;</div><div class='add'>+			memory-region = &lt;&amp;video_mem&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			venus_opp_table: opp-table {</div><div class='add'>+				compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+				opp-133330000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;133330000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-240000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;240000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_svs&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-335000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;335000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_svs_l1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-424000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;424000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_nom&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-460000048 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;460000048&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_turbo&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		videocc: clock-controller@aaf0000 {</div><div class='add'>+			compatible = "qcom,sc7280-videocc";</div><div class='add'>+			reg = &lt;0 0x0aaf0000 0 0x10000&gt;;</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;,</div><div class='add'>+				&lt;&amp;rpmhcc RPMH_CXO_CLK_A&gt;;</div><div class='add'>+			clock-names = "bi_tcxo", "bi_tcxo_ao";</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cci0: cci@ac4a000 {</div><div class='add'>+			compatible = "qcom,sc7280-cci", "qcom,msm8996-cci";</div><div class='add'>+			reg = &lt;0 0x0ac4a000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 460 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			power-domains = &lt;&amp;camcc CAM_CC_TITAN_TOP_GDSC&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;camcc CAM_CC_CAMNOC_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_SLOW_AHB_CLK_SRC&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_CPAS_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_CCI_0_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_CCI_0_CLK_SRC&gt;;</div><div class='add'>+			clock-names = "camnoc_axi",</div><div class='add'>+				      "slow_ahb_src",</div><div class='add'>+				      "cpas_ahb",</div><div class='add'>+				      "cci",</div><div class='add'>+				      "cci_src";</div><div class='add'>+			pinctrl-0 = &lt;&amp;cci0_default &amp;cci1_default&gt;;</div><div class='add'>+			pinctrl-1 = &lt;&amp;cci0_sleep &amp;cci1_sleep&gt;;</div><div class='add'>+			pinctrl-names = "default", "sleep";</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			cci0_i2c0: i2c-bus@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				clock-frequency = &lt;1000000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cci0_i2c1: i2c-bus@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				clock-frequency = &lt;1000000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cci1: cci@ac4b000 {</div><div class='add'>+			compatible = "qcom,sc7280-cci", "qcom,msm8996-cci";</div><div class='add'>+			reg = &lt;0 0x0ac4b000 0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 271 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			power-domains = &lt;&amp;camcc CAM_CC_TITAN_TOP_GDSC&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;camcc CAM_CC_CAMNOC_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_SLOW_AHB_CLK_SRC&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_CPAS_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_CCI_1_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_CCI_1_CLK_SRC&gt;;</div><div class='add'>+			clock-names = "camnoc_axi",</div><div class='add'>+				      "slow_ahb_src",</div><div class='add'>+				      "cpas_ahb",</div><div class='add'>+				      "cci",</div><div class='add'>+				      "cci_src";</div><div class='add'>+			pinctrl-0 = &lt;&amp;cci2_default &amp;cci3_default&gt;;</div><div class='add'>+			pinctrl-1 = &lt;&amp;cci2_sleep &amp;cci3_sleep&gt;;</div><div class='add'>+			pinctrl-names = "default", "sleep";</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			cci1_i2c0: i2c-bus@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				clock-frequency = &lt;1000000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cci1_i2c1: i2c-bus@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				clock-frequency = &lt;1000000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		camss: isp@acb3000 {</div><div class='add'>+			compatible = "qcom,sc7280-camss";</div><div class='add'>+</div><div class='add'>+			reg = &lt;0x0 0x0acb3000 0x0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0x0acba000 0x0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0x0acc1000 0x0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0x0acc8000 0x0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0x0accf000 0x0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0x0ace0000 0x0 0x2000&gt;,</div><div class='add'>+			      &lt;0x0 0x0ace2000 0x0 0x2000&gt;,</div><div class='add'>+			      &lt;0x0 0x0ace4000 0x0 0x2000&gt;,</div><div class='add'>+			      &lt;0x0 0x0ace6000 0x0 0x2000&gt;,</div><div class='add'>+			      &lt;0x0 0x0ace8000 0x0 0x2000&gt;,</div><div class='add'>+			      &lt;0x0 0x0acaf000 0x0 0x4000&gt;,</div><div class='add'>+			      &lt;0x0 0x0acb6000 0x0 0x4000&gt;,</div><div class='add'>+			      &lt;0x0 0x0acbd000 0x0 0x4000&gt;,</div><div class='add'>+			      &lt;0x0 0x0acc4000 0x0 0x4000&gt;,</div><div class='add'>+			      &lt;0x0 0x0accb000 0x0 0x4000&gt;;</div><div class='add'>+			reg-names = "csid0",</div><div class='add'>+				    "csid1",</div><div class='add'>+				    "csid2",</div><div class='add'>+				    "csid_lite0",</div><div class='add'>+				    "csid_lite1",</div><div class='add'>+				    "csiphy0",</div><div class='add'>+				    "csiphy1",</div><div class='add'>+				    "csiphy2",</div><div class='add'>+				    "csiphy3",</div><div class='add'>+				    "csiphy4",</div><div class='add'>+				    "vfe0",</div><div class='add'>+				    "vfe1",</div><div class='add'>+				    "vfe2",</div><div class='add'>+				    "vfe_lite0",</div><div class='add'>+				    "vfe_lite1";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;camcc CAM_CC_CAMNOC_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_CPAS_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_CSIPHY0_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_CSI0PHYTIMER_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_CSIPHY1_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_CSI1PHYTIMER_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_CSIPHY2_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_CSI2PHYTIMER_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_CSIPHY3_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_CSI3PHYTIMER_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_CSIPHY4_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_CSI4PHYTIMER_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_CAMERA_HF_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_CAMERA_SF_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_ICP_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_IFE_0_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_IFE_0_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_IFE_0_CPHY_RX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_IFE_0_CSID_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_IFE_1_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_IFE_1_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_IFE_1_CPHY_RX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_IFE_1_CSID_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_IFE_2_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_IFE_2_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_IFE_2_CPHY_RX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_IFE_2_CSID_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_IFE_LITE_0_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_IFE_LITE_0_CPHY_RX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_IFE_LITE_0_CSID_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_IFE_LITE_1_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_IFE_LITE_1_CPHY_RX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_IFE_LITE_1_CSID_CLK&gt;;</div><div class='add'>+			clock-names = "camnoc_axi",</div><div class='add'>+				      "cpas_ahb",</div><div class='add'>+				      "csiphy0",</div><div class='add'>+				      "csiphy0_timer",</div><div class='add'>+				      "csiphy1",</div><div class='add'>+				      "csiphy1_timer",</div><div class='add'>+				      "csiphy2",</div><div class='add'>+				      "csiphy2_timer",</div><div class='add'>+				      "csiphy3",</div><div class='add'>+				      "csiphy3_timer",</div><div class='add'>+				      "csiphy4",</div><div class='add'>+				      "csiphy4_timer",</div><div class='add'>+				      "gcc_axi_hf",</div><div class='add'>+				      "gcc_axi_sf",</div><div class='add'>+				      "icp_ahb",</div><div class='add'>+				      "vfe0",</div><div class='add'>+				      "vfe0_axi",</div><div class='add'>+				      "vfe0_cphy_rx",</div><div class='add'>+				      "vfe0_csid",</div><div class='add'>+				      "vfe1",</div><div class='add'>+				      "vfe1_axi",</div><div class='add'>+				      "vfe1_cphy_rx",</div><div class='add'>+				      "vfe1_csid",</div><div class='add'>+				      "vfe2",</div><div class='add'>+				      "vfe2_axi",</div><div class='add'>+				      "vfe2_cphy_rx",</div><div class='add'>+				      "vfe2_csid",</div><div class='add'>+				      "vfe_lite0",</div><div class='add'>+				      "vfe_lite0_cphy_rx",</div><div class='add'>+				      "vfe_lite0_csid",</div><div class='add'>+				      "vfe_lite1",</div><div class='add'>+				      "vfe_lite1_cphy_rx",</div><div class='add'>+				      "vfe_lite1_csid";</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 464 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 466 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 640 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 468 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 359 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 477 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 478 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 479 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 448 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 122 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 465 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 467 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 641 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 469 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 360 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			interrupt-names = "csid0",</div><div class='add'>+					  "csid1",</div><div class='add'>+					  "csid2",</div><div class='add'>+					  "csid_lite0",</div><div class='add'>+					  "csid_lite1",</div><div class='add'>+					  "csiphy0",</div><div class='add'>+					  "csiphy1",</div><div class='add'>+					  "csiphy2",</div><div class='add'>+					  "csiphy3",</div><div class='add'>+					  "csiphy4",</div><div class='add'>+					  "vfe0",</div><div class='add'>+					  "vfe1",</div><div class='add'>+					  "vfe2",</div><div class='add'>+					  "vfe_lite0",</div><div class='add'>+					  "vfe_lite1";</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;gem_noc  MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;cnoc2 SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+					&lt;&amp;mmss_noc MASTER_CAMNOC_HF  QCOM_ICC_TAG_ALWAYS</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+			interconnect-names = "ahb",</div><div class='add'>+					     "hf_0";</div><div class='add'>+</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x800 0x4e0&gt;;</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;camcc CAM_CC_IFE_0_GDSC&gt;,</div><div class='add'>+					&lt;&amp;camcc CAM_CC_IFE_1_GDSC&gt;,</div><div class='add'>+					&lt;&amp;camcc CAM_CC_IFE_2_GDSC&gt;,</div><div class='add'>+					&lt;&amp;camcc CAM_CC_TITAN_TOP_GDSC&gt;;</div><div class='add'>+			power-domain-names = "ife0",</div><div class='add'>+					     "ife1",</div><div class='add'>+					     "ife2",</div><div class='add'>+					     "top";</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@2 {</div><div class='add'>+					reg = &lt;2&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@3 {</div><div class='add'>+					reg = &lt;3&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@4 {</div><div class='add'>+					reg = &lt;4&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		camcc: clock-controller@ad00000 {</div><div class='add'>+			compatible = "qcom,sc7280-camcc";</div><div class='add'>+			reg = &lt;0 0x0ad00000 0 0x10000&gt;;</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;,</div><div class='add'>+				&lt;&amp;rpmhcc RPMH_CXO_CLK_A&gt;,</div><div class='add'>+				&lt;&amp;sleep_clk&gt;;</div><div class='add'>+			clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dispcc: clock-controller@af00000 {</div><div class='add'>+			compatible = "qcom,sc7280-dispcc";</div><div class='add'>+			reg = &lt;0 0x0af00000 0 0x20000&gt;;</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_DISP_GPLL0_CLK_SRC&gt;,</div><div class='add'>+				 &lt;&amp;mdss_dsi_phy DSI_BYTE_PLL_CLK&gt;,</div><div class='add'>+				 &lt;&amp;mdss_dsi_phy DSI_PIXEL_PLL_CLK&gt;,</div><div class='add'>+				 &lt;&amp;usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK&gt;,</div><div class='add'>+				 &lt;&amp;usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK&gt;,</div><div class='add'>+				 &lt;&amp;mdss_edp_phy 0&gt;,</div><div class='add'>+				 &lt;&amp;mdss_edp_phy 1&gt;;</div><div class='add'>+			clock-names = "bi_tcxo",</div><div class='add'>+				      "gcc_disp_gpll0_clk",</div><div class='add'>+				      "dsi0_phy_pll_out_byteclk",</div><div class='add'>+				      "dsi0_phy_pll_out_dsiclk",</div><div class='add'>+				      "dp_phy_pll_link_clk",</div><div class='add'>+				      "dp_phy_pll_vco_div_clk",</div><div class='add'>+				      "edp_phy_pll_link_clk",</div><div class='add'>+				      "edp_phy_pll_vco_div_clk";</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdss: display-subsystem@ae00000 {</div><div class='add'>+			compatible = "qcom,sc7280-mdss";</div><div class='add'>+			reg = &lt;0 0x0ae00000 0 0x1000&gt;;</div><div class='add'>+			reg-names = "mdss";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;dispcc DISP_CC_MDSS_CORE_GDSC&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_DISP_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;dispcc DISP_CC_MDSS_AHB_CLK&gt;,</div><div class='add'>+				&lt;&amp;dispcc DISP_CC_MDSS_MDP_CLK&gt;;</div><div class='add'>+			clock-names = "iface",</div><div class='add'>+				      "ahb",</div><div class='add'>+				      "core";</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+					&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+					 &amp;cnoc2 SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+			interconnect-names = "mdp0-mem",</div><div class='add'>+					     "cpu-cfg";</div><div class='add'>+</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x900 0x402&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;dispcc DISP_CC_MDSS_CORE_BCR&gt;;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			mdss_mdp: display-controller@ae01000 {</div><div class='add'>+				compatible = "qcom,sc7280-dpu";</div><div class='add'>+				reg = &lt;0 0x0ae01000 0 0x8f030&gt;,</div><div class='add'>+					&lt;0 0x0aeb0000 0 0x3000&gt;;</div><div class='add'>+				reg-names = "mdp", "vbif";</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_DISP_HF_AXI_CLK&gt;,</div><div class='add'>+					&lt;&amp;gcc GCC_DISP_SF_AXI_CLK&gt;,</div><div class='add'>+					&lt;&amp;dispcc DISP_CC_MDSS_AHB_CLK&gt;,</div><div class='add'>+					&lt;&amp;dispcc DISP_CC_MDSS_MDP_LUT_CLK&gt;,</div><div class='add'>+					&lt;&amp;dispcc DISP_CC_MDSS_MDP_CLK&gt;,</div><div class='add'>+					&lt;&amp;dispcc DISP_CC_MDSS_VSYNC_CLK&gt;;</div><div class='add'>+				clock-names = "bus",</div><div class='add'>+					      "nrt_bus",</div><div class='add'>+					      "iface",</div><div class='add'>+					      "lut",</div><div class='add'>+					      "core",</div><div class='add'>+					      "vsync";</div><div class='add'>+				assigned-clocks = &lt;&amp;dispcc DISP_CC_MDSS_VSYNC_CLK&gt;,</div><div class='add'>+						&lt;&amp;dispcc DISP_CC_MDSS_AHB_CLK&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;19200000&gt;,</div><div class='add'>+							&lt;19200000&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;mdp_opp_table&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+</div><div class='add'>+				interrupt-parent = &lt;&amp;mdss&gt;;</div><div class='add'>+				interrupts = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+						dpu_intf1_out: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mdss_dsi0_in&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+						dpu_intf5_out: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;edp_in&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@2 {</div><div class='add'>+						reg = &lt;2&gt;;</div><div class='add'>+						dpu_intf0_out: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;dp_in&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				mdp_opp_table: opp-table {</div><div class='add'>+					compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+					opp-200000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;200000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					opp-300000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;300000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_svs&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					opp-380000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;380000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_svs_l1&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					opp-506666667 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;506666667&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_nom&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					opp-608000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;608000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_turbo&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mdss_dsi: dsi@ae94000 {</div><div class='add'>+				compatible = "qcom,sc7280-dsi-ctrl",</div><div class='add'>+					     "qcom,mdss-dsi-ctrl";</div><div class='add'>+				reg = &lt;0 0x0ae94000 0 0x400&gt;;</div><div class='add'>+				reg-names = "dsi_ctrl";</div><div class='add'>+</div><div class='add'>+				interrupt-parent = &lt;&amp;mdss&gt;;</div><div class='add'>+				interrupts = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;dispcc DISP_CC_MDSS_BYTE0_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc DISP_CC_MDSS_BYTE0_INTF_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc DISP_CC_MDSS_PCLK0_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc DISP_CC_MDSS_ESC0_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc DISP_CC_MDSS_AHB_CLK&gt;,</div><div class='add'>+					 &lt;&amp;gcc GCC_DISP_HF_AXI_CLK&gt;;</div><div class='add'>+				clock-names = "byte",</div><div class='add'>+					      "byte_intf",</div><div class='add'>+					      "pixel",</div><div class='add'>+					      "core",</div><div class='add'>+					      "iface",</div><div class='add'>+					      "bus";</div><div class='add'>+</div><div class='add'>+				assigned-clocks = &lt;&amp;dispcc DISP_CC_MDSS_BYTE0_CLK_SRC&gt;,</div><div class='add'>+						  &lt;&amp;dispcc DISP_CC_MDSS_PCLK0_CLK_SRC&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;mdss_dsi_phy DSI_BYTE_PLL_CLK&gt;,</div><div class='add'>+							 &lt;&amp;mdss_dsi_phy DSI_PIXEL_PLL_CLK&gt;;</div><div class='add'>+</div><div class='add'>+				operating-points-v2 = &lt;&amp;dsi_opp_table&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+</div><div class='add'>+				phys = &lt;&amp;mdss_dsi_phy&gt;;</div><div class='add'>+</div><div class='add'>+				refgen-supply = &lt;&amp;refgen&gt;;</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+						mdss_dsi0_in: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;dpu_intf1_out&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+						mdss_dsi0_out: endpoint {</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				dsi_opp_table: opp-table {</div><div class='add'>+					compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+					opp-187500000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;187500000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					opp-300000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;300000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_svs&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					opp-358000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;358000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_svs_l1&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mdss_dsi_phy: phy@ae94400 {</div><div class='add'>+				compatible = "qcom,sc7280-dsi-phy-7nm";</div><div class='add'>+				reg = &lt;0 0x0ae94400 0 0x200&gt;,</div><div class='add'>+				      &lt;0 0x0ae94600 0 0x280&gt;,</div><div class='add'>+				      &lt;0 0x0ae94900 0 0x280&gt;;</div><div class='add'>+				reg-names = "dsi_phy",</div><div class='add'>+					    "dsi_phy_lane",</div><div class='add'>+					    "dsi_pll";</div><div class='add'>+</div><div class='add'>+				#clock-cells = &lt;1&gt;;</div><div class='add'>+				#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;dispcc DISP_CC_MDSS_AHB_CLK&gt;,</div><div class='add'>+					 &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;;</div><div class='add'>+				clock-names = "iface", "ref";</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mdss_edp: edp@aea0000 {</div><div class='add'>+				compatible = "qcom,sc7280-edp";</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				pinctrl-0 = &lt;&amp;edp_hot_plug_det&gt;;</div><div class='add'>+</div><div class='add'>+				reg = &lt;0 0x0aea0000 0 0x200&gt;,</div><div class='add'>+				      &lt;0 0x0aea0200 0 0x200&gt;,</div><div class='add'>+				      &lt;0 0x0aea0400 0 0xc00&gt;,</div><div class='add'>+				      &lt;0 0x0aea1000 0 0x400&gt;,</div><div class='add'>+				      &lt;0 0x0aea1400 0 0x400&gt;;</div><div class='add'>+</div><div class='add'>+				interrupt-parent = &lt;&amp;mdss&gt;;</div><div class='add'>+				interrupts = &lt;14&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;dispcc DISP_CC_MDSS_AHB_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc DISP_CC_MDSS_EDP_AUX_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc DISP_CC_MDSS_EDP_LINK_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc DISP_CC_MDSS_EDP_PIXEL_CLK&gt;;</div><div class='add'>+				clock-names = "core_iface",</div><div class='add'>+					      "core_aux",</div><div class='add'>+					      "ctrl_link",</div><div class='add'>+					      "ctrl_link_iface",</div><div class='add'>+					      "stream_pixel";</div><div class='add'>+				assigned-clocks = &lt;&amp;dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC&gt;,</div><div class='add'>+						  &lt;&amp;dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;mdss_edp_phy 0&gt;, &lt;&amp;mdss_edp_phy 1&gt;;</div><div class='add'>+</div><div class='add'>+				phys = &lt;&amp;mdss_edp_phy&gt;;</div><div class='add'>+				phy-names = "dp";</div><div class='add'>+</div><div class='add'>+				operating-points-v2 = &lt;&amp;edp_opp_table&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+						edp_in: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;dpu_intf5_out&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+						mdss_edp_out: endpoint { };</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				edp_opp_table: opp-table {</div><div class='add'>+					compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+					opp-160000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;160000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					opp-270000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;270000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_svs&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					opp-540000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;540000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_nom&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					opp-810000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;810000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_nom&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mdss_edp_phy: phy@aec2a00 {</div><div class='add'>+				compatible = "qcom,sc7280-edp-phy";</div><div class='add'>+</div><div class='add'>+				reg = &lt;0 0x0aec2a00 0 0x19c&gt;,</div><div class='add'>+				      &lt;0 0x0aec2200 0 0xa0&gt;,</div><div class='add'>+				      &lt;0 0x0aec2600 0 0xa0&gt;,</div><div class='add'>+				      &lt;0 0x0aec2000 0 0x1c0&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;,</div><div class='add'>+					 &lt;&amp;gcc GCC_EDP_CLKREF_EN&gt;;</div><div class='add'>+				clock-names = "aux",</div><div class='add'>+					      "cfg_ahb";</div><div class='add'>+</div><div class='add'>+				#clock-cells = &lt;1&gt;;</div><div class='add'>+				#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mdss_dp: displayport-controller@ae90000 {</div><div class='add'>+				compatible = "qcom,sc7280-dp";</div><div class='add'>+</div><div class='add'>+				reg = &lt;0 0x0ae90000 0 0x200&gt;,</div><div class='add'>+				      &lt;0 0x0ae90200 0 0x200&gt;,</div><div class='add'>+				      &lt;0 0x0ae90400 0 0xc00&gt;,</div><div class='add'>+				      &lt;0 0x0ae91000 0 0x400&gt;,</div><div class='add'>+				      &lt;0 0x0ae91400 0 0x400&gt;;</div><div class='add'>+</div><div class='add'>+				interrupt-parent = &lt;&amp;mdss&gt;;</div><div class='add'>+				interrupts = &lt;12&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;dispcc DISP_CC_MDSS_AHB_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc DISP_CC_MDSS_DP_AUX_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc DISP_CC_MDSS_DP_LINK_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc DISP_CC_MDSS_DP_PIXEL_CLK&gt;;</div><div class='add'>+				clock-names = "core_iface",</div><div class='add'>+						"core_aux",</div><div class='add'>+						"ctrl_link",</div><div class='add'>+						"ctrl_link_iface",</div><div class='add'>+						"stream_pixel";</div><div class='add'>+				assigned-clocks = &lt;&amp;dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC&gt;,</div><div class='add'>+						  &lt;&amp;dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK&gt;,</div><div class='add'>+							 &lt;&amp;usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK&gt;;</div><div class='add'>+				phys = &lt;&amp;usb_1_qmpphy QMP_USB43DP_DP_PHY&gt;;</div><div class='add'>+				phy-names = "dp";</div><div class='add'>+</div><div class='add'>+				operating-points-v2 = &lt;&amp;dp_opp_table&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SC7280_CX&gt;;</div><div class='add'>+</div><div class='add'>+				#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+						dp_in: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;dpu_intf0_out&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+						mdss_dp_out: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;usb_dp_qmpphy_dp_in&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				dp_opp_table: opp-table {</div><div class='add'>+					compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+					opp-160000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;160000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					opp-270000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;270000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_svs&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					opp-540000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;540000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_svs_l1&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					opp-810000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;810000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_nom&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pdc: interrupt-controller@b220000 {</div><div class='add'>+			compatible = "qcom,sc7280-pdc", "qcom,pdc";</div><div class='add'>+			reg = &lt;0 0x0b220000 0 0x30000&gt;;</div><div class='add'>+			qcom,pdc-ranges = &lt;0 480 40&gt;, &lt;40 140 14&gt;, &lt;54 263 1&gt;,</div><div class='add'>+					  &lt;55 306 4&gt;, &lt;59 312 3&gt;, &lt;62 374 2&gt;,</div><div class='add'>+					  &lt;64 434 2&gt;, &lt;66 438 3&gt;, &lt;69 86 1&gt;,</div><div class='add'>+					  &lt;70 520 54&gt;, &lt;124 609 31&gt;, &lt;155 63 1&gt;,</div><div class='add'>+					  &lt;156 716 12&gt;;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;intc&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pdc_reset: reset-controller@b5e0000 {</div><div class='add'>+			compatible = "qcom,sc7280-pdc-global";</div><div class='add'>+			reg = &lt;0 0x0b5e0000 0 0x20000&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+			status = "reserved"; /* Owned by firmware */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tsens0: thermal-sensor@c263000 {</div><div class='add'>+			compatible = "qcom,sc7280-tsens","qcom,tsens-v2";</div><div class='add'>+			reg = &lt;0 0x0c263000 0 0x1ff&gt;, /* TM */</div><div class='add'>+				&lt;0 0x0c222000 0 0x1ff&gt;; /* SROT */</div><div class='add'>+			#qcom,sensors = &lt;15&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "uplow","critical";</div><div class='add'>+			#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tsens1: thermal-sensor@c265000 {</div><div class='add'>+			compatible = "qcom,sc7280-tsens","qcom,tsens-v2";</div><div class='add'>+			reg = &lt;0 0x0c265000 0 0x1ff&gt;, /* TM */</div><div class='add'>+				&lt;0 0x0c223000 0 0x1ff&gt;; /* SROT */</div><div class='add'>+			#qcom,sensors = &lt;12&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "uplow","critical";</div><div class='add'>+			#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aoss_reset: reset-controller@c2a0000 {</div><div class='add'>+			compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc";</div><div class='add'>+			reg = &lt;0 0x0c2a0000 0 0x31000&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aoss_qmp: power-management@c300000 {</div><div class='add'>+			compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp";</div><div class='add'>+			reg = &lt;0 0x0c300000 0 0x400&gt;;</div><div class='add'>+			interrupts-extended = &lt;&amp;ipcc IPCC_CLIENT_AOP</div><div class='add'>+						     IPCC_MPROC_SIGNAL_GLINK_QMP</div><div class='add'>+						     IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			mboxes = &lt;&amp;ipcc IPCC_CLIENT_AOP</div><div class='add'>+					IPCC_MPROC_SIGNAL_GLINK_QMP&gt;;</div><div class='add'>+</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sram@c3f0000 {</div><div class='add'>+			compatible = "qcom,rpmh-stats";</div><div class='add'>+			reg = &lt;0 0x0c3f0000 0 0x400&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spmi_bus: spmi@c440000 {</div><div class='add'>+			compatible = "qcom,spmi-pmic-arb";</div><div class='add'>+			reg = &lt;0 0x0c440000 0 0x1100&gt;,</div><div class='add'>+			      &lt;0 0x0c600000 0 0x2000000&gt;,</div><div class='add'>+			      &lt;0 0x0e600000 0 0x100000&gt;,</div><div class='add'>+			      &lt;0 0x0e700000 0 0xa0000&gt;,</div><div class='add'>+			      &lt;0 0x0c40a000 0 0x26000&gt;;</div><div class='add'>+			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";</div><div class='add'>+			interrupt-names = "periph_irq";</div><div class='add'>+			interrupts-extended = &lt;&amp;pdc 1 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			qcom,ee = &lt;0&gt;;</div><div class='add'>+			qcom,channel = &lt;0&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;4&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tlmm: pinctrl@f100000 {</div><div class='add'>+			compatible = "qcom,sc7280-pinctrl";</div><div class='add'>+			reg = &lt;0 0x0f100000 0 0x300000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;tlmm 0 0 175&gt;;</div><div class='add'>+			wakeup-parent = &lt;&amp;pdc&gt;;</div><div class='add'>+</div><div class='add'>+			cci0_default: cci0-default-state {</div><div class='add'>+				pins = "gpio69", "gpio70";</div><div class='add'>+				function = "cci_i2c";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cci0_sleep: cci0-sleep-state {</div><div class='add'>+				pins = "gpio69", "gpio70";</div><div class='add'>+				function = "cci_i2c";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-down;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cci1_default: cci1-default-state {</div><div class='add'>+				pins = "gpio71", "gpio72";</div><div class='add'>+				function = "cci_i2c";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cci1_sleep: cci1-sleep-state {</div><div class='add'>+				pins = "gpio71", "gpio72";</div><div class='add'>+				function = "cci_i2c";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-down;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cci2_default: cci2-default-state {</div><div class='add'>+				pins = "gpio73", "gpio74";</div><div class='add'>+				function = "cci_i2c";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cci2_sleep: cci2-sleep-state {</div><div class='add'>+				pins = "gpio73", "gpio74";</div><div class='add'>+				function = "cci_i2c";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-down;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cci3_default: cci3-default-state {</div><div class='add'>+				pins = "gpio75", "gpio76";</div><div class='add'>+				function = "cci_i2c";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cci3_sleep: cci3-sleep-state {</div><div class='add'>+				pins = "gpio75", "gpio76";</div><div class='add'>+				function = "cci_i2c";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-down;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			dp_hot_plug_det: dp-hot-plug-det-state {</div><div class='add'>+				pins = "gpio47";</div><div class='add'>+				function = "dp_hot";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			edp_hot_plug_det: edp-hot-plug-det-state {</div><div class='add'>+				pins = "gpio60";</div><div class='add'>+				function = "edp_hot";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mi2s0_data0: mi2s0-data0-state {</div><div class='add'>+				pins = "gpio98";</div><div class='add'>+				function = "mi2s0_data0";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mi2s0_data1: mi2s0-data1-state {</div><div class='add'>+				pins = "gpio99";</div><div class='add'>+				function = "mi2s0_data1";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mi2s0_mclk: mi2s0-mclk-state {</div><div class='add'>+				pins = "gpio96";</div><div class='add'>+				function = "pri_mi2s";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mi2s0_sclk: mi2s0-sclk-state {</div><div class='add'>+				pins = "gpio97";</div><div class='add'>+				function = "mi2s0_sck";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mi2s0_ws: mi2s0-ws-state {</div><div class='add'>+				pins = "gpio100";</div><div class='add'>+				function = "mi2s0_ws";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mi2s1_data0: mi2s1-data0-state {</div><div class='add'>+				pins = "gpio107";</div><div class='add'>+				function = "mi2s1_data0";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mi2s1_sclk: mi2s1-sclk-state {</div><div class='add'>+				pins = "gpio106";</div><div class='add'>+				function = "mi2s1_sck";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mi2s1_ws: mi2s1-ws-state {</div><div class='add'>+				pins = "gpio108";</div><div class='add'>+				function = "mi2s1_ws";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pcie0_clkreq_n: pcie0-clkreq-n-state {</div><div class='add'>+				pins = "gpio88";</div><div class='add'>+				function = "pcie0_clkreqn";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pcie1_clkreq_n: pcie1-clkreq-n-state {</div><div class='add'>+				pins = "gpio79";</div><div class='add'>+				function = "pcie1_clkreqn";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qspi_clk: qspi-clk-state {</div><div class='add'>+				pins = "gpio14";</div><div class='add'>+				function = "qspi_clk";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qspi_cs0: qspi-cs0-state {</div><div class='add'>+				pins = "gpio15";</div><div class='add'>+				function = "qspi_cs";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qspi_cs1: qspi-cs1-state {</div><div class='add'>+				pins = "gpio19";</div><div class='add'>+				function = "qspi_cs";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qspi_data0: qspi-data0-state {</div><div class='add'>+				pins = "gpio12";</div><div class='add'>+				function = "qspi_data";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qspi_data1: qspi-data1-state {</div><div class='add'>+				pins = "gpio13";</div><div class='add'>+				function = "qspi_data";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qspi_data23: qspi-data23-state {</div><div class='add'>+				pins = "gpio16", "gpio17";</div><div class='add'>+				function = "qspi_data";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c0_data_clk: qup-i2c0-data-clk-state {</div><div class='add'>+				pins = "gpio0", "gpio1";</div><div class='add'>+				function = "qup00";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c1_data_clk: qup-i2c1-data-clk-state {</div><div class='add'>+				pins = "gpio4", "gpio5";</div><div class='add'>+				function = "qup01";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c2_data_clk: qup-i2c2-data-clk-state {</div><div class='add'>+				pins = "gpio8", "gpio9";</div><div class='add'>+				function = "qup02";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c3_data_clk: qup-i2c3-data-clk-state {</div><div class='add'>+				pins = "gpio12", "gpio13";</div><div class='add'>+				function = "qup03";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c4_data_clk: qup-i2c4-data-clk-state {</div><div class='add'>+				pins = "gpio16", "gpio17";</div><div class='add'>+				function = "qup04";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c5_data_clk: qup-i2c5-data-clk-state {</div><div class='add'>+				pins = "gpio20", "gpio21";</div><div class='add'>+				function = "qup05";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c6_data_clk: qup-i2c6-data-clk-state {</div><div class='add'>+				pins = "gpio24", "gpio25";</div><div class='add'>+				function = "qup06";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c7_data_clk: qup-i2c7-data-clk-state {</div><div class='add'>+				pins = "gpio28", "gpio29";</div><div class='add'>+				function = "qup07";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c8_data_clk: qup-i2c8-data-clk-state {</div><div class='add'>+				pins = "gpio32", "gpio33";</div><div class='add'>+				function = "qup10";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c9_data_clk: qup-i2c9-data-clk-state {</div><div class='add'>+				pins = "gpio36", "gpio37";</div><div class='add'>+				function = "qup11";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c10_data_clk: qup-i2c10-data-clk-state {</div><div class='add'>+				pins = "gpio40", "gpio41";</div><div class='add'>+				function = "qup12";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c11_data_clk: qup-i2c11-data-clk-state {</div><div class='add'>+				pins = "gpio44", "gpio45";</div><div class='add'>+				function = "qup13";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c12_data_clk: qup-i2c12-data-clk-state {</div><div class='add'>+				pins = "gpio48", "gpio49";</div><div class='add'>+				function = "qup14";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c13_data_clk: qup-i2c13-data-clk-state {</div><div class='add'>+				pins = "gpio52", "gpio53";</div><div class='add'>+				function = "qup15";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c14_data_clk: qup-i2c14-data-clk-state {</div><div class='add'>+				pins = "gpio56", "gpio57";</div><div class='add'>+				function = "qup16";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c15_data_clk: qup-i2c15-data-clk-state {</div><div class='add'>+				pins = "gpio60", "gpio61";</div><div class='add'>+				function = "qup17";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi0_data_clk: qup-spi0-data-clk-state {</div><div class='add'>+				pins = "gpio0", "gpio1", "gpio2";</div><div class='add'>+				function = "qup00";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi0_cs: qup-spi0-cs-state {</div><div class='add'>+				pins = "gpio3";</div><div class='add'>+				function = "qup00";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {</div><div class='add'>+				pins = "gpio3";</div><div class='add'>+				function = "gpio";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi1_data_clk: qup-spi1-data-clk-state {</div><div class='add'>+				pins = "gpio4", "gpio5", "gpio6";</div><div class='add'>+				function = "qup01";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi1_cs: qup-spi1-cs-state {</div><div class='add'>+				pins = "gpio7";</div><div class='add'>+				function = "qup01";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {</div><div class='add'>+				pins = "gpio7";</div><div class='add'>+				function = "gpio";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi2_data_clk: qup-spi2-data-clk-state {</div><div class='add'>+				pins = "gpio8", "gpio9", "gpio10";</div><div class='add'>+				function = "qup02";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi2_cs: qup-spi2-cs-state {</div><div class='add'>+				pins = "gpio11";</div><div class='add'>+				function = "qup02";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi2_cs_gpio: qup-spi2-cs-gpio-state {</div><div class='add'>+				pins = "gpio11";</div><div class='add'>+				function = "gpio";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi3_data_clk: qup-spi3-data-clk-state {</div><div class='add'>+				pins = "gpio12", "gpio13", "gpio14";</div><div class='add'>+				function = "qup03";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi3_cs: qup-spi3-cs-state {</div><div class='add'>+				pins = "gpio15";</div><div class='add'>+				function = "qup03";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {</div><div class='add'>+				pins = "gpio15";</div><div class='add'>+				function = "gpio";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi4_data_clk: qup-spi4-data-clk-state {</div><div class='add'>+				pins = "gpio16", "gpio17", "gpio18";</div><div class='add'>+				function = "qup04";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi4_cs: qup-spi4-cs-state {</div><div class='add'>+				pins = "gpio19";</div><div class='add'>+				function = "qup04";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi4_cs_gpio: qup-spi4-cs-gpio-state {</div><div class='add'>+				pins = "gpio19";</div><div class='add'>+				function = "gpio";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi5_data_clk: qup-spi5-data-clk-state {</div><div class='add'>+				pins = "gpio20", "gpio21", "gpio22";</div><div class='add'>+				function = "qup05";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi5_cs: qup-spi5-cs-state {</div><div class='add'>+				pins = "gpio23";</div><div class='add'>+				function = "qup05";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {</div><div class='add'>+				pins = "gpio23";</div><div class='add'>+				function = "gpio";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi6_data_clk: qup-spi6-data-clk-state {</div><div class='add'>+				pins = "gpio24", "gpio25", "gpio26";</div><div class='add'>+				function = "qup06";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi6_cs: qup-spi6-cs-state {</div><div class='add'>+				pins = "gpio27";</div><div class='add'>+				function = "qup06";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {</div><div class='add'>+				pins = "gpio27";</div><div class='add'>+				function = "gpio";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi7_data_clk: qup-spi7-data-clk-state {</div><div class='add'>+				pins = "gpio28", "gpio29", "gpio30";</div><div class='add'>+				function = "qup07";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi7_cs: qup-spi7-cs-state {</div><div class='add'>+				pins = "gpio31";</div><div class='add'>+				function = "qup07";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi7_cs_gpio: qup-spi7-cs-gpio-state {</div><div class='add'>+				pins = "gpio31";</div><div class='add'>+				function = "gpio";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi8_data_clk: qup-spi8-data-clk-state {</div><div class='add'>+				pins = "gpio32", "gpio33", "gpio34";</div><div class='add'>+				function = "qup10";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi8_cs: qup-spi8-cs-state {</div><div class='add'>+				pins = "gpio35";</div><div class='add'>+				function = "qup10";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {</div><div class='add'>+				pins = "gpio35";</div><div class='add'>+				function = "gpio";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi9_data_clk: qup-spi9-data-clk-state {</div><div class='add'>+				pins = "gpio36", "gpio37", "gpio38";</div><div class='add'>+				function = "qup11";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi9_cs: qup-spi9-cs-state {</div><div class='add'>+				pins = "gpio39";</div><div class='add'>+				function = "qup11";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi9_cs_gpio: qup-spi9-cs-gpio-state {</div><div class='add'>+				pins = "gpio39";</div><div class='add'>+				function = "gpio";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi10_data_clk: qup-spi10-data-clk-state {</div><div class='add'>+				pins = "gpio40", "gpio41", "gpio42";</div><div class='add'>+				function = "qup12";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi10_cs: qup-spi10-cs-state {</div><div class='add'>+				pins = "gpio43";</div><div class='add'>+				function = "qup12";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {</div><div class='add'>+				pins = "gpio43";</div><div class='add'>+				function = "gpio";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi11_data_clk: qup-spi11-data-clk-state {</div><div class='add'>+				pins = "gpio44", "gpio45", "gpio46";</div><div class='add'>+				function = "qup13";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi11_cs: qup-spi11-cs-state {</div><div class='add'>+				pins = "gpio47";</div><div class='add'>+				function = "qup13";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {</div><div class='add'>+				pins = "gpio47";</div><div class='add'>+				function = "gpio";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi12_data_clk: qup-spi12-data-clk-state {</div><div class='add'>+				pins = "gpio48", "gpio49", "gpio50";</div><div class='add'>+				function = "qup14";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi12_cs: qup-spi12-cs-state {</div><div class='add'>+				pins = "gpio51";</div><div class='add'>+				function = "qup14";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi12_cs_gpio: qup-spi12-cs-gpio-state {</div><div class='add'>+				pins = "gpio51";</div><div class='add'>+				function = "gpio";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi13_data_clk: qup-spi13-data-clk-state {</div><div class='add'>+				pins = "gpio52", "gpio53", "gpio54";</div><div class='add'>+				function = "qup15";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi13_cs: qup-spi13-cs-state {</div><div class='add'>+				pins = "gpio55";</div><div class='add'>+				function = "qup15";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi13_cs_gpio: qup-spi13-cs-gpio-state {</div><div class='add'>+				pins = "gpio55";</div><div class='add'>+				function = "gpio";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi14_data_clk: qup-spi14-data-clk-state {</div><div class='add'>+				pins = "gpio56", "gpio57", "gpio58";</div><div class='add'>+				function = "qup16";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi14_cs: qup-spi14-cs-state {</div><div class='add'>+				pins = "gpio59";</div><div class='add'>+				function = "qup16";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi14_cs_gpio: qup-spi14-cs-gpio-state {</div><div class='add'>+				pins = "gpio59";</div><div class='add'>+				function = "gpio";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi15_data_clk: qup-spi15-data-clk-state {</div><div class='add'>+				pins = "gpio60", "gpio61", "gpio62";</div><div class='add'>+				function = "qup17";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi15_cs: qup-spi15-cs-state {</div><div class='add'>+				pins = "gpio63";</div><div class='add'>+				function = "qup17";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi15_cs_gpio: qup-spi15-cs-gpio-state {</div><div class='add'>+				pins = "gpio63";</div><div class='add'>+				function = "gpio";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart0_cts: qup-uart0-cts-state {</div><div class='add'>+				pins = "gpio0";</div><div class='add'>+				function = "qup00";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart0_rts: qup-uart0-rts-state {</div><div class='add'>+				pins = "gpio1";</div><div class='add'>+				function = "qup00";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart0_tx: qup-uart0-tx-state {</div><div class='add'>+				pins = "gpio2";</div><div class='add'>+				function = "qup00";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart0_rx: qup-uart0-rx-state {</div><div class='add'>+				pins = "gpio3";</div><div class='add'>+				function = "qup00";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart1_cts: qup-uart1-cts-state {</div><div class='add'>+				pins = "gpio4";</div><div class='add'>+				function = "qup01";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart1_rts: qup-uart1-rts-state {</div><div class='add'>+				pins = "gpio5";</div><div class='add'>+				function = "qup01";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart1_tx: qup-uart1-tx-state {</div><div class='add'>+				pins = "gpio6";</div><div class='add'>+				function = "qup01";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart1_rx: qup-uart1-rx-state {</div><div class='add'>+				pins = "gpio7";</div><div class='add'>+				function = "qup01";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart2_cts: qup-uart2-cts-state {</div><div class='add'>+				pins = "gpio8";</div><div class='add'>+				function = "qup02";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart2_rts: qup-uart2-rts-state {</div><div class='add'>+				pins = "gpio9";</div><div class='add'>+				function = "qup02";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart2_tx: qup-uart2-tx-state {</div><div class='add'>+				pins = "gpio10";</div><div class='add'>+				function = "qup02";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart2_rx: qup-uart2-rx-state {</div><div class='add'>+				pins = "gpio11";</div><div class='add'>+				function = "qup02";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart3_cts: qup-uart3-cts-state {</div><div class='add'>+				pins = "gpio12";</div><div class='add'>+				function = "qup03";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart3_rts: qup-uart3-rts-state {</div><div class='add'>+				pins = "gpio13";</div><div class='add'>+				function = "qup03";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart3_tx: qup-uart3-tx-state {</div><div class='add'>+				pins = "gpio14";</div><div class='add'>+				function = "qup03";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart3_rx: qup-uart3-rx-state {</div><div class='add'>+				pins = "gpio15";</div><div class='add'>+				function = "qup03";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart4_cts: qup-uart4-cts-state {</div><div class='add'>+				pins = "gpio16";</div><div class='add'>+				function = "qup04";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart4_rts: qup-uart4-rts-state {</div><div class='add'>+				pins = "gpio17";</div><div class='add'>+				function = "qup04";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart4_tx: qup-uart4-tx-state {</div><div class='add'>+				pins = "gpio18";</div><div class='add'>+				function = "qup04";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart4_rx: qup-uart4-rx-state {</div><div class='add'>+				pins = "gpio19";</div><div class='add'>+				function = "qup04";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart5_tx: qup-uart5-tx-state {</div><div class='add'>+				pins = "gpio22";</div><div class='add'>+				function = "qup05";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart5_rx: qup-uart5-rx-state {</div><div class='add'>+				pins = "gpio23";</div><div class='add'>+				function = "qup05";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart6_cts: qup-uart6-cts-state {</div><div class='add'>+				pins = "gpio24";</div><div class='add'>+				function = "qup06";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart6_rts: qup-uart6-rts-state {</div><div class='add'>+				pins = "gpio25";</div><div class='add'>+				function = "qup06";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart6_tx: qup-uart6-tx-state {</div><div class='add'>+				pins = "gpio26";</div><div class='add'>+				function = "qup06";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart6_rx: qup-uart6-rx-state {</div><div class='add'>+				pins = "gpio27";</div><div class='add'>+				function = "qup06";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart7_cts: qup-uart7-cts-state {</div><div class='add'>+				pins = "gpio28";</div><div class='add'>+				function = "qup07";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart7_rts: qup-uart7-rts-state {</div><div class='add'>+				pins = "gpio29";</div><div class='add'>+				function = "qup07";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart7_tx: qup-uart7-tx-state {</div><div class='add'>+				pins = "gpio30";</div><div class='add'>+				function = "qup07";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart7_rx: qup-uart7-rx-state {</div><div class='add'>+				pins = "gpio31";</div><div class='add'>+				function = "qup07";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart8_cts: qup-uart8-cts-state {</div><div class='add'>+				pins = "gpio32";</div><div class='add'>+				function = "qup10";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart8_rts: qup-uart8-rts-state {</div><div class='add'>+				pins = "gpio33";</div><div class='add'>+				function = "qup10";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart8_tx: qup-uart8-tx-state {</div><div class='add'>+				pins = "gpio34";</div><div class='add'>+				function = "qup10";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart8_rx: qup-uart8-rx-state {</div><div class='add'>+				pins = "gpio35";</div><div class='add'>+				function = "qup10";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart9_cts: qup-uart9-cts-state {</div><div class='add'>+				pins = "gpio36";</div><div class='add'>+				function = "qup11";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart9_rts: qup-uart9-rts-state {</div><div class='add'>+				pins = "gpio37";</div><div class='add'>+				function = "qup11";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart9_tx: qup-uart9-tx-state {</div><div class='add'>+				pins = "gpio38";</div><div class='add'>+				function = "qup11";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart9_rx: qup-uart9-rx-state {</div><div class='add'>+				pins = "gpio39";</div><div class='add'>+				function = "qup11";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart10_cts: qup-uart10-cts-state {</div><div class='add'>+				pins = "gpio40";</div><div class='add'>+				function = "qup12";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart10_rts: qup-uart10-rts-state {</div><div class='add'>+				pins = "gpio41";</div><div class='add'>+				function = "qup12";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart10_tx: qup-uart10-tx-state {</div><div class='add'>+				pins = "gpio42";</div><div class='add'>+				function = "qup12";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart10_rx: qup-uart10-rx-state {</div><div class='add'>+				pins = "gpio43";</div><div class='add'>+				function = "qup12";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart11_cts: qup-uart11-cts-state {</div><div class='add'>+				pins = "gpio44";</div><div class='add'>+				function = "qup13";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart11_rts: qup-uart11-rts-state {</div><div class='add'>+				pins = "gpio45";</div><div class='add'>+				function = "qup13";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart11_tx: qup-uart11-tx-state {</div><div class='add'>+				pins = "gpio46";</div><div class='add'>+				function = "qup13";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart11_rx: qup-uart11-rx-state {</div><div class='add'>+				pins = "gpio47";</div><div class='add'>+				function = "qup13";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart12_cts: qup-uart12-cts-state {</div><div class='add'>+				pins = "gpio48";</div><div class='add'>+				function = "qup14";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart12_rts: qup-uart12-rts-state {</div><div class='add'>+				pins = "gpio49";</div><div class='add'>+				function = "qup14";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart12_tx: qup-uart12-tx-state {</div><div class='add'>+				pins = "gpio50";</div><div class='add'>+				function = "qup14";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart12_rx: qup-uart12-rx-state {</div><div class='add'>+				pins = "gpio51";</div><div class='add'>+				function = "qup14";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart13_cts: qup-uart13-cts-state {</div><div class='add'>+				pins = "gpio52";</div><div class='add'>+				function = "qup15";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart13_rts: qup-uart13-rts-state {</div><div class='add'>+				pins = "gpio53";</div><div class='add'>+				function = "qup15";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart13_tx: qup-uart13-tx-state {</div><div class='add'>+				pins = "gpio54";</div><div class='add'>+				function = "qup15";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart13_rx: qup-uart13-rx-state {</div><div class='add'>+				pins = "gpio55";</div><div class='add'>+				function = "qup15";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart14_cts: qup-uart14-cts-state {</div><div class='add'>+				pins = "gpio56";</div><div class='add'>+				function = "qup16";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart14_rts: qup-uart14-rts-state {</div><div class='add'>+				pins = "gpio57";</div><div class='add'>+				function = "qup16";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart14_tx: qup-uart14-tx-state {</div><div class='add'>+				pins = "gpio58";</div><div class='add'>+				function = "qup16";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart14_rx: qup-uart14-rx-state {</div><div class='add'>+				pins = "gpio59";</div><div class='add'>+				function = "qup16";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart15_cts: qup-uart15-cts-state {</div><div class='add'>+				pins = "gpio60";</div><div class='add'>+				function = "qup17";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart15_rts: qup-uart15-rts-state {</div><div class='add'>+				pins = "gpio61";</div><div class='add'>+				function = "qup17";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart15_tx: qup-uart15-tx-state {</div><div class='add'>+				pins = "gpio62";</div><div class='add'>+				function = "qup17";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart15_rx: qup-uart15-rx-state {</div><div class='add'>+				pins = "gpio63";</div><div class='add'>+				function = "qup17";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sdc1_clk: sdc1-clk-state {</div><div class='add'>+				pins = "sdc1_clk";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sdc1_cmd: sdc1-cmd-state {</div><div class='add'>+				pins = "sdc1_cmd";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sdc1_data: sdc1-data-state {</div><div class='add'>+				pins = "sdc1_data";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sdc1_rclk: sdc1-rclk-state {</div><div class='add'>+				pins = "sdc1_rclk";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sdc1_clk_sleep: sdc1-clk-sleep-state {</div><div class='add'>+				pins = "sdc1_clk";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-bus-hold;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sdc1_cmd_sleep: sdc1-cmd-sleep-state {</div><div class='add'>+				pins = "sdc1_cmd";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-bus-hold;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sdc1_data_sleep: sdc1-data-sleep-state {</div><div class='add'>+				pins = "sdc1_data";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-bus-hold;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sdc1_rclk_sleep: sdc1-rclk-sleep-state {</div><div class='add'>+				pins = "sdc1_rclk";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-bus-hold;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sdc2_clk: sdc2-clk-state {</div><div class='add'>+				pins = "sdc2_clk";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sdc2_cmd: sdc2-cmd-state {</div><div class='add'>+				pins = "sdc2_cmd";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sdc2_data: sdc2-data-state {</div><div class='add'>+				pins = "sdc2_data";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sdc2_clk_sleep: sdc2-clk-sleep-state {</div><div class='add'>+				pins = "sdc2_clk";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-bus-hold;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sdc2_cmd_sleep: sdc2-cmd-sleep-state {</div><div class='add'>+				pins = "sdc2_cmd";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-bus-hold;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sdc2_data_sleep: sdc2-data-sleep-state {</div><div class='add'>+				pins = "sdc2_data";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-bus-hold;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sram@146a5000 {</div><div class='add'>+			compatible = "qcom,sc7280-imem", "syscon", "simple-mfd";</div><div class='add'>+			reg = &lt;0 0x146a5000 0 0x6000&gt;;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			ranges = &lt;0 0 0x146a5000 0x6000&gt;;</div><div class='add'>+</div><div class='add'>+			pil-reloc@594c {</div><div class='add'>+				compatible = "qcom,pil-reloc-info";</div><div class='add'>+				reg = &lt;0x594c 0xc8&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		apps_smmu: iommu@15000000 {</div><div class='add'>+			compatible = "qcom,sc7280-smmu-500", "arm,mmu-500";</div><div class='add'>+			reg = &lt;0 0x15000000 0 0x100000&gt;;</div><div class='add'>+			#iommu-cells = &lt;2&gt;;</div><div class='add'>+			#global-interrupts = &lt;1&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+			interrupts = &lt;GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		anoc_1_tbu: tbu@151dd000 {</div><div class='add'>+			compatible = "qcom,sc7280-tbu";</div><div class='add'>+			reg = &lt;0x0 0x151dd000 0x0 0x1000&gt;;</div><div class='add'>+			interconnects = &lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;cnoc3 SLAVE_TCU QCOM_ICC_TAG_ACTIVE_ONLY&gt;;</div><div class='add'>+			qcom,stream-id-range = &lt;&amp;apps_smmu 0x0 0x400&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		anoc_2_tbu: tbu@151e1000 {</div><div class='add'>+			compatible = "qcom,sc7280-tbu";</div><div class='add'>+			reg = &lt;0x0 0x151e1000 0x0 0x1000&gt;;</div><div class='add'>+			interconnects = &lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;cnoc3 SLAVE_TCU QCOM_ICC_TAG_ACTIVE_ONLY&gt;;</div><div class='add'>+			qcom,stream-id-range = &lt;&amp;apps_smmu 0x400 0x400&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mnoc_hf_0_tbu: tbu@151e5000 {</div><div class='add'>+			compatible = "qcom,sc7280-tbu";</div><div class='add'>+			reg = &lt;0x0 0x151e5000 0x0 0x1000&gt;;</div><div class='add'>+			interconnects = &lt;&amp;mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY&gt;;</div><div class='add'>+			power-domains = &lt;&amp;gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC&gt;;</div><div class='add'>+			qcom,stream-id-range = &lt;&amp;apps_smmu 0x800 0x400&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mnoc_hf_1_tbu: tbu@151e9000 {</div><div class='add'>+			compatible = "qcom,sc7280-tbu";</div><div class='add'>+			reg = &lt;0x0 0x151e9000 0x0 0x1000&gt;;</div><div class='add'>+			interconnects = &lt;&amp;mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY&gt;;</div><div class='add'>+			power-domains = &lt;&amp;gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC&gt;;</div><div class='add'>+			qcom,stream-id-range = &lt;&amp;apps_smmu 0xc00 0x400&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		compute_dsp_1_tbu: tbu@151ed000 {</div><div class='add'>+			compatible = "qcom,sc7280-tbu";</div><div class='add'>+			reg = &lt;0x0 0x151ed000 0x0 0x1000&gt;;</div><div class='add'>+			interconnects = &lt;&amp;nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY&gt;;</div><div class='add'>+			power-domains = &lt;&amp;gcc HLOS1_VOTE_TURING_MMU_TBU1_GDSC&gt;;</div><div class='add'>+			qcom,stream-id-range = &lt;&amp;apps_smmu 0x1000 0x400&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		compute_dsp_0_tbu: tbu@151f1000 {</div><div class='add'>+			compatible = "qcom,sc7280-tbu";</div><div class='add'>+			reg = &lt;0x0 0x151f1000 0x0 0x1000&gt;;</div><div class='add'>+			interconnects = &lt;&amp;nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY&gt;;</div><div class='add'>+			power-domains = &lt;&amp;gcc HLOS1_VOTE_TURING_MMU_TBU0_GDSC&gt;;</div><div class='add'>+			qcom,stream-id-range = &lt;&amp;apps_smmu 0x1400 0x400&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		adsp_tbu: tbu@151f5000 {</div><div class='add'>+			compatible = "qcom,sc7280-tbu";</div><div class='add'>+			reg = &lt;0x0 0x151f5000 0x0 0x1000&gt;;</div><div class='add'>+			interconnects = &lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;lpass_ag_noc SLAVE_LPASS_CORE_CFG QCOM_ICC_TAG_ACTIVE_ONLY&gt;;</div><div class='add'>+			qcom,stream-id-range = &lt;&amp;apps_smmu 0x1800 0x400&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		anoc_1_pcie_tbu: tbu@151f9000 {</div><div class='add'>+			compatible = "qcom,sc7280-tbu";</div><div class='add'>+			reg = &lt;0x0 0x151f9000 0x0 0x1000&gt;;</div><div class='add'>+			interconnects = &lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;cnoc3 SLAVE_TCU QCOM_ICC_TAG_ACTIVE_ONLY&gt;;</div><div class='add'>+			qcom,stream-id-range = &lt;&amp;apps_smmu 0x1c00 0x400&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mnoc_sf_0_tbu: tbu@151fd000 {</div><div class='add'>+			compatible = "qcom,sc7280-tbu";</div><div class='add'>+			reg = &lt;0x0 0x151fd000 0x0 0x1000&gt;;</div><div class='add'>+			interconnects = &lt;&amp;mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY&gt;;</div><div class='add'>+			power-domains = &lt;&amp;gcc HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC&gt;;</div><div class='add'>+			qcom,stream-id-range = &lt;&amp;apps_smmu 0x2000 0x400&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		intc: interrupt-controller@17a00000 {</div><div class='add'>+			compatible = "arm,gic-v3";</div><div class='add'>+			reg = &lt;0 0x17a00000 0 0x10000&gt;,     /* GICD */</div><div class='add'>+			      &lt;0 0x17a60000 0 0x100000&gt;;    /* GICR * 8 */</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			msi-controller@17a40000 {</div><div class='add'>+				compatible = "arm,gic-v3-its";</div><div class='add'>+				reg = &lt;0 0x17a40000 0 0x20000&gt;;</div><div class='add'>+				msi-controller;</div><div class='add'>+				#msi-cells = &lt;1&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		watchdog: watchdog@17c10000 {</div><div class='add'>+			compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt";</div><div class='add'>+			reg = &lt;0 0x17c10000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;sleep_clk&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 0 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			status = "reserved"; /* Owned by Gunyah hyp */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		timer@17c20000 {</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges = &lt;0 0 0 0x20000000&gt;;</div><div class='add'>+			compatible = "arm,armv7-timer-mem";</div><div class='add'>+			reg = &lt;0 0x17c20000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			frame@17c21000 {</div><div class='add'>+				frame-number = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				reg = &lt;0x17c21000 0x1000&gt;,</div><div class='add'>+				      &lt;0x17c22000 0x1000&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@17c23000 {</div><div class='add'>+				frame-number = &lt;1&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				reg = &lt;0x17c23000 0x1000&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@17c25000 {</div><div class='add'>+				frame-number = &lt;2&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				reg = &lt;0x17c25000 0x1000&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@17c27000 {</div><div class='add'>+				frame-number = &lt;3&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				reg = &lt;0x17c27000 0x1000&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@17c29000 {</div><div class='add'>+				frame-number = &lt;4&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				reg = &lt;0x17c29000 0x1000&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@17c2b000 {</div><div class='add'>+				frame-number = &lt;5&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				reg = &lt;0x17c2b000 0x1000&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@17c2d000 {</div><div class='add'>+				frame-number = &lt;6&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				reg = &lt;0x17c2d000 0x1000&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		apps_rsc: rsc@18200000 {</div><div class='add'>+			compatible = "qcom,rpmh-rsc";</div><div class='add'>+			reg = &lt;0 0x18200000 0 0x10000&gt;,</div><div class='add'>+			      &lt;0 0x18210000 0 0x10000&gt;,</div><div class='add'>+			      &lt;0 0x18220000 0 0x10000&gt;;</div><div class='add'>+			reg-names = "drv-0", "drv-1", "drv-2";</div><div class='add'>+			interrupts = &lt;GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			qcom,tcs-offset = &lt;0xd00&gt;;</div><div class='add'>+			qcom,drv-id = &lt;2&gt;;</div><div class='add'>+			qcom,tcs-config = &lt;ACTIVE_TCS  2&gt;,</div><div class='add'>+					  &lt;SLEEP_TCS   3&gt;,</div><div class='add'>+					  &lt;WAKE_TCS    3&gt;,</div><div class='add'>+					  &lt;CONTROL_TCS 1&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cluster_pd&gt;;</div><div class='add'>+</div><div class='add'>+			apps_bcm_voter: bcm-voter {</div><div class='add'>+				compatible = "qcom,bcm-voter";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			rpmhpd: power-controller {</div><div class='add'>+				compatible = "qcom,sc7280-rpmhpd";</div><div class='add'>+				#power-domain-cells = &lt;1&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;rpmhpd_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+				rpmhpd_opp_table: opp-table {</div><div class='add'>+					compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+					rpmhpd_opp_ret: opp1 {</div><div class='add'>+						opp-level = &lt;RPMH_REGULATOR_LEVEL_RETENTION&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					rpmhpd_opp_low_svs: opp2 {</div><div class='add'>+						opp-level = &lt;RPMH_REGULATOR_LEVEL_LOW_SVS&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					rpmhpd_opp_svs: opp3 {</div><div class='add'>+						opp-level = &lt;RPMH_REGULATOR_LEVEL_SVS&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					rpmhpd_opp_svs_l1: opp4 {</div><div class='add'>+						opp-level = &lt;RPMH_REGULATOR_LEVEL_SVS_L1&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					rpmhpd_opp_svs_l2: opp5 {</div><div class='add'>+						opp-level = &lt;RPMH_REGULATOR_LEVEL_SVS_L2&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					rpmhpd_opp_nom: opp6 {</div><div class='add'>+						opp-level = &lt;RPMH_REGULATOR_LEVEL_NOM&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					rpmhpd_opp_nom_l1: opp7 {</div><div class='add'>+						opp-level = &lt;RPMH_REGULATOR_LEVEL_NOM_L1&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					rpmhpd_opp_turbo: opp8 {</div><div class='add'>+						opp-level = &lt;RPMH_REGULATOR_LEVEL_TURBO&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					rpmhpd_opp_turbo_l1: opp9 {</div><div class='add'>+						opp-level = &lt;RPMH_REGULATOR_LEVEL_TURBO_L1&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			rpmhcc: clock-controller {</div><div class='add'>+				compatible = "qcom,sc7280-rpmh-clk";</div><div class='add'>+				clocks = &lt;&amp;xo_board&gt;;</div><div class='add'>+				clock-names = "xo";</div><div class='add'>+				#clock-cells = &lt;1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		epss_l3: interconnect@18590000 {</div><div class='add'>+			compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3";</div><div class='add'>+			reg = &lt;0 0x18590000 0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;, &lt;&amp;gcc GCC_GPLL0&gt;;</div><div class='add'>+			clock-names = "xo", "alternate";</div><div class='add'>+			#interconnect-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpufreq_hw: cpufreq@18591000 {</div><div class='add'>+			compatible = "qcom,sc7280-cpufreq-epss", "qcom,cpufreq-epss";</div><div class='add'>+			reg = &lt;0 0x18591000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x18592000 0 0x1000&gt;,</div><div class='add'>+			      &lt;0 0x18593000 0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "dcvsh-irq-0",</div><div class='add'>+					  "dcvsh-irq-1",</div><div class='add'>+					  "dcvsh-irq-2";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;, &lt;&amp;gcc GCC_GPLL0&gt;;</div><div class='add'>+			clock-names = "xo", "alternate";</div><div class='add'>+			#freq-domain-cells = &lt;1&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound: sound {</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	thermal_zones: thermal-zones {</div><div class='add'>+		cpu0-thermal {</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 1&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu0_alert0: trip-point0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu0_alert1: trip-point1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu0_crit: cpu-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu0_alert0&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+				map1 {</div><div class='add'>+					trip = &lt;&amp;cpu0_alert1&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1-thermal {</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 2&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu1_alert0: trip-point0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu1_alert1: trip-point1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu1_crit: cpu-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu1_alert0&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+				map1 {</div><div class='add'>+					trip = &lt;&amp;cpu1_alert1&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2-thermal {</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 3&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu2_alert0: trip-point0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu2_alert1: trip-point1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu2_crit: cpu-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu2_alert0&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+				map1 {</div><div class='add'>+					trip = &lt;&amp;cpu2_alert1&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3-thermal {</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 4&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu3_alert0: trip-point0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu3_alert1: trip-point1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu3_crit: cpu-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu3_alert0&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+				map1 {</div><div class='add'>+					trip = &lt;&amp;cpu3_alert1&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu4-thermal {</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 7&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu4_alert0: trip-point0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu4_alert1: trip-point1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu4_crit: cpu-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu4_alert0&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+				map1 {</div><div class='add'>+					trip = &lt;&amp;cpu4_alert1&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu5-thermal {</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 8&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu5_alert0: trip-point0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu5_alert1: trip-point1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu5_crit: cpu-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu5_alert0&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+				map1 {</div><div class='add'>+					trip = &lt;&amp;cpu5_alert1&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu6-thermal {</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 9&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu6_alert0: trip-point0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu6_alert1: trip-point1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu6_crit: cpu-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu6_alert0&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+				map1 {</div><div class='add'>+					trip = &lt;&amp;cpu6_alert1&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu7-thermal {</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 10&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu7_alert0: trip-point0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu7_alert1: trip-point1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu7_crit: cpu-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu7_alert0&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+				map1 {</div><div class='add'>+					trip = &lt;&amp;cpu7_alert1&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu8-thermal {</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 11&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu8_alert0: trip-point0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu8_alert1: trip-point1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu8_crit: cpu-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu8_alert0&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+				map1 {</div><div class='add'>+					trip = &lt;&amp;cpu8_alert1&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu9-thermal {</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 12&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu9_alert0: trip-point0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu9_alert1: trip-point1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu9_crit: cpu-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu9_alert0&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+				map1 {</div><div class='add'>+					trip = &lt;&amp;cpu9_alert1&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu10-thermal {</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 13&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu10_alert0: trip-point0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu10_alert1: trip-point1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu10_crit: cpu-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu10_alert0&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+				map1 {</div><div class='add'>+					trip = &lt;&amp;cpu10_alert1&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu11-thermal {</div><div class='add'>+			polling-delay-passive = &lt;250&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 14&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpu11_alert0: trip-point0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu11_alert1: trip-point1 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cpu11_crit: cpu-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;cpu11_alert0&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+				map1 {</div><div class='add'>+					trip = &lt;&amp;cpu11_alert1&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;,</div><div class='add'>+							 &lt;&amp;cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aoss0-thermal {</div><div class='add'>+			polling-delay-passive = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 0&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				aoss0_alert0: trip-point0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				aoss0_crit: aoss0-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aoss1-thermal {</div><div class='add'>+			polling-delay-passive = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens1 0&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				aoss1_alert0: trip-point0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				aoss1_crit: aoss1-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpuss0-thermal {</div><div class='add'>+			polling-delay-passive = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 5&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpuss0_alert0: trip-point0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+				cpuss0_crit: cluster0-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpuss1-thermal {</div><div class='add'>+			polling-delay-passive = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 6&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				cpuss1_alert0: trip-point0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+				cpuss1_crit: cluster0-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpuss0-thermal {</div><div class='add'>+			polling-delay-passive = &lt;100&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens1 1&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				gpuss0_alert0: trip-point0 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpuss0_crit: gpuss0-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;gpuss0_alert0&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpuss1-thermal {</div><div class='add'>+			polling-delay-passive = &lt;100&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens1 2&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				gpuss1_alert0: trip-point0 {</div><div class='add'>+					temperature = &lt;95000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpuss1_crit: gpuss1-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cooling-maps {</div><div class='add'>+				map0 {</div><div class='add'>+					trip = &lt;&amp;gpuss1_alert0&gt;;</div><div class='add'>+					cooling-device = &lt;&amp;gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nspss0-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens1 3&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				nspss0_alert0: trip-point0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				nspss0_crit: nspss0-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nspss1-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens1 4&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				nspss1_alert0: trip-point0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				nspss1_crit: nspss1-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		video-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens1 5&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				video_alert0: trip-point0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				video_crit: video-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ddr-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens1 6&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				ddr_alert0: trip-point0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				ddr_crit: ddr-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdmss0-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens1 7&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				mdmss0_alert0: trip-point0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				mdmss0_crit: mdmss0-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdmss1-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens1 8&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				mdmss1_alert0: trip-point0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				mdmss1_crit: mdmss1-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdmss2-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens1 9&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				mdmss2_alert0: trip-point0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				mdmss2_crit: mdmss2-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdmss3-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens1 10&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				mdmss3_alert0: trip-point0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				mdmss3_crit: mdmss3-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		camera0-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens1 11&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				camera0_alert0: trip-point0 {</div><div class='add'>+					temperature = &lt;90000&gt;;</div><div class='add'>+					hysteresis = &lt;2000&gt;;</div><div class='add'>+					type = "hot";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				camera0_crit: camera0-crit {</div><div class='add'>+					temperature = &lt;110000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 IRQ_TYPE_LEVEL_LOW&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/lemans-auto.dtsi b/arch/arm64/boot/dts/qcom/lemans-auto.dtsi<br/>new file mode 100644<br/>index 000000000000..8db958d60fd1<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/lemans-auto.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/lemans-auto.dtsi</a></div><div class='hunk'>@@ -0,0 +1,104 @@</div><div class='add'>+// SPDX-License-Identifier: BSD-3-Clause</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2023, Linaro Limited</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "lemans.dtsi"</div><div class='add'>+</div><div class='add'>+/delete-node/ &amp;pil_camera_mem;</div><div class='add'>+/delete-node/ &amp;pil_adsp_mem;</div><div class='add'>+/delete-node/ &amp;q6_adsp_dtb_mem;</div><div class='add'>+/delete-node/ &amp;q6_gdsp0_dtb_mem;</div><div class='add'>+/delete-node/ &amp;pil_gdsp0_mem;</div><div class='add'>+/delete-node/ &amp;pil_gdsp1_mem;</div><div class='add'>+/delete-node/ &amp;q6_gdsp1_dtb_mem;</div><div class='add'>+/delete-node/ &amp;q6_cdsp0_dtb_mem;</div><div class='add'>+/delete-node/ &amp;pil_cdsp0_mem;</div><div class='add'>+/delete-node/ &amp;pil_gpu_mem;</div><div class='add'>+/delete-node/ &amp;pil_cdsp1_mem;</div><div class='add'>+/delete-node/ &amp;q6_cdsp1_dtb_mem;</div><div class='add'>+/delete-node/ &amp;pil_cvp_mem;</div><div class='add'>+/delete-node/ &amp;pil_video_mem;</div><div class='add'>+/delete-node/ &amp;gunyah_md_mem;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		tz_ffi_mem: tz-ffi@91c00000 {</div><div class='add'>+			compatible = "shared-dma-pool";</div><div class='add'>+			reg = &lt;0x0 0x91c00000 0x0 0x1400000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pil_camera_mem: pil-camera@95200000 {</div><div class='add'>+			reg = &lt;0x0 0x95200000 0x0 0x500000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pil_adsp_mem: pil-adsp@95c00000 {</div><div class='add'>+			reg = &lt;0x0 0x95c00000 0x0 0x1e00000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pil_gdsp0_mem: pil-gdsp0@97b00000 {</div><div class='add'>+			reg = &lt;0x0 0x97b00000 0x0 0x1e00000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pil_gdsp1_mem: pil-gdsp1@99900000 {</div><div class='add'>+			reg = &lt;0x0 0x99900000 0x0 0x1e00000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pil_cdsp0_mem: pil-cdsp0@9b800000 {</div><div class='add'>+			reg = &lt;0x0 0x9b800000 0x0 0x1e00000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pil_gpu_mem: pil-gpu@9d600000 {</div><div class='add'>+			reg = &lt;0x0 0x9d600000 0x0 0x2000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pil_cdsp1_mem: pil-cdsp1@9d700000 {</div><div class='add'>+			reg = &lt;0x0 0x9d700000 0x0 0x1e00000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pil_cvp_mem: pil-cvp@9f500000 {</div><div class='add'>+			reg = &lt;0x0 0x9f500000 0x0 0x700000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pil_video_mem: pil-video@9fc00000 {</div><div class='add'>+			reg = &lt;0x0 0x9fc00000 0x0 0x700000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		audio_mdf_mem: audio-mdf-region@ae000000 {</div><div class='add'>+			reg = &lt;0x0 0xae000000 0x0 0x1000000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		hyptz_reserved_mem: hyptz-reserved@beb00000 {</div><div class='add'>+			reg = &lt;0x0 0xbeb00000 0x0 0x11500000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		trusted_apps_mem: trusted-apps@d1900000 {</div><div class='add'>+			reg = &lt;0x0 0xd1900000 0x0 0x3800000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	firmware {</div><div class='add'>+		scm {</div><div class='add'>+			memory-region = &lt;&amp;tz_ffi_mem&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/lemans-evk-camera-csi1-imx577.dtso b/arch/arm64/boot/dts/qcom/lemans-evk-camera-csi1-imx577.dtso<br/>new file mode 100644<br/>index 000000000000..769befadd4e4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/lemans-evk-camera-csi1-imx577.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/lemans-evk-camera-csi1-imx577.dtso</a></div><div class='hunk'>@@ -0,0 +1,97 @@</div><div class='add'>+// SPDX-License-Identifier: BSD-3-Clause</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,sa8775p-camcc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+</div><div class='add'>+&amp;{/} {</div><div class='add'>+	vreg_cam1_1p8: regulator-cam1 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vreg_cam1";</div><div class='add'>+		startup-delay-us = &lt;10000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;pmm8654au_0_gpios 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;camss {</div><div class='add'>+	vdda-pll-supply = &lt;&amp;vreg_l1c&gt;;</div><div class='add'>+	vdda-phy-supply = &lt;&amp;vreg_l4a&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			csiphy1_ep: endpoint {</div><div class='add'>+				clock-lanes = &lt;7&gt;;</div><div class='add'>+				data-lanes = &lt;0 1 2 3&gt;;</div><div class='add'>+				remote-endpoint = &lt;&amp;imx577_ep1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cci1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;cci1_0_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;cci1_0_sleep&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cci1_i2c0 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	camera@1a {</div><div class='add'>+		compatible = "sony,imx577";</div><div class='add'>+		reg = &lt;0x1a&gt;;</div><div class='add'>+</div><div class='add'>+		reset-gpios = &lt;&amp;tlmm 133 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;cam1_default&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;camcc CAM_CC_MCLK1_CLK&gt;;</div><div class='add'>+		assigned-clocks = &lt;&amp;camcc CAM_CC_MCLK1_CLK&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;24000000&gt;;</div><div class='add'>+</div><div class='add'>+		dovdd-supply = &lt;&amp;vreg_s4a&gt;;</div><div class='add'>+		avdd-supply = &lt;&amp;vreg_cam1_1p8&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			imx577_ep1: endpoint {</div><div class='add'>+				clock-lanes = &lt;7&gt;;</div><div class='add'>+				link-frequencies = /bits/ 64 &lt;600000000&gt;;</div><div class='add'>+				data-lanes = &lt;0 1 2 3&gt;;</div><div class='add'>+				remote-endpoint = &lt;&amp;csiphy1_ep&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tlmm {</div><div class='add'>+	cam1_default: cam1-default-state {</div><div class='add'>+		mclk-pins {</div><div class='add'>+			pins = "gpio73";</div><div class='add'>+			function = "cam_mclk";</div><div class='add'>+			drive-strength = &lt;2&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rst-pins {</div><div class='add'>+			pins = "gpio133";</div><div class='add'>+			function = "gpio";</div><div class='add'>+			drive-strength = &lt;2&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/lemans-evk-camera.dtso b/arch/arm64/boot/dts/qcom/lemans-evk-camera.dtso<br/>new file mode 100644<br/>index 000000000000..4600d5441cce<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/lemans-evk-camera.dtso?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/lemans-evk-camera.dtso</a></div><div class='hunk'>@@ -0,0 +1,105 @@</div><div class='add'>+// SPDX-License-Identifier: BSD-3-Clause</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Camera Sensor overlay on top of leman evk core kit.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+/plugin/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,sa8775p-camcc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+</div><div class='add'>+&amp;{/} {</div><div class='add'>+	vreg_cam1_1p8: vreg_cam1_1p8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vreg_cam1_1p8";</div><div class='add'>+		startup-delay-us = &lt;10000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;pmm8654au_0_gpios 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;camcc {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;camss {</div><div class='add'>+	vdda-pll-supply = &lt;&amp;vreg_l1c&gt;;</div><div class='add'>+	vdda-phy-supply = &lt;&amp;vreg_l4a&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	ports {</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		port@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			csiphy1_ep: endpoint {</div><div class='add'>+				clock-lanes = &lt;7&gt;;</div><div class='add'>+				data-lanes = &lt;0 1 2 3&gt;;</div><div class='add'>+				remote-endpoint = &lt;&amp;imx577_ep1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cci1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;cci1_0_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;cci1_0_sleep&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;cci1_i2c0 {</div><div class='add'>+	#address-cells = &lt;1&gt;;</div><div class='add'>+	#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+	camera@1a {</div><div class='add'>+		compatible = "sony,imx577";</div><div class='add'>+		reg = &lt;0x1a&gt;;</div><div class='add'>+</div><div class='add'>+		reset-gpios = &lt;&amp;tlmm 133 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;cam1_default&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;camcc CAM_CC_MCLK1_CLK&gt;;</div><div class='add'>+		assigned-clocks = &lt;&amp;camcc CAM_CC_MCLK1_CLK&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;24000000&gt;;</div><div class='add'>+</div><div class='add'>+		dovdd-supply = &lt;&amp;vreg_s4a&gt;;</div><div class='add'>+		avdd-supply = &lt;&amp;vreg_cam1_1p8&gt;;</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			imx577_ep1: endpoint {</div><div class='add'>+				clock-lanes = &lt;7&gt;;</div><div class='add'>+				link-frequencies = /bits/ 64 &lt;600000000&gt;;</div><div class='add'>+				data-lanes = &lt;0 1 2 3&gt;;</div><div class='add'>+				remote-endpoint = &lt;&amp;csiphy1_ep&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tlmm {</div><div class='add'>+	cam1_default: cam1-default-state {</div><div class='add'>+		mclk-pins {</div><div class='add'>+			pins = "gpio73";</div><div class='add'>+			function = "cam_mclk";</div><div class='add'>+			drive-strength = &lt;2&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rst-pins {</div><div class='add'>+			pins = "gpio133";</div><div class='add'>+			function = "gpio";</div><div class='add'>+			drive-strength = &lt;2&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts<br/>new file mode 100644<br/>index 000000000000..b40fa203e4a2<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/lemans-evk.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/lemans-evk.dts</a></div><div class='hunk'>@@ -0,0 +1,804 @@</div><div class='add'>+// SPDX-License-Identifier: BSD-3-Clause</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2024-2025, Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pwm/pwm.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/qcom,q6afe.h&gt;</div><div class='add'>+#include &lt;dt-bindings/regulator/qcom,rpmh-regulator.h&gt;</div><div class='add'>+</div><div class='add'>+#include "lemans.dtsi"</div><div class='add'>+#include "lemans-pmics.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Qualcomm Technologies, Inc. Lemans EVK";</div><div class='add'>+	compatible = "qcom,lemans-evk", "qcom,qcs9100", "qcom,sa8775p";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;ethernet0;</div><div class='add'>+		mmc1 = &amp;sdhc;</div><div class='add'>+		serial0 = &amp;uart10;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dmic: audio-codec-0 {</div><div class='add'>+		compatible = "dmic-codec";</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		num-channels = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	max98357a: audio-codec-1 {</div><div class='add'>+		compatible = "maxim,max98357a";</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	edp0-connector {</div><div class='add'>+		compatible = "dp-connector";</div><div class='add'>+		label = "EDP0";</div><div class='add'>+		type = "mini";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			edp0_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;mdss0_dp0_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	edp1-connector {</div><div class='add'>+		compatible = "dp-connector";</div><div class='add'>+		label = "EDP1";</div><div class='add'>+		type = "mini";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			edp1_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;mdss0_dp1_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "qcom,qcs9100-sndcard";</div><div class='add'>+		model = "LEMANS-EVK";</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;hs0_mi2s_active&gt;, &lt;&amp;hs2_mi2s_active&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		hs0-mi2s-playback-dai-link {</div><div class='add'>+			link-name = "HS0 MI2S Playback";</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;max98357a&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cpu {</div><div class='add'>+				sound-dai = &lt;&amp;q6apmbedai PRIMARY_MI2S_RX&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			platform {</div><div class='add'>+				sound-dai = &lt;&amp;q6apm&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		hs2-mi2s-capture-dai-link {</div><div class='add'>+			link-name = "HS2 MI2S Capture";</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;dmic&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cpu {</div><div class='add'>+				sound-dai = &lt;&amp;q6apmbedai TERTIARY_MI2S_TX&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			platform {</div><div class='add'>+				sound-dai = &lt;&amp;q6apm&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vmmc_sdc: regulator-vmmc-sdc {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+</div><div class='add'>+		regulator-name = "vmmc_sdc";</div><div class='add'>+		regulator-min-microvolt = &lt;2950000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;2950000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vreg_sdc: regulator-vreg-sdc {</div><div class='add'>+		compatible = "regulator-gpio";</div><div class='add'>+</div><div class='add'>+		regulator-name = "vreg_sdc";</div><div class='add'>+		regulator-type = "voltage";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;2950000&gt;;</div><div class='add'>+</div><div class='add'>+		gpios = &lt;&amp;expander1 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		states = &lt;1800000 1&gt;, &lt;2950000 0&gt;;</div><div class='add'>+</div><div class='add'>+		startup-delay-us = &lt;100&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;apps_rsc {</div><div class='add'>+	regulators-0 {</div><div class='add'>+		compatible = "qcom,pmm8654au-rpmh-regulators";</div><div class='add'>+		qcom,pmic-id = "a";</div><div class='add'>+</div><div class='add'>+		vreg_s4a: smps4 {</div><div class='add'>+			regulator-name = "vreg_s4a";</div><div class='add'>+			regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1816000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_s5a: smps5 {</div><div class='add'>+			regulator-name = "vreg_s5a";</div><div class='add'>+			regulator-min-microvolt = &lt;1850000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1996000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_s9a: smps9 {</div><div class='add'>+			regulator-name = "vreg_s9a";</div><div class='add'>+			regulator-min-microvolt = &lt;535000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1120000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l4a: ldo4 {</div><div class='add'>+			regulator-name = "vreg_l4a";</div><div class='add'>+			regulator-min-microvolt = &lt;788000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1050000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+			regulator-allowed-modes = &lt;RPMH_REGULATOR_MODE_LPM</div><div class='add'>+						   RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l5a: ldo5 {</div><div class='add'>+			regulator-name = "vreg_l5a";</div><div class='add'>+			regulator-min-microvolt = &lt;870000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;950000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+			regulator-allowed-modes = &lt;RPMH_REGULATOR_MODE_LPM</div><div class='add'>+						   RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l6a: ldo6 {</div><div class='add'>+			regulator-name = "vreg_l6a";</div><div class='add'>+			regulator-min-microvolt = &lt;870000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;970000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+			regulator-allowed-modes = &lt;RPMH_REGULATOR_MODE_LPM</div><div class='add'>+						   RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l7a: ldo7 {</div><div class='add'>+			regulator-name = "vreg_l7a";</div><div class='add'>+			regulator-min-microvolt = &lt;720000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;950000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+			regulator-allowed-modes = &lt;RPMH_REGULATOR_MODE_LPM</div><div class='add'>+						   RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l8a: ldo8 {</div><div class='add'>+			regulator-name = "vreg_l8a";</div><div class='add'>+			regulator-min-microvolt = &lt;2504000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+			regulator-allowed-modes = &lt;RPMH_REGULATOR_MODE_LPM</div><div class='add'>+						   RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l9a: ldo9 {</div><div class='add'>+			regulator-name = "vreg_l9a";</div><div class='add'>+			regulator-min-microvolt = &lt;2970000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;3544000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+			regulator-allowed-modes = &lt;RPMH_REGULATOR_MODE_LPM</div><div class='add'>+						   RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	regulators-1 {</div><div class='add'>+		compatible = "qcom,pmm8654au-rpmh-regulators";</div><div class='add'>+		qcom,pmic-id = "c";</div><div class='add'>+</div><div class='add'>+		vreg_l1c: ldo1 {</div><div class='add'>+			regulator-name = "vreg_l1c";</div><div class='add'>+			regulator-min-microvolt = &lt;1140000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1260000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+			regulator-allowed-modes = &lt;RPMH_REGULATOR_MODE_LPM</div><div class='add'>+						   RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l2c: ldo2 {</div><div class='add'>+			regulator-name = "vreg_l2c";</div><div class='add'>+			regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+			regulator-allowed-modes = &lt;RPMH_REGULATOR_MODE_LPM</div><div class='add'>+						   RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l3c: ldo3 {</div><div class='add'>+			regulator-name = "vreg_l3c";</div><div class='add'>+			regulator-min-microvolt = &lt;1100000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+			regulator-allowed-modes = &lt;RPMH_REGULATOR_MODE_LPM</div><div class='add'>+						   RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l4c: ldo4 {</div><div class='add'>+			regulator-name = "vreg_l4c";</div><div class='add'>+			regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+			regulator-allowed-modes = &lt;RPMH_REGULATOR_MODE_LPM</div><div class='add'>+						   RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l5c: ldo5 {</div><div class='add'>+			regulator-name = "vreg_l5c";</div><div class='add'>+			regulator-min-microvolt = &lt;1100000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+			regulator-allowed-modes = &lt;RPMH_REGULATOR_MODE_LPM</div><div class='add'>+						   RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l6c: ldo6 {</div><div class='add'>+			regulator-name = "vreg_l6c";</div><div class='add'>+			regulator-min-microvolt = &lt;1620000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1980000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+			regulator-allowed-modes = &lt;RPMH_REGULATOR_MODE_LPM</div><div class='add'>+						   RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l7c: ldo7 {</div><div class='add'>+			regulator-name = "vreg_l7c";</div><div class='add'>+			regulator-min-microvolt = &lt;1620000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;2000000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+			regulator-allowed-modes = &lt;RPMH_REGULATOR_MODE_LPM</div><div class='add'>+						   RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l8c: ldo8 {</div><div class='add'>+			regulator-name = "vreg_l8c";</div><div class='add'>+			regulator-min-microvolt = &lt;2400000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+			regulator-allowed-modes = &lt;RPMH_REGULATOR_MODE_LPM</div><div class='add'>+						   RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l9c: ldo9 {</div><div class='add'>+			regulator-name = "vreg_l9c";</div><div class='add'>+			regulator-min-microvolt = &lt;1650000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;2700000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+			regulator-allowed-modes = &lt;RPMH_REGULATOR_MODE_LPM</div><div class='add'>+						   RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	regulators-2 {</div><div class='add'>+		compatible = "qcom,pmm8654au-rpmh-regulators";</div><div class='add'>+		qcom,pmic-id = "e";</div><div class='add'>+</div><div class='add'>+		vreg_s4e: smps4 {</div><div class='add'>+			regulator-name = "vreg_s4e";</div><div class='add'>+			regulator-min-microvolt = &lt;970000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1520000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_s7e: smps7 {</div><div class='add'>+			regulator-name = "vreg_s7e";</div><div class='add'>+			regulator-min-microvolt = &lt;1010000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1170000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_s9e: smps9 {</div><div class='add'>+			regulator-name = "vreg_s9e";</div><div class='add'>+			regulator-min-microvolt = &lt;300000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;570000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l6e: ldo6 {</div><div class='add'>+			regulator-name = "vreg_l6e";</div><div class='add'>+			regulator-min-microvolt = &lt;1280000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1450000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+			regulator-allowed-modes = &lt;RPMH_REGULATOR_MODE_LPM</div><div class='add'>+						   RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l8e: ldo8 {</div><div class='add'>+			regulator-name = "vreg_l8e";</div><div class='add'>+			regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1950000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+			regulator-allowed-modes = &lt;RPMH_REGULATOR_MODE_LPM</div><div class='add'>+						   RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethernet0 {</div><div class='add'>+	phy-handle = &lt;&amp;hsgmii_phy0&gt;;</div><div class='add'>+	phy-mode = "2500base-x";</div><div class='add'>+</div><div class='add'>+	pinctrl-0 = &lt;&amp;ethernet0_default&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	snps,mtl-rx-config = &lt;&amp;mtl_rx_setup&gt;;</div><div class='add'>+	snps,mtl-tx-config = &lt;&amp;mtl_tx_setup&gt;;</div><div class='add'>+</div><div class='add'>+	nvmem-cells = &lt;&amp;mac_addr0&gt;;</div><div class='add'>+	nvmem-cell-names = "mac-address";</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		hsgmii_phy0: ethernet-phy@1c {</div><div class='add'>+			compatible = "ethernet-phy-id004d.d101";</div><div class='add'>+			reg = &lt;0x1c&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;11000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;70000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mtl_rx_setup: rx-queues-config {</div><div class='add'>+		snps,rx-queues-to-use = &lt;4&gt;;</div><div class='add'>+		snps,rx-sched-sp;</div><div class='add'>+</div><div class='add'>+		queue0 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,map-to-dma-channel = &lt;0x0&gt;;</div><div class='add'>+			snps,route-up;</div><div class='add'>+			snps,priority = &lt;0x1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue1 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,map-to-dma-channel = &lt;0x1&gt;;</div><div class='add'>+			snps,route-ptp;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue2 {</div><div class='add'>+			snps,avb-algorithm;</div><div class='add'>+			snps,map-to-dma-channel = &lt;0x2&gt;;</div><div class='add'>+			snps,route-avcp;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue3 {</div><div class='add'>+			snps,avb-algorithm;</div><div class='add'>+			snps,map-to-dma-channel = &lt;0x3&gt;;</div><div class='add'>+			snps,priority = &lt;0xc&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mtl_tx_setup: tx-queues-config {</div><div class='add'>+		snps,tx-queues-to-use = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+		queue0 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue1 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue2 {</div><div class='add'>+			snps,avb-algorithm;</div><div class='add'>+			snps,send_slope = &lt;0x1000&gt;;</div><div class='add'>+			snps,idle_slope = &lt;0x1000&gt;;</div><div class='add'>+			snps,high_credit = &lt;0x3e800&gt;;</div><div class='add'>+			snps,low_credit = &lt;0xffc18000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue3 {</div><div class='add'>+			snps,avb-algorithm;</div><div class='add'>+			snps,send_slope = &lt;0x1000&gt;;</div><div class='add'>+			snps,idle_slope = &lt;0x1000&gt;;</div><div class='add'>+			snps,high_credit = &lt;0x3e800&gt;;</div><div class='add'>+			snps,low_credit = &lt;0xffc18000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpi_dma0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpi_dma1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpi_dma2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c18 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	expander0: gpio@38 {</div><div class='add'>+		compatible = "ti,tca9538";</div><div class='add'>+		reg = &lt;0x38&gt;;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	expander1: gpio@39 {</div><div class='add'>+		compatible = "ti,tca9538";</div><div class='add'>+		reg = &lt;0x39&gt;;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	expander2: gpio@3a {</div><div class='add'>+		compatible = "ti,tca9538";</div><div class='add'>+		reg = &lt;0x3a&gt;;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	expander3: gpio@3b {</div><div class='add'>+		compatible = "ti,tca9538";</div><div class='add'>+		reg = &lt;0x3b&gt;;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	eeprom@50 {</div><div class='add'>+		compatible = "giantec,gt24c256c", "atmel,24c256";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		pagesize = &lt;64&gt;;</div><div class='add'>+</div><div class='add'>+		nvmem-layout {</div><div class='add'>+			compatible = "fixed-layout";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			mac_addr0: mac-addr@0 {</div><div class='add'>+				reg = &lt;0x0 0x6&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c19 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	fan_controller: fan@18 {</div><div class='add'>+		compatible = "ti,amc6821";</div><div class='add'>+		reg = &lt;0x18&gt;;</div><div class='add'>+		#pwm-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		fan {</div><div class='add'>+			pwms = &lt;&amp;fan_controller 40000 PWM_POLARITY_INVERTED&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iris {</div><div class='add'>+	firmware-name = "qcom/vpu/vpu30_p4_s6_16mb.mbn";</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdss0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdss0_dp0 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;dp0_hot_plug_det&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdss0_dp0_out {</div><div class='add'>+	data-lanes = &lt;0 1 2 3&gt;;</div><div class='add'>+	link-frequencies = /bits/ 64 &lt;1620000000 2700000000 5400000000 8100000000&gt;;</div><div class='add'>+</div><div class='add'>+	remote-endpoint = &lt;&amp;edp0_connector_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdss0_dp0_phy {</div><div class='add'>+	vdda-phy-supply = &lt;&amp;vreg_l1c&gt;;</div><div class='add'>+	vdda-pll-supply = &lt;&amp;vreg_l4a&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdss0_dp1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;dp1_hot_plug_det&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdss0_dp1_out {</div><div class='add'>+	data-lanes = &lt;0 1 2 3&gt;;</div><div class='add'>+	link-frequencies = /bits/ 64 &lt;1620000000 2700000000 5400000000 8100000000&gt;;</div><div class='add'>+</div><div class='add'>+	remote-endpoint = &lt;&amp;edp1_connector_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdss0_dp1_phy {</div><div class='add'>+	vdda-phy-supply = &lt;&amp;vreg_l1c&gt;;</div><div class='add'>+	vdda-pll-supply = &lt;&amp;vreg_l4a&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	perst-gpios = &lt;&amp;tlmm 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	wake-gpios = &lt;&amp;tlmm 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl-0 = &lt;&amp;pcie0_default_state&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0_phy {</div><div class='add'>+	vdda-phy-supply = &lt;&amp;vreg_l5a&gt;;</div><div class='add'>+	vdda-pll-supply = &lt;&amp;vreg_l1c&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie1 {</div><div class='add'>+	perst-gpios = &lt;&amp;tlmm 4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	wake-gpios = &lt;&amp;tlmm 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl-0 = &lt;&amp;pcie1_default_state&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie1_phy {</div><div class='add'>+	vdda-phy-supply = &lt;&amp;vreg_l5a&gt;;</div><div class='add'>+	vdda-pll-supply = &lt;&amp;vreg_l1c&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pmm8654au_0_pon_resin {</div><div class='add'>+	linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qup_i2c19_default {</div><div class='add'>+	drive-strength = &lt;2&gt;;</div><div class='add'>+	bias-pull-up;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qupv3_id_0 {</div><div class='add'>+	firmware-name = "qcom/sa8775p/qupv3fw.elf";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qupv3_id_1 {</div><div class='add'>+	firmware-name = "qcom/sa8775p/qupv3fw.elf";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qupv3_id_2 {</div><div class='add'>+	firmware-name = "qcom/sa8775p/qupv3fw.elf";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;remoteproc_adsp {</div><div class='add'>+	firmware-name = "qcom/sa8775p/adsp.mbn";</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;remoteproc_cdsp0 {</div><div class='add'>+	firmware-name = "qcom/sa8775p/cdsp0.mbn";</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;remoteproc_cdsp1 {</div><div class='add'>+	firmware-name = "qcom/sa8775p/cdsp1.mbn";</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;remoteproc_gpdsp0 {</div><div class='add'>+	firmware-name = "qcom/sa8775p/gpdsp0.mbn";</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;remoteproc_gpdsp1 {</div><div class='add'>+	firmware-name = "qcom/sa8775p/gpdsp1.mbn";</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sdhc {</div><div class='add'>+	vmmc-supply = &lt;&amp;vmmc_sdc&gt;;</div><div class='add'>+	vqmmc-supply = &lt;&amp;vreg_sdc&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdc_default&gt;, &lt;&amp;sd_cd&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;sdc_sleep&gt;, &lt;&amp;sd_cd&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+</div><div class='add'>+	bus-width = &lt;4&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;tlmm 36 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	no-mmc;</div><div class='add'>+	no-sdio;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;serdes0 {</div><div class='add'>+	phy-supply = &lt;&amp;vreg_l5a&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sleep_clk {</div><div class='add'>+	clock-frequency = &lt;32768&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tlmm {</div><div class='add'>+	ethernet0_default: ethernet0-default-state {</div><div class='add'>+		ethernet0_mdc: ethernet0-mdc-pins {</div><div class='add'>+			pins = "gpio8";</div><div class='add'>+			function = "emac0_mdc";</div><div class='add'>+			drive-strength = &lt;16&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ethernet0_mdio: ethernet0-mdio-pins {</div><div class='add'>+			pins = "gpio9";</div><div class='add'>+			function = "emac0_mdio";</div><div class='add'>+			drive-strength = &lt;16&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_default_state: pcie0-default-state {</div><div class='add'>+		clkreq-pins {</div><div class='add'>+			pins = "gpio1";</div><div class='add'>+			function = "pcie0_clkreq";</div><div class='add'>+			drive-strength = &lt;2&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		perst-pins {</div><div class='add'>+			pins = "gpio2";</div><div class='add'>+			function = "gpio";</div><div class='add'>+			drive-strength = &lt;2&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wake-pins {</div><div class='add'>+			pins = "gpio0";</div><div class='add'>+			function = "gpio";</div><div class='add'>+			drive-strength = &lt;2&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie1_default_state: pcie1-default-state {</div><div class='add'>+		clkreq-pins {</div><div class='add'>+			pins = "gpio3";</div><div class='add'>+			function = "pcie1_clkreq";</div><div class='add'>+			drive-strength = &lt;2&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		perst-pins {</div><div class='add'>+			pins = "gpio4";</div><div class='add'>+			function = "gpio";</div><div class='add'>+			drive-strength = &lt;2&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wake-pins {</div><div class='add'>+			pins = "gpio5";</div><div class='add'>+			function = "gpio";</div><div class='add'>+			drive-strength = &lt;2&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd_cd: sd-cd-state {</div><div class='add'>+		pins = "gpio36";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		bias-pull-up;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart10 {</div><div class='add'>+	compatible = "qcom,geni-debug-uart";</div><div class='add'>+	pinctrl-0 = &lt;&amp;qup_uart10_default&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ufs_mem_hc {</div><div class='add'>+	reset-gpios = &lt;&amp;tlmm 149 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vcc-supply = &lt;&amp;vreg_l8a&gt;;</div><div class='add'>+	vcc-max-microamp = &lt;1100000&gt;;</div><div class='add'>+	vccq-supply = &lt;&amp;vreg_l4c&gt;;</div><div class='add'>+	vccq-max-microamp = &lt;1200000&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ufs_mem_phy {</div><div class='add'>+	vdda-phy-supply = &lt;&amp;vreg_l4a&gt;;</div><div class='add'>+	vdda-pll-supply = &lt;&amp;vreg_l1c&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_0 {</div><div class='add'>+	dr_mode = "peripheral";</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_0_hsphy {</div><div class='add'>+	vdda-pll-supply = &lt;&amp;vreg_l7a&gt;;</div><div class='add'>+	vdda18-supply = &lt;&amp;vreg_l6c&gt;;</div><div class='add'>+	vdda33-supply = &lt;&amp;vreg_l9a&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_0_qmpphy {</div><div class='add'>+	vdda-phy-supply = &lt;&amp;vreg_l1c&gt;;</div><div class='add'>+	vdda-pll-supply = &lt;&amp;vreg_l7a&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xo_board_clk {</div><div class='add'>+	clock-frequency = &lt;38400000&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/lemans-pmics.dtsi b/arch/arm64/boot/dts/qcom/lemans-pmics.dtsi<br/>new file mode 100644<br/>index 000000000000..341119fc8244<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/lemans-pmics.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/lemans-pmics.dtsi</a></div><div class='hunk'>@@ -0,0 +1,239 @@</div><div class='add'>+// SPDX-License-Identifier: BSD-3-Clause</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2023, Linaro Limited</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/spmi/spmi.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	thermal-zones {</div><div class='add'>+		pmm8654au_0_thermal: pm8775-0-thermal {</div><div class='add'>+			polling-delay-passive = &lt;100&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;pmm8654au_0_temp_alarm&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip1 {</div><div class='add'>+					temperature = &lt;125000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmm8654au_1_thermal: pm8775-1-thermal {</div><div class='add'>+			polling-delay-passive = &lt;100&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;pmm8654au_1_temp_alarm&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip1 {</div><div class='add'>+					temperature = &lt;125000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmm8654au_2_thermal: pm8775-2-thermal {</div><div class='add'>+			polling-delay-passive = &lt;100&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;pmm8654au_2_temp_alarm&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip1 {</div><div class='add'>+					temperature = &lt;125000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmm8654au_3_thermal: pm8775-3-thermal {</div><div class='add'>+			polling-delay-passive = &lt;100&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;pmm8654au_3_temp_alarm&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip1 {</div><div class='add'>+					temperature = &lt;125000&gt;;</div><div class='add'>+					hysteresis = &lt;0&gt;;</div><div class='add'>+					type = "critical";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reboot-mode {</div><div class='add'>+		compatible = "nvmem-reboot-mode";</div><div class='add'>+		nvmem-cells = &lt;&amp;reboot_reason&gt;;</div><div class='add'>+		nvmem-cell-names = "reboot-mode";</div><div class='add'>+		mode-recovery = &lt;0x01&gt;;</div><div class='add'>+		mode-bootloader = &lt;0x02&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spmi_bus {</div><div class='add'>+	pmm8654au_0: pmic@0 {</div><div class='add'>+		compatible = "qcom,pmm8654au", "qcom,spmi-pmic";</div><div class='add'>+		reg = &lt;0x0 SPMI_USID&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		pmm8654au_0_temp_alarm: temp-alarm@a00 {</div><div class='add'>+			compatible = "qcom,spmi-temp-alarm";</div><div class='add'>+			reg = &lt;0xa00&gt;;</div><div class='add'>+			interrupts-extended = &lt;&amp;spmi_bus 0x0 0xa 0x0 IRQ_TYPE_EDGE_BOTH&gt;;</div><div class='add'>+			#thermal-sensor-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmm8654au_0_pon: pon@1200 {</div><div class='add'>+			compatible = "qcom,pmk8350-pon";</div><div class='add'>+			reg = &lt;0x1200&gt;, &lt;0x800&gt;;</div><div class='add'>+			reg-names = "hlos", "pbs";</div><div class='add'>+</div><div class='add'>+			pmm8654au_0_pon_pwrkey: pwrkey {</div><div class='add'>+				compatible = "qcom,pmk8350-pwrkey";</div><div class='add'>+				interrupts-extended = &lt;&amp;spmi_bus 0x0 0x12 0x7 IRQ_TYPE_EDGE_BOTH&gt;;</div><div class='add'>+				linux,code = &lt;KEY_POWER&gt;;</div><div class='add'>+				debounce = &lt;15625&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			pmm8654au_0_pon_resin: resin {</div><div class='add'>+				compatible = "qcom,pmk8350-resin";</div><div class='add'>+				interrupts-extended = &lt;&amp;spmi_bus 0x0 0x12 0x6 IRQ_TYPE_EDGE_BOTH&gt;;</div><div class='add'>+				debounce = &lt;15625&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmm8654au_0_rtc: rtc@6100 {</div><div class='add'>+			compatible = "qcom,pmk8350-rtc";</div><div class='add'>+			reg = &lt;0x6100&gt;,</div><div class='add'>+			      &lt;0x6200&gt;;</div><div class='add'>+			reg-names = "rtc",</div><div class='add'>+				    "alarm";</div><div class='add'>+			interrupts = &lt;0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmm8654au_0_gpios: gpio@8800 {</div><div class='add'>+			compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio";</div><div class='add'>+			reg = &lt;0x8800&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			gpio-ranges = &lt;&amp;pmm8654au_0_gpios 0 0 12&gt;;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmm8654au_0_sdam_0: nvram@7100 {</div><div class='add'>+			compatible = "qcom,spmi-sdam";</div><div class='add'>+			reg = &lt;0x7100&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+			ranges = &lt;0 0x7100 0x100&gt;;</div><div class='add'>+</div><div class='add'>+			reboot_reason: reboot-reason@48 {</div><div class='add'>+				reg = &lt;0x48 0x1&gt;;</div><div class='add'>+				bits = &lt;1 7&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmm8654au_1: pmic@2 {</div><div class='add'>+		compatible = "qcom,pmm8654au", "qcom,spmi-pmic";</div><div class='add'>+		reg = &lt;0x2 SPMI_USID&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		pmm8654au_1_temp_alarm: temp-alarm@a00 {</div><div class='add'>+			compatible = "qcom,spmi-temp-alarm";</div><div class='add'>+			reg = &lt;0xa00&gt;;</div><div class='add'>+			interrupts-extended = &lt;&amp;spmi_bus 0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH&gt;;</div><div class='add'>+			#thermal-sensor-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmm8654au_1_gpios: gpio@8800 {</div><div class='add'>+			compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio";</div><div class='add'>+			reg = &lt;0x8800&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			gpio-ranges = &lt;&amp;pmm8654au_1_gpios 0 0 12&gt;;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmm8654au_2: pmic@4 {</div><div class='add'>+		compatible = "qcom,pmm8654au", "qcom,spmi-pmic";</div><div class='add'>+		reg = &lt;0x4 SPMI_USID&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		pmm8654au_2_temp_alarm: temp-alarm@a00 {</div><div class='add'>+			compatible = "qcom,spmi-temp-alarm";</div><div class='add'>+			reg = &lt;0xa00&gt;;</div><div class='add'>+			interrupts-extended = &lt;&amp;spmi_bus 0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH&gt;;</div><div class='add'>+			#thermal-sensor-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmm8654au_2_gpios: gpio@8800 {</div><div class='add'>+			compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio";</div><div class='add'>+			reg = &lt;0x8800&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			gpio-ranges = &lt;&amp;pmm8654au_2_gpios 0 0 12&gt;;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmm8654au_3: pmic@6 {</div><div class='add'>+		compatible = "qcom,pmm8654au", "qcom,spmi-pmic";</div><div class='add'>+		reg = &lt;0x6 SPMI_USID&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		pmm8654au_3_temp_alarm: temp-alarm@a00 {</div><div class='add'>+			compatible = "qcom,spmi-temp-alarm";</div><div class='add'>+			reg = &lt;0xa00&gt;;</div><div class='add'>+			interrupts-extended = &lt;&amp;spmi_bus 0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH&gt;;</div><div class='add'>+			#thermal-sensor-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmm8654au_3_gpios: gpio@8800 {</div><div class='add'>+			compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio";</div><div class='add'>+			reg = &lt;0x8800&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			gpio-ranges = &lt;&amp;pmm8654au_3_gpios 0 0 12&gt;;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi<br/>new file mode 100644<br/>index 000000000000..c69aa2f41ce2<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi</a></div><div class='hunk'>@@ -0,0 +1,1061 @@</div><div class='add'>+// SPDX-License-Identifier: BSD-3-Clause</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2023, Linaro Limited</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/regulator/qcom,rpmh-regulator.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		i2c11 = &amp;i2c11;</div><div class='add'>+		i2c18 = &amp;i2c18;</div><div class='add'>+		serial0 = &amp;uart10;</div><div class='add'>+		serial1 = &amp;uart12;</div><div class='add'>+		serial2 = &amp;uart17;</div><div class='add'>+		spi16 = &amp;spi16;</div><div class='add'>+		ufshc1 = &amp;ufs_mem_hc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vreg_12p0: vreg-12p0-regulator {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VREG_12P0";</div><div class='add'>+</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-min-microvolt = &lt;12000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;12000000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vreg_5p0: vreg-5p0-regulator {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VREG_5P0";</div><div class='add'>+</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-min-microvolt = &lt;5000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;5000000&gt;;</div><div class='add'>+</div><div class='add'>+		vin-supply = &lt;&amp;vreg_12p0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vreg_1p8: vreg-1p8-regulator {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VREG_1P8";</div><div class='add'>+</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+</div><div class='add'>+		vin-supply = &lt;&amp;vreg_5p0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vreg_1p0: vreg-1p0-regulator {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VREG_1P0";</div><div class='add'>+</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-min-microvolt = &lt;1000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1000000&gt;;</div><div class='add'>+</div><div class='add'>+		vin-supply = &lt;&amp;vreg_1p8&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vreg_3p0: vreg-3p0-regulator {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "VREG_3P0";</div><div class='add'>+</div><div class='add'>+		regulator-always-on;</div><div class='add'>+		regulator-boot-on;</div><div class='add'>+		regulator-min-microvolt = &lt;3000000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3000000&gt;;</div><div class='add'>+</div><div class='add'>+		vin-supply = &lt;&amp;vreg_12p0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vreg_conn_1p8: vreg_conn_1p8 {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vreg_conn_1p8";</div><div class='add'>+		startup-delay-us = &lt;4000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;pmm8654au_1_gpios 4 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	vreg_conn_pa: vreg_conn_pa {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "vreg_conn_pa";</div><div class='add'>+		startup-delay-us = &lt;4000&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		gpio = &lt;&amp;pmm8654au_1_gpios 6 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	wcn6855-pmu {</div><div class='add'>+		compatible = "qcom,wcn6855-pmu";</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;bt_en_state&gt;, &lt;&amp;wlan_en_state&gt;;</div><div class='add'>+</div><div class='add'>+		vddio-supply = &lt;&amp;vreg_conn_pa&gt;;</div><div class='add'>+		vddaon-supply = &lt;&amp;vreg_l2c&gt;;</div><div class='add'>+		vddpmu-supply = &lt;&amp;vreg_conn_1p8&gt;;</div><div class='add'>+		vddrfa0p95-supply = &lt;&amp;vreg_l2c&gt;;</div><div class='add'>+		vddrfa1p3-supply = &lt;&amp;vreg_l6e&gt;;</div><div class='add'>+		vddrfa1p9-supply = &lt;&amp;vreg_s5a&gt;;</div><div class='add'>+		vddpcie1p3-supply = &lt;&amp;vreg_l6e&gt;;</div><div class='add'>+		vddpcie1p9-supply = &lt;&amp;vreg_s5a&gt;;</div><div class='add'>+</div><div class='add'>+		bt-enable-gpios = &lt;&amp;pmm8654au_1_gpios 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		wlan-enable-gpios = &lt;&amp;pmm8654au_1_gpios 7 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+		regulators {</div><div class='add'>+			vreg_pmu_rfa_cmn: ldo0 {</div><div class='add'>+				regulator-name = "vreg_pmu_rfa_cmn";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vreg_pmu_aon_0p59: ldo1 {</div><div class='add'>+				regulator-name = "vreg_pmu_aon_0p59";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vreg_pmu_wlcx_0p8: ldo2 {</div><div class='add'>+				regulator-name = "vreg_pmu_wlcx_0p8";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vreg_pmu_wlmx_0p85: ldo3 {</div><div class='add'>+				regulator-name = "vreg_pmu_wlmx_0p85";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vreg_pmu_btcmx_0p85: ldo4 {</div><div class='add'>+				regulator-name = "vreg_pmu_btcmx_0p85";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vreg_pmu_rfa_0p8: ldo5 {</div><div class='add'>+				regulator-name = "vreg_pmu_rfa_0p8";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vreg_pmu_rfa_1p2: ldo6 {</div><div class='add'>+				regulator-name = "vreg_pmu_rfa_1p2";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vreg_pmu_rfa_1p7: ldo7 {</div><div class='add'>+				regulator-name = "vreg_pmu_rfa_1p7";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vreg_pmu_pcie_0p9: ldo8 {</div><div class='add'>+				regulator-name = "vreg_pmu_pcie_0p9";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			vreg_pmu_pcie_1p8: ldo9 {</div><div class='add'>+				regulator-name = "vreg_pmu_pcie_1p8";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dp0-connector {</div><div class='add'>+		compatible = "dp-connector";</div><div class='add'>+		label = "eDP0";</div><div class='add'>+		type = "full-size";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			dp0_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;mdss0_dp0_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dp1-connector {</div><div class='add'>+		compatible = "dp-connector";</div><div class='add'>+		label = "eDP1";</div><div class='add'>+		type = "full-size";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			dp1_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;mdss0_dp1_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dp-dsi0-connector {</div><div class='add'>+		compatible = "dp-connector";</div><div class='add'>+		label = "DSI0";</div><div class='add'>+		type = "full-size";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			dp_dsi0_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;dsi2dp_bridge0_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dp-dsi1-connector {</div><div class='add'>+		compatible = "dp-connector";</div><div class='add'>+		label = "DSI1";</div><div class='add'>+		type = "full-size";</div><div class='add'>+</div><div class='add'>+		port {</div><div class='add'>+			dp_dsi1_connector_in: endpoint {</div><div class='add'>+				remote-endpoint = &lt;&amp;dsi2dp_bridge1_out&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;apps_rsc {</div><div class='add'>+	regulators-0 {</div><div class='add'>+		compatible = "qcom,pmm8654au-rpmh-regulators";</div><div class='add'>+		qcom,pmic-id = "a";</div><div class='add'>+</div><div class='add'>+		vreg_s4a: smps4 {</div><div class='add'>+			regulator-name = "vreg_s4a";</div><div class='add'>+			regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1816000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_s5a: smps5 {</div><div class='add'>+			regulator-name = "vreg_s5a";</div><div class='add'>+			regulator-min-microvolt = &lt;1850000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1996000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_s9a: smps9 {</div><div class='add'>+			regulator-name = "vreg_s9a";</div><div class='add'>+			regulator-min-microvolt = &lt;535000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1120000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l4a: ldo4 {</div><div class='add'>+			regulator-name = "vreg_l4a";</div><div class='add'>+			regulator-min-microvolt = &lt;788000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1050000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+			regulator-allowed-modes = &lt;RPMH_REGULATOR_MODE_LPM</div><div class='add'>+						   RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l5a: ldo5 {</div><div class='add'>+			regulator-name = "vreg_l5a";</div><div class='add'>+			regulator-min-microvolt = &lt;870000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;950000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+			regulator-allowed-modes = &lt;RPMH_REGULATOR_MODE_LPM</div><div class='add'>+						   RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l6a: ldo6 {</div><div class='add'>+			regulator-name = "vreg_l6a";</div><div class='add'>+			regulator-min-microvolt = &lt;870000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;970000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+			regulator-allowed-modes = &lt;RPMH_REGULATOR_MODE_LPM</div><div class='add'>+						   RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l7a: ldo7 {</div><div class='add'>+			regulator-name = "vreg_l7a";</div><div class='add'>+			regulator-min-microvolt = &lt;720000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;950000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+			regulator-allowed-modes = &lt;RPMH_REGULATOR_MODE_LPM</div><div class='add'>+						   RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l8a: ldo8 {</div><div class='add'>+			regulator-name = "vreg_l8a";</div><div class='add'>+			regulator-min-microvolt = &lt;2504000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+			regulator-allowed-modes = &lt;RPMH_REGULATOR_MODE_LPM</div><div class='add'>+						   RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l9a: ldo9 {</div><div class='add'>+			regulator-name = "vreg_l9a";</div><div class='add'>+			regulator-min-microvolt = &lt;2970000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;3544000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+			regulator-allowed-modes = &lt;RPMH_REGULATOR_MODE_LPM</div><div class='add'>+						   RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	regulators-1 {</div><div class='add'>+		compatible = "qcom,pmm8654au-rpmh-regulators";</div><div class='add'>+		qcom,pmic-id = "c";</div><div class='add'>+</div><div class='add'>+		vreg_l1c: ldo1 {</div><div class='add'>+			regulator-name = "vreg_l1c";</div><div class='add'>+			regulator-min-microvolt = &lt;1140000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1260000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+			regulator-allowed-modes = &lt;RPMH_REGULATOR_MODE_LPM</div><div class='add'>+						   RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l2c: ldo2 {</div><div class='add'>+			regulator-name = "vreg_l2c";</div><div class='add'>+			regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1100000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+			regulator-allowed-modes = &lt;RPMH_REGULATOR_MODE_LPM</div><div class='add'>+						   RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l3c: ldo3 {</div><div class='add'>+			regulator-name = "vreg_l3c";</div><div class='add'>+			regulator-min-microvolt = &lt;1100000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+			regulator-allowed-modes = &lt;RPMH_REGULATOR_MODE_LPM</div><div class='add'>+						   RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l4c: ldo4 {</div><div class='add'>+			regulator-name = "vreg_l4c";</div><div class='add'>+			regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			/*</div><div class='add'>+			 * FIXME: This should have regulator-allow-set-load but</div><div class='add'>+			 * we're getting an over-current fault from the PMIC</div><div class='add'>+			 * when switching to LPM.</div><div class='add'>+			 */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l5c: ldo5 {</div><div class='add'>+			regulator-name = "vreg_l5c";</div><div class='add'>+			regulator-min-microvolt = &lt;1100000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1300000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+			regulator-allowed-modes = &lt;RPMH_REGULATOR_MODE_LPM</div><div class='add'>+						   RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l6c: ldo6 {</div><div class='add'>+			regulator-name = "vreg_l6c";</div><div class='add'>+			regulator-min-microvolt = &lt;1620000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1980000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+			regulator-allowed-modes = &lt;RPMH_REGULATOR_MODE_LPM</div><div class='add'>+						   RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l7c: ldo7 {</div><div class='add'>+			regulator-name = "vreg_l7c";</div><div class='add'>+			regulator-min-microvolt = &lt;1620000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;2000000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+			regulator-allowed-modes = &lt;RPMH_REGULATOR_MODE_LPM</div><div class='add'>+						   RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l8c: ldo8 {</div><div class='add'>+			regulator-name = "vreg_l8c";</div><div class='add'>+			regulator-min-microvolt = &lt;2400000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+			regulator-allowed-modes = &lt;RPMH_REGULATOR_MODE_LPM</div><div class='add'>+						   RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l9c: ldo9 {</div><div class='add'>+			regulator-name = "vreg_l9c";</div><div class='add'>+			regulator-min-microvolt = &lt;1650000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;2700000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+			regulator-allowed-modes = &lt;RPMH_REGULATOR_MODE_LPM</div><div class='add'>+						   RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	regulators-2 {</div><div class='add'>+		compatible = "qcom,pmm8654au-rpmh-regulators";</div><div class='add'>+		qcom,pmic-id = "e";</div><div class='add'>+</div><div class='add'>+		vreg_s4e: smps4 {</div><div class='add'>+			regulator-name = "vreg_s4e";</div><div class='add'>+			regulator-min-microvolt = &lt;970000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1520000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_s7e: smps7 {</div><div class='add'>+			regulator-name = "vreg_s7e";</div><div class='add'>+			regulator-min-microvolt = &lt;1010000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1170000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_s9e: smps9 {</div><div class='add'>+			regulator-name = "vreg_s9e";</div><div class='add'>+			regulator-min-microvolt = &lt;300000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;570000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l6e: ldo6 {</div><div class='add'>+			regulator-name = "vreg_l6e";</div><div class='add'>+			regulator-min-microvolt = &lt;1280000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1450000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+			regulator-allowed-modes = &lt;RPMH_REGULATOR_MODE_LPM</div><div class='add'>+						   RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l8e: ldo8 {</div><div class='add'>+			regulator-name = "vreg_l8e";</div><div class='add'>+			regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1950000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+			regulator-allowed-modes = &lt;RPMH_REGULATOR_MODE_LPM</div><div class='add'>+						   RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c11 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c18 {</div><div class='add'>+	clock-frequency = &lt;400000&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	io_expander: gpio@74 {</div><div class='add'>+		compatible = "ti,tca9539";</div><div class='add'>+		reg = &lt;0x74&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;tlmm 98 IRQ_TYPE_EDGE_BOTH&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		interrupt-controller;</div><div class='add'>+		#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;tlmm 97 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;io_expander_intr_active&gt;,</div><div class='add'>+			    &lt;&amp;io_expander_reset_active&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	i2c-mux@70 {</div><div class='add'>+		compatible = "nxp,pca9543";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+		reg = &lt;0x70&gt;;</div><div class='add'>+</div><div class='add'>+		i2c@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			bridge@58 {</div><div class='add'>+				compatible = "analogix,anx7625";</div><div class='add'>+				reg = &lt;0x58&gt;;</div><div class='add'>+				interrupts-extended = &lt;&amp;io_expander 2 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+				enable-gpios = &lt;&amp;io_expander 1 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+				reset-gpios = &lt;&amp;io_expander 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+				vdd10-supply = &lt;&amp;vreg_1p0&gt;;</div><div class='add'>+				vdd18-supply = &lt;&amp;vreg_1p8&gt;;</div><div class='add'>+				vdd33-supply = &lt;&amp;vreg_3p0&gt;;</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						dsi2dp_bridge0_in: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mdss0_dsi0_out&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						dsi2dp_bridge0_out: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;dp_dsi0_connector_in&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		i2c@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			bridge@58 {</div><div class='add'>+				compatible = "analogix,anx7625";</div><div class='add'>+				reg = &lt;0x58&gt;;</div><div class='add'>+				interrupts-extended = &lt;&amp;io_expander 10 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+				enable-gpios = &lt;&amp;io_expander 9 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+				reset-gpios = &lt;&amp;io_expander 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+				vdd10-supply = &lt;&amp;vreg_1p0&gt;;</div><div class='add'>+				vdd18-supply = &lt;&amp;vreg_1p8&gt;;</div><div class='add'>+				vdd33-supply = &lt;&amp;vreg_3p0&gt;;</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						dsi2dp_bridge1_in: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mdss0_dsi1_out&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						dsi2dp_bridge1_out: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;dp_dsi1_connector_in&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iris {</div><div class='add'>+	firmware-name = "qcom/vpu/vpu30_p4_s6.mbn";</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdss0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdss0_dp0 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;dp0_hot_plug_det&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdss0_dp0_out {</div><div class='add'>+	data-lanes = &lt;0 1 2 3&gt;;</div><div class='add'>+	link-frequencies = /bits/ 64 &lt;1620000000 2700000000 5400000000 8100000000&gt;;</div><div class='add'>+	remote-endpoint = &lt;&amp;dp0_connector_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdss0_dp0_phy {</div><div class='add'>+	vdda-phy-supply = &lt;&amp;vreg_l1c&gt;;</div><div class='add'>+	vdda-pll-supply = &lt;&amp;vreg_l4a&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdss0_dp1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;dp1_hot_plug_det&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdss0_dp1_out {</div><div class='add'>+	data-lanes = &lt;0 1 2 3&gt;;</div><div class='add'>+	link-frequencies = /bits/ 64 &lt;1620000000 2700000000 5400000000 8100000000&gt;;</div><div class='add'>+	remote-endpoint = &lt;&amp;dp1_connector_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdss0_dp1_phy {</div><div class='add'>+	vdda-phy-supply = &lt;&amp;vreg_l1c&gt;;</div><div class='add'>+	vdda-pll-supply = &lt;&amp;vreg_l4a&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdss0_dsi0 {</div><div class='add'>+	vdda-supply = &lt;&amp;vreg_l1c&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdss0_dsi0_out {</div><div class='add'>+	data-lanes = &lt;0 1 2 3&gt;;</div><div class='add'>+	remote-endpoint = &lt;&amp;dsi2dp_bridge0_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdss0_dsi0_phy {</div><div class='add'>+	vdds-supply = &lt;&amp;vreg_l4a&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdss0_dsi1 {</div><div class='add'>+	vdda-supply = &lt;&amp;vreg_l1c&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdss0_dsi1_out {</div><div class='add'>+	data-lanes = &lt;0 1 2 3&gt;;</div><div class='add'>+	remote-endpoint = &lt;&amp;dsi2dp_bridge1_in&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mdss0_dsi1_phy {</div><div class='add'>+	vdds-supply = &lt;&amp;vreg_l4a&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pmm8654au_0_gpios {</div><div class='add'>+	gpio-line-names = "DS_EN",</div><div class='add'>+			  "POFF_COMPLETE",</div><div class='add'>+			  "UFS0_VER_ID",</div><div class='add'>+			  "FAST_POFF",</div><div class='add'>+			  "DBU1_PON_DONE",</div><div class='add'>+			  "AOSS_SLEEP",</div><div class='add'>+			  "CAM_DES0_EN",</div><div class='add'>+			  "CAM_DES1_EN",</div><div class='add'>+			  "CAM_DES2_EN",</div><div class='add'>+			  "CAM_DES3_EN",</div><div class='add'>+			  "UEFI",</div><div class='add'>+			  "ANALOG_PON_OPT";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pmm8654au_0_pon_resin {</div><div class='add'>+	linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pmm8654au_1_gpios {</div><div class='add'>+	gpio-line-names = "PMIC_C_ID0",</div><div class='add'>+			  "PMIC_C_ID1",</div><div class='add'>+			  "UFS1_VER_ID",</div><div class='add'>+			  "IPA_PWR",</div><div class='add'>+			  "",</div><div class='add'>+			  "WLAN_DBU4_EN",</div><div class='add'>+			  "WLAN_EN",</div><div class='add'>+			  "BT_EN",</div><div class='add'>+			  "USB2_PWR_EN",</div><div class='add'>+			  "USB2_FAULT";</div><div class='add'>+</div><div class='add'>+	wlan_en_state: wlan-en-state {</div><div class='add'>+		pins = "gpio7";</div><div class='add'>+		function = "normal";</div><div class='add'>+		output-low;</div><div class='add'>+		bias-pull-down;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	bt_en_state: bt-en-state {</div><div class='add'>+		pins = "gpio8";</div><div class='add'>+		function = "normal";</div><div class='add'>+		output-low;</div><div class='add'>+		bias-pull-down;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb2_en_state: usb2-en-state {</div><div class='add'>+		pins = "gpio9";</div><div class='add'>+		function = "normal";</div><div class='add'>+		output-high;</div><div class='add'>+		power-source = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pmm8654au_2_gpios {</div><div class='add'>+	gpio-line-names = "PMIC_E_ID0",</div><div class='add'>+			  "PMIC_E_ID1",</div><div class='add'>+			  "USB0_PWR_EN",</div><div class='add'>+			  "USB0_FAULT",</div><div class='add'>+			  "SENSOR_IRQ_1",</div><div class='add'>+			  "SENSOR_IRQ_2",</div><div class='add'>+			  "SENSOR_RST",</div><div class='add'>+			  "SGMIIO0_RST",</div><div class='add'>+			  "SGMIIO1_RST",</div><div class='add'>+			  "USB1_PWR_ENABLE",</div><div class='add'>+			  "USB1_FAULT",</div><div class='add'>+			  "VMON_SPX8";</div><div class='add'>+</div><div class='add'>+	usb0_en_state: usb0-en-state {</div><div class='add'>+		pins = "gpio3";</div><div class='add'>+		function = "normal";</div><div class='add'>+		output-high;</div><div class='add'>+		power-source = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb1_en_state: usb1-en-state {</div><div class='add'>+		pins = "gpio10";</div><div class='add'>+		function = "normal";</div><div class='add'>+		output-high;</div><div class='add'>+		power-source = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pmm8654au_3_gpios {</div><div class='add'>+	gpio-line-names = "PMIC_G_ID0",</div><div class='add'>+			  "PMIC_G_ID1",</div><div class='add'>+			  "GNSS_RST",</div><div class='add'>+			  "GNSS_EN",</div><div class='add'>+			  "GNSS_BOOT_MODE";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qupv3_id_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qupv3_id_2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qup_spi16_default {</div><div class='add'>+	drive-strength = &lt;6&gt;;</div><div class='add'>+	bias-disable;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qup_i2c11_default {</div><div class='add'>+	drive-strength = &lt;2&gt;;</div><div class='add'>+	bias-pull-up;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qup_i2c18_default {</div><div class='add'>+	drive-strength = &lt;2&gt;;</div><div class='add'>+	bias-pull-up;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qup_uart12_cts {</div><div class='add'>+	bias-disable;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qup_uart12_rts {</div><div class='add'>+	bias-pull-down;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qup_uart12_tx {</div><div class='add'>+	bias-pull-up;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qup_uart12_rx {</div><div class='add'>+	bias-pull-down;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qup_uart17_cts {</div><div class='add'>+	bias-disable;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qup_uart17_rts {</div><div class='add'>+	bias-pull-down;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qup_uart17_tx {</div><div class='add'>+	bias-pull-up;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qup_uart17_rx {</div><div class='add'>+	bias-pull-down;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;serdes0 {</div><div class='add'>+	phy-supply = &lt;&amp;vreg_l5a&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;serdes1 {</div><div class='add'>+	phy-supply = &lt;&amp;vreg_l5a&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sleep_clk {</div><div class='add'>+	clock-frequency = &lt;32000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;spi16 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tlmm {</div><div class='add'>+	dp0_hot_plug_det: dp0-hot-plug-det-state {</div><div class='add'>+		pins = "gpio101";</div><div class='add'>+		function = "edp0_hot";</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dp1_hot_plug_det: dp1-hot-plug-det-state {</div><div class='add'>+		pins = "gpio102";</div><div class='add'>+		function = "edp1_hot";</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	io_expander_intr_active: io-expander-intr-active-state {</div><div class='add'>+		pins = "gpio98";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	io_expander_reset_active: io-expander-reset-active-state {</div><div class='add'>+		pins = "gpio97";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+		output-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_default_state: pcie0-default-state {</div><div class='add'>+		perst-pins {</div><div class='add'>+			pins = "gpio2";</div><div class='add'>+			function = "gpio";</div><div class='add'>+			drive-strength = &lt;2&gt;;</div><div class='add'>+			bias-pull-down;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		clkreq-pins {</div><div class='add'>+			pins = "gpio1";</div><div class='add'>+			function = "pcie0_clkreq";</div><div class='add'>+			drive-strength = &lt;2&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wake-pins {</div><div class='add'>+			pins = "gpio0";</div><div class='add'>+			function = "gpio";</div><div class='add'>+			drive-strength = &lt;2&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie1_default_state: pcie1-default-state {</div><div class='add'>+		perst-pins {</div><div class='add'>+			pins = "gpio4";</div><div class='add'>+			function = "gpio";</div><div class='add'>+			drive-strength = &lt;2&gt;;</div><div class='add'>+			bias-pull-down;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		clkreq-pins {</div><div class='add'>+			pins = "gpio3";</div><div class='add'>+			function = "pcie1_clkreq";</div><div class='add'>+			drive-strength = &lt;2&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		wake-pins {</div><div class='add'>+			pins = "gpio5";</div><div class='add'>+			function = "gpio";</div><div class='add'>+			drive-strength = &lt;2&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0 {</div><div class='add'>+	perst-gpios = &lt;&amp;tlmm 2 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	wake-gpios = &lt;&amp;tlmm 0 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pcie0_default_state&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie1 {</div><div class='add'>+	perst-gpios = &lt;&amp;tlmm 4 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	wake-gpios = &lt;&amp;tlmm 5 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;pcie1_default_state&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie0_phy {</div><div class='add'>+	vdda-phy-supply = &lt;&amp;vreg_l5a&gt;;</div><div class='add'>+	vdda-pll-supply = &lt;&amp;vreg_l1c&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcie1_phy {</div><div class='add'>+	vdda-phy-supply = &lt;&amp;vreg_l5a&gt;;</div><div class='add'>+	vdda-pll-supply = &lt;&amp;vreg_l1c&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pcieport0 {</div><div class='add'>+	wifi@0 {</div><div class='add'>+		compatible = "pci17cb,1101";</div><div class='add'>+		reg = &lt;0x10000 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+</div><div class='add'>+		qcom,calibration-variant = "QC_SA8775P_Ride";</div><div class='add'>+</div><div class='add'>+		vddrfacmn-supply = &lt;&amp;vreg_pmu_rfa_cmn&gt;;</div><div class='add'>+		vddaon-supply = &lt;&amp;vreg_pmu_aon_0p59&gt;;</div><div class='add'>+		vddwlcx-supply = &lt;&amp;vreg_pmu_wlcx_0p8&gt;;</div><div class='add'>+		vddwlmx-supply = &lt;&amp;vreg_pmu_wlmx_0p85&gt;;</div><div class='add'>+		vddrfa0p8-supply = &lt;&amp;vreg_pmu_rfa_0p8&gt;;</div><div class='add'>+		vddrfa1p2-supply = &lt;&amp;vreg_pmu_rfa_1p2&gt;;</div><div class='add'>+		vddrfa1p7-supply = &lt;&amp;vreg_pmu_rfa_1p7&gt;;</div><div class='add'>+		vddpcie0p9-supply = &lt;&amp;vreg_pmu_pcie_0p9&gt;;</div><div class='add'>+		vddpcie1p8-supply = &lt;&amp;vreg_pmu_pcie_1p8&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;remoteproc_adsp {</div><div class='add'>+	firmware-name = "qcom/sa8775p/adsp.mbn";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;remoteproc_cdsp0 {</div><div class='add'>+	firmware-name = "qcom/sa8775p/cdsp0.mbn";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;remoteproc_cdsp1 {</div><div class='add'>+	firmware-name = "qcom/sa8775p/cdsp1.mbn";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;remoteproc_gpdsp0 {</div><div class='add'>+	firmware-name = "qcom/sa8775p/gpdsp0.mbn";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;remoteproc_gpdsp1 {</div><div class='add'>+	firmware-name = "qcom/sa8775p/gpdsp1.mbn";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart10 {</div><div class='add'>+	compatible = "qcom,geni-debug-uart";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart12 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;qup_uart12_default&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart17 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;qup_uart17_default&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	bluetooth {</div><div class='add'>+		compatible = "qcom,wcn6855-bt";</div><div class='add'>+		firmware-name = "QCA6698/hpnv21", "QCA6698/hpbtfw21.tlv";</div><div class='add'>+</div><div class='add'>+		vddrfacmn-supply = &lt;&amp;vreg_pmu_rfa_cmn&gt;;</div><div class='add'>+		vddaon-supply = &lt;&amp;vreg_pmu_aon_0p59&gt;;</div><div class='add'>+		vddbtcmx-supply = &lt;&amp;vreg_pmu_btcmx_0p85&gt;;</div><div class='add'>+		vddrfa0p8-supply = &lt;&amp;vreg_pmu_rfa_0p8&gt;;</div><div class='add'>+		vddrfa1p2-supply = &lt;&amp;vreg_pmu_rfa_1p2&gt;;</div><div class='add'>+		vddrfa1p7-supply = &lt;&amp;vreg_pmu_rfa_1p7&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ufs_mem_hc {</div><div class='add'>+	reset-gpios = &lt;&amp;tlmm 149 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vcc-supply = &lt;&amp;vreg_l8a&gt;;</div><div class='add'>+	vcc-max-microamp = &lt;1100000&gt;;</div><div class='add'>+	vccq-supply = &lt;&amp;vreg_l4c&gt;;</div><div class='add'>+	vccq-max-microamp = &lt;1200000&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ufs_mem_phy {</div><div class='add'>+	vdda-phy-supply = &lt;&amp;vreg_l4a&gt;;</div><div class='add'>+	vdda-pll-supply = &lt;&amp;vreg_l1c&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_0 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;usb0_en_state&gt;;</div><div class='add'>+	dr_mode = "peripheral";</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_0_hsphy {</div><div class='add'>+	vdda-pll-supply = &lt;&amp;vreg_l7a&gt;;</div><div class='add'>+	vdda18-supply = &lt;&amp;vreg_l6c&gt;;</div><div class='add'>+	vdda33-supply = &lt;&amp;vreg_l9a&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_0_qmpphy {</div><div class='add'>+	vdda-phy-supply = &lt;&amp;vreg_l1c&gt;;</div><div class='add'>+	vdda-pll-supply = &lt;&amp;vreg_l7a&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_1 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;usb1_en_state&gt;;</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_1_hsphy {</div><div class='add'>+	vdda-pll-supply = &lt;&amp;vreg_l7a&gt;;</div><div class='add'>+	vdda18-supply = &lt;&amp;vreg_l6c&gt;;</div><div class='add'>+	vdda33-supply = &lt;&amp;vreg_l9a&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_1_qmpphy {</div><div class='add'>+	vdda-phy-supply = &lt;&amp;vreg_l1c&gt;;</div><div class='add'>+	vdda-pll-supply = &lt;&amp;vreg_l7a&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_2 {</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+	pinctrl-0 = &lt;&amp;usb2_en_state&gt;;</div><div class='add'>+	dr_mode = "host";</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_2_hsphy {</div><div class='add'>+	vdda-pll-supply = &lt;&amp;vreg_l7a&gt;;</div><div class='add'>+	vdda18-supply = &lt;&amp;vreg_l6c&gt;;</div><div class='add'>+	vdda33-supply = &lt;&amp;vreg_l9a&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;xo_board_clk {</div><div class='add'>+	clock-frequency = &lt;38400000&gt;;</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/lemans-ride-ethernet-88ea1512.dtsi b/arch/arm64/boot/dts/qcom/lemans-ride-ethernet-88ea1512.dtsi<br/>new file mode 100644<br/>index 000000000000..9d6bbe1447a4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/lemans-ride-ethernet-88ea1512.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/lemans-ride-ethernet-88ea1512.dtsi</a></div><div class='hunk'>@@ -0,0 +1,205 @@</div><div class='add'>+// SPDX-License-Identifier: BSD-3-Clause</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2023, Linaro Limited</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Ethernet card for Lemans based Ride boards.</div><div class='add'>+ * It supports 2x 1G - SGMII (Marvell 88EA1512-B2) phy for Main domain</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;ethernet0;</div><div class='add'>+		ethernet1 = &amp;ethernet1;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tlmm {</div><div class='add'>+	ethernet0_default: ethernet0-default-state {</div><div class='add'>+		ethernet0_mdc: ethernet0-mdc-pins {</div><div class='add'>+			pins = "gpio8";</div><div class='add'>+			function = "emac0_mdc";</div><div class='add'>+			drive-strength = &lt;16&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ethernet0_mdio: ethernet0-mdio-pins {</div><div class='add'>+			pins = "gpio9";</div><div class='add'>+			function = "emac0_mdio";</div><div class='add'>+			drive-strength = &lt;16&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethernet0 {</div><div class='add'>+	phy-handle = &lt;&amp;sgmii_phy0&gt;;</div><div class='add'>+	phy-mode = "sgmii";</div><div class='add'>+</div><div class='add'>+	pinctrl-0 = &lt;&amp;ethernet0_default&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	snps,mtl-rx-config = &lt;&amp;mtl_rx_setup&gt;;</div><div class='add'>+	snps,mtl-tx-config = &lt;&amp;mtl_tx_setup&gt;;</div><div class='add'>+	snps,ps-speed = &lt;1000&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		sgmii_phy0: phy@8 {</div><div class='add'>+			compatible = "ethernet-phy-id0141.0dd4";</div><div class='add'>+			reg = &lt;0x8&gt;;</div><div class='add'>+			device_type = "ethernet-phy";</div><div class='add'>+			interrupts-extended = &lt;&amp;tlmm 7 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;11000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;70000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sgmii_phy1: phy@a {</div><div class='add'>+			compatible = "ethernet-phy-id0141.0dd4";</div><div class='add'>+			reg = &lt;0xa&gt;;</div><div class='add'>+			device_type = "ethernet-phy";</div><div class='add'>+			interrupts-extended = &lt;&amp;tlmm 26 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;11000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;70000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mtl_rx_setup: rx-queues-config {</div><div class='add'>+		snps,rx-queues-to-use = &lt;4&gt;;</div><div class='add'>+		snps,rx-sched-sp;</div><div class='add'>+</div><div class='add'>+		queue0 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,map-to-dma-channel = &lt;0x0&gt;;</div><div class='add'>+			snps,route-up;</div><div class='add'>+			snps,priority = &lt;0x1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue1 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,map-to-dma-channel = &lt;0x1&gt;;</div><div class='add'>+			snps,route-ptp;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue2 {</div><div class='add'>+			snps,avb-algorithm;</div><div class='add'>+			snps,map-to-dma-channel = &lt;0x2&gt;;</div><div class='add'>+			snps,route-avcp;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue3 {</div><div class='add'>+			snps,avb-algorithm;</div><div class='add'>+			snps,map-to-dma-channel = &lt;0x3&gt;;</div><div class='add'>+			snps,priority = &lt;0xc&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mtl_tx_setup: tx-queues-config {</div><div class='add'>+		snps,tx-queues-to-use = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+		queue0 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue1 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue2 {</div><div class='add'>+			snps,avb-algorithm;</div><div class='add'>+			snps,send_slope = &lt;0x1000&gt;;</div><div class='add'>+			snps,idle_slope = &lt;0x1000&gt;;</div><div class='add'>+			snps,high_credit = &lt;0x3e800&gt;;</div><div class='add'>+			snps,low_credit = &lt;0xffc18000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue3 {</div><div class='add'>+			snps,avb-algorithm;</div><div class='add'>+			snps,send_slope = &lt;0x1000&gt;;</div><div class='add'>+			snps,idle_slope = &lt;0x1000&gt;;</div><div class='add'>+			snps,high_credit = &lt;0x3e800&gt;;</div><div class='add'>+			snps,low_credit = &lt;0xffc18000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethernet1 {</div><div class='add'>+	phy-handle = &lt;&amp;sgmii_phy1&gt;;</div><div class='add'>+	phy-mode = "sgmii";</div><div class='add'>+</div><div class='add'>+	snps,mtl-rx-config = &lt;&amp;mtl_rx_setup1&gt;;</div><div class='add'>+	snps,mtl-tx-config = &lt;&amp;mtl_tx_setup1&gt;;</div><div class='add'>+	snps,ps-speed = &lt;1000&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mtl_rx_setup1: rx-queues-config {</div><div class='add'>+		snps,rx-queues-to-use = &lt;4&gt;;</div><div class='add'>+		snps,rx-sched-sp;</div><div class='add'>+</div><div class='add'>+		queue0 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,map-to-dma-channel = &lt;0x0&gt;;</div><div class='add'>+			snps,route-up;</div><div class='add'>+			snps,priority = &lt;0x1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue1 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,map-to-dma-channel = &lt;0x1&gt;;</div><div class='add'>+			snps,route-ptp;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue2 {</div><div class='add'>+			snps,avb-algorithm;</div><div class='add'>+			snps,map-to-dma-channel = &lt;0x2&gt;;</div><div class='add'>+			snps,route-avcp;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue3 {</div><div class='add'>+			snps,avb-algorithm;</div><div class='add'>+			snps,map-to-dma-channel = &lt;0x3&gt;;</div><div class='add'>+			snps,priority = &lt;0xc&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mtl_tx_setup1: tx-queues-config {</div><div class='add'>+		snps,tx-queues-to-use = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+		queue0 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue1 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue2 {</div><div class='add'>+			snps,avb-algorithm;</div><div class='add'>+			snps,send_slope = &lt;0x1000&gt;;</div><div class='add'>+			snps,idle_slope = &lt;0x1000&gt;;</div><div class='add'>+			snps,high_credit = &lt;0x3e800&gt;;</div><div class='add'>+			snps,low_credit = &lt;0xffc18000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue3 {</div><div class='add'>+			snps,avb-algorithm;</div><div class='add'>+			snps,send_slope = &lt;0x1000&gt;;</div><div class='add'>+			snps,idle_slope = &lt;0x1000&gt;;</div><div class='add'>+			snps,high_credit = &lt;0x3e800&gt;;</div><div class='add'>+			snps,low_credit = &lt;0xffc18000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/lemans-ride-ethernet-aqr115c.dtsi b/arch/arm64/boot/dts/qcom/lemans-ride-ethernet-aqr115c.dtsi<br/>new file mode 100644<br/>index 000000000000..2d2d9ee5f0d9<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/lemans-ride-ethernet-aqr115c.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/lemans-ride-ethernet-aqr115c.dtsi</a></div><div class='hunk'>@@ -0,0 +1,205 @@</div><div class='add'>+// SPDX-License-Identifier: BSD-3-Clause</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2023, Linaro Limited</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Ethernet card for Lemans based Ride r3 boards.</div><div class='add'>+ * It supports 2x 2.5G - HSGMII (Marvell hsgmii) phy for Main domain</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;ethernet0;</div><div class='add'>+		ethernet1 = &amp;ethernet1;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tlmm {</div><div class='add'>+	ethernet0_default: ethernet0-default-state {</div><div class='add'>+		ethernet0_mdc: ethernet0-mdc-pins {</div><div class='add'>+			pins = "gpio8";</div><div class='add'>+			function = "emac0_mdc";</div><div class='add'>+			drive-strength = &lt;16&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ethernet0_mdio: ethernet0-mdio-pins {</div><div class='add'>+			pins = "gpio9";</div><div class='add'>+			function = "emac0_mdio";</div><div class='add'>+			drive-strength = &lt;16&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethernet0 {</div><div class='add'>+	phy-handle = &lt;&amp;hsgmii_phy0&gt;;</div><div class='add'>+	phy-mode = "2500base-x";</div><div class='add'>+</div><div class='add'>+	pinctrl-0 = &lt;&amp;ethernet0_default&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	snps,mtl-rx-config = &lt;&amp;mtl_rx_setup&gt;;</div><div class='add'>+	snps,mtl-tx-config = &lt;&amp;mtl_tx_setup&gt;;</div><div class='add'>+	snps,ps-speed = &lt;1000&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		hsgmii_phy0: phy@8 {</div><div class='add'>+			compatible = "ethernet-phy-id31c3.1c33";</div><div class='add'>+			reg = &lt;0x8&gt;;</div><div class='add'>+			device_type = "ethernet-phy";</div><div class='add'>+			interrupts-extended = &lt;&amp;tlmm 7 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;11000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;70000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		hsgmii_phy1: phy@0 {</div><div class='add'>+			compatible = "ethernet-phy-id31c3.1c33";</div><div class='add'>+			reg = &lt;0x0&gt;;</div><div class='add'>+			device_type = "ethernet-phy";</div><div class='add'>+			interrupts-extended = &lt;&amp;tlmm 26 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;11000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;70000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mtl_rx_setup: rx-queues-config {</div><div class='add'>+		snps,rx-queues-to-use = &lt;4&gt;;</div><div class='add'>+		snps,rx-sched-sp;</div><div class='add'>+</div><div class='add'>+		queue0 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,map-to-dma-channel = &lt;0x0&gt;;</div><div class='add'>+			snps,route-up;</div><div class='add'>+			snps,priority = &lt;0x1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue1 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,map-to-dma-channel = &lt;0x1&gt;;</div><div class='add'>+			snps,route-ptp;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue2 {</div><div class='add'>+			snps,avb-algorithm;</div><div class='add'>+			snps,map-to-dma-channel = &lt;0x2&gt;;</div><div class='add'>+			snps,route-avcp;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue3 {</div><div class='add'>+			snps,avb-algorithm;</div><div class='add'>+			snps,map-to-dma-channel = &lt;0x3&gt;;</div><div class='add'>+			snps,priority = &lt;0xc&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mtl_tx_setup: tx-queues-config {</div><div class='add'>+		snps,tx-queues-to-use = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+		queue0 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue1 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue2 {</div><div class='add'>+			snps,avb-algorithm;</div><div class='add'>+			snps,send_slope = &lt;0x1000&gt;;</div><div class='add'>+			snps,idle_slope = &lt;0x1000&gt;;</div><div class='add'>+			snps,high_credit = &lt;0x3e800&gt;;</div><div class='add'>+			snps,low_credit = &lt;0xffc18000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue3 {</div><div class='add'>+			snps,avb-algorithm;</div><div class='add'>+			snps,send_slope = &lt;0x1000&gt;;</div><div class='add'>+			snps,idle_slope = &lt;0x1000&gt;;</div><div class='add'>+			snps,high_credit = &lt;0x3e800&gt;;</div><div class='add'>+			snps,low_credit = &lt;0xffc18000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethernet1 {</div><div class='add'>+	phy-handle = &lt;&amp;hsgmii_phy1&gt;;</div><div class='add'>+	phy-mode = "2500base-x";</div><div class='add'>+</div><div class='add'>+	snps,mtl-rx-config = &lt;&amp;mtl_rx_setup1&gt;;</div><div class='add'>+	snps,mtl-tx-config = &lt;&amp;mtl_tx_setup1&gt;;</div><div class='add'>+	snps,ps-speed = &lt;1000&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mtl_rx_setup1: rx-queues-config {</div><div class='add'>+		snps,rx-queues-to-use = &lt;4&gt;;</div><div class='add'>+		snps,rx-sched-sp;</div><div class='add'>+</div><div class='add'>+		queue0 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,map-to-dma-channel = &lt;0x0&gt;;</div><div class='add'>+			snps,route-up;</div><div class='add'>+			snps,priority = &lt;0x1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue1 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,map-to-dma-channel = &lt;0x1&gt;;</div><div class='add'>+			snps,route-ptp;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue2 {</div><div class='add'>+			snps,avb-algorithm;</div><div class='add'>+			snps,map-to-dma-channel = &lt;0x2&gt;;</div><div class='add'>+			snps,route-avcp;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue3 {</div><div class='add'>+			snps,avb-algorithm;</div><div class='add'>+			snps,map-to-dma-channel = &lt;0x3&gt;;</div><div class='add'>+			snps,priority = &lt;0xc&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mtl_tx_setup1: tx-queues-config {</div><div class='add'>+		snps,tx-queues-to-use = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+		queue0 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue1 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue2 {</div><div class='add'>+			snps,avb-algorithm;</div><div class='add'>+			snps,send_slope = &lt;0x1000&gt;;</div><div class='add'>+			snps,idle_slope = &lt;0x1000&gt;;</div><div class='add'>+			snps,high_credit = &lt;0x3e800&gt;;</div><div class='add'>+			snps,low_credit = &lt;0xffc18000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue3 {</div><div class='add'>+			snps,avb-algorithm;</div><div class='add'>+			snps,send_slope = &lt;0x1000&gt;;</div><div class='add'>+			snps,idle_slope = &lt;0x1000&gt;;</div><div class='add'>+			snps,high_credit = &lt;0x3e800&gt;;</div><div class='add'>+			snps,low_credit = &lt;0xffc18000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi<br/>new file mode 100644<br/>index 000000000000..0b154d57ba24<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/lemans.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/lemans.dtsi</a></div><div class='hunk'>@@ -0,0 +1,8617 @@</div><div class='add'>+// SPDX-License-Identifier: BSD-3-Clause</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2023, Linaro Limited</div><div class='add'>+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/interconnect/qcom,icc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,dsi-phy-28nm.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,rpmh.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,sa8775p-dispcc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,sa8775p-gcc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,sa8775p-gpucc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,sa8775p-videocc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,sa8775p-camcc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/dma/qcom-gpi.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interconnect/qcom,osm-l3.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interconnect/qcom,sa8775p-rpmh.h&gt;</div><div class='add'>+#include &lt;dt-bindings/mailbox/qcom-ipcc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/firmware/qcom,scm.h&gt;</div><div class='add'>+#include &lt;dt-bindings/power/qcom-rpmpd.h&gt;</div><div class='add'>+#include &lt;dt-bindings/soc/qcom,gpr.h&gt;</div><div class='add'>+#include &lt;dt-bindings/soc/qcom,rpmh-rsc.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	interrupt-parent = &lt;&amp;intc&gt;;</div><div class='add'>+</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	clocks {</div><div class='add'>+		xo_board_clk: xo-board-clk {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sleep_clk: sleep-clk {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "qcom,kryo";</div><div class='add'>+			reg = &lt;0x0 0x0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			power-domains = &lt;&amp;cpu_pd0&gt;;</div><div class='add'>+			power-domain-names = "psci";</div><div class='add'>+			qcom,freq-domain = &lt;&amp;cpufreq_hw 0&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;100&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu0_opp_table&gt;;</div><div class='add'>+			interconnects = &lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+					&lt;&amp;epss_l3_cl0 MASTER_EPSS_L3_APPS</div><div class='add'>+					 &amp;epss_l3_cl0 SLAVE_EPSS_L3_SHARED&gt;;</div><div class='add'>+			l2_0: l2-cache {</div><div class='add'>+				compatible = "cache";</div><div class='add'>+				cache-level = &lt;2&gt;;</div><div class='add'>+				cache-unified;</div><div class='add'>+				next-level-cache = &lt;&amp;l3_0&gt;;</div><div class='add'>+				l3_0: l3-cache {</div><div class='add'>+					compatible = "cache";</div><div class='add'>+					cache-level = &lt;3&gt;;</div><div class='add'>+					cache-unified;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@100 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "qcom,kryo";</div><div class='add'>+			reg = &lt;0x0 0x100&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			power-domains = &lt;&amp;cpu_pd1&gt;;</div><div class='add'>+			power-domain-names = "psci";</div><div class='add'>+			qcom,freq-domain = &lt;&amp;cpufreq_hw 0&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_1&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;100&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu0_opp_table&gt;;</div><div class='add'>+			interconnects = &lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+					&lt;&amp;epss_l3_cl0 MASTER_EPSS_L3_APPS</div><div class='add'>+					 &amp;epss_l3_cl0 SLAVE_EPSS_L3_SHARED&gt;;</div><div class='add'>+			l2_1: l2-cache {</div><div class='add'>+				compatible = "cache";</div><div class='add'>+				cache-level = &lt;2&gt;;</div><div class='add'>+				cache-unified;</div><div class='add'>+				next-level-cache = &lt;&amp;l3_0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@200 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "qcom,kryo";</div><div class='add'>+			reg = &lt;0x0 0x200&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			power-domains = &lt;&amp;cpu_pd2&gt;;</div><div class='add'>+			power-domain-names = "psci";</div><div class='add'>+			qcom,freq-domain = &lt;&amp;cpufreq_hw 0&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_2&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;100&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu0_opp_table&gt;;</div><div class='add'>+			interconnects = &lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+					&lt;&amp;epss_l3_cl0 MASTER_EPSS_L3_APPS</div><div class='add'>+					 &amp;epss_l3_cl0 SLAVE_EPSS_L3_SHARED&gt;;</div><div class='add'>+			l2_2: l2-cache {</div><div class='add'>+				compatible = "cache";</div><div class='add'>+				cache-level = &lt;2&gt;;</div><div class='add'>+				cache-unified;</div><div class='add'>+				next-level-cache = &lt;&amp;l3_0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@300 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "qcom,kryo";</div><div class='add'>+			reg = &lt;0x0 0x300&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			power-domains = &lt;&amp;cpu_pd3&gt;;</div><div class='add'>+			power-domain-names = "psci";</div><div class='add'>+			qcom,freq-domain = &lt;&amp;cpufreq_hw 0&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_3&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;100&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu0_opp_table&gt;;</div><div class='add'>+			interconnects = &lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+					&lt;&amp;epss_l3_cl0 MASTER_EPSS_L3_APPS</div><div class='add'>+					 &amp;epss_l3_cl0 SLAVE_EPSS_L3_SHARED&gt;;</div><div class='add'>+			l2_3: l2-cache {</div><div class='add'>+				compatible = "cache";</div><div class='add'>+				cache-level = &lt;2&gt;;</div><div class='add'>+				cache-unified;</div><div class='add'>+				next-level-cache = &lt;&amp;l3_0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu4: cpu@10000 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "qcom,kryo";</div><div class='add'>+			reg = &lt;0x0 0x10000&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			power-domains = &lt;&amp;cpu_pd4&gt;;</div><div class='add'>+			power-domain-names = "psci";</div><div class='add'>+			qcom,freq-domain = &lt;&amp;cpufreq_hw 1&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_4&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;100&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu4_opp_table&gt;;</div><div class='add'>+			interconnects = &lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+					&lt;&amp;epss_l3_cl1 MASTER_EPSS_L3_APPS</div><div class='add'>+					 &amp;epss_l3_cl1 SLAVE_EPSS_L3_SHARED&gt;;</div><div class='add'>+			l2_4: l2-cache {</div><div class='add'>+				compatible = "cache";</div><div class='add'>+				cache-level = &lt;2&gt;;</div><div class='add'>+				cache-unified;</div><div class='add'>+				next-level-cache = &lt;&amp;l3_1&gt;;</div><div class='add'>+				l3_1: l3-cache {</div><div class='add'>+					compatible = "cache";</div><div class='add'>+					cache-level = &lt;3&gt;;</div><div class='add'>+					cache-unified;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu5: cpu@10100 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "qcom,kryo";</div><div class='add'>+			reg = &lt;0x0 0x10100&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			power-domains = &lt;&amp;cpu_pd5&gt;;</div><div class='add'>+			power-domain-names = "psci";</div><div class='add'>+			qcom,freq-domain = &lt;&amp;cpufreq_hw 1&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_5&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;100&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu4_opp_table&gt;;</div><div class='add'>+			interconnects = &lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+					&lt;&amp;epss_l3_cl1 MASTER_EPSS_L3_APPS</div><div class='add'>+					 &amp;epss_l3_cl1 SLAVE_EPSS_L3_SHARED&gt;;</div><div class='add'>+			l2_5: l2-cache {</div><div class='add'>+				compatible = "cache";</div><div class='add'>+				cache-level = &lt;2&gt;;</div><div class='add'>+				cache-unified;</div><div class='add'>+				next-level-cache = &lt;&amp;l3_1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu6: cpu@10200 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "qcom,kryo";</div><div class='add'>+			reg = &lt;0x0 0x10200&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			power-domains = &lt;&amp;cpu_pd6&gt;;</div><div class='add'>+			power-domain-names = "psci";</div><div class='add'>+			qcom,freq-domain = &lt;&amp;cpufreq_hw 1&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_6&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;100&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu4_opp_table&gt;;</div><div class='add'>+			interconnects = &lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+					&lt;&amp;epss_l3_cl1 MASTER_EPSS_L3_APPS</div><div class='add'>+					 &amp;epss_l3_cl1 SLAVE_EPSS_L3_SHARED&gt;;</div><div class='add'>+			l2_6: l2-cache {</div><div class='add'>+				compatible = "cache";</div><div class='add'>+				cache-level = &lt;2&gt;;</div><div class='add'>+				cache-unified;</div><div class='add'>+				next-level-cache = &lt;&amp;l3_1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu7: cpu@10300 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "qcom,kryo";</div><div class='add'>+			reg = &lt;0x0 0x10300&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			power-domains = &lt;&amp;cpu_pd7&gt;;</div><div class='add'>+			power-domain-names = "psci";</div><div class='add'>+			qcom,freq-domain = &lt;&amp;cpufreq_hw 1&gt;;</div><div class='add'>+			next-level-cache = &lt;&amp;l2_7&gt;;</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;100&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu4_opp_table&gt;;</div><div class='add'>+			interconnects = &lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+					&lt;&amp;epss_l3_cl1 MASTER_EPSS_L3_APPS</div><div class='add'>+					 &amp;epss_l3_cl1 SLAVE_EPSS_L3_SHARED&gt;;</div><div class='add'>+			l2_7: l2-cache {</div><div class='add'>+				compatible = "cache";</div><div class='add'>+				cache-level = &lt;2&gt;;</div><div class='add'>+				cache-unified;</div><div class='add'>+				next-level-cache = &lt;&amp;l3_1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu-map {</div><div class='add'>+			cluster0 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu2&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu3&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cluster1 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu4&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu5&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu6&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu7&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		idle-states {</div><div class='add'>+			entry-method = "psci";</div><div class='add'>+</div><div class='add'>+			gold_cpu_sleep_0: cpu-sleep-0 {</div><div class='add'>+				compatible = "arm,idle-state";</div><div class='add'>+				idle-state-name = "gold-power-collapse";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x40000003&gt;;</div><div class='add'>+				entry-latency-us = &lt;549&gt;;</div><div class='add'>+				exit-latency-us = &lt;901&gt;;</div><div class='add'>+				min-residency-us = &lt;1774&gt;;</div><div class='add'>+				local-timer-stop;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gold_rail_cpu_sleep_0: cpu-sleep-1 {</div><div class='add'>+				compatible = "arm,idle-state";</div><div class='add'>+				idle-state-name = "gold-rail-power-collapse";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x40000004&gt;;</div><div class='add'>+				entry-latency-us = &lt;702&gt;;</div><div class='add'>+				exit-latency-us = &lt;1061&gt;;</div><div class='add'>+				min-residency-us = &lt;4488&gt;;</div><div class='add'>+				local-timer-stop;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		domain-idle-states {</div><div class='add'>+			cluster_sleep_gold: cluster-sleep-0 {</div><div class='add'>+				compatible = "domain-idle-state";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x41000044&gt;;</div><div class='add'>+				entry-latency-us = &lt;2752&gt;;</div><div class='add'>+				exit-latency-us = &lt;3048&gt;;</div><div class='add'>+				min-residency-us = &lt;6118&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cluster_sleep_apss_rsc_pc: cluster-sleep-1 {</div><div class='add'>+				compatible = "domain-idle-state";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x42000144&gt;;</div><div class='add'>+				entry-latency-us = &lt;3263&gt;;</div><div class='add'>+				exit-latency-us = &lt;6562&gt;;</div><div class='add'>+				min-residency-us = &lt;9987&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpu0_opp_table: opp-table-cpu0 {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+		opp-shared;</div><div class='add'>+</div><div class='add'>+		opp-1267200000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1267200000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(1555200 * 4) (921600 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1363200000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1363200000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(1555200 * 4) (921600 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1459200000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1459200000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(1555200 * 4) (921600 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1536000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1536000000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(1555200 * 4) (921600 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1632000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1632000000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(1708800 * 4) (1228800 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1708800000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1708800000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(1708800 * 4) (1228800 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1785600000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1785600000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(1708800 * 4) (1228800 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1862400000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1862400000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(1708800 * 4) (1228800 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1939200000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1939200000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(1708800 * 4) (1228800 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-2016000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2016000000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(1708800 * 4) (1228800 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-2112000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2112000000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(2092800 * 4) (1555200 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-2188800000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2188800000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(2092800 * 4) (1555200 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-2265600000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2265600000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(2092800 * 4) (1555200 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-2361600000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2361600000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(3196800 * 4) (1612800 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-2457600000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2457600000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(3196800 * 4) (1612800 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-2553600000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2553600000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(3196800 * 4) (1708800 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpu4_opp_table: opp-table-cpu4 {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+		opp-shared;</div><div class='add'>+</div><div class='add'>+		opp-1267200000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1267200000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(1555200 * 4) (921600 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1363200000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1363200000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(1555200 * 4) (921600 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1459200000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1459200000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(1555200 * 4) (921600 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1536000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1536000000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(1555200 * 4) (921600 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1632000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1632000000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(1708800 * 4) (1228800 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1708800000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1708800000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(1708800 * 4) (1228800 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1785600000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1785600000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(1708800 * 4) (1228800 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1862400000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1862400000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(1708800 * 4) (1228800 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1939200000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1939200000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(1708800 * 4) (1228800 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-2016000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2016000000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(1708800 * 4) (1228800 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-2112000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2112000000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(2092800 * 4) (1555200 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-2188800000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2188800000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(2092800 * 4) (1555200 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-2265600000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2265600000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(2092800 * 4) (1555200 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-2361600000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2361600000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(3196800 * 4) (1612800 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-2457600000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2457600000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(3196800 * 4) (1612800 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-2553600000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2553600000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(3196800 * 4) (1708800 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dummy-sink {</div><div class='add'>+		compatible = "arm,coresight-dummy-sink";</div><div class='add'>+</div><div class='add'>+		in-ports {</div><div class='add'>+			port {</div><div class='add'>+				eud_in: endpoint {</div><div class='add'>+					remote-endpoint =</div><div class='add'>+					&lt;&amp;swao_rep_out1&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	firmware {</div><div class='add'>+		scm {</div><div class='add'>+			compatible = "qcom,scm-sa8775p", "qcom,scm";</div><div class='add'>+			qcom,dload-mode = &lt;&amp;tcsr 0x13000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aggre1_noc: interconnect-aggre1-noc {</div><div class='add'>+		compatible = "qcom,sa8775p-aggre1-noc";</div><div class='add'>+		#interconnect-cells = &lt;2&gt;;</div><div class='add'>+		qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	aggre2_noc: interconnect-aggre2-noc {</div><div class='add'>+		compatible = "qcom,sa8775p-aggre2-noc";</div><div class='add'>+		#interconnect-cells = &lt;2&gt;;</div><div class='add'>+		qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_virt: interconnect-clk-virt {</div><div class='add'>+		compatible = "qcom,sa8775p-clk-virt";</div><div class='add'>+		#interconnect-cells = &lt;2&gt;;</div><div class='add'>+		qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	config_noc: interconnect-config-noc {</div><div class='add'>+		compatible = "qcom,sa8775p-config-noc";</div><div class='add'>+		#interconnect-cells = &lt;2&gt;;</div><div class='add'>+		qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dc_noc: interconnect-dc-noc {</div><div class='add'>+		compatible = "qcom,sa8775p-dc-noc";</div><div class='add'>+		#interconnect-cells = &lt;2&gt;;</div><div class='add'>+		qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gem_noc: interconnect-gem-noc {</div><div class='add'>+		compatible = "qcom,sa8775p-gem-noc";</div><div class='add'>+		#interconnect-cells = &lt;2&gt;;</div><div class='add'>+		qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpdsp_anoc: interconnect-gpdsp-anoc {</div><div class='add'>+		compatible = "qcom,sa8775p-gpdsp-anoc";</div><div class='add'>+		#interconnect-cells = &lt;2&gt;;</div><div class='add'>+		qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lpass_ag_noc: interconnect-lpass-ag-noc {</div><div class='add'>+		compatible = "qcom,sa8775p-lpass-ag-noc";</div><div class='add'>+		#interconnect-cells = &lt;2&gt;;</div><div class='add'>+		qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mc_virt: interconnect-mc-virt {</div><div class='add'>+		compatible = "qcom,sa8775p-mc-virt";</div><div class='add'>+		#interconnect-cells = &lt;2&gt;;</div><div class='add'>+		qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mmss_noc: interconnect-mmss-noc {</div><div class='add'>+		compatible = "qcom,sa8775p-mmss-noc";</div><div class='add'>+		#interconnect-cells = &lt;2&gt;;</div><div class='add'>+		qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	nspa_noc: interconnect-nspa-noc {</div><div class='add'>+		compatible = "qcom,sa8775p-nspa-noc";</div><div class='add'>+		#interconnect-cells = &lt;2&gt;;</div><div class='add'>+		qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	nspb_noc: interconnect-nspb-noc {</div><div class='add'>+		compatible = "qcom,sa8775p-nspb-noc";</div><div class='add'>+		#interconnect-cells = &lt;2&gt;;</div><div class='add'>+		qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie_anoc: interconnect-pcie-anoc {</div><div class='add'>+		compatible = "qcom,sa8775p-pcie-anoc";</div><div class='add'>+		#interconnect-cells = &lt;2&gt;;</div><div class='add'>+		qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	system_noc: interconnect-system-noc {</div><div class='add'>+		compatible = "qcom,sa8775p-system-noc";</div><div class='add'>+		#interconnect-cells = &lt;2&gt;;</div><div class='add'>+		qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Will be updated by the bootloader. */</div><div class='add'>+	memory@80000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		reg = &lt;0x0 0x80000000 0x0 0x0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	qup_opp_table_100mhz: opp-table-qup100mhz {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		opp-100000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;100000000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;rpmhpd_opp_svs_l1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu {</div><div class='add'>+		compatible = "arm,armv8-pmuv3";</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-1.0";</div><div class='add'>+		method = "smc";</div><div class='add'>+</div><div class='add'>+		cpu_pd0: power-domain-cpu0 {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cluster_0_pd&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;gold_cpu_sleep_0&gt;,</div><div class='add'>+					     &lt;&amp;gold_rail_cpu_sleep_0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_pd1: power-domain-cpu1 {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cluster_0_pd&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;gold_cpu_sleep_0&gt;,</div><div class='add'>+					     &lt;&amp;gold_rail_cpu_sleep_0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_pd2: power-domain-cpu2 {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cluster_0_pd&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;gold_cpu_sleep_0&gt;,</div><div class='add'>+					     &lt;&amp;gold_rail_cpu_sleep_0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_pd3: power-domain-cpu3 {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cluster_0_pd&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;gold_cpu_sleep_0&gt;,</div><div class='add'>+					     &lt;&amp;gold_rail_cpu_sleep_0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_pd4: power-domain-cpu4 {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cluster_1_pd&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;gold_cpu_sleep_0&gt;,</div><div class='add'>+					     &lt;&amp;gold_rail_cpu_sleep_0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_pd5: power-domain-cpu5 {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cluster_1_pd&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;gold_cpu_sleep_0&gt;,</div><div class='add'>+					     &lt;&amp;gold_rail_cpu_sleep_0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_pd6: power-domain-cpu6 {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cluster_1_pd&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;gold_cpu_sleep_0&gt;,</div><div class='add'>+					     &lt;&amp;gold_rail_cpu_sleep_0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_pd7: power-domain-cpu7 {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cluster_1_pd&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;gold_cpu_sleep_0&gt;,</div><div class='add'>+					     &lt;&amp;gold_rail_cpu_sleep_0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cluster_0_pd: power-domain-cluster0 {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;cluster_sleep_gold&gt;;</div><div class='add'>+			power-domains = &lt;&amp;system_pd&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cluster_1_pd: power-domain-cluster1 {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;cluster_sleep_gold&gt;;</div><div class='add'>+			power-domains = &lt;&amp;system_pd&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		system_pd: power-domain-system {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;cluster_sleep_apss_rsc_pc&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		sail_ss_mem: sail-ss@80000000 {</div><div class='add'>+			reg = &lt;0x0 0x80000000 0x0 0x10000000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		hyp_mem: hyp@90000000 {</div><div class='add'>+			reg = &lt;0x0 0x90000000 0x0 0x600000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		xbl_boot_mem: xbl-boot@90600000 {</div><div class='add'>+			reg = &lt;0x0 0x90600000 0x0 0x200000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aop_image_mem: aop-image@90800000 {</div><div class='add'>+			reg = &lt;0x0 0x90800000 0x0 0x60000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aop_cmd_db_mem: aop-cmd-db@90860000 {</div><div class='add'>+			compatible = "qcom,cmd-db";</div><div class='add'>+			reg = &lt;0x0 0x90860000 0x0 0x20000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uefi_log: uefi-log@908b0000 {</div><div class='add'>+			reg = &lt;0x0 0x908b0000 0x0 0x10000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ddr_training_checksum: ddr-training-checksum@908c0000 {</div><div class='add'>+			reg = &lt;0x0 0x908c0000 0x0 0x1000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		reserved_mem: reserved@908f0000 {</div><div class='add'>+			reg = &lt;0x0 0x908f0000 0x0 0xe000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		secdata_apss_mem: secdata-apss@908fe000 {</div><div class='add'>+			reg = &lt;0x0 0x908fe000 0x0 0x2000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smem_mem: smem@90900000 {</div><div class='add'>+			compatible = "qcom,smem";</div><div class='add'>+			reg = &lt;0x0 0x90900000 0x0 0x200000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+			hwlocks = &lt;&amp;tcsr_mutex 3&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tz_sail_mailbox_mem: tz-sail-mailbox@90c00000 {</div><div class='add'>+			reg = &lt;0x0 0x90c00000 0x0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sail_mailbox_mem: sail-ss@90d00000 {</div><div class='add'>+			reg = &lt;0x0 0x90d00000 0x0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sail_ota_mem: sail-ss@90e00000 {</div><div class='add'>+			reg = &lt;0x0 0x90e00000 0x0 0x300000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gunyah_md_mem: gunyah-md@91a80000 {</div><div class='add'>+			reg = &lt;0x0 0x91a80000 0x0 0x80000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aoss_backup_mem: aoss-backup@91b00000 {</div><div class='add'>+			reg = &lt;0x0 0x91b00000 0x0 0x40000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpucp_backup_mem: cpucp-backup@91b40000 {</div><div class='add'>+			reg = &lt;0x0 0x91b40000 0x0 0x40000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tz_config_backup_mem: tz-config-backup@91b80000 {</div><div class='add'>+			reg = &lt;0x0 0x91b80000 0x0 0x10000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ddr_training_data_mem: ddr-training-data@91b90000 {</div><div class='add'>+			reg = &lt;0x0 0x91b90000 0x0 0x10000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cdt_data_backup_mem: cdt-data-backup@91ba0000 {</div><div class='add'>+			reg = &lt;0x0 0x91ba0000 0x0 0x1000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		lpass_machine_learning_mem: lpass-machine-learning@93b00000 {</div><div class='add'>+			reg = &lt;0x0 0x93b00000 0x0 0xf00000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@94a00000 {</div><div class='add'>+			reg = &lt;0x0 0x94a00000 0x0 0x800000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pil_camera_mem: pil-camera@95200000 {</div><div class='add'>+			reg = &lt;0x0 0x95200000 0x0 0x700000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pil_adsp_mem: pil-adsp@95900000 {</div><div class='add'>+			reg = &lt;0x0 0x95900000 0x0 0x1e00000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		q6_adsp_dtb_mem: q6-adsp-dtb@97700000 {</div><div class='add'>+			reg = &lt;0x0 0x97700000 0x0 0x80000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		q6_gdsp0_dtb_mem: q6-gdsp0-dtb@97780000 {</div><div class='add'>+			reg = &lt;0x0 0x97780000 0x0 0x80000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pil_gdsp0_mem: pil-gdsp0@97800000 {</div><div class='add'>+			reg = &lt;0x0 0x97800000 0x0 0x1e00000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pil_gdsp1_mem: pil-gdsp1@99600000 {</div><div class='add'>+			reg = &lt;0x0 0x99600000 0x0 0x1e00000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		q6_gdsp1_dtb_mem: q6-gdsp1-dtb@9b400000 {</div><div class='add'>+			reg = &lt;0x0 0x9b400000 0x0 0x80000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		q6_cdsp0_dtb_mem: q6-cdsp0-dtb@9b480000 {</div><div class='add'>+			reg = &lt;0x0 0x9b480000 0x0 0x80000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pil_cdsp0_mem: pil-cdsp0@9b500000 {</div><div class='add'>+			reg = &lt;0x0 0x9b500000 0x0 0x1e00000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pil_gpu_mem: pil-gpu@9d300000 {</div><div class='add'>+			reg = &lt;0x0 0x9d300000 0x0 0x2000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		q6_cdsp1_dtb_mem: q6-cdsp1-dtb@9d380000 {</div><div class='add'>+			reg = &lt;0x0 0x9d380000 0x0 0x80000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pil_cdsp1_mem: pil-cdsp1@9d400000 {</div><div class='add'>+			reg = &lt;0x0 0x9d400000 0x0 0x1e00000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pil_cvp_mem: pil-cvp@9f200000 {</div><div class='add'>+			reg = &lt;0x0 0x9f200000 0x0 0x700000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pil_video_mem: pil-video@9f900000 {</div><div class='add'>+			reg = &lt;0x0 0x9f900000 0x0 0x1000000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		firmware_mem: firmware-region@b0000000 {</div><div class='add'>+			reg = &lt;0x0 0xb0000000 0x0 0x800000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		scmi_mem: scmi-region@d0000000 {</div><div class='add'>+			reg = &lt;0x0 0xd0000000 0x0 0x40000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		firmware_logs_mem: firmware-logs@d0040000 {</div><div class='add'>+			reg = &lt;0x0 0xd0040000 0x0 0x10000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		firmware_audio_mem: firmware-audio@d0050000 {</div><div class='add'>+			reg = &lt;0x0 0xd0050000 0x0 0x4000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		firmware_reserved_mem: firmware-reserved@d0054000 {</div><div class='add'>+			reg = &lt;0x0 0xd0054000 0x0 0x9c000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		firmware_quantum_test_mem: firmware-quantum-test@d00f0000 {</div><div class='add'>+			reg = &lt;0x0 0xd00f0000 0x0 0x10000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tags_mem: tags@d0100000 {</div><div class='add'>+			reg = &lt;0x0 0xd0100000 0x0 0x1200000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qtee_mem: qtee@d1300000 {</div><div class='add'>+			reg = &lt;0x0 0xd1300000 0x0 0x500000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		deepsleep_backup_mem: deepsleep-backup@d1800000 {</div><div class='add'>+			reg = &lt;0x0 0xd1800000 0x0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		trusted_apps_mem: trusted-apps@d1900000 {</div><div class='add'>+			reg = &lt;0x0 0xd1900000 0x0 0x1c00000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tz_stat_mem: tz-stat@db100000 {</div><div class='add'>+			reg = &lt;0x0 0xdb100000 0x0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpucp_fw_mem: cpucp-fw@db200000 {</div><div class='add'>+			reg = &lt;0x0 0xdb200000 0x0 0x100000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	smp2p-adsp {</div><div class='add'>+		compatible = "qcom,smp2p";</div><div class='add'>+		qcom,smem = &lt;443&gt;, &lt;429&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;ipcc IPCC_CLIENT_LPASS</div><div class='add'>+					     IPCC_MPROC_SIGNAL_SMP2P</div><div class='add'>+					     IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+		mboxes = &lt;&amp;ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P&gt;;</div><div class='add'>+</div><div class='add'>+		qcom,local-pid = &lt;0&gt;;</div><div class='add'>+		qcom,remote-pid = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		smp2p_adsp_out: master-kernel {</div><div class='add'>+			qcom,entry-name = "master-kernel";</div><div class='add'>+			#qcom,smem-state-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smp2p_adsp_in: slave-kernel {</div><div class='add'>+			qcom,entry-name = "slave-kernel";</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	smp2p-cdsp0 {</div><div class='add'>+		compatible = "qcom,smp2p";</div><div class='add'>+		qcom,smem = &lt;94&gt;, &lt;432&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;ipcc IPCC_CLIENT_CDSP</div><div class='add'>+					     IPCC_MPROC_SIGNAL_SMP2P</div><div class='add'>+					     IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+		mboxes = &lt;&amp;ipcc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P&gt;;</div><div class='add'>+</div><div class='add'>+		qcom,local-pid = &lt;0&gt;;</div><div class='add'>+		qcom,remote-pid = &lt;5&gt;;</div><div class='add'>+</div><div class='add'>+		smp2p_cdsp0_out: master-kernel {</div><div class='add'>+			qcom,entry-name = "master-kernel";</div><div class='add'>+			#qcom,smem-state-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smp2p_cdsp0_in: slave-kernel {</div><div class='add'>+			qcom,entry-name = "slave-kernel";</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	smp2p-cdsp1 {</div><div class='add'>+		compatible = "qcom,smp2p";</div><div class='add'>+		qcom,smem = &lt;617&gt;, &lt;616&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;ipcc IPCC_CLIENT_NSP1</div><div class='add'>+					     IPCC_MPROC_SIGNAL_SMP2P</div><div class='add'>+					     IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+		mboxes = &lt;&amp;ipcc IPCC_CLIENT_NSP1 IPCC_MPROC_SIGNAL_SMP2P&gt;;</div><div class='add'>+</div><div class='add'>+		qcom,local-pid = &lt;0&gt;;</div><div class='add'>+		qcom,remote-pid = &lt;12&gt;;</div><div class='add'>+</div><div class='add'>+		smp2p_cdsp1_out: master-kernel {</div><div class='add'>+			qcom,entry-name = "master-kernel";</div><div class='add'>+			#qcom,smem-state-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smp2p_cdsp1_in: slave-kernel {</div><div class='add'>+			qcom,entry-name = "slave-kernel";</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	smp2p-gpdsp0 {</div><div class='add'>+		compatible = "qcom,smp2p";</div><div class='add'>+		qcom,smem = &lt;617&gt;, &lt;616&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;ipcc IPCC_CLIENT_GPDSP0</div><div class='add'>+					     IPCC_MPROC_SIGNAL_SMP2P</div><div class='add'>+					     IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+		mboxes = &lt;&amp;ipcc IPCC_CLIENT_GPDSP0 IPCC_MPROC_SIGNAL_SMP2P&gt;;</div><div class='add'>+</div><div class='add'>+		qcom,local-pid = &lt;0&gt;;</div><div class='add'>+		qcom,remote-pid = &lt;17&gt;;</div><div class='add'>+</div><div class='add'>+		smp2p_gpdsp0_out: master-kernel {</div><div class='add'>+			qcom,entry-name = "master-kernel";</div><div class='add'>+			#qcom,smem-state-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smp2p_gpdsp0_in: slave-kernel {</div><div class='add'>+			qcom,entry-name = "slave-kernel";</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	smp2p-gpdsp1 {</div><div class='add'>+		compatible = "qcom,smp2p";</div><div class='add'>+		qcom,smem = &lt;617&gt;, &lt;616&gt;;</div><div class='add'>+		interrupts-extended = &lt;&amp;ipcc IPCC_CLIENT_GPDSP1</div><div class='add'>+					     IPCC_MPROC_SIGNAL_SMP2P</div><div class='add'>+					     IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+		mboxes = &lt;&amp;ipcc IPCC_CLIENT_GPDSP1 IPCC_MPROC_SIGNAL_SMP2P&gt;;</div><div class='add'>+</div><div class='add'>+		qcom,local-pid = &lt;0&gt;;</div><div class='add'>+		qcom,remote-pid = &lt;18&gt;;</div><div class='add'>+</div><div class='add'>+		smp2p_gpdsp1_out: master-kernel {</div><div class='add'>+			qcom,entry-name = "master-kernel";</div><div class='add'>+			#qcom,smem-state-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smp2p_gpdsp1_in: slave-kernel {</div><div class='add'>+			qcom,entry-name = "slave-kernel";</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc: soc@0 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges = &lt;0 0 0 0 0x10 0&gt;;</div><div class='add'>+</div><div class='add'>+		gcc: clock-controller@100000 {</div><div class='add'>+			compatible = "qcom,sa8775p-gcc";</div><div class='add'>+			reg = &lt;0x0 0x00100000 0x0 0xc7018&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;,</div><div class='add'>+				 &lt;&amp;sleep_clk&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;&amp;usb_0_qmpphy&gt;,</div><div class='add'>+				 &lt;&amp;usb_1_qmpphy&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;&amp;pcie0_phy&gt;,</div><div class='add'>+				 &lt;&amp;pcie1_phy&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ipcc: mailbox@408000 {</div><div class='add'>+			compatible = "qcom,sa8775p-ipcc", "qcom,ipcc";</div><div class='add'>+			reg = &lt;0x0 0x00408000 0x0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			#mbox-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpi_dma2: dma-controller@800000  {</div><div class='add'>+			compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma";</div><div class='add'>+			reg = &lt;0x0 0x00800000 0x0 0x60000&gt;;</div><div class='add'>+			#dma-cells = &lt;3&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			dma-channels = &lt;12&gt;;</div><div class='add'>+			dma-channel-mask = &lt;0xfff&gt;;</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x5b6 0x0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qupv3_id_2: geniqup@8c0000 {</div><div class='add'>+			compatible = "qcom,geni-se-qup";</div><div class='add'>+			reg = &lt;0x0 0x008c0000 0x0 0x6000&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_QUPV3_WRAP_2_M_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_QUPV3_WRAP_2_S_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "m-ahb", "s-ahb";</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x5a3 0x0&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			i2c14: i2c@880000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0x0 0x880000 0x0 0x4000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP2_S0_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c14_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma2 0 0 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma2 1 0 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi14: spi@880000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0x0 0x880000 0x0 0x4000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP2_S0_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi14_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma2 0 0 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma2 1 0 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart14: serial@880000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0x0 0x00880000 0x0 0x4000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP2_S0_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart14_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c15: i2c@884000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0x0 0x884000 0x0 0x4000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP2_S1_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c15_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma2 0 1 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma2 1 1 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi15: spi@884000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0x0 0x884000 0x0 0x4000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP2_S1_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi15_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma2 0 1 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma2 1 1 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart15: serial@884000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0x0 0x00884000 0x0 0x4000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP2_S1_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart15_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c16: i2c@888000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0x0 0x888000 0x0 0x4000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP2_S2_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c16_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma2 0 2 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma2 1 2 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi16: spi@888000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0x0 0x00888000 0x0 0x4000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP2_S2_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi16_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma2 0 2 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma2 1 2 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart16: serial@888000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0x0 0x00888000 0x0 0x4000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP2_S2_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart16_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c17: i2c@88c000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0x0 0x88c000 0x0 0x4000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP2_S3_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c17_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma2 0 3 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma2 1 3 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi17: spi@88c000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0x0 0x88c000 0x0 0x4000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP2_S3_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi17_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma2 0 3 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma2 1 3 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart17: serial@88c000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0x0 0x0088c000 0x0 0x4000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP2_S3_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart17_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c18: i2c@890000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0x0 0x00890000 0x0 0x4000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP2_S4_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c18_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma2 0 4 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma2 1 4 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi18: spi@890000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0x0 0x890000 0x0 0x4000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP2_S4_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi18_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma2 0 4 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma2 1 4 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart18: serial@890000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0x0 0x00890000 0x0 0x4000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP2_S4_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart18_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c19: i2c@894000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0x0 0x894000 0x0 0x4000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP2_S5_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c19_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma2 0 5 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma2 1 5 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi19: spi@894000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0x0 0x894000 0x0 0x4000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP2_S5_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi19_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma2 0 5 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma2 1 5 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart19: serial@894000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0x0 0x00894000 0x0 0x4000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP2_S5_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart19_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c20: i2c@898000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0x0 0x898000 0x0 0x4000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP2_S6_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c20_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma2 0 6 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma2 1 6 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi20: spi@898000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0x0 0x898000 0x0 0x4000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP2_S6_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi20_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma2 0 6 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma2 1 6 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart20: serial@898000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0x0 0x00898000 0x0 0x4000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP2_S6_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart20_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpi_dma0: dma-controller@900000  {</div><div class='add'>+			compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma";</div><div class='add'>+			reg = &lt;0x0 0x00900000 0x0 0x60000&gt;;</div><div class='add'>+			#dma-cells = &lt;3&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			dma-channels = &lt;12&gt;;</div><div class='add'>+			dma-channel-mask = &lt;0xfff&gt;;</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x416 0x0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qupv3_id_0: geniqup@9c0000 {</div><div class='add'>+			compatible = "qcom,geni-se-qup";</div><div class='add'>+			reg = &lt;0x0 0x9c0000 0x0 0x6000&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clock-names = "m-ahb", "s-ahb";</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_QUPV3_WRAP_0_M_AHB_CLK&gt;,</div><div class='add'>+				&lt;&amp;gcc GCC_QUPV3_WRAP_0_S_AHB_CLK&gt;;</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x403 0x0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			i2c0: i2c@980000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0x0 0x980000 0x0 0x4000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S0_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c0_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 0 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 0 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi0: spi@980000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0x0 0x980000 0x0 0x4000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S0_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi0_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 0 QCOM_GPI_SPI&gt;,</div><div class='add'>+				     &lt;&amp;gpi_dma0 1 0 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart0: serial@980000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0x0 0x980000 0x0 0x4000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S0_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart0_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c1: i2c@984000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0x0 0x984000 0x0 0x4000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S1_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c1_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 1 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 1 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi1: spi@984000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0x0 0x984000 0x0 0x4000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S1_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi1_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 1 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 1 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart1: serial@984000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0x0 0x984000 0x0 0x4000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S1_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart1_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c2: i2c@988000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0x0 0x988000 0x0 0x4000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S2_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c2_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 2 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 2 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi2: spi@988000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0x0 0x988000 0x0 0x4000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S2_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi2_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 2 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 2 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart2: serial@988000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0x0 0x988000 0x0 0x4000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S2_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart2_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c3: i2c@98c000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0x0 0x98c000 0x0 0x4000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S3_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c3_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 3 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 3 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi3: spi@98c000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0x0 0x98c000 0x0 0x4000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S3_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi3_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 3 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 3 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart3: serial@98c000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0x0 0x98c000 0x0 0x4000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S3_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart3_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c4: i2c@990000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0x0 0x990000 0x0 0x4000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S4_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c4_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 4 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 4 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi4: spi@990000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0x0 0x990000 0x0 0x4000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S4_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi4_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 4 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 4 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart4: serial@990000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0x0 0x990000 0x0 0x4000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S4_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart4_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c5: i2c@994000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0x0 0x994000 0x0 0x4000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S5_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c5_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 5 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 5 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi5: spi@994000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0x0 0x994000 0x0 0x4000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S5_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi5_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 5 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 5 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart5: serial@994000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0x0 0x994000 0x0 0x4000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S5_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart5_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpi_dma1: dma-controller@a00000  {</div><div class='add'>+			compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma";</div><div class='add'>+			reg = &lt;0x0 0x00a00000 0x0 0x60000&gt;;</div><div class='add'>+			#dma-cells = &lt;3&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x456 0x0&gt;;</div><div class='add'>+			dma-channels = &lt;12&gt;;</div><div class='add'>+			dma-channel-mask = &lt;0xfff&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qupv3_id_1: geniqup@ac0000 {</div><div class='add'>+			compatible = "qcom,geni-se-qup";</div><div class='add'>+			reg = &lt;0x0 0x00ac0000 0x0 0x6000&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clock-names = "m-ahb", "s-ahb";</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_QUPV3_WRAP_1_M_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_QUPV3_WRAP_1_S_AHB_CLK&gt;;</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x443 0x0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			i2c7: i2c@a80000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0x0 0xa80000 0x0 0x4000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S0_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c7_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 0 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 0 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi7: spi@a80000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0x0 0xa80000 0x0 0x4000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S0_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi7_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 0 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 0 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart7: serial@a80000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0x0 0x00a80000 0x0 0x4000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S0_CLK&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart7_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table_100mhz&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c8: i2c@a84000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0x0 0xa84000 0x0 0x4000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S1_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c8_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 1 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 1 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi8: spi@a84000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0x0 0xa84000 0x0 0x4000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S1_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi8_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 1 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 1 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart8: serial@a84000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0x0 0x00a84000 0x0 0x4000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S1_CLK&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart8_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table_100mhz&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c9: i2c@a88000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0x0 0xa88000 0x0 0x4000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S2_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c9_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 2 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 2 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi9: spi@a88000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0x0 0xa88000 0x0 0x4000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S2_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi9_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 2 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 2 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart9: serial@a88000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0x0 0xa88000 0x0 0x4000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S2_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart9_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c10: i2c@a8c000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0x0 0xa8c000 0x0 0x4000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S3_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c10_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 3 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 3 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi10: spi@a8c000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0x0 0xa8c000 0x0 0x4000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S3_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi10_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 3 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 3 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart10: serial@a8c000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0x0 0x00a8c000 0x0 0x4000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S3_CLK&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart10_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 0</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 0&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC 0</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 0&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table_100mhz&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c11: i2c@a90000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0x0 0xa90000 0x0 0x4000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S4_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c11_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 4 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 4 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi11: spi@a90000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0x0 0xa90000 0x0 0x4000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S4_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi11_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 4 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 4 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart11: serial@a90000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0x0 0x00a90000 0x0 0x4000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S4_CLK&gt;;</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart11_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table_100mhz&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c12: i2c@a94000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0x0 0xa94000 0x0 0x4000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S5_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c12_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 5 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 5 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi12: spi@a94000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0x0 0xa94000 0x0 0x4000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S5_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi12_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 5 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 5 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart12: serial@a94000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0x0 0x00a94000 0x0 0x4000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S5_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart12_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c13: i2c@a98000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0x0 0xa98000 0x0 0x4000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S6_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c13_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 6 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 6 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpi_dma3: dma-controller@b00000  {</div><div class='add'>+			compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma";</div><div class='add'>+			reg = &lt;0x0 0x00b00000 0x0 0x58000&gt;;</div><div class='add'>+			#dma-cells = &lt;3&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x056 0x0&gt;;</div><div class='add'>+			dma-channels = &lt;4&gt;;</div><div class='add'>+			dma-channel-mask = &lt;0xf&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qupv3_id_3: geniqup@bc0000 {</div><div class='add'>+			compatible = "qcom,geni-se-qup";</div><div class='add'>+			reg = &lt;0x0 0xbc0000 0x0 0x6000&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clock-names = "m-ahb", "s-ahb";</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_QUPV3_WRAP_3_M_AHB_CLK&gt;,</div><div class='add'>+				&lt;&amp;gcc GCC_QUPV3_WRAP_3_S_AHB_CLK&gt;;</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x43 0x0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			i2c21: i2c@b80000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0x0 0xb80000 0x0 0x4000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP3_S0_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c21_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						&amp;clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+					   &lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						&amp;config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+					   &lt;&amp;aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						&amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+							 "qup-config",</div><div class='add'>+							 "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma3 0 0 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma3 1 0 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi21: spi@b80000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0x0 0xb80000 0x0 0x4000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP3_S0_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi21_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						&amp;clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+					   &lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						&amp;config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+					   &lt;&amp;aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						&amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+							 "qup-config",</div><div class='add'>+							 "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma3 0 0 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma3 1 0 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart21: serial@b80000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0x0 0x00b80000 0x0 0x4000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP3_S0_CLK&gt;;</div><div class='add'>+				interconnect-names = "qup-core", "qup-config";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart21_default&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table_100mhz&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rng: rng@10d2000 {</div><div class='add'>+			compatible = "qcom,sa8775p-trng", "qcom,trng";</div><div class='add'>+			reg = &lt;0 0x010d2000 0 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ufs_mem_hc: ufshc@1d84000 {</div><div class='add'>+			compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0";</div><div class='add'>+			reg = &lt;0x0 0x01d84000 0x0 0x3000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			phys = &lt;&amp;ufs_mem_phy&gt;;</div><div class='add'>+			phy-names = "ufsphy";</div><div class='add'>+			lanes-per-direction = &lt;2&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+			resets = &lt;&amp;gcc GCC_UFS_PHY_BCR&gt;;</div><div class='add'>+			reset-names = "rst";</div><div class='add'>+			power-domains = &lt;&amp;gcc UFS_PHY_GDSC&gt;;</div><div class='add'>+			required-opps = &lt;&amp;rpmhpd_opp_nom&gt;;</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x100 0x0&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_UFS_PHY_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_AGGRE_UFS_PHY_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_UFS_PHY_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_UFS_PHY_UNIPRO_CORE_CLK&gt;,</div><div class='add'>+				 &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK&gt;;</div><div class='add'>+			clock-names = "core_clk",</div><div class='add'>+				      "bus_aggr_clk",</div><div class='add'>+				      "iface_clk",</div><div class='add'>+				      "core_clk_unipro",</div><div class='add'>+				      "ref_clk",</div><div class='add'>+				      "tx_lane0_sync_clk",</div><div class='add'>+				      "rx_lane0_sync_clk",</div><div class='add'>+				      "rx_lane1_sync_clk";</div><div class='add'>+			freq-table-hz = &lt;75000000 300000000&gt;,</div><div class='add'>+					&lt;0 0&gt;,</div><div class='add'>+					&lt;0 0&gt;,</div><div class='add'>+					&lt;75000000 300000000&gt;,</div><div class='add'>+					&lt;0 0&gt;,</div><div class='add'>+					&lt;0 0&gt;,</div><div class='add'>+					&lt;0 0&gt;,</div><div class='add'>+					&lt;0 0&gt;;</div><div class='add'>+			qcom,ice = &lt;&amp;ice&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ufs_mem_phy: phy@1d87000 {</div><div class='add'>+			compatible = "qcom,sa8775p-qmp-ufs-phy";</div><div class='add'>+			reg = &lt;0x0 0x01d87000 0x0 0xe10&gt;;</div><div class='add'>+			/*</div><div class='add'>+			 * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It</div><div class='add'>+			 * enables the CXO clock to eDP *and* UFS PHY.</div><div class='add'>+			 */</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_UFS_PHY_PHY_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_EDP_REF_CLKREF_EN&gt;;</div><div class='add'>+			clock-names = "ref", "ref_aux", "qref";</div><div class='add'>+			power-domains = &lt;&amp;gcc UFS_PHY_GDSC&gt;;</div><div class='add'>+			resets = &lt;&amp;ufs_mem_hc 0&gt;;</div><div class='add'>+			reset-names = "ufsphy";</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ice: crypto@1d88000 {</div><div class='add'>+			compatible = "qcom,sa8775p-inline-crypto-engine",</div><div class='add'>+				     "qcom,inline-crypto-engine";</div><div class='add'>+			reg = &lt;0x0 0x01d88000 0x0 0x18000&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_UFS_PHY_ICE_CORE_CLK&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cryptobam: dma-controller@1dc4000 {</div><div class='add'>+			compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";</div><div class='add'>+			reg = &lt;0x0 0x01dc4000 0x0 0x28000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+			qcom,ee = &lt;0&gt;;</div><div class='add'>+			qcom,num-ees = &lt;4&gt;;</div><div class='add'>+			num-channels = &lt;20&gt;;</div><div class='add'>+			qcom,controlled-remotely;</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x480 0x00&gt;,</div><div class='add'>+				 &lt;&amp;apps_smmu 0x481 0x00&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ctcu@4001000 {</div><div class='add'>+			compatible = "qcom,sa8775p-ctcu";</div><div class='add'>+			reg = &lt;0x0 0x04001000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					ctcu_in0: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;etr0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					ctcu_in1: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;etr1_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		stm: stm@4002000 {</div><div class='add'>+			compatible = "arm,coresight-stm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x4002000 0x0 0x1000&gt;,</div><div class='add'>+				  &lt;0x0 0x16280000 0x0 0x180000&gt;;</div><div class='add'>+			reg-names = "stm-base", "stm-stimulus-base";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					stm_out: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;funnel0_in7&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@4003000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x4003000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,cmb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,cmb-msrs-num = &lt;32&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					qdss_tpdm0_out: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;qdss_tpda_in0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpda@4004000 {</div><div class='add'>+			compatible = "qcom,coresight-tpda", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x4004000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					qdss_tpda_out: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;funnel0_in6&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					qdss_tpda_in0: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;qdss_tpdm0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					qdss_tpda_in1: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;qdss_tpdm1_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@400f000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x400f000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,cmb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,cmb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					qdss_tpdm1_out: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;qdss_tpda_in1&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		funnel@4041000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x4041000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					funnel0_out: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;qdss_funnel_in0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@6 {</div><div class='add'>+					reg = &lt;6&gt;;</div><div class='add'>+					funnel0_in6: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;qdss_tpda_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@7 {</div><div class='add'>+					reg = &lt;7&gt;;</div><div class='add'>+					funnel0_in7: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;stm_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		funnel@4042000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x4042000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					funnel1_out: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;qdss_funnel_in1&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@4 {</div><div class='add'>+					reg = &lt;4&gt;;</div><div class='add'>+					funnel1_in4: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;apss_funnel1_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		funnel@4045000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x4045000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					qdss_funnel_out: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;aoss_funnel_in7&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					qdss_funnel_in0: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;funnel0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					qdss_funnel_in1: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;funnel1_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		replicator@4046000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x04046000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				port {</div><div class='add'>+					qdss_rep_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;swao_rep_out0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					qdss_rep_out0: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;etr_rep_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tmc_etr: tmc@4048000 {</div><div class='add'>+			compatible = "arm,coresight-tmc", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x04048000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x04c0 0x00&gt;;</div><div class='add'>+</div><div class='add'>+			arm,scatter-gather;</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				port {</div><div class='add'>+					etr0_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;etr_rep_out0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					etr0_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ctcu_in0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		replicator@404e000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x0404e000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				port {</div><div class='add'>+					etr_rep_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;qdss_rep_out0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					etr_rep_out0: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;etr0_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					etr_rep_out1: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;etr1_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tmc_etr1: tmc@404f000 {</div><div class='add'>+			compatible = "arm,coresight-tmc", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x0404f000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x04a0 0x40&gt;;</div><div class='add'>+</div><div class='add'>+			arm,scatter-gather;</div><div class='add'>+			arm,buffer-size = &lt;0x400000&gt;;</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				port {</div><div class='add'>+					etr1_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;etr_rep_out1&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					etr1_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ctcu_in1&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		funnel@4b04000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x4b04000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					aoss_funnel_out: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;etf0_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@6 {</div><div class='add'>+					reg = &lt;6&gt;;</div><div class='add'>+					aoss_funnel_in6: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;aoss_tpda_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@7 {</div><div class='add'>+					reg = &lt;7&gt;;</div><div class='add'>+					aoss_funnel_in7: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;qdss_funnel_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tmc_etf: tmc@4b05000 {</div><div class='add'>+			compatible = "arm,coresight-tmc", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x4b05000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					etf0_out: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;swao_rep_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				port {</div><div class='add'>+					etf0_in: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;aoss_funnel_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		replicator@4b06000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x4b06000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					swao_rep_out0: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;qdss_rep_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					swao_rep_out1: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;eud_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				port {</div><div class='add'>+					swao_rep_in: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;etf0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpda@4b08000 {</div><div class='add'>+			compatible = "qcom,coresight-tpda", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x4b08000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					aoss_tpda_out: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;aoss_funnel_in6&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					aoss_tpda_in0: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;aoss_tpdm0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					aoss_tpda_in1: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;aoss_tpdm1_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@2 {</div><div class='add'>+					reg = &lt;2&gt;;</div><div class='add'>+					aoss_tpda_in2: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;aoss_tpdm2_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@3 {</div><div class='add'>+					reg = &lt;3&gt;;</div><div class='add'>+					aoss_tpda_in3: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;aoss_tpdm3_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@4 {</div><div class='add'>+					reg = &lt;4&gt;;</div><div class='add'>+					aoss_tpda_in4: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;aoss_tpdm4_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@4b09000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x4b09000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,cmb-element-bits = &lt;64&gt;;</div><div class='add'>+			qcom,cmb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					aoss_tpdm0_out: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;aoss_tpda_in0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@4b0a000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x4b0a000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,cmb-element-bits = &lt;64&gt;;</div><div class='add'>+			qcom,cmb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					aoss_tpdm1_out: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;aoss_tpda_in1&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@4b0b000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x4b0b000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,cmb-element-bits = &lt;64&gt;;</div><div class='add'>+			qcom,cmb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					aoss_tpdm2_out: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;aoss_tpda_in2&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@4b0c000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x4b0c000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,cmb-element-bits = &lt;64&gt;;</div><div class='add'>+			qcom,cmb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					aoss_tpdm3_out: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;aoss_tpda_in3&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@4b0d000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x4b0d000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,dsb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,dsb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					aoss_tpdm4_out: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;aoss_tpda_in4&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aoss_cti: cti@4b13000 {</div><div class='add'>+			compatible = "arm,coresight-cti", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x4b13000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		etm@6040000 {</div><div class='add'>+			compatible = "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x6040000 0x0 0x1000&gt;;</div><div class='add'>+			cpu = &lt;&amp;cpu0&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			arm,coresight-loses-context-with-cpu;</div><div class='add'>+			qcom,skip-power-up;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					etm0_out: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;apss_funnel0_in0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		etm@6140000 {</div><div class='add'>+			compatible = "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x6140000 0x0 0x1000&gt;;</div><div class='add'>+			cpu = &lt;&amp;cpu1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			arm,coresight-loses-context-with-cpu;</div><div class='add'>+			qcom,skip-power-up;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					etm1_out: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;apss_funnel0_in1&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		etm@6240000 {</div><div class='add'>+			compatible = "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x6240000 0x0 0x1000&gt;;</div><div class='add'>+			cpu = &lt;&amp;cpu2&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			arm,coresight-loses-context-with-cpu;</div><div class='add'>+			qcom,skip-power-up;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					etm2_out: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;apss_funnel0_in2&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		etm@6340000 {</div><div class='add'>+			compatible = "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x6340000 0x0 0x1000&gt;;</div><div class='add'>+			cpu = &lt;&amp;cpu3&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			arm,coresight-loses-context-with-cpu;</div><div class='add'>+			qcom,skip-power-up;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					etm3_out: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;apss_funnel0_in3&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		etm@6440000 {</div><div class='add'>+			compatible = "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x6440000 0x0 0x1000&gt;;</div><div class='add'>+			cpu = &lt;&amp;cpu4&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			arm,coresight-loses-context-with-cpu;</div><div class='add'>+			qcom,skip-power-up;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					etm4_out: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;apss_funnel0_in4&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		etm@6540000 {</div><div class='add'>+			compatible = "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x6540000 0x0 0x1000&gt;;</div><div class='add'>+			cpu = &lt;&amp;cpu5&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			arm,coresight-loses-context-with-cpu;</div><div class='add'>+			qcom,skip-power-up;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					etm5_out: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;apss_funnel0_in5&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		etm@6640000 {</div><div class='add'>+			compatible = "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x6640000 0x0 0x1000&gt;;</div><div class='add'>+			cpu = &lt;&amp;cpu6&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			arm,coresight-loses-context-with-cpu;</div><div class='add'>+			qcom,skip-power-up;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					etm6_out: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;apss_funnel0_in6&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		etm@6740000 {</div><div class='add'>+			compatible = "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x6740000 0x0 0x1000&gt;;</div><div class='add'>+			cpu = &lt;&amp;cpu7&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+			arm,coresight-loses-context-with-cpu;</div><div class='add'>+			qcom,skip-power-up;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					etm7_out: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;apss_funnel0_in7&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		funnel@6800000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x6800000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					apss_funnel0_out: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;apss_funnel1_in0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					apss_funnel0_in0: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;etm0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					apss_funnel0_in1: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;etm1_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@2 {</div><div class='add'>+					reg = &lt;2&gt;;</div><div class='add'>+					apss_funnel0_in2: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;etm2_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@3 {</div><div class='add'>+					reg = &lt;3&gt;;</div><div class='add'>+					apss_funnel0_in3: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;etm3_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@4 {</div><div class='add'>+					reg = &lt;4&gt;;</div><div class='add'>+					apss_funnel0_in4: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;etm4_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@5 {</div><div class='add'>+					reg = &lt;5&gt;;</div><div class='add'>+					apss_funnel0_in5: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;etm5_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@6 {</div><div class='add'>+					reg = &lt;6&gt;;</div><div class='add'>+					apss_funnel0_in6: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;etm6_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@7 {</div><div class='add'>+					reg = &lt;7&gt;;</div><div class='add'>+					apss_funnel0_in7: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;etm7_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		funnel@6810000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x6810000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					apss_funnel1_out: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;funnel1_in4&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					apss_funnel1_in0: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;apss_funnel0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@3 {</div><div class='add'>+					reg = &lt;3&gt;;</div><div class='add'>+					apss_funnel1_in3: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;apss_tpda_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@6860000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x6860000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,cmb-element-bits = &lt;64&gt;;</div><div class='add'>+			qcom,cmb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					apss_tpdm3_out: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;apss_tpda_in3&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@6861000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x6861000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,dsb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,dsb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					apss_tpdm4_out: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;apss_tpda_in4&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpda@6863000 {</div><div class='add'>+			compatible = "qcom,coresight-tpda", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x6863000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					apss_tpda_out: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;apss_funnel1_in3&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+					apss_tpda_in0: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;apss_tpdm0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+					apss_tpda_in1: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;apss_tpdm1_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@2 {</div><div class='add'>+					reg = &lt;2&gt;;</div><div class='add'>+					apss_tpda_in2: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;apss_tpdm2_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@3 {</div><div class='add'>+					reg = &lt;3&gt;;</div><div class='add'>+					apss_tpda_in3: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;apss_tpdm3_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@4 {</div><div class='add'>+					reg = &lt;4&gt;;</div><div class='add'>+					apss_tpda_in4: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;apss_tpdm4_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@68a0000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x68a0000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,cmb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,cmb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					apss_tpdm0_out: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;apss_tpda_in0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@68b0000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x68b0000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,cmb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,cmb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					apss_tpdm1_out: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;apss_tpda_in1&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@68c0000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x68c0000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,dsb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,dsb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					apss_tpdm2_out: endpoint {</div><div class='add'>+						remote-endpoint =</div><div class='add'>+						&lt;&amp;apss_tpda_in2&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sdhc: mmc@87c4000 {</div><div class='add'>+			compatible = "qcom,sa8775p-sdhci", "qcom,sdhci-msm-v5";</div><div class='add'>+			reg = &lt;0x0 0x087c4000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "hc_irq",</div><div class='add'>+					  "pwr_irq";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_SDCC1_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_SDCC1_APPS_CLK&gt;;</div><div class='add'>+			clock-names = "iface",</div><div class='add'>+				      "core";</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;aggre1_noc MASTER_SDC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+					&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;config_noc SLAVE_SDC1 QCOM_ICC_TAG_ACTIVE_ONLY&gt;;</div><div class='add'>+			interconnect-names = "sdhc-ddr",</div><div class='add'>+					     "cpu-sdhc";</div><div class='add'>+</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x0 0x0&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+</div><div class='add'>+			operating-points-v2 = &lt;&amp;sdhc_opp_table&gt;;</div><div class='add'>+			power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;;</div><div class='add'>+			resets = &lt;&amp;gcc GCC_SDCC1_BCR&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,dll-config = &lt;0x0007642c&gt;;</div><div class='add'>+			qcom,ddr-config = &lt;0x80040868&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			sdhc_opp_table: opp-table {</div><div class='add'>+				compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+				opp-100000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;100000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;1800000 400000&gt;;</div><div class='add'>+					opp-avg-kBps = &lt;100000 0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-384000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;384000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_nom&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;5400000 1600000&gt;;</div><div class='add'>+					opp-avg-kBps = &lt;390000 0&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_0_hsphy: phy@88e4000 {</div><div class='add'>+			compatible = "qcom,sa8775p-usb-hs-phy",</div><div class='add'>+				     "qcom,usb-snps-hs-5nm-phy";</div><div class='add'>+			reg = &lt;0 0x088e4000 0 0x120&gt;;</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;;</div><div class='add'>+			clock-names = "ref";</div><div class='add'>+			resets = &lt;&amp;gcc GCC_USB2_PHY_PRIM_BCR&gt;;</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_1_hsphy: phy@88e6000 {</div><div class='add'>+			compatible = "qcom,sa8775p-usb-hs-phy",</div><div class='add'>+				     "qcom,usb-snps-hs-5nm-phy";</div><div class='add'>+			reg = &lt;0 0x088e6000 0 0x120&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_USB_CLKREF_EN&gt;;</div><div class='add'>+			clock-names = "ref";</div><div class='add'>+			resets = &lt;&amp;gcc GCC_USB2_PHY_SEC_BCR&gt;;</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_2_hsphy: phy@88e7000 {</div><div class='add'>+			compatible = "qcom,sa8775p-usb-hs-phy",</div><div class='add'>+				     "qcom,usb-snps-hs-5nm-phy";</div><div class='add'>+			reg = &lt;0 0x088e7000 0 0x120&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_USB_CLKREF_EN&gt;;</div><div class='add'>+			clock-names = "ref";</div><div class='add'>+			resets = &lt;&amp;gcc GCC_USB3_PHY_TERT_BCR&gt;;</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_0_qmpphy: phy@88e8000 {</div><div class='add'>+			compatible = "qcom,sa8775p-qmp-usb3-uni-phy";</div><div class='add'>+			reg = &lt;0 0x088e8000 0 0x2000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_USB3_PRIM_PHY_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB_CLKREF_EN&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB3_PRIM_PHY_PIPE_CLK&gt;;</div><div class='add'>+			clock-names = "aux", "ref", "com_aux", "pipe";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_USB3_PHY_PRIM_BCR&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB3PHY_PHY_PRIM_BCR&gt;;</div><div class='add'>+			reset-names = "phy", "phy_phy";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;gcc USB30_PRIM_GDSC&gt;;</div><div class='add'>+</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-output-names = "usb3_prim_phy_pipe_clk_src";</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_1_qmpphy: phy@88ea000 {</div><div class='add'>+			compatible = "qcom,sa8775p-qmp-usb3-uni-phy";</div><div class='add'>+			reg = &lt;0 0x088ea000 0 0x2000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_USB3_SEC_PHY_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB_CLKREF_EN&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB3_SEC_PHY_COM_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB3_SEC_PHY_PIPE_CLK&gt;;</div><div class='add'>+			clock-names = "aux", "ref", "com_aux", "pipe";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_USB3_PHY_SEC_BCR&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB3PHY_PHY_SEC_BCR&gt;;</div><div class='add'>+			reset-names = "phy", "phy_phy";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;gcc USB30_SEC_GDSC&gt;;</div><div class='add'>+</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-output-names = "usb3_sec_phy_pipe_clk_src";</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		refgen: regulator@891c000 {</div><div class='add'>+			compatible = "qcom,sa8775p-refgen-regulator",</div><div class='add'>+				     "qcom,sm8250-refgen-regulator";</div><div class='add'>+			reg = &lt;0x0 0x0891c000 0x0 0x84&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_0: usb@a600000 {</div><div class='add'>+			compatible = "qcom,sa8775p-dwc3", "qcom,snps-dwc3";</div><div class='add'>+			reg = &lt;0 0x0a600000 0 0xfc100&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB30_PRIM_MASTER_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_AGGRE_USB3_PRIM_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB30_PRIM_SLEEP_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB30_PRIM_MOCK_UTMI_CLK&gt;;</div><div class='add'>+			clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";</div><div class='add'>+</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_USB30_PRIM_MOCK_UTMI_CLK&gt;,</div><div class='add'>+					  &lt;&amp;gcc GCC_USB30_PRIM_MASTER_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;19200000&gt;, &lt;200000000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts-extended = &lt;&amp;intc GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;pdc 14 IRQ_TYPE_EDGE_BOTH&gt;,</div><div class='add'>+					      &lt;&amp;pdc 15 IRQ_TYPE_EDGE_BOTH&gt;,</div><div class='add'>+					      &lt;&amp;pdc 12 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "dwc_usb3",</div><div class='add'>+					  "pwr_event",</div><div class='add'>+					  "hs_phy_irq",</div><div class='add'>+					  "dp_hs_phy_irq",</div><div class='add'>+					  "dm_hs_phy_irq",</div><div class='add'>+					  "ss_phy_irq";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;gcc USB30_PRIM_GDSC&gt;;</div><div class='add'>+			required-opps = &lt;&amp;rpmhpd_opp_nom&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_USB30_PRIM_BCR&gt;;</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;aggre1_noc MASTER_USB3_0 0 &amp;mc_virt SLAVE_EBI1 0&gt;,</div><div class='add'>+					&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;config_noc SLAVE_USB3_0 0&gt;;</div><div class='add'>+			interconnect-names = "usb-ddr", "apps-usb";</div><div class='add'>+</div><div class='add'>+			wakeup-source;</div><div class='add'>+</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x080 0x0&gt;;</div><div class='add'>+			phys = &lt;&amp;usb_0_hsphy&gt;, &lt;&amp;usb_0_qmpphy&gt;;</div><div class='add'>+			phy-names = "usb2-phy", "usb3-phy";</div><div class='add'>+			snps,dis-u1-entry-quirk;</div><div class='add'>+			snps,dis-u2-entry-quirk;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_1: usb@a800000 {</div><div class='add'>+			compatible = "qcom,sa8775p-dwc3", "qcom,snps-dwc3";</div><div class='add'>+			reg = &lt;0 0x0a800000 0 0xfc100&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB30_SEC_MASTER_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_AGGRE_USB3_SEC_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB30_SEC_SLEEP_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB30_SEC_MOCK_UTMI_CLK&gt;;</div><div class='add'>+			clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";</div><div class='add'>+</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_USB30_SEC_MOCK_UTMI_CLK&gt;,</div><div class='add'>+					  &lt;&amp;gcc GCC_USB30_SEC_MASTER_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;19200000&gt;, &lt;200000000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts-extended = &lt;&amp;intc GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;intc GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;pdc 8 IRQ_TYPE_EDGE_BOTH&gt;,</div><div class='add'>+					      &lt;&amp;pdc 7 IRQ_TYPE_EDGE_BOTH&gt;,</div><div class='add'>+					      &lt;&amp;pdc 13 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "dwc_usb3",</div><div class='add'>+					  "pwr_event",</div><div class='add'>+					  "hs_phy_irq",</div><div class='add'>+					  "dp_hs_phy_irq",</div><div class='add'>+					  "dm_hs_phy_irq",</div><div class='add'>+					  "ss_phy_irq";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;gcc USB30_SEC_GDSC&gt;;</div><div class='add'>+			required-opps = &lt;&amp;rpmhpd_opp_nom&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_USB30_SEC_BCR&gt;;</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;aggre1_noc MASTER_USB3_1 0 &amp;mc_virt SLAVE_EBI1 0&gt;,</div><div class='add'>+					&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;config_noc SLAVE_USB3_1 0&gt;;</div><div class='add'>+			interconnect-names = "usb-ddr", "apps-usb";</div><div class='add'>+</div><div class='add'>+			wakeup-source;</div><div class='add'>+</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x0a0 0x0&gt;;</div><div class='add'>+			phys = &lt;&amp;usb_1_hsphy&gt;, &lt;&amp;usb_1_qmpphy&gt;;</div><div class='add'>+			phy-names = "usb2-phy", "usb3-phy";</div><div class='add'>+			snps,dis-u1-entry-quirk;</div><div class='add'>+			snps,dis-u2-entry-quirk;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_2: usb@a400000 {</div><div class='add'>+			compatible = "qcom,sa8775p-dwc3", "qcom,snps-dwc3";</div><div class='add'>+			reg = &lt;0 0x0a400000 0 0xfc100&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB20_MASTER_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_AGGRE_USB2_PRIM_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB20_SLEEP_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB20_MOCK_UTMI_CLK&gt;;</div><div class='add'>+			clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";</div><div class='add'>+</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_USB20_MOCK_UTMI_CLK&gt;,</div><div class='add'>+					  &lt;&amp;gcc GCC_USB20_MASTER_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;19200000&gt;, &lt;200000000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts-extended = &lt;&amp;intc GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;pdc 10 IRQ_TYPE_EDGE_BOTH&gt;,</div><div class='add'>+					      &lt;&amp;pdc 9 IRQ_TYPE_EDGE_BOTH&gt;;</div><div class='add'>+			interrupt-names = "dwc_usb3",</div><div class='add'>+					  "pwr_event",</div><div class='add'>+					  "hs_phy_irq",</div><div class='add'>+					  "dp_hs_phy_irq",</div><div class='add'>+					  "dm_hs_phy_irq";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;gcc USB20_PRIM_GDSC&gt;;</div><div class='add'>+			required-opps = &lt;&amp;rpmhpd_opp_nom&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_USB20_PRIM_BCR&gt;;</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;aggre1_noc MASTER_USB2 0 &amp;mc_virt SLAVE_EBI1 0&gt;,</div><div class='add'>+					&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;config_noc SLAVE_USB2 0&gt;;</div><div class='add'>+			interconnect-names = "usb-ddr", "apps-usb";</div><div class='add'>+</div><div class='add'>+			qcom,select-utmi-as-pipe-clk;</div><div class='add'>+			wakeup-source;</div><div class='add'>+</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x020 0x0&gt;;</div><div class='add'>+			phys = &lt;&amp;usb_2_hsphy&gt;;</div><div class='add'>+			phy-names = "usb2-phy";</div><div class='add'>+			snps,dis-u1-entry-quirk;</div><div class='add'>+			snps,dis-u2-entry-quirk;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tcsr_mutex: hwlock@1f40000 {</div><div class='add'>+			compatible = "qcom,tcsr-mutex";</div><div class='add'>+			reg = &lt;0x0 0x01f40000 0x0 0x20000&gt;;</div><div class='add'>+			#hwlock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tcsr: syscon@1fc0000 {</div><div class='add'>+			compatible = "qcom,sa8775p-tcsr", "syscon";</div><div class='add'>+			reg = &lt;0x0 0x1fc0000 0x0 0x30000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpucc: clock-controller@3d90000 {</div><div class='add'>+			compatible = "qcom,sa8775p-gpucc";</div><div class='add'>+			reg = &lt;0x0 0x03d90000 0x0 0xa000&gt;;</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_GPU_GPLL0_CLK_SRC&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_GPU_GPLL0_DIV_CLK_SRC&gt;;</div><div class='add'>+			clock-names = "bi_tcxo",</div><div class='add'>+				      "gcc_gpu_gpll0_clk_src",</div><div class='add'>+				      "gcc_gpu_gpll0_div_clk_src";</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		adreno_smmu: iommu@3da0000 {</div><div class='add'>+			compatible = "qcom,sa8775p-smmu-500", "qcom,adreno-smmu",</div><div class='add'>+				     "qcom,smmu-500", "arm,mmu-500";</div><div class='add'>+			reg = &lt;0x0 0x03da0000 0x0 0x20000&gt;;</div><div class='add'>+			#iommu-cells = &lt;2&gt;;</div><div class='add'>+			#global-interrupts = &lt;2&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+			power-domains = &lt;&amp;gpucc GPU_CC_CX_GDSC&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_GPU_MEMNOC_GFX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_GPU_SNOC_DVM_GFX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gpucc GPU_CC_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gpucc GPU_CC_CX_GMU_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gpucc GPU_CC_HUB_CX_INT_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gpucc GPU_CC_HUB_AON_CLK&gt;;</div><div class='add'>+			clock-names = "gcc_gpu_memnoc_gfx_clk",</div><div class='add'>+				      "gcc_gpu_snoc_dvm_gfx_clk",</div><div class='add'>+				      "gpu_cc_ahb_clk",</div><div class='add'>+				      "gpu_cc_hlos1_vote_gpu_smmu_clk",</div><div class='add'>+				      "gpu_cc_cx_gmu_clk",</div><div class='add'>+				      "gpu_cc_hub_cx_int_clk",</div><div class='add'>+				      "gpu_cc_hub_aon_clk";</div><div class='add'>+			interrupts = &lt;GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		serdes0: phy@8901000 {</div><div class='add'>+			compatible = "qcom,sa8775p-dwmac-sgmii-phy";</div><div class='add'>+			reg = &lt;0x0 0x08901000 0x0 0xe10&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_SGMI_CLKREF_EN&gt;;</div><div class='add'>+			clock-names = "sgmi_ref";</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		serdes1: phy@8902000 {</div><div class='add'>+			compatible = "qcom,sa8775p-dwmac-sgmii-phy";</div><div class='add'>+			reg = &lt;0x0 0x08902000 0x0 0xe10&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_SGMI_CLKREF_EN&gt;;</div><div class='add'>+			clock-names = "sgmi_ref";</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmu@9091000 {</div><div class='add'>+			compatible = "qcom,sa8775p-llcc-bwmon", "qcom,sc7280-llcc-bwmon";</div><div class='add'>+			reg = &lt;0x0 0x9091000 0x0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interconnects = &lt;&amp;mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY&gt;;</div><div class='add'>+</div><div class='add'>+			operating-points-v2 = &lt;&amp;llcc_bwmon_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+			llcc_bwmon_opp_table: opp-table {</div><div class='add'>+				compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+				opp-0 {</div><div class='add'>+					opp-peak-kBps = &lt;762000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-1 {</div><div class='add'>+					opp-peak-kBps = &lt;1720000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-2 {</div><div class='add'>+					opp-peak-kBps = &lt;2086000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-3 {</div><div class='add'>+					opp-peak-kBps = &lt;2601000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-4 {</div><div class='add'>+					opp-peak-kBps = &lt;2929000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-5 {</div><div class='add'>+					opp-peak-kBps = &lt;5931000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-6 {</div><div class='add'>+					opp-peak-kBps = &lt;6515000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-7 {</div><div class='add'>+					opp-peak-kBps = &lt;7984000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-8 {</div><div class='add'>+					opp-peak-kBps = &lt;10437000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-9 {</div><div class='add'>+					opp-peak-kBps = &lt;12195000&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmu@90b5400 {</div><div class='add'>+			compatible = "qcom,sa8775p-cpu-bwmon", "qcom,sdm845-bwmon";</div><div class='add'>+			reg = &lt;0x0 0x90b5400 0x0 0x600&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interconnects = &lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY&gt;;</div><div class='add'>+</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu_bwmon_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+			cpu_bwmon_opp_table: opp-table {</div><div class='add'>+				compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+				opp-0 {</div><div class='add'>+					opp-peak-kBps = &lt;9155000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-1 {</div><div class='add'>+					opp-peak-kBps = &lt;12298000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-2 {</div><div class='add'>+					opp-peak-kBps = &lt;14236000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-3 {</div><div class='add'>+					opp-peak-kBps = &lt;16265000&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmu@90b6400 {</div><div class='add'>+			compatible = "qcom,sa8775p-cpu-bwmon", "qcom,sdm845-bwmon";</div><div class='add'>+			reg = &lt;0x0 0x90b6400 0x0 0x600&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interconnects = &lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY&gt;;</div><div class='add'>+</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu_bwmon_opp_table&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		llcc: system-cache-controller@9200000 {</div><div class='add'>+			compatible = "qcom,sa8775p-llcc";</div><div class='add'>+			reg = &lt;0x0 0x09200000 0x0 0x80000&gt;,</div><div class='add'>+			      &lt;0x0 0x09300000 0x0 0x80000&gt;,</div><div class='add'>+			      &lt;0x0 0x09400000 0x0 0x80000&gt;,</div><div class='add'>+			      &lt;0x0 0x09500000 0x0 0x80000&gt;,</div><div class='add'>+			      &lt;0x0 0x09600000 0x0 0x80000&gt;,</div><div class='add'>+			      &lt;0x0 0x09700000 0x0 0x80000&gt;,</div><div class='add'>+			      &lt;0x0 0x09a00000 0x0 0x80000&gt;;</div><div class='add'>+			reg-names = "llcc0_base",</div><div class='add'>+				    "llcc1_base",</div><div class='add'>+				    "llcc2_base",</div><div class='add'>+				    "llcc3_base",</div><div class='add'>+				    "llcc4_base",</div><div class='add'>+				    "llcc5_base",</div><div class='add'>+				    "llcc_broadcast_base";</div><div class='add'>+			interrupts = &lt;GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		iris: video-codec@aa00000 {</div><div class='add'>+			compatible = "qcom,sa8775p-iris", "qcom,sm8550-iris";</div><div class='add'>+</div><div class='add'>+			reg = &lt;0x0 0x0aa00000 0x0 0xf0000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;videocc VIDEO_CC_MVS0C_GDSC&gt;,</div><div class='add'>+					&lt;&amp;videocc VIDEO_CC_MVS0_GDSC&gt;,</div><div class='add'>+					&lt;&amp;rpmhpd SA8775P_MX&gt;,</div><div class='add'>+					&lt;&amp;rpmhpd SA8775P_MMCX&gt;;</div><div class='add'>+			power-domain-names = "venus",</div><div class='add'>+					     "vcodec0",</div><div class='add'>+					     "mxc",</div><div class='add'>+					     "mmcx";</div><div class='add'>+			operating-points-v2 = &lt;&amp;iris_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_VIDEO_AXI0_CLK&gt;,</div><div class='add'>+				 &lt;&amp;videocc VIDEO_CC_MVS0C_CLK&gt;,</div><div class='add'>+				 &lt;&amp;videocc VIDEO_CC_MVS0_CLK&gt;;</div><div class='add'>+			clock-names = "iface",</div><div class='add'>+				      "core",</div><div class='add'>+				      "vcodec0_core";</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+					&lt;&amp;mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+			interconnect-names = "cpu-cfg",</div><div class='add'>+					     "video-mem";</div><div class='add'>+</div><div class='add'>+			memory-region = &lt;&amp;pil_video_mem&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_VIDEO_AXI0_CLK_ARES&gt;;</div><div class='add'>+			reset-names = "bus";</div><div class='add'>+</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x0880 0x0400&gt;,</div><div class='add'>+				 &lt;&amp;apps_smmu 0x0887 0x0400&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			iris_opp_table: opp-table {</div><div class='add'>+				compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+				opp-366000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;366000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_svs_l1&gt;,</div><div class='add'>+							&lt;&amp;rpmhpd_opp_svs_l1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-444000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;444000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_nom&gt;,</div><div class='add'>+							&lt;&amp;rpmhpd_opp_nom&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-533000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;533000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_turbo&gt;,</div><div class='add'>+							&lt;&amp;rpmhpd_opp_turbo&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-560000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;560000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_turbo_l1&gt;,</div><div class='add'>+							&lt;&amp;rpmhpd_opp_turbo_l1&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		videocc: clock-controller@abf0000 {</div><div class='add'>+			compatible = "qcom,sa8775p-videocc";</div><div class='add'>+			reg = &lt;0x0 0x0abf0000 0x0 0x10000&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_VIDEO_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;,</div><div class='add'>+				 &lt;&amp;rpmhcc RPMH_CXO_CLK_A&gt;,</div><div class='add'>+				 &lt;&amp;sleep_clk&gt;;</div><div class='add'>+			power-domains = &lt;&amp;rpmhpd SA8775P_MMCX&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cci0: cci@ac13000 {</div><div class='add'>+			compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci";</div><div class='add'>+			reg = &lt;0x0 0x0ac13000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 460 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;camcc CAM_CC_TITAN_TOP_GDSC&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;camcc CAM_CC_CAMNOC_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_CPAS_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_CCI_0_CLK&gt;;</div><div class='add'>+			clock-names = "camnoc_axi",</div><div class='add'>+				      "cpas_ahb",</div><div class='add'>+				      "cci";</div><div class='add'>+</div><div class='add'>+			pinctrl-0 = &lt;&amp;cci0_0_default &amp;cci0_1_default&gt;;</div><div class='add'>+			pinctrl-1 = &lt;&amp;cci0_0_sleep &amp;cci0_1_sleep&gt;;</div><div class='add'>+			pinctrl-names = "default", "sleep";</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			cci0_i2c0: i2c-bus@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				clock-frequency = &lt;1000000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cci0_i2c1: i2c-bus@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				clock-frequency = &lt;1000000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cci1: cci@ac14000 {</div><div class='add'>+			compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci";</div><div class='add'>+			reg = &lt;0x0 0x0ac14000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 271 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;camcc CAM_CC_TITAN_TOP_GDSC&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;camcc CAM_CC_CAMNOC_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_CPAS_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_CCI_1_CLK&gt;;</div><div class='add'>+			clock-names = "camnoc_axi",</div><div class='add'>+				      "cpas_ahb",</div><div class='add'>+				      "cci";</div><div class='add'>+</div><div class='add'>+			pinctrl-0 = &lt;&amp;cci1_0_default &amp;cci1_1_default&gt;;</div><div class='add'>+			pinctrl-1 = &lt;&amp;cci1_0_sleep &amp;cci1_1_sleep&gt;;</div><div class='add'>+			pinctrl-names = "default", "sleep";</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			cci1_i2c0: i2c-bus@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				clock-frequency = &lt;1000000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cci1_i2c1: i2c-bus@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				clock-frequency = &lt;1000000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cci2: cci@ac15000 {</div><div class='add'>+			compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci";</div><div class='add'>+			reg = &lt;0x0 0x0ac15000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 651 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;camcc CAM_CC_TITAN_TOP_GDSC&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;camcc CAM_CC_CAMNOC_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_CPAS_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_CCI_2_CLK&gt;;</div><div class='add'>+			clock-names = "camnoc_axi",</div><div class='add'>+				      "cpas_ahb",</div><div class='add'>+				      "cci";</div><div class='add'>+</div><div class='add'>+			pinctrl-0 = &lt;&amp;cci2_0_default &amp;cci2_1_default&gt;;</div><div class='add'>+			pinctrl-1 = &lt;&amp;cci2_0_sleep &amp;cci2_1_sleep&gt;;</div><div class='add'>+			pinctrl-names = "default", "sleep";</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			cci2_i2c0: i2c-bus@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				clock-frequency = &lt;1000000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cci2_i2c1: i2c-bus@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				clock-frequency = &lt;1000000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cci3: cci@ac16000 {</div><div class='add'>+			compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci";</div><div class='add'>+			reg = &lt;0x0 0x0ac16000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 771 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;camcc CAM_CC_TITAN_TOP_GDSC&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;camcc CAM_CC_CAMNOC_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_CPAS_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_CCI_3_CLK&gt;;</div><div class='add'>+			clock-names = "camnoc_axi",</div><div class='add'>+				      "cpas_ahb",</div><div class='add'>+				      "cci";</div><div class='add'>+</div><div class='add'>+			pinctrl-0 = &lt;&amp;cci3_0_default &amp;cci3_1_default&gt;;</div><div class='add'>+			pinctrl-1 = &lt;&amp;cci3_0_sleep &amp;cci3_1_sleep&gt;;</div><div class='add'>+			pinctrl-names = "default", "sleep";</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			cci3_i2c0: i2c-bus@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				clock-frequency = &lt;1000000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cci3_i2c1: i2c-bus@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				clock-frequency = &lt;1000000&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		camss: isp@ac78000 {</div><div class='add'>+			compatible = "qcom,sa8775p-camss";</div><div class='add'>+</div><div class='add'>+			reg = &lt;0x0 0xac78000 0x0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0xac7a000 0x0 0x0f00&gt;,</div><div class='add'>+			      &lt;0x0 0xac7c000 0x0 0x0f00&gt;,</div><div class='add'>+			      &lt;0x0 0xac84000 0x0 0x0f00&gt;,</div><div class='add'>+			      &lt;0x0 0xac88000 0x0 0x0f00&gt;,</div><div class='add'>+			      &lt;0x0 0xac8c000 0x0 0x0f00&gt;,</div><div class='add'>+			      &lt;0x0 0xac90000 0x0 0x0f00&gt;,</div><div class='add'>+			      &lt;0x0 0xac94000 0x0 0x0f00&gt;,</div><div class='add'>+			      &lt;0x0 0xac9c000 0x0 0x2000&gt;,</div><div class='add'>+			      &lt;0x0 0xac9e000 0x0 0x2000&gt;,</div><div class='add'>+			      &lt;0x0 0xaca0000 0x0 0x2000&gt;,</div><div class='add'>+			      &lt;0x0 0xaca2000 0x0 0x2000&gt;,</div><div class='add'>+			      &lt;0x0 0xacac000 0x0 0x0400&gt;,</div><div class='add'>+			      &lt;0x0 0xacad000 0x0 0x0400&gt;,</div><div class='add'>+			      &lt;0x0 0xacae000 0x0 0x0400&gt;,</div><div class='add'>+			      &lt;0x0 0xac4d000 0x0 0xd000&gt;,</div><div class='add'>+			      &lt;0x0 0xac5a000 0x0 0xd000&gt;,</div><div class='add'>+			      &lt;0x0 0xac85000 0x0 0x0d00&gt;,</div><div class='add'>+			      &lt;0x0 0xac89000 0x0 0x0d00&gt;,</div><div class='add'>+			      &lt;0x0 0xac8d000 0x0 0x0d00&gt;,</div><div class='add'>+			      &lt;0x0 0xac91000 0x0 0x0d00&gt;,</div><div class='add'>+			      &lt;0x0 0xac95000 0x0 0x0d00&gt;;</div><div class='add'>+			reg-names = "csid_wrapper",</div><div class='add'>+				    "csid0",</div><div class='add'>+				    "csid1",</div><div class='add'>+				    "csid_lite0",</div><div class='add'>+				    "csid_lite1",</div><div class='add'>+				    "csid_lite2",</div><div class='add'>+				    "csid_lite3",</div><div class='add'>+				    "csid_lite4",</div><div class='add'>+				    "csiphy0",</div><div class='add'>+				    "csiphy1",</div><div class='add'>+				    "csiphy2",</div><div class='add'>+				    "csiphy3",</div><div class='add'>+				    "tpg0",</div><div class='add'>+				    "tpg1",</div><div class='add'>+				    "tpg2",</div><div class='add'>+				    "vfe0",</div><div class='add'>+				    "vfe1",</div><div class='add'>+				    "vfe_lite0",</div><div class='add'>+				    "vfe_lite1",</div><div class='add'>+				    "vfe_lite2",</div><div class='add'>+				    "vfe_lite3",</div><div class='add'>+				    "vfe_lite4";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;camcc CAM_CC_CAMNOC_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_CORE_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_CPAS_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_CPAS_FAST_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_CPAS_IFE_LITE_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_CPAS_IFE_0_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_CPAS_IFE_1_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_CSID_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_CSIPHY0_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_CSI0PHYTIMER_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_CSIPHY1_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_CSI1PHYTIMER_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_CSIPHY2_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_CSI2PHYTIMER_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_CSIPHY3_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_CSI3PHYTIMER_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_CSID_CSIPHY_RX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_CAMERA_HF_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_CAMERA_SF_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_ICP_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_IFE_0_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_IFE_0_FAST_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_IFE_1_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_IFE_1_FAST_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_IFE_LITE_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_IFE_LITE_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_IFE_LITE_CPHY_RX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;camcc CAM_CC_IFE_LITE_CSID_CLK&gt;;</div><div class='add'>+			clock-names = "camnoc_axi",</div><div class='add'>+				      "core_ahb",</div><div class='add'>+				      "cpas_ahb",</div><div class='add'>+				      "cpas_fast_ahb_clk",</div><div class='add'>+				      "cpas_vfe_lite",</div><div class='add'>+				      "cpas_vfe0",</div><div class='add'>+				      "cpas_vfe1",</div><div class='add'>+				      "csid",</div><div class='add'>+				      "csiphy0",</div><div class='add'>+				      "csiphy0_timer",</div><div class='add'>+				      "csiphy1",</div><div class='add'>+				      "csiphy1_timer",</div><div class='add'>+				      "csiphy2",</div><div class='add'>+				      "csiphy2_timer",</div><div class='add'>+				      "csiphy3",</div><div class='add'>+				      "csiphy3_timer",</div><div class='add'>+				      "csiphy_rx",</div><div class='add'>+				      "gcc_axi_hf",</div><div class='add'>+				      "gcc_axi_sf",</div><div class='add'>+				      "icp_ahb",</div><div class='add'>+				      "vfe0",</div><div class='add'>+				      "vfe0_fast_ahb",</div><div class='add'>+				      "vfe1",</div><div class='add'>+				      "vfe1_fast_ahb",</div><div class='add'>+				      "vfe_lite",</div><div class='add'>+				      "vfe_lite_ahb",</div><div class='add'>+				      "vfe_lite_cphy_rx",</div><div class='add'>+				      "vfe_lite_csid";</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 565 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 564 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 468 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 359 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 759 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 758 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 604 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 477 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 478 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 479 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 448 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 545 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 546 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 547 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 465 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 467 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 469 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 360 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 761 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 760 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+				     &lt;GIC_SPI 605 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			interrupt-names = "csid0",</div><div class='add'>+					  "csid1",</div><div class='add'>+					  "csid_lite0",</div><div class='add'>+					  "csid_lite1",</div><div class='add'>+					  "csid_lite2",</div><div class='add'>+					  "csid_lite3",</div><div class='add'>+					  "csid_lite4",</div><div class='add'>+					  "csiphy0",</div><div class='add'>+					  "csiphy1",</div><div class='add'>+					  "csiphy2",</div><div class='add'>+					  "csiphy3",</div><div class='add'>+					  "tpg0",</div><div class='add'>+					  "tpg1",</div><div class='add'>+					  "tpg2",</div><div class='add'>+					  "vfe0",</div><div class='add'>+					  "vfe1",</div><div class='add'>+					  "vfe_lite0",</div><div class='add'>+					  "vfe_lite1",</div><div class='add'>+					  "vfe_lite2",</div><div class='add'>+					  "vfe_lite3",</div><div class='add'>+					  "vfe_lite4";</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+					&lt;&amp;mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+			interconnect-names = "ahb",</div><div class='add'>+					     "hf_0";</div><div class='add'>+</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x3400 0x20&gt;;</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;camcc CAM_CC_TITAN_TOP_GDSC&gt;;</div><div class='add'>+			power-domain-names = "top";</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@2 {</div><div class='add'>+					reg = &lt;2&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@3 {</div><div class='add'>+					reg = &lt;3&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		camcc: clock-controller@ade0000 {</div><div class='add'>+			compatible = "qcom,sa8775p-camcc";</div><div class='add'>+			reg = &lt;0x0 0x0ade0000 0x0 0x20000&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_CAMERA_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;,</div><div class='add'>+				 &lt;&amp;rpmhcc RPMH_CXO_CLK_A&gt;,</div><div class='add'>+				 &lt;&amp;sleep_clk&gt;;</div><div class='add'>+			power-domains = &lt;&amp;rpmhpd SA8775P_MMCX&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mdss0: display-subsystem@ae00000 {</div><div class='add'>+			compatible = "qcom,sa8775p-mdss";</div><div class='add'>+			reg = &lt;0x0 0x0ae00000 0x0 0x1000&gt;;</div><div class='add'>+			reg-names = "mdss";</div><div class='add'>+</div><div class='add'>+			/* same path used twice */</div><div class='add'>+			interconnects = &lt;&amp;mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+					&lt;&amp;mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+					&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY&gt;;</div><div class='add'>+			interconnect-names = "mdp0-mem",</div><div class='add'>+					     "mdp1-mem",</div><div class='add'>+					     "cpu-cfg";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_CORE_BCR&gt;;</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_CORE_GDSC&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_DISP_HF_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x1000 0x402&gt;;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			mdss0_mdp: display-controller@ae01000 {</div><div class='add'>+				compatible = "qcom,sa8775p-dpu";</div><div class='add'>+				reg = &lt;0x0 0x0ae01000 0x0 0x8f000&gt;,</div><div class='add'>+				      &lt;0x0 0x0aeb0000 0x0 0x3000&gt;;</div><div class='add'>+				reg-names = "mdp", "vbif";</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_DISP_HF_AXI_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_MDP_LUT_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK&gt;;</div><div class='add'>+				clock-names = "nrt_bus",</div><div class='add'>+					      "iface",</div><div class='add'>+					      "lut",</div><div class='add'>+					      "core",</div><div class='add'>+					      "vsync";</div><div class='add'>+</div><div class='add'>+				assigned-clocks = &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK&gt;;</div><div class='add'>+				assigned-clock-rates = &lt;19200000&gt;;</div><div class='add'>+</div><div class='add'>+				operating-points-v2 = &lt;&amp;mdss0_mdp_opp_table&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_MMCX&gt;;</div><div class='add'>+</div><div class='add'>+				interrupt-parent = &lt;&amp;mdss0&gt;;</div><div class='add'>+				interrupts = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						dpu_intf0_out: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mdss0_dp0_in&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						dpu_intf4_out: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mdss0_dp1_in&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@2 {</div><div class='add'>+						reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+						dpu_intf1_out: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mdss0_dsi0_in&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@3 {</div><div class='add'>+						reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+						dpu_intf2_out: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;mdss0_dsi1_in&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				mdss0_mdp_opp_table: opp-table {</div><div class='add'>+					compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+					opp-375000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;375000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_svs_l1&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					opp-500000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;500000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_nom&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					opp-575000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;575000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_turbo&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					opp-650000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;650000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_turbo_l1&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mdss0_dsi0: dsi@ae94000 {</div><div class='add'>+				compatible = "qcom,sa8775p-dsi-ctrl", "qcom,mdss-dsi-ctrl";</div><div class='add'>+				reg = &lt;0x0 0x0ae94000 0x0 0x400&gt;;</div><div class='add'>+				reg-names = "dsi_ctrl";</div><div class='add'>+</div><div class='add'>+				interrupt-parent = &lt;&amp;mdss0&gt;;</div><div class='add'>+				interrupts = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_BYTE0_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_PCLK0_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_ESC0_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK&gt;,</div><div class='add'>+					 &lt;&amp;gcc GCC_DISP_HF_AXI_CLK&gt;;</div><div class='add'>+				clock-names = "byte",</div><div class='add'>+					      "byte_intf",</div><div class='add'>+					      "pixel",</div><div class='add'>+					      "core",</div><div class='add'>+					      "iface",</div><div class='add'>+					      "bus";</div><div class='add'>+				assigned-clocks = &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC&gt;,</div><div class='add'>+						  &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;mdss0_dsi0_phy DSI_BYTE_PLL_CLK&gt;,</div><div class='add'>+							 &lt;&amp;mdss0_dsi0_phy DSI_PIXEL_PLL_CLK&gt;;</div><div class='add'>+				phys = &lt;&amp;mdss0_dsi0_phy&gt;;</div><div class='add'>+</div><div class='add'>+				operating-points-v2 = &lt;&amp;mdss_dsi_opp_table&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_MMCX&gt;;</div><div class='add'>+</div><div class='add'>+				refgen-supply = &lt;&amp;refgen&gt;;</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						mdss0_dsi0_in: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;dpu_intf1_out&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						mdss0_dsi0_out: endpoint{ };</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				mdss_dsi_opp_table: opp-table {</div><div class='add'>+					compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+					opp-358000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;358000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_svs_l1&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mdss0_dsi0_phy: phy@ae94400 {</div><div class='add'>+				compatible = "qcom,sa8775p-dsi-phy-5nm";</div><div class='add'>+				reg = &lt;0x0 0x0ae94400 0x0 0x200&gt;,</div><div class='add'>+				      &lt;0x0 0x0ae94600 0x0 0x280&gt;,</div><div class='add'>+				      &lt;0x0 0x0ae94900 0x0 0x27c&gt;;</div><div class='add'>+				reg-names = "dsi_phy",</div><div class='add'>+					    "dsi_phy_lane",</div><div class='add'>+					    "dsi_pll";</div><div class='add'>+</div><div class='add'>+				#clock-cells = &lt;1&gt;;</div><div class='add'>+				#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK&gt;,</div><div class='add'>+					 &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;;</div><div class='add'>+				clock-names = "iface", "ref";</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mdss0_dsi1: dsi@ae96000 {</div><div class='add'>+				compatible = "qcom,sa8775p-dsi-ctrl", "qcom,mdss-dsi-ctrl";</div><div class='add'>+				reg = &lt;0x0 0x0ae96000 0x0 0x400&gt;;</div><div class='add'>+				reg-names = "dsi_ctrl";</div><div class='add'>+</div><div class='add'>+				interrupt-parent = &lt;&amp;mdss0&gt;;</div><div class='add'>+				interrupts = &lt;5&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_BYTE1_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_BYTE1_INTF_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_PCLK1_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_ESC1_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK&gt;,</div><div class='add'>+					 &lt;&amp;gcc GCC_DISP_HF_AXI_CLK&gt;;</div><div class='add'>+				clock-names = "byte",</div><div class='add'>+					      "byte_intf",</div><div class='add'>+					      "pixel",</div><div class='add'>+					      "core",</div><div class='add'>+					      "iface",</div><div class='add'>+					      "bus";</div><div class='add'>+				assigned-clocks = &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_BYTE1_CLK_SRC&gt;,</div><div class='add'>+						  &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_PCLK1_CLK_SRC&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;mdss0_dsi1_phy DSI_BYTE_PLL_CLK&gt;,</div><div class='add'>+							 &lt;&amp;mdss0_dsi1_phy DSI_PIXEL_PLL_CLK&gt;;</div><div class='add'>+				phys = &lt;&amp;mdss0_dsi1_phy&gt;;</div><div class='add'>+</div><div class='add'>+				operating-points-v2 = &lt;&amp;mdss_dsi_opp_table&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_MMCX&gt;;</div><div class='add'>+</div><div class='add'>+				refgen-supply = &lt;&amp;refgen&gt;;</div><div class='add'>+</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						mdss0_dsi1_in: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;dpu_intf2_out&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						mdss0_dsi1_out: endpoint { };</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mdss0_dsi1_phy: phy@ae96400 {</div><div class='add'>+				compatible = "qcom,sa8775p-dsi-phy-5nm";</div><div class='add'>+				reg = &lt;0x0 0x0ae96400 0x0 0x200&gt;,</div><div class='add'>+				      &lt;0x0 0x0ae96600 0x0 0x280&gt;,</div><div class='add'>+				      &lt;0x0 0x0ae96900 0x0 0x27c&gt;;</div><div class='add'>+				reg-names = "dsi_phy",</div><div class='add'>+					    "dsi_phy_lane",</div><div class='add'>+					    "dsi_pll";</div><div class='add'>+</div><div class='add'>+				#clock-cells = &lt;1&gt;;</div><div class='add'>+				#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK&gt;,</div><div class='add'>+					 &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;;</div><div class='add'>+				clock-names = "iface", "ref";</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mdss0_dp0_phy: phy@aec2a00 {</div><div class='add'>+				compatible = "qcom,sa8775p-edp-phy";</div><div class='add'>+</div><div class='add'>+				reg = &lt;0x0 0x0aec2a00 0x0 0x200&gt;,</div><div class='add'>+				      &lt;0x0 0x0aec2200 0x0 0xd0&gt;,</div><div class='add'>+				      &lt;0x0 0x0aec2600 0x0 0xd0&gt;,</div><div class='add'>+				      &lt;0x0 0x0aec2000 0x0 0x1c8&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK&gt;;</div><div class='add'>+				clock-names = "aux",</div><div class='add'>+					      "cfg_ahb";</div><div class='add'>+</div><div class='add'>+				#clock-cells = &lt;1&gt;;</div><div class='add'>+				#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mdss0_dp1_phy: phy@aec5a00 {</div><div class='add'>+				compatible = "qcom,sa8775p-edp-phy";</div><div class='add'>+</div><div class='add'>+				reg = &lt;0x0 0x0aec5a00 0x0 0x200&gt;,</div><div class='add'>+				      &lt;0x0 0x0aec5200 0x0 0xd0&gt;,</div><div class='add'>+				      &lt;0x0 0x0aec5600 0x0 0xd0&gt;,</div><div class='add'>+				      &lt;0x0 0x0aec5000 0x0 0x1c8&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK&gt;;</div><div class='add'>+				clock-names = "aux",</div><div class='add'>+					      "cfg_ahb";</div><div class='add'>+</div><div class='add'>+				#clock-cells = &lt;1&gt;;</div><div class='add'>+				#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mdss0_dp0: displayport-controller@af54000 {</div><div class='add'>+				compatible = "qcom,sa8775p-dp";</div><div class='add'>+</div><div class='add'>+				reg = &lt;0x0 0x0af54000 0x0 0x104&gt;,</div><div class='add'>+				      &lt;0x0 0x0af54200 0x0 0x0c0&gt;,</div><div class='add'>+				      &lt;0x0 0x0af55000 0x0 0x770&gt;,</div><div class='add'>+				      &lt;0x0 0x0af56000 0x0 0x09c&gt;,</div><div class='add'>+				      &lt;0x0 0x0af57000 0x0 0x09c&gt;,</div><div class='add'>+				      &lt;0x0 0x0af58000 0x0 0x09c&gt;,</div><div class='add'>+				      &lt;0x0 0x0af59000 0x0 0x09c&gt;,</div><div class='add'>+				      &lt;0x0 0x0af5a000 0x0 0x23c&gt;,</div><div class='add'>+				      &lt;0x0 0x0af5b000 0x0 0x23c&gt;;</div><div class='add'>+</div><div class='add'>+				interrupt-parent = &lt;&amp;mdss0&gt;;</div><div class='add'>+				interrupts = &lt;12&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK&gt;;</div><div class='add'>+				clock-names = "core_iface",</div><div class='add'>+					      "core_aux",</div><div class='add'>+					      "ctrl_link",</div><div class='add'>+					      "ctrl_link_iface",</div><div class='add'>+					      "stream_pixel",</div><div class='add'>+					      "stream_1_pixel",</div><div class='add'>+					      "stream_2_pixel",</div><div class='add'>+					      "stream_3_pixel";</div><div class='add'>+				assigned-clocks = &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC&gt;,</div><div class='add'>+						  &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC&gt;,</div><div class='add'>+						  &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC&gt;,</div><div class='add'>+						  &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC&gt;,</div><div class='add'>+						  &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;mdss0_dp0_phy 0&gt;,</div><div class='add'>+							 &lt;&amp;mdss0_dp0_phy 1&gt;,</div><div class='add'>+							 &lt;&amp;mdss0_dp0_phy 1&gt;,</div><div class='add'>+							 &lt;&amp;mdss0_dp0_phy 1&gt;,</div><div class='add'>+							 &lt;&amp;mdss0_dp0_phy 1&gt;;</div><div class='add'>+				phys = &lt;&amp;mdss0_dp0_phy&gt;;</div><div class='add'>+				phy-names = "dp";</div><div class='add'>+</div><div class='add'>+				operating-points-v2 = &lt;&amp;dp_opp_table&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_MMCX&gt;;</div><div class='add'>+</div><div class='add'>+				#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						mdss0_dp0_in: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;dpu_intf0_out&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						mdss0_dp0_out: endpoint { };</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				dp_opp_table: opp-table {</div><div class='add'>+					compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+					opp-160000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;160000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					opp-270000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;270000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_svs&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					opp-540000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;540000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_svs_l1&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					opp-810000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;810000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_nom&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mdss0_dp1: displayport-controller@af5c000 {</div><div class='add'>+				compatible = "qcom,sa8775p-dp";</div><div class='add'>+</div><div class='add'>+				reg = &lt;0x0 0x0af5c000 0x0 0x104&gt;,</div><div class='add'>+				      &lt;0x0 0x0af5c200 0x0 0x0c0&gt;,</div><div class='add'>+				      &lt;0x0 0x0af5d000 0x0 0x770&gt;,</div><div class='add'>+				      &lt;0x0 0x0af5e000 0x0 0x09c&gt;,</div><div class='add'>+				      &lt;0x0 0x0af5f000 0x0 0x09c&gt;,</div><div class='add'>+				      &lt;0x0 0x0af60000 0x0 0x09c&gt;,</div><div class='add'>+				      &lt;0x0 0x0af61000 0x0 0x09c&gt;,</div><div class='add'>+				      &lt;0x0 0x0af62000 0x0 0x23c&gt;,</div><div class='add'>+				      &lt;0x0 0x0af63000 0x0 0x23c&gt;;</div><div class='add'>+</div><div class='add'>+				interrupt-parent = &lt;&amp;mdss0&gt;;</div><div class='add'>+				interrupts = &lt;13&gt;;</div><div class='add'>+</div><div class='add'>+				clocks = &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK&gt;,</div><div class='add'>+					 &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK&gt;;</div><div class='add'>+				clock-names = "core_iface",</div><div class='add'>+					      "core_aux",</div><div class='add'>+					      "ctrl_link",</div><div class='add'>+					      "ctrl_link_iface",</div><div class='add'>+					      "stream_pixel",</div><div class='add'>+					      "stream_1_pixel";</div><div class='add'>+				assigned-clocks = &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC&gt;,</div><div class='add'>+						  &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC&gt;,</div><div class='add'>+						  &lt;&amp;dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC&gt;;</div><div class='add'>+				assigned-clock-parents = &lt;&amp;mdss0_dp1_phy 0&gt;,</div><div class='add'>+							 &lt;&amp;mdss0_dp1_phy 1&gt;,</div><div class='add'>+							 &lt;&amp;mdss0_dp1_phy 1&gt;;</div><div class='add'>+				phys = &lt;&amp;mdss0_dp1_phy&gt;;</div><div class='add'>+				phy-names = "dp";</div><div class='add'>+</div><div class='add'>+				operating-points-v2 = &lt;&amp;dp1_opp_table&gt;;</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd SA8775P_MMCX&gt;;</div><div class='add'>+</div><div class='add'>+				#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				status = "disabled";</div><div class='add'>+</div><div class='add'>+				ports {</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					port@0 {</div><div class='add'>+						reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+						mdss0_dp1_in: endpoint {</div><div class='add'>+							remote-endpoint = &lt;&amp;dpu_intf4_out&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					port@1 {</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+						mdss0_dp1_out: endpoint { };</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				dp1_opp_table: opp-table {</div><div class='add'>+					compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+					opp-160000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;160000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					opp-270000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;270000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_svs&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					opp-540000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;540000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_svs_l1&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					opp-810000000 {</div><div class='add'>+						opp-hz = /bits/ 64 &lt;810000000&gt;;</div><div class='add'>+						required-opps = &lt;&amp;rpmhpd_opp_nom&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dispcc0: clock-controller@af00000 {</div><div class='add'>+			compatible = "qcom,sa8775p-dispcc0";</div><div class='add'>+			reg = &lt;0x0 0x0af00000 0x0 0x20000&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_DISP_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;,</div><div class='add'>+				 &lt;&amp;rpmhcc RPMH_CXO_CLK_A&gt;,</div><div class='add'>+				 &lt;&amp;sleep_clk&gt;,</div><div class='add'>+				 &lt;&amp;mdss0_dp0_phy 0&gt;, &lt;&amp;mdss0_dp0_phy 1&gt;,</div><div class='add'>+				 &lt;&amp;mdss0_dp1_phy 0&gt;, &lt;&amp;mdss0_dp1_phy 1&gt;,</div><div class='add'>+				 &lt;&amp;mdss0_dsi0_phy DSI_BYTE_PLL_CLK&gt;,</div><div class='add'>+				 &lt;&amp;mdss0_dsi0_phy DSI_PIXEL_PLL_CLK&gt;,</div><div class='add'>+				 &lt;&amp;mdss0_dsi1_phy DSI_BYTE_PLL_CLK&gt;,</div><div class='add'>+				 &lt;&amp;mdss0_dsi1_phy DSI_PIXEL_PLL_CLK&gt;;</div><div class='add'>+			power-domains = &lt;&amp;rpmhpd SA8775P_MMCX&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pdc: interrupt-controller@b220000 {</div><div class='add'>+			compatible = "qcom,sa8775p-pdc", "qcom,pdc";</div><div class='add'>+			reg = &lt;0x0 0x0b220000 0x0 0x30000&gt;,</div><div class='add'>+			      &lt;0x0 0x17c000f0 0x0 0x64&gt;;</div><div class='add'>+			qcom,pdc-ranges = &lt;0 480 40&gt;,</div><div class='add'>+					  &lt;40 140 14&gt;,</div><div class='add'>+					  &lt;54 263 1&gt;,</div><div class='add'>+					  &lt;55 306 4&gt;,</div><div class='add'>+					  &lt;59 312 3&gt;,</div><div class='add'>+					  &lt;62 374 2&gt;,</div><div class='add'>+					  &lt;64 434 2&gt;,</div><div class='add'>+					  &lt;66 438 2&gt;,</div><div class='add'>+					  &lt;70 520 1&gt;,</div><div class='add'>+					  &lt;73 523 1&gt;,</div><div class='add'>+					  &lt;118 568 6&gt;,</div><div class='add'>+					  &lt;124 609 3&gt;,</div><div class='add'>+					  &lt;159 638 1&gt;,</div><div class='add'>+					  &lt;160 720 3&gt;,</div><div class='add'>+					  &lt;169 728 30&gt;,</div><div class='add'>+					  &lt;199 416 2&gt;,</div><div class='add'>+					  &lt;201 449 1&gt;,</div><div class='add'>+					  &lt;202 89 1&gt;,</div><div class='add'>+					  &lt;203 451 1&gt;,</div><div class='add'>+					  &lt;204 462 1&gt;,</div><div class='add'>+					  &lt;205 264 1&gt;,</div><div class='add'>+					  &lt;206 579 1&gt;,</div><div class='add'>+					  &lt;207 653 1&gt;,</div><div class='add'>+					  &lt;208 656 1&gt;,</div><div class='add'>+					  &lt;209 659 1&gt;,</div><div class='add'>+					  &lt;210 122 1&gt;,</div><div class='add'>+					  &lt;211 699 1&gt;,</div><div class='add'>+					  &lt;212 705 1&gt;,</div><div class='add'>+					  &lt;213 450 1&gt;,</div><div class='add'>+					  &lt;214 643 2&gt;,</div><div class='add'>+					  &lt;216 646 5&gt;,</div><div class='add'>+					  &lt;221 390 5&gt;,</div><div class='add'>+					  &lt;226 700 2&gt;,</div><div class='add'>+					  &lt;228 440 1&gt;,</div><div class='add'>+					  &lt;229 663 1&gt;,</div><div class='add'>+					  &lt;230 524 2&gt;,</div><div class='add'>+					  &lt;232 612 3&gt;,</div><div class='add'>+					  &lt;235 723 5&gt;;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;intc&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tsens2: thermal-sensor@c251000 {</div><div class='add'>+			compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2";</div><div class='add'>+			reg = &lt;0x0 0x0c251000 0x0 0x1ff&gt;,</div><div class='add'>+			      &lt;0x0 0x0c224000 0x0 0x8&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 572 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#qcom,sensors = &lt;13&gt;;</div><div class='add'>+			interrupt-names = "uplow", "critical";</div><div class='add'>+			#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tsens3: thermal-sensor@c252000 {</div><div class='add'>+			compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2";</div><div class='add'>+			reg = &lt;0x0 0x0c252000 0x0 0x1ff&gt;,</div><div class='add'>+			      &lt;0x0 0x0c225000 0x0 0x8&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 573 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#qcom,sensors = &lt;13&gt;;</div><div class='add'>+			interrupt-names = "uplow", "critical";</div><div class='add'>+			#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tsens0: thermal-sensor@c263000 {</div><div class='add'>+			compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2";</div><div class='add'>+			reg = &lt;0x0 0x0c263000 0x0 0x1ff&gt;,</div><div class='add'>+			      &lt;0x0 0x0c222000 0x0 0x8&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#qcom,sensors = &lt;12&gt;;</div><div class='add'>+			interrupt-names = "uplow", "critical";</div><div class='add'>+			#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tsens1: thermal-sensor@c265000 {</div><div class='add'>+			compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2";</div><div class='add'>+			reg = &lt;0x0 0x0c265000 0x0 0x1ff&gt;,</div><div class='add'>+			      &lt;0x0 0x0c223000 0x0 0x8&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#qcom,sensors = &lt;12&gt;;</div><div class='add'>+			interrupt-names = "uplow", "critical";</div><div class='add'>+			#thermal-sensor-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aoss_qmp: power-management@c300000 {</div><div class='add'>+			compatible = "qcom,sa8775p-aoss-qmp", "qcom,aoss-qmp";</div><div class='add'>+			reg = &lt;0x0 0x0c300000 0x0 0x400&gt;;</div><div class='add'>+			interrupts-extended = &lt;&amp;ipcc IPCC_CLIENT_AOP</div><div class='add'>+					       IPCC_MPROC_SIGNAL_GLINK_QMP</div><div class='add'>+					       IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			mboxes = &lt;&amp;ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP&gt;;</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sram@c3f0000 {</div><div class='add'>+			compatible = "qcom,rpmh-stats";</div><div class='add'>+			reg = &lt;0x0 0x0c3f0000 0x0 0x400&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spmi_bus: spmi@c440000 {</div><div class='add'>+			compatible = "qcom,spmi-pmic-arb";</div><div class='add'>+			reg = &lt;0x0 0x0c440000 0x0 0x1100&gt;,</div><div class='add'>+			      &lt;0x0 0x0c600000 0x0 0x2000000&gt;,</div><div class='add'>+			      &lt;0x0 0x0e600000 0x0 0x100000&gt;,</div><div class='add'>+			      &lt;0x0 0x0e700000 0x0 0xa0000&gt;,</div><div class='add'>+			      &lt;0x0 0x0c40a000 0x0 0x26000&gt;;</div><div class='add'>+			reg-names = "core",</div><div class='add'>+				    "chnls",</div><div class='add'>+				    "obsrvr",</div><div class='add'>+				    "intr",</div><div class='add'>+				    "cnfg";</div><div class='add'>+			qcom,channel = &lt;0&gt;;</div><div class='add'>+			qcom,ee = &lt;0&gt;;</div><div class='add'>+			interrupts-extended = &lt;&amp;pdc 1 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "periph_irq";</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;4&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tlmm: pinctrl@f000000 {</div><div class='add'>+			compatible = "qcom,sa8775p-tlmm";</div><div class='add'>+			reg = &lt;0x0 0x0f000000 0x0 0x1000000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;tlmm 0 0 149&gt;;</div><div class='add'>+			wakeup-parent = &lt;&amp;pdc&gt;;</div><div class='add'>+</div><div class='add'>+			dp0_hot_plug_det: dp0-hot-plug-det-state {</div><div class='add'>+				pins = "gpio101";</div><div class='add'>+				function = "edp0_hot";</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			dp1_hot_plug_det: dp1-hot-plug-det-state {</div><div class='add'>+				pins = "gpio102";</div><div class='add'>+				function = "edp1_hot";</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			hs0_mi2s_active: hs0-mi2s-active-state {</div><div class='add'>+				pins = "gpio114", "gpio115", "gpio116", "gpio117";</div><div class='add'>+				function = "hs0_mi2s";</div><div class='add'>+				drive-strength = &lt;8&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			hs2_mi2s_active: hs2-mi2s-active-state {</div><div class='add'>+				pins = "gpio122", "gpio123", "gpio124", "gpio125";</div><div class='add'>+				function = "hs2_mi2s";</div><div class='add'>+				drive-strength = &lt;8&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cci0_0_default: cci0-0-default-state {</div><div class='add'>+				pins = "gpio60", "gpio61";</div><div class='add'>+				function = "cci_i2c";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up = &lt;2200&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cci0_0_sleep: cci0-0-sleep-state {</div><div class='add'>+				pins = "gpio60", "gpio61";</div><div class='add'>+				function = "cci_i2c";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-down;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cci0_1_default: cci0-1-default-state {</div><div class='add'>+				pins = "gpio52", "gpio53";</div><div class='add'>+				function = "cci_i2c";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up = &lt;2200&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cci0_1_sleep: cci0-1-sleep-state {</div><div class='add'>+				pins = "gpio52", "gpio53";</div><div class='add'>+				function = "cci_i2c";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-down;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cci1_0_default: cci1-0-default-state {</div><div class='add'>+				pins = "gpio62", "gpio63";</div><div class='add'>+				function = "cci_i2c";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up = &lt;2200&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cci1_0_sleep: cci1-0-sleep-state {</div><div class='add'>+				pins = "gpio62", "gpio63";</div><div class='add'>+				function = "cci_i2c";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-down;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cci1_1_default: cci1-1-default-state {</div><div class='add'>+				pins = "gpio54", "gpio55";</div><div class='add'>+				function = "cci_i2c";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up = &lt;2200&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cci1_1_sleep: cci1-1-sleep-state {</div><div class='add'>+				pins = "gpio54", "gpio55";</div><div class='add'>+				function = "cci_i2c";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-down;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cci2_0_default: cci2-0-default-state {</div><div class='add'>+				pins = "gpio64", "gpio65";</div><div class='add'>+				function = "cci_i2c";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up = &lt;2200&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cci2_0_sleep: cci2-0-sleep-state {</div><div class='add'>+				pins = "gpio64", "gpio65";</div><div class='add'>+				function = "cci_i2c";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-down;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cci2_1_default: cci2-1-default-state {</div><div class='add'>+				pins = "gpio56", "gpio57";</div><div class='add'>+				function = "cci_i2c";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up = &lt;2200&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cci2_1_sleep: cci2-1-sleep-state {</div><div class='add'>+				pins = "gpio56", "gpio57";</div><div class='add'>+				function = "cci_i2c";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-down;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cci3_0_default: cci3-0-default-state {</div><div class='add'>+				pins = "gpio66", "gpio67";</div><div class='add'>+				function = "cci_i2c";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up = &lt;2200&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cci3_0_sleep: cci3-0-sleep-state {</div><div class='add'>+				pins = "gpio66", "gpio67";</div><div class='add'>+				function = "cci_i2c";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-down;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cci3_1_default: cci3-1-default-state {</div><div class='add'>+				pins = "gpio58", "gpio59";</div><div class='add'>+				function = "cci_i2c";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-up = &lt;2200&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cci3_1_sleep: cci3-1-sleep-state {</div><div class='add'>+				pins = "gpio58", "gpio59";</div><div class='add'>+				function = "cci_i2c";</div><div class='add'>+				drive-strength = &lt;2&gt;;</div><div class='add'>+				bias-pull-down;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c0_default: qup-i2c0-state {</div><div class='add'>+				pins = "gpio20", "gpio21";</div><div class='add'>+				function = "qup0_se0";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c1_default: qup-i2c1-state {</div><div class='add'>+				pins = "gpio24", "gpio25";</div><div class='add'>+				function = "qup0_se1";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c2_default: qup-i2c2-state {</div><div class='add'>+				pins = "gpio36", "gpio37";</div><div class='add'>+				function = "qup0_se2";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c3_default: qup-i2c3-state {</div><div class='add'>+				pins = "gpio28", "gpio29";</div><div class='add'>+				function = "qup0_se3";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c4_default: qup-i2c4-state {</div><div class='add'>+				pins = "gpio32", "gpio33";</div><div class='add'>+				function = "qup0_se4";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c5_default: qup-i2c5-state {</div><div class='add'>+				pins = "gpio36", "gpio37";</div><div class='add'>+				function = "qup0_se5";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c7_default: qup-i2c7-state {</div><div class='add'>+				pins = "gpio40", "gpio41";</div><div class='add'>+				function = "qup1_se0";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c8_default: qup-i2c8-state {</div><div class='add'>+				pins = "gpio42", "gpio43";</div><div class='add'>+				function = "qup1_se1";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c9_default: qup-i2c9-state {</div><div class='add'>+				pins = "gpio46", "gpio47";</div><div class='add'>+				function = "qup1_se2";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c10_default: qup-i2c10-state {</div><div class='add'>+				pins = "gpio44", "gpio45";</div><div class='add'>+				function = "qup1_se3";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c11_default: qup-i2c11-state {</div><div class='add'>+				pins = "gpio48", "gpio49";</div><div class='add'>+				function = "qup1_se4";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c12_default: qup-i2c12-state {</div><div class='add'>+				pins = "gpio52", "gpio53";</div><div class='add'>+				function = "qup1_se5";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c13_default: qup-i2c13-state {</div><div class='add'>+				pins = "gpio56", "gpio57";</div><div class='add'>+				function = "qup1_se6";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c14_default: qup-i2c14-state {</div><div class='add'>+				pins = "gpio80", "gpio81";</div><div class='add'>+				function = "qup2_se0";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c15_default: qup-i2c15-state {</div><div class='add'>+				pins = "gpio84", "gpio85";</div><div class='add'>+				function = "qup2_se1";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c16_default: qup-i2c16-state {</div><div class='add'>+				pins = "gpio86", "gpio87";</div><div class='add'>+				function = "qup2_se2";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c17_default: qup-i2c17-state {</div><div class='add'>+				pins = "gpio91", "gpio92";</div><div class='add'>+				function = "qup2_se3";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c18_default: qup-i2c18-state {</div><div class='add'>+				pins = "gpio95", "gpio96";</div><div class='add'>+				function = "qup2_se4";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c19_default: qup-i2c19-state {</div><div class='add'>+				pins = "gpio99", "gpio100";</div><div class='add'>+				function = "qup2_se5";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c20_default: qup-i2c20-state {</div><div class='add'>+				pins = "gpio97", "gpio98";</div><div class='add'>+				function = "qup2_se6";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c21_default: qup-i2c21-state {</div><div class='add'>+				pins = "gpio13", "gpio14";</div><div class='add'>+				function = "qup3_se0";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi0_default: qup-spi0-state {</div><div class='add'>+				pins = "gpio20", "gpio21", "gpio22", "gpio23";</div><div class='add'>+				function = "qup0_se0";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi1_default: qup-spi1-state {</div><div class='add'>+				pins = "gpio24", "gpio25", "gpio26", "gpio27";</div><div class='add'>+				function = "qup0_se1";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi2_default: qup-spi2-state {</div><div class='add'>+				pins = "gpio36", "gpio37", "gpio38", "gpio39";</div><div class='add'>+				function = "qup0_se2";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi3_default: qup-spi3-state {</div><div class='add'>+				pins = "gpio28", "gpio29", "gpio30", "gpio31";</div><div class='add'>+				function = "qup0_se3";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi4_default: qup-spi4-state {</div><div class='add'>+				pins = "gpio32", "gpio33", "gpio34", "gpio35";</div><div class='add'>+				function = "qup0_se4";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi5_default: qup-spi5-state {</div><div class='add'>+				pins = "gpio36", "gpio37", "gpio38", "gpio39";</div><div class='add'>+				function = "qup0_se5";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi7_default: qup-spi7-state {</div><div class='add'>+				pins = "gpio40", "gpio41", "gpio42", "gpio43";</div><div class='add'>+				function = "qup1_se0";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi8_default: qup-spi8-state {</div><div class='add'>+				pins = "gpio42", "gpio43", "gpio40", "gpio41";</div><div class='add'>+				function = "qup1_se1";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi9_default: qup-spi9-state {</div><div class='add'>+				pins = "gpio46", "gpio47", "gpio44", "gpio45";</div><div class='add'>+				function = "qup1_se2";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi10_default: qup-spi10-state {</div><div class='add'>+				pins = "gpio44", "gpio45", "gpio46", "gpio47";</div><div class='add'>+				function = "qup1_se3";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi11_default: qup-spi11-state {</div><div class='add'>+				pins = "gpio48", "gpio49", "gpio50", "gpio51";</div><div class='add'>+				function = "qup1_se4";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi12_default: qup-spi12-state {</div><div class='add'>+				pins = "gpio52", "gpio53", "gpio54", "gpio55";</div><div class='add'>+				function = "qup1_se5";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi14_default: qup-spi14-state {</div><div class='add'>+				pins = "gpio80", "gpio81", "gpio82", "gpio83";</div><div class='add'>+				function = "qup2_se0";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi15_default: qup-spi15-state {</div><div class='add'>+				pins = "gpio84", "gpio85", "gpio99", "gpio100";</div><div class='add'>+				function = "qup2_se1";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi16_default: qup-spi16-state {</div><div class='add'>+				pins = "gpio86", "gpio87", "gpio88", "gpio89";</div><div class='add'>+				function = "qup2_se2";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi17_default: qup-spi17-state {</div><div class='add'>+				pins = "gpio91", "gpio92", "gpio93", "gpio94";</div><div class='add'>+				function = "qup2_se3";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi18_default: qup-spi18-state {</div><div class='add'>+				pins = "gpio95", "gpio96", "gpio97", "gpio98";</div><div class='add'>+				function = "qup2_se4";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi19_default: qup-spi19-state {</div><div class='add'>+				pins = "gpio99", "gpio100", "gpio84", "gpio85";</div><div class='add'>+				function = "qup2_se5";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi20_default: qup-spi20-state {</div><div class='add'>+				pins = "gpio97", "gpio98", "gpio95", "gpio96";</div><div class='add'>+				function = "qup2_se6";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi21_default: qup-spi21-state {</div><div class='add'>+				pins = "gpio13", "gpio14", "gpio15", "gpio16";</div><div class='add'>+				function = "qup3_se0";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart0_default: qup-uart0-state {</div><div class='add'>+				qup_uart0_cts: qup-uart0-cts-pins {</div><div class='add'>+					pins = "gpio20";</div><div class='add'>+					function = "qup0_se0";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart0_rts: qup-uart0-rts-pins {</div><div class='add'>+					pins = "gpio21";</div><div class='add'>+					function = "qup0_se0";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart0_tx: qup-uart0-tx-pins {</div><div class='add'>+					pins = "gpio22";</div><div class='add'>+					function = "qup0_se0";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart0_rx: qup-uart0-rx-pins {</div><div class='add'>+					pins = "gpio23";</div><div class='add'>+					function = "qup0_se0";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart1_default: qup-uart1-state {</div><div class='add'>+				qup_uart1_cts: qup-uart1-cts-pins {</div><div class='add'>+					pins = "gpio24";</div><div class='add'>+					function = "qup0_se1";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart1_rts: qup-uart1-rts-pins {</div><div class='add'>+					pins = "gpio25";</div><div class='add'>+					function = "qup0_se1";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart1_tx: qup-uart1-tx-pins {</div><div class='add'>+					pins = "gpio26";</div><div class='add'>+					function = "qup0_se1";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart1_rx: qup-uart1-rx-pins {</div><div class='add'>+					pins = "gpio27";</div><div class='add'>+					function = "qup0_se1";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart2_default: qup-uart2-state {</div><div class='add'>+				qup_uart2_cts: qup-uart2-cts-pins {</div><div class='add'>+					pins = "gpio36";</div><div class='add'>+					function = "qup0_se2";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart2_rts: qup-uart2-rts-pins {</div><div class='add'>+					pins = "gpio37";</div><div class='add'>+					function = "qup0_se2";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart2_tx: qup-uart2-tx-pins {</div><div class='add'>+					pins = "gpio38";</div><div class='add'>+					function = "qup0_se2";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart2_rx: qup-uart2-rx-pins {</div><div class='add'>+					pins = "gpio39";</div><div class='add'>+					function = "qup0_se2";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart3_default: qup-uart3-state {</div><div class='add'>+				qup_uart3_cts: qup-uart3-cts-pins {</div><div class='add'>+					pins = "gpio28";</div><div class='add'>+					function = "qup0_se3";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart3_rts: qup-uart3-rts-pins {</div><div class='add'>+					pins = "gpio29";</div><div class='add'>+					function = "qup0_se3";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart3_tx: qup-uart3-tx-pins {</div><div class='add'>+					pins = "gpio30";</div><div class='add'>+					function = "qup0_se3";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart3_rx: qup-uart3-rx-pins {</div><div class='add'>+					pins = "gpio31";</div><div class='add'>+					function = "qup0_se3";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart4_default: qup-uart4-state {</div><div class='add'>+				qup_uart4_cts: qup-uart4-cts-pins {</div><div class='add'>+					pins = "gpio32";</div><div class='add'>+					function = "qup0_se4";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart4_rts: qup-uart4-rts-pins {</div><div class='add'>+					pins = "gpio33";</div><div class='add'>+					function = "qup0_se4";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart4_tx: qup-uart4-tx-pins {</div><div class='add'>+					pins = "gpio34";</div><div class='add'>+					function = "qup0_se4";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart4_rx: qup-uart4-rx-pins {</div><div class='add'>+					pins = "gpio35";</div><div class='add'>+					function = "qup0_se4";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart5_default: qup-uart5-state {</div><div class='add'>+				qup_uart5_cts: qup-uart5-cts-pins {</div><div class='add'>+					pins = "gpio36";</div><div class='add'>+					function = "qup0_se5";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart5_rts: qup-uart5-rts-pins {</div><div class='add'>+					pins = "gpio37";</div><div class='add'>+					function = "qup0_se5";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart5_tx: qup-uart5-tx-pins {</div><div class='add'>+					pins = "gpio38";</div><div class='add'>+					function = "qup0_se5";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart5_rx: qup-uart5-rx-pins {</div><div class='add'>+					pins = "gpio39";</div><div class='add'>+					function = "qup0_se5";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart7_default: qup-uart7-state {</div><div class='add'>+				qup_uart7_cts: qup-uart7-cts-pins {</div><div class='add'>+					pins = "gpio40";</div><div class='add'>+					function = "qup1_se0";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart7_rts: qup-uart7-rts-pins {</div><div class='add'>+					pins = "gpio41";</div><div class='add'>+					function = "qup1_se0";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart7_tx: qup-uart7-tx-pins {</div><div class='add'>+					pins = "gpio42";</div><div class='add'>+					function = "qup1_se0";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart7_rx: qup-uart7-rx-pins {</div><div class='add'>+					pins = "gpio43";</div><div class='add'>+					function = "qup1_se0";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart8_default: qup-uart8-state {</div><div class='add'>+				qup_uart8_cts: qup-uart8-cts-pins {</div><div class='add'>+					pins = "gpio42";</div><div class='add'>+					function = "qup1_se1";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart8_rts: qup-uart8-rts-pins {</div><div class='add'>+					pins = "gpio43";</div><div class='add'>+					function = "qup1_se1";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart8_tx: qup-uart8-tx-pins {</div><div class='add'>+					pins = "gpio40";</div><div class='add'>+					function = "qup1_se1";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart8_rx: qup-uart8-rx-pins {</div><div class='add'>+					pins = "gpio41";</div><div class='add'>+					function = "qup1_se1";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart9_default: qup-uart9-state {</div><div class='add'>+				qup_uart9_cts: qup-uart9-cts-pins {</div><div class='add'>+					pins = "gpio46";</div><div class='add'>+					function = "qup1_se2";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart9_rts: qup-uart9-rts-pins {</div><div class='add'>+					pins = "gpio47";</div><div class='add'>+					function = "qup1_se2";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart9_tx: qup-uart9-tx-pins {</div><div class='add'>+					pins = "gpio44";</div><div class='add'>+					function = "qup1_se2";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart9_rx: qup-uart9-rx-pins {</div><div class='add'>+					pins = "gpio45";</div><div class='add'>+					function = "qup1_se2";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart10_default: qup-uart10-state {</div><div class='add'>+				pins = "gpio46", "gpio47";</div><div class='add'>+				function = "qup1_se3";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart11_default: qup-uart11-state {</div><div class='add'>+				qup_uart11_cts: qup-uart11-cts-pins {</div><div class='add'>+					pins = "gpio48";</div><div class='add'>+					function = "qup1_se4";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart11_rts: qup-uart11-rts-pins {</div><div class='add'>+					pins = "gpio49";</div><div class='add'>+					function = "qup1_se4";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart11_tx: qup-uart11-tx-pins {</div><div class='add'>+					pins = "gpio50";</div><div class='add'>+					function = "qup1_se4";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart11_rx: qup-uart11-rx-pins {</div><div class='add'>+					pins = "gpio51";</div><div class='add'>+					function = "qup1_se4";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart12_default: qup-uart12-state {</div><div class='add'>+				qup_uart12_cts: qup-uart12-cts-pins {</div><div class='add'>+					pins = "gpio52";</div><div class='add'>+					function = "qup1_se5";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart12_rts: qup-uart12-rts-pins {</div><div class='add'>+					pins = "gpio53";</div><div class='add'>+					function = "qup1_se5";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart12_tx: qup-uart12-tx-pins {</div><div class='add'>+					pins = "gpio54";</div><div class='add'>+					function = "qup1_se5";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart12_rx: qup-uart12-rx-pins {</div><div class='add'>+					pins = "gpio55";</div><div class='add'>+					function = "qup1_se5";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart14_default: qup-uart14-state {</div><div class='add'>+				qup_uart14_cts: qup-uart14-cts-pins {</div><div class='add'>+					pins = "gpio80";</div><div class='add'>+					function = "qup2_se0";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart14_rts: qup-uart14-rts-pins {</div><div class='add'>+					pins = "gpio81";</div><div class='add'>+					function = "qup2_se0";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart14_tx: qup-uart14-tx-pins {</div><div class='add'>+					pins = "gpio82";</div><div class='add'>+					function = "qup2_se0";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart14_rx: qup-uart14-rx-pins {</div><div class='add'>+					pins = "gpio83";</div><div class='add'>+					function = "qup2_se0";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart15_default: qup-uart15-state {</div><div class='add'>+				qup_uart15_cts: qup-uart15-cts-pins {</div><div class='add'>+					pins = "gpio84";</div><div class='add'>+					function = "qup2_se1";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart15_rts: qup-uart15-rts-pins {</div><div class='add'>+					pins = "gpio85";</div><div class='add'>+					function = "qup2_se1";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart15_tx: qup-uart15-tx-pins {</div><div class='add'>+					pins = "gpio99";</div><div class='add'>+					function = "qup2_se1";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart15_rx: qup-uart15-rx-pins {</div><div class='add'>+					pins = "gpio100";</div><div class='add'>+					function = "qup2_se1";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart16_default: qup-uart16-state {</div><div class='add'>+				qup_uart16_cts: qup-uart16-cts-pins {</div><div class='add'>+					pins = "gpio86";</div><div class='add'>+					function = "qup2_se2";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart16_rts: qup-uart16-rts-pins {</div><div class='add'>+					pins = "gpio87";</div><div class='add'>+					function = "qup2_se2";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart16_tx: qup-uart16-tx-pins {</div><div class='add'>+					pins = "gpio88";</div><div class='add'>+					function = "qup2_se2";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart16_rx: qup-uart16-rx-pins {</div><div class='add'>+					pins = "gpio89";</div><div class='add'>+					function = "qup2_se2";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart17_default: qup-uart17-state {</div><div class='add'>+				qup_uart17_cts: qup-uart17-cts-pins {</div><div class='add'>+					pins = "gpio91";</div><div class='add'>+					function = "qup2_se3";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart17_rts: qup0-uart17-rts-pins {</div><div class='add'>+					pins = "gpio92";</div><div class='add'>+					function = "qup2_se3";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart17_tx: qup0-uart17-tx-pins {</div><div class='add'>+					pins = "gpio93";</div><div class='add'>+					function = "qup2_se3";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart17_rx: qup0-uart17-rx-pins {</div><div class='add'>+					pins = "gpio94";</div><div class='add'>+					function = "qup2_se3";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart18_default: qup-uart18-state {</div><div class='add'>+				qup_uart18_cts: qup-uart18-cts-pins {</div><div class='add'>+					pins = "gpio95";</div><div class='add'>+					function = "qup2_se4";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart18_rts: qup-uart18-rts-pins {</div><div class='add'>+					pins = "gpio96";</div><div class='add'>+					function = "qup2_se4";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart18_tx: qup-uart18-tx-pins {</div><div class='add'>+					pins = "gpio97";</div><div class='add'>+					function = "qup2_se4";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart18_rx: qup-uart18-rx-pins {</div><div class='add'>+					pins = "gpio98";</div><div class='add'>+					function = "qup2_se4";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart19_default: qup-uart19-state {</div><div class='add'>+				qup_uart19_cts: qup-uart19-cts-pins {</div><div class='add'>+					pins = "gpio99";</div><div class='add'>+					function = "qup2_se5";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart19_rts: qup-uart19-rts-pins {</div><div class='add'>+					pins = "gpio100";</div><div class='add'>+					function = "qup2_se5";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart19_tx: qup-uart19-tx-pins {</div><div class='add'>+					pins = "gpio84";</div><div class='add'>+					function = "qup2_se5";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart19_rx: qup-uart19-rx-pins {</div><div class='add'>+					pins = "gpio85";</div><div class='add'>+					function = "qup2_se5";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart20_default: qup-uart20-state {</div><div class='add'>+				qup_uart20_cts: qup-uart20-cts-pins {</div><div class='add'>+					pins = "gpio97";</div><div class='add'>+					function = "qup2_se6";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart20_rts: qup-uart20-rts-pins {</div><div class='add'>+					pins = "gpio98";</div><div class='add'>+					function = "qup2_se6";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart20_tx: qup-uart20-tx-pins {</div><div class='add'>+					pins = "gpio95";</div><div class='add'>+					function = "qup2_se6";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart20_rx: qup-uart20-rx-pins {</div><div class='add'>+					pins = "gpio96";</div><div class='add'>+					function = "qup2_se6";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart21_default: qup-uart21-state {</div><div class='add'>+				qup_uart21_cts: qup-uart21-cts-pins {</div><div class='add'>+					pins = "gpio13";</div><div class='add'>+					function = "qup3_se0";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart21_rts: qup-uart21-rts-pins {</div><div class='add'>+					pins = "gpio14";</div><div class='add'>+					function = "qup3_se0";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart21_tx: qup-uart21-tx-pins {</div><div class='add'>+					pins = "gpio15";</div><div class='add'>+					function = "qup3_se0";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				qup_uart21_rx: qup-uart21-rx-pins {</div><div class='add'>+					pins = "gpio16";</div><div class='add'>+					function = "qup3_se0";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sdc_default: sdc-default-state {</div><div class='add'>+				clk-pins {</div><div class='add'>+					pins = "sdc1_clk";</div><div class='add'>+					drive-strength = &lt;16&gt;;</div><div class='add'>+					bias-disable;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cmd-pins {</div><div class='add'>+					pins = "sdc1_cmd";</div><div class='add'>+					drive-strength = &lt;10&gt;;</div><div class='add'>+					bias-pull-up;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				data-pins {</div><div class='add'>+					pins = "sdc1_data";</div><div class='add'>+					drive-strength = &lt;10&gt;;</div><div class='add'>+					bias-pull-up;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sdc_sleep: sdc-sleep-state {</div><div class='add'>+				clk-pins {</div><div class='add'>+					pins = "sdc1_clk";</div><div class='add'>+					drive-strength = &lt;2&gt;;</div><div class='add'>+					bias-bus-hold;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cmd-pins {</div><div class='add'>+					pins = "sdc1_cmd";</div><div class='add'>+					drive-strength = &lt;2&gt;;</div><div class='add'>+					bias-bus-hold;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				data-pins {</div><div class='add'>+					pins = "sdc1_data";</div><div class='add'>+					drive-strength = &lt;2&gt;;</div><div class='add'>+					bias-bus-hold;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sram: sram@146d8000 {</div><div class='add'>+			compatible = "qcom,sa8775p-imem", "syscon", "simple-mfd";</div><div class='add'>+			reg = &lt;0x0 0x146d8000 0x0 0x1000&gt;;</div><div class='add'>+			ranges = &lt;0x0 0x0 0x146d8000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			pil-reloc@94c {</div><div class='add'>+				compatible = "qcom,pil-reloc-info";</div><div class='add'>+				reg = &lt;0x94c 0xc8&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		apps_smmu: iommu@15000000 {</div><div class='add'>+			compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500";</div><div class='add'>+			reg = &lt;0x0 0x15000000 0x0 0x100000&gt;;</div><div class='add'>+			#iommu-cells = &lt;2&gt;;</div><div class='add'>+			#global-interrupts = &lt;2&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie_smmu: iommu@15200000 {</div><div class='add'>+			compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500";</div><div class='add'>+			reg = &lt;0x0 0x15200000 0x0 0x80000&gt;;</div><div class='add'>+			#iommu-cells = &lt;2&gt;;</div><div class='add'>+			#global-interrupts = &lt;2&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		intc: interrupt-controller@17a00000 {</div><div class='add'>+			compatible = "arm,gic-v3";</div><div class='add'>+			reg = &lt;0x0 0x17a00000 0x0 0x10000&gt;,     /* GICD */</div><div class='add'>+			      &lt;0x0 0x17a60000 0x0 0x100000&gt;;    /* GICR * 8 */</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#address-cells = &lt;0&gt;;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#redistributor-regions = &lt;1&gt;;</div><div class='add'>+			redistributor-stride = &lt;0x0 0x20000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		watchdog@17c10000 {</div><div class='add'>+			compatible = "qcom,apss-wdt-sa8775p", "qcom,kpss-wdt";</div><div class='add'>+			reg = &lt;0x0 0x17c10000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;sleep_clk&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 0 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		memtimer: timer@17c20000 {</div><div class='add'>+			compatible = "arm,armv7-timer-mem";</div><div class='add'>+			reg = &lt;0x0 0x17c20000 0x0 0x1000&gt;;</div><div class='add'>+			ranges = &lt;0x0 0x0 0x0 0x20000000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			frame@17c21000 {</div><div class='add'>+				reg = &lt;0x17c21000 0x1000&gt;,</div><div class='add'>+				      &lt;0x17c22000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				frame-number = &lt;0&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@17c23000 {</div><div class='add'>+				reg = &lt;0x17c23000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				frame-number = &lt;1&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@17c25000 {</div><div class='add'>+				reg = &lt;0x17c25000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				frame-number = &lt;2&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@17c27000 {</div><div class='add'>+				reg = &lt;0x17c27000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				frame-number = &lt;3&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@17c29000 {</div><div class='add'>+				reg = &lt;0x17c29000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				frame-number = &lt;4&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@17c2b000 {</div><div class='add'>+				reg = &lt;0x17c2b000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				frame-number = &lt;5&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@17c2d000 {</div><div class='add'>+				reg = &lt;0x17c2d000 0x1000&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				frame-number = &lt;6&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		apps_rsc: rsc@18200000 {</div><div class='add'>+			compatible = "qcom,rpmh-rsc";</div><div class='add'>+			reg = &lt;0x0 0x18200000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0x18210000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0x18220000 0x0 0x10000&gt;;</div><div class='add'>+			reg-names = "drv-0", "drv-1", "drv-2";</div><div class='add'>+			interrupts = &lt;GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			      &lt;GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			      &lt;GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			qcom,tcs-offset = &lt;0xd00&gt;;</div><div class='add'>+			qcom,drv-id = &lt;2&gt;;</div><div class='add'>+			qcom,tcs-config = &lt;ACTIVE_TCS 2&gt;,</div><div class='add'>+					  &lt;SLEEP_TCS 3&gt;,</div><div class='add'>+					  &lt;WAKE_TCS 3&gt;,</div><div class='add'>+					  &lt;CONTROL_TCS 0&gt;;</div><div class='add'>+			label = "apps_rsc";</div><div class='add'>+			power-domains = &lt;&amp;system_pd&gt;;</div><div class='add'>+</div><div class='add'>+			apps_bcm_voter: bcm-voter {</div><div class='add'>+				compatible = "qcom,bcm-voter";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			rpmhcc: clock-controller {</div><div class='add'>+				compatible = "qcom,sa8775p-rpmh-clk";</div><div class='add'>+				#clock-cells = &lt;1&gt;;</div><div class='add'>+				clock-names = "xo";</div><div class='add'>+				clocks = &lt;&amp;xo_board_clk&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			rpmhpd: power-controller {</div><div class='add'>+				compatible = "qcom,sa8775p-rpmhpd";</div><div class='add'>+				#power-domain-cells = &lt;1&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;rpmhpd_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+				rpmhpd_opp_table: opp-table {</div><div class='add'>+					compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+					rpmhpd_opp_ret: opp-0 {</div><div class='add'>+						opp-level = &lt;RPMH_REGULATOR_LEVEL_RETENTION&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					rpmhpd_opp_min_svs: opp-1 {</div><div class='add'>+						opp-level = &lt;RPMH_REGULATOR_LEVEL_MIN_SVS&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					rpmhpd_opp_low_svs: opp2 {</div><div class='add'>+						opp-level = &lt;RPMH_REGULATOR_LEVEL_LOW_SVS&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					rpmhpd_opp_svs: opp3 {</div><div class='add'>+						opp-level = &lt;RPMH_REGULATOR_LEVEL_SVS&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					rpmhpd_opp_svs_l1: opp-4 {</div><div class='add'>+						opp-level = &lt;RPMH_REGULATOR_LEVEL_SVS_L1&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					rpmhpd_opp_nom: opp-5 {</div><div class='add'>+						opp-level = &lt;RPMH_REGULATOR_LEVEL_NOM&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					rpmhpd_opp_nom_l1: opp-6 {</div><div class='add'>+						opp-level = &lt;RPMH_REGULATOR_LEVEL_NOM_L1&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					rpmhpd_opp_nom_l2: opp-7 {</div><div class='add'>+						opp-level = &lt;RPMH_REGULATOR_LEVEL_NOM_L2&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					rpmhpd_opp_turbo: opp-8 {</div><div class='add'>+						opp-level = &lt;RPMH_REGULATOR_LEVEL_TURBO&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					rpmhpd_opp_turbo_l1: opp-9 {</div><div class='add'>+						opp-level = &lt;RPMH_REGULATOR_LEVEL_TURBO_L1&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		epss_l3_cl0: interconnect@18590000 {</div><div class='add'>+			compatible = "qcom,sa8775p-epss-l3",</div><div class='add'>+				     "qcom,epss-l3";</div><div class='add'>+			reg = &lt;0x0 0x18590000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;, &lt;&amp;gcc GCC_GPLL0&gt;;</div><div class='add'>+			clock-names = "xo", "alternate";</div><div class='add'>+			#interconnect-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpufreq_hw: cpufreq@18591000 {</div><div class='add'>+			compatible = "qcom,sa8775p-cpufreq-epss",</div><div class='add'>+				     "qcom,cpufreq-epss";</div><div class='add'>+			reg = &lt;0x0 0x18591000 0x0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0x18593000 0x0 0x1000&gt;;</div><div class='add'>+			reg-names = "freq-domain0", "freq-domain1";</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;, &lt;&amp;gcc GCC_GPLL0&gt;;</div><div class='add'>+			clock-names = "xo", "alternate";</div><div class='add'>+</div><div class='add'>+			#freq-domain-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		epss_l3_cl1: interconnect@18592000 {</div><div class='add'>+			compatible = "qcom,sa8775p-epss-l3",</div><div class='add'>+				     "qcom,epss-l3";</div><div class='add'>+			reg = &lt;0x0 0x18592000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;, &lt;&amp;gcc GCC_GPLL0&gt;;</div><div class='add'>+			clock-names = "xo", "alternate";</div><div class='add'>+			#interconnect-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		remoteproc_gpdsp0: remoteproc@20c00000 {</div><div class='add'>+			compatible = "qcom,sa8775p-gpdsp0-pas";</div><div class='add'>+			reg = &lt;0x0 0x20c00000 0x0 0x10000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts-extended = &lt;&amp;intc GIC_SPI 768 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;smp2p_gpdsp0_in 0 0&gt;,</div><div class='add'>+					      &lt;&amp;smp2p_gpdsp0_in 1 0&gt;,</div><div class='add'>+					      &lt;&amp;smp2p_gpdsp0_in 2 0&gt;,</div><div class='add'>+					      &lt;&amp;smp2p_gpdsp0_in 3 0&gt;;</div><div class='add'>+			interrupt-names = "wdog", "fatal", "ready",</div><div class='add'>+					  "handover", "stop-ack";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;;</div><div class='add'>+			clock-names = "xo";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;,</div><div class='add'>+					&lt;&amp;rpmhpd SA8775P_MXC&gt;;</div><div class='add'>+			power-domain-names = "cx", "mxc";</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;gpdsp_anoc MASTER_DSP0 0</div><div class='add'>+					 &amp;config_noc SLAVE_CLK_CTL 0&gt;;</div><div class='add'>+</div><div class='add'>+			memory-region = &lt;&amp;pil_gdsp0_mem&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,qmp = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,smem-states = &lt;&amp;smp2p_gpdsp0_out 0&gt;;</div><div class='add'>+			qcom,smem-state-names = "stop";</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			glink-edge {</div><div class='add'>+				interrupts-extended = &lt;&amp;ipcc IPCC_CLIENT_GPDSP0</div><div class='add'>+							     IPCC_MPROC_SIGNAL_GLINK_QMP</div><div class='add'>+							     IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				mboxes = &lt;&amp;ipcc IPCC_CLIENT_GPDSP0</div><div class='add'>+						IPCC_MPROC_SIGNAL_GLINK_QMP&gt;;</div><div class='add'>+</div><div class='add'>+				label = "gpdsp0";</div><div class='add'>+				qcom,remote-pid = &lt;17&gt;;</div><div class='add'>+</div><div class='add'>+				fastrpc {</div><div class='add'>+					compatible = "qcom,fastrpc";</div><div class='add'>+					qcom,glink-channels = "fastrpcglink-apps-dsp";</div><div class='add'>+					label = "gdsp0";</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					compute-cb@1 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x38a1 0x0&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@2 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;2&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x38a2 0x0&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@3 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;3&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x38a3 0x0&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		remoteproc_gpdsp1: remoteproc@21c00000 {</div><div class='add'>+			compatible = "qcom,sa8775p-gpdsp1-pas";</div><div class='add'>+			reg = &lt;0x0 0x21c00000 0x0 0x10000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts-extended = &lt;&amp;intc GIC_SPI 624 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;smp2p_gpdsp1_in 0 0&gt;,</div><div class='add'>+					      &lt;&amp;smp2p_gpdsp1_in 1 0&gt;,</div><div class='add'>+					      &lt;&amp;smp2p_gpdsp1_in 2 0&gt;,</div><div class='add'>+					      &lt;&amp;smp2p_gpdsp1_in 3 0&gt;;</div><div class='add'>+			interrupt-names = "wdog", "fatal", "ready",</div><div class='add'>+					  "handover", "stop-ack";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;;</div><div class='add'>+			clock-names = "xo";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;,</div><div class='add'>+					&lt;&amp;rpmhpd SA8775P_MXC&gt;;</div><div class='add'>+			power-domain-names = "cx", "mxc";</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;gpdsp_anoc MASTER_DSP1 0</div><div class='add'>+					 &amp;config_noc SLAVE_CLK_CTL 0&gt;;</div><div class='add'>+</div><div class='add'>+			memory-region = &lt;&amp;pil_gdsp1_mem&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,qmp = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,smem-states = &lt;&amp;smp2p_gpdsp1_out 0&gt;;</div><div class='add'>+			qcom,smem-state-names = "stop";</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			glink-edge {</div><div class='add'>+				interrupts-extended = &lt;&amp;ipcc IPCC_CLIENT_GPDSP1</div><div class='add'>+							     IPCC_MPROC_SIGNAL_GLINK_QMP</div><div class='add'>+							     IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				mboxes = &lt;&amp;ipcc IPCC_CLIENT_GPDSP1</div><div class='add'>+						IPCC_MPROC_SIGNAL_GLINK_QMP&gt;;</div><div class='add'>+</div><div class='add'>+				label = "gpdsp1";</div><div class='add'>+				qcom,remote-pid = &lt;18&gt;;</div><div class='add'>+</div><div class='add'>+				fastrpc {</div><div class='add'>+					compatible = "qcom,fastrpc";</div><div class='add'>+					qcom,glink-channels = "fastrpcglink-apps-dsp";</div><div class='add'>+					label = "gdsp1";</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					compute-cb@1 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x38c1 0x0&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@2 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;2&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x38c2 0x0&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@3 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;3&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x38c3 0x0&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dispcc1: clock-controller@22100000 {</div><div class='add'>+			compatible = "qcom,sa8775p-dispcc1";</div><div class='add'>+			reg = &lt;0x0 0x22100000 0x0 0x20000&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_DISP_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;,</div><div class='add'>+				 &lt;&amp;rpmhcc RPMH_CXO_CLK_A&gt;,</div><div class='add'>+				 &lt;&amp;sleep_clk&gt;,</div><div class='add'>+				 &lt;0&gt;, &lt;0&gt;, &lt;0&gt;, &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;, &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;rpmhpd SA8775P_MMCX&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ethernet1: ethernet@23000000 {</div><div class='add'>+			compatible = "qcom,sa8775p-ethqos";</div><div class='add'>+			reg = &lt;0x0 0x23000000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0x23016000 0x0 0x100&gt;;</div><div class='add'>+			reg-names = "stmmaceth", "rgmii";</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "macirq", "sfty";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_EMAC1_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_EMAC1_SLV_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_EMAC1_PTP_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_EMAC1_PHY_AUX_CLK&gt;;</div><div class='add'>+			clock-names = "stmmaceth",</div><div class='add'>+				      "pclk",</div><div class='add'>+				      "ptp_ref",</div><div class='add'>+				      "phyaux";</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+					 &amp;config_noc SLAVE_EMAC1_CFG QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+					&lt;&amp;aggre1_noc MASTER_EMAC_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+			interconnect-names = "cpu-mac",</div><div class='add'>+					     "mac-mem";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;gcc EMAC1_GDSC&gt;;</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;serdes1&gt;;</div><div class='add'>+			phy-names = "serdes";</div><div class='add'>+</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x140 0xf&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+</div><div class='add'>+			snps,tso;</div><div class='add'>+			snps,pbl = &lt;32&gt;;</div><div class='add'>+			rx-fifo-depth = &lt;16384&gt;;</div><div class='add'>+			tx-fifo-depth = &lt;16384&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ethernet0: ethernet@23040000 {</div><div class='add'>+			compatible = "qcom,sa8775p-ethqos";</div><div class='add'>+			reg = &lt;0x0 0x23040000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0x23056000 0x0 0x100&gt;;</div><div class='add'>+			reg-names = "stmmaceth", "rgmii";</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "macirq", "sfty";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_EMAC0_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_EMAC0_SLV_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_EMAC0_PTP_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_EMAC0_PHY_AUX_CLK&gt;;</div><div class='add'>+			clock-names = "stmmaceth",</div><div class='add'>+				      "pclk",</div><div class='add'>+				      "ptp_ref",</div><div class='add'>+				      "phyaux";</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+					 &amp;config_noc SLAVE_EMAC_CFG QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+					&lt;&amp;aggre1_noc MASTER_EMAC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+			interconnect-names = "cpu-mac",</div><div class='add'>+					     "mac-mem";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;gcc EMAC0_GDSC&gt;;</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;serdes0&gt;;</div><div class='add'>+			phy-names = "serdes";</div><div class='add'>+</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x120 0xf&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+</div><div class='add'>+			snps,tso;</div><div class='add'>+			snps,pbl = &lt;32&gt;;</div><div class='add'>+			rx-fifo-depth = &lt;16384&gt;;</div><div class='add'>+			tx-fifo-depth = &lt;16384&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		remoteproc_cdsp0: remoteproc@26300000 {</div><div class='add'>+			compatible = "qcom,sa8775p-cdsp0-pas";</div><div class='add'>+			reg = &lt;0x0 0x26300000 0x0 0x10000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts-extended = &lt;&amp;intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;smp2p_cdsp0_in 0 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;smp2p_cdsp0_in 1 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;smp2p_cdsp0_in 2 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;smp2p_cdsp0_in 3 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			interrupt-names = "wdog", "fatal", "ready",</div><div class='add'>+					  "handover", "stop-ack";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;;</div><div class='add'>+			clock-names = "xo";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;,</div><div class='add'>+					&lt;&amp;rpmhpd SA8775P_MXC&gt;,</div><div class='add'>+					&lt;&amp;rpmhpd SA8775P_NSP0&gt;;</div><div class='add'>+			power-domain-names = "cx", "mxc", "nsp";</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;nspa_noc MASTER_CDSP_PROC 0</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 0&gt;;</div><div class='add'>+</div><div class='add'>+			memory-region = &lt;&amp;pil_cdsp0_mem&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,qmp = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,smem-states = &lt;&amp;smp2p_cdsp0_out 0&gt;;</div><div class='add'>+			qcom,smem-state-names = "stop";</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			glink-edge {</div><div class='add'>+				interrupts-extended = &lt;&amp;ipcc IPCC_CLIENT_CDSP</div><div class='add'>+							     IPCC_MPROC_SIGNAL_GLINK_QMP</div><div class='add'>+							     IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				mboxes = &lt;&amp;ipcc IPCC_CLIENT_CDSP</div><div class='add'>+						IPCC_MPROC_SIGNAL_GLINK_QMP&gt;;</div><div class='add'>+</div><div class='add'>+				label = "cdsp";</div><div class='add'>+				qcom,remote-pid = &lt;5&gt;;</div><div class='add'>+</div><div class='add'>+				fastrpc {</div><div class='add'>+					compatible = "qcom,fastrpc";</div><div class='add'>+					qcom,glink-channels = "fastrpcglink-apps-dsp";</div><div class='add'>+					label = "cdsp";</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					compute-cb@1 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x2141 0x04a0&gt;,</div><div class='add'>+							 &lt;&amp;apps_smmu 0x2181 0x0400&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@2 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;2&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x2142 0x04a0&gt;,</div><div class='add'>+							 &lt;&amp;apps_smmu 0x2182 0x0400&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@3 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;3&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x2143 0x04a0&gt;,</div><div class='add'>+							 &lt;&amp;apps_smmu 0x2183 0x0400&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@4 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;4&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x2144 0x04a0&gt;,</div><div class='add'>+							 &lt;&amp;apps_smmu 0x2184 0x0400&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@5 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;5&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x2145 0x04a0&gt;,</div><div class='add'>+							 &lt;&amp;apps_smmu 0x2185 0x0400&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@6 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;6&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x2146 0x04a0&gt;,</div><div class='add'>+							 &lt;&amp;apps_smmu 0x2186 0x0400&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@7 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;7&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x2147 0x04a0&gt;,</div><div class='add'>+							 &lt;&amp;apps_smmu 0x2187 0x0400&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@8 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;8&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x2148 0x04a0&gt;,</div><div class='add'>+							 &lt;&amp;apps_smmu 0x2188 0x0400&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@9 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;9&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x2149 0x04a0&gt;,</div><div class='add'>+							 &lt;&amp;apps_smmu 0x2189 0x0400&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@11 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;11&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x214b 0x04a0&gt;,</div><div class='add'>+							 &lt;&amp;apps_smmu 0x218b 0x0400&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		remoteproc_cdsp1: remoteproc@2a300000 {</div><div class='add'>+			compatible = "qcom,sa8775p-cdsp1-pas";</div><div class='add'>+			reg = &lt;0x0 0x2A300000 0x0 0x10000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts-extended = &lt;&amp;intc GIC_SPI 798 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;smp2p_cdsp1_in 0 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;smp2p_cdsp1_in 1 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;smp2p_cdsp1_in 2 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;smp2p_cdsp1_in 3 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			interrupt-names = "wdog", "fatal", "ready",</div><div class='add'>+					  "handover", "stop-ack";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;;</div><div class='add'>+			clock-names = "xo";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;rpmhpd SA8775P_CX&gt;,</div><div class='add'>+					&lt;&amp;rpmhpd SA8775P_MXC&gt;,</div><div class='add'>+					&lt;&amp;rpmhpd SA8775P_NSP1&gt;;</div><div class='add'>+			power-domain-names = "cx", "mxc", "nsp";</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;nspb_noc MASTER_CDSP_PROC_B 0</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 0&gt;;</div><div class='add'>+</div><div class='add'>+			memory-region = &lt;&amp;pil_cdsp1_mem&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,qmp = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,smem-states = &lt;&amp;smp2p_cdsp1_out 0&gt;;</div><div class='add'>+			qcom,smem-state-names = "stop";</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			glink-edge {</div><div class='add'>+				interrupts-extended = &lt;&amp;ipcc IPCC_CLIENT_NSP1</div><div class='add'>+							     IPCC_MPROC_SIGNAL_GLINK_QMP</div><div class='add'>+							     IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				mboxes = &lt;&amp;ipcc IPCC_CLIENT_NSP1</div><div class='add'>+						IPCC_MPROC_SIGNAL_GLINK_QMP&gt;;</div><div class='add'>+</div><div class='add'>+				label = "cdsp";</div><div class='add'>+				qcom,remote-pid = &lt;12&gt;;</div><div class='add'>+</div><div class='add'>+				fastrpc {</div><div class='add'>+					compatible = "qcom,fastrpc";</div><div class='add'>+					qcom,glink-channels = "fastrpcglink-apps-dsp";</div><div class='add'>+					label = "cdsp1";</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					compute-cb@1 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x2941 0x04a0&gt;,</div><div class='add'>+							 &lt;&amp;apps_smmu 0x2981 0x0400&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@2 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;2&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x2942 0x04a0&gt;,</div><div class='add'>+							 &lt;&amp;apps_smmu 0x2982 0x0400&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@3 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;3&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x2943 0x04a0&gt;,</div><div class='add'>+							 &lt;&amp;apps_smmu 0x2983 0x0400&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@4 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;4&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x2944 0x04a0&gt;,</div><div class='add'>+							 &lt;&amp;apps_smmu 0x2984 0x0400&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@5 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;5&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x2945 0x04a0&gt;,</div><div class='add'>+							 &lt;&amp;apps_smmu 0x2985 0x0400&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@6 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;6&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x2946 0x04a0&gt;,</div><div class='add'>+							 &lt;&amp;apps_smmu 0x2986 0x0400&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@7 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;7&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x2947 0x04a0&gt;,</div><div class='add'>+							 &lt;&amp;apps_smmu 0x2987 0x0400&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@8 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;8&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x2948 0x04a0&gt;,</div><div class='add'>+							 &lt;&amp;apps_smmu 0x2988 0x0400&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@9 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;9&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x2949 0x04a0&gt;,</div><div class='add'>+							 &lt;&amp;apps_smmu 0x2989 0x0400&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@10 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;10&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x294a 0x04a0&gt;,</div><div class='add'>+							 &lt;&amp;apps_smmu 0x298a 0x0400&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@11 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;11&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x294b 0x04a0&gt;,</div><div class='add'>+							 &lt;&amp;apps_smmu 0x298b 0x0400&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@12 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;12&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x294c 0x04a0&gt;,</div><div class='add'>+							 &lt;&amp;apps_smmu 0x298c 0x0400&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@13 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;13&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x294d 0x04a0&gt;,</div><div class='add'>+							 &lt;&amp;apps_smmu 0x298d 0x0400&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		remoteproc_adsp: remoteproc@30000000 {</div><div class='add'>+			compatible = "qcom,sa8775p-adsp-pas";</div><div class='add'>+			reg = &lt;0x0 0x30000000 0x0 0x100&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts-extended = &lt;&amp;pdc 6 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			interrupt-names = "wdog", "fatal", "ready", "handover",</div><div class='add'>+					  "stop-ack";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;;</div><div class='add'>+			clock-names = "xo";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;rpmhpd SA8775P_LCX&gt;,</div><div class='add'>+					&lt;&amp;rpmhpd SA8775P_LMX&gt;;</div><div class='add'>+			power-domain-names = "lcx", "lmx";</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;lpass_ag_noc MASTER_LPASS_PROC 0 &amp;mc_virt SLAVE_EBI1 0&gt;;</div><div class='add'>+</div><div class='add'>+			memory-region = &lt;&amp;pil_adsp_mem&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,qmp = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,smem-states = &lt;&amp;smp2p_adsp_out 0&gt;;</div><div class='add'>+			qcom,smem-state-names = "stop";</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			remoteproc_adsp_glink: glink-edge {</div><div class='add'>+				interrupts-extended = &lt;&amp;ipcc IPCC_CLIENT_LPASS</div><div class='add'>+							     IPCC_MPROC_SIGNAL_GLINK_QMP</div><div class='add'>+							     IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				mboxes = &lt;&amp;ipcc IPCC_CLIENT_LPASS</div><div class='add'>+						IPCC_MPROC_SIGNAL_GLINK_QMP&gt;;</div><div class='add'>+</div><div class='add'>+				label = "lpass";</div><div class='add'>+				qcom,remote-pid = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+				fastrpc {</div><div class='add'>+					compatible = "qcom,fastrpc";</div><div class='add'>+					qcom,glink-channels = "fastrpcglink-apps-dsp";</div><div class='add'>+					label = "adsp";</div><div class='add'>+					memory-region = &lt;&amp;adsp_rpc_remote_heap_mem&gt;;</div><div class='add'>+					qcom,vmids = &lt;QCOM_SCM_VMID_LPASS</div><div class='add'>+							  QCOM_SCM_VMID_ADSP_HEAP&gt;;</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					compute-cb@3 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;3&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x3003 0x0&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@4 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;4&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x3004 0x0&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@5 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;5&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x3005 0x0&gt;;</div><div class='add'>+						qcom,nsessions = &lt;5&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpr {</div><div class='add'>+					compatible = "qcom,gpr";</div><div class='add'>+					qcom,glink-channels = "adsp_apps";</div><div class='add'>+					qcom,domain = &lt;GPR_DOMAIN_ID_ADSP&gt;;</div><div class='add'>+					qcom,intents = &lt;512 20&gt;;</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					q6apm: service@1 {</div><div class='add'>+						compatible = "qcom,q6apm";</div><div class='add'>+						reg = &lt;GPR_APM_MODULE_IID&gt;;</div><div class='add'>+						#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+						qcom,protection-domain = "avs/audio",</div><div class='add'>+									 "msm/adsp/audio_pd";</div><div class='add'>+</div><div class='add'>+						q6apmbedai: bedais {</div><div class='add'>+							compatible = "qcom,q6apm-lpass-dais";</div><div class='add'>+							#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						q6apmdai: dais {</div><div class='add'>+							compatible = "qcom,q6apm-dais";</div><div class='add'>+							iommus = &lt;&amp;apps_smmu 0x3001 0x0&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					q6prm: service@2 {</div><div class='add'>+						compatible = "qcom,q6prm";</div><div class='add'>+						reg = &lt;GPR_PRM_MODULE_IID&gt;;</div><div class='add'>+						qcom,protection-domain = "avs/audio",</div><div class='add'>+									 "msm/adsp/audio_pd";</div><div class='add'>+</div><div class='add'>+						q6prmcc: clock-controller {</div><div class='add'>+							compatible = "qcom,q6prm-lpass-clocks";</div><div class='add'>+							#clock-cells = &lt;2&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	thermal-zones {</div><div class='add'>+		aoss-0-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 0&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu-0-0-0-thermal {</div><div class='add'>+			polling-delay-passive = &lt;10&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 1&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu-0-1-0-thermal {</div><div class='add'>+			polling-delay-passive = &lt;10&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 2&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu-0-2-0-thermal {</div><div class='add'>+			polling-delay-passive = &lt;10&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 3&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu-0-3-0-thermal {</div><div class='add'>+			polling-delay-passive = &lt;10&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 4&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpuss-0-thermal {</div><div class='add'>+			polling-delay-passive = &lt;10&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 5&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpuss-1-thermal {</div><div class='add'>+			polling-delay-passive = &lt;10&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 6&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpuss-2-thermal {</div><div class='add'>+			polling-delay-passive = &lt;10&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 7&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		audio-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 8&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		camss-0-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 9&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie-0-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 10&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpuss-0-0-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens0 11&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aoss-1-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens1 0&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu-0-0-1-thermal {</div><div class='add'>+			polling-delay-passive = &lt;10&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens1 1&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu-0-1-1-thermal {</div><div class='add'>+			polling-delay-passive = &lt;10&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens1 2&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu-0-2-1-thermal {</div><div class='add'>+			polling-delay-passive = &lt;10&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens1 3&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu-0-3-1-thermal {</div><div class='add'>+			polling-delay-passive = &lt;10&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens1 4&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpuss-3-thermal {</div><div class='add'>+			polling-delay-passive = &lt;10&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens1 5&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpuss-4-thermal {</div><div class='add'>+			polling-delay-passive = &lt;10&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens1 6&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpuss-5-thermal {</div><div class='add'>+			polling-delay-passive = &lt;10&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens1 7&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		video-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens1 8&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		camss-1-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens1 9&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie-1-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens1 10&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpuss-0-1-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens1 11&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aoss-2-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens2 0&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu-1-0-0-thermal {</div><div class='add'>+			polling-delay-passive = &lt;10&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens2 1&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu-1-1-0-thermal {</div><div class='add'>+			polling-delay-passive = &lt;10&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens2 2&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu-1-2-0-thermal {</div><div class='add'>+			polling-delay-passive = &lt;10&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens2 3&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu-1-3-0-thermal {</div><div class='add'>+			polling-delay-passive = &lt;10&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens2 4&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nsp-0-0-0-thermal {</div><div class='add'>+			polling-delay-passive = &lt;10&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens2 5&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nsp-0-1-0-thermal {</div><div class='add'>+			polling-delay-passive = &lt;10&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens2 6&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nsp-0-2-0-thermal {</div><div class='add'>+			polling-delay-passive = &lt;10&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens2 7&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nsp-1-0-0-thermal {</div><div class='add'>+			polling-delay-passive = &lt;10&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens2 8&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nsp-1-1-0-thermal {</div><div class='add'>+			polling-delay-passive = &lt;10&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens2 9&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nsp-1-2-0-thermal {</div><div class='add'>+			polling-delay-passive = &lt;10&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens2 10&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ddrss-0-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens2 11&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpuss-1-0-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens2 12&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aoss-3-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens3 0&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu-1-0-1-thermal {</div><div class='add'>+			polling-delay-passive = &lt;10&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens3 1&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu-1-1-1-thermal {</div><div class='add'>+			polling-delay-passive = &lt;10&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens3 2&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu-1-2-1-thermal {</div><div class='add'>+			polling-delay-passive = &lt;10&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens3 3&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu-1-3-1-thermal {</div><div class='add'>+			polling-delay-passive = &lt;10&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens3 4&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nsp-0-0-1-thermal {</div><div class='add'>+			polling-delay-passive = &lt;10&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens3 5&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nsp-0-1-1-thermal {</div><div class='add'>+			polling-delay-passive = &lt;10&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens3 6&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nsp-0-2-1-thermal {</div><div class='add'>+			polling-delay-passive = &lt;10&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens3 7&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nsp-1-0-1-thermal {</div><div class='add'>+			polling-delay-passive = &lt;10&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens3 8&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nsp-1-1-1-thermal {</div><div class='add'>+			polling-delay-passive = &lt;10&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens3 9&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nsp-1-2-1-thermal {</div><div class='add'>+			polling-delay-passive = &lt;10&gt;;</div><div class='add'>+</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens3 10&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ddrss-1-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens3 11&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpuss-1-1-thermal {</div><div class='add'>+			thermal-sensors = &lt;&amp;tsens3 12&gt;;</div><div class='add'>+</div><div class='add'>+			trips {</div><div class='add'>+				trip-point0 {</div><div class='add'>+					temperature = &lt;105000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				trip-point1 {</div><div class='add'>+					temperature = &lt;115000&gt;;</div><div class='add'>+					hysteresis = &lt;5000&gt;;</div><div class='add'>+					type = "passive";</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	arch_timer: timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0: pcie@1c00000 {</div><div class='add'>+		compatible = "qcom,pcie-sa8775p";</div><div class='add'>+		reg = &lt;0x0 0x01c00000 0x0 0x3000&gt;,</div><div class='add'>+		      &lt;0x0 0x40000000 0x0 0xf20&gt;,</div><div class='add'>+		      &lt;0x0 0x40000f20 0x0 0xa8&gt;,</div><div class='add'>+		      &lt;0x0 0x40001000 0x0 0x4000&gt;,</div><div class='add'>+		      &lt;0x0 0x40100000 0x0 0x100000&gt;,</div><div class='add'>+		      &lt;0x0 0x01c03000 0x0 0x1000&gt;;</div><div class='add'>+		reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";</div><div class='add'>+		device_type = "pci";</div><div class='add'>+</div><div class='add'>+		#address-cells = &lt;3&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges = &lt;0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000&gt;,</div><div class='add'>+			 &lt;0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000&gt;;</div><div class='add'>+		bus-range = &lt;0x00 0xff&gt;;</div><div class='add'>+</div><div class='add'>+		dma-coherent;</div><div class='add'>+</div><div class='add'>+		linux,pci-domain = &lt;0&gt;;</div><div class='add'>+		num-lanes = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		interrupts = &lt;GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-names = "msi0",</div><div class='add'>+				  "msi1",</div><div class='add'>+				  "msi2",</div><div class='add'>+				  "msi3",</div><div class='add'>+				  "msi4",</div><div class='add'>+				  "msi5",</div><div class='add'>+				  "msi6",</div><div class='add'>+				  "msi7",</div><div class='add'>+				  "global";</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		interrupt-map-mask = &lt;0 0 0 0x7&gt;;</div><div class='add'>+		interrupt-map = &lt;0 0 0 1 &amp;intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 0 2 &amp;intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 0 3 &amp;intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 0 4 &amp;intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;gcc GCC_PCIE_0_AUX_CLK&gt;,</div><div class='add'>+			 &lt;&amp;gcc GCC_PCIE_0_CFG_AHB_CLK&gt;,</div><div class='add'>+			 &lt;&amp;gcc GCC_PCIE_0_MSTR_AXI_CLK&gt;,</div><div class='add'>+			 &lt;&amp;gcc GCC_PCIE_0_SLV_AXI_CLK&gt;,</div><div class='add'>+			 &lt;&amp;gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK&gt;;</div><div class='add'>+</div><div class='add'>+		clock-names = "aux",</div><div class='add'>+			      "cfg",</div><div class='add'>+			      "bus_master",</div><div class='add'>+			      "bus_slave",</div><div class='add'>+			      "slave_q2a";</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;gcc GCC_PCIE_0_AUX_CLK&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;19200000&gt;;</div><div class='add'>+</div><div class='add'>+		interconnects = &lt;&amp;pcie_anoc MASTER_PCIE_0 0 &amp;mc_virt SLAVE_EBI1 0&gt;,</div><div class='add'>+				&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;config_noc SLAVE_PCIE_0 0&gt;;</div><div class='add'>+		interconnect-names = "pcie-mem", "cpu-pcie";</div><div class='add'>+</div><div class='add'>+		iommu-map = &lt;0x0 &amp;pcie_smmu 0x0000 0x1&gt;,</div><div class='add'>+			    &lt;0x100 &amp;pcie_smmu 0x0001 0x1&gt;;</div><div class='add'>+</div><div class='add'>+		resets = &lt;&amp;gcc GCC_PCIE_0_BCR&gt;,</div><div class='add'>+			 &lt;&amp;gcc GCC_PCIE_0_LINK_DOWN_BCR&gt;;</div><div class='add'>+		reset-names = "pci",</div><div class='add'>+			      "link_down";</div><div class='add'>+</div><div class='add'>+		power-domains = &lt;&amp;gcc PCIE_0_GDSC&gt;;</div><div class='add'>+</div><div class='add'>+		phys = &lt;&amp;pcie0_phy&gt;;</div><div class='add'>+		phy-names = "pciephy";</div><div class='add'>+</div><div class='add'>+		eq-presets-8gts = /bits/ 16 &lt;0x5555 0x5555&gt;;</div><div class='add'>+		eq-presets-16gts = /bits/ 8 &lt;0x55 0x55&gt;;</div><div class='add'>+</div><div class='add'>+		status = "disabled";</div><div class='add'>+</div><div class='add'>+		pcieport0: pcie@0 {</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			reg = &lt;0x0 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+			bus-range = &lt;0x01 0xff&gt;;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_ep: pcie-ep@1c00000 {</div><div class='add'>+		compatible = "qcom,sa8775p-pcie-ep";</div><div class='add'>+		reg = &lt;0x0 0x01c00000 0x0 0x3000&gt;,</div><div class='add'>+		      &lt;0x0 0x40000000 0x0 0xf20&gt;,</div><div class='add'>+		      &lt;0x0 0x40000f20 0x0 0xa8&gt;,</div><div class='add'>+		      &lt;0x0 0x40001000 0x0 0x4000&gt;,</div><div class='add'>+		      &lt;0x0 0x40200000 0x0 0x1fe00000&gt;,</div><div class='add'>+		      &lt;0x0 0x01c03000 0x0 0x1000&gt;,</div><div class='add'>+		      &lt;0x0 0x40005000 0x0 0x2000&gt;;</div><div class='add'>+		reg-names = "parf", "dbi", "elbi", "atu", "addr_space",</div><div class='add'>+			    "mmio", "dma";</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;gcc GCC_PCIE_0_AUX_CLK&gt;,</div><div class='add'>+			&lt;&amp;gcc GCC_PCIE_0_CFG_AHB_CLK&gt;,</div><div class='add'>+			&lt;&amp;gcc GCC_PCIE_0_MSTR_AXI_CLK&gt;,</div><div class='add'>+			&lt;&amp;gcc GCC_PCIE_0_SLV_AXI_CLK&gt;,</div><div class='add'>+			&lt;&amp;gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK&gt;;</div><div class='add'>+</div><div class='add'>+		clock-names = "aux",</div><div class='add'>+			      "cfg",</div><div class='add'>+			      "bus_master",</div><div class='add'>+			      "bus_slave",</div><div class='add'>+			      "slave_q2a";</div><div class='add'>+</div><div class='add'>+		interrupts = &lt;GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-names = "global", "doorbell", "dma";</div><div class='add'>+</div><div class='add'>+		interconnects = &lt;&amp;pcie_anoc MASTER_PCIE_0 0 &amp;mc_virt SLAVE_EBI1 0&gt;,</div><div class='add'>+				&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;config_noc SLAVE_PCIE_0 0&gt;;</div><div class='add'>+		interconnect-names = "pcie-mem", "cpu-pcie";</div><div class='add'>+</div><div class='add'>+		dma-coherent;</div><div class='add'>+		iommus = &lt;&amp;pcie_smmu 0x0000 0x7f&gt;;</div><div class='add'>+		resets = &lt;&amp;gcc GCC_PCIE_0_BCR&gt;;</div><div class='add'>+		reset-names = "core";</div><div class='add'>+		power-domains = &lt;&amp;gcc PCIE_0_GDSC&gt;;</div><div class='add'>+		phys = &lt;&amp;pcie0_phy&gt;;</div><div class='add'>+		phy-names = "pciephy";</div><div class='add'>+		num-lanes = &lt;2&gt;;</div><div class='add'>+		linux,pci-domain = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie0_phy: phy@1c04000 {</div><div class='add'>+		compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy";</div><div class='add'>+		reg = &lt;0x0 0x1c04000 0x0 0x2000&gt;;</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;gcc GCC_PCIE_0_PHY_AUX_CLK&gt;,</div><div class='add'>+			 &lt;&amp;gcc GCC_PCIE_0_CFG_AHB_CLK&gt;,</div><div class='add'>+			 &lt;&amp;gcc GCC_PCIE_CLKREF_EN&gt;,</div><div class='add'>+			 &lt;&amp;gcc GCC_PCIE_0_PHY_RCHNG_CLK&gt;,</div><div class='add'>+			 &lt;&amp;gcc GCC_PCIE_0_PIPE_CLK&gt;,</div><div class='add'>+			 &lt;&amp;gcc GCC_PCIE_0_PIPEDIV2_CLK&gt;;</div><div class='add'>+		clock-names = "aux",</div><div class='add'>+			      "cfg_ahb",</div><div class='add'>+			      "ref",</div><div class='add'>+			      "rchng",</div><div class='add'>+			      "pipe",</div><div class='add'>+			      "pipediv2";</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;gcc GCC_PCIE_0_PHY_RCHNG_CLK&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;100000000&gt;;</div><div class='add'>+</div><div class='add'>+		resets = &lt;&amp;gcc GCC_PCIE_0_PHY_BCR&gt;;</div><div class='add'>+		reset-names = "phy";</div><div class='add'>+</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-output-names = "pcie_0_pipe_clk";</div><div class='add'>+</div><div class='add'>+		#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie1: pcie@1c10000 {</div><div class='add'>+		compatible = "qcom,pcie-sa8775p";</div><div class='add'>+		reg = &lt;0x0 0x01c10000 0x0 0x3000&gt;,</div><div class='add'>+		      &lt;0x0 0x60000000 0x0 0xf20&gt;,</div><div class='add'>+		      &lt;0x0 0x60000f20 0x0 0xa8&gt;,</div><div class='add'>+		      &lt;0x0 0x60001000 0x0 0x4000&gt;,</div><div class='add'>+		      &lt;0x0 0x60100000 0x0 0x100000&gt;,</div><div class='add'>+		      &lt;0x0 0x01c13000 0x0 0x1000&gt;;</div><div class='add'>+		reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";</div><div class='add'>+		device_type = "pci";</div><div class='add'>+</div><div class='add'>+		#address-cells = &lt;3&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges = &lt;0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000&gt;,</div><div class='add'>+			 &lt;0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000&gt;;</div><div class='add'>+		bus-range = &lt;0x00 0xff&gt;;</div><div class='add'>+</div><div class='add'>+		dma-coherent;</div><div class='add'>+</div><div class='add'>+		linux,pci-domain = &lt;1&gt;;</div><div class='add'>+		num-lanes = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+		interrupts = &lt;GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		interrupt-names = "msi0",</div><div class='add'>+				  "msi1",</div><div class='add'>+				  "msi2",</div><div class='add'>+				  "msi3",</div><div class='add'>+				  "msi4",</div><div class='add'>+				  "msi5",</div><div class='add'>+				  "msi6",</div><div class='add'>+				  "msi7",</div><div class='add'>+				  "global";</div><div class='add'>+		#interrupt-cells = &lt;1&gt;;</div><div class='add'>+		interrupt-map-mask = &lt;0 0 0 0x7&gt;;</div><div class='add'>+		interrupt-map = &lt;0 0 0 1 &amp;intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 0 2 &amp;intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 0 3 &amp;intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				&lt;0 0 0 4 &amp;intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;gcc GCC_PCIE_1_AUX_CLK&gt;,</div><div class='add'>+			 &lt;&amp;gcc GCC_PCIE_1_CFG_AHB_CLK&gt;,</div><div class='add'>+			 &lt;&amp;gcc GCC_PCIE_1_MSTR_AXI_CLK&gt;,</div><div class='add'>+			 &lt;&amp;gcc GCC_PCIE_1_SLV_AXI_CLK&gt;,</div><div class='add'>+			 &lt;&amp;gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK&gt;;</div><div class='add'>+</div><div class='add'>+		clock-names = "aux",</div><div class='add'>+			      "cfg",</div><div class='add'>+			      "bus_master",</div><div class='add'>+			      "bus_slave",</div><div class='add'>+			      "slave_q2a";</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;gcc GCC_PCIE_1_AUX_CLK&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;19200000&gt;;</div><div class='add'>+</div><div class='add'>+		interconnects = &lt;&amp;pcie_anoc MASTER_PCIE_1 0 &amp;mc_virt SLAVE_EBI1 0&gt;,</div><div class='add'>+				&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;config_noc SLAVE_PCIE_1 0&gt;;</div><div class='add'>+		interconnect-names = "pcie-mem", "cpu-pcie";</div><div class='add'>+</div><div class='add'>+		iommu-map = &lt;0x0 &amp;pcie_smmu 0x0080 0x1&gt;,</div><div class='add'>+			    &lt;0x100 &amp;pcie_smmu 0x0081 0x1&gt;;</div><div class='add'>+</div><div class='add'>+		resets = &lt;&amp;gcc GCC_PCIE_1_BCR&gt;,</div><div class='add'>+			 &lt;&amp;gcc GCC_PCIE_1_LINK_DOWN_BCR&gt;;</div><div class='add'>+		reset-names = "pci",</div><div class='add'>+			      "link_down";</div><div class='add'>+</div><div class='add'>+		power-domains = &lt;&amp;gcc PCIE_1_GDSC&gt;;</div><div class='add'>+</div><div class='add'>+		phys = &lt;&amp;pcie1_phy&gt;;</div><div class='add'>+		phy-names = "pciephy";</div><div class='add'>+</div><div class='add'>+		eq-presets-8gts = /bits/ 16 &lt;0x5555 0x5555 0x5555 0x5555&gt;;</div><div class='add'>+		eq-presets-16gts = /bits/ 8 &lt;0x55 0x55 0x55 0x55&gt;;</div><div class='add'>+</div><div class='add'>+		status = "disabled";</div><div class='add'>+</div><div class='add'>+		pcie@0 {</div><div class='add'>+			device_type = "pci";</div><div class='add'>+			reg = &lt;0x0 0x0 0x0 0x0 0x0&gt;;</div><div class='add'>+			bus-range = &lt;0x01 0xff&gt;;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;3&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie1_ep: pcie-ep@1c10000 {</div><div class='add'>+		compatible = "qcom,sa8775p-pcie-ep";</div><div class='add'>+		reg = &lt;0x0 0x01c10000 0x0 0x3000&gt;,</div><div class='add'>+		      &lt;0x0 0x60000000 0x0 0xf20&gt;,</div><div class='add'>+		      &lt;0x0 0x60000f20 0x0 0xa8&gt;,</div><div class='add'>+		      &lt;0x0 0x60001000 0x0 0x4000&gt;,</div><div class='add'>+		      &lt;0x0 0x60200000 0x0 0x1fe00000&gt;,</div><div class='add'>+		      &lt;0x0 0x01c13000 0x0 0x1000&gt;,</div><div class='add'>+		      &lt;0x0 0x60005000 0x0 0x2000&gt;;</div><div class='add'>+		reg-names = "parf", "dbi", "elbi", "atu", "addr_space",</div><div class='add'>+			    "mmio", "dma";</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;gcc GCC_PCIE_1_AUX_CLK&gt;,</div><div class='add'>+			 &lt;&amp;gcc GCC_PCIE_1_CFG_AHB_CLK&gt;,</div><div class='add'>+			 &lt;&amp;gcc GCC_PCIE_1_MSTR_AXI_CLK&gt;,</div><div class='add'>+			 &lt;&amp;gcc GCC_PCIE_1_SLV_AXI_CLK&gt;,</div><div class='add'>+			 &lt;&amp;gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK&gt;;</div><div class='add'>+</div><div class='add'>+		clock-names = "aux",</div><div class='add'>+			      "cfg",</div><div class='add'>+			      "bus_master",</div><div class='add'>+			      "bus_slave",</div><div class='add'>+			      "slave_q2a";</div><div class='add'>+</div><div class='add'>+		interrupts = &lt;GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+			     &lt;GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-names = "global", "doorbell", "dma";</div><div class='add'>+</div><div class='add'>+		interconnects = &lt;&amp;pcie_anoc MASTER_PCIE_1 0 &amp;mc_virt SLAVE_EBI1 0&gt;,</div><div class='add'>+				&lt;&amp;gem_noc MASTER_APPSS_PROC 0 &amp;config_noc SLAVE_PCIE_1 0&gt;;</div><div class='add'>+		interconnect-names = "pcie-mem", "cpu-pcie";</div><div class='add'>+</div><div class='add'>+		dma-coherent;</div><div class='add'>+		iommus = &lt;&amp;pcie_smmu 0x80 0x7f&gt;;</div><div class='add'>+		resets = &lt;&amp;gcc GCC_PCIE_1_BCR&gt;;</div><div class='add'>+		reset-names = "core";</div><div class='add'>+		power-domains = &lt;&amp;gcc PCIE_1_GDSC&gt;;</div><div class='add'>+		phys = &lt;&amp;pcie1_phy&gt;;</div><div class='add'>+		phy-names = "pciephy";</div><div class='add'>+		num-lanes = &lt;4&gt;;</div><div class='add'>+		linux,pci-domain = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pcie1_phy: phy@1c14000 {</div><div class='add'>+		compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy";</div><div class='add'>+		reg = &lt;0x0 0x1c14000 0x0 0x4000&gt;;</div><div class='add'>+</div><div class='add'>+		clocks = &lt;&amp;gcc GCC_PCIE_1_PHY_AUX_CLK&gt;,</div><div class='add'>+			 &lt;&amp;gcc GCC_PCIE_1_CFG_AHB_CLK&gt;,</div><div class='add'>+			 &lt;&amp;gcc GCC_PCIE_CLKREF_EN&gt;,</div><div class='add'>+			 &lt;&amp;gcc GCC_PCIE_1_PHY_RCHNG_CLK&gt;,</div><div class='add'>+			 &lt;&amp;gcc GCC_PCIE_1_PIPE_CLK&gt;,</div><div class='add'>+			 &lt;&amp;gcc GCC_PCIE_1_PIPEDIV2_CLK&gt;;</div><div class='add'>+		clock-names = "aux",</div><div class='add'>+			      "cfg_ahb",</div><div class='add'>+			      "ref",</div><div class='add'>+			      "rchng",</div><div class='add'>+			      "pipe",</div><div class='add'>+			      "pipediv2";</div><div class='add'>+</div><div class='add'>+		assigned-clocks = &lt;&amp;gcc GCC_PCIE_1_PHY_RCHNG_CLK&gt;;</div><div class='add'>+		assigned-clock-rates = &lt;100000000&gt;;</div><div class='add'>+</div><div class='add'>+		resets = &lt;&amp;gcc GCC_PCIE_1_PHY_BCR&gt;;</div><div class='add'>+		reset-names = "phy";</div><div class='add'>+</div><div class='add'>+		#clock-cells = &lt;0&gt;;</div><div class='add'>+		clock-output-names = "pcie_1_pipe_clk";</div><div class='add'>+</div><div class='add'>+		#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		status = "disabled";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/monaco-evk.dts b/arch/arm64/boot/dts/qcom/monaco-evk.dts<br/>new file mode 100644<br/>index 000000000000..bb35893da73d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/monaco-evk.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/monaco-evk.dts</a></div><div class='hunk'>@@ -0,0 +1,509 @@</div><div class='add'>+// SPDX-License-Identifier: BSD-3-Clause</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/qcom,q6afe.h&gt;</div><div class='add'>+#include &lt;dt-bindings/regulator/qcom,rpmh-regulator.h&gt;</div><div class='add'>+</div><div class='add'>+#include "monaco.dtsi"</div><div class='add'>+#include "monaco-pmics.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Qualcomm Technologies, Inc. Monaco EVK";</div><div class='add'>+	compatible = "qcom,monaco-evk", "qcom,qcs8300";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		ethernet0 = &amp;ethernet0;</div><div class='add'>+		i2c1 = &amp;i2c1;</div><div class='add'>+		serial0 = &amp;uart7;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0:115200n8";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dmic: audio-codec-0 {</div><div class='add'>+		compatible = "dmic-codec";</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+		num-channels = &lt;1&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	max98357a: audio-codec-1 {</div><div class='add'>+		compatible = "maxim,max98357a";</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sound {</div><div class='add'>+		compatible = "qcom,qcs8275-sndcard";</div><div class='add'>+		model = "MONACO-EVK";</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;hs0_mi2s_active&gt;, &lt;&amp;mi2s1_active&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		hs0-mi2s-playback-dai-link {</div><div class='add'>+			link-name = "HS0 MI2S Playback";</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;max98357a&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cpu {</div><div class='add'>+				sound-dai = &lt;&amp;q6apmbedai PRIMARY_MI2S_RX&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			platform {</div><div class='add'>+				sound-dai = &lt;&amp;q6apm&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sec-mi2s-capture-dai-link {</div><div class='add'>+			link-name = "Secondary MI2S Capture";</div><div class='add'>+</div><div class='add'>+			codec {</div><div class='add'>+				sound-dai = &lt;&amp;dmic&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cpu {</div><div class='add'>+				sound-dai = &lt;&amp;q6apmbedai SECONDARY_MI2S_TX&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			platform {</div><div class='add'>+				sound-dai = &lt;&amp;q6apm&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;apps_rsc {</div><div class='add'>+	regulators-0 {</div><div class='add'>+		compatible = "qcom,pmm8654au-rpmh-regulators";</div><div class='add'>+		qcom,pmic-id = "a";</div><div class='add'>+</div><div class='add'>+		vreg_l3a: ldo3 {</div><div class='add'>+			regulator-name = "vreg_l3a";</div><div class='add'>+			regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+			regulator-allowed-modes = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l4a: ldo4 {</div><div class='add'>+			regulator-name = "vreg_l4a";</div><div class='add'>+			regulator-min-microvolt = &lt;880000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;912000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+			regulator-allowed-modes = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l5a: ldo5 {</div><div class='add'>+			regulator-name = "vreg_l5a";</div><div class='add'>+			regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+			regulator-allowed-modes = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l6a: ldo6 {</div><div class='add'>+			regulator-name = "vreg_l6a";</div><div class='add'>+			regulator-min-microvolt = &lt;880000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;912000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+			regulator-allowed-modes = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l7a: ldo7 {</div><div class='add'>+			regulator-name = "vreg_l7a";</div><div class='add'>+			regulator-min-microvolt = &lt;880000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;912000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+			regulator-allowed-modes = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l8a: ldo8 {</div><div class='add'>+			regulator-name = "vreg_l8a";</div><div class='add'>+			regulator-min-microvolt = &lt;2504000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;2960000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+			regulator-allowed-modes = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l9a: ldo9 {</div><div class='add'>+			regulator-name = "vreg_l9a";</div><div class='add'>+			regulator-min-microvolt = &lt;2970000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;3072000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+			regulator-allowed-modes = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	regulators-1 {</div><div class='add'>+		compatible = "qcom,pmm8654au-rpmh-regulators";</div><div class='add'>+		qcom,pmic-id = "c";</div><div class='add'>+</div><div class='add'>+		vreg_s5c: smps5 {</div><div class='add'>+			regulator-name = "vreg_s5c";</div><div class='add'>+			regulator-min-microvolt = &lt;1104000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1104000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l1c: ldo1 {</div><div class='add'>+			regulator-name = "vreg_l1c";</div><div class='add'>+			regulator-min-microvolt = &lt;300000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;512000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+			regulator-allowed-modes = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l2c: ldo2 {</div><div class='add'>+			regulator-name = "vreg_l2c";</div><div class='add'>+			regulator-min-microvolt = &lt;900000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;904000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+			regulator-allowed-modes = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l4c: ldo4 {</div><div class='add'>+			regulator-name = "vreg_l4c";</div><div class='add'>+			regulator-min-microvolt = &lt;1200000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1200000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+			regulator-allowed-modes = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l7c: ldo7 {</div><div class='add'>+			regulator-name = "vreg_l7c";</div><div class='add'>+			regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+			regulator-allowed-modes = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l8c: ldo8 {</div><div class='add'>+			regulator-name = "vreg_l8c";</div><div class='add'>+			regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+			regulator-allowed-modes = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		vreg_l9c: ldo9 {</div><div class='add'>+			regulator-name = "vreg_l9c";</div><div class='add'>+			regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+			regulator-initial-mode = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+			regulator-allow-set-load;</div><div class='add'>+			regulator-allowed-modes = &lt;RPMH_REGULATOR_MODE_HPM&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ethernet0 {</div><div class='add'>+	phy-mode = "2500base-x";</div><div class='add'>+	phy-handle = &lt;&amp;hsgmii_phy0&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl-0 = &lt;&amp;ethernet0_default&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	snps,mtl-rx-config = &lt;&amp;mtl_rx_setup&gt;;</div><div class='add'>+	snps,mtl-tx-config = &lt;&amp;mtl_tx_setup&gt;;</div><div class='add'>+	nvmem-cells = &lt;&amp;mac_addr0&gt;;</div><div class='add'>+	nvmem-cell-names = "mac-address";</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	mdio {</div><div class='add'>+		compatible = "snps,dwmac-mdio";</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		hsgmii_phy0: ethernet-phy@1c {</div><div class='add'>+			compatible = "ethernet-phy-id004d.d101";</div><div class='add'>+			reg = &lt;0x1c&gt;;</div><div class='add'>+			reset-gpios = &lt;&amp;tlmm 31 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			reset-assert-us = &lt;11000&gt;;</div><div class='add'>+			reset-deassert-us = &lt;70000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mtl_rx_setup: rx-queues-config {</div><div class='add'>+		snps,rx-queues-to-use = &lt;4&gt;;</div><div class='add'>+		snps,rx-sched-sp;</div><div class='add'>+</div><div class='add'>+		queue0 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,map-to-dma-channel = &lt;0x0&gt;;</div><div class='add'>+			snps,route-up;</div><div class='add'>+			snps,priority = &lt;0x1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue1 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+			snps,map-to-dma-channel = &lt;0x1&gt;;</div><div class='add'>+			snps,route-ptp;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue2 {</div><div class='add'>+			snps,avb-algorithm;</div><div class='add'>+			snps,map-to-dma-channel = &lt;0x2&gt;;</div><div class='add'>+			snps,route-avcp;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue3 {</div><div class='add'>+			snps,avb-algorithm;</div><div class='add'>+			snps,map-to-dma-channel = &lt;0x3&gt;;</div><div class='add'>+			snps,priority = &lt;0xc&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mtl_tx_setup: tx-queues-config {</div><div class='add'>+		snps,tx-queues-to-use = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+		queue0 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue1 {</div><div class='add'>+			snps,dcb-algorithm;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue2 {</div><div class='add'>+			snps,avb-algorithm;</div><div class='add'>+			snps,send_slope = &lt;0x1000&gt;;</div><div class='add'>+			snps,idle_slope = &lt;0x1000&gt;;</div><div class='add'>+			snps,high_credit = &lt;0x3e800&gt;;</div><div class='add'>+			snps,low_credit = &lt;0xffc18000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		queue3 {</div><div class='add'>+			snps,avb-algorithm;</div><div class='add'>+			snps,send_slope = &lt;0x1000&gt;;</div><div class='add'>+			snps,idle_slope = &lt;0x1000&gt;;</div><div class='add'>+			snps,high_credit = &lt;0x3e800&gt;;</div><div class='add'>+			snps,low_credit = &lt;0xffc18000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpi_dma0 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpi_dma1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;gpu_zap_shader {</div><div class='add'>+	firmware-name = "qcom/qcs8300/a623_zap.mbn";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c1 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;qup_i2c1_default&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	eeprom0: eeprom@50 {</div><div class='add'>+		compatible = "atmel,24c256";</div><div class='add'>+		reg = &lt;0x50&gt;;</div><div class='add'>+		pagesize = &lt;64&gt;;</div><div class='add'>+</div><div class='add'>+		nvmem-layout {</div><div class='add'>+			compatible = "fixed-layout";</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			mac_addr0: mac-addr@0 {</div><div class='add'>+				reg = &lt;0x0 0x6&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;i2c15 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;qup_i2c15_default&gt;;</div><div class='add'>+	pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	expander0: gpio@38 {</div><div class='add'>+		compatible = "ti,tca9538";</div><div class='add'>+		reg = &lt;0x38&gt;;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	expander1: gpio@39 {</div><div class='add'>+		compatible = "ti,tca9538";</div><div class='add'>+		reg = &lt;0x39&gt;;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	expander2: gpio@3a {</div><div class='add'>+		compatible = "ti,tca9538";</div><div class='add'>+		reg = &lt;0x3a&gt;;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	expander3: gpio@3b {</div><div class='add'>+		compatible = "ti,tca9538";</div><div class='add'>+		reg = &lt;0x3b&gt;;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	expander4: gpio@3c {</div><div class='add'>+		compatible = "ti,tca9538";</div><div class='add'>+		reg = &lt;0x3c&gt;;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	expander5: gpio@3d {</div><div class='add'>+		compatible = "ti,tca9538";</div><div class='add'>+		reg = &lt;0x3d&gt;;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	expander6: gpio@3e {</div><div class='add'>+		compatible = "ti,tca9538";</div><div class='add'>+		reg = &lt;0x3e&gt;;</div><div class='add'>+		#gpio-cells = &lt;2&gt;;</div><div class='add'>+		gpio-controller;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;iris {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qupv3_id_0 {</div><div class='add'>+	firmware-name = "qcom/qcs8300/qupv3fw.elf";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;qupv3_id_1 {</div><div class='add'>+	firmware-name = "qcom/qcs8300/qupv3fw.elf";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;remoteproc_adsp {</div><div class='add'>+	firmware-name = "qcom/qcs8300/adsp.mbn";</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;remoteproc_cdsp {</div><div class='add'>+	firmware-name = "qcom/qcs8300/cdsp0.mbn";</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;remoteproc_gpdsp {</div><div class='add'>+	firmware-name = "qcom/qcs8300/gpdsp0.mbn";</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;serdes0 {</div><div class='add'>+	phy-supply = &lt;&amp;vreg_l4a&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tlmm {</div><div class='add'>+	ethernet0_default: ethernet0-default-state {</div><div class='add'>+		ethernet0_mdc: ethernet0-mdc-pins {</div><div class='add'>+			pins = "gpio5";</div><div class='add'>+			function = "emac0_mdc";</div><div class='add'>+			drive-strength = &lt;16&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ethernet0_mdio: ethernet0-mdio-pins {</div><div class='add'>+			pins = "gpio6";</div><div class='add'>+			function = "emac0_mdio";</div><div class='add'>+			drive-strength = &lt;16&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	qup_i2c1_default: qup-i2c1-state {</div><div class='add'>+		pins = "gpio19", "gpio20";</div><div class='add'>+		function = "qup0_se1";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-pull-up;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	qup_i2c15_default: qup-i2c15-state {</div><div class='add'>+		pins = "gpio91", "gpio92";</div><div class='add'>+		function = "qup1_se7";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-pull-up;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;uart7 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ufs_mem_hc {</div><div class='add'>+	reset-gpios = &lt;&amp;tlmm 133 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+	vcc-supply = &lt;&amp;vreg_l8a&gt;;</div><div class='add'>+	vcc-max-microamp = &lt;1100000&gt;;</div><div class='add'>+	vccq-supply = &lt;&amp;vreg_l4c&gt;;</div><div class='add'>+	vccq-max-microamp = &lt;1200000&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;ufs_mem_phy {</div><div class='add'>+	vdda-phy-supply = &lt;&amp;vreg_l4a&gt;;</div><div class='add'>+	vdda-pll-supply = &lt;&amp;vreg_l5a&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_1 {</div><div class='add'>+	dr_mode = "peripheral";</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_1_hsphy {</div><div class='add'>+	vdda-pll-supply = &lt;&amp;vreg_l7a&gt;;</div><div class='add'>+	vdda18-supply = &lt;&amp;vreg_l7c&gt;;</div><div class='add'>+	vdda33-supply = &lt;&amp;vreg_l9a&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_qmpphy {</div><div class='add'>+	vdda-phy-supply = &lt;&amp;vreg_l7a&gt;;</div><div class='add'>+	vdda-pll-supply = &lt;&amp;vreg_l5a&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/monaco-pmics.dtsi b/arch/arm64/boot/dts/qcom/monaco-pmics.dtsi<br/>new file mode 100644<br/>index 000000000000..e990d7367719<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/monaco-pmics.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/monaco-pmics.dtsi</a></div><div class='hunk'>@@ -0,0 +1,50 @@</div><div class='add'>+// SPDX-License-Identifier: BSD-3-Clause</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/spmi/spmi.h&gt;</div><div class='add'>+</div><div class='add'>+&amp;spmi_bus {</div><div class='add'>+	pmm8620au_0: pmic@0 {</div><div class='add'>+		compatible = "qcom,pmm8654au", "qcom,spmi-pmic";</div><div class='add'>+		reg = &lt;0x0 SPMI_USID&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		pmm8620au_0_rtc: rtc@6100 {</div><div class='add'>+			compatible = "qcom,pmk8350-rtc";</div><div class='add'>+			reg = &lt;0x6100&gt;, &lt;0x6200&gt;;</div><div class='add'>+			reg-names = "rtc", "alarm";</div><div class='add'>+			interrupts = &lt;0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmm8620au_0_gpios: gpio@8800 {</div><div class='add'>+			compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio";</div><div class='add'>+			reg = &lt;0x8800&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			gpio-ranges = &lt;&amp;pmm8620au_0_gpios 0 0 12&gt;;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmm8650au_1: pmic@2 {</div><div class='add'>+		compatible = "qcom,pmm8654au", "qcom,spmi-pmic";</div><div class='add'>+		reg = &lt;0x2 SPMI_USID&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		pmm8650au_1_gpios: gpio@8800 {</div><div class='add'>+			compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio";</div><div class='add'>+			reg = &lt;0x8800&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			gpio-ranges = &lt;&amp;pmm8650au_1_gpios 0 0 12&gt;;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi<br/>new file mode 100644<br/>index 000000000000..816fa2af8a9a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/monaco.dtsi?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/monaco.dtsi</a></div><div class='hunk'>@@ -0,0 +1,6230 @@</div><div class='add'>+// SPDX-License-Identifier: BSD-3-Clause</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,qcs8300-gcc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,rpmh.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,sa8775p-camcc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,sa8775p-dispcc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,sa8775p-gpucc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,sa8775p-videocc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/dma/qcom-gpi.h&gt;</div><div class='add'>+#include &lt;dt-bindings/firmware/qcom,scm.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interconnect/qcom,icc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interconnect/qcom,osm-l3.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interconnect/qcom,qcs8300-rpmh.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/arm-gic.h&gt;</div><div class='add'>+#include &lt;dt-bindings/mailbox/qcom-ipcc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/power/qcom,rpmhpd.h&gt;</div><div class='add'>+#include &lt;dt-bindings/power/qcom-rpmpd.h&gt;</div><div class='add'>+#include &lt;dt-bindings/soc/qcom,gpr.h&gt;</div><div class='add'>+#include &lt;dt-bindings/soc/qcom,rpmh-rsc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/thermal/thermal.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	interrupt-parent = &lt;&amp;intc&gt;;</div><div class='add'>+	#address-cells = &lt;2&gt;;</div><div class='add'>+	#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+	clocks {</div><div class='add'>+		xo_board_clk: xo-board-clk {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-frequency = &lt;38400000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sleep_clk: sleep-clk {</div><div class='add'>+			compatible = "fixed-clock";</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-frequency = &lt;32000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpus {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		cpu0: cpu@0 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a78c";</div><div class='add'>+			reg = &lt;0x0 0x0&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cpu_pd0&gt;;</div><div class='add'>+			power-domain-names = "psci";</div><div class='add'>+			capacity-dmips-mhz = &lt;1946&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;472&gt;;</div><div class='add'>+			qcom,freq-domain = &lt;&amp;cpufreq_hw 0&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu0_opp_table&gt;;</div><div class='add'>+			interconnects = &lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+					&lt;&amp;epss_l3_cl0 MASTER_EPSS_L3_APPS</div><div class='add'>+					 &amp;epss_l3_cl0 SLAVE_EPSS_L3_SHARED&gt;;</div><div class='add'>+</div><div class='add'>+			l2_0: l2-cache {</div><div class='add'>+				compatible = "cache";</div><div class='add'>+				cache-level = &lt;2&gt;;</div><div class='add'>+				cache-unified;</div><div class='add'>+				next-level-cache = &lt;&amp;l3_0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu1: cpu@100 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a78c";</div><div class='add'>+			reg = &lt;0x0 0x100&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_1&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cpu_pd1&gt;;</div><div class='add'>+			power-domain-names = "psci";</div><div class='add'>+			capacity-dmips-mhz = &lt;1946&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;472&gt;;</div><div class='add'>+			qcom,freq-domain = &lt;&amp;cpufreq_hw 0&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu0_opp_table&gt;;</div><div class='add'>+			interconnects = &lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+					&lt;&amp;epss_l3_cl0 MASTER_EPSS_L3_APPS</div><div class='add'>+					 &amp;epss_l3_cl0 SLAVE_EPSS_L3_SHARED&gt;;</div><div class='add'>+</div><div class='add'>+			l2_1: l2-cache {</div><div class='add'>+				compatible = "cache";</div><div class='add'>+				cache-level = &lt;2&gt;;</div><div class='add'>+				cache-unified;</div><div class='add'>+				next-level-cache = &lt;&amp;l3_0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu2: cpu@200 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a78c";</div><div class='add'>+			reg = &lt;0x0 0x200&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_2&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cpu_pd2&gt;;</div><div class='add'>+			power-domain-names = "psci";</div><div class='add'>+			capacity-dmips-mhz = &lt;1946&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;507&gt;;</div><div class='add'>+			qcom,freq-domain = &lt;&amp;cpufreq_hw 2&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu2_opp_table&gt;;</div><div class='add'>+			interconnects = &lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+					&lt;&amp;epss_l3_cl0 MASTER_EPSS_L3_APPS</div><div class='add'>+					 &amp;epss_l3_cl0 SLAVE_EPSS_L3_SHARED&gt;;</div><div class='add'>+</div><div class='add'>+			l2_2: l2-cache {</div><div class='add'>+				compatible = "cache";</div><div class='add'>+				cache-level = &lt;2&gt;;</div><div class='add'>+				cache-unified;</div><div class='add'>+				next-level-cache = &lt;&amp;l3_0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu3: cpu@300 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a78c";</div><div class='add'>+			reg = &lt;0x0 0x300&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_3&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cpu_pd3&gt;;</div><div class='add'>+			power-domain-names = "psci";</div><div class='add'>+			capacity-dmips-mhz = &lt;1946&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;507&gt;;</div><div class='add'>+			qcom,freq-domain = &lt;&amp;cpufreq_hw 2&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu2_opp_table&gt;;</div><div class='add'>+			interconnects = &lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+					&lt;&amp;epss_l3_cl0 MASTER_EPSS_L3_APPS</div><div class='add'>+					 &amp;epss_l3_cl0 SLAVE_EPSS_L3_SHARED&gt;;</div><div class='add'>+</div><div class='add'>+			l2_3: l2-cache {</div><div class='add'>+				compatible = "cache";</div><div class='add'>+				cache-level = &lt;2&gt;;</div><div class='add'>+				cache-unified;</div><div class='add'>+				next-level-cache = &lt;&amp;l3_0&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu4: cpu@10000 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x0 0x10000&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_4&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cpu_pd4&gt;;</div><div class='add'>+			power-domain-names = "psci";</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;100&gt;;</div><div class='add'>+			qcom,freq-domain = &lt;&amp;cpufreq_hw 1&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu4_opp_table&gt;;</div><div class='add'>+			interconnects = &lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+					&lt;&amp;epss_l3_cl1 MASTER_EPSS_L3_APPS</div><div class='add'>+					 &amp;epss_l3_cl1 SLAVE_EPSS_L3_SHARED&gt;;</div><div class='add'>+</div><div class='add'>+			l2_4: l2-cache {</div><div class='add'>+				compatible = "cache";</div><div class='add'>+				cache-level = &lt;2&gt;;</div><div class='add'>+				cache-unified;</div><div class='add'>+				next-level-cache = &lt;&amp;l3_1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu5: cpu@10100 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x0 0x10100&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_5&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cpu_pd5&gt;;</div><div class='add'>+			power-domain-names = "psci";</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;100&gt;;</div><div class='add'>+			qcom,freq-domain = &lt;&amp;cpufreq_hw 1&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu4_opp_table&gt;;</div><div class='add'>+			interconnects = &lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+					&lt;&amp;epss_l3_cl1 MASTER_EPSS_L3_APPS</div><div class='add'>+					 &amp;epss_l3_cl1 SLAVE_EPSS_L3_SHARED&gt;;</div><div class='add'>+</div><div class='add'>+			l2_5: l2-cache {</div><div class='add'>+				compatible = "cache";</div><div class='add'>+				cache-level = &lt;2&gt;;</div><div class='add'>+				cache-unified;</div><div class='add'>+				next-level-cache = &lt;&amp;l3_1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu6: cpu@10200 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x0 0x10200&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_6&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cpu_pd6&gt;;</div><div class='add'>+			power-domain-names = "psci";</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;100&gt;;</div><div class='add'>+			qcom,freq-domain = &lt;&amp;cpufreq_hw 1&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu4_opp_table&gt;;</div><div class='add'>+			interconnects = &lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+					&lt;&amp;epss_l3_cl1 MASTER_EPSS_L3_APPS</div><div class='add'>+					 &amp;epss_l3_cl1 SLAVE_EPSS_L3_SHARED&gt;;</div><div class='add'>+</div><div class='add'>+			l2_6: l2-cache {</div><div class='add'>+				compatible = "cache";</div><div class='add'>+				cache-level = &lt;2&gt;;</div><div class='add'>+				cache-unified;</div><div class='add'>+				next-level-cache = &lt;&amp;l3_1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu7: cpu@10300 {</div><div class='add'>+			device_type = "cpu";</div><div class='add'>+			compatible = "arm,cortex-a55";</div><div class='add'>+			reg = &lt;0x0 0x10300&gt;;</div><div class='add'>+			enable-method = "psci";</div><div class='add'>+			next-level-cache = &lt;&amp;l2_7&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cpu_pd7&gt;;</div><div class='add'>+			power-domain-names = "psci";</div><div class='add'>+			capacity-dmips-mhz = &lt;1024&gt;;</div><div class='add'>+			dynamic-power-coefficient = &lt;100&gt;;</div><div class='add'>+			qcom,freq-domain = &lt;&amp;cpufreq_hw 1&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu4_opp_table&gt;;</div><div class='add'>+			interconnects = &lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+					&lt;&amp;epss_l3_cl1 MASTER_EPSS_L3_APPS</div><div class='add'>+					 &amp;epss_l3_cl1 SLAVE_EPSS_L3_SHARED&gt;;</div><div class='add'>+</div><div class='add'>+			l2_7: l2-cache {</div><div class='add'>+				compatible = "cache";</div><div class='add'>+				cache-level = &lt;2&gt;;</div><div class='add'>+				cache-unified;</div><div class='add'>+				next-level-cache = &lt;&amp;l3_1&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu-map {</div><div class='add'>+			cluster0 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu0&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu2&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu3&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			cluster1 {</div><div class='add'>+				core0 {</div><div class='add'>+					cpu = &lt;&amp;cpu4&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core1 {</div><div class='add'>+					cpu = &lt;&amp;cpu5&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core2 {</div><div class='add'>+					cpu = &lt;&amp;cpu6&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				core3 {</div><div class='add'>+					cpu = &lt;&amp;cpu7&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l3_0: l3-cache-0 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;3&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		l3_1: l3-cache-1 {</div><div class='add'>+			compatible = "cache";</div><div class='add'>+			cache-level = &lt;3&gt;;</div><div class='add'>+			cache-unified;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		idle-states {</div><div class='add'>+			entry-method = "psci";</div><div class='add'>+</div><div class='add'>+			little_cpu_sleep_0: cpu-sleep-0-0 {</div><div class='add'>+				compatible = "arm,idle-state";</div><div class='add'>+				idle-state-name = "silver-power-collapse";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x40000003&gt;;</div><div class='add'>+				entry-latency-us = &lt;449&gt;;</div><div class='add'>+				exit-latency-us = &lt;801&gt;;</div><div class='add'>+				min-residency-us = &lt;1574&gt;;</div><div class='add'>+				local-timer-stop;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			little_cpu_sleep_1: cpu-sleep-0-1 {</div><div class='add'>+				compatible = "arm,idle-state";</div><div class='add'>+				idle-state-name = "silver-rail-power-collapse";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x40000004&gt;;</div><div class='add'>+				entry-latency-us = &lt;602&gt;;</div><div class='add'>+				exit-latency-us = &lt;961&gt;;</div><div class='add'>+				min-residency-us = &lt;4288&gt;;</div><div class='add'>+				local-timer-stop;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			big_cpu_sleep_0: cpu-sleep-1-0 {</div><div class='add'>+				compatible = "arm,idle-state";</div><div class='add'>+				idle-state-name = "gold-power-collapse";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x40000003&gt;;</div><div class='add'>+				entry-latency-us = &lt;549&gt;;</div><div class='add'>+				exit-latency-us = &lt;901&gt;;</div><div class='add'>+				min-residency-us = &lt;1774&gt;;</div><div class='add'>+				local-timer-stop;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			big_cpu_sleep_1: cpu-sleep-1-1 {</div><div class='add'>+				compatible = "arm,idle-state";</div><div class='add'>+				idle-state-name = "gold-rail-power-collapse";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x40000004&gt;;</div><div class='add'>+				entry-latency-us = &lt;702&gt;;</div><div class='add'>+				exit-latency-us = &lt;1061&gt;;</div><div class='add'>+				min-residency-us = &lt;4488&gt;;</div><div class='add'>+				local-timer-stop;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		domain-idle-states {</div><div class='add'>+			silver_cluster_sleep: cluster-sleep-0 {</div><div class='add'>+				compatible = "domain-idle-state";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x41000044&gt;;</div><div class='add'>+				entry-latency-us = &lt;2552&gt;;</div><div class='add'>+				exit-latency-us = &lt;2848&gt;;</div><div class='add'>+				min-residency-us = &lt;5908&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gold_cluster_sleep: cluster-sleep-1 {</div><div class='add'>+				compatible = "domain-idle-state";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x41000044&gt;;</div><div class='add'>+				entry-latency-us = &lt;2752&gt;;</div><div class='add'>+				exit-latency-us = &lt;3048&gt;;</div><div class='add'>+				min-residency-us = &lt;6118&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			system_sleep: domain-sleep {</div><div class='add'>+				compatible = "domain-idle-state";</div><div class='add'>+				arm,psci-suspend-param = &lt;0x42000144&gt;;</div><div class='add'>+				entry-latency-us = &lt;3263&gt;;</div><div class='add'>+				exit-latency-us = &lt;6562&gt;;</div><div class='add'>+				min-residency-us = &lt;9987&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpu0_opp_table: opp-table-cpu0 {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+		opp-shared;</div><div class='add'>+</div><div class='add'>+		opp-902400000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;902400000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(681600 * 4) (921600 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1017600000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1017600000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(1017600 * 4) (921600 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1190400000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1190400000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(1708800 * 4) (921600 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1267200000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1267200000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(2092800 * 4) (998400 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1344000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1344000000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(2092800 * 4) (1075200 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1420800000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1420800000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(2092800 * 4) (1152000 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1497600000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1497600000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(2092800 * 4) (1228800 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1574400000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1574400000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(2736000 * 4) (1324800 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1670400000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1670400000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(2736000 * 4) (1401600 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1747200000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1747200000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(2736000 * 4) (1401600 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1824000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1824000000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(2736000 * 4) (1478400 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1900800000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1900800000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(2736000 * 4) (1478400 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1977600000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1977600000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(3196800 * 4) (1555200 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-2054400000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2054400000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(3196800 * 4) (1555200 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-2112000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2112000000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(3196800 * 4) (1612800 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpu2_opp_table: opp-table-cpu2 {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+		opp-shared;</div><div class='add'>+</div><div class='add'>+		opp-940800000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;940800000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(681600 * 4) (921600 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1094400000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1094400000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(1017600 * 4) (921600 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1267200000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1267200000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(1708800 * 4) (921600 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1344000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1344000000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(2092800 * 4) (998400 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1420800000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1420800000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(2092800 * 4) (998400 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1497600000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1497600000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(2092800 * 4) (1075200 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1574400000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1574400000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(2092800 * 4) (1152000 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1632000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1632000000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(2092800 * 4) (1228800 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1708800000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1708800000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(2736000 * 4) (1324800 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1804800000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1804800000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(2736000 * 4) (1324800 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1900800000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1900800000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(2736000 * 4) (1324800 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1977600000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1977600000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(2736000 * 4) (1401600 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-2054400000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2054400000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(2736000 * 4) (1478400 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-2131200000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2131200000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(3196800 * 4) (1555200 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-2208000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2208000000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(3196800 * 4) (1555200 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-2284800000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2284800000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(3196800 * 4) (1612800 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-2361600000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;2361600000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(3196800 * 4) (1612800 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	cpu4_opp_table: opp-table-cpu4 {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+		opp-shared;</div><div class='add'>+</div><div class='add'>+		opp-844800000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;844800000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(681600 * 4) (921600 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1113600000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1113600000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(1708800 * 4) (921600 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1209600000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1209600000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(2092800 * 4) (998400 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1305600000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1305600000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(2092800 * 4) (1075200 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1382400000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1382400000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(2092800 * 4) (1152000 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1459200000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1459200000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(2092800 * 4) (1228800 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1497600000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1497600000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(2736000 * 4) (1324800 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1574400000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1574400000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(2736000 * 4) (1324800 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1651200000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1651200000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(2736000 * 4) (1324800 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1728000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1728000000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(2736000 * 4) (1401600 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1804800000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1804800000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(2736000 * 4) (1478400 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1881600000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1881600000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(3196800 * 4) (1555200 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		opp-1958400000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;1958400000&gt;;</div><div class='add'>+			opp-peak-kBps = &lt;(3196800 * 4) (1612800 * 32)&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dummy_eud: dummy-sink {</div><div class='add'>+		compatible = "arm,coresight-dummy-sink";</div><div class='add'>+</div><div class='add'>+		in-ports {</div><div class='add'>+			port {</div><div class='add'>+				eud_in: endpoint {</div><div class='add'>+					remote-endpoint = &lt;&amp;swao_rep_out1&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	firmware {</div><div class='add'>+		scm: scm {</div><div class='add'>+			compatible = "qcom,scm-qcs8300", "qcom,scm";</div><div class='add'>+			qcom,dload-mode = &lt;&amp;tcsr 0x13000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	memory@80000000 {</div><div class='add'>+		device_type = "memory";</div><div class='add'>+		/* We expect the bootloader to fill in the size */</div><div class='add'>+		reg = &lt;0x0 0x80000000 0x0 0x0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	clk_virt: interconnect-0 {</div><div class='add'>+		compatible = "qcom,qcs8300-clk-virt";</div><div class='add'>+		#interconnect-cells = &lt;2&gt;;</div><div class='add'>+		qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mc_virt: interconnect-1 {</div><div class='add'>+		compatible = "qcom,qcs8300-mc-virt";</div><div class='add'>+		#interconnect-cells = &lt;2&gt;;</div><div class='add'>+		qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	qup_opp_table: opp-table-qup {</div><div class='add'>+		compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+		opp-120000000 {</div><div class='add'>+			opp-hz = /bits/ 64 &lt;120000000&gt;;</div><div class='add'>+			required-opps = &lt;&amp;rpmhpd_opp_svs_l1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu-a55 {</div><div class='add'>+		compatible = "arm,cortex-a55-pmu";</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pmu-a78 {</div><div class='add'>+		compatible = "arm,cortex-a78-pmu";</div><div class='add'>+		interrupts = &lt;GIC_PPI 7 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	psci {</div><div class='add'>+		compatible = "arm,psci-1.0";</div><div class='add'>+		method = "smc";</div><div class='add'>+</div><div class='add'>+		cpu_pd0: power-domain-cpu0 {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cluster_pd0&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;big_cpu_sleep_0 &amp;big_cpu_sleep_1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_pd1: power-domain-cpu1 {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cluster_pd0&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;big_cpu_sleep_0 &amp;big_cpu_sleep_1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_pd2: power-domain-cpu2 {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cluster_pd0&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;big_cpu_sleep_0 &amp;big_cpu_sleep_1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_pd3: power-domain-cpu3 {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cluster_pd0&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;big_cpu_sleep_0 &amp;big_cpu_sleep_1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_pd4: power-domain-cpu4 {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cluster_pd1&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;little_cpu_sleep_0 &amp;little_cpu_sleep_1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_pd5: power-domain-cpu5 {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cluster_pd1&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;little_cpu_sleep_0 &amp;little_cpu_sleep_1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_pd6: power-domain-cpu6 {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cluster_pd1&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;little_cpu_sleep_0 &amp;little_cpu_sleep_1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpu_pd7: power-domain-cpu7 {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;cluster_pd1&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;little_cpu_sleep_0 &amp;little_cpu_sleep_1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cluster_pd0: power-domain-cluster0 {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;system_pd&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;gold_cluster_sleep&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cluster_pd1: power-domain-cluster1 {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;system_pd&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;silver_cluster_sleep&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		system_pd: power-domain-system {</div><div class='add'>+			#power-domain-cells = &lt;0&gt;;</div><div class='add'>+			domain-idle-states = &lt;&amp;system_sleep&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+		ranges;</div><div class='add'>+</div><div class='add'>+		aop_image_mem: aop-image-region@90800000 {</div><div class='add'>+			reg = &lt;0x0 0x90800000 0x0 0x60000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aop_cmd_db_mem: aop-cmd-db-region@90860000 {</div><div class='add'>+			compatible = "qcom,cmd-db";</div><div class='add'>+			reg = &lt;0x0 0x90860000 0x0 0x20000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smem_mem: smem@90900000 {</div><div class='add'>+			compatible = "qcom,smem";</div><div class='add'>+			reg = &lt;0x0 0x90900000 0x0 0x200000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+			hwlocks = &lt;&amp;tcsr_mutex 3&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		lpass_machine_learning_mem: lpass-machine-learning-region@93b00000 {</div><div class='add'>+			reg = &lt;0x0 0x93b00000 0x0 0xf00000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap-region@94a00000 {</div><div class='add'>+			reg = &lt;0x0 0x94a00000 0x0 0x800000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		camera_mem: camera-region@95200000 {</div><div class='add'>+			reg = &lt;0x0 0x95200000 0x0 0x500000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		adsp_mem: adsp-region@95c00000 {</div><div class='add'>+			no-map;</div><div class='add'>+			reg = &lt;0x0 0x95c00000 0x0 0x1e00000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		q6_adsp_dtb_mem: q6-adsp-dtb-region@97a00000 {</div><div class='add'>+			reg = &lt;0x0 0x97a00000 0x0 0x80000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		q6_gpdsp_dtb_mem: q6-gpdsp-dtb-region@97a80000 {</div><div class='add'>+			reg = &lt;0x0 0x97a80000 0x0 0x80000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpdsp_mem: gpdsp-region@97b00000 {</div><div class='add'>+			reg = &lt;0x0 0x97b00000 0x0 0x1e00000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		q6_cdsp_dtb_mem: q6-cdsp-dtb-region@99900000 {</div><div class='add'>+			reg = &lt;0x0 0x99900000 0x0 0x80000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cdsp_mem: cdsp-region@99980000 {</div><div class='add'>+			reg = &lt;0x0 0x99980000 0x0 0x1e00000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu_microcode_mem: gpu-microcode-region@9b780000 {</div><div class='add'>+			reg = &lt;0x0 0x9b780000 0x0 0x2000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cvp_mem: cvp-region@9b782000 {</div><div class='add'>+			reg = &lt;0x0 0x9b782000 0x0 0x700000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		video_mem: video-region@9be82000 {</div><div class='add'>+			reg = &lt;0x0 0x9be82000 0x0 0x700000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	smp2p-adsp {</div><div class='add'>+		compatible = "qcom,smp2p";</div><div class='add'>+		interrupts-extended = &lt;&amp;ipcc IPCC_CLIENT_LPASS</div><div class='add'>+					     IPCC_MPROC_SIGNAL_SMP2P</div><div class='add'>+					     IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+		mboxes = &lt;&amp;ipcc IPCC_CLIENT_LPASS</div><div class='add'>+				IPCC_MPROC_SIGNAL_SMP2P&gt;;</div><div class='add'>+</div><div class='add'>+		qcom,smem = &lt;443&gt;, &lt;429&gt;;</div><div class='add'>+		qcom,local-pid = &lt;0&gt;;</div><div class='add'>+		qcom,remote-pid = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		smp2p_adsp_in: slave-kernel {</div><div class='add'>+			qcom,entry-name = "slave-kernel";</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smp2p_adsp_out: master-kernel {</div><div class='add'>+			qcom,entry-name = "master-kernel";</div><div class='add'>+			#qcom,smem-state-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	smp2p-cdsp {</div><div class='add'>+		compatible = "qcom,smp2p";</div><div class='add'>+		interrupts-extended = &lt;&amp;ipcc IPCC_CLIENT_CDSP</div><div class='add'>+					     IPCC_MPROC_SIGNAL_SMP2P</div><div class='add'>+					     IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+		mboxes = &lt;&amp;ipcc IPCC_CLIENT_CDSP</div><div class='add'>+				IPCC_MPROC_SIGNAL_SMP2P&gt;;</div><div class='add'>+</div><div class='add'>+		qcom,smem = &lt;94&gt;, &lt;432&gt;;</div><div class='add'>+		qcom,local-pid = &lt;0&gt;;</div><div class='add'>+		qcom,remote-pid = &lt;5&gt;;</div><div class='add'>+</div><div class='add'>+		smp2p_cdsp_in: slave-kernel {</div><div class='add'>+			qcom,entry-name = "slave-kernel";</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smp2p_cdsp_out: master-kernel {</div><div class='add'>+			qcom,entry-name = "master-kernel";</div><div class='add'>+			#qcom,smem-state-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	smp2p-gpdsp {</div><div class='add'>+		compatible = "qcom,smp2p";</div><div class='add'>+		interrupts-extended = &lt;&amp;ipcc IPCC_CLIENT_GPDSP0</div><div class='add'>+					     IPCC_MPROC_SIGNAL_SMP2P</div><div class='add'>+					     IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+		mboxes = &lt;&amp;ipcc IPCC_CLIENT_GPDSP0</div><div class='add'>+				IPCC_MPROC_SIGNAL_SMP2P&gt;;</div><div class='add'>+</div><div class='add'>+		qcom,smem = &lt;617&gt;, &lt;616&gt;;</div><div class='add'>+		qcom,local-pid = &lt;0&gt;;</div><div class='add'>+		qcom,remote-pid = &lt;17&gt;;</div><div class='add'>+</div><div class='add'>+		smp2p_gpdsp_in: slave-kernel {</div><div class='add'>+			qcom,entry-name = "slave-kernel";</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		smp2p_gpdsp_out: master-kernel {</div><div class='add'>+			qcom,entry-name = "master-kernel";</div><div class='add'>+			#qcom,smem-state-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	soc: soc@0 {</div><div class='add'>+		compatible = "simple-bus";</div><div class='add'>+		ranges = &lt;0 0 0 0 0x10 0&gt;;</div><div class='add'>+		#address-cells = &lt;2&gt;;</div><div class='add'>+		#size-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+		gcc: clock-controller@100000 {</div><div class='add'>+			compatible = "qcom,qcs8300-gcc";</div><div class='add'>+			reg = &lt;0x0 0x00100000 0x0 0xc7018&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;,</div><div class='add'>+				 &lt;&amp;sleep_clk&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ipcc: mailbox@408000 {</div><div class='add'>+			compatible = "qcom,qcs8300-ipcc", "qcom,ipcc";</div><div class='add'>+			reg = &lt;0x0 0x408000 0x0 0x1000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			#mbox-cells = &lt;2&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qfprom: efuse@784000 {</div><div class='add'>+			compatible = "qcom,qcs8300-qfprom", "qcom,qfprom";</div><div class='add'>+			reg = &lt;0x0 0x00784000 0x0 0x2410&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			gpu_speed_bin: gpu_speed_bin@240c {</div><div class='add'>+				reg = &lt;0x240c 0x1&gt;;</div><div class='add'>+				bits = &lt;0 8&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpi_dma0: dma-controller@900000 {</div><div class='add'>+			compatible = "qcom,qcs8300-gpi-dma", "qcom,sm6350-gpi-dma";</div><div class='add'>+			reg = &lt;0x0 0x900000 0x0 0x60000&gt;;</div><div class='add'>+			#dma-cells = &lt;3&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x416 0x0&gt;;</div><div class='add'>+			dma-channels = &lt;12&gt;;</div><div class='add'>+			dma-channel-mask = &lt;0xfff&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qupv3_id_0: geniqup@9c0000 {</div><div class='add'>+			compatible = "qcom,geni-se-qup";</div><div class='add'>+			reg = &lt;0x0 0x9c0000 0x0 0x2000&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_QUPV3_WRAP_0_M_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_QUPV3_WRAP_0_S_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "m-ahb",</div><div class='add'>+				      "s-ahb";</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x403 0x0&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			i2c0: i2c@980000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0x0 0x980000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S0_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c0_data_clk&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 0 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 0 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi0: spi@980000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0x0 0x980000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S0_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi0_data_clk&gt;, &lt;&amp;qup_spi0_cs&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 0 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 0 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart0: serial@980000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0x0 0x980000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S0_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart0_cts&gt;, &lt;&amp;qup_uart0_rts&gt;,</div><div class='add'>+					    &lt;&amp;qup_uart0_tx&gt;, &lt;&amp;qup_uart0_rx&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c1: i2c@984000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0x0 0x984000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S1_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c1_data_clk&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 1 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 1 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi1: spi@984000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0x0 0x984000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S1_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi1_data_clk&gt;, &lt;&amp;qup_spi1_cs&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 1 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 1 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart1: serial@984000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0x0 0x984000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S1_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart1_cts&gt;, &lt;&amp;qup_uart1_rts&gt;,</div><div class='add'>+					    &lt;&amp;qup_uart1_tx&gt;, &lt;&amp;qup_uart1_rx&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c2: i2c@988000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0x0 0x988000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S2_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c2_data_clk&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 2 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 2 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi2: spi@988000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0x0 0x988000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S2_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi2_data_clk&gt;, &lt;&amp;qup_spi2_cs&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 2 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 2 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart2: serial@988000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0x0 0x988000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S2_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart2_cts&gt;, &lt;&amp;qup_uart2_rts&gt;,</div><div class='add'>+					    &lt;&amp;qup_uart2_tx&gt;, &lt;&amp;qup_uart2_rx&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c3: i2c@98c000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0x0 0x98c000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S3_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c3_data_clk&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 3 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 3 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi3: spi@98c000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0x0 0x98c000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S3_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi3_data_clk&gt;, &lt;&amp;qup_spi3_cs&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 3 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 3 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart3: serial@98c000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0x0 0x98c000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S3_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart3_cts&gt;, &lt;&amp;qup_uart3_rts&gt;,</div><div class='add'>+					    &lt;&amp;qup_uart3_tx&gt;, &lt;&amp;qup_uart3_rx&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c4: i2c@990000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0x0 0x990000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S4_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c4_data_clk&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 4 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 4 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi4: spi@990000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0x0 0x990000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S4_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi4_data_clk&gt;, &lt;&amp;qup_spi4_cs&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 4 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 4 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart4: serial@990000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0x0 0x990000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S4_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart4_cts&gt;, &lt;&amp;qup_uart4_rts&gt;,</div><div class='add'>+					    &lt;&amp;qup_uart4_tx&gt;, &lt;&amp;qup_uart4_rx&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c5: i2c@994000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0x0 0x994000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S5_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c5_data_clk&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 5 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 5 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi5: spi@994000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0x0 0x994000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S5_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi5_data_clk&gt;, &lt;&amp;qup_spi5_cs&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 5 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 5 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart5: serial@994000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0x0 0x994000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S5_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart5_cts&gt;, &lt;&amp;qup_uart5_rts&gt;,</div><div class='add'>+					    &lt;&amp;qup_uart5_tx&gt;, &lt;&amp;qup_uart5_rx&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c6: i2c@998000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0x0 0x998000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S6_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c6_data_clk&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 6 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 6 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi6: spi@998000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0x0 0x998000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S6_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi6_data_clk&gt;, &lt;&amp;qup_spi6_cs&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma0 0 6 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma0 1 6 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart6: serial@998000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0x0 0x998000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S6_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart6_cts&gt;, &lt;&amp;qup_uart6_rts&gt;,</div><div class='add'>+					    &lt;&amp;qup_uart6_tx&gt;, &lt;&amp;qup_uart6_rx&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart7: serial@99c000 {</div><div class='add'>+				compatible = "qcom,geni-debug-uart";</div><div class='add'>+				reg = &lt;0x0 0x0099c000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP0_S7_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart7_tx&gt;, &lt;&amp;qup_uart7_rx&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpi_dma1: dma-controller@a00000 {</div><div class='add'>+			compatible = "qcom,qcs8300-gpi-dma", "qcom,sm6350-gpi-dma";</div><div class='add'>+			reg = &lt;0x0 0xa00000 0x0 0x60000&gt;;</div><div class='add'>+			#dma-cells = &lt;3&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x456 0x0&gt;;</div><div class='add'>+			dma-channels = &lt;12&gt;;</div><div class='add'>+			dma-channel-mask = &lt;0xfff&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qupv3_id_1: geniqup@ac0000 {</div><div class='add'>+			compatible = "qcom,geni-se-qup";</div><div class='add'>+			reg = &lt;0x0 0xac0000 0x0 0x2000&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_QUPV3_WRAP_1_M_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_QUPV3_WRAP_1_S_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "m-ahb",</div><div class='add'>+				      "s-ahb";</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x443 0x0&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			i2c8: i2c@a80000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0x0 0xa80000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S0_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c8_data_clk&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 0 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 0 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi8: spi@a80000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0x0 0xa80000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S0_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi8_data_clk&gt;, &lt;&amp;qup_spi8_cs&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 0 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 0 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart8: serial@a80000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0x0 0xa80000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S0_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart8_cts&gt;, &lt;&amp;qup_uart8_rts&gt;,</div><div class='add'>+					    &lt;&amp;qup_uart8_tx&gt;, &lt;&amp;qup_uart8_rx&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c9: i2c@a84000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0x0 0xa84000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S1_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c9_data_clk&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 1 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 1 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi9: spi@a84000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0x0 0xa84000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S1_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi9_data_clk&gt;, &lt;&amp;qup_spi9_cs&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 1 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 1 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart9: serial@a84000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0x0 0xa84000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S1_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart9_cts&gt;, &lt;&amp;qup_uart9_rts&gt;,</div><div class='add'>+					    &lt;&amp;qup_uart9_tx&gt;, &lt;&amp;qup_uart9_rx&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c10: i2c@a88000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0x0 0xa88000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S2_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c10_data_clk&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 2 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 2 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi10: spi@a88000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0x0 0xa88000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S2_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi10_data_clk&gt;, &lt;&amp;qup_spi10_cs&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 2 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 2 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart10: serial@a88000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0x0 0xa88000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S2_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart10_cts&gt;, &lt;&amp;qup_uart10_rts&gt;,</div><div class='add'>+					    &lt;&amp;qup_uart10_tx&gt;, &lt;&amp;qup_uart10_rx&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c11: i2c@a8c000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0x0 0xa8c000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S3_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c11_data_clk&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 3 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 3 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart11: serial@a8c000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0x0 0xa8c000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S3_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart11_tx&gt;, &lt;&amp;qup_uart11_rx&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c12: i2c@a90000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0x0 0xa90000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S4_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c12_data_clk&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 4 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 4 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi12: spi@a90000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0x0 0xa90000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S4_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi12_data_clk&gt;, &lt;&amp;qup_spi12_cs&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 4 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 4 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart12: serial@a90000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0x0 0xa90000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S4_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart12_cts&gt;, &lt;&amp;qup_uart12_rts&gt;,</div><div class='add'>+					    &lt;&amp;qup_uart12_tx&gt;, &lt;&amp;qup_uart12_rx&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c13: i2c@a94000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0x0 0xa94000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S5_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c13_data_clk&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 5 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 5 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi13: spi@a94000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0x0 0xa94000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S5_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi13_data_clk&gt;, &lt;&amp;qup_spi13_cs&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 5 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 5 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart13: serial@a94000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0x0 0xa94000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S5_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart13_cts&gt;, &lt;&amp;qup_uart13_rts&gt;,</div><div class='add'>+					    &lt;&amp;qup_uart13_tx&gt;, &lt;&amp;qup_uart13_rx&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c14: i2c@a98000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0x0 0xa98000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S6_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c14_data_clk&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 6 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 6 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi14: spi@a98000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0x0 0xa98000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S6_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi14_data_clk&gt;, &lt;&amp;qup_spi14_cs&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 6 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 6 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart14: serial@a98000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0x0 0xa98000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S6_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart14_cts&gt;, &lt;&amp;qup_uart14_rts&gt;,</div><div class='add'>+					    &lt;&amp;qup_uart14_tx&gt;, &lt;&amp;qup_uart14_rx&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			i2c15: i2c@a9c000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0x0 0xa9c000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S7_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c15_data_clk&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 7 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 7 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi15: spi@a9c000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0x0 0xa9c000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S7_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi15_data_clk&gt;, &lt;&amp;qup_spi15_cs&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma1 0 7 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma1 1 7 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart15: serial@a9c000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0x0 0xa9c000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP1_S7_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart15_cts&gt;, &lt;&amp;qup_uart15_rts&gt;,</div><div class='add'>+					    &lt;&amp;qup_uart15_tx&gt;, &lt;&amp;qup_uart15_rx&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpi_dma3: dma-controller@b00000 {</div><div class='add'>+			compatible = "qcom,qcs8300-gpi-dma", "qcom,sm6350-gpi-dma";</div><div class='add'>+			reg = &lt;0x0 0xb00000 0x0 0x60000&gt;;</div><div class='add'>+			#dma-cells = &lt;3&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x56 0x0&gt;;</div><div class='add'>+			dma-channels = &lt;4&gt;;</div><div class='add'>+			dma-channel-mask = &lt;0xf&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		qupv3_id_3: geniqup@bc0000 {</div><div class='add'>+			compatible = "qcom,geni-se-qup";</div><div class='add'>+			reg = &lt;0x0 0xbc0000 0x0 0x2000&gt;;</div><div class='add'>+			ranges;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_QUPV3_WRAP_3_M_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_QUPV3_WRAP_3_S_AHB_CLK&gt;;</div><div class='add'>+			clock-names = "m-ahb",</div><div class='add'>+				      "s-ahb";</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;2&gt;;</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x43 0x0&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			i2c16: i2c@b80000 {</div><div class='add'>+				compatible = "qcom,geni-i2c";</div><div class='add'>+				reg = &lt;0x0 0xb80000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP3_S0_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_i2c16_data_clk&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 830 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;aggre2_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config",</div><div class='add'>+						     "qup-memory";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma3 0 0 QCOM_GPI_I2C&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma3 1 0 QCOM_GPI_I2C&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			spi16: spi@b80000 {</div><div class='add'>+				compatible = "qcom,geni-spi";</div><div class='add'>+				reg = &lt;0x0 0xb80000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP3_S0_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_spi16_data_clk&gt;, &lt;&amp;qup_spi16_cs&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 830 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				dmas = &lt;&amp;gpi_dma3 0 0 QCOM_GPI_SPI&gt;,</div><div class='add'>+				       &lt;&amp;gpi_dma3 1 0 QCOM_GPI_SPI&gt;;</div><div class='add'>+				dma-names = "tx",</div><div class='add'>+					    "rx";</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			uart16: serial@b80000 {</div><div class='add'>+				compatible = "qcom,geni-uart";</div><div class='add'>+				reg = &lt;0x0 0xb80000 0x0 0x4000&gt;;</div><div class='add'>+				clocks = &lt;&amp;gcc GCC_QUPV3_WRAP3_S0_CLK&gt;;</div><div class='add'>+				clock-names = "se";</div><div class='add'>+				pinctrl-0 = &lt;&amp;qup_uart16_cts&gt;, &lt;&amp;qup_uart16_rts&gt;,</div><div class='add'>+					    &lt;&amp;qup_uart16_tx&gt;, &lt;&amp;qup_uart16_rx&gt;;</div><div class='add'>+				pinctrl-names = "default";</div><div class='add'>+				interrupts = &lt;GIC_SPI 830 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				interconnects = &lt;&amp;clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+						&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+						 &amp;config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+				interconnect-names = "qup-core",</div><div class='add'>+						     "qup-config";</div><div class='add'>+				power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;qup_opp_table&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rng: rng@10d2000 {</div><div class='add'>+			compatible = "qcom,qcs8300-trng", "qcom,trng";</div><div class='add'>+			reg = &lt;0x0 0x010d2000 0x0 0x1000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		config_noc: interconnect@14c0000 {</div><div class='add'>+			compatible = "qcom,qcs8300-config-noc";</div><div class='add'>+			reg = &lt;0x0 0x014c0000 0x0 0x13080&gt;;</div><div class='add'>+			#interconnect-cells = &lt;2&gt;;</div><div class='add'>+			qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		system_noc: interconnect@1680000 {</div><div class='add'>+			compatible = "qcom,qcs8300-system-noc";</div><div class='add'>+			reg = &lt;0x0 0x01680000 0x0 0x15080&gt;;</div><div class='add'>+			#interconnect-cells = &lt;2&gt;;</div><div class='add'>+			qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aggre1_noc: interconnect@16c0000 {</div><div class='add'>+			compatible = "qcom,qcs8300-aggre1-noc";</div><div class='add'>+			reg = &lt;0x0 0x016c0000 0x0 0x17080&gt;;</div><div class='add'>+			#interconnect-cells = &lt;2&gt;;</div><div class='add'>+			qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aggre2_noc: interconnect@1700000 {</div><div class='add'>+			compatible = "qcom,qcs8300-aggre2-noc";</div><div class='add'>+			reg = &lt;0x0 0x01700000 0x0 0x1a080&gt;;</div><div class='add'>+			#interconnect-cells = &lt;2&gt;;</div><div class='add'>+			qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie_anoc: interconnect@1760000 {</div><div class='add'>+			compatible = "qcom,qcs8300-pcie-anoc";</div><div class='add'>+			reg = &lt;0x0 0x01760000 0x0 0xc080&gt;;</div><div class='add'>+			#interconnect-cells = &lt;2&gt;;</div><div class='add'>+			qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpdsp_anoc: interconnect@1780000 {</div><div class='add'>+			compatible = "qcom,qcs8300-gpdsp-anoc";</div><div class='add'>+			reg = &lt;0x0 0x01780000 0x0 0xd080&gt;;</div><div class='add'>+			#interconnect-cells = &lt;2&gt;;</div><div class='add'>+			qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		mmss_noc: interconnect@17a0000 {</div><div class='add'>+			compatible = "qcom,qcs8300-mmss-noc";</div><div class='add'>+			reg = &lt;0x0 0x017a0000 0x0 0x40000&gt;;</div><div class='add'>+			#interconnect-cells = &lt;2&gt;;</div><div class='add'>+			qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ufs_mem_hc: ufs@1d84000 {</div><div class='add'>+			compatible = "qcom,qcs8300-ufshc", "qcom,ufshc", "jedec,ufs-2.0";</div><div class='add'>+			reg = &lt;0x0 0x01d84000 0x0 0x3000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			phys = &lt;&amp;ufs_mem_phy&gt;;</div><div class='add'>+			phy-names = "ufsphy";</div><div class='add'>+			lanes-per-direction = &lt;2&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+			resets = &lt;&amp;gcc GCC_UFS_PHY_BCR&gt;;</div><div class='add'>+			reset-names = "rst";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;gcc GCC_UFS_PHY_GDSC&gt;;</div><div class='add'>+			required-opps = &lt;&amp;rpmhpd_opp_nom&gt;;</div><div class='add'>+</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x100 0x0&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+					&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+					 &amp;config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+			interconnect-names = "ufs-ddr",</div><div class='add'>+					     "cpu-ufs";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_UFS_PHY_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_AGGRE_UFS_PHY_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_UFS_PHY_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_UFS_PHY_UNIPRO_CORE_CLK&gt;,</div><div class='add'>+				 &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK&gt;;</div><div class='add'>+			clock-names = "core_clk",</div><div class='add'>+				      "bus_aggr_clk",</div><div class='add'>+				      "iface_clk",</div><div class='add'>+				      "core_clk_unipro",</div><div class='add'>+				      "ref_clk",</div><div class='add'>+				      "tx_lane0_sync_clk",</div><div class='add'>+				      "rx_lane0_sync_clk",</div><div class='add'>+				      "rx_lane1_sync_clk";</div><div class='add'>+			freq-table-hz = &lt;75000000 300000000&gt;,</div><div class='add'>+					&lt;0 0&gt;,</div><div class='add'>+					&lt;0 0&gt;,</div><div class='add'>+					&lt;75000000 300000000&gt;,</div><div class='add'>+					&lt;0 0&gt;,</div><div class='add'>+					&lt;0 0&gt;,</div><div class='add'>+					&lt;0 0&gt;,</div><div class='add'>+					&lt;0 0&gt;;</div><div class='add'>+			qcom,ice = &lt;&amp;ice&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ufs_mem_phy: phy@1d87000 {</div><div class='add'>+			compatible = "qcom,qcs8300-qmp-ufs-phy", "qcom,sa8775p-qmp-ufs-phy";</div><div class='add'>+			reg = &lt;0x0 0x01d87000 0x0 0xe10&gt;;</div><div class='add'>+			/*</div><div class='add'>+			 * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It</div><div class='add'>+			 * enables the CXO clock to eDP *and* UFS PHY.</div><div class='add'>+			 */</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_UFS_PHY_PHY_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_EDP_REF_CLKREF_EN&gt;;</div><div class='add'>+			clock-names = "ref",</div><div class='add'>+				      "ref_aux",</div><div class='add'>+				      "qref";</div><div class='add'>+			power-domains = &lt;&amp;gcc GCC_UFS_PHY_GDSC&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;ufs_mem_hc 0&gt;;</div><div class='add'>+			reset-names = "ufsphy";</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cryptobam: dma-controller@1dc4000 {</div><div class='add'>+			compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";</div><div class='add'>+			reg = &lt;0x0 0x01dc4000 0x0 0x28000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#dma-cells = &lt;1&gt;;</div><div class='add'>+			qcom,ee = &lt;0&gt;;</div><div class='add'>+			qcom,controlled-remotely;</div><div class='add'>+			num-channels = &lt;20&gt;;</div><div class='add'>+			qcom,num-ees = &lt;4&gt;;</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x480 0x00&gt;,</div><div class='add'>+				 &lt;&amp;apps_smmu 0x481 0x00&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ice: crypto@1d88000 {</div><div class='add'>+			compatible = "qcom,qcs8300-inline-crypto-engine",</div><div class='add'>+				     "qcom,inline-crypto-engine";</div><div class='add'>+			reg = &lt;0x0 0x01d88000 0x0 0x18000&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_UFS_PHY_ICE_CORE_CLK&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tcsr_mutex: hwlock@1f40000 {</div><div class='add'>+			compatible = "qcom,tcsr-mutex";</div><div class='add'>+			reg = &lt;0x0 0x01f40000 0x0 0x20000&gt;;</div><div class='add'>+			#hwlock-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tcsr: syscon@1fc0000 {</div><div class='add'>+			compatible = "qcom,qcs8300-tcsr", "syscon";</div><div class='add'>+			reg = &lt;0x0 0x1fc0000 0x0 0x30000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		remoteproc_adsp: remoteproc@3000000 {</div><div class='add'>+			compatible = "qcom,qcs8300-adsp-pas", "qcom,sa8775p-adsp-pas";</div><div class='add'>+			reg = &lt;0x0 0x3000000 0x0 0x00100&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts-extended = &lt;&amp;pdc 6 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			interrupt-names = "wdog",</div><div class='add'>+					  "fatal",</div><div class='add'>+					  "ready",</div><div class='add'>+					  "handover",</div><div class='add'>+					  "stop-ack";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;;</div><div class='add'>+			clock-names = "xo";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;rpmhpd RPMHPD_LCX&gt;,</div><div class='add'>+					&lt;&amp;rpmhpd RPMHPD_LMX&gt;;</div><div class='add'>+			power-domain-names = "lcx",</div><div class='add'>+					     "lmx";</div><div class='add'>+</div><div class='add'>+			memory-region = &lt;&amp;adsp_mem&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,qmp = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,smem-states = &lt;&amp;smp2p_adsp_out 0&gt;;</div><div class='add'>+			qcom,smem-state-names = "stop";</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			remoteproc_adsp_glink: glink-edge {</div><div class='add'>+				interrupts-extended = &lt;&amp;ipcc IPCC_CLIENT_LPASS</div><div class='add'>+							     IPCC_MPROC_SIGNAL_GLINK_QMP</div><div class='add'>+							     IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				mboxes = &lt;&amp;ipcc IPCC_CLIENT_LPASS</div><div class='add'>+						IPCC_MPROC_SIGNAL_GLINK_QMP&gt;;</div><div class='add'>+</div><div class='add'>+				label = "lpass";</div><div class='add'>+				qcom,remote-pid = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+				fastrpc {</div><div class='add'>+					compatible = "qcom,fastrpc";</div><div class='add'>+					qcom,glink-channels = "fastrpcglink-apps-dsp";</div><div class='add'>+					label = "adsp";</div><div class='add'>+					memory-region = &lt;&amp;adsp_rpc_remote_heap_mem&gt;;</div><div class='add'>+					qcom,vmids = &lt;QCOM_SCM_VMID_LPASS</div><div class='add'>+						      QCOM_SCM_VMID_ADSP_HEAP&gt;;</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					compute-cb@3 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;3&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x2003 0x0&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@4 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;4&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x2004 0x0&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@5 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;5&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x2005 0x0&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				gpr {</div><div class='add'>+					compatible = "qcom,gpr";</div><div class='add'>+					qcom,glink-channels = "adsp_apps";</div><div class='add'>+					qcom,domain = &lt;GPR_DOMAIN_ID_ADSP&gt;;</div><div class='add'>+					qcom,intents = &lt;512 20&gt;;</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					q6apm: service@1 {</div><div class='add'>+						compatible = "qcom,q6apm";</div><div class='add'>+						reg = &lt;GPR_APM_MODULE_IID&gt;;</div><div class='add'>+						#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+						qcom,protection-domain = "avs/audio",</div><div class='add'>+									 "msm/adsp/audio_pd";</div><div class='add'>+</div><div class='add'>+						q6apmbedai: bedais {</div><div class='add'>+							compatible = "qcom,q6apm-lpass-dais";</div><div class='add'>+							#sound-dai-cells = &lt;1&gt;;</div><div class='add'>+						};</div><div class='add'>+</div><div class='add'>+						q6apmdai: dais {</div><div class='add'>+							compatible = "qcom,q6apm-dais";</div><div class='add'>+							iommus = &lt;&amp;apps_smmu 0x2001 0x0&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					q6prm: service@2 {</div><div class='add'>+						compatible = "qcom,q6prm";</div><div class='add'>+						reg = &lt;GPR_PRM_MODULE_IID&gt;;</div><div class='add'>+						qcom,protection-domain = "avs/audio",</div><div class='add'>+									 "msm/adsp/audio_pd";</div><div class='add'>+</div><div class='add'>+						q6prmcc: clock-controller {</div><div class='add'>+							compatible = "qcom,q6prm-lpass-clocks";</div><div class='add'>+							#clock-cells = &lt;2&gt;;</div><div class='add'>+						};</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		lpass_ag_noc: interconnect@3c40000 {</div><div class='add'>+			compatible = "qcom,qcs8300-lpass-ag-noc";</div><div class='add'>+			reg = &lt;0x0 0x03c40000 0x0 0x17200&gt;;</div><div class='add'>+			#interconnect-cells = &lt;2&gt;;</div><div class='add'>+			qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		stm@4002000 {</div><div class='add'>+			compatible = "arm,coresight-stm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x04002000 0x0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0x16280000 0x0 0x180000&gt;;</div><div class='add'>+			reg-names = "stm-base",</div><div class='add'>+				    "stm-stimulus-base";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					stm_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;funnel0_in7&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpda@4004000 {</div><div class='add'>+			compatible = "qcom,coresight-tpda", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x04004000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					qdss_tpda_in1: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;qdss_tpdm1_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					qdss_tpda_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;funnel0_in6&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@400f000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x0400f000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,cmb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,cmb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					qdss_tpdm1_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;qdss_tpda_in1&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		funnel@4041000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x04041000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@6 {</div><div class='add'>+					reg = &lt;6&gt;;</div><div class='add'>+</div><div class='add'>+					funnel0_in6: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;qdss_tpda_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@7 {</div><div class='add'>+					reg = &lt;7&gt;;</div><div class='add'>+</div><div class='add'>+					funnel0_in7: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;stm_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					funnel0_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;qdss_funnel_in0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		funnel@4042000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x04042000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@4 {</div><div class='add'>+					reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+					funnel1_in4: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;apss_funnel1_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@5 {</div><div class='add'>+					reg = &lt;5&gt;;</div><div class='add'>+</div><div class='add'>+					funnel1_in5: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlct0_funnel_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@6 {</div><div class='add'>+					reg = &lt;6&gt;;</div><div class='add'>+</div><div class='add'>+					funnel1_in6: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlmm_funnel_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@7 {</div><div class='add'>+					reg = &lt;7&gt;;</div><div class='add'>+</div><div class='add'>+					funnel1_in7: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlst_ch_funnel_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					funnel1_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;qdss_funnel_in1&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		funnel@4045000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x04045000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					qdss_funnel_in0: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;funnel0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					qdss_funnel_in1: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;funnel1_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					qdss_funnel_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;aoss_funnel_in7&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@4841000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x04841000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,cmb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,cmb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					prng_tpdm_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlct0_tpda_in19&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@4850000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x04850000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,cmb-element-bits = &lt;64&gt;;</div><div class='add'>+			qcom,cmb-msrs-num = &lt;32&gt;;</div><div class='add'>+			qcom,dsb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,dsb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					pimem_tpdm_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlct0_tpda_in25&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@4860000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x04860000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,dsb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,dsb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					dlst_ch_tpdm0_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlst_ch_tpda_in8&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpda@4864000 {</div><div class='add'>+			compatible = "qcom,coresight-tpda", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x04864000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@8 {</div><div class='add'>+					reg = &lt;8&gt;;</div><div class='add'>+</div><div class='add'>+					dlst_ch_tpda_in8: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlst_ch_tpdm0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					dlst_ch_tpda_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlst_ch_funnel_in0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		funnel@4865000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x04865000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					dlst_ch_funnel_in0: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlst_ch_tpda_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@4 {</div><div class='add'>+					reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+					dlst_ch_funnel_in4: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlst_funnel_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@6 {</div><div class='add'>+					reg = &lt;6&gt;;</div><div class='add'>+</div><div class='add'>+					dlst_ch_funnel_in6: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;gdsp_funnel_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					dlst_ch_funnel_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;funnel1_in7&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@4980000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x04980000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,dsb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,dsb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					turing2_tpdm_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;turing2_funnel_in0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		funnel@4983000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x04983000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				port {</div><div class='add'>+					turing2_funnel_in0: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;turing2_tpdm_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					turing2_funnel_out0: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;gdsp_tpda_in5&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@4ac0000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x04ac0000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,dsb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,dsb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					dlmm_tpdm0_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlmm_tpda_in27&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpda@4ac4000 {</div><div class='add'>+			compatible = "qcom,coresight-tpda", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x04ac4000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@1b {</div><div class='add'>+					reg = &lt;27&gt;;</div><div class='add'>+</div><div class='add'>+					dlmm_tpda_in27: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlmm_tpdm0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					dlmm_tpda_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlmm_funnel_in0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		funnel@4ac5000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x04ac5000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				port {</div><div class='add'>+					dlmm_funnel_in0: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlmm_tpda_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					dlmm_funnel_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;funnel1_in6&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@4ad0000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x04ad0000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,dsb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,dsb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					dlct0_tpdm0_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlct0_tpda_in26&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpda@4ad3000 {</div><div class='add'>+			compatible = "qcom,coresight-tpda", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x04ad3000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@13 {</div><div class='add'>+					reg = &lt;19&gt;;</div><div class='add'>+</div><div class='add'>+					dlct0_tpda_in19: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;prng_tpdm_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@19 {</div><div class='add'>+					reg = &lt;25&gt;;</div><div class='add'>+</div><div class='add'>+					dlct0_tpda_in25: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;pimem_tpdm_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1a {</div><div class='add'>+					reg = &lt;26&gt;;</div><div class='add'>+</div><div class='add'>+					dlct0_tpda_in26: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlct0_tpdm0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					dlct0_tpda_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlct0_funnel_in0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		funnel@4ad4000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x04ad4000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					dlct0_funnel_in0: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlct0_tpda_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@4 {</div><div class='add'>+					reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+					dlct0_funnel_in4: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ddr_funnel5_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					dlct0_funnel_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;funnel1_in5&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		funnel@4b04000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x04b04000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@6 {</div><div class='add'>+					reg = &lt;6&gt;;</div><div class='add'>+</div><div class='add'>+					aoss_funnel_in6: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;aoss_tpda_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@7 {</div><div class='add'>+					reg = &lt;7&gt;;</div><div class='add'>+</div><div class='add'>+					aoss_funnel_in7: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;qdss_funnel_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					aoss_funnel_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;etf0_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tmc_etf: tmc@4b05000 {</div><div class='add'>+			compatible = "arm,coresight-tmc", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x04b05000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				port {</div><div class='add'>+					etf0_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;aoss_funnel_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					etf0_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;swao_rep_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		replicator@4b06000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x04b06000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				port {</div><div class='add'>+					swao_rep_in: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;etf0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					swao_rep_out1: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;eud_in&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpda@4b08000 {</div><div class='add'>+			compatible = "qcom,coresight-tpda", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x04b08000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					aoss_tpda_in0: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;aoss_tpdm0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					aoss_tpda_in1: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;aoss_tpdm1_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@2 {</div><div class='add'>+					reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+					aoss_tpda_in2: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;aoss_tpdm2_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@3 {</div><div class='add'>+					reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+					aoss_tpda_in3: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;aoss_tpdm3_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@4 {</div><div class='add'>+					reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+					aoss_tpda_in4: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;aoss_tpdm4_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					aoss_tpda_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;aoss_funnel_in6&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@4b09000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x04b09000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,cmb-element-bits = &lt;64&gt;;</div><div class='add'>+			qcom,cmb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					aoss_tpdm0_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;aoss_tpda_in0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@4b0a000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x04b0a000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,cmb-element-bits = &lt;64&gt;;</div><div class='add'>+			qcom,cmb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					aoss_tpdm1_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;aoss_tpda_in1&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@4b0b000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x04b0b000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,cmb-element-bits = &lt;64&gt;;</div><div class='add'>+			qcom,cmb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					aoss_tpdm2_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;aoss_tpda_in2&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@4b0c000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x04b0c000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,cmb-element-bits = &lt;64&gt;;</div><div class='add'>+			qcom,cmb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					aoss_tpdm3_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;aoss_tpda_in3&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@4b0d000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x04b0d000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,dsb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,dsb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					aoss_tpdm4_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;aoss_tpda_in4&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cti@4b13000 {</div><div class='add'>+			compatible = "arm,coresight-cti", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x04b13000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@4b80000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x04b80000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,dsb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,dsb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					turing0_tpdm0_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;turing0_tpda_in0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpda@4b86000 {</div><div class='add'>+			compatible = "qcom,coresight-tpda", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x04b86000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				port {</div><div class='add'>+					turing0_tpda_in0: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;turing0_tpdm0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					turing0_tpda_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;turing0_funnel_in0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		funnel@4b87000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x04b87000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				port {</div><div class='add'>+					turing0_funnel_in0: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;turing0_tpda_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					turing0_funnel_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;gdsp_funnel_in4&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cti@4b8b000 {</div><div class='add'>+			compatible = "arm,coresight-cti", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x04b8b000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@4c40000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x04c40000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,dsb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,dsb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					gdsp_tpdm0_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;gdsp_tpda_in8&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpda@4c44000 {</div><div class='add'>+			compatible = "qcom,coresight-tpda", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x04c44000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@5 {</div><div class='add'>+					reg = &lt;5&gt;;</div><div class='add'>+</div><div class='add'>+					gdsp_tpda_in5: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;turing2_funnel_out0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@8 {</div><div class='add'>+					reg = &lt;8&gt;;</div><div class='add'>+</div><div class='add'>+					gdsp_tpda_in8: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;gdsp_tpdm0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					gdsp_tpda_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;gdsp_funnel_in0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		funnel@4c45000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x04c45000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					gdsp_funnel_in0: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;gdsp_tpda_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@4 {</div><div class='add'>+					reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+					gdsp_funnel_in4: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;turing0_funnel_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					gdsp_funnel_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlst_ch_funnel_in6&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@4c50000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x04c50000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,dsb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,dsb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					dlst_tpdm0_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlst_tpda_in8&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpda@4c54000 {</div><div class='add'>+			compatible = "qcom,coresight-tpda", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x04c54000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@8 {</div><div class='add'>+					reg = &lt;8&gt;;</div><div class='add'>+</div><div class='add'>+					dlst_tpda_in8: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlst_tpdm0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					dlst_tpda_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlst_funnel_in0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		funnel@4c55000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x04c55000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				port {</div><div class='add'>+					dlst_funnel_in0: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlst_tpda_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					dlst_funnel_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlst_ch_funnel_in4&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@4e00000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x04e00000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,dsb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,dsb-msrs-num = &lt;32&gt;;</div><div class='add'>+			qcom,cmb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,cmb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					ddr_tpdm3_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ddr_tpda_in4&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpda@4e03000 {</div><div class='add'>+			compatible = "qcom,coresight-tpda", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x04e03000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					ddr_tpda_in0: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ddr_funnel0_out0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					ddr_tpda_in1: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ddr_funnel1_out0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@4 {</div><div class='add'>+					reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+					ddr_tpda_in4: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ddr_tpdm3_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					ddr_tpda_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ddr_funnel5_in0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		funnel@4e04000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x04e04000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				port {</div><div class='add'>+					ddr_funnel5_in0: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ddr_tpda_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					ddr_funnel5_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;dlct0_funnel_in4&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@4e10000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x04e10000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,dsb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,dsb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					ddr_tpdm0_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ddr_funnel0_in0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		funnel@4e12000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x04e12000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				port {</div><div class='add'>+					ddr_funnel0_in0: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ddr_tpdm0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					ddr_funnel0_out0: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ddr_tpda_in0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@4e20000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x04e20000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,dsb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,dsb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					ddr_tpdm1_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ddr_funnel1_in0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		funnel@4e22000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x04e22000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				port {</div><div class='add'>+					ddr_funnel1_in0: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ddr_tpdm1_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					ddr_funnel1_out0: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;ddr_tpda_in1&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		etm@6040000 {</div><div class='add'>+			compatible = "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x06040000 0x0 0x1000&gt;;</div><div class='add'>+			cpu = &lt;&amp;cpu0&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			arm,coresight-loses-context-with-cpu;</div><div class='add'>+			qcom,skip-power-up;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					etm0_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;apss_funnel0_in0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		etm@6140000 {</div><div class='add'>+			compatible = "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x06140000 0x0 0x1000&gt;;</div><div class='add'>+			cpu = &lt;&amp;cpu1&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			arm,coresight-loses-context-with-cpu;</div><div class='add'>+			qcom,skip-power-up;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					etm1_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;apss_funnel0_in1&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		etm@6240000 {</div><div class='add'>+			compatible = "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x06240000 0x0 0x1000&gt;;</div><div class='add'>+			cpu = &lt;&amp;cpu2&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			arm,coresight-loses-context-with-cpu;</div><div class='add'>+			qcom,skip-power-up;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					etm2_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;apss_funnel0_in2&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		etm@6340000 {</div><div class='add'>+			compatible = "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x06340000 0x0 0x1000&gt;;</div><div class='add'>+			cpu = &lt;&amp;cpu3&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			arm,coresight-loses-context-with-cpu;</div><div class='add'>+			qcom,skip-power-up;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					etm3_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;apss_funnel0_in3&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		etm@6440000 {</div><div class='add'>+			compatible = "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x06440000 0x0 0x1000&gt;;</div><div class='add'>+			cpu = &lt;&amp;cpu4&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			arm,coresight-loses-context-with-cpu;</div><div class='add'>+			qcom,skip-power-up;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					etm4_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;apss_funnel0_in4&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		etm@6540000 {</div><div class='add'>+			compatible = "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x06540000 0x0 0x1000&gt;;</div><div class='add'>+			cpu = &lt;&amp;cpu5&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			arm,coresight-loses-context-with-cpu;</div><div class='add'>+			qcom,skip-power-up;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					etm5_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;apss_funnel0_in5&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		etm@6640000 {</div><div class='add'>+			compatible = "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x06640000 0x0 0x1000&gt;;</div><div class='add'>+			cpu = &lt;&amp;cpu6&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			arm,coresight-loses-context-with-cpu;</div><div class='add'>+			qcom,skip-power-up;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					etm6_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;apss_funnel0_in6&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		etm@6740000 {</div><div class='add'>+			compatible = "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x06740000 0x0 0x1000&gt;;</div><div class='add'>+			cpu = &lt;&amp;cpu7&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			arm,coresight-loses-context-with-cpu;</div><div class='add'>+			qcom,skip-power-up;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					etm7_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;apss_funnel0_in7&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		funnel@6800000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x06800000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					apss_funnel0_in0: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;etm0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					apss_funnel0_in1: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;etm1_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@2 {</div><div class='add'>+					reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+					apss_funnel0_in2: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;etm2_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@3 {</div><div class='add'>+					reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+					apss_funnel0_in3: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;etm3_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@4 {</div><div class='add'>+					reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+					apss_funnel0_in4: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;etm4_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@5 {</div><div class='add'>+					reg = &lt;5&gt;;</div><div class='add'>+</div><div class='add'>+					apss_funnel0_in5: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;etm5_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@6 {</div><div class='add'>+					reg = &lt;6&gt;;</div><div class='add'>+</div><div class='add'>+					apss_funnel0_in6: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;etm6_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@7 {</div><div class='add'>+					reg = &lt;7&gt;;</div><div class='add'>+</div><div class='add'>+					apss_funnel0_in7: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;etm7_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					apss_funnel0_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;apss_funnel1_in0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		funnel@6810000 {</div><div class='add'>+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x06810000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					apss_funnel1_in0: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;apss_funnel0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@3 {</div><div class='add'>+					reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+					apss_funnel1_in3: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;apss_tpda_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					apss_funnel1_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;funnel1_in4&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cti@682b000 {</div><div class='add'>+			compatible = "arm,coresight-cti", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x0682b000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@6860000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x06860000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,cmb-element-bits = &lt;64&gt;;</div><div class='add'>+			qcom,cmb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					apss_tpdm3_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;apss_tpda_in3&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@6861000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x06861000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,dsb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,dsb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					apss_tpdm4_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;apss_tpda_in4&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpda@6863000 {</div><div class='add'>+			compatible = "qcom,coresight-tpda", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x06863000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			in-ports {</div><div class='add'>+				#address-cells = &lt;1&gt;;</div><div class='add'>+				#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+				port@0 {</div><div class='add'>+					reg = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					apss_tpda_in0: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;apss_tpdm0_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@1 {</div><div class='add'>+					reg = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+					apss_tpda_in1: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;apss_tpdm1_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@2 {</div><div class='add'>+					reg = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+					apss_tpda_in2: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;apss_tpdm2_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@3 {</div><div class='add'>+					reg = &lt;3&gt;;</div><div class='add'>+</div><div class='add'>+					apss_tpda_in3: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;apss_tpdm3_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				port@4 {</div><div class='add'>+					reg = &lt;4&gt;;</div><div class='add'>+</div><div class='add'>+					apss_tpda_in4: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;apss_tpdm4_out&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					apss_tpda_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;apss_funnel1_in3&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@68a0000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x068a0000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,cmb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,cmb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					apss_tpdm1_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;apss_tpda_in1&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@68b0000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x068b0000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,cmb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,cmb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					apss_tpdm0_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;apss_tpda_in0&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tpdm@68c0000 {</div><div class='add'>+			compatible = "qcom,coresight-tpdm", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x068c0000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+</div><div class='add'>+			qcom,dsb-element-bits = &lt;32&gt;;</div><div class='add'>+			qcom,dsb-msrs-num = &lt;32&gt;;</div><div class='add'>+</div><div class='add'>+			out-ports {</div><div class='add'>+				port {</div><div class='add'>+					apss_tpdm2_out: endpoint {</div><div class='add'>+						remote-endpoint = &lt;&amp;apss_tpda_in2&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cti@68e0000 {</div><div class='add'>+			compatible = "arm,coresight-cti", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x068e0000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cti@68f0000 {</div><div class='add'>+			compatible = "arm,coresight-cti", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x068f0000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cti@6900000 {</div><div class='add'>+			compatible = "arm,coresight-cti", "arm,primecell";</div><div class='add'>+			reg = &lt;0x0 0x06900000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+			clock-names = "apb_pclk";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sdhc_1: mmc@87c4000 {</div><div class='add'>+			compatible = "qcom,qcs8300-sdhci", "qcom,sdhci-msm-v5";</div><div class='add'>+			reg = &lt;0x0 0x087c4000 0x0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0x087c5000 0x0 0x1000&gt;;</div><div class='add'>+			reg-names = "hc",</div><div class='add'>+				    "cqhci";</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "hc_irq",</div><div class='add'>+					  "pwr_irq";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_SDCC1_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_SDCC1_APPS_CLK&gt;,</div><div class='add'>+				 &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;;</div><div class='add'>+			clock-names = "iface",</div><div class='add'>+				      "core",</div><div class='add'>+				      "xo";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_SDCC1_BCR&gt;;</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;sdhc1_opp_table&gt;;</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x0 0x0&gt;;</div><div class='add'>+			interconnects = &lt;&amp;aggre1_noc MASTER_SDC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+					&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;config_noc SLAVE_SDC1 QCOM_ICC_TAG_ACTIVE_ONLY&gt;;</div><div class='add'>+			interconnect-names = "sdhc-ddr",</div><div class='add'>+					     "cpu-sdhc";</div><div class='add'>+</div><div class='add'>+			qcom,dll-config = &lt;0x000f64ee&gt;;</div><div class='add'>+			qcom,ddr-config = &lt;0x80040868&gt;;</div><div class='add'>+			supports-cqe;</div><div class='add'>+			dma-coherent;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			sdhc1_opp_table: opp-table {</div><div class='add'>+				compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+				opp-50000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;50000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_low_svs&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-100000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;100000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_svs&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-200000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;200000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_svs_l1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-384000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;384000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_nom&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_1_hsphy: phy@8904000 {</div><div class='add'>+			compatible = "qcom,qcs8300-usb-hs-phy",</div><div class='add'>+				     "qcom,usb-snps-hs-7nm-phy";</div><div class='add'>+			reg = &lt;0x0 0x08904000 0x0 0x400&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;;</div><div class='add'>+			clock-names = "ref";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_USB2_PHY_PRIM_BCR&gt;;</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_2_hsphy: phy@8906000 {</div><div class='add'>+			compatible = "qcom,qcs8300-usb-hs-phy",</div><div class='add'>+				     "qcom,usb-snps-hs-7nm-phy";</div><div class='add'>+			reg = &lt;0x0 0x08906000 0x0 0x400&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;;</div><div class='add'>+			clock-names = "ref";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_USB2_PHY_SEC_BCR&gt;;</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_qmpphy: phy@8907000 {</div><div class='add'>+			compatible = "qcom,qcs8300-qmp-usb3-uni-phy";</div><div class='add'>+			reg = &lt;0x0 0x08907000 0x0 0x2000&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_USB3_PRIM_PHY_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB_CLKREF_EN&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB3_PRIM_PHY_PIPE_CLK&gt;;</div><div class='add'>+			clock-names = "aux",</div><div class='add'>+				      "ref",</div><div class='add'>+				      "com_aux",</div><div class='add'>+				      "pipe";</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_USB3_PHY_PRIM_BCR&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB3PHY_PHY_PRIM_BCR&gt;;</div><div class='add'>+			reset-names = "phy", "phy_phy";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;gcc GCC_USB30_PRIM_GDSC&gt;;</div><div class='add'>+</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+			clock-output-names = "usb3_prim_phy_pipe_clk_src";</div><div class='add'>+</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		serdes0: phy@8909000 {</div><div class='add'>+			compatible = "qcom,qcs8300-dwmac-sgmii-phy", "qcom,sa8775p-dwmac-sgmii-phy";</div><div class='add'>+			reg = &lt;0x0 0x08909000 0x0 0x00000e10&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_SGMI_CLKREF_EN&gt;;</div><div class='add'>+			clock-names = "sgmi_ref";</div><div class='add'>+			#phy-cells = &lt;0&gt;;</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		refgen: regulator@891c000 {</div><div class='add'>+			compatible = "qcom,qcs8300-refgen-regulator",</div><div class='add'>+				     "qcom,sm8250-refgen-regulator";</div><div class='add'>+			reg = &lt;0x0 0x0891c000 0x0 0x84&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpu: gpu@3d00000 {</div><div class='add'>+			compatible = "qcom,adreno-623.0", "qcom,adreno";</div><div class='add'>+			reg = &lt;0x0 0x03d00000 0x0 0x40000&gt;,</div><div class='add'>+			      &lt;0x0 0x03d9e000 0x0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0x03d61000 0x0 0x800&gt;;</div><div class='add'>+			reg-names = "kgsl_3d0_reg_memory",</div><div class='add'>+				    "cx_mem",</div><div class='add'>+				    "cx_dbgc";</div><div class='add'>+			interrupts = &lt;GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			iommus = &lt;&amp;adreno_smmu 0 0xc00&gt;,</div><div class='add'>+				 &lt;&amp;adreno_smmu 1 0xc00&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;gpu_opp_table&gt;;</div><div class='add'>+			qcom,gmu = &lt;&amp;gmu&gt;;</div><div class='add'>+			interconnects = &lt;&amp;gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+			interconnect-names = "gfx-mem";</div><div class='add'>+			#cooling-cells = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			nvmem-cells = &lt;&amp;gpu_speed_bin&gt;;</div><div class='add'>+			nvmem-cell-names = "speed_bin";</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			gpu_zap_shader: zap-shader {</div><div class='add'>+				memory-region = &lt;&amp;gpu_microcode_mem&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			gpu_opp_table: opp-table {</div><div class='add'>+				compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+				opp-877000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;877000000&gt;;</div><div class='add'>+					opp-level = &lt;RPMH_REGULATOR_LEVEL_TURBO_L1&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;12484375&gt;;</div><div class='add'>+					opp-supported-hw = &lt;0x1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-780000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;780000000&gt;;</div><div class='add'>+					opp-level = &lt;RPMH_REGULATOR_LEVEL_TURBO&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;10687500&gt;;</div><div class='add'>+					opp-supported-hw = &lt;0x1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-599000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;599000000&gt;;</div><div class='add'>+					opp-level = &lt;RPMH_REGULATOR_LEVEL_NOM&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;8171875&gt;;</div><div class='add'>+					opp-supported-hw = &lt;0x3&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-479000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;479000000&gt;;</div><div class='add'>+					opp-level = &lt;RPMH_REGULATOR_LEVEL_SVS_L1&gt;;</div><div class='add'>+					opp-peak-kBps = &lt;5285156&gt;;</div><div class='add'>+					opp-supported-hw = &lt;0x3&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gmu: gmu@3d6a000 {</div><div class='add'>+			compatible = "qcom,adreno-gmu-623.0", "qcom,adreno-gmu";</div><div class='add'>+			reg = &lt;0x0 0x03d6a000 0x0 0x34000&gt;,</div><div class='add'>+			      &lt;0x0 0x03de0000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0x0b290000 0x0 0x10000&gt;;</div><div class='add'>+			reg-names = "gmu", "rscc", "gmu_pdc";</div><div class='add'>+			interrupts = &lt;GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "hfi", "gmu";</div><div class='add'>+			clocks = &lt;&amp;gpucc GPU_CC_CX_GMU_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gpucc GPU_CC_CXO_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_DDRSS_GPU_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_GPU_MEMNOC_GFX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gpucc GPU_CC_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gpucc GPU_CC_HUB_CX_INT_CLK&gt;;</div><div class='add'>+			clock-names = "gmu",</div><div class='add'>+				      "cxo",</div><div class='add'>+				      "axi",</div><div class='add'>+				      "memnoc",</div><div class='add'>+				      "ahb",</div><div class='add'>+				      "hub";</div><div class='add'>+			power-domains = &lt;&amp;gpucc GPU_CC_CX_GDSC&gt;,</div><div class='add'>+					&lt;&amp;gpucc GPU_CC_GX_GDSC&gt;;</div><div class='add'>+			power-domain-names = "cx",</div><div class='add'>+					     "gx";</div><div class='add'>+			iommus = &lt;&amp;adreno_smmu 5 0xc00&gt;;</div><div class='add'>+			operating-points-v2 = &lt;&amp;gmu_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+			gmu_opp_table: opp-table {</div><div class='add'>+				compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+				opp-500000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;500000000&gt;;</div><div class='add'>+					opp-level = &lt;RPMH_REGULATOR_LEVEL_SVS&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gpucc: clock-controller@3d90000 {</div><div class='add'>+			compatible = "qcom,qcs8300-gpucc";</div><div class='add'>+			reg = &lt;0x0 0x03d90000 0x0 0xa000&gt;;</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_GPU_GPLL0_CLK_SRC&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_GPU_GPLL0_DIV_CLK_SRC&gt;;</div><div class='add'>+			clock-names = "bi_tcxo",</div><div class='add'>+				      "gcc_gpu_gpll0_clk_src",</div><div class='add'>+				      "gcc_gpu_gpll0_div_clk_src";</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		adreno_smmu: iommu@3da0000 {</div><div class='add'>+			compatible = "qcom,qcs8300-smmu-500", "qcom,adreno-smmu",</div><div class='add'>+				     "qcom,smmu-500", "arm,mmu-500";</div><div class='add'>+			reg = &lt;0x0 0x3da0000 0x0 0x20000&gt;;</div><div class='add'>+			#iommu-cells = &lt;2&gt;;</div><div class='add'>+			#global-interrupts = &lt;2&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_GPU_MEMNOC_GFX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_GPU_SNOC_DVM_GFX_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gpucc GPU_CC_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gpucc GPU_CC_CX_GMU_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gpucc GPU_CC_HUB_CX_INT_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gpucc GPU_CC_HUB_AON_CLK&gt;;</div><div class='add'>+</div><div class='add'>+			clock-names = "gcc_gpu_memnoc_gfx_clk",</div><div class='add'>+				      "gcc_gpu_snoc_dvm_gfx_clk",</div><div class='add'>+				      "gpu_cc_ahb_clk",</div><div class='add'>+				      "gpu_cc_hlos1_vote_gpu_smmu_clk",</div><div class='add'>+				      "gpu_cc_cx_gmu_clk",</div><div class='add'>+				      "gpu_cc_hub_cx_int_clk",</div><div class='add'>+				      "gpu_cc_hub_aon_clk";</div><div class='add'>+			power-domains = &lt;&amp;gpucc GPU_CC_CX_GDSC&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmu@9091000 {</div><div class='add'>+			compatible = "qcom,qcs8300-llcc-bwmon", "qcom,sc7280-llcc-bwmon";</div><div class='add'>+			reg = &lt;0x0 0x9091000 0x0 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY&gt;;</div><div class='add'>+</div><div class='add'>+			operating-points-v2 = &lt;&amp;llcc_bwmon_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+			llcc_bwmon_opp_table: opp-table {</div><div class='add'>+				compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+				opp-0 {</div><div class='add'>+					opp-peak-kBps = &lt;762000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-1 {</div><div class='add'>+					opp-peak-kBps = &lt;1720000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-2 {</div><div class='add'>+					opp-peak-kBps = &lt;2086000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-3 {</div><div class='add'>+					opp-peak-kBps = &lt;2601000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-4 {</div><div class='add'>+					opp-peak-kBps = &lt;2929000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-5 {</div><div class='add'>+					opp-peak-kBps = &lt;5931000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-6 {</div><div class='add'>+					opp-peak-kBps = &lt;6515000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-7 {</div><div class='add'>+					opp-peak-kBps = &lt;7984000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-8 {</div><div class='add'>+					opp-peak-kBps = &lt;10437000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-9 {</div><div class='add'>+					opp-peak-kBps = &lt;12195000&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmu@90b5400 {</div><div class='add'>+			compatible = "qcom,qcs8300-cpu-bwmon", "qcom,sdm845-bwmon";</div><div class='add'>+			reg = &lt;0x0 0x90b5400 0x0 0x600&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interconnects = &lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY&gt;;</div><div class='add'>+</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu_bwmon_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+			cpu_bwmon_opp_table: opp-table {</div><div class='add'>+				compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+				opp-0 {</div><div class='add'>+					opp-peak-kBps = &lt;9155000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-1 {</div><div class='add'>+					opp-peak-kBps = &lt;12298000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-2 {</div><div class='add'>+					opp-peak-kBps = &lt;14236000&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-3 {</div><div class='add'>+					opp-peak-kBps = &lt;16265000&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pmu@90b6400 {</div><div class='add'>+			compatible = "qcom,qcs8300-cpu-bwmon", "qcom,sdm845-bwmon";</div><div class='add'>+			reg = &lt;0x0 0x90b6400 0x0 0x600&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interconnects = &lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY&gt;;</div><div class='add'>+</div><div class='add'>+			operating-points-v2 = &lt;&amp;cpu_bwmon_opp_table&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dc_noc: interconnect@90e0000 {</div><div class='add'>+			compatible = "qcom,qcs8300-dc-noc";</div><div class='add'>+			reg = &lt;0x0 0x090e0000 0x0 0x5080&gt;;</div><div class='add'>+			#interconnect-cells = &lt;2&gt;;</div><div class='add'>+			qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		gem_noc: interconnect@9100000 {</div><div class='add'>+			compatible = "qcom,qcs8300-gem-noc";</div><div class='add'>+			reg = &lt;0x0 0x9100000 0x0 0xf7080&gt;;</div><div class='add'>+			#interconnect-cells = &lt;2&gt;;</div><div class='add'>+			qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		llcc: system-cache-controller@9200000 {</div><div class='add'>+			compatible = "qcom,qcs8300-llcc";</div><div class='add'>+			reg = &lt;0x0 0x09200000 0x0 0x80000&gt;,</div><div class='add'>+			      &lt;0x0 0x09300000 0x0 0x80000&gt;,</div><div class='add'>+			      &lt;0x0 0x09400000 0x0 0x80000&gt;,</div><div class='add'>+			      &lt;0x0 0x09500000 0x0 0x80000&gt;,</div><div class='add'>+			      &lt;0x0 0x09a00000 0x0 0x80000&gt;;</div><div class='add'>+			reg-names = "llcc0_base",</div><div class='add'>+				    "llcc1_base",</div><div class='add'>+				    "llcc2_base",</div><div class='add'>+				    "llcc3_base",</div><div class='add'>+				    "llcc_broadcast_base";</div><div class='add'>+			interrupts = &lt;GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_1: usb@a600000 {</div><div class='add'>+			compatible = "qcom,qcs8300-dwc3", "qcom,snps-dwc3";</div><div class='add'>+			reg = &lt;0x0 0x0a600000 0x0 0xfc100&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB30_PRIM_MASTER_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_AGGRE_USB3_PRIM_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB30_PRIM_SLEEP_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB30_PRIM_MOCK_UTMI_CLK&gt;;</div><div class='add'>+			clock-names = "cfg_noc",</div><div class='add'>+				      "core",</div><div class='add'>+				      "iface",</div><div class='add'>+				      "sleep",</div><div class='add'>+				      "mock_utmi";</div><div class='add'>+</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_USB30_PRIM_MOCK_UTMI_CLK&gt;,</div><div class='add'>+					  &lt;&amp;gcc GCC_USB30_PRIM_MASTER_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;19200000&gt;, &lt;200000000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts-extended = &lt;&amp;intc GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;pdc 14 IRQ_TYPE_EDGE_BOTH&gt;,</div><div class='add'>+					      &lt;&amp;pdc 15 IRQ_TYPE_EDGE_BOTH&gt;,</div><div class='add'>+					      &lt;&amp;pdc 12 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "dwc_usb3",</div><div class='add'>+					  "pwr_event",</div><div class='add'>+					  "hs_phy_irq",</div><div class='add'>+					  "dp_hs_phy_irq",</div><div class='add'>+					  "dm_hs_phy_irq",</div><div class='add'>+					  "ss_phy_irq";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;gcc GCC_USB30_PRIM_GDSC&gt;;</div><div class='add'>+			required-opps = &lt;&amp;rpmhpd_opp_nom&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_USB30_PRIM_BCR&gt;;</div><div class='add'>+			interconnects = &lt;&amp;aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+					&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+					 &amp;config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+			interconnect-names = "usb-ddr", "apps-usb";</div><div class='add'>+</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x80 0x0&gt;;</div><div class='add'>+			phys = &lt;&amp;usb_1_hsphy&gt;, &lt;&amp;usb_qmpphy&gt;;</div><div class='add'>+			phy-names = "usb2-phy", "usb3-phy";</div><div class='add'>+			snps,dis_enblslpm_quirk;</div><div class='add'>+			snps,dis-u1-entry-quirk;</div><div class='add'>+			snps,dis-u2-entry-quirk;</div><div class='add'>+			snps,dis_u2_susphy_quirk;</div><div class='add'>+			snps,dis_u3_susphy_quirk;</div><div class='add'>+</div><div class='add'>+			wakeup-source;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		usb_2: usb@a400000 {</div><div class='add'>+			compatible = "qcom,qcs8300-dwc3", "qcom,snps-dwc3";</div><div class='add'>+			reg = &lt;0x0 0x0a400000 0x0 0xfc100&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB20_MASTER_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_AGGRE_USB2_PRIM_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB20_SLEEP_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_USB20_MOCK_UTMI_CLK&gt;;</div><div class='add'>+			clock-names = "cfg_noc",</div><div class='add'>+				      "core",</div><div class='add'>+				      "iface",</div><div class='add'>+				      "sleep",</div><div class='add'>+				      "mock_utmi";</div><div class='add'>+</div><div class='add'>+			assigned-clocks = &lt;&amp;gcc GCC_USB20_MOCK_UTMI_CLK&gt;,</div><div class='add'>+					  &lt;&amp;gcc GCC_USB20_MASTER_CLK&gt;;</div><div class='add'>+			assigned-clock-rates = &lt;19200000&gt;, &lt;120000000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts-extended = &lt;&amp;intc GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					      &lt;&amp;pdc 10 IRQ_TYPE_EDGE_BOTH&gt;,</div><div class='add'>+					      &lt;&amp;pdc 9 IRQ_TYPE_EDGE_BOTH&gt;;</div><div class='add'>+			interrupt-names = "dwc_usb3",</div><div class='add'>+					  "pwr_event",</div><div class='add'>+					  "hs_phy_irq",</div><div class='add'>+					  "dp_hs_phy_irq",</div><div class='add'>+					  "dm_hs_phy_irq";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;gcc GCC_USB20_PRIM_GDSC&gt;;</div><div class='add'>+			required-opps = &lt;&amp;rpmhpd_opp_nom&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_USB20_PRIM_BCR&gt;;</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;aggre1_noc MASTER_USB2 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;,</div><div class='add'>+					&lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+					 &amp;config_noc SLAVE_USB2 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+			interconnect-names = "usb-ddr", "apps-usb";</div><div class='add'>+</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x20 0x0&gt;;</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;usb_2_hsphy&gt;;</div><div class='add'>+			phy-names = "usb2-phy";</div><div class='add'>+			maximum-speed = "high-speed";</div><div class='add'>+</div><div class='add'>+			snps,dis-u1-entry-quirk;</div><div class='add'>+			snps,dis-u2-entry-quirk;</div><div class='add'>+			snps,dis_u2_susphy_quirk;</div><div class='add'>+			snps,dis_u3_susphy_quirk;</div><div class='add'>+			snps,dis_enblslpm_quirk;</div><div class='add'>+</div><div class='add'>+			qcom,select-utmi-as-pipe-clk;</div><div class='add'>+			wakeup-source;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		iris: video-codec@aa00000 {</div><div class='add'>+			compatible = "qcom,qcs8300-iris";</div><div class='add'>+</div><div class='add'>+			reg = &lt;0x0 0x0aa00000 0x0 0xf0000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;videocc VIDEO_CC_MVS0C_GDSC&gt;,</div><div class='add'>+					&lt;&amp;videocc VIDEO_CC_MVS0_GDSC&gt;,</div><div class='add'>+					&lt;&amp;rpmhpd RPMHPD_MX&gt;,</div><div class='add'>+					&lt;&amp;rpmhpd RPMHPD_MMCX&gt;;</div><div class='add'>+			power-domain-names = "venus",</div><div class='add'>+					     "vcodec0",</div><div class='add'>+					     "mxc",</div><div class='add'>+					     "mmcx";</div><div class='add'>+</div><div class='add'>+			operating-points-v2 = &lt;&amp;iris_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_VIDEO_AXI0_CLK&gt;,</div><div class='add'>+				 &lt;&amp;videocc VIDEO_CC_MVS0C_CLK&gt;,</div><div class='add'>+				 &lt;&amp;videocc VIDEO_CC_MVS0_CLK&gt;;</div><div class='add'>+			clock-names = "iface",</div><div class='add'>+				      "core",</div><div class='add'>+				      "vcodec0_core";</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY</div><div class='add'>+					 &amp;config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY&gt;,</div><div class='add'>+					&lt;&amp;mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+			interconnect-names = "cpu-cfg",</div><div class='add'>+					     "video-mem";</div><div class='add'>+</div><div class='add'>+			memory-region = &lt;&amp;video_mem&gt;;</div><div class='add'>+</div><div class='add'>+			resets = &lt;&amp;gcc GCC_VIDEO_AXI0_CLK_ARES&gt;;</div><div class='add'>+			reset-names = "bus";</div><div class='add'>+</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x0880 0x0400&gt;,</div><div class='add'>+				 &lt;&amp;apps_smmu 0x0887 0x0400&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			iris_opp_table: opp-table {</div><div class='add'>+				compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+				opp-366000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;366000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_svs_l1&gt;,</div><div class='add'>+							&lt;&amp;rpmhpd_opp_svs_l1&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-444000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;444000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_nom&gt;,</div><div class='add'>+							&lt;&amp;rpmhpd_opp_nom&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-533000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;533000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_turbo&gt;,</div><div class='add'>+							&lt;&amp;rpmhpd_opp_turbo&gt;;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				opp-560000000 {</div><div class='add'>+					opp-hz = /bits/ 64 &lt;560000000&gt;;</div><div class='add'>+					required-opps = &lt;&amp;rpmhpd_opp_turbo_l1&gt;,</div><div class='add'>+							&lt;&amp;rpmhpd_opp_turbo_l1&gt;;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		videocc: clock-controller@abf0000 {</div><div class='add'>+			compatible = "qcom,qcs8300-videocc";</div><div class='add'>+			reg = &lt;0x0 0x0abf0000 0x0 0x10000&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_VIDEO_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;,</div><div class='add'>+				 &lt;&amp;rpmhcc RPMH_CXO_CLK_A&gt;,</div><div class='add'>+				 &lt;&amp;sleep_clk&gt;;</div><div class='add'>+			power-domains = &lt;&amp;rpmhpd RPMHPD_MMCX&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		camcc: clock-controller@ade0000 {</div><div class='add'>+			compatible = "qcom,qcs8300-camcc";</div><div class='add'>+			reg = &lt;0x0 0x0ade0000 0x0 0x20000&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_CAMERA_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;,</div><div class='add'>+				 &lt;&amp;rpmhcc RPMH_CXO_CLK_A&gt;,</div><div class='add'>+				 &lt;&amp;sleep_clk&gt;;</div><div class='add'>+			power-domains = &lt;&amp;rpmhpd RPMHPD_MMCX&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		dispcc: clock-controller@af00000 {</div><div class='add'>+			compatible = "qcom,sa8775p-dispcc0";</div><div class='add'>+			reg = &lt;0x0 0x0af00000 0x0 0x20000&gt;;</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_DISP_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;,</div><div class='add'>+				 &lt;&amp;rpmhcc RPMH_CXO_CLK_A&gt;,</div><div class='add'>+				 &lt;&amp;sleep_clk&gt;,</div><div class='add'>+				 &lt;0&gt;, &lt;0&gt;, &lt;0&gt;, &lt;0&gt;,</div><div class='add'>+				 &lt;0&gt;, &lt;0&gt;, &lt;0&gt;, &lt;0&gt;;</div><div class='add'>+			power-domains = &lt;&amp;rpmhpd RPMHPD_MMCX&gt;;</div><div class='add'>+			#clock-cells = &lt;1&gt;;</div><div class='add'>+			#reset-cells = &lt;1&gt;;</div><div class='add'>+			#power-domain-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pdc: interrupt-controller@b220000 {</div><div class='add'>+			compatible = "qcom,qcs8300-pdc", "qcom,pdc";</div><div class='add'>+			reg = &lt;0x0 0xb220000 0x0 0x30000&gt;,</div><div class='add'>+			      &lt;0x0 0x17c000f0 0x0 0x64&gt;;</div><div class='add'>+			interrupt-parent = &lt;&amp;intc&gt;;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			qcom,pdc-ranges = &lt;0 480 40&gt;,</div><div class='add'>+					  &lt;40 140 14&gt;,</div><div class='add'>+					  &lt;54 263 1&gt;,</div><div class='add'>+					  &lt;55 306 4&gt;,</div><div class='add'>+					  &lt;59 312 3&gt;,</div><div class='add'>+					  &lt;62 374 2&gt;,</div><div class='add'>+					  &lt;64 434 2&gt;,</div><div class='add'>+					  &lt;66 438 2&gt;,</div><div class='add'>+					  &lt;70 520 1&gt;,</div><div class='add'>+					  &lt;73 523 1&gt;,</div><div class='add'>+					  &lt;118 568 6&gt;,</div><div class='add'>+					  &lt;124 609 3&gt;,</div><div class='add'>+					  &lt;159 638 1&gt;,</div><div class='add'>+					  &lt;160 720 3&gt;,</div><div class='add'>+					  &lt;169 728 30&gt;,</div><div class='add'>+					  &lt;199 416 2&gt;,</div><div class='add'>+					  &lt;201 449 1&gt;,</div><div class='add'>+					  &lt;202 89 1&gt;,</div><div class='add'>+					  &lt;203 451 1&gt;,</div><div class='add'>+					  &lt;204 462 1&gt;,</div><div class='add'>+					  &lt;205 264 1&gt;,</div><div class='add'>+					  &lt;206 579 1&gt;,</div><div class='add'>+					  &lt;207 653 1&gt;,</div><div class='add'>+					  &lt;208 656 1&gt;,</div><div class='add'>+					  &lt;209 659 1&gt;,</div><div class='add'>+					  &lt;210 122 1&gt;,</div><div class='add'>+					  &lt;211 699 1&gt;,</div><div class='add'>+					  &lt;212 705 1&gt;,</div><div class='add'>+					  &lt;213 450 1&gt;,</div><div class='add'>+					  &lt;214 643 2&gt;,</div><div class='add'>+					  &lt;216 646 5&gt;,</div><div class='add'>+					  &lt;221 390 5&gt;,</div><div class='add'>+					  &lt;226 700 2&gt;,</div><div class='add'>+					  &lt;228 440 1&gt;,</div><div class='add'>+					  &lt;229 663 1&gt;,</div><div class='add'>+					  &lt;230 524 2&gt;,</div><div class='add'>+					  &lt;232 612 3&gt;,</div><div class='add'>+					  &lt;235 723 5&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		aoss_qmp: power-management@c300000 {</div><div class='add'>+			compatible = "qcom,qcs8300-aoss-qmp", "qcom,aoss-qmp";</div><div class='add'>+			reg = &lt;0x0 0x0c300000 0x0 0x400&gt;;</div><div class='add'>+			interrupts-extended = &lt;&amp;ipcc IPCC_CLIENT_AOP</div><div class='add'>+					       IPCC_MPROC_SIGNAL_GLINK_QMP</div><div class='add'>+					       IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			mboxes = &lt;&amp;ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP&gt;;</div><div class='add'>+			#clock-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sram@c3f0000 {</div><div class='add'>+			compatible = "qcom,rpmh-stats";</div><div class='add'>+			reg = &lt;0x0 0x0c3f0000 0x0 0x400&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		spmi_bus: spmi@c440000 {</div><div class='add'>+			compatible = "qcom,spmi-pmic-arb";</div><div class='add'>+			reg = &lt;0x0 0x0c440000 0x0 0x1100&gt;,</div><div class='add'>+			      &lt;0x0 0x0c600000 0x0 0x2000000&gt;,</div><div class='add'>+			      &lt;0x0 0x0e600000 0x0 0x100000&gt;,</div><div class='add'>+			      &lt;0x0 0x0e700000 0x0 0xa0000&gt;,</div><div class='add'>+			      &lt;0x0 0x0c40a000 0x0 0x26000&gt;;</div><div class='add'>+			reg-names = "core",</div><div class='add'>+				    "chnls",</div><div class='add'>+				    "obsrvr",</div><div class='add'>+				    "intr",</div><div class='add'>+				    "cnfg";</div><div class='add'>+			qcom,channel = &lt;0&gt;;</div><div class='add'>+			qcom,ee = &lt;0&gt;;</div><div class='add'>+			interrupts-extended = &lt;&amp;pdc 1 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "periph_irq";</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;4&gt;;</div><div class='add'>+			#address-cells = &lt;2&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		tlmm: pinctrl@f100000 {</div><div class='add'>+			compatible = "qcom,qcs8300-tlmm";</div><div class='add'>+			reg = &lt;0x0 0x0f100000 0x0 0x300000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			gpio-controller;</div><div class='add'>+			#gpio-cells = &lt;2&gt;;</div><div class='add'>+			gpio-ranges = &lt;&amp;tlmm 0 0 134&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#interrupt-cells = &lt;2&gt;;</div><div class='add'>+			wakeup-parent = &lt;&amp;pdc&gt;;</div><div class='add'>+</div><div class='add'>+			hs0_mi2s_active: hs0-mi2s-active-state {</div><div class='add'>+				pins = "gpio106", "gpio107", "gpio108", "gpio109";</div><div class='add'>+				function = "hs0_mi2s";</div><div class='add'>+				drive-strength = &lt;8&gt;;</div><div class='add'>+				bias-disable;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			mi2s1_active: mi2s1-active-state {</div><div class='add'>+				data0-pins {</div><div class='add'>+					pins = "gpio100";</div><div class='add'>+					function = "mi2s1_data0";</div><div class='add'>+					drive-strength = &lt;8&gt;;</div><div class='add'>+					bias-disable;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				data1-pins {</div><div class='add'>+					pins = "gpio101";</div><div class='add'>+					function = "mi2s1_data1";</div><div class='add'>+					drive-strength = &lt;8&gt;;</div><div class='add'>+					bias-disable;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				sclk-pins {</div><div class='add'>+					pins = "gpio98";</div><div class='add'>+					function = "mi2s1_sck";</div><div class='add'>+					drive-strength = &lt;8&gt;;</div><div class='add'>+					bias-disable;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				ws-pins {</div><div class='add'>+					pins = "gpio99";</div><div class='add'>+					function = "mi2s1_ws";</div><div class='add'>+					drive-strength = &lt;8&gt;;</div><div class='add'>+					bias-disable;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c0_data_clk: qup-i2c0-data-clk-state {</div><div class='add'>+				pins = "gpio17", "gpio18";</div><div class='add'>+				function = "qup0_se0";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c1_data_clk: qup-i2c1-data-clk-state {</div><div class='add'>+				pins = "gpio19", "gpio20";</div><div class='add'>+				function = "qup0_se1";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c2_data_clk: qup-i2c2-data-clk-state {</div><div class='add'>+				pins = "gpio33", "gpio34";</div><div class='add'>+				function = "qup0_se2";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c3_data_clk: qup-i2c3-data-clk-state {</div><div class='add'>+				pins = "gpio25", "gpio26";</div><div class='add'>+				function = "qup0_se3";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c4_data_clk: qup-i2c4-data-clk-state {</div><div class='add'>+				pins = "gpio29", "gpio30";</div><div class='add'>+				function = "qup0_se4";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c5_data_clk: qup-i2c5-data-clk-state {</div><div class='add'>+				pins = "gpio21", "gpio22";</div><div class='add'>+				function = "qup0_se5";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c6_data_clk: qup-i2c6-data-clk-state {</div><div class='add'>+				pins = "gpio80", "gpio81";</div><div class='add'>+				function = "qup0_se6";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c8_data_clk: qup-i2c8-data-clk-state {</div><div class='add'>+				pins = "gpio37", "gpio38";</div><div class='add'>+				function = "qup1_se0";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c9_data_clk: qup-i2c9-data-clk-state {</div><div class='add'>+				pins = "gpio39", "gpio40";</div><div class='add'>+				function = "qup1_se1";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c10_data_clk: qup-i2c10-data-clk-state {</div><div class='add'>+				pins = "gpio84", "gpio85";</div><div class='add'>+				function = "qup1_se2";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c11_data_clk: qup-i2c11-data-clk-state {</div><div class='add'>+				pins = "gpio41", "gpio42";</div><div class='add'>+				function = "qup1_se3";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c12_data_clk: qup-i2c12-data-clk-state {</div><div class='add'>+				pins = "gpio45", "gpio46";</div><div class='add'>+				function = "qup1_se4";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c13_data_clk: qup-i2c13-data-clk-state {</div><div class='add'>+				pins = "gpio49", "gpio50";</div><div class='add'>+				function = "qup1_se5";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c14_data_clk: qup-i2c14-data-clk-state {</div><div class='add'>+				pins = "gpio89", "gpio90";</div><div class='add'>+				function = "qup1_se6";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c15_data_clk: qup-i2c15-data-clk-state {</div><div class='add'>+				pins = "gpio91", "gpio92";</div><div class='add'>+				function = "qup1_se7";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_i2c16_data_clk: qup-i2c16-data-clk-state {</div><div class='add'>+				pins = "gpio10", "gpio11";</div><div class='add'>+				function = "qup2_se0";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi0_data_clk: qup-spi0-data-clk-state {</div><div class='add'>+				pins = "gpio17", "gpio18", "gpio19";</div><div class='add'>+				function = "qup0_se0";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi0_cs: qup-spi0-cs-state {</div><div class='add'>+				pins = "gpio20";</div><div class='add'>+				function = "qup0_se0";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {</div><div class='add'>+				pins = "gpio20";</div><div class='add'>+				function = "gpio";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi1_data_clk: qup-spi1-data-clk-state {</div><div class='add'>+				pins = "gpio19", "gpio20", "gpio17";</div><div class='add'>+				function = "qup0_se1";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi1_cs: qup-spi1-cs-state {</div><div class='add'>+				pins = "gpio18";</div><div class='add'>+				function = "qup0_se1";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {</div><div class='add'>+				pins = "gpio18";</div><div class='add'>+				function = "gpio";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi2_data_clk: qup-spi2-data-clk-state {</div><div class='add'>+				pins = "gpio33", "gpio34", "gpio35";</div><div class='add'>+				function = "qup0_se2";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi2_cs: qup-spi2-cs-state {</div><div class='add'>+				pins = "gpio36";</div><div class='add'>+				function = "qup0_se2";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi2_cs_gpio: qup-spi2-cs-gpio-state {</div><div class='add'>+				pins = "gpio36";</div><div class='add'>+				function = "gpio";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi3_data_clk: qup-spi3-data-clk-state {</div><div class='add'>+				pins = "gpio25", "gpio26", "gpio27";</div><div class='add'>+				function = "qup0_se3";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi3_cs: qup-spi3-cs-state {</div><div class='add'>+				pins = "gpio28";</div><div class='add'>+				function = "qup0_se3";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {</div><div class='add'>+				pins = "gpio28";</div><div class='add'>+				function = "gpio";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi4_data_clk: qup-spi4-data-clk-state {</div><div class='add'>+				pins = "gpio29", "gpio30", "gpio31";</div><div class='add'>+				function = "qup0_se4";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi4_cs: qup-spi4-cs-state {</div><div class='add'>+				pins = "gpio32";</div><div class='add'>+				function = "qup0_se4";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi4_cs_gpio: qup-spi4-cs-gpio-state {</div><div class='add'>+				pins = "gpio32";</div><div class='add'>+				function = "gpio";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi5_data_clk: qup-spi5-data-clk-state {</div><div class='add'>+				pins = "gpio21", "gpio22", "gpio23";</div><div class='add'>+				function = "qup0_se5";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi5_cs: qup-spi5-cs-state {</div><div class='add'>+				pins = "gpio24";</div><div class='add'>+				function = "qup0_se5";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {</div><div class='add'>+				pins = "gpio24";</div><div class='add'>+				function = "gpio";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi6_data_clk: qup-spi6-data-clk-state {</div><div class='add'>+				pins = "gpio80", "gpio81", "gpio82";</div><div class='add'>+				function = "qup0_se6";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi6_cs: qup-spi6-cs-state {</div><div class='add'>+				pins = "gpio83";</div><div class='add'>+				function = "qup0_se6";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {</div><div class='add'>+				pins = "gpio83";</div><div class='add'>+				function = "gpio";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi8_data_clk: qup-spi8-data-clk-state {</div><div class='add'>+				pins = "gpio37", "gpio38", "gpio39";</div><div class='add'>+				function = "qup1_se0";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi8_cs: qup-spi8-cs-state {</div><div class='add'>+				pins = "gpio40";</div><div class='add'>+				function = "qup1_se0";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {</div><div class='add'>+				pins = "gpio40";</div><div class='add'>+				function = "gpio";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi9_data_clk: qup-spi9-data-clk-state {</div><div class='add'>+				pins = "gpio39", "gpio40", "gpio37";</div><div class='add'>+				function = "qup1_se1";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi9_cs: qup-spi9-cs-state {</div><div class='add'>+				pins = "gpio38";</div><div class='add'>+				function = "qup1_se1";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi9_cs_gpio: qup-spi9-cs-gpio-state {</div><div class='add'>+				pins = "gpio38";</div><div class='add'>+				function = "gpio";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi10_data_clk: qup-spi10-data-clk-state {</div><div class='add'>+				pins = "gpio84", "gpio85", "gpio86";</div><div class='add'>+				function = "qup1_se2";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi10_cs: qup-spi10-cs-state {</div><div class='add'>+				pins = "gpio87";</div><div class='add'>+				function = "qup1_se2";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {</div><div class='add'>+				pins = "gpio87";</div><div class='add'>+				function = "gpio";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi12_data_clk: qup-spi12-data-clk-state {</div><div class='add'>+				pins = "gpio45", "gpio46", "gpio47";</div><div class='add'>+				function = "qup1_se4";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi12_cs: qup-spi12-cs-state {</div><div class='add'>+				pins = "gpio48";</div><div class='add'>+				function = "qup1_se4";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi12_cs_gpio: qup-spi12-cs-gpio-state {</div><div class='add'>+				pins = "gpio48";</div><div class='add'>+				function = "gpio";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi13_data_clk: qup-spi13-data-clk-state {</div><div class='add'>+				pins = "gpio49", "gpio50", "gpio51";</div><div class='add'>+				function = "qup1_se5";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi13_cs: qup-spi13-cs-state {</div><div class='add'>+				pins = "gpio52";</div><div class='add'>+				function = "qup1_se5";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi13_cs_gpio: qup-spi13-cs-gpio-state {</div><div class='add'>+				pins = "gpio52";</div><div class='add'>+				function = "gpio";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi14_data_clk: qup-spi14-data-clk-state {</div><div class='add'>+				pins = "gpio89", "gpio90", "gpio91";</div><div class='add'>+				function = "qup1_se6";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi14_cs: qup-spi14-cs-state {</div><div class='add'>+				pins = "gpio92";</div><div class='add'>+				function = "qup1_se6";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi14_cs_gpio: qup-spi14-cs-gpio-state {</div><div class='add'>+				pins = "gpio92";</div><div class='add'>+				function = "gpio";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi15_data_clk: qup-spi15-data-clk-state {</div><div class='add'>+				pins = "gpio91", "gpio92", "gpio89";</div><div class='add'>+				function = "qup1_se7";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi15_cs: qup-spi15-cs-state {</div><div class='add'>+				pins = "gpio90";</div><div class='add'>+				function = "qup1_se7";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi15_cs_gpio: qup-spi15-cs-gpio-state {</div><div class='add'>+				pins = "gpio90";</div><div class='add'>+				function = "gpio";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi16_data_clk: qup-spi16-data-clk-state {</div><div class='add'>+				pins = "gpio10", "gpio11", "gpio12";</div><div class='add'>+				function = "qup2_se0";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi16_cs: qup-spi16-cs-state {</div><div class='add'>+				pins = "gpio13";</div><div class='add'>+				function = "qup2_se0";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_spi16_cs_gpio: qup-spi16-cs-gpio-state {</div><div class='add'>+				pins = "gpio13";</div><div class='add'>+				function = "gpio";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart0_cts: qup-uart0-cts-state {</div><div class='add'>+				pins = "gpio17";</div><div class='add'>+				function = "qup0_se0";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart0_rts: qup-uart0-rts-state {</div><div class='add'>+				pins = "gpio18";</div><div class='add'>+				function = "qup0_se0";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart0_tx: qup-uart0-tx-state {</div><div class='add'>+				pins = "gpio19";</div><div class='add'>+				function = "qup0_se0";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart0_rx: qup-uart0-rx-state {</div><div class='add'>+				pins = "gpio20";</div><div class='add'>+				function = "qup0_se0";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart1_cts: qup-uart1-cts-state {</div><div class='add'>+				pins = "gpio19";</div><div class='add'>+				function = "qup0_se1";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart1_rts: qup-uart1-rts-state {</div><div class='add'>+				pins = "gpio20";</div><div class='add'>+				function = "qup0_se1";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart1_tx: qup-uart1-tx-state {</div><div class='add'>+				pins = "gpio17";</div><div class='add'>+				function = "qup0_se1";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart1_rx: qup-uart1-rx-state {</div><div class='add'>+				pins = "gpio18";</div><div class='add'>+				function = "qup0_se1";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart2_cts: qup-uart2-cts-state {</div><div class='add'>+				pins = "gpio33";</div><div class='add'>+				function = "qup0_se2";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart2_rts: qup-uart2-rts-state {</div><div class='add'>+				pins = "gpio34";</div><div class='add'>+				function = "qup0_se2";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart2_tx: qup-uart2-tx-state {</div><div class='add'>+				pins = "gpio35";</div><div class='add'>+				function = "qup0_se2";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart2_rx: qup-uart2-rx-state {</div><div class='add'>+				pins = "gpio36";</div><div class='add'>+				function = "qup0_se2";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart3_cts: qup-uart3-cts-state {</div><div class='add'>+				pins = "gpio25";</div><div class='add'>+				function = "qup0_se3";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart3_rts: qup-uart3-rts-state {</div><div class='add'>+				pins = "gpio26";</div><div class='add'>+				function = "qup0_se3";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart3_tx: qup-uart3-tx-state {</div><div class='add'>+				pins = "gpio27";</div><div class='add'>+				function = "qup0_se3";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart3_rx: qup-uart3-rx-state {</div><div class='add'>+				pins = "gpio28";</div><div class='add'>+				function = "qup0_se3";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart4_cts: qup-uart4-cts-state {</div><div class='add'>+				pins = "gpio29";</div><div class='add'>+				function = "qup0_se4";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart4_rts: qup-uart4-rts-state {</div><div class='add'>+				pins = "gpio30";</div><div class='add'>+				function = "qup0_se4";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart4_tx: qup-uart4-tx-state {</div><div class='add'>+				pins = "gpio31";</div><div class='add'>+				function = "qup0_se4";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart4_rx: qup-uart4-rx-state {</div><div class='add'>+				pins = "gpio32";</div><div class='add'>+				function = "qup0_se4";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart5_cts: qup-uart5-cts-state {</div><div class='add'>+				pins = "gpio21";</div><div class='add'>+				function = "qup0_se5";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart5_rts: qup-uart5-rts-state {</div><div class='add'>+				pins = "gpio22";</div><div class='add'>+				function = "qup0_se5";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart5_tx: qup-uart5-tx-state {</div><div class='add'>+				pins = "gpio23";</div><div class='add'>+				function = "qup0_se5";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart5_rx: qup-uart5-rx-state {</div><div class='add'>+				pins = "gpio23";</div><div class='add'>+				function = "qup0_se5";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart6_cts: qup-uart6-cts-state {</div><div class='add'>+				pins = "gpio80";</div><div class='add'>+				function = "qup0_se6";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart6_rts: qup-uart6-rts-state {</div><div class='add'>+				pins = "gpio81";</div><div class='add'>+				function = "qup0_se6";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart6_tx: qup-uart6-tx-state {</div><div class='add'>+				pins = "gpio82";</div><div class='add'>+				function = "qup0_se6";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart6_rx: qup-uart6-rx-state {</div><div class='add'>+				pins = "gpio83";</div><div class='add'>+				function = "qup0_se6";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart7_tx: qup-uart7-tx-state {</div><div class='add'>+				pins = "gpio43";</div><div class='add'>+				function = "qup0_se7";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart7_rx: qup-uart7-rx-state {</div><div class='add'>+				pins = "gpio44";</div><div class='add'>+				function = "qup0_se7";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart8_cts: qup-uart8-cts-state {</div><div class='add'>+				pins = "gpio37";</div><div class='add'>+				function = "qup1_se0";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart8_rts: qup-uart8-rts-state {</div><div class='add'>+				pins = "gpio38";</div><div class='add'>+				function = "qup1_se0";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart8_tx: qup-uart8-tx-state {</div><div class='add'>+				pins = "gpio39";</div><div class='add'>+				function = "qup1_se0";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart8_rx: qup-uart8-rx-state {</div><div class='add'>+				pins = "gpio40";</div><div class='add'>+				function = "qup1_se0";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart9_cts: qup-uart9-cts-state {</div><div class='add'>+				pins = "gpio39";</div><div class='add'>+				function = "qup1_se1";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart9_rts: qup-uart9-rts-state {</div><div class='add'>+				pins = "gpio40";</div><div class='add'>+				function = "qup1_se1";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart9_tx: qup-uart9-tx-state {</div><div class='add'>+				pins = "gpio37";</div><div class='add'>+				function = "qup1_se1";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart9_rx: qup-uart9-rx-state {</div><div class='add'>+				pins = "gpio38";</div><div class='add'>+				function = "qup1_se1";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart10_cts: qup-uart10-cts-state {</div><div class='add'>+				pins = "gpio84";</div><div class='add'>+				function = "qup1_se2";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart10_rts: qup-uart10-rts-state {</div><div class='add'>+				pins = "gpio84";</div><div class='add'>+				function = "qup1_se2";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart10_tx: qup-uart10-tx-state {</div><div class='add'>+				pins = "gpio85";</div><div class='add'>+				function = "qup1_se2";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart10_rx: qup-uart10-rx-state {</div><div class='add'>+				pins = "gpio87";</div><div class='add'>+				function = "qup1_se2";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart11_tx: qup-uart11-tx-state {</div><div class='add'>+				pins = "gpio41";</div><div class='add'>+				function = "qup1_se3";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart11_rx: qup-uart11-rx-state {</div><div class='add'>+				pins = "gpio42";</div><div class='add'>+				function = "qup1_se3";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart12_cts: qup-uart12-cts-state {</div><div class='add'>+				pins = "gpio45";</div><div class='add'>+				function = "qup1_se4";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart12_rts: qup-uart12-rts-state {</div><div class='add'>+				pins = "gpio46";</div><div class='add'>+				function = "qup1_se4";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart12_tx: qup-uart12-tx-state {</div><div class='add'>+				pins = "gpio47";</div><div class='add'>+				function = "qup1_se4";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart12_rx: qup-uart12-rx-state {</div><div class='add'>+				pins = "gpio48";</div><div class='add'>+				function = "qup1_se4";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart13_cts: qup-uart13-cts-state {</div><div class='add'>+				pins = "gpio49";</div><div class='add'>+				function = "qup1_se5";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart13_rts: qup-uart13-rts-state {</div><div class='add'>+				pins = "gpio50";</div><div class='add'>+				function = "qup1_se5";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart13_tx: qup-uart13-tx-state {</div><div class='add'>+				pins = "gpio51";</div><div class='add'>+				function = "qup1_se5";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart13_rx: qup-uart13-rx-state {</div><div class='add'>+				pins = "gpio52";</div><div class='add'>+				function = "qup1_se5";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart14_cts: qup-uart14-cts-state {</div><div class='add'>+				pins = "gpio89";</div><div class='add'>+				function = "qup1_se6";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart14_rts: qup-uart14-rts-state {</div><div class='add'>+				pins = "gpio90";</div><div class='add'>+				function = "qup1_se6";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart14_tx: qup-uart14-tx-state {</div><div class='add'>+				pins = "gpio91";</div><div class='add'>+				function = "qup1_se6";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart14_rx: qup-uart14-rx-state {</div><div class='add'>+				pins = "gpio92";</div><div class='add'>+				function = "qup1_se6";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart15_cts: qup-uart15-cts-state {</div><div class='add'>+				pins = "gpio91";</div><div class='add'>+				function = "qup1_se7";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart15_rts: qup-uart15-rts-state {</div><div class='add'>+				pins = "gpio92";</div><div class='add'>+				function = "qup1_se7";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart15_tx: qup-uart15-tx-state {</div><div class='add'>+				pins = "gpio89";</div><div class='add'>+				function = "qup1_se7";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart15_rx: qup-uart15-rx-state {</div><div class='add'>+				pins = "gpio90";</div><div class='add'>+				function = "qup1_se7";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart16_cts: qup-uart16-cts-state {</div><div class='add'>+				pins = "gpio10";</div><div class='add'>+				function = "qup2_se0";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart16_rts: qup-uart16-rts-state {</div><div class='add'>+				pins = "gpio11";</div><div class='add'>+				function = "qup2_se0";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart16_tx: qup-uart16-tx-state {</div><div class='add'>+				pins = "gpio12";</div><div class='add'>+				function = "qup2_se0";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			qup_uart16_rx: qup-uart16-rx-state {</div><div class='add'>+				pins = "gpio13";</div><div class='add'>+				function = "qup2_se0";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sdc1_state_on: sdc1-on-state {</div><div class='add'>+				clk-pins {</div><div class='add'>+					pins = "sdc1_clk";</div><div class='add'>+					drive-strength = &lt;16&gt;;</div><div class='add'>+					bias-disable;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cmd-pins {</div><div class='add'>+					pins = "sdc1_cmd";</div><div class='add'>+					drive-strength = &lt;10&gt;;</div><div class='add'>+					bias-pull-up;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				data-pins {</div><div class='add'>+					pins = "sdc1_data";</div><div class='add'>+					drive-strength = &lt;10&gt;;</div><div class='add'>+					bias-pull-up;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				rclk-pins {</div><div class='add'>+					pins = "sdc1_rclk";</div><div class='add'>+					bias-pull-down;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			sdc1_state_off: sdc1-off-state {</div><div class='add'>+				clk-pins {</div><div class='add'>+					pins = "sdc1_clk";</div><div class='add'>+					drive-strength = &lt;2&gt;;</div><div class='add'>+					bias-bus-hold;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				cmd-pins {</div><div class='add'>+					pins = "sdc1_cmd";</div><div class='add'>+					drive-strength = &lt;2&gt;;</div><div class='add'>+					bias-bus-hold;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				data-pins {</div><div class='add'>+					pins = "sdc1_data";</div><div class='add'>+					drive-strength = &lt;2&gt;;</div><div class='add'>+					bias-bus-hold;</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				rclk-pins {</div><div class='add'>+					pins = "sdc1_rclk";</div><div class='add'>+					bias-bus-hold;</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		sram: sram@146d8000 {</div><div class='add'>+			compatible = "qcom,qcs8300-imem", "syscon", "simple-mfd";</div><div class='add'>+			reg = &lt;0x0 0x146d8000 0x0 0x1000&gt;;</div><div class='add'>+			ranges = &lt;0x0 0x0 0x146d8000 0x1000&gt;;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			pil-reloc@94c {</div><div class='add'>+				compatible = "qcom,pil-reloc-info";</div><div class='add'>+				reg = &lt;0x94c 0xc8&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		apps_smmu: iommu@15000000 {</div><div class='add'>+			compatible = "qcom,qcs8300-smmu-500", "qcom,smmu-500", "arm,mmu-500";</div><div class='add'>+</div><div class='add'>+			reg = &lt;0x0 0x15000000 0x0 0x100000&gt;;</div><div class='add'>+			#iommu-cells = &lt;2&gt;;</div><div class='add'>+			#global-interrupts = &lt;2&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI  98 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI  99 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		pcie_smmu: iommu@15200000 {</div><div class='add'>+			compatible = "qcom,qcs8300-smmu-500", "qcom,smmu-500", "arm,mmu-500";</div><div class='add'>+			reg = &lt;0x0 0x15200000 0x0 0x80000&gt;;</div><div class='add'>+			#iommu-cells = &lt;2&gt;;</div><div class='add'>+			#global-interrupts = &lt;2&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		intc: interrupt-controller@17a00000 {</div><div class='add'>+			compatible = "arm,gic-v3";</div><div class='add'>+			reg = &lt;0x0 0x17a00000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0x17a60000 0x0 0x100000&gt;;</div><div class='add'>+			interrupts = &lt;GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			#interrupt-cells = &lt;3&gt;;</div><div class='add'>+			interrupt-controller;</div><div class='add'>+			#redistributor-regions = &lt;1&gt;;</div><div class='add'>+			redistributor-stride = &lt;0x0 0x20000&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		watchdog@17c10000 {</div><div class='add'>+			compatible = "qcom,apss-wdt-qcs8300", "qcom,kpss-wdt";</div><div class='add'>+			reg = &lt;0x0 0x17c10000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;sleep_clk&gt;;</div><div class='add'>+			interrupts = &lt;GIC_SPI 0 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		timer@17c20000 {</div><div class='add'>+			compatible = "arm,armv7-timer-mem";</div><div class='add'>+			reg = &lt;0x0 0x17c20000 0x0 0x1000&gt;;</div><div class='add'>+			ranges = &lt;0x0 0x0 0x0 0x20000000&gt;;</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+			frame@17c21000 {</div><div class='add'>+				reg = &lt;0x17c21000 0x1000&gt;,</div><div class='add'>+				      &lt;0x17c22000 0x1000&gt;;</div><div class='add'>+				frame-number = &lt;0&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+					     &lt;GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@17c23000 {</div><div class='add'>+				reg = &lt;0x17c23000 0x1000&gt;;</div><div class='add'>+				frame-number = &lt;1&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@17c25000 {</div><div class='add'>+				reg = &lt;0x17c25000 0x1000&gt;;</div><div class='add'>+				frame-number = &lt;2&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@17c27000 {</div><div class='add'>+				reg = &lt;0x17c27000 0x1000&gt;;</div><div class='add'>+				frame-number = &lt;3&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@17c29000 {</div><div class='add'>+				reg = &lt;0x17c29000 0x1000&gt;;</div><div class='add'>+				frame-number = &lt;4&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@17c2b000 {</div><div class='add'>+				reg = &lt;0x17c2b000 0x1000&gt;;</div><div class='add'>+				frame-number = &lt;5&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			frame@17c2d000 {</div><div class='add'>+				reg = &lt;0x17c2d000 0x1000&gt;;</div><div class='add'>+				frame-number = &lt;6&gt;;</div><div class='add'>+				interrupts = &lt;GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+				status = "disabled";</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		apps_rsc: rsc@18200000 {</div><div class='add'>+			compatible = "qcom,rpmh-rsc";</div><div class='add'>+			reg = &lt;0x0 0x18200000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0x18210000 0x0 0x10000&gt;,</div><div class='add'>+			      &lt;0x0 0x18220000 0x0 0x10000&gt;;</div><div class='add'>+			reg-names = "drv-0",</div><div class='add'>+				    "drv-1",</div><div class='add'>+				    "drv-2";</div><div class='add'>+			interrupts = &lt;GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;system_pd&gt;;</div><div class='add'>+			label = "apps_rsc";</div><div class='add'>+</div><div class='add'>+			qcom,tcs-offset = &lt;0xd00&gt;;</div><div class='add'>+			qcom,drv-id = &lt;2&gt;;</div><div class='add'>+			qcom,tcs-config = &lt;ACTIVE_TCS 2&gt;,</div><div class='add'>+					  &lt;SLEEP_TCS 3&gt;,</div><div class='add'>+					  &lt;WAKE_TCS 3&gt;,</div><div class='add'>+					  &lt;CONTROL_TCS 0&gt;;</div><div class='add'>+</div><div class='add'>+			apps_bcm_voter: bcm-voter {</div><div class='add'>+				compatible = "qcom,bcm-voter";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			rpmhcc: clock-controller {</div><div class='add'>+				compatible = "qcom,sa8775p-rpmh-clk";</div><div class='add'>+				#clock-cells = &lt;1&gt;;</div><div class='add'>+				clocks = &lt;&amp;xo_board_clk&gt;;</div><div class='add'>+				clock-names = "xo";</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			rpmhpd: power-controller {</div><div class='add'>+				compatible = "qcom,qcs8300-rpmhpd";</div><div class='add'>+				#power-domain-cells = &lt;1&gt;;</div><div class='add'>+				operating-points-v2 = &lt;&amp;rpmhpd_opp_table&gt;;</div><div class='add'>+</div><div class='add'>+				rpmhpd_opp_table: opp-table {</div><div class='add'>+					compatible = "operating-points-v2";</div><div class='add'>+</div><div class='add'>+					rpmhpd_opp_ret: opp-0 {</div><div class='add'>+						opp-level = &lt;RPMH_REGULATOR_LEVEL_RETENTION&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					rpmhpd_opp_min_svs: opp-1 {</div><div class='add'>+						opp-level = &lt;RPMH_REGULATOR_LEVEL_MIN_SVS&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					rpmhpd_opp_low_svs: opp-2 {</div><div class='add'>+						opp-level = &lt;RPMH_REGULATOR_LEVEL_LOW_SVS&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					rpmhpd_opp_svs: opp-3 {</div><div class='add'>+						opp-level = &lt;RPMH_REGULATOR_LEVEL_SVS&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					rpmhpd_opp_svs_l1: opp-4 {</div><div class='add'>+						opp-level = &lt;RPMH_REGULATOR_LEVEL_SVS_L1&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					rpmhpd_opp_nom: opp-5 {</div><div class='add'>+						opp-level = &lt;RPMH_REGULATOR_LEVEL_NOM&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					rpmhpd_opp_nom_l1: opp-6 {</div><div class='add'>+						opp-level = &lt;RPMH_REGULATOR_LEVEL_NOM_L1&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					rpmhpd_opp_nom_l2: opp-7 {</div><div class='add'>+						opp-level = &lt;RPMH_REGULATOR_LEVEL_NOM_L2&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					rpmhpd_opp_turbo: opp-8 {</div><div class='add'>+						opp-level = &lt;RPMH_REGULATOR_LEVEL_TURBO&gt;;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					rpmhpd_opp_turbo_l1: opp-9 {</div><div class='add'>+						opp-level = &lt;RPMH_REGULATOR_LEVEL_TURBO_L1&gt;;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		epss_l3_cl0: interconnect@18590000 {</div><div class='add'>+			compatible = "qcom,qcs8300-epss-l3", "qcom,sa8775p-epss-l3",</div><div class='add'>+				     "qcom,epss-l3";</div><div class='add'>+			reg = &lt;0x0 0x18590000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;, &lt;&amp;gcc GCC_GPLL0&gt;;</div><div class='add'>+			clock-names = "xo", "alternate";</div><div class='add'>+			#interconnect-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		cpufreq_hw: cpufreq@18591000 {</div><div class='add'>+			compatible = "qcom,qcs8300-cpufreq-epss", "qcom,cpufreq-epss";</div><div class='add'>+			reg = &lt;0x0 0x18591000 0x0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0x18593000 0x0 0x1000&gt;,</div><div class='add'>+			      &lt;0x0 0x18594000 0x0 0x1000&gt;;</div><div class='add'>+			reg-names = "freq-domain0",</div><div class='add'>+				    "freq-domain1",</div><div class='add'>+				    "freq-domain2";</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "dcvsh-irq-0",</div><div class='add'>+					  "dcvsh-irq-1",</div><div class='add'>+					  "dcvsh-irq-2";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;, &lt;&amp;gcc GCC_GPLL0&gt;;</div><div class='add'>+			clock-names = "xo", "alternate";</div><div class='add'>+</div><div class='add'>+			#freq-domain-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		epss_l3_cl1: interconnect@18592000 {</div><div class='add'>+			compatible = "qcom,qcs8300-epss-l3", "qcom,sa8775p-epss-l3",</div><div class='add'>+				     "qcom,epss-l3";</div><div class='add'>+			reg = &lt;0x0 0x18592000 0x0 0x1000&gt;;</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;, &lt;&amp;gcc GCC_GPLL0&gt;;</div><div class='add'>+			clock-names = "xo", "alternate";</div><div class='add'>+			#interconnect-cells = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		remoteproc_gpdsp: remoteproc@20c00000 {</div><div class='add'>+			compatible = "qcom,qcs8300-gpdsp-pas", "qcom,sa8775p-gpdsp0-pas";</div><div class='add'>+			reg = &lt;0x0 0x20c00000 0x0 0x10000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts-extended = &lt;&amp;intc GIC_SPI 768 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;smp2p_gpdsp_in 0 0&gt;,</div><div class='add'>+					      &lt;&amp;smp2p_gpdsp_in 1 0&gt;,</div><div class='add'>+					      &lt;&amp;smp2p_gpdsp_in 2 0&gt;,</div><div class='add'>+					      &lt;&amp;smp2p_gpdsp_in 3 0&gt;;</div><div class='add'>+			interrupt-names = "wdog",</div><div class='add'>+					  "fatal",</div><div class='add'>+					  "ready",</div><div class='add'>+					  "handover",</div><div class='add'>+					  "stop-ack";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;;</div><div class='add'>+			clock-names = "xo";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;,</div><div class='add'>+					&lt;&amp;rpmhpd RPMHPD_MXC&gt;;</div><div class='add'>+			power-domain-names = "cx",</div><div class='add'>+					     "mxc";</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;gpdsp_anoc MASTER_DSP0 QCOM_ICC_TAG_ALWAYS</div><div class='add'>+					 &amp;config_noc SLAVE_CLK_CTL QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+</div><div class='add'>+			memory-region = &lt;&amp;gpdsp_mem&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,qmp = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,smem-states = &lt;&amp;smp2p_gpdsp_out 0&gt;;</div><div class='add'>+			qcom,smem-state-names = "stop";</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			glink-edge {</div><div class='add'>+				interrupts-extended = &lt;&amp;ipcc IPCC_CLIENT_GPDSP0</div><div class='add'>+							     IPCC_MPROC_SIGNAL_GLINK_QMP</div><div class='add'>+							     IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				mboxes = &lt;&amp;ipcc IPCC_CLIENT_GPDSP0</div><div class='add'>+						IPCC_MPROC_SIGNAL_GLINK_QMP&gt;;</div><div class='add'>+</div><div class='add'>+				label = "gpdsp";</div><div class='add'>+				qcom,remote-pid = &lt;17&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ethernet0: ethernet@23040000 {</div><div class='add'>+			compatible = "qcom,qcs8300-ethqos", "qcom,sa8775p-ethqos";</div><div class='add'>+			reg = &lt;0x0 0x23040000 0x0 0x00010000&gt;,</div><div class='add'>+			      &lt;0x0 0x23056000 0x0 0x00000100&gt;;</div><div class='add'>+			reg-names = "stmmaceth", "rgmii";</div><div class='add'>+</div><div class='add'>+			interrupts = &lt;GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH&gt;,</div><div class='add'>+				     &lt;GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH&gt;;</div><div class='add'>+			interrupt-names = "macirq", "sfty";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;gcc GCC_EMAC0_AXI_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_EMAC0_SLV_AHB_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_EMAC0_PTP_CLK&gt;,</div><div class='add'>+				 &lt;&amp;gcc GCC_EMAC0_PHY_AUX_CLK&gt;;</div><div class='add'>+			clock-names = "stmmaceth",</div><div class='add'>+				      "pclk",</div><div class='add'>+				      "ptp_ref",</div><div class='add'>+				      "phyaux";</div><div class='add'>+			power-domains = &lt;&amp;gcc GCC_EMAC0_GDSC&gt;;</div><div class='add'>+</div><div class='add'>+			phys = &lt;&amp;serdes0&gt;;</div><div class='add'>+			phy-names = "serdes";</div><div class='add'>+</div><div class='add'>+			iommus = &lt;&amp;apps_smmu 0x120 0xf&gt;;</div><div class='add'>+			dma-coherent;</div><div class='add'>+</div><div class='add'>+			snps,tso;</div><div class='add'>+			snps,pbl = &lt;32&gt;;</div><div class='add'>+			rx-fifo-depth = &lt;16384&gt;;</div><div class='add'>+			tx-fifo-depth = &lt;20480&gt;;</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		nspa_noc: interconnect@260c0000 {</div><div class='add'>+			compatible = "qcom,qcs8300-nspa-noc";</div><div class='add'>+			reg = &lt;0x0 0x260c0000 0x0 0x16080&gt;;</div><div class='add'>+			#interconnect-cells = &lt;2&gt;;</div><div class='add'>+			qcom,bcm-voters = &lt;&amp;apps_bcm_voter&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		remoteproc_cdsp: remoteproc@26300000 {</div><div class='add'>+			compatible = "qcom,qcs8300-cdsp-pas", "qcom,sa8775p-cdsp0-pas";</div><div class='add'>+			reg = &lt;0x0 0x26300000 0x0 0x10000&gt;;</div><div class='add'>+</div><div class='add'>+			interrupts-extended = &lt;&amp;intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+					      &lt;&amp;smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+			interrupt-names = "wdog",</div><div class='add'>+					  "fatal",</div><div class='add'>+					  "ready",</div><div class='add'>+					  "handover",</div><div class='add'>+					  "stop-ack";</div><div class='add'>+</div><div class='add'>+			clocks = &lt;&amp;rpmhcc RPMH_CXO_CLK&gt;;</div><div class='add'>+			clock-names = "xo";</div><div class='add'>+</div><div class='add'>+			power-domains = &lt;&amp;rpmhpd RPMHPD_CX&gt;,</div><div class='add'>+					&lt;&amp;rpmhpd RPMHPD_MXC&gt;,</div><div class='add'>+					&lt;&amp;rpmhpd RPMHPD_NSP0&gt;;</div><div class='add'>+</div><div class='add'>+			power-domain-names = "cx",</div><div class='add'>+					     "mxc",</div><div class='add'>+					     "nsp";</div><div class='add'>+</div><div class='add'>+			interconnects = &lt;&amp;nspa_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS</div><div class='add'>+					 &amp;mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS&gt;;</div><div class='add'>+</div><div class='add'>+			memory-region = &lt;&amp;cdsp_mem&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,qmp = &lt;&amp;aoss_qmp&gt;;</div><div class='add'>+</div><div class='add'>+			qcom,smem-states = &lt;&amp;smp2p_cdsp_out 0&gt;;</div><div class='add'>+			qcom,smem-state-names = "stop";</div><div class='add'>+</div><div class='add'>+			status = "disabled";</div><div class='add'>+</div><div class='add'>+			glink-edge {</div><div class='add'>+				interrupts-extended = &lt;&amp;ipcc IPCC_CLIENT_CDSP</div><div class='add'>+							     IPCC_MPROC_SIGNAL_GLINK_QMP</div><div class='add'>+							     IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+				mboxes = &lt;&amp;ipcc IPCC_CLIENT_CDSP</div><div class='add'>+						IPCC_MPROC_SIGNAL_GLINK_QMP&gt;;</div><div class='add'>+</div><div class='add'>+				label = "cdsp";</div><div class='add'>+				qcom,remote-pid = &lt;5&gt;;</div><div class='add'>+</div><div class='add'>+				fastrpc {</div><div class='add'>+					compatible = "qcom,fastrpc";</div><div class='add'>+					qcom,glink-channels = "fastrpcglink-apps-dsp";</div><div class='add'>+					label = "cdsp";</div><div class='add'>+					#address-cells = &lt;1&gt;;</div><div class='add'>+					#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+					compute-cb@1 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;1&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x19c1 0x0440&gt;,</div><div class='add'>+							 &lt;&amp;apps_smmu 0x1961 0x0400&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@2 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;2&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x19c2 0x0440&gt;,</div><div class='add'>+							 &lt;&amp;apps_smmu 0x1962 0x0400&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@3 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;3&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x19c3 0x0440&gt;,</div><div class='add'>+							 &lt;&amp;apps_smmu 0x1963 0x0400&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+</div><div class='add'>+					compute-cb@4 {</div><div class='add'>+						compatible = "qcom,fastrpc-compute-cb";</div><div class='add'>+						reg = &lt;4&gt;;</div><div class='add'>+						iommus = &lt;&amp;apps_smmu 0x19c4 0x0440&gt;,</div><div class='add'>+							 &lt;&amp;apps_smmu 0x1964 0x0400&gt;;</div><div class='add'>+						dma-coherent;</div><div class='add'>+					};</div><div class='add'>+				};</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	timer {</div><div class='add'>+		compatible = "arm,armv8-timer";</div><div class='add'>+		interrupts = &lt;GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)&gt;,</div><div class='add'>+			     &lt;GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/msm8216-samsung-fortuna3g.dts b/arch/arm64/boot/dts/qcom/msm8216-samsung-fortuna3g.dts<br/>new file mode 100644<br/>index 000000000000..fba68bf8bf79<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/msm8216-samsung-fortuna3g.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/msm8216-samsung-fortuna3g.dts</a></div><div class='hunk'>@@ -0,0 +1,25 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "msm8916-samsung-fortuna-common.dtsi"</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Samsung Galaxy Grand Prime (SM-G530H)";</div><div class='add'>+	compatible = "samsung,fortuna3g", "qcom,msm8916";</div><div class='add'>+	chassis-type = "handset";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;battery {</div><div class='add'>+	charge-term-current-microamp = &lt;200000&gt;;</div><div class='add'>+	constant-charge-current-max-microamp = &lt;1000000&gt;;</div><div class='add'>+	constant-charge-voltage-max-microvolt = &lt;4350000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;st_accel {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;st_magn {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts b/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts<br/>new file mode 100644<br/>index 000000000000..3a6eba904641<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts</a></div><div class='hunk'>@@ -0,0 +1,278 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "msm8916-pm8916.dtsi"</div><div class='add'>+#include "msm8916-modem-qdsp6.dtsi"</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * NOTE: The original firmware from Acer can only boot 32-bit kernels.</div><div class='add'>+ * To boot this device tree using arm64 it is necessary to flash 64-bit</div><div class='add'>+ * TZ/HYP firmware (e.g. taken from the DragonBoard 410c).</div><div class='add'>+ * See https://wiki.postmarketos.org/wiki/Acer_Iconia_Talk_S_(acer-a1-724)</div><div class='add'>+ * for suggested installation instructions.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Acer Iconia Talk S A1-724";</div><div class='add'>+	compatible = "acer,a1-724", "qcom,msm8916";</div><div class='add'>+	chassis-type = "tablet";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		mmc0 = &amp;sdhc_1; /* eMMC */</div><div class='add'>+		mmc1 = &amp;sdhc_2; /* SD card */</div><div class='add'>+		serial0 = &amp;blsp_uart2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;gpio_keys_default&gt;;</div><div class='add'>+</div><div class='add'>+		label = "GPIO Buttons";</div><div class='add'>+</div><div class='add'>+		button-volume-up {</div><div class='add'>+			label = "Volume Up";</div><div class='add'>+			gpios = &lt;&amp;tlmm 107 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb_id: usb-id {</div><div class='add'>+		compatible = "linux,extcon-usb-gpio";</div><div class='add'>+		id-gpios = &lt;&amp;tlmm 110 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;usb_id_default&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_i2c2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	accelerometer@10 {</div><div class='add'>+		compatible = "bosch,bmc150_accel";</div><div class='add'>+		reg = &lt;0x10&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;tlmm&gt;;</div><div class='add'>+		interrupts = &lt;115 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+</div><div class='add'>+		vdd-supply = &lt;&amp;pm8916_l17&gt;;</div><div class='add'>+		vddio-supply = &lt;&amp;pm8916_l6&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;accel_int_default&gt;;</div><div class='add'>+</div><div class='add'>+		mount-matrix = "0", "-1", "0",</div><div class='add'>+			       "-1", "0", "0",</div><div class='add'>+			       "0", "0", "1";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	magnetometer@12 {</div><div class='add'>+		compatible = "bosch,bmc150_magn";</div><div class='add'>+		reg = &lt;0x12&gt;;</div><div class='add'>+</div><div class='add'>+		vdd-supply = &lt;&amp;pm8916_l17&gt;;</div><div class='add'>+		vddio-supply = &lt;&amp;pm8916_l6&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_i2c4 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	led-controller@30 {</div><div class='add'>+		compatible = "kinetic,ktd2026";</div><div class='add'>+		reg = &lt;0x30&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		led@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_i2c5 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	touchscreen@38 {</div><div class='add'>+		/* Actually ft5446 */</div><div class='add'>+		compatible = "edt,edt-ft5406";</div><div class='add'>+		reg = &lt;0x38&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-parent = &lt;&amp;tlmm&gt;;</div><div class='add'>+		interrupts = &lt;13 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		reset-gpios = &lt;&amp;tlmm 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		vcc-supply = &lt;&amp;pm8916_l16&gt;;</div><div class='add'>+		iovcc-supply = &lt;&amp;pm8916_l6&gt;;</div><div class='add'>+</div><div class='add'>+		touchscreen-size-x = &lt;720&gt;;</div><div class='add'>+		touchscreen-size-y = &lt;1280&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;touchscreen_default&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_uart2 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;blsp_uart2_console_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;blsp_uart2_console_sleep&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mpss_mem {</div><div class='add'>+	reg = &lt;0x0 0x86800000 0x0 0x4500000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8916_codec {</div><div class='add'>+	qcom,micbias-lvl = &lt;2800&gt;;</div><div class='add'>+	qcom,mbhc-vthreshold-low = &lt;150 237 450 500 590&gt;;</div><div class='add'>+	qcom,mbhc-vthreshold-high = &lt;150 237 450 500 590&gt;;</div><div class='add'>+	qcom,hphl-jack-type-normally-open;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8916_resin {</div><div class='add'>+	linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8916_rpm_regulators {</div><div class='add'>+	pm8916_l16: l16 {</div><div class='add'>+		regulator-min-microvolt = &lt;2900000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;2900000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pm8916_l17: l17 {</div><div class='add'>+		regulator-min-microvolt = &lt;2850000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;2850000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8916_vib {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sdhc_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sdhc_2 {</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdc2_default &amp;sdc2_cd_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;sdc2_sleep &amp;sdc2_cd_default&gt;;</div><div class='add'>+</div><div class='add'>+	cd-gpios = &lt;&amp;tlmm 38 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sound {</div><div class='add'>+	model = "acer-a1-724";</div><div class='add'>+	audio-routing =</div><div class='add'>+		"DMIC1", "MIC BIAS External1",</div><div class='add'>+		"DMIC1", "Digital Mic1",</div><div class='add'>+		"AMIC2", "MIC BIAS Internal2",</div><div class='add'>+		"DMIC2", "MIC BIAS External1",</div><div class='add'>+		"DMIC2", "Digital Mic2";</div><div class='add'>+</div><div class='add'>+	pinctrl-0 = &lt;&amp;cdc_pdm_default &amp;sec_mi2s_default &amp;pri_mi2s_mclk_default &amp;cdc_dmic_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;cdc_pdm_sleep &amp;sec_mi2s_sleep &amp;pri_mi2s_mclk_sleep &amp;cdc_dmic_sleep&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb {</div><div class='add'>+	extcon = &lt;&amp;usb_id&gt;, &lt;&amp;usb_id&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_hs_phy {</div><div class='add'>+	extcon = &lt;&amp;usb_id&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;venus {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;venus_mem {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wcnss {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wcnss_iris {</div><div class='add'>+	compatible = "qcom,wcn3620";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wcnss_mem {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tlmm {</div><div class='add'>+	accel_int_default: accel-int-default-state {</div><div class='add'>+		pins = "gpio115";</div><div class='add'>+		function = "gpio";</div><div class='add'>+</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio_keys_default: gpio-keys-default-state {</div><div class='add'>+		pins = "gpio107";</div><div class='add'>+		function = "gpio";</div><div class='add'>+</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-pull-up;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdc2_cd_default: sdc2-cd-default-state {</div><div class='add'>+		pins = "gpio38";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	touchscreen_default: touchscreen-default-state {</div><div class='add'>+		reset-pins {</div><div class='add'>+			pins = "gpio12";</div><div class='add'>+			function = "gpio";</div><div class='add'>+			drive-strength = &lt;2&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		touchscreen-pins {</div><div class='add'>+			pins = "gpio13";</div><div class='add'>+			function = "gpio";</div><div class='add'>+			drive-strength = &lt;2&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb_id_default: usb-id-default-state {</div><div class='add'>+		pins = "gpio110";</div><div class='add'>+		function = "gpio";</div><div class='add'>+</div><div class='add'>+		drive-strength = &lt;8&gt;;</div><div class='add'>+		bias-pull-up;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts<br/>new file mode 100644<br/>index 000000000000..2de8b6f9531b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts</a></div><div class='hunk'>@@ -0,0 +1,483 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "msm8916-pm8916.dtsi"</div><div class='add'>+#include "msm8916-modem-qdsp6.dtsi"</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Alcatel OneTouch Idol 3 (4.7)";</div><div class='add'>+	compatible = "alcatel,idol347", "qcom,msm8916";</div><div class='add'>+	chassis-type = "handset";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		mmc0 = &amp;sdhc_1; /* eMMC */</div><div class='add'>+		mmc1 = &amp;sdhc_2; /* SD card */</div><div class='add'>+		serial0 = &amp;blsp_uart2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reserved-memory {</div><div class='add'>+		/delete-node/ reserved@86680000;</div><div class='add'>+		/delete-node/ rmtfs@86700000;</div><div class='add'>+</div><div class='add'>+		rmtfs: rmtfs@86680000 {</div><div class='add'>+			compatible = "qcom,rmtfs-mem";</div><div class='add'>+			reg = &lt;0x0 0x86680000 0x0 0x160000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+</div><div class='add'>+			qcom,client-id = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;gpio_keys_default&gt;;</div><div class='add'>+</div><div class='add'>+		label = "GPIO Buttons";</div><div class='add'>+</div><div class='add'>+		button-volume-up {</div><div class='add'>+			label = "Volume Up";</div><div class='add'>+			gpios = &lt;&amp;tlmm 107 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;gpio_leds_default&gt;;</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			gpios = &lt;&amp;tlmm 32 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			linux,default-trigger = "torch";</div><div class='add'>+			function = LED_FUNCTION_TORCH;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_headphones_avdd: regulator-headphones-avdd {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "headphones_avdd";</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+		gpio = &lt;&amp;tlmm 121 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+		pinctrl-0 = &lt;&amp;headphones_avdd_default&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb_id: usb-id {</div><div class='add'>+		compatible = "linux,extcon-usb-gpio";</div><div class='add'>+		id-gpios = &lt;&amp;tlmm 69 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;usb_id_default&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_i2c3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	headphones: audio-codec@10 {</div><div class='add'>+		compatible = "asahi-kasei,ak4375";</div><div class='add'>+		reg = &lt;0x10&gt;;</div><div class='add'>+		avdd-supply = &lt;&amp;reg_headphones_avdd&gt;;</div><div class='add'>+		tvdd-supply = &lt;&amp;pm8916_l6&gt;;</div><div class='add'>+		pdn-gpios = &lt;&amp;tlmm 114 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;headphones_pdn_default&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	speaker_codec_top: audio-codec@34 {</div><div class='add'>+		compatible = "nxp,tfa9897";</div><div class='add'>+		reg = &lt;0x34&gt;;</div><div class='add'>+		vddd-supply = &lt;&amp;pm8916_l6&gt;;</div><div class='add'>+		rcv-gpios = &lt;&amp;tlmm 50 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;speaker_top_default&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		sound-name-prefix = "Speaker Top";</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	speaker_codec_bottom: audio-codec@36 {</div><div class='add'>+		compatible = "nxp,tfa9897";</div><div class='add'>+		reg = &lt;0x36&gt;;</div><div class='add'>+		vddd-supply = &lt;&amp;pm8916_l6&gt;;</div><div class='add'>+		rcv-gpios = &lt;&amp;tlmm 111 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;speaker_bottom_default&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		sound-name-prefix = "Speaker Bottom";</div><div class='add'>+		#sound-dai-cells = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_i2c4 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	touchscreen@26 {</div><div class='add'>+		compatible = "mstar,msg2638";</div><div class='add'>+		reg = &lt;0x26&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;tlmm&gt;;</div><div class='add'>+		interrupts = &lt;13 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;tlmm 100 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;ts_int_reset_default&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;pm8916_l17&gt;;</div><div class='add'>+		vddio-supply = &lt;&amp;pm8916_l5&gt;;</div><div class='add'>+		touchscreen-size-x = &lt;2048&gt;;</div><div class='add'>+		touchscreen-size-y = &lt;2048&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_i2c5 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	magnetometer@c {</div><div class='add'>+		compatible = "asahi-kasei,ak09911";</div><div class='add'>+		reg = &lt;0x0c&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;pm8916_l17&gt;;</div><div class='add'>+		vid-supply = &lt;&amp;pm8916_l6&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;tlmm 8 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;mag_reset_default&gt;;</div><div class='add'>+		mount-matrix = "0", "1", "0",</div><div class='add'>+			       "-1", "0", "0",</div><div class='add'>+			       "0", "0", "1";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	accelerometer@f {</div><div class='add'>+		compatible = "kionix,kxtj21009";</div><div class='add'>+		reg = &lt;0x0f&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;pm8916_l17&gt;;</div><div class='add'>+		vddio-supply = &lt;&amp;pm8916_l6&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;tlmm&gt;;</div><div class='add'>+		interrupts = &lt;31 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;accel_int_default&gt;;</div><div class='add'>+		mount-matrix = "-1", "0", "0",</div><div class='add'>+			       "0", "1", "0",</div><div class='add'>+			       "0", "0", "-1";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	proximity@48 {</div><div class='add'>+		compatible = "sensortek,stk3310";</div><div class='add'>+		reg = &lt;0x48&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;tlmm&gt;;</div><div class='add'>+		interrupts = &lt;12 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;proximity_int_default&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gyroscope@68 {</div><div class='add'>+		compatible = "bosch,bmg160";</div><div class='add'>+		reg = &lt;0x68&gt;;</div><div class='add'>+		vdd-supply = &lt;&amp;pm8916_l17&gt;;</div><div class='add'>+		vddio-supply = &lt;&amp;pm8916_l6&gt;;</div><div class='add'>+		interrupt-parent = &lt;&amp;tlmm&gt;;</div><div class='add'>+		interrupts = &lt;97 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+			     &lt;98 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;gyro_int_default&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_i2c6 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	led-controller@68 {</div><div class='add'>+		compatible = "si-en,sn3190";</div><div class='add'>+		reg = &lt;0x68&gt;;</div><div class='add'>+		shutdown-gpios = &lt;&amp;tlmm 89 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;led_enable_default &amp;led_shutdown_default&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		led@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			led-max-microamp = &lt;5000&gt;;</div><div class='add'>+			function = LED_FUNCTION_INDICATOR;</div><div class='add'>+			color = &lt;LED_COLOR_ID_WHITE&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_uart2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;blsp_uart2_console_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;blsp_uart2_console_sleep&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mpss_mem {</div><div class='add'>+	reg = &lt;0x0 0x86800000 0x0 0x5000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8916_codec {</div><div class='add'>+	qcom,micbias1-ext-cap;</div><div class='add'>+	qcom,micbias-lvl = &lt;2800&gt;;</div><div class='add'>+	qcom,mbhc-vthreshold-low = &lt;75 100 120 180 500&gt;;</div><div class='add'>+	qcom,mbhc-vthreshold-high = &lt;75 100 120 180 500&gt;;</div><div class='add'>+	qcom,hphl-jack-type-normally-open;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8916_resin {</div><div class='add'>+	status = "okay";</div><div class='add'>+	linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8916_rpm_regulators {</div><div class='add'>+	pm8916_l17: l17 {</div><div class='add'>+		regulator-min-microvolt = &lt;2850000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;2850000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8916_vib {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;q6afedai {</div><div class='add'>+	dai@18 {</div><div class='add'>+		reg = &lt;SECONDARY_MI2S_RX&gt;;</div><div class='add'>+		qcom,sd-lines = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+	dai@22 {</div><div class='add'>+		reg = &lt;QUATERNARY_MI2S_RX&gt;;</div><div class='add'>+		qcom,sd-lines = &lt;0&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sdhc_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sdhc_2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdc2_default &amp;sdc2_cd_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;sdc2_sleep &amp;sdc2_cd_default&gt;;</div><div class='add'>+</div><div class='add'>+	cd-gpios = &lt;&amp;tlmm 38 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sound {</div><div class='add'>+	/* Add pin switches for speakers to allow disabling them individually */</div><div class='add'>+	model = "alcatel-idol3";</div><div class='add'>+	widgets =</div><div class='add'>+		"Speaker", "Speaker Top",</div><div class='add'>+		"Speaker", "Speaker Bottom";</div><div class='add'>+	pin-switches = "Speaker Top", "Speaker Bottom";</div><div class='add'>+	audio-routing =</div><div class='add'>+		"Speaker Top", "Speaker Top OUT",</div><div class='add'>+		"Speaker Bottom", "Speaker Bottom OUT",</div><div class='add'>+		"AMIC1", "MIC BIAS External1",</div><div class='add'>+		"AMIC2", "MIC BIAS Internal2",</div><div class='add'>+		"AMIC3", "MIC BIAS External1";</div><div class='add'>+</div><div class='add'>+	pinctrl-0 = &lt;&amp;cdc_pdm_default &amp;pri_mi2s_default &amp;pri_mi2s_ws_default &amp;sec_mi2s_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;cdc_pdm_sleep &amp;pri_mi2s_sleep &amp;pri_mi2s_ws_sleep &amp;sec_mi2s_sleep&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+</div><div class='add'>+	sound_link_backend2: backend2-dai-link {</div><div class='add'>+		link-name = "Quaternary MI2S";</div><div class='add'>+</div><div class='add'>+		cpu {</div><div class='add'>+			sound-dai = &lt;&amp;q6afedai QUATERNARY_MI2S_RX&gt;;</div><div class='add'>+		};</div><div class='add'>+		platform {</div><div class='add'>+			sound-dai = &lt;&amp;q6routing&gt;;</div><div class='add'>+		};</div><div class='add'>+		codec {</div><div class='add'>+			sound-dai = &lt;&amp;speaker_codec_top&gt;, &lt;&amp;speaker_codec_bottom&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sound_link_backend0 {</div><div class='add'>+	/* Primary MI2S is not used, replace with Secondary MI2S for headphones */</div><div class='add'>+	link-name = "Secondary MI2S";</div><div class='add'>+</div><div class='add'>+	cpu {</div><div class='add'>+		sound-dai = &lt;&amp;q6afedai SECONDARY_MI2S_RX&gt;;</div><div class='add'>+	};</div><div class='add'>+	platform {</div><div class='add'>+		sound-dai = &lt;&amp;q6routing&gt;;</div><div class='add'>+	};</div><div class='add'>+	codec {</div><div class='add'>+		sound-dai = &lt;&amp;headphones&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb {</div><div class='add'>+	status = "okay";</div><div class='add'>+	extcon = &lt;&amp;usb_id&gt;, &lt;&amp;usb_id&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_hs_phy {</div><div class='add'>+	extcon = &lt;&amp;usb_id&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;venus {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;venus_mem {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wcnss {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wcnss_iris {</div><div class='add'>+	compatible = "qcom,wcn3620";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wcnss_mem {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Only some of the pins are used */</div><div class='add'>+&amp;pri_mi2s_default {</div><div class='add'>+	pins = "gpio113", "gpio115";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pri_mi2s_sleep {</div><div class='add'>+	pins = "gpio113", "gpio115";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tlmm {</div><div class='add'>+	accel_int_default: accel-int-default-state {</div><div class='add'>+		pins = "gpio31";</div><div class='add'>+		function = "gpio";</div><div class='add'>+</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio_keys_default: gpio-keys-default-state {</div><div class='add'>+		pins = "gpio107";</div><div class='add'>+		function = "gpio";</div><div class='add'>+</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-pull-up;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio_leds_default: gpio-leds-default-state {</div><div class='add'>+		pins = "gpio32";</div><div class='add'>+		function = "gpio";</div><div class='add'>+</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gyro_int_default: gyro-int-default-state {</div><div class='add'>+		pins = "gpio97", "gpio98";</div><div class='add'>+		function = "gpio";</div><div class='add'>+</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	headphones_avdd_default: headphones-avdd-default-state {</div><div class='add'>+		pins = "gpio121";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	headphones_pdn_default: headphones-pdn-default-state {</div><div class='add'>+		pins = "gpio114";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * The OEM wired an additional GPIO to be asserted so that</div><div class='add'>+	 * the si-en,sn3190 LED IC works. Since this GPIO is not</div><div class='add'>+	 * part of the IC datasheet nor supported by the driver,</div><div class='add'>+	 * force it asserted here.</div><div class='add'>+	 */</div><div class='add'>+	led_enable_default: led-enable-default-state {</div><div class='add'>+		pins = "gpio102";</div><div class='add'>+		function = "gpio";</div><div class='add'>+</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+		output-high;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	led_shutdown_default: led-shutdown-default-state {</div><div class='add'>+		pins = "gpio89";</div><div class='add'>+		function = "gpio";</div><div class='add'>+</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mag_reset_default: mag-reset-default-state {</div><div class='add'>+		pins = "gpio8";</div><div class='add'>+		function = "gpio";</div><div class='add'>+</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	proximity_int_default: proximity-int-default-state {</div><div class='add'>+		pins = "gpio12";</div><div class='add'>+		function = "gpio";</div><div class='add'>+</div><div class='add'>+		drive-strength = &lt;6&gt;;</div><div class='add'>+		bias-pull-up;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdc2_cd_default: sdc2-cd-default-state {</div><div class='add'>+		pins = "gpio38";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	speaker_bottom_default: speaker-bottom-default-state {</div><div class='add'>+		pins = "gpio111";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	speaker_top_default: speaker-top-default-state {</div><div class='add'>+		pins = "gpio50";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ts_int_reset_default: ts-int-reset-default-state {</div><div class='add'>+		pins = "gpio13", "gpio100";</div><div class='add'>+		function = "gpio";</div><div class='add'>+</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb_id_default: usb-id-default-state {</div><div class='add'>+		pins = "gpio69";</div><div class='add'>+		function = "gpio";</div><div class='add'>+</div><div class='add'>+		drive-strength = &lt;8&gt;;</div><div class='add'>+		bias-pull-up;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts b/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts<br/>new file mode 100644<br/>index 000000000000..29d61f8d5dc9<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts</a></div><div class='hunk'>@@ -0,0 +1,272 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "msm8916-pm8916.dtsi"</div><div class='add'>+#include "msm8916-modem-qdsp6.dtsi"</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Asus Zenfone 2 Laser";</div><div class='add'>+	compatible = "asus,z00l", "qcom,msm8916";</div><div class='add'>+	chassis-type = "handset";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		mmc0 = &amp;sdhc_1; /* eMMC */</div><div class='add'>+		mmc1 = &amp;sdhc_2; /* SD card */</div><div class='add'>+		serial0 = &amp;blsp_uart2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;gpio_keys_default&gt;;</div><div class='add'>+</div><div class='add'>+		label = "GPIO Buttons";</div><div class='add'>+</div><div class='add'>+		button-volume-up {</div><div class='add'>+			label = "Volume Up";</div><div class='add'>+			gpios = &lt;&amp;tlmm 107 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+			debounce-interval = &lt;15&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		button-volume-down {</div><div class='add'>+			label = "Volume Down";</div><div class='add'>+			gpios = &lt;&amp;tlmm 117 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+			debounce-interval = &lt;15&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_sd_vmmc: regulator-sdcard-vmmc {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "sdcard-vmmc";</div><div class='add'>+		regulator-min-microvolt = &lt;2950000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;2950000&gt;;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;tlmm 87 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+</div><div class='add'>+		startup-delay-us = &lt;200&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;sd_vmmc_en_default&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb_id: usb-id {</div><div class='add'>+		compatible = "linux,extcon-usb-gpio";</div><div class='add'>+		id-gpios = &lt;&amp;tlmm 110 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;usb_id_default&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_i2c2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	magnetometer@c {</div><div class='add'>+		compatible = "asahi-kasei,ak09911";</div><div class='add'>+		reg = &lt;0x0c&gt;;</div><div class='add'>+</div><div class='add'>+		vdd-supply = &lt;&amp;pm8916_l8&gt;;</div><div class='add'>+		vid-supply = &lt;&amp;pm8916_l6&gt;;</div><div class='add'>+</div><div class='add'>+		reset-gpios = &lt;&amp;tlmm 112 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;mag_reset_default&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	imu@68 {</div><div class='add'>+		compatible = "invensense,mpu6515";</div><div class='add'>+		reg = &lt;0x68&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-parent = &lt;&amp;tlmm&gt;;</div><div class='add'>+		interrupts = &lt;36 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+</div><div class='add'>+		vdd-supply = &lt;&amp;pm8916_l17&gt;;</div><div class='add'>+		vddio-supply = &lt;&amp;pm8916_l6&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;imu_default&gt;;</div><div class='add'>+</div><div class='add'>+		mount-matrix = "1",  "0", "0",</div><div class='add'>+			       "0", "-1", "0",</div><div class='add'>+			       "0",  "0", "1";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_i2c5 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	touchscreen@38 {</div><div class='add'>+		compatible = "edt,edt-ft5306";</div><div class='add'>+		reg = &lt;0x38&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-parent = &lt;&amp;tlmm&gt;;</div><div class='add'>+		interrupts = &lt;13 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+</div><div class='add'>+		reset-gpios = &lt;&amp;tlmm 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		vcc-supply = &lt;&amp;pm8916_l11&gt;;</div><div class='add'>+		iovcc-supply = &lt;&amp;pm8916_l6&gt;;</div><div class='add'>+</div><div class='add'>+		touchscreen-size-x = &lt;720&gt;;</div><div class='add'>+		touchscreen-size-y = &lt;1280&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;touchscreen_default&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_uart2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;blsp_uart2_console_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;blsp_uart2_console_sleep&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mpss_mem {</div><div class='add'>+	reg = &lt;0x0 0x86800000 0x0 0x5500000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8916_codec {</div><div class='add'>+	qcom,micbias-lvl = &lt;2800&gt;;</div><div class='add'>+	qcom,mbhc-vthreshold-low = &lt;75 150 237 450 500&gt;;</div><div class='add'>+	qcom,mbhc-vthreshold-high = &lt;75 150 237 450 500&gt;;</div><div class='add'>+	qcom,micbias1-ext-cap;</div><div class='add'>+	qcom,hphl-jack-type-normally-open;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8916_rpm_regulators {</div><div class='add'>+	pm8916_l17: l17 {</div><div class='add'>+		regulator-min-microvolt = &lt;2850000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;2850000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sdhc_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sdhc_2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_sd_vmmc&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdc2_default &amp;sdc2_cd_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;sdc2_sleep &amp;sdc2_cd_default&gt;;</div><div class='add'>+	cd-gpios = &lt;&amp;tlmm 38 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sound {</div><div class='add'>+	audio-routing =</div><div class='add'>+		"AMIC1", "MIC BIAS External1",</div><div class='add'>+		"AMIC2", "MIC BIAS Internal2",</div><div class='add'>+		"AMIC3", "MIC BIAS External1";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb {</div><div class='add'>+	status = "okay";</div><div class='add'>+	extcon = &lt;&amp;usb_id&gt;, &lt;&amp;usb_id&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_hs_phy {</div><div class='add'>+	extcon = &lt;&amp;usb_id&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;venus {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;venus_mem {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wcnss {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wcnss_iris {</div><div class='add'>+	compatible = "qcom,wcn3620";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wcnss_mem {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tlmm {</div><div class='add'>+	gpio_keys_default: gpio-keys-default-state {</div><div class='add'>+		pins = "gpio107", "gpio117";</div><div class='add'>+		function = "gpio";</div><div class='add'>+</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-pull-up;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	imu_default: imu-default-state {</div><div class='add'>+		pins = "gpio36";</div><div class='add'>+		function = "gpio";</div><div class='add'>+</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mag_reset_default: mag-reset-default-state {</div><div class='add'>+		pins = "gpio112";</div><div class='add'>+		function = "gpio";</div><div class='add'>+</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd_vmmc_en_default: sd-vmmc-en-default-state {</div><div class='add'>+		pins = "gpio87";</div><div class='add'>+		function = "gpio";</div><div class='add'>+</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdc2_cd_default: sdc2-cd-default-state {</div><div class='add'>+		pins = "gpio38";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	touchscreen_default: touchscreen-default-state {</div><div class='add'>+		touch-pins {</div><div class='add'>+			pins = "gpio13";</div><div class='add'>+			function = "gpio";</div><div class='add'>+</div><div class='add'>+			drive-strength = &lt;2&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		reset-pins {</div><div class='add'>+			pins = "gpio12";</div><div class='add'>+			function = "gpio";</div><div class='add'>+</div><div class='add'>+			drive-strength = &lt;2&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb_id_default: usb-id-default-state {</div><div class='add'>+		pins = "gpio110";</div><div class='add'>+		function = "gpio";</div><div class='add'>+</div><div class='add'>+		drive-strength = &lt;8&gt;;</div><div class='add'>+		bias-pull-up;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts b/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts<br/>new file mode 100644<br/>index 000000000000..742a325245c5<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts</a></div><div class='hunk'>@@ -0,0 +1,274 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "msm8916-pm8916.dtsi"</div><div class='add'>+#include "msm8916-modem-qdsp6.dtsi"</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "GPLUS FL8005A";</div><div class='add'>+	compatible = "gplus,fl8005a", "qcom,msm8916";</div><div class='add'>+	chassis-type = "tablet";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		mmc0 = &amp;sdhc_1; /* eMMC */</div><div class='add'>+		mmc1 = &amp;sdhc_2; /* SD card */</div><div class='add'>+		serial0 = &amp;blsp_uart2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	battery: battery {</div><div class='add'>+		compatible = "simple-battery";</div><div class='add'>+		device-chemistry = "lithium-ion-polymer";</div><div class='add'>+		voltage-min-design-microvolt = &lt;3700000&gt;;</div><div class='add'>+		voltage-max-design-microvolt = &lt;4200000&gt;;</div><div class='add'>+		energy-full-design-microwatt-hours = &lt;13690000&gt;;</div><div class='add'>+		charge-full-design-microamp-hours = &lt;3700000&gt;;</div><div class='add'>+</div><div class='add'>+		ocv-capacity-celsius = &lt;25&gt;;</div><div class='add'>+		ocv-capacity-table-0 =</div><div class='add'>+			&lt;4186000 100&gt;, &lt;4126000 95&gt;, &lt;4078000 90&gt;,</div><div class='add'>+			&lt;4036000 85&gt;, &lt;3997000 80&gt;, &lt;3962000 75&gt;,</div><div class='add'>+			&lt;3932000 70&gt;, &lt;3904000 65&gt;, &lt;3874000 60&gt;,</div><div class='add'>+			&lt;3839000 55&gt;, &lt;3809000 50&gt;, &lt;3792000 45&gt;,</div><div class='add'>+			&lt;3780000 40&gt;, &lt;3772000 35&gt;, &lt;3764000 30&gt;,</div><div class='add'>+			&lt;3752000 25&gt;, &lt;3731000 20&gt;, &lt;3704000 16&gt;,</div><div class='add'>+			&lt;3677000 13&gt;, &lt;3670000 11&gt;, &lt;3668000 10&gt;,</div><div class='add'>+			&lt;3666000 9&gt;, &lt;3662000 8&gt;, &lt;3658000 7&gt;, &lt;3648000 6&gt;,</div><div class='add'>+			&lt;3624000 5&gt;, &lt;3580000 4&gt;, &lt;3518000 3&gt;, &lt;3434000 2&gt;,</div><div class='add'>+			&lt;3310000 1&gt;, &lt;3000000 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	flash-led-controller {</div><div class='add'>+		/* Actually qcom,leds-gpio-flash */</div><div class='add'>+		compatible = "sgmicro,sgm3140";</div><div class='add'>+		enable-gpios = &lt;&amp;tlmm 31 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		flash-gpios = &lt;&amp;tlmm 32 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;camera_flash_default&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		flash_led: led {</div><div class='add'>+			function = LED_FUNCTION_FLASH;</div><div class='add'>+			color = &lt;LED_COLOR_ID_WHITE&gt;;</div><div class='add'>+			flash-max-timeout-us = &lt;250000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;gpio_keys_default&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		button-volume-up {</div><div class='add'>+			label = "Volume Up";</div><div class='add'>+			gpios = &lt;&amp;tlmm 107 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;gpio_leds_default&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		led-red {</div><div class='add'>+			function = LED_FUNCTION_CHARGING;</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			gpios = &lt;&amp;tlmm 117 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			retain-state-suspended;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-green {</div><div class='add'>+			function = LED_FUNCTION_CHARGING;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			gpios = &lt;&amp;tlmm 118 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			retain-state-suspended;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb_id: usb-id {</div><div class='add'>+		compatible = "linux,extcon-usb-gpio";</div><div class='add'>+		id-gpios = &lt;&amp;tlmm 110 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;usb_id_default&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_i2c5 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	touchscreen@38 {</div><div class='add'>+		/* Actually ft5402 */</div><div class='add'>+		compatible = "edt,edt-ft5406";</div><div class='add'>+		reg = &lt;0x38&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-parent = &lt;&amp;tlmm&gt;;</div><div class='add'>+		interrupts = &lt;13 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+</div><div class='add'>+		reset-gpios = &lt;&amp;tlmm 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		vcc-supply = &lt;&amp;pm8916_l17&gt;;</div><div class='add'>+		iovcc-supply = &lt;&amp;pm8916_l6&gt;;</div><div class='add'>+</div><div class='add'>+		touchscreen-size-x = &lt;800&gt;;</div><div class='add'>+		touchscreen-size-y = &lt;500&gt;;</div><div class='add'>+		touchscreen-inverted-x;</div><div class='add'>+		touchscreen-swapped-x-y;</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;touchscreen_default&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_uart2 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;blsp_uart2_console_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;blsp_uart2_console_sleep&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mpss_mem {</div><div class='add'>+	reg = &lt;0x0 0x86800000 0x0 0x5000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8916_bms {</div><div class='add'>+	monitored-battery = &lt;&amp;battery&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8916_codec {</div><div class='add'>+	qcom,micbias-lvl = &lt;2800&gt;;</div><div class='add'>+	qcom,mbhc-vthreshold-low = &lt;150 180 237 450 500&gt;;</div><div class='add'>+	qcom,mbhc-vthreshold-high = &lt;150 180 237 450 500&gt;;</div><div class='add'>+	qcom,hphl-jack-type-normally-open;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8916_resin {</div><div class='add'>+	linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8916_rpm_regulators {</div><div class='add'>+	pm8916_l17: l17 {</div><div class='add'>+		regulator-min-microvolt = &lt;2850000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;2850000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8916_vib {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sdhc_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sdhc_2 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdc2_default &amp;sdc2_cd_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;sdc2_sleep &amp;sdc2_cd_default&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+</div><div class='add'>+	cd-gpios = &lt;&amp;tlmm 38 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sound {</div><div class='add'>+	model = "msm8916-1mic";</div><div class='add'>+	audio-routing =</div><div class='add'>+		"AMIC1", "MIC BIAS External1",</div><div class='add'>+		"AMIC2", "MIC BIAS Internal2",</div><div class='add'>+		"AMIC3", "MIC BIAS External1";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb {</div><div class='add'>+	extcon = &lt;&amp;usb_id&gt;, &lt;&amp;usb_id&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_hs_phy {</div><div class='add'>+	extcon = &lt;&amp;usb_id&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;venus {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;venus_mem {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wcnss {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wcnss_iris {</div><div class='add'>+	compatible = "qcom,wcn3620";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wcnss_mem {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tlmm {</div><div class='add'>+	camera_flash_default: camera-flash-default-state {</div><div class='add'>+		pins = "gpio31", "gpio32";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio_keys_default: gpio-keys-default-state {</div><div class='add'>+		pins = "gpio107";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-pull-up;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio_leds_default: gpio-led-default-state {</div><div class='add'>+		pins = "gpio117", "gpio118";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdc2_cd_default: sdc2-cd-default-state {</div><div class='add'>+		pins = "gpio38";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	touchscreen_default: touchscreen-default-state {</div><div class='add'>+		reset-pins {</div><div class='add'>+			pins = "gpio12";</div><div class='add'>+			function = "gpio";</div><div class='add'>+			drive-strength = &lt;2&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		touchscreen-pins {</div><div class='add'>+			pins = "gpio13";</div><div class='add'>+			function = "gpio";</div><div class='add'>+			drive-strength = &lt;2&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb_id_default: usb-id-default-state {</div><div class='add'>+		pins = "gpio110";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;8&gt;;</div><div class='add'>+		bias-pull-up;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts<br/>new file mode 100644<br/>index 000000000000..aa414b5d7ee4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts</a></div><div class='hunk'>@@ -0,0 +1,434 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2021 Stephan Gerhold</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "msm8916-pm8916.dtsi"</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/sound/apq8016-lpass.h&gt;</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Note: The original firmware from Huawei can only boot 32-bit kernels.</div><div class='add'>+ * To boot this device tree using arm64 it is necessary to flash 64-bit TZ/HYP</div><div class='add'>+ * firmware (e.g. taken from the DragonBoard 410c).</div><div class='add'>+ * See https://wiki.postmarketos.org/wiki/Huawei_Ascend_G7_(huawei-g7)</div><div class='add'>+ * for suggested installation instructions.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "Huawei Ascend G7";</div><div class='add'>+	compatible = "huawei,g7", "qcom,msm8916";</div><div class='add'>+	chassis-type = "handset";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		mmc0 = &amp;sdhc_1; /* eMMC */</div><div class='add'>+		mmc1 = &amp;sdhc_2; /* SD card */</div><div class='add'>+		serial0 = &amp;blsp_uart2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;gpio_keys_default&gt;;</div><div class='add'>+</div><div class='add'>+		label = "GPIO Buttons";</div><div class='add'>+</div><div class='add'>+		button-volume-up {</div><div class='add'>+			label = "Volume Up";</div><div class='add'>+			gpios = &lt;&amp;tlmm 107 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;gpio_leds_default&gt;;</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			gpios = &lt;&amp;tlmm 8 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+			function = LED_FUNCTION_INDICATOR;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-1 {</div><div class='add'>+			gpios = &lt;&amp;tlmm 9 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+			function = LED_FUNCTION_INDICATOR;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		led-2 {</div><div class='add'>+			gpios = &lt;&amp;tlmm 10 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+			function = LED_FUNCTION_INDICATOR;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb_id: usb-id {</div><div class='add'>+		compatible = "linux,extcon-usb-gpio";</div><div class='add'>+		id-gpios = &lt;&amp;tlmm 117 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;usb_id_default&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_i2c2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	magnetometer@c {</div><div class='add'>+		compatible = "asahi-kasei,ak09911";</div><div class='add'>+		reg = &lt;0x0c&gt;;</div><div class='add'>+</div><div class='add'>+		vdd-supply = &lt;&amp;pm8916_l17&gt;;</div><div class='add'>+		vid-supply = &lt;&amp;pm8916_l6&gt;;</div><div class='add'>+</div><div class='add'>+		reset-gpios = &lt;&amp;tlmm 36 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;mag_reset_default&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	accelerometer@1e {</div><div class='add'>+		compatible = "kionix,kx023-1025";</div><div class='add'>+		reg = &lt;0x1e&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-parent = &lt;&amp;tlmm&gt;;</div><div class='add'>+		interrupts = &lt;115 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+</div><div class='add'>+		vdd-supply = &lt;&amp;pm8916_l17&gt;;</div><div class='add'>+		vddio-supply = &lt;&amp;pm8916_l6&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;accel_irq_default&gt;;</div><div class='add'>+</div><div class='add'>+		mount-matrix = "-1", "0", "0",</div><div class='add'>+				"0", "1", "0",</div><div class='add'>+				"0", "0", "1";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	proximity@39 {</div><div class='add'>+		compatible = "avago,apds9930";</div><div class='add'>+		reg = &lt;0x39&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-parent = &lt;&amp;tlmm&gt;;</div><div class='add'>+		interrupts = &lt;113 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+</div><div class='add'>+		vdd-supply = &lt;&amp;pm8916_l17&gt;;</div><div class='add'>+		vddio-supply = &lt;&amp;pm8916_l6&gt;;</div><div class='add'>+</div><div class='add'>+		led-max-microamp = &lt;100000&gt;;</div><div class='add'>+		amstaos,proximity-diodes = &lt;1&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;prox_irq_default&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	regulator@3e {</div><div class='add'>+		compatible = "ti,tps65132";</div><div class='add'>+		reg = &lt;0x3e&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;reg_lcd_en_default&gt;;</div><div class='add'>+</div><div class='add'>+		reg_lcd_pos: outp {</div><div class='add'>+			regulator-name = "outp";</div><div class='add'>+			regulator-min-microvolt = &lt;5400000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;5400000&gt;;</div><div class='add'>+			enable-gpios = &lt;&amp;tlmm 97 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			regulator-active-discharge = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		reg_lcd_neg: outn {</div><div class='add'>+			regulator-name = "outn";</div><div class='add'>+			regulator-min-microvolt = &lt;5400000&gt;;</div><div class='add'>+			regulator-max-microvolt = &lt;5400000&gt;;</div><div class='add'>+			enable-gpios = &lt;&amp;tlmm 32 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			regulator-active-discharge = &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_i2c5 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	rmi4@70 {</div><div class='add'>+		compatible = "syna,rmi4-i2c";</div><div class='add'>+		reg = &lt;0x70&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-parent = &lt;&amp;tlmm&gt;;</div><div class='add'>+		interrupts = &lt;13 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+</div><div class='add'>+		vdd-supply = &lt;&amp;pm8916_l17&gt;;</div><div class='add'>+		vio-supply = &lt;&amp;pm8916_l16&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;ts_irq_default&gt;;</div><div class='add'>+</div><div class='add'>+		syna,startup-delay-ms = &lt;100&gt;;</div><div class='add'>+</div><div class='add'>+		rmi4-f01@1 {</div><div class='add'>+			reg = &lt;0x1&gt;;</div><div class='add'>+			syna,nosleep-mode = &lt;1&gt;; /* Allow sleeping */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		rmi4-f11@11 {</div><div class='add'>+			reg = &lt;0x11&gt;;</div><div class='add'>+			syna,sensor-type = &lt;1&gt;; /* Touchscreen */</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_i2c6 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	nfc@28 {</div><div class='add'>+		compatible = "nxp,pn547", "nxp,nxp-nci-i2c";</div><div class='add'>+		reg = &lt;0x28&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-parent = &lt;&amp;tlmm&gt;;</div><div class='add'>+		interrupts = &lt;21 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+</div><div class='add'>+		enable-gpios = &lt;&amp;tlmm 20 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		firmware-gpios = &lt;&amp;tlmm 2 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;nfc_default&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_uart2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;blsp_uart2_console_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;blsp_uart2_console_sleep&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpass {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;lpass_codec {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8916_codec {</div><div class='add'>+	status = "okay";</div><div class='add'>+	qcom,micbias-lvl = &lt;2800&gt;;</div><div class='add'>+	qcom,mbhc-vthreshold-low = &lt;75 150 237 450 500&gt;;</div><div class='add'>+	qcom,mbhc-vthreshold-high = &lt;75 150 237 450 500&gt;;</div><div class='add'>+	qcom,hphl-jack-type-normally-open;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8916_l8 {</div><div class='add'>+	regulator-min-microvolt = &lt;2950000&gt;;</div><div class='add'>+	regulator-max-microvolt = &lt;2950000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8916_resin {</div><div class='add'>+	status = "okay";</div><div class='add'>+	linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8916_rpm_regulators {</div><div class='add'>+	pm8916_l16: l16 {</div><div class='add'>+		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	pm8916_l17: l17 {</div><div class='add'>+		regulator-min-microvolt = &lt;2850000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;2850000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8916_vib {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sdhc_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sdhc_2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdc2_default &amp;sdc2_cd_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;sdc2_sleep &amp;sdc2_cd_default&gt;;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * The Huawei device tree sets cd-gpios = &lt;&amp;tlmm 38 GPIO_ACTIVE_HIGH&gt;.</div><div class='add'>+	 * However, gpio38 does not change its state when inserting/removing the</div><div class='add'>+	 * SD card, it's just low all the time. The Huawei kernel seems to use</div><div class='add'>+	 * polling for SD card detection instead.</div><div class='add'>+	 *</div><div class='add'>+	 * However, looking closer at the GPIO debug output it turns out that</div><div class='add'>+	 * gpio56 switches its state when inserting/removing the SD card.</div><div class='add'>+	 * It behaves just like gpio38 normally does. Usually GPIO56 is used as</div><div class='add'>+	 * "UIM2_PRESENT", i.e. to check if a second SIM card is inserted.</div><div class='add'>+	 * Maybe Huawei decided to replace the second SIM card slot with the</div><div class='add'>+	 * SD card slot and forgot to re-route to gpio38.</div><div class='add'>+	 */</div><div class='add'>+	cd-gpios = &lt;&amp;tlmm 56 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sound {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	model = "msm8916";</div><div class='add'>+	audio-routing =</div><div class='add'>+		"AMIC1", "MIC BIAS External1",</div><div class='add'>+		"AMIC2", "MIC BIAS External2",</div><div class='add'>+		"AMIC3", "MIC BIAS External1";</div><div class='add'>+</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;cdc_pdm_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;cdc_pdm_sleep&gt;;</div><div class='add'>+</div><div class='add'>+	primary-dai-link {</div><div class='add'>+		link-name = "WCD";</div><div class='add'>+		cpu {</div><div class='add'>+			sound-dai = &lt;&amp;lpass MI2S_PRIMARY&gt;;</div><div class='add'>+		};</div><div class='add'>+		codec {</div><div class='add'>+			sound-dai = &lt;&amp;lpass_codec 0&gt;, &lt;&amp;pm8916_codec 0&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	tertiary-dai-link {</div><div class='add'>+		link-name = "WCD-Capture";</div><div class='add'>+		cpu {</div><div class='add'>+			sound-dai = &lt;&amp;lpass MI2S_TERTIARY&gt;;</div><div class='add'>+		};</div><div class='add'>+		codec {</div><div class='add'>+			sound-dai = &lt;&amp;lpass_codec 1&gt;, &lt;&amp;pm8916_codec 1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb {</div><div class='add'>+	status = "okay";</div><div class='add'>+	extcon = &lt;&amp;usb_id&gt;, &lt;&amp;usb_id&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_hs_phy {</div><div class='add'>+	extcon = &lt;&amp;usb_id&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;venus {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;venus_mem {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wcnss {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wcnss_iris {</div><div class='add'>+	compatible = "qcom,wcn3620";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wcnss_mem {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tlmm {</div><div class='add'>+	accel_irq_default: accel-irq-default-state {</div><div class='add'>+		pins = "gpio115";</div><div class='add'>+		function = "gpio";</div><div class='add'>+</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio_keys_default: gpio-keys-default-state {</div><div class='add'>+		pins = "gpio107";</div><div class='add'>+		function = "gpio";</div><div class='add'>+</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-pull-up;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio_leds_default: gpio-leds-default-state {</div><div class='add'>+		pins = "gpio8", "gpio9", "gpio10";</div><div class='add'>+		function = "gpio";</div><div class='add'>+</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	nfc_default: nfc-default-state {</div><div class='add'>+		pins = "gpio2", "gpio20", "gpio21";</div><div class='add'>+		function = "gpio";</div><div class='add'>+</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mag_reset_default: mag-reset-default-state {</div><div class='add'>+		pins = "gpio36";</div><div class='add'>+		function = "gpio";</div><div class='add'>+</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	prox_irq_default: prox-irq-default-state {</div><div class='add'>+		pins = "gpio113";</div><div class='add'>+		function = "gpio";</div><div class='add'>+</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_lcd_en_default: reg-lcd-en-default-state {</div><div class='add'>+		pins = "gpio32", "gpio97";</div><div class='add'>+		function = "gpio";</div><div class='add'>+</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdc2_cd_default: sdc2-cd-default-state {</div><div class='add'>+		pins = "gpio56";</div><div class='add'>+		function = "gpio";</div><div class='add'>+</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ts_irq_default: ts-irq-default-state {</div><div class='add'>+		pins = "gpio13";</div><div class='add'>+		function = "gpio";</div><div class='add'>+</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb_id_default: usb-id-default-state {</div><div class='add'>+		pins = "gpio117";</div><div class='add'>+		function = "gpio";</div><div class='add'>+</div><div class='add'>+		drive-strength = &lt;8&gt;;</div><div class='add'>+		bias-pull-up;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/msm8916-lg-c50.dts b/arch/arm64/boot/dts/qcom/msm8916-lg-c50.dts<br/>new file mode 100644<br/>index 000000000000..22bc73b94344<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/msm8916-lg-c50.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/msm8916-lg-c50.dts</a></div><div class='hunk'>@@ -0,0 +1,143 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "msm8916-pm8916.dtsi"</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "LG Leon LTE";</div><div class='add'>+	compatible = "lg,c50", "qcom,msm8916";</div><div class='add'>+	chassis-type = "handset";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		mmc0 = &amp;sdhc_1; /* eMMC */</div><div class='add'>+		mmc1 = &amp;sdhc_2; /* SD card */</div><div class='add'>+		serial0 = &amp;blsp_uart2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;gpio_keys_default&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		label = "GPIO Buttons";</div><div class='add'>+</div><div class='add'>+		volume-up-button {</div><div class='add'>+			label = "Volume Up";</div><div class='add'>+			gpios = &lt;&amp;tlmm 108 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		volume-down-button {</div><div class='add'>+			label = "Volume Down";</div><div class='add'>+			gpios = &lt;&amp;tlmm 107 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_sd_vmmc: regulator-sdcard-vmmc {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "sdcard-vmmc";</div><div class='add'>+		regulator-min-microvolt = &lt;2950000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;2950000&gt;;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;tlmm 60 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+</div><div class='add'>+		startup-delay-us = &lt;5000&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;sd_vmmc_en_default&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_uart2 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;blsp_uart2_console_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;blsp_uart2_console_sleep&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8916_usbin {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8916_vib {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sdhc_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sdhc_2 {</div><div class='add'>+	vmmc-supply = &lt;&amp;reg_sd_vmmc&gt;;</div><div class='add'>+</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdc2_default &amp;sdc2_cd_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;sdc2_sleep &amp;sdc2_cd_default&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+</div><div class='add'>+	cd-gpios = &lt;&amp;tlmm 38 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb {</div><div class='add'>+	dr_mode = "peripheral";</div><div class='add'>+	extcon = &lt;&amp;pm8916_usbin&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_hs_phy {</div><div class='add'>+	extcon = &lt;&amp;pm8916_usbin&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;venus {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;venus_mem {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wcnss {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wcnss_iris {</div><div class='add'>+	compatible = "qcom,wcn3620";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wcnss_mem {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tlmm {</div><div class='add'>+	gpio_keys_default: gpio-keys-default-state {</div><div class='add'>+		pins = "gpio107", "gpio108";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-pull-up;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sd_vmmc_en_default: sd-vmmc-en-default-state {</div><div class='add'>+		pins = "gpio60";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdc2_cd_default: sdc2-cd-default-state {</div><div class='add'>+		pins = "gpio38";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-pull-down;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/msm8916-lg-m216.dts b/arch/arm64/boot/dts/qcom/msm8916-lg-m216.dts<br/>new file mode 100644<br/>index 000000000000..c50374979939<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/msm8916-lg-m216.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/msm8916-lg-m216.dts</a></div><div class='hunk'>@@ -0,0 +1,254 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "msm8916-pm8916.dtsi"</div><div class='add'>+#include "msm8916-modem-qdsp6.dtsi"</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "LG K10 (K420n)";</div><div class='add'>+	compatible = "lg,m216", "qcom,msm8916";</div><div class='add'>+	chassis-type = "handset";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		mmc0 = &amp;sdhc_1; /* eMMC */</div><div class='add'>+		mmc1 = &amp;sdhc_2; /* SD card */</div><div class='add'>+		serial0 = &amp;blsp_uart2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	battery: battery {</div><div class='add'>+		compatible = "simple-battery";</div><div class='add'>+		voltage-min-design-microvolt = &lt;3300000&gt;;</div><div class='add'>+		voltage-max-design-microvolt = &lt;4350000&gt;;</div><div class='add'>+		energy-full-design-microwatt-hours = &lt;8800000&gt;;</div><div class='add'>+		charge-full-design-microamp-hours = &lt;2300000&gt;;</div><div class='add'>+</div><div class='add'>+		ocv-capacity-celsius = &lt;25&gt;;</div><div class='add'>+		ocv-capacity-table-0 = &lt;4342000 100&gt;, &lt;4266000 95&gt;, &lt;4206000 90&gt;,</div><div class='add'>+			&lt;4148000 85&gt;, &lt;4094000 80&gt;, &lt;4046000 75&gt;, &lt;3994000 70&gt;,</div><div class='add'>+			&lt;3956000 65&gt;, &lt;3916000 60&gt;, &lt;3866000 55&gt;, &lt;3831000 50&gt;,</div><div class='add'>+			&lt;3808000 45&gt;, &lt;3789000 40&gt;, &lt;3776000 35&gt;, &lt;3769000 30&gt;,</div><div class='add'>+			&lt;3760000 25&gt;, &lt;3740000 20&gt;, &lt;3712000 16&gt;, &lt;3684000 13&gt;,</div><div class='add'>+			&lt;3676000 11&gt;, &lt;3674000 10&gt;, &lt;3672000 9&gt;, &lt;3669000 8&gt;,</div><div class='add'>+			&lt;3665000 7&gt;, &lt;3660000 6&gt;, &lt;3643000 5&gt;, &lt;3602000 4&gt;,</div><div class='add'>+			&lt;3542000 3&gt;, &lt;3458000 2&gt;, &lt;3326000 1&gt;, &lt;3000000 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;gpio_keys_default&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		label = "GPIO Buttons";</div><div class='add'>+</div><div class='add'>+		volume-up-button {</div><div class='add'>+			label = "Volume Up";</div><div class='add'>+			gpios = &lt;&amp;tlmm 107 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		volume-down-button {</div><div class='add'>+			label = "Volume Down";</div><div class='add'>+			gpios = &lt;&amp;tlmm 108 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_i2c2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	accelerometer@11 {</div><div class='add'>+		compatible = "bosch,bmc150_accel";</div><div class='add'>+		reg = &lt;0x11&gt;;</div><div class='add'>+</div><div class='add'>+		interrupts-extended = &lt;&amp;tlmm 115 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+</div><div class='add'>+		mount-matrix =	 "0", "1", "0",</div><div class='add'>+				"-1", "0", "0",</div><div class='add'>+				 "0", "0", "1";</div><div class='add'>+</div><div class='add'>+		vdd-supply = &lt;&amp;pm8916_l17&gt;;</div><div class='add'>+		vddio-supply = &lt;&amp;pm8916_l6&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;accel_int_default&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	magnetometer@13 {</div><div class='add'>+		compatible = "bosch,bmc150_magn";</div><div class='add'>+		reg = &lt;0x13&gt;;</div><div class='add'>+</div><div class='add'>+		interrupts-extended = &lt;&amp;tlmm 69 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+</div><div class='add'>+		vdd-supply = &lt;&amp;pm8916_l17&gt;;</div><div class='add'>+		vddio-supply = &lt;&amp;pm8916_l6&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;magn_int_default&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_i2c5 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	touchscreen@34 {</div><div class='add'>+		compatible = "melfas,mip4_ts";</div><div class='add'>+		reg = &lt;0x34&gt;;</div><div class='add'>+</div><div class='add'>+		interrupts-extended = &lt;&amp;tlmm 13 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+		ce-gpios = &lt;&amp;tlmm 12 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;touchscreen_default&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_uart2 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;blsp_uart2_console_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;blsp_uart2_console_sleep&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mpss_mem {</div><div class='add'>+	reg = &lt;0x0 0x86800000 0x0 0x4a00000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8916_bms {</div><div class='add'>+	monitored-battery = &lt;&amp;battery&gt;;</div><div class='add'>+	power-supplies = &lt;&amp;pm8916_charger&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8916_charger {</div><div class='add'>+	qcom,fast-charge-safe-current = &lt;700000&gt;;</div><div class='add'>+	qcom,fast-charge-safe-voltage = &lt;4300000&gt;;</div><div class='add'>+</div><div class='add'>+	monitored-battery = &lt;&amp;battery&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8916_codec {</div><div class='add'>+	qcom,micbias1-ext-cap;</div><div class='add'>+	qcom,micbias-lvl = &lt;2800&gt;;</div><div class='add'>+	qcom,mbhc-vthreshold-low = &lt;75 100 120 180 500&gt;;</div><div class='add'>+	qcom,mbhc-vthreshold-high = &lt;75 100 120 180 500&gt;;</div><div class='add'>+	qcom,hphl-jack-type-normally-open;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8916_rpm_regulators {</div><div class='add'>+	pm8916_l17: l17 {</div><div class='add'>+		regulator-min-microvolt = &lt;2850000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;2850000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8916_vib {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sdhc_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sdhc_2 {</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdc2_default &amp;sdc2_cd_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;sdc2_sleep &amp;sdc2_cd_default&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+</div><div class='add'>+	cd-gpios = &lt;&amp;tlmm 38 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sound {</div><div class='add'>+	audio-routing =</div><div class='add'>+		"AMIC1", "MIC BIAS External1",</div><div class='add'>+		"AMIC2", "MIC BIAS Internal2",</div><div class='add'>+		"AMIC3", "MIC BIAS External1";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb {</div><div class='add'>+	dr_mode = "peripheral";</div><div class='add'>+	extcon = &lt;&amp;pm8916_charger&gt;;</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_hs_phy {</div><div class='add'>+	extcon = &lt;&amp;pm8916_charger&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;venus {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;venus_mem {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wcnss {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wcnss_iris {</div><div class='add'>+	compatible = "qcom,wcn3620";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wcnss_mem {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tlmm {</div><div class='add'>+	accel_int_default: accel-int-default-state {</div><div class='add'>+		pins = "gpio115";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio_keys_default: gpio-keys-default-state {</div><div class='add'>+		pins = "gpio107", "gpio108";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-pull-up;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	magn_int_default: magn-int-default-state {</div><div class='add'>+		pins = "gpio69";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdc2_cd_default: sdc2-cd-default-state {</div><div class='add'>+		pins = "gpio38";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	touchscreen_default: touchscreen-default-state {</div><div class='add'>+		touchscreen-pins {</div><div class='add'>+			pins = "gpio13";</div><div class='add'>+			function = "gpio";</div><div class='add'>+			drive-strength = &lt;2&gt;;</div><div class='add'>+			bias-pull-up;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		ce-pins {</div><div class='add'>+			pins = "gpio12";</div><div class='add'>+			function = "gpio";</div><div class='add'>+			drive-strength = &lt;2&gt;;</div><div class='add'>+			bias-disable;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts<br/>index d1ccb9472c8b..eb449112a226 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts?id=539979b6ec62f7bba40b0452b0574a0f4ec4fe4e'>arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts</a></div><div class='hunk'>@@ -2,282 +2,410 @@</div><div class='ctx'> </div><div class='ctx'> /dts-v1/;</div><div class='ctx'> </div><div class='del'>-#include "msm8916.dtsi"</div><div class='del'>-#include "pm8916.dtsi"</div><div class='add'>+#include "msm8916-pm8916.dtsi"</div><div class='add'>+#include "msm8916-modem-qdsp6.dtsi"</div><div class='add'>+</div><div class='ctx'> #include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interrupt-controller/irq.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='ctx'> </div><div class='ctx'> / {</div><div class='ctx'> 	model = "Longcheer L8150";</div><div class='del'>-	compatible = "longcheer,l8150", "qcom,msm8916-v1-qrd/9-v1", "qcom,msm8916";</div><div class='add'>+	compatible = "longcheer,l8150", "qcom,msm8916";</div><div class='add'>+	chassis-type = "handset";</div><div class='ctx'> </div><div class='ctx'> 	aliases {</div><div class='del'>-		serial0 = &amp;blsp1_uart2;</div><div class='add'>+		mmc0 = &amp;sdhc_1; /* eMMC */</div><div class='add'>+		mmc1 = &amp;sdhc_2; /* SD card */</div><div class='add'>+		serial0 = &amp;blsp_uart2;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	chosen {</div><div class='ctx'> 		stdout-path = "serial0";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * For some reason, the signed wcnss firmware is not relocatable.</div><div class='add'>+	 * It must be loaded at 0x8b600000. Unfortunately, this also means that</div><div class='add'>+	 * mpss_mem does not fit when loaded to the typical address at 0x86800000.</div><div class='add'>+	 *</div><div class='add'>+	 * Load wcnss_mem to the fixed address and relocate mpss_mem to the next</div><div class='add'>+	 * working higher address. For some reason the modem firmware does not</div><div class='add'>+	 * boot when placed at 0x8a800000 to 0x8e800000.</div><div class='add'>+	 */</div><div class='ctx'> 	reserved-memory {</div><div class='del'>-		// wcnss.mdt is not relocatable, so it must be loaded at 0x8b600000</div><div class='del'>-		/delete-node/ wcnss@89300000;</div><div class='add'>+		/delete-node/ mpss@86800000;</div><div class='add'>+		/delete-node/ wcnss;</div><div class='ctx'> </div><div class='ctx'> 		wcnss_mem: wcnss@8b600000 {</div><div class='ctx'> 			reg = &lt;0x0 0x8b600000 0x0 0x600000&gt;;</div><div class='ctx'> 			no-map;</div><div class='ctx'> 		};</div><div class='add'>+</div><div class='add'>+		mpss_mem: mpss@8e800000 {</div><div class='add'>+			reg = &lt;0x0 0x8e800000 0x0 0x5000000&gt;;</div><div class='add'>+			no-map;</div><div class='add'>+		};</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	soc {</div><div class='del'>-		sdhci@7824000 {</div><div class='del'>-			status = "okay";</div><div class='add'>+	battery: battery {</div><div class='add'>+		compatible = "simple-battery";</div><div class='add'>+		voltage-min-design-microvolt = &lt;3400000&gt;;</div><div class='add'>+		voltage-max-design-microvolt = &lt;4350000&gt;;</div><div class='add'>+		energy-full-design-microwatt-hours = &lt;9500000&gt;;</div><div class='add'>+		charge-full-design-microamp-hours = &lt;2500000&gt;;</div><div class='add'>+</div><div class='add'>+		ocv-capacity-celsius = &lt;25&gt;;</div><div class='add'>+		ocv-capacity-table-0 = &lt;4330000 100&gt;, &lt;4265000 95&gt;,</div><div class='add'>+			&lt;4208000 90&gt;, &lt;4153000 85&gt;, &lt;4100000 80&gt;, &lt;4049000 75&gt;,</div><div class='add'>+			&lt;4001000 70&gt;, &lt;3962000 65&gt;, &lt;3919000 60&gt;, &lt;3872000 55&gt;,</div><div class='add'>+			&lt;3839000 50&gt;, &lt;3817000 45&gt;, &lt;3798000 40&gt;, &lt;3783000 35&gt;,</div><div class='add'>+			&lt;3767000 30&gt;, &lt;3747000 25&gt;, &lt;3729000 20&gt;, &lt;3709000 16&gt;,</div><div class='add'>+			&lt;3688000 13&gt;, &lt;3681000 11&gt;, &lt;3680000 10&gt;, &lt;3679000 9&gt;,</div><div class='add'>+			&lt;3677000 8&gt;, &lt;3674000 7&gt;, &lt;3666000 6&gt;, &lt;3641000 5&gt;,</div><div class='add'>+			&lt;3597000 4&gt;, &lt;3537000 3&gt;, &lt;3457000 2&gt;, &lt;3336000 1&gt;,</div><div class='add'>+			&lt;3000000 0&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;gpio_keys_default&gt;;</div><div class='ctx'> </div><div class='del'>-			vmmc-supply = &lt;&amp;pm8916_l8&gt;;</div><div class='del'>-			vqmmc-supply = &lt;&amp;pm8916_l5&gt;;</div><div class='add'>+		label = "GPIO Buttons";</div><div class='ctx'> </div><div class='del'>-			pinctrl-names = "default", "sleep";</div><div class='del'>-			pinctrl-0 = &lt;&amp;sdc1_clk_on &amp;sdc1_cmd_on &amp;sdc1_data_on&gt;;</div><div class='del'>-			pinctrl-1 = &lt;&amp;sdc1_clk_off &amp;sdc1_cmd_off &amp;sdc1_data_off&gt;;</div><div class='add'>+		button-volume-up {</div><div class='add'>+			label = "Volume Up";</div><div class='add'>+			gpios = &lt;&amp;tlmm 107 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='ctx'> 		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_ctp: regulator-ctp {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "ctp";</div><div class='add'>+</div><div class='add'>+		regulator-min-microvolt = &lt;2800000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;2800000&gt;;</div><div class='ctx'> </div><div class='del'>-		sdhci@7864000 {</div><div class='del'>-			status = "okay";</div><div class='add'>+		gpio = &lt;&amp;tlmm 17 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;ctp_pwr_en_default&gt;;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-			vmmc-supply = &lt;&amp;pm8916_l11&gt;;</div><div class='del'>-			vqmmc-supply = &lt;&amp;pm8916_l12&gt;;</div><div class='add'>+	flash-led-controller {</div><div class='add'>+		compatible = "sgmicro,sgm3140";</div><div class='add'>+		flash-gpios = &lt;&amp;tlmm 31 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-gpios = &lt;&amp;tlmm 32 GPIO_ACTIVE_HIGH&gt;;</div><div class='ctx'> </div><div class='del'>-			pinctrl-names = "default", "sleep";</div><div class='del'>-			pinctrl-0 = &lt;&amp;sdc2_clk_on &amp;sdc2_cmd_on &amp;sdc2_data_on&gt;;</div><div class='del'>-			pinctrl-1 = &lt;&amp;sdc2_clk_off &amp;sdc2_cmd_off &amp;sdc2_data_off&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;camera_flash_default&gt;;</div><div class='ctx'> </div><div class='del'>-			non-removable;</div><div class='add'>+		flash_led: led {</div><div class='add'>+			function = LED_FUNCTION_FLASH;</div><div class='add'>+			color = &lt;LED_COLOR_ID_WHITE&gt;;</div><div class='add'>+			flash-max-timeout-us = &lt;250000&gt;;</div><div class='ctx'> 		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_i2c1 {</div><div class='add'>+	status = "okay";</div><div class='ctx'> </div><div class='del'>-		serial@78b0000 {</div><div class='del'>-			status = "okay";</div><div class='del'>-			pinctrl-names = "default", "sleep";</div><div class='del'>-			pinctrl-0 = &lt;&amp;blsp1_uart2_default&gt;;</div><div class='del'>-			pinctrl-1 = &lt;&amp;blsp1_uart2_sleep&gt;;</div><div class='add'>+	led-controller@45 {</div><div class='add'>+		compatible = "awinic,aw2013";</div><div class='add'>+		reg = &lt;0x45&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		vcc-supply = &lt;&amp;pm8916_l17&gt;;</div><div class='add'>+		vio-supply = &lt;&amp;pm8916_l6&gt;;</div><div class='add'>+</div><div class='add'>+		led@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			led-max-microamp = &lt;5000&gt;;</div><div class='add'>+			function = LED_FUNCTION_INDICATOR;</div><div class='add'>+			color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		usb@78d9000 {</div><div class='del'>-			status = "okay";</div><div class='del'>-			dr_mode = "peripheral";</div><div class='del'>-			extcon = &lt;&amp;usb_vbus&gt;;</div><div class='del'>-</div><div class='del'>-			hnp-disable;</div><div class='del'>-			srp-disable;</div><div class='del'>-			adp-disable;</div><div class='del'>-</div><div class='del'>-			ulpi {</div><div class='del'>-				phy {</div><div class='del'>-					extcon = &lt;&amp;usb_vbus&gt;;</div><div class='del'>-					v1p8-supply = &lt;&amp;pm8916_l7&gt;;</div><div class='del'>-					v3p3-supply = &lt;&amp;pm8916_l13&gt;;</div><div class='del'>-				};</div><div class='del'>-			};</div><div class='add'>+		led@1 {</div><div class='add'>+			reg = &lt;1&gt;;</div><div class='add'>+			led-max-microamp = &lt;5000&gt;;</div><div class='add'>+			function = LED_FUNCTION_INDICATOR;</div><div class='add'>+			color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		wcnss@a21b000 {</div><div class='del'>-			status = "okay";</div><div class='add'>+		led@2 {</div><div class='add'>+			reg = &lt;2&gt;;</div><div class='add'>+			led-max-microamp = &lt;5000&gt;;</div><div class='add'>+			function = LED_FUNCTION_INDICATOR;</div><div class='add'>+			color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='ctx'> 		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_i2c2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	accelerometer@10 {</div><div class='add'>+		compatible = "bosch,bmc156_accel";</div><div class='add'>+		reg = &lt;0x10&gt;;</div><div class='ctx'> </div><div class='ctx'> 		/*</div><div class='del'>-		 * Attempting to enable these devices causes a "synchronous</div><div class='del'>-		 * external abort". Suspected cause is that the debug power</div><div class='del'>-		 * domain is not enabled by default on this device.</div><div class='del'>-		 * Disable these devices for now to avoid the crash.</div><div class='add'>+		 * For some reason the interrupt line is usually not connected</div><div class='add'>+		 * to the BMC156. However, there are two pads next to the chip</div><div class='add'>+		 * that can be shorted to make it work if needed.</div><div class='ctx'> 		 *</div><div class='del'>-		 * See: https://lore.kernel.org/linux-arm-msm/20190618202623.GA53651@gerhold.net/</div><div class='add'>+		 * interrupt-parent = &lt;&amp;tlmm&gt;;</div><div class='add'>+		 * interrupts = &lt;116 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='ctx'> 		 */</div><div class='del'>-		tpiu@820000 { status = "disabled"; };</div><div class='del'>-		funnel@821000 { status = "disabled"; };</div><div class='del'>-		replicator@824000 { status = "disabled"; };</div><div class='del'>-		etf@825000 { status = "disabled"; };</div><div class='del'>-		etr@826000 { status = "disabled"; };</div><div class='del'>-		funnel@841000 { status = "disabled"; };</div><div class='del'>-		debug@850000 { status = "disabled"; };</div><div class='del'>-		debug@852000 { status = "disabled"; };</div><div class='del'>-		debug@854000 { status = "disabled"; };</div><div class='del'>-		debug@856000 { status = "disabled"; };</div><div class='del'>-		etm@85c000 { status = "disabled"; };</div><div class='del'>-		etm@85d000 { status = "disabled"; };</div><div class='del'>-		etm@85e000 { status = "disabled"; };</div><div class='del'>-		etm@85f000 { status = "disabled"; };</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;accel_int_default&gt;;</div><div class='add'>+</div><div class='add'>+		vdd-supply = &lt;&amp;pm8916_l17&gt;;</div><div class='add'>+		vddio-supply = &lt;&amp;pm8916_l6&gt;;</div><div class='add'>+</div><div class='add'>+		mount-matrix = "0", "1", "0",</div><div class='add'>+			      "-1", "0", "0",</div><div class='add'>+			       "0", "0", "1";</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	// FIXME: Use extcon device provided by charger driver when available</div><div class='del'>-	usb_vbus: usb-vbus {</div><div class='del'>-		compatible = "linux,extcon-usb-gpio";</div><div class='del'>-		vbus-gpio = &lt;&amp;msmgpio 62 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+	magnetometer@12 {</div><div class='add'>+		compatible = "bosch,bmc156_magn";</div><div class='add'>+		reg = &lt;0x12&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-parent = &lt;&amp;tlmm&gt;;</div><div class='add'>+		interrupts = &lt;113 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+</div><div class='ctx'> 		pinctrl-names = "default";</div><div class='del'>-		pinctrl-0 = &lt;&amp;usb_vbus_default&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;magn_int_default&gt;;</div><div class='add'>+</div><div class='add'>+		vdd-supply = &lt;&amp;pm8916_l17&gt;;</div><div class='add'>+		vddio-supply = &lt;&amp;pm8916_l6&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	gpio-keys {</div><div class='del'>-		compatible = "gpio-keys";</div><div class='add'>+	light-sensor@23 {</div><div class='add'>+		compatible = "liteon,ltr559";</div><div class='add'>+		reg = &lt;0x23&gt;;</div><div class='add'>+		proximity-near-level = &lt;75&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-parent = &lt;&amp;tlmm&gt;;</div><div class='add'>+		interrupts = &lt;115 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='ctx'> </div><div class='ctx'> 		pinctrl-names = "default";</div><div class='del'>-		pinctrl-0 = &lt;&amp;gpio_keys_default&gt;;</div><div class='add'>+		pinctrl-0 = &lt;&amp;light_int_default&gt;;</div><div class='ctx'> </div><div class='del'>-		label = "GPIO Buttons";</div><div class='add'>+		vdd-supply = &lt;&amp;pm8916_l17&gt;;</div><div class='add'>+		vddio-supply = &lt;&amp;pm8916_l6&gt;;</div><div class='add'>+	};</div><div class='ctx'> </div><div class='del'>-		volume-up {</div><div class='del'>-			label = "Volume Up";</div><div class='del'>-			gpios = &lt;&amp;msmgpio 107 GPIO_ACTIVE_LOW&gt;;</div><div class='del'>-			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='del'>-		};</div><div class='add'>+	gyroscope@68 {</div><div class='add'>+		compatible = "bosch,bmg160";</div><div class='add'>+		reg = &lt;0x68&gt;;</div><div class='add'>+</div><div class='add'>+		interrupt-parent = &lt;&amp;tlmm&gt;;</div><div class='add'>+		interrupts = &lt;23 IRQ_TYPE_EDGE_RISING&gt;,</div><div class='add'>+			     &lt;22 IRQ_TYPE_EDGE_RISING&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;gyro_int_default&gt;;</div><div class='add'>+</div><div class='add'>+		vdd-supply = &lt;&amp;pm8916_l17&gt;;</div><div class='add'>+		vddio-supply = &lt;&amp;pm8916_l6&gt;;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;msmgpio {</div><div class='del'>-	gpio_keys_default: gpio_keys_default {</div><div class='del'>-		pinmux {</div><div class='del'>-			function = "gpio";</div><div class='del'>-			pins = "gpio107";</div><div class='del'>-		};</div><div class='del'>-		pinconf {</div><div class='del'>-			pins = "gpio107";</div><div class='del'>-			drive-strength = &lt;2&gt;;</div><div class='del'>-			bias-pull-up;</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='add'>+&amp;blsp_i2c5 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	rmi4@20 {</div><div class='add'>+		compatible = "syna,rmi4-i2c";</div><div class='add'>+		reg = &lt;0x20&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='ctx'> </div><div class='del'>-	usb_vbus_default: usb-vbus-default {</div><div class='del'>-		pinmux {</div><div class='del'>-			function = "gpio";</div><div class='del'>-			pins = "gpio62";</div><div class='add'>+		interrupt-parent = &lt;&amp;tlmm&gt;;</div><div class='add'>+		interrupts = &lt;13 IRQ_TYPE_EDGE_FALLING&gt;;</div><div class='add'>+</div><div class='add'>+		vdd-supply = &lt;&amp;reg_ctp&gt;;</div><div class='add'>+		vio-supply = &lt;&amp;pm8916_l6&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;tp_int_default&gt;;</div><div class='add'>+</div><div class='add'>+		syna,startup-delay-ms = &lt;10&gt;;</div><div class='add'>+</div><div class='add'>+		rmi4-f01@1 {</div><div class='add'>+			reg = &lt;0x1&gt;;</div><div class='add'>+			syna,nosleep-mode = &lt;1&gt;; /* Allow sleeping */</div><div class='ctx'> 		};</div><div class='del'>-		pinconf {</div><div class='del'>-			pins = "gpio62";</div><div class='del'>-			bias-pull-up;</div><div class='add'>+</div><div class='add'>+		rmi4-f12@12 {</div><div class='add'>+			reg = &lt;0x12&gt;;</div><div class='add'>+			syna,sensor-type = &lt;1&gt;; /* Touchscreen */</div><div class='ctx'> 		};</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;spmi_bus {</div><div class='del'>-	pm8916@0 {</div><div class='del'>-		pon@800 {</div><div class='del'>-			volume-down {</div><div class='del'>-				compatible = "qcom,pm8941-resin";</div><div class='del'>-				interrupts = &lt;0x0 0x8 1 IRQ_TYPE_EDGE_BOTH&gt;;</div><div class='del'>-				bias-pull-up;</div><div class='del'>-				linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='del'>-			};</div><div class='del'>-		};</div><div class='del'>-	};</div><div class='add'>+&amp;blsp_uart2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;blsp_uart2_console_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;blsp_uart2_console_sleep&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-&amp;smd_rpm_regulators {</div><div class='del'>-	vdd_l1_l2_l3-supply = &lt;&amp;pm8916_s3&gt;;</div><div class='del'>-	vdd_l4_l5_l6-supply = &lt;&amp;pm8916_s4&gt;;</div><div class='del'>-	vdd_l7-supply = &lt;&amp;pm8916_s4&gt;;</div><div class='add'>+&amp;pm8916_bms {</div><div class='add'>+	status = "okay";</div><div class='ctx'> </div><div class='del'>-	s1 {</div><div class='del'>-		regulator-min-microvolt = &lt;500000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;1300000&gt;;</div><div class='del'>-	};</div><div class='add'>+	monitored-battery = &lt;&amp;battery&gt;;</div><div class='add'>+	power-supplies = &lt;&amp;pm8916_charger&gt;;</div><div class='add'>+};</div><div class='ctx'> </div><div class='del'>-	s3 {</div><div class='del'>-		regulator-min-microvolt = &lt;1200000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;1300000&gt;;</div><div class='del'>-	};</div><div class='add'>+&amp;pm8916_charger {</div><div class='add'>+	status = "okay";</div><div class='ctx'> </div><div class='del'>-	s4 {</div><div class='del'>-		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;2100000&gt;;</div><div class='del'>-	};</div><div class='add'>+	monitored-battery = &lt;&amp;battery&gt;;</div><div class='ctx'> </div><div class='del'>-	l1 {</div><div class='del'>-		regulator-min-microvolt = &lt;1225000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;1225000&gt;;</div><div class='del'>-	};</div><div class='add'>+	qcom,fast-charge-safe-current = &lt;900000&gt;;</div><div class='add'>+	qcom,fast-charge-safe-voltage = &lt;4300000&gt;;</div><div class='add'>+};</div><div class='ctx'> </div><div class='del'>-	l2 {</div><div class='del'>-		regulator-min-microvolt = &lt;1200000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;1200000&gt;;</div><div class='del'>-	};</div><div class='add'>+&amp;pm8916_codec {</div><div class='add'>+	qcom,micbias-lvl = &lt;2800&gt;;</div><div class='add'>+	qcom,mbhc-vthreshold-low = &lt;75 150 237 450 500&gt;;</div><div class='add'>+	qcom,mbhc-vthreshold-high = &lt;75 150 237 450 500&gt;;</div><div class='add'>+	qcom,hphl-jack-type-normally-open;</div><div class='add'>+};</div><div class='ctx'> </div><div class='del'>-	l3 {</div><div class='del'>-		regulator-min-microvolt = &lt;500000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;1287500&gt;;</div><div class='del'>-	};</div><div class='add'>+&amp;pm8916_resin {</div><div class='add'>+	status = "okay";</div><div class='add'>+	linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+};</div><div class='ctx'> </div><div class='del'>-	l4 {</div><div class='del'>-		regulator-min-microvolt = &lt;2050000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;2050000&gt;;</div><div class='add'>+&amp;pm8916_rpm_regulators {</div><div class='add'>+	pm8916_l17: l17 {</div><div class='add'>+		regulator-min-microvolt = &lt;2850000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;2850000&gt;;</div><div class='ctx'> 	};</div><div class='add'>+};</div><div class='ctx'> </div><div class='del'>-	l5 {</div><div class='del'>-		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='del'>-	};</div><div class='add'>+&amp;pm8916_vib {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='ctx'> </div><div class='del'>-	l6 {</div><div class='del'>-		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='del'>-	};</div><div class='add'>+&amp;sdhc_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='ctx'> </div><div class='del'>-	l7 {</div><div class='del'>-		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;1800000&gt;;</div><div class='del'>-	};</div><div class='add'>+&amp;sdhc_2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	non-removable;</div><div class='add'>+};</div><div class='ctx'> </div><div class='del'>-	l8 {</div><div class='del'>-		regulator-min-microvolt = &lt;2850000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;2900000&gt;;</div><div class='del'>-	};</div><div class='add'>+&amp;sound {</div><div class='add'>+	audio-routing =</div><div class='add'>+		"AMIC1", "MIC BIAS Internal1",</div><div class='add'>+		"AMIC2", "MIC BIAS Internal2",</div><div class='add'>+		"AMIC3", "MIC BIAS Internal3";</div><div class='add'>+};</div><div class='ctx'> </div><div class='del'>-	l9 {</div><div class='del'>-		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='del'>-	};</div><div class='add'>+&amp;usb {</div><div class='add'>+	status = "okay";</div><div class='add'>+	dr_mode = "peripheral";</div><div class='add'>+	extcon = &lt;&amp;pm8916_charger&gt;;</div><div class='add'>+};</div><div class='ctx'> </div><div class='del'>-	l10 {</div><div class='del'>-		regulator-min-microvolt = &lt;2700000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;2800000&gt;;</div><div class='del'>-	};</div><div class='add'>+&amp;usb_hs_phy {</div><div class='add'>+	extcon = &lt;&amp;pm8916_charger&gt;;</div><div class='add'>+};</div><div class='ctx'> </div><div class='del'>-	l11 {</div><div class='del'>-		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;2950000&gt;;</div><div class='del'>-		regulator-allow-set-load;</div><div class='del'>-		regulator-system-load = &lt;200000&gt;;</div><div class='add'>+&amp;venus {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;venus_mem {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wcnss {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wcnss_iris {</div><div class='add'>+	compatible = "qcom,wcn3620";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wcnss_mem {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tlmm {</div><div class='add'>+	accel_int_default: accel-int-default-state {</div><div class='add'>+		pins = "gpio116";</div><div class='add'>+		function = "gpio";</div><div class='add'>+</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	l12 {</div><div class='del'>-		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;2950000&gt;;</div><div class='add'>+	camera_flash_default: camera-flash-default-state {</div><div class='add'>+		pins = "gpio31", "gpio32";</div><div class='add'>+		function = "gpio";</div><div class='add'>+</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	l13 {</div><div class='del'>-		regulator-min-microvolt = &lt;3075000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;3075000&gt;;</div><div class='add'>+	ctp_pwr_en_default: ctp-pwr-en-default-state {</div><div class='add'>+		pins = "gpio17";</div><div class='add'>+		function = "gpio";</div><div class='add'>+</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	l14 {</div><div class='del'>-		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	gpio_keys_default: gpio-keys-default-state {</div><div class='add'>+		pins = "gpio107";</div><div class='add'>+		function = "gpio";</div><div class='add'>+</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-pull-up;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	l15 {</div><div class='del'>-		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	gyro_int_default: gyro-int-default-state {</div><div class='add'>+		pins = "gpio22", "gpio23";</div><div class='add'>+		function = "gpio";</div><div class='add'>+</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	l16 {</div><div class='del'>-		regulator-min-microvolt = &lt;1800000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+	light_int_default: light-int-default-state {</div><div class='add'>+		pins = "gpio115";</div><div class='add'>+		function = "gpio";</div><div class='add'>+</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	l17 {</div><div class='del'>-		regulator-min-microvolt = &lt;2850000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;2850000&gt;;</div><div class='add'>+	magn_int_default: magn-int-default-state {</div><div class='add'>+		pins = "gpio113";</div><div class='add'>+		function = "gpio";</div><div class='add'>+</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	l18 {</div><div class='del'>-		regulator-min-microvolt = &lt;2700000&gt;;</div><div class='del'>-		regulator-max-microvolt = &lt;2700000&gt;;</div><div class='add'>+	tp_int_default: tp-int-default-state {</div><div class='add'>+		pins = "gpio13";</div><div class='add'>+		function = "gpio";</div><div class='add'>+</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts<br/>new file mode 100644<br/>index 000000000000..93d5ea279cff<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts</a></div><div class='hunk'>@@ -0,0 +1,394 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+</div><div class='add'>+/dts-v1/;</div><div class='add'>+</div><div class='add'>+#include "msm8916-pm8916.dtsi"</div><div class='add'>+#include "msm8916-modem-qdsp6.dtsi"</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/gpio/gpio.h&gt;</div><div class='add'>+#include &lt;dt-bindings/input/input.h&gt;</div><div class='add'>+#include &lt;dt-bindings/leds/common.h&gt;</div><div class='add'>+#include &lt;dt-bindings/pinctrl/qcom,pmic-gpio.h&gt;</div><div class='add'>+</div><div class='add'>+/ {</div><div class='add'>+	model = "BQ Aquaris X5 (Longcheer L8910)";</div><div class='add'>+	compatible = "longcheer,l8910", "qcom,msm8916";</div><div class='add'>+	chassis-type = "handset";</div><div class='add'>+</div><div class='add'>+	aliases {</div><div class='add'>+		mmc0 = &amp;sdhc_1; /* eMMC */</div><div class='add'>+		mmc1 = &amp;sdhc_2; /* SD card */</div><div class='add'>+		serial0 = &amp;blsp_uart2;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	chosen {</div><div class='add'>+		stdout-path = "serial0";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	speaker_amp: audio-amplifier {</div><div class='add'>+		compatible = "awinic,aw8738";</div><div class='add'>+		mode-gpios = &lt;&amp;tlmm 114 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		awinic,mode = &lt;5&gt;;</div><div class='add'>+		sound-name-prefix = "Speaker Amp";</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;spk_ext_pa_default&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	flash-led-controller {</div><div class='add'>+		compatible = "ocs,ocp8110";</div><div class='add'>+		enable-gpios = &lt;&amp;tlmm 49 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		flash-gpios = &lt;&amp;tlmm 119 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;camera_front_flash_default&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		flash_led: led {</div><div class='add'>+			function = LED_FUNCTION_FLASH;</div><div class='add'>+			color = &lt;LED_COLOR_ID_WHITE&gt;;</div><div class='add'>+			flash-max-timeout-us = &lt;250000&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio-keys {</div><div class='add'>+		compatible = "gpio-keys";</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;gpio_keys_default&gt;;</div><div class='add'>+</div><div class='add'>+		label = "GPIO Buttons";</div><div class='add'>+</div><div class='add'>+		button-volume-up {</div><div class='add'>+			label = "Volume Up";</div><div class='add'>+			gpios = &lt;&amp;tlmm 107 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+			linux,code = &lt;KEY_VOLUMEUP&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	leds {</div><div class='add'>+		compatible = "gpio-leds";</div><div class='add'>+</div><div class='add'>+		led-0 {</div><div class='add'>+			gpios = &lt;&amp;tlmm 17 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+			color = &lt;LED_COLOR_ID_WHITE&gt;;</div><div class='add'>+			default-state = "off";</div><div class='add'>+			function = LED_FUNCTION_KBD_BACKLIGHT;</div><div class='add'>+</div><div class='add'>+			pinctrl-names = "default";</div><div class='add'>+			pinctrl-0 = &lt;&amp;button_backlight_default&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	reg_ts_vcca: regulator-vcca-ts {</div><div class='add'>+		compatible = "regulator-fixed";</div><div class='add'>+		regulator-name = "regulator-vcca-ts";</div><div class='add'>+		regulator-min-microvolt = &lt;3300000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;3300000&gt;;</div><div class='add'>+</div><div class='add'>+		gpio = &lt;&amp;tlmm 78 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		enable-active-high;</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;ts_vcca_default&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb_id: usb-id {</div><div class='add'>+		compatible = "linux,extcon-usb-gpio";</div><div class='add'>+		id-gpios = &lt;&amp;tlmm 110 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;usb_id_default&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_i2c2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	led-controller@30 {</div><div class='add'>+		compatible = "kinetic,ktd2026";</div><div class='add'>+		reg = &lt;0x30&gt;;</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		vin-supply = &lt;&amp;pm8916_l17&gt;;</div><div class='add'>+		vio-supply = &lt;&amp;pm8916_l6&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;status_led_default&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		multi-led {</div><div class='add'>+			color = &lt;LED_COLOR_ID_RGB&gt;;</div><div class='add'>+			function = LED_FUNCTION_STATUS;</div><div class='add'>+</div><div class='add'>+			#address-cells = &lt;1&gt;;</div><div class='add'>+			#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+			led@0 {</div><div class='add'>+				reg = &lt;0&gt;;</div><div class='add'>+				color = &lt;LED_COLOR_ID_RED&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			led@1 {</div><div class='add'>+				reg = &lt;1&gt;;</div><div class='add'>+				color = &lt;LED_COLOR_ID_GREEN&gt;;</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			led@2 {</div><div class='add'>+				reg = &lt;2&gt;;</div><div class='add'>+				color = &lt;LED_COLOR_ID_BLUE&gt;;</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	flash-led-controller@53 {</div><div class='add'>+		compatible = "silergy,sy7802";</div><div class='add'>+		reg = &lt;0x53&gt;;</div><div class='add'>+</div><div class='add'>+		enable-gpios = &lt;&amp;tlmm 16 GPIO_ACTIVE_HIGH&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;camera_rear_flash_default&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		#address-cells = &lt;1&gt;;</div><div class='add'>+		#size-cells = &lt;0&gt;;</div><div class='add'>+</div><div class='add'>+		led@0 {</div><div class='add'>+			reg = &lt;0&gt;;</div><div class='add'>+			function = LED_FUNCTION_FLASH;</div><div class='add'>+			color = &lt;LED_COLOR_ID_WHITE&gt;;</div><div class='add'>+			led-sources = &lt;0&gt;, &lt;1&gt;;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_i2c3 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	magnetometer@d {</div><div class='add'>+		compatible = "asahi-kasei,ak09911";</div><div class='add'>+		reg = &lt;0x0d&gt;;</div><div class='add'>+</div><div class='add'>+		vdd-supply = &lt;&amp;pm8916_l17&gt;;</div><div class='add'>+		vid-supply = &lt;&amp;pm8916_l6&gt;;</div><div class='add'>+</div><div class='add'>+		reset-gpios = &lt;&amp;tlmm 111 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+		pinctrl-0 = &lt;&amp;mag_reset_default&gt;;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	imu@68 {</div><div class='add'>+		compatible = "bosch,bmi160";</div><div class='add'>+		reg = &lt;0x68&gt;;</div><div class='add'>+</div><div class='add'>+		vdd-supply = &lt;&amp;pm8916_l17&gt;;</div><div class='add'>+		vddio-supply = &lt;&amp;pm8916_l6&gt;;</div><div class='add'>+</div><div class='add'>+		mount-matrix = "0", "1", "0",</div><div class='add'>+			      "-1", "0", "0",</div><div class='add'>+			       "0", "0", "1";</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_i2c5 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	touchscreen@48 {</div><div class='add'>+		compatible = "himax,hx8527e", "himax,hx852es";</div><div class='add'>+		reg = &lt;0x48&gt;;</div><div class='add'>+</div><div class='add'>+		interrupts-extended = &lt;&amp;tlmm 13 IRQ_TYPE_LEVEL_LOW&gt;;</div><div class='add'>+		reset-gpios = &lt;&amp;tlmm 12 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+		vcca-supply = &lt;&amp;reg_ts_vcca&gt;;</div><div class='add'>+		vccd-supply = &lt;&amp;pm8916_l6&gt;;</div><div class='add'>+</div><div class='add'>+		pinctrl-0 = &lt;&amp;ts_int_reset_default&gt;;</div><div class='add'>+		pinctrl-names = "default";</div><div class='add'>+</div><div class='add'>+		linux,keycodes = &lt;KEY_BACK KEY_HOMEPAGE KEY_APPSELECT&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;blsp_uart2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+	pinctrl-0 = &lt;&amp;blsp_uart2_console_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;blsp_uart2_console_sleep&gt;;</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;mpss_mem {</div><div class='add'>+	reg = &lt;0x0 0x86800000 0x0 0x5000000&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8916_codec {</div><div class='add'>+	qcom,micbias-lvl = &lt;2800&gt;;</div><div class='add'>+	qcom,mbhc-vthreshold-low = &lt;75 100 120 180 500&gt;;</div><div class='add'>+	qcom,mbhc-vthreshold-high = &lt;75 100 120 180 500&gt;;</div><div class='add'>+	qcom,hphl-jack-type-normally-open;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8916_gpios {</div><div class='add'>+	status_led_default: status-led-default-state {</div><div class='add'>+		pins = "gpio3";</div><div class='add'>+		function = PMIC_GPIO_FUNC_NORMAL;</div><div class='add'>+		power-source = &lt;PM8916_GPIO_VPH&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+		output-high;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8916_resin {</div><div class='add'>+	status = "okay";</div><div class='add'>+	linux,code = &lt;KEY_VOLUMEDOWN&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8916_rpm_regulators {</div><div class='add'>+	pm8916_l17: l17 {</div><div class='add'>+		regulator-min-microvolt = &lt;2850000&gt;;</div><div class='add'>+		regulator-max-microvolt = &lt;2850000&gt;;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;pm8916_vib {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sdhc_1 {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sdhc_2 {</div><div class='add'>+	status = "okay";</div><div class='add'>+</div><div class='add'>+	pinctrl-names = "default", "sleep";</div><div class='add'>+	pinctrl-0 = &lt;&amp;sdc2_default &amp;sdc2_cd_default&gt;;</div><div class='add'>+	pinctrl-1 = &lt;&amp;sdc2_sleep &amp;sdc2_cd_default&gt;;</div><div class='add'>+</div><div class='add'>+	cd-gpios = &lt;&amp;tlmm 38 GPIO_ACTIVE_LOW&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;sound {</div><div class='add'>+	/*</div><div class='add'>+	 * Provide widgets/pin-switches to allow enabling speaker separately.</div><div class='add'>+	 * The hardware does not provide a way to disable the output via the</div><div class='add'>+	 * headphone jack when the speaker is enabled.</div><div class='add'>+	 */</div><div class='add'>+	model = "bq-paella";</div><div class='add'>+	widgets =</div><div class='add'>+		"Speaker", "Speaker",</div><div class='add'>+		"Headphone", "Headphones";</div><div class='add'>+	pin-switches = "Speaker";</div><div class='add'>+	audio-routing =</div><div class='add'>+		"Speaker", "Speaker Amp OUT",</div><div class='add'>+		"Speaker Amp IN", "HPH_R",</div><div class='add'>+		"Headphones", "HPH_L",</div><div class='add'>+		"Headphones", "HPH_R",</div><div class='add'>+		"AMIC1", "MIC BIAS External1",</div><div class='add'>+		"AMIC2", "MIC BIAS Internal2",</div><div class='add'>+		"AMIC3", "MIC BIAS External1";</div><div class='add'>+	aux-devs = &lt;&amp;speaker_amp&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb {</div><div class='add'>+	status = "okay";</div><div class='add'>+	extcon = &lt;&amp;usb_id&gt;, &lt;&amp;usb_id&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;usb_hs_phy {</div><div class='add'>+	extcon = &lt;&amp;usb_id&gt;;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;venus {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;venus_mem {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wcnss {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wcnss_iris {</div><div class='add'>+	compatible = "qcom,wcn3620";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;wcnss_mem {</div><div class='add'>+	status = "okay";</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+&amp;tlmm {</div><div class='add'>+	button_backlight_default: button-backlight-default-state {</div><div class='add'>+		pins = "gpio17";</div><div class='add'>+		function = "gpio";</div><div class='add'>+</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	camera_front_flash_default: camera-front-flash-default-state {</div><div class='add'>+		pins = "gpio49", "gpio119";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	camera_rear_flash_default: camera-rear-flash-default-state {</div><div class='add'>+		pins = "gpio9", "gpio16", "gpio117";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	gpio_keys_default: gpio-keys-default-state {</div><div class='add'>+		pins = "gpio107";</div><div class='add'>+		function = "gpio";</div><div class='add'>+</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-pull-up;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	mag_reset_default: mag-reset-default-state {</div><div class='add'>+		pins = "gpio111";</div><div class='add'>+		function = "gpio";</div><div class='add'>+</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sdc2_cd_default: sdc2-cd-default-state {</div><div class='add'>+		pins = "gpio38";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spk_ext_pa_default: spk-ext-pa-default-state {</div><div class='add'>+		pins = "gpio114";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ts_int_reset_default: ts-int-reset-default-state {</div><div class='add'>+		pins = "gpio12", "gpio13";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ts_vcca_default: ts-vcca-default-state {</div><div class='add'>+		pins = "gpio78";</div><div class='add'>+		function = "gpio";</div><div class='add'>+		drive-strength = &lt;2&gt;;</div><div class='add'>+		bias-disable;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	usb_id_default: usb-id-default-state {</div><div class='add'>+		pins = "gpio110";</div><div class='add'>+		function = "gpio";</div><div class='add'>+</div><div class='add'>+		drive-strength = &lt;8&gt;;</div><div class='add'>+		bias-pull-up;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/arch/arm64/boot/dts/qcom/msm8916-modem-qdsp6.dtsi b/arch/arm64/boot/dts/qcom/msm8916-modem-qdsp6.dtsi<br/>new file mode 100644<br/>index 000000000000..75103168c1fc<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git